Cypress Semiconductor 2005 Bluetooth Module User Manual

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Document ID	2789803
Application ID	ViHDh1oDUMDrNbkTJ/xOlA==
Document Description	User Manual
Short Term Confidential	No
Permanent Confidential	No
Supercede	No
Document Type	User Manual
Display Format	Adobe Acrobat PDF - pdf
Filesize	99.3kB (1241255 bits)
Date Submitted	2015-10-22 00:00:00
Date Available	2015-10-22 00:00:00
Creation Date	2015-04-01 18:33:04
Producing Software	Acrobat Distiller 9.5.5 (Windows)
Document Lastmod	2015-09-10 07:57:11
Document Title	CYBLE-022001-00 Bluetooth®Low Energy (BLE) Module
Document Creator	FrameMaker 7.0
Document Author:	Cypress Semiconductor

PRELIMINARY
CYBLE-222005-00
TM
EZ-BLETM PRoC
Module
General Description
The Cypress CYBLE-222005-00 is a fully certified and qualified
module supporting Bluetooth Low Energy (BLE) wireless
communication. The CYBLE-222005-00 is a turnkey solution
and includes onboard crystal oscillators, chip antenna, passive
components, and Cypress PRoC™ BLE.
The CYBLE-222005-00 supports a number of peripheral
functions (ADC, timers, counters, PWM) and serial
communication protocols (I2C, UART, SPI) through its
programmable architecture. The CYBLE-222005-00 includes a
royalty-free BLE stack compatible with Bluetooth 4.1 and
provides up to 16 GPIOs in a small 10 × 10 × 1.80 mm package.
The CYBLE-222005-00 is a complete solution and an ideal fit for
applications requiring BLE wireless connectivity.
Module Description
Functional Capabilities
Up to 15 capacitive sensors for buttons or sliders with
best-in-class signal-to-noise ration (SNR) and liquid tolerance
12-bit, 1-Msps SAR ADC with internal reference,
sample-and-hold (S/H), and channel sequencer
Two serial communication blocks (SCBs) supporting I2C
(master/slave), SPI (master/slave), or UART
Four dedicated 16-bit timer, counter, or PWM blocks
(TCPWMs)
Programmable low voltage detect (LVD) from 1.8 V to 4.5 V
I2S master interface
Drop-in compatible with CYBLE-022001-00 and includes
additional VREF input
Bluetooth Low Energy protocol stack supporting generic
access profile (GAP) Central, Peripheral, Observer, or
Broadcaster roles
Switches between Central and Peripheral roles on-the-go
Bluetooth 4.1 single-mode module
Industrial temperature range: –40 °C to +85 °C
Standard Bluetooth Low Energy profiles and services for
interoperability
32-bit processor (0.9 DMIPS/MHz) with single-cycle 32-bit
multiply, operating at up to 48 MHz
Custom profile and service for specific use cases
256-KB flash memory
32-KB SRAM memory
Watchdog timer with dedicated internal low-speed oscillator
(ILO)
Module size: 10.0 mm ×10.0 mm × 1.80 mm (with shield)
Benefits
The CYBLE-222005-00 module is provided as a turnkey
solution, including all necessary hardware required to use BLE
communication standards.
Proven, qualified, and certified hardware design ready to use
Two-pin SWD for programming
Up to 16 GPIOs configurable as open drain high/low,
pull-up/pull-down, HI-Z analog, HI-Z digial, or strong output
Small footprint (10 × 10 mm × 1.80 mm), perfect for space
constrained applications
Reprogrammable architecture
Certified to FCC, CE MIC, KC, and IC regulations
Bluetooth SIG 4.1 qualified
Fully certified module eliminates the time needed for design,
development and certification processes
Bluetooth SIG qualified with QDID and Declaration ID
Flexible communication protocol support
PSoC Creator™ provides an easy-to-use integrated design
environment (IDE) to configure, develop, program, and test a
BLE application
Power Consumption
TX output power: –18 dbm to +3 dbm
Received signal strength indicator (RSSI) with 1-dB resolution
TX current consumption of 15.6 mA (radio only, 0 dbm)
RX current consumption of 16.4 mA (radio only)
Low power mode support
p Deep Sleep: 1.3 µA with watch crystal oscillator (WCO) on
p Hibernate: 150 nA with SRAM retention
p Stop: 60 nA with XRES wakeup
Cypress Semiconductor Corporation
Document Number: 002-00214 Rev. **
198 Champion Court
San Jose, CA 95134-1709
408-943-2600
Revised September 10, 2015
CYBLE-222005-00
Contents
Overview............................................................................ 3
Module Description...................................................... 3
Pad Connection Interface ................................................ 5
Recommended Host PCB Layout ................................... 6
Power Supply Connections and Recommended External
Components...................................................................... 9
Connection Options..................................................... 9
External Component Recommendation ...................... 9
Critical Components List ........................................... 11
Antenna Design......................................................... 11
Electrical Specification .................................................. 12
GPIO ......................................................................... 14
XRES......................................................................... 15
Digital Peripherals ..................................................... 18
Serial Communication ............................................... 20
Memory ..................................................................... 21
System Resources .................................................... 21
Environmental Specifications ....................................... 24
Environmental Compliance ....................................... 24
RF Certification.......................................................... 24
Environmental Conditions ......................................... 24
ESD and EMI Protection ........................................... 24
Document Number: 002-00214 Rev. **
Regulatory Information ..................................................
FCC ...........................................................................
Industry Canada (IC) Certification .............................
European R&TTE Declaration of Conformity ............
MIC Japan .................................................................
KC Korea...................................................................
Packaging........................................................................
Ordering Information......................................................
Part Numbering Convention ......................................
Document Conventions .............................................
Document History Page .................................................
Sales, Solutions, and Legal Information ......................
Worldwide Sales and Design Support.......................
Products ....................................................................
PSoC® Solutions ......................................................
Cypress Developer Community.................................
Technical Support .....................................................
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Page 2 of 33
CYBLE-222005-00
Overview
Module Description
The CYBLE-222005-00 module is a complete module designed to be soldered to the applications main board.
Module Dimensions and Drawing
Cypress reserves the right to select components (including the appropriate BLE device) from various vendors to achieve the BLE
module functionality. Such selections will still guarantee that all height restrictions of the component area are maintained. Designs
should be held within the physical dimensions shown in the mechanical drawings in Figure 1. All dimensions are in millimeters (mm).
Table 1. Module Design Dimensions
Dimension Item
Specification
Length (X)
10.00 ± 0.15 mm
Width (Y)
10.00 ± 0.15 mm
Length (X)
7.00 ± 0.15 mm
Width (Y)
5.00 ± 0.15 mm
PCB thickness
Height (H)
0.50 ± 0.10 mm
Shield height
Height (H)
1.10 ± 0.10 mm
Maximum component height
Height (H)
1.30 mm typical (chip antenna)
Total module thickness (bottom of module to highest component)
Height (H)
1.80 mm typical
Module dimensions
Antenna location dimensions
See Figure 1 on page 4 for the mechanical reference drawing for CYBLE-222005-00.
Document Number: 002-00214 Rev. **
Page 3 of 33
CYBLE-222005-00
Figure 1. Module Mechanical Drawing
Side View
Top View
Bottom View
Note
1. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on
recommended host PCB layout, see Figure 3 and Figure 4 on page 6.
Document Number: 002-00214 Rev. **
Page 4 of 33
CYBLE-222005-00
Pad Connection Interface
As shown in the bottom view of Figure 1 on page 4, the CYBLE-222005-00 connects to the host board via solder pads on the back
of the module. Table 2 and Figure 2 detail the solder pad length, width, and pitch dimensions of the CYBLE-222005-00 module.
Table 2. Solder Pad Connection Description
Name
SP
Connections Connection Type
22
Solder Pads
Pad Length Dimension
Pad Width Dimension
Pad Pitch
0.71 mm
0.41 mm
0.76 mm
Figure 2. Solder Pad Dimensions
Document Number: 002-00214 Rev. **
Page 5 of 33
CYBLE-222005-00
Recommended Host PCB Layout
Figure 3 details the recommended PCB layout pattern for the host PCB. Dimensions are in mm.
Figure 3. Recommended PCB Layout Pattern for CYBLE-222005-00
Top View (On Host PCB)
To maximize RF performance, the host layout should follow these recommendations:
1. The ideal placement of the Cypress BLE module is in a corner of the host board with the chip antenna located at the far corner.
This placement minimizes the additional recommended keep out area stated in item 2.
2. It is recommended that the area around the Cypress BLE module chip antenna should contain an additional keep out area, where
no grounding or signal trace are contained. The keep out area applies to all layers of the host board. The recommended dimensions
of the host PCB keep out area are shown in Figure 4 (dimensions are in mm).
Figure 4. Recommended Host PCB Keep Out Area Around the CYBLE-222005-00 Chip Antenna
Host PCB Keep Out Area Around Chip Antenna
Document Number: 002-00214 Rev. **
Page 6 of 33
CYBLE-222005-00
Table 3 details the solder pad pitch (center-to-center) for each of the neighboring connections.
Table 3. Module Solder Pad Connection Dimensions
Pad X
Pad Y
Pad Pitch (Pad X - Pad Y)
Comments
Bottom Right Corner
1.64 mm
Distance from bottom right corner to Pad 1 center
0.76 mm
Distance from Pad 1 center to Pad 2 center
0.76 mm
Distance from Pad 2 center to Pad 3 center
0.76 mm
Distance from Pad 3 center to Pad 4 center
0.76 mm
Distance from Pad 4 center to Pad 5 center
0.76 mm
Distance from Pad 5 center to Pad 6 center
Top Right Corner
0.81 mm
Distance from top right corner to Pad 7 center
0.76 mm
Distance from Pad 7 center to Pad 8 center
0.76 mm
Distance from Pad 8 center to Pad 9 center
10
0.76 mm
Distance from Pad 9 center to Pad 10 center
10
11
0.76 mm
Distance from Pad 10 center to Pad 11 center
11
12
0.76 mm
Distance from Pad 11 center to Pad 12 center
12
13
0.76 mm
Distance from Pad 12 center to Pad 13 center
13
14
0.76 mm
Distance from Pad 13 center to Pad 14 center
14
15
0.76 mm
Distance from Pad 14 center to Pad 15 center
15
16
0.76 mm
Distance from Pad 15 center to Pad 16 center
16
17
0.76 mm
Distance from Pad 16 center to Pad 17 center
17
18
0.76 mm
Distance from Pad 17 center to Pad 18 center
Top Left Corner
19
1.50 mm
Distance from top left corner to Pad 19 center
19
20
0.76 mm
Distance from Pad 19 center to Pad 20 center
20
21
0.76 mm
Distance from Pad 20 center to Pad 21 center
21
22
0.76 mm
Distance from Pad 21 center to Pad 22 center
Document Number: 002-00214 Rev. **
Page 7 of 33
CYBLE-222005-00
Table 4 details the solder pad connection definitions and available functions for each connection pad. Table 4 lists the solder pads on
CYBLE-222005-00, the BLE device port-pin, and denotes whether the function shown is available for each solder pad. Each
connection is configurable for a single option shown with a 3.
Table 4. Solder Pad Connection Definitions
Solder Pad
Number
Device
Port Pin
UART
SPI
I2 C
TCPWM[2]
[3]
CapSense
GND
P4.1[4]
3(CTS)
3(MISO)
3(Sensor /
P5.1
P5.0
3(TX)
3(RX)
3(SCLK) 3(SCL)
3(SS) 3(SDA)
3(Sensor)
3(Sensor)
WCO
Out
ECO_OUT
CTANK)
VDDR
Radio Power Supply (1.9V to 5.5V)
VREF[5]
Voltage Reference Input (Optional)
P1.6
P0.7
P0.4
P0.5
11
GND
12
P0.6
13
P1.7
14
VDD
15
XRES
16
P3.5
17
P3.4
18
P3.7
19
P1.4
20
P1.5
21
P3.6
22
P4.0[6]
SWD
GPIO
Ground Connection
10
LCD
3(RTS)
3(CTS)
3(RX)
3(TX)
3(SS)
3(SCLK)
3(MOSI) 3(SDA)
3(MISO) 3(SCL)
3(RTS)
3(CTS)
3(SS)
3(SCLK)
3(Sensor)
3(Sensor)
3(Sensor)
3(Sensor)
3(SWDCLK)
Ground Connection
3(Sensor)
3(Sensor)
3(SWDIO)
Digital Power Supply Input (1.71 to 5.5V)
External Reset Hardware Connection Input
3(TX)
3(RX)
3(CTS)
3(RX)
3(TX)
3(RTS)
3(RTS)
3(SCL)
3(SDA)
3(MISO)
3(MOSI) 3(SDA)
3(MISO) 3(SCL)
3(MOSI)
3(Sensor)
3(Sensor)
3(Sensor)
3(Sensor)
3(Sensor)
3(Sensor)
3(CMOD)
Notes
2. TCPWM stands for timer, counter, and PWM. If supported, the pad can be configured to any of these peripheral functions.
3. The main board needs to connect both GND connections (Pad 1 and Pad 10) on the module to the common ground of the system.
4. When using the capacitive sensing functionality, Pad 2 (P4.1) can be connected to a CTANK capacitor (located off of Cypress BLE Module). CTank should be used
if implementing a shield layer on the capacitive sensor. If used, this capacitor should be placed as close to the module as possible.
5. Analog block functionality is augmented for the user with the external VREF input. The internal bandgap may be bypassed with a 1-µF to 10-µF capacitor.
6. When using the capacitive sensing functionality, Pad 22 (P4.0) must be connected to a CMOD capacitor (located off of Cypress BLE Module). The value of this
capacitor is 2.2 nF and should be placed as close to the module as possible.
7. If the I2S feature is used in the design, the I2S pins shall be dynamically routed to the appropriate available GPIO by PSoC Creator
Document Number: 002-00214 Rev. **
Page 8 of 33
CYBLE-222005-00
Power Supply Connections and Recommended External Components
Power Connections
External Component Recommendation
The CYBLE-222005-00 contains two power supply connections,
VDD and VDDR. The VDD connection supplies power for both
digital and analog device operation. The VDDR connection
supplies power for the device radio.
In either connection scenario, it is recommended to place an
external ferrite bead between the supply and the module
connection. The ferrite bead should be positioned as close as
possible to the module pin connection.
VDD accepts a supply range of 1.8 V to 5.5 V. VDDR accepts a
supply range of 1.9 V to 5.5 V. These specifications can be found
in Table 9. The maximum power supply ripple for both power
connections on the module is 100 mV, as shown in Table 7.
Figure 5 details the recommended host schematic options for a
single supply scenario. The use of one or two ferrite beads will
depend on the specific application and configuration of the
CYBLE-222005-00.
The power supply ramp rate of VDD must be equal to or greater
than that of VDDR.
Figure 6 details the recommended host schematic for an
independent supply scenario.
Connection Options
The recommended ferrite bead value is 330 Ω, 100 MHz. (Murata
BLM21PG331SN1D).
Two connection options are available for any application:
1. Single supply: Connect VDD and VDDR to the same supply.
2. Independent supply: Power VDD and VDDR separately.
Figure 5. Recommended Host Schematic Options for a Single Supply Option
Single Ferrite Bead Option
Two Ferrite Bead Option
Figure 6. Recommended Host Schematic for an Independent Supply Option
Document Number: 002-00214 Rev. **
Page 9 of 33
CYBLE-222005-00
The CYBLE-222005-00 schematic is shown in Figure 7.
Figure 7. CYBLE-222005-00 Schematic Diagram
Document Number: 002-00214 Rev. **
Page 10 of 33
CYBLE-222005-00
Critical Components List
Table 5 details the critical components used in the CYBLE-222005-00 module.
Table 5. Critical Component List
Component
Reference Designator
Silicon
U1
Description
68-pin WLCSP Programmable Radio-on-Chip (PRoC) with BLE
Crystal
Y1
24.000 MHz, 10PF
Crystal
Y2
32.768 kHz, 12.5PF
Antenna
E1
2.4 – 2.5 GHz chip antenna
Antenna Design
Table 6 details the chip antenna used in the CYBLE-222005-00 module. The specifications listed are according to the vendor’s
datasheet. The Cypress module performance improves many of these characteristics. For more information, see Table 8.
Table 6. Chip Antenna Specifications
Item
Description
Chip Antenna Manufacturer
Johanson Technology Inc.
Chip Antenna Part Number
2450AT18B100
Frequency Range
2400 – 2500 MHz
Peak Gain
0.5 dBi typical
Average Gain
-0.5 dBi typical
Return Loss
9.5 dB minimum
Document Number: 002-00214 Rev. **
Page 11 of 33
CYBLE-222005-00
Electrical Specification
Table 7 details the absolute maximum electrical characteristics for the Cypress BLE module.
Table 7. CYBLE-222005-00 Absolute Maximum Ratings
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
VDDD_ABS
Analog, digital, or radio supply relative to VSS
(VSSD = VSSA)
–0.5
–
Absolute maximum
VCCD_ABS
Direct digital core voltage input relative to VSSD
–0.5
–
1.95
Absolute maximum
VDDD_RIPPLE
Maximum power supply ripple for VDD and VDDR
input voltage
–
–
100
mV
VGPIO_ABS
GPIO voltage
–0.5
–
VDD +0.5
Absolute maximum
IGPIO_ABS
Maximum current per GPIO
–25
–
25
mA
Absolute maximum
IGPIO_injection
GPIO injection current: Maximum for VIH > VDD
and minimum for VIL < VSS
–0.5
–
0.5
mA
Absolute maximum current
injected per pin
LU
Pin current for latch up
–200
200
mA
–
3.0V supply
Ripple frequency of 100 kHz
to 750 kHz
Table 8 details the RF characteristics for the Cypress BLE module.
Table 8. CYBLE-222005-00 RF Performance Characteristics
Parameter
Description
RFO
RF output power on ANT
RXS
RF receive sensitivity on ANT
Min
Typ
Max
Units
Details/Conditions
–18
dBm
Configurable via register
settings
–
–91
–
dBm
Guaranteed by design
simulation; High Gain Mode
FR
Module frequency range
2400
–
2480
MHz
–
GP
Peak gain
–
0.5
–
dBi
–
GAvg
Average gain
–
–0.5
–
dBi
–
RL
Return loss
–
–10.5
–
dB
–
Table 9 through Table 47 list the module level electrical characteristics for the CYBLE-222005-00. All specifications are valid for –40
°C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted.
Table 9. CYBLE-222005-00 DC Specifications
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
VDD1
Power supply input voltage
1.8
–
5.5
With regulator enabled
VDD2
Power supply input voltage unregulated
1.71
1.8
1.89
Internally unregulated
supply
VDDR1
Radio supply voltage (radio on)
1.9
–
5.5
–
VDDR2
Radio supply voltage (radio off)
1.71
–
5.5
–
Active Mode, VDD = 1.71 V to 5.5 V
IDD3
Execute from flash; CPU at 3 MHz
–
1.7
–
mA
T = 25 °C,
VDD = 3.3 V
IDD4
Execute from flash; CPU at 3 MHz
–
–
–
mA
T = –40 °C to 85 °C
IDD5
Execute from flash; CPU at 6 MHz
–
2.5
–
mA
T = 25 °C,
VDD = 3.3 V
IDD6
Execute from flash; CPU at 6 MHz
–
–
–
mA
T = –40 °C to 85 °C
IDD7
Execute from flash; CPU at 12 MHz
–
–
mA
T = 25 °C,
VDD = 3.3 V
Document Number: 002-00214 Rev. **
Page 12 of 33
CYBLE-222005-00
Table 9. CYBLE-222005-00 DC Specifications (continued)
Parameter
IDD8
Description
Execute from flash; CPU at 12 MHz
Min
Typ
Max
Units
Details/Conditions
–
–
–
mA
T = –40 °C to 85 °C
IDD9
Execute from flash; CPU at 24 MHz
–
7.1
–
mA
T = 25 °C,
VDD = 3.3 V
IDD10
Execute from flash; CPU at 24 MHz
–
–
–
mA
T = –40 °C to 85 °C
IDD11
Execute from flash; CPU at 48 MHz
–
13.4
–
mA
T = 25 °C,
VDD = 3.3 V
IDD12
Execute from flash; CPU at 48 MHz
–
–
–
mA
T = –40 °C to 85 °C
–
–
–
mA
T = 25 °C, VDD = 3.3 V,
SYSCLK = 3 MHz
–
–
–
mA
T = 25 °C, VDD = 3.3 V,
SYSCLK = 3 MHz
T = 25 °C,
VDD = 3.3 V
Sleep Mode, VDD = 1.8 to 5.5 V
IDD13
IMO on
Sleep Mode, VDD and VDDR = 1.9 to 5.5 V
IDD14
ECO on
Deep-Sleep Mode, VDD = 1.8 to 3.6 V
IDD15
WDT with WCO on
–
1.5
–
µA
IDD16
WDT with WCO on
–
–
–
µA
T = –40 °C to 85 °C
IDD17
WDT with WCO on
–
–
–
µA
T = 25 °C,
VDD = 5 V
IDD18
WDT with WCO on
–
–
–
µA
T = –40 °C to 85 °C
Deep-Sleep Mode, VDD = 1.71 to 1.89 V (Regulator Bypassed)
IDD19
WDT with WCO on
–
–
–
µA
T = 25 °C
IDD20
WDT with WCO on
–
–
–
µA
T = –40 °C to 85 °C
Hibernate Mode, VDD = 1.8 to 3.6 V
IDD27
GPIO and reset active
–
150
–
nA
T = 25 °C,
VDD = 3.3 V
IDD28
GPIO and reset active
–
–
–
nA
T = –40 °C to 85 °C
Hibernate Mode, VDD = 3.6 to 5.5 V
IDD29
GPIO and reset active
–
–
–
nA
T = 25 °C,
VDD = 5 V
IDD30
GPIO and reset active
–
–
–
nA
T = –40 °C to 85 °C
Stop Mode, VDD = 1.8 to 3.6 V
IDD33
Stop-mode current (VDD)
–
20
–
nA
T = 25 °C,
VDD = 3.3 V
IDD34
Stop-mode current (VDDR)
–
40
–-
nA
T = 25 °C,
VDDR = 3.3 V
IDD35
Stop-mode current (VDD)
–
–
–
nA
T = –40 °C to 85 °C
IDD36
Stop-mode current (VDDR)
–
–
–
nA
T = –40 °C to 85 °C,
VDDR = 1.9 V to 3.6 V
Stop Mode, VDD = 3.6 to 5.5 V
IDD37
Stop-mode current (VDD)
–
–
–
nA
T = 25 °C,
VDD = 5 V
IDD38
Stop-mode current (VDDR)
–
–
–
nA
T = 25 °C,
VDDR = 5 V
IDD39
Stop-mode current (VDD)
–
–
–
nA
T = –40 °C to 85 °C
IDD40
Stop-mode current (VDDR)
–
–
–
nA
T = –40 °C to 85 °C
Document Number: 002-00214 Rev. **
Page 13 of 33
CYBLE-222005-00
Table 10. AC Specifications
Parameter
Description
Min
Typ
Max
Units
DC
–
48
MHz
Wakeup from Sleep mode
–
–
µs
Guaranteed by characterization
TDEEPSLEEP
Wakeup from Deep-Sleep mode
–
–
25
µs
24-MHz IMO. Guaranteed by
characterization
THIBERNATE
Wakeup from Hibernate mode
–
–
ms
Guaranteed by characterization
TSTOP
Wakeup from Stop mode
–
–
ms
XRES wakeup
FCPU
CPU frequency
TSLEEP
Details/Conditions
1.71 V ≤ VDD ≤ 5.5 V
GPIO
Table 11. GPIO DC Specifications
Parameter
VIH[8]
VIL
VOH
VOL
Min
Typ
Max
Units
Input voltage HIGH threshold
Description
0.7 × VDD
–
–
Details/Conditions
LVTTL input, VDD < 2.7 V
0.7 × VDD
–
–
–
LVTTL input, VDD >= 2.7 V
2.0
–
–
–
Input voltage LOW threshold
–
–
0.3 × VDD
LVTTL input, VDD < 2.7 V
–
–
0.3× VDD
LVTTL input, VDD >= 2.7 V
–
–
0.8
Output voltage HIGH level
VDD –0.6
–
–
Output voltage HIGH level
VDD –0.5
–
–
IOH = 1 mA at 1.8-V VDD
Output voltage LOW level
–
–
0.6
IOL = 8 mA at 3.3-V VDD
Output voltage LOW level
–
–
0.6
IOL = 4 mA at 1.8-V VDD
Output voltage LOW level
–
–
0.4
IOL = 3 mA at 3.3-V VDD
CMOS input
CMOS input
–
–
IOH = 4 mA at 3.3-V VDD
RPULLUP
Pull-up resistor
3.5
5.6
8.5
kΩ
–
RPULLDOWN
Pull-down resistor
3.5
5.6
8.5
kΩ
–
IIL
Input leakage current (absolute value)
–
–
nA
IIL_CTBM
Input leakage on CTBm input pins
–
–
nA
25 °C, VDD = 3.3 V
–
CIN
Input capacitance
–
–
pF
VHYSTTL
Input hysteresis LVTTL
25
40
–
mV
–
VHYSCMOS
Input hysteresis CMOS
0.05 × VDD
–
–
–
IDIODE
Current through protection diode to
VDD/VSS
–
–
100
µA
–
ITOT_GPIO
Maximum total source or sink chip
current
–
–
200
mA
–
VDD > 2.7 V
Note
8. VIH must not exceed VDD + 0.2 V.
Document Number: 002-00214 Rev. **
Page 14 of 33
CYBLE-222005-00
Table 12. GPIO AC Specifications
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
TRISEF
Rise time in Fast-Strong mode
–
12
ns
3.3-V VDDD, CLOAD = 25 pF
TFALLF
Fall time in Fast-Strong mode
–
12
ns
3.3-V VDDD, CLOAD = 25 pF
TRISES
Rise time in Slow-Strong mode
10
–
60
ns
3.3-V VDDD, CLOAD = 25 pF
TFALLS
Fall time in Slow-Strong mode
10
–
60
ns
3.3-V VDDD, CLOAD = 25 pF
FGPIOUT1
GPIO Fout; 3.3 V ≤ VDD ≤ 5.5 V
Fast-Strong mode
–
–
33
MHz
90/10%, 25 pF load, 60/40 duty
cycle
FGPIOUT2
GPIO Fout; 1.7 V≤ VDD ≤ 3.3 V
Fast-Strong mode
–
–
16.7
MHz
90/10%, 25 pF load, 60/40 duty
cycle
FGPIOUT3
GPIO Fout; 3.3 V ≤ VDD ≤ 5.5 V
Slow-Strong mode
–
–
MHz
90/10%, 25 pF load, 60/40 duty
cycle
FGPIOUT4
GPIO Fout; 1.7 V ≤ VDD ≤ 3.3 V
Slow-Strong mode
–
–
3.5
MHz
90/10%, 25 pF load, 60/40 duty
cycle
FGPIOIN
GPIO input operating frequency
1.71 V ≤ VDD ≤ 5.5 V
–
–
48
MHz
90/10% VIO
Min
Typ
Max
Units
Table 13. OVT GPIO DC Specifications (P5_0 and P5_1 Only)
Parameter
Description
Details/Conditions
IIL
Input leakage (absolute value).
VIH > VDD
–
–
10
µA
25°C, VDD = 0 V, VIH = 3.0 V
VOL
Output voltage LOW level
–
–
0.4
IOL = 20 mA, VDD > 2.9 V
Table 14. OVT GPIO AC Specifications (P5_0 and P5_1 Only)
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
TRISE_OVFS
Output rise time in Fast-Strong mode
1.5
–
12
ns
25-pF load, 10%–90%, VDD=3.3 V
TFALL_OVFS
Output fall time in Fast-Strong mode
1.5
–
12
ns
25-pF load, 10%–90%, VDD=3.3 V
TRISESS
Output rise time in Slow-Strong mode
10
–
60
ns
25 pF load, 10%-90%,
VDD = 3.3 V
TFALLSS
Output fall time in Slow-Strong mode
10
–
60
ns
25 pF load, 10%-90%,
VDD = 3.3 V
FGPIOUT1
GPIO FOUT; 3.3 V ≤ VDD ≤ 5.5 V
Fast-Strong mode
–
–
24
MHz
90/10%, 25 pF load, 60/40 duty
cycle
FGPIOUT2
GPIO FOUT; 1.71 V ≤ VDD ≤ 3.3 V
Fast-Strong mode
–
–
16
MHz
90/10%, 25 pF load, 60/40 duty
cycle
XRES
Table 15. XRES DC Specifications
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
VIH
Input voltage HIGH threshold
0.7 × VDDD
–
–
CMOS input
VIL
Input voltage LOW threshold
–
–
0.3 × VDDD
CMOS input
RPULLUP
Pull-up resistor
3.5
5.6
8.5
kΩ
–
CIN
Input capacitance
–
–
pF
–
VHYSXRES
Input voltage hysteresis
–
100
–
mV
–
IDIODE
Current through protection diode to
VDD/VSS
–
–
100
µA
–
Document Number: 002-00214 Rev. **
Page 15 of 33
CYBLE-222005-00
Table 16. XRES AC Specifications
Parameter
TRESETWIDTH
Description
Min
Typ
Max
Units
Details/Conditions
–
–
µs
–
Reset pulse width
SAR ADC
Table 17. SAR ADC DC Specifications
Parameter
Description
Min
Typ
Max
Units
bits
Details/Conditions
A_RES
Resolution
–
–
12
A_CHNIS_S
Number of channels - single-ended
–
–
8 full-speed
A-CHNKS_D
Number of channels - differential
–
–
Diff inputs use
neighboring I/O
A-MONO
Monotonicity
–
–
–
A_GAINERR
Gain error
–
–
±0.1
With external
reference
A_OFFSET
Input offset voltage
–
–
mV
Measured with 1-V
VREF
A_ISAR
Current consumption
–
–
mA
A_VINS
Input voltage range - single-ended
VSS
–
VDDA
A_VIND
Input voltage range - differential
VSS
–
VDDA
Yes
A_INRES
Input resistance
–
–
2.2
kΩ
A_INCAP
Input capacitance
–
–
10
pF
VREFSAR
Trimmed internal reference to SAR
–1
–
Min
Typ
Max
Units
Percentage of Vbg
(1.024 V)
Table 18. SAR ADC AC Specifications
Parameter
Description
Details/
Conditions
A_PSRR
Power-supply rejection ratio
70
–
–
dB
A_CMRR
Common-mode rejection ratio
66
–
–
dB
A_SAMP
Sample rate
–
–
Msps
806 Ksps for More Part
Numbers devices
Fsarintref
SAR operating speed without external ref.
bypass
–
–
100
Ksps
12-bit resolution
A_SNR
Signal-to-noise ratio (SNR)
65
–
–
dB
A_BW
Input bandwidth without aliasing
–
–
A_SAMP/2
kHz
A_INL
Integral nonlinearity. VDD = 1.71 V to 5.5 V,
1 Msps
–1.7
–
LSB
VREF = 1 V to VDD
A_INL
Integral nonlinearity. VDDD = 1.71 V to 3.6 V,
1 Msps
–1.5
–
1.7
LSB
VREF = 1.71 V to VDD
A_INL
Integral nonlinearity. VDD = 1.71 V to 5.5 V,
500 Ksps
–1.5
–
1.7
LSB
VREF = 1 V to VDD
A_dnl
Differential nonlinearity. VDD = 1.71 V to
5.5 V, 1 Msps
–1
–
2.2
LSB
VREF = 1 V to VDD
A_DNL
Differential nonlinearity. VDD = 1.71 V to
3.6 V, 1 Msps
–1
–
LSB
VREF = 1.71 V to VDD
A_DNL
Differential nonlinearity. VDD = 1.71 V to
5.5 V, 500 Ksps
–1
–
2.2
LSB
VREF = 1 V to VDD
Document Number: 002-00214 Rev. **
Measured at 1-V
reference
FIN = 10 kHz
Page 16 of 33
CYBLE-222005-00
Table 18. SAR ADC AC Specifications (continued)
Parameter
Min
Typ
Max
Units
–
–
–65
dB
Description
Min
Typ
Max
Units
VCSD
Voltage range of operation
1.71
–
5.5
IDAC1
DNL for 8-bit resolution
–1
–
LSB
IDAC1
INL for 8-bit resolution
–3
–
LSB
IDAC2
DNL for 7-bit resolution
–1
–
LSB
IDAC2
INL for 7-bit resolution
–3
–
LSB
SNR
Ratio of counts of finger to noise
–
–
Ratio
IDAC1_CRT1
Output current of IDAC1 (8 bits) in High
range
–
612
–
µA
IDAC1_CRT2
Output current of IDAC1 (8 bits) in Low
range
–
306
–
µA
IDAC2_CRT1
Output current of IDAC2 (7 bits) in High
range
–
305
–
µA
IDAC2_CRT2
Output current of IDAC2 (7 bits) in Low
range
–
153
–
µA
A_THD
Description
Total harmonic distortion
Details/
Conditions
FIN = 10 kHz
CSD
CSD Block Specifications
Parameter
Document Number: 002-00214 Rev. **
Details/
Conditions
Capacitance range of
9 pF to 35 pF, 0.1-pF
sensitivity. Radio is not
operating during the
scan
Page 17 of 33
CYBLE-222005-00
Digital Peripherals
Timer
Table 19. Timer DC Specifications
Parameter
ITIM1
Description
Block current consumption at 3 MHz
Min
–
Typ
–
Max
42
Units
µA
Details/Conditions
16-bit timer
ITIM2
Block current consumption at 12 MHz
–
–
130
µA
16-bit timer
ITIM3
Block current consumption at 48 MHz
–
–
535
µA
16-bit timer
Min
FCLK
Typ
–
Max
48
Units
MHz
Table 20. Timer AC Specifications
Parameter
TTIMFREQ
Description
Operating frequency
Details/Conditions
TCAPWINT
Capture pulse width (internal)
2 × TCLK
–
–
ns
TCAPWEXT
Capture pulse width (external)
2 × TCLK
–
–
ns
TTIMRES
Timer resolution
TCLK
–
–
ns
TTENWIDINT
Enable pulse width (internal)
2 × TCLK
–
–
ns
TTENWIDEXT
Enable pulse width (external)
2 × TCLK
–
–
ns
TTIMRESWINT
Reset pulse width (internal)
2 × TCLK
–
–
ns
TTIMRESEXT
Reset pulse width (external)
2 × TCLK
–
–
ns
16-bit counter
16-bit counter
Counter
Table 21. Counter DC Specifications
Parameter
ICTR1
Description
Block current consumption at 3 MHz
Min
–
Typ
–
Max
42
ICTR2
Block current consumption at 12 MHz
–
–
130
Units
µA
µA
ICTR3
Block current consumption at 48 MHz
–
–
535
µA
Details/Conditions
16-bit counter
Table 22. Counter AC Specifications
Parameter
TCTRFREQ
Description
Operating frequency
Min
FCLK
Typ
–
Max
48
Units
MHz
TCTRPWINT
Capture pulse width (internal)
2 × TCLK
–
–
ns
TCTRPWEXT
Capture pulse width (external)
2 × TCLK
–
–
ns
TCTRES
Counter Resolution
TCLK
–
–
ns
TCENWIDINT
Enable pulse width (internal)
2 × TCLK
–
–
ns
TCENWIDEXT
Enable pulse width (external)
2 × TCLK
–
–
ns
TCTRRESWINT
Reset pulse width (internal)
2 × TCLK
–
–
ns
TCTRRESWEXT
Reset pulse width (external)
2 × TCLK
–
–
ns
Document Number: 002-00214 Rev. **
Details/Conditions
Page 18 of 33
CYBLE-222005-00
Pulse Width Modulation (PWM)
Table 23. PWM DC Specifications
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
IPWM1
Block current consumption at 3 MHz
–
–
42
µA
16-bit PWM
IPWM2
Block current consumption at 12 MHz
–
–
130
µA
16-bit PWM
IPWM3
Block current consumption at 48 MHz
–
–
535
µA
16-bit PWM
Min
Typ
Max
Units
Table 24. PWM AC Specifications
Parameter
Description
TPWMFREQ
Operating frequency
FCLK
–
48
MHz
TPWMPWINT
Pulse width (internal)
2 × TCLK
–
–
ns
TPWMEXT
Pulse width (external)
2 × TCLK
–
–
ns
TPWMKILLINT
Kill pulse width (internal)
2 × TCLK
–
–
ns
TPWMKILLEXT
Kill pulse width (external)
2 × TCLK
–
–
ns
TPWMEINT
Enable pulse width (internal)
2 × TCLK
–
–
ns
TPWMENEXT
Enable pulse width (external)
2 × TCLK
–
–
ns
TPWMRESWINT
Reset pulse width (internal)
2 × TCLK
–
–
ns
TPWMRESWEXT
Reset pulse width (external)
2 × TCLK
–
–
ns
Details/Conditions
LCD Direct Drive
Table 25. LCD Direct Drive DC Specifications
Spec ID
SID228
Parameter
ILCDLOW
Description
Operating current in low-power mode
SID229
CLCDCAP
SID230
LCDOFFSET
LCD capacitance per segment/common
driver
Long-term segment offset
SID231
ILCDOP1
SID232
ILCDOP2
LCD system operating current
VBIAS = 5 V
LCD system operating current
VBIAS = 3.3 V
Min
–
Typ
17.5
Max
–
Units Details/Conditions
µA 16 × 4 small segment
display at 50 Hz
pF
–
500
5000
–
20
–
mV
–
–
mA
–
–
mA
Min
10
Typ
50
Max
150
Units
Hz
32 × 4 segments.
50 Hz at 25 °C
32 × 4 segments
50 Hz at 25 °C
Table 26. LCD Direct Drive AC Specifications
Spec ID
SID233
Parameter
FLCD
Description
LCD frame rate
Document Number: 002-00214 Rev. **
Details/Conditions
Page 19 of 33
CYBLE-222005-00
Serial Communication
Table 27. Fixed I2C DC Specifications
Parameter
Description
II2C1
Block current consumption at 100 kHz
II2C2
Block current consumption at 400 kHz
II2C3
Block current consumption at 1 Mbps
I C enabled in Deep-Sleep mode
II2C4
Min
Typ
Max
Units
Details/Conditions
–
–
50
µA
–
–
–
155
µA
–
–
–
390
µA
–
–
–
1.4
µA
–
Min
Typ
Max
Units
Details/Conditions
–
–
400
kHz
Table 28. Fixed I2C AC Specifications
Parameter
FI2C1
Description
Bit rate
Table 29. Fixed UART DC Specifications
Min
Typ
Max
Units
Details/Conditions
IUART1
Parameter
Block current consumption at 100 kbps
Description
–
–
55
µA
–
IUART2
Block current consumption at 1000 kbps
–
–
312
µA
–
Min
Typ
Max
Units
Details/Conditions
–
–
Mbps
–
Table 30. Fixed UART AC Specifications
Parameter
FUART
Description
Bit rate
Table 31. Fixed SPI DC Specifications
Min
Typ
Max
Units
Details/Conditions
ISPI1
Parameter
Block current consumption at 1 Mbps
Description
–
–
360
µA
–
ISPI2
Block current consumption at 4 Mbps
–
–
560
µA
–
ISPI3
Block current consumption at 8 Mbps
–
–
600
µA
–
Table 32. Fixed SPI AC Specifications
Parameter
FSPI
Description
Min
Typ
Max
Units
Details/Conditions
SPI operating frequency (master; 6x over sampling)
–
–
MHz
–
Table 33. Fixed SPI Master Mode AC Specifications
Min
Typ
Max
Units
Details/Conditions
TDMO
Parameter
MOSI valid after SCLK driving edge
Description
–
–
18
ns
–
TDSI
MISO valid before SCLK capturing edge
Full clock, late MISO sampling used
20
–
–
ns
Full clock, late MISO sampling
THMO
Previous MOSI data hold time
–
–
ns
Referred to Slave capturing edge
Table 34. Fixed SPI Slave Mode AC Specifications
Parameter
Description
Min
Typ
Max
Units
TDMI
MOSI valid before SCLK capturing edge
40
–
–
ns
TDSO
MISO valid after SCLK driving edge
–
–
42 + 3 × TCPU
ns
TDSO_ext
MISO Valid after SCLK driving edge in
external clock mode. VDD < 3.0 V
–
–
50
ns
THSO
Previous MISO data hold time
TSSELSCK
SSEL valid to first SCK valid edge
Document Number: 002-00214 Rev. **
–
–
ns
100
–
–
ns
Page 20 of 33
CYBLE-222005-00
Memory
Table 35. Flash DC Specifications
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
1.71
–
5.5
–
Number of Wait states at 32–48 MHz
–
–
CPU execution from flash
Number of Wait states at 16–32 MHz
–
–
CPU execution from flash
Number of Wait states for 0–16 MHz
–
–
CPU execution from flash
Min
Typ
Max
VPE
Erase and program voltage
TWS48
TWS32
TWS16
Table 36. Flash AC Specifications
Parameter
Description
Units
Details/Conditions
TROWWRITE[9]
TROWERASE[9]
Row (block) write time (erase and program)
–
–
20
ms
Row erase time
–
–
13
ms
–
TROWPROGRAM[9]
TBULKERASE[9]
TDEVPROG[9]
Row program time after erase
–
–
ms
–
Bulk erase time (128 KB)
–
–
35
ms
–
–
–
25
seconds
–
FEND
Flash endurance
100 K
–
–
cycles
–
FRET
Flash retention. TA ≤ 55 °C, 100 K P/E cycles
20
–
–
years
–
FRET2
Flash retention. TA ≤ 85 °C, 10 K P/E cycles
10
–
–
years
–
Min
Typ
Max
Units
Details/Conditions
Total device program time
Row (block) = 128 bytes
System Resources
Power-on-Reset (POR)
Table 37. POR DC Specifications
Parameter
Description
VRISEIPOR
Rising trip voltage
0.80
–
1.45
–
VFALLIPOR
Falling trip voltage
0.75
–
1.40
–
VIPORHYST
Hysteresis
15
–
200
mV
–
Min
Typ
Max
Units
Details/Conditions
–
–
µs
–
Table 38. POR AC Specifications
Parameter
TPPOR_TR
Description
Precision power-on reset (PPOR) response
time in Active and Sleep modes
Table 39. Brown-Out Detect
Description
Min
Typ
Max
Units
Details/Conditions
VFALLPPOR
Parameter
BOD trip voltage in Active and Sleep modes
1.64
–
–
–
VFALLDPSLP
BOD trip voltage in Deep Sleep
1.4
–
–
–
Table 40. Hibernate Reset
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
Note
9. It can take as much as 20 ms to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied on to have
completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make
certain that these are not inadvertently activated.
Document Number: 002-00214 Rev. **
Page 21 of 33
CYBLE-222005-00
Table 40. Hibernate Reset
VHBRTRIP
BOD trip voltage in Hibernate
1.1
–
–
–
VLVI1
Description
LVI_A/D_SEL[3:0] = 0000b
Min
1.71
Typ
1.75
Max
1.79
Units
Details/Conditions
–
VLVI2
LVI_A/D_SEL[3:0] = 0001b
1.76
1.80
1.85
–
VLVI3
LVI_A/D_SEL[3:0] = 0010b
1.85
1.90
1.95
–
VLVI4
LVI_A/D_SEL[3:0] = 0011b
1.95
2.00
2.05
–
VLVI5
LVI_A/D_SEL[3:0] = 0100b
2.05
2.10
2.15
–
VLVI6
LVI_A/D_SEL[3:0] = 0101b
2.15
2.20
2.26
–
VLVI7
LVI_A/D_SEL[3:0] = 0110b
2.24
2.30
2.36
–
VLVI8
LVI_A/D_SEL[3:0] = 0111b
2.34
2.40
2.46
–
VLVI9
LVI_A/D_SEL[3:0] = 1000b
2.44
2.50
2.56
–
VLVI10
LVI_A/D_SEL[3:0] = 1001b
2.54
2.60
2.67
–
VLVI11
LVI_A/D_SEL[3:0] = 1010b
2.63
2.70
2.77
–
VLVI12
LVI_A/D_SEL[3:0] = 1011b
2.73
2.80
2.87
–
VLVI13
LVI_A/D_SEL[3:0] = 1100b
2.83
2.90
2.97
–
VLVI14
LVI_A/D_SEL[3:0] = 1101b
2.93
3.00
3.08
–
VLVI15
LVI_A/D_SEL[3:0] = 1110b
3.12
3.20
3.28
–
VLVI16
LVI_A/D_SEL[3:0] = 1111b
4.39
4.50
4.61
–
LVI_IDD
Block current
–
–
100
µA
–
Min
Typ
Max
Units
Details/Conditions
–
–
µs
–
Min
Typ
Max
Units
Details/Conditions
–
–
14
MHz
SWDCLK ≤ 1/3 CPU clock frequency
Voltage Monitors (LVD)
Table 41. Voltage Monitor DC Specifications
Parameter
Table 42. Voltage Monitor AC Specifications
Parameter
TMONTRIP
Description
Voltage monitor trip time
SWD Interface
Table 43. SWD Interface Specifications
Parameter
Description
F_SWDCLK1
3.3 V ≤ VDD ≤ 5.5 V
F_SWDCLK2
1.71 V ≤ VDD ≤ 3.3 V
–
–
MHz
SWDCLK ≤ 1/3 CPU clock frequency
T_SWDI_SETUP T = 1/f SWDCLK
0.25 × T
–
–
ns
–
T_SWDI_HOLD
0.25 × T
–
–
ns
–
T_SWDO_VALID T = 1/f SWDCLK
T = 1/f SWDCLK
–
–
0.5 × T
ns
–
T_SWDO_HOLD
–
–
ns
–
T = 1/f SWDCLK
Document Number: 002-00214 Rev. **
Page 22 of 33
CYBLE-222005-00
Internal Main Oscillator
Table 44. IMO DC Specifications
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
IIMO1
IMO operating current at 48 MHz
–
–
1000
µA
–
IIMO2
IMO operating current at 24 MHz
–
–
325
µA
–
IIMO3
IMO operating current at 12 MHz
–
–
225
µA
–
IIMO4
IMO operating current at 6 MHz
–
–
180
µA
–
IIMO5
IMO operating current at 3 MHz
–
–
150
µA
–
Table 45. IMO AC Specifications
Min
Typ
Max
Units
FIMOTOL3
Parameter
Frequency variation from 3 to 48 MHz
Description
–
–
±2
Details/Conditions
FIMOTOL3
IMO startup time
–
12
–
µs
–
Min
Typ
Max
Units
Details/Conditions
–
0.3
1.05
µA
–
With API-called calibration
Internal Low-Speed Oscillator
Table 46. ILO DC Specifications
Parameter
IILO2
Description
ILO operating current at 32 kHz
Table 47. ILO AC Specifications
Min
Typ
Max
Units
Details/Conditions
TSTARTILO1
Parameter
ILO startup time
Description
–
–
ms
–
FILOTRIM1
32-kHz trimmed frequency
15
32
50
kHz
–
Table 48. ECO Trim Value Specification
Parameter
ECOTRIM
Description
24-MHz trim value
(firmware configuration)
Document Number: 002-00214 Rev. **
Value
Details/Conditions
0x00003FFA
Optimum trim value that needs to be loaded to register
CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_REG
Page 23 of 33
CYBLE-222005-00
Environmental Specifications
Environmental Compliance
This Cypress BLE module is built in compliance with the Restriction of Hazardous Substances (RoHS) and Halogen Free (HF)
directives. The Cypress module and components used to produce this module are RoHS and HF compliant.
RF Certification
The CYBLE-222005-00 module is certified under the following RF certification standards:
FCC
CE
IC
MIC
KC
Environmental Conditions
Table 49 describes the operating and storage conditions for the Cypress BLE module.
Table 49. Environmental Conditions for CYBLE-222005-00
Description
Operating temperature
Operating humidity (relative, non-condensation)
Thermal ramp rate
Minimum Specification
Maximum Specification
-40 °C
85 °C
5%
85%
–
3 °C/minute
–40 °C
85 °C
Storage temperature and humidity
–
85 ° C at 85%
ESD: Module integrated into system
Components[10]
–
15 kV Air
2.2 kV Contact
Storage temperature
ESD and EMI Protection
Exposed components require special attention to ESD and electromagnetic interference (EMI).
A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosure
near the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground.
Device Handling: Proper ESD protocol must be followed in manufacturing to ensure component reliability.
Note
10. This does not apply to the RF pins (ANT, XTALI, and XTALO). RF pins (ANT, XTALI, and XTALO) are tested for 500-V HBM.
Document Number: 002-00214 Rev. **
Page 24 of 33
CYBLE-222005-00
Regulatory Information
FCC
FCC NOTICE:
The device CYBLE-222005-00, including the antenna 2450AT18B100 from Johanson Technology, complies with Part
15 of the FCC Rules. The device meets the requirements for modular transmitter approval as detailed in FCC public
Notice DA00-1407.transmitter Operation is subject to the following two conditions: (1) This device may not cause
harmful interference, and (2) This device must accept any interference received, including interference that may cause
undesired operation.
CAUTION:
The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly
approved by Cypress Semiconductor may void the user's authority to operate the equipment.
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential
installation. This equipment generates uses and can radiate radio frequency energy and, if not installed and used in
accordance with the instructions,ê may cause harmful interference to radio communications. However, there is no
guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or
television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the
interference by one or more of the following measures:
Reorient or relocate the receiving antenna.
Increase the separation between the equipment and receiver.
Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
Consult the dealer or an experienced radio/TV technician for help
LABELING REQUIREMENTS:
The Original Equipment Manufacturer (OEM) must ensure that FCC labelling requirements are met. This includes a
clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor FCC
identifier for this product as well as the FCC Notice above. The FCC identifier is FCC ID: TBD.
In any case the end product must be labeled exterior with "Contains FCC ID: TBD"
ANTENNA WARNING:
This device is tested with a standard SMA connector and with the antennas listed below. When integrated in the OEMs
product, these fixed antennas require installation preventing end-users from replacing them with non-approved
antennas. Any antenna not in the following table must be tested to comply with FCC Section 15.203 for unique antenna
connectors and Section 15.247 for emissions.
RF EXPOSURE:
To comply with FCC RF Exposure requirements, the Original Equipment Manufacturer (OEM) must ensure to install the
approved antenna in the previous.
The preceding statement must be included as a CAUTION statement in manuals, for products operating with the
approved antennas in Table 6 on page 11, to alert users on FCC RF Exposure compliance. Any notification to the end
user of installation or removal instructions about the integrated radio module is not allowed.
The radiated output power of CYBLE-222005-00 with the chip antenna mounted (FCC ID: TBD) is far below the FCC radio frequency
exposure limits. Nevertheless, use CYBLE-222005-00 in such a manner that minimizes the potential for human contact during normal
operation.
End users may not be provided with the module installation instructions. OEM integrators and end users must be provided with
transmitter operating conditions for satisfying RF exposure compliance.
Document Number: 002-00214 Rev. **
Page 25 of 33
CYBLE-222005-00
Industry Canada (IC) Certification
CYBLE-222005-00 is licensed to meet the regulatory requirements of Industry Canada (IC), License: IC: TBD
Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensure
compliance for SAR and/or RF exposure limits. Users can obtain Canadian information on RF exposure and compliance from
www.ic.gc.ca.
This device has been designed to operate with the antennas listed in Table 6 on page 11, having a maximum gain of 0.5 dBi. Antennas
not included in this list or having a gain greater than 0.5 dBi are strictly prohibited for use with this device. The required antenna
impedance is 50 ohms. The antenna used for this transmitter must not be co-located or operating in conjunction with any other antenna
or transmitter.
IC NOTICE:
The device CYBLE-222005-00 including the antenna 2450AT18B100 from Johanson technology, complies with Canada RSS-GEN
Rules. The device meets the requirements for modular transmitter approval as detailed in RSS-GEN. Operation is
subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must
accept any interference received, including interference that may cause undesired operation.
LABELING REQUIREMENTS:
The Original Equipment Manufacturer (OEM) must ensure that IC labelling requirements are met. This includes a clearly visible label
on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor IC identifier for this product
as well as the IC Notice above. The IC identifier is TBD. In any case, the end product must be labeled in its exterior
with "Contains IC: TBD"
European R&TTE Declaration of Conformity
Hereby, Cypress Semiconductor declares that the Bluetooth module CYBLE-222005-00 complies with the essential requirements and
other relevant provisions of Directive 1999/5/EC. As a result of the conformity assessment procedure described in Annex III of the
Directive 1999/5/EC, the end-customer equipment should be labeled as follows:
All versions of the CYBLE-222005-00 in the specified reference design can be used in the following countries: Austria, Belgium,
Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway.
Document Number: 002-00214 Rev. **
Page 26 of 33
CYBLE-222005-00
MIC Japan
CYBLE-222005-00 is certified as a module with type certification number TBD. End products that integrate CYBLE-222005-00 do not
need additional MIC Japan certification for the end product.
End product can display the certification label of the embedded module.
KC Korea
CYBLE-222005-00 is certified for use in Korea with certificate number TBD.
Document Number: 002-00214 Rev. **
Page 27 of 33
CYBLE-222005-00
Packaging
The CYBLE-222005-00 is offered in tape and reel pacakging. Figure 8 details the tape dimensions used for the CYBLE-222005-00.
Figure 8. CYBLE-222005-00 Tape Dimensions
Figure 9 details the orientation of the CYBLE-222005-00 in the tape as well as the direction for unreeling.
Figure 9. Component Orientation in Tape and Unreeling Direction
Document Number: 002-00214 Rev. **
Page 28 of 33
CYBLE-222005-00
Figure 10 details reel dimensions used for the CYBLE-222005-00.
Figure 10. Reel Dimensions
The CYBLE-222005-00 is designed to be used with pick-and-place equipment in an SMT manufacturing environment. The
center-of-mass for the CYBLE-222005-00 is detailed in Figure 11.
Figure 11. CYBLE-222005-00 Center of Mass
Document Number: 002-00214 Rev. **
Page 29 of 33
CYBLE-222005-00
Ordering Information
The CYBLE-222005-00 part number and features are listed in the following table.
Part Number
CPU
Speed
(MHz)
Flash
Size
(KB)
CapSense
SCB
TCPWM
12-Bit
SAR
ADC
I2S
LCD
Package
Packing
48
256
Yes
1 Msps
Yes
Yes
22-SMT
Tape and
Reel
CYBLE-222005-00
Part Numbering Convention
The part numbers are of the form CYBLE-ABCDEF-GH where the fields are defined as follows.
For additional information and a complete list of Cypress Semiconductor BLE products, contact your local Cypress sales
representative. To locate the nearest Cypress office, visit our website.
U.S. Cypress Headquarters Address
U.S. Cypress Headquarter Contact Info
Cypress website address
Document Number: 002-00214 Rev. **
198 Champion Court, San Jose, CA 95134
(408) 943-2600
http://www.cypress.com
Page 30 of 33
CYBLE-222005-00
Acronyms
Acronym
Description
BLE
Bluetooth Low Energy
Bluetooth SIG
Bluetooth Special Interest Group
CE
European Conformity
CSA
Canadian Standards Association
EMI
electromagnetic interference
ESD
electrostatic discharge
FCC
Federal Communications Commission
GPIO
general-purpose input/output
IC
Industry Canada
IDE
integrated design environment
KC
Korea Certification
MIC
Ministry of Internal Affairs and Communications (Japan)
PCB
printed circuit board
RX
receive
QDID
qualification design ID
SMT
surface-mount technology; a method for producing electronic circuitry in which the components are placed
directly onto the surface of PCBs
TCPWM
timer, counter, pulse width modulator (PWM)
TUV
Germany: Technischer Überwachungs-Verein (Technical Inspection Association)
TX
transmit
Document Conventions
Units of Measure
Symbol
Unit of Measure
°C
degree Celsius
kV
kilovolt
mA
milliamperes
mm
millimeters
mV
millivolt
µA
microamperes
µm
micrometers
MHz
megahertz
GHz
gigahertz
volt
Document Number: 002-00214 Rev. **
Page 31 of 33
CYBLE-222005-00
Document History Page
Document Title: CYBLE-222005-00 Bluetooth® Low Energy (BLE) Module
Document Number: 002-00214
Revision
ECN
Orig. of
Change
**
PRELIMINARY
DSO
Submission
Date
Description of Change
09/10/2015 Preliminary datasheet for CYBLE-222005-00 module.
Document Number: 002-00214 Rev. **
Page 32 of 33
CYBLE-222005-00
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
Memory
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/memory
PSoC
Touch Sensing
cypress.com/go/psoc
cypress.com/go/touch
USB Controllers
Wireless/RF
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 002-00214 Rev. **
Revised September 10, 2015
All products and company names mentioned in this document may be the trademarks of their respective holders.
Page 33 of 33

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