1975_RCA_Linear_IC_Application_Notes 1975 RCA Linear IC Application Notes

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LINEAR Integrated Circuits
Application Notes

A New Approach To Data Service
1975 RCA Solid State OAT ABOOKS
Seven textbook-size volumes covering all current commercial
RCA solid-state devices (through January 1, 1975)
Linear Integrated Circuits and DMOS Devices
(Data only) .............................. SSD-201C
Linear Integrated Circuits and DMOS Devi'ces
(Application Notes only) ....................SSD-202C
COS/MOS Digital Integrated Circuits ...........SSD-203C
Power Transistors .......................... SSD-204C
RF /Microwave Devices ...................... SSD-205C
Thyristors, Rectifiers, and Diacs ..............SSD-206C
High-Reliability Devices ..................... SSD-207C
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Availabe FREE to all DATABOOK users.
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total data service. To qualify for Newsletter mailing,
use the form on page 4 (unless you received your
DATABOOK directly from RCA). You must qualify

annually since a new mailing list is started for e
configurations. 2 These circuits are not widely used
in vhf applications, however, because their gain is
low at high frequencies.

oUTPUT

RL~50n

33._
RFe

aKIl
IOOOpF

I

,,"S

1000"

1)

-14V

INPUT

L1 = tN~n~'j,'~~~ ~:p~t~:el
L2

101

0.82,."

Voo
+16V

:J.~6 inch in dia.,

=3-1/2 turns of No.20 wire, 3/8 inch in dia.,
1/2 inch long

'" Leadless disc capacitor

Fig.3 - 200-MHz common-source amplifier.

Ibl

FigA illustrates the effect of the leakage resistances RL 1 and RL2 when the insulated gate is floating. When these resistances (~1014 ohms) are approximately equal, they form a voltage divider which biases
the insulated gate at +Voo/2. This value of bias
voltage m8JI exceed the maximum rating for positive
gate voltage and, in addition, may cause an excessive
flow of drain current.

RLI,f\.2 • LEAUGE RESISTANCES

leI

Fig.2 .. Bias methods lor common-source MOS transistor
stages: (a) fixed bias; (b) source-resistor bios;
(c) constant-current bios.

Fig.3 shows a 2OO-MHz common-source amplifier
used to measure the rf power gain of the MOS transistor_ This amplifier uses amadified form of the constantcurrent biasing arrangement shown in Fig.2(c}. With
this modified biasing arrangement, both the insulated
gate and the case of the MOS transistor are operated
at dc ground potential. The insulated gate should
always have a dc path to ground even if the path is
through a multimegohm resistor. If the gate is allowed
to float, the resultant dc bias conditions may be unJRdictable and possibly harmful.

Fig.4 - Bios conditions 'or on MOS transistor
when the insulated gate is 1I00ting.

The cascade configuration represents a useful
variation of common-source circuit. In this configuration, a common-source-cormected MOS transistor is
used in the lower section of the cascade, and a commongate-connected MOStransistor is used in the upper section. Fig.5 shows the use of MOS transistors in a 200MHz cascode amplifier. This circuit normally requires
a negative voltage on the gate of Qlo a positive voltage
on the gate of Q2, and approximately equal drain-tosource voltages for each transistor. Although the gate
of Q2 may require a positive voltage of 5 to 10 volts,
the net gate-to-source voltsge for this transistor should
be approximately 0 to -1 volt.

15

AN·3193 " - - - - - - - - - - - - - - - - - - - - - - - - - - - o.9-7pF

dissipation of 30 milliwatts, for example, the 3N128
typically provides a power gain of 17.3 dB and a noise
figure of 3.9 dB when operated at 15 volts and 2,milliamperes. At the same dissipation level, however, the
power gain is reduced to 14.6 dB and the noise figure
is increased to 4.7 dB when the 3N128 is operated at 6
volts and 5 milliamperes. Fig.6 shows the variations
in power gain and noise figure of the 3N 128 as functions of the drain current and voltage.
SUBSTRATE AC GROUNDED
AT DC GATE POTENTIAL
VO"IS V

18

/

16

Selection of Operating Point

The 3NI28 provides maximum rf power gain at a
drain-to-source voltage Vns of approximately 20 volts
and a drain current In of about 5 milliamperes. The
transistor also exhibits a minimum noise figure at a
Vns of 20 volts for a drain current of about 2 milliamperes. The difference in the noise figures obtained
at 2 milliamperes and at 5 milliamperes, however, is
very small (usually between 0 and 0.2 dB) and generally
is not a significant factor in the selection of the operating point. Although a Vns of 20 volts represents the
optimum value for the 3NI28 in terms of both rf power
gain and noise figW,e, this' value is also the maximum
VOS rating for the transistor. Greater long-term reliability is achieved, therefore, by operation of the 3NI28
at a Vos of 12 to 15 volts rather than at 20 volts.
For a Vos of 15 volts and an 10 of 5 milliamperes,
the 3N128 typically provides a power gain of 18 dB and
a noise figure of 4 dB at 200 MHz. Operation of the
. 3NI28 at considerably lower drain currents, such as
those normally employed ill bnttcry-pmvered equipment,
does not seriously affect system performance. For
example, when the transistor is operated at a Vns of
15 volts and an 10 of only 1 milliampere, the power gain
and noise figure at 200 MHz are typically 15.5 dB and
4.5 dB, respectively. Because the MOS transistor is a
voltage-controlled device, -its performance for a given
power dissipation can often ,be improved by operation
at high voltage and low current levels. At a power

16

POWER GAIN

I

Fig.S. 200·MHz,cascocle amplifier.

The operating point selected determines the power
gain, noise figure, power dissipation, and, where applicable, battery life. In many applications, a compromise
between gain and available supply voltages or battery
lifetime is necessary. Knowledge of the variation in
gain and noise figure as functions of voltage and current ,is essential, therefore, before an operating point
can be selected.

.,,---

.

r\

12

6!l:

...I

NOISE FIGURE

!!i

4~
~

~
100

4

10

6

DRAIN CURRENT -

20

2

rnA

SUBSTRATE AC GROUNDED
AT OC GATE POTENTIAL
10"5 rnA

8

/

'"I'6
z
g

/

a:

~I 4
2

10 0

l.-~GAIN

•

~
,4

NOISE FIGURE

8

12

DRAIN VOLTAGE -

16

2
20

V

Fig.6 • Power gain, ancl noise figure of the RCA 3NJ28
at 200 MHz as functions of clrain current ancl voltage.
A gate voltage VG of between -0.5 and -2 volts is
normally required to bias a 3N128 for operation at a '
drain'volLuge Vn oi 15 volts and a drain current in of
5 milliamperes. If a fixed-bias circuit, as shown in
Fig.2(a), is used, the value of the gate voltage must'
be adjust.able to compensate for variations among individual transistors. For the source-resistance bias circuit shown in Fig.2(b) the value of the biasing resistor
should be 200 ohms (5 mA x 200 ohms = '1 volt>. The
source-resistance circuit will limit the variations, in
current among the different transistors to approximately

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - AN-3193
50 per cent. With the constant-current bias circuit
shown in Fig.2(c), variations in current from one transistor to another can easily be limited to less than
10 per cent. Regardless of the bias circuit or the bias
point selected, there is no danger of thermal runaway
with the 3Nl28 because this transistor has a negative
temperature coefficient at the zero-gate-bias point. In
the selection of the bias circuit for an MOS transistor
stage in which automatic gain control is employed, consideration should be given to the following principle:
The more restrictive the tolerance imposed on quiescent
operating-point current, the more difficult automatic
gain control of the stage becomes because the selfcompensating action of the constant-current bias circuit
also resists current changes that result from the agc
action.
AGC Methods

When it is necessary to employ age in an MOS
transistor stage, either of two methods may be used to
reduce transistor gain. In one method, referred to as
reverse agc, the reduction in gain is accomplished by
an increase in negative gate bias. In the other method,
the gain is decreased by reduction of the drain-tosource voltage_
In the reverse agc method, the application of higher
negative voltage to the gate reduces the drain current
and the transconductance of the transistor. The low
feedthrough capacitance of the 3N128 (typically about
0.13 picofarad) usually permits more than 30 dB of gain
reduction at frequencies up to 200 MHz. Substantially
greater gain reduction can be achieved at lower frequencies or in neutralized amplifier circuits.
Gain reduction achieved by the decrease of drainto-source voltage is usually controlled by a variable
impedance in series, or in shunt, with the MOS transistor. The variable impedance may be another MOS
transistor or a bipolar transistor. A major disadvantage
of this method is that the MOS feedback capacitance
rises by a factor of 4 or 6 times as VD approaches
zero. This increase in capacitance reduces the agc
range obtainable and decreases the effectiveness of
a fixed neutralization network. In addition, the output
impedance of the 3N 128 decrease s with a reduction in
the drain voltage.
In the cascode circuit, agc is accomplished most
effectively by application of a negative voltage to the
gate of the upper (common-gate) section. A wide agc
range can be obtained in this circuit. Gain reductions
greater than 45 dB at 200 MHz or 65 dB at 60 MHz are
realizable in an unneutralized cascode circuit.

RF Considerations
One of the prime advantage s of the 3N 128 MOS
transistor over bipolar transistors is its superior cross-

modulation, intermodulation, and modulation distortion
performance. The 3N128 has considerably lower feedback capacitance than junction-gate field-effect transistors. In addition, the 3N128 maintains a high input
resistance at frequencies well into the vhf range (the
real part of the input admittmlCc, Rc(y 11) = 0.15 mmho
at 100 MHz).
At maximum gain, the cross-modulation distortion
of the 3N128 is approximately one-tenth that of most
bipolar transistors, or roughly comparable to the crossmodulation performance of vacuum tubes (at 200 MHz,
an interfering signal of approximately 80 millivolts is
required to produce cross-modulation distortion of 1 per
cent>. However, cross-modul ation susceptibility changes
as the gain of the stagc"is changed. For a single
3Nl28, the cross-modulation distortion increases when
reverse agc is applied; the distortion is also increased,
but to a lesser extent, if agc action is achieved by reduction of the drain-to-source voltage. A deterioration
in cross-modulation performance at high attenuation
results from the fact that the MOS triode is a sharpcutoff device; as a result, large non-linearities occur
near "pinch-off." Beyond "pinch-off," the transadmittance depends primarily upon the capacitive feedthrough, which does not have large third-order nonlinearities. Cross-modulation performance at the extreme limits of attenuation, therefore, is very good. 1
In cascode stages, the effect of reverse agc on crossmodulation distortion is reduced when the agc is applied
to the gate of the common-gate stage; application of
reverse bias to the gate of the common-source stage
results in cross-modulation performance similar to
that of a single triode-connected stage. Figs.7 and 8
show the variation in cross-modulation susceptibility
as a function of agc_ The test circuits used to measure
cross-modulation distortion of .MOS transistors are
shown in Fig.9.
INITIAL BIAS CONDITIONS
TRIODE~ YO -15 V, ID·~mA
CASCODE: VO-20 V. IO-IOmA

f OES ·200 MHz
'INT- 150 MHz

UNTUNED INPUT

0

0

~A~I~E1J.l
\
J .I JJ CASCODE ill'....
(UNNEUTRALIZED)

1\

TRIODE (UNNEUTRALIZEDl

0

0

K

10

o

'=

.p: :~

"-;--..
10

~V

~
50

/

V

p:-

.00

100

INTERFERING SIGNAL -

mV

Fig.7. Cross.moclulation distortion as a Function
of the attenuation produced

by reverse age.

17

AN·3193 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - FREQIEMCY-zoo...,
==::vr

NTIAL .... CCNDITIONS

DESIRED

VOS-15V

FREGUENCY - II011H1

ro-5mA

,

II

I
I!!

~

!C

(.

.. ..~

-

,.)

lR\OIIE·COIIIIECTED

,./'

'~_I-

~

IllNNEUTRALIZEQ

I'\-..
100

1000

~SIGIW.-'"

Fig.8 • Cross.modulation distortion as a function
.·f the attenuation produced when agc is accom·
p lished by a reduction of drain·to·source yoltage.

The test circuit shown in Fig. 10 is used to measure
the intermodulation distortion of MOS transistors. In
such measurements, the receiver is tuned to 150 MHz.
The MOS is then inserted, and bias voltages are applied. When no signals sre applied . The capacitance
bridge becomes more apparent when the circuit is redrawn as shown in Fig.1Ub). The condition for neutral-

where Re means "the real part of."
All MOS transistors have a small, but measurable,
feedback component (y 12); it is possible, therefore,
that some of them will oscillate under certain circuit
conditions. This possibility may be checked by use
of methods given by Linvill 2•4 and by Stem. 3,4 If the
transistor is unconditionally stable for any combination
of passive source and load admittances, then Linvill's
critical stability factor C, as determined from the following equation, is less than 111:
IY21 Y121
C=.
2Re{Yll )Re(Y22)- Re{Y21Y12)

rn

* Conjugate match means that the transistor input and the

generator and the transistor output and load are matched
resistively and that all reactance is tuned out.

Fig.11 - Capacitance-brielge nelltralization circllit:
(a) actllal circllit configllration; (b) circllit reelrawn
to emphasize capacitance-brielge network.

19

AN-3193---------------------------------------------------------ization is that if
in- This condition implies the
following relationship:
vd -Vn or Cfvd = -Cn vn
jXf = jXn'

(4)

The voltage vn is defined by the following equation:
v

n

=(~)jX
=~ ~LCI
Vd ~ __
1_ _
Vd
VX +jX
I
+1 jwCI -w 2LCI +1
L

the generator admittance y g and the real part of the
transistor input admittance must appear to be equal_
Because the generator admittance yg is 20 mmhos and
the real part of the input admittance Re (yu) is 0.45
mmho, the coupling transformer must provide a transformation ratio of 44 to obtain tbe desired impedance
match.
The turns ratio required is determined as
follows:

"(5)

1

IWCI
If this relationship for vn is substituted in Eq.C4l, the
following result is obtained:
CrVd = -cn ( 2Vd
), or Cn = -CC<-w 2LCI +1>
.
-WLCI+1

(6)

At resonance, the equation for the neutralization capacitance Cn may be rewritten as follows:
Cn = -cr[

~-~;)WCI +1] = Cr(~> 1)

(7)

If CI» C2, Eq.(7) may be rewritten as follows:
Cn

~ Cr (~~)

(8)

The other common method of neutralization is the
transformer-coupled method shown in Fig.12. Again,
the condition for neutralization is that if = in. The
requirements for this condition are expressed by the
following equation:

Experimentally, a toms ratio of 4 was found to be approximately the optimum value. This difference results,
in part, from the fact that the parallel resistance of
the tank coil was not considered in the calculation.
At the output of the ~z amplifier, the load is also
50 ohms. Because the dc drain voltage must be blocked
from the load, a series matching capacitor was selected
which performs both dc blocking and resistive matching
simultaneously.
In the actualload-circuit nehvork shown in Fig.13( a),
the value of capacitor C s must be chosen so that the
load admittance, YL = 20 millimhos, is apparently equal
to the real part of the transistor output admittance,
Re>
Rs , then Cp ~ Cs . Therefore, a 3-picofarad capacitance
appears in paranel with the l.4-picofarad capacitance
of the MOS transistor. A small 1-to-9-picofarad variable
air capacitor was selected for the tank tuning capacitor
to compensate for variations among transistors. For a
nominal value of 2 picofarads for the air capacitor, the
total output capacitance is 6.4 picofarads. The inductance required to resonate with 6.4 picofarads at 200
MHz is 0.1 microhenry. When the total output capacitance is known, the required neutralization capacitor
can be calculated. If Cl is arbitrarily selected as 33
picofarads, the neutralization is determined from Eq.(S),

as follows:

(E..) = 1.0 pF

Cn ~ cr(Cl) = 0.2
C2
6.4

The optimum value for the neutralization capacitor
was determined experimentally by use of a small
 Capacitive bridge neutralization is used to
achieve the maximum allowable stage gain of 20 dB
for the particular 3N 128 used.
The input coil of the mixer stage is designed to
permit a conjugate match with the transistor input
admittance. The input admittance Yll of the 3N128
at 200 MHz is approximately 0.45 + j 7.2 millimhos.
Therefore, an admittance of Y11* (=0.45 - j 7.2 milliaool

3O-MHz
OUTPUT

05-3

4T

... 31S'D
TAP

5100

AT1T
2000

Fig.2 - VHF receiver "'ron' end" using the 3H128 in all stages.
• Design information for vhf MOS amplifiers is given in RCA Application Note AN-3193:
"Application Considerations for the RCA-3Nl28 VHF MOS Field-oEffect Transistor." by F.M. Carlson, August 1966.

23

AN-3341
mhos} should be presented to the mixer input_ A conjugate match is not used at the output because it is
desirable to load the input of the following (if) stage
for stability. Therefore, a step-down transformer is
used. {A conjugate match would require use of a stepup transformer because g11 > g22 at 30 MHz.}
The local oscillator is coupled into the insulated
gate of the mixer by means of an ungrounded 34O-degree
loop placed around the input tank coil at its highimpedance end. A small coupling capacitor could also
be used for this purpose. Local-oscillator. amplitude
is approximately 1.4 volts rms into the coupling loop.
Power gain of the mixer stage is 16 dB. Fig.3 shows
the conversion gain of the mixer as a function of localoscillator amplitude. A lower oscillator level than
1.1 volts would probably be desirable if spurious output
frequencies were found to be troublesome.
FREQUENCY·200 MHz

~20

I

z

z
0

~>

/'

0

Z

8-10
-20

/

V

--- -

I
1500
1000
1500
LOCAL OSCILLATOR AMPLlTUOE-mV

2000

Fig.3 - Conversion gain of the mixer stage in Fig.2
as a function of local-oscillator omplituc/e.

A 510-0hm source resistor is used in the mixer
stage to provide a drain current of 4 milliamperes.
{This value is larger than would normally be expected
for a drain current of this level because the gate is
subjected to large signal excursions by the local
oscillator.}
The maximum available gain (MAG) of the 3Nl28
at 30 MHz in a conjugately matched circuit {with Y12

24

assumed to be approximately zero} may be computed
from the y-parameters for the device, as follows:
IY211 2
17.212
MAG =
= 3610 = 35.6 dB
4 g11 g22 4
When the resistance between the drain and source terminals is low (100 to 300 ohms), an MOS transistor is
said to be ON; the drain-to-source channel resistance is
then design.ated as rds(ON). This ON condition correspilni!s to the closed-switch condition in the circuits
of Fig.1_

(a) SUBSTRATE CONNECTED

TO SOURCE

SUBSTRATE CONNECTED TO SOURCE
AMBIENT TEMP. • 25-C

.. 2'01--,---,--,---:-=r::-i
E

~1501---r--1---r-1~~7'-+-~
!:!
IZ

(bl SUBSTRATE
FLOATING

~ 501---r--1---h~~~~-+-~

B

o~~~=-__~~~~~~===¥==~
~-501---r-~F-~~--1---+-~
~

E
a:

-1'01---r7'-H-1I'-+--r--1---+-~

a:

::>
u

z

;;
~

tel SUBSTRATE CONNECTED
TO DRAIN

DRAIN-TO-SOURCE VOLTAGE (Vosl-mV

Fig.3 - Low-level Jrain current as. a lundion 01 Jrain-tosource voltage in an n-channel Jep/etion-type· MOS
transistor with substrate connected to source.
DRAIN-TO-SOURCE VOLTAGE eVDs J-2V/DIV.
(o.b,c'-I ,VOLT PER.STEPIORIGlN_ No significant connected to the source. However, if the incoming

26

-------------------------------------------------------------AN-~52
signal to be chopped exceeds -0.3 volt, the substrate
must be "floated", connected to the drain, or biased
negatively so that the source-to-substrate and drainto-substrate voltages never exceed -0.3 volt. If this

state conditions in an MOS shunt chopper. For the ON
condition, the output voltage EO is given by

(1)

OUTPUT

In Eq.(1), it is assumed that the gate leakage resistance
RG is much larger than the drain-to-source resistance
rds. If the load resistance RL is also much larger than
rds; Eq.(1) can be simplified as follows:
(Q I SHUNT CHOPPER

Eo • Es

[~J
Rs + rda

(2)

OUTPUT

VG. OD-....JIIVIr-.....

RS

"G

A,

"V\I" GATING SIGNAL
NOTE: ALTHOUGH RESISTANCE RG IS ACTUALLY
DISTRIBUTED ALONG THE LENGTH OF rds,
CONNECTION SHOWN ASSURES A WORSTCASE ANALYSIS.

(b) SERIES CHOPPER

Fig.S - Steady-state equivalent circuit 01 MOS
shunt chopper.
OUTPUT

For EO to approach zero, it is necessary that the source
resistance
be much greater than rds. The value of
EO is then given by

RS

as

EO • Es (rd/RS)

(c I

SERIES - SHUNT CHOPPER

A typical value for RS and RL in an MOS shunt chopper
is 0.1 megohm. A typical value of rds(ON) for the 40460
transistor is 90 ohms. If these values are substituted
in Eq.(3) and the signal voltage ES is assumed to be
1 millivolt, EO is calculated as follows:

Fig.4 - Basic MOS chopper circuits.

value is exceeded, the substrate, which forms two p-n
junctions with the drain and the source, becomes forward-bi ased and the resulting flow of diode current
shunts the incoming signal to ground.

(3)

EO

= 10-3 (90110 5 ) = 0.9 microvolt

1n the ON condition, therefore, the dc error voltage is

less than 0.1 per cent forthe values used, and is directly
proportional to the input sigoa!.
For the OFF condition, the steady-state output
voltage EO is given by

Steady-State Conditions

Ideally, when an MOS transistor in a shunt chopper
circuit is ON, the output voltage of the circuit should
be zero. Because the drain-1o-source resistance rds
is some finite value, however, the output cannot reach
true. zero. Fig:5 shows an equivalent circuit for steady-

Eo

=

Es [

r:r:B::'L]
Rs

+---r dB + RL

27

AN-~52----------------------~---------------------------------In most MOS transistors, both rds(OFF) and Ra are much
greater than RL. Therefore, Eq. (4) may be simplified
as follows:

4. The' performance of the series-shunt circuit is
equal to or better than that of either the series
or the shunt chopper alone fot any combination
ofRsand RL.
'

(5)

Approximate Output Voltage Eo"

(Max. Output

If RS, RL, and ES are assumed to have the values used
previously, the gate-to-source voltage Vas is assumed
to be -10 volts, and the gate resistance Ra is assumed
to be 10 12 ohms (minimum permissible gate resistance
for the 40460), the value of EO is calculated ss follows:

EO =

10-3~ :~~5J -10 [:o~: J

10-3
2

-10- 6 ~ 0.5 millivolt

Source
Load
Shunt
Resistance Resistance :Chopper

RS
(ohms)

(ohms)

1M
100 K
100
0
1M
1M
100 K
100

1M
1M
1M
1M
lOOK

100
100 K
100

=I

Series
Chopper

J.L V

mY)

Serie~Shunt

Chopper

(ON) (OFF) (ON) (OFF) (ON)

(OFF)

0.1
1
500
1000
0.1
0.05

0.0001
0.0001
0.0001
0.0001
0.0001
0.00005
0.0001
0.00005

500
900
1000
1000
90
0.1
500
333 500

500
900
1000
1000
90 0.1
0.1 0.0001
500 0.1
333 0.0001

500
900
1000
1000
90
0.1
500
333

Table /I - Steady-state chopper output voltage lor
various source and load res ;stances.

The second'term in Eq.(5) is the error term for the
OFF condition; it is not proportional to the input signal
Eg. For the numbers used, the output ernr in the OFF Transient Conditions
condition is only 0.2 per cent. If a typical value of
Fig.6 shows the ac equivalent circuit of an MaS
1014 ohms is used for the 40460 gate res,istance instead shunt chopper. The interelectrode capacitances of the
of the minimum value of 10 12 ohms, the error voltage is MaS transistor affect operation of the circuit at high
reduced to only'().002 per cent. The output error remains frequencies. The input capacitance Cgs increases the
small for any value' of signal voltage ES that does not rise time of the gate driving signal and thus increases
approach the error voltage in magnitnde.
the switching time of the chopper. This effect is not
Because the error voltage is inversely proportional usually a serious limitation, however, because the
'to the gate leakage resistance Ra, most junction gate
field-effect transistors produce larger, error voltages
r-----------------~------~~O~PUT
than MaS transistors (the minimum Ra of most junctionC d
gate devices is only 1 to 10 per cent that of MaS transistors).
YG•o-.....r-"''''R'''.---;
RS

A similar procedUre may be used for analysis of
series chopper and series-shunt chopper circuits.
The operation of all MaS chopper circuits is greatly
affected by the magnitude of the source and load resistances. Table II lists the output voltages of the
thr ee basic chopper circuits for various combinations
of source and load resistances. It is assumed that the
input voltage ES is 1 millivolt, and that the drain-tosource resistance rds is 100 ohms in the ON condition
and 1000 megohms in the OFF position. The gate leaKage resistance Ra 0012 ohms or more) is neglected.
Tbe following conclusions can be drawn from the data
shown:
1. Only the series or the series-shunt circuit should
be used when RS < rds(oN).
2. In general, RL should be high. (RL > > rds(ON)

3. The load resistance should be higher than th",
source resistance. (RL

28

~

RS)

Flg.6 - AC equivalent circuit 01 MOS shunt chopper.

switching time of the MOS transistor depends primarily
on the input and output time constants. Switching times
as short as 10 nanoseconds can lie achieved when an
MOS i.rWlt~iMLul" is di'iven from a low-impedance gene:aw&'
and the load resistance is less than about 2000 ohms.
The output capacitance Cds also tends to limit
the maximum frequency that can be chopped. When tbe
reactance of this capacitance becomes much lower than
the load resistance RL, the chopper becomes ineffective
becaUse XCds is essentially in parallel with RL and
rds(oFF).

-----------------------------AN-3452
The feedthrough capacitance Cgd is the most important of the three interelectrode capacitances because
it couples a portion of the gate drive signal into the
load circuit and causes a voltage spike to appear across
RL each time the gate drive signal changes state. Cgd
and RL form a differentiating network which allows the
leading edge of the gate drive signal to pass through.
The output capacitance Cds is beneficial to the extent
that it helps reduce the amplitude of the feed through
spike.
The effect of the feedthrough spikes can be reduced
by several methods_ Typical approaches include the
following:
(a) use of a clipping network on the output when
the input signal to he chopped is fixed in amplitude.
(b) use of a low chopping frequency.
(c) use of an MOS transistor that has a low feedthrough capacitance Cgd (some RCA MOS transistors
have typical Cgd values as low as 0.13 picofarad).

(d) use of a gate drive signal that has poor rise
"
and fall times.
(e) use of a source and load resistance as low as
feasible.
(f)

use of a shield between the gate and drain leads.

(g) use of a series-shunt chopper circuit.

Temperature Variations

The variation of MOS transistor parameters with
temperature can affect the operation of a chopper circuit
unless allowance is made for such variations in the
circuit design. It is important. therefore. to determine
the approximate degree to which" each parameter can be
expected to chauge with temperature. Fig.7 shows
curves of channel resistance rds. gate leakage current

SUBSTRATE CONNECTED TO SOURCE
VOS-Oi VGs=O. '~I.Hz

100

!/

I

.
..
::i
......
.'"
u

z

,/

300

/

t;

200

/

z
z

i..-

II

V

V

/

r;::o

:::10.0

..

E

100

/

~

u

o

-80

..
.......
....."
g;
IZ

-40

(a)

40
80
120
AMBIENT TEMPERATURE _·C

160

II

0:
II!

:>

u

SUBSTRATE CONNECTED TO SOURCE

VGs·+IO,,; VDS·O

/

V

-'

u

.

1.0

/

o

on

I

o
';"
z

4

/

100
dB
(with 0.2 volt at antenna terminals) •••••••

• Relative to 2 uV.

Table I - Over-all Tuner Perlormonce

The rf
the if strip
more fully
. transistors

section of the tuner is shown in Fig.1, and
in Fig.2. The if strip, which is described
elsewhere, 4 utilizes three 40482 bipolar
that operate at collector currents of 3.5

6-67

32

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ AN·3453

"3

to

",

p

"4

C'O

/

"s -q
CII

/

el2

/
/

/

/
/

~----~------~--------~----~--~~------/~-------------.-'sv
C"

/

"7

/
/

L3

"8

/
/

/
/

C,O

C'7

C'8

"0

All

C,s

Rl
R2
R3.R 4
RS
R6
R7
RS

L,

= 100 K\1
=220 K\1
=47 K\1
=4.7K\1
= S.2 K\1
=120K\1
=22 K\1

rosistors

112

w.

C 1,CS,C 16 = 16 pF
C2,C7 =2-12 pF, Trimmer
C3,C 6 = 0.002 /LF
C4,C 5,C'8 = 5.5-22.5 pF, ganged tuning capacitor
C 9 = 5000 pF
C lO =2.7 pF
C ll = 0.01 /LF
C12,C14,C1S = 1000 pF
C 13 = 1000 pF feed through type
e'7 =2-10 pF, Trimmer

#18 bore copper wire, 4 turns, 1/4" 1.0.,7/16" winding length, 0 0 at 100 MHz = 130.
Tunes with 34 pF capacitance at 100 MHz.
Antenna Link approximately 1 turn from ground end.
Gate Tap approximately 1-1/2 turns from ground end.

L2"= #18 bore copper wire, 4 turns, 1/4" 1.0.,7/16" winding length, 0 0 at 100 MHz = 120.
Tunes with 34 pF capacitance ot 100 MHz.
Bose Tap approximately 3/4-turn.

L3 = #18 bare copper wire, 4 turns, 7/32" 1.0.,7/16" winding length, 0 0 at 100 MHz =120.
Tunes with 34 pF capacitance at 100 MHz.
Emitter Tap approximately 1-1/2 turns from ground end.
Base Top approximately 2 turns from ground end.

Fig.! • Typical FM receiver 'ront end using RCA-40468 MOS field.effect transistor.

milliamperes in neutralized configurations and provide
an ovel'-all if gain of 94 dB.
The rf section provides a total gain of 34.5 dB,
which includes 12.7 dB in the rf stage and 218 dB in
the mixer. The mixer and oscillator were designed
according to principles established previously,5.6 and

details of their desigu are not discussed. The commoncollector oscillator provides an extremely clean oscillator waveform. In addition, the low injection level at
the mixer base, 25 to 30 millivolts, coupled with the
design of the preceding circuits, limits the maximum
possible signal at the mixer base and minimizes the
generation of spurious responses in that stage.

33

AN-~53--------------------------------------------------------

__

C,

T,

Q.68,F

I

0,

I

RIO
'000

~~+-"-1.:-O-'--HH

".

R"
UK

+---+-If---'
Rll
8.2K

°THE IN542 DIODES ARE A
MATCHED PAIR

All resistors 1/4 watt
0.01. and O.OS.. ,uF capacitors, SO.. V ceramic disks
330.. pF capacitors, l-kV disks

Fig.2 - Typical if-amplilier strip.
RF-Stage Design

The 40468 rf stage is designed to achieve the
published maximum usable stable gain of 14 dB at a
nominal operating point of 5 milliamperes. Additional
losses of 1.3 dB reduce the actual gain in the tuner to
12.7 dB. Details of the rf-stage design are given in
the Appendix.
Selection of the appropriate source and load impedances for the rf stage is based on the fact that a
low spurious response requires the gate of the 40468 to
be tapped as far down on the antenna coil as gain and
noise considerations permit. This arrangement applies
the smallest possible voltage swing to the gate and
makes optimum use of the available dynamic range.
(In a bipolar tuner designed to optimize the rejection
of spurious responses, the tap point on the antenna
coil was approximately 25 ohms.)
For low spurious response, therefore, the entire
rf coil is used as the load for the 40468. The inter stage
coil presents a load impedance to the rf stage of 3800
ohms, which nearly matches the 4200-ohm output impedance of the 40468. Although this arrangement loads
the inter stage coil and causes a degradation of selectivity of the front end, it is an acceptable compromise in
this case because the antenna coil is not loaded by the
gate of the MOS transistor.
As indicated by the calculations in the Appendix.
this approach yields a source impedance of approximately 200 ohms for the 45OO-ohm input impedance of
the gate of the 40468.
Tuner Performance

Performance of the tuner with respect to sensitivity
limiting, if rejection, and image rejection compares
favorably with that of tuners using high-performance

bipolar transistors. Figs.3, 4, and 5 show typical performance characteristics of the receiver. Receiver performance, particularly as regards spurious-responserejection figures, is highly dependent on such factors
as physical layout, power-supply decoupling, and care
in construction. The use of a negative supply voltage
facilitates the grounding of tuned circuits and the decoupling of the supply.
i

~'

~

I
I

~-dB

I
!

88

--

LIMITING

20 -dB QUIETING

1

a

I

3D-dB QUIETING

I
92

I
96

I

i
I

I

100

104

108

MODULATED INPUT SIGNAL-MHz

Fig.3 .. Sensitivity curves lor FM receiver
using circuits 01 Figs.! and 2.

The elimination of spurious response was the primary goal in this design. Generally, a circuit that has
a low spurious response is difficult to reproduce.

In

some systems, the performance of such a circuit depends
on the exact operating points of the transistors used;
when the rf-amplifier transistor in Fig.1 was repeatedly
changed, performance of the tuner remained essentially
the same. The best correlation was found with the
operating current of the transistor in the circuit. Fig.6
shows the change in the rejection of the "half-if'
spurious response as a function of drain current for a

-----------------------------AN-3453

-\0

V

-20

\

-30
-40

'-RELATIVE RESPONSE

I

I

CARRIER FREQUENCY;IOO MHz
MOOUL.AT10N~400

\

OEVIATIOi-22.5 kHz

I

I

\

-'0

Hz

-60

..c::...SIGNAL-TO~NOISE

to

\

10 2

I

RATIO
10 3

10·

SIGNAL VOL.TAGE AT ANTENNA-,..V

Fig.4 - Relatiye response as a function of signal yo/tage measured at antenna terminals.

T

0
0
0

-

60aa

IF

~-IF"REJECTION

1--1-- .

.lECTL

IMTE REfcT,or

90

~

~

~

~

=- -

DESIRED SIGNAL FREQUENCY-MHz

--

~

96

.l

94

92

90

"'"

:--r-

r--.._I

!

,

I

I

1--""" r--- r--

I
DRAIN CURRENT-mA

Fig.6 - Half-if rejection as a function
of operating point.

[

!

-

fffill 114

123456

910

DRAIN CURRENT-mA

Fig.7 - 20-dB quieting sensitiyity as a function
of operating paint.

~

Fig.5 .. Spurious-response rejection as a lunction
of frequency.

9a

typical 40468. For the normal spread of operating current in this circuit of 3.5 to 7 milliamperes, the variation in rejection is shown to be about ± 1 dB.
Fig.7 shows the variation of 20-dB quieting sensitivity as a function of drain current, aud indicates why
the 5-milliampere nominal operating point was chosen.
Below 3 milliamperes, the sensitivity of the receiver
degrades very rspidly. However, at 5 milliamperes the
actual spread of 3.5 to 7 milliamperes causes a negligible change in performance.

\0

Conclusions

The 40468 MOS field-effect transistor has been
incorporated into an FM tuner in which all other stages
are high-performance, low-capacitance bipolar types.
The wider dynamic range of the MOS transistor provides
significant improvements in the rej ection of spurious
responses over results previously achieved with bipolar
rf amplifiers.
Most significantly, the performance with respect
to spurious-response rejection has been repe ated when
devices with wide parameter variations have been used.
Furthermore, the system hss been duplicated with
comparable results. These two factors strongly indicate
that the performance advantages are real and are attributable to the characteristics of the MOS rf amplifier used
ratherthan theresult of cancellation or peculiar trapping
in a single tuner.

35

AN-~~~-------------------------------------------------------Appendix - Design of 40468 RF-Amplifier Stage

The following parameters are important in the design of the rf-amplifier stage:
40468 parameters (atVDD = 15 V, ID =5 rnA):
input resistance Rin . . . . • . .• 4500 ohms
output resistance Rout. . . • . .. 4200 ohnis
forward transmittance Yfs . . . .. 7500 /lmhos
feedback capacitance Crss (max). 0.2
pF
mixer-stage parameters:
input resistance Rin(mix) . . . .. 550 ohms
input stability IS(mix)
(from previous design) . . . . . .
4
coil data:
mounted unloaded Q. • . . • • . •. 120
tuning capacitance CT
at 100 MHz . . . . . . . . . . . . .
34
pF
antenna impeda~1Ce . . . . . . . .. 300 ohms
Fig.8 shows the ac equivalent circuit for the rf
stage. At resonll!'ce, this circuit reduces to the form
N,

where a is a skew factor smaller than unity which
is used to maintain bandwidth, and b is a number
equal to or greater than unity related to the number of
stages (inserted to maintain bandwidth in multistage
amplifiers). A skew factor of 0.2 is generally used.
Because only one stage of 100-MHz gain is used in the
amplifier shom in Fig.l, b = 1. For the values given,
therefore, MUG is given by
MUG = 0.4 Yfs = 23.5 = 13.7 dB
wCrss

(3)

The total mismatch loss is called the stability factor S,
and is equal to the difference (in dB) between MAG and
MUG, as follows:
S = MAG - MUG

=10.5 dB, or 11.3 times

(4)

This value is arbitrarily divided between the input and
output circuits by use of an input stability IS and an
output stability OS, as follows:
IS" Rin/2Rl

(5)

OS = Rout/2R2

(6)

where Rl and R2 are the total parallel impedances at
the input terminal (gate) and the output terminal (drain),
respectively. These stability terms are related to the
stability factor S as follows:
Fig.8 - AC equivalent circuit of the 40468 rf stage.

shown in Fig.9, where all impedances are referred to
the gate ami drain terminals of the 40468. The maximum
available gain (MAG> is the gain in a coniugately
matched, unilateralized circuit and is defined as follows:
IYfsl 2 Rin Rout
MAG =
4
(1)
For the ,values given above, MAG = 266 = 24.2 dB.

S =ISxOS

(7)

The division between IS and OS is made by means
of some arbitrary choices. As mentioned previously,
it was decided to maximize IS so that the signal level
at the gate would be minimized. This choice necessitates matching or nearly matching Rout to its load.
Therefore, the entire rf coil is used as the output load.
As indicated in Eq.(6), the value of R2 must be
determined to define OS; the value of IS can then be
determined and the input circuit defined. R2 consists
of the parallel combination of Rout, RT2, and (N IIN2)2 x
Rin(mix), where RT2 is the tuned impedance of the rf
coil and is given by
(8)

Fig.9 - Equivalent input (R7i ancl output (R2i circuit
of the ,f stage eluring resonance.

The maximum usable gain MUG is the stable gain
which may be realized in a practical neutralized or unneutralized circuit. It is defined by the relationship
for the unneutralized case as follows:
2 IYfsl a
MUG = - - - x (2)
wCrss b

36

The value of Rout is given above as 4IDO ohms. The
value of RT2 as calculated from Eq.(8) is 5600 ohms.
The value of the input impedance of the mixer Rin(mix).
obtained from the published data for the 40479, is 550
ohms. The only remaining component of R2 to be determined is the turns ratio NIIN2In Fig.8, the rf coil L2 represents both the input
circuit of the mixer and the output circuit of the rf
stage. Therefore, the stability of the mixer stage must
also be considered. Because stability factors are
equal to resistance ratios, the input stability of the

-----------------------------AN-3453
mixer can be considered at the top of the rf coil, as
follows:
(9)

The value of IS(mix) was' specified above as 4 (from a
previous design). Because R2 is a linear function of
(NIIN2)2 Rin(mix), manipulation of the data through
several steps provides a value of 5.5 for (NI/N2) and
a reflected value of 16,800 ohms for Rin(mix).
The output stability of the rf stage can then be
determined. R2 is computed as the parallel combination
of Rout, RT2, and (NlIN2)2 Rin(mix), and is found to
be 2100 ohms. The output stability OS is determined
from Eq'(6), as follows:
OS

=Rout/2R2 =4200/(2 x 2100) =1

(NalN2)2 RANT is 382 ohms, which is a very slight step
up. Because two of the three component terms of R 1 are
then known, the remaining term (N3/N1)2 RTI can be
determined as 456 ohms. The turns ratios are then
given by
NIIN2 = 4.3
NIIN3 = 3.7
The values of circuit components obtained by means
of this design method are given in the parts list for
Fig.!.

References

1. F. M. Carlson and E. F. McKeon, "Small Signal RF
Amplification of MOS Devices," Proceedings of the
1966 National Electronics Conference.

The value of unity indicates an impedance match between Rout and the load.

2. F. M. Carlson, "Application Considerations for the
RCA-3NI28 VHF MOS Field-Effect Transistor,"
RCA Application Note AN-3193, August 1966.

The input stabilily of the rf amplifier can then be
determined from Eq.(7), as follows:

3. D. L. Leonard, "Improve FM Performance with FETS,"
Electronic Design, Vol. 15 No.5, March 1967.

IS

= S/OS = 11.3

By use of this stabilily term, the input-circuit constants
can be calculated. Rl is determined from Eq.(5), as
follows:
Rl = Rin/2IS = 191 ohms
This value is so much lower than Rin that it is apparent
the MOS trsnsistoc does not load the antenna coil at all.
Because it is desired to match the anteJUla with
the input circuit, the value of R1 should be one-half the
reflected sntenna impedance.
Therefore, the value of

4. R. T. Peterson, "High-Quality FM and AMlFM Tuners
Using New Silicon Transistors," RCA Application
Note AN-3466, June 1967.
5. R. V. Fournier, C. H. Lee, and R. T. Peterson,
''Performance Analysis of 3- and 4-Coil FM Tuners
Using RCA High-Frequency Trsnsistors," IEEE
Transactions on Broadcast and TV Receivers,
November 1965.
6. R. V. Fournier, C. H. Lee, snd J. A. Kuklis, "A
Goal: Spurious-Signal Immunily of Solid-State AMlFM
Tuners," IEEE Transactions on Broadcast and TV
Receivers, April 1966.

37

OO(]5LJD

MOS Field· Effect Transistors

Solid State
Division

Application Note
AN-3535

An FM Tuner Using
Single-Gate MOS Field-Effect Transistors
as RF Amplifier and Mixer
by

C.H. Lee and S. Reich

Selection of the transistors for use in FM-tuner
stages involves consideration of such device characteristics as spurious l'esponse 1 , dynamic range, noise
immunity, gain, and feedthrough capacitance.
MOS
field-effect transistors are especially suitable for use
in FM rf-amplifier' and mixer stages because of their
inherent superiority for spurious-response rejection and

signal-handling capability. This Note describes an FM
tuner that uses an RCA-40468 MOS transistor as the rf
amplifier and an RCA-40559 MOStransistor as the mixer.
A conversion gain of 17.5 dB was obtained, to provide
an over-all tuner gain of approximately 30 dB. RF and
mixer circuit considerations pertinent to the design are
discussed.
Performance Features of MOS Transistors

the transistor; and a, f3, and

e are the coefficients of a

Taylor series expansion. These coefficients are related

to the first-, second-, and third-order derivatives of the
transfer characteristic as determined by the 'bias point.
It can be shown2 ,3 that mixing action within the device
is attributable to the second-order term (j3es 2), and that
cross-modulation and intermodulation result from thirdand higher-order terms. Therefore, when a device has
an inherent square-law transfer characteristic, i.e., the
drain current varies as the square of the applied gateto source voltage, third- and higher-order terms are
zero and spurious response is eliminated. The transfer
characteristic of MOS field-effect transistors more nearly
approaches this ideal square-law relationship than the
very steep exponential transfer characteristic of bipolar trans istors.

Spurious response in an FM tuner is caused by the
mixture of unwanted signals with the desired carrier in
either the rf stage or the mixer. This effect can be
expressed mathematically by use of the Taylor series
expansion of the simple transfer function of output current as a function of input voltage at the operating point,
as follows:

The dynamic-range capability of MOS field-effect
transistors is about 25 times greater than that of bipolar
transistors. In an actual tuner circuit, this large intrinsic dynamic range is reduced by a factor proportional

io • 10 + ae s + f3e s 2 + ees 3 +. • •

WithMOS field-effect transistors, as contrasted with
either bipolar transistors or junction-gate field-effect
transistors, there is no loading of the input signal, nor
drastic change of input capacitance even under extreme
overdrive conditions.

(1)

wbere io is the instantaneous value of output current of
the device; 10 is the dc component of output current; es
is the rf signal voltage present at the input terminal of

38

to the square of the circuit source impedances. 4

1 ne

net result is a practical dynamic range for MOS tuner
circuits about five times that for bipolar types.

12-67

-------------------------------AN-3535
In junction-gate field-effect transistors, a large incoming signal can have sufficiently high positive swing

12.7 dB. The mixer transistor RCA-40559 also operates
in the common-source configuration, with both the rf and
local-oscillator signals applied to the gate terminal.
The bipolar oscillator transistor RCA-40244 operates in
the common-collector mode. The conversion power gain
from the mixer stage is 17.5 dB; the total gain of the
tuner is 30_2 dB.

to drive the gate into conduction by a momentary for-

ward bias; power is then drawn from the input signal in
the same way as

if a resistance were placed across the

input circuit. In bipolar transistors, there is a gradual
change of both input impedance and input capacitance
as a function of large signal excursions. These changes
are undesirable because they can result in detuDing of
tuned circuits and widening of the input selectivity curve.

Performance of the FM tuner was evaluated by use
of the bipolar-transistor if amplifier shown in Fig.2.
The 10.7-MHz if output from the tuner is coupled to the
first if-amplifier stage by means of a double-tuned transformer T 1. The if amplifier employs two 40245 and one
40246 bipolar transistors, each operating in a neutralized
common-emitter configuration at a collector current of
3.5 milliamperes. The over-all gain of the if amplifier
is 88 dB. A detailed analysis of a similar if amplifier
is covered in an earlier publication. S

FM Tuner Design
The FM tuner shown in Fig.1 uses single-gate MOS
field-effect transistors in the rf-amplifier and mixer
stages and a bipolar tr ansistor as the local oscillator_
The rf-amplifier transistor RCA-40468 operates in the
common-source configuration with a stage gain of

Cia' Clb, Clc RF AMP.

~!t;1 wti~~irr~m~:~c~:~rppe~R~f.s-Plate Model

e2 1 C3, C4 - Areo 402 trimmer I maximum value 10 pF

LI -

rJ2!,S ~r:~ ~~~~~5(i!~ ~2~~'~~~;0}J~~~~.fO~r; ~~iuen~~~

tenna tap at 0.8 of a turn, output tap at 1.4 turns.
L2 - No.IS bare copper wire, 5 turns on 15/64" form, coil length
3/S", with O.ISI" x 0.375" Arnold slug. Qo = 104.

L3 -

~gill~e~:;~ ~/~p'.er l~\fierS t~~n~~ f~u~r~u:-:,i~~ 3/:;d~~k

tap on 2 turns. Q = 164.
-+-"T-=~---t"""'-+IBV

T1 -

~~~~I: ~~~~~'p~~!Q ~el~7f:{ti~i6:~PF~~~ii~~· c~~ia~i~~n~~-,
secondary unloaded uncoupled Q = 76 with 47-pF tuning
capacitance. Secondary has a turns ratio of 26.2 to 1.0.
Primary. No.32 enamel wile, 15 turns, space wound at 60
TPI, 0.250" x 0.500" TH slug. Secondary, No.36 enamel

All resistors in ohms,

wire,IS turns, close wound, 0.250" x 0.250" TH slug. Both

unless specified otherwise

coils on 9/32" form without shield.

Fig.! - Circuit diagram of FM tuner using MOS transistors for the rf amplifier
and mixer stages.

IK
.. 8
K

6.8
K

.. IOmF
6V

1.5K

OD2

All resistors in ohms,
unless specified otherwise

l"F

AUDIO OUT

Fig.2 - Three-stage if amplifier using bipolar transistors.

39

AN-3535---------------------------------------------------------Table
summarizes the performance of the MOS
tuner. Spurious response was evaluated with a generator
output of 350 millivolts_"

also makes it unnecessary to add neutralization com ..

ponents to the rf stage to achieve adequate gain.
Mixer-Circuit Considerations

OVER-ALL TUNER PERFORMANCE
Carrier Frequency .. . . . . . . . . . . . .

Modulation Frequency ..•••••••••
Deviation (except IHFM) . . . . . . . • .

100
400
22.5

MHz
Hz
kHz

1.75
1.5
1.75
2.5
62
96
92

/-LV
/-LV
/-LV
/-LV
dB
dB
dB

Sensitivity:

IHFM ••.•• , ....•.•••..•••
20-dB Quieting •••.••••.. ' •...
30-"
resented by the signal-limiting ~iodes. The ideal
signal-limiting diodes, with an infinite transfer slope
IRs =0), ,,!ould then limit the voltage presented to the
gates to ItS knee value, ed' The.difference voltage.
E - Bd = e s (where E is the static potential in the static
generator, ed is the diode voltage drop, and e s is the
voltage drop across the generator intemal resistance)
appears as an IR drop across Rs ' the internal impedance
of the generator. The instantaneous value of the diode
current is then equal to es/Rs. During handling the
practical range of this discharge varies from se~eral
milliamperes to several hundred milliwnperes.

Gate·Protection Methods

It has been established above that in terms of a
static discharge potential it is reasonable to represent
the MpS tran.sist~r as. a capacitor, s~ch I!s CJN in Fig.4.
The Ideal SItuatIOn 10 gate protectIon IS to provide a
signal-limiting confignration that allows for a signal
such as that shown in Fig. 4 (a) to be handled without
clipping or distortion. The signal-limiting devices
should limit all transient responses that exceed the
gate. breakdown voltage,. as shown in Fig. 4 (b). One
pos~lble .means of se~urlOg proper limiting is to place
a dIode 10 parallel WIth CrN, as shown in Fig. 4 (c).
Unfortanately, this arrangement causes several, undesirable consequences. In terms of signal ,handling,
the single diode clips the positive peaks of a sine wave
such as that in Fig. 3 (a) when the transistor is operated
in th!, vicinity of zero bi.as. The 3Nl40 dual-gate MOS
tran~lstor, for ~xwnple, IS frequently operated with the
rf SIgnal superImposed on a slightly\ positive "bias"
potential on. gate !'I0' 1. Furthermore, gate No. 2 of
the ~Nl40 IS deslgne.d to handle large positive and
n!lgati ve dc voltage SWIngs from the agc loop. A singlediode arrangement would render this device useless
for this type of circuit. It is important, therefore that
the limiting device be an effective open circ~it to
any incoming signals tbrough the amplitude range of
such signals. The best available method for accom-

1-+ 10

I.'

101

Fig. 5· Transler characteristic 01 protective diodes (a),and
resulting wave/orms in equivalent circuit (b).

45

AN-4018 - - - - - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ __
Electrical Requirements

The previous discussion points out that optimum
protection is afforded to the gate with a signal-limiting
diode that exhibits zero resistance protected MOS uansistor is compared to a high-frequency bipolar device. A laboratory experiment in which a
static charge was accumulated in a capacitor and diecharged through a circuit configuration like the one
shown in Fig. 3 demonsuated that the special siguallimiting diodes made the protected-gate MOS fieldeffect transistor less vulnerable to static discharge
damage than the bipolar uansistor by a factor greater
than two.

Power Gain and Noise Factor

In the final analysis, the question that must be answered is how the addition of the protective siguallimiting diodes affects circuit power gain and noise
factor. Performance data taken on the ten units described above in the typical rf test circuit shown in
Fig. 11 are given in Table 1. Noise-factor values show
an average degradation of 0.25 dB when the diodes are
connected. The power-gain values show that the change
in this characteristic is insignificant.

Table 1- Power Gain and Noise Factor at 200 MHz.

HYBRID
UNIT

1
2
3
4
5
6
7
8
9
10

POWER GAIN
(dB)
DIODES
DIODES
REMOVED
IN
16.4
16.3
18.8
18.5
16.2
16.5
15.7
16.3
17.8
17.7
17.2
17.5
17.0
17.1
18.0
17.9
18.5
18.5
17.3
17.3

NOISE FACTOR
(dB)
DIODES
DIODES
REMOVED
IN
3.7
3.4
2.2
2.4
3.0
3.3
3.9
3.4
2.6
2.4
2.8
2.5
3.3
3.2
2.9
2.6
2.4
2.3
3.0
3.2

47

AN-4018--------------~--------------------------------~----~---

r-----------"'T----------C';'.--'OUTPUT
\
I
\._01
I
I
I
I

I

I
I

I
I

'NPUT :rSOLOj,I-"_-'_N'+_,
C,

I

C3

: RI

,

I

l-c2

LwHifE~

'

l

lelO

C8

=---GREEN ~-----~u£J~---~

"3

01: 100 pico'arads. ceramic disc

C2 C7 C8 C9 ClO' 1000 picofarads, feed-through type
03: 1 to 10 picofarade, variable air (piston);
JFD VAM-Ol0, Johnson Co. No. 4335,' or equivalent
04: 1.8 to 8.7 picofarads, variable airi
Johnson Co. No. 160-104 or equivalent
OS: 3 picofarads, tubular ceramic
06: 22 picofarads, ceramic disc

Cn' 1.5 to 5 picofarad., variable air;
Johnson Co. No. 160-102 or equivalent
012: 100 picofarads, ceramic disc
CIS! 1.5 picofarads, tubular ceramic
014: 0.8 to 4.5 picofarads, variable air (piston);

Erie 560-013 or equivalent

SmA

Ferrite 4 beads on No. 24 wire between Ll and socket; beads
beads: are Pyroferrio Co. "Carbonyl JU or equivalent:
0.093-inch OD, O.03-inch!D, 0.063 inch thick
L 1: 4 turns O.020-inch copper ribbon, silver-plated, 0.075 to
0.085 inch wide, O.25-incb inside diameter, coil
approximately 0.80 inch long
L2: 4.5 turns 0.020-inch copper ribbon, silver-plated, 0.085 to
0.095 inch wide, 0.3125--inch inside diameter, coil approximately 0.90 inch long
R3: 36,000 ohms
Ql' MOS transistor under test
R4 , 1800 ohms
RFC: Ohmite part No. Z235
or equivalent
RS: 275 ohms, 1h watt, 1%
R 1, 27,000 ohms
Ra: 120.000 ohms
~: 1000 ohms
R2' 47,000 ohms

Fig.l1.RF testcircuitlorrlua/.gate MOS transistors.

Conclusions
Gate-protected dual-gate MOS field-effect transistors
such as the RCA-40673 make available to the circuit
designer a device capable of good rf performance without the hazards previously associated with the handling
and installation of MOS devices. Moreover, the gate
protection is provided by signal-limiting diodes that do
not significantly compromise dynamic range, noise factor, or power gain.
Acknowledgment
The authors thank L. Baar for collecting data and providing l!I!IleralsuDDort for the work described. and C. Tollin
for fabricating-the devices tested.
.

48

References

1.

H.M. Kleinman, "Application of Dual-Gate MOS
Field-Effect Transistors in Practical Radio Receivers", IEEE TRANSACTIONS ON BROADCAST
AND TV RECEIVERS, July 1967.

[Kl(]5LJD

Linear Integrated Circuits

Solid State
Division

Application Note
ICAN-4072

Applications of the RCA CA3048
Integrated-Circuit Amplifier Array
by
L. Kaplan
The RCA CA3048 integrated circuit is an array of
four identical amplifiers, each with independent inputs
and outputs, al1 on a single monolithic silicon chip. The
circuit is housed in a 16-lead dual-in-line plastic package. It has an operating and storage temperature range
of -250 C to +850 C. Each amplifier in the array has a
typical open-loop gain of 58 dB and input impedance
of 90,000 ohms. The noise in the CA3048 is inherently.
very low and is tightly control1ed in rigorous factory and
quality-control testing.
The combination of low noise, high gain, and high

input impedance make, the CA3048 a very versatile unit.
and numerous applications suggest themselves for its
use.
CIRCUIT DESCRIPTION

Fig. 1 sho;'s the complete schematic of the CA3048
integrated-circuit amplifier array. Each amplifier (A1
through A4) provides two stages of voltage gain.
The input stage is basically a differential amplifier
with a Darlington transistor added on the one side. The
output stage consists of ~ combination of three transistors and associated resistors connected in an inverting
configuratioq. For example, in amplifier A3 , Q19 is the
Darlington input transistor, and Q20 and Q21 are the

differential-pair transistors. The load resistor R29 for
the differential input stage is located in the col1ector
lead of transistor Q20· Transistors Q13' Q14' and Q17
are used in the output stage. Transistor Q17 is the actual output transistor; transistors Q13 and Q14 raise
the input impedance of the output stage so that the loading· of the 30,OOQ.ohm source resistance R29 (i.e., load
resistor for the differential-amplifier input stage) is
small. The ratio of total collector resistance to emitter
resistance [(R31 + R38)/R50l in the output stage is
1000/200, or 5. In view of the small source loading, the
stage gain, therefore, is essentially equal to 5.
A feedback network (R41' R4 2' R46 , and 07) is
connected between the output terminal and the base of
transistor Q21. The resistor values are chosen so that
the output transistor is biased at approximately 5 milliamperes for maximum dynamic range. Diode 07 compensates for variations in the .base-to--emitter voltage
of Q21 with changes in temperature. Because the other
transistor (Q20) of the differential amplifier has two
emitter-base junctions in series, two diodes, D3 and D4 ,
are required for temperature compensation.

Diodes D3

and 04 also provide temperature compensation for the
differentiall'air transistor Q1 in amplifier A2 (similarly
diodes 05 and 06 ar.e shared by amplifiers A1 and A4 )·

3·70

49

ICAN-4072
Diodes 03 and 04 and diodes 05 and 0 6 are connected
to their respective inputs through a relatively stiff voltage divider (for amplifier A3' the divider consists of
R27 and R28)' The input to amplifier A3 is normally
applied to the base of the Darlington transistor Q1g.
The 100-kilohm resistor R37 supplies bias current to
this transistor. The voltage drop across resistor R37
is small because of the very small base current of transistor Q19'
Each amplifier of the CA3048 may be viewed as an
ac operational amplifier in which a fixed resistance is
permanently connected between the output aiId the inverting input. The built-in feedback resistor delimits
the characteristics of the CA3048 amplifiers in the following ways:
1.

The impedance as viewed from the noninverting in-

putterminal consists mainly ofthe 100 kilohm inputbias resistance (R13' R1S ' R37, or R3"9)' This resistance is shunted by the input capacitance of approximately 10 picofarads and the additional resisti ve loading presented by the input impedance of the

Fig.

50

Darlington input pairs. When the amplifier is operated under open-loop conditions (inverting input at
ac ground), the total input impedance consists of
gO kilohms in shunt with the input capacitance.
When the built-in feedback loop is allowed to function (by insertion of an unbypassed resistance in
the noninverting input lead), then the loading caused
by the Darlington input pairs is reduced, and the
input resistance rises asymptotically towards 100
kilohms.
2.

The imped ance as viewed from the inverting input
terminal is small (in the order of 40 to 50 ohms.)

3.

When the CA3048 is used in its normal mode of operation, each amplifier in the array may be represented by the equivalent circuit shown in Fig. 2.
(The capacitances shown are the sum of the device
capacitances, socket capacitances, and stray capacitances.) The transconductance Gm, which is
equal to the product of the voltage gain and the
output conductance (10-3mho), is typically 0.8 mho
at midband.

I - Schematic of the CA3048 integrated-circuit
amplifier array.

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ICAN-4072
equal to 1/(R I6 + R22)! 1/(RI4 + Rig), 1/(R31 + R38)'
or 1/(R36 + R4 0). The capacitance C4 and the conductance G4 shown in Fig. 2 represent an external damping
network which can be varied or deleted as demanded by
stability or gain-bandwidth requirements.

c.
I

iil

C,

Fig. 2 - Equivalent circuit of a CA3048 amplifier.

GAIN-FREQUENCY RESPONSE
Curves of the transconductance of any amplifier in
the CA3048 array as a function of frequency up to 30
MHz ·show two break points. At frequencies above the
first break point, which occurs at 300 kHz, the transconductance rolls off at a rate of 6 dB per octave to 12
MHz. At frequencies above 12 MHz, the rate of roll-off
increases to 12 dB per octave. At frequencies up to 12
MHz, therefore, the transconductance of any amplifier in
the CA3048 array is expressed by the following equation:

A necessary and sufficient condition for a system
to be stable is that the roots of the characteristic equation of the system have no positive real parts. The
characteristic equation for the circuit of Fig. 2 is obtained by expansion of the circuit detenninant and collection of the coefficients of the complex frequency S.
The equation assumes the following form:
Al + A2S + A3s2 + A4s3 + ASS4 .= 0
(2)
After much tedious algebra, the coefficients are determined as follows:
Al = wo GIG 3 G4
A2 = w o G4 [G 3(C 1 + C2) + Gl(C 2 + C3 ) - ~ G2 ]
o

+ G I G3(C 3w o + G4 )

A3 =

(1)
- "'ogmo
CUa + S
where S is the complex frequency, ~o is the mid-band
transconductance, and "'0 = 211 X 300 x 103.
g

m

{C2C3(GI + G3 + G4 - ~o) + Cl [C3(G3
+ G4 ) + C2G4 ] } + G4 [G 3 (CI +C 2)

Wo

+ GI(C 2 + C3)] + G1G3 C3
A4 = G4 [Cl(C2 + C3) + C2C3] + C3 [Cl(w oC 2
+ G3 ) + C2(G 1 + G3)]

Fig. 3 shows the open-loop transconductance for an
amplifier in the CA3048 array as a function of frequency.
This response indicates potential uses of the CA3048
integrated circuit at frequencies that extend into the
video range.

STABILITY
The equivalent circuit shown in Fig. 2 can be used
to determine the stability of the amplifiers in the CA3048 array under various conditions of loading when undesirable external capacitance is present in the wiring
and socket. With no external generator connected to. the
circuit, the input conductance Gl is equal to 1/1000aO
mho, and the output conductance G3 is equal to 1/1000
mho (for amplifiers AI' A2, A3 , or A4 , respectively, G1
is equal to l/RIS' I/R 13 , I/R37' or l/R29' and G3 is

AS = CIC2C3
(3)
With the aid of a computer, it IS possible to check
very quickly many combinations of circuit values for
stability by solving for the roots of Eq. (2) with different circuit values assigned to the various components.
Although there are many variables involved, it is
possi.ble to state in a general sense the results of several solutions of Eq. 2.
The system cannot oscillate without capacitor C2
to introduce positive feedback. The analysis is reduced,
therefore, to the determination of the maximum value
of C 2 before oscillation occurs. With careful printedcircuit-board layout, the feedback capacitance C 2 is
. small, and the system is usually stable. If a socket is
used the feedback capacitance is greatly increased, and

20
9m AT FREQUENCIES LESS
o THAN 100 kHz· 0·8 MHO

-

a
a

r--.

a
a
-6 a

0.1

...... r--......

I"'--

-

a

-70

I"-

2

.•

""'

.••

FREQUENCY-MHz

10

"'"." •

100

Fig. 3 - Typical gain-frequency response for a CA3048
amplifier.

51

ICAN4072 _________________________________________________________
stabilization of the circuit is generally required.

1.28

As with any two-port .network, any increase in
source or load conductance aids stability. In addition,
analyses of Eq. (2) show that addition of shunt capacitance at the input is a very effective stability technique
when the source impedance is high. Introduction of
negative feedback into the circuit [which is simulated
in .Eq: (2) by a decrease in the value assigned to the
transconductance gm and an increase in the cutoff frequency 1 also improves circuit stability.

0.64

/

V
~

Another stability method, which is effective for any
source impedance or gain value, is the addition of a
damping network such as that formed by capacitance C4
and conductance G4 in Fig. 2. In this method,. the value
of C 4 is chosen so that its reactance is equal to the
parallel combination of R3 and RL at the highest frequency of desired amplification. The value of R4 is
made small so that the gain is reduced at high frequencies and is typically 1/10 or 1/20 the value of the parallel combination of R3 and RL"
The series of curves in Fig. 4 show the results of
the computation for the roots of E q. (2). It should be
noted that the maximum value shown for capacitance C2
is that obtained just before oscillation occurs. Severe
peaking of the response (or ringing) may result before
the listed value of C2 is reached. It is advisable, therefore, to maintain the capacitance of C 2 well below the
indicated value.
12

•

~ 0.32

;'!
<;

1f

a 0.1 6
~
~

.,.

0.0

•

~

ill

~ 0.04

~

v

1/

/

~ 0.04

V

0.02

,.

0..0. I
0.

L2

•

\1

0.32

1f

:l
"

I
~

l!

016

DDO

~

/

(a)

.
~

~ 0,04

~

Q02

0..0. I
100
300
1000
TOTAL INPUT CAPACITANCE-pF

30

-

30110 6

10'

-

3xl0 4

-

10!

31110 5

TOTAL CONDUCTANCE AT INPUT-mhos

Fig. 4 - Stability curves for a CA3048 amplifier: (a) permissible feeelback capacitance as a function of the
total coneluctance at the input; (b) permissible feeelback
capacitance as a function of gain reeluction anel of banelwielth increase; (c) permissible feeelback capacitance
as a function of the total input capacitance.

52

/

V

g

(c)

-

3D

I

Q64

10.

10xi0 6

24

(b)

0.02

0..0. I

I.

GAIN REDUCTION AND BANDWIDTH INCREASE-dB

:i

V

/

V

Ii

/

t

.

I

r

/

0.64

/

~ O.OB

300.0.

_______________________________________________________ ICAN4072

OUTPUT SWING VS. SUPPLY VOLTAGE
Fig. 5 shows the output voltage for anyone of the
CA3048 amplifiers as a function of supply voltage. The
solid lines represent the performance obtained with the
full open-loop gain. The dotted line shows the improvement obtained when 12 dB of negative feedback is added
by inclusion of a ISO-ohm unbypassed resistor in the inverting-input lead. The values obtained for this curve
are those which prevail when the output is loaded only
by the measuring equipment. It should be realized that
any substantial loading will tend to reduce the magnitude of the available output voltage for equivalent distortion figures. For example, an additional 1000-0hm
load exactly balances the internal load resistor, and
would reduce the available output voltage by 50 per
cent.

voltage (Enoise> and current 0noise) for the-CA3048 at
spot frequencies of 10, 100, 1000, 10000, and 100000 Hz.
From these values, the equivalent input noise voltage
for any value of source resistance may be computed by
use of the following equation:
Eequiv = ,j(Enoise)2 + (Inoise Rsource)2

BOO

600

I
~

~

~ 4r-----t------r~r__t--_+~----~t_----~
~

I

400

o

...
~

~ 200

~
~

..-/

3r-----+------r~--_t--t__1--_+--+_-

~
c

o

!1

2i-----t-------tl------h1----++----f-/--

~

~

e
;i

/

>~

...

1r-----t-~f_-r--~_t--~~--~--~~--4

0.5

1.0

1.5

Fig. 5 - Total harmonic distortion of a CA3048 amplilier
as a function of output voltage for different value of dc
supply voltage.

NOISE
Fig. 6 shows output noise obtained when a single
amplifier of the CA3048 is operated at 40 dB gain into
a "c" filter. Table 1 shows typical values of noise

TABLE I
TYPICAL NOISE VOLT AGE AND CURRENT FOR AN
AMPLIFIER IN THE CA3048 ARRAY
Frequency
Enoise
Inoise
(Hz)
(volts)
(omperes)
30.5 x
17 x
8x
6x
4x

10.9
10-9
10-9
10-9
10-9

10

100

1000

/

/

V
10,000

100,000

SOURCE RESISTANCE-OHMS

Fig. 6 • Noise output as a function of source resistance
for a CA3048 amplifier.

CIRCUIT APPLICATIONS

2.0

OUTPUT VOLTAGE- rms VOL.TS

10
100
1000
10000
100000

(4)

Laboratory measurements have shown that the noise
performance of the CA3048 is not significantly affected
by variation of the supply voltage. The values shown in
Fig. 6, therefore, may be used with supply voltages
down to about 2 volts if it is remembered that the openloop gain decreases to about 35 dB at a supply voltage
of 2.5 volts.

7.5 x
4.3 x
1.2 x
0.5 x
0.3 x

10- 12
10- 12
10- 12
10. 12
10- 12

In all the foregoing discussions, a single amplifier
has been described as though it existed alone. The
CA3048, however, consists of four separate amplifiers,
which may be used independently or in combination. A
glance at the complete schematic of the CA3048 reveals
other aspects worthy of consideration.

Two supply-voltage terminals and two ground terminals are indicated. Terminal No. 12 supplies the VCC
voltage to amplifiers A2 and. A3 , and terminal No. 15
supplies the VCC voltage to amplifiers Al and A4 . The
ground return for amplifiers Al and A4 is provided by
terminal No.2; all other ground returns are provided by
terminal No.5.
When two units are cascaded, it is preferred to let
amplifiers A2 and A3 be the input units, and amplifiers
Al and A4 be the output units. This arrangement permits separation of both the VCC and ground lines for lowand high-level signals.

If resistive decoupling is used, amplifiers A2 and
A3 can be operated at lower VCC voltages to effect a
savings in current consumption.

53

ICAN~072

_________________________________________________________

Hartley Oscillator
The Hartley oscillator is easily designed and constructed using the CA3048 amplifier. No feedback capacitor is required, and it is possible to extract "square",
sawtooth, or sinusoidal waveshapes.
In the circuit shown in Fig. 7, the tap on the coil
is located at one-fourth the total turns, capacitors C I
and C2 provide dc bl0

i:

4

~}2-~~-~-:-~==~~~~Q~5-=::L--~

vos,

GATE No.I-TO~SOURCE VOl.TAGE (VGtS)-VOLTS

vG,S
. ON THIS SIDE OF vos,· VG2S
f----HY~1L-/-:.,..f-- LINE GATE No.2 IS POSITIVE

0

WITH RESPECT TO ITS OWN

z

SOURCE.

>

la)
AMBIENT TEMPERATURE (TAI-25-C
DRA1N-TO-SOURCE VOLTS (VgSI-15

~

5

ll,v"

'"ug;

~

0'--

z

0

'(I / ' .-!-

--

"

8"

~

~

~n

GATE No.2-TO-SDURCE VOLTAGE (VG2S)-VOLTS

gate MOS transistor.

V

I-- i-2-

--

I~~E

0"1-_2':---:~..L-+':-2--+.J4L..--.J+6-----.l+6:---+.l'0-:---1+12
Fig. 10. Voltage distributions for the 3N140 dual·

TYPE 3NI40

o

-I

-2

No. 2-TO-SQURC
VOLTS (VG2SI--1

o

GATE No.I-TO-SOURCE VOLTAGE (VGISI-VOLTS

Operating curves for the 3N140 are shown in
Fig. 11. These curves can be used to establish
a quiescent operating condition for the transis·
tor. For example, a typical application may
require the 3N140 to be operated at a drain·tosource voltage V DS of 15 V and a transconduct·
ance gf. of 10.5 mmhos. As shown in Fig. 11(a),
the desired value of gf. can be obtained with a
gate·No. 2·to-source voltage V a•s of +4 V and a
gate-No. 1-to-source voltage Va" of -0.45 V.
From Fig. 11 (b), the drain current compatible
with these gate voltages is 10 mAo
Two biasing arrangements which can be used
to provide these operating conditions for the
3N140 are shown in Fig. 12. For the application
mentioned above, it may be assumed that shunt
resistance for gate No. 1 should be 25,000 n
and the dc potential on gate No.2 should be fixed
ane at rf ground. The remaining parameters for
the biasing circuits can then be obtained from
the curves showing I D as a function of Rs in
Fig. 13, with Rs = 270 n:
Vs = ID Rs = +2.7 V
Va, = Va" + Vs = +2.25 V
Va. = V a• s + VB = +6.7 V
V DD = VDS + Vs = +17.7 V

(21)
(22)
(23)
(24)

Ibi
Fig. 11. Characteristics curves for the 3N 140.

The values of the resistance voltage dividers
required to provide the appropriate gate voltages
are determined in the same manner as shown
previously for single-gate transistors. For the
circuit of Fig. 12(a), R, is 197,000 n, R, is
28,600 n, and R, R, = 11/6.7.
The circuit of Fig. 12(a) is normally used in
rf-mixer applications and in rf-amplifier circuits
which do not use agc. The circuit "of Fig. 12(b)
is recommended for the application of agc voltFIXED SUPPLY

OR
AGC VOLTAGE

R,

la)

Ib'

Fig. 12. Typical biasing circuits for the 3N140.

61

AN-4125 ________________________________________________________

5
TYPE 3N140

l!

; ~~ /

'\los0r-v".o+I5Y- 1--8
5

" .. OIOIS

Ot----

•

I~ ~J'"
1//
..0

'//

0

5

//§ 1

1/

}

V

4'

~ -y ~
[-

V

~

rP

I

the use of source resistance Rs; variations in

drain current are reduced significantly by use
of an Rs value of 1000 n.
Variations in transconductance can be virtually eliminated by application of a gain-control
voltage from a temperature-dependent voltagedivider network to gate No.2. For example, the
values of the resistance voltage dividers in the

"C

I

ance as a function of temperature. These curves
also show the compensating effects produced by

12

14

DRAIN CURRENT (IDI- MlLLlAMPERES

I. I.

Fig. 13. Draln-current curves for various values of

R. for the 3N140.

age to rf-amplifier stages. In this circuit, the rf
signal is applied to gate No.1, and the agc voltage to gate No.2.
The dual-gate MOS transistor is useful in
agc-supplied rf amplifiers because almost no agc
power is required by the device as a result of
the high dc input resistance indigenous to the
MOS transistor. Another advantage provided by
the MOS transistor is revealed by the ease with
which it obtains delayed· agc action and good
cross-modulation characteristics as a function
of agc. The applieation of agc bias to gate No. 2
while the bias on gate No, 1 is changed improves
the cross-modulation characteristics of the transistor as a function of agc applied.
81aslng fa compensate for temperature varla"ons

Unlike bipolar transistors, MOS transistors
exhibit a negative temperature coefficient for
typical values of drain current. That is, drain
current and dissipation decrease as temperature
increases, and there is no possibility of I D
runaway with elevated temperature. Unfortunately, transconductance and rf power gain also
decrease as temperature increases. Figure 14
shows curves of drain current and transconduct-

circuit of Fig. 12(a) were determined to provide
a transconductance of 9.5 mmhos at ambient
temperature, and the device temperature was
then varied through the range of -45 to
+ 100·C. The values of gate~No. 2-ro-source
voltage V G'8 required to maintain a constant
transconductance over the entire temperature
range, for Rs values of zero and 1000 n are
shown in Fig. 15.
VDS ·+I5V

9,.-g.!immhol
'-lkHI

--

Rs IN OHMS

?

~~

~

r"s°0

~

~r::\~

V

,.,

r - I--+20

/

RS-IOOO

RS·'OOO
-20

/

+40

RS;O- I--+60
+ 80
+ 100

TEMPERATURE--C

Fig. 15. Drain current and gate-No. 2·to·source volt·
age for constant ID as a function of temperature for
the circuit of Fig. 14 (b).

In a practical circuit, the required voltages
can be applied to gate No. 2 if R" or the combination of R 1 and R s , is a temperature-sensitive
resistor that is thermally linked to the MOS
transistor package. This thermistor network can
be designed to provide a desired voltage characteristic at gate No. 2 either to keep the transconductance constant or to permit some variation "'''!ith temperat!!!"e tl) cl)mpensat.e fl)!"
changes in other stages. The effects of temperature given in percentages on these other stages
may be summarized as follows: R,.-one ·percent; Ci,,-one percent; C/eedback-one percent;
Rout-plus 45 percent; Cou,-one percent.

TEMPERATURE _·c

Fig. 14. Drain current and transconductance as a
function. of temperature for the 3Nl40.

62

The data was measured on a 3N140 MOS transistor in the circuit of Fig. 12(a). Drain current was 8 mA, frequency was .200 MHz, and the
temperature varied from 0 to 100·C.

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ AN-4125

su.....my

..

All field-effect transistors may be biased similarly. Uniform quiescent operating points can be
easily aebieved in MOB field-effect transistors by
employing circuit designs that incorporate a
source resistance. For a given IDBB range, the
value of the source resistance inversely affects
the in-circuit ID spread. An increase in the value
of the source resistance minimizes. yariatioDs in
ID as a function of temperature. The dual-gate
MOB field-effect transistor is ideally suited for
use in gain-controlled stages; dual-gate transistor biasing can provide various types of age
action including temperature compensation to
assure constant output.

Adutow••d.......,.
The author thanks L.A. Jacobus and W.A. Harris for the c0mputations and computer run~" for tho curves shown in Fla. 10.
and R. Miller for collect1na much of tho data abown.

1I.'lograplly
RCA nata Sheet. Transistor RCA 40673. File No. 381.
I. R. Burns, "High-Frequency Charac:tcdstic:s of tho In!iulatcdGate Field-Effect Traosiator." RCA. Re~Iflv. Vol. XXVIII, No.
1, ScpL 1967. pp. 385-417.
L. J. Sevin, Jr., FIeld·Effect TransiStors, McGraw-HIli Book
Company, NeW York, N.Y.
C. H. Lee and S. Reich. "An FM Tuncr UslDl Singlc-Gatc
MOS Field-Effect Transistors as RF Amplifl-=r and Mixer," RCA
Application Note AN-353S.
B. F. McKeon. ''Crossmodulatlon Effects in Single-Gatc and
~~...a:~34~~ Field Effect Transiston," RCA Application

63

MOS Field-Effect Transistors

ffil(]5LJD
Solid State

Application Note
AN-4431

Division

"RF"Applications of the
Dual-GateMOS/FET up to 500 MHz
by L. S. Baar

The RCA dual-gate protected, metal-oxide silicon,
tield-effect transistor (MOS FET) is especially useful for
high-frequency applications in RF amplifier circuits_ The
dual-gate feature permits the design of simple AGC circuitry
requiring very low power. The integrated diodes protect th€!
gates against damage. due to static discharge that may develop
during handling and usage. This Note describes the use of the
RCA-3N200 dual-gate MOS FET in RF applications. The
3N200 has good power gain and a low noise factor at
frequencies up to 500 MHz, offers especially good crossmodulation performance, and has a wide dynamic range; its
low-feedback capacitance provides stable performance
without neutralization.
Gate-Protection Diodes
Fig. I shows the terminal diagram for the 3N200.

Gate No. I is the input signal electrode and Gate No.2
is normally used to obtain gain control. The back-to-back
diodes are connected from each of the gates to the
source terminal, lead No.4. If short duration pulses
greater than :j:1O volts, generated for example by static
discharge, are inadvertently applied to either gate, the
protective diodes limit these voltages and shunt the current
to the source terminal. Thus the gates, under normal
operating conditions, are protected against the effects of
overload voltages.!

LEAD
LEAD
LEAD
LEAD

i . DRAiN
2 - GATE NO.2
3 - GATE NO.1
4 - SOURCE. SUBSTRATE.
AND CASE

Operating Conditions

Typical two-port characteristics at 400 MHz including
both "y" and "s" parameters, are given for the 3N200 in the
RCA technical bulletin, File No. 437. This note makes use cif
the "y" parameters; however, designers who prefer the
alternate method can, by parallel analysis, make use of the
"8" parameters.
A recommended operating drain current (10) for the
3N200 is approximately 10 milliamperes with Gate No. 2
suffiCiently forward biased such that a change in the bias
voltage does not greatly affect the drain current. An
adequate Gate No. 2-to-source voltage (VG2S) is approximately +4 volts. The forward transadmittance (Yfs) increases
with drain current, but saturates at higher current levels. The
increase in RF performance at drain currents above 10
milliamperes is achieved only with less efficient use of input
power.
To establish the optimum operating conditions for a
type, consideration must be given to the range of variations
in characteristics values encountered in production quantities

of the type. 2 One important measure of type variation is the
range of zero bias drain current (IOS)- The current range
given in the 3N200 technical bulletin for lOS is from 0.5 rnA
to 12 mAo A fixed bias condition intended to center the
range of drain current at the desired level, still will produce
an operating drain current range of 11.5 milliamperes with a
resultant wide range of forward transconductance (gf.). The
drain current can be regulated by applying de feedback with
a bypassed source resistor (RS). A good approximation ofRS
(where 100 ~ IOS/2) can be calculated by the use of the
following formula', assuming tl).at VGIS vS. lOS is linear
over the current range under consideration:
I -)
RS'" ( - gfs(min.)

(6.IOS
- - - - I)

Eq.1

~IOO

'See Appendix

Fig. 1 - Terminal diagram for the 3N200.

12-70

64

_____________________________________________________________ AN-M31

where:
~IOS is the current range given in the 3N200 technical

bulletin
~IOQ

is the desired range of operating current

gfs(min.) is the minimum forward transconductance
at 1000 Hz
With the value of RS established. then the Gate-No.1
Voltage (VGl) can be calculated from the equation
VGI = VGlS + IOQ

Rs

Eq.2

where VGlS is estimated by:

voltage range of +2 to +5 volts. this characteristic may be
used to effect AGC delay of the device in order to maintain
the low noise figure until the RF signal is out of the noise-level
range.
Stability Considerations

Typical u y" parameter data as a function of frequency
are given in Table I. Maximum available gain (MAG) calculated from these data are also included to indicate ideal
gain performance (Le .• Yrs =0). The ability of the MOS FET
to approach these gain levels depends on the device maintaining stable performance at the required operating frequency.
There are several methods which may be used to test for
gain vs. stability. One of these methods. the Linvill Criteria
(C). is defined by the equation:

IOQ-IOS
Eq.3
gfs(avg.)

Eq.4
where:
gfs(avg.) is the average forward transconductance

To establish the Gate-No.2 Voltage (VG2). follow the
same procedure described for calculating the Gate-No. I
Voltage. except that a fixed VG2S of approximately 4 volts
is adequate.
If gain control is desired. apply a negative-going voltage
to Gate No.2. Because Gate No.2 has little control in the

CHARACTERISTICS

A value for C which is less than I indicates unconditional stability. Applying the 400-MHz values taken from
Table 1 to the Linvill Criteria yields a value of C = 0.615;
. substantially less than the value indicating unconditional
stability.

SYMBOL
100

FREQUENCY (MHz)
200
300
400

500

UNITS

y Parameters
Input Conductance

gis

0.25

0.8

2.0

3.6

6.2

mmho

Input Susceptance

bis

3.4

5.8

8.5

11.2

15.5

mmho

Magnitude of Forward Transadmittance

I I
Vfs

15.3

15.3

15.4

15.5

16.3

mmho

Angle of Forward Transadmittance

I.:!..fs

-15.0

-25.0

-35.0

-47.0

-60.0

degrees

Output Conductance

gas

0.15

0.3

0.5

0.8

1.1

mmho

Output Susceptance

bas

1.5

2.7

3.6

4.25

5.4

mmho

0.012

0.025

0.06

0.14

0.26

mmho

Magnitude of Reverse Transadmittance

I I

Angle of Reverse Transadmittance

/::!.rs

Maximum Available Gain

Vrs

MAG

-60.0

-25.0

0

32.0

24.0

17.5

14.0

20.0

degrees

13

10.0

dB

Table 1 - "y" Parameters from 100 to 500 MHz

65

AN-~1

______________________________________________________

The following equation for Maximum Usable Gain
(MUG)3 is:
2K

MUG =

I I
Yfs

IYrs I(I + cos 8 )

Eq_S

where:
8 = LYfs + LYrs
K = skew factor

device. The clamp is soldered to a feedthrough capaCitor to
provide an effective, very-low inductance bypass to RF
signals. This mounting arrangemerit still permits the use of a
source resistor for DC stability, and enables the case to
provide isolation between the input and output circuit in
addition to the isolation afforded by the shield.
TUNING

CAPACITOR C2

LYrs = angle of reverse transadmittance
LYfs = angle of forward transadmittance
The skew factor, introduced in this equation, is a safety
measure that establishes an arbitrary degree of skewing in the
frequency response which may be introduced by regeneration. A value of 0.2 for K has been established on the basis of
past experience. The value of MUG calculated at 400 MHz is
13.8 dB. This value of MUG is greater than the value of
MAG, again indicating unconditional stability, since MAG,
ignoring inherent feedback, is the conjugately matched gain.
Therefore, neutralization or circuit loading is not required to
insure stable performance, and the gain can approach MAG,
limited only by circuit losses.

INPUT BNC JACK

TOP VIEW

SHIELD

TUNING~

C::APACITOR Cz

CLAMP
FEEDTHROUGH
CAPACITOR C7

Reverse transadmittance (yrS> is composed of several
components, but the major ones are feedback capacitance
(Crss) and source-lead inductance (LS). Therefore, care must
be exercised in the application of the Yrs values, shown in
Table 1, at the upper end of the usable frequency range. The
3N200 utilizes a JEDEC TO-72 package that has 4 leads. The
data in Table I was compiled with the use of a socket which
contacts the leads of the 3N200 as close as possible to the
bottom of the package as specified by the JEDEC Standard
Proposal SP-I028 "Measurement of VHF-UHF "y" Parameters". The leads are shielded from each other to eliminate
stray capacitance between the leads, but some lead inductance is inevitable. If the device is soldered directly to the
circuit components using commercial production techniques
rather than by precise laboratory methods, then additional
source lead inductance can be expected. Also, some
additional capacitive coupling may result if the input and
output circuits are not completely isolated from each other.
Because the published Yrs value for the 3N200 is very
small, the circuit Yrs values may differ significantly from the
Yrs values shown in Table I and hence, may result in an
u..'lst2ble operatL'1g condition. It is impossible to provid~ ct~ta
for all possible mounting combinations, therefore, a recommended mounting arrangement is shown in Fig. 2. The
source and substrate in the TO-72 package of the 3N200 are
internally connected to lead No. 4 and the case. The
source-lead inductance can be reduced, if the case is used as
the source connection. Fig. 2 illustrates a partial component
layout in which the case is held by a clamp or other fingered

66

SIDE VIEW

Fig. 2 - Partial component layout of 400-MHz amplifier
circuit

The reduction of source-lead inductance provides in
addition to greater stability, a lower input and output
conductance. Table 2 shows the differences in "y" parameter
values at 400 MHz when measured with the source connection made to lead No. 4 (in accordance with the
published data for the 3N200) and when measured with the
case connected directly to the ground plane of the test jig.
The magnitude of reverse transadmittance is halved with a
significant change in its phase angle. The input conductance
is reduced by 30%, and the output conductance is reduced by
13%. A recalculation of the expressions for MAG, MUG, and
UnviIl Criteria (C) shows a significant improvement in gain
and circuit stability.
While it is difficult to provide accurate information on
the effects of shielding between the input and output
circuits, its effect can be demonstrated when all other
feedback components have been reduced to negligible values.
The circuit, shown in Fig. 3 (for component layout see Fig.
2), was measured both with and without a shield. The
maximum gain, without the shield, averaged 0.8 dB lower
than with the use of the shield.
When receiver sensitivity is an important consideration
in the design of an RF amplifier. a compromise must be
made in the circuit power gain to achieve a lower noise

_____________________________________________________________

CHARACTERISTICS

SYMBOL

FREQUENCY If) = 400 MHz
Normal

AN-~1

UNITS

Case
Grounded

Connection

Maximum Available Power Gain

MAG

13_0

15.7

dB

Maximum Usable Power Gain (unneutralized)

MUG

13.8

19.4

dB

Linvill Stability Factor, C

C

0.615

0.335

mmho

Input Conductance

9is

3.6

2.5

mmho

Input Susceptance

bis

11.2

11.7

mmho

Magnitude of Forward Transadmittance

I vts I

15.5

15.5

mmho

Angle of Forward Transadmittance

ills

-47.0

-40.0

degrees

Output Conductance

90s

0.8

0.65

mmho

Output Susceptance

bos

4.25

4.25

mmho

Magnitude of Reverse Transadmittance

I Vrs I

0.14

0.07

mmho

Angle of Reverse Transadmittance

/!..rs

"V" Parameters

14.0

49.0

degrees

Table 2 - "v" Parameters at 400 MHz with source connection to lead No.4 and with case connected to ground plane
of test jig
a relatively poor noise figure. As shown in Table 2, the input
conductance (gis) with the case grounded is 2.5 mmho. With
factor. A contour plot of noise figure as a function of
the reactive portion tuned out, the noise factor at power
·generator source admittance is shown in Fig. 4. Each contour
is a plot of noise figure as a function of the generator source
matched conditions is almost I dB higher than the optimum
conductance and susceptance. Data for the noise figure were
noise figure. However, matching to 5.0 mmho results
obtained from a test amplifier designed with very low
in a near optimum noise factor with a loss of only 0.5 dB in
feedback. Even though the area of very low-noise figure in
gain. In addition, impedance matching to high conductance
the curves in Fig. 4 cover a broad range of source admittance,
FREQUENCY(f)= 400MHz
AMBIENT TEMPERATUREITA)=25°C
.l!
impedance-matching for maximum power gain could result in
E

E

J.

+15V

I5

~12. 5

300kn

~

il
is

u

4dB

/

V

NOliE FActR

~

rW! D..
j
V::~
V
)
)
"'- \ ( ((0
I"-- ~ ~'- V ~ / V
s

7. 5

{

r-.

5dB
RS

,

'\

10

- 20 - 17.5 - 15 -12.5

-

-

-

-

10
1.5
2.5
GENERATOR SOURCE SUSCEPTANCE Ibisl -mmho

270n

o

Fig. 4 - Noise factor vs. generator source (input) admittance
Fig. 3 - 4OD-MHz amplifier circuit

(vis!

67

AN-~1

_____________________________________________________________

also benefits crossmodulation performance, as will be discussed in a later section_
Gate Protection Diodes
The diodes incorporated into RCA dual-gate MOS
FETs, for gate protection, have been designed to minimize
RF loading on the input circuits. The small amount of RF
loading results in only a fraction of a dB loss in power gain
and a negligible increase in the noise figure. The advantages
of diode protection, greatly outweigh the slight loss in power
gain, especially in an RF amplifier intended for the input
stage of a receiver.
In addition to the protection afforded in normal
handling, the diodes also provide in-circuit protection against
events such as: static discharge due to contact with the
antenna, delay in transmit-receive switching, or connection
of an antenna with an accumulated charge to the receiver.
Crossmodulation
Crossmodulation is an important consideration because
it is an inherent device characteristic where circuit considerations are secondary. Crossmodulation is the transfer of
modulation from an undesired signal on a desired signal
caused by the non-linear characteristics of a device.
Crossmodulation is proportional to the third-order term
of the expansion of the ID - VGS curve. It is normally
specified as the undesired signal voltage required to pr~duce
a crossmodulation factor of 0.01. The crossmodulation
factor is defined as the percent modulation on a desired
carrier by the modulated undesired signal divided by the
percent modulation of the undesired signa\.4
Inspection of the ID - VGlS curve of Fig. 5· offers an
insight to the possible crossmodulation as a function of
gain-reduction performance. When both channels of the
3N200 are fully conducting current, as shown by the VG2S =
4-voll curve, the device approximately tollows a square-law
chatacteristic. If the ID - VGlS curve was ideal, the
third-order term would be zero; but in practical cases, the

.i

if

./"'"

>''"'/
"

2'&1

,...II!
elJ//'r""

~

I~III
0

0.4

I

(VG1SJ

68

NO.2

CIRCUIT B

CIRCUIT C

Fig_ 6 - Biasing circuits using the 3N200

Curve A, Fig. 7 shows a curve of the undesired signal
with a crossmodulation factor of 0.01 as a function of gain
reduction. The curve indicates performance is poorest when
gain reduction is in the 3- to IS-dB region; this region represents a Gate No.2-voltage range of approximately 0.5 volt to
2 volts. The exception to the poor crossmodulation perform-

.,

1000

'"t;

"

i~

DESIRED SIGNAL(f OJ"S6MHl
UNDESIRED SIGNAL I'U). a5 MHz

: \\

I

.

6
a 100

~

;;

\\\.

~

1
2

~

vs. gate No. 1-to-source voltage

"1

I

GENERATED

.,,

~

FROM FIG 6,
CIRCUIT C
(HIGHER
INITIAL 10)

J--

v.-

~. 1--........
'.\

~.

...

~-

-- --'

~

/

-"-·~~~E C,
~~~R~~61

I

CIRCUIT C

I

1'---

CURVE A,
GENERATED
FROM FIG. 6
CIRCUIT A

~-

I"

,,

\\ J

I 1\

CURVE 0,

,---

w

GATE No.l-TO-SOURCE VOLTAGE IVGIS)- V

Fig. 5 - Drain current {/oj

GATE

CIRCUIT A

!

,
:I~I!I

-I

t

GATE

NO.2

~
~

~

Yoo

AGe
VOLTS

;

~

>;

•
•

Yoo

a

DRAIN-TO-SOURCE VOLTS (Vosl"IS

12.5

Yoo

z

AMBIENT TEMPERATUREITAI"25°C

•

third-order term and crossmodulation have some low values.
When the gain is reduced, by the application of bias to Gate
No.2, the square-law characteristic changes to a curve with a
knee. Sharp curvatures usually result in larger high-order
terms and poorer crossmodulation performance can be
expected at lower gain conditions. If in Fig. 6, Circuit A, we
assume a fIXed bias (VGIS) of approximately +0.4 volt, then
the expected variation in crossmodulation is determined at
the points where the ordinate at VGIS = +0.4 volt crosses
the curves. Crossmodulation performance at values ofVG2S
= +4 volls to cutoff is as follows: good (low crossmodulation) at +4 volts, poorer at +2 volts, poorest at +1 volt, and
again improves from zero volts to cutoff.

/1

-

1
\

\

... ""-CURVE B,
GENERATED
FROM FIG. 6,
CIRCUIT B

\

,

\.,":'

00

~

10

o

10

20

30
40
GAIN REDUCTION IdBI

Fig. 7 - Crossmodufation
circuits shown in Fig. 6

lIS.

50

60

70

gain reduction using biasing

--------------------------------------_____________________ AN-~31
ance in this· range is the sharp peak which occurs at the S-dB
level and is due to a curve inversion that takes place just prior
to the knee. Beyond the IS-dB level, crossmodulation
generally shows an improvement.
If Gate No. I is also reverse biased in conjunction with
Gate No.2 in the manner shown in Fig. 6, Circuit B, then the
overall performance is poorer because the Gate No. I voltage
wiI1 tend to follow the knee of each curve. This occurrence is
evident in Fig. 7, Curve B. If Gate No. I is biased as shown in
Fig. 6, Circuit C, the Gate No. I-to-Source voltage intercepts
the Gate No. 2 curves where the curvature is less severe,
indicating as shown by Fig. 7, Curve C an improvement in
crossmodulation performance. A further slight improvement
is possible by the use of a higher initial operating drain
current, which effectively moves the intercepts to the right
on each curve. This improvement is indicated in Fig. 7,
Curve O.
The curves in Fig. 7 establish that the biasing
arrangement which provides optimum crossmodulation
performance is the one in which Gate No. I forward bias
increases as Gate No. 2 controls the gain. This biasing
arrangement is easily accomplished by the use of a fIxed Gate
No. I voltage and a source resistor. As the Gate No.2 bias
voltage reduces the drain current, there is also a decrease in
source voltage and an increase in the Gate No. I-to-Source
voltage. The gate-to-source voltage ratings must not be
exceeded under any circumstances.
Summary
An RF amplifier, ideally, should provide high gain, a
low-noise fIgure, and low crossmodulation. The 3N200 offers
a good compromise in providing these three features. As
indicated in the section on "Stability Considerations" a
mismatch at the circuit input to a higher conductance level,
provides an improved noise fIgure. The same mismatch
condition also improves crossmodulation performance. The
input signal at the gate of the device, when mismatched as
indicated above, is lower than if it is power matched. The
same ratio applies to any undesired signal and, thus, reduces
the possibility of crossmodulation interference.

Appendix
The drain current of a device is established by the
relationship

If a source resistor is used, as shown in Fig. AI, the gate
No. I-to-source voltage is
YGlS=YGI-IORS
then
10=gfs(VGI-IO RS)+IOS
gfs YGi
10 = - - - +
I + gfs Rs

or

lOS
I + gfs RS

Fig. A 1 - Bias circuit using the 3N200

The typical curves in Fig. A2 show drain current vs.
Gate No. I-to-Source Yoltage as a function of lOS level.
These curves are almost linear when the typical operating
drain current is in the lO-milliampere region. For the
remainder of the analysis a linear relationship will be
assumed for the reqUired range of quiescent current. The
assumption of linearity dictates that gfs is a constant.
The required range of drain current is 102 - 101
where:
gfs YGI
lOS (max.)
10 2 = - - - + - - - l+gfsRS
l+gfsRS

~O

=ID2 - 101 -

lOS (max.) - lOS (min.)
l+gfsRS

~IOS

- --l+gfsRS

Solving the above equation for RS gives

where:
lOS = drain current
at:
YGlS=O, VG2S=+4volts.

where:
gfs is equal to the expected minimum value at the
required 10

69

AN-~31-----------------------------------------------------------

}t
1/

VOS·+I!5V
YG2S~+4V

..i

5

~~

12.5

II / I

0

§

5

5
2.5

0
-2

l

7
1/

?I
f!

fl J

II

V

/

II

J

V V

-I
0
I
GATE No.I-TO-SOURCE VOLTAGE (VGIS)-V

Fig. A2 - Drain current vs. gate No. '-to·source volrage

70

References:
1. L. A. Jacobus and S. Reich, "Design of Gate-Protected
MOS Field-Effect Transistors", RCA Application Note
AN4018
2. S. Reich, "Field-Effect Transistor Biasing Techniques",
EEE, Sept. 1970
3. R. A. Santilli, "RF and IF Amplifier Design Considera·
tions", IEEE Transactions on Broadcast and TV
Receivers, Nov. 1967
4. H. Thanos, "Crossmodulation on Transistorized TV
Tuners", IEEE Transactions on Broadcast and TV
Receivers, Vol. 9 No.3, Nov. 1963

OO(]5LJ[]

MOS Field - Effect Transistors
Application Note
AN-4590

Solid State
Division

Using MOS FET
Integrated Circuits in
Linear Circuit Applications
by S. Reich
Although the discrete metal-oxidHemiconductor (MOS)
lield-effect transistor (FET) has been available for many
(ears,1 its usage has been comparatively limited. Designers
~ave been reluctant to employ MOS FET devices in their
:ircuits because the gate oxide· in a discrete device is
IUInerable to damage by static electricity discharge~ en:auntered during handling and/or electrical transients found
in circuit applications. RCA engineers have now successfully
:ombined MOS FET and integrated-circuit (IC) fabrication
techniques to produce a simple monolithic MOS FET IC in
which back-ta-back diodes are connected in shunt with the
pte oxide to restrict the gate potential appearing across the
!lite oxide. The simple gate·protected IC's are of major
;ignificance because their immunity to damage by static
!Iectricity or by in-circuit transients is on a par of excellence
with that of other solid-state devices intended for similar
types of applications. Consequently. circuit deSigners can
now practically utilize the many unique MOS FET
:haracteristics. viz.. high input impedance. square-law
transfer characteristic. wide dynamic ;ange. dual·gate
:onfiguration. etc. For example. the square-law transfer
:haracteristic is especially desirable in the maintenance of
low cross·modulation characteristics in rf amplifiers).3 This
paper contains a brief review of the device theory, followed
'y a survey of some linear circuit applications for the MOS
FET Ie.

REVIEW OF DEVICE THEORY
The operating voltage applied to the MOS FET determines whether the device will function as a resistor, an
amplifier, or a diode. This section will provide a review of
these various MOS FET operational modes. Subsequently,
the useful operational modes will be employed in typical
applications.
Fig. I is a sketch, for zero gate-to-source voltage, of 10 as
a function of VOS for an n-channel depletion-type MOS
FET. Changes in the conductivity pattern are shown in the
simplified conductivity profile for each region of operation.
Ohmic - Region 'A' depicts an Io-VOS curve that is
characteristic of a resistance. The shape of this curve is a
function of VOS (drain-to-source voltage). Its slope is
governed by VGS (gate-to-source voltage). The VOS/IO

I

I I

;;-

II

II
1/

&
BREAKDOWN

~~Ioo--~-~-.IC~~~R~EN~T~)--+-f-~IF~O~RB~~

:::~:I ~
~
CIRCUIT CONDITION

~--~--------------~V~D~sl~M~A~X)r

DRAIN-TO-SOURCE VOLTAGE (Vos)

Fig. '-Regions of operation - n-channel depletion MOS
FEr.

characteristic i.e., its resistance value, is controlled by the
gate voltage.
As \tOS is increased, it produces an electrostatic stress in
the channel that modifies the channel conductivity as shown.
The channel is completely pinched off beyond VPo
(pinch-off voltage): Increasing Vos serves only to maintain
10 at a constant level.
Amplifier4 - For a fIXed gate-voltage, 10 is at a constant
level in region '8'. A change in VGS produces a change in 10;
thus in region '8' the device exhibits the transconductance
characteristic that is essential in amplifier operation (i.e., Gm
=dIO/dVGS).
"Forbidden" Region - Increase of Vos beyond its rated
maximum could produce avalanching in the drain-tosubstrate diffusion (diode). Therefore MOS FET devices
should not be operated in this region.
The duai-gate device is a serial arrangement of two
single-gate devices. This arrangement improves the MOS FET
performance by reducing capacitance from output to input
(drain to gate I), and provides an added control element that
adds to the versatility of the MOS FET_

3-71

71

AN-4590 ________

~

_______________________________________________

Gate Protection

A gate-protection system, which can be incorporated as
an integral part of the transistor structure, has been
developed for dual-gate MOS transistors. In devices that
include this protection system, a set of back-to-back diodes is
fabricated on the semiconductor pellet and connected
between each insulated gate and the source. (The low
junction-capacitance of the small diodes represents a
relatively insignificant addition to the total capacitance that
shunts the gate.) Fig. 2 is a profile drawing and schematic
symbol for
n-channel dualilate-protected depletion-type
MOS field-effect transistor. The MOS FET Ie metallization
pattern, including the connections to the drain, gate I, gate
2, source, and protective devices, all on a single monolithic
structure, is shown in Figure 3.
The back-to-back diodes do' not conduct unless the
gate-to-source voltage exceeds typically ±10 volts. The
transistor, therefore, can handle a very wide dynamic signal
'swing without significant conductive shunting effects by the
diodes Oeakage through the "nonconductive" diodes is very
low, typically I na). If the potential on either gate exceeds
typically +10 volts, the upper diode (shown in Fig. 2) of the
P,ir associated with that particular gate becomes conductive
in the forward direction and the lower diode breaks down in
the backward (Zener) direction. In this way, the back-toback diode pair provides a path to shunt excessive positive
charge from the gate to the source. Similarly, if the potential
on either gate exceeds typically -10 volts, the lower diode
becomes conductive in the forward direction and the upper
diode breaks down in the reverse direction to provld.e a shunt
path for excessive negative charge from the gate to the
source. The diode gate-protection technique is described in

a"

I. DRAIN
2 GATE 2
3 GATE J
4 SOURCE
(SUBSTRATE AND CASE)

'0'

CONNECTING PADS FROM PROTECTIVE
DtODES TO SOURCE

(:ig. 3-Monolithic protected dua/-gate MOS FET IC.

more detail in the folloWing section on integrated gate
protection.
Integratad Gate Protection

The advent of an integrated system of gate-protection in
MOS field~ffect transistors has resulted in a class of
solid-state devices that exhibits ruggedness on a par with
other solid-state rf device~. The gate-protection system
mentioned in the preceding section offers protection against
static discharge during handling operations withou t the need
for external shorting mechanisms. This system also guards
against potential damage from in-circuit transients. Because
the integral gate-protection system has provided a major
impact on ilie acceptability of MOS field~ffect transistors
for a broad spectrum of applications, it is pertinent to
examine the rudiments of this system.
Fig. 4 shows a simple equivalent circuit for a source of
static electricity that can deliver a potential eo to ihe gate
input of an MOS transistor. The static potential Es stored in

~RS

'b'
Fig. 2-Protected dual1lllte MOS FET IC: (a) schematic
diagram; (b) profile sketch.

72

_

'.
~1
LT,-CD___
Fig.. 4-Equivalent circuit for source of static electricity.

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ AN-4590

an "equivalent" capacitor Co must be discharged through an
internal generator resistance Rs. Laboratory experiments
indicate that the human body acts as a static (storage) source
with a capacitance CD ranging from 100 to 200 picofarads
and a resistance Rs greater than 1000 ohms. Although the
upper limits of accumulated static voltage can be very high,
measurements suggest that the potential stored by the human
body is usually less than 1000 volts. Experience has also
indicated that the likelihood of damage to an MaS transistor
as a result of static discharge is greatec during handling than
when the device is installed in a typical circuit. In an' rf
application, for example, static potential discharged into the
antenna must traverse an input circuit that normally provides
a large degree of attenuation to the static surge before it
appears at the gate terminal of the MaS transistor. The ideal
gate-protection signal-limiting circuit is a configuration that
atlows for,a· signal, such as that shown in Fig. 5(a), to be
handled without clipping or distortion, but limits the
amplitude of all transients that exceed a safe operating level,
as shown in Fig. 5(b). An arrangement of back-to-back
diodes, shown in Fig. 5(c), meets these requirements for
protecting the gate insulation in MaS transistors.

HANDLE THIS

'01

.,:]===
'el

'0'

-10

,.1

'01

Fig. 6-ldeal transfer characteristic of protective diodes (al.
and resulting waveforms in equivalent circuit (bl.

voltage of 20 volts. The transfer-<:haracteristic curves show
that the diodes will constrain a transient impulse to potential
values well below the ±20 volt limit, even when the source of
the transient surge is capable of delivering several hundred
milliamperes of current. (These data were measured with
I-microsecond pulses applied to the protected gate at a duty
factor of 4 x 10-3).

Fig. 5-Gate·protection requirements and solution.

Ideally, the transfer characteristic of the protective
signal-limiting diodes should have an infinite slope at
limiting, as shown in Fig. 6(a). Under these conditions, the
static potential across CD in Fig, 6(b) discharges through its
internal impedance Rs into the load represented by the
signal-limiting diodes. The ideal signal-limiting diodes, which
have lI!I infinite transfer slope, would then limit the voltage
present at the gate terminal to its knee value', ed. The
difference voltage, es appears as an IR drop across the internal
impedince of the source Rs, i.e., es Es - ed where Es is the
potential in the source of static electricity and ed is the diode
voltage drop. The instantaneous value of the diode current is
then equal to eslRs. During physical handling, practical peak
values of currents produced by static-electricity discharges
range from several milliamperes to several hundred milliamperes.
Fig. 7 shows a typical transfer characteristic curve
measured on a typical set of back-to-back diodes used to
protect the gate insulation in an MaS field-effect transistor
that is nominally rated for a gate-to-source breakdown

"

10

oa
0,&

0 .•

~i

Ii
;!

:1
ru

=

-0.4

-0.'
-0.'
-1.0

-1.2

Fig. 7- Typical diode transfer characteristic.

73

AN4590 ______________________________________________________

Electrical Requirements
The Triod.Connectecl Protectad Dual-GatelC
The previous discusSion points out that optimum
The dual-gate MOS FET can be connected so that it
protection is afforded to the gate with a signal..Jirniting diode functions as a single-gate device, as shown in Fig. 9. The
that exhibits zero resistance (i.e., an infinite transfer slope triodeo(;(Jnnected configuration has curve tracer (drain
and fast turn-on time) to all high-Ieve! transients. In addition, family) characteristics that look like the 'real' triode. The
the ideal diode adds no capacitance or loading to the rf input curves in Fig. 10 show that characteristics for the triode MOS
circuit. This ideal diode in practice simply does not exist, but FET (3NI28) and the triode-connected dual-gate MOS FET
integrated circuit techniques made possible the development (3NI87) are essentially simnar.
of a gate-protected'MOS FET IC that is close to the ideal.
For example, Fig. 8 shows typical 2OG-MHz input characteristic changes brought about by the addition oC the integrated
circuit diodes. Their effect on power gain and noise factor is
shown by the data given in Table 1. These data indicate that
\
I _I
J
there are no discernible reductions in power gain and a trivial
,
I
\
/
noise Cactor increase oC about 0.25 dB.

I,
(

I

I~r-----------------------------_,
INPUT RESISTANCE
--- INPUT CAPACITANCE
IZOO
'-ZOOMHI

*...

1000

"~~

ill"'"

~

tJ
8.0 ~

-------...----- --

c

7.0

GAT[·PROT[CTED MOS FET Ie

I-

.00
200

0

,...,

10

12

"~

5.0

__ - - .......UNPROTECTEO MOS FET

DRAIN CURRENT ClO)-mA

i!
I-

6.0

...--

..-----

1,4.0

"

Fig. 8-Input resistance and capacitance as functions of drain
current for the MOS FE T with and without diodes.

Table I - Power Gain and Noise Factor at 200 MHz
UNIT

POWER GAIN
(dB I
DIODES
DIODES
IN
REMOVED

1
2
3
4
5
6
7
8
9
10

74

16.3
18.8
16.5
16.3
17.7
17.2
17.1
17.9
18.5
17.3

16.4
18.5
16.2
15.7
17.8
17.5
17.0
18.0
18.5
17.3

NOISE FACTOR
(dBI
DIODES
IN
3.7
2.4
3.3
3.9
2.6
2.8
3.3
2.9
2.4
3.2

DIODES
REMOVED
3.4
2.2
3.0
3.4
2.4
2.5
3.2
2.6
2.3
3.0

-

4

I

--

4

Fig. 9-DUJlI-gate MOS FET Ie in II ring/__ re configuration.

':.,

_____ GATE· PROTECTED liDS FET Ie

~'\

\:==/

TrioR-Connectad-Dwlce ChI...:teristics
Some useful triode-connected-device characteristics are
provided in Table 11 in the Corm of comparisons with
dual-gate and single-gate devices. It should be noted that the
differeltcIC in lOS level between the 3NI87 and the 3N200
carries over to their triode-connected versions. A curve
showing lOSS for triode connection versus lOS for the
dual-gate configuratioro (i.e., VG2S = 4 volts) is shown in Fig.
11.
A plot of the triode-connected dual-gate transCer characteristics (10 vs. VGS) is shown in Fig. 12; similarly, gCs
curves are given in Fig. 13 as functions of 10. Curves for
typical dual-gate operation are available in commercial data
sheets. 5 ,6
Dual gates connected as tetrodes and triodes were
evaluated for Ro(ON) where 'on' resistance compares
favorably with single-gate devices. Typical variations in
Ro(ON) as a function of gate voltage are shown in Fig. 14.

1
110
"0

!:!
~
z

...

a'"

z
;;
~ 0

a

a
20
DRAIN-lO-SOURCE VOLTAGE (Vos)-V

DRAIN-lO-SOURCE VOLTAGE (VDS)-V

'01

'01

20

Fig. fO-Drain families: fa) for triode-connected protected
dual-gate device: fb} for triode.

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ AN-4590

Table II - Comparison of Typical Electrical Characteristics for Triode-Connected Dual-Gate, Dual-Gate,
and Triode MOS FET Devices
CHARACTERISTIC

CONDITIONS

TRIODE-CONNECTED
3N187

lOS

g"

3N200

DUAL-GATE CIRCUIT"
3N187
3N200

SINGLE GATE
3N128

UNITS

V OS -1Sv

6.0

2.0

15

{VOS -1SV
10"10ffiA

7.0

8.5

12

15

·2.0

·1.0

·2.0

·1.0

-1.5

V

2.0

2.0

1.0

1.0

10-4

nA

10.0

10.0

6.0

6.0

5.5

pF

0.5

0.5

0.02

0.02

0.2

pF

2.0

2.0

2.0

2.0

1.4

pF

15

rnA

mmho

f'l kHz

VGlSIOFF)

{V oS "lSV
10 "SOJIA

IGlSS

Ciss

f

VGs':!Sv
OS "lSV
10"10mA
f'" 1 kHz

COS.1SV
Crss

IO"'"10mA

f -I kHz

Coss

rOS.1SV
10 -lOrnA
f -1 kHz

ROSION)

{VOS'1 v

160

250

100

150

300

ohm

VGS=O
·V G2S

=4 v except for IGSS measurement, where VG25 '" O.

It should not be inferred from these comments that all configurations shown in Figs. 15(a) and 15(b), the MOS
single-gate applications can be handled by the protected device is normally conductive, i.e., eo is low. A negative
dual-gate device. The advent of MOS FET opened application gating-pulse turns off the MOS device so that approximately
areas in which circuit requirements imposed leakage·current 50 percent of eg appears at the output terminals. Circuit (a)
limits in the picoampere range. For these applications the features the use of an additional control potential (VG2). A
present generation of protective gate devices do not suffic~ dc potential may be applied as shown to the second gate,
and it is necessary to employ a "classical" MOS FET type thereby establishing the value of desired channel 'on'
(e.g., 3N128) and exercise precautions against gate-insulation resistance (ROS). Alternatively, circuitry can be arranged so
puncture.
that the second gate can function as a "coincidence-gate",
i.e., to reduce eo to a low value, a positive-going pulse must
SURVEY OF LINEAR APPLICATIONS
be applied to gate 2 simultaneously with a positive-pulse to
This section shows typical circuit arrangements. Some are gate 1.
documented, and others are design ideas for use of dual·gate
All circuits in Fig. IS make reference to Note (A). The
MOS FET's with integrated diodes in applications using circuit diagrams show a "jumper" connected between two
tetrode and triode-connected configurations.
terminals in the drain-to-ground-return circuits. The circuits
as drawn assume a peak generator level (eg) of less than 0.2
Choppers
The circuits shown in Fig. IS use the dual-gate MOS FET volts. Should the signal exceed this value, it is possible that
Ie in. chopper or gating circuits. In the shunt·drcuit the "n_p" parasitic diode between the drain and semi-

75

AN-4590 _________________________________________________________

~r,~N~.~7~------~--------~

.1

TRKJOE CONNECTED

c

•I
E20

I
Y
I..

II

I•

w

t
8
H

~~Z~~-_~,---L~O~-L--~-J
GATE-YO-SOURCE

VOLTAG£ 1Yos'-V

(al

IS "'''"N-:.-O.,.O------------------,
TRIODE CONNECTED
4

10

12

I DSS t TRIODE - CONNECTED)- IRA

Fig. , '-Correlation of zero·bias drain current for the pro'
tected dual·gate device in terrode (/
and triode (/OSS)
configurations.

os!

conductor substrate will be driven into conduction and load
the signal. This contingency' may be obviated (with a
simultaneous improvement in allenuator linearity) by con~~.--~-_~,~~--O~-L--~-J
necting a suitable dc potential in lieu of the "jumper", so
GATE-YO-SOURCE
that a positive potential is applied to the drain. The
VOLTAGE '''Gs1-V
magnitude of this voltage should equal or exceed the peak
Ibl
value of the rms signal f~om ego
Circuits shown in Figs. 15(c) and J 5(d) function in a ,Fig. 72- Triode-corinected protected dual·gate MOS FET IC
manner opposite to those described above, i.e., output transfer characteristics.
voltage appears at eo in the absence of a gating signal.
Consequently, a negative gating signal· reduces the level of eo. Constant·Current Sources
The characteristics of the MOS FET 1(' in the region
The dual-gate configuration can be made into an 'or' circuit,
i.e., a negative signal applied to gate 2 of sufficient magnitude beyond pinch·off make the device suitable for constantto override VG2 will also reduce the le.vel at eo.
current supplies, as illustrated in Fig. 17 (using a "triodeconnected" dual-gate device).
Attenuaton
The dual-gate device may be used to obtain higher values
Fig. J6 shows the dual-gate device in an attenuator of current-regulation with the circuit depicted in Fig. 18. A
circuit. In Fig. 16(a) both gates are used as control elements. supply circuit with a maximum output voltage capability of
This type of circuitry is particularly attractive when control about 4.0 to 5.0 volts is required for VG2. Values greater
of the allenuator must be located at some remote location. A than this will have negligible effect on output current
dc potential on gate J has greater control on the channel control.
resistance than is the case for gate 2. Thus an arrangement
The circuits in Fig. 19 use the MOS FET constant-current
can be used whereby gate 2 provides. ~ ufine" attenuatQr characteristic to make 2' regulated constant-voltage reference
adjustment and gate J controls "course" adjustment. The source by feeding lOS through a fixed-value resistor.
circuit in Fig. 16(b) shows the dual-gate device in a
In any typical amplifier application using the MOS FET
triode-connected allenuator circuit. Curves showing typical device, e.g., in Fig. 20, the voltage developed across a
vari&tions in resistance as a function of gate-voltage were bypassed source resistance provides a well-regulated fixed
reference voltage (if the amplifier stage is not s\lbjected to
given in Fig. ~ 4.

76

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ AN-4590

)000,-----------,

10,------------,

RCA 3NI87
TETROCE

3NI87
TRIODE CONNECTED
~

~ 800
o
I

~
.!!

o 600

.!O.

...

!~

400 \

~ 200~ " - ~-----I

12

-I

DRAIN CURRENT lID) - mA

GATE - TO-SOURCE VOLTAGE I VGS) - V

la)

1000,-----------,
RCA 3NI87

TRIODE - CONNECTED

10,------------,
3N200
TRIODE CQNNECTI:":O

~

~

800

o

Vas -0
G2 TIED TO GI

I

...

~

400

~

z

~

200

GATE - TO-SOURCE VOLTAGE (Vas 1- y

o

12
DRAIN CURRENT 110) - mA

Ibl

Fig. 13- Triode-connected protected dual·gate MOS FET IC
transconductance characteristics.

varying liias conditions, silch as those encountered in
connection with AGC). When a reference voltage is obtained
in this manner, it is advisable to feed it to other circuitry
through an adequate decoupling network.
General-Purpose Amplifier Circuits
Fig. 21 shows three basic single-stage amplifier configurations that utilize dual-gate-protected MOS FET IC's as triodes
and as tetrodes in common source, common~drain. and
common-gate circuits. Each configuration has its own
particular advantages for specific applications. The dual-gate
device has an added advantage in any of these configurations
in that gate 2 provides (a) reduced gate-to-drain capacity by

Fig. 14-"ON" resistance as a function of gate voltage for
tetrode- and triode-connected protected dual-gate MOS FET
IC's.

an order of magnitude, and (b) a convenient means for
controlling the gain of the stage by adjusting the dc potential
applied to gate 2.
A dual-gate device is shown in Fig. 22 as a shunt-type
altenuator to control the input level to a source-follower.
The source-follower uses the dual-gate MOS FET with gate 2
available as a control for adjusting the gain of the
source-follower. The jumper in the ground return path of the
generator can be used to insert a positive voltage on the drain
for the reasons explained above.
Fig. 23 shows a circuit using the "triode-connected"
dual-gate device in a simple 20-dB preamplifier for extending
the sensitivity range of an oscilloscope or ac voltmeter. It can
also be used in audio circuits as a phono preamplifier or
microphone preamplifier. It is shown as self-contained, i.e.,

77

AN-4590 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

lOOK

lOOK

e.

'.

(NOTE A
SEE
TEXTI

(NOTE A
SEE
TEXT)

\.,

\.1

Fig. 15--Typical chopper circuits using protected dualgate MOS FET Ie's. (a) shunttype using tetrode connection;
(b) shunt-type using triode
connection; (c) series-type
using tetrode connection; (d)
series-type using triode connection.

VG2

\"

\el

+Vcc

c

!---O

+"cc

c
(---0

I bJ

'Fig. 16-Attenuator circuits using the protected dual·gate
MOS FET Ie: lal variable series· type attenuatar with coarse
and fine controls; Ibl variable series· type attenuator using
triode-connected coniiguration.

78

with its own power supply and a by-pass switching
arrangement.
In Fig. 24 "triode-connected" MOS FET devices are used
in a simple differential amplifier configuration in which the
"triode-connected" gates of the two devices are biased from a
single source (the junction of R I and R2). This arrangement
is possible because the 3N! 87 has a typical gate current
(IGSS) in the triode configuration of 2 nanoamperes.
Therefore, the bias can be supplied through R3 with a
negligible .voltage offset. Resistor RS is used to null out the
effects of slight differences in device characteristics so that
the offset-voltage at eo can be set to zero.

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ AN-4590

+o-------------------~~~

I, I
10

"-0
1,1

Fig. 19- Voltage-reference circuits using protected dual·gate
MOS FET IC: (a) as triode; (b) as terrode.

R-Iooon
20

6mA-

R'"-zzon

3mAQ.SmA-

101

-II.;...._-i_____"o.,;.:2"-10::.;0:.;.:...-_ _ _-1
20

Fig. 17-Constant·current supply using protected dual·gate
MOS FET IC in triode configuration: (a) basic circuit;
(b) typical
vs. Vin for RCA·3N200 in the basic circuit;
(c) typical
vs. Vin for RCA·3NI87 in the basic circuit.

'0
'0

The circuit in Fig. 2S shows another differential amplifier
configuration, in which the offset voltage at eo can be set to
zero by means of appropriate potentials supplied to the No.2
gates, adjustment being provided by R6.
The circuit shown in Fig. '26 is a frequency-selective
amplifier intended for operation within the audio frequency
range of 10 Hz to 20 kHz. Frequency-selective circuits are
used for selective coding, i.e., in garage-door openers,
narrowing the bandwidth response in CW receivers to.

~-l

eliminate unwanted side bands, and in systems requmng
some form of keying impulse (e.g., synchronizing the
narration in a tape recorder with slides).
The frequency-selective circuit shown is an audio
amplifier with a twin-"T" RC filter circuit in its output. This
network provides regenerative feedback to the input circuit
at an audio frequency predetermined by the selection of
capacitors CS, C6, and C7. The peaking control R7 fine-tunes
the twin_UT" for the desired frequency of operation, and
potentiometer R8 adjusts the level of feedback for desired
performance. The circuit as shown in Fig. 26 is selective at an
audio frequency of 1200 Hz. Table III below lists values of
the bridge capacitors for operation at other frequencies.

RF Amplifiers, Oscillators, and Mixers
The circuit in Fig. 27 is a converter used to convert
100MHz WWV broadcasts to I.S MHz for reception on a
standard broadcast-band receiver. The MOS FET IC is used in
the dual-gate configuration as a mixer and is triodev+

v+

10

VI.

VOLTAGE

+-.....--'Vvv-...--o REFERENCE
SOURCE

RL

"s
. v+

Fig. 18-Protected dual·gate device as a constant-cu"ent
source.

rl~F

Fig. 20- Typical amplifier using bypassed source resistor as a
voltage source.

79

AN~90

________________________________________________________

DUAL GATE:

SOURCE FOLLOWER
,.....-------,

I
I
I

I

I

TRIODE CONNECTEO

10.01 I
I ~. I
, I
I
~Hl1411
I
I

I

____ -'I

I
I
I
I
, I
I

YDD

R

I I

I

I
IL _____ _

± Yo CONTROL

tol

Fig. 22-Shunt-type attenuator' controlling input level to
source-follower.

i~::r~~e~---, GAIN AD.t.

f-:-1
I

10 K

J

O.l,..F

1"
1000
TRIODE CONNECTED

=
INPUT

ON

~
0

•

18

=
'"

v-=-

OUT

J-~--l:
OFF

l

Fig. 23-Protected dual-gate MOS FET Ie preamplifier.

DUAL GAT[

TRIODE CONNEt TEO

'"
Fig. 27- Three basic single·stage amplifier configurations that
use protect11d dual·gate MOS FET Ie's as triodes and tetrodes:
fa) common source; fb) common drain; fc) common gate.

80

Fig. 24- Triode-connect11d MOS FET Ie's in a sImple differential amplifier circuit.

________________________________________________________ AN4590

VDD

".

",

".
Fig. 25-Protected dual·gate MOS FET Ie's in typical differential amplifier circuit using gate 2 for balance control.

IN914

0.005

.'
1+ 20 Y

Fig. 27-10 MHz·to·I.5 MHz converter for WWV reception.
0'

flO'

"

.--••-0-.--.....'-'.-,--c-.'" ••0
1500 pF

PEAKING
toNT-'L

pF

OUlP

.
-+-+_..... ..

INPUT

.. 0

L ___

o

/

~'·

SELEctVITY
CONTROL

B-

Fig. 26-Selective audio·frequency amplifier.

Table III - Capacitor values for Fig. 26

(Hz)

C5,C6
(pF)

C7
(pF)

150
300
600
2400
4800
9600

5,600
2,700
1,300
330
160
82

12,000
6,200
3,000
750
360
180

FREQUENCY

I

f---------O

connected in a crystal oscillator circuit. MOS FET
characteristics are very attractive for use in highly stable
oscillator circuits because the inherent reactive components.
Ciss and Coss• are relatively invariant over a very wide
temperature range. Additional types of oscillator circuits in a
number of different arrangements are shown in Fig. 28.
It is also feasible to use the MOS FET IC as a keyed
oscillator. by utilizing a circuit arrangement shown in Fig .
29. A negative voltage at gate 2 will key the oscillator.
Additionally. the level of the oscillator output can be
controlled by variation of RL. It should be understood that
any of the oscillator configurations shown above are
adapta~le to the circuit arrangement in Fig. 29.
A dual-gate-protected MOS FET IC is used in Fig. 30 as a
regenerative amplifier/detector. The circuit is basically an
amplifier with controlled feedback adjusted to the verge'of
oscillation. as shown in Fig. 30. Gate 2 provides a convenient
means to adjust the amplifier gain to the requisite level.
Detection is accomplished in the gate 1 input circuit by the
interaction of the diode in parallel with the 100-kilohm
resistor and the 270-picofarad capacitor.
A typical circuit that utilizes the MOS FET IC in the pix
IF section of a TV receiver is shown in Fig. 31. This circuit
utilizes gate 2 for AGC. The reverse AGC bias7 applied to
gate 2 in the circuit of Fig. 31 has the secondary effect of
making gate 1 move
a positive direction. Evaluations of
the relationship between AGC and crossmodulation show
that it is desirable to allow the voltage between gate I and
the source to move in a positive direction when gate 2 is
reverse-biased. Various circuit arrangements have been used

in

81

AN4590 ____________________________________________________

to achieve this action. Reference to a more comprehensive
review on crossmodulation as a function of bias is given in
the bibliography),]
.

lOOK
4.11(

lOOK

VD

'DO

"

0.1,...
.-TA""TlcniotJ#TI.IUd~

eOUENDfII COIL

C",,,,,TOt

,.,

TO ",
AMPLIFIER

'"
Vo

SN.I'

3N'I'

0.001".,

Fig. 3D-Protected dual·gate MOS FET IC regentlntive , .

ceiver.
c'

C"
.600

Co

~~

C"

Co

RFC

Fig. 28-0scillator circuits using MOS FET /C's: (al and (bl
Hartley oscillators; (cl and (dl Co/pirrs oscillators.

VG2

20 K

A typical circuit for an FM tuner is shown in Fig. 32. The
biasing arrangement for the rf stage incorporates proVisions
for AGC. The circuit in Fig. 33 is an rf amplifier designed for
200-MHz operation. The typical power gain for a 3N187 in
this circuit is 18 db, with a noise factor of 3.5 dB.
Typical circuits for a TV tuner are shown ill Figs.
34(aHd). Fig. 34(a) is the rfstage operating at a current level
of approximately to milliamperes. Gate I is about 2 volts
above ground potential. When AGC applied to gate 2 is
advanced the drain current decreases, with a consequent
reduction in voltage drop across the 27(N)hm source
resistances. 7

180)(

~~~~Gcr--~A1~--~~-JVV~--1---~)+

Voo

LEvEL
CONTROl-RL
lOOK

11011.

1-

100

REVERSE
AGe

1001(

IF AMPLIFIER

1F

TDN. .T

IF STAGE

'DK

00.

11"

~
~

.6.

1"

DOS

*

AU AfSISTANC£ ..awES ARE IN OH.S

TAP AT 20% OF TURNS fROM COLO END OF COIL
C·2pF/METER

Fig. 29-Gate·keyed oscillator using MOS FET IC.

82

Fig. 31- TV IF amplifier stage utilizing RCA-40820 MOS
FET IC.

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ AN-4590

REVERSE
AGC

+5V

",

~--_4~~----------~~-o+I.V

R6

RCA

Rg

40244

Ct, C9•.C15 = Trimmer capacitor, 2 to 14 pF
C2. C7. C16 = Ganged tuning capacitors. each section". 6 to 19.5 pF

ca. C6. C14. C17. C22 = 2000 pF. ceramic
C4. C5'" 1000 pF. ceramic disc
ca. eta· O.OlIJF. ceramic disc
eto = 3.3 pF, NPO ceramic

C.ll = 270pF
et2"" 500 pF. ceramic disc
et3 = 3 pF. NPO ceramic

eta =68 pF. ceramic
C20'" 50 pF. ceramic
e21 - 1200 pF. ceramic
L1 ,. antenna coil; 4 turns of No. 18 bare copper wire; inner diameter,
9/32 inch; winding length. 318 inch; nominal inductance.
O.86,uH; unloaded Q. 120; tapped approximately 11/4 turns
from ground end; antenna link approximately 1 turn from
ground end

L2
L3

;a

=

r1 interstage coil; same as L1 antenna link
rf choke. 1 JlH

L4

oscillator coil; 3 1/4 turns of No. 18 bare copper wire; inner
diameter. 9/32 inch; windi'lg length, 5/16 inch; nominal
inductance, O.062,."H, unloaded Q, 120; tapped approximately
1 turn from low end
Rl. R10 = 0.56 meBohm. 0.5 wall
R2 = 0.75 megohm. 0.5 wall
R3 =0.27 megohm. 0.5 wall
R4. R13 = 270 ohms. 0.5 wall
R5 • 22000 ohms. 0.5 watt
R6 = 56000 ohms. 0.5 watt
R7 "" 330 ohms, 0.5 watt
R8. R12 = 0.1 megohm. 0.5 watt
R9 = 4700 ohms, 0.5 watt
Rll = 1.6 megohms, 0.5 watt
Tl = first if (10.7 MHz) transformer; double·tuned with 90 per cent
of critical coupling; primary: 15 turns of No. 32 enamel wire,
space wound at 60 turns per inch on O.25·by-O.S-inch slug;
secondary: 18 turns of No. 36 enamel wire, close wound on 0.25by-O.25 inch slug; both coils wound on 9/32-inch coil form.
::z

Fig. 32-FM tuner using RCA·40822 and RCA-40823 MOS FET IC's for the rf amplifier and mixer stages.

~Oy

I

21 K

47 K

I.S K

I

I
I

L ___

,OoO ~----1000

1000

' -__-'V36vK\.-....____.:;,12"'0>AK;-___-+___ ~ge

"Ferrite bead (4); Pyroterric Co. "Carboni J" a = 3N187
0.09 in. 00: 0.03 in. 10; 0.063 in. thickness_ .,. Disc ceramic
All resistors in ohms
• Tubular ceramic
All capacitors in pF
Cl = 1.8-8.7 pF variable air capacitor: E.F. Johnson Type 160-104,
or equivalent.
C2 = 1.5-S pF variable air capacitor: E.F. Johnson Type 160·102, or
equivalent.
C3 = 1-10 pF piston-type variable air capacitor: JFo Type VAM-Ol0;
Johanson Type 433S. or equivalent
C4 =0.8-4.5 pF piston type variable air capacitor: Erie 560-013 or
equivalent.
L1 = 4 turns silver-plated 0.02-in. thick, 0.07S-0.085-in. wide, copper
ribbon, internal diameter of winding = 0.25 in., winding length
approx. 0.08 in.
L2 = 4% turns silver-plated 0.02-in. thick, 0.085·0.095-in. wide,
5/16 in. I D. Coil = .90 in. long.

Fig. 33-200-MHz amplifier usjng the RCA-3N1S7 MOS FET IC.

83

AN-4590 ___________________________________________________________

1000 pF

820K

RFC

~

AGe

'OK

v.

~

IOOQpF

1000 pF

J
,7~~~TI I
TRAPS

=

~

HI--............!--.JI-O
IZOK

1000

FROM~
RF
AMP

,F

'90"

9pf

~

IF

MIXER

12 pF

OUT

0--I1----<4---+hll~
(0'

39
,F

~

,,'

'"

'"
Fig. 34- Typical circuits using protected dual-gate MOS FET
IC's in a TV tuner for la) rf stage, Ib) mixer with rf on gate
" oscillator on gate 2; Ic) mixer with both rf and oscillator
on gates 1 and 2; Id) mixer with rf on gate 2 and oscillator
on gate 1.

Because the voltage on gate I is fixed. the effect of
applying AGe is to make the gate-to-source voltage drift in a
positive direction as a negative gate 2 (AGC) voltage is
applied. In these cases, as in the earlier IF system shown in

84.

Fig. 31, this circuit arrangement optimizes tuner performance for crossmoduiation. 2
The rf stage in Fig. 34(a) can work into any of the mixer
circuits shown in Figs. 34(b). (c). and (d).

___________________________________________________________ AN-4590

Fig. 34(b) is a mixer circuit arrangement with oscillator
injection into gate 2 and the rf signal applied to gate I. Fig.
34(c) utilizes gate I and gate 2 as the input elements for both
rf signal and oscillator. Fig. 34( d) shows the rf signal applied
to gate 2 and oscillator injection on gate I.
Each of the above circuit arrangements has its own
desirable characteristics, and the subject of mixer performance deserves a much more detailed discussion than can be
accommodated here. In this context it is intended to
demonstrate feasibility in terms of circuit arrangements.
A milCer circuit with compo".,,! values used in the
laboratory for measuring conversion power gain from 200 to
44 MHz is shown in Fig. 3S. 8

Protected dual-gate MOS FET's have been used in
applications operating at frequencies up to SOO MIIz. They
are useful in such uhf applications as rf amplifiers and mixer
circuits. For example, the RCA-3N200 has the capability to
proVide a typical rf power gain of 12.5 dB with 4.5-<1B noise
factor at . 400 MHz in a common-source configura tion
without the need for neutralization. A circuit with this
capability is shown in Fig. 36.

1--------,-------'
33 CER
1 LEADLESS

3N.00
,...

1 DISC·

•

1\

! 47~I

1.

OUTPUT

I

-=-

I

CER DISC.

re3 300
~

I
.....

t-+":\r'---~-~*~

I

I

INPUT

I

470 CERAMIC
TUBULAR
STANDOFF
RFe
OHMITE

K

1

I

1

Z460

I

I

I
I

1

L __ ~_(~(IOOO :;j,.._L ___ _ ~_..J
1-....j~

_ _ _ _ _ _ _ _.., VDS
.f15V

AU resistances in ohms
AU capacitances in pF
Cl. C2 '" 1.3-5.4 pF variable air capacitor: Harnmerland Mac 5 type
or equivalent
C3'" 1.9-13.8 pF variable air capacitor: Hammerland Mac 15 type
or equivalent
C4 .. Approx. 300 pF - capacitance formed between socket cover &
chassis
C5 '" 0.8-4.5 pF piston type variable air capacitor: Erie 560·013 or
equivalent
Ll. L2 = inductance to tune circuit

Fig. 36-Using the RCA-3N2oo MOS FET IC in a 4(J().MHz
amplifier.

... Disc. ceramic .
• Tubular ceramic.
All resistors in ohms
All capacitors in pF
Cl. C2 = 1.5-5 pF variable air capacitor: E.F. Johnson Type 160-102
or equivalent.
C3 = '-10 pF piston-type variable air capacitor: JfO Type VAM·Ol0.

Johanson Type 4335. or equivalent.
C4"" 0.9-7 pF compression-type capacitor:
equivalent

ARea 400 or

L 1 .. 5 turns silver-platea 0.02" thick. 0.07" ·O.OS" wide oopper
ribbon. Internal diameter of winding"" 0.25"; winding length

appro". 0.65", Tapped at ,·1/2 turns from Cl end of winding.
L2 = Ohmile Z·235 AF choke or equivalent.
L3 = J.W. Miller Co. '4580 0.1 ,uH AF choke or equivalent.
NOTE:
If SOn meter is used in place of sweep detector. a low pass
filter must be provided to eliminate local oscillator voltage
from load.

Fig. 35-Mixer circuit for 200 MHz-to-44 MHz conversion,
using the RCA-40821 MOS FET IC.

CONCLUSIONS

The preceding discussions outlined numerous practical
applications that utilized the unique technical features of the
RCA protected dual-gate MOS FET IC. A summary of these
technical features includes:
I. Wide dynamic range - MOS FET IC's will handle both
positive ancj negative signal excursions.
2. Crossmodulation and spurious response performance is
inherently better than with other active devices such as
bipolars and single-gate FET's.
3. The very low gate-leakage permits AGC circuitry with
virtually no power requirements.

85

AN-4590 ________________________________________________________

4. Two input control elements make the device adaptable for
mixers, remote-<:ontrol gain circuits, coincidence gate
circuits, etc. The device can also function as a triodeequivalent when the two gates are connected to a single
terminal.
5. An exceptionally high transconductance.
6. Negative temperature coefficient for drain current, so that
thermal runaway is virtually impossible.
7. Extremely low feedback capacity, typically 0.02 picofarad; this means very low oscillator"feedthrough froin the
mixer stage back to the antenna.
8. The low feedback capacity enables the dual-gate MaS FET
IC to provide good rf power gain in common-source
amplifiers without the need for neutralization.
9. In addition to the above features, the new MaS FET IC
provides protection against static electricity discharges
encountered during handling and/or in circuit applications.
This protection was achieved with insignificant compromises in overall device performance.

86

BIBLIOGRAPHY
I S.R. Hofstein and F.P. Heiman, "The Silicon Insulated
Gate Field-Effect Transistor", Proc. I.EEE, Vol. 51, No.9,
pp. 1190-1202, September, 1963.
2 E.F. McKeon "Crossmodulation Effects in Single Gate and
Dual Gate MaS Field Effect Transistors" RCA Application Note AN-3435.
3 S. Reich and L.S. Baar, "A Comparison of Solid-State and
Electron Tube Devices For TV-Receiver RF and IF
Stages." IEEE Transactions on Broadcast and TV Receivers, Vol. BTR-I3, pag. 41, April 1967.
4 J.R. Burns, "High Frequency Characteristics of Two
Insulated Gate Field Effect Transistor" RCA Review, Vol.
XXVIII No.3, Sept. 1967, pp. 385417.
5 3N187 Data Sheet, RCA File #436.
6 3N200 Data Sheet, RCA File #437.
7 S. Reich, "MaS FET Biasing Techniques," EEE, Sept. 1970.
8 L.S. Baar, "RF Applications of the Dual Gate MaS FET
Up to 500 MHz" RCA Application Note AN443 I.

[Rl(]5LJD

Linear Integrated Circuits

Solid State
Division

Application Note
ICAN-5015

Application of the RCA CA300a and CA3010
Integrated-Circuit Operational Amplifiers
BY
A. J. LEIDICH
The RCA CA300S and CA3010 Operational Amplifiers
are silicon monolithic integrated circuits designed to operate from two symmetrical low- or medium-level dc power
supplies (at supply voltages in the range from ±3 volts to
±6 volts). The power dissipation in the amplifiers ranges
from 7.0 milliwatts to 92 milliwatts depending upon the
supply-voltage level and the desired output-power level.
The amplifiers are primarily intended to operate with externally applied negative feedback; however, they may also
he operated successfully under open-loop conditions. The
main features of the CA300S and CA3010 Operational
Amplifiers are listed below:
• All-monolithic construction designed to operate at
ambient temperatures from -SS'C to +12S·C.
• Built-in temperature compensation which assures that
the gain and dc operating point are stable over the
temperature range of -SS'C to +12S·C.
• Capability of operating at extremely low dissipation
and supply-voltage levels, as well as at medium levels.
• Balanced differential-amplifier input configuration and
a single-ended output configuration.
• No shift in the dc level between the differential inputs
and the output.
• Little effect on the input offset voltage from variations
in the power-supply voltages.

The CA300S Operational Amplifier is supplied in a 14terminal flat-pack; the CA3010 Operational Amplifier is
supplied in a conventional 12-terminal TO-S package. With
the exception of the differences in their package construction, the two operational amplifiers are identical. This note
describes the circuit arrangement, lists the performance
characteristics. explains the major design considerations,
and discusses typical applications of the operational amplifiers.

CIRCUIT DESCRIPTION
Fig. I shows the schematic diagram of the CA300S or
the CA3010 Operational Amplifier. The numerals shown
alongside the circuit terminals indicate the terminal designations for the CA300S 14-terminal flat-pack and CA3010
12-terminal TO-S package. The numerals enclosed in
squares are the designations for the CA3010 package. The
diagram in the uppeF right corner of the figure shows the
orientation of the terminals on the CA300S flat-pack; the
diagram at the lower right corner shows the orientation on
the CA3010 TO-S package. (The number designations used
to refer to specific terminals in the following discussion, or
elsewhere in this note, are those for the CA300S 14terminal flat-pack. The corresponding terminals on the

3-70

87

ICAN-5015 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

CA30lO 12-terminal TO-5 pacicage can be determined from
the schematic in Fig. I.)
As shown in the schematic. diagram, each operational
amplifier consists basically of two differential amplifiers
@

the second differential amplifier is provided by current-sink
transistor Q,. Compensating diode D, provides the thermal
stabilization for the second differential amplifier and also for
the current-sink transistor, Q" in the output stage.

v+

0

•
5

'·
13

12

~

9

CA3008
14-TERMINAL FLAT-PACK

Note: RIO and RI3 not used.

CA30IO
12-TERMINAL To-S PACKAGE

Fig. I-Schematic diagram of the CA3008 or CA30IO Integ"';ted-Circuit Operational Amplifier.

and a single-ended output circuit in cascade. Circuit elements are also included to provide thermal stabilization
and to compensate for shifts in the dc operating point. In
addition, negative feedback loops are employed to cancel
common-mode signals (Le., error signals developed when
the two inputs to the operational amplifier are in phase
and of equal amplitude).

CASCADED GAIN STAGES
The pair of cascaded differential amplifiers are responsible for virtually all the gain provided by the operationalamplifier circuit. The inputs to the operational amplifier
are applied to the bases of the pair of emitter-coupled
transistors, Q. and Q" in the first differential amplifier.
The inverting input (at terminal 3) is applied to the base of
transistor Q.. and the noninverting input (at terminal 4) is
applied to the base of transistor Q.. These transistors develop the driving signals for the second differential amplier. A de constant--current-sink transistor, Q., is also
included in the first stage to provide bias stabilization for
transistors Q, and Q,. Diode D, provides thermal compensation for the first differential stage.
The emitter-coupled transistors, Q. and Q.. in the second
differential amplifier are driven push-pull by the outputs
from the first differential amplifier. Bias stabilization for

88

COMMON-MODE-REJECTION FEEDBACK LOOPS
Transistor Q, develops the negative feedback to reduce
common-mode error signals that are developed when the
same input is applied to both input terminals of the operational amplifier. Transistor Q, samples the signal that is
developed at the emitters of transistors Q. and Q•. Because
the second differential stage is driven push-pull, the signal
at this point will be zero when the first differential stage
and the base-emitter circuits of the second stage are
matched and there is no common-mode input. A portion
of any common-mode, or error, signal that appears at the
emitters of transistors Q. and Q. is developed by transistor
Q, across resistor R, (the common collector resistor for
transistors Q .. Q" and Q,) in the proper phase to reduce the
error. The emitter circuit of transistor Q, also rellects a
portion of the same error signal into current-sink transistor
Q, in the second differential stage so that the activating
error signal is further reduced.
Transistor Q. also develops feedback signals to compensate for dc common-mode effects produced by variations
in the supply voltages. For exampie, a decrease in ihe de
voltage from the positive supply results in a decrease in the
voltage at the emitters of transistors Q. and Q•. This ne~­
tive-going change in voltage is rellected by the emitter circuit of transistor Q. to the bases of current-sink transistors
Q, and Q •. Less current then flows through these transistors.
The decrease in the collector current of transistor Q, results in a reduction of the current through transistors Q.

ICAN-5015
and Q" and the collector voltages of these transistors tend
to increase. This tendency to increase on the part of the
collector voltages partially cancels the decrease that occurs
with the reduction in the positive supply voltage. The partially cancelled decrease in the collector voltage of transis·
tor Q, is coupled directly to the base .of transistor Q. and
is transmitted by the emitter circuit of this transistor to the
base of output transistor Qln. At this point, the decrease in
voltage is further cancelled by the increase in the collector
voltage of current-sink transistor 00 that results from the
decrease in current mentioned above.
In a similar manner, transistor Q;; develops the compensating feedback to cancel the effects of an increase in the
positive supply voltage or of variations in the negative supply voltage. Because of the feedback stabilization provided
by transistor Q" the CA3008 and CA3010 Operational
Amplifiers provide high common-mode rejection, have elI;cellent open-loop stability, and have a low sensitivity to
power-supply variations.
OUTPUT STAGES
In addition to their function in the cancellation of
supply-voltage variations, transistors Q~, QOI and Q,O are
used in an emitter-follower type of single-ended output
circuit. The output of the second differential amplifier is
directly coupled to the base of transistor Q.., and the emitter circuit of transistor Q. supplies the base-drive input for
output transistor Qw A small amount of signal gain in the
output circuit is made possible by the bootstrap connection
from the emitter of output transistor QlO to the emitter
circuit of transistor Qg, If this bootstrap connection were
neglected, transistor Qtl could be considered as merely a dc
constant-current sink for drive transistor Q.., Because of
the bootstrap arrangement, however, the output circuit
can provide a signal gain of 1.5 from the collector of
differential-amplifier transistor Q, to the output (terminal
12). Although this small amount of gain may seem insignificant, it does increase the output-swing capabiJities
of the operational amplifiers.
The output· from the operational-amplifier circuit is
taken from the emitter of output transistor Q" so that the
dc level of the output signal is substantially lower than
that of the differential-amplifier output at the collector of
transistor Q,. In this way, the output circuit shifts the dc
level at the output so that it is effectively the same as that
at the input when no signal is applied.
Resistor R" in series with terminal 8 (refer to Fig. 1)
increases the ac short-circuit load capability of the operational amplifier when this terminal is shorted to terminal 12
so that the resistor is connected between the output and
the negative supply.

For this reason, the special parameters for which additional clarification may be necessary arc defined in an
appendix at the end of this note.

DC CHARACTERISTICS
The operational amplifiers are designed to operate from
two symmetrical de power supplies at supply voltages in
the range from ± 3 volts to ±6 vo1ts. For opcration with
±3-volt supplies, the power dissipation in the amplifiers
is less than 7.0 milliwatts with terminal 8 open or 23
milliwatts with terminal 8 shorted to terminal 12. When
±6-volt supplies are used, the dissipation level increases
to either 30 milliwatts or 92 milliwatts. depending upon
whether tcrminal 8 is open or shorted to terminal 12.
The input offset voltage for the operational amplifiers
is typically 1.1 millivolts for all symmetrical supply voltages. This parameter is relatively insensitive to variations
in the supply voltages. When ±6-volt supplies are used,
the variation in the input offset voltage with fluctuations
in supply voltage is typically less than 300 microvolts per
volt for either supply. For ±3-volt supplies, the variation
is typically 700 microvolts per volt. The offset voltage
varies slightly with temperature as shown in Fig. 2. (Fig. 3
1.7

POSITIVE DC SUPPLY VOLTS (VCC)- +6
NEGATIVE DC SUPPLY VOLTS (VEE). 6

.

~ Q7

~
~

O.
Q

-75

-~

-2~

2~

75

12~

100

92CS-13632

Fig. 2-lnput offset voltage as a function of temperature.

Vee

+6V

De

VOLTMETER
IRCA
WV-38A
OR

EOUIVALENT )

OPERATING CHARACTERISTICS
The operating characteristics of the CA3008 and
CA3010 Integrated-Circuit Operational Amplifiers are identical. The characteristics data given in the following paragraphs, therefore, apply equally to each type. A proper
evaluation of the capabilities of the operational amplifiers
requires a thorough understanding of the parameters in
terms of which the operating characteristics are expressed.

50

FREE-AIR TEMPERATURE (TFA)--C

NOTE: Pins 8 and 12 shoutd be shorted for the pertinent

92C,-13.0.

power dissipation measurement ONLY!

Fig. 3- Test circuit used to measure the input oUset voltage.

89

ICAN-5015
shows the schematic diagram of the special test circuit
used for the offset-voltage measurements.)
.
The input bias current and the input offset current of
the amplifiers are typically 5.3 microamperes and 0.54
microampere, respectively, when ±6·voU supplies are
used. Figs. 4 and 5 show the variations in these parameters
with temperature.
POSITIVE DC SUPPLY VOLTS Wee). +6
NEGATIVE DC SUPPLY VOLTS (VEE)- -6

POSITIVE DC SUPPLY VOLTS tVee)- +6
NEGATIVE DC SUPPLY VOLTS lYEE}·-6

~~~~~~A~E:~~~A~ ~~~~,.
!II 70

I
-:.0

.0

Z
;;

"~

~~

-55-'

40

~

"'...

~"'''~'I'~
:>OG!

30

..g
..9

"

.el,11
'I'~
Ii!
~ ~,

60

.
...

IKA

r;,

20

0

II\\("~

I

z

_

'~.I.

125.../

?;

0.01

0.1

I

100

10

FREQUENCY (f) -

MHz

Fig. 6-0pen-Loop gain as a function of frequency.

-50

-2'

0

2.

50

15

100

POSITIVE DC SUPPLY VOLTSIVec)- +3
NEGATIVE DC SUPPLY VOLTS (VEEI--3

12.

R. -15 OHMS
T£RIIINAL No. I, [!]: OPEN

FREE-AIR TEMPERATURE (TFAI- 7

5

6

"~

5

TERMINAL No. B ~ SHORTED TO

~

..

:l

POSITIVE DC SUPPLY VOLTS (Vee)- +6
NEGATIVE DC SUPPLY VOLTS (VEE). - 6
FREE-AIR TEMPERATURE (TFN-Z5·C

TERMINAL No. 8 ~ OPEN

o

TERMINAL No. 12

IE

4

TERMINAL NO.8 (5) OPEN

7

..
I
:i
..

50

-75

r--..

r

I I
I I II

-~

2

•••

2

7
•

66

I

•

2

66

2

10

FREQUENCY (f)-MHz

• 6.

100

92CS-13482

Fig. 9-DiDerential and common-mode gain as a junction
of frequency at different temperatures.

100

125

ITERMINACfNo.8 OI'EN

TERMINAL No..!, SHORTED TO
,,\
;fii:' 6l--t-TERMlNI\L NO.12!--+-I-+I-".~M---j.-+~

.,

~~ 1---4---4_4-+4---+---I--I-4-I---4~-+-+-H
1\\
!~
\
,'-oJ 5

~~ 41--~---4~-+4_--+_--I--I-4-1---4_~+_+_H

\

.!~"

)c . .

POSiTiVE DC SUPPLY VOLTS (Yee)" +6

~o

NEGATIVE DC SUPPLY VOLTS (VEE). -6

~:;~;:!~ ~~~:EtiA6~~~ (TFA1·

n;

50

POSITIVE DC SUPPLY VOLTS (Vee)" +6
NEGATIVE DC SUPPLY VOLTS WEE). -6
FREE-AIR TEMPERATURE (T~4)"2!5·C

I
I
0.1

25

Fig. ll-Output-sw(ng capabilities as a function 0/ temperature.

-25f-COMMON-MODE GAIN
-50

0

92CS-13527

~~I'c?"~

a

co

g

-25

FREE-AIR TEMPERATURE (TFA)-OC

~~es.

z

!J

-50

0,..,

31--~---+~-I-+_--+_--I--~+--+_--+_+_H

2S·C

100

-.....

z

....
:.Iv
2

80

\

OU

=rC; 40

30

20

U
2

0.01

•• 6

0.1

..

.8

I
FREQUENCY {f 1 -

2

4

6 810

92CS-13481

POSITIVE DC SUPPLY VOLTS (Vee)· +6
NEGATIVE DC SUPPLY VOLTS (VEE)· -6

~5
0

680.1
2
4 6 8
FREQUENCY (f)-MHz

Fig. 12-0utpul-swing capabilities as a Junction of frequency.

~ I 60

..
iC
0,",
~o:

4

0.01

r--..

2

.

.6

2

10

.

FREQUENCY (f) • I kc/s

.8

100

MHz
92CS-13551

Fig. 10-Common-mode rejection as a junction 0/ frequency.

Output Swing: The operational amplifiers exhibit a maximum dynamic-swing capability of ±3.5 volts with terminal
8 open and of ±3.0 volts with terminal 8 shorted to terminal 12. The output-swing capability varies only slightly
with temperature, as shown in Fig. II. Fig. 12 shows the
variation in the output-swing capability with frequency.
Input and Outpnt Impedances: When the CA3008 or
CA30lO Operational Amplifier is operated from ±6-volt
supplies, it has an input impedance of 14,000 ohms at I

a
-'ni

-50

-25

0

25

50

75

100

125

FREE-AIR TEMPERATURE (TFA)-·C
9ZCS-Il:lZG

Fig. J3-lnput impedance as a function of temperature.

91

leAN-S01S
kHz and an output impedance of 200 ohms (terminal S
open) or 75 ohms (terminalS shorted to terminal 12). The
input impedance and output impedance of the amplifier are
affected by temperature as shown in Figs. 13 and 14. respectively.
POSITlVt:: DC SUPPLY VOLTS (Vee). +6
NEGATIVE DC SUPPL.Y VOLTS tYEE)- -6

FREOUENCY (f) • I kHz

CI

I

j

generalized inverting feedback configuration. and Fig. 16
provides the diagram and the equations for the noninverting configuration. In both configurations. the inputs are
returned to ground through dc paths that are effectively
identical. This condition is necessary for minimum offset
voltage (dc error).
Because the open-loop input capacitance of the operational amplifier is less than 10 picofarads. the frequency response is virtually independent of the drive source impedance. The input-impedance equations given in Figs. 15 and
16 indicate that this lack of dependenc.e is even more pronounced when the amplifiers are operated with negative
feedback.
R,

•

r--'1

r

I lol

I
I

L __ J

L
-7lI

-~

-25

0

~

25

7lI

100

125'

FREE-AIR TEMPERATURE (TFAI"':'-C
92CS-13~40

Z,
Z,

Zj

Fig. 14-Output impedance as a function of temperature.

= op_l.., lopu'llIpH.co

101 =

R,' z,l .. =O)/iZf.I ... =f1l

CIRCUIT DESIGN CONSIDERATIONS
The basic design equations for the CA300S or CA3010
Operational Amplifier in closed-loop circuits are summarized in Figs. 15 and 16. Fig. 15 shows the basic
schematic diagram and gives the design equations for the

Z,

d_.I.., Inpo' 100pHon..

AYol") = -~.., pl.

AYol .. ) II, < Zf) •
You,/Yln =

I, < Zf<

z.,. I,

= 1 < Zf/z,

You,/Vln )
10 = 101 ( - - AVol .. )

r--,
I lol I

r
I
I

z,

+

Voor

~

__ .J

L

Fig. 16-Noninverdng-/eedback configuration for
an operational amplifier.

"oor
PHASE COMPENSATION

R,

=optn..loop Input impedance
=open.loop output Impedance
Ayo (Col) =op... loop gain
Zi

lol

II, = Z,I .. = olll Zf I .. =0)

Vou " Vln

=

-I,
I, < IZf < z,)/AVol .. )

~ -Z,tZ,

Zin = Z, < II,tAVo( .. ll/lII ~ I,
10 = 101 (1 < Vou,/Vln)
• AVol .. )

~

0

Fig. 15-1nvertlng-ieedback configuration for
an operational amplifier.

92

Basically. phase compensation is used to alter the response of an amplifier so that a phas.e shift of ISO degrees
cannot occur at a frequency for which the loop gain is
unity or greater. A rule of thumb that will guarantee an
ac-stable amplifier is that at the intersection of the closedloop response with the open-loop response. the respective
slopes must have a difference less than '12 dB per octave.
With few exceptions (some of which will be covered
in the section on applications). phase compensation must
be accomplished by altering the open-loop rC5ponse of the
operational amplifier itself. One of the advantageous features of the CA3008 and CA3010 Operational Amplifiers
is that small values of capacitance properly added to the
amplifier circuit will provide the required phase compensation. When ±6-volt supplies are used. two phasecompensating networks. each of which consists of a 27picofarad capacitor in series with a 2000-ohm resistor.

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ICAN-5015
connected between terminals 1 and 14 and between ter-

mina"ls 9 and 10, cause the amplifier to roll-off at a slope
of one (6 dB per octave) all the way to unity gain (where
it then breaks into a slope of two). This value of compensation is sufficient to stabilize the amplifier for all
resistive-feedback applications including unity gain. The
response for this value of phase compensation is compared

to the original open-loop response in Fig. 17. Although
the two compensating networks are sufficient to ac stabilize
the amplifier, they arc not sufficient to produce a flat
response (within ± I dB) for closed-loop gains below 15 dB.
Fig. 18 shows a plot of the capacitance required to produce

Phase compensation may
ally by adding a capacitor in
terminal 11 and ground. A
series with a 22·ohm resistor

also be effected conventionseries with a resistor between
O.02-microfarad capacitor in
is sufficient to ac stabilize the

CA3008 or CA30lO Operational Amplifier at resistive
c!osed-Ioop gains down to unity.

The required phase compensation depends upon the
feedback configuration and not upon the location of the
drive sourcc. Hence, phase-compensating networks that
provide sufficient compensation for a lO-dB noninverting
configuration also provide sufficient compensation for a

6-dB inverting configuration because the two feedback
configurations are idcntical.

POSITIVE DC SUPPLY VOLTS Wee)- +6
NEGATIVE DC SUPPLY VOLTS (VEE). - 6
SOURCE IMPEDANCE (R,) • I KG
60

III

40

3z

30

I

."
"'"~

g

OUTPUT-POWER MODIFICATIONS

r--...

r....

00

I.....

A choice of two output-power capabilities is provided
in the CA3008 and CA3010 Operational Amplifiers. The
output can be tailored to the specific load requirements
by leaving terminal 8 open and placing an appropriate re-

",n

I--~"',p

r....

sistor between terminals 6 and 12. The minimum safe value

of load resistance (including the aforementioned resistor)
is 200 ohms when ±6-volt supplies are used. In determining
the output capability, it should be kept in mind that the
feedback network can contribute to the output loading

"'~-+-I\"'''''
+~.- ~
1-"':

20

.

:I'~

~

10

especially in the lower-gain configurations.

0
-K!

0.01

2

4

.8

0.1

2

•• 8

FREQUENCY etl -

2

4 .8

4

2

10

.8

100

MHz
92CS-I'5Ut

Fig. 17-Open-loop gain as a function of frequency lor both
phase-compensated and uncompensated operational amplifiers.
7C

DC COLLECTOR SUPPLY VOLTS (Vee) • +6
DC EMITTER SUPPLY VOLTS (YEE) • -6
FREE -AIR TEMPERATURE eTFA! • 25°C
TERMINAL No. B OPEN.

APPLICATIONS OF THE
OPERATIONAL AMPLIFIERS
The CA3008 and CA30lO Integrated-Circuit Operational Amplifiers can be adapted for us~ in a variety of
diverse applications. For example, the amplifiers 'may be
operated to provide the broad, flat gain-frequency response
required for video amplifiers or the peaked responses re-

quired for various types of shaping amplifiers. Other applications of these amplifiers include comparators, integrators,

differentia tors, and summing amplifiers. The following
paragraphs describe the circuit arrangements and the performance characteristics of the operational amplifiers in

such applications:
VIDEO AMPLIFIERS
When the feedback is applied through a purely resistive
network and suitable phase compensation is employed, flat

10

o

10

20

30

CLOSED-LOOP NON-INVERTING VOLTAGE GAIN-dB
o
6
19.1
29.7
CLOSED-LOOP INVERTING VOLTAGE GAIN -dB

40
40

9ZCS~13523

Fig. 18-Amount of phase-compensating capacitalice required
ta obtain a flat (± I-dB) gain response as a
function of frequency.

gains are aUainable from the operational amplifiers. Fig.
19 shows a 30-dB noninverting configuration of a video
amplifier, together with the closed-loop response of the circuit. The phase compensation is provided by as-picofarad
capacitor in series with a lO,OOO-ohm resistor. This arrangement provides the required amount of compensation, as

gain. The capacitors must have a resistor in series with

predicted in Fig. 18. (For purposes of comparison, the
uncompensated response of the 30-

20

~

10

,~

0
10

0.1

IK

lOOK

-6'

100

FREQUENCY- MHz

Fig. 19-Noninverting configuration and closed-loop response

0/ an operational.ampli/ier type 0/ video amplifier that provides

a gain of 30-dB•

• 6.

70

.i

IK

60
50

z

C

...co
~
!:;
0

40

NO COMPENSATION30

>
20
10

-6'
I.

30te

0
0.01

~

10

0.1

100

FREQUENCY- MHz

Fig. 20-Circuit diagram and gain-frequency response of the 30-d8 noninver,;ng video amplifier operated without pluue
compensation.

94

ICAN·5015
-6V

I"

10
60
CA300B

I;j
~

~
0

.0
40
30

>
20

\'-1'
\

-6V

10

I"

0
0.01

10

0.1

100

FREQUENCY-MHz

1.8 pF

Fig. 21-Circlfit diagram and gain-frequency response o/the 30-dB video amplifier when the phase compensation is accomplished by the addition 0/ a capacitor ilt parallel with the feedback resistor.

2"
_6V

10

.!

60

i"::

.0

~

;j

.'"

40

~

12)-+---{)

VOUT

~
>

'I'<

30

ItHlli

20-

CLOSED LORi

COMPENS~tfi~:--

10

III ;

0

III

am

19~~~, LOOP COMPENSATED

11111

11111
10

0.1

100

FREQUENCY-MHz

-6V

Fig. 22-Circuit diagram and response 0/ an inverting type 0/ operational amplifier used as a 6-dB video amplifier.

95

ICAN-S01S _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

2<
+6V

70

.
~

12}-+-----Q
VOUT

g
'"

~

0

60

~f'o.

50

V

40
30

I SLOPE

r..

OPEN LOOP COMENSATED

I-

>
20
CLOSED

~~P CDMPEN~~ED i'

10
0

111111111

0.01

~

11111111

10

0.1

100

FREQUENCY-MHz

-6V

Fig. 23-EDect of a decrease in the phase.compensating capacitance from 56 picofarads to 33 picofarads on the
response 01 the 6-dB video amplifier.

(Z,/Z,) to roll off at a one slope. Fig. 21 illustrates this
alternate technique for the 30-dB gain circuit.
The low-frequcncy input impedance of the 30-dB noninverting configuration is 480.000 ohms. as calculated from
the appropriate equation in Fig. 16 (Z, = 14.000 ohms).
Fig. 22 shows the configuration and the response of a
6-dB inverting type of video amplifier. The intersection of
the closed-loop characteristic with the compensated openloop response predicts the 3-dB bandwidth of the video
amplifier provided the transfer phase shift of the open-loop
amplifier is approximately -90 degrees. This relationship
suggests a way to extend the bandwidth without peaking. In the 6-dB video amplifier shown in Fig. 23, the
3-dB bandwidth has been increased from 5.6 MHz to 11
MHz by a decrease in the value of the phase-compensating
capacitors from 56 picofarads to 33 picofarads.

LOW·LEVEL PULSE
YIN" 3SmV
Your = 1.1V
Id= 40ft.

',"On.
tr;tf= 12On.

(.)

OVERDRIVEH PULSE
VIN" l.27V

Your = 3.2V
td=32ns

Because a broadband amplifier should. be capable of
handling digital signals. data were taken to determine this
capability. Figs. 24(a) and 24(b) illustrate the pulsehandling capabilities of the 30-dB noninverting circuit
shown in Fig. 19. Fig. 24(a) shows the low-level (nonsaturating) pulse response. The input is a 38-millivolt,
960-nanosecond pulse; the output is a 1.\-volt pulse having
a 40-nanosecond delay time. a zero storage time, and
125-nanosecond rise and fall times. Fig. 24(b) shows the
response of the amplifier for a 960-nanosecond input pulse
under 20-dB overdrive conditions. The output pulse has
an amplitude of 3.2 volts, a delay time of 32 nanoseconds,
a storage time of 160 nanoseconds, a rise time of 500
nanoseconds, and a fall time of 160 nanoseconds.

96

I. "160n.
',"SOOn.
1,=160"5

("

NOTE:

'd
Is
"
If

" D':LO\Y TIME
" STORAGE TIME
" RISE TIME
= FALL TIME

Fig. 24-Pulse-handling characteristics of the noninverting
30-d8 video amplifier: (a) Low-level pulse response;
(b) Pulse response under overdrive conditions.

ICAN-50l5
FREQUENCY-SHAPING AMPLIFIERS

These break-frequency equations are the precise equations derived from the gain equation in Fig. 16. The

The operational amplifiers may be used to create simple frequency-shaped characteristics, such as those assaciate'd with band-pass. notched-response, and single-tuned
narrow-band amplifiers.
Fig. 25 shows a noninverting amplifier that may be used
to synthesize the following peaked-response transfer function:

amount of phase compensation required is that shown

in Fig. 18 for a noninverting gain of 20 dB.
Fig. 26 shows the circuit configuration and the frequency response of a narrow-band, 100- kHz tuned amplifier. The circuit Q is 33.3. A true single-tuned response
can be obtained from only an inverting circuit configura-

tion, as shown by the gain equation for the two types of
configurations given in Figs. 15 and 16 and repeated
below:
I. For the inverting configuration. the gain equation is
given as:

where f, = 10 kc/s, f, = 40 kc/s, f, = 200 kc/s, and f,
= 800 kc/s.
In terms of the notations employed in Fig. 25, the breakfrequency equations for the amplifier may be expressed
as follows:

2rC,(R:~

VI"

2. For the noninverting configuration. the following
gain equation is used:

~=I+Z!Z
VIII
f .•

lOR,) = 10 kHz

2r~ ,R,

The "1+" term in the gain expression for the noninverting
configuration indicates that the gain of this type of circuit will never decrease to zero as required for a true
single-tuned response. The amount of phase compensation
required for the narrow-band 100- kHz amplifier is the
value given in Fig. 18 for an inverting gain of 0.0 (infinite
attenuation).

== 40 kHz

1
_rC"(R,,

+ R,)

= 200 kHz

40
ZrC"(40R,,

+ R,)

800 kHz

?

~=-z'/z,

.6V

Your

.,

40

iz

..::

~

30

!:i
0
>

:-

~~

r--.

20

-6V

10

Rr· 3oo

IC"

0.001

Rf·9K

0.01

0.1

10

FREQUENCY-MHz

A.
0.013 "F

I.
en
68 pF

Rn
2.7K

Fig. 25-Circuit diagram and response 0/ a noniuverling type of operational amplifier used 10 synthesize peaked-response
transfer functions.

97

ICAN-S01S _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

+6V

0 0 33.3

1\

11\
I \
II \

3.3 )(
16
16
CA300e

m
~

I

z

3.3K

g
w

II
~
0
>

"
12
10

/
,7

6
6

-6V

•

1.7mH

2

( TERMINALS

\

1\

17
/

0

35K

\

76

64

~.7.8.tI

92

100

108

FREQUENCY-kHz

OPEN)

"

116

124

1500 pF

Phase Compensation not shown. It is 62 pF in series with 820

n between terminals 1 and 14 and between terminals 9 and 10.

Fig. 26-Circllit diagram and response of an inverting type operational amplifier used
a narrow-hand lOO-kc/s tuned amplifier.

COMPARATOR CIRCUITS
The CA3008 and CA3010 Operational Amplifiers have
excellent transfer characteristics for comparator applications. As shown in Fig. 8. the ampJifiers have no observable
hysteresis effect; the trace (minus to plus) and retrace (plus
to minus) excursions coincide.

INTEGRATORS
The important design consideration when an operational
amplifier is to be used as an integrator is that dc feedback
be provided. This feedback is necessary so that an offset
(error) voltage cannot continuously charge the feedback capacitor until the amplifier limits. The required dc feedback
is normally provided by shunting the integrating capacitor
with a resistor so that the resulting time constant is con·
siderably longer than the periods for the frequencies of
interest. Fig. 27 shows the circuit configuration for the
use of the CA3008 or CA3010 Operational Amplifier as an
integrator and the responses of the circuit

fO.f

I-kHz square-

wave inputs. The dc gain of the circuit is limited to 20 dB
by the 39,OOO-ohm feedback resistor. The effect of this
resistor on the gain, however, becomes negligible for ac
signals at frequencies above 13 Hz because of the 0.03microfarad capacitor in parallel with it. The weighting
factor of integration for the eire:.;.:t i!; about 1 millisecond
(R
39,000 ohms; C
0.03 microfarad).

=

=

Phase compensation must also be provided in an integrating amplifier circuit to assure ac stability. In general, the
amount of compensation required is the maximum value
given by Fig. 18. because the closed-loop characteristic of
the integrator has rolled off completely at the frequency
where the intersection of the open-loop response and the
closed-loop characteristic occurs.

98

a~

DIFFERENTIATORS
The main problem in the design of differentiating amplifiers is that the gain of such amplifiers increases with
frequency; hence, they are susceptible to high-frequency
noise. The classical remedy for this effect is to connect a
small resistor in series with the input capacitor so that the
high-frequency gain is decreased. Actually, the addition of
the resistor results in a more realistic model of a differentiator because a resistance' is always added in series
with the input capacitor by the source impedance. The
schematic diagram of a CA3008 or CA30 10 Operational
Amplifier used as a differentiating circuit and the response
of the circuit for I-kHz square waves are shown in Fig.
28. A value of 51 ohms is selected for the gain-limiting
resistor to illustrate that the effect of the source impedance
is not necessarily negligible in differentiator applications.
This 51-ohm resistor limits the high-frequency numerical
gain factor of the amplifier to 433.
If the closed-loop gain of a differentiator rises to the
open-loop value before the open-loop response has started
to roll off, no phase compensation of the circuit is required. ]n order to assure that the intersection of the
closed-loop characteristic with the open-loop response occurs at a slope less than two, the RC time constant of the
phase-compensating network must be adjusted so that
the open-joop response does noi. ruli ull ill UIt:: region
of the intersection.

SCALING ADDERS
The inverting feedback configuration of the CA3008
and CA3010 Operational Amplifiers lends itself not --€:f-f--,-- OUTPUT

+Vcc
(b)

Fig.

(0)

~chemotic

diagrams showing supply-voltage connections 10 the CA300S or CA3006 for operation from either single or
dual power supplies: (aJ Differential-amplifier configuration operated from dual supplies: (b) DiDerential-amplifier configuration operated from a single supply,' (c) Cascade configuration operated from dual supplies; (d) Cascode configuration
operated from a single supply.

be added to the circuit, as shown in Figs. 4(b) and 4(d).
Tuned amplifiers that operate from dual supplies, such as
that shown in Fig. 4(a), require the least number of external

components.

For either single- or dual-supply operation, the operating
current of transistor Q. is determined by the bias voltage,
V'F., applied between terminals 2 and 3 on the CA3004 or
between terminals 8 and 12.on the CA300S and CA3006
(refer to the circuit diagrams in Fig. I). The more negative
terminal of the bias-voltage source must be connected to
terminal 3 on the CA3004 or to terminal 8 on the CA300S
and CA3006. In dual-supply systems, terminal 2 of the
CA3004 and terminal 12 of the CA300S and CA3006 are
usually returned to dc ground.
OPERATING MODES
For any given bia~ voltage V.., there are four possible
operating modes for the integrated-circuit rf amplifiers. In
general, each mode is characterized by (I) a distinct level
of operating current and corresponding transconductance,
(2) the degree of dependence of the operating current on
temperature, and (3) the way in which the transconductance

104

'

is affected by temperature. The operating points for the various modes are established by:
I. The emitter resistance selected for the constant-current-source transistor, Qa;
2. Whether the base-bias network includes the diodes
shown in Fig. 1.
3. The magnituae of the bias voltage, V.., applied to the
circuit.
Table I lists the required conditions for the four operating
modes, designated A, B, C, and D. The following paragraphs
describe the characteristics of the circuits in each operating
mode. The data are given for operation of the circuits from
symmetrical dual power supplies at three levels of dc supply
voltage (±3 volts, ±4.5 volts, and ±6 volts).
Fig. 5 shows the operating current for the various modes
as a runction~of temperature. Tfi,e current-temperature data
show that, in addition to the obvious shift in the level of
operating current, the dependence of the operating current
on temperature varies significantly with a change in the
operating mode.
When the diodes are included in the base-bias circuit

-----------------------------ICAN.5022
TABLE I
Required Conditions for Each Operating Mode of the CA3004, CA3005, and CA3006
Integrated-Circuit RF Amplifiers
Terminals Shorted

C..tJ005 or CA3006
Terminals Slzorted

In or Dut

Q·3

To
Terminal 3

To
Terminlll8

of
Bias Circuit

Emitter
Resistor(s)

5
4
4,5

4
5
4,5

C1300~
Operatjll~

.Mode·

A
B
C

D

Diodes

----

R,+Rb
+ R6
R,
R,

In
Out
In
Out

R,

"'For all modes, terminals 2, 6, and 12 of the CA3004 and terminals, I, 7, and 12 of CA300S
and CA3006 are grounded.

6.4
OPERATING MODE C

5 . 6 r - - -_ _ __

2.8
OPERATING MODE A

~ 4.8

2.4

uI

~

E

I

~

2.01---_ _ _ _ _ _ _ _ __

I

E
~

1.6r-----___,--_______ou_

a 1.2

-

u

t3 VOe

o

~

r - - - - -_________

~ 4.0r~6 VOe

0.8

:t4 . .5 VOe

! 3.2r-_______________
~

z

-.!'

g

2.41

e~

1.6

04

.t3 VOe

0.8

~~••~--~3.~--~
..--+--2~'~~4'~-f6.~~8~'-~10~5-~125

0-~5~5--.3~5,---~I5,--+---2~5,-~4~5--~6~5--~,b.--~I~__Tz5

TEMPERATURE _·C

TEMPERATURE _·C

(a)

(c)
OPERATING MOOE 0

:i6 VOC

1.2

2.4
OPERATING MODE B

~

E

~

e

1.0

I
u
:t 0.8

t6

voe

~

z

~ 06

a.

t.4.~~

1___----------------------------------

gOAl-"

I 2.0

r

J 6l----------------------------...:.==
~-

a I.Z
u

o

.oJ

~

I ___-------------------------------e~ O.2F-~~5<5~~3.--~-~..---+--t.2•.-~45--~6~5-~8~5-~1*'0•.-~125
TEMPERATURE--C

(b)

0.8

~

:: o.4L--------------------~~.·5~-t3•.---+.I5.-~.--~2~.--·4~.--~6~5---.~5,--,~~.-~125
TEMPERATURE _·C

(d)

Fig. S-Variation in the operating currents of the CA3004, CA3005, or CA3006 as a function of temperature for each mode of
operation.

105

ICAN-5022
(modes A ano C), the operating current, which is primarily
dependent on the temperature coefficient of the diffused
emitter resistor, tends to decrease with an increase in tern·
perature at a rate that is relatively independent of the bias
supply voltage VI·:". When the diodes are not used, however,
the shape of the current-temperature curves is dependent on
the magnitude of the supply voltage V"P.. The operating current then may remain constant or rise as the temperature is
increased, depending upon the value of Vfa:. The positive
supply voltages, shown in Fig. 5, have no effect on the operating current, and the current-temperature curves are not
changed by increases Of decreases in this voltage. Some deviation in the current-temperature curves is to be expected
because of normal variations in the absolute resistor values.
Fig. 6 shows the effects of different operating modes and
variations in temperature on the single-ended transconductance' of the CA3004. In general, when diodes are used in
*The single-ended transconductance is the incremental output current
for one collector of the differential pair of transistors divided by the
incremental input voltage. The curves shown of d":<; parameter are
obtained at an operating frequency of 1 MHz.

"'oZ

II OPERATING MODE C
FREQUENCY (fls I MHI

9 OPERATING MODE A
FREOUENCY Iflt I MHl
8

E
~
~

the base-bias network, the transconductance decreases with
increases in temperature. If the diodes are not used, the
transconductance may decrease, increase, or remain con~
stant as the temperature increases, depending on the value
of the negative supply voltage VEE. With the diodes out,
however, the collector operating point tends to shift when
resistive loads are used. In applications that require a stable
collector dc operating point, therefore, operating mode A
or C (diodes in) should be used.
Fig. 7 shows transconductance-temperature curves for
each operating mode of the CA3005 or CA3006, operated in
a differential~amp1ifier configuration.· These transconduct~
ance curves differ from those for the CA3004 shown in
Fig. 6 primarily because of the emitter resistors used in the
CA3004. For each operating mode, the operating points for
the differential-amplifier configuration of the CA3005 or
CA3006, as well as for the CA3004, provide a current in
each collector of the differential pair of transistors that is
equal to one-half that shown in Fig. 5.
In a cascade configuration of the CA3005 or CA3006, the
current through each part of the _common emitter-common

r-----------____

7

~~5'5~-~35~~-~,.~~~~2~5~-4~5~~65.--.8~5--"IO~5~~,25

~~'5~~-3~5o-~-~I.o-~o-~2"--'4~'---6t.5o--t.85~~IO~5--~'2'
TEMPERATURE-oC

TEMPERATURE-oC

(C)

(a)
OPERATING MODE 0
FREQUENCY (f I" IMHI

OPERATING MODE B
FREQUENCy (I)" I MHI

"'

g

i
8...~z

::

G

4~--------------

I

I

3b-__

________________ *4.,

VOe

------------------------------~.~3V~O~C

-

-i 3YDC

;;;

J

-~55--~-~~5.-~-~;5.-~.--oi~5--~4~~---6~'5C--t.M.-~1J~5--7,125
TEMPERATURE--C

(b)
Fig. 6-Variation in the single-ended transconductance of the CA3004 as a functl"on of temperature for each operating mode.

106

ICAN-5022

28

OPERATING MODE A
FREQUENCY(fI*IMHI

:t:6VDC

.:i.4.::iVDC

"

~~VDC

'0

~--~1~'-~--~~'--.~'~'6~'--~~'--'±0''-~''~'--~1!=-'
TEMPERATURE--C

~_~.·.~_~"~~_,.,--7--~~~-.~''-·'~'--~'''-~'~0''-~12~
TEMPERATURE-*C

------

~

~ 24

z6vnc

3

.... "",

= 16
~g 12

~ 20

_ _------------------:l:3VOC

~

~

~
~

-55

-;'5

-IS

25

45

65

TEMPERATURE-*C

..,PERATING MODE 0
FREQUENCYII!-IMHz

".

.

-------s

-i6YDC

4.5 VDC

_________________________________ •• wc

4

~ O~~~.-~--~--~,.~••~,--~••.--.~.~",o~.~T,,,~.--~
TEMPERATURE--C

Fig. 7-Variation in the single-ended transconductance 0/ the CA3005 or CA3006 in a differential-amplifier configuration as a
junction of temperature for each operating mode.

base cascode is equal to the total current shown in Fig. 5 in
each mode. Fig. 8 shows the transconductance-temperature

curves for each operating mode of the cascode circuit. These
curves show that, in general, the transconductance is highel

when the diodes are included in the base-bias network
(modes A and C) than it is when the diodes are not used
(modes B and D).
The power dissipation of the CA3004, CA3005, or
CA3006 is highest when the circuit is operated in mode C.

Table II shows power dissipation and the single-ended transconductance of the circuits for each operating mode. These
data may be used to determine the operating point that provides the highest value of transconductance per milliwatt of
circuit dissipation for given design conditions.

CHARACTERISTICS OF THE RF
AMPLIFIER CIRCUITS
Y PARAMETERS
In the design of rt and if circuits, the four-terminal blackbox short-circuit admittance parameters have become a

valuable tool. The determination of stability criteria, input
and output impedances as a function of load and source admittance, power gain, and voltage gain in iterative connections are all facilitated by a knowledge of the u y" parameters.
The "y" parameter curves presented in this section have
been calculated from a model and verified at several points
by measurements. These curves are a valuable aid in the
design of systems that use integrated circuits. The admittance curves are all generated for a quiescent operating current of 1.25 milliamperes in each of the transistors Q\ and
Q, in the differential-amplifier configurations and for a
current of 2.5 milliamperes in transistor Qa in the cascade
configuration. This operating current is obtained in the
operating mode D, as defined in the preceding section, with
supply voltages of ±6 volts.
The "yU parameters and their symbols are listed below:
1. Input admittance with the output voltage constant
y. = g, + jb.
where yl is the complex input admittance, gl is the' input
conductance and bl IS tne lOput susceptance.

107

ICAN-5022
TABLE

n

Relationship Between the Transconductance aDd the Power Dissipation of the
Inlegrated-circuit RF Amplillers in Each Operating Mode"
OpertJ/in,

Mod<

A

DC Suptlly

S.ngle-EIIIkd

Typ.oj
Circui!

VoIIlI,es

T,anscondud4nu

Power
DisrifHJIion

(..Us)

(miU'mlw.)

(m'U.V1/JUs)

CAJOO4
CAJOOS or CAJOO6
CAJOO4
CAJOOS or CAJOO6

=3

5.5
8.5
6.7
12.8
7.3
IS.0

6.6
6.6
15.0
15.0
25.0
2S.0

1.6
1.9
4.0
4.9
5.3
7.2

2.3
2.3
7.2
7.2
15.0
15.0

7.5
22.0
8.5
29.0
9.1
37.0

17.5
17.5
40.0
40.0
62.8
62.8

3.3
5.0
6.0
13.0
7.2
20.0

4.2
4.2
17.4
17.4
35.9
35.9

CA3OO4

CAJOOS or CAJOO6

B

C

D

=4.5
=6

CAJOO4
CAJOOS or CAJOO6
CAJOO4
CAJOOS or CAJOO6
CAJOO4
CAJOOS or CAJOO6

=4.S

CAJOO4
CAJOOS or CAJOO6
CAJOO4
CAJOOS or CAJOO6
CAJOO4
CAJOOS or CAJOO6

=4.5

CAJOO4
CAJOOS or CAJOO6
CA3004
CAJOOS or CAJOO6
CA3004
CAJOOS or CAJOO6

=4.5

=3

=6
=3

=6
=3

=6

"Circuits "'" operated in dillerentia1-amp1ifier conO.......tioDS. The tran.c:onductances and power
d/ssipatinno ohown are calculated valueo for nominal units.

2. Output admittance with the input vnltage constant
y. = g. + jb.
where y. is the complex output admittance, g. is the output
conductance, and b. is the output susceptance.
3_ Forward-transfer admittance with the output voltage
constant
yt= gt + jbt
where yt is the complex forward-transfer admittance, gt is
the forward-transfer conductance, and bt is the forwardtransfer susceptance.
4. Reverse-transfer admittance with the input voltage
constant
y. = g. + jb,
where y.. is the complex reverse-transfer admittance, g.. is
the reverse-transfer conductance, and b. is the reversetransfer susceptance.
A comparison of the parameters of the various possible
circuit configurations with those of the more familiar common-emitter parameters requires a second subscript to indicate the type of configuration being considered. Examples of
the use of the second-subscript notation are given below:
The common-emitter reverse-transfer admittance is writtenas
y•• = gn + jbn

108

The diJlerential-amplifier reverse-transfer admittance is
expressed as
yrDA.

=

grDA

+ jbrDA

The cascade-amplifier reverse-transfer admittance is given
as
Y,C"8 = grCAS

+ jbrcAs

Tbese cumbersome second subscripts will not be used
when the type of circuit for wbicb the parameter is given
is clearly indicated by an illustration or a descriptive phrase
in the text.
In general it is valuable to understand the essential differences between the "y" parameters of a regular commonemitter stage and those of the compound stages, sucb as
differential and cascade amplifiers.
The differential amplifier, wben used at radio frequencies,
consists essentially of a common-collector stage that drives
a common-base stage. In comparison to the regular, common-emitter "y" parameters, the input admittance y. the
output admittance Y., andtbe forward transfer admittance
yt, are decreased, almost exactly, by a factor of two when
tbe differential-amplifier configuration is used.
The reverse-transier admittance yr is aisu It:5:6 for the
differential amplifier tban for the single transistor in the
common-emitter configuration. The ratio of the imaginary
term in tbe differential-amplifier admittance to that of the
single transistor is 1/140 at low frequencies and 1/10 at
100 MHz. Fig. 9 sbows the ratios of imaginary parts

------------------------------ICAN-5022

r

OPEJ;iATI~G

1)0

MODE C
FREOUEIIIC'l'(fj&IIIHI

'0. _ _ _ _ _
_,

OPERATING MODE A
FREQUENCYlf}-IIIHz

'

.*6 VCC

[
l_
i
~

:l:.6VDC
z4.5VDC

ri--350i-

~

;t4511DC

_ _ _ _ _ _ _ _ ;t)VDC

I

~40~

I

'OL
25

45

'0'

65

TEMPERATURE-'C

-55

_~_~....l __ .

-]5

-15

5

25

45

..J_.--L._ ... 1
65

85

105

L
125

I.
'45

TEMPERATURE-'C

OPERATING MODE a
FREQUENCY (II-IMHz
OPERATING '-lODE 0

fREQUENCYUlolMUz

30

I·I~··­
_.4.5VOC Fl-----··'v
oc
.:l6VDC

~

30

~

u_

W

_
25

45

65

_

4

~

_

•
•
_
_
~
.-1_
----L_~ __L

85

TEMPERATURE-'C

TE\lPERATURE-'C

Fig. 8-Var;ation in the transconductance of the CAJ005 or CA3006 in a cascade configuration as a function of temperature for
each operating mode.

a

i
2

~

~ 100

Fig. 9-Ratio oj the real (conduc/ance) and the imaginary (susceptance) parts 01 the reverse-transfer admittance for a commonemitter stage to those for a diDerential~amplifier stage as a fUllction of frequency.

b .. /b.n. and real parts g••/g.DA of the reverse-transfer admittances as a function of frequency.
In the cascade configuration of the rf amplifier circuits, a
common-emitter stage drives a common-base stage. The
input admittance y. is, therefore, that of a common-emitter
stage. The forward-transfer admittance yt is that of a common-emilter stage times alpha. Because of the high-impedance drive source on the common-base stage, the output

admiltance y. is very low (0.06 x /0-' mhos) at low frequencies and is both negative and low at high frequencies.
Since the output admittance is low and may be negative, a
conjugate match cannot be obtained at the output. Practical
amplifiers arc possible however, provided that the sum
Yout + Y'oad is positive.
The reverse-transfer admittance yr for the cascade circuit is less than that for the single-stage commono..Cmitter

109

ICAN-5022 - - - - - - - - - - - - - - - - - - -_ _ _ _ _ _ _ __
circuit. The ratio of the imaginary terms of these admittances is 1/1200 at low frequencies and 1/35 at 100 MHz.
The ratios of the real parts and of the imaginary parts as
a function of frequency are shown in Fig. JO.

' ....

,
"

Q,.fg,cos

\

\

\

\

\
\

,
' ...... _---------

-zoo o.~,-jr_...........t;,7;0-j,--...........t;,i;0-,I--t-M;\n-t--........1nI
fREQUENCY-MHI

Fig. JO-Ratio of the real (conductance) and the imalfinary
(susceptance) parts of the reverse-transfer admittance
for a common- emitter slage 10 those tor a cascade
stage as a function 0/ frequency.

Although the y, is low for both the differential and cascade configurations, instability can occur in high-gain ampJitiers. A further consideration in high-gain circuits is that the

layout can contribute more feedback than the integrated
circuit. Shielding and layout therefore are of prime importance if proper advantage is to be taken of the low feedback of these circuits.
The computed y parameters for the CA3004 differential
amplifier are shown in Fig. II. The admittance parameters
for differential-amplifier operation of the CA3005 or
CA3006 are given in Fig. 12 and those for cascode-amplifier
operation of either circuit are given in Fig. 13.

VIDEO-AMPLIFIER CAPABILITIES
The CA3004, CA3005, and CA3006 integrated circuits
may be used as video amplifiers, as shown in Figs. 14(a)
and 14(b). A relatively.large number of external components is required, and the availability of internal-circuit
connections for these external components provides a large
degree of flexibility to the user with respect to such factors
as bandwidth, gain, power dissipation and peaking. In the
circuit shown in Fig. 14(a), R, should be equal to R, to
preserve the circuit balance, and C2 should be an adequate
bypass so that the noise factor and gain are not degraded.
For the cascode configuration shown in Fig. 14(b), C, is
an emitter bypass, and its reactance should be less than
1.5 ohms at the lowest video frequency to be handled.
In either cascode or single-ended differential-amplifier
configurations, the feedback is low. Each configuration provides good isolation from output to input; the high frequency performance therefore can be approximated from
the input and output parallel Rand C for a single stage or
from the total shunt Rand C between stages for an iterative
connection. The mid-frequency voltage gain can be computed from the familiar gooR,. product. As an aid to such
calculations, Table III gives the input and output parallel
Rand C and the absolute values of goo for the various circuits and configurations for operation at 1, 10, and 40 MHz.
For more precise, but more elaborate calculations, the "
parameters may ·be used for video-amplifier design.
NOISE PERFORMANCE
The noise -figure of the CA3004, CA3005 and CA3006
integrated-circuit rf amplifiers is a function of the de operating current and frequency, for both differential and cascode-amplifier configurations. The noise figure increases
both with an increase in current and with an increase in fre-

TABLE III
Input and Output Parallel RC Network, Transconductance, and Performance Data
for the CA3004, CA300S, and CA3006 Integrated-Circuit RF Amplifiers
VIDEO PERFORMANCE
(Simulated Iterative Connection)
Freq.
(MHz)

Input Parallel RC
Rin (ohms) Cin (pF)

Output Parallel RC
Rou. (o"ms)
CO"' (pF)

Transconductance, gm
(millimhos)

Higk-Freq. Mid-Band
Interstage 3-dB Point Voltage
RL (ohms) (MHz) Gain (dB)

CASCODE OPERATION (CA300S OR CA3006)
1
10
40

500
500
Isb

42
42
22

1
10
40

2500
IS00
670

16
13
10.5

1
10
40

6650
6650
2000

S
6.2
5.0

-1.67·X 10'
-1.67 X 10'
-6X 10'

3.0
3.0
3.0

7S
77

23

19.3

Measured

20

20.6

Calculated

150

5S

DIFFERENTIAL-AMPLIFIER OPERATION (CA300S OR CA3006)
10'
4 X 10'
2S00

4.0
4.0
7.6

20
20
IS.6

IS

19.5

Measured

16

20.0

Calculated

IS.4

17.2

Measured

15

IS.0

Calculated

500

DIFFERENTIAL-AMPLIFIER OPERATION (CA3004)
1.7 X 10'

10'
2 X 10'

6.5
6.1
6.S

7.S
7.S
7.6

Data obtained for circuits operated from ±6-volt dc supplies in operating mode D.

110

1000

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICAN-5022

COL.L.ECTOR CURRENT OF EACH TRANSISTOR

~1.2'

COLLECTOR CURRENT OF EACH TRANSISTOR;::I.25 mA

mA

~2

~

~I

~

~gC.I==F=~.~.9.~I.O~~~.~.~,~O~O~,~7-~~-+-7.~.~.OOO

oko,~r-~~E,.~o~~~~~,o~-r~ri~~-r~ri~,
FREOUENCY-MHz

FREQUENCY-MHI

(c)

(a)

I

COLLECTOR CURRENT
OF EACH TRANSISTOR

COLl.ECTOR CURRENT OF EACH TRANSISTOR stll.2!imA

~

~1.25mA

~IO

Yo· 90 + ib O

~8r---------'~1----~
g
~6

(0)

(b)

¥

3

COLLECTOR CURRENT OF EACH
TRANSISTORRSI,Z'mA

1,·101,. jb r

•eJ.

O•OO2

~~=;:;~~~T-~IO

IO~-r-7-r~~r-~

FREQUENCY-MHz

(e)
Fig. ll-Admittance characteristics of a CA3004 differential amplifier as a function of frequency: (a) Input admittance, y,; (b)

Output admittance, Yh' (c) Output susceptance, bo, above 10 MHz: (d) Forward-transfer admillance.
transfer admillance, Yr,

quency. For convenience, noise data were taken in a fixed
configuration as the negative supply voltage was varied. On

the data plots, the operating currents that correspond to the
various supply voltages arc included as a separate abscissa
to show that the noise figure is a direct function of operating current. Figs. 15 and 16 show representative noise-figure
data for tuned amplifiers in the differential and cascode
configuration, respectively. In each case, the input and out-

y/,'

(e) Reverse

put are tuned and the input is conjugately matched to a
50-ohm noise diode. Practically no change in noise figure
occurs with variations of the positive supply voltage V cc.
The curves in Figs. 15 and 16 show that, for optimum
single-stage noise performance, the operating current should
be low, which results in a low gain. Thus, in system applications of the tuned amplifiers, the operating current in each

stage should be adjusted to obtain the optimum overall noise

,111

ICAN-5022
8

~6 ..

COLLECTOR CURRENT OF EACH TRANSISTOR

~s-

'i-III +jb;

~l.2S filA

i

:::s 25

§

~~~~:~~~: CURRENT OF EACH TRANSISTOR::t:!I.Z5 inA

,

:201--------=_..,,--_
~

g

15

~

~ 10

€

(e)

(a)
COLLECTOR CURRENT OF EACH
TRANSISTOR'" 1.2'111"

0.02

/

TRANSISTOR ~ 1.251ft'"

/

I

/

~

/

u
1,0::1:

/

~

I

...

ID

-. ..

/

..... /

10.0
FREOUENCY- IIH.

',·V,+ jb,

2.~;;

/
bo/

0.1

0.2

COLLECTOR CURRENT OF EACH

I

'0.90+1 110

~
..

. ..

..

-0.01

1000

100.0

'---;---l.-+.~.-'--+"""""'.~."'.'"

0.1

1.0

-~I '--+--l.~.-!.-'-~--::

10
10
FREQUENCY-IiHa

100

(d)

(b)

'r·., + III,

COLLECTOR CURRENT OF EACH TRANSISTOR

+0.0003

~.I.25mA

+0.003

~

3+0.0002

i

~

i
~

+0000'

-b,
,

'0

FREQUENCY- MHz

(e)
Fig. 12-Admittance characteristics 01 Q CA3005 or CA3006 differential amplifier as a function oj frequency: (a) Input admit·
lance, y,; (b) Output admittance, YD," (c) Forward transfer admittance, YI,' (d) Reverse transfer conductance. gr;
(eJ Reverse transfer susceptance. hr.

figure by considering the gain and noise figure of the first
stage and the noise figure of the second stage. The operatingcurrent adjustment can be accomplished by a change in the
negative-supply voltage (VEE) or by means of the bias connections that are available.
Fig. 17 shows the noise figure as a function of the source
resistance for a CA3005 or CA3006 used as a differential
amplifier at an operating frequency of 12 MHz. The equa-

112

tion given in the figure can be used to predict liaise performance as a function of source resistance for dc operating
conditions. The load resistor R,. of the circuit is 2200 ohms
and RN = 800 ohms. (RN is the equivalent noise resistance).
COMMON-MODE REJECTION RATIO
The common-mode rejection ratio of a differential amplifier, defined as the ratio between the full differential gain

_________________________________________________________ ICAN,5022
l'1

~ 100
~

I

-;. eo

STAGE COLLECTOR CU./tRENT

~

2.5 mA

Ji"lIi+jbj

STAGE COLLECTOR CURRENT ~ 2.5 mA
Yf:9f+jbf

"

"

16

.... \

12

\
u

~

omo.,;--;,t--t--:.-::lF""l'=--t.--:-.-1;,,;1;0-7,-h.t-"Lio------t- _. H t100

0

~-20!;-O.l;--;t--i.rl.-;.r;)I.O,-+--i.--:-.",.7.;,o;--t,-T.--:-.-';,oilio,-1--t-.,.rt'lv,OO

FREOUENCY- .. H,

FREQUENCY-MHI

(e)

(a)

I0'2~'"
o

STAGE COLLECTOR CURRENT:= 2.15 mA

Jo. to +,beI

STAGE COLLECTOR CURRENT ~ 2.5 rnA

,r·j"

2.0

/200

~

I
J

z

IIr/

~

8 0.1

I

1.0

~

§
W

-b,
I

z

-I~LJ-j,.-t.-i6h.r'I-t--:.H6-l.-L'O-!-+H.L+---7."i--l-'~OOO
FREQUENCY -

UH,

~
~

I

I

100

I

(d)

(b)

Fig. I3-Admittance characteristics of a CA3005 or CA3006 cascade amplifier as a function of frequency: (a) Input admittance.
y,; (b) Output admittance, Yo,· (c) Forward transfer admillance, YI (d) Reverse trallsfer admittance, Yr.

+Vcc

RL

>--+--1I~PUT
c3

'oJ

(OJ

Fig. 14-Schematic diagrams showing the use of the integrated-circuit r/ amplifiers as video amplifiers: (a) CA3004 in a differential-amplifier configuration,' (b) CA3005 or CA3006 in a cascade-amplifier configuration,

113

ICAN-5022 - - - - - - - - - - - - - - - - - - - - - - - - - - 10

TABLE IV
Common-mode Rejection Ratio for the 1:A3004, CA300S, and
CA3006 Integrated-Circuit RF Amplifiers

INPUT CONJUGATELY MATCHED TO
son NOISE DIODE

~

CA3004
CA300S or CAJOO6

I

::! •

..

Operating frequency
Load resistance, RL

::>

;;:

...!!! 4

AI -SS"C

AIZS"C

AIIZS"C

102 dB
108 dB

98dB
WI dB

101 dB
107 dB

=

=

1 kc/s.
1000 ohms in each collector.

o

z

1·~F~RE~Q~UE~N~C=Y7.(I~I.7.,.~M="~.------------------~-----,

OL---~0~--~I.~,.~--~2~A----~.~~----~~1
,TOTAL DC, CURRENT!(Iccl-m~ - - - 1
2
4
6
8
ro

NEGATIVE DC SUPPLY VOLTS -

ViE

FiR. I5-Representative noise performance of the CA3004,
CA300;, or CA3006 operated in a differential-amplifier
configuration (operating mode D).
10

OPERATING MODE 0

INPUT CONJUGATELY MATCHED TO
50n NOISE DIODE

200

600

1000

1400

1800

SOURCE RESISTANCE (RS)-OHMS

Fig. 17-Noise figure of the CA300; or CA3006 in a
diDerential-amp/ifier configuration as a function
of the source resistance (operating mode D).

~6
;;:

...

i5z 4

0'L-----~0~--~1.2~2~--~2.+.4~--~.~.9----~5.35
~OTAl EMI~TER CURR~NT Q3-m,A

2

4

6

8

10

NEGATIVE DC SUPPLY VOLTS - VEE

Fig. 16-Representative noise performance 01 the CASODS
or CA3006 operated in a cascode~mplifier
configuration (operating mode D).

and the common-mode gain, is a useful performance characteristic. The common-mode rejection is a function of the
ratio of the impedance of the constant-current transistor Q,
to the load resistor. The common-mode rejection decreases
if the signal applied is large enough to saturate the constant-

Fig. 18 shows the single-ended common-mode gain'for the
CA3004, CA300S, and CA3006 as a function of frequency.
(Fig. 19 shows the method used to detennine the singleended common-mode gain.) The common-mode rejection
decreases with increasing frequency when the CA3004,
CA300S, and CA3006 are operated with a single-ended
output.
GAIN CONTROL
The gain of the CA3004, CA300S, and CA3006 circuits
may be controlled in either of two ways: (I) The negative
voltage applied to the base-bias resistor R. can be adjusted
to vary the current in transistor Q. or (2) A differential offset
voltage can be applied to transistors Q. and Q" In both
techniques, the gain-control voltage has a ground reference
in a two-supply system, and maximum gain is obtained at 0
volts. The first method provides greater gain-control range
but also requires more control voltage than the second
methud. Figs. 20 and 21 allow the typical gain control as a

current transistor. The maximum peak-to-peak input volt-

age, therefore, is a function of the supply voltages and the
bias connections of the constant-current transistor. The
common-mode rejection for a I-kHz signal is shown in
Table IV.

114

*SingIe--ended common-mode gain: The ratio of the change in the

~iJ:e;:s~~~~ ~U!~~~n';EI~~g:l1e~t:a~::1nfrg~in~~e~oft~:U!p~fi~jn£

multaneously to both inputs of the circuit, i.e .• single-ended common-

mode gain =/:lVln/AVollu as shown in Fig. 19.

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ICAN-5022
DC GAIN-CONTROL VOLTAGE
TO BIAS NETWORK OF03-VOLTS

40
POSITIVE DC SUPPLY VOLTS· +6V
NEGATIVE DC SUPPLY VOLTS· -6V

30

-6

-5

-4

-3

-2

-I

RL·IOOOO

~---------

20

DIFF. GAIN
(SINGlE-ENDEDI

-10

-20

10

a
10

~20

I

z

~30

60
~

60~~--~.~.~.~--t-~.~.~.~~r--1.~.~.~
0.1

1.0
10
FREQUENCY-MHz

100

Fig. 18-Single-ended common-mode and diUerential-mode
gain. of the CA3004, CA3005, or CA3006
as a function of frequency.

Vee
+6V

____________________________-J-ro

Fig. 2O-Gain-control characteristics of the CA3005 or CA3006
as a function 0/ the de gain-control voltage applied
to the bias networ" o/transistor QJ.

Q3 bias networks are the same, the gain characteristics for
the CA3004 are nearly the same as those for the CA3005
and CA3006. Fig. 21 shows that in the offset method of gain
control the gain range is dependent on the polarity of drive.
For maximum gain-control range on a single-ended amplifier, the common-collector transistor should be cut off
(negative voltage applied to its base). Because of the emitter
resistors, R. and R" the CA3004 circuit will require more
dc voltage for the same gain reduction as the CA3005 or
CA3006, and the dc voltage required will be a function of
the initial operating current.
GAIN-CONTROL VOLTAGE (Veal-VOLTS

0.2

0.3

0.4

0.5

I~
VEE
-6V
SINGLE-ENDED COMMON-MODE GAIN· .o.vOUT/OvlN

Fig. 19-5chematic oj the circuit used to determine

the single-ended common-mode gain.

function of voltage for the CA3005 or CA3006 for the two
methods. Fig. 20 gives the gain-control characteristic for
the CA3005 or CA3006 when the gain-control voltage is
applied to the base-bias network of transistor Q•. Since the

-40

-50

-60L---------------------------------~

Fig. 21-Gain-control characteristics of the CA3005 or CA3006

as a function of the dc oDset voltage, Vu . applied to the
diOerential pair of transistors QJ and Q•.

115

ICAN-5022 - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ __
The maximum gain-control range that can be provided
by a reduction in the current of transistor Qa varies with
frequency as shown in Fig. 22. The maximum gain-control
range that can be obtained is dependent on the full gain
used, the circuit loading, and the external-circuit layout.
-20
OPERATING MODE 0

ferential-amplifier and cascode-amplifier configurations. The
amount of cross-modulation distortion is determined by the
two-generator method with the input of the circuit under
test driven from a 50-ohm source and with its output tuned
to the frequency of the desired carrier. The amplitude of
the undesired-carrier input voltage is that necessary to produce 10 per cent cross-modulation distortion for each
manually determined gain-control setting.
Differential-Amplifier Configuration 5 - The availability
of internal connection points make possible several methods
of gain control in differential-amplifier configurations of
the CA3004, CA3005, and CA3006 circuits. Only two of
these methods need be considered, however, to obtain an
adequate evaluation of the cross-modulation characteristics.
These include (I) the variation of the current in the con-

-BOI=O-""----=20::-..c:;.---4~O:----:6=O--:ao'=-..,."OO
FREQUENCY -

MHz

Fig. 22-Maximum gain control provided by variations
in the current through QJ as a junction of frequency.

A large part of the variation in the maximum gain control for the different circuits results from differences in the
initial gain of the various circuits. Capacitive feed through
appears less for the cascode than for the differential-amplifier configuration.
The following discussion of cross modulation describes
variations of the two gain-control techniques.

CROSS-MODULATION AND MODULATION
DISTORTION
Cross-modulation and modulation distortion are important considerations in the selection of an amplifier for use
in AM systems. Cross-modulation distortion refers to the
transfer of modulation from an undesired carrier to the
desired carrier by nonlinearities in the amplifier. Modulation
distortion is a change in the modulation on the desired carried caused by the same amplifier nonlinearities that produce
cross modulation. The two forms of distortion are rel,ated
by the following equation:

D,

K

V,':V,' =

3

8m : I

where D, is the per cent of distortion in the modulation on
the desired carrier (Le., the modulation distortion), K is the
per cent of cross-modulation distortion, V, is the amplitude
of the desired-carrier voltage at the input, V, is the amplitude of the undesired·carrier voltage at the input, and m is
the per cent of modulation of the desired carrier.
When D, and K are equal and m is 100 per cent, the ratio
of V, to V, is 1.64. In the following paragraphs, data are
given for only the cross-modulation distortion. The modulation distortion can be predicted from these data, however,
on ine basis uf ine relationship uf V 1 i.u V 2' For t:xample, in

Fig. 23, V, is given as 22 millivolts for a gain of 0 dB. The
value of V" then, is 1.64 x 22, or 36 millivolts.
Figs. 23 through 27 show the cross-modulation distortion
of the CA3004, CA3005, and CA30U6 integrated circuits as
a function of their gain-control characteristics in both dif-

116

stant-current transistor, Q" and (2) the use of an offset
voltage to produce an unbalance in the differential pair of
transistors, Q, and Q,.
Fig. 23 shows the cross-modulation distortion character-

istics of the CA3004, CA3005, and CA3006 with the differential pair of transistors balanced and with age applied
to the constant-current transistor. Because of the increased

linearity that results from the emitter resistors R, and R"
the CA3004 has improved cross-modulation characteristics
at high current. The interfering signal voltage required to
produce 10 per cent of cross modulation distortion is practically a constani over the entire age range for the CA3005
and CA3006. The value of the interfering signal voltage
(approximately 15 mv) for the CA3005 and CA3006 is
twice that calculated from the logarithmic transconductance
characteristic of a single transistor.
UNDESIRED CARRIER INPUT VOLTAGE-MILLIVOLTS RMS
:5
6
10
30
60
100
300

600

m-20

!

0-30

---CA3004

~

--CACfJcP605 OR

~-40
z

~

°-50

-60

"-.......... _ - - - - - - -

-70

Fig. 23-Gain control as a function of the input voltage from an
undesired carrier that will produce cross-modulation distortion
of 10 per cent for balanced differential-amplifier operation
of the CA3004, CA3005 and CA3006. The gain-control voltage is applied to bias network of the constant-current transistor.

Fig. 24 shows the cross-modulation distortion characteristic of the CA3005 and CA3006 when an offset voltage is

applied to control the gain. The improved cross modulation
performance at - 5 dB gain is coincident with an inflection
point on the curve of tranconductance as a function of input

offset voltage. This point occurs at an offset voltage of approximately 50 millivolts.

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ICAN-5022
+6 V

volts is employed and age is applied to the constant-current
transistor. The introduction of the unbalance reduces the

-6 V

VBB

UNDESIRED INPUT VOLTAGE -MILLIYOLTS RMS

3610

I

o

FREQUENCY OF DESIRED
CARRIER. 12 tlHI

-to

F~~~~~ ?f6U:~~SIRED

OPERATING MODE 0

m

i

3060100

300

r

,'POSITIVE GAIN-CONTROL VOLTAGE. Vee

'"~I

-20

(AT TERMINAL II

-------

!-30

cross-modulation distortion to approximately 10 dB less
than that of the balanced circuit. This reduction in crossmodulation distortion, however, is accompanied by a decrease in gain of approximately 5 dB.
Cascode Configurations - Cross-modulation data for
cascade configurations of the integrated~ircuit rf amplifiers are given for only the CA3005 and CA3006 circuits.
because the CA3004 circuit is not designed for this type of
operation. When the C A3005 or CA3006 is operated in the
cascode configuration, gain control may be provided by
either of two methods: (I) A negative voltage may be applied
to the base of transistor Q, or (2) A negative voltage may
be applied to the base of transistor Q,.
In the first method, the gain is reduced by the application
of a negative-going voltage at terminal 12. As the amplitude
o! this voltage is increased to the value required to cut off
transistor Q:\. the gain of the circuit is decreased. The crossmodulation distortion characteristics for this type of gain
control are shown in Fig. 26. The cross-modulation characteristics are comparable to those of a single transistor
having a bypassed emitter resistor.

The cross-modulation distortion characteristics obtained

~

for the second method of gain control are shown in Fig. 27.
No improvement in cross-modulation characteristics over
those obtained for the first gain-control method are observed,
although the age range is greater.

~ -40

-'0
-GO

Fig. 24-00;11 control as a function of the undesired-carrier
voltage that will produce 10 percent cross-modulation
distortion for diDerential-ampli/ier operation 0/ the
CAJ005 or CA3006 when gain con/roJ is provided
by the application 01 an ooset voltage to the
differential pair of transistors.

The cross-modulalion performance is improved by the

offset of the differential pair of transistors. Fig. 25 shows
the cross-modulation data when an initial offset of 50 milliUNDESIRED CARRIER INPUT \/OLTAGE-MILUVOLTS RiotS

0'

3

6

10

30

60

100

300

MOOED

OF DESIRED CARRIER
F UNDESIRED CARRIER
V
VOLTAGE APPLIED TO
NII.l2

MIXER CAPABILITIES
The CA3004, CA3005, and CA3006 integrated circuits
may be used as mixers, modulators, and product detectors.

The schematic diagrams in Figs. 28(a) and 28(b) illustrate
the use of these circuits in mixer applications. The oscillator
input is injected at the base of transistor Q3 (because there is
no direct-hase connection available on the CA3004, a higher
oscillator drive voltage is required for this circuit); the rf
input is injected single- or double-ended to the bases of
transistors Q1 and.Q~. The use of a center-tapped inductor
for the output tuned circuit (double-ended) allows the common-mode signal of the oscillator to be balanced out so that
the oscillator will not overload subsequent stages, and provides carrier suppression for modulators.
The gain performance and generation of harmonics in

the CA3004, CA3005, and CA3006 mixer circuits are dependent on the amplitude of the oscillator drive signal and
the de bias. The expression for product detection or frequency multiplication in the CA3005 or CA3006 (collsult
Fig. 29) are determined as follows:
.=~~L
-60

Fig. 25-Gain control as a function ollhe input voltage
from an undesired carrier that will produce cross
modulation distortion of 10 per cent, for u
di/Jerenlial.umplifier configuration of the
CA3005 or CA3006 having a 50-millivolt
oOset and with the gain comrol voltage
applied 10 the bias network of the
conslant~current transistor.

ru

where e. is the output voltage, e, is the differential input
voltage, goo is the transconductance of the differential pair of
transistors (Q, and Q,), and ZL is the load impedance (total
between caneelars), For a balanced circuit, the transconductance is given by
(2)

The term I., is used to represent the collector current of

117

ICAN-5022 - - - - - - - - - - - - - - - - - - - - - - - - - - - UNDESIRED INPUT VOLTAGE-MILLIVOLTS RMS

I

o
-10

36

to

30

60100

300

FREQUENCY OF DESIRED
CARRIER. 12 MHz
FREQUENCY OF UNDESIRED
CARRIER· 16 MHI .
OPERATING MODE 0

-20

-'0
-40

-50
+6 V
-60

-6 V

-70

Fig. 26-Gain control 0/ the CAJ005 or CAJ006, in Q cascode configuration, as a function of the IIndesired-carrier voltage that
will produce 10 ~r cent cross-modulation distortion when the gain is controlled by a negative bias voltage applied to
the base of transistor Q, The schematic diagram illustrates the circuit configuration.

+6 V

-'0
-20
m

r

Q-30

~

a::. -40

z

~

-'0
-60

-6 V

-70

Fig. 27--Gain control of the CA3005 or CA3006. in a cascade configuration. as a function of the undesired-carrier voltage thai
will produce 10 per cent cross-modulation distortion when the gain is controlled by a negative bias voltage applied
to the base of transistor Q,. The schematic diagram illustrates the circuit configuration.

Fig. 28-Circuit diagrams for the use 01 the integrated--circuit rl amplifiers as mixers (operating mode D): (a) CA3004,' (b) CA3005
orCAJ006.

118

---------------------------------------------------------ICAN-5022

lFer

---

the e,e, product. The linearity of the CA3006 is illustrated
by the curve of the conversion transconductance as a func-

tion of the oscillator voltage, shown in Fig. 30. (Although the
curve is plotted on logarithmic paper because of the wiae

~

range, the relationship is linear.) The gain reaches a maximum value at approximately 2.5 volts rms. Because measurement inaccuracies prevent the use of this curve to
determine harmonic generation, spurious-signal measure..

pll~~

ments were taken on CA300S and CA3006 mixer circuits.
For these measurements, the rf input was untuned and

'he oscillator and if frequencies were held constant. For
a fixed amplitude of oscillator injection on terminal 3, the
rf was varied in frequency. and the amplitude of the responses was recorded. The results are shown in Table V.
The spurious signals generated are a function of oscillator
drive. A low oscillator drive (0.1 volt rms) produced only
three spurious signals for which the rejection was less than
70 dB down. These measurable spurious responses were
third-order products that involved the second harmonic of
either the oscillator or rf signal. The relative if gain increases
with decreasing oscillator drive because of lower mixer gain.

---'----+:1-::---'

qIff

Rf

Fig 29--Circuil diagram oj a CA3005 or CA3006
balanced mixer (operating mode D). The equation ..
derived for product detection or multiplication
are based on this circuit.

10

transistor Q3 and may be expressed as
10 = g~. e,
(3)
where gn'2 is the transconductance of transistor Q3 and e2 is
input voltage applied to transistor Q,. The output voltage,
eo, therefore is given by the foIlowing equation:
"q
eo = 2KT e, e. gm, ZL

(4)

Eq. (4) is a general expression for the output voltage of
the mixer having input signals e 1 and e 2 " With emitter degeneration in the constant-current transistor (Q3)' gm2 is

essentiaIly constant for a sufficiently large emitter current
(> I rna); the current 10, iherefore, foIlows the applied voltagee,.
When e 1 and e 2 are sinusoidal and g", is a constant, the

input signal voltages are given as foIlows:

el = EI ejw1t

* e+ EJ

(5)

(6)

With the substitution of these relationships, the equation
for the output voltage the CA300S or CA3006 now becomes
n

=

~ gm Z [E E ej(·,+·,l,
2KT
2 L
I'

o

'"
~

::i
I

~

2

~

lill
o

r
z
o •

~

U

j ",,\

* is the conjugate of E" and E,
* is the congugate of E,)
(E,

e

FREQUENCY (t I· 20 MHI
CONSTANT RF SIGNAL
CONSTANT LOAD (aoooa)
~

2

'-_.....,:--_.....,,---!--:!.....l.__-!-_ _-!-_-:---;-....

0.1
0.01

6
e 0.1
OSCILLATOR VOLTAGE-VOLTS RMS

6

B

I

Fig. JO-Conversion gain of a CAJOOS or CA3006 mixer circuit
as a function of the oscillator voltage.

+ E Ee-i(.,+.,l'j
I

•

+E
E e-j(·'-~)'j
+~
2KT'"«m , ZL [E I E.ej(·,-·,l'
-I 2

(7)

Eq. 7 gives the output voltage for a CA300S or CA3006
used as a product detector or multiplier. (Note that nnly the
two sideband frequencies are included in the output). The
requirements for product detectors or multipliers are that
the circuit should be biased in a linear region with a smaIl
signal voltage applied. Because aq gm./2KT is essentiaIly
constant, the gain of the mixer is determined from ZL and

The common-mode canceltation of the oscillator signal at
the collector outputs is indicative of the carrier suppression
that can be provided in modulators. The carrier suppression
is function of output tuned-circuit balance and the transistor offset voltage .. The contribution of the offset is illustrated in Figs. 31 and 32 which show the output signal as
a function of the offset voltage for the CA3004 and for
CA300S and CA3006 respectively. These data were obtained on circuits operated with a balanced output timed
to the oscillator frequency.

a

119

ICAN-5022
TABLE V
Response of a CA300S or CA3006 Mixer to Spurious Harmonics
Diff.-Freq.

Diff·-Freq.
Signal
Freq·.I.

Vou

Output (dB

aI/Mm.J

Frequency

(MHz)

(rm....Us)

relatil/e to
I. -I.)

fo - f~
Ilf

1.0
0.659
1.159
1.329
1.988
2.318
2.659
2.813
3.977

21. - f.
21. - 21x
2f:.: - 2£.
fJl: -f.
2£. - fa
21x - 3f.
f. - 21.
4.309
31. - f.
{:II: - 3E o
5.627
'5.977
41. - f.
f 0 = 1.659 Me/s; Vou

-=

Vote

OutPUI(dB

allerm.J
(rmsv.lls)

,elative to
I. -I.)

1
0
0.7
1
7.5
0.7
-53.1
1
0.7
-76.1
1
0.7
-75.5
1
0.7
1
0
0.7
-31.7
1
0.7
-79.6
1
0.7
1
-31.7
0.7
-35.8
1
0.7
1
-38.5
0.7
-38.9
0.7
1
oscillator injection voltage,

0
10
-53.1
0
-35

-

35
-59.3
-57
-63

Diff·-Freq.
You

Oulpul(dB

(rms ••Us)

relatioe to
I. -I.)

at term. 3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3

0
18
-54.9
0
-39.7
-39.7
-74.7
-74

Diff··Freq.
Output (dB
V ...
allerm.J relative to
(rms ••IIs) I. - f.)
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
.0.1
0.1
0.1
0.1

0
27
-52.3
0
-47.8
-47.8

All blank s _ indicate dilferenc:e-fRquency outpUl1DOl'O than 70 dB below the f. - f. output.
POSITIVE DC SUPPLY VOLTS (Vee )- +6
NEGATIVE DC SUPPLY VOLTS (VEE)·-6
FREQUENCY (f). 1.6 MH.

co

.

fj

4

II:

~

0

>

:J

0
> 100
8

i
I

....~

4

=
>

I-

~

I-

10
8

:>
0

0

a:
4

•

..u

::I
~
0

0

~1~.-j-1~2~-~'0~-~8~-~e-=-4~~~~~0~2~0~4~0~6~0~8~0~10~0~'20
DC OFFSET -

MILLIVOLTS

Fig. 3J-Caneellation of the oscilljltor signal at the output of a
CAJOO4 mixer os a function of the de offset voltag•.

UMITER CHARACTERI5flCS

CiH.nmiial-Amplifliri Cliiiifiiiiiiithm -

The

diffcrcnti;l~

amplifier. driven by a constant-current transistor, is probably
the optimum circuit configuration for bipolar transistor limiters. The advantage of such circuits in limiter applications
is that collector saturation of either transistor Q, or Q, can
be avoided because of the action of the constant-current

120

ro

~-'

IE

~

•

>

0

!;
!;

100

0

!:;

..

6

..

!:;

.

1.6 MHz

1:

...
..

e

:.
::;
-'
i
I

~

rnlOOO
8

IE

l:

FRE()UENCY Cf)

o
~

o
o

;100:
~

r

co

o

~~7~-6~-~5~-~4~-~3~-2~~-I~~0~1~0~2~0~30~4*0~&O~~.~0~70
DC OFFSET- MILLIVOLTS

Fig. 32-CanceUation of the oscillator signal at the output of a
CAJOO5 or CAJ006 m/Jeer as a function of the de offset voltage.

transistor Q,. Figs. 2 and 3 show typical limiting characteristics for the CA3004 and for the CA300S and CA30<.6
rc:;pcctivcly. Fer the Cl'.300S and C.A..3006 (ne emitter degeneration). "hard" limiting is achieved for a peak-to-peak
input of 300 millivolts for all values of totsl de current (Icc).
For the CA3004, the input voltage required for "hard" limiting is a function of Icc because of the linearizing effect of
the degenerative emitter resistors. R. and R,. As saturation

ICAN-5022
TABLE VI
Limiter Performance of a Differential Amplifier

Voltage Gain
With Emitter
Degeneration
Maximum
V Supply
(IJOUs)

(rnA)

Load
(ohms)

Maximum
Tuned
Load
(ohms)

0.5
1.0
2.0
3.0

12000
6000
3000
2000

24000
12000
6000
4000

lei

+ leI

RL

= Vsupply
leI

RL
gmRL

Resistive

+ Ie,

low~level

Degeneration

(dB)

Resistive

(dB)

Resistive
Load

Tuned

Load

Tuned
Load

31
28
25
22

37
34
31
28

.15
35
35
35

41
41
41
41

Load

Resistive Load

= 2 Vsupply Tuned Load
leI + Ie,

= voltage gain

must be prevented for good limiting, a maximum load resistor and

Voltage Gain
Without Emitler

voltage gain exists for a given

Ir.(~

and

positive supply voltage. Table VI shows the maximum resistor values and voltage gains usable for Vr.r. = 6 volts, for
the three circuit types. The low-level transconductance can
be obtained from the slope near the origin for the curves
shown in Figs. 2 and 3. The max.imum voltage gain is inde-

pendent of I,~ in the CA3005 and. CA3006 and is dependent
on I"r in the CA3004. Figs 5 through 8 show the 1"0 currents
and transconductance for optional operating conditions.
When the differential amplifier is used for limiting, the
emitter-to-base breakdown voltage for transistors Q, and Q,
cannot be exceeded without degradation in performance.
For the CA3004, CA3005, and CA3006, this voltage including a safety margin should not exceed 2.5 volts rms.
Either of two methods may be used to prevent this value
being exceeded: (1) Make sure the preceding stage limits
before the input voltage reaches 2.5 volts (maximum voltage
gain per stage approximately 20 dB), or (2) add one junction
diode (D,), as shown in Fig. 33 (this allows a maximum usable voltage gain consistent with good limiting and stability).

load). Limiting characteristics for both cases are shown in
Figs. 34 and 35. The data in Fig. 34 are obtained with
a collector load of 500 ohms. This limiting characteristic
is "soft" and is acceptable over only a 20-dB range. The
peak-to-peak voltage at the collector is never large enough
to cause saturation. The limiting characteristic shown in

Fig. 35 is obtained with a collector load of 5000 ohms, and
saturation of transistor Q 1 occurs. The limiting is harder and
covers a broader range, but severe tuned--circuit loading
occurs.
1.0
0.8
0.6

OPERATING MODE D
COLLECTOR LOAD-soon
FREQUENCYCf)-1.7MHz
OUTPUT MEASURED ACROSS 50.(1

en 0.3
:0;

'" 02

~
I

§!
0.1
... 0.08

~O.o6

g

50'"

§o.oz

-6V

O.O:,ko--"';I;;---t.4o;--;6!noc----;*'OO;-~20;k,;O-..
40ivo"6d;oo""'0;/;0"O-,·20;;/OO~-4:ut000
INPUT YOLTAGE-MILLlYOL TS RMS

Fig. 34-Limitilrg characteristics and circllit diagram
of a CAJOO5 or CA3006 cascade limiter hal'ing
a 500-ohm collector load impedance.
-VEE

Fig. 33-Circuit dial(ram of a CA3005 or CA3006 diDerentialamplifier limiter that uses a diode to provide
input overload protection.

Cascode Ampliliet - The limiting characteristics of the
CA3005 or CA3006, when used as a cascade amplifier are
dependent on the current limiting in transistor Q, or the
voltage limiting of transistor Q, (high-impedance output

APPLICATIONS OF THE RF AMPLIFIER
CIRCUITS
RF AMPLIFIER
Figs. 36, 37, and 38 illustrate the use of the CA3004, the
CA3005 or CA3006 differential-amplifier configurations,
and the CA3005 or CA3006 cascode configurations, respectively, as single-ended rf amplifiers. Adjustable matching
networks, derived from the y parameters, are included in
each circuit. The values of the adjustable components as

121

ICAN-5022 - - - - - - - - - - - - - - - - - - - - - - - - - - - Vee
+6 V

OPERATING MODE 0

COLLECTOR LOAD· 5000 .Q

OUTPUT

l/

FREQUENCY (f) • 1.7 MHz

OUTPUT MEASURED ACROSS 50

a

O'II.~O~-.!20;;----,4;i,O.-t..O"'IOO""--;;20"'O----;4;i;oo"60.!;;;O-;;,O;!;O"O"C2;;;O"'OO"4;;;O,i;OO"6000~con!,OOOO
INPUT VOLTAGE-MILLIVOLTS RMS

Fig. 35-Limitillg characteristics ana Circuit diagram of a CA3005 or CA3006 cascade limiter having a 5000·ohm collector load
impedance.

AGe

CIRCUIT ELEMENTS
L,

FREQUENCY

L,

(MHz)

(I:H)

C,
(pF)

(I1H)

C,
(pF)

.10

1.8-2.7
0.15-0.3

2-10
0.9-7

1.8-2.7
0.1-0.2

2-10
0.9-7

100

POWER GAIN PERFORMANCE
POWER GAIN
(dB)

DC
SUPPLIES

100 MHz

30 MHz

(volts)

12

24

±6

Fig. 36-Circuit used to determine the rf performance capabilities of a CA3004 integrated·circuit rf amplifier.

AGe

+ vee

CIRCUIT ELEMENTS
FREQUENCY

L,

(MHz)

(11H)

30
100

1.2-2
0.4-0.7

C,
(pF)
5·40
1-12

!p.H)

C,
(pF)

1.2-.1.
0.25-0.5

1.5-20
1-12

L,

POWER GAIN PERFORMANCE
DC
SUPPLIES

POWER GAIN
(dB)

(volts)

30 MHz

±6
±4.5

29
27.8
23.0

±.1

100 MHz
1R

16
!I.5

Fig. 37-Circuit used to determine the rf performance capabilities oj a CA3005 or CA3006 integrated-circuit rf amplifier in a
differential-amplifier configuration.

------------------------------ICAN-5022
AGe

+ Vee

.OOI5~OI5~

CIRCUIT VALUES
FREQUENCY

L,

(MHz)

(".Il)

30
100

0.3·0.6
0.07-0.12

L,

C,
(PF)

(p.ll)

C,
(pF)

14-150
5-40

0.8-1.4
0.15-..1

5-40
5-40

POWER GAIN PERFORMANCE

DC

POWER GAIN

SUPPI.lES

.OOI5~

(dB)

(valls)

30 MHz

±6
±4.S
±3

36
33
21.5

JOO MHz

20
18.5
15.0

Fig. 38-Circuit used to determine the rl performance capabilities of a CA3005 or CA3006 integrated-circllit rf amplifier in a
cascode configuration.

well as typical power gains are also shown in the figures. A
conjugate match at the input is provided for all configurations. A conjugate match at the output is impossible for the
cascade configuration 

..5

!!:

10

Fig. 41-Frequency-response characteristics of the
12-MHz· limiting amplifier shown in Fig. 39 .

..

~~

FREQUENCY- MHz

.,

Fig. 44--Frequency-response characteristics 0/ the 12-MH:t
gain-controlled amplifier shown in Fig. 40.

.01,--+-"~,-;,C"-",,,--,.-!.-7,-;,~-7-7.-:,",;-'--':-""'-;,-:,"
I

10

100

1000

10000

RMS INPUT-MICROVOLTS

Fig. 42-Limiting characteristics of the 12-MHz
limiting amplifier shown;n Fig. 39.

50

INPUT SIGNAL 12MHz .30% MODULATED
DETECTOR OUTPUT FILTER BANDWIDTH

~

5.0 kHz

DETECTED SIGNAL
GAIN CONTROL
STARTED

."

DETECTED NOISE OUTPUT

i 8I

~ ~

8'

10
100
1000
INPUT SIGNAL-MICROVOLTS

Fig. 43-0utput signal-Io-noise ratio as
a fllllction of the in"lIt signal for the
12-MHz gaill-controlled amplifier shown in Fig.40
when gailL control;s used in ollly the first stage.

loooe

distortion and drive levels is readily established.
Feedback may cause oscillation or unbalance; care must,
therefore, be taken in the external-circuit layout design .
Shielding must also be provided for both the double-sideband
modulator and product detector.
The circuit diagram of the double-sideband modulator is
shown in Fig. 48. The modulating signal is. applied singleended to the differential pair of transistors, Qt and Q:!, and
the oscillator signal is applied to the base of transistor Q,.
The output is taken double-ended from the balanced transformer, T:!. The carrier suppression is a function of bilateral
symmetry (offset, output-transformer balance, and modulation drive circuits) and the modulation-to-carrier drive ratio.
With the external-circuit bilateral symmetry carefully preserved, the carrier output is approximately 25 dB below the
double-sideband output for CA3006 units (offset 2 I millivolt) operated with a drive v, = 10 millivolts rms and v, =
31.5 millivolts rms. Although the signal-to-carrier ratio of
25 dB represents an inadequate rejection for most systems
(40 to 60 dB is usually required), this value relaxes the filter
requirements from those necessary on more commonly used
single-sideband modulators. An improvement over the 25-dB
ratio is obtained if the modulation drive v t is increased and
the carrier drive v::! is decreased, because the output is a function of the product of VI and v,.
The circuit diagram for a product detector is shown in
Fig. 49. The product detector which provides the advantage

125

ICAN-5022
+6 V
'6 V

1.75MHr

Cf

T,
I

:6'i-'-"""t";,([H

2g~~,ctll~

-6 V

-6 V

(0)

I"

Fig. 45-Circuit diagrams for the use of CA3004, CA3005. and CA3006 integrated circuits as balanced mixers to convert an
input frequency of 20 MH z to an output frequency of 1.75 MHz.

NOISE FIGURE

M

~

w

~

U

OSCILLATOR DRIVE VOLTAGE AT TERMINAL No.3-VOLTS R M S

Fig. 46-Power gain and noise figure as a function of the oscillator drive voltage for the CA3005 or CA3006 balanced mixer.
+6V
OSCILLATOR fREOUENCY (lose)- 2L75MHz
INPUT SIGNAL FREOUENCY(I,tl" 20MH.
INTERMEDIATE fREQUENCY (1"l·I.75MH.

'3

Uo)------l----+~'Cf

POWER GAIN

~24
~

~20
16

~ 12

NOISE FIGURE

"

.O'/J-f

~ a

560-B70
pf
10

2.0

3,0

1

-1

4.0

OSCILLATOR DRIVE VOL TAGE AT TERMINAL No.2-VOLTS RMS

Fig. 47-Power gain and noise figure as a function of the
oscillator drive voltage for the CA3004 balanced mixer.

126

___9,,'3"

OUTPUT

""
I

"~

T2

BIFILAR

.-_+-.-~

"=

-sv

T,

9.6:1"2

50

~lrN.

1osCC~~~~~~R
1.75 MHz

-=-

Fig. 48-Circuit diagram for the use of the CA3005 or CA3006
as a double-sideband, suppressed·carrier modulator.

-----------------------------ICAN-5022
of a double-ended out-of-phase output, is driven through a
SO-ohm adjustable feed by the double-sideband signal from
the modulator. The levels of V 11 V 21 v", and Vs are altered to
establish the relationship between the harmonic distortion
and drive levels as well as gain values for typical operation.

The results are shown in Table VII. Overdrive by the modulation (v,) or the modulated signal· (v,) results in thirdharmonic distortion of the detected signal. Note that gain is
a function of either the product of v, and v" or the product
of v.. and vS'

+6V

I.

I•

....--=---l--OUTPUT 1

'6
~----L-_OUTPUT 2

··U.,~ 1"
= .•

015

-6V

REGENERATED
CARRIER
U.75I1HII

MODULATED
SIGNAL -=

Fig. 49-Circuit diagram for the use 0/ a CA300J or CA3006 as a product detector.

TABLE VII
Gain and Distortion as a Function of Different Drive Levels for a Double~Sideband Modulator and
Product Detector Using the CAJ006
Terminal 3
Harmonic Distortion
Condition

V,

Varied

v,
Varied

v,
Varied

v,

V,

(m.
rms)

Voltage

(mv
rms)

(Volls
rms)

(oolts
1ms)

rms)

5

31.5
31.5
31.5
31.5
100
315
31.5
31.5
31.5
31.5
31.5
31.5
31.5

0.296
0.296
0.296
0.296
0.96
2.96
0.296
0.296
0.296
0.296
0.296
0.296
0.296

0.046
0.080
0.25
0.083
0.262
0.83
0.083
0.083
0.083
0.083
0.083
0.083
0.083

4.95
8.9
26.6
8.9
28
89
8.9
8.9
8.9
8.9
8.9
8.9
8.9

10

30
10
10
10
10
10
10
10
10

v,
Varied

10
10

'"

"

(m.

V,

(m.
rms)
I

1161&2

(m.
,ms)

4
4
4
4
4
4

0.5
4
12
20
4
4

"

(m.

V,

(dB be/ow fundamental)

(mv

rms)

1ms)

0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.315
0.5
1.0

36
36
36
36
36
36
17.5
36
110
188
23
36
86

Znd

51
56

Jrd

54
54
37.5
54
51
50
54
52
47.5
37
54
54
50

4th

5th

59

Notes: 1. Consult Figs. 48 and 49 for explanation of voltage designations.

2. Blank spaces indicate harmonic distortion is more than 60 dB below the fundamental.

127

DDLn5LJD
Solid State

Linear Integrated Circuits
Application Note
ICAN-5030

Division

Application of the RCA-CA3000
Integrated-Circuit DC Amplifier
BY
A. J. LEIDICH and M. E. MALCHOW
The RCA·CA3000 dc amplifier is a monolithic silicon
integrated circuit supplied in a 10·terminal TO-S package.
This stabilized and compensated differential amplifier has'
push·pull outputs, high·impedance (O.l-megohm) inputs,
and gain of approximately 30 dB at frequencies up to one
MHz. Its useful frequency response can be increased to
several tens of megahertz by the use of external resistors
or coils.
Because full gain-control capability is inherent in tire
CA3000, it can be used as a signal switch (with pedestal),
a squelchable audio amplifier (with suppressed switching
transient), a modulator, a mix.er, or a product detector.
When suitable external components are added, it can also
be used as an oscillator, a one-shot multivibrator, or a
trigger with controllable hysteresis. Within its specified
frequency range, it is an excellent limiter, and can. handle
input signals up to about 80 millivolts rms before significant cross-modulation or intermodulation products are
generated.
CIRCUIT DESCRIPTION
The circuit diagram and terminal connections for the
CA3000 dc amplifier are shown in Fig. I. The circuit is
basically a single·stage differential amplifier (Q, and Q.)
with input emitter-followers (Q. and Q,) and a constantcurrent sink (Q,) in the emitter·coupled leg. Push-pull input
and output capabilities are inherent in the differential configuration.

The use of degenerative resistors R. and R. in the emittercoupled pair increases the linearity of the circuit and decreases its gain. The low· frequency output impedance between each output (terminals 8 and 10) and ground is
essentially the value of the collector resistors R, and R, in
the differential stage.
OPERATION OF THE CIRCUIT
The CA3000 is designed for operation from a wide range
of supply voltages. Operation from either one or two power
supplies is feasible, as illustrated by the typical biasing techniques shown in Fig. 2. However, operation from two sup·
plies is recommended because fewer external bias networks
are required and, therefore, less power is consumed.
The maximum voltage that can be applied across the
circuit (positive supply voltage Vec plus negative supply
voltage V",,) is 16 volts. The maximum voltage capability
(Ve,,) of the differential pair is limited to 8 volts. Extra care
must be used to ensure that these values are not exceeded
when the circuit is used to drive" induclivt: loaus.
The operating·current conditions of the differential pair
are determined by the base-bias circuit and emitter resistance of the emitter·coupled constant·current sink (Q.), as
well as by the voltage between terminals 2 and 3. Each
possible current condition is manifested by (I) a distinct
set of dc operating characteristics with differing temperature
characteristics, (2) a particular value of gain having its own
temperature dependence, and (3) a particular dynamic

3070

128

-

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ICAN_5030
output-vollage capability. For each value of voltage between
terminals 2 and 3 (V"" when lerminal 2 is grounded). Ihere
are four possible operating modes, as described in Table I.
Table l-Operating Modes for CA3000 DC Amplifier
Shorted
Mode

"""'J\"
B

C
D

A.

A3

03

A.

·7

A9

D,
D.

A,O

All

3
VEEH

Fig_ J - Schematic diagram and terminal connections
lor the CA3000 integrated-circuit dc amplifier.

Terminals
none

5-3
4-3
5-4-3

Condition
of Diodes

--in-oul
in

oul

Q~

Emitter

Resistor
RI/+R,II

R,+Rlo
R.
R.

The opeFaling characleristics for Ihese modes of operation
are summarized in Table " for various two-supply configurations with terminal 2 grounded ani. with V ...: values
of -3 and -6 volts dc.
Table " shows thaI Ihe posilive supply voltage can be
adjusted for each mode of operation and for each value of
negative supply so thaI the nominal dc OUlput voltage is
zero. (Although the V,., value required for mode C for a
V.:I'. of -6 volts de is in excess of the maximum rating,
opera lion within ratings can be achieved wilh slightly negative values of output voltage.) The use of Ihese adjusted
values of posilive supply provides two advanlages: (1) direct interstage coupling can be effected in a single-ended
configuration, and (2) negative feedback can be introduced
from a single output back to the appropriate input. For
low-level applications in mode D with a negative supply
voltage V,'" of -3 volts dc and a positive supply voltage
V,. of 1.1 volts dc, the CA3000 has a gain of 24.4 dB, a
dissipation of 6.2 milliwatts, an output capability of 2.2
volts peak-ta-peak. and a dc output-voltage reference level
of zero.
The information in Table II can be modified for singlesupply designs by simple addition and/or sublraction of
dc values. For example, Ihe correcl information for a single

Table II-Design Characteristics of CA3000 Operating Modes
DC Supply Volts
Negative
Positive
V ••
-Y..a

--66
6
6
3.7
1.7
10.6
(over rating)
5.0
3
3
3
3
1.8
0.4
5.3
1.1

---=6

Operating
mode

--A--

Single-ended DC output volts
midband voltage (Terminal 8 or
gain-dB
10 to ground)
G ••
V ••"

31.2
27.3

-6

B

-6
-6
-6
-6

C
D
A
B

34.6
32.4
31.2
27.3

-6
-6
-3
-3
-3
-3
-3
-3
-3
-3

C
D
A
B

34.6
32.4
27.5
16.6

C
D
A

32.6
24.4
27.5
16.6
32.6
24.4

B

C
D

+2.3
+4.3
-1.5
(saturaled)
+1.0
0
0
0
0
+1.2
+2.6
-1.5
(saturated)
+1.9
0
0
0
0

Positive
voltage
swing

Negative
voltage
swing

V ... .,.·
+3.7
+1.7

Y... f ,,·
-3.8
-5.7

+7.5
+5.0
+3.7
+1.7

0
-2.4
-1.4
-1.4

-mW
--4-036
61
47
33
25

+10.6
+5.0
+1.8
+0.4

-1.5
-1.5
-2.6
-4.1

83
43
8.8
7.4

+4.5
+1.1
+1.8
+0.4
+5.3
+1_1

0
-3.3
-1.5
-1.5

14
8.5
7.2
8.4
19
6.2

- . 1 • .,1

-2.6

TOlalpower
dissipation

• V0au: and V.... I. arc the ac swing extremities above and below V••e •

129

ICAN-5030
Vee(+)

R,

.~

IIIN

OR
GROUNO

Your

R.

VOUT

R,

R.

-~
OR

III
YOUT

Your

GRD.

R,

(b)

(a)

R,

R,

~Z

RZ

.~

o-l

-VIN

OR
GRD.

RZ

* *

(b)

(b)

* Connection of terminals 4 and 5 depends on f110de of operation.
Fig.2 - Typical biasing arrangements lor the CA3000 lor operation Irom (a) two separate voltage supplies,
or (b) a single voltage supply.
supply of 12 volts de for operating mode A can be obtained
from the conditions shown in the table for mode A for
Vee 6 Vde and V•• -6 Vde by the additi9n of 6 volts

=

=

to the values shown for Vce. V r:..f Vo.e , Va..... and Vo", .•.

(It should be noted that the required voltage levels at the

.

...

~

OUTPUT OfIERATING POIIT.Ycc-V.

.l!

•

!l

!!

~
"g

!;

~
u

."
!"

input terminals 1 and 6 and at terminal 2 are also 6
volts higher.
As mentioned previously, the four operating modes exhibit different temperature characteristics. Fig. 3 shows
theoretical curves of dc output voltage as a function of

-0.2

i-D.·
;;

~oz.

10
TEIlPERATURE-·C

100

'4.

i"

-0.2

~

-0.4-

s~:!

-10

-4..

-~o
TEMPERATURE _·C

Fig.3 - Theoretical curves 01 dc output voltage as a lunction 01 temperature lor negative-supply voltoges
01 -3 and -6 volts dc (calculated lor ~ = 35 at 200C).

130

------------------------------ICAN-5030
Vee· 611', VEE. -611'

Vee· sv, VEE. -:5V

:f~
-t~----------c
~·'ai;;'0-;;10~'0,..,,12:n'O:O::,40
=::::::::D.

-.260- :0

-20

-I~;::;;::;;=~=::.:=~,
eo

-2
-60

0

TEMPERATURE - ·C

-40 -20

0

20

40

60

100

120

140

TEMPERATURE - ·C

Fig.4 - Measured curves of dc output voltage as a function of temperature for
negative-supply voltages of -3 and -6 volts dc.

-2

-.

-60

-40

-20

20
40
60
TEMPERATURE _·c

ao

100

140

120

VEE --6Vde
CURVE

GAIN (dB)

AT O·C
31.2
27.3

•. 6

eI

32.4

I

~.

=

0

~
2
-I

~

-2

-.

-60

-40

-20

20
40
60
TEMPERATURE - ·C

ao

100

140

120

Fig.5 - Theoretical curves of gain as a function of
temperature for negative-supply voltages of -3 and
-6 volts dc (calculated for ~ = 35 at 20o e).
~

!IO

;!

il

>'=40

-'I
~z

~=30

temperature for each operating mode for negative supply
voltages V,m of -3 and -6 volts dc. The experimental
curves shown in Fig. 4 are in excellent agreement with the
theoretical curves except in the case of mode C. In this
mode, the differential-pair transistors Q2 and Q, were driven
into saturation as a result of the use of symmetrical supplies
(V,.• = Vr.e) for the experimental data. The discrepancy
could be corrected by use of somewhat higher values of
positive supply voltage.
Fig. 5 shows theoretical curves of gain as a function of
temperature for the four operating modes with Vcc values
of -3 and -6 volts dc. With the diodes in (modes A and
C), the gain decreases for both values of VEE. With the
diodes out (modes B and D), on the other hand, the gain
increases with temperature for a negative supply of -3
volts dc, but decreases with temperature for a negative
supply of -6 volts dc. With the diodes out, there is a value
of negative supply (approximately -4.5 volts dc) for which
the gain is independent of temperature. Fig. 6 shows measured values of single-ended and push-pull gain for mode A
with symmetrical power supplies of ± 6 volts dc. (fhis configuration is used in the remaining discussion because it
provides the maximum sinusoidal output capability. as
shown in Table II, and because of the convenience of ±6volt dc supplies.)
The typical singie-ended voltage-gain! frequency-response
curve of the CA3000 for dc supplies of ±6 volts in operating mode A is shown in Fig. 7, together with the test circuit
used for voltage-gain measurements. The Bode responses
of the CA3000 are virtually independent of source impedance up to 10,000 ohms because of the emitter-follower
inputs. The curves in Fig. 8 show that gain and bandwidth
are virtually independent of temperature for operation in
mode A with ±6-volt dc supplies.

MODE It

"'cc·IV,Vue-GV
FREQUENCY{fl-IOO HI
PUSH-PULL
SINGLE-ENDED

~ ~~~.--=4~0~-~m~~~~2~0.-~4i;;0~••~0-7ao~'1~00.-'1*'20.-~,4'0
TEMPERATURE _·C

Fig.6 - Measured values of singl.... ended and push-pull gain for mode A operation
with symmetrical power supplies of ±6 volts dc.

131

ICAN-5030---------------------------

,

i

20

~

..
i:i
...:.
0

I--

.J

I--

~-~-

10

SOURCE

1000
OHMS

I---

0.1

I\.

4

2

8

~~-

2)(~

-=-

=

o

~
'1 1
•

CA3000

MS

I

!

Ii ,
I
I

,

10

¢?O

Ii

!!
!iI
!!

I\.

~

-

0

!!;
on

I
;

~

D

~

--+!---tI

r-

30

..~

!

"=" -6V

"
I'\.

II
II
• •

I

'\

"="

.•

4

2

2

10

\

4

100

FREQUENCY -MHz

Fig_7 - Single-ended voltage gain of CA3000 as a function of frequency in test circuit shown_

III

POSITIVE DC SUPPLY VOLTS (Vee)· +6
NEGATIVE DC SUPPLY VOLTS (VEE)- -6
D

i

;;

i..

..

~

I

III

III

III I

FREE-AIR TEMPERATURE (T~, )c-l55"C

0

~ i'-25

-10

0

.
~

-20

~

:Ii -30

!i!'"

-,
0.001

2

4

••

2

4

••

2

FREQUENCy (f) -

4

••

2

4

••

10

0.1

0.01

MHz

92CS-I3294

Fig.8,- Normalized gain-freque,ncy curves for CA3000
at three Jillerent temperatures.

Fig. 9 shows agc characteristics for the CA3000 for ao
input frequency of I kHz, together with the age voltagegain test circuit. When the age voltage at terminal 2 is
varied from 0 to -6 volts, the amplifier gain cao be varied
over a raoge o{ 90 dB.
Fig. 10 shows the test circuit used to m~asure commonmode rejection, together with curves of common-mode rejection as a function of frequency aod ,temperature. Typical

132

rejection is 97 dB at a frequency of I kHz. Fig. II shows
the test circuit used to measure the dc unbalance of the
amplifier (referred to the input), together with a curve of
the input offset voltage as a function of temperature.
Typical input offset voltage (with an assumed push-pull
differential go.in of 37 dB) is 1.5 millivolts. Fig. 12 shows
curves of input bias current, input impedance, and dynamic
output voltage as functions of temperature.

_________________________________________________________ ICAN_5030

.
6V

r-- ~

20

\

.,

1\

0.0

-I.
-20

..

.

o

TO-&
VOLTS
(ADJUSTABLE)

..

-6V

-00

-ro

Fig. 9 - AGC characteristics of CA3000 in test circuit
shown at frequency of 1 kHz.

-80
0.0

-

-

-

-

-

APPLIED DC YOLTAGE APPLIED TO TERMINAL 2

-

POSITIVE DC SUPPLY YOLTS (Vee)- +6
NEGATIVE OC SUPPLY VOLTS (YEE)· -6
FREE-AIR TEMPERATURE (TFA) • 25·C
80~

F::::

Vee

+6V

'"

z
0
i= 1D 60
uv

~I

"';<

to..

r-....

~340

"

0-

"2

~~
~

0

t-....

ZO

u
0
2

0.01

•••0.1

2

•••

2

•••10

FREQUENCY (1)- MHz

•••100

2

92CS-13295

:100
I

-6V

VEE

z
9 "

E

COMMON-MODE REJ"ECTION RATIO (CMR). 20 log

i-

(Ai!~31

-A· SINGLE-ENDED VOLTAGE GAIN AS MEASURED
IN CIRCUIT SHOWN IN FIG. 7

I"
! .2

92CS~I2983R1

~

8~'.h80,---!,40,---!,20,-.~~20!=-~.!=-~
. .!=-~
. .!=-~IOO!=-~12'-a~14O
.
n_UATUftE -

-c

Fig. 10 - Common-mode rejection of CA3000 as a function
of frequency and of temperature in test circuit shown.

133

ICAN-5030 - - - - - - - - - - - - - - - - - - - - - - - - - - Vee

'6V

.g
.
!:i

2.5
2.0

:;
i

1.5

::,

1.0

.
.t

0.5

TEMPERATURE --c

-6V

VEE

92C;5-13595

Fig. 11 - Input oIfset voltage of CA3000 as a function of temperature in test circuit shown.
POSI IV. DC .UPPLY VOLT. Vee • +6
NEGATIVE DC SUPPLY VOLTS (VEE). -6
FREQUENCY Ct) ~ IIIHI

POSITIVE DC SUPPLY VOLTS (Vee). +6
NEGATIVE oc SUPPLY VOLTS (YEE)- -6

c

~ 100

~

.:.

•
-7!i

-50

-25

0

50

o

25

7!i

50

100

-75

125

FREE-AIR TEMPERATURE (TFA)--C

...

.. !l

~~~e

~~=;

3~'1

•

-50

-25

25

50

75

100

125

FREE-AIR TEMPERATURE (TFAI-·C
92C$-13298

ycc-eViVEE--IV
MOO.A

FREQUENCY Itl-IOO Hz

£!~S '
'">l1I-

~ ~lOln-::::
..b;o,....,-~20;;;----;\--..
=---,40=---,60!:---.iIO:--I::!OO".....,I,!,20,.--,!,.O
TEMPERATURE-

-c

Fig. 12 -.Input bios current, input impeJance, anJ Jynamic output voltage of CA3000
as functions of temperature.
APPLICA TIONS
Crystal OsclUato.---The CA3000 can be used as a crystal
oscillator at frequencies up to 1 MHz by connection of a
crystal between terminals 8 and 1 and use of two external
resistors, as shown in Fig. 13(a). The output is taken
from the conector that is not connected to the crystal
(in thi!l;

ca~~

terminAl 10). If a variahle-feedhack ratio

network is used, as shown in Fig. 13(b), the feedback may
be adjusted to provide a sinusoidal oscillation. Output
waveforms for both circuits are also shown. The frequency
in each circuit is 455 kHz, as determined by the crystal.
The range of these crystal oscillators can be extended
to frequencies of \0 MHz or more by use of conector
tuning.

134

Modulated OscUJator-If a low-frequency signal is connected to terminal 2, as shown in Fig. 14, the CA3000 can
function as an oscillator and produce an amplitude-modulating signal. The waveform in Fig. 14 shows the modulated
signal output produced by the modulated oscillator circuit
when a I-kHz signal is introduced at terminal 2 and a
high-pass filter is used as the output.
Low-Frequency Mixer-In a configuration similar to that
used in modulated-oscillator applications, the CA3000 amplifier may be used as a mixer by connection of a carrier
signal at the base input of either differential-pair transistor
(terminal! or 6) and connection of a modulating signal to
terminal 2 or S.

______~-------------------------------------------------ICAN-5030
~-l-----06 V

Vaul' }--;H"')-(
-6V

1000
OHMS

1000
OHMS

,oJ

IDaa

OHMS

,OJ

Fig. 13 - Schematic diagrams and output woveform$ of (0) crystal oscillator and
(b) crystal oscillator with variable feedbock_
6V

>--u,.-"U-6 v
..

ut~27.'

t
1\)00

=

OHMS

OHMS

1000
OHMS.

VI· MODULATING SIGNAL
(60D-OHM SOURCE)

Fig. 14 - Schematic diagram and output waveform of CA3000 modulated oscillator.

Cascaded RC-Coupled Feedback Amplifier-The twostage feedback cascade amplifier shown in Fig. 15 produces
a typical open-loop midband gain of 63 dB. This circuit
uses a 100-picofarad capacitor C, to shunt the differential
outputs of the first stage. This capacitor staggers the highfrequency roll-offs of the amplifier and thus improves
stability.
The gain-frequency characteristic of the feedback amplifier is shown in Fig. 16(a) for a feedback resistance R,
approaching infinity. The low-end roll-off of the amplifier
is determined by the interstage coupling. Because agc may

be applied to the first stage, the amplifier of Fig. 15 may be
used in high-gain video-agc applications under open-loop
conditions. If feedback is used to control the gain. agc may
still be applied successfully.
Fig. 16(b) shows the agc characteristics for the two-stage
amplifier under open-loop and two closed-loop conditions
al a frequency of I kHz. As shown in Fig. 16(a), the openloop bandpass is 18 Hz to 135 kHz; under closed-loop
conditions, the bandpass is 1.3 Hz to 2 MHz for 40-dB
gain and 0.13 Hz to 6.6 MHz for 20-dB gain. The negative
feedback thus improves low-frequency performance sufli-

135

ICAN-5030 - - - - - - - - - - - - - - - - - -_ _ _ _ _ _ _ _ __

YOUT

the input is adequately shielded from the output by a
ground plane.
The CA3000 has an output capacitance of approximately
9 picofarads at a frequency of 10 MHz. This capacitance

LeN-l

T/~

60

"\

00
FOR VAGc.O

CLOSJD-LOOP

40

.,
"zI

.:=
.""

30

~

Fig_1S - Cascaded RC-coup/ed feedbaclc amplifier
using two CA3000 circuits.

CLOSJO-LOOP

20

(Rt • 9000 OHIIS)

':i
!i!

ciently so that the use of small coupling capacitors C,
and C, involves little sacrifice in low-frequency response.
If three or more CA3000 amplifiers are cascaded, the
low-frequency roll-offs must be staggered as well as
those at the high end to prevent oscillation. A three-stage
cascade has a midband gain of approximately 94 dB.
Narrow-Band Tuned Amplifier--Because of its high input and output impedances, the CA3000 is suitable for use
in parallel tuned-input and tuned-output applications. Tliere
is comparative freedom in selection of circuit Q because
the differential amplifier exhibits inherently low feedback
qualities provided the following conditions are met: (1) the
collector of the driven transistor is returned to ac ground
and the output is taken from the non-driven side, and (2)

10

':'

~

0

~

-10

-20

-so
-40

(a)

I

-3

-4

-5

AGe DC VOLTS

I

V

\
1\

i

/

\

\

/

oil
10-2

-2

-I

/

I
o

1"1

z

o

63
60

-....,,~

(At· o.l,IIEGOHII'

-

10 I

'0'

10 2

103

FREQUENCy -

104

1\

108

Hz

Fig. 16 - (a} Gain-fre'l"ency and (b} agc cltaracterisflcs ofleedbaclc amplifier sit own in Fig.1S.

136

(b)

-----------------------------ICAN·5030
will resonate a 28 microhenry coil at this frequency and
give a minimum Q of 4.SS when the collector load resistor
is the only significant load. With this low Q, stagger

+6V

tuning may be unnecessary for many broad-band applica-

tions.
Fig. 17 shows the CA3000 in a narrow-band, tuned·
input, tuned·output configuration for operation at 10 MHz
with an input Q of 26 and an output Q of 2S; the response
curve of the amplifier is also shown. The IO-MHz voltage
gain is 29.6 dB, and the total effective circuit Q is 37.
There is very little feedback skew in the response curve.
The CA3000 can be used in tuned-amplifier applications
at frequencies up to the 30-MHz range.
+6Vdc

-6V

Fig. 18 • Schematic diagram lor Schmitt trigger

using CA3000.
(terminals 3 and' S shorted together) in t.he configuration
shown in Fig. 18. Large values are required for extenial
resistors R, and R, because they receive the total collector
current from terminal 10. Because of the high impedances,
resistor RlI is actually a parallel combination of the input
impedance (approximately 0.1 megohm) of the CA3000 and
the 0.2S-megohm external resistor. The Schmitt-trigger design equations (for a
1) are summarized below. In these
equations, Q, and Q, are the differential'pair transistors, Q,
and Q, are the emitter-follower transistors, and Q, is the
constant-current sink.

8000
OHMS

v,.

-,'

50 OHMS

=

32

STATEl: Q, off, Q, conducting (not saturated)

2B

V,! =

Vee (R,) - V R• (R, + 8000)

R, + R,+ 8000

24

where 8000 ohms is the output impedance of
Q. (obtained from the published data). For R, =
27000 ohms and Vee VB. 6 Vdc,
6V (R,) - 6V (35000)
CA)
R.+ 35000

= =

20

!II
I

z ,.

~

R.
12

=(R. + 8000)

V•• + Vo,
Vee-V'I

R. = (35000) 6V + Vo,

(B)

6V-Vo,

9.6
10
10.4
FREQUENCY - MHz

11.2

Fig. 11 - Schematic diagram and response curve
lor IO-MHz tuned-input, tuned-output,
narrow-band amplilier using CA3000.
Schmitt TrIgger-The CA3000 can be operated as an
accurate, predictable Schmitt trigger provided saturation of
either side of the differential amplifier is prevented (hysteresis is less predictable if saturation occurs). Non-saturatinS operation is accomplished by operation in mode B

VO! = Vco - I. (8000)
where Is = collector current of transistor Q.
",,0.48 milliampere in operating mode B with
V•• = -6 volts dc.
VO! = 2.14 V
(C)
V r, '" Firing voltage for transition from state I to state II
V = Vo, - 0.053 - 100 I. at 2S'C
Vr, Vo, - 0.101 V at 2S'C
(D)

P,

=

STATE II:Qo conducting (not.aturated), Q, off
Van = Vee
VOI[=6V
VOl[ = (Vee - I. 8000) R. - V•• (R. + 8000)

(A)

R.+R.+8000

137

ICAN-5030 - - - - - - - - - - - - - - - - - - - - - - - - - - - V· - 2.14 V (RJ - 6 V (35000)
(B)
'II R, + 35000
V'II e Firing voltage for transition from state II back to
state 1
V' II = V'II + 0.053 + 100 I. at 2S'C
Vrll = V'II + 0.101 Vat 2S'C
(C)

HYSTERESIS VOLTAGE
Van = V"r - V"n

3.86 V (RJ
R,+ 35000

0:202 V at ZS'C

From Ibe calculations for state I, it is evident that either
V" or R, must he a known design value. Because R. is a
composite value, V" is Ibe more reasonable choice. The
ability of these equations to predict Ibe Schmitt-trigger performance is evidenced by Ibe comparisOn of calculated and
experimental data in Table III.

Table 111- Comparison of Calculated and Experimental Data for Scbmitt Triger
Cakulaled
-2.1V
-3.19V
+1.09V

Experimental

-1.I0V
-2.SIV
+1.4IV

-I.OV
-2.4SV
+1.4V

Vau

-O.IOIV
-1.83V
+1.73V

0
-1.8V
+1.8V

4) V.,=+IV

Vr,
V"u
VBY"

+O.9V
-I.ISV
+2.1V

+I.OV
-I.OV
+2.0V

S) V.,=+2V

Vr,
V"u

+1.9V
-O.472V
+2.43V

+2.0V
-O.W
+2.4V

Condition
I) V,'_ 2V

Parameter

Vr,
Vrn
VHT!!

2) V.,=-IV

V.,
Vru

V HIII

3) V.,=O

V"
VI'II

VBrl'!

138

-2.2V
-3.2V
+1.0V

ffilCIBLJIJ

Linear Integrated Circuits

Application Note

Solid State
Division

ICAN-S036

Application of the RCA-CA3002
Integrated-Circuit IF Amplifier
BY
G. E. THERIAULT AND R. G. TIPPING
The RCA·CA3002 integrated-circuit if amplifier is a
balanced differential amplifier that can be used with either
a single-ended or a push-pull input and can provide either
a direct-<:oupled or a capacitance-coupled single-ended output. Its applications include RC-coupled if amplifiers that
use the internal silicon output-coupling capacitor, video
amplifiers that use an external couplirig capacitor, envelope
detectors, product detectors, and various trigger circuits.
The CA3002 features all-monolithic silicon epitaxial construction designed for operation at ambient temperatures
from - 55 to 125°C. and contains a built-in temperaturecompensating network for stabilization of gain and dc
operating point over this operating-temperature range. It
is supplied in a 10-terminal TO-5 low-silhouette package.
Because the CA3002 is a balanced differential amplifier
fed from a constant.current source, it makes an excellent
controlled-gain amplifier. The gain-control function may
be extended to include video gating, squelching, and blanking applications. Envelope detection can be achieved by
suitable biasing of the emitter-base diode of the output
emitter-follower transistor. Product detection can be obtained by re-insertion of the carrier at the base of the
constant-current-source transistor. Various trigger and waveform-generating circuits can also be achieved by the addition of suitable external components.

CIRCUIT DESCRIPTION AND
OPERATING MODES
Fig. 1 shows the circuit diagram and terminal connce:tions for the CA3002 integrated circuit. The circuit is
basically a single-stage differential amplifier (Q, and Q,)
with input emitter-followers (Q, and Q,), a constant-current
sink (Q3) in the emitter-coupled leg, and an output emitterfollower (Q,). A single-ended input is connected to terminal
10 or a push-pull input to terminals 10 and 5. A single-ended
output is direct-coupled at terminal 8 or capacitance-coupled
at terminal 6. Terminals 5 and 10 must be provided with dc
returns to ground through equal external base resistors. The
emitters of the differential pair (Q, and Q,) are connected
through degenerative resistors (R, and R,) to the transistor
current source (Q3)' The use of these resistors improves the
linearity of the transfer characteristic and increases the
signal-handling capability.
Transistor Q, provides a high input impedance for the if
amplifier. Transistor Q5 preserves the circuit symmetry, and
also partially bypasses the base of Q,. Additional bypassing
can be obtained by connection of an external capacitor
between terminalS and ground. The emitter-follower transistor Qa provides a direct-coupled output impedance of less
than 100 ohms.

9-74

139

ICAN-5036 - - - - - - - - - - - - - - - - - - - - - - - - - - Table I-Identification of CA3002 Operating Modes

Fig. l-Schemalic diagram and terminal connections for the
CA3002 ;ntegrated~circuit if amplifier.

When voltage supplies are connected to the CA3002, the
most positive voltage must be connected to terminal 9
and the most negative voltage to terminal 2 (internally connected to the substrate and case). The CA3002 may be
operated from various supplies and at various levels. Operation from either single or dual power supplies is feasible.
When two supplies are used, they may be either symmetrical
or non-symmetricaI. When both positive and negative voltage supplies are used, external components can be minimized, as shown in Fig. 2(a). For single-supply applications,
a resistor divider and a bypass capacitor must be added
externally, as shown in Fig. 2(b). The current through R,
and R, should be greater than one milliampere. Except in
applications that use inductive drive, equal external base
resistors must be added at terminals 5 and ! 0 to provide
base-current returns. Terminal 7 can be connected to ground,
or to the negative supply if a larger negative-going voltage
swing is desired at any operating point.
FOf either single or dual supplies, the operating current
in transistor Q. is determined by the bias voltage between
terminals I and 2. The more negative point of this bias voltage must be connected to terminal 2. For dual-supply systems, terminal! is usually referenced to ground.
For any given bias voltage (VEE when terminal ! is
grounded), four operating' modes are possible, as described
in Table I. In general, each mode is characterized by (I)
a distinct dc operating point with a cbaracteristic temperature dependenee, and (2) a I"~rtiC1l1aT value of gain that
has a distinct temperature dependence.
When the diodes are utilized in the bias circuit (modes A
and C), the current is essentiaIly dependent on the temperature coefficient of the diffused emitter resistors R, and R u ,
and has a tendency to decrease with increasing temperature
at a rate independent of the negative supply voltage. The

140

Operating
Mode

Shorted
Terminals

Condition

A

none

B
C

4-2

D

4-3-2

in
out
in
out

3-2

of Diodes

QJEmitter
Resistor

R,+ RI1
~+RI1

R.
R.

temperature coefficient of the diffused collector resistor R,
is the same as that of the emitter resistor, and a constant
collector-voltage operating point results at the collector of
transistor Q.,. However, the operating point at output termi~
nal 8 is modified by the base-emitter voltage drop of transistor Q" and its temperature dependence. Typical variation
of the output operating point with temperature is shown
in Fig. 3 for the four operating modes for V"" supplies of
- 3 and - 6 volts_ The voltage between terminals 8 and
9 is denoted by V •. In mode B (with the diodes out of the
bias circuit), it should be noted that the output operating
point is constant with temperature because the change in
the collector operating point is cancelled by the change in
the base-emitter voltage drop (VD.).
When the diodes are out of the bias circuit, the currenttemperature curves become dependent on the negative supply voltage. Therefore, the value of V." can be adjusted
so that the transconductance decreases, increases, or remains constant witb temperature. As shown in Fig. 4, the
gain increases with temperature for a -3-volt V•• supply,
but decreases with increasing temJ>Crature for a - 6-volt
V•• supply. At some intermediate value of V •• (approximately - 4.5 volts), the gain 'should be constant as a functioD of tempe;rature. In any case, however, a constant ac
gain with temperature is accompanied by a change in the
collector operating point of transistor Q~.

Fig_ 2-Circuit configurations for the CA.3002 with
(a) dual voltag. supplies, and (b) a single supply_

------------------------------ICAN-5036
0.6r--::--:--=,---------------,
AT 2S·C,
MODE

Vx

VEE =-6 V

AT 25°C,

OUTPUT OF&::RATING POINT- YCC-V X

MODE

e

Vx

2.118V
I.OS4IJ

3.471 V
Z.044V

4.515V

8.2:65V
4.363V

1.577V

-0.2

-0.4

6.
TEMPERATURE-OC

65

105

125

TEMPERATURE-OC

Fig.3-01llput operating-point variation of 'he CA3002 (normalized to the 25°C operating point) as a function of temperature
with VEE supply voltages of -3 and -6 volts.

VEE --3 V

!g

!:i

;

VEE --6V

m

Il'i

I
z
0

ii'

I

;l

25.3
22.2

z

;; -I

~
!:; -I
~

..~

~

-'
>

.:.

0

GAIN-dB

21.2

I

z

-

~ 300 - - - -

j

~

20 0

~
>-

5In

il:

100

/

1/

./

"":>

~

V

V
[--METHOD II)

Fig. 17-Producl detector circuit.

~

20

40

60

80

100

120

Because of the single-ended output, a high-frequency
bypass capacitor (0.01 microfarad) is connected between
terminal 8 and ground to provide fit tering for the highfrequency components of the oscillator signal at the output.
When the amplitude of the suppressed-carrier signal and
of the osci1lator signal are varied, the gain and distortion
characteristics shown in Table III are obtained. The conversion voltage gain is constant at input signals up to 16
millivolts and would be 6 dB less for a single-sideband signal
than for the double-sideband signal. The distortion increases with increasing input signal; for distortion of less
than 1 per cent, the input drive level does not exceed 8
millivolts. The gain maximizes for oscillator voltages of
1 to 2 volts, and the distortion characteristic is also best
in this region. Distortion increases both at low oscillator
drive levels (0.25 volt) and at high levels (3 volts).
Schmitt Trigger. Fig. 18 shows the. use of the CA3002 as
a Schmitt trigger. In this application, the input is applied to
terminalS and both the output and the feedback are taken
from the output emitter-follower at terminal 8. The emitterfollower output isolates the feedback loop from the differ-

140

RMS INPUT MILLIVOLTS (AT I. 75 MHz)

Fig. 16-lnput-olllput clwracteristic:s 0/ the em'e/ope detectors
shown in Fig. 15.

Product Detector. A differential pair driven by a constantcurrent transistor can be used as a product detector if a
suppressed-carrier signal is appHed to the differential pair
and the regenerated carrier is applied to the constant-current
transistor. There are two requirements for linearity: (1) the
circuit must be operated in a linear region, and (2) the current from the constant-current transistor must be linear
with respect to the reinserted carrier voltage.

The CA3002 satisfies these requirements and can be used
as a product detector in the circuit shown in Fig. 17. A
double-sideband suppressed-carrier signal is applied at terminal 10, and the 1.7-MHz carrier is applied to terminal 1.

Table III-Performance Data for CA3002 as Product Detector

v,
v,

v,

DoubleSideband
Voltage

Oscillator
Voltage
at
Terminall

Terminal 8
at 1 kc/s

(mV)

(V)

(mV)

Conversion
Voltage
Gain
(dB)

1
4
8
16
32

1.7
1.7
1.7
1.7
1.7

12.5
50
100
200
310

21.9
21.9
21.9
21.9
19.8

60
51
46
37

4
4

0.25
0.5

22
42

15.6
20.3

15
32

4

•. v

GO

• .J

~J

4
4
4
4
4

1.3

60
50
48
31
15

23.5
21.9
21.6
17.8

49
51
52
49
42

1.7
2.0
2.5
3.0

Outpulat

~;J

11.4

dB down from Fundamental 0/ Harmonics
2nd

32

3Td

61
56
46
30
42
52
60
61
61
62
60
60

Harmonic
4th

51

*
5th

64

44

*Harmonic Distortion Greater than 6S dB Down If Omitted

146

ICAN-5036
entiat pair and makes it possible for the circuit to drive
low-impedance loads. An additional advantage is that neither
half of the differential pair saturates as the resistance of the

feedback loop is varied. Fig. 18 also shows the output swing
amI associated hysteresis of the Schmitt trigger as a function
of resistor R and the de input voltage level at terminal 5.

Sr--4r--3 r---'
'"z 2r--...~ I f-I

+6V

0>

...
'"

I
VHYS -tOV
R~

27 K

0

10 K

-6V

DC INPUT VOLTS AT

TERMINAL 5

Fig. 18-Schmitt trigger cir(.'uit and output swing
and associated hysteresis.

147

OOOBLJD

Linear Integrated Circuits
Application Note

Solid State
Division

leAN-S037

Application of the RCA-CA3007
Integrated-Circuit Audio Amplifier
by
R.G. TIPPING
The RCA-CA3007 audio driver is a balanced differential configuration with either a single-ended or a
differential input and two pusll-pull emitter-follower
outputs. The circuit features all-monolithic silicon
epitaxial construction, and is intended for use as a
direct-coupled driver in a class B audio amplifier which
exhibits both gain and operating-point stability over the
tempemture range from -55 to 1250 C. Because of its
circuit configuration (a balanced differential pair fed by
a constanklurrent transistor), the CA3007 is an excellent controlled-gain audio driver for systems requiring
audio squelching. This circuit is also usable as a servo
driver. The audio driver circuit is available in a 12-

terminal T0-5 low-silhouette paclr..age.
CIRCUIT DESCRIPTION

Fig.1 shows the schematic diagram and terminal
connections for the CA3007 circuit. The input stage
consists of a differential pair (Ql and Q2) opemting as
a phase splitter with gain. The two output signals from
the phase splitter, which are 180 degrees out of phase,

are direct-coupled through two emitter-followers (Q4 and
Q5). The emitters of the differential pair are connected
to the transistor constant-current sink Q3·
The diodes in the bias circuit of the transistor COilstant-current sink make the emitter current of Q3 essentially dependent on the temperature coefficient of the
diffused emitter resistor R 3. Because the diffused
collector resistors R 15 and R 16 should have identical
temperature coefficients, constant collector-voltage
opemting points should result at the collectors of
transistors Ql and Q2. However, the quiescent opemting
voltages at the output terminals 8 and 10 increase as
temperature increases because the base-emitter voltage
drops oi transistors Q4 and Q5 decrease as temperature
increases. This small variation in the output quiescent
operating voltage is sufficient to cause a large variation .
in the standby current of a class B push-pull output
stage wben the audio driver and the output stage are
direckloupled. Resistors Rn, R12, R13, and R17 and
transistor Q6 form a dc feedback loop which stabilizes
the quiescent operating voltage at output terminals 8

10-67

148

ICAN·5037

TO-5 PACKAGE
(BOTTOM VIEW)

Fig. 1 • Schematic aiagram ana terminal connections for the CA3007 auaio ariver.

and 10 for both temperature and power-supply variations
so that variations in the output operating points are
negligible.
Resistors Rio R7, Rs, and R14 form the input circuit; a doublEHlnded input is applied to terminals 1
and 5, and a single-ended input is applied to either
terminal 1 or terminal 5, with the other terminal returned
VCe (6 VI

to ground. The CA3007 must be ae-coupled to the input
source. In addition, any dc resistance between terminal
1 and ground should be added between terminal 5 and
ground. Output power-gain stabilization for a directcoupled driver and output stage is accomplished by
means of an ac feedback loop that connects terminals 7
and 11 to the proper emitters of the push-pull output
stage, as shown in Fig.2.
v (3."-,)')

T,
(STANCOR TA-IOI
SQUELCH

VOLTAGE....,.---
1

(

1;

!

~

5>

."
I!:
5

4

/

-4

-s

-12

-

l/

I--

-

4

Gain ys Frequency Response. The open-loop
low-frequency gain of the CA3015 and CA30 16 with
± 12-volt supplies is typically 70 dB with a 3-dB
bandwidth of 320 kHz. The unity-gain crossover
occurs at a frequency of 58 MHz.
Common-Mode Rejection. The common-mode rejection ratio of the CA3015 and CA3016 is typically
104 dB for operation with ± 12-volt supplies. A curve
of common-mode rejection ratio as a function of frequency is included in the bulletin.
Input and Output Impedances. The technical bulletin for the CA3015 and CA3016 includes curves of
input and output impedances as functions of temperature. At 25oC, the typical input impedance is 7800
ohms. The typical output impedance is 92 ohms with
terminal 5 of the CA3015 or terminal 8 of the CA3016
open, and 76 ohms with these terminals connected
to the output.

II

0

the CA3008 and CA301O, there is no hysteresis effect.
The CA3015 and CA3016 technical bulletin includes
curves of maximum peak-to-peak voltages as functions
of load resistance with terminal 5 of the CA3015 or
terminal 8 of the CA3016 open and with terminals 5 and
9 of the CA3015 or t!lrminals 8 and 12 of the CA3016
shorted. The CA3015 and CA3016 can drive a lowerresistance load when these terminals are shorted.

PHASE COMPENSATION
0

4

INPUT VOLTAGE (YIN)-mV

Fig_2 - Open-loop transfer characteristic.

12

The following section describes phase-lag and
phase-lead compensation techniques for these operational amplifiers. Fig.3 shows the various phasecompensation connections for the CA3015.

161

ICAN-5213 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
o Vec.-VEE-12 v
AMBIENT TEMPERATURE (T,\\=25-C
PEN

~NAL 5 OR TERMINAL B

\
°
c
~

;;fil °

\~

r-..

610203040

50

NON-INVERTING GAIN-dB

a:

29.7

19.1

PHASE-LAG

Fig.:! - Terminal connections for phase-lag and
phas('-lead compensation of the CA:!015.

Fig.4 shows a curve of the required phase-lag
capacitance as a function of gain, together with the
corresponding response curves. (The required capacitance values shown in this figure are applicable not
only for ±12-volt power supplies, but also for all
lower-voltage symmetrical supplies; however, smaller
capacitors could be used at lower voltages.)
Fig.5 shows curves of open-loop compensated
and uncompensated frequency response with ±12-volt
supplies. Although the phase-lag compensation capacitance of 18 picofarads shown in curve (8) of this
figure is sufficient to provide stability in resistivefeedback amplifiers down to unity gain, it is not sufficient to provide flat closed-loop response (± 1 dB)
below 20 dB.
Phase-Lead Compensation

In addition to the standard phase-lag compensation discussed above, the CA3015 and CA3016 have a

162

50

50

C'F)~'

40

Phase-Lag Compensation

When the CA3015 and CA3016 are operated from
±S-volt supplies, the phase-compensation techniques
described previously for the CA3008 and CA3010 are
applicable. 1 When the CA3015 and CA3016 are operated from ± 12-volt supplies, corrections must be msde
in the phase-lag compensation to allow for the shift
in frequency at which the second break in the openloop Bode plot occurs. At ±l2 volts, this second
break occurs at a frequency of 10 MHz. For Millereffect and conventional phase-l ag compensation, the
series RC combinations must be. sdjusted so that
1I(27TRC) =lOMHz to correct for the shift infrequency.
In sddition, the Miller technique requires a larger
value of phase-lag capacitance for a non-peaking
(± 1 dB) response to allow for the higher gain.

40

INVERTING GAIN -d B

'-v-'

MILLER EFFECT

....
1\

'2

\

I\,

20

\

~

I"

56

,

62
6&

°
-'00.'

2

4

• '.0
FREQUENCY -

•

'0

MHz

Fig.4 - Amount of phase-lag capacitance required
to obtain a flat I±l dB) response, and typical
response choracteristics.
80

Vee· -VEE • 12 V
SOURCE RESISTANCE • 50 .Q

70

1"-1'.
60

"

CB)
PHASE-LAG
COMPENSATED

o
20

-

0.1

II

CD)
PHASE-LEAD

COMPENSATED
~

(47,100, 470,OR
IOOOpFl

~

(18 pF,820 A)

,0

°

'"

"- '<
CA)

,~

I'...

f---, UNCOMPENSATED

Ice)
:-....
PHASE-LEAD
COMPENSATED

I

c'I°"l) I I

'0

\~
'''1\

~
100 ""0

FREOUENCY-MHz

Fig.5 - Open-loop gain as a function of frequency
for compensated and uncompensated amplifiers.

_ _ _ _ _--'-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ICAN·5213

phase-lead compensation capability. For this phaselead compensation, a capacitor is connected between
terminals 7 and 8 of the CA3015, as shown in Fig.3,
or between terminals 10 and 11 of the CA3016. The
effect of this capacitor is to eliminate the break at
10 MHz in the Bode plot and thus extend the 6-dB-peroctave roll-off. The second break in the Bode plot
then occurs at approximately 35 MHz, and the unitygain crossover occurs at 150 MHz. The phase-lead
compensated open-loop response is shown in curves
(C) and (0) of Fig.5 for various values of capacitance.
For optimum performance, a minimum phase-lead capacitance of 47 picofarads is recommended.
For flat (± 1 dB) responses at closed-loop gains
below 30 dB, a small amount of phase-lag compensation is required in addition to the phase-Ie ad compensation. The required phase-lag capacitance for flat
(±t dB> responses and the corresponding response
curves are shown in Fig.6. When phase-lead compen5 VCC.-VEPI2 V

~~~~,~ILT~M6~~~1~~~A«(A~~~~oEcN

sation is used, the series RC combinations should be
adjusted so that 1/(2 nRC) = 35 MHz.
The phase-lead compensation is also applicable
when ±6-volt power supplies are used, and provides a
unity-gain crossover improvement of about one octave
as compared to the uncompensated connection. As
mentioned earlier, the phase-lag capacitance requirement for ± 12-volt supplies shown in FigA is satisfactory for ±6-volt supplies, although smaller capacitors could be used with the lower voltages.
APPLICATIONS
For all applications, ac and dc balance at the
input must be preserved, i.e., the two inputs must be
returned to ground through equal impedances.
50.dB Amplifier

Fig.7 shows the circuit configuration and frequency response for a non-inverting, 5O-dB amplifier
employing phase-lead compensation. This amplifier

01\

.\
1\
0

'I

1\

5

15KQ

\

GIC

.,n

2030

40

NON-INVERTING GAIN-dB
!

6

0

,

19.1
29.7
INVERTING GAIN-dB

0

a

I

i'-r-,

40

"cC=-YEE=12V
PHASE-LEAD COMPENSATION, 2000 pF

~OPEN LOOP
COMPENSATED

"'-

50 I-- CLOSED LOOP

ClpF)=2

~

0

"

01

2

. ..

0

t'..... 1\

0

"-....

22

0

1\.\
\

I.

0

-I 0

\

•

0

0

..

2
4
1.0
FREOUENCl-MHI'

10

~

I\.

~

f\

0
6 8 ,00

0

QI

Fig.6 - Amount of phase-lag capacitance required
to obtain a flat (±I dB) response when phase·
lead compensation is used, and typical
response characteristics.

2

.

1.0

,

4

..

10

FREQUENCY-MHz

.. r\
100

Fig.7 - Circuit diagram and response curve for a
50-dB, non-inverting amplifier with phase-lead
compensation.

163

ICAN·5213 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
has a 3-dB bandwidth of 3.5 MHz, and a unity-gain
crossover at 150 MHz.
IO.dB, 42.MHz Amplifier

Fig.8 shows the circuit diagram and frequency
response for a 1O-dB, non-inverting amplifier employing both phase-lead and phase-lag compensation.
Slight peaking (2 dB) occurs for the phase compensation
shown. Flat response with bandwidth reduction to
25 MHz may be obtained by use of a phase-lag capacitance of 15 picofarads.

C~IKll

IKll
C,

27QpF

-=

C,

I r-..---:)

ISOpF ~OPF

510.a.

-=

5

AMPUF~.
Q"2_8

5

I0

/

5

"\

'~WW-T
0 14.4

I

........

0

/" V

0.6

0

\~

/11

0

5

hc\

I

0

~

I

,..-

,

1

1.0

0.8

FREQUENCY -

1.2
MHz

Fig.9 - Circuit diagram and response curves for a
bandpass amplifier using a twin-T network.

2 kll
Ikll

The symmetrical twin-T network can be designed
by use of the following equations:

fl 11111111111 ~ITNII
O~I

01

I

10

~

FREQUENCY-MHz

Fig.S - Circuit diagram and response curve for a
lO·dB, non-inverting amplifier with phase-lead
and phase-lag compensat ion.

Twin· T .Bandpass Amplifier

Fig.9 shows the circuit diagram and frequency
response of a bandpass amplifier using a twin-T network in the feedback loop. The difference in resonant
frequency between the bandpass-amplifier response
and the twin-T network response is caused by device
capacitances and loading effects. The unloaded Q
(Qo) of the twin-T network is 14.4; the Qo of the bandpass amplifier is 12.8.

164

Rl = 2 R2
Cl = \2 C2
fo

= 1I(27TRl el)

It is important in the design of this type of bandpass
amplifier that the two inputs be returned to ground
through equal resistances; in this case a value of
2000 ohms is used.

20.dB, IO·MHz Bandpass Amplifier

Fig.lO shows the circuit diagram and frequency
response of an RLC bandpass amplifier. This amplifier is designed to have a Qo of about 10 ?I

I

l

I

L___

I

T...
.J

..'MA,j\""r6-B-K--.

:-----r-~~

1.5 K

I

5 :
I

I

I

150

41

L

-------~

AF

OUTPUT

+9V

T 1· for details see Fig.7
T 2· TRW No.22960·R2 or equiv.
T3 • TRW 23148 or equiv.

Fig.6 • IO.MHz if amplifier and detector.

171

ICAN-5269---------------------------

LI027

tf~
Winding 1-5 - 17 turns #36SE or equlv_, Q/L'l< 70
Winding 3-4 - 40 turns I36SE or equlv., Q/L'l< 75
Winding ~ - 5 turns max; RX-Meter-900 ohms (no load)
Tuning slug: Winding 1-5 - Carbonyl TH or equlv., 1/4" long
Winding 3-4 - Carbonyl TH or equiv., 5/16"long
Front End: KQ 5. I, Lm = K "'LA LB = 0.049/LH

TEST CIRCUIT:

TI-2IOKHZ
0.001

-J20dS

100

o--llf-.,......®-lh
202H+
201H

50
pF

SET-UP

~2

\:--600 KHz

10K

SCOPE

TO 6
16dB

Fig_7 - Details 01IO.7.MHz input IiIter, TI.

*

Internal Connection -

Note: R6 Del eted

4
92CM-13780

Fig.8. Schematic diagram 01 RCA CAJOl2 wide-hand amplifier.

172

Do Not Use

ffilm5LJD

Linear Integrated Circuits

Solid State
Division

Application Note
ICAN-5290

Integrated-Circuit Operational Amplifiers
An operational amplifier is basically a very-highgain direct-coupled amplifier' which uses feedback for
control of response characteristics. This circuit can be
used to synthesize a broad variety of intricate transfer
functions and thus can be adapted for use in many
widely diverse applications. The operational amplifier
is principally used to perform various mathematical
functions, such as differentiation, integration, analog
comparisons, and summation. This versatile circuit,
however, may also be used for numerous other applications that have significantly different transfer and response requirements. For example, the same operational
amplifier may be adapted to provide either the broad,
flat frequency-gain response required of video amplifiers
or the peaked responses required of various types of
shaping amplifiers.

GENERAL CONSIDERATIONS
The configuration most commonly used for operational amplifiers is a cascade of two differential-amplifier circuits together with an appropriate output stage.
The cascaded differential-amplifier stages not only
fulfill the operational-amplifier requirement for a highgain direct-coupled amplifier circuit, but also provide
significant advantages with respect to application.

From' an applications standpoint, an operational
amplifier that has a differential input is much more
versatile than a single-input type. This increased versatility results from greater flexibility in selection of
the feedback configuration. With a single-input operational amplifier, only an inverting feedback configuration
can be employed. When differential inputs are used, the
feedback configuration may be either an inverting type or
a noninverting type, which depends on the common-mode
rejection for its negative feedback. The type of feedback affects the characteristics of an operational amplifier, and the two types tend to complement each other.
Because the characteristics of each type are required
equally often, the differential-input operational amplifier
is twice as versatile as the single-input type.
The differential-input operational amplifier is readily adapted to integrated-circuit construction techniques
because the stable dc-amplifier configuration lends itself
well to the monolithic diffusion process used in the
fabrication of silicon integrated circuits. In addition,
symmetrical differential-amplifier stages can be dc-cascaded readily, provided that each stage is driven pushpull by the preceding stage. The common-mode effects
that result from this arrangement make possible stable,
direct-coupled cascaded.

3·70

173

ICAN·5290 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
The capabilities and limitations of operational
amplifiers are firmly defined by a few very simple equations and rules. which are based on a certain set of
criteria that an operational amplifier must meet. Effective use of these simple relationships. however. requires
knowledge of the conditions under which each is applicable so that errors that may result from various approximations are held to a minimum. This Note explores the
theory of the design and use of operational amplifiers.
and develops each pertinent design equation in a general
way. Evaluations arethen made to determine the assumptions that must be made (or the criteria the operational
amplifier must meet) to reduce these general equations
to classical operational-amplifier design equations.
Frequency instabilities in the oPerational amplifier
and the methods used to prevent them are also discussed.
A thorough understanding of the principles of frequency
stability is imperative to the successful application of
operational amplifiers. The basic concepts and techniques involved in phase compensation (frequency stabilization) are explained in terms of (1) basic frequencystability requirements. (2) the problems that may result
from an uncontrolled frequency response. and (3) the
techniques that may be used.to correct these undesirable
effects.
Finally. the basic criteria for an operational amplifier are given. This discussion is placed last because
a basic insight to the theory of application is required
before the effects of many of the operational-amplifier
requirements can be fully appreciated.

BASIC THEORY OF OPERATIONAL AMPLIFIERS
In the development of the basic equations and
concepts associated with the use of operational amplifiers. the precise formulations for the transfer functions.
the input impedances. the output impedances. and the
loop gains are presented for both the inverting and the
noninverting feedback configurations. and classical
design equations are then derived from these precise
formulations. The effects of the load impedance and
of common-mode gain (or common-mode rejection) on
the inverting and noninverting feedback configurations
are considered separately.
Inverting Feedback Configuration
An operational amplifier operated with an inverting
feedback configuration is shown in Fig.I. The load
resistor R L is assumed to be large enough so that its
effect on tbe transfer characteristic is negligible. i.e .•
lOUT = o. (The effects of a finite R L are investigated
and evaluated subsequently in the discussion of the
equivalent-circuit model of an operational amplifier.)

Certain differential-input operational amplifiers require a significant flow of bias current at each input.
For this condition. the dc paths to ground for each input

174

must be equal so that a minimum dc offset voltage (error)
is developed at the output. Thus. for the terminology
employed .in Fig.l. Rr must equal the parallel combination of Z/.'" =0) with the series combinationofZt<'" =0)
and ZOi('" 0).

=

In the circuit of Fig.l. the drive-source impedance
affects the feedback in the inverting configuration and.
therefore. must be considered part of the' Zr term. For

R,

V;
VOUT
--+

lOUT

z,

I,
F'ig.l -Inverting·feedback operational-amplifier
configuration.
brevity. the symbol Zr is defmed to include the source
impedance as well as certain feedback design elements.
The impedances Zj and Zoi are the open-loop intrinsic
input and output impedances of the operational amplifier.
Ordinarily. these impedances are assumed in the amplifier symbol. In Fig.l. however. they are identified to
emphasize their importance in the ensuing equations.
The term A o("') is the open-loop differential voltage gain
of the operational amplifier; this parameter is frequencydependent. The terminals on the operational-amplifier
symbol labled minus (-) and plus (+) refer to the inverting and noninverting input. respectively.
Inverting.Configuration Transfer Function - The
transfer function or closed-loop gain of an operational
amplifier is generally considered to express the relationship between the input and output voltages. (It is relatively simple·to convert the voltage transfer function to
another desired transfer relationship.) In the derivation
of the transfer function for the schematic. in Fig.I. the
following differential-amplifier relationship is used as
the starting point:
VOl = -Ao("') (Y. - VI)
(1)

where V. and V. are defined as follows:

"
Ve =

VIN (Z,+Z••)/(Z.+R,) ,
Zr

+ (Z,+ZOi),I'(Zi+Rr)

..

VOl Z,/(Z,+R,)

Z, + Zo, + Z,/(Z,+R,)

(2).

v. R,/(Z, + R,)

(3)

and

V, =

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ICAN-5290
(In these and subsequent equations, the load resistor
RL is assumed to approach infinity_)

When the transfer function is given by Eq. (7), the
loop-gain equation may be written as follows:

If the expressions for Ve and V i given by Eqs. (2)
and (3) are substituted in Eq. (1), the resulting expression can be simplified as follows:

(Z,+Z.,) (Z,+R,)+Z, (Z,+Z.,+Z,+R,)+A.(",)Z, Z,
(4)

~

(5)

(6)

If Z i is assumed to be much greater than the combination of Zr in parallel with Zf + Zoi, and if Zoi is assumed to be much smaller than Z f' then the closed-loop gain
(or transfer function) may be expressed as follows:

VIN

-A.(",) Z,

..

Z,

+ Z, + A.(",) z,

z,
Z,

(8)

Eq. (8) is considered to be the classical or ideal
expression for the closed-loop gain (transfer function)
for an operational amplifier that uses the inverting type
of feedback configuration.
The difference between the open-loop gain and the
closed-loop gain is in itself an important design parameter. This "gain throwaway", which is koown as the
loop gain L.G., is defined by the following equation:
L. G. = open-loop gain, A.(",)
. VOUT
ciosed-loop gam, VIN

(11)

The loop-gain parameter can be used to predict the
accuracy of the approximate operational-amplifier relationships. In general, the higher the loop gain, the more
accurate the results provided by the approximate (or
classicai) relationships. This correlation is demonstrated in Table I, which compares values of VOUT/VIN
obtained from the precise transfer expression, Eq. (6),

C••dltIDIS: Ao(r.:)::;;:

z,/D-

(....-1)

200,000
100.000
30,000
10,000
2,000

looo!!!.. ZI

= 15,000 !!!..O, l"l = 200 !!..O, Z,
Your/V,N

= 1000!!!:._

--1!!'L.

__
(d_.)_

J!!l.

ErrDr

L.B.

46.0
40.0
29.6
20.0
6.03

44.3
39.1
29.3
19.9
6.0

1.70
0.90
0.30
0.10
0.03

14.0
20.0
30.4
40.0
54.0

You,,/V/N

froIlEq.(s)

(dB)

(7)

In addition, if the open-loop gain Ao(w) is the dominant
term in either Eq. (6) or (7), the transfer-function equation for the ihverting configuration simplifies to the
following familiar expression:
V OUT A.(",)- '"

L. G. '" -A.(",)
~

Table I - Comparison of Precise and Approximate
Formulas for Closed-Loop Gain (lnverting Configurationl

l., (Z,+R,) -

V OUT

(10)

Moreover, when the open-loop gain is very large, the
inverting loop gain can be considered to be the open-loop
gain divided by the ideal inverting closed-loop gain.
The equation for L. G. then becomes

z,

With VOl defined as indicated by Eq. (4), the accurate
equation for the transfer response (for R L - (0) becomes

A.(",) z, z,
(Z,+Z.,)(Z,+R,)+Z,(Z,+Z.,+Z,+R,)+A.(",)Z,Z,

A.~
Z,

Z,

The output voltage VOUT is expressed in terms of
VOl and VIN by the following equation:

VOUT = V., [Z, + Z,/(Z, + R,)]
Z., + Z, + Z,/(Z, + R,)
+
VIN Z., (Z, + Z.,)/(Z, + R,)
(Z, + Z.,) [Z, + (Z, + Z.,)/(Z, + R,)]

+ Z, _

L. G. = _ Z,

with values obtained from the classical approximation,
Eq.(8), for various gain settings. The tabular data show
that the classical equation is accurate to within I dB
provided the loop gain is at least 20 dB., Eq. (11) was
used to calculate all of the loop-gain values given in
the table.
Inverting-Configuration Input Impeclance, ZIN - The
input impedance ZIN for the inverting-feedback configuration of an operational amplifier, shown in Fig.l,
can be expressed as follows:

_ VIN
ZIN -lIN

where

V,
I IN =VIN'----

Z,

Therefore,

(13)

"

ZJ!I: =--~-'-

.
(9)

l--~
VI"

(14)

175

ICAN-5290 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

The ratio V ./V IN may be determined by substituting the expression for V 01 given by Eq. (4) into Eq. (2)
and dividing through by VIN (with RL - 00.) The resultant equation is then simplified to obtain the following
relationship:

(Z,+z . .> (Z, + R,)
z, (Z,+Z.. ,+Z,+R,) +(Z,+Zo,) (Z,+R,) +

=

1. Because of the virtual ground (V. = 0), the input
current I IN and feedback current If can be defined
as follows:
IrN = VIN

Z,

Ao(w)Z, Z,
(15)

If this expression for V./VIN is substituted intoEq.(14),
the result can be simplified to obtain the following
precise expression for the closed-loop input impedance:
ZIS

the negative terminal (i.e., Zj + Rr) is not zero. The
concept of a virtual ground leads to an extremely simple
three-step analysis. procedure for an inverting operational-amplifier configuration.

2. Zero current flow into the inverting terminal
(V e

= 0) indicates the following relationships:
lIN = I,

z, (Z., Z, +

z,

(16)

If Ao(w) is dominant and ZOj is small, Eq. (16)
reduces to
lIN '"

Z,

+ Z, (Z, + R,)
Ao(w)

z,

VIN

-VOUT

Z,

Z,

V OUT

(17)

A further simplification is possible when Rr is much
smaller than Z j, which' is a common condition. In this
case, the equation for the input impedance becomes

"'Z,+~

Ao(w)

(18)

Eqs. (17) and (18), which are important in voltagesumming or scaling-adder* applications, can be used to
predict the degree of interaction among multiple inputs.
When Ao(w) is large enough, Eqs. (17) and (18) may
be rewritten as follows:
~IN

A.. (w)-> '"

Zr

(23)

= _

Zf
Z,

(24)

Although the foregoing analysis is certainly an
idealized one, it is nevertheless practical because the
required approximations are usually valid. Eq. (15)
serves as a measure of the deviation from a true virtual
ground.
Inverting-Conliguration Output ImpeJance, ZOUT -

The closed-loop output impedance is the ratio of the
unloaded output voltage VO UT to the short-circuit output current lOUT as follows:
ZOUT = V OUT
IouI'

(19)

Eq. (19) is the "classical" equation for the input
impedance of an operational amplifier when an invertingfeedback configuration is used. This equation, together
with Eq. (16), implies the existence of a condition known
as a virtual ground at the node-assigned voltage V.
(shown in Fig.ll. That is, the node is at ground potential even though there is no electrical connection between this point and ground. [This statement can be
verified either intuitively by the use of Eq. (19) or
directly if Ao(w) is assumed to be infinite in Rq.(J5).]
Moreover, no current flows into the negative terminal
of the amplifier when the open-loop gain is infinite
because the voltage Ve is zero while the impedance at

(22)

3. Eq. (23) can then be rewritten to obtain the
classical gain equation, as follows:
VIN

ZIN

(21)

Z,

Z, +

Zo,R, + Z,R, + z, Z,)
(Z,+Z.,+Z,) + R, (Z,+Zo,) + Ao(w)Z, Z,

(20)

I,=-VoUT

(RL -> "')
(RL -> 0)

(25)

It is apparent from Fig.1 then that the output current
lOUT is given by
lOUT

(lh->O) = -Ao(w) (V. - V,)
Zo'

(26)

If the expression given by Eq. (3) is substituted for V j,
Eq. (26) can be rewritten as follows:
I

(R -> 0)

OUT

I.

=

-Ao(w) Z, V,
Zo. (Z, + R,)

(27)

Under short-circuit conditions , the voltage Ve
in terms of V IN is given by
V. =

*A scaling adder is an inverting operational-amplifier configuration which weights and sums multiple voltages.

176

VIN Z,/(Z,+R,)
Z, + Z,/(Z.+R,)

Z, (Z,+Z.+R,) + Z, (Z,+R,) (28)

ICAN-5290
Therefore, lOUT (at
of VIN as follows:
I

~L

= 0) can be expressed in terms

_
-A.(",) Z, Z, V'N
OUT - Z., IZ, (Z,+Z,+R,) + z, (Z,+R,»)

A noninverting operational amplifier, unlike the
inverting type, requires a differential-input arrangement
because it uses the common-mode effect in its feedback

(29)
VOl

If this expression for lOUT is substituted in Eq. (25)
and consideration is given to the intransience of V IN
in going from an unloaded to a fully loaded condition,
the equation for ZOUT becomes
ZOUT -_ Z., IZ, (Z,+Z,+R,) + z, (Z,+R,»)
-A. ("') Z, Z,

v,

+

liN

I

~ Zi

R,

(Vou.r)
--

VIN

I

lo,
-.J\/\.I\r--

RL

V,N

ZOUT=
Z.,IZ,(Z,+Z,+R,)+Z,(Z,+R,»)
IA.(",)Z,Z,-Z.,(Z,+R,»)
A.(",)Z,Z,IZ,(Z,+Z,,+Z,+R,)+
(Z,+Z.,)(Z,+R,)+A.(",)Z,Z,)
(31)
If the open-loop gain term Ao(w) is dominant, Eq. (31)
simplifies to
A.(",)

z, Z,

z, (Z, +

R,»)
(32)

This expression for ZOUT does not simplify to its
"classical" equation unless Zi is dominant also; in this
case, Eq. (32) becomes

ZOUT

1 +~
:::.Z.~
., A.(",)

Your

(30)

Finally, the desired equation for the closed-loop output
impedance is obtained if the expression for VOUT/VIN
given by Eq. (6) is substituted into Eq. (30), as follows:

ZOUT '" Z., IZ, (Z, + Z, + R,) +

-

lOUT

Ao{wl

(33)

The assumption that Zi is a dominant term is not always
valid, especially if bipolar transistor inputs are employed. Eq. (32), therefore, may be considered to take
precedence over Eq. (33).
Noninverting Feedback Configuration

Fig.2 shows the general circuit for an operational
amplifier operated with a noninverting feedback configuration. In this section, the equations for the transfer
function and the closed-loop input impedance for this
type of operational-amplifier circuit are derived. These
derivations, as did those for the inverting circuit, assume that the load resistor RL is large enough so that
its effect is negligible, i.e., RL -00 and lOUT =O. (The
effects of a finite load resistance on the noninverting
operational amplifier are evaluated in the discussion of
the equivalent-circuit model of an operational amplifier.)

Z,
V,

z,

Fig.2 - Noninverting-feedback operational-amplifier
configuration.

scheme. The following basic requirements and definitions that apply to the inverting circuit shown in Fig.l
are also valid for the general noninverting circuit of
Fig.2:

1. The dc return paths to ground for the two inputs
must be equal and finite for amplifiers that require a significant amount of input bias current.
2. The input and output impedances, Zi and Zo"
are inherent in the basic amplifier unit and ak
shown on the diagram to emphasize their importance in the relationships to be derived.
3. The open-loop gain is frequency-dependent and
is represented by the symbol Ao(w).
4. The plus and minus labels on the input terminals
designate the noninverting and inverting terminals, respectively.
In the noninverting circuit, however, the source impedance is included in the passive element Rr rather than
the frequency-dependent parameter Zr' as in the inverting circuit.

Noninverting-Configuration

Transfer

Function -

As with the inverting circuit, the transfer function developed for the non inverting operational amplifier shows
the relationship between the input and output voltages.
It is relatively simple to convert this relationship to
another type of transfer function.
When the load resistor RL approaches infinity, the

177

ICAN-5290 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
output voltage VOUT for the general circuit shown in
Fig_2 can be expressed as follows:

[Z,+Z,/(Z,+R,)]
Z.,+Z,+Z,/(Z,+R,)
+
V ,N Z., [Z,/(Z,+Z.,)]
(Z,+Z.,) [Z,+R,+Z,/(Z,+Z.,)

VOUT = V o ,

(34)

Eq_ (34) may be rewritten in the following form:

A.(",) Z, (Z,+Z,+Z.,) VIN
(Z,+R,) (Z,+Z,+Z.,) + Z, (Z,+Zo,) + A.(",)

z, Z,

(42)

If this expression for VOl is substituted into Eq. (35).
the new equatinn that results can be simplified and
divided through by V IN to obtain the desired· transfel
function. as follows:

VOUT =

v., [Z, (Z,+Z,+R,) + z, (Z,+R,)] + Z, Z., V
(Z,+R,) (Z,+Z,+Z.,) + z, (Z,+Z.,)

IN

(35)

The voltage VOl is defined by the differential-gain
expression. as follows:
V o, = A.(",) (V, - V.)

(36)

where Vi is the source voltage VIN less the voltage drop
across Rr • as given by
(37)

where

V,- V.
II N =
--Z,

Z, Z., + A.(",) z, (Z,+Z,)
(Z,+R,) (Z,+Z,+Z.,) + z, (Z,+Z.,) + A.(",)

VOUT ...
(Z,+Z,) A.(",)
V IN
(Z,+Z,) + Z, A.(",)

Eq. (44) may be rewritten as follows:

The voltage Vi> given by Eq. (37). can now be expressed
in terms of the voltages VIN and Ve. as follows:

VOUT ... _-,A.=(",,,,),-_

Z, V IN

+ R, V.

1

V ,N

(39)

V., Z,/(Z,+R,)
+
V,N Z,/(Z,+Z.,)
Z., + Z, + Z,/(Z,+R,) Z, + R, + Z,/(Z,+Z.,)
(40)

If the relationships for Vo I and Vi given by Eqs.
(36) and (39). respectively. are used. Ve can be expressed solely in terms of VIN. as shown by the following
equation:

V.=
(Z, z, + Z, Z., + A.(",) z, Z,) V,N
(Z,+R,) (Z,+Z,+Z.,) + z, (Z,+Z.,) + A.(",)

+ Z,/Z,

z, Z,

VOUT A.(",) ->

co

1

+~
Z,

(46)

The term 1 + Zr/Zr represents the closed-loop gain for
the ideal noninverting configuration. This term. which
is referred to as the ideal feedback characteristic, is
basic to operational-amplifier frequency-stabilization
theory.
As might be expected. the loop gain of an operational amplifier is defined in the same way [by Eq. (9)1
regardless of the type of feedback configuration. Under
the conditions for which Eq. (45) is a valid expression
for the transfer response. the loop gain for the noninverting configuration is given by

(41)
L. G.
Eqs. (36). (39). and (41) are now used to express VOl in
terms of VIN. as follows:

(45)

If the term Ao("') is dominant in Eq. (45). the following "classical" expression for the noninverting
transfer response results:

V ,N

V. =

(44)

A.(",)

-

It can be determined from Fig.2 that. when R L
approaches infinity. the voltage Ve is given by the
following equation:

178

+
1

Z,+R,

(43)

The transfer function that is usually associated
with the noninverting feedback configuration of an operational amplifier can be derived from Eq. (43) if the
impedance ZOi is assumed to be zero and the impedance
Zi is assumed to be very high. When these assumptions
are made. Eq. (43) becomes

(38)

v, =

z, Z,

=

1 + A.(",)
1

+~
Z,

(47)

ICAN-5290

If the second term of Eq_ (47) is very ,large, this equation reduces to

L. G. '" A.(w)

1+~

(48)

Zr

Table II compares the values calculated from the
precise and the approximate expressions [Eqs. (43) and
(46), respectively] for the closed-loop gain of the noninverting operational-amplifier configuration.
The
approximate formula is accurate to within 1 dB provided
Table II -

== 200 J!..\ z. ;::;

(53)
The following expression for the input impedance results
if Ao(uc) is also considered dominant:

Your/V/N

Vour/YIN
frolll Ell. (46)

. A.(w) Z,
ZIN =
--1 +~

L. G. from

~

'JIm Eq. (43)
~

Error
~

~

199,000
99,000
29,000
9,000
1,000

46.0
40.0
29.6
20.0
6.03

44.3
39.1
29.3
19.9
6.0

1.70
0.90
0.30
0.10
0.03

14.0
20.0
30.4
40.0
54.0

Ell. (48)

the loop gain is 20 dB or more. A comparison of Tables I
and II shows that the error. introduced by the use of the
classical gain formula for the non inverting configuration
[Eq. (46)] is identical to that introduced by the use of
the classical gain formula for the inverting configuration
[Eq. (8)].
Noninverfing-Conliguration Input Impedance, lIN -

Eq. (54) states that the non inverting input impedance is equal to the intrinsic input impedance Z i multiplied by the loop gain.
Noninverfing-Conliguratian Output Impedance, lOUT-

As in the inverting configuratiop, the closed-loop output
impedance for the noninverting configuration is defined
as the ratio of the open-circuit output voltage, VOUT,
to the short-circuit output current, lOUT, as follows:
ZOUT = Vou 'r (RL ---> "')
lOUT (RL ---> 0)

where

lOUT (RL

The following equation gives the basic definition of
the input impedance ZIN:
ZIN = VIN
lIN

(49)

(54)

Z,

1000 J!.."

loIIii')

--->

0) = A.(w) (V.- V.)

Z.,

(56)

V, (RL -> 0)

=

VIN (Z, + Z,/Z,)

R, + Z, + Z,/ZI
=

VIN - V.
Z,+R,

=

V. (R L

(50l

Z, + R,

1-~
VIN

(57)

and

When this relationship is applied in Eq. (49), the expression for the noninverting input impedance becomes
ZIN

(55)

For the general non inverting operational-amplifier configuration, the voltages Vi and Ve are given by the
following equations for the conditions indicated:

It can be readily determined from Fig.2 that the input
current lIN is given by
lIN

(52)

For the case where Zi is dominant and Zoi is small,
Eq. (52) reduces to

Comparison of Precise and Approximate
Formulas for Closed-Loop Gain
INoninverting Configurationl

CODditl,.s: A.. (w) = 1000 ~ •• II :::: 15,000 ~., 2".

Z,/]'

ZIN = ZI + R, + Z, Z, + Z., + A.(w) Z,
Z,+ Z, + Z.,

--->

VIN Z,/ZI

0) =

R,

+ z, + Z,/Z,

On the basis of the relationships expressed by
Eqs_ (57) and (58), Eq. (56) may be rewritten as follows:
lOUT (RL

--->

0) =

A.(w) VIN Z, (Z, + Z,)
Z., [(Z, + Z,) (R, + Z,) +

(51)

If the expression for the ratio of Ve/VIN' given previously by Eq. (41), is substituted into Eq. (51), the
result can be simplified to obtain the following precise
expression for the input impedance (for R L - (I):

(58)

z, Z,J

(59)

The output impedance ZOUT then hecomes
Z

- Z [Z' ZI + (Z, + Z,) (R, + Z,)] (VOUT)
ol
Ao(CtJ) Zi (Zr + Zf)
VIN
(60)

OUT -

179

ICAN-5290 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Finally, the following precise equation for the output
impedance ZOUT is obtained when the ratio for VouTI
VIN is replaced by its impedance equivalent, as given
by Eq_ (43):
ZOUT = ZOl !(Z,+Z,) (R,+Z;) + Z,Zrl
Ao(w) ZI(Z, + Z,)

x

Z, Zo; + Ao(W)ZI (Z,+Z,.)
(Z,+R,)(Z,+Z,+Zo,)+Z, (Z,+Zo,HAo(w) ZIZ"
(61)

If Ao(w) is dominant, then Eq_ (61) becomes

z

~ Z [Z' Z, + (Z, + Z,) (R, + Z;)]
OUT - 01
Ao(w) Z, Z,

1 +~

Z
Z
Z,
OUT '" 01 Ao(W)

(63)

This classical expression indicates that the output
impedance of the noninverting configuration is equal to
the intrinsic output impedance ZOi divided by the loop
gain_ It should be noted that the classical expressions
for the closed-loop output impedances for the inverting
and noninverting configurations [Eq. (33) and (63),
respectively 1 are identical.
Equivalent-Circuit Model of a Closed-Loop
Operational Amplifier

Fig.3 shows the equivalent circuit of a closed-loop
operational amplifier. This equivalent circuit is valid
for either the inverting or the noninverting configuration.
In the inverting configuration, Z r is used to represent

I

I
Zr OR Rr

(VouT/V,Nlv,Nl

I

I

I
I
I
I
I

I
I
I
L __________________________ J

I
I

AMPl.IFIER WITH FEEDBACK

Fig.3 - Equivalent-circuit model of ci closed-loop operational amplifier.

the impedance in series .with the closed-loop input impedance ZIN. In the noninverting configuration, term

180

Eflect of a Finite Load Impedance on OperationalAmp/Wer Characteristics -One of the important features

of the equivalent-circuit model is that it accurately
accounts for the effects of a finite load impedance, RLFor example, if a 2000-0hm load impedance is used on
the 46-dB (approximate) inverting amplifier for which
data are given in Table I, the equation for the transfer
response must be modified as follows:

(62)

The expression for the closed-loop output impedance
does not revert to its classical form unless both the
intrinsic input impedance Z i and the open-loop gain
Ao(w) are very large_ Under such conditions, the equation for the output impedance reduces to

z,

Zr is replaced by Rr to show that the components thus
represented are independent of frequency. The closedloop input and output impedances (ZIN and ZOUT' respectively) and the transfer function VouTIVIN were
defined previously_

,

IN

(~~T) V RL
VOUT = -'--::0=-'--::--RL + ZOUT

(64)

If Eq_ (6) is used to determine the value of VOUTIVIN
and Eq. (30l is used to determine the value of ZOUT,
the transfer-function ratio for an RL of 2000 ohms can
be calculated from Eq. (64) as follows:
.
VOUT
V

IN

=

164 (

2000 ohms
)
37.4 ohms + 2000 obms

=

162

(65)

Thus, a ratio of 44.15 dB is obtained, as compared to
44.3 dB for an open-circuit load. Similarly, if a 2000ohm load is used for the 6-dB amplifier, the gain becomes 5.98 dB, as compared to 6 dB indicated in Table I
for an open-circuit load. The error in neglecting a
2OQo-ohm load, therefore, is 0.15 dB for the 46-dB
amplifier and only 0.02 dB for the 6-dB amplifier (for
the conditions given in Table I).
Eflect of the Common Mode Gain (CMG) on Operational-Amplifier Characteristics - In the developments

of the basic equations for the inverting and noninverting
feedback configurations of the operational amplifier, it
was tacitly assumed that the common-mode gain was
essentially zero (infinite attenuation). The commonmode gain is defined as the ratio of the output voltage,
VOUT, to the input voltages, Viand Ve, when Viand
Ve are identical in amplitude and phase. The validity
of this as~umption is considered separately in this
section because the basic feedback equations become
burdensome when common-mode effects are included.
As a result, the salient features of these equations
become obscured.
An examination of Figs. 1 and 2 shows that, in
either the inverting or noninverting configuration, the
differential gain acts on the difference between the
voltages Vi and Ve' On the other hand, the commonmode gain acts on those portions of Vi and Ve that are
in phase and identical in magnitude. That is, the com-

-

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ICAN·5290

mon-mode gain acts on the smaller of the two in-phase
signals (V i or V.). In the inverting configuration Vi
is less than V e' but in the noninverting configuration
V i is greater than Ve' These conditions are reflected
by the output-voltage equations when the effects of the
common-mode gain (CMG> are considered, as follows:

=

CMR» R,

Z,

A. (w) (V, - V,) ..:. (CMG) (V,)

CMR»Z, +R,

(66)

Z,

2. For the noninverting configuration,

V. l

=

A. (w) (V, - V.) -(CMG)(V,)

(67)

If these two equations are developed further, the
following gain expressions are obtained for ZOi = 0
(i.e., VOi =V OUT ):
1. For the inverting configuration,
VOUT ="
VIN
-A.(w) Z, Z, - (CMG) R,

z, (Z,+Z,+R,)+Z, (Z,+R,)

(72)

2. For the noninverting configuration,

I. For the inverting configuration,

V. l

loop gain, Ao ("'), divided by the common-mode gain,
CMG. The following inequalities are then obtained:
I. For the inverting configuration,

z,

+Z, Z, A.(w)+R, Z, (CMG)
(68)
2. For the noninverting configuration,
VOUT =
V IN

+

A.(",) Z, (Z,
Z,) - (CMG) Z, Z,
(Z,+Z,) (R,+Z,)+Z, Z,
+A.(w) Z, Z,+(CMG) Z, (Z,+R,)

(73j

Neither of these inequalities places a suingent
resuiction on common-mode rejection.

FEEDBACK PHASE SHIFTS IN OPERATIONAL
AMPLIFIERS

In an operational amplifier, as in any other feedback amplifier, the phase of the feedback must he contIolled to assure that the design is stable with frequency
and that the desired gain-frequency response is obtained.
Fig.4 shows the gain and phase characteristics as
functions of frequency for a typical 6()..dB operational
amplifier in which no phase-compensation techniques
are employed. Over the frequency range shown, the
change in the phase of the feedback is substantially
greater than 180 degrees. This phase response indicates
that a low-frequency negative feedhack can hecome
positive and cause the amplifier to be unstable at high
frequencies unless phase-compensation methods are
employed to stabilize and control the response of the
amplifier.

(69)

In each case, the criteria for the common-mode gain,
CMG, to he negligible compared to the open-loop gain,
Ao(w), are as follows:
1. For the inverting configuration,
CMG « A.(",) Z,

R,

(70)

2. For the noninverting configuration,
CMG« A.(",) Z,
Z,+R,

(71)

Eq. (68) or inequality (70) shows that the gain of
an inverting configuration is not affected by the commonmode gain when the input impedance V i is assumed to
be inf"mite. However, when this same assumption is
made for a noninverting configuration, the gain is dependent upon the common-mode gain provided the openloop gain is finite.
Inequalities (70) and (71) may be given in terms of
the common-mode rejection, CMR, which is the open-

Effect of Excessive Phase Shift on Frequency Stability
The uansfer equation for the inverting configuration, Eq. (7), can be rearranged so that it reflects the
same classical feedback form as that for the noninverting configuration, given by Eq. (45). These equation"s,
which are based on the assumptions that Zi approaches
infinity and Zoi is zero, are repeated below for convenience:
1. For the inverting configuration,

VOUT

V",

=

(

Z,

Z,

) [

+ R,

-A. (w)

1 + A.(w}

1

I+~
Z,

2. For"the noninverting configuration.
VOUT
V IN

=

1

A. (w)
A.(w)

+

1

+~
Z,

181

ICAN-5290 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
o

ii!l

•

--- .....

I'---..

-90

i

60

~1i+r----.~~ I
~~LI:"diS:

~

I

~,

-135

4o

~~.,~

20

~

.~

0

-

~-180

~

20

""

•

-22

-270
0.01

0.1

4

1.0

40

.........

-

60
100

10

FREQUENCY-MHz

F'ig.4 - Gain and phase response of an open-loop operational amplifier operated without phose compensation.

If the phase angle Df the feedback tenn, Ao(w)1
ZrlZr), reaches 180 degrees (nDt asymptotically)
while the magnitude Df the tenn is still unity Dr greater,
DscillatiDns will DCcur. (If the term is greater than
unity, the DscillatiDns will build until limiting occurs.
This limiting decreases Ao(w), and thus the entire feedback term, until unity magnitude at a phase angle Df
180 degrees is achieved.) These unstable cDnditiDns
can be predicted readily: Fig.5 ShDWS a superpDsitiDn
Df the gain-frequency curve shDwn in Fig.4 Dn several
(1 +

I II 20 dB/DECADE OR 6 dB/OCTAVE
2!! 40 dB/DECADE OR 12dB/OCTAVE
3!60dB/DECADE OR 18dS/OCTAVE
60

OPEN-LOOP RESPONSE

40

STABLE (I+Z,/Z,}-40dB

ill

PHASE OF AO("')15 180·

I

z

~

20

UNSTABLE O+Zf /Z,)=20dB
UNSTABLE (I+ZflZrJ=12dB

FREQUENCY

On the Dther hand, if this tenn is less than unity, then
the cDnfiguratiDn is stable. This stability-detenninatiDn technique is applied to the variDus values Df 1 +
ZIZr shDwn in Fig.5; in each case, the gain Df the
amplifier at the frequency fDr which the phase angle is
ISO degrees is assumed to' be 10 (i.e., Ao(f180) = 10).
When 1 + ZIZr = 100/00., the stability ratio. is
calculated as fDllDWS:
A.(f 18o) = 10/180: = 0.1O/1SO.
z, 100/0·
-1+-

z,

Because the value Df 0.10 Dbtained fDr the stability
ratio. .is less than unity, the cDnfiguratiDn is stable.
When 1 + ZIZr = 10.0/00., the stability ratio. beCDmes
A.(f 18o)
Z
1+..1

Z,

182

10/0·
-

--

FDr this case, the stability ratio. is unity, and the CDnfiguratiDn therefDre, is unstable. As a check, an examinatiDn Df the transfer expressiDns fDr both the
inverting and the nDninverting cDnfiguratiDn (Eqs. (7)
and (45») reveals that fDr the cDnditiDn specified, each
cDntains the fDllDwing tenn:

F'ig.5 - Open-loop response and stability characteristics
of an operational amplifier.

sample plDts Df the ideal feedhack characteristic, as
given by 1 + Zr/Zr when Zr and Zr are purely resistive.
Because the crucial frequency fDr a purely resistive
feedback netwDrk is that at which Ao(w) has a phase
angle Df 180 degrees, the magnitude Df Ao(w)/(l + Zr/Zr)
at this frequency (f180) detennines whether the CDnfiguratiDn is stable. If Ao(f180)/(l + Zr/Zr) is equal
to Dr greater than unity, the cDnfiguratiDn is unstable ..

= 10/180· = 1.0/180.

1 + 1/180·
which is nDt finite and, therefore, indicates an Dscillating cDnditiDn.
When 1 + Z,/Z, = 4.0/0·,
A.(f lSo) = 10/180· = 2.50/180.
Z
4/0·
-1+...l.
Z,

-

ICAN·5290

The value obtained IS greater than unity, and the circuit,
therefore, is unstable.
When Zr and Zr are not restricted to purely resistive values, a more general situation exists because
the phase of Ao(w)/(l + Zty'Zr) is no longer dependent
solely upon Ao(w). Two examples which essentially
cover the field are given below.
Example No.1 - A characteristic of differentiating
or peaking circuits is that the feedback term 1 + Zr/Zr
is in the form K(l + jf/fl), where K and fl are constants.
Fig.6 shows a curve of this term as "a function of fre60 I-"'=-="'-=~:':::

I
I
I

40

I
1",4

'"I
~

z

r.43

20

I

CLOSED - LOOP q.:

I
I
I

~

1

'180=0,746

I
I

0r-------~_r--~r__f-------4r_----

FREQUENCY -

MHz

A.(",) =

stability ratio is greater than one; therefore, the configuration is unstable. The point of instability (fI80)
is marked in Fig.6.
The stability of an operational amplifier may be
determined more easily from an estimate of the phase
angle of the ratio Ao(w)/(l + Zr/Zr) at the frequency
of intersection (where the magnitude of the ratio is
unity). If the estimate shows that the phase angle is
less than 180 degrees," the configuration is stable. On
the other hand, if the estimate indicates a phase angle
in excess of 180 degrees, the circuit is unstable. When
the estimate shows that the phase angle is near 180
degrees, an accurate calculation is required to determine whether the operational amplifier is stable. This
border-line type" of configuration, however, is generally
undesirable from the standpoint of frequency response,
as discussed later.
In the application of the estimation technique to the
problem presented in Fig.6, the following conditions
should be noted: The feedback characteristic 1 + Zr/Zr
increases at the rate of 6 dB per octave (20 dB per
decade) for a full decade before it intersects the openloop response, Ao(w). The intersection occurs near
the second comer of the open-loop response, which
decreases at the rate of 6 dB per octave for almost a
full decade. The classical phase relationships associated with these observations are used to obtain the following phase estimates:
Phase of (I + Zr/Z,) = +90 0
-135 0 < Phase of A,,(w)< -90 0

1000

(1

+ j 0.2 ~Hz) ( 1 + j 2 ~Hz) ( 1 + j 20 ~Hz)
1 +~ =10 (1 +j __f_)

-225 0

0.1 MHz

Z,

Therefore, the following phase estimate .is obtained at
the frequency of the intersection:

Fig.6 - Basic peaking response characteristics of an
operational amplifier.
quency, for K = 10 and fl = 0.1 MHz, superimposed
upon an operational-amplifier open-loop transfer curve.
The equation for the open-loop characteristic can be
derived from Fig.5, as follows:

< Phase of Ao(w)/(l + Zr/Z,) < - 180

Thus, the configuration is unstable.
Example No.2 - An inherent characteristic of integrating or band-limiting configurations is that the
feedback term 1 + "Zr/Zr has the following form:

K
1

A.(",) =

1000
(1

+ j 0.2 ~1Hz) ( 1 + j 2 :\~Hz) ( 1 + j 20:\~Hz )

(74)

The frequency at which the stability ratio A o(w)/l +
Zr/Zr has a phase angle of 180 degrees and the magnitude of the ratio for this frequency can then be calculated. The computation reveals that the phase angle is
180 degrees at a frequency (f180) of 0.746 MHz, and the
magnitude of the ratio is 3.22 at that frequency. The

0

+ jf/f,

An example of this type of feedback characteristic is
shown in Fig.7 for K =10 and fl = 4 MHz. The application of the phase-estimation technique to this problem
results in the following estimates:
-45 0 > Phase of 1 + Zr/Z, > -90 0
-135 0 > Phase of A.( .. ) > -225 0
At the frequency of intersection, therefore, the phase
estimate is given by
-45 0

> Phase of A.( .. )/(l +

Zr/Z,)

> -180

0

183

ICAN-5290 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Thus, the configuration is stall/e.
If the three basic types of feedback characteristics
shown in Figs.5, 6, and 7 are compared, it becomes
evident that the differentiating or frequency-peaking
60

The following substitution is first made in inequality
(75):
A.(OI) .. B/O

1+~
Z,

OPEN -LOOP RESPONSE

--

(76)

If both sides of inequality (75) are then divided by the
left-hand term, the following result is obtained:

40



MHz

FREQUENCY -

Fig.7 - Basic integrating response characteristics of an
operational amplifier.

[(1 + ~ cos 0)' + (-t sin 0)'J

(78)

or
(79)

configuration is the most unstable and that the integrating or low-pass configuration is the most stable. In
fact, the techniques used to devise this latter configuration may be considered a form of phase compensation
for certain situations, as discussed later.
Effects of Excessive Phase-Shift on Frequency Response

The criterion evolved for frequency stability neither
precludes uncontrolled frequency peaking nor provides
for a 3-dB closed-loop bandwidth prediction. The conditions that are required to develop a stable, controlledresponse feedback amplifier are evolved in this section.
Criteria for a Peaked Response - Frequently peaking results wben the magnitude of the true closed-loop
gain, as given by Eq. (7) for the inverting configuration
and by Eq. (45) for the noninverting configuration, is
greater than the magnitude of the ideal closed-loop
gain (Zr'Zr for an inverting circuit and 1 + Zr/Zr for a
noninverting circuit). The criteria for frequency peaking
can be expressed for both configurations by the following expressions:

A.(",)
1
A.(w)

+

1

+~
Z,

>

1

l>ll+tcos O
and

I

1>~I-Sinol

(80)

(8ll

It is apparent from inequality (SO) that

B>..!.
2

(82)

and from inequality (79) that

cos 0 <

2B

(83)

The substitution indicated by the identity (76) is
again made, and both sides of inequality (75) are then
divided by t.he right-hand term to obtain the following
expressions:

+~

Z,

(75)

Inequality (75) may be used to develop a set of criteria
that predict frequency peaking (or preclude the occurrence of frequency peaking).

184

The real and irii~inary parts of inequality (78) must also
be less than unity, so that

I
I1 B/O
+B~ > 1
or

BL!...I

>

I 1 +B/O

(84)
(85)

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ICAN.5290

Por pm/IiI//! 10 o('('ur, the following r<,lutionships IIIlIst
be in eflect:
0.5 <

I

cos 0

II~

<

211

3·dB Bandwidth Prediction - The 3-dB bandwidth
of an operational amplifier is defined by the following
condition:

+ ZfIZ,.. must
al a s/oIU'

/('.0;,<;

illil'rsC'C'i

tile'

o#Jc'n-loop responsc', ,·\af.. ),

thall 12 dB IIl'T O('/CU'C',

An (lxulllinatiol1

of lhis "rul(, of' thumb" in terms or the phase rdatinnship
indicate'S that the phus,-' ang-It' asymptotically apprOueh(ls
180 d('grces \"hell the change in amp Iificr rl'RIl()m;(.~ with

frequency occurs lit a rat" of 12 dB per octave. Therefore, the amplifier is on the threshold of instabil it.Y.
Frequency dependence of less than 12 dB per octave
indicates that the amplifier is stsble; a dependence of
greater th"n 12 dB per octave indicates that the amplifier is unstsble.

PHASE·COMPENSATION TECHNIQUES
FOR OPERATIONAL AMPLIFIERS
(86)

The terms of Eq. (86) are rearranged and the definition
for B @... given by the identity (76) is used to obtsin
the following relationships:

(1 + t cos 0)' + ( --k sin 0)'

=

:1

(87)
Eq. (87) yields the following criteria for the 3-dB point:
I > B > __1__
1 +V2

=

B' - 1
C080=-2B

0.41-1

(88)

(89)

Inequality (88) predicts the possibility of a 3-dB
bandwidth greater than that indicated by the intersection
of Ao(U:) and 1 + Zr/Zr 

4

6

/"
-10

k-- I--

V

(
\

I2

BQI

2

4

6

IIIIOESIREO SIGNAL VOLTAGE-RMS
(FOR 10'110 CROS5-MOIlULATION OISTORnONI

Fig.7-1n·bantl crtm-modulation characteristic of Jj·MH.
ampUfier of Fig. 6 (data taken with untuned input).

Final If Amplifier Stage and Second Detector

Fig. 8 illustrates the use of the CAl018 as a last if
amplifier and second detector (0.1 volt emitter voltage on
terminal 1). The bias on transistor Q. is maintained at
approximately cutoff to permit the cascaded emitter·fol·
lower configuration (Q. and Q.) to be used as a second
detector. Because this stage is driven by a common col·
lector configuration, the input impedance to the detector
can be kept high. A low output load impedance can be
used as a result of the output current capability of the
cascaded emitter-follower configuration. The input impedance (terminal 9) of approximately 9000 ohms is largely
determined by the bias network. A minimum if input power
of 0.4 microwatt must be delivered to terminal 9 for linear
operation. The audio output power for 60 per cent modulation for this drive condition is 0.8 microwatt. Linear detection is obtained through an input range of 20 dB for 60
per cent modulation. This detector arrangement requires
less power-output capability from the last if amplifier
than a conventional diode detector- yet allows a low dc
load resistor to achieve a good ac-to-dc ratio for the first
audio amplifier.

196

•

LO

The if amplifier of Fig. 8 has a voltage gain of 30 dB at
1 MHz. Transistor Q 1 is used in the base-bias loop of the
common-emitter amplifier Q 2 to stabilize the output operating point against temperature variations. This arrangement also elimin2tes the need for an emitter resistor and
bypass capacitor, and thus provides a larger voltage-swing
capability for Q2' If Q2 is biased conventionally with
base-bias resistors, Q 1 can be made avaHable for the first
audio or age amplifier.
Class B Amplifier

Characteristics were obtained on a low-Ievel class B
amplifier to establish the idling-current performance of
nearly identical devices on a single chip with respect to
temperature variations. The transistors in the CA3018
can be used only for low-power class B operation (maximum output of 40 milliwatts) because of the hBE roll-off
and moderately high saturation resistance at high currents.
A typical circuit is shown in Fig. 9. Idling-current bias is
provided to Ql and Q2 by use of transistor Q. as a diode
(with collector and base shorted) and connection of a
series resistor to the supply. The idling current for each
transistor in the class B output is equal to the current
established in the resistance-diode loop. Because the resistor Rl is the predominant factor in CODtroUing the
current-in the bias loop, the bias current is relatively independent of temperature. In addition, because the devices
bave nearly equal characteristics and are at the same
temperature, the idling current is nearly independent
through the fuU military temperature range. The total
idling current for transistors Ql and Q2 in Fig. 9 varies
from 0.5 to 0.6 miiiiampere from -55 to + usoe. Excellent balance between output devices is achieved throughout the range.
AC feedback as well as dc feedback can be obtained by
substitution of two resistors R2 and R. in place of R 1,_

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ICAN-5296
as shown by the dotted lines in Fig_ 9_ These two resistors, which have a parallel combination equal to R 1 , are
connected between collector and base of transistors Q2
and Ql- The added feedback reduces the power gain by
approxinlately 6 dB (30 to 24 dB), but improves the
linearity of the circuiL Although the output-power capability for the circuit shown in Fig_ 9 is approximately 18
milliwatts, output levels up to 40 milliwatts can be obtained in similar configurations with optimized components_

".
r--'''''··--•••n i

I
I

T.

~_-L_-I

T,

IOO-MHz Tuned RF Amplifier
Fig. 10 illustrates the use of the CA3018 in a 100-MHz
cascade circuit with an age amplifier. Transistors Ql and
Q2 are used in a casccde configuration, and transistors
Q 3 and Q. are used to provide an agc capability and
amplification. With a positive-going agc signal, current in
the cascode amplifier is transferred to the Darlington configuration by differential-amplifier action_ This agc amplifier has the advantage of low-power drive (high input
impedance). In addition, the emitter of Ql can be backbiased with respect to the base to provide larger inputsignal-handling capability under full agc conditions.
The operating characteristics of the amplifier shown
in Fig. 10 are as follows:
Power Gain
Agc Range
3-dB Bandwidth
Noise Figure
Power Dissipation -

QII

26 dB
70 dB
4.5 MHz
6.8 dB
7.7 mW

The response characteristic is shown in Fig. 11
0

~B

e

II

\

TI-ADC Produds No. 55X1322 or equiv,

Fig_ 9-5chematic diagram for a CA.301 B class B amplifier_

'\

/

T2-Chicago Standard Trans. Corp. No. TA-l0 or equiv.
Notel. Rl 11 removed when 12 and Ira ore added.
15

<6V

0

90

95

100

105

FREQUENCY-MHz

110

lie

Fig. II-Response characteristic of 100-MB. amplifier
of Fig. 10.

Ll

L.

=0.11100.17 pH

= 0.5

to 0.8 ~H

Fig. l0-5chematic diagram for a CA.301B 100-MB.
cascode amplifier.

197

Linear Integrated Circuits

D\lCIBLJD
Solid State

Application Note
ICAN-5299

Division

APPLICATION OF THE RCA-CA3019
INTEGRATED-CIRCUIT DIODE ARRAY
BY
G. E. THERIAULT AND R. G. TIPPING
The RCA-CA3019 integrated circuit diode array provides four diodes internally connected in a diode·quad
arrangement plus two individual diodes. Its applications
include gating, mixing, modulating, and detecting circuits.
The CA3019 features all·monolithic-silicon epitaxial
construction designed for operation at ambient temperatures from -55°C to 125°C. It is supplied in a IO-termiQal TO-S low silhouette package.
Because all the diodes are fabricated simultaneously on
a single silicon chip, they have nearly identical characteristics, and their parameters track each other with tempera-

ture variations as a result of their close proximity and the
good thermal conductivity of silicon. Consequently, the
CA3019 is panicularly useful in circuit configurations
which require either a balanced diode bridge or identical
diodes.
CIRCUIT CONFIGURATION AND OPERATING
CHARACTERISTICS

Fig. I shows the circuit diagram and terminal connections for the CA30l9. Diodes D) through D. are internally interconnected to form a diode quad, while diodes
D5 and DR are available as independent diodes. Each
diode is formed from a transistor by connection of the .
collector and the base to form the diode anode and use

SUBSTRATE,

C(f)

Fig. l--Schematic diagram and terminal connections for the
CA3019 integrated-circuit diode array.

of the emitter for the diode cathode (this technique is one
of five methods by which the transistor structure can be
utilized as a diode). This diode configuration, in which the
collector-base junction is shorted, is the most useful connection for a high-speed diode because it has the lowest
storage time. The oniy charge stored is that in the base.
This configuration also exhibits the lowest forward voltage
drop, and is the only one which has no p-n-p transistor
action to the substrate. The diode has the emitter-ta-base
reverse breakdown voltage characteristic (typically 6 volts).
The monolithic process produces a substrate diode between the collector of a transistor. and its supporting substrate, as shown in Fig. 2. Connected at eacb diode anode,

-3-70

198

ICAN-5299
therefore_ is the cathode of a substrate diode for which
the anode is the substrate (terminal 7). In some applications, the substrate can be left floating because a forward
bias on any substrate diode creates a self reverse-bias on
the other substrate diodes. However, the uncertainty of this

bias and the capacitive feed through paths provided by the
substrate make it advisable to apply a reverse bias to all
substrate diodes by returning the substrate through terminal 7 to a de vollage which is morc negative than the
most negative voltage on a diode anode. Such reverse bias
is most important when ac circuit balance is essential because the capacitance of the substrate diodes is a nonlinear function of the voltage across them. In such circuits,
Ihe changing capacitance of these parasitic elements can
make good balance over a wide dynamic range impossible.
Fig. J-Typ;ca/ synthesizer mixer circuit.

~

Shorting of terminals 5 and 8 provides two independent
sets of back-to-back diodes useful for limiting and clipping, as shown in Fig. 4.

) I
(b) Diode equivalent circuit
(a) Croll section of monorilhie diode structure

Fig.2-Diagram and equivalent circuit

0/ the monolithic array.

Reverse bias of the substrate diodes is always indicated,
therefore. and should be omitted only if the inclusion of
such bias is not possible or practical. Terminal 7 may be
returned to a negative power supply as long as the com-

bined value of that supply voltage and the maximum
positive voltage on any diode anode does not exceed the
maximum rating of 25 volts. In systems that use single
power supplies. the active circuit may be raised above
ground potentiar and the signals coupled into the diodes
by capacitive or inductive means.

The operating characteristics of the ~A3019 integrated
diode array are determined primarily by the individual
diode characteristics, which are given in the technical

bulletin.

APPLICATIOMS
Although there are many possible applications for the
CA3019, this note describes a few practical circuits to
stimulate the thinking of the potential user. Besides the
obvious uses as separate diodes and possible quad combinations, some· of which are covered in the following discusssion, it should lie noted that shorting of terminals 2
and 6 in the quad effectively provides two diodes in series.
This diode connection can be used as the elements of
special balanced mixers, as ring modulators, and as com-

pensating networks that provide two diode drops. Fig. 3
shows an example of a typical synthesizer mixer circuit.

Fig. 4-Limiters using the CAJ019.

Balanced Modulator
Fig. 5 shows the use of the CA3019 as a balanced modulator which minimizes the carrier frequency from the
output by means of a symmetrical bridge network. A carrier of one polarity causes all the diodes to conduct, and
thus effectively short-circuits the signal source. A carrier
of the opposite polarity cuts off all the diodes and allows
signal current to flow to the load. If the four diodes are
identical, the bridge is perfectly balanced and no carrier
current flows in the output load. Table I lists the characteristics of the balanced modulator.
High-Speed Gat.~
In high-speed gates, the gating signal often appears at
the output and causes the output signal to ride a "pedestal." A diode-quad bridge circuit can be used tn balance
out the undesired gating signal at the output and reduce
the pedestal to the extent that the bridge is balanced.

199

ICAN-5299 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
TABLE 1_ CHARACTERISTICS OF BALANCED MODULATOR OF FIG_5
Carrier Voltage
VRMS at
30 KHz

0_15

0.75

0.75

0.50

1.0

Signal Voltage
mVRMS at
2KHz

77

245

770

245

245

Output
Frequency
KHz

28 and 32"

Output

db

Voltage
mV
rms

Below

34

6.5

VB

Output

Voltage
mV
rms

115

db

Voltage
mV
rms

7

30

0.7

41

0.82

49

26 and 34

0.02

72

0.05

72+

24 and 36

0.03

69

0.49

22 and 38

0.001

72+

om

*' Double--Sideband,

Output

VB

Below

db
Below

Output
Voltage

VB

mV
rms

440

5

db
Below

Output
Voltage

VB

mV
rms

51

14

170

2.6

50

0.1

68

0.48

64

0.04

54

60

22

0.58

72+

1.4

55

.015

db
Below

VB

3.6

37

72+

0.07

71

52.5

0.6

53

72+

0.02

72+

Suppressed.carrier Output.

All other outputs are spurious signals.

f_
I"

1

Q

r---~-----"'--o"

••
Q

Tl -

a pedestal-free output. With a proper gating voltage (1 to
3 volts rms, 1 to 500 kHz), diodes D5 and DR conduct
during one half of each gating cycle and do not conduct
during the other half of the cycle. When diodes D5 and
011 are conducting, the diode bridge (D, through D.,) is
not conducting and the high diode back resistance prevents the input signal V. from appearing across the load
resistance R r3 when diodes D5 and Dn are not conducting.
the diode bridge conducts and the low diode forward resistance allows the input signal to appear across the load
resistance. Resistor R, may be adjusted to minimize the

Technitrol No. 8511660 or equiv,

Fig.5-Balanced modulator using the CA3019.

A diode-quad gate functions as a variable impedance
between a source and a load, and can be connected either
in series or in shunt with the load. The circuit configuration used depends on the input and output impedances
of the circuits to be gated. A series gate is used if the
source and load impedances are low compared to the diode
back resistance, and a shunt gate is used if the source and
load impedances are high compared to the diode forward

resistance.
Series Gate. Fig. 6 shows the use of the CA3019 as
a series gate in which the diode bridge, in series with the
load resistance, balances out the gating signal to provide

200

Tt -

Technitrol No. 8511666 or equiv,

Fig. 6-Series gate using the CA3019.

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ICAN-5299
gating vohagc present at the output. The substrate (ter~
minal 7) is connecled to Ihe .- 6-voll supply. Fig. 7 shows
the on-Io-off ratio of the series gate as a function of frequency.

r

·0
600n

Vs

~

ON

-1011----J-.1Jl-20-·

I---...

I-W-l-_......c~ __ -

--I--I~".--I--..j

--f-

.T
o -30~-­

---

;:

---!..4..j--J~-

---

;;l
~ -40~~..j-_+~+_-_l__/~-+-++----l--..j

l5

~

o -5011--+---l--+~+--..j7--/--I-+-W-.....jI---1

~

-60~1----+-+-I-+.,<"---+_-----'f_l___l_+_·--

--

-70
4

6

8 10

6

8 100

Tl- Technitrol No. 8511666 or equiv.

FREouENCY-MHz

Fig.7 -On-to-off ralio

fOT

a fWtCtion

the series gate of Fig.6

Fig.S -Shunt gate using the CA30J9.

tlb

of {requl!ncy.

Shunt Gate. Fig. 8 shows the use of the CA3019 as a
shunt gate in which Ihe diode bridge. in shunt with the load
resistance, balances out the gating signal to provide a
pedestal-free OUlpu\. When the gating voltage V, is of
sufficient amplitude. the diode bridge (D 1 through D.)
conducts during one half of each gating cycle and does not
conduct during the other half of the cycle. When the diode
bridge is conducting, its low diode forward resistance
shunts the load resistance RL and prevents the input signal
V. from appearing at the output; when the diode bridge
is not conducting, its high diode back resistance allows the
input signal to appear at the oulput. Diode Ds and resistor Rl keep the transformer load nearly constant during
both halves of the gating cycle. The substrate (terminal 7)
can either be left floating or returned to a negative voltage, but it cannot be returned to ground. The characteristics of the shunt gate are as follows:

Gating frequency (f,) Gating voltage (V.) Signal frequency (f.) Signal voltage (V,) -

1 to 100kHz
0.8 to 1.2 Vrms
dc to SOO kHz (2 dB down)
0 to 1 Vrms

The frequency range of this circuit ·can be extended by
application of a reverse bias to the substrate. The amount
of gating voltage V. present at the output as a function
of the amplitude and frequency of V. is shown in
Table II.

TABLE 11_ GATING CHARACTERISTICS OF
SHUNT GATE SHOWN IN FIG_8
Frequency

of V.

-.!:!!L..

Amplitude
of V.
volts

Present at the
Amount 0/ V g

Output
mvs

0.8

0.2

1.0

0.5

1.2

1.3

0.8

2.0

10

1.0

4.7

10

1.2

8.7

SO

0.8

11.0

10

SO

1.0

24.0

SO

1.2

40.0

Series-Shunt Gate.
A series-shunt gate which utilizes all six diodes of the
CA3019 is shown in Fig. 9 This configuration combines
the good on-to-off impedance ratio of the shunt gate with
the low-output pedestal of the series gate.
On the gating half-cycle during which the voltage at A
is positive with respect to the voltage at B, there is no
output because the shunt diodes are forward-biased and

201

ICAN-5299 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
the series diodes are reverse-biased. Any signal passing
througb the input diodes (D4 and D 2 ) encounters a low
shunt impedance to ground (05 and Do) and a high
impedance in series with the signal path to the load (0.
and D 1 ). This arrangement assures a good on-to-off impedance ratio. When the voltages at A and B reverse, the
conduction states of the shunt and series diodes reverse,
and the signal passes througb the gate to the load resistor
R L • Any pedestal at the output is a fUnction of the resistor,
transformer, and diode balance.

signal and a 55-MHz oscillator signal is shown in Fig. 11.
The input impedance at point A is approximately 600-0hms
for a O.6-volt-rms oscillator drive.

o

D.2

OSCILLATOR AMl'UTUOE-_

0-4

0.8

O.

1.0

frf"45 MHz

ta..""MHz

'If-IO MHz

D

1/

0

r---...... r-.

/
t

Vo

I

M
t

Fig.ll -Conversion gain as a function of oscillator amplitude
lor the balanced mixer 01 Fig.10.

~I

The CA3019 mixer shown in Fig. 12 is essentially a
balanced mixer with two additional diodes (D. and D.)
added to form a half-wave carrier switch. The additional
diodes permit both legs of the circuit (D 1 - D. and
D3 - D.) to function throughout the ac cycle. As compared with a conventional balanced mixer, shown in FiglO,
this circuit effectively doubles the desired output voltage

oo

n

-=-

Vg

-=-

Fig.9 -Series-shunt gate using the CA3019.

The gate continues to operate successfully with resistors
Rl and R2 shorted if the transformer center tap is removed
from ground. In either case, no dc supply is required to
bias the gate diodes.

Balanced Mixe.
Fig. 10 illustrates the use of the CA3019 as a conventional balanced mixer. The load resistor across the output
tuned circuit is selected to provide maximum power output. The conversion gain of the mixer for a 45-MHz input

Fig.I2-Balanced mixer with
using the CA3019.

half~wave

carrier switch

and reduces the output voltage at the oscillator frequency
by half. However, the capacitances associated with the
integrated diodes prevent this circuit configuration from
realizing the improvement in conversion gain at frequencies above 20 MHz.
1:9; '-~--1>-(':5.

..

RL
15
7-45
pF

Fig.l0-Ba'anced mixer using the CA3019.

202

Ring Modulator
The use of the CA3019 as a ring modulator is shown in
Fig. 13. If a perfectly balanced arrangement were used,
carrier current of equal maguitude and opposite direction
would flow in each half of the center-tapped transformer
T 2. Thus, the effect of the carrier current in transformer
T. would be cancelled, and the carrier frequency would
n~t appear in the output. However, the ring modulator
of Fig. 13 is not exactly balanced because diodes
(D 1 +.D2) and (D3 + D.) are actually two diodes in

ICAN-5299
parallel, while diodes (D.) and (00) are individual diodes.
Nevertheless, this circuit attenuates the carrier in the output as well as an arrangement that uses both individual
diodes in two CA3019 circuits.
As the carrier passes through half of its cycle, diodes
(D 1 + D.) and (Do) conduct, and diodes (D3 + D.) and
(OS) do not conduct. When the carrier passes through the
other half of its cycle, the previously nonconducting diodes
conduct, and vice versa. As a result, the output amplitude,
is alternately switched from plus to minus at the carrier
frequency. The signal-frequency component of the output
waveform is thus symmetrical about the zero axis and is
not present in the output. Therefore, the ring modulator
suppresses both the carrier frequency and the signal frequency so that the output theoretically contains only the
upper and lower sidebands. For single-sideband transmission, one of these sidebands can be eliminated by selective
filtering. The performance of the CA3019 as a ring modulator is shown in Table III.

TI
1:2

Vc (CARRIER)
30 hHr

I

Fig.13 -Ring modulator using til. CA3019.

TABLE 111_ PERFORMANCE CHARACTERISTICS OF
RING MODULATION OF FIG_13
For a given V8
Output
Freq_ KHz

28 or 32

300

3S0

4S0

SOO

Vc mvs

600

SOO

3S0

300

Upper or
Lower
Sidebands

86

97

83

91

0.042

0.02

O.Q1S

0.020

Sig.
Freq.

30

Carrier
Freq.

26 or 34

Vgy eo in millivolts

Va mvs

2

24 or 36

+

Higher
Order
Sidebands

1.3 (-37db)

0.88 (-41db)

0.67 (-42db)

0.62 (-43db)

0.Q18

0.016

0.036

0.043

0.021

0.OS4

0.047

5.0

• db below the desired upper and lower sidebands

203

ODJ]3LJD
Solid State

Division

Linear Integrated Circuits
Application Note
ICAN-5337

Application of the RCA-CA3028A and CA3028B
Integrated-Circuit'RF Amplifiers
in the HF and VHF Ranges
by
H.C. KIEHN
The CA3028A and CA3028B monolithic-silicon integrated circuits are single-stage dffferential amplifiers.
Each circuit also contains a constant-current transistor
and suitable biasing resistors. The circuits are p-imarily
intended for service in communications systems operating
at frequencies up to 100 MHz with single power supplies.
This Note provides technical data and recommended
circuits for use of the CA3028A and CA3028B in the
following applications:
• RF Amplifier
• Autodyne Converter
• IF Amplifier
.. Limitei
In addition to the applications listed above, the
CA3028A and CA3028B are suitable for use in a wide
range of applications in dc, audio, and pulse amplifier service; they have heen used as sense amplifiers,
preamplifiers for low-level transducers, and dc ditTerential amplifiers. The CA3028B, which features tight
control of operating current, input offset voltage, and

input bias and offset current, is recommended for those
applications in which balance and operating conditions
are important.
Useful information concerning operation of the
CA3028A and CA3028B in mixers, oscillators, balanced
modulators, and similar circuits may be found in ICAN5022, "Application of the RCA CA3004, CA3005, and
CA3006 Integrated-Circuit RF Amplifiers." Biasing
considerations for the CA3028A and CA3028B differ
from the types discussed in ICAN-5022; however, dynamic performance is quite similar to that of the CA3005
and CA3006. ICAN-5022 contains circuits that illustrate operation from dual supplies which, when available,
can simplify tb.e hiasing of the CA3028J\ or CJ'.3028B.
Both the CA3028A and CA3028B are supplied in an
8-terminlll TQ..5 package which assures miuimum interlead capacitance and consequently excellent stability
in high-frequency circuits. The spacing of the leads on
the hermetically sealed package permits installation of
the integrated circuits on printed circuit boards by wavesoldering techniques.

11·73

204

____________________________________________________________ ICAN-5337
Circuit Description

The circuit diagram and terminal connections for
the CA3028A and CA3028B are shown in Fig.I. The
circuit is basically a single-stage differential amplifier
composed of transistors Ql and Q2 driven from a constant-current source Q3' A single-ended input may be
connected to terminal 1 or terminal 5, or push-pull inputs to terminals 1 and 5. Each of these terminals must
be provided with a biasing network. Care must be taken
to insure that the bias voltages on terminals 1 and 5
are nearly equal when balanced operation is desired.
This can only be achieved in practice by using a single
voltage divider as shown in Fig.2(a). Bias is first
established on the base of one transistor, in this case
Ql' through terminal 1. The base of the second transistor, Q2 in Fig.2(a), is then connected to the first
through a low-valued dc impedance. In Fig.2(a), the inductive winding of the input transformer provides the

Fig.l - Schematic diagram and terminal connections for
the CA3028A and CA30288 integrated circuits.

~OUT
osc.

FREQ.

+Vcc

Id)
2R

+Vcc
+Vcc

RFC
CA302BA
OR
CA30288

+Vcc
2R

C,
tel

(tl

Fig.2 • Connections for the CA3028A and CA30288 for use as (a) a balanced differential amplifier with a controlled
consfont-current-source drive and age capability; (b) a cascocle amplifier with a constant-impedance age capability;

(c) a cascade amplifier with conventional ago. capability; (d) a converter; (e) a mixer; (f) an oscillator.

205

ICAN-5337

low-resistance path_ An rf choke or low-valued resistor
may be used in place of transformer coupling, but
caution must be exercised because even as little as 100
ohms may cause serious unbalance in 80me applications.
A single-ended output may be taken from terminal 6 or
terminal 8, or push-pull outputs from terminals 6 and 8.
In systems with a single power supply of up to 12 volts,
terminal 7 is connected to the highest positive potential
for maximum gain. Other operating points can be selected by application of a varying bias voltage (agc) to Q3'
The circuit diagrams in Fig.2 illustrate the flexibility of the CA3028A and CA3028B. Terminal connections are shown for a differential amplifier driven from
a controlled constant-current source that has agc capability; a cascale amplifier with constant-impedance or
conventional agc capability; a converter; a mixer; and
an oscillator. The cascale mode of operation is recommended for applications that require higher gain. The

0.4

I
1

COLLECTOR CIJRRENT OF EACH TRANSISTOR= 2.2 mA

'12.°12 + Ib'2

...}

.

•0

-

~

:::::

-;?

~

i

differential male is preferred when goal limiting is
required_
Operating Modes

The CA3028A and CA3028B integrated-circuit rf
amplifiers can be operated in either the differential mode
or the cascode mode. Applications using the differential
mode are distinguished by bigh input impedance, good
gain-control characteristics, large input-signal-handling
capability, and good limiting.
For ease of design. of systems using the CA3028A
and CA3028B, admittance or "y" parameters are shown
in Fig.3 for tbe differential male and in Fig.4 for the
cascode mode. It should be noted that tbe y parameters
of the more complex differential .fud ~ascode amplifier
stages differ from those of simple common-emitter transistor stages.

40

-........

~

I

20

8

/V'2

:!i

b,. ....

.0

..

N
0

!i

~

~

-20

"

.00
FREQUENCY-MHz

l•

COLLECTOR CURRENT OF EACH TRANSISTOR=2.2 mA

'22.°22 + jb22

1

.~22

~

l!

~
~

0.5 :;

'i
0.4

•

l~

0.3 ~

~

13

0.2 ~
0.'

0

:/

"

.

0.'
0

.0

6

FREQUENCY-MHz

.0

-"\'\

./

"
FREQUENCY-MHz

. "
'00·

COLLECTOR CURRENT OF EACH TRANSISTOR= 2.2 mA

'/

2

8

~

/f

...

13

i

•• y flO

/

:!i

5
~

/

5

0 .5

~
0

--- --

~

-

'/

,,/

6

8'00

B 10

FREQUENCY-MHz

Fig.J - Y parameters 01 tloe CAJ028A anJ CAJ0288 in
tloe Jillerential-omplilier connection.

206

>-

§

If

~~

.

.'"

'II· 011 +jbll

J,.

0."

•• .."

-

e

~

""J

-92~

~

2.'

~

~

.0

COLLECTOR CURRENT OF
EACH TRANSISTOR == 2.2 mA
'21- 921 + ib21

ICAN-5337
2.5

/

STAGE COLLECTOR CURRENT ~ 4.5 mA

'11-°11+ Ib ll

/j

- .

E
E
I

Vo"

t....

..

,

100

10
FREQUENCY-MHz

"2.

112 ~ 912 + jblZ

~ 0.20

--

§

II

~
:.:

"
b..

~-~

~

0.15

I!j

I=-

lL- "

I

,-

-100

100

FREQUENCY-MHz

l-'

•

iE

1

;

STAGE COLLECTOR CURRENT=4.SmA

w!!
10

e~

~~

"8

I

//

a:

~
~

II

~-!:!!

0

) /1

;

L-10

~

~

121 - aZI + lb ZI

+\

/'

.

60

I

/
40

0

z
;!

..

,/
20

~

iil

1\

-b.,' I

...

b ,•

5

STME COLLECTOR CURRENT- 4.5

80

...l;1

I!

15

.. I
~ ~

100

10

'12.912 + Ib l2

..

~

L--+--l-~~-I--_+--+--+-+.J -'20

FREQUENCY -MHz

1iE

-60

....

I

'0

e

1/
/-bl.~I

13

o

~

'\- -40 ~

1---1---+--+-++----1--1-+-+-+-+- 80
l-/

~----~-H1'"

~

~

\1-

z 1.0
+--_+--'~--+-+4---4--~_+~H

"I.

z

0

-.......,,, /

10

w
o

II::

.0

+-_~~~~-.O

0

STAGt COLLECTOR CURRENT=2.5~

"-

____

40
II

f--

~w

d .•

~

1

4.5mA

--TI-----

I..

Oil

0.25

~

Yzz- lJ zz+jb22
2.0 ~---.

/

b" /
2

V

STAGE COLLECTOR CURRENT

0

--

~k

4

FREQUENCY-MHz

6

8
10

•

8

100

FREQUENCY-MHz

Fig.4 - Y parameters of the CA3028A and CA30288 in
the c:ascoJe connection.

For quick reference, values for input and output parallel
RC networks and transconductance values are listed in
Table I for the differential amplifier and in Table II for
the cascode amplifier.
Although the reverse transfer admittance Y12 of the
CA3028A !r CA30288 is low for either cas code or dif-

ferential operation,circuit-layout-induced instability can
occur in high-gain amplifiers. Circuit layout is of
paramount importance in both modes because undesirable
coupling admittances can be much greater than the
CA3028A or CA30288 admittances. Attention to layout
and shielding is imperative if proper advantage is to be
taken of the low feedback of the CA3028A and CA30288.

207

ICAN-~37

_________________________________________________________

Table I Input and Output Parallel RC Network Component Values,
Transconductance Values, and Performance Data for the
CA3028A and CA3028B Integrated Circuits in the Differentia) Amp) ififr.
Frequency
(MHz)
10.7
100

Input Parallel
RC Network
Rln
(ohms)

Output Parallel
RC Network

Transconductance

Cln
(pF)

Raut
(ohms)

11m
(millimhos)

4.5

2.2 x 1()4
1.8 x J()3

1800
500

c.ut
(pF)

Frequency

(MHz)

Input Parallel
RC Network
Rln
(ohms)

Cin
(pF)

Output Parallel
RC Network
Rout
(ohms)

Cout
(pF)

,v..<§'#'
7

I.

5(/

Y

0.02

1)

900
170

22
6.3

-1.67 x 1!1i
-5 x lOS

3.1
3.5

30

100
14

!'"

10

~

0

~
~

Differential Amplifier

When linear operation over a wide input-voltage
range is imperative, age voltage may be applied to the
constant-current source Q3 at terminal 7. Gain-control

208

DIFFERENTIAL-AMPLIFIER CONFIGURATION
AMBIENT TEMPERATURE (TA)-ZS·C
FREQUENCY (f)-IO.1 MHz

0.04

40

11m
(mil Ii mhos)

The transfer characteristic in Fig.5(a) shows the
excellent limiting capabilities of the CA3028A and
CA3028B differential amplifiers. This limiting performance is achieved because the constant-current
transistor Q3 limits the circuit operating current so
that the collectors of the differential-pair transistors
Ql and Q2 du Hot saturate. ··-Table III shows the maximum permissible load resistances for non-saturating
operation when single supply voltages of 9 and 12
volts are used.

+9- i=-

0.06

0.1

0.08

I

I

012

I
0.4

INPUT VOLTS (Win)

Transconductance

The differential amplifier shown in Fig.2(a) is
designed for operation at 10.7 MHz and 100 MHz. Because the amplifier consists essentially of a commoncollector stage driving a common-base stage, the input
admittance Yll, the output admittance Y22, and the
forward transfer admittance Y21 are decreased by a
factor of two. The reverse transfer admittance Y12 is
typically 140 times lower than that of a single commonemitter transistor at 10.7 MHz, and 10 times lower at
100 MHz. As a result, tbe CA3028A and CA3028B can
be aligned easily in if strips without need for neutralization.

f-

V

/

I

20

10.7
100

-

~"

5

35
15

Input and Output Parallel RC Network Component Values,
Transconductance Values, and Performance Data for the
CA3028A and CA3028B Integrated Circuit Cascade
Amplifier.

-p::;<"'~

2

o

Table II

t ~I~

5

2.

VCC ·+9V

'---

~

f\

~~~\
~ ..~\~
\

-10

-20

~

-30

o

DC BIAS VOLTAGE ON TERMINAL 7 - V

20

p~l~

I.

Vcc·+9V

~

12

"'-

\

NOISE FIGURE

o

FREQUENCY -100 MHz

,

Y\

J

9
POSITIVE DC BIAS VOLTAGE ON TERMINAL 7-V

Fig.S - Characteristics 01 the CA3028A and CA3028B in
the dillerentia/-amplilier connection: (a) IO.7-MHz
transler characteristics; (b) agc capabilities;
(c) power gain as a lunction 01 noise ligure.

_________________________________________________________ ICAN-5337
Table III Maximum Load Resistance Permissible for Non-Saturating
Operation with t9 and tl2 volt Single-Supply Voltages

CASCODE CONFIGURATION
AMBIENT TEMPERATURE (TA)::2S-C
FREQUENCY (1)-10.7 MHz

5

VCC

ICI t IC2

Maximum
Tuned Load

Maximum
Resistive Load

(volts)

(milliamperes)

(ohms)

(ohms)

-t9

5.0

+12

6.8

3.6 K
3.5 K

1.8 K
1.7 K

RL =VCclICI + IC2 Resistive Load
RL =2 VCC/ICI + IC2 Tuned Load

capabilities are -60 dB at 10.7 MHz and -46 dB at
100 MHz, as shown in Fig.5(b). Fig.5(c) shows curves
of power gain and noise figure as a function of agc
voltage. The combination of an optimum noise figure
of·5.5dB and.a power gain of 15 dB at 100 MHz makes
this circuit suitable for use as an rf amplifier in the
commercial FM band.
Cascode Amplifier

When the CA3028A or CA3028B is used in the
cascode configurationforrf-amplifier circuits, a commonemitter stage drives a common-base stage. The input
admittance Yll is essentially that of a common-emitter
stage, and the forward transfer admittance Y21 is that of
a common-emitter stage times the common-base alpha.
Because of the high-impedance drive source for the common-base stage, the output admittance Y22 is quite low
at low frequencies <0.6 J.Lmho). The reverse transfer
admittance Y12 for the cascode circuit is 900 times less
than that for a single-stage common-emitter at 10.7
MHz, and 35 times les~ at 100 MHz. As in the differential amplifier, ease in tuning is obtained without need
for neutralization.
The transfer characteristic in Fig.6 shows the
suitability of the cascode configuration for agc take-off
for FM front-end controls.
Applications

The typical applications descrihed below illustrate
the use of the CA3028A and CA3028B integrated-circuit
rf amplifiers in both the differential and the cascode
modes.
10.7-MHz Cascode IF Amplifier. Fig.7 shows an
FM if strip in which the CA3028A or CA3028B is used
in a high-gain, high-performance cascode configuration
in conjunction with a CA3012 integrated-circuit wideband amplifier. The CA3012 is used in the last stage
because of the high gain of 74 dB input to the4000·ohmload ratio-detector transformer T4' An input of approximately 400 ,microvolts is required at the base of the

_~

C'TOR SUPPLY VOL.TSIVCC)·+12

c~

.,/

+0

~~

3

V

2

,/
/

o

Q02

0.04

006
O.OB
0.1
INPUT VOL1S I vin)

0.12

0.14

Fig.6 - lO.7-MHz transfer characteristics of the CA3028A
and CA3028B in the cascoc/e connection.

CA3012 for -3 dB below full limiting. An impedancetransfer device and filter must be connected between the
CA3012 base (terminal!) and the output of the CA3028A
or CA3028B (terminal 6). The insertion loss of this
filter should be kept near 6 dB <1:2 ratio ofloaded to
unloaded Q) so that all possible gain can be realized up
to the CA3012 base. In addition to this insertion loss,
a voltage step-down loss of 5.8 dB in the interstage
filter is unavoidable. Therefore, the total voltage loss
is approximately 9 to 14 dB, and an output of 1500 to
2000 microvolts mns t be available from the CA3028A or
CA3028B to provide the required 400-microvolt input
to the CA3012.
The voltage gain of the CA3028A or CA3028B into
a 3000-0hm load is determined as follows:

va

-Y21
100 x 10-3
=----300 =49 dB
Y22 + YL 0.33 x 10-3

, This calculation indicated a sensitivity of 6.6 microvolts
at the, CA3028A or CA3028B base (terminal 2). This
value cannot be realized, however, because the CA3012
limits on noise peaks so that the gain figure is reduced.
A sensitivity of 7.5 microvolts was realized in the
design shown in Fig.7. The filter approach with highgain integrated-circuit chips differs from that for single,
cascaded transistor stages in that lumped selectivity
is required rather than distributed selectivity.
Special care must be exercised when second-channel attenuation in the order of 45 dB is required.
Selectivity is then proportioned as follows:
Interstage filter: double-tuned 220 kHz at -3 dB;
coefficient of critical coupling, 0.7; voltage
loss, 8 dB

I

209

ICAN-5337 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Converter filter: triple-tuned, 220 kHz at -3 dB;
coefficient of critical coupling, 0.8; voltage
loss, about 28 dB
Because of input limiting in the CA3012, the inter stage
filter exhibits a somewhat wider bandwidth than the
220 kHz indicated. Therefore, a coefficient of critical
coupling near 0.8 is realized, which is optimum for
minimum deviation from constant time delay. The
triple-tuned converter filter alone provides secondchannel attenuation of 30 to 33 dB, while the interstage

lO.7-MHz IF Strip Using Two CA3028A or CA3028B
Circuits. The 10.7-MHz if strip shown in Fig.8 uses
two CA3028A or CA3028B integrated circuits to provide .
less over-all gain than the circuit of Fig.7. The first
integrated circuit is connected as a cascode amplifier
and yields voltage gain of 50 dB; the second integrated
circuit is connected as a differential amplifier and
yields voltage gain of 42 dB.
When a practical interstage transformer having a .
voltage insertion loss of 9 dB is used, over-all gain is

.a.

.50
47

4.7 K

o.oat
~F

'0'

82

1.5K

550 p F

6.81(
5,..F

350,F

7.S,.V

_

6.8K

2Y, ••

=400"V

Ta: lnterstage transformer TRW #22486 or equiv.

T4: Ratio detector TRW #22516 or equiv.
Audio Output: 155 rnV rrns for 7.5 Jl.V ± 75 kHz input 3 dB
below knee of transfer characteristic.

Fig.7 - IO.7-MHz if amplifier using a CA3028A or CA3028B in the cascode mode.

filter contributes 8 to 10 dB. The filters described meet
requirements of both performance and economy.
The large collector swing that clln he nbt.ained in
cascode operation of the CA3028A or CA3028B makes
it desirable to take the age voltage from the collector or
"hot" end of the if transformer for front-end gain control
The case ode stage then operates primarily in its linear
region, and excellent selectivity (40 dB) is maintained
even for large signal inputs of approximately 0.4 volt.
Front-end gain reduction is between 40 and 50 dB.

210

83 dB and the sensitivity at the base of the first integrated circuit is 140 microvolts. A less sophisticated
converter filter (double-tuned) could be employed at the
expense of about 26 dB of second-ch8J.nel attenuation.
If the voltage insertion loss of the converter filter is
assumed to be 18 dB and the front-end voltage gain
(antenna to mixer collector) is 50 dB, this receiver
would have an IHFM* sensitivity of approximately
8 microvolts.

* Institute of High-Fidelity Manufacturers.

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - - - - - - - - - - - - I C A N · 5 3 3 7

.0.

,-

0.001

Ison

4.7K

10K

1500.0

330 pF

S.BK

330 pF

6.8 K

T,

',-

I.

140"V

44.SrnV

IS.8mV

zv,"',

T3: Interstage transformer TRW #22486 or equiv.
T4: Ratio detector TRW #22516 or equiv.
Audio Output: 155 mV rms for 140 JJ.V ± 75 kHz input 3 dB
below knee of transfer characteristic.

Fig.8· IO.7·MHz i( strip using two CA3028A or CA30288 integrated circuits.

10.7·MHz Differential.Amplifier IF Strip. Fig.9
shows a 10.7·MHz medium-gain if strip consisting of a
CA3028A or CA3028B connected as a differential amplifier and a CA3012 wide-band amplifier. As in the circuit shown in Fig.7, an input of approximately 1500
microvolts is required to the interstage filter. The
differential-mode voltage gain of the CA3028A or
CA3028B into a 30OG-ohm load is determined as follows:
-Y21

35 x 10-3

VG=--- 0.38 x 10-3 = 92.5 = 39.3 dB
Y22 + YL
This voltage gain requires that an input of approximately 15 microvolts be available at the base of the
CA3028A or CA3028B differential amplifier.
Even if a triple-tuned filter having a voltage insertion loss of 28 dB is used in a low-gain front end. a
receiver having an IHFM sensitivity of 5 microvolts
results. If 26 dB second-channel attenuation is per-

missible. a 3-microvolt-sensitivity IHFM receiver can
be realized.
88·MHz-to.l08·MHz FM Front End. Fig.lO illustrates
the use of the CA3028A or CA3028B as an rf amplifier
and a converter in an 88-to-108-MHz FM front end. For
best noise performance. the differential mode is used and
the base of the constant-current source Q3 is biased for
a power gain of 15 dB. The rf amplifier input circuit
is adjusted for an insertion loss of 2 dB to keep the
noise figure of the front end low. Because the insertion loss of the input transformer adds directly to the
integrated-circuit noise figure of 5.5 dB. the noise
figure for the front end alone is 7.5 dB. as compared
to noise figures of about 6 dB for commercial FM tuners.
Although a single-tuned circuit is shown between
the collector of the rf-amplifier stage and the base of
the converter stage. a double-tuned circuit is preferred
to reduce spurious response of the converter. If the
double-tuned circuit is critically coupled for the same
3-dB bandwidth as the single-tuned circuit. the insertion loss remains the same.

211

7

3

~

·

N

A

C

I

_________________________________________________________

68K
150.0

I.

4.7K

1

O.ool,..F

OUTPUT

r

10K

B2

I.S:,
6.8k
5.F

u.

I.

4OOl&V

Ta: Interstage transformer TRW #22486 or equiv.
T4: Ratio detector TRW #22516 or equiv.
Audio output: 155 mV rmB for 15 p.V ± 75 kHz input 3 dB
below knee of transfer characteristic.

Fig.9· 10.7·MHz if strip using a CA3028A or CA3028B in the dillerential made.

The collector of the rf stage is tapped. down on
the interstage coil at approximately 1500 ohms, and
the base of the converter stage at 150 ohms. RF voltage gain is computed as follows:
Antenna to base . . . . . . . .
Base to collector. . . . . • . .
Voltage insertion loss of
interstage coil . . . . . . .
Net rf voltage· gain . . . . . . .

. o dB
. 22 dB
. -13 dB
. 9 dB

If an if converter transformer having an impedance
of 10,000 ohms is used, the calculated voltage conversion gain is
. VG c

=~

= "12 =41.3 dB

Y22 + YL

Measured gain into the collector of the converter is
42 dB. The measured voltage gain of the rf amplifier

212

and converter into a 10,OOQ-oilm load is 52 dB; calculated gain is 50 dB. When the converter is tuned for
the commercial FM band (SS to lOS MHz), the following
parameters apply:
Input resistance Rin ••....... 170 ohms
Input capacitance Cin .....••• 6.3
pF
Output resistance Rout••.•.... SOK ohms
Output capacitance Couto •...
pF
3.5
Conversion transconductance •.•. 13 mmhos
The rf amplifier and converter shown in Fig.10
were combined with lh~ if amplifier shown in Fig.7
t

and the following performance data were measured at
100 MHz:
3(k\B (S + N)/N lHFM Sensitivity .•• 3 j.LV
Image Rejection . . . . . . . . . . . . • . . 46 dB
Receiver noise figure is the limiting factor that permits
a sensitivity of only 3 microvolts to be realized.

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ICAN-5337

---T3~ f-t--ll-~

.J

2K

1.2 K

-13d8

41
L.4".

I.

t!50dB

150

:I~·-

Ll: 3-3/4 T #18 tinned copper wire; winding length 5/16 11 on 9/32" form; tapped
at 1-3/4 T; primary - 2 turns #30 SE.
L2: 3-3/4 T #18 tinned copper wire; winding length 5/16" on 9/32" form; tapped
.t 6 2-114 T, A 3/4 T.
C Vl _2 : variable.6 C ~ 15 pF
T 1: Mixer transformer TRW #22484 or equiv.
T2: Input transformer TRW #22485 or equiv.
La: 3-1/2 T #18 tinned copper wire; winding length 5/16" on 9/32" form.
C V1 _a: variable. L}. C ~ 15 pF.

Fig. 10 - 88-MHz-to-l08-MHz FM 'ront end.

213

OOCTI3LJD

Linear Integrated Circuits

Solid State

Application Note
leAN-S338

Division

Application of the RCA
CA3021, CA3022, and CA3023
Integrated-Circuit Wideband Amplifiers
BY
G.E. THERIAULT, T. H. CAMPBELL, ANDA. J. LEIDICH
The RCA-CA302l, CA3022, and CA3023
integrated circuits are multi-purpose

hjgh-gain amplifiers designed for use in
video and AM or FM if stages in singlepower-s'upply systems. These circuits
feature monolithic-silicon construction,

and are usable throughout the temperature
range from -SSoC to 12S o C.
They are
supplied in a 12-terminal TO-S package.
The CA3021, CA3022, and CA3023 have
the same circuit configuration and the
same mid-band open-loop gain. However,
different resistor values are used in the
three circuits to provide different values
of power dissipation and open-loop bandwidth. Typical power dissipation with a
6-vo1t supply is 3 mil1iwatts for the
CA3021 , 12 mil1iwatts for the CA3022, and
36 mi11iwatts for the CA3023. Wider bandwidths can be achieved with the CA3023,
intermediate bandwidths wi·th the CA3022,
and narrower bandwidths with the CA3021.

The major feature of these circuits
is a flexibility that permits their use in
the following applications: video amplifiers operating at frequencies through
30 MHz, AM and FM if amplifiers, and
buffer amplifiers in which an isolation
capability greater than 60 dB at 1 MHz is
desired. Theareas of circuit flexibility
are as follows:
• Operation with dc supplies of 4.5
to 12 volts.
• Automatic-gain-contro1 capability
(60-dB agc range with large input-signa1handling capability).
• Limiting capability (by connection
of diodes provided on the chip).
• Gain adjustment (by addition of externa1 feedback resistor or network to
obtain desired operating gain and bandwidth) .

8-67

214

ICAN-5338

Circuit Description

gain performance.

The circuit diagram for the CA3021,
CA3022, and CA3023 is shown in Fig.l.
Amplifier gain is obtained by use of
transistors Ql' Q3' Q4' and Q6' which are
connected astwo dc-coupledcommon-emitter/
common-collector amplifiers having avoltage gain of approximately 60 dB.
The

conditions are maintained by the bias
applied between the collector and the
base of QI by the resistor-diode network
R 2 , R 3 , R I , D1 • Because the collector of
QI is held at a fixed potential that is
relatively independent of supply, device

~

characteristics,

Linear operating

and temperature,

de

coupling to the remainder of the circuit
can be used.

D2

CHOKE

r:;')

.vee

Ca'

92CS-i4411S

Fig. 1 - Circui t di agram and 70-5 terminal connections
for the CA3021, CA3022, and CA3023 integrated
circuits.

common-collector configuration provides
the necessary impedance transformation
(high-impedance input and low-impedance
output) for wide bandwidth. The output
transistor Q6 provides the low output
impedance desired for iterative operation.
The circuit must be capacitively coupled,
and should have a low-impedance source.
A source resistance of 50 ohms was used
for thecircuit measurements given in this
Note.
Fig.2 shows typical connections for
the CA3021, CA3022, and CA3023 for wideband and bandpass applications with and
without age, and for limiter applications.
An external feedback resistor R f or a
tuned circuit can be added between terminals 3 and 7 for desired bandwidth and

Co,

C,'
Fig.2 - Typical connections for the 00021, CA3022,
and CA3023 for (a) wideband and bandpass applications, (b) wideband and bandpass applications
requiring age, and (e) limiter applications.

215

ICAN-533B _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _, - - - _

For applications inwhich gain control
is desired, terminals 10 and 12 are left
floating and agc isapplied to terminal 2,
as shown in Fig.2b.
For maximum gain,
terminal 2is operated at a positive voltage not larger than the supply voltage applied
to terminalS. In the positive voltage
condition, transistors Q2 and QS are
saturated and the impedance in the
emi tters of Q1 and Q4 -i slow. When the
gain-control voltage be.comes negative,
Q2 and QS come out of saturation and

provide high degenerative emitter resistance which reduces the gain.

Because

most of the increasing signals appear
across the increasing degenerative resistance, the active gain transistors

Ql' Q3' Q4' and Q6 handle only a small
part of the large signal. As a result,
signal-handling capability increases with
increasing age.

Further increases of

gain-control voltage reduce the current in

Q1 and Q4 and thus provide the additional
gain control needed to achieve maximum
age range.

In limiting applications, diodes D2
and D3 are connected in the feedback loops,
as shown in Fig.2c (terminals 4 to 3,
6 to 7, and 8 to 9). The diodes provide
clamping for sufficient input-signal
swing; limiting can_ be achieved with
input-signal swings up to 2.5 volts rms.

Operating Characteristics
DC Supply Considerations. The most
positive voltage to be applied to the
CA3021, CA3022, and CA3023 integrated
circuits is connected to terminal 5.

The most negative voltage is connected to
the substrate through terminal 11.
The circuits can be used with single
power supplies of 4.5 to 12 volts. The
bias technique used for transistor Ql'
and thus for the remainder of the circuit,
makes the collector operating voltage of
Q1 and Q4 relatively independent of the
supply. Consequently, the current in the
circuit increases almost linearly as a

function of supply voltage. Fig.3 shows
typical power dissipation for the three
circuits as a function of supply voltage.

Because there is
collector voltage
change in output
function of supply

216

little change in the
of Q4' there is little
operating point as a
voltage.

110
MO

11

~

if
J

V

/
20

/

......o
4

V

~

-

I;

V

8
•
ID
12
Sll'PLY VDLTME-V

M

Fig.3 -Power dissipation as a function of supply
voltage.

DC Stabi I ity with Temperature. The
output operating points of the CA3021,
CA3022, and CA3023 are shown in Fig.4 as
a function of temperature and feedback
resistance.
As a result of the resistor
values used in each circuit, the output

operating point is compensated in the
temperature range between -20 oC and 75 0 C
when the circuit is operated under openloop conditions (terminals 3 and 7
floating).
Insertion of a feedback resistor between terminals 3 and 7 is
recommended to minimize degradation in

performance at temperatures outside this
range. The maximum value of the feedback
resistor R f recommended for optimum performance of each circuit is shown in the

following table:
Circuit
Rf - ohms
CA3021
18000
CA3022
5100
CA3023
2000
Use of a feedback resistor of the maximum
value provides equal ac and dc feedback,
but reduces theusable gain of the circuit
to approximately 40 dB. When equal ac and dc
feedback is not desired, as in the case
of bandpass or tuned responses, a choke
or tuned circuit can be included between
the feedback terminals 3 and 7 to providede temperature stability and permit gains

of 50 to 55 dB.
As a general rule, feedback should be
included in all applications in which
operation over an extended temperature
range is required.

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ICAN-5338

..

by addition of feedback.
Variation of
operating point is caused by the added
collector-to-emitter voltage of Q2 and Qs

CASOZI

SUPPLY VOlTAGE-6V

.8

in saturation in the emitters of

"

Q4'

V

~

.6

..

/!EED ••CK REJ'STDR' ",(DAMsI::'
18000

5600

/

.S

ating point;

..........

100

and

ae feedback can be removed

by the use of tuned ci rcui ts.
mum recommended values of R f

/

."

01

The effect is more pronounced in the
higher-current circuits, CA3022 andCA3023.
As discussed previously, full dc feedback can be used to stabilize the oper-

mIOPEN-LOOP CONDITION)

The maxiprovide

satisfactory stability when the circuit
is connected for agc.

D
-75

~

'B

-50

-25

50
75
TEMPERATURE--C

100

25

125

DC Considerations for Limiting.
In
limiter applications, diodes 02 and 03
are included in the feedback loops in the

3.2 CA3022
SUPPLY VOLTAGE-6V

~2.8

J ..-r--'-.

~2A+-~---+--~~~t-~---+'~
"~--i

~

/

mIOPEtH.'r'

g 2.0.~

e

J. .L

,.J.,

FEEDBACK RESISTOR R f (OHM~
51001--

I.

10 1.6

COND~~

~ t:;br4r~~~i~80;0~:--~~~~~
--/f
-I--

!

..I

1.2

; 0.8

I

,-

"'

--

r-

560

g

shown in Fig. 2c). Under. open-loop conditions, the dc operating point may be
such that0 2 and0 3 (usually 03) are turned
on.
The gain is then reduced and the
amplifier will not operate linearly atlow
levels.
The values of Rf recommended
previously also assure correct operation

~ 0.41--I---+--+--1--+---+---j---i

!J

circuit (external connections are made as

for limiting amplifiers.

~~.~-.~O---.±.~~O--±••~~.O~~~~~,OO~~,~
TEMPERATURE-aC

AC Frequency Response and Gain Performance. Open-loop frequency responses
for the CA3021, CA3022, and CA3023 are
given in Fig.5. The curves also show the
response characteristics tothe 3-dB point

CAson

SUPPLY VOLTAGE- 6 V

.........

/'

I

.. (OPEN-LOOP
CONDITION)

for various values of feedback resistance.

'\

Values of feedback resistance larger than

\

FEEDE

those recommended fer operating7Point

temperature stability are included to

>C. RESISTOR R,(OHMSI· ~
1000

indicate gain performance at resonance
when tuned circuits or chokes are used

2000.

2

~~

'60

.a

~

."
0
-15

-50

-25

0

25

50

75

100

125

TEMPERATURE-·C

Fig.4 -Output operating point as a function of
temperature for various values of feedback
resistance.

DC Considerations for Gain Control.
When the agc transistors Q2 and QS are
included in the circuit, the output
operating point can be held constant only

in the feedback loop.

For these measure-

ments, the circuits were operated with a

50-ohm source and a high impedance load.
Fig.6 shows the variation of gain with
temperature for the three circuits. Each
circuit was operated with sufficient

feedback to provide a closed-loop gain of
approximately 40 dB. The gain variation
is practically independent of feedback,
and is slightly greater for the CA3023
than for the other two circuits.
Fig.?
shows typical upper-3-dB frequency shifts
with temperature for the three circuits

for a gain of approximatelY 40 dB.

217

ICAN-5338 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
0

...

360000

00

39000

,

22000

',-

,,

..ob
.,.... ,1

.t

TERMINALS 10,11, a 12 CONNECTEj
TE...ERATURE-21S-C
I

o-

i

:--Fi:::Ej"i'j

,

,

[,00'01
I
I
I III
~1:fi;:I~ CONJ.rED TO fIIIOUND

\

_~z
GROUND

10 _~"""C

POINT

1.0

OJ

,

FEEDBACK R£SlSTOR Rt (OHMSI-2200

0

. . .. . . ..

0

,

00

FEEDBACK RESISTOR Rt (OHMS)-IOOOO

-~YYOLTAGE.6Y

-..- ,

10

""-- ....

100000

~Ti'i"Fi"-··IOOlr I

o

IE

OJ

10

4..

1.0

60

ato -

r~

..

0100_

-.'

0

lit COHIIIS)-IOOO

III

4

••

10

,

. . ..

100

,

10

FEEDBACK RESISTOR

IE

FREQUENCY_11Hz

FREQUENCY-11Hz

,

...,

,
\

r-""lI023

~~~.all~ ~ TO GROUND

I

Or--!E~~a~SPONSE

. . .. . . .I . .

TfEEM"....f '-'+"T

o

10

OJ

'00

Fig.5 - Frequency-response characteristics.

.i
~
Ie

;z

100 SUPPLY VOLTAGE-' VOLTS
8
RMINALS to. II, AND 12

• CONNECTED TO GROUND

~='~~A~L::I~·~ I~
0

CONNECTED TO GROUND

I

2 ~ -CA.02.
0

-::--.t.

-

""""" ~ t---.

1i~ -2

CA302:2

!

j!

~ -4

-""- ---

-6

--

CA30Z1

o

--

~

TEMPERATURE--t

r'::

-

luO.

-"

I....

1--SO~-~O~-:!SO:=->--:I~OO::-+-:!,50

Fig.6 - Voltage-gain variation lDith temperature
(feedback adjusted to provide gain of approximately
40 dB at 25°C).

218

TEMPERATURE-·C

Fig.7 - Upper-3-dB frequency shift .lDith temperature.

_________________________________________________________

ICAN~338

In buffer-amplifier applications,
reverse feedback or isolation capability
is required. The following table shows

the isolation performance of the CA3021,
CA3022, and CA3023 at three frequency
levels with the input terminated in 50 ohms.

Feedback
Resistor
Rr(ohms)

Voltage Injected
at Output
(vo Its rms)

Resultant Feedthrough Input Voltage
Below theAppl ied Output Voltage
(dB)

IBOOO
5000
2000

2

66

66

54

2

66

66

66
66

54

2

Circuit

f

CA3021
CA3022
.CA3023

AC Signal Power Output.
power-output capability of
collector output transistor
occurs for a load-resistance
than the output impedance.

The maximum
the commonQ6 in Fig.l
value higher
For determi-

= I MHz

f

= 10

MHz

f

nals 3 and 7 of the CA3021, CA3022, or
CA3023, the gain at resonance is a function
of the equivalent resistance of the feedback loop. Gain characteristics of the
three circuits as a function of feedback
resistance are shown in Fig.9.

each circuit was operated from a 6-volt
supply at a gain of approximately 40 dB

circuit,

with a variable resistor capacitively

The variation of

maximum linear signal output as afunction

of load resistance is shown in Fig.B.

tloo~--~--.----r~~----r-~

i :r----j'<---t~~,

.
.

SUPPLY VOLTAGE. 6V
TERMINALS 10,11, AND 12 CC*NECT£D TO GROUND

1-" .....

V
zo~~7/
0

For each

there is a value of feedback

40

10

!

MHz

52

nation of optimum load-resistor values,

coupled to terminal B.

= 50

~~XI
1\

..

L-',v

V

1\ I

~/

YJoy'"
..-"'

/

. . .....

FEEDBAQ( RESISTANCE (Rt)-OHIIS

. ..

10'

LOAD RESISTANCE-OHMS X 103

[g I t4iO
o

2.5

5'

7.5

10

12.5

15

LOAD RESISTANCE-otWS X 103

Fig.8 -Maximllll1 linear signal output as a function
of load resistance.

Fig.9 - Voltage gain as a function of feedback
resistance.

resistance Rr for which the gain approaches
zero.
This condition occurs when the
small-signal transconductance gm of the
transistor Q4 is equal to the conductance
of the parallel tuned circuit; signal
cancellation then results at terminal 7.

In a tuned circuit designed with the
correct feedback resistanceR r , therefore,
zero gain can be obtained at the resonant

Maximum power output was measured at a

level at which output distortion was just
discernible on an oscilloscope.

Tuned Circuit in the Feedback Loop.
When a parallel tuned circuit is included inthe feedback path between termi-

frequency.
The resistance values required for signal cancellation are 2000
ohms for the CA3021, 400 ohms for the
CA3022, and 230 ohms for the CA3023.
When the tuned-circuit impedance is made
equal to these cancellation resistance
values at resonance, the gain increases

219

ICAN-5338
at frequencies off resonance and a trapping
effect results.
For zero feedback resistance, the gai~ of each circuit is
approximately 24 dB.
For values of
feedback resistance in excess of the
cancellation re.sistance, the gain increases.
When the tuned circuit has a
resonant impedance higher than the cancellation resistance, the response is
added to the video response characteristic,
as shown in Fig.lO.
Then, because no
50

.
i

Rp.Wo Lo>R,

ft

40

1/\

z .0

:c

"~
~

\

../

20

~
10

0

z

• ••

•

I--- I---

. ..

10
FREQUENCY-MHz

:--....

•

•

100

Fig.tO - Voltage gain as afunc"tion of frequency in
a bandpass amplifier when the tuned-circuit
resonant impedance Rp is higher than the cancellation resistance Rfc.
purely resistive value occurs that is
equal to the cancellation resistance, no
cancellation occurs.
The bandwidth of the response can be
approximated by determining the total
loading ofR p onthe parallel tuned circuit
in the feedback path, as follows:

where RT is the resistance at resonance
of the unloaded Q, RX is the resistance
added to the tuned circuit for adjustment
of gain, and (R 4 + R8 l is the series
combination of the two common-collector
load resistors.
The 3-dB bandwidth for
the response is given by

Typical values for(R 4 + Ra l for the three
circuits are 39000 ohms for the CA302l,

220

10900 ohms for the CA3022,
for the CA3023.

and 4800 ohms

Output Tuned Circuits. The curves of
Fig.8 indicate that capaci ti ve coupling of
the common-collector output transistor Q6
to a matched load severely limits the
transistor output-voltage-swing capability.
If the required mismatch is
achieved byac coupling of a tuned circuit
directly across the output, the tuned
circuit will be loaded by the low output
impedance of the common-collector transistor. However, comparable output power
can be obtained by use of a resistor in
series with the circuit output and the
tuned circuit. This arrangement provides
a load for the common-collector transistor for frequencies off resonance of the
tuned circuit, and prevents the possibility of reactive loads causing emitterfollower transistor instability.
Gain Control.
The CA302l, CA3022,
and CA3023 are connected as shown in
Fig.2b when gain-control application is
desired.
Transistors Q2 and Qs are then
included in the emitter-signal path of
transistors Q 1 and Q4' respectively.
For
maximum gain, a positive voltage is
applied to terminal 2 which saturates
transistors Q 2 and Qs .
If a voltage of
6 volts is applied to te~minal 2, the
typical gain-control current is 0.8
milliampere.
The gain-control action is
provided by reduction of the voltage on
terminal 2. Thedecreasing voltage causes
transistors Q2 and QS to come out of
saturation and present a high impedance
in the emitter leads of transistors Q1
and Q4. It isimportant that good filtering
and isolation be maintained at the age
t~rminal 2 because transistors Q2 and Qs
are in the linear active region for a
portion of the age range and can, therefore, provide gain for a signal on the age
terminal.
The minimum gain is determined by a
combination of the gain of Q1 and feedthrough to the collector of Q1 along a
resistance path made up of R3 and R 2 .
Because the signals ~re out of phase,
there is a point at which cancellation of
signal results.
This cancellation occurs
in all three circuits when terminal 2 is
0.5 volt more negative than terminal 11.

- - - - - - - - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ ICAN-5338
It is accompanied by severe distortion of
signal and AM modulation_ Techniques for

obtaining agcwithout reaching the cancellation point are discussed later.
When the maximum recommended feedback resistance for operating-point
stability is used in the connection of
Fig.2b, maximum gain is reduced because
of the extra emitter resistance presented

by the saturation resistance of tran-

sistors O2 and 05- Maximum voltage gain
for each circuit is approximately 30 dB
with

the maximum

recommended

feedback

resistance and a 6-volt supply_
typical age

range

The

for each circuit is

55 dB with resistive feedback.

5 per cent) for gain control of -20 to
-30 dB because of the combination of the
low-frequency roll-off and the tuned
response.

In the region of gain control

of -50 dB,
affects

the high-frequency roll-off

the

response

and

the

resonant

frequency decreases below 3 MHz (by about
10 per cent).
At full agc the tuned
circuit becomes a trap in the feedthrough path, minimum gain is achieved

at the 3-MHz frequency,

and the response

is inverted, i. e., a notch occurs where a
bandpass hadexisted.
When tuned circuits

are included in the feedback path of the
gain-controlled amplifier,

therefore,

it

is recommended that the bandwidth be
chosen as wide as possible to minimize

When a tuned circuit is used in the
feedback loop, higher maximum gain can be
obtained in the age connection shown in

detuning effects.
Desired bandwidth
control should be obtained at the input,
at the output, or in the feedback path of

Fig.2b.
The maximum gain obtainable is
approximately 50 dB when high feedback

stages without gain control.

impedance is maintained.
A self-resonant
choke is a convenient element to add in

the feedback loop to obtain high impedance
because it provides wide bandwidth; resistance loading can be added to adjust

the gain to the desired value.

When a

combination of self-resonant choke and
added resistance is used, dc feedback is
complete and the operating point is

temperature-stable.
circuits

are

Wide-bandwidth tuned

suggested

for

all

three

circuits, but especially for the CA3022
and CA3023 because the bandwidth shifts
with gain control,

The use of emitter degeneration as a
gain-control technique improves signal-

handling capability. At full gain control,
signals as high as 2 volts rms can be
handled without the occurrence of serious
overload distortion.
Typical cross-

modulation characteristics forthe CA3021,
CA3022, and CA3023 with only feedback
resistance in the feedback loop are shown
in Fig.12.
Maximum gain for each circuit
0

"'" ~~

fOES1RED-IMHZ

\

as shown in Fig.ll.

'UNDESIRED-IO MHz

0

~

For a tuned frequency of 3 MHz at full gain,
30

---.J

/'
0

.l35v

1,/
0

-20
-30
0.1

0

---v~.~.~

20

,

. ..

ID

,

. J:w

I

/'

0

~~02":R'.2000.Q

"'"

0

-.

.0

0

,

>< /~l.J
V

~o<'<'.
"°0 .

"

i

I

.. , ..
,

10

I

,

~

- -l I
... ...

CA302IiR'''UJ.OOO .Q

10Z

10 3

k)'

INTERFERING SLGNAL-mV

Fig.12 - Cross-modulation distortion characteristics.

1".70V

.,.

....... ,~v

10

,

. ..

FREQUENCY_MHz

Fig.11 -Effect of gain control on response
characteri st i cs.

was approximately 30 dB.

When a tuned

circuit is used in the feedback loop,
more gain-control range is available as a

result of the feedthrough reduction.
Depending on the impedance of the tuned
circuit, the gain-control range is between

for example,

the resonance point of the

tuned response increases slightly (about

60 and 80 dB.

The cross-modulation

characteristics when tuned circuits are

221

ICAN-5338 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

used are similar to those obtained with
resistive feedback except for modifications caused by different feedback
characteristics of interfering

VERTICAL SCALE = 0.5 VIDIV.
HORIZONTAL SCALE = 0.5 J.6/DIV.
RI = 2000 ohms

signal~

outside the tuned-circuit passband.'

Limiting. For applications in which
signal limiting is required, the diodes
of the CA3021, CA3022, and CA3023 are
connected as shown in Fig.2c.
At low
signal levels, the diodes are cut off and
the gain performance is similar to that
described previously except for some
bandwidth reduction caused by the inherent
capacitance of the diodes.
For large

Vin::: 3 mV Ims

I i i I'""""""-1
,I

I

~.-,-,'
I
'

I

input-signal swings in the negative direction, the collector of transistor 0 1

I

becomes positive and the collector of

I

,

-dL~W -~~W -;..J ~
I

1_

~

_

I

j _~

I

transistor Q4 becomes negative, and diode

D2 begins to conduct. This action clamps
the collector of 01 to the collector of
04 and, because the diode is in the feedback path, reduces the gain. For positive
swings at the input, the collector of
transistor 01 becomes negative and the:
output at terminill, 8 becomes positive.

Yin = 10 mV rms

When the circuits are connected

..I

I

I '..J: I..J

- -;-

I

..J

~-i:±:
'
rI1~~I~~-f- ~- l--~-I- l - -

Two effects tend to limit input signals
of positive polarity: transistor 04 going
to cutoff, and diode D3 going into conduction.

I'

I-~----;-

,-- ..J -

-

--~~

-

Vin = 1 V rms

as shown in Fig.2c, limiting is symmetrical at the onset. With increased signal,
however, the symmetry is not perfectly
preserved because of dc shift in the
circuit. Typical output-signal charac-

Fig,13 - Output waveforms obtained in a limiter
application.

teristics as a function of input level

Noise Performance. The table below
shows typical noise figures for the CA3021,
CA3022, andCA3023 circuits for a frequency
of 1 MHz, a supply voltage of 6 volts,
and a source resistance of 50 ohms. The
data in the first column of noise figures

are shown in Fig.13. The lack of symmetry
at high input levels causes a decrease in
power output, as shown in the waveforms.

Limiting characteristics for the
CA3021, CA3022, and CA3023 were measured
in the circuit configurations shown in

Fig.14. The output tuned circuit was
designed to provide filtering for the
desired output frequency so that rms values
of output voltage could be obtained.

were measured in the connection shown in

Fig.2a; the second column shows data
measured in the connection shown in Fig. 2b.

Limiting characteristics were measured

for two types of feedback, resistive and
tuned circuit; results are shown in Fig.lS.
When a resonant circuit is used in the

feedback loop, the gain of the circuits
is higher and limiting occurs at a lower
input level. The effects of multistage
limiting are described later.

222.

Circuit
CA3021
CA3022
CA3023

Noise Figure -- dB
Te rm. 10, I I , 12
AGC operating,
connected to
noise measured
ground; gain
for maximum
gain of 30 dB
110 dB

5.8
7.1
7.2

7.5
8.7
8.7

ICAN-5338

.,

L,
'6V
.6V

O"tq'

•

YIN O.OI".F

f

(a)
FREQ. CI
(MHz) (pF)

TYPE

CA3021
CA3022
CA3023

E

~

0.'

0.5
1

§

(fdI)

OJ

8.2

5.1

_U

T~RCUI

/

V

I

OJ ,

FEEDBACK

(b)

Fig.14 -Circuits used for evaluation
of limiting characteristics.

10
1.2

18

I

0.3

02

(~)

36-64
3-5
1.8

CA3021
SUPPLY VOLTAGE -6V
FREQUENCY· 500 kHz

iii

~

2000
5000
600

CIRCUIT(a) CIRCUIT(b)
RI
(kfl)
'-2 ~
(mH) (pF)

LI

4-45

0.'

-

CA30Z2
SUPPLY VOLTAGE -6V
FREQUENCY. I MHz

l-

-O;-'·iO~

-...;

,/

.I

..

/,/'

I

,

.
I

10

,

.. 6 1,01

:./

,

..

I

03

•

810

1102

2

. . . II,C)!

'~r OHMS

i

/

.

"

LlA

/

V
0.1

..........

/

/

1;1

~

T

TUNED-CIRCUIT FEEDBACK

V

!:

o O.I

lU"Tni::-:::"T'Cj
..

c-

0.4

~ 0.2

""'r-..
r--.r-.

CA3023
SUPPLY VOLTAGE· 6Y

~

~

INPUT SIGNAL-mYfI'"

FREQUENCY· 5 MH~

iii

r--.

.,

810

INPUT SIGNAL-mVrml
O~

V

---/

R,.,J, OIIJS

/'

,

..

6 8 10

. J. .
1'02

'10

INPUT SIGNAL-mYrml

Fig. 15 - Limiting characteristics.

Applications

Supply voltage.
Supply current.

Video Amp1 ifiers. The use of single
CA3021, CA3022, or CA3023 integrated
circuits in video applications was discussed previously.
For an evaluation of

iterative video performance, two CA3022
circuits were operated in cascade.

Each

circuit employed O.Ol-microfarad coupling
capacitors and feedback resistors of
2000 ohms. Performance data can be summarized as follows:

6

volts

4.5

rnA
mW
dB

Power dissipation

27

Voltage gain.

61

Maximum undistorted output

with 510-ohm load.
0.25
Signal level for 3-dB signalto noise ratio
11
Dynamic range (input-output
linearity)
27
Bandwidth, 3-dB points:
upper frequency
10.5
lower frequency
50

Vrms
fl-V

dB

MHz
kHz

223

ICAN·5338
IO-MHz IF Amplifier.
Fig.16 shows a
IO-MHz amplifier employing two CA3023

circuits.

The first stage is operated

in a broadband mode with a 2000·ohm
feedback resistor between terminals 3 and
7, in accordance with the design rules
described previously: The second stage
is a tuned if amplifier.
Because the
sinusoidal output capability of the

00-400 pF

.ovcr--~------------------,

22.0

CA3023 at 10-MHz is in the 200-millivolt
range, it is necessary to step up the
voltage to drive the envelope detector;
therefore, a tuned transformer tnat has
a l-to-4 turns ratio is used at the secondstage output. The total effective circuit
Q for this if configuration is 200, and
the full rf voltage gain is 86 dB from
the input of the first stage to the output
of the step-up transformer.

+ov

n.

,a.
&.B K

ro.

AUDIO

OUTPUT

1

0 •01 1"

5.6 K

OIPF

.,

+ov

IK

IK

!

aT -200

1

4.7K

~

(SUBSTRATE)

0 .0 .1"

I'OPF

CA3018 CONFI6URATION

TO
CARRIER-IO MHz. 30 ... MODULATED

•

WITH I!CHz

DETECTOR NOISE BANDWITH-2.I.HI
SIGNAL

/'
~E

'"
I. . ... .

•
o.

10

........

. 1 " 03 2

INPUT VOLTAGE-,..VnnI

-

t-

•

1 "0.

2

Fig.16 - Schematic di agram and performance curves
for 10-MHz if amp lifier using two CA3023 circui ts.

224

ICAN-5338

below 0.5 volt and causing signal cancellation. Transistor QI of the CA3018

A CA3018 integrated-circuit transistor array isusecl to provide detection,

provides audio gain and is biased in a
conventional manner.
Fig.16 also shows
the output,..signal anclnoise characteristics
of the circuit as functions of rf input

audio amplification, andde amplification.
Detection is provided by transistors Q3
and Q4 of the CA3018; thedetected outputis
passed through a low-pass filter (Cl' C 2 •
and RI) and applied to the age amplifier
transistor Q2.
Transistor Q 2 goes from
cutoff to saturation with increasing
signal.
The voltage drop across a 100-

level for an input signal that is 30-percent modulated by a I-kHz sine wave. The
audio-output equivalent-noise bandwidth

is 2.6 kHz.

ohm degenerative resistor R2 prevents the
~55-kHz IF Amplifier.
Fig.17 shows
a 455-kHz two-stage if amplifier using

gain-control voltage in terminal 2 of the
first CA3023 amplifier from decreasing
'6V~--~------------------------~

<6V

AUDIO
1.8K

OUTPUT

I. K

CASOl8 CONfiGURATION
0
CARRIER-455 kH z. 30% MODULATED
WITH I kttl:
o DETECTOR NOISE BANDW1TH_2.6 11Hz

I

I
SIGNAL

oV

V

NOISE

..---

'0

!

I'-.

"-

0
0

--

4

6 8102

,

4

6 8103

,

... ., ... , , ...
'0

INPUT VOL.TAGE-,.Vrml

'0

,0'

Fig. 17 - Schematic diagram and performance curves
for 455-kHz ifamplifier using two 01.3021 circuits.

225

ICAN-5338 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
28-MHz Two-Stage Limiter Ampl ifier.
Fig.18 shows the circuit diagram of a
28-MHz two-stage limiter amplifier using
two CA3023 integrated ci rcui ts. Terminals
3 and 7 are connected to terminals 4 and
6, respectively; terminal 8 is connected
to terminal 9 to provide limiting action.
A self-resonarit ~oil in parallel with a
2000-ohm resistor isinserted in the feedback loop of each amplifier to provide
gain and stability. The bandwidth of the
system before limiting is 3.8 MHz, and
the effective Q is 7.35. The total gain
is 61 dB (30.5 dB per stage), and the
power dissipation is 66 milliwatts.
Fig.18 also shows the limiting performance
of the system. Full limiting occurs at an
input of 300 microvolts.

the CA302l. The tuned-circuit approach
discussed previously is used in the first
stage. The rf feedback choke is selfresonant at 455 kHz and has a Q of 3.2 in
the circuit. The second stage is a video
amplifier. Input filtering would normally
be provided to obtain the desired if
response. For the particular choice of
stage gain and age loop gain,

an inter-

stage pad network is used to maintain
stability and achieve an acceptable
signal-to-noise ratio with gain control.

The CA3018 output configuration is essentially the same as that used in the
circuit of Fig.16. The signal and noise
characteristics of the 455-kHz amplifier
are also shown in Fig.17 for the same
conditions used for the 10-MHz amplifier.

r-------------------------~--~+6V

* SELF-RESONANT AT 2B MHz
40

V

0

;

Ii

0

o

I:II

FREQUENCY- 28 MHz

\/
'0

V
10

,

,

.

~

..

,0"
4.' '0
'0 VOLTAGE-~V'm.

INPUT

4

,0"

Fig.18 -Schematic diagram and limiting performance
of tvx>-stage 28-MHz "limiter amplifie," using the
CA3023.

226

ICAN-5338
SOO-kHz Limiting Amplifier.
Fig.l9
shows the circuit diagram of a SOO-kHz
limiting amplifier using two CA3021
circuits.
Two SOO-kHz self-resonant
chokes are used in the feedback path.
A tuned circuit is included in the output
to obtain a sine-wave output.
The
limiting characteristics of this amplifier
are also shown. Although limiting occurs

for noise,

a limited signal is apparent

above the noise at an input signal of 1
microvolt. Because of the noise and early
limiting,

voltage gain can only be esti-

mated; however, it is at least 100 dB.
Good limiting performance was obtained for
input signals up to 3 volts rms. Total
power drain for the circuit with a 6-volt
supply was approximately 6 milliwatts.

1000
r-~~--~~------------.---t------O+6V

0.01

'·r'

C,
2000
pF

.. SELF-RESONANT AT ,o0 KHz

40

>
e
1 g 30

~11

1!a
2: ~
>z

20

g~

10

~ffi

o

--

FREQUENCY- 500 kHz

I

2

.. '8(0

2

•2

.. 6810

..

.

'Bco

2

.. 68104 2

.. 6ero'

INPUT VOLTAGE-".Vrms

Fig. 19 -Schematic diagram and I imi ting performance
of two-stage 500-kHz limiter amplifier using the
00021.

227

[IDCD5LJD

Linear Integrated Circuits

Solid State
Division

Application Note
leAN-S3S0

Integrated-Circuit Frequency-Modulation
IF Amplifiers
by
H.C. Kiehn and R.L. Sanquini
Vee

Silicon monolithic integrated circuits that use a
differential-amplifier configuration have certain design
features which make them more attractive than discretecomponent circuits for FM if-amplifier applications.
These features include better performance, small size,
light weight, and more potential circuit. functions per
dollar of cost.
The Dillerential Amplifier

The heart of integrated-circuit FM if amplifiers is
the differential amplifier, which is probably the best
simple configuration available today for symmetrical
limiting over a wide input-voltage range. Each half of
the differential amplifier is alternately cut off on positive and negative half-cycles of the input signal.
As shown in Fig.I, the total current through the
circuit IT is relatively constant. A current equal to
IT/2 flows through each transistor at balance (quiescent condition>. When the base voltage VBI is made

Ie,
Q,

)

i'

1

t

~

t

VeEI

"----'=='

1/8E2

~

~ IT

t

VB2

I

1

Fig.! - Basic clifferenlia/-amplifier configuration.

This material was presented at the IEEE Second Annual Semiconductor-Device Clinic on Linear Integrated Circuits in New
York City, March 24,1967.

"·73

228

ICAN-S3BO

more positive than VB2' however, the collector current
ICI increases and IC2 decreases_ The value of ICI
becomes equal to the total current IT when the following condition exists:
VBl - VB2 - VBEl ~ VBE2 (threshold)
The transistor QI is then full on, and Q2 is then cut off_
Similarly, when VBl is made more negative than VB2'
the value of IC2 becomes equal to IT; QI is then cut off
and Q2 is full on_ When the worst-case value of IT is
kIiown, the maximum load impedance for symmetrical
limiting is selected so that collector saturation does
not occur, as follows:
Resistive Load: RL = VCC/IT
RL = 2 VCC/~

Tuned Load:

the advent of the superheterodyne principle, the inte....
mediate-frequency amplifier became the first building
block that had fixed-frequency tuning, relatively high
gain, and good selectivity as a result of its operation
at a frequency lower than the signal frequency.
Because of its demands for high gain, phase linear
amplification, and good symmetrical amplitude limiting,
and because of the numerous FCC station allocations,
FM broadcasting is now facing the dilemma of providing
selectivity with good phase response. That is, receiver
selectivity must be maintained for large signal inputs
without deterioration of phase response. (A discussion
of the practical solution of this problem is beyond the
scope of this paper.) Successive limiting from the last
stsge back to the first stage can no longer be tolerated.

Under these conditions, symmetrical limiting is
obtained without spurious phase modulation_

High-Goin-Per.Package Differential Integrated-Circuit
IF Strips

The transfer characteristics for a typical differential amplifier shown in Fig_2 illustrate the excellent

Fig.3 shows the schematic diagram of a high-gain
integrated circuit, the CA30I2, which can be used in an
if-amplifier strip to drive a ratio detector. The CA3012
wide band amplifier, designed for use in FM broadcast
or communications receivers, is basically an if amplifie ....limiter intended for use with external FM detectors.
It consists of three direct-coupled cascaded differentialamplifier stages and a built-in regulated power supply.
Each of the first two stages consists of an emitte....
coupled amplifier and an emitte....follower. The operating
conditions are selected so that the dc voltage at the

LIN~R

~

Z

:l

1.0

:Ie2

:Ie,

REGION

V

,.f

""" \

i

1.>1

"U O•8

!:!
>-

~o. 6

I I

1c-

aa:: 0.4
f?
3 0.2
8
a

I-IIIo

!(Vb2-Vb ,)q

f. '\ !tiP JKT,

ill

-10 -

f

-B -6

-V 4

' l) "-.

2
0
2
4
6
DIFFERENTIAL IN:¥~q V3~J:SGE (Vbl-Vb2) -

8

10

Fi!1_2 - Transfer characteristics of basic differe~tia/­
amplifier circuit.

limiting characteristics. Further increases in input
voltage (VBl - VB2) produce no change in collector
current above 4KT/ q unita of input signal.
There are two basic approaches to the design of
integrated-circuit FM if-amplifier stages using differential amplifiers: (1) lumped-filter FM if amplifiers using
high-gain multi-stage integrated-circuit packages, or
(2) individually tuned FM if amplifiers using singlestage integrated-circuit packages. This paper discusses
the performance obtained with these approaches and
outlines their merits and limitations.
Evolution of High-Gain Selective Building Blocks

The tuned rf amplifiers used in early broadcast
receivers soon exhibited a point of diminishing returns
with regard to gain and selectivity improvements. With

Fig.3 - Schematic diagram of CA3012 integrated-circuit
. wideband amplifier.

output of each stage is identical to that at the input of
the stage. This condition is achieved by operation of
the bases of the emitter-coupled differential pair of
transistors at one-half the supply voltage and selection
of the value of the common-emitter load resistor to be
one-half that of the collector load resistor. As a result,

229

ICAN-5380

the voltage drops across the emitter and· collector load
resistors are equal, and the collector of the emittercoupled stage operates at a voltage equal to the base-toemitter voltage VBE plus the common base potential.
The potential at the output of the emitter-follower,
therefore, is the same as the common base potential.
At an operating point 3 dB down from the knee of
the transfer curve, therefore, the CA3012 requires an
input between 400 and 600 microvolts, depending on
the ratio-detector design. Fig.4 shows the use of two
CA3012 units in a 10.7-MHz if-amplifier strip. A double-

practical and does not impose too much burden on alignment. Because IHFM selectivity includes other factors
than passband, a combined filter design that provides
second-channel attenuation between 52 and 60 dB becomes imperative.
Investigation of various types of inductance-capacitance filters indicates the use of a triple-tuned type to
form the major lumped selectivity of the FM receiver.
Fig.6 shows the response curve and two configurations
for such a filter. Economy and ease of alignment are
the major features in this approach.

Fig.4 - IO.7.MHz if.amplifier strip using CA3012 integrated circuit.

tuned filter that has a voltage insertion loss of 8 dB is
located between the two CA3012 units to provide a
filter input of approximately 1000 microvolts (at terminal
5 of the first CA3012). For an if-strip sensitivity of
4 microvolts, a gain of 48 dB is required. However, if
the CA3012 used has a load impedance of 1200 ohms,
the available gain is 65 dB, or approximately 17 dB
more than required. The extra gain is not wasted, but
drives the second CA3012 harder, causing it to limit
so that its gain is reduced by approximately 17 dB.
Fig.5 shows the selectivity of the double-tuned
interstage filter. The 3-dB bandwidth is 200 kHz at
an input of 10 microvolts and 240 kHz at inputs from
500 microvolts to 0.5 volt. The coefficient of critical
coupling is approximately 0.5 at 10 microvolts and increases to 1.0 but still maintains good phase response.
The double-tuned filter should be coupled capacitanceaiding to avoid a nearly in-phase over-all relationship.
Otherwise, hypassing of terminal 10 and the ratiodetector primary becomes critical and over-all stability
is impaired.
The connection of the FM front end to the integrated-circuit if strip must provide good selectivity and
good phase response. A double-tuned filter is not
suitable from the standpoint of selectivity. An actual
IHFM* receiver selectivity between 35 and 40 dB is

*

Institute of High-Fidelity Manufacturers.

230

t:~
P:NTS INPUT

_,,-+=IO~"",-:-:

(\

I
j,

Tr
l~

Kl~
~

-20

"·"OC,.6·-"'·O,c~4"--'·C;;O!.~2---i.---,iO~'.-2--k-· 0.6
FREQUENCY DEVIATION-MHz

Fig.S • Selectivity curve for double-tuned interstage
filter.

The triple-tuned filter, which is located between
the mixer and the first integrated circuit, may have a
voltage insertion loss of 33 dB, depending on the desired
gain distribution. The pO'Ner insertion loss of the
filter, which is between 12 and 17 dB, is the loss that
contributes to if noise. If the primary impedance is
reduced to provide a lower voltage insertion loss, the
front-end gain is decreased by a corresponding amount.
Stability criteria must be the deciding factor in impedance and gain distribution.

ICAN·53BO
bottom inductance or capacitance coupling can be used.
Voltage insertion losses from 18 dB to 26 dB can be
expected. Fig.8 shows the response curve obtained
27 of

1l]~CA3012

120

. ORCA3028

r-----..... ------,,
,lr-----"'fij--', 'ff)
"

'M :
END

FRONr

·6

III

M

L~_~_J I" l-JV1
I

120
pF

I

I

:

1

1

~120
,100
pF
:
pF

000,56!

I

27,
PF:

t

:

22K

-14

I

Z

..ii!
.....
Ii

o .20

;:

·31

·3'
-0,6

-0.4

-0.2

0

0.2

0.4

FREQUENCY DEVIATION-MHz

Fig.6. Configurations and response curve lor triple-

tuned interstage filter.

Most FM front ends come equipped with a doubletuned 10.7-MHz if transformer in which a secondary
high-impedance winding is brought out capacitively
unterminated and non-polarized with respect to ground.
This configuration does not lend itself readily to optimum
skirt selectivity (form factor) when connected with an
additional single-tuned transformer to form a tripletuned filter. Most effective use of the existing front-end
filter is accomplished by the addition of another doubletuned filter, such. as those shown in Fig.7. Either

Fig.7. Configurations of two quadruple.tuned interstage
filters.

FREQUENCY DEVIATION -MHl

Fig.8. Response curve obtained with quadruple.tuned
filter.

with a quadruple-tuned interstage filter. The per-cent
coupling between filters and the coupling mode must be
determined on the basis of over-all stability and performance.
It may be appropriate to consider briefly the noise
associated with high-insertion-loss filters. Over-all
receiver noise F is calculated as follows:
F2-1 F3-1
F' =F1 + - - + - G1
G1G2
where F1, F2, and F3 are the noise figures of the first
(rf), second (mixer), and third (if) stages, respectively;
and G1 and G2 are the power gains of the first and
second stages. If a value of 27 dB is assumed for the
if noise figure F3 (filter plus integrated circuit), 10 dB
for the mixer noise figure, and 30 dB for mixer power
gain, the effect of if noise on mixer noise is determined
as follows:
F3-1
27-1
F2 ' = F2 + - - = 10 + - - = 10.87 dB
G2
30

231

ICAN-S380 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

If the rf stage is assumed to have a power gain of 15 dB

and a noise figure of 5 dB, total receiver noise is then
determined as follows:
10.87-1
F2 ~1
F =F1 + - - =5 + - - = 5.66 dB
G1

15

These calculations show that the power gain of
the rf-amplifier stage ovelTides both if noise and mixer
noise. A minimum power gain of 10 dB is advisable.
The use of a tuning capacitance of 82 picofarads
in the collector circuit of the mixer stage provides a
loaded primary impedance of approximately 10,000 ohms
and eliminates the need for a tap. The 27-picofarad
tuning capacitances that comprise the other poles of this
filter could be reduced to obtain more favorable loadedto-unloaded-Q ratios without use of additional resistor
loading. The choice of 27 picofarads was based primarily on circuit stability considerations.
Fig.9 shows one type of complete integrated-circuit
if strip, and Fig.10 shows the accompanying voltage
gains and impedances. Values are given for two levels
of mixer output impedance. All other impedance levels
shown have exhibited good stability_ Over-all performance of the circuit is illustrated in Fig.n.

Capture ratio, which was measured at various levels,
varies from 5 dB at 2 microvolts to 1.2 dB above. 500
microvolts. With careful adjustment, values as low as
0.8 dB can be obtained. The selectivity curve for the
integrated circuit if strip is shown in Fig.12. Over-all
selectivity for a given ratio detector and the if strip is
shown in Fig.13. Some distributed-selectivity receivers
have very little ·second-channel selectivity at an antenna
input of 2000 microvolts. The points marked in Fig.13
show such selectivity for several antenna input levels.
Fig.14 shows an if strip that combines high gain
per package and the single-stage-per-package approach.
CA3012 and CA3028 integrated circuits are used in a
differential-mode connection. . An if sensitivity of 15
microvolts can be obtained with this if strip.
If discrete circuits are directly replaced by single
differential integrated-circuit amplifiers, a minimum of
if transformer and printed-circuit-board redesign is required. Values of voltage gain and impedance are indicated on the block diagram in Fig.15. All three doubletuned transformers are made symmetrical with respect
to primary and secondary windings and taps.
Because the single- or double-tuned circuit used
between the mixer and the if strip has inherently less

Fig.9 - Complete 10.7-MHz if-amplifier strip using two C43012 integrateJ circuits.

insertion loss than a triple-tuned input filter, the input
required is 20 instead of 3.5 microvolts. All three
double-tuned if transformers have an insertion loss of
6 dB and a 3-dB bandwidth of 280 to 300 kHz. The ratiodetector primary impedance dictates the stage gain of
36 dB for the last integrated circuit. Each of the remaining three stages has a gain of 21.5 dB, for the total
required gain of 100 dB. The impedance required for
the desired stage gain was calculated to be 660 ohms
Fig.IO - Yoltage gain anJ impeJance values for if-amp/i-·· for both· the primary and secondary windings of the if
transformers.
fier strip of Fig.7.

232

_________________________________________________________ ICAN-5380
I.0r------=:;;:::~:::::::::::::::::::::::;=·~--~

:::v

100

eo
60

""-Q","o"

10
20
30
40
.0

.

~'Q,.-a...-o.._ ......_9'- __ _

,

6

10

IIIO~~O~

INPUT VOLTAGE-...V

Fig. 11 - Performance curves for if-amplifier strip of Fig.7_

-,

-.

-,

-.

-10
-14

POINTS INPUT
2.' V

-12
-20


TIME-5"I/DlY.

TIME-51's/DIY.
RL-soo.o.; CL -0.001 pI!

C,-o,-o.ol,.F

NO LOAD;C,,-Cy-O.ol "F

'+--*2--~4-+.~.~~2~~4~.~.H-~2~~4~.'.~--2~-4~.Hrl.
0.0001

0.001
0.01
0.1
PHASE-COMPENSATION CAPACITANCE -I'F

Fig.5 - Frequency for full power output as a function
of pha3e-componsatiiig capacitt:mce.

~

"'>:"

-'

g

.,~
I
'"~

~~

0

>
TIME-50"IIDIV.

TIME-SOlls/DIV.

Fig.7 - Waveforms for the 60-J8 amplifier
shown in Fig.6.

Fig.5 shows that full output swing with no load may be
expected up to a frequency of 280 kHz. Therefore, the
design is capable of full power output up to the 3-dB
point.

Applications

A similar approach may be used for a pulse amplifier. Two 0.01-microfarad phase-compensating capaci-

Fig.8 illustrates the use of the CA3033A in a 20-dB,
255-milliwatt power amplifier operating from a single

238

---------------------------------------------------------ICAN-5641
+36V

the rudiments of a digital voltmeter, using the linear
staircase approach, without the associated totalizing
circuitry.

IOpF
O.lI4F
SOVpSOV

Fig.IO shows a block diagram of the system, together with the waveforms of all interfaces. A squelchable integrated-circuit multivibrator is used as the clock.
As described later, the clock frequency is independent
of supply voltage. Although this independence is not a
necessary condition for circuit operation, it is inherent
in this type of operational-amplifier multivibrator circuit
and may be considered an integrated-circuit bonus.

INPUT

o-J

~~~

"

5.1K

Fig.B - 20-dB, 255-milliwatt pawer amplilier using
a CA3033A operating Irom a 36-volt supply.
36-volt supply. Fig.9 shows the pulse response of this
amplifier under no-load conditions and with a resistive
load of 500 ohms; also shown are curves of distortion
as. a function of frequency. The waveforms show that
the pulse response of the amplifier is limited by slewing
rate rather than frequency response. Some crossover
distortion is evident in the respo"lse for the SOD-ohm load.
PULSE RESPONSE-RL"500~

PULSE RESPONSE-NO LOAD

TIME-IOl4s/DIV.

TIME -IO,.s/olY.

6

4

I I
I I
I I
POWER

2

(m~I'~5

RL=500n

5

,
,
0
0.01

2

..,

0.1

OUTPU~t:

2

."

....+::!-1

/

~
220

6

FREQUENCY-kHz

Fig.9 . Pulse-response waveforms and distortion curves
lor the amplilier shown in Fig.B.

The output from the clock drives a linear staircase
generator. Input voltage to this circuit is applied directly from the multivibrator to minimize the effects of
diode temperature coefficients. The output from the
staircase generator is applied to a comparator that
compares the staircase with the voltage to be measured.
The comparator output fires a monos table multivibrator that controls the display time, which is variable
from about 100 milliseconds to one second. An inverter
following the multivibrator supplies drive of the correct
polarity to the integrator capacitor-discharge switch and
the multivibrator squelch circuit.
Circuit operation begins with the staircase generator
ramp running down until its voltage is equal to the unknown voltage on the input of the comparator. When the
two voltages are equal, the monostable multivibrator is
triggered by the output from the comparator. The output
of the monostable multi vibrator squelches the astable
multivibrator and discharges the integrating capacitor
through the bistable multi vibrator. The wait, or display
time, set by the monostable multivibrator allows sufficient time for full discharge of the integration capacitor
and appears as a steady reading on the display device.

Astable Multivibrator - A schematic diagram of a
squelchable multivibrator is shown in Fig. 11. The only
requirement that must be met by the squelch circuit is
that the amplitude of the output pulse not change as a
result of the squelch operation; otherwise, the amplitude
01 the final steps would be different from that of the
initial steps and staircase linearity would suffer.

The impedance of the feedback network can have a
significant effect on the pulse response of a given amplifier design, particularly when higher-frequency performance is required. The response is influenced by the
stray capacitance of the associated wiring, the shunt
capacitance of the feedback resistors, and the input
impedance of the operational amplifier. Because the
CA3033 and CA3033A have higher input impedance as a
result of the emitter-follower inputs, the input capacitive
loading is reduced considerably and higher-impedance
feedback networks can be used.

Freedom of the circuit from supply-voltage variations
results from the excellent saturation characteristics of
the integrated circuit at both positive and negative output swings. The positive and negative thresholds of
the circuit are given by

A simple system was fabricated to demonstrate the
ease with which the CA3033 and CA3033A operational
amplifiers may be applied. The basis of the system was

where VCC and VEE are the positive and negative supply voltages and VCE+sat and VCE-sat are the positive
and negative saturation voltages of the amplifier. Be-

Positive threshold = (VCC - VCE+

Negativethreshold = (VEE + VCE

sa

t)

~
Rl +R2

Rl
) ---sat Rl +R2

239

,

ICAN-5641---------------------------TO TOTALIZING
COUNTER

INPUT FROM
DC AMPLIFIER

+IIVlf
-IIV

CLOCK
SQUELCH

+IIX~ MU&~I~~A~~~PUT
~
'-L

O""l......"".
-25 mV

~:: ~

'-LJ
-----u

STAIRCASE GENERATOR
OUTPUT
COMPARATOR OUTPUT

~:: ~ - - - ,

MOHOSTAB~ijT~\TIVIBRATOR

+22V

o _ _ _ _ _ _ _Jl..._ _ _ _

~::~~

TOTALIZER RESET OUTPUT
BISTABLE INVERTER OUTPUT

Fig. 10 - Block rliagram anrl waveforms of rligital voltmeter system
using five CA3033 integraterl circuits.

cause these saturation voltages are low and have temperature coefficients less than 5 millivolts per degree C,
they can be· neglected for ease of computation. If the
charging current is considerably greater than the base
current, the frequency f may be expressed as follows: 3

·2

-,

r VCC

L---J VEE

SQUELCH
VOLTAGE

SQUELCH VOLTAGE, VCC , CUTS OFF MULTIVIBRATOR
I~
I
.... 2RCln(2R~1 +1)

Fig.11 - CA3033 sque/chable astable multivibrator.

240

Linear Staircase Generator - The design of a linear
staircase generator is nearly identical to that of a linear
ramp or sawtooth generator. Fig.12(a) shows a linear
ramp generator in which the non-inverting input of an
operational amplifier is grounded and a switch 51 returns
the output to . the inverting input. When Sl is closed,
the amplifier is in the unity-gain configuration and the
output is at ground less the input offset voltage. When
Sl is opened, the output moves in the positive direction
when the reference voltage Vref is negative, or in the
negative direction when Vref is positive. Because the
output under closed-loop conditions tries to maintain
the input terminal at zero voltage, the. charging current
to the capacitor is constant at a rate of dV/ dt = i/C,

------------------------------ICAN-5641
where i = Vref/R_ It is apparent that this analysis is
valid as long as the input current to the first stage is
considerably .less than the charging current.

Fig_12(b) shows the circuit for a linear staircase
generator. In this circuit, a pulse of amplitude e couples
a charge Q to the amplifier input. The charge Q is
equal to CI (e - 2Vak), where 2Vak is the forward voltage drop across the two diodes. Again, if the amplifier
input current is small compared to the effective charging
current, capacitor C2 is incrementally charged in steps
of (e - 2V a k) CI/C2. If the pulse height is made sufficiently large compared to the expected temperature
variations of the diodes, a reasonable degree of temperature independence results.

LINEAR RAM~VrefNEGATIVE
OUTPUT

3

0,
5, OPENS................. Vref POSITIVE

dV

Vref

i

(if""C

. Vref

'-"'"'R""

(a)

L

c,

. nrLfl o-j..........,-~

T

(b)

"

Fig. 12 - Diagrams 01 (a) linear ramp generator and
(b) linear staircase generator.

timing capacitor in conjunction with the diode D3 permits
the fast recycling time necessary for the one-step case.
Triggering of the :circuit is accomplished by the 470picofarad capacitor to the non-inverting input (terminal 10).

An RC timing network is incorporated at the output
of the monostable multivibrator to add an additional
ISO-millisecond delay that performs two functions.
First, the added delay allows more time to complete the
The
timing-capacitor recycling mentioned above.
second and more important function of this network is
the generation of a reset pulse at the trailing edge of
the monostable multi vibrator. Diode D4 couples the
negative output of the multivibrator to the next stage
and rapidly charges the 0.22-microfarad network timing
capacitor through the 470-ohm resistor. After the monostable multivibrator completes the cycle, diode D4 disconnects, and the 0.22-microfarad capacitor charges to
the 1. I-volt switching threshold of the next stage through
the two one-megohm resistors. This cycle is approximately ISO milliseconds.
Bistable Multivibrator - The output from the monostable multivibrator is coupled to the next stage, a bi. stable multivibrator or inverter. The switching thresholds
are determined by the 100,000- and 10,000-ohm resistors
in the positive feedback loop. The primary function of
this stage is to invert the signals from both the comparator and the monostable multivibrator to drive the
clock-astable-multivibrator squelch circuit and the
staircase capacitor-discharge switch, an RCA-3NI41
dual-gate MOS field-effect transistor. Diode D6 protects
the gates of the MOS transistor; the 47-picofarad capacitor reduces the rise time of the negative-going output
of the bistable multivibrator and prevents it from coupling
into the beginning of staircase and obscuring the first
few steps by this negative transition.
Acknow ledgment

Comparator - Regeneration is added around the
comparator circuit in this system to accelerate the transition time when the two input voltages are equal.
Fig. 13 shows a complete schematic diagram of the
entire system.

Waveforms at critical points are shown

in Fig.14. The 470-picofarad capacitor and 1000-ohm
resistor between terminals 3 and 10 of the CA3033 in
the comparator circuit provide the regeneration. Two
O.OOI-microfarad capacitors on each input filter any
externally generated noise.
Monostable Mu Itivi brator - The monostable multivibrator circuit shown in Fig.13 makes use of the extremely low input bias currents of the CA3033 by using
small timing capacitors and large timing resistors to
obtain the long (one-second) display time. The small

The author thanks A. J. Leidich for his work on the
design of the CA3033 and CA3033A and for supplying
the noise-figure curve, and J. Klinger for breadboarding
and evaluating the many circuits used in the paper.
References

1. R. Stata, "Operational Amplifiers/' Electromechanical
Design, page 51, September 1965.
2. Valley. G. E., Jr-. and Wallman, H., "Vacuum-Tube
Amplifiers," page 80, Massachusetts Institute of
Technology Radiation Laboratory Series, Volume 18,
McGraw-Hill Book Co .• New York 1948.
3. Engineering Staff of Philbrick Researches, "Philbrick Applications Manual," page 72, Second Edition.
June 1966.

241

ICAN-5641 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
LINEAR
STAIRCASE
GENERATOR

CLOCK ASTABLE
MULTIVIBRATOR

DC COMPARATOR

Vee

1f

BISTABLE INVERTER

Vee

."V ,---,
- IIV

.J

L

-"""_---''"'''''''"='_

~

L._ _ _

+ "V

/L_ll-~t_-t_--oTOTALIZER
RESET

NOTE: SUPPLY DECOUPLING NOT SHOWN

Vee -+12 V
VEE'"-12V

-IIVJ---[O" TO I
SECONO
VARIABLE DISPLAY TIME

Fig. 13 - Schematic diagram of a digital voltmeter using CA3033 integrated circuits.
STAIRCASE GENERATOR

OUTPUT (O.lVlDIV.1
ClOCK OUTPUT (IOV IDlY. I

~t

COMPARATOR

-

OUTPUT
,

------

-----------.-----._ ... _-.---.- ....
0.2 ms/DIV.

TOTAUZER RESET OUTPUT

50

~s/DIV.

cLOCK 0I1TPUT
STAIRCASE GENERATOR OUTPUT

2,..s/DIV.
BISTABLE MULTIVIBRATOR

OUTPUT

Fig. 14 - Waveforms for the digital voltmeter
shown in Fig.13.

242

+IIV
-IIV

OO(]3LJD

Linear Integrated Circuits

Solid State

Application Note

Division

ICAN-5766

APPLICATION OF THE RCA CA3020 AND CA3020A
INTEGRATED-CIRCUIT MULTI-PURPOSE
WIDE-BAND POWER AMPLIFIERS
by
W. M. AUSTIN AND H. M. KLEINMAN
The discussions in this Note are applicable to both'integrated-circuit types. The CA3020A can operate in all
circuits shown for the CA3020. The CA3020, on the other
hand, has a lower voltage rating and must not be used in
applications which require voltages on the output transistors greater than 18 volts. The integrated circuit protects
the output transistor by limiting the drive to the output
stages. The drive-limited current capability of the CA3020
is less than that of the CA3020A, but peak currents in
excess of 150 milliamperes are an assured characteristic of
the CA3020.
The RCA CA3020 and CA3020A integrated circuits are
mUlti-purpose, multi-function power amplifiers designed
for use as power-output amplifiers and driver stages in
portable and fixed communications equipment and in ac
servo control systems. The flexibility of these circuits and
the high-frequency capabilities of the circuit components
make these types suitable for a wide variety of applications
such as broadband amplifiers, video amplifiers, and video
line drivers. Voltage gains of 60 dB or more are available
with a 3-dB bandwidth of 8 MHz.
The discussions in this Note are applicable to both integrated-circuit types. The CA3020A can operate in all

circuits shown for the CA3020. The CA3020, on the other
hand, has more limited voltage- and current-handling
capability and must not be used in applications which
require voltage swings on the output transistors greater
than 18 volts or peak currents in excess of 150 milliamperes.
The CA3020 and CA3020A are designed to operate
from a single supply voltage which may be as low as + 3
volts. The maximum supply voltage is dictated by the type
of circuit operation. For transformer-loaded class B amplifier service, the maximum supply voltages are + 9 and
+ 12 volts for the CA3020 and the CA3020A, respectively.
When operated as a class B amplifier, either circuit can
deliver a typical output of 150 milliwatts from a +3-volt
supply or 400 milliwatts from a + 6-volt supply. At + 9
volts, the idling dissipation can be as low as 190 milliwatts,
and either circuit can deliver an output of 550 milliwatts.
An output of slightly more than 1 watt is available from
the CA3020A when a + 12-volt supply is used.
CIRCUIT DESCRIPTION AND OPERATION
Fig. 1 shows the schematic diagram of the CA3020 and
CA3020A, and indicates the five functional blocks into

8-67

243

ICAN-5766 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3, and terminal 2 is grounded through a suitable capacitor.
When the signal becomes positive, transistor O2 is turned
on and its collector voltage changes in a negative direction.
The same current flows out of the emitter of O2 and tends
to flow to ground through resistor R2 • However, the im
pedance of R2 is high compared to the input impedance
of the emitter of Qa, and an alternate path is available
to ground through the emitter-to-base junction of transistor
Q a and then through the bypass capacitor from terminal 2
to ground. Because this path has a much lower impedance
than R 2, most of the current takes this alternate route.
The signal current flowing into the emitter of Q 3 reduces
the magnitude of that current and, because the collector
current is nearly equal to the emitter current, the collector
current in Q3 drops and the collector voltage rises. Thus,
a positive signal on terminal 3 causes a negative ac voltage
on the collector of transistor Q 2 and a positive ac voltage
on transistor Q3' and provides the out-of-phase signals
required to drive the succeeding stages. It should be noted
that the differential amplifier is not balanced; resistor R;l
is ten per cent greater than R I . This unbalance is deliberately introduced to compensate for the fact that all of
the current in the emitter of Q2 does not flow into 0 3 ,
Use of a larger load resistor for transistor Q 3 compensates
for the lower current so that the voltage swings on the
two collectors have. nearly the same magnitude.
N

OUTPUT

DRIVER

STAGE

II
I
I
I
I
10 6 4

I

I
I

I

I

I ~~ I I
L-.l __ '_2 _~L_.-l ~
I

Fig. I-Schematic diagram of CA3020 and CA3020A
;ntegrated-circuit amplifiers.
which the circuit can be divided for understanding of its
operation. Fig. 2 shows the relationship of these blocks in
block-diagram form.
A key to the operation of the circuit is the voltage
regulator consisting of diodes D 1 , D 2 , and Da and resistors
RiO and R ll . The three diodes are designed to provide
accurately controlled voltages to the differential amplifier
so that the proper idling current for dass B operation is
established in the output stage. The characteristics of these
monolithic diodes closely match those of the driver and
output stages so that proper bias voltages arc applied over
the entire military temperature range of -55 to + 125°C.
The close thermal coupling of the circuit assures against
thermal runaway within the prescribed temperature and
dissipation ratings of the devices.
The ditferfntial amplifier operates in a class A mode to
supply the power gain and phase inversion required for
the push-pull class B driver and output stages. In normal
operation, an ac signal is capacitively coupled to terminal

AC

The power transistors (QG and 0,) are large, highcurrent devices capable of delivering peak currents greater
than 0.25 ampere. The emitters are made available to
facilitate various modes of operation or to permit the
inclusion of emitter resistors for more complete stabilization of the idling current of the amplifier. Inclusion of
such resistors also reduces distortion by introducing negative feedback, but reduces the power-output capability by
limiting the available drive.
Inclusion of emitter ·resistors between terminals 5 and 6
and ground also enhances the effectiveness of the internal
dc feedback supplied to the bases of transistors O2 and 0"
through resistors R!j and R 7 • Any increase in the idling
current in either output transistor is reflected as an increased voltage at its base. This change is coupled to the
input through the appropriate resistor to correct fQr the
increased current.
A later section of this Note describes how stable class A
operation of the output stages may be obtained.

INPUT

TO
TERMINAL

No.lO

The driver stages (transistors Q 4 and Q5) are emitterfollower amplifiers which shift the voltage level between
the collectors of the differential-amplifier transistors and
the bases of the output transistors and provide the drive
current required by the output transistors.

BUFFER
AMP.

OPERATING CHARACTERISTICS
ALTERNATE

AC
INPUT
TO
TERMINAL

No.3

Fig. 2-Functional block diagram of the CA3020 and
CA3020A.

244

Supply Voltages and Derating_ The CA3020 operates
with any supply voltage between + 3 and + 9 volts. The
CA3020A can also be operated with supply voltages up
to + 12 volts with inductive loads or + 25 volts with
resistive loads. Fig. 3 shows the permissible dissipation
rating of the CA3020 and CA3020A as a function of case

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ICAN_5766
Basic Class B Amplifier. Fig. 4 shows a typical audioamplifier circuit in which the CA3020 or CA3020A can
provide a power output of 0.5 or I watt, respectively .
Table I shows performance data for both types in this
amplifier. The circuit can be used at all voltage and poweroutput levels applicable to the CA3020 and CA3020A.

•
2

~

r - -...... . - . - - - - - -.. vCCI

~~"

vCC2

J~~~
Tell/J

510K

~"<4rUR£

o
~

~

~

~

'1-- ~
~

~

TEMPERATURE -

~

~

~

·C

Fig. 3-Dissipation rating of the CA3020 and CA3020A
as a function of case and ambient temperatures.
and ambient temperatures. At supply voltages from + 6 to
+ 12 volts, a heat sink may be required for maximum
power--output capability. The worst-case dissipation P dmax
as a function of power output can be calculated as follows:

p'm•• = (Vee, Icc,

+

Vec2 Iee2)

+

(Vcc;/(Rcc)

where Vee, and Vee2 are the supply voltages to the differential-amplifier and output-amplifier stages, respectively;
Icc, and Icc2 are the corresponding idling currents; and
Reo is the collector-to-collector load resistance of the output transformer. This equation is preferred to the conventional formula for the dissipation of a class B output transistor (i.e., 0.84 times the maximum power output) because
the Pdmax equation accounts for the device standby power
and device variability.

Table 1 -

.v

5.F

* Better Coil and Transformer OF10BA,
Thordarson TR-192, or equivalent.
• see text and tables.

Fig. 4-Basic class B audio amplifier circuit using the
CA3020 or CA3020A.

The emitter-follower stage at the input of the amplifier
in Fig. 4 is used as a buffer amplifier to provide a high
input impedance, Although many variations of biasing may

Typical Performance of CA3020 and CA3020A in Circuit of Fig. 4*

Characteristic

CA3020

CA3020A

Power Supply -

Vco, ............................. .
V
9
9
Vee2 ............................. .
9
12
V
Zero-Signal Idling Current - Icc, ...........•..... _..
15
15
rnA
24
rnA
Icc2 ...............•....
24
rnA
16
16.6
Maximum-Signal Current - Icc, ..................... .
rnA
140
Iec2 ..................... . 125
1000
mW
Maximum Power Output at 10% THO ............... . 550
Sensitivity ..................... _... _ • _ .••••• __ •••.
35
45
mV
dB
7S
7S
Power Gain., "'.' .. ,,.,' ......... , ............... .
55
55
ko
Input Resistance , .. ", ......... ' .................. .
45
SS
%
Efficiency ....................................... .
dB
66
Signal-to-Noise Ratio ...................... _.......•
70
3.3
%
% Total Harmonic Distortion at 150 mW .... _....•.... 3.1
Test Signal .................•...........•......•.. 1000 Hz/6000 generator
200
0
Equivalent Collector-to-Collector Load ...... _.....••.. 130
1000
fl
Idling-Current Adjust Resistor (R, ,) .................. . 1000
• Integrated circuit mounted on a heat sink, Wakefield 209 Alum. or equiv.

245

·ICAN-5766 - - - - - - - - - - - - - - - - - - - - - - - - - - - _
be applied to this stage, the method shown is efficient and
economical. The output of the buffer stage is applied to
terminal 3 of the differential amplifier for proper balance
of the push-pull drive to the output stages. Terminals 2
and 3 must be bypassed for approximately 1000 ohms at
the desired low-frequency rolloOff point.
At low power levels, the crossoOver distortion of the
class B amplifier can be high if the idling current is low.
For low cross-over distortion, the idling current should
be approximately 12 to 24 milliamperes, depending on
the efficiency. idling dissipation. and distortion requirements of the particular application. The idling current may
be increased by connection of a jumper between terminals
8 and 9. If higher levels of operating idling current are
desired, a resistor (R l1 ) may be used to increase the regulated voltage at terminal 11 by a slight amount with additional current injection from the power supply Vee,.
In some applications, it may be desirable to use the
input transistor Q, of the CA3020 or CA3020A for other
purposes than the basic buffer amplifier shown in Fig. 4.
In such cases, the input ac signal can be applied directly
to terminal 3.
The extended frequency range of the CA3020 and
CA3020A requires that a high-frequency ac bypass capacitor be used at the input terminal 3. Otherwise, oscillation could occur at the stray resonant frequencies of
the external components, particularly those of the transformers. Lead inductance may be sufficient to cause
oscillation if long power-supply leads are not properly
ac bypassed at the CA3020 or CA3020A common ground
point. Even the bypassing shown may be insufficient unless
good high-frequency construction practices are followed.

-

IZOO

:.

~IOOO

?

...............

-r--.

5600

§

1-- -.!!

",.-

::..-

",400

~ 200

-8"";

r;;;- r-- t--£-

/"

1/

I":::::-.

~

C:r "t I~ f-j

r Ia

I•
I

4 1\
2

1/.

/

e

/ /

Ol

-

/

100

/

./

V-

V "-"

./ . / v"

/1

~

300 400 500 600 700
POWER OUTPUT -MILLIWATTS

200

CURVE
CA3020 CA3020A

IDLING CURRENT

·I' I"
(mA)

e'

•

15
15

C

C

12

· °

•

24

14

•

POWER.SUPPL Y
VOLTAGE (V)

••
6

3

BOO

RCC

900

(OHMS)

I'~ ,..
200
150
50

1000

Rll
(OHMS)

111"

' ..0
1000
220

Fig. 6-10tal harmonic distortion of the CA3020 or
CA3020A as a funetion of power output.

r-

0

400
100
300
200
COLLECTOR-lO-COLLECTOR LOAD RESISTANCE (Ree)-OHMS

CURVE
CA3020 CA3020A

IDLING CURRENT
(mA)

POWER·SUPPLY
VOLTAGE (V)

leel

ICC2

VecI

9
9
7
8

10

9
9
6
3

A

B'

B

C'

C

0

10

6
8

Rll
(OHMS)

VCC2

12

00

9
6
3

00

00
220

Fig. S-Power ·output of the CA3020 and CA3020A as
a function of colleetor-to-collector load resistance Rec.

246

TA-25-C

~

o

1"---4. . . .

/

d

'"I 600

§,2

.~

TA-25 6 C

I!!

Fig. 5 shows typical power output of the CA3020A at
supply voltages of +3, +6, +9, and + 12 volts, and of
the CA3020 at + 6 and + 9 volts, as measured in the
basic class B amplifier circuit of Fig. 4. The CA3020A
has higher power output for all voltage-supply conditions
because of its higher peakoOutput-current capability.
Fig. 6 shows total harmonic distortion (THO) as a function of power output for each of the voltage conditions
shown in Fig. S. The values of the collector-to-collector
load resistance (Ree) and the idling-current adjust resistor
(R l1 ) shown in the figure are given merely as a fixed
reference; they are not necessarily optimum values. Higher
idling-current drain may be desired for low crossoOver
distortion, or a higher value of ~'C may be used for better
sensitivity with less power-output capability. Because the
maximum power output occurs at the same conditions of
peak-current limitations, the sensitivities at maximum.,.power output for the curVes of Figs. 5 and 6 are approximately the same. Increasing the idling-current drain by
reducing the value of the resistor Rl1 also improves the
sensitivity.

Fig. 7 illustrates the improvement in crossoOver distortion at low power levels. Distortion at 100 milliwatts is
shown as a function ~f idling current Icc. (output stages
only). There is a small improvement in total harmonic
distortion for a large increase in idling current as the
current level exceeds 15 milliamperes.
APPLICATIONS
Audio Amp6fiers. The circuit shown in Fig. 4 may be
used as a highly efficient class B audio power-output circuit
in such applications as communications systems, AM or
FM radios, tape recorders, phonographs, intercom sets,
and linear mixers. Fig. 8 shows a modification of this

-----------------------------ICAN-5766
circuit which may be used as a transformerless audio
amplifier in any of these applications or in other portable
instruments. The features of this circuit are a power·output
capability of 310 milliwatts for an input of 45 millivolls,
and a high input impedance of 50,000 ohms. The idlingcurrent drain of the circuit is 24 milliamperes. The curves
of Fig. 5 may be used 10 determine the value of the
cenler-tapped resistive load required for a specified poweroutput level (the indicated load resistance is divided by
two).

(.1

VCCl z 6V, VCC2-6V, RL -'DO OHMS,(RII-VARIABLE)

TA-25-C

2
0

•
6

4
2

\

O. COLLECTOR
LOAD LINE RIO
OR
........... ~RIO+RII OF CA3020

~

..........

'" """ -I'---.

10

E,-

14

16

(.,

Fig. 9-Method of opplying squelch to the CA3020 or
CA3020A to save idling dissipation.

I.

Fig. 7-Total harmonic distorlion os a function of idling
current for a supply voltage of 6 volts and an
output of 100 milliwatts.
The CA3020 or CA3020A provides several advantages
when used as a sound output stage or as a preamplifierdriver in communications equipment because each type is
a compact and low-power-drain circuit. The squelching
requirement in such applications is simple and economical.
+9V

r---'

I

I

I
I

I

:

DlFF. AMP. TERMINAL II

OPERATING VOLTAGE

..........

12

MOFf"

I

I

I
I

L ___ J
RCA-11I113

130-0HM SPEAKER

OR EQUIV.

Fig. 8-310·mil/iwall audio amplifier without

is "off" and draws only fractional idling dissipation. The
only current that flows is that of the buffer-amplifier transistor Q 1 in the integrated circuit and the saturating current drain of Q,. For a circuit similar to that of Fig. 8,
the squelched condition requires an idling current of approximately 7 milliamperes, as compared to a normal
idling-current drain of 24 milliamperes.
In applications requiring high gain and impedance
matching, the CA3020 or CA3020A can be adapted for
use without complex circuit modifications. Detectors having
low signal outputs or high impedances can be easily
matched to the input of the CA3020 or CA3020A buffer
amplifier. The typical integrated-circuit input impedance
of 55,000 ohms may be too low for crystal OUlput devices
such as phonograph pickups, but the sensitivity may be
sacrificed to impedance-match at the input while still providing adequate drive to the CA3020 or CA3020A. Both
types may be used in tape recorders as high-gain amplifiers,
bias oscillators, or record and playback amplifiers. The
availability of two input terminals permits the use of the
CA3020 or CA3020A as a linear mixer, and thus adds to
its flexibility in systems that require adaptation to multiple
functions, such as communications equipment and tape
recorders.
Fig. 10 illustrates the use of the audio amplifier shown
in Fig. 4 in an intercom in which a listen-talk position
switch controls two or more remote positions. Only the
speakers, the switch, and the input transformer are added
to the basic audio amplifier circuit. A suitable power supply for the intercom could be a 9-volt battery used intermittently rather than continuously.

transformers.

Fig. 9 shows a practical method of providing squelch to
the CA3020 or CA3020A. When the squelch switching
transistor Q. is in the "on" state, the CA3020 or CA3020A

Wide-Band Amplifiers. A major general-purpose application of the CA3020 and CA3020A is to provide high gain
and wide-band amplification. The CA3020 and CA3020A

247

ICAN-5766 _.,.--_-,-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
+9V

by the emitter-to-ground resistance. The circuit in Fig. II
is a wide-band video amplifier that provides a gain of 38
dB at each of the push-pull outputs, or 44 dB in a
balanced-output connection. The 3-dB bandwidth of the
circuit is 30 Hz to 8 MHz. Higher gain-bandwidth performance can be achieved if the diode-to-ground voltage
drop at terminal 12 is reduced. The lower voltage drop
permits the use of a higher ratio of output-stage collectorto-emitter resistors without departure from the desired
portion of the class A load line. It is important to note
that the temperature coefficient of the terminal-12-toground reference element should be sufficiently low to
prevent a large change in the current of the output stages.
The same method for achieving class A bias is used in
the large-signal-swing output amplifier shown in Fig. 12.
TYPE
IN706 5.8V

+ISV
30mA

T 1: Primary 4 ohms,

OUTPUT

~~::~gr~2'4~~40~O ::~::
T2: ~~1~8~,O¥h~~~a;~~~si~~~2,
or equiv.

Speakers.: 4 ohms

Fig. IO-lntercom using CA3020 or CA3020A.
have typically flat gain-bandwidth response to 8 MHz. Although the circuits are normally biased for class B operation, only the output stages operate in this mode. If

proper dc bias conditions are applied, the output stages
may be operated as linear class A amplifiers.
Fig. 11 shows the recommended method for achieving
an economical and stable class A bias. The differentialamplifier portion of the CA3020A is placed at a potential

Fig. 1 J-Wide-hand video amplifier illustrating economical and stable class A bias of CA3020A.

above ground equal to the base-to-emitter voltage Vb. of.
the integrated-circuit transistors (0.5 to 0.7 vol!).' In this
condition, the output stages have an emitter...current bias
approximately equal to the base-to-emitter voltage divided

248

5,.F

.V

Fig. 12-Large-signa/-swing output amplifier using
CA3020 or CA3020A.
Either the CA3020 or the CA3020A may be used in this
circuit with power supplies below + 18 volts; the
CA3020A can also be used with B + voltages up to 25
volts with non-inductive loads. The circuit of Fig. 12 provides a gain of 60 dB and a bandwicth of 3.2 MHz if the
output transistor Q7 has a bypassed emitter resistor. With
an unbypassed output emitter resistor, the gain is 40 dB
and the bandwidth is 8 MHz. The output stage can deliver
a 5-volt-rms signal when a supply of + 18 volts is used.
For better performance in this type of circuit, the input
signal is coupled from the buffer amplifier Q 1 to the
input terminal 3 of the differential amplifier. This arrangement provides higher gain because the collector resistor of
the differential-amplifier transistor Q 3 is larger than that
of Q2. (This difference 'results from a requirement of
differential drive balance that is not used in this circuit.)
In addition. the terminals of the unused output transistor
Qa help to form an isolating shield between the input at
terminal 3 and the output at terminal 7. This cascade of
amplifiers has a single phase inversion at the output for
much better stability than could be achieved if terminal 4
were used as the output and terminal 3 as the input.
Fig. 13 illustrates the use of the CA3020 or CA3020A
as a class A linear amplifier. This circuit features a ..very

-----------------------------ICAN-5766
low output impedance and may be used as a line-driver
amplifier for wide-band applications up to 8 MHz_ The
circuit requires a O.12-volt peak-to-peak input for a singleended output of 1 volt or a balanced peak-ta-peak output
of 2 volts from a 3-ohm output impedance at each emitter.
The input impedance is specified as 7800 ohms, but is primarily a function of the external IO,OOO-ohm resistor that
provides bias to Q, from the regulating tcrminal I J.

distortion. The CA3020 and CA3020A can drive any transformer-coupled load within their respective ratings. Several
examples of typical applications are given below.
Fig. IS illustrates the use of the CA3020 or CA3020A
to drive a germanium power-output transistor to a 2.5watt level. Because the integrated circuit is required to
deliver a maximum power output of less than SO milliwatts,
an uobypassed emitter resistor can be used in the output
stage to reduce distortion. Sensitivity for an output of 2.5
watts is 3 millivolts; this figure can be improved at a
slight increase in distortion by reduction of the 4.7 -ohm
resistors between terminals 5 and 6 and ground.

1.5
TYPE
2N2869/
2N301
OR

NON-INVERTED

@I·o/.·~='--.CJOUTPUT

RCA

40022
WITH
HEAT SINK

INVERTED

1.5K

270

1 ~4-0HM

L....J'lSPEAKER

Fig. 13-Class A linear amplier using CA3020 or
CA3020A.
Fig. 14 illustrates the practical use of the CA3020 or
CA3020A as a tuned amplifier. This circuit uses dc biasing
similar to that shown previously, and has a gain of 70 dB
at a frequency of 160 kHz. The CA3020 or CA3020A
can be used as a tuned rf amplifier or oscillator at frequencies well beyond the 8-MHz bandwidth of the basic
circuit.

T1:

g:l~:;~ ~Tr~~~ag~~eJe,go~1 fl~~~~~;~t;eT~~~:~S~~ !f~_~~~s;
(entire secondary), or equiv.

T2:

~~~:rrl; i~~~~~~~~: ~oo~~~~;~r~~~~:~rt~-~o~.ent.

0.6

Stancor TP62, or equiv.

Fig. 15-2.5-wall class A audio amplifier using the
CA3020 or CA3020A as a driver amplifier.

~3K

r---~--~~~~----~--~--{l+35V
0.001 ~F

"'-O---.,JOUTPUT
TYPE
2N2869/2N301
OR
RCA 40050
500",r
WITH

70dS GAIN
AT 160 kHz

I~5il/1 B~~E::M
.,l::JSPEAKER

4.7K

TYPE
2NZB69/2N301
OR
RCA 40050
WITH
HEAT
SINK

TYPE

IN3754

Fig. 14-160-kHz tuned amplifier using the CA3020 or
CA3020A.
Driver Amplifiers_ The high power-gain and power-output capabilities of the CA3020 and CA3020A make these
integrated circuits highly suitable for use as drivers for
higher-power stages. In most applications, the full.poweroutput capability of the circuit is not required, and large
emitter resistors may be used in the output stage to reduce

T 1:

r~i;'edr:n~:~6~O:h~~~O~eOn~:r~t~p::;ee:~tl~rtT~0~de:ros~~ary
TR·454 or equivalent.

Fig. 16-1 O-wall single-ended class B audio amplifier
using the CA3020 or CA3020A as a driver
amplifier.

249

'ICAN-5766 - - - - - - - - - - - - - - - - - - - - - - - - - - - output transistors which must be mounted on a beat sink
for reliable operation. Idling current for the entire system
is 70 milliamperes from the 3S-volt supply. Sensitivity is
10 millivolts for an output of 10 watts.
Motor ControDer and Servo Amplifier. The CA3020 or
CA3020A may be used as a 40-t0-400-Hz motor controller
and servo amplifier, as shown in Fig. 17.

Because so little of the power-output capability of tbe
CA3020 or CA3020A is used, bigber-power class B stages
can easily be accommodated by selection of suitable output transistors and appropriate transformers.
Fig. 16 sbows a medium-power class B audio amplifier
in wbicb the CA3020 or CA3020A is used as a driver.
The output stage uses a pair of TO-3-type germanium

+18Vdc

+ 10 Vdc AT (a7mA IDLING

AT~mt~et~'GNAL

\52mA FULL SrlG_N_.L=-_ _~---_

_,

IOOIloF

~O",!

270
IW

270
IW

j-'
IW

J1Jl
15Vp-p

I~v\

120 VRMS
0.245 A
29W
AT 80-400 Hz

'flO V

IIrTo~~
l...LOAD

O.3V

22K
IW

470
IW

+~ -

Fig. J 7--Motor controller and servo amplifier using
CA3020 or CA3020A.

250

STANCOR
P-B358

Linear Integrated Circuits

[Rl(]5LJD

Application Note
ICAN-5831

Solid State
Division

Application of the RCA-CA3044 and CA3044VI
Integrated Circuits
in Automatic-fine-Tuning Systems
by

w. M.

Austin, H. M. Kleinman, and J. Sundburg

This Note describes the use of the RCA-CA3044
and CA3044V1 integrated circuits as automatic-fine-tuning (AFT) system components and discusses the advantages of integrated circuits in this application. The
CA3Q44V1 is electrically identicql to the CA3044, butis
supplied with formed leads for easier printed-circuitboard mounting; throughout this Note a reference to the
CA3044 implies a similar reference to the CA3044Vl.
The RCA-CA3044 is a special-function subsystem
integrated circuit that represents a second generation of

the AFT integrated circuit, the CA3034, that was designed specifically for frequency-control applications.
The CA3044, unlike the CA3034, h. '1 internal zenerregulated power supply that improves performance and

reduces system cost. It is designed to replace the
CA3034 in similar applications with only minor changes
in the sys~em circuit.

Circuit Description and Operation
The schematic diagram of the CA3044 is shown in
Fig.1; the use of the circuit in a typical automatic-finetuning (AFT) system for a color television receiver is
shown in Fig. 2. In such a system, the CA3044 provides
all of the signal-processing components needed (with the
exception of the tuned phase-detector transformer) to derive the AFT correction signals from the output of the
video-if amplifier. The other components of the system
provide signal coupling and power-supply decoupling as
required for proper signal processing in the video intermediate-frequency range.

The CA3044 integrated circuit can be considered as
the combination of four function a: blocks: a limiteramplifier, a balanced detector, a differential amplifier,
and a regulator. The 4S-MHz limiter-amplifier composed
of Q1 and Q2 is a differential amplifier that supplies a

11·68

251

ICAN-5831
peak-to-peak output current of approximately 4 milliamperes for input levels above the limiting threshold. The
use of a load impedance which does not exceed 2000
ohms guarantees an excellent limiting characteristic and
eliminates detuning effects caused by saturation of the
amplifier under worst·case conditions. In the system
shown in Fig.2, the load impedance at the center frequency is about 1800 ohms.

°

The diode matrix composed of 1, 02' 03 and 04
constitutes a balanced detector that converts the output
of the phase transformer to a filtered dc signal. Diodes
01 through 04 perform the detection function. Diodes
07 and 08 are always reverse-biased and serve as capacitors; they filter the output of the detector in conjunction with Rg through R12' Diodes 05 and 06 are included
to balance the parasitic diodes that exist between the
cathodes of 02 and 03 and the substrate_
Transistors ~, Q4' and Qs form a constant-current
driven differential amplifier that is directly coupled to
the output of the detector. The amplifier contributes
greatly to the high sensitivity of the system and, in addition, provides sufficient power to allow the use of a lowcost tuning element. The output impedance at either
output of the amplifier is approximately 12,000 ohms.
The zener-diode regulator comprising 010 and 011
provides the regulation necessary for a differential
post-detection amplifier output that is both stable ani!
independent of temperature and power-supply variations.
The junction of 010 and 011 is connected to a bias
divider network that assures correct base bias on both
differential-amplifier pairs.

10

DIODES D5 AND D6 ACT AS CAPACITORS AND ARE USED TO
BAUNCETHE DETECTCRSUBSTRATE CAPACITANCES.

Fig.l - Schematic diagram al the CA3044 and CA3044VI.

c"

6.
oF

LI -TRW No.237:\4
OR EQUIVALENT
L2. TRW No. 237:55
OR EQUIVALENT
LS- TRW No.23703
OR EQUIVALENT

Ouring normal operation, the proper dc bias for terminals 1,3, and 7 of the CA3044 is supplied through
terminal 6 and external rf coils, as 'shown in Fig.2, RF
bypassing is required both for terminal 6 and for terminal 10, which is connected througli the primary winding of the detector transformer to terminal 2.

Operating Characteristics
The CA3044 is designed to operate from supply voltages greater than the zener regulating voltage; because
the zener-diode voltage varies from 10.5 to 11.9 volts at
the 14-milliampere current-drain level, the supply voltage should be greater than 15 volts for proper regulation and circuit operation. The effect of all component
and power-supply tolerances on zener regulating current
must be taken into account in calculation of the value
of the series regulating resistor Rs shown at the top of
Fig. 2. In the typical circuit shown in Fig.2, power is
supplied to terminal 10 of the CA3044 from a +30-volt
supply through a ls0().ohm ,series dropping resistor.
The recommended value of Rs can be determined for
other supply conditions by use of the curves in Fig.3,
which show current at terminal 10 as a function of supply voltage.
An Rs load line may be drawn through
the safe operating area to show extremes of voltage and

Fig.2 - System diagram al a typical autamatic-linetun ing (AFT) applicatian shawing the CA3044
ar CA3044VI in use in a ca/ar- TV receiver.

252

current for normal variations in product. Safe operation
with proper regulation is achieved on any load line that
avoids the lower cross-hatched area and does not exceed' the allowable maximum dissipation as determined
for a given ambient temperature. The 'cross-hatched
area represents voltage-regulation dropout resulting from
an insufficient amount of zener-diode current.

ICAN·5831
36,------------r---,,---.-.-,---,
Pd-QEVICE INPUT
DISSIPATION AT

32

:3

~2.

~

TERMINAL No-10--t___I-i-__f-lf--+ __-I

V'O;.~~1=~E ~!.IO
-J--t---"+----t+--'-----l
I

~ i

"

~ 24f---t---+----l---Ii-----+f . . .I1·.t00."..

'""'6

4

"~

"'"

I

g20~---t---~--_+--_h----t----t---~

~

~16~---t----r~~~i~---

2

-50

;I

-25

0

+25

+50

+75

+100

+125

AMBIENT TEMPERATURE _·C

z

!'2~;;4;=;~;:;+~~;:;tr

....
....z

! 4r771"-h"'b7~""""7f7_+__+----t----I
"

10

II

12

14

SUPPLY VOLTAGE (VCC)-VOLTS

Fig.3· Curves lor determining the zener.diode regulating
voltage ot terminal 10.
The maxim~m value of Rs is· determi.ned by construction of a load line from the minimum supply voltage
nicc) to the upper right com,er of the cross-hatched
area. The largest standard resistor baving a maximum
value (including tolerance) smaller than the slope of
this line is selected. Dissipation under the worst· case
conditions of minimum Rs and maximum V CC must then

be checked to assure compliance with the maximum

device ratings.

The dissipation rating of the CA3044 is 830 milli·
watts at an ambient temperature of 250 C. At ambient
temperatures above 25°C, this maximum value must be
derated J>y a factor of 5.6 milliwatts per degree. Fig.4
shows the permissible dissipation of the CA3044 as a
function of ambient temperature. The worst·case dis·
sipation may occur at either a voltage or a current maximum.
The equation for total dissipation P d in the
CA3044 is
Pd = (VCC - ViOl
Rs

VlO

where V10 is the voltage at terminal 10 and VCC is
the power-supply voltage supplied through the series
dropping resistor Rs to terminal 10. The permissible
ambient·temperature operating range for th!, CA3044 is
_ 550 C to +1250 C.
Dynamic Performance

The system diagram of Fig.2 shows the CA3044 in
its function as rf amplifier, frequency discriminator, and
post-detection differential dc amplifier. The circuit
shown is a portion of a color television receiver in
which critical tuning is essential because of the presenceof the color subcarrier and its sidebands. The

Fig.4 - Dissipation rating 01 the CA3044 and CA3044V1
as a function of ambient temperature.
CA3044 AFT system provides a uniform and accurate
tuning reference. When the correction voltage develop·
ed at terminals 4 and 5 of the CA3044 is sufficient, the
system ,'Iocks on the picture-carrier intermediate frequency and holds the tuner oscillator within t25 kHz
of the picture carrier so that a high-quality picture is
produced' at all times. Operation within such a narrow
band of oscillator frequencies represents a color-reference deviation of less than 5 per cent from the ±500kHz color-subcarrier sidebands; this deviation is in
general far smaller than the amplitude and phase-change
errors that are introduced by other receiver and transmitter functions.
The system shown in Fig.2 can be used in a typical
color receiver. The sampling connection from the picture-if amplifier to the AFT circuit is made from the output of the l~st if stage directly to the input of the
CA3044 rf amplifier. The loading effect of the AFTsystem coupling circuit on the picture-if amplifier is
negligible and does not distort the if response. Unless
provision has been made to trap out the adjacent-channel sound carrier elsewhere in the circuit, such action
must be taken at the input to the CA3044. Trapping of
the adj acent-channel sound carrier is essential because
it may have sufficient amplitude to cause limiting at the
rf amplifier/limiter stage of the CA3044. The trapping
circuit, composed of L3 and C3 in Fig.2, also helps to
peak the picture carrier at 45.75 MHz while trapping the
adj acent-channel sound carrier at 47.25 MHz. To compensate for an if response that pI aces the picture carrier
at the SO-per-cent point on the if slope, the input trap
should be adjusted to peak the response above 45.75 MHz at
the input to the CA3044.
Proper dc biasing of the amplifier/limiter stage
composed of QI and Q2 requires that a small choke,
L 4 , be used to couple terminal 6 to terminal 7. The
common bias connection at terminal 6 is bypassed with
a O.OOI-microfarad disc capacitor. No form of external
dc connection should be made to either terminal 6 or
terminal 7.
The output load on the differential amplifier consists of the impedanc", of the phase-shift transformer

253

ICAN-5831
canprising Ll and L 2 . The differential-amplifier stage
assures symmetrical limiting above 100 millivolts at
the input of terminal 7. The primary of the phase-shift
transformer is typically tuned to 46.1 MHz as an I!dditional error-correction device to help peak the picture
carrier at 45.75 MHz. The secondary is tun"d to 45.75
MHz and symmetrically drives the double-balanced detector comprising diodes D 1, D2, D3, and D4 . The
detector diodes Dl through D4 minimize frequency shifting by symmetrically loading the discriminator transformer. Symmetrical loading is assured by diodes D5
and D6 , which are used as capacitors to balance the
inherent substrate capacitances associated with D2 and

'2.5 I-

CORRECT'ON _ CONTROL VOLTAGE

'0

>

The reference levels(A, B, C, and D) indicated on
the curves of Fig.5 and 6 refer to the narrow- and wideband control points expressed as a percentage of the
zener reference voltage at terminal 10. References A
and B are narrow-band (±25-kHz) control points at 85

CO~RECTlO~

CONTROL VOLTAGE

,

TERMINAL 4

.0

. 7.'
>

I
!:;
0

>

i!
!;
0

•

--

2.'

........

/'

./ ~
./'

0

- o.oso

I

CORRECT. ON
CONTROL VOLTAGE
TERMINAL ~
REF. A -

-0.020

0.B5
V.O

V

REF. B
....... 0.33
.... 10

-

0.010

45.750

0·010

0.020

J
0.030

INPUT FREQUENCY OEVIATlON- MHz

Fig.S - Typical narrow-band dynamic control voltage
character; stics.

254

'r

"

1/

0

\

2.'

-..• -

0

-

0.5
45.7&0
Q.!5
ItlPUT FREQUENCY DEVIATION -MHz

~~:3D_
V.O

,.S

Fig.6 - Typical wide-band dynamic control voltage
characteristics.

and 33 per cent of the terminal 10 reference voltage,
while references C and D are the wide-band (± 0.9-MHz)
control points at 75 and 43 per cent of the same voltage.
The dynamically controlled test circuit for measuring
performance in the recommended application circuit is
similar to that circuit and is shown in Fig. 7. The correction voltages from terminals 4 and 5 are applied to
R •A

·~~~~~--------~
____~•.~'~kr-______ +30Y
-

REF. C

REF. D

REF. B

=

~

QO~::3'3

-=

.8

or

I'H

L2

;GNAL
GENERATOR

I

6

o.oo•
IIoF

=
Ll d~~~G~~~ 6~'!B:OM:J:ICAL BANDWIDTH OM
L2

~

REF.C
0.75
V.O

...." T"K
•

I

1

-

'\

i...

,v

12.5

CORRECTION
CONTROL VOLTAGE
TERMINAL 5

~

~.

The error signal detected by the double-balanced
detector is filtered by the 6000-0hm resistors Rg. R1O'
Rll' and R12 and diodes ~ and D8 at the inputs to the
differential output amplifier composed of Q3 and Q4'
The differential output amplifier is compensated for all
temperature-change effects including those of the zenerdiode regulator. In the absence of an error signal, output terminals 4 and 5 are at a dc level of 6.5 volts; in
mistuning or frequency correction, the output level
varies from 33 to 85 per cent of the zener-regulated voltage over the ±25-kHz limits. Fig.5 shows the typical
narrow-band response of the system shown in Fig. 2;
Fig.6 shows the wide-band response. The curves shown
are characteristic of the Fig.2 circuit for an input rf
signal level of 200 millivolts rms at terminal 7. Both
narrow- and wide-band respons~ characteristics are a
function of the CA3044 limiting level. The narrow-band
crossover slope decreases and the wide-band response
becomes narrow as the signal level decreases.

,

TERMINAL 4

.J\:i~f~R:~ACsE~~~Fn~~!'!t~~I~

Ll:ORTRe'Q~i~~I:M:.3754

L~orI~~~,~~I::T~755

Fig.7 - Correction voltage test circuit lor the CA3044
and CA3044VI.
the tuning elements of the voltage-controlled oscillator
portion of the uhf and vhf tuners. These voltages may
be used single-ended and of either phase-polarity for
uhf oscillator control. The vhf oscillator may be controlled with a push-pull output to assure attainment of
maximum tuning range. The channel-tuning defeatswitch function is normally accomplished by shorting
the control-voltage terminals 4 and 5 together. For fil-

ICAN-5831
tering purposes and to protect the integrated circuit, it

Construction

is best to include a shunt capacitor and series resistor
between the tuning elements and terminals 4 and 5; in
Fig.2, lOOO-ohm resistors and O.OOI-microfarad feedthrough capacitors are used.

Fig. B' shows a circuit board containing the circuit
of Fig.2; Fig.9 is an unobstructed view of the printedcircuit board used. The location and orientation of the
discriminator transformer coils affect the over -all response of the circuit; therefore, their placement should
be given the greatest attention. Because the metal pattern must be taken into account in component placement,
some experimentation may be necessary to achieve the
best results. It is recommended that the circuit be
shielded to prevent radiation of the. 45.75-MHz signal.

(a)

(b)

Fig.9 - An unobstructed view of the top (a) and bottom
(b) of the printed circuit board used in Fig.B.

Fig. 8 ~ Printed circuit board containing the circuit of
Fig.2.

The circuit described in this Note has been duplicated many times with both hand-made and commercial
coils. Alignment has always been rapid and positive
and the performance extremely uniform.

255

ffilffiLJD

Linear Integrated Circuits

Solid State

Application Note
ICAN-5841

Division

Feedback-Type Volume-Control Circuits for
RCA-CA3041 and CA3042 Integrated Circuits
by

L. Kaplan
This Note describes feedback-type volume controls
for use with RCA -CA3041 and CA3042 integrated circuits in television receivers. In television sets using
these integrated circuits, the volume control is often
located remote from the amplifier. The long leads required in such a configuration sometimes pick up undesirable signals that, in turn, cause the system to
exhibit hum and noise at low volume levels. The proposed feedback-type volume control reduces hum and
noise pick-up by reducing the gain of the system rather
than the signal level" 'and thus eliminates the cost of
shielding the leads.
Types of Volume Controls
Fig.! shows a conventional or "losser" type of
volume control that is susceptible to hum and noise.
When the input impedance of the amplifier is high, the
input voltage Ei and the output voltage Eo depend on the
voltage division between resistances Rl and R2. The
gain of the amplifier is constant, but the input signal is
increased or decreased according to the potentiometer
rotation.

Fig. 7 - Conventional volume-control circuit.
Fig.2 shows the basic variable-feedback volume
control.
When the wiper arm of the potentiometer is
close to the input terminal, which has a signal input Es ,
the gain of the system is essentially the open-loop
gain Ao. As the wiper arm approaches the output terminal, the gain is reduced to 3. clcs,ed-!ccp value Ac
according to the following formula:
Ao

AC=l+~Ao
where

~

is the feedback factor.

3-70

256

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ICAN-5841
CA3041 and CA3042 integrated circuits, typical values
encountered indicate that the expression is dominated
by the transconductance gm' Substitution of typical
values in Eq.(3) shows that the minimum-voltage gain
of a 0.25-megohm volume control is of the order of 98 dB
and 136 dB below the maximum gain for the RCA-CA3041
and CA3042 circuits, respectively, which is welI below
the normalIy acceptable residual levels.
Loudness Contouring

Fig_2 - A variable-feeclback volume-control circuit_
Feedback Control
Fig_3 shows the equivalent circuit of a feedback
control. Gain control in this circuit is provided by the
potentiometer, which varies according to the resistance.
ratio of Rs and Rf. The system gain Eo/Es for this
circuit can be described by the folIowing equation:

G(1-~)
s

Eo

~ =(Gs + Gi) (1 + ~~ ) + gm + GL

(1)

where Eo and Es are the output and input signal levels,
respectively; gm is the transc(~mductance of the amplifier
device; and Gs , Gf, Gi, and GL -are the conductances of
the source, feedback, input, and load resistances,
respectively.

"

Zi (max) =

~

When the control is set for maximum gain (Rs = 0;
system reduces to the folIowing expression:

= (0), the

= Gf -

gm
Gf + GL

= RL

- gm RfRL
RL + Rf

(2)

At _the minimum-gain setting, the gain of the system
is given by

Eo
Es

1+

~~

~

1 + GLRv

(6)

Gi + GL + gm + Gi GLRL

Fig.3 - Equivalent circuit of a feeclback volume control.

Eo
Es

1

Gi + GL + gm
At maximum volume, the input impedance Zi (max) changes
to the folIowing expression:

T

Rf

-'N

Gs

If the total resistance of the volume·controI potentiometer
is denoted by Rv , the input impedance at minimum volume Zi (min) is given by
~~W=~+

RS+Rf

RS

A desirable feature of audio systems in which lowfrequency overload may be encountered is- bass rolI-off
at high volume levels. The low-frequency overload may
result because of limited amplifier power output or an
inadequate loudspeaker. In either case, an unpleasant
"honking" can be avoided by use of variable low·fre·
quency cut-off. This cut-off is achieved by use of the
characteristics of the circuit shown in Fig.3. The input
impedance Zi of the system, as shown in Fig.3, is
as folIows:

G~ (Gi+GL +~)

The resistance Rf of Eq.(2) and the resistance Rs of
Eq.(3) are the same because they represent the total
resistance of the volume-control potentiometer. If the
value of Rf in Eq.(2) is made large with respect to the
load resistance RL, the gain and maximum volume reduce
to the familiar expression gmRL'
Eq.(3) shows that the gain of the system is not
zero at the minimum volume setting. For both the RCA-

Thus, the input coupling capacitor can be selected to
rolI off at the desired frequency at maximum volume with
assurance that at lower volumes the lower frequencies
will be enhanced. With typical device parameter values
of the CA3041 or CA3042, the input impedance reduces to
approximately 10,000 ohms at maximum volume. When
the CA3041 and CA3042 are used in the circuits shown
in Figs.4 through 8, the input impedance at minimum
volume is essentially the resistance of the volume control used.
Fig.4 shows a diagram of a feedback-type volumecontrol circuit for the CA3041. This circuit offers enhanced power output and gain as compared to a conventional "losser" type of volume-control-circuit such as
that shown in Fig.s. At a carrier frequency of 4.5 MHz,
the circult provides one watt of power output at ±8.5-kHz
deviation. In this circuit, the coupling capacitor and
the resistor to the grid of the output tube are eliminated.
This arrangement offers cost savings because it uses
fewer parts and is easier to assemble.
Fig.6 shows a circuit in which the CA3042 is used
in a feedback control. The circuit shown in Fig.6 can
provide 2 watts of audio power output at ±7-kHz maximum

257

ICAN-5841
+140V DC

Fig.4 - A feee/back volume-control circuit
for tire RCA-CA3041.

Fig. 7 - A conventional volume-control circuit
for tire RCA-CA3042.

14

+140VOC

tl40Y DC

330HMS

,F1
0.1

lOOK

Fig.8 - A low-cost feee/back volume-control circuit
for tire RCA-CA3042.

Fig.S - A conventional volume-control circuit
for tire RCA-CA3041.
14 5

+140

CA304Z

r r-----rI
I

I

I

::

I

I

I

I

I

I

:

:
I

'l~'

330K

SOOK

v DC

frequency deviation from the 4.S-MHz carrier. This circuit costs less than a conventional circuit such as that
shown in Fig.7 because it -uses smaller C oopling capacitors.
Fig.S shows a very-low-cost circuit that provides
essentially the same performance as the circuit shown
in Fig. 6.
An additional capacitor and resistor are
eliminated in this circuit. Although a steady-state current flows through the volume control, it is limited to
about 1.5 microamperes under worst-case conditions.
Because of the small but finite current flowing through
Ri, the current shifts ip the output transistor as the
control is rotated from mi:-;,imum to m::n:,imum. The current
deviation is ±6 milliamperes maximum about the nominal
value, and the flow is in a direction that reduces current
at low volume and increases it at high volume.

Taper.

Fig.6 - A feee/back volume-control circuit
for tire RCA-CA3042.

258

Because the gain of the system, rather than the
input signal, is varied, the volume taper of a feedback

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ .ICAN.5841
control is characteristically different from that of a
conventional "losser" type of control. Therefore, Eq.(1)
can be rewritten as follows:

(7)

where the term Rf of Eq.(1) is replaced by (a Rv) and
Rs is replaced by (1· a) Rv. The gain then becomes a
function of the term a, which expresses the taper of the
control. Curves of this equation for various tapers are
shown in Fig.9.
The exponential functions of the taper factor, a,
. .actually define the familiar logarithmic tapers; however,
.. they are arranged counterclockwise so that, as the con-

hoI is rotated clockwise, the resistance increases very

rapidly at first and th~n more slowly toward maximum
resistance. A linear taper (bottom curve of Fig.9) exhibits almost a step-function response, while the parabolic taper is slightly smoother. Clockwise log tapers
fall below the linear-taper curve, and are thus totally
unacceptable. The controls which are probably most
satisfactory are those which correspond to very-lowpercentage counterclockwise log tapers. *
• The percentage taper is calculated

8S

follows:

R(measured from start of control to wiper arm)
Total resistance
x 100,

The measurement is taken at So-per-cent rotation of the control.

.

'.Or--r.-.".!L"'---'---"-"--r--r--'---r=~
0.8

f--t--t--+---t---t---t--

0.21--+--+--t--

Fig.9 - Goin

OS 0 function of rotation for various
types of potentiomet.rs.
.

259

OOOBLJD

Linear Integrated Circuits

Solid State

Application Note
ICAN-5977

Division

Principal Features and Application,s of the
RCA-CA3040 Integrated-Circuit Wideband Amplifier
by
W. M. Austin
The RCA-CA3040 is a monolithic integrated circuit
designed for use in wideband video and intermediatefrequency amplifier applications to frequencies as high
as 100 MHz. The device, offered in a 12-pin TD-5 package, features, a balanced differential voltage gain of 37
dB with less than 1 dB of imbalance and provides a
typical 3-dB bandwidth of 55 MHz. Useful voltage gain
is well beyond the 3-dB frequency roll-off point which,
in some applications, extends to frequencies up to 200
MHz. Additional features of the CA3040 include temperature compensation for gain and voltage over the -55
to 1250 C temperature range, a choice of zero or ISOdegree phase shift from input to output terminals, and
high input and low output impedance characteristics
over a broad bandwidth. This Note -describes the operation of the CA3040, its electrical characteristics 6.&"10
ratings, and its primary application as a wideband amplifier.
CIRCUIT DESCRIPTION

Fig. 1 shows the schematic diagram for the CA3040
circuit. The heart of this circuit consists of two differentially connected cascode amplifiers that form a so-

260

called "differential cascode" amplifier. The transistors Q3 and Q4 are common-emitter amplifiers which are
connected at the emitters to form the differential transfer junction. The common-base transistors Q5 and Q6
are emitter-driven from the common-emitter transistors
Q3 and Q4' respectively, to form two differential-cascode amplifier pairs.
Each common-emitter amplifier is buffer-isolated
from the input terminals by an emitter-follower stage for
high input impedance and minimum co-channel phase
pulling. Each common-base amplifier of the cascode is
coupled to the output terminals by use of an emitterfollower stage forlow impedance at the output terminals.
When the signal flow through the device is from
terminal 4 to terminal 12 and from terminal 6 to terminai
10, there is a ISO-degree internal phase shift; when
signal flow is from terminal 4 to terminal 10 and from
terminal 6 to terminal 12, the phase shift is zero. Fig. 2
shows a signal-flow diagram for the former case. The dc
feedback loop shown is a bias-selection and temperaturetracking network. The bias network consists of reference diodes 01 and 02' transistor Q9' and resistors R3'

____________________________________________________________ ICAN-5977

RI

RIO

R2

L32K

'L5K

1.32K

a.
12

10

"

SUBSTRATE

SUBSTRATE
ALL RESISTORS IN OHMS

Fig. 1 - Schematic diagram of the CA3040 wideband
amplifier.

1 - c,:sCODE -

-

-

-

l

I

I

I

I

I

I
I
L ________ J

EMITTER-

FOLLOWER
AMP:

I

-cP-

I

I

MODE-

CONTROL
CIRCUIT

, - CASCO-;- -

I

---l
I
I
I

I

I

I-%-

I

L __ -______ ~

Fig. 2 - Signal-flow diagram of the CA3040.

261

ICAN·5977
R4 , R7' R8 , Rg, and RlO. The bias network selected
by proper connection of terminals 3, 7, 8, and 9 determines the "mode" of desired temperature tracking.

terminal 8 is externally connected to the substrate terminals 5 and 11. In this, mode, the ac gain is extremely
stable (typical variation is 0 dB); the dc variation at the
output terminals is ± 0.8 volt.

BIAS MODES

For most applications, the constant-voltage bias
mode is preferred. This mode provides typical ae-gain
variation of less than 0.5 dB over the range from rOOm
temperature (250 C) to 850 C ambient. The dynamic range
in this mode remains high, and the circuit exhibits less
'distortion and greater common· mode range for largesignal output swings. Finally, this mode requires one
less terminal connection and provides a less complex
layout design tban that required for tbe constant-gain
circuit.

The dc bias-point stability or ac gain stability of
the CA3040 is maintained over the temperature range of
·55 to 1250 C by the choice of two bias modes. These
bias modes are selected by proper connection of the
transistor Qg biasing network. Fig. 3 shows the bias
modes for (a) constant voltage and (b) constant gain.
V'2
,----QOUTPUT

Botb modes bave identical power-supply require-·
ments, as illustrated in Figs. 3 and 4. Fig. 3 sbows
tbe use of a single 12-volt power supply, and Fig. 4

OUTPUT

INPUT

Vee
+12v
ALL RESISTORS IN OHMS.
ALL CAPACITORS IN MICROFARADS

(a)

O~
OUTPUT

(a)

+6V -6V
Vee
VEE

INPUT

Vee
+12V
ALL RESISTORS IN OHMS.
ALL CAPACITORS IN MICROFARADS

(b)

Fig. 3 - Bias configurations for the CA3040 using a
single 12·yolt power supply: (a) constant-voltage
bias; (b) constant.gain bias.
In the constant·voltage bias arrangement, terminals
3 and 8 are open, and terminals 7 and 9 are externally
connected. This circuit yields a constant-voltage output for applications that use dc coupling to succeeding
stages Or that require maximum dynamic range over the
specified temperature. DC voltage variation in this
mode is less than 0.1 volt over the entire temperature
range; ac gain v';"iation is ± 2.0 dB.
In the constant· gain bias arrangement, terminals 3
and 9 are externally connected, terminal 7 is open, and

262

(b)

Fig. 4 - Bias configurations for the CA3040 using bal.
anced dual (±6 .volt) power supplies; (a) constant·
voltage bias; (b) constant-gain bios.
shows balanced dual positive and negative Govolt power
supplies. In Fig. 3(a) and 3(b), tbe inputs are biascoupled to terminal 1, which is a reference to the center
point of the power supply. Altbougb tbis connection is
most commonly used to maintain the common-mode range,

any dc supply or "stiff" bleeder (at one-half the powersupply voltage) may be used. It sbould be noted tbat
terminal 1 sbould not be direct·coupled to any external

_________________________________________________________ ICAN-5977
circuit except as a bias source;

otherwise, the input

transistors or the temperature-compensation character--

istic will not remain within the limits.

OfARACTERISTICS AND RATINGS
The high-frequency capability of the CA3040 is a
characteristic of the advanced design that has been developed in the second generation of monolithic integrated-circuit devices. The following are typical performance characteristics of the CA3040.
Fig. 5(a) shows gain as a function of frequency for
the CA3040. The test circuit used to obtain this curve
is shown in Fig. 5(b). The 3-dB bandwidth is typically
55 MHz and the minimum is 40 MHz at either differential
output when terminal 4 is driven from a single-ended
50-ohm source. At 1 MHz, using a 63-millivolt output
level, imbalance is not greater than ± 1 dB. In contrast

Fig. 6(a) shows the input resistance and capacitance characteristics of the CA3040. (The input resistance RIN is plotted as conductance GIN because the
resistance magnitude approaches infinity at approxi...
mately 22 MHz.) The test circuit used to obtain these
data is shown in Fig. 6(b). These curves were obtained

lNJUT cAPk'TAJcE

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CONOUJTANC~

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-t'o

-....J..

NOTE: SCALE
TO 300,.mho
FOR DASHED
LINE ONLY

6

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2
fREQUENCY-MHz

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200

(a)

COLLECTOR SUPPLY VOLTS (VCc)·+12
AMBIENT TEMPERATURE (TAJ-ZS-C
SINGLE-ENDED INPUT AND OUTPUT
MODE A SWITCH CLDSED,FIG. 51b)

40

Rs-son,RL-IK

~

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~ 30

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ii

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20

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468

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10

2

• OS

100

2

• OS

1000

(a)
O.l~F

V,2

rilH--QOUTPUT

V,O
OUTPUT

+6V

*FERRITE BEADSFERROXCUBE No.

56-590-658-311.
OR EQUIV.

FREOUENCY-MHz

Vee
+,12V

·VARIABLE CAPACITANCE (O.5-I.OpF) ADJUSTMENT FOR
EQUAL 3-dB BANDWIDTH AT AMPLIFIER OUTPUTS,
TERMINALS 10 AND 12. (b)

Fig. 5 - (a) Voltage gain as a function of frequency
and (b) test circuit of CA3040.
to the more common specification of minimum gain at
high frequency, the performance of the CA3040 is given
in terms of flat bandwidth relative to the I-MHz-gain
test point.

.6V
+12V

(b)
Fig. 6 - (a) Input impedance char!,cteristics and (b)
test circuit of CA3040.
with the output terminals shorted and by use of the
constant-voltage bias configuration. Although this form
of bias has a second-order effect on the input and output capacitance, the input and output capacitance and
conductance values for the circuits of Figs. 3 and 4 do
not change appreciably from those shown in Fig. 6(a).
The negative value of input resistance remains high over
the high-gain region and has sufficient magnitude (several
thousand ohms) at 150 MHz so that the amplifier remains
stable for practical values of the input matching impedance.
From 1 to 10 MHz, this resistance remains
approximately 150 kilohms. The input capacitance C lN
of the CA3040 is approximately 2.2 picofarads and remains relatively constant over the useful frequency
range.
Fig. 7(a) shows the output resistance and output
capacitance of the CA3040 amplifier as a function of
frequency. The test circuit used for these measurements
is shown in Fig. 7(b). The output resistance of the cir-

263

ICAN-5977 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
ciut is approximately 125 ohms at low frequencies and
gradua!ly rises to 215 ohms at 100 MHz, but decreases
again to 200 ohms at 150 MHz. Although a lower output
impedance (50 ohms or less) is more desirable, the higher

stant-voltage bias circuit shown in Fig. 4(a). The gain
and frequency response of the amplifiers are equivalent.
The 1-kilohm resistors at the input stage of the circuit
of Fig. 5(a), however, produce a 2.. dB increase in the
noise figure when the CA3040 is matched for maximum
power transfer. For low-noise applications, therefore,
these shunt-biasing resistors should be replaced by lowloss input matching circuits which can include rf
chokes, a transformer, or inductive-capacitive input
circuits. It is important that the dc resistances of the
two stages remain equal. An unequal de voltage drop
across the bias network produces a large- dc offset at
the output.

output impedance results in greater temperature-

stable gain. When necessary however, the output impedance can be reduced by addition of another emitterfo!lower stage. Even when this stage is directly coupled
to the output, it has little effect on the dc stability for
bias-current drains less than 0.1 milliampere.
Fig. 8(a) shows the 30-MHz noise figure as a
function of source resistance in the test circuit presented in Fig. 8(b). This amplifier is similar to the conI

O.OOl~F

40

~.

20

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-20
-30

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200~

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30

I80

~

I 60

~

OUTPUT CAPACITANCE

"

C~I 40 z

1\

-

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~

~

,/f--'

I20 ~
I00 ~
80

4

(a)

4

B 10

6

6

•

100

•o

200

FREQUENCY-MHz

5o
*FERRITE BEAD=

FERROXCUBE No.
56-590-658-38,

(b)

+12

OR EOUtv.

Fig. 7 - (a) Output impedance characteristics and (b)
test circuit of CA3040.

*

+6v

16

12

~

t

...

z

II:

:>

;;:
~

\

NOISE-FIGURE

\ '----

_L:~~~~:STRUMENT

,
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l_t~
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,
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___;
,

REQUIRED FOR
TERMINAL 4
BIAS CURRENT.

200

400
600
BOO
SOURCE RESISTANCE (RSI-OHMS

1000

*FERRITE BEADS.
FERROXCUBE No.

56-590-658-38,
OR [QUIY.

Fig. 8. - (a) Typical 30-MHz noise figure and (b) test
circuit of CA3040.

264

4

t--@-i

NOTE:
DC PATH

is
z 4

(a)

,_
>

_ _ _ _ _--.:...._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ICAN-5977
Fig. 9(a) shows the IIf noise characteristics of the
CA3040 in the test-amplifier circuit of Fig. 9(b). The
curves represent different values of source resistance.
The bandwidth of the test amplifier circuit is restricted
to adapt the circuit to a Quan-Tech noise analyzer. The
equivalent input 1/£ noise is expressed in nanovolts per
~'OO
~

?2~ 0
~200

OJ
~

~I~

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100

10

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500

0
0.01

NF-ZO LOG 1O

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0.1

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. ..

,

I
FREQENCY- klU

EN
IZS.6KIOI2IRSlI/2

. .. , . ..
10

The CA3040 has a linear phase-shift characteristic.
Fig. 10 shows the amplifier phase shift from input terminal 6 to output terminal 10 and the differential phase
between outputs over the frequency range from 1 to 60
MHz. The test amplifier of Fig. 5(b) was used to obtain
the data for these curves. The resistive portion of the
output-impedance load in Fig. 5(b) consists primarily of
the I-kilohm resistors. The capacitive load consists of
all essential circuitry as well as BNC connectors and
phase-meter input probes that represent approximately
8.5 picofarads. Any imbalance from 180 degrees of differential phase at the output terminals remains small in
comparison to the reference input-to-output phase shift
and is typically less than 1 degree at frequencies up to
50 MHz. Fig. 10 shows the differential output phase
'40

OIFI'ERENTI~\ ~

OUTPUT PH~SE

100

(a)

-t-

+12V

AMPLIFIE~ lHAS~

N~'FT (~ERM.IOI

f\
Eo

8 10

I

I

1\

FREQUENCY-MHz
TO POST

9

470p'

T::{~I=T~CH
p:LYZER

470pF'

*FERRITE

BEAD.
FERROXCUBE No.

100 OHMS

56-590-658-38.
OR EQUIV.

(b)

Fig. 9 - (a) Equivalent input noise voltage as a function of frequency oncl (b) test circuit of CA3040.
square root of the frequency. The limiting low-frequency
I/f noise approaches 125 nanovolts per J'iiZ at 10 Hz
and drops to approximately 25 nanovolts per..IHz at 100
Hz. Above 200 Hz, the noise component is primarily
shot noise.

Fig. 10 - Amplifier phose shift ancl differential output
phose as a functio~ of frequency lor the CA3040 test
circuit of Fig. 5(b).
with tenninal 10 given as the reference phase. The imbalance exists because the feedthrough capacitance
from tenninal 10 to terminal 9 is greater than that from
terminal 12 to terminal 9. The constant-current transistor (Q9 of Fig. 1) amplifies this unbalanced stray capacitance coupling. A fundamental correction for phase
can be made by adjustment of the output-capacitance
load. In Fig. 5(b), a variable capacitance Cf is used
between tenninals 9 and 12 for this purpose. The addition of Cf makes possible adjustment of the output
signals for phase and gain balance at tbe high -frequency
roll-off point.

The noise figure NF is related to the noise voltage
EN as follows:

Fig. 11(a) shows the frequency response of the
CA3040 for various values of load resistance. The test
circuit used for these measurements is shown in Fig.
11(b). This amplifier is biased from a balanced dual
power supply, but is otherwise similar to the circuit of
Fig. 5(b). The curves are valid for either method of
biasing.

where EN is the noise voltage in volts per ./HZ:" K is
Boltzmann's constant (1.38 x 10-23 joule/oK), T is the
temperature in degree~ Kelvin, and Rs is the external
source resistance in ohms.

The low -frequency portion of the curves of Fig.
11(a) shows the decrease in gain with decreased load
resistance which is characteristic of the 125-ohm output
resistance. The higher-frequency range shows the reduction in bandwidth as the load resistance is decreased.

265

ICAN-5977 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

.

40

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6dB LOCUS

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_NC

INPUT
FROM
4

2

(a)

• • '0

4

2

• • 100

fREQUENCY-MHz

COUPLED
OUTPUT:Il8.5pFLOAD

50-OHM

SIGNAL
GENERATOR

f-O

o.l,...r

O.OOI",F

+6.
0-1

F

(a)

*

*F[RROXCUSE
FERRITE BEADS·
No.

-6.

56-590--658-38,
OR [QUIV.

40

"l
BNC COUPLING

TO BOONTON
RF VOLTMETER
OR [QUIY.

i'"

30

~I:
I'i

20

z
~

10

;1:-

--

\

\

O.II&F

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O.OOl"F

(b) ,

o.l,..r
(b)

*

-6.

*rERRITE BEADSFERROXCUBE No.

56-590-658-39.
OR [QUIV.

Fig. II - (a) Frequency response curves and (b) test
circuit for CA3040.
This output ch1Jracteristic is typical of emitter-follower
circuits and is caused by a reduction in transistor beta
at higher frequencies.

WIDEBAND AMPLIFIERS
In the basic amplifier circuit of Figs. 5(b) and 11(b),
the bandwidth of the CA3040 may be increased by use of
conventional RL and RC peaking, as well as feedback
COru'L'UOn, at the input and output stages.
Fig. 12(a)
shows a typical wideband amplifier configuration using
the CA3040; Fig. 12(b) shows its frequency response.
The circuit has a wide-band series-peaked bandwidth
greater than 90 MHz at the 3-dB point and greater than
85 MHz to within ± 1 dB of gain variation. In the circuit
of Fig. 12(a), care is taken to avoid "over-peaking" of
the input at higher signal levels so that limiting and
distortion effects are minimized.
The frequency-response curves shown in Fig. 12(b),

266

6

8 10

6

8 100

200

FREQUENCY- MHz

Fig. 12 - (a) Typical CA3040 wideband-amplifier circuit with series input pealcing and (b) frequency response characteristic.
as well as in Figs. 5(a) and l1(a), were obtained with
conventional output circuits that contain BNC connectors coupled to the rf voltmeters and produce a total
capacitive load of approximately 8 to 9 picofarads. The
curve of Fig. 5(a) shows a roll-off characteristic of approximately 12 dB per octave in the 100-t0-200-l\lHz
range which is the result of capacitive loading of the
cascode and emilter-follower output stages. These output stages may be peaked for partial compensation of
the bandwidth loss that results from emitter-follower
output loading. The remaining loss in bandwidth, however, results from internal circuit effects and is less
easily corrected.
Fig. 13 (a) shows a wideband-amplifier circuit
that produces 50 dB ± 1 dB of gain up to 53MHz, as
shown by the curve of Fig. 13 (b). The curve shown
is for an input--=>~
180
OHMS

50
OHMS

=

(a)
60

40

20

o

(b)'

""
6

I
I

I{

GAIN-BANDWIDTH CURVE
FOR I.OmV(rms) INPUT
SIGNAL -0. 316Vtrmsl

OUTPUT

8 10

I

I

I II

2

6

Fig. 13 - (a) 58-MHz wideband amplifier including post
amplifier and (b) frequency response characteristic.

\
8 100

200

F'REQUENCY- MHr

267

ICAN-5977

Iicated by the fact that y-parameter data are applicable
only at the discrete frequency at which they are taken.
In view of these factors, the characteristics of the CA3040 are guaranteed to have a reasonable stability margin through evaluations in test circuits and by integrity
of design. Poor circuit design or improper layout, however,can reduce the stability margin so that oscillations
can possibly result.
The differential-amplifier configuration of the CA3040 offers the advantage in wldeband amplifier applications of neutralizing its own feedback. For this reason
the circuit layout and printed-board pattern should be
designed with a high degree of symmetry.
For stability purposes, terminal 9 of the CA3040
should not be bypassed because common-base oscillations

may result in the constant-current transistor Q9' This
effect, however, may be used to advantage in oscillator
and mixing applications.
For some applications, such as wideband if amplifiers, it is desirable to limit the high-frequency characteristics of the CA3040. In this case, series resistors
in the base input leads of transistors cq and Q2 are
recommended. Resistances of 10 to 100 ohms in series
with terminals 4 and 6 not only limit the bandwidth but
~so

act as parasitic suppressors.

CONSTRUCTION

The basic construction of the CA3040 generally
follows the usual recommendations for high-frequency
wideband amplifiers. ,Figs. 14 and 15 illustrate the

Fig. 14 - Printed-circuit board for the CA3040 wideband
amplifier circuit of Fig. 5(b) using constant-voltage bias
configuration and a single 12-volt power supply:,(a) top
view; (b) bottom view.

Fig. 15 - Printed-circuit board for the CA3040 wideband
amplifier circuit of Fig. 8(b) using constant-qain bios
configuration Dnd balanced dual (±6-volt) power supplies; (0) top view; (b) bottom view.

268

- - - - - - - - - - - - - - - - - - - - - -_ _ _ _ _ _ _ ICAN-5977
printed-board layout used for wideband appFc~tions of
the CA3040. Fig. 16(a) is an exact-scale photograph of
the printed board used in the circuits of Figs. 14 and
15. Figs. 16(b) and 16(c) show modifications in this
hoard made to accommodate the different connections
for the single 12-volt and balanced dual 6-volt power
supplies.
Fig. 16(c) shows an alternate mounting arrangement for the CA3040 in which lead connections are
made through individual holes in the printed board. The
printed board layout is intended for use with the constant-voltage bias connection in which terminal 7 is
connected to terminal 9. Before the CA3040 is mounted,
the pins for terminals 3 and 8 are cut off because they
are not used in these circuits.

The balanced dual-power-supply circuit of Fig. 15
requires greater attention to layout because of the additional difficulty in bypassing the negative supply. The
emitter circuits, as well as the substrate and case, of
the CA3040 are common to the negative supply terminals
5 and 11_ This arrangement permits the negative powersupply source impedance to become a common element

for feedback. For wideband applications, however, this
arrangement presents a problem for bypassing these
circuit elements. The series lead inductance L in microhenries is given by
L = 0.005l&.3 10glO

E~i .{).7~J

J.

where
is the lead length and d is the lead diameter,
both in inches.

(a)

Because this inductance is appreciable for some
values of bypass capacitance, the circuit may resonate
within the bandwidth of the amplifier. This resonance
always exists and, therefore, requires extensive bypassing. As a result, the use of two and sometimes three
capacitors at a bypass point is necessary for adequate
bypassing of all frequencies in the pass band. In addition, the use of ferrite beads, chokes, and resistors
may be necessary for suppression of "ripples" or "suckout" in the pass band. Because of these problems a
knowledge of the high-frequency self-resonant characteristics of passive circuit components up to frequencies
near the unity-gain point of the amplifier device is
essential. For the CA3040, this frequency may reach
800 MHz_
As an added precaution in minimizing inductance,
the leads of the CA3040 should be. trimmed to the minimum practical length. Lead trimming, forming, and
soldering, however, should be performed at least 1/32
inch from the case to avoid damage to the package_
Each lead of the CA3040 is inserted through a hole
which has a sufficiently large diameter so that the lead
just passes through without forcing. The leads are then
folded out and soldered to their respective connections_
Leadless disc capacitors are used with the circuit board
slotted at the closest bypass point_ The capacitors are
soldered directly in vertical position to the printed board_

(c)

Fig. 16 - Printec/-circuit boarc/ usec/ for the construction
of wic/ebanc/ amplifier circuits shown in this Note:
(a) exact-scale photograph; (b) moc/ifications requirec/ to
accommoc/ate connections for the single 12-volt C/C
supply; (c) moc/ifications required to accommoc/ate connections for balanced dual 6-vo/t supplies_

Fig. 17 shows the constructed wideband post amplifier in which most parts are easily identifiable_ Because the case and collector lead of each 2N5187 transistor are connected together, direct bypassing to the
case was used in this particular laYbut to reduce lead
inductance in the collector circuit of the 2N5187_ Leadless disc capacitors are used at critical bypass points.
The terminal tie-points are teflon-insulated stand-offs.
Input and output are shown as BNC connectors coupled
by O.I-microfarad disc capacitors_ The output cable and
50-ohm load of Fig. 13(a) are nut shown.

269

ICAN-5977

DISC CAPACITORS

(CASE BYPASS)

Fig_ 77 - Photograph 01 constructed post amplilier 01
Fig. 73(0).

270

OO(]5LJl]

Linear Integrated Circuits

Solid State
Division

Application Note
ICAN-6022

An Ie for AM Radio
Applications
by

L. Boor
RCA Solid State Division
Somerville. N. J.
An integrated circuit intended to be used in AM radio
applications can assume many forms depending on the class of

INTEGRATED CIRCUIT DESCRIPTION

service in which it is to be used. The RCA-CA3088E is designed
for use in high·quality AM superheterodyne receivers. It
provides the basic functions of signal conversion, if amplifica.

The schematic diagram of the RCA-CA3088E is shown in
Fig. 1. The correspondence of terminals to functional section
within the device is shown in Table I. The various stages are
designated in tenns of AM-radio functions because the primary
functions of the device are so intended; the AM-radio
terminology is continued throughout the paper for the sake of
continuity.
The heart of this integrated circuit is the second if
amplifier-detector combination. The if amplifier consists of Q7,
Q9 and QIO with their associated components. Q7 and Q10 are
emitter followers which isolate the gain stage, Q9. The supply
voltage to the collectors is regulated by the zener diode, Z I.
The quiescent operating point is stabilized by connecting the
emitter or QIO to the base orQ7 through R14. The connection
is made by externally tying pin 7 to pin 8 through a suitable
impedance. For de stabilization, pin 7 should be at ac ground

tion, detection, and audio preamplification sufficient to drive a
separate power amplifier. Auxiliary functions supplied are: a
supply-voltage regulator, internal age for the first if amplifier,
3gC voltage for an optional external rf stage, and an amplified
signal to drive a tuning-meter output. This device is housed in a
l6-lead dual-in-line plastic package.
While the circuit design is intended for use in commercial
AM broadcast receivers, it is equally suited for use in most AM
receiver applications up to a frequency of 30 MHz. In addition,
since most functions are externally accessible this device is also
a general-purpose amplifier array. The possible number and
variety of uses of the CA3088E are largely a function of the
needs and imagination of the designer.

+---......- - - { 9
RI
6.8K

ALL RESISTANCE
VALUES ARE IN

OHMS

RI7
200

BIAS
SUPPLIES

AUDIO
AMPLIFIER

Fig. 1 - Schematic diagram of the RCA CA3088E.
12-72

271

ICAN-6022 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

TABLE I. CORRESPONDeNCE OF TERMINALS
TO FUNCTION

Terminal

Function

Converter

1.2.3

First I F Amplifier

4.6

Second IF-Amplifier-Detector

7. B. 9.10

AGCAmplifier

11.13

Tuning-Meter Amplifier

12

Audio Preamplifier

14.15.16

potential. otherwise signal feedback will modify the basic
characteristic of the stage. The output of Q lOis fed directly to
Q12, an emitter follower operating at a quiescent current of
approximately 100 microamperes. This stage becomes a
detector by connecting the proper filter circuit to the emitter;
the emitter is brought out on pin 9. The rectified emitter
current develops a voltage at the junction of R20 and R21 ; the
junction is connected to the bases of the age and meter
amplifiers.
QJ 1 is an emitter fol1ower normally. used to drive a tuning
meter at pin 12. QI I is biased off with no,signal and will deliver
approximately 150 microamperes with a maximum signal as
indicated in the curve of Fig. 2.
Q8 is an age amplifier intended to control an optional
external rf amplifier. Collector voltage, applied through a load
resistor to pin 13, provides a decreasing voltage at pin 13 with
increasing signal. The voltage drop across diode D5 must be
overcome by the drive voltage to the base of Q8, thus
introducing a delay in the application of gain control to the rf
stage. The age curve of a typical circuit is shown in Fig. 2.

-sf--+---+-"""" --+--Ic-~'OO

LID
g

.---1----1.00

~

~
~
§

!:i -15f--+--+-->,I--+-++--1200 ffi
g
~

w

-20f--+-", ''l>''04-'. .i---t'---jIOO

"

~

§
~

-250
· J-<=-l'--,!-2--!.c--.+--+----!.0
INPUT SIGNAL TO PIN

a (mV-RMSI

Fig. 2 - Typical performance curves for the CA3088E.

272

o

Q5 is the lust if amplifier and is bias~d to draw one
milliampere of current under zero signal conditions. This
condition is set by the biasing circuit of Q2, 03, Q4 and diodes
o I through 04. A nominal current of one milliampere is
established in Q3, which is a mirror of Q5, thus determining the
current in Q5. The supply voltage to the biasing circuit is also
regulated by Z I. With· no signal, 06 is cut off and has no affect
on the' operating point of Q5. As signal strength increases and
the base drive voltage increases, Q6 conducts some of the base
current being applied to QS and reduces the coUector current
and, thus, the gain, as shown in Fig. 2.
Q I is normally used as a converter stage. I t is biased to a
nominal current of 0.35 milliampere by diodes D3 and D4 in
combination with the source resistor, R2. The emitter is
brought out oupin 1; this terminal may ~e bypassed or may be
used to apply a local-oscillator signal to the emitter.
QI3 and 014 form the audio driver stage, a grounded
emitter stage coupled directly to an emitter follower. The
emitter follower provides a Jow·impedance drive for an external
audio amplifier. This stage must be externally biased; a
convenient method is to feed a portion of the dc potential on
the emitter of Ql4 to the base of Q13 with the proper network
connected between pins 14 and 15. A nominal voltage gain
from pin 14 to pin 15 of 30 times is determined by the ratio of
resistor RIB to R17.
In addition to the voltage regulation pro.vided by the zener
diode, Z I, the circuit is temperature compensated by the bias
circuit described previously. Transistors Q I, Q5, and 013 are
large·geometry devices which provide low-noise performance in
the CA3088E. All emitter follower stages which have the
emitters brought out to external terminals are pro~epted against
inadvertently shorted tenninals. The size of the chip is 52 mils
by 52 mils.

APPLICATIONS
AM Broadcast Receivers
When would a designer use the CA3088E as the basic
subsystem of an AM radio? The typicallow-cost table model or
portable radio ordinarily has neither an rf amplifier stage nor a
tuning meter; therefore, two features of the CA3088E have no
use in simple AM radios. Furthermore, economic considerations
make it difficult for integrated devices to compete with discrete
devices in these minimal-performance receivers. On the other
hand, the high-performance console receiver is an application in
which all of the features of the CA3088E are useable. The
CA3088E, in which the biasing of most stages is accomplished
intemally, provides savings in the number of components to be
specified, purchased, handled, and connected.
Fig. 3 shows the circuit for a typical AM receiver using the
CA3088E. DOUble-tuned, transformer-coupled circuits are
shown here, but any of the other forms of band-pass filters may
be used that best suit the needs of the designer. The rf stage
may take on any of several forms and so is shown only as a gain
block. The intention here is not to present an optimum receiver
design, but to show how a specific device, the CA3088E, may
be used. Fig 4 shows perfcnmmce curves obtained in a receh'er
using the CA3088E in conjunction with an external rf stage.
In addition to commercial broadcast-receiver, a multitude of
receiver applications exist in communications equipment of all
forms. The CA3088E will suit many of these applications with
the extra features available in the circuit. The CA3088E may be
used as a straight if amplifier for use with a separate tuner, or it
could serve as a subsystem in a double-conversion receiver.

ICAN-6022

.----4---4---+~~~--~

0.02

AL.L RESISTANCE VALUES ARE IN OHMS

ALL CAPACITANCE VALUES ARE IN MICROFARADS

Fig. 3 - Typical AM broadcast receiver using the CA3088E.
TABLE II. INPUT AND OUTPUT IMPEDANCE DATA

1000

30% MODULATION - 400 Hz

,/

V

0

4

10

C'N
Picofarads

.

"

4

100

6.
1000

--

UNMODULATED (NOISE)

I I
4 68

10K

2468
2468
lOOK
1M

FIELD INTENSITY (I'V/M)

Fig. 4 -

Performance curves for an AM receiver with an rf stage

using the CA3088E.
Amateur radio receivers are a natural for the circuit. Narrow~
band or fixed-tuned systems, such as remote control systems,
and hand-carried receivers, systems in which the space saving
features of an integrated circuit could be important, could make
good use of the CA3088E.
High-Frequency Applications
Many receivers usc if amplifiers at the higher frequencies;
therefore, the high-frequency characteristics of the CA3088E
are important. Table II shows some of the four pole
characteristics of the individual signal stages of the CA3088E at
I MHz and 30 MHz. The forward transconductance is not
significantly affected in the frequency range considered.
The high-frequency performance of the second-if-amplifier!
detector stage is determined within the chip. Fig. 5 is a plot of
the voltage gain of the stage as a function of frequency. The
gain is down about 6 decibels at 10 MHz and about 16 decibels

COUT
Picofarads

C'b
Picofarads

1 MHz 30MHz 1 MHz 30 MHz
A;
A;
Ro
Ro
Ohms Ohms Ohms Ohms

01

12

1.5

3500

2000

lOOK

9K

05

17

1.5

2000

1000

lOOK

9K

07

3.5

75 K

45 K

.......

/

I

I-

at 30 MHz. The nominal gain of this stage is 40 decibels;
therefore, this stage has considerable gain at these frequencies.
The converter and first-if stages will operate at higher
frequencies, but stability considerations will control the
practical gain. Calculations of maximum useable gain (MUG)
and maximum available gain (MAG), using the data in Table I
for the unneutralized single-stage amplifier, show that about 10
decibels of power gain must be sacrificed to maintain good
stability at 30 MHz. More gain can be obtained by neutralizing,
but at the expense of circuit simplicity.
The audio-preamplifier stage may also be used as another if
stage provided that the low-output impedance of the emitter
follower is not detrimental to performance. The stage may be
used to drive a crystal or ceramic filter in which the typical
matching impedances are quite low. The frequency response of
this stage is very similar to that of the second-if stage with
about 6 decibels drop in gain at 10 MHz. This stage may also be
controlled by the output from pin 13 as is the case with the
external rf stage.
Fig. 6 shows the circuit of a 10.7 MHz if amplifier using two
ceramic filters. This circuit shows how the use of the CA3088E
with low-impedance filters can simplify a design. Stability is
maintained by the low-impedance terminations used with the
filters. Thc first two stages are coupled together with a
single-tuncd circuit which provides impedance matching. A

273

ICAN-6022

o
.... -4

3in

~ -8

6
-12

""'"

"'"

~"B'40iB .AIN

-I.

o

12

~

"'"

16

.............
20

r--

24

28

32

FREQUENCY (MHz)

Fig. 5 - Plot of voltage gain as a function of frequency for the
second·if-amplifierldetector st1lge of. CA3088E.
SO-microvolt input signal with 3Q..percent modulation produces

a detected audio signal of 22 millivolts at ·the detector outpuL
The audio stage may be used as an audio driver or as an
additional if stage to drive the input ceramic filter.

General.purpose Amplifier Array
The CA3088E is versatile enough to be used as a
general-purpose amplifier array_ Ql and Q5 3re internally biased

and require only a collector load to produce an amplifier. These
devices may be operated to a maximum collector voltage of 16
volts. With the addition of external biasing, the operating points
of these stages may be varied from the internally established
quiescent point. The second-if-amplifierl detector combination
is biased externally as discussed previously. Ql2, which is
normally connected as an envelope detector may be connected
as another emitter follower by loading resistors R20 and R21
with an external resistor.

274

Fig. 6 - A tat·MHz if amplifier using the CA3088E and two
ceramic filters.
The audio preamplifier is independent and biased exter~
nally. The gain-control circuits may be used as in the AM-radio
applications. If Q 12 is not used as a detector, the gain-rontrol
voltage can be applied on pin II. Q II provides a positive-going
voltage with increasing signal and Q8 provides a negative-going
voltage.
Acknowledgaments
The author thanks Messrs. Leo Harwood and Max Malchow
for their aid and suggestions in discussions concerning this
project, and Mr. Frank Curley for his aid in circuit construction
and collection of data.

OO(]5LJD

Linear Integrated Circuits

Solid State
Division

Application Note

ICAN-6048
Some Applications of
A Programmable Power
Switch/Amplifier
by L. R. Campbell and H. A. Wittlinger

The RCA-CA3094 unique monolithic programmable power
switch/amplifier IC consists of a high·gain preamplifier driving
a power·output amplifier stage. It can deliver average power of
3 watts or peak power of 10 watts to an external load, and
can be operated from either a single or dual power supply.
This Note briefly describes the ·characteristics of the CA3094,
and illustrates its use in the following circuit applications:
Class A instrumentations and power amplifiers
Class' A driver.amplifier for complementary power tran·
sistors
Wide·frequency·range power multivibrators

Amplifier·Bias·Current (lABC) terminal (No.5 in Fig. I) to
control circuit sensitivity. Response of the amplifier is es·
sentially linear as a function of the current at terminal 5.
This additional signal input "port" provides added flexibility
in many applications. Thus, the output of the amplifier is a
function of iriput signals applied differentially at terminals 2
and 3 and/or in a single-ended configuration at terminal 5. The
output portion of the monolithic circuit in the CA3094 con·
sists of a Darlington·connected transistor pair with access pro·
vided to both the collector and emitter terminals to provide
capability to usink" and/or "source" current.

Current· or voltage·controlled oscillators
Comparators (threshold detectors)
Voltage regulators
Analog timers (long time delays)
Alarm systems

Motor·speed controllers
Thyristor·firing circuits
Battery-charger regulator circuits
Ground·fault·interrupter circuits
Circuit Description
The CA3094 series of devices offers a unique combination
of circuit flexibility and power.handling capability. Although
these monolithic IC's dissipate only a few microwatts when
quiescent, they have a high current-output capability (100
milliamperes average, 300 milliamperes peak) in the active
state, and the premium.grade devices can operate at supply
voltages up to 44 volts.
Fig. I shows a schematic diagram of the CA3094. The por·
tion of the circuit preceding transistors Q12 and Q13 is the
preamplifier section and is generically similar to that· of
the RCA-CA3080 Operational Transconductance Amplifier
(OTA).l,2 The CA3094 circuits can be gain·programmed by
either digital and/or analog signals applied to a separate

INPUTS

INY. NON-INV.

2

•

92CS-ZOZ94

Fig.I-CA3094 circuit schematic diagram.

The CA3094 series of circuits consists of six types that dif·
fer only in voltage.handling capability and package options, as

11-73

275

ICAN-6048
shown below; other electrical characteristics are identical.
Package Options
CA3D94S; CA3D94T
CA3D94AS; CA3D94AT
CA3D94B8; CA3D94BT

Maximum Voltage Rating
24V
36 V
44V

The suffix "8" indicates circuits packaged in TO-5 enclosures
with leads formed to an 8-lead dual-in-line configuration (D.I"
pin spacing). The suffix "T" indicates circuits packaged in 8lead TO-5 enclosures with straight leads. The generic CA3D94
type designation is used throughout thisNote.
Class A Instrumentation Amplifiers
One of the more difficult instrumentation problems frequently encountered is the conversion of a differential input
signal to a single-ended output signal. Although this conversion can be accomplished in a straightforward design through
the use of classical op-amps, the stringent matching requirements of resistor ratios in feedback networks make the conv.,rsion particularly difficult from a practical standpoint.
Because the gain of the preamplifier section in the CA3D94
can be defined as the product of the transconductance
and the load resistance (gm RL), feedback is not needed to
obtain predictable open-loop gain performance. Fig. 2 shows
the CA3D94 in this basic type of circuit.

Under the conditions described, an input swing ediff of ±26
millivolts produces a variation in the output current 10 of
±8.35 milliamperes. The nominal quiescent output voltage is
12 milliamperes times 56D ohms or 6.7 volts. This output
level drifts approximately -4 millivolts, or -0.0595 per cent,
for each °c change in temperature. Output drift is caused by
temperature-induced variations in the base-emitter voltage of
the two output transistors, QI2 and Q!3'
Fig. 3 shows the CA3094 used in conjunction with a resistive-bridge input network; and Fig. 4 shows a single-supply

......~r---- 8.4 V

r-------~

1

OUTPUT
I VOLT
FULL
SCALE

I

.. SET TO OPTIMIZE CMRR

Fig.3-Single-supply differential-bridge amplifier.

amplifier for thermocouple signals. The RC networks· connected between terminals I and 4 in Figs. 3 and 4 provide
compensation to assure stable operation.
, - - - - t -.....-0-----_+ 12V

36 Kn
NOTES:

-30 V

PRE-AMP. GAIN IAV): 11m Rl = (51 (10-3 ) (36) (l03)~ 180
(OUTPUT AT TERMINAL I)

(~I~HU:;::o':.7~ATlON: DlFFERENTIAL INPUT!:I ±26

;).........---VOUT
mY'

DEVIATION FROM

THERMOCOUPLE

LINEARITY)
0-1 mA
I mV FROM
THERMOCOUPLE
PROOUCES
FULL-SCALE
OUTPUT C!JRRENT

OUTPuT VOLTAGE (EOI :AV (± ediff1 "(J80)(±26 mV)" ± 4.7 V
OUTPUT CURRENT, 10=

10

;:ovn

J:I

"8.35 mA

(11m Rl)(e diffl
RE

,.,%

910n

Fig.2-0pen-/oop instrumentation amplifier with differential

input and single-ended output.

The gain of the preamplifier section (to terminal No. I) is
gmRL = (5 x 10-3 ) (36 x 103 ) = 18D. The transconductance gm is a function of the current into terminal No.5,
IABC, the amplifier-bias·current. In this circuit an IABC of
26D microamperes results in a gm of 5 millimhos. The operating point of the output stage is controlled by the 2-kilohm
potentiometer. With no differential input signal (ediff = D),
this potentiometer is adjusted to obtain a quiescent output
current 10 of 12 milliamperes. This output current is established by the 56D-ohm emitter resistor, RE, as follows:
I
(gm R 0 (ediff)
0"
RE

276

120K

92CS-20280

Fig.4-Single-supplyamplifier for thermocouple signals.

Class A Power Amplifiers
The CA3094 is attractive for power-amplifier service because the output transistor can control current up to '100
milliamperes (300 milliamperes peak), the premium devices
*The components of the RC network are chosen so that
I

2rrRC .. 2 MHz.

ICAN-6048
(CA3094B) can operate at supply voltages up to 44 voits, and
the TO-5 package can dissipate power up to 1.6 watts when
equipped with a suitable heat sink that limits the case temperature to 55°C.
Fig. 5 shows a Class A amplifier circuit using the CA3094A
that is capable of delivering 280 milliwatts to a 350-ohm resistive load. This circuit has a voltage gain of 60 dB and a
(RI

+15 V

10 Ktl

-15

v (')-"'VVV--{) +15 v

~....---l

Your

-15V
92C!ii-202BI

Fig.5-Class·A amplifier - 280·mW capabilitv into a
resistive load.

3-dB bandwidth of about 50 kHz. Uperation is stable wIthout
the use of a phase-compensation network. Potentiometer R is
used to establish the quiescent operating point for class A
operation.
The circuit of Fig. 6 illustrates the use of the CA3094 in a
class A power-amplifier circuit driving a transformer-coupled
load. With dual power supplies of +7.5 volts and -7.5 volts, a
v+

*

TYPICAL

DATA

Dlg~r~xfION ~~
RB

1.5 W

JOKfl 40 K.o.

v+

+7.5

+IOV

v-

-7.5

-IOV

RE

son

4sn

*" GEN.
RADIO TYPE 1840-A
OUTPUT POWER METER
OR EQUivALENT

distortion is 0.4 per cent at a power-output level of 220
milliwatts with a rellected load resistance Rp of 310 ohms,
and is 1.4 per cent for an output of 600 milliwatts with an
Rp of 128 ohms. The setting of potentiometer R establishes
the quiescent operating point for class A operation. The
I-kilohm resistor connected between terminals 6 and 2 pro·
vides de feedback to stabilize the collector current of the out·
put transistor. The ac gain is established by the ratio of the
I-megohm resistor connected between terminals 8 and 3 and
the I-kilohm resistor connected to terminal 3. Phase campen·
sation is provided by the 680-picofarad capacitor connected
to terminal I.
Class A Driver-Amplifier for Complementary Power
Transistors
The CA3094 configuration and characteristics are ideal for
driving complementary power·output transistors;3 a typical
circuit is shown in Fig. 7. This circuit can provide 12 watts of
audio power output into an 8-ohm load with intermodulation
distortion (IMD) of 0.2 per cent when 60-Hz and 2-kHz signals are mixed in a 4: I ratio. Intermodulation distortion is
shown as a function of power output in Fig. 8.
The large amount of loop gain and the lIexibility of feedback arrangements with the CA3094 make it possible to incorporate the tone controls into a feedback network that is
closed around the entire amplifier system. The tone controls
in the circuit of Fig. 7 are part of the feedback network connected from the amplifier output Uunction of the 330- and
47-ohm resistors driven by the emitters of Q2 and Q3) to
terminal 3 of the CA3094. Fig. 9 shows voltage gain as a
function of frequency with tone controls adjusted for "lIat"
response and for responses at the extremes of tone-control
rotation. The use of tone controls incorporated in the
feedback network results in excellent signal-to-noise ratio.
Hum and noise are typically 700 microvolts (83 dB down) at
the output.
In addition to the savings resulting from reduced parts
count and circuit size, the use of the CA3094 leads to further
savings in the power-supply system. Typical values of powersupply rejection and common-mode rejection are 90 dB and
100 dB, respectively. An amplifier with 40-dB gain and 90-dB
power-supply rejection would require a 31-millivolt powersupply ripple to produce one millivolt of hum at the output.
Therefore, no filtering is required other than that provided by
the energy-storage capacitors at the output of the re,ctifier system shown in Fig. 7.
For applications in which the operating temperature range
is limited (e.g., consumer service) the thermal compensation
network (shaded area) can be replaced by a more economical
configuration consisting of a resistor-diode combination (8.2
ohms and I N5391) as shown in Fig. 7.

92CS-20Z82

Fig.6-C/ass-A amplifier with transformer·coupled load.

base resistor RB of 30 kilohms, and an emitter resistor RE of
50 ohms, CA3094 dissipation is typically 625 milliwatts. With
supplies of +10 volts and -10 volts, RB of 40 kilohms, and
RE of 45 ohms, the dissipation is 1.5 watts. Total harmonic

Power Multivibrators (Astable and Monostablel
The CA3094 is suitable for use in power multi vibrators
because its high·current output transistor can drive low-impedance circuits while the input circuitry and the frequency-determining elements are operating at micropower levels. A typical
example of an astable multivibrator using the CA3094 with a

277

ICAN~

____________________________

~

___________________________

FOR STANtJARD INPUT: SHORT C2.: R1

.2~

KG

CI _0.047,.F; REMOVE R2
FOR CERAMIC CARTRIDGE INPUT: C,-O.o047,.F
R,-2,5Mn;REMOVE JUMPER FROM C2j LEAVE H2o

TYPICAL PERFORMANCE DATA
For 12·W Audio Amplifier Circuit
Power Output (Sn load, Tone Control set at "Flat")
Music (at 5% THO. regulated supply) . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous (at 0.2% fMO. 60 Hz &: 2 kHz mixed in a 4:1 ratio.

unregulated supply) See Fig. 8

.....•....................................

Total Harmonic Oistoration
At t W. unregulated supply . . . . • • • • . . . . • • . . . . • • . . . . • . . . . . . . • . • . • . • • . • • • • • .

15'

W

12

W

0.05

%
%

At 12 W. unregulated supplv. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0.57
Voltage Gain. . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40
Hum and Noise (Below continuous Power Output I . . . . . . . . . . . . . _ .. __ . ___ .. _ . . . . . . . . •
83
Input Resistance .... _ . . . . . . . . . . . _ . _ . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . __ .. _ . .
250
Tone Control Range •.•. _ . . . . . . . . ___ . . . . . . _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Fig. 9

dB
dB

kn

Fig.1-12·watt amplifier circuit featuring true complementary·symmetrv output stage with CA3094 in driver stsge.

I§

~

15

55
1.8

~
z

1.6f-·

0

1.2

,.~

-&

2 ~~:g~UL~TED SUPPLY

II

.
i

1.4

z

C

~

..."
"

r,

z

51 0.8

~>

li

~0

"
Ili
~

0.6
0.4
0.2
0

60 Hz

'"

40

35

Fig.8-lntermodulation distortion

VI.

V

V

TREBLE BOOST

.......

V

25

-H-

~LELT

/

30

I I

8ASSCU~

V-

15

a 2 KH

60 Hz 87KHz
4
6
8
10
POWER OUTPUT 1POUTJ-W

I

I~I

.......

45

20
60 Hz 8 12 KHz

10
12

14
10

92CS·20550

power output.

dual power supply is shown in I'ig. 10. The output frequency
fOUT is determined as follows:
fOUT = 2RCln[(2RI/R2) + II
If R2 is equal to 3.08 RI, then fOUT is simply the reciprocal
ofRC.

278

50

.A-l
f'ASSBOOST

• ••100 • • •• 1000 •
FREQUENCY

..

Ie;;.

• elOOK
.

t t )-Hz
ftCS~20S51

Fig.9- Voltage gain .,s. frequency.

Fig. II is a single-supply astable multi vibrator circuit which
illustrates the use of the CA3094 for flashing an incandescent
lamp. With the component values shown, this circui\ produces
one flash per second with a 25-per-cent "on"-time while delivering output current in excess of I 00 milliamperes. During

ICAN-6048

the 7S·per.cent "off'·time it idles with micropower consump·
tion. The flashing rate can be maintained within ±2 per cent
of the nominal value over a battery voltage range from 6 to IS
volts and a temperature excursion from 0 to 70°C. The
CA3094 series of circuits can supply peak·power output in
excess of 10 watts when used in this type of circuit. The fre·
quency of oscillation fOSC is determined by the resistor
ratios, as follows:

+30Y

LED

I

fOSC = -2-R-CJ-n-[-(2-R-I-/R-2-)-+-I-)
where
92CS-Z0408

+ 15

Fig. 12-Astable power multillibrator with provisions for
varying duty cycle.

V

Fig. 13 shows a circuit incorporating independent controls
(RON and ROFF) to establish the "on" and "off' periods of
the current supplied to the LED. The network between points
"A" and "B" is analogous in function to that of the 100·
kilohm resistor R in Fig. 12.
+30V

sion

NOTE: fOUT"

I ZRI
2 RC.ln

(""R2 + II

; If RZ"3,OBR"f ouT

"'fic

92CS-20290

Fig. to-Astable multillibrator using dual supply.

47Kn

+v
NO. 57

RA

92CS-20555

Fig. 13-Astable power multivibrator with provisions for
independent control of LED Uon-off" periods.

The CA3094 is also suitable for use in monos table multi·
vibrators, as shown in Fig. 14. In essence, this circuit is a pulse
counter in which the duration of the output pulses is inde·
pendent of trigger·pulse duration. The meter reading is a func·
tion of the pulse repetition rate which can be monitored with
the speaker.

RS

••v

FEATURES

•

I FLASH/SEC.

'OSC

•

25 % DUTY CYCLE

•

~~g"'UE6N..~~

= 2 ~c.tn[(2RI/R2 +1>]

SNcPcEPENDENT OF y+

220K!1

WHERE RI

=::.::

I."

IN914

92CS-20293

Fig. 1 t-Astable mult;vibrator using single supply.

Provisions can easily be made in the circuit of Fig. II to
vary the multivibrator pulse length while maintaining an es·
sentially constant pulse repetition rate. The circuit shown in
Fig. 12 incorporates a potentiometer Rp for varying the
width of pulses generated by the astable multivibrator to drive
a light-emitting diode (LED).

@--...._OOUTPUT

100

n

• FULL - SCALED£fLECTION. 83 PULSES/SEC

Fig. 14-Power monostable multivibraror.

279

ICAN-6048
Current- or Voltage-Controlled Oscillators
Because the transconductance of the CA3094 varies linearly as a function of the amplifier bias current (lABC) supplied to terminalS, the design of a current- or voltage-controlled oscillator is straightforward, as shown in Fig. IS.
Fig. 16 and 17 show oscillator frequency as a function of
IABC for a current-controlled oscillator for two different
values of capacitor C in Fig. IS. The addition of an appropri-

r - - - - - - -.....--~- +'5 v
, Kil
47KQ

OUTP~
100
400
500
AMPLIFIER BIAS CURRENT (rABCI-pA
92CS-ZOZ84

Fig. 17-frequencv as a function of I ABC for C=100 pF

47Kn

for circuit in Fig. 15.

OR

Comparators (Threshold Detectors)
Comparator circuits are easily implemented with the
CA3094, as shown by the circuits in Fig. IS. The circuit of
Fig. IS(a) is arranged for dual-supply operation; the input voltage exceeds the positive threshold, the output voltage swings
essentially to the negative supply-voltage rail (it is assumed
that there is negligible resistive loading on the output ter-

 - -.......+-'\A'V--..:..:..:...I-<'i).-J

The circuit is applicable, for example,
With the values shown in Fig. 20, the
when the input exceeds approximately
energized until the input signal drops
5.5 volts.

Power-Supply Regulators
The CA3094 is an ideal companion device to the CA30S5
series regulator circuits4 in dual-voltage tracking regulators
that handle currents up to 100 milliamperes. In the circuit of
Fig. 21, the magnitude of the regulated positive voltage provided by the CA30S5A is adjusted by potentiometer R. A
sample of this positive regulated voltage supplies the power
for the CA3094A negative regulator and also supplies a refer-

(6).--.-. OUTPUT
-}--HIGH

JOKil

DEAD
ZONE
---LOW

IK
+15 V

to automatic ranging.
relay coil is energized
5.9 volts and remains
below approximately

MAX IOUT' % 100 mA

n

_-==~=::::;----,

10 KQ

003J&F

Fig. 19-Dual-limit threshold detector.

and the low-level limit is set by I'0tentiometer R2 to actuate
the CA30S0 low-limit detector. I ,2 A positive output signal is
delivered by the CA3094 whenever the input signal exceeds
either the high-limit or the low-limit values established by the
appropriate potentiometer settings. This output voltage is approximately 12 volts with the circuit shown.
The higll current-handling capability of the CA3094 makes
it useful in Schmitt power-trigger circuits such as that shown
in Fig. 20. In this circuit, a relay coil is switched whenever the

-15V

'-,--+-'---0 ~~~PUT

.V+,NPur RANGE-19TO

30vL_~NV----'

.,,,

IOKll

FOR 15v OUTPUT

..... V-,NPUT RANGE '-16 TO-3D V
FOR-15V OUTPUT
MAX. LINE'

,tIOO.O.075%/V

AVOUT

[VOUTHNIT'AL~ AV,N

+30V
MAX. LOAD •

~O:OTU~INITIALI ~ IOO·0.07~ %
II:L FROM I

to

VOUT

50 mAl

Fig.21-Dual-voltage tracking regulator.
R2
24Kn

I NPur >-'\A"---&~

IOOKll
UPPER TRIP POINT=30

_R_,__
R1+R 2 +R 3

LOWER TRIP

POINTI:II(30.0.026R~....!!L

R2 +R 3

Fig.20-Precision Schmitt power-trigger circuit.

input signal traverses a prescribed upper or lower trip point, as
defined by the following expressions:
Upper Trip Point = 30 ( RI + ~; + R3)
Lower Trip Point"" (30 - 0.026RI) R2 ~ R3

ence voltage to its terminal 3 to provide tracking. This circuit
provides a maximum line regulation equal to 0.075 per cent
per volt of input voltage change and a maximum load regulaof 0.075 per cent of the output voltage.
Fig. 22 shows a regulated high-voltage supply similar to the
type used to supply power for Geiger-Mueller tubes. The
CA3094, used as an oscillator, drives a step-up transformer
which develops suitable high voltages for rectification in the
RCA-44007 diode network. A sample of the regulated output
voltage is fed to the CA30S0A operational transconductance
amplifier through the 19S-megohm and 91 O-kilohm divider to
control the pulse repetition rate of the CA3094. Adjustment
of potentiometer R determines the magnitude of the regulated
output voltage. Regulation of the desired output voltage is
maintained within one per cent despite load-current variations
of 5 to 26 microamperes. The dc-to-dc conversion efficiency
is about 4S per cent.

Timers
The programmability feature inherent in the CA3094 (and
operational transconductance amplifiers in general) simplifies
the design of presettable timers such as the one shown in

281

ICAN-6048 _ _ _ _ _ _ _ _ _ _ _ _ _---,_ _ _ _ _ _ _ _ _ _ _ _ __
RL

r-'\l\l\r-.,
, - 1 9 8 MD

~?

:+900V

r-----------~~~~

(NINE 22 MD RESISTORS IN SERIES)

Fig.22-Regulated high-voltage supply.

Fig. 23. Long timing intervals (e.g., up to 4 hours) are achieved
by discharging a timing capacitor C I into the signal-input terminal (e.g., No.3) of the CA3094. This discharge current is
controlled precisely by the magnitude of the amplifier bias
current IABC programmed into terminal S through a resistor
selected by switch S2. Operation of the circuit is initiated by
charging capacitor C I through the momentary closing of
switch SI' Capacitor CI starts discharging and continues discharging until voltage EI is less than voltage E2' The differential input transistors in the CA3094 then change state, and
terminal 2 draws sufficient current to reverse the polarity of

RCA

T23028

R.

T23028 TURNS "OFF" AFTER
EXPIRATION OF TIME DELAY

TIME

R,-C.51 Mtl- "'""3"iiiN.
R2- 5.1 Mil - 3OMIN.
R3=22 un - 2HRS.
R4"'44 MJl - 4HRS.

RS -2.7 Kg,
Rsa50 Kg,
R7-2.7 K.D.
RS-1.5 Kn

92CS -20276R I

Fig.23-Presettable analog timer.

the output voltage (terminal 6). Thus, the CA3094 not only
has provision for readily presetting the time delay, but also
provides significant output current to drive control devices
such as thyristors. Resistor RS limits the initial charging current for C I' Resistor R7 establishes", minimum voltage of at
least I volt at terminal 2 to insure operation within the
common-mode-input range of the device. The diode limits the
maximum differential input voltage to S volts. Gross changes
in time-range selection are made with switch S2, and vernier
trimming adjustments are made with potentiometer R6'

282

In some timer applications, such as that shown in Fig. 24,
a meter readout of the elapsed time is desirable. This circuit
uses the CA3094 and the CA3083 transistor arrayS to control the meter and a load-switching triac. The timing cycle
starts with the momentary closing of the start switch tocharge
capacitor CI to an initial voltage determined by the SO-kilohm
vernier timing adjustment. During the timing cycle, capacitor
C I is discharged by the input bias current at terminal 3,
which is a function of the resistor value RI chosen by the
time-range selection switch. During the timing cycle the output of the CA3094, which is also the collector voltage. of QI'
is "high ". The base drive for Q I is supplied from the positive
supply through a 91-kilohm resistor. The emitter of QI'
through the 7S·ohm resistor, supplies gate-trigger current to
the triac. Diode-connected transistors Q4 and QS are connected so that transistor Q I acts as a constant-current source
to drive the triac. As capacitor CI discharges. the CA3094
output voltage at terminal 6 decreases until it becomes less
than the VCEsat of QI. At this point the flow of drive current to the triac ceases and the timing cycle is ended. The
20-kilohm resistor between terminals 2 and 6 of the CA3094
is a feedback resistor. Diode-connected transistors Q2 and Q3
and their associated networks serve to compensate for nonlinearities in the discharge-circuit network by bleeding corrective current into the 20-kilohm feedback resistor. Thus,
current flow in the meter is essentially linear with respect to
the timing period. The time periods as a function of R I are
indicated on the Time-Range Selection Switch in Fig. 24.
Alarm Circuit
Fig. 25 shows an alarm circuit utilizing two "sensor"
lines. In the "no-alarm" state, the potential at terminal 2 is
lower than the potential at terminal 3, and terminal S (I AlBC)
is driven with sufficient current through resistor RS to keep
the output voltage "high". If either "sensor" line is opened,
shorted to ground, or shorted to the other sensor line, the
output goes "low" and activates some type of alarm system.

ICAN-6048
+30V

91 Kn

120V

60 Hz

S.I K.D

270 K.D

68 K.o.

IKn

Fig.24-Presettable timer with linear readout.

The back-to-back diodes connected between terminals 2 and J
protect the CA3094 input terminals against excessive differential voltages.
+12V

R5
OOKO

R4

f1Yf1 :;:c~~o~US

IOOKA

.$"0;;;....,

5101(.0.

RAMP

GENER~:~UT +~','

LINES
R3

10 TERMINAL Z

~l-4-~~H
R2
5101<4

IOOKA

Re

* INPUT

.

TO TERMINAL :50
MOTOR

t

.

IAse

_~
, , _ _ _, - _

~
r'\. ----+ TIME
L-..J L-..J L

I'\..

CURR~

*

HVI

THIS LEVEL WILt. VARY DEPENDING ON MOTOR SPEED.
(SEE TEXT.)
(bl

92CS-20512

Fig.26-Motor·speed controller system.
92CS- 2027SRI

Fig.25-Alarm system.

Motor-Speed Controller System
Fig. 26 illustrates the use of the CA3094 in a motor-speed
controller system. Circuitry associated with rectifiers DI and
D2 comprises a full-wave rectifier which develops a train of
half-sinusoid voltage pulses to power the de motor. The motor
speed depends on the peak value of the half-sinusoids and the
period of time (during each half-cycle) the SCR is conductive.

The SCR conduction, in turn, is controlled by the time duration of the positive signal supplied to the SCR by the phase
comparator. The magnitude of the positive de voltage sup·
plied to terminal 3 of the phase comparator depends on
motor-speed error as detected by a circuit such as that shown
in Fig. 27. This de voltage is compared to that of a fixed-am·
plitude ramp wave generated synchronously with the ac-line·
voltage frequency. The comparator output at terminal 6 is
"high" (to trigger the SCR into conduction) during the period

283

ICAN-6048
when the ramp potential is less than that of the error voltage
on terminal 3. The motor·current conduction period is in·
creased as the error voltage at terminal 3 is increased in the
positive direction. Motor-speed accuracy of ±I per cent is
easily obtained with this system.
Motor-Speed Error Oetector. Fig. 27(a) shows a motor·
speed error detector suitable for use with the circuit of Fig. 26.
A CA3080 operational transconductance amplifier is used as a
voltage comparator. The reference for the comparator is es·
tablished by setting the potentiometer R so that the voltage
at terminal 3 is more positive than that at terminal 2 when the
motor speed is too low. An error voltage EI is derived from a
tachometer driven by the motor. When the motor speed is too
low, the voltage at terminal 2 of the voltage comparator is
less positive than that at terminal 3, and the output voltage at
terminal 6 goes "high". When the motor speed is too high, the
opposite input conditions exist, and the output voltage at ter·
minal6 goes "low". Fig. 27(b) also shows these conditions graph·
ically, with a linear transition region between the "high" and
Hlow" output levels. This linear transition region is known as
"proportional bandwidth". The slope of this region is deter·
mined by the proportional bandwidth control to establish the
error-correction response time.

+15V

EIN

TO PHASE

COMPARATOR

1.1

~

A

I

A

~v

A

BIAS LEVEL AT

;~~~--t_-_~~_ ~~~RMINAL NO.3
I-I

CI DISCHARGING (RAMP)

~

C1 CHARGING

EOUT

(0) -

-

-

- -- ---

(b)--- -

92CS-20274

Fig.28-Svnchronous ramp generator with input and output
waveforms.

Thyristor Firing Circuits

Temperature Controller. In the temperature control system
shown in Fig. 29, the differential input of the CA3094 is con·
nected across a bridge circuit comprised of a PTC (positive.
temperature.coefficient) temperature sensor, two 75-kilohm
resistors, and an arm containing the temperature set control.
When the temperature is "low':, the resistance of the PTC·type
sensor is also low; th~refore, terminal 3 is more positive than
PROPORTIONAL
terminal 2 and an output current from terminal 6 of the
BANDWIDTH
CONTROL
CA3094 drives the triac into conduction. When the tempera·
EOUT
ture is "high", the input conditions are reversed and the triac
TO PHASE
COMPARATOR
is cut off. Feedback from terminal 8 provides hysteresis to the
control point to prevent rapid cycling of the system. The
1.5·kilohm resistor between terminal 8 and the positive supply
101 VOLTAGE COMPARATOR
RECTIFIED AND FILTERED
IimHs the triac gale current and develops the voltage for the
SIGNAL DERIVED FROM
TACHOMETER DRIVEN BY
hysteresis feedback. The excellent power·supply·rejection and
MOTOR BEING CONTROLLED
common-mode·rejection ratios of the CA3094 permit accurate
"PROPORTIONAL BANDWIDTH"
repealability of control despite appreciable power-supply ripple. 11,e circuit of Fig. 29 is equally suitable for use with
NTC (negative.temperature·coefficient) sensors provided the
positions of the sensor and the associated resistor R are interchanged in the circuit. The diodes connected back-to-back
1'1
92CS-20276
across the input terminals of the CA3094 protect the device
Fig. 27-Motor speed error detector.
against excessive differential input signals.
Synchronous Ramp Generator. Fig. 28 shows a schematic
Thyristor Control from AC·Bridge Sensor. Fig. 30 shows a
diagram and signal waveforms for a synchronous ramp gener· line·operated thyristor·firing circuit controlled by a CA3094
ator suitable for use with the motor·controller circuit of that operates from an ac·bridge sensor. This circuit is particu·
Fig. 26. Terminal 3 is biased at approximately +2.7 volts larly suited to certain classes of sensors that cannot be oper(above the negative supply voltage). The input signal fIN at
ated from dc. The CA3094 is inoperative when the high side of
terminal 2 is a sample of the half-sinusoids (at line frequency)
the ac line is negative because there is no IABC supply to
used to power the motor in Fig. 26. A synchronous ramp sigterminalS. When the sensor bridge is unbalanced so that
terminal 2 is morc positive than terminal 3, the output stage of
nal is produced by using the CA3094 to chaige and discharge
the CA3094 is cut off when the ac line swings positive, and the
capacitor C I in response to the synchronous toggling of EIN'
output level at terminal 8 of the CA3094 goes "high". Cur·
The charging current for C I is supplied by terminal 6. When
rent from the line flows through the I N3193 diode to charge
terminal 2 swings more positive than terminal 3, transistors
the 100·microfarad reservoir capacitor, and also provides curQI2 and Q13 in the CA3094 (Fig. I) lose their base drive and
ront to drive the triac into conduction. During the succeeding
become non-conductive. Under these conditions, C I discharges
linearly through the external diode 03 and the Q10, 06 path . negative swing of the ac line, there is sufficient remanent energy in the reservoir capacHor to maintain conduction in the
in the CA3094 to produce the ramp wave. The Eout signal is
triac.
supplied to the phase comparator in Fig. 26.

284

ICAN·6048

RCA

TYPE
DI20lF

1.5M

IN914

+
10

117V
60 Hz

26V
6OH.

ALL RESISTANCES IN OHMS -1/2 WATT

Fig.29- Temperature controller.

r

.,

HIGH

IBOKn

330Kn

IlOV
AC
LINE

92CS-20413RI

Fig.30-Line·operated thvristor·firing circuit controlled by
ac-bridge sensor.

When the bridge is unbalaJ1!.:cd in the opposite direction su
that terminal 3 is morc positive than tcrmin-......Tc....,.---Q OUTPUT
REG.

reg IL ; Iquiescent + IRI
UNREG

Vr

O.03f1-F

0.001
~F

-ISV

'--r---+~""'-o REG.

OUTPUT

RI

R"EG'I L

(,)

CURRENT REGULATOR

."yf"INPUT RANGE:::I9 TO 30 V '---..J\JVv-----.J
10 Kll
FOR 15 V OUTPUT
:l:1"Io
.... V-,NPUT RANGE=_16 TO-30 V
FOR-15 V OUTPUT

REGULATION:
MAX. LINE:: A Your
;;[V':'O~U".!TC."-N-'T-'A-L""~-A-V-'N- II IOO::O.075%/V

MAX. LOAD:::

::A.:.VO~U".!T_ __

Your (INITIAL)

x 100:0.075"10 Your
(IL FROM I TO 50 mAl
92CM-20560

Fig. 20- Dual-voltage tracking regulator.

UN REG

NEG.V 1 (-I0-_......,.Ib"')_ _ _ _ _ _ _- '
HIGH-CURRENT REGULATOR

Fig. 19- Constant current regulators.

Fig. 19(b) shows a high-current regulator using the CA3085 in
conjunction with an external n-p-n transistor to regulate currents up to 3 amperes. In this circuit the quiescent regulator
current does not flow through the load and the output current
call be directly programmed by RI , i.e.,
Vref
RegIL;Rl
With this regulator currents between I milliampere and 3
amperes can be programmed directly. At currents below
I milliampere inaccuracies may occur as a result ofleakage in
the external transistor.
A Dual-Tracking Voltage Regulator
A dual-tracking voltage regulator using a CA3085 and a

The positive output voltage is regulated by a CA3085 operating in a configuration essentially similar to that described in
connection with Fig. 3. Resistor R is used as a vernier adjustment of output voltage. The negative output voltage is regulated
by the CA3094A, which is "slaved" to the regulated positive
voltage supplied by the CA3085. It should be noted that the
non-inverting input of the CA3094A and the negative supply
terminal of the CA3085 are connected to a common ground
reference. The "slaving" potential for the CA3094A is derived
from all accurate 1:1 voltage-divider network comprised of two
10-kilohm resistors connected between the +15-volt and
-IS-volt output terminals. The junction of these two resistors
is connected to the inverting input of the CA3094A. The voltage at this junction is compared with the voltage at the noninverting input, and the CA3094A then automatically adjusts
the output current at the negative terminal to maintain a negative regulated output voltage essentially equal to the regulated
positive output voltage. Typical performance data for this circuit are shown in Fig. 20.
• Specifications for the CA3094A appear in RCA Data File
No. 598 and application information is presented in
ICAN-6048.

301

ICAN-6157 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
The basic circuit of Fig. 20 can be modified to regulate dis·
similar positive and negative voltages (e.g., +15 V, -5 V) by
appropriate selection of resistor ratios in the voltage-divider
network discussed previously. As an example, to provide
tracking of the + 15 V and -5 V regulated voltages with the
circuit of Fig. 20, it is only necessary to replace the IO-kilohm
resistor connected between terminals 3 and 8 of the CA3094A
with a 3.3-kilohm resistor.
Regulators With High Ripple Rejection
When the reference-voltage source in the CA3085 is adequately fIltered, the typical ripple rejection provided by the
circuit is 56 dB. It is possible to achieve higher ripple-rejection
performance by cascading two stages of the CA3085, as shown
in Fig. 21. The voltage-regulator circuit in Fig. 21(a) provides
90 dB of ripple rejection. The output voltage is adjustable over
the range from 1.8 to 30 volts by appropriate adjustment of
resistors RI and R2. Higher regulated output currents up to
I ampere can be obtained with this circuit by adding an external
n·p-n transistor as shown in Fig. 21(b).

(.)

90dB RIPPLE REJECTION
LINE REG. <0.0001 "I.. /Vr
LOAD REG.-

i

'r---+---+---f---f--~~

However, use of this circuit places certain constraints upon the

user. Specifically, effective protection·circuit operation is
dependent upon the following conditions:
(1) The circuit configuration of Fig. 1 is used, with an
internal supply, no external load on the supply, and
terminal 14 connected to terminall3.
(2) The value of potentiometer Rp and of the sensor
resistance must be between 2000 ohms and 0.1 megohm.
(3) The ratio of sensor resistance and Rp must be greater
than 0.33 and less than 3.0 for all normal conditions. (If either
of these ratios is not met with an unmodified sensor. a series
resistor or a shunt resistor must be added to avoid undesired
activation of the circuit.)
The protective feature may be applied to other systems
when operation of the circuit is understood. The protection
circuit consists of diodes DI2 and DI5 and transistor QIO.
Diode DI2 activates the protection circuit if the sensor shown
in Fig. 1 shorts or its resistance drops too low in value, as

follows: Transistor Q6 is on during an output pulse so that the
junction of diodes Ds and D12 is 3 diode drops
(approximately 2 volts) above terminal 7. As long as V l 4 is
more positive or only 0.15 volt negative with respect to that
point, diode D12 does not conduct, and the circuit operates
normally. If the voltage at terminal 14 drops to I volt, the
anode of diode Ds can have a potential of only 1.6 to
1.7 volts, and current does not flow through diodes Ds and D9
and transistor Q6. The thyristor then turns off.
The actual threshold is approximately 1.2 volts at room
temperature, but decreases 4 millivolts per degree C at higher
temperatures. As the sensor resistance increases, the voltage at

terminal 14 rises toward the supply voltage. At a voltage of
approximately 6 volts, the zener diode DI5 breaks down and
turns on transistor QIO, which then turns off transistor Q6
and the thyristor. If the supply voltage is not at least 0.2 volt
more positive than the breakdown voltage of diode D15,
activation of the protection circuit is not possible. For this
reason, loading the internal supply may cause this circuit to
malfunction, as may selection of the wrong external supply
voltage. Fig. 7 shows a guide for the proper operation of the
protection circuit when an external supply is used with a
typical integrated-circuit zero-voltage switch.

AMBIENT TEMPERATURE _·c

Fig. 7 - Operating regions for built-in protection circuits of a typical
zero-voltage switch.

Operating-Power Options

Power to the zero-voltage switch may be derived directly
from the ac line, as shown in Fig. I, or from an external dc

power supply connected between terminals 2 and 7, as shown
in Fig. 8. When the zero-voltage switch is operated directly
from the ac line, a dropping resistor RS of 5,000 to
10,000 ohms must be connected in series with terminalS to
limit the current in the switch circuit. The optimum value for
this resistor is a function of the average current drawn from

the internal dc power supply, either by external circuit
elements or by the thyristor trigger circuits, as shown in Fig. 9.
The chart shown in Fig. I indicates the value and dissipation
rating of the resistor Rs for ac line voltages of 24, 120,208 to
230, and 277 volts.

Vec

Rs
10K

120V RMS
60 Hz

SPECIAL APPLICATION CONSIDERATIONS

As pointed out previously, the RCA integrated·circuit
zero-voltage switches (CA3058, CA3059, and CA3079) are
exceptionally versatile units that can be adapted for use in a
wide-variety of power-control applications. Full advantage of
this versatility can be realized, however, only if the user has a
basic understanding of several fundamental considerations that
apply to certain types of applicatiOns of the zero-voltage
switches.

>+----(4r:,.,THJ,?STOR
GAlE

ALL RESISTANCE
VALUES ARE
IN OHMS
92CS-22!i91

Fig. 8 - Operation of the zero-voltage switch from an external de
power supply connected between terminals 2 and 7_

307

ICAN-6182 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

120 V RMS. 5O-6O-Hz

,PERAT;cm

6.'

I

RS·S I( (JNl1lSrr

''''r~'~
'\,
\~
...

•

t\.

1;

iP~

..

~

Several techniques may be used to cope with the
half-cycling phenomenon. If the user can tolerate some
hystersis in the control, then positive feedback can be added
around the differential amplifier. Fig. II illustrates this
technique. The tabular data in the figure lists the
recommended values of resistors R I and R2 for different
sensor impedances at the control point.

'0'
2.

0

\\
•

3.

D

4
EXTERNAL LOAD OJRRENT-mA
92CS-22592

Fig. 9 - DC supply voltage as a function of external load current for

several values of dropping resistance RS.

Half-Cycling Effect

The method by which the zero-voltage switch senses the
zero crossing of the ac power results in a half-cycling
phenomenon at the control point. Fig. 10 illustrates this
phenomenon. The zero-voltage switch senses the zero-voltage
crossing every half-cycle, and an output, for example pulse
No.4, is produced to indicate the zero crossing. During the
remaining 8.3 milliseconds, however, the differential amplifier
in the zero-voltage switch may change state and inhibit any
further output pulses. The uncertainity region of the
differential amplifier, therefore, prevents pulse No.5 from
triggering the triac during the negative excursion of the ac line
voltage.

200K 18 IC

Fig. t 1 - CA3058 or CA3059 on-off controller with hysteresis.'

If a significant amount (greater than ±IO%) of controlled
hysteresis is required, then the circuit shown in Fig. 12 ·may be
employed. In this configuration, external transistor QI can be
used to provide an auxiliary timed-delay function.

TRIGGER
PULSES OUT
OFCA3059 fL--',-'-.y.-1jL-L.-',-'-..ljL-+--'1'--Y--Y--

VL

LOAD

VOLTAGE ~-4-+-+--~-+-+-"""---''--+-+--'

Fig. 10 - Ha/f-cycling phenomenon in the zero-voltage switch.

When a sensor with low sensitivity is used in the circuit, the
zero-voltage switch is very likely to operate in the linear mode.
In this mode, the output trigger current may be sufficient to
trigger the triac on the positive-going cycle, but insufficient to
trigger the device on the negative-going cycle of the triac
supply voltage. This effect introduces a half-cycling
phenomenon, i.e., the triac is turned on during the positive
half-cycle and turned off during the negative half-cycle.

308

rig. 12 - CA3058 or CA3059 on-off controller with controlled

hysteresis.

For applications that require complete elimination of
half-cycling without the addition of hysteresis, the circuit
shown in Fig. 13 may be employed. This circuit- uses a

~

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ICAN-6182

SENSITIVITY: CIRCUIT CHANGES STATE WHEN THERE
IS A CHANGE OF~ In
IN A 5K
SENSOR

n

120V
60,,-

NOTE: CIRCUIT DOES NOT EXHIBIT SPuRIOUS

• HALF-CYCLE· CONDUCTION EFFECTS

UCS-225M

Fig. 13 - Sensitive temperature control.

POSITIVE
SUPPLY VOL.TAGE
FOR BIAS
SYSTEM 1Vbl

CA3099E integrated-circuit programmable comparator with a
zero-volta,.e switch_ A block dia¥ram of CA3099E is shown in
Fig_ 14_ Because the CA3099E contains an integral flip-flop,
its output will he in either a "0" or "I" state. Consequently
the zero-voltage switch cannot operate in the linear mode, and
spurious half-cycling operation is prevented. When the
signal·input voltage at terminal 14 of the CA3099E is equal to
or less than the "low" reference voltage (LR), current flows
from the power supply through resistor R I, and a logic "0" is
applied to terminal 13 of the zero-voltage switch. This
condition turns off the triac. The triac remains off until the
signal-input voltage rises to or exceeds the "high" reference
voltage (HR), thereby effecting a change in the state of the
flip-flop so that a logic "I" is applied to terminal 13 of the
zero-voltage switch, and triggers the triac on.
"Proporational Control" Systems
The on-off nature of the contr~1 shown in Fig. I causes
some overshoot that leads to a definite steady-state error. The
addition of hysteresis adds further to this error factor.
However, the connections shown in Fig. 15(a) can be used to
add proportional control to the system. In this circuit, the
sense amplifier is connected as a free-running multivibrator. At
balance, the voltage at terminal 13 is much less than the
voltage at terminal 9. The output will be inhibited at all times
until the voltage at terminal 13 rises to the design differential
voltage between terminals 13 and 9; then proportional control
resumes. The voltage at terminal 13 is as shown in Fig. 15(b).
When this voltage is more positive ihan the threshold, power is

INTERNAL

B~~~ii

i .....

(lSIAS)

9

OUTPUT

CURRENT
CONTROL

SIGNAL INPUT

UNREGULATED
INPUT

REGULATED
OUTPUT

Y-

Fig. 14 - Block diagram of CA3099E integrated-circuit programmablel comparator.

309

ICAN-6182 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

As in the case of the hysteresis circuitry described earlier,
some special applications may require more sophisticated
systems to achieve either very precise regions of control or
very long periods.
Zero.voltage switching control can be extended to
applications in which it is desirable to have constant control of
the temperature and a minimization of system hysteresis. A
closed-loop top·burner control in which the temperature of
the cooking utensil is sensed and maintained at a particulitr
value is a good example of such an application; the circuit for
this control is shown in Fig. 17. In this circuit, a unijunction

(a)

TRIAC
OFF

TRIAC
ON

(b)

Fig. 17 - Schematic diagram of proportional zero-voltage-$w;tching
92CS-22'97

Fig. 15 - Use of the CA3058 or CA3059 in a typical heating control
with proportional control; fa} schematic diagram, and
(bJ waveform of voltage at terminal 13.

applied to the load so that the duty cycle is approximately 50.
per cent. With a 0.1 megohm sensor and values of Rp =
0.1 megohm, R2 = 10,000 ohms, and CEXT =10 microfarads,
a period greater than 3 seconds is achieved. This period should
be much shorter than the thermal time constant of the system.
A change in the value of any of these elements changes the
period, as shown in Fig. 16. As the resistance of the sensor
changes, the voltage on terminal 13 moves relative to V9. A
cooling sensor inoves VI3 in a positive direction. The triac is
on for a larger portion of the pulse cycle and increases the
average power to the load.

•

control.

oscillator is outboarded from the basic 'control by means of
the internal power supply of the zero·voltage switch. The
output of this ramp generator is applied to terminal 9 of the
zero·voltage switch and establishes a varied reference to the
differential amplifier. Therefore, gate pulses are applied to the
triac whenever the voltage at terminal 13 is greater than the
voltage at terminal 9. A varying duty cycle is established in
which the load is predominantly on with a cold sensor and
predominantly off with a hot sensor. For precise temperature
regulation, the time base of the ramp should be shorter than
the thermal time constant of the system but longer than the
period of the 60·Hz line. Fig. 18, which contains various
waveforms for the system of Fig. 17, indicates that a typical
variance of ±O.s°C might be expected at the sensor contact to
the utensil. Overshoot of the set temperature is minimized
with this approach, and scorching of any type is minimized.

CEXT·'O,..f

"2
:0'

9i
I
N

or

•
•
•
a

.•~f-~Ra.RP.82K
lOOK

I

-- r--

VPI~9
I

I

I
I
I

I~ !S:1
20

40

60

I

MM~!
80

100

120

FIRING RATE (FLASHES/MINUTE)
92CS-22598

Fig. 16 - Effect of variations in time-constant elements on period.

310

I

.2CM-ZO.,9

Fig, IS-Waveforms lor the c;rcuit of Fig. 17.

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ICAN-6182

Effect of Thyristor Load Characteristics
The zero-voltage switch is designed primarily to gate a
thyristor that switches a resistive load. Because the output
pulse supplied by the switch is of short duration, the latching
current of the triac becomes a significant factor in determining
whether other types of loads can be switched. (The
latching-current value determines whether the triac will remain
in conduction after the gate pulse is removed.) Provisions are
included in the zero-voltage switch to accommodate inductive
loads and low-power loads. For example, for loads that are less
than approximately 4 amperes rms or that are slightly
inductive, it is possible to retard the output pulse with respect
to the zero-voltage crossing by insertion of the capacitor Cx
from terminal 5 to terminal 7. The insertion of capacitor Cx
permits switching of triac loads that have a slight inductive
component and that are greater than approXimately 200 watts
(for operation from an ac line voltage of 120 volts rms).
However, for loads less than 200 watts (for example,
70 watts), it is recommended that the user employ the
T2300B* sensitive-gate triac with the zero-voltage switch
because of the low latching-current requirement of this triac.
For loads that have a low power factor, such as a solenoid
valve, the user may operate the zero-voltage switch in the de

mode. In this mode, terminal 12 is connected to terminal 7,
and the zero-crossing detector is inhibited. Whether a "high"
or "low" voltage is produced at terminal 4 is then dependent
only upon the state of the differential comparator within the
integrated-eircuit zero-voltage switch, and not upon the zero
crossingof the incoming line voltage. Of course, in this mode
of operation, the zero-voltage switch no longer operates as a

zero-voltage switch. However, for many applications that
involve the switching of low-current inductive loads, the
amount of RFI generated can frequently be tolerated.
For switching of high-eurrent inductive loads, which must
be turned on at zero line current, the triggering technique
employed in the dual-output over-under temperature
controller and the transient-free switch controller described
subsequently in this Note is recommended:

sensing amplifier. Although the RFI-eliminating function of
the zero-voltage switch is inhibited when the zero-crossing
detector is disabled, there is no problem if the load is highly
inductive because the current in the load cannot change
abruptly.
Circuits that use a sensitive-gate triac to shift the firing
point of the power triac by approximately 90 degrees have
been designed. If the primary load is inductive, this phase shift
corresponds to firing at zero current in the load. However,

changes in the power factor of the load or tolerances of
components will cause errors in this firing time.
The circuit shown in Fig. 19 uses a CA3086
integrated-circuit transistor array to detect the absence of load
current by sensing the voltage across the triac. The internal
zero-crossing detector is disabled by connection of terminal 12
to terminal 7, and control of the output is made through the
external inhibit input, terminal I. The circuit permits an
output only when the voltage at point A exceeds two V BE
drops, or 1.3 volts. When A is positive, transistors Q3 and Q4
conduct and reduce the voltage at terminal I below the inhibit
state. When A is negative, transistors QJ and Q2 conduct.
When the voltage at point A is less than ±1.3 volts, neither of
the transistor pairs conducts; terminal I is then pulled positive
by the current in resistor R3, and the output in inhibited.

Rp

120 VAC
50- 60Hz

NTC

SENSOR

Switching of Inductive Loads
For proper driving of a thyristor in full-cycle operation,
gate drive must be applied soon after the voltage across the
device reverses. When resistive loads are used, this reversal

occurs as the line voltage reverses. With loads of other power
factors, however, it occurs as the current through the load
becomes zero and reverses.
There are several methods for switching an inductive load at
the proper time. If the power factor of the load is high (i.e., if
the load is only slightly inductive), the pulse may be delayed
by addition of a suitable capacitor between terminals 5 and 7,
as described previously. For highly inductive loads, however,
this method is not suitable, and different techniques must be
used.
If gate current is continuous, the triac automatically
commutates because drive is always present "'hen the voltage
reverses. This mode is established by connection of terminals 7
and 12. The zero-erossing detector is then disabled so that
current is supplied to the triac gate whenever called for by the

92CS-2Z601

Fig. 19 - Use of the CA3058 or CA3059 together with CA3086 for

switching inductive loads.

The circuit shown in Fig. 19 forms a pulse of gate current
and can supply high peak drive to power traics with low
average current drain on the internal supply. The gate pulse
will always last just long enough to latch the thyristor so that

• Fonnerly RCA 40526

311

ICAN-6182
there is no problem with delaying the pulse to an optimum
time. As in other circuits of this type, RFI results if the load is

voltage across it to drop and thus ends the gate pulse. If the
latching current has not been attained, another gate pulse

not suitably inductive because the zero-crossing detector is

forms, but no discontinuity in the load current occurs.

disabled and initial turn·on occurs at random.
The gate pulse forms because the voltage at point A when
the thyristor is on is less than 1.3 volts: therefore, the output
of the zero-voltage switch is inhibited, as described above. The
resistor divider R I and R2 should be selected to assure this
condition. When the triac is on, the voltage at point A is

Provision of Negative Gate Current

Triacs trigger with optimum sensitivity when the polarity of
the gate voltage and the voltage at the main terminal 2 are
similar 0+ and II' modes). Sensitivity is degraded when the
polarities are opposite (I' and 111+ modes). Although RCA

approximately one-third of the instantaneous oo-state voltage

both 1- and 111+ modes, some other types have very poor

triaes are designed and specified to have the same sensitivity in

(vr) of the thyristor. For most RCA thyristors, vr (max) is

sensitivity in the 111+ condition. Because the zero·voltage

less than 2 volts, and the divider shown is a conservative one.

switch supplies positive gate pulses, it may not directly drive
some higher·current triacs of these other types.
The circuit shown in Fig. 20(a) uses the negative·going
voltage at terminal 3 of the zero-voltage switch to supply a
negative gate pulse through a capacitor. The curve in
Fig. 20(b) shows the approximate peak gate current as a
function of gate voltage VG. Pulse width is approximately

When

the load current passes through zero, the triac

commutates and turns off. Because the circuit is still being

driven by the line voltage, the current in the load attempts to
reverse, and voltage increases rapidly across the "turned-off'
triac. When this voltage exceeds 4 volts, one portion of the
CA3086 conducts and removes the inhibit signal to permit
application of gate drive. Turning the triac on causes the

80 microseconds.
Operation with Low-I mpedance Sensors

Although the zero-voltage switch can operate satisfactorily
with a wide range of sensors, sensitivity is reduced when
sensors with impedances greater than 20,000 ohms are used.

Typical sensitivity is one per cent for a SOOO-ohm sensor and
increases to three per cent for a D.l-megohm sensor.

Low-impedance sensors present a different problem. The
sensor bridge is connected across the internal power supply

120 VAC

6OH,

and causes a current drain. A SOOO-ohm sensor with its
associated SOOO-ohm series resistor draws less than

IO<¥

I~VDC

1 milliampere. On the other hand, a 300-ohm sensor draws a

current of 8 to 10 milliampers from the power supply.
Fig. 21 shows the 600-ohm load line of a 300-ohm sensor
on a redrawn power·supply regulation curve for the
zero-voltage switch. When a 1O,OOO-ohm series resistor is used,

(aJ

0

0

the voltage across the circuit is less than 3 volts and both
sensitivity and output current are significantly reduced. When
a SOOO·ohm series resistor is used, the supply voltage is nearly

'\

5 volts, and operation is approximately normal. For more
consistent operation, however. a 4000-ohm series resistor is
recommended.

1\

\

0

0

\
1\

-I

(bl

-2

GATE VOLTAGE IVG1-V

-,
92CS-22602

Fig. 20 - Use of the CA3058 or CA3059 to provide negative gate
pulses: (aJ schematic diagram; (b) peak gate current (at
terminal 3) as a function of gate voltage.

312

Fig. 21 - Power·supply regulation of the CA3058 or CA3059 with a
300-ohm sensor (600-ohm load) for two values of series
resistor.

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ICAN-6182

Although positive-temperature-coefficient (PTC) sensors
rated at 5 kilohms are available, the existing sensors in ovens
are usually of a much lower value. The circuit shown in Fig. 22
is offered to accommodate these inexpensive metal-wound

Further cycling depends on the voltage across the sensor.
Hence, very low values of sensor and potentiometer resistance

can be used in conjunction with the zero-voltage switch power
supply without causing adverse loading effects and impairing
system performance.
Interfacing Techniques
Fig. 24 shows a system diagram that illustrates the role of
the zero-voltage switch and thyristor as an interface between
the logic circuitry and the load. There are several basic
LOADS
AND

MECHANISMS

COMPUTER OR
!-OGIC OUTPUT

%

MOTORS

+

SOLENOIDS

11111

~
HE~T.ERS

~

Fig. 22 - Schematic diagram of circuit for use with low-resistance

LAMPS

ZERO-VOLTAGE

sensor.

sensors.

A

SWITCH

schematic

diagram

of the

RCA

INTERFACING I C

CA3080

powtR

SENSORS

THYRISTORS

1/

-S-

PHOTO-CELLS

integrated·circuit operational transconductance amplifier used
in Fig. 22, is shown in Fig. 23. With an amplifier bias current,

IA Be, of 100 microamperes, a forward transconductance of
2 milliohms is achieved in this configuration. The CA3080
switches when the voltage at terminal 2 exceeds the voltage at
terminal 3. This action allows the sink current, 1" to flow
from terminal13 of the zero-voltage switch (the input
impedance to terminal13 of the zero-voltage switch is
approximately 50 kilohms); gate pulses are no longer applied
to the triac because Qi of the zero-voltage switch is on. Hence,
if the PTC sensor is cold, i.e., in the low resistance state, the
load is energized. When the temperature of the PTC sensor
increases to the desired temperature, the sensor enters the high
resistance state, the voltage on terminal 2 becomes' greater
than that on terminal 3, and the triac switches the load off.

SOLID-STATE

~

TH~~~f~~RS
-~
LIMIT
SWITCHES
92CS'22605

Fig. 24 - The zero-voltage switch and thyristor as an interface.

interfacing techniques. Fig. 25(a) shows the direct input
technique. When the logic output transistor is switched from
the on state (saturated) to the off state, the load will be
turned on at the next zero-voltage crossing by means of the
interfacing zero-voltage switch and the triac. When the logic
output transistor is switched back to the on state,
zero-crossing pulses from the zero-voltage switch to the triac

(a)

(b)

Fig. 23 - Schematic diagram of the CA30BO.

Fig. 25 - Basic interfacing techniques: fa) direct input: fbJ isolated
input.

313

ICAN-6182 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

gate will immediately cease. Therefore, the load will be turned ! off to on. The light sensor is connected to the differential
amplifier input of the zero-voltage switch, which senses the
off when the triac commutates off as the sine-wave load
change of impedance at a threshold level and switches the load
current goes through zero. In this manner, both the turn-on
on as in Fig. 25(a).
and tum-off conditions for the load are controlled.
When electrical isolation between the logic circuit and the
Sensor Isolation
load is necessary, the isolated-input technique shown in
In many applications, electrical isolation of the sensor from
Fig. 25(b) is used. In the technique shown, optical coupling is
the ac input line is desirable. Two common isolation
used to achieve the necessary isolation. The logic output
techniql;les are shown in Fig. 26.
transistor switches the Iight-source portion of the isolator. The
Transformer Isolation - In Fig. 26(a), a pulse transformer
Iight-sensor portion changes from a high impedance to a low
is used to provide electrical· isolation of the sensor from
impedance when the logic output transistor is switched from
incoming ac power lines: The pulse transformer TJ isolates the

1.8 K

IW

.

I~

I.vue

T230lB

120VAC
6OH.

T,
PULSE
TRANSFORMER

J~ ~ii

"'~_--J.

"T2L-K-NI-GH-T--------------------~-------------------SP-R-AG~UE
54£-1421
(OR EQUIY.)

11212
lOR EOUIV.)

• FORMERLY RCA 40691

(a)

120VAC
60Hz

100,..PHOTO

COUPLED
ISOLATOR

INPU]--

I
J

(b)

~

I
I
I

___ ..J

92CL-l!2601

Fig. 26 - Zero-voltage switch (a) on-off controller with an isolated
sensor, (b) on-off controller with photocoupler.

314

MT2

V,

MT,

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ICAN-6182

sensor from terminal No. I of the triac Y I, and transformer
T2 isolates the CA3058 or CA3059 from the power lines.
Capacitor C1 shifts the phase of the output pulse at terminal
No.4 in order to retard the gate pulse delivered to triac Y 1 to
compensate for the small phase-shift introduced by
transformer T I.
Photocoupler Isolation - In Fig. 26(b), a photocoupler
provides electrical isolation of the sensor logic from the
incoming ac power lines. When a logic "\" is applied at the
input of the photocoupler, the triac controlling the load will
be turned on whenever the line voltage passes through zero.
When a logic "0" is applied to the photocoupler, the triac will
turn off and remain off until a logic "\" appears at the input
of the photocoupler.

technique, less power is supplied to the load (reduced duty
cycle) as the error signal is reduced (sensed temperature
approaches the set temperature).
TEMPERATURE
SETTING

/

DIFFERENTIAL
< t O.5·C

TIME

(b)

(a)

TEMPERATURE CONTROLLERS

Fig. 27
shows
a
triac
used in an on-off
temperature-controller configuration. The triac is turned on at
zero voltage whenever the voltage Vs exceeds the reference

Fig. 28 - Transfer characteristics of fa} on-off and (bJ proportional

control systems.

Before such a system is implemented, a time base is chosen
so that the on-time of the triac is varied within this time base.
The ratio of the on-to-off time of the triac within this time
interval depends on the thermal time constant of the system
and the selt;cted temperature setting. Fig. 29 illustrates the
principle of proportional control. For this operation, power is
supplied to" the load until the ramp voltage reaches a value
greater than the dc control signal supplied to the opposite side
of the differential amplifier. The triac then remains off for the
remainder of the time-base period. As a result, power is

I20VAC

6OH.

I~
15VDC+

"proportioned" to the load in a direct relation to the heat

demanded by the system.

LEVEL

I~ :liii~...

LEVEL 2
LEVEL 3
92CS-ZZ608

Fig. 27 - CA3058 or CA3059 on-off temperature controller.

voltage V r . The transfer characteristic of this system, shown in
Fig. 28(a), indicates significant thermal overshoots and
undershoots, a well-known characteristic of such a system. The
differential" or hysteresis of this system, however, can be
further increased, if desired, by the addition of positive
feedback.
For precise temperature-control applications, the
proportional-control technique with synchronous switching is
employed. The transfer curve for this type of controller is
shown in Fig. 28(b). In this case, the duty cycle of the power
supplied to the load is varied with the demand for heat
required and the thermal time constant (inertia) of the system.
For example, when the temperature setting is increased in an
on-off type of controller, full power (100 per cent duty cycle)
is supplied to the system. This effect results" in significant
temperature excursions because there is no anticipatory circuit
to reduce the power gradually before the actual set
temperature is achieved. However, in a proportional control

g~

-F~~~llill-~~~+

2'%
POWER

50%
POWER

POWER

OUTPUT

OUTPUT

OUTPUT

75%

POWER

J~
3

2

TI"'E-"-

Fig. 29 - Principles of proportional control.

For this application, a simple ramp generator can be
realized with a minimum number of active and passive

components. A ramp having good linearity is not required for
proportional operation" because of the nonlinearity of the
thermal system and the closed-loop type of control. In the
circuit shown in Fig. 30, the ramp voltage is generated when
the capacitor CI charges through resistors Ro and RI' The
time base of the ramp is determined by resistors R2 and R3,
capacitor CZ, and the breakover voltage of the D3202U* diac .

• Formerly RCA 45412

315

ICAN-6182 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

AC

TYPE
IN3193

IN Q--.t-~-,

120VAC
60Hz

.,

IMEG

TO PIN 2

·0

Vcc+6V

IN
TO PIN 9

1-+i~I-.,_~~f'l.l-"';,~olln-r-_<&OUTPUT
__+-__

TO PIN 7

~L__ _~~--~~~

COMMON

-FORMERLY RCA45412

ALL RESISTORS 112 WATT
UNLESS OTHERWISE SPECIFIED

PIN CONNECTIONS REFER TO
RCA CA3058 OR CA3059

Fig. 30 - Ramp generator.

lag the incoming line voltage. The motors, however, are
switched by the triacs at zero current, as shown in Fig. 32(b).
The problem of driving inductive loads such as these motors
by the narrow pulses generated by the zero-voltage switch is
solved by use of the sensitive-gate RCA40526 triac. The high
sensitivity of this device (3 milliamperes maximum) and low
latching current (approximately 9 milliamperes) permit
synchronous operation of the temperature-controller circuit.
In Fig. 32(a), it is apparent that, though the gate pulse Vg of
triac Y 1 has elapsed, triac Y2 is switched on by the current
through RL I. The low latching current of the RCA40526
triac results in diSSipation of only 2 ·watts in RLl, as opposed
to 10 to 20 watt, when devices that have high latching
currents are used.

When the voltage across C2 reaches approximately 32 volts,
the diac switches and turns on the 2N697S transistor and
lN914 diodes. The capacitor CI then discharges through the
collector-to-emitter junction of the transistor. This discharge
time is the retrace or flyback time of the ramp. The circuit
shown can generate ramp times ranging from 0.3 to
2.0. seconds through adjustment of R2.· For precise
temperature regulation, the time base of the ramp should be
shorter than the thermal time constant of the system, but long
with respect to the period of the 60-Hz line voltage. Fig. 31
shows a triac connected f,?r the proportional mode.

10K

"L

2W

(a)

.FORMERLY RCA 40526

(b)

Fig. 32 -.Dual output, over-under temperawre controller (a) circuit,
(bl voltage and cu"snt wallfJforms.
g2eS-Uelf

Fig. 31 - CA3058 or CA3059 proportional temperature controller.

Fig. 32(a) shows a dual-output temperature controller that
drives two triacs. When the voltage V, developed across the
temperature-sensing network exceeds the reference voltage
VR I, motor No. I turns on. When the voltage across the
network drops below the reference voltage VR2, motor No.2
turns on. ~ecause the motors are inductive, the currents 1M 1

316

Electric-Heat Application
For electric-heating applications, the RCA-2N5444
40-ampere triac and the zero-voltage switch constitute an
optimum pair. Such a combination provides synchronous
switching and effectively replaces the heavy-duty contactors
which easily degrade as a result of pitting and wearout from
the switching transients. The salient features of the 2N5444
40-ampere triac are as follows:

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ICAN-61B2

(I) 300-ampere single-surge capability (for operation at
60-Hz),
(2) a typical gate sensitivity of 20 milliamperes in the I(~
and mc+) modes,
(3) low on-state voltage of 1.5 volts maximum at
40 amperes, and
(4) available VDROM equal to 600 volts.
shows
the
circuit
diagram
of
a
Fig. 33
synchronous·switching heat·staging controller that is used for
electric heating systems. Loads as heavy as 5 kilowatts are
switched sequentially at zero voltage to eliminate RFI and
prevent a dip in line voltage that would occur if the full
25 kilowatts were to be switched simultaneously.
QI and Q4 are used as a constant-current source to charge
capacitor C in a linear manner. Transistor Q2 acts as a buffer
stage. When the thermostat is closed, a ramp voltage is
provided at output Eo. At approximately 3-second intervals,
each 5-kilowatt heating element is switched onto the power
system by its respective triac. When there is no further demand
for heat, the thermostat opens, and capacitor C discharges
through R, and R2 to cause each triac to turn off in the
reverse heating sequence. It should be noted that some
half·cycling occurs before the heating element is switched fully
on. This condition can be attributed to the inherent
dissymmetry of the triac and is further aggravated by the
slow-rising ramp voltage applied to one of the inputs. The
timing diagram in Fig. 34 shows the turn·on and turn·off
sequence of the heating system being controlled.
Seemingly, the basic method shown in Fig. 33 could be
modified to provide proportional control in which the number
of heating elements switched into the system, under any given

,

4

TIME-SECONDS

Fig. 34 - Ramp-voltage waveform for the heat-staging controller.

thermal load, would be a function of the BTU's required by
the system or the temperature differential between an indoor
and outdoor sensor within the total system environment. That
is, the closing of the thermostat would not switch in all the
heating elements within a short time interval, which inevitably
results in undesired temperature excursions, but would switch
in only the number of heating elements required to satisfy the
actual heat load.
Oven/Broiler Control
Zero·voltage switching is demonstrated in the oven control
circuit shown in Fig. 35. In this circuit, a sensor element is
included in the oven to provide a closed-loop system for
accurate control of the oven temperature.
As shown in Fig. 35, the temperature of the oven can be
adjusted by means of potentiometer R" which acts, together
with the sensor, as a voltage divider at terminal 13. The voltage

120I/AC

6OH,

I/ISA

2.7K

ALL RESISTORS 1/2 WATT
UNLESS OTHERWISE SPECIFIED.

TRANSISTORS Q I ,Q2 AND 04
ARE PART OF RCA -CA3096E
INTEGRATED-CIRCUIT N-P-N/P-N-P
TRANSISlOR ARRAY

EO

Fig. 33 - Synchronous-switching heat-staging controller using a series
of zero-voltage switches.

317

ICAN-6182 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

rr:.,

BROILER

SWr'____~____~<~

220 V
AC

1

'~

I

NTC
SENSOR
L2cr--------~--------------------__~
92CS-22616

Fig. 35 - Schematic diagram of basic oven control.

at terminal 13 is compared to the fixed bias at terminal 9
which is set by internal resistors ~ and Rs. When the oven is
cold and the resistance of the sensor is high, transistors Q2 and
Q4 are off, a pulse of gate current is applied to the triac, and
heat is applied to the oven. Conversely, as the desired
temperature is reached, the bias at terminal 13 turns the triac
off. The closed-loop feature then cycles the oven element on
and off to maintain the desired temperature to approximately
±2°C of the" set value. Also, as has been noted, external
resistors between terminals \3 and 8, and 7 and 8, can be used
to vary this temperatun; and provide hysteresis. In Fig. I I, a

circuit that provides approximately IO-per-cent hysteresis is
demonstrated.
In addition to allowing the selection of a hysteresis value,
the flexibility of the control circuit permits incorporation of
other features. A PTC sensor is readily used by intet\lhanging
terminals 9 and \3 of the circuit shown in Fig. 35 and
substituting the PTC for the NTC sensor. In both cases, the
sensor element is directly returned to "the system ground or
common, as is often desired. Terminal 9 can be connected by
external resistors to provide for a variety of biasing, e.g., to
match a lower-resistance sensor for which the switching-point
voltage has been reduced to maintain the same sensor current.
To accommodate the self-cleaning feature, external
switching, which enables both broiler and oven units to be
paralleled, can easily be incorporated in the design. Of course,
the potentiometer must be capable of a setting such that the
sensor, which must be characterized for the high, self-clean
temperature, can monitor and establish control of the
high-temperature, self-clean mode. The ease with which this
seif·clean mode can be added makes the over-all solid-state
systems cost·competitive with electromechanical systems of
comparable capability. In addition, the system incorporates
solid-state reliability while being neater, more easily calibrated,
and containing Iess-costly system wiring.
Integral-Cycle Temperature Controller INo half·cycling)
If a temperature controller which is completely devoid of
half-cycling and hysteresis is required, then the circuit shown
in Fig. 36 may be used. This type of circuit is essential for
applications in which half-cycling and the resultant dc
component could cause overheating of a power transformer on
the utility lines .

••• w
I/ZW
"

Rp
I~

15V1lC

I.
2W

IZCVAC
6OH.

...~KW

LOAD

HEATERI
RL

O.5,J'
200

v DC

*

FOR PROPORTIONAL OPERATION OPEN TERMINALS 10,11, AND 13, AND CONNECT POSITIVE RAMP VOLTAGE TO TERMINAL 13
... ,..SELECTED FOR IGT-6 mA MAXIMUM .
• FORMERLV RCA 44003
• FORMERLY RCA

40&~~

Fig. 36 - Integral-cyclB temperature controller in which half-cycling effect ;s eliminated.

318

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ICAN-6182

In the integral-cycle controller, when the temperature being
:ontrolled is low, the resistance of the thermistor is high, and
10 output signal at terminal 4 of zero volts is obtained. The
5CR (YI), therefore, is turned off. The triac (Y2) is then
triggered directly from the line on positive cycles of the ac
fOltage. When Y2 is triggered" and supplies power 10 the load
RL, capacitor C is charged to the peak of the input voltage.
lVhen the ac line swings negative, capacitor C discharges
through the triac gate to trigger the triac on the negative
~alf-cycle. The diode.resistor.capacitor "slaving network"
triggers the triac on negative half-cycle to provide only integral
:ycles of ac power to the load.
When the temperature being controlled reaches the desired
~a\ue, as determined by the thermistor, then a positive voltage
level appears at terminal 4 of the zero-voltage switch. The SCR
Ihen starts to conduct at the beginning of the positive input
:ycie to shunt the trigger current away from the gate of the
triac. The triac is then turned off. The cycle repeats when the
5CR is again turned OFF by the zero·voltage switch.
The circuit shown in Fig. 37 is similar to the configUration
in Fig. 36 except that the protection circuit incorporated in
the zero-voltage switch can be used. In this new circuit, the
NTC sensor is connected between terminals 7 and 13, and
transistor Qo inverts the signal output at terminal 4 to nullify
the phase reversal introduced by the SCR (Y d. The internal
~ower supply of the zero-voltage switch supplies bias current
to transistor Qo .

Of course, the circuit shown in Fig. 37 can readily be
converted to a true proportional integral-cycle temperature
conlroUer simply by connection of a positive·going ramp
voltage to terminal9 (with terminals 10 and II open), as
previously discussed in this Note.
Thermocouple Temperature Control
Fig. 38 shows the CA3080A operating as a pre.amplifier for
the zero·voltage switch to form a zero·voltage switching circuit
for use with thermocouple sensors.

92CS-Zl619

Fig. 38 - Thermocouple
switching.

temperature

control

"

2N5444

5~W

2.2K
5W

with

zero.voltage

MT,

'2

'K

II2W

"
RCA*'*C 526000

120VAC

01201B-

2N697S

60 H.

,W

IK

I

5KW

LOAD

(HEATER)

RL
O.5~r

lODV DC

*"

C

FOR PROPORTIONAL OPERATIOfol OPEN TERMINALS 9,10 AND II AND CONNECT POSTIVE RAMP VOLTAGE TO TERMINAL 9

**SELECTED FOR IGT"6 mA MAXIMUM
_FORMERLY RCA 44003
_FORMERLY RCA 40655

Fig. 37 - CA3058 or CA3059 integral-cycle temperature controller
that features a protection circuit and no half-cycling effect.

319

ICAN-6182 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

MACHINE CONTROL AND AUTOMATION

The earlier section on interfacing techniques indicated
several techniques of controlling ac loads through a logic
system. Many types of automatic equipment are not complex
enough or large enough to justify the cost of a flexible logic
system. A special circuit, designed only to meet the control
requirements of a particular machine, may prove more
economical. For example, consider the simple machine shown
in Fig.39; for each revolution of the motor, the belt is
advanced a prescribed distance, and the strip is then punched.
The machine also has variable speed capability.

b.

Minimized generation of EMI/RFI using zero-voltage
switching techniques in conjunction with thyristors.
c.
Elimination of high-voltage transients generated by
relaYoOontact bounce and contacts breaking inductive
loads, as shown in Fig. 39.
d. Compactness of the control system.
Theentire control system could be on one printed-circuit
board, and an over-all cost advantage would be achieved.
Fig. 41 is a timing diagram for the proposed solid-state
ZEROCROSSING

PULSE
60 HI'

MACHINE
RATE

----1 : 1'>-10 ms
ONE
REVOLUTION
MaTOR

r-----

:

MACHINE;

-~, REP. RATE-:-

:

---I

SOLENOID

OPERATION _ _ _ _ _ _-/1-_-'--'=="'-...'""---11--_ __
92CS-22622

Fig. 41 - Timing diagram for proposed solid-state machine control.
92CS-22620

Fig. 39 - Step-and-punch machine.

The typical electromechanical control circuit for such a
machine might consist of a mechanical cambank driven by a
separate variable speed motor, a time delay relay, and a few
logic and power relays. Assuming use of industrial-grade
controls, the control system could get quite costly and large.
Of greater importance is the necessity to eliminate transients
generated each time a relay or switch energizes and deenergizes
the solenoid and motor. Fig. 40 shows such transients, which
might not affect the operation of this machine, but could
affect the more sensitive solid-state equipment operating in the
area.

A more desirable system would use triacs and zero-voltage
switching to incorporate the following advantages:
a.
Incteased reliability and long life inherent in
solid-state devices as opposed to moving parts and
contacts associated with relays.

UNE

YOLTAGEf--I--i--+-_f--Ir--I_-t_-f-_

RANDOM

TURN-OFF

machine control, and Fig.42 is the corresponding control
schematic. A variable-speed machine repetition rate pulse is set
up using either a unijunction oscillator or a transistor astable
multivibrator in conjunction with a lO-millisecond one-shot
multivibrator. The first zero-voltage switch in Fig. 42 is used
to synchronize the entire system to zero-voltage crossing. Its
output is inverted to simplify adaptation to the rest of the
circuit. The center zero-voltage switch is used as an interface
for the photo-cell, to control one revolution of the motor. The
gate drive to the motor triac is continuous dc, starting at zero
voltage crossing. The motor is initiated when both the machine
rate pulse and the zero-voltage sync are at low voltage. The
bottom zero-voltage switch acts as a time-delay for pulsing the
solenoid. The inhibit input, terminal I, is used to assure that
the solenoid will not be operated while the motor is running.
The time delay can be adjusted by varying the reference level
(SOK potentiometer) at terminal 13 relative to the capacitor
charging to that level on terminal 9. The capacitor is reset by
the SCR during the motor operation. The gate drive to the
solenoid triac is direct current. Direct current is used to trigger
both the motor and solenoid triacs because it is the most
desirable means of switching a triac into an inductive load. The
output of the zero-voltage switch will be continuous dc by
connecting terminal 12 to common. The output under de
operation shOUld be limited to 20 milliamperes. The motor
triac is synchronized to zero crossing because it is a
high-crurent inductive load and there is a chance of generating
RFI. The solenoid is a very low current inductive . load, so
there would be little chance of generating RFI: therefore, the
initial triac turn-on can be random, which simplifies the
circuitry.

92CS-22621

Fig. 40 - Transients generated by relav-contact bounce and non-zero
turn-off of inductive load.

320

This example shows the versatility and advantages of the
RCA zero-voltage switch used in conjunction with triacs as
interfacing and control elements for machine controL

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ICAN-6182

6a_H'F\£D

_" ______ _

~l~~E

:

:

:

~

wi

i'6.67rr·~

I
LAMP ,
I
OUTPUT,

I

:
:

i
I

~I

II
I

W
92CS-2262~

Fig. 43 - Waveforms for 6O-Hz phase-controlled lamp dimmer.

~.

auLT'pMUPT

17.5ms t--- ___

...J

I

I

I

I

!

I

I

tA.

A

"'"

A

:
'REFERENCEI
:LEVELS
I

~VA

e\ _C!!_ f),.vetJ

e~\fIJZI\fI~fJ

y;,.

IvARIABLE

-VFV'

v

v

92C5-22625

Fig.

92C5-22623

Fig.

42 - Schematic of proposed solid-stare machine control.

400-Hz TRIAC APPLICATIONS

The increased complexity of aircraft control systems, and
the need for greater reliability than electromechanical
switching can offer, has led to the use of solid·state power
switching in aircraft. Because 400-Hz power is used almost
universally in aircraft systems, RCA offers a complete line of
triacs rated for 400·Hz applications. Use of the RCA
zero.voltage switch in conjunction with these 400-Hz triacs
results in a !Dinimum of RFI, which is especially important in
aircraft.
Areas of application for 400-Hz triacs in aircraft include:
a.
Heater controls for food-warming ovens and for
windshield defrosters.
b. Lighting controls for instrument panels and cabin
illumination
c. Motor controls
d. Solenoid controls
e. Power-supply switches
Lamp dimming is a simple triac application that
demonstrates an advantage of 400·Hz power over 60·Hz
power. Fig.43 shows the adjustment of lamp intensity by
phase control of the 60·Hz line voltage. RFI is generated by
the step functions of power each half cycle, requiring
extensive filtering. Fig. 44 shows a means of controlling power
to the lamp by the zero-voltage-switching technique. Use of
4OO-Hz power makes possible the elimination of complete or
half cycles within a period (typically 17.5 milliseconds)

44 -

Waveforms for 400-Hz zero-voltage-switched lamp dimmer.

without noticeable flicker. Fourteen different levels of lamp
intensity can be obtained in this manner. A line·synced ramp is
set up with the desired period and applied to terminal No.9 of
the differential amplifier within the zero·voltage switch, as
shown in Fig. 45. The other side of the differential amplifier
(terminal No. 13) uses a variable reference level, set by the
50K potentiometer. A change of the potentiometer setting
changes the lamp intensity.
In 400·Hz applications it may be necessary to widen and
shift the zero·voltage switch output pulse (which is typically
12 microseconds wide and centered on zero voltage crossing),
to assure that sufficient latching current is available. The 4K
resistor (terminal No. 12 to common) and the
O.OI5·microfarad capacitor (terminal No.5 to common) are
used for this adjustment.

RAMP

LINESYNCED

v.

RAMP

I
92C5-22626

Fig. 45 - Circuit diagram

for 400-Hz zero-voltage-switched lamp

dimmer.

321

ICAN-6182 _ _ _ _ _ _ _ _ _ _---'_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

SOLID-STATE TRAFFIC FLASHER

Another application which illustrates the versatility of the
zero-voltage switch, when used with RCA thyristors, involves
switching traffic-controllamps. In this type of application, it is
essential that a triac withstand a current surge of the lamp load
on a continuous basis. This surge results from the difference
between the cold and hot resistance of the tungsten filament.
If it is assumed that triac tum-on is at 90 degrees from the
zero·voltage crossing, the first current-surge peak is
approximately ten times the peak steady-state value or fifteen
times the steady·state rms value. The second current-surge
peak is approximately four times the steady·state rms value.

Transistors QI and Q2 inhibit these pulses to the gates of the
triacs until the triacs tum on by the logical "I" (Vee high)
state of the flip-flop.
The arrangement described can also be used for a
synchronous, sequential traffic-controller system by addition
of one triac, one gating transistor, a "divide-by-three" logic
circuit, and modification in the design of the diac pulse
generator. Such a system can control the familiar red, amber,
and green traffic signals that are found at many intersections.
SYNCHRONOUS LIGHT FLASHER

Fig. 47
shows
a
simplified
version
of
the
synchronous·switching traffic light flasher shown in Fig. 46 .

• FORMERLY RCA 45412

• FORMERL. Y RCA 40668

Fig. 46 - Svnchronous-switching traffic flasher.

When the triac randomly switches the lamp, the rate of
current rise di/dt is limited only by the source inductance. The
triac di/dt rating may be exceeded in some power systems. In
many cases, exceeding the rating results in excessive current
concentrations in a small area of the device which may
produce a hot spot and lead to device failure. Critical
applications. of this nature require adequate drive to the triac
gate for fast tum-on. In this case, some inductance may be
required in the load circuit to reduce the initial magnitude of
the load current when the triac is passing through the active
region. Another method may be used which involves the
switching of the triac at zero line voltage. This method
involves the supply of pulses to the triac gate only during the
presence of zero voltage on the ac line.
Fig. 46 shows a circuit in which the lamp loads are switched
at zero line voltage. This approach reduces the initial di/dt,
decreases the required triac surge-current ratings, increases the
operating lamp life, and eliminates RFI problems. This circuit
consists of two triacs, a flip-flop (FF-I), the zero-voltage
switch, and a diac pulse generator. The flashing rate in this
circuit is controlled by potentiometer R, which provides
between 10 and 120 flashes per minute. The state of FF-I
determines the triggering of triacs Y1 or Y2 by the output
pulses at terminal 4 generated by the zero-crossing circuit.

322

Flash rate is set by use of the curve shown in Fig. 16. If a more
precise flash rate is reqUired, the ramp generator described
previously may be used. In this circuit, ZVSI is the master
control unit and ZVS2 is slaved to the output of ZVSI
through its inhibit terminal (terminal I). When power is
applied to lamp No. I, the voltage of terminal 6 on ZVSI is
high and ZVS2 is inhibited by the current in Rx. When lamp

92CS-22628

Fig. 47 - Synchronous light flasher.

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ICAN-6182

No. I is off, ZVS2 is not inhibited, and triac Y2 can fire. The
power supplies operate in parallel. The on-off sensing amplifier
in ZVS2 is not used.
TRANSIENT-FREE SWITCH CONTROLLERS

The zero-voltage switch can be used as a simple solid-state
switching device that permits ac currents to be turned on or
off with a minimum of electrical transients and circuit noise.
The circuit shown in Fig. 48 is connected so that, after the
control terminal 14 is opened, the electronic logic waits until
the power-line voltage reaches a zero crossing before power is
applied to the load ZL. Conversely, when the control terminals
are shorted, the load current continues until it reaches a zero
crossing. This circuit can switch a load at zero current whether
it is resistive or inductive.
The circuit shown in Fig.49 is connected to provide the
opposite control logic to that of the circuit shown in Fig. 48.
That is, when the switch is closed, power is supplied to the
load, and when the switch is opened, power is removed from
the load.
In both configurations, the maximum rms load current that
can be switched depends on the rating of triac Y2. If Y2 is an
RCA-2N5444 triac, an rms current of 40 amperes can be
switched.
DIFFERENTIAL COMPARATOR FOR INDUSTRIAL USE

Differential comparators have found widespread use as limit
detectors which compare two analog input signals and provide
a go/no-go, logic • one" or logic "zero" output, depending

O.II'F
25VDC

upon the relative magnitudes of these signals. Because the
signals are often at very low voltage levels and very accurate
discrimination is normally required between them, differential
comparators in many cases employ differential amplifiers as a
basic building block. However, in many industrial control
applications, a high-performance differential comparator is not
reqUired. That is, high resolution, fast switching speed, and
similar features are not essential. The zero-voltage switch is
ideally suited for use in such applications. Connection of
terminal 12 to terminal 7 inhibits the zero-voltage threshold
detector of the zero-voltage switch, and the circuit becomes a
differential comparator.
Fig. 50 shows the circuit arrangement for use of the
zero-voltage switch as a differential comparator. In this
application, no external dc supply is required, as is the case
with most commercially available integrated-circuit
comparators; of course, the output-current capability of the
zero-voltage switch is reduced because the circuit is operating
in the dc mode. The 1000-ohm resistor RC, connected
between terminal 4 and the gate of the triac,limits the output
current to apprOXimately 3 milliamperes.
When the zero-voltage switch is connected in the dc mode,
the drive current for terminal 4 can be determined from a
curve of the external load current as a function of dc voltage
from terminals 2 and 7. This curve is shown in the technical
bulletin for RCA integrated-circuit zero-voltage switches, File
No. 490. Of course, if additional output current is required, an
external dc supply may be connected between terminals 2

10K

2W

100

T23018-

I~

IIT2

15VOC+
I20VAC

6OH,

I.

1/2W

I

O.I,.F
200

v DC

z.

*IF Y
FOR EXAMPLE, IS A 40-AMPERE TRIAC. THEN
SUFFICIENT IGT FOR Y2'

R, MUST BE DECREASED TO SUPPLY

• FORMERLY RCA 40691

Fig. 48 - Zero-voltage switch transient-free switch ~ont~lIer in which
power is supplied to the load when the SWitch 1$ open.

323

ICAN-6182 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

10K

O.I",r
,25 VDC

2W

IO<¥F

15VDC+

120VAC
GO Hz

IK

0.1,.'
200
V DC

* IF

Y2' FOR EXAMPLE, IS A 40-AMPERE TRIAC, RI MUST BE DECREASED TO SUPPLY
IGT FOR Y2'

SUFFICIENT

• FORMERLY RCA 40691

Fig. 49 - Zero-voltage switch transient4ree switch controller in which
power ;s applied to the load when the switch is closed.

and 7, and resistor Rx (shown in Fig. 50) may be removed.
The chart below compares some of the operating
characteristics of the zero-voltage switch, when used as a
comparator, with a typical high-performance commercially
available integrated-circuit differential comparator.

Parameters
Sensitivity
Switching speed
(rise time)

Zero-Voltage
Switch
(Typical Values)
30mV

Typical
Integrated·Circuit
Comparator (710)
2mV

> 2O l1s

90ns

*4.5 V at';; 4 rnA

3.2 V at .;; 5.0 inA

RX

.W
5K

Zl
ANY POWER
FACTOR

'ZOYAC
GO Hz

Output drive
capability

* Refer to Fig. 20; RX equals 5000 ohms.
POWER ONE-SHOT CONTROL
Fig.S! shows a circuit which triggers a triac for one complete
half-cycle of either the positive or negative alternation of the
ac line voltage. In this circuit, triggering is initiated by the
push button PB-!, which produces triggering of the triac near
zero voltage even though the button is randomly depressed
during the ac cycle. The triac does not trigger again until the
button is released and again depressed. This type of logic is
required for the solenoid drive of electrically operated stapling

324

• f"M.RlY

RCA 406.'

Fig. 50 - Differenti.1 comparator using tho CA3058 or CA3059
integrated-circuit zero-voltage switch.

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ICAN-6182

1/3 C04007A
• FORMERLY RCA 40691

Fig. 51 - Block

diagram

of a power one-shot

control using a

zero-voltage switch.

guns, impulse hammers, and the like, where load-current flow
is required for only one complete half-cycle. Such logic can
also be adapted to keyboard consoles in which contact bounce
produces transmission of erroneous information.
In the circuit of Fig. 51, before the button is depressed,
both flip-flop outputs are in the "zero" state. Transistor QG is
biased on by the output of flip-flop FF-l. The differential
comparator which is part of the zero-voltage switch" is initially
biased to inhibit output pulses. When the push button is
depressed, pulses are generated, but the state of QG

determines the requirement for their supply to the triac gate.
The first pulse generated serves as a "framing pulse" and does
not trigger the triac but toggles FF-l. Transistor QG is then
turned off. The second pulse triggers the triac and FF-J which,
in turn, toggles the second flip-flop FF-2. The output of FF-2
turns on transistor Q7, as shown in Fig. 52, which inhibits all
further output pulses. When the pushbutton is released, the
circuit resets itself until the process is repeated with the
button. Fig. 53 shows the timing diagram for the described
operating sequence.

Fig. 52 - Circuit diagram for the power one-shot control.

325

ICAN·6182 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

1~~I~z1f----..I'-------'<-----..,if-----+--

VOLTAGE!
PIN

®

OF ZERO SW
of---~L----_HH_----i4L---~~--

ff:..L

PIN 2

ff..:!

PIN I

~

PIN 12

VL~Df---------~----~--------

T1ME--

Fig. 53 - Timing diagram for the power one-shot control.

5K

ZERO
VOLTAGE
DETECTOR

5K

LINE 120YAC
INPUT 60Hl:

O.II£F

l
• FORMERLY RCA 4066B

10K

Fig. 54 - Phase Control circuit using a CA3058 or CA3059 and
CA3OB6 integrated.,;;rcuits.

326

tltW

_________________________________________________________ ICAN-6182

PHASE CONTROL CIRCUIT
Fig. 54 shows a circuit using a CA3058 or CA3059
zero-voltage
switch
together
with
two
CA3086
integrated-circuit transistor arrays to form a phase-control
circuit. This circuit is specifically designed for speed control of I
ac induction motors, but may also be used as a light dimmer.
The circuit, which can be operated from a line frequency of
50·Hz to 400-Hz, consists of a zero-voltage detector, a
line-synchronized ramp generator, a zero-current detector, and
a line·derived control circuit (i.e., the zero·voltage switch). The
zero-voltage detector (part of CA3086 No. I) and the ramp
generator (CA3086 No.2) provide a line.synchronized
ramp·voltage output to terminal 13 of the zero-voltage switch.
The ramp voltage, which has a starting voltage of 1.8 volts,
starts to rise after the line voltage passes the zero point. The
ramp generator has an oscillation frequency of twice the
incoming line frequency. The slope of the ramp voltage can be
adjusted by variation of the resistance of the 1-llIegohm
ramp-control potentiometer. The output phase can be
controlled easily to provide 1800 firing of the triac by
programming the voltage at terminal 9 of the zero·voltage
switch. The basic operation of the zero-voltage switch driving a
thyristor with an inductive load. was explained previously in
the discussion on switching of inductive loads.

Isolation of DC Logic Circuitry
As
explained earlier under Special Application
Considerations, isolation of the dc logic circuitry· from the ac
line, the triac, and the load circuit is often desirable even in
many single-phase power-control applications. In control
circuits for polyphase power systems, however, this type of
isolation is essential, because the common point of the dc logic
circuitry cannot be referenced to a common line in all phases.
In the three·phase circuits described in this section,
photo-optic techniques (i.e., photo-coupled isolators) are used
to provide the electrical isolation of the dc logic command
signal from the ac circuits and the load. The photo-coupled
isolators consist of an infrared light-emitting diode aimed at a
silicon photo transistor, coupled in a common package. The
light·emitting diode is the input section, and the photo
transistor is the output section. The two components provide a
voltage isolation typically of 1500 volts. Other isolation
techniques, such as pulse transformers, magnetoresistors, or
reed relays, can also be used with some circuit modifications.
Resistive Loads
Fig. 55 illustrates the basic phase relationships of a
balanced three-phase resistive load, such as may be used in
heater applications, in which the application of load power is

TRIAC POWER CONTROLS FOR
THREE-PHASE SYSTEMS
This section describes recommended configurations for
power-control circuits intended for use with both inductive
and resistive balanced three·phase loads. The specific design
requirements for each type of loading condition are discussed.
power-control
circuits
described,
the
In
the
integrated-circuit zero-voltage switch is used as the trigger
circuit for the power triacs. The following conditions are also
imposed in the design of the triac control circuits:
I. The load should be connected in a three-wire
configuration with the triacs placed external to the load;
eiter delta or wye arrangements may be used. Four-wire
loads in wye configurations can be handled as three
independent singie-pIWe systems. Delta configurations in
which' a triac is connected within each phase rather than
in the incoming lines can also be handled as three
independent single-phase systems.
2. Only one logic command signal is available for the
control circuits. This signal must be electrically isolated
from the three-phase power system.
3. Three separate triac gating signals are required.
4. For operation with resistive loads, the zero-voltage
SWitching technique should be used to minimize any
radio·frequency interference (RFI) that may be
generated .
• The de logic circuitry provides the low-level electrical signal that
dictates the state of the load. For temperature controls, the de logic
circuitry includes a temperature sensor for feedback. The RCA
integrated~cuit

zero-voltage switch, when operated in the de mode
with some additional circuitry. can replace the de logic ciIcuitry for
temperature controls.

GATE DRIVE

REMOVED

RANDOM
START-UP

POINT

V.

SINGLE PHASE
TURN-OFF

la)

Ib)

Fig. 55 - Voltage phase relationship for a three-phase resistive load

when the application of 1000d power is controlled by
zero-voltage switching: (a) voltage watl6forms, (b) load-circuit
orientation of voltages. (The dashed lines indicate the normal
relationship of the phases under steady-statB conditions. The
deviation at stan-up and turn-off should be noted.)

327

ICAN-6182 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

controlled· by zero-voltage switching. The following conditions
are inherent in this type of application:
I. The phases are 120 degrees apart; consequently, all three
phases cannot be switched on simultaneously at zero
voltage.
2. A single phase of a wye configuration type of three-wire
system cannot be turned on.
3. Two phases must be turned on for initial starting of the
system. These two phases form a single-phase circuit
which is out of phase with both of its component phases.
The single-phase circuit leads one phase by 30 degrees
and lags the other phase by 30 degrees.
These conditions indicate that in order to maintain a
system in which no appreciable RFI is generated by the
switching action from initial starting through the steady-state
operating condition, the system must first be turned on, by
zero-voltage switching, as a single·phase circuit and then must
revert to synchronous three-phase operation.

The three photo-coupled inputs to the three zero-voltage
switches change state simultaneously in response to a "logic
command". The zero-voltage switches then provide a positive
pulse, apprOximately 100 microseconds in duration, only at a
zero·voltage crossing relative to their particular phase. A
balanced three-phase sensing circuit is set up with the three
zero-voltage switches each connected to a particular phase on
their common side (terminal 7) and referenced at their high
side (terminal 5), through the current-limiting resistors R4,
R5, and R6, to an established artificial neutral pOint. This
artificial neutral point is electrically eqUivalent to the
inaccessible neutral point of the wye type of three-wire load
and, therefore, is used to establish the desired phase
relationships. The same artificial neutral point is also used to
establish the proper phase relationships for a delta type of
three-wire load. Because only one triac is pulsed on at a time,
the diodes (D I, 02, and 03) are necessary to trigger the
opposite.polarity triac, and, in this way, to assure initial
latching-on of the system. The three resistors (RI, R2, and
R3) are used for current limiting of the gate drive when the
opposite-polarity triac is triggered on by the line voltage.

Fig. 56 shows a simplified circuit configuration of a
three-phase heater control that employs zero-voltage
synchronous switching in the steady-state operating condition,
with random starting. In this system, the logic command to
turn on the system is given when heat is required, and the
command to turn off the system is given when heat is not
required. Time proportioning heat control is also possible
through the use of logic commands.

In critical applications that require suppression of all
generated RFI, the circuit shown in Fig. 57 may be used. In
addition to synchronous steady-state operating conditions, this
circuit also incorporates a zero-voltage starting circuit. The
start·up condition is zero-voltage synchronized to a

3' INPUT

~

I'

\

'-

3 pHASE
RESISTIVE LO~D
(DELTA OR WYE)
a

• FORMERLY RCA 44003
• FORMERLY RCA 40708

Fig. 66 - Simplified diagram of II three-phase heater control that
employs ZBro·~/tBge synchronous switching in the
Bteady-stBte operatinll conditions.

328

92CS-22637

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ICAN-6182

single-phase, 2-wire, line-to-line circuit, comprised of phases A
and B. The logic command engages the single-phase start-up
zero-voltage
switch
and
three-phase
photo-coupled
isolators OCl3, OCl4, OCl5 through the photo-coupled
isolators OCIl and OCI2. The single-phase zero-voltage
switch, which is synchronized to phases A and B, starts the
system at zero voltage. As soon as start-up is accomplished, the
three photo-coupled isolators OCl3, OCI4, and OCI5 take
control, and three-phase synchronization begins. When the
"logic command" is turned off, all control is ended, and the
triacs automatically turn off when the sine-wave current
decreases to zero. Once the first phase turns off, the other two
will turn off simultaneously, 90° later, as a Single-phase
line-to-line circuit, as is apparent from Fig. 55.

Inductive Loads
For inductive loads, zero-voltage turn-on is not generally
required because the inductive current cannot increase
instantaneously; therefore, the amount of RFI generated is
usually negligible. Also, because of the lagging nature of the
inductive current, the triacs cannot be pulse-fired at zero
voltage. There are several ways in which the zero-voltage
switch may be interfaced to a triac for inductive-load
applications. The most direct approach is to use the
zero-voltage switch in the dc mode, i.e., to provide a
continuous dc output instead of pulses at points of
zero-voltage crossing. This mode of operation is accomplished
by connection of terminal 12 to terminal 7, as shown in
Fig. 58. The output of the zero-voltage switch should also be

~------------------------------------_+_+~r£rf--~------------,·c

r--r~~~r---------~--.A

.

012018

TO
3 PHASE
RESISTIVE

LOAD
(DELTA OR WYE)

• FORMERLY RCA 44003
• FORUER1..Y RCA 40708

Fig. 57 - Three-phase

power control

92CL-22U8

that employs zero-volrage

synchronous switching both for steady-state operation and
for starting.

329

ICAN-6182 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

220

eK

v

~

POWER
. TRIAC

100

O.I,..F

92CM-22639

Fig. 58 - Triac three-phsse control circuit for an inductive load# ;.8.#

three-phase motor.

limited to approximately 5 milliamperes in the dc mode by the
750-ohm series resistor. Use of a triac such as the T23010" is
recommended for this application. Terminal 3 is connected to
terminal 2 to limit the steady..tate power dissipation within
the zero-voltage switch. For most three-phase inductive load
applications, the current-handling capability of the 40692 triac
(2.5 amperes) is not sufficient. Therefore, the 40692 is used as
a trigger triac to turn on any other currently available power
triac that may be used. The trigger triac is used only to provide

trigger pulses to the gate of the power triac (one pulse per half
cycle); the power diSsipation in this device, therefore, will be
minimal.
Simplified circuits using pulse transformers and reed relays
will also work quite satisfactorily in this type of application.
The RC networks across the three power triacs are used for
suppression of the commutating dv/dt when the circuit
operates into inductive loads.

" Formerly RCA 40692

The specific integrated-circuits, triacs, SCR's, and rectifiers included in circuit diagrams shown in this Application Note are listed
below. Additional information on these devices can be obtained by requesting the applicable RCA data-bulletin file number.
Type No.
CA3058, CA3059, and CA3079
CA3099E
CA3086
CA3080
CD4007A, CD4013A
2N5444
T2800B (40668)

File No.
490
620
483
475
479
456

Type No.
T2300B (40526)
T2301B (40691), T2301D (40692)
T64170 (40708)
52600D (40655)
01201B (44003)
03202U (45412)

364

Note: Numbers in parenthesis (e.g. 40668) are former RCA type numbers.

330

File No.
470
431
406
496
495
577

OOOBLJIJ

Linear Integrated Circuits

Solid State
Division

Application Note
ICAN-6222
DESIGNING WITH AN IC TRANSISTOR ARRAY
CONTAINING MATCHED
SUPER-BETA TRANSISTORS
by T. J. Robe

Many smail-signal, low-frequency, and video-frequency applications require an amplifying device with a very high input
impedance, low input-bias current, and low-noise characteristics
that can maintain low dc offset voltage and drift. Examples of
such applications include:
Small-signal instrumentation - chart recorders, meters, etc.
Pre-amps for op-amps.
Magnetic tape-head and photo-cartridge amplifiers.
Opto-electric amplifiers.
Medical electronics.
Devices suitable for such applications are also generally
applicable in circuits having long time constants, such as

NOTE: SHADED TRANSISTORS ARE

SUPER-BETA TYPES

timers, integrators, monostable oscillators, comparators, and

low-frequency oscillators. Matched super-beta transistors are
well suited for use in these applications.
Super-beta transistors are similar to conventional bipolar
transistors except that they have betas in the range of 1000 to
5000; the beta range of a conventional bipolar transistor is
from 50 to 400. Since super-beta transistors are commonly
used in high-source-impedance applications that require high
input impedance and low-noise characteristics, it is equally
important that they exhibit super-beta performance at operating
currents of a few microamperes. On the other hand, to achieve
broadband characteristics in video-amplifier applications, superbeta performance must be maintained with collector currents
of I milliampere or more. This Note describes the RCA-CA3095
super-beta transistor array and discusses its operation in some
typical applications.
A TRANSISTOR-ARRAY IC CONTAINING SUPER-BETA
TRANSISTORS

Fig.1 shows the schematic diagram of the RCA-CA3095E, a
monolithic ICI containing an array of n-p-n transistors of
which Q I and Q2 have super-beta characteristics. Q I and Q2
are connected, in conjunction with transistors Q3 and Q4' in a
differential-cascode-amplifier configuration. Since the superbeta transistors in this IC have a collector-emitter breakdown
voltage V(BR)CEO of about 2 volts, it is necessary to limit the
collector-emitter voltage accordingly. limiting is accomplished
7-74

9ZCS·Z0350

Fig. 1 - Schematic diagram of the CA3095E.

by means of the voltage-limiting network composed of 01,02
and Q5; these components are included on the CA3095E chip.
With this arrangement, the voltage applied to the bases of QI
and Q2 can be varied over a wide common-mode voltage range
while the collector-emitter voltages are restrained within a
maximum range of about 1.5 volts. The collectors of transistors Q3 and Q4 have a minimum collector-to-emitter breakdown voltage of 35 volts. the salient characteristics of the
differential-cascode amplifier (QI through Q4) js the "superhigh" ratio between the collector currents (at terminals 10 and
6) and the base currents (into terminals 9 and 7, respectively).
The beta of the circuit is typically in the range of 1000 to
5000 at collector currents ranging from less than I microampere to more than I milliampere. As a consequence, amplifier circuits can be designed to operate with extremely small
input base-bias currents. Implicit in this performance are high
input impedance, low noise, and low de offset-error effects.
Transistors Q5' Q6, and Q7 are conventional n-p-n types
with betas in the range of ISO to 400 at collector currents in
the range of I microampere to 10 milliamperes. These transistors also have a minimum collector-emitter breakdown voltage V(BR)CEO of 35 volts.

331

ICAN-6222

Operating the Super-Beta. Differential-Cascode Amplifier
Application· of the differential-cascode amplifier in the
CA3095E is similar to that of the classical differential-cascode
amplifier; differential input signals are applied at terminals 7
and 9 with balanced collector loads connected from terminals·
6 and 10 to the positive supply voltage. The common emitter
connection, terminal S, may be made directly or through a
"current source" (e.g., a trailsistor or resistor) to the negative
supply voltage. The circuit in Fig. 2 illustrates the use of
"mirrored" transistors (Q7' QS) as a constant-current source
to provide high emitter impedance for the differential-cascode
amplifier. As an alternative, a resistor may be used as a
"current source" (as illustrated by the circuit in Figs. 8,9,
and 11). The IC substrate (terminalS) is usually·connected directly to the negative supply terminal, as shown in Fig. 2, because it must be maintained at the most negative potential of
all elements on the CA3095E chip.
The only additional requirement for CA3095E operation is
for bias cunent into terminal II to forward-bias the network
composed of 01, 02 and Q5, and to supply base-bias cur~
rent for transistors Q3 and Q4. This base'bias current can
be provided by connecting a dropping resistor between terminal 11 and the positive supply voltage; this arrangement is
illustrated by the use of resistor RBIAS in Fig. 2. As an
alternative, this current can be supplied from the positive
supply to terminal 11 thrpugh a p-n-p constant-current-source
transistor to maximize common-mode and power-supply rejection characteristics. In most applications, however, such a
v+

constant-current- source arrangement is not necessary because
transistor Q5 conducts most of the 01, 02 signal current to
the IC substrate connected to terminal 5. As a general rule, the
current supplied to terminal 11 should be approximately 4 to
10 per cent of the current drawn from terminal S. The input
signals to the super-beta transistors (terminals 7 and 9) should
not be permitted to swing more than 6 volts below the voltage
at terminal II to avoid exceeding the VCBO rating of superbeta transistors Q I and QZ. This factor is normally a design
consideration only when one or both of the input-stage transistors is to be biased off.
Low-Frequency Operation
When an amplifier is to operate at very low frequencies, or
as a dc amplifier, the signal source must be directly coupled to
the amplifier input. This coupling requires the use of an
amplifying device with a very low input dc offset error and
low offset-error drift with temperature vadations. A matched
differential-cascode amplifier, like the one used in the
CA3095E, is particularly well suited to this requirement, not
only because of its low input offset voltage (VIO = 1 mY,
typical), but also because of its low input offset current (10 =
4 nA, typical, at IC = 100 IlA). When the input signal is provided from a high-impedance source (Rg), both of these
characteristics assume importance because the total effective
input-offset-voitage error is the sum of their effects:
.
Total Offset Error = VIO + lIOR.
The differential input impedance in megohiiis (Z;.d in Fig. 3)
of an amplifier operating at low frequencies is given by:
Z;.d = 26 mV X the number ofp-n junctions in the input stage
lIB (in nA)
Mn
where lIB is the input-slage base-bias current. Consequently,
the input bias current (JIll> must be quite low if a high input
impedance is to be established. The characteristics of the
super-beta transistors in the CA3095E are weD suited for use

V;

*Zid·:=~5D:Er:.C:I~~~17:) AND (7)
Fig.

3 - Input c;tr:ult for the differential amplifier.

in dc amplifiers requiring high input impedance. For example,
with the super-beta transistors operating at input-stage emitter
currents of 1 microampere and an HFE of 2000, the basebias current is only 0.5 nanoampere. Under these conditions,

Fig. 2 - B;8$ arrangement for operatipn of the supeMHJta differential·

cascode amplifie,.

332

z;'d=26mVX 2 = 104 megohms
O.5nA
Impedance levels of this order can also be realized by using
negative feedback in conneclion with devices having higher

ICAN-6222
input bias currents, as illustrated by the circuit shown in
Fig. 4. In this arrangement, the use of the feedback network
effectively multiplies the differential input impedance. Unfortunately, this arrangement does not avoid the input-offsetvoltage effect resulting from the flow of unequal currents
through the signal-source resistance (Rs) and the equivalent
resistance of the feedback network; i.e., Rj//Rf. Consequently,
the advantage to be gained by using super·beta transistors is
apparent.

NEGATIVE FEEDBACK

~2 :~G~~I~O~TPUT

R,**
Ri

*Zif "Zid 111+ LOOP GAIN)
INPUT DC ERROR-VOLTAGE-V ic

Vic .VIot( IIB,-IIBZI RS

** Rfl/Ri"RS
(DESIRED fOR MINIMUM ERROR VOLTAGE)

Fig. 4 - Differential input with provisions for feedback.

Considerations in Low-Noise Performance

Fig.5 shows the schematic diagram of a noise model
useful in a review of the considerations pertinent to optimizing low·noise performance in amplifier operation.

ENT!
REFERRED
TOHERE~

TOTAL INPUT-REFERRED NOISE VOLTAGE 1../T1z: ENTi
FOR AMPLIFIER DRIVEN FROM SIGNAL-SOURCE HAVING SOURCE'
RESISTANCE RS. Enlitin VlJ'Fj'i") =J4KTRs +IIn R sI2 +(En)2
92CS'Z2492

Fig. 5 - Sources of noise in the transistor-amplifier stage.

This model illustrates that consideration must be given to
three major sources of noise:
Noise contributed by the "thermal-noise" voltage de·
veloped across the signal-source resistance, Rs. The magni~
tude of this voltage in v/Rz is approximately equal to
J4KTRs for a l-cycle bandwidtIi, where k is Boltzmann's
constant (1.38 x 10,23 jouletK), T is the temperature in
degrees Kelvin, and Rs is the source resistance in ohms.
2. The noise voltage, En' resulting from the combined effects
of shot noise due to emitter current flow and thermal
noise due to transistor base resistance. These, effects add
in rms fashion to give a total En equal to (Eshot 2 +
4KTrb'b)~. The shot-noise component, Eshot, is inversely
proportional to the squ'are root of IEQ, and has a value
14.2 x 10- 12
Eshot= ~ (V/Hz.)
" IEQ
In super·beta transistors, the base resistance component of
En tends to dominate, particularly at currents greater than
10 microamperes. In addition, this component of En has
been experimentally found to be inversely related to operatingcurrent. Therefore, the total value of En is inversely reo
lated to operating current IEQ . .for example, the CA3095E
has a total l·kHz En of approximately 15 nV11Hz at a
collector current of 5 microamperes ,and approximately
8 nV/,JH;. at 50 microamperes.
3. The noise current, In, resulting from the combined "shot
noise" generated by the flow of base current and the Ilf
noise generated in the transistor. The magnitude of In is
approximately proportional to JIiB, where lIB is the base
current. The v;uue of In is typically 0.12 pA11H-l at f=
10 Hz when the super-beta differential-cascode amplifier
in the CA3095E is operating at IEQ = 5/-lA. In decreases
to approximately 0.03 pA.[HZ at f = I kHz.
When each input, terminal in a differential amplifier is driven
from a source resistance (Rs), the total noise voltage (referred
to the input, see Fig. 5) per unit bandwidth is given by:
I.

Enti (in V/.[H;.) = hKTRs + 2 (InRs)2 + (En)2 0
When amplifiers are driven from low source impedances, En is
the predominant factor in noise contributions, whereas the
effect of In predominates when input signals are supplied
from high source impedances. Consequently, since the
CA3095E operates"with very high beta at very low operating
currents, it has exceptionally low values of In' and is an excellent choice to amplify signals from high source resistances when
low amplifier noise contribution' is desired. Additionally, the
incidence of "popcorn" (burst) noise 2 is low in the CA3095E,
a characteristic which further enhances its SUitability for use in
amplifying signals supplied from high-impedance sources. Figs. 6
and 7 show typical data on In and En characteristics,
respectively, as a function of frequency, for the super·beta
transistors in the CA3095E.
Because the operating current of the super·beta transistors
in the CA3095E is adjustable over a wide range, the circuit
designer can optimize the operating current for maximum

333

ICAN-6222
CA3095E is an electronic "building block" which permits the
designer to optimize performance of a particular circuit for
gain, noise, power consumption, bandWidth, and/or other
specific considerations. Some typical circuit applications of
the CA3095E are described below.

AMBIENT TEMPERATURE (TA)-ZSOC

· ,
2

1.0

~:!. :r--...

J

.L

......

I

I

-

COLLECTOR CURRENT

l-

i·
·2
0.1

•

......

ill

(ICI~50 ~A

High-Input-Resistance Low-Noise Amplifier

I-.,., I-

0

z

0.01
10

2

. ••

2 • ••1000

100
FREQUENCY (f) -

The CA3095E contains all the transistors necessary for the
construction of a low-noise, feedback amplifier having a high
input resistance (RIN ~ 20 Mn) and a 3-dB bandwidth of
about 50 kHz. In the circuit shown in Fig. g, voltage gain is
provided by a cascade of two stages, the differential-cascode

• 10.000
••

Hz
92CS-20:564

Fig. 6 - Noise current In as a function of frequency f for each super-bera
ca$C~de-amp/ifier transistor pair (0, . Q 3 Bnd 02 - Q4J.

signal-to-noise ratio at a particular frequency and source resistance. This adjustment is accomplished by selecting an
operating point for which En is approximately equal to
.{2' In Rg. For example, the optimum operating collector
currents in the differential-cascode amplifier are about 5 microamperes when the amplifier is to be driven from two 300-kilohm
source resistors. For operation from higher source resistances,
the currents should be proportionately lower, and vice versa.
Operating currents in the range from 0.1 to 1.0 milliampere
are recommended when the amplifier is to be operated as a
low-noise video amplifier. At these current levels, the gainbandwidth product (fT) is increased significantly with respect
to low collector current operation.
ILLUSTRATIVE CIRCUIT APPLICATIONS

Uke other RCA transistor·array IC's, the CA309SE offers
the circuit designer a class of solid-state devices featuring
matched electrical and thermal characteristics, compactness,
ease of physical handling, economy, and versatility of use. The

1.2 M

A'I.~.31.5(30dB)

QI-08 CONTAINED IN
THE CA309SE

• SEE FH;.2

Fig. 8 - High-input-resistance, low-noise amplifier circuit.

stage (01, 03 - Q2, Q4) and the differential stage (07, Og).
Transistor Q6 is an interstage emitter-follower. The -voltage
gain of the amplifier (approximately 30 dB with the circuit
values shown) is essentially established by the ratio of Rg to
the parallel combination of R5 and R6. The Rg, C2 network
couples feedback around the entire amplifier. Capacitor C4
provides stabilizing compensation. The output-voltage swing
(Eo) is typically 3 volts, peak-to.peak. Typical noise·figure
data are shown in Fig. 8. Power consumption of the amplifier
is typically about 750 microamperes at a supply voltage of
12 volts, although the current in transistors 01 and Q2 is less
than 5 microamperes.
Low-Noise Video Amplifier

2~-+---r-rti---r--+-+-~--+---r-~
4

10

••

4

100
FREQUENCY (f)-Hz

••

lOCO

• 10,000
••
92CS-20563

Fig.7 - Noise vo/mge En 8S a function of frequency f for each super-betB
cascodlHlmplifier transistor pai, (0,-03 and 02- Q 41.

334

The circuit shown in Fig. 9 illustrates the use of super-beta
transistors in the input stage of a video amplifier. The circuit is
capable of delivering 4 volts, peak·to-peak, of output signal with
a typical gain of 33 dB across a bandwidth from de to 10 MHz
(3·dB point). In this application, each super-beta transistor is
biased for' operation at about 400 microamperes to achieve
wideband operation. The super-beta transistor characteristics
minimize the contributions to noise generated by noise current
(In) in the input stage. The eqUivalent input.noise.voltage·vs.
frequency characteristics for the entire amplifier circuit are
shown in Fig. I O. Transistors 0 1 through 04 are connected as an
emitter-coupled pair of cascode amplifiers with a single-ended
load resistor, R3, to drive a discrete transistor Q-PNP. This

ICAN-6222
combination provides

sufficien~

current gain to drive

Q().

the

voltage-gain-stage transistor, with load resistor RS' Resistor
R7 provides a path for de and ac feedback around this stage.

Transistor Q8 is an emitter·follower output stage. The typical
current drain of the amplifier is approximately 8 milliamperes
at a total supply voltage of 10 volts.
TRIGGER

L....rIVMIN

1-0

0,1 fl-F

V+·5V

EO~T-~+5V

QI-07 ARE CONTAINED
IN3095E

~.---'--.L..-_+1_8V

;:~
.• v

. 511-----:::::=----------1

----

NOT~;(RC)I"v~~vC

Ve

-3V
510

__!

• (RCl1n 5 "0.47 Re

~22

ft..

SEC

VR

J
_

Fig. 11 - Long-delay.monostabJe-multivibrator circuit.
3.9K
R5

AV· 33dB
BW3dS-IOMHz

is one step of Vbe (potential e7 "" 0.6 V) above the base of
transistor QI' a condition established by the diode-connected
transistor Q6 in shunt with the base of Q2' The timing cycle is
initiated by the application of a negative-going trigger pulse at
terminal 13, which is coupled to the base of Q2 through
diode·connected transistor Q7' Q2 is cut off and the output
voltage rises to essentially V+. Since QI and Q2 are emittercoupled, QI is turned on by the trigger pulse, and the potential
at terminal 10 drops rapidly; this drop pulls the left-side
electrode of capacitor C toward ground. The right-side electrode
of capacitor C is connected to the positive 5-volt supply
terminal through resistor R; this connection permits the
capacitor to be charged in the exponential characteristic of an
RC network and, primarily, determines the delay time.
Eventually, voltage e7 rises sufficiently to again switch Q2 on
(and QI off) so that the output voltage drops to its quiescent
level (approximately +1.8 V) to signify the end of the timing
period. The trigger-voltage pulse shOUld be at least -I volt in
amplitude to assure positive switching.

·SEE FIG.2
QI-Q8ARE CONTAINED

IN CA309!5E

Fig. 9 - Video amplifier.

~

80

1
~

.)\

~

1\

~

1\

g

~

...
z
...z

40

\

~

"'-

\

~
~

20

RS -20kfi

~

!l
s
iil

-

Rj.l,Jon
a
10

2

4

"

10 2

2

4

"

FREQUENCY (fl-Hz

4

II

Low-Input-Bias Current Comparator
4

8

92C$-20475

Fig. 10 - Equivalent input noise voltage vs frequency for the circuit of
Fig. 9.

Long-Delay Monostable Multivibrator

Super-beta transistors are useful in the design of longdelay, monostable multivibrator circuits, as illustrated in the
circuit of Fig. II. Basically, the circuit is a differential-cascode
amplifier biased so that, in the quiescent state, the current
path through transistors QI and Q3 is cut off, and the path
through transistors Q2 and Q4 is conductive. This arrangement
is accomplished by biasing the base of transistor Q2 so that it

The circuit shown in Fig. 12 employs the super-beta and
conventional transistors in the CA3095E in a comparator
circuit that requires an input signal of only 1.5 nanoamperes
at threshold to produce toggling. The output of the circuit
can interface directly with COS/MaS logic circuits. Transistor
pairs QI - Q3 and Q2 - Q4 are connected in the differentialcascode arrangement described above. Transistor Q6 is a
programmable constant-current source (i.e., capable of being
keyed, gated, clocked, etc.) for the differential-cascode pair.
Transistors Q7 and Q8 are a differential pair used to provide
sufficient gain for the control of the external discrete transistor Q-PNP. The reference voltage for the comparator is
applied at terminal 7; voltages in the range from 1.5 to 6.0
volts are suitable for satisfactory circuit operation.

335

ICAN·6222
Analog Timer for Long Delays

The very low input-bias-current characteristic of the super·
beta transistors in the CA3095E is very desirable in the design
of an analog timer for long time delays; the circuit shown in
Fig. 13 is illustrative, and functions in a manner quite similar
to that of the circuit of Fig. 12. Time delay can be varied in
accordance with the expression shown in Fig. 13.
The timing cycle is initiated by momentarily closing the
push-button switch to discharge timing capacitor C. At this,

instant, transistors QI and Q3 are non-conductive and Q2 and
Q4 are conductive; this arrangement prevents conduction in
transistors QS and Q·PNP. Consequently, the output is
essentially zero volts. Timing capacitor C is charged exponentially through resistor R until the voltage across the
capacitor is sufficiently large to toggle transistor QI and' Q3
into conduction (and Q2 and Q4 into non-conduction). Tran-

Y+·'OV
0,047
,F

:J;
200 K
OUTPUT

a TO

9.7 V

(DRIVES
COS/MOS
LOGIC)

NOTES:

IrBIlI I.SnA ATTHRESHOLO
0,-08 ARE CONTAINED IN CA3095E

TOTAL QUIESCENT CURRENT

l1li

100,..A
92CS-22486

Fig. '2 - Low-input·bias-current comparator circuit.

v+

,ov

ZOOK

"F1

0.47

39.
39DK

~OM

R

MOMENTARY
PUSH- BUTTON

SWITCH

-t

IO,..F

9
9?CM'2?4')8

**C-LOW LEAKAGE TYPE

*SEE FIG 2
QI-OO ARE CONTAINED IN CA3095E

DELAY

l1li

RC

Rn ~

v+-v7

Fig. 13 - Analog timer for long dela",.

336

SECONDS

ICAN-6222
sistors Q7 alld Q8 are also switched_ so as to drive Q-PNP into
conduction aDd produce a "high'- output signal (approximately

drop the dc common-mode voltage at the input of the CA741
to within its linear operating range.

9.7 volts). \\:lth' the values shuwn, the time delay can be varied
over the -range from about 90 to 725 seconds, depending on
the setting of the 100-kilohm potentiometer. The leakagecurrent loading on timing capacitor C due to transistor Q) is
quite smali, and is only of second-order importance in determining timing accuracy.
Super·Beta Transistors in Preamplifier Applications

The wide operating-current range and circuit-connection
flexibility available in the super-beta transistors contained in
the CA3095E offer numerous advantages for applications in
preamplifiers_ For example, these transistors can be simply
connected as a preamplifier for many of the common,
economy-type op-amps (e_g_, CA741, CA748)3 The combination of the CA3095E and one of these op-amps provides an
op-amp with the superior input characteristics offered by some
of the high-priced op-amps that use super-beta transistors in
their input stages_ The CA3095E in conjunction with "commodity-class" op-amps can provide an over-all circuit exhibiting orders-of-magnitude improvement over the op-amp
itself in terms of input impedance, noise, and the effects of
error currents. Several circuit combinations of this type are

described below_
Mention has already been made of the low-noise performance which can be achieved with the super-beta transistors in the CA3095E_ This attribute is a requisite for preamplifiers operating with low-level signal outputs from sources
such as tape heads and magnetic phonograph cartridges_ The
circuits described below illustrate the simplicity with which
super-beta transistor circuits using the CA3095E can be
equalized to meet the requirements for NAB playback and
RIAA phonograph-record reproduction_
Unity-Gain Preamplifier, The circuit in Fig_ 14 illustrates a
unity-gain preamplifier using the transistors in the CA3095E to
drive a CA741 op-amp_ This circuit boosts the input impedance, Zid, of the op-amp to the order of 20 megohms,
typicaL Transistors QI - Q3 and Q2 - Q4 operate as a
differential-cascode amplifier with transistor Q8 as their
constant-current source_ Transistors Q6 and Q7 are diodeconnected to establish de levels which are appropriate for
direct connection to the CA741 input terminals_ No additional
external compensation is required with this circuit because
the unity voltage gain provided by the preamplifier precedes
the internally compensated CA 741 op-amp_ The resultant
offset voltage of the combination circuit is the algebraic sum
of the offsets due to QI' Q7 vs Q2' Q6, and the offset due to
the CA741. The resultant offset can be nulled at the normal
nulling terminals on the CA741. This circuit is ideal for
amplification of signals emanating from sources with very
high impedances.
High-Gain Preamplifier The circuit in Fig_ 15 shows a highgain preamplifier using the transistors in the CA3095E to
drive a CA748 op-amp. Transistors QI - Q3, and Q2 - Q4 operate as a differential-cascode amplifier with transistor Q8 as their
constant-current source. Transistor Q7 is diode-connected to

92CS· 22484

Fig. 14 - Op-amp with unity gain preamplifier.

.. SEE FIG.2

Fig. 15 - Op-amp with high-gain preamplifier.

337

ICAN-6222
This circuit boosts the input impedance, Zid, of the op-amp
to the order of 20 megohms, typical. It also can capitalize on
the low-noise operational capability of the CA309SE, and
reduces the noise (and offset-voltage) contributions of the
CA748 by an increment equal to the gain of the preamplifier,
typically about 28 dB with the circuit constants shown_In this
case, external compensation of the CA748 may be necessary
when the over-all op-amp is connected with feedback_
The approximate value of the compensation capacitor required can be computed by use of the following relationship:

High-Input-Impedance DC-Voltmeter Circuit
The combination of a preamplifier circuit using the
CA309SE in conjunction with a CA748 op-amp as described
above is adaptable to dc-voltmeter circuits requiring high input
impedance, as illustrated by the circuit of Fig_ 17_ An ap-

_
30 X the voltage gain of the preamp
Cc (10 pF) - closed-loop voltage gain of the composite op-amp
The circuits in Fig_ 16 illustrate applications utilizing the
superior input characteristics of super-beta op-amps_ A circuit
such as the one shown in Fig_ 16(a) is useful in applications
where input impedances in the order of ISO megohms are required at frequencies up to S kHz_ Since input bias currents
are required to flow through lQ-megohm resistors in this
circuit, it is mandatory that the input stage exhibit both low
bias current and very low input offset current. (The capacitive
reactance of the coupling capacitor C must be much lower than
S megohms to achieve the high-in put-impedance characteristic
described above_) The low-drift, long-time-constant integrator
circuit shown in Fig_ 16(b) is another excellent application for
the CA309SE super-beta. transistor array_Because exceedingly
low input bias currents permit the use of a high-value integrating resistor, R, without introducing substantial error,longtime-constant integration can be accomplished. The low inputoffset-voltage drift characteristic of the super-beta transistors
also contributes to low-error performance_ Further reductions
in error effects, particularly with temperature variation, can be
achieved by using a temperature compensated bias-current
source (e.g_, RI-R3, 01)_ In the circuit of Fig_IS, such an
arrangement could be implemented by using Q6 in a diode
connected fashion to serve as 01_ With such an arrangement,
temperature-compensated bias current is applied to the inverting input terminal.
RI

D'

v'"

20M

'8M

,%

1.8M

,%

200R

,% ......2.4M
"h--r.....-{iiil-r

921:5-22501

·SEE FIG.2

Fig. 17 - Typical high-input-impedance dc-voltmstercircuit.

propriate resistor-divider network is provided to develop a dc
input signal at terminal 9 of the CA309SE with transistors
QI - Q3 and Q2 - Q4 connected in the differential-cascode
arrangement_ Biasing and dc feedback are applied at terminal 7
of the CA309SE through a 10-megohm resistor. The CA748
op-amp drives a 200-microampere meter calibrated in terms of
the voltages to be measured_ A full-scale reading occurs when
the voltage applied to pin 9 is SOO millivolts dc. The entire circuit is nulled with the SOO-kilohm zero-adjustment potentiometer. The total power-supply requirement is only 6 volts with
a supply current of only 300 microamperes; this requirement
can be met with batteries_ The input impedance of this simple
circuit is approximately 40 megohms on all scales_
Preamplifier for Tape-Head Signals

I"
LOW~ DRlfT,LONG-TIME-CONSTANT

INTEGRATOR

I.'

PIEZOELECTRIC TRANSDUCER
AMPLIFIER

Fig. 16 -

338

Typical super-beta op*Bmp applications:
(a) piezoelectric transducer amplifier
fb} fow-drift, long-time-constant integrator.

The exceptiona1low-noise characteristics of the CA309SE
make it suitable for preamplifier service in professional-grade
tape-playback systems_ A typical circuit with equalization for
NAB standards (7_S in/s) is shown in Fig_ 18. Transistors QI
and Ql are cascode-connected as the input stage, and transistor
Q6 is connected as a common-emitter post-amplifier_ Transistors Q2 and Q4 are non-conductive because the emitterbase junction in Q2 and the base-conector junction in 04 are
shunted by external wiring_ Equalization for the NAB tapeplayback, frequency-response characteristics is proVided by the
R I, C I, C2 network connected in the ac feedback path; DC
feedback stabilization is provided by the path through resistor

- -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ICAN-6222
R2_ The amplifier has an over-all gain of about 37 db at I kHz,
and can deliver output voltages in the order of 25 volts, peakto-peak. The circuit configuration of Fig. I 8 is preferred to the
differential-amplifier configuration because it limits the inputnoise contribution to that of a single transistor (e.g., QI)'

playback standards is shown in Fig. 19. Transistors QI and Q3
are cascode-connected as the input stage, and transistor Q6 is
connected as a common-emitter post-amplifier. Transistor Q2
and Q4 are non·conductive because the emitter-base junction
in Q2 and the base-collector junction in Q4 are shunted by
external wiring. Equalization for the RIAA phonographfrequency-response characteristics is provided by the R I, C I
network connected in the ac feedback path. DC feedback
stabilization is provided by the path through resistor R2' The
amplifier has an over·all gain of about 40 dB at I Hz, and can
deliver output voltages in the order of 25 volts, peak-to·peak.
The dynamic range of these circuits is typically about 95 dB
with the gains indicated.

QI-Q6ARE CONTAINED
IN CA3095E

4.3K

Fig. 18 - Tape play-back preamplifier equalized for

NAB standards (7.5 in/s).

Preamplifier for Signals from Magnetic·Phonograph Cartridges
The exceptional low-noise characteristics of the CA3095E
are also of great use in preamplifier service in equipment used
to reproduce signals from magnetic phonograph cartridges. A
typical circuit for this application with equalization for RIAA

CI-OS ARE CONTAINED IN
THE CA~095E

* SEE FIG 2
Fig. 19 - Preamplifier equalized for RIAA standards applicable
to magnetic phonograph carr;dges.

ACKNOWLEDGMENT

The circuits of Figs. 18 and 19 were designed by LA Kaplan.
REFERENCES

I. "Super-Beta Transistor Array," CA3095E, RCA Data File
No. 591.
2. "Measurement of. Burst ("Popcorn") Noise in Linear Integrated Circuits," T: J. Robe, RCA Application Note
ICAN-6732.
3. "Operational Amplifiers," RCA Data File No. 53 I.

339

DClC05LJD

Application Note

Solid State
Division

ICAN-6247
Application of the CA3126Q
Chroma-Processing IC Using
Sample-and-Hold Circuit Techniques

This Note* describes the CA3126Q monolithic integrated
circuit intended for use in processing the chrominance signal
in a color television receiver. In performing the functions of
color subcarrier regeneration and chroma control, emphasis
has been placed on utilizing all the information available in the

Two controls serve to adjust the chroma level: One control
is automatic and functions as a supplementary ACC loop to
prevent oversaturation under condition of improper transmitted burst-to-chrominance ratio, and under noisy-signal
conditions. The second chroma level control is for manual

signal so as to approach ultimate system performance capa-

adjustment of the saturation by the viewer. This control has a

bility, while at the same time substantially reducing the
number of external components and adjustments.
As contrasted with prior state·of·the·art IC designs, sample·
and·hold techniques are used in the phase detectors for the
AFPC and the ACC·killer loops of the CA3 I 26Q. The improved
signal·to-dc unbalance attained thereby makes it possible to
eliminate the adjustments conventionally used in those circuits.
The only set-up adjustment is a trimmer capacitor to tune the
crystal filter.

linear characteristic over the range of the chroma gain control.
The CA3126Q integrated circuit which performs these
functions is housed in a 16-terminal package. The external
components, shown in Fig. I, are relatively few and consist of
integration capacitors for the servo loops and the filter
network in the VCO. Table I summarizes the performance of
the circuit.

Table I - Performance Data Typical Values
Function

Nom. Supply

Supply Var.

Temp. Var.

Vee = 11.2 V

Vee ±:IV

II T = 500 e

Oscillator Characteristic

at

C, W. Carrier Ampl.

1 Vpp

±5%

+ 10%

Frequency

Nom. Sub

+70 Hz

-70 Hz

+2°

_2°

0.5 Vpp

±2.5%

-5%

±10%

-5%

ACC-3 dB Point

2.7 Vpp
20% EIN

Killer Threshold

5% EIN

Carrier

AFPC Characteristic

CHROMA
INPUT

CHROMA
OUTPUT

DC Loop Gain
Pull~in Range

40 Hz/deg.
±500 Hz

Phase Error
Noise Bandwidth fNN

100Hz

ACe and Killer Characteristic
100% Input Level (Red Field) 0.25 Vpp
::',W. CARRIER
OUTPUT

Nominal Output with
Overload Detector
Nominal Output without
Overload Detector

F;g. 1- Components external to the CA3126Q.

• This Note, revised by Wayne Austin (RCA Solid State
Division) was originally prepared by L A_ Harwood (Consumer Electronics Division) for publication in the IEEE
TRANSACTIONS ON BROADCAST AND TV RECEIVERS,
May 1973, Vol. BTR-19, No.2.

340

Diff. Phase Error Over
Entire ACe Range

,0

Manual Control Characteristic
Chroma Output Linearly

Proportional to

Control Bias
Diff. Phase Shift with
Bias Var.

2°

11-73

-----------------------------ICAN-6247
MAJOR FUNCTIONS
The signal flow and organization of the CA3126Q are
shown in block form in Fig_ 2_ The composite chroma signal is
applied to the first chroma amplifier. The output from this
stage proceeds along three paths. The first path leads to the
doubly-balanced wide-band AFPC detector. Here the burst
signal is compared with the reference carrier to produce the
required error signal for synchronization. Two sample-and-hold
circuits serve to achieve high detection efficiency and bias
stability. One sample-and-hold circuit samples the detected
signal during the horizontal keying interval and stores the peak
error signal in a flIter capacitor. A second similar circuit provides an accurate reference potential as described later. The
bias stability of this system is sufficient to eliminate the need
for the adjustments required in conventional circuit design.
The detected and flItered burst signal controls the frequency and phase of a voltage-controlled oscillator (yCO)
by operating on an electronic phase-shifter. The VCO consists
of an amplifier-limiter followed by the electronic phase-shifter.
A crystal flIter located between the output of the phaseshifter and the input of the amplifier-limiter closes the loop
of the VCO. The flItered oscillator signal is amplified to produce the required reference carriers for the AFPC and ACC
synchronous detectors. The required quadrature relationship is obtained by + ,,/4 and -,,/4 radian integrated phase-shift
networks.
The ACC-killer detector is similar in structure to the AFPC
detector, and is also driven from the first chroma amplifier
stage_ It detects synchronously the in-phase component of

the burst signal and produces a pulse signal proportional in
amplitude to the level of the burst signal. The resulting control signal passes through a sampling circuit, as described
above, and is applied to the killer and ACC amplifiers. The
action of both amplifiers is delayed so that the unkill action
takes place prior to ACC and the latter is fully activated upon
reaching the predetermined burst level. The ACC amplifier
controls the gain of the first chroma amplifier so as to maintain the burst signal constant while the killer amplifier enables
the output stage in the presence of the burst signal.
The ·signal level to the second chroma amplifier is reduced
to one fourth of the available signal level to allow for the extremes of the chroma signal excursions. A horizontal rate
keyer operating on this stage removes the burst signal so that
the output stage is activated only during the horizontal
scanning interval. A saturation control, available for front

panel control, allows a continuous gain adjustment of this
amplifier. A desirable feature of this control is the linear
correspondence between the control bias and the chroma
output signal. The chroma maximum level corresponds to the
maximum bias potential without a dead spot at the extreme
of the control range. A threshold type overload detector
monitors the output signal and maintains the output from the
second chroma amplifier below an arbitrarily set level. This
prevents the overload of the picture tube usually experienced
on noisy or excessively large chroma signals. The required
keying signals for the various functions are generated by two
cascaded keyer stages where either polarity pulses are generated.

J

CARRIER

OUTPUT
SUPPLY

VOLTAGE

8
O.ol,.F

V+24 V

10<0

J1.~AA.r.JLov
1I~ ~
SUBSTRATE

ilI
L___~3~~
"="

\!I---- 2vKA~

I

~

5,is WIDTH

HORIZONTAL
KEY INPUT

I
I
LI'"

_______________

DELAY
:
~'~ _ _ _ _ _ _

I

!rc'c

O.oI,.F.x.
.;QOI,.F
"="F1LTER-

J

*

OPTIONAL DESIGN
FEATURES
92C"-22022RI

Fig. 2- Signal flow and organization of the CA3126Q.

341

ICAN-6247
Sample-and-Hold Circuits
As previously stated, the sample-and-hold circuits shown in
Fig. 3 allow efficient utilization of the detected error signal
and provide a reliable reference potential. During the sampling
interval, the detected pulse signal available at the detector load
resistor R 13 is translated to the AFPC filter capacitor of terminal 2 via transistors QS3 and QS4. QS3 serves to isolate the
detector from the switching pulses generated in the sampling
circuits_ The sample-and-hold action is accomplished by controlling the conduction current in transistor QS4 thus alternating the charge path during those intervals. During the
sampling interval, transistor QS4 conducts and its emitter
exhibits a relatively low impedance in comparison with the
value of the integrated charging resistor R20. The detected or
sampled signal is stored in the AFPC filter capacitor which,
with R20, determines the time constant during this time
interval. During the hold period, transistor QS4 is off and the
filter time constant is several orders of magnitude larger than
previously_The discharge of the filter capacitor is reduced
to very sman base bias currents only and little of the stored
information is lost.
The "on" and "ofr' condition of the transistor QS4 is
determined by the state of the transistor-pair QII and Q\2.
During the "on" (sampling) interval, a signal from the horizontal rate keyer disables transistor QII and the collector current of the transistor Q\2 maintains the transistor QS4 in the
"on" condition. During the "orr' (hold) period, transistors
QII and Q12 change their states and the transistor QS4 is "ofr'.

REGENERATION OF THE SUBCARRIER

The regeneration of the sub carrier is performe!l in the circuit shown in Fig_ 3. This section consists of a synchronous
phase detector, the sample-and-hold circuits, and a voltagecontrolled oscmator. Several keying circuits serve to maintain
the operation in proper time sequence.
The Phase Detector
The phase detector is formed by transistors QSI' QS2 and
QS to Q 10. The composite chroma signal amplified by the
first chroma amplifier is applied to transistors Q7 and QS and
the reference carrier is applied to transistors Q9 and QS2. The
product of the two signals is developed across the load
resistor R 13. Transistors QS and Q6, triggered by a horizontal
rate keyer circuit, operate on the phase detector so as to anow
detection of the burst signal only. The current compensation
of transistors Q7 and QS by the gating transistors QS and Q6
and the absence of filtering at the output of the detector
results in transient-free switching of the phase detector. In the
absence of chrominance, the potential across the load resistor
R 13 remains constant regardless of the keying. In the presence
of the chrominance signal, the phase detector produces two
time-spaced outputs: one during the horizontal scanning
interval corresponding to the quiescent potential, the second
during the horizontal keying interval representing the detected
burst. Thus, the detected burst can be measured relative to the
quiescent potential rather than to an arbitrary reference. This
results in "'excenent stability for temperature and supply
variations.

AFPC

"F

FILTER

BYPASS

Rig
12K

3.58 MHz
CRYSTAL FILTER

POWER
SUPPLY

I
I
I

RIB
IK

I
I

I

"ALANCED

~7---~-t~~~~--+---~+----}____J-____~~~~r~F~~E~"-J~-J______~~~-l__~______
__1-- .JI
92CM-UOSO

Fig. 3- Subcarrier regeneration circuit.

342

ICAN-6247
The bias sample-and-hold circuit, similar in structure to the
above-described circuit, consists of the sampling switch QS9
and the transistor·pair Q 17 and Q 18. This circuit, also activated by a signal from a horizontal rate keyer, samples the
quiescent potential of the phase detector. The two signals,
the error and the bias, processed by the sampling circuits, are
stored in filter capacitors, and are applied to opposite terminals
of a differential phase control. The phase control circuit synchronizes the reference carrier produced by the VCO.
Depimding"on the free·running frequency of the VCO, the
detected signal is in the form of positive or negative going
pulse trains which are then stored in a filter capacitor. The
sampling switch has equal drive capabilities for both polari. ties of the signal; a requirement of particular importance in the
presence of noise signals. Non-linear operation of the detector
and sampling circuit would produce a rectified dc component
causing an erroneous detuning of the VCO.
ThaVCO Loop
The amplification and amplitude limiting of the oscillator
signal takes place in the amplifier-limiter formed by the transistor-pair Q60 and Q20. The output from Q20 is fed to the dc

controlled phase-shifter and returns to the amplifier through a
crystal filter. The amplifier operates in a non-inverting mode,
hence, the total phase shift through the phase-shifter plus crystal filter must be a multiple of 2 rr radians. The crystal filter
is tuned to the subcarrier frequency and the filter band-width
is determined by a resistor in series with the crystal. The DC
controlled phase-shifter has a phase range of apprOximately
rr
± "4 radians, and a phase change activated by a control signal
results in a corresponding oscillator frequency change.
In the phase-shifter, the oscillator signal available at the col·
lector of Q20 is applied to the base of Q14 from which it proceeds along two paths. An integrated capacitor C2 couples
this signal from the emitter of QI4 to the collector load of
QlS and, at this point, the signal is phase·shifted by approximately rr/4 radians. In the second path, the signal arriving at
the collector of QIS passes through a current splitter formed
by the transistor·pair QS6, QIS. This signal is reduced to a level
determined by the control voltage at the bases of transistors
QS6 and QIS. At one extreme, transistor QIS is OFF and the
signal at the collector of Q IS arrives through the capacitor C2
only. Conversely, with transistor QIS ON, and QS6 OFF, the
signal arriving through the transistor QIS is phase-oriented so
that the resultant signal has a phase of +3/4 rr radians. The
phase-control is linear throughout most of the control range.
A buffer amplifier is used to supply the CW carrier required for the demodulators, and the carrier is available at
terminal 8. Internally, the buffer amplifier supplies the two
synchronous detectors. Two R·C phase·shifters fed from the

buffer amplifier provide the required phase orientation. A lowpass R14-C3 filter shifts the carrier to the AFPC detector by
-rr/4 while a high-pass filter provides a +rr/4 oriented carrier
for the ACC·killer detector.
AMPLITUDE CONTROL OF THE CHROMINANCE SIGNAL
Two cascaded amplifier stages serve to process the chroma
signal and several signals are developed to control the gain of
each stage.
First Chroma Amplifier and ACC Servo Loop
The first chroma amplifier, shown in Fig. 4, is controlled by
the burst responsive ACC-killer detector only. The amplifier
formed by the transistor-pair Q I, Q2 is driven single-ended by
the applied composite chroma signal. The amplified output
from this stage drives differentially the synchronous ACCkiller detector. The gain of the first amplifier is a function of
the dc emitter current supplied by the constant current source
Q3. This current source is biased to provide a nominal current
and, hence, a nominal gain in the first amplifier stage. The bias
of the current source is reduced in response to a detected burst
signal and the gain of the first stage diminishes correspondingly.

The ACC·killer detector is similar in structure to the
AFPC detector. However, the CW carrier applied to the detector is in phase with the burst signal. The detected burst
signal is processed by a sampling circuit in the same manner as
previously described in connection with the AFPC circuit. The
signal sampling consists of the transistor follower Q73 and the
keyed transistor-pair Q40, Q41. Resistor R63 serves to produce
an intentional dc offset across the inputs of the differential
pair Q43, Q76. The detected ACC signal is unipolar with
respect to the reference potential; thus, the dc offset extends
the linear operating range of the amplifier Q43, Q76. The bias
sampling circuit consisting of transistors Q79, Q44, Q4S applies
the quiescent bias to the base of transistor Q76. In the absence
of a burst signal, the dc offset maintains transistor Q43 in the
OFF condition and the following p·n·p transistor, Q29, is also
disabled. Thus, the ACC amplifier Q28 is non-conducting and
the current source Q3 provides the maximum current to the
input stage.
The OFF state of transistor Q29 renders the killer amplifier
(transistor Q27) inoperative, a condition required to disable
the second chroma stage.
Upon amplification of the burst signal in the first chroma
amplifier, the detected burst signal increases proportionately
to the amplitude of the input signal and combines differen·
tially with the previously described bias signal in the collector
load of tran.sistor Q43. Prior to it, the detected and bias signals
are smoothed by the ACC filter capacitors. The linear operation
of the chroma amplifier, the detector, and the amplifier which
follows the sampling circuits is maintained to a signal level
sufficient to enable the transistor Q28. This potential,
approximately 0.7 V, establishes the delay of the ACC charae·

343

ICAN-6247

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4- The fint chroma amplifier and the ACe seIVO loop.

teristic as shown in Fig. 5. The chroma (burst) signal at the
output of the first stage remains essentially constant with
further increase of the input signal. The increasing de poten·
tial at the collector of Q29 also activates the killer·amplifier
Q27. In order to maintain a predictable killer threshold, this
action is referenced to the delay point of the ACC. As
previously stated, the ACC begins to function at a signal level
at which the de potential across resistor ~7 reaches 0.7 V.
The killer threshold is lower than that of the ACC action and
is determined by the voltage drop across resistors ~8 and R47.
Thus, the two threshold "signals are predictably established by
the ratio ~7/(R47 + ~8).

I

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KILLER-/--l
THRESHOLD ~(.o------<.~I-ACC
THRESHOLD

I

Fig. 5- Normal/zed ACC characteristic.

344

IOOOfo" INPUT
92CS-21156

ICAN-6247
The Second Chroma Amplifier
The operation of the second chroma amplifier is controlled
simultaneously by several signals. As described previously.
they are: a eustomer-operated chroma gain (saturation) control,
the killer detector signal, the overload detector, and the keyer.
The amplifier circuit shown in Fig. 6 is formed by the
transistor'pair Q65, Q24 and is driven differentially by the
first chroma amplifier. The signal level to this stage is reduced
by means of a resistive voltage divider. The amplifier Q65,Q24
is interrupted during the horizontal keying interval by the
transistor'pair Q66, Q23 to remove the burst information from
the composite signal. The gating transistors Q66 and Q23 are
connected so that their emitters and collectQrs are in parallel
with the respective emitters and collectors of transistors Q65
and Q24' The resulting collector current compensation main·
tains the quiescent output potential regardless of the keying
operation.

The gain of the second chroma amplifier is adjusted by
varying the current in the transistor Q25' A resistive divider
R41,R42 fed from a follower stage Q67 provides the bias
potential to the base of the transistor Q25 and the voltage drop
across resistur R40 determines the current flowing from the
collectur of Q25 to the emitters of 065 and Q24' The diode
D3 compensates the base to emitter potential of the transistor

Q25'
Since the bias resistors R40, R41, and R47, and also the
amplifier load resistor R43, are located on the same Ie chip,
the resistance ratio of these components is accuralely controlled. Thus, the gain of the second chroma amplifier
determined by these components is very predictable, and is a
function of the bias potential applied to the base of transistor
Q67 only.

~IC~6Q-~-~------1
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Fig, 6- Chroma output stage.

345

ICAN·6247 - - - - - - - - - - - - - - - - - - - - - - - - - - _
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HORIZONTAL
KEYING INPUT

Fig. 7-Comp/ete circuit diagram showing details of the keying circuit
and internal bias circuits.

347

ICAN-6247 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
The interfacing of IC's with external control circuits usually
presents problems due to the large tolerances associated with
both components. The circuit used here overcomes these
difficulties. The transistor follower Q67 exhibits negligible
loading on the bias set by the manual chroma control. Thus,
the gain of the second chroma amplifier is uniquely determined by the rotation of the gain control potentiometer and is
relatively independent of its resistance value.
The killer operation is also performed on the second chroma
amplifier. The amplified output from the ACC-killer detector
is applied to the killer switch Q20. In the presence of a burst
signal, transistor Q20 is off and the chroma amplifier remains
undisturbed. In the absence of a burst signal, the collector current in Q20 reduces the potential on the base of the transistor
Q67 so as to cut off the second chroma amplifier.
The Overload Detector

The ACC and the manually operated saturation control
provide the essential means to maintain the proper chrominance level to the picture tube. Under certain conditions,
however, the presence of the ACC is detrimental. As previously stated, the ACC servo loop maintains a constant Olltput level of the burst signal regardless of the chroma information. Transmitter variations in burst-to-chroma ratios are improperly corrected by the ACC action and, on signals with low
burst-to-chroma ratios, the excessively amplified chroma can
exceed the dynamic range of the picture tube.
Similar overload problems are experienced when receiving
weak signals. The Synchronous ACC detector produces a control signal proportional to the average value of the burst interval signal, and noise does not contribute to the output. AI-

348

though this type of noise-immune detection is necessary for
reliable operation of the killer circuits, it is less desirable for
the ACC action because the noise-peaks plus signal tend to produce undesirable over-saturation effects.
. The overload detector operating on the second chroma
stage eliminates bpth these overload problems. The chroma
signal from the output terminal of the second chroma amplifier is coupled, by means the coupling capacitor Cfb to over·
load detector Q22. Transistor Q22 is biased by means of an
internal bias supply to 0.5 V, and remains off until its base
potential is raised to approximately 0.7 V. Thus, detection
takes place whenever the chroma signal plus de bias is equal to
or exceeds 0.7 V. The detected and filtered signal lowers the
bias potential on the base of transistor Q67 and reduces the
gain of the output stage.

or

KEYING CIRCUITS

Details of the keying circuit and of the internal bias circuits are shown in the complete diagram of the CA3) 26Q in
Fig. 7. A positive horizontal rate keying pulse applied to
terminal 9 activates the keying circuit. This circuit maintains
the AFPC and ACC detectors, with the corresponding sampleand-hold circuit, in the ON position during the keying interval,
and disables the chroma output stage at the same time.
CONCLUSION

The new chroma processing circuit improves the performance of a color television receiver. The use of synchronous detection and sampling results in excellent Signal
stability and fewer external components and adjustments. An
overload detector prevents over-saturation of the picture
tube, and the improved manual control simplifies the adjustment of the chroma level.

OO(]5LJ[]

Linear Integrated Circuits

Solid State

Application Note
ICAN-6257

Division

Application of the CA3089E
FM-IF Subsystem
by L. S. Baar
The RCA-CA3089E, shown in Fig. I, is an FM·IF
virtually unchanged. The typical curves in Figs. 3 through 7
illustrate these characteristics. A reference voltage brought
subsystem intended for use in FM receiver applications. In
addition to the amplifier·limiter and quadrature detector
out to pin 10 may be used in conjunction with the AFC, if
sections, the CA3089E provides such auxiliary functions as
desired.
mute, AFC output, tuning·meter output, and delayed
rf·AGC.! This Note briefly describes each circuit section
Stability Considerations
Because the CA3089E is a very high gain device, the
and discusses practical aspects of designing with this device.
external circuit must be laid out carefully to eliminate or
Circuit Description
reduce any feedback path. 2 Fig. 8 shows a 1O.7-MHz
The three.stage direct·coupled amplifier·limiter uses a
printed-circuit-board layout of the circuit in Fig. 9(a). The
cascode input stage to reduce input noise and provide better
ground-plane layout was devised to prevent large rf currents
stability. The peak·to·peak swing of approximately 300
millivolts is developed across the 390-0hm resistor, R3I, at - at the output terminals from returning to the input grounds.
Bypass-capacitor grounds also were selected to achieve the
pin 8. The operating.point stability is provided by de
same purpose. It is recommended that bypass capacitors be
feedback to the input stage. The input voltage for an output
placed on terminals of the auxiliary functions since most of
3 dB below limiting is typically 12 microvolts rms.
them are connected to rectifier circuits which are not
The detector is a doubly balanced circuit driven
completely filtered within the device. Capacitors of the disc
symmetrically by the output of the if amplifier. The voltage
ceramic type with a 0.01- to 0.02-microfarad value are
at pin 8 is coupled through a reactance to the tuned circuit at
usually good bypass capacitors at 10.7 MHz. Larger values
pin 9. The detector output is taken from both sides and
may exhibit a self-resonance below 10.7 MHz, and actually
combined differentially to produce an audio output and
exhibit inductive reactance at their terminals. The nominal
automatic·frequency·control voltage. The audio output may
input impedance of the CA3089E is approximately 9,000
be attenuated by a current driving pin 5. The current is
ohms, and it is not recommended that an impedance match
normally provided by the mute drive, which reduces the level
be attempted. Most commercial receivers use ceramic-filter
by more than 50 dB. Fig. 2 shows the detector and
frequency-selective elements that normally have source
audio·AFC translator circuits redrawn to illustrate the
impedances of 500 ohms or less. When these flIters are
balanced circuitry. The audio output is developed across a
properly terminated with loading resistors, the typical source
5,OOO-ohm resistor, R49, Fig. I. The AFC output can be used
impedance is further decreased to 250 ohms or less. Higher
either as a current or voltage source.
levels of source impedance are possible with very careful
circuit layout; however, the maintenance of stability could
The meter output and rf·AGe circuits are driven by three
be difficult.
level detectors which detect the output levels of each of the
if amplifier stages. The tuning-meter circuit sums these levels
The CA3089E has a frequency response that is typically
and provides a voltage which is a function of the input signa\.
flat to 20 MHz; consequently, the device can provide useful
The rf-AGe circuit is driven by the level detector connected
gain well above that frequency. If the device is used at lower
to the output of the first amplifier stage, which provides the
frequencies, the larger-value bypass capacitors required may
delay. The mute logic output is developed from the output
not be adequate to bypass the higher frequencies. Double
of the third limiter. With a large signal, the if envelope is
bypassing with lower·value capacitors can overcome such a
detected, and drives the mute logic voltage low. As the
problem. Another means of alleviating the problem is to
signal-to-noise ratio deteriorates, "holes" are created in the
externally reduce the frequency response by using a small
envelope; these "holes" are detected, and provide the voltage
capacitance across the output load of the device.
to drive pin 5.
The bias supply maintains the device current drain
Quadrature-Detector Circuits
virtually constant from a supply voltage of 16 volts to
apprOximately 8 volts over a temperature range of -4O"C to
The quadrature-detector tuned circuit is connected
between pins 9 and 10. The signal voltage at pin 8 is
+IOO"C while maintaining the performance of the device

349

ICAN·6257

IF AMPLIFIER

RS
2K

C:'~

R27
750

RI9
2K

R7
2K

~~12

R'2
2.7K
R'5
2.7K

INPUT

BY-

PASSING

R,
30K
V+
V+

Q74

RSO
500

R59
150

I~

v

LEVEL DETECTOR S METER CIRCUIT

Fig. 1 - Schematic diagram of the CA3089E.

350

RSO
300

92CL·19883

ICAN-6257
IF

II

OUT

v+

AUDIO
~
R38
500

R65
50K
MUTE

R43
500

CONTROL

AFC
OUTPUT

AFC AMPLIFIER

C(

FRAME

~

SUBSTRATE

~

ALL RESISTANCE VALUES ARE IN OHMS
All. CAPACTANCE VALUES ARE IN PICOFARADS

92CL-19883

MUTE DRIVE

Fig. 1 - Schematic diagram of the CA3089E.

351

ICAN-6257

--

16

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12-

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3dB LIMITING

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40

TEMPERATURE-·C

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?- Detector, audio, and AFC circuits.

6

23~--~--~---+~~~~~--~---+--~
22

__

--

RECOVERED AUDIO

3OOI---+---+---+---4~--+---+---+----l
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RF-AGC VOLTS AT 'in"'O mV

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14

SUPPLY VOLTAGE-V

15

6

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RF-AGC VOLTS AT ein =10 mV

~

20

40

60

24
23

rf~AGC,

100

80

92CS-2334!5

and meter output as B function of

- -l

SUPPLY CURR£;;;

2.

r--- r---

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big
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METER OUTPUT AT 'in .S00Il-V

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10

SUPPLY VOLTAGE-Y

Fig. 4- Reference voltage,
supply voltage.

352

Fig. 6- Reference IfOltage,
temperatule.

,!

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~0

o

- 0

TEMPERATURE-·C

.•

~'N 10 REFERENCE VOlT~GE

5

>

0
-40

16

92CS-21342

Fig. 3- Supply current, reCOllrlrsd audio, and input limiting as !I
function of supply voltage.

4

METER OUTPUT IJ ein "500p.V
I

I
12

10

'f REFER~NCE VOlTAGE

4

>

~~ 13~--+----r---+--~L---+----r---+---1
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function of

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400

Pin

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mil!~,
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100

temperature.

~_

24

80

92CS-23344

Fig. 5- Input limiting and recovered audio as a
Fig.

~

rf~A Ge,

13

14

15

16

.20

0

~! -20

-40

92C5-23343

and meter output as a function of

AFC

TT
AGE

-20

7-10 fOSS

-

0

20

"I~r-40

TEMPERATURE--C

60

r--

80

10o

92C5-Z33"16

Fig. 7- Supply current and AFC voltage as 8 function of temperature.

ICAN-6257

a) Bottom view of printed-circuit board.

ALL RESISTANCE VALUES ARE IN OHMS
*L TUNES WITIi IDOpF Ie) AT 10.7 MHz
QoIUNLOADEDJ1I75

(G.I. AUTOMATIC MFG. DIV. EX2274, OR EQUIVALENT)

92CM-190

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TUNER AGe DC VOLTAGE
TERMINAL1NQ.IS

10K

lOOK
92CS-2)318

Fig. 13- Tuner AGe and tuning-meter output as a function of input
signal voltage.

Fig. 15-Suggested PC-board pattem and parts layout for the circuit
of Fig. 74.-

Fig. 14-/F amplifier/detector system and stereo decoder.

356

ICAN-6257
amplifier and inverter to each circuit. A simple example using
a CA3096E IC transistor array is shown in Fig. 16.3
. The CA3089E may be used effectively in narrow-band
communication receivers. In double-conversion receivers,
some of iIle functions of the CA3089E are negated at a
4SS-kHz intermediate frequency. However, if a 1O.7-MHz
intermediate frequeney is used. all of the auxiliarv features

92r.5-233:>2

Fig. 17-Oetector frequency-stabilization circuit.

amplified by the op-amp and drives a varactor to maintain
the tuned frequency on the incoming-signal frequency.

"'2C5-23351

Fig. 16-External mute and rf·AGC drive circuits fpr the CA3089E
operating at 455 kHz. External transistors are parts of the
CA3096E n-p-n/p-n-p transistor array.

may be used, but another set of problems is encountered.
The small deviation signals encountered in narrow-band
systems require the use of high-Q circuits in the quadrature
detector, as indicated in Table I. However, variations in
extemal·component parameters with temperature changes
may cause the tuned frequency of the detector to drift out
of the if pass band. Normally temperature·compensated
components are necessary. The CA3089E, operating in
conjunction
with
an
inexpensive
operational
transconductance amplifier,4,5 provides means of locking the
tuned circuit to the incoming frequency. Fig. 17 shows the
block diagram of such a system. The AFC output voltage
developed across the resistor between pins 7 and 10 is

The CA3089E may also be used as the core of an
ultra·linear FM generator; Fig. 1'8 shows the circuit. The
carrier is generated by the CA3089E with the introduction of
feedback from the output terminal; pin 8. The carrier is
modulated by the varactor connected across the tuned circuit
at the input of the CAJ089E. The varactor is driven by the
output of the differential amplifier, AI, using a CA3028
IC.6,1 This differential-amplifier stage is driven at one of its
input terminals by the audio modulating signal. Negative
feedback of the audio signal is provided by driving the other
differential-amplifier input from the recovered audio output
of the CA3089E at pin 6. The detector circuit uses a
double-tuned transformer to produce audio with very little
distortion at pin 6. This feedback technique results in a very
iow distortion modubtion.
rf output of the CA3089E atpin 8 is essentially . a square wave, and is fed to a
tuned-amplifier stage to buffer the signal and restore the
sine-wave-shaped rf output signal.

The

+IZV

+12V

.00
100

+12V

MODULATION
INPUT

10<;.-1

TlsG.I. EX23656

25V

LI= 34 lURNS No. 36 WIRE
TAP AT 5 TURNS
TYPE "E"CORE

100

~O.OIPF
':I2C"'-23354

Fig.1S - FM generator circuit.

357

oornLJD

Linear Integrated Circuits

Solid State
Division

ICAN-6259
Integrated-Circuit Stereo Decoder
Using the CA3090AQ
Stereo Multiplex Demodulator
by

l.A. Kaplan, and A.l. Limberg
RCA Solid State Division
Somerville, New Jersey, 08876

The demodulation of FM stereo broadcast information may
be accomplished very simply by use of no more than three
transistors, four to six diodes, and two small transformers as
major system components. All of these components may be very
inexpensive with minimal specifications. However, accurate
demodulation of FM stereo broadcast information, particularly
when the signal to noise ratio of the incoming signal is poor and
when the performance must be achieved over a wide ambient
temperature range such as, for example, in the automobile
nidio, is' an entirely different matter.
The system shown in Fig. 1 was built by RCA's Transistor
Applications Laboratory to demonstrate a high-performance
demodulator system. Some of the design considerations will be
discussed later, but the complexity of the filtering included and
is evident.
the bulk ofthe

Fig. 2 - Integrated-circuit mUltiplex stereo decoder.

Table I - Performance Data
40dB

SEPARATION
DISTORTION

2nd Harmonic
3rd Harmonic

4th Harmonic
5th Harmonic

,.
Fig. 1 - Multiplex stereo decoder using discrete componen ri.

By contrast, the integrated-circuit system described in this
Note*, Fig. 2, performs all the functions of its predecessor,
and does them better. Performance of the IC system is summarized in Table 1.

* This

Note supersedes RCA Tt".chnical Publication ST-4700, "[ntegrated-Circuit Stereo Decoder Does Everything," by L.A. Kaplan.
H.M. Kleinman, A.L. Limberg.

358

CAPTURE (%of CENTER FREQUENCY)
SCA REJECTION
iviONAURAL GAIN (75jlS DE-EMPHASIS,
1 kHz)
GAIN BALANCE BETWEEN CHANNELS
STERO/MONAURAL GAIN BALANCE

<0.2%
<0.1%
<0.1%
<0.1%
10%
-55 dB
6dB
<0.5 dB
<0.5 dB

INPUT IMPEDANCE

50 kilohms

TEMPERATURE COEFFICIENT OF
LOCAL OSCILLATOR

-16 Hzt"C

LAMP DRIVER CURRENT

100mA

1·74

ICAN-6259

DESIGN REQUIREMENTS AND OBJECTIVES

The stereo multiplex demodulator has simply defined tasks.
First, it must reconstruct the 38-kHz carrier which was
suppressed in forming the stereo signal. This reconstructed
carrier must be properly phased to accomplish the demodulation
process. Second, it must be substantially noise free to avoid
further significant degradation of the signal-to-noise ratio of the
output. This signal has already been degraded from that
achieved in monaural transmission because of the wider system
bandwidth of the stereo transmission.
A further function which demands narrow bandwidth in
each channel is the stereo indicator which detects the presence
of the 19-kHz pilot and energizes a lamp to inform the listener
that stereo is being transmitted. If the bandwidth of the 19-kHz
filters is too wide,noise energy in the pass-band of the filter can
be sufficient to cause the light to blink during tuning between
stations. This effect is undesirable in a high-quality system.
In essence, the demodulator must use the reconstructed
carrier to demodulate the composite signal without introducing
objectionable distortion. It must also have provisions for
inhibiting the demodulation function when poor signal-to-noise
conditions exist and, finally, must ignore completely the SCA
signal transmitted by some stations. This signal is a second
subcarrier bearing FM information modulated at about 67 kHz.
Unless care is taken, the intermodulation products of the 38kHz subcarrier (stereo) and the 67-kHz subcarrier (SCA) form
audible beats.
These requirements of phase fidelity and low noise are
difficult to achieve simultaneously in a compact, inexpensive
system using traditional techniques because of the method of
carrier synchronization. The 19-kHz pilot signal must be
selected, amplified, and doubled without disturbing its phase
relationship with the 38-kHz difference-signal (L-R) information. When conventional LC filtering techniques are used,
contlicts are established. If noise is to be reduced in the
subcarrier regeneration process, narrow bandwidth is needed in
that channel. Narrow band filters, unless they are both
accurately designed and precisely tuned, can cause substantial
phase shift.
Analysis shows that 26 degrees of phase shift of the 38-kHz
subcarrier relative to the 38-kHz sidebands will degrade the
separation of an otherwise perfect system from infinity to 26
dB. Because a degradation of 20 dB would cause' the system to
fail most instrument specifications and would be detectable by
critical listeners in some situations, it is reasonable to demand
that phase shift in the subcarrier not consume all of the
permitted degradation.
If each transformer were to have a 9-degree phase shift at 38
kHz, the reactance factor X for the 38 kHz trans.=0.1.58, where
X = 2l!.fQ/fo' This condition is obtained when the attenuation in
that transformer is computed from X = tan-IO and the
attenuation (p) =
JT+X2 so that p = JI + (.1582)2 = 1.012
. or less than 0.1 dB. Because only 4.5 degrees are permitted in
each of the 19-kHz transformers, the attenuation for permissible
phase shift will be less than 0.1 dB.
This analysis clearly shows that manual tuning of the
subcarrier channel cannot be achieved by the traditional

peaking methods, rather, it must be aligned by measuring
channel separation characteristics. Further, once correct tuning
is achieved, the permissible mistuning resulting from mechanical
or environmental conditions must be low. If quality factors
(Q's) of 25 are assumed, the permissible mistuning of a 19-kHz
transformer is given by

::f = tan 4.50° = 0.08 or a 16%
f

2Q

50

.

and for the 38-kHz coil:
tan 9° = 0.16 or 0.32%
50
50
Thesevaluesrepresent a mistuning of 30 Hz at 19 kHz and 120
Hz at 38 kHz, respectively. If the mistuning is due only to
temperature over a ±50°C ambient temperature range, the
following temperature compensation is required:
l!.f /
= 0.0016 = 0.0032
f / l!.T
50
100

= 0.000032

or 32 PPMtC for the 19-kHz transformer and 64 PPMtC for
the 38-kHz one. Finally, if higher Q coils are used to improve
selectivity and to reduce noise in the subcarrier, the stability of
the circuits must be even better.
Non-distorting demodulation and stereo disabling can be
accomplished easily, but care must be taken to insure that the
latter be accomplished in a manner that eliminates transient
level shifts when the switching occurs. Rejection of the SCA
channel is generally guaranteed to some extent by LC filtering at
the input to the demodulator which removes signal components
above 60 kHz. This method requires either expensive pre tuned
componimts, or an additional alignment, and runs the risk of
causing phase shift of the higher subcarrier sideband frequencies,
thereby degrading separation for the highest frequency components of the program.
There are three specific problems which the designer of a
stereo multiplex demodulator must consider ifhe has to achieve
an economical high performance design:
I. Provide a narrow band carrier regeneration channel with
negligible phase shift over the ambient temperature range
and life of the equipment. This setup should preferably be
alignable with a single simple adjustment.
2. Develop a system which inherently rejects the 67-kHz
SCA subcarrier so that an LC filter is not required for
that purpose.
3. Provide stereo-monaural switching without audio "plops".

In addition to these rather difficult problems, the designer must
not ignore distortion which must be kept well below 0.5
precent, and, of course, he must minimize the cost of external

components .
Description of the RCA CA3090AQ Stereo
Multiplex Demodulator IC

Fig. 3 shows the CA3090AQ as it is used in a typical FM
receiver. From this illustration, the solutions to the problems

359

ICAN-6259 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
v+o--1----------------------.-~__,

10K

IA) COMPOSITE SIGNAL
(BI STEREO ENABLE SIGNAL
tC l STEREO GATING SIGNAL
IDI DIFFERENCE SIGNAL

* SIMULATE
TEST NETWORK, TO
I dB ROLLOFF
AT !i8 kHz DUE TO FM
DETECTOR
STEREO DEFEAT I ENABLE

L-12V,IOOmA LAMP
Ct. C2 PROVIDE
DE - EMPHASIS

92:CM-23528

Fig. 3 - Block diBgram of ,he RCA CA3090AO system.

posed previously will be studied. In this circuit, carrier regeneration is accomplished by use of a phase-lock automatic frequency and phase control (AFPC) loop made up of a voltagecontrolled oscillator operating at 76 kHz, a series of flip·flops
to obtain the required signals needed in the system, and a
synchronous detector the DC output of which is proportional
to the relative phase angle between the frequency-divider out·
put and the 19-kHz component of the composite signal. Band·
width of the loop is detennined by an external RC filter and,
as will be shown later, the steady-state phase error is only
indirectly related to the bandwidth of the phase.locked loop.
The voltage-controlled oscillator (VCO) used in this circuit is
an LC oscillator. This type was chosen over the apparently
simpler RC oscillator on the basis of its superior long·term and
temperature stabilities. It is noted that the oscillator operates at
76 kHz, while the maximum frequency required by the signal
processing circuits is 38 kHz. The higher frequency is used at the
expense of extra chip complexity to insure that the reinserted
38·kHz carrier is perfectly symmetrical, because any loss of
symmetry will impair audio-channel separation. By starting at
76 kHz and dividing by two to get the required 38 kHz,
symmetry is guaranteed, though the phase of the 38 kHz may
shift relative to the 76-kHz voltage. This shift, however, is not
Significant.
Fig. 3 also shows that the switching input to the phase.
detector (AFPC) is not in phase with the pilot frequency but is
displaced by 90 degrees. This condition will exist when there is
no phase error, because the demodulator is a multiplier whose
output is proportional to the cosine of the angle between the

360

inputs. Because the output of this detector may be considered as
an error voltage in a feedback loop, the system will attempt to
make it zero, hence, the 90° displacement so