1975_RCA_Linear_IC_Application_Notes 1975 RCA Linear IC Application Notes
User Manual: 1975_RCA_Linear_IC_Application_Notes
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LINEAR Integrated Circuits
Application Notes
A New Approach To Data Service
1975 RCA Solid State OAT ABOOKS
Seven textbook-size volumes covering all current commercial
RCA solid-state devices (through January 1, 1975)
Linear Integrated Circuits and DMOS Devices
(Data only) .............................. SSD-201C
Linear Integrated Circuits and DMOS Devi'ces
(Application Notes only) ....................SSD-202C
COS/MOS Digital Integrated Circuits ...........SSD-203C
Power Transistors .......................... SSD-204C
RF /Microwave Devices ...................... SSD-205C
Thyristors, Rectifiers, and Diacs ..............SSD-206C
High-Reliability Devices ..................... SSD-207C
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configurations. 2 These circuits are not widely used
in vhf applications, however, because their gain is
low at high frequencies.
oUTPUT
RL~50n
33._
RFe
aKIl
IOOOpF
I
,,"S
1000"
1)
-14V
INPUT
L1 = tN~n~'j,'~~~ ~:p~t~:el
L2
101
0.82,."
Voo
+16V
:J.~6 inch in dia.,
=3-1/2 turns of No.20 wire, 3/8 inch in dia.,
1/2 inch long
'" Leadless disc capacitor
Fig.3 - 200-MHz common-source amplifier.
Ibl
FigA illustrates the effect of the leakage resistances RL 1 and RL2 when the insulated gate is floating. When these resistances (~1014 ohms) are approximately equal, they form a voltage divider which biases
the insulated gate at +Voo/2. This value of bias
voltage m8JI exceed the maximum rating for positive
gate voltage and, in addition, may cause an excessive
flow of drain current.
RLI,f\.2 • LEAUGE RESISTANCES
leI
Fig.2 .. Bias methods lor common-source MOS transistor
stages: (a) fixed bias; (b) source-resistor bios;
(c) constant-current bios.
Fig.3 shows a 2OO-MHz common-source amplifier
used to measure the rf power gain of the MOS transistor_ This amplifier uses amadified form of the constantcurrent biasing arrangement shown in Fig.2(c}. With
this modified biasing arrangement, both the insulated
gate and the case of the MOS transistor are operated
at dc ground potential. The insulated gate should
always have a dc path to ground even if the path is
through a multimegohm resistor. If the gate is allowed
to float, the resultant dc bias conditions may be unJRdictable and possibly harmful.
Fig.4 - Bios conditions 'or on MOS transistor
when the insulated gate is 1I00ting.
The cascade configuration represents a useful
variation of common-source circuit. In this configuration, a common-source-cormected MOS transistor is
used in the lower section of the cascade, and a commongate-connected MOStransistor is used in the upper section. Fig.5 shows the use of MOS transistors in a 200MHz cascode amplifier. This circuit normally requires
a negative voltage on the gate of Qlo a positive voltage
on the gate of Q2, and approximately equal drain-tosource voltages for each transistor. Although the gate
of Q2 may require a positive voltage of 5 to 10 volts,
the net gate-to-source voltsge for this transistor should
be approximately 0 to -1 volt.
15
AN·3193 " - - - - - - - - - - - - - - - - - - - - - - - - - - - o.9-7pF
dissipation of 30 milliwatts, for example, the 3N128
typically provides a power gain of 17.3 dB and a noise
figure of 3.9 dB when operated at 15 volts and 2,milliamperes. At the same dissipation level, however, the
power gain is reduced to 14.6 dB and the noise figure
is increased to 4.7 dB when the 3N128 is operated at 6
volts and 5 milliamperes. Fig.6 shows the variations
in power gain and noise figure of the 3N 128 as functions of the drain current and voltage.
SUBSTRATE AC GROUNDED
AT DC GATE POTENTIAL
VO"IS V
18
/
16
Selection of Operating Point
The 3NI28 provides maximum rf power gain at a
drain-to-source voltage Vns of approximately 20 volts
and a drain current In of about 5 milliamperes. The
transistor also exhibits a minimum noise figure at a
Vns of 20 volts for a drain current of about 2 milliamperes. The difference in the noise figures obtained
at 2 milliamperes and at 5 milliamperes, however, is
very small (usually between 0 and 0.2 dB) and generally
is not a significant factor in the selection of the operating point. Although a Vns of 20 volts represents the
optimum value for the 3NI28 in terms of both rf power
gain and noise figW,e, this' value is also the maximum
VOS rating for the transistor. Greater long-term reliability is achieved, therefore, by operation of the 3NI28
at a Vos of 12 to 15 volts rather than at 20 volts.
For a Vos of 15 volts and an 10 of 5 milliamperes,
the 3N128 typically provides a power gain of 18 dB and
a noise figure of 4 dB at 200 MHz. Operation of the
. 3NI28 at considerably lower drain currents, such as
those normally employed ill bnttcry-pmvered equipment,
does not seriously affect system performance. For
example, when the transistor is operated at a Vns of
15 volts and an 10 of only 1 milliampere, the power gain
and noise figure at 200 MHz are typically 15.5 dB and
4.5 dB, respectively. Because the MOS transistor is a
voltage-controlled device, -its performance for a given
power dissipation can often ,be improved by operation
at high voltage and low current levels. At a power
16
POWER GAIN
I
Fig.S. 200·MHz,cascocle amplifier.
The operating point selected determines the power
gain, noise figure, power dissipation, and, where applicable, battery life. In many applications, a compromise
between gain and available supply voltages or battery
lifetime is necessary. Knowledge of the variation in
gain and noise figure as functions of voltage and current ,is essential, therefore, before an operating point
can be selected.
.,,---
.
r\
12
6!l:
...I
NOISE FIGURE
!!i
4~
~
~
100
4
10
6
DRAIN CURRENT -
20
2
rnA
SUBSTRATE AC GROUNDED
AT OC GATE POTENTIAL
10"5 rnA
8
/
'"I'6
z
g
/
a:
~I 4
2
10 0
l.-~GAIN
•
~
,4
NOISE FIGURE
8
12
DRAIN VOLTAGE -
16
2
20
V
Fig.6 • Power gain, ancl noise figure of the RCA 3NJ28
at 200 MHz as functions of clrain current ancl voltage.
A gate voltage VG of between -0.5 and -2 volts is
normally required to bias a 3N128 for operation at a '
drain'volLuge Vn oi 15 volts and a drain current in of
5 milliamperes. If a fixed-bias circuit, as shown in
Fig.2(a), is used, the value of the gate voltage must'
be adjust.able to compensate for variations among individual transistors. For the source-resistance bias circuit shown in Fig.2(b) the value of the biasing resistor
should be 200 ohms (5 mA x 200 ohms = '1 volt>. The
source-resistance circuit will limit the variations, in
current among the different transistors to approximately
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - AN-3193
50 per cent. With the constant-current bias circuit
shown in Fig.2(c), variations in current from one transistor to another can easily be limited to less than
10 per cent. Regardless of the bias circuit or the bias
point selected, there is no danger of thermal runaway
with the 3Nl28 because this transistor has a negative
temperature coefficient at the zero-gate-bias point. In
the selection of the bias circuit for an MOS transistor
stage in which automatic gain control is employed, consideration should be given to the following principle:
The more restrictive the tolerance imposed on quiescent
operating-point current, the more difficult automatic
gain control of the stage becomes because the selfcompensating action of the constant-current bias circuit
also resists current changes that result from the agc
action.
AGC Methods
When it is necessary to employ age in an MOS
transistor stage, either of two methods may be used to
reduce transistor gain. In one method, referred to as
reverse agc, the reduction in gain is accomplished by
an increase in negative gate bias. In the other method,
the gain is decreased by reduction of the drain-tosource voltage_
In the reverse agc method, the application of higher
negative voltage to the gate reduces the drain current
and the transconductance of the transistor. The low
feedthrough capacitance of the 3N128 (typically about
0.13 picofarad) usually permits more than 30 dB of gain
reduction at frequencies up to 200 MHz. Substantially
greater gain reduction can be achieved at lower frequencies or in neutralized amplifier circuits.
Gain reduction achieved by the decrease of drainto-source voltage is usually controlled by a variable
impedance in series, or in shunt, with the MOS transistor. The variable impedance may be another MOS
transistor or a bipolar transistor. A major disadvantage
of this method is that the MOS feedback capacitance
rises by a factor of 4 or 6 times as VD approaches
zero. This increase in capacitance reduces the agc
range obtainable and decreases the effectiveness of
a fixed neutralization network. In addition, the output
impedance of the 3N 128 decrease s with a reduction in
the drain voltage.
In the cascode circuit, agc is accomplished most
effectively by application of a negative voltage to the
gate of the upper (common-gate) section. A wide agc
range can be obtained in this circuit. Gain reductions
greater than 45 dB at 200 MHz or 65 dB at 60 MHz are
realizable in an unneutralized cascode circuit.
RF Considerations
One of the prime advantage s of the 3N 128 MOS
transistor over bipolar transistors is its superior cross-
modulation, intermodulation, and modulation distortion
performance. The 3N128 has considerably lower feedback capacitance than junction-gate field-effect transistors. In addition, the 3N128 maintains a high input
resistance at frequencies well into the vhf range (the
real part of the input admittmlCc, Rc(y 11) = 0.15 mmho
at 100 MHz).
At maximum gain, the cross-modulation distortion
of the 3N128 is approximately one-tenth that of most
bipolar transistors, or roughly comparable to the crossmodulation performance of vacuum tubes (at 200 MHz,
an interfering signal of approximately 80 millivolts is
required to produce cross-modulation distortion of 1 per
cent>. However, cross-modul ation susceptibility changes
as the gain of the stagc"is changed. For a single
3Nl28, the cross-modulation distortion increases when
reverse agc is applied; the distortion is also increased,
but to a lesser extent, if agc action is achieved by reduction of the drain-to-source voltage. A deterioration
in cross-modulation performance at high attenuation
results from the fact that the MOS triode is a sharpcutoff device; as a result, large non-linearities occur
near "pinch-off." Beyond "pinch-off," the transadmittance depends primarily upon the capacitive feedthrough, which does not have large third-order nonlinearities. Cross-modulation performance at the extreme limits of attenuation, therefore, is very good. 1
In cascode stages, the effect of reverse agc on crossmodulation distortion is reduced when the agc is applied
to the gate of the common-gate stage; application of
reverse bias to the gate of the common-source stage
results in cross-modulation performance similar to
that of a single triode-connected stage. Figs.7 and 8
show the variation in cross-modulation susceptibility
as a function of agc_ The test circuits used to measure
cross-modulation distortion of .MOS transistors are
shown in Fig.9.
INITIAL BIAS CONDITIONS
TRIODE~ YO -15 V, ID·~mA
CASCODE: VO-20 V. IO-IOmA
f OES ·200 MHz
'INT- 150 MHz
UNTUNED INPUT
0
0
~A~I~E1J.l
\
J .I JJ CASCODE ill'....
(UNNEUTRALIZED)
1\
TRIODE (UNNEUTRALIZEDl
0
0
K
10
o
'=
.p: :~
"-;--..
10
~V
~
50
/
V
p:-
.00
100
INTERFERING SIGNAL -
mV
Fig.7. Cross.moclulation distortion as a Function
of the attenuation produced
by reverse age.
17
AN·3193 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - FREQIEMCY-zoo...,
==::vr
NTIAL .... CCNDITIONS
DESIRED
VOS-15V
FREGUENCY - II011H1
ro-5mA
,
II
I
I!!
~
!C
(.
.. ..~
-
,.)
lR\OIIE·COIIIIECTED
,./'
'~_I-
~
IllNNEUTRALIZEQ
I'\-..
100
1000
~SIGIW.-'"
Fig.8 • Cross.modulation distortion as a function
.·f the attenuation produced when agc is accom·
p lished by a reduction of drain·to·source yoltage.
The test circuit shown in Fig. 10 is used to measure
the intermodulation distortion of MOS transistors. In
such measurements, the receiver is tuned to 150 MHz.
The MOS is then inserted, and bias voltages are applied. When no signals sre applied . The capacitance
bridge becomes more apparent when the circuit is redrawn as shown in Fig.1Ub). The condition for neutral-
where Re means "the real part of."
All MOS transistors have a small, but measurable,
feedback component (y 12); it is possible, therefore,
that some of them will oscillate under certain circuit
conditions. This possibility may be checked by use
of methods given by Linvill 2•4 and by Stem. 3,4 If the
transistor is unconditionally stable for any combination
of passive source and load admittances, then Linvill's
critical stability factor C, as determined from the following equation, is less than 111:
IY21 Y121
C=.
2Re{Yll )Re(Y22)- Re{Y21Y12)
rn
* Conjugate match means that the transistor input and the
generator and the transistor output and load are matched
resistively and that all reactance is tuned out.
Fig.11 - Capacitance-brielge nelltralization circllit:
(a) actllal circllit configllration; (b) circllit reelrawn
to emphasize capacitance-brielge network.
19
AN-3193---------------------------------------------------------ization is that if
in- This condition implies the
following relationship:
vd -Vn or Cfvd = -Cn vn
jXf = jXn'
(4)
The voltage vn is defined by the following equation:
v
n
=(~)jX
=~ ~LCI
Vd ~ __
1_ _
Vd
VX +jX
I
+1 jwCI -w 2LCI +1
L
the generator admittance y g and the real part of the
transistor input admittance must appear to be equal_
Because the generator admittance yg is 20 mmhos and
the real part of the input admittance Re (yu) is 0.45
mmho, the coupling transformer must provide a transformation ratio of 44 to obtain tbe desired impedance
match.
The turns ratio required is determined as
follows:
"(5)
1
IWCI
If this relationship for vn is substituted in Eq.C4l, the
following result is obtained:
CrVd = -cn ( 2Vd
), or Cn = -CC<-w 2LCI +1>
.
-WLCI+1
(6)
At resonance, the equation for the neutralization capacitance Cn may be rewritten as follows:
Cn = -cr[
~-~;)WCI +1] = Cr(~> 1)
(7)
If CI» C2, Eq.(7) may be rewritten as follows:
Cn
~ Cr (~~)
(8)
The other common method of neutralization is the
transformer-coupled method shown in Fig.12. Again,
the condition for neutralization is that if = in. The
requirements for this condition are expressed by the
following equation:
Experimentally, a toms ratio of 4 was found to be approximately the optimum value. This difference results,
in part, from the fact that the parallel resistance of
the tank coil was not considered in the calculation.
At the output of the ~z amplifier, the load is also
50 ohms. Because the dc drain voltage must be blocked
from the load, a series matching capacitor was selected
which performs both dc blocking and resistive matching
simultaneously.
In the actualload-circuit nehvork shown in Fig.13( a),
the value of capacitor C s must be chosen so that the
load admittance, YL = 20 millimhos, is apparently equal
to the real part of the transistor output admittance,
Re>
Rs , then Cp ~ Cs . Therefore, a 3-picofarad capacitance
appears in paranel with the l.4-picofarad capacitance
of the MOS transistor. A small 1-to-9-picofarad variable
air capacitor was selected for the tank tuning capacitor
to compensate for variations among transistors. For a
nominal value of 2 picofarads for the air capacitor, the
total output capacitance is 6.4 picofarads. The inductance required to resonate with 6.4 picofarads at 200
MHz is 0.1 microhenry. When the total output capacitance is known, the required neutralization capacitor
can be calculated. If Cl is arbitrarily selected as 33
picofarads, the neutralization is determined from Eq.(S),
as follows:
(E..) = 1.0 pF
Cn ~ cr(Cl) = 0.2
C2
6.4
The optimum value for the neutralization capacitor
was determined experimentally by use of a small
Capacitive bridge neutralization is used to
achieve the maximum allowable stage gain of 20 dB
for the particular 3N 128 used.
The input coil of the mixer stage is designed to
permit a conjugate match with the transistor input
admittance. The input admittance Yll of the 3N128
at 200 MHz is approximately 0.45 + j 7.2 millimhos.
Therefore, an admittance of Y11* (=0.45 - j 7.2 milliaool
3O-MHz
OUTPUT
05-3
4T
... 31S'D
TAP
5100
AT1T
2000
Fig.2 - VHF receiver "'ron' end" using the 3H128 in all stages.
• Design information for vhf MOS amplifiers is given in RCA Application Note AN-3193:
"Application Considerations for the RCA-3Nl28 VHF MOS Field-oEffect Transistor." by F.M. Carlson, August 1966.
23
AN-3341
mhos} should be presented to the mixer input_ A conjugate match is not used at the output because it is
desirable to load the input of the following (if) stage
for stability. Therefore, a step-down transformer is
used. {A conjugate match would require use of a stepup transformer because g11 > g22 at 30 MHz.}
The local oscillator is coupled into the insulated
gate of the mixer by means of an ungrounded 34O-degree
loop placed around the input tank coil at its highimpedance end. A small coupling capacitor could also
be used for this purpose. Local-oscillator. amplitude
is approximately 1.4 volts rms into the coupling loop.
Power gain of the mixer stage is 16 dB. Fig.3 shows
the conversion gain of the mixer as a function of localoscillator amplitude. A lower oscillator level than
1.1 volts would probably be desirable if spurious output
frequencies were found to be troublesome.
FREQUENCY·200 MHz
~20
I
z
z
0
~>
/'
0
Z
8-10
-20
/
V
--- -
I
1500
1000
1500
LOCAL OSCILLATOR AMPLlTUOE-mV
2000
Fig.3 - Conversion gain of the mixer stage in Fig.2
as a function of local-oscillator omplituc/e.
A 510-0hm source resistor is used in the mixer
stage to provide a drain current of 4 milliamperes.
{This value is larger than would normally be expected
for a drain current of this level because the gate is
subjected to large signal excursions by the local
oscillator.}
The maximum available gain (MAG) of the 3Nl28
at 30 MHz in a conjugately matched circuit {with Y12
24
assumed to be approximately zero} may be computed
from the y-parameters for the device, as follows:
IY211 2
17.212
MAG =
= 3610 = 35.6 dB
4 g11 g22 4
When the resistance between the drain and source terminals is low (100 to 300 ohms), an MOS transistor is
said to be ON; the drain-to-source channel resistance is
then design.ated as rds(ON). This ON condition correspilni!s to the closed-switch condition in the circuits
of Fig.1_
(a) SUBSTRATE CONNECTED
TO SOURCE
SUBSTRATE CONNECTED TO SOURCE
AMBIENT TEMP. • 25-C
.. 2'01--,---,--,---:-=r::-i
E
~1501---r--1---r-1~~7'-+-~
!:!
IZ
(bl SUBSTRATE
FLOATING
~ 501---r--1---h~~~~-+-~
B
o~~~=-__~~~~~~===¥==~
~-501---r-~F-~~--1---+-~
~
E
a:
-1'01---r7'-H-1I'-+--r--1---+-~
a:
::>
u
z
;;
~
tel SUBSTRATE CONNECTED
TO DRAIN
DRAIN-TO-SOURCE VOLTAGE (Vosl-mV
Fig.3 - Low-level Jrain current as. a lundion 01 Jrain-tosource voltage in an n-channel Jep/etion-type· MOS
transistor with substrate connected to source.
DRAIN-TO-SOURCE VOLTAGE eVDs J-2V/DIV.
(o.b,c'-I ,VOLT PER.STEPIORIGlN_ No significant connected to the source. However, if the incoming
26
-------------------------------------------------------------AN-~52
signal to be chopped exceeds -0.3 volt, the substrate
must be "floated", connected to the drain, or biased
negatively so that the source-to-substrate and drainto-substrate voltages never exceed -0.3 volt. If this
state conditions in an MOS shunt chopper. For the ON
condition, the output voltage EO is given by
(1)
OUTPUT
In Eq.(1), it is assumed that the gate leakage resistance
RG is much larger than the drain-to-source resistance
rds. If the load resistance RL is also much larger than
rds; Eq.(1) can be simplified as follows:
(Q I SHUNT CHOPPER
Eo • Es
[~J
Rs + rda
(2)
OUTPUT
VG. OD-....JIIVIr-.....
RS
"G
A,
"V\I" GATING SIGNAL
NOTE: ALTHOUGH RESISTANCE RG IS ACTUALLY
DISTRIBUTED ALONG THE LENGTH OF rds,
CONNECTION SHOWN ASSURES A WORSTCASE ANALYSIS.
(b) SERIES CHOPPER
Fig.S - Steady-state equivalent circuit 01 MOS
shunt chopper.
OUTPUT
For EO to approach zero, it is necessary that the source
resistance
be much greater than rds. The value of
EO is then given by
RS
as
EO • Es (rd/RS)
(c I
SERIES - SHUNT CHOPPER
A typical value for RS and RL in an MOS shunt chopper
is 0.1 megohm. A typical value of rds(ON) for the 40460
transistor is 90 ohms. If these values are substituted
in Eq.(3) and the signal voltage ES is assumed to be
1 millivolt, EO is calculated as follows:
Fig.4 - Basic MOS chopper circuits.
value is exceeded, the substrate, which forms two p-n
junctions with the drain and the source, becomes forward-bi ased and the resulting flow of diode current
shunts the incoming signal to ground.
(3)
EO
= 10-3 (90110 5 ) = 0.9 microvolt
1n the ON condition, therefore, the dc error voltage is
less than 0.1 per cent forthe values used, and is directly
proportional to the input sigoa!.
For the OFF condition, the steady-state output
voltage EO is given by
Steady-State Conditions
Ideally, when an MOS transistor in a shunt chopper
circuit is ON, the output voltage of the circuit should
be zero. Because the drain-1o-source resistance rds
is some finite value, however, the output cannot reach
true. zero. Fig:5 shows an equivalent circuit for steady-
Eo
=
Es [
r:r:B::'L]
Rs
+---r dB + RL
27
AN-~52----------------------~---------------------------------In most MOS transistors, both rds(OFF) and Ra are much
greater than RL. Therefore, Eq. (4) may be simplified
as follows:
4. The' performance of the series-shunt circuit is
equal to or better than that of either the series
or the shunt chopper alone fot any combination
ofRsand RL.
'
(5)
Approximate Output Voltage Eo"
(Max. Output
If RS, RL, and ES are assumed to have the values used
previously, the gate-to-source voltage Vas is assumed
to be -10 volts, and the gate resistance Ra is assumed
to be 10 12 ohms (minimum permissible gate resistance
for the 40460), the value of EO is calculated ss follows:
EO =
10-3~ :~~5J -10 [:o~: J
10-3
2
-10- 6 ~ 0.5 millivolt
Source
Load
Shunt
Resistance Resistance :Chopper
RS
(ohms)
(ohms)
1M
100 K
100
0
1M
1M
100 K
100
1M
1M
1M
1M
lOOK
100
100 K
100
=I
Series
Chopper
J.L V
mY)
Serie~Shunt
Chopper
(ON) (OFF) (ON) (OFF) (ON)
(OFF)
0.1
1
500
1000
0.1
0.05
0.0001
0.0001
0.0001
0.0001
0.0001
0.00005
0.0001
0.00005
500
900
1000
1000
90
0.1
500
333 500
500
900
1000
1000
90 0.1
0.1 0.0001
500 0.1
333 0.0001
500
900
1000
1000
90
0.1
500
333
Table /I - Steady-state chopper output voltage lor
various source and load res ;stances.
The second'term in Eq.(5) is the error term for the
OFF condition; it is not proportional to the input signal
Eg. For the numbers used, the output ernr in the OFF Transient Conditions
condition is only 0.2 per cent. If a typical value of
Fig.6 shows the ac equivalent circuit of an MaS
1014 ohms is used for the 40460 gate res,istance instead shunt chopper. The interelectrode capacitances of the
of the minimum value of 10 12 ohms, the error voltage is MaS transistor affect operation of the circuit at high
reduced to only'().002 per cent. The output error remains frequencies. The input capacitance Cgs increases the
small for any value' of signal voltage ES that does not rise time of the gate driving signal and thus increases
approach the error voltage in magnitnde.
the switching time of the chopper. This effect is not
Because the error voltage is inversely proportional usually a serious limitation, however, because the
'to the gate leakage resistance Ra, most junction gate
field-effect transistors produce larger, error voltages
r-----------------~------~~O~PUT
than MaS transistors (the minimum Ra of most junctionC d
gate devices is only 1 to 10 per cent that of MaS transistors).
YG•o-.....r-"''''R'''.---;
RS
A similar procedUre may be used for analysis of
series chopper and series-shunt chopper circuits.
The operation of all MaS chopper circuits is greatly
affected by the magnitude of the source and load resistances. Table II lists the output voltages of the
thr ee basic chopper circuits for various combinations
of source and load resistances. It is assumed that the
input voltage ES is 1 millivolt, and that the drain-tosource resistance rds is 100 ohms in the ON condition
and 1000 megohms in the OFF position. The gate leaKage resistance Ra 0012 ohms or more) is neglected.
Tbe following conclusions can be drawn from the data
shown:
1. Only the series or the series-shunt circuit should
be used when RS < rds(oN).
2. In general, RL should be high. (RL > > rds(ON)
3. The load resistance should be higher than th",
source resistance. (RL
28
~
RS)
Flg.6 - AC equivalent circuit 01 MOS shunt chopper.
switching time of the MOS transistor depends primarily
on the input and output time constants. Switching times
as short as 10 nanoseconds can lie achieved when an
MOS i.rWlt~iMLul" is di'iven from a low-impedance gene:aw&'
and the load resistance is less than about 2000 ohms.
The output capacitance Cds also tends to limit
the maximum frequency that can be chopped. When tbe
reactance of this capacitance becomes much lower than
the load resistance RL, the chopper becomes ineffective
becaUse XCds is essentially in parallel with RL and
rds(oFF).
-----------------------------AN-3452
The feedthrough capacitance Cgd is the most important of the three interelectrode capacitances because
it couples a portion of the gate drive signal into the
load circuit and causes a voltage spike to appear across
RL each time the gate drive signal changes state. Cgd
and RL form a differentiating network which allows the
leading edge of the gate drive signal to pass through.
The output capacitance Cds is beneficial to the extent
that it helps reduce the amplitude of the feed through
spike.
The effect of the feedthrough spikes can be reduced
by several methods_ Typical approaches include the
following:
(a) use of a clipping network on the output when
the input signal to he chopped is fixed in amplitude.
(b) use of a low chopping frequency.
(c) use of an MOS transistor that has a low feedthrough capacitance Cgd (some RCA MOS transistors
have typical Cgd values as low as 0.13 picofarad).
(d) use of a gate drive signal that has poor rise
"
and fall times.
(e) use of a source and load resistance as low as
feasible.
(f)
use of a shield between the gate and drain leads.
(g) use of a series-shunt chopper circuit.
Temperature Variations
The variation of MOS transistor parameters with
temperature can affect the operation of a chopper circuit
unless allowance is made for such variations in the
circuit design. It is important. therefore. to determine
the approximate degree to which" each parameter can be
expected to chauge with temperature. Fig.7 shows
curves of channel resistance rds. gate leakage current
SUBSTRATE CONNECTED TO SOURCE
VOS-Oi VGs=O. '~I.Hz
100
!/
I
.
..
::i
......
.'"
u
z
,/
300
/
t;
200
/
z
z
i..-
II
V
V
/
r;::o
:::10.0
..
E
100
/
~
u
o
-80
..
.......
....."
g;
IZ
-40
(a)
40
80
120
AMBIENT TEMPERATURE _·C
160
II
0:
II!
:>
u
SUBSTRATE CONNECTED TO SOURCE
VGs·+IO,,; VDS·O
/
V
-'
u
.
1.0
/
o
on
I
o
';"
z
4
/
100
dB
(with 0.2 volt at antenna terminals) •••••••
• Relative to 2 uV.
Table I - Over-all Tuner Perlormonce
The rf
the if strip
more fully
. transistors
section of the tuner is shown in Fig.1, and
in Fig.2. The if strip, which is described
elsewhere, 4 utilizes three 40482 bipolar
that operate at collector currents of 3.5
6-67
32
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ AN·3453
"3
to
",
p
"4
C'O
/
"s -q
CII
/
el2
/
/
/
/
/
~----~------~--------~----~--~~------/~-------------.-'sv
C"
/
"7
/
/
L3
"8
/
/
/
/
C,O
C'7
C'8
"0
All
C,s
Rl
R2
R3.R 4
RS
R6
R7
RS
L,
= 100 K\1
=220 K\1
=47 K\1
=4.7K\1
= S.2 K\1
=120K\1
=22 K\1
rosistors
112
w.
C 1,CS,C 16 = 16 pF
C2,C7 =2-12 pF, Trimmer
C3,C 6 = 0.002 /LF
C4,C 5,C'8 = 5.5-22.5 pF, ganged tuning capacitor
C 9 = 5000 pF
C lO =2.7 pF
C ll = 0.01 /LF
C12,C14,C1S = 1000 pF
C 13 = 1000 pF feed through type
e'7 =2-10 pF, Trimmer
#18 bore copper wire, 4 turns, 1/4" 1.0.,7/16" winding length, 0 0 at 100 MHz = 130.
Tunes with 34 pF capacitance at 100 MHz.
Antenna Link approximately 1 turn from ground end.
Gate Tap approximately 1-1/2 turns from ground end.
L2"= #18 bore copper wire, 4 turns, 1/4" 1.0.,7/16" winding length, 0 0 at 100 MHz = 120.
Tunes with 34 pF capacitance ot 100 MHz.
Bose Tap approximately 3/4-turn.
L3 = #18 bare copper wire, 4 turns, 7/32" 1.0.,7/16" winding length, 0 0 at 100 MHz =120.
Tunes with 34 pF capacitance at 100 MHz.
Emitter Tap approximately 1-1/2 turns from ground end.
Base Top approximately 2 turns from ground end.
Fig.! • Typical FM receiver 'ront end using RCA-40468 MOS field.effect transistor.
milliamperes in neutralized configurations and provide
an ovel'-all if gain of 94 dB.
The rf section provides a total gain of 34.5 dB,
which includes 12.7 dB in the rf stage and 218 dB in
the mixer. The mixer and oscillator were designed
according to principles established previously,5.6 and
details of their desigu are not discussed. The commoncollector oscillator provides an extremely clean oscillator waveform. In addition, the low injection level at
the mixer base, 25 to 30 millivolts, coupled with the
design of the preceding circuits, limits the maximum
possible signal at the mixer base and minimizes the
generation of spurious responses in that stage.
33
AN-~53--------------------------------------------------------
__
C,
T,
Q.68,F
I
0,
I
RIO
'000
~~+-"-1.:-O-'--HH
".
R"
UK
+---+-If---'
Rll
8.2K
°THE IN542 DIODES ARE A
MATCHED PAIR
All resistors 1/4 watt
0.01. and O.OS.. ,uF capacitors, SO.. V ceramic disks
330.. pF capacitors, l-kV disks
Fig.2 - Typical if-amplilier strip.
RF-Stage Design
The 40468 rf stage is designed to achieve the
published maximum usable stable gain of 14 dB at a
nominal operating point of 5 milliamperes. Additional
losses of 1.3 dB reduce the actual gain in the tuner to
12.7 dB. Details of the rf-stage design are given in
the Appendix.
Selection of the appropriate source and load impedances for the rf stage is based on the fact that a
low spurious response requires the gate of the 40468 to
be tapped as far down on the antenna coil as gain and
noise considerations permit. This arrangement applies
the smallest possible voltage swing to the gate and
makes optimum use of the available dynamic range.
(In a bipolar tuner designed to optimize the rejection
of spurious responses, the tap point on the antenna
coil was approximately 25 ohms.)
For low spurious response, therefore, the entire
rf coil is used as the load for the 40468. The inter stage
coil presents a load impedance to the rf stage of 3800
ohms, which nearly matches the 4200-ohm output impedance of the 40468. Although this arrangement loads
the inter stage coil and causes a degradation of selectivity of the front end, it is an acceptable compromise in
this case because the antenna coil is not loaded by the
gate of the MOS transistor.
As indicated by the calculations in the Appendix.
this approach yields a source impedance of approximately 200 ohms for the 45OO-ohm input impedance of
the gate of the 40468.
Tuner Performance
Performance of the tuner with respect to sensitivity
limiting, if rejection, and image rejection compares
favorably with that of tuners using high-performance
bipolar transistors. Figs.3, 4, and 5 show typical performance characteristics of the receiver. Receiver performance, particularly as regards spurious-responserejection figures, is highly dependent on such factors
as physical layout, power-supply decoupling, and care
in construction. The use of a negative supply voltage
facilitates the grounding of tuned circuits and the decoupling of the supply.
i
~'
~
I
I
~-dB
I
!
88
--
LIMITING
20 -dB QUIETING
1
a
I
3D-dB QUIETING
I
92
I
96
I
i
I
I
100
104
108
MODULATED INPUT SIGNAL-MHz
Fig.3 .. Sensitivity curves lor FM receiver
using circuits 01 Figs.! and 2.
The elimination of spurious response was the primary goal in this design. Generally, a circuit that has
a low spurious response is difficult to reproduce.
In
some systems, the performance of such a circuit depends
on the exact operating points of the transistors used;
when the rf-amplifier transistor in Fig.1 was repeatedly
changed, performance of the tuner remained essentially
the same. The best correlation was found with the
operating current of the transistor in the circuit. Fig.6
shows the change in the rejection of the "half-if'
spurious response as a function of drain current for a
-----------------------------AN-3453
-\0
V
-20
\
-30
-40
'-RELATIVE RESPONSE
I
I
CARRIER FREQUENCY;IOO MHz
MOOUL.AT10N~400
\
OEVIATIOi-22.5 kHz
I
I
\
-'0
Hz
-60
..c::...SIGNAL-TO~NOISE
to
\
10 2
I
RATIO
10 3
10·
SIGNAL VOL.TAGE AT ANTENNA-,..V
Fig.4 - Relatiye response as a function of signal yo/tage measured at antenna terminals.
T
0
0
0
-
60aa
IF
~-IF"REJECTION
1--1-- .
.lECTL
IMTE REfcT,or
90
~
~
~
~
=- -
DESIRED SIGNAL FREQUENCY-MHz
--
~
96
.l
94
92
90
"'"
:--r-
r--.._I
!
,
I
I
1--""" r--- r--
I
DRAIN CURRENT-mA
Fig.6 - Half-if rejection as a function
of operating point.
[
!
-
fffill 114
123456
910
DRAIN CURRENT-mA
Fig.7 - 20-dB quieting sensitiyity as a function
of operating paint.
~
Fig.5 .. Spurious-response rejection as a lunction
of frequency.
9a
typical 40468. For the normal spread of operating current in this circuit of 3.5 to 7 milliamperes, the variation in rejection is shown to be about ± 1 dB.
Fig.7 shows the variation of 20-dB quieting sensitivity as a function of drain current, aud indicates why
the 5-milliampere nominal operating point was chosen.
Below 3 milliamperes, the sensitivity of the receiver
degrades very rspidly. However, at 5 milliamperes the
actual spread of 3.5 to 7 milliamperes causes a negligible change in performance.
\0
Conclusions
The 40468 MOS field-effect transistor has been
incorporated into an FM tuner in which all other stages
are high-performance, low-capacitance bipolar types.
The wider dynamic range of the MOS transistor provides
significant improvements in the rej ection of spurious
responses over results previously achieved with bipolar
rf amplifiers.
Most significantly, the performance with respect
to spurious-response rejection has been repe ated when
devices with wide parameter variations have been used.
Furthermore, the system hss been duplicated with
comparable results. These two factors strongly indicate
that the performance advantages are real and are attributable to the characteristics of the MOS rf amplifier used
ratherthan theresult of cancellation or peculiar trapping
in a single tuner.
35
AN-~~~-------------------------------------------------------Appendix - Design of 40468 RF-Amplifier Stage
The following parameters are important in the design of the rf-amplifier stage:
40468 parameters (atVDD = 15 V, ID =5 rnA):
input resistance Rin . . . . • . .• 4500 ohms
output resistance Rout. . . • . .. 4200 ohnis
forward transmittance Yfs . . . .. 7500 /lmhos
feedback capacitance Crss (max). 0.2
pF
mixer-stage parameters:
input resistance Rin(mix) . . . .. 550 ohms
input stability IS(mix)
(from previous design) . . . . . .
4
coil data:
mounted unloaded Q. • . . • • . •. 120
tuning capacitance CT
at 100 MHz . . . . . . . . . . . . .
34
pF
antenna impeda~1Ce . . . . . . . .. 300 ohms
Fig.8 shows the ac equivalent circuit for the rf
stage. At resonll!'ce, this circuit reduces to the form
N,
where a is a skew factor smaller than unity which
is used to maintain bandwidth, and b is a number
equal to or greater than unity related to the number of
stages (inserted to maintain bandwidth in multistage
amplifiers). A skew factor of 0.2 is generally used.
Because only one stage of 100-MHz gain is used in the
amplifier shom in Fig.l, b = 1. For the values given,
therefore, MUG is given by
MUG = 0.4 Yfs = 23.5 = 13.7 dB
wCrss
(3)
The total mismatch loss is called the stability factor S,
and is equal to the difference (in dB) between MAG and
MUG, as follows:
S = MAG - MUG
=10.5 dB, or 11.3 times
(4)
This value is arbitrarily divided between the input and
output circuits by use of an input stability IS and an
output stability OS, as follows:
IS" Rin/2Rl
(5)
OS = Rout/2R2
(6)
where Rl and R2 are the total parallel impedances at
the input terminal (gate) and the output terminal (drain),
respectively. These stability terms are related to the
stability factor S as follows:
Fig.8 - AC equivalent circuit of the 40468 rf stage.
shown in Fig.9, where all impedances are referred to
the gate ami drain terminals of the 40468. The maximum
available gain (MAG> is the gain in a coniugately
matched, unilateralized circuit and is defined as follows:
IYfsl 2 Rin Rout
MAG =
4
(1)
For the ,values given above, MAG = 266 = 24.2 dB.
S =ISxOS
(7)
The division between IS and OS is made by means
of some arbitrary choices. As mentioned previously,
it was decided to maximize IS so that the signal level
at the gate would be minimized. This choice necessitates matching or nearly matching Rout to its load.
Therefore, the entire rf coil is used as the output load.
As indicated in Eq.(6), the value of R2 must be
determined to define OS; the value of IS can then be
determined and the input circuit defined. R2 consists
of the parallel combination of Rout, RT2, and (N IIN2)2 x
Rin(mix), where RT2 is the tuned impedance of the rf
coil and is given by
(8)
Fig.9 - Equivalent input (R7i ancl output (R2i circuit
of the ,f stage eluring resonance.
The maximum usable gain MUG is the stable gain
which may be realized in a practical neutralized or unneutralized circuit. It is defined by the relationship
for the unneutralized case as follows:
2 IYfsl a
MUG = - - - x (2)
wCrss b
36
The value of Rout is given above as 4IDO ohms. The
value of RT2 as calculated from Eq.(8) is 5600 ohms.
The value of the input impedance of the mixer Rin(mix).
obtained from the published data for the 40479, is 550
ohms. The only remaining component of R2 to be determined is the turns ratio NIIN2In Fig.8, the rf coil L2 represents both the input
circuit of the mixer and the output circuit of the rf
stage. Therefore, the stability of the mixer stage must
also be considered. Because stability factors are
equal to resistance ratios, the input stability of the
-----------------------------AN-3453
mixer can be considered at the top of the rf coil, as
follows:
(9)
The value of IS(mix) was' specified above as 4 (from a
previous design). Because R2 is a linear function of
(NIIN2)2 Rin(mix), manipulation of the data through
several steps provides a value of 5.5 for (NI/N2) and
a reflected value of 16,800 ohms for Rin(mix).
The output stability of the rf stage can then be
determined. R2 is computed as the parallel combination
of Rout, RT2, and (NlIN2)2 Rin(mix), and is found to
be 2100 ohms. The output stability OS is determined
from Eq'(6), as follows:
OS
=Rout/2R2 =4200/(2 x 2100) =1
(NalN2)2 RANT is 382 ohms, which is a very slight step
up. Because two of the three component terms of R 1 are
then known, the remaining term (N3/N1)2 RTI can be
determined as 456 ohms. The turns ratios are then
given by
NIIN2 = 4.3
NIIN3 = 3.7
The values of circuit components obtained by means
of this design method are given in the parts list for
Fig.!.
References
1. F. M. Carlson and E. F. McKeon, "Small Signal RF
Amplification of MOS Devices," Proceedings of the
1966 National Electronics Conference.
The value of unity indicates an impedance match between Rout and the load.
2. F. M. Carlson, "Application Considerations for the
RCA-3NI28 VHF MOS Field-Effect Transistor,"
RCA Application Note AN-3193, August 1966.
The input stabilily of the rf amplifier can then be
determined from Eq.(7), as follows:
3. D. L. Leonard, "Improve FM Performance with FETS,"
Electronic Design, Vol. 15 No.5, March 1967.
IS
= S/OS = 11.3
By use of this stabilily term, the input-circuit constants
can be calculated. Rl is determined from Eq.(5), as
follows:
Rl = Rin/2IS = 191 ohms
This value is so much lower than Rin that it is apparent
the MOS trsnsistoc does not load the antenna coil at all.
Because it is desired to match the anteJUla with
the input circuit, the value of R1 should be one-half the
reflected sntenna impedance.
Therefore, the value of
4. R. T. Peterson, "High-Quality FM and AMlFM Tuners
Using New Silicon Transistors," RCA Application
Note AN-3466, June 1967.
5. R. V. Fournier, C. H. Lee, and R. T. Peterson,
''Performance Analysis of 3- and 4-Coil FM Tuners
Using RCA High-Frequency Trsnsistors," IEEE
Transactions on Broadcast and TV Receivers,
November 1965.
6. R. V. Fournier, C. H. Lee, snd J. A. Kuklis, "A
Goal: Spurious-Signal Immunily of Solid-State AMlFM
Tuners," IEEE Transactions on Broadcast and TV
Receivers, April 1966.
37
OO(]5LJD
MOS Field· Effect Transistors
Solid State
Division
Application Note
AN-3535
An FM Tuner Using
Single-Gate MOS Field-Effect Transistors
as RF Amplifier and Mixer
by
C.H. Lee and S. Reich
Selection of the transistors for use in FM-tuner
stages involves consideration of such device characteristics as spurious l'esponse 1 , dynamic range, noise
immunity, gain, and feedthrough capacitance.
MOS
field-effect transistors are especially suitable for use
in FM rf-amplifier' and mixer stages because of their
inherent superiority for spurious-response rejection and
signal-handling capability. This Note describes an FM
tuner that uses an RCA-40468 MOS transistor as the rf
amplifier and an RCA-40559 MOStransistor as the mixer.
A conversion gain of 17.5 dB was obtained, to provide
an over-all tuner gain of approximately 30 dB. RF and
mixer circuit considerations pertinent to the design are
discussed.
Performance Features of MOS Transistors
the transistor; and a, f3, and
e are the coefficients of a
Taylor series expansion. These coefficients are related
to the first-, second-, and third-order derivatives of the
transfer characteristic as determined by the 'bias point.
It can be shown2 ,3 that mixing action within the device
is attributable to the second-order term (j3es 2), and that
cross-modulation and intermodulation result from thirdand higher-order terms. Therefore, when a device has
an inherent square-law transfer characteristic, i.e., the
drain current varies as the square of the applied gateto source voltage, third- and higher-order terms are
zero and spurious response is eliminated. The transfer
characteristic of MOS field-effect transistors more nearly
approaches this ideal square-law relationship than the
very steep exponential transfer characteristic of bipolar trans istors.
Spurious response in an FM tuner is caused by the
mixture of unwanted signals with the desired carrier in
either the rf stage or the mixer. This effect can be
expressed mathematically by use of the Taylor series
expansion of the simple transfer function of output current as a function of input voltage at the operating point,
as follows:
The dynamic-range capability of MOS field-effect
transistors is about 25 times greater than that of bipolar
transistors. In an actual tuner circuit, this large intrinsic dynamic range is reduced by a factor proportional
io • 10 + ae s + f3e s 2 + ees 3 +. • •
WithMOS field-effect transistors, as contrasted with
either bipolar transistors or junction-gate field-effect
transistors, there is no loading of the input signal, nor
drastic change of input capacitance even under extreme
overdrive conditions.
(1)
wbere io is the instantaneous value of output current of
the device; 10 is the dc component of output current; es
is the rf signal voltage present at the input terminal of
38
to the square of the circuit source impedances. 4
1 ne
net result is a practical dynamic range for MOS tuner
circuits about five times that for bipolar types.
12-67
-------------------------------AN-3535
In junction-gate field-effect transistors, a large incoming signal can have sufficiently high positive swing
12.7 dB. The mixer transistor RCA-40559 also operates
in the common-source configuration, with both the rf and
local-oscillator signals applied to the gate terminal.
The bipolar oscillator transistor RCA-40244 operates in
the common-collector mode. The conversion power gain
from the mixer stage is 17.5 dB; the total gain of the
tuner is 30_2 dB.
to drive the gate into conduction by a momentary for-
ward bias; power is then drawn from the input signal in
the same way as
if a resistance were placed across the
input circuit. In bipolar transistors, there is a gradual
change of both input impedance and input capacitance
as a function of large signal excursions. These changes
are undesirable because they can result in detuDing of
tuned circuits and widening of the input selectivity curve.
Performance of the FM tuner was evaluated by use
of the bipolar-transistor if amplifier shown in Fig.2.
The 10.7-MHz if output from the tuner is coupled to the
first if-amplifier stage by means of a double-tuned transformer T 1. The if amplifier employs two 40245 and one
40246 bipolar transistors, each operating in a neutralized
common-emitter configuration at a collector current of
3.5 milliamperes. The over-all gain of the if amplifier
is 88 dB. A detailed analysis of a similar if amplifier
is covered in an earlier publication. S
FM Tuner Design
The FM tuner shown in Fig.1 uses single-gate MOS
field-effect transistors in the rf-amplifier and mixer
stages and a bipolar tr ansistor as the local oscillator_
The rf-amplifier transistor RCA-40468 operates in the
common-source configuration with a stage gain of
Cia' Clb, Clc RF AMP.
~!t;1 wti~~irr~m~:~c~:~rppe~R~f.s-Plate Model
e2 1 C3, C4 - Areo 402 trimmer I maximum value 10 pF
LI -
rJ2!,S ~r:~ ~~~~~5(i!~ ~2~~'~~~;0}J~~~~.fO~r; ~~iuen~~~
tenna tap at 0.8 of a turn, output tap at 1.4 turns.
L2 - No.IS bare copper wire, 5 turns on 15/64" form, coil length
3/S", with O.ISI" x 0.375" Arnold slug. Qo = 104.
L3 -
~gill~e~:;~ ~/~p'.er l~\fierS t~~n~~ f~u~r~u:-:,i~~ 3/:;d~~k
tap on 2 turns. Q = 164.
-+-"T-=~---t"""'-+IBV
T1 -
~~~~I: ~~~~~'p~~!Q ~el~7f:{ti~i6:~PF~~~ii~~· c~~ia~i~~n~~-,
secondary unloaded uncoupled Q = 76 with 47-pF tuning
capacitance. Secondary has a turns ratio of 26.2 to 1.0.
Primary. No.32 enamel wile, 15 turns, space wound at 60
TPI, 0.250" x 0.500" TH slug. Secondary, No.36 enamel
All resistors in ohms,
wire,IS turns, close wound, 0.250" x 0.250" TH slug. Both
unless specified otherwise
coils on 9/32" form without shield.
Fig.! - Circuit diagram of FM tuner using MOS transistors for the rf amplifier
and mixer stages.
IK
.. 8
K
6.8
K
.. IOmF
6V
1.5K
OD2
All resistors in ohms,
unless specified otherwise
l"F
AUDIO OUT
Fig.2 - Three-stage if amplifier using bipolar transistors.
39
AN-3535---------------------------------------------------------Table
summarizes the performance of the MOS
tuner. Spurious response was evaluated with a generator
output of 350 millivolts_"
also makes it unnecessary to add neutralization com ..
ponents to the rf stage to achieve adequate gain.
Mixer-Circuit Considerations
OVER-ALL TUNER PERFORMANCE
Carrier Frequency .. . . . . . . . . . . . .
Modulation Frequency ..•••••••••
Deviation (except IHFM) . . . . . . . • .
100
400
22.5
MHz
Hz
kHz
1.75
1.5
1.75
2.5
62
96
92
/-LV
/-LV
/-LV
/-LV
dB
dB
dB
Sensitivity:
IHFM ••.•• , ....•.•••..•••
20-dB Quieting •••.••••.. ' •...
30-"
resented by the signal-limiting ~iodes. The ideal
signal-limiting diodes, with an infinite transfer slope
IRs =0), ,,!ould then limit the voltage presented to the
gates to ItS knee value, ed' The.difference voltage.
E - Bd = e s (where E is the static potential in the static
generator, ed is the diode voltage drop, and e s is the
voltage drop across the generator intemal resistance)
appears as an IR drop across Rs ' the internal impedance
of the generator. The instantaneous value of the diode
current is then equal to es/Rs. During handling the
practical range of this discharge varies from se~eral
milliamperes to several hundred milliwnperes.
Gate·Protection Methods
It has been established above that in terms of a
static discharge potential it is reasonable to represent
the MpS tran.sist~r as. a capacitor, s~ch I!s CJN in Fig.4.
The Ideal SItuatIOn 10 gate protectIon IS to provide a
signal-limiting confignration that allows for a signal
such as that shown in Fig. 4 (a) to be handled without
clipping or distortion. The signal-limiting devices
should limit all transient responses that exceed the
gate. breakdown voltage,. as shown in Fig. 4 (b). One
pos~lble .means of se~urlOg proper limiting is to place
a dIode 10 parallel WIth CrN, as shown in Fig. 4 (c).
Unfortanately, this arrangement causes several, undesirable consequences. In terms of signal ,handling,
the single diode clips the positive peaks of a sine wave
such as that in Fig. 3 (a) when the transistor is operated
in th!, vicinity of zero bi.as. The 3Nl40 dual-gate MOS
tran~lstor, for ~xwnple, IS frequently operated with the
rf SIgnal superImposed on a slightly\ positive "bias"
potential on. gate !'I0' 1. Furthermore, gate No. 2 of
the ~Nl40 IS deslgne.d to handle large positive and
n!lgati ve dc voltage SWIngs from the agc loop. A singlediode arrangement would render this device useless
for this type of circuit. It is important, therefore that
the limiting device be an effective open circ~it to
any incoming signals tbrough the amplitude range of
such signals. The best available method for accom-
1-+ 10
I.'
101
Fig. 5· Transler characteristic 01 protective diodes (a),and
resulting wave/orms in equivalent circuit (b).
45
AN-4018 - - - - - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ __
Electrical Requirements
The previous discussion points out that optimum
protection is afforded to the gate with a signal-limiting
diode that exhibits zero resistance protected MOS uansistor is compared to a high-frequency bipolar device. A laboratory experiment in which a
static charge was accumulated in a capacitor and diecharged through a circuit configuration like the one
shown in Fig. 3 demonsuated that the special siguallimiting diodes made the protected-gate MOS fieldeffect transistor less vulnerable to static discharge
damage than the bipolar uansistor by a factor greater
than two.
Power Gain and Noise Factor
In the final analysis, the question that must be answered is how the addition of the protective siguallimiting diodes affects circuit power gain and noise
factor. Performance data taken on the ten units described above in the typical rf test circuit shown in
Fig. 11 are given in Table 1. Noise-factor values show
an average degradation of 0.25 dB when the diodes are
connected. The power-gain values show that the change
in this characteristic is insignificant.
Table 1- Power Gain and Noise Factor at 200 MHz.
HYBRID
UNIT
1
2
3
4
5
6
7
8
9
10
POWER GAIN
(dB)
DIODES
DIODES
REMOVED
IN
16.4
16.3
18.8
18.5
16.2
16.5
15.7
16.3
17.8
17.7
17.2
17.5
17.0
17.1
18.0
17.9
18.5
18.5
17.3
17.3
NOISE FACTOR
(dB)
DIODES
DIODES
REMOVED
IN
3.7
3.4
2.2
2.4
3.0
3.3
3.9
3.4
2.6
2.4
2.8
2.5
3.3
3.2
2.9
2.6
2.4
2.3
3.0
3.2
47
AN-4018--------------~--------------------------------~----~---
r-----------"'T----------C';'.--'OUTPUT
\
I
\._01
I
I
I
I
I
I
I
I
I
'NPUT :rSOLOj,I-"_-'_N'+_,
C,
I
C3
: RI
,
I
l-c2
LwHifE~
'
l
lelO
C8
=---GREEN ~-----~u£J~---~
"3
01: 100 pico'arads. ceramic disc
C2 C7 C8 C9 ClO' 1000 picofarads, feed-through type
03: 1 to 10 picofarade, variable air (piston);
JFD VAM-Ol0, Johnson Co. No. 4335,' or equivalent
04: 1.8 to 8.7 picofarads, variable airi
Johnson Co. No. 160-104 or equivalent
OS: 3 picofarads, tubular ceramic
06: 22 picofarads, ceramic disc
Cn' 1.5 to 5 picofarad., variable air;
Johnson Co. No. 160-102 or equivalent
012: 100 picofarads, ceramic disc
CIS! 1.5 picofarads, tubular ceramic
014: 0.8 to 4.5 picofarads, variable air (piston);
Erie 560-013 or equivalent
SmA
Ferrite 4 beads on No. 24 wire between Ll and socket; beads
beads: are Pyroferrio Co. "Carbonyl JU or equivalent:
0.093-inch OD, O.03-inch!D, 0.063 inch thick
L 1: 4 turns O.020-inch copper ribbon, silver-plated, 0.075 to
0.085 inch wide, O.25-incb inside diameter, coil
approximately 0.80 inch long
L2: 4.5 turns 0.020-inch copper ribbon, silver-plated, 0.085 to
0.095 inch wide, 0.3125--inch inside diameter, coil approximately 0.90 inch long
R3: 36,000 ohms
Ql' MOS transistor under test
R4 , 1800 ohms
RFC: Ohmite part No. Z235
or equivalent
RS: 275 ohms, 1h watt, 1%
R 1, 27,000 ohms
Ra: 120.000 ohms
~: 1000 ohms
R2' 47,000 ohms
Fig.l1.RF testcircuitlorrlua/.gate MOS transistors.
Conclusions
Gate-protected dual-gate MOS field-effect transistors
such as the RCA-40673 make available to the circuit
designer a device capable of good rf performance without the hazards previously associated with the handling
and installation of MOS devices. Moreover, the gate
protection is provided by signal-limiting diodes that do
not significantly compromise dynamic range, noise factor, or power gain.
Acknowledgment
The authors thank L. Baar for collecting data and providing l!I!IleralsuDDort for the work described. and C. Tollin
for fabricating-the devices tested.
.
48
References
1.
H.M. Kleinman, "Application of Dual-Gate MOS
Field-Effect Transistors in Practical Radio Receivers", IEEE TRANSACTIONS ON BROADCAST
AND TV RECEIVERS, July 1967.
[Kl(]5LJD
Linear Integrated Circuits
Solid State
Division
Application Note
ICAN-4072
Applications of the RCA CA3048
Integrated-Circuit Amplifier Array
by
L. Kaplan
The RCA CA3048 integrated circuit is an array of
four identical amplifiers, each with independent inputs
and outputs, al1 on a single monolithic silicon chip. The
circuit is housed in a 16-lead dual-in-line plastic package. It has an operating and storage temperature range
of -250 C to +850 C. Each amplifier in the array has a
typical open-loop gain of 58 dB and input impedance
of 90,000 ohms. The noise in the CA3048 is inherently.
very low and is tightly control1ed in rigorous factory and
quality-control testing.
The combination of low noise, high gain, and high
input impedance make, the CA3048 a very versatile unit.
and numerous applications suggest themselves for its
use.
CIRCUIT DESCRIPTION
Fig. 1 sho;'s the complete schematic of the CA3048
integrated-circuit amplifier array. Each amplifier (A1
through A4) provides two stages of voltage gain.
The input stage is basically a differential amplifier
with a Darlington transistor added on the one side. The
output stage consists of ~ combination of three transistors and associated resistors connected in an inverting
configuratioq. For example, in amplifier A3 , Q19 is the
Darlington input transistor, and Q20 and Q21 are the
differential-pair transistors. The load resistor R29 for
the differential input stage is located in the col1ector
lead of transistor Q20· Transistors Q13' Q14' and Q17
are used in the output stage. Transistor Q17 is the actual output transistor; transistors Q13 and Q14 raise
the input impedance of the output stage so that the loading· of the 30,OOQ.ohm source resistance R29 (i.e., load
resistor for the differential-amplifier input stage) is
small. The ratio of total collector resistance to emitter
resistance [(R31 + R38)/R50l in the output stage is
1000/200, or 5. In view of the small source loading, the
stage gain, therefore, is essentially equal to 5.
A feedback network (R41' R4 2' R46 , and 07) is
connected between the output terminal and the base of
transistor Q21. The resistor values are chosen so that
the output transistor is biased at approximately 5 milliamperes for maximum dynamic range. Diode 07 compensates for variations in the .base-to--emitter voltage
of Q21 with changes in temperature. Because the other
transistor (Q20) of the differential amplifier has two
emitter-base junctions in series, two diodes, D3 and D4 ,
are required for temperature compensation.
Diodes D3
and 04 also provide temperature compensation for the
differentiall'air transistor Q1 in amplifier A2 (similarly
diodes 05 and 06 ar.e shared by amplifiers A1 and A4 )·
3·70
49
ICAN-4072
Diodes 03 and 04 and diodes 05 and 0 6 are connected
to their respective inputs through a relatively stiff voltage divider (for amplifier A3' the divider consists of
R27 and R28)' The input to amplifier A3 is normally
applied to the base of the Darlington transistor Q1g.
The 100-kilohm resistor R37 supplies bias current to
this transistor. The voltage drop across resistor R37
is small because of the very small base current of transistor Q19'
Each amplifier of the CA3048 may be viewed as an
ac operational amplifier in which a fixed resistance is
permanently connected between the output aiId the inverting input. The built-in feedback resistor delimits
the characteristics of the CA3048 amplifiers in the following ways:
1.
The impedance as viewed from the noninverting in-
putterminal consists mainly ofthe 100 kilohm inputbias resistance (R13' R1S ' R37, or R3"9)' This resistance is shunted by the input capacitance of approximately 10 picofarads and the additional resisti ve loading presented by the input impedance of the
Fig.
50
Darlington input pairs. When the amplifier is operated under open-loop conditions (inverting input at
ac ground), the total input impedance consists of
gO kilohms in shunt with the input capacitance.
When the built-in feedback loop is allowed to function (by insertion of an unbypassed resistance in
the noninverting input lead), then the loading caused
by the Darlington input pairs is reduced, and the
input resistance rises asymptotically towards 100
kilohms.
2.
The imped ance as viewed from the inverting input
terminal is small (in the order of 40 to 50 ohms.)
3.
When the CA3048 is used in its normal mode of operation, each amplifier in the array may be represented by the equivalent circuit shown in Fig. 2.
(The capacitances shown are the sum of the device
capacitances, socket capacitances, and stray capacitances.) The transconductance Gm, which is
equal to the product of the voltage gain and the
output conductance (10-3mho), is typically 0.8 mho
at midband.
I - Schematic of the CA3048 integrated-circuit
amplifier array.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ICAN-4072
equal to 1/(R I6 + R22)! 1/(RI4 + Rig), 1/(R31 + R38)'
or 1/(R36 + R4 0). The capacitance C4 and the conductance G4 shown in Fig. 2 represent an external damping
network which can be varied or deleted as demanded by
stability or gain-bandwidth requirements.
c.
I
iil
C,
Fig. 2 - Equivalent circuit of a CA3048 amplifier.
GAIN-FREQUENCY RESPONSE
Curves of the transconductance of any amplifier in
the CA3048 array as a function of frequency up to 30
MHz ·show two break points. At frequencies above the
first break point, which occurs at 300 kHz, the transconductance rolls off at a rate of 6 dB per octave to 12
MHz. At frequencies above 12 MHz, the rate of roll-off
increases to 12 dB per octave. At frequencies up to 12
MHz, therefore, the transconductance of any amplifier in
the CA3048 array is expressed by the following equation:
A necessary and sufficient condition for a system
to be stable is that the roots of the characteristic equation of the system have no positive real parts. The
characteristic equation for the circuit of Fig. 2 is obtained by expansion of the circuit detenninant and collection of the coefficients of the complex frequency S.
The equation assumes the following form:
Al + A2S + A3s2 + A4s3 + ASS4 .= 0
(2)
After much tedious algebra, the coefficients are determined as follows:
Al = wo GIG 3 G4
A2 = w o G4 [G 3(C 1 + C2) + Gl(C 2 + C3 ) - ~ G2 ]
o
+ G I G3(C 3w o + G4 )
A3 =
(1)
- "'ogmo
CUa + S
where S is the complex frequency, ~o is the mid-band
transconductance, and "'0 = 211 X 300 x 103.
g
m
{C2C3(GI + G3 + G4 - ~o) + Cl [C3(G3
+ G4 ) + C2G4 ] } + G4 [G 3 (CI +C 2)
Wo
+ GI(C 2 + C3)] + G1G3 C3
A4 = G4 [Cl(C2 + C3) + C2C3] + C3 [Cl(w oC 2
+ G3 ) + C2(G 1 + G3)]
Fig. 3 shows the open-loop transconductance for an
amplifier in the CA3048 array as a function of frequency.
This response indicates potential uses of the CA3048
integrated circuit at frequencies that extend into the
video range.
STABILITY
The equivalent circuit shown in Fig. 2 can be used
to determine the stability of the amplifiers in the CA3048 array under various conditions of loading when undesirable external capacitance is present in the wiring
and socket. With no external generator connected to. the
circuit, the input conductance Gl is equal to 1/1000aO
mho, and the output conductance G3 is equal to 1/1000
mho (for amplifiers AI' A2, A3 , or A4 , respectively, G1
is equal to l/RIS' I/R 13 , I/R37' or l/R29' and G3 is
AS = CIC2C3
(3)
With the aid of a computer, it IS possible to check
very quickly many combinations of circuit values for
stability by solving for the roots of Eq. (2) with different circuit values assigned to the various components.
Although there are many variables involved, it is
possi.ble to state in a general sense the results of several solutions of Eq. 2.
The system cannot oscillate without capacitor C2
to introduce positive feedback. The analysis is reduced,
therefore, to the determination of the maximum value
of C 2 before oscillation occurs. With careful printedcircuit-board layout, the feedback capacitance C 2 is
. small, and the system is usually stable. If a socket is
used the feedback capacitance is greatly increased, and
20
9m AT FREQUENCIES LESS
o THAN 100 kHz· 0·8 MHO
-
a
a
r--.
a
a
-6 a
0.1
...... r--......
I"'--
-
a
-70
I"-
2
.•
""'
.••
FREQUENCY-MHz
10
"'"." •
100
Fig. 3 - Typical gain-frequency response for a CA3048
amplifier.
51
ICAN4072 _________________________________________________________
stabilization of the circuit is generally required.
1.28
As with any two-port .network, any increase in
source or load conductance aids stability. In addition,
analyses of Eq. (2) show that addition of shunt capacitance at the input is a very effective stability technique
when the source impedance is high. Introduction of
negative feedback into the circuit [which is simulated
in .Eq: (2) by a decrease in the value assigned to the
transconductance gm and an increase in the cutoff frequency 1 also improves circuit stability.
0.64
/
V
~
Another stability method, which is effective for any
source impedance or gain value, is the addition of a
damping network such as that formed by capacitance C4
and conductance G4 in Fig. 2. In this method,. the value
of C 4 is chosen so that its reactance is equal to the
parallel combination of R3 and RL at the highest frequency of desired amplification. The value of R4 is
made small so that the gain is reduced at high frequencies and is typically 1/10 or 1/20 the value of the parallel combination of R3 and RL"
The series of curves in Fig. 4 show the results of
the computation for the roots of E q. (2). It should be
noted that the maximum value shown for capacitance C2
is that obtained just before oscillation occurs. Severe
peaking of the response (or ringing) may result before
the listed value of C2 is reached. It is advisable, therefore, to maintain the capacitance of C 2 well below the
indicated value.
12
•
~ 0.32
;'!
<;
1f
a 0.1 6
~
~
.,.
0.0
•
~
ill
~ 0.04
~
v
1/
/
~ 0.04
V
0.02
,.
0..0. I
0.
L2
•
\1
0.32
1f
:l
"
I
~
l!
016
DDO
~
/
(a)
.
~
~ 0,04
~
Q02
0..0. I
100
300
1000
TOTAL INPUT CAPACITANCE-pF
30
-
30110 6
10'
-
3xl0 4
-
10!
31110 5
TOTAL CONDUCTANCE AT INPUT-mhos
Fig. 4 - Stability curves for a CA3048 amplifier: (a) permissible feeelback capacitance as a function of the
total coneluctance at the input; (b) permissible feeelback
capacitance as a function of gain reeluction anel of banelwielth increase; (c) permissible feeelback capacitance
as a function of the total input capacitance.
52
/
V
g
(c)
-
3D
I
Q64
10.
10xi0 6
24
(b)
0.02
0..0. I
I.
GAIN REDUCTION AND BANDWIDTH INCREASE-dB
:i
V
/
V
Ii
/
t
.
I
r
/
0.64
/
~ O.OB
300.0.
_______________________________________________________ ICAN4072
OUTPUT SWING VS. SUPPLY VOLTAGE
Fig. 5 shows the output voltage for anyone of the
CA3048 amplifiers as a function of supply voltage. The
solid lines represent the performance obtained with the
full open-loop gain. The dotted line shows the improvement obtained when 12 dB of negative feedback is added
by inclusion of a ISO-ohm unbypassed resistor in the inverting-input lead. The values obtained for this curve
are those which prevail when the output is loaded only
by the measuring equipment. It should be realized that
any substantial loading will tend to reduce the magnitude of the available output voltage for equivalent distortion figures. For example, an additional 1000-0hm
load exactly balances the internal load resistor, and
would reduce the available output voltage by 50 per
cent.
voltage (Enoise> and current 0noise) for the-CA3048 at
spot frequencies of 10, 100, 1000, 10000, and 100000 Hz.
From these values, the equivalent input noise voltage
for any value of source resistance may be computed by
use of the following equation:
Eequiv = ,j(Enoise)2 + (Inoise Rsource)2
BOO
600
I
~
~
~ 4r-----t------r~r__t--_+~----~t_----~
~
I
400
o
...
~
~ 200
~
~
..-/
3r-----+------r~--_t--t__1--_+--+_-
~
c
o
!1
2i-----t-------tl------h1----++----f-/--
~
~
e
;i
/
>~
...
1r-----t-~f_-r--~_t--~~--~--~~--4
0.5
1.0
1.5
Fig. 5 - Total harmonic distortion of a CA3048 amplilier
as a function of output voltage for different value of dc
supply voltage.
NOISE
Fig. 6 shows output noise obtained when a single
amplifier of the CA3048 is operated at 40 dB gain into
a "c" filter. Table 1 shows typical values of noise
TABLE I
TYPICAL NOISE VOLT AGE AND CURRENT FOR AN
AMPLIFIER IN THE CA3048 ARRAY
Frequency
Enoise
Inoise
(Hz)
(volts)
(omperes)
30.5 x
17 x
8x
6x
4x
10.9
10-9
10-9
10-9
10-9
10
100
1000
/
/
V
10,000
100,000
SOURCE RESISTANCE-OHMS
Fig. 6 • Noise output as a function of source resistance
for a CA3048 amplifier.
CIRCUIT APPLICATIONS
2.0
OUTPUT VOLTAGE- rms VOL.TS
10
100
1000
10000
100000
(4)
Laboratory measurements have shown that the noise
performance of the CA3048 is not significantly affected
by variation of the supply voltage. The values shown in
Fig. 6, therefore, may be used with supply voltages
down to about 2 volts if it is remembered that the openloop gain decreases to about 35 dB at a supply voltage
of 2.5 volts.
7.5 x
4.3 x
1.2 x
0.5 x
0.3 x
10- 12
10- 12
10- 12
10. 12
10- 12
In all the foregoing discussions, a single amplifier
has been described as though it existed alone. The
CA3048, however, consists of four separate amplifiers,
which may be used independently or in combination. A
glance at the complete schematic of the CA3048 reveals
other aspects worthy of consideration.
Two supply-voltage terminals and two ground terminals are indicated. Terminal No. 12 supplies the VCC
voltage to amplifiers A2 and. A3 , and terminal No. 15
supplies the VCC voltage to amplifiers Al and A4 . The
ground return for amplifiers Al and A4 is provided by
terminal No.2; all other ground returns are provided by
terminal No.5.
When two units are cascaded, it is preferred to let
amplifiers A2 and A3 be the input units, and amplifiers
Al and A4 be the output units. This arrangement permits separation of both the VCC and ground lines for lowand high-level signals.
If resistive decoupling is used, amplifiers A2 and
A3 can be operated at lower VCC voltages to effect a
savings in current consumption.
53
ICAN~072
_________________________________________________________
Hartley Oscillator
The Hartley oscillator is easily designed and constructed using the CA3048 amplifier. No feedback capacitor is required, and it is possible to extract "square",
sawtooth, or sinusoidal waveshapes.
In the circuit shown in Fig. 7, the tap on the coil
is located at one-fourth the total turns, capacitors C I
and C2 provide dc bl0
i:
4
~}2-~~-~-:-~==~~~~Q~5-=::L--~
vos,
GATE No.I-TO~SOURCE VOl.TAGE (VGtS)-VOLTS
vG,S
. ON THIS SIDE OF vos,· VG2S
f----HY~1L-/-:.,..f-- LINE GATE No.2 IS POSITIVE
0
WITH RESPECT TO ITS OWN
z
SOURCE.
>
la)
AMBIENT TEMPERATURE (TAI-25-C
DRA1N-TO-SOURCE VOLTS (VgSI-15
~
5
ll,v"
'"ug;
~
0'--
z
0
'(I / ' .-!-
--
"
8"
~
~
~n
GATE No.2-TO-SDURCE VOLTAGE (VG2S)-VOLTS
gate MOS transistor.
V
I-- i-2-
--
I~~E
0"1-_2':---:~..L-+':-2--+.J4L..--.J+6-----.l+6:---+.l'0-:---1+12
Fig. 10. Voltage distributions for the 3N140 dual·
TYPE 3NI40
o
-I
-2
No. 2-TO-SQURC
VOLTS (VG2SI--1
o
GATE No.I-TO-SOURCE VOLTAGE (VGISI-VOLTS
Operating curves for the 3N140 are shown in
Fig. 11. These curves can be used to establish
a quiescent operating condition for the transis·
tor. For example, a typical application may
require the 3N140 to be operated at a drain·tosource voltage V DS of 15 V and a transconduct·
ance gf. of 10.5 mmhos. As shown in Fig. 11(a),
the desired value of gf. can be obtained with a
gate·No. 2·to-source voltage V a•s of +4 V and a
gate-No. 1-to-source voltage Va" of -0.45 V.
From Fig. 11 (b), the drain current compatible
with these gate voltages is 10 mAo
Two biasing arrangements which can be used
to provide these operating conditions for the
3N140 are shown in Fig. 12. For the application
mentioned above, it may be assumed that shunt
resistance for gate No. 1 should be 25,000 n
and the dc potential on gate No.2 should be fixed
ane at rf ground. The remaining parameters for
the biasing circuits can then be obtained from
the curves showing I D as a function of Rs in
Fig. 13, with Rs = 270 n:
Vs = ID Rs = +2.7 V
Va, = Va" + Vs = +2.25 V
Va. = V a• s + VB = +6.7 V
V DD = VDS + Vs = +17.7 V
(21)
(22)
(23)
(24)
Ibi
Fig. 11. Characteristics curves for the 3N 140.
The values of the resistance voltage dividers
required to provide the appropriate gate voltages
are determined in the same manner as shown
previously for single-gate transistors. For the
circuit of Fig. 12(a), R, is 197,000 n, R, is
28,600 n, and R, R, = 11/6.7.
The circuit of Fig. 12(a) is normally used in
rf-mixer applications and in rf-amplifier circuits
which do not use agc. The circuit "of Fig. 12(b)
is recommended for the application of agc voltFIXED SUPPLY
OR
AGC VOLTAGE
R,
la)
Ib'
Fig. 12. Typical biasing circuits for the 3N140.
61
AN-4125 ________________________________________________________
5
TYPE 3N140
l!
; ~~ /
'\los0r-v".o+I5Y- 1--8
5
" .. OIOIS
Ot----
•
I~ ~J'"
1//
..0
'//
0
5
//§ 1
1/
}
V
4'
~ -y ~
[-
V
~
rP
I
the use of source resistance Rs; variations in
drain current are reduced significantly by use
of an Rs value of 1000 n.
Variations in transconductance can be virtually eliminated by application of a gain-control
voltage from a temperature-dependent voltagedivider network to gate No.2. For example, the
values of the resistance voltage dividers in the
"C
I
ance as a function of temperature. These curves
also show the compensating effects produced by
12
14
DRAIN CURRENT (IDI- MlLLlAMPERES
I. I.
Fig. 13. Draln-current curves for various values of
R. for the 3N140.
age to rf-amplifier stages. In this circuit, the rf
signal is applied to gate No.1, and the agc voltage to gate No.2.
The dual-gate MOS transistor is useful in
agc-supplied rf amplifiers because almost no agc
power is required by the device as a result of
the high dc input resistance indigenous to the
MOS transistor. Another advantage provided by
the MOS transistor is revealed by the ease with
which it obtains delayed· agc action and good
cross-modulation characteristics as a function
of agc. The applieation of agc bias to gate No. 2
while the bias on gate No, 1 is changed improves
the cross-modulation characteristics of the transistor as a function of agc applied.
81aslng fa compensate for temperature varla"ons
Unlike bipolar transistors, MOS transistors
exhibit a negative temperature coefficient for
typical values of drain current. That is, drain
current and dissipation decrease as temperature
increases, and there is no possibility of I D
runaway with elevated temperature. Unfortunately, transconductance and rf power gain also
decrease as temperature increases. Figure 14
shows curves of drain current and transconduct-
circuit of Fig. 12(a) were determined to provide
a transconductance of 9.5 mmhos at ambient
temperature, and the device temperature was
then varied through the range of -45 to
+ 100·C. The values of gate~No. 2-ro-source
voltage V G'8 required to maintain a constant
transconductance over the entire temperature
range, for Rs values of zero and 1000 n are
shown in Fig. 15.
VDS ·+I5V
9,.-g.!immhol
'-lkHI
--
Rs IN OHMS
?
~~
~
r"s°0
~
~r::\~
V
,.,
r - I--+20
/
RS-IOOO
RS·'OOO
-20
/
+40
RS;O- I--+60
+ 80
+ 100
TEMPERATURE--C
Fig. 15. Drain current and gate-No. 2·to·source volt·
age for constant ID as a function of temperature for
the circuit of Fig. 14 (b).
In a practical circuit, the required voltages
can be applied to gate No. 2 if R" or the combination of R 1 and R s , is a temperature-sensitive
resistor that is thermally linked to the MOS
transistor package. This thermistor network can
be designed to provide a desired voltage characteristic at gate No. 2 either to keep the transconductance constant or to permit some variation "'''!ith temperat!!!"e tl) cl)mpensat.e fl)!"
changes in other stages. The effects of temperature given in percentages on these other stages
may be summarized as follows: R,.-one ·percent; Ci,,-one percent; C/eedback-one percent;
Rout-plus 45 percent; Cou,-one percent.
TEMPERATURE _·c
Fig. 14. Drain current and transconductance as a
function. of temperature for the 3Nl40.
62
The data was measured on a 3N140 MOS transistor in the circuit of Fig. 12(a). Drain current was 8 mA, frequency was .200 MHz, and the
temperature varied from 0 to 100·C.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ AN-4125
su.....my
..
All field-effect transistors may be biased similarly. Uniform quiescent operating points can be
easily aebieved in MOB field-effect transistors by
employing circuit designs that incorporate a
source resistance. For a given IDBB range, the
value of the source resistance inversely affects
the in-circuit ID spread. An increase in the value
of the source resistance minimizes. yariatioDs in
ID as a function of temperature. The dual-gate
MOB field-effect transistor is ideally suited for
use in gain-controlled stages; dual-gate transistor biasing can provide various types of age
action including temperature compensation to
assure constant output.
Adutow••d.......,.
The author thanks L.A. Jacobus and W.A. Harris for the c0mputations and computer run~" for tho curves shown in Fla. 10.
and R. Miller for collect1na much of tho data abown.
1I.'lograplly
RCA nata Sheet. Transistor RCA 40673. File No. 381.
I. R. Burns, "High-Frequency Charac:tcdstic:s of tho In!iulatcdGate Field-Effect Traosiator." RCA. Re~Iflv. Vol. XXVIII, No.
1, ScpL 1967. pp. 385-417.
L. J. Sevin, Jr., FIeld·Effect TransiStors, McGraw-HIli Book
Company, NeW York, N.Y.
C. H. Lee and S. Reich. "An FM Tuncr UslDl Singlc-Gatc
MOS Field-Effect Transistors as RF Amplifl-=r and Mixer," RCA
Application Note AN-353S.
B. F. McKeon. ''Crossmodulatlon Effects in Single-Gatc and
~~...a:~34~~ Field Effect Transiston," RCA Application
63
MOS Field-Effect Transistors
ffil(]5LJD
Solid State
Application Note
AN-4431
Division
"RF"Applications of the
Dual-GateMOS/FET up to 500 MHz
by L. S. Baar
The RCA dual-gate protected, metal-oxide silicon,
tield-effect transistor (MOS FET) is especially useful for
high-frequency applications in RF amplifier circuits_ The
dual-gate feature permits the design of simple AGC circuitry
requiring very low power. The integrated diodes protect th€!
gates against damage. due to static discharge that may develop
during handling and usage. This Note describes the use of the
RCA-3N200 dual-gate MOS FET in RF applications. The
3N200 has good power gain and a low noise factor at
frequencies up to 500 MHz, offers especially good crossmodulation performance, and has a wide dynamic range; its
low-feedback capacitance provides stable performance
without neutralization.
Gate-Protection Diodes
Fig. I shows the terminal diagram for the 3N200.
Gate No. I is the input signal electrode and Gate No.2
is normally used to obtain gain control. The back-to-back
diodes are connected from each of the gates to the
source terminal, lead No.4. If short duration pulses
greater than :j:1O volts, generated for example by static
discharge, are inadvertently applied to either gate, the
protective diodes limit these voltages and shunt the current
to the source terminal. Thus the gates, under normal
operating conditions, are protected against the effects of
overload voltages.!
LEAD
LEAD
LEAD
LEAD
i . DRAiN
2 - GATE NO.2
3 - GATE NO.1
4 - SOURCE. SUBSTRATE.
AND CASE
Operating Conditions
Typical two-port characteristics at 400 MHz including
both "y" and "s" parameters, are given for the 3N200 in the
RCA technical bulletin, File No. 437. This note makes use cif
the "y" parameters; however, designers who prefer the
alternate method can, by parallel analysis, make use of the
"8" parameters.
A recommended operating drain current (10) for the
3N200 is approximately 10 milliamperes with Gate No. 2
suffiCiently forward biased such that a change in the bias
voltage does not greatly affect the drain current. An
adequate Gate No. 2-to-source voltage (VG2S) is approximately +4 volts. The forward transadmittance (Yfs) increases
with drain current, but saturates at higher current levels. The
increase in RF performance at drain currents above 10
milliamperes is achieved only with less efficient use of input
power.
To establish the optimum operating conditions for a
type, consideration must be given to the range of variations
in characteristics values encountered in production quantities
of the type. 2 One important measure of type variation is the
range of zero bias drain current (IOS)- The current range
given in the 3N200 technical bulletin for lOS is from 0.5 rnA
to 12 mAo A fixed bias condition intended to center the
range of drain current at the desired level, still will produce
an operating drain current range of 11.5 milliamperes with a
resultant wide range of forward transconductance (gf.). The
drain current can be regulated by applying de feedback with
a bypassed source resistor (RS). A good approximation ofRS
(where 100 ~ IOS/2) can be calculated by the use of the
following formula', assuming tl).at VGIS vS. lOS is linear
over the current range under consideration:
I -)
RS'" ( - gfs(min.)
(6.IOS
- - - - I)
Eq.1
~IOO
'See Appendix
Fig. 1 - Terminal diagram for the 3N200.
12-70
64
_____________________________________________________________ AN-M31
where:
~IOS is the current range given in the 3N200 technical
bulletin
~IOQ
is the desired range of operating current
gfs(min.) is the minimum forward transconductance
at 1000 Hz
With the value of RS established. then the Gate-No.1
Voltage (VGl) can be calculated from the equation
VGI = VGlS + IOQ
Rs
Eq.2
where VGlS is estimated by:
voltage range of +2 to +5 volts. this characteristic may be
used to effect AGC delay of the device in order to maintain
the low noise figure until the RF signal is out of the noise-level
range.
Stability Considerations
Typical u y" parameter data as a function of frequency
are given in Table I. Maximum available gain (MAG) calculated from these data are also included to indicate ideal
gain performance (Le .• Yrs =0). The ability of the MOS FET
to approach these gain levels depends on the device maintaining stable performance at the required operating frequency.
There are several methods which may be used to test for
gain vs. stability. One of these methods. the Linvill Criteria
(C). is defined by the equation:
IOQ-IOS
Eq.3
gfs(avg.)
Eq.4
where:
gfs(avg.) is the average forward transconductance
To establish the Gate-No.2 Voltage (VG2). follow the
same procedure described for calculating the Gate-No. I
Voltage. except that a fixed VG2S of approximately 4 volts
is adequate.
If gain control is desired. apply a negative-going voltage
to Gate No.2. Because Gate No.2 has little control in the
CHARACTERISTICS
A value for C which is less than I indicates unconditional stability. Applying the 400-MHz values taken from
Table 1 to the Linvill Criteria yields a value of C = 0.615;
. substantially less than the value indicating unconditional
stability.
SYMBOL
100
FREQUENCY (MHz)
200
300
400
500
UNITS
y Parameters
Input Conductance
gis
0.25
0.8
2.0
3.6
6.2
mmho
Input Susceptance
bis
3.4
5.8
8.5
11.2
15.5
mmho
Magnitude of Forward Transadmittance
I I
Vfs
15.3
15.3
15.4
15.5
16.3
mmho
Angle of Forward Transadmittance
I.:!..fs
-15.0
-25.0
-35.0
-47.0
-60.0
degrees
Output Conductance
gas
0.15
0.3
0.5
0.8
1.1
mmho
Output Susceptance
bas
1.5
2.7
3.6
4.25
5.4
mmho
0.012
0.025
0.06
0.14
0.26
mmho
Magnitude of Reverse Transadmittance
I I
Angle of Reverse Transadmittance
/::!.rs
Maximum Available Gain
Vrs
MAG
-60.0
-25.0
0
32.0
24.0
17.5
14.0
20.0
degrees
13
10.0
dB
Table 1 - "y" Parameters from 100 to 500 MHz
65
AN-~1
______________________________________________________
The following equation for Maximum Usable Gain
(MUG)3 is:
2K
MUG =
I I
Yfs
IYrs I(I + cos 8 )
Eq_S
where:
8 = LYfs + LYrs
K = skew factor
device. The clamp is soldered to a feedthrough capaCitor to
provide an effective, very-low inductance bypass to RF
signals. This mounting arrangemerit still permits the use of a
source resistor for DC stability, and enables the case to
provide isolation between the input and output circuit in
addition to the isolation afforded by the shield.
TUNING
CAPACITOR C2
LYrs = angle of reverse transadmittance
LYfs = angle of forward transadmittance
The skew factor, introduced in this equation, is a safety
measure that establishes an arbitrary degree of skewing in the
frequency response which may be introduced by regeneration. A value of 0.2 for K has been established on the basis of
past experience. The value of MUG calculated at 400 MHz is
13.8 dB. This value of MUG is greater than the value of
MAG, again indicating unconditional stability, since MAG,
ignoring inherent feedback, is the conjugately matched gain.
Therefore, neutralization or circuit loading is not required to
insure stable performance, and the gain can approach MAG,
limited only by circuit losses.
INPUT BNC JACK
TOP VIEW
SHIELD
TUNING~
C::APACITOR Cz
CLAMP
FEEDTHROUGH
CAPACITOR C7
Reverse transadmittance (yrS> is composed of several
components, but the major ones are feedback capacitance
(Crss) and source-lead inductance (LS). Therefore, care must
be exercised in the application of the Yrs values, shown in
Table 1, at the upper end of the usable frequency range. The
3N200 utilizes a JEDEC TO-72 package that has 4 leads. The
data in Table I was compiled with the use of a socket which
contacts the leads of the 3N200 as close as possible to the
bottom of the package as specified by the JEDEC Standard
Proposal SP-I028 "Measurement of VHF-UHF "y" Parameters". The leads are shielded from each other to eliminate
stray capacitance between the leads, but some lead inductance is inevitable. If the device is soldered directly to the
circuit components using commercial production techniques
rather than by precise laboratory methods, then additional
source lead inductance can be expected. Also, some
additional capacitive coupling may result if the input and
output circuits are not completely isolated from each other.
Because the published Yrs value for the 3N200 is very
small, the circuit Yrs values may differ significantly from the
Yrs values shown in Table I and hence, may result in an
u..'lst2ble operatL'1g condition. It is impossible to provid~ ct~ta
for all possible mounting combinations, therefore, a recommended mounting arrangement is shown in Fig. 2. The
source and substrate in the TO-72 package of the 3N200 are
internally connected to lead No. 4 and the case. The
source-lead inductance can be reduced, if the case is used as
the source connection. Fig. 2 illustrates a partial component
layout in which the case is held by a clamp or other fingered
66
SIDE VIEW
Fig. 2 - Partial component layout of 400-MHz amplifier
circuit
The reduction of source-lead inductance provides in
addition to greater stability, a lower input and output
conductance. Table 2 shows the differences in "y" parameter
values at 400 MHz when measured with the source connection made to lead No. 4 (in accordance with the
published data for the 3N200) and when measured with the
case connected directly to the ground plane of the test jig.
The magnitude of reverse transadmittance is halved with a
significant change in its phase angle. The input conductance
is reduced by 30%, and the output conductance is reduced by
13%. A recalculation of the expressions for MAG, MUG, and
UnviIl Criteria (C) shows a significant improvement in gain
and circuit stability.
While it is difficult to provide accurate information on
the effects of shielding between the input and output
circuits, its effect can be demonstrated when all other
feedback components have been reduced to negligible values.
The circuit, shown in Fig. 3 (for component layout see Fig.
2), was measured both with and without a shield. The
maximum gain, without the shield, averaged 0.8 dB lower
than with the use of the shield.
When receiver sensitivity is an important consideration
in the design of an RF amplifier. a compromise must be
made in the circuit power gain to achieve a lower noise
_____________________________________________________________
CHARACTERISTICS
SYMBOL
FREQUENCY If) = 400 MHz
Normal
AN-~1
UNITS
Case
Grounded
Connection
Maximum Available Power Gain
MAG
13_0
15.7
dB
Maximum Usable Power Gain (unneutralized)
MUG
13.8
19.4
dB
Linvill Stability Factor, C
C
0.615
0.335
mmho
Input Conductance
9is
3.6
2.5
mmho
Input Susceptance
bis
11.2
11.7
mmho
Magnitude of Forward Transadmittance
I vts I
15.5
15.5
mmho
Angle of Forward Transadmittance
ills
-47.0
-40.0
degrees
Output Conductance
90s
0.8
0.65
mmho
Output Susceptance
bos
4.25
4.25
mmho
Magnitude of Reverse Transadmittance
I Vrs I
0.14
0.07
mmho
Angle of Reverse Transadmittance
/!..rs
"V" Parameters
14.0
49.0
degrees
Table 2 - "v" Parameters at 400 MHz with source connection to lead No.4 and with case connected to ground plane
of test jig
a relatively poor noise figure. As shown in Table 2, the input
conductance (gis) with the case grounded is 2.5 mmho. With
factor. A contour plot of noise figure as a function of
the reactive portion tuned out, the noise factor at power
·generator source admittance is shown in Fig. 4. Each contour
is a plot of noise figure as a function of the generator source
matched conditions is almost I dB higher than the optimum
conductance and susceptance. Data for the noise figure were
noise figure. However, matching to 5.0 mmho results
obtained from a test amplifier designed with very low
in a near optimum noise factor with a loss of only 0.5 dB in
feedback. Even though the area of very low-noise figure in
gain. In addition, impedance matching to high conductance
the curves in Fig. 4 cover a broad range of source admittance,
FREQUENCY(f)= 400MHz
AMBIENT TEMPERATUREITA)=25°C
.l!
impedance-matching for maximum power gain could result in
E
E
J.
+15V
I5
~12. 5
300kn
~
il
is
u
4dB
/
V
NOliE FActR
~
rW! D..
j
V::~
V
)
)
"'- \ ( ((0
I"-- ~ ~'- V ~ / V
s
7. 5
{
r-.
5dB
RS
,
'\
10
- 20 - 17.5 - 15 -12.5
-
-
-
-
10
1.5
2.5
GENERATOR SOURCE SUSCEPTANCE Ibisl -mmho
270n
o
Fig. 4 - Noise factor vs. generator source (input) admittance
Fig. 3 - 4OD-MHz amplifier circuit
(vis!
67
AN-~1
_____________________________________________________________
also benefits crossmodulation performance, as will be discussed in a later section_
Gate Protection Diodes
The diodes incorporated into RCA dual-gate MOS
FETs, for gate protection, have been designed to minimize
RF loading on the input circuits. The small amount of RF
loading results in only a fraction of a dB loss in power gain
and a negligible increase in the noise figure. The advantages
of diode protection, greatly outweigh the slight loss in power
gain, especially in an RF amplifier intended for the input
stage of a receiver.
In addition to the protection afforded in normal
handling, the diodes also provide in-circuit protection against
events such as: static discharge due to contact with the
antenna, delay in transmit-receive switching, or connection
of an antenna with an accumulated charge to the receiver.
Crossmodulation
Crossmodulation is an important consideration because
it is an inherent device characteristic where circuit considerations are secondary. Crossmodulation is the transfer of
modulation from an undesired signal on a desired signal
caused by the non-linear characteristics of a device.
Crossmodulation is proportional to the third-order term
of the expansion of the ID - VGS curve. It is normally
specified as the undesired signal voltage required to pr~duce
a crossmodulation factor of 0.01. The crossmodulation
factor is defined as the percent modulation on a desired
carrier by the modulated undesired signal divided by the
percent modulation of the undesired signa\.4
Inspection of the ID - VGlS curve of Fig. 5· offers an
insight to the possible crossmodulation as a function of
gain-reduction performance. When both channels of the
3N200 are fully conducting current, as shown by the VG2S =
4-voll curve, the device approximately tollows a square-law
chatacteristic. If the ID - VGlS curve was ideal, the
third-order term would be zero; but in practical cases, the
.i
if
./"'"
>''"'/
"
2'&1
,...II!
elJ//'r""
~
I~III
0
0.4
I
(VG1SJ
68
NO.2
CIRCUIT B
CIRCUIT C
Fig_ 6 - Biasing circuits using the 3N200
Curve A, Fig. 7 shows a curve of the undesired signal
with a crossmodulation factor of 0.01 as a function of gain
reduction. The curve indicates performance is poorest when
gain reduction is in the 3- to IS-dB region; this region represents a Gate No.2-voltage range of approximately 0.5 volt to
2 volts. The exception to the poor crossmodulation perform-
.,
1000
'"t;
"
i~
DESIRED SIGNAL(f OJ"S6MHl
UNDESIRED SIGNAL I'U). a5 MHz
: \\
I
.
6
a 100
~
;;
\\\.
~
1
2
~
vs. gate No. 1-to-source voltage
"1
I
GENERATED
.,,
~
FROM FIG 6,
CIRCUIT C
(HIGHER
INITIAL 10)
J--
v.-
~. 1--........
'.\
~.
...
~-
-- --'
~
/
-"-·~~~E C,
~~~R~~61
I
CIRCUIT C
I
1'---
CURVE A,
GENERATED
FROM FIG. 6
CIRCUIT A
~-
I"
,,
\\ J
I 1\
CURVE 0,
,---
w
GATE No.l-TO-SOURCE VOLTAGE IVGIS)- V
Fig. 5 - Drain current {/oj
GATE
CIRCUIT A
!
,
:I~I!I
-I
t
GATE
NO.2
~
~
~
Yoo
AGe
VOLTS
;
~
>;
•
•
Yoo
a
DRAIN-TO-SOURCE VOLTS (Vosl"IS
12.5
Yoo
z
AMBIENT TEMPERATUREITAI"25°C
•
third-order term and crossmodulation have some low values.
When the gain is reduced, by the application of bias to Gate
No.2, the square-law characteristic changes to a curve with a
knee. Sharp curvatures usually result in larger high-order
terms and poorer crossmodulation performance can be
expected at lower gain conditions. If in Fig. 6, Circuit A, we
assume a fIXed bias (VGIS) of approximately +0.4 volt, then
the expected variation in crossmodulation is determined at
the points where the ordinate at VGIS = +0.4 volt crosses
the curves. Crossmodulation performance at values ofVG2S
= +4 volls to cutoff is as follows: good (low crossmodulation) at +4 volts, poorer at +2 volts, poorest at +1 volt, and
again improves from zero volts to cutoff.
/1
-
1
\
\
... ""-CURVE B,
GENERATED
FROM FIG. 6,
CIRCUIT B
\
,
\.,":'
00
~
10
o
10
20
30
40
GAIN REDUCTION IdBI
Fig. 7 - Crossmodufation
circuits shown in Fig. 6
lIS.
50
60
70
gain reduction using biasing
--------------------------------------_____________________ AN-~31
ance in this· range is the sharp peak which occurs at the S-dB
level and is due to a curve inversion that takes place just prior
to the knee. Beyond the IS-dB level, crossmodulation
generally shows an improvement.
If Gate No. I is also reverse biased in conjunction with
Gate No.2 in the manner shown in Fig. 6, Circuit B, then the
overall performance is poorer because the Gate No. I voltage
wiI1 tend to follow the knee of each curve. This occurrence is
evident in Fig. 7, Curve B. If Gate No. I is biased as shown in
Fig. 6, Circuit C, the Gate No. I-to-Source voltage intercepts
the Gate No. 2 curves where the curvature is less severe,
indicating as shown by Fig. 7, Curve C an improvement in
crossmodulation performance. A further slight improvement
is possible by the use of a higher initial operating drain
current, which effectively moves the intercepts to the right
on each curve. This improvement is indicated in Fig. 7,
Curve O.
The curves in Fig. 7 establish that the biasing
arrangement which provides optimum crossmodulation
performance is the one in which Gate No. I forward bias
increases as Gate No. 2 controls the gain. This biasing
arrangement is easily accomplished by the use of a fIxed Gate
No. I voltage and a source resistor. As the Gate No.2 bias
voltage reduces the drain current, there is also a decrease in
source voltage and an increase in the Gate No. I-to-Source
voltage. The gate-to-source voltage ratings must not be
exceeded under any circumstances.
Summary
An RF amplifier, ideally, should provide high gain, a
low-noise fIgure, and low crossmodulation. The 3N200 offers
a good compromise in providing these three features. As
indicated in the section on "Stability Considerations" a
mismatch at the circuit input to a higher conductance level,
provides an improved noise fIgure. The same mismatch
condition also improves crossmodulation performance. The
input signal at the gate of the device, when mismatched as
indicated above, is lower than if it is power matched. The
same ratio applies to any undesired signal and, thus, reduces
the possibility of crossmodulation interference.
Appendix
The drain current of a device is established by the
relationship
If a source resistor is used, as shown in Fig. AI, the gate
No. I-to-source voltage is
YGlS=YGI-IORS
then
10=gfs(VGI-IO RS)+IOS
gfs YGi
10 = - - - +
I + gfs Rs
or
lOS
I + gfs RS
Fig. A 1 - Bias circuit using the 3N200
The typical curves in Fig. A2 show drain current vs.
Gate No. I-to-Source Yoltage as a function of lOS level.
These curves are almost linear when the typical operating
drain current is in the lO-milliampere region. For the
remainder of the analysis a linear relationship will be
assumed for the reqUired range of quiescent current. The
assumption of linearity dictates that gfs is a constant.
The required range of drain current is 102 - 101
where:
gfs YGI
lOS (max.)
10 2 = - - - + - - - l+gfsRS
l+gfsRS
~O
=ID2 - 101 -
lOS (max.) - lOS (min.)
l+gfsRS
~IOS
- --l+gfsRS
Solving the above equation for RS gives
where:
lOS = drain current
at:
YGlS=O, VG2S=+4volts.
where:
gfs is equal to the expected minimum value at the
required 10
69
AN-~31-----------------------------------------------------------
}t
1/
VOS·+I!5V
YG2S~+4V
..i
5
~~
12.5
II / I
0
§
5
5
2.5
0
-2
l
7
1/
?I
f!
fl J
II
V
/
II
J
V V
-I
0
I
GATE No.I-TO-SOURCE VOLTAGE (VGIS)-V
Fig. A2 - Drain current vs. gate No. '-to·source volrage
70
References:
1. L. A. Jacobus and S. Reich, "Design of Gate-Protected
MOS Field-Effect Transistors", RCA Application Note
AN4018
2. S. Reich, "Field-Effect Transistor Biasing Techniques",
EEE, Sept. 1970
3. R. A. Santilli, "RF and IF Amplifier Design Considera·
tions", IEEE Transactions on Broadcast and TV
Receivers, Nov. 1967
4. H. Thanos, "Crossmodulation on Transistorized TV
Tuners", IEEE Transactions on Broadcast and TV
Receivers, Vol. 9 No.3, Nov. 1963
OO(]5LJ[]
MOS Field - Effect Transistors
Application Note
AN-4590
Solid State
Division
Using MOS FET
Integrated Circuits in
Linear Circuit Applications
by S. Reich
Although the discrete metal-oxidHemiconductor (MOS)
lield-effect transistor (FET) has been available for many
(ears,1 its usage has been comparatively limited. Designers
~ave been reluctant to employ MOS FET devices in their
:ircuits because the gate oxide· in a discrete device is
IUInerable to damage by static electricity discharge~ en:auntered during handling and/or electrical transients found
in circuit applications. RCA engineers have now successfully
:ombined MOS FET and integrated-circuit (IC) fabrication
techniques to produce a simple monolithic MOS FET IC in
which back-ta-back diodes are connected in shunt with the
pte oxide to restrict the gate potential appearing across the
!lite oxide. The simple gate·protected IC's are of major
;ignificance because their immunity to damage by static
!Iectricity or by in-circuit transients is on a par of excellence
with that of other solid-state devices intended for similar
types of applications. Consequently. circuit deSigners can
now practically utilize the many unique MOS FET
:haracteristics. viz.. high input impedance. square-law
transfer characteristic. wide dynamic ;ange. dual·gate
:onfiguration. etc. For example. the square-law transfer
:haracteristic is especially desirable in the maintenance of
low cross·modulation characteristics in rf amplifiers).3 This
paper contains a brief review of the device theory, followed
'y a survey of some linear circuit applications for the MOS
FET Ie.
REVIEW OF DEVICE THEORY
The operating voltage applied to the MOS FET determines whether the device will function as a resistor, an
amplifier, or a diode. This section will provide a review of
these various MOS FET operational modes. Subsequently,
the useful operational modes will be employed in typical
applications.
Fig. I is a sketch, for zero gate-to-source voltage, of 10 as
a function of VOS for an n-channel depletion-type MOS
FET. Changes in the conductivity pattern are shown in the
simplified conductivity profile for each region of operation.
Ohmic - Region 'A' depicts an Io-VOS curve that is
characteristic of a resistance. The shape of this curve is a
function of VOS (drain-to-source voltage). Its slope is
governed by VGS (gate-to-source voltage). The VOS/IO
I
I I
;;-
II
II
1/
&
BREAKDOWN
~~Ioo--~-~-.IC~~~R~EN~T~)--+-f-~IF~O~RB~~
:::~:I ~
~
CIRCUIT CONDITION
~--~--------------~V~D~sl~M~A~X)r
DRAIN-TO-SOURCE VOLTAGE (Vos)
Fig. '-Regions of operation - n-channel depletion MOS
FEr.
characteristic i.e., its resistance value, is controlled by the
gate voltage.
As \tOS is increased, it produces an electrostatic stress in
the channel that modifies the channel conductivity as shown.
The channel is completely pinched off beyond VPo
(pinch-off voltage): Increasing Vos serves only to maintain
10 at a constant level.
Amplifier4 - For a fIXed gate-voltage, 10 is at a constant
level in region '8'. A change in VGS produces a change in 10;
thus in region '8' the device exhibits the transconductance
characteristic that is essential in amplifier operation (i.e., Gm
=dIO/dVGS).
"Forbidden" Region - Increase of Vos beyond its rated
maximum could produce avalanching in the drain-tosubstrate diffusion (diode). Therefore MOS FET devices
should not be operated in this region.
The duai-gate device is a serial arrangement of two
single-gate devices. This arrangement improves the MOS FET
performance by reducing capacitance from output to input
(drain to gate I), and provides an added control element that
adds to the versatility of the MOS FET_
3-71
71
AN-4590 ________
~
_______________________________________________
Gate Protection
A gate-protection system, which can be incorporated as
an integral part of the transistor structure, has been
developed for dual-gate MOS transistors. In devices that
include this protection system, a set of back-to-back diodes is
fabricated on the semiconductor pellet and connected
between each insulated gate and the source. (The low
junction-capacitance of the small diodes represents a
relatively insignificant addition to the total capacitance that
shunts the gate.) Fig. 2 is a profile drawing and schematic
symbol for
n-channel dualilate-protected depletion-type
MOS field-effect transistor. The MOS FET Ie metallization
pattern, including the connections to the drain, gate I, gate
2, source, and protective devices, all on a single monolithic
structure, is shown in Figure 3.
The back-to-back diodes do' not conduct unless the
gate-to-source voltage exceeds typically ±10 volts. The
transistor, therefore, can handle a very wide dynamic signal
'swing without significant conductive shunting effects by the
diodes Oeakage through the "nonconductive" diodes is very
low, typically I na). If the potential on either gate exceeds
typically +10 volts, the upper diode (shown in Fig. 2) of the
P,ir associated with that particular gate becomes conductive
in the forward direction and the lower diode breaks down in
the backward (Zener) direction. In this way, the back-toback diode pair provides a path to shunt excessive positive
charge from the gate to the source. Similarly, if the potential
on either gate exceeds typically -10 volts, the lower diode
becomes conductive in the forward direction and the upper
diode breaks down in the reverse direction to provld.e a shunt
path for excessive negative charge from the gate to the
source. The diode gate-protection technique is described in
a"
I. DRAIN
2 GATE 2
3 GATE J
4 SOURCE
(SUBSTRATE AND CASE)
'0'
CONNECTING PADS FROM PROTECTIVE
DtODES TO SOURCE
(:ig. 3-Monolithic protected dua/-gate MOS FET IC.
more detail in the folloWing section on integrated gate
protection.
Integratad Gate Protection
The advent of an integrated system of gate-protection in
MOS field~ffect transistors has resulted in a class of
solid-state devices that exhibits ruggedness on a par with
other solid-state rf device~. The gate-protection system
mentioned in the preceding section offers protection against
static discharge during handling operations withou t the need
for external shorting mechanisms. This system also guards
against potential damage from in-circuit transients. Because
the integral gate-protection system has provided a major
impact on ilie acceptability of MOS field~ffect transistors
for a broad spectrum of applications, it is pertinent to
examine the rudiments of this system.
Fig. 4 shows a simple equivalent circuit for a source of
static electricity that can deliver a potential eo to ihe gate
input of an MOS transistor. The static potential Es stored in
~RS
'b'
Fig. 2-Protected dual1lllte MOS FET IC: (a) schematic
diagram; (b) profile sketch.
72
_
'.
~1
LT,-CD___
Fig.. 4-Equivalent circuit for source of static electricity.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ AN-4590
an "equivalent" capacitor Co must be discharged through an
internal generator resistance Rs. Laboratory experiments
indicate that the human body acts as a static (storage) source
with a capacitance CD ranging from 100 to 200 picofarads
and a resistance Rs greater than 1000 ohms. Although the
upper limits of accumulated static voltage can be very high,
measurements suggest that the potential stored by the human
body is usually less than 1000 volts. Experience has also
indicated that the likelihood of damage to an MaS transistor
as a result of static discharge is greatec during handling than
when the device is installed in a typical circuit. In an' rf
application, for example, static potential discharged into the
antenna must traverse an input circuit that normally provides
a large degree of attenuation to the static surge before it
appears at the gate terminal of the MaS transistor. The ideal
gate-protection signal-limiting circuit is a configuration that
atlows for,a· signal, such as that shown in Fig. 5(a), to be
handled without clipping or distortion, but limits the
amplitude of all transients that exceed a safe operating level,
as shown in Fig. 5(b). An arrangement of back-to-back
diodes, shown in Fig. 5(c), meets these requirements for
protecting the gate insulation in MaS transistors.
HANDLE THIS
'01
.,:]===
'el
'0'
-10
,.1
'01
Fig. 6-ldeal transfer characteristic of protective diodes (al.
and resulting waveforms in equivalent circuit (bl.
voltage of 20 volts. The transfer-<:haracteristic curves show
that the diodes will constrain a transient impulse to potential
values well below the ±20 volt limit, even when the source of
the transient surge is capable of delivering several hundred
milliamperes of current. (These data were measured with
I-microsecond pulses applied to the protected gate at a duty
factor of 4 x 10-3).
Fig. 5-Gate·protection requirements and solution.
Ideally, the transfer characteristic of the protective
signal-limiting diodes should have an infinite slope at
limiting, as shown in Fig. 6(a). Under these conditions, the
static potential across CD in Fig, 6(b) discharges through its
internal impedance Rs into the load represented by the
signal-limiting diodes. The ideal signal-limiting diodes, which
have lI!I infinite transfer slope, would then limit the voltage
present at the gate terminal to its knee value', ed. The
difference voltage, es appears as an IR drop across the internal
impedince of the source Rs, i.e., es Es - ed where Es is the
potential in the source of static electricity and ed is the diode
voltage drop. The instantaneous value of the diode current is
then equal to eslRs. During physical handling, practical peak
values of currents produced by static-electricity discharges
range from several milliamperes to several hundred milliamperes.
Fig. 7 shows a typical transfer characteristic curve
measured on a typical set of back-to-back diodes used to
protect the gate insulation in an MaS field-effect transistor
that is nominally rated for a gate-to-source breakdown
"
10
oa
0,&
0 .•
~i
Ii
;!
:1
ru
=
-0.4
-0.'
-0.'
-1.0
-1.2
Fig. 7- Typical diode transfer characteristic.
73
AN4590 ______________________________________________________
Electrical Requirements
The Triod.Connectecl Protectad Dual-GatelC
The previous discusSion points out that optimum
The dual-gate MOS FET can be connected so that it
protection is afforded to the gate with a signal..Jirniting diode functions as a single-gate device, as shown in Fig. 9. The
that exhibits zero resistance (i.e., an infinite transfer slope triodeo(;(Jnnected configuration has curve tracer (drain
and fast turn-on time) to all high-Ieve! transients. In addition, family) characteristics that look like the 'real' triode. The
the ideal diode adds no capacitance or loading to the rf input curves in Fig. 10 show that characteristics for the triode MOS
circuit. This ideal diode in practice simply does not exist, but FET (3NI28) and the triode-connected dual-gate MOS FET
integrated circuit techniques made possible the development (3NI87) are essentially simnar.
of a gate-protected'MOS FET IC that is close to the ideal.
For example, Fig. 8 shows typical 2OG-MHz input characteristic changes brought about by the addition oC the integrated
circuit diodes. Their effect on power gain and noise factor is
shown by the data given in Table 1. These data indicate that
\
I _I
J
there are no discernible reductions in power gain and a trivial
,
I
\
/
noise Cactor increase oC about 0.25 dB.
I,
(
I
I~r-----------------------------_,
INPUT RESISTANCE
--- INPUT CAPACITANCE
IZOO
'-ZOOMHI
*...
1000
"~~
ill"'"
~
tJ
8.0 ~
-------...----- --
c
7.0
GAT[·PROT[CTED MOS FET Ie
I-
.00
200
0
,...,
10
12
"~
5.0
__ - - .......UNPROTECTEO MOS FET
DRAIN CURRENT ClO)-mA
i!
I-
6.0
...--
..-----
1,4.0
"
Fig. 8-Input resistance and capacitance as functions of drain
current for the MOS FE T with and without diodes.
Table I - Power Gain and Noise Factor at 200 MHz
UNIT
POWER GAIN
(dB I
DIODES
DIODES
IN
REMOVED
1
2
3
4
5
6
7
8
9
10
74
16.3
18.8
16.5
16.3
17.7
17.2
17.1
17.9
18.5
17.3
16.4
18.5
16.2
15.7
17.8
17.5
17.0
18.0
18.5
17.3
NOISE FACTOR
(dBI
DIODES
IN
3.7
2.4
3.3
3.9
2.6
2.8
3.3
2.9
2.4
3.2
DIODES
REMOVED
3.4
2.2
3.0
3.4
2.4
2.5
3.2
2.6
2.3
3.0
-
4
I
--
4
Fig. 9-DUJlI-gate MOS FET Ie in II ring/__ re configuration.
':.,
_____ GATE· PROTECTED liDS FET Ie
~'\
\:==/
TrioR-Connectad-Dwlce ChI...:teristics
Some useful triode-connected-device characteristics are
provided in Table 11 in the Corm of comparisons with
dual-gate and single-gate devices. It should be noted that the
differeltcIC in lOS level between the 3NI87 and the 3N200
carries over to their triode-connected versions. A curve
showing lOSS for triode connection versus lOS for the
dual-gate configuratioro (i.e., VG2S = 4 volts) is shown in Fig.
11.
A plot of the triode-connected dual-gate transCer characteristics (10 vs. VGS) is shown in Fig. 12; similarly, gCs
curves are given in Fig. 13 as functions of 10. Curves for
typical dual-gate operation are available in commercial data
sheets. 5 ,6
Dual gates connected as tetrodes and triodes were
evaluated for Ro(ON) where 'on' resistance compares
favorably with single-gate devices. Typical variations in
Ro(ON) as a function of gate voltage are shown in Fig. 14.
1
110
"0
!:!
~
z
...
a'"
z
;;
~ 0
a
a
20
DRAIN-lO-SOURCE VOLTAGE (Vos)-V
DRAIN-lO-SOURCE VOLTAGE (VDS)-V
'01
'01
20
Fig. fO-Drain families: fa) for triode-connected protected
dual-gate device: fb} for triode.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ AN-4590
Table II - Comparison of Typical Electrical Characteristics for Triode-Connected Dual-Gate, Dual-Gate,
and Triode MOS FET Devices
CHARACTERISTIC
CONDITIONS
TRIODE-CONNECTED
3N187
lOS
g"
3N200
DUAL-GATE CIRCUIT"
3N187
3N200
SINGLE GATE
3N128
UNITS
V OS -1Sv
6.0
2.0
15
{VOS -1SV
10"10ffiA
7.0
8.5
12
15
·2.0
·1.0
·2.0
·1.0
-1.5
V
2.0
2.0
1.0
1.0
10-4
nA
10.0
10.0
6.0
6.0
5.5
pF
0.5
0.5
0.02
0.02
0.2
pF
2.0
2.0
2.0
2.0
1.4
pF
15
rnA
mmho
f'l kHz
VGlSIOFF)
{V oS "lSV
10 "SOJIA
IGlSS
Ciss
f
VGs':!Sv
OS "lSV
10"10mA
f'" 1 kHz
COS.1SV
Crss
IO"'"10mA
f -I kHz
Coss
rOS.1SV
10 -lOrnA
f -1 kHz
ROSION)
{VOS'1 v
160
250
100
150
300
ohm
VGS=O
·V G2S
=4 v except for IGSS measurement, where VG25 '" O.
It should not be inferred from these comments that all configurations shown in Figs. 15(a) and 15(b), the MOS
single-gate applications can be handled by the protected device is normally conductive, i.e., eo is low. A negative
dual-gate device. The advent of MOS FET opened application gating-pulse turns off the MOS device so that approximately
areas in which circuit requirements imposed leakage·current 50 percent of eg appears at the output terminals. Circuit (a)
limits in the picoampere range. For these applications the features the use of an additional control potential (VG2). A
present generation of protective gate devices do not suffic~ dc potential may be applied as shown to the second gate,
and it is necessary to employ a "classical" MOS FET type thereby establishing the value of desired channel 'on'
(e.g., 3N128) and exercise precautions against gate-insulation resistance (ROS). Alternatively, circuitry can be arranged so
puncture.
that the second gate can function as a "coincidence-gate",
i.e., to reduce eo to a low value, a positive-going pulse must
SURVEY OF LINEAR APPLICATIONS
be applied to gate 2 simultaneously with a positive-pulse to
This section shows typical circuit arrangements. Some are gate 1.
documented, and others are design ideas for use of dual·gate
All circuits in Fig. IS make reference to Note (A). The
MOS FET's with integrated diodes in applications using circuit diagrams show a "jumper" connected between two
tetrode and triode-connected configurations.
terminals in the drain-to-ground-return circuits. The circuits
as drawn assume a peak generator level (eg) of less than 0.2
Choppers
The circuits shown in Fig. IS use the dual-gate MOS FET volts. Should the signal exceed this value, it is possible that
Ie in. chopper or gating circuits. In the shunt·drcuit the "n_p" parasitic diode between the drain and semi-
75
AN-4590 _________________________________________________________
~r,~N~.~7~------~--------~
.1
TRKJOE CONNECTED
c
•I
E20
I
Y
I..
II
I•
w
t
8
H
~~Z~~-_~,---L~O~-L--~-J
GATE-YO-SOURCE
VOLTAG£ 1Yos'-V
(al
IS "'''"N-:.-O.,.O------------------,
TRIODE CONNECTED
4
10
12
I DSS t TRIODE - CONNECTED)- IRA
Fig. , '-Correlation of zero·bias drain current for the pro'
tected dual·gate device in terrode (/
and triode (/OSS)
configurations.
os!
conductor substrate will be driven into conduction and load
the signal. This contingency' may be obviated (with a
simultaneous improvement in allenuator linearity) by con~~.--~-_~,~~--O~-L--~-J
necting a suitable dc potential in lieu of the "jumper", so
GATE-YO-SOURCE
that a positive potential is applied to the drain. The
VOLTAGE '''Gs1-V
magnitude of this voltage should equal or exceed the peak
Ibl
value of the rms signal f~om ego
Circuits shown in Figs. 15(c) and J 5(d) function in a ,Fig. 72- Triode-corinected protected dual·gate MOS FET IC
manner opposite to those described above, i.e., output transfer characteristics.
voltage appears at eo in the absence of a gating signal.
Consequently, a negative gating signal· reduces the level of eo. Constant·Current Sources
The characteristics of the MOS FET 1(' in the region
The dual-gate configuration can be made into an 'or' circuit,
i.e., a negative signal applied to gate 2 of sufficient magnitude beyond pinch·off make the device suitable for constantto override VG2 will also reduce the le.vel at eo.
current supplies, as illustrated in Fig. 17 (using a "triodeconnected" dual-gate device).
Attenuaton
The dual-gate device may be used to obtain higher values
Fig. J6 shows the dual-gate device in an attenuator of current-regulation with the circuit depicted in Fig. 18. A
circuit. In Fig. 16(a) both gates are used as control elements. supply circuit with a maximum output voltage capability of
This type of circuitry is particularly attractive when control about 4.0 to 5.0 volts is required for VG2. Values greater
of the allenuator must be located at some remote location. A than this will have negligible effect on output current
dc potential on gate J has greater control on the channel control.
resistance than is the case for gate 2. Thus an arrangement
The circuits in Fig. 19 use the MOS FET constant-current
can be used whereby gate 2 provides. ~ ufine" attenuatQr characteristic to make 2' regulated constant-voltage reference
adjustment and gate J controls "course" adjustment. The source by feeding lOS through a fixed-value resistor.
circuit in Fig. 16(b) shows the dual-gate device in a
In any typical amplifier application using the MOS FET
triode-connected allenuator circuit. Curves showing typical device, e.g., in Fig. 20, the voltage developed across a
vari&tions in resistance as a function of gate-voltage were bypassed source resistance provides a well-regulated fixed
reference voltage (if the amplifier stage is not s\lbjected to
given in Fig. ~ 4.
76
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ AN-4590
)000,-----------,
10,------------,
RCA 3NI87
TETROCE
3NI87
TRIODE CONNECTED
~
~ 800
o
I
~
.!!
o 600
.!O.
...
!~
400 \
~ 200~ " - ~-----I
12
-I
DRAIN CURRENT lID) - mA
GATE - TO-SOURCE VOLTAGE I VGS) - V
la)
1000,-----------,
RCA 3NI87
TRIODE - CONNECTED
10,------------,
3N200
TRIODE CQNNECTI:":O
~
~
800
o
Vas -0
G2 TIED TO GI
I
...
~
400
~
z
~
200
GATE - TO-SOURCE VOLTAGE (Vas 1- y
o
12
DRAIN CURRENT 110) - mA
Ibl
Fig. 13- Triode-connected protected dual·gate MOS FET IC
transconductance characteristics.
varying liias conditions, silch as those encountered in
connection with AGC). When a reference voltage is obtained
in this manner, it is advisable to feed it to other circuitry
through an adequate decoupling network.
General-Purpose Amplifier Circuits
Fig. 21 shows three basic single-stage amplifier configurations that utilize dual-gate-protected MOS FET IC's as triodes
and as tetrodes in common source, common~drain. and
common-gate circuits. Each configuration has its own
particular advantages for specific applications. The dual-gate
device has an added advantage in any of these configurations
in that gate 2 provides (a) reduced gate-to-drain capacity by
Fig. 14-"ON" resistance as a function of gate voltage for
tetrode- and triode-connected protected dual-gate MOS FET
IC's.
an order of magnitude, and (b) a convenient means for
controlling the gain of the stage by adjusting the dc potential
applied to gate 2.
A dual-gate device is shown in Fig. 22 as a shunt-type
altenuator to control the input level to a source-follower.
The source-follower uses the dual-gate MOS FET with gate 2
available as a control for adjusting the gain of the
source-follower. The jumper in the ground return path of the
generator can be used to insert a positive voltage on the drain
for the reasons explained above.
Fig. 23 shows a circuit using the "triode-connected"
dual-gate device in a simple 20-dB preamplifier for extending
the sensitivity range of an oscilloscope or ac voltmeter. It can
also be used in audio circuits as a phono preamplifier or
microphone preamplifier. It is shown as self-contained, i.e.,
77
AN-4590 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
lOOK
lOOK
e.
'.
(NOTE A
SEE
TEXTI
(NOTE A
SEE
TEXT)
\.,
\.1
Fig. 15--Typical chopper circuits using protected dualgate MOS FET Ie's. (a) shunttype using tetrode connection;
(b) shunt-type using triode
connection; (c) series-type
using tetrode connection; (d)
series-type using triode connection.
VG2
\"
\el
+Vcc
c
!---O
+"cc
c
(---0
I bJ
'Fig. 16-Attenuator circuits using the protected dual·gate
MOS FET Ie: lal variable series· type attenuatar with coarse
and fine controls; Ibl variable series· type attenuator using
triode-connected coniiguration.
78
with its own power supply and a by-pass switching
arrangement.
In Fig. 24 "triode-connected" MOS FET devices are used
in a simple differential amplifier configuration in which the
"triode-connected" gates of the two devices are biased from a
single source (the junction of R I and R2). This arrangement
is possible because the 3N! 87 has a typical gate current
(IGSS) in the triode configuration of 2 nanoamperes.
Therefore, the bias can be supplied through R3 with a
negligible .voltage offset. Resistor RS is used to null out the
effects of slight differences in device characteristics so that
the offset-voltage at eo can be set to zero.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ AN-4590
+o-------------------~~~
I, I
10
"-0
1,1
Fig. 19- Voltage-reference circuits using protected dual·gate
MOS FET IC: (a) as triode; (b) as terrode.
R-Iooon
20
6mA-
R'"-zzon
3mAQ.SmA-
101
-II.;...._-i_____"o.,;.:2"-10::.;0:.;.:...-_ _ _-1
20
Fig. 17-Constant·current supply using protected dual·gate
MOS FET IC in triode configuration: (a) basic circuit;
(b) typical
vs. Vin for RCA·3N200 in the basic circuit;
(c) typical
vs. Vin for RCA·3NI87 in the basic circuit.
'0
'0
The circuit in Fig. 2S shows another differential amplifier
configuration, in which the offset voltage at eo can be set to
zero by means of appropriate potentials supplied to the No.2
gates, adjustment being provided by R6.
The circuit shown in Fig. '26 is a frequency-selective
amplifier intended for operation within the audio frequency
range of 10 Hz to 20 kHz. Frequency-selective circuits are
used for selective coding, i.e., in garage-door openers,
narrowing the bandwidth response in CW receivers to.
~-l
eliminate unwanted side bands, and in systems requmng
some form of keying impulse (e.g., synchronizing the
narration in a tape recorder with slides).
The frequency-selective circuit shown is an audio
amplifier with a twin-"T" RC filter circuit in its output. This
network provides regenerative feedback to the input circuit
at an audio frequency predetermined by the selection of
capacitors CS, C6, and C7. The peaking control R7 fine-tunes
the twin_UT" for the desired frequency of operation, and
potentiometer R8 adjusts the level of feedback for desired
performance. The circuit as shown in Fig. 26 is selective at an
audio frequency of 1200 Hz. Table III below lists values of
the bridge capacitors for operation at other frequencies.
RF Amplifiers, Oscillators, and Mixers
The circuit in Fig. 27 is a converter used to convert
100MHz WWV broadcasts to I.S MHz for reception on a
standard broadcast-band receiver. The MOS FET IC is used in
the dual-gate configuration as a mixer and is triodev+
v+
10
VI.
VOLTAGE
+-.....--'Vvv-...--o REFERENCE
SOURCE
RL
"s
. v+
Fig. 18-Protected dual·gate device as a constant-cu"ent
source.
rl~F
Fig. 20- Typical amplifier using bypassed source resistor as a
voltage source.
79
AN~90
________________________________________________________
DUAL GATE:
SOURCE FOLLOWER
,.....-------,
I
I
I
I
I
TRIODE CONNECTEO
10.01 I
I ~. I
, I
I
~Hl1411
I
I
I
____ -'I
I
I
I
I
, I
I
YDD
R
I I
I
I
IL _____ _
± Yo CONTROL
tol
Fig. 22-Shunt-type attenuator' controlling input level to
source-follower.
i~::r~~e~---, GAIN AD.t.
f-:-1
I
10 K
J
O.l,..F
1"
1000
TRIODE CONNECTED
=
INPUT
ON
~
0
•
18
=
'"
v-=-
OUT
J-~--l:
OFF
l
Fig. 23-Protected dual-gate MOS FET Ie preamplifier.
DUAL GAT[
TRIODE CONNEt TEO
'"
Fig. 27- Three basic single·stage amplifier configurations that
use protect11d dual·gate MOS FET Ie's as triodes and tetrodes:
fa) common source; fb) common drain; fc) common gate.
80
Fig. 24- Triode-connect11d MOS FET Ie's in a sImple differential amplifier circuit.
________________________________________________________ AN4590
VDD
".
",
".
Fig. 25-Protected dual·gate MOS FET Ie's in typical differential amplifier circuit using gate 2 for balance control.
IN914
0.005
.'
1+ 20 Y
Fig. 27-10 MHz·to·I.5 MHz converter for WWV reception.
0'
flO'
"
.--••-0-.--.....'-'.-,--c-.'" ••0
1500 pF
PEAKING
toNT-'L
pF
OUlP
.
-+-+_..... ..
INPUT
.. 0
L ___
o
/
~'·
SELEctVITY
CONTROL
B-
Fig. 26-Selective audio·frequency amplifier.
Table III - Capacitor values for Fig. 26
(Hz)
C5,C6
(pF)
C7
(pF)
150
300
600
2400
4800
9600
5,600
2,700
1,300
330
160
82
12,000
6,200
3,000
750
360
180
FREQUENCY
I
f---------O
connected in a crystal oscillator circuit. MOS FET
characteristics are very attractive for use in highly stable
oscillator circuits because the inherent reactive components.
Ciss and Coss• are relatively invariant over a very wide
temperature range. Additional types of oscillator circuits in a
number of different arrangements are shown in Fig. 28.
It is also feasible to use the MOS FET IC as a keyed
oscillator. by utilizing a circuit arrangement shown in Fig .
29. A negative voltage at gate 2 will key the oscillator.
Additionally. the level of the oscillator output can be
controlled by variation of RL. It should be understood that
any of the oscillator configurations shown above are
adapta~le to the circuit arrangement in Fig. 29.
A dual-gate-protected MOS FET IC is used in Fig. 30 as a
regenerative amplifier/detector. The circuit is basically an
amplifier with controlled feedback adjusted to the verge'of
oscillation. as shown in Fig. 30. Gate 2 provides a convenient
means to adjust the amplifier gain to the requisite level.
Detection is accomplished in the gate 1 input circuit by the
interaction of the diode in parallel with the 100-kilohm
resistor and the 270-picofarad capacitor.
A typical circuit that utilizes the MOS FET IC in the pix
IF section of a TV receiver is shown in Fig. 31. This circuit
utilizes gate 2 for AGC. The reverse AGC bias7 applied to
gate 2 in the circuit of Fig. 31 has the secondary effect of
making gate 1 move
a positive direction. Evaluations of
the relationship between AGC and crossmodulation show
that it is desirable to allow the voltage between gate I and
the source to move in a positive direction when gate 2 is
reverse-biased. Various circuit arrangements have been used
in
81
AN4590 ____________________________________________________
to achieve this action. Reference to a more comprehensive
review on crossmodulation as a function of bias is given in
the bibliography),]
.
lOOK
4.11(
lOOK
VD
'DO
"
0.1,...
.-TA""TlcniotJ#TI.IUd~
eOUENDfII COIL
C",,,,,TOt
,.,
TO ",
AMPLIFIER
'"
Vo
SN.I'
3N'I'
0.001".,
Fig. 3D-Protected dual·gate MOS FET IC regentlntive , .
ceiver.
c'
C"
.600
Co
~~
C"
Co
RFC
Fig. 28-0scillator circuits using MOS FET /C's: (al and (bl
Hartley oscillators; (cl and (dl Co/pirrs oscillators.
VG2
20 K
A typical circuit for an FM tuner is shown in Fig. 32. The
biasing arrangement for the rf stage incorporates proVisions
for AGC. The circuit in Fig. 33 is an rf amplifier designed for
200-MHz operation. The typical power gain for a 3N187 in
this circuit is 18 db, with a noise factor of 3.5 dB.
Typical circuits for a TV tuner are shown ill Figs.
34(aHd). Fig. 34(a) is the rfstage operating at a current level
of approximately to milliamperes. Gate I is about 2 volts
above ground potential. When AGC applied to gate 2 is
advanced the drain current decreases, with a consequent
reduction in voltage drop across the 27(N)hm source
resistances. 7
180)(
~~~~Gcr--~A1~--~~-JVV~--1---~)+
Voo
LEvEL
CONTROl-RL
lOOK
11011.
1-
100
REVERSE
AGe
1001(
IF AMPLIFIER
1F
TDN. .T
IF STAGE
'DK
00.
11"
~
~
.6.
1"
DOS
*
AU AfSISTANC£ ..awES ARE IN OH.S
TAP AT 20% OF TURNS fROM COLO END OF COIL
C·2pF/METER
Fig. 29-Gate·keyed oscillator using MOS FET IC.
82
Fig. 31- TV IF amplifier stage utilizing RCA-40820 MOS
FET IC.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ AN-4590
REVERSE
AGC
+5V
",
~--_4~~----------~~-o+I.V
R6
RCA
Rg
40244
Ct, C9•.C15 = Trimmer capacitor, 2 to 14 pF
C2. C7. C16 = Ganged tuning capacitors. each section". 6 to 19.5 pF
ca. C6. C14. C17. C22 = 2000 pF. ceramic
C4. C5'" 1000 pF. ceramic disc
ca. eta· O.OlIJF. ceramic disc
eto = 3.3 pF, NPO ceramic
C.ll = 270pF
et2"" 500 pF. ceramic disc
et3 = 3 pF. NPO ceramic
eta =68 pF. ceramic
C20'" 50 pF. ceramic
e21 - 1200 pF. ceramic
L1 ,. antenna coil; 4 turns of No. 18 bare copper wire; inner diameter,
9/32 inch; winding length. 318 inch; nominal inductance.
O.86,uH; unloaded Q. 120; tapped approximately 11/4 turns
from ground end; antenna link approximately 1 turn from
ground end
L2
L3
;a
=
r1 interstage coil; same as L1 antenna link
rf choke. 1 JlH
L4
oscillator coil; 3 1/4 turns of No. 18 bare copper wire; inner
diameter. 9/32 inch; windi'lg length, 5/16 inch; nominal
inductance, O.062,."H, unloaded Q, 120; tapped approximately
1 turn from low end
Rl. R10 = 0.56 meBohm. 0.5 wall
R2 = 0.75 megohm. 0.5 wall
R3 =0.27 megohm. 0.5 wall
R4. R13 = 270 ohms. 0.5 wall
R5 • 22000 ohms. 0.5 watt
R6 = 56000 ohms. 0.5 watt
R7 "" 330 ohms, 0.5 watt
R8. R12 = 0.1 megohm. 0.5 watt
R9 = 4700 ohms, 0.5 watt
Rll = 1.6 megohms, 0.5 watt
Tl = first if (10.7 MHz) transformer; double·tuned with 90 per cent
of critical coupling; primary: 15 turns of No. 32 enamel wire,
space wound at 60 turns per inch on O.25·by-O.S-inch slug;
secondary: 18 turns of No. 36 enamel wire, close wound on 0.25by-O.25 inch slug; both coils wound on 9/32-inch coil form.
::z
Fig. 32-FM tuner using RCA·40822 and RCA-40823 MOS FET IC's for the rf amplifier and mixer stages.
~Oy
I
21 K
47 K
I.S K
I
I
I
L ___
,OoO ~----1000
1000
' -__-'V36vK\.-....____.:;,12"'0>AK;-___-+___ ~ge
"Ferrite bead (4); Pyroterric Co. "Carboni J" a = 3N187
0.09 in. 00: 0.03 in. 10; 0.063 in. thickness_ .,. Disc ceramic
All resistors in ohms
• Tubular ceramic
All capacitors in pF
Cl = 1.8-8.7 pF variable air capacitor: E.F. Johnson Type 160-104,
or equivalent.
C2 = 1.5-S pF variable air capacitor: E.F. Johnson Type 160·102, or
equivalent.
C3 = 1-10 pF piston-type variable air capacitor: JFo Type VAM-Ol0;
Johanson Type 433S. or equivalent
C4 =0.8-4.5 pF piston type variable air capacitor: Erie 560-013 or
equivalent.
L1 = 4 turns silver-plated 0.02-in. thick, 0.07S-0.085-in. wide, copper
ribbon, internal diameter of winding = 0.25 in., winding length
approx. 0.08 in.
L2 = 4% turns silver-plated 0.02-in. thick, 0.085·0.095-in. wide,
5/16 in. I D. Coil = .90 in. long.
Fig. 33-200-MHz amplifier usjng the RCA-3N1S7 MOS FET IC.
83
AN-4590 ___________________________________________________________
1000 pF
820K
RFC
~
AGe
'OK
v.
~
IOOQpF
1000 pF
J
,7~~~TI I
TRAPS
=
~
HI--............!--.JI-O
IZOK
1000
FROM~
RF
AMP
,F
'90"
9pf
~
IF
MIXER
12 pF
OUT
0--I1----<4---+hll~
(0'
39
,F
~
,,'
'"
'"
Fig. 34- Typical circuits using protected dual-gate MOS FET
IC's in a TV tuner for la) rf stage, Ib) mixer with rf on gate
" oscillator on gate 2; Ic) mixer with both rf and oscillator
on gates 1 and 2; Id) mixer with rf on gate 2 and oscillator
on gate 1.
Because the voltage on gate I is fixed. the effect of
applying AGe is to make the gate-to-source voltage drift in a
positive direction as a negative gate 2 (AGC) voltage is
applied. In these cases, as in the earlier IF system shown in
84.
Fig. 31, this circuit arrangement optimizes tuner performance for crossmoduiation. 2
The rf stage in Fig. 34(a) can work into any of the mixer
circuits shown in Figs. 34(b). (c). and (d).
___________________________________________________________ AN-4590
Fig. 34(b) is a mixer circuit arrangement with oscillator
injection into gate 2 and the rf signal applied to gate I. Fig.
34(c) utilizes gate I and gate 2 as the input elements for both
rf signal and oscillator. Fig. 34( d) shows the rf signal applied
to gate 2 and oscillator injection on gate I.
Each of the above circuit arrangements has its own
desirable characteristics, and the subject of mixer performance deserves a much more detailed discussion than can be
accommodated here. In this context it is intended to
demonstrate feasibility in terms of circuit arrangements.
A milCer circuit with compo".,,! values used in the
laboratory for measuring conversion power gain from 200 to
44 MHz is shown in Fig. 3S. 8
Protected dual-gate MOS FET's have been used in
applications operating at frequencies up to SOO MIIz. They
are useful in such uhf applications as rf amplifiers and mixer
circuits. For example, the RCA-3N200 has the capability to
proVide a typical rf power gain of 12.5 dB with 4.5-<1B noise
factor at . 400 MHz in a common-source configura tion
without the need for neutralization. A circuit with this
capability is shown in Fig. 36.
1--------,-------'
33 CER
1 LEADLESS
3N.00
,...
1 DISC·
•
1\
! 47~I
1.
OUTPUT
I
-=-
I
CER DISC.
re3 300
~
I
.....
t-+":\r'---~-~*~
I
I
INPUT
I
470 CERAMIC
TUBULAR
STANDOFF
RFe
OHMITE
K
1
I
1
Z460
I
I
I
I
1
L __ ~_(~(IOOO :;j,.._L ___ _ ~_..J
1-....j~
_ _ _ _ _ _ _ _.., VDS
.f15V
AU resistances in ohms
AU capacitances in pF
Cl. C2 '" 1.3-5.4 pF variable air capacitor: Harnmerland Mac 5 type
or equivalent
C3'" 1.9-13.8 pF variable air capacitor: Hammerland Mac 15 type
or equivalent
C4 .. Approx. 300 pF - capacitance formed between socket cover &
chassis
C5 '" 0.8-4.5 pF piston type variable air capacitor: Erie 560·013 or
equivalent
Ll. L2 = inductance to tune circuit
Fig. 36-Using the RCA-3N2oo MOS FET IC in a 4(J().MHz
amplifier.
... Disc. ceramic .
• Tubular ceramic.
All resistors in ohms
All capacitors in pF
Cl. C2 = 1.5-5 pF variable air capacitor: E.F. Johnson Type 160-102
or equivalent.
C3 = '-10 pF piston-type variable air capacitor: JfO Type VAM·Ol0.
Johanson Type 4335. or equivalent.
C4"" 0.9-7 pF compression-type capacitor:
equivalent
ARea 400 or
L 1 .. 5 turns silver-platea 0.02" thick. 0.07" ·O.OS" wide oopper
ribbon. Internal diameter of winding"" 0.25"; winding length
appro". 0.65", Tapped at ,·1/2 turns from Cl end of winding.
L2 = Ohmile Z·235 AF choke or equivalent.
L3 = J.W. Miller Co. '4580 0.1 ,uH AF choke or equivalent.
NOTE:
If SOn meter is used in place of sweep detector. a low pass
filter must be provided to eliminate local oscillator voltage
from load.
Fig. 35-Mixer circuit for 200 MHz-to-44 MHz conversion,
using the RCA-40821 MOS FET IC.
CONCLUSIONS
The preceding discussions outlined numerous practical
applications that utilized the unique technical features of the
RCA protected dual-gate MOS FET IC. A summary of these
technical features includes:
I. Wide dynamic range - MOS FET IC's will handle both
positive ancj negative signal excursions.
2. Crossmodulation and spurious response performance is
inherently better than with other active devices such as
bipolars and single-gate FET's.
3. The very low gate-leakage permits AGC circuitry with
virtually no power requirements.
85
AN-4590 ________________________________________________________
4. Two input control elements make the device adaptable for
mixers, remote-<:ontrol gain circuits, coincidence gate
circuits, etc. The device can also function as a triodeequivalent when the two gates are connected to a single
terminal.
5. An exceptionally high transconductance.
6. Negative temperature coefficient for drain current, so that
thermal runaway is virtually impossible.
7. Extremely low feedback capacity, typically 0.02 picofarad; this means very low oscillator"feedthrough froin the
mixer stage back to the antenna.
8. The low feedback capacity enables the dual-gate MaS FET
IC to provide good rf power gain in common-source
amplifiers without the need for neutralization.
9. In addition to the above features, the new MaS FET IC
provides protection against static electricity discharges
encountered during handling and/or in circuit applications.
This protection was achieved with insignificant compromises in overall device performance.
86
BIBLIOGRAPHY
I S.R. Hofstein and F.P. Heiman, "The Silicon Insulated
Gate Field-Effect Transistor", Proc. I.EEE, Vol. 51, No.9,
pp. 1190-1202, September, 1963.
2 E.F. McKeon "Crossmodulation Effects in Single Gate and
Dual Gate MaS Field Effect Transistors" RCA Application Note AN-3435.
3 S. Reich and L.S. Baar, "A Comparison of Solid-State and
Electron Tube Devices For TV-Receiver RF and IF
Stages." IEEE Transactions on Broadcast and TV Receivers, Vol. BTR-I3, pag. 41, April 1967.
4 J.R. Burns, "High Frequency Characteristics of Two
Insulated Gate Field Effect Transistor" RCA Review, Vol.
XXVIII No.3, Sept. 1967, pp. 385417.
5 3N187 Data Sheet, RCA File #436.
6 3N200 Data Sheet, RCA File #437.
7 S. Reich, "MaS FET Biasing Techniques," EEE, Sept. 1970.
8 L.S. Baar, "RF Applications of the Dual Gate MaS FET
Up to 500 MHz" RCA Application Note AN443 I.
[Rl(]5LJD
Linear Integrated Circuits
Solid State
Division
Application Note
ICAN-5015
Application of the RCA CA300a and CA3010
Integrated-Circuit Operational Amplifiers
BY
A. J. LEIDICH
The RCA CA300S and CA3010 Operational Amplifiers
are silicon monolithic integrated circuits designed to operate from two symmetrical low- or medium-level dc power
supplies (at supply voltages in the range from ±3 volts to
±6 volts). The power dissipation in the amplifiers ranges
from 7.0 milliwatts to 92 milliwatts depending upon the
supply-voltage level and the desired output-power level.
The amplifiers are primarily intended to operate with externally applied negative feedback; however, they may also
he operated successfully under open-loop conditions. The
main features of the CA300S and CA3010 Operational
Amplifiers are listed below:
• All-monolithic construction designed to operate at
ambient temperatures from -SS'C to +12S·C.
• Built-in temperature compensation which assures that
the gain and dc operating point are stable over the
temperature range of -SS'C to +12S·C.
• Capability of operating at extremely low dissipation
and supply-voltage levels, as well as at medium levels.
• Balanced differential-amplifier input configuration and
a single-ended output configuration.
• No shift in the dc level between the differential inputs
and the output.
• Little effect on the input offset voltage from variations
in the power-supply voltages.
The CA300S Operational Amplifier is supplied in a 14terminal flat-pack; the CA3010 Operational Amplifier is
supplied in a conventional 12-terminal TO-S package. With
the exception of the differences in their package construction, the two operational amplifiers are identical. This note
describes the circuit arrangement, lists the performance
characteristics. explains the major design considerations,
and discusses typical applications of the operational amplifiers.
CIRCUIT DESCRIPTION
Fig. I shows the schematic diagram of the CA300S or
the CA3010 Operational Amplifier. The numerals shown
alongside the circuit terminals indicate the terminal designations for the CA300S 14-terminal flat-pack and CA3010
12-terminal TO-S package. The numerals enclosed in
squares are the designations for the CA3010 package. The
diagram in the uppeF right corner of the figure shows the
orientation of the terminals on the CA300S flat-pack; the
diagram at the lower right corner shows the orientation on
the CA3010 TO-S package. (The number designations used
to refer to specific terminals in the following discussion, or
elsewhere in this note, are those for the CA300S 14terminal flat-pack. The corresponding terminals on the
3-70
87
ICAN-5015 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CA30lO 12-terminal TO-5 pacicage can be determined from
the schematic in Fig. I.)
As shown in the schematic. diagram, each operational
amplifier consists basically of two differential amplifiers
@
the second differential amplifier is provided by current-sink
transistor Q,. Compensating diode D, provides the thermal
stabilization for the second differential amplifier and also for
the current-sink transistor, Q" in the output stage.
v+
0
•
5
'·
13
12
~
9
CA3008
14-TERMINAL FLAT-PACK
Note: RIO and RI3 not used.
CA30IO
12-TERMINAL To-S PACKAGE
Fig. I-Schematic diagram of the CA3008 or CA30IO Integ"';ted-Circuit Operational Amplifier.
and a single-ended output circuit in cascade. Circuit elements are also included to provide thermal stabilization
and to compensate for shifts in the dc operating point. In
addition, negative feedback loops are employed to cancel
common-mode signals (Le., error signals developed when
the two inputs to the operational amplifier are in phase
and of equal amplitude).
CASCADED GAIN STAGES
The pair of cascaded differential amplifiers are responsible for virtually all the gain provided by the operationalamplifier circuit. The inputs to the operational amplifier
are applied to the bases of the pair of emitter-coupled
transistors, Q. and Q" in the first differential amplifier.
The inverting input (at terminal 3) is applied to the base of
transistor Q.. and the noninverting input (at terminal 4) is
applied to the base of transistor Q.. These transistors develop the driving signals for the second differential amplier. A de constant--current-sink transistor, Q., is also
included in the first stage to provide bias stabilization for
transistors Q, and Q,. Diode D, provides thermal compensation for the first differential stage.
The emitter-coupled transistors, Q. and Q.. in the second
differential amplifier are driven push-pull by the outputs
from the first differential amplifier. Bias stabilization for
88
COMMON-MODE-REJECTION FEEDBACK LOOPS
Transistor Q, develops the negative feedback to reduce
common-mode error signals that are developed when the
same input is applied to both input terminals of the operational amplifier. Transistor Q, samples the signal that is
developed at the emitters of transistors Q. and Q•. Because
the second differential stage is driven push-pull, the signal
at this point will be zero when the first differential stage
and the base-emitter circuits of the second stage are
matched and there is no common-mode input. A portion
of any common-mode, or error, signal that appears at the
emitters of transistors Q. and Q. is developed by transistor
Q, across resistor R, (the common collector resistor for
transistors Q .. Q" and Q,) in the proper phase to reduce the
error. The emitter circuit of transistor Q, also rellects a
portion of the same error signal into current-sink transistor
Q, in the second differential stage so that the activating
error signal is further reduced.
Transistor Q. also develops feedback signals to compensate for dc common-mode effects produced by variations
in the supply voltages. For exampie, a decrease in ihe de
voltage from the positive supply results in a decrease in the
voltage at the emitters of transistors Q. and Q•. This ne~
tive-going change in voltage is rellected by the emitter circuit of transistor Q. to the bases of current-sink transistors
Q, and Q •. Less current then flows through these transistors.
The decrease in the collector current of transistor Q, results in a reduction of the current through transistors Q.
ICAN-5015
and Q" and the collector voltages of these transistors tend
to increase. This tendency to increase on the part of the
collector voltages partially cancels the decrease that occurs
with the reduction in the positive supply voltage. The partially cancelled decrease in the collector voltage of transis·
tor Q, is coupled directly to the base .of transistor Q. and
is transmitted by the emitter circuit of this transistor to the
base of output transistor Qln. At this point, the decrease in
voltage is further cancelled by the increase in the collector
voltage of current-sink transistor 00 that results from the
decrease in current mentioned above.
In a similar manner, transistor Q;; develops the compensating feedback to cancel the effects of an increase in the
positive supply voltage or of variations in the negative supply voltage. Because of the feedback stabilization provided
by transistor Q" the CA3008 and CA3010 Operational
Amplifiers provide high common-mode rejection, have elI;cellent open-loop stability, and have a low sensitivity to
power-supply variations.
OUTPUT STAGES
In addition to their function in the cancellation of
supply-voltage variations, transistors Q~, QOI and Q,O are
used in an emitter-follower type of single-ended output
circuit. The output of the second differential amplifier is
directly coupled to the base of transistor Q.., and the emitter circuit of transistor Q. supplies the base-drive input for
output transistor Qw A small amount of signal gain in the
output circuit is made possible by the bootstrap connection
from the emitter of output transistor QlO to the emitter
circuit of transistor Qg, If this bootstrap connection were
neglected, transistor Qtl could be considered as merely a dc
constant-current sink for drive transistor Q.., Because of
the bootstrap arrangement, however, the output circuit
can provide a signal gain of 1.5 from the collector of
differential-amplifier transistor Q, to the output (terminal
12). Although this small amount of gain may seem insignificant, it does increase the output-swing capabiJities
of the operational amplifiers.
The output· from the operational-amplifier circuit is
taken from the emitter of output transistor Q" so that the
dc level of the output signal is substantially lower than
that of the differential-amplifier output at the collector of
transistor Q,. In this way, the output circuit shifts the dc
level at the output so that it is effectively the same as that
at the input when no signal is applied.
Resistor R" in series with terminal 8 (refer to Fig. 1)
increases the ac short-circuit load capability of the operational amplifier when this terminal is shorted to terminal 12
so that the resistor is connected between the output and
the negative supply.
For this reason, the special parameters for which additional clarification may be necessary arc defined in an
appendix at the end of this note.
DC CHARACTERISTICS
The operational amplifiers are designed to operate from
two symmetrical de power supplies at supply voltages in
the range from ± 3 volts to ±6 vo1ts. For opcration with
±3-volt supplies, the power dissipation in the amplifiers
is less than 7.0 milliwatts with terminal 8 open or 23
milliwatts with terminal 8 shorted to terminal 12. When
±6-volt supplies are used, the dissipation level increases
to either 30 milliwatts or 92 milliwatts. depending upon
whether tcrminal 8 is open or shorted to terminal 12.
The input offset voltage for the operational amplifiers
is typically 1.1 millivolts for all symmetrical supply voltages. This parameter is relatively insensitive to variations
in the supply voltages. When ±6-volt supplies are used,
the variation in the input offset voltage with fluctuations
in supply voltage is typically less than 300 microvolts per
volt for either supply. For ±3-volt supplies, the variation
is typically 700 microvolts per volt. The offset voltage
varies slightly with temperature as shown in Fig. 2. (Fig. 3
1.7
POSITIVE DC SUPPLY VOLTS (VCC)- +6
NEGATIVE DC SUPPLY VOLTS (VEE). 6
.
~ Q7
~
~
O.
Q
-75
-~
-2~
2~
75
12~
100
92CS-13632
Fig. 2-lnput offset voltage as a function of temperature.
Vee
+6V
De
VOLTMETER
IRCA
WV-38A
OR
EOUIVALENT )
OPERATING CHARACTERISTICS
The operating characteristics of the CA3008 and
CA3010 Integrated-Circuit Operational Amplifiers are identical. The characteristics data given in the following paragraphs, therefore, apply equally to each type. A proper
evaluation of the capabilities of the operational amplifiers
requires a thorough understanding of the parameters in
terms of which the operating characteristics are expressed.
50
FREE-AIR TEMPERATURE (TFA)--C
NOTE: Pins 8 and 12 shoutd be shorted for the pertinent
92C,-13.0.
power dissipation measurement ONLY!
Fig. 3- Test circuit used to measure the input oUset voltage.
89
ICAN-5015
shows the schematic diagram of the special test circuit
used for the offset-voltage measurements.)
.
The input bias current and the input offset current of
the amplifiers are typically 5.3 microamperes and 0.54
microampere, respectively, when ±6·voU supplies are
used. Figs. 4 and 5 show the variations in these parameters
with temperature.
POSITIVE DC SUPPLY VOLTS Wee). +6
NEGATIVE DC SUPPLY VOLTS (VEE)- -6
POSITIVE DC SUPPLY VOLTS tVee)- +6
NEGATIVE DC SUPPLY VOLTS lYEE}·-6
~~~~~~A~E:~~~A~ ~~~~,.
!II 70
I
-:.0
.0
Z
;;
"~
~~
-55-'
40
~
"'...
~"'''~'I'~
:>OG!
30
..g
..9
"
.el,11
'I'~
Ii!
~ ~,
60
.
...
IKA
r;,
20
0
II\\("~
I
z
_
'~.I.
125.../
?;
0.01
0.1
I
100
10
FREQUENCY (f) -
MHz
Fig. 6-0pen-Loop gain as a function of frequency.
-50
-2'
0
2.
50
15
100
POSITIVE DC SUPPLY VOLTSIVec)- +3
NEGATIVE DC SUPPLY VOLTS (VEEI--3
12.
R. -15 OHMS
T£RIIINAL No. I, [!]: OPEN
FREE-AIR TEMPERATURE (TFAI- 7
5
6
"~
5
TERMINAL No. B ~ SHORTED TO
~
..
:l
POSITIVE DC SUPPLY VOLTS (Vee)- +6
NEGATIVE DC SUPPLY VOLTS (VEE). - 6
FREE-AIR TEMPERATURE (TFN-Z5·C
TERMINAL No. 8 ~ OPEN
o
TERMINAL No. 12
IE
4
TERMINAL NO.8 (5) OPEN
7
..
I
:i
..
50
-75
r--..
r
I I
I I II
-~
2
•••
2
7
•
66
I
•
2
66
2
10
FREQUENCY (f)-MHz
• 6.
100
92CS-13482
Fig. 9-DiDerential and common-mode gain as a junction
of frequency at different temperatures.
100
125
ITERMINACfNo.8 OI'EN
TERMINAL No..!, SHORTED TO
,,\
;fii:' 6l--t-TERMlNI\L NO.12!--+-I-+I-".~M---j.-+~
.,
~~ 1---4---4_4-+4---+---I--I-4-I---4~-+-+-H
1\\
!~
\
,'-oJ 5
~~ 41--~---4~-+4_--+_--I--I-4-1---4_~+_+_H
\
.!~"
)c . .
POSiTiVE DC SUPPLY VOLTS (Yee)" +6
~o
NEGATIVE DC SUPPLY VOLTS (VEE). -6
~:;~;:!~ ~~~:EtiA6~~~ (TFA1·
n;
50
POSITIVE DC SUPPLY VOLTS (Vee)" +6
NEGATIVE DC SUPPLY VOLTS WEE). -6
FREE-AIR TEMPERATURE (T~4)"2!5·C
I
I
0.1
25
Fig. ll-Output-sw(ng capabilities as a function 0/ temperature.
-25f-COMMON-MODE GAIN
-50
0
92CS-13527
~~I'c?"~
a
co
g
-25
FREE-AIR TEMPERATURE (TFA)-OC
~~es.
z
!J
-50
0,..,
31--~---+~-I-+_--+_--I--~+--+_--+_+_H
2S·C
100
-.....
z
....
:.Iv
2
80
\
OU
=rC; 40
30
20
U
2
0.01
•• 6
0.1
..
.8
I
FREQUENCY {f 1 -
2
4
6 810
92CS-13481
POSITIVE DC SUPPLY VOLTS (Vee)· +6
NEGATIVE DC SUPPLY VOLTS (VEE)· -6
~5
0
680.1
2
4 6 8
FREQUENCY (f)-MHz
Fig. 12-0utpul-swing capabilities as a Junction of frequency.
~ I 60
..
iC
0,",
~o:
4
0.01
r--..
2
.
.6
2
10
.
FREQUENCY (f) • I kc/s
.8
100
MHz
92CS-13551
Fig. 10-Common-mode rejection as a junction 0/ frequency.
Output Swing: The operational amplifiers exhibit a maximum dynamic-swing capability of ±3.5 volts with terminal
8 open and of ±3.0 volts with terminal 8 shorted to terminal 12. The output-swing capability varies only slightly
with temperature, as shown in Fig. II. Fig. 12 shows the
variation in the output-swing capability with frequency.
Input and Outpnt Impedances: When the CA3008 or
CA30lO Operational Amplifier is operated from ±6-volt
supplies, it has an input impedance of 14,000 ohms at I
a
-'ni
-50
-25
0
25
50
75
100
125
FREE-AIR TEMPERATURE (TFA)-·C
9ZCS-Il:lZG
Fig. J3-lnput impedance as a function of temperature.
91
leAN-S01S
kHz and an output impedance of 200 ohms (terminal S
open) or 75 ohms (terminalS shorted to terminal 12). The
input impedance and output impedance of the amplifier are
affected by temperature as shown in Figs. 13 and 14. respectively.
POSITlVt:: DC SUPPLY VOLTS (Vee). +6
NEGATIVE DC SUPPL.Y VOLTS tYEE)- -6
FREOUENCY (f) • I kHz
CI
I
j
generalized inverting feedback configuration. and Fig. 16
provides the diagram and the equations for the noninverting configuration. In both configurations. the inputs are
returned to ground through dc paths that are effectively
identical. This condition is necessary for minimum offset
voltage (dc error).
Because the open-loop input capacitance of the operational amplifier is less than 10 picofarads. the frequency response is virtually independent of the drive source impedance. The input-impedance equations given in Figs. 15 and
16 indicate that this lack of dependenc.e is even more pronounced when the amplifiers are operated with negative
feedback.
R,
•
r--'1
r
I lol
I
I
L __ J
L
-7lI
-~
-25
0
~
25
7lI
100
125'
FREE-AIR TEMPERATURE (TFAI"':'-C
92CS-13~40
Z,
Z,
Zj
Fig. 14-Output impedance as a function of temperature.
= op_l.., lopu'llIpH.co
101 =
R,' z,l .. =O)/iZf.I ... =f1l
CIRCUIT DESIGN CONSIDERATIONS
The basic design equations for the CA300S or CA3010
Operational Amplifier in closed-loop circuits are summarized in Figs. 15 and 16. Fig. 15 shows the basic
schematic diagram and gives the design equations for the
Z,
d_.I.., Inpo' 100pHon..
AYol") = -~.., pl.
AYol .. ) II, < Zf) •
You,/Yln =
I, < Zf<
z.,. I,
= 1 < Zf/z,
You,/Vln )
10 = 101 ( - - AVol .. )
r--,
I lol I
r
I
I
z,
+
Voor
~
__ .J
L
Fig. 16-Noninverdng-/eedback configuration for
an operational amplifier.
"oor
PHASE COMPENSATION
R,
=optn..loop Input impedance
=open.loop output Impedance
Ayo (Col) =op... loop gain
Zi
lol
II, = Z,I .. = olll Zf I .. =0)
Vou " Vln
=
-I,
I, < IZf < z,)/AVol .. )
~ -Z,tZ,
Zin = Z, < II,tAVo( .. ll/lII ~ I,
10 = 101 (1 < Vou,/Vln)
• AVol .. )
~
0
Fig. 15-1nvertlng-ieedback configuration for
an operational amplifier.
92
Basically. phase compensation is used to alter the response of an amplifier so that a phas.e shift of ISO degrees
cannot occur at a frequency for which the loop gain is
unity or greater. A rule of thumb that will guarantee an
ac-stable amplifier is that at the intersection of the closedloop response with the open-loop response. the respective
slopes must have a difference less than '12 dB per octave.
With few exceptions (some of which will be covered
in the section on applications). phase compensation must
be accomplished by altering the open-loop rC5ponse of the
operational amplifier itself. One of the advantageous features of the CA3008 and CA3010 Operational Amplifiers
is that small values of capacitance properly added to the
amplifier circuit will provide the required phase compensation. When ±6-volt supplies are used. two phasecompensating networks. each of which consists of a 27picofarad capacitor in series with a 2000-ohm resistor.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ICAN-5015
connected between terminals 1 and 14 and between ter-
mina"ls 9 and 10, cause the amplifier to roll-off at a slope
of one (6 dB per octave) all the way to unity gain (where
it then breaks into a slope of two). This value of compensation is sufficient to stabilize the amplifier for all
resistive-feedback applications including unity gain. The
response for this value of phase compensation is compared
to the original open-loop response in Fig. 17. Although
the two compensating networks are sufficient to ac stabilize
the amplifier, they arc not sufficient to produce a flat
response (within ± I dB) for closed-loop gains below 15 dB.
Fig. 18 shows a plot of the capacitance required to produce
Phase compensation may
ally by adding a capacitor in
terminal 11 and ground. A
series with a 22·ohm resistor
also be effected conventionseries with a resistor between
O.02-microfarad capacitor in
is sufficient to ac stabilize the
CA3008 or CA30lO Operational Amplifier at resistive
c!osed-Ioop gains down to unity.
The required phase compensation depends upon the
feedback configuration and not upon the location of the
drive sourcc. Hence, phase-compensating networks that
provide sufficient compensation for a lO-dB noninverting
configuration also provide sufficient compensation for a
6-dB inverting configuration because the two feedback
configurations are idcntical.
POSITIVE DC SUPPLY VOLTS Wee)- +6
NEGATIVE DC SUPPLY VOLTS (VEE). - 6
SOURCE IMPEDANCE (R,) • I KG
60
III
40
3z
30
I
."
"'"~
g
OUTPUT-POWER MODIFICATIONS
r--...
r....
00
I.....
A choice of two output-power capabilities is provided
in the CA3008 and CA3010 Operational Amplifiers. The
output can be tailored to the specific load requirements
by leaving terminal 8 open and placing an appropriate re-
",n
I--~"',p
r....
sistor between terminals 6 and 12. The minimum safe value
of load resistance (including the aforementioned resistor)
is 200 ohms when ±6-volt supplies are used. In determining
the output capability, it should be kept in mind that the
feedback network can contribute to the output loading
"'~-+-I\"'''''
+~.- ~
1-"':
20
.
:I'~
~
10
especially in the lower-gain configurations.
0
-K!
0.01
2
4
.8
0.1
2
•• 8
FREQUENCY etl -
2
4 .8
4
2
10
.8
100
MHz
92CS-I'5Ut
Fig. 17-Open-loop gain as a function of frequency lor both
phase-compensated and uncompensated operational amplifiers.
7C
DC COLLECTOR SUPPLY VOLTS (Vee) • +6
DC EMITTER SUPPLY VOLTS (YEE) • -6
FREE -AIR TEMPERATURE eTFA! • 25°C
TERMINAL No. B OPEN.
APPLICATIONS OF THE
OPERATIONAL AMPLIFIERS
The CA3008 and CA30lO Integrated-Circuit Operational Amplifiers can be adapted for us~ in a variety of
diverse applications. For example, the amplifiers 'may be
operated to provide the broad, flat gain-frequency response
required for video amplifiers or the peaked responses re-
quired for various types of shaping amplifiers. Other applications of these amplifiers include comparators, integrators,
differentia tors, and summing amplifiers. The following
paragraphs describe the circuit arrangements and the performance characteristics of the operational amplifiers in
such applications:
VIDEO AMPLIFIERS
When the feedback is applied through a purely resistive
network and suitable phase compensation is employed, flat
10
o
10
20
30
CLOSED-LOOP NON-INVERTING VOLTAGE GAIN-dB
o
6
19.1
29.7
CLOSED-LOOP INVERTING VOLTAGE GAIN -dB
40
40
9ZCS~13523
Fig. 18-Amount of phase-compensating capacitalice required
ta obtain a flat (± I-dB) gain response as a
function of frequency.
gains are aUainable from the operational amplifiers. Fig.
19 shows a 30-dB noninverting configuration of a video
amplifier, together with the closed-loop response of the circuit. The phase compensation is provided by as-picofarad
capacitor in series with a lO,OOO-ohm resistor. This arrangement provides the required amount of compensation, as
gain. The capacitors must have a resistor in series with
predicted in Fig. 18. (For purposes of comparison, the
uncompensated response of the 30-
20
~
10
,~
0
10
0.1
IK
lOOK
-6'
100
FREQUENCY- MHz
Fig. 19-Noninverting configuration and closed-loop response
0/ an operational.ampli/ier type 0/ video amplifier that provides
a gain of 30-dB•
• 6.
70
.i
IK
60
50
z
C
...co
~
!:;
0
40
NO COMPENSATION30
>
20
10
-6'
I.
30te
0
0.01
~
10
0.1
100
FREQUENCY- MHz
Fig. 20-Circuit diagram and gain-frequency response of the 30-d8 noninver,;ng video amplifier operated without pluue
compensation.
94
ICAN·5015
-6V
I"
10
60
CA300B
I;j
~
~
0
.0
40
30
>
20
\'-1'
\
-6V
10
I"
0
0.01
10
0.1
100
FREQUENCY-MHz
1.8 pF
Fig. 21-Circlfit diagram and gain-frequency response o/the 30-dB video amplifier when the phase compensation is accomplished by the addition 0/ a capacitor ilt parallel with the feedback resistor.
2"
_6V
10
.!
60
i"::
.0
~
;j
.'"
40
~
12)-+---{)
VOUT
~
>
'I'<
30
ItHlli
20-
CLOSED LORi
COMPENS~tfi~:--
10
III ;
0
III
am
19~~~, LOOP COMPENSATED
11111
11111
10
0.1
100
FREQUENCY-MHz
-6V
Fig. 22-Circuit diagram and response 0/ an inverting type 0/ operational amplifier used as a 6-dB video amplifier.
95
ICAN-S01S _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
2<
+6V
70
.
~
12}-+-----Q
VOUT
g
'"
~
0
60
~f'o.
50
V
40
30
I SLOPE
r..
OPEN LOOP COMENSATED
I-
>
20
CLOSED
~~P CDMPEN~~ED i'
10
0
111111111
0.01
~
11111111
10
0.1
100
FREQUENCY-MHz
-6V
Fig. 23-EDect of a decrease in the phase.compensating capacitance from 56 picofarads to 33 picofarads on the
response 01 the 6-dB video amplifier.
(Z,/Z,) to roll off at a one slope. Fig. 21 illustrates this
alternate technique for the 30-dB gain circuit.
The low-frequcncy input impedance of the 30-dB noninverting configuration is 480.000 ohms. as calculated from
the appropriate equation in Fig. 16 (Z, = 14.000 ohms).
Fig. 22 shows the configuration and the response of a
6-dB inverting type of video amplifier. The intersection of
the closed-loop characteristic with the compensated openloop response predicts the 3-dB bandwidth of the video
amplifier provided the transfer phase shift of the open-loop
amplifier is approximately -90 degrees. This relationship
suggests a way to extend the bandwidth without peaking. In the 6-dB video amplifier shown in Fig. 23, the
3-dB bandwidth has been increased from 5.6 MHz to 11
MHz by a decrease in the value of the phase-compensating
capacitors from 56 picofarads to 33 picofarads.
LOW·LEVEL PULSE
YIN" 3SmV
Your = 1.1V
Id= 40ft.
',"On.
tr;tf= 12On.
(.)
OVERDRIVEH PULSE
VIN" l.27V
Your = 3.2V
td=32ns
Because a broadband amplifier should. be capable of
handling digital signals. data were taken to determine this
capability. Figs. 24(a) and 24(b) illustrate the pulsehandling capabilities of the 30-dB noninverting circuit
shown in Fig. 19. Fig. 24(a) shows the low-level (nonsaturating) pulse response. The input is a 38-millivolt,
960-nanosecond pulse; the output is a 1.\-volt pulse having
a 40-nanosecond delay time. a zero storage time, and
125-nanosecond rise and fall times. Fig. 24(b) shows the
response of the amplifier for a 960-nanosecond input pulse
under 20-dB overdrive conditions. The output pulse has
an amplitude of 3.2 volts, a delay time of 32 nanoseconds,
a storage time of 160 nanoseconds, a rise time of 500
nanoseconds, and a fall time of 160 nanoseconds.
96
I. "160n.
',"SOOn.
1,=160"5
("
NOTE:
'd
Is
"
If
" D':LO\Y TIME
" STORAGE TIME
" RISE TIME
= FALL TIME
Fig. 24-Pulse-handling characteristics of the noninverting
30-d8 video amplifier: (a) Low-level pulse response;
(b) Pulse response under overdrive conditions.
ICAN-50l5
FREQUENCY-SHAPING AMPLIFIERS
These break-frequency equations are the precise equations derived from the gain equation in Fig. 16. The
The operational amplifiers may be used to create simple frequency-shaped characteristics, such as those assaciate'd with band-pass. notched-response, and single-tuned
narrow-band amplifiers.
Fig. 25 shows a noninverting amplifier that may be used
to synthesize the following peaked-response transfer function:
amount of phase compensation required is that shown
in Fig. 18 for a noninverting gain of 20 dB.
Fig. 26 shows the circuit configuration and the frequency response of a narrow-band, 100- kHz tuned amplifier. The circuit Q is 33.3. A true single-tuned response
can be obtained from only an inverting circuit configura-
tion, as shown by the gain equation for the two types of
configurations given in Figs. 15 and 16 and repeated
below:
I. For the inverting configuration. the gain equation is
given as:
where f, = 10 kc/s, f, = 40 kc/s, f, = 200 kc/s, and f,
= 800 kc/s.
In terms of the notations employed in Fig. 25, the breakfrequency equations for the amplifier may be expressed
as follows:
2rC,(R:~
VI"
2. For the noninverting configuration. the following
gain equation is used:
~=I+Z!Z
VIII
f .•
lOR,) = 10 kHz
2r~ ,R,
The "1+" term in the gain expression for the noninverting
configuration indicates that the gain of this type of circuit will never decrease to zero as required for a true
single-tuned response. The amount of phase compensation
required for the narrow-band 100- kHz amplifier is the
value given in Fig. 18 for an inverting gain of 0.0 (infinite
attenuation).
== 40 kHz
1
_rC"(R,,
+ R,)
= 200 kHz
40
ZrC"(40R,,
+ R,)
800 kHz
?
~=-z'/z,
.6V
Your
.,
40
iz
..::
~
30
!:i
0
>
:-
~~
r--.
20
-6V
10
Rr· 3oo
IC"
0.001
Rf·9K
0.01
0.1
10
FREQUENCY-MHz
A.
0.013 "F
I.
en
68 pF
Rn
2.7K
Fig. 25-Circuit diagram and response 0/ a noniuverling type of operational amplifier used 10 synthesize peaked-response
transfer functions.
97
ICAN-S01S _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
+6V
0 0 33.3
1\
11\
I \
II \
3.3 )(
16
16
CA300e
m
~
I
z
3.3K
g
w
II
~
0
>
"
12
10
/
,7
6
6
-6V
•
1.7mH
2
( TERMINALS
\
1\
17
/
0
35K
\
76
64
~.7.8.tI
92
100
108
FREQUENCY-kHz
OPEN)
"
116
124
1500 pF
Phase Compensation not shown. It is 62 pF in series with 820
n between terminals 1 and 14 and between terminals 9 and 10.
Fig. 26-Circllit diagram and response of an inverting type operational amplifier used
a narrow-hand lOO-kc/s tuned amplifier.
COMPARATOR CIRCUITS
The CA3008 and CA3010 Operational Amplifiers have
excellent transfer characteristics for comparator applications. As shown in Fig. 8. the ampJifiers have no observable
hysteresis effect; the trace (minus to plus) and retrace (plus
to minus) excursions coincide.
INTEGRATORS
The important design consideration when an operational
amplifier is to be used as an integrator is that dc feedback
be provided. This feedback is necessary so that an offset
(error) voltage cannot continuously charge the feedback capacitor until the amplifier limits. The required dc feedback
is normally provided by shunting the integrating capacitor
with a resistor so that the resulting time constant is con·
siderably longer than the periods for the frequencies of
interest. Fig. 27 shows the circuit configuration for the
use of the CA3008 or CA3010 Operational Amplifier as an
integrator and the responses of the circuit
fO.f
I-kHz square-
wave inputs. The dc gain of the circuit is limited to 20 dB
by the 39,OOO-ohm feedback resistor. The effect of this
resistor on the gain, however, becomes negligible for ac
signals at frequencies above 13 Hz because of the 0.03microfarad capacitor in parallel with it. The weighting
factor of integration for the eire:.;.:t i!; about 1 millisecond
(R
39,000 ohms; C
0.03 microfarad).
=
=
Phase compensation must also be provided in an integrating amplifier circuit to assure ac stability. In general, the
amount of compensation required is the maximum value
given by Fig. 18. because the closed-loop characteristic of
the integrator has rolled off completely at the frequency
where the intersection of the open-loop response and the
closed-loop characteristic occurs.
98
a~
DIFFERENTIATORS
The main problem in the design of differentiating amplifiers is that the gain of such amplifiers increases with
frequency; hence, they are susceptible to high-frequency
noise. The classical remedy for this effect is to connect a
small resistor in series with the input capacitor so that the
high-frequency gain is decreased. Actually, the addition of
the resistor results in a more realistic model of a differentiator because a resistance' is always added in series
with the input capacitor by the source impedance. The
schematic diagram of a CA3008 or CA30 10 Operational
Amplifier used as a differentiating circuit and the response
of the circuit for I-kHz square waves are shown in Fig.
28. A value of 51 ohms is selected for the gain-limiting
resistor to illustrate that the effect of the source impedance
is not necessarily negligible in differentiator applications.
This 51-ohm resistor limits the high-frequency numerical
gain factor of the amplifier to 433.
If the closed-loop gain of a differentiator rises to the
open-loop value before the open-loop response has started
to roll off, no phase compensation of the circuit is required. ]n order to assure that the intersection of the
closed-loop characteristic with the open-loop response occurs at a slope less than two, the RC time constant of the
phase-compensating network must be adjusted so that
the open-joop response does noi. ruli ull ill UIt:: region
of the intersection.
SCALING ADDERS
The inverting feedback configuration of the CA3008
and CA3010 Operational Amplifiers lends itself not --€:f-f--,-- OUTPUT
+Vcc
(b)
Fig.
(0)
~chemotic
diagrams showing supply-voltage connections 10 the CA300S or CA3006 for operation from either single or
dual power supplies: (aJ Differential-amplifier configuration operated from dual supplies: (b) DiDerential-amplifier configuration operated from a single supply,' (c) Cascade configuration operated from dual supplies; (d) Cascode configuration
operated from a single supply.
be added to the circuit, as shown in Figs. 4(b) and 4(d).
Tuned amplifiers that operate from dual supplies, such as
that shown in Fig. 4(a), require the least number of external
components.
For either single- or dual-supply operation, the operating
current of transistor Q. is determined by the bias voltage,
V'F., applied between terminals 2 and 3 on the CA3004 or
between terminals 8 and 12.on the CA300S and CA3006
(refer to the circuit diagrams in Fig. I). The more negative
terminal of the bias-voltage source must be connected to
terminal 3 on the CA3004 or to terminal 8 on the CA300S
and CA3006. In dual-supply systems, terminal 2 of the
CA3004 and terminal 12 of the CA300S and CA3006 are
usually returned to dc ground.
OPERATING MODES
For any given bia~ voltage V.., there are four possible
operating modes for the integrated-circuit rf amplifiers. In
general, each mode is characterized by (I) a distinct level
of operating current and corresponding transconductance,
(2) the degree of dependence of the operating current on
temperature, and (3) the way in which the transconductance
104
'
is affected by temperature. The operating points for the various modes are established by:
I. The emitter resistance selected for the constant-current-source transistor, Qa;
2. Whether the base-bias network includes the diodes
shown in Fig. 1.
3. The magnituae of the bias voltage, V.., applied to the
circuit.
Table I lists the required conditions for the four operating
modes, designated A, B, C, and D. The following paragraphs
describe the characteristics of the circuits in each operating
mode. The data are given for operation of the circuits from
symmetrical dual power supplies at three levels of dc supply
voltage (±3 volts, ±4.5 volts, and ±6 volts).
Fig. 5 shows the operating current for the various modes
as a runction~of temperature. Tfi,e current-temperature data
show that, in addition to the obvious shift in the level of
operating current, the dependence of the operating current
on temperature varies significantly with a change in the
operating mode.
When the diodes are included in the base-bias circuit
-----------------------------ICAN.5022
TABLE I
Required Conditions for Each Operating Mode of the CA3004, CA3005, and CA3006
Integrated-Circuit RF Amplifiers
Terminals Shorted
C..tJ005 or CA3006
Terminals Slzorted
In or Dut
Q·3
To
Terminal 3
To
Terminlll8
of
Bias Circuit
Emitter
Resistor(s)
5
4
4,5
4
5
4,5
C1300~
Operatjll~
.Mode·
A
B
C
D
Diodes
----
R,+Rb
+ R6
R,
R,
In
Out
In
Out
R,
"'For all modes, terminals 2, 6, and 12 of the CA3004 and terminals, I, 7, and 12 of CA300S
and CA3006 are grounded.
6.4
OPERATING MODE C
5 . 6 r - - -_ _ __
2.8
OPERATING MODE A
~ 4.8
2.4
uI
~
E
I
~
2.01---_ _ _ _ _ _ _ _ __
I
E
~
1.6r-----___,--_______ou_
a 1.2
-
u
t3 VOe
o
~
r - - - - -_________
~ 4.0r~6 VOe
0.8
:t4 . .5 VOe
! 3.2r-_______________
~
z
-.!'
g
2.41
e~
1.6
04
.t3 VOe
0.8
~~••~--~3.~--~
..--+--2~'~~4'~-f6.~~8~'-~10~5-~125
0-~5~5--.3~5,---~I5,--+---2~5,-~4~5--~6~5--~,b.--~I~__Tz5
TEMPERATURE _·C
TEMPERATURE _·C
(a)
(c)
OPERATING MOOE 0
:i6 VOC
1.2
2.4
OPERATING MODE B
~
E
~
e
1.0
I
u
:t 0.8
t6
voe
~
z
~ 06
a.
t.4.~~
1___----------------------------------
gOAl-"
I 2.0
r
J 6l----------------------------...:.==
~-
a I.Z
u
o
.oJ
~
I ___-------------------------------e~ O.2F-~~5<5~~3.--~-~..---+--t.2•.-~45--~6~5-~8~5-~1*'0•.-~125
TEMPERATURE--C
(b)
0.8
~
:: o.4L--------------------~~.·5~-t3•.---+.I5.-~.--~2~.--·4~.--~6~5---.~5,--,~~.-~125
TEMPERATURE _·C
(d)
Fig. S-Variation in the operating currents of the CA3004, CA3005, or CA3006 as a function of temperature for each mode of
operation.
105
ICAN-5022
(modes A ano C), the operating current, which is primarily
dependent on the temperature coefficient of the diffused
emitter resistor, tends to decrease with an increase in tern·
perature at a rate that is relatively independent of the bias
supply voltage VI·:". When the diodes are not used, however,
the shape of the current-temperature curves is dependent on
the magnitude of the supply voltage V"P.. The operating current then may remain constant or rise as the temperature is
increased, depending upon the value of Vfa:. The positive
supply voltages, shown in Fig. 5, have no effect on the operating current, and the current-temperature curves are not
changed by increases Of decreases in this voltage. Some deviation in the current-temperature curves is to be expected
because of normal variations in the absolute resistor values.
Fig. 6 shows the effects of different operating modes and
variations in temperature on the single-ended transconductance' of the CA3004. In general, when diodes are used in
*The single-ended transconductance is the incremental output current
for one collector of the differential pair of transistors divided by the
incremental input voltage. The curves shown of d":<; parameter are
obtained at an operating frequency of 1 MHz.
"'oZ
II OPERATING MODE C
FREQUENCY (fls I MHI
9 OPERATING MODE A
FREOUENCY Iflt I MHl
8
E
~
~
the base-bias network, the transconductance decreases with
increases in temperature. If the diodes are not used, the
transconductance may decrease, increase, or remain con~
stant as the temperature increases, depending on the value
of the negative supply voltage VEE. With the diodes out,
however, the collector operating point tends to shift when
resistive loads are used. In applications that require a stable
collector dc operating point, therefore, operating mode A
or C (diodes in) should be used.
Fig. 7 shows transconductance-temperature curves for
each operating mode of the CA3005 or CA3006, operated in
a differential~amp1ifier configuration.· These transconduct~
ance curves differ from those for the CA3004 shown in
Fig. 6 primarily because of the emitter resistors used in the
CA3004. For each operating mode, the operating points for
the differential-amplifier configuration of the CA3005 or
CA3006, as well as for the CA3004, provide a current in
each collector of the differential pair of transistors that is
equal to one-half that shown in Fig. 5.
In a cascade configuration of the CA3005 or CA3006, the
current through each part of the _common emitter-common
r-----------____
7
~~5'5~-~35~~-~,.~~~~2~5~-4~5~~65.--.8~5--"IO~5~~,25
~~'5~~-3~5o-~-~I.o-~o-~2"--'4~'---6t.5o--t.85~~IO~5--~'2'
TEMPERATURE-oC
TEMPERATURE-oC
(C)
(a)
OPERATING MODE 0
FREQUENCY (f I" IMHI
OPERATING MODE B
FREQUENCy (I)" I MHI
"'
g
i
8...~z
::
G
4~--------------
I
I
3b-__
________________ *4.,
VOe
------------------------------~.~3V~O~C
-
-i 3YDC
;;;
J
-~55--~-~~5.-~-~;5.-~.--oi~5--~4~~---6~'5C--t.M.-~1J~5--7,125
TEMPERATURE--C
(b)
Fig. 6-Variation in the single-ended transconductance of the CA3004 as a functl"on of temperature for each operating mode.
106
ICAN-5022
28
OPERATING MODE A
FREQUENCY(fI*IMHI
:t:6VDC
.:i.4.::iVDC
"
~~VDC
'0
~--~1~'-~--~~'--.~'~'6~'--~~'--'±0''-~''~'--~1!=-'
TEMPERATURE--C
~_~.·.~_~"~~_,.,--7--~~~-.~''-·'~'--~'''-~'~0''-~12~
TEMPERATURE-*C
------
~
~ 24
z6vnc
3
.... "",
= 16
~g 12
~ 20
_ _------------------:l:3VOC
~
~
~
~
-55
-;'5
-IS
25
45
65
TEMPERATURE-*C
..,PERATING MODE 0
FREQUENCYII!-IMHz
".
.
-------s
-i6YDC
4.5 VDC
_________________________________ •• wc
4
~ O~~~.-~--~--~,.~••~,--~••.--.~.~",o~.~T,,,~.--~
TEMPERATURE--C
Fig. 7-Variation in the single-ended transconductance 0/ the CA3005 or CA3006 in a differential-amplifier configuration as a
junction of temperature for each operating mode.
base cascode is equal to the total current shown in Fig. 5 in
each mode. Fig. 8 shows the transconductance-temperature
curves for each operating mode of the cascode circuit. These
curves show that, in general, the transconductance is highel
when the diodes are included in the base-bias network
(modes A and C) than it is when the diodes are not used
(modes B and D).
The power dissipation of the CA3004, CA3005, or
CA3006 is highest when the circuit is operated in mode C.
Table II shows power dissipation and the single-ended transconductance of the circuits for each operating mode. These
data may be used to determine the operating point that provides the highest value of transconductance per milliwatt of
circuit dissipation for given design conditions.
CHARACTERISTICS OF THE RF
AMPLIFIER CIRCUITS
Y PARAMETERS
In the design of rt and if circuits, the four-terminal blackbox short-circuit admittance parameters have become a
valuable tool. The determination of stability criteria, input
and output impedances as a function of load and source admittance, power gain, and voltage gain in iterative connections are all facilitated by a knowledge of the u y" parameters.
The "y" parameter curves presented in this section have
been calculated from a model and verified at several points
by measurements. These curves are a valuable aid in the
design of systems that use integrated circuits. The admittance curves are all generated for a quiescent operating current of 1.25 milliamperes in each of the transistors Q\ and
Q, in the differential-amplifier configurations and for a
current of 2.5 milliamperes in transistor Qa in the cascade
configuration. This operating current is obtained in the
operating mode D, as defined in the preceding section, with
supply voltages of ±6 volts.
The "yU parameters and their symbols are listed below:
1. Input admittance with the output voltage constant
y. = g, + jb.
where yl is the complex input admittance, gl is the' input
conductance and bl IS tne lOput susceptance.
107
ICAN-5022
TABLE
n
Relationship Between the Transconductance aDd the Power Dissipation of the
Inlegrated-circuit RF Amplillers in Each Operating Mode"
OpertJ/in,
Mod<
A
DC Suptlly
S.ngle-EIIIkd
Typ.oj
Circui!
VoIIlI,es
T,anscondud4nu
Power
DisrifHJIion
(..Us)
(miU'mlw.)
(m'U.V1/JUs)
CAJOO4
CAJOOS or CAJOO6
CAJOO4
CAJOOS or CAJOO6
=3
5.5
8.5
6.7
12.8
7.3
IS.0
6.6
6.6
15.0
15.0
25.0
2S.0
1.6
1.9
4.0
4.9
5.3
7.2
2.3
2.3
7.2
7.2
15.0
15.0
7.5
22.0
8.5
29.0
9.1
37.0
17.5
17.5
40.0
40.0
62.8
62.8
3.3
5.0
6.0
13.0
7.2
20.0
4.2
4.2
17.4
17.4
35.9
35.9
CA3OO4
CAJOOS or CAJOO6
B
C
D
=4.5
=6
CAJOO4
CAJOOS or CAJOO6
CAJOO4
CAJOOS or CAJOO6
CAJOO4
CAJOOS or CAJOO6
=4.S
CAJOO4
CAJOOS or CAJOO6
CAJOO4
CAJOOS or CAJOO6
CAJOO4
CAJOOS or CAJOO6
=4.5
CAJOO4
CAJOOS or CAJOO6
CA3004
CAJOOS or CAJOO6
CA3004
CAJOOS or CAJOO6
=4.5
=3
=6
=3
=6
=3
=6
"Circuits "'" operated in dillerentia1-amp1ifier conO.......tioDS. The tran.c:onductances and power
d/ssipatinno ohown are calculated valueo for nominal units.
2. Output admittance with the input vnltage constant
y. = g. + jb.
where y. is the complex output admittance, g. is the output
conductance, and b. is the output susceptance.
3_ Forward-transfer admittance with the output voltage
constant
yt= gt + jbt
where yt is the complex forward-transfer admittance, gt is
the forward-transfer conductance, and bt is the forwardtransfer susceptance.
4. Reverse-transfer admittance with the input voltage
constant
y. = g. + jb,
where y.. is the complex reverse-transfer admittance, g.. is
the reverse-transfer conductance, and b. is the reversetransfer susceptance.
A comparison of the parameters of the various possible
circuit configurations with those of the more familiar common-emitter parameters requires a second subscript to indicate the type of configuration being considered. Examples of
the use of the second-subscript notation are given below:
The common-emitter reverse-transfer admittance is writtenas
y•• = gn + jbn
108
The diJlerential-amplifier reverse-transfer admittance is
expressed as
yrDA.
=
grDA
+ jbrDA
The cascade-amplifier reverse-transfer admittance is given
as
Y,C"8 = grCAS
+ jbrcAs
Tbese cumbersome second subscripts will not be used
when the type of circuit for wbicb the parameter is given
is clearly indicated by an illustration or a descriptive phrase
in the text.
In general it is valuable to understand the essential differences between the "y" parameters of a regular commonemitter stage and those of the compound stages, sucb as
differential and cascade amplifiers.
The differential amplifier, wben used at radio frequencies,
consists essentially of a common-collector stage that drives
a common-base stage. In comparison to the regular, common-emitter "y" parameters, the input admittance y. the
output admittance Y., andtbe forward transfer admittance
yt, are decreased, almost exactly, by a factor of two when
tbe differential-amplifier configuration is used.
The reverse-transier admittance yr is aisu It:5:6 for the
differential amplifier tban for the single transistor in the
common-emitter configuration. The ratio of the imaginary
term in tbe differential-amplifier admittance to that of the
single transistor is 1/140 at low frequencies and 1/10 at
100 MHz. Fig. 9 sbows the ratios of imaginary parts
------------------------------ICAN-5022
r
OPEJ;iATI~G
1)0
MODE C
FREOUEIIIC'l'(fj&IIIHI
'0. _ _ _ _ _
_,
OPERATING MODE A
FREQUENCYlf}-IIIHz
'
.*6 VCC
[
l_
i
~
:l:.6VDC
z4.5VDC
ri--350i-
~
;t4511DC
_ _ _ _ _ _ _ _ ;t)VDC
I
~40~
I
'OL
25
45
'0'
65
TEMPERATURE-'C
-55
_~_~....l __ .
-]5
-15
5
25
45
..J_.--L._ ... 1
65
85
105
L
125
I.
'45
TEMPERATURE-'C
OPERATING MODE a
FREQUENCY (II-IMHz
OPERATING '-lODE 0
fREQUENCYUlolMUz
30
I·I~··
_.4.5VOC Fl-----··'v
oc
.:l6VDC
~
30
~
u_
W
_
25
45
65
_
4
~
_
•
•
_
_
~
.-1_
----L_~ __L
85
TEMPERATURE-'C
TE\lPERATURE-'C
Fig. 8-Var;ation in the transconductance of the CAJ005 or CA3006 in a cascade configuration as a function of temperature for
each operating mode.
a
i
2
~
~ 100
Fig. 9-Ratio oj the real (conduc/ance) and the imaginary (susceptance) parts 01 the reverse-transfer admittance for a commonemitter stage to those for a diDerential~amplifier stage as a fUllction of frequency.
b .. /b.n. and real parts g••/g.DA of the reverse-transfer admittances as a function of frequency.
In the cascade configuration of the rf amplifier circuits, a
common-emitter stage drives a common-base stage. The
input admittance y. is, therefore, that of a common-emitter
stage. The forward-transfer admittance yt is that of a common-emilter stage times alpha. Because of the high-impedance drive source on the common-base stage, the output
admiltance y. is very low (0.06 x /0-' mhos) at low frequencies and is both negative and low at high frequencies.
Since the output admittance is low and may be negative, a
conjugate match cannot be obtained at the output. Practical
amplifiers arc possible however, provided that the sum
Yout + Y'oad is positive.
The reverse-transfer admittance yr for the cascade circuit is less than that for the single-stage commono..Cmitter
109
ICAN-5022 - - - - - - - - - - - - - - - - - - -_ _ _ _ _ _ _ __
circuit. The ratio of the imaginary terms of these admittances is 1/1200 at low frequencies and 1/35 at 100 MHz.
The ratios of the real parts and of the imaginary parts as
a function of frequency are shown in Fig. JO.
' ....
,
"
Q,.fg,cos
\
\
\
\
\
\
,
' ...... _---------
-zoo o.~,-jr_...........t;,7;0-j,--...........t;,i;0-,I--t-M;\n-t--........1nI
fREQUENCY-MHI
Fig. JO-Ratio of the real (conductance) and the imalfinary
(susceptance) parts of the reverse-transfer admittance
for a common- emitter slage 10 those tor a cascade
stage as a function 0/ frequency.
Although the y, is low for both the differential and cascade configurations, instability can occur in high-gain ampJitiers. A further consideration in high-gain circuits is that the
layout can contribute more feedback than the integrated
circuit. Shielding and layout therefore are of prime importance if proper advantage is to be taken of the low feedback of these circuits.
The computed y parameters for the CA3004 differential
amplifier are shown in Fig. II. The admittance parameters
for differential-amplifier operation of the CA3005 or
CA3006 are given in Fig. 12 and those for cascode-amplifier
operation of either circuit are given in Fig. 13.
VIDEO-AMPLIFIER CAPABILITIES
The CA3004, CA3005, and CA3006 integrated circuits
may be used as video amplifiers, as shown in Figs. 14(a)
and 14(b). A relatively.large number of external components is required, and the availability of internal-circuit
connections for these external components provides a large
degree of flexibility to the user with respect to such factors
as bandwidth, gain, power dissipation and peaking. In the
circuit shown in Fig. 14(a), R, should be equal to R, to
preserve the circuit balance, and C2 should be an adequate
bypass so that the noise factor and gain are not degraded.
For the cascode configuration shown in Fig. 14(b), C, is
an emitter bypass, and its reactance should be less than
1.5 ohms at the lowest video frequency to be handled.
In either cascode or single-ended differential-amplifier
configurations, the feedback is low. Each configuration provides good isolation from output to input; the high frequency performance therefore can be approximated from
the input and output parallel Rand C for a single stage or
from the total shunt Rand C between stages for an iterative
connection. The mid-frequency voltage gain can be computed from the familiar gooR,. product. As an aid to such
calculations, Table III gives the input and output parallel
Rand C and the absolute values of goo for the various circuits and configurations for operation at 1, 10, and 40 MHz.
For more precise, but more elaborate calculations, the "
parameters may ·be used for video-amplifier design.
NOISE PERFORMANCE
The noise -figure of the CA3004, CA3005 and CA3006
integrated-circuit rf amplifiers is a function of the de operating current and frequency, for both differential and cascode-amplifier configurations. The noise figure increases
both with an increase in current and with an increase in fre-
TABLE III
Input and Output Parallel RC Network, Transconductance, and Performance Data
for the CA3004, CA300S, and CA3006 Integrated-Circuit RF Amplifiers
VIDEO PERFORMANCE
(Simulated Iterative Connection)
Freq.
(MHz)
Input Parallel RC
Rin (ohms) Cin (pF)
Output Parallel RC
Rou. (o"ms)
CO"' (pF)
Transconductance, gm
(millimhos)
Higk-Freq. Mid-Band
Interstage 3-dB Point Voltage
RL (ohms) (MHz) Gain (dB)
CASCODE OPERATION (CA300S OR CA3006)
1
10
40
500
500
Isb
42
42
22
1
10
40
2500
IS00
670
16
13
10.5
1
10
40
6650
6650
2000
S
6.2
5.0
-1.67·X 10'
-1.67 X 10'
-6X 10'
3.0
3.0
3.0
7S
77
23
19.3
Measured
20
20.6
Calculated
150
5S
DIFFERENTIAL-AMPLIFIER OPERATION (CA300S OR CA3006)
10'
4 X 10'
2S00
4.0
4.0
7.6
20
20
IS.6
IS
19.5
Measured
16
20.0
Calculated
IS.4
17.2
Measured
15
IS.0
Calculated
500
DIFFERENTIAL-AMPLIFIER OPERATION (CA3004)
1.7 X 10'
10'
2 X 10'
6.5
6.1
6.S
7.S
7.S
7.6
Data obtained for circuits operated from ±6-volt dc supplies in operating mode D.
110
1000
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICAN-5022
COL.L.ECTOR CURRENT OF EACH TRANSISTOR
~1.2'
COLLECTOR CURRENT OF EACH TRANSISTOR;::I.25 mA
mA
~2
~
~I
~
~gC.I==F=~.~.9.~I.O~~~.~.~,~O~O~,~7-~~-+-7.~.~.OOO
oko,~r-~~E,.~o~~~~~,o~-r~ri~~-r~ri~,
FREOUENCY-MHz
FREQUENCY-MHI
(c)
(a)
I
COLLECTOR CURRENT
OF EACH TRANSISTOR
COLl.ECTOR CURRENT OF EACH TRANSISTOR stll.2!imA
~
~1.25mA
~IO
Yo· 90 + ib O
~8r---------'~1----~
g
~6
(0)
(b)
¥
3
COLLECTOR CURRENT OF EACH
TRANSISTORRSI,Z'mA
1,·101,. jb r
•eJ.
O•OO2
~~=;:;~~~T-~IO
IO~-r-7-r~~r-~
FREQUENCY-MHz
(e)
Fig. ll-Admittance characteristics of a CA3004 differential amplifier as a function of frequency: (a) Input admittance, y,; (b)
Output admittance, Yh' (c) Output susceptance, bo, above 10 MHz: (d) Forward-transfer admillance.
transfer admillance, Yr,
quency. For convenience, noise data were taken in a fixed
configuration as the negative supply voltage was varied. On
the data plots, the operating currents that correspond to the
various supply voltages arc included as a separate abscissa
to show that the noise figure is a direct function of operating current. Figs. 15 and 16 show representative noise-figure
data for tuned amplifiers in the differential and cascode
configuration, respectively. In each case, the input and out-
y/,'
(e) Reverse
put are tuned and the input is conjugately matched to a
50-ohm noise diode. Practically no change in noise figure
occurs with variations of the positive supply voltage V cc.
The curves in Figs. 15 and 16 show that, for optimum
single-stage noise performance, the operating current should
be low, which results in a low gain. Thus, in system applications of the tuned amplifiers, the operating current in each
stage should be adjusted to obtain the optimum overall noise
,111
ICAN-5022
8
~6 ..
COLLECTOR CURRENT OF EACH TRANSISTOR
~s-
'i-III +jb;
~l.2S filA
i
:::s 25
§
~~~~:~~~: CURRENT OF EACH TRANSISTOR::t:!I.Z5 inA
,
:201--------=_..,,--_
~
g
15
~
~ 10
€
(e)
(a)
COLLECTOR CURRENT OF EACH
TRANSISTOR'" 1.2'111"
0.02
/
TRANSISTOR ~ 1.251ft'"
/
I
/
~
/
u
1,0::1:
/
~
I
...
ID
-. ..
/
..... /
10.0
FREOUENCY- IIH.
',·V,+ jb,
2.~;;
/
bo/
0.1
0.2
COLLECTOR CURRENT OF EACH
I
'0.90+1 110
~
..
. ..
..
-0.01
1000
100.0
'---;---l.-+.~.-'--+"""""'.~."'.'"
0.1
1.0
-~I '--+--l.~.-!.-'-~--::
10
10
FREQUENCY-IiHa
100
(d)
(b)
'r·., + III,
COLLECTOR CURRENT OF EACH TRANSISTOR
+0.0003
~.I.25mA
+0.003
~
3+0.0002
i
~
i
~
+0000'
-b,
,
'0
FREQUENCY- MHz
(e)
Fig. 12-Admittance characteristics 01 Q CA3005 or CA3006 differential amplifier as a function oj frequency: (a) Input admit·
lance, y,; (b) Output admittance, YD," (c) Forward transfer admittance, YI,' (d) Reverse transfer conductance. gr;
(eJ Reverse transfer susceptance. hr.
figure by considering the gain and noise figure of the first
stage and the noise figure of the second stage. The operatingcurrent adjustment can be accomplished by a change in the
negative-supply voltage (VEE) or by means of the bias connections that are available.
Fig. 17 shows the noise figure as a function of the source
resistance for a CA3005 or CA3006 used as a differential
amplifier at an operating frequency of 12 MHz. The equa-
112
tion given in the figure can be used to predict liaise performance as a function of source resistance for dc operating
conditions. The load resistor R,. of the circuit is 2200 ohms
and RN = 800 ohms. (RN is the equivalent noise resistance).
COMMON-MODE REJECTION RATIO
The common-mode rejection ratio of a differential amplifier, defined as the ratio between the full differential gain
_________________________________________________________ ICAN,5022
l'1
~ 100
~
I
-;. eo
STAGE COLLECTOR CU./tRENT
~
2.5 mA
Ji"lIi+jbj
STAGE COLLECTOR CURRENT ~ 2.5 mA
Yf:9f+jbf
"
"
16
.... \
12
\
u
~
omo.,;--;,t--t--:.-::lF""l'=--t.--:-.-1;,,;1;0-7,-h.t-"Lio------t- _. H t100
0
~-20!;-O.l;--;t--i.rl.-;.r;)I.O,-+--i.--:-.",.7.;,o;--t,-T.--:-.-';,oilio,-1--t-.,.rt'lv,OO
FREOUENCY- .. H,
FREQUENCY-MHI
(e)
(a)
I0'2~'"
o
STAGE COLLECTOR CURRENT:= 2.15 mA
Jo. to +,beI
STAGE COLLECTOR CURRENT ~ 2.5 rnA
,r·j"
2.0
/200
~
I
J
z
IIr/
~
8 0.1
I
1.0
~
§
W
-b,
I
z
-I~LJ-j,.-t.-i6h.r'I-t--:.H6-l.-L'O-!-+H.L+---7."i--l-'~OOO
FREQUENCY -
UH,
~
~
I
I
100
I
(d)
(b)
Fig. I3-Admittance characteristics of a CA3005 or CA3006 cascade amplifier as a function of frequency: (a) Input admittance.
y,; (b) Output admittance, Yo,· (c) Forward transfer admillance, YI (d) Reverse trallsfer admittance, Yr.
+Vcc
RL
>--+--1I~PUT
c3
'oJ
(OJ
Fig. 14-Schematic diagrams showing the use of the integrated-circuit r/ amplifiers as video amplifiers: (a) CA3004 in a differential-amplifier configuration,' (b) CA3005 or CA3006 in a cascade-amplifier configuration,
113
ICAN-5022 - - - - - - - - - - - - - - - - - - - - - - - - - - 10
TABLE IV
Common-mode Rejection Ratio for the 1:A3004, CA300S, and
CA3006 Integrated-Circuit RF Amplifiers
INPUT CONJUGATELY MATCHED TO
son NOISE DIODE
~
CA3004
CA300S or CAJOO6
I
::! •
..
Operating frequency
Load resistance, RL
::>
;;:
...!!! 4
AI -SS"C
AIZS"C
AIIZS"C
102 dB
108 dB
98dB
WI dB
101 dB
107 dB
=
=
1 kc/s.
1000 ohms in each collector.
o
z
1·~F~RE~Q~UE~N~C=Y7.(I~I.7.,.~M="~.------------------~-----,
OL---~0~--~I.~,.~--~2~A----~.~~----~~1
,TOTAL DC, CURRENT!(Iccl-m~ - - - 1
2
4
6
8
ro
NEGATIVE DC SUPPLY VOLTS -
ViE
FiR. I5-Representative noise performance of the CA3004,
CA300;, or CA3006 operated in a differential-amplifier
configuration (operating mode D).
10
OPERATING MODE 0
INPUT CONJUGATELY MATCHED TO
50n NOISE DIODE
200
600
1000
1400
1800
SOURCE RESISTANCE (RS)-OHMS
Fig. 17-Noise figure of the CA300; or CA3006 in a
diDerential-amp/ifier configuration as a function
of the source resistance (operating mode D).
~6
;;:
...
i5z 4
0'L-----~0~--~1.2~2~--~2.+.4~--~.~.9----~5.35
~OTAl EMI~TER CURR~NT Q3-m,A
2
4
6
8
10
NEGATIVE DC SUPPLY VOLTS - VEE
Fig. 16-Representative noise performance 01 the CASODS
or CA3006 operated in a cascode~mplifier
configuration (operating mode D).
and the common-mode gain, is a useful performance characteristic. The common-mode rejection is a function of the
ratio of the impedance of the constant-current transistor Q,
to the load resistor. The common-mode rejection decreases
if the signal applied is large enough to saturate the constant-
Fig. 18 shows the single-ended common-mode gain'for the
CA3004, CA300S, and CA3006 as a function of frequency.
(Fig. 19 shows the method used to detennine the singleended common-mode gain.) The common-mode rejection
decreases with increasing frequency when the CA3004,
CA300S, and CA3006 are operated with a single-ended
output.
GAIN CONTROL
The gain of the CA3004, CA300S, and CA3006 circuits
may be controlled in either of two ways: (I) The negative
voltage applied to the base-bias resistor R. can be adjusted
to vary the current in transistor Q. or (2) A differential offset
voltage can be applied to transistors Q. and Q" In both
techniques, the gain-control voltage has a ground reference
in a two-supply system, and maximum gain is obtained at 0
volts. The first method provides greater gain-control range
but also requires more control voltage than the second
methud. Figs. 20 and 21 allow the typical gain control as a
current transistor. The maximum peak-to-peak input volt-
age, therefore, is a function of the supply voltages and the
bias connections of the constant-current transistor. The
common-mode rejection for a I-kHz signal is shown in
Table IV.
114
*SingIe--ended common-mode gain: The ratio of the change in the
~iJ:e;:s~~~~ ~U!~~~n';EI~~g:l1e~t:a~::1nfrg~in~~e~oft~:U!p~fi~jn£
multaneously to both inputs of the circuit, i.e .• single-ended common-
mode gain =/:lVln/AVollu as shown in Fig. 19.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ICAN-5022
DC GAIN-CONTROL VOLTAGE
TO BIAS NETWORK OF03-VOLTS
40
POSITIVE DC SUPPLY VOLTS· +6V
NEGATIVE DC SUPPLY VOLTS· -6V
30
-6
-5
-4
-3
-2
-I
RL·IOOOO
~---------
20
DIFF. GAIN
(SINGlE-ENDEDI
-10
-20
10
a
10
~20
I
z
~30
60
~
60~~--~.~.~.~--t-~.~.~.~~r--1.~.~.~
0.1
1.0
10
FREQUENCY-MHz
100
Fig. 18-Single-ended common-mode and diUerential-mode
gain. of the CA3004, CA3005, or CA3006
as a function of frequency.
Vee
+6V
____________________________-J-ro
Fig. 2O-Gain-control characteristics of the CA3005 or CA3006
as a function 0/ the de gain-control voltage applied
to the bias networ" o/transistor QJ.
Q3 bias networks are the same, the gain characteristics for
the CA3004 are nearly the same as those for the CA3005
and CA3006. Fig. 21 shows that in the offset method of gain
control the gain range is dependent on the polarity of drive.
For maximum gain-control range on a single-ended amplifier, the common-collector transistor should be cut off
(negative voltage applied to its base). Because of the emitter
resistors, R. and R" the CA3004 circuit will require more
dc voltage for the same gain reduction as the CA3005 or
CA3006, and the dc voltage required will be a function of
the initial operating current.
GAIN-CONTROL VOLTAGE (Veal-VOLTS
0.2
0.3
0.4
0.5
I~
VEE
-6V
SINGLE-ENDED COMMON-MODE GAIN· .o.vOUT/OvlN
Fig. 19-5chematic oj the circuit used to determine
the single-ended common-mode gain.
function of voltage for the CA3005 or CA3006 for the two
methods. Fig. 20 gives the gain-control characteristic for
the CA3005 or CA3006 when the gain-control voltage is
applied to the base-bias network of transistor Q•. Since the
-40
-50
-60L---------------------------------~
Fig. 21-Gain-control characteristics of the CA3005 or CA3006
as a function of the dc oDset voltage, Vu . applied to the
diOerential pair of transistors QJ and Q•.
115
ICAN-5022 - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ __
The maximum gain-control range that can be provided
by a reduction in the current of transistor Qa varies with
frequency as shown in Fig. 22. The maximum gain-control
range that can be obtained is dependent on the full gain
used, the circuit loading, and the external-circuit layout.
-20
OPERATING MODE 0
ferential-amplifier and cascode-amplifier configurations. The
amount of cross-modulation distortion is determined by the
two-generator method with the input of the circuit under
test driven from a 50-ohm source and with its output tuned
to the frequency of the desired carrier. The amplitude of
the undesired-carrier input voltage is that necessary to produce 10 per cent cross-modulation distortion for each
manually determined gain-control setting.
Differential-Amplifier Configuration 5 - The availability
of internal connection points make possible several methods
of gain control in differential-amplifier configurations of
the CA3004, CA3005, and CA3006 circuits. Only two of
these methods need be considered, however, to obtain an
adequate evaluation of the cross-modulation characteristics.
These include (I) the variation of the current in the con-
-BOI=O-""----=20::-..c:;.---4~O:----:6=O--:ao'=-..,."OO
FREQUENCY -
MHz
Fig. 22-Maximum gain control provided by variations
in the current through QJ as a junction of frequency.
A large part of the variation in the maximum gain control for the different circuits results from differences in the
initial gain of the various circuits. Capacitive feed through
appears less for the cascode than for the differential-amplifier configuration.
The following discussion of cross modulation describes
variations of the two gain-control techniques.
CROSS-MODULATION AND MODULATION
DISTORTION
Cross-modulation and modulation distortion are important considerations in the selection of an amplifier for use
in AM systems. Cross-modulation distortion refers to the
transfer of modulation from an undesired carrier to the
desired carrier by nonlinearities in the amplifier. Modulation
distortion is a change in the modulation on the desired carried caused by the same amplifier nonlinearities that produce
cross modulation. The two forms of distortion are rel,ated
by the following equation:
D,
K
V,':V,' =
3
8m : I
where D, is the per cent of distortion in the modulation on
the desired carrier (Le., the modulation distortion), K is the
per cent of cross-modulation distortion, V, is the amplitude
of the desired-carrier voltage at the input, V, is the amplitude of the undesired·carrier voltage at the input, and m is
the per cent of modulation of the desired carrier.
When D, and K are equal and m is 100 per cent, the ratio
of V, to V, is 1.64. In the following paragraphs, data are
given for only the cross-modulation distortion. The modulation distortion can be predicted from these data, however,
on ine basis uf ine relationship uf V 1 i.u V 2' For t:xample, in
Fig. 23, V, is given as 22 millivolts for a gain of 0 dB. The
value of V" then, is 1.64 x 22, or 36 millivolts.
Figs. 23 through 27 show the cross-modulation distortion
of the CA3004, CA3005, and CA30U6 integrated circuits as
a function of their gain-control characteristics in both dif-
116
stant-current transistor, Q" and (2) the use of an offset
voltage to produce an unbalance in the differential pair of
transistors, Q, and Q,.
Fig. 23 shows the cross-modulation distortion character-
istics of the CA3004, CA3005, and CA3006 with the differential pair of transistors balanced and with age applied
to the constant-current transistor. Because of the increased
linearity that results from the emitter resistors R, and R"
the CA3004 has improved cross-modulation characteristics
at high current. The interfering signal voltage required to
produce 10 per cent of cross modulation distortion is practically a constani over the entire age range for the CA3005
and CA3006. The value of the interfering signal voltage
(approximately 15 mv) for the CA3005 and CA3006 is
twice that calculated from the logarithmic transconductance
characteristic of a single transistor.
UNDESIRED CARRIER INPUT VOLTAGE-MILLIVOLTS RMS
:5
6
10
30
60
100
300
600
m-20
!
0-30
---CA3004
~
--CACfJcP605 OR
~-40
z
~
°-50
-60
"-.......... _ - - - - - - -
-70
Fig. 23-Gain control as a function of the input voltage from an
undesired carrier that will produce cross-modulation distortion
of 10 per cent for balanced differential-amplifier operation
of the CA3004, CA3005 and CA3006. The gain-control voltage is applied to bias network of the constant-current transistor.
Fig. 24 shows the cross-modulation distortion characteristic of the CA3005 and CA3006 when an offset voltage is
applied to control the gain. The improved cross modulation
performance at - 5 dB gain is coincident with an inflection
point on the curve of tranconductance as a function of input
offset voltage. This point occurs at an offset voltage of approximately 50 millivolts.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ICAN-5022
+6 V
volts is employed and age is applied to the constant-current
transistor. The introduction of the unbalance reduces the
-6 V
VBB
UNDESIRED INPUT VOLTAGE -MILLIYOLTS RMS
3610
I
o
FREQUENCY OF DESIRED
CARRIER. 12 tlHI
-to
F~~~~~ ?f6U:~~SIRED
OPERATING MODE 0
m
i
3060100
300
r
,'POSITIVE GAIN-CONTROL VOLTAGE. Vee
'"~I
-20
(AT TERMINAL II
-------
!-30
cross-modulation distortion to approximately 10 dB less
than that of the balanced circuit. This reduction in crossmodulation distortion, however, is accompanied by a decrease in gain of approximately 5 dB.
Cascode Configurations - Cross-modulation data for
cascade configurations of the integrated~ircuit rf amplifiers are given for only the CA3005 and CA3006 circuits.
because the CA3004 circuit is not designed for this type of
operation. When the C A3005 or CA3006 is operated in the
cascode configuration, gain control may be provided by
either of two methods: (I) A negative voltage may be applied
to the base of transistor Q, or (2) A negative voltage may
be applied to the base of transistor Q,.
In the first method, the gain is reduced by the application
of a negative-going voltage at terminal 12. As the amplitude
o! this voltage is increased to the value required to cut off
transistor Q:\. the gain of the circuit is decreased. The crossmodulation distortion characteristics for this type of gain
control are shown in Fig. 26. The cross-modulation characteristics are comparable to those of a single transistor
having a bypassed emitter resistor.
The cross-modulation distortion characteristics obtained
~
for the second method of gain control are shown in Fig. 27.
No improvement in cross-modulation characteristics over
those obtained for the first gain-control method are observed,
although the age range is greater.
~ -40
-'0
-GO
Fig. 24-00;11 control as a function of the undesired-carrier
voltage that will produce 10 percent cross-modulation
distortion for diDerential-ampli/ier operation 0/ the
CAJ005 or CA3006 when gain con/roJ is provided
by the application 01 an ooset voltage to the
differential pair of transistors.
The cross-modulalion performance is improved by the
offset of the differential pair of transistors. Fig. 25 shows
the cross-modulation data when an initial offset of 50 milliUNDESIRED CARRIER INPUT \/OLTAGE-MILUVOLTS RiotS
0'
3
6
10
30
60
100
300
MOOED
OF DESIRED CARRIER
F UNDESIRED CARRIER
V
VOLTAGE APPLIED TO
NII.l2
MIXER CAPABILITIES
The CA3004, CA3005, and CA3006 integrated circuits
may be used as mixers, modulators, and product detectors.
The schematic diagrams in Figs. 28(a) and 28(b) illustrate
the use of these circuits in mixer applications. The oscillator
input is injected at the base of transistor Q3 (because there is
no direct-hase connection available on the CA3004, a higher
oscillator drive voltage is required for this circuit); the rf
input is injected single- or double-ended to the bases of
transistors Q1 and.Q~. The use of a center-tapped inductor
for the output tuned circuit (double-ended) allows the common-mode signal of the oscillator to be balanced out so that
the oscillator will not overload subsequent stages, and provides carrier suppression for modulators.
The gain performance and generation of harmonics in
the CA3004, CA3005, and CA3006 mixer circuits are dependent on the amplitude of the oscillator drive signal and
the de bias. The expression for product detection or frequency multiplication in the CA3005 or CA3006 (collsult
Fig. 29) are determined as follows:
.=~~L
-60
Fig. 25-Gain control as a function ollhe input voltage
from an undesired carrier that will produce cross
modulation distortion of 10 per cent, for u
di/Jerenlial.umplifier configuration of the
CA3005 or CA3006 having a 50-millivolt
oOset and with the gain comrol voltage
applied 10 the bias network of the
conslant~current transistor.
ru
where e. is the output voltage, e, is the differential input
voltage, goo is the transconductance of the differential pair of
transistors (Q, and Q,), and ZL is the load impedance (total
between caneelars), For a balanced circuit, the transconductance is given by
(2)
The term I., is used to represent the collector current of
117
ICAN-5022 - - - - - - - - - - - - - - - - - - - - - - - - - - - UNDESIRED INPUT VOLTAGE-MILLIVOLTS RMS
I
o
-10
36
to
30
60100
300
FREQUENCY OF DESIRED
CARRIER. 12 MHz
FREQUENCY OF UNDESIRED
CARRIER· 16 MHI .
OPERATING MODE 0
-20
-'0
-40
-50
+6 V
-60
-6 V
-70
Fig. 26-Gain control 0/ the CAJ005 or CAJ006, in Q cascode configuration, as a function of the IIndesired-carrier voltage that
will produce 10 ~r cent cross-modulation distortion when the gain is controlled by a negative bias voltage applied to
the base of transistor Q, The schematic diagram illustrates the circuit configuration.
+6 V
-'0
-20
m
r
Q-30
~
a::. -40
z
~
-'0
-60
-6 V
-70
Fig. 27--Gain control of the CA3005 or CA3006. in a cascade configuration. as a function of the undesired-carrier voltage thai
will produce 10 per cent cross-modulation distortion when the gain is controlled by a negative bias voltage applied
to the base of transistor Q,. The schematic diagram illustrates the circuit configuration.
Fig. 28-Circuit diagrams for the use 01 the integrated--circuit rl amplifiers as mixers (operating mode D): (a) CA3004,' (b) CA3005
orCAJ006.
118
---------------------------------------------------------ICAN-5022
lFer
---
the e,e, product. The linearity of the CA3006 is illustrated
by the curve of the conversion transconductance as a func-
tion of the oscillator voltage, shown in Fig. 30. (Although the
curve is plotted on logarithmic paper because of the wiae
~
range, the relationship is linear.) The gain reaches a maximum value at approximately 2.5 volts rms. Because measurement inaccuracies prevent the use of this curve to
determine harmonic generation, spurious-signal measure..
pll~~
ments were taken on CA300S and CA3006 mixer circuits.
For these measurements, the rf input was untuned and
'he oscillator and if frequencies were held constant. For
a fixed amplitude of oscillator injection on terminal 3, the
rf was varied in frequency. and the amplitude of the responses was recorded. The results are shown in Table V.
The spurious signals generated are a function of oscillator
drive. A low oscillator drive (0.1 volt rms) produced only
three spurious signals for which the rejection was less than
70 dB down. These measurable spurious responses were
third-order products that involved the second harmonic of
either the oscillator or rf signal. The relative if gain increases
with decreasing oscillator drive because of lower mixer gain.
---'----+:1-::---'
qIff
Rf
Fig 29--Circuil diagram oj a CA3005 or CA3006
balanced mixer (operating mode D). The equation ..
derived for product detection or multiplication
are based on this circuit.
10
transistor Q3 and may be expressed as
10 = g~. e,
(3)
where gn'2 is the transconductance of transistor Q3 and e2 is
input voltage applied to transistor Q,. The output voltage,
eo, therefore is given by the foIlowing equation:
"q
eo = 2KT e, e. gm, ZL
(4)
Eq. (4) is a general expression for the output voltage of
the mixer having input signals e 1 and e 2 " With emitter degeneration in the constant-current transistor (Q3)' gm2 is
essentiaIly constant for a sufficiently large emitter current
(> I rna); the current 10, iherefore, foIlows the applied voltagee,.
When e 1 and e 2 are sinusoidal and g", is a constant, the
input signal voltages are given as foIlows:
el = EI ejw1t
* e+ EJ
(5)
(6)
With the substitution of these relationships, the equation
for the output voltage the CA300S or CA3006 now becomes
n
=
~ gm Z [E E ej(·,+·,l,
2KT
2 L
I'
o
'"
~
::i
I
~
2
~
lill
o
r
z
o •
~
U
j ",,\
* is the conjugate of E" and E,
* is the congugate of E,)
(E,
e
FREQUENCY (t I· 20 MHI
CONSTANT RF SIGNAL
CONSTANT LOAD (aoooa)
~
2
'-_.....,:--_.....,,---!--:!.....l.__-!-_ _-!-_-:---;-....
0.1
0.01
6
e 0.1
OSCILLATOR VOLTAGE-VOLTS RMS
6
B
I
Fig. JO-Conversion gain of a CAJOOS or CA3006 mixer circuit
as a function of the oscillator voltage.
+ E Ee-i(.,+.,l'j
I
•
+E
E e-j(·'-~)'j
+~
2KT'"«m , ZL [E I E.ej(·,-·,l'
-I 2
(7)
Eq. 7 gives the output voltage for a CA300S or CA3006
used as a product detector or multiplier. (Note that nnly the
two sideband frequencies are included in the output). The
requirements for product detectors or multipliers are that
the circuit should be biased in a linear region with a smaIl
signal voltage applied. Because aq gm./2KT is essentiaIly
constant, the gain of the mixer is determined from ZL and
The common-mode canceltation of the oscillator signal at
the collector outputs is indicative of the carrier suppression
that can be provided in modulators. The carrier suppression
is function of output tuned-circuit balance and the transistor offset voltage .. The contribution of the offset is illustrated in Figs. 31 and 32 which show the output signal as
a function of the offset voltage for the CA3004 and for
CA300S and CA3006 respectively. These data were obtained on circuits operated with a balanced output timed
to the oscillator frequency.
a
119
ICAN-5022
TABLE V
Response of a CA300S or CA3006 Mixer to Spurious Harmonics
Diff.-Freq.
Diff·-Freq.
Signal
Freq·.I.
Vou
Output (dB
aI/Mm.J
Frequency
(MHz)
(rm....Us)
relatil/e to
I. -I.)
fo - f~
Ilf
1.0
0.659
1.159
1.329
1.988
2.318
2.659
2.813
3.977
21. - f.
21. - 21x
2f:.: - 2£.
fJl: -f.
2£. - fa
21x - 3f.
f. - 21.
4.309
31. - f.
{:II: - 3E o
5.627
'5.977
41. - f.
f 0 = 1.659 Me/s; Vou
-=
Vote
OutPUI(dB
allerm.J
(rmsv.lls)
,elative to
I. -I.)
1
0
0.7
1
7.5
0.7
-53.1
1
0.7
-76.1
1
0.7
-75.5
1
0.7
1
0
0.7
-31.7
1
0.7
-79.6
1
0.7
1
-31.7
0.7
-35.8
1
0.7
1
-38.5
0.7
-38.9
0.7
1
oscillator injection voltage,
0
10
-53.1
0
-35
-
35
-59.3
-57
-63
Diff·-Freq.
You
Oulpul(dB
(rms ••Us)
relatioe to
I. -I.)
at term. 3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0
18
-54.9
0
-39.7
-39.7
-74.7
-74
Diff··Freq.
Output (dB
V ...
allerm.J relative to
(rms ••IIs) I. - f.)
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
.0.1
0.1
0.1
0.1
0
27
-52.3
0
-47.8
-47.8
All blank s _ indicate dilferenc:e-fRquency outpUl1DOl'O than 70 dB below the f. - f. output.
POSITIVE DC SUPPLY VOLTS (Vee )- +6
NEGATIVE DC SUPPLY VOLTS (VEE)·-6
FREQUENCY (f). 1.6 MH.
co
.
fj
4
II:
~
0
>
:J
0
> 100
8
i
I
....~
4
=
>
I-
~
I-
10
8
:>
0
0
a:
4
•
..u
::I
~
0
0
~1~.-j-1~2~-~'0~-~8~-~e-=-4~~~~~0~2~0~4~0~6~0~8~0~10~0~'20
DC OFFSET -
MILLIVOLTS
Fig. 3J-Caneellation of the oscilljltor signal at the output of a
CAJOO4 mixer os a function of the de offset voltag•.
UMITER CHARACTERI5flCS
CiH.nmiial-Amplifliri Cliiiifiiiiiiithm -
The
diffcrcnti;l~
amplifier. driven by a constant-current transistor, is probably
the optimum circuit configuration for bipolar transistor limiters. The advantage of such circuits in limiter applications
is that collector saturation of either transistor Q, or Q, can
be avoided because of the action of the constant-current
120
ro
~-'
IE
~
•
>
0
!;
!;
100
0
!:;
..
6
..
!:;
.
1.6 MHz
1:
...
..
e
:.
::;
-'
i
I
~
rnlOOO
8
IE
l:
FRE()UENCY Cf)
o
~
o
o
;100:
~
r
co
o
~~7~-6~-~5~-~4~-~3~-2~~-I~~0~1~0~2~0~30~4*0~&O~~.~0~70
DC OFFSET- MILLIVOLTS
Fig. 32-CanceUation of the oscillator signal at the output of a
CAJOO5 or CAJ006 m/Jeer as a function of the de offset voltage.
transistor Q,. Figs. 2 and 3 show typical limiting characteristics for the CA3004 and for the CA300S and CA30<.6
rc:;pcctivcly. Fer the Cl'.300S and C.A..3006 (ne emitter degeneration). "hard" limiting is achieved for a peak-to-peak
input of 300 millivolts for all values of totsl de current (Icc).
For the CA3004, the input voltage required for "hard" limiting is a function of Icc because of the linearizing effect of
the degenerative emitter resistors. R. and R,. As saturation
ICAN-5022
TABLE VI
Limiter Performance of a Differential Amplifier
Voltage Gain
With Emitter
Degeneration
Maximum
V Supply
(IJOUs)
(rnA)
Load
(ohms)
Maximum
Tuned
Load
(ohms)
0.5
1.0
2.0
3.0
12000
6000
3000
2000
24000
12000
6000
4000
lei
+ leI
RL
= Vsupply
leI
RL
gmRL
Resistive
+ Ie,
low~level
Degeneration
(dB)
Resistive
(dB)
Resistive
Load
Tuned
Load
Tuned
Load
31
28
25
22
37
34
31
28
.15
35
35
35
41
41
41
41
Load
Resistive Load
= 2 Vsupply Tuned Load
leI + Ie,
= voltage gain
must be prevented for good limiting, a maximum load resistor and
Voltage Gain
Without Emitler
voltage gain exists for a given
Ir.(~
and
positive supply voltage. Table VI shows the maximum resistor values and voltage gains usable for Vr.r. = 6 volts, for
the three circuit types. The low-level transconductance can
be obtained from the slope near the origin for the curves
shown in Figs. 2 and 3. The max.imum voltage gain is inde-
pendent of I,~ in the CA3005 and. CA3006 and is dependent
on I"r in the CA3004. Figs 5 through 8 show the 1"0 currents
and transconductance for optional operating conditions.
When the differential amplifier is used for limiting, the
emitter-to-base breakdown voltage for transistors Q, and Q,
cannot be exceeded without degradation in performance.
For the CA3004, CA3005, and CA3006, this voltage including a safety margin should not exceed 2.5 volts rms.
Either of two methods may be used to prevent this value
being exceeded: (1) Make sure the preceding stage limits
before the input voltage reaches 2.5 volts (maximum voltage
gain per stage approximately 20 dB), or (2) add one junction
diode (D,), as shown in Fig. 33 (this allows a maximum usable voltage gain consistent with good limiting and stability).
load). Limiting characteristics for both cases are shown in
Figs. 34 and 35. The data in Fig. 34 are obtained with
a collector load of 500 ohms. This limiting characteristic
is "soft" and is acceptable over only a 20-dB range. The
peak-to-peak voltage at the collector is never large enough
to cause saturation. The limiting characteristic shown in
Fig. 35 is obtained with a collector load of 5000 ohms, and
saturation of transistor Q 1 occurs. The limiting is harder and
covers a broader range, but severe tuned--circuit loading
occurs.
1.0
0.8
0.6
OPERATING MODE D
COLLECTOR LOAD-soon
FREQUENCYCf)-1.7MHz
OUTPUT MEASURED ACROSS 50.(1
en 0.3
:0;
'" 02
~
I
§!
0.1
... 0.08
~O.o6
g
50'"
§o.oz
-6V
O.O:,ko--"';I;;---t.4o;--;6!noc----;*'OO;-~20;k,;O-..
40ivo"6d;oo""'0;/;0"O-,·20;;/OO~-4:ut000
INPUT YOLTAGE-MILLlYOL TS RMS
Fig. 34-Limitilrg characteristics and circllit diagram
of a CAJOO5 or CA3006 cascade limiter hal'ing
a 500-ohm collector load impedance.
-VEE
Fig. 33-Circuit dial(ram of a CA3005 or CA3006 diDerentialamplifier limiter that uses a diode to provide
input overload protection.
Cascode Ampliliet - The limiting characteristics of the
CA3005 or CA3006, when used as a cascade amplifier are
dependent on the current limiting in transistor Q, or the
voltage limiting of transistor Q, (high-impedance output
APPLICATIONS OF THE RF AMPLIFIER
CIRCUITS
RF AMPLIFIER
Figs. 36, 37, and 38 illustrate the use of the CA3004, the
CA3005 or CA3006 differential-amplifier configurations,
and the CA3005 or CA3006 cascode configurations, respectively, as single-ended rf amplifiers. Adjustable matching
networks, derived from the y parameters, are included in
each circuit. The values of the adjustable components as
121
ICAN-5022 - - - - - - - - - - - - - - - - - - - - - - - - - - - Vee
+6 V
OPERATING MODE 0
COLLECTOR LOAD· 5000 .Q
OUTPUT
l/
FREQUENCY (f) • 1.7 MHz
OUTPUT MEASURED ACROSS 50
a
O'II.~O~-.!20;;----,4;i,O.-t..O"'IOO""--;;20"'O----;4;i;oo"60.!;;;O-;;,O;!;O"O"C2;;;O"'OO"4;;;O,i;OO"6000~con!,OOOO
INPUT VOLTAGE-MILLIVOLTS RMS
Fig. 35-Limitillg characteristics ana Circuit diagram of a CA3005 or CA3006 cascade limiter having a 5000·ohm collector load
impedance.
AGe
CIRCUIT ELEMENTS
L,
FREQUENCY
L,
(MHz)
(I:H)
C,
(pF)
(I1H)
C,
(pF)
.10
1.8-2.7
0.15-0.3
2-10
0.9-7
1.8-2.7
0.1-0.2
2-10
0.9-7
100
POWER GAIN PERFORMANCE
POWER GAIN
(dB)
DC
SUPPLIES
100 MHz
30 MHz
(volts)
12
24
±6
Fig. 36-Circuit used to determine the rf performance capabilities of a CA3004 integrated·circuit rf amplifier.
AGe
+ vee
CIRCUIT ELEMENTS
FREQUENCY
L,
(MHz)
(11H)
30
100
1.2-2
0.4-0.7
C,
(pF)
5·40
1-12
!p.H)
C,
(pF)
1.2-.1.
0.25-0.5
1.5-20
1-12
L,
POWER GAIN PERFORMANCE
DC
SUPPLIES
POWER GAIN
(dB)
(volts)
30 MHz
±6
±4.5
29
27.8
23.0
±.1
100 MHz
1R
16
!I.5
Fig. 37-Circuit used to determine the rf performance capabilities oj a CA3005 or CA3006 integrated-circuit rf amplifier in a
differential-amplifier configuration.
------------------------------ICAN-5022
AGe
+ Vee
.OOI5~OI5~
CIRCUIT VALUES
FREQUENCY
L,
(MHz)
(".Il)
30
100
0.3·0.6
0.07-0.12
L,
C,
(PF)
(p.ll)
C,
(pF)
14-150
5-40
0.8-1.4
0.15-..1
5-40
5-40
POWER GAIN PERFORMANCE
DC
POWER GAIN
SUPPI.lES
.OOI5~
(dB)
(valls)
30 MHz
±6
±4.S
±3
36
33
21.5
JOO MHz
20
18.5
15.0
Fig. 38-Circuit used to determine the rl performance capabilities of a CA3005 or CA3006 integrated-circllit rf amplifier in a
cascode configuration.
well as typical power gains are also shown in the figures. A
conjugate match at the input is provided for all configurations. A conjugate match at the output is impossible for the
cascade configuration
..5
!!:
10
Fig. 41-Frequency-response characteristics of the
12-MHz· limiting amplifier shown in Fig. 39 .
..
~~
FREQUENCY- MHz
.,
Fig. 44--Frequency-response characteristics 0/ the 12-MH:t
gain-controlled amplifier shown in Fig. 40.
.01,--+-"~,-;,C"-",,,--,.-!.-7,-;,~-7-7.-:,",;-'--':-""'-;,-:,"
I
10
100
1000
10000
RMS INPUT-MICROVOLTS
Fig. 42-Limiting characteristics of the 12-MHz
limiting amplifier shown;n Fig. 39.
50
INPUT SIGNAL 12MHz .30% MODULATED
DETECTOR OUTPUT FILTER BANDWIDTH
~
5.0 kHz
DETECTED SIGNAL
GAIN CONTROL
STARTED
."
DETECTED NOISE OUTPUT
i 8I
~ ~
8'
10
100
1000
INPUT SIGNAL-MICROVOLTS
Fig. 43-0utput signal-Io-noise ratio as
a fllllction of the in"lIt signal for the
12-MHz gaill-controlled amplifier shown in Fig.40
when gailL control;s used in ollly the first stage.
loooe
distortion and drive levels is readily established.
Feedback may cause oscillation or unbalance; care must,
therefore, be taken in the external-circuit layout design .
Shielding must also be provided for both the double-sideband
modulator and product detector.
The circuit diagram of the double-sideband modulator is
shown in Fig. 48. The modulating signal is. applied singleended to the differential pair of transistors, Qt and Q:!, and
the oscillator signal is applied to the base of transistor Q,.
The output is taken double-ended from the balanced transformer, T:!. The carrier suppression is a function of bilateral
symmetry (offset, output-transformer balance, and modulation drive circuits) and the modulation-to-carrier drive ratio.
With the external-circuit bilateral symmetry carefully preserved, the carrier output is approximately 25 dB below the
double-sideband output for CA3006 units (offset 2 I millivolt) operated with a drive v, = 10 millivolts rms and v, =
31.5 millivolts rms. Although the signal-to-carrier ratio of
25 dB represents an inadequate rejection for most systems
(40 to 60 dB is usually required), this value relaxes the filter
requirements from those necessary on more commonly used
single-sideband modulators. An improvement over the 25-dB
ratio is obtained if the modulation drive v t is increased and
the carrier drive v::! is decreased, because the output is a function of the product of VI and v,.
The circuit diagram for a product detector is shown in
Fig. 49. The product detector which provides the advantage
125
ICAN-5022
+6 V
'6 V
1.75MHr
Cf
T,
I
:6'i-'-"""t";,([H
2g~~,ctll~
-6 V
-6 V
(0)
I"
Fig. 45-Circuit diagrams for the use of CA3004, CA3005. and CA3006 integrated circuits as balanced mixers to convert an
input frequency of 20 MH z to an output frequency of 1.75 MHz.
NOISE FIGURE
M
~
w
~
U
OSCILLATOR DRIVE VOLTAGE AT TERMINAL No.3-VOLTS R M S
Fig. 46-Power gain and noise figure as a function of the oscillator drive voltage for the CA3005 or CA3006 balanced mixer.
+6V
OSCILLATOR fREOUENCY (lose)- 2L75MHz
INPUT SIGNAL FREOUENCY(I,tl" 20MH.
INTERMEDIATE fREQUENCY (1"l·I.75MH.
'3
Uo)------l----+~'Cf
POWER GAIN
~24
~
~20
16
~ 12
NOISE FIGURE
"
.O'/J-f
~ a
560-B70
pf
10
2.0
3,0
1
-1
4.0
OSCILLATOR DRIVE VOL TAGE AT TERMINAL No.2-VOLTS RMS
Fig. 47-Power gain and noise figure as a function of the
oscillator drive voltage for the CA3004 balanced mixer.
126
___9,,'3"
OUTPUT
""
I
"~
T2
BIFILAR
.-_+-.-~
"=
-sv
T,
9.6:1"2
50
~lrN.
1osCC~~~~~~R
1.75 MHz
-=-
Fig. 48-Circuit diagram for the use of the CA3005 or CA3006
as a double-sideband, suppressed·carrier modulator.
-----------------------------ICAN-5022
of a double-ended out-of-phase output, is driven through a
SO-ohm adjustable feed by the double-sideband signal from
the modulator. The levels of V 11 V 21 v", and Vs are altered to
establish the relationship between the harmonic distortion
and drive levels as well as gain values for typical operation.
The results are shown in Table VII. Overdrive by the modulation (v,) or the modulated signal· (v,) results in thirdharmonic distortion of the detected signal. Note that gain is
a function of either the product of v, and v" or the product
of v.. and vS'
+6V
I.
I•
....--=---l--OUTPUT 1
'6
~----L-_OUTPUT 2
··U.,~ 1"
= .•
015
-6V
REGENERATED
CARRIER
U.75I1HII
MODULATED
SIGNAL -=
Fig. 49-Circuit diagram for the use 0/ a CA300J or CA3006 as a product detector.
TABLE VII
Gain and Distortion as a Function of Different Drive Levels for a Double~Sideband Modulator and
Product Detector Using the CAJ006
Terminal 3
Harmonic Distortion
Condition
V,
Varied
v,
Varied
v,
Varied
v,
V,
(m.
rms)
Voltage
(mv
rms)
(Volls
rms)
(oolts
1ms)
rms)
5
31.5
31.5
31.5
31.5
100
315
31.5
31.5
31.5
31.5
31.5
31.5
31.5
0.296
0.296
0.296
0.296
0.96
2.96
0.296
0.296
0.296
0.296
0.296
0.296
0.296
0.046
0.080
0.25
0.083
0.262
0.83
0.083
0.083
0.083
0.083
0.083
0.083
0.083
4.95
8.9
26.6
8.9
28
89
8.9
8.9
8.9
8.9
8.9
8.9
8.9
10
30
10
10
10
10
10
10
10
10
v,
Varied
10
10
'"
"
(m.
V,
(m.
rms)
I
1161&2
(m.
,ms)
4
4
4
4
4
4
0.5
4
12
20
4
4
"
(m.
V,
(dB be/ow fundamental)
(mv
rms)
1ms)
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.315
0.5
1.0
36
36
36
36
36
36
17.5
36
110
188
23
36
86
Znd
51
56
Jrd
54
54
37.5
54
51
50
54
52
47.5
37
54
54
50
4th
5th
59
Notes: 1. Consult Figs. 48 and 49 for explanation of voltage designations.
2. Blank spaces indicate harmonic distortion is more than 60 dB below the fundamental.
127
DDLn5LJD
Solid State
Linear Integrated Circuits
Application Note
ICAN-5030
Division
Application of the RCA-CA3000
Integrated-Circuit DC Amplifier
BY
A. J. LEIDICH and M. E. MALCHOW
The RCA·CA3000 dc amplifier is a monolithic silicon
integrated circuit supplied in a 10·terminal TO-S package.
This stabilized and compensated differential amplifier has'
push·pull outputs, high·impedance (O.l-megohm) inputs,
and gain of approximately 30 dB at frequencies up to one
MHz. Its useful frequency response can be increased to
several tens of megahertz by the use of external resistors
or coils.
Because full gain-control capability is inherent in tire
CA3000, it can be used as a signal switch (with pedestal),
a squelchable audio amplifier (with suppressed switching
transient), a modulator, a mix.er, or a product detector.
When suitable external components are added, it can also
be used as an oscillator, a one-shot multivibrator, or a
trigger with controllable hysteresis. Within its specified
frequency range, it is an excellent limiter, and can. handle
input signals up to about 80 millivolts rms before significant cross-modulation or intermodulation products are
generated.
CIRCUIT DESCRIPTION
The circuit diagram and terminal connections for the
CA3000 dc amplifier are shown in Fig. I. The circuit is
basically a single·stage differential amplifier (Q, and Q.)
with input emitter-followers (Q. and Q,) and a constantcurrent sink (Q,) in the emitter·coupled leg. Push-pull input
and output capabilities are inherent in the differential configuration.
The use of degenerative resistors R. and R. in the emittercoupled pair increases the linearity of the circuit and decreases its gain. The low· frequency output impedance between each output (terminals 8 and 10) and ground is
essentially the value of the collector resistors R, and R, in
the differential stage.
OPERATION OF THE CIRCUIT
The CA3000 is designed for operation from a wide range
of supply voltages. Operation from either one or two power
supplies is feasible, as illustrated by the typical biasing techniques shown in Fig. 2. However, operation from two sup·
plies is recommended because fewer external bias networks
are required and, therefore, less power is consumed.
The maximum voltage that can be applied across the
circuit (positive supply voltage Vec plus negative supply
voltage V",,) is 16 volts. The maximum voltage capability
(Ve,,) of the differential pair is limited to 8 volts. Extra care
must be used to ensure that these values are not exceeded
when the circuit is used to drive" induclivt: loaus.
The operating·current conditions of the differential pair
are determined by the base-bias circuit and emitter resistance of the emitter·coupled constant·current sink (Q.), as
well as by the voltage between terminals 2 and 3. Each
possible current condition is manifested by (I) a distinct
set of dc operating characteristics with differing temperature
characteristics, (2) a particular value of gain having its own
temperature dependence, and (3) a particular dynamic
3070
128
-
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ICAN_5030
output-vollage capability. For each value of voltage between
terminals 2 and 3 (V"" when lerminal 2 is grounded). Ihere
are four possible operating modes, as described in Table I.
Table l-Operating Modes for CA3000 DC Amplifier
Shorted
Mode
"""'J\"
B
C
D
A.
A3
03
A.
·7
A9
D,
D.
A,O
All
3
VEEH
Fig_ J - Schematic diagram and terminal connections
lor the CA3000 integrated-circuit dc amplifier.
Terminals
none
5-3
4-3
5-4-3
Condition
of Diodes
--in-oul
in
oul
Q~
Emitter
Resistor
RI/+R,II
R,+Rlo
R.
R.
The opeFaling characleristics for Ihese modes of operation
are summarized in Table " for various two-supply configurations with terminal 2 grounded ani. with V ...: values
of -3 and -6 volts dc.
Table " shows thaI Ihe posilive supply voltage can be
adjusted for each mode of operation and for each value of
negative supply so thaI the nominal dc OUlput voltage is
zero. (Although the V,., value required for mode C for a
V.:I'. of -6 volts de is in excess of the maximum rating,
opera lion within ratings can be achieved wilh slightly negative values of output voltage.) The use of Ihese adjusted
values of posilive supply provides two advanlages: (1) direct interstage coupling can be effected in a single-ended
configuration, and (2) negative feedback can be introduced
from a single output back to the appropriate input. For
low-level applications in mode D with a negative supply
voltage V,'" of -3 volts dc and a positive supply voltage
V,. of 1.1 volts dc, the CA3000 has a gain of 24.4 dB, a
dissipation of 6.2 milliwatts, an output capability of 2.2
volts peak-ta-peak. and a dc output-voltage reference level
of zero.
The information in Table II can be modified for singlesupply designs by simple addition and/or sublraction of
dc values. For example, Ihe correcl information for a single
Table II-Design Characteristics of CA3000 Operating Modes
DC Supply Volts
Negative
Positive
V ••
-Y..a
--66
6
6
3.7
1.7
10.6
(over rating)
5.0
3
3
3
3
1.8
0.4
5.3
1.1
---=6
Operating
mode
--A--
Single-ended DC output volts
midband voltage (Terminal 8 or
gain-dB
10 to ground)
G ••
V ••"
31.2
27.3
-6
B
-6
-6
-6
-6
C
D
A
B
34.6
32.4
31.2
27.3
-6
-6
-3
-3
-3
-3
-3
-3
-3
-3
C
D
A
B
34.6
32.4
27.5
16.6
C
D
A
32.6
24.4
27.5
16.6
32.6
24.4
B
C
D
+2.3
+4.3
-1.5
(saturaled)
+1.0
0
0
0
0
+1.2
+2.6
-1.5
(saturated)
+1.9
0
0
0
0
Positive
voltage
swing
Negative
voltage
swing
V ... .,.·
+3.7
+1.7
Y... f ,,·
-3.8
-5.7
+7.5
+5.0
+3.7
+1.7
0
-2.4
-1.4
-1.4
-mW
--4-036
61
47
33
25
+10.6
+5.0
+1.8
+0.4
-1.5
-1.5
-2.6
-4.1
83
43
8.8
7.4
+4.5
+1.1
+1.8
+0.4
+5.3
+1_1
0
-3.3
-1.5
-1.5
14
8.5
7.2
8.4
19
6.2
- . 1 • .,1
-2.6
TOlalpower
dissipation
• V0au: and V.... I. arc the ac swing extremities above and below V••e •
129
ICAN-5030
Vee(+)
R,
.~
IIIN
OR
GROUNO
Your
R.
VOUT
R,
R.
-~
OR
III
YOUT
Your
GRD.
R,
(b)
(a)
R,
R,
~Z
RZ
.~
o-l
-VIN
OR
GRD.
RZ
* *
(b)
(b)
* Connection of terminals 4 and 5 depends on f110de of operation.
Fig.2 - Typical biasing arrangements lor the CA3000 lor operation Irom (a) two separate voltage supplies,
or (b) a single voltage supply.
supply of 12 volts de for operating mode A can be obtained
from the conditions shown in the table for mode A for
Vee 6 Vde and V•• -6 Vde by the additi9n of 6 volts
=
=
to the values shown for Vce. V r:..f Vo.e , Va..... and Vo", .•.
(It should be noted that the required voltage levels at the
.
...
~
OUTPUT OfIERATING POIIT.Ycc-V.
.l!
•
!l
!!
~
"g
!;
~
u
."
!"
input terminals 1 and 6 and at terminal 2 are also 6
volts higher.
As mentioned previously, the four operating modes exhibit different temperature characteristics. Fig. 3 shows
theoretical curves of dc output voltage as a function of
-0.2
i-D.·
;;
~oz.
10
TEIlPERATURE-·C
100
'4.
i"
-0.2
~
-0.4-
s~:!
-10
-4..
-~o
TEMPERATURE _·C
Fig.3 - Theoretical curves 01 dc output voltage as a lunction 01 temperature lor negative-supply voltoges
01 -3 and -6 volts dc (calculated lor ~ = 35 at 200C).
130
------------------------------ICAN-5030
Vee· 611', VEE. -611'
Vee· sv, VEE. -:5V
:f~
-t~----------c
~·'ai;;'0-;;10~'0,..,,12:n'O:O::,40
=::::::::D.
-.260- :0
-20
-I~;::;;::;;=~=::.:=~,
eo
-2
-60
0
TEMPERATURE - ·C
-40 -20
0
20
40
60
100
120
140
TEMPERATURE - ·C
Fig.4 - Measured curves of dc output voltage as a function of temperature for
negative-supply voltages of -3 and -6 volts dc.
-2
-.
-60
-40
-20
20
40
60
TEMPERATURE _·c
ao
100
140
120
VEE --6Vde
CURVE
GAIN (dB)
AT O·C
31.2
27.3
•. 6
eI
32.4
I
~.
=
0
~
2
-I
~
-2
-.
-60
-40
-20
20
40
60
TEMPERATURE - ·C
ao
100
140
120
Fig.5 - Theoretical curves of gain as a function of
temperature for negative-supply voltages of -3 and
-6 volts dc (calculated for ~ = 35 at 20o e).
~
!IO
;!
il
>'=40
-'I
~z
~=30
temperature for each operating mode for negative supply
voltages V,m of -3 and -6 volts dc. The experimental
curves shown in Fig. 4 are in excellent agreement with the
theoretical curves except in the case of mode C. In this
mode, the differential-pair transistors Q2 and Q, were driven
into saturation as a result of the use of symmetrical supplies
(V,.• = Vr.e) for the experimental data. The discrepancy
could be corrected by use of somewhat higher values of
positive supply voltage.
Fig. 5 shows theoretical curves of gain as a function of
temperature for the four operating modes with Vcc values
of -3 and -6 volts dc. With the diodes in (modes A and
C), the gain decreases for both values of VEE. With the
diodes out (modes B and D), on the other hand, the gain
increases with temperature for a negative supply of -3
volts dc, but decreases with temperature for a negative
supply of -6 volts dc. With the diodes out, there is a value
of negative supply (approximately -4.5 volts dc) for which
the gain is independent of temperature. Fig. 6 shows measured values of single-ended and push-pull gain for mode A
with symmetrical power supplies of ± 6 volts dc. (fhis configuration is used in the remaining discussion because it
provides the maximum sinusoidal output capability. as
shown in Table II, and because of the convenience of ±6volt dc supplies.)
The typical singie-ended voltage-gain! frequency-response
curve of the CA3000 for dc supplies of ±6 volts in operating mode A is shown in Fig. 7, together with the test circuit
used for voltage-gain measurements. The Bode responses
of the CA3000 are virtually independent of source impedance up to 10,000 ohms because of the emitter-follower
inputs. The curves in Fig. 8 show that gain and bandwidth
are virtually independent of temperature for operation in
mode A with ±6-volt dc supplies.
MODE It
"'cc·IV,Vue-GV
FREQUENCY{fl-IOO HI
PUSH-PULL
SINGLE-ENDED
~ ~~~.--=4~0~-~m~~~~2~0.-~4i;;0~••~0-7ao~'1~00.-'1*'20.-~,4'0
TEMPERATURE _·C
Fig.6 - Measured values of singl.... ended and push-pull gain for mode A operation
with symmetrical power supplies of ±6 volts dc.
131
ICAN-5030---------------------------
,
i
20
~
..
i:i
...:.
0
I--
.J
I--
~-~-
10
SOURCE
1000
OHMS
I---
0.1
I\.
4
2
8
~~-
2)(~
-=-
=
o
~
'1 1
•
CA3000
MS
I
!
Ii ,
I
I
,
10
¢?O
Ii
!!
!iI
!!
I\.
~
-
0
!!;
on
I
;
~
D
~
--+!---tI
r-
30
..~
!
"=" -6V
"
I'\.
II
II
• •
I
'\
"="
.•
4
2
2
10
\
4
100
FREQUENCY -MHz
Fig_7 - Single-ended voltage gain of CA3000 as a function of frequency in test circuit shown_
III
POSITIVE DC SUPPLY VOLTS (Vee)· +6
NEGATIVE DC SUPPLY VOLTS (VEE)- -6
D
i
;;
i..
..
~
I
III
III
III I
FREE-AIR TEMPERATURE (T~, )c-l55"C
0
~ i'-25
-10
0
.
~
-20
~
:Ii -30
!i!'"
-,
0.001
2
4
••
2
4
••
2
FREQUENCy (f) -
4
••
2
4
••
10
0.1
0.01
MHz
92CS-I3294
Fig.8,- Normalized gain-freque,ncy curves for CA3000
at three Jillerent temperatures.
Fig. 9 shows agc characteristics for the CA3000 for ao
input frequency of I kHz, together with the age voltagegain test circuit. When the age voltage at terminal 2 is
varied from 0 to -6 volts, the amplifier gain cao be varied
over a raoge o{ 90 dB.
Fig. 10 shows the test circuit used to m~asure commonmode rejection, together with curves of common-mode rejection as a function of frequency aod ,temperature. Typical
132
rejection is 97 dB at a frequency of I kHz. Fig. II shows
the test circuit used to measure the dc unbalance of the
amplifier (referred to the input), together with a curve of
the input offset voltage as a function of temperature.
Typical input offset voltage (with an assumed push-pull
differential go.in of 37 dB) is 1.5 millivolts. Fig. 12 shows
curves of input bias current, input impedance, and dynamic
output voltage as functions of temperature.
_________________________________________________________ ICAN_5030
.
6V
r-- ~
20
\
.,
1\
0.0
-I.
-20
..
.
o
TO-&
VOLTS
(ADJUSTABLE)
..
-6V
-00
-ro
Fig. 9 - AGC characteristics of CA3000 in test circuit
shown at frequency of 1 kHz.
-80
0.0
-
-
-
-
-
APPLIED DC YOLTAGE APPLIED TO TERMINAL 2
-
POSITIVE DC SUPPLY YOLTS (Vee)- +6
NEGATIVE OC SUPPLY VOLTS (YEE)· -6
FREE-AIR TEMPERATURE (TFA) • 25·C
80~
F::::
Vee
+6V
'"
z
0
i= 1D 60
uv
~I
"';<
to..
r-....
~340
"
0-
"2
~~
~
0
t-....
ZO
u
0
2
0.01
•••0.1
2
•••
2
•••10
FREQUENCY (1)- MHz
•••100
2
92CS-13295
:100
I
-6V
VEE
z
9 "
E
COMMON-MODE REJ"ECTION RATIO (CMR). 20 log
i-
(Ai!~31
-A· SINGLE-ENDED VOLTAGE GAIN AS MEASURED
IN CIRCUIT SHOWN IN FIG. 7
I"
! .2
92CS~I2983R1
~
8~'.h80,---!,40,---!,20,-.~~20!=-~.!=-~
. .!=-~
. .!=-~IOO!=-~12'-a~14O
.
n_UATUftE -
-c
Fig. 10 - Common-mode rejection of CA3000 as a function
of frequency and of temperature in test circuit shown.
133
ICAN-5030 - - - - - - - - - - - - - - - - - - - - - - - - - - Vee
'6V
.g
.
!:i
2.5
2.0
:;
i
1.5
::,
1.0
.
.t
0.5
TEMPERATURE --c
-6V
VEE
92C;5-13595
Fig. 11 - Input oIfset voltage of CA3000 as a function of temperature in test circuit shown.
POSI IV. DC .UPPLY VOLT. Vee • +6
NEGATIVE DC SUPPLY VOLTS (VEE). -6
FREQUENCY Ct) ~ IIIHI
POSITIVE DC SUPPLY VOLTS (Vee). +6
NEGATIVE oc SUPPLY VOLTS (YEE)- -6
c
~ 100
~
.:.
•
-7!i
-50
-25
0
50
o
25
7!i
50
100
-75
125
FREE-AIR TEMPERATURE (TFA)--C
...
.. !l
~~~e
~~=;
3~'1
•
-50
-25
25
50
75
100
125
FREE-AIR TEMPERATURE (TFAI-·C
92C$-13298
ycc-eViVEE--IV
MOO.A
FREQUENCY Itl-IOO Hz
£!~S '
'">l1I-
~ ~lOln-::::
..b;o,....,-~20;;;----;\--..
=---,40=---,60!:---.iIO:--I::!OO".....,I,!,20,.--,!,.O
TEMPERATURE-
-c
Fig. 12 -.Input bios current, input impeJance, anJ Jynamic output voltage of CA3000
as functions of temperature.
APPLICA TIONS
Crystal OsclUato.---The CA3000 can be used as a crystal
oscillator at frequencies up to 1 MHz by connection of a
crystal between terminals 8 and 1 and use of two external
resistors, as shown in Fig. 13(a). The output is taken
from the conector that is not connected to the crystal
(in thi!l;
ca~~
terminAl 10). If a variahle-feedhack ratio
network is used, as shown in Fig. 13(b), the feedback may
be adjusted to provide a sinusoidal oscillation. Output
waveforms for both circuits are also shown. The frequency
in each circuit is 455 kHz, as determined by the crystal.
The range of these crystal oscillators can be extended
to frequencies of \0 MHz or more by use of conector
tuning.
134
Modulated OscUJator-If a low-frequency signal is connected to terminal 2, as shown in Fig. 14, the CA3000 can
function as an oscillator and produce an amplitude-modulating signal. The waveform in Fig. 14 shows the modulated
signal output produced by the modulated oscillator circuit
when a I-kHz signal is introduced at terminal 2 and a
high-pass filter is used as the output.
Low-Frequency Mixer-In a configuration similar to that
used in modulated-oscillator applications, the CA3000 amplifier may be used as a mixer by connection of a carrier
signal at the base input of either differential-pair transistor
(terminal! or 6) and connection of a modulating signal to
terminal 2 or S.
______~-------------------------------------------------ICAN-5030
~-l-----06 V
Vaul' }--;H"')-(
-6V
1000
OHMS
1000
OHMS
,oJ
IDaa
OHMS
,OJ
Fig. 13 - Schematic diagrams and output woveform$ of (0) crystal oscillator and
(b) crystal oscillator with variable feedbock_
6V
>--u,.-"U-6 v
..
ut~27.'
t
1\)00
=
OHMS
OHMS
1000
OHMS.
VI· MODULATING SIGNAL
(60D-OHM SOURCE)
Fig. 14 - Schematic diagram and output waveform of CA3000 modulated oscillator.
Cascaded RC-Coupled Feedback Amplifier-The twostage feedback cascade amplifier shown in Fig. 15 produces
a typical open-loop midband gain of 63 dB. This circuit
uses a 100-picofarad capacitor C, to shunt the differential
outputs of the first stage. This capacitor staggers the highfrequency roll-offs of the amplifier and thus improves
stability.
The gain-frequency characteristic of the feedback amplifier is shown in Fig. 16(a) for a feedback resistance R,
approaching infinity. The low-end roll-off of the amplifier
is determined by the interstage coupling. Because agc may
be applied to the first stage, the amplifier of Fig. 15 may be
used in high-gain video-agc applications under open-loop
conditions. If feedback is used to control the gain. agc may
still be applied successfully.
Fig. 16(b) shows the agc characteristics for the two-stage
amplifier under open-loop and two closed-loop conditions
al a frequency of I kHz. As shown in Fig. 16(a), the openloop bandpass is 18 Hz to 135 kHz; under closed-loop
conditions, the bandpass is 1.3 Hz to 2 MHz for 40-dB
gain and 0.13 Hz to 6.6 MHz for 20-dB gain. The negative
feedback thus improves low-frequency performance sufli-
135
ICAN-5030 - - - - - - - - - - - - - - - - - -_ _ _ _ _ _ _ _ __
YOUT
the input is adequately shielded from the output by a
ground plane.
The CA3000 has an output capacitance of approximately
9 picofarads at a frequency of 10 MHz. This capacitance
LeN-l
T/~
60
"\
00
FOR VAGc.O
CLOSJD-LOOP
40
.,
"zI
.:=
.""
30
~
Fig_1S - Cascaded RC-coup/ed feedbaclc amplifier
using two CA3000 circuits.
CLOSJO-LOOP
20
(Rt • 9000 OHIIS)
':i
!i!
ciently so that the use of small coupling capacitors C,
and C, involves little sacrifice in low-frequency response.
If three or more CA3000 amplifiers are cascaded, the
low-frequency roll-offs must be staggered as well as
those at the high end to prevent oscillation. A three-stage
cascade has a midband gain of approximately 94 dB.
Narrow-Band Tuned Amplifier--Because of its high input and output impedances, the CA3000 is suitable for use
in parallel tuned-input and tuned-output applications. Tliere
is comparative freedom in selection of circuit Q because
the differential amplifier exhibits inherently low feedback
qualities provided the following conditions are met: (1) the
collector of the driven transistor is returned to ac ground
and the output is taken from the non-driven side, and (2)
10
':'
~
0
~
-10
-20
-so
-40
(a)
I
-3
-4
-5
AGe DC VOLTS
I
V
\
1\
i
/
\
\
/
oil
10-2
-2
-I
/
I
o
1"1
z
o
63
60
-....,,~
(At· o.l,IIEGOHII'
-
10 I
'0'
10 2
103
FREQUENCy -
104
1\
108
Hz
Fig. 16 - (a} Gain-fre'l"ency and (b} agc cltaracterisflcs ofleedbaclc amplifier sit own in Fig.1S.
136
(b)
-----------------------------ICAN·5030
will resonate a 28 microhenry coil at this frequency and
give a minimum Q of 4.SS when the collector load resistor
is the only significant load. With this low Q, stagger
+6V
tuning may be unnecessary for many broad-band applica-
tions.
Fig. 17 shows the CA3000 in a narrow-band, tuned·
input, tuned·output configuration for operation at 10 MHz
with an input Q of 26 and an output Q of 2S; the response
curve of the amplifier is also shown. The IO-MHz voltage
gain is 29.6 dB, and the total effective circuit Q is 37.
There is very little feedback skew in the response curve.
The CA3000 can be used in tuned-amplifier applications
at frequencies up to the 30-MHz range.
+6Vdc
-6V
Fig. 18 • Schematic diagram lor Schmitt trigger
using CA3000.
(terminals 3 and' S shorted together) in t.he configuration
shown in Fig. 18. Large values are required for extenial
resistors R, and R, because they receive the total collector
current from terminal 10. Because of the high impedances,
resistor RlI is actually a parallel combination of the input
impedance (approximately 0.1 megohm) of the CA3000 and
the 0.2S-megohm external resistor. The Schmitt-trigger design equations (for a
1) are summarized below. In these
equations, Q, and Q, are the differential'pair transistors, Q,
and Q, are the emitter-follower transistors, and Q, is the
constant-current sink.
8000
OHMS
v,.
-,'
50 OHMS
=
32
STATEl: Q, off, Q, conducting (not saturated)
2B
V,! =
Vee (R,) - V R• (R, + 8000)
R, + R,+ 8000
24
where 8000 ohms is the output impedance of
Q. (obtained from the published data). For R, =
27000 ohms and Vee VB. 6 Vdc,
6V (R,) - 6V (35000)
CA)
R.+ 35000
= =
20
!II
I
z ,.
~
R.
12
=(R. + 8000)
V•• + Vo,
Vee-V'I
R. = (35000) 6V + Vo,
(B)
6V-Vo,
9.6
10
10.4
FREQUENCY - MHz
11.2
Fig. 11 - Schematic diagram and response curve
lor IO-MHz tuned-input, tuned-output,
narrow-band amplilier using CA3000.
Schmitt TrIgger-The CA3000 can be operated as an
accurate, predictable Schmitt trigger provided saturation of
either side of the differential amplifier is prevented (hysteresis is less predictable if saturation occurs). Non-saturatinS operation is accomplished by operation in mode B
VO! = Vco - I. (8000)
where Is = collector current of transistor Q.
",,0.48 milliampere in operating mode B with
V•• = -6 volts dc.
VO! = 2.14 V
(C)
V r, '" Firing voltage for transition from state I to state II
V = Vo, - 0.053 - 100 I. at 2S'C
Vr, Vo, - 0.101 V at 2S'C
(D)
P,
=
STATE II:Qo conducting (not.aturated), Q, off
Van = Vee
VOI[=6V
VOl[ = (Vee - I. 8000) R. - V•• (R. + 8000)
(A)
R.+R.+8000
137
ICAN-5030 - - - - - - - - - - - - - - - - - - - - - - - - - - - V· - 2.14 V (RJ - 6 V (35000)
(B)
'II R, + 35000
V'II e Firing voltage for transition from state II back to
state 1
V' II = V'II + 0.053 + 100 I. at 2S'C
Vrll = V'II + 0.101 Vat 2S'C
(C)
HYSTERESIS VOLTAGE
Van = V"r - V"n
3.86 V (RJ
R,+ 35000
0:202 V at ZS'C
From Ibe calculations for state I, it is evident that either
V" or R, must he a known design value. Because R. is a
composite value, V" is Ibe more reasonable choice. The
ability of these equations to predict Ibe Schmitt-trigger performance is evidenced by Ibe comparisOn of calculated and
experimental data in Table III.
Table 111- Comparison of Calculated and Experimental Data for Scbmitt Triger
Cakulaled
-2.1V
-3.19V
+1.09V
Experimental
-1.I0V
-2.SIV
+1.4IV
-I.OV
-2.4SV
+1.4V
Vau
-O.IOIV
-1.83V
+1.73V
0
-1.8V
+1.8V
4) V.,=+IV
Vr,
V"u
VBY"
+O.9V
-I.ISV
+2.1V
+I.OV
-I.OV
+2.0V
S) V.,=+2V
Vr,
V"u
+1.9V
-O.472V
+2.43V
+2.0V
-O.W
+2.4V
Condition
I) V,'_ 2V
Parameter
Vr,
Vrn
VHT!!
2) V.,=-IV
V.,
Vru
V HIII
3) V.,=O
V"
VI'II
VBrl'!
138
-2.2V
-3.2V
+1.0V
ffilCIBLJIJ
Linear Integrated Circuits
Application Note
Solid State
Division
ICAN-S036
Application of the RCA-CA3002
Integrated-Circuit IF Amplifier
BY
G. E. THERIAULT AND R. G. TIPPING
The RCA·CA3002 integrated-circuit if amplifier is a
balanced differential amplifier that can be used with either
a single-ended or a push-pull input and can provide either
a direct-<:oupled or a capacitance-coupled single-ended output. Its applications include RC-coupled if amplifiers that
use the internal silicon output-coupling capacitor, video
amplifiers that use an external couplirig capacitor, envelope
detectors, product detectors, and various trigger circuits.
The CA3002 features all-monolithic silicon epitaxial construction designed for operation at ambient temperatures
from - 55 to 125°C. and contains a built-in temperaturecompensating network for stabilization of gain and dc
operating point over this operating-temperature range. It
is supplied in a 10-terminal TO-5 low-silhouette package.
Because the CA3002 is a balanced differential amplifier
fed from a constant.current source, it makes an excellent
controlled-gain amplifier. The gain-control function may
be extended to include video gating, squelching, and blanking applications. Envelope detection can be achieved by
suitable biasing of the emitter-base diode of the output
emitter-follower transistor. Product detection can be obtained by re-insertion of the carrier at the base of the
constant-current-source transistor. Various trigger and waveform-generating circuits can also be achieved by the addition of suitable external components.
CIRCUIT DESCRIPTION AND
OPERATING MODES
Fig. 1 shows the circuit diagram and terminal connce:tions for the CA3002 integrated circuit. The circuit is
basically a single-stage differential amplifier (Q, and Q,)
with input emitter-followers (Q, and Q,), a constant-current
sink (Q3) in the emitter-coupled leg, and an output emitterfollower (Q,). A single-ended input is connected to terminal
10 or a push-pull input to terminals 10 and 5. A single-ended
output is direct-coupled at terminal 8 or capacitance-coupled
at terminal 6. Terminals 5 and 10 must be provided with dc
returns to ground through equal external base resistors. The
emitters of the differential pair (Q, and Q,) are connected
through degenerative resistors (R, and R,) to the transistor
current source (Q3)' The use of these resistors improves the
linearity of the transfer characteristic and increases the
signal-handling capability.
Transistor Q, provides a high input impedance for the if
amplifier. Transistor Q5 preserves the circuit symmetry, and
also partially bypasses the base of Q,. Additional bypassing
can be obtained by connection of an external capacitor
between terminalS and ground. The emitter-follower transistor Qa provides a direct-coupled output impedance of less
than 100 ohms.
9-74
139
ICAN-5036 - - - - - - - - - - - - - - - - - - - - - - - - - - Table I-Identification of CA3002 Operating Modes
Fig. l-Schemalic diagram and terminal connections for the
CA3002 ;ntegrated~circuit if amplifier.
When voltage supplies are connected to the CA3002, the
most positive voltage must be connected to terminal 9
and the most negative voltage to terminal 2 (internally connected to the substrate and case). The CA3002 may be
operated from various supplies and at various levels. Operation from either single or dual power supplies is feasible.
When two supplies are used, they may be either symmetrical
or non-symmetricaI. When both positive and negative voltage supplies are used, external components can be minimized, as shown in Fig. 2(a). For single-supply applications,
a resistor divider and a bypass capacitor must be added
externally, as shown in Fig. 2(b). The current through R,
and R, should be greater than one milliampere. Except in
applications that use inductive drive, equal external base
resistors must be added at terminals 5 and ! 0 to provide
base-current returns. Terminal 7 can be connected to ground,
or to the negative supply if a larger negative-going voltage
swing is desired at any operating point.
FOf either single or dual supplies, the operating current
in transistor Q. is determined by the bias voltage between
terminals I and 2. The more negative point of this bias voltage must be connected to terminal 2. For dual-supply systems, terminal! is usually referenced to ground.
For any given bias voltage (VEE when terminal ! is
grounded), four operating' modes are possible, as described
in Table I. In general, each mode is characterized by (I)
a distinct dc operating point with a cbaracteristic temperature dependenee, and (2) a I"~rtiC1l1aT value of gain that
has a distinct temperature dependence.
When the diodes are utilized in the bias circuit (modes A
and C), the current is essentiaIly dependent on the temperature coefficient of the diffused emitter resistors R, and R u ,
and has a tendency to decrease with increasing temperature
at a rate independent of the negative supply voltage. The
140
Operating
Mode
Shorted
Terminals
Condition
A
none
B
C
4-2
D
4-3-2
in
out
in
out
3-2
of Diodes
QJEmitter
Resistor
R,+ RI1
~+RI1
R.
R.
temperature coefficient of the diffused collector resistor R,
is the same as that of the emitter resistor, and a constant
collector-voltage operating point results at the collector of
transistor Q.,. However, the operating point at output termi~
nal 8 is modified by the base-emitter voltage drop of transistor Q" and its temperature dependence. Typical variation
of the output operating point with temperature is shown
in Fig. 3 for the four operating modes for V"" supplies of
- 3 and - 6 volts_ The voltage between terminals 8 and
9 is denoted by V •. In mode B (with the diodes out of the
bias circuit), it should be noted that the output operating
point is constant with temperature because the change in
the collector operating point is cancelled by the change in
the base-emitter voltage drop (VD.).
When the diodes are out of the bias circuit, the currenttemperature curves become dependent on the negative supply voltage. Therefore, the value of V." can be adjusted
so that the transconductance decreases, increases, or remains constant witb temperature. As shown in Fig. 4, the
gain increases with temperature for a -3-volt V•• supply,
but decreases with increasing temJ>Crature for a - 6-volt
V•• supply. At some intermediate value of V •• (approximately - 4.5 volts), the gain 'should be constant as a functioD of tempe;rature. In any case, however, a constant ac
gain with temperature is accompanied by a change in the
collector operating point of transistor Q~.
Fig_ 2-Circuit configurations for the CA.3002 with
(a) dual voltag. supplies, and (b) a single supply_
------------------------------ICAN-5036
0.6r--::--:--=,---------------,
AT 2S·C,
MODE
Vx
VEE =-6 V
AT 25°C,
OUTPUT OF&::RATING POINT- YCC-V X
MODE
e
Vx
2.118V
I.OS4IJ
3.471 V
Z.044V
4.515V
8.2:65V
4.363V
1.577V
-0.2
-0.4
6.
TEMPERATURE-OC
65
105
125
TEMPERATURE-OC
Fig.3-01llput operating-point variation of 'he CA3002 (normalized to the 25°C operating point) as a function of temperature
with VEE supply voltages of -3 and -6 volts.
VEE --3 V
!g
!:i
;
VEE --6V
m
Il'i
I
z
0
ii'
I
;l
25.3
22.2
z
;; -I
~
!:; -I
~
..~
~
-'
>
.:.
0
GAIN-dB
21.2
I
z
-
~ 300 - - - -
j
~
20 0
~
>-
5In
il:
100
/
1/
./
"":>
~
V
V
[--METHOD II)
Fig. 17-Producl detector circuit.
~
20
40
60
80
100
120
Because of the single-ended output, a high-frequency
bypass capacitor (0.01 microfarad) is connected between
terminal 8 and ground to provide fit tering for the highfrequency components of the oscillator signal at the output.
When the amplitude of the suppressed-carrier signal and
of the osci1lator signal are varied, the gain and distortion
characteristics shown in Table III are obtained. The conversion voltage gain is constant at input signals up to 16
millivolts and would be 6 dB less for a single-sideband signal
than for the double-sideband signal. The distortion increases with increasing input signal; for distortion of less
than 1 per cent, the input drive level does not exceed 8
millivolts. The gain maximizes for oscillator voltages of
1 to 2 volts, and the distortion characteristic is also best
in this region. Distortion increases both at low oscillator
drive levels (0.25 volt) and at high levels (3 volts).
Schmitt Trigger. Fig. 18 shows the. use of the CA3002 as
a Schmitt trigger. In this application, the input is applied to
terminalS and both the output and the feedback are taken
from the output emitter-follower at terminal 8. The emitterfollower output isolates the feedback loop from the differ-
140
RMS INPUT MILLIVOLTS (AT I. 75 MHz)
Fig. 16-lnput-olllput clwracteristic:s 0/ the em'e/ope detectors
shown in Fig. 15.
Product Detector. A differential pair driven by a constantcurrent transistor can be used as a product detector if a
suppressed-carrier signal is appHed to the differential pair
and the regenerated carrier is applied to the constant-current
transistor. There are two requirements for linearity: (1) the
circuit must be operated in a linear region, and (2) the current from the constant-current transistor must be linear
with respect to the reinserted carrier voltage.
The CA3002 satisfies these requirements and can be used
as a product detector in the circuit shown in Fig. 17. A
double-sideband suppressed-carrier signal is applied at terminal 10, and the 1.7-MHz carrier is applied to terminal 1.
Table III-Performance Data for CA3002 as Product Detector
v,
v,
v,
DoubleSideband
Voltage
Oscillator
Voltage
at
Terminall
Terminal 8
at 1 kc/s
(mV)
(V)
(mV)
Conversion
Voltage
Gain
(dB)
1
4
8
16
32
1.7
1.7
1.7
1.7
1.7
12.5
50
100
200
310
21.9
21.9
21.9
21.9
19.8
60
51
46
37
4
4
0.25
0.5
22
42
15.6
20.3
15
32
4
•. v
GO
• .J
~J
4
4
4
4
4
1.3
60
50
48
31
15
23.5
21.9
21.6
17.8
49
51
52
49
42
1.7
2.0
2.5
3.0
Outpulat
~;J
11.4
dB down from Fundamental 0/ Harmonics
2nd
32
3Td
61
56
46
30
42
52
60
61
61
62
60
60
Harmonic
4th
51
*
5th
64
44
*Harmonic Distortion Greater than 6S dB Down If Omitted
146
ICAN-5036
entiat pair and makes it possible for the circuit to drive
low-impedance loads. An additional advantage is that neither
half of the differential pair saturates as the resistance of the
feedback loop is varied. Fig. 18 also shows the output swing
amI associated hysteresis of the Schmitt trigger as a function
of resistor R and the de input voltage level at terminal 5.
Sr--4r--3 r---'
'"z 2r--...~ I f-I
+6V
0>
...
'"
I
VHYS -tOV
R~
27 K
0
10 K
-6V
DC INPUT VOLTS AT
TERMINAL 5
Fig. 18-Schmitt trigger cir(.'uit and output swing
and associated hysteresis.
147
OOOBLJD
Linear Integrated Circuits
Application Note
Solid State
Division
leAN-S037
Application of the RCA-CA3007
Integrated-Circuit Audio Amplifier
by
R.G. TIPPING
The RCA-CA3007 audio driver is a balanced differential configuration with either a single-ended or a
differential input and two pusll-pull emitter-follower
outputs. The circuit features all-monolithic silicon
epitaxial construction, and is intended for use as a
direct-coupled driver in a class B audio amplifier which
exhibits both gain and operating-point stability over the
tempemture range from -55 to 1250 C. Because of its
circuit configuration (a balanced differential pair fed by
a constanklurrent transistor), the CA3007 is an excellent controlled-gain audio driver for systems requiring
audio squelching. This circuit is also usable as a servo
driver. The audio driver circuit is available in a 12-
terminal T0-5 low-silhouette paclr..age.
CIRCUIT DESCRIPTION
Fig.1 shows the schematic diagram and terminal
connections for the CA3007 circuit. The input stage
consists of a differential pair (Ql and Q2) opemting as
a phase splitter with gain. The two output signals from
the phase splitter, which are 180 degrees out of phase,
are direct-coupled through two emitter-followers (Q4 and
Q5). The emitters of the differential pair are connected
to the transistor constant-current sink Q3·
The diodes in the bias circuit of the transistor COilstant-current sink make the emitter current of Q3 essentially dependent on the temperature coefficient of the
diffused emitter resistor R 3. Because the diffused
collector resistors R 15 and R 16 should have identical
temperature coefficients, constant collector-voltage
opemting points should result at the collectors of
transistors Ql and Q2. However, the quiescent opemting
voltages at the output terminals 8 and 10 increase as
temperature increases because the base-emitter voltage
drops oi transistors Q4 and Q5 decrease as temperature
increases. This small variation in the output quiescent
operating voltage is sufficient to cause a large variation .
in the standby current of a class B push-pull output
stage wben the audio driver and the output stage are
direckloupled. Resistors Rn, R12, R13, and R17 and
transistor Q6 form a dc feedback loop which stabilizes
the quiescent operating voltage at output terminals 8
10-67
148
ICAN·5037
TO-5 PACKAGE
(BOTTOM VIEW)
Fig. 1 • Schematic aiagram ana terminal connections for the CA3007 auaio ariver.
and 10 for both temperature and power-supply variations
so that variations in the output operating points are
negligible.
Resistors Rio R7, Rs, and R14 form the input circuit; a doublEHlnded input is applied to terminals 1
and 5, and a single-ended input is applied to either
terminal 1 or terminal 5, with the other terminal returned
VCe (6 VI
to ground. The CA3007 must be ae-coupled to the input
source. In addition, any dc resistance between terminal
1 and ground should be added between terminal 5 and
ground. Output power-gain stabilization for a directcoupled driver and output stage is accomplished by
means of an ac feedback loop that connects terminals 7
and 11 to the proper emitters of the push-pull output
stage, as shown in Fig.2.
v (3."-,)')
T,
(STANCOR TA-IOI
SQUELCH
VOLTAGE....,.---
1
(
1;
!
~
5>
."
I!:
5
4
/
-4
-s
-12
-
l/
I--
-
4
Gain ys Frequency Response. The open-loop
low-frequency gain of the CA3015 and CA30 16 with
± 12-volt supplies is typically 70 dB with a 3-dB
bandwidth of 320 kHz. The unity-gain crossover
occurs at a frequency of 58 MHz.
Common-Mode Rejection. The common-mode rejection ratio of the CA3015 and CA3016 is typically
104 dB for operation with ± 12-volt supplies. A curve
of common-mode rejection ratio as a function of frequency is included in the bulletin.
Input and Output Impedances. The technical bulletin for the CA3015 and CA3016 includes curves of
input and output impedances as functions of temperature. At 25oC, the typical input impedance is 7800
ohms. The typical output impedance is 92 ohms with
terminal 5 of the CA3015 or terminal 8 of the CA3016
open, and 76 ohms with these terminals connected
to the output.
II
0
the CA3008 and CA301O, there is no hysteresis effect.
The CA3015 and CA3016 technical bulletin includes
curves of maximum peak-to-peak voltages as functions
of load resistance with terminal 5 of the CA3015 or
terminal 8 of the CA3016 open and with terminals 5 and
9 of the CA3015 or t!lrminals 8 and 12 of the CA3016
shorted. The CA3015 and CA3016 can drive a lowerresistance load when these terminals are shorted.
PHASE COMPENSATION
0
4
INPUT VOLTAGE (YIN)-mV
Fig_2 - Open-loop transfer characteristic.
12
The following section describes phase-lag and
phase-lead compensation techniques for these operational amplifiers. Fig.3 shows the various phasecompensation connections for the CA3015.
161
ICAN-5213 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
o Vec.-VEE-12 v
AMBIENT TEMPERATURE (T,\\=25-C
PEN
~NAL 5 OR TERMINAL B
\
°
c
~
;;fil °
\~
r-..
610203040
50
NON-INVERTING GAIN-dB
a:
29.7
19.1
PHASE-LAG
Fig.:! - Terminal connections for phase-lag and
phas('-lead compensation of the CA:!015.
Fig.4 shows a curve of the required phase-lag
capacitance as a function of gain, together with the
corresponding response curves. (The required capacitance values shown in this figure are applicable not
only for ±12-volt power supplies, but also for all
lower-voltage symmetrical supplies; however, smaller
capacitors could be used at lower voltages.)
Fig.5 shows curves of open-loop compensated
and uncompensated frequency response with ±12-volt
supplies. Although the phase-lag compensation capacitance of 18 picofarads shown in curve (8) of this
figure is sufficient to provide stability in resistivefeedback amplifiers down to unity gain, it is not sufficient to provide flat closed-loop response (± 1 dB)
below 20 dB.
Phase-Lead Compensation
In addition to the standard phase-lag compensation discussed above, the CA3015 and CA3016 have a
162
50
50
C'F)~'
40
Phase-Lag Compensation
When the CA3015 and CA3016 are operated from
±S-volt supplies, the phase-compensation techniques
described previously for the CA3008 and CA3010 are
applicable. 1 When the CA3015 and CA3016 are operated from ± 12-volt supplies, corrections must be msde
in the phase-lag compensation to allow for the shift
in frequency at which the second break in the openloop Bode plot occurs. At ±l2 volts, this second
break occurs at a frequency of 10 MHz. For Millereffect and conventional phase-l ag compensation, the
series RC combinations must be. sdjusted so that
1I(27TRC) =lOMHz to correct for the shift infrequency.
In sddition, the Miller technique requires a larger
value of phase-lag capacitance for a non-peaking
(± 1 dB) response to allow for the higher gain.
40
INVERTING GAIN -d B
'-v-'
MILLER EFFECT
....
1\
'2
\
I\,
20
\
~
I"
56
,
62
6&
°
-'00.'
2
4
• '.0
FREQUENCY -
•
'0
MHz
Fig.4 - Amount of phase-lag capacitance required
to obtain a flat I±l dB) response, and typical
response choracteristics.
80
Vee· -VEE • 12 V
SOURCE RESISTANCE • 50 .Q
70
1"-1'.
60
"
CB)
PHASE-LAG
COMPENSATED
o
20
-
0.1
II
CD)
PHASE-LEAD
COMPENSATED
~
(47,100, 470,OR
IOOOpFl
~
(18 pF,820 A)
,0
°
'"
"- '<
CA)
,~
I'...
f---, UNCOMPENSATED
Ice)
:-....
PHASE-LEAD
COMPENSATED
I
c'I°"l) I I
'0
\~
'''1\
~
100 ""0
FREOUENCY-MHz
Fig.5 - Open-loop gain as a function of frequency
for compensated and uncompensated amplifiers.
_ _ _ _ _--'-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ICAN·5213
phase-lead compensation capability. For this phaselead compensation, a capacitor is connected between
terminals 7 and 8 of the CA3015, as shown in Fig.3,
or between terminals 10 and 11 of the CA3016. The
effect of this capacitor is to eliminate the break at
10 MHz in the Bode plot and thus extend the 6-dB-peroctave roll-off. The second break in the Bode plot
then occurs at approximately 35 MHz, and the unitygain crossover occurs at 150 MHz. The phase-lead
compensated open-loop response is shown in curves
(C) and (0) of Fig.5 for various values of capacitance.
For optimum performance, a minimum phase-lead capacitance of 47 picofarads is recommended.
For flat (± 1 dB) responses at closed-loop gains
below 30 dB, a small amount of phase-lag compensation is required in addition to the phase-Ie ad compensation. The required phase-lag capacitance for flat
(±t dB> responses and the corresponding response
curves are shown in Fig.6. When phase-lead compen5 VCC.-VEPI2 V
~~~~,~ILT~M6~~~1~~~A«(A~~~~oEcN
sation is used, the series RC combinations should be
adjusted so that 1/(2 nRC) = 35 MHz.
The phase-lead compensation is also applicable
when ±6-volt power supplies are used, and provides a
unity-gain crossover improvement of about one octave
as compared to the uncompensated connection. As
mentioned earlier, the phase-lag capacitance requirement for ± 12-volt supplies shown in FigA is satisfactory for ±6-volt supplies, although smaller capacitors could be used with the lower voltages.
APPLICATIONS
For all applications, ac and dc balance at the
input must be preserved, i.e., the two inputs must be
returned to ground through equal impedances.
50.dB Amplifier
Fig.7 shows the circuit configuration and frequency response for a non-inverting, 5O-dB amplifier
employing phase-lead compensation. This amplifier
01\
.\
1\
0
'I
1\
5
15KQ
\
GIC
.,n
2030
40
NON-INVERTING GAIN-dB
!
6
0
,
19.1
29.7
INVERTING GAIN-dB
0
a
I
i'-r-,
40
"cC=-YEE=12V
PHASE-LEAD COMPENSATION, 2000 pF
~OPEN LOOP
COMPENSATED
"'-
50 I-- CLOSED LOOP
ClpF)=2
~
0
"
01
2
. ..
0
t'..... 1\
0
"-....
22
0
1\.\
\
I.
0
-I 0
\
•
0
0
..
2
4
1.0
FREOUENCl-MHI'
10
~
I\.
~
f\
0
6 8 ,00
0
QI
Fig.6 - Amount of phase-lag capacitance required
to obtain a flat (±I dB) response when phase·
lead compensation is used, and typical
response characteristics.
2
.
1.0
,
4
..
10
FREQUENCY-MHz
.. r\
100
Fig.7 - Circuit diagram and response curve for a
50-dB, non-inverting amplifier with phase-lead
compensation.
163
ICAN·5213 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
has a 3-dB bandwidth of 3.5 MHz, and a unity-gain
crossover at 150 MHz.
IO.dB, 42.MHz Amplifier
Fig.8 shows the circuit diagram and frequency
response for a 1O-dB, non-inverting amplifier employing both phase-lead and phase-lag compensation.
Slight peaking (2 dB) occurs for the phase compensation
shown. Flat response with bandwidth reduction to
25 MHz may be obtained by use of a phase-lag capacitance of 15 picofarads.
C~IKll
IKll
C,
27QpF
-=
C,
I r-..---:)
ISOpF ~OPF
510.a.
-=
5
AMPUF~.
Q"2_8
5
I0
/
5
"\
'~WW-T
0 14.4
I
........
0
/" V
0.6
0
\~
/11
0
5
hc\
I
0
~
I
,..-
,
1
1.0
0.8
FREQUENCY -
1.2
MHz
Fig.9 - Circuit diagram and response curves for a
bandpass amplifier using a twin-T network.
2 kll
Ikll
The symmetrical twin-T network can be designed
by use of the following equations:
fl 11111111111 ~ITNII
O~I
01
I
10
~
FREQUENCY-MHz
Fig.S - Circuit diagram and response curve for a
lO·dB, non-inverting amplifier with phase-lead
and phase-lag compensat ion.
Twin· T .Bandpass Amplifier
Fig.9 shows the circuit diagram and frequency
response of a bandpass amplifier using a twin-T network in the feedback loop. The difference in resonant
frequency between the bandpass-amplifier response
and the twin-T network response is caused by device
capacitances and loading effects. The unloaded Q
(Qo) of the twin-T network is 14.4; the Qo of the bandpass amplifier is 12.8.
164
Rl = 2 R2
Cl = \2 C2
fo
= 1I(27TRl el)
It is important in the design of this type of bandpass
amplifier that the two inputs be returned to ground
through equal resistances; in this case a value of
2000 ohms is used.
20.dB, IO·MHz Bandpass Amplifier
Fig.lO shows the circuit diagram and frequency
response of an RLC bandpass amplifier. This amplifier is designed to have a Qo of about 10