1980_AMD_MOS_LSI_Data_Book 1980 AMD MOS LSI Data Book
User Manual: 1980_AMD_MOS_LSI_Data_Book
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Advanced Micro Devices
MOS/LSI Data Book
Copyright
© 1980 by Advanced Micro Devices, Inc.
Advanced Micro Devices reserves the right to make changes in its products without
notice in order to improve design or performance characteristics. The company
assumes no responsibility for the use of any circuits described herein.
901 Thompson Place, P.O. Box 453, Sunnyvale, California 94086
(408) 732-2400 TWX: 910-339-9280 TELEX: 34-6306
AM-PUB118
TABLE OF CONTENTS
PRODUCT SELECTOR GUiDE ..................................................... ;........
1-1
MOS CROSS REFERENCE GUIDE. . .. .. .. . . . .. . .. . . .. . . .. .. .. .. .. . . .. .. .. . . .. .. .. .. . . .. .. ..
1-5
RANDOM ACCESS MEMORIES:
Am9016 (Military)
16384 x 1 Dynamic R/W Random Access Memory. . . . . . . . . . . . . . . .
Am9016 (Commercial)
16384 x 1 Dynamic R/W Random Access Memory ............. , .,
Am9044/9244
4096 x 1 Static R/W Random Access Memory ....... , ...........
Am9101/91L01/2101 Family
256 x 4 Static R/W Random Access Memories ... " . . . .. . . . . . . . ..
Am9111/91L11/2111 Family
256 x 4 Static R/W Random Access Memories. . . .. . . . . . . . . . . . . ..
Am9112/91L12 Family
256 x 4 Static R/W Random Access Memories ...................
Am9114/9124
1024 x 4 Static R/W Random Access Memory ...................
Am9130/91L30
1024 x 4 Static R/W Random Access Memories .. " ............. ,
Am9131/91L31
1024 x 4 Static R/W Random Access Memories. . .. . . . . . . . . . . . . ..
Am9140/91L40
4096 x 1 Static R/W Random Access Memories ................. ,
Am9141/91L41
4096 x 1 Static R/W Random Access Memories. . . . . . . . . . . . . . . . ..
Am9147
4096 x 1 Static R/W Random Access Memory ... " " ............
2-1
2-11
2-21
2-25
2-31
2-37
2-43
2-47
2-55
2-57
2-65
2-67
UV ERASABLE-PROGRAMMABLE ROMs
Am1702A
256-Word x 8-Bit Programmable Read-Only Memory.. . . . . . . . . . . . . 3-1
Am9708/2708
1024 x 8 Erasable Read Only Memory .......................... 3-7
Am2716
2048 x 8-Bit UV Erasable PROM .............................. , 3-11
Am9732/Am2732
4096 x 8-Bit UV Erasable PROM ............................... 3-16
READ ONLY MEMORIES
Am9208
Am9214/3514
Am9216
Am9217/8316A
Am9218/8316E
Am9232/9233
SHIFT REGISTERS:
Am14/1506Am14/1507
Am1402A/1403A/1404A/
Am2802/2803/2804
Am2805/2806/2807/2808
Am2809
Am2810
Am2814/3114
Am2825/2826/2827
Am2833/2533
Am2847/2896
Am2855/2856/2857
Am4025/5025/4026/5026/
4027/5027
Am4055/5055/4056/5056/
4057/5057
Am9401/2401
1024 x 8 Read-Only Memory ................. , ........... " .. "
512 x 8 Read-Only Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2048 x 8 Read-Only Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2048 x 8 Read-Only Memory. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . ..
2048 x 8 Read-Only Memory ... , ., ., ............. , ...... " .... ,
4096 x 8 Read-Only Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4-1
4-5
4-11
4-15
4-18
4-21
Dual 100-Bit Dynamic Shift Registers. . . . . . . . . . . . . .. . . . . . . . . . . . . .
5-1
1024-Bit Dynamic Shift Registers ...............................
512- and 1024-Bit Dynamic Shift Registers. . . . . . . . .. . . . . . . . . . . . ..
Dual 128-Bit Static Shift Register .............................. ,
Dual 128-Bit Static Shift Register ...............................
Dual 128-Bit Static Shift Register. . . . . . . . . .. . . . . . . . . . . . . . . . . . . ..
2048-Bit Dynamic Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1024-Bit Static Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Quad 80-Bit and Quad 96-Bit Static Shift Registers. . . . . . . . . . . . . ..
Quad 128-Bit, Dual 256-Bit and Single 512-Bit Static
Shift Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5-7
5-13
5-19
5-23
5-27
5-31
5-36
5-40
5-44
2048-Bit Dynamic Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-48
Quad 128-Bit, Dual 256-Bit and Single 512-Bit Static
Shift Registers ............................................. . 5-53
Dual 1024-Bit Dynamic Shift Register .......................... . 5-57
FIRST-IN FIRST-OUT MEMORIES:
Am2812/2812A1
32 x 8 and 32 x 9 First-In First-Out Memories. , ................. .
2813/2813A
64 x 4 First-In First-Out Memories ............................. .
Am2841/3341/2841 A
6-1
6-7
TABLE OF CONTENTS (Cont.)
MICROPROCESSORS AND PERIPHERAL CIRCUITS:
Am8048/8035
Single-Chip 8-Bit Microcomputers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
Am8080N9080A
8-Bit Microprocessor ........................................... 7-5
Am8085NAm8085A-2/
9085ADM
Single-Chip 8-Bit N-Channel Microprocessor " ................. " 7-13
Am8155/8156
2048-Bit Static MOS RAM with I/O Ports and Timer ............. " 7-26
Am8251/9551
Programmable Communications Interface. . . . . . . .. . . . . . . . . . . . . . .. 7-36
Am8253/8253-5
Programmable Interval Timer ................................. " 7-43
Am8255N8255A-5
Programmable Peripheral Interface ............................. 7-49
Am8257/9557
Programmable DMA Controller .................................. 7-54
Am8279/8279-5
Programmable Keyboard/Display Interface . . . . . . . . . . . . . . . . . . . . . .. 7-62
Am9511A
Arithmetic Processor, ....................................... " 7-66
Am9512
Floating Point Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-91
Am9513
System Timing Controller ................................ " " .. 7-110
Am9517A
Multimode DMA Controller ..................................... 7-135
Am9519A
Universal Interrupt Controller ................................... 7-149
BIPOLAR SUPPORT PRODUCTS FOR MOS MICROPROCESSOR AND MEMORY SYSTEMS:
Am3212
8-Bit Input/Output Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Am3216
4-Bit Bidirectional Bus Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Am3226
4-Bit Bidirectional Bus Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Am3448A
IEEE-488 Quad Bidirectional Bus Transceiver.. . . . . . . . . . . . . . . . . . .
AmZ8103
Octal Bus Transceiver (Inverting) ...............................
AmZ8104
Octal Bus Transceiver (Non-Inverting) ...........................
AmZ8107
Octal Bus Transceiver (Inverting) ...............................
AmZ8108
Octal Bus Transceiver (Non-Inverting) ......................... "
AmZ8120
Octal Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . ..
AmZ8121
8-Bit Comparator .............................................
AmZ8127
Clock Generator ............................................ "
Octal Latch (Inverting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AmZ8133
AmZ8136
8-Bit Decoder w/Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AmZ8140
Octal 3-State Buffer (Inverting) .................................
AmZ8144
Octal 3-State Buffer (Non-Inverting) .. . . . . . . . . . . . . . . . . . . . . . . . . . ..
AmZ8148
Address Decoder w/Acknowledge ........................... , ...
AmZ8160
Error Detection and Correction Unit ........................... "
AmZ8161
EDC Bus Buffer (Inverting to Bus) ..............................
AmZ8162
EDC Bus Buffer (Non-Inverting to Bus) . . . . . . . . . . . . . . . . . . . . . . . . ..
AmZ8163
Refresh and EDC Controller ...................................
AmZ8164
Dynamic Memory Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AmZ8165
Dynamic RAM Driver (Inverting) .................................
AmZ8166
Dynamic RAM Driver (Non-Inverting) . . . . . . . . . . . . . .. . . . . . . . . . . . ..
AmZ8173
Octal Latch (Non-Inverting) ....................................
Am8212
8-Bit Input/Output Port ....................................... "
Am8216
4-Bit Bidirectional Bus Driver (Non-Inverting) . . . . . . . . . . . . . . . . . . . ..
Am8224
Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Am8226
4-Bit Bidirectional Bus Driver (Inverting) .........................
Am8228
System Controller/Bus Driver for Am9080A ......................
Am8238
System Controller/Bus Driver for Am9080A ......................
8-58
8-65
8-65
8-1
8-6
8-6
8-12
8-12
8-14
8-18
8-22
8-23
8-28
8-32
8-32
8-36
8-41
8-49
8-49
8-50
8-51
8-52
8-52
8-23
8-58
8-65
8-70
8-65
8-77
8-77
APPLICATION NOTES:
Improved Performance with the Am9124 ., . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . ..
Am9130/9140 ............................................................................
Application of First-In First-Out Memories ...................................................
Algorithm Details for the Am9511 . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Designing Interrupt Systems with the Am9519 ........................................... . . ..
2-72
9-1
9-17
9-26
9-49
APPENDICES
Commitment to Excellence. . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Product Assurance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Packages ................................ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A-1
B-1
C-1
D
PRODUCT SELECTOR GUIDE
1 K STATIC RAMs
Part
Number
Am9101A
Am91L01A
Am9101B
Am91L018
Am9101e
Am91L01e
Am9101D
Am9111A
Am91L11A
Am91118
Am91L118
Am9111e
Am91L11e
Am9111D
Am9112A
Am91L12A
Am91128
Am91L128
Am9112e
Am91L12e
Am9112D
Organization
256 x 4
256 x 4
256 x 4
256 x 4
256 x 4
256 x 4
256 x 4
256 x 4
256 x 4
256 x 4
256 x 4
256 x 4
256 x 4
256 x 4
256 x 4
256 x 4
256 x 4
256 x 4
256 x 4
256 x 4
256 x 4
Access
Time (ns)
500
500
400
400
300
300
250
500
500
400
400
300
300
250
500
500
400
400
300
300
250
Power Dissipation (mW)
Standby
Active
Pins
Supply
Voltage (V)
Temp.
Range
47
38
47
38
47
38
47
47
38
47
38
47
38
47
47
38
47
38
47
38
47
290
173
290
173
315
189
315
290
173
290
173
315
189
315
290
173
290
173
315
189
315
22
22
22
22
22
22
22
18
18
18
18
18
18
18
16
16
16
16
16
16
16
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
e,M
e,M
e,M
e,M
e,M
e,M
e,M
e,M
e,M
e,M
e,M
e,M
e,M
e
C,M
e,M
e,M
e,M
e,M
e,M
C
D,P
D,P
D,P
D,P
D,P
D,P
D,P
D,P
D,P
D, P
D, P
D, P
D, P
D, P
D, P
D, P
D, P
D, P
D, P
D, P
D, P
350
250
350
250
350
350
250
350
250
350
350
250
350
250
350
350
250
350
250
350
578
367
578
367
578
367
578
367
578
578
367
578
367
578
367
578
367
578
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
e,M
e,M
e,M
e,M
e
e,M
e,M
e,M
e,M
e
e,M
e,M
e,M
e,M
e
C,M
e,M
e,M
e,M
e
e,M
C,M
e,M
e,M
e,M
e,M
e,M
e
e
e,M
e,M
e,M
e,M
e,M
e,M
e
e
e
D, P
D, P
D, P
D, P
D, P
D, P
D, P
D, P
D, P
D,P
D,P,F
D,P, F
D,P,F
D,P,F
D, P
D,P,F
D,P, F
D,P, F
D, P, F
D, P
D, P, F
D, P, F
D, P, F
D, P, F
D, P, F
D, P, F
D, P, F
D, P
D,P
D, P, F
D, P, F
D, P, F
D, P, F
D, P, F
D, P, F
D, P
D, P
D, P
Package
4K STATIC RAMs
Am90448
Am90L448
Am9044e
Am90L44C
Am9044E
Am92448
Am92L448
Am9244e
Am92L44e
Am9244E
Am91148
Am91L148
Am9114e
Am91L14e
Am9114E
Am91248
Am91L248
Am9124e
Am91L24e
Am9124E
Am9130A
Am91L30A
Am9130B
Am91L308
Am9130e
Am91L30e
Am9130D
Am91L30D
Am9130E
Am9131A
Am91L31A
Am91318
Am91L318
Am9131e
Am91L31C
Am9131D
Am91L31D
Am9131E
4096 x 1
4096 x 1
4096 x 1
4096 x 1
4096 x 1
4096 x 1
4096 x 1
4096 x 1
4096 x 1
4096 x 1
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
450
450
300
300
200
450
450
300
300
200
450
450
300
300
200
450
450
300
300
200
500
500
400
400
300
300
250
250
200
500
500
400
400
300
300
250
250
200
150
100
150
100
150
150
100
150
100
150
84
72
84
72
84
72
84
78
84
84
72
84
72
84
72
84
72
84
1-1
PRODUCT SELECTOR GUIDE (Cont.)
I
I,
I
4K STATIC RAMs (Cant.)
Part
Number
Am9140A
Am91L40A
Am9140B
Am91L40B
Am9140C
Am91L40e
Am9140D
Am91L40D
Am91L40E
Am9141A
Am91L41A
Am9141B
Am91L41B
Am9141C
Am91L41e
Am9141D
Am91L41D
Am9141E
Am9147·70
Am9147-55
Organization
4096
4096
4096
4096
4096
4096
4096
4096
4096
4096
4096
4096
4096
4096
4096
4096
4096
4096
4096
4096
x1
x1
x1
x1
x1
x1
x1
x1
x1
x1
x1
x1
x1
x1
x1
x1
x1
x1
x1
x1
Access
Time (ns)
Power Dissipation (mW)
Standby
Active
Pins
Supply
Voltage (V)
Temp.
Range
84
72
84
72
84
72
84
72
84
84
72
84
72
84
72
84
72
84
100
150
578
367
578
367
578
367
578
367
578
367
578
367
578
367
578
367
578
367
800
900
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
18
18
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
e,M
e,M
e,M
e,M
e,M
e,M
e
e
e
e,M
e,M
e,M
e,M
e,M
e,M
e
e
e
e
C
Supply
Voltage (V)
Temp.
Range
Package
e, L
e, L
e, L
e
P,D,F
P, D, F
P,D
P, D
Operating Power
Max (mW)
Outputs
263
620
620
660
700
515
368
368
499
368
368
420
420
420
420
3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State
500
500
400
400
300
300
250
250
200
500
500
400
400
300
300
250
250
200
70
55
Package
D,
D,
D,
D,
D,
D,
D,
D,
D,
D,
D,
D,
D,
D,
D,
D,
D,
D,
D,
D,
P,
P,
P,
P,
P,
P,
P
P
P
P,
P,
P,
P,
P,
P,
P
P
P
P
P
F
F
F
F
F
F
F
F
F
F
F
F
DYNAMIC RAMs
Part
Number
Am9016e
Am9016D
Am9016E
Am9016F
Organization
16384
16384
16384
16384
x
x
x
x
1
1
1
1
Access
Time (ns)
Power Dissipation (mW)
Standby
Active
Pins
8
8
8
8
175
175
175
175
16
16
16
16
300
250
200
150
+12
+12
+12
+12
±5
±5
±5
±5
ROMs
Part
Number
Organization
Access Time
(nsec)
Temp.
Range
Am9214
Am9208B
Am9208e
Am9216B
Am9216e
8316A
Am9217A
Am9217B
8316E
Am9218B
Am9218e
Am9232B
Am9232e
Am9233B
Am9233e
512 x 8
1024 x 8
1024 x 8
2048 x 8
2048 x 8
2048 x 8
2048 x 8
2048 x 8
2048 x 8
2048 x 8
2048 x 8
4096 x 8
4096 x 8
4096 x 8
4096 x 8
500
400
300
400
300
550
550
450
450
450
350
450
300
450
300
e,M
e,M
e,M
e,M
e
e,M
e,M
e,M
e,M
e,M
e
e,M
e
e,M
e
1-2
Supply
Voltages
+5
+5,
+5,
+5,
+5,
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+12
+12
+12
+12
D
PRODUCT SELECTOR GUIDE (Cont.)
U.V. ERASABLE PROMs
Part
Number
Organization
Access
Time (ns)
Temp.
Range
Operating Power Act/Stby Max (mW)
Supply
Voltages
Outputs
Number
of Pins
24
Am1702A
256 x 8
1000
C, E
676
-9, +5
3-State
Am1702AL
256 x 8
1000
C, E
-
-9, +5
3-State
24
Am1702A-1
256 x 8
550
C,E
676
-9, +5
3-State
24
Am1702AL-1
256 x 8
550
C, E
-
-9, +5
3-State
24
Am1702A-2
256 x 8
650
C, E
676
-9, +5
3-State
24
Am1702AL-2
256 x 8
650
C,E
-
-9, +5
3-State
24
Am9708/2708
1024 x 8
450
C,M
800
+5, +12, -5
3-State
24
Am2708-1
1024 x 8
350
C
800
+5, +12, -5
3-State
24
Am2716
2048 x 8
450
C
525/132
+5
3-State
24
Am2716-1
2048 x 8
350
C
525/132
+5
3-State
24
Am2716-2
2048 x 8
390
C
525/132
+5
3-State
24
Am2732
4096 x 8
450
C
787/157
+5
3-State
24
FIRST-IN FIRST-OUT MEMORIES
Organization
Serial I/O
Fullness
Flag
Output
Enable
Am2812
32 x 8
Yes
Yes
Am2812A
32 x 8
Yes
Yes
Part Number
Package
Pins
Data Rate
MHz
Yes
28
0.5
C, EO
Yes
28
1.0
C,E
Temp.
Range
Am2813
32 x 9
No
Yes
Yes
28
0.5
C, E
Am2813A
32 x 9
No
Yes
Yes
28
1.0
C, E
Am2841
64 x 4
No
No
No
16
1.0
C, E
Am2841A
64 x 4
No
No
No
16
1.2
C
SHIFT REGISTERS
Part
Number
Capacity/
Organization
Supply
Voltages
Mode
Speed
(MHz)
2
+5, -5
Clock
Phases
Two
TTL
Clocks
Recire
Logic
. Pins
Output
Single-ended
No
No
8
Two
No
No
16
Single-ended
Two
No
No
8
Single-ended
Am1507
Dual 100
Dynamic
Am2802
Quad 256
Dynamic
10
+5, -5
Am2803
Dual 512
Dynamic
10
+5, -5
Am2804
Single 1024
Dynamic
10
+5, -5
Two
No
No
8
Single-ended
Am2805/Am2807
Single 512
Dynamic
4
+5, -5
Two
No
Yes
10/8
Single-ended
Am2808
Single 1024
Dynamic
4
+5, -5
Two
No
Yes
8
Single-ended
Am2827
Single 2048
Dynamic
6
+5, -10.5
Two
No
Yes
8
Push-pull
2
Am9401/ Am2401
Dual 1024
Dynamic
+5
One
Yes
Yes
16
Single-ended
Am2809
Dual 128
Static
2.5
+5, -12
One
Yes
Yes
8
Push-pull
A!T1 2814
Dual 128
Static
2.5
+5, -12
One
Yes
Yes
16
Push-pull
2
+5, -12
One
Yes
Yes
8
Push-pull
One
Yes
Yes
16
Push-pull
Yes
16
Push-pull
Am2833
Am2847
Am2855
Single 1024
Quad 80
Quad 128
Static
Static
Static
+5, -12
3
2.5
+5, -12
One
Yes
One
Yes
Yes
10
Push-pull
One
Yes
Yes
8
Push-pull
Am2856
Dual 256
Static
2.5
+5, -12
Am2857
Single 512
Static
2.5
+5, -12
°E
IS ext~nded
temperature range, -55°C to 85°C.
1-3
UNDERSTANDING THE AMD ROM PIN
Example:
Customer Identifier
A unique 5 digit code
that is assigned to
each customer pattern.
Speed
A = 500 or 550nsec
B = 400 or 450nsec
e = 300 or 350nsec
D = 250nsec
Package Type
P = Plastic
D = Side-Brazed
e = eerdip
1-4
Operating Temperature Range
e = ooe ~ TA ~ 70 0 e
I = -25°e ~ TA ~ +85°e
L = Special
M = -55°e ~ TA ~ +125°e
MOS MEMORY CROSS REFERENCE
AMI
AMD
MOSTEK
AMD
SIGNETICS
AMD
S3514
S42168
S4264
S6831A
S68318
S68332
S8865
Am9214
Am9218
Am9264
Am9217
Am9218
Am9232
Am9208
MK1002P
MK1007
MK2147
MK2600
MK30000
MK31000
MK32000
MK34000
MK36000
MK37000
MK3702
MK3708
MK4116
Am2810
Am2847
Am9147
Am9214
Am9208
Am9217
Am9232
Am9218
Am9264
Am9265
Am1702A
Am2708
Am9016
Am1702A
Am9101
Am9111
Am9112
Am1101
Am2802
Am2803
Am2804
Am2805
Am1406/1506
Am1407/1507
Am2806
Am2809
Am2807
Am2808
Am2847
Am2833
Am9208
Am9218
Am9216
Am9232
Am9264
EA
AMD
EA-2308A
EA-2316N8316A
EA-2316E/8316E
EA-4700
EA-8332
Am9208
Am9217
Am9218
Am9208
Am9232
FAIRCHILD
AMD
F16K
F2114
F2114L
F2533
F2708
F3341
F3341A
F3347
F3357-2
F3508
F3514
F3515
F3516E
Am9016
Am9114
Am9114
Am2833
Am2708
Am2841
Am2841A
Am2847
Am2847
Am9208
Am9214
Am9214
Am9216
G.I.
AMD
R03-8316
R03-9322
Am9217
Am9232
INTEL
AMD
1402A
1403A
1404A
1405A
1406
1407
1506
1507
1702
1702A
1702AL
2101N8101A
2111N8111A
2112A
2114
2114L
2117
2147
2148
2308/8308
2316N8316A
2316E/8316E
2332
2364
2401
2405
2708
Am2802
Am2803
Am2804
Am2805
Am1406
Am1407
Am1506
Am1507
Am9708
Am1702A
Am1702AL
Am9101
Am9111
Am9112
Am9114
Am9114
Am9016
Am9147
Am9148
Am9208
Am9217
Am9218
Am9233
Am9265
Am2401
Am2405
Am2708
MOTOROLA
AMD
MCM2114
MCM2147
MCM4116
MCM68308
MCM68332
MCM8316A
MCM8316E
Am9114
Am9147
Am9016
Am9208
Am9232
Am9217
Am9218
1702A
2101
2111
2112
2501
2502
2503
2504
2505
2506
2507
2512
2521
2524
2525
2532
2533
2607
2616
2617
2632
2664
NATIONAL
AMD
SYNERTEK
AMD
MM101A
MM1402A
MM1403A
MM1404A
MM1702A
MM2101A
MM2111A
MM2112A
MM2114
MM2114L
MM2316A
MM2708
MM4006
MM4007
MM4025
MM4026
MM4027
MM4055
MM4056
MM4057
MM5025
MM5026
MM5027
MM5055
MM5057
MM5058
MM5202AQ
MM52116
MM52132
MM5214
MM52164
MM5235
MM5257
MM5258
MM5290
Am1101A
Am2802
Am2803
Am2804
Am1702A
Am9101
Am9111
Am9112
Am9114
Am9114
Am9217
Am2708
Am1406
Am1407
Am2825
Am2826
Am2827
Am2855
Am2856
Am2857
Am2855
Am2826
Am2827
Am2855
Am2857
Am2833
Am1702A
Am9218
Am9232
Am9214
Am9264
Am9265
Am9044
Am9218
Am9016
SY1402
SY1403
SY1404
SY2316A
SY2316E
SY2332
SY2333
SY2364
SY2405
SY2802
SY2803
SY2804
SY2825
SY2826
SY2827
SY2833
SY3514
SY3515
Am2802
Am2803
Am2804
Am9217
Am9218
Am9232
Am9233
Am9264
Am2405
Am2802
Am2803
Am2804
Am2825
Am2826
Am2827
Am2833
Am9214
Am9214
NEC
AMD
JLPD2308
JLPD2316A
JLPD2316E
JLPD2332
Am9208
Am9217
Am9218
Am9232
1-5
T.I.
AMD
TMS2708
TMS3114
TMS3120
TMS3128
TMS3133
TMS3406
TMS3407
TMS2412
TMS3413
TMS3414
TMS40L44
TMS4044
TMS40L45
TMS4045
TMS4116
TMS4244
TMS4245
TMS4700
TMS4732
S8P8316M
Am2708
Am2814
Am2847
Am2809
Am2833
Am1406
Am1407
Am2802
Am2803
Am2804
Am90L44
Am9044
Am91L14
Am9114
Am9016
Am9244
Am9124
Am9208
Am9232
Am9218
D
Random Access Memories
NUMERICAL INDEX
Am2101
Am2111
Am9016
Am9016
Am9044
Am9101
Am91L01
Am9111
Am91L11
Am9112
Am91L12
Am9114
Am9124
Am9130
Am91L30
Am9131
Am91L31
Am9140
Am91L40
Am9141
Am91L41
Am9147
Am9244
Page
256 x 4 Static ............................................................... 2-25
256 x 4 Static ............................................................... 2-31
16384 x 1 Dynamic (Military Version) .......................................... 2-1
16384 x 1 Dynamic (Commercial Version) ...................................... 2-11
4096 x 1 Static .............................................................. 2-21
256 x 4 Static ............................................................... 2-25
256 x 4 Static ...................................... ~ ......................... 2-25
256 x 4 Static ............................................................... 2-31
256 x 4 Static ............................................................... 2-31
256 x 4 Static ............................................................... 2-37
256 x 4 Static ............................................................... 2-37
1024 x 4 Static .............................................................. 2-43
1024 x 4 Static .............................................................. 2-43
1024 x 4 Static .............................................................. 2-47
1024 x 4 Static .............................................................. 2-47
1024 x 4 Static .............................................................. 2-55
1024 x 4 Static .............................................................. 2-55
4096 x 1 Static .............................................................. 2-57
4096 x 1 Static .............................................................. 2-57
4096 x 1 Static .............................................................. 2-65
4096 x 1 Static .............................................................. 2-65
4096 x 1 Static .............................................................. 2-67
4096 x 1 Static .............................................................. 2-21
Application Note
Improved Performance with the Am9124 ....................................................... 2-72
Am9016
Extended Operating Temperature Range
16,384 x 1 Dynamic R/W Random Access Memory
DISTINCTIVE CHARACTERISTICS
GENERAL DESCRIPTION
• High density 16K x 1 organization
• Replacement for MK4116 (P)-83/84
• Low maximum power dissipation 462mW active, 20mW standby
• High speed operation - 200ns access, 375ns cycle
• :::,:10% tolerance on standard +12, +5, -5 voltages
• TTL compatible interface signals
• Three-state output
• RAS only, RMW and Page mode clocking options
• 128 cycle refreshing
• Unlatched data output
• Standard 16-pin, .3 inch wide dual-in-line package
• Double poly N-channel silicon gate MOS technology
• 100% MIL-STD-883 reliability assurance testing
• Extended ambient operating temperature (-55 to +85°C)
The Am9016 is a high-speed, 16K-bit, dynamic, read/write random access memory. It is organized as 16,384 words by 1 bit per
word and is packaged in a standard 16-r:n DIP or 18-pin leadless
chip carrier. The basic memory element is a single transistor cell
that stores charge on a small capacitor. This mechanism requires
periodic refreshing of the memory cells to maintain stored
information.
All input signals, including the two clocks, are TTL compatible.
The Row Address Strobe (RAS) loads the row address and the
Column Address Strobe (CAS) loads the column address. The
row and column address signals share seven input lines. Active
cycles are initiated when RAS goes low, and standby mode is
entered when RAS goes high. In addition to normal read and write
cycles, other types of operations are available to improve versatility, performance and power dissipation.
The 3-state output buffer turns on when the column access time
has elapsed and turns off after CAS goes high. Input and output
data are the same polarity.
BLOCK DIAGRAM
WRITE
I
I
RAS
r
I
CAS
I
MULTIPLEXED
CLOCK
GENERATOR
1 --<1"
.-
~
CLOCK
GENERATOR
NO.1
1
I
I
CLOCK
GEN:~~TOR
I
~
I
I
I
WRITE
CLOCKS
I
T
~
-,
_ _ YDD
I
I
DATA
IN
BUFFER
DATA IN
I
r----
DATA
OUT
BUFFER
LATCH
RELEASE
--YCC
--YSS
--YBB
DATA OUT
r
DUMMY CELLS
A6
I
AS
A4
MUX
ADDRESS
INPUT
BUFFERS
(7)
A3
A2
"-
I---
r-V
MEMORY ARRAY
..... L--I.-
I
~~~ I
LINES I
ROW
DECODER
1:128
128 SENSE·REFRESH AMPS
ii-
!
i
Al
1 OF 2
DATA
BUS
SELECT
l-
DATA
IN/OUT
L--...-
MEMORY ARRAY
AO
DUMMY CELLS
f-~1fgf~~-
rI
V
MUX
SWITCH
I
r
AG-AS
~
COLUMN DECODERS
1 OF 64
A6
MOS·l90
ORDERING INFORMATION
Ambient
Temperature
-55°C
~
TA
~
+85°C
Access Time
Package
Type
300ns
Hermetic DIP
AM9016CDL
AM9016DDL
AM9016EDL
Chip Carrier
AM9016CZL
AM9016DZL
AM9016EZL
2-1
250ns
200ns
Am9016 (Military)
CONNECTION DIAGRAMS
Leadless
Chip Carrier
01
DIP
VBB VSS CAS
VBB
VSS
01
CAS
DO
WE
DO
AS
RM
A6
NC
AD
A3
A3
A2
A4
A4
A1
AS
voo
A1
VOO VCC AS
AO-A6
CAS
01
DO
RAS
VDD
VCC
VSS
VBB
WE
ADDRESS INPUTS
COLUMN ADDRESS STROBE
DATA IN
DATA OUT
ROW ADDRESS STROBE
POWER (+12V)
POWER (+5V)
GROUND
POWER (-5V)
WRITE ENABLE
vcc
Top Views
MOS-191
MAXIMUM RATINGS above which useful life may be impaired
Storage Temperature
-65 to +150°C
Ambient Temperature Under Bias
-55 to +85°C
Voltage on Any Pin Relative to VBB
-0.5 to +20V
VDD and VCC Supply Voltages with Respect to VSS
-1.0 to +15.0V
VBB - VSS (VDD - VSS > OV)
OV
Power Dissipation
1.0W
50mA
Short Circuit Output Current
The products described by this specification include internal circuitry designed to protect input devices from damaging accumulations of
static charge. It is suggested nevertheless, that conventional precautions be observed during storage, handling and use in order to avoid
exposure to excessive voltages.
OPERATING RANGE
Ambient Temperature
VCC
VDD
vee
VSS
ELECTRICAL CHARACTERISTICS over operating range (Notes 1, 11)
Parameters
Description
Am9016X
Test Conditions
VOH
Output HIGH Voltage
10H
= -5.0mA
VOL
Output LOW Voltage
10L
= 4.2mA
VIH
Input HIGH Voltage for Address, Oata In
VIHC
Input HIGH Voltage for CAS, RAS, WE
VIL
Input LOW Voltage
IIX
Input Load Current
VSS
~
VI
10Z
Output Leakage Current
VSS
~
VO
ICC
VCC Supply Current
Output OFF (Note 4)
ISS
100
VSS Supply Current, Average
VOO Supply Current, Average
CI
Input Capacitance
CO
Output Capacitance
~
7V
~
VCC, Output OFF
Min
Typ
Max
Units
2.4
VCC
Volts
VSS
0.40
Volts
2.4
7.0
Volts
2.7
7.0
Volts
-1.0
0.80
Volts
-10
10
p.A
-10
10
p.A
-10
10
p.A
Standby, RAS "" VIHC
200
Operating, Minimum Cycle Time
400
Operating
1001
RAS Cycling, CAS Cycling,
Minimum Cycle Times
35
Page Mode
1004
RAS ~ VIL, CAS Cycling,
Minimum Cycle Times
27
RAS - Only
Refresh
1003
RAS Cycling, CAS"" VIHC,
Minimum Cycle Times
27
Standby
1002
RAS, CAS, WE
Address, Oata In
RAS"" VIHC
2.25
Inputs at OV, f = 1MHz,
Nominal Supply Voltages
10.0
Output OFF
7.0
2-2
5.0
p.A
mA
pF
Am9016 (Military)
SWITCHING CHARACTERISTICS over operating range (Notes 2, 3, 5, 10)
Am9016C
Description
Parameters
tAR
RAS LOW to Column Address Hold Time
tASC
Min
Max
Am9016D
Min
Max
Am9016E
Min
Max
Units
200
160
120
ns
Column Address Set-up Time
0
0
0
ns
0
ns
tASR
Row Address Set-up Time
tCAC
Access Time from CAS (Note 6)
tCAH
CAS LOW to Column Address Hold Time
85
tCAS
CAS Pulse Width
185
tCP
Page Mode CAS Precharge Time
100
100
80
ns
tCRP
CAS to RAS Precharge Time
0
0
0
ns
0
0
165
185
75
5,000
165
135
55
5,000
135
ns
ns
5,000
ns
tCSH
CAS Hold Time
300
250
200
ns
tCWD
CAS LOW to WE LOW Delay (Note 9)
145
125
95
ns
tCWL
WE LOW to CAS HIGH Set-up Time
100
85
70
ns
tDH
CAS LOW or WE LOW to Data In Valid Hold Time (Note 7)
85
75
55
ns
tDHR
RAS LOW to Data In Valid Hold Time
200
160
120
ns
tDS
Data In Stable to CAS LOW or WE LOW Set-up Time (Note 7)
0
0
0
tOFF
CAS HIGH to Output OFF Delay
0
tPC
Page Mode Cycle Time
tRAC
Access Time from RAS (Note. 6)
60
0
60
275
295
0
ns
200
ns
225
250
300
ns
50
ns
tRAH
RAS LOW to Row Address Hold Time
45
tRAS
RAS Pulse Width
300
tRC
Random Read or Write Cycle Time
460
tRCD
RAS LOW to CAS LOW Delay (Note 6)
35
tRCH
Read Hold Time
0
0
0
tRCS
Read Set-up Time
0
0
0
tREF
Refresh Interval
tRMW
Read Modify Write Cycle Time
600
500
405
ns
tRP
RAS Precharge Time
150
150
120
ns
tRSH
CAS LOW to RAS HIGH Delay
185
165
135
ns
tRWC
Read/Write Cycle Time
525
425
375
ns
tRWD
RAS LOW to WE LOW Delay (Note 9)
260
210
160
ns
tRWL
WE LOW to RAS HIGH Set-up Time
100
85
70
tT
Transition Time
tWCH
Write Hold Time
85
75
55
tWCR
RAS LOW to Write Hold Time
200
160
120
ns
tWCS
WE LOW to CAS LOW Set-up Time (Note 9)
0
0
0
ns
tWP
Write Pulse Width
85
75
55
ns
35
5,000
250
410
115
35
2
3
OTES
I. Typical values are for TA = 25°C, nominal supply voltages and
nominal processing parameters.
!. Signal transition times am assumed to be 5ns. Transition times
are measured between specified high and low logic levels.
'. Timing reference levels for both input and output signals are the
specified worst-case logic levels.
.. VCC is used in the output buffer only. ICC will therefore depend
only on leakage current and output loading. When the output is
ON and at a logic high level, VCC is connected to the Data Out
pin through an equivalent resistance of approximately 1350. In
standby mode vec may be reduced to zero without affecting
stored data or refresh operations.
. Output loading is two standard TTL loads plus 100pF
capacitance.
Both RAS and CAS must be low to read data. Access timing will
depend on the relative positions of their falliing edges. When
tRCD is less than the maximum value shown, access time depends on RAS and tRAC governs. When tRCD is more than the
maximum value shown access time depends on CAS and tCAC
7.
8.
9.
10.
11.
2-3
25
5,000
50
200
ns
65
ns
375
85
25
2
3
ns
5,000
50
ns
ns
ns
2
3
ms
ns
50
ns
ns
governs. The maximum value listed for tRCD is shown for reference purposes only and does not restrict operation of the part.
Timing reference points for data input set-up and hold times will
depend on what type of write cycle is being performed and will be
the later falling edge of CAS or WE.
At least eight initialization cycles that exercise RAS should be
performed after power-up and before valid operations are begun.
The tWCS, tRWD and tCWD parameters are shown for reference
purposes only and do not restrict the operating flexibility of the
part. When the falling edge of WE follows the falling edge of CAS
by at most tWCS, the data output buffer will remain off for the
whole cycle and an "early write" cycle is defined. When the failing edge of WE follOWS the falling edges of RAS and CAS by at
least tRWD and tCWD respectively, the Data Out from the addressed cell will be valid at the access time and a "read/write"
cycle is defined. The falling edge of WE may also occur at intermediate positions, but the condition and validity of the Data Out
signal will not be known.
Switching characteristics are listed in .alphabetical order.
All voltages referenced to VSS.
Am9016 (Military)
SWITCHING WAVEFORMS
READ CYCLE
tRC
tRAS
-'K
L
!Lm'~
jt-
tAR
I~r
I
tRCD
tRSH
I
I
tCSH
tCAS
~~
-'
:--tCAH_
_tRAH_j
tASR----lADDRESS
~
-tCRP-
\---
tASC---j
ROW ADDRESS
x
COLUMN ADDRESS
/
XXX
XXX
xx
.X
.\.
tRCH-
t--=tRCS-l
=!
TXXXXXXXX/
MMMMNvt"
~X
I'MMhM\.
tCAC
tOFF_
tRAC
DO
WRITE CYCLE (EARLY WRITE)
tRC
tRAS
\.
"Lm,-h-
tAR
I<-
I
tRCD
tCSH
tRSH
:
~K
tASR
ADDRESS
-J--:::-
.~
I-tRAH-
,[
teAS
-tCAH-
-tCRP---
tASC-j-
ROW ADDRESS
XXX XXX
COLUMN ADDRESS
XX
tCWL
(X
X
X
Xl.
XXXX
I--tWcs-\l--tWCHi
XX
I
01
XX
INPUT STABLE
tDS~R
XXX X
XXXX
tRWL
I I
tWCR
DO
XX X
tr
.X
X
I--tDH---=--:l
(OFF)
MOS·193
READ·WRITE/READ·MODIFY·WRITE CYCLE
tRMW
,~'--
tRAS
~r
tAR
~r
~tRCD--l
r
r
tRSH
I - -, - t C R P _
tCSH
tCAS
~\
}f-
-'E-.
f-tRAH_
tASR---i-ADDRESS
moooo
ROW
ADDRESS
..... L...
f-tCAHtASC-i--
~-
X
COLUMN
ADDRESS
_tCWL_
tRWD
J--_tRCS_--j
WE
tCWD
tRWL
I
\
T
t-"--tCACtRAC
-tWP----J
OUTPUT VALID
DO
...;
tDS
--l
I
tOFF
"1\:
-l-
I-tDH
MOS·194
2-4
Am9016 (Military)
SWITCHING WAVEFORMS (Cont.)
RAS ONLY REFRESH CYCLE
tRC
tRAS
I<-
-'\
i\.tRP
IVIHI
tASR-
ADDRESS~
oo __
~I~O~FF~I
f--tRAH
ROW ADDRESS
__________________________________________________________________
MOS-195
PAGE MODE CYCLE
tRAS
tAR
-'K .-
-'\
tASR_T:
ADDRESS
~
-
ROW
ADDRESS
I---LtCAS--
V
\r
- -
I
COLUMN
ADDRESS
-
!l--tCACtRAC
/
COLUMN
,\
ADDRESS
\
t
xx
,XXX
fit
COLUMN
\
XX.,fl\ ADDRESS
t
XX
I-tCAC-
XAXXXXYX
:A
X
-'~f-
r- ~f-
~~
y
xxx
xx
rxx
.-
tWCH
-I
",,---j
tRCS---i-
XA
X
XXX
XX
f-tOFF
r-~
DO
ffl~
-
!--tOFF
r=- ........
XXXXXXX
-Ef-
J~
I-- f--tCAH
tASC----i-
~
-·---tRSH
_tCP_\
-'
_tRAH
I
tPC
I
tCSH I
_tRCD_'_
I
tRCH
I-tWP
--,
I
~y
XAX70
'tXX :XXAXXXXXX x
tRWl
tDS
-
!----tDH-
INPUT STABLE
X-\.
XXXXXXXXXXX
XAAXXXXXXX .XX
tDHR
MOS-196
2-5
Am9016 (Military)
APPLICATION INFORMATION
REFRESH
The Am9016 electrical connections are such that if power is
applied with the device installed upside down it will be permanently damaged. Precautions should be taken to avoid this
mishap.
The Am9016 is a dynamic memory and each cell must be refreshed at least once every refresh interval in order to maintain
the cell contents. Any operation that accesses a row serves to
refresh all 128 cells in the row. Thus the refresh requirement
is met by accessing all 128 rows at least once every refresh
interval. This may be accomplished, in some applications, in
the course of perform ing normal operations. Alternatively,
special refresh operations may be initiated. These special
operations could be simply additional conventional accesses or
they could be "RAS-only" cycles. Since only the rows need to
be addressed, CAS may be held high while RAS is cycled and
the appropriate row addresses are input. Power required for
refreshing is minimized and simplified control circuitry will
often be possible.
OPERATING CYCLES
Random read operations from any location hold the WE line
high and follow this sequence of events:
1) The r~w address is applied to the address inputs and RAS is
switched low.
2) After the row address hold time has elapsed, the column
address is applied to the address inputs and CAS is switched
low.
3) Following the access time, the output will turn on and valid
read data will be present. The data will remain valid as long
as CAS is low.
4) CAS and RAS are then switched high to end the operation.
A new cycle cannot begin until the precharge period has
elapsed.
DATA INPUT/OUTPUT
Data is written into a selected cell by the combination of WE
and CAS while RAS is low. The later negative transition of WE
or CAS strobes the data into the internal register. In a write
cycle, if the WE input is brought low prior to CAS, the data is
strobed by CAS, and the set-up and hold times are referenced
to CAS. If the cycle is a read/write cycle then the data set-up
and hold times are referenced to the negative edge of WE.
Random write operations follow the same sequence of events,
except that the WE line is low for some portion of the cycle. If
the data to be written is available early in the cycle, it will
usually be convenient to simply have WE low for the whole
write operation.
In the read cycle the data is read by maintaining WE in the
high state throughout the portion of the memory cycle in
which CAS is low. The selected valid data will appear at the
output within the specified access time.
Sequential Read and Write operations at the same location can
be designed to save time because re-addressing is not necessary.
A read/write cycle holds WE high until a val id read is established
and then strobes new data in with the falling edge of WE.
After the power is first applied to the device, the internal circuit requires execution of at least eight initialization cycles
which exercise RAS before valid memory accesses are begun.
DATA OUTPUT CONTROL
Any time CAS is high the data output will be off. The output
contains either one or zero during read cycle after the access
time has elapsed. Data remains valid from the access time until
CAS is returned to the high state. The output data is the same
polarity as the input data.
ADDRESSING
14 address bits are required to select one location out of the
16,384 cells in the memory. Two groups of 7 bits each are
multiplexed onto the 7 address lines and latched into the
internal address registers. Two negative-going external clocks
are used to control the mUltiplexing. The Row Address Strobe
(RAS) enters the row address bits and the Column Adpress
Strobe (CAS) enters the column address bits.
The user can control the-output state during write operations
by controlling the placement of the WE signal. In the "early
write" cycle (see note 9) the output is at a high impedance
state throughout the entire cycle.
When RAS is inactive, the memory enters its low power standby mode. Once the row address has been latched, it need not
be changed for successive operations within the same row,
allowing high-speed page-mode operations.
POWER CONSIDERATIONS
RAS and/or CAS can be decoded and used as a. chip select
signal for the Am9016 but overall system power is minimized
if RAS is used for this purpose. The devices which do not
receive RAS will be in low power standby mode regardless
of the state of CAS.
Page-mode operations first establish the row address and then
maintain RAS low while CAS is repetitively cycled and designated operations are performed. Any column address within
the selected row may be accessed in any sequence. The maximum time that RAS can remain low is the factor limiting the
number of page-mode operations that can be performed.
At all times the Absolute Maximum Rating Conditions must
be observed. During power supply sequencing VBB should
never be more positive than VSS when power is applied to VDD.
Multiplexed addressing does not introduce extra delays in the
access path. By inserting the row addrftSs first and the column
address second, the memory takes advantage of the fact that
the delay path through the memory is shorter for column
addresses. The column address does not propagate through the
cell matrix as the row address does and it can therefore arrive
somewhat later than the row address without impacting the
access time.
2-6
Am9016 (Military)
TYPICAL CHARACTERISTICS
>
~
1.2
I
Tc
1.1
...............
c
c
~
= 23°C
1.0
()
cI:
~
C 0.9
c
~
~
I
I
'"
cI:
.............
~
~
1.2
I
Tc = 23°C
~
1.1
II
~
1.0
iil"
III
()
e::
G()
0.9
~
i
0.8
()
e::
0.7
-4.0
14
0.9
I
I
I
0.8
cI:
e::
13
12
11
II
cI:
cI:
0.7
10
1.0
()
cI:
e::
1.1
()
()
()
~
e::
-4.5
-5.0
-5.5
-6.0
0.7
4.0
5.0
4.5
5.5
6.0
VOO SUPPLY VOLTAGE - VOLTS
vee - VOLTS
VCC - VOLTS
Typical Access Time (Normalized)
tRAC Versus
Case Temperature
Typical Operating Current
1001 Versus VOO
Typical Standby Current
1002 Versus VOO
30~--~----~--~----~
1.4
6
~
N
V
1.2
1/
()
1.1
cI:
II:
~
1.0
()
0.9
e::
25~---+----4---~----~
C
!2
/
!::..
1.2
~
N
C
15
!2
25 45 65 85 105125
13
12
11
voo -
T C. CASE TEMPERATURE - °c
~ ~I
12
11
voo -
VOLTS
--
~
13
14
VOLTS
Typical Operating Current
1001 Versus
Case Temperature
Typical Page Mode
Current
1004 Versus VOO
Typical Refresh Current
1003 Versus VOO
--
0.8
0.4
10
14
I
1
1.0
0.6
/v
0.8
-55 -35 -15 5
I
Tc =1 23 °C
cI:
E
/V
()
1.4
TC = 23°C
V
II
!::..
cI:
1.2
III
III
0.8 t---
()
Typical Access Time
(Normalized)
tRAC Versus VCC
Typical Access Time
(Normalized)
tRAC Versus VBB
Typical Access Time
(Normalized)
tRAC Versus VOO
16r---~----~--~----~
voo =
cI:
E
13.2V
cI:
cI:
E
E
C
M
C
!2
!2
5~~~~~~~~~~
-55 -35 -15 5
VOO - VOLTS
T c. CASE TEMPERATURE - °C
Typical Standby Current
1002 Versus
Case Temperature
Typical Refresh Current
1003 Versus
Case Temperature
Typical Page Mode Current
1004 Versus
Case Temperature
1.4
16
Joo 1= 1t2vI
0.6
II
I-- I--
~ 1.0
c 0.8
!2
Joo 1= 1~.2J
14
1.2
N
25 45 65 85 105 125
VOO - VOLTS
~
'"
I'-.....
M
-.....'" r-..... r-....
C
!2
........
12
......
10
......
riC~:37k. I-- I-tR~ ~150Jns
I
tRC
1
r-.....~
0.4
-55 -35 -15 5 25 45 65 85 105125
T c. CASE TEMPERATURE - °c
I
~
75Jns
I
E
-
I I I
6
-55 -35 -15 5
cI:
25 45 65 85 105 125
T c. CASE TEMPERATURE _ °C
6L-~~~~~-L~~~
-55 -35 -15 5 25 45 65 85 105 125
T c. CASE TEMPERATURE - ·C
MOS·197
2-7
Am9016 (Military)
TYPICAL CHARACTERISTICS (Cont.)
Input Voltage Levels
Versus vee
3.0
rJ)
!:i
3.0
Tc = 23°C
VBB = -SV
I
2.S
..J
g;
0
I
1.S
..J
I;:)
g;
11
12
O.S
I
2.0
g
-4.5
-5.0
-5.5
-6.0
Input Voltages Levels
Versus vee
Input Voltage Levels
Versus
Case Temperature
Input Voltage Levels
Versus
Case Temperature
3.0
3.0
VDD = 12v,1
VBB = -5V
rJ)
2.S
!:i
>
vllc iMA1)
..J
W
>
VIH(MIN)-
W
>
w 1.5
..J
VIL
--
I
2.0
..J
W
(~AX)
""-
>
w
;:)
g;
-4.5
-5.0
-S.5
.I.
~ -VIH(MIN)
1.5 -
r--
~
I-
;:)
Q.
1.0
2.0 :;;;::
>
I-
I-
2.5
I
1.S
..J
VDO = 12V
VBB = -5V
~
o
v!HCI(MI~)
0
0.5
-4.0
:
0.5
-4.0
14
13
VBB - VOLTS
..J
~
12
11
VDD - VOLTS
Tc = 23°C
VOD = 12V
2.S
10
I
1.0
g;
VDD - VOLTS
3.0
~
Q.
1.0
14
13
1.5
..J
l-
O.S
10
1
VILC (MAX)
W
>
w
;:)
Q.
1.0
2.0
I
..J
>
w
1.S
VIHCI(MIN)
>
2.0
..J
W
;:)
2.5
!:i
0
>
2.0
IQ.
TC =.23°C
VDO = 12V
rJ)
2.S
!:i
..J
W
>
w
3.0
Tc = 23°C
VBB = -SV
rJ)
0
>
Input Voltage Levels
Versus vee
Input Voltage Levels
Versus vee
VBB - VOLTS
r--
~ 1.0
1
0.5
-55 -35 -15 5 25 4S 65 85 105125
-6.0
~
;:)
I
1.0
=rr.r
0.5
-55 -35 -15 5 25 45 65 85 105125
TC. CASE TEMPERATURE _ °c
TC. CASE TEMPERATURE - °c
TYPICAL CURRENT WAVEFORMS
LONG RAS/CAS
RAS
II
CAS
IBB - mA
L_ ',-J
+100
+80
+60
+40
+20
0
,,\
1\
1"- j\
II\.
(
J
V
V
"
III A
\
I \
\
I \
,-J
J
,
I l
J v
,
~
11
I
t.-..
'4
II
~
I\.
\
I
\
1
'""'-_ J
J
I
\.
I~
\
I
I
\
,\11
III
I II
Vv
......
j
\.
,
I
,/\
I\.iJ ~ \
)1
'I
I \
I
r
""
---
I
{\..
}
I
In
1\ fll ~~
J ' "- '-\..--I
/II
I
+
..-
f\
\
i
I
J\
\
l-
,
,
u
,
\
I
---t-
I
.L1-_1
+20
0
-20
-40
+100
+80
+60
+40
+20
100 - mA
0
ISS - mA
RAS ONLY
!
1\
/ \
J \
I)
V
/I
(
1I 1\
I
I
It
50ns/DIV
MOS·191
2-8
Am9016 (Military)
V-Address Lines
VSS PAD
c=J
o0
0 0 0 0 1
I
0 0 0
X'0 1 0
1 1
Lr
X'
-x ,.co
C\I
~
-
_j~o
Data Array Left
~
0
1
3
7
Data Array Right
1
~
0
15
1
0
31
1
Row Decode Transition
Column Decode Transition
AO
A1
A2
A3
A4
A5
A6
every
every
every
every
every
every
every
64
16
32
8
4
2
4
o1
columns
columns
columns
columns
columns
columns
columns
1 1 1 1 1
63
1 000 0 0 1
0 0
65
1 0
1 1
67
I~
go
jJ
~O
X'
AO
A1
A2
A3
A4
A5
A6
every 64
every 16
every 32
every 8
every 4
every 8
every 8
rows
rows
rows
rows
rows
rows
rows
71
1
~
~
79
0
1
0
95
1
1111111
AO
A1
A2
A3
A4
A5
A6
(64x)
1
1---(16x)
• 11 0
1--,-(32x)
1-(8x)-1 0
1111
0000
1100
0011
1001
0110
I
o
:D
:D
o
o
w
:::
:::
. 10
127
.
• 1
0
0
0
0
1
0
(64x)
0
1--(16x)
11 0
1--(32x)
1-(8x)--1 0
1111
0000
1100
0011
1001
0110
• '1 0
/
I
:D
o
:D
:D
:::
0
:::
0
O'l
O'l
--J
0
:::
.j:>.
:D
:D
0
:D
:D
:::
:::
:::
:::
:j
--J
co,
X-Decode Right
X-Decode Left
TOPOLOGICAL BIT MAP
2-9
• 0
0
0
0
0
1
1
0
co
en
0
j\j
--J
PHYSICAL DIMENSIONS
18-Pin Leadless Chip Carrier
NO.1 LEAD
~~~
",I
lilld
-1
Millimeters
Inches
Reference
Symbol
Min
Max
Min
Max
A
.350
.360
8.89
9.14
8.64
B
.330
.340
8.38
C
.275
.285
6.99
7.24
0
.235
.245
5.97
6.22
E
.285
.295
7.24
7.37
F
.265
.275
6.73
6.99
G
.210
.220
5.33
5.59
H
.170
.180
4.32
4.57
.042
.048
1.07
1.22
K
.012
.018
0.33
0.46
L
.012
.018
0.33
0.46
M
.040
.050
1.02
1.27
N
.020
.030
0.51
0.76
.055
1.14
1.40
P
.045
Q
.008R
R
.012R
S
.090
Notes
0.20R
0.30R
2.29
.110
2.79
Notes:
1. Index area: A notch, identification mark or elongation
shall be used to identify pin 1.
2. 14 spaces.
3. Applies to all four corners.
4. Shaded areas are metallized to facilitate external
connections.
5. 18 locations.
6. No organic or polymeric materials shall be molded to the
package.
16-Pin Hermetic
Min
Max
A
.130
.200
b
.016
.020
bl
.050
.070
C
.009
.011
0
.745
.785
E
.240
.310
El
.290
.320
e
.090
.110
L
.125
.150
Q
.015
.060
Sl
.005
ex
3'
Standard
Lead
Finish
Metallization and Pad Layout
r----1SCAS
--,.",cP~ ··,·dl,"",'••• "·,,
DO
AS
A3
A4
AS
vee
DIE SIZE 0.106" X 0.205"
2-10
Inches
Reference
Symbol
13'
b
Am9016
16,384 x 1 Dynamic· R/W Random Access Memory
DISTINCTIVE CHARACTERISTICS
GENERAL DESCRIPTION
•
•
•
•
•
•
•
•
•
•
•
•
The Am9016 is a high speed, 16k-bit, dynamic, read/write
random access memory. It is organized as 16,384 words by
1 bit per word and is packaged in a standard 16-pin DIP. The
basic memory element is a single transistor cell that stores
charge on a small capacitor. This mechanism requires periodic
refreshing of the memory cells to maintain stored information_
All input signals, including the two clocks, are TTL compatible.
The Row Address Strobe (RAS) loads the row address and the
Column Address Strobe (CAS) loads the column address_ The
row and column address signals share 7 input Iines_ Active
cycles are initiated when RAS goes low, and standby mode is
entered when RAS goes high. In addition to normal read and
write cycles, other types of operations are available to improve
versatility, performance, and power dissipation_
•
High density 16k x 1 organization
Direct replacement for MK4116
Low maximum power dissipation 462mW active, 20mW standby
High speed operation - 150ns access, 320ns cycle
±10% tolerance on standard +12, +5, -5 voltages
TTL compatible interface signals
Three-state output
RAS only, RMW and Page modedocking options
128 cycle refreshing
Unlatched data output
Standard 16-pin, .3 inch wide dual in-line package
Double poly N-channel silicon gate MaS technology
100% MIL-STD-883 reliability assurance testing
The three-state output buffer turns on when the column access
time has elapsed and turns off after CAS goes high. Input and
output data are the same polarity.
BLOCK DIAGRAM
WRITE
__
.
VDD
I
I
-RAS
~
CAS
CLOCK
GENERATOR
NO.1
I
I
MULTIPLEXEO
CLOCK
GENERATOR
I
I
CLOCK
GENERATOR
NO.2
I
~
I
I
---'1'
-
I
WRITE
CLOCKS
1
I
~
I
I
--VSS
--VBB
~
DATA
IN
BUFFER
DATA
OUT
BUFFER
LATCH
RELEASE
I
--VCC
DATA IN
I
r-
DATA OUT
DUMMY CELLS
A6
!
AS
A4
MUX
ADDRESS
INPUT
BUFFERS
(7)
A3
A2
I--
"
r-V
MEMORY ARRAY
I
d~~ I
I
ROW
DECODER
1:128
128 SENSE-REFRESH AMPS
LINES
~-~
!-
j
1 OF 2
DATA
BUS
SELECT
DATA
IN/OUT L.-~
I
Al
--
MEMORY ARRAY
AO
DUMMY CELLS
r-~if3'~~-
r....
MUX
SWITCH
I
~
AG-AS
I
COLUMN DECODERS
1 OF 64
A6
MOS-ll1O
ORDERING INFORMATION
Ambient
Temperature
O°C
~
TA
~
+70°C
Access Time
Package
Type
300ns
250ns
200ns
150ns
Hermetic DIP
Molded DIP
AM9016CDC
AM9016CPC
AM9016DDC
AM9016DPC
AM9016EDC
AM9016EPC
AM9016FDC
AM9016FPC
2-11
Am9016 (Commercial)
CONNECTION DIAGRAM
vee
vss
01
CAS
WE
DO
RAS
A6
AD
A3
A2
A4
Al
AO-A6
CAS
DI
DO
RAS
VDD
VCC
VSS
VBB
WE
AS
voo
vcc
ADDRESS INPUTS
COLUMN ADDRESS STROBE
DATA IN
DATA OUT
ROW ADDRESS STROBE
POWER (+12V)
POWER (+5V)
GROUND
POWER (-5V)
WRITE ENABLE
Top View
Pin 1 is marked for orientation.
MaS·1S1
MAXIMUM RATINGS beyond which useful life may be impaired
Storage Temperature
Ambient Temperature Under Bias
Voltage on Any Pin Relative to VBB
-0.5V to +20V
VDD and VCC Supply Voltages with Respect to VSS
vss -
VSS (VDD - VSS
-1.0V to +15.0V
> OV)
OV
1.0W
Power Dissipation
50 rnA
Short Circuit Output Current
The products described by this specification include internal circuitry designed to protect input devices from damaging accumulation of
static charge. It is suggested nevertheless, that conventional precautions be observed during storage, handling, and use in order to avoid
exposure to excessive voltages.
OPERATING RANGE
Ambient Temperature
VDD
VCC
vee
VSS
ELECTRICAL CHARACTERISTICS over operating range (Notes 1, 11)
Am9016X
Parameters
Description
VOH
Output HIGH Voltage
VOL
Output LOW Voltage·
Test Conditions
IOH= -S.OmA
IOL = 4.2mA
Min.
Max.
Units
2.4
VCC
Volts
VSS
0.40
Volts
Typ.
VIH
Input HIGH Voltage for Address, Data In
2.4
7.0
Volts
VIHC
Input HIGH Voltage for CAS, RAS, WE
2.7
7.0
Volts
VIL
Input LOW Voltage
-1.0
0.80
Volts
IIX
Input Load Current
VSS ... VI ... 7V
-10
10
p.A
IOZ
Output Leakage Current
VSS ... VO ... VCC, Output OFF
-10
10
p.A
ICC
VCC Supply Current
Output OFF (Note 4)
-10
10
p.A
IBB
100
Standby, RAS
VBB Supply CLirrent, Average
VOO Supply Current, Average
CI
Input Capacitance
CO
Output Capacitance
~
VIHC
Operating, Minimum Cycle Time
100
200
Operating
1001
RAS Cycling, CAS Cycling,
Minimum Cycle Times
35
Page Mode
1004
RAS ... VIL, CAS Cycling,
Minimum Cycle Times
27
RAS Only
Refresh
1003
RAS Cycling, CAS ~ VIHC,
Minimum Cycle Times
27
Standby
1002
RAS, CAS, WE
Address, Data In
RAS
~
VIHC
mA
1.S
10
Inputs at OV, f = 1MHz,
Nominal Supply Voltages
S.O
Output OFF
7.0
2-12
p.A
pF
Am9016 (Commercial)
SWITCHING CHARACTERISTICS over operating range (Notes 2, 3, 5, 10)
Am9016C
Description
Parameters
Min
Max
Am9016D
Min
Max
Am9016E
Min
Max
Am9016F
Mi n
Max
U'
mts
tAR
RAS LOW to Column Address Hold Time
200
160
120
95
ns
tASC
Column Address Set-up Time
-10
-10
-10
-10
ns
tASR
Row Address Set-up Time
0
0
0
0
tCAC
Access Time from CAS (Note 6)
tCAH
CAS LOW to Column Address Hold Time
85
tCAS
CAS Pulse Width
185
tCP
Page Mode CAS Precharge Time
100
100
80
tCRP
CAS to RAS Precharge Time
-20
-20
-20
20
ns
165
185
75
10,000
165
135
45
55
10,000
135
ns
100
10,000
100
ns
ns
10,000
60
ns
ns
tCSH
CAS Hold Time
300
250
200
150
ns
tCWD
CAS LOW to WE LOW Delay (Note 9)
145
125
95
70
ns
tCWL
WE LOW to CAS HIGH Set-up Time
100
85
70
50
ns
tDH
CAS LOW or WE LOW to Data In Valid
Hold Time (Note 7)
85
75
55
45
ns
tDHR
RAS LOW to Data In Valid Hold Time
200
160
120
95
ns
tDS
Data In Stable to CAS LOW or
WE LOW Set-up Time (Note 7)
0
0
0
0
ns
tOFF
CAS HIGH to Output OFF Delay
tPC
Page Mode Cycle Time
tRAC
Access Time from RAS (Note 6)
tRAH
RAS LOW to Row Address Hold Time
45
tRAS
RAS Pulse Width
300
tRC
Random Read or Write Cycle Time
460
tRCD
RAS LOW to CAS LCW Delay (Note 6)
35
tRCH
Read Hold Time
0
tRCS
Read Set-up Time
0
tREF
Refresh Interval
0
0
60
295
60
275
250
300
35
10,000
250
35
10,000
85
200
200
25
10,000
150
65
20
ns
ns
10,000
ns
ns
50
0
ns
ns
ns
0
2
2
ns
ns
150
320
0
2
40
20
0
0
0
170
375
0
2
50
25
410
115
0
225
ms
ns
tRMW
Read Modify Write Cycle Time
600
500
405
320
tRP
RAS Precharge Time
150
150
120
100
ns
tRSH
CAS LOW to RAS HIGH Delay
185
165
135
100
ns
tRWC
Read/Write Cycle Time
525
425
375
320
ns
tRWD
RAS LOW to WE LOW Delay (Note 9)
260
210
160
120
ns
tRWL
WE LOW to RAS HIGH Set-up Time
100
85
70
50
IT
Transition Time
tWCH
Write Hold Time
85
75
55
45
ns
tWCR
RAS LOW to Write Hold Time
200
160
120
95
ns
tWCS
WE LOW to CAS LOW Set-up Time
(Note 9)
-20
-20
-20
-20
ns
tWP
Write Pulse Width
85
75
55
45
ns
3
3
50
IIOTES
1. Typical values are for TA = 25°C, nominal supply voltages and
nominal processing parameters.
2. Signal transition times are assumed to be 5ns. Transition times are
measured between specified high and low logic levels.
3. Timing reference levels for both input and output signals are the
specified worst-case logic levels.
4. VCC is used in the output buffer only. ICC will therefore depend only
on leakage current and output loading. When the output is ON and
at a logic high level, VCC is connected to the Data Out pin through
an equivalent resistance of approximately 135f1. In standby mode
VCC may be reduced to zero without affecting stored data or refresh
operations.
5. Output loading is two standard TTL loads plus 100pF capacitance.
6. Both RAS and CAS must be low to read data. Access timing will
depend on the relative positions of their falling edges. When tRCD is
less than the maximum value shown, access time depends on RAS
and tRAC governs. When tRCD is more than the maximum value
shown access time depends on CAS and tCAC governs. The
7.
8.
9.
10.
11.
2-13
50
3
50
3
ns
35
ns
maximum value listed for tRCD is shown for reference purposes
only and does not restrict operation of the part.
Timing reference points for data input set-up and hold times will
depend on what type of write cycle is being performed and will be
the later falling edge of CAS or WE.
At least eight initialization cycles that exercise RAS should be performed after power-up and before valid operations are begun.
The tWCS, tRWD and tCWD parameters are shown for reference
purposes only and do not restrict the operating flexibility of the part.
When the falling edge of WE follows the falling edge of CAS by at
most tWCS, the data output buffer will remain off for the whole cycle
and an "early write" cycle is defined. When the falling edge of WE
follows the falling edges of RAS and CAS by at least tRWD and
tCWD respectively, the Data Out from the addressed cell will be
valid at the access time and a "read/write" cycle is defined. The
falling edge of WE may also occur at intermediate positions, but the
condition and validity of the Data Out signal will not be known.
Switching characteristics are listed in alphabetical order.
All voltages referenced to VSS.
Am9016 (Commercial)
SWITCHING WAVEFORMS
READ CyctE
tRC
tRAS
\
1L,,,~L
tAR
~[-
tRCD-----j
tRSH
I
I
tCSH
tCAS
~K
j?~
I~
!-tRAH_
tASe
tASR-rADDRESS
~
ROW ADDRESS
-tCAH_
------i
_tCRP_
1--
/
COLUMN ADDRESS
X
,,\
~tRCS-l
MMMMN.6(""
tRCH-
[--I
'/
I'CXXXXXXXX
~'\
tCAC
tOFF_
tRAC
DO
MOS-192
WRITE CYCLE (EARLY WRITE)
tRC
tRAS
'\
rL,",~ L
tAR
-'.-
I
tRCD
-'
~
tCAS
"t
~[!--tCAH-
I-tRAH1
;---tCRP-
tASC-j-
tASR---tADDRESS
tRSH
:
tCSH
ROW ADDRESS
COLUMN ADDRESS
.LAX
tCWL
AAA
XX
XAllllA
XXXllA
_tWCs--j
tr
I(X
llXXllX
XXX
XXXAAXXXAAXJ
XXX
.LllXAXX
·tRWL
I
INPUT STABLE
XoX
XX
X
tDS~
DO
J
I I
tWCR
DI
I-tWCH
!--tDH-
tDHR
(OFF)
MOS-193
READ-WRITE/READ-MODIFY-YVRITE CYCLE
tRMWtRAS
-'f\
·C"-
tAR
1-'(-
f----
tRCD---1
(
I
tRSH
r--- : - t C R P _
tCSH
tCAS
~~
J'-
...,'-
-'t"
_tCAH_
!-tRAH_
tASR---t-ADDRESS
~
ROW
ADDRESS
tASC---i-
~
COLUMN
I\PDRESS
I---tCWLtRWL
tRWD
r-tRCS-j
teWD
I
-'i\
WE
I-tCACtRAC
i-'
I--tWP--!
.,
OUTPUT VALID
DO
-'[-
tDS~ ~tDH
I
""\
-l-
tOFF
MOS-l94
2-14
Am9016 (Commercial)
SWITCHING WAVEFORMS (Cent.)
RAS ONLY REFRESH CYCLE
fJ
~------------------tRC------------------~
r--'~-- tRAS -----------l
~i\
'-----
\r-
f-----tRPIVIH)
ADDRESS
~
55 ___
~1~0~FF~)
ROW ADDRESS
__________________________________________________________________________________________________
MOS-195
PAGE MODE CYCLE
tRAS
~
i
Ir-
I r---
I'~
tRCD ,,
')
-
I
ADDRESS
~
-
\-tCAS_J1~
-
1~1r-
jf-
I-- r--- tCAH
__ tRAH
tASC--i-
ROW
ADDRESS
~
COLUMN
ADDRESS
COLUMN
\
IJ\ /
COLUMN
X X,\ ADDRESS
/
. V \.
ADDRESS
'/
IXX
J ~tCAC- -
I--tOFF
I
I
tRAe
r--:lrDO
M~
tRCS--1-
x
xx xxx
XXXXX x
tASH
_ t C P _I
-
tASR-i-
-8-
~---tAR~
XXXXX
---'~~
I
tCAC
I
_tCWL_
tWP
~
I -r- tOFF
'----,.__ :::l
tRCH
--
x
-----j
tWCH
~
XXXXXY
,x
/X'( : x
i
t--
tRCH--j
y
r---
\A
1
I
'(X
x
xx
xli
-tAWL
r-
Xli.
[
XX
XXX
XXXX :XX x T
XAAAXXAA
XXXXX
tDS
-
-tDH-
INPUT STABLE
A
XAXXA
tDHR
MOS-196
2-15
Am9016 (Commercial)
APPLICATION INFORMATION
The Am9016 electrical connections are such that if power is
applied with the device installed upside down it will be permanently damaged. Precautions should be taken to avoid this
mishap.
REFRESH
The Am9016 is a dynamic memory and each cell must be refreshed at least once every refresh interval in order to maintain
the cell contents. Any operation that accesses a row serves to
refresh all 128 cells in the row. Thus the refresh requirement
is met by accessing all 128 rows at least once every refresh
interval. This may be accomplished, in some applications, in
the course of perform ing normal operations. Alternatively,
special refresh operations may be initiated. These special
operations could be simply additional conventional accesses or
they could be "RAS-only" cycles. Since only the rows need to
be addressed, CAS may be held high while RAS is cycled and
the appropriate row addresses are input. Power required for
refreshing is minimized and simplified control circuitry will
often be possible.
OPERATING CYCLES
Random read operations from any location hold the WE line
high and follow this sequence of events:
1) The row address is applied to the address inputs and RAS is
switched low.
2) After the row address hold time has elapsed, the column
address is applied to the address inputs and CAS is switched
low.
3) Following the access time, the output will turn on and valid
read data will be present. The data will remain valid as long
as CAS is low.
4) CAS and RAS are then switched high to end the operation.
A new cycle cannot begin until the precharge period has
elapsed.
DATA INPUT/OUTPUT
Data is written into a selected cell by the combination of WE
and CAS while RAS is low. The later negative transition of WE
or CAS strobes the data into the internal register. In a write
cycle, if the WE input is brought low prior to CAS, the data is
strobed by CAS, and the set-up and hold times are referenced
to CAS. If the cycle is a read/write cycle then the data set-up
and hold times are referenced to the negative edge of WE.
Random write operations follow the same sequence of events,
except that the WE line is low for some portion of the cycle .. If
the data to be written is available early in the cycle, it will
usually be convenient to simply have WE low for the whole
write operation.
In t~e read cycle the data is read by maintaining WE in the
high state throughout the portion of the memory cycle in
which CAS is low. The selected valid data will appear at the
output within the specified access time.
Sequential Read and Write operations at the same location can
be designed to save time because re-addressing is not necessary_
A read/write cycle holds WE high until a valid read is established
and then strobes new data in with the falling edge of WE.
After the power is first applied to the device, the internal circuit requires execution of at least eight initialization cycles
which exercise RAS before valid memory accesses are begun.
DATA OUTPUT CONTROL
Any time CAS is high the data output will be off. The output
contains either one or zero during read cycle after the access
time has elapsed. Data remains valid from the access time until
CAS is returned to the high state. The output data is the same
polarity as the input data.
ADDRESSING
14 address bits are required to select one location out of the
16,384 cells in the memory. Two groups of 7 bits each are
multiplexed onto the 7 address lines and latched into the
internal address registers. Two negative-going external clocks
are used to control the multiplexing. The Row Address Strobe
(RAS) enters the row address bits and the Column Address
Strobe (CAS) enters the column address bits.
The user can control the output state during write operations
by controlling the placement of the WE signal. In the "early
write" cycle (see note 9) the output is at a high impedance
state throughout the entire cycle.
When RAS is inactive, the memory enters its low power standby mode. Once the row address has been latched, it need not
be changed for successive operations within the same row,
allowing high-speed page-mode operations.
Page-mode operations first establish the row address and then
maintain RAS low while CAS is repetitively cycled and designated operations are performed. Any column address within
the selected row may be accessed in any sequence. The maximum time that RAS can remain low is the factor limiting the
number of page-mode operations that can be performed.
POWER CONSIDERATIONS
RAS and/or CAS can be decoded and used as a chip select
signal for the Am9016 but overall system power is minimized
if RAS is used for this purpose. The devices which do not
receive RAS will be in low power standby mode regardless
of the state of CAS.
At all times the Absolute Maximum Rating Conditions must
. be observed. During power supply sequencing VBS should
never be more positive than VSS when power is applied to VDD.
Multiplexed addressing does not introduce extra delays in the
access path. By inserting the row addr~ss first and the column
address second, the memory takes advantage of the fact that
the delay path through the memory is shorter for column
addresses. The column address does not propagate through the
cell matrix as the row address does and it can therefore arrive
somewhat later than the row address without impacting the
access time.
2-16
Am9016 (Commercial)
TYPICAL CHARACTERISTICS
Typical Access Time
(Normalized)
tRAC Versus VOO
Typical Access Time
(Normalized)
tRAC Versus vee
1.2 ....-----,....-1---,-----,,-----..,
1.2
~
II
0
0
:::..
«
u
e:
So
:::..
u
«
~
Te =1 23•c
1
1.1
...............
1.0
~
-.........
0.9
..............
«
e:
12
11
r==""F--f-......-l-=;;;;;;;;J
0.9
~--~----~--~--~
0.8
~--~----~--~--~
13
14
~
II
u
u
:::..
1.1
1.0
u
I
«
II:
5-
I
0.9
u
:::..
u
«
0.7 L...-__--'-____L...-_ _....I...._ _----J
-4.0
-4.5
-5.0
-5.5
-6.0
e:
I
0.8
0.7
4.0
4.5
5.0
6.0
5.5
VBB -. VOLTS
VCC - VOLTS
Typical Access Time
(Normalized)
tRAC Versus
Case Temperature
Typical Operating Current
1001 Versus VOO
Typical Standby Current
1002 Versus VOO
1.1
/
u
/
u
0.9
30.----r----,....---,---_,
/
I
«
1.4.----r----,....---,-----,
Te
Te = 23·C
1.2
25~--_r----~---~--~
~
20 ~--+--+--
«
C
15
o
9
9
C-
e:
~--~----~--~--~
1.2
vee SUPPLY VOLTAGE - VOLTS
II
«
e:ii3"
:::..
u
C- 1.0
~
u
«
= 23·C
ID
1.2
u
1.1
:::.. 1.0
0.8
0.7
10
e:
Te
ID
ID
e:
G"
~
Typical Access Time
(Normalized)
tRAC Versus VCC
= 23·C
~-----J-----~_
E
N
0.8
0.7
-10
20
50
110
80
12
11
13
13
11
14
14
Te. CASE TEMPERATURE - ·C
vee - VOLTS
veo - VOLTS
Typical Refresh Current
1003 Versus VOO
Typical Page Mode
Current
1004 Versus VOO
Typical Operating Current
1001 Versus
Case Temperature
16.----r----.-----,---_,
16....-----r----,....----,---_,
30
1
vee
14~--~----~--~--~
~
12~--+-
25
14~--~----~---r~~
~
12
= 13.2V
«
20 ~
IRC
-
E
-
15 -
= 375n5 - r - -
-
IRC == 500n5
IRC == 750n5
-
10
12
11
13
14
11
0
9
50
80
110
Typical Standby Current
1002 Versus
Case Temperature
Typical Refresh Current
1003 Versus
Case Temperature
Typical Page Mode Current
1004 Versus
Case Temperature
16
1
vee
14
i
I
«
1.0
E
12
M
0.8
20
Te. CASE TEMPERATURE - ·C
1.2
N
5
-10
14
vee - VOLTS
vee = 13.2V
E
13
vee - VOLTS
1.4
«
12
-..............
0.6
0.4
-10
o
9
r--.. -..... .....r--.
20
50
80
10
~ 13.2V
_1
-
1
16....-----,-----,----~--_,
vee
!
= 13.2V
14
IRC = 1375n5
~
12~-~--+_-_+-~
IRC = 500n5
1
10
I IRC
......_=--
~--=t=
= 1750n5
i
110
Te. CASE TEMPERATURE _ ·C
6
-10
I
I
20
50
6L...---~----~--~--~
80
Te. CASE TEMPERATURE _ ·C
110
-10
20
50
80
110
Te. CASE TEMPERATURE - ·C
MOS-197
2-17
Am9016 (Commercial)
TYPICAL CHARACTERISTICS (Cont.)
Input Voltage Levels
Versus VDD
Input Voltage Levels
Versus VDD
3.0
!II
!:i
3.0
Te = 23°C
VBB = -5V
!II
2.5
..J
~
...:J
a.
~
1.0
3.0
11
0.5
-4.0
14
13
-4.5
-5.0
-5.5
-S.O
Input Voltage Levels
Versus
Case Temperature
VDD=4
-
W
VIL
...
:J
!II
-+--
>
I
2.0
a.
-5.5
>
w
..J
...
VBB - VOLTS
1.5 -
- - VIL (MAX) - -
a.
VIH(MIN)- I
-
80
---
1.0
~
50
20
-
:J
I
0.5
·-10
-6.0
2.0 -
..J
W
-
!
I
1.0
~
-
I
VILC (MAX)
...
:J
i
-5.0
0
I
..J
W
>
w 1.5
..J
VDD = 12V
VBB = -5V
2.5
>
VIHCI(MIN)
I
--i--
I
-4.5
!II
!:i
0
-t------
3.0
2.5
!:i
I
(~AX)
I
1.0 -
VDD = 12V
VBB = -5V
I ----,-
VIH (MIN)
I
3.0
I
= 23°C!
..J
0.5
-4.0
12
11
Input Voltage Levels
Versus
Case Temperature
>
w 1.5
..J
~
0.5
10
Input Voltages Levels
Versus vee
>
a.
1.0
~
VBB - VOLTS
2.5 - - i - 2.0 -
a.
..J
VDD - VOLTS
0
I
1.5
...:J
1.0
14
13
I
VILC (MAX)
>
w
VDD - VOLTS
Te
!:i
12
I
2.0
..J
W
1.5
..J
0.5
10
!II
I
..J
W
:J
a.
>
2.0
>
W
1.5
I
VIHC (MIN)
0
I
..J
W
...
!:i
0
2.0
Te = 23°C
VDD = 12V
2.5 1----
!II
>
>
>
w
3.0
Te = 23°C
VBB = -5V
2.5 -
!:i
0
I
Input Voltage Levels
VerstJs vee
0.5
-10
110
Te. CASE TEMPERATURE _ °c
20
50
80
110
Te. CASE TEMPERATURE _ °c
TYPICAL CURRENT WAVEFORMS
RAS
II
[
+so
+40
+20
0
,
ISS - rnA
0
I~
i'
1\
"-
,..,
t....
"-
v
I
I
IA
{\
1-"
In
J'
/ I
/1
n
J " "- \....-.1
-, \J
'-,
rl
I
\
l
J
'I,
1\
r-
/ \
J
11
I
/
r
\
IJ
"
I
I
--'
' 1\
III 'II/
/1\
\..
\
'r-r-l
'
T+-t
II\,
"1
I
/
\
f\
/ \I
)
~
I
III
\
v \
I
,,-.J
1
l-
V
111 A'
\
ip..,1.f\
I
!
+100
+80
+so
+40
+20
II\.
V
1
~~
,
1"\
f'l
I
l _ _ J
L 10- -1/
+20
0
-20
-40
+100
+80
100 - rnA
,
II
CAS
IBB - rnA
RAS ONLY
LONG RAS/CAS
RAS/CAS
II II / V
V"1
III
!\.~
/\
""
\
VV
I
II
(
J \
)
\
I\,
50ns/DIV
MOS-,.
2-18
Am9016 (Commercial)
V-Address Lines
VSS PAD
c=J
o0 o0
0 0 1
I0
x
-~
x .....
0 0
1
O 1 0
1 1
3
~xr
~~
-l~o
se.
--
Data Array Left
~
0
7
Data Array Right
1
0
15
1
0
31
1
Row Decode Transition
Column Decode Transition
AO
A1
A2
A3
A4
A5
A6
every
every
every
every
every
every
every
64
16
32
8
4
2
4
o1
columns
columns
columns
columns
columns
columns
columns
1 1 1 1 1
63
AO
A1
A2
A3
A4
A5
A6
1 0 0 0 0 0 1
0 0 0
65
1 0
1 1
67
I0
go
~~I
I
~0
every
every
every
every
every
every
every
64
16
32
8
4
8
8
rows
rows
rows
rows
rows
rows
rows
71
-~
i~
79
0
95
1
AO
A1
A2
A.3
A.4
A.5
A.6
(64x)
1
1---(16x)
• 1 10
1--.-(32x)
1-(8x)-1 0
1111
0000
1100
0011
1001
0110
I
JJ
o
::E
o
JJ
.
.
10
1 1 1 1 1 1 1
127
o
(64x)
1--(16x)-11°
1--(32x)
1-(8x)-1 0
1111
0000
0011
1100
1001
0110
1
0
0
0
0
1
0
JJ
JJ
JJ
JJ
JJ
0
0
0
0
0
1
1
JJ
o
0
0
0
0
0
0
O'l
O'l
O'l
-...J
:j
-...J
(!)
(!)
N
-...J
::E
::E
w
. 10
I
JJ
o
::E
.
w
~
::E
::E
::E
X-Decode Right
X-Decode Left
TOPOLOGICAL BIT MAP
2-19
::E
U1
::E
Am9016 (Commercial)
Metallization and Pad Layout
vss
01
CAS
2 -----------------,
WE
DO
flAs
AO
5
A2
6
AI
VOO
7--------~
8 _ _ _ _ _ _ _ _ _ _ _ _ _ _---.J
A6
12
A3
L - -_ _ _ _ _ _ _ _ _ _
10
l______________
9
DIE SIZE 0.106" X 0.205"
2-20
13
AS
vee
Am9044 • Am9244
4096 x 1 Static R/W Random Access Memory
DISTINCTIVE CHARACTERISTICS
GENERAL DESCRIPTION
• LOW OPERATING POWER (MAX)
Am9044/Am9244
38SmW (70mA)
Am90L44/Am92L44
27SmW (SOmA)
• LOW STANDBY POWER (MAX)
Am92L44
110mW (20mA)
• Access times down to 200ns (max)
• Military temperature range available to 250ns (max)
• Am9044 is a direct plug-in replacement for 4044
• Am9244 pin and function compatible with Am9044 and
4044 plus CS power down feature
• Fully static - no clocking
• Identical access and cycle time
• High output drive 4.0mA sink current @ O.4V
• TTL identical interface iogic levels
• 100% MIL-STD-883 reliability assurance testing
The Am9044 and Am9244 are high performance, static, NChannel, read/write, random access memories organized as
4096 x 1. Operation is from a single 5V supply, and all input!
output levels are identical to standard TTL specifications. Low
power versions of both devices are available with power savings of about 30%. The Am9044 and Am9244 are the same
except that the Am9244 offers an automatic CS power down
feature.
The Am9244 remains in a low power standby mode as long
as CS remains high, thus reducing its power requirements.
The Am9244 power decreases from 385mW to 165mW in the
standby mode, and the Am92L44 from 275mW to 110mW. The
CS input does not affect the power dissipation of the Am9044.
Data readout is not destructive and the same polarity as data
input. CS provides for easy selection of an individual package
when the outputs are OR-tied. The outputs of 4.0mA for
Am9244 and Am9044 provide increased short circuit current for
improved compacitive drive.
BLOCK DIAGRAM
CONNECTION DIAGRAM
_1_8_
vee
ADDRESS 0
vec
ADDRESS 1
ADDRESS 6
__
9_ GND
MEMORY ARRAY
64 ROWS
64 COLUMNS
ADDRESS 2
ADDRESS 7
ADDRESS 3
ADDRESS 8
ADDRESS 4
ADDRESS 9
ADDRESS 5
ADDRESS 10
DATA OUT
ADDRESS 11
WRITE ENABLE
DIN
11
DATA IN
CHIP SELECT
GND (VSS)
DOUT
cs _ _..........01
WE _8----'_-1
Top View
Pin 1 is marked for orientation.
MOS-256
MOS-257
ORDERING INFORMATION
Acce •• Times
Ambient
Temperature
Package
Type
Plastic
O'C "" TA .. +70'C
Hermetic
-55'C .. TA "" +125'C
Hermetic
ICC
Current
Level
450ns
300ns
250na
200na
450na
300na
250na
200ns
70mA
AM9044BPC
AM9044CPC
AM9044DPC
AM9044EPC
AM9244BPC
AM9244CPC
AM9244DPC
AM9244EPC
SOmA
AM90L44BPC
AM90L44CPC
AM90L44DPC
AM92L44BPC
AM92L44CPC
AM92L44DPC
70mA
AM9044BDC
AM9044CDC
AM9044DDC
AM9244BDC
AM9244CDC
AM9244DDC
SOmA
AM90L44BDC
AM90L44CDC
AM90L44DDC
AM92L44BDC
AM92L44CDC
AM92L44DDC
90mA
AM9044BDM
AM9044CDM
AM9044DDM
AM9244BDM
AM9244CDM
AM9244DDM
SOmA
AM90L44BDM
AM90L44CDM
AM92L44BDM
AM92L44CDM
Am9044
Am9244
2-21
AM9044EDC
AM9244EDC
Am9044 • Am9244
MAXIMUM RATINGS beyond which useful life may be impaired
Storage Temperature
-65°C to +150°C
Ambient Temperature Under Bias
- 55°C to + 125°C
VCC with Respect to VSS
-O.5V to + 7.0V
All Signal Voltages with Respect to VSS
-O.5V to +7.0V
Power Dissipation (Package Limitation)
1.0W
DC Output Current
10mA
The products described by this specification include internal circuitry designed to protect input devices from damaging accumulations
of static charge. It is suggested nevertheless, that conventional precautions be observed during storage, handling and use in order to
avoid exposure to excessive voltages.
OPERATING RANGE
Part Number
Am9044DC/PC
Am90L44DC/PC
Am9244DC/PC
Am92L44DC/PC
Ambient Temperature
O°C ~ TA ~ +70°C
vee
VSS
OV
Part Number
+5.0V ±10%
Am9044DM
Am90L44DM
Am9244DM
Am92L44DM
Description
10H
Output High Current
10L
Output Low Current
Min.
Test Conditions
VOH =2.4V
VOH
= 2AV
1 VCC = 4.5V ·1 70°C
I VCC = 4.5V I 125°C
I TA = +70°C
J TA = +125°C
VOL= OAV
VSS
vee
-55°C ~ TA ~ +125°C
OV
+5.0V ±10%
Am9044XX
Am90L44XX
Am9244XX
Am92L44XX
ELECTRICAL CHARACTERISTICS over operating range
Parameter
Ambient Temperature
Typ.
Max.
Min.
-1.0
-1.0
-A
-.4
4.0
4.0
3.2
3.2
Typ.
Max.
Units
mA
mA
VIH
Input High Voltage
2.0
VCC
2.0
VCC
Volts
VIL
Input Low Voltage
-0.5
0.8
-0.5
0.8
Volts
IIX
Input Load Current
10
/LA
VSS~VI~VCC
10
OAV~VO~VCC
10Z
Output Leakage Current
CI
Input Capacitance (Note 1)
ClIO
1/0 Capacitance (Note 1)
Output Disabled
I TA=+125°C
I TA = +70°C
-50
50
-50
50
-10
10
-10
10
Test Frequency = 1.0MHz
T A = 25°C, All pins at OV
/LA
3.0
5.0
3.0
5.0
5.0
6.0
5.0
6.0
pF
ELECTRICAL CHARACTERISTICS over operating range
Am92L44
Parameter
ICC
IPD
VCC Operating
Supply Current
Max. VCC CS ~ VIL
for Am9244/92L44
Automatic CS Power
Down Cur;ent
Max. Vee
(CS?-VIH)
Am9244
Am90L44
Am9044
Typ. Max. Typ. Max. Typ. Max. Typ. Max. Units
Test Conditions
Description
TA = O°C
50
70
50
70
TA = -55°C
60
80
60
80
TA = O°C
20
30
-
-
TA = -55°C
22
33
-
-
mA
mA
4. The internal write time of the memory is defined by the
overlap of CS low and WE low. Both signals must be low
to initiate a write and either signal can terminate a write by
going high. The data input setup and hold timing should be
referenced to the rising edge of the signal that terminates
the write.
5. Chip Select access time (teo) is longer for the Am9244
than for the Am9044. The specified address access time
will be valid only when Chip Select is low soon enough fOI
teo to elapse.
Notes:
1. Typical values are for TA = 25°C, nominal supply voltage
and nominal processing parameters.
2. For test purposes, not more than one output at a time
should be shorted. Short circuit test duration should not
exceed 30 seconds.
3. Test conditions assume signal transition times of 10ns or
less, timing reference levels of 1.5V and output loading of
one standard TTL gate plus 100pF.
2-22
Am9044 • Am9244
SWITCHING CHARACTERISTICS over operating range (Note 3)
Am9044B
Am9244B
Parameter
Description
Min.
Max.
Am9044C
Am9244C
Min.
Max.
Am9044D
Am9244D
Min.
Max.
Am9044E
Am9244E
Min.
Max.
Units
Read Cycle
tRC
Address Valid to Address Do Not Care Time
(Read Cycle Time)
tA
Address Valid to Data Out Valid Delay
(Address Access Time)
tCO
Chip Select Low to Data Out Valid (Note 5)
tCX
Chip Select Low to Data Out On
tOTD
Chip Select High to Data Out Off
tOHA
Address Unknown to Data Out Unknown Time
450
300
250
450
II Am9044
Am9244
200
250
300
200
100
100
70
70
450
300
250
200
20
20
100
80
ns
20
20
60
60
20
20
20
20
450
300
250
200
200
150
100
100
250
200
150
150
Write Cycle
tWC
Address Valid to Address Do Not Care Time
(Write Cycle Time)
tW
Write Enable Low to
Write Enable High Time (Note 4)
I Am9044
I Am9244
tWR
Write Enable High to Address Do Not Care Time
tOTW
Write Enable Low to Data Out Off Delay
tDW
Data In Valid to Write Enable High Time
0
0
0
100
150
100
100
0
0
0
tDH
Write Enable Low to Data In Do Not Care Time
0
Address Valid to Write Enable Low Time
0
tPD
Chip Select High to Power Low Delay (Am9244 only)
tPU
Chip Select Low to Power High Delay (Am9244 only)
tCW
Chip Select Low to Write Enable High Time
(Note 4)
tWO
Write Enable High To Output Turn On
0
0
200
100
0
0
0
200
150
100
100
250
200
150
0
100
100
I---READ CYCLE-----j
I
IRC
I
150
70
I - - WRITE CYCLE---I
I
IWC
I
POWER DOWN WAVEFORM (Am9244 ONLY)
MOS-258
2-23
ns
0
100
150
SWITCHING WAVEFORMS
I---READ CYCLE---I
I
IRC
I
60
200
tAW
I Am9044
I Am9244
0
60
80
70
Am9044 • Am9244
TYPICAL CHARACTERISTICS
Typical ICC
Versus VCC Characteristics
1.50
Typical tacc
Versus VCC Characteristics
....--,----,-...,.....----r"-...---..----.
1.2
Typical C Load Versus
Normalized tacc Characteristics
1.15
TA = 25·C
1.25 I---t----l--+---+-+--t---I
o
~
C
1.1
S
w
~ 1.0
1.00 1---t-""''''''''''-+---+:=ooo+--=+---1
c
N
:::i 0.751---'l----l1---tc(
1\
::IE
Z
o
1.00
a:
Z
0.9
0.8
4.0
7
4
1.05
. . . . .V
"-
Am9044 AND Am9244
c(
::IE
g 0.50 .-.H-.I'--t-"'o:f--/--t---t----1
4.5
5.0
5.5
1.3
~ 5.0V
VCC
t:!
-I
~m9044 AND Am9244
1.1
c(
V
::IE
a: 1.0
V
0
Z
0.9
0
~
./
S 1.2
V
cw
~
~
c(
V
-25
200
1.1
1.0
"""'
..... ......... ~m9044 AND Am9244
a:
0
Z
..............
0.9
r-........
..............
0.8
0
25
50
70
100
400
300
~ 5.0V
::IE
./
0.8
-55
Am9044 AND Am9244
Normalized ICC
Versus Ambient Temperature
1.2
cw
V
CAPACITANCE LOAD - pF
1.3
u
u
V
0.90
100
6.0
Normalized tacc
Versus Ambient Temperature
VCC
. /V
./
0.95
vee
VCC
1.4
.........
1.10
~
w
TA = 25·C
0.7
125
-55
-25
TA - AMBIENT TEMPERATURE - ·C
25
50
70
.............
100
125
TA - AMBIENT TEMPERATURE - ·C
MOS-259
BIT MAP
A2
Address Designators
External
AO
A1
A2
A3
A4
A5
A6
A7
AS
A9
A10
A11
AO
3
16
A4
AS
4
15
As
Ag
5
6
14
A7
A10
DO
7
13
12
11
A6
Internal
A2
A1
AO
AS
A9
A10
A3
A4
A5
A7
A6
A11
WE
Vss
Figure 1. Bit Mapping Information.
2-24
Cs
A11
01
Am9101/Am91L01/Am2101 FAMILY
256x4 Static R/W Random Access Memories
PART
NUMBER
Am2101
Am2101·2
Am9101A
Am91L01A
Am2101·1
Am9101B
Am91 L01B
Am9101C
Am91 L01C
Am9101D
ACCESS
TIME
1000ns
650ns
500ns
400ns
300ns
250ns
DISTINCTIVE CHARACTERISTICS
FUNCTIONAL DESCRIPTION
•
•
The Am9101/Am91 LOl series of devices are high·performance,
low·power, 1024-bit, static, read/write random access memories.
They offer a wide range of access times including versions as fast
as 200ns. Each memory is implemented as 256 words by 4 bits per
word. This organization permits efficient design of small memory
systems and allows finer resolution of incremental memory depth.
•
•
•
•
•
•
•
•
•
•
•
256 x 4 organization
Low operating power
125mW Typ; 290mW maximum - standard power·
1OOmW Typ; 175mW maximum - low power
DC standby mode reduces power up to 84%
Logic voltage levels identical to TTL
High output drive - two full TTL loads
High noise immunity - full 400mV
Single 5 volt power supply tolerances: ±5% commercial, ±10% military
Uniform switching characteristics - access times insensitive to
supply variations, addressing patterns and data patterns
Both military and commercial temperature ranges available
Two chip enable inputs
Output disable control
Zero address set·up and hold times for simplified timing
100% MI L·STD·883 reliability assurance testing
Am9101 BLOCK
These memories may be operated in a DC standby mode for
reductions of as much as 84 percent of the normal power dissipation.
Data can .be retained with a power supply as low as 1.5 volts. The
low power An'l91 LOl series offer reduced power r,:iissipation during
normal operating conditions and even lower dissipation in the stand·
by mode.
The Chip Enable input control signals act as high order address lines
and they control the write amplifier and the output buffers. The
Output Disable signal provides independent control over the output
state of enabled chips.
These devices are all fully static and no refresh operations or sense
amplifiers or clocks are required. Input and output signal levels are
identical to TTL specifications, providing simplified interfacing and
high noise immunity. The outputs will drive two full TTL loads for
increased fan-out and better bus interfacing capability.
DIAGR~M
CONNECTION DIAGRAM
Top View
ADDRESS 3
32 X 8
STORAGE
ARRAY
32 X8
STORAGE
ARRAY
32 X 8
STORAGE
ARRAY
32 X 8
STORAGE
ARRAY
A5----------------~
A6----------------~
----------------_1
ADDRESS 4
ADDRESS 1
WRITE ENABLE
ADDRESS 0
CHIP ENABLE 1
ADDRESS 5
OUTPUT DISABLE
ADDRESS 6
CHIP ENABLE 2
ADDRESS 7
DATA OUT 4
WE
(GNDI VSS
DATA IN 4
CE1
DATA IN 1
DATA OUT 3
CE2
A7
vce (+5vl
ADDRESS 2
DATA IN 3
DATA OUT 1
OD
DATA OUT 2
DATAIN2
MOS·343
Note: Flat Pack version available in 24-pin package.
'-40S·344
ORDERING INFORMATION
Ambient
Temperature
Specification
Package
Type
Molded DIP
o
OoC to +70 C
Hermetic DIP
Hermetic DIP
i5°C to +125°C
Hermetic Flat Pack
Power
Type
Access Times
1000ns
650ns
P2101
P2101·2
500ns
400ns
300ns
P2101·1
AM9101APC
AM9101BPC
AM9101CPC
Low
AM91 L01APC
AM91L01BCP
AM91 L01CPC
Standard
C2101·1
AM9101ADC
AM9101BDC
AM9101CDC
Low
Standard
AM91L01ADC
AM91L01BDC
AM91L01CDC
AM9101ADM
AM9101BDM
AM9101CDM
Low
Standard
AM91L01ADM
AM91L01BDM
AM9101BFM
AM91L01CDM
!ltandard
C2101
C2101·2
AM9101AFM
AM91L01AFM
Low
2-25
AM91L01BFM
250n5
AM9101DPC
AM9101DDC
f)
Am9101/Am91L01/Am2101 Family
MAXIMUM RATINGS above which the useful-life may be impaired
Storage Temperature
Ambient Temperature Under Bias
-65°C to +150°C
VCC With Respect to Vss, Continuous
-O.5V to +7.0V
DC Voltage Applied to Outputs
DC Input Voltage
-O.5V to +7.0V
-O.5V to +7.0V
Power Dissipation
1.0W
ELECTRICAL CHARACTERISTICS
Test Conditions
Description
Parameters
Am9101/
Am91 L01
Family
Min. Max.
o
T A = oOC to +7o e
Vec = +5.0V ±5%
Am9101PC, Am9101DC
Am91 LOl PC Am91 LOl DC
Am2101
IOH = -200.uA
Am2101
Family
Min. Max.
2.4
Units
Volts
VOH
Output HIGH Voltage
VCC= MIN.
VOL
Output LOW Voltage
VCC = MIN.
VIH
Input HIGH Voltage
2.0
VCC
2.2
VCC
Volts
VIL
Input LOW Voltage
-0.5
0.8
-0.5
0.65
Volts
III
Input Load Current
10
10
.uA
VOUT= VCC
5.0
15
VOUT = O.4V
-10
-50
Am9101A/B
50
IOH = -150.uA
2.2
IOL = 3.2mA
ILO
VCE = VIH
TA = 25°C
ICCl
Data out open
VCC = Max.
Power Supply Current
VIN = VCC
TA = O°C
ICC2
Am91 01 C/D/E
55
Am91L01A/B
31
Am91L01C
34
Am9101A/B
55
Am91 01 C/D/E
60
Am91L01A/B
33
Am91 L01C
36
ELECTRICAL CHARACTERISTICS
Parameters
Volts
0.45
VCC = MAX., OV .;;; VIN .;;; 5.25V
Output Leakage Current
Am9101DM, Am9101FM
Am91 L01DM, Am91 LOl FM
0.4
IOL = 2.0mA
Description
60
mA
70
Am9101/
Am91 L01
Family
Min.
Max.
TA = _55°C to +125°e
Vee = +5.0V ±10%
Test Conditions
.uA
VCC =4.75V
2.4
VCC = 4.5V
2.2
Units
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
0.4
Volts
VIH
Input HIGH Voltage
2.0
VCC
Volts
VIL
Input LOW Voltage
-0.5
0.8
Volts
III
Input Load Current
VCC = MAX., OV';;; VIN';;; 5.5V
10
.u A
ILO
Output Leakage Current
VCE = VIH
IOH = -200.uA
VCC = MIN., IOL = 3.2mA
TA = 25°C
ICCl
Data out open
VCC = Max.
Power Supply Current
VIN = VCC
TA = _55°C
ICC3
Volts
VOUT= VCC
10
VOUT =0.4V
-10
Am9101A/B
50
Am9101C
55
Am91 L01A/B
31
Am91 L01C
34
Am9101A/B
60
Am9101C
65
Am91 L01A/B
37
Am91 L01C
40
.uA
mA
CAPACITANCE
Parameters
CIN
Description
Input Capacitance, VIN
Test Conditions
= OV
TA
COUT
Output Capacitance, VOUT
= 25°C, f = lMHz
= OV
2-26
Typ.
Max.
Am2101
4.0
8.0
Am9101 /Am91 L01
3.0
6.0
Am2101
8.0
12
Am9101/Am91 L01
6.0
9.0
Units
pF
pF
Am9101/Am91L01/Am2101 Family
SWITCHING CHARACTERISTICS
over operating temperature and voltage range
Output Load = 1 TTL Gate + 100pF
TA = 0 to 70°C
Transition Times = 10ns
TA = -55 to +125°C
Input Levels, Output References = O.SV and 2.0V
2101
Parameters
Description
Vcc = +5V ±5%
Vcc = +5V ±10%
2101-2
9101A
91L01A
2101-1
91018
91L018
9101C
91L01C
91010
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Units
300
400
250
tRC
Read Cycle Time
tA
Access Time
1000
650
500
500
400
300
250
ns
tco
Chip Enable to Output
ON Delay (Note 1)
SOO
400
350
200
175
150
125
ns
too
Output Disable to Output
ON Delay
700
350
300
175
150
125
100
ns
toH
Previous Read Data Valid with
Respect to Address Change
0
tOF1
Output Disable to Output
OFF Delay
0
200
0
150
0
150
5.0
125
5.0
100
5.0
100
5.0
75
ns
tOF2
Chip Enable to Output
OFF Delay
0
200
0
150
0
150
10
125
10
125
10
100
10
100
ns
1000
650
500
0
500
40
0
40
40
ns
30
ns
twe
Write Cycle Time
1000
650
500
500
400
300
250
ns
tAW
Address Set-up Time
150
150
100
0
0
0
0
ns
twp
Write Pulse Width
750
400
300
175
150
125
100
ns
tcw
Chip Enable Set-up Time
(Note 1)
900
550
400
175
150
125
100
ns
tWR
Address Hold Time
50
50
50
0
0
0
0
ns
tow
Input Data Set-up Time
700
400
280
150
125
100
85
ns
tOH
Input Data Hold Time
100
100
100
0
0
0
0
ns
Note: 1. Both CE1 and CE2 must be true to enable the chip.
SWITCHING WAVEFORMS
READ CYCLE
WRITE CYCLE
'RC
I
ADDRESS~
~
I
I
CRTPENABLE 1
CHIP ENABLE 2
WRITE ENABLE
OUTPUT DISABLE
~
I
I
t
f
I
I
C
\
1-
I
I
f
~'AW
LI
1
~~'OD4
'WP
1:
A,o,,~I
4-'OH
, .OUTPUT VALID
'A
'cw
I
'r»------1
'00
DATA OUT
/
'
I
I
I
f
L
--j
'wc
I
I
.:::~
I
I
-------
r,,.l-,,"
~
DATA IN
1\'WR~
f
:
DATA INPUT STABLE
~
MOS·304S
2-27
Am9101/Am91L01/Am2101 Family
CONNECTION DIAGRAM
Top View
Flat Package
VCC (+5V)
ADDRESS 3
24
ADDRESS 2
23
ADDRESS 4
ADDRESS 1
22
WRITE ENABLE
ADDRESS 0
21
CHIP ENABLE 1
ADDRESS 5
20
DUTPUT DISABLE
ADDRESS 6
19
CHIP ENABLE 2
ADDRESS 7
lB
DATA OUT 4
(GND) VSS
17
DATA IN 4
16
DATA OUT 3
NC
NC
10
15
DATA IN 3
DATA IN 1
11
14
DATA OUT 2
DATA OUT 1
12
13
DATA IN 2
Pin 1 is marked for orientation.
MOS·346
teo Access Time from Chip Enable. The minimum time during
which the chip enable must be LOW prior to reading data on
the output.
tOH Minimum time which will elapse between change of
address and any change of the data output.
tOF1 Time delay between output disable HIGH and output
data float.
tOF2 Time delay between chip enable OFF and output data
float.
twe Write Cycle Time. The minimum time required between
successive address changes while writing.
tAW Address Set·up Time. The minimum time prior to the
falling edge of the write enable during which the address inputs
must be correct and stable.
twp The minimum duration of a LOW level on the write enable
guaranteed to write data.
tWR Address Hold Time. The minimum time after the rising
edge of the write enable during which the address must remain
steady.
tow Data Set-up Time. The minimum .tLme that the data input
must be steady prior to the rising edge of the write enable.
tOH Data Hold Time. The minimum time that the data input
must remain steady after the rising edge of the write enable.
tew Chip Enable Time during Write. The minimum duration
of a LOW level on the Chip Select prior to the rising edge of
WE to guarantee writing.
DEFINITION OF TERMS
FUNCTIONAL TERMS
CE1, CE2 Chip Enable Signals. Read and Write cycles can be
executed only when both CE1 is low and CE2 is high.
WE Active LOW Write Enable. Data is written into the memory
if WE is LOW and read from the memory if WE is HIGH.
Static RAM A random access memory in which data is stored
in .bistable latch circuits. A. static memory will store data as
long as power is supplied to the chip without requiring any
special clocking or refreshing operations.
N-Channel An insulated gate field effect transistor technology
in which the transistor source and drain are made of N-wpe
material, and electrons serve as the carriers between the two
regions. N-Channel transistors exhibit lower thresholds and
faster switching speeds than P-Channel transistors.
SWITCHING TERMS
too Output enable time. Delay time from falling edge of 00
to output on.
tRe Read Cycle Time. The minimum time required between
successive address changes while reading.
tA Access Time. The time delay between application of an
address and stable data on the output when the chip is enabled.
2-28
Am9101/Am91 L01/Am2101 Family
POWER DOWN STANDBY OPERATION
large system, memory pages not being accessed can be
placed in standby to save power. A standby recovery time
must elapse following restoration of normal power before
the memory may be accessed.
To ensure that the output of the device is in a high impedance OFF state during standby, the chip select should
be held at VIH or VCES during the entire standby cycle.
The Am9101/Am91 L01 Family is designed to maintain
storage in a standby mode. The standby mode is entered by
lowering Vcc to around 1.5-2.0 volts (see table and graph
below). When the voltage to the device is reduced, the
storjlge cells are isolated from the data lines, so their contents will not change. The standby mode may be used by a
battery operated backup power supply system, or, in a
EJ
STANDBY OPERATING CONDITIONS OVER TEMPERATURE RANGE
Description
Parameters
Min.
Test Conditions
VCC in Standby Mode
VpD
VPD = 2.0V
ICC in Standby Mode
TA = -55°C
All Inputs = VPD
VPD = 1.5V
Am91 LOl
Am9101
VPD = 2.0V
Am91LOl
Am9101
Rate of Change of VCC
Standby Recovery Time
Chip Deselect Time
CE Bias in Standby
dv/dt
tR
tcp
VCES
30
T A =1 250e I
25
INPUTS = 5.0V
Am9101
20
E
I
/
15
r-
.....J
q:
--- --
f
u
~
10
25
31
RECOVERY
24
WRITE
\
20
q:
E
I
I
_0
~
zq:
.J
18
16
14
12
8
1---------,
ADDRESS 2 2 - - - - - - ,
I
22
Vee (+5VI
ADDRESS4
ADDRESS6
6
ADDRESS 7
7
20
WRITE ENABLE
19
CHIP ENABLE 1
18
OUTPUT DISABLE
17
CHIP ENABLE 2
1.0
J
HIGH
~ STATE
\
'\.
....,...."
VOUT-VOLTS
Typical Power Supply Current
Versus Ambient Temperature
30
- -- "
I °
TA = 70 e
q:
I
TA = 25°e
\
t~ow
~
Vee=IMAX.-
28
26
ADDRESS 0 4
Vee = 4.75V
o
o
1.05
ADDRESS 1 3
\
I
STAr
Access Time
Versus Vcc Normalized·
to Vce = +5.0 Volts
21
/'
\/
L
10
+
o
o
Metallization and Pad Layout
5
V/).LS
11\
I \
Vee -VOLTS
ADDRESS 5
mA
ns
ns
Volts
22
/
READ OR
CYCLE
ADDRESS 3
mA
31
41
28
34
34
46
1.0
Typical Output Current
Versus Voltage
0
II
STANDBY MODE
11
13
13
17
11
13
13
17
Units
tRC
0
VPD
Typical Power Supply Current
Versus Voltage
DESELECT
CHIP
Max.
Am91LOl
Am9101
Am91L01
Am9101
VPD = 1.5V
TA = O°C
All Inputs = VPD
IpD
Typ.
1.5
~
24
q:
E
I
0.95
u
!:?
..........
r--....
22
-.......
~
20
18
--
16
(GNDI VSS
0.90
14
12
B
DATA IN 211 - - - - - - '
DATA OUT 4
15
DATA IN 4
14
DATA OUT 3
13
L------12
DATA IN 3
DATAOUT2
DATA IN 1 9 - - - - - - '
DATAOUT110--------'
16
0.85
4.0
4.5
5.0
Vee - VOLTS
5.5
6.0
10
o
25
50
75
TA - AMBIENT TEMPERATURE - °e
DIE SIZE 0.132" X 0.131"
(Pin numbers are for DIP configurations only)
MOS·347
2-29
Am9101/Am91L01/Am2101 Family
APPLICATIONS
/4
114
DATA IN {
11281TSI
I!.. 4
/
ADDRESS
10-71
01
WE
READ!
WRITE
CONTROL
DO
......
1
MEMORY
SYSTEM
DISABLE
ISTANDBYI
DO
~
WE
Am91L01
256 X4
ffi
CE2
OD
DO
00
~
I
~
1
DO
00
I
A
WE
Am91LDI
256 X 4
WE
Am91LOI
256 X4
ffi
CE2
CE2
f
00
DO
~
I
DATA OUT
Am91LOI
256 X 4
ffi
CE2
00
~
DI
DI
A
WE
OD
~
~
I
01
ffi
Am91LOI
256X 4
ffi
CE2
A
'----
DI
A
WE
Am91LOI
256 X 4
CE2
-
I
DI
A
WE
DO
* L-
I
01
A
C=D 1 ......
00
~
I
V
ffi
-
CE2
00
~
Am91LOI
256 X 4
ffi
CE2
Jr-D
WE
Am91LOI
256 X 4
ffi
CE2
ADDRESS 8
01
A
WE
Am91LOI
256 X4
ffi
00
ADDRESS 9
01
A
A
v-
I
I
1
t-...
/8
/
00
DO
~
4
14
I
I
J-
DATA
OUT
I
I
DO
~
41 DATA OUT
I
:1
OUTPUT
STROBE
Am25LS07
Am25LS07
6·BIT REGISTER 6·BIT REGISTER
f6
f6
MEMORY SYSTEM
768 WORDS BY 12 BITS PER WORD
"'05-34
Typical tA Versus
Ambient Temperature
Typical V1N Limits
Versus Ambient Temperature
r-----r----;----,
300
1.61-----f----+-------J
250
I.B
Typical tA Versus CL
260
Vee = MIN.
240
,/
220
~
1.4 I - - - - - + - - - - j - - - - - I
I
200
:!1.21-------+----+--~
~
~
------
I
200
V
:!lBO
150
./
./"
,/
/'
160
1.0 '--_ _--..l._ _ _....l..._ _---'
75
o
25
50
T A - AMBIEN'r TEMPERATURE - °e
100
o
140
50
25
75
TA - AMBIENT TEMPERATURE - °e
o
100
200
300
400
500
600
eL - pF
MOS
2-30
Am9111/Am91L11/Am2111 FAMILY
256x4 Static R/W Random Access Memories
PART
NUMBER
Am2111
Am2111-2
Am9111A
Am91 L11A
Am2111-1
Am9111B
Am91L11B
Am9111C
Am91L11C
Am9111D
ACCESS
TIME
1000ns
650ns
500ns
400ns
300ns
250ns
DISTINCTIVE CHARACTERISTICS
FUNCTIONAL DESCRIPTION
•
•
The Am9111/Am91 L 11 series of devices are high performance,
low power, 1024-bit, static, read/write random access memories.
They offer a wide range of access times including versions as fast as
200ns. Each memory is implemented as 256 words by 4 bits per
word. This organization permits efficient design of small memory
systems and allows finer resolution of incremental memory depth.
The input data and output data signals are bussed together to share
common I/O pins. This feature not only decreases the package size,
but helps eliminate external logic in bus-oriented memory systems.
•
•
•
•
•
•
•
•
•
•
•
256 x 4 organization for small memory systems
Low operating power dissipation
125mW Typ; 290mW maximum - standard power
1 OOmW Typ; 175mW maximum - low power
DC standby mode reduces power up to 84%
Logic voltage levels identical to TTL
High output drive - two full TTL loads
High noise immunity - full 400mV
Single 5 volt power supply tolerances: ±5% commercial, ±10% milit~ry
Uniform switching characteristics - access times insensitive to
supply variations, addressing patterns and data patterns
Both military and commercial temperature ranges available
Bussed input and output data ori common pins.
Output disable control
Zero address set-up and hold times for simplified timing
100% MIL-STD-883 reliability assurance testing
These memories may be operated in a DC standby mode for
reductions of as much as 84% of the normal power dissipation. Data
can be retained with a power supply as low as 1.5 volts. The low
power Am91 L 11 series offer reduced power dissipation during
normal operating conditions and even lower dissipation in the standby mode.
The Chip Enable input control signals act as high order address
lines and they control the write amplifier and the output buffers.
The Output Disable signal provides independent control over the
output state of enabled chips.
These devices are all fully static and no refresh operations or sense
amplifiers or clocks are required. Input and output signal levels are
identical to TTL specifications, providing simplified interfacing and
high noise immunity. The outputs· will drive two full TTL loads for
increased fan-out and better bus interfacing capability.
Am9111 BLOCK DIAGRAM
32X8
STORAGE
ARRAY
32X8
STORAGE
ARRAY
32X8
STORAGE
ARRAY
CONNECTION DIAGRAM
Top View
A5--------------~
A6--------------~
ADDRESS 2
ADDRESS 4
ADDRESS'
WRITE ENABLE
ADDRESS 0
~
ADDRESS 5
DATil 1/04
ADDRESS r;
DATA 1/0 3
WE
ADDRESS 7
DATA 1/02
GEl
(GND) VSS
m
A7--------------~
vce (+5 V)
ADDRESS 3
32X8
STORAGE
ARRAY
DATA I/O,
CHIP ENABLE 2
OUTPUT DISABLE
OD
~-r----~----~-----.~~
MOS-350
Note: Flat Pack version available in 24-pin package.
MOS-351
ORDERING INFORMATION
Ambient
Temperature
Specification
Package
Type
Molded DIP
o
OOC to +70 C
Power
Type
Standard
Access Times
1000ns
P2111
650ns
P2111-2
Low
Hermetic DIP
Hermetic DIP
5°C to +125°C
Hermetic Flat Pack
Standard
C2111
C2111-2
Low
Standard
500ns
P2111-1
AM9111APC
AM91LllAPC
C2111-1
AM9111ADC
AM91L11ADC
AM9111ADM
AM91L11ADM
Low
Standard
Low
AM9111AFM
AM91Ll1AFM
2-31
400ns
300ns
AM9111BPC
AM9111CPC
AM91L11BPC
AM91L11CPC
AM9111BDC
AM9111CDC
AM91L11BDC
AM9111BDM
AM91Ll1BDM
AM9.111BFM
AM91L11CDC
AM9111CDM
AM91L11CDM
AM91Ll1BFM
250ns
AM9111DPC
AM9111DDC
Am9111/Am91L11/Am2111 Family
MAXIMUM RATINGS above which the useful life may be impair'ed
Storage Temperature
Ambient Temperature Under Bias
VCC With Respect to VSS, Continuous
-O.5V to +7.0V
DC Voltage Applied to Outputs
DC Input Voltage
-O.5V to +7.0V
-O.5V to +7.0V
Power Dissipation
1.0W
ELECTRICAL CHARACTERISTICS
Description
Parameters
Am9111/
Am91 L 11
Family
Min. Max.
T A ~ o°c to +70°C
VCC ~ +5.0V ±5%
Am9111 PC, Am9111 DC
Am91 L 11 PC, Am91 L 11 DC
Am2111
Test Conditions
VOH
Output HIGH Voltage
VCC
= MIN.
VOL
Output LOW Voltage
VCC
= MIN.
= -200/.LA
10H = -150/.LA
10L = 3.2mA
10L = 2.0mA
10H
Am2111
Family
Min. Max.
2.4
Units
Volts
2.2
0.4
Volts
0.45
VIH
Input HIGH Voltage
2.0
VCC
2.2
VCC
Volts
VIL
Input LOW Voltage
-0.5
0.8
-0.5
0.65
Volts
III
Input Load Current
10
10
pA
ILO
VCC
= MAX., OV
.;; VIN .;; 5.25V
= VCC
VOUT = O.4V
5.0
15
-10
-50
Am9111A/B
50
VOUT
I/O Leakage Current
VCE '= VIH
TA = 25°C
ICC1
Power Supply Current
Data out open
VCC = Max.
VIN = VCC
ICC2
TA
= O°C
Am9111 C/D/E
55
Am91 L11A/B
31
Am91L11C
34
Am9111A/B
55
Am9111 C/D/E
60
Am91 L11A/B
33
Am91L11C
36
ELECTRICAL CHARACTERISTICS
Am9111 DM,.Am9111 FM
Am91 L 110M, Am91 L11 FM
Parameters
VCC = +5.0V ±10%
Description
Test Conditions
= 4.75V
VCC = 4.5V
VCC
= -200j..lA
60
mA
70
Am9111/
Am91L11
Family
Max.
Min.
TA = _55°C to +125°C
/.LA
Units
2.4
VOH
Output HIGH Voltage
VOL
Output LOW Voitage
VIH
Input HIGH Voltage
2.0
VCC
Volts
VIL
Input LOW Voltage
-0.5
0.8
Volts
III
Input Load Current
10
/.LA
ILO
Output Leakage Current
10H
VCC = MIN., 10L = 3.2mA
VCC
Vcr
= MAX., OV';;
0.4
VIN .;; 5.5V
VOUT
= VIH
= VCC
TA = 25°C
Power Supply Current
-10
Am9111A/Am9111 B
50
Am9111C
55
Am91 L11A/Am91 L1,1B
31
Data out open
VCC = Max.
Am91 L11C
34
VIN =VCC
Am9111 A/Am9111 B
60
TA = -55°C
ICC3
Volts
10
VOUT = O.4V
ICC1
Volts
2.2
Am9111C
65
Am91 L11A/Am91 L 11B
37
Am91L11C
40
/.LA
mA
CAPACITANCE
Parameters
CIN
Description
Test Conditions
Input Capacitance, VIN = OV
TA
COUT
= 25°C, f = 1 mHz
Output Capacitance, VOUT = OV
2-32
Typ.
Max.
Am2111
4.0
8.0
Am9111/Am91 L11
3.0
6.0
Am2111
10
15
Am9111/Am91 L11
8.0
11
Units
pF
pF
Am9111/Am91L11/Am2111 Family
SWITCHING CHARACTERISTICS over operating temperature and voltage range
Output Load = 1 TTL Gate + 100pF
TA = 0 to 70°C
Transition Times = 10ns
TA = -55 to +125°C
Input Levels, Output References = 0.8V and 2.0V
2111
Parameters
Description
Vee = +5V ±5%
Vee = +5V ±10%
2111-2
9111A
91L11A
2111-1
91118
91L118
9111C
91L11C
91110
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Units
tRC
Read Cycle Time
tA
Access Time
1000
650
500
500
400
300
250
ns
teo
Chip Enable to Output
ON Delay (Note 1)
800
400
350
200
175
150
125
ns
too
Output Disable to Output
ON Delay
700
350
300
175
150
125
100
ns
toH
Previous Read Data Valid with
Respect to Address Change
0
tOF1
Output Disable to Output
OFF Delay
0
200
0
150
0
150
5.0
125
5.0
100
5.0
100
5.0
75
ns
tOF2
Chip Enable to Output
OFF Delay
0
200
0
150
0
150
10
150
10
125
10
125
10
100
ns
1000
650
500
0
400
500
40
0
300
40
250
40
ns
ns
30
twc
Write Cycle Time
1000
650
500
500
400
300
250
tAW
Address Set-up Time
150
150
100
0
0
0
0
ns
twp
Write Pulse Width
750
400
300
175
150
125
100
ns
tew
Chip Enable Set-up Time
(Note 1)
900
550
400
175
150
125
100
ns
tWR
Address Hold Time
50
50
50
0
0
0
0
ns
tow
Input Data Set-up Time
700
400
280
150
125
100
85
ns
tOH
Input Data Hold Time
100
100
100
0
0
0
0
ns
ns
ote: 1. Both CE1 and CE2 must be LOW to enable the chip.
SWITCHING WAVEFORMS
READ CYCLE
WRITE CYCLE
Ii---------IRC--------l--------IWC-------~I
ADDRESS
I
C
H
I P E2N A B L E 1 - - : - - - \
CHIP
ENABLE
(NOTE 1)
I
WRITE ENABLE
OUTPUT DISABLE
C
==:l--------.~
I
f
I \
I
~IAW
I·
ICW,
I
~r-:---~I~.----------:-I-----I--"-'\\
L~~~~~-4;~
twp
I
I~J-
Ifr-----tWR
-----t--r--I."
DATA I/O
i-------IA-------l
MOS-352
2-33
fI
Am9111/Am91L11/Am2111 Family
CONNECTION DIAGRAM
Top View
Flat Package
VCC (+5V)
ADDRESS 3
ADDRESS 2
ADDR!,SS 4
ADDRESS'
NC
ADDRESS 0
WRITE ENABLE
ADDRESS 5
CHIP ENABLE'
ADDRESS 6
DATA 1/04
NC
DATA 1/03
ADDRESS 7
DATA 1/02
NC
DATA 110,
NC
NC
NC
CHIP ENABLE 2
(GND) VSS
OUTPUT DISABLE
Pin 1 is marked for orientation.
MOS-353
teo
Access Time from Chip Enable. The minimum time during
which the chip enable must be LOW prior to reading data on
the output.
tOH Minimum time which will elapse between change of
address and any change of the data output.
tOF1 Time delay between output disable HIGH and output
data float.
tOF2 Time delay between chip enable OFF and output data
float.
DEFINITION OF TERMS
FUNCTIONAL TERMS
CE 1, CE2 Chip Enable Signals. Read and Write cycles can be
executed onTy when both CE 1 and CE2 are LOW.
WE Active LOW Write Enable. Data is written into the memory
if WE is LOW and read from the memory if WE is HIGH.
Static RAM A random access memory in which data is stored
in bistable latch circuits. A. static memory will store data as
long as power is supplied to the chip without requiring any
special clocking or refreshing operations.
twe Write Cycle Time. The minimum time required between
successive address changes while writing.
tAW Address Set-up Time. The minimum time prior to the
falling edge of the write enable during which the address inputs
must be correct and stable.
twp The minimum duration of a LOW level on the write enable
guaranteed to write data.
tWR Address Hold Time. The minimum time after the rising
edge of the write enable during which the address must remain
steady.
tow Data Set-up Time. The minimum time that the data input
must be steady prior to the rising edge of the write enable.
N-Channel An insulated gate field effect transistor technology
in which the transistor source and drain are made of N-type
material, and electrons serve as the carriers between the two
regions. N-Channel transistors exhibit lower thresholds and
faster switching speeds than P-Channel transistors.
SWITCHING TERMS
too
Output enable time. Delay time from falling edge of 00
to output on.
tRe Read Cycle Time. The minimum time required between
successive address changes while reading.
tA Access Time. The time delay between application of an
address and stable data on the output when the chip is enabled.
tOH Data Hold Time. The minimum time that the data inpu1
must remain steady after the rising edge of the write enable.
Chip Enable Time during Write. The minimum duratior
of a LOW level on the Chip Select prior to the rising edge o·
WE to guarantee writing.
tew
2-34
Am9111/Am91L11/Am2111 Family
POWER DOWN STANDBY OPERATION
The Am9111/Am91 L 11 Family is designed to maintain
storage in a standby mode. The standby mode is entered by
lowering VCC to around 1.5-2.0 volts (see table and graph
below). When the voltage to the device is reduced, the
storage cells are isolated from the data lines, so their
contents will not change. The standby mode may be used
by a battery operated backup pewer supply system, or, in a
large system, memory pages not being accessed can be
placed in standby to save power. A standby recovery time
must elapse following restoration of normal power before
the memory may be accessed.
To ensure that the output of the device is in a high impedance OFF state during standby, the chip select should
be held at VIH or VCES during the entire standby cycle.
STANDBY OPERATING CONDITIONS OVER TEMPERATURE RANGE
Parameters
Description
Test Conditions
Min.
VCC in Standby Mode
VPD
Max.
Am91L11
11
25
Am9111
13
31
VPD = 2.0V
Am91 L11
13
31
Am9111
17
41
VPD = 1.5V
Am91L11
11
28
Am9111
13
34
Am91 L11
13
34
Am9111
17
VPD = 1.5V
TA = O°C
All Inputs = VpD
ICC in Standby Mode
IpD
Typ.
Units
1.5
TA = -55~C
All Inputs = VPD
VPD = 2.0V
mA
mA
46
dv/dt
Rate of Change of VCC
tR
Standby Recovery Time
tcP
Chip Deselect Time
0
ns
VCES
CE Bias in Standby
VpD
Volts
1.0
ns
Typical Power Supply Current
Versus Voltage
Typical Output Current
Versus Voltage
24
30
TA = 25°e
25
INPUTS = 5.0V
Am9111
20
r"" ~
~
STANDBY MODE
RECOVERY
E
I
I
lB
Vcc (+5V)
17
ADDRESS 4
ADDRESS 1
ADDRESS 0
3
rgf~~~~iii~-16
WRITE ENABLE
15
CHIP ENABLE 1
4
14
ADDRESS 5
DATA 1/0 4
~
z
«
I
I
10
\
I
\
,
HIGH
\ STATE
7~ow
0
\
STATE
2
2
3
o
o
4
"-"i-...
Vee- VOLTS
VOUT-VOLTS
Access Time
Versus Vee Normalized
to Vee = +5.0 Volts
Typical Power Supply Current
Versus Ambient Temperature
1.05
I
-
°
TA = 70 e
1.0
~
Vee = 4.75V
TA = 25'e
11\
+'
o
o
~
«
/'
\1/
I \
14
12
..J
I
Metallization and Pad Layout
ADDRESS 2
_0
18
16
/
READ OR
WRITE
CYCLE
ADDRESS 3
20
«
I
10
\
22
~
/..J
DESELECT
CHIP
VIps
tRC
~
30
28
~
26
.............
24
«
22
I
20
1l
18
E
0.95
5
I
Vee=MAX.-
............
r--
-- -r-
16
0.90
ADDRESS 6
14
12
=~1IJ+--13
ADDRESS 7
(GND) VSS
OUTPUT
DISABLE
7-
~~~~~~~~!!:~T-12
8 _ _ _- - '
9
L--_ _ _ _ 11
'--------10
DATA 1/0 3
DATA 1/0
DATA 1/0
2
0.85
4.0
10
4.5
5.0
V(:e- VOLTS
5.5
6.0
o
75
50
25
TA - AM81ENT TEMPERATURE -'e
1
CHIP ENABLE 2
DIE SIZE: 0.132" X 0.131"
(Pin numbers shown are for DIP versions only)
MOS-354
2-35
Am9111/Am91L11/Am2111 Family
Am9111 FAMILY - APPLICATION INFORMATION
directly to such a processor since the common I/O pins act as
a bidirectional data bus.
These memory products provide all of the advantages of
AMD's other static N-channel memory circuits: +5 only power
supply, all. TTL interface, no clocks, no sensing, no refreshing,
military temperature range available, low power versions available, high speed, high output drive, etc. In addition, the
Am9111 series features a 256 x 4 organization with common
pins used for -both Data In and Data Out signals.
.
The Output Disable control signal is provided to prevent signal
contention for the bus lines, and to simplify tri-state bus
control in the external circuitry. If the chip is enabled and the
output is enabled and the memory is in the Read state, then the
output buffers will· be impressing data on the bus lines. At
that point, if the external system tries to drive the bus with
data, in preparation for a write operation, there will be conflict
for domination of the bus lines. The Output Disable signal
allows the user direct control over the output buffers, independent of the state of the memory. Although there are
alternative ways to resolve the conflict, norr:nally Output
Disable will be held high during a write operation.
This bussed I/O approach cUts down the package pin count
allowing the design of higher density memory systems. It also
provides a direct interface to bus-oriented systems, eliminating
bussing logic that could otherwise be required. Most microprocessor systems, for example, transfer information on a
bidirectional data bus. The Am9111 memories can connect
Typical tA Versus
Ambient Temperature
Typical VIN Limits
Versus Ambient Temperature
Typical tA Versus CL
r-----.----r----,
1.8
300
1.61----+----+----1
2501-----+----1-----1
260
vce= MIN.
240
./
220
c
I
c
I
~
200
I ~
V---"""-
. . . . .v
200
~
180
1.21----+----+----1
150 f-----+----+-------j
1.0 L-._ _....I......_ _-.L._ _---I
75
25
50
o
100 L..-_ _....I...._ _---1.._ _---'
25
50
75
o
. . . . .V
V
160
TA - AMBIENT TEMPERATURE -
°e
TA - AMBIENT TEMPERATURE -
°e
140 L-.--1._....I......_I...-......J.._..L..---I
o 100 200 300 400 500 600
eL - pF
MOS-355
2-36
Am9112/Am91L12 FAMILY
256x4 Static R/W Random Access Memories
Part
Number
Access
Time
Am2112
Am2112-2
Am9112A
Am91L12A
Am9112B
Am91L12B
Am9112C
Am91L12C
Am9112D
1000ns
650ns
500ns
400ns
300ns
250ns
Distinctive Characteristics
FUNCTIONAL DESCRIPTION
•
•
•
The Am9112/Am91 L 12 series of products are high performance,
low power, 1024-bit, static read/write random access memories.
They offer a range of speeds and power dissipations including
versions as fast as 200ns and as low as 1OOmW typical.
•
•
•
•
•
•
•
•
•
•
256 x 4 organization
16-pin standard DIP
Low operating power dissipation
125mW Typ; 290mW maximum - standard power
100mW Typ; 175mW maximum -low power
DC standby mode reduces power up to 84%
20mW Typ; 47mW maximum
Logic voltage levels identical to TTL
High output drive - two full TTL loads guaranteed
High noise immunity - full 400mV
Uniform switching characteristics - access times insensitive to
supply variations, address patterns and data patterns.
Single +5 V power supply - tolerances ± 5% commercial,
± 10% military
Each memory is implemented as 256 words by 4-bits per word. This
organization allows efficient design of small memory systems and
permits finer resolution of incremental memory word size relative
to 1024 by 1 devices. The output and input data signals are
internally bussed together and share 4 common I/O pins. This
feature keeps the package size small and provides a simplified
interface to bus-oriented systems.
The Am9112/Am91 L 12 memories may be operated in a DC standby
mode for reductions of as much as 84% of the normal operating
power dissipation. Though the memory cannot be operated, data
can be retained in the storage cells with a power supply as low as
1.5 volts. The Am91 L12 versions offer reduced power during
normal operating conditions as well as even lower dissipation in
standby mode.
Bus oriented I/O data
Zero address, set-up, and hold times guaranteed for simpler timing
Direct plug-in replacement for 2112 type devices
100% MIL-STD-883 reliability assurance testing
The eight Address inputs are decoded to select 1-of-256 locations
within the memory. The Chip Enable input acts as a high-order
address in multiple chip systems. It also controls the write amplifier
and the output buffers in conjunction with the Write Enable input.
When CE is low and WE is high, the write amplifiers are disabled,
the output buffers are enabled and the memory will execute a read
cycle. When CE is low and WE is low, the write amplifiers are
enabled, the. output buffers are disabled and the memory will
execute a write cycle. When CE is high both the write amplifiers and
the output buffers are disabled.
Am9112 BLOCK DIAGRAM
32 X 8
STORAGE
ARRAY
32 X 8
STORAGE
ARRAY
32 X 8
STORAGE
ARRAY
These memories are fully static and require no refresh operations
or sense amplifiers or clocks. All input and output voltage levels are
identical to standard TTL specifications, including the power supply.
32 X 8
STORAGE
ARRAY
CONNECTION DIAGRAM
Top View
ADDRESS 3
ADDRESS 2
\5----------------~
'6
-----------------1
ADDRESS 1
COLUMN DECODER/INPUT CONTROL/
OUTPUT 8UFFERS/SELECT LOGIC/
DISA8LE LOGIC
ADDRESSO
ADDRESS 5
ADDRESS 6
ADDRESS 7
(GND)
MOS-356
Note:
Pin 1 is marked
for orientation.
vss
MOS-357
ORDERING INFORMATION
Ambient
Temperature
Specification
Package
Type
Molded DIP
O°C to +70°C
1000ns
650ns
Standard
P2112
P2112-2
C2112
C2112·2
Hermetic DIP
-55°C to +125°C
Hermetic Flat Pack
500ns
400ns
300ns
AM9112APC
AM9112BPC
AM9112CPC
AM91L12APC
AM91L12BPC
AM91L12CPC
AM9112ADC
AM9112BDC
AM9112CDC
Low
AM91L12ADC
AM91L12BDC
AM91L12CDC
Standard
AM9112ADM
AM9112BDM
AM9112CDM
AM91L12ADM
AM91L12BDM
AM91 L12CDM
Standard
AM9112AFM
AM9112BFM
Low
AM91L12AFM
AM91L12BFM
Low
Standard
Hermetic DIP
Access Times
Power
Type
Low
2-37
250ns
AM9112DPC
AM9112DDC
fJ
Am91121Am91L12 Family
MAXIMUM RATINGS above which the useful life may ba impaired
Storage Temperature
Ambient Temperature Under Bias
VCC With Respect to VSS, Continuous
-O.5V to +7.0V
DC Voltage Applied to Outputs
DC Input Voltage
-O.5V to +7.0V
-O.5V to +7.0V
Power Dissipation
1.0W
ELECTRICAL CHARACTERISTICS
Am9112/
Am91 L 12
Family
Min.
Max.
Am9112PC. Am9112DC
Am91L12PC, Am91L12DC
vcc: +5V ±5%
Parameters
Description
VOH
Output HIGH Voltage
VCC: MIN., 10H : -200/-lA
VOL
Output LOW Voltage
Vcc: MIN., 10L: 3.2mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
III
I nput Load Current
ILO
Test Conditions
2.4
VCE: VIH
Volts
2.0
VCC
Volts
-0.5
0.8
Volts
10
/-lA
VOUT: VCC
5.0
VOUT: O.4V
-10
Am9112A/B
TA: 25°C
ICC1
Data out open
VCC = MAX.
VIN = VCC
Power Supply Current
TA
ICC2
= O°C
55
Am91L12A/B
31
Am91L12C
34
Am9112A/B
55
Am9112C/D/E
60
Am91 L12A/B
33
Am91L12C
36
ELECTRICAL CHARACTERISTICS
Am9112!
Am91 L 12
Family
Min.
Max.
Parameters
VCc: +5.0V ±10%
Description
Test Conditions
= -200/-lA
/-lA
50
Am9112C/D/E
Am9112DM. Am9112FM
Am91L12DM, Am91L12FM
Volts
0.4
VCC: MAX., OV';; VIN .;; 5.25V
I/O Leakage Current
Units
Vcc: 4.75V
2.4
VCC: 4.50V
2.2
mA
Units
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
2.0
VCC
Volts
VIL
I nput LOW Voltage
-0.5
0.8
Volts
III
Input Load Current
.;; VIN .;; 5.5V
10
/-lA
= VCC
VOUT = O.4V
10
ILO
I/O Leakage Current
10H
VCC
VCC
VCE
= MIN.,
10L
= MAX., OV
= VIH
= 3.2mA
0.4
VOUT
-10
TA
= 25°C
Data out open
Power Supply Current
VCC
VIN
= MAX.
= VCC
TA
ICC3
= -55°C
Volts
/-lA
50
Am9112A/B
ICC1
Volts
Am9112C
55
Am91L12A/B
31
Am91L12C
34
Am9112A/B
60
Am9112C
65
Am91L12A/B
37
Am91 L 12C
40
mA
CAPACITANCE
Parameters
CIN
Description
Input Capacitance, VIN
= OV
TA
COUT
Typ.
Max.
Am2112
4.0
8.0
Am9112/Am91 L 12
3.0
6.0
Am2112
10
18
Am9112/Am91 L 12
8.0
11
Test Conditions
Output Capacitance, VOUT
= 25°C, f = 1 mHz
= OV
2-38
Uni
pF
pF
Am9112/Am91L12 Family
SWITCHING CHARACTERISTICS
over operating temperature and voltage range
:)utput Load = 1 TTL Gate +100pF
rransition Times = 10ns
input Levels, Output References = O.8V and 2.OV
Am9112A
Am91L12A
)arameters
Description
Min
Am9112B
Am91L12B
Max
Min
Max
Am9112C
Am91L12C
Min
Am9112D
Max
Min
Max
Units
tRe
Read Cycle Time
tA
Access Time
teo
Output Enabled to Output ON Delay
(Note 1)
5.0
toH
Previous Read Data Valid with Respect
to Address Change
40
tOF
Output Disabled to Output OFF Delay
(Note 2)
5.0
twe
Write Cycle Time
500
400
300
250
ns
tAW
Address Set-up Time
0
0
0
0
ns
tWR
Address Hold Time
0
0
0
0
ns
twp
Write Pulse Width (Note 3)
175
150
125
100
ns
tew
Chip Enable Set-up Time
175
150
125
100
ns
tow
Input Data Set-up Time
150
125
100
85
ns
tOH
Input Data Hold Time (Note 4)
0
0
0
0
ns
500
400
300
400
500
175
5.0
150
40
SWITCHING WAVEFORMS
100
ns
300
5.0
125
5.0
40
5.0
125
250
5.0
250
ns
100
ns
30
ns
5.0
100
75
ns
(Note 5)
READ CYCLE
WRITE CYCLE
Ir--.---------tRc--------+-I -------twc--------l.!
0-.
ADDRESS
~------.~r-----c
I
I
I
-----:-I~.!~t~~.-tC-D_t-CD=~----I-:I ~f ~w, '·----1:1· .!Jr---
WRITEENABLE
U\1.5
J
tDFi - - - t - t D F
tOH~ ~
DATA 1/0
2.0~
----I------------O-.B~
f
r--
tDW
--l
---\
r
tDH
Ilr~DATAINPUT~
.
STABLE
1)------
--tA------I.1
1---'
~otes:
1. Output is enabled and tco commences only with both CE LOW and WE HIGH.
2. Output is disabled and tDF defined from either the rising edge of CE or the falling edge of WE.
3. Minimum twp is valid when CE has been HIGH at least tDF before WE goes LOW. Otherwise tWP(min.)
= tOW(min.)
+ tOF(max.)'
4. When WE goes HIGH at the end of the write cycle, it will be possible to turn on the output buffers if CE is still LOW. The data out will be
the same as the data iust written and so will not conflict with input data that may still be on the 1/0 bus.
5. See" Application I nformation" section of this specification.
M05-358
2-39
Am9112/Am91L12 Family
teo Output Enable Time. The time during which CE must be
LOW and WE must be HIGH prior to data on the output.
tOH Minimum time which will elapse between change of address
and any change on the data output.
tOF Time which will elapse between a change on the chip enable
DEFINITION OF TERMS
FUNCTIONAL TERMS
CE Active LOW Chip Enable. Data can be read from or written
into the memory only if CE is LOW.
WE Active LOW Write Enable. Data is written into the memory
if WE is LOW and read from the memory if WE is HIGH.
Static RAM A random access memory in which data is stored
in bistable latch circuits. A static memory will store data as long
as power is supplied to the chip without requiring any special
clocking or refreshing operations.
N·Channel An insulated gate field effect transistor ·technology
in which the transistor source and drain are made of N·type
material, and electrons serve as the carriers between the two
regions. N·Channel transistors exhibit lower thresholds and faster
switching speeds than P-Channel transistors.
or the right enable and on data outputs being driven to
a floating status.
twe Write Cycle Time. The minimum time required between
successive address changes while writing.
tAW Address Set-up Time. The minimum time prior to the
falling edge of the write enable during which the address inputs
must be correct and stable.
twp The minimum duration of a LOW level on the write enable
guaranteed to write data.
twR Address Hold Time. The minimum time after the rising edge
of the write enable during which the address must remain steady.
tow Data Set-up Time. The minimum time that the data input
must be steady prior to the rising edge of the write enable.
SWITCHING TERMS
tOH Data Hold Time. The minimum time that the data input
must remain steady after the rising edge of the write enable.
tew Chip Enable Time During Write. The minimum duration of a
LOW level on the Chip Select while the write enable is LOW to
guarantee writing.
tRe Read Cycle Time. The minimum time required between
successive address changes while reading.
tA Access Time. The time delay between application of an
address and stable data on the output when the chip is enabled.
2-40
Am9112/Am91 L12 Family
POWER DOWN STANDBY OPERATION
large system, memory pages not being accessed can be
placed in standby to save power. A standby recovery time
must elapse following restoration of normal power before
the memory may be accessed.
To ensure that the output of the device is in a high impedance OFF state during standby, the chip select should
be held at VIH or VCES during the entire standby cycle.
The Am91121Am91 L 12 Family is designed to maintain
storage in a standby mode. The standby mode is entered by
lowering VCC to around 1.5-2.0 volts (see table and graph
below). When the voltage to the device is reduced, the
storage cells are isolated from the data I ines, so their contents will not change. The standby mode may be used by a
battery operated backup power supply system, or; in a
STANDBY OPERATING CONDITIONS OVER TEMPERATURE RANGE
Parameters
Description
VpD
Max.
Units
1.5
Am91 L12
11
25
Am9112
13
31
VPD = 2.0V
Am91 L12
13
31
Am9112
17
41
VPD = 1.5V
Am91 L12
11
28
Am9112
13
34
Am91L12
13
34
Am9112
17
46
VPD = 1.5V
TA = O°C
All Inputs = VPD
ICC in Standby Mode
IpD
Typ.
Min.
Test Conditions
VCC in Standby Mode
TA = -55°C
All Inputs = VPD
VPD = 2.0V
mA
mA
dv/dt
Rate of Change of VCC
tR
Standby Recovery Time
tcP
Chip Deselect Time
0
ns
VCES
CE Bias in Standby
VPD
Volts
ns
Typical Power Supply Current
Versus Voltage
Typical Output Current
Versus Voltage
24
30
TA =1 250e I
25
INPUTS = 5.0V
Am9112
/~
15
RECOVERY
18
_0
14
dJ
z
t----~t___
1.4t---
c:
I
~=MAZt--
1.21--------+---1-----1
$-
200
240 1----1--+--+--\--_+--1
I ~
J----
~......--
220 I---t--+--+--_+----t::.o./~
c:
~
.........
V
200 I----t--+-V-~.::........\---+--I
1BOVIL
1501-------+---1-----1
1601---t--+--+--_+-_+_----1
1.0 L-._ _...I-_ _---..l.._ _----"
o
25
50
75
T A - AMBIEN"r TEMPERATURE -
°e
100 L -_ _--'-_ _ _l.--_ _-I
o
50
25
TA - AMBIENT TEMPERATURE -
75
°e
140 L...-----'_....l.-_-'--_l..-...--.J.._....I
o 100 200 300 400 500 600
eL - pF
MOS-360
2·42
Am9114 • Am9124
1024 x 4 Static R/W Random Access Memory
DISTINCTIVE CHARACTERISTICS
GENERAL DESCRIPTION
• LOW OPERATING POWER (MAX)
Am9124/Am9114
368mW (70mA)
Am91L24/Am91L14
262mW (50mA)
• LOW STANDBY POWER (MAX)
Am9124
158mW (30m A)
Am91L24
105mW (20mA)
• Access times down to 200ns (max)
• Military temperature range available to 300ns (max)
• Am9114 is a direct plug-in replacement for 2114
• Am9124 pin and function compatible with Am9114 and 2114,
plus CS power down feature
• Fully static - no clocking
• Identical access and cycle time
• High output drive 4.0mA sink current @ O.4V - 9124
3.2mA sink current @ O.4V - 9114
• TTL identical input/output levels
• 100% MIL-STD-883 reliability assurance testing
The Am9114 and Am9124 are high performance, static, NChannel, read/write, random. access memories organized as
1024 x 4. Operation is from a single 5V supply, and all input!
output levels are identical to standard TTL speCifications. Low
power versions of both devices are available with power
savings of over 30%. The Am9114 and Am9124 are the same
except that the Am9124 offers an automatic CS power down
feature.
The Am9124 remains in a low power standby mode as long as
CS remains high, thus reducing its power requirements. The
Am9124 power decreases from 368mW to 158mW in the
standby mode, and the Am91 L24 from 262mW to 105mW. The
CS input does not affect the power dissipation of the Am9114.
(See Figure 1, page 4).
Data readout is not destructive and the same polarity as data
input. CS provides for easy selection of an individual package
when the outputs are OR-tied. The outputs of 4.0mA for
Am9124 and 3.2mA for Am9114 provides increased short circuit current for improved capacitive drive.
BLOCK DIAGRAM
A3
A4
CONNECTION DIAGRAM
ADDRESS
BUFFERS
AS
ADDRESS 6
A6
ADDRESS S
VCC
ADDRESS 7
ADDRESS 4
ADDRESS 8
A7
A8
ADDRESS 3
ADDRESS 9
ADDRESS 0
INPUT/OUTPUT 1
Al
ADDRESS 1
INPUT/OUTPUT 2
A2
ADDRESS 2
INPUT/OUTPUT 3
CHIP SELECT
INPUT/OUTPUT 4
AO
A9
GND (VSS)
WRITE ENABLE
cs
We
1/01
1/02
1/03
Top View
Pin 1 is marked for orientation.
1/04
MOS·067
MOS-066
ORDERING INFORMATION
Access Times
Ambient
Temperature
Package
Type
Plastic
O°C ~ TA ~ 70°C
Hermetic
-55°C ~ TA ~ +125°C
Hermetic
ICC
Current
Level
Am9124
(Power Down Option)
Am9114
450ns
300ns
70mA
Am9114BPC
Am9114CPC
50mA
Am91L14BPC
Am91L14CPC
70mA
Am9114BDC
Am9114CDC
50 rnA
Am91L14BDC
Am91L14CDC
200ns
450ns
300ns
Am9114EPC
Am9124BPC
Am9124CPC
Am91L24BPC
Am91L24CPC
Am9114EDC
Am9124BDC
Am9124CDC
Am91L24BDC
Am91L24CDC
BOmA
Am9114BDM
Am9114CDM
Am9124BDM
Am9124CDM
60mA
Am91L14BDM
Am91L14CDM
Am91L24BDM
Am91L24CDM
2-43
200ns
Am9124EPC
Am9124EDC
Am9114 • Am9124
MAXIMUM RATINGS beyond which useful life may be impaired
Storage Temperature
Ambient Temperature Under Bias
Vee with Respect to Vss
-O.5V to +7.0V
All Signal Voltages with Respect to Vss
-O.5V to + 7.0V
Power Dissipation (Package Limitation)
1.0W
DC Output Current
10mA
The products described by this specification include internal circuitry designed to protect input devices from damaging accumulations of
static charge. It is suggested nevertheless, that conventional precautions be observed during storage, handling and use in order to
avoid exposure to excessive voltages.
OPERATING RANGE
Part Number
Am9114DC/PC
Am91 L 14DC/PC
Am9124DC/PC
Am91 L24DC/PC
Ambient Temperature
Vss
O°C ~ TA ~ +70°C
OV
VCC
Part Number
Ambient Temperature
Vss
VCC
Am9114DM
Am91L14DM
Am9124DM
Am91L24DM
-55°C ~ TA ~ +125°C
OV
+5.0V ± 10%
+5.0V ± 5%
ELECTRICAL CHARACTERISTICS over operating range
Parameter
Min.
Test Conditions
Description
VOH
= 2.4V
= 2.2V
Val
= O.4V
V OH
Am9114XX
Am91L14XX
Am9124XX
Am91L24XX
= 4.75V
= 4.5V
Vee
Typ.
Max.
Min.
-1.4
-1.0
-1.0
-1.0
Typ.
Max. Units
mA
tOH
Output High Current
tal
Output Low Current
V IH
Input High Voltage
2.0
Vee
2.0
Vee
Volts
V il
Input Low Voltage
-0.5
0.8
-0.5
0.8
Volts
IIX
Input Load Current
10
p.A
Vee
TA
TA
= +70°C
= +125°C
4.0
3.2
3.2
2.4
I
Vss ~ VI ~ Vee
mA
10
TA
O.4V ~ Va ~ Vee
Output Disabled
= +125°C
= +70°C
loz
Output Leakage Current
los
Output Short Circuit Current
(Note 2)
CI
Input Capacitance (Note 1)
ClIO
I/O Capacitance (Note 1)
Test Frequency = 1.0MHz
T A = 25°C, All pins at OV
TA
-50
50
-50
50
-10
10
-10
10
O°Cto +70°C
95
75
-55°C to +125°C
115
75
3.0
5.0
3.0
5.0
5.0
6.0
5.0
6.0
p.A
mA
pF
ELECTRICAL CHARACTERISTICS over operating range
Am91L24
Parameter
lee
Description
Vee Operating
Supply Current
Test Conditions
Max. Vee, CS ~Vll
for Am9124/91 L24
TA
Automatic CS Power
Down Current
Max. Vee
(CS ~ VIH)
= 25°C
40
TA = O°C
TA = -55°C
Am91 L 14
Am9114
= 25°C
60
40
60
50
70
50
70
60
80
60
80
-
-
TA = O°C
20
30
-
-
TA = -55°C
22
33
-
-
TA
Ipo
Am9124
Typ. Max. Typ. Max. Typ. Max. Typ. Max. Units
Notes:
1. Typical values are for TA = 25°C, nominal supply voltage
and nominal processing parameters.
2. For test purposes, not more than one output at a time
should be shorted. Short circuit test duration should not exceed 30 seconds.
3. Test conditions assume signal transition times of 10ns or
less, timing reference levels of 1.5V and output loading of
one standard TTL gate plus 100pF.
24
15
mA
mA
4. The internal write time of the memory is defined by the
overlap of CS low and WE low. Both signals must be low to
initiate a write and either signal can terminate a write by
going high. The data input setup and hold timing should be
referenced to the rising edge of the signal that terminates
the write.
5. Chip Select access time (teo) is longer for the Am9124 than
for the Am9114. The specified address access time will be
valid only when Chip Select is low soon enough for teo to
elapse.
2-44
Am9114 • Am9124
SWITCHING CHARACTERISTICS over operating range (Note 3)
Description
Parameter
Am9114B
Am9124B
Min.
Max.
Am9114C
Am9124C
Min.
Max.
Am9114E
Am9124E
Min.
Max.
Unit
Read Cycle
tRC
Address Valid to Address Do Not Care Time (Read Cycle Time)
tA
Address Valid to Data Out Valid Delay (Address Access Time)
tCO
Chip Select Low to Data Out Valid (Note 5)
tCX
Chip Select Low to Data Out On
450
I Am9114
I Am9124
300
300
120
100
70
420
280
185
20
20
tOTD
Chip Select High to Data Out Off
tOHA
Address Unknown to Data Out Unknown Time
200
450
100
200
ns
20
80
60
50
50
50
450
300
200
200
150
120
250
200
150
Write Cycle
tWC
tW
Address Valid to Address Do Not Care Time (Write Cycle Time)
Write Enable Low to Write Enable High Time (Note 4)
tWR
Write Enable High to Address Do Not Care Time
tOTW
Write Enable Low to Data Out Off Delay
lOW
Data In Valid to Write Enable High Time
tDH
I Am9114
I Am9124
0
0
100
0
80
60
200
150
120
Write Enable Low to Data In Do Not Care Time
0
0
0
tAW
Address Valid to Write Enable Low Time
0
tPD
Chip Select High to Power Low Delay (Am9124 only)
tPU
Chip Select Low to Power High Delay (Am9124 only)
tCW
Chip Select Low to Write Enable High Time (Note 4)
ns
0
200
0
I Am9114
I Am9124
0
150
100
0
0
200
150
120
250
200
150
SWITCHING WAVEFORMS
I
READ CYCLE
IRC----II
I
READ CYCLE
IRC
1
1-1
WRITE CYCLE
---Iwc----II
POWER DOWN WAVEFORM (Am9124 ONLy)
MOS-069
2-45
Am9114 • Am9124
TYPICAL CHARACTERISTICS
Typical ICC
Versus VCC Characteristics
Typical tacc
Versus VCC Characteristics
Typical C Load Versus
Normalized tacc Characteristics
1.15 .........- __':'T""-..,....--r----r---,
TA = 25'C
1.50 r---r'-r---;--.----;--.----..
TA = 25'C
1.25 1---+-+---+--+---+--+----1
~c
1.00
........... I---~
/
I!J
Am9114 AND Am9124
(ACTIVE)-f--
:J 0.75
~ 0.50 I /........
z
If/)/
0.25
-~
I I
i\
~
1.0
~.-!-f'....-+--+--+----+-+-.....-+V------,l
c:(
Am9114 AND Am9124
1.00
""/::"'_-+--+---+---+--+----I
~
~
0.9
1--+-+--+---+-+--+-+---1
o
z
0.95
1--+--+-+--f---+--4
tl
I
I
I
I
~1.05
I!J
vce
CAPACITANCE LOAD - pF
Normalized ICC
Versus Ambient Temperature
1.4 r - - - - ; - - - , . - - r - - - . - - - , - - - - ; - - - - ,
1.3...---,---,--.----,---r-----,----,
VCC
5.0V
:!
VCC! 5.0V
1.31----+--+----+--+__--+---+--1
u
u
1.1
./
w
:J
Am9114 AND Am9124
V-
c:(
::;;
a:
0
1.0
0.9
-25
0
25
50
1.2~
!:1
1.1
:J
~
~
./
V
O.B
-55
,,/
CJ
~
/
VI
z
~
~'P' Am9124
0.901 ....
00--'--20'-0-...J.....-30'-0-...J.....---'400
Normalized tacc
Versus Ambient Temperature
1.2
~
a:
1
O.B '---'-.......-'---'--'--'---'--'
4.0
4.5
5.0
5.5
6.0
VCC
01234567
c'"
Am9114
Am9124 (STAND BY)
o
N
~
1.1
::;;
I"+-
1.10
~
70
TA - AMBIENT TEMPERATURE _
100
r-....
............. ~9114 AND A~9124
1.0 I----+----+-~'k--+--t----+----+
......................... 1
0.9
--
f----+----+--f---+-~-..::---+--I
...............
O.B f----+----+--f---+---It----+---"
..........~
0.7 '--_......._ - - '_ _.l.--_..J._ _' - - _......._ - - - '
-55
-25
25
50
70
100
125
125
'c
TA - AMBIENT TEMPERATURE _ 'C
MOS-361
BIT MAP
--- ---
Worst Case Current
(mA at 0° C)
Configuration
2Kx8
4K x 12
8K x 16
Part
Number
100%
Duty Cycle
50%
Duty Cycle
9114
91L14
280
200
280
200
9124
91L24
200
140
160
110
9114
91L14
840
600
840
600
9124
91L24
480
330
420
285
9114
91L14
2240
1600
2240
1600
9124
91L24
1120
760
1040
700
1/03
1101
Address Designators
External
Internal
AD
At
A2
A3
A9
AS
A7
AD
Al
A2
A3
A4
AS
A6
A7
AS
A9
CELL :
NUMBER
~
I
A4
AS
A6
10231'" !63
102363
+___ INTERNAL
1023 t-..
r-
~~';3~~~~~~~1
.
====
Figure 1. Supply Current Advantages of Am9124.
Figure 2. Bit Mapping Information.
2-46
=
ROW 63
Am9130 · Am91l30
1024 x 4 Static R/W Random Access Memories
DISTINCTIVE CHARACTERISTICS
GENERAL DESCRIPTION
•
•
•
•
•
The Am9130 and Am91 L30 products are high performance,
adaptive, low-power, 4k-bit, static, read/write random access
memories. They are implemented as 1024 words by 4 bits per
word. Only a single +5V power supply is required for normal
operation. A DC power-down mode reduces power while retaining data with a supply voltage as low as 1.5V.
1k x 4 organization
Fully static data storage - no refreshing
Single +5V power supply
High-speed - access times down to 200ns max.
Low operating power
- 578mW max., 9130
- 368mW max., 91 L30
• Interface logic levels identical to TTL
• High noise immunity - 400mV worst-case
• High output drive - two standard TTL loads
o DC power-down mode - reduces power by >80%
• Single phase, low voltage, low capacitance clock
• Static clock may be stopped in either state
• Data register on-chip
• Address register on-chip
• Steady power drain - no large surges
• Unique Memory Status signal
- improves performance
. - self clocking operation
• Full MIL temperature range available
• 100% MIL-STD-883 reliability assurance testing
All interface signal levels are identical to TTL specifications,
providing good noise immunity and simplified system design.
All inputs are purely capacitive MOS loads. The outputs will
drive two full TIL loads or more than eight low-power Schottky
loads.
Operational cycles are initiated when the Chip Enable clock
goes HIGH. When the read or write is complete, Chip Enable
goes LOW to preset the memory for the next cycle. Address
and Chip Select signals are latched on-chip to simplify system
timing. Output data is also latched and is available until the
next operating cycle. The WE signal is HIGH for all read operations and is LOW during the Chip Enable time to perform a
write. Data In and Data Out signals share common I/O pins .
Memory Status is an output signal that indicates when data is
actually valid and when the preset interval is complete. It can
be used to generate the CE input and to improve the memory
performance.
CONNECTION DIAGRAM
BLOCK DIAGRAM
AO
A1
ROW
ADDRESS
DECODERS
A2
A3
64
ADDRESS 6
STORAGE CELL MATRIX
A4
64x16
64xl6
64x16
64x16
VCC (+5.0V)
ADDRESS 7
ADDRESS 0
ADDRESS B
ADDRESS 1
A5
ADDRESS 9
ADDRESS 2
DATA 1/0 1
ADDRESS 3
CE
REF. ROW
r--------,
~~----~--~~--~~
A6
DATA 1/02
ADDRESS 4
DATA 1/0 3
ADDRESS 5
A7
WRITE ENABLE
DATA 1/04
AB
A9
CHIP SELECT
OUTPUT DISABLE
OUTPUT ENABLE
MEMORY STATUS
CHIP ENABLE
(GND) VSS
VCCo--
Top View
GNDo-OE
OD
MPR·376
WE
1/01
1/02
1/03
1/04
Pin 1 is marked for orientation.
MS
MPR·377
ORDERING INFORMATION
Package
Type
Molded
Hermetic
Ambient Temperature
O°C,,;;; T A ,,;;; +70°C
O°C,,;;; T A ,,;;; +70°C
DIP
-55°C,,;;; TA ,,;;; +125°C
Power
Type
500ns
400ns
Access Time
300n5
250n5
STD
AM9130APC
AM9130BPC
AM9130CPC
AM9130DPC
AM91 L30DPC!
LOW
AM91L30APC
AM91L30BPC
AM91L30CPC
STD
AM9130ADC
AM9130BDC
AM9130CDC
AM9130DDC
LOW
AM91L30ADC
AM91L30BDC
AM91L30CDC
AM91L30DDC
STD
AM9130ADM
AM9130BDM
AM9130CDM
LOW
AM91L30ADM
AM91L30BDM
AM91L30CDM
2-47
200ns
AM9130EPC
AM9130EDC
Am9130 • Am91L30
MAXIMUM RATINGS
above which the usefullife'may be impaired
Storage Temperature
Ambient Temperature Under Bias
VCC with Respect to Vss
-O.5V to +7.0V
All Signal Voltages with R~spect to Vss
-O.5V to +7.0V
Power Dissipation
1.25W
The products described by this specification include internal circuitry designed to protect input devices from damaging accumulations-of
static charge. It is suggested, nevertheless, that conventional precautions be observed during storage, handling and use in order to avoid
exposure to excessive voltages.
OPERATING RANGE
POWER-DOWN RANGE
Vcc
VSS
VCC
VSS
Ambient Temperature
Part Number
4.75V .;; VCC .;;; 5.25V
4.50V .;; vcc .;;; 5.50V
OV
OV
1.5V .;;; VCC .;;; 5.25V
1.5V .;;; vCC .;;; 5.50V
OV
OV
o°c.;;; TA';;; +70°C
-55°C';;; TA';;; +125°C
AM91X30XDC
AM91X30XDM
ELECTRICAL CHARACTERISTICS over operating
Parameters
Description
range (Note 1)
Am9130
Test Conditions
Min.
Typ.
Am91L30
Max.
Min.
VCC = 4.75V
2.4
2.4
VCC = 4.5V
2.2
2.2
VOH
Output HIGH Voltage
10H = -200J,lA
VOL
Output LOW Voltage
10L = 3.2mA
VIH
Input HIGH Voltage
2.0
VIL
Input LOW Voltage
-0.5
Typ.
Units
Volts
0.4
VCC
0.8
Max.
2.0
-0.5
0.4
Volts
VCC
0.8
Volts
Volts
III
Input Load Current
VSS .;;; VIN .;;; VCC
10
10
J,lA
ILO
Output Leakage Current
VSS';;; VOUT';;; VCC, Output disabled
10
10
J,lA
TA = 25°C
ICC
Max. VCC
Output disabled
VCC Supply Current
CIA
Input Capacitance (Address)
COUT
Output Capacitance
CIC
Input Capacitance (Controll
Ci/o
I/O Capacitance
70
125
80
Min_
Test Conditions
Am9130
Typ.
3.0
6.0
3.0
6.0
pF
7.0
4.0
7.0
pF
6.0
9.0
6.0
9.0
pF
6.0
9.0
6.0
9.0
pF
Max.
Min.
tPS
Power Down Set-Up Time
tEL
tEL
tPH
Power Up Hold Time
tEL
tEL
ICC in Standby
(Note 2)
3.0
VCC = 1.5V
72
36
MINIMUM
CE
ANO
OE
Vce
V/J,lS
ns
ns
28
55
mA
78
60
mA
TA
89
68
mA
45
mA
=
_55°
52
20
16
TA = O°C
56
48
mA
TA=-55°C
64
55
mA
POWER DOWN WAVEFORM
OPERATING
Unit
TA = O°C
TA = 25°C
Vce
Am91L30
Typ.
Max.
3.0
TA = 25°C
mA
4.0
VCC Rate of Change
VCC = 2.0V
65
110
dV/dt
IpD
40
TA = -55°C
Test frequency = 1 MHz
TA = 25°C
All pins at OV
Description
100
TA = O°C
POWER DOWN CHARACTERISTICS
Parameter
50
~~~"'"'~;f
I
I
/
--......::
f-""1
I"~
~
'!I:ttA
2-48
Am9130 • Am91 L30
SWITCHING CHARACTERISTICS over operating range
READ CYCLE (Notes 7, 8, 9)
Description
Parameter
tRC
Read Cycle Time (Note 5)
Am9130A
Am9iL30A
Am9130B
Am91 L30B
Am9130C
Am91 L30C
Am9130D
Am91 L30D
Min.
Min.
Min.
Min.
Max.
770
Max.
620
tA
Access Time (Note 3)
(CE to Output Valid Delay)
tEH
Chip Enable HIGH Time (Note 14)
500
tEL
Chip Enable LOW Time (Note 14)
250
tCH
Chip Enable to Chip Select Hold Time
200
tAH
Chip Enable to Address Hold Time
tCS
Chip Select to CE Set-Up Time (Note 4)
tAS
Address to Chip Enable Set-Up Time
0
0
tRS
Read to Chip Enable Set-Up Time
0
0
tRH
Chip Enable to Read Hold Time
0
0
tOH
Chip Enable to Output OFF Delay (Note 3)
0
tCF
OE or 00 to Output OFF Delay (Note 11)
Max.
470
500
Max.
300
Max.
320
395
400
Am9130E
Min.
250
Unit
ns
200
ns
ns
400
300
250
200
200
150
125
100
ns
170
150
130
120
ns
200
170
150
130
120
ns
-5
-5
-5
-5
-5
ns
0
0
0
ns
0
0
0
ns
0
0
0
ns
0
ns
0
0
0
165
200
115
135
125
100
ns
110
ns
tCO
OE or 00 to Output ON Delay (Note 11)
tES
Output Enable to CE LOW Set-Up Time (Note 12)
90
75
60
55
50
ns
tOM
Data Out to Memory Status Delay
0
0
0
0
0
ns
tP
I nternal Preset I nterval (Note 14)
220
185
150
tEL
tEL
tEL
tEL
tEL
ns
SWITCHING WAVEFORMS
READ CYCLE
I
'II--"'~
tRC
--MI
1
CHIP
ENABLE
:
""
ADDRESS
_----'-'-£.L-iffL11f.fJ~
til
I
tAS-+----l"I r - t A H - - j
~II
~rrr"1ItCS-H ~tCH---j ~~"""IInnnnnnnnnnnn.rrr-----
~I
I
OUTPUT
ENABLE
I
II
tRS
I
I
---------I-~
_...:f
I·
I
I
tCO
OUTPUT VALID
1 ~'==-\~__
--1,
- - - __
1
(NOTE 6)
~
~tCF-----j
-!
I
-)!-\1\0-_ _ _...;...-._ _ _ _ _ _ _
I
f--+-tOH
MEMORY
STATUS
tRH
~I
OUTPUT
DISABLE
DATA 1/0
I
~
m
•1
"
MPR-379
2-49
Am9130 • Am91L30
SWITCHING CHARACTERISTICS over operating range
WRITE CYCLE (Notes 7, 8, 9)
Description
Parameter
Am9130A
Am91 L30A
Am9130B
Am91 L30B
Am9130C
Am91 L30C
Am9130D
Am91 L30D
Am9130E
Min.
Min.
Min.
Min.
Min.
Max.
770
tWC
Write Cycle Time (Note 5)
tA
Access Time (CE to Output ON Delay)
Max.
620
Max.
470
395
400
500
Max.
300
Max.
Unit
200
ns
ns
320
250
tEH
Chip Enable HIGH Time (Notes 14,15)
500
400
300
250
200
ns
tEL
Chip Enable LOW Time (Notes 14,15)
250
200
150
125
100
ns
tAS
Address to Chip Enable Set-Up Time
0
0
0
0
0
ns
tAH
Chip Enable to Address Hold Time
200
170
150
130
120
ns
tCS
Chip Select to CE Set-Up Time (Note 4)
-5
-5
-5
-5
-5
ns
tCH
Chip Enable to Chip Select Hold Time
200
170
150
130
120
ns
tWW
Write Pulse Width (Note 10)
200
165
135
115
100
ns
tDS
Data Input Set-Up Time (Note 10)
200
165
135
115
100
ns
tDH
Data Input Hold Time (Note 10)
0
0
0
0
0
ns
tDM
Data Out to Memory Status Delay
0
0
0
0
0
tP
Internal Preset Interval
-
tEL
tEL
tEL
tEL
ns
tEL
ns
SWITCHING WAVEFORMS
WRITE CYCLE
OUTPUT~
_ _ _
DISABLE
_
DATA 1/0
Mi~A~~~
l=E
~H I ~1
(NOTES6,151
r-
;f
I
I.
tCF
D~~A
_I
1
__ __ _ 1_ ---::l-
tA
I
tOM
_
_
II
STABLE
IDS
--1
"\~_ _ _ _ _ _ __
:'f-
LJ1\'-----f--+IDH
tP
MPR-380
2-50
Am9130· Am91L30
SWITCHING CHARACTERISTICS over operating range
READ/MODIFY/WRITE CYCLE (Notes 7, 8, 9)
Description
Parameter
tRMWC
R/M/W Cycle Time (Notes 5,16)
tA
Access Time (CE to Output Valid Delay)
tEH
Chip Enable HIGH Time (Notes 14, 15)
tEL
tCH
Am9130A
Am91 L30A
Am9130B
Am91 L30B
Am9130C
Am91 L30C
Am9130D
Am91 L30D
Am9130E
Min.
Min.
Min.
Min.
Min.
Max.
1170
Max.
740
950
500
400
900
730
Chip Enable LOW Time (Notes 14,15)
250
Chip Enable to Chip Select Hold Time
200
Max.
Max.
625
Max.
520
300
250
Unit
ns
200
ns
570
480
400
200
150
125
100
ns
170
150
130
120
ns
120
ns
ns
tAH
Chip Enable to Address Hold Time
200
170
150
130
tCS
Chip Select to CE Set-Up Time (Note 4)
-5
-5
-5
-5
-5
ns
tAS
Address to Chip Enable Set-Up Time
0
0
0
0
0
ns
tRS
Read to Chip Enable Set-Up Time
0
0
0
0
0
ns
tOH
Chip Enable to Output OFF Delay
0
d
0
0
0
ns.
tDH
Data Input Hold Time (Note 10)
0
0
0
0
0
ns
ns
tDS
Data Input Set-Up Time (Note 10)
200
165
135
115
100
tWW
Write Pulse Width (Note 10)
200
165
135
115
100
tCF
OE or 00 to Output OFF Delay (Note 11)
tCO
OE or 00 to Output ON Delay (Note 11)
tDV
Data Valid after Write Delay
10
10
10
10
10
ns
tR
Read Mode Hold Time
tA
tA
tA
tA
tA
ns
tOM
Data Out to Memory Status Delay
0
tP
Internal Preset Interval
200
165
220
135
185
115
0
0
0
ns
110
ns
0
tEL
tEL
tEL
125
150
ns
100
tEL
ns
tEL
ns
SWITCHING CHARACTERISTICS
READ/MODIFY/WRITE CYCLE
=--:l
tRMWC
I !"
""
M
~tAH---l
CHIP
ENABLE
o! ( ' "
N,
I
tAS---r---l
ADDRESS
I
~
~I/
tRS
I'
I·
\'wwll
,"-
WRITE
ENABLE
I
_
_
_
_
OUTPUT
ENABLE
(NOTE 13)
,II~~~
II
I
OUTPUT
DISABLE
tOH
+---J
- - - I~
DATA 1/0
___
I
---t
I.
tCo-l------1,~_............,.....,..,.
I
J,-
tA----I
tDM-1----<~1
MEMORY
STATUS
(NOTES 6, 15)
/
--MPR-381
2-51 '
Am9130 • Am91L30
NOTES:
1.
Typical operating supply current values are specified for
nominal processing parameters, nominal supply voltage
and the specific ambient temperature shown.
2.
Typical power·down supply current values are specified
for nominal processing parameters, the specific supply
voltage shown and the specific ambient temperature
shown.
3.
At any operating temperature the minimum access time,
tA(min.), will be greater than the maximum CE to
output OFF delay, tOH(max.).
4.
The negative value shown indicates that the Chip Select
input may become valid as late as 5ns following the
start of the Chip Enable rising edge.
5.
The worst-case cycle times are the sum of CE rise time,
tEH, CE fall time and tEL. The cycle time values shown
include the worst-case tEH and tEL requirements and
assume CE transition times of 10ns.
6.
The Memory Status signal is a two-state output and is
not affected by the Output Disable or Output Enable
signals. If the output data buffers are turned off, Memory
Status will continue to reflect the internal status of the
memory.
7.
Output loading is assumed to be one standard TTL gate
plus 50pF of capacitance.
8.
Timing reference levels for both input and output signals
are 0.8V and 2.0V.
9.
CE and WE transition times are assumed to be ~1 Ons.
10.
The internal write time of the memory is defined by
the overlap of CE high and WE low. Both signals must
be present on a selected chip to initiate a write. Either
signal can terminate a write. The tWW, tDS and tDH
specifications should all be referenced to the end of the
write time. The Write Cycle timing diagram shows
termination by the falling edge of CEo If termination is
defined by bringing WE high while CE is high, the
following timing applies:
CE
1->-
~-'ww
Jtr
11.
The output data buffer can be ON and output data
valid only when Output Enable is high and Output
Disable is low. OE and OD perform the same function
with opposite control polarity.
12.
The output data buffer should be enabled before the
falling edge of CE in order to read output information.
When the output is disabled and CE is low, the output
data register is cleared.
13.
Input and output data are the same polarity.
14.
The Chip Enable waveform requirements may be defined
by the Memory Status output waveform. For a read
cycle, the basic CE requirement is that tEH;): tA and
tEL;): tP:
M
_s
CE
_'",.,,£\~_Ly,",."
MPR-383
15.
The Memory Status output functions as if all operations
are read cycles. If a write cycle begins with WE low and
Data In stable at the time CE goes high, the rising edge
of MS may be used as an indication that the write is
complete and CE may be brought low. In a cycle where
WE goes low at some point within the CE high time, the
rising edge of MS should be ignored as an indication of
write status. The falling edge of MS is always valid
independent of the type of operation being performed.
16.
For the R/MNI/ cycle, tEH (min.) is defined as tR (min.)
+tCF (max.) + tDS (min.). This provides a conservative
design with no I/O overlap and assumes that tCF begins
at the end of the tR time. Other designs with somewhat
shorter R/MNI/ cycles are possible.
~\.----
!--tos------j \--rtOH
Ol/0>mm
INPUT STABLE
~
MPR-382
FUNCTION DESCRIPTION
Block Diagram
The block diagram for the Am9130 shows the interface connections along with the general signal flow. There are ten
address lines (AO through A9) that are used to specify one
of 1024 locations, with each location containing 4 bits. The
Chip Select signal acts as a high order address. The Chip
Enable clock latches the addresses into th!! address registers
and controls the sequence of internal activities.
the rows is selected. The 64 cells on the selected row are then
connected to their respective bit line columns. Meanwhile, the
column address signals (A6 through A9) are decoded and
used to select 4 of 64 columns for the sense amplifiers. Thus a
single cell is connected to each output path.
During read operations, the sensed data is latched into the
output register and is available for the balance of the operating
cycle. During write operations, the write amplifier is turned on
and drives the input data onto the sense lines, up the column
The row address signals (AO through A5) and their inversions
are distribut!'!d to the 64 row address decoders where one of
2-52
Am9130 • Am91L30
bit lines and into the selected cell. Read and write data are
the same polarity.
To execute a read cycle, WE is held high while CE is high. To
perform a write operation, the WE line is switched low while
CE is high. Only a narrow write pulse width is required to
successfully write into a cell. In many cases, however, it will
be convenient to leave the WE line low during the whole
cycle.
The data buffer is three·state and unselected chips have
their outputs turned off so that several may be wire-ored
together. The Output Enable and Output Disable si'gnals provide asynchronous controls for turning off the output buffers.
Within the storage matrix there is an extra row of simulated
cells. This reference row is selected on every operating cycle
in addition to the addressed row and provides internal timing
signals that control the data flow through the memory. The
Memory Status output signal is derived from the reference
row and uses the same designs for its sense and buffer circuits
as used by the data bits.
A write cycle can take place only when three conditions are
met: The chip is selected, CE is high, and WE is low. This
means that if either CE goes low or WE goes high, the writing
is terminated.
Data In and Data Out
Chip Enable
The requirements for incoming data during a write operation
show a minimum set-up time with respect to the termination
of the write. Termination occurs when either WE goes high or
CE goes low. If incoming data changes during a write operation,
the information finally written in the cell will be that stable
data preceeding the termination by the set-up time. Since the
data being written during a write cycle is impressed on the
sense amplifier inputs, the output data will be the same as the
input once the write is established.
The Chip Enable input is a control clock that coordinates all
internal activities, The rising edge of CE begins each cycle and
strobes the Address and Chip Select signals into the on-chip
register. Internal timing signals are derived from CE and from
transitions of the address latches and the reference cells.
When the actual access time of the part has been reached (or
a write operation is complete), CE may be switched low if
desired. The worst-case time as specified in the data sheet may
be used to determine the access. Alternatively, the access or
write-complete time indicated by the rising edge of the
Memory Status output signal may be used.
During a read cycle, once all of the addressing is complete and
the cell information has propagated through the sense amplifier, it enters the output data register. The read information
can also flow through to the output if the buffer is enabled. As
long as CE is high, the addressing remains valid and the output
data will be stable. When CE goes low to begin the internal
preset operation, the output information is latched into the
data register. It will remain latched and stable as long as CE
is low. If the output is disabled when CE is low, the output
data register is cleared. At the start of every cycle when CE
goes high, the output data latch is cleared in preparation for
new information to come from the sense amplifier, and the
output buffer is turned off.
When CE goes low, the internal preset operation begins. The
memory is ready for a new cycle only after the preset is
complete. The worst-case CE low time specified in the data
sheet may be used to determine the preset interval. Alternatively, the actual preset time is indicated as complete when
Memory Status goes low.
There are no restrictions on the maximum times that CE may
remain in either state so the clock may be extended or stopped
whenever convenient. After power-on and before beginning a
valid operation, the clock should be brought low to initially
preset the memory.
OE and 00 are designed to provide asynchronous control of
the output buffer independent of the synchronous Chip Select
control. The OE and 00 control lines perform the same
internal function except that one is inverted from the other.
If either OE is low or OD is high, the output buffer wi II turn
off. If the CS input is latched low and OE is high and 00 is
low, then the output buffer can turn on when data is
available.
Address and Chip Select
The Address inputs are latched into the on-chip address
register by the rising edge of CEo Addresses must be held
stable for the specified minimum time following the rising
edge of CE in order to be properly loaded into the register.
Following the address hold time, the address inputs are ignored
by the memory until the next cycle is initiated.
Memory Status
The Chip Select input acts as a high order address for use when
the system word capacity is larger than that of an individual
chip. It allows the Address lines to be wired in parallel to all
chips with the CS lines then used to select one active row of
chips at a time. Unselected chips have their output buffers off
so that selected chips wired to the same data lines can dominate the output bus. Only selected chips can perform write
operations.
CS is latched in the same way that Addresses are. Once a
memory is selected or deselected, it will remain that way
until a new cycle with new select information begins.
The Memory Status output is derived from the actual performance of the reference row of cells. Since the reference row is
always doing a read operation, the MS output will appear in
every operating cycle, whether a read or write is being performed. MS uses the same output circuitry as used in the data
path. The result is that Memory Status tracks very closely
the true operating performance of the memory.
Write Enable
The Write Enable line controls the read or write condition of
the devices. When the CE clQck is low, the WE signal may be
in any state without affecting the memory. WE does not
affect the status of the output buffer.
The rising edge of MS indicates when output data is valid and
tracks changes in access time with changing operating conditions. The rising edge also specifies the end of the time that
CE must be held high for a read. CE may be high as long as
desired, but may safely go low any time after MS goes high.
The falling edge of MS occurs after CE goes low and the
internal preset period is complete. It indicates that CE may
go high to begin a new cycle. See the Am9130/40 Application
Note for details.
2-53
fJ
Am9130 • Am91L30
CHARACTERISTICS
Access Time
Versus Ambient Temperature
Access Change
Versus Capacitive Load
,
60
40
~
l/
u
u
«
~
w
20
7 t-
<.:l
Z
«
I
U
-20
/
-
/
/
Supply Current
Versus Ambient Temperature
1.3
w
:;;
""
1.2
1.2
i=
I
,
1/
Ul
Ul
W
u
u
1.1
~
1.0
«
~
0.9
«
::i
VCC = 5.0V
0
z
TA = 25°C
DC LOAD = 1 TTL GATE
~~
~
/
u
_u
~::i
«
~
V'
100
200
300
CAPACITIVE LOAD - pF
z
25
50 75 100 125
AMBIENT TEMPERATURE - °c
MPR-384
0.9 f-- -
1--- f---
1\,
I-f'i'\
0.8
i
0.7
-50 -25 0
400
~r\
1.0
0
0.8
o
\~
1.1
-50 -25
MPR-385
0
25
50
L
~
75 100 125
AMBIENT TEMPERATURE - °c
Typical Output Currents
Versus Output Voltage
Typical lee Versus Vee
25~--~----~---------.
50
TA =1 25oC
40
«
E
,r
~
30
I
u
_u
20
~
'i
~
~
15
:)
u
f--
,/
10
20
I
f--
i2f--
:)
0
~
1.0
2.0
3.0
4.0
5.0
1.0
MPR-387
V CC - V
2.0
3.0
OUTPUT VOLTAGE - V
MPR-388
Bit Map
Metallization and Pad Layout
BIT 1
22
21
CELL 0
20
COL 15
COL 0
COL 0
} BIT 1
}BIT 2
19
COL 15
COLO
} BIT 3
18
COLO
17
COL 15
16
15
14
13
10
11
BIT 4
CELL 1024
For bit mapping purposes:
Row address LSB = A5, MSB = AO
Column address LSB = AG, MSB = A9
DIE SIZE 0.192" X 0.197"
2·54
MPR-386
Am9131 • Am91 L31
1024 x 4 Static R/W Random Access Memories
DISTINCTIVE CHARACTERISTICS
GENERAL DESCRIPTION
•
•
•
•
•
The Am9131 and Am91 L31 products are high performance, low-power, 4k-bit, static, read/write random access
memories. They are implemented as 1024 words by 4 bits
per word. Only a single +5V power supply is required for
normal operation. A DC power-down mode reduces power
while retaining data with a supply voltage as· low as 1.5V.
•
•
•
•
•
•
•
•
•
•
•
1 k X 4 organization
Fully static data storage - no refreshing
Single +5V power supply
High-speed - access times down to 200ns max.
Low operating power
- 578mW max., 9131
- 368mW max., 91 L31
Interface logic levels identical to TTL
High noise immunity - 400mV worst-case
High output drive - two standard TTL loads
DC power-down mode - reduces power by >80%
Single phase, low voltage, low capacitance clock
Static clock may be stopped in either state
Data register on-chip
Address register on-chip
Steady power drain - no large surges
Full MIL temperature range available
100% M I L-STD-883 reliability assurance testing
All interface signal levels are identical to TTL specifications,
providing good noise immunity and simplified system design. All inputs are purely capacitive MOS loads. The outputs will drive two full TTL loads or more than eight
low-power Schottky loads.
Operational cycles are initiated when the Chip Enable
clock goes HIGH. When the read or write is complete,
Chip Enable goes LOW to preset the memory for the next
cycle. Address and Chip Select signals are latc11ed on-chip
to simplify system timing. Output data is also latched and is
available until the next operating cycle. The WE signal is
HIGH for all read operations and is LOW during the Chip
Enable time to perform a write. Data In and Data Out
signals share common I/O pins.
BLOCK DIAGRAM
CONNECTION DIAGRAM
AO
A1
ROW
ADDRESS
DECODERS
A2
A3
64
ADDRESS 6
VCC (+S.OV)
STORAGE CELL MATRIX
ADDRESS 7
ADORESS 0
ADDRESS
8
ADDRESS 1
ADD~ESS
9
ADDRESS 2
DATA 1/0 1
ADDRESS 3
A4
64x 16
AS
64x 16
64x 16
64x 16
CE
r-_______R~EF
ROW~~____~____~____~~
A6
A7
DATA 1/0 2
ADDRESS 4
DATA 1/0 3
ADDRESS S
DATA 1/0 4
WRITE ENABLE
AS
CHIP SELECT
OUTPUT DISABLE
A9
DO NOT
CONNECT
OUTPUT ENABLE
(GND) VSS
CHIP ENABLE
Vcco--
Top View
GNDo-OE
00
WE
1/01
1/02
1/03
1/04
Pin 1 is marked for orientation.
MOS·362
MOS·363
ORDERING INFORMATION
Package
Type
Hermetic
DIP
Access Time
Ambient Temperature
Power
Type
500ns
400ns
300ns
250ns
200ns
O°C':;;;;TA ':;;;;+70°C
STD
LOW
Am9131ADC
Am91 L31ADC
Am9131BDC
Am91 L31BDC
Am9131CDC
Am91 L31CDC
Am9131DDC
Am91 L31DDC
Am9131 EDC
STD
LOW
Am9131ADM
Am91L31ADM
Am9131BDM
Am91 L31BDM
Am9131CDM
Am91 L31CDM
-55°C':;;;; T A':;;;; +125°C
2-55
Am9131 • Am91L31
The Am9131 and Am91 L31 memories are identical in
every respect to their counterparts in the Am9130 and
Am91 L30 family. with the single exception that the Memory Status output is not functional. Pin 10 on the Am9131 /
L31 products should not be used and should not be connected to any external circuit. Please refer to the Am9130/
L30 data sheet for the electrical and switching characteristics of the Am9131 /L31.
Metallization and Pad Layout
.....----22
21
20
19
18
17
16
15
14
10
11----'
'-----13
'------12
DIE SIZE 0.192" x 0.197"
2-56
Am9140· Am91L40
4096 x 1 Static R/W Random Access Memories
GENERAL DESCRIPTION
DISTINCTIVE CHARACTERISTICS
•
•
•
•
•
•
•
•
o
•
•
•
•
•
•
o
•
The Am9140 and Am91 L40 products are high performance,
adaptive, low-power, 4k-bit, static, read/write random access
memories. They are implemented as 4096 words by 1 bits per
word. Only a single +5V power supply is required for normal
operation. A DC power-down mode reduces power while retaining data with a supply voltage as low as 1.5V.
4k x 1 organization
Fully static data storage - no refreshing
Single +5V power supply
High-speed - access times down to 200ns max.
Low operating power
- 578mW max., 9140
- 368mW max., 91 L40
Interface logic levels identical to TTL
High noise immunity - 400mV worst-case
High output drive - two standard TTL loads
DC power-down mode - reduces power by >80%
Single phase, low voltage, low capacitance clock
Static clock may be stopped in either state
Data register on-chip
Address register on-chip
Steady power drain - no large surges
Unique Memory Status signal
- improves performance
- self clocking operation
Full MIL temperature range available
100% MIL-STD-883 reliability assurance testing
All interface signal levels are identical to TTL specifications,
providing good noise immunity and simplified system design.
All inputs are purely capacitive MOS loads. The outputs will
drive two full TTL loads or more than eight low-power Schottky
loads.
Operational cycles are initiated when the Chip Enable clock
goes HIGH. When the read or write is complete, Chip Enable
goes LOW to preset the memory for the next cycle. Address
and Chip Select signals are latched on-chip to simplify system
timing. Output data is also latched and is available until the
next operating cycle. The WE signal is HIGH for all read operations and is LOW during the Chip Enable time to perform a
write.
Memory Status is an output signal that indicates when data is
actually valid and when the preset interval is complete. It can
be used to generate the CE input and to improve the memory
performance.
BLOCK DIAGRAM
CONNECTION DIAGRAM
AO
Al
ROW
ADDRESS
DECODER
A2
A3
64
A4
STORAGE CELL MATRIX
A5
64x64
CE
A6
ADDRESS 6
VCC (+5.0V)
ADDRESS 7
ADDRESS 0
ADDRESS 8
ADDRESS 1
ADDRESS 9
ADDRESS 2
ADDRESS 10
ADDRESS 3
ADDRESS 11
ADDRESS 4
DATA IN
ADDRESS 5
A7
COLUMN
ADDRESS
DECODER
A8
A9
DATA OUT
Al0
SENSE
AMP
All
OUTPUT
BUFFER
1/0
CONTROL
LOGIC
VCC
GND
,J
0-0--
OUT
MPR·389
WRITE ENABLE
OUTPUT DISABLE
CHIP SELECT
MEMORY STATUS
OUTPUT ENABLE
(GND) VSS
CHIP ENABLE
Top View
DATA
IN
Pin 1 is marked for orientation.
MS
MPR·390
ORDERING INFORMATION
Package
Type
Molded
Hermetic
DIP
Power
Ambient Temperature
O°C ,,;;; TA
O°C,,;;; TA
,,;;;
+ 70°C
,,;;;
-55°C,,;;; TA
,,;;;
+70°C
+125°C
Type
500ns
400ns
Access Time
300ns
STD
LOW
AM9140APC
AM9140BPC
AM9140CPC
AM91L40APC
AM91L40BPC
STD
AM9140ADC
AM9140BDC
LOW
STD
AM91L40ADC
AM9140ADM
LOW
AM91L40ADM
250ns
200ns
AM9140EPC
AM91L40CPC
AM9140DPC
AM91L40DPC
AM9140CDC
AM91L40CDC
AM9140DDC
AM91L40DDC
AM9140EDC
AM91L40BDC
AM9140BDM
AM91L40BDM
AM91L40CDM
2-57
AM9140CDM
Am9140· Am91l40
MAXIMUM RATINGS above which the usefullife'may be impaired
Storage Temperature
Ambient Temperature Under Bias
VCC with Respect to Vss
-O.5V to +7.0V
All Signal Voltages with R~spect to Vss
-O.5V to +7.0V
1.25W
Power Dissipation
The products described by this specification include internal circuitry designed to protect input devices from damaging accumulations of
static charge. It is suggested, nevertheless, that conventional precautions be observed during storage, han-dling and use in order to avoid
exposure to excessive voltages.
OPERATING RANGE
POWER DOWN RANGE
Vcc
VSS
VCC
VSS
Ambient Temperature
Part Number
4.75V < VCC < 5.25V
4.50V < VCC < 5.50V
OV
OV
1.5V < VCC < 5.25V
1.5V < vee < 5.50V
OV
OV
0°C
tA
I
I
I
mlrT'1r"X"ll~---:I~--W-RI-T-E
-DA-T-A-O-UT-.---""'»).----
tDM-H
MEMORY
STATUS
H-tDH
___(_No_te_s_6._15_)_ _ _ _ _ _ _ _ _ _ _ _ _ _ _
J~
I--tP--j
~~
______________
* Assumes output is enabled.
MPR-39:
2-60
Am9140· Am91L40
SWITCHING CHARACTERISTICS over operating range
READ/MODIFY/WRITE CYCLE (Notes 7, 8, 9)
Description
Parameter
tRMWC
R/M/W Cycle Time (Notes 5, 16)
tA
Access Time (CE to Output Valid Delay)
tEH
Chip Enable HIGH Time (Notes 14, 15)
tEL
tCH
Am9140A
Am91 L40A
Min.
Max.
Am9140B
Am91 L40B
Min. Max.
Am9140C
Am91 L40C
Min. Max.
Am9140D
Am91 L40D
Min.
Max.
Am9140E
Min.
Max.
970
785
605
510
420
500
300
400
250
Unit
ns
200
ns
700
565
435
365
300
ns
Chip Enable LOW Time (Notes 14, 15)
250
200
150
125
100
ns
Chip Enable to Chip Select Hold Time
200
170
150
130
120
ns
tAH
Chip Enable to Address Hold Time
200
170
150
130
120
ns
tCS
Chip Select to CE Set-Up Time (Note 4)
-5
-5
-5
-5,
-5
ns
tAS
Address to Chip Enable Set-Up Time
0
0
0
0
0
ns
tRS
Read to Chip Enable Set-Up Time
0
0
0
0
0
ns
tOH
Chip Enable to Output OF F Delay
0
0
0
0
0
ns.
tDH
Data input Hold Time (Note 10)
0
0
.0
0
0
ns
tDS
Data Input Set-Up Time (Note 10)
200
165
135
115
100
ns
tWW
Write Pulse Width (Note 10)
200
165
135
115
100
tCF
OE or 00 to Output OF F Delay (Note 11)
200
165
135
115
ns
100
ns
110
ns
tCO
OE or 00 to Output ON Delay (Note 11)
tDV
Data Valid after Write Delay
10
10
10
10
10
ns
tR
Read Mode Hold Time
tA
tA
tA
tA
tA
ns
tDM
Data Out to Memory Status Delay
0
tP
Internal Preset Interval
220
0
0
tEL
tEL
125
150
185
0
0
tEL
tEL
ns
tEL
ns
SWITCHING WAVEFORMS
READ/MODIFY/WRITE CYCLE
==I
.RMWC
CHIP
ENABLE
'AS----t---j
ADDRESS
!
I'" I
NI~
""
--Vi
I
I
I
f--'AH----1
~ II
.RS
I
~
I
i·ww---t I
r
I
.R
I
OUTPUI
ENABLE
i~
OUTPUT
DISABLE
DATA OUT
DATA IN
~
~
tDM
MEMORY
STATUS
I
I
INPUT
"\XXXXXXXXXXXXX
STABLEI~
f-'P-j
-----~!~------\~~
(NOTES 6, 1 5 1 ,
_
MPR-394
2-61
. Am9140' Am91L40
NOTES:
1.
Typical operating supply current values are specified for
nominal processing parameters, nominal supply voltage
and the specific ambient temperature shown.
2.
Typical power-down supply current values are specified
for nominal processing parameters, the specific supply
voltage shown and the specific ambient temperature
shown.
3.
At any operating temperature the minimum access time,
tA(min.), will be greater than the maximum CE to
output OFF delay, tOH(max.).
4.
The negative value shown indicates that the Chip Select
input may become valid as late as 5.0ns following -the
start of the Chip Enable rising edge.
5.
The worst-case cycle times are the sum of CE rise time,
tEH, CE fall time and tEL. The cycle time values shown
include the worst-case tEH and tEL requirements and
assume CE transition times of 10ns.
6.
The Memory Status signal is a two-state output and is
. not affected by the Output Disable or Output tnable
signals. If the output data buffers are turned off, Memory
Status will continue to reflect the internal status of the
memory.
7.
Output loading is assumed to be one standard TTL gate
plus 50pF of capacitance.
8.
Timing reference levels for both input and output signals
are 0.8V and 2.0V.
9.
CE and WE transition times are assumed to be ";;10ns.
10.
The internal write time of the memory is defined by
the overlap of CE high and WE low. Both signals must
be present on a selected chip to initiate a write. Either
signal can terminate a write. The tWW, tDS and tDH
specifications should all be referenced to the end of the
write time. The Write Cycle timing diagram shows
termination by the falling edge of CEo If termination is
defined by bringing WE high while CE is high, the
following timing applies:
01
~
INPUT STABLE
11.
The output data buffer can be ON and output data
valid only when Output Enable is high and Output
Disable is low. OE and OD perform the same function
with opposite control polarity.
12.
The output data buffer should be enabled before the
falling edge of CE in order to read output information.
When the output is disabled and CE is low, the output
data register is cleared.
13.
Input and output data are the same polarity.
14.
The Chip Enable waveform requirements may be defined
by the Memory Status output waveform. For a read
cycle, the basic CE requirement is that tEH;;;' tA and
tEL;;;' tP:
:-:-""M"L\'-----1
~F
MPR·396
15.
16.
The Memory Status output functions as if all operations
are read cycles. If a write cycle begins with WE low and
Data In stable at the time CE goes high, "the rising edge
of MS may be used as an indication that the write is
complete and CE may be brought low. In a cycle where
WE goes low at some point within the CE high time, the
rising edge of MS should be ignored as an indication of
write status. The falling edge of MS is always valid
independent of the type of operation being.performed.
For the R/M/W cycle, tEH (min.) is defined as tR (min.)
+ tWW. Note 5 defines tRMWC but it may also be viewed
as tRC + tWW, Modify times are assumed to be zero. For
systems with bata In and Data Out tied together R/M/W
timing should make allowance for tCF time so that no
bus conflict occurs (see Am9130 data sheet for timing
approach).
~
MPR-395
FUNCTIONAL DESCRIPTION
Block Diagram
The block diagram for the Am9140 shows the interface connections along with the general signal flow. There are twelve
address lines (AO through All) that are used to specify one
of 4096 locations, with each location containing one bit. The
Chip Select signal acts as a high order address. The Chip
Enable clock latches the addresses into the address registers
and controls the sequence of internal activities.
the rows is selected. The 64 cells on the selected row are then
connected to their respective bit line columns. Meanwhile,
the column address signals (A6 through A 11) are decoded
and used to select one of 64 columns for the sense amplifier.
Thus a single cell i~ connected into the output path.
The row address signals (AO through A5) and their inversions
are distributed to the 64 row address decoders where one of
2-62
During read operations, the sensed data is latched into the
output register and is available for the balance of the operating
cycle. During write operations, the write amplifier is turned on
and drives the input data onto the sense lines, up the column
Am9140· Am91L40
bit lines and into the selected cell. Read and write data are
the same polarity.
To execute a read cycle, WE is held high while CE is high. To
perform a write operation, the WE line is switched low while
CE is high. Only a narrow write pulse width is required to
successfully write into a cell. In many cases, however, it will
be convenient to leave the WE line low during the whole
cycle.
The data buffer is three-state and unselected chips have
their outputs turned off so that several may be wire-ored
together. The Output Enable and Output Disable signals provide asynchronous controls for turning off the output buffers.
Within the storage matrix there is an extra row of simulated
cells. This reference row is selected on every operating cycle
in addition to the addressed row and provides internal timing
signals that control the data flow through the memory. The
Memory Status output signal is derived from the reference
row and uses the same designs for its sense and buffer circuits
as used by the data bits.
A write cycle can take place only when three conditions are
met: The chip is sele,cted, CE is high, and WE is low. This
means that if either CE goes low or WE goes high, the writing
is terminated.
Chip Enable
The requirements for incoming data during a write operation
show a minimum set-up time with respect to the termination
of the write. Termination occurs when either WE goes high or
CE goes low. If incoming data changes during a write operation,
the inform;;tion finally written in the cell will be that stable
data preceeding the termination by the set-up time. Since the
data being written during a write cycle is impressed on the
sense amplifier inputs, the output data will be the same as the
input once the write is established.
Data In and Data Out
The Chip Enable input is a control clock that coordinates all
internal activities. The rising edge of CE begins each cycle and
strobes the Address and Chip Select signals into the on-chip
register. Internal timing signals are derived from CE and from
transitions of the address latches and the reference cells.
When the actual access time of the part has been reached (or
a write operation is complete). CE may be switched low if
desired. The worst-case time as specified in the data sheet may
be used to determine the access. Alternatively, the access or
write-complete time indicated by the rising edge of the
Memory Status output signal may be used.
During a read cycle, once all of the addressing is complete and
the cell information has propagated through the sense amplifier, it enters the output data register. The read information
can also flow through to the output if the buffer is enabled. As
long as CE is high, the addressing remains valid and the output
data will be stable. When CE goes low to begin the internal
preset operation, the output information is latched into the
data register. It will remain latched and stable as long as CE
is low. If the output is disabled when CE is low, the output
data register is cleared. At the start of every cycle when CE
goes high, the output data latch. is cleared in preparation for
new information to come from the sense amplifier, and the
output buffer is turned off.
When CE goes low, the internal preset operation begins. The
memory is ready for a new cycle only after the preset is
complete. The worst-case CE low time specified in the data
sheet may be used to determine the preset interval. Alternatively, the actual preset ti me is indicated as complete when
Memory Status goes low.
There are no restrictions on the maximum times that CE may
remain in either state so the clock may be extended or stopped
whenever convenient. After power-on and before beginning a
valid operation, the clock should be brought low to initially
preset the memory.
OE and 00 are designed to provide asynchronous control of
the output buffer independent of the synchronous Chip Select
control. The OE and 00 control lines perform the same
internal function except that one is inverted from the other.
If either OE is low or 00 is high, the output buffer will turn
off. If the CS input is latched low and OE is high and 00 is
low, then the output buffer can turn on when data is
available.
Address and Chip Select
The Address inputs are latched into the on-chip address
register by the rising edge of CEo Addresses must be held
stable for the specified minimum time following the rising
edge of CE in order to be properly loaded into the register.
Following the address hold time, the address inputs are ignored
by the memory until the next cycle is initiated.
Memory Status
The Chip Select input acts as a high order address for use when
the system word capacity is larger than that of an individual
chip. It allows the Address lines to be wired in parallel to all
chips with the CS lines then used to select one active row of
chips at a time. Unselected chips have their output buffers off
so that selected chips wired to the same data lines can dominate the output bus. Only selected chips can perform write
operations.
The Memory Status output is derived from. the actual performance of the reference row of cells. Since the reference row is
always doing a read operation, the MS output will appear in
every operating cycle, whether a read or write is being performed. MS uses the same output circuitry as used in the data
path. The result is that Memory Status tracks very closely
the true operating performance of the memory.
CS is latched in the same way that Addresses are. Once a
memory is selected or deselected, it will remain that way
until a new cycle with new select information begins.
Write Enable
The Write Enable line controls the read or write condition of
the devices. When the CE clock is low, the WE signal may be
in any state without affecting the memory. WE does not
affect the status of the output buffer.
The rising edge of MS indicates when output data is valid and
tracks changes in access time with changing operating conditions. The rising edge also specifies the end of the time that
CE must be held high for a read. CE may be high as long as
desired, .but may safely go low any time after MS goes high.
The falling edge of MS occurs after CE goes lOIN and the
internal preset period is complete. It indicates that CE may
go high to begin a new cycle. See the Am9130/40 Application
Note for details.
2-63
Am9140· Am91L40
CHARACTE R 1ST ICS
Access Time
Versus Ambient Temperature
Access Change
Versus Capacitive Load
Supply Current
Versus Ambient Temperature
1.3
1.2
UJ
::;
I
i=
40h-~~·--+--+~~~~--4
ts80%
Single phase, low voltage, low capacitance clock
Static clock may be stopped in either state
Data register on-chip
Address register on-chip
Steady power drain - no large surges
Full MIL temperature range available
100% reliability assurance testing in compliance with
M I L-STD-883
All interface signal levels are identical to TTL specifications, providing good noise immunity and simplified system
design. All inputs are purely capacitive MOS loads. The
outputs will drive two full TTL loads or more than eight
low-power Schottky loads.
Operational cycles are initiated when the Chip Enable clock
goes HIGH. When the read or write is complete, Chip Enable goes LOW to preset the memory for the next cycle.
Address and Chip Select signals are latched on-chip to
simplify system timing. Output data is also latched and is
available until the next operating cycle. The WE signal is
HIGH for all read operations and is LOW during the Chip
Enable time to perform a write.
BLOCK DIAGRAM
CONNECTION DIAGRAM
AO
Al
ROW
ADDRESS
DECODER
A2
A3
ADDRESS 6
VCC (+5.0V)
ADDRESS 7
ADDRESS 0
ADDRESS S
ADDRESS 1
64
A4
STORAGE CELL MATRIX
A5
64 x 64
CE
ADDRESS 9
ADDRESS 2
ADDRESS 10
ADDRESS 3
ADDRESS 11
ADDRESS 4
DATA IN
ADDRESS 5
A6
A7
DATA OUT
COLUMN
ADDRESS
DECODER
AS
A9
L____J==:;64C ==11---+----1
A10
SENSE
AMP
LATCH
All
WRITE ENABLE
CHIP SELECT
OUTPUT DISABLE
WRITE
AMP
DONOT
CONNECT
OUTPUT ENABLE
(GNDI VSS
CHIP ENABLE
1/0
CONTROL
LOGIC
VCC
GND
0---0---OE
OD
WE
DATA
OUT
Top View
DATA
IN
Pin 1 is marked for orientation,
MOS·364
MOS·365
ORDERING INFORMATION
Package
Type
Hermetic
DIP
Ambient Temperature
Power
Type
0°C VIH)
O°C
100mA
70mA
70mA
50mA
30mA
20mA
JOL
+70°C
2.1mA
2.1mA
3.2mA
3.2mA
4.0mA
4.0mA
10L
+125°C
-
-
2.4mA
2.4mA
3.2mA
3.2mA
10H
+70°C
10H
+125°C
lOS
O°C
lOS
-55°C
1.0mA
1.0mA
1.0mA
1.0mA
1.4mA
1.4mA
1.0mA
1.0mA
1.0mA
1.0mA
40mA
75mA
75mA
95mA
95mA
-
75mA
75mA
115mA
115mA
-
-
40mA
Am91L24
-
Figure 1. DC Parameter Comparison.
S.2SV
PIS = 4096N
70
(
AMD STATIC R/W RAr.l
SPEED-POWER PRODUCT
VCC : :2;6OIIS _
T
50
. . Am91L02(A)
30
20
-
tC
tC
~
60
40
~(tCS ICC) + ~tOVL
- - ICC ) +
'" '"""'~
~
Am91~0140
1975
~
19n
1976
=
Maximum average power per bit
= Chip select active time
=
=
=
=
=
Address cycle time
Current overlap time
Operating current
Power-down current
Number of 1k rows in system memory
For example, a 4k memory using Am91L24 with a Chip Select
time of 300ns and an address cycle time of 800ns would show:
""'-
10
1974
Where PIS
tCS
tC
tOVL
ICC
IPD
N
Am91L02(B)
J
tC - tCS - tOVL
tC
IPD) + (N - 1) IPD
•
-...
Am91L24
S.2SV [300
100
PIS = 4096 (4) 800 (SOmA) + 800 (SOmA) +
1978
800 - 300 - 100
]
800
(20m A) + 20mA (3)
DATE OF FIRST MANUFACTURE
1.405-366
=
Figure 2. Speed· Power Product.
0.0304mW/bit
MEMORY CAPACITY EFFECTS
The advantage of the "clocked" and the "no deselect" modes
with the Am9124 series is illustrated in Figure 4 for various memory sizes using calculations based on the above equations. Figure 4 makes the conservative assumption that the supply current (ICC) rises immediately to its maximum value when CS goes
low; that it does not change for SOnsec following the rising edge of
CS, and subsequently decreases linearly to the power-down
current (IPD) over a 100nsec period.
The second approach dynamically decodes addresses to generate Chip Select: CS is deselected (high) when no memory addressing is required. This means that the entire memory is in a
power-down mode when it is not being accessed, and one row is
powered-up only during active operations. This approach requires an extra timing signal to deactivate all CS signals when
memory access is not under way. The power dissipation equation
for this "clocked" mode is the same as in the "no deselect" mode
above, except that a duty cycle factor is also included.
_ (SUPPlY)
PIS - Voltage
(_1)~(Active
Num?er
of bits
Row
Current
)
From Figure 4, it can be observed that the Am9124 offers power
advantages that increase as system size increases. The "clocked"
mode reduces power consumption even further. In addition,
"clocked" mode may be helpful in systems where bus contention
may be a problem for any 1k x 4 part with common data 1/0.
+
Table 1 illustrates total worst-case memory supply current requirement as a function of chip count. It is assumed that the
system memory designer will take advantage of the best access
times so that the width of Chip Select will equal the width of the
read or write cycle. Typically, system memory configurations are
for~
Current )
(
Deselected )
(current
Overlap after +
Current for
+
Inactive
(
Deselect
Addressed Row
Rows
2-73
fJ
The Am9124
memory size increases and the memory system power becomes
less dependent on duty cycle. Even for small systems, the
Am9124 offers significant power savings.
400
TIMING SPECIFICATIONS
350
300
!
Am9101/11/12
The timing patterns for the 2114, the Am9114 and the Am9124 are
all the same .. The timing parameter differences between the
Am9124 and the 2114 involve tCO (Chip Select access time) in
the read operation, tW (Write Enable pulse width) and tCW (Write
Overlap)_ Table 2 summarizes the timing differences. In most
systems, the tCO differences will not be a problem. Usually, Chip
Select is decoded directly from an address. Thus, as long as tCO
plus the decode time is less than the access time, the system will
Am9102
250
200
POWER DISSIPATION
VCC = +5.25 VOLTS
TA = O"C
• = STANDBY
I
~ Am91L01/Lll/L12
, 21L02A
150
100
50
r
I
.180
Am91L02
Am91LO~C
I
; Am9130
2114
I
.160
T2114L.
Am9114.
Am9124. Am91L30
t
I
I
Am91L 14/Am91L24
--t---
.140
/,2114
' Am9124'
• Am91L24'
I
.120
4k
lk
CHIP BIT DENSITY
.100
MOS-367
I
Figure 3. Power Dissipation Improvements.
.080
such that one row (1 k words in this case) is addressed all the time
whether or not memory read/write is required; or a particular row
is addressed only when an actual read/write operation will be
performed_ The worst-case memory operating currents for the
two modes of memory operation are illustrated in the table. The
"clocked" mode of operation is shown for a memory access duty
cycle of 25%; otherwise the current consumption would be the
same as if a row was active at all times. A close approximation of
the current consumption for most such memory systems can be
calculated with the following equation:
~
.060
.040
~
"r---..... ___
r--:::
"'"
CLOCKED CS
~
Am~lL14C.
Am91L24C.
lk X N. NO DESELECT
/
....... Am9124C. 2k X
CLOCKED CS
r:r.---- r--
~
NO DESELECT
~-
.020
400
t---
~Am9124C. lk X N.
"
300
2114L
Am9114C
Am9124C. 1 k X N.
NO DESyLECT
500
Am91
L~4C.
I
4k X IN.
"T" I·
600
700
800
900
1000
CYCLE TIME - ns
~M)
LiCe = K -ICC
4
+
M
(1 - K)-IPD
4
+
M
(N -1)-IPD
4
MOS-368
Figure 4. Cycle Time Effects on Power.
Where K = duty cycle fraction
M = number of bits in a word
N = number of 1k words
not know, from a timing point of view, which chip is installed_
Similarly, most systems maintain very wide write pulse widths so
that in the write operation, the Slightly wider tW pulse widths
should not be a problem.
Example: for an 8k x 16 memory at 25% duty cycle using
Am91L24,
Ice = .25 (4) (50)
+
.75 (4) (20)
+
(8 - 1) (4) (20)
BUS CONTENTION
= 670mA
The Am9124 4k static RAMs, along with the 2114, because of
their common Data I/O pins, may have problems with bus contention when used improperly_ A similar situation is true for the earlier
Am9112 and 2112 memories. If the chip is selected and the
memory is in the Read state, then the output buffers will be driving
Data Out onto the Data I/O lines. If the external system tries to
drive the same lines with information there may be contention for
control of the I/O bus and large surge currents can result. Even
when WE is switched low, atthe start of a Write cycle for example,
there will be some delay before the internal buffers turn off and
It is evident from the table that the Am9124/L24 average worstcase current improves memory system power consumption, relative to the 2114 and 2114L, by quite significant factors, with the
exact difference depending on memory size and configuration.
The power-down feature advantage of the Am9124 is further
demonstrated by plotting the average supply current per chip
versus memory size as shown in Figure 5_ The average supply
current per chip converges towards the power-down value as
2-74
The Am9124
been turned off. Several methods are available to accomplish
this.
80
I
vcc = 5.25V
TA = O"C
In many systems CS is derived directly from addresses and is low
for the whole memory cycle. For writing, the designer should
make sure that tW is at least tOw plus tOTW and the input data
should be delayed until tOTW following the falling edge of WE.
With address setup and hold specifications of zero, it will often be
convenient to make WE a cycle-width level (tW = tWC) so that the
only subcycie timing required will be the delay before the assertion of input data.
V!~!~14
70
c(
E
60
Il.
:f
u
f5Il.
50
ffi
a:
a:
::)
U
~
40
Il.
Il.
/'
~
::)
'"w
~
c(
a:
30
...........
~
c(
20
~
~ r--
----
2k
-----
Am91L14
/~:~26UTY CYCLE)
r---..:..
"-.Am9124
Because both CS and WE must be low to cause a Write to take
place, either signal may be used to determine the effective write
pulse timing. Thus WE could be a level that goes active early in
the cycle while CS is inactive. CS then becomes the Write timing
signal, going active sometime later after tOTW has expired. In
some systems this approach will simplify the timing for driving the
Data In lines.
I
.1.
J
I
~CLE)
~Am91L24
i--
4k
For systems where CS is high for at least tOTD preceding the
falling edge of WE, tW may be used at its minimum specified
value. When CS is high for at least tOTD before the start of the
write cycle, then no other subcycle timing is necessary; WE and
Data In may occur together.
(100% DUTY CYCLE)
l'Am91L24
(25% DUTY CYCLE)
8k
16k
32k
64k
MEMORY WORD SIZE
MOS·369
MEMORY SYSTEM DESIGN
Figure 5. Capacity Effects on Power.
Figure 6 shows a typical way to connect four Am9124 chips to
make a 2k X 8 memory. The ten Address lines and the Write
Enable control line are tied in parallel to all four chips.
contention can therefore still be a problem. Such contention can
cause several problems and should not be ignored.
Address 10 and its inversion are used to select one of the two
row~ of chips for each operating cycle. As long as A 10 is low, the
upper row will be active and will communicate on the data bus
The proper system design procedure is to assure that incoming
Data to be written not be entered until the output buffers have
TABLE 1. MEMORY SUPPLY CURRENT REQUIREMENT.
Average Worst Case
Current (mA at O°C)
Memory
Configuration
2k x 8
Part
Number
One1krow
active
at all times
2114
2114L
400
280
400
280
Am9114
Am91L14
280
200
280
200
Am9124
Am91L24
200
140
140
95
1200
840
1200
840
840
600
480
330
840
600
2114
2114L
4k X 12
Am9114
Am91L14
Am9124
Am91L24
8k X 16
One 1k row
active only when
accessed at
25% duty cycle
390
262.5
2114
2114L
3200
2240
3200
2240
Am9114
Am91L14
2240
1600
2240
1600
Am9124
Am91L24
1120
760
1000
670
2-75
fJ
The Am9124
TABLE 2. TIMING COMPARISON.
tW (ns)
tCO (ns)
Cycle
Time
(ns)
2114
Am9114
200
300
450
70
100
120
Am9124
2114
Am9114
185
280
420
120
150
200
while the lower row is deselected and can neither read nor write.
When A lOis high, the row roles are reversed.
Driving and buffering limitations for both the inputs and outputs
will be dictated by a) accumulated leakage currents and b) accumulated capacitance. On an address line, for example, many
chips may be driven in parallel from a standard TTL output. As the
/10
Am9124
150
200
250
120
150
200
150
200
250
As the capacity of systems like the one in Figure 6 grows, decoding of the Chip Select information gradually involves more
logic. An 8k x 8 memory is shown in Figure 7. It takes advantage of binary decoders like the Am25LS138 or the
Am25LS2538. These parts offer package count advantages,
especially as the system gets bigger, plus control logic is included that permits deselection. A Memory Request signal is
used to deselect all the memory rows when access is not required. Thi~ approach takes advantage of the automatic
power-down feature of the Am9124.
The type of memory illustrated is easily expanded to many different capacities. A 4k X 16, for example, could be implemented
with 16 Am9124 chips (4 in each row), using the same control line
configuration, plus an additional address line decoded to enable
the correct row.
,-
Am9124
number of chips goes up, the leakage currents in the MOS
memory gradually become a significant load for the TTL
driver, especially in the high logic level state. Similarly, many
parallel inputs will present a capacitive load that degrades the
rise and fall times of the signal. Added buffering will be necessary in larger memory systems.
The Data 1/0 lines have corresponding bits tied together in vertical columns. The control logic is arranged such that only one of
the output buffers at a time will drive an I/O line, and only one
chip at a time will write from an I/O line.
ADDRESSES 0-9
tCW (ns)
2114
Am9114
Am9124
1k X 4
A
Am9124
1k X 4
A
ADDRESS 10
cs
READ/WRITE
WE
CS
WE
I/O
I/O
l
t
()
Am9124
1k X 4
A
'--' A
Am9124
1k X 4
CS
CS
WE
WE
I/O
I/O
f
4" v
t
,
4
/
V
DATA I/O
MOS-370
Figure 6. 2k x 8 Memory System.
2-76
The Am9124
ADDRESS 0-9
10
A
Am91L24
1k X 4
A
-
cs
CS
-
READ/WRITE
ADDRESS 10
A
YO
ADDRESS 11
B
Y1 v
ADDRESS 12
C
Y2
ADDRESS 13
E1
Y3
ADDRESS 14
E2
Y4
ADDRESS 15
E3
Y5
MEMORY REQUEST
E4
Y6
Y7
+
POL
0-0-00-0-0-0--
WE
OE'8
OE2
3 TO 8 DECODER
Am25LS2538
I/O
I/O
J
J
Am91L24
1k X 4
A
Am91L24
1k X 4
-
CS
cs
-
-
I/O
I/O
l
f
•
•
•
•
•
-=~A
ROW1
WE
WE
I
I
I
ROWO
-
WE
I~A
Am91L24
1k X 4
•
•
•
•
•
~
~
----;
~
Am91L24
1k X 4
A
~
~
-----4
~
~
Am91L24
1k X 4
cs
-
CS
ROW7
-
WE
WE
I/O
I/O
t
t
4.,..-
4 .......
t
DATA I/O
'-105-371
Figure 7. 8k x 8 Memory System "Clocked" Mode.
Figure 7 uses the Am25LS2538 to decode more address lines
than necessary for a capacity of 8k words. This allows considerable flexibility in where the memory is mapped within a
much larger address space. Reassignment of addresses 13,
14 and 15 allows mapping into other locations without additional logic. If Memory Request is not needed, the E4 input
may be tied high. In that case the memory will operate with
one row active at all times in the same way as Figure 6.
2-77
UV Erasable-Programmable ROM
NUMERICAL INDEX
Erasable
Page
Am1702A
Am2708
Am2716
Am2732
Am9708
Am9732
256 x 8 .................................................................. 3-1
1024 x 8 ................................................................. 3-7
2048 x 8 ............... : ................................................. 3-11
4096 x 8 ...............................................................,.. 3-16
1024 x 8 ................................................................. 3-7
4096 x 8 .' ................................................................ 3-16
Am1702A
256-Word by a-Bit Programmable Read Only Memory
GENERAL DESCRIPTION
DISTINCTIVE CHARACTERISTICS
•
Field programmable 2048 bit ROM
•
Access times down to 550 nanoseconds
The Am1702A is a 2048-bit electrically programmable ultraviolet light erasable Read Only Memory. It is organized
as 256 by 8 bits. It is packaged in a 24 pin dual in-line
hermetic cerdip package with a foggy lid.
•
100% tested for programmability
•
Inputs and outputs TTL compatible
•
Three-state output - wired-OR capability
•
Typical programming time of less than 2 minutes/device
•
Clocked VGG mode for lower power dissipation
•
100% MIL-STD-883 reliability assurance testing
The transparent lid allows the user to erase any previously
stored bit pattern by exposing the die to an ultraviolet (UV)
light source. Initially, and after each erasure, all 2048 bits are
in the zero state (output low). The data is selectively written
into specified address locations by writing in ones.
A low power version, the Am1702AL, is available which permits the VGG input to be clocked for lower average power
dissipation.
CONNECTION DIAGRAM
BLOCK DIAGRAM
P
(PROGRAMMING
INPUT)
AD
Al
A2
VOO
Al
vee
AD
vee
001
A3
002
A4
003
AS
004
A6
005
A7
006
VGG
007
VBB
008
~
A2
A3
A4
ONE.QF-256
DECODER
256 X 8
MEMORY ARRAY
A5
A6
A7
cs-----~
vee
001 002 003 004 005 006 007 008
Top View
Pin 1 is marked for orientation
MOS-373
MOS-372
ORDERING INFORMATION
Access Time (ns)
Ambient Temperature
Specification
Package
Type
Clocked
O°C to +70°C
Hermetic DIP
Transparent Window
No
Yes
AM1702A
AM1702AL
AM1702A-2
AM1702AL-2
AM1702A-1
AM1702AL-1
-55°C to +85°C
Hermetic DIP
Transparent Window
No
Yes
AM9702AHDL
AM9702ALHDL
AM9702A-2HDL
AM9702AL-2HDL
AM9702A-1HDL
AM9702AL-1 DHL
1000
VGG
3-1
650
550
Am1702A
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
Power Dissipation
1W
vee -20 V to vee +0.5 V
Input and Supply Voltages (Operating)
Input and Supply Voltages (Programming)
-50 V
The products described by this specification include internal circuitry designed to protect input devices from damaging accumulations 0
static charge. It is suggested nevertheless, that conventional precautions be observed during storage, handling and use in order to avoil
exposure to excessive voltages.
OPERATING RANGE,
Read Mode (Notes 1, 2)
vee
Ambient Temperature
VDD
vee
VGG
ELECTRICAL CHARACTERISTICS over operating range (Note 3)
Parameter
Description
Am1702A
Am9702A
Typ.
Min.
Test Conditions
ICF1
Output Clamp Current
TA = o°c, Vo = -1.0V
ICF2
Output Clamp Current
T A = 25° C, VO = -1.0V
8
Max.
Am1702AL
Am9702AL
Min.
Typ.
Max.
14
5.5
8
mA
13
5
7
mA
7
10
mA
Unit
1000
VGG = VCC, 10L = OmA
VCS = VCC -2.0, T A = 25°C
IDD1
10L =OmA, VCS =VCC-2.0,
TA = 25°C
35
50
35
50
mA
IDD2
10L=OmA,VCS=0,TA =25°C
32
46
32
46
mA
IDD3
10L = OmA, VCS = VCC -2.0,
TA = O°C
38
60
38
60
mA
VDD Current (Note 4)
IGG
VGG Current
IL1
Input Leakage CUrrent
VI = OV
ILO
Output Leakage Current
CS = VCC -2.0, VO = OV
IOH
Output Source Current
VO =OV
IOL
Output Sink Current
VO = 0.45V
VIH
Input HIGH Level
VIL
Input LOW Level
VOH
Output HIGH Level
VOL
Output LOW Level
1.6
Description
/.I A
3.5
4
mA
mA
2.0
VCC+0.3
0.65
VCC-2.0
VCC+0.3
Volts
0.65
Volts
-1.0
3.5
4.5
-3.0
1.6mA
/.I A
1.0
-2.0
-1.0
Volt!
4.5
0.45
2.0mA
Volt~
0.4
SWITCHING CHARACTERISTICS over operating range (Note
Parameter
/.I A
1.0
1.0
10H = -200/.lA
I
I
1.0
-2.0
VCC-2.0
10L
1.0
1.0
5)
Am1702A-1
Am1702AL-1
Am9702A-1
Am9702AL-1
Min.
Max.
Am 1702A-2
Am1702AL-2
Am9702A-2
Am9702AL-2
Min.
Max.
Am1702A
Am1702AL
Am9702A
Am9702AL
Min.
Max.
Unit
tACC
Address to Output Access Time
550
650
1000
tCO
Output Delay from CS
450
350
900
ns
tCS
Chip Select Delay
100
300
100
ns
ns
tDVGG
Set-up Time, VGG
tOO
Output Deselect
300
300
300
tDH
Previous Read Data Valid
100
100
100
ns
tOHC
Data Out Valid from VGG (Note 6)
5.0
5.0
5.0
/.IS
frcq.
Repetition Rate
1.8
1.6
1.0
MHz
0.3
0.3
0.4
/.IS
ns
CAPACITANCE (Note 7)
Parameter
Description
CI
Input Capacitance
CO
Output Capacitance
CVGG
VGG Capacitance
Conditions
TA = 25°C
All unused pins are at VCC
3-2
Typ
Max
Uni1
8
15
pF
10
15
pF
30
pF
Am1702A
SWITCHING WAVEFORMS
READ OPERATION (Note 2)
X
ADDRESS
I
XIXXXIIIIIII
·)UlJ[J[J[J[IJ[J[I
I--tDVGG
DATA OUT
MOS-374
DESELECTION
ADDRESS~
I- • I
tDVGG-+_---.j
vee
VGG
teo~
tCS
CLOCKED
I
VGG
~
DATADUT
;;;. Ons
j---tOD
~ DATA VALID ~-----MOS-375
CLOCKED VGG OPERATION (Note 1)
The VGG input may be clocked between +5V (VCC) and -9V
to save power. To read the data, the chip select (CS) must be
low (~ VIL) and the VGG level must be lowered to -9V at
leasttDVGG priorto the address selection. Once the data has
appeared atthe output and the access time has elapsed, VGG
may be raised to +5V ..The data output will remain stable for
tOHC. To deselect the chip, CS is raised to ~ VIH, and the
output will go the high impedance state after tOD. The chip
will be deselected when CS is raised to VIH whether the VGG
is at +5V or at -9V.
3-3
Am1702A
Programming Boards are available forthe Data 1/0 automatic
programmer (part number 1010/1011), for the S'pectrum
Dynamics programmer (part number 434-549), and for the
Pro-Log programmer (part number PM9001).
PROGRAMMING THE Am1702A
Each storage node in the Am1702A consists of an MOS
transistor whose gate is not connected to any circuit element. The transistors are all normally off, making all outputs
LOW in an unprogrammed device. A bit is programmed to a
HIGH by applying a large negative voltage to the MOS transistor; electrons tunnel through the gate insulation onto the
gate itself. When the programming voltage is removed, a
charge is left on the gate which holds the transistor on. Since
the gate is completely isolated, there is no path by which the
charge can escape, except for random high energy electrons
which might retunnel through the gate insulation. Under
ordinary conditions retunneling is not significant. The application of high energy to the chip through X-rays or UV light
(via the quartz window) raises energy levels so that, the
charge can escape from the gate region, erasing the program
and restoring the device to all LOW.
ERASING THE Am1702A
The Am1702A may be erased (restored to all LOW's) by
exposing the die to ultraviolet light from a high intensity
source. The recommended dosage is 6 W-sec/cm 2 at a
The Ultraviolet Products, Inc., models
wavelength of 2537
UVS-54 or S-52 can erase the Am1702A in about 15 minutes,
with the devices held one inch from the lamp. (Caution
should be used when Am1702A's are inspected under
fluorescent lamps after being programmed, as some
fluorescent lamps may emit sufficient UV to erase or "soften" the PROM.)
A.
In order to program a specified byte, al18 address lines must
be in the binary complement of the address desired when
pulsed VDD and VGG move to their negative level. The complemented address must be stable for at least tACW before
VDO and VGG make their negative transitions. The voltage
swing of the address lines during programming is between
-47V ± lV and OV. The addresses must then make a transition to the true state at least tATW before the program pulse
is applied. For good data retention, the addresses should be
programmed in sequence from 0 to 255, a minimum of 32
times. 001 through 008 are used as the data inputs to
program the desired pattern. A low level at the data input
(-47V ± 1V) will program the selected bit to 1 and a high
level (OV) will program it to a O. All 8 bits addressed are
programmed simultaneously.
PROGRAMMING REQUIREMENTS (Note
Parameter
CAUTION
Ultraviolet radiation is invisible and can damage human
eyes. Precautions should be taken to avoid exposureto direct
or reflected ultraviolet radiation. It will often be convenient to
fully enclose the ultraviolet source and the EROMs being
erased to prevent accidental exposure.
Ultraviolet lamps can also ionize oxygen and create ozone
which is harmful to humans. Erasing should be carried out in
a well ventilated area in order to minimize the concentration
of ozone.
2)
Description
ILl1P
I nput Current, Address and Data
ILl2P
I nput Current, Program and VGG Inputs
IBB
VBB Current
lOOP
IOD Current During Programming Pulse
VIHP
Input HIGH Voltage
Condition
Max.
Unit
VI = -48V
10
mA
VI = -48V
10
mA
Min.
Typ.
0.05
VDD = VProg = -48V, VGG = -35V
200
mA
Note 8
mA
0.3
Volts
VIL1P
Voltage Applied to Output to Program a HIGH
-:-46
-48
Volts
VIL2P
Input LOW Level on Address Inputs
-40
-48
Volts
VIL3P
Voltage Applied to VDD and Program Inputs
-46
-48
Volts
VIL4P
Voltage Applied to VGG Input
-35
-40
Volts
tr/>PW
Programming Pulse Width
3.0
ms
tDW
Data Set-up Time
25
IlS
tDH
Data Hold Time
10
IlS
tVW
VGG and VDD Set-up Time
tVD
VGG and VDD Hold Time
10
tACW
Address Set-up Time (Complement)
25
IlS
tACH
Address Hold Time (Complement)
25
IlS
tATW
Address Set-up Time (True)
10
IlS
tATH
Address Hold Time (True)
10
IlS
VGG = -35V, VDD = VProg = --48V
100
Duty Cycle
IlS
100
20
3-4
IlS
%
Am1702A
PROGRAMMING WAVEFORMS
ADDRESS
INPUTS
x~
0=X;
I
A
-40 TO -48
------'
i-tACW-j
tATH---\
VDD
-46 TO -48
------i--/'----+----+--'
VGG
-35TO-40------~--_4---~--J
OUTPUTS
tDH
PROGRAM PIN
-46 TO -48 - - - - - - - - -
MOS-376
TYPICAL PERFORMANCE CURVES
900
-
800
700
w
:;:
~
til
til
W
u
u
Average Current Versus
Duty Cycle for Clocked VGG
Access Time
Versus Temperature
Access Time
Versus Load Capacitance
900 r -......-r"--.-r-"T"""""T"~--,,......,
45
1-+--+-I--t---+--+-+-1r---;
40
800
700 _ _
~
600
I
500
:;:
400
til
til
E
I
600
w
~
t--+---+--+--+--t--t
200
t--+---+--+--+--t--t
100
I-+-+--+--+-+--I-
a
a
~
lTTL LOAD
VCC= +5V
VDD = -9V
VGG = -9V
T A = 25' C
e
25
(!)
20
w
300
~
~
200
vee = +5V
100
VDD= -9V
VGG = -9V
a
a
LOAD CAPACITANCE - pF
ffi
>
1 TTL LOAD::: 20 pF
~
I
:r\. ,
~
E
I
~
4
3
2
1
o
a
f-
::>
u
e
"' "I"I".
'"
I"
I"
DUTY CYCLE - %
e
J J L
w
I". ,,~=vec·-I.1.. 1 1.1
g~
1 1 1
I 1 1
-4 J--J---t
::>E
iill
csl = ~.O ~-I-
~ ~ -4.5 l--1h~
o..W
f-O::
::>0::
-I-
20
40
60
80
100
AMBIENT TEMPERATURE _ 'e
~a -5~/~~~-~-~-~~
e
120
VOO VOLTAGE - VOLTS
Output Current
Versus Temperature
~~
4
2u
3
w
a
U
o::~
::>E
iill
f-f-
~ffi
2
16
"- ~
.........
VCC = +5V
VDO =.-9V
VGG = -9V
VOL = +0.45V
1
-
I ...L
~
E
I
f-
~
r- ~-.J I
CS =0.0 ~-~
::>
u
><:
--
en
VCC = +5V
~- VOD=-9V
VGG = -9V
4
-VOL=O.OV
-
f-O::
::>0::
0::>
.:r U
Output Sink Current
Versus Output Voltage
5
f-I
::>fo..z
f-w
::>0::
00::
..J::>
10 20 30 40 50 60 70 80 90 100
~~
I I I I
(jr-
a
f-I
::>fo..z
f-w
::>0::
00::
..J::>
u
VOD = -9V
VGG =-9V
INPUTS = VCC
OUTPUTS ARE OPEN
9
8
7
.,""
VI'
Output Current
Versus VOD Supply Voltage
I
vcc = +5V
~
,/~
.,""
1000
a
20 30 40 50 60 70 80 90
AM81ENT TEMPERATURE _ 'C
10
IDO Current
Versus Temperature
9
15
10
1001
,/
0
500
10 20 30 40 50 60 70 80 90 100
~ I\,
35
30
400
W
300
~
CLOCKED VGG = -9V
VDD=-9V
CS = VIH
TA = 2S'C
_-1:1S =
12
VCC = +5V
VDD= -9V
VGG =-9V
VOL = 25'C
10
z
CS=O.O~
f-
~
p.o j
e
o
. /V
-3
-2 -1
0
1
OUTPUT VOLTAGE - VOLTS
3-5
/
,/
-4
10 20 30 40 50 60 70 80 90
AM81ENT TEMPERATURE _ 'C
V
./
f::>
0
..J
5
0
14
MOS-377
Am1702A
NOTES:
1. During read operations VGG may be clocked high to reduce power consumption. This involves swinging VGG
up to VCC. See "Clocked VGG Operation". This mode is
possible only with the Am1702AL.
2. During Read operations:
Pins 12, 13, 15,22,23 = +5.0V ±5%
Pins 16, 24 = -9.0V ±5%
During Program operations:
TA = 25°C
Pins 12, 22, 23 = OV
Pins 13, 24 are pulsed low from OV to -47V ±1V
Pin 15 = +12.0V ±10%
Pin 16 is pulsed low from OV to -37.5V ±2.5V
3. Typical values are for TA = 25°C, nominal supply voltages
and nominal processing parameters.
4. IDD may be reduced by pulsing the VGG supply between
VCC and -9V. VDD current will be directly proportional to
the VGG duty cycle. The data outputs will be unaffected by
address or chip select changes while VGG is at VCC. For
this option specify AM1702AL.
5. VIL = OV, VIH = 4.0V, tr = tf .:;; 50ns, Load = 1 TTL gate.
6. The output will remain valid for tOHC after the VGG pin is
raised to VCC, even if address change occurs.
7. These parameters are guaranteed by design and are not
100% tested.
8. Do notallowlDDtoexceed300mAformorethan 100JLsec.
3-6
Am9708/Am2708
1024
x 8 Erasable Read Only Memory
GENERAL DESCRIPTION
DISTINCTIVE CHARACTERISTICS
•
•
•
•
•
•
•
•
•
•
The Am2708 is an 8,192-bit erasable and programmable MOS
read-only memory. It is organized as 1024 words by 8 bits per
word. Erasing the data in the EROM is accomplished by
projecting ultraviolet light through a transparent window for a
predetermined time period.
Direct replacement for Intel 2708/8708
Interchangeable with Am9208, Am9216 masked ROMs
Full military temperature operation
Fast programming time - typically 50 sec.
TTL compatible interface signals
Fully static operation - no clocks
Fast access time - 350ns
Three-state outputs
Tested for 100% programmability
100% MIL-STD-883 reliability assurance testing
When the Chip SelectlWrite Enable input is at the high logic
level, the device is unselected and the data lines are in their high
impedance state. The device is selected when CSIWE is at the
low logic level. The contents of a particular memory location,
specified by the 10 address lines, will be available on the data
lines after the access time has elapsed. For programming,
CSIWE is connected to +12V and is used in conjunction with
the Program input. The Address and Data lines are TTL compatible for all operating and programming modes.
CONNECTION DIAGRAM
BLOCK DIAGRAM
24
VCC(+5V)
23
ADDRESSB
ADDRESS 5
22
ADDRESS 9
ADDRESS 4
21
VBB(-5V)
ADDRESS 3
20
CHIP SELECT/
WRITE ENABLE
19
VDD(+12V)
128 X 64
MEMORY ARRAY
ROW
SELECT
A4-A9
ADDRESS 7
ADDRESS 6
ADDRESS 2
PROGRAM - - - - - - -
AO-A3
ADDRESS 1
------,
CS/WE ------~
Am2708!
Am9708
DATA BUFFERS
18
PROGRAM
ADDRESS 0
17
DATA OUT8
DATA OUT 1
16
DATA OUT7
10
15
DATAOUT6
DATA OUT3
11
14
DATAOUT5
(GND)VSS
12
13
DATAOUT4
DATA OUT2
D01-D08
Top View
Pin 1 is marked for orientation.
MOS-053
MOS-052
ORDERING INFORMATION
Package
Type
Hermetic DIP
Transparent Window
Hermetic DIP
Transparent Window
Ambient Temperature
Specification
O°C ~ TA ~ + 70°C
-55°C
~
TA
3-7
~
+125°C
Order Number
AM270BDC (450ns)
AM270B-1DC (350ns)
AM970BDM (4BOns)
Am970B/Am2708
MAXIMUM RATINGS
above which the useful life may be impaired
Storage Temperature
Ambient Temperature Under Bias
All Signal Voltages, except Program and eS/WE, with Respect to VBB
-O.3V to +15V
Program Input Voltage with Respect to VBB
-O.3V to +35V
eS/WE Input with Respect to VBS
-O.3V to +20V
vee and VSS with Respect to VSS
-O.3V to +15V
VDD with Respect to VBB
-O.3V to +20V
1.5W
Power Dissipation
The product described by this specification includes internal circuitry designed to protect input devices from excessive accumulation of
static charge. It is suggested, nevertheless, that conventional precautions be observed during storage, handling and use in order to avoid
exposure to any voltages that exceed the maximum rating$.
OPERATING RANGE
Ambient Temperature
VDD
VBB
VCC
VSS
O°C to +70°C
- 55°C to + 125°C
PROGRAMMING CONDITIONS
Ambient Temperature
VDD
VCC
VBB
VSS
CS/WE
VIHP
+25°C
READ OPERATION
ELECTRICAL CHARACTERISTICS
Parameters
VIL
over operating range (Notes 1,7)
Description
Test Conditions
Min.
Input LOW Voltage
VIH
Input HIGH Voltage
VOL
Output LOW Voltage
VOH
Output HIGH Voltage
Typ.
Max.
Units
VSS
0.65
Volts
TA = O°C to +70°C
3.0
VCC+l
Volts
TA = -55°C to +125°C
2.4
VCC+l
Volts
0.45
Volts
IOL = 1.6mA
IOH = - lOO/LA
3.7
Volts
IOH = -1.0mA
2.4
Volts
III
Address and Chip Select
Input Load Current
VSS ",;; VIN ",;; VCC
1.0
10
/LA
ILO
Output Leakage Current
VOUT = Worst Case
CSIWE = + 5.0V
1.0
10
/LA
IDD
VDD Supply Current
ICC
VCC Supply Current
ISS
VSS Supply Current
TA = O°C
50
TA = -55°C
All inputs HIGH.
CSIWE = +5.0V
TA = O°C
6.0
TA=-55°C
30
TA = O°C
Power Dissipation
TA = 70°C
CIN
Input Capacitance
COUT
Output Capacitance
TA = 25°C
f = lMHz
All pins at OV
READ OPERATION
SWITCHING CHARACTERISTICS
Parameters
tACC
over operating range .(Notes 2, 7)
Description
Address to Output Access Time
(Note 3)
tCO
Chip Select to Output on Delay
(Note 4)
tDF
Chip Select to Output OFF Delay
tOH
Previous Read Data Valid with
Respect to Address Change
Test Conditions
Output Load:
One Standard
TTL Gate Plus
100pF
Max.
4.0
6.0
pF
8.0
12.0
pF
-55°e",;; TA ",;; +125°e
Min.
120
0
3-8
mA
mW
450! 350
0
mA
800
270812708-1
tr = tf",;; 20ns
45
mA
60
ooe ",;; TA ",;; 70 0 e
Min.
10
15
TA = -55°C
PD
65
80
120
0
0
Max.
Units
480
ns
150
ns
150
Am9708lAm2708
PROGRAMMING CHARACTERISTICS under programming conditions
Parameter
Description
Min.
Max.
Units
tAS
Address Set Up Time
10
J.lS
tCSS
CS/WE Set Up Time
10
J.lS
tDS
Data Set Up Time
10
J.lS
tAH
Address Hold Time (Note 5)
1.0
J.lS
tCH
CS/WE Hold Time (Note 5)
0.5
J..LS
tDH
Data Hold Time
1.0
J.lS
tDF
Chip Select to Output Off Delay
tDPR
Program to Read Delay
0
120
ns
10
J.lS
ms
tPW
Program Pulse Width
0.1
1.0
tPR, tPF
Program Pulse Transition Times
0.5
2.0
J.lS
VIHW
CS/WE Input High Level
11.4
12.6
Volts
VIHP
Program Pulse High Level (Note 6)
25
27
Volts
VILP
Program Pulse Low Level (Note 6)
VSS
1.0
Volts
SWITCHING WAVEFORMS
READ CYCLE
A D D R E S S _ X ' - - - -_ _ _
X'----_
I
CS/WE
DATA OUT
~-,CO-,oH~---:--1~-.-II
fl,,,
--------------.. .t:!XXXt
'"""'
LOA" I--~~
~
VALID
MOS·054
PROGRAM MODE (Note 5)
-READ~t
LOOP • ••-------------------------------ONEPROGRAMLOOP------------------------------~-------RLOEAODp
VIHW
=tj-------------lHI-----------,
CS/WE
VIL
VIH
ADDRESS
VIL
VIHP
PROGRAM
PULSE
VILP
I
II
ADDRESS 0
:2K M"'~'
A_D_D_R_ES_S_1_02_3. . . ;._. . .J.~ _~
:f-A_D_D_R_ES_S_1O_2J.2:-L...¥..l..._ _
_ __
I ~tcss~t~tPW-1
I
~I....oo--~tDF ItDS~
VIH
DATA
01-08
~
"tJ:
~-----DA-T-A-I-N---~~~~~----D~A~A·~~IN ~~~~
___
_ _ _ _D_A_T_AIN_ _ _ _
~~~~~~D_~_:_TA_
VIL
MOS·055
3-9
Am9708lAm2708
PROGRAMMING THE Am2708
All 8192 bits of the Am270B are in the logic HIGH state after
erasure. When any of the output bits are programmed, the output state will change from HIGH to LOW. Programming of the
device is initiated by raising the CS/WE input to +12V. A
memory location is programmed by addressing the device and
supplying B data bits in parallel to the data out lines. When
address and data bits are set up, a programming pulse is applied
to the program input. All addresses are programmed sequentially in a similar manner. One pass through all 1024 addresses
is considered one program loop. The number of program loops
(N) required to complete the programming cycle is a function
of the program pulse width (tPW) such that N > 100ms/tPW
requirement is met. Do not apply more than one program pulse
per address without sequentially programming all other
addresses. There should be N successive loops through all locations. The Program pin will source the IIPL current when it
is low (VILP) and CS/WE is high (VIHW). Thu Program pin
should be actively pulled down to maintain its low level.
ERASING THE Am2708
The Am270B can be erased by exposing the die to highintensity, short-wave, ultra-violet light at a wavelength of 2537
angstroms through the transparent lid. The recommended
dosage is ten watt-seconds per square centimeter. This erasing
condition can be obtained by exposing the die to model S-52
ultraviolet lamp manufactured by Ultra-Violet Products, Inc.
or Product Specialties, Inc. for approximately 20 to 30 minutes
from a distance of about 2.5 centimeters above the transparent
lid. The light source should not be operated with a short-wave
filter installed. All bits will be in a logic HIGH state when
erasure is complete.
CAUTION
Ultraviolet radiation is invisible and can damage human eyes.
Precautions should be taken to avoid exposure to direct or
reflected ultraviolet radiation. It will often be convenient to
fully enclose the ultraviolet source and the EROMs being
erased to prevent accidental exposure.
Ultraviolet lamps can also ionize oxygen and create ozone
which can be harmful to humans. Erasing should be carried
out in a well ventilated area in order to minimize the concentration of ozone.
NOTES:
1. Typical values are for T A = 25° C, nominal supply voltages
and nominal processing parameters.
2. Timing reference levels (Read) Inputs: High = 2.8V (DC), 2.2V (OM); Low = O.BV
Outputs: High = 2.4V, Low = O.BV
3. Typical access time is 280ns.
4. Typical chip select to output on delay is 60ns.
5. tAH must be greater than tCH.
6. VIHP-VILP>25Volts.
7. VSS must be applied prior to VCC and VDD. VSS must
also be the last power supply switched off.
Am2716/Am4716
x
2048
8-Bit UV Erasable PROM
DISTINCTIVE CHARACTERISTICS
•
•
•
•
•
•
•
•
•
GENERAL DESCRIPTION
Direct replacement for Intel 2716
Interchangeable with Am9218 - 16K ROM
Single +5V power supply
Fast access time - 450ns standard with 350ns and 390ns
options
Low power dissipation
- 525mW active
- 132mW standby
Fully static operation - no clocks
Three-state outputs
TTL compatible inputs/outputs
100% MIL-STD-883 reliability assurance testing
The Am2716/Am4716 is a 16384-bit ultraviolet erasable and programmable read-only memory. It is organized as 2048 words
by 8 bits per word, operates from a single +5V supply, has a
static standby mode and features fast single address location
programming.
Because the Am2716/Am4716 operates from a single +5V supply, it is ideal for use in microprocessor systems. All programming
signals are TTL levels, requiring a single pulse. For programming
outside of the system, existing EPROM programmers may be
used. Locations may be programmed singly, in blocks, or at
random. Total programming time for all bits is 100 seconds.
BLOCK DIAGRAM
CONNECTION DIAGRAM
Top View
DATA OUTPUTS
00-0 7
Vee 0---GND 0---VPP 0----
OE
OUTPUT ENABLE
CHIP ENABLE AND
PROG LOGIC
CEJPGM
Ao-A1O
ADDRESS
INPUTS
==
-----
~
ttt
tttt
A7C~bvee
OUTPUT BUFFERS
~
V
DECODER
f
V-GATING
r--!I-
r-;-
·
··
X
DECODER
16384 BIT
CELL MATRIX
~
Mode
22b A9
A.4C4
21 b
VPP
A3 C
5
20b
OE
A2 C
6
19
Al C
7
Am27161
Am4716
b
Al0
18 ::J CE/PGM
AoCa
17::Je>r
00 C
16 ::J 06
9
15 ::J 05
11
14
GNDe 12
13
02 C
MODE· SELECTION
~
23b
3
01C 10
MOS-199
As
Aj;C2
As C
b
b
04
03
MOS-200
CElPGM
(18)
OE
(20)
Vpp
(21)
Vee
(24)
Outputs
(9-11, 13-17)
Read
V IL
VIL
+5
+5
DOUT
Standby
VIH
Don't Care
+5
+5
High
Program
Pulsed
VIL to V IH
V IH
+25
+5
DIN
Program Verify
V IL
VIL
+25
+5
DOUT
Program Inhibit
V IL
VIH
+25
+5
High
Z
Addresses
Outputs
CElPGM: Chip Enable/Program
OE:
Output Enable
Ao-A10:
°o-OJ:
Z
ORDERING INFORMATION
Package Type
Hermetic DIP
Transparent Window
Ambient Temperature
Specification
O°C os;; TA os;; +70°C
Order
Number
tAcc (n8)
tce(ns)
AM2716DC
450
450
120
AM2716-1DC
350
350
120
AM2716-2DC
390
390
120
AM2716-6DC
450
650
200
AM4716DC
450
1000
200
AM4716-6DC
650
650
200
3-11
toe(ns)
Am2716/Am4716
MAXIMUM RATINGS
above which the useful life may be impaired
-65 to +125°e
Storage Temperature
Ambient Temperature Under Bias
+6 to -O.3V
Voltage on All Inputs/Outputs (except V pp ) with Respect to GND
+26.5 to -O.3V
Voltage on Vpp During Program with Respect to GND
READ OPERATION
DC CHARACTERISTICS
ooe.s; TA ~ +70oe, Vee (Notes 1, 2)
= +5V
±5%, except +5V ±10% for Am2716-1, Vpp (Note 2)
Parameters
Min
Test Conditions
Description
= Vee for all device types.
Max
Units
/LA
III
Input Load Current
VIN
ILO
Output Leakage Current
VOUT
10
/LA
IpP1 (Note 2)
Vpp Current
= 5.25V/OV
= 5.25V/OV
Vpp = 5.25V
10
5 (Note 3)
mA
lee1 (Note 2)
Vee Current (Standby)
CE
= VIH' OE = VIL
25
mA
lee2 (Note 2)
Vee Current (Active)
OE
= CE = VIL
100
mA
VIL
Input Low Voltage
-0.1
O.S
Volts
2.0
Vee+ 1
Volts
0.45
Volts
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
= 2.1 mA @ Vee (Min)
IOH_ = -4oo/LA @ Vee (Min)
IOL
Volts
2.4
AC CHARACTERISTICS
ooe.s; TA ~ +70 oe, Vee (Notes 1, 2)
Parameters
= +5V
Description
±5%, except +5V ±10% for Am2716-1, Vpp (Note 2)
Test Conditions
(Note 4)
CE to Output Delay
= OE =
OE = VIL
Output Enable to Output Delay
CE = V1L
tOF
Output Enable High to
Output Float
CE
toH
Output Hold from Addresses,
CE or OE, Whichever
Occurred First
CE = OE = V1L
tAee
tee
toe
Address to Output Delay
CAPACITANCE
TA
CE
Min
Values
V 1L
= V1L
0
= Vee for all device types.
Max Values
2716
2716-1
2716-2
2716-6
4716
4716-6
Units
450
350
390
450
450
650
ns
450
350
390
650
1000
650
ns
120
120
120
200
200
200
ns
100
100
100
100
100
100
ns
ns
0
(Note 5)
= +25°e, f = 1MHz
Parameters
Typ
Max
Units
Input Capacitance
VIN = OV
4
6
pF
Output Capacitance
VOUT = OV
S
12
pF
Description
Test Conditions
Notes: 1. Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
2. Vpp may be connected directly to Vee except during programming. The supply current would then be the sum of lee and IpP1'
3. SmA for Am4716 and Am4716-6.
4. Other Test Conditions: a) Output Load: 1 TTL gate and CL = 100pF
b) Input Rise and Fall Times: .;;20ns
c) Input Pulse Levels: O.S to 2.2V
d) Timing Measurement Reference Level:
Inputs: 1V and 2V
Outputs: O.SV and 2V
5. This parameter is only sampled and is not 100% tested.
; 3-12
Am2716/Am4716
AC WAVEFORMS (Note 1)
~--------------ADDRESSES
VALID
ADDRESSES
'-----------------
'----------------1 - - - - - tcE-----'
1'------1--------
HIGHZ
HIGHZ
OUTPUT
'\"",.l1....a.....I....a...""'""....._ _ _ _ _ _ _ _ _ _ _ _-1..1-'-1-1
MOS-201
Notes: 1. Vcc must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
2. OE may be delayed up to tACC - tOE after the falling edge of CE without impact on tACC'
3. tOF is specified from DE or CEo whichever occurs first.
3-13
Am2716/Am4716
PROGRAM OPERATION
DC PROGRAMMING CHARACTERISTICS
TA
=
+25°C ±5°C, VCC (Note 1)
= 5V
Parameters
±5%, Vpp (Notes 1, 2)
= 25V
::t1V
Test Conditions
Description
Min
Max
Units
III
Input Current
VIN = 5.25/0.45V
10
p,A
IpP1
Vpp Supply Current
CE/PGM = V IL
5
rnA
IpP2
Vpp Supply Current During Programming Pulse
CE/PGM = VIH
30
rnA
lee
Vee Supply Current
V IL
Input Low Level
V IH
Input High Level
100
rnA
-0.1
O.B
Volts
2.0
Vee +1
Volts
AC PROGRAMMING CHARACTERISTICS
TA
=
+25°C ±5°C, VCC (Note 1)
Parameters
= 5V
±5%, Vpp (Notes 1, 2)
= 25V
Description
±1V
Test Conditions
Min
Max
Units
tAs
Address Set-up Time
2
p,s
tOES
Output Enable Set-up Time
2
p,s
tos
Data Set-up Time
2
p,s
tAH
Address Hold Time
2
p,s
tOEH
Output Enable Hold Time
tOH
Data Hold Time
tOF
Output Disable to Output Float Delay (CE/PGM = Vld
0
120
toE
Output Enable to Output Delay (CE/PGM = Vld
-
120
ns
tpw
Program Pulse Width
45
55
ms
Input tR and tF (10% to 90%) = 20ns
Input Signal Levels = O.B to 2.2V
Input Timing Reference Level = 1V and 2V
Output Timing Reference Level =:' O.BV and 2V
2
p,s
2
p,s
ns
tpRT
Program Pulse Rise Time
5
-
ns
tPFT
Program Pulse Fall Time
5
-
ns
Notes: 1. Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
2. Vpp must not be greater than 26 volts including overshoot. Perrrlanent device damage may occur if the device is taken out of or put into the socket
when Vpp = 25 volts is applied. Also, during OE = CE/PGM = VIH' Vpp must not be switched from 5 volts to 25 volts or vice versa.
PROGRAMMING WAVEFORMS
PROGRAM
VERIFY
PROGRAM
VIH
ADDRESSES
VIL
lAS
VIH
DATA IN
STABLE
ADD N
DATA OUT
VALID
DATA
DATA IN
STABLE
ADD N + M
VIL
VIH
()E
VIL
VIH
~PGM
VIL
lPRT
MOS-202
3-14
Am2716/Am4716
ERASING THE Am2716/Am4716
In order to clear all locations of their programmed contents, it is
necessary to expose the Am2716/Am4716 to an ultraviolet light
source. A dosage of 15 Wseconds/cm 2 is required to completely
erase an Am2716/Am4716. This dosage can be obtained by
exposure to an ultraviolet lamp [wavelength of 2537 Angstroms
(A)] with intensity of 12000pW/cm2 for 15 to 20 minutes. The
Am2716/Am4716 should be about one inch from the source and
all filters should be removed from the UV light source prior to
erasure.
It is important to note that the Am2716/Am4716, and similar devices, will erase with light sources having wavelengths shorter
than 4000 Angstroms. Although erasure times will be much
longer than with UV sources at 2537 nevertheless the exposure
to florescent light and sunlight will eventually erase the Am2716/
Am4716, and exposure to them should be prevented to realize
maximum system reliability. If used in such an environment, the
package windows should be covered by an opaque label or
substance.
A,
device selection. Output Enable (OE) is the output control and
should be used to gate data to the outputs pins, independent of
device selection. Assuming that addresses are stable, address
access time (tACe) is equal to the delay from CE to output
(tCE) for all devices except Am2716-6 and Am4716. Data is
available~ the outputs 120~or 200ns (tOE) after the falling
edge of OE, assuming that CE has been low and addresses
have been stable for at least tACC - toE.
STANDBY MODE
The Am2716/Am4716 has a standby mode which reduces the
active power dissipation by 75%, from 525mW to 132mW. The
Am2716/Am4 716 is placed in the standby mode by applying a TTL
high signal to the CE input. When in standby mode, the outputs
are in a high impedance state, independent of the OE input.
OUTPUT OR-TIEING
To accommodate multiple memory connections, a 2-line control
function is provided to allow for:
1. Low memory power dissipation
2. Assurance that output bus contention will not occur.
PROGRAMMING THE Am2716/Am4716
It is recommended that CE be decoded- and used as the primary
device selecting function, while OE be made a common connection to all devices in the array and connected to the READ line
from the system control bus. This assures that all deselected
memory devices are in their low-power standby mode and that
the output pins are only active when data is desired from a
particular memory device.
Upon delivery, or after each erasure the Am2716/Am4716 has all
16384 bits in the "1," or high state. "Os" are loaded into the
Am2716/Am4716 through the procedure of programming.
The programming mode is entered when +25V is applied to the
Vpp pin and when OE is at VIH' The address to be programmed is
applied to the proper address pins. 8-bit patterns are placed on
the respective data output pins. The voltage levels should be
standard TTL levels. When both the address and data are stable,
a 50msec, TTL high level pulse is applied to the CE/PGM input to
accomplish the programming.
PROGRAM INHIBIT
Programming of multiple Am2716/Am4716s in parallel with different data is also easily accomplished. Except for CE/PGM, all
like inputs (including DE) of the parallel Am2716/Am4716s may
be common. A TTL level program pulse applied to an Am2716/
Am4716's CE/PGM input with Vpp at 25V will program that
Am2716/Am4716. A low level CE/PGM input inhibits the other
Am2716/Am4716s from being programmed.
The procedure can be done manually, address by address, randomly, or automatically via the proper circuitry. All that is required
is that one 50msec program pulse be applied at each address to
be programmed. It is necessary that this program pulse width not
exceed 55msec. Therefore, applying a DC level to the CE/PGM
input is prohibited when programming.
PROGRAM VERIFY
READ MODE
A verify should be performed on the programmed bits to determine that they were correctly programmed. The verify may be
performed with Vpp at 25V. Except during programming and
program verify, Vpp must be at VCC'
The Am2716/Am4716 has two control functions, both of which
must be fogically satisfied in order to obtain data at the outputs.
Chip Enable (CE) is the power control and should be used for
3-15
Am 9732/Am2732
4096 x 8-Bit UV Erasable PROM
DISTINCTIYE CHARACTERISTICS
GENERAL DESCRIPTION
•
•
•
•
•
The Am2732 is a 32768-bit ultraviolet erasable and programmable read-only memory. It is organized as 4096 words by 8 bits
per word, operates from a single +5V supply, has a static standby
mode, and features fast single address location programming.
•
•
•
•
Direct replacement for Intel 2732
Pin compatible with Am9233 - 32K ROM
Single +5V power supply
Fast access time - 450ns
Low power dissipation
- 787mW active
-157mW standby
Fully static operation - no clocks
Three-state outputs
TTL compatible inputs/outputs
100% MIL-STD-883 reliability assurance testing
Because the Am2732 operates from a single +5V supply, it is
ideal for use in microprocessor systems. All programming signals
are TTL levels, requiring a single pulse. For programming outside·
of the system, existing EPROM programmers may be used.
Locations may be programmed singly, in blocks, or at random.
Total programming time for all bits is 200 seconds.
BLOCK DIAGRAM
CONNECTION DIAGRAM
DATA OUTPUTS
VCCo-
00-07
GNDoVPPOOUTPUT ENABLE
CHIP ENABLE AND
PROG LOGIC
OUTPUT BUFFERS
V
DECODER
V-GATING
AD-All
ADDRESS
INPUTS
24
A6
23
AS
A5
22
A9
A4
21
All
A3
20
OEivpp
19
Al0
A2
X
DECODER
Am9732/
Am2732
Al
32768-BIT
CELL MATRIX
vee
A7
18
CE/PGM
AO
17
07
00
16
06
05
01
10
15
02
11
14
04
GND
12
13
03
MOS-490
MODE SELECTION
~
MOS-491
CE/PGM
(18)
OEivPp
(20)
vee
(24)
Read
VIL
VIL
+5
DOUT
Standby
VIH
Don't Care
+5
HighZ
Program
VIL
VPP
+5
DIN
Program Verify
VIL
VIL
+5
DOUT
Program Inhibit
VIH
VPP
+5
HighZ
Mode
Outputs
(9-11,13-17)
Top View
Pin 1 is marked for orientation.
AO-A11:
00-07:
CE/PGM:
OENPP:
Addresses
Outputs
Chip Enable/Program
Output Enable
ORDERING INFORMATION
Order Number
Package
Type
Ambient Temperature
Specification
450ns
550ns
Hermetic DIP
Transparent Window
O°C ~ TA ~ +70°C
AM2732DC
AM2732-6DC
3-16
Am97321Am2732
MAXIMUM RATINGS above which the useful life may be impaired
-65 to +125°e
Storage Temperature
Ambient Temperature Under Bias
+6 to -O.3V
Voltage on All Inputs/Outputs (Except OENPP) with Respect to GND
+26.5 to -O.3V
OENPP with Respect to GND
READ OPERATION
DC CHARACTERISTICS
ooe
~
TA
~
+7o oe, vee
=
+5V ±5%
Parameters
Description
Min
Test Conditions
Max
Units
J.l.A
III
Input Load Current
VIN = 5.25V
10
ILO
Output Leakage Current
VOUT = 5.25V
10
J.l.A
ICC1
VCC Current (Standby)
CE = VIH, OE = VIL
30
mA
ICC2
VCC Current (Active)
OE = CE = VIL
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 2.1mA
VOH
Output High Voltage
IOH = -400J.l.A
150
mA
-0.1
0.8
Volts
2.0
VCC+1
Volts
0.45
Volts
2.4
Volts
AC CHARACTERISTICS
ooe
~
TA
~
+ 7ooe, vee
Parameters
=
+5V ±5%
tACC
Address to Output Delay
tCE
CE to Output Delay
tOE
Output Enable to Output Delay
tDF
Output Enable High to
Output Float
tOH
Address to Output Hold
Am2732-6
Am2732
Min
Test Conditions
Description
Output Load: 1 TTL gate and CL = 100pF
Input Rise and Fall Times: ,.;;;20ns
Input Pulse Levels: 0.8 to 2.2V
Timing Measurement Reference Level:
Inputs: 1V and 2V
Outputs: 0.8V and 2V
Max
Min
Max Units
CE = OE = VIL
450
550
ns
OE = VIL
450
550
ns
CE = VIL
120
120
ns
100
ns
CE = VIL
0
CE = OE = VIL
0
100
0
ns
0
CAPACITANCE (Note 1)
TA = +25e, f = 1MHz
Parameters
Description
Typ
Max
Units
4
6
pF
VIN = OV
20
pF
VOUT = OV
12
pF
Test Conditions
CIN1
Input Capacitance (Except OEIVPP)
VIN = OV
CIN2
OENPP Input Capacitance
COUT
Output Capacitance
Note: 1. This parameter is only sampled and is not 100% tested.
3-17
Am97321~732
AC WAVEFORMS (Note 1)
-------------------ADDRESSES
VALID
ADDRESSES
'---------------------
'-------------I------ICE-----i
1 ' - - - - - - + -- - - - - -
_7"""'l~-'7'-r-r- - - - - - ----~......"""\
HIGH Z
OUTPUT
HIGH Z
----------------t-HH-t--+-<
-+-_______ ___
'-'a....J.........--a.......
~.4-L.J
MOS-492
Notes: 1. OE may be delayed up to 330ns after the falling edge of CE without impact on tACC.
2. tDF is specified from OE or CE, whichever occurs first.
3-18
Am9732/Am2732
PROGRAM OPERATION
DC PROGRAMMING CHARACTERISTICS
TA = +25°e ±5°e, vee = 5V ±5%, VPP = 25V ±1V
Parameters
Test Conditions
Description
III
Input Current (All Inputs)
VIN = VIL or VIH
VOL
Output Low Voltage During Verify
IOL = 2.1mA
VOH
Output High Voltage During Verify
IOH = -400p.A
ICC
VCC Supply Current
VIL
Input Low Level (All Inputs)
VIH
Input High Level (All Inputs Except OE/vPP)
IPP
VPP Supply Current
Min
Max
Units
10
p.A
0.45
Volts
Volts
2.4
150
mA
-0.1
0.8
Volts
2.0
VCC+1
Volts
30
mA
CE = VIL, OE = VPP
AC PROGRAMMING CHARACTERISTICS (Note 1)
TA = +25°e ±5°e, vee = 5V ±5%, VPP = 25V ±1V
Parameters
Test Conditions
Description
Min
Max
Units
tAS
Address Set-up Time
2
P.s
tOES
Output Enable Set-up Time
2
P.s
P.s
tDS
Data Set-up Time
2
tAH
Address Hold Time
0
P.s
tOEH
Output Enable Hold Time
2
P.s
Input tR and tF (10% to 90%) = 20ns
Input Signal Levels = 0.8 to 2.2V
Timing Measurement Reference Level:
Inputs: 1Vand 2V
Outputs: 0.8V and 2V
tDH
Data Hold Time
tDF
Chip Enable to Output Float Delay
tDV
Data Valid From CE (CE = VIL, OE = VIL)
2
P.s
0
120
ns
-
1
P.s
ms
tPW
Program Pulse Width
45
55
tPRT
Program Pulse Rise Time
50
-
ns
tVR
VPP Recovery Time
2
-
P.s
Note: 1. When programming the Am2732, a 0.1 p.F capacitor is required across OE/VPP and ground to suppress spurious voltage transients which may
damage the device.
PROGRAMMING WAVEFORMS
f----------
PROGRAM
---------1----
ADDRESS N
ADDRESSES
DATA----(
HIGHZ
DATA IN STABLE
ADD.N
tDV
OEivpp
tPRT
tAH-t---l
CEjPGM
MOS-493
3-19
Am9732/Am2732
ERASING THE Am2732
Enable (CE) is the power control and should be used for device
selection. Output Enable (OENPP) is the output control and
should be used to gate data to the output pins, independent of
device selection. Assuming that addresses are stable, address
access time (tACC) is equal to the delay from CE to output (tCE).
Data is available at the outputs 120ns (tOE) after the falling edge
of OE, assuming that CE has been low and addresses have been
stable for at least tACC - tOE.
In order to clear all locations of their programmed contents, it is
necessary to expose the Am2732 to an ultraviolet light source. A
dosage of 15 Wseconds/cm 2 is required to completely erase an
Am2732. This dosage can be obtained by eXRosure to an ultraviolet lamp [(wavelength of 2537 Angstroms (A)] with intensity
of 12000l1W/cm2 for 15 to 20 minutes. The Am2732 should be
about one inch from the source and all filters should be removed
from the UV light source prior to erasure.
STANDBY MODE
It is important to note that the Am2732, and similar devices, will
erase with light sources having wavelengths shorter than 4000
Angstroms. Although erasure times will be much longer than with
UV sources at 2537'&', nevertheless the exposure to fluorescent
light and sunlight will eventually erase the Am2732, and exposure
to them should be prevented to realize maximum system reliability. If used in such an environment, the package windows
should be covered by an opaque label or substance.
The Am2732 has a standby mode which reduces the active
power dissipation by 80%, from 787mWto 157mW. The Am2732
is placed in the standby mode by applying a TTL high signal to the
CE input. When in standby mode, the outputs are in a high
impedance state, independent of the OE input.
OUTPUT OR-TIEING
To accommodate multiple memory connections, a 2 line control
function is provided to allow for:
1. Low memory power dissipation
2. Assurance that output bus contention will not occur.
PROGRAMMING THE Am2732
Upon delivery, or after each erasure the Am2732 has all 32768
bits in the "1", or high state. "O"s are loaded into the Am2732
through the procedure of programming.
The programming mode is entered when +25V is applied to the
OENPP pin. A 0.1p.F capaCitor must be placed across OENPP
and ground to suppress spurious voltage transients which may
damage the device. The address to be programmed is applied to
the proper address pins. 8-bit patterns are placed on the respective data output pins. The voltage levels should be standard TTL .
levels. When both the address and data are stable, a 50msec,
TTL low level pulse is applied to the CE/PGM input to accomplish
the programming.
The procedure can be done manually, address by address, randomly, or automatically via the proper circuitry. All that is required
is that one 50msec program pulse be applied at each address to
be programmed. It is necessary that this program pulse width not
exceed 55msec. Therefore, applying a DC low level to the CEI
PGM input is prohibited when programming.
It is recommended that CE be decoded and used as the primary
device selecting function, while OE be made a common connection to all devices in the array and connected to the READ line
from the system control bus. This assures that all deselected
memory devices are in their low-power standby mode and that
the output pins are only active when data is desired from a
particular memory device.
PROGRAM INHIBIT
Programming of multiple Am2732s in parallel with different data is
also easily accomplished. Except for CE/PGM, all like inputs
(including OE) of the parallel Am2732s may be common. A TTL
level program pulse applied to an Am2732's CE/PGM input with
VPP at 25V will program that Am2732. A high level CE/PGM input
inhibits the other Am2732 from being programmed.
PROGRAM VERIFY
A verify should be performed on the programmed bits to determine that they were correctly programmed. The verify must be
performed with OENPP and CE at VIL. Data should be verified
tDV after the falling edge of CEo
READ MODE
The Am2732 has two control functions, both of which must be
logically satisfied in order to obtain data at the outputs. Chip
3-20
Read-Only Memories
NUMERICAL INDEX
Mask Programmed
Am3514
Am9208
Am9214
Am9216
Am9217/8316A
Am9218/8316E
Am9232
Am9233
Page
512 x 8 .................................................................. 4-5
1024 x 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .. 4-1
512 x 8 .................................................................. 4-5
2048 x 8 ................ "................................................. 4-11
2048 x 8 ................................................................. 4-15
2048 x 8 ................................................................. 4-18
4096 x 8 ................................................................. 4-21
4096 x 8 ................................................................. 4-21
Am9208
1024 x 8 Read Only Memory
FUNCTIONAL DESCRIPTION
The Am9208 devices are high performance, 8192 bit, static,
mask programmed, read only memories. Each memory is
implemented as 1024 words by 8 bits per word. This organization simplifies the design of small memory systems and
permits incremental memory sizes as small as 1024 words.
The fast- access times provided allow the ROM to service high
performance microcomputer applications without stalling the
processor.
DISTINCTIVE CHARACTERISTICS
•
•
•
•
•
•
•
•
•
o
•
1024 x 8 organization
High speed - 400ns access time
Fully capacitive inputs - simplified driving
2 fully programmable chip selects- increased flexibility
Logic voltage levels compatible to TTL
Three-state output buffers - simplified expansion
Standard supply voltages - +12V, +5.0V
No Vss supply required
N-channel silicon gate MaS technology
100% MIL-STD-883 reliability assurance testing
Direct plug-in replacement for Intel 8308/2308 and T.!. 4700
Two Chip Select input signals are logically ANDed together
to provide control of the output buffers. Each Chip Select
polarity may be specified by the customer thus allowing the
addressing of 4 memory chips without external gating. The
outputs of unselected chips are turned off and assume a high
impedance state. This permits wire-O Ring with additional
Am9208 devices and other three-state components_
These memories are fully static and require no clock signals of
any kind. A selected chip will output data from a location
specified by whatever address is present on the address input
lines. The Am9208 is pin compatible with the Am9216 which
is a 16k-bit mask programmed ROM. Input and output voltage
levels are compatible to TTL specifications, providing simplified
interfacing.
CONNECTION DIAGRAM
Top View
BLOCK DIAGRAM
Ag
ADDRESS 7
Vcc(+SVI
AS
A7
A6
STORAGE
ARRAY
64 X '28
ADDRESS 6
ADDRESS S
ADDRESS 5
ADDRESS 9
AS
ADDRESS 4
NC
ADDRESS J
Cs,/Cs,
ADDRESS 2
V D D(+'2VI
A4
AJ
ADDRESS'
A2
A,
ADDRESS 0
OUPTUT S
CS 2/Cs 2
AO
CS,
CS 2
OUTPUT'
OUTPUT 7
OUTPUT 2
OUTPUT 6
OUTPUT J
OUTPUT 5
(GNDIVss
OUTPUT 4
Note: Pin 1 is marked for orientation.
MOS-379
MOS-376
ORDERING INFORMATION
Package Type
Hermetic DIP
Plastic DIP
Ambient Temperature
Specification
Access
Tim~
400ns
ooe
~
TA
~
70°C
AM9208BDe
-55°C
~
TA
~
+125°e
AM9208BDM
ooe
~
TA
~
70°C
AM9208BPe
4-1
Am9208
MAXIMUM RATINGS (Above which
the useful life may be impaired)
Storage Temperature
Ambient Temperature Under Bias
VDD with Respect to Vss
15V
Vee with Respect to Vss
+7.0V
DC Voltage Applied to Outputs
-O.5V to +7.0V
DC Input Voltage
-O.5V to +7.0V
Power Dissipation
1.0W
The products described by this specification include internal circuitry designed to protect input devices from damaging accumulations of
static charge. It is suggested nevertheless, that conventional precautions be observed during storage, handling and use in order to avoid
exposure to excessive voltages.
OPERATING RANGE
Part Number
Ambient Temperature
Vss
Vee
Voo
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Parameters
VOH
Description
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
ILO
Output Leakage Current
III
Input Leakage Current
Test Conditions
3.7
3.7
IOH = -4.0 rnA
2.4
2.4
VCC Supply. Current
Volts
0.4
Volt~
VCC+ 1.0
2.6
VCC+ 1.0
Volts
-0.5
O.B
-0.5
0.4
O.B
Volts
10
10
J.LA
10
10
J.LA
Arn920BB/e
35
43
Arn920BD
44
50
Arn920BB/C
4B
53
Arn920BD
55
61
Arn920BB/C
13
15
Arn920BD
15
17
Chip disable
VDD Supply Current
Units
2.4
IOL = 3.2 rnA
Deselected
ICC
Am9208DM
Max.
Min
IOH = -1.0rnA
Selected
IDD
Am9208DC/PC
Min
Max
rnA
rnA
Am9208BDM/Am9208BDCI
Am9208BPC
Parameters
Description
ta
Address to Output Access Time
tco
Chip Select to Output ON Delay
tOH
Previous Read Data Valid with
Respect to Address Change
tOF
Chip Select to Output OFF Delay
CI
Input Capacitance
Co
Output Capacitance
Test Conditions
tr = tf = 20ns
Output load:
one standard
TTL gate
plus 100pF
(Note 1)
Min
Max
Units
400
ns
160
ns
ns
20
TA = 25°C, f = 1MHz
All pins at OV
120
ns
6.0
pF
6.0
pF
Notes: 1. Timing reference levels - Inputs: High = 2.0V, Low = 1.0V. Outputs: High = 2.4V, Low = 0.8V
SWITCHING WAVEFORMS
MOS-380
4-2
Am9208
TYPICAL CHARACTERISTICS
100, Icc Vers~s
Temperature (Normalized)
A Output Capacitance
Versus A Output Delay
20
1.4
VCC =5.5V
1.31- Voo = 13.2V
53N
1.2
:J
1.1"
<{
~
a
z
I
0
_0
1.0
0.9
"I
I
151-- VCC =4.5V
Voo= 10.BV
10
>-
r--- 1'-0...
f"- 1"-.....
O.B
~
irf-
-5
a
-10
.,...V"
::J
....... 1'-.
U
_u 0.7
-/ ~C.- f - - -
0
f-
. . . . t'-..
"
-4.0
\?-
.~
r-p.
~r-I-.
-2.0
0~~~1....-~1....-~--I--I--I
o
0.2
-
T'
~ -10 I--+--+--+-.j--.:":..t---+--f-----l
-12
"
~I--""
~
~u
V cc =4.5V
Voo= 10.BV-
_1'1
-16
-14 f - - TYPleAL~t-TA = 70°C
0.4
0.6
VOL -VOLTS
O.B
1.0
0L-~~-J-~~~~~
2.4
2.B
3.2
3.6
4.0
V OH - VOLTS
MOS-381
PROGRAMMING INSTRUCTIONS
CUSTOM PATTERN ORDERING INFORMATION
The Am9208 is programmed from punched cards, card coding forms or from paper tape in card image form in the format as shown
below.
Logic "1"
Logic "0"
a more positive voltage (normally +5.0 V)
a more negative voltage (normally OV)
FIRST CARD
Column Number
10 thru 29
32 thru 37
50 thru 62
65 thru 72
Description
Customer Name
Total number of "1 's" contained in the data.
This is optional and should be left blank if not used.
9208B
Data
SECOND CARD
Column Number
31
33
Description
CS2 input required to select chip (0 or 1)
CSl input required to select chip (0 or 1)
Two options are provided for entering the data pattern with the remaining cards.
OPTION 1 is the Binary Option where the address and data are presented in binary form on the basis of one word per card. With
this option 1024 data cards are required.
Column Number
10,12,14,16,18
20,22,24,26,28
Address input pattern with the most significant bit (Ag) in column 10 and the least significant bit (AD)
in column 28.
40, 42, 44, 46, 48,
50,52,54
Output pattern with the most significant bit (Oa) in column 40 and the least significant bit (0 1 ) in
column 54.
73 thru 80
Coding these columns is not essential and may be used for card identification purposes.
4-3
Am9208
OPTION 2 is the Hexadecimal Option and is a much more compact way of presenting the data. This format requires only 64 data
cards. Each data card contains the 8-bit output information for 16 storage locations in the memory. The address indicated
in columns 21, 22 and 23 is the address of the data presented in columns 30 and 31. Addresses for successive data are assumed to
be in incremental ascending order from the initial address. Since the address in columns 21, 22 and 23 always points only to the
first data on the card, column 23 is always zero. Columns 21 and 22 take all hex values from 00 through 3F: 64 cards in all. Data
is entered in hex values and may be any combination of 8 bits, that is, hex values from 00 through FF.
A
0
0
R
121122123
OUTPUT VALUES FOR ADDR +
0
1
2
3
4
5
6
7
'
8
9
A
B
C
0
E
F
30131 32 33 134 35 36137 3839140 4142143 44 45146 47 48149 50 51152 53 54155 56 57158 5960161 62 63164 6566167 68 69170 71 72173 74 75176
~
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4-4
Am9214/Am3514
512 x 8 Read Only Memory
FUNCTIONAL DESCRIPTION
DISTI NCTIVE CHARACTER ISTICS
The Am9214/Am3514 devices are high performance; 4096-bit,
static, read only memories. Each memory is implemented as
512 words by 8 bits per word. This organization simplifies
the design of small memory systems and permits incremental
memory sizes as small as 512 words.
•
Single 5-volt power supply
Tolerances: ±5% commercial, ±10% military
•
•
•
•
•
•
•
•
•
•
512 x 8 organization
Fully static operation - no clocks
4 programmable chip selects
High-speed - 500 ns access
Three-state output buffers
Low power dissipation - 263 mW max.
Logic voltage levels identical to TTL
High noise immunity - full 400mV
N-Channel silicon gate MOS technology
Military and commercial temperature ranges available
•
•
100% MIL-STD-883 reliability assurance testing
Directly plug~in compatible with FSC 3514, MOSTEK 2600
Four Chip Select input signals are logically AN Ded together
to provide control of the output buffers. Each Chip Select
polarity may be specified by the customer thus allowing the
addressing of up to 16 memories without external gating. The
outputs of unselected chips are turned off and assume a high
impedance state. This permits wire-ORing with additional
Am9214 devices and other three-state components.
These memories are fully static and require no clock signals of
any kind. A selected chip will output data from a location
specified by whatever address is present on the address input
lines. Input and output voltage levels are identical to TTL
specifications, providing simplified interfacing and standard
worst-case noise immunity of 400mV. Only a single supply of
+5 volts is required for power.
CONNECTION DIAGRAM
Top View
BLOCK DIAGRAM
Aa
Al
A2
A3
N.C.
STORAGE
ARRAY
ROW
DECODER
64x64
A4
A5
AS
A7
AS
VCC (+5V)
CHIP SELECT 2
CHIP SELECT 1
CHIP SELECT 3
CHIP SELECT a
OUTPUT a
ADDRESS 0
OUTPUT 1
ADDRESS 1
OUTPUT 2
ADDRESS 2
OUTPUT 3
ADDRESS 3
OUTPUT 4
ADDRESS 4
OUTPUT 5
ADDRESS 5
OUTPUT 6
ADDRESS 6
OUTPUT 7
ADDRESS 7
(GND) Vss
ADDRESS S
CSa
CSI
CS2
CS3
Note: Pin 1 is marked for orientation.
MOS-383
UOS-382
ORDERING INFORMATION
Package
Type
Ambient Temperature
Specification
O°C
~
TA
~
+70°C
Hermetic DIP
-55°C
~
TA
~
Access Time
1000ns
700ns
500ns
AM35142CC
AM35141CC
AM9214CC
AM35142DC
AM35141DC
AM9214DC
AM9214CM
+125°C
AM9214DM
4-5
Am92141Am3514
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
Supply Voltage to Ground Potential (Pin 10 to Pin 9) Continuous
-O.5V to +7.0V
DC Voltage Applied to Outputs
DC Input Voltage
-O.5V to +7.0V
-O.5V to +7.0V
Power Dissipation
1.0W
The products described by this specification include internal circuitry designed to protect input devices from excessive accumulations of
static charge. It is suggested nevertheless, that conventional precautions be observed during storage, handling and use in order to avoid
exposure to any voltages that exceed the maximum ratings.
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
o
T A = ooc to +70 C
Am9214DC
Am35141DC
Am35142DC
Parameters
Vec = +5V ±5%
Am3514
Am9214
Description
Test Conditions
VOH
Output HIGH Voltage
VCC = 4.75V, IOH = 500}.lA
VOL
Output LOW Voltage
VCC = 4.75V, IOL = 2.4rnA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
(See Note 1)
III
Input Load Current
VCC = 5.25V, OV
ILO
Output Leakage Current
Min.
2.4
Max.
Min.
Max.
Units
Vce
2.4
VCC
Volts
0.4
Volts
0.4
2.0
VCC
VCC- 2 . 75
VCC
Volts
-0.5
0.8
-0.5
0.55
Volts
5.25V
1.0
1.0
}.IA
Output OFF, VOUT = 0.4 to VCC
1.0
1.0
}.IA
50
50
rnA
~
VIN
~
Data Out Open
ICC
Power Supply Current
VCC
= 5.25V
VIN = VCC
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Vce = +5V ± 10%
Am9214DM
Parameters
Description
Am9214
Test Conditions
VOH
Output HIGH Voltage
VCC = 4.5V, IOH = 500}.lA
VOL
Output LOW Voltage
VCC= 4.5V, IOL = 2.4 rnA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
(See Note 1)
III
Input Load Current
VCC
ILO
Output Leakage Current
Output OFF, VOUT
ICC
Power Supply Current
Data Out Open
VCC = 5.5V
VIN = VCC
= 5.5V, OV
~
VIN ~ 5.5V
= 0.4 to VCC
Min.
Max.
Units
2.2
VCC
Volts
0.4
Volts
2.0
VCC
Volts
-0.5
0.8
Volts
10
}.I A
10
}.IA
70
rnA
Notes: 1. Input Logic levels that swing more negative than -0.5 volts will be subject to clamping currents attempting to keep the input from falling.
4-6
Am9214/Am3514
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Output Load: 1.5 TTL Gate +100pF for Am9214, 1.5 TTLGate only for Am3514
Transition Times: 10ns
Input Levels: O.8V and 2.0V
Output Reference: 1.5V
Parameter
Description
Am9214
Min;
Test Conditions
Max.
Am35141
Min.
Max.
Am35142
Min.
Max.
Units
tc
Cycle Time
tA
Access Time
500
700
1000
ns
tco
Chip Select to Output On Delay
200
500
900
ns
tOH
Previous Read Data Valid with
Respect to Address Change
CI
Input Capacitance
6.0
8.0
8.0
pF
Co
Output Capacitance
10
12
12
pF
500
ns
50
ns
TIMING DIAGRAM
1-I'-----tc-----...-j·1
ADDRESSES
)Kr---------"\~
_ _ _ _..oJ
CHIP
SELECTS
DATA
OUT
_____
D_IS_AB_L_ED____
I
I
~I_______J~~
~----
I_____________
_ _ _ _ _ _ _ _ _ _ _ EN_A_BL_E_D
_
______________
I--"l
~''"-
----------------------------~~-~-~-~~~
I
--tA----I1
r---I.
MOS-384
Unselected chips will have high impedance outputs. Active
level definition for each of the four chip Select inputs may be
either high or· low and is programmed along with the data
pattern.
GLOSSARY OF TERMS
Cycle Time - Specifies the maximum rate at which new read
operations may be initiated, and thus the minimum time
between successive address changes.
Access Time - Maximum delay from the arrival of the last
stable address line to valid output data on a selected chip.
Output Hold Time (tOH) - Minimum delay which will elapse
between a change of the input address and any consequent
change in the output data.
Output Enable Time (teo) - Maximum delay from the arrival
of four active Chip Select signals to enabled output data.
4-7
Am9214/Am3S14
PROGRAMMING INSTRUCTIONS
CUSTOM PATTERN ORDERING INFORMATION
The Am9214 (or Am3514) is programmed on IBM cards, IBM coding form, or on paper tape in card image form in the format as
shown below.
Logic "1"
Logic "0"
a more positive voltage (normally +5.0V)
a more negative voltage (normally OV)
FIRST CARD
Column Number
10 thru 29
32 thru 37
50 thru 62
65 thru 72
Description
Customer Name
Total number of "1 's" contained in the data.
This is optional and should be left blank if not used.
9214 or 35141 or 35142
Date
SECOND CARD
Column Number
29
31
33
35
Description
CS3 input required
CS2 input required
CS1 input required
CSa input required
(0
to
to
to
or 1) to select chip.
select chip.
select chip.
select chip.
Two options are provided for entering the data pattern with the remaining cards.
OPTION 1 is the Binary Option where the address and data are presented in Binary form on a one-word-per-card basis. With this
option, 512 more cards are required:
Column Number
10,12, 14, 16, 18
20,22,24,26
Address input pattern, the most significant bit (As) is in column 10.
40, 42, 44, 46, 48,
50,52,54
Output pattern, the most significant bit (0 7 ) is in column 40.
73 thru 80
Coding these columns is not essential and may be used for card identification purposes.
OPTION 2 is the Hexadecimal Option and is a much more compact way of presenting the data. This format requires only 32
data cards (see chart).
Each data card contains the 8-bit output information for 16 storage locations in the memory. The address indicated in columns
21, 22 and 23 is the address of the data presented in columns 30 and 31. Addresses for successive data are assumed to be in
incremental ascending order from the initial address. Since the address in columns 21,22 and 23 always points only to the first
data on the card, column 23 is always zero. Columns 21 and 22 take all hex values from 00 through 1 F: 32 cards in all. Data is
also entered in hex values and may be any combination of 8 bits, that is, hex value from 00 through F F.
4-8
Am9214/Am3S14
A
D
D
R
~
OUTPUT VALUES FOR ADDR +
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
30\31 3233\34 35 36\37 38 39\40 4142\43 44 45146 47 48149 50 51\52 5354\55 56 57\58 59 60\61 62 63\64 6566\67 68 69170 71 72173 74 75176
~
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4-9
Am9214/Am3514
Am9214 PER FORMANCE CURVES
Typical Power Supply Current
Versus Voltage
Typical Output Current
Versus Voltage
TA = 25'C
INPUTS = 5.0V
1 and q,2" Data entering the
register on ¢, ,wtll ,appear at the output on <1>1 (from the
negative edge ,0(<1>1 tQ the negative edge of <1>21.
M05-396
Am1402A/Am2802
ORDERING INFORMATION
Standard
Speed Range
Order Number
Extended
Speed Range
Order Number
Part Number
Package Type
Temperature
Range
Am1402A/
2802
Hermetic DIP
Hermetic DIP
Molded DIP
O°C to +70°C
-55°C to+125°C
O°C to +70°C
AM1402A
AMl402ADM
AM 1402APC
AM2802DC
AM2802DM
AM2802PC
Am1403A/
2803
TO-99
TO-99
Molded DIP
O°C to +70°C
-55°C to +125°C
O°C to +70°C
AM1403A
AM.14Q3AHM
AM1403APC
AM2803HC
AM2803HM
AM2803PC
Am1404A/
2804
TO-99
TO-99
Mini DIP Plastic
O°C to +70°C
_55°C to +125°C
O°C to +70°C
. AM1404A
. AM1404AHM
AM1404APC
AM2804HC
AM2804HM
AM2804PC
5-7
Am1402A/03A/04A· Am2802l03/04
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature
Temperature Under Bias
Power Dissipation
600mW
(Note 1)
Data and Clock Input Voltages with respect to most Positive Supply Voltage, Vee
0.3Vto -20V
Power Supply Voltage, VDD with respect to Vee
0.3 Vto -20 V
OPERATING RANGE
Part Number
Temperature Range
Vcc
VDD
Am1402A, Am1403A, Am1404A
5V ±5%
-4.75V to -9.45V
O°C to +70°C
Am1402ADM, Am1403AHM, Am1404AHM
5V ±5%
-4. 75V to -9.45V
Am2802DC, Am2803HC, Am2804HC
5V ±5%
-5V ±5%
_55°C to +125°C
o
O°C to +70 C
Am2802DM, Am2803HM, Am2804HM
5V ±5%
-5V ±5%
_55°C to +125°C
ELECTRICAL CHARACTERISTICS over operating range
Am1402A, 3A, 4A
Parameters
Description
Test Conditions
Min.
V IH
Input HIGH Voltage
Vee-2 .O
VIL
Input LOW Voltage
Vce- 1O
II
I nput Current
10
Iet>L
VCC-4·2
Units
V
VCC-10
VCC-4.2
V
500
nA
Output Leakage Current
T A = 25°C, VOUT = OV
<10
1000
<10
1000
nA
Clock Leakage Current
TA = 25°C, Vet> = -12V
10
1000
10
1000
nA
D~iving
TTL,
Output HIGH Voltage Driving MOS
R,L = 3k to VOO,
VOO = -5V ±5%
RL = 4,7k to VOO,
VOO = -5V ±5%
2.4
3.5
VCC-l.9
VCC-l
VCC-l.9
VCC-l
VCC-l.9
VCC-l
2.4
3,5
VCC-l.9
VCC-l
V
RL = 4.7k to VOO,
VOO = -9V ±5%
RL = 6.2k to VOO, 3.9k to Vce
VOO = -9V ±5%
VOO = -5V±5%,
RL,= 3k to VOO, IOL = -1.6rnA
-0.3
0.5
-0.3
0.5
-0.3
0.5
V
Output LOW Voltage
RL = 4.7k to VOO
VOO =-9V ±5%,IOL = -1.6rnA
Vet>H
Clock Input HIGH Level
Vet>L
Clock I nput LOW Level
VOO = -5V ±5%
VOO = -9V ±5%
VOO Current, VOO = -5 V ±5%
VOO Current, VOO = -9V ±5%
VCC-l
VCC+0.3
VCC-l
VCC+0.3
Vce- 15
Vee- 17
VCC-15
Vce- 17
VCC-14.7
VCC-12.6
VCC-12.6
5 MHz Data Rate
TA = 25°C
33% Duty eyc'le
TA = O°C
Vet>L = VCC-17V
TA = _55°e
VOO Current, VOO = -5V ±5%
(Note 1)
Max.
<10
Output HIGH Voltage Driving TTL
100(-9)
Typ.
Vee-2 .O
500
Output HIGH Voltage Driving MOS
(Note 1)
Min.
<10
VOH
100(-5)
Am2802, 3, 4
Max.
TA=25°C
Output HIGH Voltage
VOL
Typ.
40
50
V
V
VCC-14.7
40
50
56
56
rnA
70
50
60
10MHz Data Rate
TA = 25°C
40% Duty Cycle
TA = O°C
68
Vet>L = VCC-17
TA =_55°C
80
3MHz Data Rate
TA = 25°C
26% Duty Cycle
TA = O°C
Vet>L = VCC-14.7V
TA = _55°C
30
40
45
30
rnA
40
45
rnA
60
Note: 1. Power dissipation is directly proportional to clock duty cycle and independent of frequency. The duty cycle is the clock LOW time (one cia.
line) divided by the clock period. At VDD = -9V the maximum duty cycle is 26%. The duty cycle should be kept as small as possible to minimi
power dissipation.
5-8
Am1402A103A104A • Am2802/03/04
SWITCHING CHARACTERISTICS AND OPERATING CONDITIONS
(Over Operating Range)
Am1402A! Am1403A! Am1404A
Parameter
Voo
Description
Test Conditions
Min.
=-5 V :!:5%
(Tesl Load 1)
Typ.
Max.
Voo
=-9 V :!:5%
(Tesl Load 2)
Min.
Typ.
Max.
Units
fc
Clock Frequency Range
(Note 1)
2.5
(Note 1)
1.5
MHz
fd
Data Repetition Rate
(Note 1)
5.0
(Note 1)
3.0
MHz
trpPW
Clock Pulse Width
0.13
10
0.17
10
J.LS
t¢d
Clock Pulse Delay (Note 2)
10
(Note 2)
10
(Note 2)
ns
tf, tr
ts
Clock Pulse Rise/Fall Time
1000
ns
Data Set Up Time
tr - tf .;; 50 ns
th
Data Hold Time
tr
= tf .;;
t¢pw
= 130 ns
1000
50 ns
30
60
ns
20
20
ns
90
110
tpd +, tpd-
Clock to Data Out Delay
CIN*
Input Capacitance
@
1 MHz, 250 mVPP
5
10
5
10
pF
COUT*
C¢*
Output Capacitance
@
1 MHz, 250 mVPP
5
10
5
10
pF
Clock Capacitance
@
1 MHz, 250 mVPP
110
140
110
140
pF
SWITCHING CHARACTERISTICS AND OPERATING CONDITIONS
Am2802! Am2803! Am2804
Parameter
(Over Operating Range)
voo
Clock Pulse Width = 70nsec
Clock LOW Level = (VCc-15)
Description
Min.
Test Conditions
= tf = 10 ns
(Note 1)
Clock Frequency Range
fd
Data Repetition Rate (Note 1)
t¢pw
Clock Pulse Width
t¢d
Clock Pulse Delay
tf, tr
Clock Pulse Rise/Fall Time
ts
Data Set Up Time
30
th
Data Hold Time
20
tpd+. tpd-
Clock to Data Out Delay
(Note 3)
t¢pw
= -5 V :!:5%
(Tesl Load 1)
fc
tr
ns
= 70 ns
Typ.
Max.
5.0 (Note 4)
10.0 (Note 4)
Units
MHz
MHz
0.07
10
J.LS
10
(Note 2)
ns
1000
ns
ns
ns
90
ns
Notes:
1. See minimum operating frequency graph for low limits on data rep. rate.
2. Upper limit on t¢d is determined by minimum frequency.
3. See max clock pulse delay graph for guarantee.
4. For additional information on 10MHz operation (5MHz clock rate) see AMD application note dated July 1973 on "Applications of Dynamic
Shift Registers."
DESCRIPTION OF TERMS
OPERATIONAL TERMS
VOH Minimum logic HIGH output voltage with output HIGH current
IOH flowing out of output.
SWITCHING TERMS
I¢d The delay between the LOW to HIGH transition of a clock
phase to the HIGH to LOW transition of the other clock phase.
I¢pw The clock pulse widths necessary for correct operation.
Ma.ximum logic LOW output voltage with output LOW current
into junction of output and load resistor.
'IH Logic HIGH input voltage.
'lL
Logic LOW input voltage.
10L
Clock LOW input voltage.
'OH Clock HIGH input voltage.
Input leakage current.
o Output leakage current.
)0
Power supply current.
'IN Input capacitance.
~¢
Input clock capacitance.
:OUT Output capacitance.
1f0L
'OL
If. Ir The clock pulse rise and fa" times necessary for correct operation.
Is The time required for the input data to be present prior to the
LOW to HIGH transition of the clock phase to ensure correct operation.
Ih The time required for the input data to remain present after the
LOW to HIGH transition of the clock phase to ensure correct operation.
I pd + The propagation delay from the HIGH to LOW clock phase ¢I
transition to the output LOW to HIGH transition.
I pd _ The propagation delay from the HIGH to LOW clock phase ¢2
transition to the output HIGH to LOW transition.
'UNCTIONAL TERMS
I' ¢2
The two clock phases required by the dynamic shift register.
: The clock frequency of the shift register.
I
The input data repetition rate.
5-9
Am1402A/03A/04A • Am2802/03/04
SWITCHING WAVEFORMS
BIT 2
BIT 1
BITN
BIT N + 1 ..
BIT N + 2
BIT 1
BIT 2
~-------------------+5V
10%
+5V
10%
t¢2
CLOCK
90%
90%
-I,
-'"I r,_+-om,,,,
----10V
I
IN BIT 1
+
~
i
-OA-T-A-IN--O
r --------------;-------------
'--IN--BI-T-2------------------------------------------
tpd+ -
f,:=
f,:=
-OA-T-A-O-U-T------------------------------------------------------------1-.5-V""*
1.5V
5V
OV
tpd-
*'-_____ :::,
OUT BIT 1
OUT BIT 2
Clock Rise TIme 10 ns
Clock Fall Time 10 ns
Output Load 1 TTL Load
Test Load 1
Test Load 2
3k
4.7k
1.105-398
CIRCUIT DIAGRAM
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
BIT2
IL ________________
Vee
Vee
_
1.105-399
5-10
Am1402A103A104A· Am2802l03l04
POWER CHARACTERISTICS
Minimum Operating Data Rate
or Maximum Clock Pulse Delay
Versus Temperature
(For Small Duty Cycles)
10- 4
10k
IOH Versus VOH
~
40
VCC = +4.75
VDD' -4.75
VI LC = -10.25
I
Cl
10- 3 :Y
1k
>-
:t
I
w
100
10- 2
l-
-
VS~I = !5bv
1k
CHANGING,
STATE
UNKNOWN
!
I
=
DON'T CARE;
ANY CHANGE
PERMITTED
200
125°C
I- VGG
WILL BE
CHANGING
FROM L TO H
l...-
v
II
MAY CHANGE
FROM L TO H
Typical Propagation Delay
Versus Ambient Temperature
I
f-
OUTPUTS
CHARACTERISTIC CURVES
Typical Power-Supply
Currents Versus Frequency
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
INPUTS
I- 1!
5
~- I -
VSS = +5.0V
VGG = -12.0V
I
25 45
65 85 105125
AMBIENT TEMPERATURE -"C
DEFINITION OF TERMS
MOS-408
SET-UP and HOLD TIMES The shift register will accept the data
that is present on its input around the time the clock goes from
LOW-to-HIGH. Because of variations in ind.ividual devices, there
is some uncertainty as to exactly when, relative to this clock
transition, the data will be stored. The set-up and hold times
define the limits on this uncertainty. To guarantee storing the
correct data, the data inputs should not be changed between
the maximum set-up time before the clock transition and the
maximum hold time after the clock transition_ Data changes
within this interval mayor may not be detected.
nATIC SHI FT REGISTER A shift register that is capable of
naintaining stored data without being continuously clocked.
1I10st static shift registers are constructed with cjynamic master
Ind static slave flip-flops. The data is stored dynamically while
he clock is LOW and is transferred to the static slaves while the
:Iock is HIGH. The clock may be stopped indefinitely in the
-1IGH state, but there are limitations on the time it may reside
n the LOW state_
5-21
Am2809
APPLICATIONS
128-Word x 8-Bit Pseudo-Random Access Memory
Data stored in the four dual 128-bit shift registers can be accessed randomly by 'Comparing the desired aqdress with the
address currently available at the shift register 1/0_ A pair of Am93L16 low-power counters keeps track of data addresses
as the data circulates around the memory_ Other Am93L 16 counters are used as 4-bit registers with enables by grounding
the count enables_ They are used to store the requested address, the new data to be written into the memory, and the data
read from the memory_ The Am93L24 comparators switch the memories from the recirculate mode to the write mode to
enter new data in a write operation. Similarly, the output storage registers are enabled when the Am93L24s indicate
comparison in a read operation.
M05-409
Metallization and Pad Layout
IN B
7
OUT B
6
5 CP
VCC B
. RC
1
IN A 2
3 4
OUT A VGG
86 X 95 Mils
5-22
Am2810
Dual 128-Bit Static Shift Register
Distinctive Characteristics
• 100% reliability assurance testing in compliance with
MI L-STD-883
• Operation guaranteed from DC to 2 MHz
• 2 nd Source to Mostek 1002P
• Built-in pull-up resistors
LOGIC SYMBOL
FUNCTIONAL DESCRIPTION
The Am2810 is a dual 128-bit static shift register built using P-channel
silicon gate MOS technology_ The two registers each have a two-input
multiplexer on their inputs, so that input data may be selected from
one of two sources_ Each register has a separate clock input, and
operates with a low-voltage TTL clock signal. The registers shift on the
LOW-to-H IG H edge of the clock signal. Data at the inputs must be
steady for a set-up time before and a hold time after this clock transition. Since data storage is static, the clock may be halted indefinitely
in the HIGH state. The outputs of each register can drive one TTL load
or three Am93L low-power TTL loads_
13
RC
14
RIN
15
DIN
Am2810
128-61T SHIFT REGISTER
18)
OUT
12
CP
The two-input multiplexer on the input of each register is controlled by
the RC (recirculate control) input. When RC is LOW, data is accepted
on the Rin input; when RC is HIGH, data is accepted on the Din input.
The inputs to the registers have built-in pull-up resistors to provide total
TTL compatibility. The VRA pin controls the pull-up resistors for
register A Din and RC inputs. The VRB pin controls the pull-up resistors
for the register B Din and RC inputs. The VRct> pin controls the resistor
on the clock input to both registers. When the resistor control pins are
tied to VGG (-12V), the resistors are enabled and pull the inputs they
affect up to VSS. When the resistor control pins are tied to VSS the
resistors are all very high impedance and the inputs they affect all
exhibit normal MOS characteristics. The Rin inputs are intended to be
the ~'recirculate inputs from an MOS output ant:! these inputs do not
have pull-up resistors associated with them.
RC
DIN
Am2810
128-81T SHIFT REGISTER
OUT
(A)
CP
V RA = Pin 16
Vss = Pin 7
V OD = Pin 6
VGG = Pin 11
=Pin1
VRct> = Pin 10
V
RB
MOS-410
LOGIC BLOCK DIAGRAM (One Register Shown)
VSS
va - - - - - - l - - '
DIN---_--+---r~
RC----~-~~_J
Am2810
128-61T
SHIFT REGISTER
OUT
OUT
RIN -------~_J
CLOCK - - - - - . , . . - - - - - - - - - '
TO OTHER REGISTER
CP INPUT
MOS-411
ORDERING INFORMATION
CONNECTION DIAGRAMS
V R6
DIN B
Package
Type
Molded DIP
Hermetic DIP
Hermetic DIP
Temperature
Range
O°C to +7SoC
O°C to +7SoC
-SSoC to +12SoC
On."
Numbel
AM2810PC
AM2810DC
AM2810Df,'
V RA
DINA
RIN B
RIN A
ACB
RCA
OUT B
voo
OUTA
VGG
Vss
VR~
CP B
CPA
Note: Pin 1 is marked for orientation.
5-23
MOS-412
Am281 0
MAXIMUM RATING (Above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
VDD Supply Voltage
VSS -10V to VSS +O.3V
VGG Supply Voltage
VSS -20V to VSS +O.3V
DC Input Voltage
VSS -10V to VSS +O.3V
OPERATING RANGE
Vss
Voo
O°C to +75°C
5.0V ±5%
OV
-12.0V ±5%
_55° C to + 125° C
5.0V ±5%
OV
-12.0V ±5%
Part Number
Am2810XC
Am1002P
Am1002L
Am2810XM
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless otherwise noted)
Typ.
Parameters
Description
Test Conditions
Min.
= -100.uA
IOL = 1.6mA
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Level
Guaranteed input logical HIGH
voltage for all inputs
VIL
Input LOW Level
Guaranteed input logical LOW
voltage for all inputs
IlL
(Note 2)
Resistors Disabled
Input LOW Current
IIL(n)
(Note 2)
Resistors Enabled
Input LOW Current
VSS = MAX., VIN = OV
VRA = VRB = VR = VSS
VSS = MAX., VIN = O.4V, Am2810/Am1002P only
VRA = VRB = VR¢ '" VGG
11L = VIN = VSS
14
25
-4
-10
35
-55°C to +125°C
I nputs and Outputs Open
Units
Volts
O°C to +75°C
f
Max.
(Note 1)
O°C to +75°C
mA
-15
_55° C to +125° C
Notes: 1. Typical Limits are at VSS = 5.0V, VGG = -12V, 25°C ambient and maximum loading.
2. On chip ·pull-up resistors are provided for the clock and data inputs; they are enabled when the appropriate V R input is at -12V. When the V f
inputs are at VSS ' the resistors are disabled and the inputs exhibit normal MOS characteristics (II L and II H)' the recircu late data inputs have n.
pull·up resistors and always exhibit MOS characteristics. All pull-up resistors are disabled on the Am 1 002L except the one on the clock.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Parameters
Description
Test Conditions
Am2810
Min.
Typ. Max.
Am1002P/
Am1002L
Min. Typ. Max.
Units
MHz
f max
Maximum Clock Frequency
2.0
t¢pwH
t-
Q
1 L
H25 0C
10k
~
I
-
= OV
= -12.0 V
0 - - - +5.0V
INPUT
PATTERN
200
~
+b.o~
VOO
VGG
Typical Propagation Delay
Versus Ambient Temperature
CLOCK
PULSE
Am2Bl0
12B·BIT SHIFT REGISTER
(AOR 81
OUT
1--'-"-"
I
CL = 20pF
IiNCLUDING SCOPE
ANDJIGI
MOS-415
MOS-414
DEFINITION OF TERMS
SET-UP and HOLD TIMES The shift register will accept the data
that is present on its input around the time the clock goes from
LOW-to-H IGH. Because of variations in individual devices, there
is some uncertainty as to exactly when, relative to this clock
transition, the data will be stored. The set-up and hold times
define the limits on this uncertainty. To guarantee storing the
·correct data, the data inputs should not be changed between
the maximum set-up time before the clock transition and the
maximum hold time after the clock transition. Data changes
within this interval mayor may not be detected.
5TATIC SHIFT REGISTER A shift register that is capable of
llaintaining stored data without being continuously clocked.
Vlost static. shift registers are constructed with dynamic master
tnd static slave flip-flops. The data is stored dynamically while
he clock is LOW and is transferred to the static slaves while the
:Iock is HIGH. The clock may be stopped indefinitely in the
ilGH state, but there are limitations on the time it may reside
n the LOW state.
5-25
Am2810
APPLICATIONS
I
I
REGISTER ADDRESS
I
I
I I
A,
AO
I
L
A3
A2
234567
nm
I
I
I
DIN
r---
1'( '(
128 BIT SHIFT REGISTER
IBI
OUT
-CP
89
."
·V
> - - DIN
I
I
b
RC
Arn2810
128·BIT SHifT REGISTER
IAI
OUT
-CP
DIN
~
VRA --12V
VRS "VR¢'" +5v
RC
RIN
DIN
Am2810
12881T SHIFT REGISTER
IBI
OUT
·
6
DIN
OUT
··
RC
LRIN
DI\TA IN
12B BIT SHIFT REGISTER
,BI
CP
···
I
Am2810
12881T SHIFT REGISTER
IAI
OUT
-CP
-"
u-=
VRA'-12V
VAB :+5V
VRo"-12V
Am2Bl0
,CP
-"
·V
·V
u-=
~
RC
RIN
I
LRI~
IIIII
I
RC
RIN
Am~810
Am9301
1 OF 10 DECODER
01
6
r- E~~I;CE
r
u-=
I
~
VRA '-12V
RC
VAB
RIN
DIN
Am2810
128·81T SHIFT REGISTER
IBI
OUT
:>
VA¢'.r. +5V
I---<
CP
CLOCK
-PEAD ENABLE
),
IIIII
IS E 10 1, 12 13 14 15 16
IsO
1,1
S2
I
Am9312
B·tf\lPUT MULTIPLEXER
Z
Z
'(
I
"I
DATA OUT
Eight Register 256-Bit Memory System
Data enters one of the eight 256-bit registers when the write enable input to the decoder is LOW. The addressed register
will accept the data on the data input; the other seven registers will recirculate their data. Outputs are driven directly into
an Am9312 8-input multiplexer. Obviously, the read and write registers need not be the same. Note that the VRrt> input
is connected to VGG on only one device; the pull-up resistor on this device will pull the line up for all the devices. The
VRB inputs are all connected to VSS, since only MOS compatibility is needed. The VRA inputs are all connected to VGG
because each recirculate input needs a separate pull-up. This also increases the loading on the data input.
TRUTH TABLE
RC
RIN
DIN
Data Entered
L
L
L
H
X
X
L
H
H
H
X
X
L
H
L
H
H = HIGH Voltage level
L = LOW Voltage Level
X = Don't Care
Metallization and Pad Layout
R IN --,-.". _u,. e.. ,
B
RC
8
OUT
B
Voo
Vss
A
86 X 95 Mils
5-26
MOS-416
Am 2814/3114
Dual 128-Bit Static Shift Register
Distinctive Characteristics
• 2nd Source to Texas Instruments 3114
• Operation guaranteed from DC to 2.5MHz.
• 100% reliability assurance testing in compliance with
MIL-ST D-883
• Full military grade devices available
FUNCTIONAL DESCRIPTION
LOGIC SYMBOL
The Am3114 is a dual 128-bit static shift register built using
P-channel silicon gate MOS technology. The two registers
each have a two-input multiplexer on their inputs, so that
input data may be selected from one of two sources. Both
registers have a common clock input, and operate with a lowvoltage TTL clock signal. The registers shift on the LOW-toHIGH edge of the clock signal. Data at the inputs must be
steady for a set-up time before and a hold time after this
clock transition. Since data storage is static, the clock may
be halted indefinitely in the HIGH state. The outputs of each
register can drive one TTL load or three Am93L low-power
TTL loads.
13
-
RIN
15
-
DIN
-
CP
-
The two-input multiplexer on the input of each register is
controlled by the RC (recirculate control) input. When RC is
LOW, data is accepted on the Din input; when RC is HIGH.
data is accepted on the R in input. The Am2814 is functionally identical to the Am3114. but is specified with
higher performance.
I
14
RC
Am3114
128-BIT SHIFT REGISTER
IB)
OUT f - - 12
i
RIN
DIN
RC
Am3114
128-BIT SHIFT REGISTER
IA)
OUT I - -
CP
Vss = Pin
7
VDD= Pin 6
VGG=Pinll
MOS-417
LOGIC BLOCK DIAGRAM (One Register Shown)
RIN---------r~
RC-----~~--~-J
DIN
DIN-----------L-'
Am3114
128-BIT
SHIFT REGISTER
OUT
CP
CLOCK--------------.
TO OTHER REGISTER
CP INPUT
MOS-418
ORDERING INFORMATION
CONNECTION DIAGRAM
NC
Package
Type
Temperature
Range
Molded DIP
Hermetic DIP
Hermetic DIP
_25 0 eta +85° C
0
_25 C to +85° C
0
-55 C to +125°C
Am3114
Order
Number
Am2814
Order
Number
TMS3114NC
TMS3114JC
AM2814PC
AM2814DC
AM2814DM
NC
A DIN
B DIN
A RIN
B RIN
ARC
A OUT
V DD
B RC
BOUT
VGG
Vss
NC
NC
CP
Notes: 1. Pin 1 is marked for orientation.
2. NC = No Connection.
5-27
MOS-419
Am28141Am3114
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
V DO Supply Voltage
VSS -10V to VSS +O.3V
V GG Supply Voltage
DC Input Voltage
VSS -20V to VSS +O.3V
VSS -15V to VSS +O.3V
OPERATING RANGE
Part Number
VSS
VDD
Am2814PC, DC
Am3114JC, NC
-11Vto-13V
-11.4V to -12.6V
Am2814DM
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless otherwise noted)
Typ.
Parameters
Description
Test Conditions
VOH
Output HIGH Voltage
VOH
Min.
Max.
(Note 1)
Units
IOH
= -200).LA
Output LOW Voltage
IOL
= 1.6mA
Input HIGH Level
Guaranteed input logical HIGH
voltage for all inputs
VIL
Input LOW Level
Guaranteed input logical LOW
voltage for all inputs
0.6
IlL
Input LOW Current
VSS
= MAX., VIN = 0.6V
0.5
).LA
IIH
Input HIGH Current
VIN - VSS
0.5
).LA
ISS
VSS Power Supply Current
Inputs and Outputs Open
f = lMHz
VIH
VGG Power Supply Current
IGG
Note 1.
Typical Limits are at VSS
= 5.0V,
VGG
Volts
VSS-l
Am3114
Am2814
Volts
0.4
0.2
l
I
3.5
VSS -1.5
Volts
Am3114
15
Am2814XC
14
25
Am2814XM
14
35
Am3114
-4
Volts
rnA
Inputs and Outputs Open
f = lMHz
Am2814XC
-4
-10
Am2814XM
-4
-15
= -12 V, 25°C ambient and
maximum loading.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Parameters
Description
Test Conditions
Min.
Am3114
Typ. Max.
Min.
f max
Maximum Clock Frequency
tcppw H
tcppw L
Clock HIGH Time
.330
00
.200
Clock LOW Time
.130
100
.170
t r , tf
Clock Rise and Fall Times
ts(D)
Set-up Time, D or R Inputs
(see definitions)
th(D)
Hold Time, D or R Inputs
(see definitions)
ts(RC)
Set-up Time, RC Input (see definitions)
th(RC)
Hold Time, RC Input (see definitions)
tpd
Delay, Clock to Output LOW or HIGH
RL
t pr , tpF
Output Rise and Fall Times
10% to 90%
Cin
Capacitance, Any Input (Note 3)
f
2.0
Am2814
Typ. Max.
00
100
5
100
tr
= tf
.;;; 50ns
5
100
).Ls
).LS
).LS
ns
100
100
ns
100
100
ns
150
150
= 2.7k, CL = 20pF
= 1 MHz, VIN = VSS
Notes: 3. This parameter is periodically sampled but not 100% tested. It is guaranteed by design.
4. At any temperatu're, tpd min. is always much greater than th(D) max.
5-28
Units
MHz
2.5
350
13
ns
(Note4)
250
3
ns
100
ns
7
pF
Am2814/3114
TIMING DIAGRAM
'Pd MAX
+5V----------------------------------~~~~~~~~~~_h--------------------~_,~~~~~~
~
90%
OUTPUT
~
10%
•
OV ----------------------------------~~~~~~~~~~------------.--------~~~~~~~
WRITING NEW DATA
RECIRCULATING
M05·420
TEST CI RCUIT
Typical Power-Supply Currents
Versus Frequency
7
~
E
6
54
3-
2
II
I
425°C I
l\2~oCI
}::
4
3
2
1
1k
~ +~.OIV
i2~OCI
~
z
0
150
r--
f=
~
~
,..,. n-
.....
~
I
-!~~
,/L. . . r~',
~
lL
10k
L/
/" .,'r'"
I
0
11"~
125°C
I
I
>I
I
I
I
IGG
11 - VSSI
,0 VDD~OV
9 VGG = -12.0V
+5.0V
1/
~
ISS-
/
~
0 - - - - +5.0V
INPUT
PATTERN
200
UI
.,
I
Typical Propagation Delay
Versus Ambient Temperature
~
k-"
RC
,/
L......_ _-\DIN
+-t-- H -
7- t=f-t
,------\CP
Vss = +5.0V
1 VDD = OV
VGG = -12.0V
Am3114
128-81T SHIFT REGISTER
IA OR 81
OUT
1--*-'"
I
CL = 20pF
(INCLUDING SCOPE
ANDJIGI
100
lOOk
1M
10M
CLOCK FREQUENCY - Hz
-55 -35 -15
5
25 45
65 85 105125
AMBIENT TEMPERATURE _
°c
CLOCK
PULSE
MOS·422
MOS·421
)EFINITION OF TERMS
SET-UP and HOLD TIMES The shift register will accept the data
that is present.on its input around the time the clock goes from
LOW-to-H IGH. Because of variations in individual devices, there
is some uncertainty as to exactly when, relative to this clock
transition, the data will be stored. The set·up and hold times
define the· limits on this uncertainty. To guarantee storing the
correct data, the data inputs should not be changed between
the maximum set·up time before the clock transition and the
maximum hold time after the clock transition. Data change~
within this interval mayor may riot be detected.
iTATIC SHIFT REGISTER A shift register that is capable of
naintaining stored data without being continuously clocked.
110st static. shift registers are constructed with dynamic master
nd static slave flip-flops. The data is stored dynamically while
he. clock is LOW and is transferred to the static slaves while the
lock is HIGH. The clock Olay be stopped indefinitely in the
IIGH state, but there are limitations on the time it may reside
, the LOW state.
5-29
Am281413114
APPLICATIONS
I
REGISTER ADDRESS
I I I
AO
A,
I
A2
RC
LRIN
A3
,--DIN
Am9301
Am3114
128 BIT SHIFT REGISTER
,
.1
Iii -".....
2345678
mn
~RIN
_
OUT
D,N
RC
Am3114
128 BIT SHIFT REGISTER
OUT
(BI
IBI
'·OF-IO DECODER
10
~
b
r- E~~~~E
; - - - CP
CP
I
-
~
6
IIIII
RC
LRIN
.-+-- D,N
I I I I I
Am3114
128 BIT SHIFT REGISTER
OUT
IAI
u-=
~CP
D,N
···
~
b
D,N
DATA IN
RC
Am3114
128 BIT SHIFT REGISTER
Lr=RIN
-
OUT
D,N
Am31t4
128 BIT SHIFT REGISTER
IBI
IAI
~CP
t>-
OUT
(BI
RC
LRIN
Am3114
128 BIT SHIFT REGISTER
CP
I
··
·
t>-
RC
R'N
I
OUT
f--
CP
CLOCK
-READ ENABLE
b IIIII
JSOE
'0 I, '2 '3 14 '5 IS
15 , 8 lNPUTA;0~+~PlEXER
52
z
171
z
i I
Eight Register 256-Bit Memory System
Data enters one of the eight 256-bit registers when the write enable input to the decoder is LOW. The addressed register
will accept the data on the data input; the other seven registers will recirculate their data. Outputs are driven directly into
an Am9312 8-input multiplexer. Obviously, the read and write registers need not be the same. Pull-up resistors are required
on all register inputs driven from TTL.
MOS-423
TRUTH TABLE
RC
DIN
BIN
Data Entered
L
L
H
H
L
H
X
X
X
X
L
H
L
H
L
H
H = HIGH Voltage level
L = LOW Voltage Level
X = Don't Care
5-30
Am2825· Am2826· Am2827
2048-Bit Dynamic Shift Registers
Distinctive Characteristics
• 6 MHz data rate guaranteed
• Single 2048 and dual 1024-bit configurations
• Low power dissipation
• TTL compatible data inputs and outputs
•
•
•
•
On chip recirculate and input select controls
Plug-in replacement for National 5025/26/27
Full military temperature range devices available
100% reliability assurance testing in compliance with
MI L-STD-883
FUNCTIONAL DESCRIPTION
LOGIC DIAGRAMS
Am2825
The Am2825/26/27 are military and commercial grade
2048-bit dynamic shift registers. The Am2825 is a dual
1024-bit device with on-chip recirculate and a load control
(LC) common to both registers. When LC is HIGH, the two
registers recirculate data; when LC is LOW new data is entered through the data inputs. The Am2826 is similar, but
each register has two data inputs, selected by separate input
select (IS) signals. The Am2827 is a single 2048-bit register
with on-chip recirculate and a load control. All the devices
can drive one standard TTL load or three Am93L series
low-power TTL loads. The select, load command, and data
inputs may be driven by TTL signals. Two high-voltage
clock signals, 1 and 2, are required. Internally, each shift
register consists of two multiplexed registers, so that a data
shift occurs on each 1 or 2 clock pulse. The data rate,
therefore, is double the frequency of either clock signal.
LC
3(3)
OUT A
9(14)
INA
-'-'-t--",,--J
OUT B
INB ..:4.:.:;(6)_ _L~
·1
VGG = Pin 8 (13)
Voo
= Pin 10 (15)
Am2826
OUT A
11A-'-'---L~
ORDERING INFORMATION
12B-"'--t--,~
OUTB
Package
Type
10-Pin Molded
16-Pin Hermetic
16-Pin Hermetic
16-Pin Molded
16-Pin Hermetic
16-Pin Hermetic
8-Pin Molded
8-Pin Hermetic
8-Pin Hermetic
Temperature
Range
O°C to +70°C
O°C to +70°C
-55°C to +125°C
O°C to +70°C
O°C to +70°C
-55°C to +125°C
O°C to +70°C
-55°C to +125°C
O°C to +70°C
Order
Number
11B-"'---L~
Voo = Pin
AM2825PC
AM2825DC
AM2825DM
AM2826PC
AM2826DC
AM2826DM
AM2827PC
AM2827DM
AM2827DC
15
Am2827
LC
MOS-424
CONNECTION DIAGRAMS
Top View
Am2825
OUT A
·1
Am2825
NC
NC
NC
NC
"1
Voo
LC
OUT A
Voo
OUT A
·1
IN A
"1
VGG
ISA
11A
VSS
VGG
IN B
·2
12A
VGG
OUT
NC
Vss
OUT B
LC
NC
Vss
Am2827
Voo
LC
NC
Am2826
·2
OUT B
ISB
128
118
NC
NC
·2
VSS
OUT B
MOS·425
5-31
Am2825 • Am2826 • Am2827
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
DC Input Voltage with Respect to VSS
-20V to +O.3V
OPERATING RANGE
Part Number
AM2825/6/7DM
AM2825/6/7PC,DC
-10.0V to -11.0V
_55°C to +125°C
-lO.OV to -11.0V
OOC to +70 C
0
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Typ.
"arameters
Max.
Units
Volts
0.0
VSS
0.4
Guaranteed input logical H IG H voltdge
for all inputs except clocks
VSS -1.0
VSS +0.3
Volts
Guaranteed input logical LOW voltage
for all inputs except clocks
VSS -10
VSS -4.2
Volts
Description
VOH
Output High Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Level
VIL
Input LOW Level
Test Conditions
= -0.5mA
IOL = 1.6mA
Min.
(Note 1)
2.4
IOH
= -10V, TA = 25°C
= -15V, TA = 25°C
II
Input Leakage Current
VIN
10
500
I¢
Clock I nput Leakage Current
V¢
50
1000
V¢H
Clock HIGH Level
V¢L
Clock LOW Level
VSS -1.0
VGG -0.3
.D1MHz-
u
10k
fE
V
-c-·
:::>
~
"ug
1.0k
u
::;;
:::>
~
100
GUARANTEED
Il-
V./
/
,?-y
"'
20
100
60
140
18
\
V¢~-11.0V
~
VDD~
'\
52
'\
48
-
OV
VSS ~ +5.25V ¢f ~ 3.0 MHz
¢pw ~ 125 ns
VGG ~-11.0V-
Vss ~ +5V
vGG ~ -10.5V-
16
V¢~-10.5V
14
12
44
........ r--.
40
36
10
/.ta; ~
-40
40
80
120
TA - AMBIENT TEMPERATURE - °c
r\
A~
~~ TA ~ 75°C
,
-
I
32
0.01
oV
o
-2.0
:::\
VDD~ OV
VSS ~ +5.25V
TA~+25°C
10
50 60 70 80
58
--
·54
~
52
/
I
J~
50
48
-8.0
20 30 40
56
TA ~ 125°C
-6.0
VGG~-11.0V
I
o
90
Typical Power Supply Current Versus
Clock Pulse Width tpw
46
-4.0
125 ns
100 - rnA
T~J5oJ- \. -. -::::
k::: ~
"
I
~
1
~
V¢~-11.0V
0
Vs~ ~ +5V
<{
-20
¢pw
0.1
<{
VOH Versus IOH
56
~0
<{
/
/
I-
Typical Power Supply Current
Versus Temperature
60
z
4.2
:::>
::;;
~
1\\
TA - AMBIENT TEMPERATURE - °c
0
_0
~
u
1.0
~
'\
I
V DD ~ OV
VGG ~ -10.5V
V¢ ~ -10.5V
4.0
60
80
100
120
140
20
40
TA - AMBIENT TEMPERATURE - °c
E
I
a::
4.3
I
>-
u
x
64
:::>
u
"'r\.
::;;
68
1--
"g
::;;
,
10
-60
<{
~
4.4
"-
I!
::;;
4.1
z
~
4.5
U
.J..'l'v
V
fE
-"'"""'"
:::>
./
I
4.6
>u
/
I
I
-10
VO H (NEGATIVE WITH RESPECT TO VSS) - VOLTS
I
~
VGG ~ -11.0V
/
V
V¢~-11.0V
V DD
~
OV
Vss ~ +5.25V
I
44
90
V
V
./
f¢~3MHz
110
130
¢pw- ns
150
MOS-42B
Metallization and Pad Layouts
Am2825
OUT A
1-
_ _ _--,
Am2827
Am2826
OUTA
1------,
14
13
12
LC
3
IN B
4
Vss
6
ISA
12A
ISB
11B
VSS
10 02
B
1..-.----9
DIE SIZE 0.145" X 0.162"
11A
VGG
12B
DIE SIZE 0.145" X 0.162"
5-35
OUTB
DIE SIZE 0.145" X 0.162"
Am2833/2533
1024-Bit Static Shift Registers
Distinctive Characteristics
• Second source to Signetics 2533
• All inputs are low-level DTL/TTL compatible
• 100% reliability assurance testing in compliance with
M I L-STD-883 .
• Static operation with single clock input.
• DC to 2.0MHz operation with Am2833
FUNCTIONAL DESCRIPTION
LOGIC SYMBOL
The Am2533/2833 is a quasi-static 1024-bit MaS shift
register using low-threshold P-channel silicon gate technology.
The device has a single TTL/DTL compatible clock input,
Cpo Data in the register is stored in static, cross-coupled
latches while the clock is LOW, so that the clock may be
stopped indefinitely in the LOW state. When the clock
shifts from LOW to HIGH to LOW adynamic transfer of
data occurs from one static latch to the next. The input of
the register is a two-input multiplexer with both data inputs available. A select line, S, determines whether data will
be accepted from the 10 input (S = LOW) or the 11 input
(S = HIGH). The register can be placed in the recirculate
mode by tying the output, 0, to one of the data inputs, and
using the select line as a write/recirculate control. The
Am2833 is functionally identical to the Am2533 but has
superior performance over an extended temperature range.
Vee =
Pin
=
Voo =
Pin 2
VGG
8
Pin 4
MOS-429
LOGIC DIAGRAM
IN
1024-BITS
OUT
CLOCK
Cp
MOS-43
ORDERING INFORMATION
Package
Type
Temperature
Range
Molded DIP
Hermetic DIP
Hermetic DIP
O°C to +70°C
O°C to +70°C
_55°C to +125°C
CONNECTION DIAGRAM
Top View
Am2533
Order
Number
Am2833
Order
Number
AM2533V
AM2533DC
AM2833PC
AM2833DC
AM2833DM
OUT
1-12V)VGG
V
CC
(+5_0V)
IF
CP
(GNO)V
oo
10
Note: Pin 1 marked for orientation
MOS-'
5-36
Am283312533
MAXIMUM RATING
(Above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
Voo Supply Voltage
VCC -20V to VCC +O.3V
VGG Supply Voltage
VCC -20V to VCC +O.3V
DC Input Voltage
VCC -20V to VCC +O.3V
OPERATING RANGE
Part No.
Temperature
Vec
o°c to +70°C
5.0V ±5%
-12V ±5%
OV
-55°C to +125°C
5.0V ±5%
-12V ±5%
OV
. Am2833PC/ Am2533PC
Am2833DC/ Am2533pC
I
I
Am2833DM
Voo
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Parameters
Description
Test Conditions
VOH
Output HIGH Voltage
VCC = MIN., IOH = -100,uA
VOL
Output LOW Voltage
VCC = MIN., IOL = 1.6mA
(Note 3)
Guaranteed input logical LOW
voltage for all inputs
IlL
Input LOW Current
VCC = MAX., VIN = OV, TA = 25°C
IIH
I nput
liT
Peak input transition
current (Note 3)
Vlmax
Voltage at maximum
input current
VCC Power Supply
Current
Max.
Volts
Volts
VCC+O·3
Volts
0.8
Volts
10
-150
500
TA = 25°C
VSS-4.0
,uA
VSS-3.0
f = 2.0MHz
-1.6
mA
VSS-1.5
V
16
30
Am2833PC, DC
16
54
Am2833DM
20
70
Am2533
f=1.5MHz
nA
-300
1.5';;; VSS - VIN .;;; 4.0, TA = 25°C
f = 1.5M Hz
Units
0.4
VGG
TA = 25°C, VIN = VCC -1.0 (Note 3)
f = 2.0MHz
VGG Power Supply
IGG
3.5
H IG H voltage for all inputs
Input LOW Level
Current
2.4
V CC -1
VIL
ICC
Typ.
(Note 1)
Guaranteed input logical
Input HIGH Level
Current
Min.
0.2
VIH
:~ IG H
(Unless Otherwise Noted)
mA
Am2533
-5.0
-7.5
Am2833PC, DC
-5.0
-14
Am2833DM
-7.0
-18
mA
::Hes: 1. Typical limits are at Vee = 5.0V. VGG = -12V, 25°e ambient.
2. Power supply currents are with inputs and outputs open.
3. A special input pull-up circuit becomes active at VI N = VSS -3.5V to pull the internal input node up to the MaS threshold. To return the
internal node to the LOW state, current must be drawn from the MaS input. This current is maximum at approximately 2.0V.
NITCHING CHARACTERISTICS OVER OPERATING RANGE
(Unless Otherwise Noted)
Am2533
rameters
Description
Test Conditions
Min.
Typ.
(Note 1)
1.5
2.0
f max
Maximum Clock Frequency
tcppw L
tcppw H
Clock LOW Time
0.250
Clock HIGH Time
0.350
t r , tf
Clock Rise and Fall Times
ts(t)
Set-up Time, 10 or 11 Input
(see definitions)
th(t)
Hold Time, 10 or 11 Input
(see definitions)
ts(S)
Set-up Time, S Input
(see definitions)
thIS)
Hold Time, S Input
(see definitions)
tpd
Delay, Clock to Output
LOW or HIGH
:pr, tpf
Output Rise and Fall Times
~m
Capacitance, Any Input (Note 2)
....
Am2833
Max.
Min.
Typ.
(Note 1)
2.0
3.0
Max.
Units
MHz
00
0.200
00
100
1
0.250
100
1
,us
,us
,us
50
50
ns
50
50
ns
80
80
ns
50
50
ns
tr = tf .;;; 25ns
RL = 2.9k, CL = 20pF
300
300
10% to 90%
150
f - 1 MHz, VIN - VCC
es: 1. Typical limits are at Vee = 5.0V, VGG = -12.0V and TA = 25°e
2. This parameter is periodically sampled but not 100% tested. It is guaranteed by design.
5-37
3
5
3
ns
150
ns
5
pF
Am2833/2533
TIMING DIAGRAM
+5V
cp
50%
50%
OV
r-----t¢pwH - - - - - - 1
!sll) MAX.--I------+
+5V
50%
50%
OV
+5V
10
OV
+5V
OV
+5V
-
3.0'1
OUTPUT
0.4'1
OV
WRITE DATA FROM 10
WRITE DATA FROM II
1.105-432
TYPICAL PERFORMANCE CURVES
Power Dissipation
Versus Ambient Temperature
tpd as a Function
of Ambient Temperature
300
280
I
>-
;;
:5w
E
I
0
0..
260
240
Vss = 5.0V
VDO = OV
=R""
0
f-
220 ' - -
f::l
200
r -r--
180
./
~
0
105
100
95
160
0
10
20
30 40 50
TA _oC
60
70
L
V
+-
1--- ._-
i
V
-50
80
7
/,/
+75
+125°
1.105-4
DEFINITION OF TERMS
SET-UP a"nd HOLD TIMES The shift register will accept the c
that is present on its input around the time the (:Iock goes fr
HIGH-to-LOW. Because of variations in individual devices, tt
is some uncertainty as to exactly when, relative to this cI
transition, the data will be stored. The set-up and hold ti
define the limits on this uncertainty. To guarantee storing
correct data, the data inputs should not be changed betl/\
the maximum set-up time ""before the clock transition and
maximum hold time after the clock transition. Data chal
within this interval mayor may not be detected.
STATIC SHIFT REGISTER A shift register that is capable of
maintaining stored data without being continuously clocked.
Most static shift registers are constructed with dynamic master
and static slave flip-flops. The data is stored dynamically while
the clock is HIGH and is transferred to the static slaves while the
clock is LOW. The clock may be stopped indefinitely in the
LOW state, but there are limitations on the time it may reside
in the HIGH state.
5-38
Am2833/2533
I
REGISTER ADDRESS
I
I I
AO
A1
1
~IO
6
~vcc
I
S
Ll1
A3
A2
234567
nni
I
E%~I;CE
I
Am9301
1-0F-10 DECODER
o
APPLICATIONS
I
T
S
Am 2533/2633
1024-BIT SHIFT REGISTER
OUT
LS=11
-10
lep
,-CP
9
j??
I
IIIII
I I I I I
10
>---
CP
Am2533/2633
1024-6 IT SHIFT REGISTER
LS=11
-10
I
OUT
···
~VCC
I
10
Am2533/2833
1024-6 IT SHIFT REGISTER
CP
S
Ll1
>---
OUT
···
J
DATA IN
S
S
Ll1
OUT
~VCC
I
>-1-
Am 2533/2633
1024-61T SHIFT REGISTER
S
Am2533/2833
1024-61T SHIFT REGISTER
LS=11
10
OUT
CP
Am2533/2833
1024-61T SHIFT REGISTER
OUT
I-
CP
I
--READ ENABLE
6 Illil
CLOCK
Is E
J s~
I
Eight Register 2048-Bit Memory System
S2
10 11 12 13 14 15 IS
6-INPul:Jc+~PLEXER
z
Z
"I
? I
DATA OUT
Data enters one of the eight 2048-bit registers when the write enable input to the decoder is LOW. The
addressed register will accept the data on the data input; the other seven registers will recirculate their data.
Outputs are driven directly into an Am9312 8-input multiplexer. Obviously, the read and write registers
need not be the same.
MOS-434
TRUTH TABLE
S
Data Entered
L
L
x
L
L
H
H
H
X
H
X
X
L
H
L
H
H = HIGH Voltage level
L = LOW Voltage Level
X = Don't Care
Metallization and Pad Layout
OUT
::1;:1,,1'&-- 8 VCC
DIE SIZE: 0.133" X 0,163"
5-39
Am2847· Am2896
Quad BO-Bit and Quad 96-Bit Static Shift Registers
Distinctive Characteristics
• Plug-in replacement for 25328, TMS3120, TMS 3409,
MK1007,3347
• Internal recirculates on each register
• Single TTL compatible clock
• Outputs sink two TTL loads
• Operation guaranteed from DC to 3 MHz
• 100% reliability assurance testing in compliance with
MI L-STD-883
FUNCTIONAL DESCRIPTION
LOGIC SYMBOL
The Am2847 and Am2896 are quad 80-and 96-bit static
MaS shift registers_ Each device contains four shift registers,
each with a TTl.. -compatible input, output, and recirculate
control. When the RC signal is LOW, the corresponding
register accepts data from its data input; when RC is HIGH,
the data at the register output is written back in at the
input. The four registers are driven by a common TTL
compatible clock input. The registers shift on the HIGH-toLOW transition of the clock. Storage is dynamic while the
clock is HIGH and static while the clock is LOW, so the
clock may be stopped indefinitely in the LOW state. Each
register output can drive two TTL unit loads.
14
IN B
IN C
IN 0
CP
10
15
11
QUAD SHIFT
REGISTER
OUT B
OUTC
aUTO
Vss
VOO
VGG
=
=
=
13
Pin 16
Pin 8
Pin 12
MOS-43E
LOGIC BLOCK DIAGRAM
(One Register Shown)
RC
n·BIT STATIC
SHIFT REGISTER
OUT
OUT
INPUT
CLOCK
Am2847 n
Am2896 n
TO OTHER REGISTERS
= 80
= 96
MOS-4:
CONNECTION DIAGRAM
Top View
ORDERING INFORMATION
Am2847 Quad 80-Bit
Package
Type
Temperature
Range
Order
Number
16-Pin Molded DIP
O°C to +70°C
AM2847PC
16-Pin Hermetic DIP
O°C to +70°C
AM2847DC
16-Pin Hermetic DIP -55°C to +125°C AM2847DM
OUTA
VSS
RCA
IN 0
INA
RC 0
OUT B
RC B
IN B
Am2896 Quad 96-Bit
O°C to +70°C
16-Pin Molded DIP
AM2896PC
O°C to +70°C
16-Pin Hermetic DIP
AM2896DC
16-Pin Hermetic DIP -55°C to +125°C AM2896DM
aUTO
VGG
CP
OUTC
IN C
VOO
RC C
Note: Pin 1 is marked for orientation_
5-40
MOS-~
Am2847 • Am2896
MAXIMUM RATINGS
(Above which the useful life may be impaired)
-65°C to +160°C
_55°C to +125°C
Storage Temperature
Temperature (Ambient) Under Bias
VDD Supply Voltage
Vss -10V to VSS +0.3V
VGG Supply Voltage
Vss -20 V to Vss +0.3 V
DC Input Voltage
Vss -20V to Vss +0.3V
OPERATING RANGE
Part Number
Ambient Temperature
Am2847DM
Am2896DM
-55°C to +125°C
Am2847PC, DC
Am2896PC, DC,
O°C to +70°C
5.0V ±5%
OV
-12V ±5%
5.0V ±5%
OV
-12V ±5%
:LECTRICAL CHARACTERISTICS OVER OPERATING RANGE
'arameters
VOH
VOL
Description
Output HIGH Voltage
Output LOW Voltage
(Unless Otherwise Noted) T
Test Conditions
yp.
(Note 1)
Min.
IOH = -0.5mA
Units
Max.
204
IOL = 3.2mA
O°C to 70°C
IOL = 204mA
_55° to 125°C
Volts
004
Volts
VIH
Input HIGH Level
Guaranteed input logical HIGH voltage
for all inputs
VSS -1.0
VSS +0.3
Volts
VIL
Input LOW Level
Guaranteed input logical LOW voltage
for all inputs
VSS -18.5
0.8
Volts
III
Input Leakage Current
VIN = -5.0V, all other pins connected to VSS
IlL
Input LOW Current
VIN = Oo4V
IIH
Input HIGH Current
VIN = VSS -1.0V
IDD
-1.0
J.lA
mA
mA
-0.1
O°C to 70
VDD Power Supply Current
Output open, f = 2.5MHz
IGG
1.0
-1.6
VGG Power Supply Current
0
e
35
25
-55°C to 125°C
45
O°C to 70°C
15
mA
10
20
-55°C to 125°C
te: 1. Typical Limits are at VSS = 5.0V. VGG = -12V. 25°C ambient.
IITCHING CHARACTERISTICS OVER OPERATING RANGE
'ameters
Description
(Unless Otherwise Noted)
Test Conditions
Min.
Typ.
. oOe to 70°C
f
0
2.5
-55°C to125°C
tpw L
t r,
tf
:s
h
pd
Clock HIGH Time
Clock LOW Time
O°C to 70°C
.140
100
-55°C to 125°C
.150
10
O°C to 70°C
.140
-55°C to 125°C
.180
Hold Time, D or RC Inputs (see definitions)
Delay, Clock to Output LOW or HIGH
MHz
J.lS
00
Clock Rise and Fall Times
Set·Up Time, D or RC Inputs (see definitions)
Units
3.0
Clock Frequency
tpw H
Max.
10
tr = tf = 10ns
O°C to 70°C
120
-55°C to 125°C
120
O°C to 70°C
40
-55°C to 125°C
60
200
ns
ns
tr = tf = 10ns
RL = 4k, CL = 10pF
J.lS
ns
O°C to 70°C
200
(Note 3)
ns
280
-55°C to 125°C
:in
Capacitance, Data Clock and RC Inputs (Note 2)
f = 1MHz, VIN = VSS
3.0
7.0
pF
:
Capacitance, Clock Input (Note 2)
f = 1MHz, VIN = VSS
3.0
7.0
pF
's: 2. This parameter is periodically sampled but not 100% tested. It is guaranteed by design.
3. At any temperature, tpd min. is always much greater than th(D) max.
5-41
Am2847 • Am2896
TIMING DIAGRAM
OV
5V
RC
OV
tPdM~AX.
:::::itpdMAX.
+5V
5V
5~~~
OUTPUT
OV
50~O%
---------------------'~~~~~~~---------------------------------------------'~~~~~~~OV
WRITING NEW DATA
RECIRCULATING
MOS·438
KEY TO TIMING DIAGRAM
PERFORMANCE CURVES
Typical Data Output
HIGH Current
Versus Data Output Voltage
2.5
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
WILL BE
STEADY
2.0 t-~
«
WILL BE
CHANGING
FROM HTO L
9
..!IIJ]J
_
MAY CHANGE
FROM L TO H
DON'T CARE:
ANY CHANGE
PERMITTED
CHANGING:
STATE
UNKNOWN
-r-. r-
1.0
0.5
WILL BE
CHANGING
FROM L TO H
o
o
-
r-.....
:I:
_ _ MAY CHANGE
FROMHTOL
TA = -55'C
i '~
1.5
E
_
VDD = GNO
VSS = +5.0V
VGG = -12.0V
TA = +25'C
::z
v
I-f--t--
TC = +125'C
t'\.. /
......
, '\.
r---. <..
22
'-
18
«
E
I
I-
~
=>
u
16 f -
II
5~'CI
~2~,d
14
-"'"
125'C
12
II I I
10
"...
-55'C
8
f-
o
lk
12r~
f-r--
I I
10k
lOOk
11
>-
v
I
/,/
~
..H
II
IL
Cl
~G
z
Q
~
..l1
(:J
JI
~
«
«
V;,;= +5.0
VDD =OV
vGG = -12.0V
1M
200
l:
I
CLOCK FREQUENCY - Hz
Typical Propagation Delay
Versus Ambient Temperature
~O
-"'" 11
25'C
....... ~
"
Typical Power-Supply Currents
Versus Frequency
20
",
10M
150
-
. /V
--*,
/""
V
,/
,/' V-~'
,/
100
·55 ·35 ·15
VSS = +5.0V
VOO = OV
VGG = -12.0V
5
25
45
65 85 105125
AMBIENT TEMPERATURE _
vc
MOS·
SET-UP and HOLD TIMES The shift register will accept the (
that is present on its input around the time the clock goes fl
HIGH-to-LOW. Because of variations in individual devices, tl
is some uncertainty as to exactly when, relative to this cl
transition, the data will be stored. The set-up and hold ti
define the limits on this uncertainty. To guarantee storing
correct data, the data inputs should not be changed bet\/'
the maximum set-up time before the clock transition and
maximum hold time after the clock transition, Data cha
within this interval mayor may not be detected.
DEFINITION OF TERMS
STATIC SHIFT REGISTER A shift register that is capable of
maintaining stored data without being continuously clocked.
Most static shift registers are constructed with dynamic master
and static slave flip-flops. The data is stored dynamically while
the clock is HIGH and is transferred to the static slaves while the
clock is LOW. The clock may be stopped indefinitely in the LOW
state, but there are limitations on the time it may reside in
the HIGH state.
5-42
Am2847 • Am2896
Metallization and Pad Layouts
Am2847
OUT A
Am2896
16
Vss
15
IN D
15
IN D
RC A
RC A
14
RC D
14 RC D
IN A
OUT B
16 Vss
OUT A
4
13
OUT D
12
VGG
IN A
3
OUT B
4
13 OUTD
12 VGG
RC B
RC B
11
CP
11
IN B
CP
IN B
10
IN C
10 IN C
OUTC
RC C
OUT C
DIE SIZE 0.106" X 0.128"
7
9
DIE SIZE 0.106" X 0.128"
5-43
RCC
Am2855· Am2856· Am2857
Quad 128-Bit, Dual 256-Bit and Single 512-Bit Static Shift Registers
Distinctive Characteristics
• High-speed replacement for National 5055/617
• Internal recirculate
• Single TTL compatible clock
• Operation quaranteed from DC to 2.5MHz
• 100% reliability assurance testing in compliance witl
MIL-STD-883
FUNCTIONAL DESCRIPTION
LOGIC SYMBOLS
These devices are a family of static P-channel MOS shift
registers in three configurations. The Am2855 is a quad
128·bit register; the Am2856 is a dual 256-bit register; and
the Am2857 is a single 512-bit register. All three devices
include on chip recirculate. The registers are all clocked by
a single low-level clock input. Because the registers are
static, the clock may be stopped indefinitely in the LOW
state without loss of data. Each of the registers has a single
data input; data on the input is written into the register on
the H IGH-to-LOW clock edge. A single recirculate control
(RC) on each chip determines whether the registers on that
chip are to write data in from the data inputs or recirculate
the data appearing on the output. If RC is LOW, new data
is written in; if RC is HIGH then the data on the output will
be written back into the register input on the next
clock pulse.
RC
IN A
IN 6
IN C
IN 0
CP
13
5
11
14
OUT A
Am2655
QUAD 128-61T
SHIFT REGISTER
OUT 6
OUT C
12
aUTO
Vss = Pin 8
VOO = Pin 16
VGG = Pin 10
10
RC
IN A
OUT A
Am2856
DUAL 256-6 IT
SHIFT REGISTER
IN 6
CP
Vss = Pin 5
4
OUT 6
VOO = Pin 9
VGG = Pin 7
1
I
RC
2 - IN
512-61T
S~7~~5~EGISTER
OUT I - - 3
Vss = Pin 4
VOO = Pin 8
5 - CP
VGG=Pin6
MOS-440
LOGIC BLOCK DIAGRAM
(One Register Shown)
n-BIT STATIC
SHIFT REGISTER
CLOCK
OUT r----4~__t
OUT
- - t - - - - - - -......
Am2855 n
Am2856 n
Am2857 n
TO OTHER
REGISTERS
= 128
= 256
= 512
MOS-4
ORDERING INFORMATION
CONNECTION DIAGRAMS
Am2855
Package
Type
Temperature
Range
Order
Number
16-Pin Molded DIP
16-Pin Hermetic DIP
16-Pin Hermetic DIP
aOc to +7aoC
aOc to +7aoC
-55°C to +125°C
AM2855PC
AM2855DC
AM2855DM
10-Pin Plastic DIP
TO-100 Can
TO-10a Can
aOc to +7aoC
aOc to +7aoC
-55°C to +125°C
AM2856PC
AM2856HC
AM2856HM
8-Pin Molded DIP
8-Pin Hermetic DIP
8-Pin Hermetic DIP
aOc to +70°C
aOc to +7aoC
_55°C to +125°C
AM2857PC
AM2857DC
AM2857DM
V OD
NC
IN
A
OUT IN OUT
ABC
NC OUT
B
IN
C
Am2856
IN
0 VGG
RC
CP
NC 0gr Vss
Vss
Am2856
Am2857
RC
Vaa
IN A
OUT A
IN
NC
IN B
OUT
Vss
RC
Vaa
VGG
CP
OUT B
Vss
NC
VGG
CP
MaS
5-44
Am2855 • Am2856 • Am2857
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature
-65°C to +160°C
Temperature (Ambient) Under Bias
VDD Supply Voltage
Vss -10V to Vss +0.3V
VGG Supply Voltage
Vss -20V to Vss +0.3V
DC Input Voltage
Vss -20 V to Vss +0.3 V
:lPERATING RANGE
Part Number
Am2855DM
Am2856HM
Am2857DM
Am2855PC, DC
Am2856HC
Am2857PC, DC
Ambient Temperature
Vss
-55°C to +125° C
5.0V ±5%
OV
-12V ±5%
5.0V ±5%
OV
-12V ±5%
O°C to +70°C
VDD
LECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Typ.
arameters
Test Conditions
Description
Min.
(Note 1)
Max.
Units
Volts
VOH
Output HIGH Voltage
IOH = -0.5mA
VOL
Output LOW Voltage
IOL = 1.6mA
VIH
Input HIGH Level
Guaranteed input logical HIGH voltage
for all inputs
VSS:"1.0
VSS +0.3
Volts
VIL
Input LOW Level
Guaranteed input logical LOW voltage
for all inputs
VSS -18.5
VSS -4.2
Volts
IlL
Input Leakage Current
0.5
J.lA
IDD
VDD Power Supply Current
VGG Power Supply Current
IGG
te: 1.
2.4
0.4
VIN = -10.0V, all other pins GND,
0.01
TA=25°C
TA = 25°C,
trppwH = 160 ns
Data = 1010...
output open
20.0
28.0
12.0
16.0
f = 2.5 MHz
Volts
rnA
Typical Limits are at Vss = 5.0V, VGG = -12V, 25°C ambient and maximum loading.
(ITCHING CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Max.
Units
c
Clock Frequency
0
2.5
MHz
:rppw H
Clock HIGH Time
0.16
10.0
J.ls
·rppw L
Clock LOW Time
0.200
00
J.lS
r, tf
Clock Rise and Fall Times
200
ns
s
Set·up Time, D or RC Inputs (see definitions)
t r =tf=50ns
100
h
Hold Time, D or RC Inputs (see definitions)
tr = tf = 50ns
40
RL = 4k, CL = 10pF
(Note 3)
ameters
Description
Test Conditions
Min.
Typ.
10
ns
ns
ns
pd
Delay, Clock to Output LOW or HIGH
:in
Capacitance:Data In and RC Inputs (Note 2)
f=1MHz,VIN=VSS
3
7
pF
:rp
Capacitance, Clock Input (Note 2)
f=1MHz,VIN=VSS
3
7
pF
,s: 2. This parameter is periodically sampled but not 100% tested. I t is guaranteed by design.
3. At any temperature, tpd min. is always much greater than th(D) max.
5-45
160
280
Am2855 • Am2856 • Am2857
TIMING DIAGRAM
-ltrf-
r-t¢PwH--j
J- i't
-ltfr-
____________________~)2¥-------------------1--~~---9~___________-_______________________________-__~:~'
5V
CP
1~
OV
10%
f------t¢pwL-----i
5V
DIN
OV
5V
RC
OV
'"':::::tAX.
5V
+5V
50~0%
OUTPUT
--------------------~~~~~~~--------------------------------------------~~~~~~~~OV
OV
WRITING NEW DATA
RECIRCULATING
MOS-443
PERFORMANCE CURVES
KEY TO TIMING DIAGRAM
Typical Data Output
HIGH Current
Versus Data Output Voltage
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
WILL BE
STEADY
2.0
-
~
V
0
111
GG
z
Q
150
r--- -
1-
... ~1H
~
'
V
,/
VSS = +5.0V
Vaa =ov
VGG = -12.0V
VDD-OV
VGG· -12.0V
1M
CLOCK FREQUENCY-Hz
10M
....... V
, /V
100
-55 -35 -15
5
25 45
65 85 105 125
AMBIENT TEMPERATURE -"C
MOS-'
DEFINITION OF TERMS
SET-UP and HOLD TIMES The shift register will accept the c
that is present on its input around the time the clock goes fr
HIGH-to-LOW, Because of variations in individual devices, tt
is some uncertainty as to exactly when, relative to this cI
transition, the data will be stored. The set-up and hold ti
define the limits on this uncertainty .. To guarantee storing
correct data, the data inputs should not be changed bet",
the maximum set-up time before the clock transition and
maximum hold time after the clock transition. Data char
within this interval mayor may not be detected.
STATIC SHIFT REGISTER A shift register that is capable of
maintaining stored data without being continuously clocked,
Most static shift registers are constructed with dynamic master
and static slave flip-flops, The data is stored dynamically while
the clock is HIGH and is transferred to the static slaves while the
clock is LOW. The clock may be stopped indefinitely in the LOW
state, but there are limitations on the time it may reside in
the HIGH state.
5-46
Am2855 • Am2856 • Am2857
Metallization and Pad Layouts
Am2856
Am2855
RC
VDD
RC
10
16
9
14 OUT A
IN A 2
IN A
1
OUT B 4
OUT A
2
IN C 5
IN B
3
OUT D 7
OUT B
4
13 IN B
12 OUT C
11 IN D
Am2857
Vao
RC
IN
2
OUT
3
DIE SIZES: 0.101" X 0.142"
5-47
5
6
7
VSS
CP
VGG
Vaa
Am4025/5025 • Am4026/5026 • Am4027/5027
2048 -Bit Dynamic Shift Registers
Distinctive Characteristics
• 6 MHz data rate guaranteed
• Single 2048 and dual 1024-bit configurations
• Low power dissipation
• TT L compatible data inputs and outputs
•
•
•
•
On chip recirculate and input select controls
Alternate source to National parts
Full military temperature range devices available
100% reliability assurance testing in compliance with
MI L-STD-883
I
FUNCTIONAL DESCRIPTION
LOGIC DIAGRAMS
The Am4025/617 and Am502!?/617 are military and commercial grade 2048-bit dynamic shift registers.
The
Am4025/5025 is a dual 1024·bit device with on-chip recirculate and a load control (LC) common to both registers.
When LC is HIGH, the two registers recirculate data; when
LC is LOW new data is entered through the data inputs. The
Am4026/5026 is similar, but each register has two data inputs, selected by separate input select (I S) signals. The
Am4027/5027 is a single 2048·bit register with on·chip recirculate and a load control. All the devices can drive one
standard TTL load or three Am93L series low·power TTL
loads. The select, load command, and data inputs may be
driven by TTL signals. Two high-voltage clock signals, ct>1
and ct>2, are required. Internally, each shift reg·ister consists
of two multiplexed registers, so that a data shift occurs on
each <1>1 or ct>2 clock pulse. The data rate, therefore, is
double the frequency of either clock signal.
Am4025/5025
LC
3(3)
OUT A
INA
9(14)
--t---L-~
OUT B
416)
INB
Vss
• "1
"2
Am4026/5026
= Pin 5 (8)
= Pin 8 (13)
= Pin 10 (15)
VGG
VDD
12A
OUT A
14
11A
ORDERING INFORMATION
Package
Type
10-Pin Molded
16·Pin Hermetic
16-Pin Hermetic
16-Pin Molded
16-Pin Hermetic
16-Pin Hermetic
8-Pin Molded
8·Pin Hermetic
8-Pin Hermetic
Temperature
Range
O°C to +70°C
O°C to +70°C
-55°C to +125°C
O°C to +70°C
O°C to +70°C
-55°C to +125°C
O°C to +70°C
O°C to +70°C
-55°C to +125°C
12
12B
OUTB
Order
Number
liB
MM5025N
MM5025D
MM4025D
MM5026N
MM5026DC
MM4026D
MM5027N
AM5027DC
AM4027DM
"1
°2
Am4027/5027
LC
MOS-445
CONNECTION DIAGRAMS
Top Views
MM4025D
.,
OUTA
NC
VDe
OUT A
"1
MM4027/5027
MM4026/5026
MM5025N
NC
"1
"1
Vee
LC
OUTA
Vee
'''' A
LC
IN A
LC
VGG
ISA
I1A
VSS
NC
VGG
IN B
"2
12A
VGG
OUT
Vss
OUTB
ISB
12B
NC
NC
IN B
NC
liB
NC
NC
"2
NC
"2
Vss
OUT B
VSS
OUTB
MOS-"-4
5-48
Am40/5025 • Am40/5026 • Am40/5027
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
DC Input Voltage with Respect to VCC
-20V to +O.3V
OPERATING RANGE
Part Number
_55°e to +125°e
oOe to +70o e
-12V ±10%
-12V ±10%
MM4025/6/7
MM5025/6/7
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Typ.
larameters
Description
Max.
Units
0.0
VSS
0.4
Volts
Volts
VSS -1.7
VSS +0.3
Volts
VSS -10
VSS -4.2
Volts
Min.
Test Conditions
VOH
VOL
Output High Voltage
Output LOW Voltage
VIH
Input HIGH Level
VIL
Input LOW Level
Guaranteed input logical LOW voltage
for all inputs except clocks
II
Irp
Input Leakage Current
Clock Input Leakage Current
VIN = -10V, TA = 2SoC
Vrp = -1SV, TA = 2SoC
IOH = -O.SmA
IOL = 1.6mA
Guaranteed input logical HIG H voltage
for all inputs except clocks
2.4
10
SO
VrpH
Clock HIGH Level
VSS -1.0
VrpL
Clock LOW Level
VSS -18.S
IGG
VGG Current
TA=2SoC
VDD Current
IDD
(Note 1)
.01MHzd Clock delay time. The time elapsing between the LOW-toHIGH transition of one clock input and the HIGH-toLOW transition of the other clock input. During ttjJd both clocks are HIGH
and all data is stored on capacitive nodes.
5-50
Am40/5025 • Am40/5026 • Am40/5027
SWITCHING WAVEFORMS
BIT 1
BIT 2
BITN
BIT N+l
BIT N +2
BIT 1
BIT 2
V¢H
10%
10%
'111
CLOCK
I
90%
"-'=i
I
f-I r="
VQlL
V¢H
10%
¢2
CLOCK
90%
-=1
~ts
D
DATA IN
IN BIT 1
90%
90%
I--
t¢2pw - j - D A T A RATE
~,~ ~
IN BIT 2
'''~
DATA OUT
I
m
VIH
VIL
] r,:="""v~
OUT BIT 1
VOH
VOL
OUT BIT 2
Clock Rise Time 20ns
Clock Fall Time 20ns
Output Load 1 TTL Load
MOS·448
Metallization and Pad Layouts
Am4025/5025
OUTA
1-----,
Am4026/5026
OUT A
Am4027/5027
1-----,
==I=--::::L
8 Vee
·11A
VGG
7
IN
6
VGG
5
~2
12B
ISA
LC
3
IN B
4
11B
Vss
5
Vss
12A
ISB
DIE SIZE 0.145" X 0.162"
8
DIE SIZE 0.145" X 0.162"
5-51
DIE SIZE 0.145" X 0.162"
Am40/5025 • Am40/5026 • Am40/5027
OPERATING CHARACTERISTICS
Guaranteed Minimum Clock
Frequency Versus Temperature
~
100k
I
>-
u
fE
~
~
~ ~ =.<::>v
u
:;)
100
~
"
'I.,cY
4.4
4.3
u
VOO= -5.0V
4.2 IVGG =-17.0V
~
4.1
x
::;
60
100
'\
I- V'" = -17.0V
c.
~-e.
1,\
10
........ 1-""
/'
>-
V
«
E
I
0
1.0
u
/
fE
"'pw
:;)
~«
I-
«
o
E
r--
10
,
o
40
VGG = -18.5V
.... ~
.........
........ ~
36
32
.,....,...
5B
I--
/.~ ~
A~ 1\
TA = 75°C
~~
oV
~
90
T~ = ~5oJ1\
I-- ~
r;;-
~~
J:
44
Typical Power Supply Current Versus
Clock Pulse Width t¢pw
V",=-12V
I
"'pw = BO ns
"-
VOH Versus IOH
VGG =-12V
5'
Vss = GNO
_ "'f = 3.0 MHz
\
40
-40
BO
120
TA - AMBIENT TEMPERATURE - °c
12
«
VOO = -5.3V
4B
u
0::
0
50 60 70 BO
,
loo-mA
Vss = +5V
14
52
VGG =-1B.5V
20 30 40
1B
16
1--
v", = -1B.5V
\
60
56
z
TA = +25'C
10
~\
6B
64
E
~
Vss = GNO
I
o
0.0 1
-60
-20
20
60
100
140
TA -AMBIENTTEMPERATURE _oc
:;)
VOO = -5.3V
I
0.0 1
BO ns
v",= -1B.5V
I
I
O. 1
~
Typical Power Supply Current
Versus Temperature
Typical Power Supply Current
Versus Data Rate
::;
I
....
\
4.0
20
40
60
BO
100
120 140
TA - AMBIENT TEMPERATURE - °c
140
TA - AMBIENT TEMPERATURE - °c
J:
......
10
I
VSS=GNO
«
20
E
'r\.
~
:;)
-20
100
t3
::;
,
10
-60
- " "-
4.5
g
","'"
VI'
~
z
fE
",«;
g
::;
4.6
:;)
'?c'"
'?c~
1.0k
4.7
u
'<,'V
u
J:
::;
I
>-
//
//
10k
:;)
Guaranteed Maximum t¢p
Versus Temperature (Note 2)
Maximum Clock Frequency
Versus Temperature
56
54
l -I-
~
"
52
I
Ji:
T A = 125°C
50
4B
46
44
-2.0
-4.0
-6.0
-B.O
-10
I
L
V
/
V
VGG = -1B.5V
v",= -1B.5V
V OO =-5.3V
Vss = GNO
V
BO
~
/
"'f=3mHz
9p
100
110
"'pw - ns
VOH (NEGATIVE WITH RESPECT TO VSS) - VOLTS
MOS-449
5-52
Am4055/5055 • Am4056/5056 • Am4057/5057
Quad 128-Bit, Dual 256-Bit and Single 512-Bit Static Shift Registers
Distinctive Characteristics
• Internal recirculate
• Single TTL compatible clock
• Operation guaranteed from DC to 1.5MHz
• 100% reliability assurance testing in compliance with
MI L-STD-883
FUNCTIONAL DESCRIPTION
These devices are a family of static P-channel MOS shift
registers in three configurations. The Am40SS/S0SS is a
quad 128·bit register; the Am40S6/S0S6 is a dual 2S6·bit
register; and the Am40S7/S0S7 is a single S12-bit register.
All three devices include on chip recirculate. The registers
are all clocked by a single low-level clock input. Because the registers are static, the clock may be stopped
indefinitely in the LOW state without loss of data. Each of
the registers has a single data input; data on the input is
written into the register on the HIGH-to-LOW clock edge.
A single recirculate control (RC) on each chip determines
whether the registers on that chip are to write data in from
the data inputs or recirculate the data appearing on the
output. If RC is LOW, new data is written in; if RC is HIGH
then the data on the output will be written back into the
register input on the next clock pulse.
LOGIC SYMBOLS
RC
INA
IN B
IN C
IN 0
CP
13
S
11
9
14
OUT A
Am40SS/SOSS
QUAD 128-B IT
SHIFT REGISTER
OUT B
12
OUTC
aUTO
VSS = Pin 8
VDD = Pin 16
VGG = Pin 10
10
RC
IN A
OUT A
Am40S6/S0S6
DUAL 256-BIT
SHIFT REGISTER
IN B
CP
VSS = Pin 5
VDD = Pin 9
OUT B
VGG = Pin 7
RC
IN
A,n40S7/S0S7
512-BIT SHIFT REGISTER
VSS" Pin 11
VDD w Pin 0
OUT
CP
VGG
= Pin
G
MOS·450
LOGIC BLOCK DIAGRAM
(One Register Shown)
n-BIT STATIC
SHIFT REGISTER
CLOCK
OUT
1---4>---1 >---
OUT
- - 1 - - - - - - -....
Am4055/5055
Am4056/5056
Am4057/5057
TO OTHER
REGISTERS
n = 128
n = 256
n=512
MOS·451
ORDERING INFORMATION
CONNECTION DIAGRAMS
Am4055/5055
Am40S6/S056
RC
Package
Type
16-Pin Molded DIP
16·Pin Hermetic DIP
16·Pin Hermetic DIP
Temperature
Range
O°C to +70°C
O°C to +70°C
-SSoC to +12SoC
Order
Number
TO-100 Can
TO-100 Can
O°C to +70°C
-SSoC to +12SoC
MMSOS6H
MM40S6H
INC
NC
INO
8-Pin Molded DIP
8-Pin Hermetic DIP
8·Pin Hermetic DIP
O°C to +70°C
O°C to +70°C
-SSoC to +12SoC
MMSOS7N
MMSOS7D
MM40S7D
aUTO
VGG
RC
INA
MMSOSSN
MMSOSSD
MM40SSD
NC
OUT B
VOO
NC
QUTA
IN B
VSS
VSS
OUTC
CP
Am4057/5057
RCDs
2
7
NC
OUT
3
6
VGG
Vss
4
S
CP
-
5-53
Voo
IN
MOS·452
m
Am40/50S5 - Am40/5056 -Am40/S057
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
VDD Supply Voltage
Vss -10V to Vss +0.3 V
V GG Supply Voltage
Vss -20V to Vss +0.3V
DC Input Voltage
Vss -20V to Vss +0.3V
OPERATING RANGE
Part Number
Ambient Temperature
Vss
-Sso C to +12So C
5.0V ±S%
OV
-12V ±S%
S.OV ±S%
OV
-12V ±S%
VDD
Am40S5
Am40S6
Am40S7
AmSOS5
AmS056
O°C to +70°C
.AmS057
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Typ.
Parameters
Description
Test Conditions
Min.
VOH
Output HIGH Voltage
IOH =-O.SmA
VOL
Output LOW Voltage
IOL = 1.6mA
Input HIGH Level
Guaranteed input logical HIGH voltage 1405S/6/7
for all inputs
15OSS/617
VIL
Input LOW Level
Guaranteed input logical LOW voltage
for all inputs
IlL
Input Leakage Current
VIN = -10.0V, all other pins GND.
TA = 2SoC
VIH
IDD
VDD Power Supply Current
IGG
VGG Power Supply Current
Note: 1. Typical Limits are at VSS
= 5.0V,
VGG
(Note 1)
Max.
Volts
Volts
0.4
VSS-l.0
VSS+0.3
VSS-1.5
VSS+0.3
VSS-18.S
VSS-4.2
Volts
p.A
0.01
O.S
TA = 2SoC.
f
~
2.2MHz
lS.0
20.0
t-
III
G
IJ:
0
~U
25°cl
I-~
12n
":so.5 )J
A1l
JI
1k
10k
lOOk
VGG' -1~~V
1M
CLOCK FREQUENCY-Hz
~
z
i=
~
ov
10M
/,,/
V
. / ....... f'
0
~
;t
1
VOO"
l/
I
r1l
~
I-~
C
. . . r-....K..
Vss = +5.0V
20
---
"
i" ~
1.5
E
150
-
-
'X
V l/
V
./ ../r,l>'
'" ./
Vss
'"
100
-55 -35 -15
= +5.0V
= OV
= -12.0V
Voo
VGG
5
25
45
65 85 105125
AMBIENT TEMPERATURE _ °c
MOS-454
EFINITION OF TERMS
SET-UP and HOLD TIMES The shift register will accept the data
that is present on its input around the time the clock goes from
HIGH-to-LOW. Because of variations in individual devices, there
is some uncertainty as to exactly when, relative to this clock
transition, the data will be stored_ The set-up and hold times
define the limits on this uncertainty_ To guarantee storing the
correct data; the data inputs should not be changed between
the maximum set-up time before the clock transition and the
maximum hold time after the clock transition. Data changes
within this interval mayor may not be detected_
'ATlC SHIFT REGISTER A shift register that is capable of
lintaining stored data without being continuously clocked.
)st static shift registers are constructed with dynamic master
:l static slave flip-flops_ The data is stored dynamically while
l clock is HIGH and is transferred to the static slaves while the
·ck is LOW_ The clock may be stopped indefinitely in the LOW
te, but there are limitations on the time it may reside in
! HIGH state_
5-55
Am40/5055 • Am40/5056 • Am40/5057
Metallization and Pad Layouts
Am4055/5055
RC
Am4056/5056
VOO
16
RC
10
14 OUT A
9 Voo
-==r:;I;;II;I~
IN AB 2
OUT
4 -
INA
1
OUT A
2
13 IN B
12 OUT C
IN C
5
IN B
3
OUT 0
7
OUT B
4
11
9
IN 0
10
5
CP VGG
Vss
Am4047/5057
IN
2
OUT
3
DIE SIZES 0.101" X 0.140"
5-56
6
7
CP VGG
Am9401/Am2401
Dua11024-Bit Dynamic Shift Register
Disti nctive Characteristics
FUNCTIONAL DESCRIPTION
The Am9401 is a dual 1024·bit dynamic shift register built
using ion·implanted, N·channel, silicon gate MOS technology. The device operates from a single +5 volt power
supply and all inputs and outputs, including the clock, are
directly TTL compatible. Data is entered into the register
on the LOW-to·HIGH transition of the clock input. New
data appears on the output following the HIGH·to·LOW
clock transition. There are two chip select inputs, CS x and
CS y ; if either is HIGH then the data in both registers
recirculates and the outputs go to a HIGH impedance OFF
state. If both chip selects are LOW, then the outputs will be
LOW for LOW data and OFF for HIGH data (similar to TTL
open collectors). When the chip is selected, the writerecirculate lines control the entry of new data. If W/R is
HIGH new data is written into the corresponding register; if
W/R is LOW, the data on the output is recirculated. An
internal pull-up resistor to Vee is provided at RL' This
point may be connected to the output to establish the
HIGH logic level. Many register outputs may be connected
together with the RL connected only once. The Am9401 is
a high performance plug·in replacement for the Am2401.
• Single +5V power supply
• High speed - 2 MHz min.
• Single phase TTL clock
• Low clock capacitance - 7.0 pF max.
• Low Power
315 mW max. @ 2MHz
40 /lW/bit typo @ 2 MHz
• Chip select, write, and recirculate logic on chip
• 100% reliability assurance testing in accordance with
MI L·STD·883
LOGIC SYMBOL
12
IN 1
W/R 1
W/R 2
OUT 1
15
11
14
13
Vee = Pin 16
GND=Pin8
MOS·455
LOGIC BLOCK DIAGRAM
1.3k!l
NOMINAL
IN
1024-BIT
SHIFT REGISTER
INo------------------r-4
OUT
CP O - - - - - - - - - - - - - - - - r - - - - - - _ - - - - - - - - f CLOCK
W/R
0------------1
TO SECOND REGISTER
Note: Only one register shown.
MOS·456
ORDERING INFORMATION
CONNECTION DIAGRAM
Top View
OUT 1
Package
Type
Temperature
Range
Order
Number
Order
Number
IN 2
IN 1
OUT 2
W/R 1
O°C to +70°C AM9401PC P2401
16·Pin Molded DIP
16-Pin Hermetic DIP
0°Cto+70°C AM9401DC C2401
16·Pin Hermetic DIP -55°Cto +125°C AM9401DM
VCC
RLl
CSx
RL2
W/R 2
CSy
CP
NC
NC
GND
NC
Note: Pin 1 is marked for orientation.
5-57
MOS·457.
Am9401/Am2401
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
Power Dissipation
1W
Voltage on Any Pin
-O.5V to +7 .OV
OPERATING RANGE
Ambient Temperature
Part Number
VCC
Am9401. 2401PC. DC
Am9401DM
Parameters
Description
Conditions
Input Leakage Current
VIN
ILO
Output Leakage Current
VOUT
ICC
VCC Current
VCC ':' MAX.
80% Duty Cycle
Input HIGH Level
= 25°C
TA
= O°C to
TA
= _55°C to +125°C
VIL
Input LOW Level
Output LOW Current
VOL
VOL
Output LOW Voltage
IOL
= 1.6mA, RL connected
VOH
Output HIGH Voltage'
IOH
= -1mA, RL connected
RL
Internal Load Resistor
Typical values are at 25°C and VCC
+70°C
f max
6.3
Description
Minimum Data and Clock Rate
Clock LOW Time
tcppw(H)
Clock HIGH Time
t r • tf
Clock Rise and Fall Times
ts
Data and Control Set-Up Time
th
Data and Control Hold Time
tpd
Note: 2. CL
Delay, Clock or Chip Select to Output
= 20pF
10
10
/.I A
100
100
/.I A
70
50
60
0.65
Volts
0.65
-0.3
6.3
10
mA
80
Volts
mA
0.45
0.45
Volts
2.4
VCC
2.4
VCC
Volts
0.5
3.0
0.5
3.0
kn
1.5
Am2401
Typ.
Conditions
Min
(Note 1)
Am9401
Max
Min
Typ
1.0
Max
Units
2.0
MHz
TA
= 25°C
= O°C to +70°C
= -55°C to +125°C
= O°C to +70°C
TA
= -55°C
TA
= 25°C
0.2
1000
0.1
1000
TA
= O°C
0.2
40
0.1
40
TA
= -55°C to
0.1
1.0
TA
1.0
1.0
25
25
kHz
100
0.8
10
10
0.4
I---
to +125°C
to +70°C
+125°C
50
50
200
80
150
150
= 1OOpF.
Load
250
= 1 TTL gate
500
/.IS
ns
ns
ns
RL connected (Note 2)
CL
/.IS
9
160
320
Note 2
ns
for Am9401. The capacitive load is limited primarily by the internal load register.
CAPACITANCE (T A
=
Parameters
Description
CIN
Units
2.2
Maximum Data and Clock Rate
TA
tcppw(L)
Max.
= 5.0V.
TA
fmin
Typ.
50
-0.3
= 0.45V
Min.
80
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Parameters
Max.
2.2
IOL
Note: 1.
(Note 1)
= 5.25V
TA
VIH
Min.
= 5.25V
III
Am9401
Am2401
Typ.
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Am2401
25°C)
Conditions
Capacitance, All Data Inputs
f
Crt>
Capacitance, Clock Input
COUT
Capacitance, Data Output
= 1 MHz,
VIN
Min.
Am9401
Typ.
Max.
Min.
Typ.
Max.
Units
4.0
7.0
4.0
7.0
pF
4.0
7.0
4.0
7.0
pF
10
14
5.0
10
pF
= 250mV
All Pins at RL Ground
5-58
Am9401/Am2401
SWITCHING WAVEFORMS
'1'
/---t.ppwILI
:: t
CP
V IH
DATA IN
W/R
CS
V IL
t.ppwIHI----j
tI
f
r-tS+th~
I
1.5V
g
~
'f:tI;f;fII;IJ.
1.5V
f-tpd-j
f-tpdj
,~ -'" "'' "\\\'t
DATA OUT
ICS= LOWI
f
lTl
111
VOL
t
SEE NOTE
1.5V
Note: HIGH level on output is established by externally connected load resistor.
MOS-458
TYPICAL PERFORMANCE CHARACTERISTICS
Power Supply Current !lcd
Versus Data Rep. Rate
60
CONST~NT
50
).V""", ~
lOOk
1M
-
I I I
-
14
12
.9
10
...J
f0o-
- - DATA=O
- - - DATA = 1
10k
~
OL
-
..J
I
PULSE
WIDTH = 400ns
I
0
lk
_
:: r-
~ ..........
pw = 400n,
VCC = 5.25V
.5:'
1""'"":---'"
I
4
-50 -25
Power Supply Current !lcd
Versus Ambient Temperature (DOC)
55
~
~"'5.<5J
\lc~. 5\1
DATA REP RATE - Hz
60
~VOL =0.45V-
221-1
II
...J
-v
V'
-- -'-
~/
20
24
CONSTANT
DUTY
r-- CYCli= 80%
_
PULSE
WIDTH= lOllS /
40
Temperature Dependence of
Output LOW Level Sink Capability
-<
I
-e.
0
lOOms
60
10
30
50
20
40
AMBIENT TEMPERATURE _ °c
70
MOS-459
TRUTH TABLE
W/R
CSx
CSy
DIN
DATA ENTERED
OUTPUT
OPERATION
OFF
OFF
Deselected, Recirculate
Deselected, Recirculate
DIN (t-1024)
DIN (t-1024)
DIN (t-1024)
Read, Write
Read, Write
Read, Recirculate
X
X
H
X
X
H
X
X
H
H
L
L
H
L
L
L
L
L
DIN (t-1024)
DIN (t-1024)
LOW
HIGH
X
DIN (t-1024)
L
5-59
Am9401/Am2401
APPLICATIONS
R/W----------~--------_+--1_----------------~~~----------------.__+----------------~~~
DO----------r---~----_+--~----------~----_r--r_----------._----+__+----------_,
°1----------r-~~----_+--~--------_+~----_r--~--------~+_----+__+--------__,
y2~_r_r~------------------~------------------__i
y3P--r-+--------------------~--------------------+_------------------~
°2------------+_~----_+--~------~--~----_r--~------_+--._----+__+--------~_,
°3------------~~----_+--~------~~~----_r--~------_+~+_----+__+--------_r,
/
4k x4 REGISTER ARRAY
Eight Am2401's form this 16k register array. Data inputs (00-03) and data outputs (00-03) may be
connected directly to TTL. Note that the load resistors are only connected once to each line. A pair of
devices (a 1 k x 4 section) is selected by address bits AO and A1. The data in the selected devices are read
out and, if RM is LOW, updated with new data. All clock lines are driven from TTL levels.
Metallization and Pad Layout
OUTI
1 ____________- ,
, - - - - - - - - - - - - - - - 16
Vee
IN 2
OUT 2
IN 1
3
CS x
5
CS y
6--~~~~~~__
L ____~-=---------~
GND
DIE SIZE 0.133" X 0.142"
5-60
MOS-460
First-In First-Out Memory
NUMERICAL INDEX
Page
Am2812/2812A
Am2813/Am2813A
Am2841/3341/
2841A
32 x 8 First-In First-Out Memory ............................................ 6-1
32 x 9 First-In First-Out Memory ............................................ 6-1
64 x 4 First-In First-Out Memory ............................................ 6-7
/
Am2812/ Am2812A • Am2813 I Am2813A
32x8 and 32x9 First-In First-Out Memories
Distinctive Characteristics
• Completely independent read and write operations
• "Half-full" flag
• Am2812 has serial or parallel input and output
• Data rates up to 1 MHz
FUNCTIONAL DESCRIPTION
LOGIC SYMBOLS
The Am2812 and Am2813 are 32 word by 8-bit and 9-bit
first-in first-out memories, respectively. Both devices have completely independent read and write controls and have threestate outputs controlled by an output enable pin (OE). Data
on the data inputs (Di) are written into the memory by a pulse
on load (PL). The data word automatically ripples through
the memory until it reaches the output·or another data word.
Data is read from the memory by applying a shift out pulse
on PD. This dumps the word on the outputs (OJ) and the next
word in the buffer moves to the output. An output ready signal (OR) indicates that data is available at the output and also
provides a memory empty signal. An input ready (I R) signal
indicates that the device is ready to accept data and also provides a memory full signal. Both the Am2812 and Am2813
have master reset inputs which clear all data from the device
(reset to all LOWs), and a FLAG signal which goes HI GH when
the memory contains more than 15 words.
11
1
28
27
26
9
10
12
13
23
22
21
14
15
3
20
18
25
= Pin 24
= Pin 16
VGG = Pin 2
Vss
VOO
10
OE
28
27
26
23
22
21
20
17
18
The Am2812 can perform input and output data transfer on a
bit-serial basis as well as on 8-bit parallel words. The input
buffer is in reality an 8-bit shift register which can be loaded in
parallel by the P L command or can be loaded serially through
the DO input by using the SL clock. When 8 bits have been
shifted into the input buffer serially, the 8-bit word automatically moves in parallel through the memory. The output
includes a built-in parallel-to-serial converter, so that data can
be shifted out of the 07 output by using the SO clock. After
8 clock pulses a oew 8-bit word appears at the outputs.
11
12
13
Am2813
9X32FIFO
14
15
3
25
= Pin 24
= Pin 16
VGG = Pin 2
VSS
19
VOO
MOS-461
CONNECTION DIAGRAMS
Top Views
Am2812
The timing and function of the four control signals, PL, I R, PO,
and OR, are designed so that two FIFOs can be placed end to
end, with 0 R of the first driving PL of the second and I R of the
second driving PO of the first. With this simple interconnection,
strings of FIFOs can control each other reliably to make a
FI.FO array any number of words deep.
ORDERING INFORMATION
DO VGG OR
MR
PD
SD
00
Q,
Q2
Q3
OE
Q4
Q5
Q6
Am2813
Package
Type
Frequency
Temperature
Range
Hermetic DIP
Hermetic DIP
Hermetic DIP
Hermetic DIP
Hermetic DIP
Hermetic DIP
500KHz
500KHz
1MHz
1MHz
500KHz
1MHz
O'C to +70'C
-55'C to +85'C
O'C to +70'C
-55'C to +85°C
- 55'C to + 125°C
-55'C to +125°C
Am2812
Order
Number
Am2813
Order
Number
AM2812DC
AM2812DL
AM2812ADC
AM2812ADL
AM2813DC
AM2813DL
AM2813ADC
AM2813ADL
AM2813DM
AM2813ADM
Note: Pin 1 is marked for orientation.
6-1
MOS-462
Am2812/Am2812A • Am2813/Am2813A
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
VDD Supply Voltage
Vss -7V to Vss +0.3V
VGG Supply Voltage
Vss -20 V to Vss +0.3 V
DC Input Voltage
Vss -10V to Vss +0.3V
OPERATING RANGE
Part Number
Ambient Temperature
Vss
Voo
VGG
O°Cto +70°C
5.0V:t5%
OV
-12V:t5%
-55°C to +85°C
5.0V:t5%
OV
-12 :t5%
-55°C to +125°C
5.0V:t5%
OV
-12V:t5%
Am2812DC, Am2812ADC
Am2813DC, Am2813ADC
Am2812DL, Am2812ADL
Am2813DL, Am2813ADL
Am2813DM, Am2813ADM
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Typ.
Parameters
Description
Test Conditions
VOH
Output HIGH Voltage
IOH
VOL
Output LOW Voltage
IOL
VIH
Input HIGH Level
VIL
Input LOW Level
IlL
Input Leakage Current
VIN
IIH(Note 2)
Input HIGH Current
VIN
VPUP
Input Pull·up Initiation Voltage
VBAR
Voltage at Peak Input Current
IBAR
Maximum Input Current
IGG
IDD
VGG Current (Note 5)
VDD Current
Min.
= .300mA
= 1.6mA
(Note 1)
Max.
Units
V
Vss -1.0
V
0.4
V
VSS -1.0
= OV
= VSS
(Note 2)
(Note 2)
-1.0V (Note 2)
I
VSS
I
VSS
IlA
IlA
2.0
(Note 2)
= O°C
V
1.0
250
= MIN.
= MAX.
(Note 2)
TA
0.8
to +70°C
V
VSS -1.5
V
1.6
mA
14
22
30
45
T A - -55°C to +85°C
V
2.2
mA
27
= O°C to +70°C
TA = -55°C to +85°C
TA
mA
55
Notes: 1. Typical limits are at VSS = 5.0V, VGG = -12.0V, T A = 25° C
2. Pull up circuit on Am2813 only. See graph of input V-I characteristics.
3. Am2813ADM and Am2813ADM: IGG is guaranteed for T A = -55°C to +125°C
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Parameters
Conditions/Note
Test Conditions
Am2812/Am2813
Min.
Typ.
Max.
Am2812A/Am2813A
Min.
Typ.
Max.
Units
1.0
MHz
fp
Maximum Parallel Load or Dump Frequency
0.5
tlR+
Delay. PL or SL HIGH-to IR In·Active
100
300
1100
80
300
450
tlRtpwH(P)
Delay. PL or SL LOW to IR Active
100
250
800
80
250
400
Minimum PL or PD HIGH Time
100
100
80
ns
tpwL(P)
Minimum PL or PD LOW Time
tpwH(S)
Minimum SL or SD HIGH Time
Am2812 only
tpwH(P)
tpwL(P)
tpwL(S)
Minimum PL or PD HIGH Time
Minimum PL or PD LOW Time
Minimum SL or SO LOW Time
Am2813ADM Only
Am2813ADM Only
Am2812 only
th(O)
Data Hold Time
ns
ns
100
100
80
ns
350
350
300
ns
200
ns
200
300
ns
ns
350
350
190
170
300
250
a
a
to PL
ns
ts(O)
Data Set·Up Time
tOR+
Delay. PD or SD HIGH to OR LOW
OE HIGH
100
450
1100
100
350
520
ns
tOR-
Delay. PD or SD LOW to OR HIGH
OE HIGH
100
400
850
100
300
470
ns
8
IlS
50
200
50
200
a
100
a
100
to SL
100
90
ns
tPT
Ripple through Time
FIFO Empty
tDH
Delay. OR LOW to Data Out Changing
PD
tDA
Delay. Data Out to OR HIGH
tMRW
Minimum Reset Pulse Width
600
500
tDO
Delay. OE LOW to Output OFF
600
500
ns
tEO
Delay. OE HIGH to Output Active
600
500
ns
tDF
Delay from PL or SL HIGH to Flag HIGH
or PD or SD HIGH to Flag LOW
1.0
IlS
CI
Input Capacitance
7
pF
Notes:
10
= LOW
PD = HIGH
0,5
1.0
7
3.
0.5
ns
ns
ns
I R is active HI G H on Am2813 and active LOW on Am2812.
4. Minimum and maximum delays generally occur at opposite temperature extremes. Devices at approximately the same temperature will have
compatible switching characteristics and will drive each other.
.
6-2
Am2812/Am2812A • Am2813/Am2813A
TIMING DIAGRAM
AT LEAST tpwH
1.5V
PLor SL
INPUT READY
(lR)
---t------
1.5V
90%
Note: IR inverted on Am2812.
POor SO
OUTPUT READY
IORI
1.5V
DATA OUT
MOS·.c66
KEY TO TIMING DIAGRAM
USER NOTES
1. When the memory is empty the last word read will remain on
th~ outputs until' the master reset is strobed or a new data
word falls through to the output. However, OR will remain
LOW, indicating data at the output is not valid.
WAVEFORM
2. When the output data changes as a result of a pulse on PD, the
OR signal always goes LOW before there is any change in
output data and always stays LOW until after the new data
has appeared on the outputs, so anytime OR is HIGH, there
is good, stable data on the outputs.
_ _ MAY CHANGE
FROM HTOL
WILL BE
CHANGING
·FROM H TO L
..!IffJJ"MAYCHANGE
FROM L TO H
WILL BE
CHANGING
FROM L TO H
3. If PD is held HIGH while the memory is empty and a word
is written into the input, then that word will fall through the
memory to the output. OR will go HIGH for one internal
cycle (at least tOR+) and then will go back LOW again. The
stored word will remain on the outputs. If more words are
written into the FIFO, they will line up behind the first word
and will not appear on the outputs until PD has been brought
LOW.
4. When the master reset is brought LOW, the control register
and the outputs are cleared. fA goes HIGH and OR goes LOW.
If PLis HIGH when the master reset goes HIGH then the data
on the inputs will be written into the memory and iR will
return to the HIGH state until PL is brought LOW. If PL is
LOW when the master reset is ended, then iR will go LOW
but the data on the inputs will not enter the memory until
PLgoes HIGH.
5. The output enable pin inhibits dump commands while it is
LOW and forces the Q outputs to a high impedance state.
6. The serial load and dump lines should not be used for interconnecting two F I FOs. Use the parallel interconnection instead.
7. If less than eight bits have been shifted in using the serial load
command, a parallel load pulse will destroy the data in the
partially filled input register.
6-3
_
INPUTS
OUTPUTS
MUST BE
STEADY
WILL BE
STEADY
DON'T CARE:
ANY CHANGE
PERMITTED
CHANGING:
STATE
UNKNOWN
Pull-up Characteristic Input
Versus Input Voltage
~
Current
E -2.5
I
I-
z
~ -2.0
~
u
---c
CONTROL
LOGIC
-
Or-
'-- S
-
Co
,R
MR
0-
~s
op.
,R
MR
0--
~s
C,
00-,R
"'"-----
MR
01-1-
~r-S
C63
C62
00-
'-R
MR
op-
LL- ----<
SO
CONTROL
LOGIC
OR
-
---
-::::
M05·469
CONNECTION DIAGRAM
Top View
ORDERING INFORMATION
vGG
Package
Type
Temperature
Range
aOc to +70°C
Molded DIP
aOc to +70°C
Hermetic DIP
Hermetic DI P -55°C to +125°C
Am3341
Order
Number
AM3341PC
AM3341 DC
Am2841
Order
Number
Am2841A
Order
Number
AM2841PC
AM2841DC
AM2841DM
AM2841APC
AM2841ADC
IR
VSS
so
SI
OR
DO
00
0,
a,
O2
O2
03
°3
V OD
MR
Note: Pin 1 is marked for orientation.
M05·470
6·7
Am2841/3341/2841A
MAXIMUM RATING (Above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
VDD Supply Voltage
Vss -7V to Vss +O.3V
VGG Supply Voltage
Vss -20V to Vss +O.3V
DC I nput Voltage
Vss -1 OV to Vss +O.3V
OPERATING RANGE
Part No.
Ambient Temperature
VSS
VDD
Am3341PC, DC
Am2841PC, DC
o
O°C to +70 C
+5.0 ±5%
GND
-12.0 ±5%
+5.0 ±5%
GND
-12.0 ±5%
Am2841 APC, DC
Am2841DM
-55°C to +125°C
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Typ.
Parameters
Description
Conditions
VOH
Output HIGH Voltage
10H
= .300mA
10L
=
VOL
Output LOW Voltage
VIH
Input HIGH Level
VIL
Input LOW Level
IlL
Input Leakage Current
VIN
IIH
Input HIGH Current
VIN
Min.
(Note 1)
Max.
Units
0.4
Volts
0.8
Volts
1.0
J.LA
2.0
Volts
Volts
VSS -1.0
1.6mA
Volts
VSS -1.0
= OV
= VSS -1.0V
VSS
I
j
250
J.LA
= MIN.
= MAX.
VPUP
Input Pull·up Initiation Voltage
(Note 2)
2.2
Volts
VBAR
Voltage at Peak Input Current
(Note 2)
VSS -1.5
Volts
IBAR
Maximum Input Current
(Note 2)
1.6
mA
IGG
VGG Current
IDD
VDD Current
TA
TA
TA
TA
Notes: 1. Typical limits are at VSS = 5.0V, VGG
2. See graph of input V-I characteristics.
= -12.0V,
TA
VSS
= O°C to +70°C
= -55°C to +125°C
= O°C to +70°C
= -55°C to +125°C
7
12
mA
16
30
45
mA
60
= 25°C
SWITCHING CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Parameters
Definition
f max
Maximum Sl or SO
Frequency
Test Conditions
Min.
Am3341
Typ. Max.
0.75
Min.
Am2841
Typ. Max.
1.0
Min.
Am2841A
Typ. Max.
Units
MHz
1.2
tlR+
Delay. Sl HIGH to IR LOW
90
250
550
80
400
80
350
ns
tlR-
Delay. Sl LOW to IR HIGH
138
275
550
100
550
100
450
ns
tOV+
Minimum Time SI and
IR both HIGH
100
80
tov-
Minimum Time SI and
IR both LOW
100
80
80
ns
tDSI
Data Release Time
400
200
200
ns
tDD
Data Set-up Time
25
tOR+
Delay. SO HIGH to OR LOW
90
250
500
70
200
450
80
200
370
tOR-
Delay. SO LOW to OR HIGH
170
350
850
70
200
550
70
200
450
ns
tpT
Ripple through Time
FIFO Empty
10
32
8
16
8
16
J.LS
tDH
Delay. OR LOW to Data Out
SO = LOW
tMRW
Minimum Reset Pulse Width
tDA
Delay, Data Out to OR HIGH
CI
Input Capacitance (Except
MR)
7
7
7
pF
CMR
Input Capacitance MR
15
7
7
pF
80
0
0
75
0
30
ns
400
0
400
0
20
ns
ns
75
75
400
SO = HIGH
ns
20
ns
ns
Note: Switching times over the entire temperature range are such that two devices at approximately the same ambient temperature can drive each other.
6-8
A,m2841/3341/2841A
TIMING DIAGRAM
SHIFT IN
(511
INPUT READY
(lRI
1.5V
1--------tDSI-----~~
SHIFT DUT
(501
OUTPUT READY
(ORI
tOR+
I------MAX.-------I
DATA OUT
(00-0 31
'"fmfifr'
USER NOTES
1. When the memory is empty the last word read will remain on
the outputs until the master reset is strobed or a new data
word falls through to the output. However, OR will remain
LOW, indicating data at the output is not valid.
2. When the output data changes as a result of a pulse on SO, the
OR signal always goes LOW before there is any change in
output data and always stays LOW until after the new data
has appeared on the outputs, so anytime OR is HIGH, there
is good, stable data on the outputs.
3. If SO is held HIGH while the memory is empty and a word
is written into the input, then that word will fall through the
memory to the output. OR will go HIGH for one internai
cycle (at least tOR+) and then will go back LOW again. The
stored word will remain on the outputs. If more words are
written into the FIFO, they will line up behind the first word
and will not appear on the outputs until SO has been brought
LOW.
4. When the master reset is brought LOW, the control register
and the outputs are cleared. I R goes HIGH and OR goes LOW.
If SI is HIGH when the master reset goes HIGH then the data
on the inputs will be written into the memory and I R will
return to the LOW state until SI is brought LOW. If SI is
LOW when the master reset is ended, then IR will go HIGH,
but the data on the inputs will not enter the memory until
SI goes HIGH.
6-9
MOS-471
Am2841/3341/2841 A
«
Pull-up Characteristic Input
Current Versus Input Voltage
E -2.5
I
I-
~
-2.0
c::
~
U
0.
~
-1.5
I,MAX.-I-
j
i2
i2
I-
0°'11
-1.0 - I - 25°C--.
I
o
~W'
W
YJJ
!': -0.5
~
o
1.0
2.0
~\
'~1
70°C~
\
V
3.0
4.0
5.0
60
V IN - INPUT VOLTAGE - VSS
MOS·472
The data falling through the register stacks up at the output end.
At the output the last control register bit is buffered and brought
out as Output Ready (OR). A HIGH on OR indicates there is a
"1" in the last control register bit and therefore there is valid
data on the four data outputs 00-03. An input signal, shift out
(SO)' is used to shift the data out of the FIFO. A LOW-to-HIGH
transition on SO clears the last register bit, causing 0 R to go
LOW, indicating that the data on the outputs may no longer be
valid. When SO goes LOW, the "0" which is now present at the
last control register bit allows the data in the next to the last
register to move into the last register position and on to the
outputs. The "0" in the control register then "bubbles" back
toward the input as the data shifts toward the output.
DESCRIPTION OF THE Am3341 FIFO OPERATION
The Am3341 FIFO consists internally of 64 four-bit data registers
and one 64-bit control register, as shown in the logic block
diagram. A"l" in a bit of the control register indicates that a
four-bit data word is stored in the corresponding data register. A
"0" in a bit of the control register indicates that the corresponding data register does not contain valid data. The control
register directs the movement of data through the data registers.
Whenever the nth bit of the control register contains a "1" and
the (n+1 )th bit contains a "0", then a strobe is generated causing
the (n+1 lth data register to read the contents of the nth data
register, simultaneously setting the (n+1 )th control register
bit and cleari ng the nth control register bit, so that the control
flag moves with the data. In this fashion data in the data register
moves down the stack of data registers toward the output as long
as there are "empty" locations ·ahead of it. The fall through operation stops when the data reaches a register n with a "1" in the
(n+1 )th control register bit, or the end of the register.
If the memory is emptied by reading out all the data, then when
the last word is being read out and SO goes HIGH, OR will go
LOW as before, but when SO next goes LOW, there is no data
to move into the last location, so OR remains LOW until more
data arrives at the output. Similarly, when the memory is full
data written into the first location will not shift into the second
when 51 goes LOW, and IR will remain LOW instead of returning
to a HIGH state.
Data is initially loaded from the four data inputs 00-03 by
applying a LOW-to-HIGH transition on the shift in (51) input.
A "1" is placed in the first control register bit simultaneously.
The first control register bit is returned, buffered, to the input
ready (I R) output, and this pin goes LOW indicating that data has
been entered into the first data register and the input is now
"busy", unable to accept more data. When 51 next goes LOW,
the fall-through process begins (assuming that at least the second
location is empty). The data in the first register is copied into
the second, and the first control register bit is cleared. This
causes IR to go HIGH, indicating the inputs are available for
another data word.
The pairs of input and output control signals are designed so that
the SO input of one FIFO can be driven by the I R output of
another, and the OR output of the first FIFO can drive the 51
input of the second, allowing simple expansion of the FIFO to
any depth. Wider buffers are formed by allowing parallel rows of
FI FOs to operate together, as shown in the application on the
last page.
An over-riding master reset (MR) is used to reset all control
register bits and remove the data from the output (i. e. reset the
outputs to all LOW).
6-10
Am2841/3341/2841 A
~~IIII[[I~
51
7
50
L---
Co
Co
Co
Co
Co
Co
80
C,
C,
C,
C,
C,
C,
8,
AO
Al
C2
C2
C2
C2
C2
C2
82
A2
C3
C3
C3
C3
C3
C3
83
A3
51
---L
50
_--L
L~H-L--_
1
I CJ
~H
INITIAL CONDITION
FIFO empty, SI LOW IR HIGH, word "A" on inputs.
2
Word "C" written in same manner, and so on. When buffer is full,
all control bits are 1's and I R stays LOW.
~~~;IIII [[[~
51
L-H--_
8
L!LT'~0-LI_0~1_0-L1_0~1_°-L1o~I~€l~
3
AO
AO
Al
Al
A2
A3
FO
EO
DO
Co
80
F,
E,
D,
C,
B,
Al
H2
G2
F2
E2
D2
C2
B2
A2
H3
G3
F3
E3
D3
C3
B3
A3
L
~
IR
OR
= delay) I R goes LOW
9
DO
Co
80
D,
C,
8,
"2
D2
C2
B2
A3
D3
C3
83
o
olol~
OR
L
L
Release data into FI FO by lowering SI. After delay, data moves to
second location, and IR goes HIGH indicating input available for
new data word.
AO
AO
AO
AO
AO
AO
AO
AO
Al
Al
Al
Al
Al
Al
Al
Al
A2
A2
A2
A2
A2
A2
A2
A3
A3
A3
A3
A3
A3
A3
I 1 I 1 1,
I
ClSSl
~C"_j~~A,-.....
~
HO
HO
HO
Go
FO
Eo
Do
Co
HI
HI
G,
F,
E,
D,
C,
A2
H2
H2
H2
G2
F2
E2
A3
H3
H3
H3
G3
F3
E3
10
_5_0_
L-H
When SO goes LOW, the "0" in the last control bit bubbles toward
the memory input. OR goes HIGH as the new word arrives at the
output. I R goes HIGH when "0" reaches input.
HI
L -SI- -
t::..H-L
FIRST READ OPERATION
SO goes HIGH, indicating "Ready to Read". OR then goes LOW
indicating "Data Read".
50
_--L
4
AO
~I~I_l-L1_'~I_'_I~'~1_l_IL1~ll~_~~0
~L
Write input into first stage by raising SI. (Ll
indicating data has been entered.
Go
G,
L -51- -
_5_0_ L
A.H-L~
HO
HI
51
L---
L
lil~J
H~
~L-H
H
~L;..o~l....:o--Ll...:..l~l...:.....:..l~1....:'_IL...:..'....1I....:'--,-1T'L...J
OR
H-L-H
f-----164 BITS)---------j
Data spontaneously 'ripple through registers to end of FIFO, causing
OR to go HIGH. The time required for data to fall completely
through the FI FO is the "Ripple-through Time".
Read word "S" out, word
5
BO
AO
AO
AO
AO
AO
AO
AO
8,
Al
Al
Al
Al
Al
Al
Al
82
A2
A2
A2
A2
A2
A2
A2
83
A3
A3
A3
A3
A3
A3
A3
11
_5_1_
50
---L
"e" moves to output, and so on.
HD
HO
HO
HO
HO
HO
HO
HO
H,
H,
HI
H,
H,
H,
HI
HI
H2
H2
H2
H2
H2
H2
H2
H2
H3
HJ
HJ
HJ
HJ
HJ
H3
H3
50
- - - L--H--L
Read word "H". OR stays LOW because FI FO is empty. Word
"H" remains in output until new word falls through.
Word "S" written into FIFO
6
H-L _5_1_
80
80
80
80
80
80
80
8,
8,
8,
8,
8,
8,
8,
AO
Al
82
82
82
82
82
82
82
A2
83
83
83
83
83
83
83
A3
_5_0_ L
SI goes LOW allowing word "S" to fall through.
MOS-480
6-11
Am2841/3341/2841A
APPLICATION
DO
01
02
03
00
01
02
03
DO
Dl
D2
D3
51
IR
OR
SO
DO
Dl
00
01
02
03
DO
Dl
D2
D3
SHIFT
IN
Am3341/Am2841
4X84FIFO
00
01
02
03
DO
Dl
D2
D3
51
IR
OR
SO
51
IR
OR
SO
DO
Dl
00
01
02
03
DO
Dl
00
D3
OR
SO
SI
IR
Am3341/Am2841
4 X 64 FIFO
Am33411 Am2841
4X64FIFD
00
01
02
03
00
01
02
03
SHIFT
OUT
J"-04
DS
Os
07
°2
D3
Am3341/Am2841
4X64FIFO
DR
SO
51
°2
03
Am3341/Am2841
4 X 64 FIFO
51
°2
Am3341/Am2841
4X64FIFO
01
02
03
04
as
06
07
OR
SO
The composite input ready indicates both devices are ready to receive data. The shift in pulse must be
wide enough for all devices to load data under worst case conditions.
8 X 192 FIFO Buffer Using Am3341/Am2841
MOS·473
Metallization and Pad Layout
IR
2
VGG
1
V55
16
50
15
14 OR
513
Do 4
13 Qo
D1 5
12 Q1
D2 6
11 Q2
D3 7
9
MR
126 x 138Mils
6-12
10
Q3
Microprocessors
and
Peripheral Circuits
NUMERICAL INDEX
Am8035
Am8048
Am8080N9080A
Am8085NAm8085A-5/
Am9085ADM
Arn8155
Am8156
Am8251/9551
Am8253/8253-5
Am8255A
Am8255A-5
Am8257/9557
Am8279
Am8279-5
Am9511A
Am9512
Am9513
Am9517A
Am9519A
Single-Chip 8-Bit Microcomputer .................................... 7-1
Single-Chip 8-Bit Microcomputer .................................... 7-1
8-Bit ............................................................. 7-5
Single-Chip 8-Bit N-Channel ....................................... 7-13
2048-Bit Static MOS RAM with I/O Ports and Timer .................. 7-26
2048-Bit Static MOS RAM with I/O Ports and Timer .................. 7-26
Programmable Communications Interface ........................... 7-36
Programmable Interval Timer ...................................... 7-43
Programmable Peripheral Interface ................................. 7-49
Programmable Peripheral Interface ................................. 7-49
Programmable DMA Controller ..................................... 7-54
Programmable Keyboard/Display Interface ........................... 7-62
Programmable Keyboard/Display Interface ........................... 7-62
Arithmetic Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-66
Floating Point Processor ........................................... 7-91
System Timing Controller ......................................... 7-110
Multimode DMA Controller ........................................ 7-135
Universal Interrupt Controller ...................................... 7-149
7
Am 8048/8035
Single Chip a-Bit Microcomputers
DISTINCTIVE CHARACTERISTICS
GENERAL DESCRIPTION
•
•
•
•
•
•
•
•
•
•
•
The Am8048 contains a 1k 8 program memory, a 64 x 8
RAM data memory, 27 I/O lines, and an 8-bit timer/counter in
addition to on board oscillator and clock circuits. For systems
that require extra capability, the Am8048 can be expanded
using. standard memories and Am9080A peripherals. The
Am8035 is the equivalent of an Am8048 without program
memory.
x
8-bit CPU, ROM, RAM, I/O in single package
Single +5V supply
All instructions 1 or 2 cycles
Over 90 instructions: 70% single byte
1K x 8 ROM
64 x 8 RAM
27 I/O lines
Interval timer/event counter
Easily expandable memory and I/O
Single level interrupt
100%. reliability assurance testing to MIL-STD-883
The microprocessor is designed to be an efficient controller.
The Am8048' has extensive bit handling capability 'as 'well as
facilities for both binary and BCD arithmetic. Efficient use of
program memory results from an instruction set consisting'
mostly of single byte instructions and no instructions over two
bytes in length.
CONNECTION DIAGRAM
Top View
BLOCK DIAGRAM
vee
To
T,
XTAL,
XTAL 2
RESET
4
55
5
P 27
P26
P2S
P24
P 17
INT
EA
RD
PSEN
8-BIT
TIMER/EVENT
COUNTER
271/0
LINES
WR
ALE
10
DBa
DB,
12
DB2
14
DB3
15
11
Am8048
Am8035
13
P'6
P,s
P'4
P'3
P'2
P"
P,o
DB4
16
Voo
PROG
DBs
DB6
17
P23
18
DB7
19
P22
P2,
Vss
20
P 20
Note: Pin 1 is marked for orientation.
MOS·164
MOS-163
ORDERING INFORMATION
Package
Type
Ambient Temperature
Specification
Hermetic DIP*
O°C
~
TA
~
+ 70°C
Molded DIP
*Hermetic
= Ceramic = DC = CC = 0-40-1.
7-1
Order Numbers
AM8048DC
AM8048CC
AM8035DC
AM8035CC
AM8048PC
AM8035PC
Am8048/8035
MAXIMUM RATINGS (Above which useful life may be impaired)
Storage Temperature
Ambient Temperature Under Bias
Voltage on Any Pin with Respect to Ground
-O.5V to
+ 7.0V
Power Dissipation
1.5W
The products described by this specification include internal Circuitry designed to protect input devices from damaging accumulations
of static charge. It is suggested nevertheless, that conventional precautions be observed during storage, handling and use in order to
avoid exposure to excessive voltages.
DC AND OPERATING CHARACTERISTICS
TA = 0 to 7Q°C, Vee = voo = +5.0V ±10% (Note 1), Vss = .OV
Limits
Test Conditions
Description
Parameters
Min
Typ
Max
Units
VII:'
Input Low Voltage (All Except RESET, X1, X2)
-.5
.S
Volts
V IL1
Input Low Voltage (RESET, X1, X2)
-.5
.6
Volts
VIH
Input High Voltage (All Except XTAL1, XTAL2, RESET)
2.0
Vee
Volts
VIH1
Input High Voltage (X1, X2, RESET)
3.S
Vee
Volts
VOL
Output Low Voltage (BUS)
VOL
VO L1
Output Low Voltage (RD, WR, PSEN, ALE)
10L
VOL2
Output Low Voltage (PROG)
10L
VOL3
Output Low Voltage (All Other Outputs)
10L
= 2.0mA
= 1.SmA
= 1.0mA
= 1.6mA
VOH
Output High Voltage (BUS)
10H
= -400/LA
2.4
Volts
VO H1
Output High Voltage (RD, WR, PSEN, ALE)
10H
= -100/LA
2.4
Volts
VO H2
Output High Voltage (All Other Outputs)
10H
= -40/LA
2.4
III
Input Leakage Current (T1, INT)
Vss ~ V IN ~ Vee
ILI1
Input Leakage Current (P10-P17, P20-P27, EA, SS)
Vss + .45 ~ VIN ~ Vee
ILO
Output Leakage Current (BUS, TO) (High Impedance State)
Vss + .45 ~ VIN ~ Vee
±10
/LA
100
Voo Supply Current
5
15
rnA
100 + lee
Total Supply Current
60
135
rnA
.45
Volts
.45
Volts
.45
Volts
.45
Volts
Volts
±10
/LA
-500
/LA
INPUT AND OUTPUT WAVEFORMS FOR AC TESTS
.:: ______-'X : :}
TEST POINTS {:::
x'-______
AC CHARACTERISTICS
TA
= 0 to 70°C,
Vee
= Voo =
+5.0V ±10% (Note 1), Vss
= OV
Am8048
Am8035
Test Conditions
Parameters
Description
(Note 2)
Min
Max
Units
tLL
ALE Pulse Width
400
tAL
Address Set-up to ALE
120
ns
tLA
Address Hold from ALE
SO
ns
tee
Control Pulse Width (PSEN, RD, WR)
700
ns
tow
Data Set-up Before WR
500
ns
two
Data Hold After WR
C L = 20pF
120
tey
Cycle Time
6MHz XTAL (3.6MHz XTAL for -S)
2.5
15.0
/Ls
tOR
Data Hold
0
200
ns
tRO
PSEN, RD to Data In
500
ns
tAW
Address Set-up to WR
tAO
Address Set-up to Data In
tAFe
Address Float to RD, PSEN
0
ns
teA
Control Pulse to ALE
10
ns
ns
ns
230
ns
950
Notes: 1. Vee and Voo for AmS035-S are ±5%.
2. Control Outputs: C L = SOpF.
Bus Outputs: CL = 150pF, tey = 2.5/Ls.
7·2
ns
Am8048/B035
WAVEFORMS
INSTRUCTION FETCH FROM EXTERNAL PROGRAM MEMORY
I-r>--------CV--------l
rlll---i
ALE
~_-------I
J
I
PSEN
BUS
L
1
1....-
I-t-IAFC
I
-,,,~-";"'LA~I
~
b,,,
W
f-ICC-~_t_-_t_-tCA
FLOAn"O
-FL-O-A-TIN-G-)(
~,,,1--'''3
'",,'ocnO"
MOS-165
READ FROM EXTERNAL DATA MEMORY
ALE
J
L
RD
BUS
FLOATING
MOS-166
WRITE TO EXTERNAL DATA MEMORY
ALE
J
L
rlcc
ICA
I
WR
Ilow
BUS
two
FLOATING
FLOATING
MOS-167
J\-----------c
PORT 2 TIMING
ALE
EXPANDER
PORT
OUTPUT
IpL -
ILP
11-----"""
PORT CONTROL
PCH
EXPANDER
PORT
INPUT
PCH
___________________
~~------lpP-------J
PROG
MOS-168
7-3
Am8048/8035
AC CHARACTERISTICS (Port 2 Timing)
= 0 to 70°C, Vcc = 5V ±10% (Note 1), Vss = OV
Am8048
Am8035
TA
Description
Parameters
Test Conditions
Min.
Max.
Units
tcp
Port Control Set-up before Falling Edge of PROG
110
tpc
Port Control Hold after Falling Edge of PROG
100
tpR
PROG to Time P2 Input Must be Valid
top
Output Data Set· up Time
250
tpo
Output Data Hold Time
65
tpF
Input Data Hold Time
tpp
PROG Pulse Width
1200
ns
tpL
Port 2 I/O Data Set-up
350
ns
tLP
Port 2 I/O Data Hold
150
ns
ns
ns
810
0
ns
ns
ns
150
ns
PIN DESCRIPTION
Vss
INT
Circuit GND potential.
Interrupt input. Initiates an interrupt if interrupt is enabled. Interrupt is disabled after a reset. Also testable with conditional jump
instruction (Active low).
VDD
Power supply; +5V during operation. low power standby pin for
Am8048 ROM.
RD
VCC
Output strobe activated during a BUS read. Can be used to
enable data onto the BUS from an external device.
Main power supply; +5V.
Used as a Read Strobe to External Data Memory (Active low).
PROG
RESET
Output strobe for Am8243 I/O expander.
Input which is used to initialize the processor. Also used during
power down (Active low).
P10·PH Port 1
WR
8-bit quasi-bidirectional port.
Output strobe during a BUS write (Active low) (Non-TTL V 1H ).
P 20·P27 Port 2
Used as write strobe to External Data Memory.
8-bit quasi-bidirectional port.
ALE
P20-P 23 contain the four high order program counter bits during
an exteral program memory fetch and serve as a 4-bit I/O expander bus for Am8243.
Address latch Enable. This signal occurs once during each cycle
and is useful as a clock output.
The negative edge of ALE strobes address into external data and
program memory.
00.07 BUS
True bidirectional port which can be written or read synchronously using the RD, WR strobes. The port can also be statically
latched.
PSEN
Program Store Enable. This output occurs only during a fetch to
external program memory (Active low).
Contains the 8 low order program counter bits during an external
program memory fetch, and receives the addressed instruction
under the control of PSEN. Also contains the address and data
during an external RAM data store instruction, under control of
ALE, RD and WR.
SS
Single step input can be used in conjunction with ALE to "single
step" the processor through each instruction (Active low).
EA
External Access input which forces all program memory fetches
to reference external memory. Useful for emulation and debug,
and essential for testing and program verification (Active high).
TO
Input pin testable using the conditional transfer instructions JT0
and JNTo. To can be designated as a clock output using ENTO
ClK instruction. To is also used during programming.
XTAL 1
T1
One side of crystal input for internal oscillator. Also input for
external source (Not TTL compatible).
Input pin testable using the JT1 , and JNT1 instructions. Can be
designated the timer/counter input using the STRT CNT instruction.
Other side of crystal input.
XTAL 2
7-4
Am8080A/9080A
a-Bit Microprocessor
•
•
•
•
•
Distinctive Characteristics
• Plug-in replacements for 8080A, 8080A-1, 8080A-2
• High-speed version with 11lsec instruction cycle
• Military temperature range operation to 1.5llsec
GENERAL DESCRIPTION
Ion-implanted, n-channel, silicon-gate MOS technology
3.2mA of output drive at O.4V (two full TTL loads)
700mV of high, 400mV of low level noise immunity
820mW maximum power Clissipation at ±5% power
100% reliability assurance testing to MIL-STD-883
An accumulator plus six general purpose registers are available
to the programmer. The six registers are each 8 bits long and
may be used singly or in pairs for both 8 and 16-bit operations.
The accumulator forms the primary working register and is the
destination for many of the arithmetic and logic operations.
The Am9080A products are complete, general-purpose, singlechip digital processors. They are fixed instruction set, parallel,
8-bit units fabricated with Advanced N·Channel Silicon Gate
MOS technology. When combined with external memory and
peripheral devices, powerful microcomputer systems are
formed. The Am9080A may be used to perform a wide variety
of operations, ranging from complex arithmetic calculations to
character handling to bit control. Several versions are available
offering a range of performance options.
A general purpose push-down stack is an important part of the
processor architecture. The contents of the stack reside in R!W
memory and the control logic, including a 16-bit stack pointer,
is located on the processor chip. Subroutine call and return
instructions automatically use the stack to store and retrieve
the contents of the program counter. Push and Pop instructions allow direct use of the stack for storing operands, passing
parameters and saving the machine state.
The processor has a 16-bit address bus that may be used to
directly address up to 64K bytes of memory. The memory
may be any combination of read/write and read-only. Data
are transferred into or out of the processor on a bi-directional
8-bit data bus that is separate from the address lines. The data
bus transfers instructions, data and status information between
system devices. All transfers are handled using asynchronous
handshaking controls so that any speed memory or I/O device
is easily accommodated.
An asynchronous vectored interrupt capability is included to
allow external signals to modify the instruction stream. The
interrupting device may specify an interrupt instruction to be
executed and may thus vector the program to a particular
service location, or perform some other direct function. Direct
memory access (DMA) capability is also included.
BLOCK DIAGRAM
I
REGISTER ARRAY
I
~--
STACK POINTER
I
PROGRAM COUNTER
I
---~--
ADDRESS LATCHES
TIMING
CONTROL
LINES
ALU
ARITHMETIC AND LOGIC UNIT
INTERFACE
CONTROL ~------'
LINES
MOS-155
ORDERING INFORMATION
Package Type
Ambient Temperature
Specification
Hermetic DIP*
O°C",;; T A ",;; +70°C
Molded DIP
Hermetic DIP
Minimum Clock Period
250n5
320n5
380n5
480n5
AM9080A-4DC
AM9080A-4CC
AM9080A-1 DC
AM9080A-1CC
D8080A-1
AM9080A-2DC
AM9080A-2CC
D8080A-2
AM9080ADC
AM9080ACC
D8080A
AM9080A-4PC
AM9080A-1PC
P8080A-l
AM9080A-2PC
P8080A-2
AM9080APC
P8080A
AM9080A-2DM
AM9080ADM
AM8080A
-55°C",;; TA ",;; +125°C
-Hermetic = Ceramic = DC = CC = D-40-1.
7-5
Am8080A/9080A
CONNECTION DIAGRAM
Top View
INTERFACE SIGNAL SUMMARY
TYPE
All
Al0
(GNO)VSS
39
A14
04
38
A13
05
37
A12
06
PINS
ABBREVIATION
SIGNAL
INPUT
1
VSS
Ground
INPUT
3
VDD,VCC,VBB
+12V, +5V, -5V Supplies
INPUT
2
1
STSTB
¢2 TTL
RDYIN
Basic DMA Configuration.
7-57
MOS-476
Am8257
AC CHARACTERISTICS: DMA (MASTER) MODE (TA = 0 to 7oo e, vee = 5.0V ±5%, GND = OV)
Timing Requirements
Parameters
Description
OJ
OJ
Max
Units
(SI, S4) (Measured at 2.0V) (Note 1)
Min
160
ns
(SI, S4) (Measured at 3.3V) (Note 3)
250
ns
300
ns
tDO
HROj or ~Delay from
tDOl
HROj or ~Delay from
tAEl
AENj Delay from O~ (Sl) (Note 1)
tAET
AEN~ Delay from
tAEA
Address (AB) (Active) Delay from AENj (Sl) (Note 4)
OJ
(SI) (Note 1)
200
20
OJ (Sl) (Note 2)
OJ (SI) (Note 2)
(Stable) Delay from OJ (Sl) (Note 2)
(Stable) Hold from Of (Sl) (Note 2)
ns
ns
tFAAB
Address (AB) (Active) Delay from
250
ns
tAFAB
Address (AB) (Float) Delay from
150
ns
tASM
Address (AB)
250
ns
tAli
Address (AS)
tASM-50
ns
tAHR
Address (AB) (Valid) Hold from RDj (Sl, SI) (Note 4)
60
ns
300
tAHW
Address (AB) (Valid) Hold from WRj (Sl, SI) (Note 4)
tFADB
Address (DB) (Active) Delay from
tAFDB
Address (DB) (Float)
tASS
Address (DB) Setup to Address Stable~ (Sl, S2) (Note 4)
100
50
OJ (Sl) (Note 2)
Delay from OJ (S2) (Note 2)
tSn +20
tAHS
Address (DB) (Valid) Hold from Address Stable~ (S2) (Note 4)
tSTl
Address Stablej Delay from
tSn
Address Stable~ Delay from
tSW
Address Stable Width (Sl, S2) (Note 4)
tASC
tDBC
tAK
DACKj or ~Delay from O~ (S2, Sl) and TC/Markj Delay from
TC/Mark~ Delay from OJ (S4) (Notes 1, 5)
OJ (Sl)
OJ (S2)
250
ns
ns
ns
ns
(Note 1)
200
(Note 1)
140
ns
ns
tCY-l00
ns
RD~ or WR (Ext)~ Delay from Address Stable~ (S2) (Note 4)
70
ns
RD~ or WR (Ext)~ Delay from Address (DB) (Float) (S2) (Note 4)
20
ns
OJ
tDCl
RD~ or WR (Ext)~ Delay from
mCT
RDj Delay from O~ (Sl, SI) and WRj Delay from
tFAC
tAFC
tRWM
RD Width (S2, Sl or SI) (Note 4)
tWWM
tWWME
Notes: 1.
2.
3.
4.
5.
6.
7.
ns
300
(S2) and WR~ Delay from
OJ
OJ
(S3) and
250
200
ns
200
ns
RD or WR (Active) from
300
ns
RD or WR (Float) from
150
ns
OJ
(S3) (Notes 2, 6)
ns
(S4) (Notes 2, 7)
OJ (Sl) (Note 2)
OJ (SI) (Note 2)
2tCY+t0-50
ns
WR Width (S3, S4) (Note 4)
tCY-50
ns
WR (Ext) Width (S2, S4) (Note 4)
2tCY-50
ns
load = 1 TTL.
load = 1 TTL + 50pF.
load = 1 TTL + (Rl = 3.3K), VOH = 3.3V.
Tracking Parameter.
.:ltAK < 50ns.
.:ltDCl < 50ns.
.:ltDCT < 50ns.
7-58
Am8257
DMA MODE WAVEFORMS
CONSECUTIVE CYCLES AND BURST MODE SEQUENCE
Sl
so
Sl
Sl
S2
S3
I
S4
S2
Sl
S3
S4
Sl
Sl
Sl
CLOCK
DRQO-3
--~--~~----~~-r----~----~~------~------------~~~----+-------------
HRQ
"'"'..... _------
HLDA
AEN _ _ _ _ _ _ _.....--'1
ADR 0-7 (LOWER ADR)
DATA 0-7 (UPPER ADR) - - - - - - - - - - - - - _ -..::._ _~
ADRSTB - - - - - - - - - - - - - - - -__~
DACK0-3
----------~~~
MEM RD/I/O RD - - - - - - - - - - - - - -
MEM WR/I/O RD - - - - - - - - - - - - - -
READY --------------+--+---f-±-n:---+--+-----~,_T"""---+_----_____________ ~~~-J.
TC/MARK - - - - - - - - _____ -+~--~--+_.&....-+-I'+-----------I.------;a,....+_-------
CLOCK
Sl
I
Sl
I
SO
Sl
Sl
I
S2
S3
S4
I
Sl
I
Sl
I
Sl
Note: The clock waveform is duplicated for clarity. The Am8257/9557 requires only one clock input.
Figure 1. Consecutive Cycles and Burst Mode Sequence.
7-59
MOS-S12
Am8257
S1
S2
S3
S4
S1
S1
so
S1
S2
CLOCK
ORQ 0-3
____________-J''+__________________
~~--------
HRQ
HLOA
AEN
,------
J
Figure 2. Control Override Sequence.
so
S1
S2
S3
SW
I
SW
MOS-513
S4
S1
S1
S1
CLOCK
ORQ 0-3
----~-----------+~------~----
MEM RO/l/O RO - - - - - -
MEM WR/VO WR - - - - - -
READY
--------------~~------~~~~-----------
\:t....._____
TC/MARK __________________....../...__________________
Figure 3. Not Ready Sequence.
7-60
MOS-514
Am8257
Metallization and Pad Layout
iOii
40
39
38
37
36
I
i6W
A7
A6
AS
A4
TC
MEMR
MEMW
MARK
5
READY
6
HlOA
7
34 A2
AOSTB
8
33 AI
AEN
9
35 A3
32 AO
HRO 10
CS
31 VCC
30 DO
11
29 01
ClK 12
28 02
RESET 13
OACK2 14
27 03
i5AcK3
15
26 04
OR03
OR02
ORal
OROO
GNO
16
17
18
19
20
25
24
23
22
21
DIE SIZE 0.196"
7-61
x 0.210"
OACK 0
OACK 1
05
06
07
Am
8279/Am8279-5
Programmable Keyboard/Display Interface
DISTINCTIVE CHARACTERISTICS
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GENERAL DESCRIPTION
The Am8279 is a general purpose programmable keyboard
and display I/O interface device deSigned for use with
Am8080Al8085A microprocessors. The keyboard portion can
provide a scanned interface to a 64 contact key matrix which
can be expanded to 128. The keyboard portion will also interface to an array of sensors or a strobed interface keyboard,
such as the Hall effect and Ferrite variety. Key depressions can
be 2 key lockout or N key rollover. Keyboard entries are debounced and stored in an 8 character FIFO. If more than 8
characters are entered, over run status is set. Key entries set
the interrupt output line to the CPU.
The display portion provides a scanned display interface for LED,
incandescent and other popular display technologies. Both
numeric and alphanumeric segment displays may be used as
well as simple indicators. The Am8279 has a 16 x 8 display
RAM which can be organized into a dual 16 x 4. The RAM
can be loaded or interrogated by the CPU. Both right entry,
calculator and left entry typewriter display formats are possible. Both read and write of the display RAM can be done
with auto-increment of the display RAM address.
Am8085A Compatible
Simultaneous keyboard display operations
Scanned keyboard mode
Scanned sensor mode
Strobed input entry mode
8 character keyboard FIFO
2 key lockout or N key rollover vv'ith contact dabounce
Dual 8 or 16 numerical display
Single 16 character display
Right or left entry 16-byte display RAM
Mode programmable from CPU
Programmable scan timing
Interrupt output on key entry
BLOCK DIAGRAM
Ro
WR
cs
c/o
KEYBOARD
OEB~NUDNCE
CONTROL
OUT AO_3
OUT BQ..3
SLo- 3
RLo-1
CNTUSTB
MOS-132
ORDERING INFORMATION
Package Type
Hermetic DIp·
Ambient Temperature
Specification
O°C
~
TA
~
+70°C
Molded DIP
"Hermetic
= Ceramic = DC = CC =
D-40-1.
7-62
Order Numbers
AMB279DC
AM8279CC
AM8279-5DC
AMB279-5CC
AMB279PC
AMB279-5PC
Am8279/Am8279-5
PIN NAMES
LOGIC SYMBOL
CONNECTION DIAGRAM
Top View
CPU
INTERFACE
Name
I/O
DBo·DB7
1;0
RL3
RL1
CLK
RLo
ClK
Clock Input
tRQ
CNTLlSTB
RESET
Reset Input
RL4
SHtFT
RLs
SL3
RLs
SL2
CS
Chip Select
RD
Read Input
RL7
SL 1
WR
Write Input
SLo
C/O
Buffer Address
WR
OUT Bo
OUTB1
DBa
OUTB2
o
o
IRQ
Slo·Sl3
Interrupt Request Output
Scan Lines
OUT B3
RLa·Rl7
Return Lines
SHIFT
Shifllnput
DB3
CNTLlSTB
Control/Strobe Input
DB4
OUTA2
DBs
OUTA3
DBs
OUT Ao
DISPLAY
DATA
vee
RL2
Function
Data Bus (Bidirectional)
o
o
o
OUT A o·A 3
OUT B o·B 3
BD
Display (A) Outputs
OUTA1
Display (B) Outputs
DB7
iiii
CS
Blank Display Output
VSS
C/O
Note: Pin 1 is marked for orientation.
MOS·134
MOS·133
MAXIMUM RATINGS
above which useful life may be impaired
Storage Temperature
Ambient Temperature Under Bias
Vee with Respect to V ss
-O.SV to
+ 7.0V
All Signal Voltages with Respect to Vss
-O.SV to
+ 7.0V
1W
Power Dissipation
The products described by this specification include internal circuitry designed to protect input devices from damaging accumulations of
static charge. It is suggested, nevertheless, that conventional precautions be observed during storage, handling and use in order to avoid
exposure to excessive voltages.
DC CHARACTERISTICS
TA
=
O°C to +70°C, Vss
=
OV (Note 1)
Max.
Units
VIL1
Input Low Voltage for Return lines Only
-O.S
1.4
V
VIL2
Input Low Voltage for All Others
-O.S
0.8
V 1H1
Input High Voltage for Return lines Only
2.2
Parameter
Description
Min.
Test Conditions
VIH2
Input High Voltage for All Others
VOL
Output Low Voltage
Note 2
VO H
Output High Voltage on Interrupt Line
Note 3
11L1
Input Current on Shift, Control and Returns
Typ.
V
2.0
.4S
= Vee
= OV
=
VIN
IIL2
Input Leakage Current on All Others
VIN
IOFL
Output Float Leakage
VO UT
lee
Power Supply Current
V
V
3.S
VIN
V
V
+10
J.LA
-100
J.LA
Vee to OV
±10
J.LA
=
±10
J.LA
120
mA
Vee to OV
Notes: 1. Am8279, Vee = +S.OV ±S%; Am8279-S, Vee = +S.OV ±10%.
2. Am8279, IOL = 1.6mA; Am8279-S, IOL = 2.2mA.
3. Am8279, IOH = -100J.LA; Am8279-S, IOH = -400J.LA.
CAPACITANCE
Parameter
Description
Test Conditions
Input Capacitance
Output Capacitance
VOUT = Vee
7-63
Min.
Max.
Units
Am8279/Am8279-5
AC CHARACTERISTICS (TA
= O°C to 70°C, Vss = OV) (Note 1)
BUS PARAMETERS
Read Cycle:
Am8279
Parameter
Description
Am8279-5
Max.
Min.
Max.
Min.
Units
tAR
Address Stable Before READ
50
0
ns
5
0
ns
tRA
Address Hold Time for READ
tRR
READ Pulse Width
tRO
Data Delay from READ (Note 2)
tAD
Address to Data Valid (Note 2)
tOF
READ to Data Floating
tReY
Read Cycle Time
250
420
450
10
100
10
1
ns
250
ns
100
Min.
ns
p.,s
Am8279
Description
150
1
Write Cycle:
Parameter
ns
300
Am8279-5
Max.
Min.
Max.
Units
tAW
Address Stable Before WRITE
50
0
ns
tWA
Address Hold Time for WRITE
20
0
ns
tww
WRITE Pulse Width
400
250
ns
tow
Data Set-up Time for WRITE
300
150
ns
two
Data Hold Time for WRITE
40
0
ns
Notes: 1. Am8279, Vee = +5.0V ±5%; Am8279-5, Vee = +5.0V ±10%.
2. Am8279, C L = 100pF; Am8279-5; C L = 150pF.
Other Timings:
Am8279
Parameter
Description
Min.
Max.
Min.
Am8279-5
Max.
Units
Clock Pulse Width
Clock Period
Keyboard Scan Time
Keyboard Debounce Time
Key Scan Time
Display Scan Time
5.1msec
10.3msec
80jLsec
10.3msec
Digit-on Time
Blanking Time
Internal Clock Cycle
480jLsec
160jLsec
10jLsec
INPUT WAVEFORMS FOR AC TESTS
2.4
2.0
0.8
\
;-
2.0
TEST POINTS
---I
~
0.8
0.45
MOS-135
7-64
Am8279/Am8279-5
WAVEFORMS
READ OPERATION
V
~I
cio,cs
---..A----------------------l""1 ~"'_____________
(SYSTEM'S
ADDRESS BUS)
RD
'" -
DATA BUS
(OUTPUT)
'0'
'eo
'---
\ f - o > - - - - - DATA V A L I D , - - - - - I \
MOS-136
WRITE OPERATION
j
1\l
(SYSTEM'S
ADDRESS BUS)
Jl\
tWA
~-----tww-----~
' - - - - - -
(WRITE CONTROL)
DATA BUS
(INPUT)
DATA
MAY CHANGE
DATA VALID----l
DATA
MAY CHANGE
MOS-137
CLOCK INPUT
~-------------tCY--------~
MOS-138
7-65
Am9S11A
Arithmetic Processor
DISTINCTIVE CHARACTERISTICS
GENERAL DESCRIPTION
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The Am9511A Arithmetic Processing Unit (APU) is a monolithic
MOS/LSI device that provides high performance fixed and
floating point arithmetic and a variety of floating point
trigonometric and mathematical operations. It may be used to
enhance the computational capability of a wide variety of
processor-oriented systems.
Replaces Am9511
Fixed point 16 and 32 bit operations
Floating point 32 bit operations
Binary data formats
Add, Subtract, Multiply and Divide
Trigonometric and inverse trigonometric functions
Square roots, logarithms, exponentiation
Float to fixed and fixed to float conversions
Stack-oriented operand storage
DMA or programmed I/O data transfers
End signal simplifies concurrent processing
Synchronous/Asynchronous operations
General purpose 8-bit data bus interface
Standard 24 pin package
+12 volt and +5 volt power supplies
Advanced N-channel silicon gate MOS technology
100% MIL-STD-883 reliability assurance testing
All transfers, including operand, result, status and command
information, take place over an 8-bit bidirectional data bus.
Operands are pushed onto an internal stack and a command
is issued to perform operations on the data in the stack. Results are then available to be retrieved from the stack, or additional commands may be entered.
Transfers to and from the APU may be handled by the
associated processor using conventional programmed I/O, or
may be handled by a direct memory access controller for improved performance. Upon completion of each command, the
APU issues an end of execution signal that may be used as
an interrupt by the CPU to help coordinate program execution.
BLOCK DIAGRAM
CONNECTION DIAGRAM
Top View
(GND) VSS
ClK
(+SV) VCC
RESET
EACK
SVREQ
8
DBO-DB7
DO
NOT
USE
-r-
DBO
DBl
VDD (+12V)
DB2
DB7
DB3
DBS
DB4
DBS
Pin 1 is marked for orientation.
MOS-046
MOS-047
ORDERING INFORMATION
Package
Type
Hermetic DIP
Maximum Clock Frequency
Ambient
Temperature
2MHz
3MHz
O°C .:;: TA .:;: + 70°C
Am9511ADC
Am9511A-1 DC
-55°C.:;: TA .:;: +125°C
Am9511ADM
Am9511A-1 DM
7-66
Am9S11A
INTERFACE SIGNAL DESCRIPTION
VCC: +5V Power Supply
VDD: + 12V Power Supply
VSS: Ground
SVACK (Service Acknowledge, Input)
ClK (Clock, Input)
An external timing source connected to the ClK input provides
the necessary clocking. The ClK input can be asynchronous to
the RD and WR control signals.
RESET (Reset, Input)
A HIGH on this input causes initialization. Reset terminates any
operation in progress, and clears the status register to zero. The
internal stack pointer is initialized and the contents of the stack
may be affected but the command register is not affected by the
reset operation. After a reset the END output will be HIGH, and
the SVREQ output will be lOW. For proper initialization, the
RESET input must be HIGH for at least five ClK periods following
stable power supply voltages and stable clock.
cio (Command/Data Select, Input)
The C/O input together with the RD and WR inputs determines
the type of transfer to be performed on the data bus as follows:
C/D
RD
WR
L
H
L
Also, the SVREQ will be automatically cleared after completion
of any command that has the service request bit as O.
Function
Push data byte into the stack
L
L
H
Pop data byte from the stack
H
H
L
Enter command byte from the data bus
H
L
H
Read Status
X
L
L
Undefined
L = LOW
H = HIGH
X = DON'T CARE
END (End of Execution, Output)
A lOW on this output indicates that execution of the current
command is complete. This output will be cleared HIGH by activating the EACK input LOW or performing any read or write
operation or device initialization using the RESET. If EACK is
tied lOW, the END output will be a pulse (see EACK description). This is an open drain output and requires a pull up to +5V.
Reading the status register while a command execution is in
progress is allowed. However any read or write operation clears
the flip-flop that generates the END output. Thus such continuous reading could conflict with internal logic setting the END
flip-flop at the completion of command execution.
EACK (End Acknowledge, Output)
This input when LOW makes the END output go LOW. As mentioned earlier HIGH on the END output signals completion of a
command execution. The END output signal is derived from an
internal flip-flop which is clocked at the completion of a command. This flip-flop is clocked to the reset state when EACK is
LOW. Consequently, if the EACK is tied LOW, the END output
will be a pulse that is approximately one ClK period wide.
SVREQ (Service Request, Output)
A HIGH on this output indicates completion of a command. In
this sense this output is same as the END output. However,
whether the SVREQ output will go HIGH at the completion of a
command or not is determined by a service request bit in the
command register. This bit must be 1 for SVREQ to go HIGH.
The SVREQ can be cleared (Le., go lOW) by activating the
SVACK input lOW or initializing the device using the RESET.
A lOW on this input activates the reset input of the flip-flop
generating the SVREQ output. If the SVACK input is permanently tied LOW, it will conflict with the internal setting of the
flip-flop to generate the SVREQ output. Thus the SVREQ indication cannot be relied upon if the SVACK is tied LOW.
DBD-DB7 (BidirectiQnal Data Bus, Input/Output)
These eight bidirectional lines are used to transfer command,
status and operand information between the device and the host
processor. D80 is the least significant and D87 is the most
significant bit position. HIGH on the data bus line corresponds to
1 and lOW corresponds to O.
When pushing operands on the stack using the data bus, the
least significant byte must be pushed first and most significant
byte last. When popping the stack to read the result of an operation, the most significant byte will be available on the data bus
first and the least significant byte will be the last. Moreover, for
pushing operands and popping results, the number of transactions must be equal to the proper number of bytes appropriate
for the chosen format. Otherwise, the internal byte pointer will
not be aligned properly. The Am9511A single precision format
requires 2 bytes, double precision and floating-point formats require 4 bytes.
CS (Chip Select, Input)
This input must be LOWto accomplish any read or write operation to the Am9511A.
To perform a write operation data is presented on D80 through
D87 lines, C/O is driven to an appropriate level and the CS input
is made lOW. However, actual writing into the Am9511 A cannot
start until WR is made LOW. After initiating the write operation
by a WR HIGH to lOW transition, the PAUSE output will go
LOW momentarily (TPPWW).
The WR input can go HIGH after PAUSE goes HIGH. The data
lines, cio input and the CS input can change when appropriate
hold time requirements are satisfied. See write timing diagram
for details.
To perform a read operation an appropriate logic level is established on the cio input and CS is made LOW. The Read operation does not start until the RD input goes LOW. PAUSE will go
LOW for a period of TPPWR. When PAUSE goes back HIGH
again, it indicates that read operation is complete and the required information is available on the DBO through D87 lines.
This information will remain on the data lines as long as RD input
is lOW. The RD input can return HIGH anytime after PAUSE
goes HIGH. The CS input and cin inputs can change anytime
after RD returns HIGH. See read timing diagram for details.
RD (Read, Input)
A LOW on this input is used to read information from an internal
location and gate that information on to the data bus. The CS
input must be LOW to accomplish the read operation. The
input determines what internal location is of interest. See
CS input descriptions and read timing diagram for details. If the
END output was LOW, performing any read operation will make
the END output go HIGH after the HIGH to LOW transition of the
RD input (assuming CS is LOW).
cin
clo,
7-67
Am9S11A
WR (Write, Input)
A LOW on this input is used to transfer information from the data
bus into an internal location. The CS must be LOW to accomplish the write operation. The ci5 determines which internal
location is to be written. See ci5, CS input descriptions and
write timing diagram for details.
If the END output was LOW, performing any write operation will
make the END output go HIGH after the LOW to HIGH transition
of the WR input (assuming CS is LOW).
PAUSE (Pause, Output)
This output is a handshake signal used while performing read or
write transactions with the Am9511A. A LOW at this output indicates that the Am9511A has not yet completed its information
transfer with the host over the data bus. During a read operation,
after CS went LOW, the PAUSE will become LOW shortly (TRP)
after RD goes LOW. PAUSE will return high only after the data
bus contains valid output data. The CS and RD should remain
LOW when PAUSE is LOW. The RD may go high anytime after
PAUSE goes HIGH. During a write operation, after CS went
LOW, the PAUSE will be LOW for a very short duration
(TPPWN) after WR goes LOW. Since the minimum of TPPWW
is 0, the PAUSE may not go LOW at all for fast devices. WR may
go HIGH anytime after PAUSE goes HIGH.
bus through appropriate interface and buffer circuitry. Multiplexing facilities exist for bidirectional communication between
the internal eight and sixteen-bit buses. The Status Register and
Command Register are also accessible via the eight-bit bus.
The Am9511A operations are controlled by the microprogram
contained in the Control ROM. The Program Counter supplies
the microprogram addresses and can be partially loaded from
the Command Register. Associated with the Program Counter is
the Subroutine Stack where return addresses are held during
subroutine calls in the microprogram. The Microinstruction
Register holds the current microinstruction being executed. This
register facilitates pipelined microprogram execution. The Instruction Decode logic generates various internal control signals
needed for the Am9511A operation.
The Interface Control logic receives severa! external inputs and
provides handshake related outputs to facilitate interfacing the
Am9511A to microprocessors.
COMMAND FORMAT
Each command entered into the Am9511A consists of a single
8-bit byte having the format illustrated below:
SVREQ
I
.
FUNCTIONAL DESCRIPTION
Major functional units of the Am9511A are shown in the block
diagram. The Am9511A employs a microprogram controlled
stack oriented architecture with 16-bit wide data paths.
The Arithmetic Logic Unit (ALU) receives one of its operands
from the Operand Stack. This stack is an 8-word by 16-bit 2-port
memory with last in-first out (UFO) attributes. The second
operand to the ALU is supplied by the internal 16-bit bus. In
addition to supplying the second operand, this bidirectional bus
also carries the results from the output of the ALU when required. Writing into the Operand Stack takes place from this
internal 16-bit bus when required. Also connected to this bus are
the Constant ROM and Working Registers. The ROM provides
the required constants to perform the mathematical operations
(Chebyshev Algorithms) while the Working Registers provide
storage for the intermediate values during command execution.
Communication between the external world and the Am9511A
takes place on eight bidirectional input/output lines DBO through
DB7 (Data Bus). These signals are gated to the internal eight-bit
SINGLE
I
I
FIXED ....
I·-----OP~~~T~ON
.
(sr)
764
3
Bits 0-4 select the operation to be performed as shown in the
table. Bits 5-6 select the data format for the operation. If bit 5
is a 1, a fixed point data format is specified. If bit 5 is a 0,
floating pOint format is specified. Bit 6 selects t,he precision of
the data to be operated on by fixed pOint commands (if bit 5
= 0, bit 6 must be 0). If bit 6 is a 1, single-precision (16-bit)
operands are indicated; if bit 6 is a 0, double-precision (32-bit)
operands are indicated. Results are undefined for all illegal
combinations of bits in the command byte. Bit, 7 indicates
whether a service request is to be issued after the command
is executed. If bit 7 is a 1, the service request output
(SVREQ) will go high at the conclusion of the command and
will remain high until reset by a low level on the service
acknowledge pin (SVACK) or until completion of execution of
a succeeding command where bit 7 is 0. Each command issued to the Am9511 A requests post execution service based
upon the state of bit 7 in the command byte. When bit 7 is a
0, SVREQ remains low.
7-68
Am9511A
COMMAND SUMMARY
Command Code
7
6
5
4
3
2
1
0
Command
Mnemonic
sr
sr
sr
sr
sr
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
1
1
1
0
1
1
1
1
1
1
0
0
1
1
1
0
1
0
0
1
SADD
SSUB
SMUL
SMUU
SDIV
sr
sr
sr
sr
sr
0
0
0
0
0
1
1
1
1
0
0
1
1
1
0
0
0
1
0
1
1
1
1
0
1
1
1
1
1
1
0
1
0
DADD
DSUB
DMUL
DMUU
DDIV
sr
sr
sr
sr
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
1
sr
sr
sr
sr
sr
sr
sr
sr
sr
sr
sr
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
sr
sr
sr
sr
sr
sr
sr
sr
sr
sr
sr
sr
sr
sr
sr
sr
sr
sr
0
0
0
0
0
1
0
0
1
0
0
0
0
0
Command Description
FIXED-POINT 16-BIT
Add TOS to NOS. Result to NOS. Pop Stack.
Subtract TOS from NOS. Result to NOS. Pop Stack.
Multiply NOS by TOS. Lower half of result to NOS. Pop Stack.
Multiply NOS by TOS. Upper half of result to NOS. Pop Stack.
Divide NOS by TOS. Result to NOS. Pop Stack.
FIXED-POINT 32-BIT
0
1
Add TOS to NOS. Result to NOS. Pop Stack.
Subtract TOS from NOS. Result to NOS. Pop Stack.
Multiply NOS by TOS. Lower half of result to NOS. Pop Stack.
Multiply NOS by TOS. Upper half of result to NOS. Pop Stack.
Divide NOS by TOS. Result to NOS. Pop Stack.
FLOATING-POINT 32-BIT
0
0
0
0
1
0
1
FADD
FSUB
FMUL
FDIV
Add TOS to NOS. Result to NOS. Pop Stack.
Subtract TOS from NOS. Result to NOS. Pop Stack.
Multiply NOS by TOS. Result to NOS. Pop Stack.
Divide NOS by TOS. Result to NOS. Pop Stack.
DERIVED FLOATING-POINT FUNCTIONS
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
1
1
1
1
1
0
1
1
0
0
0
0
1
0
1
0
1
1
1
1
0
1
1
0
1
0
1
0
1
SORT
SIN
COS
TAN
ASIN
ACOS
ATAN
LOG
LN
EXP
PWR
Square Root of TOS. Result in TOS.
Sine of TOS. Result in TOS.
Cosine of TOS. Result in TOS.
Tangent of TOS. Result in TOS.
Inverse Sine of TOS. Result in TOS.
Inverse Cosine of TOS. Result in TOS.
Inverse Tangent of TOS. Result in TOS.
Common Logarithm (base 10) of TOS. Result in TOS.
Natural Logarithm (base e) of TOS. Result in TOS.
Exponential (ex) of TOS. Result in TOS.
NOS raised to the power in TOS. Result in NOS. Pop Stack.
DATA MANIPULATION COMMANDS
0
1
1
0
1
1
0
0
1
1
1
0
0
1
0
0
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
1
0
0
0
1
1
1
1
0
0
0
1
1
1
0
NOP
FIXS
FIXD
FLTS
FLTD
CHSS
CHSD
CHSF
PTOS
PTOD
PTOF
POPS
POPD
POPF
XCHS
XCHD
XCHF
PUPI
No Operation
Convert TOS from floating point to 16-bit fixed point format.
Convert TOS from floating point to 32·bit fixed point format.
Convert TOS from 16·bit fixed point to floating point format.
Convert TOS from 32·bit fixed point to floating point format.
Change sign of 16·bit fixed point operand on TOS.
Change sign of 32·bit fixed point operand on TOS.
Change sign of floating point operand on TOS.
Push 16·bit fixed point operand on TOS to NOS (Copy)
Push 32·bit fixed point operand on TOS to NOS. (Copy)
Push floating point operand on TOS to NOS. (Copy)
Pop 16-bit fixed point operand from TOS. NOS becomes TOS.
Pop 32-bit fixed point operand from TOS. NOS becomes TOS.
Pop floating pOint operand from TOS. NOS becomes TOS.
Exchange 16·bit fixed point operands TOS and NOS.
Exchange 32·bit fixed point operands TOS and NOS.
Exchange floating point operands TOS and NOS.
Push floating point constant "7T" onto TOS. Previous TOS becomes NOS.
NOTES:
1. TOS means Top of Stack. NOS means Next on Stack.
2. AMD Application Brief "Algorithm Details for the Am9511A
APU" provides detailed descriptions of each command func·
tion, including data ranges, accuracies, stack configurations,
etc.
3. Many commands destroy one stack location (bottom of
stack) during development of the result. The derived func·
tions may destroy several stack locations. See Application
Brief for details.
4. The trigonometric functions handle angles in radians, not
degrees.
5. No remainder is available for the fixed·point divide functions.
6. Results will be undefined for any combination of command
coding bits not specified in this table.
7·69
II
Am9511A
COMMAND INITIATION
except for format conversion commands. Thus when the result
is taken from the stack, the total number of bytes popped out
should be appropriate with the precision - single precision results are 2 bytes and double precision and floating-point results
are 4 bytes. The following procedure must be used for reading
the result from the stack:
After properly positioning the required operands on the stack, a
command may be issued. The procedure for initiating a command execution is as follows:
1. Enter the appropriate command on the DBO-DB7 lines.
2. Establish HIGH on the C/O input.
3. Establish LOW on the CS input.
4. Establish LOW on the WR input after an appropriate set up
time (see timing diagrams).
5. Sometime after the HIGH to LOW level transition of WR
input, the PAUSE output will become LOW. After a delay of
TPPWW, it will go HIGH to acknowledge the write operation.
The WR input can return to HIGH anytime after PAUSE going
HIGH. The DBO-DB7, clo and CS inputs are allowed to
change after the hold time requirements are satisfied (see
timing diagram).
1. A LOW is established on the ci5 input.
2. The CS input is made LOW.
3. After appropriate set up time (see timing diagrams), the RD
input is made LOW. The PAUSE will become LOW.
4. Sometime after this, PAUSE will return HIGH indicating that
the data is available on the DBO-DB7 lines. This data will
remain on the DBO-DB7 lines as long as the RD input remains LOW.
5. Anytime after PAUSE goes HIGH, the RD input can return
HIGH to complete·transaction.
6. The CS and ci5 inputs can change after appropriate hold
time requirements are satisfied (see timing diagram).
7. Repeat this procedure until all bytes appropriate for the precision of the result are popped out.
An attempt to issue a new command while the current command
execution is in progress is allowed. Under these circumstances,
the PAUSE output will not go HIGH until the current command
execution is completed.
Reading of the stack does not alter its data; it only adjusts the
byte pointer. If more data is popped. than the capacity of the
stack, the internal byte pointer will wrap around and older data
will be read again, consistent with the LIFO stack.
OPERAND ENTRY
The Am9511A commands operate on the operands located at
the TOS and NOS and results are returned to the stack at NOS
and then popped to TOS. The operands required for the
Am9511A are one of three formats - single precision fixed-point
(2 bytes), double preCision fixed-point (4 bytes) or floating-point
(4 bytes). The result of an operation has the same format as the
operands except for float to fix or fix to float commands.
STATUS READ
The Am9511A status register can be read without any regard to
whether a command is in progress or not. The only implication
that has to be considered is the effect this might have on the
END output discussed in the signal descriptions.
Operands are always entered into the stack least significant byte
first and most significant byte last. The following procedure must
be followed to enter operands onto the stack:
The following procedure must be followed to accomplish status
register reading.
1. Establish HIGH on the ciD input.
2. Establish LOW on the CS input.
3. After appropriate set up time (see timing diagram) RD input is
made LOW. The PAUSE will become LOW.
4. Sometime after the HIGH to LOW transition of RD input, the
PAUSE will become HIGH indicating that status register
contents are available on the DBO-DB7 lines. The status data
will remain on DBO-DB7 as long as RD input is LOW.
5. The RD input can be returned HIGH anytime after PAUSE
goes HIGH.
6. The C/O input and CS input can change after satisfying appropriate hold time requirements (see timing diagram).
1. The lower significant operand byte is established on the
DBO-DB7 lines.
2. A LOW is established on the ci5 input to specify that data is
to be entered into the stack.
3. The CS input is made LOW.
4. After appropriate set up time (see timing diagrams), the WR
input is made LOW. The PAUSE output will become LOW.
5. Sometime after this event, the PAUSE will return HIGH to
indicate that the write operation has been acknowledged.
6. Anytime after the PAUSE output goes HIGH the WR input
can be made HIGH. The DBO-DB7, ci5 and CS inputs can
change after appropriate hold time requirements are satisfied
(see timing diagrams).
DATA FORMATS
The above procedure must be repeated until all bytes of the
operand are pushed into the stack. It should be noted that for
single precision fixed-point operands 2 bytes should be pushed
and 4 bytes must be pushed for double precision fixed-point or
floating-point. Not pushing all the bytes of a quantity will result in
byte pointer misalignment.
The Am9511A Arithmetic Processing Unit handles operands in
both fixed-point and floating-point formats. Fixed-point operands
may be represented in either single (16-bit operands) or double
precision (32-bit operands), and are always represented as
binary, two's complement values.
The Am9511A stack can accommodate 8 single precision
fixed-point quantities or 4 double precision fixed-point or floating-point quantities. Pushing more quantities than the capacity
of the stack will result in loss of data which is usual with any
LIFO stack.
16-BIT FIXED-POINT FORMAT
s ----VALUE----I
I I I
I I I I
I
15
(MSB)
DATA REMOVAL
32-BIT FIXED-POINT FORMAT
Result from an operation will be available at the TOS. Results
can be transferred from the stack to the data bus by reading the
stack. When the stack is popped for results, the most significant
byte is available first and the least significant byte last. A result is
always of the same precision as the operands that produced it
SI---------VALUE---------!
!..
II I I
I
31
(MSB)
7-70
Am9511A
The sign (positive or negative) of the operand is located in the
most significant bit (MSB). Positive values are represented by
a sign bit of zero (S = 0). Negative values are represented by
the two's complement of the corresponding positive value with
a sign bit equal to 1 (S = 1). The range of values that may be
accommodated by each of these formats is -32,768 to
+32,767 for single precision and -2,147,483,648 to
+2,147,483,647 for double precision.
FLOATING POINT FORMAT
The format for floating-point values in the Am9511A is given
below. The mantissa is expressed as a 24-bit (fractional) value;
the exponent is expressed as an unbiased two's complement
7-bit value having a range of -64 to +63. The most significant
bit is the sign of the mantissa (0 = positive, 1 = negative), for a
total of 32 bits. The binary point is assumed to be to the left of
the most significant mantissa bit (bit 23). All floating-point data
values must be normalized. Bit 23 must be equal to 1, except for
the value zero, which is represented by all zeros.
Floating point binary values are represented in a format that
permits arithmetic to be performed in a fashion analogous to
operations with decimal values expressed in scientific notation.
(5.83 x 102 )(8.16 x 101 ) = (4.75728
X
104 )
MI'E EXPONENT--j-------- MANTISSA-------II
.slsl
I I I I
I
In the decimal system, data may be expressed as values between 0 and 10 times 10 raised to a power that effectively
shifts the implied decimal point right or left the number of
places necessary to express the result in conventional form
(e.g., 47,572.8). The value-portion of the data is called the
mantissa. The exponent may be either negative or positive.
The concept of floating point notation has both a gain and a
loss associated with it. The gain is the ability to represent the
significant digits of data with values spanning a large dynamic
range limited only by the capacity of the exponent field. For
example, in decimal notation if the exponent field is two digits
wide, and the mantissa is five digits, a range of values (positive or negative) from 1.0000 x 10-99 to 9.9999 X 10+99 can
be accommodated. The loss is that only the significant digits
of the value can be represented. Thus there is no distinction
in this representation between the values 123451 and
123452, for example, since each would be expressed
as: 1.2345 x 105 . The sixth digit has been discarded. In most
applications where the dynamic range of values to be represented is large, the loss of significance, and hence accuracy
of results, is a minor consideration. For greater precision a
fixed point format could be chosen, although with a loss of potential dynam'c range.
3130
LJ2423I
I I I I I
J
0
The range of values that can be represented in this format is
±(2.7 x 10-20 to 9.2 X 1018 ) and zero.
STATUS REGISTER
The Am9511A contains an eight bit status register with the following bit assignments:
I I I
BUSY
SIGN
ZERO
7
6
5
i
ERROR CODE
4
3
2
o
BUSY:
Indicates that Am9511A is currently executing a command (1 = Busy).
SIGN:
Indicates that the value on the top of stack is negative
(1 = Negative).
ZERO: Indicates that the value on the top of stack is zero
(1 = Value is zero).
ERROR This field contains an indication of the validity of the
CODE: result of the last operation. The error codes are:
0000 - No error
1000 - Divide by zero
0100 - Square root or log of negative number
1100 - Argument of inverse sine, cosine, or eX too
large
XX10 - Underflow
XX01 - Overflow
CARRY: Previous operation resulted in carry or borrow from
most significant bit. (1 = Carry/Borrow, 0 = No
Carry/No Borrow)
The Am9511 is a binary arithmetic processor and requires
that floating point data be represented by a fractional mantissa value between .5 and 1 multiplied by 2 raised to an appropriate power. This is expressed as follows:
value = mantissa x 2exponent
For example, the value 100.5 expressed in this form is
0.11001001 x 27. The decimal equivalent of this value may be
computed by summing the components (powers of two) of the
mantissa and then multiplying by the exponent as shown below:
value = (2- 1 + 2-2 + 2- 5 + 2-8 ) X 27
= (0.5 + 0.25 + 0.03125 + 0.00290625) x 128
= 0.78515625 x 128
= 100.5
If the BUSY bit in the status register is a one, the other status
bits are not defined; if zero, indicating not busy, the operation is
complete and the other status bits are defined as given above.
7-71
Am9511A
Table 1.
Summary
Description
Hex Code
(sr 1)
Hex Code
(sr 0)
SADO
EC
6C
16-18
Add TOS to NOS. Result to NOS. Pop Stack.
SSUB
EO
60
30-32
Subtract TOS from NOS. Result to NOS. Pop Stack.
SMUL
EE
6E
84-94
Multiply NOS by TOS. Lower result to NOS. Pop Stack.
SMUU
F6
76
80-98
Multiply NOS by TOS. Upper result to NOS. Pop Stack.
SOIV
EF
6F
84-94
Divide NOS by TOS. Result to NOS. Pop Stack.
Command
Mnemonic
=
=
Execution
Cycles
16-BIT FIXED-POINT OPERATIONS
32-BIT FIXED-POINT OPERATIONS
DADO
AC
2C
20-22
Add TOS to NOS. Result to NOS. Pop Stack.
DSUB
AD
20
38-40
Subtract TOS from NOS. Result to NOS. Pop Stack.
Muitipiy NOS by TOS. Lower resuit to NOS. Pop StacK.
DMUL
AE
2E
194-210
DMUU
86
36
182-218
Multiply NOS by TOS. Upper result to NOS. Pop Stack.
DDIV
AF
2F
196-210
Divide NOS by TOS. Result to NOS. Pop Stack.
FADO
90
10
54-368
FSUB
91
11
70-370
Subtract TOS from NOS. Result to NOS. Pop Stack.
FMUL
92
12
146-168
Multiply NOS by TOS. Result to NOS. Pop Stack.
FDIV
93
13
154-184
Divide NOS by TOS. Result to NOS. Pop Stack.
32-BIT FLOATING-POINT PRIMARY OPERATIONS
Add TOS to NOS. Result to NOS. Pop Stack.
32-BIT FLOATING-POINT DERIVED OPERATIONS
SOAT
81
01
782-870
SIN
82
02
3796-4808
Square Root of TOS. Result to TOS.
Sine of TOS. Result to TOS.
COS
83
03
3840-4878
Cosine of TOS. Result to TOS.
TAN
84
04
4894-5886
Tangent of TOS. Result to TOS.
ASIN
85
05
6230-7938
Inverse Sine of TOS. Result to TOS.
ACOS
86
06
6304-8284
Inverse Cosine of TOS. Result to TOS.
ATAN
87
07
4992-6536
Inverse Tangent of TOS. Result to TOS.
LOG
88
08
4474-7132
Common Logarithm of TOS. Result to TOS.
LN
89
09
4298-6956
Natural Logarithm of TOS. Result to TOS.
EXP
8A
OA
3794-4878
e raised to power in TOS. Result to TOS.
PWA
88
08
8290-12032
NOS raised to power in TOS. Result to NOS. Pop Stack.
NOP
80
00
FIXS
9F
1F
FIXD
9E
1E
FLTS
90
10
FLTD
9C
1C
DATA AND STACK MANIPULATION OPERATIONS
4
No Operation. Clear or set SVREO.
90-214 }
90-336
Convert TOS from floating point format to fixed point format.
62-156 }
56-342
Convert TOS from fixed point format to floating point format.
CHSS
F4
74
CHSD
84
34
22-24 }
26-28
Change sign of fixed point operand on TOS.
CHSF
95
15
16-20
Change sign of floating point operand on TOS.
PTOS
F7
77
PTOO
87
37
16 }
20
PTOF
97
17
20
POPS
F8
78
POPD
88
38
12
POPF
98
18
12
XCHS
F9
79
XCHD
89
39
18 }
26
XCHF
99
19
26
PUPI
9A
1A
16
1O}
Push stack. Duplicate NOS in TOS.
Pop stack. Old NOS becomes new TOS. Old TOS rotates to bottom.
Exchange TOS and NOS.
Push floating point constant
7-72
7T
onto TOS. Previous TOS becomes NOS.
Am9S11A
cles when running at a 3MHz rate translates to 14 microseconds (44 x 32/Ls = 14/Ls). Variations in execution cycles
reflect the data dependency of the algorithms.
COMMAND DESCRIPTIONS
This section contains detailed descriptions of the APU commands. They are arranged in alphabetical order by command
mnemonic. In the descriptions, TOS means Top Of Stack and
NOS means Next On Stack.
In some operations exponent overflow or underflow may be
possible. When this occurs, the exponent returned in the result will be 128 greater or smaller than its true value.
All derived functions except Square Root use Chebyshev
polynomial approximating algorithms. This approach is used
to help minimize the internal microprogram, to minimize the
maximum error values and to provide a relatively even distribution of errors over the data range. The basic arithmetic
operations are used by the derived functions to compute the
various Chebyshev terms. The basic operations may produce
error codes in the status register as a result.
Many of the functions use portions of the data stack as
scratch storage during development of the results. Thus previous values in those stack locations will be lost. Scratch locations destroyed are listed in the command descriptions and
shown with the crossed-out locations in the Stack Contents
After diagram.
Table 1 is a summary of all the Am9S11A commands. It shows
the hex codes for each command, the mnemonic abbreviation, a
brief description and the execution time in clock cycles. The
commands are grouped by functional classes.
Execution times are listed in terms of clock cycles and may
be converted into time values by multiplying by the clock
period used. For example, an execution time of 44 clock cy-
The command mnemonics in alphabetical order are shown
below in Table 2.
Table 2.
Command Mnemonics in Alphabetical Order.
ACOS
ASIN
ATAN
CHSD
CHSF
CHSS
COS
DADD
DDIV
DMUL
DMUU
DSUB
EXP
FADD
FDIV
FIXD
FIXS
FLTD
FLTS
FMUL
FSUB
LOG
LN
NOP
POPD
POPF
POPS
PTOD
PTOF
PTOS
PUPI
PWR
SADD
SDIV
SIN
SMUL
SMUU
SQRT
SSUB
TAN
XCHD
XCHF
XCHS
ARCCOSINE
ARCSINE
ARCTANGENT
CHANGE SIGN DOUBLE
CHANGE SIGN FLOATING
CHANGE SIGN SINGLE
COSINE
DOUBLE ADD
DOUBLE DIVIDE
DOUBLE MULTIPLY LOWER
DOUBLE MULTIPLY UPPER
DOUBLE SUBTRACT
EXPONENTIATION (eX)
FLOATING ADD
FLOATING DIVIDE
FIX DOUBLE
FIX SINGLE
FLOAT DOUBLE
FLOAT SINGLE
FLOATING MULTIPLY
FLOATING SUBTRACT
7-73
COMMON LOGARITHM
NATURAL LOGARITHM
NO OPERATION
POP STACK DOUBLE
POP STACK FLOATING
POP STACK SINGLE
PUSH STACK DOUBLE
PUSH STACK FLOATING
PUSH STACK SINGLE
PUSH 7T'
POWER (X Y )
SINGLE ADD
SINGLE DIVIDE
SINE
SINGLE MULTIPLY LOWER
SINGLE MULTIPLY UPPER
SQUARE ROOT
SINGLE SUBTRACT
TANGENT
EXCHANGE OPERANDS DOUBLE
EXCHANGE OPERANDS FLOATING
EXCHANGE OPERANDS SINGLE
Am9511A
ACOS
ATAN
32-BIT FLOATING-POINT INVERSE COSINE
32-BIT FLOATING-POINT
INVERSE TANGENT
7
6
5
4
3
2
°°
° ° ° °
7
Binary Coding: I sr
Hex Coding:
86 with sr = 1
06 with sr =
Execution Time: 6304 to 8284 clock cycles
Description:
The 32-bit floating-point operand A at the TOS is replaced by the
32-bit floating-point inverse cosine of A. The result R is a value in
radians between and 71". Initial operands A, B, C and D are lost.
ACOS will accept all input data values within the range of -1.0 to
+ 1.0. Values outside this range will return an error code of 1100
in the status register.
Accuracy: ACOS exhibits a maximum relative error of 2.0 x
10- 7 over the valid input data range.
Status Affected: Sign, Zero, Error Field
Hex Coding:
2
°
87 with sr = 1
07 with sr =
Execution Time: 4992 to 6536 clock cycles
Description:
Tr.a 32-bit floating-point operand A at the TOS is replaced by the
32-bit floating-point inverse tangent of A. The result R is a value in
radians between -71"/2 and +71"/2. Initial operands A, C and Dare
lost. Operand B is unchanged.
AT AN will accept all input data values that can be represented in
the floating point format.
Accuracy: ATAN exhibits a maximum relative error of 3.0 x
10- 7 over the input data range.
Status Affected: Si.gn, Zero
°
STACK CONTENTS
A
543
Binary Coding: LI_s_r...L..._0--L_0..--L_0..--L_O_L__l--L_----l
°
BEFORE
6
°
STACK CONTENTS
AFTER
BEFORE
R
A
-TOS-
AFTER
~------~
B
B
C
C
D
-TOS---
R
L------~
B
D
1---32-1
1--32-1
1 - 32 ---t.~1
1-32-1
ASIN
CHSD
32-BIT FLOATING-POINT INVERSE SINE
32-BIT FIXED-POINT SIGN CHANGE
7
543
2
°
Binary Coding: LI_sr---L_0..--L_0--L_O_l-0---.,;'------l_0---L_---'
0---L_..--L_--L_0_1-_'--0-L_0----'
Binary Coding: LI_s_r-L._
Hex Coding:
Hex Coding:
6
7
85 with sr = 1
05 with sr =
Execution Time: 6230 to 7938 clock cycles
Description:
The 32-bit floating-point operand A at the TOS is replaced by the
32-bit floating-point inverse sine of A. The result R is a value in
radians between -71"/2 and +71"/2. Initial operands A, B, C and D
are lost.
ASIN will accept all input data values within the range of -1.0 to
+ 1.0. Values outside this range will return an error code of 1100
in the status register.
Accuracy: ASIN exhibits a maximum relative error of 4.0 x
10- 7 over the valid input data range.
Status Affected: Sign, Zero, Error Field
~------~
-TOS-
3
2
°
°
STACK CONTENTS
AFTER
BEFORE
R
A
~------~
B
B
C
C
D
1---32-1
4
Status Affected: Sign, Zero, Error Field (overflow)
STACK CONTENTS
A
5
B4 with sr = 1
34 with sr =
Execution Time: 26 to 28 clock cycles
Description:
The 32-bit fixed-point two's complement integer operand A at
the TOS is subtracted from zero. The result R replaces A at
the TOS. Other entries in the stack are not disturbed.
Overflow status will be set and the TOS will be returned unchanged when A is input as the most negative value possible
in the format since no positive equivalent exists.
°
BEFORE
6
1--32-1
7-74
-TOS
---
AFTER
R
B
C
D
D
1-32-1
1---32-1
Am9S11A
cos
CHSF
32-81T FLOATING-POINT SIGN CHANGE
7
6
5
4
32-81T FLOATING-POINT COSINE
320
7
6
5
4
3
2
Binary Coding: LI_s_r---"-_°----'-_°--'-_--'-_°----'-_---"-_°----'_1-----'
Binary Coding: I sr
°
°
0
°
°
Hex Coding:
Hex Coding:
95 with sr = 1
15 with sr = °
Execution Time: 16 to 20 clock cycles
Description:
The sign of the mantissa of the 32-bit floating-point operand A at
the TOS is inverted. The result R replaces A at the TOS. Other
stack entries are unchanged.
If A is input as zero (mantissa MSB = 0), no change is made.
Status Affected: Sign, Zero
83 with sr = 1
03 with sr = °
Execution Time: 3840 to 4878 clock cycles
Description:
The 32-bit floating-point operand A at the TOS is replaced by
R, the 32-bit floating-point cosine of A. A is assumed to be in
radians. Operands A, C and D are lost. B is unchanged.
The COS function can accept any input data value that can
be represented in the data format. All input values are range
reduced to fall within an interval of -rr/2 to +rr/2 radians.
Accuracy: COS exhibits a maximum relative error of 5.0 x
10- 7 for all input data values in the range of -2rr
to +217 radians.
Status Affected: Sign, Zero
STACK CONTENTS
BEFORE
AFTER
A
R
---- TOS----
B
B
C
C
°
STACK CONTENTS
D
BEFORE
D
1 - - - 32--"".-11
AFTER
A
1---32---1
-TOS-
R
B
B
C
D
CHSS
•I
1---32
16-81T FIXED-POINT SIGN CHANGE
7
6
5
4
Binary Coding: I sr
2
3
•I
DADO
°
32-81T FIXED-POINT ADD
° °
°
1---32
~----'--~-----'-----"--~-~-~~
Hex Coding:
F4 with sr = 1
74 with sr = °
Execution Time: 22 to 24 clock cycles
Description:
16-bit fixed-point two's complement integer operand A at the TOS
is subtracted from zero. The result R replaces A at the TOS. All
other operands are unchanged.
Overflow status will be set and the TOS will be returned unchanged when A is input as the most negative value possible in
the format since no positive equivalent exists.
Status Affected: Sign, Zero, Overflow
7
Binary Coding:
A
..
TOS
.
5
3
4
2
°
LI_sr---1._0......L_--'-_O_.L...----'_---'_o~_o____'
Hex Coding:
AC with sr = 1
2C with sr = °
Execution Time: 20 to 22 clock cycles
Description:
The 32-bit fixed-point two's complement integer operand A at the
TOS is added to the 32-bit fixed-point two's complement integer
operand B at the NOS. The result R replaces operand B and the
Stack is moved up so that R occupies the TOS. Operand B is lost.
Operands A, C and D are unchanged. If the addition generates a
carry it is reported in the status register.
If the result is too large to be represented by the data format, the
least significant 32 bits of the result are returned and overflow
status is reported.
Status Affected: Sign, Zero, Carry, Error Field
STACK CONTENTS
BEFORE
6
AFTER
R
B
B
C
C
D
D
BEFORE
E
E
A
STACK CONTENTS
AFTER
-TOS-
R
F
F
B
C
G
G
C
D
H
H
D
1---32
7-75
A
.1
1•
32
.1
Am9511A
DDIV
DMUU
32-BIT FIXED-POINT DIVIDE
32-BIT FIXED-POINT MULTIPLV, UPPER
7
6
°
Binary Coding: I sr
5
4
3
°
2
__ __ __ __ __
__
Hex Coding:
AF with sr = 1
2F with sr =
Execution Time: 196 to 210 clock cycles when A oft
18 clock cycles when A = 0.
Description:
The 32-bit fixed-point two's complement integer operand B at
NOS is divided by the 32-bit fixed-point two's complement integer operand A at the TOS. The 32-bit integer quotient R replaces B and the stack is moved up so that R occupies the
TOS. No remainder is generated. Operands A and B are lost.
Operands C and D are unchanged.
If A is zero, R is set equal to B and the divide-by-zero error
status will be reported. If either A or B is the most negative
value possible in the format, R will be meaningless and the
overflow error status will be reported.
Status Affected: Sign, Zero, Error Field
L-~
~
~
°
~
~
BEFORE
A
~~~
C
C
D
A
1---32-1
°
432
--'--_°----'__----'__°~__----'______'_____'___o____,
Hex Coding:
AE with sr = 1
2E with sr =
Execution Time: 194 to 210 clock cycles
Description:
The 32-bit fixed-point two's complement integer operand A at the
TOS is multiplied by the 32-bit fixed-point two's complement integer operand B at the NOS. The 32-bit least significant half of the
product R replaces B and the stack is moved up so that R occupies the TOS. The most significant half of the product is lost.
Operands A and B are lost.· Operands C and D are unchanged.
The overflow status bit is set if the discarded upper half was
non-zero. If either A or B is the most negative value that can
be represented in the format, that value is returned as Rand
the overflow status is set.
Status Affected: Sign, Zero, Overflow
°
STACK CONTENTS
-TOS--
AFTER
R
C
C
D
1--32-1
DSUB
32-BIT FIXED-POINT SUBTRACT
Binary Coding: I-I_s_r
A
°
B
32-BIT FIXED-POINT MULTIPLV, LOWER
5
°
°
D
DMUL
6
2
-TOS--
1--32-1
7
3
°
1 - - - 32---11--11
D
BEFORE
4
ST ACK CONTENTS
BEFORE
R
B
°
5
B6 with sr = 1
36 with sr =
Execution Time: 182 to 218 clock cycles
Description:
The 32-bit fixed-point two's complement integer operand A at
the TOS is multiplied by the 32-bit fixed-point two's complement integer operand B at the NOS. The 32-bit most significant half of the product R replaces B and the stack is moved
up so that R occupies the TOS. The least significant half of
the product is lost. Operands A and B are lost. Operands C
and D are unchanged.
If A or B was the most negative value possible in the format,
overflow status is set and R is meaningless.
Status Affected: Sign, Zero, Overflow
Hex Coding:
AFTER
-TOS--
6
Binary Coding: I sr
~
°
STACK CONTENTS
7
°
7
6
5
4
3
2
°
Bi nary Coding: IL-s_r-'--_0----'_____'___0____'______'______'__0---'-__----'
Hex Coding:
AD with sr = 1
2D with sr =
Execution Time: 38 to 40 clock cycles
Description:
The 32-bit fixed-point two's complement operand A at the
TOS is subtracted from the 32-bit fixed-point two's complement operand B at the NOS. The difference R replaces
operand B and the stack is moved up so that R occupies the
TOS. Operand B is lost. Operands A, C and D are unchanged.
If the subtraction generates a borrow it is reported in the carry
status bit. If A is the most negative value that can be represented in the format the overflow status is set. If the result
cannot be represented in the data format range, the overflow
bit is set and the 32 least significant bits of the result are returned as R.
Status Affected: Sign, Zero, Carry, Overflow
AFTER
BEFORE
R
A
°
STACK CONTENTS
--TOS--
AFTER
R
C
B
C
B
C
D
C
D
D
A
1--32-1
1----32-1
D
1--'----32-1
1---32-1
7-76
Am9511A
EXP
FDIV
32-81T FLOATING-POINT eX
32-81T FLOATING-POINT DIVIDE
3
6
7
5
3
4
2
°
°
Binary Coding~ LI_s_r-,-_0_,--0--",--0_,--_,--0_LI·_1--,1_0---,
Binary Codi ng: LI_s_r-L-_0---..JL-0---..JL----1_0---..JL-0_L----1_---.J
Hex Coding:
Hex Coding:
7
6
5
4
2
93 with sr = 1
13 with sr =
Execution Time: 154 to 184 clock cycles for A 1=
22 clock cycles for A =
Description:
32-bit floating-point operand B at NOS is divided by 32-bit
floating-paint operand A at the TOS. The result R replaces Band
the stack is moved up so that R occupies the TOS. Operands A
and B are lost. Operands C and D are unchanged.
If operand A is zero, R is set equal to B and the divide-by-zero
error is reported in the status register. Exponent overflow or
underflow is reported in the status register, in which case the
mantissa portion of the result is correct and the exponent portion
is offset by 128.
Status Affected: Sign, Zero, Error Field
8A with sr = 1
OA with sr =
Execution Time: 3794 to 4878 clock cycles for IAI ~ 1.0 x 2 5
34 clock cycles for IAI > 1.0 x 2 5
Description:
The base of natural logarithms, e, is raised to an exponent value
specified by the 32-bit floating-point operand A at the TOS. The
result R of eA replaces A. Operands A, C and D are lost. Operand
B is unchanged.
EXP accepts all input data values within the range of -1.0 x 2+ 5
to + 1.0 X 2+5. Input values outside this range will return a code of
1100 in the error field of the status register.
Accuracy: EXP exhibits a maximum relative error of 5.0 x
10- 7 over the valid input data range.
Status Affected: Sign, Zero, Error Field
°
STACK CONTENTS
BEFORE
A
-TOS--
B
°
°
°
STACK CONTENTS
AFTER
AFTER
BEFORE
R
A
B
B
C
C
D
C
D
R
-TOS-
D
1~32----1
1 - - - 3 2 ----I
1 - - -32----1
1---32----1
FADD
FIXD
32-81T FLOATING-POINT ADD
32-81T FLOATING-POINT TO
32-81T FIXED-POINT CONVERSION
7
6
5
4
320
7
Bi nary Coding :1L_s_r-'-_0--"_0--"'----'_0---'_0--'_0--'_0--,
Hex Coding:
90 with sr = 1
10 with sr =
Execution Time: 54 to 368 clock cycles for A "#
24 clock cycles for A =
Description:
32-bit floating-paint operand A at the TOS is added to 32-bit
floating-paint operand B at the NOS. The result R replaces Band
the stack is moved up so that R occupies the TOS. Operands A
and B are lost. Operands C and D are unchanged.
Exponent alignment before the addition and normalization of the
result accounts for the variation in execution time. Exponent
overflow and underflow are reported in the status register, in
which case the mantissa is correct and the exponent is offset by
128.
Status Affected: Sign, Zero, Error Field
°
°
BEFORE
STACK CONTENTS
6
5
4
3
°
2
Binary Coding: LI_s_r-'-_0---..JL-0--'_---..J_---..J_ _L----..JL-0-......l
Hex Coding:
9E with sr = 1
1E with sr =
Execution Time: 90 to 336 clock cycles
Description:
32-bit floating-paint operand A at the TOS is converted to a
32-bit fixed-point two's complement integer. The result R replaces A. Operands A and D are lost. Operands Band Care
unchanged.
If the integer portion of A is larger than 31 bits when converted, the overflow status will be set and A will not be
changed. Operand D, however, will still be lost.
Status Affected: Sign, Zero Overflow
°
°
STACK CONTENTS
AFTER
AFTER
BEFORE
R
A
B
C
B
B
C
D
C
C
A
-TOS-
D
1---32---1
-TOS-
R
D
1 - - - 32----1
1 - -32----1
7-77
1---32-1
Am9S11A
FIXS
FLTS
32-BIT FLOATING-POINT TO
16-BIT FIXED-POINT CONVERSION
16-BIT FIXED-POINT TO
32-BIT FLOATING-POINT CONVERSION
Binary Coding:
7
6
5
I sr
0
0
4
3
o
2
Binary Coding:
~~--~--~--~--~--~--~~
Hex Coding:
9F with sr = 1
1F with sr = 0
Execution Time: 90 to 214 clock cycles
Description:
32-bit floating-paint operand A at the TOS is converted to a
16-bit fixed-point two's complement integer. The result R replaces the lower half of A and the stack is moved up by two
bytes so that R occupies the TOS. Operands A and Dare
lost. Operands Band C are unchanged, but appear as upper
(u) and lower (I) halves on the 16-bit wide stack if they are
32-bit operands.
If the integer portion of A is larger than 15 bits when converted, the overflow status will be set and A will not be
changed. Operand D, however, will still be lost.
Status Affected: Sign, Zero, Overflow
STACK CONTENTS
BEFORE
-
A
B
1-1- - - -
BEFORE
A
BI
Cu
32-----..~1
4
3
2
0
0
STACK CONTENTS
.
AFTER
Ru
TOS
RI
B
R
D
5
0
9D with sr = 1
1D with sr = 0
Execution Time: 62 to 156 clock cycles
Description:
16-bit fixed-point two's complement integer A at the TOS is
converted to a 32-bit floating-point number. The lower half of the
result R (RI) replaces A, the upper half (Ru) replaces H and the
stack is moved down so that Ru occupies the TOS. Operands A,
F, G and H are lost. Operands B, C, D and E are unchanged.
Status Affected: Sign, Zero
Bu
C
6
0
Hex Coding:
AFTER
..
TOS
7
I sr
C
B
D
C
E
D
F
E
G
H
CI
FMUL
32-BIT FLOATING-POINT
MULTIPLY
FLTD
32-BIT FIXED-POINT TO
32-BIT FLOATING-POINT CONVERSION
Binary Coding:
7
6
5
I sr
0
o
4
3
2
o
Binary Coding:
~~--~--~--~--~--~--~~
A
---TOS~
5
0
0
4
3
2
0
0
o
o
92 with sr = 1
12 with sr = 0
Execution Time: 146 to 168 clock cycles
Description:
32-bit floating-paint operand A at the TOS is multiplied by the
32-bit floating-point operand B at the NOS. The normalized result
R replaces B and the stack is moved up· so that R occupies the
TOS. Operands A and B are lost. Operands C and D are unchanged.
Exponent overflow or underflow is reported in the status register,
in which case the mantissa portion of the result is correct and the
exponent portion is offset by 128.
Status Affected: Sign, Zero, Error Field
STACK CONTENTS
AFTER
BEFORE
9C with sr = 1
1C with sr = 0
Execution Time: 56 to 342 clock cycles
Description:
32-bit fixed-point two's complement integer operand A at the TOS
is converted to a 32-bit floating-point number. The result R replaces A atthe TOS. Operands A and D are lost. Operands Band
C are unchanged.
Status Affected: Sign, Zero
STACK CONTENTS
6
Hex Coding:
o
o
Hex Coding:
BEFORE
7
I sr
AFTER
A
R
-TOS-
R
B
B
B
C
C
C
C
D
D
1--32-1
D
1--- 32 - -.....~I
1---32---1.-1
7-78
1---32-1
Am9S11A
FSUB
LN
32-BIT FLOATING-POINT SUBTRACTION
32-BIT FLOATING-POINT
NATURAL LOGARITHM
6
7
3
4
5
2
°
7
Binary Coding: LI_s_r-L._0.--J_0.--J_.--J,--0.--J_o_L-0---.1_--1
Hex Coding:
91 with sr = 1
11 with sr =
Execution Time: 70 to 370 clock cycles for A 'I
26 clock cycles for A =
Description:
32-bit floating-point operand A at the TOS is subtracted from
32-bit floating-point operand B at the NOS. The normalized
difference R replaces B and the stack is moved up so that R
occupies the TOS. Operands A and B are lost. Operands C
and D are unchanged.
Exponent alignment before the subtraction and normalization
of the result account for the variation in execution time.
Exponent overflow or underflow is reported in the status register in which case the mantissa portion of the result is correct
and the exponent portion is offset by 128.
Status Affected: Sign, Zero, Error Field (overflow)
°
A
Hex Coding:
3
C
C
D
°
STACK CONTENTS
AFTER
A
-TOS--
R
~------------~
D
B
D
LOG
1-32---1--11
32-BIT FLOATING-POINT
COMMON LOGARITHM
Binary Coding: I sr I
Hex Coding:
5
4
3
° ° °
I
I
°
°
° ° °
NO
OPERATION
°
°
A
__________
STACK CONTENTS
~
7
5
4
3
2
° ° ° ° ° ° °°
°
~
B
C
D
1-32----1
6
Binary Coding: I sr
Hex Coding:
80 with sr = 1
00 with sr =
Execution Time: 4 clock cycles
Description:
The NOP command performs no internal data manipulations. It
may be used to set or clear the service request interface line
without changing the contents of the stack:
Status Affected: The status byte is cleared to all zeroes.
AFTER
---- TOS - - -L __________
R
B
1--.....---32-1
NOP
2
88 with sr = 1
08 with sr =
Execution Time: 4474 to 7132 clock cycles for A>
20 clock cycles for A ~
Description:
The 32-bit floating-paint operand A at the TOS is replaced by R,
the 32-bit floating-point common logarithm (base 10) of A.
Operands A, C and D are lost. Operand B is unchanged.
The LOG function accepts any positive input data value that can
be represented by the data format. If LOG of a non-positive value
is attempted an error status of 0100 is returned.
Accuracy: LOG exhibits a maximum absolute error of 2.0 x 10-7
for the input range from 0.1 to 10, and a maximum
relative error of 2.0 x 10- 7 for positive values less
than 0.1 or greater than 10.
Status Affected: Sign, Zero, Error Field
BEFORE
L----------
C
1-32-1
6
°
BEFORE
B
7
°
°
R
~----------~
B
1-32-1
2
Status Affected: Sign, Zero, Error Field
~-------~
~
4
89 with sr = 1
09 with sr =
Execution Time: 4298 to 6956 clock cycles for A >
20 clock cycles for A~
Description:
The 32-bit floating-point operand A at the TOS is replaced by
R, the 32-bit floating"point natural logarithm (base e) of A.
Operands A, C and D are lost. Operand B is unchanged.
The LN function accepts all positive input data values that can
be represented by the data format. If LN of a non-positive
number is attempted an error status of 0100 is returned.
Accuracy: LN exhibits a maxi~um absolute error of 2 x 10- 7
for the input range from e- 1 to e, and a maximum
relative error of 2.0 x 10-7 for positive values less
than e- 1 or greater than e.
AFTER
~TOS~
5
Binary Coding: LI_s_r-L_O__'--0.--J'--0----l'-----''--O_L-0--...J'--_
°
°
STACK CONTENTS
BEFORE
6
1 - 3 2 - - - a..~1
7-79
II
Am9S11A
POPD
POPS
32-81T
STACK POP
16-81T
STACK POP
7
Binary Coding:
6
5
3
4
2
6
7
°
Binary Coding:
_s_r--'--_0--1._--'-_--'-_-'-_0_'--0---'_0---'
L-I
5
4
2
3
°
_s_r-'--_-'--_...1..-_-'--_.1....-0_'--0---'_0--'
L-I
B8 with sr = 1
38 with sr =
Execution Time: 12 clock cycles
Description:
The 32-bit stack is moved up so that the old NOS becomes the
new TOS. The previous TOS rotates to the bottom of the stack. All
operand values are unchanged. POPD and POPF execute the
same operation.
Status Affected: Sign, Zero
°
F8 with sr = 1
78 with sr =
Execution Time: 10 clock cycles
Description:
The 16-bit stack is moved up so that the old NOS becomes the
new TOS. The previous TOS rotates to the bottom of the stack. All
operand values are unchanged.
Status Affected: Sign, Zero
STACK CONTENTS
STACK CONTENTS
Hex Coding:
/'
BEFORE
Hex Coding:
AFTER
BEFORE
°
.
AFTER
B
A
c
B
c
D
C
D
D
A
D
E
1---32-1
1---32-1
E
F
F
G
A
----TOS--
B
1
G
H
H
A
~16--1
1--16--1
PTOD
32-81T
STACK POP
PUSH 32-81T
TOS ONTO STACK
6
sr
5
4
3
° °
°
7
2
°
° ° °
B
C
POPF
7
Binary Coding:
TOS
Binary Coding:
6
I sr
°
4
3
2
°
°
98 with sr = 1
18 with sr =
Execution Time: 12 clock cycles
Description:
The 32-bit stack is moved up so that the old NOS becomes the
new TOS. The old TOS rotates to the bottom of the stack. All
operand values are unchanged. POPF and POPD execute the
same operation.
Status Affected: Sign, Zero
B7 with sr = 1
37 with sr =
Execution Time: 20 clock cycles
Description:
The 32-bit stack is moved down and the previous TOS is
copied into the new TOS location. Operand D is lost. All other
operand values are unchanged. PTOD and PTOF execute the
same operation.
Status Affected: Sign, Zero
STACK CONTENTS
STACK CONTENTS
Hex Coding:
Hex Coding:
5
°
AFTER
AFTER
BEFORE
B
A
C
B
C
D
C
B
D
A
D
C
BEFORE
A
----TOS--
B
1---32
.1
1•
32-1
1-32
7-80
----TOS---
A
A
• 1
1-32
• 1
Am9511A
PTOF
PUPI
PUSH 32-BIT
TOS ONTO STACK
PUSH 32-BIT
FLOATING-POINT 11"
7
5
6
4
3
° °
Hex Coding:
97 with sr
1
17 with sr
°
Execution Time: 20 clock cycles
Binary Coding:
1
2
7
°
°
sr
6
5
4
3
°
2
Binary Coding: ,--I_sr---'-_O---'-_O--'--_----'-_-L-_o----''-------'-_o--'
Hex Coding:
Description:
The 32-bit stack is moved down and the previous TOS is copied
into the new TOS location. Operand D is lost. All other operand
values are unchanged. PTOF and PTOD execute the same operation.
Status Affected: Sign, Zero
9A with sr = 1
1A with sr =
Execution Time: 16 clock cycles
Description:
The 32-bit stack is moved down so that the previous TOS occupies the new NOS location. 32-bit floating-point constant 1T is
entered into the new TOS location. Operand D is lost. Operands
A, Band C are unchanged.
Status Affected: Sign, Zero
STACK CONTENTS
STACK CONTENTS
=
=
BEFORE
AFTER
BEFORE
°
AFTER
A
A
B
A
B
c
B
C
B
D
c
D
C
1-32-1
1-32--1
1-32-1
1-1--32-1
A
---TOS---
PTOS
PUSH 16-BIT
TOS ONTO STACK
7
6
543
2
°
Binary Coding: IL-sr---'-_---'--_---'-_---'-_o---'_---'_---'-_--'
Hex Coding:
F7 with sr = 1
77 with sr =
Execution Time: 16 clock cycles
Description:
The 16-bit stack is moved down and the previous TOS is copied
into the new TOS location. Operand H is lost and all other
operand values are unchanged.
Status Affected: Sign, Zero
°
STACK CONTENTS
BEFORE
A
B
.
AFTER
TOS
A
A
C
B
D
C
E
D
F
E
G
F
H
G
7-81
---TOS-
A
Am9S11A
PWR
SADD
32-BIT
FLOATING-POINT X Y
16-BIT
FIXED-POINT ADD
76543210
7
6
543
°
2
Binary COding:l'---_s_r-'--_o---'_o---'_o---'_---'_o---'l_iIiJ
Binary Codi ng: Ll_s_r--1-_---L-_--1-_0----'_----'_ _L--0---'_0---'
Hex Coding:
Hex Coding:
88 with sr = 1
OB with sr =
Execution Time: 8290 to 12032 clock cycles
Description:
32-bit floating-point operand B at the NOS is raised to the power
specified by the 32-bit floating-point operand A at the TOS. The
result R of BA replaces B and the stack is moved up so that R
occupies the TOS. Operands A, B, and D are lost. Operand C is
unchanged.
The PWR function accepts all input data values that can be
represented in the data format for operand A and all positive
values for operand B. If operand B is non-positive an error status
of 0100 will be returned. The EXP and LN functions are used to
implement PWR using the relationship BA = EXP [A(LN B)].
Thus if the term [A(LN B)] is outside the range of -1.0 x 2+ 5 to
+ 1.0 X 2+ 5 an error status of 11 OOwill be returned. Underflow and
overflow conditions can occur.
EC with sr = 1
6C with sr =
Execution Time: 16 to 18 clock cycles
Description:
16-bit fixed-point two's complement integer operand A at the
TOS is added to 16-bit fixed-point two's complement integer
operand B at the NOS. The result R replaces B and the stack
is moved up so that R occupies the TOS. Operand B is lost.
All other operands are unchanged.
If the addition generates a carry bit it is reported in the status
register. If an overflow occurs it is reported in the status register and the 16 least significant bits of the result are returned.
°
°
Status Affected: Sign, Zero, Carry, Error Field
Accuracy: The error performance for PWR is a function of
the LN and EXP performance as expressed by:
I(Relative Error)pWRI= I(Relative Error)EXp+IA(Absolute
Error)LNI
The maximum relative error for PWR occurs when
A is at its maximum value while [A(LN B)] is near
1.0 x 2 5 and the EXP error is also at its maximum. For most practical applications the relative
error for PWR will be less than 7.0 x 10- 7 •
STACK CONTENTS
Status Affected: Sign, Zero, Error Field
A
A
--TOS-
B
R
C
C
D
AFTER
D
E
R
E
F
C
F
G
G
H
H
A
C
D
1-1-'---32-1
TOS
B
STACK CONTENTS
BEFORE
AFTER
BEFORE
11---- 32---1
1--16--1
7-82
Am9S11A
SDIV
SIN
16-BIT
FIXED-POINT DIVIDE
32-BIT
FLOATING-POINT SINE
a
l'--sr--'-_--'-_-----.l._O---'-_--'-_------'_~_~
7
Binary Coding:
6
5
4
3
2
Binary Coding:
Hex Coding:
EF with sr = 1
6F with sr = 0
Execution Time: 84 to 94 clock cycles for A =j 0
14 clock cycles for A = 0
Description:
16-bit fixed-point two's complement integer operand B at the
NOS is divided by 16-bit fixed-point two's complement integer
operand A at the TOS. The 16-bit integer quotient R replaces B
and the stack is moved up so that R occupies the TOS. No
remainder is generated. Operands A and B are lost. All other
operands are unchanged.
If A is zero, R will be set equal to B and the divide-by-zero error
status will be reported.
Status Affected: Sign, Zero, Error Field
7
6
5
4
3
2
0
I sr
0
0
0
0
0
a
Hex Coding:
82 with sr = 1
02 with sr = a
Execution Time: 3796 to 4808 clock cycles for IAI > 2- 12
radians
30 clock cycles for IAI .;; 2- 12 radians
Description:
The 32-bit floating-point operand A at the TOS is replaced by
R, the 32-bit floating-point sine of A. A is assumed to be in
radians. Operands A, C and 0 are lost. Operand B is unchanged.
The SIN function will accept any input data value that can be
represented by the data format. All input values are range reduced to fall within the interval -rr/2 to +rr/2 radians.
Accuracy: SIN exhibits a maximum relative error of 5.0 x
10- 7 for input values in the range of -2rr to +2rr
radians.
Status Affected: Sign, Zero
STACK CONTENTS
BEFORE
A
AFTER
TOS
R
B
C
C
0
0
E
BEFORE
E
F
A
F
G
B
G
H
C
H
1--16--1
STACK CONTENTS
><
AFTER
---TOS-
o
1-32-1
1--16--1
7-83
R
B
Am9511A
SMUL
SMUU
16-BIT FIXED-POINT
MULTIPL V, LOWER
16-BIT FIXED-POINT
MULTIPL V, UPPER
7
Binary Coding:
6
5
I sr
4
3
o
2
0
7
Binary Coding:
0
Hex Coding:
6
5
4
I sr
3
o
2
0
0
EE with sr = 1
6E with sr = 0
Execution Time: 84 to 94 clock cycles
Description:
16-bit fixed-point two's complement integer operand A at the TOS
is multiplied by the 16-bit fixed-point two's complement integer
operand B at the NOS. The 16-bit least significant half of the
product R replaces B and the stack is moved up so that R
occupies the TOS. The most significant half of the product is lost.
Operands A and B are lost. All other operands are unchanged.
The overflow status bit is set if the discarded upper half was
non-zero. If either A or B is the most negative value that can be
represented in the format, that value is returned as R and the
overflow status is set.
Status Affected: Sign, Zero, Error Field
F6 with sr = 1
76 with sr = 0
Execution Time: 80 to 98 clock cycles
Description:
16-bit fixed-point two's complement integer operand A at the
TOS is multiplied by the 16-bit fixed-point two's complement
integer operand B at the NOS. The 16-bit most significant half
of the product R replaces B and the stack is moved up so that
R occupies the TOS. The least significant half of the product
is lost. Operands A and B are lost. All other operands are unchanged.
If either A or B is the most negative value that can be represented in the format, that value is returned as R and the
overflow status is set.
Status Affected: Sign, Zero, Error Field
STACK CONTENTS
STACK CONTENTS
BEFORE
Hex Coding:
AFTER
BEFORE
R
A
B
C
B
C
C
D
C
D
D
E
D
E
E
F
E
F
F
G
F
G
G
H
G
H
H
><
H
><
A
TOS
1--16--1
1--16--1
7-84
AFTER
TOS
R
Am9511A
SQRT
TAN
32-BIT FLOATING-POINT SQUARE ROOT
32-BIT FLOATING-POINT TANGENT
7
6
5
4
3
2
7
° ° ° ° ° ° °
81 with sr
1
Binary Coding: 1 sr
Hex Coding:
=
Hex Coding:
STACK CONTENTS
AFTER
A
---TOS-
R
B
B
C
C
D
I ..
1•
32-1
32-1
SSUB
16-BIT FIXED-POINT SUBTRACT
7
6
5
4
Hex Coding:
AFTER
A
TOS
R
STACK CONTENTS
AFTER
A
--TOS-
R
~----------~
B
1-.--32~ 6
C
°
STACK CONTENTS
320
BEFORE
B
ED with sr = 1
6D with sr =
Execution Time: 30 to 32 clock cycles
Description:
16-bit fixed-point two's complement integer operand A at the
TOS is subtracted from 16-bit fixed-point two's complement integer operand B at the NOS. The result R replaces B and the
stack is moved up so that R occupies the TOS. Operand B is
lost. All other operands are unchanged.
If the subtraction generates a borrow it is reported in the carry
status bit. If A is the most negative value that can be represented in the format the overflow status is set. If the result
cannot be represented in the format range, the overflow
status is set and the 16 least significant bits of the result are
returned as R.
Status Affected: Sign, Zero, Carry, Error Field
BEFORE
4
°
~------~
2
°
Binary Coding: L...I_sr-""_--L._--'-_O_'--_'----I_O-""_--'
3
5
84 with sr = 1
04 with sr =
Execution Time: 4894 to 5886 clC'ck cycles for IAI > 2- 12
radians
30 clock cycles for IAI ~ 2- 12 radians
Description:
The 32-bit floating-point operand A at the TOS is replaced by
the 32-bit floating-point tangent of A. Operand A is assumed
to be in radians. A, C and D are lost. B is unchanged.
The TAN function will accept any input data value that can be
represented in the data format. All input data values are
range-reduced to fall within -1T/4 to +1T/4 radians. TAN is unbounded for input values near odd multiples of 1T/2 and in
such cases the overflow bit is set in the status register. For
angles smaller than 2- 12 radians, TAN. returns A as the tangent of A.
Accuracy: TAN exhibits a maximum relative error of 5.0 x
10- 7 for input data values in the range of -21T to
+21T radians except for data values near odd multiples of 1T/2.
Status Affected: Sign, Zero, Error Field (overflow)
°
01 with sr =
Execution Time: 782 to 870 clock cycles
Description:
32-bit floating-point operand A at the TOS is replaced by R, the
32-bit floating-point square root of A. Operands A and D are lost.
Operands Band C are not changed.
SORT will accept any non-negative input data value that can be
represented by the data format. If A is negative an error code of
0100 will be returned in the status register.
Status Affected: Sign, Zero, Error Field
BEFORE
6
Binary Coding: L...1_sr--,-_0--L._o--,-_D_,--O_,---..J'--o--,-_o--,
D
1-32-1
XCHD
EXCHANGE 32-BIT STACK OPERANDS
7
6
5
4
3
2
°
Binary Coding: LI_sr--1_0--L__---L..._ _....l-__....l-_o--'_0--L_--'
Hex Coding:
B9 with sr = 1
39 with sr =
Execution Time: 26 clock cycles
Description:
32-bit operand A at the TOS and 32-bit operand B at the NOS
are exchanged. After execution, B is at the TOS and A is at
the NOS. All operands are unchanged. XCHD and XCHF
execute the same operation.
Status Affected: Sign, Zero
°
B
C
C
D
D
E
BEFORE
STACK CONTENTS
E
F
A
--TOS-
F
G
B
A
G
H
C
C
D
H
A
D
1--16--1
1---16--1
1-32-1
7-85
AFTER
B
Am9511A
XCHF
XCHS
EXCHANGE 32-81T
STACK OPERANDS
EXCHANGE 16-81T
STACK OPERANDS
7
Binary Coding:
6
I sr
5
4
3
° °
°
Hex Coding:
2
° °
7
°
1
6
5
4
3
2
°
Bi nary Codi ng: 1L...._sr--L_--'-_--'-_-L-_-'---o_L--0---1._-----'
99 with sr = 1
19 with sr =
Execution Time: 26 ClOCK cycles
Description:
32-bit operand A at the TOS and 32-bit operand B at the NOS
are exchanged. After execution, B is at the TOS and A is at
the NOS. All operands are unchanged. XCHD and XCHF
execute the same operation.
Status Affected: Sign, Zero
Hex Coding:
F9 with sr = 1
79 with sr =
Execution Time: 18 clock cycles
Description:
16-bit operand A at the TOS and 16-bit operand B at the NOS
are exchanged. After execution, B is at the TOS and A is at
the NOS. All operand values are unchanged.
Status Affected: Sign, Zero
°
STACK CONTENTS
BEFORE
A
STACK CONTENTS
BEFORE
AFTER
TOS
B
B
--A
C
C
AFTER
0
0
B
E
E
B
A
F
F
C
C
G
G
o
1-32-1
o
1----32-1
H
H
A
---TOS-
7-86
Am9S11A
MAXIMUM RATINGS beyond which useful life may be impaired
Storage Temperature
Ambient Temperature Under Bias
VDD with Respect to VSS
vee with
-O.5V to +15.0V
-O.5V to + 7.0V
Respect to VSS
All Signal Voltages with Respect to VSS
-O.5V to + 7.0V
2.0W
Power Dissipation (Package Limitation)
The products described by this specification include internal circuitry designed to protect input devices from damaging accumulations of
static charge. It is suggested, nevertheless, that conventional precautions be observed during storage, handling and use in order to avoid
exposure to excessive voltages.
OPERATING RANGE
Part Number
Ambient Temperature
VCC
VSS
VDD
Am9511ADC
+5.0V ±5%
+12V ±5%
Am9511ADM
+5.0V ±10%
+12V ±10%
ELECTRICAL CHARACTERISTICS Over Operating Range (Note 1)
Parameters
Description
Test Conditions
Min.
Typ.
Max.
Units
0.4
Volts
Volts
VOH
Output HIGH Voltage
10H = -2OOILA
VOL
Output LOW Voltage
10L = 3.2mA
VIH
Input HIGH Voltage
2.0
VCC
Volts
VIL
Input LOW Voltage
-0.5
0.8
Volts
IIX
Input Load Current
±10
ILA
10Z
Data Bus Leakage
3.7
VSS,.;; VI,.;; VCC
VO = O.4V
10
VO = VCC
10
50
TA = +25°C
ICC
VCC Supply Current
VDD Supply Current
95
TA = -55°C
100
50
CO
Output Capacitance
Input Capacitance
CIO
I/O Capacitance
mA
90
95
TA = O°C
TA = -55°C
CI
90
TA = O°C
TA = +25°C
IDD
ILA
mA
100
fc = 1.0MHz, Inputs = OV
7-87
pF
8
10
5
8
pF
10
12
pF
Am9511A
SWITCHING CHARACTERISTICS over operating range (Notes 2, 3)
Am9511A
Parameters
Description
TAPW
EACK LOW Pulse Width
TCDA
Min.
Am9511A-1
Max.
Min.
Max
Units
100
75
ns
C/D to AD LOW Set up Time
0
0
ns
TCDW
C/D to WA LOW Set up Time
0
0
ns
TCPH
Clock Pulse HIGH Width
200
140
ns
TCPL
Clock Pulse LOW Width
240
160
ns
TCSA
CS LOW to AD LOW Set up Time
0
0
ns
TCSW
CS LOW to WA LOW Set up Time
TCY
Clock Period
480
150
0
TDW
Data Bus Stable to WA HIGH Set up Time
TEAE
EACK LOW to END HIGH Delay
TEPW
END LOW Pulse Width (Note 4)
TOP
Data Bus Output Valid to PAUSE HIGH Delay
320
3300
ns
175
ns
ns
100 (Note 9)
200
~
ns
0
5000
400
300
0
0
ns
ns
Data
3.5TCY+50
5.5TCY+300
3.5TCY+50
5.5TCY+200
Status
1.5TCY+50
3.5TCY+300
1.5TCY+50
3.5TCY+200
ns
TPPWA
PAUSE LOW Pulse Width Aead (Note 5)
TPPWW
PAUSE LOW Pulse Width Write (Note 8)
TPA
PAUSE HIGH to AD HIGH Hold Time
0
0
ns
TPW
PAUSE HIGH to WA HIGH Hold Time
0
0
ns
TACD
AD HIGH to C/D Hold Time
0
0
ns
TACS
AD HIGH to CS HIGH Hold Time
0
0
ns
TAO
AD LOW to Data Bus ON Delay
50
50
ns
50
50
ns
100 (Note 9)
ns
150
ns
TAP
AD LOW to PAUSE LOW Delay (Note 6)
TAZ
AD HIGH to Data Bus OFF Delay
50
TSAPW
SVACK LOW Pulse Width
100
TSAA
SVACK LOW to SVAEQ LOW Delay
TWCD
WA HIGH to C/D Hold Time
60
30
ns
TWCS
WA HIGH to CS HIGH Hold Time
60
30
ns
TWO
WA HIGH to Data Bus Hold Time
ns
150
Write Inactive Time (Note 8)
TWP
WA LOW to PAUSE LOW Delay (Note 6)
Data
2.
3.
4.
5.
= 25°C, nominal supply voltages and
nominal processing parameters.
Switching parameters are listed in alphabetical order.
Test conditions assume transition times of 20ns or less, output
loading of one TTL gate plus 1OOpF and timing reference levels
of 0.8V and 2.0V.
END low pulse width is specified for EACK tied to VSS. Otherwise TEAE applies.
Minimum values shown assume no previously entered command is being executed for the data access. If a previously
entered command is being executed, PAUSE LOW Pulse Width
75
20
20
3TCY
4TCY
4TCY
150
6.
7.
8.
9.
7-88
ns
200
3TCY
NOTES
1. Typical values are for TA
50
300
II Command
TWI
200
ns
ns
100 (Note 9)
ns
is the time to complete execution plus the time shown. Status
may be read at any time without exceeding the time shown.
PAUSE is pulled low for both command and data operations.
TEX is the execution time of the current command (see the
Command Execution Times table).
PAUSE low pulse width is less than 50ns when writing into the
data port or the control port as long as the duty cycle requirement (TWI) is observed and no previous command is being
executed. TWI may be safely violated as long as the extended
TPPWW that results is observed. If a previously entered command is being executed, PAUSE LOW Pulse Width is the time
to complete execution plus the time shown.
150ns for Am9511A-1DM.
Am9511A
SWITCHING WAVEFORMS
READ OPERATIONS
CLOCK
\~~-TCS-R~---------------~
~
TRO
BUS
OATA
!-TRZ(MAX.)
-1 ~TRZ(MIN.)
rTOP
-------------------------~~~~~~~~~~~~:OU~T:PU~T~V~A~LI~D~~~~I---------MOS-048
WRITE OPERATIONS
CHIP \
SELECT
X-
~~---T-CS-W-___i------------------------------------------
COMMAND!~
DATA~
I-TCDW
!-----TPPWW------l
l--
TEX
-I ,
-_-_-~~L-~~=--------------~~~~~______
SVREQ ______________________________________________________________
(N_ot_._7)___
TSAR---I-l
i-iSAPW-j
'{ T
MOS-049
7-89
Am9511A
APPLICATION INFORMATION
The diagram in Figure 2 shows the interface connections for
the Am9511A APU with operand transfers handled by an
Am9517 DMA controller, and CPU coordination handled by an
Am9519 Interrupt Controller. The APU interrupts the CPU to
indicate that a command has been completed. When the performance enhancements provided by the DMA and Interrupt
operations are not required, the APU interface can be
simplified as shown in Figure 1. The Am9511 A APU is designed with a general purpose 8-bit data bus and interface
control so that it can be conveniently used with any general
8-bit processor.
ADDRESS BUS
CPU
C/O
Am9511A
ARITHMETIC
PROCESSOR
UNIT
iOR
R5
lOW
WR
ClK
ClK
ROY
PAUSE
cs
SYSTEM DATA BUS
Figure 1. Am9511A Minimum Configuration Example.
MOS-OSO
,0,4.,0,5.,0,6
.A7
~
C ~ffi
AO-A15
HOLD
YJ
B
~ 8 ~~
A
YO
~G~
1
HLDA
I1
AODAESSBUS
11
!
TOO
Am9517
HACK
READY
I"~ I~~ 12 I~,
AOSTEl
I~
~d
)' r
0
INT
XTAL
D~
"-- , ,
A m8224
C LOCK
SYNC
GENEA ATOR
--
ViR 0-DBIN
SYNC
f-<> ';;'""
- r--
DBIN
~
INTA
,2_;2
RESET
-r-
RDVIN IREADY
f--
RESiN
mTB
T
-
RESET
READY
~..
MEMW 10~~I
00-07
I'-L...J...
00-07
"1'1"
STSTB
DBO
DB7
t .
1
L " "" "' "" ".
r"
GINT
Am9519
INTERRUPT
IREOO
~"""""-I~'
DBO-DB7
PAUSE
1
I
j
1"-
l'
G
L
I
I
6;~E';,
DEVICES
SYSTEM DATA BUS tOeD-DBlI
ClKRESET
I
r-r?
CS SVREQ SVACK CID
f
1W
INTERRUPT
A
AD
WA
Am9511A
ARITHMETIC
PROCESSING UNIT
PAi:iSEOBO-OB7
E.ACi{
J1
~
)
V
"
Am8238
SYSTEM
CONTROLLER
JOE 00-07
-I AD~~:~~~3~~CH
I
......
CPU
....
.....
AEN
I~ ~
...
,0,8-,0,15
DMACQNTROllER
HREO
1
i:TVlCES
I~
A4-A7
AO-A3
CS
t
Am9080A
"-
AO
ER
+~
I
Figure 2. Am9511 A High Performance Configuration Example.
MOS-OSl
7-90
Am9S12
Floating-Point Processor
DISTINCTIVE CHARACTERISTICS
GENERAL DESCRIPTION
•
•
•
•
•
•
•
•
•
•
•
•
•
•
The Am9512 is a high performance floating-point processor unit
(FPU). It provides single precision (32-bit) and double precision
(64-bit) add, subtract, multiply and divide operations. It can be
easily interfaced to enhance the computational capabilities of
the host microprocessor.
Single (32-bit) and double (64-bit) precision capability
Add, subtract, multiply and divide functions
Compatible with proposed IEEE format
Easy interfacing to microprocessors
8-bit data bus
Standard 24-pin package
12V and 5V power supplies
Stack oriented operand storage
Direct memory access or programmed I/O Data Transfers
End of execution signal
Error interrupt
All inputs and outputs TTL level compatible
Advanced N-channel silicon gate MOS technology
100% MIL-STD-883 reliability assurance testing
The operand, result, status and command information transfers
take place over an 8-bit bidirectional data bus. Operands are
pushed onto an internal stack by the host processor and a command is issued to perform an operation on the data stack. The
results of this operation are available to the host processor by
popping the stack.
Information transfers between the Am9512 and the host processor can be handled by using programmed I/O or direct memory
access techniques. After completing an operation, the Am9512
activates an "end of execution" signal that can be used to interrupt the host processor.
BLOCK DIAGRAM
TWO PORT DATA STACK
8 X 17
ERR
SVACK
SVREQ
EACK
END
INTERFACE
CONTROL
RESET
C/O
cs
AD
CONTROL ROM
768 X 16
WR
PAUSE
1.405·203
ORDERING INFORMATION
Package
Type
Hermetic DIP
Maximum Clock Frequency
Ambient
Temperature
2MHz
3MHz
O°C ",; T A ",; 70°C
AM9512DC
AM9512-1DC
-55°C",; TA ",; +125°C
AM9512DM
AM9512-1DM
7-91
Am9S12
the flip-flop that generates the END output. Thus such continuous reading could conflict with internal logic setting of the END
flip-flop at the end of command execution.
CONNECTION DIAGRAM
Top View
VSS
END
VCC
ClK
EACK (End Acknowledge, Input)
EACK
This input when lOW makes the END output go lOW. As mentioned earlier HIGH on the END output signals completion of a
command execution. The END signal is derived from an internal
flip-flop which is clocked at the completion of a command. This
flip-flop is clocked to the reset state when EACK is lOW. Consequently, if EACK is tied lOW, the END output will be a pulse
that is approximately one ClK period wide.
RESET
SVACK
c/o
SVREQ
AD
ERR
WR
DO NOT
USE
cs
DBD
PAUSE
DBl
VDD
DB2
DB7
DB3
D86
DB4
DBS
Note: Pin 1 is marked for orientation.
SVREQ (Service Request, Output)
MOS·204
INTERFACE SIGNAL DESCRIPTION
A HIGH on this output indicates completion of a command. In
this sense this output is the same as the END output. However,
the SVREQ output will go HIGH at the completion of a command. This bit must be 1 for SVREQ to go HIGH. The SVREQ
can be cleared (Le., go lOW) by activating the SVACK input
lOW or initializing the device using the RESET. Also, the
SVREQ will be automatically cleared after completion of any
command that has the service request bit as o.
VCC: +5V Power Supply
VDD: +12V Power Supply
SVACK (Service Acknowledge, Input)
VSS: Ground
ClK (Clock, Input)
An external timing source connected to the ClK input provides
the necessary clocking.
A lOW on this input clears SVREQ. If the SVACK input is permanently tied lOW, it will conflict with the internal setting of the
SVREQ output. rhus the SVREQ indication cannot be relied
upon if the SVACK is tied lOW.
RESET (Reset, Input)
A HIGH on this input causes initialization. Reset terminates any
operation in progress, and clears the status register to zero. The
internal stack pointer is initialized and the contents of the stack
may be affected. After a reset the END output, the ERR output
and the SVREQ output will be lOW. For proper initialization,
RESET must be HIGH for at least five ClK periods following
stable power supply voltages and stable clock.
C/O (Command/Data Select, Input)
The c/is input together with the RD and WR inputs determines the
type of transfer to be performed on the data bus as follows:
C/D
RD
l
l
WR
Function
H
l
Push data byte into the stack
l
H
Pop data byte from the stack
H
H
l
Enter command
H
l
H
Read Status
X
l
l
Undefined
L = LOW
H = HIGH
X = DON'T CARE
END (End of Execution, Output)
A HIGH on this output indicates that execution of the current
command is complete. This output will be cleared lOW by activating the EACK input lOW or performing any read or write
operation or device initialization using the RESET. If EACK is tied
lOW, the END output will be a pulse (see EACK description).
Reading the status register while a command execution is in
progress is allowed. However any read or write operation clears
DBO-DB7 (Data Bus, Input/Output)
These eight bidirectional lines are used to transfer command,
status and operand information between the device and the host
processor. DBO is the least significant and DB7 is the most
significant bit position. HIGH on a data bus line corresponds to 1
and lOW corresponds to O.
When pushing operands on the stack using the data bus, the least
significant byte must be pushed first and most significant byte
last. When popping the stack to read the result of an operation,
the most Significant byte will be available on the data bus first and
the least significant byte will be the last. Moreover, for pushing
operands and popping results, the number of transactions must
be equal to the proper number of bytes appropriate for the chosen
format. Otherwise, the internal byte pointer will not be aligned
properly. The Am9512 single precision format requires 4 bytes
and double precision format requires 8 bytes.
ERR (Error, Output)
This output goes HIGH to indicate that the current command
execution resulted in an error condition. The error conditions
are: attempt to divide by zero, exponent overflow and exponent
underflow. The ERR output is cleared lOW on read status register operation or upon RESET.
The ERR output is derived from the error bits in the status
register. These error bits will be updated internally at an appropriate time during a command execution. Thus ERR output going
HIGH may not correspond with the completion of a command.
Reading of the status register can be performed while a command execution is in progress. However it should be noted that
reading the status register clears the ERR output. Thus reading
the status register while a command execution in progress may
result in an internal conflict with the ERR output.
7-92
Am9512
CS (Chip Select, Input)
output was HIGH, performing any read operation will make the
END output go LOW after the HIGH to LOW transition of the RD
input (assuming CS is LOW). If the ERR output was HIGH performing a status register read operation will make the ERR output LOW. This will happen after the HIGH to LOW transition of
the RD input (assuming CS is LOW).
This input must be LOW to accomplish any read or write operation
to the Am9512.
To perform a write operation, appropriate data is presented on
DBO through DB7 lines, appropriate logic level on the C/O input
and the CS input is made LOW. Whenever WR and RD inputs
are both HIGH and CS is LOW, PAUSE goes LOW. However
actual writing into the Am9512 cannot start until WR is made
LOW. After initiating the write operation by the HIGH to LOW
transition on the WR input, the PAUSE output will go HIGH
indicating the write operation has been acknowledged. The WR
input can go HIGH after PAUSE goes HIGH. The data lines, C/O
input and the CS input can change when appropriate hold time
requirements are satisfied. See 'tJrite timing diagram for details.
WR (Write, Input)
A LOW on this input is used to transfer information from the data
bus into an internal location. The CS must be LOW to accomplish
the write operation. The cio determines which internal location is
to be written. See C/O, CS input descriptions and write timing
diagram for details.
If the END output was HIGH, performing any write operation will
make the END output go LOW after the LOW to HIGH transitionaf
the WR input (assuming CS is LOW).
To perform a read operation an appropriate logic level is established on the cio input and CS is made LOW. The PAUSE output
goes LOW because WR and RD inputs are HIGH. The read
operation does not start until the RD input goes LOW. PAUSE will
go HIGH indicating that read operation is complete and the required information is available on the DBO through DB7lines. This
information will remain on the data lines as long as RD is LOW.
The RD input can return HIGH anytime after PAUSE goes
HIGH. The CS input and C/O input can change anytime after RD
returns HIGH. See read timing diagram for details. If the CS is
tied LOW permanently, PAUSE will remain LOW until the next
Am9512 read or write access.
PAUSE (Pause, Output)
This output is a handshake signal used while performing read or
write transactions with the Am9512. If the WR and RD inputs are
both HIGH, the PAUSE output goes LOW with the CS input in
anticipation of a transaction. If WR goes LOW to initiate a write
transaction with proper signals established on the DBO-DB7, C/O
inputs, the PAUSE will return HIGH indicating that the write
operation has been accomplished. The WR can be made HIGH
after this event. On the other hand, if a read operation is desired,
the RD input is made LOW after activating CS LOW and establishing proper cio input. (The PAUSE will go LOW in response to
CS going LOW.) The PAUSE will return HIGH indicating completion of read. The RD can return HIGH after this event. It should be
noted that a read or write operation can be initiated without any
regard to whether a command execution is in progress or not.
Proper device operation is assured by obeying the PAUSE output
indication as described.
RD (Read, Input)
A LOW on this input is used to read information from an internal
location and gate that information onto the data bus. The CS input
must be LOW to accomplish the read operation. The cio input
determines what internal location is of interest. See C/O, CS input
descriptions and read timing diagram for details. If the END
FUNCTIONAL DESCRIPTION
DB7 (Data Bus). These signals are gated to the internal 8-bit bus
through appropriate interface and buffer circuitry. Multiplexing
facilities exist for bidirectional communication between the internal eight and 17-bit buses. The Status Register and Command
Register are also located on the 8-bit bus.
Major functional units of the Am9512 are shown in the block
diagram. The Am9512 employs a microprogram controlled stack
oriented architecture with 17-bit wide data paths.
The Arithmetic Unit receives one of its operands from the
Operand Stack. This stack is an eight word by 17-bit two port
memory with last in - first out (LIFO) attributes. The second
operand to the Arithmetic Unit is supplied by the internal 17-bit
bus. In addition to supplying the second operand, this bidirectional bus also carries the results from the output of the Arithmetic
Unit when required. Writing into the Operand Stack takes place
from this internal 17-bit bus when required. Also connected to this
bus are the Constant ROM and Working Registers. The ROM
provides the required constants to perform the mathematical
operations while the Working Registers provide storage for the
intermediate values during command execution.
The Am9512 operations are controlled by the microprogram
contained in the Control ROM. The Program Counter supplies the
microprogram addresses and can be partially loaded from the
Command Register. Associated with the Program Counter is the
Subroutine Stack where return addresses are held during subroutine calls in the microprogram. The Microinstruction Register
holds the current microinstruction being executed. The register
facilitates pipelined microprogram execution. The Instruction Decode logic generates various internal control signals needed for
the Am9512 operation.
The Interface Control logic receives several external inputs and
provides handshake related outputs to facilitate interfacing the
Am9512 to microprocessors.
Communication between the external world and the Am9512
takes place on eight bidirectional input/output lines, DBO through
COMMAND FORMAT
The Operation of the Am9512 is controlled from the host processor by issuing instructions called commands. The command format is shown below:
OP CODE
I
I
The command consists of 8 bits; the least significant 7 bits specify
the operation to be performed as detailed in the accompanying
table. The most significant bit is the Service Request Enable bit.
This bit must be a 1 if SVREQ is to go high at end of executing a
command.
The Am9512 commands fall into three categories: Single precision arithmetic, double precision arithmetic and data manipulation. There are four arithmetic operations that can be performed
with single precision (32-bit), or double precision (54-bit)
floating-point numbers: add, subtract, multiply and divide. These
operations require two operands. The Am9512 assumes that
these operands are located in the internal stack as Top of Stack
7-93
Am9512
operand located in TOS, exchanging single precision operands
located at TOS and NOS, as well as copying and popping single
or double precision operands. See also the sections on status
register and operand formats.
(TOS) and Next on Stack (NOS). The result will always be returned to the previous NOS which becomes the new TOS. Resuits from an operation are of the same precision and format as
the operands. The results will be rounded to preserve the accuracy. The actual data formats and rounding procedures are described in a later section. In addition to the arithmetic operations,
the Am9512 implements eight data manipulating operations.
These include changing the sign of a double or single precision
The Execution times of the Am9512 commands are all data
dependent. Table 2 shows one example of each command execution time:
Table 1. Command Decoding Table.
Command Bits
7
6
5
4
3
2
1
0
x
0
0
0
0
0
0
1
SADD
Add TOS to NOS Single Precision and result to NOS. Pop stack.
X 0
0
0
0
0
1
0
SSUB
Subtract TOS from NOS Single Precision and result to NOS. Pop stack.
X
0
0
0
0
0
1
1
SMUL
Multiply NOS by TOS Single Precision and result to NOS. Pop stack.
X
0
0
0
0
1
0
0
SDIV
Divide NOS by TOS Single Precision and result to NOS. Pop stack.
X
0
0
0
0
1
0
1
CHSS
Change sign of TOS Single Precision operand.
X
0
0
0
0
1
1
0
PTOS
Push Single Precision operand on TOS to NOS.
X
0
0
0
0
1
1
1
POPS
Pop Single Precision operand from TOS. NOS becomes TOS.
X
0
0
0
1
0
0
0
XCHS
Exchange TOS with NOS Single Precision.
X
0
1
0
1
1
0
1
CHSD
Change sign of TOS Double Precision operand.
X
0
1
0
1
1
1
0
PTOD
Push Double Precision operand on TOS to NOS.
X
0
1
0
1
1
1
1
POPD
Pop Double Precision operand from TOS. NOS becomes TOS.
X
0
0
0
0
0
0
0
CLR
CLR status.
X
0
1
0
1
0
0
1
DADD
Add TOS to NOS Double Precision and result to NOS. Pop stack.
X
0
1
0
1
0
1
0
DSUB
Subtract TOS from NOS Double Precision and result to NOS. Pop stack.
X
0
1
0
1
0
1
1
DMUL
Multiply NOS by TOS Double Precision and result to NOS. Pop stack.
X
0
1
0
1
1
0
0
DDIV
Divide NOS by TOS Double Precision and result to NOS. Pop Stack.
Notes: X = Don't Care
Mnemonic
Description
Operation for bit combinations not listed above is undefined.
Table 2. Am9S12 Execution Time in Cycles.
Single Precision
Double Precision
Min
Typ
Max
Min
Typ
Max
Add
58
220
512
Add
578
1200
3100
Subtract
56
220
512
Subtract
578
1200
3100
Multiply
192
220
254
Multiply
1720
1770
1860
Divide
228
240
264
Divide
4560
4920
5120
Note: Typical for add and subtract, assumes the operands are within six decimal orders of magnitude. Max is derived from the
maximum execution time of 1000 executions with random 32-bit or 64-bit patterns.
Table 3. Some Execution Examples.
Command
TOS
NOS
Result
Clock periods
SADD
3F800000
3F800000
40000000
SSUB
3F800000
3F800000
00000000
56
SMUL
40400000
3FCOOOOO
40900000
198
SDIV
40000000
3F800000
3FOOOOOO
228
CHSS
3F800000
BF800000
10
PTOS
3F800000
-
16
58
POPS
3F800000
-
-
14
XCHS
3F800000
4000000
-
26
CHSD
3FFOOOOOOOOOOOOO
24
3FFOOOOOOOOOOOOO
-
BFFOOOOOOOOOOOOO
PTOD
40
POPD
3FFOOOOOOOOOOOOO
-
CLR
3FFOOOOOOOOOOOOO
-
-
DADD
3FFOOOOOAOOOOOOO
8000000000000000
3FFOOOOOAOOOOOOO
DSUB
3FFOOOOOAOOOOOOO
8000000000000000
3FFOOOOOAOOOOOOO
578
DMUL
BFF8000000000000
3FF8000000000000
C002000000000000
1748
DDIV
BFF8000000000000
3FF8000000000000
BFFOOOOOOOOOOOOO
4560
Note: TOS, NOS and Result are in hexadecimal; Clock period is in decimal.
7-94
26
4
578
Am9512
COMMAND INITIATION
When the stack is popped for results, the most significant byte is
available first and the least significant byte last. A result is always
of the same preCision as the operands that produced it. Thus
when the result is taken from the stack, the total number of bytes
popped out should be appropriate with the precision - Single
precision results are 4 bytes and double precision results are 8
bytes. The following prodedure must be used for reading the
result from the stack:
After properly positioning the required operands in the stack, a
command may be issued. The procedure for initiating a command
execution is as follows:
1. Establish appropriate command on the DBO-DB7 lines.
2. Establish HIGH on the C/O input.
3. Establish LOW on the CS input. Whenever WR and RD inputs
are HIGH the PAUSE output follows the CS input. Hence
PAUSE will become LOW.
4. Establish LOW on the WR input after an appropriate set up
time (see timing diagrams).
5. Sometime after the HIGH to LOW level transition of WR input,
the PAUSE output will become HIGH to acknowledge the write
operation. The WR input can return to HIGH anytime after
PAUSE goes HIGH. The DBO-DB7, C/O and CS inputs are
allowed to change after the hold time requirements are satisfied (see timing diagram).
1. A LOW is established on the C/O input.
2. The CS input is made LOW. When WR and RD inputs are both
HIGH, the PAUSE output follows the CS input, thus PAUSE
will be LOW.
3. After appropriate set up time (see timing diagrams), the RD
input is made LOW.
4. Sometime after this, PAUSE will return HIGH indicating that
the data is available on the DBO-DB7 lines. This data will
remain on the DBO-DB7 lines as long as the RD input remains
LOW.
5. Anytime after PAUSE goes HIGH, the RD input can return
HIGH to complete transaction.
6. The CS and C/O inputs can change after appropriate hold time
requirements are satisfied (see timing diagram).
7. Repeat this procedure until all bytes appropriate for the precision of the result are popped out.
An attempt to issue a new command while the current command
execution is in progress is allowed. Under these circumstances,
the PAUSE output will not go HIGH until the current command
execution is completed.
OPERAND ENTRY
Reading of the stack does not alter its data; it only adjusts the byte
pointer. If more data is popped than the capacity of the stack, the
internal byte pointer will wrap around and older data will be read
again, consistent with the LIFO stack.
The Am9512 commands operate on the operands located at the
TOS and NOS and results are returned to the stack at NOS and
then popped to TOS. The operands required for the Am9512 are
one of two formats - single precision floating-point (4 bytes) or
double precision floating-point (8 bytes). The result of an operation has the same format as the operands. In other words, operations using single precision quantities always result in a
Single precision result while operations involving double precision quantities will result in double precision result.
READING STATUS REGISTER
The Am9512 status register can be read without any regard to
whether a command is in progress or not. The only implication
that has to be considered is the effect this might have on the END
and ERR outputs discussed in the signal descriptions.
Operands are always entered into the stack least significant byte
first and most significant byte last. The following procedure must
be followed to enter operands into the stack:
The following procedure must be followed to accomplish status
register reading.
1. Establish HIGH on the C/O input.
2. Establish LOW on the CS input. Whenever WR and RD inputs are HIGH, PAUSE will follow the CS input. Thus,
PAUSE will go LOW.
3. After appropriate set up time (see timing diagram) RD ~s
made LOW.
4. Sometime after the HIGH to LOW transition of RD, PAUSE
will become HIGH indicating that status register contents are
available on the DBO-DB7 lines. These lines will contain this
information as long as RD is LOW.
5. The RD input can be returned HIGH anytime after PAUSE
goes HIGH.
6. The C/O input and CS input can change after satisfying appropriate hold time requirements (see timing diagram).
1. The lower significant operand byte is established on the
DBO-DB7 lines.
2. A LOW is established on the cio input to specify that data is to
be entered into the stack.
3. The CS input is made LOW. Whenever the WR and RD inputs
are HIGH, the PAUSE output will follow the CS input. Thus
PAUSE output will become LOW.
4. After appropriate set up time (see timing diagrams), the WR
input is made LOW.
5. Sometime after this event, PAUSE will return HIGH to indicate that the write operation has been acknow~ed.
6. Anytime after the PAUSE output goes HIGH the WR input can
be made HIGH. The DBO-DB7, C/O and CS inputs can change
after appropriate hold time requirements are satisfied (see
timing diagrams).
DATA FORMATS
The above procedure must be repeated until all bytes of the
operand are pushed into the stack. It should be noted that for
single precision operands 4 bytes should be pushed and 8 bytes
must be pushed for double precision. Not pushing all the bytes of
a quantity will result in byte pointer misalignment.
The Am9512 handles floating-point quantities in two different
formats - single precision and double preCision. The single precision quantities are 32-bits long as shown below.
F'·""D'"
The Am9512 stack can accommodate 4 single precision quantities or 2 double precision quantities. Pushing more quantities
than the capacity of the stack will result in loss of data which is
usual with any LIFO stack.
I
31
REMOVING THE RESULTS
30
23
M
22
Bit 31:
S = Sign of the mantissa. 1 represents negative and 0 represents positive.
Result from an operation will be available at the TOS. Results can
be transferred from the stack to the data bus by reading the stack.
7-95
Am9512
STATUS REGISTER
Bits 23-30
E = These a-bits represent a biased exponent. The bias is
27 -1 = 127
The Am9512 contains an a-bit status register with the following
format.
Bits 0-22
M = 23-bit mantissa. Together with the sign bit, the mantissa
represents a signed fraction in sign-magitude notation.
There is an implied 1 beyond the most significant bit (bit 22)
of the mantissa. In other words, the mantissa is assumed to
be a 24-bit normalized quantity and the most significant bit
which will always be 1 due to normalization is implied. The
Am9512 restores this implied bit internally before performing
arithmetic; normalizes the result and strips the implied bit
before returning the results to the external data bus. The
binary pOint is between the implied bit and bit 22 of the
mantissa.
Bit 0 and bit 4 are reserved. Occurrence of exponent oerflow (V),
exponent underflow (U) and divide exception (D) are indicated
by bits 1,2 and 3 respectively. An attempt to divide by zero is the
only divide exception. Bits 5 and 6 represent a zero result and
the sign of a result respectively. Bit 7 (Busy) of the status register indicates if the Am9512 is currently busy executing a command. AI! the bits are initialized to zero upon reset. Also,
executing a CLR (Clear Status) command will result in all zero
status register bits. A zero in Bit 7 indicates that the Am9512 is
not busy and a new command may be initiated. As soon as a
new command is issued, Bit 7 becomes 1 to indicate the device
is busy and remains 1 until the command execution is complete,
at which time it will become O. As soon as a new command is
issued, status register bits 0, 1, 2, 3, 4, 5 and 6 are cleared to
zero. The status bits will be set as required during the command
execution. Hence, as long as bit 7 is 1, the remainder of the
status register bit indications should not be relied upon unless the ERR occurs. The following is a detailed status bit
description.
The quantity N represented by the above notation is
r-----Bias
J-.
N = (-1)s
Provided E
-j;
2 E-(2
L
1)
r-Binary Point
(1!M)
0 or all 1'so
A double precision quantity consists of the mantissa sign bit(s),
an 11 bit biased exponent (E), and a 52-bit mantissa (M). The bias
for double precision quantities is 2 10 - 1. The double preCision
format is illustrated below.
Bit 0
Bit 1
F;MPUED'"
Bit 2
M
63
52
62
51
Bit 3
Bit 63:
S = Sign of the mantissa. 1 represents negative and 0 represents positive.
Bits 52-62
E = These 11 bits represent a biased exponent. The bias is
2 10 - 1 = 1023.
Bit 6
Bit 0-51
M = 52-bit mantissa. Together with the sign bit, the mantissa
represents a signed fraction in sign-magnitude notation.
There is an implied 1 beyond the most Significant bit (bit 51)
of the mantissa. In other words, the mantissa is assumed to
a 53-bit normalized quantity and the most significant bit,
which will always be a 1 due to normalization, is implied. The
Am9512 restores this implied bit internally before performing arithmetic; normalizes the result and strips the implied bit
before returning the result to the external data bus. The
binary pOint is between the implied bit and bit 51 of the
mantissa.
Bit 7
All other status register bits are valid when the Busy bit is zero.
ALGORITHMS OF FLOATING-POINT ARITHMETIC
1. Floating Point to Decimal Conversion
As an introduction to floating-point arithmetic, a brief description of the Decimal equivalent of the Am9512 floating-point
format should help the reader to understand and verify the
validity of the arithmetic operations. The Am9512 single precision format is used for the following discussions. With a minor
modification of the field lengths, the discussion would also
apply to the double precision format.
The quantity N represented by the above notation is
,
...---Bias
1L
N = (-1)5 2 E-(2
Provided E
1=
1)
Bit 4
Bit 5
Reserved
Exponent overflow (V): When 1, this bit indicates that
exponent overflow has occurred. Cleared to zero
otherwise.
Exponent Underflow (U): When 1, this bit indicates that
exponent underflow has occurred. Cleared to zero
otherwise.
Divide Exception (D): When 1, this bit indicates that an
attempt to divide by zero is made. Cleared to zero
otherwise.
Reserved
Zero (Z): When 1, this bit indicates that the result returned
to TOS after a command is all zeros. Cleared to zero
otherwise.
Sign (S): When 1, this bit indicates that the result returned
to TOS is negative. Cleared to zero otherwise.
Busy: When 1, this bit indicates the Am9512 is in the
process of executing a command. It will become zero after
the command execution is complete.
r-- Binary point
There are three parts in a floating point number:
a. The sign - the sign applies to the sign of the number. Zero
means the number is positive or zero. One means the
number is negative.
(1!M)
0 or all 1'so
7-96
Am9S12
a. Unpack TOS and NOS.
b. The exponent of TOS is compared to the exponent of
NOS.
c. If the exponents are equal, go to step f.
d. Right shift the mantissa of the number with t; ,~ smaller
exponent.
e. Increment the smaller exponent and go to step b.
f. Set sign of result to sign of larger number.
g. Set exponent of result to exponent of larger number.
h. If sign of the two numbers are not equal, go to m.
Add Mantissas.
j. Right shift resultant mantissa by 1 and increment exponent of result by 1.
k. If MSB of exponent changes from 1 to 0 as a result of the
increment. set overflow status.
Round if necessary and exit.
m. Subtract smaller mantissa from larger mantissa.
n. Left shift mantissa and decrement exponent of result.
o. If MSB of exponent changes from 0 to 1 as a result of the
decrement, set underflow status and exit.
p. If the MSB of the resultant mantissa = 0, go to n.
q. Round if necessary and exit.
b. The exponent - the exponent represents the magnitude of
the number. The Am9512 single precision format has an
excess 12710 notation which means the code representation is 12710 higher than the actual value. The following are
a few examples of actual versus coded exponent.
Actual
Coded
+127 10
+25410
12710
+110
o
-126 10
c. The mantissa - the mantissa is a 23-bit value with the
binary point to the left of the most significant bit. There is a
hidden 1 to the left of the binary point so the mantissa is
always less than 2 and greater than or equal to 1.
To find the Decimal equivalent of the floating point number,
the mantissa is multiplied by 2 to the power of the actual
exponent. The number is negated if the sign bit = 1. The
following are two examples of conversion:
Example 1
Floating Point No.
Sign
=0
~
100000 111 1000 00000000 0000000000 B
Exponent
Mantissa
4. Floating-Point Multiply
Floating-point multiply basically involves the addition of the
exponents and multiplication of the mantissas. The following
is a step by step description of a floating multiplication algorithm (Figure 2):
Coded Exponent = 1 0 0 0 0 0 1 1 B
Actual Exponent = 1 0 0 0 0 0 1 1 B - 0 1 1 1 1 1 1 1 B = 0 0 0 0 0 1 0 0 B = 4'0
Mantissa = 1.1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B
=1+
1/2 + 1/4
=
1.75 10
Decimal No. = 24 x 1.75 = 16 x 1.75 = 2BlO
Check if TOS or NOS = O.
If either TOS or NOS = 0, Set result to 0 and exit.
Unpack TOS and NOS.
Convert EXP (TOS) and EXP (NOS) to unbiased form.
EXP (TOS) = EXP (TOS) -127 10
EXP (NOS) = EXP (NOS) -127 10
e. Add exponents.
EXP = EXP (TOS) + EXP (NOS)
f. If MSB of EXP (TOS) = MSB of EXP (NOS) = 0 and MSB
of EXP = 1, then set overflow status and exit.
g. If MSB of EXP (TOS) = MSB of EXP (NOS) = 1 and MSB
of EXP = 0, then set underflow status and exit.
h. Convert Exponent back to biased form.
EXP = EXP + 12710
If sign of TOS = sign of NOS, set sign of result to 0, else set
sign of result to 1.
j. Multiply mantissa.
k. If MSB of resultant = 1, right shift mantissa by 1 and
increment exponent of resultant.
If MSB of exponent changes from 1 to 0 as a result of the
increment, set overflow status.
m. Round if necessary and exit.
a.
b.
c.
d.
Example 2
Floating Point No.
Sign
=10
~
11110 100 11000000000000000000 00 B
Exponent
Mantissa
Code Exponent = 0 1 1 1 1 0 1 0 B
Actual Exponent = 0 1 1 1 1 0 1 0 B - 0 1 1 1 1 1 1 1 B = 1 1 1 1 1 0 1 1 B = - 510
Mantissa = 1.0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B
=
Decimal No.
1 + 1/4 + 1/B = 1.375,0
= _2- 5 x 1.375 = - .04296B75,0
2. Unpacking of the Floating-Point Numbers
The Am9512 unpacks the floating point number into three
parts before any of the arithmetic operation. The number is
divided into three parts as described in Section 1. The sign and
exponent are copied from the original number as 1 and 8-bit
numbers respectively. The mantissa is stored as a 24-bit
number. The least significant 23 bits are copied from the
original number and the MSB is set to 1. The binary point is
assumed to the right of the MSB.
The abbreviations listed below are used in the following sections of algorithm description:
SIGN - Sign of Result
EXP - Exponent of Result
MAN - Mantissa of Result
SIGN (TOS) - Sign of Top of Stack
EXP (TOS) - Exponent of Top of Stack
MAN (TOS) - Mantissa of Top of Stack
SIGN (NOS) - Sign of Next on Stack
EXP (NOS) - Exponent of Next on Stack
MAN (NOS) - Mantissa of Next on Stack
5. Floating-Point Divide
The floating-point divide basically involves the subtraction of
exponents and the division of mantissas. The following is a
step by step description of a division algorithm (Figure 3).
a.
b.
c.
d.
3. Floating-Paint Add/Subtract
The floating-point add and subtract essentially use the same
algorithm. The only difference is that floating-point subtract
changes the sign of the floating-point number at top of stack
and then performs the floating-point add.
e.
f.
The following is a step by step description of a floating-point
add algorithm (Figure 1):
g.
7-97
If TOS = 0, set divide exception error and exit.
If NOS = 0, set result to 0 and exit.
Unpack TOS and NOS.
Convert EXP (TOS) and EXP (NOS) to unbiased form.
EXP (TOS) = EXP (TOS) - 12710
EXP (NOS) = EXP (NOS) - 12710
Subtract exponent of TOS from exponent of NOS.
EXP = EXP (NOS) - EXP (TOS)
If MSB of EXP (NOS) = 0, MSB of EXP (TOS) = 1 and
MSB of EXP = 1, then set overflow status and exit.
If MSB of EXP (NOS) = 1, MSB of EXP (TOS) = 0, and
MSB of EXP = 0, then set underflow status and exit.
6
Am9512
y
N
y
y
y
SET
OVERFLOW
STATUS
SET
UNDERFLOW
STATUS
SUBTRACTION
ROUNDING
Figure 1. Conceptual Floating-Point Addition/Subtraction.
h. Add bias to exponent of result.
EXP = EXP + 12710
If sign of TOS = sign of NOS, set sign of result to 0, else set
sign of result to 1.
j. Divide mantissa of NOS by mantissa of TOS.
k. If MSB = 0, left shift mantissa and decrement exponent of
resultant, else go to n.
If MSB of exponent changes from to 1 as a result of the
decrement, set underflow status.
m. Go to k.
n. Round if necessary and exit.
MOS·205
The method used for doing the rounding during floating-point
arithmetic is known as "Round to Even", i.e., if the resultant
number is exactly halfway between two floating point numbers, the number is rounded to the nearest floating-point
number whose LSB of the mantissa is 0. In order to simplify the
explanation, the algorithms will be illustrated with 4-bit arithmetic. The existence of an accumulator will be assumed as
shown:
°
OF
B1
B2
B3
B4
The algorithms described above provide the user a means of
verifying the validity of the result. They do not necessarily
reflect the exact internal sequence of the Am9512.
The bit labels denote:
6. Rounding
The Am9512 adopts a rounding algorithm that is consistent
with the Intel® standard for floating-point arithmetic. The following description is an excerpt from the paper published in
proceedings of Compsac 77, November 1977, pp. 107-112 by
Dr. John F. Palmer of Intel Corporation.
OF - The overflow bit
B1-B4 - The 4 mantissa bits
G - The Guard bit
R - The Rounding bit
ST - The "Sticky" bit
7-98
G
R
ST
Am9S12
N
RESULT = 0
y
SET
OVERFLOW
STATUS
SET
UNDERFLOW
STATUS
Figure 2. Conceptual Floating-Point Multiplication.
MOS-206
The Sticky bit is set to one if any ones are shifted right of the
rounding bit in the process of denormalization_ If the Sticky bit
becomes set, it remains set throughout th~ operation. All
shifting in the Accumulator involves the OF, G, Rand ST bits.
The ST bit is not affected by left shifts but, zeros are introduced
into OF by right shifts.
B1
B2
B3
B4
B5
B6
B7
B8
Then G=B5, R=B6, ST=B7 V B8. The rounding is then performed as in addition of magnitudes.
Rounding during division - let the first six bits of the normalized quotient be
Rounding during addition of magnitudes - add 1 to the G
position, then if G=R=ST=O, set B4 to a ("Rounding to
Even").
Rounding during subtraction of magnitudes - if more than one
left shift was performed, no rounding is needed, otherwise
round the same way as addition of magnitudes.
B1
B2
B3
B4
B5
B6
Then G=B5, R=B6, ST=O if and only if remainder = O. The
rounding is then performed as in addition of magnitudes.
Rounding during multiplication - let the normalized double
length product be:
7-99
Am9512
Figure 3. Conceptual Floating-Point Division.
MOS-207
CHSD
CHSS
CHANGE SIGN DOUBLE PRECISION
CHANGE SIGN SINGLE PRECISION
7
6
5
Binary Coding: \SRE \ 0
4
3
o
2
o
0
Hex Coding:
AD IF SRE = 1
2D IF SRE = 0
Execution Time: See Table 2
Description:
The sign of the double precision TOS operand A is complemented. The double precision result R is returned to TOS. If
the double precision operand A is zero, then the sign is not
affected. The status bit Sand Z indicate the sign of the result and if
the result is zero. The status bits U, V and D are always cleared to
zero.
Status Affected: S, Z. (U, V, D always zero.)
7
6
5
4
3
Binary Coding: ISRE I 0
0
0
0
A
B
TOS
NOS
0
0
Hex Coding:
85 IF SRE = 1
05 IF SRE = 0
Execution Time: See Table 2
Description:
The sign of the single precision operand A at TOS is complemented. The single precision result R is returned to TOS. If the
exponent field of A is zero, all bits of R will be zeros. The status
bits Sand Z indicate the sign of the result and if the result is zero.
The status bits U, V and D are cleared to zero.
Status Affected: S, Z. (U, V, D always zero.)
STACK CONTENTS
STACK CONTENTS
BEFORE
2
AFTER
BEFORE
R
A
I--- TOS
B
B
I--- NOS
C
D
7-100
--
AFTER
i
R
B
C
D
Am9S12
DSUB
CLR
CLEAR STATUS
6
5
4
3
2
Binary Coding: ISREI 0
7
0
0
0
0
DOUBLE PRECISION
FLOATING-POINT SUBTRACT
0
0
7
6
5
4
Binary Coding: ISRE I 0
1
0
0
Hex Coding:
80 IF SRE = 1
00 IF SRE = 0
Execution Time: 4 clock cycles
Description:
The status bits S, Z, D, U, V are cleared to zero. The stack is not
affected. This essentially is a no operation command as far as
operands are concerned.
Status Affected: S, Z, D, U, V always zero.
3
o
o
2
o
Hex Coding:
AA IF SRE = 1
2A IF SRE = 0
Execution Time: See Table 2
Description:
The double precision operand A at TOS is subtracted from the
double precision operand B at NOS. The result is rounded to
obtain the final double precision result R which is returned to
TOS. The status bits S, Z, U and V are affected to report sign of
the result, if the result is zero, exponent underflow and exponent
overflow respectively. The status bit D will be cleared to zero.
Status Affected: S, Z, U, V. (D always zero.)
STACK CONTENTS
BEFORE
AFTER
~-----A------~~NTOOSS~~------R------~
~
B
DADD
7
6
0
5
4
3
0
2
0
DOUBLE PRECISION
FLOATING-POINT MULTIPLY
0
7
0
Status Affected: S, Z, U, V. (D always zero.)
' - - -_ _ _ _ _:_ _ _ _ _ _
4
3
o
2
o
0
Hex Coding:
AB IF SRE = 1
2B IF SRE = 0
Execution Time: See Table 2
Description:
The double precision operand A from TOS is multiplied by the
double precision operand B from NOS. The result is rounded to
obtain the final double precision result R which is returned to
TOS. The status bits S, Z, U and V are affected to report sign of
the result, if the result is zero, exponent underflow and exponent
overflow respectively. The status bit D will be cleared to zero.
STACK CONTENTS
AFTER
---'~ ~~: ~L_
5
0
Status Affected: S, Z, U, V. (D always zero.)
STACK CONTENTS
BEFORE
6
Binary Coding: ISREI
Hex Coding:
A9 IF SRE = 1
29 IF SRE = 0
Execution Time: See Table 2
Description:
The double precision operand A from TOS is added to the double
precision operand B from NOS. The result is rounded to obtain
the final double precision result R which is returned to TOS. The
status bits S, Z, U and V are affected to report sign of the result, if
the result is zero, exponent underflow and exponent overflow
respectively. The status bit D will be cleared to zero.
Undefined
DMUL
DOUBLE PRECISION FLOATING-POINT ADD
Binary Coding: ISREI
~
U_nd_:_fi_ne_d__
____
__'I
~----B-E-FA-O-R-E------t~ ~1TNOOSS
.
7-101
B
~
~
~_E_R
____A
__
_____1
Undefined
Am9512
SSUB
DDIV
SINGLE PRECISION
FLOATING-POINT SUBTRACT
DOUBLE PRECISION
FLOATING-POINT DIVIDE
Binary Code:
7
6
ISREI
°
Hex Coding:
5
4
3
2
°
·0
7
°
°
6
Binary Coding: ISREI
4
2
3
°
°
° =° ° ° °
=°
AC IF SRE = 1
2C IF SRE =
Execution Time: See Table 2
Description:
The double precision operand B from NOS is divided by the
double precision operand A from TOS. The result (quotient) is
rounded to obtain the final double precision result R which is
returned to TOS. The status bits, S, Z, 0, U and V are affected to
report sign of the result, if the result is zero, attempt to divide by
zero, exponent underflow and exponent overflow respectively.
82 IF SRE
1
02 IF SRE
Execution Time: See Table 2
Description:
The single precision operand A at TOS is subtracted from the.
single precision operand B at NOS. The result is rounded to
obtain the final single precision result R 'vvhich is returned to TOS.
The status bits S, Z, U and V are affected to report the sign of the
result, if the result is zero, e~ponent underflow and exponent
overflow respectively. The status bit 0 will be cleared to zero.
Status Affected: S, Z, 0, U, V
Status Affected: S, Z, U, V. (0 always zero.)
°
Hex Coding:
5
STACK CONTENTS
STACK CONTENT
BEFORE
BEFORE
AFTER
-11-I--
t--_ _ _A
___
B
----- --
A
TOS
R (see note)
B
NOS
Undefined
C
5
4
3
2
SINGLE PRECISION
FLOATING-POINT MULTIPLY
°
7
Binary Coding: IL.S_R_E...JI_o---'-_o--'-_O_.l..-0_L--0__'-O__'----l
Hex Coding:
81 IF SRE = 1
01 IF SRE =
Execution Time: See Table 2
Description:
The single precision operand A from TOS is added to the single
precision operand B from NOS. The result is rounded to obtain
the final single precision result R which is returned to TOS. The
status bits S, Z, U and V are affected to report the sign of the
result, if the result is zero, exponent underflow and exponent
overflow respectively. The status bit 0 will be cleared to zero.
°
Status Affected: S, Z, U, V. (0 always zero.)
A
B
C
I
0
-- --
5
432
°
Binary Coding: I'--S_R_E->..I_O---'-_O--'-_O_.l...-0---''--O_'-----''-----'
Hex Coding:
83 IF SRE = 1
03 IF SRE =
Execution Time: See Table 2
Description:
The single precision operand A from TOS is multiplied by the
single precision operand B from NOS. The result is rounded to
obtain the final single precision result R which is returned to TOS.
The status bits S, Z, U and V are affected to report the sign of the
result, if the result is zero, exponent underflow and exponent
overflow respectively. The status bit 0 will be cleared to zero.
°
STACK CONTENTS
AFTER
TOS
R
NOS
C
0
-.
6
Status Affected: S, Z, U, V. (0 always zero.)
STACK CONTENT
BEFORE
0
SMUL
SINGLE PRECISION FLOATING-POINT ADD
6
R
C
Undefined
SADD
7
TOS
NOS
0
Note: If A is zero, then R = B (Divide exception).
AFTER
Undefined
BEFORE
E~
II
7-102
.
D
AFTER
~:~: =1f-------l~
I
I
Undefined
Am9S12
SDIV
PTOD
SINGLE PRECISION
FLOATING-POINT DIVIDE
PUSH STACK DOUBLE PRECISION
7
6
5
7
°
432
0- L _
o---L_---L_O_L-0_
.Binary Coding: L-IS_R_E-1I_0----1_0- - - L _
Hex Coding:
6
5
Binary Coding: iSREI 0
4
2
3
°
°
°
Hex Coding: AE IF SRE = 1
2E IF SRE =
Execution Time: See Table 2
Description:
The double precision operand A from the TOS is pushed back on
to the stack. This is effectively a duplication of A into two consecutive stack locations. The status Sand Z are affected to report
sign of the new TOS and if the new TOS is zero respectively. The
status bits U, V and D will be cleared to zero.
°
84 IF SRE = 1
04 IF SRE =
Execution Time: See Table 2
Description:
The single precision operand B from NOS is divided by the
single precision operand A from TOS. The result (quotient) is
rounded to obtain the final result R which is returned to TOS.
The status bits S, Z, D, U and V are affected to report the sign of
the result, if the result is zero, attempt to divide by zero, exponent underflow and exponent overflow respectively.
°
Status Affected: S, Z. (U, V, D always zero.)
STACK CONTENTS
Status Affected: S, Z, D, U, V
BEFORE
STACK CONTENTS
BEFORE
~-----~----~~~~:~~------:----~
AFTER
A
I---TOS-
R (see note)
B
--NOS---
C
C
D
D
Undefined
AFTER
Note: If exponent field of A is zero then R = B (Divide exception).
PTOS
POPS
PUSH STACK SINGLE PRECISION
POP STACK SINGLE PRECISION
7
6
5
4
3
2
6
7
Binary Coding: ISREI 0
°
4
3
0
o
2
°
°
87 IF SRE = 1
07 IF SRE = 0
Execution Time: See Table 2
Description:
The single precision operand A is popped from the. stack. The
internal stack control mechanism is such that A will be written at
the bottom of the stack. The status bits Sand Z are affected to
report the sign of the new operand at TOS and if it is zero,
respectively. The status bits U, V and D will be cleared to zero.
Note that only the exponent field of the new TOS is checked for
zero, if it is zero status bit Z will set to 1.
·86 IF SRE = 1
06 IF SRE =
Execution Time: See Table 2
Description:
This instruction effectively pushes the single precision operand
from TOS on to the stack. This amounts to duplicating the
operand at two locations in the stack. However, if the operand at
TOS prior to the PTOS command has only its exponent field as
zero, the new content of the TOS will all be zeroes. The contents
of NOS will be an exact copy of the old TOS. The status bits S
and Z are affected to report the sign of the new TOS and if the
content of TOS is zero, respectively. The status bits U, Vand D
will be cleared to zero.
Status Affected: S, Z. (U, V, D always zero.)
Status Affected: S, Z. (U, V, D always zero.)
Binary Coding: ISRE I
Hex Coding:
° ° ° °
Hex Coding:
5
°
°
STACK CONTENTS
STACK CONTENTS
AFTER
BEFORE
A
~TOS-
B
A
I----TOS-
B
I---NOS-
C
B
I--NOS-
BEFORE
C
D
D
A
AFTER
~------~
~------~
C
A* See note
~------~
D
Note: A" = A if Exponent field of A is not zero.
A* = 0 if Exponent field of A is zero.
7-103
A
~------~
B
C
Am9S12
POPD
XCHS
POP STACK DOUBLE PRECISION
EXCHANGE TOS AND NOS
SINGLE-PRECISION
6
5
4
Binary Coding: ISRE I 0
7
1
0
3
2
o
6
5
4
Binary Coding: ISRE I 0
0
0
7
Hex Coding:
AF IF SRE = 1
2F IF SRE = 0
Execution Time: See Table 2
Description:
The double precision operand A is popped from the stack. The
internal stack control mechanism is such that A will be written at
the bottom of the stack. This operation has the same effect as
exchanging TOS and NOS. The status bits Sand Z are affected to
report the sign of the new operand at TOS and if it is zero,
respectively. The status bits U, V and D will be cleared to zero.
3
0
0
0
Hex Coding:
88 IF SRE = 1
08 IF SRE = 0
Execution Time: See Table 2
Description:
The single precision operand A at the TOS and the single precision operand B at the NOS are exchanged. After execution, B is at
the TOS and A is at the NOS. All other operands are unchanged.
Status Affected: S, Z (U, V and D always zero.)
Status Affected: S, Z (U, V and D always zero.)
STACK CONTENTS
BEFORE
STACK CONTENTS
BEFORE
2
0
AFTER
AFTER
A
I--TOS-
B
B
r---NOS-
A
~------------~
r------:----~~:~:~~------:----~
r------------~
~------------~
C
D
~------------~
C
D
Am25lS138
loiM
t - - - - - - - - I Gl
A15 t - - - - - O I G2A
+12V
A13
t-----~
C
A12
t-----~
B
All
t------\ A
cs
Y I""
ABr---------------------;
Voo
ADO-AD7
-;"
~.------.:...8--BI-T_DA_T_A_BU_S_ _ _ _---,
ADr---------------~
RST6.5
Vss
Am9512
.A
-
Vee
c/o
Am8085
.------1
+5V
11 0
l'
A14 t - - - - - O
I G2B
DBO·DB7
AD
WR r - - - - - - - - - - - - - - - - - - - < > I WR
ERR
1----------------------1 elK
END I - - READY RESET OUT 1--------------------1 RESET
EACK ___...J
L -_ _ _ _----I
+5V ,..O---:.'!::"--~l.:!~
'"""~
r
RST5.5
ClK OUT
1-
10K
Figure 1. Am9512 to Am8085 Interface.
7-104
MOS-213
Am9512
MAXIMUM RATINGS beyond which useful life may be impaired
Storage Temperature
Ambient Temperature Under Bias
VDD with Respect to VSS
vee with
-O.5V to +15.0V
Respect to VSS
-O.5V to + 7.0V
-O.5V to + 7.0V
All Signal Voltages with Respect to VSS
Power Dissipation (Package Limitation)
2.0W
The products described by this specification include internal circuitry designed to protect input devices from damaging accumulations of
static charge. It is suggested, nevertheless, that conventional precautions be observed during storage, handling and use in order to avoid
.
exposure to excessive voltages.
OPERATING RANGE
Part Number
Ambient Temperature
VSS
VCC
VDD
Arn9512DC
+5.0V ±5%
+12V ±5%
Arn9512DM
+5.0V ±10%
+12V ±10%
ELECTRICAL CHARACTERISTICS Over Operating Range (Note 1)
Parameters
Description
Test Conditions
Min.
Typ.
Max.
Units
0.4
Volts
Volts
3.7
VOH
Output HIGH Voltage
10H = -2001LA
VOL
Output LOW Voltage
10L = 3.2rnA
VIH
Input HIGH Voltage
2.0
vee
Volts
VIL
Input LOW Voltage
-0.5
0.8
Volts
IIX
Input Load Current
±10
/LA
10Z
Data Bus Leakage
VSS';; VI.;;
vce
VO = O.4V
10
vce
10
VO =
50
TA = +25°C
ICC
VCC Supply Current
50
TA = +25°C
VDO Supply Current
TA =
ooe
CO
Output Capacitance
Input Capacitance
CIO
I/O Capacitance
90
95
mA
100
TA = -55°C
CI
rnA
100
TA = -55°C
100
90
95
TA = O°C
ILA
fc = 1.0MHz, Inputs = OV
7-105
pF
8
10
5
8
pF
10
12
pF
Am9512
SWITCHING CHARACTERISTICS
Parameters
Am9512DC
Max
Description
Am9512-1DC
Max
Min
Min
Units
100
75
ns
ns
TAPW
EACK LOW Pulse Width
TCDR
C/D to RD LOW Set-up Time
0
0
TCDW
C/D to WR LOW Set-up Time
0
0
TCPH
Clock Pulse HIGH Width
200
TCPL
Clock Pulse LOW Width
240
160
ns
TCSP
CS LOW to PAUSE LOW Delay (Note 5)
150
100
ns
TCSR
CS to RD LOW Set-up Time
0
0
ns
TCSW
CS LOW to WR LOW S~t-up Time
0
0
TCY
Clock Period
480
150
TOW
Data Valid to WR HIGH De!ay
TEAE
EACK LOW to END LOW Delay
TEHPHR
END HIGH to PAUSE HIGH Data Read when Busy
TEHPHW
END HIGH to PAUSE HIGH Write when Busy
500
140
ns
500
ns
ns
2000
ns
200
175
ns
5.5TCY+300
5.5TCY+200
ns
200
175
ns
5000
320
nl>
100
ns
TEPW
END HIGH Pulse Width
TEX
Execution Time
TOP
Data Bus Output Valid to PAUSE HIGH Delay
TPPWR
PAUSE LOW Pulse Width Read
TPPWRB
END HIGH to PAUSE HIGH Read when Busy
TPPWW
PAUSE LOW Pulse Width Write when Not Busy
TPPWWB
PAUSE LOW Pulse Width Write when Busy
TPR
PAUSE HIGH to Read HIGH Hold Time
0
0
ns
TPW
PAUSE HIGH to Write HIGH Hold Time
0
0
ns
TRCD
RD HIGH to C/D Hold Time
0
0
ns
TRCS
RD HIGH to CS HIGH Hold Time
0
0
ns
TRO
RD LOW to Data Bus On Delay
50
50
TRZ
400
300
ns
See Table 2
ns
0
0
Data
3.5TCY+50
5.5TCY+300
3.5TCY+50
5.5TCY+200
Status
1.5TCY+50
3.5TCY+300
1.5TCY+50
3.5TCY+200
1.5TCY+50
3.5TCY+300
Data
See Table 2
Status
1.5TCY+50
TCSW+50
3.5TCY+200
TCSW+50
50
200
ns
ns
ns
See Table 2
RD HIGH to Data Bus Off Delay
ns
50
ns
150
ns
ns
TSAPW
SVACK LOW Pulse Width
TSAR
SVACK LOW to SVREQ LOW Delay
TWCD
WR HIGH to C/D Hold Time
60
30
ns
TWCS
WR HIGH to CS HIGH Hold Time
60
30
ns
TWD
WR HIGH to Data Bus Hold Time
20
20
ns
75
100
200
300
NOTES:
1. Typical values are for T A = 25°C, nominal supply voltages
and nominal processing parameters.
2. Switching parameters are listed in alphabetical order.
3. Test conditions assume transition times of 20ns or less, output loading of one TIL gate plus 100pF and timing reference
levels of 0.8V and 2.0V.
ns
4. END HIGH pulse width is specified for EACK tied to VSS.
Otherwise TEAE applies.
5. PAUSE is pulled low for both command and data operations.
6. TEX is the execution time of the current command (see the
Command Execution Times table).
7. PAUSE will go low at this paint if CS is low and RD and WR are
high.
7-106
Am9512
TIMING DIAGRAMS
READ OPERATION
~
ClK
~
AD
TCOR
TCSR
\
cs
TCSP
~
PAUSE
00-01
c/o
MOS-208
OPERAND READ WHEN Am9S12 IS BUSY
ClK
-
I-TCOR
'(~
\
i{
.' J
--TRCS-
TPR
I-TCSR
--<
~V-
t---t--TRO
~
Ii
TRCO
TPPWRB
[\
{{
).1
-
.(
\I
/
00-07
nl'1l'lI.IIIlI.lI.II
:II
~IYIIIIIlI.II
~~
IIIIIYXXXXXI
IIIYYIIIII
YYII
~
NOtE 7
TRZ-
I-TOP
IlI.IXX
IIIIlI.AX
lI.IIIIII
DATA
VA.LlO
l-
~K
))
c/o
\~
~r
(L
))
TEHPHR_
END
7
\'--------
---------;ff.....----J
M05-209
7-107
Am9S12
TIMING DIAGRAMS (Cont.)
OPERAND ENTRY
~
CLK~.
:~:~::-\'-----TCSP
~
~x=
DATA
VALID
00-07
~'----
CiD
MOS-210
COMMAND OR DATA WRITE WHEN Am9512 IS BUSY
ClK
I
~-------------------TPPWWB---------------------1
t--+-- TWO
00-07
CID
END
~t ~
)
TEHPHW
\
MOS-211
7-108
Am9S12
TIMING DIAGRAMS (Cont.)
COMMAND INITIATION
ClK
\'----
,
),
\
f,
f--
f-- f--TCSW
\
fl,
\
II
H
i
TPW
))
\
~
reDW)
DATA VALID
I,
l-
I'',I
--
TOW-
-~
00-07
TWCS
I
.--
TCSP_
I
/
II
"j
i
I-TWD
NOtE 7
J?
K
'i
I
I- TWC0"1
Clli
I
I
TEX
END
p
~
)
I'
i,
I
TEX
SVREQ
Ii
(I
I,
f',
/)
}
~~]
{'"
"~y
! \~TSAR}
TSAPW-Y-
-----------Ir-------------(~------~
SVACK
"
MOS-212
7-109
Am9513
System Timing Controller
DISTINCTIVE CHARACTERISTICS
GENERAL DESCRIPTION
• Five independent 16-bit counters
The Am9513 System Timing Controller is an LSI circuit designed
to service many types of courting, sequencing and timing applications. It provides the capability for programmable frequency
synthesis, high resolution programmable duty cycle waveforms,
retriggerable digital timing functions, time-of-day clocking, coincidence alarms, complex pulse generation, high resolution baud
rate generation, frequency shift keying, stop-watching timing,
event count accumulation, waveform analysis and many more. A
variety of programmable operating modes and control features
allow the Am9513 to be personalized for particular applications as
well as dynamically reconfigured under program control.
•
•
•
•
•
High speed counting rates
Up/down and binary/BCD counting
Internal oscillator frequency source
Tapped frequency scaler
Programmable frequency output
• 8-bit or 16-bit bus interface
• Time-of-day option
• Alarm comparators on counters 1 and 2
• Complex duty cycle outputs
• One-shot or continuous outputs
The STC includes five general-purpose 16-bit counters. A variety
of internal frequency sources and external pins may be selected
as inputs for individual counters with software selectable activehigh or active-low input polarity. Both hardware and software
gating of each counter is available. three-state outputs for each
counter provide either pulses or levels. The counters can be
programmed to count up or down in either binary or BCD. The
accumulated count may be read without disturbing the counting
process. Any of the counters may be internally concatenated to
form an effective counter length of up to 80 bits.
• Programmable count/gate source selection
• Programmable input and output polarities
• Programmable gating functions
• Retriggering capability
• +5 volt power supply
• Standard 40-pin package
• 100% MIL-STD-883 reliability assurance testing
TABLE OF CONTENTS
CONNECTION DIAGRAM
(+SV) VCC
General Description ................................
Pinout ......................................... '...
Block Diagram .....................................
Interface Signal Description .........................
Functional Description ..............................
Control Port Registers ..............................
Data Port Registers ................................
Register Access ...................................
Master Mode Control Options .......................
Operating Mode Description .........................
Counter Mode Control Options ......................
Command Descriptions .............................
Maximum Ratings ..................................
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . ..
SWitching Characteristics ...........................
Applications Information ............................
7-110
7-110
7-111
7-111
7-113
7-114
7-116
7-117
7-118
7-120
7-124
7-126
7-130
7-130
7-132
7-134
OUT 3
OUT2
39
GATE 2
OUT 1
GATE 1
Xl
38
37
OUT 4
OUTS
36
X2
FOUT
35
34
GATE 3
GATE 4
GATES
C/O
\VA
cs
10
11
AD
DBO
DBl
Am9513
12
13
DB2
DB3
DB4
DBS
33
SOURCE 1,
32
31
SOURCE 2
SOURCE 3
30
SOURCE 4
29
28
SOURCES
27
26
DB14
16
25
17
24
DB6
DB7
23
22
21
GATE lA/DB8
Advanced Micro Devices reserves the right to modify information
contained in this document without notice.
Figure 1.
ORDERING INFORMATION
. Counting Frequency
Temperature Range
Molded
Hermetic*
7MHz
AM9513PC
O°C
~
TA ~ + 70°C
AM9513DC
AM9513CC
Hermetic
-55°C
~
TA
~
+125°C
*Hermetic = Ceramic = DC = CC = 0-40-1.
7-110
DB10/GATE 3A
DB9/GATE 2A
VSS (GND)
Top View
Pin 1 is marked for orientation.
Package Type
DB1S
DB13
DB12/GATE SA
DBll/GATE 4A
AM9513DM
MOS·172
Am9513
GENERAL BLOCK DIAGRAM
+ __--,
SOURCE 1·5 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
GATE 1·5 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-=1---,
Xl-----1
OUTS
X 2 - - - - - 1L...._ _ _....
FOUT
OUT4
OUT3
OUT2
WR--BUS
INTERFACE
Ro--CONTROL
cfo--CS - - - ' - -_ _ _ _ _.....
OUTI
MOS·169
Figure 2.
SRC
SRC
INPUT
SELECT
LOGIC
GATE
FREQ
GATE
FREQ
INPUT
SELECT
LOGIC
TCN-l
TCN-l
COUNTER
CONTROL
LOGIC
COUNTER
CONTROL
LOGIC
MOS·142
Figure 3. Counter Logic Groups 1 and 2.
Figure 4. Counter Logic Groups 3, 4 and 5.
INTERFACE SIGNAL DESCRIPTION
FOUT (Frequency Out, Output)
Figure 5 summarizes the interface signals and their abbreviations
for the STC. Figure 1 shows the signal pin assignments for the
standard 40-pin dual in-line package.
The FOUT output is derived from a 4-bit counter that may be
programmed to divide its input by any integer value from 1
through 16 inclusive. The input to the counter is selected from any
of 15 sources, including the internal scaled oscillator frequencies.
FOUT may be gated on and off under software control and when
off will exhibit a low impedance to ground. Control over the
various FOUT options resides in the Master Mode register. After
power-up, FOUT provides a frequency that is 1/16 that of the
oscillator.
VCC: +5 volt power supply
VSS: Ground
X1, X2 (Crystal)
GATE1-GATE5 (Gate, Inputs)
X1 and X2 are the connections for an external crystal used to
determine the frequency of the internal oscillator. The crystal
should be a parallel-resonant, fundamental-mode type. An RC or
LC or other reactive network may be used instead of a crystal. For
driving from an external frequency source, X1 should be left open
and X2 should be connected to a TTL source and a pull-up
resistor.
The Gate inputs may be used to control the operations of individual counters by determining when counting may proceed. The
same Gate input may control up to three counters. Gate pins may
also be selected as count sources for any of the counters and for
the FOUT divider. The active polarity for a selected Gate input is
programmed at each counter. Gating function options allow
level-sensitive gating or edge-initiated gating. Other gating
7-111
Am9513
modes are available including one that allows the Gate input to
select between two counter output frequencies. All gating functions may also be disabled. The active Gate input is conditioned
by an auxiliary input when the unit is operating with an external
8-bit data bus. See Data Bus description. Schmitt-trigger circuitry
on the GATE inputs allows slow transition times to be used.
SRC1-SRCS (Source, Inputs)
The Source inputs provide external signals that may be counted
by any of the counters. Any Source line may be routed to any or all
of the counters and the FOUT divider. The active polarity for a
selected SRC input is programmed at each counter. Any duty
cycle waveform will be accepted as long as the minimum pulse
width is at least half the period of the maximum specified counting
frequency for the part. Schmitt-trigger circuitry on the SRC inputs
allows slow transition times to be used.
OUT1-0UTS (Counter, Outputs)
Each 3-state OUT signal is directly associated with a corresponding individual counter. Depending on the counter configuration, the OUT signal may be a pulse, a square wave, or a
complex duty cycle waveform. OUT pulse polarities are individually programmable. The output circuitry detects the counter state
that would have been all bits zero in the absence of a reinitialization. That information is used to generate the selected waveform
type. An optional output mode for Counters 1 and 2 overrides the
normal output mode and provides a true OUT signal when the
counter contents match the contents of an Alarm register.
OBO-OB7, OB8-0B15 (Data Bus, Input/Output)
The 16, bidirectional Data Bus lines are used for information
exchanges with the host processor. HIGH on a Data Bus line
corresponds to one and LOW corresponds to zero. These lines
act as inputs when WR and CS are active and as outputs when
RD and CS are active. When CS is inactive, these pins are placed
in a high-impedance state.
After power-up or reset, the data bus will be configured for 8-bit
width and will use only DBO through DB7. DBO is the least significant and DB7 is the most significant bit position. The data bus
may be reconfigured for 16-bit width by changing a control bit in
Signal
+5 Volts
Ground
Crystal
Read
Write
Chip Select
Control/Data
Source N
Gate N
Data Bus
Frequency Out
Out N
Abbreviation
VCC
VSS
X1, X2
RD
WR
CS
C/O
SRC
GATE
DB
FOUT
OUT
Type
Power
Power
I/O, I
Input
Input
Input
Input
Input
Input
I/O
Output
Output
the Master Mode register. This is accomplished by writing an
8-bit command into the low-order DB lines while holding the
DB13-DB15 lines at a logic high level. Thereafter all 16 lines can
be used, with DBO as the least significant and DB15 as the most
significant bit position.
When operating in the 8-bit data bus environment, DB8-DB15 will
never be driven active by the Am9513. DB8 through DB12 may
optionally be used as additional Gate inputs (see Figure 6). If
unused they should be held high. When pulled low, a GATENA
signal will disable the action of the corresponding counter N
gating. DB13-DB15 should be held high in 8-bit bus mode
whenever CS and WR are simultaneously active.
CS (Chip Select, Input)
The active-low Chip Select input enables Read and Write operations on the data bus. When Chip Select is high, the Read and
Write inputs are ignored. The first Chip Select signal after
power-up is used to clear the power-on reset circuitry.
RO (Read, Input)
The active-low Read signal is conditioned by Chip Select and
indicates that internal information is to be transferred to the data
bus. The source will be determined by the port being addressed
and, for Data Port reads, by the contents of the Data Pointer
register. WR and RD should be mutually exclusive.
WR (Write, Input)
The active-low Write signal is conditioned by Chip Select and
indicates that data bus information is to be transferred to an
internal location. The destination will be determined by, the port
being addressed and, for Data Port writes, by the contents of the
Data Pointer register. WR and RD should be mutually exclusive.
C/o (Control/Data, Input)
The Control/Data signal selects source and destination locations
for read and write operations on the data bus. Control Write
operations load the Command register and the Data Pointer.
Control Read operations output the Status register. Data Read
and Data Write transfers communicate with all other internal
registers. Indirect addressing at the data port is controlled internally by the Data Pointer register.
Pins
2
1
1
1
5
5
16
5
Figure S. Interface Signal Summary.
Data Bus Width (MM14)
Package
Pin
16 Bits
12
13
14
15
16
17
18
19
20
22
23
24
25
26
27
28
DBO
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
8 Bits
DBO
DB1
DB2
DB3
DB4
DB5
DB6
DB7
GATE
GATE
GATE
GATE
GATE
(VI H)
(VIH)
(VIH)
Figure 6. Data Bus Assignments.
7-112
1A
2A
3A
4A
5A
Am9513
FUNCTIONAL DESCRIPTION
comparators associated with them, plus the extra logic necessary
for operating in a 24-hour time-of-day mode. For real-time operation the time-of-day logic will accept 50Hz, 60Hz or 100Hz input
frequencies.
The Am9513 block diagrams (Figures 2, 3 and 4) indicate the
interface signals and the basic flow of information. Internal control
lines and the internal data bus have been omitted. The control
and data registers are all connected to a common internal 16-bit
bus. The external bus may be a or 16 bits wide; in the a-bit mode
the internal 16-bit information is multiplexed to the low order data
bus pins DBO through DB7.
Each general counter has a single dedicated output pin. It may be
turned off when the output is not of interest or may be configured
in a variety of ways to drive interrupt controllers, Darlington buffers, bus drivers, etc. The counter inputs, on the other hand, are
specifically not dedicated to any given interface line. Considerable versatility is available for configuring both the input and the
gating of individual counters. This not only permits dynamic reassignment of inputs under software control, but also allows
multiple counters to use a single input, and allows a single gate
pin to control more than one counter. Indeed, a single pin can be
the gate for one counter and, at the same time, the count source
for another.
An internal oscillator provides a convenient source of frequencies
for use as counter inputs. The oscillator'S frequency is controlled
at the X1 and X2 interface pins by an external reactive network
such as a crystal. The oscillator output is divided by the Frequency Scaler to provide several sub-frequencies. One of the
scaled frequencies (or one of ten input signals) may be selected
as an input to the FOUT divider and then comes out of the chip at
the FOUT interface pin.
A powerful command structure simplifies user interaction with the
counters. A counter must be armed by one of the ARM commands before counting can commence. Once armed, the counting process may be further enabled or disabled using the
hardware gating facilities. The ARM and DISARM commands
permit software gating of the count process in some modes.
The STC is addressed by the external system as two locations: a
control port and a data port. The control port provides direct
access to the Status and Command registers, as well as allowing
the userto update the Data Pointer register. The data port is used
to communicate with all other addressable internal locations. The
Data Pointer register controls the data port addressing.
The LOAD command causes the counter to be reloaded with the
value in either the associated Load register or the associated
Hold register. It will often be used as a software retrigger or as
counter initialization prior to active hardware gating.
Among the registers accessible through the data port are the
Master Mode register and five Counter Mode registers, one for
each counter. The Master Mode register controls the programmable options that are not controlled by the Counter Mode
registers.
The DISARM command disables further counting independent of
any hardware gating. A disarmed counter may be reloaded using
the LOAD command, may be incremented or decremented using
the STEP command and may be read using the SAVE command.
A count process may be resumed using an ARM command.
Each of the five general-purpose counters is 16 bits long and is
independently controlled by its Counter Mode register. Through
this register, a user can software select one of 16 sources as the
counter input, a variety of gating and repetition modes, up or
down counting in binary or BCD and active-high or active-low
input and output polarities.
The SAVE command transfers the contents of a counter to its
associated Hold register. This command will overwrite any previous Hold register contents. The SAVE command is designed to
allow an accumulated count to be preserved so that it can be read
by the host CPU at some later time.
Associated with each counter are a Load register and a Hold
register, both accessible through the data port. The Load register
is used to automatically reload the counter to any predefined
value, thus controlling the effective count period. The Hold register is used to save count values without disturbing the count
process, permitting the host processor to read intermediate
counts. In addition, the Hold register may be used as a second
Load register to generate a number of complex output
waveforms.
Two combinations of the basic commands exist to either LOAD
AND ARM or to DISARM AND SAVE any combination of counters. Additional commands are provided to: step an individual
counter by one count; set and clear an output toggle; issue a
software reset; clear and set special bits in the Master Mode
register; and load the Data Pointer register.
All five counters have the same basic control logic and control
registers. Counters 1 and 2 have additional Alarm registers and
7-113
Am9513
The Data Pointer consists of a 3-bit Group Pointer, a 2-bit Element Pointer and a 1-bit Byte Pointer, depicted in Figure 8. The
Byte Pointer bit indicates which byte of a 16-bit register is to be
transferred on the next access through the data port. Whenever
the Data Pointer is loaded, the Byte Pointer bit is set to one,
indicating a least-significant byte is expected. The Byte Pointer
toggles following each 8-bit data transfer with an 8-bit data bus
(MM13 = 0), or it always remains set with the 16-bit data bus
option (MM13 = 1). The Element and Group pointers are used to
select which internal register is to be accessible through the Data
Port. Although the contents of the Element and Group Pointer in
the Data Pointer register cannot be read by the host processor,
the Byte Pointer is available as a bit in the Status register.
CONTROL PORT REGISTERS
The STC is addressed by the external system as only two locations: a Control port and a Data port. Transfers at the Control port
(C/O = High) allow direct access to the command register when
writing and the status register when reading. All other available
internal locations are accessed for both reading and writing via
the Data port (C/O = Low). Data port transfers are executed to
and from the location currently addressed by the Data· Pointer
register. Options available in the Master Mode register and the
Data Pointer control structure allow several types of transfer
sequencing to be used. See Figure 7.
Transfers to and from the control port are always 8 bits wide. Each
access to the Control port will transfer data between the Command register (writes) or Status register (reads) and Data Bus
pins DBO-DB7, regardless of whether the Am9513 is in 8-or 16-bit
bus mode. When the Am9513 is in 8-bit bus mode, Data Bus pins
DB13-D815 should be held at a logic high whenever CS and WR
are both active.
Random access to any available internal data location can be
accomplished by simply loading the Data Pointer using the command shown in Figure 9 and then initiating a data read or data
write. This procedure can be used at any time, regardless of the
setting of the Data Pointer Control bit (MM14). When the 8-bit data
bus configuration is being used (MM13 = 0), two bytes of data
would normally be transferred following the issuing of the "Load
Data Pointer" command.
Command Register
The Command register provides direct control over each of the
five general counters and controls access through the Data port
by allowing the user to update the Data Pointer register. The
"Command Description" section of this data sheet explains the
detailed operation of each command. A summary of all commands appears in Figure 21. Six of the command types are used
for direct software control of the counting process. Each of these
six commands contains a 5-bit S field. In a linear-select fashion,
each bit in the S field corresponds to one of the five general
counters (S1 = Counter 1, S2 = Counter 2, etc.). When an S bit is
a one, the specified operation is performed on the counter so
designated; when an S bit is a zero, no operation occurs for the
corresponding counter.
To permit the host processor to rapidly access the various internal
registers, automatic sequencing of the Data Pointer is provided.
Sequencing is enabled by clearing Master Mode bit 14 (MM14) to
zero. As shown in Figure 10, several types of sequencing are
available depending on the data bus width being used and the
initial Data Pointer value entered by command.
When E1 = 0 or E2 = 0 and G4, G2, G1 point to a Counter Group,
the Data Pointer will proceed through the Element cycle. The
Element field will automatically sequence through the three values 00, 01 and 10 starting with the value entered. When the
transition from 10 to 00 occurs, the Group field will also be
incremented by one. Note that the Element field in this case does
not sequence to a value of 11. The Group field circulates only
within the five Counter Group codes.
Data Pointer Register
The 6-bit Data Pointer register is loaded by issuing the appropriate command through the control port to the Command register. As shown in Figure 7, the contents of the Data Pointer register
are used to control the Data Port multiplexer, selecting which
internal register is to be accessible through the Data Port.
""C
CONTROL
PORT
+8
A
~16 to..
~
'"::>
CD
~
DATA
BUS
MULTIPLEXER
t
If E2, E1 = 11 and a Counter Group is selected, then only the
Group field is sequenced. This is the Hold cycle. It allows the Hold
registers to be sequentially accessed while bypassing the Mode
and Load registers. The third type of sequencing is the Control
I
I
I
1
I
I
COMMAND
REGISTER
6
BYTE
POINTER
1
,
I--
6
I
I
STATUS
REGISTER
DATA
PORT
f1
1+
.
~
I
DATA
PORT
MUX
L
lI--
8/16
I
DATA POINTER
REGISTER
5
GROUP AND ELEMENT
ADDRESS
M6
PREFETCtI
LATCH
I
I
c::>-
I
COUNTER 1 MODE REGISTER
I
COUNTER 1 LOAD REGISTER
I
COUNTER 1 HOLD REGISTER
I
fCOUNTERS 2. 3, 4, 5 MODE.
l LOAD AND HOLD REGISTERS
MASTER MODE REGISTER
I
COUNTER 1 ALARM REGISTER
J
COUNTER 2 ALARM REGISTER
I
MaS-SOl
Figure 7. Am9513 Register Access.
7-114
Am9513
I
G4
I . I
G2
l
G1
I
E2
I
E1
BP
I
I
I
' - - - - - - Byte Pointer
1 = Least significant Byte Transferred next
Most significant Byte Transferred next
o=
Group Pointer
000
001
010
011
100
101
110
111
=
=
=
=
=
=
=
=
L--_ _ _ _ _ _ _ _ _ _
Illegal
Counter Group 1
Counter Group 2 _ _ _ _ _ _ _ _ _
Counter Group 3
Counter Group 4
Counter Group 5
Illegal
Control Group - - - - - - - - - -
J
Element Pointer
t
OO = Mode Re~ister) Element Cycle
01 = Load Register
10 = Hold Register
Increment
11 = Hold Register/Hold Cycle Increment
00 = Alarm Register 1
)
01 = Alarm Register 2
Control Cycle
{ 10 = Master Mode Register Increment
11 = Status Register/No Increment
MOS·173
Figure 8. Data Pointer Register.
cycle. If G4, G2, G1 = 111 and E2, E1 i- 11, the Element Pointer
will be incremented through the values 00, 01 and 10, with no
change to the Group Pointer.
When G4, G2, G1 = 111 and E2, E1 = 11, no incrementing takes
place and only the Status register will be available through the
data port. Note that the Status register can also always be read
directly through the Control port.
For all of these auto-sequence modes, if an 8-bit data bus is used,
the Byte pointer will toggle after every data transfer to allow the
least and most significant bytes to be transferred before the
Element or Group Fields are incremented.
Prefetch Circuit
In order to minimize the read access time to internal Am9513
registers, a prefetch circuit is used for all read operations through
the Data Port. Following each read or write operation through the
Data Port, the Data Pointer register is updated to point to the next
register to be accessed. Immediately following this update, the
new register data is transferred to a special prefetch latch at the
interface pad logic. When the user performs a subsequent read of
the Data Port, the data bus drivers are enabled, outputting the
prefetched data on the bus. Since the internal data register is
accessed prior to the start of the read operation, its access time is
transparent to the user. In order to keep the prefetched data
consistent with the data pointer, prefetches are also performed
after each write to the Data Port and after execution at the "Load
Data Pointer" command. The following rules should be kept in
mind regarding Data Port Transfers.
1. The Data Pointer register should always be reloaded before
reading from the Data Port if a command other than "Load
Data Pointer" was issued to the Am9513 following the last
Data Port read or write. The Data Pointer does not have to be
loaded again if the first Data Port transaction after a command
entry is a write, since the Data Port write will automatically
cause a new pre fetch to occur.
2. Operating modes N, 0, Q and R allow the user to save the
counter contents in the Hold register by applying an activegOing gate edge. If the Data Pointer register had been pointing
to the Hold register in question, the prefetched value will not
correspond to the new value saved in the Hold register. To
7-115
avoid reading an incorrect value, a new "Load Data Pointer"
command should be issued before attempting to read the
saved data. A Data Port write (to another register) will also
initiate a prefetch; subsequent reads will access the recently
saved Hold register data. Many systems will use the "saving"
gate edge to interrupt the host CPU. In systems such as this
the interrupt service routine should issue a "Load Data
Pointer" command prior to reading the saved data.
Status Register
The 8-bit read-only Status register indicates the state of the Byte
Pointer bit in the Data Pointer register and the state of the OUT
signal for each of the general counters. See Figures 11 and 19.
The OUT signals reported are those internal to the chip after the
polarity-select logic and just before the 3-state interface buffer
circuitry.,
The Status register OUT bit reflects an active-high or active-low
TC output, or a TC Toggled output, as programmed in the Output
Control Field of the Counter Mode register. That is, it reflects the
Element Cycle
Counter 1
Counter 2
Counter 3
Counter 4
Counter 5
Hold Cycle
Hold
Mode
Register
Load
Register
~egister
Hold
Register
FF01
FF02
FF03
FF04
FF05
FF09
FFOA
FFOB
FFOC
FFOD
FF11
FF12
FF13
FF14
FF15
FF19
FF1A
FF1B
FF1C
FF1D
Master Mode Register = FF17
Alarm 1 Register = FF07
Alarm 2 Register = FFOF
Notes:
1. All codes are in hex.
2. When used with an 8-bit bus, only the two low order hex digits
should be written to the command port; the 'FF' prefix should be
used only for a 16-bit data bus interface.
Figure 9. Load Data Pointer Commands.
Am9513
exact state of the OUT pin. When the Low Impedance to Ground
Output option (CM2-CMO = 000) is selected, the Status register
will reflect an active-high TC Output. When a High Impedance
Output option (CM2-CMO = 100) is selected, the Status register
will reflect an active-low TC output.
For Counters 1 and 2, the OUT pin will reflect the comparator
output if the comparators are enabled. The Status register bit and
OUT pin are active high if CM2 = 0 and active-low if CM2 = 1.
When the High Impedance option is selected and the comparator
is enabled, the status register bit will reflect an active-high comparator output. When the Low Impedance to Ground option is
selected and the comparator is enabled, the status register bit will
reflect an active-low comparator output.
The Status register is normally accessed by reading the control
port (see Figure 7) but may also be read via the data port as part
of the Control Group.
Counter 1 Hold Reg.
Counter 1 Mode Reg.
Counter 2 Hold Reg.
Counter 1 Load Reg.
•
•
Counter 1 Hold Reg.
~
••
~
Counter 2 Mode Reg.
~
Counter 5 Hold Reg.
HOLD CYCLE
Counter 2 Load Reg.
~
Counter 2 Hold Reg.
~
••
As shown in Figures 3 and 4, each of the five Counter Logic
Groups consists of a 16-bit general counter with associated
control and output logic, a 16-bit Load register, a 16-bit Hold
register and a 16-bit Mode register. In addition, Counter Groups 1
and 2 also include 16-bit Comparators and 16-bit Alarm registers.
The comparator/alarm functions are controlled by the Master
Mode register. The operation of the Counter Mode registers is
the same for all five counters. The host CPU has both read and
write access to all registers in the Counter Logic Groups through
the data port. The counter itself is never directly accessed.
The 16-bit read/write Load register is used to control the effective
period of the general counter. Any 16-bit value may be written
into the Load register. That value can then be transferred into the
counter each time that Terminal Count (TC) occurs. "Terminal
Count" is defined as that period of time when the counter contents would have been zero if an external value had not been
transferred into the counter. Thus the terminal count frequency
can be the input frequency divided by the value in the Load
register. In all operating modes the contents of either Load or
Hold register will be transferred into the counter when TC occurs.
In cases where values are being accumulated in the counter, the
Load register action can be transparent by filling the Load register with all zeros.
The 16-bit read/write Hold register is dual-purpose. It can be
used in the same way as the Load register, thus offering an
alternate source for modulo definition for the counter. The Hold
register may also be used to store accumulated counter values
for later transfer to the host processor. This allows the count to be
sampled while the counting process proceeds. Transfer of the
counter contents into the Hold register is accomplished by the
hardware interface in some operating modes or by the software
SAVE command at any time.
Counter Mode Register
The 16-bit read/write Counter Mode register controls the gating,
counting, output and source select functions within each Counter
Logic Group. The "Counter Mode Control Options" section of this
data sheet describes the detailed control options available.
Figure 18 shows the bit assignments for the Counter Mode
registers.
Alarm Registers and Comparators
•
Counter 5 Hold Reg.
Alarm Reg. 1
~
DATA PORT REGISTERS
Counter Logic Groups
Added functions are available in the Counter Logic Groups for
Counters 1 and 2 (see Figure 3). Each contains a 16-bit Alarm
register and a 16-bit Comparator. When the value in the counter
reaches the value in the Alarm register, the Comparator output
will go true. The Master Mode register contains control bits to
individually enable/disable the comparators. When enabled, the
ELEMENT CYCLE
Alarm Reg. 2
Master Mode Reg.
CONTROL GROUP CYCLE
'STATUS CYCLE
OUT 4
OUT 5
OUT 2
OUT 3
BYTE
POINTER
OUT 1
MOS-175
MOS-174
Figure 10. Data Pointer Sequencing.
Figure 11. Status Register Bit Assignments.
7-116
Am9513
comparator output appears on the OUT pin of the associated
counter in place of the normal counter output. The output will
remain true as long as the comparison is true, that is, until the next
input causes the count to change. The polarity of the Comparator
output will be active-high if the Output Control field of the Counter
Mode register is 001 or 010 and active-low if the Output Control
field is 101.
REGISTER ACCESS
Information Transfer Protocols
The control signal configurations for all information transfers on
the Am9513 data bus are summarized in Figure 12. The interface
control logic assumes these conventions:
1. RD and WR are never active at the same time.
2. RD, WR and C/O are ignored unless CS is Low.
Command Initiation
1. Establish the appropriate command on the DBO-DB7 lines.
Figure 21 lists the command codes. When using the Am9513
in 16-bit mode, data bus lines DB8-DB15 should be set high
during the write operation. In 8-bit data bus mode, DB13-DB15
should be set high during the write operation.
2. Establish a High on the C/O input.
3. Establish a Low on the CS input.
4. Establish a Low on the WR input.
5. Sometime after the minimum WR low pulse duration has been
achieved, drive WR high, taking care the CS, ci5 and data
setup times are met (see Timing Diagram).
6. After meeting the required CS, ci5 and data hold times, these
signals can be changed (see Timing Diagram).
A new read or write operation to the Am9513 should not be
performed until the write recovery time is met (see Timing
Diagram).
Setting the Data Pointer Register
The Data Pointer register selects which register is to be accessed
through the data port. The Pointer is set as follows:
1. Using Figures 8 and 9, select the appropriate Data Pointer
Group and Element codes for the register to be accessed.
Note that two codes are provided for the Hold registers, to
accommodate both the Hold Cycle and Element Cycle autosequencing modes shown in Figure 10. If auto-sequencing is
disabled, either Hold code may be used.
Data Bus
Operation
CS C/O RD WR
0
0
0
0
0
Transfer contents of register addressed
by Data Pointer to the data bus.
0
0
0
Transfer contents of data bus to data
register addressed by Data Pointer.
Transfer contents of Status register to
data bus.
0
0
Transfer contents of data bus into
Command register.
X
X
1
No transfer.
1
X
X
X
No transfer.
X
X
0
0
Illegal Condition.
The Data Pointer register is now set. Setting the Data Pointer
register automatically sets the Byte Pointer to 1, ind~cating a least
significant byte is expected for 8-bit data bus interfacing. If Master
Mode register bit MM14 = a, the Data Pointer will automatically
sequence through one of the cycles shown in Figure 10 after
reading or writing each register. For convenience, bit MM14 can
be set or cleared by software command.
Reading the Status Register
The procedure for reading the Status register through the Control
port is given in the following. The Status register can also be read
from the data port as outlined in the Reading from the Data Port
section of this data sheet.
The procedure for executing a command is as follows:
Signal
Configuration
2. Using the "Writing to the Command Register" procedure
given above, write the appropriate "Load Data Pointer" command to the Command register. Note that the command
summary in Figure 21 has the Group field and Element field
switched from the format given in Figure 8.
Figure 12. Data Bus Transfers.
7-117
1. Establish a High on the ciiS input.
2. Establish a Low on the CS input.
3. After the appropriate CS and C/O setup time (see Timing
Diagram) make RD Low.
4. Sometime after RD goes Low, the Status register contents will
appear on the data bus. These lines will contain the information as long as RD is Low. If the state of an OUT pin changes
while RD is Low, this will be reflected by a change in the
information on the data bus.
5. RD can be driven High to conclude the read operation after
meeting the minimum RD pulse duration.
6. CS and C/O can change after meeting the appropriate hold
time requirements (see Timing Diagram).
A new read or write operation to the Am9513 should not be
attempted until the read recovery time is met (see Timing
Diagram).
Writing to the Data Port
The registers which can be written to through the data port are the
Load, Hold and Counter Mode registers for Counters 1 through 5,
the Alarm registers for Counters 1 and 2 and the Master Mode
register. The PlccDdure for writing to these three registers is as
follows:
1. Prior to performing the actual write operation, the Data Pointer
should be set to point to the register to be written to, as outlined
above in the "Setting the Data Pointer" section of this data
sheet. In cases where auto-sequencing of the Data Pointer is
used, the Pointer has to be set only once to the first register in
the sequence. When auto-sequencing is disabled, repetitive
accesses can be made to the same register without reloading
the Data Pointer each time.
2. Establish the appropriate data on the DBO-DB7Iines (8-bit bus
mode) or DBO-DB15 (16-bit bus mode). When using the 8-bit
bus mode, data bus lines DB13-DB15 should be set High
during the write operation and DBO-DB7 should be set to the
lower data byte for the first write and to the upper data byte for
the second write.
3. Establish a Low on the C/O input.
4. Establish a Low on the CS input.
5. Establish a Low on the WR input.
6. Drive WR High sometime after the minimum WR low pulse
duration has been achieved, taking care the CS, cif5 and data
setup times are met (see Timing Diagram).
7. After meeting the required CS, cio and data hold times, these
signals can be changed (see Timing Diagram).
8. After meeting the write recovery time (see Timing Diagram) a
new read or write operation can be performed. For the 8-bit
bus mode, steps 2 through 7 should be repeated, this time
II
Am9513
placing the high data byte on pins DBO-DB7. The user is not
required to drive CS or cio High between successive reads or
writes, although this is permissible.
Reading From the Data Port
The registers which can be read from the Data port are the Load,
Hold and Counter Mode registers for Counters 1 through 5, the
Alarm registers for Counters 1 and 2, the Master Mode register
and the Status register. The Status register can also be read from
the Control port. The procedure for reading these registers is as
follows:
1. Prior to performing the actual read operation, the Data Pointer
should be set to point to the register to be read, as outlined in
the "Settling the Data Pointer" section of this data sheet. In
cases where auto-sequencing of the Data Pointer is used, the
Pointer has to be set only once to the first register in the
sequence. When auto-sequencing is disabled, repetitive accesses can be made to the same register without reloading the
Data Pointer each time. Special care must be taken to reset
the Data Pointer after issuing a command other than "Load
Data Pointer" to the Am9513 or when operating a counter in
modes N, 0, Q or R. See the "Prefetch Circuit" section of this
document for elaboration.
2. Establish a Low on the C/O input.
3. Establish a Low on the CS input.
4. Establish a Low on RD after waiting for the appropriate CS and
cii5 setup time (see Timing Diagram).
5. Sometime after RD goes Low, the register contents will appear on the data bus. In both 8- and 16-bit bus modes the low
register byte will appear on DBO-DB7. In addition, in 16-bit bus
mode, the upper register byte will appear on DB8-DB15. For
8-bit bus mode, pins DB8-DB15 are not driven by the Am9513.
This information will remain stable as long as RD is Low. If the
register value is changed during the read, the change will not
be reflected by a change in the data being read, for the
reasons outlined in the "Prefetch Circuit" section of this
document.
6. RD can be driven High to conclude the read operation after
meeting the minimum RD pulse duration.
7. CS and C/O can change after meeting appropriate hold time
requirements (see Timing Diagram).
8. After waiting the minimum read recovery time (see Timing
Diagram), a new read or write operation can be started. For
8-bit bus mode, steps 2 through 7 should be repeated to read
out the high register byte on DBO-DB7. (If the Status register is
being read in 8-bit mode, the two reads will return the Status
register each time. In 16-bit mode, reads from the Status
register return undefined data on DB8-0B15.) The user is not
required to drive CS or C/O High between successive reads or
writes, although this is permissible.
MASTER MODE CONTROL OPTIONS
The 16-bit Master Mode (MM) register is used to control those
internal activities that are not controlled by the individual Counter
Mode registers. This includes frequency control, time-of-day operation, comparator controls, data bus width and data pOinter
sequencing. Figure 13 shows the bit assignments for the Master
Mode register. This section describes the use of each control
field.
Master Mode register bits MM12, MM13 and MM14 can be individually set and reset using commands issued to the Command
register. In addition they can all be changed by writing directly to
the Master Mode register.
FOUT Divider
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
FOUT Source
= Divide by 16
= Divide by 1
= Divide by 2
= Divide by 3
= Divide by 4
= Divide by 5
= Divide by 6
= Divide by 7
= Divide by 8
= Divide by 9
= Divide by 10
= Divide by 11
= Divide by 12
= Divide by 13
= Divide by 14
= Divide by 15
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
= Fl
= SRC 1
= SRC 2
= SRC 3
= SRC 4
= SRC 5
= GATE 1
= GATE 2
= GATE 3
= GATE 4
= GATE 5
= Fl
= F2
= F3
= F4
= F5
~
FOUT Gate
0= FOUT On
1 = FOUT Off (Low Z to GND)
Compare 2 Enable
0= Disabled
1 = Enabled
Data Bus Width
0= 8-Bit Bus
1 = 16-Bit Bus
Compare 1 Enable
0= Disabled
1 = Enabled
Time-of-Day Mode _ _ _ _ _ _---1
00 = TOO Disabled
01 = TOO Enabled; 7 5 Input
10 = TOO Enabled; 7 6 Input
11 = TOO Enabled; 7 10 Input
Data Pointer Control
o = Enable Increment
1 = Disable Increment
Scaler Control
o = Binary Division
1 = BCD Division
Figure 13. Master Mode Register Bit ASSignments.
7-118
Mos·leo
Am9513
C15
C12
CB
I
Counter 21
C4
I
I
Hours
C15
Counter 1
I
Minutes
C12
I
ing can be, respectively, 50Hz, 60Hz or 100Hz. With divide-by-ten
specified and with 100Hz input, the least significant decade of
Counter 1 accumulates time in hundredths of seconds (tens of
milliseconds). For accelerated time applications other input frequencies may be useful.
CO
CB
I
C4
I
I
Seconds
The input for Counter 2 should be the TC output of Counter 1,
connected either internally or externally, for TOO operation. Both
counters should be set up for BCD counting. The Load registers
should be use~ to initialize the counters to the proper time. Either
count up or count down may be used.
CO
I
To read the time, a SAVE command should be issued to Counters
1 and 2. Because counts ripple between the counters, the possibility exists of the SAVE command occurring after Counter 1 has
counted but before Counter 2 has. This would result in an incorrectly saved time. To guard against this, Counter 2 should be
resaved if Counter 1's saved value indicates a ripple carry/borrow
may have been generated. In other words, Counter 2 should be
resaved if the value saved from Counter 1 is 0 (up counting),
59.94 (down counting, MM1-MMO = 01), 59.95 (down counting,
MM1-MMO = 10), or 59.99 (down counting, MM1-MMO = 11). By
the time this test is performed and Counter 2 is resaved, any
rippling carry/borrow will have updated Counter 2.
+ 5, 6, or 10
1/10 Sec.
MOS-1B2
Figure 14. Time-of-Day Storage Configuration.
After power-on reset or a Master Reset command, the Master
Mode register is cleared to an all zero condition. This results in the
following configuration:
Time-of-day disabled
Both Comparators disabled
FOUT Source is frequency F1
FOUT Divider set for divide-by-16
FOUT gated on
Data Bus 8 bits wide
Data Pointer Sequencing enabled
Frequency Scaler divides in binary
Comparator Enable
Bits MM2 and MM3 control the Comparators associated with
Counter 1 and 2. When a Comparator is enabled, its output is
substituted for the normal counter output on the associated OUT1
orOUT2 pin. The comparator output will be active-high if the
output control ,field of the Counter Mode register is 001 or 010 and
active low for a code of 101. Once the compare output is true, it will
remain so until the count changes and the comparison therefore
goes false.
Time-of-Day
Bits MMO and MM1 of the Master Mode register specify the
time-of-day (TOO) options. When MMO = 0 and MM1 = 0, the
special logic used to implement TOO is disabled and Counters 1
and 2 will operate in exactly the same way as Counters 3, 4 and 5.
When MMO = 1 or MM1 = 1, additional counter decoding and
control logic is enabled on Counters 1 and 2 which causes their
decades to turn over at the counts that generate appropriate
24-hour TOO accumulations.
The two Comparators can always be used individually in any
operating mode. One special case occurs when the time-of-day
option is invoked and both Comparators are enabled. The operation of Comparator 2 will then be conditioned by Comparator 1 so
that a full 32-bit compare must be true in order to generate a true
signal on OUT2. OUT1 will continue, as usual, to reflect the state
of the 16-bit comparison between Alarm 1 and Counter 1.
Figure 14 shows the counter configurations for TOO operation.
The, two most significant decades of Counter 2 contain the
"hours" digits and they can hold a maximum count of 23 hours.
The two least Significant decades of Counter 2 indicate "minutes"
and will hold values up to 59. The three most significant decades
of Counter 1 indicate "seconds" and will contain values up to
59.9. The least significant decade of Counter 1 is used to scale
the input frequency in order to output tenth-of-second periods into
the next decade. It can be set up to divide-by-five (MMO = 1, MM1
= 0), divide-by-six (MMO = 0, MM1 = 1), or divide-by-ten (MMO =
1, MM1 = 1). The input frequency, therefore, for real-time clock-
FOUT Source
Master Mode bits MM4 through MM7 specify the source input for
the FOUT divider. Fifteen inputs are available for selection and
they include the five Source pins, the five Gate pins and the five
internal frequencies derived from the oscillator. The 16th combination of the four control bits (all zeros) is used to assure that an
active frequency is available at the input to the FOUT divider
following reset.
FOUT Divider
1
TCN-l_
GATEN-l _
GATEN _
1
MGU~~~pl~:XU:R
COUNTER MODE
REGISTER
Bits MM8 throught MM11 specify the dividing ratio for the FOUT
Divider. The FOUT source (selected by bits MM4 through MM7) is
divided by an integer value between 1 and 16, inclusive, and is
then passed to the FOUT output buffer. After power-on or reset,
the FOUT divider is set to divide-by-16.
1
I
rpo-
AND POLARITY
SELECT LOGIC
GATEN+l-,L-_ _ _ _--I
GATEN/A - - - - - - - - '
FOUT Gate
EDGE
LEVEL
AND
GATE
CONTROL
LOGIC
H I
COUNTER
MOS-179
Master Mode bit MM12 provides a software gating capability for
the FOUT signal. When MM12 = 1, FOUT is off and in a low
impedance state to ground. MM12 may be set or cleared in
conjunction with the loading of the other bits in the Master Mode
register; alternatively, there are commands that allow MM12 to be
individually set or cleared directly without changing any other
Master Mode bits. After power-up or reset, FOUT is gated on.
Figure 15. Gating Control.
7-119
Am9513
When changing the FOUT divider ratio or FOUT source, transient
pulses as short as half the period of the FOUT source may appear
on the FOUT pin. Turning the FOUT gate on or off can also
generate a transient. This should be considered when using
FOUT as a system clock source.
the oscillator frequency in binary steps so that each subfrequency is 1/16 of the preceding frequency. When MM15 = 1,
the Scaler divides in BCD steps so that adjacent frequencies are
related by ratios of 10 instead of 16 (see Figure 16).
.
Bus Width
OPERATING MODE DESCRIPTIONS
Bit MM13 controls the multiplexer at the data bus interface in
order to configure the part for an a-bit or 16-bit external bus. The
internal bus is always 16 bits wide. When MM13 = 1, 16-bitdatais
transferred directly between the internal bus and all 16 of the
external bus lines. In this configuration, the Byte Pointer bit in the
Data Pointer register remains set at all times. When MM13 = 0,
16-bit internal data is transferred a byte at a time to and from the
eight low-order external data bus lines. The Byte Pointer bit
toggles with each byte transfer in this mode.
Counter Mode register bits CM15-CM13 and CM7 -CM5 select the
operating mode for each counter (see Figure 17). To simplify
references to a particular mode, each mode is assigned a letter
from A through X.
To keep the following mode descriptions concise and to the point,
the phrase "source edges" is used to refer to active-going source
edges only, not to inactive-going edges. Smilarly, the phrase
"gate edges" refers only to active-going gate edges. Also, again
to avoid verbosity and euphuism, the descriptions of some modes
states that a counter is stopped or disarmed "on a TC, inhibiting
further counting." As is fully explained in the TC section of this
data sheet, for these modes the counter is actually stopped or
disarmed following the active-going source edge which drives the
counter out of TC. In other words, since a counter in the TC state
always counts, irrespective of its gating or arming status, the
stopping or disarming of the count sequence is delayed until TC
is terminated.
When the Am9513 is set to operate with an a-bit data bus width,
pins DB8 through DB15 are not used for the data bus and are
available for other functions. Pins DB13 through DB15 should be
tied high. Pins DBa through DB12 are used as auxiliary gating
inputs, and are labeled GATE1A through GATE5A respectively.
The auxiliary gate pin, GATENA, is logically ANDed with the gate
input to Counter N, as shown in Figure 15. The output of the AN D
gate is then used as the gating signal for Counter N.
Data Pointer Sequencing
MODE A
Software-Triggered Strobe with No Hardware Gating
Bit MM14 controls the Data Pointer logic to enable or disable the
automatic sequencing functions. When MM14 = 1, the contents
of the Data Pointer can be changed only directly by entering a
command. When MM14 = 0, several types of automatic
sequencing of the Data Pointer are available. These are described in the Data Pointer register section of this document.
Mode A is one of the simplest operating modes. The counter will
be available for counting source edges when it is issued an ARM
command. On each TC the counter will reload from the Load
register and automatically disarm itself, inhibiting further counting. Counting will resume when a new ARM command is issued.
Thus the host processor, by controlling MM14, may repetitively
read/write a single internal location, or may sequentially read/
write groups of locations. Bit MM14 can be loaded by writing to the
Master Mode register or can be set or cleared by software
command.
MODEB
Software-Triggered Strobe with Level Gating
Mode B is identical to Mode A except that source edges are
counted only when the assigned Gate is active. The counter must
be armed before counting can occur. Once armed, the counter
will count all source edges which occur while the Gate is active
and disregard those edges which occur while the Gate is inactive.
Scaler Ratios
Master Mode bit MM15 confrols the counting configuration of the
Frequency Scaler counter. When MM15 = 0, the Scaler divides
. . . . - - - - - - - - - - - - - - - - - - - - - - - - - - - - _ ' F1
....-----------------------F2
....----------------F3
r---------
r-;=.------;l
X1OSC
X2_
t-------;-~
I
4 BITS
4 BITS
I
I
4 BITS
I
=:J
4 BITS
~ _ _I_ _I_ _I_ _I_ _ _
F4
1 - - - ; - - F5
FREQUENCY SCALER
Frequency
F1
F2
F3
F4
F5
BCD
Scaling
MM15 = 1
Binary
Scaling
MM15 = 0
OSC
OSC
F1
F1
F1
F1
+ 10
+ 100
+ 1,000
+ 10,000
F1
F1
F1
F1
Figure 16. Frequency Scaler Ratios.
7-120
+ 16
+ 256
+ 4,096
+ 65,536
MOS·1S0
Am9513
Operating Mode
A
B
C
D
E
F
G
H
I
J
K
L
Special Gate (CM?)
0
0
0
0
0
0
0
0
0
0
0
0
Reload Source (CM6)
0
0
0
0
0
0
1
1
1
1
1
1
Repetition (CM5)
0
0
0
1
1
1
0
0
0
1
1
1
Gate Control (CM15-CM13)
Count to TC once, then disarm
000
X
LEVEL EDGE
X
000
LEVEL EDGE
000
X
Count to TC twice, then disarm
X
Count to TC repeatedly
Gate input does not gate counter input
X
X
Start count on active gate edge and
stop count on next TC.
X
000
LEVEL EDGE
X
X
X
X
X
X
X
Count only during active gate level
LEVEL EDGE
X
X
X
X
X
X
X
X
Start count on active gate edge and
stop count on second TC.
X
No hardware retriggering
X
X
X
X
X
X
Reload counter from Load Register
on TC
X
X
X
X
X
X
Reload counter on each TC, a~ernating
reload source between Load and Hold
Registers.
X
X
X
X
X
X
X
X
X
X
X
X
X
Transfer Load Register into counter on
each TC that gate is LOW; transfer Hold
Register into counter on each TC that
gate is HIGH.
On active gate edge transfer counter
into Hold Register and then reload
counter from Load Register.
Operating Mode
M
N
O·
P
Q
R
S
T
U
V
W
X
Special Gate (CM?)
1
1
1
1
1
1
1
1
1
1
1
1
Reload Source (CM6)
0
0
0
0
0
0
1
1
1
1
1
1
Repetition (CM5)
0
0
0
1
1
1
0
0
0
1
1
1
Gate Control (CM15-CM13)
Count to TC once .. then disarm
000
LEVEL EDGE
X
000
LEVEL EDGE
000
000
X
Count to TC twice, then disarm
X
Count to TC repeatedly
X
X
Gate input does not gate counter input
Count only during active gate level
LEVEL EDGE
X
Start count on aCtive gate edge and
stop count on next TC.
X
X
X
X
X
X
X
X
X
X
Start count on active gate edge and
stop count on second TC.
No hardware retriggering
Reload counter from Load Register
on TC
X
X
X
X
Reload counter on each TC, alternating
reload source between Load and Hold
Registers.
Transfer Load Register into counter on
each TC that gate is LOW; transfer Hold
Register into counter on each TC that
gate is HIGH.
On active gate edge transfer counter
into Hold Register and then reload
counter from Load Register.
X
X
X
X
Note: Operating modes M, P, T, U, Wand X are reserved and should not be used.
Figure 17. Counter Control Interaction.
7-121
LEVEL EDGE
Am9513
This permits the Gate to turn the count process on and off. On
each TC the counter will reload from the Load register and automatically disarm itself, inhibiting further counting until a new
ARM command is issued.
MODEC
Hardware-Triggered Strobe
Mode C is identical to Mode A, except that counting will not begin
until a Gate edge is applied to the armed counter. The counter
must be armed before application of the triggering Gate edge;
Gate edges applied to a disarmed counter are disregarded. The
counter will start counting on the first source edge after the
triggering Gate edge and will continue counting until TC. At TC,
the counter will reload from the Load register and automatically
disarm itself. Counting will then remain inhibited until a new ARM
command and a new" Gate edge are applied in that ordor. Noto
that after application of a triggering Gate edge, the Gate input will
be disregarded for the remainder of the count cycle. This differs
from Mode S, where the Gate can be modulated throughout the
count cycle to stop and start the counter.
MODE D
Rate Generator with No Hardware Gating
Mode D is typically used in frequency generation applications. In
this mode, the Gate input does not affect counter operation. Once
armed, the counter will count to TC repetitively. On each TC the
counter will reload itself from the Load register; hence the Load
register value determines the time between TCs. A square wave
rate generator may be obtained by specifying the TC Toggled
output mode in the Counter Mode register.
MODE E
Rate Generator with Level Gating
Mode E is identical to Mode D, except the counter will only count
those source edges which occur while the Gate input is active.
This feature allows the counting process to be enabled and
disabled under hardware control. A square wave rate generator
may be obtained by speCifying the TC Toggled output mode.
MODE F
Non-Retriggerable One-Shot
Mode F provides a non-retriggerable one-shot timing function.
The counter must be armed before it will function. Application of a
Gate edge to the armed counter will enable counting. When the
counter reaches TC, it will reload itself from the Load register. The
counter will then stop counting, awaiting a new Gate edge. Note
that unlike Mode C, a.new ARM command is not needed afterTC,
only a new Gate edge. After application of a triggering Gate edge,
the Gate input is disregarded until TC.
MODEG
Software-Triggered Delayed Pulse One-Shot
I
I
In Mode G, the Gate does not affect the counter's operation. Once
armed, the counter will count to TC twice and then automatically
disarm itself. For most applications, the counter will initially be
loaded from the Load register either by a LOAD command or by
the last TC of an earlier timing cycle. Upon counting to the first TC,
the counter will reload itself from the Hold register. Counting will
proceed until the second TC, when the counter will reload itself
from the Load register and automatically disarm itself, inhibiting
further counting. Counting can be resumed by issuing a new ARM
command. A software-triggered delayed pulse one-shot may be
generated by specifying the TC Toggled output mode in the
Counter Mode register. The initial counter contents control the
delay from the ARM command until the output pulse starts. The
Hold register contents control the pulse duration.
MODEH
Software-Triggered Delayed Pulse One-Shot with Hardware
Gating
Mode H is identical to Mode G except that th'3 Gate input is used
to qualify which source edges are to be counted. The counter
must be armed for counting to occur. Once armed, the counter will
count all source edges that occur while the Gate is active and
disregard those source edges that occur while the Gate is inactive. This permits the Gate to turn the count process on and off. As
with Mode G, the counter will be reloaded from the Hold register
on the first TC and reloaded from the Load register and disarmed
on the second TC. This mode allows the Gate to control the
extension of both the initial output delay time and the pulse width.
MODEl
Hardware-Triggered Delayed Pulse Strobe
Mode I is identical to Mode G, except that counting will not begin
until a Gate edge is applied to an armed counter. The counter
must be armed before application of the triggering Gate edge;
Gate edges applied to a disarmed counter are disregarded. An
armed counter will start counting on the first source edge after the
triggering Gate edge. Counting will then proceed in the same
manner as in Mode G. After the second TC, the counter will
disarm itself. An ARM command and Gate edge must be issued in
this order to restart counting. Note that after application of a
triggering Gate edge, the Gate input will be disregarded until the
second TC. This differs from Mode H, where the Gate can be
modulated throughout the count cycle to stop and start the
counter.
MODEJ
Variable Duty Cycle Rate Generator with No Hardware
Gating
Mode J will find the greatest usage in frequency generation
applications with variable duty cycle requirements. Once armed,
the counter will count continuously until it is issued a DISARM
command. On the first TC, the counter will be reloaded from the
Hold register. Counting will then proceed until the second TC at
which time the counter will be reloaded from the Load register.
Counting will continue, with the reload source alternating on each
TC, until a DISARM command is issued to the counter. (The third
TC reloads from the Hold register, the fourth TC reloads from the
Load register, etc.) A variable duty cycle output can be generated
by specifying the TC Toggled output in the Counter Mode register. The Load and Hold values then directly control the output duty
cycle, with high resolution available when relatively high count
values are used.
MODEK
Variable Duty Cycle Rate Generator with Level Gating
Mode K is identical to Mode J except that source edges are only
counted when the Gate is active. The counter must be armed for
counting to occur. Once armed, the counter will count all source
edges which occur while the Gate is active and disregard those
source edges which occur while the Gate is inactive. This permits
the Gate to turn the count process on and off. As with Mode J, the
reload source used will alternate on each TC, starting with the
Hold register on the first TC after any ARM command. When the
TC Toggled output is used, this mode allows the Gate to modulate
the duty cycle of the output waveform. It can affect both the high
and low portions of the output waveform.
MODEL
Hardware-Triggered Delayed Pulse One-Shot
Mode L is similar to Mode J except that counting will not begin
until a Gate edge is applied to an armed counter. The counter
must be armed before application of the triggering Gate edge;
7-122
Am9513
Gate edges applied to a disarmed counter are disregarded. The
counter will start counttng source edges after the triggering Gate
edge and counting will proceed until the second TC. Note that
after application of a triggering Gate edge, the Gate input will be
disregarded for the remainder of the count cycle. This differs from
Mode K, where the gate can be modulated throughout the count
cycle to stop and start the counter. On the first TC after application
of the triggering Gate edge, the counter will be reloaded from the
Hold register. On the second TC, the counter will be reloaded
from the Load register and counting will stop until a new gate edge
is issued to the counter. Note that unlike Mode K, new Gate edges
are required after every second TC to continue counting.
MODEN
Software-Triggered Strobe with Level Gating and Hardware
Retriggering
the Gate is active and disregard those edges which occur while
the Gate is inactive. This permits the Gate to turn the count
process on and off. After the issuance of an ARM command and
the application of an active Gate, the counter will count to TC
repetitively. On each TC the counter will reload itself from the
Load register. The counter may be retriggered at any time by
presenting an active-going Gate edge to the Gate input. The
retriggering Gate edge will transfer the contents of the counter
into the Hold register. The first qualified source edge after the
retriggering Gate edge will transfer the contents of the Load
register into the counter. Counting will resume on the second
qualified source edge after the retriggering gate edge. Qualified
source edges are active-going edges which occur while the Gate
is active.
MODE R
Mode N provides a software-triggered strobe with level gating
that is also hardware retriggerable. The counter must first be
issued an ARM command before counting can occur. Once
armed, the counter will count all source edges which occur while
the gate is active and disregard those source edges which occur
while the Gate is inactive. This permits the Gate to turn the count
process on and off. After the issuance of an ARM command and
the application of an active Gate, the counter will count to TC.
Upon reaching TC, the counter will reload from the Load register
and automatically disarm itself, inhibiting further counting.
Counting will resume upon the issuance of a new ARM command.
All active-going Gate edges issued to an armed counter will
cause a retrigger operation. Upon application of the Gate edge,
the counter contents will be saved in the Hold register. On the first
qualified source edge after application of the retriggering gate
edge the contents of the Load register will be transferred into the
counter. Counting will resume on the second qualified source
edge after the retriggering Gate edge. Qualified source edges are
active-going edges which occur while the Gate is active.
MODE 0
Software-Triggered Strobe with Edge Gating and Hardware
Retriggering
Retriggerable One-Shot
Mode R is similar to Mode Q, except that edge gating rather than
level gating is used. In other words, rather than use the Gate level
to qualify which source edges to count, Gate edges are used to
start the counting operation. The counter must be armed before
application of the triggering Gate edge; Gate edges applied to a
disarmed counter are disregarded. After application at a Gate
edge, an armed counter will count all source edges until TC,
irrespective of the Gate level. On the first TC the counter will be
reloaded from the Load register and stopped. Subsequent
counting will not occur until a new Gate edge is applied. All Gate
edges applied to the counter, including the first used to trigger
counting, initiate a retrigger operation. Upon application of a Gate
edge, the counter contents are saved in the Hold register. On the
first source edge after the retriggering Gate edge, the Load register contents will be transferred into the counter. Counting will
resume on the second source edge after the retriggering Gate
edge.
MODES
In this mode, the reload source for LOAD commands (irrespective
of whether the counter is armed or disarmed) and for TC-initiated
reloads is determined by the Gate input. The Gate input in Mode S
is used only to select the reload source, not to start or modulate
counting. When the Gate is Low, the Load register is used; when
the Gate is High, the Hold register is used. Note the Low-Load,
High-Hold mnemonic convention. Once armed, the counter will
count to TC twice and then disarm itself. On each TC the counter
will be reloaded from the reload source selected by the Gate.
Following the second TC, an ARM command is required to start a
new counting cycle.
a
Mode is similar to Mode N, except that counting will not begin
until an active-going Gate edge is applied to an armed counter
and the Gate level is not used to modulate counting. The counter
must be armed before application of the triggering Gate edge;
Gate edges applied to a disarmed counter are disregarded. Irrespective of the Gate level, the counter will count all source edges
after the triggering Gate edge until the first TC. On the first TC the
counter will be reloaded from the Load register and disarmed. A
new ARM command and a new Gate edge must be applied in that
order to initiate a new counting cycle. Unlike Modes C, F, I and L,
which disregard the Gate input once counting starts, in Mode
the count process will be retriggered on all active-going Gate
edges, including the first Gate edge used to start the counter. On
each retriggering Gate edge, the counter contents will be transferred into the Hold register. On the first source edge after the
retriggering Gate edge the Load register contents will be transferred into the counter. Counting will resume on the second source
edge after a retrigger.
a
MODE V
Frequency-Shift Keying
Mode V provides frequency-shift keying modulation capability.
Gate operation in this mode is identical to that in Mode S. If the
Gate is Low, a LOAD command or a TC-induced reload will reload
the counter from the Load register. If the Gate is High, LOADs and
reloads will occur from the Hold register. The polarity of the Gate
only selects the reload source; it does not start or modulate
counting. Once armed, the counter will count repetitively to TC.
On each TC the counter will reload itself from the register determined by the polarity of the Gate. Counting will continue in this
manner until a DISARM command is issued to the counter. Frequency shift keying may be obtained by specifying a TC Toggled
output mode in the Counter Mode register. The switching of
frequencies is achieved by modulating the Gate.
MODEQ
Rate Generator with Synchronization
(Event Counter with Auto-Read/Reset)
Mode Q provides a rate generator with synchronization or an
event counter with auto-read/reset. The counter must first be
issued an ARM command before counting can occur. Once
armed, the counter will count all source edges which occur while
7-123
Am9513
COUNTER MODE CONTROL OPTIONS
Output Control
Each Counter Logic Group includes a 16-bit Counter Mode (CM)
register used to control all of the individual options available with
its associated general counter. These options include output
configuration, count control, count source and gating control.
Figure 18 shows the bit assignments for the Counter Mode registers. This section describes the control options in detail. Note that
generally each counter is independently configured and does not
depend on information outside its Counter Logic Group. The
Counter Mode register should be loaded only when the counter is
Disarmed. Attempts to load the Counter Mode register when the
counter is armed may result in erratic counter operation.
Counter mode bits CMO through CM2 specify the output control
configuration. Figure 19 shows a schematic representation of the
output control logic. The OUT pin may be off and in a high
impedance state, or it may be off with a low impedance to ground.
The three remaining valid combinations represent the two basic
output waveforms.
After power-on reset or a Master Reset command, the Counter
Mode registers are initialized to a preset condition. The value
entered is OBOO hex and results in the following control
configuration:
Output low impedance to ground
Count down
Count binary
Count once
Load register selected
No retriggering
F1 input source selected
Positive-true input polarity
No gating
One output form available is called Terminal Count (TC) and
represents the period in time that the counter reaches an equivalent value of zero. TC will occur on the next count when the
counter is at 0001 for down counting, at 9999 (BCD) for BCD up
counting or at FFFF (hex) for binary up counting. Figure 20 shows
a Terminal Count pulse and an example context that generated it.
The TC width is determined by the period of the counting source.
Regardless of any gating input or whether the counter is Armed or
Disarmed, the terminal count will go active for only one clock
cycle. Figure 20 assumes active-high source polarity, counter
armed, counter decrementing and an external reload value of K.
The counter will always be loaded from an external location when
TC occurs; the user can choose the source location and the
value. If a non-zero value is picked, the counter will never really
attain a zero state and TC will indicate the counter state that
would have been zero had no parallel transfer occurred.
The other output form, TC Toggled, uses the trailing edge of TC to
toggle a flip-flop to generate an output level instead of a pulse.
Count Source Selection
Count Control
OXXXX = Count on Rising Edge
1XXXX = Count on Falling Edge
XOOOO = TCN-1
X0001 = SRC 1
X0010 = SRC 2
X0011 = SRC 3
X0100 = SRC 4
X0101 = SRC 5
X0110 = GATE 1
X0111 = GATE 2
X1000 = GATE 3
X1001 = GATE 4
X1010 = GATE 5
X1011=F1
X1100 = F2
X1101=F3
X1110 = F4
X1111 = F5
[
OXXXX
1XXXX
XOXXX
X1 XXX
XXOXX
XX1 XX
XXXOX
XXX1X
XXXXO
XXXX1
Output Control _ _ _---I
Gating Control
000
001
010
011
100
101
110
111
=
=
=
=
=
=
=
=
= Disable Special Gate
= Enable Special Gate
= Reload from Load
= Reload from Load or Hold
= Count Once
= Count Repetitively
= Binary Count
= BCD Count
= Count Down
= Count Up
No Gating
Active High Level TCN-1
Active High Level GATE N+1
Active High Level GATE N-1
Active High Level GATE N
Active Low Level GATE N
Active High Edge GATE N
Active Low Edge GATE N
000
001
010
011
100
101
110
111
=
=
=
=
=
=
=
=
Inactive, Output Low
Active High Terminal Count Pulse
TC Toggled
Illegal
Inactive, Output High Impedance
Active Low Terminal Count Pulse
Illegal
Illegal
MOS-176
Note: See Figure 17 for restrictions on Count Control and Gating Control bit combinations.
Figure 18. Counter Mode Register Bit Assignments.
7-124
Am9513
1------1
I
I
COUNTER
OUTPUT
TC/TC TOGGLED
SELECT
I
2:1 MUX
I
I
I
LOW ZTO
GROUND/HIGH
Z CONTROL
OUT
PIN
I--
I
r-
I
INTERNAL TC
~ CONNECTION TO
ADJACENT COUNTER
POLARITY
CONTROL
I
COMPARATOR
OUTPUT
L -----------
I
'------ TO STATUS
REGISTER
~
MOS-502
COUNTERS 1 AND 2 ONLY
Figure 19. Output Control Logic.
The toggle output is 1/2 the frequency of TC. The TC Toggled
output will frequently be used to generate variable duty-cycle
square waves in Operating Modes G through K.
In Mode L the TC Toggled output can be used to generate a
one-shot function, with the delay to the start of the output pulse
and the width of the output pulse separately programmable. With
selection of the minimum delay to the start of the pulse, the output
will toggle on the source pulse following application of the triggering Gate edge.
Note that the TC Toggled output form contains no implication
about whether the output is active-high or active-low. Unlike the
TC output, which generates a transient pulse which can clearly be
active-high or active-low, the TC Toggled output waveform only
flips the state of the output on each TC. The sole' criteria of
whether the TC Toggled output is active-high or active-low is the
level of the output at the start of the count cycle. This can be
controlled by the Set and Clear Output commands.
TC (TERMINAL COUNT)
On each Terminal Count (TC), the counter will reload itself from
the Load or Hold register. TC is defined as that period of time
when the counter contents would have been zero had no reload
occurred. Some special conditions apply to counter operation
immediately before and during TC.
1_ In the clock cycle before TC, an internal signal is generated
that commits the counter to go to TC on the next count, and
retriggering by a hardware Gate edge (Modes N, 0, Q and R)
or a software LOAD or LOAD-and-ARM command will not
extend the time to TC. Note that the "next count" driving the
counter to TC can be caused by the application of a count
source edge (in level gating modes, the edge must occur while
the gate is active, or it will be disregarded), by the application
of a LOAD or LOAD-and-ARM command (see 2 below) or by
the application of a STEP command.
2. If a LOAD or LOAD-and-ARM command is executed during
the cycle preceding TC, the counter will immediately go to TC.
If these commands are issued during TC, the TC state will
immediately terminate.
3. When TC is active, the counter will always count the next
source edge issued to it, even if it is disarmed or gated off
during TC. This means that TC will never be active for longer
than one count period and it may, in fact, be shorter if a STEP
command or a LOAD or LOAD-and-ARM command is applied
during TC (see item 2 above). This also means that a counter
that is disarmed or stopped on TC is actually disarmed/
stopped immediately following TC.
This may cause count sequences different from what a user might
expect. Since the counter is always reloaded at the start of TC,
and since it always counts at the end of TC. the counter contents
following TC will differ by one from the reloaded value, irrespective of the operating mode used.
If the reloaded value was 0001 for down counting, 9999 (BCD) for
BCD up counting or FFFF (hex) for binary up counting, the count
at the end of TC will drive the counter into TC again regardless of
whether the counter is gated off or disarmed. As long as these
values are reloaded, the TC output will stay active. I{ a TC Toggled output is selected, it will toggle on each count. Execution of a
LOAD, LOAD-and-ARM or STEP command with these counter
contents will act the same as application of a source pulse,
causing TC to remain active and a TC Toggled output to toggle.
TC OUTPUT
1----,
- - - - - - - '
TCT~~~~~~
______________________
~~f
~f~--------------------J~
Figure 20. Counter Output Waveforms.
7-125
MOS-503
Am9513
Count Control
Counter Mode bits CM3 through CM? specify the various options
available for direct control of the counting process. CM3 and CM4
operate independently of the others and control up/down and
BCD/binary counting. They may be combined freely with other
control bits to form many types of counting configurations. The
other three bits and the Gating Control field interact in complex
ways. Bit CM5 controls the repetition of the count process. When
CM5 = 1, counting will proceed in the specified mode until the
counter is disarmed. When CM5 = 0, the count process will
proceed only until one full cycle of operation occurs. This may
occur after one or two TC events. The counter is then disarmed
automatically. The single or double TC requirement will depend
on the state of other control bits. Note that even if the counter is
automatically disarmed upon a TC, it always counts the count
source edge which generates the trailing TC edge.
of the available inputs are internal frequencies derived from the
internal oscillator (see Figure 16 for frequency assignments). Ten
of the available inputs are interface pins; five are labeled SRC and
five are labeled GATE.
The 16th available input is the TC output from the adjacent
lower-numbered counter. (The Counter 5 Te wraps around to the
Counter 1 input.) This option allows internal concatenating that
permits very long counts to be accumulated. Since all five counters may be concatenated, it is possible to configure a counter that
is 80 bits long on one Am9513 chip. When TCN--1 is the source,
the count ripples between the connected counters. External connections can also be made, and can use the toggle bit for even
longer counts. This is easily accomplished by selecting a TC
Toggled output mode and wiring OUTN to one of the SRC inputs.
Gating Control
Counter Mode bits CM13 through CM15 specify the hardware
gating options. When "no gating" is selected (000) the counter
will proceed unconditionally as long as it is armed. For any other
gating mode, the count process is conditioned by the specified
gating configuration.
When TC occurs, the counter is always reloaded with a value
from either the Load register or the Hold register. Bit CM6
specifies the source options for reloading the counter. When CM6
= 0, the contents of the Load register will be transferred into the
counter at every occurrence of TC. When CM6 = 1, the counter
reload location will be either the Load or Hold Register. The
reload location in this case may be controlled externally by using
a GATE pin (Modes S and V) or may alternate on each TC (Modes
G through L). With alternating sources and with the TC Toggled
output selected, the duty cycle of the output waveform is controlled by the relative Load and Hold values and very fine resolution
of duty cycle ratios may be achieved.
For a code of 100 in this field, counting can proceed only when the
pin labeled GATEN associated with Counter N is at a logic high
level. When it goes low, counting is simply suspended until the
Gate goes high again. A code of 101 performs the same function
with an opposite active polarity. Codes 010 and 011 offer the same
function as 100, but specify alternate input pins as Gating
Sources. This allows any of three interface pins to be used as
gates for a given counter. On Counter 4, for example, pin 34, pin
35 or pin 36 may be used to perform the gating function. This also
allows a single Gate pin to simultaneously control up to three
counters.
Bit CM? controls the special gating functions that allow retriggering and the selection of Load or Hold sources for counter reloading. The use and definition of CM? will depend on the status of the
Gating Control field and bits CM5 and CM6.
For codes of 110 or 111 in this field, counting proceeds after the
specified active Gate edge until one or two TC events occur.
Within this interval the Gate input is ignored, except for the
retriggering option. When repetition is selected, a cycle will be
repeated as soon as another Gate edge occurs. With repetition
selected, any Gate edge applied after TC goes active will start a
new count cycle. Edge gating is useful when implementing a
digital single-shot since the gate can serve as a convenient
firing trigger.
When some form of Gating is specified, CM? controls hardware
retriggering. In this case, when CM? = 0 hardware retriggering
does not occur; when CM? =-~ 1 the counter is retriggered any time
an active-going Gate edge occurs. Retriggering causes the
counter value to be saved in the Hold register and the Load
register contents to be transferred into the counter.
Whenever hardware retriggering is enabled (Modes N, 0, Q and
R) all active going Gate edges initiate retrigger operations. On
application of the Gate edge, the counter contents will be transferred to the Hold register. On the first qualified source edge after
application of the retriggering Gate edge, the Load register contents will be transferred into the counter. (Qualified source edges
are edges which occur while the counter is gated on and Armed.)
A 001 code in this field selects the TC output from the adjacent
lower-numbered counter as the gate. Thus, one counter may be
configured to generate a counting "window" for another counter.
This means that if level gating is used, the edge occurring on
active-going gate transitions will initiate a retrigger. Similarly,
when edge gating is enabled, an edge used to start the counter
will also initiate a retrigger. The first count source edge applied
after the Gate edge will not increment/decrement the counter but
reload it.
COMMAND DESCRIPTIONS
The command set for the Am9513 allows the host processor to
customize and manage the operating modes and features for
particular applications, to initialize and update both the internal
data and control information, and to manipulate operating bits
during operation. Commands are entered directly into the 8-bit
Command register by writing into the Control port (see Figure ?).
When No Gating is specified, the definition of CM? changes. In
this case, when CM? = 0 the Gate input has no effect on the
counting; when CM? = 1 the GATE N input specifies the reload
source (either the Load or Hold register) used to reload the
counter when TC occurs. Figure 1? shows the various available
control combinations for these interrelated bits.
All available commands are described in the following text. Figure
21 summarizes the command codes and includes a brief description of each function. Figure 22 shows all the unused code combinations; unused codes should not be entered into the Command
register since undefined activities may occur.
Count Source Selection
Counter Mode bits CM8 through CM12 specify the source used as
input to the counter and the active edge that is counted. Bit CM12
controls the polarity for all the sources; logic zero counts rising
edges and logic one counts falling edges. Bits CM8 through CM11
select 1 of 16 counting sources to route to the counter input. Five
Six of the command types are used for direct software control of
the counting process and they each contain a 5-bit S field. In a
linear-select fashion, each bit in the S field corresponds to one of
the five general counters (S1 = Counter 1, S2 = Counter 2, etc.).
When an S bit is a one, the specified operation is performed on
the counter so designated; when an S bit is a zero, no operation
?-126
Am9513
Command Code
C7
C6
C5
C4
C3
C2
C1
CO
0
0
0
E2
E1
G4
G2
G1
Load Data Pointer register with contents of E and G fields.
(G 'f 000, G 'f 110)
0
0
S5
S4
S3
S2
S1
Arm counting for all selected counters
0
S5
S4
S3
S2
S1
Load contents of specified source into all selected counters
0
0
0
Command Description
S5
S4
S3
S2
S1
Load and Arm all selected counters
0
S5
S4
S3
S2
S1
Disarm and Save all selected counters
S5
S4
S3
S2
S1
Save all selected counters in hold register
0
S5
S4
S3
S2
S1
Disarm all selected counters
0
0
0
~
~
N4
N2
N1
Set output bit N (001
0
N4
N2
N1
Clear output bit N (001
~
N
~
0
N4
N2
N1
Step counter N (001
~
N
~
101)
0
0
0
Set MM14 (Disable Data Pointer Sequencing)
0
Set MM12 (Gate off FOUT)
0
Clear MM14 (Enable Data Pointer Sequencing)
0
Clear MM12 (Gate on FOUT)
0
0
0
N
101)
101)
Set MM13 (Enter 16-bit bus mode)
0
0
0
0
0
0
0
0
Clear MM13 (Enter 8-bit bus mode)
Master reset
Figure 21. Am9513 Command Summary.
occurs for the corresponding counter. This type of command
format has three basic advantages. It saves host software by
allowing any combination of counters to be acted on by a single
command. It allows simultaneous action on multiple counters
where synchronization of commands is important. It· allows
counter-specific service routines to control individual counters
without needing to be aware of the operating context of other
counters.
each ARM or LOAD-and-ARM command, a counter in one of
these modes will reload from the Hold register on the first TC and
alternate reload sources thereafter (reload from the Load register
on the second TC, the Hold register on the third, etc.).
In edge gating modes (Modes C, F, I, L, 0 and R) after disarming
and rearming a triggered counter, a new Gate edge will be
required to resume counting. In Modes C, F, I and L counting will
resume from the current counter value. In modes 0 and R the
new Gate edge will both start and retrigger the counter, causing
the counter to be reloaded with a new value.
Arm Counters
Coding:
C7
C6
o
0
C5
C4
C3
C2
C1
CO
I
S5
S4
S3
S2
S1
I
Description: Any combination of counters, as specified by the S
field, will be enabled for counting. A counter must be armed
before counting can commence. Once armed, the counting process may be further enabled or disabled using the hardware
gating facilities. This command can only arm or do nothing for a
given counter; a zero in the S field does not disarm the counter.
ARM and DISARM commands can be used to gate counter
operation on and off under software control. DISARM commands
entered while a counter is in the TC state will not take effect until
the counter leaves TC. This ensures that the counter never
latches up in a TC state. (The counter may leave the TC state
because of application of a count source edge; execution of a
LOAD or LOAD-and-ARM command; or execution of a STEP
command.)
Load Counters
Coding:
I C7
I0
C6
C5
0
C4
C3
C2
C1
CO
S5
S4
S3
S2
S1
I
I
Description: Any combination of counters, as specified in the S
field, will be loaded with previously entered values. The source of
information for each counter will be either the associated Load
register or the associated Hold register, as determined by the
operating configuration in the Mode register. The Load/Hold
contents are not changed. This command will cause a transfer
independent of any current operating configuration for the
counter. It will often be used as a software retrigger, or as counter
initialization prior to active hardware gating.
If a LOAD or LOAD-and-ARM command is executed during the
cycle preceding TC, the counter will go immediately to TC. This
occurs because the LOAD operation is performed by generating
a pseudo-count pulse, internal to the Am9513, and the Am9513 is
expecting to go into TC on the next count pulse. The reload
In modes which alternate reload sources (Modes G-L), the
ARMing operation is used as a reset for the logic which determines which reload source to use on the upcoming TC. Following
7-127
Am9513
source used to reload the counter will be the same as that which
would have been used if the TC were generated by a source
edge rather than by the LOAD operation.
Execution of a LOAD or LOAD-and-ARM command while a
counter is in TC will cause the TC to end. For Armed counters in
all modes except S or V, the reload source used will be that to be
used for the upcoming TC. (The LOADing operation will not alter
the selection of reload source for the upcoming TC.) For Disarmed counters in modes except S or V, the reload sources used
will be the LOAD register. For modes S or V, the reload source
will be selected by the GATE input, regardless of whether the
counter is Armed or Disarmed.
Special considerations apply when modes with alternating reload sources are used (Modes G-L). If a LOAD command drives
the counter to TC in these modes, the reload source for the next
TC will be from the opposite reload location. In other words, the
LOAD-generated TC will cause the reload sources to alternate
just as a TC generated by a source edge would. Note that if a
second LOAD command is issued during the LOAD-generated
TC (or during any other TC, for that matter) the second LOAD
command will terminate the TC and cause a reload from the
source designated for use with the next TC. The second LOAD
will not alter the reload source for the next TC since the second
LOAD does not generate a TC; reload sources alternate on TCs
only, not on LOAD commands.
Save Counters
Coding:
C7
C6
C5
o
C4
C3
C2
C1
CO
S5
S4
S3
S2
S1
Description: Any combination of counters, as specified by the S
field, will have their contents transferred into their associated
Hold register. The transfer takes place without interfering with any
counting that may be underway. This command will overwrite any
previous Hold register contents. The SAVE command is designed to allow an accumulated count to be preserved so that it
can be read by the host CPU at some later time.
Disarm and Save Counters
Coding:
C7
C6
C5
C4
C3
C2
C1
CO
o
0
S5
S4
S3
S2
S1
Description: Any combination of counters, as specified by the S
field, will be disarmed and the contents of the counter will be
transferred into the associated Hold registers. This command is
identical to issuing a DISARM command followed by a SAVE
command.
Set Output
Coding:
C7
.C6
C5
C4
C3
o
Load and Arm Counters
Coding:
C7
C6
C4
C3
C2
C1
CO
S5
S4
S3
S2
S1
Description: Any combination of counters, as specified in the S
field, will be first loaded and then armed. This command is
equivalent to issuing a LOAD command and then an ARM
command.
A LOAD-and-ARM command which drives a counter to TC generates the same sequence of operations as execution of a LOAD
command and then an ARM command. In modes which disarm
on TC (Modes A-C and N-O, and Modes G-I and S if the current
TC is the second in the cycle) the ARM part of the LOAD-andARM command will re-enable counting for another cycle. In
modes which alternate reload sources (Modes G-L) the ARMing
operating will cause the next TC to reload from the HOLD register, irrespective of which reload source the current TC used.
1
CO
N4
N2
N1
Description: The output toggle for counter N is set. The OUTN
signal will be 9riven high unless a TC output is specified.
Clear Output
Coding:
C7
C6
C5
C4
C3
C2
C1
CO
o
0
N4
N2
N1
(001 :os; N :os; 101)
Description: The output toggle for counter N is reset. The OUTN
signal will be driven low unless a TC output is specified.
Step Counter
Coding:
C7
C6
C5
C4
C3
C2
C1
CO
o
N4
N2
N1
(001 :os; N:os; 101)
Disarm Counters
C7
C1
(001 :os; N :os; 101)
C5
o
Coding:
C2
C6
C5
C4
C3
C2
C1
CO
0
S5
S4
S3
S2
S1
Description: Any combination of counters, as specified by the S
field, will be disabled from counting. A disarmed counter will
cease all counting independent of other control conditions. The
only exception to this is that a counter in the TC state will always
count once, in order to leave TC, before DISARMing. This count
may be generated by a source edge, by a LOAD or LOAD-andARM command (the LOAD-and-ARM command will negate the
DISARM command) or by a STEP command. A disarmed
counter may be updated using the LOAD command and may be
read using the SAVE command. A count process may be resumed using an ARM command. See the ARM command description for further details.
Desqription: Counter N is incremented or decremented by one,
depending on its operating configuration. If the Counter Mode
register associated with the selected counter has its CM3 bit
cleared to zero, this command will cause the counter to decrement by one. If CM3 is set to a logic high, this command will
increment the counter by one. The STEP command will take
effect even on a disarmed counter.
Load Data Pointer Register
Coding:
C7
C6
C5
C4
C3
C2
C1
CO
o
o
o
E2
E1
G4
G2
G1
(G4, G2, G1 t- 000, t: 110)
Description: Bits in the E and G fields will be transferred into the
corresponding Element and Group fields of ·the Data Pointer
7-128
Am9513
register as shown in Figure 8. The Byte Pointer bit in the Data
Pointer register is set. Transfers into the Data Pointer only
occur for G field values of 001, 010, 011, 100, 101 and 111.
Values of 000 and 110 for G should not be used. See the "Setting
the Data Pointer Register" section of this document for additional
details.
Disable Data Pointer Sequencing
Coding:
I
C7
I
1
C6
C5
C4
C3
C2
C1
CO
000
o
I
I
Description: This command sets Master Mode bit 14 without
affecting other bits in the Master Mode register. MM14 controls
the automatic sequencing of the Data Pointer register. Disabling
the sequencing allows repetitive host processor access to a given
internal location without repetitive updating of the Data Pointer.
MM14 may also be controlled by loading a full word into the
Master Mode register.
Enable Data Pointer Sequencing
Coding:
I C7
I1
C6
C5
C4
C3
C2
000
C1
CO
0
o
I
I
C6
C5
C4
C3
C2
C1
0
CO
1
I
1
C6
C4
1 0
C3
o
C2
C1
1
CO
1
C3
C2
C1
CO
0
0
Gate On FOUT
I C7
I1
Coding:
C6
C5
C4
C3
0
0
C2
C1
CO
0
Description: This command clears Master Mode bit 12 without
affecting other bits in the Master Mode register. MM12 controls
the output status of the FOUT signal. When MM12 is cleared,
FOUT will become active and will drive out the selected and
divided FOUT signal. MM12 may also be controlled by loading the
full Master Mode register in parallel. When FOUT is gated on or
off, a transient pulse may be generated on the FOUT signal.
Master Reset
I C7
I1
I
I
C6
C5
C4
C3
C2
C1
CO
I
1. Using the procedure given in the "Command Initiation" section of this data sheet, enter the FF (hex) command to perform
a software reset.
2. Using the "Command Initiation" procedure, enter the LOAD
command for all counters,opcode SF (hex).
3. Using the procedure given in the "Setting the Data Pointer
Register" section of this data sheet, set the Data Pointer to
a valid code. The legal Data Pointer codes are given in
Figure 9.
The Master Mode, Counter Mode, Load and Hold registers can
now be initialized to the desired values.
C7
C5
1
C4
Description: This command sets Master Mode bit 12 without
affecting other bits in the Master Mode register. MM12 controls
the output state of the FOUT signal. When gated off, the FOUT
line will exhibit a low impedance to ground. MM12 may also be
controlled by loading the full Master Mode register in parallel.
Enable a-Bit Data Bus
I C7
C5
Following either a power-up or software reset, the LOAD command should be applied to all the counters to clear any that may
be in a TC state. The Data Pointer register should also be set to a
legal value, since reset does not initialize it. A complete reset
operation is given in the following.
Description: This command sets Master Mode bit 13 without
affecting other bits in the Master Mode register. MM13 controls
the multiplexer in the data bus buffer. When MM13 is set, no
multiplexing takes place and all 16 external data bus lines are
used to transfer information into and out of the STC. MM13 may
also be controlled by loading the full Master Mode register in
parallel.
Coding:
C6
Description: The Master Reset command duplicates the action
of the power-on reset circuitry. It disarms all counters, enters
0000 in the Master Mode, Load and Hold registers and enters
OBOO (hex) in the Counter Mode registers. \
Enable 16-Bit Data Bus
I C7
I1
I C7
Coding:
Coding:
Description: This command clears Master Mode bit 14 without
affecting other bits in the Master Mode register. MM14 controls
the automatic sequencing of the Data Pointer register. Enabling
the sequencing allows sequential host processor access to several internal locations without repetitive updating of the Data
Pointer. MM14 may also be controlled by loading a full word into
the Master Mode register. See the "Data Pointer Register" section of this document for additional information on Data Pointer
sequencing.
Coding:
Gate Off FOUT
C6
C5
I
I
C4
C3
C2
C1
0
0
0
0
1
0
0
Description: This command clears Master Mode bit 13 without
affecting other bits in the Master Mode register. MM13 controls
the multiplexer in the data bus buffer. When MM13 is cleared, the
multiplexer is enabled and 16-bit internal information is transferred eight bits at a time to the eight low-order external data bus
lines. MM13 may also be controlled by loading the full Master
Mode register in parallel.
1
0
1
0
0
0
X
X
0
0
0
0
X
X
·Unused except when XXX = 111.
Figure 22. Am9513 Unused
7-129
CO
0
0
0
X
X
X
/
commln~ Codes.
Am9513
MAXIMUM RATINGS beyond which useful life may be impaired
Storage Temperature
-55°e to +125°e
Ambient Temperature Under Bias
vee with Respect to VSS
-0.5V to +7.0V
All Signal Voltages with Respect to VSS
-0.5V to + 7.0V
1.5W
Power Dissipation (Package Limitation)
The products described by this specification include internal circuitry designed to protect input devices from damaging accumulations of
static charge. It is suggested, nevertheless, that conventional precautions be observed during storage, handling and use in order to avoid
exposure to excessive voltages.
OPERATING RANGE
Part Number
Temperature
VCC
Am9513DC
+5V ±5%
Am9513DM
+5V ±5%
VSS
ELECTRICAL CHARACTERISTICS over operating range (Notes 1 and 2)
Parameter
Description
VIL
Input Low Voltage
VIH
Input High Voltage
c----
Test Conditions
Min
Typ
Max
All Inputs Except X2
VSS-0.5
0.8
X2 Input
VSS-0.5
0.8
All Inputs Except X2
2.0
VCC
X2 Input
3.4
VCC
0.2
Units
Volts
Volts
Volts
VITH·
Input Hysteresis (SRC and GATE Inputs Only)
VOL
Output Low Voltage
VOH
Output High Voltage
IIX
Input Load Current (Except X2)
VSS"';; VIN",;; VCC
±10
J.LA
IOZ
Output Leakage Current (Except X1)
VSS ",;; VOUT ",;; VCC
High Impedance State
±25
J.LA
ICC
VCC Supply Current
IOL
= 3.2mA
IOH
= -200J.LA
= -1.5mA
IOH
= -55°C
= O°C
TA = +25°C
0.3
0.4
2.4
Volts
1.5
275
TA
225
TA
mA
160
CIN
Input Capacitance
f = 1MHz, TA = +25°C,
10
COUT
Output Capacitance
15
CIO
IN/OUT Capacitance
All pins not under
test at OV.
7-130
Volts
20
pF
Am9513
ENABLED
COUNT
SOURCE
(NOTE 10)
GATE INPUT
(NOTE 13)
-------+--------+----------------------------'
cs
(NOTE 15)
c/i)
IN~~~~ -------+'HI
OUT
Figure 23. Bus Transfer Switching Waveforms.
MOS-le3
~------------TEHEH------------~
ENABLED
COUNT
SOURCE
(NOTE 10) - - - - - '
TEHEL
TGVEH
(NOTE 12)
GATE
(NOTE 13)
______
I-----+-- TEHGV
~------------------J
FOUT
~I-.----------TEHYV--------~~:l I
OUT_------1~'---~~
-t },,---------,!
__
~
TCHCH
(NOTE
_
\---------11
\
TCHCL
FN_~_~_-_fTFN(~~E14)----II
FN"
\---
5(
Figure 24. Counter Switching Waveforms.
7-131
MOS-184
Am9513
SWITCHING CHARACTERISTICS over operating range (Notes 2, 3, 4)
Am9513
Parameter
Description
Figure
Min
Max
Min
Max
Units
TAVRL
c/o
Valid to Read Low
23
25
ns
TAVWH
C/O Valid to Write High
23
170
ns
TCHCH
X2 High to X2 High (X2 Period)
24
145
ns
TCHCL
X2 High to X2 Low (X2 High Pulse Width)
24
70
ns
TCLCH
X2 Low to X2 High (X2 Low Pulse Width)
24
70
ns
TDVWH
Data In Valid to Write High
23
80
ns
TEHEH
Count Source High to Count Source High (Source Cycle Time) (Note 10)
24
145
ns
TEHEL
TELEH
Count Source Pulse Duration (Note 10)
24
70
ns
TEHFV
Count Source High to FOUT Valid (Note 10)
24
TEHGV
Count Source High to Gate Valid (Level Gating Hold Time)
(Notes 10, 12, 13)
24
40
ns
ns
500
TEHRL
Count Source High to Read Low (Set-up Time) (Notes 5, 10)
23
190
TEHWH
Count Source High to Write High (Set-up Time) (Notes 6, 10)
23
100
TEHYV
Count Source High to Out Valid (Note 10)
ns
TC Output
24
300
Immediate or Delayed Toggle Output
24
300
Comparator Output
24
350
75
TFN
FN High to FN+1 Valid (Note 14)
24
TGVEH
Gate Valid to Count Source High (Level Gating Set-up Time)
(Notes 10, 12, 13)
24
70
ns
ns
ns
ns
TGVGV
Gate Valid to GateValid (Gate Pulse Duration) (Notes 11,13)
24
145
ns
TGVWH
Gate Valid to Write High (Notes 6, 13)
23
0
ns
TRHAX
Read High to C/O Don't Care
23
0
ns
TRHEH
Read High to Count Source High (Notes 7, 10)
23
0
ns
TRHQX
Read High to Data Out Invalid
23
20
ns
TRHQZ
Read High to Data Out at High Impedance
(Data Bus Release Time)
23
85
1000
ns
ns
TRHRL
Read High to Read Low (Read Recovery Time)
23
TRHSH
Read High to CS High (Note 15)
23
TRHWL
Read High to Write Low (Read Recovery Time)
23
1000
ns
23
160
ns
ns
0
TRLQV
Read Low to Data Out Valid
TRLQX
Read Low to Data Bus Driven (Data Bus Drive Time)
23
20
ns
TRLRH
Read Low to Read High (Read Pulse Duration) (Note 15)
23
160
ns
TSLRL
CS Low to Read Low (Note 15)
23
20
ns
TSLWH
CS Low to Write High (Note 15)
23
170
ns
TWHAX
Write High to C/O Don't Care
23
0
ns
TWHDX
Write High to Data In Don't Care
23
0
ns
TWHEH
Write High to Count Source High (Notes 8, 10, 17)
23
400
ns
TWHGV
Write High to Gate Valid (Notes 8, 13, 17)
23
400
TWHRL
Write High to Read Low (Write Recovery Time)
23
TWHSH
Write High to CS High (Note 15)
23
ns
1000
ns
ns
0
TWHWL
Write High to Write Low (Write Recovery Time)
23
1000
ns
TWHYV
Write High to Out Valid (Note 9,17)
23
650
ns
TWLWH
Write Low to Write High (Write Pulse Duration) (Note 15)
23
7-132
150
ns
Am9513
NOTES:
1. Typical values are for TA = 25°C, nominal supply voltage
and nominal processing parameters.
2. Test conditions assume transition times of 10ns or less,
timing reference levels of O.SV and 2.0V and output loading
of one TTL gate plus 100pF, unless otherwise noted.
3. Abbreviations used for the switching parameter symbols are
given as the letter T followed by four or five characters. The
first and third characters represent the signal names on
which the measurements start and end. Signal abbreviations used are:
A (Address) = C/D
C (Clock) = X2
D (Data In) = D80-D815
E (Enabled counter source input)
SRC1-SRC5,
GATE1-GATE5, F1-F5, TCN-1
F = FOUT
G (Counter gate input) = GATE1-GATE5, TCN-1
Q (Data Out) = D80-D815
R (Read) = RD
S (Chip Select) = CS
W (Write) = WR
Y (Output) = OUT1-0UT5
The second and fourth letters designate the reference
states of the signals named in the first and third letters
respectively, using the following abbreviations.
H =
L =
V=
X=
Z =
High
Low
Valid
unknown or don't care
high impedance
4. Switching parameters are listed in alphabetical order.
5. Any input transition that occurs before this minimum setup
requirement will be reflected in the contents read from the
status register.
6. Any input transition that occurs before this minimum setup
requirement will act on the counter before the execution of
the operation initiated by the write. Failure to meet this setup
time when issuing commands to the counter may result in
incorrect counter operation.
7. Any input transition that occurs after this minimum hold time
is guaranteed to not influence the contents read from the
status register on the current read operation.
S. Any input transition that occurs after this minimum hold time
is guaranteed to be seen by the counter as occurring after the
action initiated by the write operation. Failure to meet this
hold time when issuing commands to the counter may result
in incorrect counter operation.
9. This parameter applies to cases where the write operation
causes a change in the output bit.
10. The enabled count source is one of F1-F5, TCN-1,
SRC1-SRC5 or GATE1-GATE5, as selected in the applicable Counter Mode register. The timing diagram assumes
the counter counts on rising source edges. The timing specifications are the same for falling-edge counting.
11. This parameter applies to edge gating (CM15-CM13 = 110
or 111) and gating when both CM7 = 1 and CM15-CM13 =f
000. This parameter represents the minimum GATE pulse
width needed to ensure that the pulse initiates counting or
count~r reloading.
12. This parameter applies to both edge and level gating
(CM15-CM13 = 001 through 111) and gating when both CM7
= 1 and CM15-CM13 = 000. This parameter represents the
minimum setup or hold times to ensure that the Gate input is
seen at the intended level on the active source edge. Failure
to met the required setup and hold times may result in
incorrect counter operation.
13. This parameter assumes that the GATENA input is unused
(16-bit bus mode) or is tied high. In cases where the
GATENA input is used, this timing specification must be met
by both the GATE and GATENA inputs.
14. Signals F1-F5 cannot be directly monitored by the user. The
phase difference between these signals will manifest itself
by causing counters using two different F signals to count at
different times on nominally simultaneous transitions in the
F signals.
15. This timing specification assumes that CS is active
whenever RD or WR are active. CS may be held active
indefinitely.
16. This parameter assumes X2 is driven from an external gate
with a square wave.
17. This parameter assumes that the write operation is to the
command register.
7-133
Am9513
APPLICATION INFORMATION
Following either type of Reset, all five counters are disabled
0800 is loaded into each Counter Mode register, and 0000 i~
loaded in the Master Mode register. This results in each counter
being configured to count down in binary on the positive-going
edge of the internal F1 frequency source with no repetition or
gating. The Master Mode register is cleared to configure the
Am9513 for an 8-bit data bus width; binary division of the internal
oscillator; FOUT gated on and set to divide F1 by 16; time-of-day
mode and comparators 1 and 2 disabled: and the Data Pointer
increment enabled.
The X1 and X2 inputs can be driven with a RC network, an
external TTL-level square wave, or a crystal. Figure 25 shows
the suggested methods of connecting different frequency
sources to the internal oscillator input.
The use of a crystal provides a highly accurate frequency source
at moderate cost, and accordingly, will usually be the preferred
method of operation. The Am9513 is designed to use a crystal in a
parallel-resonant mode. The two ceramic capacitors connecting
X1 and X2 to ground ensure proper loading on the crystal. The
capacitor to X2 may be an adjustable type for fine-tuning the
resonant frequency f, : critical applications.
Reset will clear the Load and Hold registers for each counter but
will not chan98 either the counter contents or the Data Pointer
register. Following a reset, the "Load All Counters" command
(opcode 5F hex) should be issued to clear any counters that may
be at TC. The Master Mode and Counter Mode, Load and Hold
registers may now be set.
An RC network provides a very low cost frequency source but
may exhibit large frequency variations over recommended
power supply and temperature ranges. Note that there is a resistor internal to the Am9513 in parallel 'vvith any external
resistance.
The following initialization procedure should be followed on
Counters 1 and 2 when Time-of-Day mode is selected.
Initialization Procedures
1. Set Time-ot-Day enabled in the Master Mode register and load
Counter Mode registers 1 and 2.
2. If Time-of-Day is to count up, load 0000 in Load registers 1 and
2 and execute command FF43 (Load) to load this value into
the counters. This step conditions the count circuitry.
3. Load the desired start time into the Load registers and execute
command FF43 again.
4. For counting up, load Load registers 1 and 2 with 0000.
5. Counters 1 and 2 may now be armed.
The reset function in the Am9513 is accomplished in two
ways: automatically during power-up and by software Master
Reset command. Power-up reset circuitry is internally triggered
by the rising VCC voltage when a predetermined threshold is
reached. An internal flip-flop is set by the rising supply voltage
and controls the reset operation. The reset flip-flop remains set
until cleared by the first active Chip Select input. A reset may also
by initiated by the host processor by entering the Master Reset
command. This software reset is active for the duration of the
command write; otherwise it performs the same function as the
power-up reset.
(NO
CONNECTION)
Xl
Am9513
Am95l3
Am95l3
+5V
R
Rin!
'----15-60pF
ADJUSTABLE
CERAMIC
MOS·18S
Figure 25. Driving the X1 and X2 Inputs.
Metallization and Pad Layout
OUT 2 2 _ _ _ _
~(+5V),VC,C_;=~~=~
I
OUT 1
GATE 1
OUT 3
GATE 2
OUT'
OUT5
GATE 3
GATE 4
Xl
GATE 5
FOUT
SOURCE 1
SOURCE 2
CID
WR
SOURCE 3
SOURCE'
SOURCES
DBO
12--..
081
OB2
0813
083
084
DB11/GATE4A
~~~~:;DB12/GATE5A
DB10/GATE3A
OB5
086
OB7
U
22 OB9jGATE 2A
21
VSS(GNO)
GATE1A/081
DIE SIZE 0.185"
7-134
x 0.226"
Am9517A
Multimode DMA Controller
DISTINCTIVE CHARACTERISTICS
GENERAL DESCRIPTION
•
The Am9517 A Multimode Direct Memory Access (DMA) Controller is a peripheral interface circuit for microprocessor systems. It is designed to improve system performance by allowing
external devices to directly transfer information to or from the
system memory. Memory-to-memory transfer capability is also
provided. The Am9517A offers a wide variety of programmable
control features to enhance data throughput and system optimization and to allow dynamic reconfiguration under program
control.
Four independent DMA channels, each with separate registers for Mode Control, Current Address, Base Address,
Current Word Count and Base Word Count.
• Transfer modes: Block, Demand, Single Word, Cascade
• Independent autoinitialization of all channels
• Memory-to-memory transfers
• Memory block initialization
• Address increment or decrement
• Master system disable
• Enable/disable control of individual DMA requests
o Directly expandable to any number of channels
• End of Process input for terminating transfers
• Software DMA requests
• Independent polarity control for DR EQ and DACK signals
• Compressed timing option speeds transfers - up to 2M
words/second
• +5 volt power supply
• Advanced N-channel silicon gate MOS technology
• 40 pin Hermetic DIP package
• 100% M I L-STD-883 reliability assurance testing
The Am9517 A is designed to be used in conjunction with an external 8-bit address register such as the Am74LS373. It contains four independent channels and may be expanded to any
number of channels by cascading additional controller chips.
The three basic transfer modes allow programmability of the
types of DMA service by the user. Each channel can be individually programmed to Autoinitialize to its original condition
following an End of Process (EOP).
Each channel has a full 64K address and word count capability.
An external EOP signal can termjnate a DMA or memory-tomemory transfer. This is useful for block search or compare
operations using external comparators or for intelligent peripherals to abort erroneous services.
BLOCK DIAGRAM
EOP
DECREMENTOR
INC/DECREMENTOR
TEMP WORD
COUNT REG (16)
TEMP ADDRESS
REG (16)
RESET
16 BIT BUS
16 BIT BUS
cs
READY
CLOCK
AEN
TIMING
AND
CONTROL
READ BUFFER
READ/WRITE BUFFER
ADSTB
MEMR
MEMW
COMMAND
CONTROL
fOR
lOW
HACK
HREQ
DACKO-DACK3
MOS-033
ORDERING INFORMATION
Package
Type
Hermetic DIP/
Molded DIP
Maximum Clock Frequency
Ambient Temperature
3MHz
AM9517ADC/PC
AM9517A-1 DC/PC
Hermetic DIP
7-135
4MHz
AM9517A-4DC/PC
Am9517A
CONNECTION DIAGRAM
lOR
lOW
MEMR
MEMW
(NOTE 11)
READY
HACK
ADSTB
AEN
HREQ
CS
ClK
RESET
DACK2
DACK3
DREQ3
DREQ2
DREQl
DREQO
(GND) VSS
Top View
Pin 1 is marked for orientation.
Figure 1.
MOS-034
INTERFACE SIGNAL DESCRIPTION
VCC: +5 Volt Supply
VSS: Ground
ClK (Clock, Input)
This input controls the internal operations of the Am9517A and
its rate of data transfers. The input may be driven at up to 3MHz
for the standard Am9517A and up to 4MHz for the Am9517A-4.
CS (Chip Select, Input)
Chip Select is an active low input used to select the Am9517 A as
an I/O device during an I/O Read or I/O Write by the host CPU.
This allows CPU communication on the data bus. During multiple transfers to or from the Am9517A by the host CPU, CS may
be held low providing lOR or lOW is toggled following each
transfer.
RESET (Reset, Input)
Reset is an asynchronous active high input which clears the
Command, Status, Request and Temporary registers. It also
clears the first/last flip/flop and sets the Mask register. Following
a Reset the device is in the Idle cycle.
READY (Ready, Input)
Ready is an input used to extend the memory read and write
pulses from the Am9517A to accommodate slow memories or
I/O peripheral devices.
HACK (Hold Acknowledge, Input)
The active high Hold Acknowledge from the CPU indicates that
control of the system buses has been relinquished.
DREQD-DREQ3 (DMA Request, Input)
The DMA Request lines are individual asynchronous channel
request inputs used by peripheral circuits to obtain DMA service.
In Fixed Priority, DREQO has the highest priority and DREQ3
has the lowest priority. Polarity of DREQ is programmable.
Reset initializes these lines to active high.
DBD-DB7 (Data Bus, Input/Output)
The Data Bus lines are bidirectional three-state signals connected to the system data bus. The outputs are enabled during
the I/O Read by the host CPU, permitting the CPU to examine
the contents of an Address register, the Status register, the
Temporary register or a Word Count register. The Data Bus is
enabled to input data during a host CPU I/O write, allowing the
CPU to program the Am9517A control registers. During DMA
cycles the most significant eight bits of the address are output
onto the data bus to be strobed into an external latch by ADSTB.
In memory-to-memory operations data from the source memory
location comes into the Am9517A's Temporary register on the
read-from-memory half of the operation. On the write-to-memory
half of the operation, the data bus outputs the Temporary register data into the destination memory location.
lOR (I/O Read, Input/Output)
I/O Read is a bidirectional active low three-state line. In the Idle
cycle, it is an input control Signal used by the CPU to read the
control registers. In the Active cycle, it is an output control signal
used by the Am9517A to access data from a peripheral during a
DMA Write transfer.
lOW (I/O Write, Input/Output)
I/O Write is a bidirectional active low three-state line. In the Idle
cycle it is an input control signal used by the CPU to load information into the Am9517A. In the Active cycle it is an output
control signal used by the Am9517A to load data to the
peripheral during a DMA Read transfer.
Write operations by the CPU to the Am9517A require a rising
WR edge following each data byte transfer. It is not sufficient to
hold the lOW pin low and toggle CS.
EOP (End of Process, Input/Output)
EOP is an active low bidirectional open-drain signal providing
information concerning the completion of DMA service. When a
channel's Word Count goes to zero, the Am9517A pulses EOP
low to provide the peripheral with a completion signal. EOP may
also be pulled low by the peripheral to cause premature completion. The reception of EOP, either internal or external, causes the
currently active channel to terminate the service, to set its TC bit
in the Status register and to reset its request bit. If Autoinitialization is selected for the channel, the current registers will be
updated from the base registers. Otherwise the channel'S mask
bit will be set and the register contents will remain unaltered.
7-136
Am9517A
During memory-to-memory transfers, EOP will be output when
the TC for channel 1 occurs. EOP always applies to the channel
with an active DACK; external EOP8 are disregarded in
DACKO-DACK3 are all inactive.
Because EOP is an open-drain signal, an external pullup resistor is required. Values of 3.3K or 4.7K are recommended; the
EOP pin can not sink the current passed by a 1K pullup.
AO-A3 (Address, Input/Output)
The four least significant address lines are bidirectional 3-state
signals. During DMA Idle cycles they are inputs and allow the
host CPU to load or read control registers. When the DMA is
active, they are outputs and provide the lower 4-bits of the output address.
A4-A7 (Address, Output)
The four most significant address lines are three-state outputs
and provide four bits of address. These lines are enabled only
during DMA service.
HREQ (Hold Request, Output)
The Hold Request to the CPU is used by the DMA to request
control of the system bus. 80ftware requests or unmasked
DREOs cause the Am9517A to issue HREO.
DACKO-DACK3 (DMA Acknowledge, Output)
The DMA Acknowledge lines indicate that a channel is active. In
many systems they will be used to select a peripheral. Only one
DACK will be active at a time and none will be active unless the
DMA is in control of the bus. The polarity of these lines is programmable. Reset initializes them to active-low.
AEN (Address Enable, Output) .
Address Enable is an active high signal used to disable the
system bus during DMA cycles to enable the output of the external latch which holds the upper byte of the address. Note that
during DMA transfers HACK and AEN should be used to deselect all other I/O peripherals which may erroneously be accessed as programmed I/O during the DMA operation. The
Am9517A automatically deselects itself by disabling the C8
input during DMA transfers.
ADSTB (Address Strobe, Output)
The active high Address 8trobe is used to strobe the upper
address byte from DBO-DB7 into an external latch.
MEMR (Memory Read, Output)
The Memory Read Signal is an active low three-state output
used to access data from the selected memory location during a
memory-to-peripheral or a memory-to-memory transfer.
Name
Size
Number
Base Address Registers
Base Word Count Registers
Current Address Registers
Current Word Count Registers
Temporary Address Register
Temporary Word Count Register
Status Register
Command Register
Temporary Register
Mode Registers
Mask Register
Request Register
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
S bits
S bits
S bits
6 bits
4 bits
4 bits
4
4
4
4
1
1
1
1
1
4
1
1
Figure 2. Am9S17A Internal Registers.
MEMW (Memory Write, Output)
The Memory Write signal is an active low three-state output
used to write data to the selected memory location during a
peripheral-to-memory or a memory-to-memory transfer.
FUNCTIONAL DESCRIPTION
The Am9517A block diagram includes the major logic blocks and
all of the internal registers. The data interconnection paths are
also shown. Not shown are the various control signals between
the blocks. The Am9517A contains 344 bits of internal memory
in the form of registers. Figure 2 lists these registers by name
and shows the size of each. A detailed description of the registers and their functions can be found under Register Description.
The Am9517A contains three basic blocks of control logic. The
Timing Control block generates internal timing and external
control signals for the Am9517A. The Program Command Control block decodes the various commands given to the Am9517A
by the microprocessor prior to servicing a DMA Request. It also
decodes each channel's Mode Control word. The Priority Encoder block resolves priority contention among DMA channels
requesting service simultaneously.
The Timing Control block derives internal timing from the clock
input. In Am90S0A systems this input will usually be the cf>2 TTL
clock from an AmS224. However, any appropriate system clock
will suffice.
DMA Operation
The Am9517A is designed to operate in two major cycles. These
are called Idle and Active cycles. Each device cycle is made up
of a number of states. The Am9517A can assume seven separate states, each composed of one full clock period. 8tate 1 (81)
is the inactive state. It is entered when the Am9517A has no
valid DMA requests pending. While in 81, the DMA controller is
inactive but may be in the Program Condition, being programmed by the processor. 8tate 0 (80) is the first state of a DMA
service. The Am9517A has requested a hold but the processor
has not yet returned an acknowledge. An acknowledge from the
CPU will signal that transfers may begin. 81,82,83 and 84 are
the working states of the DMA service. If more time is needed to
complete a transfer than is available with normal timing, wait
states (8W) can be inserted before 84 by the use of the Ready
line on the Am9517A.
Memory-to-memory transfers require a read-from and a
write-to-memory to complete each transfer. The states, which
resemble the normal working states, use two digit numbers for
identification. Eight states are required for each complete
transfer. The first four states (811, 812, 813, 814) are used for
the read-from-memory half and the last four states (821, 822,
823 and 824) for the write-to-memory half of the transfer. The
Temporary Data register is used for intermediate storage of the
memory byte.
IDLE Cycle
When no channel is requesting service, the Am9517A will enter
the Idle cycle and perform "81" states. In this cycle the'
Am9517A will sample the DREO lines every clock cycle to de
termine if any channel is requesting a DMA service. The devie'
will also sample C8, looking for an attempt by the microproc(
sor to write or read the internal registers of the Am9517A. WI'
C8 is low and HACK is low the Am9517A enters the Proc'
Condition. The CPU can now establish, change or inspe.'
internal definition of the part by 'reading from or writing
internal registers. Address lines AO-A3 are inputs to thf
and select which registers will be read or written. The.;
lOW lines are used to select and time reads or writes. r
7-137
Am9S17A
number and size of the internal registers, an internal flip/flop is
used to generate an additional bit of address. This bit is used to
determine the upper or lower byte of the 16-bit Address and
Word Count registers. The flip/flop is reset by Master Clear or
Reset. A separate software command can also reset this flip/
flop.
Special software commands can be executed by the Am9517A
in the Program Condition. These commands are decoded as
sets of addresses when both CS and lOW are active and do not
make use of the data bus. Functions include Clear First/Last
Flip/Flop and Master Clear.
signals of its own. These would conflict with the outputs of the
active channel in the added device. The Am9517A will respond
to DREQ with DACK but all other outputs except HREQ will be
disabled.
Figure 3 shows two additional devices cascaded into an initial
device using two of the previous channels. This forms a two
level DMA system. More Am9517As could be added at the second level by using the remaining channels of the first level.
Additional devices can also be added by cascading into the
channels of the second level devices forming a third level.
2ND LEVEL
ACTIVE CYCLE
When the Am9517A is in the Idle cycle and a channel requests a
DiviA service, the device will output a HREQ to the microprocessor and enter the Active cycle. It is in this cycle that the DMA
service will take place, in one of four modes:
HOLD REO
Block Transfer Mode: In Block Transfer mode, the Am9517A
will continue making transfers until a TC (caused by the word
count going to zero) or an external End of Process (EOP) is
encountered. DREQ need be held active only until DACK becomes active. An autoinitialize will occur at the end of the service if the channel has been programmed for it.
Demand Transfer Mode: In Demand Transfer mode the device will continue making transfers until a TC or external EOP is
encountered or until DREQ goes inactive. Thus, the device requesting service may discontinue transfers by bringing DREQ
inc!ctive. Service may be resumed by asserting an active DREQ
once again. During the time between services when the micro,rocessor is allowed to operate, the intermediate values of ad'ss and word count may be read from the Am9517A Current
"'!ss and Current Word Count registers. Autoinitialization will
,ur following a TC or EOP at the end of service. Follow'itialization, an active-going DREQ edge is required to
v DMA service.
This mode is used to cascade more than one
. for simple system expansion. The HREQ and
the additional Am9517A are connected to
I.( signals of a channel of the initial
DMA requests of the additional device
'riority network circuitry of the pre1in is preserved and the new de"nowledge requests. Since the
ice is used only for prioritizing
.0t output any address or control
HREO
DREO
HREO
HACK
DACK
HACK
HOLD ACK
Single Transfer Mode: In Single Transfer mode, the Am9517A
will make a one-byte transfer during each HREQ/HACK handshake. When DREQ goes active, HREQ will go active. After the
CPU responds by driving HACK active, a one-byte transfer will
take place. Following the transfer, HREQ will go inactive, the
word count will be decremented and the address will be either
incremented or decremented. When the word count goes to zero
a Terminal Count (TC) will cause an Autoinitialize if the channel
has been programmed to do so.
To perform a single transfer, DREQ must be held active only
until the corresponding DACK goes active. If DREQ is held continuously active, HREQ will go inactive following each transfer
and then will go active again and a new one-byte transfer will be
made following each rising edge of HACK. In 8080N9080A
systems this will ensure one full machine cycle of execution
between DMA transfers. Details of timing between the Am9517A
and other bus control protocols will depend upon the characteristics of the microprocessor involved.
Am9517A
1ST LEVEL
MICROPROCESSOR
Am9517A
DR EO
HREO
DACK
HACK
INITIAL DEVICE
Am9517A
ADDITIONAL
DEVICES
MOS-035
Figure 3. Cascaded Am9S17As.
TRANSFER TYPES
Each of the three active transfer modes can perform three different types of transfers. These are Read, Write and Verify.
Write transfers move data from an I/O device to the memory by
activating lOR and MEMW. Read transfers move data from
memory to an I/O device by activating MEMR and lOW. Verify
transfers are pseudo transfers; the Am9517A operates as in
Read or Write transfers generating addresses, responding to
EOP, etc., however, the memory and I/O control lines remain
inactive.
Memory-te-Memory: The Am9517A includes a block move
capability that allows blocks of data to be moved from one memory address space to another. When Bit CO in the Command
register is set to a logical 1, channels 0 and 1 will operate as
memory-to-memory transfer channels. Channel 0 forms the
source address and channel 1 forms the destination address.
The channel 1 word count is used. A memory-to-memory transfer is initiatecj by setting a software DMA request for channel O.
Block Transfer Mode should be used for memory-to-memory.
When channel 0 is programmed for a fixed source address, a
single source word may be written into a block of memory.
When setting up the Am9517A for memory-to-memory operation, it is suggested that both channels 0 and 1 be masked out.
Further, the channel 0 word count should be initialized to the
same value used in channel 1. No DACK outputs will be active
during memory-to-memory transfers.
The Am9517A will respond to external EOP signals during
memory-to-memory transfers. Data comparators in block search
schemes may use this input to terminate the service when a
match is found. The timing of memory-to-memory transfers may
be found in Timing Diagram 4.
7-138
Am9517A
Autointialize: By programming a bit in the Mode register a
channel may be set up for an Autoinitialize operation. During
Autoinitialization, the original values of the Current Address and
Current Word Count registers are automatically restored from
the Base Address and Base Word Count registers of that channel following EOP. The base registers are loaded simultaneously with the current registers by the microprocessor and remain unchanged throughout the DMA service. The mask bit is
not set by EOP when the channel is in Autoinitialize. Following
Autoinitialize the channel is ready to repeat its service without
CPU intervention.
Priority: The Am9517A has two types of priority encoding
available as software selectable options. The first is Fixed Priority which fixes the channels in priority order based upon the
descending value of their number. The channel with the lowest
priority is 3 followed by 2, 1 and the highest priority channel, O.
The second scheme is Rotating Priority. The last channel to get
service becomes the lowest priority channel with the others
rotating accordingly. With Rotating Priority in a single chip DMA
system, any device requesting service is guaranteed to be recognized after no more than three higher priority services have
occurred. This prevents anyone channel from monopolizing the
system.
1st Service
highest
o
lowest
3
2nd Service
3rd Service
2 _ _ service~3 - - - service
1 - - service~ 3 - - request
0
2
,0
1
1
2
The priority encoder selects the highest priority channel requesting service on each active-going HACK edge. Once a
channel is started, its operation will not be suspended if a request is received by a higher priority channel. The high priority
channel will only gain control after the lower priority channel
releases HREQ. When control is passed from one channel to
another, the CPU will always gain bus control. This ensures
generation of riSing HACK edge to be used to initiate selection of
the new highest-priority requesting channel.
Compressed Timing: In order to achieve even greater
throughput where system characteristics permit, the Am9517A
can compress the transfer time to two clock cycles. From Timing
Diagram 3 it can be seen that state 83 is used to extend the
access time of the read pulse. By removing state 83 the read
pulse width is made equal to the write pulse width and a transfer
consists only of state 82 to change the address and state 84 to
perform the read/write. 81 states will still occur when A8-A 15
need updating (see Address Generation). Timing for compressed transfers is found in Timing Diagram 6.
Address Generation: In order to reduce pin count, the
Am9517A multiplexes the eight higher order address bits on the
data lines. 8tate 81 is used to output the higher order address
bits to an external latch from which they may be placed on the
address bus. The falling edge of Address 8trobe (AD8TB) is
used to load these bits from the data lines to the latch. Address
Enable (AEN) is used to enable the bits onto the address bus
through a 3-state enable. The lower order address bits are output by the Am9517A directly. Lines AO-A7 should be connected
to the address bus. Timing Diagram 3 shows the time relationships between ClK, AEN, AD8TB, DBO-DB7 and AO-A7.
During Block and Demand Transfer mode services which include multiple transfers, the addresses generated will be sequential. For many transfers the data held in the external address latch will remain the same. This data need only change
when a carry or borrow from· A7 to A8 takes place in the normal
sequence of addresses. To save time and speed transfers, the
Am9517A executes 81 states only when updating of A8-A15 in
the latch is necessary. This means for long services, 81 states
may occur only once every 256 transfers, a savings of 255 clock
cycles for each 256 transfers.
REGISTER DESCRIPTION
Current Address Register: Each channel has a 16-bit Current
Address register. This register holds the value of the address
used during DMA transfers. The address is automatically incremented or decremented after each transfer and the intermediate values of the address are stored in the Current Address
register during the transfer. This register is written or read by the
microprocessor in successive 8-bit bytes. It may also be
reinitialized by an Autoinitialize back to its original value. Autoinitialization takes place only after an EOP.
Current Word Count Register: Each channel has a 16-bit Current Word Count register. This register should be programmed
with, and will return on a CPU read, a value one less than the
number of words to be transferred. The word count is decremented after each transfer. The intermediate value of the word
count is stored in the register during the transfer. When the
value in the register goes to zero, a TC will be generated. This
register is loaded or read in successive 8-bit bytes by the microprocessor in the Program Condition. Following the end of a DMA
service it may also be reinitialized by an Autoinitialize back to its
original value. Autoinitialize can occur only when an EOP occurs. Note that the contents of the Word Count register will be
FFFF (hex) following on internally generated EOP.
Base Address and Base Word Count Registers: Each channel has a pair of Base Address and Base Word Count registers.
These 16-bit registers store the original values of their associated current registers. During Autoinitialize these values are
used to restore the current registers to their original values. The
base registers are written simultaneously with their corresponding current register in 8-bit bytes during DMA programming by
the microprocessor. Accordingly, writing to these registers when
intermediate values are in the Current registers will overwrite the
intermediate values. The Base registers cannot be read by the
microprocessor.
7-139
Am9S17A
Command Register: This a-bit register controls the operation
of the Am9517A. It is programmed by the microprocessor in the
Program Condition and is cleared by Reset. The following table
lists the function of the command bits. See Figure 4 for address
coding.
7
6
5
o - - Bit Number
432
Request Register: The Am9517A can respond to requests for
DMA service which are initiated by software as well as by a
DREO. Each channel has a request bit associated with it in the
4-bit Request register. These are nonmaskable and subject to
prioritization by the Priority Encoder network. Each register bit is
set or reset separately under software control or is cleared upon
generation of a TC or external EOP. The entire register is
cleared by a Reset. To set or reset a bit, the software loads the
proper form of the data word. See Figure 4 for address coding.
o Memory·to-memory disable
1 Memory-to-memory enable
6
5
4
3
2
o - - Bit Number
o
Channel 0 address hold disable
Channel 0 address hold enable
X If bit 0 = 0
o
Select channel
Select channel
Select channel
Select channel
Controller enable
Controller disable
o
0 Normal timing
Compressed timing
X If bit 0 = 1
0 Fixed Priority
Rotating Priority
0 Late write selection
Extended write selection
X If bit 3 = 1
0 DREQ sense active high
DREQ sense active low
0 DACK sense active low
DACK sense active high
0
1
2
3
Reset request bit
Set request bit'
Software requests will be serviced only if the channel is in Block
mode. When initiating a memory-to-memory transfer, the
software request for channel 0 should be set.
Mask Register: Each channel has associated with it a mask bit
which can be set to disable the incoming DREO. Each mask bit
is set when its associated channel produces an EOP if the
channel is not programmed for Autoinitialize. Each bit of the 4-bit
Mask register may also be set or cleared separately under
software control. The entire register is also set by a Reset. This
disables all DMA requests until a clear Mask register instruction
allows them to occur. The instruction to separately set or clear
the mask bits is similar in form to that used with the Request
register. See Figure 4 for instruction addressing.
6
5
4
3
2
o - - Bit Number
Mode Register: Each channel has a 6-bit MOde register associated with it. When the register is being written to by the
microprocessor in the Program Condition, bits 0 and 1 determine which channel Mode register it to be written.
Select channel 0 mask bit
Select channel 1 mask bit
Select channel 2 mask bit
765
4
3
2
o
Select channel 3 mask bit
- - B i t Number
o
Channel
Channel
Channel
Channel
0
1
2
3
select
select
select
select
00 Verify transfer
01 Write transfer
10 Read transfer
11 Illegal
XX If bits 6 and 7 = 11
Clear mask bit
1 Set mask bit
All four bits of the Mask Register may also be written with a
single command.
7
6
5
4
3
2
o - - Bit Number
0 Clear Cha'nnel 0 mask bit
Set Channel 0 mask bit
0 Autoinitialize disable
Autoinitialize enable
0 Clear Channel 1 mask bit
Set Channel 1 mask bit
0 Address increment select
Address decrement select
0 Clear Channel 2 mask bit
Set Channel 2 mask bit
00 Demand mode select
01 Single mode select
10 Block mode select
11 Cascade mode select
0 Clear Channel 3 mask bit
Set Channel 3 mask bit
7-140
Am9517A
Status Register: The Status registers may be read out of the
Am9517A by the microprocessor. It indicates which channels
have reached a terminal count and which channels have pending DMA requests. Bits 0-3 are set each time a TC is reached by
that channel, including after each Autoinitialization. These bits
are cleared by Reset and each Status Read. Bits 4-7 are set
whenever their corresponding channel is requesting service.
7
I
6
I
5
I
4
I
3
I
Software Commands: There are two special software commands which can be executed in the Program Condition. They
do not depend on any specific bit pattern on the data bus. The
two software commands are:
o -- Bit Number
2
I
Temporary Register: The Temporary register is used to hold
data during memory-to-memory transfers. Following the completion of the transfers, the last word moved can be read by the
microprocessor in the Program Condition. The Temporary register always contains the last byte transferred in the previous
memory-to-memory operation, unless cleared by a Reset.
I
I
I
'---
Channel 0 has reached
Channell has reached
Channel 2 has reached
Channel 3 has reached
Clear First/Last Flip/Flop: This command may be issued prior
to writing or reading Am9517A address or word count information. This initializes the flip/flop to a known state so that
subsequent accesses to register contents by the microprocessor will address lower and upper bytes in the correct
sequence.
TC
TC
TC
TC
Master Clear: This software instruction has the same effect
as the hardware Reset. The Command, Status, Request,
Temporary and Internal First/Last Flip/Flop registers are
cleared and the Mask register is set. The Am9517A will enter
the Idle cycle.
Channel 0 request
Channel 1 request
Channel 2 request
Channel 3 request
Figure 4 lists the address codes for the software commands.
Interface Signals
A3
A2
A1
AD
lOR
lOW
1
0
0
0
0
1
Read Status Register
Operation
Write Command Register
1
0
0
0
1
0
1
0
0
1
0
1
Illegal
1
0
0
1
1
0
Write Request Register
1
0
1
0
0
1
Illegal
1
0
1
0
1
0
Write Single Mask Register Bit
1
0
1
1
0
1
Illegal
1
0
1
1
1
0
Write Mode Register
1
1
0
0
0
1
Illegal
1
1
0
0
1
0
Clear Byte Pointer Flip/Flop
1
1
0
1
0
1
Read Temporary Register
1
1
0
1
1
0
Master Clear
1
1
1
0
0
1
Illegal
1
1
1
0
1
0
Illegal
1
1
1
1
0
1
Illegal
1
1
1
1
1
0
Write All Mask Register Bits
Figure 4. Register and Function Addressing.
7-141
6
Am9517A
Channel
a
1
2
3
Operation
Register
Signals
CS lOR lOW A3 A2 Al AD
a
Internal
Flip/Flop
Data Bus
DBa-DB7
Base & Current
Address
Write
a
0
1
1
0
a
0
a
0
a
0
0
0
0
1
AO-A7
A8-A15
Current
Address
Read
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
AO-A7
A8-A15
Base & Current
Word Count
Write
0
1
1
0
0
a
a
0
0
0
a
0
1
1
a
1
WO-W7
W8-W15
Current
Word Count
Read
0
0
1
1
0
a
0
a
0
a
1
1
0
a
1
WO-W7
W8-W15
Base & Current
Address
Write
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
1
AO-A7
A8-A15
Current
Address
Read
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
1
AO-A7
A8-A15
Base & Current
Word Count
Write
0
0
1
1
0
0
0
0
0
0
1
1
1
0
1
WO-W7
1
Current
Word Count
Read
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
1
WO-W7
W8-W15
Base & Current
Address
Write
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
1
AO-A7
A8-A15
Current
Address
Read
0
0
0
a
1
1
0
0
1
1
0
0
0
0
0
1
AO-A7
A8-A15
Base & Current
Word Count
Write
0
0
1
1
0
0
0
0
1
0
0
1
1
0
1
WO-W7
W8-W15
Current
Word Count
Read
0
0
0
1
1
0
0
1
1
a
0
1
1
a
a
1
WO-W7
W8-W15
Base & Current
Address
Write
0
0
1
1
a
0
0
a
1
1
1
1
0
0
0
1
AO-A7
A8-A15
Current
Address
Read
0
0
0
0
1
1
0
0
1
1
1
1
0
0
0
AO-A7
A8-A15
Base & Current
Word Count
0
0
1
1
0
0
D
0
1
1
-I
Write
1
1
0
1
WO-W7
1
Current
Word Count
Read
0
0
0
0
1
1
0
a
1
1
1
1
1
1
0
1
WO-W7
W8-W15
0
1
Figure 5. Word Count and Address Register Command Codes.
7-142
1
W8-W15
W8-W15
Am9517A
MAXIMUM RATINGS above which useful life may be impaired
o
Storage Temperature
-65°e to +150 e
Ambient Temperature Under Bias
-55°e to +125°e
vee with Respect to VSS
-O.5V to +7.0V
All Signal Voltages with Respect to VSS
-O.5V to +7.0V
Power Dissipation (Package Limitation)
1.5W
The products described by this specification include internal circuitry designed to protect input devices from damaging accumulations of
static charge. It is suggested, nevertheless, that conventional precautions be observed during storage, handling and use in order to avoid
exposure to excessive voltages.
OPERATING RANGE
vee
Part Number
Am9517ADC/PC
O°C to +70°C
5.0V ±5%
Am9517A-1DC/PC
O°C to +70°C
5.0V ±5%
Am9517 A-4DC/PC
O°C to +70°C
5.0V ±5%
-55°C to +125°C
5.0V ±10%
Am9517ADM
ELECTRICAL CHARACTERISTICS over operating range (Note 1)
Parameter
Description
Test Conditions
= -2001JA
10H = -100pA.
10L = 3.2mA
Min
10H
Typ
Max
2.4
Unit
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
0.4
Volts
VIH
Input HIGH Voltage
2.0
VCC+0.5
Volts
VIL
Input LOW Voltage
-0.5
0.8
Volts
IIX
Input Load Current
VSS':;; VI.:;; VCC
-10
+10
IJA
102
Output Leakage Current
VCC .:;; VO .:;; VSS+.40
-10
+10
IJA
ICC
VCC Supply Current
= +25°C
= O°C
TA = -55°C
(HREQ Only)
65
75
TA
CO
Output Capacitance
CI
I nput Capacitance
CIO
I/O Capacitance
TA
fc
Volts
3.3
130
150
mA
175
= 1.0MHz, Inputs = OV
NOTES:
4
8
pF
8
15
pF
10
18
pF
8. Output loading on the data bus is 1 Standard TTL gate plus
15pF for the minimum value and 1 Standard TTL gate plus
100pF for the maximum value.
9. Successive read and/or write operations by the external
processor to program or examine the controller must be
timed to allow at least 600ns for the Am9517A or
Am9517A-1 and at least 450ns for the Am9517A-4 as recovery time between active read or write pulses.
10. Parameters are listed in alphabetical order.
11. Pin 5 is an input that should always be at a logic high level.
An internal pull-up resistor will establish a logic high when
the pin is left floating. Alternatively, pin 5 may be tied to
VCC.
12. Signals READ and WRITE refer to lOR and MEMW respectively for peripheral-to-memory DMA operations and to
MEMR and lOW respectively for memory-to-peripheral
DMA operations.
13. If N wait states are added during the write-to-memory half of
a memory-to-memory transfer, this parameter will increase
by N (TCY).
1. Typical values are for T A = 25°C, nominal supply voltage
and nominal processing parameters.
2. Input timing parameters assume transition times of 20ns or
less. Waveform measurement points for both input and output signals are 2.0V for High and O.8V for Low, unless
otherwise noted.
3. Output loading is 1 Standard TTL gate plus 50pF capacitance unless noted otherwise.
4. The new lOW or MEMW pulse width for normal write will be
TCY -1 OOns and for extended write will be 2TCY-1 OOns. The
net lOR or MEMR pulse width for normal read will be
2TCY-50ns and for compressed read will be TCY-50ns.
5. TOO is specified for two different output HIGH levels. TD01
is measured at 2.0V. TD02 is measured at 3.3V. The value
for TD02 assumes an external 3.3kfl pull-up resistor connected from HREO to VCC.
6. DREO should be held active until DACK is returned.
7. DREO and DACK signals may be active high or active low.
Timing diagrams assume the active high mode.
7-143
Am9S17A
SWITCHING CHARACTERISTICS
ACTIVE CYCLE (Notes 2,3, 10, 11 and 12)
Am9S17A
Parameter
Description
Min
Max
Am9S17A-1
Min
Max
Am9S17A-4
Min
Max
Unit
TAEL
AEN HIGH from ClK lOW (S1) Delay Time
300
300
225
ns
TAET
AEN lOW from ClK HIGH (S1) Delay Time
200
200
150
ns
TAFAB
ADR Active to Float Delay from ClK HIGH
150
150
120
ns
TAFC
READ or WRITE Float from ClK HIGH
150
150
120
ns
TAFDB
DB Active to Float Delay from ClK HIGH
250
250
190
ns
TAHR
ADR from READ HIGH Hold Time
TCY-100
TAHS
DB from ADSTB lOW Hold Time
50
TAHW
ADR from WRITE HIGH Hold Time
TCY-50
TAK
TASM
TCY-100
ns
50
40
ns
TCY-50
TCY-50
TCY-100
ns
220
ns
250
190
ns
250
190
ns
190
ns
DACK Valid from ClK lOW Delay Time
280
EOP HIGH from ClK HIGH Delay Time
250
EOP LOW to ClK HIGH Delay Time
250
ADR Stable from ClK HIGH
250
250
280
TASS
DB to ADSTB LOW Setup Time
100
100
100
ns
TCH
Clock High Time (Transitions.,.; 10ns)
120
120
100
ns
TCl
Clock low Time (Transitions.,.; 10ns)
150
150
110
ns
TCY
ClK Cycle Time
320
320
250
ns
TDCl
ClK HIGH to READ or WRITE lOW Delay
(Note 4)
270
270
200
ns
TDCTR
READ HIGH from ClK HIGH (S4)
Delay Time (Note 4)
270
270
210
ns
TDCTW
WRITE HIGH from ClK HIGH (S4)
Delay Time (Note 4)
200
200
150
ns
160
160
120
ns
250
250
190
ns
TDQ1
TDQ2
HREQ Valid from ClK HIGH Delay Time
(Note 5)
TEPS
EOP LOW from ClK lOW Setup Time
60
60
45
TEPW
EOP Pulse Width
300
300
225
TFAAB
ADR Float to Active Delay from ClK HIGH
TFAC
READ or WRITE Active from ClK HIGH
200
TFADB
DB Float to Active Delay from ClK HIGH
300
THS
HACK valid to ClK HIGH Setup Time
TIDH
Input Data from MEMR HIGH Hold Time
ns
190
ns
200
150
ns
300
225
ns
250
250
ns
100
100
75
ns
0
0
0
ns
TIDS
Input Data to MEMR HIGH Setup Time
250
250
190
ns
TODH
Output Data from MEMW HIGH Hold Time
20
20
20
ns
TODV
Output Data Valid to MEMW HIGH (Note 13)
200
200
125
ns
TQS
DREQ to ClK lOW (S1, S4) Setup Time
120
120
90
ns
TRH
ClK to READY lOW Hold Time
20
20
20
ns
TRS
READY to ClK LOW Setup Time
100
100
60
ns
TSTl
ADSTB HIGH from elK HIGH Delay Time
200
200
150
TSn
ADSTB lOW from ClK HIGH Delay Time
140
140
110
7-144
ns
ns
Am9517A
SWITCHING CHARACTERISTICS
PROGRAM CONDITION (IDLE CYCLE)
(Notes 2, 3, 10, 11 and 12)
Am9S17A
Parameter
Description
Min.
Max.
Am9S17A-4
Am9S17A-1
Min.
Max.
Min.
Max.
Unit
50
50
50
ns
ADR Valid to WRITE HIGH Setup Time
200
200
150
ns
TCW
CS LOW to WRITE HIGH Setup Time
200
200
150
ns
TDW
Data Valid to WRITE HIGH Setup Time
200
200
150
ns
TRA
ADR or CS Hold from READ HIGH
TRDE
Data Access from READ LOW (Note 8)
TDRF
DB Float Delay from READ HIGH
20
TRSTD
Power Supply HIGH to RESET LOW
Setup Time
500
TAR
ADR Valid or CS LOW to READ LOW
TAW
0
0
150
ns
0
300
200
20
100
20
500
200
ns
100
ns
500
J1-s
TRSTS
RESET to First IOWR
2
2
2
TCY
TRSTW
RESET Pulse Width
300
300
300
ns
TRW
READ Width
300
300
250
ns
TWA
ADR from WRITE HIGH Hold Time
20
20
20
ns
TWC
CS HIGH from WRITE HIGH Hold Time
20
20
20
ns
TWD
Data from WRITE HIGH Hold Time
30
30
30
ns
TWWS
Write Width
200
200
200
ns
TAD
Data Access from ADR Valid, CS LOW
350
300
300
ns
SWITCHING WAVEFORMS
~---------TCW----------~
1----------- TWWS
-------~~
Ir-"';""'---
~----------TAW----------~
AO-A3
Dl..lO'+_ _ _ _ _IN_P_UT_V..;A_Ll_D_ _ _ _--l41Ow:~
~----------TDW----------
DBO-DB7 Ol.~~
__I
_ _ _ _._:;IN.::.P.:.UT~VA.:.:L:::ID~_ _ _ _--.,;~~~
Timing Diagram 1. Program Condition Write Timing (Note 9).
MOS-036
~[-
AO-A3
-l-
XXYXYJI
IIlXXXXXXXXXXX
ADDRESS MUST BE VALID
-
-TAR-j
TRW
I--TRA
J
f-----f--TAD------jt~_~~
~
I
TRDE
DBO-DB7
T RDF
(:
DATAOUTVALlD}---
Timing Diagram 2. Program Condition Read Cycle (Note 9).
MOS-037
7-145
Am9S17A
SWITCHING WAVEFORMS (Cont.)
so
Sl
S2
S3
S4
S2
S3
S4
SI
SI
Sl
TCH
HACK
AEN
ADSTB
DBO-DB7
AO-A7
- - - - - - - I I \ - ,--~"",--~~---:-----';"'---:-~-i--~~T-AFA-B--
------4\---~
DACK
READ
----\\0-------'1
WRITE
----H------.J!
1NT EOP
j,
Timing Diagram 3. Active Cycle Timing Diagram.
MOS-038
7-146
Am9517A
SWITCHING WAVEFORMS (Cent.)
elK
ADSTB
AO-A7
DBO-DB7
INT EOP
EXT EOP
Timing Diagram 4. Memory-to-Memory.
MOS-039
fI
elK
READY
Timing Diagram 6. Compressed Timing.
Timing Diagram 5. Ready Timing.
MOS-040
vee
~f-of_------TRsTD-------~
________________
RESET
IOROR lOW
MOS-041
_
--Jr~======~-T-R-S1W--------------~-~~
t
T~~TS-1
--------------------------------------~)~
Timing Diagram 7. Reset Timing.
MOS-042
7-147
Am9517A
APPLICATION INFORMATION
Figure 6 shows a convenient method for configuring a DMA
system with the Am9517A Controller and a microprocessor
system. The Multimode DMA Controller issues a Hold Request
to the processor whenever there is at least one valid DMA Request from a peripheral device. When the processor replies with
a Hold Acknowledge signal, the Am9517A takes control of the
Address Bus, the Data Bus and the Control Bus. The address for
the first transfer operation comes out in two bytes - the least
significant eight bits on the eight Address outputs and the most
significant eight bits on the Data Bus. The contents of the Data
Bus are then latched into the Am74LS373 register to complete
the full 16 bits of the Address Bus. The Am74LS373 is a high
speed, low power, 8-bit, 3-state register in a 20-pin package.
After the initial transfer takes place, the register is updated only
after a carry or borrow is generated in the least significant address byte. Four DMA channels are provided when one
Am9517A is used.
~
ADDRESS BUS AO-A15
.<~ /~
AO-A15
BUSEN
I ,,7
-
AEN
HlDA
HACK
HlDRQ
HREQ
...J
tJ
CPU
AO-A3
~ I~ I~
CP
I
A4-A7
12 I~
RESET
8·BIT lATCH
CS
ADSTB
M
M
~
~
~
I
C
4~
t t
CLOCK
OE
Am74lS373
Am9517A
'"
A8-A15
......
-
DBODB7
r
"
C
/~
-)
V
41
MEMR
} OO~'"
MEMW
BUS
iOii
lOW
DBO-DB7
""'7 ~
SYSTEM DATA BUS
V
Figure 6. Basic DMA Configuration.
Metallization and Pad Layout
~.~
iOii1
~
MEMR
MEMW
~M
4 -----,
38
37
(Tie to +5V)
READY
5
6
36
35
EOP
A3
HACK
7
34
A2
ADSTB
8
AEN
9
;;dl;••;~I~!llffE;
A5
A4
33
A1
AO
HREQ 10
32
31
vce (+5V)
CS
11
30
DBO
ClK 12
29
DB1
RESET 13
28
DB2
DACK2 14
DACK3
OREQ3
DREQ2
ellE01
DREQO
--==~~tft=~!fH~~q~~~==
15
16 17
18
19
(GND) VSS 20
7-148
27
DB3
26
25
24
23
22
DB4
DACKO
DACK1
DB5
DB6
21
DB7
DIE SIZE
0.198" X 0.210"
MOS-043
Am9519A
Universal Interrupt Controller
DISTINCTIVE CHARACTERISTICS
GENERAL DESCRIPTION
The Am9519A Universal Interrupt Controller is a processor
support circuit that provides a powerful interrupt structure
to increase the efficiency and versatility of
microcomputer-based systems. A single Am9519A manages up to eight maskable interrupt request inputs, resolves priorities and supplies up to four bytes of fully
programmable response for each interrupt. It uses a simple expansion structure that allows many units to be cascaded for control of large numbers of interrupts. Several
programmable control features are provided to enhance
system flexibility and optimization.
• Eight individually maskable interrupt inputs
• Software interrupt request capability
• Fully programmable 1, 2, 3 or 4 byte responses
• Unlimited daisy-chain expansion capability
• Fixed or rotating priority resolution
• Common vector option
• Polled mode option
• Optional automatic clearing of acknowledged interrupts
• Bit set/reset capability for Mask register
The Universal Interrupt Controller is designed with a general purpose interface to facilitate its use with a wide
range of digital systems, including most popular 8-bit
microprocessors. Since the response bytes are fully programmable, any instruction or vectoring protocol appropriate for the host processor may be used.
• Master Mask bit disables all interrupts
• Pulse-catching interrupt input circuitry
• Polarity control of interrupt inputs and output
• Various timing options including 8085A compatible
Am9519A-1
• Single +5V supply
o 100% MIL-STO-883 reliability assurance testing
When the Am9519A controller receives an unmasked Interrupt Request, it issues a Group Interrupt output to the CPU.
When the interrupt is acknowledged, the controller outputs
the one-to-four byte response associated with the highest
priority unmasked interrupt request. The ability of the CPU
to set interrupt requests under software control permits
hardware prioritization of software tasks and aids system
diagnostic and maintenance procedures.
BLOCK DIAGRAM
BYTE
CONTROL
MEMORY
BX2
cs
AD
RESPONSE
MEMORY
B X 32
RIW RAM
iVA
c/o
PAUSE
DBO-DB7
INTERRUPT
CONTROL
EO
INTERRUPT
REQUESTS
GINT _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---1
M05-143
ORDERING INFORMATION
Package
Type
DOC
~
Hermetic DIP"
-55°C
Molded DIP
"DC
=
Timing Options
Ambient
Temperature
DOC
Side-Brazed Ceramic
TA
~
~
~
TA
TA
CC
~
~
=
+7DoC
+125°C
+7DoC
Am9519A
Am9519A-1
AM9519ADC/CC
AM9519A-1 DC/CC
AM9519ADM
AM9519APC
Cerdip
7-149
AM9519A-1PC
Am9519A
CONNECTION DIAGRAM
cs
28
VCC (+5V)
Wl\
27
C/O
lID
26
I"ACR
DB7
25
IREQ7
DB6
24
IRE06
DB5
23
IRE05
DB4
22
IRE04
DB3
21
IRE03
DB2
20
IRE02
edge transition. Active inputs are latched internally in the
Interrupt Request Register. After the IRR bit is cleared, an
IREO transition of the programmed polarity must occur to
initiate another request.
RIP (Response In Process, Input/Output)
Response In Process is a bidirectional signal used when
two or more Am9519A circuits are cascaded. It permits
multibyte response transfers to be completed without interference from higher priority interrupts. An Am9519A that
is responding to an acknowledged interrupt will treat RIP
as an output and hold it low until the acknowledge response is finished. An Am9519A without an acknowledged
interrupt will treat RIP as an input and will ignore lACK
pulses as long as RIP is low. The RIP output is open drain
and requires an external plIlIlIp resistor to VCC.
Am9519A
OBI
10
19
IREOI
DBO
11
18
IREOO
RIP
12
17
GINT
EI
13
16
EO
lACK (Interrupt Acknowledge, Input)
(GND)VSS
14
15
PAUSE
INTERFACE SIGNAL DESCRIPTION
The active low Interrupt Acknowledge line indicates that
the external system is asking for interrupt response information. Depending on the programmed state of the
Am9519A, it will accept 1, 2, 3 or 4 lACK pulses; one response byte is transferred per pulse. The first lACK pulse
causes selection of the highest priority unmasked pending
interrupt request and generates a RIP output signal.
VCC: +5 Volt Power Supply
VSS: Ground
PAUSE (Pause, Output)
Top View
Pin 1 is marked for orientation.
MOS·DI9
The active-low Pause signal is used to coordinate interrupt
responses with data bus and control timing. Pause goes
low when the first lACK is received and remains low until
"RiP" goes low. The external system can use Pause to stretch
the acknowledge cycle and allow the control timing to automatically adjust to the actual priority resolution delays in
the interrupt system. Second, third and fourth response
bytes do not cause Pause to go low. Pause is an open drain
output and requires an external pullup resistor to vec.
DBO - DB7 (Data Bus, Input/Output)
The eight bidirectional data bus signals are used to transfer information between the Am9519A and the system data
bus. The direction of transfer i"s controlled by the lACK,
WR and RD input signals. Programming and control information are written into the device; status and response
data are output by it.
CS (Chip Select, Input)
The active low Chip Select input enables read and write
operations on the data bus. Interrupt acknowledge responses are not conditioned by CS.
EO (Enable Out, Output)
The active high EO signal is used to implement daisychained cascading of several Am9519A circuits. EO is connected to the EI input of the next lower priority chip. On
receipt of an interrupt acknowledge, each EO will go inactive
until it has been determined that no valid interrupt request is
pending on that chip. If an active request is present, EO
remains low. EO is also held low when the master mask bit is
active, thus disabling all lower priority chips.
RD (Read, Input)
The active low Read signal is conditioned by CS and indicates that information is to be transferred from the
Am9519A to the data bus.
WR (Write, Input)
The active low Write signal is conditioned by es and indicates that data bus information is to be transferred from
the data bus to a location within the Am9519A.
EI (Enable In, Input)
The active high EI signal is used to implement daisychained cascading of several Am9519A circuits. EI is connected to EO of the next higher priority chip. It may also be
used as a hardware disable input for the interrupt system.
When EI is low lACK inputs are ignored. EI is internally
pulled up to VCC so that no external pullup is needed when
EI is not used.
C/o (Control/Data, Input)
The e/iS control signal selects source and destination locations for data bus read and write operations. Data read or
write transfers are made to or from preselected internal
registers or memory iocations. Control write operations
load the command reqister and control read operations
output the status register.
GINT (Group Interrupt, Output)
IREQO - IREQ7 (Interrupt Request, Input)
The Interrupt Request signals are used by external devices to indicate that service by the host CPU is desired.
IREO inputs are accepted asynchronously and they may
be programmed for either a high-to-Iow or low-to-high
The Group Interrupt output signal indicates that at least
one unmasked interrupt request is pending. It may be
programmed for active high or active low polarity. When
active low, the output is open drain and requires an external pull up resistor to VCC.
7-150
Am9519A
REGISTER DESCRIPTION
Interrupt Request Register (lRR): The 8-bit IRR is used to
store pending interrupt requests. A bit in the IRR is set
whenever the corresponding IREQ input goes active. Bits
may also be set under program control from the CPU,
thus permitting software generated interrupts. IRR bits
may be cleared under program control. An IRR bit is automatically cleared when its interrupt is acknowledged. All
IRR bits are cleared by a reset function.
Interru~t Service Register (lSR): The 8-bit ISR contains
one bit for each IREQ input. It is used to indicate that a
pending interrupt has been acknowledged and to mask all
lower priority interrupts. When a bit is set by the acknowledge logic in the ISR, the corresponding IRR bit is
cleared. If an acknowledged interrupt is not programmed
to be automatically cleared, its ISR bit must be cleared by
the CPU under program control when it is desired to
permit interrupts from lower priority devices. When the
interrupt is programmed for automatic clearing, the ISR
bit is automatically reset during the acknowledge sequence. All ISR bits are cleared by a reset function.
Interrupt Mask Register (lMR): The 8-bit IMR is used to
enable or disable the individual interrupt inputs. The IMR
bits correspond to the IREQ inputs and all eight may be
loaded, set or cleared in parallel under program control.
In addition, individual IMR bits may be set or cleared by
the CPU. A reset function will set all eight mask bits, disabling all requests. A mask bit that is set does not disable
the IRR, and an IREQ that arrives while a corresponding
mask bit is set will cause an interrupt later when the mask
bit is cleared. Only unmasked interrupt inputs can generate a Group Interrupt output.
Response Memory: An 8 x 32 read/write response memory is included in the Am9519A. It is used to store up to
four bytes of response information for each of the eight
interrupt request inputs. All bits in the memory are programmable, allowing any desired vector, opcode, instruction or other data to be entered. The Am9519A transfers
the interrupt response information for the highest priority
unmasked interrupt from the memory to the data bus
when the lACK input is active.
Auto Clear Register: The 8-bit Auto Clear register contains one bit for each IREQ input and specifies the operating mode for each of the ISR bits. When an auto clear bit
is off, the corresponding ISR bit is set when that interrupt
is acknowledged and is cleared by software command.
When an auto clear bit is on, the corresponding ISR bit is
cleared by the hardware at the end of the acknowledge
sequence. A reset function clears all auto clear bits.
Status Register: The 8-bit Status register contains information concerning the internal state of the chip. It is
especially useful when operating in the polled mode in
order to identify interrupting devices. Figure 1 shows the
status register bit assignments. The polarity of the GINT
bit 7 is not affected by the GINT polarity control (Mode bit
status register bit assignments. Bits SO-52 are set asynchronously to a status register read operation. It is recommended to read the register twice and to compare the binary
vectors for equality prior to the proceeding with device service in polled mode. The polarity of the GINT bit 7 is not
affected by the GINT polarity control (Mode bit 3). The Status
register is read by executing a read operation (CS = 0, RS = 0)
with the control location selected (c/iS = 1).
Mode Register: The 8-bit Mode register controls the
operating options of the Am9519A. Figure 2 shows the bit
assignments for the Mode register. The five low order
mode bits (0 through 4) are loaded in parallel by command. Bits 5,6 and 7 are controlled by separate commands.
(See Figure 4.) The Mode register cannot be read out directly to the data bus, but Mode bits 0, 2 and 7 are availablo
as part of the Status register.
Command Register: The 8-bit Command register stores
the last command entered. Depending upon the command opcode, it may initiate internal actions or precondition the part for subsequent data bus transfers. The
Command register is loaded by executing a write operation (WR = 0) with the control location selected (Ci5 = 1),
as shown in Figure 3.
Byte Count Register: The length in bytes of the response
associated with each interrupt is independently programmed so that different interrupts may have different length
responses. The byte count for each response is stored in
eight 2-bit Byte Count registers. For a. given interrupt the
Am9519A will expect to receive a number of lACK pulses
that equals the corresponding byte count, and will hold RIP
low until the count is satisfied.
7-151
Am9519A
1 s71 s61 s51 s41 s31 s21 S1
1so I
~
Priority Mode
o Fixed
1 Rotating
Binary vector indicating the
number of the highest priority
unmasked bit that is set in I R R.
Valid only when S7 = O.
Vector Selection
o Individual vector
1 Common vector
Master Mask Bit
o Chip disarmed
1 Chip armed
'--_ _ _ Interrupt Mode
o Interrupt
1 Polled
Interrupt Mode
o Interrupt
1 Polled
' - - - - - - - - GINT Polarity
o Active low
1 Active high
Priority Mode
o Fixed
1 Rotating
' - - - - - - - - - I REQ Polarity
o Active low
1 Active high
Enable Input
o Chip disabled
1 Chip enabled
1....-_ _ _ _ _ _ _ _ _
Group Interrupt
1 No unmasked
IRR bit set
o At least one unmasked
IRR bitset
Figure 1. Status Register Bit Assignments.
' - - - - - - - - - - - - - Master Mask Bit
o Chip disarmed·
1 Chip armed
Figure 2. Mode Register Bit Assignments.
MOS·025
FUNCTIONAL DESCRIPTION
Interrupts are used to improve system throughput and response time by eliminating heavy dependence on
software polling procedures. Interrupts allow external devices to asynchronously modify the instruction sequence
of a program being executed. In systems with multiple·interrupts, vectoring can further improve performance by allowing direct identification of the interrupting device and
its associated service routine. The Am9519A Universal Interrupt Controller contains, on one chip, all of the circuitry
necessary to detect, prioritize and manage eight vectored
interrupts. It includes many options and operating modes
that permit the design of sophisticated interrupt systems.
Operating Sequence
A brief description of a typical sequence of events in an
operating interrupt system will illustrate the general interactions among the host CPU, the interrupt controller and the
interrupting peripheral.
1. The Am9519A controller is initialized by the CPU in
order to customize its configuration and operation for
the application at hand. Both the controller and the
CPU are then enabled to accept interrupts.
MOS·026
2. One (or more) of the interrupt request inputs to the
controller becomes active indicating that peripheral
equipment is asking for service. The controller asynchronously accepts and latches the request(s).
3. If the request is masked, no further action takes place.
If the request is not masked, a Group Interrupt output
is generated by the controller.
4. The GINT signal is recognized by the CPU which normally will complete the execution of the current instruction, insert an interrupt acknowledge sequence
into its instruction execution stream, and disable its
internal interrupt structure. The controller expects to
receive one or more lACK signals from the CPU during
the acknowledge sequence.
Reset
The ~eset function is accomplished by software command
or automatically during power-up. The reset command
may be issued by the CPU at any time. Internal power up
circuitry is triggered when VCC reaches a predetermined
threshold, causing a brief internal reset pulse. In both
cases, the resulting internal state of the machine is that all
registers are cleared except the Mask register which is
set. Thus no Group Interrupt will be generated and no interrupt requests will be recognized. The response memory
and Byte Count registers are not affected by reset. Their
contents after power-up are unpredictable and must be
estabiished by the host CPU during initialization.
Register Preselection
00 Interrupt service register
01 Interrupt mask register
10 Interrupt request register
11 Auto clear register
5. When the controller receives the lACK signal, it brings
PAUSE low and selects the highest priority unmasked
pending request. When selection is complete, the RIP
output is brought low and the first byte in the response
memory associated with the selected request is output
on the data bus. PAUSE stays low until RIP goes low. RIP
stays low until the last byte of the response has been
transferred.
6. During the acknowledge sequence, the IRR bit corresponding to the selected request is automatically
cleared, and the corresponding ISR bit is set. When the
ISR bit is set, the Group Interrupt output is disabled until
a higher priority request arrives or the ISR bit is cleared.
The ISR bit will be cleared by either hardware or
software.
7. If a higher priority request arrives while the currerit request is being serviced, GINT will be output by the controller, but will be recognized and acknowledged only if
the CPU has its interrupt input enabled. If acknowledged,
the corresponding higher priority ISR bit will be set and
the requests nested.
7-152
Am9519A
Information Transfers
Figure 3 shows the control signal configurations for all
information transfer operations between the Am9519 and
the data bus. The following conventions are assumed: RD
and WR active are mutually exclusive; RD, WR and C/Dhave
no meaning unless CS is low; active lACK pulses occur only
when CS is high.
Fo..!:. reading, the Status register is selected directly by the
C/D control input. Other internal registers are read by preselecting the desired register with mode bits 5 and 6, and
then executing a data read. The response memory can be
read only with lACK pulses. For writing, the Command
register is selected directly by the C/D control input. The
Mask and Auto Clear registers are loaded following
specific commands to that effect. To load each level of the
response memory, the response preselect command is issued to select the desired level. An appropriate number of
data write operations are then executed to load that level.
CONTROL INPUT
CS C/O RD WR lACK
DATA BUS
OPERATION
0
0
0
1
1
Transfer contents of
preselected data register
to data bus
0
0
1
0
1
Transfer contents of data bus
to preselected data register
0
1
0
1
1
Transfer contents of status
register to data bus
0
1
1
0
1
Transfer contents of data
bus to command register
1
X
X
X
0
Transfer contents of selected
response memory location
to data bus
1
X
X
X
1
No information transferred
chip interface, with IREOO the highest and IRE07 the lowest. In the rotating mode, relative priority is the same as
for the fixed mode and the most recently serviced request
is assigned the lowest priority. In the fixed mode, a lower
p-riority request might never receive service if enough
higher priority requests are active. In the rotating mode,
any request will receive service within a maximum of
seven other service cycles no matter what pattern the request inputs follow_
Mode bit 1 selects the individual I common vector option.
Individual vectoring provides a unique location in the response memory for each interrupt request. The common
vector option always supplies the response associated
with IREOO no matter which request is being acknowledged.
Mode bit 2 specifies interrupt or polled operation. In the
polled mode the Group Interrupt output is disabled. The CPU
may read the Status register to determine if a request is
pending. Since lACK pulses are not normally supplied in
polled mode, the IRR bit is not automatically cleared, but may
be cleared by command. With no lACK input the ISR and the
response memory are not used. An Am9519A in the polled
mode has EI connected to EO so that in multichip interrupt
systems the polled chip is functionally removed from the
priority hierarchy.
Mode bit 3 specifies the sense of the GINT output. When
active high polarity is selected the output is a two-state
configuration. For active low polarity, the output is open
drain and requires an external pull-up resistor to provide
the high logic level. The open drain output allows wiredor configurations with other similar output signals.
Mode bit 4 specifies the sense of the IREO inputs. When
active low polarity is selected, the IRR responds to falling
edges on the request inputs. When active high is selected,
the IRR responds to rising edges.
Mode bits 5 and 6 specify the register that will be read on
subsequent data read operations (C/O = 0, RD = 0). This
preselection remains valid until changed by a reset or a
command.
Figure 3. Summary of Data Bus Transfers.
The Pause output may be used by the host CPU to ensure that
proper timing relationships are maintained with the Am9519A
when lACK is active. The lACK pulse width required depends
on several variables, including: operating temperature, internal logic delays, number of interrupt controllers chained
together, and the priority level ofthe interrupt being acknowledged. When delays in these variables combine to delay
selection of a request following the falling edge of the first
lACK, the Pause output may be used to extend the lACK
pulse, if necessary. Pause will remain low until a request
has been selected, as indicated by the falling edge of RIP.
Typically, the internal interrupt selection process is quite
fast, especially for systems with a single Am9519A and Pause
will consequently remain low for only a very brief interval
and will not cause extension of the lACK timing.
Operating Options
The Mode register specifies the various combinations of
operating options that may be selected by the CPU. It is
cieared by power-up or by a reset command.
Mode bit 0 specifies the rotating/fixed priority mode (see
Figure 2). In the fixed mode, priority is assigned to the request inputs based upon their physical location at the
7-153
Mode bit 7 is the master mask bit that disables all request
inputs. It is used to disable all interrupts without modifying the IMR so that the previous IMR contents are valid
when interrupts are re-enabled. When the master mask bit
is low, it causes the EO line to remain disabled (low).
Thus, for multiple-chip interrupt systems, one master
mask bit can disable the whole interrupt structure. Alternatively, portions of the structure may be disabled. The
state of the master mask bit is available as bit S3 of the
Status register.
Programming
After reset, the Am9519A must be initialized by the CPU in
order to perform useful work. At a minimum, the master
mask bit and at least one of the IMR bits should be enabled. If vectoring is to be used, the response memory
must be loaded; if not, the mode must be changed to a
non-vectored configuration. Normally, the first step will
be to modify the Mode register and the Auto clear register in order to establish the configuraton desired for the
application. Then the response memory and byte count
will be loaded for those request levels that will be in use.
Finally, the master mask bit and at least portions of the
IMR will be enabled to allow interrupt processing to proceed.
Am9519A
Commands
The host CPU configures, changes and inspects the internal
condition of the Am9519A using the set of commands shown
in Figure 4. An "X" entry in the table indicates a "don't
care" state. All commands are entered by directly loading
the Command register as shown in Figure 3 (C/O = " WR
= 0). Figure 5 shows the coding assignments for the Byte
Count registers. A detailed description of each command is
contained in the Am9519A Application Note AMPUB-07'.
BY1
BYO
COUNT
0
,
,
2
,,
0
6
0
0
5
0
0
0
0
0
1
3
4
Figure 5. Byte Count Coding.
COMMAND CODE
7
0
COMMAND
DESCRIPTION
4
3
2
1
0
0
0
0
X
0
X
0
X
Reset
Clear all IRR and all IMR bits
0
0
0
,
,
'I
B2
81
80
Clear IRR and IMR bit specified by 82, 81, 80
0
0
1
0
0
X
X
X
Clear all IMR bits
0
0
1
0
1
82
81
80
Clear IMR bit specified by B2, 81, 80
0
0
1
1
0
X
X
X
Set all IMR bits
0
0
1
1
1
82
81
80
Set IMR bit specified by 82, 81, 80
0
1
0
0
0
X
X
X
Clear all IRR bits
0
1
0
0
1
82
81
80
Clear IRR bit specified by 82.81.80
0
1
0
1
0
X
X
X
Set all IRR bits
0
1
0
1
1
B2
81
80
Set IRR bit specified by 82. 81.80
0
1
1
0
X
X
X
X
Clear highest priority ISR bit
0
1
1
1
0
X
X
X
Clear all ISR bits
0
1
1
1
1
82
81
80
Clear ISR bit specified by 82.81, 80
1
0
0
M4
M3
M2
M1
MO
Load Mode register bits 0-4 with specified pattern
1
0
1
0
M6
M5
0
0
Load Mode register bits 5. 6 with specified pattern
1
0
1
0
M6
M5
0
1
Load Mode register bits 5, 6 and set mode bit 7
1
0
1
0
M6
M5
1
0
Load Mode register bits 5, 6 and clear mode bit 7
1
0
1
1
X
X
X
X
1
1
0
0
X
X
X
X
1
1
1
8Y1
8YO
L2
L1
LO
0
Preselect IMR for subsequent loading from data
bus
Preselect Auto Clear register for subsequent
loading from data bus
Load BY', 8YO into byte count register and
preselect response memory level specified by L2,
L 1, LO for subsequent loading from data bus
Figure 4. Am9519A Command Summary.
7-154
MAXIMUM RATINGS
Am9519A
above which useful life may be impaired
Storage Temperature
-65°C to +150°C
Ambient Temperature Under Bias
-55°C to +125°C
VCC with Respect to VSS
-O.5V to +7.0V
All Signal Voltages with Respect to VSS
-O.5V to +7.0V
Power Dissipation (Package Limitation)
1.5W
The products described by this specification include internal circuitry designed to protect input devices from damaging accumulations of
static charge. It is suggested, nevertheless, that conventional precautions be observed during storage, handling and use in order to avoid
exposure to excessive voltages.
OPERATING RANGE
Part Number
Am9519ADC/CC
Am9519A-1DC
Am9519ADM
vce
vss
O°C """ TA """ +70°C
+5.0V ±5%
OV
-55°C""" TA """ +125°C
+5.0V ±10%
OV
Ambient Temperature
ELECTRICAL CHARACTERISTICS
Parameter
Over Operating Range (Note 1)
Description
VOH
Output High Voltage
(Note 12)
VOL
Output Low Voltage
VIH
VIL
Input High Voltage
Input Low Voltage
IIX
Input Load Current
10Z
Output Leakage Current
Test Conditions
= -200JLA
10H = -100JLA (EO only)
10L = 3.2mA
10L = 1.0mA (EO only)
10H
VSS """ VIN """ VCC
I
EI Input
I Other Inputs
VSS """ VOUT """ VCC, Output off
TA
= +25°C
= O°C
Min.
Typ.
Max.
2.4
Volts
2.4
0.4
0.4
2.0
-0.5
VCC
0.8
-60
10
-10
10
-10
10
80
125
100
145
15
ICC
VCC Supply Current
CO
Output Capacitance
fc = 1.0MHz
CI
Input Capacitance
TA = 25°C
10
CIO
I/O Capacitance
All pins at OV
20
TA
7-155
Unit
Volts
Volts
Volts
JLA
p,A
rnA
pF
Am9519A
SWITCHING CHARACTERISTICS
Parameters
•
/
Over Operating Range (Notes 2, 3, 4, 5)
Am9519A
Max
Description
Min
Min
TAVRL
C/O Valid and CS LOW to Read LOW
0
0
TAVWL
C/O Valid and CS LOW to Write LOW
0
0
TCLPH
RIP LOW to PAUSE HIGH (Note 6)
75
TCLOV
RIP LOW to Data Out Valid (Note 7)
TDVWH
Data In Valid to Write HIGH
250
TEHCL
Enable in HIGH to RIP LOW (Notes 8, 9)
30
TIVGV
Interrupt Request Valid to Group Interrupt Valid
TIVIX
Interrupt Request Valid to Interrupt Request Don't Care
(IREO Pulse Duration)
300
75
50
Am9519A-1
Max
Units
ns
ns
300
ns
40
ns
200
300
30
800
250
ns
300
ns
650
ns
250
ns
TKHCH
lACK HIGH to RIP HIGH (Note 8)
400
350
TKHKL
lACK HIGH to lACK LOW (iACK Recovery)
500
500
ns
TKHNH
lACK HIGH to EO HIGH (Notes 10, 11)
800
700
ns
TKHOX
lACK HIGH to Data Out Invalid
20
200
20
100
ns
TKLCL
lACK LOW to RIP LOW (Note 8)
75
600
75
450
ns
TKLKH
lACK LOW to lACK HIGH (1st lACK)
975
TKLNL
lACK LOW to EO LOW (Notes 10, 11)
TKLPL
lACK LOW to PAUSE LOW
25
175
TKLOV
lACK LOW to Data Out Valid (Note 7)
25
TKLOV1
1st lACK LOW to Data Out Valid
75
TPHKH
PAUSE HIGH to lACK HIGH
0
0
TRHAX
Read HIGH to C/O and CS Don't Care
0
0
TRHOX
Read HIGH to Data Out Invalid
20
TRLOV
Read LOW to Data Out Valid
TRLOX
Read LOW to Data Out Unknown
50
50
ns
TRLRH
Read LOW to Read HIGH (RD Pulse Duration)
300
250
ns
TWHAX
Write HIGH to C/O and CS Don't Care
0
0
ns
TWHDX
Write HIGH to Data In Don't Care
0
0
ns
TWHRW
Write HIGH to Read or Write LOW (Write Recovery)
600
400
ns
TWLWH
Write LOW to Write HIGH (WR Pulse Duration)
300
250
ns
800
125
ns
ns
100
ns
25
125
ns
300
25
200
ns
650
75
490
ns
200
20
300
ns
ns
100
ns
200
ns
NOTES:
1. Typical values for TA = 25°C, nominal supply voltage and
2.
3.
4.
5.
6.
7.
8.
nominal processing parameters.
Test conditions assume transition times of 20ns or less, timing
reference levels of 0.,8V and 2.0V and output loading of one
TTL gate plus 100pF, unless otherwise noted.
Transition abbreviations used for the switching parameter
symbols include: H = High, L = Low, V = Valid, X = unknown
or don't care, Z = high impedance.
Signal abbreviations used for the switching parameter symbols include: R = Read, W = Write, 0 = Data Out, D = Data
In, A = Address (CS and C/O), K = Interrupt Acknowledge,
N = Enable Out, E = Enable In, P = Pause, C = RIP.
Switching parameters are listed in alphabetical order.
During the first lACK pulse, PAUSE will be low long enough to
allow for priority resolution and will not go high until after RIP
goes low (TCLPH).
TKLOV applies only to second, third and fourth lACK pulses
while RIP is low. During the first lACK pulse, Data Out will be
valid following the falling edge of RIP (TCLOV).
RIP is pulled low to indicate that an interrupt request has been
selected. RIP cannot be pulled low until EI is high following an
internal delay. TKLCL will govern the falling edge of RIP when
7-156
9.
10.
11.
12.
EI is always high or is high early in the acknowledge cycle.
TEHCL will govern when EI goes high later in the cycle. The
riSing edge of EI will be determined by the length of the preceding priority resolution chain. RIP remains low until after the
rising edge of the lACK pulse that transfers the last response
byte for the selected IREO.
Test conditions for the EI line assume timing reference levels
of 0.8V and 2.0V with transition times of 10ns or less.
Test conditions for the EO line assume output loading of two
LS TTL gates plus 30pF and timing reference levels of 0.8V
and 2.0V. Since EO normally only drives EI of another
Am9519A, higher speed operation can be specified with this
more realistic test condition.
The arrival of lACK will cause EO to go low, disabling additional circuits that may be connected to EO. If no valid interrupt
is pending, EO will return high when EI is high. If a pending
request is selected. EO will stay low until after the last lACK
pulse for that interrupt is complete and RIP goes high.
VOH specifications do not apply to RIP or to GINT when
active-low. These outputs are open-drain and VOH levels will
be determined by external circuitry.
Am9519A
SWITCHING WAVEFORMS
IVIX
==§;:
-"v~x~
---"\
IREO
GINT
[I
.,..--~
---------:
r--
~:=
""~'------~
------------------------~------~------------~i
---L\
~~_: -:- t~-~-~- -" "'- - - - - -" I I ~1------------1-1-Lt=-r--r, ~ ~'"
EO
I
kTKI
___________
TK_L_N_'
(Note8)
~
'~"",---.:---_.JI
TKLCL
"'''
II
I
DB
MOS-144
Interrupt Operations
D
\
'--
DB--------~:XXI
MOS-145
Data Bus Trans.fers
7-157
Am9519A
APPLICATIONS
I\.
ADDRESS BUS
V
+
I
AO-A15
CS
iOR
RD
lOW
WR
INT
GINT
INTA
lACK
CPU
C/O
1m>
Am9519A
8
L
IRE Q
PAUSE
ROY
DB
DBO-DB7
't
+
~
SYSTEM DATA BUS
Figure 6. Base Interrupt System Configuration.
MOS·146
t\.
f
AD-A15
ADDRESS BUS
L~
-B
G
HLDA
TANK
AmBDBDA/
Am9DBOA
rD~
r-~
¢1_¢1
-
¢ 2 - ¢2
RESIN
RDY
RESET
SYNC
RDYIN
,--STSTB
Am8224
0--
~ Va 0--
!~~
INT
XTAL
~Y2
V
---
HLDA
INTA
WR o---c WR
DBIN
-
lOW
DBIN
iDA
RDY
RESET
SYNC
~
AmB228
~
i'r
STSTB
'-----
+
L "'
+
'-0
GINT
_
EI
+
WR
CS
Am9519A
C/D
RiP
f
EO
PAUSE
L~
lACK
RD
'--c
WR
R1l'
~>.
IREO
8
INTERRUPT
REOUESTS
V
SYSTEM DATA BUS
C/D
Am9519A
PAUSE
INTERRUPT
REOUESTS
""-/
fACi(
EI
IREO
8)'
CS
-
GINT
t\.
(DBD-DB71
V
Figure 7. Expanded Interrupt System Configuration.
7-158
MOS·147
Bipolar Support Products
for
MOS Microprocessor
and Memory Systems
NUMERICAL INDEX
Am3212
Am3216
Am3226
Am3448A
AmZ8103
AmZ8104
AmZ8107
AmZ8108
AmZ8120
AmZ8121
AmZ8127
AmZ8133
AmZ8136
AmZ8140
AmZ8144
AmZ8148
AmZ8160
AmZ8161
AmZ8162
AmZ8163
AmZ8164
AmZ8165
AmZ8166
AmZ8173
Am8212
Am8216
Am8224
Am8226
Am8228
Am8238
Page
8-Bit Input/Output Port ............................. : ............ 8-58
4-Bit Bidirectional Bus Driver .................................... 8-65
4-Bit Bidirectional Bus Driver .................................... 8-65
IEEE-488 Quad Bidirectional Bus Transceiver. . . . . . . . . . . . . . . . . . . . 8-1
Octal Bus Transceiver (Inverting) ............................... 8-6
Octal Bus Transceiver (Non-Inverting) .................. . . . . . . . .. 8-6
Octal Bus Transceiver (Inverting) ............................... 8-12
Octal Bus Transceiver (Non-Inverting) . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-12
Octal Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-14
8-Bit Comparator ............................................. 8-18
Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-22
Octal Latch (Inverting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-23
8-Bit Decoder w/Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-28
Octal 3-State Buffer (Inverting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-32
Octal 3-State Buffer (Non-Inverting) .. . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-32
Address Decoder w/Acknowledge. . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. 8-36
Error Detection and Correction Unit .. . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-41
EDC Bus Buffer (Inverting to Bus) .............................. 8-49
EDC Bus Buffer (Non-Inverting to Bus) . . . . . . . . . . . . . . . . . . . . . . . . .. 8-49
Refresh and EDC Controller ................................... 8-50
Dynamic Memory Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-51
Dynamic RAM Driver (Inverting) ................................ 8-52
Dynamic RAM Driver (Non-Inverting) . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-52
Octal Latch (Non-Inverting) .................................... 8-23
8-Bit Input/Output Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-58
4-Bit Bidirectional Bus Driver (Non-Inverting) . . . . . . . . . . . . . . . . . . . .. 8-65
Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-70
4-Bit Bidirectional Bus Driver (Inverting) ......................... 8-65
System Controller/Bus Driver for Am9080A ...................... 8-77
System Controller/Bus Driver for Am9080A ...................... 8-77
Am3448A
IEEE-488 Quad Bidirectional Transceiver
DISTINCTIVE CHARACTERISTICS
GENERAL DESCRIPTION
•
•
•
•
•
•
•
•
The Am3448A is a quad bidirectional transceiver meeting the
requirement of IEEE-488 standard digital interface for programmable instrumentation for the dJiver, receiver, and composite device load. One pull-up enable input is provided for
each pair of transceivers which controls the operating mode of
the driver outputs as either an open collector or active pull-up
configuration.
•
•
•
•
•
Four independent driver/receiver pairs
Three-state outputs
High impedance inputs
Receiver hysteresis - 600mV (Typ.)
Fast Propagation Times - 15-20ns (Typ.)
TTL compatible receiver outputs
Single +5 volt supply
Open collector driver output option with internal passive
pull up
Power up/power down protection (No invalid information
transmitted to bus)
No bus loading when power is removed from device
Required termination characteristics provided
Advanced Schottky processing
100% product assurance screening to MIL-STD-883
requirements
The receivers feature input hysteresis for improved noise immunity in system applications. The device bus (receiver input)
changes from standard bus loading to a high impedance load
when power is removed. In addition no spurious noise is generated on the bus during power-up or power-down.
LOGIC DIAGRAM
DATA
A
BUS
A
C
SEND/
RECEIVE A
SEND/
RECEIVE C
PULL-UP
ENABLE
PULL-UP
ENABLE
SEND/
RECEIVE B
SEND/
RECEIVE D
DATA
BUS
B
B
BUS
C
DATA
DATA
D
BUS
o
LlC-447
LlC-446
CONNECTION DIAGRAM
Top View
ORDERING INFORMATION
SEND/REC.
INPUT A
Package
Type
Temperature
Range
Order
Number
Hermetic DIP
Molded DIP
Dice
OOG to +70oG
OOG to +70oG
OOG to +70oG
MG3448AL
MG3448AP
AM3448AX
DATA A
BUS A
PULL-UP ENABLE
INPUT A-B
BUS B
DATAB
SEND/REC.
INPUT B
GND
Vee
SEND/REC.
INPUT 0
DATA 0
BUS 0
PULL-UP ENABLE
INPUT C-D
BUSC
DATAC
SEND/REC.
INPUT C
Note: Pin 1 is marked for orientation.
8-1
LlC-448
Am3448A
ABSOLUTE MAXIMUM RATINGS above which the useful life may be impaired
Storage Temperature
Supply Voltage
7.0V
Input Voltage
5.5V
150mA
Driver Output Current
ELECTRICAL CHARACTERISTICS
The following conditions apply unless otherwise noted:
Am3448A
TA
= O°C to 70°C
Vcc MIN.
= 4.75V
Vcc MAX.
= 5.25V
DC ELECTRICAL CHARACTERISTICS over operating temperature range
Typ.
Parameters
Test Conditions
Min.
(Note 1)
Max.
= O.BV
2.75
-
-
-1.5
5.0V ~ V(BUS) ~ 5.5V
0.7
-
2.5
= 0.5V
-1.3
-
-3.2
= OV, OV ~ V(BUS) ~ 2.75V
-
-
0.04
= 2.0V, IIC(O) = -18mA
VI(S/R) = 2.0V, VIH(O) = 2.0V,
VIH(E) = 2.0V,IOH = -5.2mA
VI(S/R) = 2.0V,IO l (0) = 48mA
VI(S/R) = 2.0V, VIH(O} = 2.0V
VIH(E) = 2.0V
VI(S/R) = 2.0V
VI(S/R) = 2.0V
-
-
-1.5
Volts
2.5
-
-
Volts
-
-
0.5
Volts
-30
-
-120
rnA
2.0
-
-
Volts
-
-
O.B
Volts
-200
-
40
-
-
200
VI(S/R)
400
600
-
VI(S/R)
-
1.6
1.8
0.8
1.0
-
2.7
-
-
Volts
-
-
0.5
Volts
-75
rnA
Description
Units
Bus Characteristics
V(BUS)
Bus Voltage
I(BUS)
Bus Pin Open, VI(S/R)
I(BUS)
VIC(BUS)
Bus Current
= -12mA
V(BUS)
VCC
3.7
Volts
rnA
Driver Characteristics
VIC(O)
Driver Input Clamp Voltage
VOH(O}
Driver Output Voltage - High Logic State
VOl(O)
Driver Output Voltage - Low Logic State
105(0)
Output Short Circuit Current
VIH(O}
Driver Input Voltage - High Logic State
Vll(O)
Driver Input Voltage - Low Logic State
11(0)
Driver Input Current - Data Pins
IIB(O)
VI(S/R)
VI(S/R)
= VI(E) = 2.0V
0.5 ~ VI(O) ~ 2.7V
I VI(O) = 5.5V
p.A
Receiver Characteristics
VHYS(R)
VllH(R)
Receiver Input Hysteresis
Receiver Input Threshold
VIHl(R)
VOH(R)
Receiver Output Voltage - High Logic State
VOl(R}
Receiver Output Voltage - Low Logic State
10S(R)
Receiver Output Short Circuit Current
= 0.8V
= O.BV, Low to High
VI(S/R) = 0.8V, High to Low
VI(S/R) = O.BV, IOH(R) = -800p.A,
V(BUS) = 2.0V
VI(S/R) = 0.8V,IOl(R) = 16mA, V(BUS) = 0.8V
VI(S/R) = 0.8V, V(BUS) = 2.0V
-15
mV
Volts
Enable, Send/Receive Characteristics
II(S/R)
Input Current - Send/Receive
II(E)
0.5 ~ VI(S/R) ~ 2.7V
-100
-
20
-
-
100
0.5 ~ VI(E) ~ 2.7V
-200
-
20
= 5.5V
-
-
100
-
63
85
-
106
125
VI(S/R)
IIB(S/R)
Input Current - Enable
VI(E)
IIB(E)
= 5.5V
p.A
p.A
Power Supply Current
ICCl
ICCH
Power Supply Current
I
Listening Mode - All Receivers On
Talking Mode - All Drivers On
Note 1. Typical limits are at VCC = 5.0V, 25°C ambient and maximum loading.
8-2
rnA
Am3448A
SWITCHING CHARACTERISTICS
Parameters
tpLH(D)
(Vee = S.OV, TA = 2SoC unless otherwise noted)
Test Conditions
Description
Propagation Delay of Driver (Fig. 2)
Propagation Delay of Receiver (Fig. 1)
tpHL(R)
tpHZ(R)
tpZH(R)
tpLZ(R)
Typ.
Max.
-
Propagation Delay Time - Send/Receiver to Data
(Fig. 4)
Output Low to High
-
2S
Output High to Low
-
23
30
Logic High to Third State
-
Third State to Logic High
-
30
Logic Low to Third State
-
30
Third State to Logic Low
tpHZ(D)
Logic High to Third State
-
30
Third State to Logic High
-
30
Logic Low to Third State
-
30
tpLZ(D)
Propagation Delay Time - Send/Receiver to Bus
(Fig. 3)
Third State to Logic Low
tpOFF(E)
Pull-Up Enable to Open Collector
-
30
Open Collector to Pull-Up Enable
-
20
Turn-On Time - Enable to Bus (Fig. S)
ns
ns
30
tpZL(D)
tpON(E)
ns
17
tpZL(R)
tpZH(D)
Units
15
Output High to Low
tpHL(D)
tpLH(R)
Min.
Output Low to High
ns
30
ns
TRUTH TABLE
Send/Rec.
Enable
Into Flow
0
X
Bus -+Data
Comments
1
1
Data -+Bus
Active Pull-Up
1
0
Data -+Bus
Open Collector
X = Don't Care
PROPAGATION DELAY TEST CIRCUITS AND WAVEFORMS
TO SCOPE
(OUTPUn
+s.ov
tl
- -I ·'""'~o,
, . - - - - - - - -...... - - - - 3.0V
TO SCOPE
(INPUn
INPUT
~
1.SV
j I; '""'''
OUTPUT
1.SV
ov
1.SV
1N916
OR EQUIV.
SENDI
REC.
f = 1.0MHz
tTLH = tTHL ,,:; S.Ons (10-90%)
Duty Cycle = SO%
"Includes Jig and Probe Capacitance.
Figure 1. Bus Input to Data Output (Receiver).
LlC-449
TO SCOPE
(INPUn
TO SCOPE
3.0V (OUPUT) 2.3V
DRIVER INPUT
38.3
LlC-4S0
~
""'0' -I 11.SV
1.SV
-I 1- .,,::,
t~2-.o-v------""""\L
OUTPUT
BUS
VO
H
O.8V
CL
I
VOL
30pF
f = 1.0MHz
tTLH = tTHL ,,:; S.Ons (10-90%)
Duty Cycle = SO%
PULL-UP ENABLE
"Includes Jig and Probe Capacitance.
LlC-4S1
~
3.0V
Figure 2. Data Input to Bus Output (Driver).
8-3
LlC-4S2
Am3448A
PROPAGATION DELAY TEST CIRCUITS AND WAVEFORMS (Cont.)
3.0V
0-- ZL
..Jf
~
TO SCOPE
(OUTPUT)
INPUT
, . - - - 3.0V
!\.'\,._l.S_v_ _ _ _ _ _
1.SV
OV
tpZH(D) -
ZL
TO OPEN
LOW OUTPUT
TO OPEN
13.S
480
TO SCOPE
(INPUT) - - - - - . .
------"-=--
OV
1.1V
f = 1.0MHz·
tTLH = tTHL .;; 5.0ns (10-90%)
Duty Cycle- = 50%
C L = 15pF (Includes Jig and Probe Capacitance)
Figure 3. Send/Receive Input to Bus Output (Driver).
LlC-453
TO SCOPE
(OUTPUT) S.OV
INPUT
LlC-4S4
-Lr - - - - - - -...., - - - - - 3.0V
..-...Il 1.SV
""\ 1.SV
OV
tpZH(R)
OUTPUT HIGH
TO OPEN
OUTPUT LOW
TO OPEN
VOL
OV
f = 1.0MHz
tTLH = tTHL .;; 5.0ns (10-90%)
Duty Cycle = 50%
CL = 15pF (Includes Jig and Probe Capacitance)
Figure 4. Send/Receive Input to Data Output (Receiver).
LlC-455
LlC-456
3.0V
TO SCOPE
(OUTPUT)
INPUT
ENABLE
BUS
~ 1.SV
tpON(E)
TO SCOPE
(INPUT)
480
j
I--
OUTPUT _ _ _ _
1.SV
~
3.0V
-II- tPOFF(E~V
....Jl-0~-·O-V------90-%-C : : :
PULSE
GENERATOR
CL
LlC-4S7
=
f = 1.0MHz
tTLH = tTHL';; 5.0ns (10-90%)
Duty Cycle = 50%
15pF (Includes Jig and Probe Capacitance)
Figure 5. Enable Input to Bus Output (Driver).
8-4
LlC-458
Am3448A
PROPAGATION DELAY TEST CIRCUITS AND WAVEFORMS (Cont.)
TYPICAL RECEIVER HYSTERESIS
CHARACTERISTICS
~
~
TYPICAL BUS LOAD LINE
6.0
4.0
E 2.0
5.0 ,-"---'-"""""--r---r----r-,--,
~~c==2~:~V 4=+:+I~=l
4.01-t----t--t--I--+-++-l--l
I
!z
w
~
3.0 t--t----t--t--I--+--++-I---I
~
2.0 t--t--l--+--I--+--++-I---I
~ -6.0
1.0 t--t---l--+--I--+--++-I---I
~ -S.O
@-10
.IF -12
!5
~
o
§
oc:r::c:t::I:I~
o
0.5
1.0
1.5
2.0
,.1-- -~
0
CI
~
I
c(
I--.J
-2.0
-4.0
-~I-'
.,.14
-4.0 -2.0
VI. INPUT VOLTAGE - VOLTS
J ..... -=
. . .v
0
2.0
4.0
6.0
Vsus. BUS VOLTAGE - VOLTS
LIC-459
TYPICAL APPLICATION
...
INSTRUMENT
A
(WITH GP-IB)
INSTRUMENT
B
(WITH GP-IB)
·
··
-------------
··
PROGRAMMABLE
CALCULATOR
(WITH GP-IB)
...
16 LINES TOTAL
(FOUR Am344SA'S FOR EACH BUS INTERFACE)
TYPICAL MEASUREMENT SYSTEM APPLICATION
8-5
LIC-460
AmZ8103 • AmZ8104
Octal Three-State Bidirectional Bus Transceivers
DISTINCTIVE CHARACTERISTICS
FUNCTIONAL DESCRIPTION
• a-bit bidirectional data flow reduces system package count
• 3-state inputs/outputs for interfacing with bus-oriented
systems
• PNP inputs reduce input loading
• VCC - 1.15V VOH interfaces with TTL, MOS and CMOS
• 48mA, 300pF bus drive capability
;; AmZ8103 inverting transceivers
• AmZ8104 non-inverting transceivers
• Transmit/Receive and Chip Disable simplify control logic
• 20-pin ceramic and molded DIP package
• Low power - 8mA per bidirectional bit
• Advanced Schottky processing
• Bus port stays in hi-impedance state during power up/down
• 100% product assurance screening to MIL-STD-883
requirements
The AmZ8103 and AmZ8104 are 8-bit 3-state Schottky transceivers. They provide bidirectional drive for bus-oriented microprocessor and digital communications systems. Straight through
bidirectional transceivers are featured, with 24m A drive capability
on the A ports and 48mA bus drive capability on the B ports. PNP
inputs are incorporated to reduce input loading.
One input, Transmit/Receive determines the direction of logic
signals through'the bidirectional transceiver. The Chip Disable
input disables both A and B ports by placing them in a 3-state
condition. Chip Disable is functionally the same as an active LOW
chip select.
The output high voltage (VOH) is specified at VCC - 1.15V
minimum to allow interfacing with MOS, CMOS, TTL, ROM, RAM,
or microprocessors.
AmZ8104
LOGIC DIAGRAM
CHIP
DISABLE -....---,,--_
(CD)
TRANSMITI
iiECEiVE
(TIA)
AmZ8103 has inverting transceivers.
BLI·216
CONNECTION DIAGRAM
Top View
LOGIC SYMBOL
APORT
CD
11
AmZ81 031
AmZ81 04
TIA
19
18
17
16
15
14
13
12
BPORT
BLI·169
vee = Pin 20
GND = Pin 10
Note: Pin 1 is marked for orientation.
8-6
BLI·170
AmZ8103· AmZ8104
AmZ8103· AmZ8104
ABSOLUTE MAXIMUM RATINGS (Above which the useful life may be impaired)
-65 to +150°C
Storage Temperature
Supply Voltage
7.0V
Input Voltage
5.5V
Output Voltage
5.5V
Lead Temperature (Soldering, 10 seconds)
ELECTRICAL CHARACTERISTICS
The Following Conditions Apply Unless Otherwise Noted:
MIL
eOM'L
TA
TA
= -55 to +125°e
= 0 to 70 e
0
vee MIN
vee MIN
= 4.5V
= 4.75V
DC ELECTRICAL CHARACTERISTICS
Parameters
VIH
VIL
vee MAX
vee MAX
= 5.5V
= 5.25V
over operating temperature range
Description
Test Conditions
A PORT (AO-A7)
= VIL MAX, T/R = 2.0V
Logical "1" Input Voltage
CD
Logical "0" Input Voltage
= VIL MAX,
TiA' = 2.0V
CD
ilL
Logical "0" Input Current
Input Clamp Voltage
CD
= 2.0V, liN = -12mA
10D
Output/Input 3-State Current
CD
= 2.0V
Logical "0" Output Voltage
lOS
Output Short Circuit Current
IIH
Logical "1" Input Current
II
Input Current at Maximum Input Voltage
VO
VO
VCC-1.15
VCC-0.7
2.7
3.95
-10
Units
Volts
O.B
0.7
VC
VOL
Max
2.0
MIL
= -O.4mA
CI2.. = VIL MAX,
T/R = O.BV
10H = -3.0mA
10L = 12mA
CD = VIL MAX,
T/A = O.BV
COM'L, 10L = 24mA
CD = VIL MAX, T/R = O.BV, VO = OV,
vec = MAX, Note 2
CD = VIL MAX, T/R = 2.0V, VI = 2.7V
CD = 2.0V, VCC = MAX, VI = VCC MAX
CD = VIL MAX, T/R = 2.0V, VI = O.4V
Logical "1" Output Voltage
(Note 1)
COM'L
10H
VOH
Typ
Min
Volts
Volts
0.3
0.4
0.35
0.50
-3B
-75
0.1
BO
/LA
1
mA
Volts
mA
-70
-200
/LA
-0.7
-1.5
Volts
= O.4V
= 4.0V
-200
BO
/LA
B PORT (BO-B7)
VIH
VIL
VOH
VOL
Logical "1" Input Voltage
= VIL MAX, T/R = VIL MAX
COM'L
CD = VIL MAX,
T/R = VIL MAX
MIL
CD
Logical "0" Input Voltage
CD
Logical "1" Output Voltage
lOS
Output Short Circuit Current
Logical "1" Input Current
II
Input Current at Maximum Input Voltage
Logical "0" Input Current
Input Clamp Voltage
10D
Output/Input 3-State Current
VIH
Logical "1" Input Voltage
= VIL MAX,
TiA = 2.0V
IIH
ilL
2.0V
= 20mA
= 4BmA
CD = VIL MAX, T/R = 2.0V, VO = OV,
VCC = MAX, Note 2
CD = VIL MAX, T/R = VIL MAX, VI = 2.7V
CD
Logical "0" Output Voltage
VC
= VIL MAX,
TiA =
= -O.4mA
10H = -5mA
10H = -10mA
10H
Volts
2.0
O.B
0.7
VCC-1.15
VeC-O.B
2.7
3.9
2.4
3.6
Volts
Volts
10L
0.3
0.4
10L
.4
0.5
-50
-150
0.1
BO
/LA
1
mA
-25
= 2.0V, VCC = MAX, VI = VCC MAX
CD = VIL MAX, T/R = VIL MAX, VI = O.4V
CD = 2.0V, liN = -12mA
VO = O.4V
CD = 2.0V
VO = 4.0V
CD
Volts
mA
-70
-200
/LA
-0.7
-1.5
Volts
-200
200
/LA
CONTROL INPUTS CO, TIR
VIL
Logical "0" Input Voltage
IIH
Logical "1" Input Current
II
Input Current at Maximum Input Voltage
= 2.7V
VCC = MAX, VI = VCC MAX
ilL
Logical "0" Input Current
VI
= O.4V
Input Clamp Voltage
liN
= -12mA
VC
Volts
2.0
O.B
COM'L
0.7
MIL
VI
0.5
Volts
20
/LA
1.0
mA
T/R
-0.1
-.25
CD
-0.1
-0.25
-O.B
-1.5
2.0V, VCC
70
100
VINA
100
150
70
100
90
140
mA
Volts
POWER SUPPLY CURRENT
AmZB103
ICC
Power Supply Current
AmZB104
=, VI =
= O.4V,
CD = 2.0V,
CD = VINA
CD
CD
= MAX
= T/R = 2V, VCC = MAX
VI = O.4V, VCC = MAX
= 0.4V, T/R = 2V, VCC = MAX
8-7
mA
AmZ8103· AmZ8104
AmZ8103
AC ELECTRICAL CHARACTERISTICS (vee = 5.0V, T A = 25°C)
Parameters
Description
Typ
Min
Test Conditions
(Note 1)
Max
Units
A PORT DATA/MODE SPECIFICATIONS
tPDHLA
Propagation Delay to a Logical "0" from
B Port to A Port
CD = OAV, T/A = 0.4V (Figure 1)
A1 = 1k, A2 = Sk, C1 = 30pF
8
12
ns
tPDLHA
Propagation Delay to a Logical "1" from
B Port to A Port
CD = OAV, T/A = OAV (Figure 1)
A1 = 1k, A2 = Sk, C1 = 30pF
11
16
ns
tPLZA
Propagation Delay from a Logical "0" to
3-8tate from CD to A Port
BO to 87 = 2AV, TlR = OAV (Figure 3)
83 = 1, AS = 1k, C4 = 1SpF
10
1S
ns
tPHZA
Propagation Delay from a Logical "1" to
3-8tate from CD to A Port
80 to 87 = 0.4V, T/A
83 = 0, AS = 1k, C4
= OAV (Figure 3)
= 1SpF
8
1S
ns
tPZLA
Propagation Delay from 3-8tate to
a Logical "0" from CD to A Port
80 to 87 = 2AV, TiA' = OAV (Figure 3)
83 = 1, AS = 1k, C4 = 30pF
20
30
ns
tPZHA
Propagation De!ay from 3-State to
a Logical "1" from CD to A Port
BO to B7 = O.4V, TiA = O.4V (Figure 3)
83 = 0, AS = Sk, C4 = 30pF
19
30
ns
B PORT DATA/MODE SPECIFICATIONS
= OAV, T/A = 2AV (Figure 1) I
= 100n, A2 = 1k, C1 = 300pF
A1 = 6670, A2 = Sk, C1 = 4SpF
CD = OAV, T/A = 2AV (Figure 1) I
IA1 = 100n, A2 = 1k, C1 = 300pF
A1 = 6670, A2 = Sk, C1 = 4SpF
AO to A7 = 2AV, T/A = 2AV (Figure 3)
83 = 1, AS = 1k, C4 = 1SpF
AO to A7 = OAV, T/A = 2AV (Figure 3)
83 = 0, AS = 1k, C4 = 1SpF
AO to A7 = 2AV, T/A = 2AV (Figure 3)J
183 = 1, AS = 100n, C4 = 300pF
183 = 1, AS = 6670, C4 = 4SpF
AO to A7 = OAV, T/A = 2AV (Figure 3)
83 = 0, AS = 1k, C4 = 300pF
83 = 0, AS = Skn, C4 = 4SpF
CD
tPDHL8
tPDLH8
Propagation Delay to a Logical "0" from
A Port to 8 Port
Propagation Delay to a Logical "1" from
A Port to 8 Port
tPLZB
Propagation Delay from a Logical "0" to
3-8tate from CD to 8 Port
tPHZB
Propagation Delay from A Logical "1" to
3-8tate from CD to 8 Port
tPZLB
Propagation Delay from 3-8tate to
a Logical "0" from CD to 8 Port
tPZHB
Propagation Delay from 3-8tate to
a Logical "1" from CD to 8 Port
I A1
I
I
12
18
7
12
1S
20
9
14
13
18
ns
8
1S
ns
2S
3S
16
2S
22
3S
14
2S
23
3S
ns
22
3S
ns
26
3S
ns
27
3S
ns
ns
ns
ns
ns
TRANSMIT RECEIVE MODE SPECIFICATIONS
tTAL
CD = OAV (Figure 2)
81 = 1, A4 = 100n, C3
Propagation Delay from Transmit Mode
to Aeceive a Logical "0," T/A to A Port
= SpF
= 1, A3 = 1k, C2 = 30pF
CD = OAV (Figure 2)
81 = 0, A4 = 100n, C3 = SpF
82 = 0, A3 = Sk, C2 = 30pF
CD = OAV (Figure 2)
81 = 1, A4 = 100n, C3 = 300pF
82 = 1, A3 = 300n, C2 = SpF
CD = OAV (Figure 2)
81 = 0, A4 = 1k, C3 = 300pF
82 = 0, A3 = 300n, C2 = SpF
82
tTAH
Propagation Delay from Transmit Mode
to Aeceive a Logical "1," T/A to A Port
tATL
Propagation Delay from Aeceive Mode
to Transmit a Logical "0," T/A to 8 Port
tATH
Propagation Delay from Aeceive Mode
to Transmit a Logical "1," TIA to B Port
Notes: 1. All typical values given are for VCC = S.OV and TA = 2SoC.
2. Only one output at a time should be shorted.
FUNCTIONAL TABLE
Inputs
Conditions
Chip Disable
0
0
1
0
1
X
A Port
Out
In
HI-Z
B Port
In
Out
HI-Z
Transmit/Aeceive
8-8
ArnZ8103 • ArnZ8104
ArnZ8104
AC ELECTRICAL CHARACTERISTICS
Parameters
(vee
=
5.0V, T A
Description
=
25°C)
Typ
Test Conditions
Min
(Note 1)
Max
Units
A PORT DATA/MODE SPECIFICATIONS
tPDHLA
Propagation Delay to a Logical "0" from
8 Port to A Port
CD = O.4V, T/R = O.4V (Figure 1)
R1 = 1k, R2 = 5k, C1 = 30pF
14
18
ns
tPDLHA
Propagation Delay to a Logical "1" from
8 Port to A Port
CD =O.4V, T/R = O.4V (Figure 1)
R1 = 1k, R2 = 5k, C1 = 30pF
13
18
ns
tPLZA
Propagation Delay from a Logical "0" to
3-State from CD to A Port
80 to 87 = O.4V, T/R = O.4V (Figure 3)
S3 = 1, R5 = 1k, C4 = 15pF
11
15
ns
tPHZA
Propagation Delay from a Logical "1" to
3-State from CD to A Port
80 to 87 = 2.4V, T/R = O.4V (Figure 3)
S3 = 0, R5 = 1k, C4 = 15pF
8
15
ns
tPZLA
Propagation Delay from 3-State to
a Logical "0" from CD to A Port
80 to 87 = O.4V, T/R = O.4V (Figure 3)
S3 = 1, R5 = 1k, C4 = 30pF
27
35
ns
tPZHA
Propagation Delay from 3-State to
a Logical "1" from CD to A Port
80 to 87 = 2.4V, T/R = O.4V (Figure 3)
S3 = 0, R5 = 5k, C4 = 30pF
19
25
ns
18
23
11
18
16
23
11
.18
8 PORT DATA/MODE SPECIFICATIONS
CD = O.4V, T/R = 2.4V (Figure 1)
tPDHL8
Propagation Delay to Logical "0" from
A Port to 8 Port
IR1
IR1 = 667n, R2 = 5k, C1 = 45pF
CD = O.4V, T/R = 2.4V (Figure 1)
tPDLH8
Propagation Delay to Logical "1" from
A Port to 8 Port
I
= 100n, R2 = 1k, C1 = 300pF
IR1
I
= 100n, R2 = 1k, C1 = 300pF
IR1 = 6670, R2 = 5k, C1 = 45pF
ns
ns
tPLZ8
Propagation Delay from a Logical "0" to
3-State from CD to 8 Port
AO to A7 = O.4V, T/R = 2.4V (Figure 3)
S3 = 1, R5 = 1k, C4 = 15pF
13
18
ns
tPHZ8
Propagation Delay from a Logical "1" to
3-State from CD to 8 Port
AO to A7 = 2.4V, T/R = 2.4V (Figure 3)
S3 = 0, R5 = 1k, C4 = 15pF
8
15
ns
tPZL8
Propagation Delay from 3-State to
a Logical "0" from CD to 8 Port
32
40
16
22
26
35
14
22
30
40
ns
28
40
ns
31
40
ns
28
40
ns
AO to A7 = O.4V, T/R = 2.4V (Figure 3)
IS3 =
II S3 = 1, R5 = 6670, C4 = 45pF
AO to A7 = 2.4V, T/R = 2.4V (Figure 3)
tPZH8
Propagation Delay from 3-State to
a Logical "1" from CD to 8 Port
I
1, R5 = 100n, C4 = 300pF
II S3 = 0, R5 =
I
1k, C4 = 300pF
II S3 = 0, R5 = 5kn, C4 = 45pF
ns
ns
TRANSMIT RECEIVE MODE SPECIFICATIONS
tTRL
tTRH
Propagation Delay from Transmit Mode
to Receive a Logical "0," TiFf to A Port
Propagation Delay from Transmit Mode
to Receive a Logical "1," TiFi to A Port
CD = O.4V (Figure 2)
S1 = 0, R4 = 100n, C3 = 5pF
S2 = 1, R3 = 1k, C2 = 30pF
CD = O.4V (Figure 2)
S1 = 1, R4 = 100n, C3 =5pF
S2 = 0, R3 = 5k, C2 = 30pF
tRTL
Propagation Delay from Receive Mode
to Transmit a Logical "0," T/Ff to 8 Port
CD = O.4V (Figure 2)
S1 = 1, R4 = 100n, C3 = 300pF
S2 = 0, R3 = 300n, C2 = 5pF
tRTH
Propagation Delay from Receive Mode
to Transmit a Logical "1," TiR to 8 Port
CD = O.4V (Figure 2)
S1 = 0, R4 = 1k, C3 = 300pF
S2 = 1, R3 = 300n, C2 = 5pF
Notes: 1. All typical values given are for VCC = 5.0V an~ TA = 25°C.
2. Only one output at a time should be shorted.
DEFINITION OF FUNCTIONAL TERMS
CD
AO-A7 A port inputs/outputs are receiver output drivers when
T/R is LOW and are transmit inputs when TiFf is HIGH.
Chip Disable forces all output drivers into 3-state when
HIGH (same function as active LOW chip select, eS).
TIR
Transmit/Receive direction control determines whether A
port or B port drivers are in 3-state. With T/Ff HIGH A port
is the input and B port is the output. With T/Ff LOW A port
is the output and B port is the input.
80-87 B port inputs/outputs are transmit output drivers when
T/R is HIGH and receiver inputs when T/R' is LOW.
8-9
· AmZ8103 • AmZ8104
SWITCHING TIME WAVEFORMS
AND AC TEST CIRCUITS
Vcc
AmZB103 ~
, - - - - 3.0V
::::.~~------1-.5-V ~;.
r---r,:--.JI..,:""
'''"'
OUTPUT _ _ _ _ _
Bn OR A n .
.."
INPUT
Vcc
OUTPUT
.V
DEVICE
UNDER
TEST
'i
'---
-=
t r • tf < 10ns
10% to 90%
Note: C1 includes test fixture capacitance.
BLI-172
BU-171
Figure 1. Propagation Delay from A Port to B Port
or from B Port to A Port.
_ - - - - - - - - - - _ - - - - - - 3.0V
OV
Vcc
1-.....-----------0 B PORT
APORTn-----------~~
vcc~
Vcc
DEVICE
UNDER
TEST
S2"1
Tiii
BPORT
APORT
tr =tf < 10ns
10% to 90%
Note: C2 and C3 include test fixture capacitance.
BLI·173
BLI-174
Figure 2. Propagation Delay from T/R to A Port or B Port.
, _ _ _ _ _ _ _ _ _ _ _, , - - - - - 3.0V
Vcc
INPg~ ~1'5V
1.SV\/f
"-l '--r--
I L::f"
o~~lE
"'~ §.",
o~i
IF
.,,--oj
'"vITv
------------
1----------- TCK
1--_ _ _ _ _ _ _ _ _ _
TCK/2
1----------_
TCK/4
I-----------WAIT
WAIT
CONTROL
1--------------TIMEouf
CPU STATUS ----------~
n:N~~~ - - - - - - - - - - 1
Bll·16B
8-22
AmZ8133·
AmZ8173
Octal Latches with Three-State Outputs
DISTINCTIVE CHARACTERISTICS
FUNCTIONAL DESCRIPTION
• 18ns max data in to data out
• Non-inverting AmZ8173, inverting AmZ8133
• Three-state outputs interface directly with bus organized
systems
• Hysteresis on latch enable input for improved noise margin
• 100% product assurance screening to MIL-STD-883
requirements
The AmZ8133 and AmZ8173 are octal latches with three-state
outputs for bus organized system applications. The latches appear to be transparent to the data (data changes asynchronously)
when latch enable, G, is HIGH. When G is LOW, the data that
meets the set-up times is latched. Dat~pears on the bus when
the output enable, OE, is LOW. When OE is HIGH the bus output
is in the high-impedance state.
The AmZ8173 has non-inverted data inputs while the AmZ8133
is inverting.
LOGIC DIAGRAM
AmZ8173
LATCH
ENABLE
Inputs Do through D7 are inverted on the AmZ8133.
CONNECTION DIAGRAMS
Top Views
BLI-041
LOGIC SYMBOL
°0
°1
°2
6
13
14
17
16
°3
°4
05
°6
D)
11
AmZ6173
DE
BE
Yo
DO
°1
"1
Y2
°2
Vee
Y)
D7 DB
Y6
Y5
D5 54
°3
Y3 GND
Y4
Yo
Y1
Y2
Y3
Y4
Y5
Y6
Y)
9
12
15
16
19
G
Vec
GND
Note: Pin 1 is marked for orientation.
=
=
Pin 20
Pin 10
Inputs Do through D7 are inverted on the AmZ8133.
BlI-042
8-23
BLI-043
AmZ8133· AmZ8173
. AmZ8133 • AmZ8173
ELECTRICAL CHARACTERISTICS
The Following Conditions Apply Unless Otherwise Specified:
COM'L
T A; o°c to +70°C
VCC; 5.0V ±5%
MIN.;4.75V
MAX.; 5.25V
MIL
TA;-55°Cto+125°C
VCC; 5.0V ±10%
MIN. ; 4.50V
MAX. ; 5.50 V
DC CHARACTERISTICS OVER OPERATING RANGE
Parameters
Description
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
Typ.
Test Conditions
VCC
VIN
VCC
VIN
= MIN.
= VIH or
VIL
= MIN.
= VIH or
VIL
(Note 1)
= -1.0mA
10H = -2.6mA
10H
I
MIL
I COM'L
Min.
(Note 2)
2.4
3.4
2.4
3.4
Max.
Units
Volts
10L
= 12mA
0.4
10L
= 24mA
0.5
Volts
VIH
Input HIGH Level
Guaranteed input logical HIGH
voltage for all inputs
VIL
I nput LOW Level
Guaranteed input logical LOW
voltage for all inputs
VI
Input Clamp Voltage
VCC
= MIN.,IIN = -18mA
-1.5
Volts
IlL
Input LOW Current
VCC
= MAX.,
VIN
= OAV
-0.4
mA
IIH
Input HIGH Current
VCC
= MAX.,
VIN
= 2.7V
20
/lA
II
Input HIGH Current
VCC
= MAX.,
VIN
= 7.0V
0.1
mA
102
Off-State ( High-I mpedance)
Output Current
VCC
= MAX.
ISC
Output Short Circuit Current
(Note 3)
VCC
= MAX.
ICC
Power Supply Current
(Note 4)
VCC
= MAX.
Note$: 1.
2.
3.
4.
I
Vo
I
Vo
Volts
2.0
I
MIL
0.7
I
COM'L
0.8
= OAV
= 2AV
Volts
-20
20
-30
24
/lA
-85
mA
40
mA
For .cond.iti~ns shown as MI N. or MAoX., use .the appropri~te value s~ecified under Electrical Characteristics for the applicable device type.
TVPlcal limits are at VCC = 5.0 V, 25 C ambient and maximum loading.
Not more than one output should be shorted at a time. Duration of the short circuit test should not exceed one second.
I nputs grounded; outputs open.
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
Supply Voltage to Ground Potential Continuous
DC Voltage Applied to Outputs for High Output State
DC Input Voltage
DC Output Current, Into Outputs
DC Input Current
8-24
-0.5V to +7.0V
-0.5V to +Vcc max.
-0.5V to +7.0V
30mA
-30 mA to +5.0 mA
AmZ81a3 • AmZ8173
AmZ8133
SWITCHING CHARACTERISTLCS
(TA = +25°C, Vee = 5.0V)
Parameters
Typ
Max
Units
Enable to Output
20
18
30
30
ns
Data Input to Output
13
15
20
23
ns
Min
Description
tplH
tpHl
tplH
tpHl
I
3
0
ns
LOW Data to Enable
13
7
ns
tpw
Enable Pulse Width
15
tZH
ts(H)
HIGH Data to Enable
ts(L)
LOW Data to Enable
th(H)
HIGH Data to Enable
th(L)
-OEto Yi
ns
-OEto Yi
20
25
ns
tlZ
AmZ8133
SWITCHING CHARACTERISTICS
OVER OPERATING RANGE
Parameters
tPl.H
Description
COM'L
MIL
T A = O°C to +70°C
VCC = 5.0V ±5%
T A = -55°C to +125°C
VCC = 5.0V ±to%
Min.
Enable to Output
tpHL
tPLH
Data Input to Output
tpHL
Max.
Min.
40
35
40
20
25
30
21
HIGH Data to Enable
5
5
ts(L)
LOW Data to Enable
0
th(H)
HIGH Data to Enable
14
0
15
th(L)
LOW Data to Enable
9
10
tpw
Enable Pulse Width
17
20
tZL
tHZ
tLZ
OE to Yi
OE to Yi
Max.
35
ts(H)
tZH
Cl. = 45pF
RL,. = 667fl
I
ns
28
36
tZl
tHz
Test t::onditions
C l. = 5pF
RL = 667fl
Units
T,,:st Conditions
ns
ns
j
ns
CL = 45pF
RL
=
667.11
ns
ns
28
28
36
36
36
36
33
33
ns
m
ns
:
"AC performance over the operating temperature range is guaranteed by testing defined in Group A, Subgroup 9.
LOW-POWER SCHOTTKY INPUT/OUTPUT
CURRENT INTERFACE CONDITIONS
PNP
_
DRIVEN INPUTS G, DE
VCC--------------~~---L----------~----
1.6kn
NOM.
J
Note: Actual current flow direction shown,
8-25
BLI·044
AmZ8133 • AmZ8173
AmZ8173
SWITCHING CHARACTERISTICS
(TA = 25°C, Vee: = 5.0V)
Parameters
Description
tplH
Min
Typ
Max
20
30
18
30
Enable to Output
tpHl
tplH
Data Input to Output
tpHl
ts(H)
HIGH Data to Enable
0
ts(L)
LOW Data to Enable
0
th(H)
HIGH Data to Enable
10
th(L)
LOW Data to Enable
10
Enable Pulse Width
15
°tpw
tZH
10
18
12
18
tpLH
20
COM'L
MIL
TA = O°C to +70°C
VCC = 5.0V ±5%
TA = -55°C.to +125°C
VCC = 5.0V ±10%
Enable to Output
tpHL
tslH)
Dat;3 Input to Output
Max.
Min.
35
35
40
19
20
20
25
0
0
LOW Data to Enable
HIGH Data to Enable
0
11
0
12
thl L )
LOW Data to Enable
15
17
tpw
Enable Pulse Width
17
20
tslL)
thl H)
tZH
tZL
tHZ
tLZ
OE t"Yi
OE t"Yi
Max.
40
HIGH Data to Enable
28
Test Conditions
ns
ns
CL = 45pF
RL = 667.11
ns
ns
*AC performance over the operating temperature range is guaranteed by testing defined in Group A, Subgroup 9.
8-26
Units
ns
28
36
36
36
36
33
33
Cl = 5pF
Rl = 6670
ns
25
tpHL
tpLH
ns
36
Min.
C l = 45pF
Rl = 66711
ns
OEto Yi
Description
ns
28
tlZ
Parameters
ns
ns
OEto Yi
AmZ8173
SWITCHING CHARACTERISTICS
OVER OPERATING RANGE
Test Conditions
ns
tZl
tHZ
Units
ns
ns
CL - 5pF
RL=667n
AmZ8133· AmZ8173
Metallization and Pad Layouts
AmZ8173
AmZ8133
Of
20
DE
Vee
20
Vee
Yo
19
Y7
Yo
2
19
Y7
Do
18
07
0;;
3
18
0;
01
17
06
0;
4
17
~
Y1
16
Y6
Y1
5
16
Y6
Y2
15
Ys
Y2
6
15
Ys
O2
14
05
0;
7
14
OS
03
13
04
OJ
8
13
~
Y3
12
Y4
Y3
9
12
Y4
11
G
GNO
10
11
G
GNO
10
DIE SIZE 0.073" X 0.089"
FUNCTION TABLES
DEFINITION OF FUNCTIONAL TERMS
AmZ8173
Inputs
OE G
H
x
Internal
ArnZ8173
Di
°i
Outputs
Vi
X
X
Z
Function
Dj
The latch data inputs.
G
The latch enable input. The latches are transparent when G
is HIGH. Input data is latched on the HIGH-to-LOW transition.
Hi-Z
L
H
L
H
L
L
H
H
L
H
L
L
X
NC
NC
Latched
Function
Transparent
Vj
The three-state latch outputs.
OE
The output enable control. When OE is LOW, the outputs
Vj are enabled. When OE is HIGH, the outputs Vj are-in
the high-impedance (off) state.
ArnZ8133
Inputs
OE G
Di
°i
Outputs
Vi
H
x
X
X
Z
L
H
L
H
H
L
H
H
L
L
L
L
X
NC
NC
Internal
H = HIGH
L = LOW
ArnZ8133
Hi-Z
OJ
The latch inverting data inputs.
G
The latch enable input. The latches are transparent when G
is HIGH. Input data is latched on the HIGH-to-LOWtransition.
Vj
The three-state latch outputs.
Transparent
Latched
OE The output enable control. When OE is LOW, the inverted
NC = No Change
Z = High Impedance
outputs Vj are enabled. When OE is HIGH, the outputs Vj
are in the high-impedance (off) state.
X = Don't Care
8-27
AmZ8136
Eight-Bit Decoder With Control Storage
DISTINCTIVE CHARACTERISTICS
FUNCTIONAL DESCRIPTION
•
•
•
•
•
•
•
The AmZ8136 is an eight-bit decoder with control storage. It
provides a conventional 8-bit decoder function with two enable
inputs which may also be used for data input. This can be used to
implement a demultiplexer function. In addition, the "exclusive-OR" gates provide polarity control of the selected output.
The 3-state outputs are enabled by an active LOW input on the
output enable, OE.
8-bit decoder/demultiplexer with control storage
3-state outputs
Common clock enable
Common clear
Polarity control
Advanced Low Power Schottky Process
100% product assurance screening to MIL-STD-883
requirements
The three control bits representing the output selection and the
single bit polarity control are stored in "D" type flip-flops. These
flip-flops have Clear, Clock, and Clock Enable functions provided.
The G1 and G2 inputs provide either polarity for input control or
data.
LOGIC DIAGRAM
8-Bit Decoder/Demultiplexer with Control Storage
BU-l90
CONNECTION DIAGRAM
LOGIC SYMBOL
DE
Yo
19
01
Yl
11
18
G2
Y2
12
CE
C
POL
DE
Y3
13
Y4
14
CLR
Y5
15
CP
Y6
16
Y7
17
Yo GND
Note: Pin 1 is marked for orientation.
BLI-191
BLI-192
8-28
A
B
C POL
4
5
6
7
Vee = 20
GND = 10
ArnZ8136
ELECTRICAL CHARACTERISTICS
The Following Conditions Apply Unless Otherwise Specified:
COM'L
T A = OOC to +70°C
MIL
TA
= _55°e
to +125°C
Vee = 5.0V ±5%
MIN.
= 5.0V
MIN.
Vee
±10%
= 4.75V
= 4.50V
= 5.25V
= 5.50V
MAX.
MAX.
DC CHARACTERISTICS OVER OPERATING RANGE
VOH
Output HIGH Voltage
VOL
Output lOW Voltage
Typ.
Test Conditions
Description
Parameters
(Note 1)
= -2.6mA, COM'l
10H = -1.0mA, Mil
VCC = MIN.
VIN = VIH or Vil
10H
VCC = MIN.
VIN = VIH or Vil
10l
(Note2)
2.4
3.2
2.4
3.4
= 24mA, COM'l
Max.
Units
Volts
0.4
0.5
0.35
0.4
Volts
10l = 12mA, Mil
VIH
Input HIGH level
Guaranteed input logical HIGH
voltage for all inputs
Vil
Input lOW level
Guaranteed input logical lOW
voltage for all inputs
VI
Input Clamp Voltage
VCC = MIN., liN = -18mA
III
Input lOW Current
VCC
IlH
Input HIGH Current
II
Input HIGH Current
VCC
10
Off·State (High-Impedance)
Output Current
VCC = MAX.
ISC
Output Short Circuit Current
(Note 3)
VCC
= MAX.
ICC
Power Supply Current
(Note 4)
VCC
= MAX.
Notes: 1.
2.
3.
4.
Min.
Volts
2.0
I
I
Mil
0.7
COM'l
0.8
Volts
-1.5
Volts
-0.4
mA
VCC = MAX., VIN = 2.7V
20
J.l.A
= MAX., VIN = 7.0V
0.1
mA
= MAX., VIN = 0.4 V
VO=O.4V
-20
Vo = 2.4V
20
-15
37
J.l.A
-85
mA
56
mA
For conditions shown as MIN. or MAX., use the appropriate value specified under Electrical Characteristics for the applicable device type.
Typical limits are at VCC = 5.0V, 25°C ambient and maximum loading.
Not more than one output should be shorted at a time. Duration of the short circuit test should not exceed one second.
Test Conditions: A = B = C = G1 = G2 = OE = CE = GND; ClK = ClR = POL = 4.5V.
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
-O.5V to +7.0V
Supply Voltage to Ground Potential Continuous
DC Voltage Applied to Outputs for High Output State
-O.5V to +V CC max.
-O.5V to +7.0V
DC Input Voltage
30mA
DC Output Current, Into Outputs
-30mA to +5.0mA
DC Input Current
8-29
AmZ8136
SWITCHING CHARACTERISTICS
(TA = + 25°C, Vee = 5.0V)
Typ.
Max.
Units
G 1 to Yo - Y7
17
23
25
34
ns
tpLH
tpHL
G2 to Yo - Y7
20
26
30
39
ns
tpLH
tpHL
CPtoYO -Y7
24
30
36
45
ns
tpLH
tpHL
CLR to Yo - Y7
24
31
36
46
ns
ts
th
CE to CP
25
0
ns
ts
th
A, B, C, POL to CP
15
0
ns
tHZ
tLZ
OEtoYO -Y7
9
11
14
17
ns
tZH
tZL
OE to Yo - Y7
15
16
22
24
ns
ts
Set-up Time, Clear Recovery to CP
tpw
Pulse Width
Parameters
tpLH
tpLH
Min.
Description
I
I
15
Clear
15
C L = 45pF
RL = 6670
CL = 5pF
RL = 6670
C L = 45pF
RL = 6670
ns
20
Clock
Test Conditions
ns
SWITCHING CHARACTERISTICS
OVER OPERATING RANGE·
COM'L
MIL
TA
O°C to +70°C
V CC
5.0V ±5%
TA
_55°C to +125°C
VCC
5.0V ±10%
=
Parameters
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
ts
th
ts
Description
<31 to Yo -
Y7
G2 toY O -Y7
CPtoYO -Y7
CLR to Yo - Y7
CE to CP
A, B, C, POL to CP
th
tHZ
tLZ
tZH
tZL
Min.
tpw
Pulse Width
I
I
Min.
=
Max.
29
31
39
42
34
37
44
48
40
42
51
55
47
54
58
66
30
0
0
17
20
0
0
OE to Yo - Y7
Set-up Time, Clear Recovery to CP
Max.
27
OE to Yo - Y7
ts
=
=
18
34
25
27
28
30
Clock
17
20
Clear
15
15
*AC performance over the operating temperature range is guaranteed by testing defined in Group A, Subgroup 9.
8-30
ns
ns
ns
C L = 45pF
RL = 6670
ns
ns
17
25
Test Conditions
ns
27
23
Units
ns
CL = 5.OpF
RL = 6670
ns
ns
ns
CL = 5.OpF
RL = 6670
AmZ8136
FUNCTION TABLE
Internal
Registers
Inputs
Mode
C B A POL CE ClR G* OE CP
Clear
X X X
X X X
Hold
Select
Output
Disable
NC
X
X
X
X
L
L
L
L
H
X X X
X
H
H
L
L
L
H
L
H
L
L H
H
L
L H L
H
L
L H H
H
L
H
H
L
H L
L
H
L
H
H
L
H L H
H
L
H
H
L
Oc
Three-State Outputs
YO Y, Y2 Y3 Y4 Y5 Ye
OB OA OPOl
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
H
NC
L
t
NC
NC
NC NC NC NC NC NC NC NC
H
L
t
L
L
L
H
H
L
L
L
L
L
L
H
H
L
L
L
H
H
L
H
L
L
L
L
L
L
H
H
L
t
t
t
t
t
t
t
L
H
L
H
L
L
H
L
L
L
L
L
L
H H L
H
L
H
H
L
H H H
H
L
H
H
L
NC NC
L
L
H
H
H
L
L
L
H
L
L
L
H
L
L
H
L
L
L
L
H
L
L
L
H
L
H
H
L
L
L
L
L
H
L
L
H
H
L
H
L
L
L
L
L
L
H
L
H
H
H
H
L
L
L
L
L
L
L
H
L
L
L
L
L
H
H
L
L
L
L
L
H
H
H
H
H
H
H
L H
L
L
H
H
L
t
t
L
L
L
L
H
L
H
L
H
H
H
H
H
H
L
H L
L
L
H
H
L
1
L
H
L
L
H
H
L
H
H
H
H
H
L H H
L
L
H
H
L
t
L
H
H
L
H
H
H
L
H
H
H
H
H L
L
L
H
H
L
H
L
L
L
H
H
H
H
L
H
H
H
H
L
H
L
H
H
H
H
H
L
H
H
H
H
L
L
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
H
H
H
L
X
X
X
X
H
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
NC
NC
NC
Z
Z
Z
Z
Z
Z
Z
Z
H H H
L
L
H
H
L
X X X
X X X
H
L
H
L
L
t
t
t
t
t
L
L
H
L
L
t
X
X
X X X
X
X
X
X
H
X
NC
L
H L H
L
L
H
H
L
H H L
L
L
H
H
L
= No Change
X
= Don't Care
Z
= High-Impedance
*
L
L
H
H
CLEAR - When the CLEAR input is LOW, the control
register outputs (OA, 0B, Oc, Opod are set LOW
regardless of any other inputs.
CLOCK - Enters data into the control register on the
LOW-to-HIGH transition.
CE
CLOCK ENABLE - Allows data to enter the control
register when CE is LOW. When CE is HIGH, the OJ
outputs do not change state, regardless of data or
clock input transitions.
POL
Input to the control register bit used for determining the polarity of the selected output.
G1
Active LOW part ofthe expression G = G1 G2 [or G =
(<31 ) G2 ] where Gis either data inputfortheselected
Yn or is used as an input enable.
G2
Active HIGH part of the expression G = G1 G2 .
. . - - - - - - - - - 20
=
G
L
H
L
L
Vcc
, - - - - - - 19
G1
CE
1iiH;;+--- 18
G2
c.;;;+-- 17
Y7
R i i i i i + - - 16
Y6
A
c.;&+-POL
15
Y5
c - I ; H - - 14
Y4
;';;1+---
GND
The three-state outputs. When active (OE = LOW),
one of eight outputs is selected by the code stored in
the control register, with the polarity of all eight
determined by the bit stored in the POL flip-flop of
the control register. The selected output can further
be controlled by G according to the expression
YSELECTED
G
CP
A,B,C Inputs to the control register which are entered on
the LOW-to-HIGH clock transition if CE is LOW.
OE
L
H
L
H
METALLIZATION AND PAD LAYOUT
CP
Yn
G, G2
t = Low-to-High Transition
DEFINITION OF TERMS
CLR
Y7
X
X
10 - - - - - - - '
' - - - - - - - - 12
Y2
Y1
DIE SIZE 0.084" X 0.099"
8-31
Y3
' - - - - - - - - 11
EEl 0POL'
OUTPUT ENABLE. When OE is HIGH the Y n outputs
are in the high impedance state; when OE is LOW
the Y n's are in their active state as determined by the
other control logic. The OE input affects the Y n output buffers only and has no effect on the control
register or any other logic.
13
AmZ8140·
AmZ8144
Octal Three-State Buffers
FUNCTIONAL DESCRIPTION
DISTINCTIVE CHARACTERISTICS
•
•
•
•
•
•
•
•
The AmZ8140 and AmZ8144 are octal buffers fabricated using
advanced low-power Schottky technology. The 20-pin package
provides improved printed circuit board density for use in memory
address and clock driver applications.
Three-state outputs drive bus lines directly
Hysteresis at inputs inproves noise margin
PNP inputs reduce DC loading on bus lines
Data-to-output propagation delay times - 16ns MAX
Enable-to-output - 20ns MAX
48mA output current
20-pin hermetic and molded DIP packages
100% product assurance testing to MIL-STD-883
requirements
Three-state outputs are provided to drive bus lines directly. The
AmZ8140 and AmZ8144 are specified at 48mA and 24mA output
sink current. Four buffers are enabled from one common line and
the other four from a second enable line. The AmZ8140 and
AmZ8144 enables are of similar polarity for use as a unidirectional
buffer in which both halves are enabled simultaneously.
Improved noise rejection and high fan-out are provided by input
hysteresis and low current PNP inputs.
LOGIC DIAGRAMS
AmZ8140
AmZ8144
DO
YO
04
Y4
01
Y1
05
Vs
Y4
INPUTS
0
OE
02
'(2
06
'(6
03
'(3
07
Y7
OE03
OUTPUT
X
Z
L
H
L
L
L
H
Dj
Y
Y6
H
X
Z
L
H
H
Y7
L
L
L
<5E47
Note: All devices have input hysteresis.
BLI·l94
CONNECTION DIAGRAMS
LOGIC SYMBOLS
Top Views
DO
vee
i:nm'
OE03
DO
11
13
15
vee
Vo
Y7
YO
01
07"
01
07
Y6
V1
Y6
Y1
02
06
02
06
YS
Y2
YS
Y2
19
03
05
03
05
Y3
Y4
Y3
BLI-197
18
16
14
12
11
13
15
06
AmZ8144
GNO
04
GNO
17
OE47
'17
Y4
OUTPUT
OE
Y
H
BLI-193
Dm
INPUTS
YS
17
07
OE47
19
04
BLI-l98
BU-l95
Note: Pin 1 is marked for orientation.
vee
BU-l96
18
8-32
16
14
12
= Pin 20
GND = Pin 10
AmZ8140· AmZ8144
ELECTRICAL CHARACTERISTICS
The Following Conditions Apply Unless Otherwise Specified:
COM'L
MIL
TA
TA
= 0 to 70°C
= -55 to +125°C
VCC
VCC
= 5.0V
= 5.0V
(MIN
(MIN
±5%
±10%
= 4.75V
= 4.50V
MAX
MAX
= 5.25V)
= 5.50V)
DC CHARACTERISTICS OVER OPERATING RANGE
Typ
Parameters
VOH
Test Conditions (Note 1)
Description
VCC = MIN, VIH = 2.0V
IOH = -3.0mA, VIL = VIL MAX
MIL, IOH = -12mA
VCC = MIN,
High-Level Output Voltage
VIL = 0.5V
COM'L, IOH = -15mA
(Note 2)
2.4
3.4
2.0
0.25
0.4
0.35
0.5
VIH
High-Level Input Voltage
Guaranteed input logical HIGH
voltage for all inputs
VIL
Low-Level Input Voltage
VIK
Input Clamp Voltage
VCC = MIN, II = -18mA
Hysteresis (VT + - VT - )
VCC = MIN
COM'L, IOL = 48mA
IOZL
Off-State Output Current,
Low-Level Voltage Applied
II
Input Current at Maximum
Input Voltage
VCC = MAX, VI = 7.0V
IIH
High-Level Input Current, Any Input
ilL
Low-Level Input Current
ISC
Short Circuit Output Current (Note 3)
VCC = MAX
ICC
AmZ8140
Supply Current
VCC = MAX
Outputs Open
ICC
Volts
2.0
0.2
IOZH
AmZ8144
Volts
0.55
I COM'L
I MIL
Off-State Output Current,
High-Level Voltage Applied
Units
Volts
2.0
AIiIOL = 24mA
VCC = MIN
VCC = MAX
VIH = 2.0V
VIL = VIL MAX
Max
AIiIOL = 12mA
Low-Level Output Voltage
VOL
Min
0.8
0.7
Volts
-1.5
Volts
Volts
0.4
VO = 2.7V
20
VO = O.4V
-20
/LA
0.1
mA
VCC = MAX, VIH = 2.7V
20
/LA
VCC = MAX, VIL = OAV
-200
/LA
-225
mA
-50
All Outputs HIGH
13
23
All Outputs LOW
26
44
Outputs at Hi-Z
29
50
All Outputs HIGH
13
23
All Outputs LOW
27
46
Outputs at Hi-Z
32
54
rT)A
mA
Notes: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
2. All typical values are VCC = 5.0V, T A = 25°C.
3. Not more than one output should be shorted at a time, and duration of the short-circuits should not exceed one second.
MAXIMUM RATINGS
above which the useful life may be impaired
Storage Temperature
-65°C to +150°C
Temperature (Ambient) Under Bias
_55°C to +125°C
Supply Voltage to Ground Potential
-O.5V to +7.0V
DC Voltage Applied to Outputs for HIGH Output State
DC Input Voltage
-------------------------------
____________ -O.5V to +VCC max.
-O.5V to +7.0V
150mA
DC Output Current
-30mA to +5.0mA
DC Input Current
8-33
AmZ8140· AmZ8144
AmZ8140· AmZ8144
SWITCHING CHARACTERISTICS
(TA = +25°e, vee = 5.0V)
AmZ8144
AmZ8140
Typ
Max
tPLH
Propagation Delay Time,
Low-to-High-Level Output
6
tPHL
Propagation· Delay Time,
High-to-Low-Level Output
tPZL
tPZH
tPLZ
tPHZ
Parameters
Min
Min
Test Conditions
Typ
Max
Units
10
9
13
ns
9
13
11
16
ns
Output Enable Time to Low Level
13
20
13
20
ns
Output Enable Time to High Level
8
14
8
14
ns
Output Disable Time from Low Level
13
20
13
20
ns
Output Disable Time from High Level
12
18
12
18
ns
Description
(Notes 1-5)
CL"= 45pF
RL = 667fl
CL
RL
= 5.0pF
= 667fl
AmZ8140
SWITCHING CHARACTERISTICS
OVER OPERATING RANGE·
MIL
COM'L
TA
VCC
Parameters
Description
= 0 to 70°C
= 5.0V ±5%
Min
Max
=
TA
-55 to +125°C
VCC
5.0V ±10%
=
Min
Max
Units
Propagation Delay Time,
Low-to-High-Level Output
13
15
ns
Propagation Delay Time,
High-to-Low-Level Output
15
18
ns
tPZL
Output Enable Time to Low Level
25
30
ns
tPZH
Output Enable Time to High Level
18
21
ns
tPLH
r--tPHL
tPLZ
Output Disable Time from Low Level
25
30
ns
tPHZ
Output Disable Time from High Level
21
25
ns
Test Conditions
CL
RL
= 45pF
= 66m
CL
RL
= 5.0pF
= 66m
AmZ8144
SWITCHING CHARACTERISTICS
OVER OPERATING RANGE·
COM'L
MIL
TA
VCC
= 0 to 70°C
= 5.0V ±5%
Min
Max
=
TA
-55 to +125°C
VCC
5.0V ±10%
=
Max
Units
15
16
ns
Propagation Delay Time,
High-to-Low-Level Output
18
20
ns
tPZL
Output Enable Time to Low Level
25
30
ns
tPZH
Output Enable Time to High Level
18
21
ns
tPLZ
Output Disable Time from Low Level
25
30
ns
tPHZ
Output Disable Time from High Level
21
25
ns
Parameters
Description
tPLH
Propagation Delay Time,
Low-to-High-Level Output
tPHL
Min
·AC performance over the operating temperature range is guaranteed by testing defined in Group A, Subgroup 9.
8-34
Test Conditions
CL
RL
= 45pF
= 66m
CL = 5.0pF
RL = 667fl
AmZ8140 • AmZ8144
APPLICATION
AO-A7
A8-A15
AmZ8002
AD
00-07
AS
R/W
BUSAK
08-015
BLI-l99
METALLIZATION AND PAD LAYOUTS
AmZ8144
AmZ8140
20
OE03
DO
Y7
vee
20
vee
19
OE47
OE03
19
OE47
18
00
Y7
18
17
YO
07
17
YO
07
01
Y6
16
15
Y1
06
01
Y6
16
15
Y1
06
02
Y5
14
13
Y2
05
02
Y5
14
13
Y2
05
12
Y3
11
04
03
03
Y4
GNO
10
12
Y3
Y4
11
04
GNO
10
DIE SIZE 0.060" X 0.103"
DIE SIZE 0.060" X 0.103"
8-35
AmZ8148
Chip Select Address Decoder With Acknowledge
DISTINCTIVE CHARACTERISTICS
FUNCTIONAL DESCRIPTION
• One-ai-Eight Decoder provides eight chip select outputs
• Acknowledge output responds to enables and acknowledge
input command
• Open-collector Acknowledge output for wired-OR application
• Inverting and non-inverting enable inputs for upper address
decoding
• 100% product assurance screening to MIL-STD-883
requirements
The AmZ8148 Address Decoder combines a three-line to eightline decoder with four qualifying enable inputs (two active
HIGH and two active LOW) and the acknowledge output required for "ready" or "wait state" control of all popular MOS
microprocessors.
The acknowledge output, ACK, is active LOW and responds to
the combination of all enables and an acknowledge active, input
command.
The eight chip select outputs are individually active LOW in
response to the combination of all enables active and the corresponding 3-bit input code at the S inputs.
The AmZ8148 is intended for chip select decoding in small,
medium or large systems where multiple chip selects must be
generated and address space must be allocated conservatively.
LOGIC DIAGRAM
So
ENABLE
INPUTS
1:~ ------1
E3
E4
Y1
BLI-045
CONNECTION DIAGRAM
Top View
LOGIC SYMBOL
AmZ8148
Ao
A1
Vo V1 V2 V3 V4 Vs V6 V7
Note: Pin 1 is marked for orientation.
BLI-046
8-36
BLI-047
AmZ8148
ELECTRICAL CHARACTERISTICS
The Following Conditions Apply Unless Otherwise Specified:
COM'L
MIL
TA
TA
= O°C to +70°C
= -55°C to +125°C
Vee
Vee
= 5.0V
= 5.0V
±5%
±10%
(MIN.
(MIN.
= 4.75V
= 4.50V
MAX.
MAX.
= 5.25V)
= 5.50V)
DC CHARACTERISTICS OVER OPERATING RANGE
Typ.
Parameters
Description
Test Conditions (Note 1)
VOH
Output HIGH Voltage
Vee = MIN.
VIN = V IH or V IL
VOL
Output LOW Voltage
Vee = MIN.
V IN = VIH or VIL
VIH
Input HIGH Level
Guaranteed input logical HIGH
voltage for all inputs
VIL
Input LOW Level
Guaranteed input logical LOW
voltage for all inputs
VI
Input Clamp Voltage
Vee
IlL
Input LOW Current
Vee
IIH
Input HIGH Current
Vee
II
Input HIGH Current
Vee
= MIN., liN = -18mA
= MAX., VIN = O.4V
= MAX., VIN = 2.7V
= MAX., VIN = 7.0V
Ise
Output Short Circuit Current
(Note 3)
Vee
= MAX.
Power Supply Current (Note 4)
Vee
= MAX.
lee
Notes: 1.
2.
3.
4.
IOH
= - 44OILA
IOL
= 4.0mA
= 8.0mA
IOL
Min.
(Note 2)
2.4
3.4
Max.
Volts
0.4
Volts
0.45
Volts
2.0
I MIL
I
Units
0.7
Volts
0.8
COM'L
-15
15
-1.5
Volts
-0.36
mA
20
p.A
0.1
mA
-85
mA
20
mA
For conditions shown as MIN. or MAX., use the appropriate value specified under Electrical Characteristics for the applicable device type.
Typical limits are at Vee = 5.0V, 25°C ambient and maximum loading.
Not more than one output should be shorted at a time. Duration of the short circuit test should not exceed one second.
TEST CONDITIONS: So = S1 = S2 = E1 = E2 = GND: Ao = A1 = E3 = E4 = 4.5V.
MAXIMUM RATINGS (Above whieh the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
-O.5V to + 7.0V
Supply Voltage to Ground Potential Continuous
DC Voltage Applied to Outputs for High Output State
-O.5V to +Vee max.
DC Input Voltage
-O.5V to + 7.0V
DC Output Current Into Outputs
30mA
DC Input Current
-30mA to +5.0mA
8-37
ArnZ8148
SWITCHING CHARACTERISTICS
(TA = +25°C, Vee = 5.0V)
Typ.
Max.
Units
14
19
20
27
ns
Si to Yi (Two Level Delay)
13
15
18
21
ns
E 1 • E2 to Yi
13
16
18
23
ns
E3. E4 to Yi
15
19
21
27
ns
Ai to ACK
25
16
35
22
ns
E 1 • E2 to ACK
29
25
40
ns
35
ns
E3. E4 to ACK
29
25
40
35
ns
Parameters
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
Description
Si to
Min.
Vi (Three Level Delay)
tpHL
Test Conditions
ns
ns
ns
ns
CL
RL
= 15pF
= 2.0k!l
ns
ns
SWITCHING CHARACTERISTICS
OVER OPERATING RANGE
MIL
COM'L
=
TA
O°C to +70°C
VCC
5.0V ±5%
Parameters
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
Description
=
TA
= _55°C to +125°C
VCC = 5.0V ±10%
Max.
Units
Si to Yi (Three Level Delay)
27
34
30
36
ns
Si to Yi (Two Level Delay)
23
28
25
31
ns
E1. E2 to Yi
23
29
25
31
ns
E3. E4 to Yi
27
34
28
36
ns
Ai to ACK
45
31
45
35
E1• E2 toACK
45
39
45
40
ns
E3. E4 to ACK
45
39
45
40
ns
Min.
Max.
8-38
Min.
Test Conditions
ns
ns
ns
ns
ns
ns
ns
ns
CL = 50pF
RL = 2.0k!l
AmZ8148
DEFINITION OF FUNCTIONAL TERMS
METALLIZATION AND PAD LAYOUT
So, S1, S2 Three-line to eight-line chip select decoder inputs.
E1 , E2
The active LOW enable inputs. A HIGH on either the
E1 or E2 input forces all decoded functions to be
disabled, and forces ACK HIGH.
r-----20
YJ
Y4
A,
17
S2
Ao
16
E,
15
E2
14
EJ
The active HIGH enable inputs. A LOW on either E3 or
E4 inputs forces all the decoded functions to be inhibited, and forces ACK HIGH.
The acknowledge inputs, Ao and A1 , are active LOW
inputs used as conditions for an active LOW output at
the acknowledge, ACK, output.
SO
The acknowledge output, ACK, is an active LOW
output used to signal the microprocessor that specific
devices have been selected. ACK goes LOW only
when E1 and E2 are. LOW, E3 and E4 are HIGH and Ao
or A1 is LOW.
Vee
, - - - - - - 19
18
S,
The eight active LOW chip select outputs.
Ys
Y6
GND
10---------'
13
E4
'------12
'-------11
Yo
'(7
DIE SIZE: 0.081" X 0.096"
LOW-POWER SCHOTTKY INPUT/OUTPUT
CURRENT INTERFACE CONDITIONS
vee---------+----r--------~----~-----------------
Note: Actual current flow direction shown.
BLI-048
8-39
AmZ8148
APPLICATION DIAGRAM
Ao
Ao
A,
J
A3
;
A4
i
AS
ADDRESS
PORT
A
A,
A2
AmB2SSA
~o
~0
(
A6
~
A7
'(
AS
(
Ag
(
~
~
A,O
A"
A'2
AD
\VA
(
A14
(
~
A,S
' - - SO
YO
' - - - S,
Y,
S2
'(2
E,
'(3 f - -
E4
Y4
Ys
Y6 I--
1 - . - E2
{J:~ rr=~
I
~I
ACK
PORT
A
A,
TO
OTHER
CHIP
SELECT
INPUTS
AmB2SSA
~O
~0
PORT
B
7
I--
'(7
A
CS
AO
r--r--
E3
BLOCK
ENABLE
PORT
C
,
AD
\VA
IJOW
{
~
~
¢=>
t-
IJOR
CONTROL
<=>
I
A'3
DATA
PORT
B
7
~
PORT
C
CS
~
J
ACK
BLI-049
FUNCTION TABLES
CHIP SELECT OUTPUTS Y i
52
S1
50
E1
E2
E3
E4
YO
Y1
Y2
Y3
Y4
Ys
Y6
Y7
L
L
L
L
L
H
H
L
H
H
H
H
H
H
H
L
L
H
L
L
H
H
H
L
H
H
H
H
H
H
L
H
L
L
L
H
H
H
H
L
H
H
H
H
H
L
H
H
L
L
H
H
H
H
H
L
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
L
H
H
H
H
L
H
L
L
H
H
H
H
H
H
H
L
H
H
H
H
L
L
L
H
H
H
H
H
H
H
H
L
H
H
H
H
L
L
H
H
H
H
H
H
H
H
H
L
X
X
X
H
X
X
X
H
H
H
H
H
H
H
H
X
X
X
X
H
X
X
H
H
H
H
H
H,
H
H
X
X
X
X
X
L
X
H
H
H
H
H
H
H
H
X
X
X
X
X
X
L
H
H
H
H
H
H
H
H
ACKNOWLEDGE OUTPUT ACK
~
E2
E3
E4
AO
A1
ACK
H
X
X
X
X
X
H
X
H
X
X
X
X
H
X
X
L
X
X
X
H
X
X
X
L
X
X
H
L
L
H
H
L
X
L
L
L
H
H
X
L
L
8-40
AmZ8160
Cascadable 16-Bit Error Detection and Correction Unit
ADVANCED DATA
DISTINCTIVE CHARACTERISTICS
GENERAL DESCRIPTION
• Modified Hamming Code
Detects multiple errors and corrects single bit errors in a
parallel data word. Ideal for use in dynamic memory
systems.
The AmZ8160 Error Detection and Correction Unit (EDC) contains the logic necessary to generate 6 check bits on a 16-bit
data field according to a modified Hamming Code, and to correct
the data word when check bits are supplied. Operating on data
read from memory, the AmZ8160 will correct any single bit error
and will detect all double on some triple bit errors. The AmZ8160
is expandable to operate on 32-bit words (7 ch~ck bits) and
64-bit words (8 check bits). In all configurations, the device
makes the error syndrome available on separate outputs for
data logging.
• Syndromes provided
The AmZ8160 makes available the syndrome bits when an
error occurs so the location of memory faults can be logged.
• Microprocessor compatible
The AmZ8160 is designed to work with AmZ8000
microprocessor systems.
The AmZ8160 also features two diagnostic modes, in which
diagnostic data can be forced into portions of the chip to simplify
device testing and to execute system diagnostic functions. The
product is supplied in a 48 lead hermetic DIP package.
• Advanced circuit and process technologies
Newest bipolar LSI techniques provide very high
performance.
Data-in to error detection typically 30ns
Data-in to corrected data out typically 50ns
• Built-in Diagnostics
Extra logic on the chip provides diagnostic functions to be
used during device test and for system diagnostics.
SYSTEM EXAMPLE
8-41
»
3
N
Q)
-"
en
o
LE OUT
OE BYTE 0
CBo_s
(CHECK
BITS)
7
"7
DATA
OUTPUT
LATCH
BYTE 0
,...,...,.. 8,
DATAo_7 ~
rDATAS_1
~8"
IS.2I7
r-+r+-
DATA
OUTPUT
LATCH
BYTE 1
CORRECTION
LOGIC
ht-
BIT-INERROR
DECODE
U
R-
MUX
j
OE BYTE
-
DATA
INPUT
LATCH
BYTE 0
~ f-
I\)
~
CHECK
BIT
GENERATION
U7
r\16
DATA
INPUT
LATCH
BYTE 1
(X)
~
-
DIAG MO
7
j
I
,--7,
,
3,
"7
-
CONTROL
LOGIC
~
GENER
CORR
MUX
I--
_
PASST
r--
~
I
DIAGNOSTIC
LATCH
i,
SC o•s
SYNDROME!
~ CHECK
BITS
OE SC
7,
'-1
COD
DRIVERS
7
~
LE
LE 0
r?r-
<:J
CHECK BIT
INPUT
LATCH
'----
MUX
-
BLOCK DIAGRAM
r
ERROR
SYNDROME 7,
GENERAIT
TION
ERROR
DETECTION
-c> MULT ERROR
AmZ8160
EDC Architecture
The EDC Unit isa powerful 16-bit cascadable slice used for
check bit generation, error detection, error correction and diagnostics.
As shown in the block diagram, the device consists of the
following:
-
Data Input Latch
Check Bit Input Latch
Check Bit Generation Logic
Syndrome Generation Logic
Error Detection Logic
Error Correction Logic
Data Output Latch
Diagnostic Latch
Control Logic
Data Input Latch
16 bits of data are loaded from the bidirectional DATA lines
under control of the Latch Enable input, LE IN. Depending on the
control mode the input data is either used for check bit generation or error detection/correction.
Check Bit Input Latch
Seven check bits are loaded under control of LE IN. Check bits
are used in the Error Detection and Error Correction modes.
Check Bit Generation Logic
This block generates the appropriate check bits for the 16 bits of
data in the Data Input Latch. The check bits are generated according to a modified Hamming code.
Syndrome Generation Logic
In both Error Detection and Error Correction modes, this logic
block compares the check bits read from memory against a
newly generated set of check bits produced for the data read in
from memory. If both sets of check bits match, then there are no
errors. If there is a mismatch, then one or more of the data or
check bits is in error.
The syndrome bits are produced by an exclusive-OR of the two
set's of check bits. If the two sets of check bits are identical
(meaning there are no errors)' the syndrome bits will be all
zeroes. If there are errors, the syndrome bits can be decoded to
determine the number of errors and the bit-in-error.
Error Detection Logic
This section decodes the syndrome bits generated by the Syndrome Generation Logic. If there are no errors in either the input
data or check bits, the ERROR and MULTI ERROR outputs
remain HIGH. If one or more errors are detected, ERROR goes
LOW. If two or more errors are detected, both ERROR and
MULTI ERROR go LOW.
Error Correction Logic
For single errors, the Error Correction Logic complements (corrects) the single data bit in error. This corrected data is loadable
into the Data Output Latch, which can then be read onto the
bidirectional data lines. If the single error is one of the check bits,
the correction logic does not place corrected check bits on the
syndrome/check bit outputs. If the corrected check bits are
needed the EDC must be switched to Generate Mode.
Data Output Latch
The Data Output Latch is used for storing the result of an error
correction operation. The latch is loaded from the correction
logic under control of the Data Output Latch Enable, LE OUT.
The Data Output Latch may also be loaded directly from the
Data Input Latch under control of the PASS THRU control input.
The Data Output Latch is split into two 8-bit (byte) latches which
may be enabled independently for reading onto the bidirectional
data lines.
Diagnostic Latch
This is a 16-bit latch loadable from the bidirectional data lines
under control of the Diagnostic Latch Enable, LE DIAG. The
Diagnostic Latch contains check bit information in one byte and
control information in the other byte. The Diagnostic Latch is
used for driving the device when in Internal Control Mode, or for
supplying check bits when in one of the Diagnostic Modes.
Control Logic
The control logic determines the specific mode the device operates in. Normally the control logic is driven by external control
inputs. However, in Internal Control Mode, the control signals
are instead read from the Diagnostic Latch.
8-43
AmZ8160
PIN DEFINITIONS
DATAO_15
16 bidirectional data lines. They provide input to
the Data Input Latch and Diagnostic Latch, and
receive output from the Data Output Latch. DATAo
is the least significant bit; DATA15 the most significant.
CBO-6
Seven Check Bit input lines. The check bit lines
are used to input check bits for error detection.
Also used to input syndrome bits for error correction in 32 and 64-bit configurations.
LE IN
Generate Mode, MULTI ERROR is forced HIGH.
(In a 64-bit configuration, MULTI ERROR must be
externally implemented.)
CORRECT
Correct input. When HIGH this signal allows the
correction network to correct any single-bit error in
the Data Input Latch (by complementing the
bit-in-error) before putting it onto the Data Output
Latch. When LOW the EDC will drive data directly
from the Data Input Latch to the Data Output Latch
without correction.
LE OUT
Latch Enable - Data Output Latch. Controls the
latching of the Data Output Latch. When LOW the
Data Output Latch is latched to its previous state.
When HIGH the Data Output Latch follows the
output of the Data Input Latch as modified by the
correction logic netvv'ork. In Correct Mode, singlebit errors are corrected by the network before
loading into the Data Output Latch. In Detect
Mode, the contents of the Data Input Latch are
passed through the correction network unchanged
into the Data Output Latch. The inputs to the Data
Output Latch are unspecified if the EDC is in Generate Mode.
Latch Enable - Data Input Latch. Controls latching of the input data. When HIGH the Data Input
Latch and Check Bit Input Latch follow the input
data and input check bits. V'Ihen LOW, the Data
Input Latch and Check Bit Input Latch are latched
to their previous state.
G""'-=E""""N=E=R-:-AT""'E=" Generate Check Bits input. When this input is
LOW the EDC is in the Check Bit Generate Mode.
When HIGH the EDC is in the Detect Mode or
Correct Mode.
In the Generate Mode the circuit generates the
check bits or partial check bits specific to the data
in the Data Input Latch. The generated check bits
are placed on the SC outputs.
OE BYTE 0, Output Enable - Bytes 0 and 1, Data Output
OE BYTE 1 Latch. These lines control the 3-state outputs for
each of the two bytes of the Data Output Latch.
When LOW these lines enable the Data Output
Latch and when HIGH these lines force the Data
Output Latch into the high impedance state. The
two enable lines can be separately activated to
enable only one byte of the Data Output Latch at a
time.
In the Detect or Correct Modes the EDC detects
single and multiple errors, and generates syndrome bits based upon the contents of the Data
Input Latch and Check Bit Input Latch. In Correct
Mode, single-bit errors are also automatically corrected - corrected data is placed at the inputs of
the Data Output Latch. The syndrome result is
placed on the SC outputs and indicates in a coded
form the number of errors and the bit-in-error.
SC O- 6
Syndrome/Check Bit outputs. These seven lines
hold the check/partial-check bits when the EDC is
in Generate Mode, and will hold the syndrome/
partial syndrome bits when the device is in Detect
or Correct Modes. These are 3-state outputs.
PASS
THRU
Pass Thru input. This line when HIGH forces the
contents of the Check Bit Input Latch onto the
Syndrome/Check Bit outputs (SC O- 6 ) and the unmodified contents of the Data Input Latch onto the
inputs of the Data Output Latch.
DIAG
MODEO_1
Diagnostic Mode Select. These two lines control
the initialization and diagnostic operation of the
EDC.
CODE 100 - 2 Code Identification inputs. These three bits identify the size of the total data word to be processed
and which 16-bit slice of larger data words a particular EDC is processing. The three allowable
data word sizes are 16, 32 and 64 bits and their
respective modified Hamming codes are designated 16/22, 32/39 and 64/72. Special CODE 10
input 001 (10 2 , 101 , 100 ) is also used to instruct the
EDC that the signals CODE 10 0 - 2 • DIAG
MODEo_1 , CORRECT and PASS THRU are to be
taken from the Diagnostic Latch, rather than from
the input control lines.
Output Enable - Syndrome/Check Bits. When
LOW, the 3-state output lines SC O- 6 are enabled.
When HIGH, the SC outputs are in the high impedance state.
Error Detected output. When the EDC is in Detect
or Correct Mode, this output will go LOW if one or
more syndrome bits are asserted, meaning there
are one or more bit errors in the data or check bits.
If no syndrome bits are asserted, there are no errors detected and the output will be HIGH. In Generate Mode, ERROR is forced HIGH. (In a 64-bit
configuration, ERROR must be externally implemented.)
LE DIAG
Multiple Errors Detected output. When the EDC is
in Detect or Correct Mode, this output if LOW indicates that there are two or more bit errors that
have been detected. If HIGH this indicates that
either one or no errors have· been detected. In
8-44
Latch Enable - Diagnostic Latch. When HIGH the
Diagnostic Latch follows the 16-bit data on the
input lines. When LOW the outputs of the Diagnostic Latch are latched to their previous states.
The Diagnostic Latch holds diagnostic check bits.
and internal control signals for CODE 100- 2 • DIAG
MODEo_1 • CORRECT and PASS THRU.
AmZ8160
FUNCTIONAL DESCRIPTION
Check and Syndrome Bit Labeling
The EDC contains the logic necessary to generate check bits on a
16-bit data field according to a modified Hamming code. Operating on data read from memory, the EDC will correct any singlebit error, and will detect all double and some triple-bit errors. It
may be configured to operate on 16-bit data words (with 6 check
bits), 32-bit data words (with 7 check bits) and 64-bit data words
(with 8 check bits). In all configurations, the device makes the
error syndrome bits available on separate outputs for error data
logging.
The check bits generated in the EDC are designated as follows:
• 16-bit configuration - CX CO, C1, C2, C4, C8;
• 32-bit configuration - CX, CO, C1, C2, C4, C8, C16;
• 64-bit configuration - CX, CO, C1, C2, C4, C8, C16, .C32.
Syndrome bits are similarly labeled SX through S32. There are
only 6 syndrome bits in the 16-bit configuration, 7 for 32 bits and
8 syndrome bits in the 64-bit configuration.
Code and Byte Specification
The EDC may be configured in several different ways and operates differently in each configuration. It is necessary to indicate
to the device what size data word is involved and which bytes of
the data word it is processing. This is done with input lines
CODE IDo-2' as shown in Table I. The three modified Hamming
codes referred to in Table I are:
FUNCTIONAL DESCRIPTION 16-BIT DATA WORD CONFIGURATION
The 16-bit format consists of 16 data bits, 6 check bits and is
referred to as 16/22 code (see Figure 1).
The 16-bit configuration is shown in Figure 2.
Generate Mode
• 16/22 code • 32/39 code • 64/72 code -
16 data bits
6 check bits
22 bits in total.
32 data bits
7 check bits
39 bits in total.
64 data bits
8 check bits
72 bits in total.
In this mode check bits will be generated that correspond to the
contents of the Data Input Latch. The check bits generated
are placed on the outputs SC O- 5 (SC s is unspecified for 16-bit
operation).
Check bits are generated according to a modified Hamming
code. Details of the code for check bit generation are contained
in Table IV. Each check bit is generated as either an XOR or
XNOR of eight of the 16 data bits as indicated in the table. The
XOR function results in an even parity check bit, the XNOR is an
odd parity check bit.
CODE 10 input 001 (10 2, 101 , 100 ) is a special code used to
operate the device in Internal Control Mode (described later in
this section).
Detect Mode
In this mode the device examines the contents of the Data Input
Latch against the Check Bit Input Latch, and will detect all
single-bit errors, all double-bit errors and some triple-bit errors. If
one or more errors are detected, EFfROR goes LOW. If two or
more errors are detected, MULTI ERROR goes LOW. Both error
indicators are HIGH if there are no errors.
TABLE I. HAMMING CODE AND. SLICE IDENTIFICATION.
CODE CODE CODE
102
101
100 Hamming Code and Slice Selected
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Code 16/22
Internal Control Mode
Code 32/39, Bytes 0 and
Code 32/39, Bytes 2 and
Code 64/72, Bytes 0 and
Code 64/72, Bytes 2 and
Code 64/72, Bytes 4 and
Code 64/72, Bytes 6 and
Also available on device outputs SC O_5 are the syndrome bits
generated by the error detection step. The syndrome bits may
be decoded to determine if a bit error was detected and, for
single-bit errors, which of the data or check bits is in error. Table
V gives the chart for decoding the syndrome bits generated by
the 16-bit configuration (as an example, if the syndrome bits
SXlSO/S1/S2/S4/S8 were 101001 this would be decoded to indicate that there is a single-bit error at data bit 9). If no error is
detected the syndrome bits will all be zeroes.
1
3
1
3
In Detect Mode, the contents of the Data Input Latch are driven
directly to the inputs of the Data Output Latch without correction.
5
7
Correct Mode
Control Mode Selection
The device control lines are GENERATE, CORRECT, PASS
THRU, DIAG MODE o_1 and CODE IDo_2. Table II indicates the
control modes selected by various combinations of the control
line inputs.
Diagnostics
Table III shows specifically how DIAG MODEo_1 select between
normal operation, initialization and one of two diagnostic modes:
In this mode, the EDC functions the same as in Detect Mode
except that the correction network is allowed to correct (complement) any single-bit error of the Data Input Latch before putting it onto the inputs of the Data Output Latch. If multiple errors
are detected, the output of the correction network is unspecified.
If the single-bit error is a check bit there is no automatic correc. tion. If check bit correction is desired, this .can be done by placing the device in Generate Mode to produce a correct check bit
sequence for the data in the Data Input Latch.
The Diagnostic Modes allow the user to operate the EDC under
software control in order to verify proper functioning of the
device.
8-45
Pass Thru Mode
In this. mode, the unmodified contents of the Data Input Latch
are placed on the inputs of the Data Output Latch and the contents of the Check Bit Input Latch are placed on outputs SC O- 5'
AmZ8160
TABLE II. EDC CONTROL MODE SELECTION.
GENERATE
CORRECT
PASS THRU
DIAG MODEO_1
( DM 1. DMO)
CODE IDO_2
(ID2. ID1. IDo)
LOW
LOW
LOW
00
Not 001
Generate
LOW
LOW
LOW
01
Not 001
Generate Using Diagnostic Latch
LOW
LOW
LOW
10
Not 001
Generate
LOW
LOW
LOW
11
Not 001
Initialize
LOW
LOW
HIGH
00
Not 001
Pass Thru
LOW
LOW
HIGH
01
Not 001
Pass Thru
LOW
LOW
HIGH
10
Not 001
Pass Thru
LOW
LOW
HIGH
11
Not 001
Undefined
LOW
HIGH
LOW
00
Not 001
Generate
LOW
HIGH
LOW
01
Not 001
Generate Using Diagnostic Latch
LOW
HIGH
LOW
10
Not 001
Generate
LOW
HIGH
LOW
11
Not 001
Initialize
LOW
HIGH
HIGH
00
Not 001
Pass Thru
Control Mode Selected
LOW
HIGH
HIGH
01
Not 001
Pass Thru
LOW
HIGH
HIGH
10
Not 001
Pass Thru
LOW
HIGH
HIGH
11
Not 001
Undefined
HIGH
LOW
LOW
00
Not 001
Detect
HIGH
LOW
LOW
01
Not 001
Detect
HIGH
LOW
LOW
10
Not 001
Detect Using Diagnostic Latch
HIGH
LOW
LOW
11
Not 001
Initialize
HIGH
LOW
HIGH
00
Not 001
Pass Thru
HIGH
LOW
HIGH
01
Not 001
Pass Thru
HIGH
LOW
HIGH
10
Not 001
Pass Thru
HIGH
LOW
HIGH
11
Not 001
Undefined
HIGH
HIGH
LOW
00
Not 001
Correct
HIGH
HIGH
LOW
01
Not 001
Correct
HIGH
HIGH
LOW
10
Not 001
Correct Using Diagnostic Latch
HIGH
HIGH
LOW
11
Not 001
Initialize
HIGH
HIGH
HIGH
00
Not 001
Pass Thru
HIGH
HIGH
HIGH
01
Not 001
Pass Thru
HIGH
HIGH
HIGH
10
Not 001
Pass Thru
HIGH
HIGH
HIGH
11
Not 001
Any
Any
Any
Any
001
Undefined
Internal Control Using Diagnostic Latch
TABLE III. DIAGNOSTIC MODE CONTROL.
DIAG
MODE 1
DIAG
MODEo
0
0
Non-diagnostic mode. The EDC functions normally in all modes.
0
1
Diagnostic Mode A. The contents of the Diagnostic Latch are substituted for the normally generated check bits when in the Generate Mode.
The EDC functions normally in the Detect or Correct modes.
1
0
Diagnostic Mode B. In the Detect or Correct Mode, the contents of the
Diagnostic Latch are substituted for the check bits normally read from
the Check Bit Input Latch. The EDC functions normally in the
Generate Mode.
1
1
Initialize. The inputs of the Data Output Latch are forced to zeroes and
the check bits generated correspond to the all-zero data.
Diagnostic Mode Selected
8-46
ArnZ8160
INPUT CHECK BITS
FOR 1S-BIT CONFIGURATION
CHECK BITS
DATA
I .I,
BYTE 1
IIII
BYTE 0
cx
CO
C1
C21 C41
DT"
CX
DATAo_1S
CBO
CO
C1
DON'T
CARE
ca
C4
!!I!!
1 1
CB l
CB 2
CB 3
CB.
CBs
CB 6
cal
0
15
C2
CODE
100 _2
EDC
SC o
SC,
SC 2
SC 3
SC.
SC S
1-000
SC 6
,11 "L 1J. 1 l
Uses Modified Hamming Code 16/22
- 16 data bits
- 6 check bits
- 22 bits in total
UNSPECIFIED
FOR lS-BIT
CONFIGURATION
SOICO
S2/C2
SBICS
SYNDROME/CHECK BIT OUTPUTS
FOR 1S-BIT CONFIGURATION
Figure 2. 16 Bit Configuration.
Figure 1. 16 Bit Data Format.
BLI-202
TABLE IV. 16-BIT MODIFIED HAMMING CODE - CHECK BIT ENCODE CHART.
PartiCipating
Data Bits
Generated
Check
Bits
Parity
CX
Even (XOR)
0
CO
Even (XOR)
X
C1
Odd (XNOR)
X
C2
Odd (XNOR)
X
C4
Even (XOR)
C8
Even (XOR)
1
2
3
X
X
X
X
X
4
X
X
X
6
7
X
8
9
X
X
X
X
X
X
X
5
X
X
X
X
X
X
X
X
10
11
X
X
X
13 14
X
15
X
X
X
X
X
X
X
12
X
X
X
X
X
X
X
X
X
X
The check bit is generated as either an XOR or XNOR of the eight data bits noted by an "X" in the table.
TABLE V. SYNDROME DECODE
TO BIT-IN-ERROR.
Syndrome
Bits
S8
S4
S2
0
0
1
0
0
*
SX
SO
Sl
0
0
0
0
0
1
C1
TABLE VI. DIAGNOSTIC LATCH LOADING 16-BIT FORMAT.
0
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
1
1
C8
C4
T
C2
T
T
M
T
T
15
T
13
7
T
0
1
0
CO
T
T
M
T
12
6
T
0
1
1
T
10
4
T
0
T
T
M
1
0
0
CX
T
T
14
T
11
5
T
1
0
1
T
9
3
T
M
T
T
M
1
1
1
1
0
1
T
M
8
T
2
T
T
M
1
T
T
M
T
M
Data Bit
Internal Function
0
Diagnostic Check Bit X
1
Diagnostic Check Bit 0
2
Diagnostic Check Bit 1
3
Diagnostic Check Bit 2
4
Diagnostic Check Bit 4
5
Diagnostic Check Bit 8
6, 7
M
T
* - no errors detected
Number - the location of the single bit-In-error
T - two errors detected
M - three or more errors detected
8-47
Don't Care
8
CODE 100
9
CODE 10 1
10
CODE 102
11
DIAG MODE 0
12
DIAG MODE 1
13
CORRECT
14
PASS THRU
15
Don't Care
BLI-203
ArnZ8160
Diagnostic Latch
Internal Control Mode
The Diagnostic Latch serves both for diagnostic uses and internal control uses. It is loaded from the DATA lines under the
control of LE DIAG. Table VI shows the loading definitions for
the DATA lines.
This mode is selected by CODE IDo_2 input 001 (ID2, ID 1 , 100 ).
When in Internal Control Mode, the EDC takes the CODE 100 - 2,
DIAG MODE o_1 , CORRECT and PASS THRU control signals
from the internal Diagnostic Latch rather than from the external
input lines.
Generate Using Diagnostic Latch (Diagnostic Mode A)
Table VI gives the format for loading the Diagnostic Latch.
Detect Using Diagnostic Latch (Diagnostic Mode B)
Correct Using Diagnostic Latch (Diagnostic Mode B)
32 and 64·Bit Operation
These are special diagnostic modes selected by DIAG MODE o_1
where either normal check bit inputs or outputs are substituted
for by check bits loaded into the Diagnostic Latch. See Table III
for details.
The EDC can easily be cascaded to operate on 32 and 64-bit data
words. Since this is unlikely to occur in a Z8000 system, it is not
discussed in this data sheet. Interested users should refer to the
Am2960 data sheet for more information.
LOGIC SYMBOL
DATA15 _0
CONNECTION DIAGRAM
Top View
CB O_6
GENERATE
LE IN
CORRECT
LEOUT
PASS THRU
OE BYTE 0
OE BYTE 1
OESC
CODE 1D0_2
DIAG MODE o.1
LE DIAG
Note: Pin 1 is marked for orientation.
BLI-204
8-48·
BLI·205
AmZ8161
• AmZ8162
4-Bit Error Correction Multiple Bus Buffers
IN DEVELOPMENT
DISTINCTIVE CHARACTERISTICS
FUNCTIONAL DESCRIPTION
• Quad high-speed LSI bus-transceiver
• Provides complete data path interface between the AmZ8160
Error Detection and Correction Unit, the system data bus and
dynamic RAM memory
• 3-state 24mA output to data bus
• 3-state data output to memory
• Inverting data bus for AmZ8161 and non-inverting for
AmZ8162
• Data bus latches allow operation with multiplexed buses
• Advanced Low-Power Schottky processing
• 100% product assurance screening to MIL-STD-883
requirements
The AmZ8161 and AmZ8162 are high-performance, low-power
Schottky multiple bus buffers that provide the complete data
path interface between the AmZ8160 Error Detection and Correction Unit, dynamic RAM memory and the AmZ8000 system
data bus. The AmZ8161 provides an inverting data path between
the data bus (Bj) and the AmZ8160 error correction data input
(Yj) and the AmZ8162 provides a non-inverting configuration (Bj
to Yj). Both devices provide inverting data paths between the
AmZ8160 and memory data bus thereby optimizing internal data
. path speeds.
The AmZ8161 and AmZ8162 are 4-bit devices. Four devices are
used to interface each 16-bit AmZ8160 Error Detection and Correction Unit with dynamic memory. The system can easily be
expanded to 32 or more bits for wider memory applications. The
4-bit configuration allows enabling the appropriate devices
two-at-a-time for intermixed word or byte, read and write in 16-bit
systems with error correction.
Data latches between the error correction data bus and the
system data bus facilitate the addition of error corrected memory
in synchronous data bus systems. They also provide a data
holding capability during single-step system operation.
AmZ8161 LOGIC DIAGRAM
DATA
INPUT
FROM MEMORY SELECT
OJ
S
s
OUTPUT
ENABLE
TO Y
OEY
CONNECTION DIAGRAM
Top View
DATA
OUTPUT
TO MEMORY
DO
ERROR
CORRECTION
DATA BUS
Y
24 pin slim (0.3")
SYSTEM
DATA BUS
B
BLI·206
BLI·207
*AmZ8162 is the same function but non-inverting between the Y bus
to the system data bus, B. This is done by making both latches
inverting.
Note: Pin 1 is marked for orientation.
8-49
AmZ8163
Dynamic Memory Timing, Refresh and EDC Controller
DISTINCTIVE CHARACTERISTICS
•
•
•
•
•
Complete AmZ8000 CPU to dynamic RAM contol interface
RAS!CAS Sequencer to eliminate delay lines
Memory request/refresh arbitration
Controls for Word!Byte read or write
Complete EDC data path and mode controls
•
•
•
•
Refresh interval timer independent of CPU
Refresh control during Single Step or Halt modes
EDC error flag latches for error logging under software control
Also, complete control for 8-Bit MOS JLP
FUNCTIONAL DESCRIPTION
The AmZ8163 is a high speed bus interface controller forming an
integral part of the AmZ8000 memory support chip set using
dynamic MOS RAMs with Error Detection and Correction (EDC).
The complete chip set includes the AmZ8127 Clock Generator
and Controller, the AmZ8164 Dynamic Memory Controller, the
AmZ8161!2 EDC Bus Buffers, the AmZ8160 EDC Unit and optional AmZ8165!6 RAM Drivers.
enables and controls. The enable controls are configured for both
word and byte operations including the data controls for byte write
with error correction. The AmZ8163 generates bus and operating
mode controls for the AmZ8160 EDC Unit.
The AmZ8163 uses the AmZ8127 16MHz (4 x ClK) output to
generate RAS!Address MUXlCAS timing. An internal refresh
interval timer generates the memory refresh request independent
of the CPU to guarantee the proper refresh timing under all
combinations of CPU and DMA memory requests.
The AmZ8163 provides all of the control interface functions including RAS!Address MUX!CAS timing (without delay lines), refresh timing, memory request!refresh arbitration and all EDC
FUNCTION DIAGRAM
REFRESH AND EDC CONTROLLER
AmZS164
DMC
LATCH
ENABLE
RFSH
Am9016
RAMs
RASI MSEL CASI
WE
l
AmZ8161/62
EDC MULTPLE
DATA BUS
BUFFERS
I
(1MHz)
0
~
(16MHz)
CD
c:
If)
I
FORCE
REFRESH
(FOR TRANSPARENT
REFRESH DURING
I/O OR INTERNAL
OPERATION)
ERR
L
MCE
(ADDS ONE WAIT
STATE FOR USE
WITH SLOWER
300ns RAMs)
MERR
mrn
LMERR
iN'fMEi1R
ERRACK
INTACK
BLI-167
8-50
AmZ8164
Dynamic Memory Controller
ADVANCED INFORMATION
DISTINCTIVE CHARACTERISTICS
FUNCTIONAL DESCRIPTION
• Dynamic Memory Controller for 16K and 64K MaS dynamic
RAMs
• 8-Bit Refresh Counter for refresh address generation, has
clear input and terminal count output
• Refresh Counter Terminal count selectable at 256 or 128
• Latch Input RAS DecOder provides 4 RAS outputs, all active
during refresh
• Dual 8-Bit Address Latches plus separate RAS Decoder
Latches
• Grouping functions on a common chip minimizes speed differential/skew between address, RAS and CAS outputs
• 3-Port 8-Bit Address Multiplexer with Schottky speed
• Burst mode, distributed refresh or transparent refresh mode
determined by user
• Non-inverting address, RAS and CAS paths
• 100% product assurance screening to MIL-STD-883
requirements
The AmZ8164 Dynamic Memory Controller replaces severar MSI
devices by grouping several unique functions. Two 8-bit latches
capture and hold the memory address from the AmZ8000 multiplexed data and address bus. These latches and a clearable,
8-bit refresh counter feed into an 8-bit, 3-input, Schottky speed
MUX, for output to the dynamic RAM address lines. The device
is also compatible with Am8085 or any CPU interfacing with
dynamic RAMs.
The same silicon chip also includes a special RAS decoder and
CAS buffer. Placing these functions on the same chip minimizes
the time skew between output functions which would otherwise
be separate MSI chips, and therefore, allows a faster memory
cycle time by the amount of skew eliminated.
Pulsing the active LOW refresh line, RFSH, switches the MUX to
the counter output, inhibits CAS, and forces all four RAS decoder
outputs active simultaneously. The counter is advanced at the end
of the refresh cycle - the LOW-to-HIGH transition of RFSH. Various refresh modes can be accommodated - for 16K or 64K
RAMs and for a wide variety of processor configurations.
A15 is a dual function input which controls the refresh counter's
range. For 64K RAMs it is an address input. For 16K RAMs it can
be pulled to + 12V through 1KD to terminate the refresh count at
128 instead of 256 if this is needed.
LOGIC DIAGRAM
CONNECTION DIAGRAM
Top View
MSEL-----------------------------,
II
39
38
37
36
00
8-BIT
MUX
35
34
33
8-BIT
LATCH
32
31
30
EN------~~--~
CLR------~--------~
29
1--+_______
28
TC
27
26
25
24
RSELO
RSEL 1
RASI
RAS
DECODE
RASa
23
RAS 1
22
RAS 2
21
RAS3
RFSH
CASIN
CASOUT
Note: Pin 1 is marked for orientation.
BLI-208
8-51
BLI-209
AmZ8165 • AmZ8166
Octal Dynamic Memory Drivers with Three-State Outputs
DISTINCTIVE CHARACTERISTICS
FUNCTIONAL DESCRIPTION
• Controlled rise and fall characteristics
Internal resistors provide symmetrical drive to HIGH and
LOW states, eliminating need for external series resistor.
The AmZ8165 and AmZ8166 are designed and specified to drive
the capacitive input characteristics of the address and control
lines of M08 dynamic RAMs. The unique design of the lower
output driver includes a collector resistor to control undershoot on
the HIGH-to-LOW transition. The upper output driver pulls up to
Vcc - 1.15V to be compatible with M08 memory and is designed
to have a rise time symmetrical with the lower output's controlled
fa!1 time. This allows optimization of Dynamic RAM performance.
• Output swings designed to drive 16K and 64K RAMs
VOH guaranteed at Vcc - 1.15V. Undershoot going LOW
guaranteed at less than O.5V.
• Large capacitive drive capability
35mA min source or sink current at 2.0V. Propagation
delays specified for 50pF and 500pF loads.
• Pin-compatible with 'S240 and 'S244
Non-inverting AmZ8166 replaces 748244; inverting
AmZ8165 replaces 748240. Faster than '8240/244 under
equivalent load.
• No-glitch outputs
Outputs forced into OFF state during power up and down.
CONNECTION DIAGRAM
Top View
2G
2Y4
lYl
lA2
2A4
2Y3
1Y2
lA3
2A3
2Y2
1Y3
lA4
2A2
2Yl
1Y4
GND
2Al
The inclusion of an internal resistor in the lower output driver
eliminates the requirement for an external series resistor, therefore reducing package count and the board area required. The
internal resistor controls the output fall and undershoot without
slowing the output rise.
These devices are designed for use with the AmZ8164 Dynamic
Memory Controller where large dynamic memories with highly
capacitive input lines require additional buffering. Driving eight
address lines or four RA8 and four CA8 lines with drivers on the
same silicon chip also provides a significant performance advantage by minimizing skew between drivers. Each device has
specified skew between drivers to improve the memory access
worst case timing over the min and max tpD difference of unspecified devices.
Vee
16
lAl
The AmZ8165 and AmZ8166 are pin-compatible with the popular
'8240 and '8244 with identical3-state output enable controls. The
AmZ8165 has inverting drivers and the AmZ8166 has non-inverting drivers.
TYPICAL OUTPUT DRIVER
------1~--_o
Vee
R ",,30n
+---R ",,25n
Note: Pin 1 is marked for orientation.
-----<1>----_0
BLI-210
OUTPUT TO
RAM ADDRESS
OR CONTROL
LINES
GND
BLI·211
LOGIC DIAGRAMS
BLI-212
BLI·213
AmZ8165
AmZ8166
lAl
lYl
2Al
2Yl
2Yl
lA2
1Y2
2A2
2Y2
2Y2
lA3
1Y3
2A3
2Y3
lA4
16
lY4
2A4
2G
2Y4
Inputs
2Y3
Outputs
G
A
Y
H
L
L
X
H
L
Z
Inputs
Outputs
G
A
Y
H
L
L
X
L
Z
2'1'4
L
H
8-52
H
L
H
AmZ8165· AmZ8166
MAXIMUM RATINGS
(Above which the useful life may be impaired)
Storage Temperature
-65 to +150°C
Temperature (Ambient) Under Bias
-55 to +125°C
Supply Voltage to Ground Potential Continuous
-0.5 to + 7.0V
DC Voltage Applied to Outputs for High Output State
-0.5V to +Vee max
-0.5 to + 7.0V
DC Input Voltage
DC Output Current, into Outputs
30mA
-30 to +5.0mA
DC Input Current
ELECTRICAL CHARACTERISTICS
The Following Conditions Apply Unless Otherwise Specified:
COM'L
MIL
TA = 0 to 70°C
TA = -55 to +125°C
Vee = 5.0V ±10%
Vee = 5.0V ±10%
(MIN = 4.50V
(MIN = 4.50V
MAX = 5.50V)
MAX = 5.50V)
DC CHARACTERISTICS OVER OPERATING RANGE
Typ
Parameters
Description
Test Conditions (Note 1 )
VO H
Output High Voltage
Vee = MIN
VIN = VIH or Vil
VOL
Output LOW Voltage
Vee = MIN
VIN = VIH or Vil
VIH
Input HIGH Level
Guaranteed input logical HIGH voltage
for all inputs
Vil
Input LOW Level
Guaranteed input logical LOW voltage
for all inputs
VI
Input Clamp Voltage
Vee.= MIN, liN = -18mA
III
Input LOW Current
Vee
IIH
Input HIGH Current
Vee = MAX, VIN
II
Input HIGH Current
Vee
IOZH
Off-State Current
=
MAX, VIN
10H
IOl
IOl
= -1mA
Min
(Note 2)
Vee- U5
Vee- O.7V
= 1mA
= 12mA
Max
Units
Volts
0.5
0.8
Volts
Volts
2.0
= 0.4V
= 2.7V
0.8
Volts
-1.2
Volts
-200
}LA
20
}LA
0.1
mA
Vo = 2.7V
100
}LA
-200
=
MAX, VIN = 7.0V
}LA
IOZl
Off-State Current
Vo = O.4V
IOl
Output Sink Current
VOL = 2.0V
35
mA
IOH
Output Source Current
VOH = 2.0V
-35
mA
Ise
Output Short Circuit Current
(Note 3)
=
-60
(see IOH)
Vee
MAX
24
50
86
125
All Outputs Hi-Z
86
125
All Outputs HIGH
53
75
All Outputs HIGH
AmZ8165
lec
Supply Current
AmZ8166
-200
All Outputs LOW
All Outputs LOW
Vee = MAX
Outputs Open
Vee = MAX
Outputs Open
All Outputs Hi-Z
92
130
116
150
mA
mA
Notes: 1. For conditions shown as MIN or MAX, use the appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical limits are at Vee = 5.0V, 25°C ambient and maximum loading.
3. Not more than one output should be shorted at a time. Duration of the short circuit test should not exceed one second.
8-53
ArnZ8165· ArnZ8166
ArnZ8165 • ArnZ8166
SWITCHING CHARACTERISTICS
(TA = +2soe, vee = s.OV)
Parameters
Description
Test Conditions
Min
Cl = OpF
Propagation Delay Time from
LOW-to-HIGH Output
tplH
Figure 1 Test Circuit
Figure 3 Voltage Levels
and Waveforms
Propagation Delay Time from
HIGH-to-LOW Output
tpHl
Typ
Max
6
(Note 4)
Cl = SOpF
6
9
1S
Cl = SOOpF
1S
22
3S
C L = OpF
Cl = SOpF
4
(Note 4)
6
12
20
Cl = SOOpF
20
30
4S
Units
ns
ns
Output Disable Time from
LOW, HIGH
=1
13
20
Figures 2 and 4, S = 2
8
12
Output Enable Time from
LOW, HIGH
Figures 2 and 4, S = 1
13
20
tpzH
Figures 2 and 4, S = 2
13
20
tSKEW
Output-to-Output 8kew
Figures 1 and 3, C L
= SOpF
±O.S
±3.0
(Note S)
ns
VO NP
Output Voltage Undershoot
Figures 1 and 3, C L
= SOpF
0
-O.S
Volts
tpLZ
tpHZ
tpZL
Figures 2 and 4, S
ns
ns
SWITCHING CHARACTERISTICS
OVER OPERATING RANGE (Note 6)
MIL
COM'L
TA
VCC
Parameters
Description
Test Conditions
el
tplH
Propagation Delay Time
LOW-to-HIGH Output
Figures 1 and 3
tpHl
Propagation Delay Time
HIGH-to-LOW Output
Figures 1 and 3
Output Disable Time from
LOW, HIGH
Figures 2 and 4 .
Output Enable Time from
LOW, HIGH
Figures 2 and 4
tpZH
VONP
Output Voltage Undershoot
Figures 1 and 3, C l
tplZ
tpHZ
tpZl
= SOpF
Cl = SOOpF
= 0 to 70°C
= 5.0V ±10%
= -55 to +125°C
VCC = 5.0V ±10%
TA
Min
Max
Min
Max
4
20
4
20
13
40
13
40
Cl =, SOpF
4
24
4
24
Cl = 500pF
17
SO
17
SO
8 = 1
24
24
8=2
16
16
8 = 1
28
28
8=2
28
28
-O.S
-O.S
= 50pF
Notes: 4. Typical time shown for reference only - not tested.
S. Time Skew specification is guaranteed by design but not tested.
6. AC performance over the operating temperature range is guaranteed by testing defined in Group A, Subgroup 9.
SWITCHING TEST CIRCUITS
vee
BLI-215
BU-214
DEVICETl
OUTPUT
I
*
CL
LZ, ZL
R
D~~~~
FROM
OUTPUT
R
":" 2kO
o-_-..____6",8VOO_ _C"'s
1
150
CL
PF
21
HZ, ZH
·tpd specified at C = SO and 500pF.
Figure 1. Capacitive Load Switching.
Figure 2. Three-State Enable/Disable.
8-54
Units
ns
ns
ns
ns
Volts
AmZ8165 • AmZ8166
TYPICAL SWITCHING CHARACTERISTICS
VOLTAGE WAVEFORMS
E~~~~~
r------..------- 3.0V
\~1_.5_V
---.!1.5V
AmZ8165
_ _ _ _ _ OV
f - - - - f - - IpZH
, - - - - - - - 3.0V
INPUT
------OV
~VOL
_
ov
tr
= tf = 2.Sns
tr
=
tf
=
2.5ns
f = 1MHz
f = 2.5MHz
tpw = 200ns
tpw = BOOns
BLI-217
BLI-218
Figure 4. Three-State Control Levels.
Figure 3. Output Drive Levels.
The RAM Driver symmetrical output design offers significant improvement over a standard Schottky output by providing a balanced drive
output impedance (=330 both HIGH and LOW), and by pulling upto MOS V OH levels (Vee - 1.15V). External resistors, not required with
the RAM Driver, protect standard Schottky drivers from error causing undershoot but also slow the output rise by adding to the internal R.
The RAM Driver is optimized to drive LOW at maximum speed based on safe undershoot control and to drive HIGH with a symmetrical
speed characteristic. This is an optimum approach because the dominant RAM loading characteristic is input capacitance.
The curves shown below provide performance characteristics typical of both the inverting (AmZ8165) and non-inverting (AmZ8166) RAM
Drivers.
1000
1000
u..
u..
Co
Co
I
...J
(,)
w 100
(,)
z
w 100
(,)
Z
;!
(3
~
c:(
~
MAX @ +25°C
(3
~
c:(
10
(,)
10
(,)
C
cc:(
c:(
0
0
-'
1.0
-'
0
10
20
30
40
50
1.0
0
tpLH - ns
BLI-219
II
I
...J
(,)
10
20
30
40
50
tpHL - ns
Figure 5. tpLH vs. CL'
Figure 6. tpHL vs. CL'
BLI-220
The curves above depict the typical tpLH and tPHl for the RAM Driver outputs as a function of load capacitance. The minimums and
maximums are shown for worst case design. The typical band is provided as a guide for intermediate capacitive loads.
8-55
ArnZ8165 • ArnZ8166
APPLICATION
64K1256K X 22·BIT MEMORY
CHECK
BITS
7/8
07
RASa
RAS1
ADDR
16
AmZ8001/2
CPU
AmZ8164
DYNAMIC
MEMORY
CONTROLLER
I
I
22 Am9016s OR Am9064s
00
AS
I
I
--+--+-I
I
--+--+---+--+--
AD DR
ADDR
I
I
22 Am9016s OR Am9064s
I
HAS,
RAS3
1-----1 CAS
AmZ8166
I
2j Am9016s OR Am906j"
I
I
I
I
22 Am9016s OR Am9064s
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
.--------i
AmZ8166
~~
/------------------------------t
Ao
AmZ8163
REFRESH
AND EDC
CONTROLLER
AmZ8127
CLOCK GENI
CONTROLLER
BLI·221
·Address and RAS/CAS drivers each drive 22 RAM inputs at each output. Timing skew is minimized by
using one device for address lines and one device for RAS/CAS, spreading the CAS loading over four
drivers to equalize the capacitive load on each driver.
DYNAMIC MEMORY CONTROL WITH ERROR DETECTION AND CORRECTION
Metallization and Pad Layouts
AmZ8165
AmZ8166
1G
1
19
2G
1G
1
19
2G
1Y1
1A1
2
18
1Y1
1A1
2
18
2Y4
3
17
2A4
2Y4
3
17
2A4
1A2
4
16
1Y2
1A2
4
16
1Y2
2Y3
5
15
2A3
2Y3
5
15
2A3
1A3
6
14
1Y3
1A3
6
14
1Y3
2Y2
7
13
2A2
2Y2
7
13
2A2
1A4
8
12
1Y4
1A4
8
12
1Y4
2Y1
9
11
2A1
2Y1
9
11
2A1
DIE SIZE 0.094" X 0.060"
DIE SIZE 0.094" X 0.060"
8-56
AmZ8165· AmZ8166
ORDERING INFORMATION
Order the part number according to the table below to obtain the desired package, temperature range, and screening level.
AmZ8165
Order Number
AmZ8166
Order Number
Package
Type
Temperature
Range
Screening
Level
AMZ8165PC
AMZ8165DC
AMZ8165DM
AMZ8166PC
AmZ8166DC
AMZ8166DM
P-20
D-20
D-20
C
C
M
C-1
C-1
C-3
AMZ8165XC
AMZ8165XM
AMZ8166XC
AMZ8166XM
Dice
Dice
C
M
} Visual Inspection
to MIL-STD-883
Method 2010B.
Notes: 1. P = Molded DIP, D = Hermetic DIP. Number following letter is number of leads.
2. C = 0 to 70°C, Vee = 4.50 to 5.50V, M = -55 to +125°C, Vee = 4.50 to 5.50V.
3. Levels C-"I and C-3 conform to MIL-STD-883, Class C. Level B-3 conforms to MIL-STD-883, Class B.
8-57
Am3212· Am8212
Eight-Bit Input/Output Port
Distinctive Characteristics
• Fully parallel, 8-bit data register and buffer replacing
latches, multiplexers and buffers needed in microprocessor systems.
• 4.0V output high voltage for direct interface to MOS
microprocessors, such as the Am9080A family.
• Input load current 250JlA max.
• Reduces system package count
• Available for operation over both commercial and
military temperature ranges.
• Advanced Schottky processing with 100% reliability
assurance testing in compliance with M I L-STD-883.
• Service request flip-flop for interrupt generation
• Three-state outputs sink 15mA
• Asynchronous register clear with clock over-ride
FUNCTIONAL DESCRIPTION
CONNECTION DIAGRAM
Top View
All of the principal peripheral and input/output functions
of a Microcomputer System can be implemented with the
Am3212. Am8212. The Am3212 • Am8212 input/output
port consists of an 8-latch with 3·state output buffers along
with control and device selection logic, which can be used to
implement latches, gated buffers or multiplexers.
os;
LOGIC DIAGRAM
MO
vcc
MO
INT
01,
01 8
DO,
0°8
01 2
01 7
0°2
0°7
01 3
01 6
0°3
0°6
01 4
01 5
0°4
0°5
STB
CLR
GNO
OS2
STB
011
001
Note: Pin 1 is marked for orientation.
LlC-424
01 2
PIN DEFINITION
00 2
00 3
00 4
005
0I,- DI 8
DATA IN
DO,- D08
DATA OUT
DS,- DS 2
DEVICE SELECT
MD
MODE
STB
STROBE
INT
INTERRUPT (ACTIVE LOW)
CLR
CLEAR (ACTIVE LOW)
00 6
ORDERING INFORMATION
00 7
DOS
CLR
8-58
Package
Type
Temperature
Range
Order
Number
Hermetic DIP
Hermeti~ DIP
Molded DIP
Dice
Hermetic DIP
Hermetic 0 I P
Molded DIP
-55°C to +125°C
aOc to +7aoC
aOc to +7aoC
aOc to +7aoC
aOc to +7aoC
-55°C to +125°C
aOc to +7aoC
AM8212DM
08212
P8212
AM8212XC
03212
MD3212
P3212
Am3212 • Am8212
FUNCTIONAL DESCRIPTION (Cont'd)
MD (Mode)
Data Latch
This input is used to control the state of the output buffer and
to determine the source of the clock input (C) to the data
latch.
The 8 flip-flops that make up the data latch are of a "0" type
design_ The output (0) of the flip-flop will follow the data
input (0) while the clock input (C) is high. Latching will occur
when the clock (C) returns low.
When MO is high (output mode) the output buffers are enabled and the source of clock (C) to the data latch is from the
device selection logic (DS1 • DS2)_
The data latch is cleared by an asynchronous reset input
(CLR). (Note: Clock (C) Overrides Reset (CLR)).
When MO is low (input mode) the' output buffer state is
determined by the device selection logic (DS1 . OS2) and the
source of clocl~ (C) to the data latch is the STB (Strobe) input.
Output Buffer
The outputs of the data latch (0) are connected to 3-state,
non-inverting output buffers. These buffers have a common
control line (EN); this control line either enables the buffer
to transmit the data from the outputs of the data latch (0)
or disables the buffer, forcing the output into a high impedance state. (3-state). This high-impedance state allows the
Am3212 • Am8212 to be connected directly onto the microprocessor bi-directional data bus.
STB (Strobe)
This input is used as the clock (C) to the data latch for the
input mode MO = 0) and to synchronously reset the service
request flip-flop (SR).
Note that the SR flip-flop is negative edge triggered.
Service Request Flip-Flop
Control Logic
The SR flip-flop is used to generate and control interrupts
in microcomputer systems. It is asynchronously set by the
CLR input (active low). When the (SR) flip-flop is set it is in
the non-interrupting state.
The Am3212 • Am8212 has control inputs OS" OS2, MO
And STB. These inputs are used to control device selection,
data latching, output buffer state and service request fli p-flop.
DS 1 , DS 2 (Device Select)
These 2 inputs are used for device selection. When OS1 is low
and OS2 is high (OS1 • OS2) the device is selected. In the
selected state the output buffer is enabled and the service
request flip-flop (SR) is asynchronously set.
The output of the (SR) flip-flop (Q) is connected to an inverting input of a "NOR" gate. The other input to the "NOR"
gate is non-inverting and is connected to the device selection
logic (OS1 . OS2). The output of the "NOR" gate (lNT) is
active low (interrupting state) for connection to active low
input priority generating circuits.
TRUTH TABLE
STB
MD
DS 1 - DS 2
Data Out Equals
CLR
DS1-DS2
STB
SR*
INT
0
1
0
0
0
Three-State
0
1
1
1
1
0
1
Data Latch
0
0
1
0
0
1
0
0
0
0
0
0
Three-State
'-
1
1
0
Data Latch
1
1
0
1
0
0
1
Data Latch
1
0
0
1
1
1
0
1
Data In
1
1
\....
1
0
0
1
1
1
Data In
1
1
Data In
CLR - Resets Data Latch
- Sets SR Flip-Flop (no effect on Output Buffer)
• Internal SR Flip-Flop
Metallization and Pad Layout
,---------24
GNO
Vee
,-------23
INT
22
21
DiS
DOS
20
19
01 7
007
IS
17
01 6
00 6
16
15
015
005
'-----'---14
ill
DIE SIZE
'------13
OS2
0.091" X 0.112"
8-59
Am3212 • Am8212
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
Supply Voltage
Output Voltage
-O.5V to +7.0V
-O.5V to +7.0V
-1.0V to +5.5V
125mA
Input Voltages
Output Current (Each Output)
ELECTRICAL CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (Unless Otherwise Noted)
P8212, 08212, P3212, 03212 (COM'L)
Am82120M, M03212 (MIL)
T A = O°C to +70°C
T A = _55° C to +125° C
VCC = 5.0V ± 5%
VCC = 5.0V ± 10%
DC CHARACTERISTICS
Parameters
Typ.
Max.
Units
VF = 0.45V
-0.25
mA
Input Load Current MO Input
VF = 0.45V
-0.75
mA
Input Load Current OS1 Input
Input Leakage Current
ACK, OS, CR, 011 - 018 Inputs
VF = 0.45V
-1.0
mA
VR = 5.25V
10
/J A
/J A
/JA
Test Conditions
Description
IF
Input Load Current
ACK, OS2, CR, 011 - 018 Inputs
IF
IF
IR
Min.
(Note 1)
IR
Input Leakage Current MO Input
VR = 5.25V
30
IR
Input Leakage Current OS1 Input
VR = 5.25V
40
Vc
Input Forward Voltage Clamp
IC = -5.0mA
VIL
Input LOW Voltage
VIH
Input HIGH Voltage
VOL
Output LOW Voltage
VOH
COM'L
-1.0
MIL
-1.2
COM'L
0.85
MIL
0.80
Volts
2.0
Volts
Volts
0.45
10L = 15mA
10H = -1.0mA
Output HIGH Voltage
COM'L
3.65
4.0
MIL
3.3
3.4
4.0
MIL
10H = -0.5mA
ISC
Short Circuit Output Current
VO= OV
110 1
Output Leakage Current
High Impedance
Vo = 0.45V/5.25V
ICC
Power Supply Current
Note 2
Volts
4.0
-15
90
AC CHARACTERISTICS (Note 3)
Parameters
Volts
-75
mA
20
/J A
130
mA
Typ.
Description
Min.
(Note 1)
30
8
Max.
Units
tpw
Pulse Width
tpd
Data to Output Delay
12
30
ns
twe
Write Enable to Output Delay
18
40
ns
tset
Data Set-up Time
15
th
Data Hold Time
20
tr
Reset to Output Delay
18
ns
ns
ns
40
ns
ns
ts
Set to Output Delay
15
30
te
Output Enable/Disable Time
14
45
ns
tc
Clear to Output Delay
25
55
ns
CAPACITANCE (Note 4)
TEST LOAD (15mA and 30pF)
F = 1.0MHz, vBIAS = 2.5V, VCC = +5.0V, TA = 25°C
Typ_
Max_
Units
CIN
OS1 MO Input Capacitance
9.0
12
pF
CIN
OS2, CK, ACK, 011-018
Input Capacitance
5.0
9.0
pF
001-008 Output Capacitance
8.0
Parameters
COUT
Description
300n
TO D. U. T.
12
0----.---....
pF
Notes: 1. Typical limits are at VCC = 5.0V, 25°C ambient and maximum loading.
.
2. CLR = STB = HIGH; OS1 = OS2 = MO = LOW; all data inputs are gound, all data outputs are open.
3. Conditions of Test: a) Input pulse amplitude = 2.5V
b) Input rise and fall times 5.0ns
c) Between 1.0V and 2.0V measurements made at 1.5V with 15mA and 30pF Test Load.
4. This parameter is sampled and not 100% tested.
8-60
'30pF
I
600n
'I ncluding Jig and Probe
Capacitance.
LlC-42S
Am3212 • Am8212
TIMING DIAGRAM
DATA
15V
x---------¥
15V
---'
STS or
1'--------
5Sj. DS 2
OUTPUT
OUTPUT
I
'''\
DO
---\./
v----1j'-_____ _
~tSET
I
15V
1.5V.71\.
DATA
'''.''''."'0
OUTPUT
STS
_ _ _ --'
-
L'"":;.1 __
'''\
-'~'
t\
~'ffll
~tR:j
'''\
. Test Load.
Note: Alternative
l~
"",0
30 PF
~"1
111~
I
":"
lk
8-61
Am3212 • Am8212
TYPICAL CHARACTERISTICS
~
Vcc = 5.0V
-50
I
~'f'
'i
",VI
Vcc = 5.0V
I
~
a: -150
-200
I
~
Cl
f-
-2
~
:::>
u
f-
~
f-
f-
:::>
:::>
o
-1
1.0
INPUT VOLTAGE - VOLTS
OUTPUT LOW VOLTAGE - VOLTS
Data to Output Delay
Versus Load Capacitance
Data to Output Delay
Versus Temperature
Vcc = 5.0V
T A = 25°C
22
Vcc
c:
I
~
"
f-
:::>
.... I ~_
20 r-t++
<{
10 r---';t-----+---t---1---+---1
<{
f-
12r---+----r---+----r-~
<{
100
150
200
250
o
o
25
JB
DS 2
f5._,.., ......... t-+-
20
1--:':'-
~
15
tsIZ.
a:
$:
300
25
-25
50
75
100
t+t
DS 1
I
10
-25
TEMPERATURE _ °c
LOAD CAPACITANCE - pF
t++
L ....
-r
-"
w
10~-~-~-~---~~
-!:
__ .f.-
f-
O~~-~-~-~-~~
50
30
III
<{
Cl
o
~
w
of-
Cl
f-
f-
o
~r--
35
:::>
f-
f-
5.0
Vcc = 5.0V
~
Cl
t++
18r---+----r---+~~r_--1
~
o
o
4.0
40
>-
Cl
30r-~--_+--_r--~--+_
....
~
3.0
VOLTAGE - VOLTS
Write Enable to Output Delay
Versus Temperature
~ 5.0V
>-
2.0
OUTPUT HIGH
20
I
40r-~---+---r--~--+---1
~
~
40r---_+-----r~~1_---1
~
:::>
:::>
u
o
-3
>-
~
f-
f-
TA=&c
-300
I
I
60r---_+-----r----~~~
:::>
-250
c:
E
I
~
~
<{
E
f-
!-'V
:::>
80r---_+-----r----~---1
<{
-' TA = 75°C_
u
~
100 r-----r---r---...,-----,
TA =.25°C_
I -100
f-
Output Current Versus
Output HIGH Voltage
Output Current Versus
Output LOW Voltage
Input Current Versus
Input Voltage
50
25
75
100
TEMPERATURE - °c
LlC-42B
LOGIC SYMBOLS
OUTPUT DEVICE
INPUT DEVICE
11
11
STS
DI
Detailed
DO
DI
STS
DO
10
10
15
16
17
1B
20
19
20
19
22
21
22
21
16
1S
Am3212
Am8212
Am3212
Am8212
15
17
14
LlC-429
LlC-430
-=
Vee
INPUT
STROBE _
Symbolic
OUTPUT
FLAG
SYSTEM
OUTPUT
SYSTEM
INPUT
LlC-431
_
LlC-432
DATA BUS
8-62
Am3212· Am8212
TYPICAL APPLICATIONS OF THE Am8212
VCC--~~---------------'
GATED BUFFER (3-STATE)
STB
By tying the mode signal low and the strobe input high, the
data latch is acting as a straight through gate. The output
buffers are then enabled from the device selection logic OS,
and OS2.
INPUT
DATA
(250MA)
When the device selection logic is false, the outputs are 3-state.
OUTPUT
DATA
(15mA)
(3.65V MIN.)
Am3212
AmB212
When the device selection logic is true, the input data from the
system is directly transferred to the output.
L....---------OI CLR
GATING { - CONTROL
DS 2 )
,=--=-~-----------------'
(DSj -
LlC·433
Bi-Directional Bus Driver
Two Am3212 • Am8212's wired back-to back can be used as
a symmetrical drive, bi-directional bus driver. The devices are
controlled by the data bus input control which is connected
to OS1 on the first Am3212 • Am8212 and to OS2 on the
second. While one device is active, and acting as a straight
through buffer the other is in its 3-state mode.
STB
DATA
f------------'
BUS ~--......,..,------...,
Am3212
AmB212
1 - - - ' - - - - - - ( DATA
BUS
DATA BUS CONTROL
STB
Am3212
AmB212
LlC·434
Interrupting Input Port
INPUT
STROBE
The Am3212 • Am8212 accepts a strobe from the system
input source, which in turn clears the service request flip·flop
and interrupts the processor. The processor then goes through
a service routine, identifies the port, and causes the device
selection logic to go true - enabling the system input data
onto the data bus.
DATA BUS
SYSTEM
INPUT
SYSTEM
RESET
L....-~""""'---_
TO CPU
INTERRUPT INPUT
LlC·435
8-63
Am3212 • Am8212
TYPICAL APPLICATIONS OF THE Am8212 (Cant'd)
Interrupt Instruction Port
Output Port (With Hand-Shaking)
The Am3212 • Am8212 can be used to gate the interrupt
instruction, normally RESTART instructions, onto the data
bus. The device is enabled from the interrupt acknowledge
signal from the microprocessor and from a port selection signal. This signal is normally tied to ground. (OS1 could be
used to multiplex a variety of interrupt instruction ports onto
a common bus).
The Am3212 • Am8212 is used to transmit data from the
data bus to a system output. The output strobe could be a
hand-shaking signal such as "reception of data" from the device that the system is outputting to. It in turn, can interrupt
the system signifying the reception of date. The selection of
the port comes from the device selection logic. ~OS1· OS2).
DATA BUS
RESTART
INSTRUCTION
IRST 0- RST 7)
. . . . - - - - - - OUTPUT STROBE
DATA BUS
STB
STB
Am3212
AmB212
Am3212
AmB212
SYSTEM OUTPUT
SYSTEM RESET
PQ!l.T_
SELECTION (OS1) _ _ _ _.....
LlC·436
SYSTEM - INTERRUPT
INTERRUPT - - - - - - - - - '
ACKNOWLEOGE-
L-~-=--_ _ _ _--'-
PORT SELECTION
I~CH CONTROL)
} IOS1- 2)
0S
--
LlC-437
Am9080A Status Latch
The input to the Am3212 • Am8212 latch comes directly
from the Am9080A data bus. Timing shows that when
the SYNC signal is true (OS1 input). and 1 is true,
(OS1 input) then the status data will be latched into the
Am3212 • Am8212. The mode signal is tied high so that
the output on the latch is active and evabled all the time.
/:0
---------
01
°
2
03
04
05
Am9080A
06
07
B
7
3
4
5
6
DO
01
O2
03
DATA BUS
04
05
06
07
19
SYNC
17
OBIN
¢1
-
¢2
22
STATUS LATCH
15
12Vr\.
ovJ
\...-
3
"---- 0 1
5
~ :------'p
4
DO
6
-
7
8
-
9
15
r-17
r-19
r-21
r---
20
22
~
STACK
f o - - HLTA
Am3212
AmB212
18
~TL)
W6
10
16
CLOCK GEN.
& DRIVER
r---- INTA
CIA
OS2
MO
DATA
OUT
M1
INP
BASIC
STATUS
CONTROL _ _ _ _
-+-'
BUS
MEMR
OS1
13
1
2f
OBIN
1
VCC
8-64
LlC·43B
Am3216 • Am3226 •Am8216 •Am8226
Four-Bit Parallel Bidirectional Bus Driver
Distinctive Characteristics
• Output high voltage compatible with direct interface
to MOS
• Three-state outputs
• Advanced Schottky processing
• Available in military and commercial temperature
range
• Am3226 and Am8226 have inverting outputs
• Data bus buffer driver for 8080 type CPU's
• Low input load current - 0.25mA maximum
• High output drive capability for driving system data
bus - 50mA at 0.5V
• 100% reliability assurance testing in compliance with
MI L-STD-883
• Am3216 and Am8216 have non-inverting outputs
FUNCTIONAL DESCRIPTION
I
The Am3216, Am3226, Am8216 and Am8226 are four-bit,
bi-directional bus drivers for use in bus oriented applications.
The non-inverting Am3216 and Am8216, and inverting
Am3226 and Am8226 drivers are provided for flexibility in
system design.
together so that the driver can be used to buffer a true bi-directiona I bus. The DO outputs on this side of the driver have a
special high voltage output drive capability so that direct interface to the 8080 type CPUs is achieved with an adequate
amount of noise immunity.
Each buffered line of the four bit driver consists of two
separate buffers that are three-state to achieve direct bus interface and bi-directional capability. On one side of the driver the
output of one buffer and the input of another are tied together
(DB), this side is used to interface to the system side components such as memories, I/O, etc., because its interface is
TTL compatible and it has high drive (50mA). On the other
side of the driver the inputs and outputs are separated to
.provide maximum flexibility. Of course, they can be tied
The CS input is a device enable. When it i~ "high" the output
drivers are all forced to their high-impedance state. When it is
a "LOW" the device is enabled· and the dir~ction of the data
flow is determined by the DIEN input.
The DIEN input controls the direction of data flow which is
accomplished by forcing one of the pair of buffers into its high
impedance state and allowing the other to transmit its data. A
simple two gate circuit is used for this function.
LOGIC DIAGRAMS
Am3216 • Am8216
Am3226 • Am8226
01 0 O - - - - - I > - - _ + _ - - - .
01 0 o----t:><>--+----,
DBa
000 o--t---<>Cu---t-----'
000 o - - f - - - - < ; . I - - + - - - '
Ol,o--+----I>--_+_---.
01,
o--t---t:><>--+_---,
DO,
0--1--O-_+_-,
01 2 0 - - + - - - - 1 >--_+_---.
OB 2
01 30--f---[:><>--+_---,
OB 3
0030--f---<>C;.t---+_--'
LlC-439
OlEN 0 - - - + - + - - - - - - - '
OlEN 0 - - - + - + - - - - - - - '
'-----_+_----2 (TTL)
4>2 CLK (TTL LEVEL)
VCC
+5.0V
VDD
+12V
GND
OV
RESIN
RESET INPUT
RESET
RESET OUTPUT
RDYIN
READY INPUT
READY
READY OUTPUT
SYNC
SYNC INPUT
STSTB
STATUS STB (ACTIVE LOW)
¢1
4>1
¢2
4>2
Am9080A/8080A CLOCKS
10
¢2 ITTL )
SYNC
-------+---1
J
STSTB
RESET
RDYIN
-------+--1 D
Q
CONNECTION DIAGRAM
Top View
1 - - - - - - READY
lIC-619
RESET
ORDERING INFORMATION
XTAL 1
RDYIN
XTAL 2
READY
Package
Type
Temperature
Range
Order
Number
Hermetic DIP
Hermetic DIP
Molded DIP
Dice
Hermetic DIP
-55°C to +125°C
O°C to +70°C
O°C to +70°C
O°C to +70°C
O°C to +70°C
AM8224DM
D8224
AM8224PC
AM8224XC
AM8224-4DC*
SYNC
¢2 ITTL)
STSTB
GND
* For use with Am9080A-4 with clock period between 250ns and 320ns.
VCC
RESIN
TANK
OSC
¢1
¢2
VDD
Note: Pin 1 is marked for orientation.
8-70
lIC-620
Am8224
MAXIMUM RATINGS
(Above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
Supply Voltage to Ground Potential
VCC
7.5V
VDD
15V
Maximum Output Current 1 and 2 (Note 1 )
100mA
ELECTRICAL CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
The Following Conditions Apply Unless Otherwise Noted:
Am8224XC, Am82244XC (COM'L)
Am8224XC (MIL)
Parameters
T A = O°C to +70°C
T A = -55°C to +125°C
Description
VCC = 5.0V ± 5%
VCC=5.0V± 10%
VDD = 12V ± 5%
VDD = 12V ± 10%
Test Conditions
Typ.
(Note 2)
Min.
Max.
Units
IF
I nput Current Loading
VF = 0.45V
-0.25
mA
IR
Input Leakage Current
VR = 5.25V
10
J,LA
Vc
Input Forward Clamp Voltage
VIL
Input LOW Voltage
VIH
VIWVIL
Input HIGH Voltage
RESIN Input Hysteresis
IC = -5.0mA
COM'L
-1.0
MIL
-1.2
VCC = 5.0V
0.8
COM'L
Reset input
MIL
Volts
Volts
2.6
2.2
2.8
2.2
Volts
0.5
Volts
All other inputs
2.0
VCC = 5.0V
0.25
(4)1, 4>2), Ready, Reset, STSTB
0.45
IOL = 2.5mA
VOL
Output LOW Voltage
Volts
All other inputs
IOL = 15mA
0.45
4>1,4>2; IOH = -100J,LA
VOH
Output HIGH Voltage
READY, RESET; IOH = -100J,LA
COM'L
9.4
COM'L
MIL
All other outputs; IOH = -1.0mA
ISC
Output Short Circuit Current
(All Low Voltage Outputs Only)
11
VDD -1.6V VDD-1.0V
MIL
Vo =OV
3.6
4.0
3.35
4.0
2.4
3.0
Volts
-10
VCC = 5.0V
mA
-60
ICC
Power Supply Current
VCC = MAX. (Note 3)
70
115
mA
IDD
Power Supply Current
VDD = MAX.
5.0
12
mA
Notes: 1. Caution: 4>1 and 4>2 outputs do not have short circuit protection.
2. Typical limits are at VCC = 5.0 V, Voo = 12 V, 25°C ambient and maximum loading.
3. For conditions shown as MI N. or MAX., use the appropriate value specified under Electrical Characteristics for the applicable device type.
TEST CI RCUIT
CRYSTAL REQUIREMENTS
VCC
(
Tolerance: .005% at 0° C - 70° C
Resonance: Series (F undamental) *
Load Capacitance: 20-35pF
Equivalent Resistance: 75-20 ohms
Power Dissipation (Min): 4mW
Rl
INPUT
lC L
I
*With frequency in excess of 18MHz
use 3rd overtone XTALs and tank
circuit.
R2
~
lIe·621
8-71
Am8224
AC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
Am8224·4XC
Am8224XM
Parameters
Description
Test Conditions
Min.
Typ.
Max.
Min.
<1>1 Pulse Width
2tCY
---23ns
9
2tCY
---20ns
9
t2
<1>2 Pulse Width
5tCY
---35ns
9
0
5tCY
---35ns
9
0
2tCY
- - -17ns
9
2tCY
---14ns
9
tl
tOl
<1>1 to <1>2 Delay
tD2
<1>2 to <1>1 Delay
t03
<1>1 to <1>2 Delay
Cl =20pF
to 50pF
2tCY
tr
<1>1 and <1>2 Rise Time
tf
<1>1 and <1>2 Fall Time
to2
<1>2 to <1>2 (TTL) Delay
toss
<1>2 to STSTB Delay
tpw
STSTB Pulse Width
tORS
RDYIN Set·up Time
to Status Strobe
tORH
RDYIN Hold Time
After STSTB
tDR
ROYIN or RESIN
to 92 Delay
tClK
ClK Period
fMax.
Maximum Oscillating
Frequency
Cin
2tCY
--+22ns
9
9
<1>2 (TTL).
Cl = 30pF
Rl = 300n
R2 = 600n
STSTB,
Cl=15pF,
Rl = 2.0kn
R2 = 4.0kn
Ready and Reset
Cl = 10pF
Rl = 2.0kn
R2 = 4.0kn
Vec
= +5.0V
Min.
Max.
Typ.
Max.
110
0
ns
35
2tCY
--+20ns
9
76
55
20
20
20
20
20
20
6tCY
9
tCY
--18ns
9
4tCY
50ns--9
Units
45
9
15
15
-5.0
6tCY
6tCY
---30ns
9
--
-5.0
15
137
167
ns
9
tCY
--15ns
9
4tCY
50ns--9
18
ns
-61
4tCY
111
9
4tCY
---25ns
9
4tCY
---25ns
9
tCY
9
9
27
28
28.12
VCC = 5.0V
VOO = 12V
VBIAS = 2.5V
f = 1.0MHz
ns
86
tCY
-
AC CHARACTERISTICS (For
Typ.
2tCY
4tCY
-9-
Input Capacitance
Parameters
-5.0
6tCY
---33ns
9
(Note 2)
Am8224XC
MHz
36
8.0
8.0
pF
8.0
tCY = 488.28n5)
±5%
Voo
Description
= +12V
±5%
Test Conditions
Min.
Typ.
Max.
Units
t1
<1>1 Pulse Width
89
ns
t2
<1>2 Pulse Width
236
ns
0
ns
tD1
Delay <1>1 to <1>2
tD2
Delay <1>2 to <1>1
tD3
Delay <1>1 to <1>2 Leading Edges
tr
Output Rise Time
20
ns
tf
Output Fall Time
20
ns
tDSS
<1>2 to STSTB Delay
tD'i'>2
<1>2 to <1>2 (TTL) Delay
tpw
Status Strobe Pulse Width
tDRS
RDYIN Set-up Time to STSTB
tDRH
RDYIN Hold Time After STSTB
tDR
Ready or Reset to <1>2 Delay
FREQ
Oscillator
<1>1 and <1>2 Loaded
CL = 20 to 50pF
95
109
Ready and Reset Loaded
CL = 20 to 50pF
R1 = 2.0kfl. ,R2 = 4.0kfl.
Fre~uency
ns
129
ns
296
326
ns
-5.0
15
ns
40
ns
-167
ns
217
ns
192
ns
18.432
MHz
Notes: 1. All measurements referenced to 1.5V unless specified otherwise.
2. Am8224-4 parameter limits are given for tCY = 250ns or an oscillating frequency of 36MHz. Between 28.12MHz and 36MHz min. and max. limits
should be ratioed between the calculated Am8224XC limits at 28.12MHz and the given 36MHz parameter limits.
8-72
Am8224
SWITCHING WAVEFORMS
---l-tFr--tcv-------t1
1,~I--L
~l------Ji--f~,. ~X_ _ _/
l--::;~l---t¢2------Jr'''--4
"
'""~--
--,""ij I
If
."n"
SYNC
(FROM 8080AI
I'"'
""_________________
\'--__~--JI
I
1f------tDSS---,----1-----0--1--1tpw,
STSTB~~---------------~----~~~-------
j ~ ' "'
' ""
OR ~~~:~==*==
I
==*=----1-----------------
___======_--x=-___
It_""-1~_ __
RE~~~
I___________________
~'''~
t _ _ _ _ __
RESET
OUT
Voltage measurement points: ¢" ¢2 Logic "0" = 1.0V, Logic "'"
All other signals measured at '.5 V.
=
a.ov.
LlC-622
To avoid the unwanted oscillation and increase the desired
frequency output it is necessary to provide a parallel tuned
resonant circuit of low impedance. The external LC network is
connected to the TANK input and is AC coupled. See typical
application with Am8228 and Am9080A in Figure 2.
Oscillator
The oscillator circuit derives its basic operating frequency
from an external, series resonant, fundamental mode crystal.
Two inputs are provided for the crystal connections (XT AL 1,
XTAL2).
The formula for the LC network is:
The selection of the external crystal frequency depends mainly
on the speed at which the CPU is to be run. Basically, the
oscillator operates at 9 times the desired processor speed.
F ==
1
211 y'I'C
The output of the oscillator is buffered and brought out
on OSC (pin 12) so that other system timing signals can be
derived from this stable, crystal-controlled source.
The formula to determine the crystal frequency is:
Clock Generator
f(XTAL) ==
times 9
The Clock Generator consists of a synchronous "divide by
nine" counter and the associated decode gating to create the
waveforms of the two clocks and auxiliary timing signals.
tCY
When using crystals above 1OMHz a small amount of frequency
"trimming" is necessary to produce the desired frequency. The
addition of a selected capacitance (20pF - 30pF) in series
with the crystal will accomplish this function.
The waveforms generated by the decode gating follow a
simple 2-5-2 digital pattern. See Figure 2. The clocks generated; cp, and CP2, can best be thought of as consisting of
"units" based on the oscillator frequency. Assume that one
"unit" equals the period of the oscillator frequency. By multiplying the number of "units" that are contained in a pulse
width or delay, times the period of the oscillator frequency,
the approximate time in nanoseconds can be derived.
Another input to the oscillator is TANK. This input allows
the use overtone mode crystals. This type of crystal generally
has a much lower output at its rated frequency and has a tendency to oscillate at its fundamental.
8-73
Am8224
The outputs of the clock generator are connected to two
high level drivers for direct interface to the CPU. A TTL level
phase 2 is also brought out 1>2 (TTL) for external timing
purposes. It.is especially useful in OMA dependent activities.
This si~nal is used to gate the requesting device onto the bus
once the CPU issues the Hold Acknowledgement (H LOA).
flop is required. The Am8224 has this feature built-in. The
ROYIN input presents the asynchronous "wait request" to
the "0" type flip-flop. By clocking the flip-flop with 1>20, a
synchronized READY signal at the correct input level, can be
connected directly to the CPU.
Several other signals are also generated internally so that
optimum timing of the auxiliary flip-flops and status strobe
(STSTB) is achieved.
USED ONLY FOR
OVERTONE CRYSTALS
I---~
Dh
IrGJl
L~2'~
lUNIT
-.J
-±I
I"
13
12
14
20pf-30pf
(ONLY NEEDED
ABOVE 10M Hz)
15
TANK
OSC
1
=--
~2(TTL)
OSC.
FREe
RDYIN
~J
CC
1 : 2 : 3
I
I
MANUAL
2
_AmB224
RESIN
19
SYNC
RESET
EXAMPLE: ICY - 500n,
DSC - 18mHz/55n,
~1 = 11 On, (2 x 55n,)
~2· 275n, (5 x 55n,)
~2-~1 - liOn, (2 x 55n,).
STSTB (TO AmB22B PIN'1)
LlC-624
LlC-623
Figure 1. Clock Generator Waveforms.
Figure 2. Typical Application with Am8224
and Am9080A.
STSTB (Status Strobe)
APPLICATION PRECAUTIONS WHEN USING Am8224 UP
TO 36MHz
At the beginning of each machine cyCle the CPU issues status
information on its data bus. This information tells what type
of action will take place during that machine cycle. By bringing
in the SYNC signal from the CPU, and gating it with an internal timing signal (1), A), an active low strobe can be derived
that occurs at the start of each machine cycle at the earliest
possible moment that status data is stable· on the bus. The
STSTB signal connects directly to the Am8228 System Controller.
Usage with Third Harmonic Crystal or Am9080A-4
The use of the Am8224 with a third harmonic crystal requires
a minor modification to the external circuitry associated with
the Am8224. The changes are as follows:
- Series capacitor in conjunction with the xtal
- Adding a tuned circuit in the "tank" lead
- Tuning of circuit to proper frequency
The power-on Reset also generates STSTB, but of course,
for a longer period of time. This feature allows the Am8228
to be automatically reset without additional pins devoted for
this function.
It is necessary to maintain the crystal activity to a proper level
if an xtal controlled circuit is to operate properly. A 20-30pfd
capacitor placed in series will help achieve this level in third
overtone crystal, while helping .to suppress the fundamental
mode. The Am8224 has an auxiliary port provided to allow
for a tuned circuit. This tuned circuit eliminates the tendency
of the circuit to oscillate at the crystal's fundamental. The
tank or tuned circuit must have the following properties:
Power-On Reset and Ready Flip-Flops
A common function in microcomputer systems is the generation of an automatic system reset and start-up upon initial
power-on. The Am8224 has a built-in feature to accomplish
this feature.
An external RC network is connected to the R ESI N input.
The slow transition of the power supply rise is sensed by an
internal Schmitt Trigger. This circuit converts the slow transition into a clean, fast edge when its input level reaches a
predetermined value. The output of the Schmitt Trigger is
connected to a "0" type flip-flop that is clocked with 1>20
(an internal timing signal). The flip-flop is synchronously
. reset and an active high level that complies with the microprocessor input spec is generated. For manual switch type
system Reset circuits, an active low switch closing can be
connected to the R ESI N input in addition to the power-on
RC network.
1. It must be parallel resonant at the crystal frequency (third
order).
2. The off resonance impedance must be low enough to spoil
the AC gain of the Am8224.
3. The circuit must be DC decoupled (or returned to VCC) at
a low impedance (substantially below lOOn).
All frequency determining components must be in close proximity to the Am8224. Insert crystal and tune tank for best
waveform at Pin 12 (OSC). If counter is available, adjust for
match of crystal marking. The circuit in Figure 3 will accomplish the above result for the 36MHz range.
The READY input to the CPU has certain timing specifications
such as "set-up and hold" thus, an external synchronizing flip8-74
Am8224
Vee Ground
C4
20-30pF
RESET
VCC
RESIN
S~36MHZ
c:::J
T
XTAL 1
THIRD
OVERTONE
XTAL 2 _ _ _ _ _
..J
RDYIN
C2>
1000pF
Due to the nature of our device (fast switching, higher voltage)
it is necessary to provide a bypass capacitor from Vec to
ground in the immediate proximity of the Am8224. This
insures proper operation of the device while reducing noise
spiking on adjacent circuits.
READY
C1
5-30pF
SYNC
2 ITTL )
Resin Bypass
STSTB
GND
The use of a high impedance capacitor for timing R-C, and/or
timing components remotely located from the Am8224 device
may cause a disturbance to occur during the linear transition
region. The capacitor for this function should be of the ceramic
type and a value of 1000pF or greater.
LlC-625
Figure 3.
C1
= E.F.
L1
=
This can be cured by placing a >1000pfd ceramic capacitor
from Resin (Pin 2) to Ground (Pin 8) in the immediate proximityof the device. This will allow the timing R-C to be placed
at will.
Johnson
275-0430-005
5-30pF Trimmer or Equiv.
J.W. Miller Inductor
9230-08
APPLICATIONS
The Am8224 can be driven from an external source of frequency by connecting as shown and driven with approximately
500mV over a wide frequency range.
------tl f---o ~:pTUETRNAL
10,OOOpF
LlC-626
The Am8224 can oscillate without a xtal by placing a small
value capacitor (10 .... 200pF) in place of a crystal.
RESET
Vcc
RESIN
XTAL 1
RDYIN
XTAL2
---.I
TANK
NC
READY
SYNC
2ITTL)
STSTB
GND
~
osc
<1>1
2
VDD
Lle-627
8-75
Am8224
Metallization and Pad Layout
RESET
1----------,
RESIN
2 -----,
RDYIN
3
READY
4
SYNC
5
¢21TTL1
6
STSTB
GND
. - - - - - - - - 16
XTAL 1
.11'f'IHH---14
XTAL2
--t-..!.r
7 -----'
VCC
r - - - - - 15
13
TANK
12
OSC
'-------10
B ---------'
¢2
V DD
DIE SIZE 0.085" X 0.084"
8-76
Am8228· Am8238
System Controller and Bus Driver for 8080A Compatible Microprocessors
Distinctive Characteristics
• Multi-byte instruction interrupt acknowledge
• Selectable single level vectored interrupt (RST-7)
• 2S-pin molded or hermetic DIP package
• Single chip system controller and data bus driver for
Am90S0/S0S0A systems
• AmS23S-4 high speed version available for use with
1J.l,sec instruction cycle of Am90S0A-4
• Bi-directional three-state bus driver for CPU independent operation
• Advanced low-power Schottky processing
• 100% reliability assurance testing in compliance with
MI L-STD-SS3
• Available in military and commercial temperature
range
• AmS23S has extended IOW/MEMW pulse width
FUNCTIONAL DESCRIPTION
LOGIC SYMBOL
The Am8228 and Am8238 are single chip System Controller
Data Bus drivers for the Am9080A Microcomputer System.
They generate all control signals required to directly interface
Am9080A/8080A compatible system circuits (memory and
I/O) to the CPU.
Bi-directional bus drivers with three-state outputs are provided
for the system data bus, facilitating CPU independent bus
operations such as direct memory access. Interrupt processing
is accommodated by means of a single vectored interrupt or
by means of the standard a080A multiple byte interrupt vector
operation.
13
15
17
16
12
11
10
9
6
19
18
21
20
8
23
24
LOGIC DIAGRAM
26
25
DO
27
0,
O2
CPU
DATA
BUS
03
04
SYSTEM
DATA
BUS
BI-OI RECTIONAL
BUS DRIVER
05
Os
Vee
07
GND
= Pin
= Pin
28
14
LlC-629
CONNECTION DIAGRAM
Top View
ffifB _ -_ _ _ _ _ _ _ _....J
OBIN
---------------1
~-------------_o
HLOA
LIC-628
---------------f
Molded DIP
Hermetic DIP
Hermetic DIP
Dice
Hermetic DIP
Molded DIP
28
Vce
HLDA
27
i70W
WR
26
MElViW
DBIN
25
IIOA
DB4
24
MEMA
04
23
iNi'A
DB7
22
BiJS'E'N
21
06
20
DBe
~_ _....1
ORDERING INFORMATION
Package
Type
mrs
Temperature
Range
O°C to +70°C
o
O°C to +70 C
-55°C to +125°C
O°C to +70°C
OOC to +70°C
OOC to +70°C
Am8228
Order
Number
AM8228PC
08228
AM8228DM
AM8228XC
Am8228
Am823B
07
Am8238
Order
Number
DB3
AM8238PC
08238
AM8238DM
AM8238XC
AM8238-4DC*
AM8238·4PC*
*For use with Am9080A-4 with minimum
clock period of 250ns.
03
10
19
05
DB2
11
18
DBS
02
12
17
01
DBa
13
Ie
OBI
GND
14
IS
Do
Note: Pin 1 is marked for orientation,
, 8-77
LIC-630
Am8228 • Am8238
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
Supply Volatge to Ground Potential (Pin 28 to Pin 14) Continuous
DC
DC
DC
DC
-0.5V to +7.0V
-0.5 V to +Vcc max.
Voltage Applied to Outputs for HIGH Output State
Input Voltage
Output Current, Into Outputs
Input Current
-1.5V to +7.0V
50mA
-30mA to +5.0mA
ELECTRICAL CHARACTERISTICS The Following Conditions Apply Unless Otherwise Noted:
Am8228XM, Am8238XM
Am8228XC, Am8238XC, Am8238-4XC
TA = -55°C to +125°C
o
T A = OoC to +70 C
VCCMIN.
VCCMIN.
= 4.50V
VCCMAX.
VCCMAX.
= 4.75V
= 5.50V
= 5.25V
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
Parameters
VOH
Description
Typ.
Test Conditions (Note 2)
Output HIGH Voltage
VCC= MIN.
10H = -10,uA
l
MIL
0 0 -0 7 \ COM'L
10H = -1.0mA All other outputs
VOL
Output Low Voltage
VCC = MIN.
10L
= MIN.,
Vc
Input Clamp Voltage (All Inputs)
VCC
VTH
Input Threshold Voltage (All Inputs)
VCC = 5.0V
IF
Input Load Current
VCC
= 2.0mA
10L = 10mA
= MAX.,
IC
VF
= MAX., VR
INTA Current
See INTA test circuit
10(OFF)
Offstate Output Current (All Control Outputs)
VCC = MAX., Vo
3.6
3.B
= 5.25V
lOS
Short Circuit Current (All Outputs)
VCC = 5.0V
Power Supply Current
VCC
Test
Conditions
Units
Volts
00- 0 7
0.45
All other outputs
0.45
Volts
-1.0
Volts
2.0
Volts
STSTB
-500
02 and 06
-750
All other inputs
-250
DBO-DB7
20
All other inputs
100
5.0
= 5.25V
100
-100
-90
-15
= MAX.
AC CHARACTERISTICS
OVER OPERATING TEMPERATURE RANGE
Max.
2.4
= 0.45V
ICC
Description
3.B
-0.75
= 0.45V
liNT
Parameters
3.35
O.B
VCC
Vo
(Note 1)
= -5.0mA
Input Leakage Current
IR
Min.
140
190
Am8228XM/
Am8228XC/
Am8238XM
Am8238XC
Am8238-4XC
Typ.
Typ.
Typ.
Min. (Note 1) Max. Min. (Note 1) Max. Min. (Note 1) Max.
,uA
,uA
mA
,uA
mA
mA
Units
tpw
Width of Status Strobe
22
22
22
ns
tss
Set-up Time, Status Inputs 00-07
12
S.O
S.O
ns
tSH
Hold Time, Status Inputs 00-07
5.0
Delay from STSTB to MEMR
20
30
60
20
30
60
20
30
40
20
30
60
20
30
60
20
30
45
20
30
60
20
30
60
20
30
60
Delay from STSTB to INTA, lOR
tDC
CL
Delay from STSTB to all other
Control Signals
tRR
Delay from DBIN to Control Outputs
tRE
Delay from DBIN to
BOSOA Bus
I
I
tRD
Delay from System Bus to BOSOA
Bus During Read
tWR
Delay from WR to Control Outputs
tWE
Delay to Enable System Bus DBO-DB7
After STSTB
two
Delay from BOSOA Bus 00-07 to
System Bus DBO-DB7 During Write
tE
Delay from System Bus Enable
to System Bus DBO-DB7
CL
= 25pF
5.0
CL
ns
5.0
= 100pF
Enable
Disable
5.0
= 100pF
5.0
ns
ns
15
35
15
30
15
30
25
45
25
45
12
20
25
45
25
45
25
35
15
30
15
30
15
20
ns
20
45
20
45
ns
25
36
25
30
ns
20
40
20
40
ns
25
35
20
30
ns
15
2S
15
25
5.0
5.0
20
45
25
30
20
40
25
30
15
25
5.0
5.0
ns
ns
tHO
HLDA to Read Status Outputs
tDS
Set-up Time, System Bus Inputs to HLDA
10
10
10
ns
tDH
Hold Time, System Bus Inputs to HLDA
20
20
20
ns
Notes: 1. Typical values are for T A = 25°C and nominal supply voltages.
2. For conditions shown as MIN. or MAX., use the appropriate value specified under electrical characteristics for the appl icable device type.
8-78
Am8228 • Am8238
CAPACITANCE (This parameter is periodically sampled and not 100% tested.)
Parameters
Description
Input Capacitance
Min.
(Note 1)
Max.
8.0
12
pF
7.0
15
pF
8.0
15
pF
VBIAS = 2.5V, VCC = 5.0V
T A = 25°C, f = 1.0MHz
Output Capacitance Control Signals
I/O
Typ.
Test Conditions
I/O Capacitance (D or DB)
Units
SWITCHING WAVEFORMS
~1
----------.u
H::t
STATUS STROBE
*
"4 r''"~ f,----~\
i\1 I
If'""
1J
AmBOBO
DATA BUS
DBIN
fOR.
I\
MEM R
'"''''"'"'
SYSTEM BUS
DURING READ
AmBOBOBUS
DURING READ
I
1 T'"
HLDA
INTA.
pw
----------------------"""'\v
I.
1
f,..--:..'-----
1
=1 -ft:::1
1
I-
------1- --all
-0
--------E
~'"'1_---------
I:::tDS-+-tDHI
------1----1
tHO
::-1
------I---tR~D
I I
-1~H--tOC·_-
_ _ _
*+____ *
DU~~~t?R~~~ - - - - - - - - - - - - -
- -
Du~~~6E~R~~~ -
\
f.
f
::::j
_ _
twR=B
--"--*
c _ t W R_ _
----J
I
-- -- -- -- ~--t---i
-- -- -- -- -- -- --
- ~tWD:::i
*,.--------------------
~
\~-tE--l-----'-f~tE
SYSTEM BUS _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
OUTPUTS
~
~
Voltage measurements points: DO - 07 (when outputs) Logic "0" = 0.8 V, Logic "1"
°Extended IOW/MEMW for Am8238 only.
L __________________
r= 3.0 V.
All other signals measured at 1.5 V.
lIC·631
8-79
Am8228 • Am8238
TEST CIRCUITS
/j1.0kH
+12V
±10%
AM8228
AM8238
INTA
I
23
lIC·633
lIC·632
Note 1. For 00-07: R1 = 4.0kn, R2 = oon, CL = 25pF.
For all other outputs: .r;'!1 = 500n, R2 = 1.0kn, CL
INTA (for RST 7)
= 100pF.
II\S1
OUTPUT
PIN
UNDER TEST
00-----41-----\
I
25pf
lIC·634
tRE
Enable 8080 bus, HIGH-Z to logic "0"
Enable 8080 bus, HIGH-Z to logic "1"
Disable 8080 bus, logic "0" to HIGH-Z
Disable 8080 bus, 10gic"1 "to HIGH-Z
S2
le
S,
S2
Closed
Open
Closed
Open
Open
Closed
Open
Closed
Test Circuit for OBIN to 8080A BUS
The "read" control signals (MEM R, I/O Rand INTA) are
derived by combinational logic from Status Bit and the DBIN
input.
The "write" control signals (MEM W, I/O W) are similarly
derived from the Status Bits and the WA input.
FUNCTIONAL DESCRIPTION
Bi-Directional Bus Driver: An eight-bit, bi-directional bus
driver is provided to buffer the Am9080A/8080A data bus
from Memory and I/O devices, The Am9080A data bus has
an input requirem~nt of *3.0 volts (min) and can drive (sink)
a current of at least 3.2mA. The Am8228 • Am8238 data bus
driver matches these input requirements and provides enhanced
noise immunity. The output drive is set for 10mA typical for
Memory and I/O devices.
All Control Signals are ,iactive LOW" and directly interface
AAM, ROM and I/O components.
The INTA control signal is normally used to gate the "interrupt instruction port" onto the bus. It also provides a special
feature in the Am8228 • Am8238. If only one basic vector is
needed in the interrupt structure, the Am8228 • Am8238 can
automatically insert a AST 7 instruction onto the bus. To use
this option, connect the INT A output of the Am8228 •
Am8238 (pin 23) to the +12 volt supply through a series
resistor (1 k ohms). The voltage is sensed internally by the
Am8228 • Am8238 and logic is "set-up" so that when the
DBIN input is active, a AST 7 instruction is gated on to the
bus when an interrupt is acknowledged.
•
When using a multiple byte instruction as an Interrupt Instruction, the Am8228 • Am8238 will generate an INTA pulse ~or
each of the instruction bytes.
The Bi-Directional Bus Drive is controlled by signals from the
Gating Array for proper bus flow and the outputs can be
forced to high impedance state (three-state) for DMA activities.
Status Latch: The Am8228 • Am8238 stores the status information in the Status Latch when ·the STSTB input goes
"LOW". The output of the Status Latch is connected to the
Gating Array and is part of the Control Signal generation.
Gating Array: The Gating Array generates control signals
(MEM A, MEM W, I/O A,. I/O Wand INTA) by gating the
outputs of the Status Latch Am9080A signals; i.e., DBIN, WE,
and HLDA.
·The 8080A has an Input requirement of 3.3V and
mum current of .1.9mA.
~an
The BUSEN (Bus Enable) input of the Gating Array is an
asynchronous input that forces the data bus output buffers
and control signal buffers into their high-impedance state if
it is a "HIGH". If BUSEN is a "LOW", normal operation of
the data buffer and control signals take place. This facilitates
CPU independent bus operations such as direct memory access.
drive a maxi·
8-80
Am8228 • Am8238
LOADING RULES
DEFINITION OF FUNCTIONAL TERMS
Data bus to-from Am90S0A/SOSOA
Data bus to-from user system
Input/output read strobe output active LOW
Input/output write strobe output active LOW
Memory read strobe, output, active LOW
Memory write strobe, output, active LOW
Data bus input strobe, input active H IG H
Interrupt acknowledge strobe, input, active
LOW
Hold input from Am90S0A/SOSOA active
HIGH
Write input strobe, active HIGH
07- 0 0
OB7- 0B O
I/OR
I/OW
MEMR
MEMW
OBIN
INTA
HLDA
WR
BUSEN
Signal
STSTB
Metallization and Pad Layout
Input Load
Output
Sink
Output
Source
DO
15
250pA
2mA
-10pA
01
17
250pA
2mA
-10pA
02
12
750pA
2mA
-10pA
03
10
250pA
2mA
-10pA
04
6
250pA
2mA
-10pA
05
19
250pA
2mA
-10pA
Os
21
750pA
2mA
-10pA
8
250pA
2mA
-10pA
DBO
13
250pA
10mA
-lmA
DB1
16
250pA
10mA
-lmA
DB2
11
250pA
10mA
-lmA
DB3
9
250pA
10mA
-lmA
DB4
5
250pA
10mA
-lmA
DBs
18
250pA
10mA
-lmA
DBS
20
250pA
10mA
-lmA
DB7
7
250pA
10mA
-lmA
07
BUS ENABLE INPUT, input, 3-state output
control, active LOW for 3-state out
Status Strobe, input, strobes status on data
bus into status latch, active LOW
Pin No_
STSTB
1
500pA
DBIN
4
250pA
28
27
26
25
Vee
WR
3
250pA
iTOw
HLDA
2
250pA
MEMW
IIOR
MEM R
24
10mA
-lmA
24
MEMR
MEMW
26
10mA
-lmA
DBIN
23
INTA
IIOR
25
10mA
-lmA
DB4
22
21
BUS EN
D6
lOW
27
10mA
-lmA
10mA
-lmA
STSTB
HLDA
WR
D4
DB7
D7
DB3
9
20
DB6
BUSEN
22
19
D5
INTA
23
18
DB5
GND
14
Vee
28
D3
10
17
D1
DB2
11
16
DB1
D2
12
DBa
13
15
14
GND
250pA
DO
DIE SIZE 0.110" X 0.136"
STATUS WORD CHART
TYPE OF MACHINE CYCLE
Data Bus
Status
Instruction Memory Memory
Write
Read
Bit
Information
Fetch
Do
D1
D2
D3
D4
D5
D6
D7
INTA
WO
STACK
HLTA
OUT
M1
INP
MEM R
CD
®
®
0
1
0
0
0
1
0
1
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
Stack Stack
Read Write
Input Output
Interrupt
Write Acknowledge
Read
@) ® ®
0
1
1
0
0
0
0
1
0
0
1
0
0
0
0
0
0
1
0
0
0
0
1
0
Halt
Acknowledge
Interrupt
Acknowledge
While Halt
(j)
®
®
@
0
0
0
0
1
0
0
0
1
1
0
0
0
1
0
1
0
1
0
0
0
1
1
1
0
1
0
1
0
0
0
0
I
I
®
STATUS
WORD
~ INTA
(NONE)
I NTA
IIOW
I/O R
MEM W
MEM R
MEMW
MEM R
MEM R
S-81
CONTROL
SIGNALS
Application Notes
NUMERICAL INDEX
Page
Am9130/Am9140 ............................................................................ 9-1
First-In First-Out Memories ................................................................... 9-17
Am9511 .................................................................................... 9-26
Am9519 ........................................' ............................................ 9-49
Am9130/Am9140
DESIGNING WITH SELF-CLOCKING, ADAPTIVE 4K STATIC R/W RANDOM ACCESS MEMORIES
By Joseph H. Kroeger
TABLE OF CONTENTS
GENERAL CHARACTERISTICS
Introduction ........................................ 9-2
Design Philosophy .................................. 9-3
Interface Considerations ............................ 9-3
Power Supply ...................................... 9-3
INTERNAL CIRCUITRY
Address Register. . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Address Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Memory Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Bit and Data Lines ................................
Sense Amplifier .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Data I/O Stages ...................................
Memory Status Circuit .............................
INTERFACE SIGNALS ................................ 9-4
Signal Flow ........................................ 9-4
Chip Enable ....................................... 9-4
Address and Chip Select ............................ 9-5
Write Enable ....................................... 9-6
Data In and Data Out ............................... 9-6
Output Enable and Output Disable ................... 9-7
Memory Status ..................................... 9-7
9-7
9-8
9-8
9-8
9-9
9-10
9-10
SYSTEM DESIGNS
Interface Timing ................................... 9-11
Small Memory Arrays .............................. 9-12
Memory Status Timing ............................. 9-13
Memory Status Coordination ........................ 9-14
Handshaking Control .............................. 9-15
Interleaved Operation .............................. 9-15
9-1
Am91301 Am9140
parts available. As usual at AMD, all parts are 100% reliability
assurance tested to the requirements of MIL-STD-883.
GENERAL CHARACTERISTICS
Intraduction
Figure 2 shows the pin assignments for the two memories.
The package for both parts is a standard 22-pin dual in-line.
Both memory configurations are manufactured from the same
basic chip and use only specialized metal interconnect layers
to define the structural differences. This approach allows
several manufacturing efficiencies to be realized and permits
each part to benefit from the combined volume of both parts.
The Am9130 and Am9140 products from Advanced Micro
Devices are 4K-bit, static, self-clocking, adaptive, read/write
random access memories. Both types of devices use only a
single +5 volt power supply, yet offer high speed performance
and low power dissipations. Figure 1 lists the appropriate part
numbers for the combinations of variables available at press
time. As product enhancement proceeds, it is anticipated that
higher speed parts and wider ranges of low-power and military
temperature parts will be available. Plastic DIP packages will
also become an option. The latest factory data sheets show all
available variations of parts.
The Am9130 and Am9140 memories are implemented with
AMD's LlNOX N-channel silicon gate MOS technology. The
processing and design rules are exactly the same as those used
for some time to produce the popular Am9102 line of 1 K
static R/W memories. LlNOX features physically flat structures, triple ion-implantation, and low capacitance, high-speed
devices. The new 4K memories are very dense with more than
27,500 active transistors in an area of less than 37,800 mil 2 .
The chip measures 192 x 197 mils with 58% of the area
devoted to the 4096 storage cells.
The Am9130 is organized as 1024 words by 4 bits per word;
the Am9140 is organ ized as 4096 words by 1 b it per word.
Parts are available in both commercial and military temperature ranges. Although the standard power parts offer quite low
per-bit power dissipation, there is also a family of low-power
ORGANIZATION
AMBIENT
TEMPERATURE
O°C < TA <"70°.C
1024 x 4
-55°C < TA < 125°C
O°C < TA < 70°C
4096 x 1
-55°C < TA < +125°C
ACCESS TIME
POWER
300ns
400ns
500ns
200ns
AM9130ADC
AM9130BDC
AM9130CDC
AM91 L30ADC
AM91 L30BDC
AM91 L30CDC
STANDARD
AM9130ADM
AM9130BDM
AM9130CDM
LOW
AM91L30ADM
AM91L30BDM
STANDARD
LOW
AM9130EDC
AM9140ADC
AM9140BDC
AM9140CDC
LOW
AM91L40ADC
AM91L40BDC
AM91 L40CDC
STANDARD
AM9140ADM
AM9140BDM
AM9140CDM
AM91L40ADM
AM91L40BDM
STANDARD
LOW
AM9140EDC
Figure 1. Part Number Matrix.
ADDRESS 6
VCC (+5.oVI
ADDRESS6
vcc (+5.oVI
ADDRESS 7
ADDRESS 0
ADDRESS 7
ADDRESS 0
ADDRESS B
ADDRESS 1
ADDRESSB
ADDRESS 1
ADDRESS 9
ADDRESS 2
ADDRESS 9
ADDRESS 2
DATA liD 1
ADDRESS 3
ADDRESS 10
ADDRESS3
DI',TA 1/02
ADDRESS 4
ADDRESS 11
ADDRESS4
DATA I/O 3
ADDRESS 5
DATA IN
ADDRESS 5
DATA 1/04
WRITE ENABLE
DATA OUT
OUTPUT DISABLE
CHIP SELECT
OUTPUT DISABLE
Ci1iP"SEi:m
MEMORY STATUS
OUTPUT ENABLE
MEMORY STATUS
OUTPUT ENABLE
(GND) VSS
CHIP ENABLE
(GNDI VSS
1kx4
CHIP ENABLE
4kx1
MPR·402
Figure 2. Pin Assignments.
9-2
MPR·403
Am91301Am9140
Design Philosophy
All inputs include protection networks designed to prevent
damaging accumulations of static charge. During normal operation, the protection circuitry is inactive and may be modeled
as a simple series RC. See Figure 3. The first functionally
active connection for every input is the gate of an MOS
transistor. No active sources or drains are connected to the
inputs so that no transient or steady-state currents are impressed on the driving signals other than the simple charging
or discharging of the input capacitance, plus the accumulated
leakage associated with the protection network and the input
gate. Input capacitances are usually around 5pF and leakage
currents are usually less than 11lA.
Read/write random access memories are customarily divided
into two categories based on the storage mechanism used in
the memory cells. Dynamic memories use dynamic cells that
store information in the form of charge on small capacitors.
Static memories use static cells that store information in the
form of latched currents flowing through transistors. Dynamic
memories must be periodically refreshed in order to maintain
the stored information. Static memories maintain the stored
data without refreshing as long as power is applied. (Both
types are volatile - that is, stored information is lost when
power is removed.)
The basic storage mechanisms of the cells contribute significantly to the characteristics of the overall memory, but an
important contribution is also made by the access method
used with a particular cell. Dynamic storage has conventionally
been used with dynamic decoding and control circuitry. Similarly, static storage has traditionally used static support
circuitry. But those associations are not necessary. Other
combinations are possible and provide different overall specifications. One example is provided by Advanced Micro Devices'
4K dynamic memories, the Am9050 and Am9060. They use
static circuitry on some input signals in order to significantly
improve several timing characteristics. There also exist several
types of read-only memories that use dynamic decoding for
improved performance.
MPR·404
Figure 3. Equivalent Input Circuit.
The output buffers can source at least 200llA worst-case and
can sink at least 3.2mA worst-case, while still maintaining TTL
output logic levels. Thus, the memories can drive two standard
TTL loads or nine standard Low-Power Schottky TTL loads.
This unusually high output drive capability allows not only
improved fan-out, but also better capacitive drive and noise
immunity.
The Am9130 and Am9140 memories take advantage of a new
combination that provides static storage together with a novel
type of clocked access method. The storage cells use a conventional, fully static design. The decoding and sensing circuits
use a clocked static approach that has no dynamic nodes. The
clocked circuitry allows the addition of several new features,
increases speed and decreases power dissipation relative to
an analogous non-clocked design. At the same time, the usual
disadvantages of a clock have been either eliminated or minimized in these new memories.
Delays in the output circuits show little variation with changes
in the DC loads being driven. Changes with capacitive loading
are shown by the curve in Figure 4. Access times are specified
for a total load of one TTL gate plus 50pF of capacitance.
This philosophy, combined with Advanced N-channel MOS
technology, has produced these new combinations of features,
including:
60
•
•
•
•
•
•
•
•
•
o
•
•
•
•
Vc~
1
= 5 0V
TA = 25°C
Fully static storage
Fast access and cycle times
Low operating power dissipation
Self-clocking mode of operation
Single phase, low voltage, low capacitance clock
Static clock that may be stopped in either state
Address register on-chip
Output data register on-chip
Single +5 volt power supply requirement
Interface logic levels identical to TTL
High output drive capability
Nearly constant power drain; no large current surges
DC standby mode for reduced power consumption
Operation over full military temperature range
I
U
u
«
~
w
/
40
'"'"w
20
(!l
z
«
I
/
u
-20
o
V
V
100
V
/'
V
/
200
300
400
CAPACITIVE LOAD - pF
MPR·405
Figure 4. Access Change Versus Load.
Interface Considerations
Power Supply
In common with other AMD static R/W RAM's, all of the
input and output signals for the Am9130 and Am9140 memories are specified with logic levels identical to those of standard
TTL circuits. The worst-case input high and low levels are
2.0V and O.8V, respectively; the Worst-case output high and
low levels are 2.4V and O.4V, respectively. Thus, with TTL
interfacing, the normal worst-case noise immunity of at least
400mV is maintained.
The Am9140 and Am9130 memories require only a single
supply voltage. They perform their normal operations at a Vee
of +5·volts. The commercial temperature range parts have a
voltage tolerance of ±5%; the military temperature range
tolerance is ±10%. The worst-case current drains are specified
in the data sheets at the high side of the voltage tolerance and
the low end of the temperature range. In addition, the current
9-3
Am91301Am9140
specifications take into account the worst-case distribution of
processing parameters that may be encountered during the
manufacturing life of the product.
The row address signals (AO through A5) and their inversions
are distributed to the 64 row address decoders where one of
the rows is selected. The 64 cells on the selected row are then
connected to their respective bit line columns. Meanwhile,
the column address signals (A6 through A9) have been decoded
and used to select one of 16 columns for each of the four
sense amplifiers. The end result is that one cell is connected
to one sense amplifier.
The current drain for these parts is relatively quite constant
over their various operating cycles. Since the basic storage
mechanism involves latched currents in each cell, there is a
necessary cumulative current flowing at all times, even when
the memory is not being actively accessed. The average currents
specified are largely independent of the CE input state, or the
condition of any of the input signals. At the falling edge of the
CE clock, there is a brief current surge of an additional 4 to
8mA that occurs as the decoders are being preset.
During read operations, the sensed data is latched into the
output register and is available for the balance of the operating
cycle. During write operations, the write amplifier is turned
on and drives the input data onto the sense lines, up the
column bit lines and into the selected cells. Input and output
data signals share common interface pins.
Dynamic memories usually have quite different current characteristics. Their average power dissipation is proportional to
their operating frequency, so that average current drain
decreases significantly when they are cycling slowly or doing
refresh operations only. There are very large peak currents
associated with every cycle in a dynamic memory, no matter
how frequently or infrequently the cycles occur. Power
supplies and power distribution systems must be capable of
handling these peak demands.
The output buffers use a three-state design that simplifies
external interfacing. Unselected chips have the outputs turned
off so that several chips may be wire-ored together easily.
The Output Enable and Output Disable signals provide fully
asynchronous controls for turning off the output buffers
when desired.
Within the storage matrix, there is an extra row of simulated
cells. This reference row is selected on every operating cycle
in addition to the addressed row and provides internal timing
signals that help control the data flow through the part. The
Memory Status output signal is derived from the reference
row and uses the same designs for its sense and buffer circuits
as used by the data bits. Memory Status specifies when output
data is available and simplifies generation of Chip Enable.
Power vs. speed characteristics for the Am9130 and Am9140
4K statics are flat horizontal lines. See Figure 5. A representative 4K dynamic has a rising line as shown. The dynamic
dissipation becomes higher than the regular-power static
parts out near the high end of the speed range. The cross-over
occurs much earlier for the low-power statics.
The power-down mode is entered by simply bringing both CE
and OE low and then ramping Vee down as low as 1.5V.
Power dissipation will fall by more than 80%. Normal cycles
may resume when Vee has been returned to its operating
range. See specification sheets for further details.
Figure 7 is the block diagram for the Am9140 version. The
basic operation and signal flows are similar to the Am9130.
There are two additional address lines (A 10, All), allowing
selection of one of 4096 locations. Each location contains
one bit so only one set of data I/O circuits are needed. Input
and output data signals use separate interface pins.
Chip Enable
The Chip Enable input is a control clock that coordinates all
internal activities. All active memory functions are initiated
when CE goes high. At the completion of the active operation,
CE goes low to preset the memory for the next cycle. There
are no restrictions on the maximum times that CE may remain
in either state so the clock may be extended or stopped whenever convenient. After power-up and before beginning a valid
operation, the clock should be brought low to initially preset
the memory.
POWER
Figure 8 illustrates a basic operating cycle for either of the
memories. The rising edge of CE begins each cycle and strobes
the Address and Chip Select signals into the on-chip register.
Internal timing signals are derived from CE and from transitions of the address latches and the reference cells. Various
control functions are activated by these timing signals as the
addresses arid data flow through the memory.
SPEED-
MPR-406
Figure 5. Power Versus Speed Comparisons.
When the actual access time of the part has been reached (or
a write operation is complete), CE may be switched low if
desired. The worst-case time as specified in the data sheet may
be used to determine the access. Alternatively, the access, or
write complete time indicated by the rising edge of the
Memory Status output signal may be used. (See the Memory
Status section of this Note.) It is perfectly acceptable to leave
the CE clock high following the access time; some system
operating modes will find it convenient to do so. A Read/
Modify/Write cycle, for example, will keep CE high after the
access until the modify and write portions of the cycle are
finished.
INTERFACE SIGNALS
Signal Flow
Figure 6 is the block diagram for the Am9130 version and
shows the interface connections along with the general signal
flow. There are ten address lines (AO through A9) that are
used to specify one· of 1024 locations, with each location
containing four bits. The Chip Select signal acts as a high order
address for multiple chip memory configurations. The Chip
Enable clock latches the addresses into the address registers
and controls the sequences of internal activities.
9-4
Am91301Am9140
AO
Al
A2
A3
64
ROW
'ADDRESS
DECODERS
STORAGE CELL MATRIX
A4
64x16
A5
64x16
64x16
64x16
CE
REF, ROW
r--------,
~_r~--~~--r_~_,~
A6
A7
AS
A9
SA
OB
VCCO--GNDO---
1/01
1/02
1/03
1/04
MS
MPR-407
Figure 6. Am9130 Block Diagram.
AO
Al
ROW
ADDRESS
DECODER
A2
A3
64
A4
STORAGE CELL MATRIX
A5
64 x 64
CE
A6 n -__~--------~
A7
COLUMN
ADDRESS
DECODER
AS
A9
Ala
All
1/0
CONTROL
LOGIC
VCC
GNO
0--0--DATA
OUT
DATA
IN
MS
MPR-408
Figure 7. Am9140 Block Diagram.
When CE does go low, the internal preset operation begins.
The memory is ready for a new cycle only after the preset is
complete. The worst-case CE low time specified in the data
sheet may be used to determine the preset interval. Alternatively, the actual preset time is indicated as complete as soon
as Memory Status goes low. CE may remain low as long as
desired.
Address and Chip ~elect
The Address inputs are binary coded lines that specify the
word location to be accessed within the memory. The Am9130
has 1024 word locations, anyone of which may be selected
by a ten-bit binary address (2 10 = 1024). The Am9140 has
4096 locations and so uses a 12·bit address (2 12 = 4096).
9·5
Am9130/ Am9140
CE~
I
ADA/CS
200<
\
/
XXXXXXXXXXXXXXXX"---___
I
'-
/
MS
\
MPR·409
Figure 8. Basic Operating Cycle.
To execute a read cycle, WE is held high while CE is high. To
perform a write operation, the WE line is switched low during
the cycle. The data sheet for the memories shows the mini·
mum write pulse width required to successfully complete the
writing of information into a cell. In many cases, however, it
will be convenient to leave the WE line low during the whole
cycle so that no intra·cycle timing is necessary for a write
operation. The memories are designed so that WE may remain
low continuously as long as successive write cycles are being
executed.
The Address input signals are latched into an on·chip address
register by the rising edge of CEo They are allowed to become
stable at the same time that the clock goes high: The address
set·up time is zero. They must be held stable for the specified
minimum time following the CE rising edge in order to be
properly loaded into the register. Once the address hold time
has been observed, the address inputs are ignored by the
memory until the next cycle is initiated.
The Chip Select input acts as a high order address for use when
the memory system word capacity is larger than the word
capacity of an individual chip. When multiple chips are stacked
up, the Address lines may be wired in parallel to all chips and
the CS lines used to individually select one active chip, or
row of chips, at a time. Chip Select controls the operation of
both the output buffers and the write amplifiers. Unselected
chips have their output buffers off so that selected chips wired
to the same data lines can dominate the output bus. Only
selected chips can perform write operations so the Write
Enable control signal and the input data lines may be wired
in parallel to several chips.
A write cycle can take place only when three conditions are
met: The chip is selected, CE is high, and WE is low. This
means that if either CE goes low or WE goes high, the writing
is terminated. Thus, the full minimum write pulse width must
appear within the CE high time to perform a successful write.
If WE is low when CE goes high to initiate a new cycle, the
write amplifier is enabled and the write data propagates onto
the data lines internally. However, no columns or rows are
selected unti I after the address for the new cycle is decoded,
so actual writing into the cell is delayed by the decoding
time following CEo This delay means that the minimum write
pulse width cannot apply when WE goes low very early in
the cycle.
CS is latched into the on·chip register in the same way that
Addresses are. This means that once a memory is selected or
deselected, it will remain that way until a new cycle with new
select information begins. The OE. and aD lines provide
asynchronous control over the output buffer when that
function is necessary on a selected chip.
Data In and Data Out
Write Enable
The specification sheet requirements for incoming data during
a write operation show a minimum set·up time with respect to
the termination of the write. Termination occurs when either
WE goes high or CE goes low. Input data may arrive earlier
than the set·up time, where convenient. If incoming data
changes during a write operation, the information finally
written in the cell will be that stable data preceeding the termi·
nation by the set·up time. The data input hold time with
respect to the termination of write is zero. If the Am9140
is used with the Data In and Data Out lines remaining separate,
the input data may occupy the bus at all times, if desired. The
valid written data is then determined by the timing of WE.
The Write Enable line controls the read or write status of the
devices. When the CE clock is low, the WE signal may be any
value without affecting the memory. This allows the line to be
indeterminant while the using system is deciding what tJ"Je next
cycle will be. WE does not affect the status of the output
buffer.
If the Am9140 is used with the Data In and Data Out tied
together, or if the Am9130 is used, care should be taken to
avoid conflict between incoming and outgoing data on the
shared lines. It is important to note that when WE is low, it
does not turn off the output buffers; the potential conflict
must be resolved in other ways. One convenient method is
Chip Select is an active low function - that is, the input signal
must be low at the rising edge of CE in order to select the
chip. Most CS signals are derived from high order addresses.
In small systems, a simple NAND gate can provide the neces·
sary logic. In larger systems, a binary decoder (such as the
Am25LS138) works well. In either case, the outputs are active
low and thus directly match the input polarity of the Chip
Select.
9-6
Am9130/ Am9140
to tie the Output Enable line to the WE line. Then, whenever
WE goes low to write, it also turns off the output buffer. After
a delay long enough for the output to reach its high impedance
state, the input data can be introduced without conflict. The
time that WE is low should be long enough to cover the output
turn·off delay as well as the input data set·up time.
mance. Thus, the access time indicated by Memory Status will
always be better than the worst-case specification as long as
the conditions and assumptions on which the worst-case
numbers are predicated are better. Further, real operating
results change with changing conditions and Memory Status
follows those changes. Thus, for example, as temperature
decreases, access time also decreases and MS tracks the change
in access exactly.
Since the data being written during a write cycle is impressed
on the sense amplifier inputs, the output data will be the same
as the input once the write is established. The conflicts occur
with old output data that remains from a previous cycle or
with new data that may be accessed before the write is established. If the write (and the associated input data) can be
initiated while the output buffers are turned off, the conflict
is eliminated; even if the outputs turn on, the output data will
match the input data.
There are many different ways to use the Memory Status
signal and several are illustrated in this Note. Basically it offers
improved performance and self-timed operation, along with
other related implications.
During a read cycle, once all of the addressing is complete and
the cell information has propagated through the sense amplifier, it enters an output data register. The read information can
also flow through to the output if the buffer is enabled. As
long as CE is high, the addressing remains valid and the output
data will be stable. When CE goes low to begin the internal
preset operation, the output information is latched into the
data register. It will remain latched and stable as long as CE
is low.
The circuitry for the address register is shown in Figure 9.
Inverters K and L isolate the register from the input pin and
convert the TTL input levels to the wider logic swings used
internally. M inverts the address so that both A and A propagate to the inputs of the register.
INTERNAL CIRCUITRY
Address Register
Transistors 1, 3 5, and 7 are depletion devices. Transistor pairs
1, 2 and 3, 4 form two inverters that are cross-coupled to
provide the basic latch. Transistor pairs 5, 6 and 7, 8 are used
to enter information into the latch. If point A goes high, then
5 and 6 turn on and 7 and 8 turn off, forcing the latch to one
polarity. Notice that the circuit would work without transistors
5 or 7. They are added to minimize the propagation delay
through the register.
At the start of every cycle when CE goes high, the output
data latch is cleared in preparation for new information to
come from the sense amplifier, and the output buffer is turned
off. This is done so that in mUltiple chip systems with the
outputs bussed together, old data from one chip will not
interfere with new data being accessed on another.
When transistors 9 and 10 are turned on, 5, 6, 7 and 8 are
turned off and the latch is isolated from the input signal.
When transistors 11 and 12 are turned on, the outputs from
the register are held low and the following address decoders
are in their preset state.
Output Enable and Output Disable
The OE and 00 control lines perform the same internal function except that one is inverted from the other. If either OE is
low or 00 is high, the output buffer will turn off. If the CS
input is latched low and OE is high and 00 is low, then the
output buffer can turn on when data' is available.
The timing for the address register operation is shown in
Figure 10. ----__,
cr - - - - - + - - - - - ,
SElRE~~
------+----.-----f---
Bll DETAil
SElRE~~
------+----.-----f---
cr ------+---....,
¢DEe
vee
T
----f
>--____'--
¢l
OUTPUT
e~~~~-----+----....,
INPUT
DATA
LINES
MPR·414
Figure 13. Bit and Data Line Organization.
Data I/O Stages
Memory Status Circuit
The output stage shown in Figure 15 includes the output data
register plus the output control logic plus the output buffer.
Information from the sense amplifier can flow into and
through the register and on to the output pin at the access
time. As long as the CE clock is high, the cell addressing will
be valid and the sense amplifier and output can remain stable.
When CE goes low, the register inputs are isolated from the
sensed data and the output can stay valid until CE next
goes high.
The Memory Status output is derived from the internal ¢L
timing signal that is in turn derived from the true perfor·
mance of the reference row. MS uses the same output buffer,
control logic, register and sense amplifier circuitry as used in
the data path. Even where a control gating function is absent,
the circuitry is included but disabled. At the input to the MS
sense circuit, a pseudo data line pair is created that is directly
analogous to the storage cell data lines, including the EQ and
column select devices. The result is that Memory Status
tracks the output data very closely under all operating conditions.
There are several signals that can turn off the output buffer.
Only when they are all simultaneously in the necessary state
will the output turn on. When CE goes high, the output will
turn off until the access time arrives as indicated by ¢L When
CS is latched high, the output will be off. When OE is low the
outputs will be off. When 00 is high the outputs will be off.
Since the final output circuits are the same for both MS and
Data, they respond identically to variations in loading. If the
data output is heavily loaded, then similar equivalent loading
should be used on the Memory Status output in order to
maintain their responses relative to each other.
The write amplifier control logic only allows a write to take
place on a selected chip with the CE high and the Write Enable
low. Note that the WE line does not affect the output buffer.
On the Am9130, the data input and output signals are tied
together and share common interface pins.
The MS output is always enabled and never enters a threestate off mode. Even on an unselected chip, the MS signal
continues to reflect the status of the memory.
9-10
Am9130/ Am9140
TO OUTPUT BUFFER
FROM
Am90aOA
FROM
Ama22a
{AO~A9
A10
DBO-DB3
DB4-DB7
MPR-417
Figure 16. 1 k x 8 R/W Memory for Am9080A.
SYSTEM DESIGNS
Interface Timing
The specification sheets for the Am9130 and Am9140 show
the various input requirements and output responses for the
memories. In each case, the parameters shown are worst-case
in order to fully describe the operational limits of the parts.
But many system situations allow the timings to be greatly
simplified. For example, in small memories that are only one
chip deep, the Chip Select signal may not be required and CS
may be tied low. Similarly, in many instances 00 may be
tied low or OE may be tied high or both.
In some circumstances, it may be quite convenient to leave
the addresses stable longer than the parts require. The falling
edge of CE might be used by the associated system to initiate
the derivation of a new address and the decision about reading
or writing the next cycle. Those signals can then stay stable
until the following decision time.
DATA LINE INPUT
It will quite often be easy to leave the Write Enable line low
during all of the CE high time of a write cycle. This eliminates
some intra-cycle timing of the write pulse_ The WE line may
be any value as long as CE is low. Similarly, it will also be easy
to have the Data In information available during the time
that WE is low - indeed, WE will often be useful as the
control line for gating the incoming data on and off_
MPR-415
Figure 14. Sense Amplifier Circuit.
Many times CE can be easily and directly derived from other
signals in the using system. Figure 16 shows an example of a
small memory for a microprocessor. Two Am9130 parts form
a 1 K x 8 memory for an Am9080A. The processor supplies the
Addresses and the chip select signals_ The Am8228 System
Controller associated with the processor supplies the M EM R
and M EMW control lines as well as a buffered data bus. A 10
is inverted and used for the Chip Select signal, placing the
addressing range in the second 1 K of system memory. For
larger systems or different configurations, other select logip
may be required.
WE
TO
DATA
IN
WRITE
AMPLIFIER
DATA
LINES
I
es
FROM
SENSE
AMPLIFIER
Vee
I
I
I
CDATA
~LJOUT
¢L
DE
The Controller can request a Memory Read or a Memory Write
operation. The NAND gate shown generates a CE when either
request is made. When MEMR is high, the output buffers are
turned off via theOD control. When MEMR is truethe memory
output will be connected to the data bus_ When MEMW is low,
a write operation is performed at the specified address. There
is always sufficient time between operation requests for the
memory to be fully preset..
OD
MPR-416
Figure 15. Data 1/0 Stages.
9-11
Am91301 Am9140
CYCLE REQUEST·
ADDRESSES 0-9
10/
/
CE
CE
A·
A
ADDRESS 10
CS
READ/WRITE
WE
L
-r
CS
Am9130
lk X4
L
DE
00
WE
I
~7
'----
L
-r
CE
A
A
CS Am9130
WE 1 k X 4
CS
L
DE
WE
DE
rOO
110
110
4V
/
I
CE
A
CS
Am9130
lk X 4
L
-r
DE
rOO
110
~
L
Am9130
lk X 4
WE
I
CE
00
A
CS
Am9130
lk X 4
DE
rOO
110
CE
110
~
Am9130
lk X 4
WE
DE
00
110
t
4V
/
4V
/
t- . -t
DATA 110
MPR-418
Figure 17. 2k x 12 Memory System.
Small Memory Arrays
Added buffering will usually only be necessary when the
transition times begin to cause the overall system delays to
be excessive.
As an illustration of a conventional approach for operating
multiple chips, Figure 17 shows a convenient way to connect
six Am9130 chips to make a 2K. x 12 memory. The Chip
Enable clock is wired in parallel to all six chips, as are the ten
Address lines and the R/W control line. Output Disable is tied
to ground, allowing Output Enable to provide asynchronous
external control of the output buffer status. OE is tied to
Write Enable so that the R/W line turns off the output buffers
when it goes low during a write cycle.
As the capacity of systems like the one in Figure 17 grows,
decoding of the Chip Select information gradually involves
a little more logic. If the memory was 3K x 12, for example,
it might be implemented with three rows of Am9130 chips.
Select information is then needed to assure that only one of
the rows at most is active at a time. A one-of-three decoder
is easy to implement from two address lines with simple gates
as shown in Figure 18. As the number of rows to be selected
grows, however, both the wiring and the gate count tend to
get much more complex.
Address 10 and its inversion are used to select one of the two
rows of chips for each operating cycle. As long as A lOis low,
the upper row will respond to the clock and will communicate
on the data bus while the lower row is deselected and can
neither read nor write. When A lOis high the row roles are
reversed.
~ I~~:::::::
The Data I/O lines have corresponding bits tied together in
vertical columns. The control logic is arranged so that only
one of the output buffers at a time will drive an I/O line,
and only one chip at a time will write from an I/O line.
:::-----+---11
The type of memory illustrated is easily expanded to many
different .oapacities. An 8K x 16, for example, could be implemented 'with 32 Am9140 chips (16 in each row), using the
same control line configuration, plus two more address lines.
_
Driving and buffering limitations for both the inputs and
the outputs will be dictated by a} accumulated leakage currents
and b} accumulated capacitance. On an address line, for
example, many chips may be driven in parallel from a standard
TTL output. As the number of chips goes up, the leakage
currents in the MOS memory gradually become a significant
load for the TTL output especially in the high logic level state.
Similarly, many parallel inputs will present a capacitive load
that will degrade the rise and fall characteristics of the signal.
~"'"ow"
CS(ROW 11
Al0
Am25LS138
OR
Am25LS139
CS(ROW 21
CS(ROW 31
All
MPR-419
Figure 18. Chip Select Decoding.
9-12
Am9130/ Am9140
Another approach (also shown in the Figure 18) takes advantage of MSI binary decoders like the Am25LS138 or
Am25LS139. Both offer package count advantages, especially
as the system gets bigger, and control logic is included that
permits deselection of all rows. This can be handy for powerdown situations and some other circumstances. Notice that
the output polarity is such that the decoders interface directly
with the memory chips.
I
\
CHIP~
ENABLE
~
~
MEMORY
STATUS
DATA
OUT
(a)
The Am9140 can be converted to a common I/O instead of a
separate I/O device simply by wiring together the Data In and
the Data Out lines. When that is done, the same precautions
suggested for the Am9130 concerning bus contention should
be observed. Conversion of the Am9130 from common to
separate I/O is only slightly more complex. The Am2915
(or Am2905) is a quad three-state bus transceiver. When
connected as illustrated in Figure 19, it serves to create the
bus needed by the Am9130 from separate input and output
data. It even includes convenient registers on both sides. For
a circuit without the registers and other control features of
the Am2915, try the Am8T26. Both are four bits wide and
so match up nicely with a column of Am9130 chips operating
in parallel.
CHIP~
ENABLE
MEMORY
STATUS
¢
""'\
!J
\
l
\
(b)
'\--\
CHIP~
ENABLE
MEMORY
STATUS
/
~'
~~LJ,
(c)
MPR·421
Figure 20. Memory Status Information.
Am9130
Am9130
I
Am291-S-
The front edge of MS also specifies the end of the time that
CE must be held high for that operation. See Figure 20b.
Though CE may be high as long as desired, it may safely go
low any time after MS goes high. MS will stay high until the
internal preset operation is complete. Thus, it will not go low
until some time after CE goes low and the total time that
MS is high depends not only on the actual operating conditions
of the memory, but also the delay from MS high to CE low.
DATA 1/0
The falling edge of MS specifies that the memory is ready
for a new operation to be initiated. See Figure 20c. When
several chips are operated in parallel, the latest falling edge will
indicate the earliest time that their CE should go high. The
chip with the longest access time will also be the chip with the
longest preset time. The picture in Figure 21 shows an MS
waveform during a simple read cycle.
- -r-~---~"""----'
I
DATA
IN
DATA
OUT
EN
MPR·420
Figure 19.
Memory Status Timing
Figure 20 shows the timing information conveyed by the MS
output. The rising edge indicates that output data is valid and
makes a convenient strobe for output to the rest of the system.
See Figure 20a. When several chips are being used in parallel,
the Memory Status signal from the slowest chip should be the
strobe in order to assure that all the data bits are available and
valid. There is a brief nominal delay from the worst-case output data to the rising edge of MS. That time is always greater
then zero under similar loading conditions for the two signals.
Figure 21. Read Cycle Waveforms.
9-13
Am9130/Am9140
Memory Status is derived from the selection of the row of
reference cells and the reference row is always doing a read
operation. Thus, the MS output will appear in every operating
cycle, whether a read or a write is being performed. If the
Write Enable line is low at the start of the cycle, and if the
input data are present at the same time, MS may be considered
a valid indication that the write is complete and CE may be
switched low. However, if WE is not low or input data are not
present until sometime later in the cycle, then the worst·case
write timing requirements as shown in the specification sheet
must be observed, independent of indications from the rising
edge of MS. The falling edge of MS will be fully valid in any
type of cycle.
dotted line. The timing for this arrangement is shown in
Figure 25. The memory will free·run. at its best speed and
the System Status will provide a synchronizing signal for use
by the rest of the system.
~------------~~------------------ CLOCK
Since the requirements for the two transitions of the Chip
Enable clock can be fully specified by the transitions of the
Memory Status output, these memories can be effectively selfclocking. The MS output may be inverted and then used as the
CE input as shown in Figure 22. Not only will the memory run
properly, but it will run at its best frequency for any given set
of operating conditions and it will change that frequency as
the conditions change. There are many potential capabilities
implied by the Memory Status concept, including: adaptive
self-timed memories, true asynchronous operations, elimination of support circuit skews, temperature compensation, new
memory architectures, improved speed/power ratio, etc.
CE
CE
Am9130/
Am9140
Am9130/
Am9140
MS 1
MS2
~-------------+---..
~
A
~
o-v-----v
........
STATUS
HIGH
__________________ or;'\~ STATUS
LOW
~~~-
MPR·423
Figure 23. Status Coordination Logic.
!
CE
CE
Am9130/
Am9140
f
MS
I
CE~
\
/
MS\
CE
~
Am9130/
Am9140
Am9130/
Am9140
MSl
MS2
CLOCK
/
L
MS
MPR·422
MPR·424
Figure 22. The Self-Clocking Memory.
Figure 24. Clock Generation Logic.
Memory Status Coordination
Figure 23 shows logic for combining mUltiple Memory Status
signals. Gate A is used to detect when both MS outPl)ts are
high indicating that output data is available. Similarly, gate B
detects that both MS outputs are low, indicating that the
preset period is complete for both chips. The system associated
with the memory can use this information to coordinate the
flow and the generation ofthe CE clock. Essentially, this logic
allows the slowest chip to govern the overall memory speed.
The inputs to the coordinating logic can of course be expanded
to handle as many chips as desired.
MSl
MS2
To combine these two pieces of status information, a simple
cross-coupled latch can be added as shown in Figure 24. Since
there are times when neither condition is true, the latch
serves to maintain the previous status indication until a new
state is valid. The result is a System Status signal that specifies
for the system the same information that each MS signal
specifies for an individual chip.
SYSTEM
STATUS
CHIP
ENABLE
The clock may be derived independently for synchronization
with the using system. Alternatively, the System Status signal
may be inverted and used for the CE clock as indicated by the
\
/
/
/
L
L
\
I
MPR·425
Figure 25. Status Timing.
9-14
Am91301Am9140
Handshaking Control
a memory system. An example configuration is shown in
Figure 27, with each support logic block being similar to the
circuitry previously discussed. Each row is clocked only when
it is addressed by the Chip Select signal (AD or AD). Unselected
rows wait in their preset state until they are selected and
clocked. The Cycle Request input is steered to the selected
row by added logic. The Status Acknowledge outputs are
three-state and only the SA for the selected row is turned on.
The selected row will proceed when its preset is complete.
When the data from the requested operation is available,
the Status Acknowledge output goes high. The using system
can then request another operation immediately once a new
address is ready.
For systems that cannot be memory-driven, some means of
controlling the clocking is needed. To permit the memory
to single-step, a gate can be inserted in the dotted line of
Figure 24 with a control line to turn the clock on or off. A
more versatile and more asynchronous approach is illustrated
in Figure 26. An additional latch is added to generate the
clock so that the status information is derived independent of
the clock control.
When the Cycle Request input is low, the memory will preset
and prepare for an active cycle. When all is ready, Status
Acknowledge will go low. When CR goes high, the memory
will execute a cycle and will acknowledge conditions of access
by bringing SA high. CR and SA then form a simple asynchronous handshaking pair for memory control. Notice that CR
may go high at any time to start a cycle. If the chips are ready
(SA low), the clock will proceed, but if preset is not complete
(SA high) the memory will wait before initiating the requested
cycle.
Independent clocking of each row adds little support circuit
complexity while providing increased overall performance
in two ways. First, the speed of each access is limited only
by the slowest device in the selected row rather than the
slowest device in the whole array. Secondly, successive operations in different rows will be faster because the wait for preset
is eliminated; one row will preset while another is being
accessed. Notice that the low order bit is used as the Chip
Select address. In many systems, this will improve the distribution of alternate accesses for sequential information by
mapping even addresses in one row and odd addresses in the
other.
The timing for CR is quite simple. It should be held high until
SA goes low. If SA is already low, a narrow CR pulse will
suffice. Thus, a brief Cycle Request will cause the memory
to execute one complete cycle and stop. If CR is held high, the
memory will access (SA goes high) and then will leave the
clock high until CR goes low. This allows Read/Modify!Write
operations to be performed quite easily.
In any event, no matter where the operation is addressed or
when it is requested, the memory will respond in the best
possible time. The Cycle Request and Status Acknowledge
signals form a true asynchronous handshaking pair. All of the
variations in performance caused by the timing of the request,
the row addressing patterns, the speeds of the individual chips
and the memory operating conditions are automatically
reflected in the response of the Acknowledge signal. An
interesting challenge will be to design using systems that can
take advantage of this unusual capability.
Interleaved Operation
With the clock derived locally within the memory from the
MS signals, and with the clocking logic integrated on a single
chip, it becomes convenient to individually clock each row of
CE
CE
Am9130/
Am9140
Am9130/
Am9140
MSl
MS2
STATUS
ACKNOWLEDGE
CYCLE
REQUEST
D
MPA-426
Figure 26. Handshaking Control.
9-15
Am91301Am9140
CE
10/
Al-A10
R/W
CE
A
/
J
1
CE
CE
WE
L:.
DE
~
cs
00
AO
MS
liD
t--
liD
MS
I--
liD
MS
t--
MS
liD
t--
l
I
CLOCK
LOGIC
.,
CYCLE
~ REQUEST
STATUS
ACKNOWLEDGE
CLOCK
LOGIC
~
cs
MS
MS
I
I
MS
MS
00
r
DE
WE
~A
liD f - -
liD f - -
CE
liD
CE
r--
1/01--
CE
CE
1
/
4
/
4
~
1
,
/
4
/
4
DATA liD 116 BITS)
MPR-427
Figure 27. 2k x 16 Interleaved Memory System.
9-16
APPLICATION OF
FIRST-IN FIRST-OUT MEMORIES
By John Springer, Digital Applications
The Am3341 /2841, Am2812 and Am2813 are asynchronous
first-in first-out memories using P-channel silicon gate MOS
technology. All use the same fundamental storage mechanism,
but are organized differently. The Am3341/2841 contains up
to 64 four-bit words; the Am2812 holds up to 32 eight-bit
words; the Am2813 holds up to 32 nine-bit words. All devices
can easily be expanded to hold either more words or wider
words. The Am2841 is functionally identical to the Am3341,
but is faster. The logic symbols for these devices are shown
in Figure 1.
DO
01
D2
03
two pieces of digital equipment operating at different speeds.
Such an application is illustrated in Fi.gure 2, where machine
1 might be a relatively slow electromechanical input device
and machine 2 might be a digital computer (or vice-versa).
Data is frequently handled in a configuration like this by
having machine 1 generate an interrupt requesting service from
machine 2 every time a data word is available. If machine 1
transmits only a single word infrequently then the interruptoriented approach is reasonable, but if machine 1 is going to
transmit 20 or 30 words, then the interrupt approach is
inefficient. As each of the words becomes available, an interrupt must be generated, machine 2 must react, cleaning up
its active processing, locate the interrupt, store the new data
word, and return to its active processing only to receive
another interrupt milliseconds later.
Qo
Q1
Am3341 / Am2841
4X64FIFO
Q2
Q3
51
OR
IR MR
SO
OE
MACHINE 1
(SLOW)
FIFO
BUFFER
MACHINE 2
(FAST)
READ
' - - - - - - - - ' CLOCK
MOS-478
OE
DO
01
D2
D3
D4
D5
D6
D7
D8
PL
IR
QO
Q1
Figure 2. Asynchronous Interface between
Two Digital Machines
Q2
Q3
Am2813
9X32FIFO
Q4
QS
Q6
Q7
Q8
OR
PD
An alternative processing method is cycle stealing on a direct
memory access (DMA) channel. In this configuration the
system is designed so that machine 1 has direct access to the
memory of machine 2. As data becomes available from
machine 1, it is inserted into machine two's memory during
time periods when machine 2 is not using the memory. This
method is fairly efficient, especially for transfer of large blocks
of data from a disc or tape, but it also can result in interference with the active processing of machine 2 due to contention
for the memory channel.
MOS-477
Figure 1. Logic Symbols
THE FUNCTION OF A
FIRST-IN FIRST-OUT MEMORY
The most efficient way to handle the interface between these
two machines is by using a special memory between the
machines to temporarily store the data from machine 1 until
machine 2 is ready to accept it. The memory must be large
enough to store all the data that machine 1 might generate
in-between services by machine 2, and should be able to
write the data at the speed of, and under control of, machine 1,
A first-in first-out memory (FI FO) is a read/write data storage
unit that automatically keeps track of the order in which data
was entered into the memory, and reads the data out in the
same order. It behaves like a shift register whose length is
always exactly equal to the number of words stored. The most
common application of a FIFO is as a buffer memory between
9-17
FIFO Memories
while reading the data at the speed of machine 2. An extremely
useful feature in such a memory is the ability to perform
read and write operations at the two different rates simultaneously and completely independently. This allows machine
1 to write new data into the memory at the same time that
machine 2 is re~ding data from the memory without requiring
any kind of synchronization between the two.
necessary so that the buffer can perform alternate read and
write operations at the maximum speed of both machines.
The control logic to do this is fairly complex and requires an
independent clock running at more than twice the frequency
of machine 1 or 2.
The problem of handling read and write operations simultaneously is alleviated if a 2-port RAM is used. Such a device
(e.g., the Am9338) has two independent sets of address inputs,
one for reading and one for writing, so no synchronizing of
read and write requests need occur. Unfortunately, two port
RAMs are limited to small numbers of bits, and, therefore,
are fairly expensive to use in a FI FO of reasonable size.
METHODS OF CONSTRUCTING FI FO BUFFERS
There are a number of ways in which FI FO memories can be
built. The design becomes trivial if there is no requirement for
independent reading and writing. The data can be written into
a shift register, for example, which is clocked by machine 1.
When a block of data has been written, the register can be
shifted until the first data word is available at the output, and
then shift control can be handed to machine 2, which shifts
the data out as required. This method requires that data
transfer occur in blocks only, since once the data has been
shifted to the output, a new word cannot be written until
the last block has been completely read.
The Am3341/2841, Am2812 and Am2813 are totally integrated solutions to the problem of asynchronous F I FOs. A
special unique control system is integrated into the device to
make possible completely independent reading and writing.
Because the control and data storage are intimately mixed on
one LSI chip, a very efficient, cost-effective FI FO can be constructed. The three devices, all of which use the same basic
control scheme, are organized into three different configurations to provide optimum flexibility for all applications.
A somewhat more flexible FIFO can be built using a random
access memory with counters used to generate the read and
write addresses. A multiplexer is used to select the appropriate
address counter for a read or write, and the counter is incremented at the end of the cycle, so that the next read or write
will occur at the next counter address. Since the location of
the next read and write are held in independent counters,
reading and writing can be randomly intermixed. However,
using an ordinary RAM, only one operation can be performed
during a given cycle, since only one address can be selected
at a time.
STORAGE AND CONTROL IN THE
Am3341/2841, Am2812 AND Am2813
The Am3341/2841, 64 x 4 FIFO will be used to explain the
storage technique. A similar scheme is used in the Am2812
32 x 8 FIFO and Am2813 32 x 9 FIFO. A logic block diagram
of the Am3341 is shown in Figure 3. Data words are stored in
64 four-bit registers, connected so the output of one feeds the
input of the next. Note that if all 64 registers were clocked
together, the device would look like a quad 64-bit shift
register. FIFO operation is performed by clocking each register
independently so that data can be selectively shifted through
the registers. To shift or not to shift: that is the decision which
must be made independently by each of the 64 registers. The
decision is made by examining a control flip-flop associated
with each register to determine if that register contains valid
data or not.
If the RAM is very fast relative to the machines using it, then
the control logic can be designed to receive read and write
requests independently and to execute them so quickly that
the FI FO buffers appear to operate completely asynchronously.
In the general case, this means the RAM cycle time must be
less than half the cycle time of machines 1 or 2. This is
--- ----- ---
00
4·BIT
REGISTER
4BIT
REGISTER
0
,
STROBE
STROBE
~cl
r--PL
OR 51
IR
>---c
t-
Co
I-
MR
[R
'---
Of-t-
'-- S
CONTROL
LOGIC
--- ----- ---
4BIT
REGISTER
62
4·BIT
REGISTER
63
STROBE
STROBE MR
L
a-
~s
t---
C,
op
MR
Or-r-
5
C62
00-
[R
---
MOS 479
Figure 3
9-18
i
R
MR
op-
..... , - S
*-
Or-r-
C63
'- R
MR
Lr---
rL-:
CONTROL
LOGIC
010'---
50
f-
OR PD
I---
OR
FIFO Memories
InitiallY, the FIFO is reset and there is no data anywhere in it.
The control flip-flops are all reset to "0." A write command
causes a 4-bit data word to be entered into the first register
and sets the control flip-flop for that register, indicating valid
data is present. The control flip-flop for the second register is
a "0" and this causes it to continually examine the control
flip-flop for the first register, looking for a "1." When the data
is written into the fi rst register, the second register sees the" 1 ,"
and a clock is generated to it, copying the data from the first
register into the second, setting the control flip-flop for the
second register, and clearing the control flip-flop for the first
register. In exactly the same fashion, the third register copies
the data from the second, and the fourth from the third until
finally the data ends up in the last location. At this point all
64 registers contain the same data, but only the last control
flip-flop contains a "1," the others all having been reset as the
data was copied into the next register.
As soon as the data moves from the first register to the second,
the control flip-flop for the first register is cleared. A new data
word can then be written into the first register. The first
control bit is brought out as "input ready" (I R), and data can
be entered anytime it is HIGH. When the data has been accepted, I R goes LOW (a "1" in the control bit) and when the data
moves to the second register, I R goes HIGH again. The new
data falls through the registers as long as there are "Os" in the
corresponding control flip-flops. Eventually it reaches the
register immediately behind a register already containing data.
Since the control bit for that register is already a "1," the
data is not moved any further and remains stacked up behind
the existing data. A read command on the output causes the
last control flip-flop to be cleared, creating a new empty
location. The next to the last word is copied into the last
word and the hole in the control register moves back toward
the input as the data words move down one place. This
process can continue until all data has been shifted out of the
memory. When the last word has been read the external signal
.output ready (OR) remains LOW, indicating no more data is
available.
may not be entered until this data has moved to the second
register, indicated by IR going HIGH. The OR signal goes
HIGH whenever valid data is present on the FIFO output.
Whenever a shift-out command is received, OR goes LOW
while the data is being changed_ If there is no more data, OR
stays LOW, indicating the memory is empty. Otherwise OR
returns HIGH as soon as the new data is on the outputs. Data
is entered into the FIFO by a LOW-to-HIGH transition on
_shift-in (PL), whilll I~ is HIGH. The fact that both these signals.
. are HIGH causes il- strobe to the first data register to be generated, loading the data on the data inputs into register and
setting the first control flip-flop. When the control flip-flop is
set, I R goes LOW, indicating the data has been accepted. The
input data can be changed after I R has gone LOW. When 51 is
then brought LOW, the data is transferred to the next register
(unless there is already data there) and IR goes back HIGH,
indicating that the input is ready to receive more data. If the
memory is full, then the data in the first register will not move
to the second, and I R will stay LOW. Once data moves into the
second register, it falls spontaneously through the FIFO until
it stacks up behind data already present.
Data in the last FIFO location is presented on the data outputs.
While data is there, OR is HIGH. The next data word is obtained by applying a LOW-to-HIGH transition on shift-out
(SO). This results in OR going LOW. The data does not
actually change until SO is brought LOW again. The new data,
if any, will be brought to the output and, after the data is
stable, OR will go HIGH again. If the memory is empty, OR
will remain LOW until a new word falls through from the
input. Note that anytime OR is HIGH, there is good, stable
data on the outputs.
MASTER-RESET
The master reset pin (M R) is used to clear all data from the
FI FO. When it goes LOW; all the control flip-flops are cleared
and the output buffer is cleared. IR will be forced HIGH during
this. time. When the M R signal is removed the FI FO is ready
to accept new data. Note that if 81 is held HIGH as the master
reset ends, then both SI and I R will be HIGH, resulting in
immediate entry of the data on the data inputs into the FI FO.
If this is not desired, then 81 should be held LOW during the
master reset and until new data is ready to be entered.
This scheme allows the reading and writing of data to occur
completely independently and even simultaneously. Data can be
written into the device as rapidly as the device is capable of
moving it away from the first register; it can be read at the
same rate. The only constraint imposed by this scheme is that
a certain amount of time is required for the first data word
to propagate to the end of the register. This time is referred
to as the "ripple -through" time and is the internal shift
time multiplied by the number of bits from input to output.
EXPANSION METHODS USING
THE Am3341/2841
The four control signals on the Am3341 have been designed
so that devices can be directly connected end-to-end, as in
Fig. 6, and can thereby control each other. When data appears
at the output of the first device OR goes HIGH. This causes an
SI command to the second device which in turn causes I R to
go LOW. Since I R is connected to SO, this causes a shift-out
at the first device, driving OR LOW until new data is available,
and the process repeats. Lengthening of the FIFO stack requires only this simple interconnection.
CONTROL SIGNALS TO THE Am3341/2841 AND Am2813
There are four signals used with the Am3341 /2841 and Am2813
to control the reading and writing of data. These are parallel
load (PL, or 51 on 3341), input ready (IR), parallel dump
(PD or 50 on 3341) and output ready (OR).
To make a wider FI FO devices are simply operated in parallel.
Since each device is autonomous there need be no interconnection between paralleled devices, except that all the shift-ins
at the front are connected together and all the shift outs at
the end are connected together. Data then ripples independently through each row of FI FOs.
The two outputs, I R and OR, are derived from the state of
the first and last control flip-flops, respectively, and are used
to indicate the presence or absence of data at the input and
output of the FIFO. When I R is LOW (that is, input not ready)
then there is data residing in the first data register. New data
9-19
FIFO Memories
1
g
\~~~ I I I II I I
A2
AJ
so
S,
L--
H
~I
I
I
I
I
·7
Co
Co Co Co
C,
C,
C,
C,
C,
B,
A,_
C2
C2
C2
C2
C2
B2
A2
CJ
CJ
CJ
CJ
CJ
BJ
AJ
C J _ CJ
Bo
Ao
S,
so
_-L
I~
I
,.
OR
.. L
INITIAL CONDITION
FIFO empty, SI LOW IR HIGH, word "A" on inputs.
2
Co
C , _ C,
L-H-L--
--L
--
C o _ Co
C 2 _ C2
~~~;I I 1.1 I II g
L_H _
S, _
_
Word "C" written in same manner, and so on. When buffer is full,
all control bits are 1's and IR stays LOW.
---
8
-
HO
Go
FO
EO
00
Co
BO
H,
G,
F,
E,
0,
C,
B,
A'r--
H2
G2
F2
E2
02
C2
B2
A2 r - - -
HJ
GJ
FJ
EJ
OJ
CJ
BJ
AJr--
AO r - - -
S_'_
L_
SO_L
~~t~I_'~I_'_I~'~I_'~I_'~I~'~I,-~~ol
L~
3.
B O _ AO
AO
B , _ A,
A,
B 2 _ A2
A2
B J _ AJ
AJ
---
9
r-r-I-r---
so
S_'_
H_L_
L _s,_
--L
L2I'l o lololololU
~l--H~
~L
L
B O _ AO
AO
B,~
AO
AO
A,
A,
A,
A,
A,
A,
A,
A'r---
B 2 _ A2
A2
AO
A2
A2
AO
A2
A2
A2
AO
A2r--
B J _ AJ
AJ
AJ
AJ
AJ
AJ
AJ
AJI--
S,
L--
H
10
A0r--
_SO_L
~I~~
IR
OR
~(64B'T51---l
B O _ BO
AO
AO
AO
AO
Ao
AO
Aol--
B , _ B,
A,
A,
A,
A,
A,
A,
A, I - -
B 2 _ B2
A2
A2
A2
A2
A2
A2
A21--
B J _ BJ
AJ
AJ
AJ
AJ
AJ
AJ
AJI--
0,
C,
B,_
02
02
C2
B2_
HJ
GJ
FJ
EJ
OJ
OJ
CJ
BJ_
\ ..... _" .... __ A .... .."A_ .... ~~
_S_O_
H_L
~I'I'I'IG\55~
IR
t... . . -' . . . . /(_A_.......
OR
l- H
---
HO
HO
HO
Go
FO
EO
DO
Cor--
H,
H,
H,
G,
F,
E,
0,
C'r--
H2
H2
H2
G2
F2
E2
02
C2 r - - -
HJ
HJ
HJ
GJ
FJ
EJ
OJ
CJr-_50
_ L--H-L
11
---
_s,_
HO
HO
HO
HO
HO
H,
H,
H,
H,
H,
H,
H,
H'r--
H2
H2
H2
H2
H2
H2
H2
H2r--
HJ
HJ
HJ
HJ
HJ
HJ
HJ
HJr--
HO
HO
HOr--
_S_O_
L-H-L
Read word "H". OR stays LOW because FIFO is empty. Word
"H" remains in output until new word falls through.
Ao_
BO
BO
BO
BO
BO
BO
B , _ B,
B,
B,
B,
B,
B,
B,
A, ; - - - - -
B 2 _ B2
B2
B2
B2
B2
B2
B2
A21--
B J _ BJ
BJ
BJ
BJ
BJ
BJ
BJ
AJ
S,
BO_
0,
E2
FO
--L
B O _ Bo
~--L-_
Co
E,
F2
Go
Read word "8" out, word "C" moves to output, and so on.
Word "8" written into FIFO
6
00
F,
G2
L-H
so
S_'_
L_H_
DO
G,
H2
L _5_'_
Data spontaneously ripple through registers to end of FIFO, causing
OR to go HIGH. The time required for data to fall completely
through the FI FO is the "Ripple-through Time".
5
EO
H,
HO
When SO goes LOW, the "0" in the last control bit bubbles toward
the memory input. OR goes HIGH as the new word arrives at the
output. IR goes HIGH when "0" reaches input.
Release data into FIFO by lowering SI. After delay, data moves to
second location, and IR goes HIGH indicating input available for
new data word.
4
~t:..H--L
FIRST READ OPERATION
50 goes HIGH, indicating "Ready to Read". OR then goes LOW
indicating "Data Read".
Write input into first stage by raising SI. (ll = delay) IR goes LOW
indicating data has been entered.
r--_SO_L
SI goes LOW allowing word "8" to fall through.
Figure 4
9-20
1.405-480
FIFO Memories
IR
PL OR SI
INTERNAL
STROBE
INPUT
DATA
MOS·481
INPUT TIMING SEQUENCE, Am3341/2841 AND Am2813
51 is brought HIGH (1) causing internal strobe (2) which loads data. When data has been loaded, IR
goes LOW (3) indicating data can be changed (4). SI may then be brought LOW (5) causing I R to return
HIGH (6).
PO OR SO
OR
'----+-------;----'--- -
(LOW IF
DEVICE
EMPTY)
DATA
OUT
MOS·482
OUTPUT TIMING SEQUENCE, Am3341/2841 AND Am2813
Data out changes (1); then OR goes HIGH (2). When SO goes HIGH (3), OR goes LOW (4) indicating
data is about to change. After SO goes LOW (5) the data actually changes (6) and after it is stable, 0 R
goes HIGH again (7).
Figure 5
DO
01
02
03
SHIFT
IN
07
°1
Am3341! Am2841
4 X 64 FIFO
°2
03
OR
SO
SI
Am3341!Am2841
4X64FIFO
SI
°1
°2
03
DO
01
02
03
OR
SO
SI
IR
00
°1
°2
03
DO
01
02
03
OR
SO
SI
IR
Am3341!Am2841
4X64FIFO
00
00
°1
°2
03
°2
03
OR
SO
°1
SHIFT
OUT
I
00
DO
01
02
03
00
DO
01
02
03
I
J'L
04
05
06
00
DO
01
02
03
Am3341!Am2841
4X64FIFO
SI
IR
°1
°2
03
DO
01
02
03
OR
SO
SI
IR
Am3341! Am2841
4 X 64 FIFO
00
Am3341!Am2841
4X64FIFO
°1
°2
03
°4
°5
06
°7
OR
SO
I
The composite input ready indicates both devices are ready to receive data. The shift in pulse must be
wide enough for all devices to load data under worst case conditions.
MOS.483
Figure 6. 8 x 192 FIFO Buffer Using Am3341/2841
CONTROL SIGNALS ON THE Am2812
Internally operation is like the Am3341/2841. The control
signa Is are slightly different, however, and there are some ad·
ditional features. There is a parallel load (PL) input, used to
The Am2812 is controlled exactly like the Am3341 and
Am2813, except that the input ready signal is inverted.
9·21
FIFO Memories
load an 8-bit word onto the first stage of the FIFO, and an input ready output (iR) which indicates that the FIFO is ready
to receive a new data word. At the output, there is a dump
command (PO), used to bring the next data word to the outputs, and an output ready signal (OR) which indicates that
good data is available on the data outputs.
The next data word is shifted onto the outputs by a pulse on
parallel dump (PO). When PO goes HIGH, the OR signal goes
LOW, indicating that output data is about to be changed. When
PO then goes LOW, the output data changes with the word behind the outputs moving onto the outputs. When the new output data has stabilized, OR will go HIGH indicating that good
data is once again available on the FIFO outputs. If the PO
pulse emptied the FI FO, then the OR signal will remain
LOW and the last word read will remain on the outputs until a
new data word falls through from the front of the FIFO.
Oata is loaded into the first FIFO location by a LOW-to-HIGH
word is present at the output, OR (output ready) will be HIGH.
PL OR SL
INTERNAL
STROBE
DATA
IN
MOS-484
Am2812 INPUT TIMING
When data is steady, PL or SL is brought HIGH (1) causing internal data strobe to be generated (2). When
data has been loaded, iR goes HIGH (3) and data may be changed (4). fA remains HIGH until PL is brought
LOW (5); then iR goes LOW (6) indicating new data may be entered.
OR
PO OR SD
DATA
OUT
MOS-485
Am2812 OUTPUT TIMING
When data out is steady (1), OR goes HIGH (2). When PO or SO goes HIGH (3)' OR goes LOW (4). When
PO or SO goes LOW again (5), the output data changes (6) and OR returns HIGH (7).
Figure 7.
transition on PL when iR is LOW. (It is the coincidence of PL
HIGH and IR LOW which results in the internal load strobe.)
When the data has been entered the first control flip-flop sets,
causing TR to go HIGH. When PL goes LOW again, the data in
the front of the FIFO begins falling through the stack toward
the output, and fA goes LOW as soon as it has moved to the
second register. If the FI FO was filled to capacity when the
data was loaded, then fA will stay HIGH; new data cannot be
entered, and any additional shift in command will be ignored
until fA goes LOW after some data has been removed from
the FIFO.
Oata entered into the FIFO falls through the registers until it
reaches either the output or another data word. When a data
MASTER RESET
A direct clear signal can be applied to the FIFO by a LOW logic
level on the M R input. This will clear all the internal control
register bits and will clear the data from the outputs. fA will
go LOW indicating the FIFO is ready to receive new data. If
the PL input is held HIGH when the MR returns to a HIGH
state, then an internal input strobe will be generated, and
whatever data is on the inputs will be loaded into the FI FO.
If this is not desired then PL should be held LOW at the end of
the master reset. The master reset will cause OR to go LOW
and remain LOW until new data falls through from the input.
9-22
FIFO Memories
FLAG
SYSTEM INTERFACING
A flag output is available on the Am2812 and Am2813 to indicate whether the FI Fa is more or less than half full. The flag
signal is generated by summing the "ls" in the control flipflops, and therefore is not affected by the movement of data
through the register_ The flag signal goes HIGH when the 15th
±1 (Le_, the 14th, 15th, or 16th) word is loaded into the FIFO_
It will remain HIGH until there are less than 15 ±1 words in
the memory. It is always HIGH if there are more than 16 words
in the FIFO.
Normally the input and output of a stack of FI FOs are interfaced with TTL logic. A special interface circuit is used
internally on the inputs of the AMO family of FI FOs to
provide complete electrical compatibility with TTL outputs;
no external components need be used. The circuit works by
using an MaS transistor inside the chip as a pull-Up resistor
in the HIGH state. When the voltage applied to the input is
LOW, the internal resistor is disabled and presents no loading
to the TTL output. TH E V -I characteristic of the input is
shown in Figure 8.
OUTPUT ENABLE
The Am2812 and Am2813 data outputs are 3-state signals.
When OE is HIGH, they will be in either a HIGH or LOW
state; if OE is LOW, they will go to a high-impedance OFF
state. Outputs of several F I Fa buffers can then be tied together onto a bus, and one of the buffers can be selected to
drive the bus. When OE is LOW, the dump function (both SO
and PO) is disabled.
Pull-Up Characteristic Input
Current Versus Input Voltage
1
VDDD
cf>2
vccD
vssD
DBO
DBl
DB2
DB3
DB4
DBS
C
"
,.~
:II
o
Cl
:II
:g
J>
I:
~:II
o
o
CONTROL ROM
704 X 16
~
DBS
:II
DB7
MOS-002
Figure 2. Arithmetic Processing Unit Block Diagram.
9-28
Am9511 Application Note
eration accesses the status register and a write operation enters a command. When C/O is low (Data Port), a read operation accesses data from the top of the data stack and a write
operation enters data into the top of the data stack.
Data Stack
Figure 5 shows the two logical organizations of the internal
data stack. It operates as a true push-down stack or FILO
stack. That is, the data first written in will be the data last read
out. Within each stack entry, the least significant byte is entered first and retrieved last.
Data Formats
The APU executes both 16- and 32-bit fixed-point operations.
All fixed-point operands and results are represented as birlary
two's complement integer values. The 16-bit format can express numbers with a range of -32,768 to +32,767. The
32-bit format can express numbers with a range of
-2,147,483,648 to +2,147,483,647.
Figure 6 shows a typical sequence for 32 bit operations. 6a
represents the stack prior to entry of data. 6b shows the stack
following entry of the LS Byte of operand C. 6c illustrates the
stack contents following the entry of four bytes of operand C.
When operands C, B and A are all fully entered the stack appears as in 6e. If a command is then issued, to add B to A for
example, the stack contents look like 6f where R is the result
of B + A. When the first (MSB) byte of R is removed the
stack appears as in 6g. 6h shows the stack following the
complete retrieval or R. An even number of bytes should always be transferred for any data operation.
The floating-point format uses a 32-bit word with fields as
shown in Figure 3. The most significant bit (bit 31) indicates
the sign of the mantissa. The next seven bits form the exponent and the remaining 24 bits form the mantissa value.
The exponent of the base 2 is an unbiased two's complement
number with a range of -64 to +63. The mantissa is a
sign-magnitude number with an assumed binary point just to
the left of the most significant mantissa bit (bit 23). All
floating-point values must be normalized, which makes bit 23
always equal to 1 except when representing a value of zero.
The number Zero is represented with binary zeros in all 32 bit
positions.
r-==
I ------IF
I -
MANTISSA SIGN
~ _,EXPONENT SIGN
I.stiLi
·-rI------
Mfe-EXPONENT ..
I I I I . I I
3130
TOP OF STACK (TOS)
NEXT ON STACK (NOS)
MANTISSA
1-1
.
I I I I I
_
-
-
I
32 - - - - - - , .
32 BIT OPERANDS
2423
MOS-003
Figure 3. Floating Point Format.
Status Register
The Am9511 Status register format is shown in Figure 4.
When the Busy bit (bit 7) is high, the APU is processing a
previously entered command and the balance of the Status
register should not be considered valid. When the Busy bit is
low, the operation is complete and the other status bits are
valid.
7
6
5
4
3. 2
- - - - TOP OF STACK (TOS)
I--------t
. - - - - NEXT ON STACK (NOS)
I--------t
0
1
1--16-1
= Carry or Borrow
16 BIT OPERANDS
1
= Overflow
1
= Underflow
MOS·OOS
Error
Field
01 = Negative Argument
Figure 5. Stack Configurations.
10 = Zero Divisor
11 = Argument too Large
1
= Top of Stack is Zero
1
= Top of Stack is
Command Format
Each command executed by the APU is specified by a single
byte with the format shown in Figure 7. Bits 0 through 4 indicate the operation to be performed. Bits 5 and 6 specify the
data format. Bit 7 is used to control the Service Request interface line. When bit 7 is a one, the SVREQ output will go true
when the execution of the command is complete.
Negative
1 = Busy
MOS-004
Figure 4. Status Register.
9-29
Am9511 Application Note
TOS
A4
(e)
C4
B4
I
I
I
A3
I
B3
I
C3
I
R4
C4
(f)
C4
TOS
C3
I
I
(c)
TOS
C2
I
I
I
I
I
I
I
I
B1
I
C1
I
I
I
I
I
I
I
I
I
(d)
C3
I
I
I
(g)
R3
I
C3
I
I
I
I
R2
C2
I
I
I
I
I
I
I
R2
R1
I
C2
A1
B1
C1
J
I
R3 I
C3 I
TOS
I
I
C4
C1
I
B2
C2
1
I
TOS
A2
C1
I
I
R1
C1
C4
I
I
I
I
I
I
I
C2
MOS-OOS
Figure 6. Stack Data Sequence Example.
SVREQ
I
.
(sr)
7
SINGLE
I
6
I
FIXED
5
1·-·I-------oP~~'6T~ON-----t·-1
.
.
4
3
2
o
MOS-007
Figure 7. Command Format.
9-30
Am9S11 Application Note
Summary
Description
Hex Code
(sr = 1)
Hex Code
(sr = 0)
SADD
EC
6C
16-18
Add TOS to NOS. Result to NOS. Pop Stack.
SSU8
ED
6D
30-32
Subtract TOS from NOS. Result to NOS. Pop Stack.
SMUL
EE
6E
84-94
Multiply NOS by TOS. Lower result to NOS. Pop Stack.
SMUU
F6
76
80-98
Multiply NOS by TOS. Upper result to NOS. Pop Stack.
SDIV
EF
6F
84-94
Divide NOS by TOS. Result to NOS. Pop Stack.
Command
Mnemonic
Execution
Cycles
16·BIT FIXED· POINT OPERATIONS
32·BIT FIXED·POINT OPERATIONS
DADD
AC
2C
20-22
Add TOS to NOS. Result to NOS. Pop Stack.
DSU8
AD
2D
38-40
Subtract TOS from NOS. Result to NOS. Pop Stack.
DMUL
AE
2E
. 194-210
Multiply NOS by TOS. Lower result to NOS. Pop Stack.
DMUU
86
36
182-218
Multiply NOS by TOS. Upper result to NOS. Pop Stack.
DDIV
AF
2F
196-210
Divide NOS by TOS. Result to NOS. Pop Stack.
32·BIT FLOATING· POINT PRIMARY OPERATIONS
FADD
90
10
54-368
FSU8
91
11
70-370
Add TOS to NOS. Result to NOS. Pop Stack.
Subtract TOS from NOS. Result to NOS. Pop Stack.
FMUL
92
12
146-168
Multiply NOS by TOS. Result to NOS. Pop Stack.
FDIV
93
13
154-184
Divide NOS by TOS. Result to NOS. Pop Stack.
SORT
81
01
782-870
SIN
82
02
3796-4808
32·BIT FLOATING·POINT DERIVED OPERATIONS
Square Root of TOS. Result to TOS.
Sine of TOS. Result to TOS.
COS
83
03
3840-4878
Cosine of TOS. Result to TOS.
TAN
84
04
4894-5886
Tangent of TOS. Result to TOS.
ASIN
85
05
6230-7938
Inverse Sine of TOS. Result to TOS.
ACOS
86
06
6304-8284
Inverse Cosine of TOS. Result to TOS.
ATAN
87
07
4992-6536
Inverse Tangent of TOS. Result to TOS.
LOG
88
08
4474-7132
Common Logarithm of TOS. Result to lOS.
LN
89
09
4298-6956
Natural Logarithm of TOS. Result to TOS.
EXP
8A
OA
3794-4878
e raised to power in TOS. Result to TOS.
PWR
88
08
8290-12032
NOS raised to power in TOS. Result to NOS. Pop Stack.
DATA AND STACK MANIPULATION OPERATIONS
Nap
80
00
FIXS
9F
1F
FIXD
9E
1E
FLTS
9D
10
FLTD
9C
1C
4
No Operation. Clear or set SVREO.
90-214 }
90-336
Convert TOS from floating point format to fixed point format.
62-156 }
56-342
Convert TOS from fixed pOint format to floating point format.
CHSS
F4
74
CHSD
84
34
22-24 }
26-28
Change sign of fixed point operand on TOS.
16-20
Change sign of floating point operand on TOS.
CHSF
95
15
PTOS
F7
77
PTOD
87
37
16 }
20
PTOF
97
17
20
POPS
F8
78
POPD
88
38
10 }
12
POPF
98
18
12
,. }
XCHS
F9
79
XCHD
89
39
26
XCHF
99
19
26
PUPI
9A
1A
16
Push stack. Duplicate NOS in TOS.
Pop stack. Old NOS becomes new TOS. Old TOS rotates to bottom.
Exchange TOS and NOS.
Push floating point constant
Figure 8.
9-31
7T
onto TOS. Previous TOS becomes NOS.
Am9511 Application Note
ALGORITHM DISCUSSION
DERIVED FUNCTION ERROR PERFORMANCE
Computer approximations of transcendental functions are
often based on some form of polynomial equation, such as:
Since each of the derived functions is an approximation of the
true function, results computed by the Am9511 are not always
exact. In order to more comprehensively quantify the error
performance of the component, the following graphs have
been prepared. Each function has been executed with a
statistically significant number of diverse data values, spanning the allowable input data range, and resulting errors have
been tabulated. Absolute errors (that is, the number of bits in
error) have been converted to relative errors according to the
following equation:
F(X) = Ao
+ A1X + A2X2 + A3X3 + A4X4 . . . .
(1-1)
The primary shortcoming of an approximation in this form is
that it typically exhibits very large errors when the magnitude
of I X I is large, although the errors are small when I X I is
small. With polynomials in this form, the error distribution is
markedly uneven over any arbitrary interval.
Fortunately, a set of approximating functions exists that not
only minimizes the maximum error but also provides an even
distribution of errors within the selected data representation interval. These are known as Chebyshev Polynomials and are
based upon cosine functions. 1 ,2 These functions are defined
as follows:
T n(X) = Cos nO; where n = 0,1,2 ...
0= Cos- 1X
Absolute Error
Relative Error = - - - - True Result
This conversion permits the error to be viewed with respect to
the magnitude of the true result. This provides a more objective measurement of error performance since it directly translates to a measure of significant digits 9f algorithm accuracy.
(1-2)
For example, if a given absolute error is 0.001 and the true
result is also 0.001, it is clear that the relative error is equal to
1.0 (which implies that even the first significant digit of the result is wrong). However, if the same absolute error is computed for a true result of 10000.0, then the first six significant
digits of the result are correct (0.001/10000 = 0.0000001).
The various terms of the Chebyshev series can be computed
as shown below:
To(X) = Cos (0·0) = Cos (0) = 1
(1-4)
T 1 (X) = Cos (Cos- 1 X) = X
(1-5)
T 2(X) = Cos 20 = 2Cos 2 0 - 1 = 2Cos 2 (Cos- 1 X) - 1 (1-6)
= 2X2 - 1
Each of the following graphs was prepared to illustrate relative
algorithm error as a function of input data range. Natural
Logarithm is the only exception; since logarithms are typically
additive, absolute error is plotted for this function.
In general, the next te'rm in the Chebyshev series can be recursively derived from the previous term as follows:
Tn(X) = 2X [Tn -1(X)] - Tn-2 (X); n~ 2
(1-7)
The terms T 3, T4, T sand T s are given below for reference:
T3 = 4X 3 - 3X
(1-8)
T4= 8X4 - 8X2 + 1
(1-9)
3
s
Ts = 16X - 20X + 5X
(1-10)
4
2
Ts = 32Xs - 48X + 18X - 1
(1-11)
Two graphs have not been included in the following figures:
common logarithms and the power function (X Y). Common
logarithms are computed by multiplication of the natural
logarithm by the conversion factor 0.43429448 and the error
function is therefore the same as that for natural logarithm.
The power function is realized by combination of natural log
and exponential functions according to the equation:
Chebyshev polynomials can be directly substituted for corresponding terms of a power series expansion by simple algebraic manipulation:
1 = To
X = T1
X2 = 1/2 (To + T 2)
X 3 = 1/4 (3T1 + T 3 )
X4 = 1/8 (3To + 4T2 + T 4)
XS = 1/16 (10T1 + 5T3 + Ts)
XS = 1/32 (10To + 15T2 + 6T4
+ Ts)
XY
=
e yLnx
The error for the power function is a combination of that for
the logarithm and exponential functions. Specifically, the relative error for PWR is expressed as follows:
(1-12)
(1-13)
(1-14)
(1-15)
(1-16)
(1-17)
(1-18)
IREpWR I,
=
I RE Exp I + IX (AE LN ) I
where:
REpWR
RE EXP
AELN
X
Each of the derived functions except square root implemented
in the Am9511 APU has been reduced to Chebyshev polynomial form. A sufficient number of terms has been used to
provide a mean relative error of about one part in 107 •
Each of the functions is implemented as a three-step process.
The first step involves range reduction. That is, the input argument to the function is transformed to fall within a range of
values for which the function' can compute a valid result. For
example, since functions like sine and cosine are periodic for
multiples of 7T/2 radians, input arguments for these func;tions
are converted to lie within the range of -7T/2 to +7T/'d.. Processing of the range-reduced input argument according to the
appropriate Chebyshev expansion is done in the second step.
The third step includes any necessary post processing of the
result, such as sign correction in sine or cosine for a particular
quadrant. Range reduction and post processing are unique to
each of the functions, while processing the Chebyshev expansion is performed by an algorithm that is common to all
functions.
=
=
=
=
relative error for power function
relative error for exponential function
absolute error for natural logarithm
value of independent variable in X Y
Notes:
1. Properties of Chebyshev polynomials taken from: Applied Numerical Methods; Carnahan, Luther, Wikes; John Wiley & Sons, Inc.;
1969.
2. Derived function algorithms adapted from: Algorithms for Special
Functions (I and II); NLlmerische Mathematic (1963); Clenshaw,
Miller, Woodger.
9-32
Am9S11 Application Note
10- 8 '--_ _---'----"L.----"_ _ __
_ lola
_100
_10- 10
10- 8 l -_ _--L._..J.._...._ _
10- 20
10- 10
_10 10
_100
DATA VALUES (RADIANS)
_10- 10
10- 20
10- 10
DATA VALUES (RADIANS)
MOS-008
MOS-009
COSINE
SINE
10-8 '--_ _...J....---l....._
_ lola
_100
...._ _
_10- 10
10- 20
10- 10
DATA VALUES (RADIANS)
MOS-Ol0
TANGENT
10- 8 I..-_ _....L..._---I
_10 0
_10- 10
10- 8
10- 20
1..------'---
_10 10
10- 10
DATA VALUES
_10 0
10- 20
10- 10
10 0
DATA VALUES
MOS-012
MOS-Oll
INVERSE COSINE
INVERSE SINE
9-33
Am9511 Application Note
10-8 '--_ _-'---''--''--'''--_..L-..LL_ _
_ 10 20
_10 10
_10 0
_10- 10
10- 20
10- 10
DATA VALUES
MOS-OI3
INVERSE TANGENT
10- 10
100
10 10
10- 10
DATA VALUES
10 0
10 10
DATA VALUES
MOS-OI4
MOS-OIS
NATURAL LOG
SQUARE ROOT
10- 8 ' - - - - - ' - - _......." - - - _10 10
DATA VALUES
MOS-OIS
9-34
Am9511 Application Note
cles when running at a 3MHz rate translates to 14 microseconds (44 x 32f.Ls = 14f.Ls). Variations in execution cycles
reflect the data dependency of the algorithms.
COMMAND DESCRIPTIONS
This section contains detailed descriptions of the APU commands. They are arranged in alphabetical order by command
mnemonic. In the descriptions, TOS means Top Of Stack and
NOS means Next On Stack.
In some operations exponent overflow or underflow may be
possible. When this occurs, the exponent returned in the result will be 128 greater or smaller than its true value.
All derived functions except Square Root use Chebyshev
polynomial approximating algorithms. This approach is used
to help minimize the internal microprogram, to minimize the
maximum error values and to provide a relatively even distribution of errors over the data range. The basic arithmetic
operations are used by the derived functions to compute the
various Chebyshev terms. The basic operations may produce
error codes in the status register as a result.
Many of the functions use portions of the data stack as
scratch storage during development of the results. Thus previous values in those stack locations will be lost. Scratch locations destroyed are listed in the command descriptions and
shown with the crossed-out locations In the Stack Contents
After diagram.
Figure 8 is a summary of all the Am9511 commands. It shows
the hex codes for each command, the mnemonic abbreviation, a brief description and the execution time in clock cycles. The commands are grouped by functional classes.
Execution times are listed in terms of clock cycles and may
be converted into time values by multiplying by the clock
period used. For example, an execution time of 44 clock cy-
ACOS
ASIN
ATAN
CHSD
CHSF
CHSS
COS
DADO
DDIV
DMUL
DMUU
DSUB
EXP
FADD
FDIV
FIXD
FIXS
FLTD
FLTS
FMUL
FSUB
Figure 9 lists the command mnemonics in alphabetical order.
LOG
LN
NOP
POPD
POPF
POPS
PTOD
PTOF
PTOS
PUPI
PWR
SADD
SDIV
SIN
SMUL
SMUU
SQRT
SSUB
TAN
XCHD
XCHF
XCHS
ARCCOSINE
ARCSINE
ARCTANGENT
CHANGE SIGN DOUBLE
CHANGE SIGN FLOATING
CHANGE SIGN SINGLE
COSINE
DOUBLE ADD
DOUBLE DIVIDE
DOUBLE MULTIPLY LOWER
DOUBLE MULTIPLY UPPER
DOUBLE SUBTRACT
EXPONENTIATION (eX)
FLOATING ADD
FLOATING DIVIDE
FIX DOUBLE
FIX SINGLE
FLOAT DOUBLE
FLOAT SINGLE
FLOATING MULTIPLY
FLOATING SUBTRACT
COMMON LOGARITHM
NATURAL LOGARITHM
NO OPERATION
POP STACK DOUBLE
POP STACK FLOATING
POP STACK SINGLE
PUSH STACK DOUBLE
PUSH STACK FLOATING
PUSH STACK SINGLE
PUSH 7T
POWER (X Y)
SINGLE ADD
SINGLE DIVIDE
SINE
SINGLE MULTIPLY LOWER
SINGLE MULTIPLY UPPER
SQUARE ROOT
SINGLE SUBTRACT
TANGENT
EXCHANGE OPERANDS DOUBLE
EXCHANGE OPERANDS FLOATING
EXCHANGE OPERANDS SINGLE
Figure 9. Command Mnemonics in Alphabetical Order.
9-35
Am9S11 Application Note
ACOS
ATAN
32-BIT FLOATING-POINT INVERSE COSINE
32-BIT FLOATING-POINT
INVERSE TANGENT
7
6
5
4
3
Binary Coding: I sr
0
0
0
0
2
°
7
0
86 with sr = 1
06 with sr =
Execution Time: 6304 to 8284 clock cycles
Description:
The 32-bit floating-point operand A at the TOS is replaced by the
32-bit floating-point inverse cosine of A. The result R is a value in
radians between and 1T. Initial operands A, B, C and D are lost.
ACOS will accept all input data values within the range of -1.0 to
+ 1.0. Values outside this range will return an error code of 1100
in the status register.
Accuracy: ACOS exhibits a maximum relative error of 2.0 x
10- 7 over the valid input data range.
Status Affected: Sign, Zero, Error Field
Hex Coding:
°
Hex Coding:
STACK CONTENTS
A
543
o
2
87 with sr = 1
07 with sr =
Execution Time: 4992 to 6536 clock cycles
Description:
Tt':d 32-bit floating-point operand A at the TOS is replaced by the
32-bit floating-point inverse tangent of A. The result R is a value in
radians between '-1T/2 and +1T/2. Initial operands A, C and Dare
lost. Ope'rand B is unchanged.
AT AN will accept all input data values that can be represented in
the floating point format.
Accuracy: AT AN exhibits a maximum relative error of 3.0 x
10- 7 over the input data range.
Status Affected: Sign, Zero
°
BEFORE
6
Binary Coding: LI_s_r-L-_0-L_0-L_0_l....-0_L-__L-----L_--l
°
STACK CONTENTS
AFTER
BEFORE
R
A
-TOS-
AFTER
~-------~
B
B
C
C
-TOS--
R
~-------~
B
D
D
1---32-1
1 - 32 ----;.-11
1--32-1
ASIN
CHSD
32-BIT FLOATING-POINT INVERSE SINE
32-BIT FIXED-POINT SIGN CHANGE
7
Binary Coding:
6
543
2
°
I _sr----L_0-L_0---L_O_L-0----l_---L_0-L_--'
7
Hex Coding:
85 with sr = 1
05 with sr =
Execution Time: 6230 to 7938 clock cycles
Description:
The 32-bit floating-point operand A at the TOS is replaced by the
32-bit floating-point inverse sine of A. The result R is a value in
radians between -1T/2 and +1T/2. Initial operands A, B, C and D
are lost.
ASIN will accept all input data values within the range of -1.0 to
+ 1.0. Values outside this range will return an error code of 1100
in the status register.
Accuracy: ASIN exhibits a maximum relative error of 4.0 x
10- 7 over the valid input data range.
Status Affected: Sign, Zero, Error Field
Hex Coding:
~------~
-TOS-
4
3
2
°
°
Status Affected: Sign, Zero, Error Field (overflow)
STACK CONTENTS
A
5
B4 with sr = 1
34 with sr =
Execution Time: 26 to 28 clock cycles
Description:
The 32-bit fixed-point two's complement integer operand A at
the TOS is subtracted from zero. The result R replaces A at
the TOS. Other entries in the stack are not disturbed.
Overflow status will be set and the TOS will be returned unchanged when A is input as the most negative value possible
in the format since no positive equivalent exists.
°
BEFORE
6
Binary Coding: LI_sr----L_0---L_---L_-L_O_L----..l_0-L_O--'
L
STACK CONTENTS
AFTER
BEFORE
R
A
~---------~
-TOS
-
AFTER
R
B
B
B
C
C
D
D
D
1-32-1
1---32-1
1---32-1
1---32-1
9-36
C
Am9S11 Application Note
cos
CHSF
32-BIT FLOATING-POINT SIGN CHANGE
7
6
543
2
32-BIT FLOATING-POINT COSINE
°
7
6
5
4
3
2
°
Binary Coding: LI_s_r---L_0----1_0----1_----1_0----1_----1_0----L_-----l
Binary Coding: LI_s_r-L_0-----lL-0-----l_0-----l_0-----l_0---'_---l._---'
Hex Coding:
Hex Coding:
95 with sr =: 1
15 with sr =:
Execution Time: 16 to 20 clock cycles
Description:
The sign of the mantissa of the 32-bit floating-point operand A at
the TOS is inverted. The result R replaces A at the TOS. Other
stack entries are unchanged.
If A is input as zero (mantissa MSB =: 0), no change is made.
Status Affected: Sign, Zero
83 with sr =: 1
03 with sr =:
Execution Time: 3840 to 4878 clock cycles
Description:
The 32-bit floating-point operand A at the TOS is replaced by
R, the 32-bit floating-point cosine of A. A is assumed to be in
radians. Operands A, C and D are lost. B is unchanged.
The COS function can accept any input data value that can
be represented in the data format. All input values are range
reduced to fall within an interval of -1T/2 to +1T/2 radians.
Accuracy: COS exhibits a maximum relative error of 5.0 x
10- 7 for all input data values in the range of -21T
to +21T radians.
Status Affected: Sign, Zero
°
STACK CONTENTS
BEFORE
AFTER
A
~------~
---TOS--
B
C
R
~------~
B
C
D
STACK CONTENTS
BEFORE
D
1---- 32-1
°
AFTER
A
~------~
1----32-1
-TOS--
R
L-------~
B
B
C
D
CHSS
1---32-1
16-BIT FIXED-POINT SIGN CHANGE
7
6
5
4
3
DADO
°
2
32-BIT FIXED-POINT ADD
Binary Coding: LI_s_r--L-_--L-_--L..-_--L..-_0---l._---l._0--L_O----'
Hex Coding:
F4 with sr =: 1
74 with sr =:
Execution Time: 22 to 24 clock cycles
Description:
16-bit fixed-point two's complement integer operand A at the TOS
is subtracted from zero. The result R replaces A at the TOS. All
other operands are unchanged.
Overflow status will be set and the TOS will be returned unchanged when A is input as the most negative value possible in
the format since no positive equivalent exists.
Status Affected: Sign, Zero, Overflow
°
7
A
..
TOS
.
6
5
4
3
2
°
Binary Coding: LI_s_r---L_0----1_---1_0----1_----L_---1_0----L_0-----l
Hex Coding:
AC with sr =: 1
2C with sr =:
Execution Time: 20 to 22 clock cycles
Description:
The 32-bit fixed-point two's (;omplement integer operand A at the
TOS is added to the 32-bit fixed-point two's complement integer
operand B at the NOS. The result R replaces operand B and the
Stack is moved up so that R occupies the TOS. Operand B is lost.
Operands A, C and D are unchanged. If the addition generates a
carry it is reported in the status register.
If the result is too large to be represented by the data format, the
least significant 32 bits of the result are returned and overflow
status is reported.
Status Affected: Sign, Zero, Carry, Error Field
STACK CONTENTS
BEFORE
1---32-1
AFTER
R
°
B
B
C
C
D
D
BEFORE
E
E
A
F
F
B
C
G
G
C
D
H
H
D
A
1 - - - 32 ---il.~1
1 -3 2 - -.....·-11
STACK CONTENTS
~------~
9-37
AFTER
-TOS-
R
~-------~
Am9S11 Application Note
DDIV
DMUU
32-BIT FIXED-POINT DIVIDE
32-BIT FIXED-POINT MULTIPLY, UPPER
7
6
5
4
3
2
7
°
6
5
4
321
°
]j]
Binary Coding: L-I_s_r--'--_0---''------'_0--'_----'_--'_--'-_---'
Binary Coding :1L _s_r...L._0--.JL-.---1_--.J_O---'_---'_1
Hex Coding:
Hex Coding:
AF with sr :=: 1
2F with sr :=: °
Execution Time: 196 to 210 clock cycles when A f= °
18 clock cycles when A :=: 0.
Description:
The 32-bit fixed-point two's complement integer operand B at
NOS is divided by the 32-bit fixed-point two's complement integer operand A at the TOS. The 32-bit integer quotient R replaces B and the stack is moved up so that R occupies the
TOS. No remainder is generated. Operands A and B are lost.
Operands C and D are unchanged.
If A is zero, R is set equal to B and the divide-by-zero error
status will be reported. If either A or B is the most negative
value possible in the format, R will be meaningless and the
overflow error status will be reported.
Status Affected: Sign, Zero, Error Field
STACK CONTENTS
BEFORE
A
r--------,
R
B
C
C
D
D
1---32--1
6
5
4
R
~------~
C
D
D
~
1 - - - 32----0..-11
1--32--1
DSUB
32-BIT FIXED-POINT SUBTRACT
3
2
°
Bina ry Coding: L-I_s_r--'-_0---'_---'_0-.1._-.1._----'_-.1._0--'
Hex Coding:
AE with sr :=: 1
2E with sr :=: °
Execution Time: 194 to 210 clock cycles
Description:
The 32-bit fixed-point two's complement integer operand A at the
TOS is multiplied by the 32-bit fixed-point two's complement integer operand B at the NOS. The 32-bit least significant half of the
product R replaces B and the stack is moved up so that R occupies the TOS. The most significant half of the product is lost.
Operands A and B are lost. Operands C and D are unchanged.
The overflow status bit is set if the discarded upper half was
non-zero. If either A or B is the most negative value that can
be represented in the format, that value is returned as Rand
the overflow status is set.
Status Affected: Sign, Zero, Overflow
STACK CONTENTS
AFTER
C
32-BIT FIXED-POINT MULTIPLV, LOWER
7
-TOS---
B
1--32-1
DMUL
BEFORE
STACK CONTENTS
BEFORE
AFTER
-TOS---
A
B6 with sr :=: 1
36 with sr :=: °
Execution Time: 182 to 218 clock cycles
Description:
The 32-bit fixed-point two's complement integer operand A at
the TOS is multiplied by the 32-bit fixed-point two's complement integer operand B at the NOS. The 32-bit most significant half of the product R replaces B and the stack is moved
up so that R occupies the TOS. The least significant half of
the product is lost. Operands A and B are lost. Operands C
and D are unchanged.
If A or B was the most negative value possible in the format,
overflow status is set and R is meaningless.
Status Affected: Sign, Zero, Overflow
7
6
5
4
3
2
°
Binary Coding: 0_°............1_-.1._°---'-_---'-_---'-_°-----1-_--'
Hex Coding:
AD with sr = 1
2D with sr :=: °
Execution Time: 38 to 40 clock cycles
Description:
The 32-bit fixed-point two's complement operand A at the
TOS is subtracted from the 32-bit fixed-point two's complement operand B at the NOS. The difference R replaces
operand B and the stack is moved up so that R occupies the
TOS. Operand B is lost. Operands A, C and D are unchanged.
If the subtraction generates a borrow it is reported in the carry
status bit. If A is the most negative value that can be represented in the format the overflow status is set. If the result
cannot be represented in the data format range, the overflow
bit is set and the 32 least significant bits of the result are retumed as R.
Status Affected: Sign, Zero, Carry, Overflow
AFTER
BEFORE
STACK CONTENTS
AFTER
R
A
B
C
B
C
C
D
C
D
A
-TOS---
----TOS---
R
D
D
A
1--32-1
1 - -32----0--11
1----32--1
1---32--1
9-38
Am9511 Application Note
EXP
FDIV
32-BIT FLOATING-POINT eX
32-BIT FLOATING-POINT DIVIDE
7
6
5
°
432
7
6
5
4
3
2
°
Binary Coding ~ Ic--sr------'_o------'_o--'-_o--'-_--'-_o------'_--L_o---'
Bi nary Coding: ,-I_s_r-'--_0--'-_0--'-_--'-_0--'-_0---,_--'-_--'
Hex Coding:
Hex Coding:
93 with sr = 1
13 with sr =
Execution Time: 154 to 184 clock cycles for A f
22 clock cycles for A =
Description:
32-bit floating-point operand B at NOS is divided by 32-bit
floating-point operand A at the TOS. The result R replaces Band
the stack is moved up so that R occupies the TOS. Operands A
and B are lost. Operands C and D are unchanged.
If operand A is zero, R is set equal to B and the divide-by-zero
error is reported in the status register. Exponent overflow or
underflow is reported in the status register, in which case the
mantissa portion of the result is correct and the exponent portion
is offset by 128.
Status Affected: Sign, Zero, Error Field
8A with sr = 1
OA with sr =
Execution Time: 3794 to 4878 clock cycles for IAI :S 1.0 x 2 5
34 clock cycles for IAI > 1.0 x 25
Description:
The base of natural logarithms, e, is raised to an exponent value
specified by the 32-bit floating-point operand A at the TOS. The
result R of eA replaces A. Operands A, C and D are lost. Operand
B is unchanged.
EXP accepts all input data values within the range of -1.0 x 2+ 5
to + 1.0 X 2+ 5 . Input values outside this range will return a code of
1100 in the error field of the status register.
Accuracy: EXP exhibits a maximum relative error of 5.0 x
10-7 over the valid input data range.
Status Affected: Sign, Zero, Error Field
°
ST ACK CONTENTS
BEFORE
A
-TOS---
B
°
°
ST ACK CONTENTS
°
AFTER
BEFORE
R
A
B
B
C
C
D
C
D
-TOS---
AFTER
R
D
1---32-1
1--32-1
1--32-1
1---32-1
FADD
FIXD
32-BIT FLOATING-POINT ADD
32-BIT FLOATING-POINT TO
32-BIT FIXED-POINT CONVERSION
7
6
5
320
4
7
Binary Coding: ,-I_sr------'_O--'-_O--'-_--'-_o--'-_o--'-_o--'-_o---'
Hex Coding:
° °
BEFORE
STACK CONTENTS
A
--TOS-
5
4
320
Binary Coding: LI_s_r--L-_O--'_0--l_---1_--l_---1_--'-_0---l
90 with sr = 1
10 with sr =
Execution Time: 54 to 368 clock cycles for A of24 clock cycles for A =
Description:
32-bit floating-point operand A at the TOS is added to 32-bit
floating-point operand B at the NOS. The result R replaces Band
the stack is moved up so that R occupies the TOS. Operands A
and B are lost. Operands C and D are unchanged.
Exponent alignment before the addition and normalization of the
result accounts for the variation in execution time. Exponent
overflow and underflow are reported in the status register, in
which case the mantissa is correct and the exponent is offset by
128.
Status Affected: Sign, Zero, Error Field
°
6
Hex Coding:
9E with sr = 1
1E with sr =
Execution Time: 90 to 336 clock cycles
Description:
32-bit floating-point operanc;l A at the TOS is converted to a
32-bit fixed-point two's complement integer. The result R replaces A. Operands A and D are lost. Operands Band Care
unchanged.
If the integer portion of A is larger than 31 bits when converted, the overflow status will be set and A will not be
changed. Operand D, however, will still be lost.
Status Affected: Sign, Zero Overflow
AFTER
BEFORE
°
STACK CONTENTS
-TOS---
AFTER
R
R
A
B
C
B
B
C
D
C
C
1--32-1
1--32-1
~----------~
r------------~
D
1---32-1
D
9-39
1--32-1
m
•
Am9511 Application Note
FIXS
FLTS
32-BIT FLOATING-POINT TO
16-BIT FIXED-POINT CONVERSION
16-BIT FIXED-POINT TO
32-BIT FLOATING-POINT CONVERSION
7
5
6
4
3
2
7
°
6
5
4
3
2
°
Binary Coding: L-I_sr--L_0---L_0--L_--L_-L-_----'--_-L-----l
Binary Coding: Li_IL--0--L_0---L_---L_--.L_--L_o_L--'
Hex Coding:
9D with sr = 1
1D with sr =
Execution Time: 62 to 156 clock cycles
Description:
16-bit fixed-point two's complement integer A at the TOS is
converted to a 32-bit floating-point number. The lower half of the
result R (RI) replaces A, the upper half (Ru) replaces H and the
stack is moved down so that Ru occupies the TOS. Operands A,
F, G and H are lost. Operands B, C, D and E are unchanged.
Status Affected: Sign, Zero
9F with sr = 1
1F with sr =
Execution Time: 90 to 214 clock cycles
Description:
32-bit floating-point operand A at the TOS is converted to a
16-bit fixed-point two's complement integer. The result R rep/aces the lower half of A and the stack is moved up by two
bytes so that R occupies the TOS. Operands A and Dare
lost. Operands Band C are unchanged, but appear as upper
(u) and lower (I) halves on the 16-bit wide stack if they are
32-bit operands.
If the integer portion of A is larger than 15 bits when converted, the overflow status will be set and A will not be
changed. Operand D, however, will still be lost.
Status Affected: Sign, Zero, Overflow
STACK CONTENTS
BEFORE
..
A
TOS ------1_
Bu
C
BI
AFTER
TOS -----t_1
Ru
RI
B
C
B
D
C
E
D
F
E
G
Cu
3 2 - -.....-11
STACK CONTENTS
A
R
B
°
BEFORE
AFTER
D
f-ool.e
. ----
Hex Coding:
°
H
CI
FMUL
32-BIT FLOATING-POINT
MULTIPLY
FLTD
7
32-BIT FIXED-POINT TO
32-BIT FLOATING-POINT CONVERSION
6
5
6
° °
9C with sr
1
4
3
2
° °
~~_---L_~_~_----'--_~_~----l
Hex Coding:
=
°
1C with sr =
Execution Time: 56 to 342 clock cycles
Description:
32-bit fixed-point two's complement integer operand A at the TOS
is converted to a 32-bit floating-point number. The result R replaces A at the TOS. Operands A and D are lost. Operands Band
C are unchanged.
Status Affected: Sign, Zero
BEFORE
A
STACK CONTENTS
---TOS-
3
°
2
92 with sr = 1
12 with sr =
Execution Time: 146 to 168 clock cycles
Description:
32-bit floating-point operand A at the TOS is multiplied by the
32-bit floating-point operand B at the NOS. The normalized result
R replaces B and the stack is moved up so that R occupies the
TOS. Operands A and B are lost. Operands C and D are unchanged.
Exponent overflow or underflow is reported in the status register,
in which case the mantissa portion of the result is correct and the
exponent portion is offset by 128.
Status Affected: Sign, Zero, Error Field
ST ACK CONTENTS
AFTER
BEFORE
°
Binary Coding: I sr
4
Binary Coding: L-I_s_r---L-_0---L_0--L_--L_O_L--0-'L-----L_O---'
Hex Coding:
7
5
AFTER
A
R
°
-TOS-
R
B
B
B
C
C
C
C
D
D
1--32---1
D
1--32-1
1-32-1
9-40
1-32-1
Am9S11 Application Note
FSUB
LN
32-BIT FLOATING-POINT SUBTRACTION
32-BIT FLOATING-POINT
NATURAL LOGARITHM
7
Binary Coding:
5
6
4
3
°
2
IL_sr----'-_o--'-_o_-'---_L-0----'_o----'_o--'-_~
Hex Coding:
7
91 with sr = 1
11 with sr =
Execution Time: 70 to 370 clock cycles for A oJ
26 clock cycles for A =
Description:
32-bit floating-point operand A at the TOS is subtracted from
32-bit floating-point operand B at the NOS. The normalized
difference R replaces B and the stack is moved up so that R
occupies the TOS. Operands A and B are lost. Operands C
and D are unchanged.
Exponent alignment before the subtraction and normalization
of the result account for the variation in execution time.
Exponent overflow or underflow is reported in the status register in which case the mantissa portion of the result is correct
and the exponent portion is offset by 128.
Status Affected: Sign, Zero, Error Field (overflow)
°
STACK CONTENTS
A
---TOS-
Hex Coding:
C
D
2,
°
Status Affected: Sign, Zero, Error Field
BEFORE
STACK CONTENTS
AFTER
A
-TOS---
R
B
B
c
o
1-32-1
1-32-1
LOG
1-32----"-11
32-BIT FLOATING-POINT
COMMON LOGARITHM
7
Binary Coding:
1
sr
6
1
5
° °
1
4
1
3
0
2
°
o
°o
NO
OPERATION
88 with sr = 1
08 with sr: = 0
Execution Time: 4474 to 7132 clock cycles for A> 0
20 clock cycles for A .:;;
Description:
The 32-bit floating-point operand A at the TOS is replaced by R,
the 32-bit floating-point common logarithm (base 10) of A.
Operands A, C and 0 are lost. Operand B is unchanged.
The LOG function accepts any positive input data value that can
be represented by the data format. If LOG of a non-positive value
is attempted an error status of 0100 is returned.
Accuracy: LOG exhibits a maximum absolute error of 2.0 x 10-7
for the input range from 0.1 to 10, and a maximum
relative error .of 2.0 x 10-7 for positive values less
than 0.1 or greater thao 10.
Status Affected: Sign, Zero, Error Field
°
STACK CONTENTS
-TOS
B
7
6
543
2
Binary COding: 'I sr
0
0
0
Hex Coding:
0
0
0
0
°
80 with sr = 1
00 with sr =
Execution Time: 4 clock cycles
Description:
The NOP command performs no internal data manipulations. It
may be used to set or clear the service request interface line
without changing the contents of the stack.
Status Affected: The status byte is cleared to all zeroes.
AFTER
R
B
C
o
1-32----1
1-----32-1
NOP
Hex Coding:
BEFORE
°
°
D
A
3
°
R
C
4
89 with sr = 1
09 with sr =
Execution Time: 4298 to 6956 clock cycles for A >
20 clock cycles for A.:;;
Description:
The 32-bit floating-point operand A at the TOS is replaced by
R, the 32-bit floating-point natural logarithm (base e) of A.
Operands A, C and 0 are lost. Operand B is unchanged.
The LN function' accepts all positive input data values that can
be represented by the data format. If LN of a non-positive
number is attempted an error status of 0100 is returned.
Accuracy: LN exhibits a maximum absolute error of 2 x 10- 7
for the input range from e- 1 to e, and a maximum
relative error of 2.0 x 10- 7 for positive values less
than e- 1 or greater than e.
AFTER
B
5
Binary Coding: LI_sr----'-_O--'-_O--'-_0_-'--_'--0_'--0----'-_--'
°
°
BEFORE
6
"""1·1----32--....·~1
9-41
°
m
Am9S11 Application Note
Binary Coding:
I
POPD
POPS
32-81T
STACK POP
16-81T
STACK POP
7
6
sr
0
5
4
3
2
0
0
0
7
Binary Coding:
0
I
~~
__
4
5
6
sr
~
__
~
2
3
_ _- L_ _
~
o
__
~
o
__
o
o
~~
B8 with sr = 1
38 with sr = 0
Execution Time: 12 clock cycles
Description:
The 32-bit stack is moved up so that the old NOS becomes the
new TOS. nre previous TOS rotates to the bottom of the stack. All
operand values are unchanged. POPD and POPF execute the
same operation.
Status Affected: Sign, Zero
Hex Coding:
F8 with sr = 1
78 with sr = 0
Execution Time: 10 clock cycles
Description:
The 16-bit stack is moved up so that the old NOS becomes the
new TOS. The previous TOS rotates to the bottom of the stack. All
operand values are unchanged.
Status Affected: Sign, Zero
STACK CONTENTS
STACK CONTENTS
Hex Coding:
BEFORE
AFTER
BEFORE
B
A
B
c
B
C
c
D
C
D
D
A
D
E
1--32---1
1--32---1
E
F
F
G
G
H
H
A
A
Binary Coding:
-TOS-
POPF
PTOD
32-81T
STACK POP
PUSH 32-81T
TOS ONTO STACK
7
6
5
I sr
0
0
4
3
2
0
0
0
Binary Coding:
0
98 with sr = 1
18 with sr = 0
Execution Time: 12 clock cycles
Description:
The 32-bit stack is moved up so that the old NOS becomes the
new TOS. The old TOS rotates to the bottom of the stack. All
operand values are unchanged. POPF and POPD execute the
same operation.
Status Affected: Sign, Zero
Hex Coding:
-TOS-
7
6
I sr
0
5
3"
4
AFTER
B
2
0
0
Hex Coding:
B7 with sr = 1
37 with sr = 0
Execution Time: 20 clock cycles
Description:
The 32-bit stack is moved down and the previous TOS is
copied into the new TOS location. Operand D is lost. All other
operand values are unchanged. PTOD and PTOF execute the
same operation.
Status Affected: Sign, Zero
STACK CONTENTS
BEFORE
A
..
TOS
STACK CONTENTS
AFTER
B
B
C
C
D
D
A
1---32-1
1---32-1
BEFORE
~
AFTER
_TOS_~
1-32-1
9-42
1-32-1
Am9S11 Application Note
PTOF
PUPI
PUSH 32-BIT
TOS ONTO STACK
PUSH 32-BIT
FLOATING-POINT 1T
7
Binary Coding:
I sr
6
5
0
0
4
3
2
0
Binary Coding:
0
Hex Coding:
I
7
6
5
sr
0
0
4
3
2
0
0
0
97 with sr = 1
17 with sr = 0
Execution Time: 20 clock cycles
Description:
The 32-bit stack is moved down and the previous TOS is copied
into the new TOS location. Operand D is lost. All other operand
values are unchanged. PTOF and PTOD execute the same operation.
Status Affected: Sign, Zero
9A wit/1sr = 1
1A with sr = 0
Execution Time: 16 clock cycles
Description:
The 32-bit stack is moved down so that the previous TOS occupies the new NOS location. 32-bit floating-point constant 17' is
entered into the new TOS location. Operand D is lost. Operands
A, Band C are unchanged.
Status Affected: Sign, Zero
STACK CONTENTS
STACK CONTENTS
BEFORE
A
Hex Coding:
AFTER
BEFORE
AFTER
A
A
B
A
B
c
B
C
B
D
c
D
C
1-32-1
11-01- - 3 2 - - - - - 1
---TOS----
1-32---1
1-1 .....---
32---l
PTOS
PUSH 16-BIT
TOS ONTO STACK
7
Binary Coding:
6
543
I sr I 1 I 1 I
2
0
0
Hex Coding:
F7 with sr = 1
77 with sr = 0
Execution Time: 16 clock cycles
Description:
The 16-bit stack is moved down and the previous TOS is copied
into the new TOS location. Operand H is lost and all other
operand values are unchanged.
Status Affected: Sign, Zero
STACK CONTENTS
BEFORE
A
B
AFTER
TOS
A
A
C
B
D
C
E
D
F
E
G
F
H
G
9-43
I--- TOS-
17'
A
Am9S11 Application Note
SADD
PWR
32-81T
16-81T
FLOATING-POINT XV
FIXED-POINT ADD
7
Binary Coding:
6
5
4
3
2
1
°
7
I _s_r--'--_0---l_0---l_o--'_---l_o--'l_iliJ
5
4
3
°
2
Binary Codi ng :\L _s_r-"--_-'-_-"--_0--'_--'_ _'---0--'_0--'
L
Hex Coding:
6
8B with sr = 1
OB with sr =
Execution Time: 8290 to 12032 clock cycles
Description:
32-bit floating-point operand B at the NOS is raised to the power
specified by the 32-bit floating-point operand A at the TOS. The
result R of BA replaces B and the stack is moved up so that R
occupies the TOS. Operands A, B, and D are lost. Operand C is
unchanged.
The PWR function accepts all input data values that can be
represented in the data format for operand A and all positive
values for operand B. If operand B is non-positive an error status
of 0100 will be returned. The EXP and LN functions are used to
implement PWR using the relationship BA = EXP [A(LN B)].
Thus if the term [A(LN B)] is outside the range of -1.0 x 2+ 5 to
+ 1.0 X 2+ 5 an error status of 1100 will be returned. Underflow and
overflow conditions can occur.
Hex Coding:
EC with sr = 1
6C with sr =
Execution Time: 16 to 18 clock cycles
Description:
16-bit fixed-point two's complement integer operand A at the
TOS is added to 16-bit fixed-point two's complement integer
operand B at the NOS. The result R replaces B and the stack
is moved up so that R occupies the TOS. Operand B is lost.
All other operands are unchanged.
If the addition generates a carry bit it is reported in the status
register. If an overflow occurs it is reported in the status register and the 16 least significant bits of the result are returned.
Status Affected: Sign, Zero, Carry, Error Field
°
°
Accuracy: The error performance for PWR is a function of
the LN and EXP performance as expressed by:
I(Relative Error)PWR!= !(Relative Error)EXP+ !A(Absolute
ErrorlLNI
The maximum relative error for PWR occurs when
A is at its maximum value while [A(LN B)] is near
1.0 x 2 5 and the EXP error is also at its maximum. For most practical applications the relative
error for PWR will be less than 7.0 x 10- 7
STACK CONTENTS
A
A
---TOS-
B
R
C
C
D
AFTER
D
E
R
E
F
C
F
G
G
H
H
A
C
o
1-1'---32---1
TOS
B
STACK CONTENTS
BEFORE
AFTER
BEFORE
Status Affected: Sign, Zero, Error Field
1---- 32----1
9-44
Am9511 Application Note
SDIV
SIN
16-BIT
FIXED-POINT DIVIDE
32-BIT
FLOATING-POINT SINE
7
6
5
4
3
2
0
Binary Codi ng :1~_s_r....I.-_-'--_...L-_O--'-_---'-_---'-_--'-------'
Binary Coding:
I
7
6
5
4
3
2
sr
0
0
0
0
0
o
o
82 with sr = 1
02 with sr = 0
Execution Time: 3796 to 4808 clock cycles for IAI > 2- 12
radians
30 clock cycles for IAI.,,; 2- 12 radians
Description:
The 32-bit floating-point operand A at the TOS is replaced by
R, the 32-bit floating-point sine of A. A is assumed to be in
radians. Operands A, C and 0 are lost. Operand B is unchanged.
Hex Coding:
EF with sr = 1
6F with sr = 0
Execution' Time: 84 to 94 clock cycles for A ~ 0
14 clock cycles for A = 0
Description:
16-bit fixed-point two's complement integer operand B at the
NOS is divided by 16-bit fixed-point two's complement integer
operand A at the TOS. The 16-bit integer quotient R replaces B
and the stack is moved up so that R occupies the TOS. No
remainder is generated. Operands A and B are lost. All other
operands are unchanged.
If A is zero, R will be set equal to B and the divide-by-zero error
status will be reported.
Status Affected: Sign, Zero, Error Field
Hex Coding:
The SIN function will accept any input data value that can be
represented by the data format. All input values are range reduced to fall within the interval -TT/2 to +rr/2 radians.
Accuracy: SIN exhibits a maximum relative error of 5.0 x
10- 7 for input values in the range of -2rr to +2rr
radians.
Status Affected: Sign, Zero
STACK CONTENTS
BEFORE
A
AFTER
TOS
R
B
C
C
0
0
E
BEFORE
E
F
A
F
G
B
G
H
C
H
~
1-16--1
1--16--1
o
1-32-1
STACK CONTENTS
9-45
AFTER
---TOS-
R
B
Am9S11 Application Note
Binary Coding:
Hex Coding:
SMUL
SMUU
16-BIT FIXED-POINT
MULTIPLV, LOWER
16-BIT FIXED-POINT
MULTIPL V, UPPER
7
6
I sr I
1
I
5
4
1
°
3
2
7
°°
Bina ry Coding:
6
5
4
3
°
2
0
_sr----1_--L_---L._-t-_O
_ - ' - - - _ l . . . . . . - - - - - 1 _---'
LI
EE with sr = 1
6E with sr =
Execution Time: 84 to 94 clock cycles
Description:
16-bit fixed-point two's complement integer operand A at the TOS
is multiplied by the 16-bit fixed-point two's complement integer
opeJand B at the NOS. The 16-bit least significant half of the
product R replaces B and the stack is moved up so that R
occupies the TOS. The most significant half of the product is lost.
Operands A and B are lost. All other operands are unchanged.
The overflow status bit is set if the discarded upper half was
non-zero. If either A or B is the most negative value that can be
represented in the format, that value is returned as R and the
overflow status is set.
Status Affected: Sign, Zero, Error Field
°
F6 with sr = 1
76 with sr. =
Execution Time: 80 to 98 clock cycles
Descri ption:
16-bit fixed-point two's complement integer operand A at the
TOS is multiplied by the 16-bit fixed-point two's complement
integer operand B at the NOS. The 16-bit most significant half
of the product R replaces B and the stack is moved up so that
R occupies the TOS. The least significant half of the product
is lost. Operands A and B are lost. All other operands are unchanged.
If either A or B is the most negative value that can be represented in the format, that value is returned as R and the
overflow status is set.
Status Affected: Sign, Zero, Error Field
STACK CONTENTS
STACK CONTENTS
Hex Coding:
°
AFTER
BEFORE
R
A
B
C
B
C
C
0
C
0
0
E
0
E
E
F
E
F
F
G
F
G
G
H
G
H
H
><
H
BEFORE
A
TOS
1--16--1
9-46
AFTER
TOS
R
><
1--16--1
Am9S11 Application Note
SQRT
TAN
32-BIT FLOATING-POINT SQUARE ROOT
32-BIT FLOATING-POINT TANGENT
Binary Coding:
1
7
6
5
4
3
2
sr
a
a
a
a
a
a
7
a
Binary Coding:
STACK CONTENTS
AFTER
A
----TOS-
R
B
B
C
C
32-1
1-
SSUB
16-BIT FIXED-POINT SUBTRACT
Binary Coding:
1
7
6
5
sr
__
__
L-~
~
4
~
a
_ _- L_ _
a
2
3
~
__
~
a
__
STACK CONTENTS
..
TOS
BEFORE
STACK CONTENTS
AFTER
A
--TOS-
R
B
C
~~
ED with sr = 1
6D with sr = a
Execution Time: 30 to 32 clock cycles
Description:
16-bit fixed-point two's complement integer operand A at the
TOS is subtracted from 16-bit fixed-point two's complement integer operand B at the NOS. The result R replaces B and the
stack is moved up so that R occupies the TOS. Operand B is
lost. All other operands are unchanged.
If the subtraction generates a borrow it is reported in the carry
status bit. If A is the most negative value that can be represented in the format the overflow status is set. If the result
cannot be represented in the format range, the overflow
status is set and the 16 least significant bits of the result are
returned as R.
Status Affected: Sign, Zero, Carry, Error Field
BEFORE
320
B
Hex Coding:
~I
4
84 with sr = 1
04 with 'sr = a
Execution Time: 4894 to 5886 clock cycles for IAI > 2- 12
radians
30 clock cycles for IAI ~ 2- 12 radians
Description:
The 32-bit floating-paint operand A at the TOS is replaced by
the 32-bit floating-point tangent of A. Operand A is assumed
to be in radians. A, C and D are lost. B is unchanged.
The TAN function will accept any input data value that can be
represented in the data format. All input data values are
range-reduced to fall within -7T/4 to +7T/4 radians. TAN is unbounded for input values near odd multiples of 7T/2 and in
such cases the overflow bit is set in the status register. For
angles smaller than 2- 12 radians, TAN, returns A as the tangent of A.
Accuracy: TAN exhibits a maximum relative error of 5.0 x
10- 7 for input data values in the range of - 27T to
+27T radians except for data values near odd multiples of 7T/2.
Status Affected: Sign, Zero, Error Field (overflow)
D
1-32--1
5
Hex Coding:
81 with sr = 1
01 with sr = a
Execution Time: 782 to 870 clock cycles
Description:
32-bit floating-point operand A at the TOS is replaced by R, the
32-bit floating-point square root of A. Operands A and D are lost.
Operands Band C are not changed.
SORT will accept any non-negative input data value that can be
represented by the data format. If A is negative an error code of
0100 will be returned in the status register.
Status Affected: Sign, Zero, Error Field
Hex Coding:
BEFORE
6
_s_r--,--_O~__
O~_O__-"--O__-,---__-,---O---,__O---,
,--I
D
1----32-1
1-32-1
XCHD
EXCHANGE 32-BIT STACK OPERANDS
7
6
5
3
4
a
2
Binary Coding: L[Sf_sr-l.__
0---L__- L_ _~_ _~_O---.J'--O--'-__-'
Hex Coding:
B9 with sr = 1
39 with sr = a
Execution Time: 26 clock cycles
Description:
32-bit operand A at the TOS and 32-bit operand B at the NOS
are exchanged. After execution, B is at the TOS and A is at
the NOS. All operands are unchanged. XCHD and XCHF
execute the same operation.
Status Affected: Sign, Zero
AFTER
R
B
C
C
D
D
E
BEFORE
STACK CONTENTS
E
F
A
--TOS-
AFTER
B
F
G
B
A
G
H
C
C
H
A
D
1-32-1
9-47
D
1 - - - - 32-----1
Am9S11 Application Note
Binary Coding:
1
XCHF
XCHS
EXCHANGE 32-BIT
STACK OPERANDS
EXCHANGE 16-BIT
STACK OPERANDS
7
6
5
sr
a
a
L-~
Hex Coding:
_ _- L_ _
3
4
~
__
~
__
a
2
a
~
__
a
L_~
__
7
6
543
Binary Coding :1L _sr----'-__- L_ _- - ' -_ _- L -_ _
~
99 with sr = 1
19 with sr =
Execution Time: 26 clock cycles
Description:
32-bit operand A at the TOS and 32-bit operand B at the NOS
are exchanged. After execution, B is at the TOS and A is at
the NOS. All operands are unchanged. XCHD and XCHF
execute the same operation.
Status Affe'cted: Sign, Zero
a
2
~O__L_0~__~
Hex Coding:
F9 with sr = 1
79 with sr = a
Execution Time: 18 clock cycles
Description:
16-bit operand A at the TOS and 16-bit operand B at the NOS
are exchanged. After execution, B is at the TOS and A is at
the NOS. All operand values are unchanged.
Status Affected: Sign, Zero
a
STACK CONTENTS
AFTER
BEFORE
A
TOS
B
B
A
C
C
AFTER
D
D
B
E
E
B
A
F
F
C
C
G
G
D
D
H
H
1-32-1
1----32-1
1--16--1
ST ACK CONTENTS
BEFORE
A
--TOS-
9-48
Advanced Micro Devices
Designing Interrupt Systems
With the Am9519 Universal
Interrupt Controller
By Joseph H. Kroeger
Copyright
©
1978 by Advanced Micro Devices, Inc.
Advanced Micro Devices cannot assume responsibility for use of any circuitry described other than circuitry entirely
embodied in an Advanced Micro Devices' product.
AM-PUB071
9-49
TABLE OF CONTENTS
I INTRODUCTION
General ...................................................................... 9-51
Features ..................................................................... 9-51
II HARDWARE INTERFACE
Block Diagram ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Interface Signal Description ....................................................
Interface Considerations .......................................................
IREO Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
9-52
9-52
9-53
9-54
9-55
III OPERATING DESCRIPTION
Reset ........................................................................
Register Description ...........................................................
Information Transfers ..........................................................
Operating Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Operating Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
9-56
9-56
9-58
9-58
9-60
IV COMMAND DESCRIPTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-61
V SYSTEM INTERFACE
Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-64
Initialization and Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-65
9-50
Am9519 Application Note
INTRODUCTION
MAIN PROGRAM
General
Processors exist as tools for the implementation of information
system transfer functions. All useful processor systems include at least one peripheral device in order to communicate
with the user of the system. The processor not only manipulates information once it is in the system, but also handles the
transfer of information to and from the user via the peripherals. Often several devices are integral parts of the overall system. All peripherals must be serviced in one way or another
by the system processor. The basic parameters that influence
the design of peripheral serviCing algorithms are the frequency of service required, the service latency allowed and
the service duty cycle of the devices.
There are two general methods used to initiate and coordinate
this activity: Program controlled service and Interrupt driven
service. In program controlled transfers, the processor
schedules all peripheral events; an Interrupt driven system, on
the other hand, allows modification of the system activities by
external devices.
Figure 1. Basic Interrupt Procedure.
Features
With no interrupt capability, processors must depend on
software polling techniques to service peripheral devices. As
the number of such devices grows and/or as the complexity of
service increases, the polling program becomes very time
consuming and the overhead devoted to polling becomes a
significant fraction of the available processing resource. When
this limits system performance, the use of interrupts can often
provide substantial improvement.
The Am9519 Universal Interrupt Controller is a processor
support device designed to enhance the interrupt handling
capability of a wide variety of processors. A single Am9519
manages the masking, priority resolution and vectoring of up
to eight interrupts. It may be easily expanded by the addition
of other Am9519 chips to handle a nearly unlimited set of interrupt inputs. It offers many programmable operating options
to improve both the efficiency and versatility of its host system
operations. The Am9519 is well adapted to a wide range of
uses including small, simple, as well as large, sophisticated,
interrupt systems.
Interrupts are used to enhance processor system throughput
and response time by minimizing or eliminating the need for
software polling procedures. Interrupts are hardware
mechanisms that allow devices external to the processor to
asynchronously modify the instruction sequence of the processor program being executed. An elementary single interrupt could be used simply to alert the processor to the fact
that some kind of service is desired and thus to initiate a polling routine. More complex systems may have multiple interrupts and vectoring protocols which can be used to further
improve performance and eliminate all polling requirements.
Vectoring allows direct identification of the interrupting device
and its associated service routine.
The Am9519 provides any mix of one, two, three and four
byte responses to the host processor during the interrupt
acknowledge process. The response bytes are all fully programmable so that any appropriate addressing, vectoring, instruction or other message protocol may be used. Contention
among multiple interrupts is managed interr,dlly using either
fixed or rotating priority resolution circuitry. The direct vectoring capability ofthe Am9519 may be bypassed using the polled
mode option.
An internal mask register permits individual interrupts to be disabled. It may be loaded in parallel by the host processor with any
bit pattern, or mask bits may be individually controlled. The interrupt inputs use "pulse-catching" circuitry so that an external
register is not needed to capture interrupt pulses. Narrow noise
pulses, however, are ignored. The interrupt· polarity may be
selected as either active-high or active-low.
Figure 1 illustrates the essential functioning of a typical interrupt procedure. As the main program is executing instructions,
an external interrupt arrives, in this example during instruction
M+2.The processor completes M+2 and then, instead of
executing M+3, it performs some kind of interrupt acknowledge procedure, often involving execution of an additional interrupt instruction. The result will usually be that the address
of instruction M+3 is saved for future reference, and the location of instruction N is determined. The processor then proceeds to execute the interrupt service routine starting with instruction N. The service routine may save, and later restore,
the processor status as well as perform tasks requested by
the interrupting device. The last instruction in the routine
(N+K) directs the processor to resume the main program at
instruction M+3.
Another important feature of the Am9519 is its ability to generate software interrupts. The host processor can set interrupt
requests under program control, thus permitting hardware to
resolve the priority of software tasks. This is often .a powerful
system asset, especially for sophisticated operating software,
as well as an aid for system testing, diagnostiC, debugging
and maintenance procedures.
The Am9519 is implemented with AM D's LlNOX n-channel
silicon gate MOS technology. This process features low profile
structures, triple ion-implantation, both depletion and
enhancement transistors, and small, low capacitance, low
power, high speed Circuitry. The chip contains 4,400 transistors within a total chip area of 28,766 square mils. It is packaged in a standard 28-pin dual in-line package.
Notice that the presence of the hardware interrupt has caused
a modification of the sequence of instruction execution; an
additional block of instructions has been inserted in the main
program. Interrupts provide the system designer with a significant capability that can help optimize his cost/performance
tradeoffs.
9-51
m
Am9519 Application Note
CHIP SELECT
READ
WRITE
BYTE
COUNT
MEMORY
8.2
R/WRAM
BUS
CONTROL
CONTROUDATA
RESPONSE
MEMORY
8.32
RIW RAM
PAUSE
INTERRUPT ACKNOWLEDGE
RESPONSE IN PROCESS
ENABLE IN
INTERRUPT
CONTROL
ENABLE OUT
INTERRUPT
REQUESTS
GROUP INTERRUPT
MOS-018
Figure 2. Am9519 Block Diagram.
HARDWARE INTERFACE
Description
Block Diagram
+5 Volts
Ground
Data Bus
Response In Process
Interrupt Request
Chip Select
Read
Write
Control/Data
Interrupt Acknowledge
Enable In
Enable Out
Group Interrupt
Pause
The block diagram of the Am9519 shown in Figure 2 indicates
the interface signals and the basic internal information flow.
Interrupt Request inputs are captured and latched in the Interrupt Request register. Any requests not masked by the Interrupt Mask register will cause a Group Interrupt output to the
host processor if the unit is enabled. When the processor is
ready to handle the interrupt it issues an Interrupt Acknowledge pulse which causes (a) the priority of pending interrupts
to be resolved and (b) a byte from the response memory associated with the highest priority interrupt to be transferred to
the data bus. The transfer of additional response bytes is controlled by additional Interrupt Acknowledge signals. Other interrupt management functions are controlled by the Auto
Clear register, the Interrupt Service register and the Mode register. Control of the Am9519 is exercised by the host processor using the Command register. The Status register reports
on the internal condition of the part.
Abbreviation
Type
Pins
-
VCC
VSS
DB
RIP
IREO
CS
RD
WR
C/O
lACK
EI
EO
GINT
PAUSE
Power
Power
I/O
I/O
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
1
1
8
1
8
1
1
1
1
1
1
1
1
1
Figure 3. Am9519 Interface Signal Summary.
The Am9519 is addressed by the host processor as two distinct ports: a control port and a data port. The control port
provides direct access to the Status register and the Command register. The data port is used to communicate with all
other internal locations.
Interface Signal Description
Figure 3 summarizes the interface signals. Figure 4 shows the
interface signal pin assignments.
Data Bus (DB)
The eight three-state bidirectional data bus lines are used to
transfer information between the Am9519 and the system
data bus. The direction of information flow is controlled by the
CS, RD, WR and lACK input signals. Data and command information are written into the device; status, data and response information are output by it.
cs
28
VCC (+5V)
WIl
27
C/D
1m
26
TAl:R
DB7
25
IREm
DB6
24
IRE06
DB5
23
IRE05
DB4
22
IRE04
DB3
21
IRE03
DB2
20
IRE02
Am9519
DBl
10
19
IREOl
DBa
11
18
IREOO
TITP
12
17
GINT
EI
13
16
EO
(GND)VSS
14
15
PAUSE
MOS-019
Figure 4. Connection Diagram.
9-52
Am9519 Application Note
Chip Select (CS)
Interrupt Acknowledge (lACK)
The Chip Select input is an active low signal used to condition
the chip for read and write operations on the data bus;
Read/Write transfers will not take place unless the CS input is
low. Chip Select does not condition Interrupt Acknowledge
operations. Chip Select is usually derived by decoding an address output by the host processor; the negative-true polarity
matches outputs from typical decoder circuits.
The Interrupt Acknowledge input is an active low signal generated by the host processor and used to request interrupt response information. One response byte will be transferred by
the Am9519 for each lACK pulse received and up to four
bytes may be transferred during each interrupt acknowledge
sequence. The first lACK pulse following a GINT output also
initiates the internal selection of the highest priority unmasked
interrupt.
Read (RD)
Many processors provide interrupt acknowledge signals directly, including the BOB5, the BOBOA and the 2650. For
others, such as the ZBO and the 6BOO, it can be generated
quite easily with simple gating.
The Read input is an active low signal conditioned by Chip
Select that indicates information is to be transferred from the
Am9519 to the data bus. Read is usually a timed pulse issued
by the host processor.
Pause
Write (WR)
The Pause output is an active low signal used during lACK
cycles to indicate that the Am9519 has not completed the
data bus transfer operation presently underway. The lACK
pulse should be extended by the host processor at least until
the PAUSE output goes high. The width of active PAUSE
pulses is a function of several variables; it will be quite short
in some systems and longer in others. PAUSE is an open
drain output and requires an external pullup resistor to establish the high logic level. PAUSE signals should be wired together in multiple chip interrupt systems. _
The Write input is an active low signal conditioned by Chip
Select that indicates information is to be transferred from the
data bus to the Am9519. Write is usually a timed pulse issued
by the host processor.
Control/Data (C/O)
The Control/Data input acts as the port address line and is
used to select source and destination locations for read and
write transfers. Data transfers (C/O=O) are made to or from
preselected internal memory or register locations. Control
transfers (C/O = 1) write into the command register or read
from the status register.
Enable In (EI)
The Enable In input is an active high signal used to implement a "daisy-chain" expansion capability with other Am9519
chips. EI may also be used as a hardware disable/enable
input for the interrupt system. When EI is low, lACK inputs to
the chip are ignored. Internally, a relatively high impedance
resistor is connected between EI and VCC so that an unused
EI requires no external pullup resistor.
Interrupt Request (IREO)
The eight Interrupt Request inputs are used by external devices to indicate that service is desired. The Interrupt Request
Register associated with the inputs uses asynchronous
pulse-catching circuitry to latch any active requests that occur.
The input polarity may be programmed to capture either
positive-going or negative-going transitions. Reset selects the
active low option.
Enable Out (EO)
The Enable Out output is an active high signal used to implement a "daisy-chain" expansion capability with other
Am9519 chips. When the lACK input goes low, EO goes low
until EI goes high and the chip determines th1.t no unmasked
request is pending. EO is a two-state output with relatively
modest drive capability.
Response In Process (RIP)
The Response In Process signal is a bidirectional line designed to be used when two or more Am9519 circuits are
connected together. RIP is used to prevent new higher priority
interrupts from interferring with an Interrupt Acknowledge process that is underway. An Am9519 that is responding to a
selected interrupt will treat RIP as an output and will hold the
signal low until the acknowledge response is complete. An
Am9519 without a selected interrupt will treat RIP as an input
and will ignore lACK pulses as long as RIP is low. The RIP
lines from multiple Am9519 circuits may be wired directly
together. RIP is an open drain signal, and requires an external
pullup resistor to VCC in order to establish the logic high level.
Interface Considerations
All of the input and output signals for the Am9519 are
specified with logic levels identical to those of standard TTL
circuits. The worst-case input logic levels are 2.0V high and
O.BV low. Except for the open drain signals, the worst-case
output logic levels are 2AV high and OAV low. Thus, for TTL
interfacing, the normal worst-case noise immunity of at least
400mV is maintained. The logic level specifications take into
account all combinations of the three variables that affect the
logic level threshold: ambient temperature, supply voltage
and processing parameters. A change in any of these toward
nominal values will improve the actual operating margins.
Group Interrupt (GINT)
When active, the Group Interrupt output indicates that at least
one bit is set in the Interrupt Request Register (IRR) which is
not masked by the Interrupt Mask Register or the Interrupt
Service Register. GINT is used to notify the host processor
that service is desired. It may be programmed for either active
high or active low polarity in order to simplify the interface
with the host circuitry. Reset selects active low. When active
high is selected the output is a standard two-state buffer
configuration. When active low is selected the output is open
drain and requires an external pullup resistor to VCC in order
to establish the logic high level. The open drain configuration
is useful for wired-or connections in systems with more than
one Am9519.
The PAUSE and RIP outputs are open drain with no active
pullup transistors; their output high levels are established by
the external circuitry. The GINT output, when programmed for
active low polarity (GINT), is also an open drain output that
does not control its output high level.
All of the output buffers except EO and the open drain outputs
can source at least 200J.tA worst-case and can sink at least
3.2mA worst-case while maintaining TTL output logic levels.
EO normally only drives EI of another Am9519 chip and is
specified with less drive capability in order to improve the
9-53
0
Am9519 Application Note
priority resolution speed in multi-chip interrupt systems. The
open drain outputs all sink at least 3.2mA as the other outputs
do. Current sourcing for the open drain outputs is determined
by the external circuitry. Figure 5 summarizes the types of
outputs on the Am9519.
THREE-STATE
BIDIRECTIONAL
Within the limits of normal operation, the input protection circuitry is inactive and may be modeled as a lumped series RC
as shown in Figure 6. The functionally active input connection
during normal operation is the gate of an MOS transistor. Except for EI, no active sources or drains are connected to the
inputs so that neither transient nor steady-state currents are
impressed on the driving signals by the Am9519 other than
the ~harging or discharging of the input capacitance and the
accumulated leakage associated with the protection network
and the input circuit. Lumped input capacitances are usually
around 6pF and leakage currents are usually less than 1p.A
BIDIRECTIONAL
OPEN DRAIN
FUNCTIONALLY
ACTIVE
INTERNAL
CIRCUITRY
---I
MOS-021
~
.
Figure 6. Input Circuitry.
:2:0'
-=-
OPEN DRAIN
~SD
Signal
MOS-020
Output Description
Data Bus (DBO-DB7)
Bidirectional, Three-State
Response In Process (RIP)
Bidirectional, Open-drain
Pause
Open-drain
Group Interrupt (GINT)
Enable Out (EO)
Fanout from the driving circuitry into the Am9519 inputs will
generally be limited by transition time considerations rather
than DC current limitations when the loading is dominated by
MOS circuits like the Am9519. In an operating environment,
all inputs should be terminated so they do not float and accumulate stray static charges. Unused inputs should be tied
directly to Ground or to VCC, as appropriate. An input in use
will have some type of logic output driving it and termination
during operation will not be a problem. Where inputs are driven from logic external to the card containing this chip, however, on-board termination should be provided to protect the
chip when the board is unplugged and the input would otherwise float. A pull-up resistor or a simple inverter or gate will
suffice.
IREO Timing
The circuitry at the IREO inputs is quite straightforward and is
illustrated in Figure 7. Inverters 1 and 2 buffer the input and
shift the logic voltages to the somewhat wider swing used internally. The exclusive-or gate is used to select the sense of
the active transition edge that will set the IRR. Mode register
bit M4 is used directly for control of the exclusive-or gate. The
selected interface edge will always produce a negative going
transition at output 3. Inverters 4, 5, 6, 7 and 8 form a delay
chain. Nor gate 9 has three inputs and the IRR bit will be set
when all three inputs to 9 are low. As shown in the timing
diagram of Figure 8, the input to gate 9 from inverter 8 is
normally low when there is no active IREO signal at the interface. When a transition occurs, the output of gate 3 will go
low and only the signal from inverter 5 prevents the immediate setting of the IRR bit. As shown in the left portion of
the timing diagram, if the output from 3 has returned high before the output from 5 goes low, the IREO transition will be
ignored and the IRR bit will not be set. On the other hand, the
right side of the timing diagram shows that if the active IREO
input is present long enough, then the output from both 3 and
5 will become low at the same time, and output 9 will go high.
Output 8 is used to turn off Nor gate 9 after the IRR bit is set.
Two-State when active high
{ Open-Drain when active low
Two-state, low drive
Figure 5. Am9519 Output Buffer Summary and Circuitry.
Unprotected open gate inputs of high quality MOS transistors
exhibit very high resistances on the order of 1014 ohms. It is
easy in many circumstances for charge to enter the gate node
of such an input faster than it can be discharged and consequently for the gate voltage to rise high enough to break
down the oxides and destroy the transistor. All inputs to the
Am9519 include protection networks to help prevent damaging accumulations of static charge. The protection circuitry
is designed to slow the transitions of incoming current surges
and to provide low impedance discharge paths for voltages
beyond the normal operating levels. Please note, however,
that input energy levels can nonetheless be too high to be
successfully absorbed. Conventional design, storage, and
handling precautions should be observed so that the protection networks themselves are not overstressed.
9-54
Am9519 Application Note
MOS-022
Figure 7. Interrupt Request Logic.
In summary, the input circuitry for the IREO signals provides
these characteristics:
1.
2.
3.
4.
5.
I~J
Polarity for IREO inputs is controlled;
Narrow IREO pulses are ignored;
Wide IREO pulses are captured;
Transitions to active levels are captured just once;
New transitions are required to generate new interrupts.
v
v
CD
The IRR thus acts in a "pulse-catching" mode with respect to
the IREO inputs. Figure 9 shows the types of IREO
waveforms that will be recognized and latched by the IRR.
Note that a transition to a level may be used although only a
pulse is required; it is not necessary to maintain an IREO
input active level. Further, a continuously active level on IREO
will not cause a new interrupt each time IRR is cleared. There
must be a new active transition on IREO after IRR is cleared
in order to generate a new interrupt. An active level must go
inactive for a specific interval before its new active edge will
be recognized.
\'----I~I--------~\~_______
rtl
I
_0_ _ _
G0_9
__S_E_T_IR_R________________
~~
@IRR
,----
--------tlr------J
To minimize noise sensitivity, all active IREO pulses narrower
than a specific value will be ignored by the IRR. To maintain
the pulse-catching characteristics, ali active IREO pulses
wider than the specified data sheet minimum will be captured
by the IRR. The results for intermediate pulse widths will depend on characteristics of the particular part being used and
its operating conditions, especially temperature.
MOS-023
Figure 8. IREQ Internal Timing.
ACTIVE
EDGES
'--I
Power Supply
The Am9519 requires only a single +5V power supply. The
commercial temperature range parts have a voltage tolerance
of ±51)(; the military temperature range tolerance is ± 101)(.
Maximum supply currents are specified in the data sheet at
the high end of the voltage tolerance and the low end of the
temperature range. In addition, the current specifications take
into account the worst-case distribution of processing
parameters that may be encountered during the manufacturing life of the product. Typical supply current values, on the
other hand, are specified for a nominal supply of +5.0 volts,
nominal ambient temperature of 25°e, and nominal processing parameters. Supply current always decreases with.
increasing ambient temperature; thermal run-away is not a
problem.
IREO
ACTIVE
HIGH
U
_-----'Y\'---__
\)
IREO
ACTIVE
LOW
_----In~)
___
U
Although supply current will vary from part to part, a given unit
at a given operating temperature will exhibit a nearly constant
power drain. There is no functional operating region that will
cause more than a few percent change in the supply current.
Oecoupling of vee, then, is straightforward and will generally
be used simply to isolate the Am9519 from external vee
noise.
IRR
_________________
.J!
(INTERNAL)
MOS-024
Figure 9. IREQ Waveforms.
9-55
Am9519 Application Note
Interrupt Service Register (ISR)
OPERATING DESCRIPTION
Reset
The Am9519 does not include an external hardware reset input. The reset function is accomplished either by software
command or automatically during power-up. The reset may be
initiated by the host processor at any time simply by writing all
zeros into the command port. Power-up reset circuitry is internally triggered by the rising VCC voltage when a predetermined threshold is reached, generating a brief internal reset
pulse.
The ISR is eight bits long and is used to store the acknowledge status of individual interrupts. When an lACK pulse arrives, the Am9519 selects the highest priority request that is
pending, then clears the associated IRR bit and sets the associated ISR bit. When the ISR bit is programmed for automatic clearing, it is reset by the internal hardware before the
end of the acknowledge sequence. When the ISR bit is not
programmed for automatic clearing, it must be reset by command from the host processor.
Internally, the Am9519 uses the ISR to erect a "maskfng
fence". When an ISR bit is set and fixed priority mode is
selected, only requests of higher priority will cause a new
GINT output. Thus, requests from lower priority interrupts (and
from new requests associated with the set ISR bit) will be
fenced out and ignored until the ISR bit is cleared. In the
rotating priority mode, all requests are fenced by an ISR bit
that is set, and no new GINT outputs will be generated until
the ISR is cleared. When auto clear is specified, no fence is
erected since the ISR bit is cleared.
The response memory and byte count· registers are not affected by resets. Their content after power-up are unpredictable and if they are to be used, they must first be initialized by the host processor. A software reset does not disturb previous response memory and byte count contents.
The Interrupt Mask register is set to all ones by a reset, thus
disabling recognition of interrupts by the chip. The Status register continues to reflect the internal condition of the chip and
is not otherwise directly affected by a reset. All other registers
are cleared to all zeros by a reset. The polarities of the Mode
register control bits are assigned to provide a reasonable
operating option environment when cleared by a reset.
If an unmasked interrupt arrives from a device of higher priority than the current ISR, GINT will go true and the host processor will be interrupted if its interrupt input is enabled.
When the new interrupt is acknowledged, the associated
higher priority ISR bit is set and the fence moves up to the
new level. When the new ISR bit is cleared, the fence will
then fall back to the previous ISR level.
Register Description
The Am9519 uses several control and operation registers plus
the response memory to perform and manage its many functions. Figure 10 lists these elements and summarizes their
size and number.
Description
Interrupt Request Register
Interrupt Service Register
Interrupt Mask Register
Auto Clear Register
Status Register
Mode Register
Command Register
Byte Count
Response Memory
The ISR may be read onto the data bus by preselecting it in
Mode register bits M5 and M6, followed by a read operation
at the data port.
Bit
Abbreviation Size Quantity
IRR
ISR
IMR
ACR
8
8
8
8
8
8
8
2
32
Interrupt Mask Register (IMR)
The IMR is eight bits long and is used to enable/disable the
processing of individual interrupts. Only unmasked IRR bits
can cause a Group Interrupt to be generated. The IMR does
not otherwise affect the operation of the IRR. An IRR bit that
is set while masked will cause a GINT when its IMR bit is
cleared.
1
1
1
1
1
1
1
8
8
All eight IMR bits may be set, cleared, read or loaded in parallel by the host processor. In addition, individual IMR bits may
be set or cleared by command. This allows a control routine
to directly enable and disable an individual interrupt without
disturbing the other mask bits and without knowledge of their
state or the system context.
Figure 10. Am9519 Register and Memory Summary.
The IMR polarity is active high for masking; a zero enables
the interrupt and a one disables it. The power-on reset and
the software reset cause all IMR bits to be set, thus disabling
all requests.
Interrupt Request Register (IRR)
The IRR is eight bits long and is used to recognize and store
active transitions on the eight Interrupt Request input lines. A
bit in the IRR is set whenever the corresponding IREO input
makes an inactive-to-active transition and meets the minimum
active pulse width requirements. IRR bits may also be set by
the host processor under program control using two types of
commands. This capability allows software initiated interrupts,
and is a significant tool for system testing and for sophisticated software designs.
Auto Clear Register (ACR)
The ACR is eight bits long and specifies the automatic clearing option for each of the ISR bits. When an auto clear bit is
set, the corresponding ISR bit that has been set in an lACK
cycle is cleared by the internal hardware before the end of the
lACK sequence. When an auto clear bit is not set, the corresponding ISR bit that has been set in an lACK cycle is
cleared by command from the host processor.
All IRR bits are cleared by a reset. Individual IRR bits are
cleared automatically when their interrupts are acknowledged
by the host processor. Four types of commands, in addition to
reset, allow the host program to clear IRR bits.
The auto clear option, when selected, provides two concomitant functional effects. First, it eliminates the need for the associated interrupt service routine to issue a command to clear
the ISR bit. Secondly, it eliminates the masking fence that
would otherwise have been erected, allowing lower priority interrupts to cause a new GINT output.
The IRR may be read onto the data bus by preselecting it in
Mode register bits M5. and M6, followed by a read operation
at the data port.
9-56
Am9519 Application Note
The ACR is loaded in parallel from the data bus by issuing
the ACR load preselect command followed by a write into the
data port. The ACR may be read onto the data bus by preselecting it in Mode register bits M5 and M6, followed by a
read operation at the data port.
Status bits S2, S1 and SO form a three bit field indicating the
encoded binary number of the highest priority unmasked bit
that is set in the IRR. This field should be considered invalid
except when bit S7 of the Status register is low, indicating
that at least one unmasked interrupt request is present. The
binary coding of the field corresponds to the zero through
seven numbering of the IREO inputs. When more than one
unmasked IRR bit is set, the S2, S1, SO field will indicate the
one unfenced request that is the highest priority as determined by the priority mode being used. Thus, the number of
the dominant interrupt after all masking, fencing and priority
resolution, is encoded into the Status register. This field is quite
useful in the polled mode since it can act as a psuedo-vector for
the host processor software.
Status Register
The Status Register is eight bits long and contains information
describing the internal state of the Am9519 chip. The Status
register is read directly by executing a read operation at the
control port. Figure 11 shows the Status bit assignments.
187 186 1S51 s41 s31 S21 81 1so 1
L=:
Command Register
The Command Register is eight bits long and is used to store
the most recently entered command. It is loaded directly from
the data bus by executing a write operation at the control port.
Depending on the specific command opcode that is entered,
an immediate internal activity may be initiated or the part may
be preconditioned for subsequent data bus transfers. The
"Command Description" section of this note explains each
command operation. The commands are summarized in
Figure 17.
Binary vector indicating the
number of the highest priority
unmasked bit that is set in I RR.
Valid only when S7 = O.
Master Mask Bit
Chip disarmed
1 Chip armed
o
Interrupt Mode
Interrupt
1 Polled
o
Mode Register
Priority Mode
o Fixed
1 Rotating
The Mode register is eight bits long and controls the operating
modes and options of the Am9519. Figure 12 shows the bit
assignments for the Mode register. No single command or interface operation will load all bits of the Mode register in parallel. The five low order bits (MO through M4) are loaded in
parallel directly from the command register. Mode bits M5,
M6, and M7 are controlled by separate commands. The Mode
register cannot be read out on the data bus. The data in
Mode bits MO, M2, and M7 are available as part of the Status
register. The Mode register is cleared by a software reset or a
power-up reset. The "Operating Options" section of this note
describes the detailed functions associated with each Mode
bit.
Enable Input
o Chip disabled
1 Chip enabled
Group Interrupt
1 No unmasked
IRR bit set
o At least one unmasked
IRR bit set
MOS·025
Figure 11. Status Register Bit Assignments.
The high order status bit, S7, reflects the information state of
the Group Interrupt signal. Note that the polarity definition of
S7 is independent of the defined polarity of GINT (Mode bit
M3). Bit S7 remains valid when GINT is disabled by the polled
mode option, thus permitting the host processor to check for
"interrupts" by reading the Status register.
Priority Mode
Fixed
1 Rotating
o
Status bit S6 reflects the state of the Enable In input signal
and is used to indicate, in a multiple chip interrupt structure,
which chips in the chain are disabled. When S6 is high, the
chip can generate a GINT output and operation of its EO signal proceeds. When S6 is low, no GINT will be generated and
EO will be forced low.
Vector Selection
o Individual vector
1 Common vector
'---_ _ _ Interrupt Mode
o Interrupt
1 Polled
' - - - - - - - - GINT Polarity
o Active low
1 Active high
Status bit S5 reflects the state of the Priority Mode option, as
specified by bit MO of the Mode register. When S5 is high,
rotating priority has been selected. When S5 is low, fixed
priority has been selected.
L -_ _ _ _ _ _
IREO Polarity
o Active low
1 Active high
Status bit S4 reflects the state of the Interrupt Mode option,
as specified by bit M2 of the Mode register. When S4 is high,
the polled mode has been selected and GINT disabled. When
S4 is low, the interrupt mode has been selected.
L -_ _ _ _ _ _ _ _ _
Register Preselection
00
01
10
11
Status bit S3 reflects the state of the Master Mask bit as
specified by bit M7 of the Mode register. When S3 is low, the
chip has been disarmed and IRR bits that are set will not
generate GINT outputs. When S3 is high, the chip has been
armed and interrupts can occur.
L..-_ _ _ _ _ _ _ _ _ _ _
Interrupt service register
Interrupt mask register
Interrupt request register
Auto clear register
Master Mask Bit
o Chip disarmed
MOS·026
1 Chip armed
Figure 12. Mode Register Bit Assignments.
9-57
Am9519 Application Note
Information Transfers
1. the operating temperature,
2. the actual internal logic delays,
3. the number of Am9519 chips cascaded together,
4. the priority level of the interrupt being acknowledged,
5. the Mode register operating options,
6. the byte position within the response sequence.
Figure 13 summarizes the control signal configurations for all
information transfers on the Am9519 data bus. The interface
control logic assumes the following conventions:
1. RD and WR are never active at the same time.
2. RD, WR and C/O are ignored unless CS is low.
Control Input
CS C/O RO WR lACK
The worst-case lACK pulse widths must be long enough to
accomodate the accumulated delays that can occur in large
interrupt systems operating in worst-case situations. Yet small
systems operating under typical conditions will require only
relatively narrow lACK pulses. The PAUSE output from the
Am9519 is designed to provide interactive feedback to the
hast processor so that the lACK pulse width may be adaptively adjusted to meet the requirements of the actual interrupt
being processed. PAUSE will go low fairly quickly following
the falling edge of lACK, and will return high when lACK is no
longer required.
Data Bus
Operation
0
0
0
1
1
Transfer contents of data register specified by Mode bits MS, M6 to data bus.
0
0
1
0
1
Transfer contents of data bus to data register specified by Command register.
0
1
0
1
1
Transfer contents of Status register to
data bus.
0
1
1
0
1
Transfer contents of data bus to Command register.
1
X
X
X
0
Transfer contents of selected response
memory location to data bus.
1
X
X
X
1
During the first lACK of a complete acknowledge sequence,
the PAUSE output remains low until the highest priority interrupt has been selected and the RIP output goes low. On subsequent lACK pulses for additional responses bytes associated with the same interrupt (RIP still low), PAUSE will
remain high. The Am9519 expects the first lACK input to remain low at least until the PAUSE output goes high. Subsequent lACK inputs should meet the specified input pulse
width requirements as called out in the data sheet.
No information transferred; data bus
outputs off.
Figure 13. Summary of Data Bus Transfers.
When lACK is low, internal logic disables the CS input. This
prevents signals on the address bus from inadvertently selecting the chip.
°It will normally be convenient for the PAUSE Signal to provide
a "not ready" indication to the host processor which would
then stall the Interrupt Acknowledge operation until PAUSE
goes high. In 8080N9080A microprocessor systems, PAUSE
can be used directly in the CPU Ready logic and many other
processor systems have similar coordination schemes.
The host processor may read the Status register directly by
simply performing a read operation with the control port
selected. When a read is executed at the data port, the information transferred will be the contents of the ISR, IMR, IRR
or ACR, depending on the state of Mode register'bits M5 and
M6.
Operating Options
The Mode register bits are used to establish the operating
modes and conditions for the many functional features of the
Am9519. The Mode register allows the host processor to personalize the interrupt system for the application at hand.
Priority Selection
The host processor may write directly into the command register by simply performing a write operation with the control part
selected. When a write is executed into the data part, the contents of the data bus will be transferred to the ACR, IMR or
response memory, depending an which command preceded
the data write. Note that Mode bits M5 and M6 do nat preselect the location for data write operations; only a command
can do so.
Bit MO in the Mode register specifies the priority operating
mode for the Am9519. When MO=O, fixed priority is selected
and the eight IREO inputs are assigned a priority based on
their physical location at the chip interface. IREOO has the
highest priority and IREO? has the lowest. See Figure 14.
HIGHEST
PRIORITY
When the response memory preselect command is issued, it
should be followed by an appropriate number of data write
operations to load 1, 2, 3, or 4 bytes of response information.
If more than four bytes are written, the response memory addressing will "wrap around" and overwrite the information already entered. Response bytes are output by the Am9519
during lACK operations in the same order they were entered.
Entry of response· information into each new level must be
preceded by a new response memory preselect command.
Interrupt Acknowledge operations are initiated by the host
processor and occur following recognition of a GINT signal
from the Am9S19. When an lACK signal arrives, the interrupt
system selects the highest priority unmasked pending interrupt request and then outputs a response byte associated
with the selected interrupt. The selection process and the access of the response byte will take a variable amount of time
that depends on several parameters, including:
LOWEST
PRIORITY
Figure 14. Fixed Priority Mode.
9-58
MOS-027
Am9519 Application Note
Priority is not resolved until the host processor initiates the interrupt acknowledge sequence. Thus, for example, an IRE05
input may cause a GINT output to the host, but if an input ~n
IRE02 arrives before the falling edge of lACK, then it IS
IRE02 that will be selected and serviced. Notice that inherent
in the fixed priority structure is the possibility that IRE05
might never be selected and serviced as long as there are
higher priority interrupts pending. IRE02 could end up being
serviced many times before IRE05 is acknowledged. In many
systems this is an appropriate method for handling the interrupting devices. Where circumstances permit, the masking
capability of the Am9519 can be used by the host processor
to modify the effective priority structure, perhaps by masking
out recently serviced high priority devices, thus allowing lower
priority inputs to be recognized.
Vectoring
Bit M1 of the Mode register specifies the vectoring option.
When M1 =0 the individual vector mode is selected and each
interrupt is associated with its own unique four-byte location in
the response memory. When M1 = 1, on the other hand, the
common vector mode is selected and all response information
is supplied from the location associated with IREOO, no matter which request is being acknowledged. This operating option will be useful in situations where several similar devices
share a common service routine and direct individual device
identification is not important. This may be true simply because of the nature of the peripheral/system interaction, or it
may be a transient system condition that only uses the common vector option temporarily, perhaps to save the overhead
involved in filling the response memory twice.
Alternatively, where the eight interrupts have similar priority
and service bandwidth requirements, the rotating priority
mode may be selected (Mode register bit MO= 1). As shown in
Figure .15 the relative priorities remain the same as in the
fixed mode; that is, IRE02 is higher than IRE03 which is
higher than IRE04, etc. However, in rotating priority mode,
the lowest priority position in the circular chain is assigned by
the hardware to the most recently serviced interrupt.
Polled Mode
Bit 2 of the Mode register allows the system to disable the
GINT output. When M2=0 the interrupt mode is selected with
the GINT output enabled. This might be considered the "normal" interrupt mode and makes full use of the interrupt control
and management capabilities of the Am9519. When M2= 1
the polled mode is selected which prevents the GINT output
from going true by forcing it to its inactive state. In this condition, since no interrupts are supplied to the host processor,
there will usually not be any lACK pulses returned to the
Am9519. Consequently, ISR bits are not set, fences are not
erected and IRR bits will n6t be automatically cleared. In the
polled mode the host processor may read the Status register
to determine if a request is pending and which request has
the highest priority. IRR bits may be cleared by the host
software. When the polled option is selected, the EI input is
connected directly to the EO output thus functionally removing
the polled chip from the external priority hierarchy.
(NEW
HIGHEST
PRIORITy)
Effectively, the polled mode of operation bypasses the hardware
interrupt, inter-chip priority resolution, vectoring and fenCing functions ofthe Am9519. What remains is the request latching, masking and intra-chip priority resolution.
(LAST
INTERRUPT
SERVICED)
GINT Polarity
Bit 3 of the Mode register specifies the sense of the GINT
output. When M3=O, Group Interrupt is selected as active low
(GINT) and becomes an .open drain output. This allows simple
wired-or connections to other similar Am9519 outputs as well
as to other sources of interrupts, and matches the polarity required by many processors. When M3= 1, Group Interrupt is
selected as active high (GINT) and becomes a two-state
push-pull output, simplifying the interface to processors with
active high interrupt inputs.
M05·028
Figure 15. Rotating Priority Mode.
The example illustrated in Figure 15 assumes that IRE05 has
just finished being serviced and has therefore been assigned
the lowest priority. Thus, IRE06 occupies the new highest
priority position, IREO? next-to-highest, etc. If two new interrupts then arrive at level 1 and level 4, IRE01 will be selected
and serviced, and will become the lowest priority. IRE04 will
then be acknowledged unless an active input on IRE02 or
IRE03 has arrived in the meantime.
IREQ Polarity
Bit 4 of the Mode register specifies the sense of the IREO inputs. When M4=0 the Interrupt Request signals are selected
as active low (IREO) and a negative-going transition is required to set the IRR. When M4= 1 the Interrupt Request signals are selected as active high (I REO) and a positive-going
transition is required to set the IRR. This sense option helps
simplify the interface to interrupting devices.
This rotating priority scheme prevents any request from
dominating the system. It assures that an input will not have
to wait for more than seven other service cycles before being
acknowledged. Rotation occurs when the ISR bit of the presently selected interrupt is cleared.
In the rotating priority mode, inputs other than the one currently being serviced are fenced out and will not cause interrupts until the ISR bit is cleared. Thus, only one bit at a time
will be set in the ISA. Care should be used when selecting
the rotating mode to keep from doing so at a time when more
than one ISR is set.
Register Preselection
Bits 5 and 6 of the Mode register specify the internal data
register that will be output by the Am9519 on any read
operation at the data port (CS=O, RD=O, C/D=O). These bits
do not affect destinations for write operations. The four
9-59
m
•
Am9519 Application Note
2. The requests are captured and latched in the IRR asynchronously. The latching action of the IRR cannot be disabled and active requests will always be stored unless a
previous request at the same IRR bit has not been
cleared.
3. If the active IRR bit is masked by the corresponding bit in
the IMR, no further action takes place. When the IRR bit is
not masked, an active Group Interrupt output will be generated if the Am9519 is not in its polled mode.
4. 'The GINT output from the Am9519 is used by the host
processor as an interrupt input. When GINT is recognized
by the host, it normally will complete the execution of its
current instruction and will then execute some form of interrupt acknowledge sequence instead of the next program
instruction. As part of the acknowledge cycle, the processor usually automatically disables its interrupt input. The
Am9519 expects to receive one or more lACK signals from
the processor during the acknowledge sequence.
5. When lACK is received, the Am951,9 brings its PAUSE
output low and begins selection of the highest priority unmasked active IRR bit. All interrupts that have become active before the falling edge of lACK are considered. When
selection is complete, the RIP output is pulled low by the
Am9519 and the contents of the first byte in the response
memory associated with the selected request is accessed.
PAUSE stays low until RIP goes low. RIP stays low until
the last byte of the response has been transferred.
6. After PAUSE goes high, the host processor accepts the
response byte on the data bus and brings the lACK line
high. If another byte of response is required, another lACK
pulse is output and is used by the Am9519 to access the
next byte.
7. In parallel with the transfer of the first response byte, the
Am9519 automatically clears the selected IRR bit and automatically sets the selected ISR bit. If the auto clear function is not in force for the selected interrupt, the ISR bit will
cause a masking fence to be erected and GINT will be
disabled until a higher priority interrupt arrives or until the
ISR bit is cleared. The interrupt service routine will usually
clear the ISR bit, often near the end of the routine.
8. If a higher priority request arrives while the current request
is being serviced, and if the fixed priority mode is in effect,
then GINT will be output again by the Am9519. The GINT
signal will be recognized by the host processor only if the
host has enabled its interrupt input. If this new request is
acknowledged, the Am9519 will clear the corresponding
IRR bit and set the corresponding ISR bit.
9. When the host processor has completed all interrupt service activity to satisfy the interrupting devices, it will normally clear the remaining ISR bit, if any, enable its internal
interrupt system, if it has not already done so, and then return to the main program.
registers available for reading are the IRR, ISR, IMR and
ACR. Preselect coding for each register is shown in Figure
12. The preselection remains in effect for all data read
transfers until the contents of M5 and M6 are changed.
The ability to examine these important operating registers,
combined with the information available in the Status register,
provides significant insight into the internal conditions of the
Am9519. This allows the host processor not orily enhanced
dynamic operating flexibility, but also access to important
diagnostic/testing/debugging information.
Master Mask
Bit 7 of the Mode register specifies the armed status of the
Am9519 by way of the Master Mask control bit. When M7 = 0
the chip is disarmed just as if all eight bits in the IMR had
been set. That is, IREO inputs will be accepted and latched
but will not cause GINT outputs to the host. In addition, the
EO output is brought low, disabling any lower priority chips
that may be attached. When M7 = 1, the chip is armed and
any active unmasked interrupt inputs will be able to cause
GINT outputs to the host processor.
The Master Mask capability permits the host system to disarm
a chip and prevent processing of the interrupts without disturbing the contents of the IMR. Thus when the chip is rearmed, the old IMR conditions remain in effect and need not
be reloaded. Note that a single command to the Master Mask
bit of the highest priority interrupt chip is able to shut down
the complete interrupt system, no matter how large.
Mode Reset
When a power-up or software reset occurs, the Mode register
is cleared to all zeros. This means that after reset the following Mode register operating options will be in effect:
Fixed priority
Individual vectoring
Interrupt (non-polled) operation
GINT active low sense
IREO active low sense
ISR preselected for reading
Chip disarmed by Master Mask
Operating Sequence
The management of interrupts by the Am9519 is illustrated
below with a description of a fairly typical sequence of events.
The Am9519 has already been initialized and enabled and is
ready to run. The host processor has enabled its internal interrupt structure.
1. One (or more) of the IREO inputs becomes active indicating that service is desired.
9-60
Am9519 Application Note
COMMAND DESCRIPTIONS
SET IMR
The Am9519 command set allows the host processor to customize and alter the interrupt operating modes and features
for particular applications, to initialize and update the response locations, and to manipulate the internal controlling bit
sets during interrupt servicing. Commands are entered from
the data bus directly into the Command register by writing into
the Am9519 control port (CS=O, WR=O, C/D=1). All the
available commands are described below and are summarized in Figure 17. In the binary coding of the commands,
"X" indicates a do-not-care bit position.
Coding:
Description: All bits in the IMR are set to ones. All IRR bits
will therefore be masked and unable to generate an active
GINT. If GINT had been active, it will go inactive after the
command is entered.
SET SINGLE IMR BIT
Coding:
RESET
Coding:
Description: A single bit in the IMR is set. Other bits are not
changed. If the corresponding bit in the IRR was active and
generating a GINT output, GINT will become inactive after the
command is entered. The IMR bit set is specified by the 82,
81, 80 field as shown in Figure 16.
Description: The Reset command allows the host processor
to establish a known internal condition. The response memory
and byte count registers are not affected by the software reset. The IMR is set to all ones. The ISR, IRR, ACR and Mode
registers are cleared to all zeros.
CLEARIRR
CLEAR IRR AND IMR
Coding:
Coding:
Description: All bits in the IRR are cleared to zeros. GINT will
become inactive. New transitions on the IREO inputs will be
necessary to cause an interrupt.
Description: All bits in the IMR and all bits in the IRR are
cleared at the same time. Thus all interrupts are enabled and
the previous history of all IREO transitions is forgotten. If
GINT was active when the command was entered, it will go
inactive.
CLEAR SINGLE IRR BIT
CLEAR SINGLE IMR AND IRR BIT
Coding:
Coding:
Description: A single bit in the IRR is cleared to zero. It will
not cause an active GINT until it is set. The IRR bit cleared is
specified by the 82, 81, 80 field as shown in Figure 16.
Description: The same single bit position is cleared in both
the IMR and the IRA. Other bits are not changed. If the
specified IRR bit was generating an active interrupt output,
GINT may go inactive upon entry of the command. The bit
position cleared is specified by the 82, 81, 80 field as shown
in Figure 16.
SETIRR
Coding:
CLEAR IMR
Coding:
Description: All bits in the IRR are set to ones. Any that are
unmasked will be able to cause an active GINT output. This
command allows the host CPU to initiate eight interrupts in
parallel.
Description: All bits in the IMR are cleared to zeros. All IRR
bits will therefore be unmasked and any IRR bits that had
been set will be able to cause an active GINT output after the
command is entered.
SET SINGLE IRR BIT
r---.---~--~--.---~---r---r---'
Coding:
CLEAR SINGLE IMR BIT
C6
~--~--~--+---+---1----r---r--~
Coding:
Description: A single bit in the IRR is set to a one. If it is unmasked it will be able to generate an active GINT. This command allows the host processor to simulate with software the
arrival of a hardware interrupt request. It also gives the
software access to the hardware priority resolution, masking
and control features of the Am9519. The bit set is specified by
the 82, 81, 80 field as shown in Figure 16.
Description: A single bit in the IMR is cleared. Other bits are
not changed. If the corresponding bit in the IRR was set, it will
be unmasked and will be able to cause an active GINT after
entry of the command. The IMR bit cleared is specified by the
82, 81, 80 field as shown in Figure 16.
9-61
r:tII
~
Am9519 Application Note
CLEAR HIGHEST PRIORITY ISR BIT
Thus, this command may be considered as three distinct
commands, depending on the coding of N1 and NO:
Coding:
1. Load M5, M6 only
2. Load M5, M6 and set M7
3. Load M5, M6 and clear M7
Description: A single bit in the ISR is cleared to zero. If only
one bit was set, that is the one cleared. If more than one bit
was set, this command clears the one with the highest priority. This command is useful in software contexts where the
service routine does not know which device is being serviced.
It should be used with caution since the highest priority ISR
bit may not really be the bit intended. When using the auto
clear option on some interrupts and/or when a subroutine
nesting hierarchy is not priority driven, the highest priority ISR
bit may not correspond to the one being serviced.
The Command Summary in Figure 17 lists all three versions.
PRESELECT IMR FOR WRITING
Coding:
Description: The IMR is targeted to be loaded from the data
bus when the next write operation occurs at the data port. All
subsequent data write operations will also load the IMR until a
different command is entered. Read operations may be successfully inserted between the entry of this command and the
subsequent writing of data into the IMR. The Mode register is
not affected by this command.
CLEARISR
Coding:
PRESELECT ACR FOR WRITING
Description: All bits in the ISR are cleared to zeros. Mask
fencing is eliminated.
Coding:
CLEAR SINGLE ISR BIT
Description: The ACR is targeted to be loaded from the data
bus when the next write operation occurs at the data port. All
subsequent data write operations will also load the ACR until
a different command is entered. Read operations may be
successfully inserted between the entry of this command and
the subsequent writing of data into the ACR. The Mode register is not affected by this command.
Coding:
Description: A single bit in the ISR is cleared to zero. If the
bit was already cleared, no effective operation takes place.
The bit cleared is specified by the B2, B1, BO field as shown
in Figure 16. This will be the most useful command for service
routines to use in managing the ISR without the help of the
auto-clear option.
PRESELECT RESPONSE MEMORY FOR WRITING
Coding:
LOAD MODE BITS MO THROUGH M4
Description: One level in the response memory is targeted for
loading from the data bus by subsequent data write operations. The byte count register for that level is loaded from the
BY1, BYO field in the command. The L2, L 1, LO field specifies
which of the eight response levels is being selected. This
command should be followed by one to four data write operations to load response bytes. Field coding:
Coding:
Description: The five low order bits of the Command register
are transferred into the five low order bits of the Mode register. This command controls all of the Mode options except the
master mask and the register preselection.
Description: The M6, M5 field in the command is loaded into
the M6, M5 locations in the Mode register; This field controls
the register preselection bits in the Mode register. The N1, NO
field in the command controls Mode bit M7 (Master Mask) and
is decoded as follows:
N1
o
o
1
.!::!..Q.
0
1
0
Count
L2
L1
LO
Level
0
1
0
0
0
0
1
2
0
0
1
1
1
0
3
0
1
0
2
1
1
4
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
BY1
BYO
0
0
The byte count value does not control the number of bytes
entered into the response memory. It does control the number
of bytes read from the memory by lACK pulses. Response
bytes are output by the Am9519 in the same order they were
entered.
No change to M7
Set M7
Clear M7
(Illegal)
9-62
Am9519 Application Note
B2
B1
BO
Bit
Specified
0
0
0
0
0
0
1
1
0
1
0
0
1
1
2
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
Figure 16. Coding of B2, B1, BO Field of Commands.
COMMAND CODE
7
6
5
4
3
2
1
0
COMMAND
DESCRIPTION
0
0
0
0
0
0
0
0
1
0
0
X
0
X
0
X
Reset
Clear all IRR and all IMR bits
0
0
0
1
1
B2
Bl
BO
Clear IRR and IMR ,bit specified by 82, 81, 80
0
0
1
0
0
X
X
X
Clear all IMR bits
0
0
1
0
1
B2
81
BO
Clear IMR bit specified by 82, Bl, BO
Set all IMR bits
0
0
1
1
0
X
X
X
0
0
1
1
1
82
Bl
80
Set IMR bit specified by B2, 81, 80
0
1
0
0
0
X
X
X
Clear all IRR bits
0
1
0
0
1
82
Bl
80
Clear IRR bit specified by B2, 81, BO
0
1
0
1
0
X
X
X
Set all IRR bits
0
1
0
1
1
82
Bl
80
Set IRR bit specified by B2, 81, 80
0
1
1
0
X
X
X
X
Clear highest priority ISR bit
0
1
1
1
0
X
X
X
Clear all ISR bits
0
1
1
1
1
B2
81
BO
Clear ISR bit specified by 82, 81, 80
1
0
0
M4
M3
M2
Ml
MO
Load Mode register bits 0-4 with specified pattern
1
0
1
0
M6
M5
0
0
Load Mode register bits 5, 6 with specified pattern
1
0
1
0
M6
M5
0
1
Load Mode register bits 5, 6 and set Mode bit 7
1
0
1
0
M6
M5
1
0
Load Mode register bits 5, 6 and clear Mode bit 7
1
0
1
1
X
X
X
X
1
1
0
0
X
X
X
X
1
1
1
BYl
8YO
L2
L1
LO
Preselect IMR for subsequent loading from data
bus
Preselect ACR for subsequent
loading from data bus
Load BY1, BYO into byte count register and
preselect response memory'level specified by L2,
L 1, LO for subsequent loading from data bus
Figure 17. Am9519 Command Summary.
9-63
Am9519 Application Note
SYSTEM INTERFACE
After the fall of lACK, all chips wait until a brief internal delay
elapses and then examine EI. If EI is low, internal activity is
suspended until EI goes high. If EI is high, then the internal
circuitry is checked to see if an unmasked request is pending.
If so, RIP is brought low, PAUSE is brought high, EO is kept
low, and the first response byte is output on the data bus. In
this example, there is no request in chip A and therefore the
EO(A) line is brought high. This then allows chip B to see if it
has an unmasked request waiting for service. If not, EO(B)
goes high also and, with no interrupts at C, EO(C) goes high,
driving EI(D) high. Since chip 0 finds a waiting request, it
does not bring EO(D) high but it does bring RIP low. When
RIP goes low it allows all the PAUSE outputs to switch high
which permits the termination of the lACK pulse.
Expansion
Several Am9519 chips may be cascaded to expand the
number of interrupts than can be handled by the system. A
two-chip configuration is shown connected to an 8080N9080A
microprocessor in Figure 18. In general, expansion past a
single Am9519 will require simply an added Chip Select signal
for each extra chip, and perhaps an inverter for the GINT signal if the processor interrupt input is active-high. The GINT,
PAUSE, and RIP signals are all designed to be wire-OR'ed in
expanded systems.
Priority management in expanded systems is controlled by the
Enable In, Enable Out and Response In Process signals. Figure 19 shows the basic interconnections for an example interrupt system that can accept up to 40 interrupts, using five
Am9519 chips. Notice that iACK is wired in parallel to all five
circuits, and that the GINT, RIP, and PAUSE lines are respectively tied together. The three pullup resistors are used to establish the high logic levels for the open-drain outputs. Enable
In of the first chip (A) is allowed to float, or may be tied high.
Each Enable Out signal is connected to the next lower level
Enable In input. Each chip accepts eight IREO inputs; for purposes of this example it is assumed that an active interrupt
arrives at chip 0 in the chain.
It can be seen, then, that the PAUSE output will automatically
adjust the position of its rising edge to accommodate the
exact functional and operational conditions that occur for each
particular lACK cycle. For larger systems, like that in Figure
19, operating at high temperatures with slow versions of the
Am9519 and servici~g low priority interrupts, the processor
delay caused by PAUSE may be quite long and a few processor wait cycles may be required to extend the lACK pulse.
On the other hand, when a system like Figure 18 is running at
typical room temperatures with typical parts and the interrupt
is a high priority one, the PAUSE output width will be quite
narrow and no wait cycles will be necessary.
The RIP output serves two basic functions within the interrupt
system. First, its falling edge informs the other connected
chips that an interrupt request has been selected and PAUSE
may, therefore, be released. Secondly, as long as RIP is low,
only the single chip that is pulling RIP down is allowed to respond to lACK inputs. RIP stays low until all response bytes
for the selected interrupt have been transferred.
Figure 20 shows the timing relationships for the configuration
of Figure 19. When the IREO arrives, a GINT output is generated by chip 0 and is used to interrupt the host processor.
When the host returns an lACK pulse, all the EO lines are
brought low in parallel. PAUSE also goes low, and is used to
extend the lACK pulse.
t\.
AO-A1S
¥
f
ADDRESS BUS
v
lJ:~
B
G
HlDA
Am8080A/
Am9080A
XTAl
rD~
-
¢2_¢2
RESIN
RDY
RESET
SYNC
RDYIN
,--STSTB
Am8224
--
Wii
DBIN
YJ
1
.---~
¢1_¢1
~
~Y4
'---
INT
TANK
~Y2P-
o----c
-
HLDA
PP-
INTA
Wii
lOW
DBIN
iOR
RDY
RESET
SYNC
~
Am8228
STSTB
'----
VtN-
+
L
eo
WR
CS
lACK
C/D
>---b applies between L1 and L2 . b1 applies betWeen L1 and 0.500"
beyond reference plane.
C-3
PACKAGE OUTLINES (Cont.)
MOLDED DUAL IN-LINE PACKAGES
P-8-1
P-10-1
tl~D
..
A
T~W"-----r~
t
I
l
L
L
PLANE
La""ANG
I
I
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f
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--l ~
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c
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b
IIL=
-c
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P-16-1
P-14-1
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f--
b
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P-18-1
P-20-1
P-22-1
C-4
A
jSEATING
-PLANE
f-E2-\
PACKAGE OUTLINES (Cont.)
MOLDED DUAL IN-LINE PACKAGES (Cont.)
P-28-1
P-24-1
P-40-1
Ie::::::::::::::::::1
sl-l~
AMD Pkg.
P-8-1
P-10-1
P-14-1
P-16-1
P-18-1
P-20-1
Parameters
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
A
.150
.200
.150·
.200
.150
.200
.150
.200
.150
.200
b
.015
.022
.015
.020
.015
.020
.015
.020
.015
.020
.015
.020
.055
.065
.055
.065
.055
.065
.055
.065
.055
.065
.055
.065
.009
.011
.009
.011
.009
.011
.009
.011
.009
.011
.009
.011
o
.375
.395
.505
.550
.745
.775
.745
.775
.895
.925
1.010
E
.240
.260
.240
.260
.240
.260
.240
.260
.240
.260
.310
.385
.310
.385
.310
.385
.310
.385
.310
.385
.090
.110
.090
.110
.090
.110
.090
.110
.090
l
.125
.150
.125
.150
.125
.150
.125
.150
a
.015
.060
.015
.060
.015
.060
.015
.030
.040
.070
.040
.065
.010
.Q1
o·
P-22-1
P-24-1
P-28-1
P-40-1
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
.200
.150
.200
.170
.215
.150
.200
.150
.200
.015
.020
.015
.020
.015
.020
.015
.020
.055
.065
.055
.065
.055
.065
.055
.065
.009
.011
.009
.011
.009
.011
.009
.011
1.050
1.080
1.120
1.240
1.270
1.450
1.480
2.050
2.080
.250
.290
.330
.370
.515
.540
.530
.550
.530
.550
.310
.385
.410
.480
.585
.700
.585
.700
.585
.700
.110
.090
.110
.090
.110
.090
.110
.090
.110
.090
.110
.125
.150
.125
.150
.125
.160
.125
.160
.125
.160
.125
.160
.060
.015
.060
.015
.060
.015
.060
.015
.060
.015
.060
.015
.060
.040
.030
.040
.025
.055
.015
.045
.035
.065
.040
.070
.040
.070
Notes: 1. Standard lead finish is tin plate or solder dip.
2. Dimension E2 is an outside measurement.
C-5
Min.
.150
PACKAGE OUTLINES (Cant.)
HERMETIC DUAL IN-LINE PACKAGES
TD5
i.
0-8-1
0-8-2
1
4
-l Sl I--
--I b1 I--
I
D
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P~lSEATINGH
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0-14-1
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~f-b t
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0-14-3
0-16-2
0-16-1
[~:::::::I
~ ~b1
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I
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~ ~f-b
~1
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PLANE
IS.EATING
L
C-
a
C-6
f--E1-----l
PACKAGE OUTLINES (Cant.)
HERMETIC DUAL IN·LlNE PACKAGES (Cont.)
0·18·1
0·18·2
I
A
E
I
0
~~""'" t:JI:l
L
I
PLANE
~ ~ -H--~Q
e
0·20-1
0-20-2
0-22-1
0-22-2
0-24-1 and 0-24-4
C-7
c
~_
~
~El-1
PACKAGE OUTLINES (Cont.)
HERMETIC DUAL IN-LINE PACKAGES (Cont.)
0-24-4*
0-24-2
0-28-1
0-28-2
T28
E
)
l~
D
15
14
_1-- 5 1
0-40-1
\
0-40-2
0-48-2
c-s
PACKAGE OUTLINES (Cant.)
HERMETIC DUAL IN-LINE PACKAGES (Cont.)
0-8-1
0-8-2
CEROIP
SIOEBRAZED
AMO Pkg.
Common
Name
38510
AppendlxC
0-14-1
0-14-2
0-14-3
(Note 2)
0-16-1
0-16-2
CEROIP
SIOEBRAZED
METAL
DIP
CEROIP
SIOEBRAZED
-
-
Parameters
Min.
Max.
A
.130
b
0-1(1)
0-1 (3)
0-1(1)
0-2(1)
0-2(3)
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
.130
.200
.100
.200
.100
.200
.130
.200
.100
.200
.022
.016
.020
.015
.022
.015
.023
.016
.020
.015
.022
.040
.065
.050
.070
.040
.065
.030
.070
.050
.070
.040
.065
.011
.008
.013
.009
.011
.008
.013
.008
.011
.009
.011
.008
.013
.820
Min.
Max.
Min.
.200
.100
.200
.016
.020
.015
b1
.050
.070
c
.009
0
.370
AOO
.500
.540
.745
.785
.690
?30
.660
.785
.745
.785
.780
E
.240
.285
.260
.310
.240
.285
.260
.310
.230
.265
.240
.310
.260
.310
E1
.300
.320
.290
.320
.290
.320
.290
.320
.290
.310
.290
.320
.290
.320
e
.090
.1W
.090
.110
.090
.110
.090
.110
.090
.110
.090
.110
.090
.110
L
.125
.150
.125
.160
.125
.150
.125
.160
.100
.150
.125
.150
.125
.160
Q
.015
.060
.020
.060
.015
.060
.020
.060
.020
.080
.015
.060
.020
.060
S1
.004
a
3°
13°
Standard
Lead
Finish
AMO Pkg.
Common
Name
.010
.005
.005
3°
.005
.020
13°
3°
13°
.005
3°
13°
b
bore
b
bore
e
b
bore
0-18-1
0-18-2
0-20-1
0-20-2
0-22-1
0-22-2
0-24-1
CEROIP
SIOEBRAZED
CEROIP
SIOEBRAZED
CEROIP
SIOEBRAZED
CEROIP
-
-
38510
Appendix C
-
-
Parameters
Min.
A
.130
b
-
-
Min.
Max.
0-3(1)
Max.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
.200
.100
.200
.140
.220
.100
.200
.140
.220
.100
.200
.150
.225
.016
.020
.015
.022
.016
.020
.015
.022
.016
.020
.015
.022
.016
.020
b1
.050
.070
.040
.065
.050
.070
.040
.065
.045
.065
.030
.060
.045
.065
c
.009
.011
.008
.013
.009
.011
.008
.013
.009
.011
.008
.013
.009
.011
M!n.
0
.870
.920
.850
.930
.935
.970
.950
1.010
1.045
1.110
1.050
1.110
1.230
1.285
E
.280
.310
.260
.310
.245
.285
.260
.310
.360
.405
.360
.410
.510
.545
E1
.290
.320
.290
.320
.290
.320
.290
.320
.390
.420
.390
.420
.600
.620
e
.. 090
.110
.090
.110
.090
.110
.090
.110
.090
.110
.090
.110
.090
.110
L
.125
.150
.125
.160
.125
.150
.125
.160
.125
.150
.125
.160
.120
.150
Q
.015
.060
.020
.060
.015
.060
.020
.060
.015
.060
.020
.060
.015
.060
S1
.005
a
Standard
Lead
Finish
.005
3°
13°
b
.005
.005
3°
bore
3°
13°
bore
b
e-g
.005
.005
13°
3°
13°
b
.010
bore
b
PACKAGE OUTLINES (Cont.)
HERMETIC DUAL IN-LINE PACKAGES (Cont.)
AMO Pkg.
0·24·2
Common
Name
SIDE·
BRAZED
0·28·1
0·28·2
CEROIP
SIDE·
BRAZED
0-24-4/0·24-4 •
CERVIEW
0·40·1
0·40·2
0·48·2
CEROIP
SIDE·
BRAZED
SIDE·
BRAZED
38510
Appendix C
-
0·3(3)
Parameters
Min.
A
Min.
Max.
-
0·5
Max.
Max.
Min.
-
Min.
Max.
.100
.200
.150
.225
.150
.225
.100
.200
.150
.225
.100
.200
.100
.200
b
.015
.022
.016
.020
.016
.020
.015
.022
.016
.020
.015
.022
.015
.022
b1
.030
.060
.045
.065
.045
.065
.030
.060
.045
.065
.030
.060
.030
.060
c
.OOB
.013
.009
.011
.009
.011
.OOB
.013
.009
.011
.OOB
.013
.OOB
.013
2.430
Min.
Min.
Max.
Min.
Max.
Max.
0
1.170
1.200
1.235
1.2BO
1.440
1.500
1.380
1.420
2.020
2.100
1.960
2.040
2.370
E
.550
.610
.510
.550
.510
.550
.560
.600
.510
.550
.550
.610
.570
.610
E1
.590
.620
.600
.630
.600
.630
.590
.620
.600
.630
.590
.620
.590
.620
e
.090
.110
.090
.110
.090
.110
.090
.110
.090
.110
.090
.110
.090
.110
L
.120
.160
.120
.150
.120
.150
.120
.160
.120
.150
.120
.160
.125
.160
Q
.020
.060
.015
.060
.015
.060
.020
.060
.015
.060
.020
.060
.020
.060
S1
.005
30
(l'
Standard
Lead
Finish
.010
borc
.005
130
.005
130
30
b
30
b
Notes: 1.· Load finish b is tin plate. Finish c is gold plate.
2. Used only for LM10B/LM10BA.
3. Dimensions E and D allow for off-center lid, meniscus and glass overrun.
C-10
.005
.005
.005
130
b
borc
b orc
PACKAGE OUTLINES (Cant.)
FLAT PACKAGES
F-10-1
F-10-2
F-14-1 and F-14-2
F-16-1 and F-16-2
s
r-L---j
i
,.
r
.1 14)l
Ir
I
L
•
:I1
0
b
+=I
I
I
7
B
IJ
I
0
1
,
I--E--J
e
- - L 1- - - - i
1--,
Q
L
r-
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L
~===::::::;"IIIr;=11= = =
A
Q
==J===Ib~ !
Q
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f t
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f
1.I rli24)
0
12 131
IIII
T
~
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f
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~
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F-24-3
---1
f
L
,~Ir---- E1------j
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L1
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L
b
L
===~III~II===
F-24-2
b
01===
=T:
I
f--E---j
E
F-24-'1
F-22-1
F-20-'
fti~iL-1i·1J1
1114
1
I
Note: Notch is pin 1 index on cerpack.
~
1.
T
1.
T
I
F-28-1
Irill
DoI
0".
12 13
II] III
e
C-11
1
1
r
t
01
!
PACKAGE OUTLINES (Cont.)
FLAT PACKAGES (Cont.)
F-42-1
F-28-2
F-48-2
~
!
t'l
A
,!
i
i
i
!
i
Parameters
A
b
c
D
D1
E
E1
e
L
L1
F-1D-1
F-4
~1
F-14-1
F-4
F-16-1
F-14-2
METAL
FLAT PAK
CERPACK
.F-1
F-2D-1
F-16-2
METAL
FLAT PAK
CERPACK
F-22-1
METAL
FLAT PAK
CERPACK
-
F-5
F-1
-
-
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
.080
.019
.006
.255
.045
.012
.003
.235
.045
.015
.004
.230
.080
.019
.006
.255
.045
.012
.003
.230
.085
.019
.006
.425
.045
.015
.003
.370
.085
.019
.006
.520
.045
.015
.003
.380
.240
.240
.260
.275
.055
.370
.980
.040
.240
.245
.285
.290
.055
.370
.980
.040
.245
.085
.019
.006
.400
.410
.285
.305
.055
.370
.980
.040
.045
.015
.004
.490
.260
.275
.055
.370
.980
.040
.085
.019
.006
.270
.280
.260
.280
.055
.370
.980
.040
.045
.015
.004
.370
.240
.080
.019
.006
.275
.275
.260
.280
.055
.370
.980
.040
.245
.285
.290
.055
.370
.980
.040
.380
.090
.019
.006
.420
.440
.420
.440
.055
.320
.980
.040
Standard
Lead
Finish
Parameters
A
b
0
01
E
E1
e
L
L1
Q
51
Standard
Lead
Finish
.045
.300
.920
.010
.005
F-24-1
CERPACK
.045
.300
.920
.010
.005
.045
.300
.920
.020
.005
b
c
b
F-24-2
METAL
FLAT PAK
F-24-3
METAL
FLAT PAK
F-28-1
METAL
FLAT PAK
c
b
AMO Pkg.
Common
Name
38510
Appendix C
c
.045
.300
.920
.010
.005
F-6
-
F-8
Min.
Max.
Min.
Max.
Min.
Max.
.050
.015
.004
.580
.090
.019
.006
.620
.045
.015
.003
.360
.045
.015
.003
.380
.385
.410
.055
.320
.980
.040
.245
.090
.019
.006
.420
.440
.420
.440
.055
.320
.980
.040
.045
.015
.003
.360
.360
.090
.019
.006
.410
.420
.285
.305
.055
.370
.980
.040
.080
.019
.006
.410
.410
.410
.410
.055
.320
1.000
.040
.045
.265
.920
.020
.005
b
.045
.300
.920
.010
.005
c
.045
.250
.920
.010
O·
.360
.045
.270
.955
.010'
0
c
c
.045
.300
.920
.020
.005
F-28-2
CERAMIC
FLAT PAK
Min.
.065
.016
.007
.700
.625
.045
.415
1.475
.017
.005
c
F-42-1
CERAMIC
FLAT PAK
c
F-48-2
CERAMIC
FLAT PAK
-
·Max.
Min.
Max.
Min.
Max.
.085
.025
.010
.720
.720
.650
.650
.055
.435
1.500
.025
.070
.017
.006
1.030
.115
.023
.012
1.090
1.090
.660
.660
.055
.370
1.370
.060
.070
.018
.006
1.175
.110
.022
.010
1.250
1.250
.670
.670
.055
.370
1.365
.055
.620
.045
.320
1.300
.020
.005
c
Notes: 1. Lead finish b is tin plate. Finish c is gold plate.
2. Dimensions E1 and D1 allow for off-center lid, meniscus, and glass overrun.
C-12
.045
.250
.920
.010
b
-
Max.
.380
.045
.300
.920
.010
.005
c
-
Min.
r
f f
.045
.015
.004
.230
.045
.300
.920
.010
.005
Q
F-10-2
METAL
FLAT PAK
CERPACK
t
I I
\
AMD Pkg.
Common
NAME
38510
Appendix C
A
I=E~Q
Q
.615
.045
.320
1.310
.020
.015
c
SALES OFFICES AND REPRESENTATIVES
SOUTHWEST AREA
Advanced MIcro DevIce.
9595 Wilshire Boulevard
Suite 401
Beverly Hills, Cal~ornia 90212
Tel: (213) 278-9700
(213) 278-9701
TWX: 91().49Q.2143
Advanced MIcro Devl,,"
1414 West Broadway Road
Suite 239
Tempe, ArIzona 85282
Tel: (602) 244-9511
TWX: 91C>-950-0127
Advanced MIcro Devl,,"
4000 MacAtthur Blvd.
Suite 5000
Newport Beach, CalifornIa 92560
Tel: (714) 752-6262
TWX: 910-595-1575
Advanced MIcro Devl,,"
13771 No. Central Expy.
Suite 1008
Dallas, Texas 75243
Tel: (214) 234-5886
TWX: -91 C>-867-4795
Advanced MIcro Devl,,"
5955 Desoto Ave., Suite 249
Woodland Hills, California 91367
Tel: (213) 992-4155
TWX: 91().494-4720
NORTHWEST AREA
Advanced MIcro Device.
3350 Scott Boulevard
~~~:'a 19;,~a,Bb~iI~ia
95051
Tel: (408) 727-1300
TWX: 91C>-338-0192
Advanced Micro Devl,,"
7000 Broadway
Suite 401
Denver, Colorado 80221
Tel: (303) 426-7100
TWX: 91C>-931-2562
Advanced Micro Devl,,"
7110 S.W. Fir Loop, Suite 130
re~:ar(~'6ftl ~~~23
TWX: 91 ().458-8797
Advanced Micro Device.
Honeywe'l Ctr., Suite 1002
600 l08th Ave. N.E.
~~~I~0"6) ~~~~~6'1i8n
98004
MI[)'AMERICA AREA
Advanced Micro Devices
1111 Plaza Drlve, Suite 420
Schaumburg, Illinois 60195
Tel: (312) 882-8660
TWX: 91C>-291-3589
Adv.nced Micro DevIce.
3400 West 66th Street
Suite 375
Edina, Minnesota 55435
Tel: (612) 929-5400
TWX: 91C>-576-0929
Advenced Micro DevIce.
50 McNaughton Road
Suite 102
Columbus, Ohio 43213
Tel: (614) 864-9906
TWX: 81C>-339-2431
Advanced Micro DevIce.
33150 Schoolcraft, Suite 104
¥~~(~i~i~~~~~l50
TWX: 81C>-242-87n
MI[)'ATlANTlC AREA
Advanced MIcro DevIce.
40 Crossway Park Way
Woodbury, New York 11797
Tel: (516) 364-8020
TWX: 51C>-221-1819
Advanced MIcro DevIce.
6808 Newbrook Ave.
E. Syracuse, New York 13057
NORTHEAST AREA
Advanced MIcro DevIce.
300 New Boston Park
Woburn, Massachusetts 01801
Tel: (617) 933-1234
TWX: 71C>-348-1332
~~LJ~~ 5~"J~~r6
SOUTHEAST AREA
Advanced MIcro DevIce.
793 Elkridge Landing,.#IIN
Unthicum, Maryland 21090
Tel: (301) 796-9310
TWX: 71C>-861-0503
Advanced Micro DevIce.
1001 N.w. 62nd Street
Suite 100
Ft. Lauderdale, Florida 33309
Tel: (305) 771-6510
TWX: 51C>-955-9490
Advanced Micro Device.
6755 Peachtree Industrtal Boulevard
Suite 104
Advanced MIcro Devlcea
2 Kilmer Road
Edison, New Jersey 08817
Tel: (201) 985-6800
TWX: 71C>-48C>-6260
Advanced MIcro Devlcea
1 Gibralter Plaza, Suite 219
~~~sr:l~i ~~~r,oania 19044
TWX: 51C>-665-7572
Advenced Micro Devlc••
82 Washington Street, Suite 206
Poughkeepsie, New York 12601
Tel: (914) 471-8180
TWX: 51C>-248-4219
~~I~n~o!;".:'l~~9~g360
TWX: 61C>-766-0430
Advanced Micro DevIces
501 Archdale Dr .. Suite 227
Charlotte, North Carolina 26210
Tel: (704) 525-1875
Advanced Micro Devices International Sales Offices
BELGIUM
Advanced Micro Devices
FRANCE
Advanced Micro Devices, S.A.
Overseas Corporation
Avenue de Tervueren, 412, bte 9
B-II50 Bruxelles
~til'~~.nJl~~t~a~~tre
i~~J~~) 6~1g9 93
~~~J~!J~~.75
F.IJ64oo Cannes
Advanced Micro Devices, S.A.
Silic 314, Immeuble Helsinki
74, rue d'Arcueil
F-94588 Rungis Cedex
Tel: (01) 686.91.86
TELEX: 202053
GERMANY
Advanced Micro Devices GmbH
Rosenheimer Str. 139
0-8000 Muenchen 80
Tel: (089) 40 19 76
TELEX: C>-523883
Advanced Micro Devices GmbH
Harthaeuser Hauptstrasse 4
0-7024 Filderstadl 3
i~LJ~:I~j2~}I~ 30
JAPAN
Advanced Micro Devices, K.K.
Dai 3 Hoya Building
8-17, Kamitakaido l-chome
Suginaml-ku, Tokyo 168
Tel: (03) 329-2751
TELEX: 2324064
Advanced Micro Devices, K.K.
Daidoh-Seimel Ezaka Dai-2 Bldg.
23-5, l-chome, Ezaka-cho, Suita-shi
Osaka 564
Tel: (06) 386-9161
ITALY
Advanced Micro Devices S.R.L.
Centro Direzionale
SWEDEN
Advanced Micro Devices AB
Box 7013
S-172 07 Sundbyberg
~~LJ~) l~ci~ 35
UNITED KINGDOM
Advanced Micro Devices (U.K.) Ltd.
A.M.D. House,
Goldsworth Road,
Woking.
Surrey GU21 lJT
Tel: Woking (04862) 22121
TELEX: 859103
Palazzo Vasari, 3° Piano
1-20090 MI2 - Segrate (MI)
~~LJ~~) ~~2:~13-4-5
International Sales Representatives and Distributors
ARGENTINA
Thiko, S.A. Electronica
Peru 653
1068 - Buenos Aires
GERMANY
Cosmos Eleklronlk GmbH
Hegelstrasse 16
0-8000 Muenchen 83
~~r:e(lt~n~0-4132
3;7~~0
~~LJ~96.~l~~
EBV-Eleklronik Vertriebs GmbH
TELJU:
Koti International Corporatior'l
1660 RolI!ns Road
~~I~Ii(2f~~9~~~~~ia
94010
TELEX: 33)491
AUSTRAUA
A.J. Distributors Ply. Ltd.
P.O. Box 71
44 Prospect Road
Prospect, S.A. 5082
Tel: (6) 269-1244
TELEX: 82635
R and 0 Electronics
257 Burwood Highway
P.O. Box 206
Burwood 3125
Victoria
Tel: (03)
TELEX: AA33288
288-8232162
Rand 0 Electronics
P.O. Box 57
Crows Nest N.S.W. 2065
Sydney
Tel: (61) 439-5488
TELEX: (790) 25468
AUSTRIA
Kontron Ges.m.b.H.
Industriestr. B 13
A-2345 Brunn am Gebirge
Tel: (02236) 8 66 31
TELEX: 79337
BELGIUM
MCA Tronix S.P.R.L.
Route du Condroz, 513
B-42oo Ougree
Tel: (041) 3627801362795
TELEX: 42052
DENMARK
Advanced Electronic of Denmark Aps
Mariendalsvej 55
DK-2OOQ Copenhagen F
Tel: (01) 19 44 33
TELEX: 22 431
FINLAND
KomdelOY
Vanha Finnoontie 4
Box 32
SF'()2271 Espoo 27
Tel: (0) 885 011
TELEX: 12 1926
FRANCE
A2M
6, Avenue du G,,"eral De Gaulle
HallA
F-78150 Le Chesnay
Tel: (01) 954.91.13
TELEX: 698 376
~r.'~~I~;,orini~~~~~~ (LED)
F-69352 Lyon Cedex 2
~~LJ~~8~~:io85
RTf
73, avenue Charles De Gaulle
F-92200 Neuilly-sur-Seine
i~~J~~) ~~~J.Ol
~~~~terhaching b. Muenchen
~~LJ~96.~~J~~-1
Indelco, S.R.L. - Roma
Via C. Colombo, 134
Hl0147 Roma
Tel: (06) 514 0722
TELEX: 611517
Cramer Italia S.p.A.
Via Ferrarese, 10/2
1-40126 Bologna
Tel: (051) 372777
TELEX: 511870
EBV-Elektronik Vertriebs GmbH
Oststr.129
0-4000 Duesseldorf
Cramer Italia S.p.A.
Via S. Simpliciano, 2
1-20121 Milano
Tel: (02) 809326
~~LJ~~Ig:58~2~r
Cramer ltalia S.p.A.
3° Traversa Domenico Fontana, 22 AJB
EBV-Eleklronik Vertrlebs GmbH
Kiebitzrain 18
[)'3008 Burgwedel I/Hannover
Tel: (05139) 50 38
TELEX: C>-923694
EBV-Eleklronik Vertriebs GmbH
Mytiusstr. 54
0-6000 Franldurt 1
~~LJ~IU;~16
EBV-Eleklronik Vertriebs GmbH
Alexanderstr. 42
[).7000 Stuttgart 1
NETHERLANDS
Arcobel BV
Van Almondestraat 6
P.O. Box 344
NL-5340 AE Oss
~~LJ~I~~t2oo/27574
Cramer Italia S.p.A.
Corso Traiano, 109
1-10127 Torino
~~LJ~~1)2~11i5~06212067
NORWAY
A.S Kjell Bakke
~~8~~0~143
N-2011 Stroemmen
~~LJ~~) t~~ 50
~~LJ~:I~;2~~~181/83
Elbatex GmbH
Caecilienstr. 24
[).7100 Heilbronn
Tel: (07131) 89 00 1
TELEX: C>-728362
Nordelektronik Vertriebs GmbH
Bahnhofstr. 14
[)'2301 Kiel-Ra.isdorl
Tel: (04307) 54 83
SINGAPORE
JAPAN
Advanced Technology Corporation
of Japan
Tashi Bldg., 3rd Floor
No.8, Minami Motomachi
Shinjuku-ku, Tokyo 160
Tel: (03) 265-9416
Chiyoda-ku, Tokyo 100
Tel: (03) 218-5690
MEV-Mikro Elektronik Vertrieb
H. Uchotka GmbH
Muenchener Slrasse 16A
~~~~)k~1J~6
TELEX: C>-527826
INDIA
SRI RAM Associates
P.O. Box 60965
Sunnyvale, CA 94088
Tel: (408) 738-2295
TELEX: 348369
SRI RAM Associates
245 Jayanagara III Block
Bangalore 560011
Tel: 611606
TELEX: 845-8162
ISRAEL
TalvitOl\ Electronics, Ltd.
P.O. Box 21104
9, Biltmor Street
Tel-Aviv
~LJ~)~~
ITALY
Indelco, S.R.L. - Milano
Via S. Simpliciano, 2
1-20121 Milano
Tel: (02) 862963
~~m~~:;'h ~:~isLtd
100 Beach Road
Singapore 0718
Tel: 292 4342
7464260
TELEX: RS 34235
TAIWAN
Everdata Pacific Co.
3421 Geary Blvd.
San Francisco, CA 94118
Tel: (415) 668-7524
TELEX: 171470
Everdata International Corp.
II/F 219, Chung Hsiao E. Rd.
Sec. 4, Taipei
Tel: 752-9911
TELEX: 21528
~~: ~~~~~c~Fany, Ltd.
Nordeleklronik Vertriebs GmbH
Harksheiderweg 238-240
[)'2085 Ouickborn
Tel: (04106) 40 31
TELEX: 0.2t4299
!f:1fcie~)i~~ ~i Muenchen
~;1~~~~ ~~I~g~l
TELEX: 13033
SWilZERLAND
Kurt Hirt AG
Thurgauerstr. 74
CH-8050 Zuerich
Tel: (01) 302 21 21
TELEX: 53461
~1~~a~~oo
Cramer Ilalia S.p.A.
Via C. Colombo, 134
HlOt47 Roma
Tel: (06) 517981
TELEX: 611517
SWEDEN
Svensk Teleindustri AB
Box 5024
Dainichi Electronics
Kohraku Building
1-8, l-chcme, Kohraku
SOUTH AFRICA
South Continental Devices (Ply.) Ltd.
P.O. Box 56420
~~:eygm~~~~400
TELEX: 4-24849 SA
Dainichi Electronics
Kintetsu-Takama Building
38-3 Takama-cho
Narashi 630
lSI Ltd.
8-3, 4-chcme, Udabashi
Chiyoda-ku, Tokyo 102
Tel: (03) 264-3301
Kanematsu Denshi K.K.
Takanawa Bldg., 2nd Floor
19-26, 3-chcme, Takanawa
Min,toku, Tokyo 108
SOUTH AMERICA
Intectra
2349 Charleston Road
Mountain View, CA 94043
Tel: (415) 967-8818/25
TELEX: 345 545
Microtek, Inc.
Naito Buildil)Q
7-2-8 Nishish.njuku
Shinjuku-ku, Tokyo 160
~~~1"e~;~'19
~~LJ~) ]2~~17
Tel: (03) 386 19 58
SPAIN
Barcelona
Regula S.A.
Avda. de Ram6n y Cajal, 5
Madrid-16
KOREA
Duksung Trading Co.
Room 301 - Jinwon Bldg. 507-30
Sinrim 4-Dong
Gwanak-ku
Seoul
Tel: 856-9764
TELEX: K23459
~~LJ~~) :~~g.? 00104108
Sagitr6n, S.A.
General de Importaciones Electronicas
.
Ct. Castell6, 25, 2~
Madfid..l
~~LJ~~) tIi;f24
UNITED KINGDOM
Candy Electronic Components
52 College Road
Maidstone, Kent ME15 6SA
Tel: (0622) 54051
TELEX: 965998
Hawke-Cramer
Hawke Electro.:'cs Limited
Amotex House
45 Hanworth Road
Sunbury-on-Thames
Middlesex TW16 5DA
Tel: (01) 979-7799
TELEX: 923592
Dage Eurosem, Ltd.
Haywood House
64 High Street
Pinner, Middlesex, HA5 5QA
Tel: (01) 868 0028/9
TELEX: 24506
ITT Electronic Services
Edinburgh Way
Harlow, Essex CM20 2DF
Tel: Harlow (0279) 26777
TELEX: 81525
Memec, Ltd.
Thame Park Industrial Estate
Thame
Oxon OX93RS
Tel: Thame (084 421) 3146
TELEX: 837508
Ouarndon Electronics
~~~ir:n~uctors) Ltd.
~~~!: (~~2) 363291
TELEX: 37163
u.s. and Canadian Sales Representatives
ALABAMA
~r~~=~f~:,~r~~~nts
Huntsville. Alabama 35801
Tel: (205) 533-6440
lWX: 810-726-2110
CAUFORNIA
(Nor1hem)
12 Incorporated
3350 Scott Boulevard
Suite 1001. Bldg. 10
Santa Clara. Calilomla 95050
Tel: (408) 988-3400
lWX: 910-338-0192
~)
e
7827 Conv0 Court. Suite 407
San DI~O. aldornla 92111
Tel: (40 278-2150
lWX: 910-335-1267 .
CANADA (Ea."m)
Vltel Electronics
3300 Cote Vertu. Suite 203
St. Laurent. Quebec.
Canada H4R 2B7
Tel: (514) 331-7393
lWX: 610-421-3124
TELEX: 05-821762
Vital Electronics
1 Vulcan St.. Suite 203
Rexdale. Ontario.
Canada M9W 113
Tel: (416) 245-8528
lWX: 610-491-3728
Vitel Electronics
85 Albert Street. Suite 1610
Ottawa. Ontario
Canada KIP 6A4
CONNECTICUT
ScIentific Components
1185 South Maln Street
Cheshire. Connecticut 06410
Tel: (203) 272-2965
lWX: 710-455-2078
FLORIDA
INDIANA
Electro Reps .• Inc.
941 E. 86th St.. Suite 101
~~!a(m)Ii~5~if.;':
46240
lWX: 810-341-3217
Electro Reps .• Inc.
3601 Hobson Rd .• Suite 106
Ft. Wayne. Indiana 46815
Tel: (219) 483-0518
lWX: 810-332-1613
~B~eJo~ ~ates. Inc.
235 South Central Ave.
Oviedo. Florida 32765
Tel: (305) 365-3283
lWX: 810-856-3520
Conle~ & Associates. Inc.
~~6~ eO':t~econd Ave.
IOWA
Lorenz Sales. Inc.
5270 No. Park PI.. N.E.
Cedar Raplds. Iowa 52402
Tel: (319) 3n-4668
Boca Raton. Florida 33432
Tel: (305) 395-6108
lWX: 510-953-7548
Conley & Associates. Inc.
4021 W. Waters Avenue
Suite 2
Tampa. Florida 33614
~\8~~b:rt~~5:
KANSAS
Kebco Sales
7070 West 107th Street
Suite 160
Overland Park. Kansas 66212
Tel: (913) 649-1051
lWX: 910-749-40n
GEORGIA
~~~~;c~::'=~~ri~,A~~~t~ N.E.
Suite 103
~:,~(~o!;~~~~60
lWX: 810-766-9430
MICHIGAN
SAl. Marketing Corp.
P.O. Box N
Brighton. Michigan 48116
Tel: (313) 227-1786
lWX: 810-242-1518
~L~~3b&~96
CANADA (W....m)
Vital Electronics
3665 Klngsway. Suite 211
Burnaby. British Columbia
Canada V5R 5W2
Tel: (604) 438-6121
lWX: 610-953-4925
NEBRASKA
Lorenz Sales
2809 Garfietd Avenue
Uncaln. Nebraska 68502
Tel: (402) 475-4660
NEW JERSEY
T.A.I.Corp.
12 So. Black Horse Pike
Bellmawr. New Jersey 06031
Tel: (609) 933-2600
lWX: 71()..639-1810
MISSOURI
Kebco Manulacturers
75 Worthington Drive. Ste. 101
Mariland Heights. Missouri 63043
Tel: (314) 576-4111
lWX: 910-764-0826
~!~~~~r.2~f~~o'"ania
15017
TEXAS
Bonser-Philhower Sales
13777 N. Central Expressway
Suite 212
Dallas. Texas 75243
Tel: (214) 234-8438
Bonser-Philhower
~~o~~~:,:s~'OXi. Suite 200
NEW MEXICO
The Thorson Company
1101 Cerdenas. N.E.
Suite 109
Albuquerque. New MexiCO 87110
Tel: (505) 265-5655
lWX: 910-989-1174
NEW YORK
~~c;.:er''[frive
East Syracuse. New York 13057
Tel: (315) 437-6343
lWX: 710-541-1506
OHIO
Dolluss-Root & Co.
134n Prospect Road
~~;?(~~6~'~~~0044136
ILLINOIS
Oasis Sales. Inc.
1101 Towne Road
Elk Grove Village. Illinois 60007
Tel: (312) 640-1850
lWX: 910-222-1n5
PENNSYLVANIA
Dolfuss-Root & Co.
United tndustrial Park
Suite 203A. Building A
98 Vanadium Road
lWX: 810-427-9148
Dolfuss-Root & Co.
683 Miamisburg-Centerville Road
Suite 202
Centerville. Ohio 45459
Tel: (513) 433-6ne
Tel: (713) 783-0063
Bonser-Philhower Sales
8330 Burnett Rd.
Suit. 133
Austin. Texas 78758
Tel: (512) 458-3569
UTAH
R2
940 North 400 East. Suite B
NIorth Salt Lake. Utah 84054
Tel: (801) 298-2631
lWX: 910-925-5607
WASHINGTON
Venture Electronics
1601 116th N.E .• Suite 109
P.O. Box 3034
Bellevue. Washi~on 98005
~LJx~a:ret,5
WISCONSIN
Oasis Sales. Inc.
N.81 W. 12920 Lacn Road
Suite 111
Menomonee Falls. Wisconsin 53051
Tel: (414) 445-6682
U.S. AND CANADIAN STOCKING DISTRIBUTORS
ALABAMA
Hamilton/Avnet Electronics
4812 Commercial Drive
Huntsville, Alabama 35805
Tel: (205) 533·1170
Hall·Mark Electronics
4900 Bradford Drive. N.w.
P.O. Box 1133
Huntsville, Alabama 35807
Tel: (205) 837-8700
ARIZONA
Wyle Distribution Group
8155 North 24th Avenue
Phoenix. Arizona 85021
Tel: (602) 249-2232
Hamilton/Avnet Electronics
505 South Madison Drive
Tempe, Arizona 85281
Tel: (602) 275-7851
TWX: 910-951-1535
CALIFORNIA
Avnet Electronics
350 McCormick Avenue
Irvine Industrial Complex
Costa Mesa. California 92626
Tel: (714) 754-6084
TWX: 910-595-1928
Bell Industries
1161 North Fairoaks Avenue
Sunnyvale, California 94086
Tel: (408) 734-8570
TWX: 910-339-9378
Hamilton Electro Sales
10912 West Washin~ton Boulevard
Culver City. California 90230
Tel: (213) 558-2131
(714) 522-8220
TWX: 910-340-6364
910-340-7073
TELEX: 67-36-92
Hamilton/Avnet Electronics
1175 Bordeaux
Sunnyvale, California 94086
Tel: (408) 743-3300
TWX: 910-339-9332
Future Electronics
~~~~:~~~~"B~YtiSh Columbia
Canada V5R 5J7
Tel: (604) 438-5545
TWX: 610-922-1668
IOWA
Schweber Electronics
5270 Nor1h Park Place, N.E_
Cedar Rapids, fowa 52402
Tel: (319) 373-1417
Future Electronics
Baxter Centre
1050 Baxter Road
Ottawa. On'arlo
Canada K2C 3P2
Tel: (613) 820-8313
COLORADO
Wyle Distribution Group
451 East 124th Avenue
Thornton, Colorado 80241
Tel: (303) 457-9953
Hamilton/Avnet Electronics
8765 East Orchard Road
Suite 708
Englewood, Colorado 80111
Tel: (303) 740-1000
Bell tndustries
8155 West 48th Avenue
'f.r:aV~~~i'4~~~~r~~~
80033
TWX: 910-938-0393
CONNECTICUT
Hamilton/Avnet Electronics
Commerce Park
Commerce Drive
Danbury, Connecticut 06810
Tel: (203) 797-2800
TWX: 710-456-9974
Schweber Electronics
Finance Drive
Commerce Industrial Park
Danbury, Connecticut 06810
Tel: (203) 792-3500
Arrow Electronics
295 Treadwell Street
Hamden. Connecticut 06514
Tel: (203) 248-3801
TWX: 710-465-0780
~~~5DY~~~,~~~?o~?:d92123
Wilshire Electronics
Village Lane
Barnes Industrial Park
P.O_ Box 200
Wallingford, Connecticut 06492
Tel: (203) 265-3822
Hamilton/Avnet Electronics
3170 Pullman
Costa Mesa, California 92626
Tel: (714) 641-1850
FLORtDA
Arrow Electronics
115 Palm Bay Road, N.w.
Suite 10
Palm Bay. Florida 22905
Tel: (305) 725-1480
Hamilton/Avnet Electronics
Tel: (714) 571-7500
TELEX: 69-54-15
Wyle Distribution Group
9525 chesa8eake Drive
¥~~ ?~if)56~~I~f;~ia
92123
TV/X: 910-335-1590
Schweber Electronics
17811 Gillette
Irvine, California 92714
Tel: (213) 537-4320
TWX: 910-595-1720
Schweber Electronics
3110 Patrick Henry Drive
Santa Clara, California 95050
Tel: (408) 496-0200
TWX: 910-338-2043
Wyle Distribution Group
124 Maryland Avenue
EI Segundo, California 90545
Tel: (213) 322-8100
TWX: 910-348-7140
910-348-7111
Arrow Electronics
720 Palomar Avenue
Sunnyvale, California 94086
Tel: (408) 739-3011
TWX: 910-339-9371
Wyle Distribution Group/Santa Clara
3000 Bowers Avenue
Santa Clara, California 95052
Tel: (408) 727-2500
TWX: 910-338-0296
910-338-0541
Wyle Distribution Group
Orange County Division
17872 Cowan
Irvine, California 92714
Tel: (714) 641-1600
CANADA
Hamilton/Avnet Electronics
2670 Sabourin
SI. Laurent, Quebec, Canada H4S , M2
Tel: (514) 331-6443
TWX: 610-421-3731
Hamilton/Avnet Electronics
3688 Nashua Road
Mississauga, Ontario, Canada l4V 1M5
Tel: (416) 677-7432
TWX: 610-492-8867
Hamilton/Avnet Electronics
1735 Courtwood Crescen'
Onawa,. Ontario. Canada K2C 3J2
Tel: (613) 226-1700
TWX: 610-562-1906
RAE Indus'rial Electronics, Ltd.
3455 Gardner Court
Burnaby, British Columbia
Canada V5G 4J7
Tel: (604) 291-8866
TWX: 610-929-3065
TELEX: 04-356533
Hamilton/Avnet Electronics
485 Gradle Drive
Indianapolis, Indiana 46032
Tel: (317) 844-9333
Arrow Electronics
1001 N.W. 62nd Street, Suite 402
FI. Lauderdale, Florida 33300
Tel: (305) 776-7790
Hall-Mark Electronics
7233 lake Ellenor Drive
Orlando, Florida 32809
Tel: (305) 855-4020
TWX: 810-850-0183
Hall-Mark Electronics
1302 West McNabb Road
Ft. Lauderdale, Florida 33309
Tel: (305) 971-9280
TWX: 510-956-9720
Hamilton/Avnet Electronics
6600 N.W_ 20th Avenue
FI. Lauderdale, Florida 33309
Tel: (305) 97t-2900
Hamilton/Avnet Electronics
3197 Tech Drive North
SI. Petersburg. Florida 33702
Tel: (813) 576-3930
Hall-Mark Electronics
2091 Springdale Road
S~ringdale Business Center
~el~r~1~\1I3~~~3J~sey
KANSAS
Hall-Mark Electronics
11870 West 91st Street
Congleton Industrial Park·
Shawnee Mission, Kansas 66214
Tel: (913) 888-4747
TWX: 510-928-1831
Electronic Devices Co., Inc.
3301 Juan Tabo, N.E_
Albuquerque, New Mexico 87111
Tel: (505) 293-1935
MARYLAND
Arrow Electronics
4801 Benson Avenue
Baltimore, Maryland 21227
Tel: (301) 247-5200
NEW YORK
Arrow Electronics
900 Broad Hollow Road
~:r:mi~?gi~94~~06ork
Hall-Mark Electronics
6655 Amberton Drive
Baltimore. Maryland 21227
Tel: (301) 796-9300
TWX: 710-862-1942
~~~(;'iii )~~rt~8g021 076
Tel: (617) 275-5100
Wilshire Electronics
One Wilshire Road
~~lrli(21~)'2~~~i~8~usetts
01803
TWX: 710-332-6359
~;t t3~)'97\~~i~~~
Hall-Mark. Electronics
1177 Industrial Drive
Bensenville, fIIinols 60106
Tel: (312) 860-3800
TWX: 910-222-1815
Hamilton/Avnet Electronics
3901 North 25th Avenue
Schiller Park, IllinOis 60176
Tel: (312) 678-6310
TWX: 910-227-0060
~~~~et~~~~c~b~ive
Elk Grove Village, fIIinois 60007
Tef: (312) 437-9680
TWX: 910-222-1834
Hamilton/Avnet Electronics
5 Hub Drive
Melville, New York 11746
Tel: (516) 454-6000
TWX: 510-224-6166
Hamilton/Avnet Electronics
6500 Joy Road
East Syracuse, New York 13057
Tel: (315) 437-2642
TWX: 710-541-0959
Summit Distributors, Inc.
916 Main Street
Buffalo, New York 14202
Tel: (716) 884-3450
TWX: 710-522-1692
Wilshire Electronics
110 Parkway South
Hauppauge
Long Island, New York 11787
Tel: (516) 543-5599
MICHtGAN
Arrow Electronics
3921 VarSi%Drive
48104
TWX: 810-223-6020
Hamilton/Avnet Electronics
32487 Schoolcraft
Livonia, Michigan 48150
Tel: (313) 522-4700
TWX: 810-242-8775
Pioneer/Michigan
13485 Stamford
Livonia, Michigan 48150
Tel: (313) 525-1800
TWX: 810-242-3271
Wilshire Electronics
10 Hooper Road
Endwell, New York 13760
Tel: (607) 754-1570
TWX: 510-252-0194
'f.r:S\~~'li ~j':7W:
11590
TWX: 510-222-9470
510-222-3660
MISSOURI
Hall-Mark Electronics
13789 Rider Trail
Earth City, Missouri 63045
Tel: (314) 291-5350
TWX: 910-760-0671
Hamilton/Avnet Electronics
13743 Shoreline Court
Earth City, Missouri 63045
Tel: (314) 344-1200
NEW JERSEY
Arrow Electronics
~~g~:s~~~~I,I~e~OJ:rsey
Wilshire Electronics
1260 Scottsville Road
Rochester, New York 14623
Tel: (716) 235-7620
TWX: 510-253-5226
Schweber Electronics
Jericho Turnpike
Hamilton/Avnet Electronics
7449 Cahill Road
Edina, Minnesota 55435
Tel: (612) 941-3801
NORTH CAROLINA
Arrow Electronics
1337-G South Park Drive
Kernersville, North Carolina 27284
Tel: (919) 996-2039
Hall-Mark Electronics
1208 Front Street. Building K
Raleigh, North Carolina 27609
Tel: (919) 832-4465
TWX: 510-928-1831
Hamilton/Avnet Electronics
2803 Industrial Drive
Raleigh, North Carolina 27609
Tel: (919) 829-8030
OHIO
Arrow Electronics
6238 Cochran
Solon, Ohio 44139
Tel: (216) 248-3990
Arrow Electronics
7620 McEwen Road
Centerville, Ohio 45459
Tel: (513) 435-5563
TWX: 810-459-1611
08057
Tel: (609) 235-1900
Arrow Electronics
285 Midland Avenue
Saddle Brook, New Jersey 07662
Tel: (201) 797-5800
TWX: 710-988-2206
Hamilton/Avnet Electronics
10 Industrial Road
Fairfield. New Jersey 07006
Tel: (201) 575-3390
PENNSYLVANIA
Schweber Electronics
101 Rock Road
~~~S~~~~~'!a~~~~~~ania
19044
15238
TWX: 710-795-3122
Hamilton/Avnet Electronics
333 Metro Park
Rochester, New York 14623
Tel: (716) 442-7820
Hall-Mark Electronics
7838 12th Avenue South
Bloomington, Minnesota 55420
Tel: (612) 854-3223
TWX: 910-576-3187
ILLfNOfS
Arrow Electronics
492 LUnt Avenue
Schaumburg, fIIinois 60193
Tel: (312) 893-9420
13088
MASSACHUSETTS
Arrow Electronics
960 Commerce Way
Woburn, Massachusetts 01801
Tel: (617) 933-8130
TWX: 510-224-6494
Schweber Electronics
Almac Stroum Electronics
8022 Southwest Nimbus, Bldg. 7
Koll Business Park
Portland, Oregon 97005
Tel: (503) 641-9070
TWX: 910-467-8743
Pioneer/Pittsburgh
259 Kappa Drive
Arrow Electronics
20 Oser Avenue'
Hauppauge
Long Island, New York 11787
Tel: (516)'231-1000
TWX: 510-227-6623
~~:~~t~a~~~~husetts 01730
OREGON
Hamilton/Avnet Electronics
6024 S.w. Jean Road
Bldg. C, Suite 10
Lake Oswego, Oregon 97034
Tel: (503) 635-8831
~~~sr~1~') ~:~~8l~gnia
PioneerlWashington
9100 Gaither Road
Gaithersburg, Maryland 20760
Tel: (301) 948-0710
TWX: 710-828-0545
Hamilton/Avnet Electronics
50 Tower Office Park
Woburn, Massachusetts 01801
Tel: (617) 935-9700
TWX: 710-393-0382
OKLAHOMA
Hall-Mark Electronics
4846 South 83rd East Avenue
Tulsa, Oklahoma 74145
Tel: (918) 835-8458
TWX: 910-845-2290
TWX: 510-224-6155
Arrow Electronics
3000 South Winton Road
Rochester, New York 14623
Tel: (716) 275-0300
TWX: 510-253-4766
TWX: 710-862-1861
TELEX: 8-79-68
Arrow Electronics
10 Knollcrest Drive
Reading, Ohio 45237
Arrow Electronics
7705 Malt~e Drive
~~?m~) 6~;{g~~
GEORGIA
ArroVi Electronics
2979 Pacific Drive
Hamilton/Avnet ElectroniCS
67001-85
Suite 1E
Norcross, Georgia 30071
Tel: (404) 448-0800
11735
TWX: 710-545-0230
Hamilton/Avnet Electronics
7235 Standard Drive
MINNESOTA
Arrow Electronics
5230 West 73rd Street
Edina, Minnesota 55435
Tel: (612) 830-1800
~~~c(~~\ ~:~:~ka5io071
08003
TWX: 510-667-1750
NEW MEXICO
Hamilton/Avnet Electronics
2450 Baylor Drive, S.E_
Albuquerque, New Mexico 87119
Tel: (505) 765-1500
Hamilton/Avnet Electronics
9219 Quivlra Road
Overland Park. Kansas 66215
Tel: (913) 888-8900
Pioneer/Florida
6220 South Orange Blossom Traif
Suite 412
Orlando, Florida 32809
Tel: (305) 859-3600
TWX: 810-850-0177
TWX: 810/766-0439
Wilshire Electronics
1111 Paulison Avenue
Clifton, New Jersey 07015
Tel: (201) 340-1900
TWX: 710-989-7052
Hamilton/Avnet Electronics
954 Senate Drive
Dayton, Ohio 45459
Tel: (513) 433-0610
TWX: 810-450-2531
Hamilton/Avnet
4588 Emery Industrial Parkway
Cleveland. Ohio 44128
Tel: (216) 831-3500
TWX: 810-427-9452
Future Electronics
5647 Ferrier Street
Montreal, Quebec, Canada H4P 2K5
Tel: (514) 731-7441
TWX: 610/421-3251
05-827789
tNDIANA
Pioneer/Indiana
6406 Castle Place Drive
Indianapolis, Indiana 46250
Tel: (317) 849-7300
TWX: 810-260-1794
Hamilton/Avnet Electronics
1 Keystone Avenue
Cherry Hill, New Jersey 06003
Tel: (609) 424-0100
Arrow Electronics
P_O_ Box 37856
Cincinnati, Ohio 45222
Tel: (513) 761-5432
TWX: 810-461-2670
ruture Electronics
4800 Dufferin Street
Downsview. Ontario
Cnn"d. M3H 5S9
T.I: (4'6) 663-5563
Arrow Electronics
2718 Rand Road
Indianapolis, Indiana 46241
Tel: (317) 243-9353
TWX: 810-341-3119
Schweber Electronics
18 Madison Road
Fairfield, New Jersey 07006
Tel: (201) 227-7880
TWX: 710-480-4733
Pioneer/Cleveland
4800 East 131st Street
Cleveland, Ohio 44105
Tel: (216) 587-3600
TWX: 810-422-2211
TEXAS
Hall-Mark Electronics
P.O. Box 22035
11333 Page Mill Road
Dallas, Texas 75222
Tel: (214) 234-7300
TWX: 910-867-4721
Hall-Mark Electronics
8000 Westglen
Houston, Texas 77063
Tel: (713) 781-6100
TWX: 910-881-2711
Hall-Mark Electronics
10109 McKalla Drive
Suite F
Austin, Texas 78758
Tel: (512) 837-2814
TWX: 910-874-2010
Hamilton/Avnet Electronics
2111 West Walnut Hill Lane
Irving, Texas 75062
i~LJ~~4~~~095~~11
Hamilton/Avnet Electronics
3939 Ann Arbor Street
Houston, Texas 77042
Tel: (713) 780-1771
Hamilton/Avnet Electronics
1050811. Boyer Boulevard
Austin, Texas 78757
Tel: (512) 837-8911
Schweber Electronics
4202 Beltway Drive
Dallas, Texas 75234
Tel: (214) 661-5010
TWX: 910-860-5493
Schweber Electronics
7420 Harwin Drive
Houstoo. Texas 77036
Tel: (713) 784-3600
UTAH
Bell Industries
3639 W.st 2150 South
Salt Lake City, Utah 84120
Tel: (801) 972-6969
TWX: 910-925-5686
Hamilton/Avnet Electronics
1585 West 2100 South
Salt Lake City, Utah 84119
Tel: (801) 972-2800
TWX: 910-925-4018
WASHINGTON
Hamilton/Avnet Electronics
14212 N.E. 21st Street
Bellevue Washington 98005
Tel: (206) 746-8750
TWX: 910-443-2449
Wyle Distribution Group
1750 132nd Avenue, N.E.
Bellevue, Washington '98005
Tel: (206) 453-8300
TWX: 910-443-2526
Almac Stroum Electronics
5811 Sixth Avenue South
Seattle. Washington 98108
Tel: (206) 763-2300
TWX: 910-444-2067
WISCONSIN
Arrow Electronics
434 West Rawson Avenue
Oak Creek, Wisconsin 53154
Tel: (414) 764-6600
TWX: 910-262-1193
Hall-Mark Electronics
9657 South 20th Street
Oak Creek, Wisconsin 53154
Tel: (414) 761-3000
Hamilton/Avnet Electronics
2975 Moorland Road
New Berlin. Wisconsin 53151
Tel: (414) 784-4510
9-9-BO
ADVANCED
MICRO
DEVICES, INC.
901 Thompson Place
p. O. Box 453
Sunnyvale,
California 94086
(408) 732-2400
TWX: 910-339-9280
TELEX: 34-6306
TOLL FREE
(800) 538-8450
9-80
Am9S17A
During memory-to-memory transfers, EOP will be output when
the TC for channel 1 occurs. EOP always applies to the channel
with an active DACK; external EOPS are disregarded in
DACKO-DACK3 are all inactive.
Because EOP is an open-drain signal, an external pullup resistor is required. Values of 3.3K or 4.7K are recommended; the
EOP pin can not sink the current passed by a 1K pull up.
AO-A3 (Address, Input/Output)
The four least significant address lines are bidirectional 3-state
signals. During DMA Idle cycles they are inputs and allow the
host CPU to load or read control registers. When the DMA is
active, they are outputs and provide the lower 4-bits of the output address.
A4-A7 (Address, Output)
The four most significant address lines are three-state outputs
and provide four bits of address. These lines are enabled only
during DMA service.
HREQ (Hold Request, Output)
The Hold Request to the CPU is used by the DMA to request
control of the system bus. Software requests or unmasked
DREQs cause the Am9517A to issue HREQ.
DACKO-DACK3 (DMA Acknowledge, Output)
The DMA Acknowledge lines indicate that a channel is active. In
many, systems they will be used to select a peripheral. Only one
DACK will be active at a time and none will be active unless the
DMA is in control of the bus. The polarity of these lines is programmable. Reset initializes them to active-low.
AEN (Address Enable, Output) .
Address Enable is an active high signal used to disable the
system bus during DMA cycles to enable the output of the external latch which holds the upper byte of the address. Note that
during DMA transfers HACK and AEN should be used to deselect all other I/O peripherals which may erroneously be accessed as programmed I/O during the DMA operation. The
Am9517A automatically deselects itself by disabling the CS
input during DMA transfers.
ADSTB (Address Strobe, Output)
The active high Address Strobe is used to strobe the upper
address byte from DBO-DB7 into an external latch.
MEMR (Memory Read, Output)
The Memory Read signal is an active low three-state output
used to access data from the selected memory location during a
memory-to-peripheral or a memory-to-memory transfer.
Name
Size
Number
Base Address Registers
Base Word Count Registers
Current Address Registers
Current Word Count Registers
Temporary Address Register
Temporary Word Count Register
Status Register
Command Register
Temporary Register
Mode Registers
Mask Register
Request Register
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
8 bits
8 bits
8 bits
6 bits
4 bits
4 bits
4
4
4
4
1
1
1
1
1
4
1
1
Figure 2. Am9S17 A Internal Registers.
MEMW (Memory Write, Output)
The Memory Write signal is an active low three-state output
used to write data to the selected memory location during a
peripheral-to-memory or a memory-to-memory transfer.
FUNCTIONAL DESCRIPTION
The Am9517A block diagram includes the major logic blocks and
all of the internal registers. The data interconnection paths are
also shown. Not shown are the various control signals between
the blocks. The Am9517A contains 344 bits of internal memory
in the form of registers. Figure 2 lists these registers by name
and shows the size of each. A detailed description of the registers and their functions can be found under Register Description.
The Am9517A contains three basic blocks of control logic. The
Timing Control block generates internal timing and external
control signals for the Am9517A. The Program Command Control block decodes the various commands given to the Am9517A
by the microprocessor prior to servicing a DMA Request. It also
decodes each channel's Mode Control word. The Priority Encoder block resolves priority contention among DMA channels
requesting service simultaneously.
The Timing Control block derives internal timing from the clock
input. In Am9080A systems this input will usually be the tjJ2 TTL
clock from an Am8224. However, any appropriate system clock
will suffice.
DMA Operation
The Am9517A is designed to operate in two major cycles. These
are called Idle and Active cycles. Each device cycle is made up
of a number of states. The Am9517A can assume seven separate states, each composed of one full clock period. State 1 (S1)
is the inactive state. It is entered when the Am9517A has no
valid DMA requests pending. While in S1, the DMA controller is
inactive but may be in the Program Condition, being programmed by the processor. State 0 (SO) is the first state of a DMA
service. The Am9517A has requested a hold but the processor
has not yet returned an acknowledge. An acknowledge from the
CPU will signal that transfers may begin. S1, S2, S3 and S4 are
the working states of the DMA service. If more time is needed to
complete a transfer than is available with normal timing, wait
states (SW) can be inserted before S4 by the use of the Ready
line on the Am9517A.
Memory-to-memory transfers require a read-from and a
write-to-memory to complete each transfer. The states, which
resemble the normal working states, use two digit numbers for
identification. Eight states are required for each complete
transfer. The first four states (S11, S12, S13, S14) are used for
the read-from-memory half and the last four states (S21 , S22,
S23 and S24) for the write-to-memory half of the transfer. The
Temporary Data register is used for intermediate storage of the
memory byte.
IDLE Cycle
When no channel is requesting service, the Am9517A will enter
the Idle cycle and perform "S1" states. In this cycle the
Am9517A will sample the DREQ lines every clock cycle to determine if any channel is requesting a DMA service. The device
will also sample CS, looking for an attempt by the microprocessor to write or read the internal registers of the Am9517A. When
CS is low and HACK is low the Am9517A enters the Program
Condition. The CPU can now establish, change or inspect the
internal definition of the part by 'reading from or writing to the
internal registers. Address lines AO-A3 are inputs to the device
and select which registers will be read or written. The lOR and
lOW lines are used to select and time reads or writes. Due to the
7-137
Am9S17A
number and size of the internal registers, an internal flip/flop is
used to generate an additional bit of address. This bit is used to
determine the upper or lower byte of the 16-bit Address and
Word Count registers. The flip/flop is reset by Master Clear or
Reset. A separate software command can also reset this flip/
flop.
Special software commands can be executed by the Am9517A
in the Program Condition. These commands are decoded as
sets of addresses when both CS and lOW are active and do not
make use of the data bus. Functions include Clear First/Last
Flip/Flop and Master Clear.
signals of its own. These would conflict with the outputs of the
active channel in the added device. The Am9517A will respond
to DREQ with DACK but all other outputs except HREQ will be
disabled.
Figure 3 shows two additional devices cascaded into an initial
device using two of the previous channels. This forms a two
level DMA system. More Am9517As could be added at the second level by using the remaining channels of the first level.
Additional devices can also be added by cascading into the
channels of the second level devices forming a third level.
2ND LEVEL
ACTIVE CYCLE
When the Am9517A is in the Idle cycle and a channel requests a
DMA service, the device will output a HREQ to the microprocessor and enter the Active cycle. It is in this cycle that the DMA
service will take place, in one of four modes:
HOLD REO
Block Transfer Mode: In Block Transfer mode, the Am9517A
will continue making transfers until a TC (caused by the word
count going to zero) or an external End of Process (EOP) is
encountered. DREQ need be held active only until DACK becomes active. An autoinitialize will occur at the end of the service if the channel has been programmed for it.
Demand Transfer Mode: In Demand Transfer mode the device will continue making transfers until a TC or external EOP is
encountered or until DREQ goes inactive. Thus, the device requesting service may discontinue transfers by bringing DREQ
incfctive. Service may be resumed by asserting an active DREQ
once again. During the time between services when the microprocessor is allowed to operate, the intermediate values of address and word count may be read from the Am9517A Current
Address and Current Word Count registers. Autoinitialization will
only occur following a TC or EOP at the end of service. Following Autoinitialization, an active-going DREQ edge is required to
initiate a new DMA service.
Cascade Mode: This mode is used to cascade more than one
Am9517A together for simple system expansion. The HREQ and
HACK signals from the additional Am9517A are connected to
the DREQ and DACK signals of a channel of the initial
Am9517A. This allows the DMA requests of the additional device
to propagate through the priority network circuitry of the preceding device. The priority chain is preserved and the new device must wait for its turn to acknowledge requests. Since the
cascade channel in the initial device is used only for prioritizing
the additional device, it does not output any address or control
HREQ
DR EO
HREO
HACK
DACK
HACK
HOLD ACK
Single Transfer Mode: In Single Transfer mode, the Am9517A
will make a one-byte transfer during each HREQ/HACK handshake. When DREQ goes active, HREQ will go active. After the
CPU responds by driving HACK active, a one-byte transfer will
take place. Following the transfer, HREQ will go inactive, the
word count will be decremented and the address will be either
incremented or decremented. When the word count goes to zero
a Terminal Count (TC) will cause an Autoinitialize if the channel
has been programmed to do so.
To perform a single transfer, DREQ must be held active only
until the corresponding DACK goes active. If DREQ is held continuously active, HREQ will go inactive following each transfer
and then will go active again and a new one-byte transfer will be
made following each rising edge of HACK. In 8080A/9080A
systems this will ensure one full machine cycle of execution
between DMA transfers. Details of timing between the Am9517A
and other bus control protocols will depend upon the characteristics of the microprocessor involved.
Am9517A
1ST LEVEL
MICROPROCESSOR
Am9517A
DR EO
HREO
DACK
HACK
INITIAL DEVICE
Am9517A
ADDITIONAL
DEVICES
MOS·035
Figure 3. Cascaded Am9S17 As.
TRANSFER TYPES
Each of the three active transfer modes can perform three different types of transfers. These are Read, Write and Verify.
Write transfers move data from an I/O device to the memory by
activating lOR and MEMW. Read transfers move data from
memory to an I/O device by activating MEMR and lOW. Verify
transfers are pseudo transfers; the Am9517A operates as in
Read or Write transfers generating addresses, responding to
EOP, etc., however, the memory and I/O control lines remain
inactive.
Memory-to-Memory: The Am9517A includes a block move
capability that allows blocks of data to be moved from one memory address space to another. When Bit CO in the Command
register is set to a logical 1, channels 0 and 1 will operate as
memory-to-memory transfer channels. Channel 0 forms the
source address and channel 1 forms the destination address.
The channel 1 word count is used. A memory-to-memory transfer is initiated by setting a software DMA request for channel o.
Block Transfer Mode should be used for memory-to-memory.
When channel 0 is programmed for a fixed source address, a
single source word may be written into a block of memory.
When setting up the Am9517A for memory-to-memory operation, it is suggested that both channels 0 and 1 be masked out.
Further, the channel 0 word count should be initialized to the
same value used in channel 1. No DACK outputs will be active
during memory-to-memory transfers.
The Am9517A will respond to external EOP signals during
memory-to-memory transfers. Data comparators in block search
schemes may use this input to terminate the service when a
match is found. The timing of memory-to-memory transfers may
be found in Timing Diagram 4.
7-138
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37 Create Date : 2013:09:17 15:39:13-08:00 Modify Date : 2013:09:17 19:17:35-07:00 Metadata Date : 2013:09:17 19:17:35-07:00 Producer : Adobe Acrobat 9.55 Paper Capture Plug-in Format : application/pdf Document ID : uuid:9b889ba9-8bb8-ef4c-b413-9e97f092b7ad Instance ID : uuid:c9083a86-a4e5-c74e-8273-b66a2f4679cf Page Layout : SinglePage Page Mode : UseNone Page Count : 565EXIF Metadata provided by EXIF.tools