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1

Signetics

Linear
Data Manual
Volume 1:
Communications

Signetics

Linear Products

1987 linear
Data Manual
Volume 1:
Communications

Signetics reserves the right to make changes, without notice, in the products,
including circuits, standard 'cells, and/or software, described or contained herein in
order to improve design and/or performance. Signetics assumes no responsibility or
liability for the use of any of these products, conveys no license or title under any
patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work
right infringement, unless otherwise specified. Applications that are described herein
for any of these products are for illustrative purposes only. Signetics makes no
representation or warranty that such applications will be suitable for the specified use
without further testing or modification.
LIFE SUPPORT APPLICATIONS
Signetics' Products are not designed for use in life support appliances, devices, or
systems where malfunction of a Signetics Product can reasonably be expected to
result in a personal injury. Signetics' customers using or selling Signetics' Products
for use in such applications do so at their own risk and agree to fully indemnify
Signetics for any damages resulting in such improper use or sale.

Signetics registers eligible circuits under
the Semiconductor Chip Protection Act.

@ Copyright 1987 Signetics Corporation

All rights reserved.

Signetics

Preface

Linear Products

The Linear Division, one of four
Signetics product divisions, is a major
supplier of a broad line of linear integrated circuits ranging from high performance application specific designs to
many of the more popular industry standard devices.
A fifth Signetics division, the Military
Division, provides military-grade integrated circuits, including Linear. Please consult the Signetics Military data book for
information on such devices.
Employing Signetics' high quality processing and screening standards, the
Linear Division is dedicated to providing
high-quality linear products to our customers worldwide.
The three 1987 Linear Data and Applications Manuals provide extensive technical data and application information for a

February 1987

broad range of products serving the
needs of a wide variety of markets.

Volume 1 -

Communications:

Contains data and application information concerning our radio and audio
circuits, compandors, phase-locked
loops, compact disc circuits, and ICs for
RF communication, telephony and modem applications.

Volume 2 -

Industrial:

Contains data and application information concerning our data conversion
products (analog-to-digital and digital-toanalog), sample-and-hold circuits, comparators, driver/receiver ICs, amplifiers,
position measurement devices, power
conversion and control ICs and music/
speech synthesizers.

includes tuning, video IF and audio IF
Circuits, sync processors/ generators,
color decoders and encoders, video processing ICs, vertical deflection circuits,
Videotex and Teletext ICs and power
supply controllers for video applications.
Each volume contains extensive product-specific application information. In
addition there are selector guides and
product-specific symbols and definitions
to facilitate the selection and understanding of Linear products. A functional
Table of Contents for each of the three
volumes and a complete product and
application note listing is also included.

Volume 3 - Video:

Although every effort has been made to
ensure the accuracy of information in
these manuals, Signetics assumes no
liability for inadvertent errors.

Contains data and application information concerning our video products. This

Your suggestions for improvement in
future editions are welcome.

iii

Signetics

Product Status

Linear Products

DEFINITIONS
Data Sheet
Identification

Product Status

Definition
This data sheet contains the design target or goal

Objecllve Speclflcallon

FormaUve or In Design

Preliminary SpecIfication

Preproduction Product

Product Spec/f/cstlon

Full Production

specifications for product development. Specifications may
change in any manner without notice.
This data sheet contains preliminary data and supplementary

data will be pUblished at a later date. Signetics reserves the
right to make changes at any time'without notice in order to
improve design and supply the best possible product.

This data sheet contains Final Specifications. Signetics
reserves the right to make changes at any time without
notice in order to improve design and supply the bost

possible product.

February 1967

iv

Signetics

Volume 1
Communications

Linear Products

Preface
Product Status
Section 1:

GENERAL INFORMATION

Section 2:

QUALITY AND RELIABILITY

Section 3:

12 C SMALL AREA NETWORKS

Section 4:

RF COMMUNICATIONS
Signal Processing
Frequency Synthesis
Phase-Locked Loops
Compandors

Section 5:

DATA COMMUNICATIONS
Line Drivers/Receivers
Modems
Fiber Optics

Section 6:

TELECOMMUNICATIONS
Compandors
Phase-Locked Loops
Telephony

Section 7:

RADIOIAUDIO
Radio Circuits
Audio Circuits
Compact Disk

Section 8:

SPEECHI AUDIO SYNTHESIS

Section 9:

PACKAGE INFORMATION

Section 10: SALES OFFICES

February 1987

v

Signetics

Section 1
General Information

Linear Products

INDEX

Contents of Volume 1, COMMUNiCATIONS ........................................................1-3
Alphanumeric Listing of all Linear Products ........................................................1-8
Application Note Listing
- by Product Group ................................................................................... 1-14
-by Part Number ..................................................................................... 1-17
Outline of Contents of Volume 2, INDUSTRIAL ................................................. 1-20
Outline of Contents of Volume 3, ViDEO ......................................................... 1-21
Cross Reference Guide by Company .............................................................. 1-22
SO Availability List ...................................................................................... 1-25
Ordering Information .................................................................................... 1-27

Signetics

Volume 1:
Communications
Contents

Linear Products

Preface ............................................................................................................................... .... . .. .. .. .. . . .. .. .. . . . . . . . . .
Product Status......................................................................................................................... ... .. .. .. . . . . .. . . . . .. . . . . .
Outline of Contents ............................................................................................................................... . . . . . . .. . . . . .

iii
iv
v

Section 1 - General Information
Contents of Volume 1, COMMUNICATIONS ...............................................................................................................
Alphanumeric Listing of all Linear Products................................................................................................................
Application Note Listing
- by Product Group ............................................................................................................................... .. ...... .. ...
- by Part Number ...............................................................................................................................................
Outline of Contents of Volume 2, INDUSTRIAL ..........................................................................................................
Outline of Contents of Volume 3, VIDEO ......................................................................... .........................................
Cross Reference Guide by Company....................................................................................................................... .
SO Availability List ...............................................................................................................................................
Ordering Information .............................................................................................................................................

1-3
1-8
1-14
1-17
1-20
1-21
1-22
1-25
1-27

Section 2 - Quality and Reliability
Quality and Reliability.................................................................................................................... ........................

2-3

Section 3 - Small Area Networks
SMALL AREA NETWORKS

Introduction to 12C................................................................................................................................................
3-3
12C Bus Specification................................................................................................................. ...........................
3-4
AN168
The Inter-Integrated Circuit (12C) Serial Bus: Theory and Practical Considerations .................................. 3-16
PCF21DD
4-Segment LCD Duplex Driver .................................................................................................... (Vol 2)
PCF2111
64-Segment LCD Duplex Driver .................................................................................................. (Vol 2)
PCF2112
32-Segment LCD Static Driver .................................................................................................... (Vol 2)
PCF82DD
Single-Chip CMOS Male/Female Speech Synthesizer.......................................................................
8-6
PCF857D
256 X 8 Static RAM .................................................................................................................(Vol 3)
PCF8571
1k Serial RAM ........................................................................................................................ (Vol 3)
PCF8573
Clock/Timer With 12C Interface ............................................................................................... (Vol 2, 3)
PCF8574
8-Bit Remote I/O Expander ................................................................................................... (Vol 2, 3)
PCF8576
Universal LCD Driver for Low Multiplex Rates ................................................................................ (Vol 2)
PCF8577
32-/64-Segment LCD Driver for Automotive ................................................................................... (Vol 2)
PCF8591
8-Bit A/D and D/A Converter ..................................................................................................... (Vol 2)
SAA1D57
PLL Radio Tuning Circuit ................. , ......................................................................................... 4-193
SAA1060
32-Segment LED Driver .............................................................................................................(Vol 2)
SAA1061
16-Segment LED Driver .............................................................................................................(Vol 2)
SAA3028
IR Receiver ............................................................................................................................(Vol 3)
SAS3013
6-Function Analog Memory (6-Bit D/ A Converter) ........................................................................... (Vol 3)
SAS3035
FLL TV Tuning Circuit (Eight D/ A Converters) ............................................................................... (Vol 3)
SAS3036
FLL TV Tuning Circuit ..............................................................................................................(Vol 3)
SAS3037
FLL TV Tuning Circuit (Four D/ A Converters) ................................................................................ (Vol 3)
TDAI540P,D
14-Bit D/A Converter-Serial Input.. ........................................................................................... 7-355
TDA8400
Frequency Synthesizer.............................................................................................................. 4-220
TDA8440
AudiolVideo Switch.................................................................................................................. 7-210
TDA8442
I/O Expander ..........................................................................................................................(Vol 3)
TDA8443
RGB/YUV Matrix Switch ............................................................................................................(Vol 3)
TEA1017
13-Bit Series-to-Parallel Converter ................................................................................................ (Vol 2)
TEA6000
FM IF System and Computer Interface Circuit ................................................................................ 7-104

February 1987

1-3

Signetics Linear Products

Contents

Volume 1: Communications

Section 4 - RF Communications
RF SIGNAL PROCESSING
Amplifiers
NE/SA5204
NE/SA/SE5205
NE/SE5539
AN140
NE5592
NE/SE592
AN141

Wide-band High Frequency Amplifier............................................................................................
Wide-band High Frequency Amplifier............................................................................................
Ultra-High Frequency Operational Amplifier....................................................................................
Compensation Techniques for Use With the NE/SE5539............................ ............. ..................... ....
Video Amplifier..................................................................................................................... .. .
Video Amplifier..................................................................................................................... . ..
Using the NE/SE592 Video Amplifier ...................................................... ................... ..................

4-3
4-14
4-26
4-34
4-40
4-46
4-55

Mixer/Modulators/Demodulators
Balanced Modulator/Demodulator ................................................................................................ 4-60
MC1496/1596
AN189
Balanced Modulator/Demodulator Applications Using the MC1496/MC1596 .......................................... 4-64
NE602
Double-Balanced Mixer and Oscillator........................................................................................... 4-69
AN198
Designing With the NE/SA602.................................................................................................... 4-75
AN1981
New Low Power Single Sideband Circuits (NE602) ......................................................................... 4-79
Applying the Oscillator of the NE602 in Low Power Mixer Applications. ................................... ........... 4-87
AN1982
NE612
Low Power VHF Mixer/Oscillator ................................................................................................. 4-90
TDA 1574
FM Front-End IC (VHF Mixer and Oscillator) ............................................ ..................... ................ 4-96
TDA5030A
VHF Mixer-Oscillator (VHF Tuner IC) ............................................................................................ 4-102
TDA5230
VHF, Hyperband, and UHF Mixer/Oscillator With IF Amp ................................................................. 4-106
IF Systems
CA3089
MC3361
NE604
AN199
AN1991
NE605
NE614
TDA1576

FM IF System .........................................................................................................................
Low Power FM IF ....................................................................................................................
Low Power FM IF System.........................................................................................................
Designing With the NE/SA602....................................................................................................
Audio Decibel Level Detector With Meter Driver.............................................................................
Low Power FM IF System .................................................................................... ;....................
Low Power FM IF System .........................................................................................................
FM-IF (Quadrature Detector).......................................................................................................

4-110
4-116
4-119
4-130
4-140
4-142
4-146
4-156

Slngle·Chip Receivers
NE605
Low Power FM IF System......................................................................................................... 4-142
TDA7000
Single-Chip FM Radio Circuit...................................................................................................... 7-49
TDA7010
Single-Chip FM Radio Circuit (SO Package) .................... .............................................................. 7-85
FREQUENCY SYNTHESIS
Prescalers
SAB1164/65
SAB1256

1GHz Divide-by-64 Prescaler...................................................................................................... 4-163
1GHz Divide-by-256 Prescaler..................................................................................................... 4-168

Synthesizers
HEF4750V
HEF4751V
SAA1057
AN196
AN197
TDA8400
TDD1742

Frequency Synthesizer..............................................................................................................
Universal Divider......................................................................................................................
PLL Radio Tuning Circuit .................................. ;........................................................................
Single-Chip Synthesizer for Radio Tuning......................................................................................
Analysis and Basic Application of the SM 1057 (PLL Radio Tuning)...................................................
FLL Tuning Circuit with Prescaler................................................................................................
CMOS Frequency Synthesizer.....................................................................................................

4-174
4-184
4-193
4-201
4-208
4-220
4-226

PHASE·LOCKED LOOPS
AN177
An Overview of the Phase-Locked Loop (PLL) ............................................................................... 4-236
Modeling the PLL ...................................................................................................................; 2-241
AN178
NE/SE564
Phase-Locked Loop.................................................................................................................. 2-257
AN179
Circuit Description of the NE564 ................................................................................................. 4-266
AN180
Frequency Synthesis With the NE564 .......................................................................................... 4-273
AN1801
10.8MHz FSK Decoder With the NE564 ....................................................................................... 4-277
AN181
A 6MHz FSK Converter Design Example for the NE564 .................................................................. 4-280
AN182
Clock Regenerator With Crystal-Controlled Phase-Locked veo (NE564) ............................................... 4-282
NE/SE565
Phase-Locked Loop ............................................. ;.................................................................... 4-291
AN183
Circuit Description of the NE565 PLL. .......................................................................................... 4-297
AN184
Typical Applications With NE565.... .................................. ........................ .................... ...... ......... 4-301
NE/SE566
Function Generator.................................................................................................................. 4-304
AN185
Circuit Description of the NE566 ................................................................................................. 4-309
AN186
Waveform Generators With the NE566 ......................................................................................... 4.-310
February 1987

1·4

Signetics Linear Products

Volume 1: Communications

Contents

NE/SE567
AN187
AN188
NE568

Tone Decoder/Phase-Locked Loop ..............................................................................................
Circuit Description of the NE567 Tone Decoder .............................................................................
Selected Circuits Using the NE567 ..............................................................................................
150MHz Phase-Locked Loop......................................................................................................

4-313
4-325
4-330
4-333

COMPANDORS
AN174
AN176
NE570/SA571
NE/SA572
AN 175
NE575

Applications for Compandors: NE570/571/SA571............................................................................
Compandor Cookbook ...............................................................................................................
Compandor .... ......................... ............... .......... ...................................................... .... .............
Programmable Analog Compandor...............................................................................................
Automatic Level Control Using the NE572 .....................................................................................
Low Voltage Compandor ...........................................................................................................

4-341
4-350
4-357
4-364
4-372
4-373

Section 5 - Data Communications
LINE DRIVERS/RECEIVERS
Symbols and Definitions for Line Drivers...................................................................................................................
MC1488
Quad Line Driver.............................................. .......................................................................
MC1489/A
Quad Line Receivers ......................................... .......................................................................
ANl13
Using the MC1488/1489 Line Drivers and Receivers.......................................................................
NE5170
Octal Line Driver .....................................................................................................................
NE5l80/8l
Octal Line Receiver..................................................................................................................

5-3
5-4
5-8
5-11
5-14
5-21

MODEMS
NE5050
AN1951
NE5080
NE5081
AN195
AN1950

Power Line Modem..................................................................................................................
NE5050: Power Line Modem Application Board Cookbook................................................................
High-Speed FSK Modem Transmitter (IEEE 802.4)... .................... .................... ...............................
High-Speed FSK Modem Receiver (IEEE 802.4) .............................................. ...............................
Applications Using the NE5080/5081 ............................................ ............ .................. .................
Application of NE5080 and NE5081 With Frequency Deviation Reduction ............................................

5-26
5-30
5-44
5-48
5-52
5-60

FIBER OPTICS
NE/SA/SE5212
NE568

Transimpedance Amplifier .......................................................................................................... 5-63
150MHz Phase-Locked loop...................................................................................................... 4-333

Section 6 - Telecommunications
COMPANDORS
AN 174
AN 176
NE570/5711SA571
NE/SA572
AN175
NE575

Applications for Compandors: NE570/571/SA571 ............................................................................
Compandor Cookbook...............................................................................................................
Compandor. ............................................................................................................................
Programmable Analog Compandor...............................................................................................
Automatic Level Control Using the NE572 .....................................................................................
Low Voltage Compandor ...........................................................................................................

4-341
4-350
4-357
4-364
4-372
4-373

PHASE-LOCKED LOOPS
AN 177
An Overview of the Phase-Locked Loop (PLL)...............................................................................
AN 178
Modeling the PLL ....................................................................................................................
NE/SE564
Phase-Locked Loop..................................................................................................................
AN 179
Circuit Description of the NE564 .................................................................................................
AN180
Frequency Synthesis With the NE564 ..........................................................................................
AN1801
10.8MHz FSK Decoder With the NE564 .......................................................................................
A 6MHz FSK Converter Design Example for the NE564 ..................................................................
AN181
Clock Regenerator With Crystal-Controlled Phase-locked veo (NE564)...............................................
AN182
Phase-Locked Loop..................................................................................................................
NE/SE565
AN183
Circuit Description of the NE565 PLL...........................................................................................
Typical Applications With NE565.................................................................................................
AN184
Function Generator..................................................................................................................
NE/SE566
AN185
Circuit Description of the NE566.................................................................................................
AN186
Waveform Generators With the NE566 .........................................................................................
Tone Decoder/Phase-Locked Loop..............................................................................................
NE/SE567
AN187
Circuit Description of the NE567 Tone Decoder .............................................................................
AN188
Selected Circuits Using the NE567 ..............................................................................................
NE568
150MHz Phase-Locked Loop......................................................................................................

4-236
4-241
4-257
4-266
4-273
4-277
4-280
4-282
4-291
4-297
4-301
4-304
4-309
4-310
4-313
4-325
4-330
4-333

TELEPHONY
NE5900
PCD3310
PCD33l1133l2
PCD3315
PCD3360
February 1987

Call Progress Decoder..............................................................................................................
Pulse and DTMF Dialer With Redial ............................................................................................
DTMF/Modem/Musical Tone Generator .......................................................................... ..............
CMOS Redial and Repertory Dialer .............................................................................................
Programmable Multi-Tone Telephone Ringer ..................................................................................

1-5

6-3
6-10
6-24
6-37
6-45

•

Signetics Linear Products

Contents

Volume 1: Communications

TEA1046A
TEA1060/61
TEA1067
AN1942
AN1943
TEA1068
TEA1075
TEA1080

Transmission Interface With DTMF ..............................................................................................
Versatile Telephone Transmission Circuits With Dialer Interface .. , ......................................................
Low Voltage Transmission IC With Dialer Interface .........................................................................
Application of the Low Voltage Versatile Transmission Circuit........ ....................................................
Supply of Peripheral Circuits With the TEAt067 Speech Circuit .........................................................
Versatile Telephone Transmission Circuit .......................................................................................
DTMF Generator for Telephone Dialing ........................................................................................
Supply IC for Telephone Set Peripherals ......................................................................................

6-53
6-65
6-76
6-88
6-108
6-114
6-125
6-135

Section 7 - Radiol Audio
RADIO CIRCUITS
AM Radio
TDA1072A
AN1961
TEA5550
TEA5570

AM Receiver Circuit.................................................................................................................
Integrated AM TDA 1072A Receiver..............................................................................................
AM Radio Circuit.....................................................................................................................
AM/FM Radio Receiver Circuit ...................................................................................................

7-3
7-15
7 -26
7-34

FM Radio
CA3089
NE602
AN198
AN1981
AN 1982
NE604
AN199
AN1991
NE612
NE614
TDA1001B
TDA1574
TDA1576
TDA7000
AN192
AN193
TDA7010
TDA7021
TEA5560
TEA5570
TEA6000

FM IF System .........................................................................................................................
Double-Balanced Mixer and Oscillator...........................................................................................
Designing With the NE/SA602................................................ ....................................................
New Low-Power Single Sideband Circuits (NE602)...................... ....................................................
Applying the Oscillator of the NE602 in Low-Power Mixer Applications................................................
Low-Power FM IF System .........................................................................................................
Designing With the NE/SA602....................................................................................................
Audio Decibel Level Detector With Meter Driver (NE604) .................................................................
Low Power VHF Mixer/Oscillator.................................................................................................
Low Power FM IF System .........................................................................................................
Interference Suppressor.............................................................................................................
FM Front-End IC (VHF Mixer and Oscillator) .................................................................................
FM-IF System (Quadrature Detector) ............................................................................................
Single-Chip FM Radio Circuit......................................................................................................
A Complete FM Radio on a Chip ...............................................................................................
TDA7000 for Narrow Band FM Reception.....................................................................................
FM Radio Circuit (SO Package) ..................................................................................................
Single-Chip FM Radio Circuit......................................................................................................
FMIIF System........................................................................................................................ .
AM/FM Radio Receiver Circuit ...................................................................................................
FM IF System and Computer Interface (MUSTI) Circuit. ...................................................................

4-110
4-69
4-75
4-79
4-87
4-119
4-130
4-140
4-90
4-146
7-43
4-96
4-156
7-49
7-54
7-69
7-85
7-90
7-96
7-34
7-104

Stereo Decoders
LM1870
TDA1005A
TDA1578A
TDA7040
TEA5580
TEA5581
",,758
AN191

Stereo Demodulator With Blend ........................................................................................... ;......
Frequency Multiplex PLL Stereo Decoder......................................................................................
PLL Stereo Decoder.................................................................................................................
PLL Stereo Decoder (Low Voltage) .............................................................................................
PLL Stereo Decoder.................................................................................................................
PLL Stereo Decoder.................................................................................................................
FM Stereo Multiplex Decoder Phase-Locked Loop..........................................................................
Stereo Decoder Applications Using the p.A758 .............................. ; ................................................

7-114
7-119
7-129
7-138
7-144
7-147
7-154
7-159

Digital Tuning Circuits
SAA1057
PLL Radio Tuning Circuit ........................................................................................................... 4-193
Single-Chip Synthesizer for Radio Tuning ...................................................................................... 4-201
AN196
AN197
Analysis and Basic Application of the SAA 1057 (PLL Radio Tuning) ................................................... 4-208
AUDIO CIRCUITS
Preamplifiers
NE542
AN190
TDA1522

Dual Low-Noise Preamplifier ... , ........ ,.......................................................................................... 7-167
Applications of Low-Noise Stereo Amplifiers: NE542 ........................................................................ 7-171
Stereo Cassette Preamplifier ...................................................... , ............................................... 7-174

Tone/Volume/Switching
TDA 1029
Stereo Audio Switch.................................................................................................................
TDA 1074A
DC-Controlled Dual Potentiometers ..............................................................................................
TDA1524A
Stereo-TonelVolume Control Circuit .............................................................................................
TDA3810
Spatial, Stereo, Pseudo-Stereo Processor ......................................................................................
Video/Audio Switch ..................................................................................................................
TDA8440
12C Active Tone Controlier With Source Inputs and Fader ................................................................
TEA6300
February 1987

1·6

7-180
7-189
7-196
7-204
7-210
7-216

Signetics Linear Products

Volume 1: Communications

Contents

II
I

Dolby
NE5240
NE645/646
NE648/649
NE650

Dolby Digital Audio Decoder.......................................................................................................
Dolby Noise Reduction Circuit..................................................................... ...............................
Low Voltage Dolby Noise Reduction Circuit...................................................................................
Dolby B-Type Noise Reduction Circuit ..........................................................................................

7-226
7-230
7-235
7-240

Power Amplifiers
Symbols and Definitions for Audio Power Amplifiers.....................................................................................................
TDA1010A
6W Audio Amplifier With Preamplifier ...........................................................................................
TDA1011A
2 to 6W Audio Power Amplifier With Preamplifier ...........................................................................
TDA1013A
4W Audio Amplifier With DC Volume Control .................................................................................
AN148
Audio Amplifier With TDA 1013A ...... ..... ........................ ...............................................................
TDA1015
1 to 4W Audio Amplifier With Preamplifier....................................................................................
TDA1020
12W Audio Amplifier With Preamplifier..........................................................................................
TDA1510
2 X 12W Audio Amplifier...........................................................................................................
AN1491
Car Radio Audio Power Amplifier up to 24W With the TDA1510 .......................................................
12 to 20W Audio Amplifier ........................................................................................................
TDA1512
40W High-Performance Hi-Fi Amplifier ..........................................................................................
TDA1514
24W BTL Audio Amplifier........................................................................ ..................................
TDA1515A
Car Radio Audio Power Amplifiers up to 20W With the TDA 1515 ............ ......... .................................
AN1481
TDA1520A
20W Hi-Fi Audio Amplifier ..........................................................................................................
AN149
20W Hi-Fi Power Amplifier With the TDA1520A ..............................................................................
TDA1521
2 X 12 Hi-Fi Audio Power Amplifier.............................................................................................
5W Audio Amplifier................................................................. ........... ......................................
TDA2611A
TDA7050
Low Voltage Mono/Stereo Power Amplifier.................................................. .... ..............................

7-245
7-246
7-251
7-255
7-256
7-267
7-272
7-276
7-260
7-266
7-293
7-296
7-300
7-307
7-312
7-317
7-322
7-326

COMPACT DISK
SAA7210
SAA7220
TDA1540
TDA1541
TDA5708
TDA5709

7-329
7-343
7-355
7-360
7-366
7-366

Decoder for Compact Disk Digital Audio System.......................................... ..................................
Digital Filter for Compact Disk Digital Audio System........................................................................
14-Bit DAC (Serial Output).........................................................................................................
16-Bit Dual D/ A Converter - Serial Output.................................................. ..................................
Photo Diode Signal Processor....................................................................................................
Radial Error Signal Processor................................................................... ..................................

Section 8 - Speech! Audio Synthesis
OM8210
PCD3311/3312
PCF8200
SAA1099

Section 9 -

Speech Encoding and Editing System ..........................................................................................
DTMF/Modem/Musical Tone Generator ........................................................................................
Single-Chip CMOS Male/Female Speech Synthesizer.......................................................................
Stereo Sound Generator for Sound Effects and Music Synthesis .......................................................

6-3
6-24
6-6
6-16

Packaging Information

Substrate Design Guidelines for Surface Mounted Devices............................................................................................
Test and Repair.......... .................. .............................................................. ....................... ..................................
Fluxing and Cleaning ............................................................................................................................................
Thermal Considerations for Surface-Mounted Devices...................................................................................................
Package Outlines for Prefixes ADC, AM, CA, DAC, LF, LM, MC, NE, SA, SE, SG, 1lA, and ULN .........................................
Package Outlines for Prefixes HEF, OM, MEA, PCD, PCF, PNA, SAA, SAB, SAF, TBA, TCA, TDA, TDD and TEA...................

9-3
9-14
9-17
9-22
9-35
9-52

Section 10 - Sales Office Listings
Sales Office Listings .......................................................................................................................... " . . . . . . . . .. . .. .. . .

February 1967

1-7

10-3

Signetics

Alphanumeric
Product List

Linear Products

Vol 1
ADC0801 /2/3/4/5
ADC0820
AM6012
CA3089
DAC-08 Series
DAC800
HEF4750V
HEF4751V
ICM7555
LF198
LF298
LF398
LMlll
LMl19
LM124
LM139/A
LM158
LM193/A
LM211
LM219
LM224
LM239/A
LM258
LM293/A
LM311
LM319
LM324
LM339/A
LM358
LM393/A
LM1870
LM2901
LM2903
MC1408-7
MC1408-8
MC1458
MC1488
MC1489/A
MC1496
MC1508-8
MC1558
MC3302
MC3303
MC3361
MC3403
MC341 0
MC3410C
MC3503
MC351 0
NE/SE521
NE/SE522
NE/SE527
NE/SE529
NE/SE530
NE/SE531
February 1987

8-Bit CMOS AID Converter
8-Bit CMOS AID Converter
12-Bit Multiplying 0/ A Converter
FM IF System
8-Bit High-Speed Multiplying 0/ A Converter
12-Bit 0/ A Converter
Frequency Synthesizer
Universal Divider
CMOS Timer
Sample-and-Hold Amplifier
Sample-and-Hold Amplifier
Sample-and-Hold Amplifier
Voltage Comparator
Dual Voltage Comparator
Low Power Quad Operational Amplifier
Quad Voltage Comparator
Low Power Dual Operational Amplifier
Low Power Dual Voltage Comparator
Voltage Comparator
Dual Voltage Comparator
Low Power Quad Operational Amplifier
Quad Voltage Comparator
Low Power Dual Operational Amplifier
Low Power Dual Voltage Comparator
Voltage Comparator
Dual Voltage Comparator
Low Power Quad Operational Amplifier
Quad Voltage Comparator
Low Power Dual Operational Amplifier
Low Power Dual Voltage Comparator
Stereo Demodulator With Blend
Quad Voltage Comparator
Low Power Dual Voltage Comparator
8-Bit Multiplying 0/ A Converter
8-Bit Multiplying 0/ A Converter
General Purpose Operational Amplifier
Quad Line Driver
Quad Line Receivers
Balanced Modulator/Demodulator
8-Bit Multiplying 0/ A Converter
General Purpose Operational Amplifier
Quad Voltage Comparator
Quad Low Power Operational Amplifier
Low Power FM IF
Quad Low Power Operational Amplifier
10-Bit High-Speed Multiplying 0/ A Converter
10-Bit High-Speed Multiplying 0/ A Converter
Quad Low Power Operational Amplifier
10-Bit High-Speed Multiplying 0/ A Converter
High-Speed Dual Differential Comparator/Sense Amp
High-Speed Dual Differential Comparator/Sense Amp
Voltage Comparator
Voltage Comparator
High Slew Rate Operational Amplifier
High Slew Rate Operational Amplifier

1-8

Vol 2

5-11
5-18
5-100
4-110
5-111
5-124
4-174
4-184
7-3
5-317
5-317
5-317
5-254
5-257
4-29
5-263
4-123
5-271
5-254
5-257
4-29
5-263
4-123
5-271
5-254
5-257
4-29
5-263
4-123
5-271
7-114

5-4
5-8
4-60

5-263
5-271
5-130
5-130
4-34
6-4
6-8
5-130
4-34
5-263
4-40

4-116
4-40
5-136
5-136
4-40
5-136
5-285
5-290
5-296
5-301
4-53
4-60

Vol 3

Signetics linear Products

Alphanumeric Product list

Vol 1
NE/SA532
NE/SE538
NE542
NE544
NE/SE555
NE/SA/SE556/1
NE/SAlSE558
NE/SE564
NE/SE565
NE/SE566
NE/SE567
NE568
NE570
NE/SA571
NE/SA572
NE575
NE587
NE589
NE590
NE591
NE/SE592
NE/SA594
NE602
NE604
NE605
NE612
NE614
NE645
NE646
NE648
NE649
NE650
NE/SE4558
NE/SE5018
NE/SE5019
NE5020
NE/SE5030
NE5034
NE5036
NE5037
NE5044
NE5045
NE5050
NE5060
NE5080
NE5081
NE5090
NE/SAlSE51 05/ A
NE/SE5118
NE/SE5119
NE5150
NE5151
NE5152
NE5170
NE5180
NE5181
NE5204
NE/SAlSE5205
NE/SA5212
NE/SA5230
NE5240
NE/SE5410
NE/SE5512
February 1987

Low Power Dual Operational Amplifier
High Slew Rate Operational Amplifier
Dual Low-Noise Preamplifier
Servo Amplifier
Timer
Dual Timer
Quad Timer
Phase-Locked Loop
Phase-Locked Loop
Function Generator
Tone Decoder/Phase-Locked Loop
150MHz Phase-Locked Loop
Compandor
Compandor
Programmable Analog Compandor
Low Voltage Compandor
LED Decoder/Driver
LED Decoder/Driver
Addressable Peripheral Drivers
Addressable Peripheral Drivers
Video Amplifier
Vacuum Fluorescent Display Driver
Low Power VHF Mixer/Oscillator
Low Power FM IF System (Independent IF Amp)
Low Power FM IF System
Low Power VHF Mixer/Oscillator
Low Power FM IF System (Independent IF Amp)
Dolby Noise Reduction Circuit
Dolby Noise Reduction Circuit
Low Voltage Dolby Noise Reduction Circuit
Low Voltage Dolby Noise Reduction Circuit
Dolby B-Type Noise Reduction Circuit
Dual General Purpose Operational Amplifier
8-Bit Microprocessor-Compatible D/ A Converter
8-Bit Microprocessor-Compatible D/ A Converter
10-Bit Microprocessor-Compatible D/A Converter
10-Bit High-Speed Microprocessor-Compatible AID
8-Bit High-Speed AID Converter
6-Bit A/ D Converter (Serial Output)
6-Bit A/D Converter (Parallel Outputs)
Programmable Seven-Channel RC Encoder
Seven-Channel RC Decoder
Power Line Modem
Sample-and-Hold Circuit
High-Speed FSK Modem Transmitter
High-Speed FSK Modem Receiver
Addressable Relay Driver
12-Bit High-Speed Comparator
8-Bit Microprocessor-Compatible D/ A Converter
8-Bit Microprocessor-Compatible D/ A Converter
RGB Video D/ A Converter
RGB Video D/ A Converter
RGB Video D/ A Converter
Octal Line Driver
Octal Line Receiver
Octal Line Receiver
Wideband High Frequency Amplifier
Wideband High Frequency Amplifier
Transimpedance Amplifier
Low Voltage Operational Amplifier
Dolby Digital Audio Decoder
10-Bit High-Speed Multiplying D/A Converter
Dual High Performance Operational Amplifier

1-9

Vol 2

Vol 3

4-123
4-68
7-167
8-34
7-47
7-32
7-38
4-257
4-291
4-304
4-313
4-333
4-357
4-357
4-364
4-373

4-46
4-69
4-119
4-142
4-90
4-146
7-230
7-230
7-235
7-235
7-240

11-6

6-49
6-59
6-34
6-34
4-231
6-74

11-109

4-178

4-201

4-48
5-144
5-150
5-156
5-31
5-36
5-43
5-50
8-4
8-16
5-26
5-322
5-44
5-48

5-14
5-21
5-21
4-3
4-14
5-63

6-28
5-277
5-164
5-169
5-181
5-181
5-181
6-14
6-21
6-21
4-155
4-166
4-267
4-109

7-226
5-208
4-75

11-25
11-25
11-25

11-66
11-77

Signetics Linear Products

Alphanumeric Product List

Vol 1
NE/SE5514
NE5517/A
NE5520
NE/SE5521
NE/SE55321 A
NE5533/A
NE5534A
NE/SE5535
NE/SE5537
NE/SE5539
NE/SE5560
NE/SE5561
NE/SA/SE5562
NE5568
NE/SAlSE5570
NE5592
NE5900
OM8210
PCD3310
PCD3311
PCD3312
PCD3315
PCD3360
PCF1303
PCF2100
PCF2111
PCF2112
PCF8200
PCF8566
PCF8570
PCF8571
PCF8573
PCF8574
PCF8576
PCF8577
PCF8582
PCF8591
PNA7509
PNA7518
SA532
SA534
SA55611
SA558
SA571
SA572
SA594
SA723C
SA741C
SA747C
SA1458
SA5205
SA5212
SA5230
SA5534A
SA5562
SA5570
SAA1027
SAA1057
SAA1060
SAA1061
SAA1099
SAA3004,T
SAA3006
February 1987

Quad High Performance Operational Amplifier
Dual Operational Transconductance Amplifier
LVDT Signal Conditioner
LVDT Signal Conditioner
Internally-Compensated Dual Low-Noise Operational Amp
Single and Dual Low-Noise Operational Amp
Single and Dual Low-Noise Operational Amp
Dual High Slew Rate Op Amp
Sample-and-Hold Amplifier
Ultra· High Frequency Operational Amplifier
Switched-Mode Power Supply Control Circuit
Switched-Mode Power Supply Control Circuit
SMPS Control Circuit, Single Output
Switched-Mode Power Supply Controller
Three-Phase Brushless DC Motor Driver
Video Amplifier
Call Progress Decoder
Speech Encoding and Editing System
Pulse and DTMF Dialer With Redial
DTMF/Modem/Musical Tone Generator
DTMF/Modem/Musical Tone Generator
CMOS Redial and Repertory Dialer
Programmable Multi-Tone Telephone Ringer
18-Element LCD Bar Graph LCD Driver
LCD Duplex Driver
LCD Duplex Driver
LCD Driver
Single-Chip CMOS Male/Female Speech Synthesizer
Universal LCD Driver for Low Multiplex Rates
256 X 8 Static RAM
IK Serial RAM
Clock/Calendar With Serial I/O
8-Bit Remote I/O Expander
Universal LCD Driver for Low Multiplex Rates
32/64 Segment LCD Driver for Automotive
12 C CMOS EPROM (256 X 8)
8-Bit AID and DI A Converter
7 -Bit AID Converter
8-Bit Multiplying DAC
Low Power Dual Operational Amplifier
Low Power Quad Operational Amplifier
Dual Timer
Quad Timer
Compandor
Programmable Analog Compandor
Vacuum Fluorescent Display Driver
Precision Voltage Regulator
General Purpose Operational Amplifier
Dual Operational Amplifier
General Purpose Operational Amplifier
Wide-band High Frequency Amplifier
Transimpedance Amplifier
Low Voltage Operational Amplifier
Single and Dual Low-Noise Operational Amp
SMPS Control Circuit, Single Output
Three-Phase Brushless DC Motor Driver
Stepper Motor Driver
PLL Radio Tuning Circuit
LED Display Interface
Output Port Expander
Stereo Sound Generator for Sound Effects and Music
IR Transmitter (448 Commands)
IR Transmitter (2K Commands, Low Voltage)

1-10

4-26

4-40
6-3
8-3
6-10
6-24
6-24
6-37
6-45

Vol 2
4-81
4-251
5-338
5-358
4-87
4-93
4-93
4-129
5-327
4-211
8-67
8-86
8-97
8-129
8-45
4-225

Vol 3

11-89

11-103

6-79
6-83
6-90
6-95
8-6
6-100

7-12
7-24
6-120
6-141

4-3
4-12
4-21
4-33

4-41
5-59
5-71
5-217
4-123
4-29
7-32
7-38

11-14
11-52

4-357
4-364

4-14
5-63

6-74
8-211
4-142
4-148
4-34
4-166
4-267
4-109
4-93
8-97
8-45
8-49

11-77

4-193
6-152
6-155
8-16
5-13
5-29

Signetics Linear Products

Alphanumeric Product list

Vol 1
SAA3027
SAA3028
SAA5025D
SAA5030
SAA5040
SAA5045
SAA5050
SAA5055
SAA5230
SAA5350
SAA7210
SAA7220
SAA9001
SAB1164
SAB1165
SAB1256
SAB3013
SAB3035
SAB3036
SAB3037
SAF1032P
SAF1039P
SE521
SE522
SE527
SE529
SE530
SE531
SE532
SE538
SE555
SE555C
SE556-1C
SE556/-1
SE558
SE564
SE565
SE566
SE567
SE592
SE4558
SE5018
SE5019
SE5030
SE5118
SE5119
SE5205
SE5212
SE541 0
SE5512
SE5514
SE5521
SE5532/A
SE5534A
SE5535
SE5537
SE5539
SE5560
SE5561
SE5562
SE5570
SG1524C
SG2524C
February 1987

IR Transmitter
IR Remote Control Transcoder With 12C
Teletext Timing Chain for 525-Line System
Teletext Video Input Processor
Teletext Acquisition and Control Circuit
Gearing and Address Logic Array (GALA)
Teletext Character Generator
Teletext Character Generator
Teletext Video Processor
Single-Chip Color CRT Controller (625-Line System)
Compact Disk Decoder
Digital Filter and Interpolator for Compact Disk
317k-Bit CCD Memory
1GHz Divide-by-64 Prescaler
1GHz Divide-by-64 Prescaler
1GHz Divide-by-256 Prescaler
Hex 6-Bit D/ A Converter
FLL Tuning and Control Circuit (Eight D/ A Converters)
FLL Tuning and Control Circuit
FLL Tuning and Control Circuit (Four D/A Converters)
Remote Control Receiver
Remote Control Transmitter
High-Speed Dual Differential Comparator/Sense Amp
High-Speed Dual Differential Comparator/Sense Amp
Voltage Comparator
Voltage Comparator
High Slew Rate Operational Amplifier
High Slew Rate Operational Amplifier
Low Power Dual Operational Amplifier
High Slew Rate Operational Amplifier
Timer
Timer
Dual Timer
Dual Timer
Quad Timer
Phase-Locked Loop
Phase-Locked Loop
Function Generator
Tone Decoder/Phase-Locked Loop
Video Amplifier
Dual General Purpose Operational Amplifier
8-Bit Microprocessor-Compatible D/ A Converter
8-Bit Microprocessor-Compatible D/ A Converter
10-Bit High-Speed Microprocessor-Compatible A/D Converter
8-Bit Microprocessor-Compatible D/ A Converter
8-Bit Microprocessor-Compatible D/ A Converter
Wide-band High Frequency Amplifier
Transimpedance Amplifier
10-Bit High-Speed Multiplying D/ A Converter
Dual High Performance Operational Amplifier
Quad High Performance Operational Amplifier
LVDT Signal Conditioner
Internally-Compensated Dual Low-Noise Operational Amp
Single and Dual Low-Noise Operational Amp
Dual High Slew Rate Op Amp
Sample-and-Hold Amplifier
Ultra High-Frequency Operational Amplifier
Switched-Mode Power Supply Control Circuit
Switched-Mode Power Supply Control Circuit
SMPS Control Circuit, Single Output
Three-Phase Brushless DC Motor Driver
Improved SMPS Push-Pull Controller
Improved SMPS Push-Pull Controller

1-11

Vol 2

Vol 3
5-38
5-47
13-14
13-25
13-32
13-44
13-48
13-48
13-61
13-67

7-329
7-343
11-129
4-92
4-92
4-97
4-45
4-50
4-65
4-75
5-3
5-3

4-163
4-163
4-168

5-285
5-290
5-296
5-301
4-53
4-60
4-123
4-68
7-47
7-47
7-32
7-32
7-38
4-257
4-291
4-304
4-313
4-46

4-14
5-63

4-26

4-231
4-48
5-144
5-150
5-31
5-164
5-169
4-166
4-267
5-208
4-75
4-81
5-358
4-87
4-93
4-129
5-327
4-211
8-67
8-86
8-97
8-45
8-131
8-131

11-109

11-77

11-89

Signetics Linear Products

Alphanumeric Product list

Vol 1
SG3524
SG3524C
SG3526A
TBA120
TCA520
TDA1001B
TDA1005A
TDA10l0A
TDA10llA
TDA1013A
TDA1015
TDA1020
TDA1023
TDA1029
TDA1072A
TDA1074A
TDA1510
TDA1512
TDA1514
TDA1515A
TDA1520A
TDA1521
TDA1522
TDA1524A
TDA1534
TDA1535
TDAl540
TDA1541
TDA1574
TDA1576
TDA1578A
TDA1721
TDA2540
TDA2541
TDA2545A
TDA2546A
TDA2549
TDA2555
TDA2577A
TDA2578A
TDA2579
TDA2582
TDA2593
TDA2594
TDA2595
TDA2611A
TDA2653A
TDA3047,T
TDA3048,T
TDA3505
TDA3563
TDA3564
TDA3566
TDA3567
TDA3651A
TDA3652
TDA3653
TDA3654
TDA3810
TDA4501
TDA4502
TDA4503
February 1987

SMPS Control Circuit
Improved SMPS Push-Pull Controller
Switched-Mode Power Supply Control Circuits
IF Amplifier and Demodulator
Operational Amplifier (Low Voltage)
Interference Suppressor
Frequency Multiplex PLL Stereo Decoder
6W Audio Amplifier With Preamplifier
2 to 6W Audio Power Amplifier With Preamplifier
4W Audio Amplifier With DC Volume Control
1 to 4W Audio Amplifier With Preamplifier
12W Audio Amplifier With Preamplifier
Time-Proportional Triac Trigger
Stereo Audio Switch
AM Receiver Circuit
DC-Controlled Dual Potentiometers
2 X 12W Audio Amplifier
12 to 20W Audio Amplifier
40W High-Performance Hi-Fi Amplifier
24W BTL Audio Amplifier
20W Hi-Fi Audio Amplifier
2 X 12W Hi-Fi Audio Power Amplifier
Stereo Cassette Preamplifier
Stereo-Tone/Volume Control Circuit
14-Bit AID Converter, Serial Output
High Performance Sample and Hold Amplifier With Resolution to
16 Bits
14-Bit DAC - Serial Output
16-Bit Dual DIA Converter, Serial Output
FM Front End IC (VHF Mixer and Oscillator)
FM IF System
PLL Stereo Decoder
8-Bit Multiplying DIA Converter
Video IF Amplifier and Demodulator, AFT, NPN Tuners
Video IF Amplifier and Demodulator, AFT, PNP Tuners
Quasi-Split Sound IF System
Quasi-Split Sound IF and Sound Demodulator
Multistandard Video IF Amplifier and Demodulator
Dual TV Sound Demodulator
Sync Circuit With Vertical Oscillator and Driver
Sync Circuit With Vertical Oscillator and Driver
Synchronization Circuit
Control Circuit for Power Supplies
Horizontal Combination
Horizontal Combination
Horizontal Combination
5W Audio Output Amplifier
Vertical Deflection Circuit With Oscillator
IR Preamplifier
IR Preamplifier
Chroma Control Circuit
NTSC Decoder With RGB Inputs
NTSC Decoder
PALINTSC Decoder With RGB Inputs
NTSC Color Decoder
Vertical Deflection
Vertical Deflection
Vertical Deflection
Vertical Deflection
Spatial, Stereo, Pseudo-Stereo Processor
Small Signal Subsystem IC for Color TV
Complete Video IF IC With Vertical and Horizontal Sync
Small Signal Subsystem for Monochrome TV

1-12

Vol 2

Vol 3

8-184
8-131
8-192
8-3
4-138
7-43
7-119
7-246
7-251
7-255
7-267
7-272
8-243
7-180
7-3
7-189
7-276
7-288
7-293
7-296
7-307
7-317
7-174
7-196
5-78

7-355
7-360
4-96
4-156
7-129

5-335
5-221
5-233

5-239
7-3
7-8
8-8
8-11
7-14
8-15
9-3
9-14
9-31
14-3
9-41
9-46
9-51
7-332
12-3
5-52
5-56
10-11
10-18
10-38
10-47
10-60
12-9
12-16
12-9
12-20
7-204
6-3
6-13
6-15

Signetics Linear Products

Alphanumeric Product list

Vol 1
TDA4505
TDA4555
TDA4565
TDA4570
TDA4580
TDA5030A
TDA5040
TDA5230
TDA5702
TDA5703
TDA5708
TDA5709
TDA6800
TDA7000
TDA7010T
TDA70211
TDA7040T
TDA7050
TDA8400
TDA8432
TDA8440
TDA8442
TDA8443/A
TDA8444
TDD1742
TEAl 017
TEAl 039
TEA1046A
TEAl 060
TEAl 061
TEAl 067
TEAl 068
TEAl 075
TEAl 080
TEA2000
TEA5550
TEA5560
TEA5570
TEA5580
TEA5581
TEA6000
TEA6300
UC1842
UC2842
UC3842C
ULN2003
ULN2004
p.A723
f.lA723C
p.A733
p.A733/C
f.lA741
p.A741C
p.A747
f.lA747C
p.A758

February 1987

Small Signal Subsystem IC for Color TV
Multistandard Color Decoder
Color Transient Improvement Circuit (CTI)
NTSC Color Difference Decoder
Video Control Combination Circuit With Automatic Cut-Off Control
VHF Mixer-Oscillator (VHF Tuner IC)
Brushless DC Motor Driver
VHF/UHF Mixer-Oscillator
8-Bit Digital-to-Analog Converter
8-Bit Analog-to-Digital Converter
Photo Diode Signal Processor
Radial Error Signal Processor
Video Modulator Circuit
Single-Chip FM Radio Circuit
Single-Chip FM Radio Circuit (SO Package)
Single Chip FM Radio Circuit
PLL Stereo Decoder (Low Voltage)
Low Voltage Mono/Stereo Power Amplifier
FLL Tuning Circuit With Prescaler
Deflection Processor With 12 C Bus
Video/ Audio Switch
Quad DAC With 12C Interface
RGB/YUV Switch Inputs
Octuple 6-Bit D/ A Converter With 12C Bus
CMOS Frequency Synthesizer
13-Bit Serial-to-Parallel Converter
Control Circuit for Switched-Mode Power Supply
Transmission Interface With DTMF
Telephone Transmission Circuit With Dialer Interface
Telephone Transmission Circuit With Dialer Interface
Low Voltage Transmission IC With Dialer Interface
Low Voltage Transmission IC With Dialer Interface
DTMF Generator for Telephone Dialing
Supply IC for Telephone Peripherals
Digital RGB to NTSC/PAL Encoder
AM Radio Circuit
FM IF System
AM/FM Radio Receiver Circuit
PLL Stereo Decoder
PLL Stereo Decoder
FM IF System and Computer Interface (MUSTI) Circuit
12C Active Tone Controller With Source Inputs
Current Mode PWM Controller
Current Mode PWM Controller
Current Mode PWM Controller
High Voltage/Current Darlington Transistor Array
High Voltage/Current Darlington Transistor Array
Precision Voltage Regulator
Precision Voltage Regulator
Differential Video Amplifier
Differential Video Amplifier
General Purpose Operational Amplifier
General Purpose Operational Amplifier
Dual Operational Amplifier
Dual Operational Amplifier
FM Stereo Multiplex Decoder Phase-Locked Loop

1-13

Vol 2

Vol 3

6-24
10-67
10-82
10-86
10-91
4-102

4-102
8-57
4-106
5-243
5-84

4-106
11-56
11-21

7-366
7-368
11-3
7-49
7-85
7-90
7-138
7-326
4-220

4-86
9-62
11-60
10-101
10-107

7-210

5-247
4-226
6-158
8-203

14-12

6-53
6-65
6-65
6-76
6-114
6-125
6-135
10-116
7-26
7-96
7-34
7-144
7-147
7-104
7-216
8-216
8-216
8-216
6-42
6-42
8-211
8-211
4-245
4-245
4-142
4-142
4-148
4-148
7-154

11-123
11-123

Signetics

Application Notes
by Product Group

Linear Products

Vol 1

Vol 2

Vol 3

4-34
4-55
4-75
4-79
4-87
4-130
4-140

4-219
4-240

11-97
11-118

Signal Processing
AN140
AN141
AN198
AN1981
AN1982
AN199
AN1991

Compensation Techniques for Use With the SE/NE5539
Using the NE592/5592 Video Amplifier
Designing With SAlNE602
New Low Power Single Sideband Circuits (NE602)
Applying the Oscillator of the NE602 in Low Power Mixer Applications
Designing With the NE/SA604
Audio Decibel Level Detector With Meter Driver

4-189
4-199

Frequency Synthesis
AN196
AN197

Single-Chip Synthesizer For Radio Tuning
Analysis and Basic Application of the SAA1057 (VBA8101)

4-201
4-208

Phase-Locked Loops
AN177
AN178
AN179
AN180
AN1081
AN181
AN182
AN183
AN184
AN185
AN186
AN187
AN188

An Overview of Phase-Locked Loops (PLL)
Modeling the PLL
Circuit Description of the NE564
The NE564: Frequency Synthesis
10.8MHz FSK Decoder With the NE564
A 6MHz FSK Converter Design Example for the NE564
Clock Regenerator With Crystal Controlled Phase~Locked VCO
Circuit Description of the NE565
Typical Applications With NE565
Circuit Description of the NE566
Waveform Generators With the NE566
Circuit Description of the NE567 Tone Decoder
Selected Circuits Using the NE567

4-236
4-241
4-266
4-273
4-277
4-280
4-282
4-297
4-301
4-309
4-310
4-325
4-330

Applications for Compandors: NE570/571/SA571
Automatic Level Control: NE572
Compandor Cookbook

4-341
4-372
4-350

Compandors
AN174
AN175
AN 176

Line Drivers/Receivers
AN113
AN195
AN1950
AN1951

Applications Using the MC1488/1489 Line Drivers and Receivers
Applications Using the NE5080/5081
Exploring the Possibilities in Data Communications
NE5050: Power Line Modem Application Board Cookbook

5-11
5-52
5-60
5-30

Telephony
AN1942
AN1943

TEA1067: Application of the Low Voltage Versatile Transmission Circuit
TEA 1067: Supply of Peripheral Circuits With the TEA 1067 Speech Circuit

6-88
6-108

TDA 1072A: Integrated AM Receiver
Designing With the SA/NE602
New Low Power Single Sideband Circuits (NE602)
Applying the Oscillator of the NE602 in Low Power Mixer Applications
Stereo Decoder Applications Using the p.A758
A Complete FM Radio on a Chip
TDA7000 for Narrow-Band FM-Reception
Designing With the SAlNE604
Audio Decibel Level Detector With Meter Driver (NE604)

7-15
4-75
4-79
4-87
7-159
7-54
7-69
7-130
7-140

Radio Circuits
AN1961
AN198
AN1981
AN1982
AN191
AN192
AN193
AN199
AN1991
February 1987

1-14

6-11

Signetics Linear Products

Application Notes by Product Group

Vol 1

Vol 2

Vol 3

Audio Circuits

AN148
AN1481
AN149
AN1491
AN190

Audio Amplifier With TDA 1013
Car Radio Audio Power Amplifiers up to 20W With the TDA 1515
20W Hi-Fi Power Amplifier With the TDA1520A
Car Radio Audio Power Amplifiers up to 24W With the TDA1510
Applications of Low Noise Stereo Amplifiers: NE542

7-258
7-300
7-312
7-280
7-171

Operational Amplifiers

AN142
AN144
AN1441
AN1511
AN160
AN164
AN165
AN166

Audio Circuits Using the NE5532/33/34
Applications for the NE5512 and NE5514
Applications for the NE5514
Low Voltage Gated Generator: NE5230
Applications for the MC3403
Explanation of Noise
Integrated Operational Amplifier Theory
Basic Feedback Theory
,

4-101
4-78
4-84
4-121
4-45
4-8
4-18
4-25

High Frequency Amps

AN199
AN1991

Designing With the NE/SA604
Audio Decibel Level Detector With Meter Driver

4-130
4-140

4-189
4-199

4-34
4-55

4-219
4-240

Video Amps

AN140
AN141

Compensation Techniques for Use With the SE/NE5539
Using the NE592/5592 Video Amplifier

11-97
11-118

Transconductance

AN145

4-264

NE5517: General Description and Applications for Use With the NE5517/A
Transconductance Amplifier

Data Conversion

AN100
AN101
AN105
AN106
AN108
AN1081
AN109
AN110

An Overview of Data Converters
Basic DACs
Digital Attenuator
Using the DAC08 Without a Negative Supply
An Amplifiying, Level Shifting Interface for the PNA 7507 Video D/ A Converter
NE5150/51/52: Family of Video D/ A Converters
Microprocessor-Compatible DACs
Monolithic 14-Bit DAC With 85dB SIN Ratio

5-3
5-91
5-98
5-123
5-77
5-188
5-174
5-226

Applications for the NE521 /522/527/529

5-306

Comparators

AN116

Position Measurement

AN118
AN1181
AN1182

LVDT Signal Conditioner: Applications Using the NE5520
NE5521 in a Modulated Light Source Design Application
NE5521 in Multi-faceted Applications

5-343
5-363
5-367

Line Drivers/Receivers

AN113

Applications Using the MC1488/1489 Line Drivers and Receivers

5-11

6-11

Display Drivers

AN112
LED Decoder Drivers: Using the NE587 and NE589
Serlal-to-Parallel Converters
AN103

6-68
6-163

13-Bit Serial-to-Parallel Converter

Timers

AN 170
AN171

February 1987

7-53
7-42

NE555 and NE556 Applications
NE558 Applications

1-15

11-20
11-32

Signetics Linear Products

Application Notes by Product Group

Vol 1

Vol 2

Vol 3

Motor Control and Sensor Circuits
AN127
AN131
AN1311
AN132
AN133
AN1341

Using the SAA 1027 With Airpax Four-Phase Stepper Motors
Applications Using the NE5044 Encoder
Low Cost AID Conversion Using the NE5044
Applications Using the NE5045 Decoder
Applications Using the NE544 Servo Amplifier
Control System for Home Computer Robotics

8-52
8-12
8-14
8-22
8-40
8-23

Switched-Mode Power Supply
AN120
AN121
AN 122
AN123
AN124
AN125
AN126
AN1261
AN128
AN1291

An Overview of SMPS
Forward Converter Application Using the NE5560
NE5560 Push-Pull Regulator Application
NE5561 Applications
External Synchronization for the NES561
Progress in SMPS Magnetic Component Optimization
Applications Using the SG3524
High Frequency Ferrite Power Transformer and Choke
Introduction to the Series-Resonant Power Supply
TDA1023: Design of Time-Proportional Temperature Controls

8-62
8-82
8-83
8-91
8-96
8-225
8-190
8-138
8-235
8-251

Tuning Circuits
AN157

Microcomputer Peripheral IC Tunes and Controls a TV Set: SAB3035

4-61

Remote Control System
AN 172
AN173
AN1731

Circuit Description of the Infrared Receiver TDA3047/TDA3048
Low Power Preamplifiers for IR Remote Control Systems
SAA3004: Low Power Remote Control IR Transmitter and Receiver
Preamplifiers

5-60
5-62
5-20

Synch Processing and Generator
AN158
AN162
AN1621

Features of the TDA2595 Synchronization Processor
A Versatile High-Resolution Monochrome Data and Graphics
Directives for a Print Layout Design on Behalf of the
IC Combination TDA2578A and TDA3651
Color Decoding and Encoding

AN155/A
AN1551
AN156
AN1561

Multi-Standard Color Decoder With Picture Improvement
Single-Chip Multi-Standard Color Decoder TDA4555/4556
Application of the NTSC Decoder: TDA3563
Application of the TEA2000 Color Encoder

9-57
9-25
9-30
10-3
10-73
10-25
10-121

Videotex/Teletext
AN152
AN153
AN154

February 1987

A Single-Chip CRT Controller
The 5 Chip Set Teletext Decoder
Teletext Decoders: Keeping up With the Latest Technology Advances

1-16

13-89
13-3
13-8

Application Notes
by Part Numbers

Signetics

Linear Products

DAC08
MC1488
MC1489/A
MC1496/1596

AN106:
ANl13:
ANl13:
AN189:

MC3403
NE5044

AN160:
AN131:
AN1311:
AN1341:
AN132:
AN1951:

NE5045
NE5050
NE5080/5081

NE5517

AN195:
AN1950:
AN1081:
ANl16:
ANl16:
AN1511:
AN116:
ANl16:
AN1511:
AN190:
AN133:
AN144:
AN1441:
AN145:

NE5520

ANl18:

NE5521

AN1181:

NE5532/33/34
NE5539

ANl182:
AN142:
AN140:

NE5150/51/52
NE521
NE522
NE5230
NE527
NE529
NE531
NE542
NE544
NE5512/5514

NE555
NE556
NE/SE5560

AN170:
AN170:
AN121:
AN122:
AN125:

NE/SE5561

AN123:
AN124:
AN125:

NE/SE5562

AN125:

NE/SE5568

AN125:

NE558
NE564

AN171:
AN179:
AN180:
AN1801:

February 1987

Using the DAC08 Without a Negative Supply
Using the MC1488/89 Line Drivers and Receivers
Using the MC1488/89 Line Drivers and Receivers
Balanced Modulator/Demodulator Applications Using
the MC1496/1596
Applications for the MC3403
Applications Using the NE5044 Encoder
Low Cost AID Conversion Using the NE5044
Control System for Home Computer and Robotics
Applications Using the NE5045 Decoder
NE5050: Power Line Modem Application Board
Cookbook
Applications Using the NE5080, NE5081
Exploring the Possibilities in Data Communications
NE5150/51/52 Family of Video D/ A Converters
Applications for the NE521 /522/527/529
Applications for the NE521/522/5271529
Low Voltage Gated Generator: NE5230
Applications for the NE5211522/527/529
Applications for the NE521 /522/527/529
Low Voltage Gated Generator: NE5230
Applications of Low Noise Stereo Amplifiers: NE542
Applications Using the NE544 Servo Amplifier
Applications for the NE5512
Applications for the N E5514
NE5517: General Description and Applications for
Use With the NE5517 / A Transconductance Amplifier
LVDT Signal Conditioner: Applications Using the
NE5520
NE5521 in a Modulated Light Source Design
Application
NE5521 in Multi-faceted Applications
Audio Circuits Using the NE5532/33/34
Compensation Techniques for Use With the
SEINE5539
NE555 and NE556 Applications
NE555 and NE556 Applications
Forward Converter Application Using the NE5560
NE5560 Push-Pull Regulator Application
Progress in SMPS Magnetic Component
Optimization
NE5561 Applications
External Synchronization for the NE5561
Progress in SMPS Magnetic Component
Optimization
Progress in SMPS Magnetic Component
Optimization
Progress in SMPS Magnetic Component
Optimization
NE558 Applications
Circuit Description of the NE564
The NE564: Frequency Synthesis
10.8MHz FSK Decoder With the NE564

1-17

Vol 1

Vol 2

5-11
5-11

5-123
6-11
6-11

Vol 3

4-64
4-45
8-12
8-14
8-23
8-22
5-30
5-52
5-60
5-188
5-306
5-306
4-121
5-306
5-306
4-121

11-32

7-171
8-40
4-78
4-84
4-264
5-343
5-363
5-367
4-101
4-34

4-219
7-53
7-53
8-82
8-83
8-225
8-91
8-96
8-225
8-225
8-225
7-42

4-266
4-273
4-277

11-97

Signetics Linear Products

Application Notes by Part Numbers

Vol 1
NE564

AN182:
AN181:

NE565
NE566
NE567
NE570/571/SA571
NE572
NE587/589
NE592/5592
NE/SA602

AN183:
AN184:
AN185:
AN186:
AN187:
AN188:
AN 174:
AN175:
AN112:
AN141:
AN198:
AN1981:
AN1982:

NE/SA604

AN199:
AN1991:

PCF8570

AN167:

PNA7509

AN108:

SAA1027

AN127:

SAA1057
SAA3004

AN196:
AN197:
AN1731:

SAA5025D
SAA5030
SAA5040
SAA5045
SAA5050
SAA5230

AN153:
AN153:
AN153:
AN153:
AN153:
AN154:

SAA5240

AN154:

SAA5350
SAB3035

AN152:
AN157:

SG1524C

AN1261:

SG3524C

AN1261:
AN125:

TDA1013A
TDA1023
TDA1072A
TDA1510

AN126:
AN148:
AN1291:
AN1961:
AN1491:

TDA1515

AN1481:

TDA1520A
TDA1540
TDA2578

AN149:
AN110:
AN1621:

February 1987

Clock Regenerator With Crystal Controlled PhaseLocked VCO
A 6MHz FSK Converter Design Example for the
NE564
Circuit Description of the NE565
FSK Demodulator With NE565
Circuit Description of the NE566
Waveform Generators With the NE566
Circuit Description of the NE567 Tone Decoder
Selected Circuits Using the NE567
Applications for Compandors: NE570/571/SA571
Automatic Level Control: NE572
LED Decoder Drivers: Using the NE587 and NE589
Using the NE592/5592 Video Amplifier
Designing With the NE/SA602
New Low Power Single Sideband Circuits (NE602)
Applying the Oscillator of the NE602 in Low Power
Mixer Applications
Designing With the NE/SA604
Audio Decibel Level Detector With Meter Driver
(NE602)
PCF8570: Twisted-Pair Bus Carries Speech, Data,
Text and Images
An Amplifying, Level Shifting Interface for the
PNA7509 Video D/A Converter
Using the SAA1027 With Airpax Four-Phase Stepper
Motors
Single-Chip Synthesizer for Radio Tuning
Analysis and Basic Application of the SAA 1057
SAA3004: Low Power Remote Control IR
Transmitter and Receiver Preamplifiers
The 5 Chip Set Teletext Decoder
The 5 Chip Set Teletext Decoder
The 5 Chip Set Teletext Decoder
The 5 Chip Set Teletext Decoder
The 5 Chip Set Teletext Decoder
Teletext Decoders: Keeping Up With the Latest
Technology Advances
Teletext Decoders: Keeping Up With the Latest
Technology Advances
SAA5350: A Single-Chip CRT Controller
Microcomputer Peripheral IC Tunes and Controls a
TV Set
High Frequency Ferrite Power Transformer and
Choke
High Frequency Ferrite Power Transformer and
Choke
Progress in SMPS Magnetic Component
Optimization
Applications Using the SG3524
Audio Amplifier With TDA1013A
Design of Time-Proportional Temperature Controls
TDA 1072A: Integrated AM Receiver
Car Radio Audio Power Amplifiers Up to 24W With
the TDA1510
Car Radio Audio Power Amplifiers Up to 20W With
the TDA1515
20W Hi-Fi Power Amplifier With the TDA 1520A
Monolithic 14-Bit DAC With 85dB SIN Ratio
Directives for a Print Layout Design on Behalf of
the IC Combination TDA2578A and TDA3651

1-18

Vol 2

Vol 3

6-68
4-240

11-118

4-282
4-280
4-297
4-301
4-309
4-310
4-325
4-330
4-341
4-372
4-55
4-75
4-79
4-87
4-130

4-189

4-140

4-199

5-77

11-20

8-52
4-201
4-208
5-20
13-3
13-3
13-3
13-3
13-3
13-8
13-8
13-89
4-61
8-138
8-138
8-225
8-190
7-258
8-251
7-15
7-280
7-300
7-312
5-226
9-30

Signetics Linear Products

Application Notes by Part Numbers

Vol 1

TDA2595
TDA2595

AN158:
AN162:

TDA2653

AN162

TDA3047

AN172:
AN173:

TDA3048

AN172:
AN173:

TDA3505

AN155/A:

TDA3563
TDA3651

AN156:
AN1621:

TDA4555

AN155/A:

AN1551:
TDA7000
TEA1017
TEA1067

AN192:
AN193:
AN103:
AN1942:
AN1943:

TEA2000
p.A758

February 1987

AN1561:
AN191:

Features of the TDA2595 Synchronization Processor
A Versatile High-Resolution Monochrome Data and
Graphics Display Unit
A Versatile High-Resolution Monochrome Data and
Graphics Display Unit
Circuit Description of the Infrared Receiver
Low Power Preamplifiers for IR Remote Control
Systems
Circuit Description of the Infrared Receiver
Low Power Preamplifiers for IR Remote Control
Systems
Multi-Standard Color Decoder With Picture
Improvement
Application of the NTSC Decoder: TDA3563
Directives for a Print Layout Design on Behalf of
the IC Combination TDA2578A and TDA3651
Multi-Standard Color Decoder With Picture
Improvement
Single-Chip Multi-Standard Color Decoder TDA45551
4556
A Complete FM Radio on a Chip
TDA7000 for Narrowband FM Reception
13-Bit Serial-to-Parallel Converter
TEA1067: Application of the Low Voltage Versatile
Transmission Circuit
TEA 1067: Supply of Peripheral Circuits With the
TEA 1067 Speech Circuit
Application of the TEA2000 Color Encoder
Stereo Decoder Applications Using the p.A 758

1·19

Vol 2

Vol 3

9-57
9-25
9-25
5-60
5-62
5-60
5-62
10-30
10-25
9-30
10-3
10-73
7-54
7-69

6-88
6-108
10-121
7-159

Signetics

Outline
Volume 2:
Industrial

Linear Products

Preface
Section 1:

GENERAL INFORMATION

Section 2:

QUALITY AND RELIABILITY

Section 3:

12 C SMALL AREA NETWORKS

Section 4:

AMPLIFIERS
Operational
High Frequency
Transconductance
Fiber Optics

Section 5:

DATA CONVERSION
Analog-to-Digital
Digital-to-Analog
Comparators
Sample-and-Hold
Position Measurement

Section 6:

INTERFACE
Line Drivers/Receivers
Peripheral Drivers
Display Drivers
Serial-to-Parallel Converters

Section 7:

TIMERS

Section 8:

POWER CONVERSION/CONTROL

Section 9:

PACKAGE INFORMATION

Section 10: SALES OFFICES

February 1987

1-20

Signetics

Outline
Volume 3:
Video

Linear Products

Preface
Section 1:

GENERAL INFORMATION

Section 2:

QUALITY AND RELIABILITY

Section 3:

12 C SMALL AREA NETWORKS

Section 4:

TUNING SYSTEMS
Tuner Control Peripherals
Tuning Circuits
Prescalers
Tuner IC

Section 5:

REMOTE CONTROL SYSTEMS

Section 6:

TELEVISION SUBSYSTEMS

Section 7:

VIDEO IF

Section 8:

SOUND IF AND SPECIAL AUDIO PROCESSING

Section 9:

SYNCH PROCESSSING AND GENERATION

Section 10: COLOR DECODING AND ENCODING
Section 11: SPECIAL PURPOSE VIDEO PROCESSING
Video Modulator/Demodulator
AID Converters
D/ A Converters
Switching
High Frequency Amplifiers
CCD Memory
Section 12: VERTICAL DEFLECTION
Section 13: VIDEOTEX/TELETEXT
Section 14: SWITCHED-MODE POWER SUPPLIES FOR TV/MONITOR
Section 15: PACKAGE INFORMATION
Section 16: SALES OFFICES

February 1987

1-21

Cross Reference Guide

Signetics

Pin-for-Pin Functionally-Compatible*
Cross Reference by Competitor
Linear Products

Competitor
Signetics
Competitor Part Number Part Number

Temperature
Range (OC)
Package

AMD

AM6012F
DAC·08AF
DAC·08CN
DAC-08CF
DAC·08EN
DAC·08EF
DAC·08HN
DAC·08HF
DAC·08F
LF198H
SE5537H
LF398H
NE5537H
LF398D
NE5537D
LF398N
NE5537N
NE5534/AF
NE5534/AF
SE5534/AF
NE5020N
NE5018N
SE50t9F
SE50t8F

o to

+70
-55 to + 125
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
-55 to + 125
-55 to +125
-55 to +125
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
-55 to + 125
o to +70
o to +70
-55 to +125
-55 to 125

Ceramic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Ceramic
Metal Can
Metal Can
Metal Can
Metal Can
SO
SO
Plastic
Plastic
Ceramic
Ceramic
Ceramic
Plastic
Plastic
Ceramic
Ceramic

XR·5532/A N NE5532/AF
XR·5532/A P NE5532/AN
XR·L567CN
NE567F
XR·L567CP
NE567N
XR·5534/ A CN NE5534/ AF
XR·5534/ A CP NE5534/ AN
XR·5534/ A M SE5534/ AF
XR·558CN
NE558F
XR·558CP
NE558N
XR·558M
SE558F
XR·1524N
SG3524F
XR·t524P
SG3524N
XR·2524P
SG3524N
XR·3524N
SG3524F
XR·3524P
SG3524N

o to
o to
o to
o to
o to
o to

+70
+70
+70
+70
+70
+70
-55 to + 125
o to +70
o to +70
-55 to +125
o to +70
o to +70
o to +70
o to +70
o to +70

Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Ceramic
Plastic
Ceramic
Ceramic
Plastic
Plastic
Ceramic
Plastic

1lA080/DA
1lA0801CDC
1lA0801CPC
1lA0801EDC
1lA0801EPC
1lA1458TC
1lA1488DC
IlA1488PC
IlA1489/A PC
1lA1489/A PC
1lA198HM
IlAt98RM

o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70

Ceramic
Ceramic
Plastic
Ceramic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Metal Can
Plastic

Datel

Exar

Fairchild

AM6012DC
DAC·08AQ
DAC·08CN
DAC·08CQ
DAC·08EN
DAC·08EQ
DAC·08HN
DAC·08HQ
DAC·08Q
LF198H
LF198H
LF398H
LF398H
LF398L
LF398L
LF398N
LF398N
AM·453·2
AM·453·2C
AM·453·2M
DAC·UPtOBC
DAC·UP8BC
DAC·UP8BM
DAC·UP8BQ

DAC·08F
MC1408F
MC1408N
DAC·08EF
DAC·08AF
MC1458N
MC1488F
MC1488N
MC1489/AF
MC1489/AN
NE5537H
NE5537N

Competitor
Signetlcs
Competitor Part Number Part Number

Temperature
Range (OC)
Package
-40 to +85
-40 to +85
o to +70
o to +70
o to +70
-40 to +85
-40 to +85
o to +70
o to +70
o to +70
o to +70
-55 to + 125
-55 to + 125
o to +70
o to +70

Ceramic
Plastic
Ceramic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Metal Can
Plastic
Plastic
Plastic

1lA723DC
1lA723DM
1lA723HC
1lA723PC
1lA733DC
1lA733DM
1lA733PC
1lA741NM
1lA741RC
1lA741TC
1lA747DC
1lA747PC
1lA9667DC
1lA9667PC
IlA9668DC
IlA9668PC

LM290tF
LM2901N
LM311F
LM324F
LM324N
MC3302F
MC3302N
LM339/AF
LM339/AN
MC3403F
MC3403N
SE5537H
SE5537N
NE555N
NE556·tN,
NE556N
1lA723CF
IlA723F
1lA723CH
1lA723CN
1lA733F
1lA733F
1lA733N
1lA741N
1lA741CF
1lA741CN
1lA747CF
1lA747CN
ULN2003F
ULN2003N
ULN2004F
ULN2004N

o to +70
-55 to + 125
o to +70
o to +70
o to +70
-55 to + 125
o to +70
-55 to + 125
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70

Ceramic
Ceramic
Metal Can
Plastic
Ceramic
Ceramic
Plastic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic

Harris

HA·2539
HA·2420·2/8B
HA·2425N
HA·2425B
HA1·5102·2
HA1·5135·2
HAt·5t35·5
HA3·51 02·5
HA1·5202·5
HA·5320B

NE5539
SE5060F
NE5060N
NE5060F
SE5532/AF
SE5534/AF
NE5534/AF
NE5532/AN
NE5532/AF
NE5060F

o to +70
-55 to +125
o to +70
o to +70
-55 to + 125
-55 to + 125
o to +70
o to +70
o to +70
o to +70

Plastic
Ceramic
Plastic
Ceramic
Ceramic
Ceramic
Ceramic
Plastic
Ceramic
Ceramic

Intersll

ADC0803LCD ADCOB03·1 LCF - 40 to + B5
ADCOB04
ADCOB04·t CN o to +70
ADCOB05
ADCOB05·t LCN -40 to + 85

Motorola

DAC·OBCD
DAC·08CQ
DAC·08ED
DAC·OBEF
DAC·OBHQ
DAC·OBQ

1lA290tDC
1lA290tPC
1lA311RC
1lA324DC
1lA324PC
1lA3302DC
1lA3302PC
1lA339/ADC
1lA339/APC
1lA3403DC
1lA3403PC
1lA398HC
1lA398RC
1lA555TC
1lA556PC

1-22

DAC·OBCN
DAC·OBCF
DAC·OBEN
DAC-OBEF
DAC·OBHF
DAC·OBF

o to
o to
o to
o to
o to

+70
+70
+70
+70
+70
-55 to + t25

Ceramic
Plastic
Plastic
Plastic
Ceramic
Plastic
Ceramic
Ceramic
Ceramic

Signetics Linear Products

Cross Reference Guide

Competitor
Signetics
Competitor Part Number Part Number
LM2901N
LM311J-B
LM311N
LM324J
LM324N
LM339/A J
LM339/A N
LM35BN
LM393A/J
LM393A1N
MC140BL
MC140BP
MC14BBL
MC14BBP
MC14B9/A L
MC14B9/A P
MC1496L
MC1496P
MC3302L
MC3302P
MC3361D
MC3361P
MC3403L
MC3403P
MC3410CL
MC3410L

National

Temperature
Range (OC)
Package

MC3510L
NE592F
NE592F
NE592N
NE565N
SE592F
SE592F
SE592H

LM2901N
LM311F
LM311N
LM324F
LM324N
LM339/AF
LM339/AN
LM35BN
LM393/AF
LM393/AN
MC140BF
MC140BN
MC14BBF
MC14BBN
MC14B9/AF
MC14B9/AN
MC1496F
MC1496N
MC3302F
MC3302N
MC3361D
MC3361N
MC3403F
MC3403N
MC3410CF
MC341OF
NE5410F
SE5410F
NE592F-B
NE592F-14
NE592N
NE565N
SE592F-8
SE592F-14
SE592H

-40 to +B5
+70
+70
+70
+70
+70
+70
+70
+70
+70
+70
+70
+70
+70
+70
+70
+70
+70
-40 to +B5
-40 to +B5
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
-55 to +125
-55 to + 125
-55 to + 125

Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
SO
Plastic
Ceramic
Plastic
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Plastic
Plastic
Ceramic
Ceramic
Metal Can

ADC0803F
ADC0803N
ADC0805
ADCOB20BCN
ADC0820CCN
ADC0820BCD
ADCOB20CCD
ADCOB20BD
ADC0820CD
DAC0800LCJ
DACOBOOLJ
DACOBOOLCN
DACOB01LCJ
DACOB01LCN
DAC0802LJ
DACOB02LCJ
DACOB02LCN
DACOB06LCJ
DACOB06LCN
DACOB07LCJ
DACOB07LCN
DACOBOBLCJ

ADC0803-1 LCF
ADC0803-1 LCN
ADCOB05-1 LCN
ADCOB20BNEN
ADC0820CNEN
ADC0820BSAN
ADCOB20CSAN
ADC0820BSEF
ADCOB20CSEF
DAC-OBEF
DAC-OBF
DAC-OBEN
DAC-OBCF
DAC-OBCN
DAC-OBAF
DAC-OBHF
DAC-08HN
MC1408-6F
MCI40B-6N
MCI40B-7F
MCI40B-7N
MC140BF

-40 to +85
-40 to +85
-40 to + 85
o to +70
o to +70
-40 to +85
-40 to +B5
-55 to +125
-55 to + 125
o to +70
-55 to + 125
o to +70
o to +70
o to +70
-55 to +125
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70

Ceramic
Plastic
Plastic
Plastic
Plastic
Plastic
Plastic
Ceramic
Ceramic
Ceramic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic

o to
o to
o to
o to
o to
o to
o to
o to
o to
o to
o to
o to
o to
o to
o to
o to
o to

Competitor
Signetics
Competitor Part Number Part Number
DACOBOBLCN
DACOBOBLD
LF19BH
LF39BH
LF39BN
LM13600AN
LM13600N
LM145BN
LM161H
LM161J
LM2524J
LM2524N
LM2901N
LM2903N
LM30B9
LM319J
LM319N
LM324J
LM324N
LM324AD
LM324AN
LM339/AJ
LM339/AN
LM3524J
LM3524N
LM358H
LM358N
LM361H
LM361J
LM361N
LM393/AN
LM555J
LM555N
LM556J
LM556N
LM556CJ
LM556CN
LM565CN
LM566N
LM566CN
LM567CN
LM733CN
LM741CJ
LM741CN
LM741J
LM741N
LM747CJ
LM747CN
LM747J
LM747N
UC3B42D
UC3B42J
UC3B42N
UC2B42D
UC2B42J
UC2B42N
UC1B42J
UC1B42N

1-23

MC1408N
MC140BF
SE5537H
NE5537H
NE5537N
NE5517N
NE5517N
MC145BN
SE529H
SE529F
SG3524F
SG3524N
LM2901N
LM2903N
CA30B9N
LM319F
LM319N
LM324F
LM324N
LM324AD
LM324AN
LM339/AF
LM339/AN
SG3524F
SG3524N
LM35BH
LM358N
NE529H
NE529D
NE529N
LM393/AN
NE555F
NE555N
SE556-1F
SE556-1N
NE556-1F
NE556-1N
NE565N
SE566N
NE566N
NE567N
MA733CN
MA741CF
MA741CN
MA741F
IJA741N
MA747CF
IJA747CN
jJ747F
IJA747N
UC3B42D
UC3B42FE
UC3B42N
UC2B42D
UC2B42FE
UC2B42N
UC1B42FE
UC1B42N

Temperature
Range (OC)
Package

o to
o to

+70
+70
-55 to + 125
o to +70
o to +70
o to +70
o to +70
o to +70
-55 to + 125
-55 to + 125
o to +70
o to +70
-40 to +85
-40 to +B5
-55 to + 125
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
-55 to +125
-55 to +125
o to +70
o to +70
o to +70
-55 to + 125
o to +70
o to +70
o to +70
o to +70
o to +70
-55 to + 125
-55 to + 125
o to +70
o to +70
-55 to + 125
-55 to + 125
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
-55 to + 125
-55 to +125

Plastic
Ceramic
Metal Can
Metal Can
Plastic
Plastic
Plastic
Plastic
Metal Can
Ceramic
Ceramic
Plastic
Plastic
Plastic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Plastic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Metal Can
Plastic
Metal Can
SO
Plastic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Plastic
Plastic
Plastic
Plastic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Plastic
Ceramic
Plastic
Plastic
Ceramic
Plastic
Ceramic
Plastic

Signetics linear Products

Cross Reference Guide

Competitor
Signetics
Competitor Part Number Part Number

Temperature
Range (OC)
Package

NEC

J.LPC1571C

NE571N

PMI

CMP-05GP
CMP-05CZ
CMP-05BZ
CMP-05GZ
CMP-05FZ
DAC1408A-6P
DAC1408A-6Q
DAC1408A-7N
DAC1408A-7Q
DAC1408A-8N
DAC1408A-8Q
DAC1508A-8Q
DAC312FR
OP27BZ
OP27CZ
PM747Y
SMP-10AY
SMP-10EY
SMP-11AY
SMP-11EY

NE5105N
SE5105F
SE5105F
SA5105N
SA5105N
MC1408-6N
MC1408-6F
MC1408-7N
MC1408-7F
MC1408-8N
MC1408-8F
MC1408-8F
AM6012F
SE5534AFE
SE5534FE
J.LA747N
SE5060F
NE5060N
SE5060F
NE5060N

o to
o to

RC4805DE
RC4805EDE
RM4805DE
RM4805ADE
RC5532/ A DE
RC5532/ A NB
RC5534/ A DE
RC5534/ A NB
RM5532/ A DE
RM5534/ A DE

NE5105N
NE5105AN
SE5105F
SE5105AF
NE5532/ AF
NE5532/ AN
NE5534/ AF
NE5534/ AN
SE5532/ AF
SE5534/ AF

Silicon
General

SG3524J
SG3526N

Sprague

TI

Raytheon

+70

Plastic

+70
to + 125
to + 125
to +85
to +85
+70
+70
+70
+70
+70
+70
to + 125
+70
to + 125
to + 125
to + 125
to +125
+70
to + 125
+70

Plastic
Ceramic
Ceramic
Plastic
Plastic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic

-55
-55
o to
o to
o to
o to
-55
-55

+70
+70
to + 125
to + 125
+70
+70
+70
+70
to +125
to + 125

Plastic
Plastic
Ceramic
Ceramic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Ceramic

SG3524F
SG3526N

o to
o to

+70
+70

Ceramic
Plastic

UDN6118A
UDN6118R
ULN8142M
ULN8160A
ULN8160R
ULN8161M
ULN8168M
ULN8564A
ULN8564R
ULS8564R

SA594N
SA594F
UC3842N
NE5560N
NE5560F
NE5561N
NE5568N
NE564N
NE564F
SE564F

-40
-40
o to
o to
o to
o to
o to
o to
o to
-55

to +85
to +85
+70
+70
+70
+70
+70
+70
+70
to + 125

Plastic
Ceramic
Plastic
Plastic
Ceramic
Plastic
Plastic
Plastic
Ceramic
Ceramic

ADC0803N
ADC0804CN
ADC0805N
LM111J
LM311D

ADC0803-1 LCN -40
ADC0804-1 CN o to
ADC0805-1 LCN - 40
LM111F
-55
LM311D
o to

to +85
+70
to + 85
to +125
+70

Plastic
Plastic
Plastic
Ceramic
Plastic

-55
-55
-40
-40
o to
o to
o to
o to
o to
o to
-55
o to
-55
-55
-55
-55
o to
-55
o to

o to
o to

Competitor
Signetics
Competitor Part Number Part Number

Unltrode

Temperature
Range (OC)
Package

LM311J
LM311JG
LM324D
LM324J
LM339/AJ
LM339/AN
LM358P
LM393/A P
MC1458P
NE5532/ A JG
NE5532/A P
NE5534/ A JG
NE5534/A P
NE555JG
NE555P
NE556D
NE556J
NE556N
NE592
NE592A
NE592J
NE592N
SA556D
SE5534/A JG
SE555JG
SE556J
SE556N
SE592
SE592J
SE592N
SN55107AJ
SN55108AJ
SN75107AJ
SN75107AN
SN75108AJ
SN75108AN
SN75188J
SN75188N
SN75189AJ
SN75189AN
SN75189J
SN75189N
TL592A
TL592P
J.LA723CJ
J.LA723CN
J.LA723MJ
J.LA723MU

LM311F
LM311FE
LM324N
LM324F
LM339/AF
LM339/AN
LM358N
LM393/AN
MC1458N
NE5532/ AF
NE5532/AN
NE5534/AF
NE5534/AN
NE555N
NE555N
NE556N
NE556-1F
NE556-1N
NE592N14
NE592F14
NE592F
NE592N-14
SA556N
SE5534/AF
SE555N
SE556-1F
SE556-1N
SE592N14
SE592F-14
SE592N-14
NE521F
SE522F
NE521F
NE521N
NE522F
NE522N
MC1488F
MC1488N
MC1489AF
MC1489AN
MC1489F
MC1489A
NE592F14
NE592NB
J.LA723CF
J.LA723CN
J.LA723F
J.LA723D

o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
-40 to +85
-55 to + 125
-55 to + 125
-55 to + 125
-55 to + 125
-55 to + 125
-55 to + 125
-55 to +125
o to +70
-55 to + 125
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
o to +70
-55 to + 125
-55 to + 125

Ceramic
Ceramic
Plastic
Ceramic
Ceramic
Plastic
Plastic
Plastic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Plastic
Plastic
Plastic
Ceramic
Plastic
Plastic
Ceramic
Ceramic
Plastic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Plastic
Ceramic
Plastic
Plastic
Ceramic
Plastic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
Plastic
Ceramic
SO

UC3524J
UC3524N

SG3524F
SG3524N

o to
o to

Ceramic
Plastic

+70
+70

'THERE MAY BE PARAMETRIC DIFFERENCES BETWEEN SIGNETICS'
PARTS AND THOSE OF THE COMPETITION.

1-24

Signetics

SO Availability List

Linear Products

PART
NUMBER

SMD
PACKAGE

ADC0820D
'DAC08ED
'LF398D
LM1870D
LM2901D
LM2903D
LM311D
LM319D

SOL-20
SO-16
SO-14
SOL-20
SO-14
SO-8
SO-8
SO-14

LM324AD
LM324D
LM339D
LM358AD
LM358D
LM393D
'MC1408-8D
MC1458D
MC1488D
MC1489D
MC1489AD
MC3302D
MC33610
MC3403D

SO-14
SO-14
SO-14
SO-8
SO-8
SO-8
SO-16
SO-8
SO-14
SO-14
SO-14
SO-14
SOL-16
SO-14

NE4558D
'NE5018D
'NE5019D
'NE5036D
NE5037D
NE5044D

SO-8
SOL-24
SOL-24
SO-14
SO-16
SO-16

NE5045D
NE5090D
NE5105/AD

SO-16
SOL-16
SO-8

NE5170A
NE5180A
NE5204D
NE5205D
NE521 0

PLCC-28
PLCC-28
SO-8
SO-8
SO-14

NE5212D8

SO-8

NE522D

SO-14

NE5230D
NE527D

SO-8
SO-14

NE529D

SO-14

February 1987

PART
NUMBER

DESCRIPTION
8-Bit CMOS AID
8-Bit 0/ A Converter
Sample-and-Hold Amp
Stereo Demodulator
Quad Volt Comparator
Dual Volt Comparator
Voltage Comparator
High-Speed Dual
Comparator
Quad Op Amp
Quad Op Amp
Quad Volt Comparator
Dual Op Amp
Dual Op Amp
Dual Comparator
8-Bit 0/ A Converter
Dual Op Amp
Quad Line Driver
Quad Line Receiver
Quad Line Receiver
Quad Volt Comparator
Low Power FM IF
Quad Low Power Op
Amp
Dual Op Amp
8-Bit 0/ A Converter
8-Bit 0/ A Converter
6-Bit AID Converter
6-Bit AID Converter
Prog 7-Channel
Encoder
7-Channel Decoder
Address Relay Driver
High-Speed
Comparator
Octal Line Driver
Octal Line Receiver
High-Frequency Amp
High-Frequency Amp
High-Speed Dual
Comparator
Transimedance
Amplifier
High-Speed Dual
Comparator
Low Voltage Op Amp
High-Speed
Comparator
High-Speed
Comparator

1-25

SMD
PACKAGE

NE532D
'NE544D
'NE5512D
'NE5514D
NE5517D
NE5520D
'NE5532D

SO-8
SOL-16
SO-8
SOL-16
SO-16
SOL-16
SOL-16

'NE5533D
NE5534AD
NE5534D
NE5537D
NE5539D

SOL-16
SO-8
SO-8
SO-14
SO-14

NE555D
NE556D
NE5560D
NE5561D
NE5562D
NE5568D
NE558D
NE5592D
NE564D
'NE565D
NE566D
NE567D
NE568D
NE571D
NE572D
'NE587D

SO-8
SO-14
SO-16
SO-8
SOL-20
SO-8
SOL-16
SO-14
SO-16
SO-14
SO-8
SO-8
SOL-20
SOL-16
SOL-16
SOL-20

'NE589D

SOL-20

NE5900D
NE592D14
NE592D8
NE592HD14
NE592HD8
'NE594D
NE602D

SOL-16
SO-14
SO-8
SO-14
SO-8
SOL-20
SO-8

NE604D

SO-16

NE605
NE612D

SOL-20
SO-8

NE614D

SO-16

'PCD3311TD

SO-16

DESCRIPTION
Dual Op Amp
Servo Amp
Dual Hi-Perf Op Amp
Quad Hi-Perf Op Amp
Dual Hi-Perf Amp
LVDT Signal Cond Ckt
Dual Low-Noise Op
Amp
Low-Noise Op Amp
Low-Noise Op Amp
Low-Noise Op Amp
Sample-and-Hold Amp
Hi-Freq Amp
Wideband
Single Timer
Dual Timer
SMPS Control Ckt
SMPS Control Ckt
SMPS Control Ckt
SMPS Control Ckt
Quad Timer
Dual Video Amp
Hi-Frequency PLL
Phase Locked Loop
Function Generator
Tone Decoder PLL
PLL
Compandor
Prog Compandor
7 Seq LED Driver
(Anode)
7 Seq LED Driver
(Cath)
Call Progress Decoder
Video Amp
Video Amp
Hi-Gain Video Amp
Hi-Gain Video Amp
Vac Fluor Disp Driver
Double Bal Mixer /
Oscillator
Low Power FM IF
System
FM IF System
Double Balanced
Mixer/Oscillator
Low Power FM IF
System
DTMF/Melody
Generator

Signetics Linear Products

SO Availability List

PART
NUMBER

SMD
PACKAGE

PCD3312TD

SO-8

PCD3315TD
PCD3360TD
PCF2100TD

SOL-28
SO-16
SOL-28

PCF2111TD

VSO-40

PCF2112TD

VSO-40

PCF8570TD
PCF8571TD
PCF8573TD
PCF8574TD
PCF8576TD
PCF8577TD

SO-8
SO-8
SO-16
SO-16
VSO-56
VSO-40

SA5105/AD

SO-8

SA5230D
SA5212D8
SA532D
SA534D
SA555D
SA571D
SA572D
'SA594D
SA602D

SO-8
SO-8
SO-8
SO-14
SO-8
SOL-16
SOL-16
SOL-20
SO-8

SA604D

SO-16

PART
NUMBER

DESCRIPTION
DTMF/Melody
Generator With ICC
Repertory Pulse Dial
Progress Tone Ringer
LCD Duplex Driver
(40)
LCD Duplex Driver
(64)
LCD Duplex Driver
(32)
Static RAM (256 X 8)
1K Serial RAM
Clock/Timer
Remote I/O Expander
MUX/Static Driver
32-/64-Segment LCD
Driver
High-Speed
Comparator
Low Voltage Op Amp
Transimpedance Amp
Dual Op Amp
Dual Op Amp
Single Timer
Compandor
Compandor
Vac Fluor Disp Driver
Double Bal Mixer /
Oscillator
Lower Power FM IF
System

SMD
PACKAGE

SAA3004TD
SG3524D
TDA1001BTD
TDA1005ATD
TDA3047TD
TDA3048TD
TDA5040TD

SOL-20
SO-16
SO-16
SO-16
SO-16
SO-16
SO-8

TDA7010TD
TDA7050TD
TDD1742TD
ULN2003D
ULN2004D
j.lA723CD
I1A741CD
I1A747CD

SO-16
SO-8
SOL-28
SO-16
SO-16
SO-14
SO-8
SO-14

DESCRIPTION
R/C Transmitter
SMPS Control Circuit
Noise Suppressor
Stereo Decoder
IR Preamp
IR Preamp
Brushless DC Motor
Driver
FM Radio Circuit
Mono/Stereo Amp
Frequency Synthesizer
Transistor Array
Transistor Array
Voltage Regulator
Single Op Amp
Dual Op Amp

NOTE:
""Non-standard pinout.

UNDER DEVELOPMENT
PART
NUMBER
26LS31D
26LS32D
26LS33D
26LS29D
26LS30D

SMD
PACKAGE
SO-16
SO-16
SO-16
SO-16
SO-16

DESCRIPTION
RS-422
RS-422
RS-422
RS-423
RS-423

Line
Line
Line
Line
Line

NOTE:
For information regarding additional SO products released since the publication of this document, contact your local Signetics Sales Office,

February 1987

1-26

Driver
Receiver
Receiver
Driver
Receiver

Signetics

Ordering Information
for Prefixes ADC, AM, CA, DAC,
ICM, LF, LM, MC, NE, OP, SA,
SE, SG, pA, UC, ULN

Linear Products

Signetics' Linear integrated circuit products may be ordered by contacting either
the local Signetics sales office, Signetics
representatives and/or Signetics authorized distributors. A complete listing is
located in the back of this manual.

Table 1. Part Number Description
PART NUMBER

CROSS REF
PART NO.

.!'!E.~~lr"!

PRODUCT
DESCRIPTION

PRODUCT
FAMILY

LF398

LIN

Sample-and-Hold Arne

L

Minimum Factory Order:
Commercial Product:

Description of
Product Function

$1000 per order
$250 per line item per order
Military Product:
$250 per line item per order

~ Linear Product Family

Table 1 provides part number information concerning Signetics originated
products.
Table 2 is a cross reference of both the
old and new package suffixes for all
presently existing types, while Tables 3
and 4 provide appropriate explanations
on the various prefixes employed in the
part number descriptions.

~ Package Descriptions -

Device Number
Device Family and Temperature Range Prefix Tables 3 & 4

As noted in Table 3, Signetics defines
device operating temperature range by
the appropriate prefix. It should be noted, however, that an SE prefix (-55°C to
+ 125°C) indicates only the operating
temperature range of a device and not
its military qualification status. The military qualification status of any Linear
product can be determined by either
looking in the Military Data Manual and/
or contacting your local sales office.

February 1987

See Table 2

1-27

See

•

Signetics Linear Products

Ordering Information

Table 2. Package Descriptions
OLD

NEW

A, AA
A

N
N-14

B, BA

N
D

F

F

I,IK

I

K
L

H
H

NA, NX

N

R

Q

Q,

T, TA
U
V
XA
XC
XC
XL, XF

H
U
N
N
N
N
N
A
EC
FE

February 1987

PACKAGE
DESCRIPTION

14-lead plastic DIP
14-lead plaslic DIP
(selected analog
products only)
16-lead plastic DIP
Microminiature
package (SO)
14-, 16-, 18-, 22-,
and 24-lead
ceramic DIP
(Cerdip)
14-, 16-, 18-, 22-,
28-, and 4-lead
ceramic DIP
1O-Iead TO-l 00
10-lead high-profile
TO-l00 can
24-lead plastic DIP
10-, 14-, 16-, and
24-lead ceramic
flat
8-lead TO-99
SIP plastic power
8-lead plastic DIP
18-lead plastic DIP
20-lead plastic DIP
22-lead plastic DIP
28-lead plastic DIP
PLCC
TO-46 header
8-lead ceramic DIP

Table 3. Signetics Prefix and
Device Temperature
PREFIX

DEVICE TEMPERATURE
RANGE

NE
SE
SA

o to +70·C
-55·C to + 125·C
-40·C to +85·C

Table 4. Industry Standard Prefix
PREFIX

ADC
AM
CA
DAC
ICM
LF
LM
MC
NE
OP
SA
SE
SG
/lA
UC
ULN

DEVICE FAMILY

Linear
Linear
Linear
Linear
Linear
Linear
Linear
Linear
Linear
Linear
Linear
Linear
Linear
Linear
Linear
Linear

Industry
Industry
Industry
Industry
Industry
Industry
Industry
Industry
Industry
Industry
Industry
Industry
Industry
Industry
Industry
Industry

1-28

Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard

Signetics

Ordering Information
for Prefixes HE, OM, MA, ME,
PC, PN, SA, T8, TC, TO, TE

Linear Products

Signetics' integrated circuit products
may be ordered by contacting either the
local Signetics sales office, Signetics
representatives and/or Signetics authorized distributors.

Minimum Factory Order:
Commercial Product:

$ 1000 per order
$ 250 per line item per order
Table 1 provides part number information concerning Signetics/Philips integrated circuits.
Table 2 provides package suffixes and
descriptions for all presently existing
types. Letters following the device number not used in Table 2 are considered
to be part of the device number.
Table 3 provides explanations on the
various prefixes employed in the part
number descriptions. As noted in Table
3, Signetics/Philips device operating
temperature is defined by the appropriate prefix.

OPERATING TEMPERATURE:
The third letter of the prefix, in a threeletter prefix, is the temperature designator.
The letters A to F give information about
the operating temperature:
A: Temperature range not specified.
See data sheet.
e.g. TDA2541 N
B: 0 to +70°C
e.g. PCB8573PN
C: -55°C to + 125°C
e.g. PCC2111 PN
D: -25°C to + 70°C
e.g. PCD8571 PN
E: -25°C to + 85°C
e.g. PCE2111 PN
F: -40°C to + 85°C
e.g. PCF2111 PN

February 1987

Table 1. Part Number Description
PART
NUMBER

L

lP~~5~.1

PRODUCT
DESCRIPTION

PRODUCT
FAMILY

l

N

LIN

Video IF Amplifier
LDescriPtion of
Product Function
Product Family Linear

Package Description - See Table 2A
L..-_-Device Number
'------_Device Family and Temperature Range Prefix-See Table 3A

Table 2. Package Description
SUFFIX
PN
TD
DF
U

PACKAGE DESCRIPTION
8-, 14-, 16·, 18-, 20-, 24-, 28-, 40-lead plastic DIP
Microminiature Package (SO)
14-, 16-, 18-, 22-, 24-lead ceramic DIP
Single in-line plastic (SIP) and SIP power packages

Table 3. Device Prefix
PREFIX

DEVICE FAMILY

HEx
OM
MAx
MEx

CMOS circuit
Linear circuit
Microcomputer
Microcomputer peripheral

PCx
PNx

CMOS circuit
NMOS circuit

SAx
TBx
lCx
TDx
lEx

Digital
Linear
Linear
Linear
Linear

1-29

circuit
circuit
circuit
circuit
circuit

Signetics

Section 2
Quality and Reliability

Linear Products

INDEX
Signetics Zero Defects..............................................................................
Linear Division Quality and Reliability...........................................................
Linear Division Product Flow ......................................................................

2-3
2-5
2-7

"Given the increasingly intense competitive
pressures our customers face, they should
demand nothing less than zero defects
from every IC vendor. We now know that
zero defects is an achievable goal. Why
should IC customers pay for errors?"
Norman Neumann
President
Signetics Corporation

Signetics

Quality and Reliability

..
I

Linear Products

SIGNETICS' ZERO DEFECTS
PROGRAM
In recent years, American industry has demanded increased product quality of its IC
suppliers in order to meet growing international competitive pressures. As a result of this
quality focus, it is becoming clear that what
was once thought to be unattainable - zero
defects - is, in fact, achievable.
The IC supplier committed to a standard of
zero defects provides a competitive advantage to today's electronics OEM. That advantage can be summed up in four words:
reduced cost of ownership. As IC customers
look beyond purchase price to the total cost
of doing business with a vendor, it is apparent
that the quality-conscious supplier represents
a viable cost reduction resource. Consistently
high quality circuits reduce requirements for
expensive test equipment and personnel, and
allow for smaller inventories, less rework, and
fewer field failures.

REDUCING THE COST OF
OWNERSHIP THROUGH TOTAL
QUALITY PERFORMANCE
Quality involves more than just IC's that work.
It also includes cost-saving advantages that
come with error-free service - on-time delivery of the right quantity of the right product at
the agreed-upon price. Beyond the product,
you want to know you can place an order and
feel confident that no administrative problems
will arise to tie up your time and personnel.
Today, as a result of Signetics' growing
appreciation of the concern with cost of
ownership, our quality improvement efforts
extend out from the traditional areas of product conformance into every administrative
function, including order entry, scheduling,
delivery, shipping, and invoicing. Driving this
process is a Corporate Quality Improvement
Team, comprised of the president and his
staff, which oversees the activities of 30 other
Quality Improvement Teams throughout the
company.

CUSTOMER/VENDOR
COOPERATION IS AT THE
HEART OF ZERO DEFECTS
AND REDUCED COSTS
Working to a zero defects standard requires
that emphasis be consistently placed, not on
February 1987

"catching" defects, but on preventing them
from ever occurring. This strong preventive
focus, which demands that quality be "built-in"
rather than "inspected in," includes a much
greater attention to ongoing communication on
quality-related issues. At Signetics, a focus on
this cooperative approach has resulted in better service to all customers and the development of two innovative customer /vendor programs: Ship-to-Stock and Self-Qual.
As a result of their participation in the Ship-toStock Program, many of our customers have
eliminated costly incoming testing on selected ICs. We will work together with any customer interested to establish a Ship-to-Stock
Program, and identify the products to be
included in the program and finalize all necessary terms and conditions. From that point,
the specified products can go directly from
the receiving dock to the assembly line or into
inventory. Signetics then provides, free of
charge, monthly reports on those products.
In our efforts to continually reduce cost of
ownership, we are now using the experience
we have gained with Ship-to-Stock to begin
developing a Just-in-Time Program. With Justin-Time, products will be delivered to the
receiving dock just as they are needed, permitting continuous-flow manufacturing and eliminating the need for expensive inventories.
Like Ship-to-Stock, our Self-Qual Program
employs a cooperative approach based on
ongoing information exchange. At Signetics,
formal qualification procedures are required
for all new or changed materials, processes,
products, and facilities. Prior to 1983, we
created our qualification programs independently. Our major customers would then test
samples to confirm our findings. Now, under
the new Self-Qual Program, customers can
be directly involved in the prequalification
stage. When we feel we have a promising
enhancement to offer, customers will be invited to participate in the development of the
qualification plan. This eliminates the need to
duplicate expensive qualification testing and
also adds another dimension to our ongoing
efforts to build in quality.

PRODUCT RELIABILITY:
QUALITY OVER TIME IS THE
GOAL
Our concern with product reliability has developed from communication with many customers. In discussions, these customers have

2-3

emphasized the high cost of field failures,
both in terms of dollars and reputations in the
marketplace.
In response to these concerns, we have
placed an emphasis on improving product
reliability. As a result of this effort, our product
reliability has improved more than fourfold in
a five-year period (see Figure 1). A key
program, SURE (Systematic and Uniform Reliability Evaluation), highlights the significant
progress made in this critical area.
SURE was first instituted in 1964 as the core
reliability measurement for all Signetics products. In 1980, as a first major step toward
improving product reliability, SURE was enhanced by increasing sampling frequency and
size and by extending stress tests. As a result
of these improvements, most of our major
customers now utilize SURE data with no
requests for additional reliability testing.

WE WANT TO WORK WITH
YOU
At Signetics, we know that our success depends on our ability to support all our customers with the defect-free, higher density, higher
performance products needed to compete
effectively in today's demanding business
environment. To achieve this goal, quality in
another arena - that of communicationsis vital. Here are some specific ways we can
maintain an ongoing dialogue and information
exchange between your company and ours
on the quality issue:
• Periodical face-to-face exchanges of
data and quality improvement ideas
between the customer and Signetics
can help prevent problems before they
occur.
• Test correlation data is very useful. Line
pull information and field failure reports
also help us improve product
performance.
• When a problem occurs, provide us as
soon as possible with whatever specific
data you have. This will assist us in
taking prompt corrective action.
Quality products are, in large measure, the
result of quality communication. By working
together, by opening up channels through
which we can talk openly to each other, we
will insure the creation of the innovative,
reliable, cost effective products that help
insure a competitive edge.

Signetics Linear Products

Quality and Reliability

~r-----------------------~F=====~~~~

__________________________

~~~~:L-

~~~~~-----------------------------------~~~,~~~'~~~-===~------------------------------

~~~~~~~~~-------------------------

1984

1985

1986

1987

1988

1989

1990

TIME FRAME

Figure 1

QUALITY AND RELIABILITY
ASSURANCE

LINEAR PRODUCT QUALITY

• Customer liaison

Signetics has put together a winning process
for the manufacturing of Linear Integrated
Circuits. The circuits produced by our Linear
Division must meet rigid criteria as defined in
our design rules and as evaluated through
product characterization over the device operating temperature range. Product conformance to specification is measured throughout the manufacturing cycle. Our standard is
Zero Defects and our ,customers' statistics
and awards for outstanding product quality
demonstrate our advance toward this goal.

The result of this continual involvement at all
stages of production enables us to provide
feedback to refine present and future designs, manufacturing processes, and test
methodology to enhance both the quality and
reliability of the products delivered to our
customers.

Nowhere is this more evident than at our
Electrical Outgoing Product Assurance inspection gate. Over the past six years, the
measured defect level at the first submission
to Product Assurance for Linear products has
dropped from over 4000PPM (0.4%) to under
150PPM (0.015%) (see Figure 2). Signetics

Signetics' Linear Division Quality and Reliability Assurance Department is involved in all
stages of the production of our Linear ICs:
• Product Design and Process
Development
• Wafer Fabrication
• Assembly
• Inspection and Test
• Product Reliability Monitoring

February 1987

2-4

calls the first submittal to a Product or Quality
Assurance gate our Estimated Process Quality or EPQ. It is an internal measure used to
drive our Quality Improvement Programs toward our goal of Zero Defects. All product
acceptance sampling plans have zero as their
acceptance criteria. Only shipments that
demonstrate zero defects during these acceptance tests may be shipped to our customers. This is in accordance with our commitment to our Zero Defect policy.
The results from our Quality Improvement
Program have allowed Signetics to take the
industry leadership position with its Zero Defects Limited Warranty pOlicy. No longer is it
necessary to negotiate a mutually acceptable
AQL between buyer and Signetics. Signetics
will replace any lot in which a customer finds
one verified defective part.

Signetics Linear Products

Quality and Reliability

~~----------------------------------------------~

4200

Ffgure 2. Electrical Estimated Process Quality (EPQ)

QUALITY DATABASE
REPORTING SYSTEM - QA05
The capabilities of our manufacturing process
are measured and the results are recorded
through our corporate-wide QA05 database
system. The QA05 system collects the results
on all finished lots and feeds this data back to
concerned organizations where appropriate
corrective actions can be taken. The QA05
reports Estimated Process Quality (EPQ) data
which are the sample inspection results for
first submittal lots to Quality Assurance inspection for electrical. visual/mechanical.
hermeticity. and documentation. Data from
this system is available upon request and is
distributed routinely to our customers who
have formally adopted our Ship-to-Stock program.

SIGNETICS' SHIP-TO-STOCK
PROGRAM
Ship-to-Stock is a joint program between
Signetics and a customer which formally
certifies specific parts to go directly into
inventory or to the assembly line from the
February 1987

customer's receiving dock without incoming
inspection. This program was developed at
the request of several major customers after
they had worked with us and had a chance to
experience the data exchange and joint corrective action that occurs as part of our
quality improvement program.
The key elements of the Ship-to-Stock program are:
• Signetics and customer agree on a list
of products to be certified, complete
device correlation, and sign a
specification.
• The product Estimated Product Quality
(EPQ) must be 300ppm or less for the
past 3 months.
• Signetics will share Quality (QA05) and
Reliability data on a regular basis.
• Signetics will alert Ship-to-Stock
customers of any changes in quality or
reliability which could adversely impact
their product.
Any customer interested in the benefits of the
Ship-to-Stock program should contact his

2-5

local Signetics sales office for a brochure and
further details.

RELIABILITY BEGINS WITH THE
DESIGN
Quality and reliability must begin with design.
No amount of extra testing or inspection will
produce reliable ICs from a design that is
inherently unreliable. Signetics follows very
strict design and layout practices with its
circuits. To eliminate the possibility of metal
migration, current density in any path cannot
exceed 5 X 105 amps/ cm 2 . Layout rules are
followed to minimize the possibility of shorts,
circuit anomalies, and SCR type latch-up
effects. All circuit designs are computerchecked using the latest CAD software for
adherence to design rules. Simulations are
performed for functionality and parametric
performance over the full operating ranges of
voltage and temperature before going to
production. These steps allow us to meet
device specifications not only the first time,
but also every time thereafter.

•

Signetics Linear Products

Quality and Reliability

PRODUCT CHARACTERIZATION
Before a new design is released, the characterization phase is completed to insure that
the distribution of parameters resulting from
lol-Io-Iot varialions is well wilhin specified
limits. Such extensive characterization data
also provides a basis for identifying unique
application-related problems which are not
part of normal data sheet guarantees.

PRODUCT QUALIFICATION
Linear products are subjected to rigorous
qualification procedures for all new products
or redesigns to current products. Qualification
testing consists of:
• High Temperature Operating Life:
TJ = 150·C, 1000 hours, static bias
• High Temperature Storage Life:
TJ = 150·C, 1000 hours, unbiased
• Temperature Humidity Biased Life:
85·C, 85% relative humidity, 1000
hours, static bias
• Pressure Cooker:
15 psig, 121 ·C, 192 hours, unbiased
• Thermal Shock:
-65·C to + 150·C, 300 cycles, 5 minute
dwell, liquid to liquid, unbiased
Formal qualification procedures are required
for all new or changed products, processes,
and facilities. These procedures ensure the
high level of product reliability our customers
expect. New facilities are qualified by corporate groups as well as by the quality organizations of specific units that will operate in the
facility. After qualification, products manufactured by the new facility are subjected to
highly accelerated environmental stresses to
ensure that they can meet rigorous failure
rate requirement\;. New or changed processes are similarly qualified.

ONGOING RELIABILITY
ASSESSMENT PROGRAMS
The SURE Program
The SURE (Systematic and Uniform Reliability Evaluation) program audits products from
each of Signetics Linear Division's process
families: Low Voltage, Medium Voltage, High
Voltage, and Dual-Layer Metal, under a variety of accelerated stress conditions. This
program, first introduced in 1964, has evolved
to suit changing product complexities and
performance requirements.

The Audit Program
Samples are selected from each process
family every four weeks and are subjected to
each of the following stresses:
• High Temperature Operating Life:
TJ = 150·C, 1000 hours, static bias
• High Temperature Storage Life:
TJ = 150·C, 1000 hours, unbiased
• Temperature Humidity Biased Life:
85·C, 85% relative humidity, 1000
hours, static bias
• Pressure Cooker:
20 psig, 127·C, 72 hours, unbiased
• Thermal Shock:
-65·C to + 150·C, 300 cycles, 5 minute
dwell, liquid-to-liquid, unbiased
• Temperature Cycling:
-65·C to +150·C, 1000 cycles, 10
minute dwell, air-to-air, unbiased

The Product Monitor Program
In addition, each Signetics assembly plant
performs Pressure Cooker and Thermal
Shock SURE Product Monitor stresses on a
weekly basis on each molded package by pin
count per the same conditions as the SURE
Program.

Product Reliability Reports
The data from these test matrices provides a
basic understanding of product capability, an
indication of major failure mechanisms, and
an estimated failure rate resulting from each
stress. This data is compiled periodically and
is available to customers upon request.

February 1987

2-6

Many customers use this information in lieu of
running their own qualification tests, thereby
eliminating time-consuming and costly additional testing.

Reliability Engineering
In addition to the product performance monitors encompassed in the Linear SURE program, Signetics' Corporate and Division Reliability Engineering departments sustain a
broad range of evaluation and qualification
activities.
Included in the engineering process are:
• Evaluation and qualification of new or
changed materials, assembly/wafer-fab
processes and equipment, product
designs, facilities, and subcontractors.
• Device or generic group failure rate
studies.
• Advanced environmental stress
development.
• Failure mechanism characterization and
corrective action/prevention reporting.
The environmental stresses utilized in the
engineering programs are similar to those
utilized for the SURE monitor; however, more
highly-accelerated conditions and extended
durations typify these engineering projects.
Additional stress systems such as biased
pressure pot, power-temperature cycling, and
cycle-biased temperature-humidity, are also
included in some evaluation programs.

Failure Analysis
The SURE Program and the Reliability Engineering Program both include failure analysis
activities and are complemented by corporate, divisional, and plant failure analysis
departments. These engineering units provide a service to our customers who desire
detailed failure analysis support, who in turn
provide Signetics with the technical understanding of the failure modes and mechanisms actually experienced in service. This
information is essential in our ongoing effort
to accelerate and improve our understanding
of product failure mechanisms and their prevention.

Signetics Linear Products

Quality and Reliability

LINEAR DIVISION LINEAR PROCESS FLOW

0------------

I

0------------

SCANNING ELECTRON MICROSCOPE CONTROL
Wafers are sampled daily by the Quality Control Laboratory from each fabrication area and subtected
to SEM analysis. This process control reveals manufacturing defects such as contact and oxide step
coverage in the metalization process which may result in early failures.

OlE SORT VISUAL ACCEPTANCE

Product is inspected for defects caused during fabrication, wafer testing, or the mechanical scribe
and break operation. Defects such as scratches, smears and glassivaled bonding padS are included
in the lot acceptance criteria.
DIE ATTACH AND WIRE BONDING

The latest automated equipment is used under statistical process control program.

o _______ - - - _ _

PRE·SEAL VISUAL ACCEPTANCE

Product is inspected to detect any damage incurred at the die attach and wire bonding stations.
Defects such as scratches, contamination and smeared ball bonds are included in the lot acceptance
criteria.

__________ SEAL TESTS
Hermetic package seal Integrity is ensured by 100% and fine gross leak testing.

SYMBOL
Devices are marked with the Signetics logo, device number and period date code of assembly or
custom symbol per mdividual specification requirements.

________ 100% PRODUCTION ELECTRICAL TESTING
Every device is tested to aU data sheet parameters guaranteeing temperature specifications.

BURN-IN (SUPR U LEVEL B OPTION)
Devices are burned in lor 21 hours at 155°C maximum Junction Temperature.

1000;" PRODUCTION ELECTRICAL TESTING
Every device is tested to all data sheet parameters guaranteeing temperature specifications.

________ VISUAL

L...""'::::::":;;::::'::::::".....I

All products are visually inspected per the requirements specified in Signetics' or customer
documents.

_ _ _ _ _ _ _ _ FINAL QUALITY ASSURANCE GATE
The final QA inspection step guarantees the specified mechanical and electrical AQL's. Every shipment is sealed and identified by QA personnel.

February 19B7

2-7

Signetics

Section 3
Small Area Networks

Linear Products

II
INDEX
Introduction to 12C ...................................................................................
12 C Bus Specification................................................................................
AN168
The Inter-Integrated Circuit (12C) Serial Bus: Theory and
Practical Considerations.......................................................

3-3
3-4
3-16

Signetics

Introduction to 12C

Linear Products

THE 12C CONCEPT
The Inter-IC bus (12C) is a 2-wire serial bus
designed to provide the facilities of a small
area network, not only between the circuits of
one system, but also between different systems; e.g., teletext and tuning.
Philips/Signetics manufactures many devices
with built-in 12C interface capability, any of
which can be connected in a system by
simply "clipping" it to the 12 C bus. Hence, any
collection of these devices around the 12C
bus is known as "clips."
The 12 C bus consists of two bidirectional
lines: the Serial Data (SDA) line and the Serial
Clock (SCl) line. The output stages of devices connected to the bus (these devices
could be NMOS, CMOS, 12C, TIL, ... ) must
have an open-drain or open-collector in order
to perform the wired-AND function. Data on

February 1987

the 12C bus can be transferred at a rate up to
100kbits/sec. The physical bus length is
limited to 13 feet and the number of devices
connected to the bus is solely dependent on
the limiting bus capacitance of 400pF.
The inherent synchronization process, built
into the 12C bus structure using the wiredAND technique, not only allows fast devices
to communicate with slower ones, but also
eliminates the "Carrier Sense Multiple Access/Collision Detect" (CSMA/CD) effect
found in some local area networks, such as
Ethernet.
12 C

Master-slave relationships exist on the
bus; however, there is no central master.
Therefore, a device addressed as a slave
during one data transfer could possibly be the
master for the next data transfer. Devices are

also free to transmit or receive data during a
transfer.
To summarize, the 12C bus eliminates interfacing problems. Since any peripheral device
can be added or taken away without affecting
any other devices connected to the bus, the
12C bus enables the system designer to build
various configurations using the same basic
architecture.
Application areas for the 12C bus include:
Video Equipment
Audio Equipment
Computer Terminals
Home Appliances
Telephony
Automotive
Instrumentation
Industrial Control

3-3

•

Signetics

12C Bus
Specification

Linear Products

INTRODUCTION
For 8-bit applications, such as those requiring
single-chip microcomputers, certain design
criteria can be established:
• A complete system usually consists
of at least one microcomputer and
other peripheral devices, such as
memories and 1/0 expanders.
• The cost of connecting the various
devices within the system must be
kept to a minimum.
• Such a system usually performs a
control function and does not require
high-speed data transfer.
• Overall efficiency depends on the
devices chosen and the
Interconnecting bus structure.
In order to produce a system to satisfy these
criteria, a serial bus structure is needed.
Although serial buses don't have the through·
put capability of parallel buses, they do require less wiring and fewer connecting pins.
However, a bus is not merely an interconnecting wire, it embodies all the formats and
procedures for communication within the system.
Devices communicating with each other on a
serial bus must have some form of protocol
which avoids all possibilities of confusion,
data loss and blockage of information. Fast
devices must be able to communicate with
slow devices. The system must not be depen·
dent on the devices connected to it, otherwise modifications or improvements would be
impossible. A procedure has also to be resolved to decide which device will be in
control of the bus and when. And if different
devices with different clock speeds are connected to the bus, the bus clock source must
be defined.

a receiver, while a memory can both receive
and transmit data. In addition to transmitters
and receivers, devices can also be consid·
ered as masters or slaves when performing
data transfers (see Table 1). A master is the
device which initiates a data transfer on the
bus and generates the clock signals to permit
that transfer. At that time, any device addressed is considered a slave.
The 12C bus is a multi-master bus. This means
that more than one device capable of controlling the bus can be connected to it. As
masters are usually microcomputers, let's
consider the case of a data transfer between
two microcomputers connected to the 12C
bus (Figure 1). This highlights the masterslave and receiver-transmitter relationships to
be found on the 12 C bus. It should be noted
that these relationships are not permanent,
but only depend on the direction of data
transfer at that time. The transfer of data
would follow in this way:
1) Suppose microcomputer A wants to send
information to microcomputer B
- microcomputer A (master) addresses
microcomputer B (slave)
- microcomputer A (master transmitter)
sends data to microcomputer B (slave
receiver)
- microcomputer A terminates the
transfer.
2) If microcomputer A wants to receive information from microcomputer B

- microcomputer A (master) addresses
microcomputer B (slave)
- microcomputer A (master receiver)
receives data from microcomputer B
(slave transmitter)
- microcomputer A terminates the
transfer.
Even in this case, the master (microcomputer
A) generates the timing and terminates the
transfer.
The possibility of more than one microcomputer being connected to the 12C bus means
that more than one master could try to initiate
a data transfer at the same time. To avoid the
chaos that might ensue from such an event,
an arbitration procedure has been developed.
This procedure relies on the wired-AND connection of all devices to the 12 C bus.
If two or more masters try to put information
on to the bus, the first to produce a one when
the other produces a zero will lose the
arbitration. The clock signals during arbitration are a synchronized combination of the
clocks generated by the masters using the
wired·AND connection to the SCl line (for
more detailed information concerning arbitration see Arbitration and Clock Generation).
Generation of clock signals on the 12 C bus is
always the responsibility of master devices;
each master generates its own clock signals
when transferring data on the bus. Bus clock
signals from a master can only be altered
when they are stretched by a slow slave

All these criteria are involved in the specification of the 12C bus.

THE 12C BUS CONCEPT
Any manufacturing process (NMOS, CMOS,
12 l) can be supported by the 12C bus. Two
wires (SDA - serial data, SCl - serial clock)
carry information between the devices con·
nected to the bus. Each device is recognized
by a unique address - whether it is a micro·
computer, LCD driver, memory or keyboard
interface - and can operate as either a transmitter or receiver, depending on the function
of the device. Obviously an LCD driver is only
February 1987

Figure 1. Typical 12C Bus Configuration

3·4

Signetics Linear Products

12C Bus Specification

Table 1. Definition of 12C Bus Terminology
TERM

device holding down the clock line or by
another master when arbitration takes place.

DESCRIPTION

Transmitter

The device which sends data to the bus

Receiver

The device which receives data from the bus

Master

The device which initiates a transfer, generates clock
signals and terminates a transfer

Slave

The device addressed by a master

Multi-master

More than one master can attempt to control the
bus at the same time without corrupting the message

Arbitration

Procedure to ensure that if more than one master
simultaneously tries to control the bus, only one is
allowed to do so and the message is not corrupted

Synchronization

Procedure to synchronize the clock signals of two or
more devices

GENERAL CHARACTERISTICS
Both SDA and SCL are bidirectional lines,
connected to a positive supply voltage via a
pull-up resistor (see Figure 2). When the bus
is free, both lines are High. The output stages
of devices connected to the bus must have
an open-drain or open-collector in order to
perform the wired-AND function. Data on the
12C bus can be transferred at a rate up to
100kbitls. The number of devices connected
to the bus is solely dependent on the limiting
bus capacitance of 400pF.

BIT TRANSFER
-'t--1P----

+VDD

SDA (SERIAL DATA UNE)

+-___~___-._____+-__

SCL~~~ER_~_L_C_~_K.U_N_E)~_ _ _

r------

-I

I

I

II

SCLK1

mrr

II II

-.J

I
I

II

I
I

-I

j-----I

I
SCiJ( 2

I

-.J

OUT
I
I
I
I
I
I SCLK
DATA
I
IN
IN
L ________________
...J

I
1_______________ ...JI I
SCLK
IN

DATA
IN

DEVlCE1

I

Due to the variety of different technology
devices (CMOS, NMOS, 12L) which can be
connected to the 12C bus, the levels of the
logical 0 (Low) and 1 (High) are not fixed and
depend on the appropriate level of VD D (see
Electrical Specifications). One clock pulse is
generated for each data bit transferred.

Data Validity
The data on the SDA line must be stable
during the High period of the clock. The High
or Low state of the data line can only change
when the clock signal on the SCL line is Low
(Figure 3).

Start and Stop Conditions
Within the procedure of the 12C bus, unique
situations arise which are defined as start and
stop conditions (see Figure 4).

DEVICE 2

Figure 2. Connection of Devices to the 12 C Bus

A High-to-Low transition of the SDA line while
SCL is High is one such unique case. This
situation indicates a start condition.
A Low-to-High transition of the SDA line while
SCL is High defines a stop condition.
Start and stop conditions are always generated by the master. The bus is considered to be
busy after the start condition. The bus is
considered to be free again a certain time
after the stop condition. This bus free situation will be described later in detail.

Figure 3_ Bit Transfer on the 12 C Bus

SDA

1\1
I

SCL

I

C~

in
I

I

--r-:--t"
r~
rtjL~ J '----.I 'L../ L~ J

srART CONDITION

STOP CONDITION

SCL

TRANSFERRING DATA

Byte Format
Every byte put on the SDA line must be 8 bits
long. The number of bytes that can be
transmitted per transfer is unrestricted. Each
byte must be followed by an acknowledge bit.

Figure 4. Start and Stop Conditions

February 1987

SDA

Detection of start and stop conditions by
devices connected to the bus is easy if they
possess the necessary interfacing hardware.
However, microcomputers with no such interface have to sample the SDA line at least
twice per clock period in order to sense the
transition.

3·5

•

Signetics Linear Products

12C Bus Specification

r-..,

r-,

SDANaX
I
I
I
I

I
I
I
I

I
I

I
I

I

~

MS8

ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER

BYTE COMPLETE,
INTERRUPT WITHIN RECEIVER

I

CLOCK UNE HELD IDW WHILE
INTERRUPTS ARE SERVICED

SCL~
~ ~
is iV'V 'y
2

I
I
I
I
I
I
I

3~V:CK\..J
r:- rt--t
i i
-8

L_...l

I
I
I
I
I
I
I

P

L_J

START

SlOP

CONDmON

CONDITION

Figure 5. Data Transfer on the 12C Bus

DATA OUTPUT
BYTRANSMmER

-R
II

I

/

\l1_"'~

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I

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':":~=~ I I
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t ·

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SCL~~II

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S i t

IL:J

START
CONDmON

CIDCK PULSE FOR
ACKNOWLEDGEMENT

Figure 6. Acknowledge on the 12C Bus

Data is transferred with the most significant
bit (MSB) first (Figure 5). If a receiving device
cannot receive another complete byte of data
until it has performed some other function, for
example, to service an internal interrupt, it
can hold the clock line SCL Low to force the
transmitter into a wait state. Data transfer
then continues when the receiver is ready for
another byte of data and releases the clock
line SCL.
In some cases, it is permitted to use a
different format from the 12C bus format, such
as CBUS compatible devices. A message
which starts with such an address can be
terminated by the generation of a stop condition, even during the transmission of a byte.
In this case, no acknowledge is generated.

Acknowledge
Data transfer with acknowledge is obligatory.
The acknowledge-related clock pulse is generated by the master. The transmitting device
releases the SDA line (High) during the acknowledge clock pulse.

February 1987

The receiving device has to pull down the
SDA line during the acknowledge clock pulse
so that the SDA line is stable Low during the
high period of this clock pulse (Figure 6). Of
course, setup and hold times must also be
taken into account and these will be described in the Timing section.
Usually, a receiver which has been addressed
is obliged to generate an acknowledge after
each byte has been received (except when
the message starts with a CBUS address.
When a slave receiver does not acknowledge
on the slave address, for example, because it
is unable to receive while it is performing
some real-time function, the data line must be
left High by the slave. The master can then
generate a STOP condition to abort the
transfer.
If a slave receiver does acknowledge the
slave address, but some time later in the
transfer cannot receive any more data bytes,
the master must again abort the transfer. This
is indicated by the slave not generating the
acknowledge on the first byte following. The

3·6

slave leaves the data line High and the
master generates the STOP condition.
In the case of a master receiver involved in a
transfer, it must signal an end of data to the
slave transmitter by not generating an acknowledge on the last byte that was clocked
out of the slave. The slave transmitter must
release the data line to allow the master to
generate the STOP condition.

ARBITRATION AND CLOCK
GENERATION

Synchronization
All masters generate their own clock on the
SCL line to transfer messages on the 12C bus.
Data is only valid during the clock High period
on the SCL line; therefore, a defined clock is
needed if the bit·by-bit arbitration procedure
is to take place.
Clock synchronization is performed using the
wired·AND connection of devices to the SCL
LINE. This means that a High-to-Low transi-

Signetics Linear Products

12C Bus Specification

START COUNTINCl
WAIT -I-2'~H PERIOD

II
STATE
CLK

1

I
'-~

----~~----~,----------~-----~----

CLK

2---f---7~,~------------~r~4-----'~~-SCL

Figure 7. Clock Synchronization Durtng the Arbitration Procedure

TRANSMITTER 1 LOSES ARBITRAnON
DATA1~SDA

DATA

1

SCL

A master which loses the arbitration can
generate clock pulses until the end of the
byte in which it loses the arbitration,
If a master does lose arbitration during the
addressing stage, it is possible that the winning master is trying to address it. Therefore,
the losing master must switch over immediately to its slave receiver mode.

Figure 8 shows the arbitration procedure for
two masters. Of course more may be involved, depending on how many masters are
connected to the bus. The moment there is a
difference between the internal data level of
the master generating OATA 1 and the actual
level on the SOA line, its data output is
switched off, which means that a High output
level is then connected to the bus. This will
not affect the data transfer initiated by the
winning master. As control of the 12 e bus is
decided solely on the address and data sent
by competing masters, there is no central
master, nor any order of priority on the bus.

Use of the Clock Synchronizing
Mechanism as a Handshake
Figure 8. Arbitration Procedure of Two Masters

tion on the Sel line will affect the devices
concerned. causing them to start counting off
their low period, Once a device clock has
gone low it will hold the Sel line in that state
until the clock High state is reached (Figure
7). However, the low-to-High change in this
device clock may not change the state of the
Sel line if another device
clock is still within its low period. Therefore,
Sel will be held low by the device with the
longest low period. Devices with shorter low
periods enter a High wait state during this
time.
When a/l devices concerned have counted off
their low period, the clock line will be released and go High. There will then be no
difference between the device clocks and the

February 1987

Arbitration can carry on through many bits,
The first stage of arbitration is the comparison
of the address bits, If the masters are each
trying to address the same device, arbitration
continues into a comparison of the data,
Because address and data information is
used on the 12 e bus for the arbitration, no
information is lost during this process.

state of the sel line and a/l of them will start
counting their High periods. The first device
to complete its High period will again pull the
Sel line low.
In this way, a synchronized Sel clock is
generated for which the low period is determined by the device with the longest clock
low period while the High period on Sel is
determined by the device with the shortest
clock High period,

Arbitration
Arbitration takes place on the SDA line in
such a way that the master which transmits a
High level, while another master transmits a
low level, will switch off its DATA output
stage since the level on the bus does not
correspond to its own level.

3-7

In addition to being used during the arbitration
procedure, the clock synchronization mecha·
nism can be used to enable receiving devices
to cope with fast data transfers, either on a
byte or bit level.
On the byte level, a device may be able to
receive bytes of data at a fast rate, but needs
more time to store a received byte or prepare
another byte to be transmitted. Slave devices
can then hold the Sel line Low, after reception and acknowledge of a byte, to force the
master into a wait state until the slave is
ready for the next byte transfer in a type of
handshake procedure,
On the bit level, a device such as a microcomputer without a hardware 12 e interface
on-chip can slow down the bus clock by
extending each clock low period. In this way,
the speed of any master is adapted to the
internal operating rate of this device.

•

Signetics Linear Products

12C Bus Specification

FORMATS
Data transfers follow the format shown in
Figure 9. After the start condition, a slave
address is sent. This address is 7 bits long;
the eighth bit is a data direction bit (R/W). A
zero indicates a transmission (WRITE); a one
indicates a request for data (READ). A data
transfer is always terminated by a stop condition generated by the master. However, if a

master still wishes to communicate on the
bus, it can generate another start condition,
and address another slave without first generating a stop condition. Various combinations
of read/write formats are then possible within
such a transfer.
At the moment of the first acknowledge, the
master transmitter becomes a master receiv-

er and the slave receiver becomes a slave
transmitter. This acknowledge is still generated by the slave.
The stop condition is generated by the master.
During a change of direction within a transfer,
the start condition and the slave address are
both repeated, but with the R/W bit reversed.

SDAV~~~
I

I

I

I

SCLW~v.vv~
L :J
L -.J
L-----J l..-.--J L--..J

START ADDRESS
CONDITION

R/W

I

I

ACK

DATA

Figure 9_ A

Com~lete

L--..J
ACK

I

I

DATA

l..-.--J
ACK

SlOP
CONDITION

Data Transfer

Possible Data Transfer Formats are:
a) Master transmitter transmits to slave
receiver. Direction is not changed.

S

SLAVE ADDRESS

A

DATA

A

DATA

A

P

1/

A = ACKNOWLEDGE
5 = START
P = STOP

b) Master reads slave immediately after
first byte.

R/W

'O'(WRII'1!l

DATA TRANSFERREO
+ ACKNOWLEDGI!l

(II BYTES

S

SLAVE ADDRESS

Mil

A

DATA

A

DATA

A

1/
~'(READ)

DATA TRANSFERRED
+ ACKNOWLEDGE)

(II BYTES

c) Combined formats.

I S I SLAVE ADDRESS I R/W I A I DATA I A I S I SLAVE ADDRESS I R/W I A I DATA I A I p I

~J
WRITE

~

J l~n~

+ ACKNOWLEDGE)

+ ACKNOWLEDGE)

READ OR
WRITE

DIRECTION OF
TRANSFER MAY
CHANGE AT
THIS POINT

NOTES:
1. Combined formats can be used, for example, to control a serial memory. During the first data byte, the internal memory location has to be written. After the start condition is repeated,

data can then be transferred.
2. AU decisions on auto-increment or decrement of previously accessed memory locations, etc" are taken by the designer of the device.
3. Each byte is followed by an acknowledge as indicated by the A blocks in the sequence.
4. \2C devices have to reset their bus logic on receipt of a start condition so that they all anticipate the sending of a slave address.

February 1987

3-8

Signetics Linear Products

12C Bus Specification

ADDRESSING
The first byte after the start condition determines which slave will be selected by the
master. Usually, this first byte follows that
start procedure. The exception is the general
call address which can address all devices.
When this address is used, all devices
should, in theory, respond with an acknowledge, although devices can be made to
ignore this address. The second byte of the
general call address then defines the action
to be taken.

Definition of Bits in the First
Byte
The first seven bits of this byte make up the
slave address (Figure 10). The eighth bit
(LSB -least significant bit) determines the
direction of the message. A zero on the least
significant position of the first byte means that
the master will write information to a selected
slave; a one in this position means that the
master will read information from the slave.
MaB
-SLAVEADDRESS-

LSB

o

A

FIRST BYTE

X

X

X

X

X

x

I

x

B

A

SECONDBVTE

(GENERAL CALL ADDRESS)

Figure 11. General Call Address Format

H'08'

I s I "'00' I A I H'02' I A I ABCDOOO I X I A I ABCDOO1 I X I A I ABCDOIO I X I A I p I
Figure 12. Sequence of a Programming Master
biiities in group 1111 will also only be used for
extension purposes but are not yet allocated.
The combination OOOO~as been defined
as a special group. The following addresses
have been allocated:
FIRST BYTE
Slave
Address

edge this address and behave as a slave
receiver. The second and following bytes will
be acknowledged by every slave receiver
capable of handling this data. A slave which
cannot process one of these bytes must
ignore it by not acknowledging.
The meaning of the general call address is
always specified in the second byte (Figure
11 ).

R/W

Figure 10. The First Byte After the
Start Procedure

0000
0000

000
000

0
1

General call address
Start byte

There are two cases to consider:
1. When the least significant bit B is a zero.
2. When the least significant bit B is a one.

When an address is sent, each device in a
system compares the first 7 bits after the start
condition with its own address. I! there is a
match, the device will consider itsel! addressed by the master as a slave receiver or
slave transmitter, depending on the R/W bit.

0000
0000

001
010

X
X

CBUS address
Address reserved for
different bus format

When B is a zero, the second byte has the
following definition:

0000
0000
0000
0000
0000

011
100
101
110
111

X
X
X
X
X

The slave address can be made up of a fixed
and a programmable part. Since it is expected
that identical ICs will be used more than once
in a system, the programmable part of the
slave address enables the maximum possible
number of such devices to be connected to
the 12C bus. The number of programmable
address bits of a device depends on the
number of pins available. For example, if a
device has 4 fixed and 3 programmable
address bits, a total of eight identical devices
can be connected to the same bus.
12 C

The
bus committee is available to coordinate allocation of 12C addresses.
The bit combination 1111 XXX of the slave
address is reserved for future extension purposes.
The address 1111111 is reserved as the
extension address. This means that the addressing procedure will be continued in the
next byte(s). Devices that do not use the
extended addressing do not react at the
reception of this byte. The seven other possi-

February 1987

] To be defined

No device is allowed to acknowledge at the
reception of the start byte.
The CBUS address has been reserved to
enable the intermixing of CBUS and 12 C
devices in one system. 12 C bus devices are
not allowed to respond at the reception of this
address.
The address reserved for a different bus
format is included to enable the mixing of 12C
and other protocols. Only 12 C devices that are
able to work with such formats and protocols
are allowed to respond to this address.
General Call Address
The general call address should be used to
address every device connected to the 12C
bus. However, if a device does not need any
of the data supplied within the general call
structure, it can ignore this address by not
acknowledging. I! a device does require data
from a general call address, it will acknowl-

3-9

00000110 (H'06') Reset and write the programmable part of slave
address by software and
hardware. On receiving this
two-byte sequence, all devices (designed to respond
to the general call address)
will reset and take in the
programmable part of their
address.
Precautions must be taken
to ensure that a device is
not pulling down the SDA
or SCL line after applying
the supply voltage, since
these low levels would
block the bus.
00000010 (H'02') Write slave address by
software only. All devices
which obtain the programmable part of their address
by software (and which
have been designed to respond to the general call
address) will enter a mode
in which they can be programmed. The device will
not reset.

Signetics Linear Products

12C Bus Specification

An example of a data transfer of a programming master is shown in Figure 12 (ABCD
represents the fixed part of the address).

(8)

s

00000100 (H'04') Write slave address by
hardware only. All devices
which define the programmable part of their address
by hardware (and which respond to the general call
address) will latch this programmable part at the reception of this two-byte sequence. The device will not
reset.

oooooooo

A

IsI

DATA

A

P

II

+ ACKNOWLEDGE)

DUMPADDRFORH/WMASTER

IXI

A

WRITE

a. Configuring master sends dump address to hardware master

s

DUMPADDR FROM H/W MASTER

R/W

WRITE

When B is a one, the two-byte sequence is a
hardware general call. This means that the
sequence is transmitted by a hardware master device, such as a keyboard scanner,
which cannot be programmed to transmit a
desired slave address. Since a hardware
master does not know in advance to which
device the message must be transferred, it
can only generate this hardware general call
and its own address, thereby identifying itself
to the system (Figure 13).

February 1987

A

(n BYTES

Mill A I

SLAVEADDRH/WMASTER

The remaining codes have not been fixed and
devices must ignore these codes.

Start Byte
Microcomputers can be connected to the 12C
bus in two ways. If an on-chip hardware 12C
bus interface is present, the microcomputer
can be programmed to be interrupted only by
requests from the bus. When the device
possesses no such interface, it must constantly monitor the bus via software. Obvious-

DATA

Figure 13. Data Transfer From Hardware Master Transmitter

Sequences of programming procedure are
published in the appropriate device data
sheets.

In some systems an alternative could be that
the hardware master transmitter is brought in
the slave receiver mode after the system
reset. In this way, a system configuring master can tell the hardware master transmitter
(which is now in slave receiver mode) to
which address data must be sent (Figure 14).
After this programming procedure, the hardware master remains in the master transmitter mode.

A

SECOND
BYTE

GENERAL
CALL ADDRESS

00000000 (H'OO') This code is not allowed to
be used as the second
byte.

The seven bits remaining in the second byte
contain the device address of the hardware
master. This address is recognized by an
intelligent device, such as a microcomputer,
connected to the bus which will then direct
the information coming from the hardware
master. If the hardware master can also act
as a slave, the slave address is identical to
the master address.

I

1

MASTER ADDRESS

A

DATA

I

(n BYTES

A

I

DATA

I

A

P

/I

+ ACKNOWLEDGE)

b. Hardware master dumps data to selected slave device
Figure 14. Data Transfer of Hardware Master Transmitter Capable of Dumping
Data Directly to Slave Devices

II

II

SDAi\i
?~~I
I I
ACK~~:~DGE i \.lI I
I I
--r---i'
r;\ r;\
r;\. r,:-... r,:-... Jj-""ti _i \..J ' \..J • "-?~ , \..J \..J ACK\..J i _i
SOL

v

LS..J

LSr...J

i----srARTBYTEOOOOOOO1-/

Figure 15. Start Byte Procedure
Iy, the more times the microcomputer monitors, or polls, the bus, the less time it can
spend carrying out its intended function.
Therefore, there is a difference in speed
between fast hardware devices and the relatively slow microcomputer which relies on
software polling.
In this case, data transfer can be preceded by
a start procedure which is much longer than
normal (Figure 15). The start procedure consists of:
a)
b)
c)
d)

A start condition, (S)
A start byte 00000001
An acknowledge clock pulse
A repeated start condition, (Sr)

After the start condition (S) has been transmitted by a master requiring bus access, the

3-10

start byte (00000001) is transmitted. Another
microcomputer can therefore sample the
SDA line on a low sampling rate until one of
the seven zeros in the start byte is detected.
After detection of this Low level on the SDA
line, the microcomputer is then able to switch
to a higher sampling rate in order to find the
second start condition (Sr) which is then used
for synchronization.
A hardware receiver will reset at the reception
of the second start condition (Sr) and will
therefore ignore the start byte.
After the start byte, an acknowledge-related
clock pulse is generated. This is present only
to conform with the byte handling format used
on the bus. No device is allowed to acknowledge the start byte.

Signetics Linear Products

12C Bus Specification

,...,
I __________________- J

~

~I

I

ICL

I

I
!UN

i

I

I
-L~~~I-I--------------------I-L-J--L-J--J ~__________________________~I L--J

CON~

~':.a

nDATABITS

RrJ: I

ACK

RELATED
CLOCK PULSE

Figure 16. Data Format of Transmissions With CBUS Recelver/Tranamltter
CBUS Compatibility
Existing CBUS receivers can be connected to
the 12C bus. In this case, a third line called
OLEN has to be connected and the acknowl·
edge bit omitted. Normally, 12C transmissions
are multiples of 8·bit bytes; however, CBUS
devices have different formats.
In a mixed bus structure, 12C devices are not
allowed to respond on the CBUS message.
For this reason, a special CBUS address
(0000001 X) has been reserved. No 12C de·
vice will respond to this address. After the
transmission of the CBUS address, the OLEN
line can be made active and transmission,
according to the CBUS format, can be per·
formed (Figure 16).
After the stop condition, all devices are again
ready to accept data.
Master transmitters are allowed to generate
CBUS formats after having sent the CBUS
address. Such a transmission is terminated
by a stop condition, recognized by all devices.
In the low speed mode, full 8·bit bytes must
always be transmitted and the timing of the
OLEN signal adapted.
If the CBUS configuration is known and no
expansion with CBUS devices is foreseen,
the user is allowed to adapt the hold time to
the specific requirements of device(s) used.

ELECTRICAL SPECIFICATIONS
OF INPUTS AND OUTPUTS OF
12C DEVICES
The 12C bus allows communication between
devices made in different technologies which
might also use different supply voltages.
For devices with fixed input levels, operating
on a supply voltage of +5V ± 10%, the fol·
lowing levels have been defined:
VILmax = 1.5V (maximum input Low
voltage)

February 1987

VDDI-t=-5V:t1O%

lip

Rp

~~~;---~r---~t---~;---~-r­

~L----~----~----~~----~----~.Figure 17. Fixed Input Level Devices Connected to the 12C Bus

lip

lip

~--~-+--~~~--~~----+-+---~~-­

~L----~----~------~----~----~

__

Figure 18. Devices With a Wide Ragge of Supply Voltages Connected
to the I C Bus
VIHmin = 3V (minimum input High
voltage)
Devices operating on a fixed supply voltage
different from + 5V (e.g. 12 L), must also have
these input levels of 1.5V and 3V for VIL and
VIH, respectively.
For devices operating over a wide range of
supply voltages (e.g. CMOS), the following
levels have been defined:
VILmax = 0.3Voo (maximum input Low
voltage)
VIHmin = 0.7Voo (minimum input High
voltage)
For both groups of devices, the maximum
output Low value has been defined:
VOLmax = 0.4V (max. output voltage Low)
at 3mA sink current

3-11

The maximum low-level input current at
VOLmax of both the SDA pin and the SCL pin
of an 12C device is -101lA, including the
leakage current of a possible output stage.
The maximum high-level input current at
O.9Voo of both the SDA pin and SCL pin of an
12C device is 10llA, including the leakage
current of a possible output stage.
The maximum capacitance of both the SDA
pin and the SCL pin of an 12 C device is 10pF.
Devices with fixed input levels can each have
their own power supply of + 5V ± 10%. Pullup resistors can be connected to any supply
(see Figure 17).
However, the devices with input levels related
to Voo must have one common supply line to
which the pull-up resistor is also connected
(see Figure 18).

Signetics Linear Products

12C Bus Specification

When devices with fixed input levels are
mixed with devices with VDD-related levels,
the latter devices have to be connected to
one common supply line of + 5V ± 10% along
with the pull-up resistors (Figure 19).

VDDI =5V:IO%

Rp

VDD2 =5V±10%

VDD3 =5V:IO%

Rp

Input levels are defined in such a way that:
1. The noise margin on the Low level is 0.1
VDD·
2. The noise margin on the High level is 0.2
VDD·
3. Series resistors (Rs) up to 300s?' can be
used for flash-over protection against high
voltage spikes on the SDA and SCL line
(due to flash-over of a TV picture tube, for
example) (Figure 20).

SM'~~-r--~i---~-t--~~----+-t­
~L-----4----~~----~------+------4-

Figure 19. Devices With Voo Related LeveJs Mixed With Fixed Input Level
Devices on the I C Bus

The maximum bus capacitance per wire is
400pF. This includes the capacitance of the
wire itself and the capacitance of the pins
connected to it.

Rs

TIMING
The clock on the 12C bus has a minimum Low
period of 4.71.LS and a minimum High period of
4 MS. Masters in this mode can generate a bus
clock with a frequency from 0 to 100kHz.

~L

Figure 21 shows the timing requirements in
detail. A description of the abbreviations used
is shown in Table 2. All timing references are
at VILmax and VILmin.

I

l D~CE J I O~CE I
8M

All devices connected to the bus must be
able to follow transfers with frequencies up to
100kHz, either by being able to transmit or
receive at that speed or by applying the clock
synchronization procedure which will force
the master into a wait state and stretch the
Low periods. In the latter case the frequency
is reduced.

VDD

]"
Rs

As

Rs

Rp

LD05650S

Figure 20. Serial Resistors (Rs) for Protection Against High Voltage

LOW-SPEED MODE

Data Format and Timing

As explained previously, there is a difference
in speed on the 12 C bus between fast hardware devices and the relatively slow microcomputer which relies on software polling.
For this reason a low speed mode is available
on the 12C bus to allow these microcomputers
to poll the bus less often.

The bus clock in this mode has a Low period
of 130MS ± 25MS and a High period of
390MS ± 25MS, resulting in a clock frequency
of approx. 2kHz. The duty cycle of the clock
has this Low-to-High ratio to allow for more
efficient use of microcomputers without an
on-chip hardware 12 C bus interface. In this
mode also, data transfer with acknowledge is
obligatory. The maximum number of bytes
transferred is not limited (Figure 22).

Start and Stop Conditions
In the low-speed mode, data transfer is preceded by the start procedure.

8M

~L

Figure 21. Timing Requirements for the 12C Bus

February 1987

Rp

3-12

Signetics Linear Products

12C Bus Specification

Table 2. Timing Requirement for the 12C Bus
LIMITS
PARAMETER

SYMBOL

UNIT

fSCl

SCL clock frequency

tSUF

Time the bus must be free before a new transmission can start

tHO; STA

Hold time start condition. After this period the first clock pulse is generated

tLOW

Min

Max

0

100

kHz

4.7

MS

4

MS

The Low period of the clock

4.7

MS

tHIGH

The High period of the clock

4

J1S

tsu; STA

Setup time for start condition (Only relevant for a repeated start condition)

4.7

MS

tHO; OAT

Hold time DATA
for CBUS compatible masters
for 12C devices

5
O·

MS

tsu; OAT

Setup time DATA

250

tR

Rise time of both SDA and SCL lines

tF

Fall time of both SDA and SCL lines

tsu; STO

Setup time for stop condition

J1S
ns
1
300

4.7

NOTES:
All values referenced to VIH and VIL levels.
* Note that a transmitter must internally provide a hold time to bridge the undefined region (300ns max.) of the falling edge of SeL.

Figure 22. Data Transfer Low-Speed Mode

IF

1

SCL

1

I

1

1

1 Itt.; SfA -rt--I
~
LS.J

I----IHIGH----I

Figure 23. Timing Low-Speed Mode

February 1987

3-13

MS

ns
MS

Signetics Linear Products

12C Bus Specification

LOW SPEED MODE
CLOCK
DUTY CYCLE

: tLOW ~ 1301'S ± 251'S
: tHIGH ~ 390llS ± 2511S
: 1:3 Low-to-High (Duty cycle of
clock generator)

START BYTE
MAX. NO. OF BYTES
PREMATURE TERMINATION OF TRANSFER
ACKNOWLEDGE CLOCK BIT
ACKNOWLEDGEMENT OF SLAVES

: 0000 0001
:
:
:
:

UNRESTRICTED
NOT ALLOWED
ALWAYS PROVIDED
OBLIGATORY

In this mode, a transfer cannot be terminated
during the transmission of a byte.
The bus is considered busy after the first start
condition. It is considered free again one
minimum clock Low period, 10511S, after the
detection of the stop condition. Figure 23
shows the timing requirements in detail, Table
3 explains the abbreviations.

Table 3. Timing Low Speed Mode
LIMITS
SYMBOL

PARAMETER

UNIT
Min

Max

tBUF

Time the bus must be free before a new transmission can start

105

I'S

tHO: STA

Hold time start condition. After this period the first clock pulse is generated

365

I'S

tHO: STA

Hold time (repeated start condition only)

210

tLOW

The Low period of the clock

105

155

I'S

tHIGH

The High period of the clock

365

415

liS

tSU: STA

Setup time for start condition (Only relevant for a repeated start condition)

105

155

liS

tHO; tOAT

Hold time DATA
for CBUS compatible masters
for 12C devices

5
O'

tsu: OAT

Setup time DATA

250

tR

Rise time of both SDA and SCL lines

tF

Fall time of both SDA and SCL lines

tsu: STO

Setup time for stop condition

I'S

liS
I'S

ns

1

105

300

ns

155

liS

NOTES:
All values referenced to VIH and V1l levels.

• Note that a transmitter must Internally provide a hold time to bridge the undefined region (300ns max.) of the falling edge of SCL.

February 1987

3-14

I'S

Signetics Linear Products

12C Bus Specification

APPENDIX A
Maximum and minimum values of the pull-up
resistors Rp and series resistors Rs (See
Figure 20).
In a 12 C bus system these values depend on
the following parameters:
- Supply voltage
- Bus capacitance
- Number of devices (input current + leakage current)
1) The supply voltage limits the minimum value of the Rp resistor due
to the specified 3mA as minimum
sink current of the output stages,
at OAV as maximum low voltage.
In Graph 1, VDD against Rpmin is
shown.

In Graph 2, Rsmax against Rp is shown.
2) The bus capacitance is the total capacitance of wire, connections, and
pins. This capacitance limits the maximum value of Rp because of the
specified rise time of 11.1s.

In Graph 3, the bus capacitance - RPmax
relationship is shown.
3) The maximum high-level input current
of each input! output connection has a
specified value of 10MA max. Due to
the desired noise margin of 0.2 VDD
for the high level, this input current
limits the maximum value of Rp. This
limit is dependent on VDD.
In Graph 4 the total high-level input current - RPmax relationship is shown.
20

~

£'
w
3

16

12

§

:IE
:::>
:IE

MAXIMUM VALUE Rs (2)

~

:IE

Graph 2

,

20

TOTAL HIGH LEVEL INPUT CURRENT (,u\)

\

oL-__

~

____

~

o

__

~

__

12

Graph 4

\\

~

18

,/Rs=O

MAltR~

Graph 1
The desired noise margin of 0.1 VDD for the
low level limits the maximum value of Rs.

@VDD=Si
o
o

100

200

--=:::
300

BUS CAPACITANCE (PF)

Graph 3

February 1987

3·15

--=
400

12C LICENSE
Purchase of Signetics or Philips 12 C components conveys a license under the Philips 12 C
patent rights to use these components in an
12C system, provided that the system conforms to the 12 C standard specification as
defined by Philips.

Signetics

AN168
The Inter-Integrated Circuit (PC)
Serial Bus: Theory and
Practical Consideration

Linear Products

Author: Carl Fenger

INTRODUCTION
The 12C (Inter-IC) bus is becoming a popular
concept which implements an innovative serial bus protocol that needs to be understood.
On the hardware level 12C is a collection of
microcomputers (MAB8400, PCD3343,
83C351, 84CXX) and peripherals (lCD/lED
Jrivers, RAM, ROM, clock/timer, AID, D/ A,
IR transcoder, I/O, DTMF generator, and
various tuning circuits) that communicate serially over a two-wire bus, serial data (SDA)
and serial clock (SCl). The 12 C structure is
optimized for hardware simplicity. Parallel
address and data buses inherent in conventional systems are replaced by a serial protocol that transmits both address and bidirectional data over a 2-line bus. This means that
interconnecting wires are reduced to a minimum; only Vee, ground and the two-wire bus
are required to link the controller(s) with the
peripherals or other controllers. This results in
reduced chip size, pin count, and interconnections. An 12C system is therefore smaller,
simpler, and cheaper to implement than its
parallel counterpart.
The data rate of the 12C bus makes it suited
for systems that do not require high speed.
An 12C controller is well suited for use in
systems such as television controllers, telephone sets, appliances, displays or applications involving human interface. Typically an
12C system might be used in a control function where digitally-controllable elements are
adjusted and monitored via a central processor.
The 12C bus is an innovative hardware interface which provides the software designer
the flexibility to create a truly multi-master
environment. Built into the serial interface of
the controllers are status registers which
monitor all possible bus conditions: bus free/
busy, bus contention, slave acknowledgement, and bus interference. Thus an 12C
system might include several controllers on
the same bus each with the ability to asynchronously communicate with peripherals or
each other. This provision also provides expandability for future add-on controllers. (The
12C system is also ideal for use in environments where the bus is subject to noise.
Distorted transmissions are immediately detected by the hardware and the information
presented to the software.) A slave acknowl-

February 1987

Application Note
edgement on every byte also facilitates data
integrity.
An 12C system can be as simple or sophisticated as the operating environment demands. Whether in a single master or multimaster system, noisy or 'safe', correct system operation can be insured under software
control.

CONTROLLERS
Currently the family of 12C controllers include
the MAB8400, and the PCD 3343 (the
PCD3343 is basically a CMOS version of the
MAB8400). The MAB8400 is based on the
8048 architecture with the 12C interface builtin. The instruction set for the MAB8400 is
similar to the 8048, with a few instructions
added and a few deleted. Tables 1 and 2
summarize the differences.
Programs for the MAB8400 and PCD 3343
may be assembled on an 8048-assembler
using the macros listed in Appendix A. The
serial I/O instructions involve moving data to
and from the SO, S1, and S2 serial I/O control
registers. The block diagram of the 12C interface is shown in Figure 1.

SERIAL 1/0 INTERFACE
A block diagram of the Serial Input/Output
(SIO) is shown in Figure 1. The clock line of
the serial bus (SCl) has exclusive use of Pin
3, while the Serial Data (SDA) line shares Pin

2 with parallel I/O signal P23 of port 2.
Consequently, only three I/O lines are available for port 2 when the 12 C interface is
enabled.
Communication between the microcomputer
and interface takes place via the internal bus
of the microcomputer and the Serial Interrupt
Request line. Four registers are used to store
data and information controlling the operation
of the interface:
• data shift register SO
• address register SO'
• status register S1
• clock control register S2.

THE 12 C BUS INTERFACE:
SERIAL CONTROL REGISTERS
SO, S1
All serial 12 C transfers occur between the
accumulator and register SO. The 12 C hardware takes care of clocking out/in the data,
and receiving/generating an acknowledge. In
addition, the state of the 12C bus is controlled
and monitored via the bus control register S1.
A definition of the registers is as follows:
SO is the data shift
register used to perform the conversion between serial and parallel data format. All
transmissions or receptions take place
through register SO MSB first. All 12C bus
receptions or transmissions involve moving
data to/from the accumulator from/to SO.
Data Shift Register SO -

Table 1. MAB8400 Family Instructions not in the MAB8048 Instruction Set
SERIAL 1/0

MOV A,Sn
MOV Sn,A
MOV Sn,#data
EN SI
DIS SI

REGISTER

CONTROL

DEC @Rr
DJNZ @Rr,addr

SEl MB2
SEl MB3

CONDITIONAL
BRANCH

JNTF addr

Table 2. MAB8048 Instructions not in the MAB8400 Family Instruction Set
DATA MOVES

MOVX A,@R
MOVX @R,A
MOVP3 A,@A
MOVD A,P
MPVD P,A
ANlD P,A
ORlD P,A

FLAGS

ClR
CPl
CLR
CPL

FO
FO
F1
F1

BRANCH

*JNI addr
JFO addr
JF1 addr

* replaced by
JTO, JNTO

3-16

CONTROL

ENTOClK

Signetics Linear Products

Application Note

The Inter-Integrated Circuit (1 2C) Serial Bus:
Theory and Practical Consideration

AN168

INTREQ

T

ENSI
DISSI

WRSO

~~~~~-?

INITIALIZE
(Pin 17)

o

•

__~~__4-~,-~-rRDSO

LRB

RESET

PIN

INTERNAL MICROCOMPUTER BUS

BIT 7

MST TRX BS
RDS1
S1
CLOCK

SERIAL CLOCK PULSE GENERATOR

PROGR. COUNTER

1...- - - - - INTERNAL CLOCK

Figure 1_ Block Diagram of the MAB8400 SIO Interface
Address Register SO' - In multi-master
systems, this register is loaded with a controller's slave address. When activated,
(ALS = 0). the hardware will recognize when
it is being addressed by setting the AAS
(Addressed As Slave) flag. This provision
allows a master to be treated as a slave by
other masters on the bus.
Status Register S 1 - S1 is the bus status
register. To control the SIO interface, information is written to the register. The lower 4
bits in Sl serve dual purposes; when written
to, the control bits ESO, BC2, BC1, BCO are
programmed (Enable Serial Output and a 3bit counter which indicates the current number of bits left in a serial transfer). When
reading the lower four bits, we obtain the

February 1987

status information AL, AAS, ADO, LRB (Arbitration Lost, Addressed As Slave, Address
Zero (the general call has been received), the
Last Received Bit (usually the acknowledge
bit». The upper 4 bits are the MST, TRX, BB,
and PIN control bits (Master, Transmitter, Bus
Busy, and Pending Interrupt Not). These bits
define what role the controller has at any
particular time. The values of the master and
transmitter bits define the controller as either
a master or slave (a master initiates a transfer
and generates the serial clock; a slave does
not), and as a transmitter or receiver. Bus
Busy keeps track of whether the bus is free or
not, and is set and reset by the 'Start' and
'Stop' conditions which will be defined. Pending Interrupt Not is reset after the completion

3-17

of a byte transfer + acknowledge, and can be
polled to indicate when a serial transfer has
been completed. An alternative to polling the
PIN bit is to enable the serial interrupt; upon
completion of a byte transfer, an interrupt will
vector program control to location 07H.

SERIAL CLOCKI ACKNOWLEDGE
CONTROL REGISTER S2
Register S2 contains the clock-control register and acknowledge mode bit. Bits
S20 - S24 program the bus clock speed. Bit
S26 programs the acknowledge or not-acknowledge mode (1/0). The various 12C bus
clock speed possibilities are shown in
Table 3.

Signetics Linear Products

Application Note

The Inter-Integrated Circuit (1 2C) Serial Bus:
Theory and Practical Consideration
Table 3. Clock Pulse
Frequency Control
When Using a 4.43MHz Crystal
HEX
520 -524
CODE
0
1
2
3
4
5
6
7
8
9
A
B
C
D

E
F
10
11
12
13
14
15
1\,
17
18'
19'
lA'
1B'
lC
10

lE
IF

DIVISOR

APPROX.
fCLOCK
(kHz)

Not Allowed
39
114
45
98
51
87
63
70
75
59
87
51
99
45
123
36
147
30
171
26
195
23
243
18
291
15
339
13
387
11
483
9.2
579
7.7
675
6.6
771
5.8
963
4.6
1155
3.8
1347
3.3
1539
2.9
1923
2.3
2307
1.9
2691
1.7
3075
1.4
3843
1.2
4611
1.0
5379
0.8
6147
0.7

AN168

The losing Master is now configured as a
slave which could be addressed during this
very same cycle. These provisions allow for a
number of microcomputers to exist on the
same bus. With properly written subroutines,
software for anyone of the controllers may
regard other masters as transparent.

12C PROTOCOL AND
ASSEMBLY LANGUAGE
EXAMPLES
12 C data transfers follow a well-defined protocol. A transfer always takes place between a
master and a slave. Currently a microcomputer can be master or slave, while the 'CLIPS'
peripherals are always slaves. In a 'bus-free'
condition, both SCl and SDA lines are kept
logical high by external pull-up resistors. All
bus transfers are bounded by a 'Start' and a
'Stop' condition. A 'Start' condition is defined
as the SDA line making a high-to-Iow transition while the SCl line is high. At this point,
the internal hardware on all slaves are activated and are prepared to clock-in the next 8
bits and interpret it as a 7-bit address and a
R/W control bit (MSB first). All slaves have an
internal address (most have 2 - 3 programmable address bits) which is then compared
with the received address. The slave that
recognized its address will respond by pulling
the data line low during a ninth clock generated by the master (all 12 C byte transfers
require the master to generate 8 clock pulses
plus a ninth aCknowledge-related clock
pulse). The slave-acknowledge will be registered by the master as a '0' appearing in the
lRB (last Received Bit) position of the Sl
serial 1/0 status register. If this bit is high

after a transfer attempt, this indicates that a
slave did not acknowledge, and that the
transfer should be repeated.
After the desired slave has acknowledged its
address, it is ready to either send or receive
data in response to the master's driving
clock. All other slaves have withdrawn from
the bus. In addition, for multi-master systems,
the start condition has set the 'Bus Busy' bit
of the serial 110 register Sl on all masters on
the bus. This gives a software indication to
other masters that the bus is in use and to
wait until the bus is free before attempting an
access.
There are two types of 12C peripherals that
now must be defined: there are those with
only a chip address such as the 110 expander, PCF8574, and those with a chip address
plus an internal address such as the static
RAM, PCF8570. Thus after sending a start
condition, address, and R/W bit, we must
take into account what type of slave is being
addressed. In the case of a slave with only a
chip address, we have already indicated its
address and data direction (R/W) and are
therefore ready to send or receive data. This
is performed by the master generating bursts
of 9 clock pulses for each byte that is sent or
received. The transaction for writing one byte
to a slave with a chip address only is shown in
Figure 3.
In this transfer, all bus activity is invoked by
writing the appropriate control byte to the
serial 110 control register Sl, and by moving
data tolfrom the serial bus buffer register SO.
Coming from a known state (MOV Sl,#18HSlave, Receiver, Bus not Busy) we first load
the serial 110 buffer SO with the desired

• only values that may be used In the low speed mode
(ASC~1).

Vce
These speeds represent the frequency of the
serial clock bursts and do not reflect the
speed of the processor's main clock (Le. it
controls the bus speed and has no effect on
the CPU's execution speed).

SCL
SDA

BUS ARBITRATION
Due to the wire-AND configuration of the 12 C
bus, and the self-synchronizing clock circuitry
of 12 C masters, controllers with varying clock
speeds can access the bus without clock
contention. During arbitration, the resultant
clock on the bus will have a low period equal
to the longest of the low periods; the high
period will equal the shortest of the high
periods. Similarly, when two masters attempt
to drive the data line simultaneously, the data
is 'ANDed', the master generating a low while
the other is driving a high will win arbitration.
The resultant bus level will be low, and the
loser will withdraw from the bus and set its
'Arbitration lost' flag (Sl bit 3).
February 1987

MAB

AO

8400

:;~

A1

A2

AO

:;,.~

A1

A2

RAM (128-BYTE)

1/0 EXPANDOR

ADDR· '40'H

Figure 2. Schematic for Assembly Examples

6-18

ADDR • 'AO'H

Signetics Linear Products

Application Note

The Inter-Integrated Circuit (1 2C) Serial Bus:
Theory and Practical Consideration

AN168

ROtWR

I

SDA

I
II

SCl

" ,,~.-----------ACKNOWlEDGE------------J

--nnnnnJUUlM
I

I
I START

ADDRESS '40H'

[U1JlJlJlJUlJ1J~r-

I

I

I
I

I
I
I

I CONDITION

I

I

I

DATA '2AH'

I STOP
I CONDITION

I

;Initialize Sl-Slave, Receiver, Bus not
;Busy, Enable Serial 1/0.
;Preload SO with Slave's address &
;RiVii bit.
;Invoke start condition & slave address
; (Master, Transmitter, Bus Busy, Enable
;Serial 1/0, Bit Counter = 000).
;Check for transmission complete, ack.
;received, no arbitration, etc.
;Get a data byte.
;Transmit data byte.
;Wait for transmission complete again.
;Generate Stop condition
;(Master, Transmitter, Bus not Busy).

MOV S1.#18H
MOV SO,#40H
MOV Sl,#OF8H

CALL

I
I

I

ACKW~:

MOV A,#2AH
MOV SO,A
CALL ACKWT:
MOV Sl,#OD8H

Figure 3
slave's address (MOV SO,#40H), To transmit
this preceded by a start condition, we must
first examine the control register Sl, which,
after initialization, looks like this:
MAS·
BUS
TER TRANS BUSY

PIN

ESO

BC2

BC1

BCQ

To transmit to a slave, the Master, Transmitter, Bus Busy, PIN (Pending Interrupt Not),
and ESO (Enable Serial Output) must be set
to a I. This results in an 'F8H' being written to
Sl, This word defines the controller as a
Master Transmitter, invokes the transfer by
setting the' Bus Busy' bit, clears the Pending
Interrupt Not (an inverted flag indicating the
completion of a complete byte transfer), and
activates the serial output logic by setting the
Enable Serial Output (ESO) bit.

BIT COUNTER S12, S11, S10
BC2, BC1, and BCO comprise a bit-counter
which indicates to the logic how long the
word is to be clocked out over the serial data
line. By setting this to a OOOH, we are telling it
February 1987

to produce 9 clocks (8 bits plus an acknowledge clock) for this transfer. The bit counter
will then count off each bit as it is transmitted.
The bit counter possibilities are shown in
Table 4.
Thus the bit counter keeps track of the
number of clock pulses remaining in a serial
transfer. Additionally, there is a not-acknowledge mode (controlled through bit 6 of clock
control register S2) which inhibits the acknowledge clock pulse, allowing the possibility of straight serial transfer. We may thus
define the word size for a serial transfer (by

preloading BC2, BC1, BCO with the appropriate control number), with or without an acknowledge-related clock pulse being generated. This makes the controller able to transmit
serial data to most any serial device regardless of its protocol (e.g., C-bus devices).

CHECKING FOR SLAVE
ACKNOWLEDGE
After a 'Start' condition and address have
been issued, the selected slave will have
recognized and acknowledged its address by

Table 4. Binary Numbers in Bit-Count Locations BC2, BC1 and BCa
BC2

BCl

BCQ

0
0
0
1
1
1
1
0

0
1
1
0
0
1
1
0

1
0
1
0
1
0
1
0

3-19

BITS/BYTE
WITHOUT ACK

BITS/BYTE
WITH ACK

1
2
3
4

2
3
4
5
6
7
8
9

5
6
7
8

Signetics Linear Products

Application Note

The Inter-Integrated Circuit (1 2C) Serial Bus:
Theory and Practical Consideration
pulling the data line low during the ninth clock
pulse. During this period, the software (which
runs on the processor's 4MHz clock) will
have been either waiting for the transfer to be
completed by polling the PIN bit in S1 which
goes low on completion of a transfer/reception (whose length is defined by the preloaded Bit-counter value), or by the hardware
in Serial Interrupt mode. The serial interrupt
(vectored to 07H) is enabled via the EN SI
(enable serial interrupt) instruction.
At the point when PIN goes low (or the serial
interrupt is received) the 9-bit transfer has
been completed. The acknowledgement bit
will now be in the LRB position of register S1,
and may be checked in the routine' ACKWT'
(Wait for Acknowledge) as shown in Figure 4.

ACKWT:

AN168

MOV A,S1

;Get bus status word
;from S1.
;Poll the PI N bit
;until it goes low
;indicating transfer
;completed
;Jump to BUSERR
;routine if acknowledge
;not received.
;transfer complete,
;acknowledge received - return.

JB4 ACKWT

JBO BUSERR

RET

Figure 4

MASTER READS ONE BYTE
FROM SLAVE

A read operation is a similar process; the
address, however, will be 41 H, the LSB
indicating to the I/O device that a read is to
be performed. During the data portion of a
read, the I/O port 8574 will transmit the
contents of its latches in response to the
clock generated by the master. The Master/
Receiver in this case generates a low-level
acknowledge on reception of each byte (a
'positive' acknowledge). Upon completion of
a read, the master must generate a 'negative'
acknowledge during the ninth clock to indicate to the slaves that the read operation is
finished. This is necessary because an arbitrary number of bytes may be read within the
same transfer. A negative acknowledge conAfter a successful address transfer/acknowlsists of a high signal on the data line during
edge, the slave is ready to be sent its data. the ninth clock of the last byte to be read. To
The instruction MOV SO,A will now automati- accomplish this, the master 8400 must leave
cally send the contents of the accumulator the acknowledge mode just before the final
out on the bus. After calling the ACKWT byte, read the final byte (producing only 8
routine once more, we are ready to terminate clock pulses), program the bit-counter with
the transfer. The Stop condition is created by 001 (preparing for a one-bit negative acthe instruction 'MOV S1, #OD8H'. This reknowledge pulse), and simply move the consets the bus-busy bit, which tells the hard- tents of SO to the accumulator. This final
ware to generate a Stop - the data line
instruction accomplishes two things simultamakes a low-to-high transition while the clock neously: it transfers the final byte to the
remains high. All bus-busy flags on other accumulator and produces one clock pulse
masters on the bus are reset by this signal. . on the SCL line. The structure of the serial
I/O register SO is such that a read from it
The transfer is now complete - PCF8574
I/O Expandor will transfer the serial data causes a double-buffered transfer from the
12C bus to SO, while the original contents of
stream to its 8 output pins and latch them
SO are transferred to the accumulator. Beuntil further update.
cause the number of clocks produced on the
bus is determined by the control number in
the Bit Counter, by presetting it to 001, only

This routing must go one step further in multimaster systems; the possibility of an Arbitration Lost situation may occur if other masters
are present on the bus. This condition may be
detected by checking the 'AL' bit (bit 3). If
arbitration has been lost, provisions for reattempting the transmission should be taken.
If arbitration is lost, there is the possibility that
the controller is being addressed as a Slave.
If this condition is to be recognized, we must
test on the' AAS' bit (bit 2). A 'General Call'
address (OOH) has also been defined as an
'all-call' address for all slaves; bit 1, ADO,
must be tested if this feature is to be recognized by a Master.

February 1987

3-20

one clock is generated. At this point in time
the slave is still waiting for an acknowledge;
the bus is high due to the pull-up, as single
clock pulse in this condition is interpreted as
a 'negative' acknowledge. The slave has now
been informed that reading is completed; a
Stop condition is now generated as before.
The read process (one byte from a slave with
only a chip address) is shown in Figure 5.

Signetics Linear Products

Application Note

The Inter-Integrated Circuit (1 2C) Serial Bus:
Theory and Practical Consideration

AN168

'NEGATIVE ACKNOWLEDGE'
RD

SDA

ACKNOWLEDGE

seL

I START

I CONDITION
I

t
MOV S1,#18H
MOV SO,#41H

MOV S1,#OF8H
CALL ACKWT

WAIT:

MOV S2,#01H
MOV SO,A
MOV A,S1
JB4 Wait
MOV S1,#OA9H

MOV A,SO
MOV S1,#OD8H

I STOP
I CONDITION
I
I

;Initialize serial 1/0 control
;register.
;Preload serial register SO
;with slave address and RD
;control bit.
;Send address to bus along with
;start condition.
:Wait for acknowledge (as
;before),
;Leave acknowledge mode.
;Read data from slave to SO.
;Test for byte received by
;testing S1 PIN bit.
;Wait until PIN received,
;Set Bit Counter to 1 and
;become a receiver (A9 =
;Mst,Rec,Bus Busy,Bit Coutner =
;001),
;Move data to accumulator and
;clock out a negative
;acknowledge,
;Generate Stop Condition,
WF1432{1S

Figure 5

February 1987

3-21

•

Application Note

Signetics Linear Products

The Inter-Integrated Circuit (1 2C) Serial Bus:
Theory and Practical Consideration

AN168

COMMUNICATION WITH PERIPHERAL REQUIRED

MOV S1, #18H

MOV SO, #OAOH
MOV S1, #OF8H
CALL ACKWT
MOVA,#OOH
MOV SO,A
CALL ACKWT
MOV SI, #18H
MOV A,#OA1H
MOV SO,A
MOV S1,#OFBH
CALL ACKWT
MOV A,SO
CALL ACKWT
MOV A,SO
CALL ACKWT
MOV RO,A
MOV A,SO
CALL ACKWT
MOV R1,A
MOV S2,#01H
MOV A,SO

WAIT1:

MOV R2,A
MOV A,S1
JB4 WAIT1
MOV S1,#OD8H
MOV S2,#41H

;Initialize bus-status register
;Master, Transmitter,
;Bus-not-Busy, Enable SIO.
;Load SO with RAM's chip
;address.
;Start condo and transmit
;address.
;Wait until address received.
;Set up for transmitting RAM
;Iocation address.
;Transmit first RAM address.
;Wait.
;Set up for a repeated Start
;condition.
;Get RAM chip address & RD bit.
;Send out to bus
;preceded by repeated Start.
;Wait.
;First data byte to SO.
;Wait.
;Second data byte to SO.
;And First data byte to Acc.
;Wait.
;Save first byte in RO.
;Third data byte to SO
;and second data byte to Acc.
;Wait.
;Save second data byte
;in R1.
;Leave ack. mode.
;Bit Counter=001 for neg ack.
;Third data byte to acc
;negative ack. generated.
;Save third data byte in R2.
;Get bus status.
;Wait until transfer complete.
;Stop condition.
;Restore acknowledge mode.

PFoonos

Figure 6. Flowchart for Reading/Writing One Byte to an 12 C
Peripheral; Single-Master, Single-Address Slave
These examples apply to a slave with a chip
address - more than one byte can be written/read within the same transfer; however,
this option is more applicable to 12C devices
with sub-addresses such as the static RAMs
or Clock/Calendar. In the case of these types
of devices, a slightly different protocol is
used. The RAM, for example, requires a chip
address and an internal memory location
before it can deliver or accept a byte of
information. During a write operation, this is
February 1987

done by simply writing the secondary address
right after the chip address - the peripheral
is designed to interpret the second byte as an
internal address. In the case of a Read
operation, the slave peripheral must send
data back to the Master after it has been
addressed and sub·addressed. To accomplish this, first the Start, Address, and Subaddress is transmitted. Then we have a
repeated start condition to reverse the direction of the data transfer, followed by the chip

3-22

Figure 7

address and RD, then a data string (w/
acknowledges). This repeated Start does not
affect other peripherals - they have been
deactivated and will not reactivate until a
Stop condition is detected. 12 C peripherals
are equipped with auto-incrementing logic
which will automatically transmit or receive
data in consecutive (increasing) locations.
For example, to read 3 consecutive bytes to
PCB8571 RAM locations 00, 01 and 02, we
use the following format as shown in Figure 7.

Signetics Linear Products

Application Note

The Inter-Integrated Circuit (1 2C) Serial Bus:
Theory and Practical Consideration
This routine reads the contents of location 00,
01 and 02 of the PCBB571 12B-byte RAM and
puts them in registers RO, R1, and R2. The
auto-incrementing feature allows the programmer to indicate only a starting location,
then read an arbitrary block of consecutive
memory addresses. The WAIT 1 loop is
required to poll for the completion of the final
byte because the ACKWT routine will not
recognize the negative acknowledge as a
valid condition.

February 19B7

BUS ERROR CONDITIONS:
ACKNOWLEDGE NOT RECEIVED
In the above routines, should a slave fail to
acknowledge, the condition is detected during the 'ACKWT' routine. The occurrence
may indicate one of two conditions: the slave
has failed to operate, or a bus disturbance
has occurred. The software response to either event is dependent on the system application. In either case, the 'BusErr' routine
should reinitialize the bus by issuing a 'Stop'
condition. Provision may then be taken to

3-23

AN168

repeat the transfer an arbitrary number of
times. Should the symptom persist, either an
error condition will be entered, or a backup
device can be activated.
These sample routines represent Single-master systems. A more detailed analysis of multimaster/noisy environment systems will be
treated in further application notes. Examples
of more complex systems can be found in the
'Software Examples' manual; publication
939B 615 70011.

•

Application Note

Signetics Linear Products

The Inter-Integrated Circuit (1 2C) Serial Bus:
Theory and Practical Consideration
APPENDIX A
Only the 8048 assembler is capable of assembling MAB8400 source code when it has
at least a "DATA" or "Define Byte" assembler directive, possibly in combination with a
MACRO facility.

AN168

The new instructions can be simply defined
by MACROs. The instructions which are not
in the MAB8400 should not be in the
MAB8400 source program.
An example of a macro definitions list is given
here for the Intel Macro Assembler.

This list can be copied in front of a MAB8400
source program; the new instructions are
added to the MAB8400 source program by
calling the MACRO via its name in the opcode field and (if required) followed by an
operand in the operand field.

MACRO DEFINITIONS
LINE

SOURCE STATEMENT

1 $MACROFILE
2 ;MACROS FOR 8048 ASSEMBLER RECOGNITION
3 ;OF 8400 COMMANDS
4
MOVSOA
5
DB 3CH
6
ENDM
7
MOVASO
8
DB OCH
9
ENDM
10
MOVS1A
11
DB 3DH
12
ENDM
13
MOVASI
14
DB ODH
15
ENDM
16
MOVS2A
17
DB 3EH
18
ENDM
MOVSO
19
20
DB 9CH,L
21
ENDM
22
MOVSl
23
DB 9DH,L
24
ENDM
25
MOVS2
DB 9EH,L
26
ENDM
27
ENSI
28
29
DB 85H
30
ENDM
DISSI
31
32
33
34;
35; PORT 0 INSTRUCTIONS:
36;
37
38
39;
40
41
42
43;
44
45
46
47;
48
49
50
51;

February 1987

MACRO

;MOV SO,A

MACRO

;MOV A,SO

MACRO

;MOV SI,A

MACRO

;MOV A,SI

MACRO

;MOV S2,A

MACRO L

;MOV 80,#DATA

MACRO L

;MOV SI,#DATA

MACRO L

;MOV S2,#DATA

MACRO

;EN 81

MACRO

;D18 SI (Disable serial
interrupt)

DB
ENDM

95H

INAPO
DB
ENDM

MACRO
08H

;IN A,PO

OUTPOA
DB
ENDM

MACRO
38H

;OUTL PO,A

ORLPO
DB
ENDM

MACRO L
88H,L

;ORL PO,#DATA

ANLPO
DB
ENDM

MACRO L
98H,L

;ANL PO,#DATA

3-24

Signetics Linear Products

Application Note

The Inter-Integrated Circuit (1 2C) Serial Bus:
Theory and Practical Consideration

AN168

MACRO DEFINITIONS (Continued)
LINE

SOURCE STATEMENT

52; DATA MEMORY INSTRUCTIONS:
53

DECARO
DB
ENDM

MACRO
OCOH

;DEC @RO

DECAR1
DB
ENDM

MACRO
OC1H

;DEC @R1

SELMB2
DB
ENDM

MACRO
OA5H

;SEL MB2

SELMB3
DB
ENDM

MACRO
OB5H

;SEL MB3

DJNZAO
DB
ENDM

MACRO L
;DJNZ @RO,ADDR
OEOH,L AND OFFH

76
77

DJNZA1
DB
ENDM

MACRO L
;DJNZ @R1,ADDR
OE1 H,L AND OFFH

78;
79

JNTF

MACRO L

DB
ENDM

06H,L AND OFFH

54
55
56;
57

58
59
60;
61; SELECT MEMORY BANK INSTRUCTIONS:
62
63

64
65;

66
67
68
69;
70; CONDITIONAL JUMP INSTRUCTIONS:
71
72

73
74;
75

80
81

82
83; END OF MACRO DEFINITIONS

February 1987

3-25

;JUMP IF TIMER FLAG IS
NON ZERO

•

Application Note

Signetics Linear Products

The Inter-Integrated Circuit (1 2C) Serial Bus:
Theory and Practical Consideration

AN168

THE 8400 INSTRUCTIONS BUILT FROM THE MACRO LIST
LOC/OBJ

LINE

0000
OOOOOC
0001 OD
0002 3C
0003 3D
0004 3E

0005 9C
0006 56

0007 9D
0008 9F

0009 9E
OOOA E8
OOOB 85
OOOC 95
OOOD 08
OOOE 38
OOOF 88
0010 5A
0011 98
0012 2F
0013 CO
0014 C1
0015 A5
0016 B5

0017 EO

SOURCE STATEMENT

2
3+
4
5+
6
7+
8
9+
10
11 +
12

ORG 0
MOVASO
DB
MOVAS1
DB
MOVSOA
DB
MOVS1A
DB
MOVS2A
DB
MOVSO

13 +

DB

9CH,56H

14

MOVS1

9FH

15+

DB

9DH,9FH

16

MOVS2

OE8H

17+

DB

9EH,OE8H

18
19 +
20
21 +
22
23 +
24
25 +
26
27 +

ENS1
DB
DISSI
DB
INAPO
DB
OUTPOA
DB
ORLPO
DB

28
29 +

ANLPO
DB

30
31 +
32
33 +
34
35+
36
37+
38

DECARO
DB
DECAR1
DB
SELMB2
DB
SELMB3
DB
DJNZAO

39 +

DB

OEOH,567H AND
OFFH

40

DJNZA1

OEFEH

41 +

DB

OE1 H,OEFEH AND
OFFH

42
43 +

JNTF
DB

789H
06H, 789H AND
OFFH

44

END

;MACRO for MOV A,SO
OCH
;MACRO for MOV A,S1
ODH
;MACRO for MOV SO,A
3CH
;MACRO For MOV S1,A
3DH
;MACRO For MOV S2,A
3EH
56H

;MACRO For MOV SO,
#56H

;MACRO for MOV S1,
#9FH

;MACRO for MOV S2,
#OE8H

;MACRO for EN S1
85H
;MACRO for DIS SI
95H
;MACRO for IN A,PO
08H
;MACRO for OUTL PO,A
38H
5AH
88H,5AH
2FH
98H,2FH

;MACRO for ORL PO,A

;MACRO for ANL PO,A

;MACRO for DEC @RO
OCOH
;MACRO for DEC @R1
OC1H
;MACRO for SEL MB2
OA5H
;MACRO for SEL MB3
OB5H
567H

;MACRO for DJNZ @RO,
567H

0019 67

0019 E1

;MACRO for DJNZ @R1,
OEFEH

001A FE
001B 06
001C 89

February 1987

3-26

;MACRO for JNTF 789H

Signetics

Section 4
RF Communications

Linear Products

INDEX
RF SIGNAL PROCESSING
Amplifiers
NE/SA5204
NE/SA/
SE5205
NE/SE5539
AN140
NE5592
NE/SE592
AN141

Wide-band High Frequency Amplifier ...................................... .

4-3

Wide-band High Frequency Amplifier ...................................... .
Ultra-High Frequency Operational Amplifier .............................. .
Compensation Techniques for Use With the NE/SE5539 ........... .
Video Amplifier ................................................................. .
Video Amplifier ................................................................. .
Using the NE/SE592 Video Amplifier ..................................... .

4-14
4-26
4-34
4-40
4-46
4-55

Mixer/Modulators/Demodulators
MC1496/
1596
AN189
NE602
AN198
AN1981
AN1982
NE612
TDA1574
TDA5030A
TDA5230

Balanced Modulator/Demodulator........................................... 4-60
Balanced Modulator/Demodulator Applications Using the
MC1496/MC1596 ............................................................... 4-64
Double-Balanced Mixer and Oscillator..................................... 4-69
Designing With the NE/SA602 .............................................. 4-75
New Low Power Single Sideband Circuits (NE602) .................... 4-79
Applying the Oscillator of the NE602 in Low Power
Mixer Applications.............................................................. 4-87
Low Power VH F Mixer/Oscillator ........................................... 4-90
FM Front-End IC (VHF Mixer and Oscillator)............................ 4-96
VHF Mixer-Oscillator (VHF Tuner IC) ...................................... 4-102
VHF, Hyperband, and UHF Mixer/Oscillator With IF Amp ............ 4-106

IF Systems
CA3089
MC3361
NE604
AN199
AN1991
NE605
NE614
TDA1576

FM IF System ...................................................................
Low Power FM IF ..............................................................
Low Power FM IF System ...................................................
Designing With the NE/SA602 ..............................................
Audio Decibel Level Detector With Meter Driver .......................
Low Power FM IF System ...................................................
Low Power FM IF System ...................................................
FM-IF (Quadrature Detector) .................................................

4-110
4-116
4-119
4-130
4-140
4-142
4-146
4-156

FREQUENCY SYNTHESIS
Preacaler
SAB1164/65
SAB1256

lGHz Divide-by-64 Prescaler ................................................. 4-163
lGHz Divide-by-256 Prescaler ............................................... 4-168

Signetics Linear Products

Section 4 RF Communications

Contents

Synthesizers
HEF4750V
HEF4751V
SAA1057
AN196
AN197
TDA8400
TDD1742

Frequency Synthesizer.........................................................
Universal Divider................................................................
PLL Radio Tuning Circuit.....................................................
Single-Chip Synthesizer for Radio Tuning.................................
Analysis and Basic Application of the SAA 1057
(PLL Radio Tuning).............................................................
FLL Tuning Circuit With Prescaler..........................................
CMOS Frequency Synthesizer...............................................

4-174
4-1 B4
4-193
4-201
4-208
4-220
4-226

PHASE-LOCKED LOOPS
AN177
AN178
NE/SE564
AN179
AN180
AN1801
AN181
AN182
NE/SE565
AN183
AN184
NE/SE566
AN185
AN186
NE/SE567
AN187
AN188
NE568
COMPANDORS
AN 174
AN176
NE570/5711
SA571
NE/SA572
AN175
NE575

An Overview of the Phase-Locked Loop (PLL) .........................
Modeling the PLL...............................................................
Phase-Locked Loop............................................................
Circuit Description of the NE564 ...........................................
Frequency Synthesis With the NE564.....................................
10.BMHz FSK Decoder With the NE564 ..................................
A 6MHz FSK Converter Design Example for the NE564.............
Clock Regenerator With Crystal-Controlled Phase-Locked
VCO (NE564) ....................................................................
Phase-Locked Loop ............................................................
Circuit Description of the NE565 PLL .....................................
Typical Applications With NE565............................................
Function Generator.............................................................
Circuit Description of the NE566 ...........................................
Waveform Generators With the NE566 ...................................
Tone Decoder/Phase-Locked Loop ........................................
Circuit Description of the NE567 Tone Decoder ........................
Selected Circuits Using the NE56?........................................
150MHz Phase-Locked Loop ................................................

4-236
4-241
4-257
4-266
4-273
4-277
4-2BO
4-2B2
4-291
4-297
4-301
4-304
4-309
4-310
4-313
4-325
4-330
4-333

Applications for Compandors: NE570/571/SA571 ...................... 4-341
Compandor Cookbook......................................................... 4-350
Compandor ..... .................... ..............................................
Programmable Analog Compandor..........................................
Automatic Level Control Using the NE572 ...............................
Low Voltage Compandor ......................................................

4-357
4-364
4-372
4-373

NEjSA5204

Signetics

Wide-band High-Frequency
Amplifier
Product Specification

Linear Products
DESCRIPTION
The NE/SA5204 is a high-frequency
amplifier with a fixed insertion gain of
20dB. The gain is flat to ± O.5dB from DC
to 200M Hz. The -3dB bandwidth is
greater than 350M Hz. This performance
makes the amplifier ideal for cable TV
applications. The NE/SA5204 operates
with a single supply of 6V, and only
draws 25mA of supply current, which is
much less than comparable hybrid parts.
The noise figure is 4.8dB in a 75n
system and 6dB in a 50n system.
The NE/SA5204 is a relaxed version of
the NE5205. Minimum guaranteed bandwidth is relaxed to 350M Hz and the "S"
parameter Min/Max limits are specified
as typicals only.
Until now, most RF or high-frequency
designers had to settle for discrete or
hybrid solutions to their amplification
problems. Most of these solutions required trade-offs that the designer had
to accept in order to use high-frequency
gain stages. These include high power
consumption, large component count,
transformers, large packages with heat
sinks, and high part cost. The NE/
SA5204 solves these problems by incorporating a wideband amplifier on a single
monolithic chip.
The part is well matched to 50 or 75n
input and output impedances. The
standing wave ratios in 50 and 75n
systems do not exceed 1.5 on either the
input or output over the entire DC to
350M Hz operating range.

No external components are needed
other than AC-coupling capacitors because the NE/SA5204 is internally compensated and matched to 50 and 75n.
The amplifier has very good distortion
specifications, with second and thirdorder intermodulation intercepts of
+ 24dBm and + 17dBm, respectively, at
100MHz.
The part is well matched for 50n test
equipment such as signal generators,
oscilloscopes, frequency counters, and
all kinds of signal analyzers. Other applications at 50n include mobile radio, CB
radio, and data/video transmission in
fiber optics, as well as broadband LANs
and telecom systems. A gain greater
than 20dB can be achieved by cascading additional NE/SA5204s in series as
required, without any degradation in amplifier stability.

FEATURES
• 200MHz (min.), ± O.5dB bandwidth
• 20dB Insertion gain
• 4.8dB (6dB) noise figure
Zo 75n (Zo 50n)
• No external components required
• Input and output impedances
matched to 50175n systems
• Surface-mount package available
• Cascadable

=

=

PIN CONFIGURATION
N, D Packages

TOPWEW
00127808

APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•

Antenna amplifiers
Amplified splitters
Signal generators
Frequency counters
Oscilloscopes
Signal analyzers
Broadband LANs
Networks
Modems
Mobile radio
CB radio
Telecommunications

Since the part is a small, monolithic IC
die, problems such as stray capacitance
are minimized. The die size is small
enough to fit into a very cost-effective 8pin small-outline (SO) package to further
reduce parasitic effects.

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

o to
B-Pin Plastic DIP

February 12, 19B7

NE5204N

-40 to +B5·C

o to
B-Pin Plastic SO package

ORDER CODE

+70·C

SA5204N

+70·C

NE5204D

-40 to +B5·C

SA5204D

4-3

B53-1191 B75B6

Signetlcs Linear Products

Product Specification

NE/SA5204

Wide-band High-Frequency Amplifier

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

UNIT

RATING

Vcc

Supply voltage

9

V

VIN

AC input voltage

5

Vp_p

TA

Operating ambient temperature range
NE grade
SA grade

o to +70
-40 to +85

·C

1160
780

mW
mW

PD

Maximum power dissipation I, 2
= 25·C (still-air)
N package
D package

·C

TA

TJ

Junction temperature

TSTG

Storage temperature range

TSOLD

Lead temperature
(soldering 60s)

150

·C

-55 to + 150

·C

300

·C

NOTES:
1. Derate above 25°C, at the following rates

N package at 9.3mW!'C
o package at 6.2mW!'C.
2. See "Power Dissipation Considerations" section.

EQUIVALENT SCHEMATIC
vee

Rt

R,

R,

VOUT

a.

V,N

R,

a,

RE2
RE'

.".

Rn
.".

February 12, 1987

4-4

Product Specification

Signetics Linear Products

NE/SA5204

Wide-band High-Frequency Amplifier

DC ELECTRICAL CHARACTERISTICS at Vcc = 6V, Zs = ZL = Zo = 50n and TA = 25°C, in all packages, unless otherwise
specified.
LIMITS
SYMBOL

PARAMETER

UNIT

TEST CONDITIONS

Min
Vcc

Operating supply voltage range

Over temperature

5

Icc

Supply current

Over temperature

19

S21

Insertion gain

Sll

f

Input return loss

= 100MHz, over temperature
f = 100MHz

16

DC -550MHz
f
S22

Output return loss

DC -550MHz
f

S12

= 100MHz

Isolation

= 100MHz

DC -550MHz
BW

Bandwidth

BW

Bandwidth

Saturated output power
1dB gain compression

8

V

24

31

mA

19

22

dB

25

dB

12

dB

27

dB

12

dB

-25

dB

-18

dB

200

350

MHz

-3dB

350

550

MHz

4.8

dB

f

Noise figure (50n)

Max

±0.5dB

= 100MHz
f = 100MHz
f = 100MHz
f = 100MHz

Noise figure (75n)

Typ

6.0

dB

+7.0

dBm

+4.0

dBm

Third-order intermodulation
intercept (output)

f

= 100MHz

+17

dBm

Second-order intermodulation
intercept (output)

f

= 100MHz

+24

dBm

35
34

<

20=500
TA =25°C

32

Vee=8V
Vec=7V
Vec=6V
Vec=5V

ffi

~

26

~

22

~

20

a

24

II.

~'"

18

~

/,

A'A'

"

5

16

5

5.5

6.5

10'

7.5

Figure 1. Supply Current vs Supply Voltage

February 12, 1987

• • 10'

FREQUENCY -MHz

SUPPLY VOLTAGE-V

Figure 2. Noise Figure vs Frequency

4-5

Signetics Linear Products

Product Specification

NE/SA5204

Wide-band High-Frequency Amplifier

25

25

YCC~~i=

YCC~6V

Vee=5V

-Zo=500

_TAz2S·C

T,,_25 0 C

6

I 102

-Zo=500

,

10

• 103

'0'

Figure 3. Insertion Gain vs Frequency (S21)

Figure 4. Insertion Gain vs Frequency (S2,)

8 r - - Vcc- 7Y
7

Vcc=6V

;1
I-

-4

-5
-6

1

~ -~
0-2

r-Zo=500

-3

~TA=25.C

-4

10'

8

• • 102

~

a 103

8

40

/

25

Q

0
CJ
w

,

20
15

IL

V

~
w

20

'"•

8 102

• 103

",-

~

Zo=500

I
I

I

6

a:
w

15

~

10

Q

~

[

/

'I'

I-

10
4

25

I-

TA=25·C

II)

"I

Ii:w

:/

I-

~
z

...

30

w

a:
w
a:

.......

i

35

~ 30
~

"
"

Figure 6. 1dB Gain Compression vs Frequency

m

llL
W

........

FREQUENCY -MHZ'

Figure 5. Saturated Output Power vs Frequency

"I

-

TA=25·C

10'

........

.............

-5
-I

FREOUENCY-MHz

e

....

YcC=5Y

I--Zo=500

I--

.......

.....

i - - Vec=IV

i

-3

Vec- BV

9
Yc .IV

Vcc· 5V

~
~ :~

8 103

6

• • 102

FREQUENCY -MHz

10
Ycc=7Y

,

-Vee=8V

FREQUENCY-MHz

11
10

.......,

r...~

T..,=85·C

"

10
10'

-40.I~~rt-

Tl.

Yee=7Y'7

5

10

""

TA=2S·C

Zo=500

I
I
I

4

POWER SUPPLY VOLTAGE-V

r-- I -

10
POWER SUPPLY VOLTAGE-V

Of'(J4700S

Figure 7. Second-Order Output Intercept vs Supply Voltage

February 12, 1987

Figure 8. Third-Order Intercept vs Supply Voltage

4-6

Signetics Linear Products

Product Specification

NEjSA5204

Wide-band High-Frequency Amplifier

2.0

2.0

1.9

'"
~

'"

1.9

1.8

1.8

1.7

1.7

'"
~

1.6

'">I-

> 1.5

. ==

I::I

~

..
::I
I0

1.4
1.3

"

Zo=750

1.2

1.6
1.5
1.4
1.3

I---Zo=750

1.2

1.1 -

Zo=500

1.1 I--- Zo = 500

1.0
10'

1.0
10'

8 102

6

Figure 9. Input VSWR vs Frequency

35

"''''

30

"I",
I
"'0
0 ....

.... z
z'"
"'::I

::III-w
wa:
"'I1-::1
::Ie..
"I-

~5

• • 103

II

-10
I

..........

25
20

8 102

Figure 10. Output VSWR vs Frequency

40

",'Il

6

FREQUENCY -MHz

FREQUENCY -MHz

-

- IS

~~ ::-- ..... OUTPUT

'~"

~

~

VCC=6V
Zo = 500
TA=2r C

ZO=50ll
TA=25°C
VCC=6V

z

2-20

INPU~

IS

~ -25

."-

.."..,.. i--'"

V

~

10
10'

6

8102

6

-30
10'

8103

FREQUENCV-MHz

6

8 102

6

8103

FREQUENCY -MHz

Figure 11. Input (S,,) and Output (S22) Return Loss vs
Frequency

Figure 12. Isolation vs Frequency (S'2)

25

25
VCC=8V""\

"'"zI
:c

"z

VCc=~V

0

tiw

II)

-

VCC=TV"""\ \
20

VCC=5V -

15

~

/

'"~
~

"'-

20

ti

II)

!

Zo = 750
TA=25°C

.

rr-

r_,

"0z
W

-r---

TA= -40 0 ; )
TA= 25°CL

TA= 85°C'IS I--- Zo = 750
r-VCC=6V

••

10

10
10'

6

a 102

6

10'

8 103

8 102

6

8 103

Figure 14. Insertion Gain vs Frequency (S21)

Figure 13. Insertion Gain vs Frequency (S21)

February 12. 1987

6

FREQUENCY -MHz

FREQUENCY-MHz

4-7

Signetics Linear Products

Product Specification

NEjSA5204

Wide-band High-Frequency Amplifier

THEORY OF OPERATION
The design is based on the use of multiple
feedback loops to provide wide-band gain
together with good noise figure and terminal
impedance matches. Referring to the circuit
schematic in Figure 15, the gain is set primarily by the equation:
(1)

which is series-shunt feedback. There is also
shunt-series feedback due to RF2 and RE2
which aids in producing wide-band terminal
impedances without the need for low value
input shunting resistors that would degrade
the noise figure. For optimum noise performance, RE1 and the base resistance of 0 ,
are kept as low as possible, while RF2 is
maximized.
The noise figure is given by the following
equation:

NF

= 10Log

t
,

~] }

[rb + RE1 +
1 + _ _ _ _-=2"'q"'lc1
Ro

dB
(2)

where IC1 = 5.5mA, RE1 = 12f!, rb = 130f!,
KT/q = 26mV at 25·C and Ro = 50 fora SOf!
system and 75 for a 75f! system.

The DC input voltage level VIN can be determined by the equation:
(3)

where RE1 = 12f!, VSE = O.BV, IC1 = SmA
and lea = 7mA (currents rated at Vcc = 6V).
Under the above conditions, VIN is approximately equal to W.

The output stage is a Darlington pair (Oa and
O2) which increases the DC bias voltage on
the input stage (a,) to a more desirable
value, and also increases the feedback loop
gain. Resistor Ro optimizes the output VSWR
(Voltage Standing Wave Ratio). Inductors L,
and L2 are bondwire and lead inductances
which are roughly 3nH. These improve the
high-frequency impedance matches at input
and output by partially resonating with O.SpF
of pad and package capacitance.

Level shifting is achieved by emitter-follower

03 and diode 04, which provide shunt feedback to the emitter of 0, via RF1. The use of
an emitter-follower buffer in this feedback
loop essentially eliminates problems of shuntfeedback loading on the output. The value of
RF1 = 140f! is chosen to give the desired
nominal gain. The DC output voltage VOUT
can be determined by:
VOUT =' Vcc - (lc2+ Ica)R2,
where Vcc = 6V, R2 = 22Sf!, IC2
Ice = SmA.

(4)

= 7mA

and

From here, it can be seen that the output
voltage is approximately 3.3V to give relatively equal positive and negative output swings.
Diode 05 is included for bias purposes to
allow direct coupling of RF2 to the base of
The dual feedback loops stabilize the DC
operating point of the amplifier.

a,.

POWER DISSIPATION
CONSIDERATIONS
When using the part at elevated temperature,
the engineer should consider the power dissipation capabilities of each package.
At the nominal supply voltage of 6V, the
typical supply current is 2SmA (30mA max).
For operation at supply voltages other than
6V, see Figure 1 for Ice versus Vee curves.
The supply current is inversely proportional to
temperature and varies no more than 1mA
between 2S·C and either temperature extreme. The change is 0.1 % per ·C over the
range.
The recommended operating temperature
ranges are air-mount specifications. Better
heat-sinking benefits can be realized by
mounting the SO and N package bodies
against the PC board plane.

vee

R,
225

R,
650

Ro

l,

'0

3nH

VOUT

a,
a,
R3
140

a,

140

200

Figure 15. Schematic Diagram

February 12, 19B7

4-8

Signetics linear Products

Product Specification

Wide-band High-Frequency Amplifier

PC BOARD MOUNTING
In order to realize satisfactory mounting of the
NE5204 to a PC board, certain techniques
need to be utilized. The board must be
double-sided with copper and all pins must be
soldered to their respective areas (i.e., all
GND and Vee pins on the package). The
power supply should be decoupled with a
capacitor as close to the Vee pins as possible, and an RF choke should be inserted
between the supply and the device. Caution
should be exercised in the connection of
input and output pins. Standard microstrip
should be observed wherever possible. There
should be no solder bumps or burrs or any
obstructions in the signal path to cause
launching problems. The path should be as
straight as possible and lead lengths as short
as possible from the part to the cable connection. Another important consideration is that
the input and output should be AC-coupled.
This is because at Vee = 6V, the input is
approximately at 1V while the output is at
3.3V. The output must be decoupled into a
low-impedance system, or the DC bias on the
output of the amplifier will be loaded down,
causing loss of output power. The easiest
way to decouple the entire amplifier is by
soldering a high-frequency chip capacitor directly to the input and output pins of the
device. This circuit is shown in Figure 16.
Follow these recommendations to get the
best frequency response and noise immunity.
The board design is as important as the
integrated circuit design itself.
Both of the evaluation boards that will be
discussed next do not have input and output
capacitors because it is assumed the user will
use AC-coupled test systems. Chip or foil
capacitors can easily be inserted between the
part and connector if the board trace is
removed.

NE/SA5204

8-LEAD MINI-PACK; PLASTIC (50-8; SOT-96A)

1

n n

o

D :::: 0

u

,

.~

CAPACITOR HOLE (0.25 M )

Vee PLANE
OUTPUT

GNDPLANE
INPUT

GNOPlANE

1__ ···- __1

SO PACKAGE
HOLE BACKSIDE

SO PACKAGE
HOLE TOPSIDE

TOP

BOTTOM

GNDFLANGE
SMA CONNECTOR

Figure 17. PC Board Layout for NE5204 Evaluation

vcc

f--oVOUT

AC
COUPLING
CAPACITOR

Figure 16. Circuit Schematic for
Coupling and Power Supply Decoupling

February 12, 1987

~

4-9

Signetics linear Products

Product Specification

NE/SA5204

Wide-band High-Frequency Amplifier

tion around its side to isolate Vee and ground.
The square hole is for the SO package which
is put in upside-down through the bottom of
the board so that the leads are kept in
position for soldering. Both holes are just
slightly larger than the capacitor and IC to
provide for a tight fit.

50n. EVALUATION BOARD
The evaluation board layout shown in Figure
17 produces excellent results. The board is to
scale and is for the SO package. Both top
and bottom are copper clad and the ground
planes are bonded together through 50n
SMA cable connectors. These are solder
mounted on the sides of the board so that the
signal traces line up straight to the connector
signal pins.

This board should be tested in a system with
50n input and output impedance for correct
operation.

Solid copper tubing is soldered through the
flange holes between the two connectors for
increased strength and grounding characteristics. Two- or four-hole flanges can be used.
A flat, round decoupling capacitor is placed in
the board's round hole and soldered between
the bottom Vcc plane and the top side
ground. The capacitor is as thin or thinner
than the PC board thickness and has insula-

75n. EVALUATION BOARD
Another evaluation board is shown in Figure
18. This system uses the same PC board as
presented in Figure 17, but makes use of 75n
female N-type connectors. The board is
mounted in a nickel plated box' that is used
to support the N-type connectors. This is an

excellent way to test the part for cable TV
applications. Again, the board should be tested in a system with 75n input- and outputimpedance for correct operation.
NOTE:
"'The box and connectors are available as a "MOOPACK SYSTEM" from the ANZAC division of
ADAMS-RUSSELL CO., INC., 80 Cambridge Street,
Burlington, MA 01803.

SCATTERING PARAMETERS
The primary specifications for the NE5204
are listed as S-parameters. S-parameters are
measurements of incident and reflected currents and voltages between the source, amplifier, and load as well as transmission
losses. The parameters for a two-port network are defined in Figure 19.

FEEDTHRU

MODEL 7014
7014-1 (BNC)
7014-2 (TNC)
7014-3 (TYPE H)
7014-4 (SMA)

0.469r-/
I
(11.9)!

0'3~iCO'062
(U)

0.750
(19.1)

1.084
(27.5)

0.200 (5.1) TVP
0.290 (7.4) TVP

[0·
O.984L-J
(24.9)

TYP

(1.6)

BOTTOMV,EW

Figure 18. 75n N-Type Connector System

February 12, 1987

l lS
r-

4-10

Product Specification

Signetics Linear Products

NEjSA5204

Wide-band High-Frequency Amplifier

.

S1\ -

s"

INPUT RETURN LOSS

S" -

POWER REFLECTED
FROM INPUT PORT

"I

S" 'VTRANSDUCER POWER GAIN

POWER AVAILABLE FROM
GENERATOR AT INPUT PORT

I··

s"

S" -

FORWARD TRANSMISSION LOSS
OR INSERTION GAIN

S" -

OUTPUT RETURN LOSS
POWER REFLECTED
FROM OUTPUT PORT

REVERSE TRANSMISSION LOSS
OR ISOLATION

POWER AVAILABLE FROM
GENERATOR AT OUTPUT PORT

REVERSE TRANSDUCER
POWER GAIN

a. Two·Port Network Defined

b.
Figure 19

75n System

50n System

2,

25

Vee- 8V
VCC=7V

ve~~~~~

.....

VCC7'6V
VCC=5V

vcc=~v

vcc- 5V

f--Zo=500

r- TA:l25°C
r----

I.

I--

I.'

•

• 102

IS

I.

8 103

FREQUENCV-MHz

I.'

I
zo.1 50

-15

i
Q -20

<)

TA =25°C

!1i

I

I
z

2

VCC==6V - -

~

I.,....-V

I,

-25

5
!1l

6

10'

-20

-25

c--

10'

..
~i

........

30

~~

~Z

Za:

a:" 25

~W

~!
!is

20

-

VCC=6V

lA.2re
Zo·500

'103

IS

MHz

40
35

-- "

30

~z

za: 25 r - - -OUTPUT
a:"
wa: 20

:::--.... ~

,,~

~w

a:~

INP~~ N",

.""

1NPrT

~"
~

~5

VCC=6V

15

I><

20=750

TA",2SoC

6

10

• 102

FREQUENCY-MHz

I.'

6

6

8102

FREQUENCY -

e. Input (Sll) and Output (S22) Return Loss vs
Frequency

8103

MHz

f. Input (Sll) and Output (S22) Return Loss vs
Frequency
Figure 20

February 12, 1987

8,02

o~

OUTPUT

15

,.I.'

.. lZ
"0

~

,,~

V

6

d. S12 Isolation vs Frequency

4
'""
I-

=

a.
;; 1.'
1.3
1.2
1.1 1.0
'0'

::>

0.
I-

:>
0

Zo=7S0
20-500
6

8 102

IP2 = POUT + IMR2
IP3

= POUT + IMR3/2

where POUT is the power level in dBm of each
of a pair of equal level fundamental output
signals, IP2 and IP3 are the second- and thirdorder output intercepts in dBm, and IMR2 and
IMR3 are the second- and third- order intermodulation ratios in dB. The intermodulation
intercept is an indicator of intermodulation
performance only in the small-signal operat-

a: 1.7

VCc""SV

1.6

> 1.5
I:>

The intercept point is determined by measuring the intermodulation ratio at a single output
level and projecting along the appropriate
product slope to the point of intersection with
the fundamental. When the intercept point is
known, the intermodulation ratio can be determined by the reverse process. The second-order IMR is equal to the difference
between the second-order intercept and the
fundamental output level. The third-order IMR
is equal to twice the difference between the
third-order intercept and the fundamental output level. These are expressed as:

2.0
1.9
1.8

TA = 25"C

1.7

The intermodulation intercept is an expression of the low level linearity of the amplifier.
The intermodulation ratio is the difference in
dB between the fundamental output signal
level and the generated distortion product
level. The relationship between intercept and
intermodulation ratio is illustrated in Figure
22, which shows product output levels plotted
versus the level of the fundamental output for
two equal strength output signals at different
frequencies. The upper line shows the fundamental output plotted against itself with a 1dB
to 1dB slope. The second and third order
products lie below the fundamentals and
exhibit a 2:1 and 3:1 slope, respectively.
The intercept point for either product is the
intersection of the extensions of the product
curve with the fundamental output.

11 +S221
OUTPUT VSWR = -I- - I < 1.5
1 -S22

ldB GAIN COMPRESSION AND
SATURATED OUTPUT POWER

VOUT 2

:. - - = --2- = - - 2 - = PI

INTERMODULATION INTERCEPT
TESTS

6

8 103

FREQUENCY -MHz

1.6
1.5
1.'
1.3
Zo =750
1.2
1.1 ~.~ Za-SOP.
1.0
10'

r--

6

8 102

FREQUENCY-MHz

a. Input VSWR vs Frequency
b. Output VSWR vs Frequency
Figure 21. Input/Output VSWR vs Frequency
February 12, 1987

4-12

Signetics Linear Products

Product Specification

NE/SA5204

Wide-band High-Frequency Amplifier

ing range of the amplifier. Above some output
level which is below the 1dB compression
point, the active device moves into largesignal operation. At this point, the intermodulation products no longer follow the straightline output slopes, and the intercept description is no longer valid. It is therefore important
to measure IP 2 and IP3 at output levels well
below 1dB compression. One must be careful, however, not to select levels which are
too low, because the test equipment may not
be able to recover the signal from the noise.
For the NE5204, an output level of -1 0.5dBm
was chosen with fundamental frequencies of
100.000 and 100.01 MHz, respectively.

+30'--T~H-'~RO'-0-R~O~ER--r--,--cr-n--~~~~

+20

INTERCEPT POINT
1 dB --r-. T
r

+10

COMPRESSION
POINT
-

-20
-30
-40 "'----'-___L-'__- ' -__- ' - - - '__- ' -____--'-__..J
-60 -50 -40 -30 -20 -10
0 +10 +20 ,..30 -r-40
INPUT LEVEL

dBm

ADDITIONAL READING ON
SCATTERING PARAMETERS
For more information regarding S-parameters, please refer to High-Frequency Amplifiers; by Ralph S. Carson of the University of
Missouri, Rolla, Copyright 1985, published by
John Wiley & Sons, Inc.

February 12, 1987

Figure 22
S-Parameter Techniques for Faster, More
Accurate Network Design, HP App Note 95-1,
Richard W. Anderson, 1967, HP Journal.

4-13

S-Parameter Design, HP App

~Iote

154, 1972.

•

i

Signetics

NEjSAjSE5205
Wide-band High Frequency
Amplifier
Product Specification

Linear Products
DESCRIPTION
The NE/SA/SE5205 is a High Frequency Amplifier with a fixed insertion gain of
20dB. The gain is flat to ± 0.5dB from DC
to 450MHz, and the -3dB bandwidth is
greater than 600MHz in the EC package.
This performance makes the amplifier
ideal for cable TV applications. For lower
frequency applications, the part is also
available in industrial standard dual inline and small outline packages. The
NE/SAlSE5205 operates with a single
supply of 6V, and only draws 25mA of
supply current, which is much less than
comparable hybrid parts. The noise figure is 4.8dB in a 75n system and 6dB in
a 50n system.
Until now, most RF or high frequency
designers had to settle for discrete or
hybrid solutions to their amplification
problems. Most of these solutions required trade-offs that the designer had
to accept in order to use high frequency
gain stages. These include high power
consumption, large component count,
transformers, large packages with heat
sinks, and high part cost. The NE/SA/
SE5205 solves these problems by incorporating a wide-band amplifier on a single monolithic chip.
The part is well matched to 50 or 75n
input and output impedances. The
Standing Wave Ratios in 50 and 75n
systems do not exceed 1.5 on either the
input or output from DC to the -3dB
bandwidth limit.
Since the part is a small monolithic IC
die, problems such as stray capacitance
are minimized. The die size is small
enough to fit into a very cost-effective 8pin small-outline (SO) package to further
reduce parasitic effects. A TO-46 metal
can is also available that has a case
connection for RF grounding which increases the -3dB frequency to 650MHz.
The metal can and Cerdip package are
hermetically sealed, and can operate
over the full -55°C to + 125°C range.
No external components are needed
other than AC coupling capacitors because the NE/SA/SE5205 is internally
compensated and matched to SO and
February 12, 1987

75n. The amplifier has very good distortion specifications, with second and
third-order intermodulation intercepts of
+ 24dBm and + 17dBm respectively at
100MHz.

PIN CONFIGURATIONS
N, FE, 0 Packages

The device is ideally suited for 7Sn
cable television applications such as
decoder boxes, satellite receiver / decoders, and front-end amplifiers for TV receivers. It is also useful for amplified
splitters and antenna amplifiers.
The part is matched well for 50n test
equipment such as signal generators,
oscilloscopes, frequency counters and
all kinds of signal analyzers. Other applications at Son include mobile radio, CB
radio and data/video transmission in
fiber optics, as well as broad-band LANs
and telecom systems. A gain greater
than 20dB can be achieved by cascading additional NE/SAlSES205s in series
as required, without any degradation in
amplifier stability.

TOP VIEW

EC Package

NOTE:

Tab denotes Pin 1.

FEATURES
• 650MHz bandwidth
• 20dB insertion gain
• 4.8dB (6dB) noise figure
Zo 75n (Zo 50n)
• No external components required
• Input and output impedances
matched to 50175n systems
• Surface mount package available
• Excellent performance in cable
TV 75n systems

=

=

APPLICATIONS
• 75n cable TV decoder boxes
• Antenna amplifiers
• Amplified splitters
• Signal generators
• Frequency counters
• Oscilloscopes
• Signal analyzers
• Broad-band LANs
• Fiber-optics
• Modems
• Mobile radio
• CB radio
• Telecommunications
4-14

853-0058 87583

Signetics Linear Products

Product Specification

NE/SA/SE5205

Wide-band High Frequency Amplifier

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

4-Pin Cerdip

o to
o to
o to

+70°C

NE5205FE

B-Pin Plastic DIP

a to +70°C

NE5205N

B-Pin Plastic SO

-40°C to + B5°C

SA5205D

B-Pin Plastic DIP

-40°C to + B5°C

SA5205N

B-Pin Cerdip

-40°C to + B5°C

SA5205FE

B-Pin Cerdip

-55°C to + 125°C

SE5205FE

B-Pin Plastic SO
B-Pin Metal can

+70°C

NE5205D

+70°C

NE5205EC

EQUIVALENT SCHEMATIC
Vcc

R,

Rt

Ro
VOUT

0,
V,N

R.

Ot

Ro,
REt

.",.

RF'
.",.

February 12, 19B7

4-15

Signetics Linear Products

Product Specification

NEjSAjSE5205

Wide-band High Frequency Amplifier

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

RATING

UNIT

Vcc

Supply voltage

9

V

VAC

AC input voltage

5

Vp_p

TA

Operating ambient temperature range
NE grade
SA grade
SE grade

o to +70
-40 to +85
-55 to + 125

'C
'C
'C

780
1160
780
1250

mW
mW
mW
mW

Po

Maximum power dissipation,
TA=25'C (still air)1, 2
FE package
N package
D package
EC package

NOTES:
1. Derate above 25°C, at the following rates:

FE package al 6.2mW/"C
N package al 9.3mWI"C
o package al 6.2mW I"C
EC package al 10.0mWI"C
2. See "Power Dissipation Considerations" section.

DC ELECTRICAL CHARACTERISTICS at Vcc = 6V, Zs = ZL = Zo = 50n and TA = 25'C, in all packages, unless otherwise
specified.
SE5205
SYMBOL

PARAMETER

NE/SA/SE5205

TEST CONDITIONS

UNIT
Min

Typ

Max

Min

6.5
6.5

5
5

Operating supply voltage range

Over temperature

5
5

Icc

Supply current

Over temperature

20
19

24

30
31

20
19

S21

Insertion gain

f = 100MHz
Over temperature

17
16.5

19

21
21.5

17
16.5

811

Input return loss

f = 100MHz D, N, FE
DC - fMAX D, N, FE

S11

Input return loss

25
12

Output return loss

S22

Output return loss

Isolation

27

February 12, 1987

12

19

21
21.5

dB

dB
dB

-25
-18

dB
dB

26

-18

dB
dB

12

-25

dB
dB

10

f = 100MHz

4-16

mA
mA

27

f = 100MHz EC package

DC-fMAX

30
31

10

DC-FMAX
S12

24

24

f = 100MHz D, N, FE
DC-fMAX

V
V

25

f = 100MHz EC package

Max

8
8

12

DC-fMAX EC
S22

Typ

dB
dB

Signetics Linear Products

Product Specification

NEjSAjSE5205

Wide-band High-Frequency Amplifier

at Vee ~ 6V, Zs ~ ZL ~ Zo ~ 50S< and TA ~ 25°C, in all packages, unless otherwise
specified.

DC ELECTRICAL CHARACTERISTICS

SE5205
SYMBOL

PARAMETER

NE/SAlSE5205
UNIT

TEST CONDITIONS
Min

Typ

Max

Min

Typ

Max

BW

Bandwidth

±0.5dB D, N

fMAX

Bandwidth

-3dB D, N

fMAX

Bandwidth

± 0.5dB EC

300

500

MHz

fMAX

Bandwidth

± 0.5dB FE

300

300

MHz

fMAX

Bandwidth

-3dB EC

fMAX

Bandwidth

-3dB FE

450

J

28

~
a:
a:

~

MHz

Noise figure (75S<)

f

~

100MHz

4.8

4.8

Noise figure (50S<)

f

~

100MHz

6.0

6.0

dB

Saturated output power

f

~

100MHz

+7.0

+7.0

dBm

dB

1dB gain compression

f

~

100MHz

+4.0

+4.0

dBm

Third-order intermodulation
intercept (output)

f

~

100MHz

+17

+17

dBm

Second-order intermodulation
intercept (output)

f

~

100MHz

+24

+24

dBm

1 1

11
-

TA

Zo,:500
TA=25°C

.JVCC=8V
1

25°C

V~c=!V
Vee= 6V
Vee= 5V

2.

"~"

MHz

400

400

35
3.
30

MHz

600

32

"E

MHz

550

2.
22

~-

:A

A"

~~

.. -

1

20

,.
18

'I

5

5.5

5

•. 5

7.5

'0'

l

1
(j

8 102

FREQUENCY -MHz

SUPPLY VOLTAGE-V

Figure 1. Supply Current vs Supply Voltage

Figure 2. Noise Figure vs Frequency

2S

Vcc· 7V

Vcc! 8V

!!l

VCC-7V~'f--

I 20

z

~
~

Vee= BV

VCC=:5V

~

~

ffi

vcc· 6V

I:-

VCC:=6V
Vcc=5V

15 -Zo·50Q

-TA==25°C

""

10

'0'

6

8 102

6

FREQUENCY -MHl'

Figure 3. Insertion Gain vs Frequency (52,)

February 12, 1987

8 102

FREaUENCY -MH2:

Figure 4. Insertion Gain vs Frequency (52,)

4-17

II

Signetics Linear Products

Product Specification

Wide-band High-Frequency Amplifier

NEjSAjSE5205

10
9
B

11
10

Vee=7V
Vee=6V

Vee=BV

-

~ ~

i

VCC=5V

~

I-

~O -2-~

~

-

-4 r-TA=25"C
•

102

8

Vee=BV

i=
1

0

-Zo=500
TA=25'C

6

8103

35

~

30

0

20

II:

z

'"

.."...i
I-

1/

'"

/

25

If

I
Q

8w

II:

I!!3!;
II:

w

Q

TA=25°C
Zo·500

~

15

~
a:

;:

'">
...'"3!;

TA=25°C
Zo=500

[

II:

f

15

'/

20

/

10

10

7

8

4

10

10
POWER SUPPLY VOLTAGE-V

Figure 8. Third·Order Intercept vs
Supply Voltage

2.0

2.0

1.9

1.9

1.B

1.8

1.7

a: 1.7
jI:
1.6

1.6

'>"
'"...

1.5

1.3

I-

r=

I-

'"0

Zo=750

1.2
1.1

I--

5
4

1.4

-

I

'(

I-

Figure 7. Second-Order Output Intercept vs
Supply Voltage

I-

8 102

25

POWER SUPPLY VOLTAGE-V

II:
jI:

.....

30

Q

II:

"

ID

I-

3!;

" ...

E

ID

I;:

"-

Figure 6. 1dB Gain Compression vs Frequency

40

..
.

.......

FREQUENCY-MHz

Figure 5. Saturated Output Power vs Frequency

E

-

-,...
6

10'

FREQUENCY-MHz

...I

....

Vec=5V

-3 -4
-5
-6

-3 r-Zo=500

10'

Vee=7V

5

§ :~

-5
-6

Vee=BV

1.5
1.4
1.3
1.2

r--- Zo=SOO

1.0
10'

1.1
6

t--- Zo= 500

1.0
10'

8 102

6

8 102

FREQUENCY-MHz

FREQUENCY -MHz

Figure 9. Input VSWR vs Frequency

February 12, 1987

r--- Zo =750

Figure 10. Output VSWR vs Frequency

4-18

Signetics Linear Products

Product Specification

Wide-band High-Frequency Amplifier

,

40

a:I!:g

Ich

35

U)U)

~

9

30

-'z

za:

a: ~
=> ....

25

wa:

20

5

15

-

=>a.
a. ....
~

I
I

,

10
10'

II:

I~ ~ ~, OUTPUT

=>

....a.

I
6

'"....>

I

INP~~

TA=2r C

3:

I

~

Zo= son

I

I

I

VCC=~V

.... W

a: ~
.... =>

i

NE/SA/SE5205

v.-

8102

=>

0

"'\

6

8103

2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
-Zo=750
1.2
1.1 -Zo=500
1.0
10'

VCC=~v,

..

8 102

Figure 12. Isolation vs Frequency (5 12)

Figure 11. Input (511l and Output (522) Return Loss vs
Frequency

25

a

FREQUENCY-MHz

FREQUENCY-MHz

25

VCC=7V"""\ \

I

'0

..
"

I
z 20

z

....

VCc=~V

0

~ 15

VCC=5V~

W

'":!!!

r----10

T~= -55~

\

TA= 25°C

,.,
,

TA= 8SoC

Zo =750

6

8 102

6

8103

I..

10'

6

8 102

6

8 103

FREQUENCY-MHz

FREQUENCY -MHz

Figure 13. Insertion Gain vs Frequency (521)

February 12. 1987

.•

TA=25°C

10
10'

r-

"""'\1

TA=12S o C ~

I--Zo=750
I-- VCC=6V

r-

Figure 14. Insertion Gain vs Frequency (521l

4-19

Product Specification

Signetics Linear Products

Wide-band High-Frequency Amplifier

NE/SA/SE5205

THEORY OF OPERATION
The design is based on the use of multiple
feedback loops to provide wide-band gain
together with good noise figure and terminal
impedance matches. Referring to the circuit
schematic in Figure 15, the gain is set primarily by the equation:
(1)

which is series-shunt feedback. There is also
shunt-series feedback due to RF2 and RE2
which aids in producing wideband terminal
impedances without the need for low value
input shunting resistors that would degrade
the noise figure. For optimum noise performance, RE1 and the base resistance of Q,
are kept as low as possible while RF2 is
maximized.
The noise figure is given by the following
equation:
NF=
10 Log

f

1+

[rb + RE1 +

~]J
2qic1

dB (2)

Ro

where ic1 = 5.5mA, RE1 = 12n, rb = 130n,
KT /q = 26mV at 25°C and Ro = 50 for a 50n
system and 75 for a 75n system.
The DC input voltage level VIN can be determined by the equation:

where RE1 = 12n, VSE = 0.8V, IC1 = 5mA
and IC3 = 7mA (currents rated at Vcc = 6V).
Under the above conditions, VIN is approximately equal to 1V.
Level shifting is achieved by emitter-follower
Q3 and diode Q4 which provide shunt feedback to the emitter of Q, via RF1. The use of
an emitter-follower buffer in this feedback
loop essentially eliminates problems of shunt
feedback loading on the output. The value of
RF1 = 140n is chosen to give the desired
nominal gain. The DC output voltage VO UT
can be determined by:
VOUT = VCC - (ic2+ IC6)R2,
where Vcc
IC6 = 5mA.

= 6V,

R2

= 225n,

(4)
IC2

= 7mA

and

From here it can be seen that the output
voltage is approximately 3.3V to give relatively equal positive and negative output swings.
Diode Q5 is included for bias purposes to
allow direct coupling of RF2 to the base of Q,.
The dual feedback loops stabilize the DC
operating point of the amplifier.
The output stage is a Darlington pair (Q6 and
Q2) which increases the DC bias voltage on
the input stage (Q,) to a more desirable
value, and also increases the feedback loop
gain. Resistor Ro optimizes the output VSWR

(Voltage Standing Wave RatiO). Inductors L,
and L2 are bondwire and lead inductances
which are roughly 3nH. These improve the
high frequency impedance matches at input
and output by partially resonating with 0.5pF
of pad and package capacitance.

POWER DISSIPATION
CONSIDERATIONS
When using the part at elevated temperature,
the engineer should consider the power dissipation capabilities of each package.
At the nominal supply voltage of 6V, the
typical supply current is 25mA (30mA Max).
For operation at supply voltages other than
6V, see Figure 1 for Icc versus Vcc curves.
The supply current is inversely proportional to
temperature and varies no more than 1mA
between 25°C and either temperature extreme. The change is 0.1 % per °C over the
range.
The recommended operating temperature
ranges are air-mount specifications. Better
heat sinking benefits can be realized by
mounting the D and EC package body against
the PC board plane.

PC BOARD MOUNTING
In order to realize satisfactory mounting of the
NE5205 to a PC board, certain techniques
need to be utilized. The board must be
double-sided with copper and all pins must be
soldered to their respective areas (i.e., all

Vee

A,
22S

A,
650

a,
a,
A,
140

a,

140

200

Figure 15. Schematic Diagram
February 12, 1987

4-20

Ao

L,

10

3nH

VOUT

Signetics Linear Products

Product Specification

Wide-band High-Frequency Amplifier

GND and Vee pins on the SO package). In
addition, if the EC package is used, the case
should be soldered to the ground plane. The
power supply should be decoupled with a
capacitor as close to the Vee pins as possible
and an RF choke should be inserted between
the supply and the device. Caution should be
exercised in the connection of input and
output pins. Standard microstrip should be
observed wherever possible. There should be
no solder bumps or burrs or any obstructions
in the signal path to cause launching problems. The path should be as straight as
possible and lead lengths as short as possible from the part to the cable connection.
Another important consideration is that the
input and output should be AC coupled. This
is because at Vee = 6V, the input is approximately at 1V while the output is at 3.3V. The
output must be decoupled into a low impedance system or the DC bias on the output of
the amplifier will be loaded down causing loss
of output power. The easiest way to decouple
the entire amplifier is by soldering a high
frequency chip capacitor directly to the input
and output pins of the device. This circuit is
shown in Figure 16. Follow these recommendations to get the best frequency response
and noise immunity. The board design is as
important as the integrated circuit design
itself.

NE/SA/SE5205

vcc

f--o VOUT

V'No--j

AC
COUPLING

CAPACITOR

Figure 16. Circuit Schematic
for Coupling and Power Supply
Decoupllng

8-LEAD MINI-PACK; PLASTIC (SO-8; SOT-96A)

Both of the evaluation boards that will be
discussed next do not have input and output
capacitors because it is assumed the user will
use AC coupled test systems. Chip or foil
capacitors can easily be inserted between the
part and connector if the board trace is
removed.
CAPACITOR HOlE (0.':0")---,

50n EVALUATION BOARD
The evaluation board layout shown in Figure
17 produces excellent results. The board is to
scale and is for the SO package but can be
used for the EC package as well. Both top
and bottom are copper clad and the ground
planes are bonded together through 50n
SMA cable connectors. These are solder
mounted on the sides of the board so that the
signal traces line up straight to the connector
signal pins.
Solid copper tubing is soldered through the
flange holes between the two connectors for
increased strength and grounding characteristics. Two or four hole flanges can be used.
A flat round decoupling capacitor is placed in
the board's round hole and soldered between
the bottom Vee plane and the top side
ground. The capacitor is as thin or thinner
than the PC board thickness and has insulation around its side to isolate Vee and ground.
The square hole is for the SO package which
is put in upside down through the bottom of
the board so that the leads are kept in
February 12, 1987

-t

Vee PLANE
OUTPUT

PLANE

0.75"

GNDPLANE

l

SO PACKAGE
HOLE BACKSIDE

SO PACKAGE
HOLE TOPSIDE
BOTTOM

TOP

GND FLANGE
SMA CONNECTOR

Figure 17. BC Board Layout for NE/SA/SE5205 Evaluation

4-21

Product Specification

Signetics Linear Products

NEjSAjSE5205

Wide-band High-Frequency Amplifier

position for soldering. Both holes are just
slightly larger than the capacitor and IC to
provide for a tight fit.

presented in Figure 17, but makes use of 7Sn
female N-type connectors. The board is
mounted in a .nickel plated box' that is used
to support the N-type connectors. This is an
excellent way to test the part for cable TV
applications. Again, the board should be tested in a system with 7Sn input and output
impedance for correct operation.

This board should be tested in a system with
son input and output impedance for correct
operation.

7sn EVALUATION BOARD

"The box and connectors are available as a "MODM

Another evaluation board is shown in Figure
16. This system uses the same PC board as

PACK SYSTEM" from the ANZAC division of

ADAMS-RUSSELL CO.• INC .. 80 Cambridge Street.
Burlington, MA 01803.

SCATTERING PARAMETERS
The primary specifications for the NE/SAI
SES20S are listed as S-parameters. S-parameters are measurements of incident and reflected currents and voltages between the
source, amplifier and load as well as transmission losses. The parameters for a two-port
network are defined in Figure 19.

FEEOTHAU

··...·M
)! I
(11 .•

MODEL 701.
7014-1 (BHC)
7014-2 (TNC)
7014-3 (TYPE N)
7014-4 (SMA)

.'3~it.'.82TYP
(t.5)

0.750
(19.1)

1.084
(27.S)

0.200 (5.1) TYP

[0·
O.984L--J
(24.9)

(1.8)

BOTTOMV'EW

Figure 18. 75n N-Type Connector System

521

•

•

I~

8"

Figure 19a. Two-Port Network Defined

February 12, 1967

l .Lr
r- •.

4-22

290 (7.4) TYP

Signetlcs Linear Products

Product Specification

Wide-band High-Frequency Amplifier

S" -

INPUT RETURN LOSS

S" -

POWER REFLECTED
FROM INPUT PORT

Actual S-parameter measurements using an
HP network analyzer (model 8505A) and an
HP S-parameter tester (models 8503A1B) are
shown in Figure 20. These were obtained with
the device mounted in a PC board as described in Figures 17 and 18.

FORWARD TRANSMISSION LOSS
OR INSERTION GAIN

S" "VTRANSDUCER POWER GAIN

POWER AVAILABLE FROM
GENERATOR AT INPUT PORT
S" -

NEjSAjSE5205

S22 -

OUTPUT RETURN LOSS

For Son system measurements, SMA connectors were used. The 7Sn data was obtained using N-connectors.

POWER REFLECTED
FROM OUTPUT PORT

REVERSE TRANSMISSION LOSS
OR ISOLATION

POWER AVAILABLE FROM
GENERATOR AT OUTPUT PORT

REVERSE TRANSDUCER
POWER GAIN

Values for the figures below are measured
and specified in the data sheet to ease
adaptation and comparison of the NE/SAI
SES20S to other high frequency amplifiers.

Figure 19b

son System

75n System
25

25

-

VCC=8V""",

VCC~~

'Il

z
;;

iii'"

VCC:;=6V

~

YCC=5V

-Zo=50D

15

_TA-2SoC

VCC",7V

1z 20

Vcc- 7V =7

I 20

5

.,
;;
z
g

'"

"

vcc=~v

Ii:W

VCC=5V-

'" " r--~

I--

10

=

Zo 750
TA=25°C

10
6

10'

8 102

6

10'

FREQUENCY-MHz

a. Insertion Gain vs Frequency (5 21 )

b. Insertion Gain vs Frequency (521)

-10

-10

I

-15

I

'"
1
z

II

~
iil

I
I

Q -20

- -25

I

-30
6

10'

zo=lson
TA=25'C
VCC=6V

'Il

-15

I

_~,

z

Q -20

t;;

I' .......... i- I

~ -25

~I

Zo = 750

TA=25°C

6

10'

09
==
-'z

30

""
"'"
....

2.

z ..

d. 5'2 Isolation vs Frequency
40

.,ig

i~
z~

~I

.........
-

VCC=8V

Zo·sao

OUTPUT

I~

-0 "
•

8 102

6

09
-'z

30

z ..

""
"'"
~:i!

25

-

r--- t- OUTPUT

~

20

........ X
VCC=6V

INP,T

z"
-0
"

8103

V

20=750
TA",2S·C

10
10'

FREQUENCY-MHz

6

8,02

FREQUENCY - MHz

e. Input (S,d and Output (522) Return Loss vs
Frequency

f. Input (511) and Output (522) Return Loss vs
Frequency

Figure 20
February 12, 1987

:g"'

5~
.....

'NP~~ ~"

TA=2r C

10
10'

35

I",

III:::~

I;jw

20

6 8,03

8,02

FREQUENCY - MHz

c. Isolation vs Frequency (5'2)

35

V

I
-30

8 102

40

.,"

l/V

VCC=6V

-

FREQUENCY -MHz

11

8 102

FREQUENCY -MHz

4-23

Signetics Linear Products

Product Specification

NEjSAjSE5205

Wide-band High-Frequency Amplifier

The most important parameter is S21. It is
defined as the square root of the power gain,
and, in decibels, is equal to voltage gain as
shown below:
ZD

= ZIN = ZOUT

to 1dB slope. The second and third order
products lie below the fundamentals and
exhibit a 2:1 and 3:1 slope, respectively.

INPUT RETURN LOSS = S11dB
S"dB = 20 Log Is ,, 1
OUTPUT RETURN LOSS = S22dB
S22dB = 20 Log IS221

for the NE/SA/SES20S

INPUT VSWR =

The intercept point for either product is the
intersection of the extensions of the product
curve with the fundamental output.

11 + S11 I
-I- - I .;; 1.S
1-S11

OUTPUT VSWR =

11+S22 1

-I--I';; 1.5
1 -S22

VOUT 2
POUT

~

2

1dB GAIN COMPRESSION AND
SATURATED OUTPUT POWER

VOUT
:. - - = --2- =--2= PI
PIN

VIN

VIN

The 1dB gain compression is a measurement
of the output power level where the smallsignal insertion gain magnitude decreases
1dB from its low power value. The decrease
is due to nonlinearities in the amplifier, an
indication of the point of transition between
small-signal operation and the large signal
mode.

ZD
PI = VI 2
PI
VI

= Insertion
= Insertion

Power Gain
Voltage Gain

Measured value for the
NE/SA/SES205 = IS21 12 = 100

The saturated output power is a measure of
the amplifier's ability to deliver power into an
external load. It is the value of the amplifier's
output power when the input is heavily overdriven. This includes the sum of the power in
all harmonics.

... PI =POUT
- - = IS21 12 = 100
PIN
VOUT
and VI=--=VPl=S21 =10
VIN
In decibels:
PI(dB) = 10 Log IS2112 = 20dB
VI (dB) = 20 Log S21

INTERMODULATION INTERCEPT
TESTS

= 20dB

The intermodulation intercept is an expression of the low level linearity of the amplifier.
The intermodulation ratio is the difference in
dB between the fundamental output signal
level and the generated distortion product
level. The relationship between intercept and
intermodulation ratio is illustrated in Figure
22, which shows product output levels plotted
versus the level of the fundamental output for
two equal strength output signals at different
frequencies. The upper line shows the fundamental output plotted against itself with a 1dB

:. PI(dB) = VI (dB) = S21 (dB) = 20dB
Also measured on the same system are the
respective voltage standing wave ratios.
These are shown in Figure 21. The VSWR
can be seen to be below 1.5 across the entire
operational frequency range.
Relationships exist between the input and
output return losses and the voltage standing
wave ratios. These relationships are as follows:

The intercept point is determined by measuring the intermodulation ratio at a single output
level and projecting along the appropriate
product slope to the point of intersection with
the fundamental. When the intercept point is
known, the intermodulation ratio can be determined by the reverse process. The second
order IMR is equal to the difference between
the second order intercept and the fundamental output level. The third order IMR is
equal to twice the difference between the
third order intercept and the fundamental
output level. These are expressed as:
IP2 = POUT + IMR2
IP3 = POUT + IMR3/2
where POUT is the power level in dBm of each
of a pair of equal level fundamental output
signals, IP2 and IP3 are the second and third
order output intercepts in dBm, and IMR2 and
IMR3 are the second and third order intermodulation ratios in dB. The intermodulation
intercept is an indicator of intermodulation
performance only in the small signal operating range of the amplifier. Above some output
level whiCh is below the 1dB compression
point, the active device moves into largesignal operation. At this point the intermodulation products no longer follow the straight
line output slopes, and the intercept description is no longer valid. It is therefore important
to measure IP2 and IP3 at output levels well
below 1dB compression. One must be careful, however, not to select too low levels
because the test equipment may not be able
to recover the signal from the noise. For the
NE/SAlSES20S we have chosen an output
level of -1 O.SdBm with fundamental frequencies of 100.000 and 100.01 MHz, respectively.

2.0
I .•

1.9

1.B
1.7

~
~

1.'

TA= 25"C

Vcc- 6V

~

~

1.6

'">

I.'

~

~

i!O

1.7
1.6

- -I

,

TA_2S"C

'~--;-r-r-VCC=6V

----+I-

1.5
1.4

j

0

I.'
1.1

1.0
10'

'.3

-Zo 75{l

1.2

r-- 20=500

1.1
6

~Zo-50n

1.0
10'

8102

6

FREQUENCY -MHz

a. Input VSWR vs Frequency

b. Output VSWR vs Frequency

Figure 21. Input/Output VSWR vs Frequency
February 12, 1987

8 102

FREQUENCY -MHz

4-24

Signetics Linear Products

Product Specification

Wide-band High-Frequency Amplifier

ADDITIONAL READING ON
SCATTERING PARAMETERS
For more information regarding S-parameters, please refer to High-Frequency Amplifiers by Ralph S. Carson of the University of
Missouri, Rolla, Copyright 1985; published by
John Wiley & Sons, Inc.
"S-Parameter Techniques for Faster, More
Accurate Network Design", HP App Note 951, Richard W. Anderson, 1967, HP Journal.
"S-Parameter Design", HP App Note 154,
1972.

NE/SA/SE5205

t-30
+20

~

+10

w

~

......
~E

["

....

-10

0

"

-20

THIRD ORDER
INTERCEPT POINT
t
1 dB
COMPRESSION
POINT
!
i
I
FUNDAMENTAL
RESPONSE
-~

i
I

-30

-40 1£....-'-_-"-""'-'_-'-_-'---'_-'-_ _-"-_-'
-60 -50 -40 -30 -20 -10
0 +10 ,..20 ,.-30 ,.-40
INPUT LEVEL
dBm

Figure 22

February 12, 1987

4-25

NE/SE5539

Signetics

Ultra-High Frequency
Operational Amplifier
Product Specification

Linear Products

PIN CONFIGURATION

DESCRIPTION

FEATURES

The NE/SE5539 is a very wide bandwidth, high slew rate, monolithic operational amplifier for use in video amplifiers, RF amplifiers, and extremely high
slew rate amplifiers.

• Gain bandwidth product: 1.2GHz
at 17dB
• Slew rate: SOO/V IlS
• Full power response: 48MHz
• AVOL: 52dB typical
• 350M Hz unity gain

Emitter-follower inputs provide a true
differential high input impedance device.
Proper external compensation will allow
design operation over a wide range of
closed-loop gains, both inverting and
non-inverting, to meet specific design
requirements.

D, F, N Packages

FREQUENCY
COMPENSATION

APPLICATIONS
•
•
•
•

Fast pulse amplifiers
RF oscillators
Fast sample and hold
High gain video amplifiers
(BW> 20MHz)

TOP VIEW

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

o to
o to
o to

14-Pin Plastic DIP
14-Pin Plastic SO
14-Pin Cerdip

ORDER CODE

+70°C

NE5539N

+70°C

NE5539D

+70°C

NE5539F

14-Pin Plastic DIP

-55°C to + 125°C

SE5539N

14-Pin Cerdip

-55°C to + 125°C

SE5539F

ABSOLUTE MAXIMUM RATINGS 1
PARAMETER

SYMBOL

RATING

UNIT

Vcc

Supply voltage

±12

V

Po

Internal power dissipation

550

mW

-65 to + 150

°C

150

°C

o to 70
-55 to + 125

°C
°C

300

°C

TSTG

Storage temperature range

TJ

Max junction temperature

TA

Operating temperature range
NE
SE

TSOLO

Lead temperature (10sec max)

NOTE:

1. Differential input voltage should not exceed O.25V to prevent excessive input bias current and
common-mode voltage 2.5V. These voltage limits may be exceeded if current is limited to less
than 10mA.

October 10, 1986

4-26

853-0814 85931

Product Specification

Signetics Linear Products

NE/SE5539

Ultra-High Frequency Operational Amplifier

EQUIVALENT CIRCUIT
(12) FREOUENCY COMPo
(10)

+VCC

{-)14

VERTING INPUT

V

(+)1

'"

NO N-tNVERTtNG

INPUT

~-F

~

>

V

I~- v

?-

'"

t--o

III

(8) OUTPUT

I

2.2K

(7)GND

J

~

-K

'"

(3)-VCC

DC ELECTRICAL CHARACTERISTICS Vcc = ± 8V, TA = 25°C, unless otherwise specified.
SE5539
SYMBOL

PARAMETER

UNIT
Min

Vos

Input offset voltage

2

5

2

3

Over temp

0.1

3

TA = 25°C

0.1

1

CMRR

Common·mode rejection ratio

Min

25

TA = 25°C

5

13

5

10

Over temp

80

70

80

5
IlV/oC

10
70

80

vA
nA/oC

0.5

6

70

2.5

2

0.5

F=1kHz, Rs=100n, VCM. ±1.7V

Max

5

Over temp

D.lsl D.T

Typ

mV

5

D.losl D.T

Input bias current

Max

TA = 25°C

Input offset current

Is

Typ

Over temp
Vo = OV, Rs = 100n

D.Vosl D.T

los

NE5539

TEST CONDITIONS

20

vA
nArC
dB
dB

RIN

Input impedance

100

100

kn

ROUT

Output impedance

10

10

n

October 10, 1986

4-27

Signetics Linear Products

Product Specification

NE/SE5539

Ultra-High Frequency Operational Amplifier

DC ELECTRICAL CHARACTERISTICS

vee = ± 6V,

(Continued)

TA = 25'C, unless otherwise specified.
SE5539

SYMBOL

PARAMETER

UNIT
Min

VOUT

Output voltage swing

RL = 150n to GND and
470n to -Vce

Output voltage swing

RL = 2kn to
GND
TA = 25'C

lee+

Positive supply current

lee-

Negative supply current

PSRR

Power supply rejection ratio

Va = 0, R j =

Max

Min

Typ

+2.3 +2.7

-Swing

-1.7

+ Swing

+2.3 +3.0

-Swing

-1.5

+ Swing

+2.5 +3.1

-Swing

-2.0

Large signal voltage gain

AVOL

Large signal voltage gain

AVOL

Large signal voltage gain

DC ELECTRICAL CHARACTERISTICS

V

-2.1
V
-2.7

Over temp

14

16

= 25'C

14

17

Over temp

11

15

TA = 25'C

11

14

Over temp

300

1000

14

16

11

15

200

1000

47

52

57

Vo=+2.3V, -1.7V
RL = 150n to GND, 470n to -Vee
Vo=+2.3V, -1.7V
RL = 2n to GND

47

52

57

Va = +2.5V, -2.0V
RL = 2kn to GND

= ± 6V,

mA

mA

00

~Vee=±IV

vee

V

-2.2

TA = 25'C
AVOL

Max

00

TA
Va = 0, R j =

Typ

+ Swing

Over temp
VOUT

NE5539

TEST CONDITIONS

TA = 25'C
Over temp

46

TA = 25'C

46

IlVN
dB

dB

60
53

dB

56

T A = 25'C, unless otherwise specified.
SE5539

SYMBOL

PARAMETER

TEST CONDITIONS

UNIT
Min

Vas

Input offset voltage

los

Input offset current

Is

Input bias current

CMRR

Common-mode reiection ratio

lee+

Positive supply current

lee-

Negative supply current

PSRR

Power supply rejection ratio

2

5

TA = 25'C

2

3

Over temp

0.1

3

TA = 25'C

0.1

1

Over temp

5

20

TA = 25'C

4

10

70

65
11

14

= 25'C

11

13

Output voltage swing

RL = 150n to GND
and 390n to - Vee

Over temp

6

11

TA = 25'C

6

10

Over temp

300

1000

October 10, 1986

4-28

p.A

mA

IlVN

+ Swing

+ 1.4

-Swing

-1.1

-1.7

+ Swing

+1.5

+2.0

-Swing

-1.4

-1.6

TA = 25'C

IlA

mA

TA = 25'C

VOUT

mV

dB

Over temp
TA

Over temp

Max

Over temp

VeM = ± 1.3V, Rs = lOOn

~Vee=±IV

Typ

+2.0
V

Signetics Linear Products

Product Specification

NEjSE5539

Ultra-High Frequency Operational Amplifier

AC ELECTRICAL CHARACTERISTICS

vcc = ± 8V, RL = 150n to GND & 470n to -Vcc, unless otherwise specified.
SE5539

SYMBOL

PARAMETER

UNIT
Min

BW

Gain bandwidth product

NE5539

TEST CONDITIONS
Typ

Max

Min

Typ

Max

ACL = 7, Va = 0.1 Vp_p

1200

1200

MHz

Small-signal bandwidth

ACL = 2, RL = 150n1

110

110

MHz

ts

Settling time

ACL = 2, RL = 150n1

15

15

ns

SR

Slew rate

ACL = 2, RL = 150n1

600

600

VIJ1s

tpD

Propagation delay

ACL = 2, RL = 150n1

7

7

ns

Full power response

ACL = 2, RL = 150n1

48

48

MHz

Full power response

Av = 7, RL = 150n1

20

20

MHz

Input noise voltage

Rs= son

4

4

nV/YHz

NOTE:
1. External compensation.

AC ELECTRICAL CHARACTERISTICS

Vcc = ±6V, RL = 150n to GND and 390n to -VCC, unless otherwise specified.
SE5539

SYMBOL

PARAMETER

TEST CONDITIONS

UNIT
Min

Typ

Max

Gain bandwidth product

ACL = 7

700

MHz

Small-signal bandwidth

ACL = 21

120

MHz

ts

Settling time

ACL = 21

23

ns

SR

Slew rate

ACL = 21

330

VIJ1s

Propagation delay

ACL = 21

4.5

ns

Full power response

ACL = 21

20

MHz

BW

tpD

NOTE:
1. External compensation.

TYPICAL PERFORMANCE CURVES
NE5539 Open-Loop Gain

NE5539 Open-Loop Phase

Q

360 l·'::
....
::-'-J.J..l.lllll:-:::-'...J....l.l..W'OOM"-H•.LJ..J..llWl,G...

October 10, 1986

1MHz

4-29

10MHz

100MHI

lGHz

II
I

Signetics Linear Products

Product Specification

NEjSE5539

Ultra-High· Frequency Operational Amplifier

TYPICAL PERFORMANCE CURVES (Continued)
Power Bandwidth (NE)

Power Bandwidth (SE)
4

.-77A

5

~
'\

4

3dBB.W.

,

~

3dB B.W.

~ .......

Xi

3

'r---

3

\

GAIN (-2)
Vee = :r8V

-'

f\."'2:Kll

,
,..."

FREQUENCY IN CYClES PER SECOND

,-

Vee

=

:!Cav

At. = 15011
GAIN {-2j

,..,"

..

FREQUENCY IN CYCLES PER SECONO

SE5539 Open-Loop Gain vs Frequency

Power Bandwidth

,...

3.04V

.-mm..

"'\

I ..
,

~

\.

3.~--------------~----~~~----+-----~

\.
r--

Vee = :!:6V
R!.. = 1261)

,....

~~

______________L-______________L-__

II!..

GAIN (-7j

At. = ISOU

FREQUENCY IN CYCLES PER SECOHD

SE5539 Open-Loop Phase vs Frequency

Gain Bandwidth Product vs Frequency
AV "" Xl0

I

I

3d88AjIOTH
~AV '" X7.S

L
3dB BAJWIlTH

,.I

'00,,",
fMEOUENCY' IN CYCLES PER SECOND

~

NOTE

October 10, 1986

:s

TA

:s

125°C

4-30

Vee
RL

--

FREOUENCY IN CYClES PER SECOND

Indicate. typical
distribution -55°C

"

~~

FREQUENCY IN CYCLES PER SECOND

,....

,......

''''''

=

~~

'00 ....

= !:6V150[1

Product Specification

Signetics Linear Products

NEjSE5539

Ultra-High Frequency Operational Amplifier

cal circuit layout is extremely critical. Breadboarding is not recommended. A doublesided copper-clad printed cirucit board will
result in more favorable system operation. An

CIRCUIT LAYOUT
CONSIDERATIONS
As may be expected for an ultra-high frequency, wide gain bandwidth amplifier, the physi-

example utilizing a 28dB non-inverting amp is
shown in Figure 1.

·F

OPTlOHAl
OFFSET
ADJ.
+Yo-~~-----o-y

·5

·4

.,

7S

•

V,.

.,
75

NOTES:
R, - 750 5% CARBON

Rs - 20k TRIMPOT (CERMEn
R, - 1.5k (28dB GAIN)
Ra ... 470&1 5% CARBON

R2 '" 750 5% CARBON
Ra .. 750 5% CARBON
R4 - 3Sk 5% CARBON

Top Plane Copper1
(Component Side)

-v

.,.

§

••

Yj

00.

.0 0

I
NE55J9

w/comp.

_0

'I

0
0

•

Vo

·3
•

Vo

NOTES:
(X) indicates ground connection to top plane.

oRa is on bottom side.
NOTE:
Bond edges of top and bottom ground plane copper.

Figure 1. 28dB Non-Inverting Amp Sample PC Layout

October 10, 1986

Bottom Plane
Copper1

+V

.Ib

..

Component Side
(Component Layout)

Qx)

00.

eo

RFC 3T # 26 BUSSWIRE ON
FERROXCUBE VK 200 09/3B CORE
BYPASS CAPACITORS
lnF CERAMIC
(MEPCO OR EOUIV.)

4-31

........

Signetlcs Linear Products

Product Specification

Ultra-High Frequency Operational Amplifier

NE5539 COLOR VIDEO
AMPLIFIER
The NE5539 wideband operational amplifier
is easily adapted for use as a color video
amplifier. A typical circuit is shown in Figure 2
along with vector-scope 1 photographs showing the amplifier differential gain and phase
response to a standard five-step modulated
staircase linearity signal (Figures 3, 4 and 5).
As can be seen in Figure 4, the gain varies
less than 0.5% from the bottom to the top of
the staircase. The maximum differential
phase shown in Figure 5 is approximately
+0.1°.

NE/SE5539

'5.
75

+v

'*

22nF

.70

The amplifier circuit was optimized for a 75n
input and output termination impedance with
a gain of approximately 10 (20dB).

75

-v

NOTE:
1. The input signal was 200mV and the output 2V.
Vcc was ±8V.

Figure 2. NE5539 Video Amplifier

Figure 4. Differential Gain < 0.5%

Figure 3. Input Signal
NOTE:

1. Instruments used for these measurements were Tektronix, 146 NTSC test signal generator, 520A NTSC vectorscope, and 1480 waveform monitor.

October 10, 1986

4-32

Signetlcs linear Products

Product Specification

NEjSE5539

Ultra-High Frequency Operational Amplifier

PHASE
ERROR

Figure 5. Differential Phase + 0.1 0

APPLICATIONS
+8V

ZIN

=50n -+-'Nv---1.,-.--'-!
470

118

+- Zo = sou

~,,--+---'\M~......

87

lK

2K

<=

1.5pF

Figure 6. Non-Inverting Follower

+8V

3.3pF

Figure 7. Inverting Follower

October 10, 1986

4-33

AN140

Signetics

Compensation Techniques for
Use With the NEjSE5539
Application Note

Linear Products

NE5539 DESCRIPTION
The Signetics SE/NE5539 ultra-high frequency operational amplifier is one of the fastest
monolithic amplifiers made today. With a unity
gain bandwidth of 350MHz and a slew rate of
600V / MS, it is second to none. Therefore, it is
understandable that to attain this speed,
standard internal compensation would have
to be left out of its design. As a consequence,
the op amp is not unconditionally stable for all
closed-loop gains and must be externally
compensated for gains below 17dB. Properly
done, compensation need not limit slew rate.
The following will explain how to use the
methods available with the SEINE5539.

LEAD AND LAG-LEAD
COMPENSATION
A useful method for compensating the device
for closed-loop gains below seven is to use
lag-lead and lead networks as shown in
Figure 1. The lead network is primarily concerned with compensating for loss of phase
margin caused by distributed board capacitance and input capacitance, while lag-lead is
mainly for optimizing transient response.
Lead compensation modifies the feedback
network and adds a zero to the overall
transfer function. This increases the phase,
but does not greatly change the gain magnitude. This zero improves the phase margin.
To determine components, it can be shown
that the optimal conditions for amplifier stability occur when:

However, when the stability criteria is obtained, it should be noted that the actual
bandwidth of the closed-loop amplifier will be
reduced. Based on using a double-sided copper-clad printed circuit board with a distribut~
ed capacitance of 3.5pF and a unity gain
configuration, CLEAD would be 3.5pF. Another
way of stating the relationship between the
distributed capacitance closed-loop gain and
the lead compensation capacitor is:
R1
CLEAD = CDIST-

COIST

r

RF

--11--

When bandwidth is of primary concern, the
lead compensation will usually be adequate.
For closed-loop gains less than seven, laglead compensation is necessary for stability.
If transient response is also a factor in design,
a lag-lead compensation network may be
necessary (Reference Figure 1). For practical
applications, the following equations can be
used to determine proper lag-lead components:

*

r
':'

1T(GBW)

= - - 5 - Rad/Sec

(7)

where
(8)

therefore,
1T(GBW) =

1

(9)

(RLAG)(CLAG)

5
and

(10)

LAG-LEAD
COMPENSATION
WILL CONTROL
GAIN PEAKING

O·~~P~H~AS~E~~-~-~

-~. r--~~-~~~~~

(5)

-180· r-----~-"'~-\--~

Using the above equation will insure a closedloop gain of seven above the network break

70MHz

a_ Closed-Loop Inverting Gain of
Seven Gain-Phase Response
(Uncompensated)
CF

I

CDIST

LEAD

r -

-If--

O·

-40

RF

•

-80

",,",COMPENSATED

-120
-180
VOUT

VOUT

-'""

VON

76r---

-240
NON·INVERTING

-280
1MHz

10MHz

100MHz

NOTES:
CL = CLAG
RL'" RLAG

b. Open-Loop Phase
Figure 1_ Standard Lag-Lead Compensation

February 1987

4-34

"

~UNCOMPENSATED\---l

-200

INVERTING

(6)

GAIN

Therefore,

*

LAG LEAD RLL

WLAG

(4)

R1

VON

21T(GBW)
WLAG ~ --1-0- Rad/Sec

(2)

RF

(1)

CLEAD

frequency. CLAG may now be approximated
using:

Figure 2

1GHz

Application Note

Signetics Linear Products

AN140

Compensation Techniques for Use With the NEjSE5539

This method adds a pole and zero to the
transfer function of the device, causing the
actual open-loop gain and phase curve to be
reshaped, thus creating a progressive improvement above the critical frequency where
phase changes rapidly. (Near 70MHz, see
Figures 2a and 2b.) But also, the lag-lead
network can be adjusted to optimize gain
peaking for transient responses. Therefore,
rise time, overshoot, and settling time can be
changed for various closed-loop gains. The
result of using this technique is shown for a
pulse amplifier in Figure 3.

SMALL SIGNAL RESPONSE

OUTPUT
200mV
p.p
INPUT
100mV
p.p

l00mVlOIV
10nolOlV

Figure 3. Compensated Pulse Response

cc

cc

V,N o--'lM~+--I
VOUT

VOUT

V,N 0------4'"'-1
NON·INVERTING

INVERTING

Figure 4. Pin 12 Compensation

2K

2K

NON·INVERTING

INVERTING

Figure 5. Pulse Response Test Circuits

February 1987

4-35

Signetics Linear Products

Application Note

Compensation Techniques for Use With the NEjSE5539

CRITICALLY DAMPED

Co, can be added in series with the resistor
(Rd across the inputs. This should be a large
value to block DC but not affect the benefits
of the compensation components at high
frequencies. A value of 0.011lF as shown in
Figure 8 is sufficient.

UNDER DAMPED

INPUT

AN140

10CmVlDIV

INTERNAL CHARACTERISTICS
OF THE NE/SE5539
OUTPUT

In order to better understand the compensation procedure, a detailed discussion of the
amplifier follows.

10nsJDIV

RISE TIME -

RISE TIME - 2.4ns
Rc = 11SU-Cc=4.6pF
PROPAGATION DELAY .. 2.3ns

The complete amplifier schematic is shown in
Figure 9. To clarify the effect of the compensation pin, the schematic is split into five main
parts as shown in Figure 10.

2.1 ns

Rc .. 2OO Cc=5.4pF
PROPAGATION DELAY = 2,3ns

(0)

(b)

Figure 6. Small Signal Response - Non-Inverting

CRITICALLY DAMPED

UNDER DAMPED

INPUT
OUTPUT

10CmV/DIV

Each segment in Figure 10 is defined as
follows: starting from the non-inverting input,
Section A1 is the amplification from the input
to the base of transistor 04. A2 is from the
base of 04 to the summation point at the
collector of 03. Furthermore, A3 represents
the gain from the non-inverting input to the
summation point via the common emitter side
of 02 and 03' Finally, BF is the feedback
factor of the positive feedback loop from the
collector of 03 to the base of 04'
From Figure 10, it can be seen that the total
gain (AT) is:
A1 A2

10nsiDIV

AT
RISE TIME - 5.3n8

RISE TIME - 3.3n8

Rc = 226U - Cc = 2.3pF

Rc - 460 - Co = 2.0pF

PROPAGATION DELAY.,. 5.1n8

PROPAGATION DELAY = 4.5ns

(0)

(b)

Figure 7. Small Signal Response - Inverting

USING PIN 12 COMPENSATION
An alternate method of external compensation is obtained by use of the SE/NE5539
frequency compensation pin. The circuits in
Figure 4 show the correct way to use this pin.
As can be seen, this method saves the use of
one capacitor as compared to standard laglead and lead compensation as shown in
Figure 1.
But, most importantly, both methods are
equally effective; i.e., a good wide-band amplifier below 17dB, with control over ringing
and overshoot. For example, inverting and
non-inverting amplifier circuits using Pin 12
are shown in Figure 5. The corresponding
pulse response for each circuit is shown in
Figures 6 and 7 for the network values
recommended. As shown by the response
photos, the overshoot and settling time can
be controlled by adjusting Rc and Cc. In
damping the overshoot, rise time is slightly

February 1987

decreased. Also, the non-inverting configuration (Figure 6) gives a very fast response time
compared to the inverting mode.

Cc

Figure 8. Co Will Reduce Output
Offset and Noise
If it is important to reduce output offset
voltage and noise, an additional capacitor,

4-36

= 1 _ (BF A2)+A3 (1 + BFA2)

Each term in this equation plays a role at
different frequencies to determine the total
transfer function of the device. Of particular
importance is the pole in A3 (near 340MHz)
which causes a roll-off of 12dB/octave and
loss of phase margin just before unity gain.
This can be seen in the Bode plot in Figure
11a. To overcome this pole, a capacitor and
resistor are connected as shown in Figures
12a and 12b. The compensation pin is connected to the emitter of 05, which is in an
emitter-follower configuration. Therefore, a
reactance connected to Pin 12 acts essentially as if it were connected at the base of 05'
Since the capacitor is connected here, it is
now a component of BF and a zero is added
to the transfer function. The resistor across
the input pins controls overall gain and causes AT to cross OdB at a lower frequency; the
capacitor in the feedback loop controls phase
shift and gain peaking.
To further explain, Bode plots 01 open-loop
response using varying capaCitor values and
corresponding pulse responses are shown in
Figures 13a through 131. The changes in gain
and phase can readily be seen, as is the
effect on bandwidth.

Signetics Linear Products

Application Note

Compensation Techniques for Use With the NE/SE5539

AN140

COMPENSATION

10K

lK

820

lK

r1.5K
3.3K

1.8K

Vas

-IN
+IN 0--

H(O
l

~r*4 okJ I "--

~o,
10K

5.9K

V010

H'
3.2K UK

UK

5.6K

100

--

o.
0--0 OUT

10K

10K

10K

2.2K

J-

t--;-

2.4K

......

o~

~07
~
~

~Oa
10K

1.15K

Figure 9. Complete Schematic of NE/SE5539

OUTPUT

Figure 10. Internal Sections

February 1987

4-37

Signetics Linear Products

Application Note

AN140

Compensation Techniques for Use Wjth the NEjSE5539

COMPUTER ANALYSIS
The open-loop and pulse response plots
were generated using an IBM 370 computer
and SPICE, a general-purpose circuit simulation program. Each transistor in the part is
mathematically modeled after actual device
parameters, which were measured in the
laboratory. These models are then combined
with the resistors and voltage sources
through node numbers so that the computer
knows where each is connected.

iD 55
:£
>
c

-

o·

------~--~--~------.+

OUTPUT

r--....

..........
OdS

-:-..

"'-

$

.,Cw
l:
0.

-

""""'180 0

"'

270 350

-l~

f(MHz)

Co

Rc

RI

ALTERNATE
LOWERS OFFSET

a. Open-Loop Gain - No
Compensation (Computer
Simulation)
a_ Pin 12 Compensation Showing Internal Connections -Inverting

I I
I I

-------.--~--...,...-----+

OUTPUT

11\

1
\

I

11\

II

It

U

II

J
INPUT

I
I
5nslOlV

OUTPUT

b. Closed-Loop Non-Inverting
Response - No Compensation
(Computer SimulatlonOscillation is Evident)
Figure 11
To indicate the accuracy of this system, the
actual open-loop gain is compared to the
computer plots in Figures 14 and 15. The real
payoff for this system is that once a credible
simulation is achieved, any outside circuit can
be modeled around the op amp. This would
be used to check for feasibility before breadboarding in the lab. The internal circuit can be
treated like a black box and the outside circuit
program altered to whatever application the
user would like to examine.

February 1987

-l~Rc

RI

Co
ALTERNATE

LOWERS OFFSET

b. Pin 12 Compensation Showing Internal Connections - Non-Inverting
Figure 12

4-38

Signetics Linear Products

Application Note

AN140

Compensation Techniques for Use With the NEjSE5539

I I
I\.

46

...........

OUTPUT

44

~

..........
OdS

>

"'

I

............

~

r-.....

'"

INPUT

c

250350

c;;;>

O~TP~T
.........
'.'1

\i

Ii!

..........

r--

Ii\.

73'

INPUT

'\.

I

\
",\

~

7S

5nsJDIV

3S0
Sns/OIV

! (MHz)

d. Closed-Loop Non-Inverting Pulse
Response - Rc 200[2, Cc 2pF, Av 3
(Computer Simulation - Critically-Damped)

=

c. Open-Loop Pin 12 CompensatlonRc = 200[2, Cc = 2pF (Computer
Simulation)

,

!\

E

""'

"-

,sa 3sa

............. OdS

1\

INPUT

OdS

!(MHz)

b. Closed-Loop Non-Inverting Pulse
Response - Rc = 200[2, Cc = 1pF,
Av = 3 (Computer
Simulation - Underdamped)

43

...........

"'-

92'

5nsJDIV

!(MHz)

OUTPUT

k..

1

'40' "

a. Open-Loop Pin 12 CompensationRc = 200[2, Cc = 1pF,
(Computer Simulation)

-

=

=

e. Open-Loop Pin 12 CompensationRc = 200[2, Cc = 3pF,
(Computer Simulation)

f. Closed-Loop Non-Inverting Pulse
Response - Rc 200[2, Cc 3pF, Av 3
(Computer Simulation - Overdamped)

=

=

=

Figure 13

1. J. Millman and C. C. Halkias: Integrated
Electronics: Analog and Digital Circuits and
Systems. McGraw-Hili Book Company, New
York, 1972.

'20
'00
60

.."

60

m

SS

:!>

'"

........

"'

20

-20
1MHz

........

3sa
!(MHz)

10MHz

100MHz 350 1GHz

Figure 14. Actual Open-Loop Gain
Measured in Lab

February 19B7

2. A. Vladimirescu, Kaihe Zhang, A. R. Newton, D. O. Peterson, A. Sanquiovanni-Vincentelli: "Spice Version 2G," University of California, Berkeley, California, August 10, 1981.

>

t----

40

Figure 15. Computer-Generated
Open-Loop Gain

4-39

3. Signetics: Analog Data Manual 1983,
Signetics Corporation, Sunnyvale, California
19B3.

•

NE5592

Signetics

Video Amplifier
Product Specification

Linear Products

DESCRIPTION

FEATURES

The NE5592 is a dual monolithic, twostage, differential output, wideband video amplifier. It offers a fixed gain of 400
without external components and an
adjustable gain from 400 to 0 with one
external resistor. The input stage has
been designed so that with the addition
of a few external reactive elements between the gain select terminals, the
circuit can function as a high-pass, lowpass, or band-pass filter. This feature
makes the circuit ideal for use as a video
or pulse amplifier in communications,
magnetic memories, display, video recorder systems, and floppy disk head
amplifiers.

•
•
•
•

PIN CONFIGURATION

120MHz bandwidth
Adjustable gain from 0 to 400
Adjustable pass band
No frequency compensation
required
• Wave shaping with minimal
external components

D, N Packages

APPLICATIONS
• Floppy disk head amplifier
• Video amplifier
• Pulse amplifier in
communications
TOP VIEW

• Magnetic memory
• Video recorder systems

ORDERING INFORMATION
DESCRIPTION
14·Pin Plastic DIP
14·Pin SO package

TEMPERATURE RANGE

o to
o to

ORDER CODE

70'C

NE5592N

70'C

NE5592D

EQUIVALENT CIRCUIT
r---~----~----~~--~------~----~--~+V

t----t-::=;-::I--i------+---.....VVI....~--_t---<>

OUTPUT 1

INPUT 1
OUTPUT 2
G

0"

R,.
L-__~----~--------4-------~--~--_4--~

October 10, 1986

4-40

-v

853-0888 85933

Signetics Linear Products

Product Specification

NE5592

Video Amplifier

ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise specified.
SYMBOL

RATING

UNIT

Vcc

Supply voltage

PARAMETER

±8

V

VIN

Differential input voltage

±5

V

VCM

Common mode Input voltage

±6

V

lOUT

Output current

10

mA

TA

Operating temperature range
NE5592

TSTG

Storage temperature range

PD

Power dissipation

DC ELECTRICAL CHARACTERISTICS

o to

°C

+70

-65 to + 150

°C

500

mW

TA = + 25°C, Vss = ± 6V, VCM = 0, unless otherwise specified. Recommended
operating supply voltage is Vs = ± 6.0V, and gain select pins are connected together.
LIMITS

SYMBOL

PARAMETER

Differential voltage gain

UNITS

TEST CONDITIONS

RL

= 2kn,

VOUT

= 3Vp.p

Min

Typ

Max

400

480

600

3

14

VIV

RIN

Input resistance

CIN

Input capacitance

2.5

los

Input offset current

0.3

3

tJ.A

ISlAS

Input bias current

5

20

p.A

Input noise voltage
VIN

Common-mode rejection ratio

PSRR

Supply voltage rejection ratio
Channel separation

Vos

Output offset voltage
gain select pins open

VCM

Output common-mode voltage

VOUT

Output differential voltage swing

ROUT

Output resistance

Icc

Power supply current
(total for both sides)

October 10, 1986

pF

4

nV/YHZ

60

93
87

dB
dB

50

85

dB

65

75

dB

BW 1kHz to 10MHz
± 1.0

Input voltage range

CMRR

kn

VCM ± IV, f < 100kHz
VCM ± IV, f = 5MHz

f!,vs

=

± 0.5V

VOUT = lVp_p; f = 100kHz
(output referenced) RL = 1kn

= 00
= 00
RL = 00
RL = 2kn

RL
RL

RL

4-41

= 00

V

0.5
0.25

1.5
0.75

V
V

2.4

3.1

3.4

V

3.0

4.0

V

20

n

35

44

mA

Product 'Specification

Signetics Linear Products

NE5592

Video Amplifier

DC ELECTRICAL CHARACTERISTICS

Vss = ± 6V, VCM = 0, O'C";; TA ..;; 70'C, unless otherwise specified. Recommended
operating supply voltage is Vs = ± 6.0V, and gain select pins are connected together.
LIMITS

SYMBOL

PARAMETER

Differential voltage gain

UNITS

TEST CONDITIONS

RL = 2kn, VOUT = 3Vp_p

Min

Typ

Max

350

430

600

1

11

V/V

RIN

Input resistance

los

Input offset current

5

/1 A

IBIAS

Input bias current

30

I1A

VIN

Input voltage range

CMRR

Common-mode rejection ratio

PSRR

Supply voltage rejection ratio
Channel separation

Vos

Output offset voltage
gain select pins connected
together
gain select pins open

VOUT

Output differential voltage swing

Icc

Power supply current
(total lor both sides)

AC ELECTRICAL CHARACTERISTICS

kn

± 1.0

V

VCM ± tv, I < 100kHz
Rs= rJ>

55

dB

tlVs = ± 0.5V

50

dB

VOUT = tv p.p; I = 100kHz
(output relerenced) RL = 1kn
RL =

00

RL =

00

RL = 2kn
RL =

75

dB

1.5

V

t.O

V

2.8

V
47

00

mA

TA = + 25'C, Vss = ± 6V, VCM = 0, unless otherwise specilied. Recommended
operating supply voltage Vs = ± 6.0V. Gain select pins connected together.
LIMITS

PARAMETER

SYMBOL

TEST CONDITIONS

UNITS
Min

BW

Bandwidth

tR

Rise time

tpD

Propagation delay

October 10, 1986

VOUT = lVp.p

Typ

Max

25

20

MHz

12

ns

15
VOUT = lVp.p

4-42

7.5

ns

Signetics Linear Products

Product Specification

Video Amplifier

NE5592

TYPICAL PERFORMANCE CHARACTERISTICS
Common-Mode Rejection Ratio
as a Function of Frequency

tJ

Output Voltage Swing as a
Function of Frequency

Channel Separation as a
Function of Frequency

100 r-r-T"TTT""'-"'-nT....,.....,..,...,.,

..~

20

90

Rl '"' 1 kO:

80

.

a:

z

70

~

0

w

15

~

50

;;!

a:
w 40

,.
z
,.,.
0

~

= :t6V
TA = 25"C
Rs = 0
VIN = 2V P"P

10

0
10'

0
0

l/

Vs

20

0

10

Q

30

0

osc TO (5SE

~

10'
10'
FREQUENCY - Hz

I--

10'
10

20

15

FREQUENCY - Hz

Differential Overdrive
Recovery Time

Pulse Response as a
Function of Temperature

Pulse Response as a
Function of Supply Voltage

0

¥: ~ i5~~-

5

~ 40
>= 5

i

~
~

5

a:

20

~Q

15

~

w

10
50

40

= 25 C+-++'v!;:.-=:!--:;.:-!;a"'v4
1.21-t--I-+--+-+-+:;ooOo"'~""I
Vs = t6V

-- -- -- -- - 7 - --1-·1··

0.8

~~ O.4J0.6t-:::1=1=t:J'V::;~~~!.v~s~~=:~.±3I.~v

/
i;""

"

5

0.21--1-+--1,..,11.r--.-.t-.-_f-.-.+.-_-+-_--1.,_--1_

>

120

160

Vs

=

RL.

= 1kO

t6V

I

1

0.6

~
....

0.4
0.2

=

TA

0.8

ooc
~

TA

=25OC_

I I I

TA = 7OOC-

I
1--

5

-0.2
-0.4
-15-10-5

5 10 15 202530 35
TIME - ns

200

1.2

~g

O~~~-+_+~~~~
-15-10-5 0

80

1.6
1.4

:

0

1.4I-TA

~

0

r--~L J ,~

1.6

+++-

~.I-.

0

I

5 10 15 2025 3035
TIME· ns

DIFFERENTIAL INPUT VOLTAGE· mV

Voltage Gain as a
Function of Temperature

.

..

1.

v. l = .I.v-

At.

= 1kO"-

f - 1MHz -

~

0.8
0.4

~

60

•

1.2

LI.l

Gain vs Frequency as a
Function of Temperature

.."

.
i!:

Vs

RL

'iii

"w

TA

~ -0.4

-TA =

~

Q

-ITAIIII70~

.......

-1.6

> 20

o

10

20 30 40 50
TEMPERATURE: "C

60

70

10

10'

I
10 6

I

.."

= 100kHz
= 250C

F
TA

/

""

250C

/

1.1

I II
I II
107

"

1

= OOC

~ 30

i ~:::

= ±6V~

= 11eO

50
40

Voltage Gain as a
Function of Supply Voltage

I
108

FREQUENCY" Hz

7

SUPPLY VOLTAGE" V

October 10, 1986

4-43

Signetics Linear Products

Product Specification

Video Amplifier

NE5592

TYPICAL PERFORMANCE CHARACTERISTICS
Gain vs Frequency as a
Function of Supply Voltage
60

11111

v.

= ±BV

v.

= ±6V
= ±3Y

Vs

(Continued)

= 25'C
= lkfl

T.
RL

TA = 250C

......

AL = 1kO

I:
Ii;

~

"

~120

107

106

-~

=

210

'\

1111 I I
108

10·

10- 1
1

102

10

Supply Current as a
Function of Supply Voltage
50

.....

~

~

~

I'

3

105

10'

Output Voltage Swing and Sink
Current as a Function of Supply
Voltage

T. = 25'C

Vs = :t6V

~ 40

104

103

RADJ.· OHMS

FREQUENCY· Hz

Supply Current as a
Function of Temperature
5

JI
107

10 6

'\

1

= ±3V

IrVs

1.'

FREQUENCY· Hz

=- :l,:6V

10

Vs
:t8Y
Vs = :t6V

240

108

= 250C

.'\..

1\

90

w 150

..

TA
Vs

102

~180

10
10'

Voltage Gain as a
Function of RADJ

Phase vs Frequency as a
Function of Supply Voltage

TA

dtf

..

~9' i.~"'- -

~ f:>'>~'I'

3

L

..,

= 25'C

5

~

2/
1

32

o

10

20

30

40

50

60

o

70

TEMPERATURE - "C

Output Voltage Swing as a
Function of Load Resistance
Vs
TA

-

= :t:8V
= 250(:

Input Resistance as a
Function of Temperature
GAIN 1
Vs

w 20
z

.....
...

I

10 1

1()2
103
LOAD RESISTANCE· OHMS

= ±6V

./

Y;l

w
a:

104

./

15

V

::>

i!i

•

10

010203040506070
TEMPERATURE· 'C

October 10, 1966

Input Noise Voltage as a
Function of Frequency

II

J

1

SUPPLY VOLTAG~· ±V

25

0

!

3

SUPPLY VOLTAGE· ±V

4-44

t:t::t;t:t;:t:t;::t=t;:D

1
1

102

10"

10'

FREQUENCY· Hz

10'

101<1

Product Specification

Signetics Linear Products

NE5592

Video Amplifier

TEST CIRCUITS TA = 25°C, unless otherwise specified.

O.2",F

V,.
51

October 10, 1986

4-45

51

Radj

lK

lK

NE/SE592

Signetics

Video Amplifier
Product Specification

Linear Products
DESCRIPTION

FEATURES

The NE/SE592 is a monolithic, twostage, differential output, wideband video amplifier. It offers fixed gains of 100
and 400 without external components
and adjustable gains from 400 to 0 with
one external resistor. The input stage
has been designed so that with the
addition of a few external reactive elements between the gain select terminals, the circuit can function as a highpass, low-pass, or band-pass filter. This
feature makes the circuit ideal for use as
a video or pulse amplifier in communications, magnetic memories, display, video
recorder systems, and floppy disk head
amplifiers. Now available in an a-pin
version with fixed gain of 400 without
external components and adjustable
gain from 400 to 0 with one external
resistor.

•
•
•
•

PIN CONFIGURATIONS

120MHz bandwidth
Adjustable gains from 0 to 400
Adjustable pass band
No frequency compensation
required
• Wave shaping with minimal
external components

0, F, N Packages
INPUT 2

INPUT 1

1

HC

11

G2A GAIN
SELECT
G1A GAIN
SELECT

APPLICATIONS

V·

• Floppy disk head amplifier
• Video amplifier
• Pulse amplifier in
communications
• Magnetic memory
• Video recorder systems

OUTPUT 2

7

TOP VIEW

H Package"
G,. GAIN SELECT

v+

INPUT 2
G28 GAIN
SELECT

EQUIVALENT CIRCUIT
r---~------~-----'----~-------1------~-O.V

VNOTES:
Pin 5 connected to case.
*Metal cans (H) not recommended for new designs.

008

D, F, N, Packages

~---1--~~~4-------~----+-~~~----+-~OUTPUT1
INPUT 1
OUTPUT 2

G,.

INPUT 2

G1B GAIN
SELECT

v-

2"

3

OUTPUT 2 4

7

INPUT 1
G1A GAIN
SELECT

6

V+

5 OUTPUT 1
TOP VIEW

L---~----4-------~----------~--~-o-V

November 6, 1986

4-46

853-0911 86387

Product Specification

Signetlcs Linear Products

NEjSE592

Video Amplifier

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

o to
o to

14-Pin Plastic DIP
14-Pin Cerdip
14-Pin Cerdip

ORDER CODE

+70°C

NE592N14

+70°C

NE592F14

-55°C to +125°C

o to
o to

14-Pin SO
6-Pin Plastic Dip
6-Pin Cerdip

SE592F14

+70°C

NE592D14

+70°C

NE592N6

-55°C to +125°C

o to
o to

6-Pin SO
10-Lead metal can
10-Lead metal can

SE592F6

+70°C

NE592D6

+70°C

NE592H

-55°C to + 125°C

SE592H

NOTE:

Also N8, N14, D8 and D14 package parts available in "High" gain version by adding "H" before package
designation, as: NE592HD8.

ABSOLUTE MAXIMUM RATINGS TA = + 25°C, unless otherwise specified.
SYMBOL

RATING

UNIT

Supply voltage

±6

V

VIN

Differential input voltage

±5

V

VCM

Common-mode input voltage

±6

V

lOUT

Output current

10

mA

TA

Operating temperature range
SE592
NE592

-55 to + 125
o to +70

·C
°C

TSTG

Storage temperature range

-65 to +150

°C

PD

Power dissipation

500

mW

Vce

PARAMETER

November 6, 1966

4-47

•

Signetics Linear Products

Product Specification

NEjSE592

Video Amplifier

DC ELECTRICAL CHARACTERISTICS T A = + 25°C, Vss = ± 6V, VCM = 0, unless otherwise specified. Recommended
operating supply voltages Vs = ± 6.0V. All specifications apply to both standard and
high gain parts unless noted differently.
SE592

NE592
SYMBOL

AVOL

PARAMETER

Differential voltage gain,
standard part
Gain 11
Gain 22 .4

RL

= 2kn,

VOUT

= 3Vp.p

High gain part
RIN

Input resistance
Gain 11
Gain 22.4

CIN

Input capacitance2

los

Input offset current

IBIAS

Input bias current

VNOISE

Input noise voltage

VIN

Input voltage range

CMRR

Common-mode rejection ratio
Gain 24
Gain 24

PSRR

Supply voltage rejection ratio
Gain 24

VOS

Output
Gain
Gain
Gain

offset voltage
1
24
33

VCM

Output common-mode voltage

VOUT

Output voltage swing
differential

ROUT

Output resistance

Icc

Power supply current

Min

Typ

Max

Min

Typ

Max

250
80

400
100

600
120

300
90

400
100

500
110

400

500

600

10

4.0
30

Gain 24

20

VCM± 1V, , < 100kHz
VCM± 1V, , = 5MHz
.,Vs

= ±0.5V

= 00

RL = 2kU

2.0

4-48

pF

0.4

3.0

9.0

30

9.0

20

12

JiA
JiA
JiVRMS

± 1.0

V

60

86
60

60

86
60

dB
dB

50

70

50

70

dB

0.35

1.5
1.5
0.75

2.4

2.9

3.4

3.0

4.0
20

RL = 00

kn
kn

5.0

12

RL = 00
RL = 00
RL = 00
RL

4.0
30

0.4

± 1.0

VIV
VIV
VIV

2.0

BW 1kHz to 10MHz

NOTES:
1. Gain select Pins G1A and G1B connected together.
2. Gain select Pins G2A and G2B connected together.
3. All gain select pins open.
4. Applies to 10- and 14-pin versions only.

November 6, 1986

UNIT

TEST CONDITIONS

18

0.35

1.5
1.0
0.75

2.4

2.9

3.4

3.0

4.0

18

V
V

20
24

V
V
V

n
24

rnA

Signetics Linear Products

Product Specification

Video Amplifier

NEjSE592

DC ELECTRICAL CHARACTERISTICS Vss=±6V, VCM=O, O'C&

"
~
w
"~

g
~

Vs
fay
TA as"c
RL:= lku

=

60

~

=
=

GAIN 2

Vs
±&V
TA" 2~C

Pulse Response

15

10

5

0

10

~

~

~

TIME-ns

Gain vs Frequency as a
Function of Temperature

Voltage Gain as a
Function of Supply Voltage

1.10

Vs = fay

VS" ±6V
RL lk!i
GAIN 2

50

z

1.08

~

1.04

~

1.02

"- ........
-..: lIo...

~ 1.00

~ 0.98

i

~ I--..

.....

0.96

0.92

0

....

"

November 6, 1986

.

........

20

30

40

50

1\

"
"

-'" ~ -

0.94

0.90

''!o,. -

70

-10 ,

,...

1.'
1.0

30

~

TA = as"C

=

1.08

0.9

"

100

50
FREQUENeY-MHl

4-50

Til."
125°e
500 1000

/'

~-

J~

0.7

0.'
0.'

,-

-1

0.8
A=: ssoe
III
A" 25"e

5

.",~~

)If

V

I
I

,

8

SUPPLY VOLTAGE- ±V

"--

~

Product Specification

Signetics Linear Products

NEjSE592

Video Amplifier

TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Gain vs Frequency
as a Function of
Supply Voltage

Voltage Gain as a
Function of RADJ (Figure 3)

Voltage Gain
Adjust Circuit
GAIN 2

" f-+-Iftt---1f-Htt-t- ~~: ~~c

1-4

9 cr-- o.2"F
1!1"r-r-+-H,,--T---O

Vs - __:r6V

~~ ~O:5ko~l;

.

• 1 592

rir:

1000

FIGURE 3

L'---1f-"H"-'+-~-o

4

"

\

I"\,
10

\

-10

R••

t-+t-t+-t-t-H+-H"\P.7'';-;;;;i
\1 Vs- faY
Vs= f6Y

'--Vs = ±6V

-'..J-J"!5~'~0-l...U,5t;0"",;!;00;-'..J-J~5OO~10'OO

,

TA = 25°C

!-,

lK

FREQUENCY-MHz

10K

100K

1M

I

RADJ-fl

Supply Current as a
Function of Temperature

Supply Current as a
Function of Supply Voltage
28

V~" ),v

T A '" 25°C

Output Voltage and Current
Swing as a Function of
Supply Voltage
'.0
TA" 25°C

'.0

-

18

, ./

"

i"-

16

.

V
'.0

./

r-....

V

V

~

3.0

~~
?

20

20

60

100

140

TEMPERATURE-oC

.

./
5

3

3.0

•

Input Resistance
as a Function of
Temperature

~

'.0

0

5.0

0

'.0

0

.

./

~

~

o"';;0-'-'-~50;-;C1O~0.L.l-\,,\;00~,,,-JLLl,,!:-.-:!,,,
LOAD RESISTANCE-I!

November 6, 1986

6.0

tv

7.0

'.0

GAIN 2

r1~r;-t~~-tHt~!~:J6

'0r1~r;-t~~-tHt~·W~·;'~0~MFH'1
70

r1~r;-t~~-tHt+-H*-I

//

30

0

5.0

Input Noise Voltage
as a Function of
Source Resistance

V

0

;

g

4.0

SUPPLY VOLTAGE_

SUPPL.Y VOlTAGE- tV

GAIN 2
Vs" t6V

I

Vc\)~'"

'.0

0

~

.

£~, i-"

~V

12

Output Voltage Swing
as a Function of
Load Resistance

>~

~

/

/

10

. . . .V

-

-

o

0!-,~~~1O~~~~UL~,~.~~~,,,
20

"

TEMPERATURE_oC

4-51

SOURCE AESISTANCE-Il

•

Signetics Linear Products

Product Specification

NEjSE592

Video Amplifier

TYPICAL PERFORMANCE CHARACTERISTICS (Continued)

TEST CIRCUITS TA = 25'C, unless
otherwise specified.

Phase Shift as a
Function of. Frequency

'I'
-,

,

~

GAIN 2

~:~ ;5~~

"

-so

-150

r-...

~! ~ :5~~

~
«

-100

-10

~

""" "

-20

510

~

-'00

-15

-25

Phase Shift as a
Function of Frequency

\

-250

~

-300

,

1

,

, •

3

• •

4
7
FREQUENCY-MHI

li

-350

100
10
FREOUENCY-MHz

1

10

OPQ4600S

~!: :s~6

so

Vs -

"

RL" lKO

GAIN 1

OP04610S

Voltage Gain as a
Function of Frequency
(All Gain Select Pins Open)

Voltage Gain as a
Function of Frequency

"

1000

±6V

TA" 25°C
GAIN 3

30

...........

"

20

GAIN 2

10

30

~

20

1\

10

1

10

100

V

-20

~

0

V~

0

-10

'\

1000

~::~

."

\

V
.1

1

10

100

1000

FREQUENCY-MHz

OP04630S

OP04620S

November 6, 1986

1\

/

-30

FREQUENCY-MHz

/

4-52

'to

510

Signetics Linear Products

Product Specification

NEjSE592

Video Amplifier

TYPICAL APPLICATIONS

.,
v,

-,
NOTE:

vo(s)

V,(s)

1.4 X 10 4

"'--Z(s) + 2re

1.4 X 104

"'--Z(s) + 32

Basic Configuration

..

.,
0.2"F

T

Vo

AMPLITUDI!:

'''EQUENCY:

41 pFd

R!AD HlAD

I

-,

OI1F!RI!NTIATOA/AMPlI:e"

-,
Z!RO CAOHINQ DETECTOR

T

NOTE:
For frequency F1 «1,1211" (32) C
dVi
Vo == 1.4 X 104CdT"

Disc/Tape Phase-Modulated Readback Systems

November 6, 1986

4-53

Differentiation With High
Common-Mode Noise Rejection

Signetics Linear Products

Product Specification

NEjSE592

Video Amplifier

FILTER NETWORKS
FILTER
TYPE

ZNETWORK
A

A

0

Y.JIw

A

1.4 x 10'
--L

HIGH PASS

~[_s
]
R
s + l/RC

C

11--0
c

L

~~

G+l~LJ

LOW PASS

L

~

Vo Is) TRANSFER
V, Is) FUNCTION

J

BAND PASS

1.4 x 10'[
s
L
52 + R/L s + l/LC

BAND REJECT

1.4Xl0 4 [
52+1/LC
]
R
52 + l/LC + s/RC

L

~
NOTE:

In the networks above, the R value used is assumed to include 2re, or approximately 320.

November 6, 1986

4-54

Signetics

AN141
Using the NEjSE592 Video
Amplifier
Application Note

Linear Products

VIDEO AMPLIFIER PRODUCTS

Table 1. Video Amplifier Comparison File

NE/SE592 Video Amplifier
The 592 is a two-stage differential output,
wide-band video amplifier with voltage gains
as high as 400 and bandwidths up to
120MHz.
Three basic gain options are provided. Fixed
gains of 400 and 100 result from shorting
together gain select pins G1A - G18 and
G2A - G2 8, respectively. As shown by Figure
1, the emitter circuits of the differential pair
return through independent current sources.
This topology allows no gain in the input
stage if all gain select pins are left open.
Thus, the third gain option of tying an external
resistance across the gain select pins allows
the user to select any desired gain from 0 to
400V IV. The advantages of this configuration
will be covered in greater detail under the
filter application section.

PARAMETER

NE/SE592

Bandwidth (MHz)

120

120

Gain

0,100,400

10,100,400

RIN (k)

4-30

4-250

Vp_p (Vs)

4.0

4.0

2. Subtract the maximum 592 output offset
(from the data sheet). This gives the output
offset allowed as a function of input offset
currents (1.5V - 1.0V = 0.5V).
3. Divide by the circuit gain (assume 100).
This refers the output offset to the input.

4. The maximum input resistor size is:
RMAX

=

Input Offset Voltage
Max Input Offset Current

Three factors should be pointed out at this
time:

0.005V

1. The gains specified are differential. Singleended gains are one· half the stated value.

= 1.00kn

2. The circuit 3dB bandwidths are a function
of and are inversely proportional to the gain
settings.
3. The differential input impedance is an inverse function of the gain setting.
In applications where the signal source is a
transformer or magnetic transducer, the input
bias current required by the 592 may be
passed directly through the source to ground.
Where capacitive coupling is to be used, the
base inputs must be returned to ground
through a resistor to provide a DC path for the
bias current.
Due to offset currents, the selection of the
input bias resistors is a compromise. To
reduce the loading on the source, the resistors should be large, but to minimize the
output DC offset, they should be
small- ideally on. Their maximum value is
set by the maximum allowable output offset
and may be determined as follows:
1. Define the allowable output offset (assume
1.5V).

February 1987

(1)

733

Filters
As mentioned earlier, the emitter circuit of the
NE592 includes two current sources.
Since the stage gain is calculated by dividing
the collector load impedance by the emitter
impedance, the high impedance contributed
by the current sources causes the stage gain
to be zero with all gain select pins open. As
shown by the gain vs. frequency graph of
Figure 3, the overall gain at low frequencies is
a negative 48dB.
Higher frequencies cause higher gain due to
distributed parasitic capacitive reactance.
This reactance in the first stage emitter circuit
causes increasing stage gain until at 10MHz
the gain is OdB, or unity.

5pA

Of paramount importance during the design
of the NE592 device was bandwidth. In a
monolithic device, this precludes the use of
PNP transistors and standard level·shifting
techniques used in lower frequency devices.
Thus, without the aid of level shifting, the
output common-mode voltage present on the
NE592 is typically 2.9V. Most applications,
therefore, require capacitive coupling to the
load. An exception to the rule is a differential
amplifier with an input common-mode range
greater than + 2.9V as shown in Figure 2. In
this circuit, the NE592 drives a NE511 B
transistor array connected as a differential
cascode amplifier. This amplifier is capable of
differential output voltages of 48V p.p with a
3dB bandwidth of approximately 10MHz (depending on the capacitive load). For optimum
operation, Rl is set for a no-signal level of
+ 18V. The emitter resistors, RE, were select·
ed to give the cascode amplifier a differential
gain of 10. The gain of the composite amplifier is adjusted at the gain selected pOint of the
NE592.

4·55

Referring to Figure 4, the impedance seen
looking across the emitter structure includes
small re of each transistor.
Any calculations of impedance networks
across the emitters then must include this
quantity. The collector current level is approx·
imately 2mA, causing the quantity of 2 re to
be approximately 32.11. Overall device gain is
thus given by
Vo(s)
V1N(S)

= 1.4 X
Z(5)

104

+ 32

(2)

where Z(5) can be resistance or a reactive
impedance. Table 2 summarizes the possible
configurations to produce low, high, and
bandpass filters. The emitter impedance is
made to vary as a function of frequency by
using capacitors or inductors to alter the
frequency response. Included also in Table 2
is the gain calculation to determine the voltage gain as a function of frequency.

Signetics Linear Products

Application Note

Using the NEjSE592 Video Amplifier

AN141

+30V

t-----------+~-ol OUTPUTS

I =~PEAK

INPUT o----jf-.o---_~~

v-

-6V

NOTE:

NOTE:
All resistor values are in ohms.

AU resistor values are in ohms.

Figure 2. Video Amplifier With High Level Differential Output

Figure 1. 592 Input Structure

Table 2. Filter Networks
VS' '8V
TA'2Ii C

/
-"

.-----

/

/

/

L

R

/""\

FILTER
TYPE

Z NETWORK

~

\

Vo(s) TRANSFER
V,(s) FUNCTION

LOW
PASS

----

HIGH
PASS

----

1.4 X 104
L

[s+

AF03770S

\

\

c

R

~I

0

1.4X104
R

[s +

AF03780S

~/L]
~/RC

]

"
Of>06330S

Figure 3. Voltage Gain as a Function
of Frequency (All Gain Select
Pins Open)

Differentiation
With the addition of a capacitor across the
gain select terminals, the NE592 becomes a
differentiator. The primary advantage of using
the emitter circuit to accomplish differentiation is the retention of the high common
mode noise rejection. Disc file playback systems rely heavily upon this common-mode
rejection for proper operation. Figure 5 shows
a differential amplifier configuration with
transfer function.

Disc File Decoding
In recovering data from disc or drum files,
several steps must be taken to precondition
February 1987

c
~I--<:>
AF03790S
R

L

~

BAND
PASS

----

BAND
REJECT

----

1.4 X 104
L

[s2 +

R/~

+ 1/LC ]

1.4 X 104 [
s2+1!LC
]
S2 + 1/LC + s/RC
R

AF03750S

NOTE: In the networks above, the R value used is assumed to include 2 reo or approximately 320.

the linear data. The NE592 video amplifier,
coupled with the 8T20 bidirectional one-shot,
provides all the Signal conditioning necessary
for phase-encoded data.
When data is recorded on a disc, drum or
tape system, the readback will be a Gaussian
shaped pulse with the peak of the pulse
corresponding to the actual recorded transi-

4-56

tion point. This readback signal is usually
500,.Np_p to 3mVp_p for oxide coated disc
files and 1 to 20mVp_p for nickel-cobalt disc
files. In order to accurately reproduce the
data stream originally written on the disc
memory, the time of peak point of the Gaussian readback Signal must be determined.

Signetics Linear Products

Application Note

AN141

Using the NE/SE592 Video Amplifier

<6

ed because the NE592 has no gain at DC due
to the capacitance across the gain select
terminals.

<6

02~

r"

v,

-6

The output of the first stage amplifier is
routed to a linear phase shift low-pass filter.
The filter is a single-stage constant K filter,
with a characteristic impedance of 200S1
Calculations for the filter are as follows:

vo

~r

L = 2F}wc

where
R = characteristic impedance (.12)

NOTE,
Vo(s)

1.4 x 104

-~---

V 1 (s)

Z(s)

+ 2re

C=1,!w c

NOTES,
For frequency F1 <

1.4 X 104

< 1/21r(32)C

Vo~1.4 X 104C~

Z(s) + 32

where

dT

We

All resistor values are in ohms.

Figure 4. Basic Gain Configuration
for NES92, N14

Figure S. Differential With High
Common-Mode Noise Rejection

The classical approach to peak time determination is to differentiate the input Signal.
Differentiation results in a voltage proportional to the slope of the input signal. The zerocrossing point of the differentiator, therefore,
will occur when the input signal is at a peak.
Using a zero-crossing detector and one-shot,
therefore, results in pulses occurring at the
input peak pOints.
A circuit which provides the preconditioning
described above is shown in Figure 6. Read-

back data is applied directly to the input of the
first NE592. This amplifier functions as a
wide-band AC-coupled amplifier with a gain of
100. The NE592 is excellent for this use
because of its high phase linearity, high gain
and ability to directly couple the unit with the
readback head. By direct coupling of readback head to amplifier, no matched terminating resistors are required and the excellent
common-mode rejection ratio of the amplifier
is preserved. DC components are also reject-

4mH
r--~---------------~~----~

= cut-off frequency (radians/sec)

The second NE592 is utilized as a low noise
differentiatorlamplifier stage. The NE592 is
excellent in this application because it allows
differentiation with excellent common-mode
noise rejection.
The output of the differentiator/amplifier is
connected to the 8T20 bidirectional monostable unit to provide the proper pulses at the
zero-crossing points of the differentiator.
The circuit in Figure 6 was tested with an
input signal approximating that of a read back
Signal. The results are shown in Figure 8.

L_ _-+_ _ _ _ _ ___Q<5V

4mH

r--1---------------4-.---frnn~--+_-~----__Q-5V
~.O'~F

8T20

CLR

Xl00AC
PRE·AMPLIFIER

LINEAR PHASE
LOW PASS FIt. TER

DIFFERENTIA TOR

BIOIRECTlONAl
ONE-SHOT

NOTE,
All resistor values are in ohms

Figure 6. SMHz Phase-Encoded Data Read Circuitry

February 1987

4-57

DIGITAL
OUTPUTS

Signetics Linear Products

Application Note

Using the NEjSE592 Video Amplifier

AN141

r---~-------'------~~--------O+6V

lK

2.7K
10pF

~
+

6

51

MC1496

51
12

I.

10

.IK

'.7K

56K

0.1

lK

-=

-=

lK
~--~----+-~~~~-----------4--------------------~-------o_6V
NOTE:
All resistor values are in ohms

Figure 7. Wlde·Band AGe Amplifier

Automatic Gain Control
The NE592 can also be connected in conjunction with a MC1496 balanced modulator
to form an excellent automatic gain control
system.
The signal is fed to the signal input of the
MC1496 and RC-coupled to the NE592. Unbalancing the carrier input of the MC1496
causes the signal to pass through unattenuated. Rectifying and filtering one of the NE592
outputs produces a DC signal which is proportional to the AC signal amplitude. After
filtering; this control signal is applied to the
MC1496 causing its gain to change.

February 1987

4·58

Signetics Linear Products

Application Note

Using the NE/SE592 Video Amplifier

,

,
~ ~ \.

V

,

J

V~

tv \. J

V

~

1\ 1\

I

II

V

I

U UI I""

~

r"\

" f'I

AN141

PRE·AMPLIFIER OUTPUT

lOOmV/DIV.

DtFFERENTIATOR
2OOmV/DIY.

:"""

TIME BASE 2OOno/DIV.

•

!
I
~

'J

,.

,

f.1'1
II U Q\J

~

f..I I
lHI

[J

"'V

PRE·AMP AND DIFFERENTIATOR
SUPER IMPOSED
BOTH 200mV IDlY.

TIME BASE200ns/DIY.

r

rf

I\t..

"rr

I J V \,01

.1 U V ~
y

I I I

I J I

IV

1 L L

•

1J

,...
DIFFERENTIATOR
2OOmV/DIV.

8T20 Q OUTPUT

2V/DIV.

TIME BASE 2OOM/DIV.

Figure 8. Test Results of Disc File Decoder Circuit

February 1987

4-59

MC1496/MC1596

Signetics

Balanced Modulator/
Demodulator
Product Specification
Linear Products

DESCRIPTION

FEATURES

The MC1496 is a monolithic doublebalanced modulator/demodulator designed for use where the output voltage
is a product of an input voltage (signal)
and a switched function (carrier). The
MC1596 will operate over the full military
temperature range of -55°C to + 125°C.
The MC1496 is intended for applications
within the range of O°C to + 70°C.

• Excellent carrier suppression
6SdB typ @ O.SMHz
SOdB typ @ 10MHz

PIN CONFIGURATION

• Adjustable gain and signal
handling
• Balanced inputs and outputs
• High common-mode rejectlon8SdB typ

F, N Packages

SlQN:~~T~~~

1

GAIN ADJUST 2
GAIN ADJUST 3

SIG::~~~~~

4

APPLICATIONS
• Suppressed carrier and amplitude
modulation
• Synchronous detection
• FM detection
• Phase detection

TOP VIEW

• Sampling
• Single sideband
• Frequency doubling

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

14-Pin Cerdip

010 + 70°C

MC1496F

14-Pin Plastic

o 10

MCI496N

+70'C

14-Pin Cerpip

-55'C 10 + 125'C

MC1596F

14-Pin Plastic

-55'C to + 125'C

MC1596N

EQUIVALENT SCHEMATIC

CARRIER (-)
INPUT(+)

O-,,'O'------1r-----1---'
8

SIGNAL(-) o.:.-----~
INPUT (+)
BIAS

y_

March 18, 1987

o!--------j;:::::::=_--J=~:g

GAIN
ADJUST

o-.:.-~.....,.---~-'---C

14

4-60

853-1201 88136

Signetics Linear Products

Product Specification

Balanced Modulator/Demodulator

MC1496/MC1596

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

RATING

UNIT

30

V

Va - VlO

Dilferential input signal

±5.0

V

V4 -V 1

Differential input signal

(5± Is Ra)

V

V2- Vl.
V3- V4

Input signal

5.0

V

Bias current

10

mA

1190
1420

mW
mW

Operating temperature range
MC1496
MC1596

to +70
-55 to + 125

°c
°c

Storage temperature range

-65 to + 150

°c

Applied voltage

Is
PD

TA

TSTG

Maximum power dissipation. TA = 25°C
(still-air)1
F package
N package

o

•

NOTE:
1. Derate above 25°C. at the following rates:
F package at 9.5mW
N package at II.4mWrC.

rc.

DC ELECTRICAL CHARACTERISTICS Vcc· + 12VDC; VCC--8.0VDC; Is-l.0mADC; RL=3.9kn; Re=I.0kn; TA=25°C,
unless otherwise specified.
MC1596
SYMBOL

PARAMETER

UNIT
Min

RIP
CIP

Single-ended input impedance
Parallel input resistance
Parallel input capacitance

Rap
Cop

Single-ended output impedance
Parallel output resistance
Parallel output capacitance

MC1496

TEST CONDITIONS
Typ

Max

Min

Typ

Max

Signal port. f = 5.0MHz
200
2.0

200
2.0

kn
pF

40
5.0

40
5.0

kn
pF

f = 10MHz

Input bias current

p.A

las

11 + 14
las=-2-

12

25

12

30

lac

la + 110
lac = - 2 -

12

25

12

30

liaS
IIOC

Input offset current
liaS = 11 -14
Iloe = la -110

0.7
0.7

5.0
5.0

0.7
0.7

7.0
7.0

TellO
100

p.A

Average temperature coefficient
of input offset current
Output offset current
16- 112

2.0
14

Va

Average temperature coefficient
of output offset current
Common-mode quiescent
output voltage (Pin 6 or Pin 12)

ID+
10-

Power supply current
16 + 112
114

2.0
3.0

PD

DC power dissipation

33

Teloo

March 18. 1987

p.A

2.0
50

15

90

90

8.0

8.0

IlA
nArC

80

p.A

nA/oC

VDe
mADe

4-61

3.0
4.0

2.0
3.0
33

4.0
5.0
mW

Signetlcs Linear Products

Product Specification

Balanced Modulator/Demodulafor

MC1496/MC1596

AC ELECTRICAL CHARACTERISTICS Vcc=+12oc; Vcc=-9.0Voc; Is=1.0mAoc; RL=3.9kn; RE=1.0kn; TA=+25°C,
unless otherwise specified.
MC1596
SYMBOL

PARAMETER

UNIT
Min

VeFT

Ves

BW3dB

Carrier feedthrough

Carrier suppressions

Transadmittance bandwidth
(Magnitude) (RL = SOn)

Avs

Signal gain

CMV
AeM

Common-mode input swing
Common-mode gain

DVOUT

Differential output voltage
swing capability

March 18, 1987

MC1496

TEST CONDITIONS

Ve = 60mVRMS sinewave and
offset adjusted to zero
Ie = 1.0kHz
Ie = 10MHz
Ve = 300mVp.p squarewave:
Offset adjusted to zero
fe = 100kHz
Offset not adjusted fe = 1.0kHz
Is = 10kHz, 300mVRMS sinewave
Ie = 500kHz, 60mVRMS sinewave
Ie = 10MHz, 60mV RMS sinewave

Signal port, Is = 100kHz
Signal port, Is = 1.0kHz
IVe I = 0.5Voe

4-62

Max

Min

40
140

50

Carrier input port,
Ve=60mVRMS
sinewave Is = 1.0kHz,
300mVRMS sinewave
Signal input port,
Vs = 300mVRMS
sinewave IVe I = 0.5Voe
Vs = 100mVRMS; 1= 1.0kHz
IVe 1= 0.5Voe

Typ

2.5

Typ

Max

40
140

"VRMS

0.04

0.2

0.04

0.4

20

100

20

200

65
50

65
50

dB

300

300

MHz

80

80

MHz

3.5

VIV

5.0
-85

5.0
-85

Vp_p
dB

8.0

8.0

Vp.p

3.5

40

mVRMS

2.5

Signetics Linear Products

Product Specification

Balanced Modulator/Demodulator

MC1496/MC1596

TEST CIRCUITS
10~F

10K

SOK
1000
10K

J:

lK

+8V

1"'

.01

r

+ 12VOC

~

1000

OUTPUT

Is INPUT

SOOPF

Ie INPUT

0
.01
-8VDC

":'

1.8K

Signal Gain and Output SwIng
Carrier Rejection and Suppression
+ 12VDC

3.9K

hO......-r-.+Vo
b:>---~-Vo

MODULATING
SIGNAL
10K
INPUT

n--Y~-,..,J

CARRIER NULL

-8VDC

Carrier Rejection and Suppression

March 18, 1987

4-63

•

AN189

Signetics

Balanced Modulator/
Demodulator Applications
Using the MC1496/MC1596
Linear Products

Application Note

age will be full wave multiplication of Ve and
Vs. Thus for sine wave signals, VOUT becomes:

BALANCED MODULATORI
DEMODULATOR APPLICATIONS
USING MC1496/MC1596
The MC1496 is a monolithic transistor array
arranged as a balanced modulator-demodulator. The device takes advantage of the excellent matching qualities of monolithic devices
to provide superior carrier and signal rejection. Carrier suppressions of 50dB at 10MHz
are typical with no external balancing networks required.

VOUT

= ExEy [CoS(wx + wy)t + cos( wx - wy)t ]
(1)

As seen by font = K (fc - fs) + K (fc + fs)
(see Figure 2), the output voltage will contain
the sum and difference frequencies of the two
original signals. In addition, with the carrier
input ports being driven into saturation, the
output will contain the odd harmonics of the
carrier signals.

Applications include AM and suppressed carrier modulators, AM and FM demodulators,
and phase detectors.

THEORY OF OPERATION
As Figure 1 suggests, the topography includes three differential amplifiers. Internal
connections are made such that the output
becomes a product of the two input signals
Ve and Vs.

BIASING
Since the MC1496 was intended for a multitude of different functions as well as a myriad
of supply voltages, the biasing techniques are
specified by the individual application. This
allows the user complete freedom to choose
gain, current levels, and power supplies. The
device can be operated with single-ended or
dual supplies.

To accomplish this the differential pairs
01 - 02 and 03 - 04, with their cross-coupled collectors, are driven into saturation by
the zero crossings of the carrier signal Ve.
With a low level signal, Vs driving the third
differential amplifier 05 - 06, the output volt-

VOI+l

Of primary interest in beginning the bias
circuitry design is relating available power
supplies and desired output voltages to device requirements with a minimum of external
components.
The transistors are connected in a cascode
fashion. Therefore, sufficient collector voltage
must be supplied to avoid saturation if linear
operation is to be achieved. Voltages greater
than 2V are sufficient in most applications.
Biasing is achieved with simple resistor divider networks as shown in Figure 3. This
configuration assumes the presence of symmetrical supplies. Explaining the DC biasing
technique is probably best accomplished by

03

VOH
9

•

Internally provided with the device are two
current sources driven by a temperaturecompensated bias network. Since the transistor geometries are the same and since VBE
matching in monolithic devices is excellent,
the currents through 07 and Oe will be
identical to the current set at Pin 5. Figures 2
and 3 illustrate typical biasing arrangements
from split and single-ended supplies, respectively.

°L

•

CARRIER H o - - - + - - - + - - . . . . . l

--+------1---'

1... ) 0 - - -.....

INPUT

SIGNAL

lNPUT

(+)O'------+-_...J

•

•,ASo-.....- .....--£=----1::

03
500

,.
v-o---......--<>--___

02
500

---J
NOTE:

All resistor values are in ohms
NOTE:
All resistor values are in ohms

Figure 2. Single-Supply Biasing

Figure 1. Balanced Modulator Schematic
February 1987

4-64

Signetics Linear Products

Application Note

Balanced Modulator/Demodulator Applications
Using the MC1496/MC1596
an example. Thus, the initial assumptions and
criteria are set forth:
1. Output swing greater than 4Vp_p.
2. Positive and negative supplies of 6V are
available.
3. Collector current is 2mA. It should be
noted here that the collector output current is equal to the current set in the
current sources.

AN189

~vo-------------.---------------,
I~K

1.SK

As a matter of convenience, the carrier signal
ports are referenced to ground. If desired, the
modulation signal ports could be ground referenced with slight changes in the bias arrangement. With the carrier inputs at DC
ground, the quiescent operating paint of the
outputs should be at one-half the total positive voltage or 3V for this case. Thus, a
collector load resistor is selected which drops
3V at 2mA or 1.5k~1 A quick check at this
point reveals that with these loads and current levels the peak-to-peak output swing will
be greater than 4V. It remains to set the
current source level and proper biasing of the
signal ports.

II

I

-

g

g

0

I-

I

Countless other bias arrangements can be
used with other power supply voltages. The
important thing to remember is that sufficient
DC voltage is applied to each bias point to
avoid collector saturation over the expected
signal wings.

BALANCED MODULATOR
In the primary application of balanced modulation, generation of double sideband sup-

+

...

::;

~

:i

I

!:+

r
FREOUENCY - - - - - - -.......

~
+

H~n

NOTES:
fe Carrier Fundemental
fs Modulating Signal
fe± fs Fundamental Carrier Sidebands
fe± nfs Fundamental Carrier Sideband Harmonics
nfe Carrier Harmonics
nfe± nfs Carrier Harmonic Sidebands

Figure 4. Modulator Frequency Spectrum
February 1987

4-65

pressed carrier modulation is accomplished.
Due to the balance of both modulation and
carrier inputs, the output, as mentioned, contains the sum and difference frequencies
while attenuating the fundamentals. Upper
and lower sideband Signals are the strongest
signals present with harmonic sidebands being of diminishing amplitudes as characterized by Figure 4.

Signetics Linear Products

Application Note

Balanced Modulator/Demodulator Applications
Using the MC1496/MC1596
Gain of the 1496 is set by including emitter
degeneration resistance located as RE in
Figure 5. Degeneration also allows the maximum signal level of the modulation to be
increased. In general, linear response defines
the maximum input signal as

AN189

,-""'.......,....-1>-----"",.....-----.-0 +12 Vdc

RL
3.91(

51

Vs .;; 15 • RE(Peak)

Vc
CARAIER

INPUT

and the gain is given by
RL
Avs=--RE + 2re

I-.....-+-o.vo

O.l .. F

o---j'I-.....- - - - - - - - l

MC1496

V,

.1---.....- 0 -vo

MODULATING
SIGNAL
INPUT

L....:i'-----"r--o
51

(2)

j
15

This approximation is good for high levels of
carrier Signals. Table 1 summarizes the gain
for different carrier signals.
As seen from Table 1, the output spectrum
suffers an amplitude increase of undesired
sideband signals when either the modulation
or carrier signals are high. Indeed, the modulation level can be increased if RE is increased without significant consequence.
However, large carrier signals cause odd
harmonic sidebands (Figure 4) to increase. At
the same time, due to imperfections of the
carrier waveforms and small imbalances of
the device, the second harmonic rejection will
be seriously degraded. Output filtering is often used with high carrier levels to remove all
but the desired sideband. The filter removes
unwanted Signals while the high carrier level
guards against amplitude variations and maximizes gain. Broadband modulators, without
benefit of filters, are implemented using low
carrier and modulation Signals to maximize
linearity and minimize spurious sidebands.

AM MODULATOR

6.8K

v'
-8Vdc

NOTE:

All resistor values are in ohms

Figure 5. Double Sideband Suppressed Carrier Modulator

Table 1. Voltage Gain and Output Spectrum vs Input Signal
CARRIER INPUT
SIGNAL (Ve)

APPROXIMATE
VOLTAGE GAIN

OUTPUT SIGNAL
FREQUENCY(S)

RLVC
Low-level DC

fM
2(RE + 2rE) (:T l

- RL
--

High-level DC

fM

R + 2re

RLVc(rms)
Low-level AC

fc± fM
20 ( :T l(RE + 2re)
0.637RL

fc ± fM, 3fc ± fM·
5fc ± fM···

---

High-level AC

The basic current of Figure 5 allows no carrier
to be present in the output. By adding offset
to the carrier differential pairs, controlled
amounts of carrier appear at the output
whose amplitude becomes a function of the
modulation signal or AM modulation. As
shown, the carrier null circuit is changed from
Figure 5 to have a wider range so that wider
control is achieved. All connections are
shown in Figure 6.

RE + 2re

+12 VDC

,.

"

RL

3.9K

H>-+-o.vo

Ve O.ll'f ,-'W.~-~--I
CARRIER INPUT ~f-'~------1

s~~t~J:t~ ~v.--,.----~--j

AM DEMODULATION
As pointed out in Equation 1, the output of the
balanced mixer is a cosine function of the
angle between Signal and carrier inputs. Further, if the carrier input is driven hard enough
to provide a switching action, the output
becomes a function of the input amplitude.
Thus the output amplitude is maximum when
there is 0° phase difference as shown in
Figure 7.

6.8.

v.
• VDC

NOTE:

All resistor values are in ohms

Figure 6. AM Modulator

Amplifying and limiting of the AM carrier is
accomplished by IF gain block providing 55dB
Febnuary 1987

4-66

Signetics Linear Products

Application Note

Balanced Modulator/Demodulator Applications
Using the MC1496/MC1596

AN189

+12V

3.9K

600

HIGH
FREQUENCY
2

3.9K

'K

5

Me1.

AMPUFlERANO
UMITER

'OK

'0
5'

~IC\

5'

-00

0

90

0

PHASE ANGLE
-BV

NOTE,
All resistor values are in ohms

Figure 7. AM Demodulator
of gain or higher with limiting of 400IN. The
limited carrier is then applied to the detector
at the carrier ports to provide the desired
switching function. The signal is then demodulated by the synchronous AM demodulator
(1496) where the carrier frequency is attenuated due to the balanced nature of the
device. Care must be taken not to overdrive
the signal input so that distortion does not
appear in the recorded audio. Maximum conversion gain is reached when the carrier
signals are in phase as indicated by the
phase-gain relationship drawn in Figure 7.
Output filtering will also be necessary to
remove high frequency sum components of
the carrier from the audio signal.

NOTE,
All resistor values are in ohms

Figure 8. Phase Comparator

PHASE DETECTOR
The versatility of the balanced modulator or
multiplier also allows the device to be used as
a phase detector. As mentioned, the output of
the detector contains a term related to the
cosine of the phase angle. Two signals of
equal frequency are applied to the inputs as
per Figure 8. The frequencies are multiplied
together producing the sum and difference
frequencies. Equal frequencies cause the
difference component to become DC while
the undesired sum component is filtered out.

February 1987

The DC component is related to the phase
angle by the graph of Figure 9. At 90° the
cosine becomes zero, while being at maximum positive or maximum negative at 0° and
180°, respectively.
The advantage of using the balanced modulator over other types of phase comparators is
the excellent linearity of conversion. This
configuration also provides a conversion gain
rather than a loss for greater resolution. Used
in conjunction with a phase-locked loop, for

4-67

instance, the balanced modulator provides a
very low distortion FM demodulator.

FREQUENCY DOUBLER
Very similar to the phase detector of Figure 8,
a frequency doubler schematic is shown in
Figure 10. Departure from Figure 8 is primarily
the removal of the low-pass filter. The output
then contains the sum component which is
twice the frequency of the input, since both
input Signals are the same frequency.

Signetics Linear Products

Application Note

Balanced Modulator/Demodulator Applications
Using the MC1496/MC1596

AN189

...... ...... ......L....I~L......
L...J L..J

vco .....J

~"''''r''\.C

......

uv v
'cc.""c
;J?:>J..,?..,J

ovoc AVERAGE

,,·0'

fYYYYYVY\

+ VDC AVERAGE

tJi-180°

V\.AJ\.J\.A.}J\

- VOC AVERAGE

INPUT

'r"'"

V

_

25VOC

Me,,,,
Me, ...

"""

lSmV(rmo}

Figure 9. Phase Detector ± Voltages

t ...

'.
NOTE:
All resistor values are in ohms

Figure 10. Low Frequency Doubler

February 1987

4·68

Signetics

NE/SA602
Double-Balanced Mixer and
Oscillator
Product Specification

Linear Products
DESCRIPTION

FEATURES

The SAlNE602 is a low-power VHF
monolithic double-balanced mixer with
input amplifier, on-board oscillator, and
voltage regulator. It is intended for high
performance, low power communication
systems. The guaranteed parameters of
the SA602 make this device particularly
well suited for cellular radio applications.
The mixer is a "Gilbert cell" multiplier
configuration which typically provides
18dB of gain at 45MHz. The oscillator
will operate to 200M Hz. It can be configured as a crystal oscillator, a tuned tank
oscillator, or a buffer for an external L.O.
The noise figure at 45MHz is typically
less than 5dB. The gain, intercept performance, low-power and noise characteristics make the SA/NE602 a superior
choice for high-performance battery operated equipment. It is available in an 8lead dual in-line plastic package and an
8-lead SO (surface-mount miniature
package).

• Low current consumption: 2.4mA
typical
• Excellent noise figure: < 5.0dB
typical at 45MHz
• High operating frequency
• Excellent gain, intercept and
sensitivity
• Low external parts count;
suitable for crystal! ceramic filters
• SA602 meets cellular radio
specifications

PIN CONFIGURATION
D, FE, N Packages

INPUT.O.
INPUT B

Vee

2

7

OSCILLATOR

GROUND

3

6

OSCILLATOR

OUTPUT A

4

5

OUTPUT B

TOP VIEW

APPLICATIONS
•
•
•
•
•
•

Cellular radio mixer/oscillator
Portable radio
VHF transceivers
RF data links
HF/VHF frequency conversion
Instrumentation frequency
conversion

• Broadband LANs

BLOCK DIAGRAM

September 13, 1985

4-69

853-0390 80473

II

Product Specification

Signetics Linear Products

Double-Balanced Mixer and Oscillator

NEjSA602

ORDERING INFORMATION
DESCRIPTION

ORDER CODE

TEMPERATURE RANGE

o to
o to
o to

8-Pin Plastic DIP
8-Pin Plastic SO
8-Pin Cerdip

NES02N

+70'C
+70'C

NES020

+70'C

NES02FE

8-Pin Plastic 01 P

-40'C to + 85'C

8-Pin Plastic SO

-40'C to + 85'C

SAS02N
SAS02D

8-Pin Cerdip

- 40'C to

+ 85'C

SAS02FE

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

Vee

Maximum operating voltage

TSTG
TA

RATING

UNIT

9

V

Storage temperature

-65 to +150

'C

Operating ambient temperature range
NE602
SAS02

o to +70
-40 to +85

'C
'C

AC/DC ELECTRICAL CHARACTERISTICS

TA = 25'C, Vee = SV, Figure 1
LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS
Min

Vee

Typ

4.5

Power supply voltage range

UNIT
Max
8.0

V

2.8

mA

DC current drain

2.4

fiN

Input signal frequency

500

fose

Oscillator frequency

200

Noise figured at 45MHz

5.0

S.O

dB

-15

-17

dBm

Third-order intercept point

RIN
CIN

RFIN

= -45dBm:

f1 = 45.0
f2 = 45.0S

MHz
MHz

Conversion gain at 45MHz

14

dB

RF input resistance

1.5

kn

RF input capacitance

3

Mixer output resistance

(Pin 4 or 5)

1.5

3.5

pF
kn

DESCRIPTION OF OPERATION
0.5 to 1.31'H

12PF I

~
44.545MHz THIRD OVERTONE CRYSTAL

vee

1SOpF

NE602

1.5 to
44.2/l

~
120pF

Figure 1. Test Configuration
September 13, 1985

4-70

The NE/SAS02 is a Gilbert cell, an oscillatorl
buffer, and a temperature compensated bias
network as shown in the equivalent circuit. The
Gilbert cell is a differential amplifier (Pins 1 and
2) which drives a balanced switching cell. The
differential input stage provides gain and determines the noise figure and signal handling
performance of the system.
The NE/SAS02 is designed for optimum low
power performance. When used with the
SAS04 as a 45MHz cellular radio 2nd IF and
demodulator, the SAS02 is capable of receiving -119dBm signals with a 12dB SIN ratio.
Third-order intercept is typically -15dBm
(that's approximately + 5dBm output intercept
because of the RF gain). The system designer
must be cognizant of this large signal limitation. When designing LANs or other closed
systems where transmission levels
are high, and small-signal or signal-to-noise
issues not critical, the input to the NES02
should be appropriately scaled.

Product Specification

Signetics Linear Products

Double-Balanced Mixer and Oscillator

Besides excellent low power performance
well into VHF, the NE/SA602 is designed to
be flexible. The input, output, and oscillator
ports can support a variety of configurations
provided the designer understands certain
constraints, which will be explained here.
The RF inputs (Pins 1 and 2) are biased
internally. They are symmetrical. The equivalent AC input impedence is approximately
1.5k II 3pF through 50MHz. Pins 1 and 2 can
be used interchangeably, but they should not
be DC biased externally. Figure 3 shows
three typical input configurations.

The mixer outputs (Pins 4 and 5) are also
internally biased. Each output is connected to
the internal positive supply by a 1.5k.ll resistor. This permits direct output termination yet
allows for balanced output as well. Figure 4
shows three single ended output configurations and a balanced output.
The oscillator is capable of sustaining oscillation beyond 200M Hz in crystal or tuned tank
configurations. The upper limit of operation is
determined by tank "a" and required drive
levels. The higher the "a" of the tank or the
smaller the required drive, the higher the

NE/SA602
permissible oscillation frequency. If the required l.O. is beyond oscillation limits, or the
system calls for an external l.O., the external
signal can be injected at Pin 6 through a DC
blocking capacitor. External l.O. should be at
least 200mV p.p.
Figure 5 shows several proven oscillator
circuits. Figure 5a is appropriate for cellular
radio. As shown, an overtone mode of operation is utilized. Capacitor C3 and inductor L1
suppress oscillation at the crystal fundamental frequency. In the fundamental mode, the
suppression network is omitted.
Figure 6 shows a Colpitts varacter tuned tank
oscillator suitable for synthesizer-controlled
applications. It is important to buffer the
output of this circuit to assure that switching
spikes from the first counter or prescaler do
not end up in the oscillator spectrum. The
dual-gate MOSFET provides optimum isolation with low current. The FET offers good
isolation, simplicity, and low current, while the
bipolar transistors provide the simple solution
for non-critical applications. The resistive divider in the emitter-follower circuit should be
chosen to provide the minimum input signal
which will assure correct system operation.
When operated above 100MHz, the oscillator
may not start if the a of the tank is too low. A
22k.ll resistor from Pin 7 to ground will
increase the DC bias current of the oscillator
transistor. This improves the AC operating
characteristic of the transistor and should
help the oscillator to start. 22k.ll will not upset
the other DC biasing internal to the device,
but smaller resistance values should be
avoided.

o

GNU

Figure 2. Equivalent Circuit

.....

a. Single-Ended Tuned Input

N....

b. Balanced Input (For Attenuation
of Second-Order Products)
Figure 3. Input Configuration

September 13, 1985

4-71

c. Single-Ended Untuned Input

•

Signetics Linear Products

Product Specification

Double-Balanced Mixer and Oscillator

NEjSA602

CF1J465
OR EQUIVALENT
NE602

FILTER K&L38780 OR EOUIVALENT
*CT MATCHES 3.SKO TO NEXT STAGE.

a. Single-Ended Ceramic Filter

b. Single-Ended Crystal Filter

NE802

NE802

c. Single-Ended 1FT

d. Balanced Output
Figure 4. Output Configuration

R

1

NE602

a. Colpitts Crystal Oscillator
(Overtone Mode)

NE602

NE602

b. Colpitts LIC Tank Oscillator

c. Hartley LIC Tank Oscillator

Figure 5. Oscillator Circuits

September 13, 1985

4-72

Product Specification

Signetics Linear Products

NEjSA602

Double-Balanced Mixer and Oscillator

S.5.uH

~-"""--"""---~~FFER

5

I..______~

l000PF¥~
1 ..

t

1000pF

O.06.H

-=

t

DC CONTROL VOLTAGE
FROM SYNTHESIZER

MV.l0S
OR EQUIVALENT

rO.01PF

lOOK

2K

-=

3SKI26

2N5484

2pF

~~--~~~~-.

t---4----l(----o
TO SYNTHESIZER

O.OlpF

lOOK
lOOK

Figure 6. Colpitts Oscillator Suitable for Synthesizer Applications and Typical Buffers

*

0.5 to 1.3,LH

44.545 MHz

THIRD OVERTONE CRVST Al

Vee

SA602

SFG455A3

OREQiLENTr

-=-

Figure 7. Typical Application for Cellular Radio

September 13. 1985

4-73

"::"

II

Product Specification

Signetlcs Linear Products

Double-Balanced Mixer and Oscillator

-

+••

....
....:>~

..

.

-

..

-14.5

-"

'~.5

-12

E

!!. -'3
~ -14 I--

-20

OJ

..

0

U
a;

E -30

I!!
!

-40

NEjSA602

-'2
12.5 -

.1-'3.5

r--

-15

S -16.5

~

i!

-'6
-'7

-50

~

-'5.5

-'7.5

-'8.

5
-19.0

-'8

-'9.5
4

5

6

7

8

9

.0

/

I

/

vV

I
40

40

80

.20

TEMPERATURE tOe)

Vcc(VOLTS)
OP01310S

Figure 8. SAINE602 Thlrd-order
Intermod and 1dB Compression
Point Performance

Figure 9. Input Thlrd·Order
Intercept Point vs Vcc

Figure 10. Third·Order Intercept
Point vs Temperature

~r-----'-----~----~

+40
TEMPERATURE (Oc)

Figure 11

September 13, 1985

+80

!4O=-------7-------~+40~------J+80

~~------~------+~4-0------+~80

TEMPERATURE !"C)

TEMPERATURE (OC)

Figure 12

Figure 13

4·74

Signetics

AN198
Designing With the NEjSA602
Application Note

Linear Products

Author: Robert J. Zavrel, Jr.

INTRODUCTION
The NE/SA602 represents a new industry
standard for low power, double-balanced mixers. This device also includes an on-board
local oscillator and voltage regulator. Typical
power supply requirements are 2.5mA at 6V
for a conversion gain of 18dS and a noise
figure of 5dS with operation up to 200MHz.
The NE/SA602 is available in either an 8-pin
DIP or a surface mount package. These
specifications render this device an ideal
choice for portable battery-operated applications.

CIRCUIT CONFIGURATIONS
Figure 1 shows a simplified block diagram of
the NE/SA602. A multiplier "Gilbert Cell" is
used as the mixer portion of the device with
the input differential amplifier providing most
of the conversion gain. This differential amplifier also serves as an input balun which helps
reduce the second-order distortion products.
Figure 2 shows some possible balanced and
unbalanced input and output circuits while
Table 1 summarizes these configurations'
relative advantages and disadvantages.
Figure 3 shows a simplified version of the
internal circuitry adjacent to the device pins.
The oscillator can be configured with a crystal, a tank, or as a buffer/driver for an
external oscillator. When used as a buffer
amplifier, optimum performance will be
achieved when Pin 6 is driven with a 200 to
300mV RMS signal through capacitive coupling.
This La amplitude tolerance becomes more
critical as the La frequency approaches the
200M Hz maximum. Figure 4 shows a typical

February 1987

test circuit for the NE/SA602. For this overtone circuit, it is important to specify the
parallel mode crystal frequency and use a
crystal with a loading capacitance of 5pF.

DESIGN DATA
Figure 6 shows typical intermodulation and
compression point performance of the
NE/SA602. The compression point defines
the upper limit of the effective mixer dynamic

range at about -25dSm. This level is mainly a
function of the circuit insertion loss prior to
the 602 input. The input third order intercept
point is shown here at the minimum value of
-15dSm, and, as such, can be considered a
worst-case condition.
The remaining charts show various mixer
parameters over temperature and supply voltage variation. The overall optimum supply
voltage is between 5 and 6V, and this value
range is thus recommended. Unless specifically indicated, Figure 4 was the test circuit
used to produce the data. The frequency
schemes used here are typical of those found
in cellular radio applications employing a
455kHz 2nd IF. All of the major specifications
are nearly constant over the 200MHz frequency range with the exception of the La
drive level tolerance and device impedances.
The noise figure has been optimized for a
45MHz input frequency.

process used by the NE602, the phase integrity through all three ports is superb. This
aspect makes the NE602 an ideal choice for
image rejection mixer applications. Signetics
AN 1981 is dedicated to a detailed description
of image rejection mixer techniques, or "dual
quadrature mixers".
AN1982 presents a detailed discussion of
oscillator configurations possible with the
NE602. Figure 4 presents a typical overtone
crystal configuration. However, a more traditional Colpitts fundamental circuit can be built
using only the 5.6 and 22pF capacitors.
Newer damping techniques in crystal technology can eliminate the need for tank circuits in
overtone oscillators as well.
Although Signetics offers specifications up to
200MHz, the NE602 has been used successfully up to 900MHz. However, no guarantees
can be made at frequencies over 200MHz on
any specification.

vcc
GND

ADDITIONAL COMMENTS
The NE602 has some obvious specification
advantages: very low power consumption for
very respectable performance. There are also
some characteristics which are not obvious to
the user. As a result of the very fast bipolar

4-75

Figure ,_ NE/SA602 Functional Diagram

•

Signetlcs Linear Products

Application Note

AN198

Designing With the NE/SA602

NE602

b. Balanced Input (for attenuation
of second-order products)

a. Single-Ended Input

NE802

NE602

c. Single-Ended Output

d. Balance Output (for 3dB output improvement)
Figure 2. Circuit Configurations

Table 1
ADVANTAGES

Input Pins 1 & 2

Output Pins 4 & 5

February 1987

DISADVANTAGES

Single-ended

No sacrifice in
3rd-order
performance.
simplified circuit

Increase in 2ndorder products

Balanced

Reduce 2nd·order
products

Impedance match
more difficult to
achieve

Single-ended

Simple interface to
filters

3dB reduction in
output. less RF
and LO isolation

Balanced

3dB improvement
in output. better
LO and RF
isolation at the
output

More complex
circuitry required

4-76

Signetics Linear Products

Application Note

AN198

Designing With the NE/SA602

8

1.SK

Vee

1.SK

CD

GND

Figure 3. NE/SA602 Equivalent Circuit

0.5 to 1.3#4H
34.2MHz THIRD OVERTONE CRYSTAL

Vee

lS0pF

NE602

1.5 to
4.2j1.H

120pF

10.7MHz

Figure 4. Typical Application

February 1987

4-77

Signetics Linear Products

Application Note

Designing With the NE/SA602

AN198

D, N Packages
+10

-10

-11
-12

'~~·o'"

....
:>

INPUT 8

2

7

OSCILLATOR

I!::>

GROUND

3

6

OSCILLATOR

ID

OUTPUT A 4

5

-10

E

-20

Ii:
w

-14

!

-16

-12.5-

r-- ~'3.5

r-

"a:w -15

E -30

'0

-40

OUTPUT B

-13

':

0

-12

J.5

-17
TOP

-50

view

-18

•

10

7

Vcc VOLTS

Figure 6. NE/SA602 Third-Order
Intermod and 1dB Compression
Point Performance

Figure 5. Pin Configuration

-14.5

E -15.5

/'

':

$ -16.5
ffi
!

i

-17.5

-18.5
-19.0

/

-19.5

/
-40

Figure 7. Input Third-Order Intercept
Point VB Vee

22r-----..,...----...,..-----...,

rr~

/
4V

40

80

120

o

TEMPERATURE ('C)

Figure 8. Input Third-Order Intercept Point vs Temperature

c

S
IEw

+~

Figure 9

.~----::::;;;l_-==---+-------l

i----

a:

,,!Ii

+40
TEMPERATURE ('C)

~

I-.
4V

3
6V

------

8V
6V

4

!40~~--------~0------------+~40~---------+~~~

TEMPERATURE ('C)
AT 45 MHz INPUT FREQUENCY

Figure 10

February 1987

+40

-40

TEMPERATURE rC)

Figure 11

4-78

+~

Signetics

AN1981
New Low Power Single
Sideband Circuits
Application Note

Linear Products

by Robert J. Zavrel Jr.

INTRODUCTION
Several new integrated circuits now permit
RF designers to resurrect old techniques of
single-sideband generation and detection.
The high cost of multi-pole crystal filters limits
the use of the SSB mode to the most
demanding applications. yet the advantages
of SSB over full-carrier AM and FM are welldocumented (Ref 1 & 2). The use of multipole filters can now be circumvented by
reviving some older techniques without sacrificing performance. This has been made
possible by the availability of some new RF
and digital integrated circuits.

DESCRIPTION
Figure 1 shows the frequency spectrum of a
1OMHz full-carrier double-sideband AM signal
using a 1kHz modulating tone. This wellknown type of signal is used by standard AM
broadcast radio stations. Full-carrier AM's
advantage is that envelope detection can be
used in the receiver. Envelope detection is a
simple and economical technique because it
simplifies receiver circuitry. Figure 2 shows
the time domain "envelope" of the same AM
signal.
The 1kHz tone example of Figures 1 and 2
serves as a simple illustration of an AM
signal. Typically, the sidebands contain complex waveforms for voice or data communications. In the full-carrier double sideband mode
(AM), all the modulation information is contained in both sidebands, while the carrier
"rides along" without contributing to the
transfer of intelligence. Only one sideband
without the carrier is needed to effectively
transmit the modulation information. This
mode is called "single-sideband suppressed
carrier". Because of its reduced bandwidth, it
has the advantages of improved spectrum
utilization, better signal-to-noise ratios at low
signal levels, and improved transmitter efficiency when compared with either FM or fullcarrier AM. A finite frequency allocation using
SSB can support three times the number of
channels when compared with comparable
FM or AM full-carrier systems.
There are three basic methods of singlesideband generation. All three use a balanced
modulator to produce a double-sideband suppressed carrier signal. The undesired sideband is then removed by phase and amplitude nulling (the phasing method), high Q
multi-pole filters (the filter method), or a
February 1987

CARRIER

LOWER

UPPER

SIDEBAND

SIDEBAND

9.9tI9MHz

1o.000MHz

1o.OOIMHz

Figure 1. Frequency Domain Display of
a 10MHz Carrier AM Modulated by a
1kHz Tone (Spectrum Analyzer Display)

1+--1 mS ----+I

10MHz CARRIER

Figure 2. Time Domain Display of the
Same Signal Shown in Figure 1
(Oscilloscope Display)
"third" method which is a derivation of the
phasing technique called here the "Weaver"
method for the apparent inventor. The reciprocal of the generator functions is employed
to produce sideband detectors. Generators
start with audio and produce the SSB signal;
detectors receive the SSB signal and reproduce the audio. Since the sideband signal is
typically produced at radio frequencies, it can
be amplified and applied to an antenna or
used as a subcarrier.
Reproduction of the audio Signal in a fullcarrier AM receiver is simplified because the
carrier is present. The signal envelope, which
contains the carrier and the sidebands, is
applied to a non-linear device (typically a
diode). The effect of envelope detection is to
multiply the sideband signal by the carrier;
this results in the recovery of the audio
waveform. The mathematical basis for this
process can be understood by studying trigonometric identities.
Since the carrier is not present in the received
SSB signal, the receiver must provide it for
proper audio detection. This signal from the
local oscillator (LO) is applied to a mixer
(multiplier) together with the SSB signal and
detection occurs. This technique is called

4-79

product detection and is necessary in all SSB
methods. A major problem in SSB receivers is
the ability to maintain accurate LO frequencies to prevent spectral shifting of the audio
signal. Errors in this frequency will result in a
"Donald Duck" sound which can render the
signal unintelligible for large frequency errors.

Theory of Single-Sideband
Detection
Figures 3 through B illustrate the three methods of SSB generation and detection. Since
they are reciprocal operations, the circuitry for
generation and detection is similar with all
three methods. Duplication of critical circuitry
is easy to accomplish in transceiver applications by using appropriate switching circuits.
Figures 3 and 4 show the generation and
detection techniques employed in the filter
method. In the generator a double sideband
signal is produced while the carrier is eliminated with the balanced modulator. Then the
undesired sideband is removed with a high Q
crystal bandpass filter. A transmit mixer is
usually employed to convert the SSB signal to
the desired output frequency. The detection
scheme is the reciprocal. A receive mixer is
used to convert the selected input frequency
to the IF frequency, where the filter removes
the undesired SSB response. Then the signal
is demodulated in the product detector. A
major drawback to the filter method is the fact
that the filter is fixed-tuned to one frequency.
This necessitates the receive and transmit
mixers for multi-frequency operation.
Figures 5 and 6 show block diagrams of a
generator and demodulator which use the
phase method. Figure 5 also includes a
mathematical model. The input signal
(Cos(Xt)) is fed in-phase to two RF mixers
where "X" is the frequency of the input
signal. The other inputs to the mixers are fed
from a local oscillator (LO) in quadrature
(Cos(Yt) and Sin(Yt)), where "Y" is the frequency of the LO signal. By differentiating the
output of one of the mixers and then summing
with the other, a single sideband response is
obtained. Switching the mixer output that is
differentiated will change the selected sideband, upper (USB) or lower (LSB). In most
cases the mixer outputs will be the audio
passband (300 to 3000Hz). Differentiating the
passband involves a 90 degree phase shift
over more than three octaves. This is the
most difficult aspect of using the phasing
method for voice band SSB.

II

Application Note

Signetics Linear Products

New Low Power Single Sideband Circuits

AUDIO
INPUT

AN1981

}------{~---o~~T~~
BALANCED
MODULATOR

MODULATOR
LO

TRANSMIT

LO

Figure 3. Filter Method

sse

Generator

PRODUCT
DETECTOR

1ST MIXER

AUDIO
OUTPUT

RFSS8
INPUT

For voice systems, difficulty of maintaining
accurate broadband phase shift is eliminated
by the technique used in Figures 7 and 8. The
"Weaver" method is similar to the phasing
method because both require two quadrature
steps in the signal chain. The difference
between the two methods is that the Weaver
method uses a low frequency (1.8kHz) sub·
carrier in quadrature rather than the broad·
band 90 degree audio phase shift. The de·
sired sideband is thus "folded over" the
1.8kHz subcarrier and its energy appears
between 0 and 1.5kHz. The undesired side·
band appears 600Hz farther away between
2.1 and 4.8kHz. Consequently, sideband reo
jection is determined by a low·pass filter
rather than by phase and amplitude balance.
A very steep low·pass response in the Weaver method is easier to achieve than the very
accurate phase and amplitude balance needed in the phasing method. Therefore, better
sideband rejection is possible with the Weaver method than with the phasing method.

Quadrature Dual Mixer Circuits
One of the two critical stages in the phasing
method and both critical stages in the Weaver
method require quadrature dual mixer circuits.
Figures 9 and 10 show two methods of
obtaining quadrature La signals for dual mixer applications. Other methods exist for producing quadrature La signals, particularly use
of passive LC circuits. LC circuits will not
maintain a quadrature phase relationship
when the operating frequency is changed.
The two illustrated circuits are inherently
broad·banded; therefore, they are far more
flexible and do not require adjustment. These
circuits are very useful for SSB circuits, but
also can be applied to FSK, PSK, and QPSK
digital communications systems.

PRODUCT
DETECTOR

RECEIVE
LO

LO

Figure 4. Filter Method

sse

SIN(yt)

Detector

LOWER SIDEBAND

AUOIO OUTPUT

RFSSB

2SIN(xt)

INPUT

The NE602 is a low power, sensitive, active,
double-balanced mixer which shows excellent phase characteristics up to 200M Hz. This
makes it an ideal candidate for this and many
other applications.

COS (yl)

Figure 5. Phasing Method Detector with Simplified Mathematical Model

CLOCK
SIN(4yt)

RF
SSB

OUTPUT

Figure 6. Phasing Method Generator

February 1987

4-80

The circuit in Figure 9 uses a divide·by·four
dual flip-flop that generates all four quadra·
tures. Most of the popular dual flip·flops can
be used in different situations. The HEF4013
CMOS device uses very little power and can
maintain excellent phase integrity at clock
rates up to several megahertz. Consequently,
the HEF4013 can be used with the ubiquitous
455kHz intermediate frequency with excellent
power economy. For higher clock rates (up to
120MHz for up to 30MHz operation), the fast
TTL 74F7 4 is a good choice. It has been
tested to 30MHz operating frequencies with
good results (> 30 dB SSB rejection). At
lower frequencies (SMHz) sideband rejection
increases to nearly 40dB with the circuits
shown. The ultimate low frequency rejection
is mainly a function of the audio phase shifter.

Signetics Linear Products

Application Note

New Low Power Single Sideband Circuits

AN1981

Better performance is possible by employing
higher tolerance resistors and capaCitors .
• FLO

The circuit in Figure 10 shows another technique for producing a broadband quadrature
phase shift for the LO. The advantage of this
circuit over the flip-flops is that the clock
frequency is identical to the operating frequency; however, phase accuracy is more
difficult to achieve. A PLL will maintain a
quadrature phase relationship when the loop
is closed and the VCO voltage is zero. The
DC amplifier will help the accuracy of the
quadrature condition by presenting gain to
the VCO control circuit. The other problem
that can arise is that PLL circuits tend to be
noisy. Sideband noise is troublesome in both
SSB and FM systems, but SSB is less sensitive to phase noise problems in the LO.

OfFSET BY

7......
LO

7.2KHz FROM
RECEIVED SIGNAL

1.8kHz
LP. FILTER

Figure 7. Weaver Method Generator

.FLO
OFFSET 7.2kHz
FROM RECEIVED SIGNAL

Figure 11 shows a circuit that is effective for
driving the 74F7 4, or other TTL gates, with a
signal generator or analog LO. The NE5205
provides about 20dB gain with 50n input and
output impedances from DC to 450MHz. Minimum external components are required. The
1kn resistor is about optimum for "pulling"
the input voltage down near the logic threshold. A 50n output level of OdBm can be
used to drive the NE5205 and 74F74 to
1OOMHz. Two NE5205s can be cascaded for
even more sensitivity while maintaining extremely wide bandwidth. An advantage of
using digital sources for the LO is that lowfrequency power supply ripple will not cause
hum in the receiver front end. This is a
common problem in direct conversion designs.

7.2ttHzLO

1.IMI.Hz
LP.: FILTER

Figure 8. Weaver Method Detector

r------------J~-o~

,...
o·

7=

'--1'---------<> 270"
0--.4-----------------'

4110UTPUT
FREQUENCY

Figure 9. Dual Flip·Flop Quadrature Synthesis

CO&u1

SIN",t

Figure 10. PLL Quadrature Synthesis

February 1987

4-81

Figure 12 shows the interface cirCUitry between the 74F7 4 and the NE602 LO ports.
The total resistance reflects conservative current drain from the 74F7 4 outputs, while the
tap on the voltage divider is optimized for
proper NE602 operation. The low signal
source impedance further helps maintain
phase accuracy, and the isolation capacitor is
miniature ceramic for DC isolation.

Audio Amplifiers and Switching
Using active mixers (NE602) in these types of
circuits gives conversion gain, typically 18dB.
More traditional applications use passive diode ring mixers which yield conversion loss,
typically 7dB. Consequently, the detected
audio level will be about 25dB higher when
using the NE602. This fact can greatly reduce
the first audio stage noise and gain requirements and virtually eliminate the" microphonicl! effect common to direct conversion receivers. Traditional direct conversion receivers use passive audio LC filters at the mixer
output and low nOise, discrete JFETs or
bipolars in the first stages. The very high
audio sensitivity required by these amplifiers
makes them respond to mechanical vibration-thus the "microphonics" result. The

•

",','

r,:

Signetics Linear Products

Application Note

New Low Power Single Sideband Circuits

AN1981

method; thus the higher cost may be justified
in some applications.

I

CK1

Cia

Figure 11. FAST TTL Driver from Analog Signal Source Using NE5205

180'
,.".

Q2

5100

~

~
510tl

30tl

0.1

"1
30tl

·sv

~

~

o

Figure 12. Interface Circuitry Between 74F74 and the NE602s
conversion gain allows use of a simple op
amp stage (Figure 13) set up as an integrator
to eliminate ultra-sonic and RF instability. The
NE5534 is well known for its low noise, high
dynamic range, and excellent audio characteristics (Reference 12) and makes an ideal
audio amp for the 602 detector.
The sideband select function is easily accomplished with an HEF4053 CMOS analog
switch. This triple double-pole switch drives
the phase network discussed in the next
section and also chooses one of two amplitude balance potentiometers, one for each
sideband. Figure 14 illustrates this circuit. A
buffer op amp is used with the two sideband
select sections to reduce THO, maintain amplitude integrity, and not change the filter
network input resistance values. The gain
distribution within both legs of the receiver
was found to be very consistent (within 1dB),
thus the amplitude balance pots may be
eliminated in less demanding applications.
The NE602s have excellent gain as well as
phase integrity.

Audio Phase Shift Circuits
The two critical stages for the phasing method are a dual quadrature mixer and a broadband audio phase shifter (differentiatOr).
There are several broadband, phase shift
techniques available. Figure 15 shows an
analog all-pass differential phase shift circuit.
When the inputs are shorted and driven with a
microphone circuit, the outputs will be 90
degrees out-of-phase over the 300 to 3000Hz
band. This "splitting" and phase shift is
February 1987

necessary for the phaSing generator. For
phasing demodulation the two audio detectors are fed to the two inputs. The outputs are
then summed to affect the sideband rejection
and audio output.
Standard 1% values are shown for the resistors and capacitors, although better gain
tolerances can be obtained with 0.1 % lasertrimmed integrated resistors. Polystyrene capacitors are preferred for better value tolerance and audio performance. Two quad op
amps fit nicely into this application. One op
amp serves as a switch buffer and the other
three form a phasing section. The NE5514
quad op amps perform well for this application. Careful attention to active filter configurations can yield highly linear and very high
dynamic range circuits. Yet these characteristics are much easier to achieve at audio than
the common IF RF frequencies. This fact,
coupled with the lack of IF tuned circuits,
shielding, and higher power requirements
make audio IF systems attractive indeed.
Figure 16 shows a "tapped" analog delay
circuit which uses weighted values of resistors to affect the phase shift. This technique
takes advantage of the Hilbert transform.
(Readers are requested to consult Reference
4 for detailS.) Excellent phase and amplitude
balance are possible with this technique, but
the price for components is high. It should be
stressed that the audio phase shift accuracy
and amplitude balance are the limiting factors
for SSB rejection when using the phase

4-82

The summing amplifier is a conventional,
inverting op amp circuit. It may be useful to
configure a low-pass filter around this amplifier, and thus help the sharp audio filters which
follow. Audio filters are necessary to shape
the desired bandpass. Steep slope audio
bandpass filters can be built from switched
capacitor filters or from active filters requiring
more op amps. Switched capacitor filters
have the disadvantage of requiring a clock
frequency in the RF range. Harmonics can
cause interference problems if careful design
techniques are not used. Also, better dynamic
range is obtained with active filter techniques
using "real" resistors although much work is
being done with SCF's and performance is
improving.

Audio Processing
Direct conversion receivers rely heavily on
audio filters for selectivity. Active analog or
switched capacitor filters can produce the
high Q and dynamic ranges necessary. Signal
strength or "S-meters" can be constructed
from the NE602' s companion part, the
NE604. The "RSSI" or "received signal
strength indicator" function on the 604 provides a logarithmic response over a 90dB
dynamic range and is easy to use at audio
frequencies. Finally, the AGC (automatic gain
control) function can also be performed in the
audio section. Attack and delay times can be
independently set with excellent distortion
specifications with the NE572 compander IC.
The audio-derived AGC eliminates the need
for gain contrOlling and RF stage, but relies
on an excellent receiver front-end dynamic
range. In ACSSB systems transmitter compression and receiver expansion are defined
by individual system specifications.

Phasing-Filter Technique
High quality SSB radio specifications call for
greater than 70dB sideband rejection. Using
the circuits described in this paper for the
phasing method, rejection levels of 35dB are
obtainable with good reliability. Coupled with
an inexpensive two-pole crystal or ceramic
filter, the 70dB requirement is obtained. Also,
the filtering ahead of the NE602 greatly
improves the intermodulation performance of
the receiver. Figure 17 shows a complete
SSB receiver using the Phasing-Filter technique. The sensitivity of the NE602 allows low
gain stages and low power consumption for
the RF amplifier and first mixer. A new
generation of low power CMOS frequency
synthesizers is now available from several
manufacturers including the TDD1742T and
dual chip HEF4750/51 solutions.

Direct Conversion Receiver
The antenna can be connected directly to the
input of the NE602 (via a bandpass filter) to

Signetics Linear Products

Application Note

New Low Power Single Sideband Circuits

AN1981

....'

0.'.'

RESONANT

TUNED
CIRCUIT

r

NE602
CIRCUIT

FROM
FIGURES
9&12

'5V

450pF

Figure 13. Phasing Method Detector for Direct Conversion Receiver

form a direct conversion SSB receiver using
the phasing method. 35dB sideband rejection
is adequate for many applications, particularly
where low power and portable battery operation are required. Figure 13 shows a typical
circuit for direct conversion applications.
There are many other applications which can
make use of SSB technology. Cordless telephones use FM almost exclusively. Eavesdropping could be greatly reduced for systems which employ SSB rather than FM.
Furthermore, the better signal-to-noise ratio
will extend the range, and battery life will be
extended because no carrier is needed.
SSB is also used for subcarriers on microwave links and coaxial lines. Telephone communications networks that use 88B are
called FDM or Frequency Domain Multiplex
systems. The low power and high sensitivity
of the NE602 can offer FDM designers new
techniques for system configuration.

Weaver Method Receiver
Techniques
The same quadrature dual mixer can be used
for the first stage in both the phasing and

February 19B7

Weaver method receiver. The subcarrier
stage in the Weaver method receiver can use
CMOS analog switches (HEF4066) for great
power economy. Figure 18 shows a circuit for
the subcarrier stage. A 1.8kHz subcarrier
requires a 7.2kHz clock frequency. If switched
capacitor filters are used for the low-pass and
audio filters, a single clock generator can be
used for all circuits with appropriate dividers.
Furthermore, if the receiver is used as an IF
circuit, the fixed LO signal could also be
derived from the same clock. This has the
added advantage that harmonics from the
various circuits will not interfere with the
received signal.

Results
The circuit shown in Figures 13, 14, and 15
has a 10dB SIN sensitivity of 0.5tJ.V with a
dynamic range of about BOdB. Single-tone
audio harmonic distortion is below 0.05% with
two-tone intermodulation products below
55dB at RF input levels only 5dB below the
1dB compression point. The sideband rejection is about 3BdB at a 9MHz operating
frequency. The good audio specifications are
a side benefit to direct conversion receivers.

4-83

When used with inexpensive ceramic or crystal filters, this circuit can provide these specifications with > 70dB sideband rejection.

Conclusions
Single sideband offers many advantages over
FM and full-carrier double-sideband modulation. These advantages include: more efficient spectrum use, better signal-to-noise
ratios at low signal levels, and better transmitter efficiency. Many of the disadvantages can
now be overcome by using old techniques
and new state-of-the-art integrated circuits.
Effective and inexpensive circuits can use
direct conversion techniques with good results. 35dB sideband rejection with less than
1tJ.V sensitivity is obtained with the NE602
circuits. 70dB sideband rejection and superior
sensitivity are obtained by using phasing-filter
techniques. Either the phasing or Weaver
methods can be used in either the direct
conversion or IF section applications. The
filter and phase-filter methods can be used in
only the IF application.

Signetlcs Linear Products

Application. Note

New Low Power Single Sideband Circuits

HEF4053

2X NE5S14

AN1981

BROADBAND PHASE SHIFT NElWORK
FIGURE 15 CIRCUIT

NE5534

DETECTOR

NE5534
DETECTOR

UK

USB
AMPLITUDE
BALANCE POTS
LSB

10K

UK
SSB
AUDIO
OUTPUT

THE THREE
SWITCH CONTROL
PINS ARE TIED
TOGETHER FOR
ONE BIT
SIDEBAND SELECT
FUNCTION

Figure 14. Sideband Select Switching Function

10kll

10k(}

10kll

10kll

10kll

10kll

ANALOG
SWITCH
BUFFERS
INPUT

A

INPUT

B

Figure 15

February 1987

4-84

Signetics Linear Products

Application Note

New Low Power Single Sideband Circuits

CLOCK

VOICE
INPUT

I

TAPPED
DElAY UNE
NSAMPLES

I

R,

AN1981

RETICONTA

......

R,

RN-2

R.

• R,

RN-1

• R•

RN=R1

l

VOl CE8O"

WEIGHTED SUM

FIXED DELAY
N/2SAMPLES
REFERENCE
CHANNEL

VOIC EO"

RETICDN TAD-32

Figure 16. Broadband 90' Audio Phase Shift Technique Using Tapped Delay Line (Reference 4)

1ST MIXER
DIRECT
CONVERSION
PHASINGSSB
RECEIVER

FRONT
END
FILTERS

AUDIO FILTERS.
II-METERAND
AGC

SYNTHESIZED

LO

Receivers built using this technique can exhibit excellent characteristics without resorting to expensive multi-pole
filters or an IF Amplifier chain.

Figure 17. Complete Phasing-Filter Receiver

February 1987

4-85

Signetlcs Linear Products

Application Note

New Low Power Single Sideband Circuits

AN1981

:!O"12OMHz
LO
CLOCK

'.F

NE602

SSB
RFINPUT

OUAL
FLIP-FLOP

450p'

74F74

'80"

HEF 40'3
DUAL
FLIP-FLOP
FIGURE 9
CIRCUIT

NE602

'.'

OSCILLATOR
AND + 512
CIRCUIT

Figure 18. Weaver Method Receiver Concept Example For ,;;; 30MHz Operation

REFERENCES
1.

Spectrum Scarcity Drives Land-mobile
Technology, G. Stone, Microwaves and
RF, May, 1983.

2.

SSB Technology Fights its Way into the
Land-mobile Market, B. Manz, Microwaves and RF, Aug., 1983.
A Third Method of Generation and Detection of Single-Sideband Signals, D. Weaver, Proceedings of the IRE, 1956.
Delay Lines Help Generate Quadrature
Voice for SSB, Joseph A. Webb and M.
W. Kelly, Electronics, April 13, 1978.

3.

4.

February 1987

5.

6.
7.
8.

9.

A Low Power Direct Conversion Sideband Receiver, Robert J. Zavrel Jr., ICCE
Digest of Technical Papers, June, 1985.
Electronic Filter Design Handbook, Arthur
B. Williams, McGraw-Hili, 1981.
Solid State Radio Engineering, Herbert L.
Krauss, et ai, Wiley, 1980.
ACSB-An Overview of Amplitude Compandored Sideband Technology, James
Eagleson, Proceedings of RF Technology Expo 1985.
The ARRL Handbook for the Radio Amateur, American Radio Relay League,
1985.

4-86

10. Designing With the SAlNE602 (AN198),
Signetics Corp., Robert J. Zavrel Jr.,
1985.
11. RF IC's Thrive on Meager Battery-Supply
Diet, Donald Anderson, Robert J. Zavrel
Jr., EON, May 16, 1985.
12. Audio IC Op Amp Applications, Walter
Jung, Sams Publications, 1981.

13. 2 Meter Transmitter Uses Weaver Modulation, Norm Bernstein, Ham Radio, July,
1985.

Signetics

AN1982
Applying the Oscillator of the
NE602 in Low Power Mixer
Applications

Linear Products

Application Note

by Donald Anderson

most commonly used configurations in their
most basic form.

rent, 200M Hz oscillation can be achieved with
high Q and appropriate feedback.

INTRODUCTION

In each case the Q of the tank will affect the
upper frequency limits of oscillation: the
higher the Q the higher the frequency. The
NE602 is fabricated with a 6GHz process, but
the emitter resistor from Pin 7 to ground is
nominally 20k. With O.25mA typical bias cur-

The feedback, of course, depends on the Q
of the tank. It is generally accepted that a
minimum amount of feedback should be
used, so even if the choice is entirely empirical, a good trade-off between starting characteristics, distortion, and frequency stability
can be quickly determined.

For the designer of low power RF systems,
the Signetics NE602 mixer/oscillator provides mixer operation beyond 500MHz, a
versatile oscillator capable of operation to
200M Hz, and conversion gain, with only
2.5mA total current consumption. With a
proper understanding of the oscillator design
considerations, the NE602 can be put to work
quickly in many applications.

DESCRIPTION
Figure 1 shows the equivalent circuit of the
device. The chip is actually three subsystems:
A Gilbert cell mixer (which provides differential input gain), a buffered emitter follower
oscillator, and RF current and voltage regulation. Complete integration of the DC bias
permits simple and compact application. The
simplicity of the oscillator permits many configurations.
While the oscillator is simple, oscillator design
isn't. This article will not address the rigors of
oscillator design, but some practical guidelines will permit the designer to accomplish
good performance with minimum difficulty.

o

Either crystal or LC tank circuitry can be
employed effectively. Figure 2 shows the four

GND

Figure 1

TCO'B30S

a. Fundamental
Crystal

b. Overtone
Crystal

c. Colpitts
L/C Tank
Figure 2

February 1987

4-87

d. Hartley
L/C Tank

Signetics Linear Products

Application Note

Applying the Oscillator of the NE602
in Low Power Mixer Applications

AN1982

Crystal Circuit Considerations
Crystal oscillators are relatively easy to implement since crystals exhibit higher Q's than LC
tanks. Figure 3 shows a complete implementation of the SA602 (extended temperature
version) for cellular radio with a 45MHz first IF
and 455kHz second IF.

0.510 1.3pH

THIRD OVERTONE CRYSTAL

vee

The crystal is a third overtone parallel mode
with 5pF of shunt capacitance and a trap to
suppress the fundamental.
NE802

LC Tank Circuits
LC tanks present a little greater challenge for
the designer. If the Q is too low, the oscillator
won't start. A trick which will help if all else
fails is to shunt Pin 7 to ground with a 22k
resistor. In actual applications this has been
effective to 200MHz with high Q ceramic
capacitors and a tank inductor of O.OBIlH and
a Q of 90. Smaller resistor value will upset DC
bias because of inadequate base bias at the
input of the oscillator. An external bias resistor could be added from Vce to Pin 6, but this
will introduce power supply noise to the
frequency spectrum.
The Hartley configuration (Figure 2D) offers
simplicity. With a variable capacitor tuning the
tank, the Hartley will tune a very large range
since all of the capacitance is variable.
Please note that the inductor must be coupled to Pin 7 with a low impedance capacitor.
The Colpitts oscillator will exhibit a smaller
tuning range since the fixed feedback capacitors limit variable capacitance range; however, the Colpitts has good frequency stability
with proper components.

Synthesized Frequency Control
The NE602 can be very effective with a
synthesizer if proper precautions are taken to
minimize loading of the tank and the introduction of digital switching transients into the
spectrum. Figure 4 shows a circuit suitable for
aircraft navigation frequencies (lOB - 11 BMHz)
with 10.7MHz IF.
The dual gate MOSFET provides a high
degree of isolation from prescaler switching
spikes. As shown in Figure 4, the total current

February 1987

TC\l1820S

Figure 3. Cellular Radio Application
consumption of the NE602 and 3SK126 is
typically 3mA. The MOSFET input is from the
emitter of the oscillator transistor to avoid
loading the tank. The Gate 1 capacitance of
the MOSFET in series with the 2pF coupling
capacitor adds slightly to the feedback capacitance ratio. Use of the 22k resistor at Pin
7 helps assure oscillation without upsetting
DC bias.
For applications where optimum buffering of
the tank, or minimum current are not mandatory, or where circuit complexity must be
minimized, the buffers shown in Figure 5 can
be considered.
The effectiveness of the MRF931 (or other
VHF bipolar transistors) will depend on frequency and required input level to the prescaler. A bipolar transistor will generally provide the least isolation. At low frequencies the
transistor can be used as an emitter follower,
but by VHF the base emitter junction will start

4-88

to become a bidirectional capacitor and the
buffer is lost.
The 2N54B4 has an IDSS of 5mA max. and
the 2SK126 has IDSS of 6mA max. making
them suitable for low parts count, modest
current buffers. The isolation is good.

Injected LO
If the application calls for a separate local
oscillator, it is acceptable to capacitivelycouple 200 to 300mV at Pin 6.

Summary
The NE602 can be an effective low power
mixer at frequencies to 500MHz with oscillator operation to 200M Hz. All DC bias is
provided internal to the device so very compact designs are possible. The internal bias
sets the oscillator DC current at a relatively
low level so the designer must choose frequency selective components which will not
load the transistor. If the guidelines mentioned are followed, excellent results will be
achieved.

Application Note

Signetics Uneer Products

Applying the Oscillator of the NE602
in low Power Mixer Applications

AN1982

Vee
0.1

0.001

+---IIH>-i~ ~ESCAl.ER
0.01
L-----1>---'T'---'T'-If--~....---=~-__tH 3SK128 OR EOUlllALENT

Yee

33O/l

lOnF

NEI02

10.7 MHz

K&L38780

12FF"

IF

"1

OR EOUIY

2-10pF

18K

FROM
SYNTHLOOP

FILTER
MY2IOS

OREQUIV

NOTES:

• Permits impedance match of NE602 output, ie: 1.5K//3pF to 3.5K filter impedance .
.. Choose for impedance match to next stage.

Figure 4

OK"

0.01

~

22K

PRESCALER

2FF

0.01

0-1f-__-t---+--t~

MRF931

0--lf'-.--~~--I

PRESCAl.ER

47K

47K

2N5484

NOTE:
• 2K or as necessary for current limits or prescaler impedance match.

Figure 5

February 1987

OK"

1001(

OK"

4-89

1

3SK128

NE612

Signetics

Double-Balanced Mixer and
Oscillator
Product Specification
Linear Products
DESCRIPTION

FEATURES

The NE612 is a low-power VHF monolithic double-balanced mixer with onboard oscillator and voltage regulator. It
is intended for low cost, low power
communication systems with signal frequencies to 500MHz and local oscillator
frequencies as high as 200MHz. The
mixer is a "Gilbert cell" multiplier configuration which provides gain of 14dB or
more at 49MHz.

•
•
•
•
•

The oscillator can be configured for a
crystal, a tuned tank operation, or as a
buffer for an external L.O. Noise figure at
49MHz is typically below 6dB and makes
the device well suited for high performance cordless telephone. The low
power consumption makes the NE612
excellent for battery operated equipment. Networking and other communications products can benefit from very low
radiated energy levels within systems.
The NE612 is available in an 8-lead dual
in-line plastic package and an 8-lead SO
(surface mounted miniature package).

PIN CONFIGURATION

Low current consumption
Low cost
Operation to 500MHz
Low radiated energy
Low external parts count;
suitable for crystal/ceramic filter
• Excellent sensitivity, gain, and
noise figure

APPLICATIONS
•
•
•
•
•
•
•
•

Cordless telephone
Portable radio
VHF transceivers
RF data links
Sonabuoys
Communications receivers
Broadband LANs
HF and VHF frequency
conversion

BLOCK DIAGRAM

September 13, 1985

4-90

853-0391 80472

Signetics Linear Products

Product Specification

Double-Balanced Mixer and Oscillator

NE612

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

o to
o to

B-Pin Plastic DIP
B-Pin Plastic SO

ORDER CODE

+70·C

NE612N

+70·C

NE612D

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

RATING

Vee

Maximum operating voltage

TSTG

Storage temperature

TA

Operating ambient temperature range

UNIT

9

V

-65 to + 150

·C

o to

·C

+70

AC/DC ELECTRICAL CHARACTERISTICS TA = 25·C, Vee = 6V, Figure 1
LIMITS
SYMBOL

PARAMETER

TEST CONDITION

UNIT
Min

Power supply voltage range

Vee

Typ

Max
B.O

V

2.4

2.8

mA

4.5

DC current drain
fiN

Input signal frequency

500

MHz

fosc

Oscillator frequency

200

MHz

Noise figured at 49MHz

5.0

dB

-15

dBm

Third-order intercept point at 49MHz

RIN

RFIN

= -45dBm

Conversion gain at 49MHz

14

dB

RF input resistance

1.5

kn

RF input capacitance

CIN

Mixer output resistance

(Pin 4 or 5)

3

pF

1.5

kn

DESCRIPTION OF OPERATION
0.5 to

1'PF I

1.3~H

~

THIRD OVERTONE CRYSTAL

vee

150pF

NE612

1.5 to
44.2~

~
120pF

47pF r-~r---':r-­

INPUT C f g o . 2 0 9 to O.283I-t-------iI--'\IIt.--+1:::10

RL

LINEAR
IF AMPLIFIER
OUTPUT

300

r-~~~---~~~~~~~~~~+-~

L--~""

1nF

BUFFERED

>--.....M~--t------t"9-1FDSCILLATOR
RL OUTPUT
75

~--1----------14-~~~~~,

EMF 1
t"'98MHz

NOTES:
Coli Data
L1: TOKO Me-lOa, 514HNE·150023S14; L=O.078pH
L2: TOKO MG-111, E516HNS·200057; L "" O.OB,uH
L3: TOKO coil set 7P, N1 = 5.5 + 5.5 turns, N2 = 4 turns

November 14, 1986

4·97

Signetlcs Linear Products

FM Front-End

Product Specification

Ie

TDA1574

DC AND AC ELECTRICAL CHARACTERISTICS Vce = V15-4 = 8.5V; TA = 25°C; measured in test circuit (Block Diagram).
unless otherwise specified.
LIMITS
SYMBOL

UNIT

PARAMETER
Min

Typ

Max

Supply (Pin 15)

= V15 - 4
= 115

Vee

Supply voltage

7

16

V

lee

Supply current (except mixer)

16

23

30

mA

Reference voltage (Pin 5)

4.0

4.2

4.4

V

35

V5_ 4
Mixer

V1.2-4
V16, 17-4
116 + 117
NF
NF
EMF11P3

DC characteristics
Input bias voltage (Pins 1 and 2)
Output voltage (Pins 16 and 17)
Output current (Pin 16 + Pin 17)

4.5

V
V
mA

AC characteristics (II = 98MHz)
Noise figure
Noise figure including transforming network
3rd order intercept point
Conversion power gain

9
11
115

dB
dB
dB"V

4(VM(Out) 10.7 MHz)2 RS1
(EMFI 98 MHz)2 x RML

14

dB

12
13

n
pF

Gp

10 log

1
4

Input resistance (Pins 1 and 2)
Output capacitance (Pins 16 and 17)

R1,2-4
C16,17
Oscillator

V7,8-4
VS-4

DC characteristics
Input voltage (Pins 7 and 8)
Output voltage (Pin 6)

1.3
2

V
V

Af

AC characteristics (fose = 108.7MHz)
Residual FM (Bandwidth 300Hz to 15kHz);
de-emphasis = 50"s

2.2

Hz

1.2
3.5

V
V

Linear IF amplifier

V13 - 4
V10-4

DC characteristics
Input bias voltage (Pin 13)
Output voltage (Pin 10)
AC characteristics (fl
Input impedance

= 10.7MHz)

R14-13
C14 - 13

240

300
13

360

n
pF

240

300
3

360

n
pF

27

30

dB

Output impedance
R10-4
C10-4
Voltage gain
GVIF

20 log V10-4
V14-13
T A = -40 to + 85°C

0

dB

V1O - 4RMS
V10-4RMS

1 dB compression point (RMS value)
at Vee = 8.5V
at Vee = 7.5V

900
500

mV
mV

NF

Noise figure
at Rs = 300n

6.5

dB

AGVIF

November 14. 1986

4-98

Signetics Linear Products

FM Front-End

Product Specification

Ie

TDA1574

DC AND AC ELECTRICAL CHARACTERISTICS (Continued) vee = V15 - 4 = 8.5V; TA = 25°C; measured in test circuit
(Block Diagram). unless otherwise specified.
LIMITS
PARAMETER

SYMBOL

Min

Typ

Max

I

UNIT

Keyed AGe

118

DC characteristics
Output voltage range (Pin 18)
AGC output current
at 13 = t/> or
V12-4 = 450mV; V18-4 = Vee/2
at V3_4 = 2V and
V12-4 = 1V; V18-4 = V15-4

V18-4
V18-4

Narrow-band threshold
at V3_4 = 2V; V12 - 4 = 550mV
at V3_4 = 2V; V12 - 4 = 450mV

V18 - 4

-1 18

0.5

25

50

2

Vee- 0.3

V

100

p.A

5

mA

1

V
V

Vee- 0.3

AC characteristics (fl = 98MHz)
Input impedance
4
3

A3-4
C3_4

EMF2RMS

Wide-band threshold (AMS value)
(see Figures 1. 2. 3 and 4)
at V12-4 =0.7V; V18-4=Vee/2; 118=0

-

kn
pF

19

mV

6.0

V

110

mV
mV

Oscillator output buffer (Pin 9)
V9_4

DC output voltage

V9- 4RMS
V9- 4RMS

Oscillator output voltage (AMS value)
at AL = 00
at AL = 75n

25

A9-15

DC ouput impedance

2.5

kn

THD

Signal purity
total harmonic distortion

-15

dBC

fs

Spurious frequencies
at EMF1 = 1V; AS1 = 50n

-35

dBC

Electronic standby switch (Pin 11)
OSCillator; linear IF amplifier; AGC at TA = -40 to + 85°C
V11-4
V11_4

Input switching voltage
for threshold ON; V18_4>Vee-3V
for threshold OFF; V18-4 

4.4

V

4-99

II

Signetics Linear Products

FM Front-End

Product Specification

Ie

TDA1574

IOr---,---,---,---,----,--,

10r---r---r---r---r---r--.

VI8 _.

v18_4

IV)

IV)

~0~0~-L--750~0~~~~60~0~----~700
V 12_4(mV)

Figure 1. Keyed AGC Output Voltage V18-4 as a Function
of RMS Input Voltage V3-4' Measured In Test Circuit
(Block Diagram) at V12-4 = O.7V; 118 = q,

Figure 2. Keyed AGC Output Voltage V18 _ 4 as a Function
of Input Voltage VI2-4' Measured in Test Circuit
(Block Diagram) at V3-4 = 2V; 1,8 = q,

5

118
ImA)
4

I

3

L
I

2

I

1

1

o
o

1

IL

0

10

20

400

30

V3_4 ImV )

Figure 3. Keyed AGC Output Current 118 as a Function
of RMS Input Voltage V3-4' Measured in Test Circuit
(Block Diagram) at V12-4 O.7V; V18-4 8.5V

=

November 14. 1986

500

600
700
VI2_4ImV)

Figure 4. Keyed AGC Output Current 118 as a Function
of Input Voltage V12 _ 4. Measured In Test Circuit
(Block Diagram) at V3_4 = 2V; V,8-4 = 8.5V

=

4-100

Signetics Linear Products

Product Specification

Ie

FM Front-End

TDA1574

10

r-------~~--------~~----------------~--~~----------------------------------------ovcc

SFE

10

18

LINEAR

QHQf-o
l OUTPUT

IF AMPLIFIER

TDA1574

9

1nF

BUFFERED

>----'lMr--If------f-=-iF:----<> g~$~~:TOR
~ Rl

'fasC>

I

~

ANTENNA

Vee

GAIN CONTROLLED

RF PRESTAGE

L-____________~------------------------------------~------------------_o~~~~~

NOTES,
1. Field strength indication of main IF amplifier.
Coli Data:
L1: TOKO MC-108, N1 ,., 5.5 turns, N2 = 1 turn
L2, see Block Diagram

L3,

J

Figure 5. TDA1574 Application Diagram

November 14, 1986

4-101

•

TDA5030A

Signetics

VHF MixerjOscillator Circuit
Product Specification

Linear Products

DESCRIPTION
The TDA5030A performs the VHF mixer,
VHF oscillator, SAW filter IF amplifier,
and UHF IF amplifier functions in television tuners.

FEATURES
• A balanced VHF mixer
• An amplitude-controlled VHF
local oscillator
• A surface acoustic wave filter IF
amplifier
• A UHF IF preamplifier
• A buffer stage for driving an
external prescaler with the local
oscillator signal
• A voltage stabilizer
• A UHF/VHF switching circuit

VHF INPUT 2

DECOUP

7 DECOUP

4

~~~~ ~Ff.aEfp~

1

osc OUTPUT

~~ 'citEfp~

1

SWITCH INPUT

IrN~~~
11 ~~~
IrN~~~ - ._ _ _.....'_0 ~~~::r

VHFDECOUP

1

VHF INPUT

2

IFAMP
DECOUP
IF PREAMP

INPUT

DESCRIPTION

TEMPERATURE RANGE

18-Pin Plastic DIP (SOT-l02A)
20-Pin Plastic SO DIP (SOT-163A)

ORDER CODE

- 25°C to + 85°C

TDA5030AN

- 25°C to +85°C

TDA5030ATD

BLOCK DIAGRAM

NC 6
MIX/IF PREAMP
(UHF) OUTPUT

~~~~ '6'~~~

13 SWITCH INPUT

IrN~~

12

gU~~~T

IfN~~

-'0"1-_ _ _.r-

gU~~T

TOP VIEW

18

18

VHF
LOCAL
OSCILLATOR

15

L

J

BUFFERED
OSCILLATOR
OUTPUT

-t

SAW FILTER
IF AMPLIFIER

I

I

I

13

I

TDA5030A

~

11
VHF
MIXER

~

UHF IF
PREAMPLIFIER

~

5

I

1

D Package

ORDERING INFORMATION

4

N Package
DECOUP

TOP VIEW

APPLICATIONS
• Mixer/oscillator
• TV tuners
• CATV
• LAN
• Demodulator

I
o---! =1

PIN CONFIGURATIONS

!3,'4

!'7

I
7

6

8

9

STABILIZER
AND
SWllCH

I

10

I

12

NOTE:
Pinout is for 18-pin N package.

January 14, 1987

4-102

853·1150 87202

Signetics linear Products

Product Specification

TDA5030A

VHF Mixer/Oscillator Circuit

UHFIVHF
SWITCH

1.5pF

8,

I

I

1nF

1nF
IDCAL OSCILLATOR OUTPUT

18

17

16

II

15

TDA5030

1nF

270

VHF INPUT 0 - - - - - - - '
IF INPUT

o---------____..J

Figure 1. Test Circuit

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

RATING

UNIT

14

V

Vee

Supply voltage (Pin 15)

V,

Input voltage (Pin 1, 2, 4, and 5)

V12

Switching voltage (Pin 12)

-110,11,13

Output currents

10

mA

tss

Storage·circuit time on outputs
(Pin 10 and 11)

10

s

o to
o to

5

V

Vee+0.3

V

TSTG

Storage temperature range

-65 to +150

·C

TA

Operating ambient temperature range

-25 to +85

·C

TJ

Junction temperature

+125

·C

OJA

Thermal resistance from junction to
ambient

+55

·C/W

January 14, 1987

4-103

270

Signetics Linear Products

Product Specification

TDA5030A

VHF Mixer/Oscillator Circuit

DC AND AC ELECTRICAL CHARACTERISTICS

Measured in circuit of Figure 1; Vee
specified.

= 12V;

TA = 25°C, unless otherwise

LIMITS
SYMBOL

UNIT

PARAMETER
Min

Typ

Max

Supply

10

13.2

V

55

mA

Vce

Supply voltage

Icc

Supply current

V12

Switching voltage VHF

0

2.5

V

V12

Switching voltage UHF

9.5

Vee+ 0.3

V

112

Switching current UHF

0.7

mA

470

MHz

9
10
12

dB
dB
dB

42

VHF mixer (including IF amplifier)

fR

Frequency range

NF

Noise figure (Pin 2)
50MHz
225M Hz
300MHz

7.5
9
10

Optimum source admittance (Pin 2)
50MHz
225MHz
300MHz

0.5
1.1
1.2

ms
ms
ms

Input conductance (Pin 2)
50MHz
225MHz
300M Hz

0.23
0.5
0.67

ms
ms
ms

G

GI

CI

Input capacitance (Pin 2)
50MHz

V2-3

Input voltage for 1 % cross-modulation
(in channel); Rp > 1kS"2; tuned circuit
with Cp = 22pF; fRES = 36MHz

50

97

V2-14

Input voltage for 10kHz pulling (in channel) at

Av

Voltage gain

< 300M Hz

2.5

pF

99

dBIIV

100
22.5

dBIIV
24.5

26.5

dB

UHF preamplifier (including IF amplifier)

GI

Input conductance (Pin 5)

0.3

CI

Input capacitance (Pin 5)

3.0

NF

Noise figure

5

V5-14

Input voltage for 1 % cross-modulation (in channel)

Av

Voltage gain

Gs

Optimum source admittance

January 14, 1987

88

90

31.5

33.5
3.3

4-104

ms
pF

6

dB
dBIIV

35.5

dB
ms

Signetics Linear Products

Product Specification

TDA5030A

VHF Mixer/Oscillator Circuit

DC AND AC ELECTRICAL CHARACTERISTICS (Continued)

Measured in circuit 01 Figure 1; Vee
unless otherwise specilied.

= 12V;

TA = 25'C,

LIMITS
UNIT

PARAMETER

SYMBOL

Min

Typ

Max

VHF mixer
YC2-6,7

Conversion transadmittance

5.7

ms

Zo

Output impedance

1.6

k!1

VHF oscillator
IA

Frequency range

520

MHz

Dol

Frequency shift
DoVce = 10%; 70 to 330M Hz

70

200

kHz

Dol

Frequency drift
DoT = 15k; 70 to 330MHz

250

kHz

Dol

Frequency drilt Irom 5sec to 15min after switching on

200

kHz

SAW filter IF amplifier
Za.9

Input impedance
Z10, 11 = 2k!1, 1= 36MHz

Za, 9-10, 11

Transimpedance

Z10,11

Output impedance
Za, 9 = 1.6k!1; 1= 36MHz

340+ j100

!1

2.2

k!1

50+j40

!1

20
20

mV
mV

90

!1

VHF local oscillator buffer stage
V13
V13

Output voltage
RL = 75!1; 1< 100MHz
RL = 75!1; I> 100MHz

Z13

Output impedance
1= 100MHz

RF

--(RF+LO)

January 14, 1987

14
10

RF Signal on LO output; RL = 50!1; VI = 1V; I';;; 225MHz

4-105

10

dB

TDA5230

Signetics

VHF, Hyperband, and UHF
MixerjOsciliator With IF Amp
Preliminary Specification

Linear Products
DESCRIPTION

FEATURES

The TDA5230 consists of three (VHF,
Hyperband, UHF) mixer/oscillators, and
an IF Amplifier Circuit for TV tuner or
communication front end designs. The
integration of these functions within one
IC facilitates the construction of a complex tuner design with higher performance and fewer components than circuitry using discrete transistors.

• Balanced mixer for VHF having a
common emitter input
• Amplitude-controlled oscillator for
VHF
• Balanced mixer for hyperband &
UHF with common base input
• Balanced hyperband & UHF
oscillator
• Balanced mixer for UHF with
common base input
• SAW filter preamplifier with a
75n output impedance
• Buffer stage for drive of a
prescaler with the OSCillator
signal (VHF only)
• Voltage stabilizer for OSCillator
stability

PIN CONFIGURATION

• Band switch circuit

APPLICATIONS
• CATV
• Communication receiver
• TV tuners
• Data communication

ORDERING INFORMATION
DESCRIPTION
24-Pin Plastic DIP (80T-137)

February 1987

TEMPERATURE RANGE

ORDER CODE

-25°C to +80°C

TDA5230D

4-106

D Package
VHFOSC
(BASE IN)
VHFLO.
OUT
VHFOSC
(COLLECT IN)
HYPERBAND
OSCIN
HYPERBAND
OSCIN
UHFOSC
(BASE IN)
UHFOSC
(COLLECT IN)
UHFOSC

VHF IN

22 ~YPERBAND
21 ~YPERBAND

(COLLECT IN)

UHFOSC
(BASE IN)

TOP VIEW

Signetics Linear Products

Preliminary Specification

TDA5230

VHF, Hyperband, and UHF Mixer/Oscillator With IF Amp

BLOCK DIAGRAM

1

4

3

i2

r--

VHF
OSC

HYPERB.

osc

1.1k

i

5

T

0- t V

T

I

I

I

I
I
I

I

I

UHF
OSC

1k

--

~

11m

t

1k

~

9

8

7

I

12

11

TDA5230

r

+12V

r- rr--

~

.......

~

r-

•

~

I

I

-=-

I

-=-

IF
AMPL

~
>
~
IVY IVY VY
1

1

t-

~r

MIXER

MIXER

SWITCH-=-

MIXER

J
VHF

M

1-

5k

5k

24

23

t-

--

I~

ff

~

~L

~

ff

~L

HYPERB.
STAGE

"""-

[(f

IDC STAB +
INTERNAL
BIASINGS

'--

r--

UHF
STAGE

I

22

21

.,!:O

19

18

f7

16

15

14

13

BDOB691S

February 1987

4-107

<
::I:

:n

(J)

<5.
OJ

~

~

U

eD
....

0-

0

:::::J

PO
:::::J

Q.

C

::I:

."

~

X-

eD

""'0
en
Q.
0

....0-

r !l.
-=-

-::'

-:

rC29

~C30

6H

~

10 C27~28 OR C29-3O

I

t

HYBRID

t

I

;:C28

:;::=

117

I

~
::::;;
=r
:;;

r r:u 114

113

S

LI~t-j

I

~C24

L._._

NOTES:
1. LS-L7 is a matching transformer (n=L7/L6=6). Terminated with son, it simulates the impedance of a saw·filter on Pins 11-12.
2. em is the simulated maximum allowable input capacitance of the saw-filter, which is 18pF if the capacitance between the leads to Pins 11 -12 is < 4pF.
3. In the application em, L6 and L7 must be replaced by a saw-filter and an inductance across its input which lunes out the total capacitance between the pins if no
4. This circuit is mounted on the V-H-U p.b.c. number: 3373.

Figure 1. Test Circuit for All Band VHF-UHF Mixer Oscillation IC TDA5230

»

tiLl

I~C231 r

22

3
u

."

C29

(j)

3'

Ie

has been connected.

~

-I

-<
is'
(1)

i')

:;;

~

W

0

0

~

OJ

Preliminary Specification

Signetics linear Products

VHF, Hyperband, and UHF Mixer/Oscillator With IF Amp

TDA5230

Component Values of Circuit in Figure 1
Resistors

R1 =
R2=
R3 =
R4 =
R5 =

47kn
18n
4.7kn
1.2kn
47kn

R6 = 100n
R7 = 22kn
R8 = 22kn
R9 = 2.2kn
R10 = 22kn

R11=1kn
R12 = 2.2kn
R13 = 22kn
R14 = 2.2kn
R15=2.2kn
R16 = 10n (SMD)

C11
C12
C13
C14
C15
C16
C17
C18
C19
C20

C21 = 1nF
C22 = 1nF
C23 = 15pF (N750)
C24 = 15pF (N750)
C25 = 1nF
C26 = 1nF
C27 = 1nF
C28=1nF
C29 = 1nF
C30 = 1nF

Capacitors

C1
C2
C3
C4
C5
C6
C7
C8
C9
C10

=
=
=
=
=
=
=
=
=
=

11lF -40V
1nF
82pF (N750)
1nF
1.8pF (N750)
1.8pF (N750)
1nF
1nF
1nF
1nF

=
=
=
=
=
=
=
=
=
=

12pF (N750)
1nF
1.5pF (SMO)
1.5pF (SMO)
1nF
5.6pF (SMO)
100pF (SMO)
1.5pF (SMO)
1.5pF (SMO)
1nF

Diodes and IC

01 = 669096

02 = 6A482

03 = 669096

04 = 664056

Colis

L1 =
L2 =
L3 =
L4 =
L5 =
wire

2.5\ ¢3
6.5\ <1>4
2.5t 1/>2.5
1.5t 1/>2.5
1.5\ 1/>3
used: 0.4 for

February 1987

L6
L7
L8
L9

=
=
=
=

2t
TOKO 7kN
10t
Mat: 113kN
51lH
2 X 6 t TOKO 7kN
Mat: 113kN
L1 - Ls and 0.1 for L6. L7. and L9

4-109

IC = TOA5230

C31=1nF
C32 = 1nF
CM = 18pF (N750)

CA3089

Signetics

FM IF System
Product Specification

Linear Products

DESCRIPTION
CA3089 is a monolithic integrated circuit
that provides all the functions of a comprehensive FM IF system. The block
diagram ~hows the CA3089 features,
which incllide a three-stage FM IF amplifier /limiter configuration with level detectors for each stage, a doubly-balanced quadrature FM detector and an
audio amplifier that features the optional
use of a muting (squelch) circuit.
The circuit design of the IF system
includes desirable features such as delayed AGe for the RF tuner, an AFC
drive circuit, and an output signal to drive
a tuning meter and/or provide stereo
switching logic. In addition, internal power supply regulators maintain a nearly
constant current drain over the voltage
supply range of +8V to + l8V.
The CA3089 is ideal for high-fidelity
operation. Distortion in a CA3089 FM IF
system is primarily a function of the
phase linearity characteristic of the outboard detector coil.

The CA3089 utilizes a 16-lead dual-inline plastic package and can operate
over the ambient temperature range of
-40°C to + 85°C.

PIN CONFIGURATION
N Package

FEATURES

IF INPUT
BVPASSING

• Exceptional limiting sensitivity:
10llV typo at -3dS point
• Low distortion: 0.1 % typo (with
double-tuned coli)
• Single-coil tuning capability
• High recovered audio: 400mV
typo
• Provides specific signal for
control of interchannel muting
(squelch)
• Provides specific signal for direct
drive of a tuning meter
• Provides delayed AGC voltage
for RF amplifier
• Provides a specific circuit for
flexible AFC
• Internal supply/voltage regulators

IF INPUT
BYPASSING

QUADRATURE
INPUT

TOP VIEW

APPLICATIONS
• High-fidelity FM receivers
• Automotive FM receivers
• Communications FM receivers

BLOCK DIAGRAM

.Fe
OUTPUT

AUOIO
OUTPUT

OEI..AYED
AGe FOR C>-~-~'t-f1

RF AMPl
10K

12

470

TO STEREO
THRESHOLD

lOGIC CIRCUITS

NOTES:
1. All resistor values are typical and in ohms. 00
2. L tunes with 100pF (C) at 10.7MHz

November 14. 1986

~

75 (G,I. EX27825 or equivalent)

4-110

853'0044 86551

Signetics Linear Products

Product Specification

CA3089

FM IF System

EQUIVALENT SCHEMATIC

h

. il

. ~r
II

24
i

!O-..j"

.,
i

j~
~!

iii
'~~ !I
Ii

NOTES:
1. All resistance values are typical and in ohms.
2. All capacitance values are in picofarads.

November 14, 1986

4·111

Product Specification

Signetics Linear Products

CA3089

FM IF System

ORDERING INFORMATION
DESCRIPTION

16-Pin Plastic DIP

TEMPERATURE RANGE

ORDER CODE

-40·C to + 85·C

CA3089N

ABSOLUTE MAXIMUM RATINGS
SYMBOL

Vec

PD

RATING

UNIT

DC supply voltage:
between terminals 11 and 4
between terminals 11 and 14

PARAMETER

18
18

V
V

DC current (out of Terminal 15)

2

mA

600
derate linearly
6.7

mW/·C

Device dissipation:
up to TA = 60·C
above TA = 60·C

...

mW

TA

Operating ambient temperature range

-40 to +85

·C

TSTG

Storage temperature range

-65 to +150

·C

TSOLD

Lead soldering temperature
(10sec max)

+300

·C

November 14, 1986

4-112

Product Specification

Signetics Linear Products

CA3089

FM IF System

DC ELECTRICAL CHARACTERISTICS TA = 25°C, V+ = 12V, unless otherwise specified.
LIMITS
SYMBOL

PARAMETER

TEST CONDITIONS

UNIT
Min

Typ

Max

No signal input, non-muted

16

23

30

mA

Static (DC) Characteristics
111

Quiescent circuit current

DC Voltages'
V1

Terminal 1 (1 F input)

No signal input, non-muted

1.2

1.9

2.4

V

V2
V3

Terminal 2 (AC return to input)
Terminal 3 (DC bias to input)

No signal input, non-muted
No signal input, non-muted

1.2
1.2

1.9
1.9

2.4
2.4

V
V

V6
V7
V10

Terminal 6 (audio output)
Terminal 7 (AFC)
Terminal 10 (DC reference)

No signal input, non-muted
No signal input, non-muted
No signal input, non-muted

5.0
5.0
5.0

5.6
5.6
5.6

6.0
6.0
6.0

V
V
V

10

25

jJ.V

Dynamic Characteristics
VI(UM)

Input limiting voltage (-3dB pOint)3
AMR AM rejection (Terminal 6)'

Va

Recovered audio voltage (Terminal 6)3

THO
THO

Total harmonic distortion: 1
Single tuned (Terminal 6)3
Double tuned (Terminal 6)'

S + N/N
MUIN

Signal plus noise-to-noise ratio (Terminal 6)3
Mute input (Terminal 5)

MUOUT

Mute output (Terminal 12)

MTR

Meter output (Terminal 13)

AGC

Delay AGC (Terminal 15)

THO

Double tuned (Terminal 6)'

VIN = 0.1V, fa = 10.7MHz,
fMOD = 400Hz, AM Mod = 30%

= 400Hz, VIN = 0.1
Deviation = ± 75kHz, VIN = 0.1V
V5 = 2.SV
VIN = 50/-IV
VIN = OV
VIN = 0.1V
VIN = 500/-IV
VIN = OV
VIN = 0.01V
VIN = 10/-IV
fMOD = 400Hz
VIN = 0.1

45

55

400

500

600

mV

0.5
0.1

1.0

%
%

fMOD

60
50

dB

70
70

dB
dB
0.5

4.0
2.5
1.0

3.5
1.5
0.7
0.5

4.0

V
V
V
V
V

5.0

V
V

0.1

%

NOTES
1. THO characteristics and audio level are essentially a function of the phase and Q characteristics of the network connected between Terminals 8, 9,

and 10.
2. Test circuit Figure 1.
3. Test circuit Figure 2.
4. Test circuit Figures 1 and 2.

November 14, 1986

4·113

II

Signetics Linear Products

Product Specification

FM IF System

CA3089

TEST CIRCUITS

;t!j~iI

I
I
I

v·'

12V

INPUT

I
C1

I

I--h·
I
I

SIGNAL
VOLTAGE

100pF

I
I 5.

SIGNAL
INPUT
VOLTAGE

NOTES:
1. L tunes with 100pF (e) at 10.7MHz.
2. AU resistor values are typical and in ohms.
3. 00 (unloaded) ~ 75 (G.t automatic mfg. div. EX27825 or equivalent).

Figure 1. Test Circuit Using a Single-Tuned Detector Coli
NOTES:
AU resistor values are typical and in ohms.
T: Prj-Qo (unloaded) ~ 75 (tunes with 100pF (el) 20 t of 349 on 7/32' dia.
form) Sec. - Q (unloaded) = 75 (tunes with 100pF (C2) 20 t of 349 on 7/32'
dia. form)
kQ (percent of critical coupling) > 70%
(Adjusted for coil voltage Vc"" 150mV)
Above values permit proper operation of mute (squelch) circuit I E' type slugs,
spacing 4mm

Figure 2. Test Circuit Using a Double-Tuned Detector Coil

November 14, 1986

4-114

Signetics Linear Products

Product Specification

FM IF System

CA3089

TEST CIRCUITS
v+

.12Y

,.."

INPUT

NOTES:
All resistor values are typical and in ohms.
1. Waller 4SN3FIC or equivalent.
2. Murata SFG 10.7mA or equivalent.
3. Rs will affect stability depending on circuit layout. To increase stability Rs is decreased.
Range of Rs is 330
4. L tunes with 100pF (C) at 10.7MHz 00 unloaded ~ 75 (G.I. EX27825 or equivalent).
Performance data at fa = 98MHz, fMOD = 400Hz, deviation = ± 74kHz.
± 74kHz.
- 3dB limiting sensitivity
2JJ,V (antenna level)
20dB quieting sensitivity
1JiV (antenna level)
SOdB quieting sensitivity
1.511V (antenna level)

Figure 3. Typical FM Tuner With a Single-Tuned Detector Coli

SYSTEM DESIGN
CONSIDERATIONS
The CA3089 is a very high gain device and
therefore careful consideration must be given
to the layout of external components to
minimize feedback. The input bypass capacitors should be located close to the input
terminals and the values should not be large

to match this impedance. The value of the
input termination resistor should be as low as
possible without degrading system operation.
The lower the value of this resistor the
greater the system stability. An input terminating resistor between 500 and 1000 is recommended.

nor should the capacitors be of the type
which might introduce inductive reactance to
the circuit. An example of good bypass capacitors would be ceramic disc with values in
the range of 0.01 to O.OS/lF.
The input impedance of the CA3089 is approximately 10,0000. It is not recommended

TYPICAL PERFORMANCE CHARACTERISTICS
Muting Action, Tuner AGC
(Tuning meter output as a
function of input signal voltage.)

"'"
Z
0-

"

U>

AFC Characteristics
(Current at Terminal 7 as a
function of change in frequency.)
125

~~:'~~~AT~~~~::~~~ET(~ ~~~ T2StC
TEST CIRCUIT

0

en

1:1

2i
c i< -20
::>"

":e

....

-

TUNER AGe DC

........

~~~~~::L

~

J.
Y

~ ~ -40

"~ -50

j /'"

;:

::>

:e -60
1

10

10K

~
pA

25

a

Z

w -50

0:

/

a:

::>

-75

" -100

1

-125

V
-100

100K

V

/

0-

2

,

~-

V
1/

i!: -25

-50

a

50

100

CHANGE IN FReQUENCY (ll.f)- kHz
0P0937OS

November 14, 1986

50

~;~~:"E~E~::;:T~:~ ~~v== 2~oC

(T
SEe TEST CIRCUIT fiGURE 3

0
0-

"

\

75

0:

3 0

NO. 13 METER CIRC~X(33K 11 TO GNO)
{RIGHT CO-ORDINATE}

100
1K
INPUT SIGNAL - JJ.V

'~"

~

~
VOLTAGE ~.\.
AT TERMINAL

a:0

i!:

U>

>

1",,(

>0

00:

I":;I

5

0

AJO. 15'
(RIGHT CO-ORDINATE)

00-

~ '" -30

6

, ( RECOVERED AUDIO
FROM fULL OUTPUT
(LEFT CO-OROINATE)-

CD'"
1:1 IX -10

100

SEe FIGURE 3

OP09380S

4-115

MC3361

Signetics

Low Power FM IF
Objective Specification

Linear Products

DESCRIPTION

FEATURES

The MC3361 is a monolithic low-power
FM IF signal processing system consisting of an oscillator, mixer, limiting amplifier, quadrature detector, filter amplifier,
squelch, scan control and mute switch. It
is intended for use in narrow band FM
dual conversion communications equipment. The MC3361 is available in a 16lead, dual-in-line plastic package and
16-lead SO (surface-mounted miniature
package).

• 2_0V to B.OV operation
• Low current: 4.2mA typ at
Vee = 4.0Voc
• Excellent sensitivity: 2.0jlV for
-3dB limiting typ
• Low external parts count
• Operation to 60MHz

PIN CONFIGURATION

February 1987

GND

MUTE

SCAN
CONTROL

MIXER
OUTPUT

Vee

4

U~~IW

5

oeCOUPUNG
UMITER

I~~

• Cordless telephone
• Narrow band receivers
• Remote control

SQUELCH
IN

FILTER
OUTPUT

FILTER
INPUT

4-116

RECOVERED
AUDIO

RF
INPUT
GND
AUDIO
MUTE

1

~8"rJ1!ROL
fN FILTER AMP OUT
1.0!'F

1-.....#>1'--:-1+ I-<> FILTER AMP IN
20k

8.21<

1-"""'''1'-......-0

I
I

I

J.

AF OUTPUT

0•Ol !'F

I
L._:.
___ j IOUADCOIL
OUADCOIL
TOKOTYPE
RMC-2A6597HM

February 1987

4·118

Signetics

NE/SA604
Low Power FM IF System
Product Specification

Linear Products
DESCRIPTION

FEATURES

The NE/SA604 is a monolithic low power FM IF system incorporating two limiting intermediate frequency amplifiers,
quadrature detector, muting, logarithmic
signal strength indicator, and voltage
regulator. The NE/SA604 is available in
a 16-lead dual in-line plastic and Cerdip
packages and 16-lead SO (surfacemounted miniature package).

• Low power consumption: 2.3mA
typical
• Logarithmic Received Signal
Strength Indicator (RSSI) with a
dynamic range in excess of 90dB
• Separate data output
• Audio output with muting
• Low external count; suitable for
crystal/ceramic filters
• Excellent sensitivity: 1.5J.1V across
input pins (O.27J.1V into 50.11
matching network) for 12dB
SINAD (Signal-to-Noise and
Distortion ratio) at 455kHz
• SA604 meets cellular radio
specifications

PIN CONFIGURATION
D, F, N Packages
IF AMP

DECOUPLING
IF AMP
OECOUPLtNG

MUTe INPUT

3

RSSI OUTPUT

5

AUDIO OUTPUT

6

DATA OUTPUT

7

IF AMP
OUTPUT

LIMITER
INPUT

LIMITER
OECOUPUNG
10

QUADRATURE

INPUT

9

8

LIMITER
OECOUPUNG

LIMITER
OUTPUT

TOP VIEW

APPLICATIONS
• Cellular Radio FM IF
• Communications receivers
• Intermediate frequency
amplification and detection up to
15MHz
• RF level meter
• Spectrum analyzer
• Instrumentation

BLOCK DIAGRAM

November 4, 1985

4-119

853-0395 81127

Product Specification

Signetlcs Linear Products

NEjSA604

Low Power FM IF System

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE

o to
o to
o to

16-Pin Plastic DIP
16-Pin Plastic SO
16-Pin Cerdip

ORDER CODE

+70·C

NE604N

+70·C

NE604D

+70·C

NE604F

16-Pin Plastic DIP

-40·C to + 85·C

SA604N

16-Pin Cerdip

-40·C to + 85·C

SA604F

16-Pin Plastic SO

-40·C to + 85·C

SA604D

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

RATING

UNIT

Vee

Maximum operating voltage

9

V

TSTG

Storage temperature range

-65 to + 150

·C

TA

Operating ambient temperature range
NE604
SA604

o to +70
-40 to +85

·C
·C

DC ELECTRICAL CHARACTERISTICS
SYMBOL

Vee

TA = 25·C; Vee

PARAMETER

= + 6V,

unless otherwise stated.

TEST CONDITIONS

MIN

TYP

4.5

Power supply voltage range
DC current drain
Mute switch input threshold
(on)
(off)

MAX

UNIT

8.0

V

2.7

mA

1.0

V
V

1.7

AC ELECTRICAL CHARACTERISTICS TA = 25·C; Vee = + 6V, unless otherwise stated. RF frequency = 455kHz; RF
level = -47dBm; FM modulation = 1kHz with+ 8kHz peak deviation. Audio output with
C-message weighted filter and de-emphasis capacitor.
SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

-90

dBm

Input limiting - 3dB

Test at Pin 16

AM rejection

80% AM 1kHz

30

After C filter and de-emphasis
capacitor

80

100

mVRMS

250

350

mVRMS

12

15

Recovered audio level
Recovered data level
SINAD sensitivity
THD

Total harmonic distortion

SIN

Signal-to-noise ratio
RSSI output

RF level- 97dBm

dB

dB

-35
No modulation for noise

70

R4 = 100kn
RF level = -97dBm
RF level = -47dBm
RF level = 3dBm

0
2.0
4.0

RSSI range

R4

RSSI accuracy

R4

= 100kn
= 100kn

dB
75

dB
400
2.6
5.0

mV
V
V

Pin 5

90

dB

Pin 5

± 1.5

dB

IF input impedance

1.5

kn

IF output impedance

1.0

kn

Limiter input impedance

1.5

kn

Quadrature detector data output impedance

50

Muted audio output impedance

November 4, 1985

kn
50

4·120

kn

Signetics Linear Products

Product Specification

low Power FM IF System

NEjSA604

TYPICAL APPLICATION

kHz IF

NE604 TEST SETUP

NE604 TEST CIRCUIT

RSSIOUTPUT

B

November 4, 1985

4-121

Product Specification

Signetics Linear Products

NEjSA604

Low Power FM IF System

NE604 TEST CIRCUIT

=
--,

, - -......- - - , Q

20 LOADED

I

I F,
I

I

L-*:-l
DATA
OUTPUT

MUTE
INPUT

Vee

RSSI
OUTPUT

NOTES:

C1 10nF +80-20% 63V K10000-Z5V Ceramic
C2 1OOnF ± 10% SOV Polyester
C3 1OOnF ± 10% SOV Polyester
C4 1OOnF ± 10% 50V Polyester
C5 1OOnF ± 10% SOV Polyester

C6 10pF ± 2% 10DV NPO Ceramic
C7 1QOnF ± 10% SOV POlyester
CB 1OOnF ± 10% SOV Polyester

C9 15nF ± 10% SOV Polyester
G10 150pF±2% 100V N1500 Ceramic

ell 1nF ± 10% 1DOV K2000-Y5P Ceramic
C12 6.8uF±20% 25V Tantalum
F1 455kHz Ceramic Filter Murata SFG455A3
F2 455kHz IF Filter A2S49
A1 SH1± 1% 1/4W Metal Film
R2 1500n ± 1 % 1/4W Metal Film
RS 1500,Q±5% 1/BW Carbon Composition
R4 100kn±1% 1/4W Metal Film

Figure 1. NE604 Test Circuit and Parts List

DESCRIPTION OF OPERATION
The NE/SA604 is comprised of five subsystems for IF signal processing. These subsystems, two IF limiting amplifiers, quadrature
detector, audio mute, and logarithmic signal
strength, can be configured to satisfy many
high-performance or low-power systems objectives. Internal temperature compensated
bias regulation completes the circuitry. Taken
together, the SA604 exceeds the demanding
technical requirements for cellular radio.

November 4, 1985

Figure 2 shows the equivalent circuits of the
NE/SA604.

Limiting Amplifiers
The NE/SA604 has two independent limiting
IF amplifiers. The first has a gain of 30dB.
The second has 60dB gain. Both have 1.5k
nominal input impedance and 15MHz bandwidth. The output impedance of the first
limiter is approximately 1kQ. These impedances permit direct interface with popular
ceramic filters such as the SFU455. On the
surface, the 1k output of the first limiter would
not seem correct. However, approximately

4-122

6dB insertion loss is required between limiter
stages to optimize the linearity of the signal
strength indicator. The impedance mismatch
has little effect on passband. Use of an
interstage filter reduces wide·band noise. A
DC blocking capacitor or L/C filter can also
be used.
As the signal frequency increases, the 90dB
total gain can become a source of instability.
Figure 3 shows the limiters as a closed-loop
system with stray capacitance and the equivalent AC input impedance setting the loop
gain.

Signetics Linear Products

Product Specification

NE/SA604

Low Power FM IF System

ADJUST FOR 6 dB INSERTION
LOSS RELATIVE TO THE 1 K
SOURCE (PIN 14) AND THE 1.SK LOAD (PIN 12) ......

,--"'Y<:'v---.,

Figure 2. Equivalent Circuit

eSTRAY

~------~~------l

rr~~
"::'"

"':'"

-=-

-=-

-=-

Figure 3. Considerations for Stability

November 4, 1985

4-123

The equivalent AC attenuation factor from the
output to the input must be greater than 90dB
or oscillation can occur. The input impedance
of the device is nominally 1.5k. The stray
layout capacitance is a frequency-dependent
impedance so that as the frequency of operation or the value of stray capacitance increases. the output-to-input attenuation factor decreases. Keep stray capacitance low by
using good RF layout technique. Sockets
should be avoided above 455kHz.
Good RF layout is the proper way to avoid
instability. However, if system constraints require, stability can be achieved by only using
one of the limiting amplifiers, or by adding a
resistance, RIN, which will increase the attenuation factor.

Procuct Specification

Signetics linear Products

Low Power FM IF System

NEjSA604

455 kHz
Q
20

=
I" --,

I
I

L

~ l00nF

a. Cellular Radio Configuration

,.

NE804 1.F.INPUT (~V) (15OO!l)
10

100

lOOK

10.

...
4V

0

~:!l
..i~=
.. "z

""'

"C2

3V

ila!c

!J0o ....
!J;~

I~~

!;~l!

o~=
ot+

1

2V

....

~e.
c

1V

-80

-120

-100

-80

....

....

NE602 RF INPUT (dBm) (SOH)

b. Cellular Circuit Performance
Figure 4

November 4, 1985

4-124

-20

II

~:-:-l

Product Specification

Signetics Linear Products

Low Power FM IF System

Adding an input resistor is an easy way to
reduce the attenuation factor, but may make
correct termination of interstage filters difficult
or impossible. At 455kHz instability should not
be a problem if reasonable RF layout is used.

NEjSA604

c,
VIN>---i

1-..-+.....----<.---.---4- VOUT
I

RPul

RPL

I
I

Quadrature Detector
The detector of the NE604 is a four quadrant
multiplier of the Gilbert cell type. It can be
used for frequency or amplitude demodulation. Figure 4 indicates a typical quadrature
FM configuration. Fully limited in-phase signal
is applied to the multiplier internally. 90°
phase shift is accomplished with the L/C
tuned circuit connected directly to Pin 8 and
capacitively to Pin 9. Because of the DC bias
of the NE604, the phase shift network must
be returned to ground through a low impedance capacitor. Recovered signal is continuously available at Pin 7 or on a switched basis
at Pin S.
The quadrature coil or crystal/ceramic discriminator affects three system parameters:
bandwidth, linearity, and detected Signal amplitude. Figure 6 shows three quadrature
curves.

EQUATION
~C1

Your
VIN

1
- - - (1

RPLI I RPU

Q

':"w

.1w

+ ]2Q- ) +
'''0

',----<>----<> ~~:?UT
tOOK

Figure 7. Synchronous AM Detection

Audio Mute
An electronic switch permits muting or
squelch of one of the demodulated outputs.
The data (unmuted output) and audio (muted
output) both have 50kn output impedance
and their detected signals are 180 degrees
out of phase with each other. The mute input
(Pin 3) has a very high impedance and is
compatible with three and five volt CMOS and
TTL levels. Little or no DC level shift occurs
after muting when the quadrature detector is

adjusted to the IF center frequency. Muting
will attenuate the audio signal by more than
60dS and no voltage spikes will be generated
by muting.

Signal Strength Indicator
The logarithmic signal strength indicator is a
current source output with maximum source
current of 50pA. The signal strength indicator's transfer function is approximately 10pA
per 20dB and is independent of IF frequency.

The interstage filter must have a 6dS insertion loss to optimize slope linearity.
There is some temperature dependence to
the signal strength output. Figure 8 shows the
characteristic. Two suggested lead circuits
are shown to improve linearity in critical
applications. For cellular radio applications
use of either technique and the SA604 device
(-40°C to + 85°C) will assure compliance with
ASSI criteria.

SAlNE604

10K

':'

NORMALIZE SLOPE
WITH THIS RESISTOR
:0;;;5000 PPMfC
TEMPERATURE SENSOR
':' 1.51<0 NOMINAL

a. Temperature-Compensated RSSI Circuits
Figure 8. Signal Strength

November 4, 1985

4·126

b.

Signetics Linear Products

Product Specification

Low Power FM IF System

NE/SA604

73.8
73.6

./

_ 73.4
ID

:!!.

z

~
0
~

~

II:

z

iii

./
./a

72.8

/

72.6
72.4

72.2

~

100

./

-40

RL:= lOOK!l
A=-113dBm=2.7p.V

,.

---

./

73.2

0

;:
u 73.0

illa:

IU"

40

80

120

TEMPERATURE ("C)

lK

1500n INPUT SIGNAL STRENGTH (p.V)

c. RSSI vs Signal Strength
Figure 8 (Continued)

34.5
34.0
33.5
_

33.0

ID

:a
~

~
:E

32.5

n

Figure 9. NE/SA604 Signal-To-Noise Ratio

,

75

" ""-

31.0

.s

30.0

"

o

:ilss
..........

29.5
29.0
-40

50

........ 100.

40

80

In

45

/

/
,r/
-40

120

40

80

120

TEMPERATURE ("C)

TEMPERATURE ("C)

Figure 10. NE/SA604 AM Rejection vs Temperature

November 4, 1985

,/

is

........

/

1/

585

S
Oao

...... ~

< 30.5

./

>70

"-

31.5

Temperature

80

\.

32.0

VB

Figure 11. NE/SA604 Audio Output

4-127

VB

Temperature

•

Signetics Linear Products

Product Specification

Low Power FM IF System

NEjSA604

2.S

340

L.n.

320

P""

300

i

v

2S0

!5 260
::5 240
~c

200
lS0
160

V

ld'

V

V

~

1.6

so

40

,/

/

-40

120

Figure 12. NE/SA604 Data Output vs Temperature

S.sv

--

2.6

...... ~ ~

1ffi

4.SY-

""I'"
so

~

2.0

~

G
~

it

~

m66.S

:!!.

i!!

i

~cc=4.SV

i
so

40
TEMPERATURE (OC)

Figure 14. NE/SA604 SINAD vs Temperature and

67.0

Vcc=6.0V

-40

120

TEMPERATURE (OC)

67.5

-

Vee =8.5V

2.2

II:

I"

40

2.4

a:

~ ...

-40

120

Figure 13. RSSI vs Temperature

6.0;-

10

so

40
TEMPERATURE (OC)

TEMPERATURE (OC)

16

V"

/

2.0

1.S

I-- fa

;:J'

/

~ .2.2

/'

-40

,/"

2.4

. .f

220

~

2.6

Figure 15. SA604 Supply Current vs Temperature

VCC

-89.5

[,

'c\,.
-90.0

"'

66.0

t'-.....

"'-.,

f'..

,

"

i- 91 .0
:!!. -91.5

,

"'~ -92.0

40

60

i'..

...I

'tI...

~ -92.5

........

-93.0

...........

-93.5

I'"rtJ

65.0

"

1

...I

"-

65.5

-40

"'

-90.5

~

-94.0
-40

120

0

40

80

- ro
120

TEMPERATURE (OC)

TEMPERATURE (OC)

OPOO31OS

Figure 16. NE/SA604 Muting vs Temperature

November 4, 1985

Figure 17. NE/SA604 limiting RF Level vs Temperature

4-128

Signetics Linear Products

Product Specification

Low Power FM IF System

NEjSA604

5.2
5.0
4.8
4.6

;£

4.4

iii 4.2

'"a:

/

4.0
3.8
3.6
3.4
3.2

V

V

~

V

~

-

-41

kl

/~

-4'

1/

-43

-44

iii'

~ -45 ~
~

-46

/

\
~

.....

-47

/
./

-48

if
40

80

-40

120

Figure 18. NE/SA604 Large-Signal Uncompensated
RSSI Voltage vs Temperature

2.7

r::t'

2.5

--

r-

8.5V

.
'" ...
. rf
2.3

~'I'

!!1

....
....

'"

2.1

'.0
1.9

~

If

1\

I~

~

,.0

8.5V

-~

./

:> 140
.5-

...,

6.0V

i

120

,...... a-

80

4.5V

80

40

/

~

I~

//

./ ~/
V...... a
~
..."

80

,.0

-40

Figure 20. NE/SA604 Supply Current vs
Temperature and Voltage

4.5V

-:/'1'

20
40

A

~ 6.0'l ;jJ

a: 100
"U

i'

/

160

40

80

,.0

TEMPERATURE (OC)

TEMPERATURE (Oe)

November 4, 1985

80

180

. . .V

-40

40

'00

"CJ

<.> 2.4

::I!

\

J

Figure 19. NE/SA604 Total Harmonic
Distortion vs Temperature

-a.-

!I

....
z

\

TEMPERATURE (Oe)

TEMPERATURE (Oe)

<"
.5-

-

1\

I

-49
-40

2.6

.....

/

OP00350$

Figure 21. Small-Signal RSSI vs Temperature and Voltage

4-129

•

Signefics

AN199
Designing With the NE/SA604
Application Note

Linear Products

INTRODUCTION
The NE/SA604 represents a new standard of
performance in low power FM IF integrated
circuits. Originally designed for cellular radio
applications, the 604 is also well suited to
other radio frequency circuits where good
performance and low power consumption are
the important design considerations. When
used with its companion double-balanced
mixer, the NE/SA602, a low power system
solution for the cellular radio and other RF
applications is realized (Reference 1).
Figures 1 and 2 show the device pin-out and
a functional diagram of the 604. The device
provides an IF amplifier, quadrature detector,
received signal strength indicator (RSSI), and
mute circuit. Two detector outputs are provided for audio and data information with the
audio output being controlled by the mute
circuit.

be found in Reference 2. The detected audio
appears at the data terminal (Pin 7) and, via
the mute circuit, al the audio (Pin 6) terminal.
The cellular radio specifications call for a
logarithmic signal strength indicator accurate
within 3dB over an 80dB dynamic range. The
604 meets this requirement with an effective
technique. A sample current corresponding to
the output of each IF stage is fed to a
summing amplifier. The output of this amplifier provides a current source which is reflected by a current mirror. The current mirror
output that appears on pin 5 provides the
logarithmic RSSI information. It is usable over
a 90dB dynamic range with 1.5dB accuracy.
Typically, a 100k.l1 resistor is used to convert
the RSSI current to a voltage which is logarithmically proportional to the received signal
strength.

PACKAGING
CIRCUIT OVERVIEW
The IF amplifier consists of five differential
stages with a total gain of about 90dB.
Provision is made for an external inter-stage
filter to reduce broadband noise and increase
receiver selectivity. The differential input to
the first IF section appears at Pins 15 and 16.
One pin is usually AC-coupled to ground (Pin
15) with Pin 16 used as the" high" input. The
first IF section has a typical gain of 40dB with
its output appearing on Pin 14. Similar to the
first IF section, the second section uses a
differential input appearing at Pins 12 and 11,
with Pin 11 usually AC-coupled to ground.
The five stages are identical and anyone may
go into limiting, depending on the RF input
level.
The interstage filter can be ceramic, crystal,
or an LC circuit. RSSI tracking is optimized
when the filter circuit loss is 6dB. The output
impedance of both amplifier sections (Pins 14
and 9) is about 1k.l1. For convenience, an
"L" pad circuit showing 6dB loss is shown in
Figure 3. This circuit allows observation of the
RSSI response without using a filter.
The quadrature detector multiplies two IF
signals to produce the audio output. One of
the IF signals is differentially phase shifted by
an external quadrature tank or discriminator
circuit connected between Pins 8 and 9
(Figure 4). The second IF Signal is fed to the
other detector input internally. Figure 5 shows
the desired phase/frequency response of the
quadrature-tuned circuit. A detailed mathematical explanation of detector operation can
February 1987

Both the NE/SA604 and its companion double balanced mixer, the NE/SA602, are available in either the plastic dual-in-line "DIP" or
surface mounted "SO" packages. The NE
prefix specifies a 0 to+ 70°C operating temperature range while SA specifies-40
to+ 85°C operation. The extensive temperature data presented in this application note
pertain to both the SA and NE devices.

TYPICAL APPLICATIONS
Figure 6 is a simplified schematic diagram of
the 604 which details the internal circuitry
adjacent to the device's pins. This should
help the designer match impedances to external circuitry. Figure 7 shows the schematic
diagram of a typical test circuit using the 604
and 602.
The quadrature tuned circuit (F3) shifts the
phase of the IF signal as shown in Figure 5.
Low distortion demodulation is obtained if the
IF Signal deviation is restricted to the linear
portion of the S-curve. There are three variables affecting quadrature linearity: circuit Q,
deviation, and IF frequency. If the deviation is
increased, the Q must be decreased for a
given degree of linearity. The circuit Q will
also affect the demodulated signal level. A
higher Q will yield a higher audio output from
the quadrature detector since the phase shift
will be greater for a given deviation. The
quadrature Q must be optimized for a given
frequency deviation, IF frequency, and desired linearity. A loaded Q of about 20 is

4-130

typical for narrow band FM applications using
a 455kHz IF.
The supply voltage for the 602/604 pair can
range from 4.5 to 8V. Optimum overall performance is realized at 6.0V for the device pair.
Several operation parameters are plotted for
supply voltage as well as temperature.
Quadrature detector linearity can be affected
by temperature variations. LC circuit resonances will drift as the coil and capacitor
values change with temperature. This effect
becomes more critical with increased circuit
Q. If wide temperature variations are expected, careful choice of circuit components
can minimize this effect. Most inductors have
positive temperature coefficients (increase of
inductance with increase of temperature). If a
negative coefficient capacitor is chosen to
compensate the inductor, the resonant frequency will track over temperature.
Since a bipolar current source is used to
provide the RSSI function, the current will
change with temperature. An increase in
temperature will result in an increase in RSSI
indication (Figure 8, uncorrected response).
The circuit shown in Figure 9 will "smooth"
the response over temperature by dropping
the load impedance presented to Pin 5 as
temperature increases (Figure 8, corrected
response).
All the major performance parameters of the
604 are shown in Figure 10. Figure 11 illustrates a typical test set-up for measuring
many of the discussed parameters. Figures
12 to 25 provide a comprehensive guide to
604 performance over temperature and "~er
variables.

USE AS A FIELD STRENGTHI
RF VOLTMETER
As stated earlier the RSSI function is usable
over a 90dB dynamic range. This function
taken alone can provide a useful RF voltmeter function. The circuit in Figure 26 can be
used as a field strength or RF voltmeter
application. A linear readout device can be
calibrated directly in decibels or logarithmically for power, current, or volts.

USE AS AN AM SYNCHRONOUS
DETECTOR
The 604 can also be used as an AM envelope
detector. The IF signal is fed to both the 604,
as in the FM application, and to an additional

Signetics Linear Products

Application Note

Designing With the NEjSA604

linear IF amplifier (Figure 27). The linear
amplifier then feeds the quadrature detector
which mixes with the AM limited carrier and
demodulates the envelope. 1 % THD is obtainable with this technique with a 90% AM
modulated signal.

AN199

detector then acts as the product detector.
With the addition of a simple switching array,
a single 604 can be used for FM, AM, or SSB
detection in a communications receiver!

IF AMP
INPUT
IF AMP
DECOUPLING
IF AMP
OUTPUT

IF AMP
DECOUPLING

GND

REFERENCES
USE AS A PRODUCT
DETECTOR
Figure 28 shows how the 604 can be used as
a product detector for SSB or DSB. In this
case the LO is applied to the 604 IF amplifier
and an external linear IF amplifier is used for
the SSB or DSB signal. The 604 quadrature

LIMITER
INPUT
LIMITER
DECOUPLING
LIMITER
DECOUPLING
LIMITER
OUTPUT

1. Zavrel, R.: Signetics AN198 Designing With
the SAINE 602, December, 1984.
2. Hayward, W.: Introduction to Radio Frequency Design, 1982, Prentice-Hall.
Written by Bob Zavrel

QUADRATURE
INPUT

TOP VIEW

Figure 1. Pin Configuration

II",'
~

Figure 2. Block Diagram

February 1987

4-131

.
'}

Signetics Linear Products

Application Note

AN199

Designing With the NEjSA604

UK

3K

14,-,

~

12,-,
SAINE&04

)

SAlNE604

Figure 3. 6dB "L" Pad

Figure 4. Quadrature Network

Figure 5

February 1987

4-132

Application Note

Signetics Linear Products

AN199

Designing With the NE/SA604

•
Figure 6. Application Demonstration Board

February 1987

4-133

:;'

,',1

Signetics Linear Products

Application Note

Designing With the NE/SA604

AN199

20/,

47 pF
220pF
O.1IlF
10nF

C1
C2

C3
C4

2%
10%
80%

100 V
100V
SOV
63V

N750 Ceramic
N750 Ceramic

Polyester

Kl0000 - 25X Ceramic

20%
~F±

C5

0.1

C8
C7
C8
C9

5.6 pF ± 25%

C10
C11
C12
C13
C14
C15
C16
C17
C18
R1
R2
RFC
L1
L2
F1
F2
F3
X1

10%

22pF± 2%
lnF±lO%
Q.lIlF ±lO%
0.1 j..I.F± 10%
6.8 /JF ± 20%
1 nF±lO%
15nF±1Q%
10pF± 2%
O.l/J-F± 10%
0.1 ,u.F± l()'1lo

O.l,u.F ± 10%
150pF± 2%
1.SK± 5%
l00K± 1%
5.5,uH
0.209 - 0.283 IlH
O.5-1.3/-1H
455 kHz

455 kHz
44.545 MHz

SOV
100V
100V
100V
50V
SOV
25 V
100V
50V
100V
SOV
50V
50V
100 V
l/BW

Polyester

NPO Ceramic
Nl50 Ceramic
K2000 - Y5P Ceramic
Polyester
Polyester
Tantalum
K2000 - Y5P Ceramic
Polyester
NPO Ceramic
Polyester
Polyester
Polyester
N1S00 Ceramic
Carbon Composition
1/4W
Metal Film
RF Chocke J.w. Miller 542 - 4609
Adjustable VHF Coit Miller 48A257MPC
Adjustable Coil 1811 - 0036TW
Ceramic Filter Murata SFG 455A3
IF Filter Toko A2549
Third Overtone Crystal

Figure 7. Application Test Board Parts

,/

RL "" lOOK n
A=-113dBm=2.7 jJ.V

10

1K

100

15000 INPUT SIGNAL STRENGTH (jJ.V)

Figure 8. RSSI vs Signal Strength

February 1987

4-134

Signetics linear Products

Application Note

AN199

Designing With the NE/SA604

SAlNE604

SOK

O.1~F

Figure 9. Temperature·Compensated RSSI Circuit

NE604 I.F. INPUT

100

10

(~N)

(15000)

1K

_----

//------------//---

-0

/

/'

fa~ ....

..••-::::.\••,

~~!

_/J"

/'

\\

.,~<....

~wit -40

~~~

/

L._._:~~~~~~~._._._

I~:I:

-<>0

e

1V

' .................~?!~=-..-...........

, //

--'

-120

3V

2V

/~'" ~-.~

~II~

-80

/

\.

fBge

4V

RSSI (VOLTS).,/

\\

~a~
~~~

::~
0:"0

100K

10K

AUDIO

-100

-80

-so

-20

SAlNE602 RF INPUT (dBm) (500)

Figure 10. NE602/604 System Performance

ACDVM

AUDIO
DISTORTION &
LEVEL METER
HP339A

Figure 11. NE/SA602INE/SA604 Applications Board

February 19B7

4·135

•

I

Application Note

Signetics Linear Products

AN199

Designing With the NEjSA604

73.8

25

iii
z

:s

9V 8.5V 8V

20

73.6

15

_ 73.4

IL!""

10

""

i7

!:(.4V

" "-

'\

w

0

m

:s
z 73.2

~

-5

i!!i
-10

'\.

73.0
72.S

~

0

~

-15

tlw

lr

iil

'\
u

72.2

-20

o

-40

40

80

./

/

r/"
-40

120

40

m

33.0

n

,

75

./

'\..

'" '\..

32.0

to:; 31.5

~

Figure 13. NE/SA604 Signal·To-Nolse Ratio vs
Temperature

\.

~ 32.5

~

31.0

......

./

,~

""- ........
'0.

29.0
-40

40

80

50

In

45

/

V

.........

30.0
29.5

lif
-40

120

40

Figure 14. NE/SA604 AM Rejection vs Temperature

2.8
~

300

~

260

6

240

V

V

~

2.6
2.4

V"

V

160

2.0

V

200
180

/

~

l§" 220

Iei'"

1.8

V

-40

1.6
40

80

V

V

V

""

40

80

Figure 17. RSSI va Temperature

4-136

fa

/

TEMPERATURE ('C)

Figure 16. NE/SA604 Data Output vs Temperature

-

IrI'

-40

120

TEMPERATURE ('C)

February 1987

120

Figure 15. NE/SA604 Audio Output vs Temperature

340

320

I!:

80

TEMPERATURE ('C)

TEMPERATURE ('C)

280

/'

I/V"

30.5

[

120

80

34.5
33.5

80

TEMPERATURE ('C)

Figure 12. NE/SA604 Indicated Gain vs
Temperature and Voltage

_

Id"

LV"

TEMPERATURE ('C)

34.0

,~

/

72.6
72.4

-

./V"

Q

I'I:l. ~

0

:t~

"-

~

/

120

Signetics Linear Products

Application Note

Designing With the NE/SA604

87.5

67.0

l~

Iii 88.5
l!.

i!!

i

AN199

-89.5

"

~

...........

....

f'.. r--.....

,

-40

40

80

TEMPERATURE (OC)

5.2

4.8
4.6

4.2

/

'" 4.0
Ie

3.4
3.2

""

~

~ 4.4

/'

V

I"-'"

.......

"

..........

-93.5

"!2z
......'"

"
'"
::E

-41

/ ~

o(J

-42

Ll

-43

i

Q

~

-44
-45
-46

I~

,

\

-47

r:I
40

80

..... i'oo._

/

\

J

~

\

Id'"

!\

I~

-40

120

40

80

120

TEMPERATURE (Oe)

Figure 21. NE/SA604 Total Harmonic Distortion va
Temperature

200

r::!'

8.5V

-'

8.5V

-00..-

180

"IJ

./

:> 140

.",,'1'

--~

6.0V

.s
=

,...

4.5V

60
40

l~
-40

."

80 I~

V

/'/

/

a: 100

..,...... .0-

cf'

120

"U

P

/
,/>
;r 6.O'l jJ

160

2.1

1.9

I

\

J

-49

2.3

2.0

0(]

OPQ0310S

2.4

2.2

-

120

80

Figure 19. NE/SA604 Limiting RF Level vs Temperature

2.7

...~

40
TEMPERATURE (Oe)

Figure 20. NE/SA604 Large Signal Uncompensated
RSSI Voltage va Temperature

< 2.5

0

-40

120

-

~

-94.0

TEMPERATURE (Oe)

.s

~

-93.0

-48

-40

2.6

"-

~ -92.5

/

/

I"'

-92.0

Figure 18. NE/SA604 Muting va Temperature

5.0

'"

~-91.5

""-

85.0

~

§

rtJ

3.6

~

e- 91 .0

66.0

3.8

0....

-90.5

65.5

(ij

1

-90.0

I~

V

/

i£/

4.5V

,

/.,/ fJ

....... ~

20
-40
40

80

120

40

80

120

TEMPERATURE (Oe)

TEMPERATURE (Oe)

Figure 22. NE/SA604 Supply Current va
Temperature and Voltage

February 1987

Figure 23. Smail-Signal RSSI vs Temperature and Voltage

4-137

•

Application Note

Signetics Linear Products

Designing With the NEjSA604

AN199

-

2.6

16~~__~----+-----~-----+-----+----~

C

§.

....z

2.'

W
II:
II:

::>
(J

~ 2.2

~

0.
0.

::>

"'
10 ~-----+------+------+------+-----~~--~

-40

40

80

2.0

~

Figure 24. NE/SA604 SINAD vs Temperature and Vce

I
SENSITIVITY
_ _ _ _ _ _- ,

12

NE604

lOOK

Figure 26. Field Strength Meter

February 1987

40

Figure 25. SA604 Supply Current vs Temperature

2pF

10K~

~c=4.5V

TEMPERATURE (0C)

TEMPERATURE (OC)

o

Vcc=6.0V

-40

120

-

Vee = 8.5V

4-138

80

Signetics Linear Products

Application Note

AN199

Designing With the NE/SA604

MIXER

12

NE604

>---......

---0

~~::tT

lOOK

Figure 27. AM Synchronous Detector

r--------1------------<>~~UT
12

NE6D4

>--~--<>~~~~UT
100K

Figure 28. Product Detector

February 19B7

4-139

•

Signetics

AN1991
Audio Decibel Level Detector
With Meter Driver
Application Note

Linear Products

Author: Robert J. Zavrel Jr.

DESCRIPTION
Although the NE604 was designed as an RF
device intended for the cellular radio market,
it has features which permit other design
configurations. One of these features is the
Received Signal Strength Indicator (RSSI). In
a cellular radio, this function is necessary for
continuous monitoring of the received signal
strength by the radio's microcomputer. This
circuit provides a logarithmic response proportional to the input signal level. The NE604
can provide this logarithmic response over an
aOdS range up to a 15MHz operating frequency. This paper describes a technique which
optimizes this useful function within the audio
band.
A sensitive audio level indicator circuit can be
constructed using two integrated circuits: the
NE604 and NES32. This circuit draws very
little power (less than SmA with a single 6V
power supply) making it ideal for portable
battery operated equipment. The small size
and low-power consumption belie the aOdS
dynamic range and 10.SIN sensitivity.

The RSSI function requires a DC output
voltage which is proportional to the IOg10 of
the input signal level. Thus a standard 0 - S
voltmeter can be linearly calibrated in decibels over a single aOdS range. The entire
circuit is composed of 9 capacitors and two
resistors along with the two ICs. No tuning or
calibration is required in a manufacturing
setting.
The Audio Input vs Output Graph shows that
the circuit is within I.SdS tolerance over the
aOdS range for audio frequencies from 100Hz
to 10kHz. Higher audio levels can be measured by placing an attenuator ahead of the
input capacitor. The input impedance is high
(about SOk), so lower impedance terminations
(SO or 600n) will not be affected by the input
impedance. If very accurate tracking is reqUired « O.SdS accuracy), a 40 or SOdS
segment can be "selected". A range switch
can then be added with appropriate attenuators if more than 40 or SOdS dynamic range is
required.

OdB-300mVp.T.p..L

.1

....)~

SOLID LINE IN~I~TES
IDEAL SLOPE
DOITED LINE.! -'
INDICATES
MEASURED SLOPE

.J

Vcc=8V
)

~

b?

0~'
....

o

r- 17

-100

....

-80

-60

-40

-20

AUDIO INPUT (dB)

.---------------------~----__o+8V

18
METER

r~

Figure 1

February 1987

4-140

Signetics linear Products

Application Note

Audio Decibel level Detector With Meter Driver

There are two amplifier sections in the B04
with 2 and 3 stages in the first and second
sections respectively. Each stage outputs a
sample current to a summing circuil. The
summing circuit has a current mirror which
appears at Pin 5. This current is thus proportional to the 10glO of the input audio signal. A
voltage is dropped across the 100k resistor
by the current, and a 0.11lF capacitor is used
to bypass and filter the output signal. The 532
op amp is used as a buffer and meter driver,
although a digital voltmeter could replace
both the op amp and the meter shown. The
rest of the capacitors are used for power
supply and amplifier input bypassing.
The RC circuit between Pins 14 and 12 forms
a low-pass filter which can be adjusted by
changing the value of C1. Raising the capaci-

February 1987

tance will lower the cut-off frequency and also
lower the zero signal output resting voltage
(about O.BV). Lowering the capacitance value
will have the opposite effect with some reduction in dynamic range, but will raise the
frequency response. The 2kn resistor value
provides the near-ideal inter-stage loss for
maximum RSSI linearity. C2 can also be
changed. The trade-off here is between output damping and ripple. Most analog and
digital metering methods will tend to cancel
the effects of small or moderate ripple voltages through integration, but high ripple voltages should be avoided.
A second op amp is used with an optional
second filter. This filter has the advantage of
a low impedance signal source by virtue of
the first op amp. Again, a trade-off exists

4-141

AN1991

between meter damping and ripple attenuation. If very low ripple and low damping are
both required, a more complex active lowpass filter should be constructed.
Some applications of this circuit might include:
1. Portable acoustic analyzer
2. Microphone tester
3. Audio spectrum analyzer
4. VU meters
5. S-meter for direct conversion radio
receiver
6. Audio dynamic range testers
7. Audio analyzers (THD, noise, separation,
response, etc.)

Signetics

NE/SA605
Low Power FM IF System
Objective Specification

Linear Products
DESCRIPTION

FEATURES

The NE/SA605 is a monolithic,low power FM IF system incorporating VHF
monolithic, double-balanced mixer with
input amplifier, on-board oscillator, two
limiting intermediate frequency amplifiers, quadrature detector, muting, logarithmic signal strength indicator, and
voltage regulator.

• Low power consumption: 5.3mA
typical
• Excellent noise figure: < 5.0dB
typical at 45MHz
• High operating frequency
• Excellent gain, intercept, and
sensitivity
• Low external parts count;
suitable for crystal/ceramic filters
• SA605 meets cellular radio
specifications
• Logarithmic Received Signal
Strength Indicator (RSSI) with a
dynamic range in excess of 80dB
• Separate data output
• Audio output with muting
• Excellent sensitivity: 1.5tN across
input pins (O.27J1.V into 50n
matching network) for 12dB
SINAD (Signal-to-Noise and
Distortion ratio) at 455kHz

It is intended for high performance, low
power communication systems. The
guaranteed parameters of the SA605
make this device particularly well-suited
to cellular radio applications. The mixer
is a "Gilbert cell" multiplier configuration
which typically provides 15dB of gain at
45MHz. The oscillator will operate to
200M Hz. It can be configured as a
crystal oscillator, a tuned tank oscillator,
or a buffer for an external L.O. The noise
figure at 45MHz is typically less than
5dB. The gain, intercept performance,
low power, and noise characteristics
make the NE/SA605 a superior choice
for high-performance battery-operated
equipment.

PIN CONFIGURATION

The NE/SA605 is available in 20-lead
dual in-line plastic and Cerdip packages
and 20-pin SO (surface-mounted miniature) packages.

ORDERING INFORMATION
TEMPERATURE RANGE

ORDER CODE

20-Pin Plastic DIP

DESCRIPTION

o to +70°C

NE605N

20-Pin Plastic SO

o to

NE605D

20-Pin Ceramic DIP

o to +70°C

NE605F

20-Pin Plastic DIP

_40°C to +'B5°C

SA605N

20-Pin Plastic SO

-40°C to + B5°C

SA605D

20-Pin Ceramic DIP

-40°C to + B5°C

SA605F

February 1987

+70°C

4-142

D, F, N Packages

RF

BYPASS

AUDIO OUT

8

13

12

QUAD IN

~:&~~
~:::'b~~

11 UMITEROUT

lOP VIEW

APPLICATIONS
• Cellular radio FM IF
• Communications receivers
• Intermediate frequency
amplification and detection up to
25MHz
• RF level meter
• Spectrum analyzer
• Instrumentation
• Portable radio
• VHF transceivers
• RF data links
• HF/VHF frequency conversion
• Instrumentation frequency
conversion
• Broadband LANs

Signetics Linear Products

Objective Specification

Low Power FM IF System

NE/SA605

BLOCK DIAGRAM

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

RATING

UNIT

Vee

Maximum operating voltage

9

V

TSTG

Storage temperature range

-65 to + 150

°C

TA

Operating temperature range
NE605
SA605

o to +70
-40 to +85

°C
°C

February 1987

4-143

Objective Specification

Signetics Linear Products

low Power FM IF System

NE/SA605

DC ELECTRICAL CHARACTERISTICS T A = 25°C; Vee = + 6V, unless otherwise stated.
LIMITS
PARAMETER

SYMBOL

TEST CONDITIONS

UNIT
Min

Vee

Power supply voltage range

Typ

4.5

DC current drain

5.3

Mute switch input threshold
(on)
(off)

Max

8.0

V

6.0

mA

1.0

V
V

1.7

AC ELECTRICAL CHARACTERISTICS TA = 25°C; Vee = +6V, unless otherwise stated. RF frequency = 45MHz; IF

frequency = 455MHz; FM modulation = 1kHz with ± 8kHz peak deviation. Audio output
with C-message weighted filter and de-emphasis capacitor.
LIMITS

PARAMETER

SYMBOL

TEST CONDITIONS

UNIT
Min

Typ

Max

fiN

Input signal frequency

500

MHz

fose

Oscillator frequency

200

MHz

Noise figured at 45MHz

5.0

dB

-15

dBm

Third-order intercept point

RFIN = -45dBm:

f, =45.0
f2 = 45.06

Conversion gain at 45MHz
RIN

RF input resistance

CIN

RF input capacitance

Input limiting -3dB

Recovered audio level

THD

Total harmonic distortion

SIN

Signal-to-noise ratio
RSSI output

kn
3

Test at Pin 1

3.5

pF

1.5

kn

-117

dBm

80% AM 1kHz

30

After C filter and de-emphasis
capacitor

80

100

mVRMS

250

350

mVRMS

12

15

dB

Recovered data level
SINAD sensitivity

1.5

(Pin 20)

Mixer output resistance

AM rejection

dB

15
Single-ended input

RF level -117dBm

dB

-35
No modulation for noise

70

RRSSI = 100K
RF level = -117dBm
RF level = -67dBm
RF level = -23dBm

0
2.0
4.0

RSSI range

RRSSI

RSSI accuracy

RRSSI

= 100k
= 100k

dB
75

dB
400
2.6
5.0

mV
V
V

Pin 7

90

dB

Pin 7

± 1.5

dB

IF input impedance

1.5

kn

IF output impedance

1.0

kn

Limiter input impedance

1.5

kn

Quadrature detector data output
impedance

50

kn

Muted audio output impedance

50

kn

February 1987

4-144

Signetics Linear Products

Objective Specification

low Power FM IF System

Circuit Description
The NE/SA605 is an RF/IF signal processing
system suitable for second IF or single conversion systems with input frequency as high
as 500MHz. The bandwidth of the IF amplifiers is 25M Hz. However, the gain distribution
is optimized for 455kHz. The overall system is
well-suited to battery operation as well as
high-performance and high quality products
of all types.
The input stage is a Gilbert cell mixer with
oscillator. Typical mixer characteristics include a noise figure of 5dB, conversion gain
of 15dB, and input third order intercept of
-15dBm. The oscillator will operate well in
excess of 200MHz in LIC tank configurations,
either Hartley or Colpitts. For crystal oscillators, the Colpitts configuration is used.
The output of the mixer is internally loaded
with a 1.5k!1 resistor permitting direct con-

NEjSA605

nection to a 455kHz ceramic filter. The equivalent input impedance of the limiting IF ampliers is also 1.Sk!1. With most 455kHz ceramic
filters and many crystal filters, no impedance
matching network is necessary. To achieve
optimum linearity of the log signal strength
indicator, there must be a 6dB insertion 1055
between the first and second IF stages. If the
IF filter or interstage network does not cause
6dB insertion 1055, a fixed or variable resistor
can be added between the first IF output (Pin
16) and the interstage network ..
The signal from the second limiting amplifier
goes to a Gilbert cell quadrature detector.
One port of the Gilbert cell is internally driven
by the IF. The other output of the IF is ACcoupled to a tuned quadrature network. This
signal, which now has a 90 0 phase relationship to the internal signal, drives the other
port of the multiplier cell.

FILl 1

Overall, the IF section has a gain of 92dB. For
operation at intermediate frequencies greater
than 455kHz, special care must be given to
layout, termination, and interstage 1055 to
avoid instability. Alternatively, if gain distribution permits, only the second limiting IF stage
can be used. This stage has 57dB of gain.
The demodulated output of the quadrature
detector is available at two pins, one continuous and one with a mute switch. Signal
attenuation with the mute activated is greater
than 60dB. The mute input is very high
impedance and is compatible with CMOS or
TIL levels.
A log signal strength indicator completes the
circuitry. The output range is greater than
80dB and is temperature compensated. This
log signal strength indicator exceeds the
criteria for AMPs or TACs cellular telephone.

FILl 2

CJ

1"

C16

C17
20

18

-1FT;"l

17

III

NE605

1

C12

en

Cl0
R2

I

C9

c~

ctj
v+

Figure 1. NE/SA605 45MHz Test and Application Circuit

February 1987

4-145

-1

•

NE614

Signetics

Low Power FM IF System
Product Specification

Linear Products
DESCRIPTION

FEATURES

The NE614 is a monolithic low power
FM IF system incorporating two limiting
intermediate frequency amplifiers, quadrature detector, muting, logarithmic signal strength indicator, and voltage regulator. The NE614 is available in a 16lead dual in-line plastic package and 16lead SO (surface-mounted miniature
package).

• Low power consumption
• Logarithmic signal strength
indicator
• Separate data output
• Audio output with muting
• Low e.xternal count; suitable for
crystal/ceramic filters
• Excellent sensitivity

PIN CONFIGURATION

APPLICATIONS
• Cellular Radio FM IF
• Communications receivers
• Intermediate frequency
amplification and detection up to
15MHz
•
•
•
•
•

N, 0 Packages
IF AMP

OECOUPllNG
IF AMP
OECOUPLING
MUTE INPUT

IF AMP
OUTPUT

3

GND
LIMITER
INPUT

RSS\ OUTPUT

5

AUDIO OUTPUT

6

OA TA OUTPUT

7

10

LIMITER
OECOUPLING

8

9

LIMITER
OUTPUT

LIMITER
DECOUPLING

QUADRATURE

INPUT

TOP VIEW

RF level meter
Spectrum analyzer
Instrumentation
Cordless telephone
Remote control

BLOCK DIAGRAM

November 4, 1985

4-146

853·0396 81127

Product Specification

Signetics Linear Products

NE614

low Power FM IF System

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

o to
o to

16-Pin Plastic DIP
16-Pin Plastic SO

ORDER CODE

+70°C

NE614N

+70°C

NE614D

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

RATING

UNIT

Vee

Maximum operating voltage

9

V

TSTG

Storage temperature range

-65 to + 150

°C

TA

Operating ambient temperature range
NE614

o to

°C

+70

DC ELECTRICAL CHARACTERISTICS TA = 25°C; Vce = + 6V, unless otherwise stated.
SYMBOL

Vee

PARAMETER

TEST CONDITIONS

MIN

Power supply voltage range

TYP

4.5

DC current drain
Mute switch input threshold
(on)
(off)

MAX

UNIT

8.0

V

3.0

mA

1.0

V
V

1.7

AC ELECTRICAL CHARACTERISTICS TA = 25°C; Vee = + 6V, unless otherwise stated. RF frequency = 455kHz; RF
level = -47dBm; FM modulation = 1kHz with +8kHz peak deviation. Audio output with
C-message weighted filter and de-emphasis capacitor.
SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

-90

-80

dBm

Input limiting - 3dB

Test at pin 16

AM rejection

80% AM 1kHz

30

After C filter and
de-emphasis capacitor

80

100

mVRMS

250

350

mVRMS

8

12

dB

75

dB

Recovered audio level
Recovered data level
SINAD sensitivity
THD

Total harmonic distortion

SIN

Signal-to-noise ratio

RF level- 97dBm

dB

-35
No modulation

dB

IF input impedance

1.5

kQ

IF output impedance

1.0

kQ

Limiter input impedance

1.5

kQ

Quadrature detector data
output impedance

50

kQ

Muted audio output impedance

November 4, 1985

50

4-147

kQ

•

Signetics Linear Products

Product Specification

NE614

Low Power FM IF System

TYPICAL APPLICATION

kHz IF

O.1/o1FJ

TEST SETUP

MUTE INPUT

NE 614 TEST CIRCUIT

RSSIOUTPUT

B

November 4, 1985

4-148

Signetlcs Linear Products

Product Specification

low Power FM IF System

NE614

NE 614 TEST CIRCUIT

r--_---. ---,
Q

= 20 LOADED

I

I

I F,
I

~~~-l

OATA
OUTPUT

MUTE
INPUT

Vee

RSSI
OUTPUT

NOTES:

C1 10nF +80-20% G3V K10000~Z5V Ceramic
C2 1QOnF±10% SOV Polyester
C3 1OOnF ± 10% SOV Polyester

C4 1OOnF ± 10% SOV Polyester
CS 100nF ± 10% SOV Polyester
C6 10pF±2% 10DV NPO Ceramic
C7 100nF ± 10% SOV Polyester
CS 100nF±10% SOV Polyester
C9 15nF ± 10% SOV Polyester
C10 150pF ± 2% 1
N 1500 Ceramic

aov

Cll 1nF±10% tODV K2000-Y5P Ceramic
C12 6,8.uF ± 20% 25V Tantalum
F1 455kHz Ceramic Filter Murata SFG455A3
F2 455kHz IF Filter A2549
R1 51.Q±1% 1/4W Metal Film
R2 1500.(2±1% 1/4W Metal Film
A3 1500.Q±5% 1/8W Carbon Composition
R4 100kn±1% 1/4W Metal Film

Figure 1. NE614 Test Circuit and Parts List

DESCRIPTION OF OPERATION

Limiting Amplifiers

The NE614 is comprised of five subsystems
for IF signal processing. These subsystems,
two IF limiting amplifiers, quadrature detector,
audio mute, and logarithmic signal strength,
can be configured to satisfy many high·
performance or low power systems objec·
tives. Internal temperature compensated bias
regulation completes the circuitry.

The NE614 has two independent limiting IF
amplifiers. The first has a typical gain of
30dS. The second typically has 60dS gain.
Soth have 1.5k nominal input impedance and
15MHz bandwidth. The output impedance of
the first limiter is approximately 1kn. These
impedances permit direct interface with popu·
lar ceramic filters such as the SFU455. On
the surface, the 1k output of the first limiter
would not seem correct. However, approximately 6dS insertion loss is required between

Figure 2 shows the equivalent circuits of the
NE614.

November 4, 1985

4-149

limiter stages to optimize the linearity of the
signal strength indicator. The impedance mismatch has little effect on passband. Use Of an
interstage filter reduces wide-band noise. A
DC blocking capacitor or LlC filter can also
be used.
As the signal frequency increases, the 90dS
total gain can become a source of instability.
Figure 3 shows the limiters as a closed-loop
system with stray capacitance and the equivalent AC input impedance setting the loop
gain.

Signetic$ Linecr Products

Product Specification

NE614

Low Power FM IF System

AO,JUST FOR 6 dB INSERTION
LOSS RELATIVE TO THE 1K
SOURCE (PIN 14) AND THE UK LOAD (PIN 12) .....
,..-~"I'r-,

Figure 2. Equivalent Circuit

eSTRAY

...--------if-------,

I

I

~
-= ":"

":'"

":"

":"

Figure 3. Considerations for Stability

November 4, 1985

4-150

The equivalent AC attenuation factor from the
output to the input must be greater than 90dB
or oscillation can occur. The input impedance
of the device is nominally 1.5k. The stray
layout capacitance is a frequency-dependent
impedance so that as the frequency of operation or the value of stray capacitance increases, the output-to-input attenuation factor decreases. Keep stray capacitance low by
using good RF layout technique. Sockets
should be avoided above 455kHz.
Good RF layout is the proper way to avoid
instability. However, if system constraints require, stability can be achieved by only using
one of the limiting amplifiers, or by adding a
resistance, RIN, which will increase the attenuation factor.

Signetics linear Products

Product Specification

Low Power FM IF System

NE614

r --1
455 kHz
Q;;; 20

+6Vo-""'""""1r'"TTn..,...--,

I

I

"-J:-:Fl

a. NE614 Application Circuit

.

NE614 1.F.INPUr (,u.Y) (15OO!l)
100

,

,_

10K

...

h~~!
w~z

~.o

.25

~~~

....

5~~

....

~§~
1<
0< •

21+1
00

~-

'"

-80

NE612 RF INPUT (dBm) (SOD)

b. Typical Application Circuit Performance
Figure 4
Adding an input resistor is an easy way to
reduce the attenuation factor, but may make
correct termination of interstage filters difficult
or impossible. At 455kHz instability should not
be a problem if reasonable RF layout is used.
Figure 4a indicates a 455kHz circuit configuration which should serve as a reasonable
starting point for many applications. This
circuit is configured for 46/49MHz cordless
telephone.

is applied to the multiplier internally. 90'
phase phase shift is accomplished with the LI
C tuned circuit connected directly to Pin 8 and
and capacitively to Pin 9. Because of the DC
bias of the NE614, the phase shift network
must be returned to ground through a low
impedance capacitor. Recovered signal is
continuously available at Pin 7 or on a
switched basis at Pin 6.

Quadrature Detector

Q

The detector of the NE614 is a four quadrant
multiplier of the Gilbert cell type. It can be
used for frequency or amplitude demodulation. Figure 4b indicates a typical quadrature
FM configuration. Fully limited in-phase signal
November 4, 1985

Table 1. System Parameters as
Applied to Figure 4a
Aw = 211'*8kHz
Wo = 211'*455kHz
CP = 180pF
RPU = 233K
RPL = 40K
LP = 644fJH

4-151

,.,

20

Signetics Linear Products

Product SpecificCltion

NE614

Low Power FM IF System

jOOADTANK----l

C,
VIN>-i

t-.,....+.....,--"t'""-.....,--r~ VOUT

: ,LTcp ! LP
I

APL

I

APui

I

EQUATION

Your =
V,N

!we,

- - : - ,-~--:",,---

RPLIIRPU (1 + 12Q:;;;) + )we1

wo (APLI

I APU) CP

Q

•

il.w

= PEAK DEVIATION

=CENTER FREQUENCY

ture network can cause non-linearity in the
detected output. A typical loaded Q for the
455kHz quadrature coil of Figure 4 is 20.
Using the test circuit of Figure 4 with an input
of -47dBm, the recovered audio is typically
90mVRMS with -35dB distortion.
While the NE614 was designed principally for
FM applications, the detector can be used for
synchronous amplitude demodulation if the
carrier is limited through the internal circuitry
and AGC'o external to the device. The AGC'd
signal is applied to Pin 8 instead of a quadrature signal. The signal strength indicator can
control AGC. A low-pass filter on the output
completes the demodulator. Figure 7 shows
the equivalent circuit.

Figure 5. General Equations
For Quadrature Coli
The quadrature coil or crystal/ceramic discriminator affects three system parameters:
Bandwidth, linearity, and detected signal amplitude. Figure 6 shows three quadrature
curves.
Curve A has the most narrow bandwidth and
high peak-to-peak output versus frequency
deviation corresponding to a high Q network.
Curve C is very low Q with good linearity and
shows how very large deviations can be
processed. Curve B shows how the quadra-

Audio Mute
An electronic switch permits muting or squelch
of one of the demodulated outputs. The data
(unmuted output) and audio (muted output)
both have 50kSl output impedance and their
detected signals are 180 degrees out of phase
with each other. The mute input (Pin 3) has a
very high impedance and is compatible with
three and five volt CMOS and TTL levels. Little
or no DC level shift occurs after muting when
the quadrature detector is adjusted to the IF
center frequency. Muting will attenuate the
audio signal by more than 60dB and no voltage
spikes will be generated by muting.

Signal Strength Indicator
The logarithmic signal strength indicator is a
current source output with maximum source
current of 50pA. The signal strength indicator's
transfer function is approximately 10pA per
20dB and is independent of IF frequency. The
interstage filter must have a 6dB insertion loss
to optimize slope linearity.

RESONANCE
FREQUENCY ---....

Figure 6. Quadrature

MIXER

12

NE614

>---....---o_~~~~UT
lOOK

Figure 7. Synchronous AM Detection

November 4, 1985

4-152

Product Specification

Signetics Linear Products

NE614

Low Power FM IF System

25
20

I.

I

73.8

-

kI.

,

8.5

6Y

73.6

~t70

33.0

II

~Oeo

",

~

30.5
30.0

,/

~

I

i
i

~ 55

40

2.8

320

2.6

300

~280
~260

.:r

l-

220

V

'"

~

1.6
40
70
TEMPERATURE ('C)

I

I

1.8

I

o

40

70

TEMPERATURE ('C)

Figure 12. NE614 Data Output vs Temperature

November 4. 1985

~

2.0

I
o

./

iii 2.2

~

i

180

V",

2.4

,/

200

160

70

Figure 11. NE614 Audio Output vs Temperature

340

~

40
TEMPERATURE ('C)

Figure 10. NE614 AM Rejection vs Temperature

Q

1

o

70

TEMPERATURE ('C)

S 240

I

i

45

29.0

I

:

50

..........

29.5

r/

Figure 13. RSSI

4-153

VB

Temperature

•

Product Specification

Signetics Linear Products

NE614

Low Power FM IF System

16

VCC='8.SV

2.8

I---f---j

~

Vcc= 6.0V

-Vcc=4.SV

10

I---f---j
40

2.0

40

70

Figure 14. NE614 SINAD

VB

70

TEMPeRATURE (OC)

TEMPERATURE (Oc)

Figure 15. NE614 Supply Current

Temperature and Vcc

67.5

-88.5

87.0

-80.5

Temperature

VB

-80.0

j' -81.0
!!. -91.5

"""""" IC....... r-....

ill

~ -92.0

-'

"-

Il: -92.5

I"

'tl..

-83.0

65.S

",

-93.S
-84.0

65.0
40
70
TEMPERATURE (Oc)

-41

5.0

-42

,.."

'.4 V

~
in 4.2

70

Figure 17. NE614 limiting RF Level vs Temperature

5.2

4.6

40
TEMPERATURE (Oc)

Figure 16. NE614 Muting vs Temperature

4.8

o

i"

.....

IJ

-43

~

I

-44

l
Q

i!:

til

a: 4.0
3.8

1

-45

II

-46

/

-47

3.6

-48

~

Id

3.4
-49

3.2

o

40
70
TEMPERATURE (Oc)

o

40
70
TEMPERATURE (Oc)

OPQ1570S

Figure 18. NE614 Large Signal Uncompensated
RSSI Voltage VB Temperature

November 4, 1985

Figure 19. NE614 Total Harmonic Distortion vs
Temperature

4-154

Product Specification

Signetics Linear Products

Low Power FM IF System

NE614

2.7
8.5V

2.6

;r 2.5

g

~

....
c
z
S!
til
....
....

2.3

til

g

--~

2.1

/

140

1--1--1----1--1

~ 120

6.0V

a: 100

2.2

c

:II

:>

2.'

f--f---f----,j-9

80

~,4.5V

60

2.0

1.'

o

40
40
70
TEMPERATURE (OC)

Figure 20. NE614 Supply Current vs
Temperature and Voltage

November 4, 1985

70

TEMPERATURE (Oe)

Figure 21. Small-Signal RSSI vs Temperature and Voltage

4-155

TDA1576

Signetics

FM-IF (Quadrature Detector)
Product Specification

Linear Products

DESCRIPTION

FEATURES

APPLICATIONS

TDA 1576 is an IC which provides all the
functions of a comprehensive FM-IF system. The block diagram of the TDA 1576
includes a 4-stage FM-IF Amplifier/Limiter with level detector, quadrature FM
detector, FM detector, internal regulator,
AFC output, and audio meeting circuit.
The TDA1576 is ideal for application
areas that require low distortion characteristics (THD).

• Symmetrical limiting IF amplifier

• High-fidelity receiver
• Communication receiver
• Automotive receiver

• Symmetrical quadrature
demodulator
• Internal muting circuit
• Symmetrical AFC output
• Field-strength Indication output
• Detune-detector
• Reference voltage output
• Electronic smoothing of the
supply voltage
• Standby on/off switching circuit

• TVRO

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

- 30·C to + 80·C

TDA1576N

18-Pin PlastiC DIP (SOT-102C)

ABSOLUTE MAXIMUM RATINGS
SYMBOL

VCC=Vl-18

PARAMETER

Supply voltage (Pin 1)

RATING

UNIT

23

V

Vcc
0
23
0
7
0
6
23
0

V
V
V
V
V
V
V
V
V

Voltages
V2- 18
-V2- 18
VS-18
-VS-18
V12 - 19
-V12-18
V13-19
V14 - 19
-V14 - 18

at Pin 2
at Pin 5
at Pin 12
at Pin 13
at Pin 14

PTOT

Total power dissipation

800

mW

TSTG

Storage temperature range

-65 to +150

·C

TA

Operating ambient temperature range

-30 to +80

·C

/lCRA

Thermal resistance from crystal to ambient

80

·C/W

January 14, 1987

4-156

853-113487196

Product Specification

Signetics Linear Products

TDA1576

FM-IF (Quadrature Detector)

BLOCK DIAGRAM AND TEST CIRCUIT
+

D
33pF

(2x)
3

lis

17

25k

~.1"F

25k

O.1,uF

4·STAGE
LlMITERI
AMPLIFIER

16

-=

t-

-

~~

Rs

Vs

1
1:
15k

MUTING

1

+
~5V)

f2W

1

15k

2
AFC
VOLTAGE

t

I

Q

Vee

4

7

~

r--

~r
aUADRATURE
DEMODULATOR

1->-+

O.1,uF

'V

C

L

15

VI
(IF)

10

t

r--

,.

5.5
k

r--

+

-

)t3.7k

-=
TDA1576

LEVEL
DETECTOR

1

INDICATOR
DRIVER

1->--

STANDBY
SWITCH

4V_
(BVSE)

DETUN~

1.7V
F-'+-J
__D,ETECT~~~

INTERNAL
POWER
SUPPLY

I
I
I

~4cl~) ~~~)

5.3V

20k

13

3.ak

14

VF

1-+10~....._..J

12

220k
~- -,
·1

- : (25k) 1 M
1nF
ON
(AM)

FIEL[)'STRENGTH
INDICATOR

j 111=
O.SmA

~85VT)

~

J

-=

-=

VFo
ZERO·ADJUSTMENT
OF FIEL[).STRENGTH
INDICATOR

~

r""Nor
I

10k~-l
~

+

DETUNE·
VOLTAGE

«23V)

NOTES:
1. For de·emphasis T = SOILS: Cs _ 9 = 6.8nF. For stereo operation: Ce _ 9 = 56pF
2. L = O.38p.H; 00 = 70; QL = 20; adjusted to minimum 2nd harmonic distortion (d2); at VI = 1 mY; coil: 6 turns CuL (O.2Smm) on coil former KAN (C).

January 14, 1987

4-157

I
I
I
I

Signetlcs Linear Products

Product Specification

TDA1576

FM-IF (Quadrature Detector)

DC AND AC ELECTRICAL CHARACTERISTICS

VCC = 8.5V fa = 10.7MHz; ilf = ± 22.5kHz; 1M = 400Hz; Rs = 60n; de-emphasis T = 50"s (CB_ 9 = 6.8nF); TA = 25°C; measured in the Block Diagram. unless otherwise specilied. The demodulator circuit is adjusted at
minimum 2nd harmonic (d2) distortion: V1 = 1mY; ill = ± 75kHz.
LIMITS

SYMBOL

UNIT

PARAMETER
Min

Vcc

Supply voltage range (Pin 1)

7.5

Icc

Supply current; without load (112 = 113 = 0)

10

Typ

Max

20

V

16

23

rnA

30

"V

IF amplifier/detector

VI

Sensitivity at -3dB belore limiting

22

VI
VI

IF sensitivity lor
S + NIN = 26dB
S + N/N = 46dB

8
35

"V
"V
mV

V3-7(P-P)

IF output voltage (peak-to-peak value)
VI = 1mV; Z3-18 = Z7-18

680

R3-7

IF output resistance

250

n

R4-B
C4 _ 6

Detector input impedance

30
1

kn
pF
kn

R8; R9

Output resistance

3.7

V8- 18 = V9-1

DC output voltage

5.5

Va

AF output voltage; QL = 20

dTOT
dTOT

Total distortion
single tuned circuit; QL = 20
two tuned circuits

60

67

V
75

mV

0.1
0.02

%
%

S+N/N

Signal pulse noise-to-noise ratio
B = 250Hz to 15kHz; VI > 1mV

76

dB

ex

AM rejection; VI = 10mV
FM: 1M = 70Hz; ill = ± 22.5kHz
AM: 1M = 1kHz; m = 0.3

54

dB 1

VI

IF input voltage range; cc > 40dB

0.5

QCl00

Hum suppression at I = 100Hz
Vee = Vl-18 = 100mVRMS
C2-18 = 47"F

43

AVS_9
ilIa

± ilV8 _ 9
± ilVs-9

500

mV

48

dB

AFC tuning slope at QL = 20

B.5

mY/kHz

AFC offset voltages; QL = 20
at VI = 1mV
at VI = 30"V to 500mV (relerence at 1mV and muting)

25

100
50

mV
mV

600

mV

0

200

mV

3.6

4.1

Field-strength indication

VI

Indicator sensitivity; 114 = 0

VF = V13-1S

Field-strength indicator voltage
R13 _ 18 =3.6kn; 114=0; VI=O

20

VF = V13-18

VI = 250mV

-113

Available output current

V13 - 1B

Reverse voltage at the output lor FM 'olf'; VS - 1B

January 14. 19B7

3.2

> 3.5V

4-158

V

2

rnA

5

V

Signetics Linear Products

Product Specification

FM-IF (Quadrature Detector)

TDA1576

DC AND AC ELECTRICAL CHARACTERISTICS (Continued) Vcc=8.5V fo=10.7MHz; af=±22.5kHz; fM=400Hz;
Rs = 60n; de-emphasis T = 50llS (Ce _ 9 = 6.8nF);
TA = 25°C; measured in lhe Block Diagram, unless otherwise specified. The demodulator circuit is adjusted at
minimum 2nd harmonic (d2) distortion: VI = 1mY;
al = ±75kHz.
LIMITS
SYMBOL

PARAMETER

UNIT
Min

Typ

Max

20

100

Detune-detector
110

Quiescent input current; V10 _9 = 0

Vll -18

Output voltage range

ill

Available output current

Av

Voltage gain; aVll/a(± VlO_9) at 111 = 0.2SmA

3.3

Vl0-9

Input offset voltage (Pin 10) at VII _ 18 = 2.5V

20

1.8
0.35

0.5

nA

5.0

V

0.65

rnA

mV

Reference voltage
VREF=VI2 - 18

Output voltage; -112 = 1rnA

5.1

V

-112

Available output current

2.5

rnA

Standby switch

V5 ON
V5 OFF

Required control voltage within
the rated ambient temperature and supply voltage ranges
lor FM 'on'
lor FM 'off'

-15

Input switching current for FM 'on'

2

V
V

100

j.tA

3.5

NOTE:
1. Simultaneously measured.

30

150

20

TY~

I--

1.5

QL=3O

--

I

do/"
50

./

......
o

10

Q L =30

/I

J

/1

10

o

V

II"

100

20

o

o

VccM

,,-

)p-

....

L

January 14, 1987

20

+ 15kHz; 1M'" 400Hz; typical

values

Figure 1. Supply Current Consumption;
Without Load

/"

./
10

Figure 2. AF Output Voltage

4-159

V

./

VccM
NOTE:
Vee = 1mV(IF); .6.f =

20

0.5

o
o

./

./

~

/'

%50
At (kHz)

NOTE:
Vj ... 1 mV (IF); fM - 400Hz; adjusted at minimum 2nd
harmonic distortion; typical values.

Figure 3_ Total Distortion for Single
Tuned Circuit

Signetics Linear Products

Product Specification

FM-IF (Quadrature Detector)

TDA1576

.11±75kHz

+20

S+N

,~'!OkIiZ
, :15kHz

-40
-60
N

-80

1

10

10'

NOTE:
S = Signal Voltage; N "" Noise Voltage; Vee = 15V; fM = 400Hz; B = 250Hz to 16kHz; Q L = 20; Ca _ 9 = 6.BnF; Typical Values.

Figure 4. AF Output Voltage Level as a Function of IF Input Voltage

,,"

~

.;

"oK'"
"

~,,,

"

~,,~~~""'(I
\+
.;

,

,.

?r;.~

~.,.;'"

"

~"'~7"'~",.'"

o

1

10

NOTE:
R13 -18 = 3.6kO

Figure 5. Voltage at Field-Strength Indicator Output (Proportional to V12-18l

/1
/1

/

FM'oJ,/\

/ I
I

/

1/
-40

-80 o

I

-40

V

-60

0.2

0.4

".\.,l=ott
1)1 RI••1O =24OkQ
11(Ra.1O =180kQ
1 \ (1)

f-J-

I

\ f-I-

L

-Jl-

-60
FM'off'

0.6

0.8

-80 o

I

'I

i'.

o

-200

-100

+100

+200

.II (kHz)

Figure 6. Attenuation of Output Voltage
("'Vol as a Function of the Muting
Control Voltage V 11 - 18

January 14, 1987

Figure 7. FM 'on'/FM 'off'
Standby Switch; Attenuation of
Output Voltage ("'Vol as a Function of
Control Voltage Vs -18

4-160

NOTES:
1. Limited by external preset (0: • V12 _1S).

Figure 8. Detune-Detector Output
Voltage Vee 7.5 to 20V; Ql 20

=

=

Signetics Linear Products

Product Specification

FM-IF (Quadrature Detector)

33pF

TDA1576

r---..,
I

I

r-----,
I
I
1--1--+-..---+---,

39pF

I

I

I

I

1k

TDA1578

580pF

I

L21

I

I
I

I

39pF

9
CS-9

NOTES,
Adjustment of the demodulator circuit is obtained with an IF signal which is higher than the 3dS limiting level; L2 should be short-circuited or detuned, L1 should be adjusted to min. d2
distortion, and then 12 to min. d2 distortion. Coil data: L1 "" L2 = Q.SS/AH; 00 = 70; coil former KAN (C).

Figure 9. Example of the TDA1576 When Using a Demodulator With Two Tuned Circuits

0.3

~

0.1

o

-75

~1----- ----V

-50

+25

-25

/
+50

('o=10.7MHz)

NOTES,
1M = 400Hz; C8 _9 "" 6.8nF; Af = ± 75kHz; Vo = 330mV for a frequency deviation 6.f "'" ± 75kHz.

Figure 10. Total Distortion as a Function of Detunlng

January 14, 1987

4-161

+75
"(kHz)

•

Signetics Linear Products

Product Specification

TDA1576

FM-IF (Quadrature Detector)

r-,
R5
~ I 4.7k

-::FMIIF
INPUT
V,

J1C4

A 1mA

R6
220k

rR~

V REF

C6
O.I"F

O.1/AF

C3
O.I"F

.---'VVIr--

VF

DETUNE·
VOLTAGE

R3
3.6k

n~o
-=-

C6

,J1nF

O.47",F

R.

16

17

16

15

14

13

12

11

10

R9
180k

TDA1576

C9

Vee
~

rO.1"F

Rl
10

33pF

C7
580pF

+

Cll~)

C2

147"F

RIO
'40k

R2
750

FMON

Cl.

+
AFC
VOLTAGE

NOTES:
1. For mono: ell

=

6.8nF; for stereo: ell

=

56pF.

Figure 11. Application Example of Using TDA1576

January 14, 1987

4-162

Vo
(AF)

SAB1164/65

Signetics

1GHz Divide-by-64 Prescaler
Product Specification

Linear Products
DESCRIPTION

FEATURES

This silicon monolithic integrated circuit
is a prescaler in current-mode logic. It
contains an amplifier, a divide-by-64
scaler and an output stage. It has been
designed to be driven by a sinusoidal
signal from the local oscillator of a
television tuner, with frequencies from
70MHz up to 1GHz, for a supply voltage
of 5V ± 10% and an ambient temperature of 0 to 70°C. It features a high
sensitivity and low harmonic contents of
the output signal.

• 3mV (typ) sensitivity
• Differential inputs
• AC input coupling; internally
based
• Outputs edge-controlled for low
RFI
• Power consumption: 210mW (typ)
• Mini-DIP package
• Low output impedance (SAB1165)

PIN CONFIGURATION

1C08vee
C12

7QL

C23

8QH

VEE

4

5

VEe

TOP VIEW

APPLICATIONS
• PLL or FLL tuning systems, FM/
communications/TV
• Frequency counters

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

o to
o to

8-Pin Plastic DIP (SOT-97 A)
8-Pin Plastic DIP (SOT-97 A)

BLOCK DIAGRAM

ORDER CODE

+70°C

SAB1164N

+70°C

SAB1165N

Vee
8

L
C1

C2

~r-

e-!r-

[>

-c

a

r---

+64

-c

Of--

I

[>

r-r!-o
r-~

I

I
5

4

NOTE,
Divide-by-64 = 6 binary dividers

December 2, 1986

4-163

853-1 026 86699

Product Specification

Signetics Linear Products

1GHz Divide-by-64 Prescaler

SAB1164/65

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

Vcc

Supply voltage (DC)

V,

Input voltage

TSTG

Storage temperature range

TJ
(JeA

RATING

UNIT

7

V

o to Vce

V

-65 to +125

·C

Junction temperature

125

·C

Thermal resistance from crystal to
ambient

120

·C/W

DC ELECTRICAL CHARACTERISTICS Vee = OV (ground); Vee = 5V; TA = 25·C, unless otherwise specified.
The circuit has been designed to meet the DC specifications as shown below, after thermal equilibrium has been established. The circuit is in a
test socket or mounted on a printed-circuit board.
LIMITS
SYMBOL

UNIT

PARAMETER

Min
VOH
VOL

Output voltage
HIGH level
LOW level

lec

Supply current

Typ

42

Max
Vee
Vee- O.B

V
V

50

mA

AC ELECTRICAL CHARACTERISTICS Vee = OV (ground); Vee = 5V± 10%; TA = 0 to + 70·C
LIMITS
SYMBOL

PARAMETER

UNIT
Min

V'(RMS)

Input voltage RMS value (see Figure 2)
input frequency 70MHz
150MHz
300MHz
500MHz
900MHz
lGHz

Typ

Max

9
4
3
3
2
3

17.5
10
10
10
10
17.5

mV
mV
mV
mV
mV
mV

200

mV

V'(RMS)

Input overload voltage RMS value
input frequency range 70MHz up to 1GHz

VO(p.P)

Output voltage swing

Ro
Ro

Output resistance
SAB1164
SAB1165

f:J.Vo

Output unbalance

tTLH

Output rise time 1
f, = lGHz

25

ns

tTHL

Output fall time 1
f, = lGHz

25

ns

O.B

1

V

1
0.5

kU
kU
O.t

V

NOTE:
1. Between 10% and 90% of observed waveform.

FUNCTIONAL DESCRIPTION
The circuit contains an amplifier, a divide-by64 scaler and an output stage. It has been
designed to be driven by a sinusoidal signal
from the local oscillator of a TV tuner, with
frequencies from 70MHz up to 1GHz, for a
supply voltage of 5V ± 10% and an ambient
temperature of 0 to + 70·C.

December 2, 19B6

The inputs are differential and are internally
biased to permit capacitive coupling. For
asymmetrical drive the unused input should
be connected to ground via a capacitor.

The output differential stage has two complementary outputs. The output voltage edges
are slowed down internally to reduce the
harmonic contents of the signal.

The first divider stage will oscillate in the
absence of an input signal; an input Signal
within the specified range will suppress this
oscillation.

Wide, low-impedance ground connections
and a short capacitive bypass from the Vee
pin to ground are recommended.

4·164

Signetics Linear Products

Product Specification

SAB1164j65

1GHz Divide-by-64 Prescaler

HYBRID JUNCTION

1000

}

~SC'LLOSCOPE

50

GUARANTEED
OPERATING AREA

Vh
10

4,S

t--------------lOnH
rvvv-.

Vcc=5V

±10nF

±O.47"F

8

~~~ )

~-=

10nF

2

6

10nF

3

7

l~

---l~

-=

rr

I

TOTUNING
SYSTEM
(TWISTED LEADS)

VEE=OV
TC15500S

NOTE:
TV tuning system. The output peak-to-peak voltage is about 1V.

Figure 6. Circuit Diagram

December 2, 1986

4-167

SAB1256

Signetics

1GHz Divide-by-256 Prescaler
Product Specification

Linear Products

PIN CONFIGURATION

DESCRIPTION

FEATURES

This silicon monolithic integrated circuit
is a prescaler in current-mode logic. It
contains an amplifier, a divide-by-256
scaler and an output stage. It has been
designed to be driven by a sinusoidal
signal from the local oscillator of a
television tuner, with frequencies from
lOMHz up to 1GHz, for a supply voltage
of 5V± 10% and an ambient temperature
of 0 to lO°C. It features a high sensitivity
and low harmonic contents of the output
signal.

• 3mV (typ.) sensitivity
• AC input coupling, internally
biased
• Outputs edge-controlled for low

N Package

IC08vee

RFI
• 235mV typical power dissipation
• Low output impedance""1kr2

C12

TQL

C23

6QH

VEE

4

5

VEE

TOP VIEW

APPLICATIONS
• PLL or FLL tuning systems,
FM/ communications/TV
• Frequency counters

ORDERING INFORMATION
DESCRIPTION

ORDER CODE

TEMPERATURE RANGE

8-Pin Plastic DIP (SOT-97)

SAB1256N

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

RATING

UNIT

7

V
V

Vee
VI

Supply voltage (DC)

TSTG

Storage temperature range

-65 to +150

'C

TJ

Junction temperature

125

°C

eCA

Thermal resistance from crystal to
ambient

120

'C/W

o to Vce

Input voltage

BLOCK DIAGRAM
Vee
8

l
C1

C2

o-!I-

o---!I- [>

I
Qt--

-C
+258

-c:

"0:1--

I-~

I

I
4

[> I-r!--<>

5

NOTE:
Divide-by-256 - 8 binary dividers.

December 2, 1986

4-168

853-1052 86702

Signetlcs linear Products

Product Specification

1GHz Divide-by-256 Prescaler

SAB1256

DC ELECTRICAL CHARACTERISTICS VEE = OV (ground); Vcc = 5V; TA = 25°C, unless otherwise specified. The circuit has
been designed to meet the DC specifications as shown below, after thermal
equilibrium has been established. The circuit is in a test socket or mounted on a
printed-circuit board.
LIMITS
PARAMETER

SYMBOL

UNIT
Min

VOH

Typ

Output voltage
HIGH level

VOL

LOW level

Icc

Supply current

Max

Vcc

47

V

Vee- 0.8

V

55

mA

AC ELECTRICAL CHARACTERISTICS VEE = OV (ground); Vee = 5V ± 10%; T A = O°C to + 70°C.
LIMITS
SYMBOL

UNIT

PARAMETER
Min

VI(RMS)

Input voltage RMS value (see Figure 2)
Input frequency 70MHz
150MHz
300MHz
500MHz
900MHz
1GHz

VI(RMS)

Input overload voltage RMS value
input frequency range 70MHz to 1GHz

VO(p.P)

Output voltage swing

0.8

Typ

Max

9
4
3
3
2
3

17.5
10
10
10
10
17.5

mV
mV
mV
mV
mV
mV

200

mV

1

V

1

kn

Ro

Output resistance

AVo

Output unbalance

tTLH

Output rise time 1
fl = lGHz

40

ns

tTHL

Output fall time
fl = lGHz

40

ns

0.1

V

NOTE:
1, Between 10% and 90% of observed waveform.

FUNCTIONAL DESCRIPTION
The circuit contains an amplifier, a divide-by256 scaler and an output stage. It has been
designed to be driven by a sinusoidal signal
from the local oscillator of a TV tuner, with
frequencies from 70MHz up to 1GHz, for a
supply voltage of 5V ± 10% and an ambient
temperature of 0 to 70°C.

December 2, 1986

The inputs are differential and are internally
biased to permit capacitive coupling. For
asymmetrical drive the unused input should
be connected to ground via a capacitor.

The output differential stage has two complementary outputs. The output voltage edges
are slowed down internally to reduce the
harmonic contents of the signal.

The first divider stage will oscillate in the
absence of an input signal; an input signal
within the specified range will suppress this
oscillation.

Wide, low-impedance ground connections
and a short capacitive bypass from the Vcc
pin to ground are recommended.

4-169

II

Signetlcs Linear Products

Product Specification

SAB1256

1GHz Divide-by-256 Prescaler

HYBRID JUNCTION

SI~~.1~~~

)-++__-1

GENERAlOR

R,=502
(-3dO)

~
(-:dO)

t-++----lIr---=-J+
}

~LLOSCOPE

50

4.5

t------------~---~---_o

VEE=OV

TC153QOS

NOTES:

SOn

Cables must be
coaxial.
The capacitors are leadless ceramic (multi-layer capacitors) of 10nF.
All conshort and of approximately equal lengths. short and of approximately equal lengths.
Hybrid junction is ANZAC H-183-4 or similar.

Figure 1. Test Circuit for Defining Input Voltage

1000

$'100

.s

!

>"

-

O;EU:A~~ci~~'h

10

1

...... I II
o

600

1200

',(MHz)

Figure 2. Typical Sensitivity Curve Under Nominal Conditions

December 2. 1986

4-170

Signetics Linear Products

Product Specification

1GHz Divide-by-256 Prescaler

SAB1256

..
I

NOTE:
V!(AMS) =- 25mV; Vee

=

5V; reference value

=

son
Figure 3. Smith Chart of Typical Input Impedance

December 2, 1986

4-171

Signetics Linear Products

Product

SAB1256

1GHz Divide-by-256 Prescaler

}

DIFFERENTIAL
INPUTS

I

2k

~VtDERS

2k

+-__

__~__________

~3

~

Figure 4. Input Stage

lk

I'L--+----C

"U--+----+----I
'-------+--------1.:.....0 VEE
NOTE:
Vee" 5V; 1== 1mA.

Figure 5. Output Stage

December 2, 1986

Spec~ication

4-172

Product Specification

Signetics Linear Products

SAB1256

1GHz Divide-by-256 Prescaler

>1OnH
r---t-----JTTT~----~--------__oVCC=5V

J

10nF

10nF

~~D>--Qf--=-+-il

I

TOTUNING
SYSTEM

10nF

(TWISTED LEADS)

/----+-

t------------------------4-----+----------~VEE=OV

Figure 6. Circuit Diagram

December 2, 1986

•
I

NOTE:
Application in a television tuning system. The output peak-ta-peak voltage is about 1V.

4-173

HEF4750V

Signetics

Frequency Synthesizer
Product Specification

Linear Products

PIN CONFIGURATION

DESCRIPTION

FEATURES

The HEF4750V frequency synthesizer is
one of a pair of LOCMOS devices,
primarily intended for use in high-performance frequency synthesizers; e.g., in
all communication, instrumentation, television and broadcast applications. A
combination of analog and digital techniques results in an integrated circuit
that enables high performance. The
complementary device is the universal
divider type HEF4751V.

• Wide choice of reference
frequency using a single crystal
• High-performance phase
comparator -low phase -low
noise spurii
• System operation to > lGHz
• Typical l5MHz input at 10V
• Flexible programming:
- frequency offsets
- ROM compatible
- fractional channel capability
• Program range 6 Y2 decades,
including up to 3 decades of
prescaler control
• Division range extension by
cascading
• Built-In phase modulator
• Fast lock feature
• Out-of-Iock indication
• Low power dissipation and high
noise immunity

Together with a standard prescaler, the
two LOCMOS integrated circuits offer
low-cost single-loop synthesizers with
full professional performance.

APPLICATIONS
Some examples of applications for the
HEF4750V in combination with the
HEF4751V are:
• VHF/UHF mobile radios
• HF SSB transceivers
• Airborne and marine
communications and navaids
• Broadcast transmitters
• High quality radio and television
receivers
• High-performance citizens band
equipment
• Signal generators

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

28-Pin Cerdip

_40°C to + 85°C

HEF4750VDF

28-Pin Cerdip

-55°C to +125°C

HEC4750VDF

November 6, 1986

4-174

F Package

OUT

NS,

Ns"
OSC
XTAL

Ao
A,

"'"
"'"

V..
lOP VIEW
PIN
NO.

1
2
3

SYMBOL

10

V
STB
TCB
OL
TCA
TRA
TCC
PC,
PC,
Ao

11

A,

12

A,

13

Ao

15

Vss
A,

16

As

17

Ao

18

A,

19

Ao

•
5

6

7
8

9

DESCRIPTION
Phase comparator input
Strobe input
Timing capacitor CB pin

Out-of-Iock indication
Timing capacitor CA pin
Biasing pin (resistor RA)
Timing capacitor Cc pin
Analog phase comparator output
Digital phase comparator output
Programming inputs/programmable

divider
Programming inputs/programmable

divider

,.

20

A.

21
22
23
2'
25
26
27

XTAL
OSC
NSo
NS,
R
OUT
MOD

Programming inputs/programmable
divider
Programming inputs/programmable
divider
Programming inputs/programmable
divider
Programming inputs/programmable
divider
Programming inputs/programmable
divider
Programming inputs/programmable
divider
Programming inputs/programmable
divider
Programming inputs/programmable
divider
Reference oscillator/buffer output
Reference oscillator/buffer input
Programming inputs, prescaler
Programming inputs, prescaler
Phase comparator input. reference
Reference divider output
Phase modulation input

853-0905 86381

Signetics Linear Products

Product Specification

Frequency Synthesizer

HEF4750V

BLOCK DIAGRAM

14

28
OL

osc
22

At

XTAL NSo

21

23

10111213151617181920

24

OUT R

V

TCB MOD STB

TRA

TCA

4

TCC

28251327

u

PROGRAMMING INPUTS
REFERENCE DIVIDER

EXTERNAL CIRCUITRY
CRYSTAL STANDARD

NOTES:
1. PC 1 = analog output
2. PC 2 = 3-state output

Block Diagram Comprising Five Basic Functions: Phase Comparator 1 (PC1), Phase Comparator 2 (PC2),
Phase Modulator, Reference Oscillator and Reference Divider (These Functions are Described Separately)

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

Voo

Supply voltage

VI

Voltage on any input

±I
Po
Po

RATING

UNIT

-0.5 to + 15

V

-0.5 to Voo +0.5

V

DC current into any input or output

10

mA

Power dissipation per package for
TA = 0 to +85°C

500

mW

Power dissipation per output for
= 0 to +85°C

100

mW

TA

TSTG

Storage temperature range

-65 to +150

°C

TA

Operating ambient temperature
HEF4750V
HEC4750V

-40 to +85
-55 to + 125

°C
°C

November 6, 1986

4-175

Signetics Linear Products

Product Specification

Frequency Synthesizer

HEF4750V

HEF4750V, HEC4750V VDD = 10V±5%; voltages are referenced to Vss
less otherwise specified. For definitions see Note 1.

DC ELECTRICAL CHARACTERISTICS

= OV,

un-

LIMITS
SYMBOL

PARAMETER

TA =-40'C
Min

Typ

TA = +25'C
Min

Max

Typ

TA = +85'C
Max

Min

Typ

UNIT
Max

IDO

Quiescent device current2

100

100

750

!1A

± liN

Input current; logic
inputs, MOD3

300

300

1000

nA

± Iz

Output leakage current at
Y2 VOO3,4
TCA, hold-state
TCC, analog
switch OFF
PC2, high impedance
OFF-state

VIL
VIH

Logic input voltage
LOW
HIGH

VOL
VOH

Logic output vOltage3
LOW; at 1101 < 1!1A
HIGH

± Iz
± Iz

20

0.05

20

60

nA

20

0.05

20

60

nA

50

500

nA

0.3Voo

V
V

50

50
0.3VOO

0.3VOO

0. 7Voo

0.7Voo

0.7Voo

Voo-50mV

50
Voo-50mV

50
Voo-50mV

rnV
rnV

10L
10L

Logic output current LOW;
at VOL = 0.5V3
outputs OL, PC 2, OUT
output XTAL

5.5
2.8

4.6
2.4

3.6
1.9

rnA
rnA

-IOH
-IOH

Logic output current HIGH;
at VOH = VOO - 0.5V3
outputs OL, PC2, OUT
output XTAL

1.5
1.4

1.3
1.2

1.0
0.9

rnA
rnA

'0

Output TCC sink
currents, 4, 5

2.1

rnA

-10

Output TCC source
currents, 4, 6

1.9

rnA

RI

Internal resistance
of TCe
loutput swing I.;; 200mV
specified output range: 0.3
Voo to 0.7 VOo3, 4

0.7

kn

eN

Output TCC voltage
with respect to
TCA input voltage 3, 4, 7

10

Output PC1 sink
current3, 4, 9

1.1

rnA

-10

Output PC1 source
current3, 4, 9

1.0

rnA

RI

Internal resistance
of PC 1
loutput swing I.;; 200mV
specified output range:
0.3 VOO to 0.7 V003, 4

1.4

kn

November 6, 1986

0

0

4·176

0

V

Signetics Linear Products

Product Specification

Frequency Synthesizer

HEF4750V

DC ELECTRICAL CHARACTERISTICS (Continued) HEF4750V, HEC4750V voo = 10V± 5%; voltages are referenced to
Vss = OV, unless otherwise specified, For definitions see Note 1.
LIMITS
TA = -40'C

PARAMETER

SYMBOL

Min

tN

Output PCl voltage
with respect to
TCC input voltage3, 4, 10

VEOR

EaR generation
VEOR=VOO-VTCA3, 4, 8, 11

10
10

Source current; HIGH
at VOUT = 1,12 VOO;
output in ramp mode 3, 4
TCA
TCS

Typ

TA = +25'C
Max

Min

Typ

TA=+85'C
Max

Min

Typ

UNIT
Max

0

0

0

V

0.9

0.7

0.6

V

13
2.5

mA
mA

AC ELECTRICAL CHARACTERISTICS

General Note
The dynamic specifications are given for the circuit built-up with external components as given in Figure 6, under the following conditions; for
definitions see Note 1; for definitions of times see Figure 17; Voo = 10V± 5%; T A = 25'C; input transition times';; 20ns; RA = 68kn ± 30% (see
also Note 4); CA = 270pF; CB = 150pF; Cc = lnF; Co = 10nF; unless otherwise specified.
LIMITS
PARAMETER

SYMBOL

TEST CONDITIONS

UNIT

Min
STCA
STCA
STCB
STCB

Slew rate 11
TCA
TCA
TCS
TCS

ITCA
ITCB

Ramp linearity13
TCA
TCS

RA= minimum
RA = maximum
RA = minimum
RA= maximum

Typ

Max

52
28
20
10

V/p.s
V/p.s
V/p.s
V/p.s

2

2

%
%

tcsCA

Start of TCA ramp delay

200

ns

tRCA

Delay of TCA hold

40

ns

tVCA

Delay of TCA discharge

60

ns

tvcs

Start of TCS ramp delay

60

ns

tres

TCS ramp duration

250
350
450

ns
ns
ns

VMoo=4V
VMOO = 6V
VMOO = 8V

trCB

Required TCS min. ramp duration 14

150

ns

tpwvL
tPWVH

Pulse width
V: LOW
V: HIGH

20
20

ns
ns

tPWRL
tpWRH

R: LOW
R: HIGH

20
20

ns
ns

tpWSL
tPWSH

STS: LOW
STS: HIGH

20
20

ns
ns

50
50

ns
ns

tfCA
tICS

Fall time
TCA
TCS

November 6, 1986

4-177

Signetics Linear Products

Product Specification

Frequency Synthesizer

HEF4750V

AC ELECTRICAL CHARACTERISTICS (Continued)
LIMITS
SYMBOL

PARAMETER

TEST CONDITIONS

UNIT
Min

Typ

Max

fpR

Prescaler input frequency

All division ratios

30

MHz

fDIV

Binary divider frequency

All division ratios

30

MHz

fosc

Crystal oscillator frequency

10

MHz

Icc
Icc

Average power supply current
with speed-up 1:1015
without speed-up 16

3.6
3.2

mA
mA

Locked state

NOTES:

1. Definitions:
RA - external biasing resistor between pins TRA and Vss ; 68 kil± 30%.
CA = external timing capaCitor for time/voltage converter, between pins TCA and Vss.
Cs - external timing capacitor for phase modulator, between pins TCB and Vss.
Cc - external hold capacitor between pins TCC and Vss.
Co - decoupling capacitor between pins TRA and Voo.
Logic inputs: V, R, STB, A" to A9, NSo, NSJ, OSC.
Logic outputs: OL, PC2 , XTAL, OUT.
Analog signals: TCA, TCB, TCC and MOD.
2. TRA at Voo; TCA, TCB, TCC and MOD at Vss; logic inputs at Vss or Voo.
3. All logic inputs at Vss or Voo.
4. RA connected; its value chosen such that ITRA - 1001lA.
5. The analog switch is in the ON position
(see Figure 1).

Figure 1. Equivalent Cicuit for Note 5
6. The analog switch is in the ON position
(see Figure 2).

Figure 2_ Equivalent Circuit for Note 6
7. This guarantees the DC voltage gain,
combined with DC offset. Input condition:
0.3Voo';; VTCA';; 0.7Voo. !:N - VTce - VTCA.

V DD

10k

leC
ANALOG
SWlleH

10k

Figure 3. Circuit for Note 7
8. See Figure 4.

Figure 4. Equivalent Circuit for PCl Sink Current
November 6, 1986

4-178

Signetics linear Products

Product Specification

HEF4750V

Frequency Synthesizer

9. See Figure 5.
OO

~
~

Tee

pc,

1.

Vss

Figure 5. Equivalent Circuit for PC 1 Source Circuit
10. This guarantees the DC voltage gain, combined with DC offset.
Input condition: 0.3 VDD :::;;:; Vrcc < O.7VDD.
{!.v ~ VPC1 - VTCC.

20k

20k

Figure 6. Circuit for Note 10
11. Switching Jevel at TeA, generating an Ex-OR
signal, during increasing input voltage.

12. See Figure 7.

,
70% VOOj

l
SPEClFIEO
RANGE

,---='F
t =----

30% VOO~

Figure 7. Waveform at the Output
13. Definition of the ramp linearity at full swing. See
Figure 8.

70% VO• ----~"
3O%VDD

NOTE:
flY
Linearity = 1J2 VDO X 100%

Figure S. /}, V is the Maximum Deviation of the Ramp Waveform to the Straight
Line, Which Joins the 30% Voo and 70% Voo Points
14. The external components and modulation input
voltage must be chosen such that this requirement will be fulfilled, to ensure that CA is
sufficiently discharged during that time.

November 6, 1986

4-179

Product Specification

Signetics Linear Products

HEF4750V

Frequency Synthesizer

15. Circuit connections for power supply current
specification, with speed-up 1: 1O. V and A are in

the range of PC" such that the output voltage at
PC, is equal to 5V.
fose = 5MHz (external clock)
fSTB = t2.5kHz
fv -125kHz

r---------~------~---+~V

DIVISION

RATlO-~

+5V

PC,

R

J'"L.
J'"L.

HEF4750V

V

PC.

STB
.".

Vss
TRA

OL
TCA

TCB

TCC

OSC XTAL

Cc

J1..

Figure 9. Circuli for Nole 15
16. Circuit connections for power supply current
specification, without speed-up. V and R are in
the range of PC" such that the output voltage at
PC, is equal to 5V.
fose = 5MHz (external clock)
fSTB - 12.5kHz
fv - 12.5kHz

+~V

Ns"
Voo
+5V

DIVISION RATIO - 400

MOD

Pc,

R

J'"L.
J'"L.

Nil,

HEF4750V

V

Pc.

STB
.".

Vss
TRA

R•

.".

Figure 1O. Circuil for Nole 16

November 6, 1986

4·180

OL

Product Specification

Signetics Linear Products

HEF4750V

Frequency Synthesizer

pc,

R
HEF4750V

V

pc.

STB
OL

Vss
TRA

Figure 11. Test Circuit for Measuring AC Characteristics

FUNCTIONAL DESCRIPTION
Phase Comparator 1
Phase comparator 1 (PC 1) is built around a
SAMPLE and HOLD circuil. A negative·going
transition at the V input causes the hold
capacitor (C A) to be discharged and, after a

specified delay, caused by the Phase Modula·
tor by means of an interna'i V' pulse, it
produces a positive·going ramp. A negativegoing transition at the R input terminates the
ramp. Capacitor CA holds the voltage that the
ramp has attained. Via an internal sampling
switch this voltage is transferred to Cc and in

I
---------,I

v

R

turn buffered and made available at output
PC 1·
If the ramp terminates before an R input is
present, an internal end of ramp (EaR) signal
is produced. These actions are illustrated in
Figure 12.

I

I- ~~~~':.:~~~~~~E ~
v

~".

TCA
(ANALOG)

I\,
-HOLD

...

voo

...... ......

j

/
RESET

VOLTAGE
TRANSFERRED TO TCC
RAMP

HOLD

EOR

Vss

t

,------------I

ANALOG
SAMPLING --ON
ON
OFF
SWITCH'S, - - O N - l - - , - - - - - - - O F F - - - - - - - - - + - - - O N - - - - - - - - - - -

~NA~

_________________________

...... ......

...... ......

... _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____

dC~~

Figure 12. Waveforms Associated With PC1

November 6, t 986

4-181

Signetics Linear Products

Product Specification

Frequency Synthesizer

The result phase characteristic is shown in
Figure 13. PCl is designed to have a high
gain, typically 3200 V/cycle (at 12.5kHz). This
enables a low noise performance.

Phase Comparator 2
Phase comparator 2 (PC2) has a wide range,
which enables faster lock times to be
achieved than otherwise would be possible. It
has a linear ± 360·C phase range, which
corresponds to a gain of typically 5V Icycle.
This digital phase comparator has three stable states:
• Reset state

HEF4750V

ouJ~tI

VOIJ"AGE

Figure 13. Phase Characteristic of PCl

• V' leads R state
• R leads V' state
Conversion from one state to another takes
place according to the state diagram of Figure 14.
Output produces positive or negative-going
pulses with variable width; they depend on
the phase relationship of R and V'. The
average output voltage is a linear function of
the phase difference. Output PC2 remains in
the high-impedance OFF state in the region in
which PC l operates. The resultant phase
characteristic is shown in Figure 15.

ACTIVE R·EDGE
(NEGATIVE GOING)

ACTIVE R·EDGE
(NEGATIVE GOING)

ACTIVE ,,"EDGE
(NEGATIVE GOING)

ACTIVE V·EDGE
(NEGATIVE GOING)

Figure 14. State Diagram of PC2

Strobe Function
The strobe function Is intended for applications requiring extremely fast lock times. In
normal operation the additional strobe input
(STB) can be connected to the V input and
the circuit will function as described in the
previous sections.
In single, phase-locked loop type frequency
synthesizers, the comparison frequency generally used is either the nominal channel
spacing or a sub-multiple, PC2 runs at the
higher frequency (a higher reference frequency must also be used), while strobing takes
place on the lower frequency, thereby obtaininga decrease in lock time. In a system using
the Universal Divider HEF4751V, the output
OFS cycles on the lower frequency, the
output OFF cycles on the higher frequency.

Out-of-Lock Function
There are a number of situations in which the
system goes from the locked to the out-oflock state (OL goes HIGH):
1. When V' leads R, however out of the range
of PC1.
2. When R leads V'.
3. When an R pulse is missing.
4. When a V pulse is missing.
5. When two successive STB commands
occur, the first without corresponding V signal.

Phase Modulator
The phase modulator only uses one external
capacitor, Ca at pin TCB. A negative-going
November 6, 1986

_/

Figure 15. Phase Characteristics of PC2
transition at the V input causes Ca to produce
a positive-going linear ramp. When the ramp
has reached a value almost equal to the
modulation input voltage (at MOD), the ramp
terminates, CB discharges and a start signal
to the CA ramp at TCA is produced. A linear
phase modulation is reached in this way. If no
modulation is required, the MOD input must
be connected to a fixed voltage of a certain
positive value up to VDD. Care must be taken
that the V' pulse is never smaller than the
minimum value to ensure that the external
capacitor of PC1(CA) can be discharged during that time. Since the V' pulse width is
directly related to the TCB ramp duration,
there is a requirement for the minimum value
of this ramp duration.

Reference Oscillator
The reference oscillator normally operates
with an external crystal as shown in the block
diagram. The internal circuitry can be used as
a buffer amplifier in case an external reference should be required.

4-182

Reference Divider
The reference divider consists of a binary
divider with a programmable division ratio of
l-to-l024 and a prescaler with selectable
division ratios of 1, 2, 10 and 100, according
to the following tables:
Binary divider
N (Ao TO Ag)

DIVISION RATIO

0
0 1GHz
• Typical 15MHz input at 10V
• Flexible programming:
frequency offsets
ROM compatible
fractional channel capability
• Program range 6.5 decades,
including up to 3 decades of
prescaler control
• Division range extension by
cascading
• Built-in phase modulator
• Fast lock feature
• Out-of-Iock Indication
• Low power dissipation and high
noise Immunity

The system comprising one HEF4751V
UD together with prescalers is a fullyprogrammable divider with a maximum
configuration of 5 decimal stages, a
programmable mode M stage
(1 :;;; M :;;; 16, non-decimal fraction channel selection), and a mode H stage
(H = 1 or 2, stage for half-channel offset). Programming is performed in BCD
code in a bit-parallel, digit-serial format.
To accommodate fixed or variable frequency offset, two numbers are applied
in parallel, one being subtracted from
the other to produce the internal program. The decade selection address is
generated by an internal program counter which may run continuously or on
demand. Two or more universal dividers
can be cascaded. Each extra UD (in
slave mode) adds two decades to the
system. The combination retains the full
programmability and features of a single
UD. The UD provides a fast output signal
flip-flop at output OFF, which can have a
phase jitter of ± 1 system input period, to
allow fast frequency locking. The slow
output signal FS at output OFS, which is
jitter-free, is used for fine phase control
at a lower speed.

PIN CONFIGURATION

APPLICATIONS
• VHF/UHF mobile radios
• HF SSB transceivers
• Airborne and marine
communications and navigations
• Broadcast transmitters
• High quality radio and television
receivers
• Signal generators

F,N Packages

00,
OD,

82

PE

pc

TOP VIEW
PIN
NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

DESCRIPTION

SYMBOL

~,

"'-,
"'-,

~.

150,
1504
150,
150,
150,
1500
PE

PC
Vss
SI

!!o
B,
!!,

B,
IN
15§Y

} Da1a inpu1s

)-~-Program enable
Program clock

} Borrow inpu'
Data inputs
Input
Sync output

Oi'B,
OFB2 } Prescaler control outputs

0i'B,
OFS

Ai
OFF

Output signal (slow)
Rate input
Output signal (FAST)

VDD

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

28-Pin Plastic DIP (SOT-117)

-40'C to

+ 85'C

HEF4751VPN

28-Pin Cerdip (SOT-135A)

-55'C to

+ 125'C

HEC4751VDBF

November 14, 1986

4-184

853·0107 86553

Product Specification

Signetics Linear Products

HEF4751V

Universal Divider

BLOCK DIAGRAM
SI

4

3

2 1

15

4

m>o - - - - - - 00.
11 10 9

8

7

8

PC

PE

13

5

12

I

SUBTRAC1O~

18
17
18
19

,---- I

de"]

OSY

21

d. d.
LDAD PULSES

de
de

1

I

rt-

+1.2,5, 10/11

+nml /nm.+1

~
I

RS4

n.

+110

~

LATCH

lis

~cIo

ii

RS2

10
LATCH
H

:--

--(;4-+H

r- ~ OFS
27

I

1-4
RSO

r-----

LATCH

n,

+M

t

I

{4

LA~H

~

-----

f4

RS1

! 28

de

I

LATCH

ii

RS3

~

22

I

~d.

~ ~ ~ ~

I
I

23

C3

+10

~
I
I

24

r-----

I

C2

C1

J -1-)

!

t
LATCH
M

om.

RS
SWITCHES

November 14, 1986

---,

LATCH

r----H. r----- -I
PR~ER 1
o

t

110 II, do 110

a..a. 1

LATCH

20

PROGRAM
COUNTER

"~T----Ity
21
J tt tt

C
D
0
CARRYFF

4

IN

PROGRAM DECODER

-II,

!14

4-185

do_

4':-a,

LATCH

no

de':

RSH

-LATCii'n"

i-' !!..o

OFF

Signetics Linear Products

Product Specification

Universal Divider

HEF4751V

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

Voo

Supply voltage

VI

Voltage on any input

±I

RATING

UNIT

-0.5 to +15

V

-0.5 to Voo + 0.5

V

DC current into any input or output

10

mA

PTOT

Total power dissipation per package
for TA = 0 to +85'C

500

mW

Po

Power dissipation per output for
TA = 0 to +85'C

100

mW

TSTG

Storage temperature range

-65 to +150

'C

TA

Operating ambient temperature range

-40 to +85

'C

DC ELECTRICAL CHARACTERISTICS

Vss

= ov
LIMITS

SYMBOL

PARAMETER

VDo
(V)

VOH
(V)

VOL
(V)

TA

= -40'C

Min
IOL

-IOH

Output (sink)
current LOW
Output (source)
current HIGH

4.75
5
10
5
5
10

AC ELECTRICAL CHARACTERISTICS
SYMBOL
tpHL

PARAMETER
Propagation delay
IN ..... OSY
HIGH-to-LOW

0.4
0.4
0.5
4.6
2.5
9.5

Max

TA

= +25'C

Min

TA

Max

= +85'C

Min

UNIT

Max

1.6
1.7
2.9

1.4
1.5
2.7

1.1
1.2
2.2

mA
mA
mA

1.0
3.0
3.0

0.85
2.5
2.5

0.55
1.7
1.7

mA
mA
mA

Vss = OV; TA = 25'C; input transition times';; 20ns.

TEST CONDITIONS

Voo
(V)

LIMITS
UNIT
Min

Typ

Max

CL = 10pF

5
10

135
45

270
90

ns
ns

5
10
5
10

30
12
45
20

60
25
90
40

ns
ns
ns
ns

Output transition times
tTHL

HIGH-to-LOW

CL = 50pF

tTLH

LOW-to·HIGH

CL

fMAX

Maximum input frequency; IN

fMAX

Maximum input frequency; IN

fMAX

Maximum input frequency; PC

= 50pF

0=50%

1 COb ratio> 1
0=50%
1 COb ratio = 1

5
10

4
12

8
24

MHz
MHz

5
10

2
6

4
12

MHz
MHz

5
10

0.15
0.5

0.3
1.0

MHz
MHz

Typical Formula for P (j.lW)
Po

Dynamic power dissipation per
package (P) 1

5V
10V

NOTE:
fl = input frequency (MHz)
fo = output frequency (MHz)
CL = load capacitance (pF)
~ (foCLl = sum of outputs
VDD = supply voltage (V)

November 14, 1986

4-186

1 200 fl + ~ (foCd X Voo2
5 400 fl + ~ (foed X Voo2

Product Specification

Signetics Linear Products

HEF4751V

Universal Divider

,----------.-OFF
C3
INPUT

I

+10/11

I

I
L

".
RS3

OFB;,

--<>-~----I

•

"3

RS2

"2

RSO

RS1

EXTERNAL PRESCALER

UNIVERSAL DIVIDER

",

NOTES,

1";;;M';;;;16; 1.:s;;;H~2; n5>O; VfOFS=j(ns'104+n4'103+n3'102+n2'10+n1) M+nol H+nh_

Figure 1. The HEF4751V UD Used in a System With 3 (Fast) Prescalers

November 14, 1986

C4

OFS

(f~

4-187

Signetics Linear Products

Product Specification

Universal Divider

HEF4751V

I

OD,

r--

-

r--

Figure 2. Timing Diagram Showing Program Data Inputs

November 14, 1986

4-188

Product Specification

Signetics Linear Products

HEF4751V

Universal Divider

Allocation of Data Input
INPUTS

FETCH
PERIOD

A3

A1

A2

0
1
2
3
4
5

nOA
n1A
n2A
n3A
n4A
nSA

6

M

Allocation of Data Input

Ao

B3

B2

B1

S1

Bo

nOB
n1B
n2B
n3B
n4B
nSB
COb
control

bin

X
X
X
X
X
1,12 channel

I

X

control

8a to 8 0 During Fetch Period 6

83

82

COb DIVISION RATIO

81

80

L
L
H
H

L
H
L
H

1
2
5
10/11

L
L
H
H

L
H
H
L

b

CHANNEL CONFIGURATION
H=1
H = 2; nh = 0
H = 2; nh = 1
test state

H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial

PROGRAM DATA INPUT (see
also Figures 1 and 2)

P = A - B - bin or if this result is negative;
P=A-B-bin+M'lOs

The programming process is timed and controlled by input PC and PE. When the program enable (PE) input is HIGH, the positive
edges of the program clock (PC) signal step
through the internal program counter in a
sequence of 8 states. Seven states define
fetch periods, each indicated by a LOW signal
at one of the corresponding data address
outputs (000 to OOs). These data address
signals may be used to address the external
program source. The data fetched from the
program source is applied to inputs Ao to A3
and Bo to B3. When PC is LOW in a fetch
period, an internal load pulse is generated.
The data is valid during this time and has to
be stable. When PE is LOW, the programming
cycle is interrupted on the first positive edge
of PC. On the next negative edge at input PC,
fetch period 6 is entered. Data may enter
asynchronously in fetch period 6.

The numbers A and B, each consisting of six
four bit digits nA to nSA and nOB to nSB, are
applied in fetch period 0 to 5 to the inputs Ao
to A3 (data A) and Bo to B3 (data B) in binary
coded negative logic.

Ten blocks in the UD need program input
signals (see Block Diagram). Four of these
(COb, C3, C4 and RSH) are concerned with
the configuration of the UD and are programmed in fetch period 6. The remaining
blocks (RSO to RS4 and Cl) are programmed
with number P, consisting of six internal digits
no to ns·
P = (ns • 104 + n4 • 103 + n3 • 102 + n2 •
10+n1)' M+no
These digits are formed by a substractor from
two external numbers A and B and a borrowin (bin).
November 14, 1986

A= (nSA • 104 + n4A • 103 + n3A
102 +n2A' 10+n1A)' M+nOA
B = (nSB' 104 + n4B • 103 + n3B • 102 + n2B'
10+n1B)'M+nOB
Borrow-in (bin) is applied via input SI in fetch
period 0 (SI = HIGH: borrow; SL = LOW: no
borrow).
Counter Cl is automatically programmed with
the most significant non-zero digit (n ms) from
the internal digits ns to n2 of number P. The
counter chain C - 2 to Cl (Figure 1) is fully
programmable by the use of pulse rate feedback.
Rate feedback is generated by the rate selectors RS4 to RSO and RSH, which are programmed with digits n4 to no and nh, respectively. In fetch period 6 the fractional counter
C3, half-channel counter C4 and COb are
programmed and configured via data B inputs. Counter C3 is programmed in fetch
period 6 via data A inputs in negative logic
(except all HIGH is understood as: M = 16).
The counter CO is a side steppable 10/11
counter composed of an internal part COb and
an external part COa. COb is configured via B3
and B2 to a division ratio of 1 or 2 or 10/11;
CO. must have the complementary ratio 10/

4-189

11 or 5/6 or 2/3 or 1, respectively. In the
latter case, COb comprises the whole CO
counter with internal feedback. COa is then
not required.
The half channel counter C4 is enabled with
Bo = HIGH and disabled with Bo = LOW. With
C4 enabled, a half channel offset can be
programmed with input B1 = HIGH, and no
offset with B 1 = LOW.

FEEDBACK TO PRESCALERS
(see also Figures 3 and 4)
The counters Cl, CO, C - 1 and C - 2 are
side-steppable counters, i.e., their division
ratio may be increased by one, by applying a
pulse to a control terminal for the duration of
one division cycle. Counter C2 has 10 states,
which are accessible as timing signals for the
rate selectors RSl and RS4. A rate selector,
programmed with n (n1 to n4 in the UD)
generates n of 10 basic timing periods an
active signal. Since n .;; 9, 1 of 10 periods is
always non-active. In this period RSl transfers the output of rate selector RSO, which is
timed by counter C3 and programmed with
no. Similarly, RSO transfers RSH output during one period of C3. Rate selector RSH is
timed by C4 and programmed with nh. In one
of the two states of C4, if enabled, or always,
if C4 is disabled, RSH transfers the LOW
active signal at input Ai to RSO. If Ai is not
used it must be connected to HIGH. The
feedback output signals of RS1, RS2 and
RS3 are externally available as active LOW
signals at outputs OFB1, OFB2 and OFB3.
Output OFB 1 is intended for the prescaler at
the highest frequency (if present), OFB2 for

•

Signetics Linear Products

Product Specification

HEF4751V

Universal Divider

the next (if present) and OFB3 for the lowest
frequency prescaler (if present). A prescaler
needs a feedback signal, which is timed on
one of its own division cycles in a basic timing
period. The timing signal at 05Y is LOW
during the last UD input period of a basic
timing period and is suitable for timing of the
feedback for the last external prescaler. The
synchronization signal for a preceding prescaler is the OR-function of the sync. input and
sync. output of the following prescaler (all
sync. signals active LOW).

CASCADING OF UDs (see
Figure 6)
A UD is programmed into the' slave' mode by
the program input data: n2A = 11, n28 = 10,
n3A = n4A = n38 = n48 = n58 = O. A UD operating in the slave mode performs the function

of two extra programmable stages C2' and
C3' to a 'master' (not slave) mode operating
UD. More slave UDs may be used, every
slave adding two lower significant digits to the
system.
Output OFB3 is converted to the borrow
output of the program data subtractor, which
is valid after fetch period 5. Input 51 is the
borrow input (both in master and in slave
mode), which has to be valid in fetch period O.
Input 51 has to be connected to output OFB 3
of a following slave, if not present to LOW.
For proper transfer of the borrow from a lower
to a higher significant UD subtractor, the UDs
have to be programmed sequentially in order
of significance or synchronously if the program is repeated at least the number of UDs
in the system.
Rate input Ri and output OF5 must be
connected to rate output OFB 1 and the input

IN of the next slave UD. The combination
thus formed retains the full programmability
and features of one UD.

OUTPUT (see Figure 5)
The normal output of the UD is the slow
output OF5, which consists of evenly spaced
LOW pulses.
This output is intended for accurate phase
comparison. If a better frequency acquisition
time is required, the fast output OFF can be
used. The output frequency on OFF is a
factor M • H higher than the frequency on
OF5. However, phase jitter of maximum ± 1
system input period occurs at OFF, since the
division ratio of the counters preceding OFF
are varied by slow feedback pulse trains from
rate selectors following OFF.

co•

.. 5/6

OUT'

l----f=...--I

UNIVERSAL DIVIDER

Figure 3. Block Diagram Showing Feedback to Prescalers

November 14, 1986

4-190

Signetics Linear Products

Product Specification

Universal Divider

HEF4751V

BASlCnUING PERIOD

BASIC TIMING PERKlD

BASIC nUING PERtOO

(n-1)

(n)

(n+1)

IN'

•
----------------------------------+~--------------------------------~~1_--+~---

NOTE:

1. Scaling factor.

Figure 4. Timing Diagram Showing Signals Occurring In Figure 3

OFS

OFF

---1
1---------------------- (M'H) PULSES --------------------1
Figure 5. Timing Diagram Showing Output Pulses

November 14, 1986

4-191

L

i

I

Signetics Linear Products

Product Specification

Universal Divider

,--

HEF4751V

PC

PE

PC'

PE'

I
I

51'

IN

OFS'

OSY

'----------(> OFF'

OF~¢---+_~--_+~----_i

OF&, Q---......- - - -.....------t

L---------------------------L ----------------- J
MASTER UNIVERSAL DIVIDER

SLAVE UNIVERSAL DIVIDER

(n2A<9; "2B<9)

(n2A -11j "2B"'1O)

8D07590S

Figure 6. Block Diagram Showing Cascading of UDs

November 14, 1986

4-192

Signetics

SAA1057
Pll Radio Tuning Circuit
Product Specification

Linear Products

DESCRIPTION
The SAA 1057 performs the entire PLL
synthesizer function (from frequency inputs to tuning voltage output) for all
types of radios with the AM and FM
frequency ranges.
The circuit comprises the following:
• Separate input amplifiers for the
AM and FM VeO-signals.
• A divider-by-10 for the FM channel.
• A multiplexer which selects the AM
or FM input.
• A 15-bit-programmable divider for
selecting the required frequency.
• A sample-and-hold phase detector
for the in-lock condition, to achieve
the high spectral purity of the veo
signal.
• A digital memory frequency/phase
detector, which operates at a 32
times higher frequency than the
sample-and-hold phase detector, so
fast tuning can be achieved.
• An in-lock counter detects when
the system is in-lock. The digital
phase detector is switched-off
automatically when an in-lock
condition is detected.
• A reference frequency oscillator
followed by a reference divider. The
frequency is generated by a 4MHz
quartz crystal. The reference
frequency can be chosen either
32kHz or 40kHz for the digital
phase detector (that means 1kHz
and 1.25kHz for the sample-andhold phase detector), which results
in tuning steps of 1kHz and
1.25kHz for AM, and 10kHz and
12.5kHz for FM.
• A programmable current amplifier
(charge pump), which controls the
output current of both the digital
and the sample/hold phase
detector in a range of 40dB. It also
allows the loop gain of the tuning
system to be adjusted by the
microcomputer.
• A tuning voltage amplifier, which
can deliver a tuning voltage of up
to 30V.
November 14, 1986

• BUS: this circuitry consists of a
format control part, a 16-bit shift
register and two 15-bit latches.
Latch A contains the to be tuned
frequency information in a binary
code. This binary-coded number,
multiplied by the tuning spacing, is
equal to the synthesized frequency.
The programmable divider (without
the fixed divide-by-10 prescaler for
FM) can be programmed in a
range between 512 and 32,767.
Latch B contains the control
information.

FEATURES

PIN CONFIGURATION
N Package

II
TOP VIEW

• On-chip prescaler with up to
120MHz input frequency
• On-chip AM and FM input
amplifiers with high sensitivity
(30mV and 10mV, respectively)
• Low current drain (typically 16mA
for AM and 20mA for FM) over a
wide supply voltage range (3.6V
to 12V)
• On-chip amplifier for loop filter
for both AM and FM (up to 30V
tuning voltage)
• On-Chip programmable current
amplifier (charge pump) to adjust
the loop gain
• Only one reference frequency for
both AM and FM
• High signal purity due to a
sample and hold phase detector
for the in-lock condition
• High tuning speed due to a
powerful digital memory phase
detector during the out-lock
condition
• Tuning steps for AM are: 1kHz
or 1.25kHz for a VCO frequency
range of 512kHz to 32MHz
• Tuning steps for FM are: 10kHz
or 12.5kHz for a VCO frequency
range 70MHz to 120MHz
• Serial 3-line bus Interface to a
microcomputer

APPLICATIONS
• Hi-Fi radios
• Auto radios
• Communication receivers

• Testlfeatures

4-193

853·0956 86556

Signetics Linear Products

Product Specification

SAA1057

PLL Radio Tuning Circuit

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

1B-Pin Plastic DIP (SOT-102HE)

-25·C to + BO·C

BLOCK DIAGRAM
TR

IN

TCA TCB

FFM

DCA

OUT

FAM

VCC1~~------------~~

T-______,..._____

VOC2 ().!l
16

CURRENT
STABILIZER

DCS

r----f''·O TEST
OLEN

13

CLB

14

DATA

12

BUS/LOAD
&
CONTROL
LOGIC

November 14, 19B6

SAA1057

4-194

Product Specification

Signetics Linear Products

SAA1057

PLL Radio Tuning Circuit

ABSOLUTE MAXIMUM RATINGS
RATING

UNIT

VCC1; VCC2

SYMBOL

Supply voltage; logic and analog part

PARAMETER

-0.3 to 13.2

V

VCC3

Supply voltage; output amplifier

VCC2 to +32

V

PTOT

Total power dissipation

800

mW

TA

Operating ambient temperature range

-30 to +85

°C

TSTG

Storage temperature range

-65 to + 150

°C

DC AND AC CHARACTERISTICS

VEE ~ OV; VCC1 ~ VCC2 ~ 5V; VCC3 ~ 30V; TA ~ 25°C, unless otherwise specified.

LIMITS
PARAMETER

SYMBOL

VCC1
VCC2
VCC3
ITOT

TEST CONDITIONS

Supply voltages

UNIT
Min

Typ

Max

3.6
3.6
VCC2

5
5

12
12
31

Supply currents 1
AM mode

V
V
V

16

mA

20

mA

ITOT ~ ICC1 + ICC2 in-lock:
BRM ~ '1';
FM mode

ITOT

PDM

~

'0' lOUT

~

0
0.3

ICC3

0.8

1.2

mA

RF inputs (FAM, FFM)
fFAM

AM input frequency

512kHz

32

MHz

fFFM

FM input frequency

70

120

MHz

VI(RMS)

Input voltage at FAM

30

500

mV

VI(RMS)

Input voltage at FFM

10

500

mV

RI

Input resistance at FAM

2

RI

Input resistance at FFM

135

n

CI

Input capacitance at FAM

3.5

pF

CI

Input capacitance at FFM

3

pF

VSIVNS

Voltage ratio allowed between selected and
non-selected input

-30

dB

kn

Crystal oscillator (XTAL)2
fXTAL

Maximum input frequency

Rs

Crystal series resistance

4

MHz
150

n

BUS inputs (OLEN, CLB, DATA)
VIL

Input voltage LOW

0
2.4

0.8

V

VCC1

V

VIH

Input voltage HIGH

-IlL

Input current LOW

VIL

~

0.8V

10

J1A

IIH

Input current HIGH

VIH

~

2.4V

10

IlA

November 14, 1986

4-195

Signetics Linear Products

Product Specification

SAA1057

PLL Radio Tuning Circuit

DC AND AC CHARACTERISTICS (Continued)

VEE = OV; VCC1 = VCC2 = 5V; VCC3 = 30V; T A = 25°C, unless otherwise
specified.
LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

UNIT
Min

Typ

Max

BUS Inputs timlng 3 (OLEN, CLB, DATA)
teLBlead

Lead time for CLB to DLEN

tTlead

Lead time for DATA to the first CLB pulse

1

j.lS

0.5

j.lS

teLBlag1

Setup time for DLEN to CLB

5

j.lS

teLBH

CLB pulse width HIGH

5

j.lS

teLBL

CLB pulse width LOW

5

j.lS

tOATAlead

Setup time for DATA to CLB

2

IlS

tOATAhold

Hold time for DATA to CLB

0

j.lS

tOLENhoid

Hold time for DLEN to CLB

2

j.lS

tCLBlag2

Setup time for DLEN to, CLB load pulse

2

j.ls

tOIST

Busy time from load pulse to next start of
transmission

5

j.lS

tOlsT
tOIST

Busy time
Asynchronous mode
Synchronous mode6

0.3
1.3

ms
ms

After word 'B' to other
device

Sample-and-hold clrcult4, 5 (TR, TCA, TCB)
VTCA, VTCB

Minimum output voltage

VTCA, VTCB

Maximum output voltage

CTCA
CTCA

Capacitance at TCA
(external)

tOIS
tOIS

Discharge time at TCA

1.3

V
VCC2- 0.7

V

REFH='1'
REFH ='0'

2.2
2.7

nF
nF

REFH = '1'
REFH = '0'

5
6.25

j.lS
j.lS

n

RTR

Resistance at TR (external)

VTR

Voltage at TR during discharge

100

CTCB

Capacitance at TCB (external)

10

nF

IBIAS

Bias current into TCA, TCB in-lock

10

nA

0.7

V

Programmable current amplifier (PCA)
±IOIG

Output current of the digital phase detector

0.4

mA

0.023
0.07
0.23
0.7
2.3

dB
dB
dB
dB
dB

1.0

MAN

Current gain of PCA
VCC2:;" 5V (only for P1)

P1
P2
P3
P4
P5

Gp1
Gp2
Gp3
Gp4
Gp5

CP3

CP2

CP1

CPO

0
0
0
0
1

0
0
0
1
1

0
0
1
1
1

0
1
0
0
0

STCB

Ratio between the output current of StH into
PCA and the voltage on CTCB

Ll.VTCB

Offset voltage on TCB
12 in-lock

November 14, 1986

1

4-196

V

Product Specification

Signetics Linear Products

SAA1057

PLL Radio Tuning Circuit

DC AND AC CHARACTERISTICS (Continued)

VEE = OV; VCCl
specified.

= VC C2 = SV;

VCC3

= 30V;

TA

= 2SoC,

unless otherwise

LIMITS
SYMBOL

PARAMETER

TEST CONDITIONS

UNIT
Min

Typ

Max

Output amplifier (IN, OUT)
VIN

Input voltage
in-lock; equal to internal reference voltage

1.3

V

Output voltages

minimum

VOUT
VOUT
VOUT
±IOUT

O.S

-lOUT = 1mA
maximum
lOUT = 1mA
maximum
louT = 0.1mA
Maximum output current, VOUT

= 1'2

VCC3

V

VCC3- 2

V

VCC3- 1

V

S

rnA

Test output (TEST)7

!

VTL

Output voltage LOW

O.S

VTH

Output voltage HIGH

12

V

ITOFF

Output current OFF, VTH

10

pA

ITON

Output current ON, VTL

1S0

V

IlA

Ripple rejection (see Figure 4)
At fRIPPLE = 100Hz
t.vCCl / t;.VOUT
flVCC2/ flVOUT
flVCC3/ flVOUT
VOUT 17) must be the same as the busy-time for a
next transmission to the SAA1057. When the other device has a separate DLEN or has less clock pulses than the SAA1057 it is not necessary to
keep to this busy-time; 5J.1s will be sufficient.
7. Open-collector output.

November 14, 1986

II

4-197

Product Specification

Signetics Linear Products

SAA1057

Pll Radio Tuning Circuit

OPERATION DESCRIPTION
Control Information
The following functions can be controlled with
the data word bits in latch B. For data word
format and bit position see Figure 2.
FM
FM/AM selection; '1' = FM, '0' = AM
REFH
Reference frequency selection; '1' = 1.25kHz, '0'
CP3 }
CP2
CP1
CPO

= 1kHz

(sample-and-hold phase detector)

Control bits for the programmable current amplifier
(see section Characteristics)

SB2

enables last 8 bits (SLA to TO) of data word B; '1'
word B will be set to '0' automatically

SLA

Load mode of latch A; '1'

PDMI
PDMO

Phase detector mode
PDU1 PDMO

'0'

= asynchronous

DIGITAL PHASE DETECTOR

Automatic onloff
on
off

X
0
1

0
1
1

= synchronous,

= enables, '0' = disables; when programmed '0', the last 8 bits of data

BRM

Bus receiver mode bit; in this mode the supply current of the BUS receiver will be switched-off automatically after a data
transmission (current-draw is reduced); '1' = current switched; '0' = current always on

T3

Test bit; must be programmed always '0'

T2

Test bit; selects the reference frequency (32 or 40kHz) to the TEST pin

T1

Test bit; must be programmed always '0'

TO

Test bit; selects the output of the programmable counter to the TEST pin
T3

T2

T1

TO

0

0

0

0

0

1

0

0

Reference frequency

0

0

0

1

Output programmable counter

0

1

0

1

Output in-lock counter
'0' = out-lock
'1' = in-lock

November 14, 1986

TEST (PIN 18)

1

4·198

Product Specification

Signetics Linear Products

PLL Radio Tuning Circuit

SAA1057

For the complete initialization (defining all
control bits) a transmission of word B should
follow. This means that the IC is ready to
accept word A.

achieved when bit 'SLA' of word B is set to
'1'. This mode should be used for small
frequency steps where low tuning noise is
important (e.g., search and manual tuning).
This mode should not be used for frequency
changes of more than 31 tuning steps. In this
case asynchronous loading is necessary.
This is achieved by setting bit 'SLA' to '0'.
The in-lock condition will then be reached
more quickly, because the frequency information is loaded immediately into the divider.

Synchronous/Asynchronous
Operation

Restrictions to the Use of the
Programmable Current Amplifier

APPLICATION INFORMATION
Initialize Procedure
Either a train of at least 10 clock pulses
should be applied to the clock input (CLB) or
word B should be transmitted, to achieve
proper initialization of the device.

Synchronous loading of the frequency word
into the programmable counter can be

voltage VCC2 is below 5V (CP3, CP2, CP1 and
CPO are all set to '0'). This is to avoid
possible instability of the loop due to a too
small range of the sample and hold phase
detector in this condition.

Transient Times of the Bus
Signals
When the SAA1057 is operating in a system
with continuous activity on the bus lines, the
transient times at the bus inputs should not
be less than 100ns. Otherwise the signal-tonoise ratio of the tuning voltage is reduced.

The lowest current gain (0.023) must not be
used in the in-lock condition when the supply

II
i,

~

BIT NO.

15

NOTE:
1. During the zero setup time (tLzsu) CLB can be LOW or HIGH, but no transient of the signal is permitted. This can be
of use when an 12C bus is used for other devices on the same data and clock lines.

Figure 1. BUS Format

DATA WORD A.

Figure 2. Bit Organization of Data Words A and B

November 14, 1986

4-199

,.

"

Product Specification

Signetics Linear Products

SAA1057

PLL Radio Tuning Circuit

+5V

10nF 22k

oVJ1f o--j
4 MHz

!

17

XTAL

-L..5
CXTAL-rPF

*"

Figure 3. Circuit Configuration Showing
External 4MHz Clock

I
DCA

J...100 nF<')

T

IN

TEST

18

17

22nF

AM OSCILLATORo---j

~

330 nF<1)

SAA1057

11 FAM

XTAL

(Z,' 2 kfl)

1

DLEN

4MHz

UpF

DH~

,3

~

BUS
NOTE:

Values depend on the tuner diode characteristics.

Figure 4. Application Example of the SAA 1057 PLL Frequency Synthesizer Module

November 14, 1986

4-200

Signetics

AN196
Single-Chip Synthesizer for
Radio Tuning
Application Note

Linear Products

Authors: J. Matull and J. Van Straaten
To remain competitive, manufacturers of domestic radios must not only produce a comprehensive range of reliable equipment with
the required performance at the right price,
but must also meet the needs of the market
with regard to styling, ease of operation and
available functions. Although the widespread
use of integrated circuits has allowed vast
improvements of performance and reliability
and has increased the range of available
facilities, the integrated circuits are not always optimally matched, resulting in partial
redundancy and a large number of peripheral
components. We foresaw this problem and
were able to avoid it by using a total systems
approach to manufacture our comprehensive
range of ideally-matched integrated circuits
for signal processing and digital control of
tuning, displays and analog functions in all
classes of radio. We can now, therefore,
devote our design resources and considerable knowledge of integration technologies
and techniques to reducing radio manufacturers' development and assembly costs by
minimizing the number of integrated circuits
needed to implement the wide range of
features and facilities required in today's
radios.
If a radio must incorporate facilities such as
search tuning and/ or tuning by direct entry of

February 1987

frequency at a keyboard, variable-capacitance diode tuning must be used and a stable
local oscillator signal can be generated by
indirect frequency synthesis with a phaselocked loop (PLL) controlled by a microcomputer. We have now used bipolar technology
to combine analog circuits with several types
of logic (12L, ECL and miniwatt) so that all the
functions previously performed by three integrated circuits can be performed by a single
18-pin LSI integrated circuit called synthesizer module SAA1057. The component economy afforded by the SAA1057 is amply illustrated by Figure 1 which shows that tuning
synthesizer functions which previously required the use of three integrated circuits and
a large number of peripheral components can
now be performed by the SAA 1057 and only
16 peripheral components.
The SAA 1057 is not only economical with
regard to the required number of components. It also consumes very little current
( < 20mA) and is able to meet the varied
performance requirements of all classes of
radio from battery-powered portables to
mains-powered hi-fi tuners. For example, a
novel twin-phase detector system in the PLL
achieves the fast tuning oiten required for car
radios and also ensures that, when the PLL is
locked, the VCO signal has high spectral

4-201

purity to ensure low distortion in hi-fi tuners.
The wide frequency range (AM 512kHz to
32M Hz, FM 70MHz to 120MHz) and high
maximum tuning voltage (30V) make the
SAA1057 suitable for multi-waveband mains
sets. The low current consumption combined
with the wide supply voltage range (3.6V to
12V) due to internal stabilization allow it to be
used in battery-powered portables.
In addition to the basic function of tuning by
direct entry of frequency, the SAA 1057 can
also provide the following software-controlled
facilities:
• Search tuning with muted interstation
noise
• Continuous up/down step tuning
(manual tuning)
• Accurate storage and automatic tuning
to preset frequencies
• Loading of frequency data in
synchronism with the sampling
frequency to prevent disturbance of the
tuning lock
• Feed out of a number of internal
signals for alignment purposes
• Adjustment of PLL current gain over
40dB range (0.023 to 2.3) to eliminate
switching of external loop filter
components during waveband selection.

Signetics Linear Products

Application Note

Single-Chip Synthesizer for Radio Tuning

~
~

AN196

15
14·

13
12
11

10

l
9V

a. Three Integrated Circuits and 36 Peripheral Components

SAA1057

18

3,6V to 12V

b. Synthesizer Module SAA1057 and 16 Peripheral Components
Figure 1. Basic Radio Tuning Synthesizers

February 1987

4-202

TEST

Signetics Linear Products

Application Note

Single-Chip Synthesizer for Radio Tuning

AN196

simply and economically accommodated are
analog signal control, extra display functions,
and remote control via an infrared data link.

OPERATING PRINCIPLES OF
FREQUENCY SYNTHESIS

Figure 2. Integrated Circuits for Tuning Systems Using SAA 1057

BIPOLAR CIRCUITS

A basic digitally-controlled PLL for radio tuning is shown in Figure 3. The output from the
voltage-controlled local oscillator in the radio
is converted into a pulse train, and frequency
divided by a programmable divider, before
being applied to one of the inputs of the
phase detector. The output from the crystalcontrolled reference oscillator is converted
into a pulse train, and frequency divided by
one of two ratios, before being applied to the
other input of the phase detector. The phase
detector output, which is proportional to the
relative phase (and therefore the frequency)
of the two input signals, is passed through the
low-pass loop filter to remove the high-frequency components and fed back to the VCO
as the tuning control voltage. The loop is
locked, and the radio correctly tuned, when
fose = NfREF where N is the programmable
division ratio determined by selecting the
frequency of the required broadcast.

Remote control
TDB2033

Gain·controlled remote IR receiver amplifier

Frequency synthesizer
SAA1057

Radio tuning PLL frequency synthesizer

Local Oscillator Inputs

Display drivers
SAA1060

32·segment LED

SAA1062/T

20 static outputs for LCD

SAA1063

32·segment FTD

Tuner switching
SAA1300

5·line switching circuit

As the word 'module' in the name of the
SAA1057 indicates, this new IC is part of a
modular, data bus·compatible, digitally·con·
trolled tuning system in accordance with the
system's design philosophy followed for other
circuits in our range of ICs for digital systems
in radios. The modular approach minimizes
radiation and reduces wiring and screening
costs because:
• all the sensitive signal processing
circuits for the tuning systems are now
in the SAA 1057 which can be mounted
in the ideal position close to the tuner
• internal HF dividers eliminate the need
for an external prescaler
• two sensitive, internally-switched VCO
inputs to the SAA1057 allow direct
connection of the FM and AM local
oscillator signals without additional
impedance matching, amplification or
switching
February 1987

BRIEF DESCRIPTION OF THE
FUNCTIONS OF THE SAA 1057
(Figure 4)

• the crystal-controlled reference oscillator
for the PLL operates at the same
frequency for the AM and FM
waveband and causes little radiation
because it generates a low level
sinewave
• the separate microcomputer and
memory can be mounted close to the
keyboard and their capacity can be
tailored to meet the demands of
specific radios
• the frequency display driver can be
mounted close to its display.
As shown in Figure 2, the data bus compatibility of tuning systems using the SAA 1057
also allows the simple addition of circuits as
required for waveband switching and for driving LED, LCD or fluorescent displays of
preset station number, waveband and channel number. Other facilities which can be

4-203

The local oscillator signals from the radio are
applied to inputs FFM for FM and FAM for
AM. Since these inputs have a sensitivity of
30mV to 500mV (AM) and 10mV to 500mV
(FM), the local oscillator signals can be directly applied without preamplification or buffering. A separate pin (DCA) allows the bias
circuitry of the internal input amplifiers to be
decoupled by an external capacitor. The input
frequency range is 512kHz to 32MHz for AM
and 70MHz to 120MHz for FM, the FM
signals being passed through an internal
divide-by-ten HF prescaler which is switched
off by software to minimize current consumption while tuning the AM band. Since the AM
and FM local oscillator signals are automatically selected by software, they need not be
externally switched during waveband selection.

Programmable Divider
This 15-bit frequency divider, which is designed in a special manner to minimize current consumption, is programmed with a binary-coded divisor (N) to synthesize the required frequency for the voltage-controlled
local oscillator in the radio. The local oscillator frequency (foscl is usually the IF above
the tuned frequency. The dividing number is
(32foscl/fREF for AM and (3.2foscl/fREF for

II,
~

!

i;

I

Signetlcs Linear Products

Application Note

Single-Chip Synthesizer for Radio Tuning

divided local oscillator signal is applied as
one of the inputs to a dual-phase detector
system.

MOS CIRCUITS
Display drivers
PCE2100
PCE2110
PCE2111

40-segment LCD
)
60-segment LCD + 2 LEDs
64-segment LCD

PCE2112

32-segment LCD static

in duplex mode

SAA1061

16 static outputs for LED drive and switching functions

SAB3044

2-digit LED

Single-chip a-bit microcomputers
MAB8021

With 1k byte ROM and 28-pin package

MAB8048

With 1k byte ROM and 40-pin package

MAB84XX

NMOS family with 1 to 4k byte ROM and 12C bus

MAB85XX

CMOS family with 0.5 to 4k byte ROM and 12C bus

Memories
PCD8571

128 X 8-bit CMOS memory with serial 1/0

PCB1400

100 X 16-bit EEPROM with serial I/O

Infrared remote-control receivers
SAB3023

Receiver and analog memory

SAB3033

Receiver and analog memory

SAB3042

Receiver and decoder with C-bus

SAB3028

Receiver and decoder with 12C bus

7 X 64 commands

SAB3021

2 X 64 commands

SAB3027

32 X 64 commands

~

I

-;;:;,;- -- -- -iVOL TAGE
CONTRDLLED
LOCAL
OSCllLA TORS

rl------I
PHASE

DETECTOR

hlTWUp

tune clown
Vto..nt!

locked

FAEQUENCY
SYNTHESIZER

Figure 3. A Basic Digitally-Controlled PLL for Radio Tuning
FM, where fREF is the output frequency from
the reference frequency divider (40kHz or
February 1987

Reference Frequency Oscillator
This stable, temperature-compensated oscillator is controlled by an inexpensive 4MHz
crystal (series resistance < 150n) connected in series with a capacitor between Pin 17
of the SAA 1057 and the common return line.
The reference frequency may alternatively be
derived from a stable external source. In this
case, a 4MHz squarewave of 5Vp_p may be
connected to Pin 17 via a series-connected
10nF capacitor and 22kn resistors.

Reference Frequency Divider
This circuit divides the frequency of the signal
from the reference oscillator by 125 or 100 to
obtain a reference frequency of 32kHz or
40kHz for the dual-phase detector system
under the control of software. If the selected
reference frequency is 32kHz, the minimum
tuning step is 1kHz on AM and, due to the
divide-by-ten HF divider, 10kHz on FM. If the
selected reference frequency is 40kHz, the
minimum tuning steps for AM and FM are
1.25kHz and 12.5kHz, respectively. If larger
tuning steps are required, integer multiples of
these tuning steps can be selected by software.

Phase Detector System

Infrared remote-control transmitters
SAB3004

AN196

32kHz). The minimum divisor is 512 and the
maximum divisor is 32,767. The frequency-

4-204

To simplify the design of the PLL loop filter,
the SAA 1057 incorporates a novel dualphase detector system that uses the same
reference frequency for AM and FM. One of
the phase detectors is a high-speed digital
memory (flip-flop) type, the other is a high
gain and analog memory (sample and hold)
type. The digital phase detector operates at
the reference frequency, generates about
100 times as much tuning current as the
analog phase detector and provides highspeed tuning over a wide frequency range.
The analog phase detector operates at Y32 of
the reference frequency. has no region of
uncertainty in its transfer characteristic and
provides increased spectral purity of the local
oscillator signal when the PLL is locked. The
'hold' voltage from the analog phase detector
is converted into a DC current and summed
with the output pulses from the digital phase
detector to provide a current proportional to
tuning error. This current drives a gain-programmable amplifier to generate the tuning
voltage output.
The analog phase detector is always operating, but the digital phase detector can be
switched on/off by setting/resetting the inlock detector with featuresltest bits in the
software (e.g., to minimize noise during step
tuning). If the software does not include any
featuresltest bits, the digital phase detector
is automatically switched on if the tuning error
exceeds the phase range of the analog phase

Application Note

Signetics Linear Products

Single-Chip Synthesizer for Radio Tuning

TA

AN196

TCA TCB

GAIN
PAOGRAM-

MABLE
CURRENT
AMPLIFIER

LOOP
AMPL

"

5

Figure 4. Block Diagram of the SAA 1057

detector. This could occur, for example, as
the result of executing a large frequency
change. When the in· lock detector deter·
mines that the tuning error has been reduced
to within the operating range of the analog
phase detector for three consecutive sam·
piing periods, the digital phase detector is
automatically switched off again.

Gain-Programmable Current
Amplifier
The sum of the output currents from the two
phase detectors drives a gain'programmable
bidirectional current source which replaces
the normally· used resistor between the
charge pump and loop amplifier of a PlL. This
allows the loop gain of the Pll to be software
programmed over a 40dB range within the
limits 0.023 to 2.3, thereby eliminating the
need to switch loop filter components during
waveband selection.

Loop Amplifier
The loop amplifier is capable of providing a
tuning voltage output of up to 30V and only
requires a series·connected RC network be·
tween its input and output to form an active
low·pass loop filter. The supply voltage for
the loop amplifier (VCC3) need not be stabi·
lized but it should be adequately filtered.
February 1987

Reception of Frequency and
Control Data
Data for the SAA 1057 consists of serially·
transmitted 17 ·bit frequency setting and con·
trol words from a microcomputer. Both types
of word incorporate a zero start bit which is
tested to identify a correct transmission. Each
word also contains a latch selection bit which
is 0 for a frequency setting word and 1 for a
control word. The incoming data is transmit·
ted via an asychronous data highway with
separate data (DATA), clock (ClB) and en·
able (DlEN) lines. The logic levels on the
lines are TTl·compatible and are indepen·
dent of supply voltage.

A control word includes fifteen bits for the
following purposes:
• one bit (FM) to control the switch to
select the required input from the AM
or FM local oscillator. If the AM input is
selected, the divide·by·ten prescaler is
switched off to conserve power
• one bit (REF H) to program the divisor
for the reference frequency divider
• four bits (CPO to CP3) to set the gain
of the gain'programmable current
amplifier

Sixteen bits of each incoming data word are
loaded into a shift register. The bus, load and
control logic then checks that the transmis·
sian is valid by checking that the first bit is
zero and that the word length is correct
during the HIGH period of the DlEN line. If
valid, the data word is then transferred to the
appropriate latch by the next pulse on the
clock line.

• one bit (SB2) to determine whether the
remaining eight features/test bits should
be used or not
• one feature bit (SlA) which determines
whether frequency setting data is
loaded into the programmable divider
immediately after reception
(asynchronous loading) or synchronized
with the sampling frequency
(synchronous loading). Synchronous
loading is for minimizing noise during
manual tuning without muting

A frequency·setting word includes fifteen bits
which define the required frequency ex·
pressed as a 15·bit binary·coded divisor (512
to 32767) for the programmable divider.

• two features bits (PDMO and PDM1)
which set the operating mode of the
digital phase detector as previously
described

4-205

Application Note

Signetics Linear Products

Single-Chip Synthesizer for Radio Tuning

30V_v~e~e~3r-

AN196

__________________________________________________________________________--,
C1
R1

rH

C2

leA le!::!

SAA 1057

(,AIN
PROC;HAM-

MAtHE

CUflRf:NT
AMf'llf"l[fl

(;4

1?_C5

13 DLEN

CBO~S

14 CLB

12CBUS 12 DATA

veo
4Vto28V

Figure 5. An AM/FM Frequency Synthesizer Using the SAA 1057

• one feature bit (BRM) which sets the
bus receiver into an automatic mode so
that it is switched off to conserve
power aiter a data transmission
• four test bits (TO to T3) which can
route the reference signal, the output
from the programmable divider or the
output level from the in-lock detector to
the TEST pin for alignment purposes.

mance, application flexibility and low power
consumption. A description of the techniques
listed here is beyond the scope of this article
but further information can be found in the
references:
• travelling-wave dividers in the divide·byten prescaler ensure low current
consumption and high sensitivity for the
RF inputs
• a tail-end divider is used to increase
the speed of the digital phase detector

TECHNIQUES USED TO OBTAIN
THE HIGH PERFORMANCE OF
THE SAA1057

• a rate-select technique in the
programmable divider minimizes phase
jump in the digital phase detector

Many new circuit techniques have been used
in the SAA 1057 to achieve the high perlor-

• current consumption is minimized by
using stacked logic for the three

February 1987

4-206

different types of digital circuits (1 2l,
Eel and miniwaU). In this way, many of
the logic circuits act as current sources
for other logic circuits
• use of a bandgap current reference
ensures that the current consumption
remains constant over a wide range of
supply voltage and operating
temperature
• the op amps at the RF inputs have an
input bias current of less than lanA
and also have a very high slew rate
• the tuning voltage is derived from a
30V op amp with a low bias current
and a high slew rate.

Application Note

Signetics Linear Products

Single-Chip Synthesizer for Radio Tuning

AN196

BASIC APPLICATION OF THE
SAA1057

ACKNOWLEDGEMENT
The authors wish to thank H. Pruim of the IC
development department, Nijmegen, J. L.
Baurdoux of the car radio development department, Eindhoven, and U. Schillhof of the
application laboratory, Hamburg, for their
contributions to this project.

Figure 5 is the circuit diagram of a complete
frequency synthesizer using the SAA 1057.
The functions and values for each component in the diagram are as follows:
REF

FUNCTION

VALUE

Rl

Defines the current in the analog phase detector

180n

REFERENCES

R2

Loop filter resistor (value depends on Vee)

18kn

1.

R3

Low-pass filter resistor (value depends on Vee)

R4

Matching resistor for 75n FM input

180n

Cl
C2

Sample capacitor (low leakage type)

2.2nF typ

C3
C4

Decoupling of internal reference voltage
Loop filter capacitor (value depends on Veo)

330nF typ

Cs

Low-pass filter capacitor, normally located in the tuner
(value depends on loop frequency)
Power supply filtering

100nF typ
100nF

100n min
10kn typ

Cs
C7

Hold capacitor (low leakage type)

10nF typ
47j.lF

Power supply filtering

100j.lF

Decoupling of RF input stages

10nF

ClO

DC blocking

11nF

Cl l

Series capacitor for crystal
(value depends on crystal)

33pF

PERFORMANCE OF THE CIRCUIT FOR FM
87.5 (88) to 108 MHz

Tuning steps

10 kHz or 12.5 kHz

Intermediate frequency

10.7 MHz (variable in steps of 10 kHz
or 12.5 kHz)

Tuning voltage of the VCO

4 to 28 V

VCO gain

0.3 to 3 MHzlV

Ref. frequency

32 kHz

Prog. divider ratios

9820 (9870) to 11870

Time to tune across band

< 400

Gain of current amplifier

0.3

Loop filter time constant

1 ms

RMS ripple on tuning voltage noise
(20 Hz to 20 kHz)

5 j.lV

1 kHz

<1

February 1987

3.

1nF

DC blocking

Ce
Cg

Tuning range

2.

ms

j.lV (0.3 j.lV)

4-207

4.

5.

UNDERHILL, M. J. 'Phase lock frequency
synthesis for communications', symposium on phase-locked loops and their
applications, January 18th 1980, Department of Electrical Engineering, University
of Technology, Delft.
UNDERHILL, JORDAN, CLARK and
SCOTT, 'A general purpose LSI frequency synthesizer system' 32nd annual symposium on frequency control, 1978, Department of Electrical Engineering, University of Technology, Delft.
UNDERHILL, M. J. 'Universal frequency
synthesizer IC system' lEE communications '7B, 4th to 7th April 1978.
KASPERKOVITZ, W. D. 'Ultra high frequency divider', Philips Technical Review, Vol. 38, No.2, 1978/79, pp. 50 to
65.
KASPERKOVITZ, W. D. and VERBEEK,
R. 'Low power circuit block for digital
telephone exchanges', Microelectronics
and Reliability, Vol. 15, 1976, pp. 163 to
170.

•

i

Signetics

AN197
Analysis and Basic Application
of the SAA1057
Application Note

Linear Products

Author; J. Matull

INTRODUCTION
Early digital tuning systems for AM/FM radio
receivers were constructed from ICs out of
standard logic families (ECL, TIL etc.).
Later, first dedicated ICs for PLL frequency
synthesizers have appeared on the market,
but there were still several packages required
for the complete tuning system. The partitioning of functions depends on the semiconductor technologies used. The tuning part of a
digital tuning system typically requires three
packages; a prescaler in ECL or Schottky TTL
(speed), a programmable divider and other
digital functions in either LOCMOS, NMOS or
12L (packing density, current consumption)
and a loop amplifier with FET inputs (low bias
current) and a bipolar output stage (current,
slew rate).
Now, more sophisticated ICs for digital tuning
of radio receivers are showing. The SAA1057,
being described in this report, belongs to this
new generation of radio PLL frequency synthesizers. It comprises all of the functions of a
digital PLL frequency synthesizer and all active components from the inputs for the local
oscillators to the output for the varactor
tuning voltage on one monolithic chip, requiring only a minimum of external passive components.

SYSTEM DESCRIPTION
A functional block diagram of the SAA 1057 is
shown in Figure 1. This system is designed to
handle both AM and FM local oscillator frequencies in a microcomputer -controlled radio
receiver. Attention has been paid to the
power consumption of the IC in order to
permit its use in portable as well as in mains
operated radios.
An important property of the SAA 1057 is its
very low radiation. This is due to the compact
one-chip design which does not require an
external prescaler and its control line and due
to the crystal controlled reference oscillator
which operates with a low sine-wave voltage
swing.

RF Inputs
Separate inputs are provided for the AM and
FM local oscillators. Amplifiers at the inputs
offer high sensitivity for easy interfacing to the

February 1987

radio's VCOs. No external buffers are required. A built-in divide-by-10 prescaler for
FM permits a maximum input frequency of
120MHz while the AM input can directly
handle up to 32M Hz.
An input multiplexer permits both oscillators
to be operating at the same time, thus saving
cost for switching the oscillators in the radio.
On AM, the prescaler is switched off in order
to reduce the current drain of the chip.
There is one pin, DCA, for the decoupling
of the input amplifiers' bias circuitry.

Programmable Divider
This 15 bit divider is programmed with a
binary coded dividing number, N, in order to
synthesize a desired frequency fvco. In view
of the current consumption, this divider was
designed according to the rate select technique. This implies a minimum permissible
dividing number, Nmin, which is equal to 512
in the SAA 1057. The maximum dividing
number, Nmax , is given by the 15 bit length as
32767.

Phase Detectors
A novel phase detector concept is used in the
SAA1057, permitting the use of the same
reference frequency on AM and FM, thereby
facilitating the design of the loop filter.
Two phase and frequency sensitive detectors
are used in this concept, a high-speed digital
flip-flop type detector and a high-gain analog
sample and hold type detector. The digital
phase detector (PO) operates at the reference frequency and provides for high tuning
speed. The analog PO operates at 1/32 of
the reference frequency and provides for
improved spectral purity of the radio's VCO
after lock has been achieved. There is no
region of uncertainty in the analog PO's
transfer characteristic.

This oscillator is designed to operate with a
low-cost 4MHz crystal. Only one pin is required for this stable, temperature-compensated oscillator.

The analog PO is always operating. The
digital PO can be switched on/ off either under
software control (see also 2.9) or automatically. If no features/test bits are selected, the
digital PD is automatically switched on if the
operating range of the analog PO is exceeded, e.g. when a jump in frequency is
executed. It is automatically switched off
again if the operating range of the analog PO
has not been exceeded during three consecutive sampling periods. That is accomplished by the in-lock detector. This detector
can be set and reset under software control
to establish the different modes of PO operation.

In case of an externally available 4MHz signal
of sufficient stability, the pin XTAL can be
supplied with a resistor from that source.

The "hold" voltage of the analog PO is
converted to a DC current and summed with
the output pulses of the digital PD.

Reference Divider

Gain-Programmable Current
Amplifier

Two outputs of the programmable divider are
fed to the phase detectors. They differ in
frequency by a factor of 32.

Reference Oscillator

This divider generates the reference frequency for the digital phase detector from the
4MHz crystal frequency. This reference frequency is either 32kHz or 40kHz. It can be
changed under software control and outputted at the pin TEST in case that is desired,
e.g. for aligning the frequency of the reference oscillator.
With these two reference frequencies, the
minimum step size for changing the VCO's
frequency is 1kHz and 1.25kHz on AM. On io
FM, the step size is 10kHz and 12.5kHz due'"
to the divide-by-10 prescaler. Larger steps in
VCO frequency (integer multiples of the values given above) can be achieved under
software control.

4-208

The output current of the phase detector
configuration is passed through a gain-programmable amplifier. This is an equivalent for
the normally used series resistor from the
charge pump to the loop amplifier. The advantage of this solution is that the loop gain
can be programmed under software control
without any changes in hardware.

Loop Amplifier
The on-chip loop amplifier requires only a CR
series connection between its input and output pins to build a basic loop filter. Tuning
voltages of up to 30 volts can be generated.
The supply voltage for this amplifier, VCC3,
need not be stabilized; however, it should be
sufficiently filtered.

Signetics Linear Products

Application Note

Analysis and Basic Application of the SAA1057

AN197

TA TCA TCB

VCC2 DCS VI!:E

1----t- XTAl
DCA

'AM
'FM

Vceo

II

OUT

IN -lr---------l

t----t- TEST

OLEN CLCK DATA

Figure 1. Functional Block Diagram

Data Reception
The SAA 1057 requires both frequency and
control information from an external microcomputer. This information is received via an
asynchronous serial data link with separate
data (DATA), shift clock (CLCK) and enable
(OLEN) lines. This structure with the associated timing requirements used to be called
CBUS. The logic levels on these CBUS lines
are TIL compatible, independent of the supply voltage.

February 1987

Incoming data is received in a shift register. A
bus, load and control logic performs a format
check on received data and a decision on
whether the transmission was valid or not.
Only correctly received data are transferred
to one of the two latches. Frequency information is stored in latch A and control information in latch B.

Features/Test
In addition to the basic PLL operation of the
SAA 1057 there are a few features and test

4-209

functions which can be enabled by certain
bits in the control information.
Examples are synchronous loading of frequency data to prevent an out-of-Iock condition due to that transmission, disabling of the
digital phase detecta( to avoid tuning noise in
case of step tuning, and outputting of the
reference frequency, e.g., for the alignment of
the crystal oscillator frequency. Details are
described in the application section of this
report.

Signetics Linear Products

Application Note

Analysis and Basic Application of the SM1057

AN197

Table 1. Description of Components
R1
R2
R3
R4
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
Y1

e.g. R1 = 390
e.g. R2 = 18
min. R3 = 100
e.g. R4 = 180
typo C1 = 2.2
typo C2=10
typo C3=10
e.g. C4 = 330
e.g. C5 = 100
e.g. C6 = 100
typo C7 = 1
e.g. C8 = 100
typo C9=10
typo C10 = 22
e.g. C11 = 33

Defines current in S/H detector
Loop filter resistor, depends on VCO
Low·pass filter resistor
Matching resistor for FM input
Sample capacitor, low leakage type
Hold capacitor, low leakage type
Decoupling of internal reference voltage
Loop filter capacitor, depends on VCO
LOW-pass. filter capacitor, mostly located in tuner, depends on loop frequency
Power supply filter capacitor
DC blocking capacitor
Power supply filter capacitor
Decoupling of RF input stages
DC blocking capacitor
Series capacitor for crystal
Crystal for reference OSCillator, f = 4.000MHz

n
kn
n
n
nF
nF
nF
nF
nF
nF
nF
nF
nF
nF
pF

Al
TEST

18

Vl

Cll

DH~

8AA 1057

GND
CLCK
OLEN
DATA
Cl0
AMOS

C8

V~1n[)--------~=-+---------------------------~

Figure 2. Basic Application

Power Supply

TEST

VCC112

Cl.CK~~
DLEN~

GNO

DATA

o...'-~_"/

GNO

VTUN

'MOS
GNO

Besides the already mentioned supply voltage for the loop amplifier there are two pins
for the supply of the whole circuit: Vcc, and
VCC2. The supply voltage may be chosen in
the range from 3.6 to 12 volts without significant influence on the supply current due to
the internal stabilizer, which is decoupled at
pin DCS. The supply voltage should be well
filtered.

AMOS

APPLICATION
The circuit diagram for the basic application
of the SAA 1057 in an AM/FM radio receiver
is shown in Figure 2; a short description of the
components is given in Table 1.

SM 1057 RADIO PLL SYNTHESIZER

Figure 3. Bottom View of PC Board

February 1987

4-210

Signetics Linear Products

Application Note

Analysis and Basic Application of the SAA1057

As there are many ways in which radio
receivers can be different from each other,
e.g. number of wave bands, supply voltages,
tuning voltage range, VIF characteristic of
the VCO, the synthesizer circuitry has to be
designed for a specific application.

AN197

C4

>--....---<>

In this chapter information is given on all of
the components in the circuit diagram and on
the software requirements of the SAA 1OS7
for a number of receiver tuning procedures.
A typical lay-out of a printed circuit board for
the application of the SAA 1OS7 is given in
Figure 3. There are two connectors; one for
the supply voltages and the connection of the
radio receiver and one for the CBUS from the
microcomputer or a synthesizer controller,
like the SYCO II.

Let Zo
R4

= 7sn,

(1)

then

135 -7S

= - - - = 169n
135 -75

The closest standard resistor is R4
ohms.

= 180

The DC blocking capacitors, C7 and C10,
should be chosen so that their series reactance at the lowest VCO frequency is small
compared to the input impedance. Thus,
C7> > - - - - - 2 • 1f • fFM,min • RiFM

(2)

and
C10> > --,-----:=-2 -" -fAM,min - RiAM

t--r-

8~.)

The oscillator frequency lines are either realized on a PC board or as a screened cable,
depending on their length, among others. The
output at the AM VCO is not critical; it can be
an inductive or capacitive tap at the resonant
circuit, provided the output voltage is at least
30 millivolts rms into a load of 2 kn. The
minimum required FM oscillator voltage is 10
millivolts rms, the input resistance of the SAA
10S7 is 13Sn. In order to minimize the
voltage standing wave ratio, VSWR, a resistor, R4, is used to match the input reSistance,
RiFM' to that of the connecting cable, ZOo
Ignoring the capacitances, R4 can be calculated according to

80(s)

Figure 5. PLL Block Diagram

Interfacing of the Tuning
Voltage

fs = 1kHz or 1.2SkHz
DeSigning the Loop Filter

The output of the loop amplifier is connected
to the varicap tuning diodes via a CR lowpass filter, R3 and CS.

Due to the on-chip loop amplifier and gainprogrammable current amplifier, the loop filter
consists of only two external components, R2
and C4. The loop filter principle is shown in
Figure 4.

Although there is no lower limit of R3, a
minimum of about 1DOn should be used to
avoid capacitive loading of the loop amplifier
output. For CS, there is normally a lower limit
given by the deSign of the varactor tuned
resonant circuits in the radio.
The cut-off frequency of the low-pass filter,
f ,p , should be less than the sampling frequency, fs, of the phase detector in order to
attenuate potential ripple at this frequency.
On the other hand, the cut-off frequency
should be high compared to the loop's natural frequency, fn' to keep the decrease of the
phase margin as small as possible. fn de·
pends on the FIV characteristic of the VCO,
the dividing number, N, and the loop filter
design.

As outlined earlier, the commonly used series
resistor between charge pump and loop amplifier input is replaced by a gain-programmable current amplifier in the SAA10S7. Therefore, the loop filter transfer function evaluates
to
VOUT (s)

KF =
with T

i;;(s) =

1 + sT
sC4

(6)

= R2 - C4.

The basic block diagram of a PLL in terms of
gain is shown in Figure 5.
The output to input ratio reflects a second
order system:

Thus, the choice of the low-pass filter's cutoff frequency is a compromise between ripple
rejection at the sampling frequency and loss
of phase margin.

(7)

8i (s)

(4)

(3)

or

with KIP
1
1
->R3-C5>-wn
2" -fs

with Wn
February 1987

VOUT

Figure 4. Loop Filter Principle

Interfacing of the Tuner's
Oscillators

RiFM -Zo
R4=--RiFM - Zo

.,

=

2 -,,-f n

4-211

= gain of digital phase detec-

tor including current amplifier
(S)

KF

= gain of loop filter as given

Kv
N

=
=

in Equation (6)
gain of VCO
integer divisor

Signetics linear Products

Application Note

AN197

Analysis and Basic Application of the SAA1057

vs.

Table 2. Loop Filter Input Current

Gain Programming

CP3

CP2

CP1

CPO

Idlg

a
a
a
a

a
a
a

a
a

a

O.OlmA
0.03mA
O.lmA
0.3mA
1.OmA

a
a
a

1
1
1

1
1

1

1

with Idig = current programmed according to
Table 2
and
dfyCO
SyCO=-dV'une

(13)

being the slope of the VCO's FIV characteristic.
Since neither SyCO nor N remain constant
over a larger frequency band, wn and l""
should be calculated for several points in the
wave band considered, in order to find the
appropriate constants for best loop performance. See the Appendix for a design example.
The lock-up time not only depends on the
loop filter components but also on the current
gain setting. The longest time which can
occur is that for a jump from one end of a
wave band to the other. It consists of two
parts:
tband ~ tslew

+ tsettle

(14)

The output pulses of the digital phase detector can be assumed to have an average duty
cycle of 50 0/0 during most of the slew time.
Therefore, tslew can be approximated as
C4' .:lV,une
tslew '" 2' ----"'=
Idig

(15)

The settling time, tsettle, depends on wn and
can be estimated from
(16)

with wnt taken from Figure 6 for a certain
overshoot and wn as given by Equation (12).

-

wn'

Figure 6. Type 2. Second Order Step Response
Substituting KF yields

with wn
(8)

l"

K'P' Ky

Oo(s)

- - C - · (1 + sT)

0i(S)

S2

+ S'

K'I" Ky • R2

N

+

= loop bandwidth or natural
frequency
= damping factor

The gain of the phase detector, KiL, is the
output current of the p.o. times the gain of
the programmable current amplifier. In order
to simplify the calculation, we re-write Equation (10) as follows:

K'I" Ky

C4·N

clearly showing the Characteristic Equation of
a second order polynomial:
(9)

=

W

n

V

ldi9 • Svco
C4'N

By comparison of coefficients one obtains
W

n

=VK<{J'Ky
C4'N
R2'C4

l"=wn ' - -2February 1987

(10)
(11 )

4-212

(12)

The output phase response of a type 2
second order system (Figure 5) to a phase
step input is shown in Figure 6. The curves
can also be used for frequency inputs and
outputs. The required damping factor, l", for a
given overshoot can be taken from the plot.
Also, the natural frequency, w n, can be calculated if l" and the lock-up time, tsettle, are
known.

The Analog Phase Detector
In the analog PD a comparison of the relative
phase of two digital signals is performed. In
principle, a voltage ramp is started by the
crystal controlled reference frequency and
stopped by the high-speed output of the
programmable divider. As only every 32nd
output pulse is sampled, the phase jitter of
that rate-multiplier type divider is eliminated.
The ramp voltage is transferred to the hold
capacitor, C2. Any deviation from the ramp's
center voltage is converted to a current,
amplified in the gain-programmable current
amplifier, and fed into the loop amplifier.

Application Note

Signetics Linear Products

Analysis and Basic Application of the SAA1057

The voltage ramp is generated by first charging the capacitor. C1, with internal circuitry
and then discharging it with a constant current, which is defined by an external resistor,
R 1. Thus, the slope of the ramp, i.e. the gain
of the analog PD, can be changed by changing the component values of C1 and R 1.
There are two limitations. For R1, there exists
a minimum value of 100 ohms in order to limit
the discharge curren1 to a safe value and for
C2, there is a maximum value given for both
reference frequencies to permit complete
pre·charging of that capacitor.

1500
1200
1000
820

680

560

if

AN197

The maximum ramp amplitude depends on
the supply voltage, VCC2, and is typically

470

a: 390

(17)

330

The time required for a discharge of C1 from
VrcA max to VrCA min depends on the value of
C1 a'nd the discharge current, which is defined by R1. The maximum time is

270

220

C1 'Vramp
t ramp = - - - Idis

180
150

(18)

With
120

--

100

R1MIN

0

(19)

VCC2 (VOLTS)

Figure 7. Maximum R1 as a Function of VCC2

----_._-----'

and the maximum permitted time, idis, we can
calculate the maximum value of resistor R 1 to
be
(20)
VrR is the voltage at pin 1 of the SAA 1057
during the discharging of capacitor, C1. The
dependency of the upper limit of A1 on VCC2
is shown in Figure 7 for two different values of
C1.

17
10nF

22K
SM 1057

.

rnn
.'GJ

40MHz

The center voltage is typically
VCC2
Vr.o = -2- + 0.3V

5 VOLTS

PEAK-TO-PEAK

(21)

giving an operating range of the analog PD of

Vramp

VSH = Vr.o ± -2-

Figure 8. Connection of an External 4MHz Source

Table 3. Loop Filter Input Current Per Volt Change of the
Hold Capacitor Voltage
CP3

CP2

CP1

CPO

lanalog PER VOLT

0
0
0
0
1

0
0
0
1
1

0
0
1
1
1

0

O.03=mJ1A
O.l=mJ1A
0.3=mJ1A
1.0=m/lA
3.5=mJ1A

February 1987

1

0
0
0

4-213

(22)

As the maximum output current of the analog
PD depends on VCC2, only a "gain" constant
of 1.5J1A1V is specified. i.e. a deviation of 1
volt from the center voltage, Vr.o, produces an
output current of 1.5/lA. This current is amplified in the gain-programmable amplifier and
then fed into the loop amplifier. In Table 3
there are given some loop filter input current
values for different gain settings of the gain·
programmable amplifier.
To obtain the maximum currents obtainable
from the analog PO, the values in Table 3
have to be multiplied by 1/2' V ramp '

•

Signetics Linear Products

Application Note

AN197

Analysis and Basic Application of the SAA1057

OlEN

U

CLCK

DATA

TEST FOR START BIT

Figure 9. CBUS Timing

DATA

Figure 10. Data Word for Frequency

DATA

Figure 11. Data Word for Control Information

Generating the Reference
Frequency
The simplest way of completing the reference
frequency oscillator is to connect a 4MHz
quartz crystal from pin 17 (XTAL) to ground.
Any crystal with a series resistance of not
more than 150n will do. As crystal frequencies are normally specified for a certain
external capacitance, a series capacitor, Cll,
should be connected in series with the crystal, Yl. If the crystal spec is properly chosen,
a fixed capacitor will normally do. If we
assume a mis-alignment of 50ppm the resulting veo frequency of e.g. 100MHz would be
offset by 5kHz, i.e., half the step size. That is
normally unimportant. In special applications,
however, it might be necessary to tune the
crystal. There is room for a series trimmer
capacitor on the PC board.

February 1987

Table 4. Frequency Programming Range
INPUT

fREF = 1kHz
32

AM

fmin =
f max =

512kHz
32767kHz

640kHz
40958.75kHz

FM

fmin =
fmax=

5.12MHz
327.67MHz

6.40MHz
409.5875MHz

Another way of generating the reference
frequency is the use of an external 4M Hz
source of satisfaC10ry stability. In Figure 8 it is
shown how to conneC1 such an external
source.
Please note that the stray capacitance at pin
17 should not exceed 8pF.

Transmitting Data to the
SAA1057
All information is entered serially into the SAA
1057. The timing of the CBUS data transmission is shown in Figure 9.

4-214

fREF
32

= 1.25kHz

There are two checks performed on data
received in the SAA 1057:
- a test for the start bit
- a test for correct word length.
The start bit is tested during the high time of
the first clock pulse. It has to be '0' to indicate
the beginning of a proper transmission.

Application Note

Signetics Linear Products

Analysis and Basic Application of the SAA1057

Table 5 Phase Detector Mode
PDM1

PDMO

0
0
1
1

0
1
0
1

(FM = '0') or one tenth of the frequency at
the FM input (FM = '1 ') is switched to the
input of the programmable divider. In AM
mode (FM = '0') a part of the FM signal path
is switched off in order to reduce the current
drain of the chip.

DIGITAL PD

Automatic on/off
Automatic on/off
On
Off

Table 6. TEST Signals
T3

T2

T1

TO

0
0
0
0

0
1
0
1

0
0
0
0

0
0
1
1

OUTPUT AT TEST (PIN 18)

Reference frequency
Output of prog. divider
Output of in·lock detector
low = out·of·lock
high = in·lock

Table 7. Control Information
TRANSMISSION

SB2

SLA

PDMI

PDMO

Control 1
Control 2
Control 3

1
1
1

0
1
1

0
0
1

X
X
1

x = don't

care

The word length is defined as the number of
clock pulses during the time interval
DLEN = '1', i.e., the number of data bits plus
1 (start bit). The word length for the SAA1057
is 17.
Correctly received data are transferred to
their latch by another pulse on the CLCK line,
the so·called load pulse. Clock pulses need
not be symmetric; however, minimum high
and low times should be observed.
Due to internal data shifting there is a time
after the reception of the load pulse during
which the SAA 1057 does not react to infor·
mation on the CBUS lines. This time is called
busy time. Under worst case conditions this
busy time is as long as 1.3 milliseconds, i.e. a
following data transmission to the SAA1057
must not start before 1.3 milliseconds have
passed since the trailing edge of the load
pulse. If the following transmission is, howev·
er, intended for a different device, e.g. a
display driver, it may start as early as 51's
after the load pulse for the SAA1057.
Frequency Information
The organization of the data word for the
setting of frequency is shown in Figure 10.
Frequency is expressed as a dividing number,
N, for the programmable divider according to
the following formulae:
NAM

=

32 'fOSCAM

'

fREF
32 'fOSCFM
NFM=
'
10'fREF

February 1987

(23)
(24)

with fosc being the VCO frequency (nor·
mally the sum of tuning fre·
quency and IF) and
fREF being the reference frequency
at the digital PD of either
32kHz or 40kHz.
The dividing number has then to be convert·
ed to binary notation in a 15·bit format as
shown in Figure 10 and a '0' added for the
register select bit, thereby defining latch A as
the destination of the data word.
Due to the applied divider principle, the mini·
mum dividing number is Nmin = 512. In case a
smaller value is transmitted, N = 512 will be
programmed. The maximum dividing number
of Nmax = 32767 results from the 15·bit
length. The total programming range of the
SAA1057 is given in Table 4.
Concerning the usability of the given pro·
gramming range the frequency limits of the
SAA1057 (AM: 0.512 to 32M Hz, FM: 60 to
120M Hz) as well as any relevant licensing
regulations (e.g., FCC, GPO etc.) have to be
observed.
Control Information
The organization of the data word for the
transmission of control information is shown
in Figure 11.

By setting the control bits either low or high
the mode of operation of the SAA 1057 is
programmed. The register select bit is always
'1' to define latch B as the destination of
control information.
Control bit FM - With the control bit FM
either the frequency at the AM input

4-215

AN197

Control bit REFH - With the control bit
REFH the reference divider can be pro·
grammed for two different dividing numbers,
Nro = 125 and Nr1 = 100. In connection with
the 4MHz reference oscillator this results in
the reference frequencies frO = 32kHz and
fr1 = 40kHz and the sampling frequencies
fso = 1kHz (REFH = '0') and f51 = 1.25kHz
(REFH = '1 '), respectively.
Control bits CP3 to CPO - With the control
bits CP3 through CPO the gain of the gain·
programmable current amplifier is influenced.
In addition to a minimum gain there are 4
steps available which may be combined at
will. In Table 2 there are given some program·
ming examples and the resulting loop filter
input currents under control of the digital PD.
With a given loop filter the PLL gain can be
changed under software control in a range of
1 to 100 with intermediate values resulting
from programming of bit combinations. The
current from the analog PD depends on the
amount of phase error and the supply voltage, VCC2, as outlined in section 3.4. See also
Table 3 for some current values.
Control bit SB2 - With the control bit SB2 it
can be chosen whether the features/test bits
(lower half of control word) shall be used
(SB2 = '1 ') or not (SB2 = '0'). In case of
SB2 = '0' the lower 8 bits of the control word
are interpreted as all "zeros" independent of
the actual transmitted bit pattern. Please
note, that the length of the control word must
not be shortened in view of the format requirements of the SAA1057. In case of
SB2 = '1' the actual value of the lower 8 bits
is used.
Control bit SLA - With this control bit it can
be chosen whether transmitted frequency
information is loaded into the programmable
divider immediately after reception
(SLA = '0') or synchronized to the sampling
frequency (SLA = '1 'J.

Asynchronous loading is mandatory for frequency changes of more than 31 tuning
steps, e.g., when recalling a pre-programmed
station from memory. Synchronous loading
(SLA = '1 'J is recommended for manual tuning without muting in order to minimize tuning
noise.
Control bits PDM1, PDMO - With these
control bits the operating mode of the phase
detectors is selected according to Table 5.

The meaning of automatic on/off is that in
case of a phase error exceeding the operating range of the analog PD the digital PD is

Signetics Linear Products

Application Note

Analysis and Basic Application of the SAA1057

SEND CONTROL 1

OUTPUT SILT

DELAY 1

OUTPUT SILT
DELAY 1

SEND CONTROL 1

SEND CONTROL 2

SEND FREQUENCY

SEND FREQUENCY

AN197

SEND FREQUENCY

DELAY 2

NO

DELAY 3
SEND CONTROL 3
OUTPUT SILT

SILT = §lbent luning (Switching Signal)

Figure 12. Data Sequences for the Synthesizer

February 1987

4-216

Signetics Linear Products

Application Note

Analysis and Basic Application of the SAA1057

Vee

Please note, that between consecutive transmissions to the SAA 1057 there has to be a
minimum time delay of 1.3 milliseconds
(SLA = '1'). This need not necessarily be a
restriction, as processing of data in the microcomputer, e.g. BCD to binary conversion or
operating a display driver, also takes time.

Vee

"1r

c

R

TO

100

SAA
1057

V
TO

cr

a)

SAA

1057

b)
Figure 13. Power Supply Filtering

automatically switched on. It is switched off
again as described in section 2.5, i.e. if the
analog PO's operating range has not been
exceeded during three consecutive sampling
periods. For the in· lock condition it is recom·
mended to switch the digital PO permanently
off in order to improve the digital PO perma·
nently off in order to improve the veo's
spectral purity. Otherwise, induced distur·
bances could cause a temporary out·of·lock
condition and, thus, an audible noise.
Control bit BRM - With this control bit the
bus receiver mode is selected, i.e. whether
the bus receiver is permanently switched on
(BRM = '0') or automatically switched off af·
ter each data transmission (BRM = '1') in
order to reduce the current drain.
Control bits T3 to TO - These bits are test
bits. T3 and Tl must always be programmed
low. With T2 and TO a few internal signals can
be put out at Pin 18 (TEST) as shown in
Table 6.

Software Considerations
After power has been applied to the SAA
1057, an initialization must be performed
before any meaningful data transmission
takes place. This initialization can either con·
sist of a train of at least 10 clock pulses on
the CLCK line and afterwards a transmission
of control information (word B) or by transmit·
ting that control information twice, as it contains a sufficient number of clock pulses.
A number of radio tuning operations is exe·
cuted with the audio part being mute in order
to suppress any tuning noise. This applies to
recalling of stored stations, executing numeri·
cal frequency inputs, changing of wave bands
and to automatic search tuning. During manu·
al tuning undistorted listening should be pas·
sible. From the above there result a few
different sequences of data transmissions
from a MC to the SAA1057, as shown in
Figure 12.

February 1987

It is assumed that at power·up the receiver is
silent. Therefore, no SILT signal need be
output to operate switching or squelch
circuitry.
In Table 7 a proposal is made for a few
control bits which are not dictated by tuner
characteristics or test signals.
FM and REFH depend on the current wave·
band and the desired veo step size. ep3 to
CPO depend on the tuner characteristics and
tuning time specification, their programming
need not be the same for each control word.
The word" control 3" sets the synthesizer to
synchronous loading of frequency data, i.e.
no extra control information is required in
case of manual tuning, and switches the
digital phase detector off for best spectral
purity of the tuner's yeo.
The different delays shown in Figure 12 serve
for the following purposes. 'Delay l' is intend·
ed to permit the audio squelch circuitry to
reach a certain muting depth before tuning
changes. The time is typically in the range
between 0 and 50 milliseconds. 'Delay 2' is to
adjust search tuning sweep speed to a speci·
fied value. The time depends largely on the
frequency step size and on receiver time
constants. In case of the minimum step size
there might be no delay allowed at all. Time is
typically between 0 and 50 milliseconds. During 'delay 3' the actual tuning process takes
place. In order to permit any frequency to be
tuned to, this time is normally between 200
and 500 milliseconds.
The path for manual tuning in Figure 12
depends on the type of actuator, e.g. tuning
knob or plus/minus buttons. In case of a
tuning knob the tuning speed depends on the
user's action. In case of plus/minus buttons
and one step per operation it is nearly the
same. But in case of an auto-repeat function
some time delay is required to adjust the
speed, as shown for the path of automatic
search tuning.

4-217

AN197

Power Supply Requirements
As shown in Figure 2, two different supply
voltages are required for the SAA1057.
VCCl/2 is between 3.6 and 12 volts and VCC3
between VCC2 and 31 volts, depending on the
varactor diodes used in the tuner. If the full
programming range of the gain-programmable current amplifier is to be used, VCCl/2
should, however, not be less than 5 volts.
Power supply ripple cannot be neglected
because of the limited ripple rejection of the
SAA1057. For the calculation of permissible
power supply ripple let us assume the following;
- we use an FM tuner
- the maximum slope is Svco = 3MHzIV
- the desired signal-to-noise ratio is
SNR = 75dB
- SN R is based on a deviation of
Ilf = ± 40kHz
- SNR depends on supply ripple only
From the data sheet it can be seen that the
rejection of VCC2 and VCC3 ripple is dominating. If we assume both voltages to be of equal
influence each of them has to give an SNR
which is 3dB better than specified. The permissible supply ripple voltage (peak-to-peak)
can be calculated from
2 • Ilf
(rVCCi - SNR - 3dB)
V Vce- = - - • 10 .:...o.:::.:::...--,-_ _--=r,
I
Svco
20
(25)

with i = 2 or 3, indicating VCC2, VCC3
rVCCi = ripple rejection of VCCi in dB
For the data assumed above we will get
Vr VCC2 = 0.6mV peak-to-peak
Vr:VCC3 = 6mV peak-to-peak
In other words, if the power supply ripple in
the basic application of Figure 2 is not greater
than indicated above, an overall signal-tonoise ratio of 75dB can be achieved with a
VCO slope of 3MHzIV and no other noise
sources being present.
If, however, the actual power supply ripple is
larger than the limit calculated for a desired
SNR, additional filtering has to be used. The
design of a filter circuit depends on the
permitted voltage drop. If a drop of several
volts is acceptable, a circuit as given in Figure
13a can be used. If the drop should be less
than lV, Figure 13b could be used.

Signetics Linear Products

Application Note

Analysis and Basic Application of the SAA1057

Let us assume that a stabilized supply voltage
of BV with a maximum ripple of 5mV peak-topeak is available, We choose the filter circuit
of Figure 13a to generate the supply voltage
VCC1/2' The attenuation is given by
a = 20 -109Yl + (",RC)2

(26)

The required attenuation is 20 - log (51
0,6) = 1B,5dB, In order not to operate the
SAA 1057 below 5V, the drop across R should
be less than 3V, Thus,
Rmax

3V
= --

lBmA

= 16711

detector, giving improvements in tuning
speed as well as in spectral purity of the VCO,
The use of the same reference frequency for
both AM and FM tuning simplifies the design
of the loop filter. The PLL gain can be
programmed in a range of 1 to 100 under
software control, thereby eliminating the need
for switching of external loop filter components.

For the basic application to AM/FM radios
there is information given on hardware, software, power supply and a design example for
the calculation of the loop filter.

AN197

The tuning time from one end of the band to
the other is assumed to be not longer than
004 seconds, If we split this time into equal
parts for the slew and settle times, we can
calculate capacitor C4 by rewriting equation
(15) as
C4 '" tsl ew - Idig
2 - AVtune

(15a)

For the first trial a medium value is taken for
the loop filter current, e,g,
Idig = 0,1 mA (CP = 0010)
We then get from Equation (15a)

We select
R = 15011
C = l00I'F

BIBLIOGRAPHY

and obtain an attenuation of
a=21dB ® fr=120Hz

2,

1.

Now let us calculate component values for
Figure 13b as a filter for VCC3' Let us assume
a supply voltage of 30V with a ripple of 1 Vp_p
and a maximum tuning voltage of 27V, The
allowed voltage drop should be less than lV,
The required filter attenuation is 20 log
(1/0,006) = 4404dB, Again the attenuation is
given by Equation (26), The voltage drop is
(27)
with
IE = load current = ICC3

3,
4,

5,
6,

Phase-Locked Loop Systems Data Book;
Motorola Inc" 1973,
p, Atkinson eta!.: "Design of Type 2
Digital Phase-Locked Loops," The Radio
and Electronic Engineer; November
1975,
R. Best: Theorie und Anwendungen des
Phase-Locked Loops; AT-Verlag, 1976,
AB, Przedpelski: "Analyze, don't estimate, phase-locked-loop," Electronic
Design, May 10, 197B,
H, Geschwinde: Eintahrung in die PLLTechnik; Vieweg, 197B,
M,J, Underhill: "Phase Lock Frequency
Synthesis for Communications," Symposium on Phase Lock Loops and Applications, Delft University of Technology,
January 19BO,

and obtain
a = 4404dB
AV = O,7V

APPENDIX

Design Example
® fr = 120Hz
®VBE = O,6V
B = 100
IE = lmA

In case of higher attenuation, I.e, a larger time
constant R - C, a speed-up path for a quick
charging of C at power-on should be provided, Otherwise, VCC3 could reach its nominal
value too late and tuning to the desired
frequency can be delayed,

SUMMARY
This report has described a new microcomputer-controlled AM/FM radio PLL frequency
synthesizer IC, the SAA 1057, and its basic
application,
There are several unique design ideas realized in the IC_ The most important is the
combination of a digital and an analog phase

February 19B7

C4 = O,331'F
and calculate an approximate slew time of
tslew '" 0,16 seconds
Now we have to determine the lower limit of
the loop's natural frequency and see if the
actual frequency is larger. From Figure 6 we
read "'nt = 7 for a maximum overshoot of 1
010 at an optimum damping factor of 0,7, We
re-write Equation (16) as
Wn

Based on the Circuit Diagram of Figure 2 a
PLL frequency synthesizer for an FM radio
shall be designed, The following tuner data
are given:
tuning range
fRF = BB to 10BMHz
tuning steps
AfRF = 10kHz
intermediate frequency
flF = 10,70MHz
Vtune = 4 to 2BV
tuning voltage
VCOgain
SVCO = 3,0 to O,3MHzIV
Svco is assumed to decrease linearly from
the low end of the tuning range to the high
end,
From the tuning step size it is obvious to use
REFH = 0, I.e" 32kHz reference frequency,
Using Equation (24) we can calculate the min
and max values of the dividing number, N, for
the programmable divider:
Nmin = 9B70
Nmax = llB70

·t

Wn = - -

(16a)

tsettle

and calculate
wn,min

B = DC gain of transistor
We select
R = 10k11
C = 221'F

C4 '" Oo4l'F
We choose the closest standard capacitor
value of

~ 355- 1

with tsettle = 0,2 seconds being our initial
assumption, Using Equation (12) we calculate
the loop's natural frequency for the low and
high ends of the tuning range,
"'n,low = 304 s-1
"'n,high = BB S-1
As both values are well above the minimum,
the settling time will not be larger than assumed and we will not have to change the
assumptions made so far.
Now, we have to solve for resistor, R2,
Looking at Equation (11) we quickly realize
that the damping factor, \, will change with
"'n, thereby influencing the overshoot Let us
try to solve this dilemma by calculating R2 for
the mid of the tuning range, We take
N = 10B70
Svco = 1, 7MHzIV
Idig = O,lmA
\ = 0,7
C4 = O,331'F
and get
"'n = 21B S-1
R2 = 1950011

4-218

Signetics Linear Products

Application Note

Analysis and Basic Application of the SAA1057

We choose a standard resistor value of
R2 = 18klG
and check the damping factor with the aid of
Equation (11) at the ends of the tuning range
end get
tlow = 0.87
thigh = 0.25
The low
end the
resulting
shoot of
time of

end value is still good. At the high
response is highly under-damped,
in wnt = 18 for a maximum over1 0/0. That would mean a settling
t.ettle = 0.2 seconds

which is equal to our assumption. In reality,
the digital phase detector will be switched off
earlier due to the action of the analog PD.
Thus, tuning from one end of the band to the
other is achieved in less than 0.4 seconds. If
the calculated damping factor thigh is regarded too small, a new calculation can be started

February 1987

with a higher current gain, e.g. Idig = 0.3mA
(CP = 0110). This would result in thigh = 0.45
and tlow = 1.56 which is now too large.
For normal applications it seems to be satisfactory to use only one value for the gainprogrammable amplifier. Using more than one
value within one wave-band requires additional software in the jlC because the tuning
frequency has to be checked against some
cross-over frequency.
For the low-pass filter, R3 and C5, we get
from Equation (5) by using wn = Wn,low
4.6ms > R3 • C5

> 0.32ms

We choose the filter time constant to be 1
millisecond, resulting in component values of
e.g.
R3 = 10klG
C5 = 0.1jlF

4-219

AN197

As the filter capaCitor might be designed in
view of RF reasons, a modification may be
necessary which, however, should include R3
to maintain the time-constant of the low-pass
filter.

ADDENDUM
The currently available samples of the
SAA 1057 are stamped as N 1653. These
samples require an extra current of approximately 10jlA at room temperature into Pin 4.
This extra current can most easily be realized
by connecting a resistor between Pins 4 and
16. In this case, the supply voltage VCC1/2
shall not be changed, once a resistor value
has been fixed. For a nominal supply voltage
of VCC1/2 = 5V, a resistor value of 270kn is
an adequate solution at room temperature. At
ambient temperatures above approximately
40 to 45°C it may be necessary to increase
the resistor value.

•

I

TDA8400

Signetics

FLL Tuning Circuit With
Prescaler
Product Specification

Linear Products

DESCRIPTION

FEATURES

The TDA8400 provides closed-loop digital tuning of TV receivers, with or without
AFC, as required. It comprises a 1.1 GHz
prescaler, with the divide-by-64 ratio,
which drives a tuning interface providing
a tuning voltage of 33V (maximum) via
an external output transistor. The
TDA8400 can also drive external PNP
transistors to provide 4 high-current outputs for tuner band selection.

• Combined analog and digital
circuitry minimizes the number of
additional interfacing components
required
• Frequency measurement with
resolution of 50kHz
• On-chip prescaler
• Tuning voltage amplifier
• 4 high-current outputs for direct
band selection
• Tuning with control of speed
• Tuning with or without AFC
• Single-pin, 4MHz, on-Chip
oscillator
• 12C bus slave transceiver

The IC can be used in conjunction with a
microcomputer from the MAB8400 family and is controlled via a two-wire, bidirectional 12C bus.

PIN CONFIGURATION

APPLICATIONS

N Package

TOP VIEW

~~.
1
2

INS
P3

3

P2
P1

• TV receivers
• Satellite receivers
• CATV converters

SCL

SDA
TUN
TI

10

DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

18-Pin DIP (SOT -102 HE, KE)

o to 70°C

TDA8400N

ABSOLUTE MAXIMUM RATINGS

Vccs
Vccp

PARAMETER
Supply voltage:
(Pin 10)
(Pin 15)

VN

Input/output voltage (each pin)

PTOT

Total power dissipation

High~current

Vccs

band-selection

output ports

1

Serial dock line
12C bus
Serial data line
Tuning voltage amplifier output
Tuning voltage amplifier inverting
input
+ 5V supply voltage (synthesizer)
Crystal oscillator input

11

asc

12
13
14
15
16
17

AFCAFC+
OUP
Vccp
VCO+
VCO-

Output from prescaler (test)
+ 5V supply voltage (prescalerf

18

GND

Ground

AFC amplifier inputs

Inputs to prescaler

NOTES:

RATING

UNIT

6
6

V
V

6

V

350

mW

TSTG

Storage temperature range

-65 to + 150

°C

TA

Operating ambient temperature range

-10 to +80

°C

February 12, 1987

DESCRIPTION

Input synthesizer (test) 1

PO

ORDERING INFORMATION

SYMBOL

SYMBOL

4-220

1. Connected to ground for application.
2. Left open-circuit for application.

853-117487583

Signetics Linear Products

Product Specification

TDA8400

FlL Tuning Circuit With Prescaler

BLOCK DIAGRAM

IIces

-fl

04MHz

vcc-

VC~

osc

16

17

11

15

TDA8400

14

t-------;:::::::::::::~--------~---ooup
15-81T
FREQUENCy BUFFER

SCL

<>--"+--1

t--------------i-----------------1---o INS

BANOSWITCHES
+1211

[Eo]J (f~:m [ECl
TUNING CONTROL CIRCUIT
W!J I AFCFI

Gil
30V

12·81T

TUNING COUNTER

AFC+o-~13~--------------------------------------------~A~F~C~~
AFC_o-_'~24_------------------------------------------~~~~

February 12, 1987

4-221

TI

"rUN

Signetics Linear Products

Product Specification

TDA8400

FLL Tuning Circuit With Prescaler

DC ELECTRICAL CHARACTERISTICS TA = 25'C; vccs, Vccp at typical voltages, unless otherwise specified.
LIMITS

SYMBOL

PARAMETER

Vccs
Vccp

Supply voltage
Synthesizer (Pin 10)
Prescaler (Pin 15)

Iccs
Iccp

Supply current
Synthesizer (Pin 10)
Prescaler (Pin 15)

UNIT
Min

Typ

Max

4.5
4.5

5
5

5.5
5.5

12
43

V
V
rnA
rnA

PTOT

Total power dissipation

TA

Operating ambient temperature range

0

275
+70

'C

TSTG

Operating storage temperature range

-10

+85

'C

V

mW

12C bus inputs/outputs Inputs: SDA (Pin 7); SCL (Pin 6)
VIH

Input voltage HIGH

3.1

5.5

VIL

Input voltage LOW

-0.3

1.6

V

IIH

Input current HIGH

10

JlA

Input current LOW

10

IlA

IlL

SDA output (Pin 7, open-collector)
VOL

Output voltage LOW at IOL = 3mA

IOL

Output sink current

004

V

5

rnA

Tuning voltage amplifier Input TI, output TUN (Pins 9, 8)
ITI

Input bias current

-5

-ITUNL

Output current LOW at VTUN = OAV

20

CHo
CH 1

Minimum charge IT to tuning amplifier
TUHN =0
TUHN = 1

5
125

JlA'Jls
/lA'JlS

ITO
IT1

Maximum current I into tuning amplifier
TUHN =0
TUHN = 1

18
440

/lA
/lA

+5

nA

/lA

AFC amplifier (Inputs AFC+, AFC- Pins 13, 12)
VOIF

Differential input voltage

g1

Transconductance at AFCS = 1

go
VCM
CMRR

Common mode rejection ratio

50

PSRR

Power supply (VCC1) rejection ratio

50

II

Input current

5

10

Transconductance at AFCS = 0

30

50

Common mode input voltage

2.5

1

V

15

/lA1V
/lA1V

70
VCC1- 1

V
dB
dB

1

JlA

1.2
10

rnA
IlA

Main band-selection output ports PO, P1, P2, P3 (Pins 5 to 2, open-colleclor)
IBSL1
IBSH1

Output sink current
LOW impedance
HIGH impedance

February 12, 1987

0.8

4-222

1

Signetics Linear Products

Product Specification

TDA8400

FLL Tuning Circuit With Prescaler

DC ELECTRICAL CHARACTERISTICS (Continued) TA = 25°C; VCCS, Vccp at typical voltages, unless otherwise specified.
LIMITS
PARAMETER

SYMBOL

UNIT
Typ

Min

Max

Prescaler Inputs (VCO+ Pin 16; VCO- Pin 17)
VI(RMS)
VI(RMS)
VI(RMS)
VI(RMS)
VI(RMS)
VI(RMS)

Input differential voltage (RMS value)
at f = 70MHz
at f = 150MHz
at f = 300MHz
at f = 500MHz
at f = 900MHz
at f = 1.1GHz

17.5
10
10
10
10
25

200
200
200
200
200
200

mV
mV
mV
mV
mV
mV

fl

Input frequency

0.07

1.1

GHz

150

n

4

V

OSC input (Pin 11)
RXTAl

Crystal resistance at resonance (4MHz)

Power-down reset
VPD

Maximum supply voltage VCC1 at which power-down reset is
active

3

Voltage level for valid module address
Voltage level PO (Pin 5) for valid module address as a function
of MA1, MAO

VVA01
VVA10
VVA11

MA1

MAO

0

0

0
1
1

1
0
1

FUNCTIONAL DESCRIPTION

Prescaler
The integrated prescaler has a divide-by-64
ratio with a maximum input frequency of
1.1 GHz. It will oscillate in the absence of an
input signal within the frequency range of
BOOMHz to 1.1GHz.

Tuning
This is performed using frequency-locked loop
digital control. Data corresponding to the required tuner frequency is stored in the 15-bit
frequency buffer. The actual tuner frequency
(1.1GHz maximum) is applied to the circuit on
the two complementary inputs VCO+ and
VCO- which drive the integrated prescaler.
The resulting frequency (FDIV) is measured
over a period controlled by a time reference
counter and fed via a gate to a 15-bit frequency counter where it is compared to the contents of the frequency buffer. The result of the
comparison is used to control the tuning
voltage so that the tuner frequency equals the
contents of the frequency buffer multiplied by
50kHz within a programmable tuning window
(TUW).
The system cycles over a period of 2.56ms,
controlled by the time reference counter which
is clocked by an on-Chip 4MHz reference
oscillator. Regulation of the tuning voltage is
performed by a charge pump frequencyFebruary 12, 19B7

I

I

""tH"r

-0.3
2.4
VCCs-0.3
locked loop system. The charge IT flowing into
the tuning voltage amplifier (external capacitance CINT = 0.5,.,F) is controlled by the tuning
counter, 3-bit DAC, and the charge pump
circuit. The charge IT is linear with the frequency deviation Af in steps of 50kHz. For
loop gain control, the relationship AIT I Af is
programmable. In the normal mode (control bit
TUHN = logiC 1; see Table 2) the minimum
charge IT at Af = 50kHz equals 125,.,A-/lS
(typ.).
By programming the tuning sensitivity bits
(TUS; see Table 3) the charge IT can be
doubled up to 6 times. From this, the maximum charge IT at Af = 50kHz equals
26 X 125,.,A-,.,s (typ.). The maximum tuning
current I is 440,.,A, while T is limited to the
duration of the tuning cycle (2.56ms).
In the tuning-hold mode (TUHN = logic 0) the
tuning current I is reduced, and, as a consequence, the charge into the tuning amplifier is
also reduced. An in-lock situation can be
detected by reading FLOCK. The TDAB400
can be programmed to tune in the digital mode
or the AFC mode by setting AFCF. In the
digital mode (AFCF = logic 0), the tuning window is programmable through the TUW flag.
When the tuner oscillator frequency is within
the programmable tuning window (TUW),
FLOCK is set to logic 1.

4-223

O.B
Vccs - 1.6
VCCS

V
V
V

In the AFC mode, FLOCK will remain at logic 1
provided the tuner frequency is within a
± BOOkHz hold range. Switching from digital
mode to AFC mode is determined by the
microcontroller (AFCF flag). Switching from
AFC mode to digital mode can be determined
by the microcontroller, but if the frequency of
the tuning oscillator does not remain within the
hold range, the system automatically reverts
to digital tuning. Switching back to the AFC
mode will then have to be effected externally
again. The tuning mode can be checked by
reading the AFCT flag.
The occurence of positive and negative transitions in the FLOCK signal can be read by FLI
1Nand FLION. The AFC amplifier has programmable transconductance to 2 predefined
values.

Control
For tuner band selection there are four output
ports, PO to P3, which are capable of driving
external PNP transistors (open collector) as
current sources. Output port PO can also be
used as valid address input with an active
level determined by module address bits MAO
and MA1.

Reset
The TDAB400 goes into the power-down reset
mode when VCC1 is below 3V (typ.). In this
mode all registers are set to a defined state.

Signetics Linear Products

Product Specification

FLl Tuning Circuit With Prescaler

TDA8400

INSTRUCTION BYTE

MODULE ADDRESS

DATA/CONTROL BYTE

MA MA

l

Msa

Msa

_Msa
RIW

c

Figure 1. 12

Bus Write Format

DATA/CONTROl. BYTE

INSTRUCTION BYTE

"
FREQ

TCDO
TEST

"

'0

D.

0,

D.

0,

0,

"

"

0,

"

'.

0,

"
FlO

F13

F,2

FII

F'O

F9

F8

F7

F6

F,

FO

F3

F2

F'

FO

TUHN

TUS2

TUS'

TUSO

P3

P2

P'

PO

TUW

AFCS

AFCF

TCD1

Do

Figure 2. Tuning Control Format

OPERATION
Write

Table 2. Tuning Current Control

The TDA8400 is controlled via a bidirectional
two·wire 12 C bus; additional information on the
12C bus is available on request.
For programming, a module address, R/W bit
(logic 0), an instruction byte, and a datal
control byte are written into the device in the
format shown in Figure 1.
The module address bits MA1, MAO are used
to give a 2·bit module address as a function of
the voltage at port input PO as shown in Table
1.

Table 1. Valid Module Addresses
PO
Don't care
GND
Y2 Vees
Vees

MA1

MAO

0
0
1
1

0
1
0
1

Acknowledge (A) is generated by the TDA8400
only when a valid address is received and the
device is not in the power·down reset mode.

Tuning
Tuning is controlled by the instruction and
data/control bytes as shown in Figure 2.
Frequency
Frequency is set when Bit 17 of the instruction
byte is set to logic 1; the remaining bits of this
byte are processed as being data. Instruction
bytes are fully decoded. All frequency bits are
set to logic 1 and control bits to logic 0 at reset.
The test instruction byte cannot be used for
any other purpose.
February 12, 1987

TUHN

TYP.IMAX
(j.tA)

TYP.ITM'N
(j.tA/j.ts)

0
1

18'
440

5'
125

NOTE:

1. Values after reset.
Tuning Hold
The TUHN bit is used to decrease the maxi·
mum tuning current (I) and, as a consequence,
the minimum charge IT (at Af = 50kHz) into the
tuning amplifier.
Tuning Sensitivity
To be able to program an optimum loop gain,
the charge IT can be programmed by changing
T using tuning sensitivity (TUS). Table 3 shows
the minimum charge IT obtained by programming the TUS bits at Af = 50kHz;
TUHN = logic 1.

Table 3. Minimum Charge IT as
a Function of TUS
TUS2
0
0
0
0
1
1
1

TUS1
0
0
1
1
0
0
1

TUSO
0
1
0
1
0
1
0

NOTE:
The minimum tuning pulse is 21JS.

4-224

TYP.
ITM'N
(mA·j.ts)
0.125
0.25
0.5
1
2
4
8

Tuning Mode
AFCF determines whether the TDA8400 has to
tune in the digital mode or the AFC mode as
shown in Table 4.

Table 4. Selection of Tuning
Mode as a Function of
AFCF
AFCF

TUNING MODE

0
1

Digital
AFC

If the tuner oscillator frequency comes out of
the hold range when in the AFC mode, the
device will automatically switch to digital tuning
and AFCF is reset to logic O.
Tuning Window
In the digital tuning mode TUW determines the
tuning window (see Table 5) and the device is
said to be in the "in-lock" situation.

Table 5. Tuning Window
Programming
TUW

TUNING WINDOW (kHz)

0
1

0
±200

Signetics Linear Products

Product Specification

FLL Tuning Circuit With Prescaler

TDA8400

FOV

Transconductance

Read

The transconductance (g) of the AFC amplifier is programmed via the AFC sensitivity bit
AFCS as shown in Table 6.

Information is read from the TDA8400 when
the R/W bit is set to logic 1. Only one
information byte is sent from the device. No
acknowledge is required from the master
after transmitting. The format of the information byte is shown in Figure 3.

Table 6_ Transconductance
Programming
AFCS

TYP.

Tuning/Reset Information Bits

TRANSCONDUCTANCE

1
0

(/lA/V)

10
50

Band Selection Control Ports
(PX)
For band selection control, there are four
output ports, PO to P3, which are capable of
driving external PNP transistors (open collector) as current sources. If a logic 1 is programmed on any of the PX bits PO to P3. the
PNP transistor will conduct and the relevant
output goes LOW. All outputs are HIGH after
reset.

FLOCK Set to logic 1 when the tuning oscillator frequency is within the programmed tuning window (TUW) in the
digital tuning mode, or within the
± 800kHz AFC hold range in the AFC
mode.
FLl1 N Set to logic 0 (Active-LOW) when
FLOCK changes from 0 to 1 and is
reset to logic 1 automatically after
tuning information has been read.

Indicates frequency overflow. When
the tuner oscillator frequency is too
high with respect to the programmed
frequency, FOV is at logic 1, and,
when too low, FOV is at logic O.

RESN Set to logic 0 (active Low) by a
power-down reset. It is reset to logic
1 automatically after tuning/reset information has been read.
MWN

MWN (frequency measuring window,
Active-LOW) is at logic 1 for a period
of 1.28ms, during which time the
results of frequency measurement
are processed. During the remaining
time, MWN is at logic 0 and the
received frequency is measured.

AFCT

AFCT (tuning mode flag) is set to
logic 1 when the TDA8400 is in AFC
mode and reset to logic 0 when in the
digital mode.

FLION Same as for FL/1 N but it is set to
logic 0 when FLOCK changes from 1
to O.

TUNING/RESET INFORMATION

MODULE ADDRESS

~~:~
g

RESN

FOV
FLJON
L-_ _ _ _ _ _ _ _ _ FLJ1N
L-------------FLOCK
L--------------FROMTOA.~O

Figure 3. Information Byte Format

February 12, 1987

4-225

1001742

Signetics

CMOS Frequency Synthesizer
Preliminary Specification

Linear Products
PIN CONFIGURATION

DESCRIPTION

FEATURES

The TDD1742 is a CMOS low-current
frequency synthesizer IC designed for
VHF/UHF portable or mobile transceivers. This IC combines in a single chip
many features of the HEF4751 (divider
circuit), and HEF4750 (synthesizer), including a high-gain phase comparator,
using a sample-and-hold technique. A
multiplexed or bus-structured programming sequence has been adopted to
allow interfacing to an external ROM or
a microcontroller. Operation down to a
7V supply rail is possible with a maximum input frequency of 8.5MHz.

• Single-chip with on-board
sample-and-hold capacitor
• Low power requirements
• High-performance phase
comparator with low phase noise
and spurious response
• Auxiliary digital phase
comparator for fast locking
• On-board phase modulator
• Simple interface to memory
• Microprocessor controllable
• Power-on reset circuitry

Figure 1 shows the functional block
diagram of the TDD1742 with the principal features of a reference oscillator,
programmable reference and main dividers, the two phase comparators, phase
modulator, and the programming input
interfaces.

D Package

APPLICATIONS
• Cellular radio
• Digital frequency synthesizers
• Communications equipment
(HF-UHF)
• Portable transceivers

TOP VIEW
00013605

PIN NO.

1
2

ORDERING INFORMATION
DESCRIPTION

SYMBOL
VOD3

PCl
PC2

TEMPERATURE RANGE

ORDER CODE

-40°C to + 85°C

TDD1742TD

28-Pin Plastic DIP (SOT-136A)

Test 2
Test 1

Vss
RF IN
VOO2

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VOO1,
VOO2,
VOO3

PARAMETER
Supply voltage
Voltage on any input

RATING

UNIT

-0.5 to + 15

V

-0.5 to VOOl +0.5

V

0.5

V

Voor Vool

Relative supply voltage

VOO3- VOOl

Relative supply voltage

0.5

V

Direct current into any input

±10

mA

Direct current into any output

±10

mA

Po

Power dissipation
TA = 0 to +85°C

500

mW

TSTG

Storage temperature

-65 to +150

°C

TA

Operating ambient temperature

-40 to +85

°C

February 1987

4-226

9
10

11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

FB
OL
RES
XTAL
OSC
VOD1

DB3
DB2
DBl
DBO
ABO
ABl
AB2
PE2
PEl
MOD
MEMEN
TRB
TRC
TRA

DESCRIPTION

Main power supply; + 7 to + 10V
High-gain phase comparator
(analog)
Low-gain phase comparator
(digital)

Test pin
Test pin
Positive power supply
RF input
Power supply for TIL-compatible
stages; + 5V ± 10%
Feedback to prescaler
Out-af-Iock indication
Power-on reset
Reference oscillator/buffer output
Reference oscillator/buffer input
Main power supply; + 7 to + 10V
Data bus inputs
Data bus inputs
Data bus inputs
Data bus inputs
Address bus
Address bus
Address bus
Program enable 2
Program enable 1
Phase modulation input
Memory enable
Bias resistor As
Bias resistor Rc
Bias resistor RA

Signetics Linear Products

Preliminary Specification

CMOS Frequency Synthesizer

TDD1742

BLOCK DIAGRAM
TRB

MOD

,---------1-0 TRA
~-----_+~~l

IN

I----+OTRC
~r-r-+-------~PC.

•.
' ..'.

,y,

DBO~§

I

DBl
DB.
DB3

ABO

_......,1------+1

PROGRAM DATA

~=~====:::I

PROM CONTROL

AB2
AB, ....

PE2
PEl

YEMEN

DECODER AND
CIRCUITRY

;;::t====~S

RESo-......,~-----:::::::::J--------~

CLKON.-=::~Jr-----------~
esc

February 1987

XTAL

4-227

Signetics Linear Products

Preliminary Specification

TDD1742

CMOS Frequency Synthesizer

PIN DESCRIPTIONS AND FUNCTIONS
SYMBOL

DESCRIPTION

Inputs

DBO to DB3

TTL-compatible data bus inputs

PEl, PE2

TTL-compatible program enable inputs which initiate the programming cycle or strobe the internal data
latches

IN

Input to the main programmable divider, usually from a prescaler

OSC

Input to reference oscillator which, together with the XTAL output and an external crystal, is used to
generate the reference frequency. Alternatively, the OSC input may be used as a buffer amplifier for an
external reference oscillator

RES

Power-on reset; following power-up, an initial pulse is applied to this pin to set the internal counters

MOD

High-impedance linear phase modulator input, which applies a vOltage-controlled delay to the output of
the programmable divider before being applied to the phase comparator input

Outputs

PCt

High gain phase comparator output is used when the system is in lock to give low levels 01 noise and
spurious outputs. This comparator uses a sample-and-hold technique similar to that used in the
HEF4750, but in the TDD1742 the sample-and-hold capacitor is on-chip

PC2

Low gain digital phase comparator which enables fast lock times to be achieved when the system
initially is out-ol-Iock. This comparator is inhibited when the phase is within the locking range 01 PC1,
i.e., tristate output

OL

Out-ol-Iock flag which is HIGH when the digital phase comparator PC2 is in operation, i.e., when the
system is out-oj-lock

FB

Feedback output to control the modulus 01 the external prescaler

XTAL

Output to lorm crystal oscillator circuit in combination with the OSC input

Bidirectional pins

ABO-AB2

TTL-compatible bidirectional address bus. Provides address output to an external memory or receives
output Irom a microcomputer. The outputs are all tristate with internal pulldowns

MEMEN

Mode control and memory enable pin. At general reset, the mode 01 operation can be set to
microcomputer mode, MEMEN LOW, or memory mode, MEMEN HIGH. For further inlormation, see
PROGRAMMING section

TRA

Current mirror pin lor control 01 the gain 01 PCt

TRB

Current mirror pin lor control of the phase modulator gain

TRC

Current mirror pin lor analog biasing

T1 & T2

Test pins should be left unconnected

February 1987

4-228

Signetics Linear Products

Preliminary Specification

TDD1742

CMOS Frequency Synthesizer

DC ELECTRICAL CHARACTERISTICS

SYMBOL

at VOO, = 7AV, V002 = 5.0V, V003 = 7AV; voltages are referenced to Vss, unless
otherwise noted.

LIMITS

PARAMETER
Min

Typ

UNIT
Max

Quiescent device current 2, 3

1.5
100
1.5

mA
IlA
mA

±IIN

Input current logic inputs, MOD 2, 3

300

nA

± Iz
±Iz

Output leakage current at '12 V002. 3
PC2, high-impedance OFF-state
MEMENB, high-impedance state

50
1.6

nA
IlA

Iz

1/0 current, high-impedance state ABO to AB2

30

IlA

1001
1002
10D3

VIH

Logic input voltage
LOW
CMOS inputs
CMOS 1/0
TTL inputs
TTL 110's
HIGH
CMOS Inputs
CMOS 1/0
TTL inputs
TTL 110's

VOL
VOH

Logic output voltage 2
1101< 11lA
LOW
HIGH 2

VIL
VIL

VIH

VOL
VOL
VDL
VOL
VOL
VOL

5

)
)

0.3V001
0.8

V

)

O.7V001

V

)

2

V

50

mV
mV

VDD1- 5O

Logic output voltage
LOW2
Output MEMENB
10L =4mA
Output PC2
10L = 1.5mA
Outputs CLK, OL
IOL = 1mA
Output XTAL at:
10L = 3mA
Output FB
10L = 1mA
Outputs ABO, AB1, AB2
10L = 0.2mA

1

V

0.5

V

0.5

V

0.5

V

0.5

V

004

V

VOH

Logic output voltage
HIGH 2. 3
Output PC2
10H =-1.5mA
Outputs CLK, OL
IOH=-1mA
Output XTAL at:
IOH =-3mA
Output FB
10H =-1mA
Outputs ABO, AB1 at:
10H = 0.2mA
Output AB2 at:
IOH=0.8mA

204

V

10

Output PC1 sink current 2, 3, 4

1

mA

-10

Output PC 1 source current 2, 3, 5

1

mA

RIN

Internal resistance of PC1, locked state
loutput swing I
200mV, specified output range: 2. 3
0.5VOO - 0.5V to 0.5VDO + 0.5V

VOH
VOH
VOH

VOH
VOH

February 1987

<

4-229

VOD1 - 0.5

V

VD01- 0.5

V

VOD1- 1

V

VOD2- 1

V

204

V

TBD

•

Signetics Linear Products

Preliminary Specification

CMOS Frequency Synthesizer

1DD1742

AC ELECTRICAL CHARACTERISTICS The dynamic specification is given for the circuit, built up with the external
components as given in Figure 4, unless otherwise specified.
LIMITS
SYMBOL

DESCRIPTION

UNIT

TEST CONDITIONS
Min

fiN

Programmable divider input frequency, all division ratios

Square wave input

8.5

Ioiv

Reference divider input frequency, all division ratios

Square wave input

9

fose

Grystal oscillator frequency

GIN

Input capacity IN, aSG

3

pF

GIN

Input capacity DBO to DB3, PE1, PE2, ABO to AB2

5

pF

70
70

ns
ns

9

tpOHL
tpOLH

FB feedback output to externalS prescaler delays IN _ FB

IDO

Average power supply current 3, 7

NOTES:
1. Definitions:
RA = External biasing resistor between pins TRA and V ss
AB = External biasing resistor between pins TRB and Vss
Rc = External biasing resistor between pins TRC and Vss
CA = Decoupling capacitor between pins TRA and Voo
Cs = Decoupling capacitor between pins TRB and Voo
Cc = Decoupling capacitor between pins TRC and Voo

2. All logiC inputs
3. RA connected,
As connected,
Rc connected,

4.

at
its
its
its

CMOS logic inputs
CMOS logic outputs
CMOS logic 1/0
TIL logic inputs
TIL logic output
TIL logic 1/0
Analog inputs
Analog output
Analog biasing pins

Vss or Voo
value chosen such that ITRA = 20pA
value chosen such that ITRB = 20pA
value chosen such that ITRC = 20pA

EQUIVALENT CIRCUIT:

INPUT FORCED LOW
BY 2 PRECEDING R PULSES

:
:
:
:

Locked state

TBD

OSC, RES
Ol, PC2, XTAl, ClK
MEMENB
DBO to DB3, PE1, PE2
ABO to AB2
MOD, IN
PC1
TRA, TRB, TRC

TC20920S

Internal Voltage-Follower VF.
EQUIVALENT CIRCUIT:

INPUT FORCED HIGH
BY 2 PRECEDING V PULSES

[>

~

1~'
":" Vss

Internal Voltage VF.

6.

IN

\.

----,.:~.3O%_---'1

30%

FB----i~-_1~~:---t5--HL
Waveforms IN -

FB

7. fosc = 5MHz, external clock, division ratio 400
fiN = 2MHz, division ratio 160

February 1987

4-230

MHz

12

CL = 10pF

: FB
:
:
:
:

MHz

35
35

r:,

[> -

10

5.

Typ Max

MHz

rnA

Signetics Linear Products

Preliminary Specification

TDD1742

CMOS Frequency Synthesizer

REFERENCE OSCILLATOR AND
DIVIDER CHAIN

MAIN PROGRAMMABLE
DIVIDER

The reference oscillator chain comprises a
crystal oscillator and dividers to give the
required reference frequency drive to the
phase comparators.

The main programmable divider is a rate
feedback binary divider. Referring to the
Block Diagram, the programmable divider
uses a fixed 7-bit binary divider (0-128) and
two rate selectors (n1 and no). One rate
selector controls a 7-bit fully programmable
dual modulus divider (o-n2/n2 + 1) and the
other rate selector controls an external dual
modulus prescaler (o-AiA + 1).

A single inverter is used as an oscillator stage
and oscillates satisfactorily with crystals up to
9MHz. Alternatively, an external reference
source may be applied to the input of this
inverter (OSC pin) at logic level drive or at a
lower level (300mV min) if a biasing resistor is
connected from OSC to XTAL. The reference
divider chain comprises a fixed 0-4 stage
followed by three cascaded programmable
dividers with ratios of 0-12/13/14/15,0-5/6/
7/9 and 0-1/2/4/8. The output of this last
stage is applied as one input to the two phase
comparators. Hence, a number of division
ratios are possible between 240 and 4320,
enabling all the usual VHF and UHF channel
spacings to be accommodated with reference
crystals in the range 1 - 9MHz.

February 1987

The overall division ratio (N) is given by:
N=(128 n2+n1)A+no
where 0 < no < 1 27
0< n1 < 127
1 

dOe
dt

increases and the error voltage

becomes a rapidly varying function of time.
Under this condition the beat note waveform
no longer looks sinusoidal; it looks like a
series of aperiodic cusps, depicted schematically in Figure 2a. Because of its asymmetry,
the beat note waveform contains a finite De
component that pushes the average value of
the veo toward wI> and lock is established.
When the system is in lock, ~w is equal to
zero and only a steady-state DC error voltage
remains.
Figure 2b displays an oscillogram of the loop
error voltage Vd(t) in an actual PLL system
February 1987

Figure 3_ Exhibited by First-Order Fast Capture Transient
during the capture process. Note that as lock
is approached, ~w is reduced, the low-pass
filter attenuation becomes less, and the amplitude of the beat note increases.
The total time taken by the PLL to establish
lock is called the pull-in time. Pull-in time
depends on the initial frequency and phase
differences between the two Signals as well
as on the overall loop gain and the low-pass
filter bandwidth. Under certain conditions, the
pull-in time may be shorter than the period of
the beat note and the loop can lock without
an oscillatory error transient.

4-242

A specific case to illustrate this is shown in
Figure 3. The 565 PLL is shown acquiring
lock within the first cycle of the input signal.
The PLL was able to capture in this short time
because it was operated as a first-order loop
(no low-pass filter) and the input tone-burst
frequency was within its lock and capture
range.

EFFECT OF THE LOW-PASS
FILTER
In the operation of the loop, the low-pass filter
serves a dual function.

Signetics Linear Products

Application Note

Modeling the PLL

AN178

First, by attenuating the high frequency error
components at the output of the phase comparator, it enhances the interference-rejection
characteristics; second, it provides a shortterm memory for the PLL and ensures a rapid
recapture of the signal if the system is thrown
out of lock due to a noise transient. Decreasing the low-pass filter bandwidth has the
following effects on system performance
(Long Time eon stant):
a. The capture process becomes slower, and
the pull-in time increases.
b. The capture range decreases.
c. Interference-rejection properties of the PLL
improve since the error voltage caused by
an interfering frequency is attenuated further by the low-pass filter.
d. The transient response of the loop (the
response of the PLL to sudden changes of
the input frequency within the capture
range) becomes underdamped.
The last effect also produces a practical
limitation on the low-pass loop filter bandwidth and roll-off characteristics from a stability standpoint. These points will be explained
further in the following analysis.

MATHEMATICALLY DEFINING
PLL OPERATION
As mentioned previously, the phase comparator is basically an analog multiplier that forms
the product of an RF input signal, Vi(t), and
the output signal, volt), from the veo. Refer
to Figure 1 and assume that the two signals
to be multiplied can be described by
Vi(t) = VI sin Wit
volt)

(3)

= Vo sin (wot + eel

Wo,

(4)

ee

where wI>
and
are the frequency and
phase difference (or phase error) characteristics of interest. The product of these two
signals is an output voltage given by
ve(t)

= K1VIVo(sin Wit) [sin(wot + eell

(5)

where K1 is an appropriate dimensional constant. Note that the amplitude of ve(t) is
directly proportional to the amplitude of the
input signal VI. The two cases of an unlocked
loop (WI 4= wo) and of a locked loop
(WI = WO) are now considered separately.
Unlocked State (WI 4= wo)
When the two frequencies to the phase
comparator are not synchronized, the loop is
not locked. Furthermore, the phase angle
difference
in Equations 4 and 5 is meaningless for this case since it can be eliminated
by appropriately choosing the time origin.

ee

Using trigonometric identities, Equation 5 can
be rewritten as

Vd(t) = Vo = AK2VIVo cosee

- COS(WI + wo)t]

(6)

When ve(t) is passed through the low-pass
filter, F(s), the sum frequency component is
removed, leaving
VI(t)

= K2VIVOcos (WI - wo)t

(7)

where K2 is a constant. After amplification,
the control voltage for the veo appears as
Vd(t) = AK2VIVOcos (WI - wo)t

(8)

This equation shows that a beat frequency
effect is established between WI and wo,
causing the veo's frequency to deviate by
± Aw from wo' in proportion to the signal
amplitude (AK2VIVo) passing through the filter. If the amplitude of VI is sufficiently large
and if signal limiting or saturation does not
occur, the veo output frequency will be
shifted from wo' by some Aw until lock is
established where
WI = Wo =

wo'±

~w

(9)

If lock cannot be established, then either VI is
too small to drive the veo to produce the
necessary ± Aw deviation or WI is beyond the
dynamic range of the veo, i.e., WI~WO'± Aw.
Remedies for these no lock conditions are:

1. Increase VI either internally or externally to
the loop by providing additional amplification.
2. Increase the internal loop gain by adjusting
upward (larger -3dB frequency) the response of the low-pass filter.
3. Shift wo' closer to the expected WI. Establishing frequency lock leads to the second
case where WI = woo
Locked State (WI = wo)
When WI and Wo are frequency synchronized, the output Signal from the phase comparator for WI = Wo = wand a phase shift of
ee is

K1VI Vo
= - 2 - [cos ee - cos (2wt

+ eel]
(10)

The low-pass filter removes the high frequency, Ae component of ve(t), leaving only the
De component. Thus,
(11)

February 1987

After amplification the De voltage driving the
veo and maintaining lock within the loop is

4-243

(12)

Suppose WI and Wo are perfectly synchronized to the free-running frequency wo'. For
this case, Vo will be zero, indicating that
must be ± 90°. Thus Vo is proportional to the
phase difference or phase error between ei
centered about a reference phase
and
angle of ± 90°. If WI changes slightly from
wo', the first effect will be a change in from
± 90°. Vo will adjust and settle out to some
nonzero value to correct wo; under this
condition frequency lock is maintained with
WI = WOo The phase error will be shifted by
some amount Ae from the reference phase
angle of ± 90°. This concept can be simplified
by redefining
as

ee

eo

ee

ee

(13)

e,

where is the inherent, reference phase shift
of ± 90° and Ae is the departure from this
reference value. Now the veo control voltage becomes
Vo

= AK2VIVo cos (e,± Ae)
(14)

Since the sine function is odd, a momentary
change in Ae contains information about
which way to adjust the veo frequency to
correct and maintain the locked condition.
The maximum range over which Ae changes
can be tracked is _90° to +90°. This corresponds to a
range from 0 to 180°.

ee

In addition to being an error signal, Vo represents the demodulated output of an FM input
applied as Vin(t) assuming a linear veo characteristic. Thus, FM demodulation can be
accomplished with the PLL without the inductively-tuned circuits that are employed with
conventional detectors.

DETERMINING PLL MODEL
PARAMETERS
Since the PLL is basically an electronic servo
loop, many of the analytical techniques developed for control systems are applicable to
phase-locked systems. Whenever phase lock
is established between Vi(t) and volt) the
linear model of Figure 4 can be used to
predict the performance of the PLL system.
represent the phase angles
Here ei and
associated with the input/output waveshapes, respectively; F(s) represents a generalized voltage transfer function for the lowpass filter in the s complex frequency domain;
and Kd and Ko are conversion gains of the
phase comparator and veo, respectively,
each having units as shown. The 1/s term
associated with the veo accounts for the
inherent 90° phase shift in the loop since the
veo converts a voltage to a frequency and

eo

•
I

'....•.
.'

.,

"

Signetics Linear Products

Application Note

Modeling the Pll

ANU8

since phase is the integral of frequency. Thus
the VCO functions as an integrator in the
feedback loop.
Specific values of Kd and Ko for all of
Signetics' general purpose PLLs can be
found in the sections describing the particular
loop of interest. However, sometimes it may
be desired to determine these conversion
gains exactly for a specific device. The measurement scheme shown in Figure 5 can be
used to determine Kd and Ko for a loop under
lock. The function of the Khron-Hite filters is
to extract the fundamental sinusoidal frequency component of their square wave inputs for application to the Gain-Phase Meter.
If the input signal from the Function Generator is sinusoidal, then the first Khron-Hite filter
may be eliminated. It is recommended to use
high impedance oscilloscope probes so as to
not distort the input of VCO waveshapes,
thereby potentially altering their phase relationships. The frequency counter can be driven from the scope as shown, or connected
directly to the input or VCO, provided its input
impedance is large.

8(0)

Figure 4. Linear Model of PLL System

i

... Vcc

- 'BIAS

BlASANO

----"'IV'.-----: GAIN SET

LOW PASS
FILTER

Vo

The procedure to follow for obtaining Kd and
Ko is as follows:

1. Establish the desired external bias and
gain conditions for the PLL under test.
2. With the Function Generator turned off, set
the free-running frequency of the loop via
the timing capacitor and timing resistor if
appropriate. Monitor fa' with the Frequency
Counter.

3. Turn on the Function Generator and check
to make sure the amplitude of the input
signal is appropriate for the particular loop
under test.

4. Adjust the input frequency for lock. Lock is
discernable on a dual-trace scope when
the input and VCO waveforms are synchronized and stationary with respect to each
other. One should be especially careful to
check that locking has not occurred between the VCO and some harmonic frequency. Carefully inspect both waveshapes, making sure each has the same
period. (If a second Frequency Counter is
available, an alternate scheme can be
used to confirm frequency locking. One
frequency counter is used to monitor the
input signal frequency, and the second
counter is used for the VCO frequency.
When the two counters display the same
frequency, the PLL is locked.)
5. Set the input frequency to the free-running
frequency and note the Gain-Phase Meter
display. It should be approximately
90 o± 1OOnominally. Record the phase error,
the veo control voltage, V o, and the
input frequency, fl.

e.,

February 1987

Figure 5. Measurement Scheme for Kd and Ko Determinations

6. Adjust fl for frequencies above and below
fa' and record
appropriate.

ee and

Vo for each flo as

ee

7. Making a plot of Vo versus
is useful for
checking the measurement data and the
system's linearity. The slope of this plot
(AVO/AOe) is Kd in units of V/o. Multiplying
this slope by 18011, gives the desired Kd in
volts/radian.
8. A plot of fl = fa versus Vo while the loop
remains locked will check the veo linearity. The slope of this plot is Ko at the
particular free-running frequency. The units
of slope taken directly from the graph are
HzlV. Multiplying this slope figure by 21T
gives the desired Ko in units of radians/
volt-sec.
Kd is generally constant over wide frequency
ranges, but is linearily related to the input
signal amplitude. Ko is constant with input
signal level but does vary linearily with fa'.
Often it is convenient to specify a normalized
Ko as
KO rad
Ko (norm) -- fa'
V

(15)

The Ko value at any desired free-running
frequency then can be estimated as
Ko (@ any fa')

= Ko(norm)fO'

(16)

The loop gain for the PLL system is
(17)

4-244

(Often when the gain A is due to an amplifier
internal to the Ie, A will be included in either
Kd or Ko. This is further illustrated in the
article on the 565 PLL.)

MODELING THE PLL SYSTEM
WITH VARIOUS LOW·PASS
FILTERS
The open-loop transfer function for the PLL is
KvF(s)
T(s)=--

s

(18)

Using linear feedback analYSis techniques,
and assuming that the veo is in the forward
path, the closed-loop transfer characteristics
H(s) can be related to the open-loop performance as
T(s)
H(s)=-1 +T(s)

(19)

and the roots of the characteristic system
polynomial can be readily determined by rootlocus techniques.
From these equations, it is apparent that the
transient performance and frequency response of the loop is heavily dependent upon
the choice of filter and its corresponding
transfer characteristic, F(s).

Signetics linear Products

Application Note

AN 178

Modeling the PLL

Zero-Order Filter - F{s) = 1
The simplest case is that of the first-order
loop where F(s) = 1 (no filter). The ciosedloop transfer function then becomes
Kv
T(s)=-S+ Kv

First-Order Filter
With the addition of a single-pole low-pass
filter F(s) of the form
(21)

T,

= R,C" the PLL becomes a secwhere
ond-order system with the root locus shown
in Figure 6b. Again, an open-loop pole is
located at the origin because of the integrating action of the VCO. Another open-loop
pole is positioned on the real axis at -1fT,
where
is the time constant of the low-pass
filter.

T,

One can make the following observations
from the root locus characteristics of Figure
6b:
a. As the loop gain Kv increases for a given
choice of
the imaginary part of the
closed-loop poles increases: thus, the natural frequency of the loop increases and
the loop becomes more and more underdamped.

T"

b. If the filter time constant is increased, the
real part of the closed-loop poles becomes
smaller and the loop damping is reduced.
As in any practical feedback system, excess
shifts or non-dominant poles associated with
the blocks within the PLL can cause the root
loci to bend toward the right half plane as
shown by the dashed line in Figure 6b. This is
likely to happen if either the loop gain or the
filter time constant is too large and may
cause the loop to break into sustained oscillations.

First-Order Lag-Lead Filter
The stability problem can be eliminated by
using a lag-lead type of filter, as indicated in
February 1987

lock range. For the simple first-order lag filter
of Figure 6b, the capture range can be
approximated as

(22)

F(s)

~

JWL = 2y
~ IKv
~

2wc ",2Y ~
(20)

This transfer function gives the root locus as
a function of the total loop gain Kv and the
corresponding frequency response shown in
Figure 6a. The open-loop pole at the origin is
due to the integrating action of the VCO. Note
that the frequency response is actually the
amplitude of the difference frequency component versus modulating frequency when the
PLL is used to track a frequency-modulated
input signal. Since there is no low-pass filter
in this case, sum frequency components are
also present at the phase comparator output
and must be filtered outside of the loop if the
difference frequency component (demodulated FM) is to be measured.

1
F(s)=-1 + T,S

Figure 6c. This type of a filter has the transfer
function

71

where T2 = R2C and T, = R,C. By proper
choice of R2, this type of filter confines the
root locus to the left half-plane and ensures
stability. The lag-lead filter gives a frequency
response dependent on the damping, which
can now be controlled by the proper adjustment of T, and T2. In practice, this type of
filter is important because it allows the loop to
be used with a response between that of the
first- and second-order loops and it provides
an additional control over the loop transient
response. If R2 = 0, the loop behaves as a
second-order loop and as R2 .... 00, the loop
behaves as a first-order loop due to a polezero cancellation. However, as first-order operation is approached, the noise bandwidth
increases and interference rejection decreases since the high frequency error components in the loop are now attenuated to a
lesser degree.

Second- and Higher-Order
Filters
Second- and higher-order filters, as well as
active filters, occasionally are designed and
incorporated within the PLL to achieve a
particular response not possible or easily
obtained with zero- or first-order filters. Adding more poles and more gain to the closedloop transfer function reduces the inherent
stability of the loop. Thus the designer must
exercise extreme care and utilize complex
stability analysis if second-order (and higher)
filters or active filters are to be considered.

CALCULATING LOCK AND
CAPTURE RANGES

(23)
where F(O) is the value of the low-pass filters
transfer function at DC.
Since the capture range wc denotes a transient condition, it is not as readily derived as
the lock range. However, an approximate
expression for the capture range can be
written as (2-sided capture range).

2wc = 4mc",Kvl F(iwc) I

(24)

where F(iwc) is the magnitude of the lowpass filter transfer function evaluated at We.
Solution of Equation 24 frequently involves a
"trial and error" process since the capture
range is a function of itself. Note that at all
times the capture range is smaller than the

4-245

(26)
Equations 23 and 24 show that the capture
range increases as the low-pass filter time
constant is decreased, whereas the lock
range is unaffected by the filter and is determined solely by the loop gain.
Figure 7 shows the typical frequency-to-vOItage transfer characteristics of the PLL. The
input is assumed to be a sine wave whose
frequency is swept slowly over a broad frequency range. The vertical scale is the corresponding loop error voltage. In Figure 7a, the
input frequency is being gradually increased.
The loop does not respond to the signal until
corresponding to
it reaches a frequency
the lower edge of the capture range. Then,
the loop suddenly locks on the input and
causes a negative jump of the loop error
voltage. Next, Vd varies with frequency with a
slope equal to the reciprocal of VCO conversion gain (1fKo) and goes through zero as
WI = wo'. The loop tracks the input until the
input frequency reaches W2, corresponding to
the upper edge of the lock range. The PLL
then loses lock and the error voltage drops to
zero. If the input frequency is swept slowly
back, the cycle repeats itself, but is inverted,
as shown in Figure 7b. The loop recaptures
the signal at W3 and tracks it down to w4. The
total capture and lock ranges of the system
are:

w"

2wc

In terms of the basic gain expression in the
system, the lock range of the PLL wL can be
shown to be numerically equal to the DC loop
gain (2-sided lock range).

(25)

71

This approximation is valid for

= "'3- w ,

(27)

and
(28)
Note that, as indicated by the transfer characteristics of Figure 7, the PLL system has an
inherent selectivity about the free-running
frequency, wo'. It will respond only to the
input Signal frequencies that are separated
from wo' by less than we or wL, depending
on whether the loop starts with or without an
initial lock condition. The linearity of the
frequency-to-voltage conversion characteristics for the PLL is determined solely by the
VCO conversion gain. Therefore, in most PLL
applications, the VCO is required to have a
highly linear voltage-to-frequency transfer
characteristic.

Application Note

Signetics Linear Products

Modeling the PLL

F(o)

AN178

o------- 1.0, and critically damped ~ ~ 1.0. Now
examine this PLL system's response to various types of inputs.

February 1987

Figure 8_ Input Signal Representing a Unit Step of Phase at Constant
Frequency

H(s)

80 (s)

8.(s)

=-

S
E(s)

=-

S

~

wn 2

+ 2~wns + Wn 2)
s + 2~wn
=
S2 + 2~wnS + Wn 2
S(S2

(39)

When

(40)

(depending upon the working units) while
maintaining the same input frequency. Mathematically this input has the form

~ ~

1, these phase responses are
(44)

and
(45)

4-247

',"
.,

Signetics Linear Products

Application Note

Modeling the PLL

AN178

Figure 9 is a plot of the veo phase response
and the phase error transient for various
damping factors. Note from this figure that an
underdamped system has overshoot which
can cause the loop to break lock if this
overshoot is too large. The critical condition
for maintaining lock is to keep the phase error
within the dynamic range for the phase comparator of -rr/2 to rr2 radians. For the underdamped case, the peak phase-error overshoot is
Oe(max) = e - trr/>

v"1=-f2

The time expression for the veo frequency
change for a unit step-of-frequency input is
the same as the time response veo phase
change due to a step-of-phase input (Equation 41), or

tion, it is important that the veo vOltage-tofrequency characteristic be linear so that the
output is not distorted. Over the linear range
of the veo, the conversion gain is given by
Ko (in radian IV-sec)
(56)

wo(t) for frequency step input = Oo(t) for
phase step input Thus
Wo(t)=1 +

(46)

e- tWnt
V
2 sin (wnt~+qr)
1-r
(52)

Since the loop output voltage is the veo
voltage, we can get the loop output voltage
as
(57)

for r * 1.
which must be less than rr/2 to maintain lock.
Lock can also be broken for the overdamped
and critically-damped loops if the input phase
shift is too large where the phase error
exceeds ± rr/2 radians.
The analysis and equations given are based
upon the small-signal model of Figure 4, If the
signal amplitudes become too large, one or
more functional blocks in the system can
saturate, causing a slew rate type limiting
action that may break lock.
The transient change in the veo frequency
due to the unit step-of-phase input can be
found by taking the time derivative of Equation 41 or alternatively by finding the inverse
Laplace transform of

Unit Ramp-of-Frequency Input
This form of input signal represents sweeping
the input frequency at a constant rate and
direction as shown in Figure 11. The amplitude and phase of the input remain constant;
the input frequency changes linearly with
time. Since the input signal to the PLL model
is a phase, a unit ramp-of-frequency appears
as a phase acceleration type input that can
be mathematically described as
1

8;(s)

=;s

(53)

The veo output phase change is

Oo(t)

= i!

2rt
2t [
- 2 2W - wn 2) +
2
wn
wn
2
( 1 - 4t w n 2 + 4r2wn h
1- 2

r

Unit Step-of-Frequency Input

O;(s)

t2

=- - - +

4)

(48)

1

(49)

The veo output phase is

X e - tWnt sin(wnt

Y1="f2 + qr')]
(55)

where qr = arc tan
~

~

W

2 + qr
-2wn )

and qr is given in Equation 42.

PLL BUILDING BLOCKS
VCO

The transient time expression for the veo
phase change is

(51)
February 1987

The input stage formed by transistors 01 and
02 may be viewed as a differential amplifier
which has an equivalent collector resistance
Rc and whose differential gain at balance is
the ratio of Rc to the dynamic emitter resistance, re, of 01 and 02.
Rc
RCIE
0.052

The time expression for the veo phase
change is

This type of input occurs when the input
frequency is instantaneously changed from
one frequency to another as is done in FSK
and modem applications. For this input, as
shown in Figure 10,

Phase Comparator
All of Signetics' analog phase-locked loops
use the same form of phase comparatoroften called the doubly-balanced multiplier or
mixer. Such a circuit is shown in Figure 12.

0.026

Wn 2
Wo(s) = sOo(s) = 2
2 (47)
s + 2twns + wn
which is

The gain Ko can be found from the data
sheet. When the veo voltage is changed, the
frequency change is virtually instantaneous.

Since three different forms of veo have been
used in the Signetics PLL series, the veo
details will not be discussed until the individualloops are described. However, a few general comments about veos are in order.
When the PLL is locked to a signal, the veo
voltage is a function of the frequency of the
input signal. Since the veo control voltage is
the demodulated output during FM demodula-

4-248

(58)

where IE is the total De bias current for the
differential amplifier pair.
The switching stage formed by 03 - 06 is
switched on and off by the veo square wave.
Since the collector current swing of 02 is the
negative of the collector current swing of 01,
the switching action has the effect of multiplying the differential stage output first by + 1
and then by -1. That is, when the base of 04
is positive, RC2 receives 11 and when the base
of 06 is positive, RC2 receives i2 = i1. Since
the circuit is called a multiplier, performing the
multiplication will gain further insight into the
action of the phase comparator.
eonsider an input signal which consists of
two added components: a component at
frequency wI which is close to the freerunning frequency and a component at frequency wk which may be at any frequency.
The input signal is
v;(t) + Vk(t) = Vlsin(w;t + 0;) +
(59)

Signetics Linear Products

Application Note

AN17S

Modeling the PLL

80 (t)

I I

11.8

1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2

L~

1/

rl

L

0.8

I

frequency difference frequency component.
This is the beat frequency component that
feeds around the loop and causes lock-up by
modulating the VCO. As Wo is driven closer
to WI> this difference component becomes
lower and lower in frequency until Wo = WI
and lock is achieved. The first term then
becomes

t 8.(1)

0.6

l-r=0.10
~r=0.25
~r=0.50

I-

'L . / \
~
V r=0.7:\ If
"r=1
I t-'"
I
I

0.4
0.2
-0.2

(62)

-0.4

-0.6
-0.8

I

-1.0
01234.567891Lwn(t)

Figure 9. VCO Phase and Loop Phase Error Transient Responses for Various
Damping Factors

INPUT
VOLTAGE

'il)

'*

11\ /\ /\ IH\ f\ f\
I V V 'v'IVVV~
I "
I " I~

If n 0 in the first term, the loop can lock
when WI = (2n + 1)wo, giving the DC phase
comparator component
2AdVI
Ve(t) = VE =---COSOi
7T(2n + 1)

I

'rrww/f ..

Note also that the phase comparator's output
during lock is (assuming Ad is constant) also
a function of the input amplitude VI. Thus, for
a given DC phase comparator output VE, an
input amplitude decrease must be accompanied by a phase change. Since the loop can
remain locked only for IIi between 0 and 180°,
the lower VI becomes, the more the lock
range is reduced.

Figure 11. Input Signal for a Unit Ramp-of-Frequency Input
where IIi and Ilk are the phase in relation to
the VCO signal. The unity square wave developed in the multiplier by the VCO signal is

[

where wa is the VCO frequency. Multiplying
the two terms, using the appropriate trigonometric relationships, and inserting the differential stage gain Ad gives:

~

V
_ _1 - cos

[(2n + 1) wot - wit - IIi]

n = 0 (2n + 1)

4
~
- - - sin [(2n + 1)wat]
n = 0 7T(2n + 1)
(60)

~

-

~
VI
~
---cos [(2n + 1) wat + wit + IIi]
n=0(2n+1)

~
Vk
+ ~ ---cos [(2n + 1) wat-wkt-IIk]
n=O (2n+ 1)

-

~~ __
V
k_ cos [(2n + 1) (Jot + (Jkt+ Ok! ]
n = 0 (2n + 1)
(61)

Assuming that temporarily Vk is zero, if w1 is
close to wo, the first term (n = 0) has a low
February 1987

4-249

(63)

showing that the loop can lock to odd harmonics of the free-running frequency. The
(2n + 1) term in the denominator shows that
the phase comparator's output is lower for
harmonic lock, which explains why the lock
range decreases as higher and higher odd
harmonics are used to achieve lock.

Figure 10. Input Signal for a Unit Step-of-Frequency at Constant Phase

INPUT

which is the usual phase comparator formula
showing the DC component of the phase
comparator during lock. This component
must equal the voltage necessary to keep the
VCO at wo0 It is possible for Wo to equal WI
momentarily during the lock-up process and,
yet, for the phase to be incorrect so that Wo
passes through WI without lock being
achieved. This explains why lock is usually
not achieved instantaneously, even when
WI = wo at t = O.

Note from the second term that during lock
the lowest possible frequency is
Wo + WI = 2wl. A sum frequency component
is always present at the phase comparator
output. This component is usually greatly
attenuated by the low-pass filter capacitor
connected to the phase comparator output.
However, when rapid tracking is required (as
with high-speed FM detection or FSK), the
requirement for a relatively high frequency
cutoff in the low-pass filter may leave this
component unattenuated to the extent that it
interferes with detection. At the very least,
additional filtering may be required to remove
this component. Components caused by
n 0 in the second term are both attenuated
and of much higher frequency, so they may
be neglected.

'*

I

•

Signetics Linear Products

Application Note

ANU8

Modeling the PLL

amplitude detector. The output of the quadrature-phase detector is given by

+v~

2AqVI
Vq=-rr-sin OJ

(64)

where VI is the constant or modulated AM
Signal and OJ''''90· in most cases so that sine
OJ=l and
(65)
This is the demodulation principle of the
autodyne receiver and the basis for the 567
tone decoder operation.

INITIAL PLL SETUP CHOICES

Figure 12. Integrated Phase Comparator Circuit

Suppose that other frequencies represented
by Vk are present. What is their effect for
Vk*O?
The third term shows that Vk introduces
another difference frequency component. Obviously, if Wk is close to WI, it can interfere
with the locking process since it may form a
bea:t frequency of the same magnitude as the
desired locking beat frequency. However,
suppose lock has been achieved so that
WO = wI· In order for lock to be maintained,
the average phase comparator output must
be constant. If we = wk is relatively low in
frequency, the phase OJ must change to
compensate for this beat frequency. Broadly
speaking, any signal in addition to the signal
to which the loop is locked causes a phase
variation. Usually this is negligible since Wi< is
often far removed from wI. However, it has
been stated that the phase OJ can move only
between 0 and 180·. Suppose the phase limit
has been reached and Vk appears. Since it
cannot be compensated for, it will drive the
loop out of lock. This explains why extraneous signals can result in a decrease in the
lock range. If Vk is assumed to be an instantaneous noise component, the same effect
occurs. When the full swing of the loop is
being utilized, noise will decrease the lock or
tracking range. This effect can be reduced by
decreasing the cutoff frequency of the lowpass filter so that the WO - Wk is attenuated
to a greater extent. which illustrates that
noise immunity and out-band frequency rejection is improved (at the expense of capture
range since WO - WI is likewise attenuated)
when the low-pass filter capacitor is large.

February 1987

The third term can have a DC component
when wk is an odd harmonic of the locked
frequency so that (2n + 1) (we - WI) is zero
and Ok makes its appearance. This will have
an effect on 01 which will change the 01
versus frequency w1. This is most noticeable
when the waveform of the incoming signal is.
for example. a square wave. The Ok term will
combine with the OJ term so that the phase is
a linear function of input frequency. Other
waveforms will give different phase versus
frequency functions. When the input ampli·
tude VI is large and the loop gain is large. the
phase will be close to 90· throughout the
range of veo swing, so this effect is often
unnoticed.
The fourth term is of little consequence
except that if Wk approaches zero. the phase
comparator output will have a component at
the locked frequency WO at the output. For
example. a DC offset at the input differential
stage will appear as a square wave of fundamental WO at the phase comparator output.
This is usually small and well attenuated by
the low-pass filter. Since many out-band signals or noise components may be present,
many Vk terms may be combining to influence
locking and phase during lock. Fortunately.
only those close to the locked frequency
need be considered.

Quadrature-Phase Detector
(QPD)
The quadrature-phase detector action is exactly the same except that its output is
proportional to the sine of the phase angle.
When the phase OJ is 90·. the quadrature·
phase detector output is then at its maximum.
which explains why it makes a useful lock or

4-250

In a given application. maximum PLL effectiveness can be achieved if the designer
understands the tradeoffs which can be
made. Generally speaking. the designer is
free to select the frequency. lock range.
capture range. and input amplitude.

FREE-RUNNING FREQUENCY
SELECTION
Setting the center or free-running frequency
is accomplished by selecting one or two
external components. The center frequency
is usually set in the center of the expected
input /tequency range. Since the loop's ability
to capture is a function of the difference
between the incoming and free-running frequencies. the band edges of the capture
range are a/ways an equal distance (in Hz)
from the center frequency. Typically, the lock
range is also centered about the free-running
frequency. Occasionally. the center frequency is chosen to be offset from the incoming
frequency so that the tracking range is limited
on one side. This permits rejection of an
adjacent higher or lower frequency signal
without paying the penalty for narrow-band
operation (reduced tracking speed).
All of Signetics' loops use a phase comparator in which the input signal is multiplied by a
unity square wave at the veo frequency. The
odd harmonics present in the square wave
permit the loop to lock to input signals at
these odd harmonics. Thus, the center frequency may be set to, say. 1ta or 1'5 of the
input signal. The tracking range, however, will
be considerably reduced as the higher harmonics are utilized.
The foregoing phase comparator discussion
would suggest that the PLL cannot lock to
subharmonics because the phase comparator cannot produce a DC component if WI is
less than WOo

Signetics Linear Products

Application Note

Modeling the Pll

The loop can lock to both odd harmonic and
subharmonic signals in practice because
such signals often contain harmonic components at woo For example, a square wave of
fundamental WQ/3 will have a substantial
component at Wo to which the loop can lock.
Even a pure sine wave input signal can be
used for harmonic locking if the PLL input
stage is overdriven. (The resultant internal
limiting generates harmonic frequencies.)
Locking to even harmonics or subharmonics
is the least satisfactory. since the input or
VCO signal must contain second harmonic
distortion. If locking to even harmonics is
desired, the duty cycle of the input and VCO
signals must be shifted away from the symmetrical to generate substantial, even harmonic, content.
In evaluating the loop for a potential application, it is best to actually compute the magnitude of the expected signal component nearest woo This magnitude can be used to
estimate the capture and lock ranges.
All of Signetics' loops are stabilized against
center frequency drift due to power supply
variations. Both the 565 and the 567 are
temperature-compensated over the entire
military temperature range (-55 to + 125'C).
To benefit from this inherent stability, however, the designer must provide equally stable
(or better) external components. For maximum cost effectiveness in some noncritical
applications, the designer may wish to trade
some stability for lower cost external components.

GUIDELINES FOR LOCK RANGE
CONTROL
Two things limit the lock range. First, any
VCO can swing only so far; it the input signal
frequency goes beyond this limit, lock will be
lost. Second, the voltage developed by the
phase comparator is proportional to the product of both the phase and the amplitude of
the in-band component to which the loop is
locked. If the signal amplitude decreases, the
phase difference between the Signal and the
VCO must increase in order to maintain the
same output voltage and, hence, the same
frequency deviation. The 564 contains an
internal limiter circuit between the signal input
and one input to the phase comparator. This
circuit limits the amplitude of large input
signals such as those from TTL outputs to
approximately 100mV before they are applied
to the phase comparator. The limiter significantly improves the AM rejection of the PLL
for input signal amplitudes greater than
100mV.
This happens so often with low input amplitudes that even the full ± 90' phase range of
the phase comparator cannot generate
February 1987

AN 178

enough voltage to allow tracking wide deviations. When this occurs, the effective lock
range is reduced. Weak input Signals cause a
reduction of tracking capability and greater
phase errors. Conversely, a strong input signal will allow the use of the entire VCO swing
capability and keeps the VCO phase (referred
to the input signal) very close to 90' throughout the range. Note that the lock range does
not depend on the low-pass filter. However, if
a low-pass filter is in the loop, it will have the
effect of limiting the maximum rate at which
tracking can occur. Obviously, the LPF capacitor voltage cannot change instantly, so
lock may be lost when large enough step
changes occur. Between the constant frequency input and the step-change frequency
input is some limiting frequency slew rate at
which lock is just barely maintained. When
tracking at this rate, the phase difference is at
its limit of 0' or 180'. It can be seen that if the
LPF cutoff frequency is low, the loop will be
unable to track as fast as if the LPF cutoff
frequency is higher. Thus, when maximum
tracking rate is needed, the LPF should have
a high cutoff frequency. However, a high
cutoff frequency LPF will attenuate the sum
frequencies to a lesser extent so that the
output contains a significant and often bothersome signal at twice the input frequency.
The phase comparator's output contains both
sum and difference frequencies. During lock,
the difference frequency is zero, but the sum
frequency of twice the locked frequency is
still present. This sum frequency component
can then be filtered out with an external lowpass filter.

INPUT LEVEL AMPLITUDE
SELECTION
Whenever amplitude limiting of the in-band
Signal occurs, whether in the loop input stages or prior to the input, the lock and capture
ranges become independent of signal amplitude.
Better noise and out-band signal immunity is
achieved when the input levels are below the
limiting threshold, since the input stage is in
its linear region and the creation of crossmodulation components is reduced. Higher
input levels will allow somewhat faster operation due to greater phase comparator gain
and will result in a lock range which becomes
constant with amplitude as the phase comparator gain becomes constant. Also, high
input levels will result in a linear phase versus
frequency characteristic.

CAPTURE RANGE CONTROL
There are two main reasons for making the
low-pass filter time constant large. First. a
large time constant provides an increased

4-251

memory effect in the loop so that it remains at
or near the operating frequency during momentary fading or loss of signal. Second, the
large time constant integrates the phase
comparator's output so that increased immunity to noise and out-band Signals is obtained.
Besides the lower tracking rates attendant to
large loop filters, other penalties must be paid
for the benefits gained. The capture range is
reduced and the capture transient becomes
longer. Reduction of capture range occurs
because the loop must utilize the magnitude
of the difference frequency component at the
phase comparator to drive the VCO towards
the input frequency.
If the LPF cutoff frequency is low, the difference component amplitude is reduced and
the loop cannot swing as far. Thus, the
capture range is reduced.

LOCK-UP TIME AND TRACKING
SPEED CONTROL
In tracking applications, lock-up time is normally of little consequence, but occasions do
arise when it is desirable to keep lock-up time
short to minimize data loss when noise or
extraneous signals drive the loop out of lock.
Lock-up time is of great importance in tone
decoder type applications. Tracking speed is
important if the loop is used to demodulate an
FM signal. Although the following discussion
dwells largely on lock-up time, the same
comments apply to tracking speeds.
No simple expression is available which adequately describes the acquisition or lock-up
time. This may be appreciated when we
review the following factors which influence
lock-up time.
a. Input phase
b. Low-pass filter characteristic
c. Loop damping
d. Deviation of input frequency from center
frequency
e. In-band input amplitude
f. Out-band signals and noise
g. Center frequency
Fortunately, it is usually sufficient to know
how to improve the lock-up time and what
must be sacrificed to get faster lock-up.
Consider an operational loop or tone decoder
where occasionally the lock-up transient is
too long. What can be done to improve the
situation - keeping in mind the factors that
influence lock?
a. Initial phase relationship between incoming signal and VCO - This is the greatest
single factor influencing the lock time. If
the initial phase is wrong, it first drives the

•

Signetics Linear Products

Application Note

Modeling the PLL

AN178

f. Out-band signals and noise - Low levels
of extraneous signals and noise have little
effect on the lock-up time, neither improving or degrading it. However, large levels
may overdrive the loop input stage so that
limiting occurs, at which point the in-band
signal starts to be suppressed. The lower
effective input level can cause the lock-up
time to increase, as discussed in e above.

100%

/

80%

II

60%

40%

20%

f-

NOTE:
THE ABSCISSA Will, IN GENERAL.

/

g. Center frequency - Since lock-up time
can be described in terms of the number of
cycles to lock, fastest lock-up is achieved
at higher frequencies. Thus, whenever a
system can be operated at a higher frequency, lock will typically take place faster.
Also. in systems where different frequencies are being detected, the higher frequencies, on the average, will be detected
before the lower frequencies.

BE DIFFERENT FOR EACH LOOP

OPERATING CONDITION.

Ii

0%

10

15

20

2S

35

30

However, because of the wide variation due
to initial phase, the reverse may be true for
any single trial.

INPUT CYCLES

Figure 13. Probability of Lock vs Input Cycles
veo frequency away from the input frequency so that the veo frequency must
walk back on the beat notes. Figure 13
gives a typical distribution of lock-up times
with the input pulse initiated at random
phase. The only way to overcome this
variation is to send phase information all
the time so that a favorable phase relationship is guaranteed at t = O. For example. a
number of PLLs or tone decoders may be
weakly locked to low amplitude harmonics
of a pulse train and the transmitted tone
phase related to the same pulse train.
Usually. however. the incoming phase cannot be controlled.
b. Low-pass filter - The larger the low-pass
filter time constant. the longer will be the
lock-up time. The lock-up time can be
reduced by decreasing the filter time constant. but in dOing so. some of the noise
immunity and out-band signal rejection will
be sacrificed. This is unfortunate. since
this is what necessitated the use of a large
filter in the first place. Also present will be
a sum frequency (twice the veo frequency) component at the low pass filter and
greater phase jitter resulting from out-band
signals and noise. In the case of the tone
decoder (where control of the capture
range is required since it specifies the
device bandwidth) a lower value of lowpass capacitor automatically increases the
bandwidth. Speed is gained only at the
expense of added bandwidth.
c. Loop damping - A simple first-order lowpass filter of the form
1
F(s)=-1 + ST
February 1987

PLL MEASUREMENT
TECHNIQUES

produces a loop damping of
(67)

Damping can be increased not only by
reducing IT, as discussed above, but also
by reducing the loop gain Kv. Using the
loop gain reduction to control bandwidth or
capture and lock ranges achieves better
damping for narrow bandwidth operation.
The penalty for this damping is that more
phase comparator output is required for a
given deviation so that phase errors are
greater and noise immunity is reduced.
Also, more input drive may be required for
a given deviation.
d. Input frequency deviation from free-running frequency - Naturally, the further an
applied input signal is from the free-running frequency of the loop, the longer it will
take the loop to reach that frequency due
to the charging time of the low-pass filter
capacitor. Usually, however, the effect of
this frequency deviation is small compared
to the variation resulting from the initial
phase uncertainty. Where loop damping is
very low, however, it may be predominant.
e. In-band input amplitude - Since input amplitude is one factor in the phase comparator's gain Kd , and since Kd is a factor in the
loop gain Kv damping is also a function of
input amplitude. When the input amplitude
is low, the lock-up time may be limited by
the rate at which the low-pass capacitor
can charge with the reduced phase comparator output (see d above).

(66)

4-252

This section deals with measurements of PLL
operation. The techniques suggested are
meant to help the designer in evaluating the
performance of the PLL during the initial
setup period as well as to point out some
pitfalls that may obscure loop evaluation.
Recognizing that the test equipment may be
limited, techniques are described which require a minimum of standard test items.
The majority of the PLL tests described can
be done with a Signal generator, a scope and
a frequency counter. Most laboratories have
these. A low cost digital voltmeter will facilitate accurate measurement of the veo conversion gain. Where the need for a FM
generator arises, it may be met in most cases
by the veo of a Signetics PLL. Any of the
loops may be set up to operate as a veo by
simply applying the modulating voltage to the
low-pass filter terminal(s). The resulting generator may be checked for linearity by using
the counter to check frequency as a function
of modulating voltage. Since the veos may
be modulated right down to De, the calibration may be done in steps. Moreover, loop
measurements may be made by applying a
constant frequency to the loop input and the
modulating signal to the low-pass filter terminal to simulate the effect of a FM input so that
an FM generator may be omitted for many
measurements.

FREE-RUNNING FREQUENCY
Free-running frequency measurements are
easily made by connecting a frequency counter or oscilloscope to the veo output of the

Signetics Linear Products

Application Note

Modeling the Pll

AN 178

loop. The loop should be connected in its
final configuration with the chosen values of
input, bypass, and low-pass filter capacitors.
No input signal should be present. As the
free-running frequency is read out, it can be
adjusted to the desired value by the adjustment means selected for the particular loop.
It is important not to make the frequency
measurement directly at the timing capacitor,
unless the capacity added by the measurement probe is much less than the timing
capacitor value, since the probe capacity will
then cause a frequency error.

~--------------,

I

I

CeXT
I

I

I
I

lOW-PASS
FIL TER
CAPACITOR

I

~

When the frequency measurement is to be
converted to a DC voltage for production
readout or automated testing, a calibrated
phase-locked loop can be used as a frequency meter.

I
I

________ :~S~~f.K~DJ

•

a. Measurement Setup

'.....
",,'

CAPTURE AND LOCK RANGES
Figure 14a shows a typical measurement
setup for capture and lock range measurements. The signal input from a variable frequency oscillator is swept linearly through the
frequency range of interest and the loop FM
output is displayed on a scope or (at low
frequencies) X-Y recorder. The sweep voltage is applied to the X axis.
Figure 14b shows the type of trace which
results. The lock range is given by the outer
lines on the trace, which are formed as the
incoming frequency sweeps away from the
center frequency. The inner trace, formed as
the frequency sweeps toward the center
frequency, designates the capture range. Linearity of the VCO is revealed by the straightness of the trace portion within the lock
range. The slope (At! AV) is the conversion
gain Ko for the VCO at the particular freerunning frequency.
By using the sweep technique, the effect on
free-running frequency, capture range, and
lock range of the input amplitude, supply
voltage, low-pass filter and temperature can
be examined.
Because of the lock-up time duration and
variation, the sweep frequency must be much
lower than the free-running frequency, especially when the capture range is below 10%
of the free-running frequency. Otherwise, the
apparent capture and lock range will be
functions of sweep frequency. It is best to
start sweeping as slowly as possible and, if
desired, increase the rate until the capture
range begins to show an apparent reduction - indicating that the sweep is too fast.
Typical sweep frequencies are in the range of
1/1000 to 1/100,000 of the free-running
frequency. In the case of the 567, the quadrature detector output may be similarly displayed on the Y axis, as shown in Figure 15,
February 1987

c~~ ~~"'

~~

1 l: V

~

~

V
i-

'v

I.

lOCK tANGE

r--

b. Oscilloscope Display
Figure 14. Capture and Lock Ranges

QU10RAT1e PHAJe OeT~TDR OJTPUT

I 1_WJ

(P'i 1OFj7l

11

t...

\li -U

Ji

.1

PHiEDEICT0J::TI
(PT 20Fj7l

i

I

i

r-

1

Figure 15. Quadrature-Phase Detector and Phase Comparator Outputs of the
NES67 PLL
showing the output level versus frequency for
one value of input amplitude.
Capture and lock range measurements may
also be made by sweeping the generator
manually through the band of interest.

4-253

Sweeping must be done very slowly as the
edges of the capture range are approached
(sweeping toward center frequency) or the
lock-up transient delay will cause an error in
reading the band edge. Frequency should be
read from the generator rather than the loop

Application Note

Signetics Linear Products

AN 178

Modeling the Pll

VCO because the VCO frequency gyrates
wildly around the center frequency just before
and after lock. Lock and unlock can be readily
detected by simultaneously monitoring the
input and VCO signals, the DC voltage at the
low-pass filter, or the AC beat frequency
components at the low-pass filter. The latter
are greatly reduced during lock as opposed to
frequencies just outside of lock.

FM AND AM DEMODULATION
DISTORTION
These measurements are quite straight-forward. The loop is simply set up for FM
detection and the test signal is applied to the
input. A spectrum analyzer or distortion analyzer (HP333A) can be used to measure
distortion at the FM output.
For FM demodulation, the input Signal amplitude must be large enough so that lock is not
lost at the frequency extremes. The data
sheets give the lock (or tracking) range as a
function of input Signal and the optional range
control adjustments. Due to the inherent linearity of the VCOs, it makes little difference
whether the FM carrier is at the free-running
frequency or offset slightly as long as the
tracking range limits are not exceeded.
The faster the FM modulation in relation to
the center frequency, the lower the value of
the capacitor in the low pass filter must be for
satisfactory tracking. As this value decreases,
however, it attenuates the sum frequency
component of the phase comparator output
less. The demodulated Signal will appear to

low-pass filter voltage is then monitored on
an oscilloscope which is synchronized to the
modulating waveform, as shown in Figure 17.
Figure 18 shows typical waveforms displayed.
The loop damping can be estimated by comparing the number and magnitude of the
overshoots with the graph of Figure 19, which
gives the transient phase error due to a step
in input frequency.

have greater distortion unless this component
is filtered out before the distortion is measured.

NATURAL FREQUENCY AND
DAMPING
Circuits and mathematical expressions for the
natural frequencies and dampings are given
in Figure 16 for two first-order low-pass filters.
Because of the integrator action of the PLL in
converting frequency to phase, the order of
the loop always will be one greater than the
order of the LPF. Hence, both these firstorder LPFs produce a second-order PLL
system.

An expression for calculating the damping for
any underdamped second-order system
(~ < 1.0) when the normalized peak overshoot is known is
(68)

The natural frequency (wn) of a loop in its
final circuit configuration can be measured by
applying a frequency-modulated signal of the
desired amplitude to the loop. Figure 16
shows that the natural frequency is a function
of Kd, which is, in turn, a function of input
amplitude. As the modulation frequency (wm)
is increased, the phase relationship between
the modulation and recovered sine wave will
go through 90° at wm = Wn and the output
amplitude will peak.

Examination of Figure 18 shows that the
normalized peak overshoot of the error voltage is approximately 1.4. Using this value for
Mp in Equation 68 gives a damping of
~""0.28.

Another way of estimating damping is to
make use of the frequency response plot
measured for the natural frequency (wn) measurement. For low damping constants, the
frequency response measurement peak will
be a strong function of damping. For high
damping constants, the 3dB down point will
give the damping. Figure 19 tabulates some
approximate relationships.

Damping is a function of Kd, Ko, and the lowpass filter. Since Ko and Kd are functions of
the free-running frequency and input amplitude, respectively, damping is highly dependent on the particular operating condition of
the loop. Damping estimates for the desired
operating condition can be made by applying
an input signal which is frequency-modulated
within the lock range by a square wave. The

NOISE
The effect of input noise on loop operation is
very difficult to predict. Briefly, the input noise

.,

.
T1

CIRCUIT

out

.,

= A,e

72" R:zC

TRANSfER FUNCllON

TRANSFER FUNCTION

,

1 +&'2
f (s) =

F(.)= - 1 +aT1

"',""+-=-.'"',,"-,+"'-",,7",

NATURAl FREOUENCV

NATURAL FREQUENCY

.

,

f= - ( 1 2 + . - )
2

b. Lag-Lead

a. Simple
Figure 16. First-Order Low-Pass Filters
February 1987

KoKer

4-254

Signetics Linear Products

Application Note

AN 178

Modeling the Pll

components near the center frequency are
converted to phase noise. When the phase
noise becomes so great that the ± 90· permissible phase variation is exceeded, the
loop drops out of lock or fails to acquire lock.
The best technique is to actually apply the
anticipated noise amplitude and bandwidth to
the input and then perform the capture and
lock range measurements as well as perform
operating tests with the anticipated input level
and modulation deviations. By including a
small safety factor in the loop design to
compensate for small processing variations,
satisfactory operation can be assured.

REXT

J

CEXT

Figure 17_ Measurement Setup for Display of PLL Transient Response

I

!

INPUT MODULATION

I

I

+

t

:
.):

/I'v

r"
,
T

I

I

~

I

II

1\

V~

ERROR VOLTAGE

I

lol_AI

I

,

:1

~!I

!

I

I

I
t+I
I

III'

II

L+JI

I

!
i

.-n

IN~UT MOIDULATIION

II

I

T

r::: ~Io-"

t

!

I

fo+.:lf

I

.1

I

ER~OR Vci..TAGE i

II

~

I!
11

I

i
I

!

I

,

t

II

Ii

$

I

T

t

"t

INPUT MODULATION

f

I
I

~

I

I

Damped With ~

= 1_0

J

b. Critically

\
c

r- i--

I
ERROR VOLTAGE

/

""

c. Overdamped With

(C 0)

~

= 10

d_ Highly Overdamped With

Figure 18_ Transient Response of PLL Error Voltage to Square Wave Frequency
Modulation for Various Damping Conditions

February 1987

4-255

~

1

I

=CCRIT, RexT =0)

+L

f

-~I

= 0_28

I

(CeXT

(CEXT > CCRIT, R EXT = 0)

a_ Underdamped With

II

1

~

I
I

I

>

10

SigneticsLinear Products

Application Note

Modeling the PLL

AN178

..

-:in' 0.7

~

0.•
0.'

0.'
0

'"

!;

0 .•

0:

0

0:

0.2

~

0.1

ffi

if

0 .•

/- \

~

0.1
-0,2

'-0,3

0.' ' \

~

\

r;... \\\

r;- ~

..........:::

5
I

DAMPING
FACTOR

~

I
::::---

\'\ r-....

2

•

\ I, ~ ,...
\

V-

PEAK AMPLITUDE

w-3dB

LOW FREQUENCY

Wn

AMPLITUDE

I

0.3
0.5
0.7
1.0
5.0

OJ /

'-{-.3

6.0dB
3.2dB
2.2dB
1.3dB
0.5dB

1.8
2.1
2.5
4.3
10

••1

a. Transient Phase Error as an Indication of Damping

b. Ratio of Peak Amplitude to Low Frequency Amplitude of
Error Voltage From Modulating Frequency Response

Figure 19. Estimating the Damping In a Second-Order PLL

February 1987

4-256

NEjSE564

Signetics

Phase-locked loop
Product Specification

Linear Products

DESCRIPTION

FEATURES

The NE564 is a versatile, high guaranteed frequency phase-locked loop designed for operation up to 50MHz. As
shown in the Block Diagram, the NE564
consists of a veo, limiter, phase comparator, and post detection processor.

• Operation with single 5V supply
• TTL-compatible inputs and
outputs
• Guaranteed operation to 50MHz
• External loop gain control
• Reduced carrier feedthrough
• No elaborate filtering needed in
FSK applications
• Can be used as a modulator
• Variable loop gain (externally
controlled)

PIN CONFIGURATION
D, F, N Packages

LOOPGAIH

2

15

HVSTIERE!NS SET

COMPARATOR

3

14

ANAL.OG OUTPUT

CONTROL

tHPUT TO PHASE
"",,"YCO

L.00fI FtLTIER

4

FMO. SET CAP.

LOOfI FILTER

5

FREQ. SET CAP.

FM/RF INPUT

6

BIAS FILTER

7

11

VCOOUTPUT #2

Y.
9

'leo OUTPUT TTL

TOP VIEW

APPLICATIONS
•
•
•
•
•

High-speed modems
FSK receivers and transmitters
Frequency synthesizers
Signal generators
Various satcom/TV systems

ORDERING INFORMATION
DESCRIPTION
16-Pin Plastic SO
16-Pin Plastic DIP
16-Pin Plastic DIP
16-Pin Cerdip

TEMPERATURE RANGE

o to
o to

ORDER CODE

+70'C

NE564D

+70'C

NE564N

-55'C to +125'C

o to

SE564N

+70'C

NE564F

BLOCK DIAGRAM

,- - - - - - - -

,.

-0-------

14------- -,
I

I
I
I
I
I
I
I

~-------~--------------~

November 6, 1986

4-257

853-0908 86384

Signetics linear Products

Product Specification

NEjSE564

Phase-Locked Loop

ABSOLUTE MAXIMUM RATINGS
SYMBOL

V+

PARAMETER

RATING

UNIT

V

Supply voltage
Pin 1
Pin 10

14
6

lOUT

(Sink) Max (Pin 9)

10

mA

PD

Power dissipation

600

mW

TA

Operating ambient temperature
NE
SE

o to +70
-55 to +125

°C

Storage temperature

-65 to +150

°C

TSTG
NOTE:

Operation above 5V will require heatsinking of the case.

DC AND AC ELECTRICAL CHARACTERISTICS

Vee = 5V, TA = 25°C, fa = 5MHz, 12 = 4001/A, unless otherwise specified.

SE564
SYMBOL

PARAMETER

Maximum VCO frequency
Lock range

Capture range

VCO frequency drift with

temperature

veo

free-running frequency

Demodulated output voltage

Distortion
SIN

Signal-to-noise ratio
AM rejection
Demodulated output at
operating voltage

lee

Supply current
Output
"1" output leakage current
"0" output voltage

November 6, 1986

UNIT
Min

Typ

Max

Min

Typ

Max

C1 = 0 (stray)

50

65

45

60

MHz

Input;;' 200mVRMS TA = 25°C
TA=125°C
TA = -55°C
TA - O°C
TA = 70°C

40
20
50

70
30
80

40

70

% of fa

Input;;' 200mVRMS, R2 = 27n.

20

70
40

fo=5MHz, TA=-55°C to +125°C
TA = 0 to +70°C
= 0 to +70°C
fa = 500kHz, TA = - 55°C to + 125°C
TA = 0 to +70°C
C1 = 91pF
Re = lOOn. "Internal"

veo

frequency change with
supply voltage

NE564

TEST CONDITIONS

Vee

= 4.5V

20
1500

300

800

30

% of fo
PPMI"C

600
500
4

to 5.5V

Modulation frequency: 1kHz
fa = 5MHz, input deviation:
2%T = 25°C
l%T = 25°e
l%T=O°C
1%T=-55°C
l%T = 70 0 e
l%T= 125°C

30
500

5

6

3

8

16
8

28
14

6

10

12

16

3.5

16
8

5

6.5

MHz

3

8

% of fa

28
14
13

mVRMS
mVRMS
mVRMS
mVRMS
mVRMS
mVRMS

15

Deviation: 1% to 8%

1

1

%

Std. condition, 1% to 10% dev.

40

40

dB

Std. condition, 30% AM

35

35

dB

12
14

mVRMS
mVRMS

Modulation frequency: 1kHz
fa = 5MHz, input deviation: 1%
Vee = 4.5V
Vee = 5.5V

7
8

12
14

7
8

Vee = 5V 11, 110

45

60

45

60

mA

VOUT = 5V, Pins 16, 9

1
0.3
0.4

20
0.6
0.8

1
0.3
0.4

20
0.6
0.8

p.A
V
V

lOUT = 2mA, Pins 16, 9
lOUT = 6mA, Pins 16, 9

4-258

Signetics Linear Products

Product Specification

Phase-Locked Loop

NE/SE564

TYPICAL PERFORMANCE CHARACTERISTICS
Lock Range vs Signal Input

YCO Capacitor vs Frequency

1000

8

I

I

I PIN~

~

I
>

10'

I
400JiA

I

I

~
~

"IPIN, = O~A-..

E

.!.

"~

10'

:.
"

10'

Z

i'-.

i\.'\

U

~
~

i'-.

10'

w

~

.

i'-.

10'

100

Z

"in

l-

~

10

0,7

0.8

10

J

i\

ie

I

\\ /, /
\\ If( T~'~r
0.9

1.0

1.1

1.2

,

\.

10

102

10'

103

.~

10'

FREQUENCY kHz

1.3

NORMALIZED LOCK RANGE

Typical Normalized YCO
Frequency as a Function of
Pin 2 Bias Current

1.0
~
~

I

~

0.99

Normalized YCO Frequency
as a Function of Temperature

1

J
I

I

veo FREQUENCY: 5MHz

~
11

1.05

8

1.00

Og

r'O
!

FREQUENCY: 50MHz

1

Typical Normalized YCO
Frequency as a Function of
Pin 2 Bias Current

6 1.00

i"-

.....
.....

logs

8

~

1.10

~

1,05

0

....

BIAS CURRENT: - 200j.lA

I

}-

1.00

f

0.95

0.9 7

0.90

0.90

0.98
600I-'A

400
~AS

November 6, 1986

200
CURRENT ().IA), PIN 2

+200

+200
BIAS CURRENT (!J.A), PIN 2

4-259

+400

-\ --

FREQUENCY: SMHz

r-so

~

==-==

f

FREQUENCY: 500 KHz

BIAi CUATNT:
-25

...... -.....

2OO J.l(

25

50

TEMPERATURE (IN °C)

75

100

125

Signetlcs Linear Products

Product Specification

NE/SE564

Phase-Locked Loop

TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Vo • PHASE COMPARATOR'S
OUTPUT VOLTAGE IN mV

SOD

1
I

vco FREQUENCY
!INMHZ

·o=1.0MHz

600

; 1 " " = SOO,A

1.6

.f
400

200

'81As=O!lA

1.4

'0= 1.0MHz

r
40

120

140

-400

160

200

400

600

O· PHASE
ERROR IN
DEGREES

-200

.S

.6

-400

-600

-SOD

Variation of the Phase Comparator's Output Voltage
vs Phase Error and Bias Current (KDl

VCO Output Frequency as a Function of
Input Voltage and Bias Current (Kol

TEST CIRCUIT
+5Vo---~--~--,---,--,

R3

'K

veo
OUTPUT

R,

390

INPUT C3

o--i .---_-16 '
O.lpF

2

'0

1: : .~ "'

R2

November 6, 1986

9

3
DEMODU-

lK

-

r-1 r---<~-t
-=

'6

LATED

'4

O.lPF.:r: OUTPUT

564
'3

C,

'2

430pF

4-260

Signetics Linear Products

Product Specification

NE/SE564

Phase-Locked Loop

FUNCTIONAL DESCRIPTION
(Figure 1)
The NE564 is a monolithic phase-locked loop
with a post detection processor. The use of
Schottky clamped transistors and optimized
device geometries extends the frequency of
operation to greater than 50MHz.
In addition to the classical PLL applications,
the NE564 can be used as a modulator with a
controllable frequency deviation.
The output voltage of the PLL can be written
as shown in the following equation:
(fiN-fa)
Vo=--Kvco

(1)

KvCO = conversion gain of the VCO
fiN = frequency of the input signal
fa = free-running frequency of the VCO
The process of recovering FSK signals involves the conversion of the PLL output into
logic compatible signals. For high data rates,

a considerable amount of carrier will be
present at the output of the PLL due to the
wide band nature of the loop filter. To avoid
the use of complicated filters, a comparator
with hysteresis or Schmitt trigger is required.
With the conversion gain of the VCO fixed,
the output voltage as given by Equation 1
varies according to the frequency deviation of
fiN from fa. Since this differs from system to
system, it is necessary that the hysteresis of
the Schmitt trigger be capable of being
changed, so that it can be optimized for a
particular system. This is accomplished in the
564 by varying the voltage at Pin 15 which
results in a change of the hysteresis of the
Schmitt trigger.
For FSK signals, an important factor to be
considered is the drift in the free-running
frequency of the VCO itself. If this changes
due to temperature, according to Equation 1 it
will lead to a change in the DC levels of the
PLL output, and consequently to errors in the
digital output signal. This is especially true for
narrow-band signals where the deviation in fiN
itself may be less than the change in fa due

EQUIVALENT SCHEMATIC
r-----------------'r-------------------,

I

'

I
I

7

It

I
I

PHASE

II

•

~::
II

II

II
I
I
I

I'
I
I

I
I
I

: .~---i--~~~~~~~==t=~~+J

Figure 1
November 6, 1986

4-261

to temperature. This effect can be eliminated
if the DC or average value of the signal is
retrieved and used as the reference to the
comparator. In this manner, variations in the
DC levels of the PLL output do not affect the
FSK output.

VCO Section
Due to its inherent high-frequency performance, an emitter-coupled oscillator is used
in the VCO. In the circuit, shown in the
equivalent schematic, transistors 021 and
023 with current sources 0 25 - 026 form the
basic oscillator. The approximate free-running
frequency of the oscillator is shown in the
following equation:

fa "" 22 Rc (C 1 + Cs)
Rc = R19 = R20 = 100n (INTERNAL)
C1 = external frequency setting capacitor
Cs = stray capacitance

(2)

•

Signetics Linear Products

Product Specification

Phase-Locked Loop

NEjSE564

Variation of Vo (phase detector output voltage) changes the frequency of the oscillator.
As indicated by Equation 2, the frequency of
the oscillator has a negative temperature
coefficient due to the positive temperature
coefficient of the monolithic resistor. To compensate for this, a current IR with negative
temperature coefficient is introduced to
achieve a low frequency drift with temperature.

LOCK RANGE ADJUSTMENT

lOOP FILTER
O.01J,1F

q.

ANALOG OUT
1kHz

r - -____

BIAS FILTER

POST DETECTION fiLTER

Phase Comparator Section
The phase comparator consists of a doublebalanced modulator with a limiter amplifier to
improve AM rejection. Schottky-clamped vertical PNPs are used to obtain TIL level
inputs. The loop gain can be varied by changing the current in 04 and 015 which effectively changes the gain of the differential amplifiers. This can be accomplished by introducing
a current at Pin 2.

5V

6V

Figure 2. FM Demodulator at 5V
whose output voltage is shown in the following equation:

Post Detection Processor
Section

(3)

The post detection processor consists of a
unity gain transconductance amplifier and
comparator. The amplifier can be used as a
DC retriever for demodulation of FSK signals,
and as a post detection filter for linear FM
demodulation. The comparator has adjustable hysteresis so that phase jitter in the
output signal can be eliminated.
As shown in the equivalent schematic, the DC
retriever is formed by the transductance amplifier 0 4 2 - 0 43 together with an external
capacitor which is connected at the amplifier
output (Pin 14). This forms an integrator

gM
C2

= transconductance of the amplifier
= capacitor at the output (Pin 14)

vided by 047 - 048. The hysteresis is varied
by changing the current in 052 with a resulting
variation in the loop gain of the comparator.
This method of hysteresis control, which is a
DC control, provides symmetriC variation
around the nominal value.

Design Formula
The free-running frequency of the VCO is
shown by the following equation:

VIN = signal voltage at amplifier input
With proper selection of C2, the integrator
time constant can be varied so that the output
voltage is the DC or average value of the
input signal for use in FSK, or as a post
detection filter in linear demodulation.
The comparator with hysteresis is made up of
049 - 050 with positive feedback being pro-

(4)

fa"" 22 Rc (C, + Cs)

= lOon
= external cap in farads
Cs = stray capacitance
Rc

C1

5V

FINE FREQUENCY
ADJUSTMENT

MOOULATING
INPUT

INPUT
O.47jJF
fc:cSMHz ~
fm = 'kHz
BIAS FIL.TER

~

,.'"

O.1JJF

O.47.uF

,.'" o----j

lK

~O.1.uF

7

5V

200

'K

'K
5V

FREQUENCY SET CAP
MODULATED OUTPUT
(TIL!

'2V

Figure 3. FM Demodulator at 12V

November 6, 1986

Figure 4. Modulator

4-262

Signetics Linear Products

Product Specification

Phase-locked loop

NE/SE564

The loop filter diagram shown is explained by
the following equation:
Fs

~

1
- - - (First Order)
1 + SRC3

R ~ R12

~

the frequency deviation in the input signal
should be 1% or higher.

Figure 5 shows a high-frequency FSK decoder designed for input frequency deviations of
± 1.0MHz centered around a free-running frequency of 10.8MHz. The value of the timing
capacitance required was estimated from Figure 8 to be approximately 40pF. A trimmer
capacitor was added to fine tune fo' to
10.8MHz.

Modulation Techniques
The NE564 phase-locked loop can be modulated at either the loop filter ports (Pins 4 and
5) or the input port (Pin 6) as shown in Figure
4. The approximate modulation frequency
can be determined from the frequency conversion gain curve shown in Figure 5. This
curve will be appropriate for signals injected
into Pins 4 and 5 as shown in Figure 4.

(5)

R13 ~ 1.3kn (Internal)*

By adding capacitors to Pins 4 and 5, a pole is
added to the loop transfer function at

The lock range graph indicates that the
± 1.0MHz frequency deviations will be within
the lock range for input signal levels greater
than approximately 50mV with zero Pin 2 bias
current. (While strictly this figure is appropriate only for 5MHz, it can be used as a guide
for lock range estimates at other fo' frequencies).

FSK Demodulation

w~--

RC3
NOTE:
* Refer to Figure 1.

APPLICATIONS
FM Demodulator
The NE564 can be used as an FM demodulator. The connections for operation at 5V and
12V are shown in Figures 2 and 3, respectively. The input signal is AC coupled with the
output signal being extracted at Pin 14. Loop
filtering is provided by the capacitors at Pins 4
and 5 with additional filtering being provided
by the capacitor at Pin 14. Since the conversion gain of the VCO is not very high, to
obtain sufficient demodulated output signal

The 564 PLL is particularly attractive for FSK
demodulation since it contains an internal
voltage comparator and VCO which have TTL
compatible inputs and outputs, and it can
operate from a single 5V power supply. Demodulated DC voltages associated with the
mark and space frequencies are recovered
with a single external capacitor in a DC
retriever without utilizing extensive filtering
networks. An internal comparator, acting as a
Schmit! trigger with an adjustable hysteresis,
shapes the demodulated voltages into compatible TIL output levels. The high-frequency
design of the 564 enables it to demodulate
FSK at high data rates in excess of 1.0M
baud.

The hysteresis was adjusted experimentally
via the 10kn potentiometer and 2kn bias
arrangement to give the waveshape shown in
Figure 7 for 20k, 500k, 2M baud rates with
square wave FSK modulation. Note the magnitude and phase relationships of the phase
comparators' output voltages with respect to
each other and to the FSK output. The highfrequency sum components of the input and
VCO frequency also are visible as noise on
the phase comparator's outputs.

''''

OUTPUT

fl0.FISV

""."

~

, _ L.-_ _ _ _ _ _ _ _ _ _----'

Figure 5_ 10_8MHz FSK Decoder Using the 564

November 6, 1986

4-263

•

Signetics Linear Products

Product Specification

NEjSE564

Phase-Locked Loop

- 2!mv

200mV

t-

50",S

--

~

r-

~

l~

I--

~

~

~

~

r--

r--

I'--

~

~

-2.

- a. Data Rate

-

I""'-

io--

= 20k Baud

b. Data Rate

= SOOk Baud

2.

c. Data Rate

= 2.0m

Baud

NOTES:
1. Top trace"" Pin 4
2. Center trace"" Pin 5
3, Bottom trace = Pin 16

Figure 6. Phase Comparator (Pins 4 and 5) and FSK (Pin 16) Outputs

OUTLINE OF SETUP
PROCEDURE
1.

2.

3.

Determine operating frequency of the
VCO:
If -i- N in feedback loop, then
fa = N X fiN.
Calculate value of the VCO frequency set
capacitor:

1
Co "" 2200 fa
November 6, 1986

4.

5.

Set 12 (current sinking into Pin 2) for ""
1001lA. After operation is obtained, this
value may be adjusted for best dynamic
behavior.
Check VCO output frequency with digital
counter at Pin 9 of device (loop open,
VCO to ¢ de!.). Adjust Co trim or frequency adj. Pins 4 - 5 for exact center frequency, if needed.
Close loop and inject input signal to Pin
6. Monitor Pins 3 and 6 with two-channel

4-264

scope. Lock should occur with
equal to 90· (phase error).
6.

7.

~¢3 _ 6

If pulsed burst or ramp frequency is used
for input signal, special loop filter design
may be required in place of simple single
capacitor filter on Pins 4 and 5. (See PLL
application section).
The input signal to Pin 6 and the VCO
feedback signal to Pin 3 must have a duty
cycle of 50% for proper operation of the
phase detector. Due to the nature of a
balanced mixer if signals are not 50% in

Signetics Linear Products

Product Specification

NEjSE564

Phase-locked loop

duty cycle, DC offsets will occur in the
loop which tend to create an artificial or
biased VCO offset.

8.

For multiplier circuits where phase jitter is
a problem, loop filter capacitors may be
increased to a value of 10 - 50"F on Pins

4, 5. Also, careful supply decoupling may
be necessary. This includes the counter
chain Vce lines.

+5V
BIAS ADJUST

.471'F

r-"10",K,,,"_~-;~
'2
.471,F CER.

1

2K~!

~~~---------.
INPUT SIGNAL

ruo--1
I,

'1;
•.
'I:
,

f= Nxt,

'------i. N

.......- 0 - - - '

Figure 7. NE564 Phase· Locked Frequency Multiplier With VCXO

November 6, 1986

4·265

Signetics

AN179
Circuit Description of the
NE564
Application Note

Linear Products

CIRCUIT DESCRIPTION Of The
NE564

functional with variable supply voltages between 5 and 12V.·

The 564 contains the functional blocks shown
in Figure 1. In addition to the normal PLL
functions of phase comparator, VCO, amplifier and low-pass filter, the 564 has internal
circuitry for an input signal limiter, a OC
retriever, and a Schmitt trigger. The complete
circuit for the 564 is shown in Figure 1.

Signal limiting is accomplished in the 564 with
a differential amplifier whose output voltage is
clipped by diodes 0 1 and 02 (see Figure 2).
Schottky diodes are used because their limiting occurs between 0.3 to OAV instead of the
0.6 to 0.7V for regular IC diodes. This lower
limiting level is helpful in biasing, especially
for 5V operation. When limiting, the OC voltage across R2 R3 remains at the Schottky
diode voltage. Good high-frequency performance for Q2 and Q3 is achieved with current
levels in the low mA range. Current-source
biasing is established via the current mirror of
05 and Q4 (See Figure 1).

Limiter
The input limiter functions to produce a near
constant amplitude output that serves as the
input for the phase comparator. Eliminating.
amplitude variations in the FM input signal
improves the AM rejection of the PLL Additional features of the 564' s limiter are that it is
capable of accepting TTL signals, operates at
high frequencies up to 50 MHz, and remains

Base biasing for Q3 is of concern because of
the nature of the input signal which can be
either a TTL digital signal of 0 to 5V amplitude

Figure 1. Schematic Diagram of NES64
February 1987

4-266

or a low-level, AC coupled analog signal.
Compatibility for either type is achieved by
modifying the limiter of Figure 2 with the
addition of the vertical Schottky PNP transistors Q1 and Q5 as shown in Figure 3. The
input signal voltage appears as a collectorbase voltage for Q1, which presents no problems for either high TTL level inputs or lowlevel analog inputs. Q5 is in turn diode-biased
by 03 and 04 (see Figure 1) which places the
base voltages of Q1 and Q5 at approximately
1.0V. This same biasing network establishes
a 1.3V bias at the base of Q13 for biasing the
phase comparator section. A differential output signal from the input limiter is applied to
one input of the phase comparator (Q9
through Q12) after buffering the level shifting
through the Q7 - Q8 emitter-followers.
*When operating above 5Voc, a limiting resistor must be
used from Vee to Pin 10 of the 564.

Signetics Linear Products

Application Note

Circuit Description of the NE564

AN179

+Vcc

+Vcc

A.

900
A,

,""

AS

0,

Figure 2. Basic Limiter Stage

A2

·3

2K

2K

,""

Figure 3. Limiter Stage With Input Buffering

Phase Comparator
The phase comparator section of the 564 is
shown in Figure 4. It is basically the conven·
tional, double-balanced mixer commonly
used in PLL circuits, with a few exceptions.
The transconductance, gM, for the 01S - 014
differential amplifier is directly proportional to
the mirror current in 015' Thus, by externally
sinking or sourcing current at Pin 2, gM can be
changed to alter the phase comparator's
conversion gain, Kd. The nominal current
injected into this node by the internal current
source is O.75mA for 5V operation. If the
current is externally removed by gating, the
phase comparator can be disabled and the
veo will operate at its free-running frequency.

A.

,""

A"
,.,.

,.,.

A13

FA""
VCO

Figure 4. Phase Comparator Section

February 1987

4-267

•

Signetics Linear Products

Application Note

AN179

Circuit Description of the NE564

VD • PKAse COW'ARATOR'S
OUTPUT vOt. TAGf .. mY

...
to '"

1.0 MHz

...

-200

-400

-eoo

Figure 5. Variation of the Phase Comparator's Output Voltage vs Phase Error and Bias Current

February 1987

4-268

Signetics Linear Products

Application Note

Circuit Description of the NE564

AN179

The variation of Kd with bias current at Pin 2
is shown in the experimental results of Figure
5. Note that the inherent 90' phase error in
the loop produces an approximate zero·
phase comparator output voltage. For any
particular bias current, the slope of the line is
the Kd conversion gain for the phase compar·
ator. Numerically the data of Figure 5 can be
expressed as

."

'"
.,.;t----~------------~

'"

...

'"

VoltS)
Kd",,0.46 ( rad

'"

'"

'"

'"

volts )
X ISlAS (IlA)
rad X !lA

+ 7.3 X 10- 4( - - - - -

I" -I

--'"

.,.

.,

"',

'"

'"

-I

...

(1 )

.

""

Figure 6. VCO Section of NE564

Equation 1 is valid for bias current less than
800!lA where saturation occurs within the
phase comparator.
The current level established in 015 of Figure
3 determines all other quiescent currents in
the phase comparator (09 through 014)' Cur·
rents through R12 and R13 set the common·
mode output voltage from the phase compar·
ator (Pins 4 and 5). Since this common·mode
voltage is applied to the VCO to establish its
quiescent currents, the VCO conversion gain
(Ko) also depends upon the bias current at
Pin 2.

veo
The VCO is of the basic emitter·coupled
astable type with several modifications includ·
ed to achieve the high frequency, TTL com·
patible operation while maintaining low fre·
quency drift with temperature changes. The
basic oscillator in Figure 6 consists of 019,
020, 0210 and 023 with current sinks of 025
and 026. The master current sink of 028
keeps the total current constant by altering
the ratio of currents in 025 - 026 and the
dummy current sink of 027'
The input drive voltage for the VCO is made
up of common·mode and difference·mode
components from the phase comparator. Af·
ter buffering the level shifting through
0 17 -018 and R15-R16, the VCO control
voltage is applied differentially to the base of
0 27 and to the common bases of 025 and
026·
The VCO control voltages from the phase
comparator are the Pin 4 and Pin 5 voltages
or

Figure 7. VCO Waveshapes

(2)

V5

= VC12 = VS17 = VCM

- Y2VOM

(3)

where VCM and VOM are the respective com·
mon·mode and difference· mode voltages.
February 1987

4-269

•

~.

;,'.

i

Signetics Linear Products

Application Note

Circuit Description of the NE564

Emitter-followers 017 and 018 convert these
control voltages into control currents through
06 and 0 7 of the form
16 =

~
[VCM R15

V2VDM -

3 VBE]

9R (VCM -

(10)
where 0';;; x ,;;; 1. Thus

x is defined to be

(4)

These individual currents are summed in 08
and become with R15 = R16 = R.
18 = I = 16 + 17 =

AN179

(11)
Currents 16 and 17 establish proportional currents in 025, 026, and 027 in a manner similar
to the analysis above since the current in 028
is a constant, or
10 = IC28 = IE25 + IE26 + E27A + IE27B

3 VBE)

(6)

Writing 16 and 17 as functions of the total I
current gives
(7)
(8)

Now consider variations in 16 and 17 while I
remains constant.
Let 'x' indicate the current imbalance such
that

It can be shown that the 07 - 08 diode pair
will cause identical differential currents to be
reflected in both the 025 - 026 and the
027 A - 027B differential amplifier pairs. Consequently, the constant-current of 10, jointly
shared by the differential amplifier pairs, will
divide in each pair with the same x factor
imbalance as in Equation 11.
IE25 + IE26 = xlo

(12)

210

(13)

x

IE25 = IE26 =

IE27A + IE27B = (1 - x)lo
1 -x
IE27A = IE27B = (-2-)10

(14)
(15)

Now consider plaCing a capacitor between
the collectors of 025 and 026 (Pins 12 and
13). Oscillation will occur with the capacitor
alternately being charged by 021 and 023 and
constantly discharged by 025 and 0 26 , When
the 021 and 022 pair conducts, 023 and 024
will be off, causing a negative ramp voltage to
appear at Pin 13 and a constant voltage at
Pin 12 as shown in Figure 7. During the nex1
half-cycle, the transistor roles and voltages
are reversed. Capacitor discharge is via 025
and 026, which act as constant-current sinks
with current amplitudes as in Equation 13.
During each half-cycle, the capacitor voltage
changes linearly by 2!!,v volts in LH seconds
where
(16)

and
C2t:,v
Ll.T=--.
IE25

Combining these two equations with Equation
13 gives a half period of
4C R20
Ll.T=--

x

(9)

(17)

(18)

Utilizing Equation 11 with the Ll.T expression
gives the desired VCO frequency expression
of

veo FREQUENCV
"Utu

VDM
VDM
fa = fo'(1 + ) = fa' [
RI
2(VCM - 3 VBE)

]

(19)
where fa' is the VCO's free-running frequency
given by
1
fo'=--22 R20 C

800
Vo IN rnV

..

(20)

Equation 19 shows that the oscillator frequency is a linear function of the differential
voltage from the phase comparator. Resistors
R35 and R36 function to insure that an initial
current imbalance exists between the
0 25 - 026 transistor pair and the dummy 027.
This imbalance insures that the oscillator is
self-starting when power is first applied to the
circuit.
The VCO conversion gain is determined as
(21)

Figure 8. VCO Output as a Function of Input Voltage and Bias Current
February 1987

4-270

which is valid as long as the transistor's VBE
changes are small with respect to the common-mode voltage. Both fa and Ko are in-

Signetics Linear Products

Application Note

Circuit Description of the NE564

AN179

:>---0 FSK OUT

IN

I
I
I

I
I
I
I

HYSTERESlS
ADJUST

L.
.JI
I ___________
DC RETRIEVER

Figure 9. Post Detection Processor for FSK
versely proportional to R, which has a strong
positive temperature coefficient. An internal
current IR having an equal and opposite
negative temperature coefficient is inserted
into the VCO as shown in Figure 6.
Experimental determination of Ko can be
found from the data of Figure 8 where Ko is
the slope of either line. Numerically these
results are for ISlAS = O.
Ko

MHz

rad

= 0.95-- = 5.9

X 106- - -

V

and for ISlAS = 8001lA
MHz
rad
Ko = 1.7-- = 10.45 X 106- - V
volt·sec
(23)

It must be noted that the specific values
obtained for Ko in the manner above are valid
only for the 1.0MHz free-running frequency
where the data was taken. However, good
estimates for Ko at other free-running frequencies can be obtained by linearly scaling
Ko to the desired fa'. Thus, it is sometimes
convenient to define a normalized Ko as
Ko

= t;;; = 5.9

= 10.45

rad

rad

V (ISlAS = 0)

V (lSIAS =

February 1987

800I1A)

Ko(any fa')

= Ko(norm)fO'·

(25)

The additional VCO circuitry of 029 through
036 functions to produce the TTL and ECl
compatible outputs at Pins 9 and 11.

Amplifier

volt·sec

(22)

Ko(norm)

The Ko estimate for any bias then can be
obtained by multiplying the normalized conversion gain by the desired free-running frequency, or

(24)

The difference-mode voltage from the phase
comparator is extracted and amplified by the
amplifier in Figure 1. The single-ended output
from this amplifier serves as input signals for
both the Schmitt Trigger and a second differential amplifier. low-pass filtering with a large
capacitance at Pin 14 produces a stable DC
reference level as the second input to the
Schmitt Trigger. When the Pll is locked, the
voltage at Pin 14 is directly proportional to the
difference between the input frequency and
fa'. Thus Pin 14 provides the demodulated
output for an FM input signal.

Schmitt Trigger
In FSK applications, the Pin 14 voltage will
assume two different voltage levels corresponding to the mark and space input frequencies. A voltage comparator could be
used to sense and convert these two voltage
levels to logic compatible levels. However, at
high data rates, VDM will contain a consider-

4-271

able amount of carrier signal which can be
removed by extensive filtering. Normally this
complex filtering requires quite a few components, most all of which are external to the
monolithic PlL. Also, since the control voltage for the comparator depends upon Ko and
the deviations of the mark and space frequencies from fa', the filtering has to be
optimized for each different system utilized.
However the necessary DC reference level
for the comparator is present in the Pll but
buried in carrier-frequency feedthrough which
appears as noise in the system. A Schmitt
trigger with variable hysteresis can be used
successfully to decode the FSK data without
the need for extensive filtering.
Consider the system shown in Figure 9 where
the input signal is the single-ended output
derived from the amplifier section of the 564.
The DC retriever functions to establish a DC
reference voltage for the Schmitt trigger. The
upper and lower trigger points are adjustable
externally around the reference voltage giving
the variable hysteresis. For very low data
rates, carrier feedthrough will be negligible
and the ideal situation depicted in Figure 10
results. Increased data rate produces the
carrier feedthrough shown in Figure 10b,
where false FSK outputs result because the
feedthrough amplitude exceeds the hysteresis voltage. Having the capability to increase
the hysteresis, as in Figure 10c, produces the
desired FSK output in the presence of carrier
feedthrough.
Another important factor to be considered is
the temperature drift of the fa' in the VCO.
Small changes in fa' will change the DC level
of the input voltage to the Schmitt trigger.
This DC voltage shift would produce errors in
the FSK output in narrow-band systems
where the mark and space deviations in fiN
are less than the fa' change with temperature. However, this effect can be eliminated if
the DC or average value of the amplifier
signal is retrieved and used as the reference
voltage for the Schmitt trigger. In this manner,
variations in the fa' with temperature do not
affect the FSK output.

II

Signetics Linear Products

Application Note

Circuit Description of the NE564

AN179

IN

~

__~r--l~____ __
TIME

a. Low Data Rates With Negligible Carrier Feedthrough

UTP

IN

l

VH

LTP
vOC(Ol

F"

OUT

1

TIIM!

b. False FSK Outputs Due to Feedthrough and Low Hysteresis

IN

FSK
OUT

TIME

c. Increased Hysteresis Restores Proper FSK Output
in the Presence of Feedthrough
Figure 10. Waveshapes for FSK Decoding in the Post Detection Processor

February 1987

4-272

Signetics

AN180
Frequency Synthesis With the
NE564
Application Note

Linear Products

FREQUENCY SYNTHESIS WITH
THE NE564
Frequency multiplication can be achieved
with the PLL in two ways:
a. Locking to a harmonic of the input signal.
b. Insertion of a counter (digital frequency
divider) in the loop.
Harmonic locking is simpler and usually can
be achieved by setting the VCO free-running
frequency to a multiple of the input frequency
and allowing the PLL to lock. However, a
limitation of this scheme is that the lock range
decreases as successively higher and weaker
harmonics are used for locking. This limits the
practical harmonic locking range to multiples
of approximately less than ten. For larger
multiples, the second scheme is more desirable.
A block diagram of the second scheme is
shown in Figure 1a. Here, the loop is broken
between the VCO and the phase comparator
and a counter is inserted. In this case, the
fundamental of the divided VCO frequency is
locked to the input reference frequency so
that the VCO is actually running at a multiple
of the reference frequency. The amount of
multiplication is determined by the counter.
An obvious practical application of this multiplication property is the use of the PLL in wide
range frequency synthesizers.
In frequency multiplication applications, it is
important to take into account that the phase
comparator is actually a mixer and that its
output contains sum and difference frequency
components. The difference frequency is DC
and is the error voltage which drives the VCO

= fc
= fOIN

'0

= NFIH

Producing a large number of frequencies with
close spacing requires a counter with a large
N for the system of Figure 1a. Large N values,
in turn, require reference frequencies too low
to be practical for commercially available
crystals. To overcome this difficulty, a second
counter (7M) is inserted as a prescaler as in
Figure 1b to divide down the reference frequency input. This also gives more programming flexibility, since the synthesized output
frequencies are functions of both M and N
integers, each of which can be changed
separately. As an example of fractional frequency synthesis, the two counters can be
set to generate an output frequency exactly
16/3 of the input reference frequency. In this
case N = 16, M = 3, and the initial fo' is set to
approximately 16/3 times the reference frequency input. The output always will be exactly 16/3 of the input frequency as long as the
PLL remains in lock.
PLL frequency synthesizers based upon Figure 1b find wide applications in many types of

communications systems that require precisely spaced channels having narrow bandwidths which are centered around relatively
high frequencies. For example, Citizens Band
(CB) transceiver applications require forty
channels corresponding to forty different reference frequencies, each separated by
10kHz bandwidths and centered in the
26 - 27MHz range. Channel 4 uses
27.005MHz; Channel 5 uses 27.015MHz;
Channel 6 uses 27.025MHz; and so on.
These frequencies could be produced by
using forty different crystals - one for each
channel. However, this becomes expensive
and adds unnecessary complexity to the
system. Frequency-mixing techniques have
been employed to reduce the number of
crystals needed to less than one crystal per
channel. For example, one common mixer
design uses 14 crystals for 23 channels. As a
general rule, most practical approaches that
use numerous crystals and mixers to produce
discrete frequencies require more than one
crystal for every two channel frequencies
produced. As the number of channels grows
large, frequency synthesis using PLLs becomes more attractive, especially since usually only one or two crystals are needed.
Frequency stability of all channels will be
essentially the same as that of the crystal
reference frequency. Reduced system complexity, size, weight, and power consumption
are key advantages of PLL synthesizers.
Since the function of frequency synthesizers
is to generate frequencies and not to linearly
decode or demodulate input signals, digital
PLLs are more commonly used than analog
loops.

fO = NflN

IN LOCK
fiN
'IN

to keep the PLL in lock. The sum frequency
components (of which the fundamental is
twice the frequency of the input signal), if not
well filtered, will induce incidental FM on the
VCO output. This occurs because the VCO is
running at many times the frequency of the
input signal and the sum frequency component which appears on the control voltage to
the VCO causes a periodic variation of its
frequency about the desired multiple. For
frequency multiplication, it is generally necessary to filter quite heavily to remove this sum
frequency component. The tradeoff, of
course, is a reduced capture range and a
more under-damped loop transient response.

a. Frequency Multiplication

b. Fractional-Frequency SyntheSis
Figure 1. Frequency SyntheSiS Using PLLs

February 1987

4-273

Signetics Linear Products

Application Note

AN180

Frequency Synthesis With the NE564

50'
OE'

osc

o

,,r------------------------------',,
~-'-~--~'~,
,,i
,,
I

,

I
IL _________________
564 PLL
I
~

Nt~

""',

2

2V

, ,-,-- - -.....- -- 1\.

II

I

1

J

f n n n,
II I I I I I I I I I I \ I \...I IwI
III
i-

rtf
i-

Ir"

I

If

2V

a. Block Diagram Organization

b. Waveshapes

Figure 2. Fractional Frequency Synthesis With the 564

February 1987

~ I""""

4-274

~ I-"

Signetics Linear Products

Application Note

Frequency Synthesis With the NE564

•

AN180

to

0.1""

r.
1

.IV

-: lK

N.....

...
...

"r-"T----,

.. .-......

..

•

2.1

---'

"'...

..

co••" ..

'.,-3.• MHz

It

t.I.411Ht

,.21 •• MH.z

•

O.l~

to

..

'00

E
-=-

lK

to

He'"

.
........
'.S.IMHI:

...."

~

...."

.IV

L.._ _ _ _ _ _ _ _ _....I

c. Circuit Implementation
Figure 2. Fractional Frequency Synthesis With the 564 (Continued)

February 1987

4-275

Signetics Linear Products

Application Note

Frequency Synthesis With the NE564

Analog PLLs also can be used for frequency
synthesis applications. The 564 is particularly
well suited for these applications because the
loop is open between the VCO output and the
phase comparator input. Also, the phase
comparator input and VCO output are compatible with TTL counters.

NE564 FREQUENCY SYNTHESIS
WITH CRYSTAL CONTROL
The system shown in Figure 2 has been used
to generate frequencies of 5.4M Hz and
21.6MHz from a 3.6MHz crystal-controlled
source. This reference Signal input is produced by using the crystal as the frequencydetermining element in the VCO of a second
PLL. The thermal stability 01 all three frequen-

February 19B7

cies will be the same as the stability afforded
by the crystal. It may be necessary to place a
small detuning capaCitor in parallel with the
crystal to precisely tune the PLL to the
crystal's resonant frequency and to prevent
oscillations at harmonics of the resonant
frequency. The value of this tuning capacitance must always be kept considerably less
than the value required to produce an fa'
without the crystal present. Otherwise the
crystal will lose control and the input reference frequency will be set by the capacitor
alone.
A recommendation for improved 564 operation is to utilize a divide-by-N counter in the
loop which produces" square" waves for the
phase comparator that have as close to a

4-276

AN180

50% duty cycle as possible. Normally, counters with even N values produce square wave
outputs perfectly compatible for the phase
comparator. Counters for odd N values more
commonly produce unsymmetrical outputs
that can be less desirable inputs to the phase
comparator. An easy modification to "square
up" odd divide-by-N counter outputs is to
insert a single toggling flip-flop stage between
the counter output and the phase comparator's input. This produces an effective 2N
multiplication of the input frequency within the
PLL. The extra factor of two is removed by a
second toggle flip-flop whose input is the
output from the first flip-flop. This is the same
system as was previously shown in Figure 2a
where the + N counter becomes a + 2N and
M = 2 for the second counter.

AN1801

Signetics

10.8MHz FSK Decoder With
NE564
Application Note
Linear Products

FSK DEMODULATION WITH
THE 564
The 564 PLL is particularly attractive for FSK
demodulation since it contains an internal
voltage comparator and VCO which have TTL
compatible inputs and outputs, and it can
operate from a single 5V power supply. Demodulated DC voltages associated with the
mark and space frequencies are recovered
with a single external capacitor in a DC
retriever without utilizing extensive filtering
networks. An internal comparator, acting as a
Schmitt trigger with an adjustable hysteresis,
shapes the demodulated voltages into compatible TTL output levels. The high frequency
design of the 564 enables it to demodulate
FSK at high data rates in excess of 1.0M
baud.
Figure 1 shows a high-frequency FSK decoder designed for input frequency deviations of
± 1.0MHz centered around a free-running frequenc,. of 10.8MHz. The value of the timing
capacitance required was estimated from Figure 4a to be approximately 40pF. A trimmer
capacitor was added to fine tune fa' to
10.8MHz.
Figure 2b indicates that the ± 1.0MHz frequency deviations will be within the lock
range for input signal levels greater than
approximately 50mV with zero Pin 2 bias
current. While strictly this figure is appropriate
only for 5MHz, it can be used as a guide for
lock range estimates at other fa' frequencies.
A more thorough analysis confirms these lock
range conclusions and serves as a guide for
designing other systems. The closed-loop
gain of the PLL is equal to the system's lock
range and is found as the product of Kd and
Ko adjusted to 10.8MHz
(1)

Thus Pin 2 could be left as an open circuit
and the internally set closed-loop gain would
be adequate for tracking the mark and space
input frequencies. However, to be safe, a bias
adjustment as shown in Figure 1 is recommended to allow for Kd and Ko variations from
device to device.
Designing for a capture range of approximately 700kHz gives a low-pass filter time
constant of

Wc""~
T

2WL = Kv = 2.73 X 107

(21T X 700 X 103) ""

V

1.18ms

Therefore, choose the low-pass filter capacitor as
T

1.41/ls

C =- =--""lnF
R
1.3k

(3)

Two 1nF capacitors were selected for the
design.
Capacitive coupling was used for the FSK
input and is recommended to avoid DC feedthrough. This DC voltage would act as a DC
offset to shift fa' from 10.8MHz. Balanced
biasing with the 1.0kn resistors from Pin 7 to
Pins 3 and 6 also is recommended to establish symmetrical, quiescent current conditions
in the limiter and phase comparator sections
of the 564. The 470n pull-up resistor for the
VCO output was found to give a rise time less
than IOns. This rise time was further reduced
by adding the lOOn resistor between Pins 9
and 11. Figure 3 shows an unmodulated
10.8MHz input signal and the VCO output.
Note the approximate 90° phase lag of the
VCO output.

X (21T X 10.8 X 106 ~dian)
sec

February 1987

2.73 X 107
T

T=

volt
MHz
2WL = (0.46 - .-) (0.875-)
radian
volt

2WL = 2.73 X 107 radian
sec

(2)

(Lock range total)

4-277

A O.I/lF DC retriever capacitor (Pin 14) has
less than 1n impedance at fa, and represents a good compromise between high baud
rates (-100k baud) at fa' and higher-order
filtering. If very high baud rates are used, this
capacitor could be made smaller with an
accompanying increase in the Schmitt trigger
hysteresis voltage. The hysteresis was adjusted experimentally via the 10kn potentiometer and 2kn bias arrangement to give the
waveshape shown in Figure 5 for 20k, 500k,
and 2M baud rates with square wave FSK
modulation. Note the magnitude and phase
relationships of the phase comparator's output voltages with respect to each other and to
the FSK output. The high frequency sum
components of the input and VCO frequency
also are visible as noise on the phase comparator's outputs.
The phase comparator's outputs exhibit the
waveshapes shown in Figure 4 when the FM
input is changed from a square wave FSK
modulation to a triangular sweep at a 100Hz
modulation rate. The amplitude of the triangular sweep was increased from that used with
square wave modulation, causing the loop to
be driven in and out of lock. The loop is
locked during the smooth, linear portions of
the phase comparator's waveshapes and
locked during the remaining portions. Lock
and capture frequencies were measured for a
Pin 2 bias current of 375/lA and
fa' = 10.8MHz as:
Lock: fL1 = 6.2MH z fL2=18.4MH z
Capture: fCl = 9.3MH z fC2=12.2MH z ·P
When the loop is locked, the phase detector's outputs represent the demodulated FM
output. When unlocked, high frequency harmonics are present, increasing in amplitude
until lock is achieved.

Application Note

Signetics Linear Products

10.8MHz FSK Decoder With NE564

~

O.l,.F

,

AN1801

..""
10

"

OUTPUT

,.
,.

'*'

I NESe41

--

••v

"

~

...

UK

lOI'F

"
.".

Figure 1. 10.8MHz FSK Decoder Using the NE564

1000

4-r ~7'
10'
10'

u.
Q.
w 10'

"i!z

ic

"

~

r-

I

I

r

f--

I
I
~' .... =o,""
I

~

l'-.

10'

I

~

'\.

102

1\,

10

10

102

103

104

I

\ I I IOj5Mj
Vcc=5V

i\ \

10

10 5

0.7

FREQUENCY kH.

If

0.8 0.9 1.0

1.1

1.2

1.3

NQRMAUZEO LOCK RANGE

a. VCP Timing Capacitor vs Frequency

b. Lock Range vs Input Signal Level and Bias Current

Figure 2. NE564 Characteristics

February 1987

I

' ..... =400,.A

4-278

Application Note

Signetics Linear Products

AN1801

10.8MHz FSK Decoder With NE564

:

.

?.:;r~

"'-I

"-,

"-,

"'-I

.

INPUT

-'

---.I

-./

~

~

~

VCO

'""--'

'""--'

........I

---.I

PIN 4
-

"'""'
PINS

---.I

?v

Figure 3. PLL Input and VCO Output for Phase and
Frequency Lock at 10.8MHz

==

_J..,

- .... -

Figure 4. Phase Comparator Outputs Showing Lock and
Capture Ranges

,
"
"
.. "- - - ... '" "
(b) 5001( BAUD

r-

~

,..

;:: ;::

,...

~

""-

""-

"'-

io--

io--

....-.

,...~

~ ./

,...~ ~ ~

....-.

i.--

"

'.S

~ .I ~

/ ~

~~
""-

l00J,

100m!

~

"

,
,., ,.

- -

-

~

~

I--

(e) 2.OM BAUD

,oJ . . .
",

\~

1-

100m'"

~~ i"- V'

"."- ~ 1'1
,..-

1-

""'oS

',/, 1'.... 1.1,., ".

~ ',t"

- -

"
NOTE,
Top trace-Pin 4
Center trace - Pin 5
BoHom trace - Pin 16

Figure 5. Phase Comparator (Pins 4 and 5) and FSK (Pin 16) Outputs for Various Data Rates

February 1987

4-279

AN181

Signetics

A 6MHz FSK Converter Design
Example for the NE564
Application Note

Linear Products

Design Example
It is desired to design an FSK converter
operating at 6MHz with deviation of ± 1%.
Supply voltage is 5V. Input to the 564 is from
a radio receiver with an amplitude of
0.5VRMS. Worst case SIN is ladS. An overall
loop damping factor of 0.5 is specified

•.SV

.

:::-t-.,....-t-..,...-...,..--..,...-t--,

O:::...

...

*0.,.,

0U11'UI'

m.

Using the circuit in Figure 1
First the frequency determining capacitor
must be established. Using the equation

.

1

~'''F

fo=--22RcCo
where Rc is the internal resistance in the
VCO oscillator equal to lOOn. Given two
parameters the third is calculated fo = 6MHz;
therefore

1
Co= 22 X 100 X 6 X 106

75pF.

A parallel 2 - 20pF trimmer and a 68pF ± 5%
fixed mica capacitor is chosen.
Next, signal level versus bias current and lock
range is examined.

1000

I

-

.1

-

T I

-

~

t-

I~

I

Z

!2

It's now possible to determine the damping
factor of the closed-loop. First, the natural
frequency of the loop is calculated from the
relationship

= 7.2 X 106 radians
sec 'volt

(1)

i

~

J

0.7

0 .•

KD = Phase detector conversion gain

I/
'\ \ If 'YOMi'

1\
0.1

1.1

1.2

T

= loop filter time constant in seconds.

1.3

NORMALIZED LOCK RANGE

Figure 2. Lock Range vs Signal Input
The signal input to the 564 is specified to be
0.5VRMS; in the lock range graph, the input
level is well within the limiting region of the
564. Thus, no external AM limiter circuit is
required and a 10dS SIN (3.1:1) min. should
provide reliable communication with a narrow
deviation of ± 1% (± 60kHz) and there is no
February 1987

18 = 2001lA·
The value obtained for Ko is for data taken at
1MHz and must be multiplied by 6 in order to
find the correct value.
radians
Therefore, Ko=6 X 7.2 X 10 6 - - sec 'yolt

volts
in-radian

Vee" 6Y

1,0

Next, using the KD graph (Figure 3b), ± 1
radian (_90' ± 57'); I.e., Afl = 1 radian, results
in an output of 0.6V Irad.

where
radians
Ko = VCO conversion gain in - - sec'volt

!

1045 X 106rad/sec
Ko=-----0.2V

0.6
Therefore, KD = rad = 0.6 VIrad at

'pIN,"O.uA

I

I.

Multiplying Afo by 211 results in

-

;/ 100

..

problem with adequate lock range as it pertains te> bias current. We are free to use any
loop gain necessary. The bias current sinking
into Pin 2 is set to an initial value of 20011A.

I

IPtN:=4OOpA

>

e
J

I

Figure 1. FSK Decoder Using the 564

For fo = 6MHz and 18 = 2001lA, Ko may be
derived from Figure 3a by first constructing an
extrapolated transfer line with slope onequarter of the angle between the existing
Is = 0 and Is = 800 plots.
Interpolation gives
(1048 - 1.25MHz)
Ko ~ ' - - - - - - ' (OA-0.2V)

4-280

(6MH z) = 4.34 X 107 radians
sec'volt
KoKD=Kv = (4.34 X 10 7)(0.6) = 2.6 X 10 7
The damping factor specified (0.5) is now
used to determine the necessary filter time
constant (Pins 4, 5).
1
1
wn
t=2r
=--=(2)
~ 2VKVT 2Ky
r 1
:.r= (4)(2.6 X 10 7)(0.5)2 38ns

Signetlcs Linear Products

Application Note

A 6MHz FSK Converter Design Example for the NE564

AN181

Note that the filters on Pins 4 and 5 operate
differentially with the net effect that break
frequency is
wp

1

= RC (single pole filter - 3dB freg.)

Now solving for wn using (1);

w,,= [

(2.6 X 107)
(3.8 X 10- 8)

]h

6

=26 X 10 radians/
sec

fn = 4.16MHz (natural frequency of the loop
and approximate one-sided capture
BW.)
The value of the loop filter capacitor may be
determined by dividing the time constant by
the value of the internal resistance, 1.3kn.

a. VCO Output Frequency as a Function of Input Voltage and Bias
Current (Ko)
~o·

I'H4SI! COMP....... 'I'OIII'S

OUTPUT VOlTAGE ... mV

This value filter time constant will give a lessthan-critically-damped response allowing the
fast excursion in Vco frequency necessary to
good FSK reception. The tradeoff between
response speed and carrier frequency harmonic rejection will have to be considered. A
longer time constant gives more carrier rejection but slower response and less damping
(Refer to equation 2).

'0,"'·0_

The next step is to test the circuit under
actual operating conditions with the specified
FSK signal. The level on Pin 15 (hysteresis
adjust) must be set in the vicinity of + 1.4V in
order to attain proper FSK demodulation.
Final signal tests may be carried out with
noise injected through a resistive summing
network at the input (Pin 6) to simulate the
10dB SIN.
Note that the loop filter response actually
operates on the frequency spectrum above
(+) and below (-) the carrier center frequency, or center of deviation, for a symmetric FM
or FSK signal. This may be seen in Figure 4.

A(n

L:
-21.

(fo-fp)

I
I

i"\

'.

(to + fp)

-3dB

21.

Figure 4. Bandpass Effect of Loop
Filter
b. Variation of the Phase Comparator's Output Voltage vs Phase
Error and Bias Current (Ko)
Figure 3.

February 1987

4-281

•

I

Signetics

AN182
Clock Regenerator
With Crystal-Controlled
Phase-Locked VCO (NE564)

Linear Products

Application Note

"unknown" input is compared to the
"known" VCO frequency of the NE564. The
differential error signal that is generated is fed
through a DC amplifier and a voltage-tocurrent converter. The change in the current
generated forces the VCO frequency to vary
in its frequency and/or phase relationship,
such that a 0 of 90· lagging is obtained (the
actual phase relationship may be somewhat
less than 90· depending upon the KdKo (gain)
product of the NE564 at the operating frequency and bias current). The external filtering incorporated at Pins 4 and 5 control the
dynamic frequency response and loop stability criteria.

INTRODUCTION
In order to obtain a local clock signal in
Multiplexed Data Transmission systems, a
phase and frequency coherent method of
signal extraction is required. A Master-Slave
system using the quartz crystal as the primary
frequency determining element in a phaselock loop VCO is used to reproduce a phase
coherent clock from an asynchronous Data
Stream.
The NE564, a versatile phase-locked loop
(PLL) operating at frequencies of 50MHz, has
inputs and outputs designed to be TTL compatible. The Signetics NE564 is used to
generate the phase-locked, crystal-stabilized
clock reference signal.

THE CLOCK REGENERATOR
CIRCUIT
The basic building blocks of the clock regenerator circuit are shown in Figure 4. The PLL
is shown as a frequency multiplier incorporating a divide by "N" in the VCO phase
detector feedback loop. The functions of the
ringing circuit and the NE527 high-speed
comparator will be discussed later.
The waveforms of Figure 5 indicate the waveforms transmitted over a T1 line. The bipolar
signal transmitted has" no" DC components
induced in the transmission line (reference
should be made to the ellect of normal mode
and common ellects on signal information).
When transmitted over telephone wire pairs,
the resultant signal (at the receive end) will
have been degraded in both waveshape and
signal-to-noise ratios. Typical attenuation factors for a T1 line are - 30dS per 6000 feet.

The NE564 is a first order system; therefore,
the use of single capacitors (at Pins 4 and 5)
will automatically create a "second-order"
system. An RC series filter combination will
cause a lead-lag condition that will permit
dynamic selectivity, along with closed-loop
stability.

Its particular adaptation, for use with a crystal-controlled VCO instead of the usual RC
control elements, requires a brief review of
the principles of the Phase-Lock Loop design.
The NE564 Phase-Locked Loop is a fully
contained system, including limiter, phase
detector, VCO, DC amplifiers, DC retriever
and output comparator (reference Figure 1).
For the clock regeneration system to be
discussed, the portions of the NE564 implemented are the input limiter, phase detector
and VCO.

In addition, pair-to-pair crosstalk can degrade
signal-to-noise ratios. The energy transmitted
in the bipolar system of signal transfer is
centered at 772kHz (generated by the bit
format).

LOOP GAIN FUNCTIONS
The phase detector conversion gain (~) and
the VCO conversion gain (Ko) determine, in
large part, the lock range, capture range and
linearity characteristics of the NE564. These
device parameters are both dependent upon
bias current and operating frequency. Some
typical curves for each of the parameters are
shown for the NE564 in Figures 2 and 3.

The signal limiter amplifies low level inputs
(until saturation is reached, which is typically
60mVp.p for the NE564). The signal limiter
output is fed to the phase detector, where the

--

At the receiving end the bipolar signal information is converted to a unipolar pulse train
after being amplified, filtered and fed through
an automatic level control circuit. Some types
of PCM systems use the rectified and filtered
DC (average) to control the phase of the
regenerator clock; however, in newer systems, bipolar signals are preprocessed (or

LOW . . . .

Fl.""

----------,

,.

I

I
I
I
I

I

'-

11. CIU1'

+Vcc,o

L

..

,.

13

8

I
I

---------~-----------J[--------------------J

c:o..

":"

Figure
February 1987

~

4-282

Signetics Linear Products

Application Note

Clock Regenerator With Crystal-Controlled
Phase-Locked VCO (NE564)

AN182

liD· PttASf. ~ARATOR'S
OUTPUT YOI. 'Aat: .. ".y

800

'0 .. 1.0MHz
000

I

II

200

,eo

.........--.

:·filttAlE

-200

-coo

-lOG

-lOG

Figure 2. Variation of the Phase Comparator's Output Voltage vs Phase Error and Bias Current

February 1987

4-283

Signetics Linear Products

Application Note

Clock Regenerator With Crystal-Controlled
Phase-Locked VCO (NE564)

..

AN182

-

veo FREOUENCY

-400

800
YOIiI".V

,.
Figure 3. VCO Output Frequency as a Function of Input Voltage and Bias Current

preconditioned) by terminal common equip·
ment resulting in unipolar information,

T1 Data Transmission
The bipolar signal, as transmitted on a Tl
line, appears below with the original binary,
converted unipolar and clock waveform (ref·
erence Figure 5),
The bipolar signal, when transmitted over
standard wire pairs, will be degraded both in
wave shape and signal·to·noise by the time it
reaches the signal repeater. This is due to the
attenuation factor of the cable which is nearly
-30dB for 6000 It, In addition, pair to pair
crosstalk degrades signal-to-noise, The energy in the transmitted bipolar signal is centered
at 772kHz due to the particular bit format.
Bipolar signals have no DC offset.
At each receiving station the bipolar signal is
amplified, filtered and fed through an automatic level control circuit. A full wave rectified
signal is then sent to the clock regeneration
circuit. This is essentially the format followed
by some of the original Tl repeater equipment. The clock regeneration circuit described here could be adapted to this system,

February 1987

J'LJ1
DATA

-....
Figure 4

THE T1 SPECTRUM
The bipolar signal is similar to NRZ data in
that it does not contain carrier information, In
order to give the PLL coherent frequency
information sufficient to obtain" capture" and
lock, carrier components must be obtained
from the data stre,am, The time duration of
the frequency information fed to the PLL is
also important in order to obtain accurate and
stable information to update the PLL In order
to begin the extraction of frequency information, the positive-going portions o,f the bipolar
data signals are used to drive a class "C"

4-284

transistor tank circuit (reference Figure 4)
which is sharply tuned to the basic clock
frequency (1,544MHz), Each positive half cycle of data then starts a wave train of
coherent information which is phase synchronous with each succeeding positive data bit.
When the LC tank is optimally tuned, relatively extended periods without data bits can be
tolerated with minimal loss of frequency and
phase information, The combination of good
short-term frequency stability of the high "Q"
LC tank, coupled with the long-term stability
of the crystal-controlled VCO, is the founda-

Signetics Linear Products

Application Note

Clock Regenerator With Crystal-Controlled
Phase-locked VCO (NE564)

AN182

particular worst case condition is shown in
Figure 7 below.
BlNARV CODE

Solving equation 1 for the relative amplitude
of the 1.544MHz spectral component with the
pulse spacing shown,

..... ""'y
CYCLE

Ab
F(16)( T)

",""",A.

I

sin( 16rb)
(16rb)

I

where T = 2nb, n = 16.
CLOCK
1..........

Ab
sin( ~62n: )
= ((2)(16)b) (16nb)

Figure 5

A 2
327r

32b

= (0.02)A
= -34dB

I

~,
o

•

323.8nI

Figure 6
1

tion of the NE564 clock regeneration system
accuracy.

f=-

It must be emphasized that data pulse synchronization of the preprocessing circuit must
be frequency coherent with the fundamental
period of the time base to be extracted. That
is, if the time period of the clock is Vfc = T,
where fe is the clock frequency, then the
spacing between any positive code bit sequence must be n X t (reference Figure 6).

where f ,,;; fa = 1.544MHz

Looking at the spectral analysis of the relative
energy available to the clock extraction circuitry (with a worst-case duty cycle of 1 of 16)
will demonstrate the need for enchancing the
particular desired frequency component before applying the signal to the Phase-Lock
Loop. For fa = 1.544MHz, the period is
T = 647.67ns. The pulse or bit width is
323.8ns.
Here the bit duration 323.8ns = b. The Fourier expansion of the discrete spectrum is
related by the following equation:

I I

(Ab)
F(n)=T

sin( n7b )
n7b

n=0,1,2 ...

(2)

T

If we consider the special case of a single
pulse present out of 16 bipolar or 32NRZ
periods, then
T = 16 bipolar bit times
= 16 X 647.67ns = 10.3611S
f = 96.5kHz
Accordingly, the spectral lines will be spaced
in multiples of 96.5kHz. The spectrum for this

It is evident that as the bit spacing increases
to the point where fa is the 16th harmonic of
the fundamental, very little fa energy is available to drive a phase-loCk regeneration circuit. F(16) is also ineffective since it is an even
sub harmonic of fa. The PLL will not normally
lock to even harmonics; in fact, an error
signal is produced which tends to force the
VCO out of lock. This fact further stresses the
need for preprocessing in the frequency domain. The class "C" pulsed resonant tank
significantly multiplies the magnitude of the fa
spectral component and filters out unwanted
subharmonics.
The loop error voltage available from the
phase detector for phase correction of the
VCO is directly related to the product of the
incoming coherent spectral energy multiplied
in the balanced mixer with the reference
signal derived from the VCO. Since the phase
error information is integrated in the loop
filters, the instantaneous magnitude of the DC
error voltage is proportional to the time integral of coherent mixer products. Thus, as the
magnitude and time duration of the desired
frequency component is increased in the

.

(F")

T

(1)

The basic frequency component resulting
from various bit spacing factors is defined by
the equation

NOTE:
= 96.5kHz spacing

Figure 7
February 1987

4-285

Signetlcs Linear Products

Application Note

Clock Regenerator With Crystal-Control/ed
Phase-Locked VCO (NE564)
preprocessing circuitry, the VCO phase accuracy is greatly improved. Capture time is
obviously enhanced also.
The signal from the tuned tank is buffered by
a FET follower N-channel enhancement
mode device (reference Figure 12). This provides power gain with virtually no loading on
the tank circuit and avoids degrading the
"0". The buffered signal is then fed to a highspeed comparator (Signetics' NE527) which
allows for waveform symmetry adjustment in
addition to providing a standard TTL output to
drive the NE564 PLL.
In the particular circuit shown in Figure 12,
the 1.544MHz information is applied to the
phase detector input of the NE564 PhaseLock Loop. The VCO, however, is operated at
four (4) times this frequency to order to take
advantage of economical and readily available crystals. The VCO signal is fed through a
divide-by-four counter (74LS73) to provide
the Phase Detector reference and final regenerated clock signal. To avoid loading, the
clock signal (1.544MHz) is buffered by the
75451 peripheral driver which provides a
high-speed open collector TTL output. The
input signal is AC coupled in order to reduce
DC bias errors in the Phase Detector caused
by "0" level variations.

AN182

NE564 CRYSTAL-CONTROLLED
VCO
As shown in Figure 8, the crystal is operated
with a series capacitor. When properly
trimmed, this allows the crystal to operate
near the series resonant mode. A crystal
manufactured to operate in the series resonant mode will do so only if it sees a pure
resistance looking into the oscillator terminals. The circuit below shows an oscillator
which looks inductive with the equivalent
crystal circuit and trimmer capacitor Ct (reference Figure 9).
If La is small and the internal gain of the
device high over a wide frequency range, Lo
may resonate with the Co of the crystal at a
very high frequency. Under certain conditions
the circuit may even tend to operate in the
3rd overtone mode unless measures are
taken to roll-off the circuit gain. This is the
purpose of Cs in Figure 8. Since the gain of
the VCO is a factor in spurious oscillation, the
current injected into Pin 2 will also have an
effect in this respect. (Ko increases with 12)'
At higher operating frequencies this parameter may become more critical in attaining
stable start ups in the desired frequency
mode. Obviously the size of Cs must be
smaller than the value needed to cause free
running near the desired frequency without
the crystal connected.

CRYSTAL SPECIFICATION

Figure 8

The Crystal
The crystal used was chosen to match the
NE564 VCO drive characteristics. It is an
" AT" cut oscillator crystal which operates
near the anti-resonate or "parallel" mode in
this circuit. The crystal may have to be finetuned, as indicated in Figure 8. The pulling
characteristic of the crystal is adequate to
allow for 0 to 70·C operational drift plus initial
and aging accuracy tolerance factors and still
retain lock between master and slave station
VCXOs. The average lock range at room
temperature with one of sixteen data bits
present is typically 1000Hz for a 6.176MHz
crystal with a capture range greater than
500Hz.
For VCO operation at 6.176MHz, Cs is 22pF,
Cc is 18pF, and Ct, a 1 - 8pF trimmer capacitor (reference Figure 8).

Crystals may be manufactured to operate in
either the series mode with no external capacitance (purely resistive load) or in the
parallel mode with a specified value of load
capacitance. The 564 tends to operate at a
frequency above the specified value when a
series mode crystal is used. For a design
frequency of 6.176000MHz and zero load
capacitance. Referring to Figure 8, for
Cs = 10pF and CT = 1OpF the average center
frequency for an NE564 sample measured in
the lab was 6181.192kHz. For the same Cs,

but with CT equal to 60pF, fa measured
6176.565kHz. A second crystal showed a
spread of 6176.600kHz to BI80.855kHz. The
effect of the VCO was to pull the crystal to a
frequency above its design value. This effect
is then nearly tuned out by the external
capacitances Cs and CT. If CT is sufficiently
increased, the crystal will see a purely resistive load and operate at its rated frequency.
A second approach is to specify a crystal
which is to operate near the anti-resonate or
parallel mode. Normally this is done with a
certain value of external load capacitance
specified by the customer which matches the
existing circuit parameters. The maximum
difference between series and parallel resonance for any crystal is 0.5% of fa (series
resonant mode); for fr = 6.126MHz, 0.5% of
fr = 30kHz. The usual value would be lower
than this.

fa=fr~ro

ro = electromechanical coupling factor,
fa = parallel resonant frequency). The particular cut of the crystal material determines the
drift response over temperature. For oscillator
applications, the AT cut offers the best overall stability over a wide frequency and temperature range. Final design uses second approach.
For a stability or total tolerance of ± 15ppm
over the rated operating range of -20·C to
+ 70·C, a certain manufacturer's crystal actually performed as shown above (Refer to
Figure 11).
Calibration accuracy is the allowable frequen_
cy tolerance at the reference temperature,
i.e., ± 10ppm @ 25·C.
Third, is a long-term drift spec which determines the customer's maximum allowable
drift due to aging effects. An acceptable value
in quality crystals is ± 2ppm/year.

NOTES:
Co "" XT AL Shunt capacitors
C1 = Equivalent Xl AL series resonant arm capacitance
L1 = Equivalent Motional Inductance
R1 = Equivalent crystal series resistance
Cs

= External

shunt or stray capacitance

Figure 9
February 1987

4-286

Signetics Linear Products

Application Note

Clock Regenerator With Crystal-Controlled
Phase-Locked VCO (NE564)

NOTES,
Cl = Motional capacitance
Co = Shunt capacitance
Rl = Equivalent Resistance
Ll "" Equivalent inductance

Figure 10. Basic Crystal Equivalent Circuit

--~

+"'"

-20"<:

+70"<:

Figure 11. Design Example
Using our reference crystal of 6.176MHz and
the above specifications, the crystal limits
over a 1 year period would be:
Temperature
stability:
± 15ppm X 6.176
=± 93Hz
Calibration
± 10ppm X 6.176
tolerance:
=± 62Hz
@25°C
Long term drift: ± 2ppm X 1 X 6.176
=±12Hz
Total:
(± 167Hz)
The above figure of ± 167Hz then determines
the capture and lock range over which two
crystal stabilized VCOs must track under
worst case conditions when the exact same
crystal specifications are used for master and
slave units within an operational system.

Crystal Specifications
•AT' Cut OSCillator Type
Fundamental mode operation HC·33 Case
(Standard)
Calibration tolerance:
± 10ppm @ 25°C
Temperature stability:
± 15ppm; -15°C to + 65°C
Circuit operating condition:
Parallel resonance

February 1987

Frequency specified: 6.176000MHz
Part designation:
Craven # A330 DEF·32 or equivalent

Setup Procedure
Referring to Figure 12, the following setup
procedure will aid the user in establishing
proper circuit operation.
Regulated supply voltage of + 5V and -6V
are required. Current drain on the + 5V line is
- 100mA, and 6mA for the -6V.
With proper voltage applied, (1) First check
the supply currents to be sure they are in the
range indicated above. (2) Check the operation of the NE564 VCXO by looking at Pin 9
with an oscilloscope (see Figure 13). A reasonably symmetric square wave should be
present, having a frequency near 6.1 MHz. (3)
Attach a DVM across the 2k resistor which
feeds Pin 2 of the NE564 and adjust for a
reading of 2.00V, indicating a 1mA DC current
flowing into Pin 2 (The (+) lead of the DVM
should be connected to the end of the 2k
resistor which ties to the wiper of the 10k pot
and the (-) lead to Pin 2 of the 564; reference
Figure 14). (4) The exact center frequency is
set by adjusting C(, the crystal trimmer cap,
for exactly 6.176000MHz with no signal input
(thiS sets the center frequency of the VCXO
to free-run in the center of the capture range).
(5) Enable strobe 'A' and 'B' with a + 2. 7V
min. to + 5V max. level. Apply a standard
1.544MBS NRZ data signal to the input
terminal, terminated in 50n. The amplitude
should be + 3 to + 5V (0 to peak). Set the duty
cycle for 1 bit in a 16-bit period. Note the data

4-287

AN182

generator must be driven from a crystalcontrolled master oscillator also adjusted for
a center data rate of 1.544 OOOMBS. Monitor
the buffered output of the ringing circuit with a
scope connected to the source of the S0213
(Figure 15). The waveform should appear as
in Figure 17. (6) Adjust tank trimmer cap CT
for a maximum amplitude and note that the
cycle period should be 647ns. (7) Now monitor the comparator output signal at Pin 7 and
adjust Rt for a 50% duty cycle. The same
signal will appear at Pin 5 of the NE527
except it will be inverted. The signal on Pin 7
of the NE527 and Pin 6 of the NE564 should
appear as shown in Figure 19. Now attach
one lead of a dual-trace scope to Pin 7 of the
NE527 and the other to Pin 3 of the NE564 as
shown (Figure 16).
The two Signals should be in phase-locked
with an approximate 90° differential as shown
in Figure 20 (data signal applied to @
1.544MBS). If lock does not occur, a slight
trimming of the crystal trimmer CT should
correct for slight differences in master-toslave crystal tolerance. It is recommended
that master and slave crystals be of the exact
same design and specification to insure optimal tracking over time and temperature. A
recommended manufacturer and part number
appears at the end of this application note for
your convenience.
Once lock is attained, move one lead of the
dual-trace scope to the buffered output of the
75451 Pin 3, leaving the other scope probe
on Pin 6 of the NE564. The phase-locked
waveform should appear as in Figure 25. If a
data word generator is being used, you may
check overall operation for various bit patterns by synchronizing the scope trigger on
the "end of word" pulse, then observe the
phase error effect as different combinations
are fed in.

PHASE JITTER
When operating with real-time data transmission, the PLL loop filters must be optimized to
minimize regenerated clock jitter. A good
grade of mylar capacitor is recommended as
connected to Pins 4 and 5 of the NE564. A
simple pair of shunt-connected loop filter
caps of 0.33!LF to 0.76!LF was found to be
adequate.

II

~

"'tJ ()
:1'
_
0

oen

~

(i)

::J

~
()
00

,7'

co

'"....

0;;0
(') (i)

+5V

h1."F
2K

'"1-= I I
I

1.544MHz

'0

":"

"'l

4700

1K

3V

4700

NE564

(11:1'

--,

11

S0213

51OK.

~()

'-'-<

I

47o.

-=

ON'3M

c,.

10Hz

00

,K

l,F'

1000

-

BUFFER
AMP

g

a

(i)

a.

-

-=

00

ClASS
'C'

a-

a

12

1K

< ...
oQ
.z. . . :e_.
m()9.

•

G

(i)

a.::J
(i)

10K

I
I

'G-6OpF

'0 =

(i)

"A"

r-

22~ II

7'<0

,,,,DJ

STROBE

430pF MICA

N
00

(')

5-

DRIVE

-6V

10 14

StGNAL

DRIVER

MONITOR
TEST POINT

74LS73
.;.4

Cc = 18pF SILVER MICA
Cr 1-8pF TRIMMER
XTAl = CRVEN A330 DEF-32

=

-=

'AT' CUT OSCILLATOR

'0 =6.176000MHz

1 II

r-...J

~45'

c. = 22pF SILVER MICA

CRYSTAL

,,-I

1.544MHz
BUFFERED
OUTPUT

-= f'1.rr

1.544Mttz

NOTES:
Cs = 22pF silver mica
Cc = 18pF silver mica
CT = 1.BpF trimmer
XTAL = crven A330 Def-32
,AT' cut oscillator
crystal to = 6.176000MHz.

»
z
Figure 12. Data Transmission System Clock Regenerator

-?J

'Q.

~

o

~

::J

00

Z

I\)

~

Signetics Linear Products

Application Note

Clock Regenerator With Crystal-Controlled
Phase-locked VCO (NE564)

NOTE:
Check

veo

AN182

free-running frequency and output waveshape.

Figure 13. Check VCO Free-Running Frequency
and Output Waveshape

0

..

.1

•

0

~;
50213

Figure 14

lr- sc"""
...r:rTC07560S

Figure 16

Figure 15

500nS

lOOmV
lOOmV

SOOns

III' I II '1

I

l
I

,.

,..,

,..

"\

!n

,

,.

" ~I\t "\ In I

II

II fI\ \ I II \ \ 1
U \1
U IV \ 1I

I'

II J Il \

lOOmV

1 J rn IT r 1
L I .J .J IL LJ J
L.

200mV

lL

U

200nS

n

DATAWUT
1.544a18)5

1

Il

COMPARATOR OUTPUT
C1

If

L

I
U

2V

IL

r .........
.....

~

J

I
l

NE514
~3

2V

Figure 19. Ringing Circuit to Square Wave Conversion

February 1987

_t

J Ul

Figure 18. Ringing Circuit Response (4 Data Pulses In 16)

500nS

I

r"\ In f"I

J

v

2V

Figure 17. Ringing Circuit Response (1 Data Pulse In 16)

DATA 141ft '1)

LU J IL I

D4TAPULSE
( lin 181

Figure 20. Phase Comparator Signals (in Lock)

4-289

Signetics linear Products

Application Note

Clock Regenerator With Crystal-Controlled
Phase-Locked VCO (NE564)

IV

200nS

....

IV

200nS
Ml,l.TR.E DATA ,'.

I

I
J

..1IMT"'"
,.

l

~

AN182

r
J

1
l

J

r

........

Q.OC1(
1

II

CUT

I

>:II

,

Il

........

Q.OC1( OUT
1

I

2V
OP0377DS

Figure 21. Regenerated Clock Signals

IV

Figure 22. Regenerated Clock Signals

200nS

~

>:II

I

I

.L. ....

L

r...

:n

I

III

I I I II

-

VCOCUT

II

• • 17.....)

....

I
J

(rWO>COI1

A

I

.I III

-

I
J

I

J.
I

J

..

04TA .. (RANDOM)

It..

r

J

~

Il

a.oac OUT (BUFFEMD)

2V

Figure 25. Regenerated Clock Signal
Relative to Random NRZ Data Signal

References
1. "Fourier Analysis" by Hwei P. Hsu. Simon & Schuster Tech
Outlines
2. "Pulse and Digital Circuits" by Millman and Taub McGraw Hill
3. "Phaselock Techniques" by Floyd M. Gardner Wiley. 1966

February 1987

I 11 /I

1.1 Il L I

YCOOUT

'.178MHa

Figure 24. Regenerated Clock Signal
Relative to NE564 YCO Signal

200nS

L

1
li-

2

Figure 23. Regenerated Clock Signals
Relative to NE564 YCO Signal

IV

,........

CLOCK CUT

IMfA ..

I

4-290

NE/SE565

Signetics

Phase-locked loop
Product Specification

Linear Products

DESCRIPTION
The NE/SE565 Phase-Locked Loop
(PLL) is a self-contained, adaptable filter
and demodulator for the frequency
range from 0.001 Hz to 500kHz. The
circuit comprises a voltage-controlled
oscillator of exceptional stability and linearity, a phase comparator, an amplifier
and a low pass filter as shown in the
Block Diagram. The center frequency of
the PLL is determined by the free-running frequency of the veo; this frequency can be adjusted externally with a
resistor or a capacitor. The low pass
filter, which determines the capture
characteristics of the loop, is formed by
an internal resistor and an external capacitor.

FEATURES

PIN CONFIGURATIONS

• Highly stable center frequency
(200ppmJOC typ.)
• Wide operating voltage range
(± 6V to ± 12V)
• Highly linear demodulated output
(0.2% typ.)

F, N Packages

INPUT

2

INPUT

3

yeo OUTPUT
PHASE
COMPARATOR

4

10 v+
5
EXTERNAL C
REFERENCE 6
FORVCO
OUTPUT
8 EXTERNAL R
DEMODULATED 7
FORVCO
OUTPUT
'-----'

• Center frequency programming
by means of a resistor or
capacitor, voltage or current
• TTL and DTL compatible square
wave output; loop can be
opened to Insert digital
frequency divider
• Highly linear triangle wave output
• Reference output for connection
of comparator in frequency
discriminator
• Bandwidth adjustable from
<±1% to >±60%
• Frequency adjustable over 10 to
1 range with same capacitor

veo INPUT

TOP VIEW
C011180S

o
INPUT

Package 1

1

11

v+
~~1E~~~L C

10

~~1EV~tL R

12

vcaOUTPUT 4
PHASE
COMPARATOR 5
vcorNPUT
NC •

9 NC

REFERENCE
OUTPUT

DEMODULATED
OUTPUT

TOP VIEW
NOTE:
1. SO ru1Q non·standard pin out.

APPLICATIONS
• Frequency shift keying

BLOCK DIAGRAM

c2
DEMOD. OUTPUT

INPUT

L __...J-=-"-"t"1T-OREF.

November 6, 1986

4-291

OUTPUT

• Modems
• Telemetry receivers
• Tone decoders
• seA receivers
• Wide-band FM discriminators
•
•
•
•

Data synchronizers
Tracking filters
Signal restoration
Frequency multiplication &
division

853-0909 86385

Signetics Linear Products

Product Specification

NEjSE565

Phase-Locked Loop

EQUIVALENT SCHEMATIC
~~~_E_~

....
zw

z
Z
z

""

:>

:>

..."

a:

~

ttl

VV

1.0

V

""-

:>

co

Q

W

"w~

~
~

.
0

10

14

18

22

TOTAL SUPPLY VOLTAGE -

26

rrr tt~

I

~

111111

€

.
....

:>

-1

....
:>

8
a::• ol'lll!il'1:i
fN_
0

........

f-l,

~J

,/

0.5

2.0

i1

1.5

"> 1
Z I
z>-

:>"

0.20.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

DESIGN FORMULAS
(See Figure 1)
Free-running frequency of VCO:
1.2
fo""-- in Hz
4R 1C1
BfO
in Hz
Vee
1 • /2iifL
Capture range: fe""± V ~-2"
T
Lock range: fL

where

T =

=±-

(3.6 X 103) X C2

2.0

November 6, 19B6

10

I-+-f",",d--+--lf-/-+--+--I

3.0

2.5

0.2 0.4 0.6 0.8 1.0 1.2

v,o-v,

~ffi
w:>

>
I

V- =6V
=6V

1.0
0.5

z

-1.5

:I:

-2.0
-2.5

"

./

L

V

V

./

V

.
.
z

0:

-1

:>

-2

....
....

:>

0

>

"z

.

\ I
r......

0:

..

....:>
....
:>
0

'\

'\

!/'

1\ II

\ I

r-

-

I

./
,

-n-~-~

1.4 1.6 1.8

NORMALIZED LOCK RANGE

VCO Output
Waveform

~

~

n

W01~

t--

~

-2
V+=V-=6V

0

TEMPERATURE _ °C

this output signal which causes the VCO to
shift its frequency to match that of the input.
Consequently, the linearity of the phase comparator output with frequency is determined
by the voltage-to-frequency transfer function
of the VCO.
Because of its unique and highly linear VCO,
the 565 PLL can lock to and track an input
signal over a very wide bandwidth (typically
± 60%) with very high linearity (typically, within 0.5%).
A typical connection diagram is shown in
Figure 1. The VCO free-running frequency is
given approximately by

TYPICAL APPLICATIONS
FM Demodulation
The 565 Phase-Locked Loop is a general
purpose circuit designed for highly linear FM
demodulation. During lock, the average DC
level of the phase comparator output Signal is
directly proportional to the frequency of the
input Signal. As the input frequency shifts, it is

1-+--+-+-+--+--+-++--+--1

I
~
~

1.5

100

'11

./

v+

"0 -0.5
"-w

."

RELATIVE FREE·RUNNING FREOUENCY - I.

.e.a:

2.5
0

w

-2

1.0

r-,.......",....,-,--,-..-r-n--I

Change In Free-Running
VCO Frequency as a
Function of Temperature

z"
-"-1.0

0

V

1000

.j

VOLTAGE BETWEEN PIN 7 AND PIN 10 -

Lock Range
as a Function of
Gain Setting Resistance
(Pins 6-7)

>

0.5

"oz

V

v+ =6V
V- =6V

Lock Range
as a Function of
Input Voltage

and should be adjusted to be at the center of
the input signal frequency range. C1 can be
any value, but R1 should be within the range
of 2000 to 20,000.11 with an optimum value on
the order of 4000.11. The source can be direct

4-294

coupled if the DC resistances seen from Pins
2 and 3 are equal and there is no DC voltage
difference between the pins. A short between
Pins 4 and 5 connects the VCO to the phase
comparator. Pin 6 provides a DC reference
voltage that is close to the DC potential of the
demodulated output (Pin 7). Thus, if a resistance is connected between Pins 6 and 7, the
gain of the output stage can be reduced with
little change in the DC voltage level at the
output. This allows the lock range to be
decreased with little change in the freerunning frequency. In this manner the lock
range can be decreased from ± 60% of fo to
approximately ± 20% of fo (at ± 6V).
A small capacitor (typically O.OOIIlF) should
be connected between Pins 7 and B to
eliminate possible oscillation in the control
current source.
A single-pole loop filter is formed by the
capacitor C2, connected between Pin 7 and
the positive supply, and an internal resistance
of approximately 3600.11.

Signetics Linear Products

Product Specification

NEjSE565

Phase-Locked Loop

r---~----~----r---~----~------O·+6V

C,

.ru

DEMODULATED
OUTPUT
REfERENCE
OUTPUT

'----"------0 - 6V
~--~----------------------~--~-6V

Figure 1

Frequency Shift Keying (FSK)
FSK refers to data transmission by means of
a carrier which is shifted between two preset
frequencies. This frequency shift is usually
accomplished by driving a VCO with the
binary data signal so that the two resulting
frequencies correspond to the "0" to "1"
states (commonly called space and mark) of
the binary data signal.
A simple scheme using the 565 to receive
FSK signals of 1070Hz and 1270Hz is shown
in Figure 2. As the signal appears at the input,
the loop locks to the input frequency and
tracks it between the two frequencies with a
corresponding DC shift at the output.
The loop filter capaCitor C2 is chosen smaller
than usual to eliminate overshoot on the
output pulse, and a three-stage RC ladder
filter is used to remove the carrier component
from the output. The band edge of the ladder
filter is chosen to be approximately half way
between the maximum keying rate (in this
case 300 baud or 150Hz) and twice the input
frequency (approximately 2200Hz). The output signal can now be made logic compatible
by connecting a voltage comparator between
the output and Pin 6 of the loop. The freerunning frequency is adjusted with R1 so as to
result in a slightly-positive voltage at the
output with fiN = 1070Hz.
The input connection is typical for cases
where a DC voltage is present at the source
and therefore a direct connection is not

Figure 2
desirable. Both input terminals are returned to
ground with identical resistors (in this case,
the values are chosen to effect at 600n input
impedance).

Frequency Multiplication
There are two methods by which frequency
multiplication can be achieved using the 565:
1. Locking to a harmonic of the input signal.
2. Inclusion of a digital frequency divider or
counter in the loop between the VCO and
phase comparator.
The first method is the simplest, and can be
achieved by setting the free-running frequency of the VCO to a multiple of the input
frequency. A limitation of this scheme is that
the lock range decreases as successively
higher and weaker harmonics are used for
locking. If the input frequency is to be constant with little tracking required, the loop can
generally be locked to anyone of the first 5
harmonics. For higher orders of multiplication,
or for cases where a large lock range is
desired, the second scheme is more desirable. An example of this might be a case
where the input signal varies over a wide
frequency range and a large multiple of the
input frequency is required.
A block diagram of the second scheme is
shown in Figure 3. Here the loop is broken
between the VCO and the phase comparator,
and a frequency divider is inserted. The
fundamental of the divided VCO frequency is
locked to the input frequency in this case, so
that the VCO is actually running at a multiple
of the input frequency. The amount of multi-

'----'---------~-6V

Figure 3
November 6, 1986

Figure 4

4-295

plication is determined by the frequency divider. A typical connection scheme is shown in
Figure 4. To set up the circuit, the frequency
limits of the input signal must be determined.
The free-running frequency of the veo is
then adjusted by means of R1 and C1 (as
discussed under FM demodulation) so that
the output frequency of the divider is midway
between the input frequency limits. The filter
capacitor, C2, should be large enough to
eliminate variations in the demodulated output voltage (at Pin 7), in order to stabilize the
VCO frequency. The output can now be taken
as the VCO squarewave output, and its fundamental will be the desired multiple of the
input frequency (fiN) as long as the loop is in
lock.

SeA (Background Music)
Decoder
Some FM stations are authorized by the FCC
to broadcast uninterrupted background music
for commercial use. To do this, a frequency
modulated subcarrier of 67kHz is used. The
frequency is chosen so as not to interfere
with the normal stereo or monaural program;
in addition, the level of the subcarrier is only
10% of the amplitude of the combined signal.
The SCA signal can be filtered out and
demodulated with the NE565 Phase-Locked
Loop without the use of any resonant circuits.
A connection diagram is shown in Figure 5.
This circuit also serves as an example of
operation from a single power supply.
A resistive voltage divider is used to establish
a bias voltage for the input (Pins 2 and 3). The
demodulated (multiplex) FM signal is fed to
the input through a two-stage high-pass filter,
both to effect capacitive coupling and to
attenuate the strong signal of the regular
channel. A total signal amplitude, between
80mV and 300mV, is required at the input. Its
source should have an impedance of less
than 10,000n.
The Phase-Locked Loop is tuned to 67kHz
with a 5000n potentiometer; only approximate tuning is required, since the loop will
seek the signal.

II

Signetics Linear Products

Product Specification

NE/SE565

Phase-Locked Loop

The demodulated output (Pin 7) passes
through a three-stage low pass filter to provide de-emphasis and attenuate the high-

frequency noise which often accompanies
SeA transmission. Note that no capacitor is
provided directly at Pin 7; thus, the circuit is

r-------~r_----~r_------~----~----_r-o:~!~
10k

h~l~

.018

1.8k

.047

__r-__~r,iI---Tcq.--1~l~kI,-L~l~k_L~lk~.l-oIBACKGROUND
Io1USIC(SCAI

Figure 5

November 6, 1986

.018

4-296

operating as a first-order loop. The demodulated output signal is in the order of 50mV and
the frequency response extends to 7kHz.

Signetics

AN183
Circuit Description of the
NE565 PLL
Application Note

Linear Products

CIRCUIT DESCRIPTION OF THE
NE565 PLL
The 565 is a general purpose PLL designed
to operate at frequencies below 1MHz. The
loop is broken between the VCO and phase
comparator to allow the insertion of a counter
for frequency multiplication applications. With
the 565, it is also possible to break the loop
between the output of the phase comparator
and the control terminal of the VCO to allow
additional stages of gain or filtering. This is
described later in this section.
The VCO is made up of a precision current
source and a non-saturating Schmitt trigger.
In operation, the current source alternately
charges and discharges an external timing
capacitor between two switching levels of the
Schmitt trigger, which in turn controls the
direction of current generated by the current
source.
A simplified diagram of the VCO is shown in
Figure 1. 11 is the charging current created by
the application of the control voltage Ve. In
the initial state, Q3 is off and the current 11
charges capacitor C1 through the diode 02.
When the voltage on C1 reaches the upper
triggering threshold, the Schmitt trigger
changes state and activates the transistor Q3.
This provides a current sink and essentially
grounds the emitters of Q1 and Q2' The
charging current 11 now flows through 0 1, Q1
and Q3 to ground. Since the base-emitter
voltage of Q2 is the same as that of Q1, an
equal current flows through Q2' This discharges the capacitor C1 until the lower
triggering threshold is reached, at which point
the cycle repeats itself. Because the capacitor C1 is charged and discharged with the
constant current 11, the VCO produces a
triangle waveform as well as the square wave
output of the Schmitt trigger.
The complete circuit for the 565 is shown in
Figure 2. Transistors Ql - Q7 and diodes
0 1 - 03 form the precision current source.
The base of Q1 is the control voltage input to
the VCO. This voltage is transferred to Pin 8
where it is applied across the external resistor
R1. This develops a current through R1 which
enters Pin 8 and becomes the charging
current for the VCO. With the exception of the
negligible Q1 base current, all the current that
enters Pin 8 appears at the anodes of diodes
02 and 03. When Qa (controlled by the
Schmitt trigger) is on, 0 3 is reverse-biased
and all the current flows through 02 to the
duplicating current source Qs - Q7, R2 - R3
February 1987

and appears as the capacitor discharge current at the collector of Qs. When Qa is off, the
duplicating current source Qs - Q7, R2 - R3
floats and the charging current passes
through 03 to charge Cl'

The switching stage Qla, Q19, Q22 and Q23 is
driven from the Schmitt trigger via Pin 5 and
011. Diodes 012 and 0 13 limit the phase
comparator output, and differential amplifier
Q26 and Q27 provides increased loop gain.

The Schmitt trigger (Q11' Q12) is driven from
the capacitor triangle waveform by the emitter-follower Q9. Oiodes 06 - 09 prevent saturation of Q11 and Q12, enhancing the switching speed. The Schmitt trigger output is
buffered by emitter-follower Q13 and is
brought out to Pin 4, and is also connected
back to the current source by the differential
amplifier (Q14 - Q16)'

The loop low pass filter is formed with an
external capacitor (connected to Pin 7) and
the collector resistance R24 (typically 3.6kn).
The voltage on Pin 7 becomes the error
voltage which is then connected back to the
control voltage terminal of the VCO (base of
Q1)' Pin 6 is connected to a tap on the bias
resistor string and provides a reference voltage which is nominally equal to the output
voltage on Pin 7. This allows differential
stages to be both biased and driven by
connecting them to Pins 6 and 7.

When operated from dual symmetrical
supplies, the square wave on Pin 4 will swing
between a low level of slightly (O.2V) below
ground to a high level of one diode voltage
drop (O.7V) below the positive supply. The
triangle waveform on Pin 9 is approximately
centered between the positive and negative
supplies and has an amplitude of 2V with
supply voltages of ± 5V. The amplitude of the
triangle waveform is directly proportional to
the supply voltages.
The phase comparator is again of the doublybalanced modulator type. Transistors Q20
and Q24 form the signal input stage, and must
be biased externally. If dual symmetrical
supplies are used, it is simplest to bias Q20
and Q24 through external resistors to ground.

The free-running center frequency of the 565
is adjusted by means of R1 and C1 and is
given approximately by
(1)

When the phase comparator is in the limiting
mode (VIN;;' 200mVp.p), the lock range can
be calculated from the expression:
(2)

r-----------~------o+v

SCHMITT
TRIGGER

Figure 1. Simplified Diagram of NE565

4-297

veo

•

Application Note

Signetics Linear Products

Circuit Description of the NE565 Pll

Rg

AN183

R15

~--~----~~------~----~----~----~----~----~L-

CURRENT SOURCE

vco

SCHMITT TRIGGER

°25

028.

R26

~ R27

______-L__

~l

PHASE COMPARAlOR AMPLIFIER FILTER

Figure 2. Circuit Diagram of 565
where Ko is the VCO conversion gain, Kd is
the phase comparator's conversion gain, A is
the amplifier gain, and I1d is the maximum
phase error over which the loop can remain in
lock. Specific values for the terms of Equation
2 for the 565 are
1.4
Kd = --V Irad

(3)

11"

A = 1.4

to each side of the free·running frequency, or
a total lock range of:
16fO

2fL~±--Hz

The lock·in range can be written as:

fe~±~ ~=±~
211"

(8)

(9)

to each side of the free·running frequency or
a total capture range of:

fe~~
11"

50fo'

rad

Ko = - - - - - - - Vee Volt·sec

where wL is the one·sided tracking range

(6)

where Vee is the total supply voltage applied
to the circuit.

(10)

and

T

is the time constant of the loop filter

The tracking range for the 565 then becomes:

(11 )

(7)

February 1987

y327rf0 '
Vee
(12)

The capture range, over which the loop can
acquire lock with the input signal, is given
approximately by:

11"

ed = 2rad

211"

Vee

(4)
(5)

T

4·298

y327rf0 '
TVee

(13)

This approximation works well lor narrow
capture ranges (Ie = hfd but becomes too
large as the limiting case is approached
(fe= ftJ·
When it is desired to operate the 565 out 01
its limiting mode (VIN < 200mVp.p or
32mVRMS), Kd can be estimated from the
graph in Figure 3 for the specific input voltage
anticipated. The previous calculations for the
lock and capture ranges remain valid with the
new value of Kd from the graph being used to
replace the KdA product in Equation 2. In
Figure 3, the DC amplifier gain A has been
included in the Kd value.

Signetics linear Products

Application Note

Circuit Description of the NE565 PLL

AN183

Kd
VOL TS/RAD

.5

I

DIFFERENTIAL
r - INPUT
OR SECOND
r - _~INPUT
AC[
r - GROUNDED

/

.01

1/

/1/

/

/

.05
I

/

SINGLE - ENDED

INPUT

o--ji~--+--I

/
.01

INPUT

)"

.-

800
.005
565 PIN 7 '6VSUPPl.V

II

.001
.5

10

50

INPUT
mV - RMS

100

I

Figure 3. Phase Comparator's Conversion Gain, Kd , for the
565 as a Function of Input Signal Amplitude
For applications where both a narrow lock
range and a large output voltage swing are
required, it is necessary to inject a constant
current into Pin 8 and increase the value of
R1. One scheme for this is shown in Figure 4.
The basis for this scheme is the fact that the
output voltage controls only the current
through R1, while the current through 01
remains constant Thus, if most of the charging current is due to 01 the total current can
be varied only a small amount due to the
small change in current through R1. Consequently, the VCO can track the input signal
over a small frequency range, yet the output
voltage of the loop (control voltage of the
VCO) will swing its maximum value.
Diode D1 is a Zener diode, used to allow a
larger voltage drop across RA than would
otherwise be available. D4 is a diode which
should be matched to the emitter-base junction of 01 for temperature stability. In addition, D1 and 02 should have the same breakdown voltages and D3 and D4 should be
similar so that the voltage seen across Rs
and Rc is the same as that seen across Pins
10 and 1 of the phase-locked loop. This
causes the frequency of the loop to be
insensitive to power supply variations. The
free-running frequency can be found by:

Figure 4. Narrow Bandwidth FM Demodulator Using the 565

where VD is the forward-biased diode voltage
(",,0.7V), Vz is the zener diode breakdown
voltage, V1 is the positive supply voltage, and
V2 is the negative supply voltage.
When the output excursion at Pin 7 need be
only a volt or so, diodes 01, 02 and D3 may
be replaced by short circuits.
The value of R1 can be selected to give a
prescribed output voltage for a given frequen·
cy deviation.
(16)
where fl.f is the desired frequency deviation
per volt of output
In most instances, Rs and RA are chosen to
be equal so that the voltage drop across
them is about 200mV. For best temperature
stability, diode D1 should be a base-collector
shorted transistor of the same type as 01.

When the 565 is connected normally, feedback to the VCO from the phase comparator
is internal. That is, an amplifier makes the Pin
8 voltage track the Pin 7 (phase comparator
output) voltage. Since the capacitor C1
charge current is determined by the current
through resistance R1, the frequency is a
function of the voltage at Pin 8. It is pOSSible,
(14)
however, to bypass and swamp the internal
loop amplifier so that the current into Pin 8 is
no longer a function of the Pin 8 voltage but
and the total range is given by:
only of the Pin 7 voltage. This makes a
greater charge-discharge current variation
2fL ~
22.4VD(Rs + Rc)RAfO'
Hz possible, allowing a greater lock range. Figure
(]V1] + ~2]- Vz - VD)[8RsR1 + RA(Rs + Rcll 5 shows such a circuit in which the /lA741
operational amplifier is set for a differential
(15)
February 1987

4-299

gain of 5, feeding current to Pin 8 through the
33kn resistor (simulating a current source).
Not only is the tracking range greatly expanded, but the output voltage as a function
of frequency is five times greater than normal.
In setting up such a circuit, the deSigner
should keep in mind that for best frequency
stability, the charge-discharge current should
be in the range of 50 to 1500/1A, which also
specifies the Pin 8 input current range, showing that a ratio of upper to lower lock extremes of about 30 can be achieved.
Many times it would be advantageous to be
able to break the feedback connection between the output (Pin 7) and the control
voltage terminal (01) of the VCO. This can be
easily done once it is seen that it is the
current into Pin 8 which controls the VCO
frequency. Replacing the external resistor R1
with a current source, such as in Figure 6,
effectively breaks the internal voltage feedback connection. The current flowing into Pin
8 is now independent of the voltage on Pin 8.
The output voltage (on Pin 7) can now be
amplified or filtered and used to drive the
current source by a scheme such as that
shown in Figure 6. This scheme allows the
addition of enough gain for the loop to stay in
lock over a 100: 1 frequency range or, conversely, to stay in lock with a preCise phase
difference (between input and VCO signals)
which is almost independent of frequency
variation. Adjustment of the voltage to the
non-inverting input of the op amp, together
with a large enough loop gain allows the
phase difference to be set at a constant value
between 0° and 180°. In addition, it is now
possible to do special filtering to improve the
performance in certain applications. For in-

Signetics Linear Products

Application Note

Circuit Description of the NE565 Pll

AN183

stance, in frequency multiplication applications, it may be desirable to include a notch
filter tuned to the sum frequency component
to minimize incidental FM without excessive
reduction of capture range.

+10V

8.2K

22K (19 TO 1556 HI: LOCK)
33K !57 TO 1910 Hz LOCK)

t--+--+-----"A1'v--,
.22J'F

INPUT

<>-7

lK

.221

lK

50K

,F

-10V

Figure 5. Expanded Lock Range Configuration for the 565

r - - -......---~.....--------<>.,2

.,

A.v.!!f
Figure 6. Increased Loop Gain and Lock Range for the 565

February 1987

4-300

AN184

Signetics

Typical Applications With

NE565
Application Note

Linear Products

FSK DEMODULATION
FSK refers to data transmission by means of
a carrier which is shifted between two preset
frequencies. This frequency shift is usually
accomplished by driving a veo with the
binary data signal so that the two resulting
frequencies correspond to the "0" and "1"
states (commonly called space and mark) of
the binary data signal.

FSK Demodulation with the 565
A simple scheme using the 565 to receive
FSK signals of 1070Hz and 1270Hz is shown
in Figure 1. As the signal appears at the input,
the loop locks to the input frequency and
tracks it between the two frequencies with a
corresponding De shift at the output (Pin 7).

,-~-"""1--~--~--r-O+5V

O.1JlF

D---i

10K

A more sophisticated approach primarily useful for narrow frequency deviations is shown
in Figure 2. Here, a constant current is
injected into Pin 8 by means of transistor 0 1 .
This has the effect of decreasing the lock
range and increasing the output voltage sensitivity to the input frequency shift. The basis
for this scheme is the fact that the output
voltage (control voltage for the VeO) controls

February 19B7

10K

2

I

FSK

II

INPUT

600
~--~------------------------~---o-5V

Figure 1. FSK Decoder Using the 565

The loop filter capacitor C2 is chosen to set
the proper overshoot on the output and a
three-stage RC ladder filter is used to remove
the sum frequency components. The band
edge of the ladder filter is chosen to be
approximately half-way between the maximum keying rate (300 baud or bits per second, or 150Hz). The free-running frequency
should be adjusted (with R1) so that the DC
voltage level at the output is the same as that
at Pin 6 of the loop. The output signal can
now be made logic compatible by connecting
a voltage comparator between the output and
Pin 6.
The input connection is typical for cases
where a DC voltage is present at the source
and, therefore, a direct connection is not
desirable. Both input terminals are returned to
ground with identical resistors (in this case,
the values are chosen to achieve a 600n
input impedance).

+14V

-5V

Figure 2. FSK Decoder With Expanded 565
Output Voltage Range
only the current through R1, while the current
through 01 remains constant. Thus, if most of
the capacitor charging current is due to OJ,
the current variation due to R1 will be a small
percentage of the total charging current and,
consequently, the total frequency deviation of
the veo will be limited to a small percentage

4-301

of the center frequency. A 0.25J.1F loop filter
capacitor gives approximately 30% overshoot
on the output pulse, as seen in the accompanying photographs. Figure 3 shows the output
of the !lA710 comparator and the output of
the 565 phase· locked loop.

Application Note

Signetics Linear Products

Typical Applications With NE565

AN184

LOGIC IOUTPU) 15V/CM!_

l

l

I

U

I

)

/ ~i\

~

f' hi

~Ij

t\...

'.

\

\./' .-f

PLL rTPUT AFHR i'L TER roo mVltMI
B. 100 Baud

lOGI

OUTPL 15V/CL -

I
/

r

I
I
I

"

/

.............

"-- /

1\

'\,

~

/

Pll OUTPUT AFTER FILTER

1200mtcM1 I

I

b. 200 Baud

l
I

J

r,

LOGL OUTLT 15vJMI

.rl
J

"'-V

1",

r 11

I--

V,
/

"-V I"'-V
PLL OUTPUT AFTER FILTER

12oom'tMI

c. 300 Baud
Figure 3

February 1987

/

I

4-302

I

Signetics Linear Products

Application Note

Typical Applications With NE565

AN184

seA
+Vcc
+lDVOLTS
+24 VOLTS

1.aK

'OK

6K

,00'

'0 7

4.7K

'K

'K

BACKGROUND
MUSIC (SCA)

NE565

4.7K

4.7K

4.7K

Figure 4. SeA Decoder

February 1987

,K

4-303

Demodulator Using the

565
This application involves demodulation of a
frequency·modulated subcarrier of the main
channel. A popular example here is the use of
the PLL to recover the SCA (Subsidiary Carri·
er Authorization or storecast music) Signal
from the combined Signal of many cammer·
cial FM broadcast stations. The SCA signal is
a 67kHz frequency·modulated subcarrier
which puts it above the frequency spectrum
of the normal stereo or monaural FM program
material. By connecting the circuit of Figure 4
to a point between the FM discriminator and
the de·emphasis filter of a commercial band
(home) FM receiver and tuning the receiver to
a station which broadcasts an SCA Signal,
one can obtain hours of commercial-free
background music.

•

NEjSE566

Signetics

Function Generator
Product Specification

Linear Products

DESCRIPTION

FEATURES

The NE/SE566 Function Generator is a
voltage-controlled oscillator of exceptional linearity with buffered square wave
and triangle wave outputs. The frequency of oscillation is determined by an
external resistor and capacitor and the
voltage applied to the control terminal.
The oscillator can be programmed over
a ten-to-one frequency range by proper
selection of an external resistance and
modulated over a ten-to-one range by
the control voltage, with exceptional linearity.

• Wide range of operating voltage
(up to 24V; single or dual)
• High linearity of modulation
• Highly stable center frequency
(200ppmfOC typical)
• Highly linear triangle wave output
• Frequency programming by
means of a resistor or capacitor,
voltage or current
• Frequency adjustable over 10-to1 range with same capacitor

PIN CONFIGURATIONS

APPLICATIONS
•
•
•
•
•
•

Tone generators
Frequency shift keying
FM modulators
Clock generators
Signal generators
Function generators

D, N Packages

GROUNOo'V'
Ne

2

7

C1

SQUARE WAVE
OUTPUT

3

6

R

TRIANGLE WAVE

4

5

1

OUTPUT

MODULATION
INPUT

TOP VIEW

F Package
NC ,

GROUND

3

SQUARE WAVE
TRIANGLE

4

WAVE 5

NC'

8

MODULATION
INPUT

TOP VIEW

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

8-Pin Plastic SO

o to + 70°C

14-Pin Cerdip

o to + 70°C

NE566F

8-Pin Plastic DIP

o to + 70°C

NE566N

NE566D

14-Pin Cerdip

-55°C to + 125°C

SE566F

8-Pin Plastic DIP

-55°C to + 125°C

SE566N

BLOCK DIAGRAM

November 6, 1986

4-304

853-0910 86386

Signetics Linear Products

Product Specification

NEjSE566

Function Generator

EQUIVALENT SCHEMATIC

v'

GROUND

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

RATING

UNIT

V+

Maximum operating voltage

26

V

VIN

Input voltage

3

Vp_p

Storage temperature range

-65 to + 150

·C

Operating ambient temperature
range
NE566
SE566

o to +70
-55 to +125

·C
·C

300

mW

TSTG
TA

PD

Power dissipation

November 6, 1986

4-305

•

Signetics Linear Products

Product Specification

NEjSE566

Function Generator

DC ELECTRICAL CHARACTERISTICS TA = 25°C; Vee = ± 6V, unless otherwise specified.
NES66

SE566
SYMBOL

UNIT

PARAMETER
Min

Typ

Max

Min

Typ

Max

General
TA

Operating ambient temperature range

-55

125

a

70

Vee

Operating supply voltage

±6

±12

±6

±12

V

Icc

Operating supply current

12.5

rnA

7

12.5

7

°C

veo '
fMAX

1

1

MHz

Frequency drift with temperature

500

600

ppm/oC

Frequency drift with supply voltage

0.1

Control terminal input impedance2

1

Maximum operating frequency

FM distortion (± 10% deviation)

0.2

Maximum sweep rate
Sweep range

0.2

1

2

1
0.75

0.4

1

1

10:1

10:1

%N
Mn

1.5

%
MHz

Output

tR
tF

Triangle wave output
impedance
voltage
linearity
Square wave input
impedance
voltage
duty Cycle
Rise time
Fall Time

1.9

5
45

50
2.4
0.2
50
5.4
50
20
50

1.9

55

NOTES:
1. The external resistance for frequency adjustment (R 1) must have a value between 2kS'l and 20kS'l.
2. The bias voltage (Vel applied to the control terminal (Pin 5) should be in the range 'l'.v+ ~ Vc ~ v+.

November 6, 1986

4-306

5
40

50
2.4
0.5

n
Vp.p
%

50
5.4
50
20
50

n
Vp.p
%
ns
ns

60

Signetics Linear Products

Product Specification

NEjSE566

Function Generator

TYPICAL PERFORMANCE CHARACTERISTICS
Normalized Frequency as a
Function of Control Voltage
2.S

v+

>u

ffi

2.0

"0a:w
u.

1.5

":::;

1.0

":IEa:
0

z

""

'"~

V

~

w
U

z
;0

",,/

0.5

100

=12VOLTS

/V

W

N

Normalized Frequency as a
Function of Aeslstance (A1)
v+

= 12 VOLTS
Vc-10 VOLTS

50

""

10

'"

iii
w

a:

1.5

2.0

2.5

CONTROL VOLTAGE
(BETWEEN PIN 8 AND PIN 5) -

""'0w
:z

3.0

0.1

~

.
z

17.5

VOLTS

15.0

III

0:
0:

:0

<.>

12.5

...

~ 10.0

iii

7.5

Ll~~
-I)
~

V

"-

~

V

1/

V

I

1.0

~
w

0.1

;

13

18

19

22

25

OPERATING INSTRUCTIONS
The NE/SE566 Function Generator is a general purpose voltage-controlled oscillator designed for highly linear frequency modulation.
The circuit provides simultaneous square
wave and triangle wave outputs at frequencies up to 1MHz. A typical connection diagram is shown in Figure 1. The control
terminal (Pin 5) must be biased externally with
a voltage (Vel in the range

:r4V+ <'Vc<'V+
where Vee is the total supply voltage. In
Figure 1, the control voltage is set by the
voltage divider formed with R2 and R3. The

November 6, 1986

1 V

1/

-1.0

z

-1.5

'" I\..

0.01

'\

1/

' ~,\'
i"'l..I. 1-1": ~\'

,\\' lY

-75-50-25

0 +25+50+75+100+125

TEMPERATURE _1°C)

VCO Output Waveforms

>
I

..

V+ _12 VOLTS

z

..

1/1'\

ii:

[/]\.

1/

:0

0

>
I

I\..

"I"'-

'"Z

10' 104

..

ii:

'\

102

,\lW ~ \ \ W
l\ \' 'IV

I!::0

I

10

1\\ 1:\\\ ~

i/TYPICAL

- 2.5

V+ • 12 VOLTS
Vc.10.5 VOLTS
R1- 4K

f\-

0.0001
SUPPLY VOLTAGE - V

-0.5

III

10

'''I

~ 0.001

V
10

10

~

1

V+=12VOLTS
Vc=10VOLTS

:r: - 2.0 )Y
u

,,

Frequency as a Function
of Capacitance (C1)

<.>

~~

0.5

+0.5

NORMALIZED FREOUENCY

A1_4kO

/

0.2

.,
".

~
,,

Power Supply Current as a
Function of Supply Voltage
20.0

+ 2.5
+ 2.0

>u + 1.0
Z

20

1

1.0

t

+ 1.5

,/V
0.5

Change In Frequency as a
Function of Temperature

r-r-

r-r-

8
B

:0

,

10'

12
10

I!::0
0

10'

FREQUENCY - hz

modulating signal is then AC coupled with the
capacitor C2. The modulating signal can be
direct coupled as well, if the appropriate DC
bias voltage is applied to the control terminal.
The frequency is given approximately by

and R, should be in the range 2k!1
R, < 20k!1.

<

A small capacitor (typically O.001IlF) should
be connected between Pins 5 and 6 to
eliminate possible oscillation in the control
current source.

4-307

If the VCO is to be used to drive standard
logic circuitry, it may be desirable to use a
dual supply as shown in Figure 2. In this case
the square wave output has the proper DC
levels for logic circuitry. RTL can be driven
directly from Pin 3. For DTL or TTL gates,
which require a current sink of more than
1mA, it is usually necessary to connect a 5k!1
resistor between Pin 3 and negative supply.
This increases the current sinking capability
to 2mA. The third type of interface shown
uses a saturated transistor between the 566
and the logic circuitry. This scheme is used
primarily for TTL circuitry which requires a
fast fall time « 50ns) and a large current
sinking capability.

•

-,',','

Signetics Linear Products

Product Specification

NEjSE566

Function Generator

.--......- ......--ov·

+8 VOLTS
15K

10K

Figure 1

November 6, 1986

Figure 2

4-308

AN185

Signefics

Circuit Description of the
NE566
Application Note
Linear Products

CIRCUIT DESCRIPTION OF THE
566 PLL
The 566 is the voltage-controlled oscillator
portion of the 565. The basic die is the same
as that of the 565; modified metalization is
used to bring out only the VCO. The 566

circuit diagram is shown in Figure 1. Transistor 0'8 provides a buffered triangle waveform
output. (The triangle waveform is available at
capacitor C, also, but any current drawn from
Pin 7 will alter the duty cycle and frequency.)
The square wave output is available from 0'9

by Pin 4. The circuit will operate at frequencies up to 1MHz and may be programmed by
the voltage applied on the control terminal
(Pin 5), by injecting current into Pin 6, or by
changing the value of the external resistor
and capacitor (R, and C,).

·v
liN
0.1 TO 1mA

9
I

+p~n
I

r-----·T-~r_------~r-~r-------~--~--~------_._Ov·

".

vco--.--t'

Rn

R.

~----~------~~-L-----L----__~__-l______-J~

____1-o,
GNO

CURRENT SOURCE

veo

SCHMITT TRIGGER

Figure 1. Circuit Diagram of the NE566

February 1987

4-309

•

Signetics

AN186
Waveform Generators With the
NE566
Application Note

Linear Products

WAVEFORM GENERATORS

Ramp Generators

The oscillator portion of many of the PLLs
can be used as a precision, voltage-controllable waveform generator. Specifically, the 566
Function Generator contains the oscillator of
the 565 PLL. Most of the applications which
follow are designs using the 566. Many of
these designs can be modified slightly to
utilize the oscillator section of the 564 if
higher frequency performance is desired.

Figure 1 shows how the 566 can be wired as
a positive or negative ramp generator. In the
positive ramp generator, the external transistor driven by the Pin 3 output rapidly discharges C, at the end of the charging period
so that charging can resume instantaneously.
The PN P transistor of the negative ramp
generator likewise rapidly charges the timing
capacitor C, at the end of the discharge
period. Because the circuits are reset so

,vee

quickly, the temperature stability of the ramp
generator is excellent. The period
1
T is2fo
where fo is the 566 free-running frequency in
normal operation .. Therefore,

T=

...!.. = _R_T,-C..:.,'V_c:..:c,2fo

(1)

5(Vcc- Vc)

~Vcc

1.5K

~
Vc
10K

..-!--i-oH----+--O

~

1.SK

/\/V
r-

4-~~~
10K

SAWTOOTH

T --/

a. Negative Ramp

a. Positive Sawtooth

+Vcc

~SAWTOOTH

~PULSE
I--T-I
b. Positive Ramp
Figure 1. Ramp Generators
February 1987

b. Negative Sawtooth
Figure 2. Sawtooth and Pulse Generators

4-310

Application Note

Signetics Linear Products

AN186

Waveform Generators With the NE566

where Vc is the bias voltage at Pin 5 and RT
is the total resistance between Pin 6 and Vcc.
Note that a short pulse is available at Pin 3.
(Placing collector resistance in series with the
external transistor collector will lengthen the
pulse.)

stability. The charge and discharge times may
be estimated by using the formula

Sawtooth and Pulse Generator

where RT is the combined resistance between Pin 6 and Vcc for the interval considered.

Figure 2 shows how the Pin 3 output of the
566 can be used to provide different charge
and discharge currents for C, so that a
sawtooth output is available at Pin 4 and a
pulse at Pin 3. The PNP transistor should be
well saturated to preserve good temperature

T

= _R-,-TC---,-1V--,c:;.:c:....

(2)

5(Vcc- Vc)

Triangle-to-Sine Converters
Conversion of triangle wave shapes to sinusoids is usually accomplished by diode-resistor shaping networks, which accurately reconstruct the sine wave segment by segment.
Two simpler and less costly methods may be

used to shape the triangle waveform of the
566 into a sinusoid with less than 2% distortion.
In Figure 3, the non-linear IDS.VDS transfer
characteristic of a P-channel junction FET is
used to shape the triangle waveform.
The amplitude of the triangle waveform is
critical and must be carefully adjusted to
achieve a low distortion sinusoidal output.
Naturally, where additional waveform accuracy is needed, the diode-resistor shaping
scheme can be applied to the 566 with
excellent results since it has very good output
amplitude stability when operated from a
regulated supply.

"'12 V

2K

25K
AMPLITUDE

,.-

ADJUST

5K

5K

SQuARe
WAVE

OUTPUT

.IL

ru

TRIANGLE
WAVE

OUTPUT

"IV' -::

SINE

1M

IN9l4

ADJUST

WAVE
OUTPUT

-'2V

Figure 3_ Triangle-to-Sine Converters

.'2V

.,

1.SK

.001

~

vc
+12V

+12V

~

'OK

.,

I

180K

se.

,

APPLICATION OF poweR

3R1C,

R,

6.2V

,'K
OPTIONAL ~
REGULATED
CAPACITOR
CHARGING CIRCUIT

TONE FREO. '"

0.5 SEC TONE
BURST FOLLOWING

-=

Ic'

-=-50-=
,F

:f'

Figure 4. Single-Burst Tone Generator
February 1987

4-311

.,

Signetics Linear Products

Application Note

Waveform Generators With the NE566

AN186

"-Vcc

-Vee

-Vee
CENTER
FREO.
ADJUST

+Vee

CeNTER

MOO.

FREO.
ADJ.

MODULATION
FREQUENCY
ADJUST

FREQ.

20K

ADJUST
1.SK

'K

1.SK
'OK

N
'OK

p~
R

.".

.".

.".

.".

.".

.".

LOW-PASS FIt. TER OR

_
-

_
-

c,

DEVIATION
ADJUST

~ ICi

.".

LOW-PASS Fil TER OR SINE CONVERTER

SINE CONVERTER MAY

MAY BE INSERTED HERE IF SINUSOIDAL
MODULATION IS REQUIREO

BE INSERTED HERE
IF SINUSOIDAL MODULATION
IS RECUIRED

a. Small Frequency Deviations to ± 20%

b. Large Frequency Deviations to ± 100%

Figure 5. Frequency-Modulated Generators

Single-Tone Burst Generator
Figure 4 is a tone burst generator which
supplies a tone for one· half second after the
power supply is activated; its intended use is
a communications network alert signal. Ces·
sation of the tone is accomplished at the
SCR, which shunts the timing capacitor C,
charge current when activated. The SCR is
gated on when C2 charges up to the gate
voltage which occurs in 0.5 seconds. Since
only 70llA are available for triggering, the SC
must be sensitive enough to trigger at this
level. The triggering current can be increased,

February 1987

of course, by reducing R2 (and increasing C2
to keep the same time constant). If the tone
duration must be constant under widely varying supply voltage conditions, the optional
Zener diode regulator circuit can be added,
along with the new value for R2, Rl = 82kn.
If the SCR is replaced by an NPN transistor,
the tone can be switched on and off at will at
the transistor base terminal.

Low Frequency FM Generators
Figure 5 shows FM generators for low frequency (less than 0.5MHz center frequency)
applications. Each uses a 566 function gener-

4-312

ator as a modulation generator and a second
566 as the carrier generator.
Capacitor C, selects the modulation frequency adjustment range and C, ' selects the
center frequency. Capacitor C2 is a coupling
capacitor which only needs to be large
enough to avoid distorting the modulating
waveform.
If a frequency sweep in only one direction is
required, the 566 ramp generators given in
this section may be used to drive the carrier
generator.

Signetics

NEjSE567
Tone DecoderjPhase-Locked
Loop
Product Specification

Linear Products

DESCRIPTION
The NE/SE567 tone and frequency decoder is a highly stable phase-locked
loop with synchronous AM lock detection and power output circuitry. Its primary function is to drive a load whenever a
sustained frequency within its detection
band is present at the self-biased input.
The bandwidth center frequency and
output delay are independently determined by means of four external components.

FEATURES
• Wide frequency range (_01Hz to
500kHz)
• High stability of center frequency
• Independently controllable
bandwidth (up to 14%)
• High out-band signal and noise
rejection
• Logic-compatible output with
100mA current sinking capability
• Inherent Immunity to false
signals

• Frequency adjustment over a
20-to-1 range with an external
resistor
• Military processing available

FE, D, N Packages

~~:~~:~~T~~

8

OUTPUT

2

7

GROUND

INPUT
SUPPLY

3

6

~~'::;NTS

VOLTAGE"'V

4

5

TIMING

LOW·PASS FIL TEA
CAPACITOA Cz

APPLICATIONS
• Touch-Tone@ decoding
• Carrier current remote controls
• Ultrasonic controls (remote TV,
etc.)
• Communications paging
• Frequency monitoring and
control
• Wireless intercom
• Precision oscillator

0

PIN CONFIGURATIONS

A1

AND C,
ELEMENT ",

TOP VIEW

F Package

BLOCK DIAGRAM

LOOP

LOW

PASS
FILTER

~C2

+v

®Touch-Tone is a registered trademark of AT & T.

November 5, 1986

4-313

853-0124 86356

m
c:

z

0

<

CD

0

'V

3

<:
)0

C"

~

06

00

0'.

021

Oll

9'

0,

039

••

''''

04'

0"

0'

r

4.7k
e _________ .,

<0

ex>

r

C3 L

m

m

Z
-t
VI

0

:J:

m

i!:
)0

-t

(=)

r ."t·d
·V

..."

,

c,t
:

.;.

t.:.

06

R20

-=-R12

en

0"
:J

::1

~

(J)

~

0

,-S"
CD

(J)

a

0

(3

0

a.
(J)
....

~

"U

a.

c

()

iii"

..........
"'0
';j

0

(I)

(J)

·V

"'j

.....

0

R22

I

r-tF

r'

O~

8060

R36

R40

r-

0
0

C

'"
a.
(J)

A43

~

-=-

":" 'V

R13

'V

.:!

~

r-

0
0

u

~

.;.

I I

I

'1
A26

<.

R27

"U

(3

Z

m

..........
R28.2'

R36<

R44>

R41S

a.
c

n.

en

en

"0
CD

01
0-

IT

m

."-J

()

S.

0"
:J

Signetics Linear Products

Product Specification

Tone Decoder/Phase-Locked Loop

NE/SE567

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

a to
a to
a to
a to

8-Pin Plastic SO
14-Pin Cerdip
8-Pin Cerdip
8-Pin Plastic DIP

ORDER CODE

+ 70·C

NE567D

+ 70·C

NE567F

+ 70·C

NE567FE

+ 70·C

NE567N

14-Pin Cerdip

- 55·C to + 125°C

SE567F

8-Pin Cerdip

- 55·C to + 125·C

SE567FE

8-Pin Plastic DIP

- 55·C to + 125·C

SE567N

ABSOLUTE MAXIMUM RATINGS
SYMBOL
TA

PARAMETER

Operating temperature
NE567
SE567

Vcc
V+

Positive voltage at input

V-

Negative voltage at input

VOUT

Output voltage (collector of output
transistor)

Operating voltage

TSTG

Storage temperature range

PD

Power dissipation

November 5, 1986

RATING

UNIT

a to +70
-55 to + 125

·C
·C

10

V
V

0.5 +

Vs

-10

VDC

15

VDc

-65 to + 150

·C

300

mW

4-315

..
i

Signetics linear Products

Product Specification

NE/SE567

Tone Decoder/Phase-Locked Loop

DC ELECTRICAL CHARACTERISTICS v + = 5.0V; TA = 25'C, unless otherwise specified.
SYMBOL

I

NE567

SE567

UNIT

TEST CONDITIONS

PARAMETER

Min

Typ

Max

Min

Typ

Max

Center frequency 1
fa

Highest center frequency

fa

Center frequency stability2

fa

Center frequency distribution

fa

Center frequency shift with
supply voltage

-55 to + 125'C
o to +70'C
1
fa = 100kHz = - - 1.1 R1C1

-10

1
10 = 100kHz = - - 1.1 R1C1

500

500

kHz

35 ± 140
35 ±60

35 ± 140
35 ±60

ppm/'C
ppm/'C

0

+10

0.5

1

14

16

2

4

-10

0

+10

%

0.7

2

%/V

14

18

% 0110

3

6

% 0110

Detection bandwidth
1
10 = 100kHz = - - 1.1 R,C,

BW

Largest detection bandwidth

12

10

BW

Largest detection bandwidth
skew

BW

Largest detection bandwidthvariation with temperature

VI = 300mVRMS

±0.1

±0.1

%I'C

BW

Largest detectionbandwidthvariation with supply voltage

VI = 300mVRMS

±2

±2

%N

Input
RIN

Input resistance

VI

Smallest detectable input
voltage4

IL = 100mA, fl = 10

15

Largest no-output input voltage4

IL = 100mA, II = 10

10

Greatest simultaneous out-band
signal-to-in-band signal ratio
Minimum input signal to
wide-band noise ratio

Bn = 140kHz

20

25

20

25

15

15

10

20

25

kn

20

25

mVRMS

15

mVRMs

+6

+6

dB

-6

-6

dB

Output
Fastest on-off cycling rate
"1" output leakage current
"0" output voltage

fo/20

10/20

VB = 15V

0.01

25

0.01

25

JJ.A

IL=30mA
IL = 100mA

0.2
0.6

0.4
1.0

0.2
0.6

0.4
1.0

V
V

tF

Output lall time3

RL = 50n

30

30

ns

tR

Output rise time3

RL = 50n

150

150

ns

General
Vcc

4.75

Ope,ating voltage range
Supply current quiescent
Supply current - activated

IpD

RL = 20kn

Quiescent power dissipation

9.0
6

8

11

13

30

NOTES:

1. Frequency determining resistor R, should be between 2 and 20k~l
2. Applicable over 4.75V to 5.75V. See graphs for more detailed information.
3. Pin 8 to Pin 1 feedback RL network selected to eliminate pulsing during turn-on and turn-off.

4. With R2 = 130k!'l from Pin 1 to V+. See Figure 1.

November 5, 1986

4-316

4.75

9.0

V

7

10

mA

12

15

35

mA
mW

Signetics Linear Products

Product Specification

NE/SE567

Tone Decoder/Phase-Locked Loop

TYPICAL PERFORMANCE CHARACTERISTICS
Largest Detection
Bandwidth vs
Operating Frequency

Bandwidth vs Input
Signal Amplitude
300

~

15

.

I
:z:

200

"~
>

.."
!

N

'\

:z:

;SO

10

.0

I-

10'

C

1

\

ic

150

...,
z

0

I-

~

0

0"

>

I
w

10'

""

u.

250

E

Detection Bandwidth as
a Function of C2 and C3

100

~
N

I-

~

""- '-.....
'-..... I'---- I'---- c,

is

iil

8'
.0

"::la:

50

10'

I'---- r--. c,

10'
4
6
6 10 12
BANDWIDTH - % OF fo

14 16

0.1

1

10

100

o

1000

2

CENTER FREQUENCY - kHz

6
8
10 12
BANDWIDTH - % OF

'0

14

16

OP04300$

Typical Supply Current vs
Supply Voltage

..

E
I

25
20

w
a:
a:
~

-

10

00-

~

::>

til

V

~+ttl=+==t==!=t:l==I

500
300

AOLOlD
"ON" CURRENT

1-4+t+-+--++-t+--I

~

/V'

::>

CJ

/'

15

Typical Output Voltage VB
Temperature
>

.,

CUR,RENT

30~-+-+~~"~I'L~IB-A-N~D-WL'D~T~H-~
10

I

~-++-+-+"'>"I-f\.LlMiTEI·U'-

10

10

SUPPLY VOLTAGE - V

50

BANDWIDTH -

I

0.9

I

0.8

z

0.7

;;;:
w

"...

QUIESCE~I

I

1.0

1000 ....--r-"1~,...-J.,.....l""!'Tll--,

I~

I-

z

Greatest Number of Cycles
Before Output

I-

0.5

0

>

0.4

I-

::>

0.3

::>
0

0.2

0I-

100

I, = ,OOmA

0.6

r--.

IL= 30mA

0.1
0
-75

V

/

V

I
-25

% 0110

0

25

50 75 100125

TEMPERATURE - 'C

OPD43208

Typical Frequency Drift
With Temperature
(Mean and SO)

Typical Frequency Drift
With Temperature
(Mean and SO)

1.5

1.5

+

+V=4.75V

1.0

....
0



0.8

r--.

1'1,

o!..

~

.......

"'-

E

8:- 100
~I
-200

15I-

~t

.

0.7

~13

0.4

2:
I
2:

i"

0:;

~

15.0

0.9

--r--.t--.

1:;<.>

/

0.6

5.5

6.0

6.5

SUPPLY VOLTAGE -

v

PHASE-LOCKED LOOP
TERMINOLOGY CENTER
FREQUENCY (fo)
The free-running frequency of the current
controlled oscillator (CCO) in the absence of
an input signal.

2 3 4 5

November 5, 1986

:J:

7.5

10

8
6

~

5.0

4

;:l

2.5

2

20

40

-75

100

2.

3.

TYPICAL RESPONSE

INPUT

-

-

OUTPUT
~~

~~

~--

-25

0

25

75

TEMPERATURE -

kHz

Figure 1 shows a typical connection diagram
for the 567. For most applications, the following three-step procedure will be sufficient for
choosing the external components R1, C1 , C2
and Ca.
1. Select R1 and Cl for the desired center
frequency. For best temperature stability,
R, should be between 2K and 20K ohm,
and the combined temperature coefficient of the R,Cl product should have
sufficient stability over the projected temperature range to meet the necessary
requirements.

125

·C

Select the low-pass capacitor, C2, by
referring to the Bandwidth versus Input
Signal Amplitude graph. If the input amplitude Variation is known, the appropriate value of faC2 necessary to give the
desired bandwidth may be found. Conversely, an area of operation may be
selected on this graph and the input level
and C2 may be adjusted accordingly. For
example, constand bandwidth operation
requires that input amplitude be above
200mVrms. The bandwidth, as noted on
the graph, is then controlled solely by the
faC2 product (fa (Hz), C2("F».
The value of Ca is generally non-critical.
Ca sets the band edge of a low-pass filter
which attenuates frequencies outside the
detection band to eliminate spurious outputs. If Ca is too small, frequencies just
outside the detection band will switch the
output stage on and off at the beat
frequency, or the output may pulse on
and off during the turn-on transient. If Ca
is too large, turn-on and turn-off of the

NOTE:
RL = 100n
+V

Response to 100mVRMS Tone Burst

~

OUTPUT

-

INPUTo---)

Rl

587

R,

.

fD"'R,'C,

R2

VV

INPUT

NOTES:

SIN =-6dB
RL = 100n
Noise Bandwidth"" 140Hz

Response to Same Input Tone Burst
With Wldeband Noise

4-318

+v

JlI

~­

-- --

Detection Band Skew
A measure of how well the detection band is
centered about the center frequency, fa. The
skew is defined as (fMAX+ fMIN-2fa)/2fa
where fmax and fmin are the frequencies
corresponding to the edges of the detection
band. The skew can be reduced to zero if
necessary by means of an optional centering
adjustment.

10

OPERATING INSTRUCTIONS

Lock Range
The largest frequency range within which an
input signal above the threshold voltage will
hold a logical zero state on the output.

10.0

14
12

BAN DWITH AT 25·C

CENTER FREQUENCY -

Detection Bandwidth (BW)
The frequency range, centered about fa,
within which an input signal above the threshold voltage (typically 20mVRMS) will cause a
logical zero state on the output. The detection
bandwidth corresponds to the loop capture
range.

I-

z

./

----

V

Where
VI = Input voltage (VRMS)
C2 = Low-pass filter capacitor ("F)

.
I

0.3

7.0

DESIGN FORMULAS

....
0

-

12.5

e

0.1
5.0

~

l-

0.2

= aoc TO 70°C

/

0.5

-300
4.5

Typical Bandwidth Variation
Temperature

Figure 1

Signetics Linear Products

Product Specification

NEjSE567

Tone DecoderjPhase-Locked Loop

output stage will be delayed until the voltage
on C3 passes the threshold voltage. (Such
delay may be desirable to avoid spurious
outputs due to transient frequencies.) A typical minimum value for C3 is 2C2.
4. Optional resistor R2 sets the threshold for
the largest "no output" input voltage. A
value of 130kn is used to assure the
tested limit of 1OmVRMS min. This resistor
can be referenced to ground for increased sensitivity. The explanation can
be found in the "optional controls" section which follows.

OUT1'tJT
(peN IJ

1-:

Y'

'''''
LOW PASS

,.OV

FILTER
(PIN 21

'.7V

AVAILABLE OUTPUTS (Figure 2)
The primary output is the uncommitted output
transistor collector, Pin 8. When an in-band
input signal is present, this transistor saturates; its collector voltage being less than 1.0
volt (typically 0.6V) at full output current
(100mA). The voltage at Pin 2 is the phase
detector output which is a linear function of
frequency over the range of 0.95 to 1.05 fo
with a slope of about 20mV per percent of
frequency deviation. The average voltage at
Pin 1 is, during lock, a function of the in-band
input amplitude in accordance with the transfer characteristic given. Pin 5 is the controlled
oscillator square wave output of magnitude
(+V -2VSE)""(+V-1.4V) having a DC average of + VI 2. A 1kn load may be driven from
pin 5. Pin 6 is an exponential triangle of 1Vp_p
with an average DC level of + V12. Only high
impedance loads may be connected to pin 6
without affecting the CCO duty cycle or temperature stability.

PIN'
VOLTAGE

II

(AVGI 4 .0

'.0
2S~ ____, -____~_

o

100

200m Vrrns

IN-BAND

INPUT
VOLTAGE

Figure 2

INCREASE

DECREASE
SENSITIVITY

SENSITIVITY

OPERATING PRECAUTIONS
A brief review of the following precautions will
help the user achieve the high level of performance of which the 567 is capable.
1. Operation in the high input level mode
(above 200mV) will free the user from
bandwidth variations due to changes in
the in-band signal amplitude. The input
stage is now limiting, however, so that
out-band signals or high noise levels can
cause an apparent bandwidth reduction
as the inband signal is suppressed. Also,
the limiting action will create in-band
components from sub-harmonic signals,
so the 567 becomes sensitive to signals
at fo/3, fo/5, etc.
2. The 567 will lock onto signals near (2n + 1)
fo, and will give an output for signals near
(4n + 1) fo where n = 0, 1, 2, etc. Thus,
signals at 5fo and 9fo can cause an
unwanted output. If such signals are anticipated, they should be attenuated before
reaching the 567 input.
3. Maximum immunity from noise and outband signals is afforded in the low input
November 5, 1986

Y.

R.

DECREASE
RS tSENStTlVITY

1-_"";"-0-<2.5K INCREASE
SENSITIVITY

lie

l.OK

}

SILICON
DIOOESfOR
TEMPERATURE
COMrENSATION
(OPTIONAL)

Figure 3

4.

level (below 200mV RM S) and reduced
bandwidth operating mode. However, decreased loop damping causes the worstcase lock-up time to increase, as shown by
the Greatest Number of Cycles Before
Output vs Bandwidth graph.
Due to the high switching speeds (20ns)
associated with 567 operation, care
should be taken in lead routing. Lead
lengths should be kept to a minimum.

4-319

The power supply should be adequately
bypassed close to the 567 with a 0.0111F
or greater capacitor; grounding paths
should be carefully chosen to avoid
ground loops and unwanted voltage variations. Another factor which must be
considered is the effect of load energization on the power supply. For example,
an incandescent lamp typically draws 10
times rated current at turn-on. This can

Signetics Linear Products

Product Specification

NE/SE567

Tone Decoder/Phase-Locked Loop

cause supply voltage fluctuations which
could, for example, shift the detection band of
narrow-band systems sufficiently to cause
momentary loss of lock. The result is a lowfrequency oscillation into and out of lock.
Such effects can be prevented by supplying
heavy load currents from a separate supply or
increasing the supply filter capacitor.

+V

+V

..7

RA
200 TO lK

AL

AL

•

+V

+V

•

"7

C,

At

At

'01(

..7

SPEED OF OPERATION
Minimum lock-up time is related to the natural
frequency of the loop. The lower it is, the
longer becomes the turn-on transient. Thus,
maximum operating speed is obtained when
C2 is at a minimum. When the signal is first
applied, the phase may be such as to initially
drive the controlled oscillator away from the
incoming frequency rather than toward it.
Under this condition, which is of course
unpredictable, the lock-up transient is at its
worst and the theoretical minimum lock-up
time is not achievable. We must simply wait
for the transient to die out.
The following expressions give the values of
C2 and C3 which allow highest operating
speeds for various band center frequencies.
The minimum rate at which digital information
may be detected without information loss due
to the turn-on transient or output chatter is
about 10 cycles per bit, corresponding to an
information transfer rate of fo/10 baud.

AL

'01(

C3

•

A.
2OCITO
'K

-::-

Figure 4

.v

d
LOWERSf o

Ie,
'v

SIl.ICON
}

DIODES

FOR

TEMPERATURE
COMPENSATION

In cases where turn-off time can be sacrificed
to achieve fast turn-on, the optional sensitivity
adjustment circuit can be used to move the
quiescent C3 voltage lower (closer to the
threshold voltage). However, sensitivity to
beat frequencies, noise and extraneous signals will be increased.

OPTIONAL CONTROLS (Figure 3)
The 567 has been designed so that, for most
applications, no external adjustments are required. Certain applications, however, will be
greatly facilitated if full advantage is taken of
the added control possibilities available
through the use of additional external components. In the diagrams given, typical values
are suggested where applicable. For best
results the resistors used, except where noted, should have the sams temperature coefficient. Ideally, silicon diodes would be lowresistivity types, such as forward-biased tran-

November 5, 1986

(Of"TIONAL)

Figure 5
sistor base-emmitter junctions. However, ordinary low-voltage diodes should be adequate for most applications.

SENSITIVITY ADJUSTMENT
(Figure 3)
When operated as a very narrow-band detector (less than 8 percent), both C2 and C3 are
made quite large in order to improve noise
and out-band signal rejection. This will inevitably slow the response time. If, however, the
output stage is biased closer to the threshold
level, the turn-on time can be improved. This
is accomplished by drawing additional current
to terminal 1. Under this condition, the 567

4-320

will also give an output for lower-level signals
(10mV or lower).
By adding current to terminal 1, the output
stage is biased further away from the threshold voltage. This is most useful when, to
obtain maximum operating speed, C2 and C3
are made very small. Normally, frequencies
just outside the detection band could cause
false outputs under this condition. By desensitizing the output stage, the out-band beat
notes do not feed through to the output
stage. Since the input level must be somewhat greater when the output stage is made
less sensitive, rejection of third harmonics or
in-band harmonics (of lower frequency signals) is also improved.

Signetics Linear Products

Product Specification

NEjSE567

Tone DecoderjPhase-Locked Loop

DETECTION BANO -

% of '0

"

V'

".
PI~6~ ~r--W"""--S

i Aa

RaRe

the AC components at the quadrature phase
detector (lock detector) output cause the
output stage to move through its threshold
more than once. Many loads, for example
lamps and relays, will not respond to the
chatter. However, logic may recognize the
chatter as a series of outputs. By feeding the
output stage output back to its input (Pin 1)
the chatter can be eliminated. Three
schemes for doing this are given in Figure 4.
All operate by feeding the first output step
(either on or off) back to the input, pushing
the input past the threshold until the transient
conditions are over. It is only necessary to
assure that the feedback time constant is not
so large as to prevent operation at the
highest anticipated speed. Although chatter
can always be eliminated by making C3 large,
the feedback circuit will enable faster operation of the 567 by allowing C3 to be kept
small. Note that if the feedback time constant
is made quite large, a short burst at the input
frequency can be stretched into a long output
pulse. This may be useful to drive, for example, stepping relays.

A=AA+--

NOTE:

t
i"C

r

Ae + Ac

OPTIONAL SiliCON
DIODES FOR
TEMPERATURE
COMPENSATION

130( 10k+R )l00mV,I'M)

0---1
~~'.!'~NEL 0--7

Vo

OR RECEIVER

24% Bandwidth Tone Decoder

Dual-Tone Decoder
OUTl'UT
UNT01K
OHM MIN.
LOAD)

NOTES
R2"" R j /5
Adjust Rj so that ¢ = 90 Q with control midway.

0 0 to 1800 Phase Shifler
NOTES:
1. Resistor and capacitor values chosen for desired frequencies and bandwidth.
2. If Ca is made large so as to delay turn-on of the top 567, decoding of sequential ('1 '2) tones is possible.

November 5, 1986

4-323

Signetics Linear Products

Product Specification

NE/SE567

Tone Decoder/Phase-locked loop

TYPICAL APPLICATIONS (Continued)

567

.IU1IU" 2fo

567
8

567

6

J1J1

~~~M~
( :!:6%)

CONNECT PIN 3
TO 2.8V TO
INVERT OUTPUT

-

Oscillator With Quadrature Output

Oscillator With Double Frequency
Output

Precision Oscillator With 20ns
Switching

567

567
3

6

8-

OUTPUT

I

5

567
IOKll
~

IKnIMIN)

..n.ru

VCO
TERMINAL

1'6%)
RI
~

- Ie,
Pulse Generator With 25% Duty Cycle

November 5, 1986

DUTY
CYCLE
AOJUST

Precision Oscillator to Switch 100mA
Loads

4-324

Pulse Generator

Signetics

AN187
Circuit Description of the
NE567 Tone Decoder
Application Note

Linear Products

CIRCUIT DESCRIPTION OF THE
NE567 TONE DECODER
The NE56? is a PLL designed specifically for
frequency sensing or tone decoding. The
NE56? has a controlled oscillator, a phase
comparator and a second auxiliary or quadrature-phase detector. In addition, however, it
contains a power output stage which is driven
directly by the quadrature-phase detector output. During lock, the quadrature-phase detector drives the output stage on, so the device
functions as a tone decoder or frequency
relay. The tone decoder free-running frequency and bandwidth are specified by the free-

running frequency and capture range of the
loop portion. Since a tone decoder, by definition, responds to a stable frequency, the lock
or tracking range is relatively unimportant
except as it limits the maximum attainable
capture range. The complete circuit diagram
of the NE56? is shown in Figure 1.
The current-controlled oscillator is shown in
simplified form in Figure 2. It provides both a
square wave output and a quadrature output.
The control current Ie sweeps the oscillator
±?% of the free-running frequency, which is
set by external components R1 and C1.

4+V

Figure 1_ Circuit Diagram of NE567

February 198?

4-325

Transistors 0 1 through 06 form a flip-flop
which can switch Pin 5 between VSE and + V
-VSE. Thus, the R1C1 network is driven from
a square wave of + V -2VSE peak-to-peak
volts. On the positive portion of the square
wave, C1 is charged through R1 until V1 is
reached. A comparator circuit driven from C1
at Pin 6 then supplies a pulse which resets
the flip-flop so that Pin 5 switches to VSE and
C1 is discharged until V2 is reached. A second
comparator then supplies a pulse which sets
the flip-flop, and C1 resumes charging.

Signetics Linear Products

Application Note

Circuit Description of the NE567 Tone Decoder

The total swing of the capacitor voltage, as
determined by the comparator sensing voltages, is
V'-V2=(+V-2VSE)

= K(

+ V - 2VSE)

(1 )

Due to the excellent matching of integrated
resistors, the resistor ratio K may be considered constant. Figure 3 shows the Pin 5 and

Pin 6 voltages during operation. It is obvious
from the proportion that t, + t2 is independent
of the magnitude of + V and dependent only
on the time constant R,C, of the external
components. Moreover, if (V, + V 2)/2 = + VI
2, then t, = t2 and the duty cycle is 50%.
Note that the triangular waveform is phaseshifted from the square wave.
A differential stage (022 and 023) amplifies
the triangular wave with respect to (V, + V2)1
2 to provide the quadrature output. (Due to
the exponential distortion of the triangle
wave, the quadrature output is actually
phase-shifted about 80', but no operating

AN187

compromises result from this slight deviation
from true quadrature.)
One source of error in this oscillator scheme
is current drawn by the comparators from the
R,C, mode. An emitter-follower, therefore, is
inserted at X to minimize this drain and 02'
placed in series with 020 to drop the comparator sensing voltage one VSE to compensate
for the VSE drop in the emitter-follower.
In order to insure that the square wave drops
quickly and accurately to VSE, an active
clamp scheme is applied to the collector of
02. The base of 09 is held at 2V SE so that as
02 is turned on its base current, its collector

+vo--o~~--~--------~--------------------------------?-----,

••
0,

.,

COMPARATOR
Ql4-018

v,

COMPARATOR
024-028

V2

·'3

(EXT.)

·24

i

FLlP·FLOP

Figure 2. Simplified Diagram of NE567 Tone Decoder Current-Controlled Oscillator

+V-2VBE

1
/,--

r-

v~...

+V-VSE

/,'" ' ..... }

V,-V2",K(+V-2VSE)

.... V2

'---

~VBE

- - - PINS
_____
PIN6

Figure 3. Current-Controlled Oscillator Waveshapes in the NE567
February 1987

4-326

·'2

Signetics Linear Products

Application Note

AN187

Circuit Description of the NE567 Tone Decoder

is held at VSE. Because 02 and 03 have the
same geometry and their base-emitter voltages are the same, the maximum 02 current,
when clamped, is essentially the same as the
collector current of 03 (as limited by R5)' The
flip-flop was optimized for maximum switching
speed to reduce frequency drift due to switching speed variations.
Current control of the frequency is achieved
by making R21 somewhat less than R24 and
restoring the proper voltage for 50% duty
cycle by drawing Ie of 100/lA for the R21 , 0 20
junction. When Ie is then varied between 0
and 200/lA, the frequency changes by ± 7%.
Because of the slight shift in the voltage
levels VI and V2 with Ie, the square wave duty
cycle changes from about 47% to about 53 %
over the control range. To avoid drift of freerunning frequency with temperature and supply voltage changes when Ie 0, Ie is also
made a function of + V -2VSE.

'*

A doubly balanced multiplier formed by 032
through 0 37 (Figure 1) functions as the phase
comparator. The input Signal is applied to the
base of 032· Transistors 034 - 037 are driven
by a square wave taken from the CCO at the
collector of 02. Phase comparator input bias
is provided by three diodes, 038 through 040,
connected in series, assuring good bias voltage matching from run to run. Emitter resistors R26 and R27, in addition to providing the
necessary dynamic range at the input, help
stabilize the gain over the wide temperature
range.
The loop DC amplifier is formed by 0 51 and
052' Having a current gain of 8, it permits
even a small phase detector output to drive
the CCO the full ± 7%. Therefore, full detection bandwidth can be obtained for any inband input signal greater than about
70mV RM S. However, the main purpose of
high loop gain in the tone decoder is to keep
the locked phase as close to rr/2 as possible
for all but the smallest input levels, since this
greatly facilitates operation of the quadrature
lock detector. Emitter-resistors R36 and R37
help stabilize the gain over the required
temperature range. Another function of the
DC amplifier is to allow a higher impedance
level at the low pass filter terminal (Pin 2) so
that a smaller capacitor can be used for a
given loop cutoff frequency. Once again,
emitter-resistors help stabilize the loop gain
over the temperature range.
The quadrature-phase detector (OPD),
formed by a second doubly-balanced multiplier 0 42 - 047 is driven from the quadrature
output (E, F, in Figure 1) of the CCO. The
signal input comes from the emitters of the
input transistors 032 and 0 33 ,

February 1987

The output stage, 053 through 062, compares
the average OPD current in the low pass
output filter R3C3 with a temperature-compensated current in R39 (forming the threshold voltage VI)'
Since R3 is slightly lower in value than R39,
the output stage is normally off. When the
lock and the OPD current Iq occurs, Pin 1
voltage drops below the threshold voltage Vt
and the output stage is energized.
The uncommitted collector (Pin 8) of the
power NPN output transistor can drive both
100 - 200mA loads and logic elements, including TIl.
The Ko conversion gain for the NE567 tone
decoder is given by
radians)
volt-sec

Ko = 0.44wo' ( - - -

(2)

while the Kd conversion gain depends upon
the input signal level as shown in Figure 4.
These parameters can be used to calculate
the lock and capture range as has been
illustrated previously.
The NE567 tone decoder is a specialized
loop which can be setup to respond to a
given tone (constant frequency) within its
bandwidth. The free-running frequency is set
by a resistor RI and capacitor CI' The bandwidth is controlled by the low-pass filter
capacitor C2. A third capacitor C3 integrates
the output of the quadrature-phase detector
(OPD) so that the DC lock-indicating component can switch the power output stage on
when lock is present. The NE567 is optimized
for stability and predictability of free-running
frequency and bandwidth.

must achieve lock. Second, the output capacitor C3 must charge sufficiently to activate the
output stage. For minimum response time,
these events must be as brief as possible.
As previously discussed, the lock time of a
loop can be minimized by reducing the response time of the low-pass filter. Thus, C2
must be as small as possible. However, C2
also controls the bandwidth. Therefore, the
response time is an inverse function of bandwidth as shown by Figure 5, reprinted from
the NE567 data sheet. The upper curve
denotes the expected worst-case response
time when the bandwidth is controlled solely
by C2 and the input amplitude is 200mVRMS
or greater. The response time is given in
cycles of free-running frequency. For example, a 2% bandwidth at a free-running frequency of 1000 cycles can require as long as
280 cycles (280ms) to lock when the initial
phase relationship is at its worst. Figure 6
gives a typical distribution of response time
versus input phase. Note that, assuming random initial input phase, only 39'180 = Y6 of the
time will the lock-up time be longer than half
the worst-case lock-up time. Figure 7 shows
some actual measurements of lock-up time
for a setup having a worst-case lock-up time
of 27 cycles and a best-case lock-up time of
four input cycles.
The lower curve on the graph of Figure 5
shows the worst-case lock-up time when the
loop gain is reduced as a means of reducing
the bandwidth (see data sheet, Alternate
Method of Bandwidth Reduction). The value
of C2 required for this minimum response time
is
C2 (min)

Two events must occur before an output is
given. First, the loop portion of the NE567

130 [10k + RA ]
=t;;;R;:- J-lF

(3)

..

VOlTS/RAD

v

,

...
...

....

V

V'
517.ptN2

·tii

Y

50

, ..

)

1M'UT

MV-HIIS

... 1000

Figure 4. Phase Comparator Conversion Gain. Kd. for the NESS7 Tone Decoder

4-327

•

Signetics linear Products

Application Note

AN187

Circuit Description of the NE567 Tone Decoder

,000

/

'\.

'\

"r\

:'\

"

"~

/

~ ....OW'DTH".".D.V,c,_

50

I

BANDWIOTH uMl'n::D

~

"-

3

4

5

-

I--

..

r'N'fjC2) '\

EXrRNAL RESISTOR

2

20

3D 40 50

/

'00

'"

~

• 80

/

±to

t120

t150

tl •

BANDWIDTH (% of t'o)

Figure 5. Greatest Number of Cycles Before
Output for the NE567 Tone Decoder

Figure 6. Lock-Up Time vs Initial
Phase for the NES67 Tone Decoder

Figure 7. Lock-Up Time Variation Due to Random Initial
Phase for the NES67 Tone Decoder

Figure 8. Lock-Up Transient Response
for NES67 Tone Decoder

It is important to note that noise immunity and
rejection of out· band tones suffer somewhat
when this minimum value of C2 is used so
that response time is gained at their expense.
Except at very low input levels, input ampli·
tude has only a minor effect on the lock·up
time - usually negligible in comparison to the
variation caused by input phase.
Lock·up transients can be displayed on a twochannel scope with case. Figure 8 shows the
display which results. The top trace shows
the square wave which either gates the input
generator signal off and on (or shifts the
frequency in and out of the band if you have a
generator which has a frequency control input
only). The lower trace shows the voltage at
Pin 2, the low-pass filter voltage. The input
frequency is offset slightly from the freerunning frequency so that the locked and
unlocked voltages are different. It is apparent
February 1987

that, while the C2 decay during unlock is
always the same, the lock transient is different each time.
This is because the turn-on repetition rate is
such that a different initial phase relationship
occurs with each appearance of the in-band
signal. It is tempting to adjust the repetition
rate so that a fast, constant lock-up transient
is displayed. However, in doing so, a favorable initial phase is created that is not present
in actual operation. On the contrary, it is most
realistic to adjust the repetition rate so that
the longest lock-up time is displayed, such as
the fifth lock transient shows. Once this
display is achieved, the effect of various
adjustments in C2 or input amplitude is seen.
However, the repetition rate must be readjusted for worst-case lock-up after each such
change.

4-328

Once lock is achieved, the quadrature-phase
detector output at Pin 1 is integrated by C3 to
extract the DC component. As C3 charges
from its quiescent value Vq (see Figure 9) to
its final value (Vq • eN), it passes through the
output stage threshold, turning it on. The total
voltage change is a function of input amplitude. Since the unadjusted Vq is very close
(within 50mV) to VI> the output stage turns on
very soon after lock. Only a small fraction of
the output stage time constant (T = 4700C3)
expires before Vt is crossed so that C3 does
not greatly influence the response time. However, as shown in Figure 9a, the turn-off delay
time can be quite long when C3 is large.
Figure 9b shows how desensitizing the output
stage by connecting a high-value resistor
between Pin 1 and Pin 4 (positive supply
voltage) can equalize the turn-on and turn-off
time. If turn-off delay is important in the

Signetics linear Products

Application Note

Circuit Description of the NE567 Tone Decoder

AN187

b.
UNLOCK

LOCK

V

q

Vt

-+.I

I

___

----I

,,
I

I

--------1c.

"""'''''''''''''-I'-. '

v .....

,:m
-l ~RN-ON

~----------~I--~
DelAY

-.1,

IT~ELAY

L,;,RN-OFF

d.

a. Vq Slightly Greater Than VI

e.
LOCK

UNLOCK

I
I
Vq _ _ _...
Vt

I

---I

I
I
-------1"

,
,I
,,I m'--------I....II
-J, ~N-ON
~
DELAY

hURN-OFF
DELAY

b. Vq Much Greater Than VI
Figure 9. Effect of Threshold Voltage Adjustment on
Tone Decoder Turn-On and Turn-Off Delay
overall response time. then desensitizing can
reduce the total delay.
But why not make C3 very small so that these
delays can be totally neglected? The problem
here is that the QPO output has a large
second harmonic component of the freerunning frequency that must be filtered out.
Also. noise, out-band signals, and difference
frequencies formed by close out-band frequencies beating with the VCO frequency
appear at the QPO output. All these must be
attenuated by C3 or the output stage will
chatter on and off as the threshold is approached. The more noisy the input signal
and the larger the near-band signals, the
greater C3 must be to reject them. Thus,
there is a complicated relationship between
the input spectrum and the size of C3. What

February 1987

must be done, then, is to make C3 more than
sufficient for proper operation (no false outputs or missed signals) under actual operating conditions and then reduce its value in
small steps until either the required response
time is obtained or operation becomes unsatisfactory.
In setting up the tone decoder for maximum
speed, it is best to proceed as follows:
a. After the center frequency has been set,
adjust C2 to give the desired bandwidth
or, if the graph of response time in cycles
(Figure 7) suggests that worst-case lockup time will be too long, incorporate the
loop gain reduction scheme as an alternate means of bandwidth reduction (see
data sheet).

4-329

Check lock-up time by observing the
waveform at Pin 2 while pulsing the input
signal on and off (or in and out of the
band when a FM generator is used).
Adjust repetition rate to reveal worst lockup time.
Starting with a large value of C3 (say 10
C2), reduce it as much as possible in
steps while monitoring the output to be
certain that no false outputs or missed
signals occur. The full input spectrum
should be used for this test. Ignore brief
transients or chatter during turn-on and
turn-off as they can be eliminated with
the chatter prevention feedback technique described in the data sheet.
Use the desensitizing technique, also
described in the data sheet, to balance
turn-on and turn-off delay.
Apply the chatter prevention technique to
clean up the output.

If this procedure results in a worst-case
response time that is too slow, the following
suggestions may be considered:
a. Relax the bandwidth requirement.
b. Operate the entire system at higher frequency when this option is available.
c. Use two tone decoders operating at
slightly different frequencies and OR the
outputs. This will reduce the statistical
occurrence of the worst-case lock-up
time so that excessive lock-up time occurs. For example, if the lock-up time is
marginal 10% of the time with one unit, it
will drop to 1% with two units.
d. Control the in-band input amplitude to
stabilize the bandwidth, set up two tone
decoders for maximum bandwidth, and
overlap the detection bands to make the
desired frequency range equal to the
overlap. Since both tone decoders are on
only when a tone appears within the
overlap range, the outputs can be AN Oed
to provide the desired selectivity.
e. If the system design permits, send the
tone to be detected continuously at a low
level (say 25mVRMS) to keep the loop in
lock at all times. The output stage, slightly desensitized, can then be gated on as
required by increaSing the signal amplitude during the on time. Naturally, the
signal phase should be maintained as the
amplitude is changed. This scheme is
extremely fast, allowing repetition rates
as fast as 1'3 to 1'2 the free-running
frequency when C3 is small. This is equivalent to ASK (amplitude shift keying).

II',
~

......•

,.

Signetics

AN188
Selected Circuits Using the
NE567
Application Note

Linear Products

Touch-Tone@ Decoder
Touch-Tone® decoding is of great interest
since all sorts of remote control applications
are possible if you make use of the encoder
(the pushbutton dial) that will ultimately be
part of every phone. A low cost decoder can
be made as shown in Figure 1. Seven 567
tone decoders, their inputs connected in
common to a phone line or acoustical coupler, drive three integrated NOR gate packages. Each tone decoder is tuned, by means
of R1 and C" to one of the seven tones. The
R2 resistor reduces the bandwidth to about
8% at 100mV and 5% at 50mVRMS. Capacitor C4 decouples the seven units. The seven
R2 resistors and capacitor C4 can be eliminated at the expense of a somewhat slower
response at low input voltages (50 to
1OOmVRMS). The bandwidth can be controlled
in the normal manner by selecting C2 to be
4.7 JJ.F for the three lower frequencies and
2.2JJ.F for the four higher frequencies.

t=:---r-;:::==tr~-[-)-

The only unusual feature of this circuit is the
means of bandwidth reduction using the R2
resistors. An external resistor RA can be used
to reduce the loop gain and, therefore, the
bandwidth. Resistor R2 serves the same
function as RA except that instead of going to
a voltage divider for DC bias, it goes to a
common point with the six other R2 resistors.
In effect, the five 567s which are not being
activated during the decoding process serve
as bias voltage sources for the R2 resistors of
the two NE567s which are being activated.
Capacitor C4 decouples the AC currents at
the common point.

DIGIT

COMPONENT VALUES (TYPICAL)

R,
R2
R3

TONE DECODER APPLICATIONS
(NE567)

c,

C2
C3
C.

The NE567 is a special purpose PLL intended
solely for use as a tone decoder. It contains a
complete PLL including VCO, phase comparator, and amplifier as well as a quadraturephase detector of multiplier. If the signal
amplitude at the lock frequency is above a
minimal value, the driver amplifier turns on,
driving a load with as much as 200mA. Thus
the 567 gives an output whenever an in-band
tone is present. The 567 is optimized for both
free-running frequency and bandwidth stability.

Figure 1. Low Cost Touch-Tone®
®Touch-Tone is a registered trademark of Bell Laboratories.

February 1987

-,

'+.."....-++-~

4-330

6.8 to 15kn
4.7kn
2.0kn
O.1IlF
1.01lF 6V
2.21lF 6V
250llF 6V

De~';;'~:r

Signetics Linear Products

Application Note

Selected Circuits Using the NE567

AN188

OUTPUT

a. NORing Outputs Together
+v

+v

INPUT<>--7

b. Disabling the Second Decoder
Until Enabled by the First

c. Blocking Power to the Second
Decoder (Pin 7) Until the First

Figure 2. Detection of Two Simultaneous or Sequential Tones

Dual-Tone Decoder
Two 567 tone decoders connected as shown
in Figure 2a perrnit decoding of simultaneous
or sequential tones. Both units must be on
before an output is given. Rj Cj and Rj' Cj'
are chosen respectively for tones 1 and 2. If
sequential tones (tone 1 followed by tone 2)
are to be decoded, then C3 is made very large
to delay turn off of unit 1 until unit 2 has
turned on and the NOR gate is activated.
February 1987

Note that the wrong sequence (tone 2 fol·
lowed by tone 1) will not provide an output
since unit 2 will turn off before unit 1 comes
on. Figure 2b shows a circuit variation which
eliminates the NOR gate. The output is taken
from unit 2, but the unit 2 output stage is
biased off by Ru and Dj until activated by
tone 1. A further variation is given in Figure
2c. Here, unit 2 is turned on by the unit 1
output when tone 1 appears, reducing the

4-331

standby power to half. Thus, when unit 2 is
on, tone 1 is or was present. If tone 2 is now
present, unit 2 comes on also and an output
is given. Since a transient output pulse may
appear during unit 1 turn on, even if tone 2 is
not present, the load must be slow in reo
sponse to avoid a false output due to tone 1
alone.

Application Note

Signetics Linear Products

AN188

Selected Circuits Using the NE567

High-Speed, Narrow-Band Tone
Decoder
The circuit of Figure 2a may be used to obtain
a fast, narrow-band tone decoder. The detection bandwidth is achieved by overlapping the
detection bands of the two tone decoders.
Thus, only a tone within the overlap portion
will result in an output. The input amplitude
should be greater than 70mVRMS at all times
to prevent detection band shrinkage and C2
should be between 130/fo and 1300/fOI'F
where fo is the nominal detection frequency.
The small value of C2 allows operation at the
maximum speed so that worst-case output
delay is only about 14 cycles.

ON
FREaueNCY

<>--1

INPUT
l00·1000mVrms

Low-Cost Frequency Indicator
Figure 3 shows how two tone decoders set
up with overlapping detection bands can be
used for a go/no-go frequency meter. Unit 1
is set 6% above the desired sensing frequency and unit 2 is at 6% below the desired
frequency. Now, if the incoming frequency is
within 13% of the desired frequency, either
unit 1 or unit 2 will give an output. If both units
are on, it means that the incoming frequency
is within 1% of the desired frequency. Three
light bulbs and a transistor allow low cost
read-out.

~O.13'S~O.13fS~

-.... FREQUENCY

Phase Modulator
If a phase-locked loop is locked onto a signal
at the free-running frequency, the phase of
the VCO will be 90· with respect to the input
signal. If a current is injected into the VCO
terminal (the low-pass filter output), the phase
will shift sufficiently to develop an opposing
average current out of the phase comparator
so that the VCO voltage is constant and lock
is maintained. When the input signal amplitude is low enough so that the loop frequency
swing is limited by the phase comparator
output rather than the VCO swing, the phase
can be modulated over the full range of 0 to
180·. If the input signal is a square wave, the
phase will be a linear function of the injected
current.

Figure 3. Low Cost Frequency Detector With Lamp Readout

j-------

-------~

J""'Lrt....f'Lveo-4-'----+
I
"i+K

OUTPUT I
I

I
I
IL ______________ JI

A block diagram of the phase modulator is
given in Figure 4a. The conversion factor K is
a function of which loop is used, as well as
the input square wave amplitude. Figure 4b
shows an implementation of this circuit using
the 567.

a. Block Diagram

J"1..J"'1....r

-

0---4"""",-+ +-,""""".....-0
33K

PHASE

CONTROLOA

MODULATtON

VOlTAGE

b. Circuit Implementation With the NE5S7
Figure 4. Phase Modulation Using the PLL

February 1987

4-332

NE568

Signetics

150MHz Phase-locked loop
Preliminary Specification

Linear Products
DESCRIPTION

FEATURES

The NE568 is a monolithic phase-locked
loop (PLL) which operates from 1Hz to
frequencies in excess of 150MHz. The
integrated circuit consists of a limiting
amplifier, a current-controlled oscillator
(ICO), a phase detector, a level shift
circuit, VII and IIV converters, an output
buffer, and bias circuitry with temperature and frequency compensating characteristics. The design of the NE568 is
particularly well-suited for demodulation
of FM signals with extremely large deviation in systems which require a highly
linear output. In satellite receiver applications with a 70MHz IF, the NE568 will
demodulate ± 10% deviations with less
than 4.0% non-linearity (1.5% typical). In
addition to high linearity, the circuit has a
loop filter which can be configured with
series or shunt elements to optimize
loop dynamic performance. The NE568
is available in 20-pin dual in-line and 20pin SO (surface-mounted) plastic packages.

• Operation to 150MHz
• High linearity buffered output
• Series or shunt loop filter
component capability
• Temperature compensated

PIN CONFIGURATION
D. N Packages

APPLICATIONS
•
•
•
•

Satellite receivers
Fiber-optic video links
VHF FSK demodulators
Clock recovery

lOPVlEW

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

o to
o to

20-Pin Plastic SOL Package
20-Pin Plastic DIP

ORDER CODE

+70°C

NE568D

+70°C

NE568N

BLOCK DIAGRAM
LF1

LF2

lF3

LF4

FREQADJ

OUTFILT

Vou,

TCADJ2

TCADJ1

V,N
11

10
GND2

February 1987

aND1

TCAP1

TCAP2

GND1

4-333

REFBYP

PNPBYP

INPBYP

Signetics linear Products

Preliminary Specification

NE568

150MHz Phase-Locked Loop

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

RATING

UNIT

Vee

Supply voltage

TA

Operating free-air ambient temperature range

TJ

Junction temperature

TSTG

Storage temperature range

-65 to + 150

°C

PDMAX

Maximum power dissipation

500

mW

ELECTRICAL
CHARACTERISTICS
The electrical characteristics listed below are
actual tests (unless otherwise stated) per-

6

V

o to +70

°C

+150

°C

formed on each device with an automatic IC
tester prior to shipment. Performance of the
device in automated test setup is not necessarily optimum. The NE568 is layout-sensitive.

Evaluation of performance for correlation to
the data sheet should be done with the circuit
and layout of Figures 1 - 3 with the evaluation
unit soldered in place. (Do not use a socke!!)

DC ELECTRICAL CHARACTERISTICS TA = 25°C, Vee = 5V, fa = 70MHz, Test Circuit Figure 1, fiN = -20dBm, R4 = On
(ground), unless otherwise specified.
LIMITS
SYMBOL

PARAMETER

TEST CONDITIONS

UNIT
Min

Vcc

Supply voltage

lee

Supply current

February 1987

4.75

4-334

Typ

Max

5

5.25

V

60

75

mA

Signetics Linear Products

Preliminary Specification

150MHz Phase-locked loop

NE568

AC ELECTRICAL CHARACTERISTICS
LIMITS
PARAMETER

SYMBOL

TEST CONDITIONS

UNIT
Min

fose

Maximum oscillator operating frequency3

1.5

mVp_p
dBm
MHz

fol7
Dev = ± 10%, Input = -20dBm
Dev=±20%,lnput=-20dBm
Dev=±20%,lnput=+10dBm

4.0
5.5
5.5

%

Lock range 2

Input = -20dBm

±25

±35

% of fa

Capture range 2

Input = -20dBm

±20

±30

% of fa

100

ppm/'C

Figure t

TC of fa
RIN

MHz
2000
+10

50
_20 1

Demodulated bandwidth

Non-linearity5

Max

150

Input signal level
BW

Typ

Input resistance 4

1

Output impedance
Demodulated VOUT

AM rejection

fa

Distribution 6

fa

Drift with supply

Dev = ± 20% of fa
measured at Pin 4

0.45

VIN = -20dBm (30% AM)
OdBm (30% AM)
referred to ± 20% deviation
Centered at 70MHz, R2 = 1.2kn,
C2 = 17pF, R4 = On
(C2 + CSTRAY = 20pF)
4.75V to 5.25V

-15

kn

6

n

0.52

Vp_p

30
50

dB

0
1

+15

%

%N

NOTES:
1. Signal level to assure all published parameters. Device will continue to function at lower levels with varying performance.
2. Limits are set symmetrical to fa. Actual characteristics may have asymmetry beyond the specified limits.
3. Not 100% tested, but guaranteed by deSign.
4. Input impedance depends on package and layout capacitance. See Figures 4 and 5.
5. Linearity is tested with incremental changes in input frequency and measurement of the DC output voltage at Pin 14 (VOUT). Nonlinearity is then
calculated from a straight line over the deviation range specified.
6. Free-running frequency is measured as feedthrough to Pin 14 (VOUT) with no input signal applied.

February 1987

4-335

II',"
"

~

,

Signetics Linear Products

Preliminary Specification

NE568

150MHz Phase-locked loop

VCC2

lF1

GND2

lF2

GND1

lF3

C9

,*C1
-::-::-

TCAP1
FREQADJ

TCAP2
NE568
GND1

OUTFllT

vcc,
REPBYP

Vee

PNPBYP
INPBYP

f

C7

Figure 1. Test and Application Circuit

February 1987

4-336

R1

C10

Signetics Linear Products

Preliminary Specification

NE568

150MHz Phase-Locked Loop

FUNCTIONAL DESCRIPTION
The NE568 is a high-performance phaselocked loop (PLL). The circuit consists of
conventional PLL elements, with special circuitry for linearized demodulated output, and
high-frequency performance. The process
used has NPN transistors with fT> 6GHz.
The high gain and bandwidth of these transistors make careful attention to layout and
bypass critical for optimum performance. The
performance of the PLL cannot be evaluated
independent of the layout. The use of the
application layout in this data sheet and
surface-mount capacitors are highly recommended as a starting paint.
The input to the PLL is through a limiting
amplifier with a gain of 200. The input of this
amplifier is differential (Pins 10 and 11). For
single-ended applications, the input must be
coupled through a DC-blocking capacitor with
low impedance at the frequency of interest.
The single-ended input is normally applied to
Pin 11 with Pin 10 AC-bypassed with a lowimpedance capacitor. The input impedance is
characteristically slightly above 500n. Impedance match is not necessary, but loading the
signal source should be avoided. When the
source is 50 or 75n, a DC-blocking capacitor
is usually all that is needed.
Input amplification is low enough to assure
reasonable response time in the case of large
signals, but high enough for good AM rejection. After amplification, the input Signal
drives one port of a multiplier-cell phase
detector. The other port is driven by the
current-controlled oscillator (ICO). The output
of the phase comparator is a voltage proportional to the phase difference of the input and

February 1987

ICO signals. The error signal is filtered with a
low-pass filter to provide a DC-correction
voltage, and this voltage is converted to a
current which is applied to the ICO, shifting
the frequency in the direction which causes
the input and ICO to have a 90' phase
relationship.
The oscillator is a current-controlled multivibrator. The current control affects the chargel
discharge rate of the timing capacitor. It is
common for this type of oscillator to be
referred to as a voltage-controlled oscillator
(VCO), because the output of the phase
comparator and the loop filter is a voltage. To
control the frequency of an integrated ICO
multivibrator, the control signal must be conditioned by a voltage-to-current converter. In
the NE568, special circuitry predistorts the
control signal to make the change in frequency a linear function over a large controlvoltage range.
The free-running frequency of the oscillator
depends on the value of the timing capaCitor
connected between Pins 4 and 5. The value
of the timing capacitor depends on internal
resistive components and current sources.
When R2 = 1.2kn and R4 = on, a very close
approximation of the correct capacitor value
is:
0.0014
C'=-- F
fo
where
C' = C2 + CSTRAY.
The temperature-compensation resistor, R4,
affects the actual value of capacitance. This
equation is normalized to 70MHz. See Figure
6 for correction factors.

4-337

The loop filter determines the dynamic characteristics of the loop. In most PLLs, the
phase detector outputs are internally connected to the ICO inputs. The NE568 was
designed with filter output to input connections from Pins 20 (¢ DET) to 17 (ICO), and
Pins 19 (¢ DET) to 18 (ICO) external. This
allows the use of both series and shunt loopfilter elements. The loop constants are:
KD

= 0.127VIRadian

(Phase Detector

Constant)
Radians
Ko = 4.2 X log - - - (ICO Constant)
V-sec
The loop filter determines the general characteristics of the loop. CapaCitors Cg, C10 , and
resistor R1, control the transient output of the
phase detector. Capacitor Cg suppresses
70MHz feedthrough by interaction with 100n
load resistors internal to the phase detector.

2" (50)(fo)

F

At 70MHz, the calculated value is 45pF.
Empirical results with the test and application
board were improved when a 56pF capacitor
was used.
The natural frequency for the loop filter is set
by C10 and R1. If the center frequency of the
loop is 70MHz and the full demodulated
bandwidth is desired, i.e., fsw = fol7
= 10MHz, and a value for R1 is chosen, the
value of C10 can be calculated.

•
~

•

c.

..

Preliminary Specification

Signetics Linear Products

150MHz Phase-Locked Loop

NE568

PARTS LIST AND LAYOUT 70MHz APPLICATION NE568D
C1

100nF

±10%

Ceramic chip

1206
0805

C2 1

18pF

±2%

Ceramic chip

ci

34pF

±2%

Ceramic OR chip

C3

100nF

±10%

Ceramic chip

1206

C4

100nF

±1O%

Ceramic chip

1206

C5

6.8"F

±10%

Tantalum

35V

C6

100nF

±10%

Ceramic chip

1206
1206

C7

100nF

±10%

Ceramic chip

Ca

100nF

±10%

Ceramic chip

1206

Cg

56pF

±2%

Ceramic chip

0805 or 1206

C10

560pF

±2%

Ceramic chip

0805 or 1206

C11

47pF

±2%

Ceramic chip

0805 or 1206

C12

100nF

±10%

Ceramic chip

1206

C 13

100nF

± 10%

Ceramic chip

1206

±10%

R1

27n

R2

2kn

Chip

YaW

Trim pot

R3 3

43n

YaW

±10%

Chip

R4 4

YaW

4.5kn

±10%

Chip

YaW

R53

50n

±10%

Chip

YaW

RFC15

10"ft

±10%

Surface mount

RFC25

10"H

±10%

Surface mount

NOTES:
1. C 2 + CSTRA Y - 20pF.
2. C2 + eSTRAY = 36pF for temperature-compensated configuration with R4 = 4.5kn.
3. For son setup. R, - 62n, R3 - 7Sn for 7Sn application.
4. For test configuration R4 (GNO) and C2 - 18pF.
5. On chip resistors Gumpers} may be substituted with minor degradation of performance.

On

a. Component Side Top of Board

For the test circuit, R1 was chosen to be 27n.
The calculated value of C10 is 590pF; 560pF
was chosen as a production value. (In actual
satellite receiver applications, improved video
with low carrier/noise has been observed
with a wider loop-filter bandwidth.)
A typical application of the NE568 is demodulation of FM signals. In this mode of operation, a second single-pole filter is available at
Pin 15 to minimize high frequency feedthrough to the output. The roll-off frequency is
set by an internal resistor of 350n ± 20%,
and an external capacitor from Pin 15 to
ground. The value of the capacitor is:

C=

1
21T (350)fBW

Two final components complete the active
part of the circuitry. A resistor from Pin 12 to
ground sets the temperature stability of the
circuit, and a potentiometer from Pin 16 to
ground permits fine tuning of the free-running
oscillator frequency. The Pin 16 potentiometer is normally 1.2kn. Adjusting this resistance controls current sources which affect
the charge and discharge rates of the timing
capacitor and, thus, the frequency. The value
of the temperature stability resistor is chosen
from the graph in Figure 6.
The final consideration is bypass capacitors
for the supply lines. The capacitors should be
ceramic chips, preferably surface-mount
types. They must be kept very close to the
device. The capacitors from Pins 8 and 9
return to VCCI before being bypassed with a
separate capacitor to ground. This assures
that no differential loops are created which
might cause instability. The layouts for the
test circuits are recommended.

b. Back of Board

NOTES:
1. Board is laid out for King BNG Connector PIN KC-79-243-M06 or equivalent. Mount on bottom (back) of board. Add stand-off in each corner.
2. Back and top side ground must be connected at 8 pOint minimum.

Figure 2

February 1987

4-338

F

Signetics Linear Products

Preliminary Specification

150MHz Phase-Locked Loop

NE568

PARTS LIST AND LAYOUT 70MHz APPLICATION NE568N
C,

100nF

±10%

Ceramic chip

50V

C2'

17pF

±2%

Ceramic OR chip

50V

C22

34pF

±2%

Ceramic chip

0805

C3

100nF

±10%

Ceramic chip

50V

C4

100nF

±10%

Ceramic chip

50V

Cs

6.8iJF

±10%

Tantalum

35V

Ce

100nF

± 10%

Ceramic OR chip

50V

C7

100nF

±10%

Ceramic chip

50V

Ce

100nF

±10%

Ceramic chip

50V

Cg

56pF

±2%

Ceramic chip

50V

C,o

560pF

±2%

Ceramic chip

50V

Cn

47pF

±2%

Ceramic OR chip

50V

C'2

100nF

± 10%

Ceramic OR chip

50V

C'3

100nF

±10%

Ceramic OR chip

50V

R,

27n

±10%

Carbon

hw

R2

2kn

Trim pot

R33

43n

±10%

Carbon

R4 4

4.5kn

±10%

Carbon

V4W

RS3

50n

±10%

Carbon

V4W

RFC,

10iJH

±10%

RFC2

10iJH

±10%

V4W

NOTES:

1. C 2 + CSTRAY ~ 20pF for test configuration with R4 ~ On.
2. C2 ~ 34pF for temperature·compensated configuration with R4 ~ 4.5k'1
3. For 50n setup. R, ~ 62n; R3 ~ 75n for 75n applications.
4. For test configuration R. ~ on (GND) and C2 - 17pF.

.
.
••
,.... ••

• •

.;..

-

~:

..

~&~
mnm··. o

I ~,

I

• •-..::."•
I __• e

::1V ...

...

~

&III

a. Component Side for Leaded Components

b. Solder Side of Board and Chip Capacitors

NOTES,
1. Board is laid out for King BNC Connector PIN KC-79-243-MOS or equivalent mounted on the component side of the board.
2. Component side and solder side ground planes must be connected at 8 points minimum.

Figure 3

February 1987

4-339

Signetics Linear Products

Preliminary Specification

NE568

150MHz Phase-Locked Loop

1.2SE3

1.25ES

150.0

Z'N \

w

~

\.

!:j 500.0

500.0

'\

~

250.0

0.0
1.0

80

76.29

75
1:i' 73.11

i 70.60
o 70
~ 68.09
66.09
65
64.46
63.0

60
1.05

rZ

C,=47pF

-[

3k

lk

'~

o Y
o

/

-

/V

V

/

VI-

2k C,=IJPF

C,=80pF

-I 1

10 20 30 40 50 60 70 80 90 100

Rro (PIN 12) Y. '.

FREQUENCY (MHz)

Figure 5. NE568 Input Impedance With
CP = 1.49pF 20-Pin Dual In-Line Plastic
Package

Figure 6

4.0

II\,

"

'\J

3.5

"'"' "

~IJl-\
~

-........
2.5

1.15

II

'J

3.0

1.20 1.25 1.30 1.35 1.40
FREQ. ADJ (kQ)
71.64 69.71 67.26 64.54 62.06 59.70 57.55 55.S3
1.10

~

0.0 ' - - - - - - ' - - - - - ' - - - - ' =
1.0
10.0
100.0
1.0ES

PINI2=GND

"

~

z

1-----1----4.....".~,..
..-...-..-..--1
...

C2~17PFI

"

~ 4k

V

C,~34~F

5k

\.[\
250.0

Figure 4. NE568 Input Impedance With
CP = O.5pF 20-Pin SO Package

78.72

6k

1-----1----\.:-\1-----;

>

"

100.0
10.0
FREQUENCY (MHz)

7k

~ ::: ~~~::~~::.~:
...~\:\~.S-Z,-"N-l-----l
ii:l
RI~\\

1.0E3

i

r-----,---.....,.----,

o

10 20 30 40 50 60 70 80 90 100 110 120
TYPICAL OUTPUT LINEARITY

lcc(mA)

·27.33 ·27.44 ·27.56 ·27.63 ·28.10 ·28.50 ·28.97 ·29.48
veo LEVEL (dBm)

Figure 7. Typical Vco Frequency vs R2 Adjustment

February 1987

Figure 8. Typical Output Linearity

4-340

AN174

Signetics

Applications for Compandors:

NE570/571/SA571
Application Note

Linear Products

APPLICATIONS
The following circuits will illustrate some of
the wide variety of applications for the
NE570.

BASIC EXPANDOR
Figure 1 shows how the circuit would be
hooked up for use as an expandor. Both the
rectifier and AG cell inputs are tied to Y,N so
that the gain is proportional to the average
value of (V,N). Thus, when Y'N falls 6dB, the
gain drops 6dB and the output drops 12dB.
The exact expression for the gain is

.

Gain expo =

Ie

[2

2

R3 V IN (avg) ]
;
R1 R2 Ie

= 14011A

The maximum input that can be handled by
the circuit in Figure 1 is a peak of 3V. The
rectifier input current can be as large as
1= 3VIR 1 = 3VI10k = 300j.lA. The AG cell
input current should be limited to I = 2.BV I
R2 = 2.BV 120k = 1401lA. If it is necessary to
handle larger input voltages than 0 ± 2.BV
peak, external resistors should be placed in
series with R1 and R2 to limit the input current
to the above values.
Figure 1 shows a pair of input capacitors C'N1
and C,N2. It is now necessary to use both
capacitors if low level tracking accuracy is not
important. If R1 and R2 are tied together and

share a common capacitor, a small current
will flow between the AG cell summing node
and the rectifier summing node due to offset
voltages. This current will produce an error in
the gain control signal at low levels, degrading tracking accuracy.
The output of the expandor is biased up to 3V
by the DC gain provided by R3, R4 . The
output will bias up to
VOUT

R3
DC = (1+-)
R4

VREF

For supply voltages higher than 6V, R4 can
be shunted with an external resistor to bias
the output up to hvcc.
Note that it is possible to externally increase
R1, R2, and R3, and to decrease R3 and R4.
This allows a great deal of flexibility in setting
up system levels. If larger input signals are to
be handled, R1 and R2 may be increased; if a
larger output is required, R3 may be increased. To obtain the largest dynamic range
out of this circuit, the rectifier input should
always be as large as possible (subject to the
± 30011A peak current restriction).

BASIC COMPRESSOR
Figure 2 shows how to use the NE570/571 as
a compressor. It functions as an expandor in
the feedback loop of an op amp. If the input
rises 6dB, the output can rise only 3dB. The
3dB increase in output level produces a 3dB
increase in gain in the AG cell, yielding a 6dB

increase in feedback current to the summing
node. Exact expression for gain is
.
Gain compo

=

[

R1 R2 Is
] Y2
2 R3V'N (avg)

The same restrictions for the rectifier and AG
cell maximum input current still hold, which
place a limit on the maximum compressor
output. As in the expandor, the rectifier and
AG cell inputs could be made common to
save a capacitor, but low level tracking accuracy would suffer. Since there is no DC
feedback path around the op amp through
the AG cell, one must be provided externally.
The pair of resistors Roc and the capacitor
CDC must be provided. The op amp output will
bias up to
VOUT

DC = (1

2RDC

+ Fi4)

VREF

For the largest dynamic range, the compressor output should be as large as possible so
that the rectifier input is as large as possible
(subject to the ± 30011A peak current restriction). If the input signal is small, a large output
can be produced by reducing R3 with the
attendant decrease in input impedance, or by
increasing R1 or R2. It would be best to
increase R2 rather than R1 so that the rectifier
input current is not reduced.

R,

AOC

~ CRECT
~
ROC

\lOUT

VOUT

A.

"REF

+

Figure 2. Basic Compressor

DISTORTION TRIM
Distortion can be produced by voltage offsets
in the AG cell. The distortion is mainly even
harmonics, and drops with decreasing input
signal (input signal meaning the current into
the AG cell). The THD trim terminal provides

Figure 1. Basic Expandor
February 19B7

4-341

Application Note

Signetics Linear Products

AN174

Applications for Compandors: NE570j571jSA571

Vee

'2.

".

r--------,.

Rs will supply an extra current to the rectifier
equal to (VCC - 1.3V)R s. In this case, the
expandor transfer characteristic will deviate
towards l-to-I at low levels. At low levels the
expandor gain will stop dropping and the
expansion will cease. In a compressor, this
would lead to a lack of compression at low
levels. Figure 6 shows some typical transfer
curves. An Rs value of approximately 2.5M
would trim the low level tracking so as to
match the Bell system N2 trunk compandor
characteristic.

3.6V

UK

o

'M

To THO Trim

..

20K

±_,oo,'

...

Figure 3. THO Trim Network
a means for trimming out the offset voltages
and thus trimming out the distortion. The
circuit shown in Figure 3 is suitable, as would
be any other capable of delivering ± 30iJA
into 100n resistor tied to I.BV.

-20 -10
0
+10
EXPANDOR INPUT LEVEL dB OR
COMPRESSOR OUTPUT LEVEL

It is possible to deviate from the 2-to-l
transfer characteristic at low levels as shown
in the circuit of Figure 4. Either RA or Rs, (but
not both), is required. The voltage on GRECT
is 2 X VSE plus VIN avg. For low level inputs
VIN avg is negligible, so we can assume 1.3V
as the bias on GRECT. If RA is placed from
GRECT to AND we will bleed off a current

I = 1.3VIRA. If the rectifier average input
current is less than this value, there will be no
gain control' input to the ':)'G cell so that its
gain will be zero and the expandor output will
be zero. As the input level is raised, the input
current will exceed 1.3VIRA and the expandor output will become active. For large input
signals, RA will have little effect. The result of
this is that we will deviate from the 2-to-l
expansion, present at high levels, to an infinite expansion at low levels where the output
shuts off completely. Figure 5 shows some
examples of tracking curves which can be
obtained. Gomplementary curves would be
obtained for a compressor, where at low level
signals the result would be infinite compression. The bleed current through RA will be a
function of temperature because of the two
VSE drops, so the low level tracking will drift
with temperature. If a negative supply is
R.

CIN1

~~

r----------.

o

~10

EXPANDOR INPUT LEVEL dB OR
COMPRESSOR OUTPUT LEVel

Figure 6. Mistracking With RB

RECTIFIER BIAS CURRENT
CANCELLATION
The rectifier has an input bias current of
between 50 and 100nA. This limits the dynamic range of the rectifier to about 60dS. It
also limits the amount of attenuation of the
':)'G cell. The rectifier dynamic range may be
increased by about 20dS by the bias current
trim network shown in Figure 7. Figure B
shows the rectifier performance with and
without bias current cancellation.

ATTACK AND DECAY TIME

·{.1----'\f,2

The attack and decay times of the compandor are determined by the rectifier filter time
constant 10k X GRECT. Figure 9 shows how
the gain will change when the input signal
undergoes a 10, 20, or 30dB change in level.

Figure 4. Expandor With Low Level Mistracking
February 1987

'2.
"0

Figure 5. Mistracklng With RA

LOW LEVEL MISTRACKING
The compandor will follow a 2-to-l tracking
ratio down to very low levels. The rectifier is
responsible for errors in gain, and it is the
rectifier input bias current of < 100nA that
produces errors at low levels. The magnitude
of the error can be estimated. For a full-scale
rectifier input signal of ± 200"A, the average
input current will be 127iJA. When the input
signal level drops to a 1"A average, the bias
current will produce a 10% or 1dB error in
gain. This will occur at 42dB below the
maximum input level.

available, if would be desirable to tie RA to
that, rather than ground, and to increase its
value accordingly. The bleed current will then
be less sensitive to the VSE temperature drift.

4-342

The attack time is much faster than the
decay, which is desirable in most applications. Figure 10 shows the compressor attack
envelope for a + 12dB step in input level. The
initial output level of I unit instantaneously
rises to 4 units, and then starts to fall towards

Signetics Linear Products

Application Note

AN174

Applications for Compandors: NE570j571jSA571

15V

:t

3301(

k::---1
o

3.6'V

2

4

6

8

10

TIME CONSTANTS

12

'4

16

18

lOKe REer

10MEG
~100K

Figure 11. Compressor Release
Envelope -12dB Step

TO RECTIFIER
INPUT
PIN 2 OR 15

Figure 7. Rectifier Bias Current
Compensation

ftECTIf"fR INPUT LEVEL, dill'll

Figure 8. Rectifier Performance With
Bias Current Compensation

7

8

9

10

its final value of 2 units. The CCITT recommendation on attack and decay times for
telephone system compandors defines the
attack time as when the envelope has fallen
to a level of 3 units, corresponding to t = 0.15
in the figure. The CCITT recommends an
attack time of 3 ± 2ms, which suggests an RC
product of 20ms. Figure 11 shows the compressor output envelope when the input level
is suddenly reduced 12dB. The output, initially
at a level of 4 units, drops 12dB to 1 unit and
then rises to its final value of 2 units. The
CCITT defines release time as when the
output has risen to 1.5 units, and suggests a
value of 13.5 ± 9ms. This corresponds to
t = 0.675 in the figure, which again suggests a
20ms RC product. Since R1 = 10k, the CCITT
recommendations will be met if GRECT = 2j.lF.
There is a trade-off between fast response
and low distortion. If a small CRECT is used to
get very fast attack and decay, some ripple
will appear on the gain control line and
produce distortion. As a rule, a 1j.lF CRECT will
produce 0.2% distortion at 1kHz. The distortion is inversely proportional to both frequency and capacitance. Thus, for telephone applications where CRECT = 2j.lF, the ripple
would cause 0.1 % distortion at 1kHz and
0.33% at 800Hz. The low frequency distortion
generated by a compressor would be cancelled (or undistorted) by an expandor, providing that they have the same value of
GRECT·

TIME CONSTANTS - 10K CRECT

Figure 9. Gain vs Time Input Steps
of ± 10, ± 20, ± 30dB

!~E----I. .
o

1

2

3

..

5

,

TIME CONSTANTS' 10KeREer

Figure 10. Compressor Attack Envelope
+ 12dB Step

February 1987

FAST ATTACK, SLOW RELEASE
HARD LIMITER
The NE570/571 can be easily used to make
an excellent limiter. Figure 12 shows a typical
circuit which requires Y2 of an NE570/571, Y2
of an LM339 quad comparator, and a PNP
transistor. For small signals, the toG cell is
nearly off, and the circuit runs at unity gain as
set by Rs, R7. When the output signal tries to
exceed a + or -1 V peak, a comparator
threshold is exceeded. The PNP is turned on
and rapidly charges G4 which activates the
toG cell. Negative feedback through the toG
cell reduces the gain and the output signal
level. The attack time is set by the RG
product of R1s and G4, and the release time is
determined by G4 and the internal rectifier

4-343

resistor, which is 10k. The circuit shown
attacks in less than 1ms and has a release
time constant of lOOms. Rg trickles about
0.7 p.A through the rectifier to prevent C4 from
becoming completely discharged. The gain
cell is activated when the voltage on Pin 1 or
16 exceeds two diode drops. If C4 were
allowed to become completely discharged,
there would be a slight delay before it recharged to > 1.2V and activated limiting
action.
A stereo limiter can be built out of 1 NE5701
571, 1 LM339 and two PNP transistors. The
resistor networks R12, R13 and R14, R15,
which set the limiting thresholds, could be
common between channels. To gang the
stereo channels together (limiting in one
channel will produce a corresponding gain
change in the second channel to maintain the
balance of the stereo image), then Pins 1 and
16 should be jumpered together. The outputs
of all 4 comparators may then be tied together, and only one PNP transistor and one
capacitor C4 need be used. The release time
will then be the product 5k X C4 since two
channels are being supplied current from C4.

USE OF EXTERNAL OP AMP
The operational amplifiers in the NE570/571
are not adequate for some applications. The
slew rate, bandwidth, noise, and output drive
capability can limit performance in many systems. For best performance, an external op
amp can be used. The external op amp may
be powered by bipolar supplies for a larger
output swing.
Figure 13 shows how an external op amp may
be connected. The non-inverting input must
be biased at about 1.8V. This is easily accomplished by tying it to either Pin 8 or 9, the THO
trim pins, since these pins sit at 1.8V. An
optional RC decoupling network is shown
which will filter out the noise from the NE5701
571 reference (typically about 10j.lV in 20kHz
BW). The inverting input of the external op
amp is tied to the inverting input of the
internal op amp. The output of the external op
amp is then used, with the internal op amp
output left to float. If the external op amp is
used single supply (+ Vee and ground), it
must have an input common-mode range
down to less than 1.8V.

N2 COMPANDOR
There are four primary considerations involved in the application of the NE570/571 in
an N2 compandor. These are matching of
input and output levels, accurate 600n input
and output impedances, conformance to the
Bell system low level tracking curve, and
proper attack and release times.

Signetics Linear Products

Application Note

AN174

Applications for Compandors: NE570/571/SA571

2/4 LUau

112 .S70/571

OR LU3U

2.15

10K
0,

UMEG

...

R.

.000

R,

On

."'"
R,

."'"
R,

1,12

R,

100
7,10

-

A..

c:r::;
I"'"

A"

11.4l
+

IA'

OUT

+ 15V Pin 13
GND Pin 4
Rj, R2, R4 are internal to the NE570/571.

Figure 12. Fast Attack, Slow Release Hard Limiter

...

RGAINTRIM

'pF

Figure 13. Use of External Op Amp
Figure 14 shows the implementation of an N2
compressor. The input levei of O.245V RMS is
stepped up to 1.41 VRMS by the 600n: 20kn
matching transformer. The 20k input resistor
properly terminates the transformer. An internal
20kn resistor (Rs) is provided, but for accurate
impedance termination an external resistor
should be used. The output impedance is provided by the 4kn output resistor and the 4kn:
600n output transformer. The O.275VRMS output level requires a 1.4V op amp output level.
This can be provided by increaSing the value of
R2 with an external resistor, which can be
selected to fine trim the gain. A rearrangement
of the compressor gain equation (6) allows us to
determine the value for R2.
Gain 2 x 2 Rs VIN avg

R2=--------~~~~

R1 19
12 X 2 X 20k X 1.27
10k X 140!,A

ROUT

4.ok

Figure 14. N2 Compressor
The external resistance required will thus be
36.3k - 20k = 16.3k.

network around the op amp provides DC
feedback to bias the output at DC.

The Bell-compatible low level tracking characteristic is provided by the low level trim
resistor from CRECT to Vee. As shown in
Figure 6, this will skew the system to a 1:1
transfer characteristic at low levels. The 2!,F
rectifier capacitor provides attack and release
times of 3ms and 13.5ms, respectively, as
shown in Figures 10 and 11. The R-C-R

An N2 expandor is shown in Figure 15. The
input level of 3.27VRMS is stepped down to
1.33V by the 600n:100n transformer, which
is terminated with a 100n resistor for accurate impedance matching. The output impedance is accurately set by the 150n output
resistor and the 150n:600n output transformer. With this configuration, the 3.46V
transformer output requires a 3.46V op amp

= 36.3k

February 1987

4-344

Signetlcs Linear Products

Application Note

AN174

Applications for Compandors: NE570/571/SA571

R,20K

R GAIN TRIM

6000 loon

10K

327
VRMS
6000

loon

·,N

v cc --~M----1

•

Figure 15_ N2 Expandor

output. To obtain this output level, it is necessary to increase the value of R3 with an
external trim resistor. The new value of R3
can be found with the expandor gain equation
R3

~

Rl R2 Is Gain
--:--:--2 VIN avg
10k X 20k

x

140/IA X 2.6

2 X 1.20
~

30.3k

An external addition to R3 of 10k is required,
and this value can be selected to accurately
set the high level gain.
A low level trim resistor from CRECT to Vcc of
about 3M provides matching of the Bell lowlevel tracking curve, and the 21lF value of
CRECT provides the proper attack and release
times. A 16k resistor from the summing node
to ground biases the output to 7V DC.

VOLTAGE-CONTROLLED
ATTENUATOR
The variable gain cell in the NE570/571 may
be used as the heart of a high quality voltagecontrolled amplifier (VCA). Figure 16 shows a
typical circuit which uses an external op amp
for better performance, and an exponential
converter to get a control characteristic of
-6dBIV. Trim networks are shown to null out
distortion and DC shift, and to fine trim gain to
OdB with OV of control voltage.
Op amp A2 and transistors 01 and 02 form
the exponential converter generating an exponential gain control current, which is fed

February 1987

into the rectifier. A reference current of
150/IA, (15V and R20 ~ 100k), is attenuated a
factor of two (6dB) for every volt increase in
the control voltage. Capacitor Ca slows down
gain changes to a 20ms time constant
(Ca X Rl) so that an abrupt change in the
control voltage will produce a smooth sounding gain change. R18 assures that for large
control voltages the circuit will go to full
attenuation. The rectifier bias current would
normally limit the gain reduction to about
70dB. R18 draws excess current out of the
rectifier. After approximately 50dB of attenuation at a -6dB/V slope, the slope steepens
and attenuation becomes much more rapid
until the circuit totally shuts off at about 9V of
control voltage. Al should be a low noise high
slew rate op amp. R13 and R14 establish
approximately a OV bias at Al 's output.
With a OV control voltage, R19 should be
adjusted for OdB gain. At 1V(-6dB gain) R9
should be adjusted for minimum distortion
with a large (+ 10dBm) input Signal. The
output DC bias (Al output) should be measured at full attenuation (+ 10V control voltage) and then R8 is adjusted to give the same
value at OdB gain. Properly adjusted, the
circuit will give typically less than 0.1 % distortion at any gain with a DC output voltage
variation of only a few millivolts. The clipping
level (140IlA into Pin 3, 14) is ± 10V peak. A
signal-to-noise ratio of 90dB can be obtained.
If several VCAs must track each other, a

common exponential converter can be used.
Transistors can simply be added in parallel
with 02 to control the other channels. The
transistors should be maintained at the same
temperature for best tracking.

4-345

AUTOMATIC LEVEL CONTROL
The NE570 can be used to make a very high
performance ALC as shown in Figure 17. This
circuit hook-up is very similar to the basic
compressor shown in Figure 2 except that the
rectifier input is tied to the input rather than
the output. This makes gain inversely proportional to input level so that a 20dB drop in
input level will produce a 20dB increase in
gain. The output will remain fixed at a constant level. As shown, the circuit will maintain
an output level of ± 1dB for an input range of
+ 14 to -43dB at 1kHz. Additional external
components will allow the output level to be
adjusted. Some relevant design equations
are:
Output level

~

Is
Gain

Rl R2 Is
--2 R3

~

140/IA

Rl R2 Is
where
2 R3 VIN (avg)

1r
- VIN
- - ~ --=
~ 1.11

VIN (avg)

2v' 2

(for sine wave)

If ALC action at very low input levels is not
desired, the addition of resistor Rx will limit
the maximum gain of the circuit.

Rl + Rx
- - - X R2 X Is
Gain max ~ __
1._8_V---:--:=_ __
2 R3
The time constant of the circuit is determined
by the rectifier capacitor, CRECT, and an
internal 10k resistor.

I

Signetics Linear Products

Application Note

Applications for Compandors: NE570j571jSA571

AN174

+15V

,.Ok
Rl0

1QOk

lOOk

R8
220k
R7

1'.':

THO
TRIM

3.8V

OCSHIFT
TRIM

62k
Rl0

R9

":'

62k
R13

J

+10pF

1000

Cl

IN

C.

220k
R11

51k

R1.

'"TF
OUT
Cs 100k
R17

R6

100k
RS

CONTROL R22
VOLTAGE '.091<
0-10V o--"",~-..-+--..--""",_~

1:ii ----~ - ~
.. MEG
R18

-15V

lOOk
ROO

TC1C36OS

Figure 16. Voltage·Controlied Attenuator

T

= 10k GRECT

Response time can be made laster at the
expense 01 distortion. Distortion can be approximated by the equation:
THD

l/o1F
=( -)
GRECT

(1kHZ)
- - X 0.2%
Ireq.

proper selection of fixed resistors can be
used instead of the potentiometer. The op·
tional threshold resistor will make the com·
pression or expansion ratio deviate towards
1:1 at low levels. A wide variety of (input)
output characteristics can be created with
this circuit, some of which are shown in
Figure 18.

HI·FI COMPANDOR
VARIABLE SLOPE
COMPRESSOR·EXPANDOR
Gompression and expansion ratios other than
2:1 can be achieved by the circuit shown in
Figure 18. Rotation of the dual potentiometer
causes the circuit hook-up to change from a
basic compressor to a basic expandor. In the
center of rotation, the circuit is 1:1, has
neither compression nor expansion. The (input) output transfer characteristic is thus
continuously variable from 2:1 compression,
through 1:1 up to 1:2 expansion. If a fixed
compression or expansion ratio is desired,
February 1987

The NE570 can be used to construct a high
performance compandor suitable for use with
music. This type of system can be used for
noise reduction in tape recorders, transmission systems, bucket brigade delay lines, and
digital audio systems. The circuits to be
described contain features which improve
performance, but are not required for all
applications.
A major problem with the simple NE570
compressor (Figure 2) is the limited op amp
gain at high frequencies. For weak input
signals, the compressor circuit operates at

4-346

high gain and the 570 op amp simply runs out
of loop gain. Another problem with the 570 op
amp is its limited slew rate of about 0.6V I/oiS.
This is a limitation of the expandor, since the
expandor is more likely to produce large
output signals than a compressor.
Figure 20 is a circuit for a high fidelity
compressor which uses an external op amp
and has a high gain and wide bandwidth. An
input compensation network is required for
stability.
Another feature of the circuit in Figure 20 is
that the rectifier capacitor (Gg) is not
grounded, but is tied to the output of an op
amp circuit. This circuit, built around an
LM324, speeds up the compressor attack
time at low signal levels. The response times
of the simple expandor and compressor (Figures 1 and 2) become longer at low Signal
levels. The time constant is not simply
10k X GRECT, but is really:
( 10k + 2 ( 01, : : : ) ) X GRECT

Signetlcs Linear Products

Application Note

AN174

Applications for Compandors: NE570/571/SA571

lj.1f

(2.15)

When the rectifier input level drops from
OdBm to -30dBm. the time constant in·
creases from 10. 7k X GRECT to 32.6k
X GRECT. In systems where there is unity
gain between the compressor and expandor,
this will cause no overall error. Gain or loss
between the compressor and expandor will
be a mistracking of low signal dynamics. The
circuit with the LM324 will greatly reduce this
problem for systems which cannot guarantee
the unity gain.

It,

.x

331<

-

(5"2)~-----it------+

CI,11)

"

300<
1.1'1

Figure 17. Automatic Level Control

,... r-----1_--00v..
I

r---------------------------~DU~~~~

'

"')

""

I

EXPANSION

a,t

3M

(1.11)

(5,12)~""......- -....- - - " "..........

""

When a compressor is operating at high gain,
(small input signal), and is suddenly hit with a
signal, it will overload until it can reduce its
gain. Overloaded, the output will attempt to
swing rail to rail. This compressor is limited to
approximately a 7Vp_p output swing by the
brute force clamp diodes D3 and D4 . The
diodes cannot be placed in the feedback loop
because their capacitance would limit high
frequency gain. The purpose of limiting the
output swing is to avoid overloading any
succeeding circuit such as a tape recorder
input.
The time it takes for the compressor to
recover from overload is determined by the
rectifier capacitor Gg. A smaller capacitor will
allow faster response to transients, but will
produce more low frequency third harmonic
distortion due to gain modulation. A value of
11'F seems to be a good compromise value
and yields good subjective results. Of course,
the expandor should have exactly the same
value rectifier capacitor for proper transient
response. Systems which have good low
frequency amplitude and phase response can
use compandors with smaller rectifier capaci·
tors, since the third harmonic distortion which
is generated by the compressor will be undis·
torted by the expandor.
Simple compandor systems are subject to a
problem known as breathing. As the system

"".

.....

(2.11)

OUTPUT

10d11/DIV

THftllHOLD

1 MEG

.00

INPUT LIYI:L

Figure 18. Variable Slope Compressor-Expandor

February 1967

4-347

10da1DfY.

Figure 19. Typical Input-Output
Tracking Curves of Variable Ratio
Compressor-Expandor

•

Signetics Linear Products

Application Note

Applications for Compandors: NE570j571jSA571

is changing gain, the change in the background noise level can sometimes be heard.

AN174

+

."F Co

The compressor in Figure 20 contains a high
frequency pre-emphasis circuit (C2, Rs and
Ca, R14), which helps solve this problem.
Matching de-emphasis on the expandor is
required. More complex designs could make
the pre-emphasis variable and further reduce
breathing.
The expandor to complement the compressor
is shown in Figure 21. Here an external op
amp is used for high slew rate. Both the
compressor and expandor have unity gain
levels of OdB. Trim networks are shown for
distortion (THD) and DC shift. The distortion
trim should be done first, with an input of OdB
at 10kHz. The DC shift should be adjusted for
minimum envelope bounce with tone bursts.
When applied to consumer tape recorders,
the subjective performance of this system is
excellent.

....
A..

•-:>-........
""'......-<
A..
THD

TRIM

11K

~-AJ..,..,.-+7.SV
A..

COMPRESSOR
I.

e,

•

fit

R,.

e7K

471(

...

e,
.

D,
D.

Figure 20. Hi-Fi Compressor With Pre-emphasis

February 1987

4-348

Signetics Linear Products

Application Note

Applications for Compandors: NE570j571jSA571

AN174

+3.6V

+7.5V

C7
O.OO5",F
D.C.
R7
220k

EXPANDOR

R1l

SHIFT
TRIM

68k

Rl0
10k
62k
R13

S",F+

IN
Cl

OF

+

co
lOOk

R5

1._
.".

Figure 21. HI-FI Expandor With De-emphasis

February 1987

4-349

Signetics

AN176
Compandor Cookbook
Application Note

Linear Products

Compandors are versatile, low cost, dualchannel gain control devices for audio frequencies_ They are used in tape decks, cordless telephones, and wireless microphones
performing noise reduction. Electronic organs, modems and mobile telephone equipment use compandors for signal level control.
So what is companding? Why do it at all?
What happens when we do it? Compandor is
the contraction of the two words compressor
and expandor. There is one basic reason to
compress a Signal before sending it through a
telephone line or recording it on a cassette
tape: to process that signal (music, speech,
data) so that all parts of it are above the
inherent noise floor of the transmission medium and yet not running into the max. dynamic
range limits, causing clipping and distortion.
The diagrams below demonstrate the idea;
they are not totally correct because in the real
world of electronics the 3kHz tone is riding on
the 1kHz tone. They are shown separated for
better explanation.
Figure 1 is the signal from the source. Figure
2 shows the noise always in the transmission
medium. Figure 3 shows the max limits of the
transmission medium and what happens
when a signal larger than those limits is sent
through it. Figure 4 is the result of compressing the signal (note that the larger signal
would not be clipped when transmitted).

3V

-3V

Figure 1_ Original Signal Input
MAX DYNAMIC
RANGE 6V pk-pk

Figure 3

Figure 2_ Wide-Band Noise Floor
of Transmission Line

3V

The received/playback signal is processed
(expanded) in exactly the same - only inverted - ratio as the input signal was compressed. The end result is a clean, undistorted Signal with a high signal-to-noise ratio.
This document has been designed to give the
reader a basic working knowledge of the
Signetics Compandor family. The analyses of

-3V

Figure 4_ Signal After Compression

BLOCK DIAGRAMS
NE570/571/SA571

NE572

INPUT
INPUT

CURRENT
CONTROLLED
GAIN CELL

OUTPUT

OUTPUT
ATTACK
TIME
CAPACITOR

INPUT

CURRENT
CONTROLLED
GAIN CELL

BUFFER

RELEASE
TIME
CAPACITOR

VOLT.-TO
CURRENT
CONVERTER

INPUT
ATTACKIRELEASE
TIME CONsTANT

SEE NOTES

ATENO

CAPACITOR

February 1987

VOLTAGE
TO
CURRENT

4-350

Signetics Linear Products

Application Note

Compandor Cookbook

AN176

CURRENT

R2

CONTROLLED
GAIN CELL

VOLTAGE TO
CURRENT
CONVERTER

R,

t--""""--H---f

V~o---~~---4---t

~----------------~--oV~

Figure 5. Basic Compressor
three primary applications will be accompanied by "recipes" describing how to select
external components (for both proper operation and function modification). Schematic
and artwork for an application board are also
provided. For comprehensive technical information consult the Compandor Product Guide
or the Linear Data Manual.
The basic blocks in a compandor are the
current-controlled variable gain cell (llG), voltage-to-current converter (rectifier), and operational amplifier. Each Signetics compand or
package has two identical, independent
channels with the following block diagrams
(notice that the 570171 is different from the
572).
The operational amplifier is the main signal
path and output drive.
The full-wave averaging rectifier measures
the AC amplitude of a signal and develops a
control current for the variable gain cell.
The variable gain cell uses the rectifier control current to provide variable gain control for
the operational amplifier gain block.
The compandor can function as a Compressor, Expandor, and Automatic Level Controller or as a complete compressor/expandor
system as described in the following:
1) The COMPRESSOR function processes
uncontrolled input signals into controlled
output signals. The purpose of this is to
avoid distortion caused by a narrow dynamic range medium, such as telephone
lines, RF and satellite transmissions, and
magnetic tape. The Compressor can also
limit the level of a signal.
2) The EXPANDOR function allows a user to
increase the dynamic range of an incoming
February 1987

compressed signal such as radio broadcasts.
3) The compressor / expandor system allows
a user to retain dynamic range and reduce
the effects of noise introduced by the

increase in value, thereby causing the output
signal's amplitude to increase.

transmission medium.
4) The AUTOMATIC LEVEL CONTROL (ALC)

The complete equation for the compressor
gain is:

function (like the familiar automatic gain
control) adjusts its gain proportionally with
the input amplitude. This ALC circuit therefore transforms a widely varying input signal into a fixed amplitude output signal
without clipping and distortion.

HOW TO DESIGN COMPANDOR
CIRCUITS
The rest of the cookbook will provide you with
basic compressor, expandor, and automatic
level control application information. A
NE570/571 has been used in all of the
circuits. If high-fidelity audio or separately
programmable attack and decay time are
needed, the NE572 with a low noise op amp
should be used.
The compressor (see Figure 5) utilizes all
basic building blocks of the compandor. In
this configuration, the variable gain cell is
placed in the feedback loop of the standard
inverting amplifier circuit. The gain equation is
Av = -RF/R IN · As shown above, the variable
gain cell acts as a variable feedback resistor
(RF) (See Figure 5).
As the input signal increases above the
crossover level of OdS, the variable resistor
decreases in value. This causes the gain to
decrease, thus limiting the output amplitude.
Selow the crossover level of OdS, an increase
in input signal causes the variable resistor to

4-351

In the compressor configuration, the rectifier
is connected to the output.

Gain compo = [
where: Rl
R2
R3
18

R1R218
2 R3VIN (avg)

]1'2

= 10k
= 20k
= 20k
= 140pA

VIN(avg) = 0.9(VIN(RMS»)

COMPRESSOR RECIPE
1) DC bias the output half way between the
supply and ground to get maximum headroom. The circuit in Figure 6 is designed
around a system supply of 6V, thus the
output DC level should be 3V.

where:

R4 = 30k
VREF = 1.8V
RDC is external

manipulating the equation, the result is. . .
Roc

VOUT)
= (( - -1
VREF

)R4
-2

Note that the C(oG) should be large enough to
totally short out any AC in this feedback loop.

•

Signetics Linear Products

Application Note

Compandor Cookbook

AN176

2) Analyze the OUTPUT signal's anticipated
amplitude.
a) if larger than 2.8V peak, R2 needs to be
increased. (see INGREDIENTS section)
b) if larger than 3.0V peak, R, will a/so
need to be increased.

By limiting the peak input currents we avoid
signa/ distortion.
3) The input and output coupling caps need to
be large enough not to attenuate any
desired frequencies (Xc = 1/(6.28xf)).
4) The CRECT should be 1flF to 2flF for initial
setup. This directly affects Attack and Release times.
5) An input buffer may be necessary if the
source's output impedance needs matching.
6) Pre-emphasis may be used to reduce
noise-pumping, breathing, etc., if present.
See the NE570/571 data sheet for specific
details.
7) Distortion (THD) trim pins are available if
the already low distortion needs to be
further reduced. Refer to data sheet for
trimming network. Note that if not used, the
THD trim pins should have 200pF caps to
ground.
8) At very low input signal levels, the rectifier's errors become significant and can be
reduced with the Low Level Mistracking
network. (This technique prevents infinite
compression at low input levels.)
The EXPANDOR utilizes all the basic building
blocks of the compandor (see Figure 7). In
this configuration the variable gain cell is
placed in the inverting input lead of the
operational amplifier and acts as a variable
input resistance, RIN. The basic gain equation
for operational amplifiers in the standard
inverting feedback loop is Av = -RF/RIN.

Roc
5,12

~coc

;>--------~~---oV""T

7,10

VIlEF

NOTES:
Max AC current into:
• Gaincell is 140/JA peak
• Rectifier is 300pA peak
All components are internal, except the caps and Roc

Figure 6. Basic Compressor
As the input amplitude increases above the
crossover level of OdBM, this variable resistor
decreases in value, causing the gain to increase, thus forcing the output amplitude to
increase (refer to Figure 10).

The complete equation for the expandor gain
is:

Below the crossover level, an increase in
input amplitude causes the variable resistor
to increase in value, thus forcing the output
amplitude to decrease.
In the expandor configuration the rectifier is
connected to the input.

where: R1 = 10k
R2 = 20k
R3 = 20k
Is = 140J1A
VIN(avg) = 0.9 (VIN(RMS))

RF

,..---...-..

~
VOUT

~1

R,

R,

R3

CURRENT
CONTROLLED
GAIN CELL

VOLTAGE
TO CURRENT
CONVERTER

~
Figure 7. Basic Expandor
February 1987

4-352

V""T

Signetlcs Linear Products

Application Note

Compandor Cookbook

EXPANDOR RECIPE
1) DC bias the output halfway between the
supply and ground to get maximum headroom. The circuit in Figure 8 is designed
around a system supply of 6V so the output
DC level should be 3V.
VOUT DC = (1 + R3/R4)VREF
where: R3 = 20k
R4 = 30k
VREF = 1.8V
Note that when using a supply voltage higher
than 6V the DC output level should be adjusted. To increase the DC output level, it is
recommended that R4 be decreased by adding parallel resistance to it. (Changing R3
would also affect the expandor's AC gain and
thus cause a mismatch in a companding
system.)
2) Analyze the input signal's anticipated am-

plitude:
a) if larger than 2.8V peak, R2 needs to be
increased. (see INGREDIENTS section)

AN176

The complete gain equation for the ALe is:

As the input amplitude increases above the
crossover point, the overall system gain decreases proportionally, holding the output
amplitude constant.

Gain

=

R1R2 1S

2 R3 VIN(avg)

As the input amplitude decreases below the
crossover point, the overall system gain increases proportionally, holding the output
amplitude at the same constant level.
VIN
1r
where--- = 2" r.:
VIN(avg)
vo<2

= 1.11

(for sine wave)

20K

vJ

3,14

VOUT

20K

7,10

-~N2

Rl

2,15 10K

b) if larger than 3.0V peak, Rl will a/so
need to be increased. (see INGREDIENTS)
By limiting the peak input currents we avoid
signa/ distortion.

3) The input and output decoupling caps need
to be large enough not to attenuate any
desired frequencies.
4) The CRECT should be 11'F to 21'F for initial
setup.
5) An input buffer may be necessary if the
source's output impedance needs matching.
6) De-emphasis would be necessary if the
complementary compressor circuit had
been pre-emphasized (as in a tape deck
application). See the Hi-Fi Expandor application in the Linear Data Manual.
7) Distortion (THO) trim pins are available if
the already low distortion needs to be
further reduced. See Linear Data Manual
for trimming network. Note that if not used,
the THO trim pins should have 200pF caps
to ground.
8) At very low input Signal levels, the rectifier's errors become significant and can be
reduced with the Low Level Mistracking
network (see Linear Data Manual). (This
technique prevents infinite expansion at
low input levels.)

NOTE:
All components are internal except caps.

Figure 8. Basic Expandor

1""

(2,15)

Rl

(5,12)~-----U----"""

30pF
1""

Ra 20K

vlN o - -.......-il-'+::.-o--.y,.........- -.....-~
(8,11)

In the ALC configuration, (Figure 9), the
variable gain cell is placed in the feedback
loop of the operational amplifier (as in the
Compressor) and the rectifier is connected to
the input.

R.
30K

l.ev

Figure 9. Automatic Level Control
February 1987

4-353

II

Application Note

Signetics Linear Products

Compandor Cookbook

Note that for very low input levels, ALC may
not be desired and to limit the maximum gain,
resistor Rx has been added. The modified
gain equation is:

R1

+ Rx )

(
X_
R2_
X_
Is __
Gain max. = _ _1.8V
____

2 R3
Rx~

AN176

Rs (20kf2) acts in conjunction with R4 as the
feedback resistor (RF) (expandor configuration) in the equation. (R3'S value can be either
reduced or increased externally.) However, it
is recommended that R4 be the one to
change when adjusting the output DC level.
R4 (30kf2) acts as the input resistor (RIN) in
the standard non-inverting op amp circuit. (Its
value can only be reduced.)
VOUT DC = (1 + (R3/R4»VREF
(for the Expandor)
VOUT DC = (1 + (2RDC/R4»VREF
(for the Compandor, ALC)

«desired max gain) X 26k) -10k

INGREDIENTS
[Application guidelines for internal and external components (and input/output constraints) needed to tailor (cook) each of the
three entrees (applications) to your taste.]
R1 (10kf2) limits input current to the rectifier.
This current should not exceed an AC peak
value of ± 300pA. An external resistor may be
placed in series with R1 if the input voltage to
the rectifier will exceed ± 3.0V peak (I.e.,
10k X 300pA = 3.0V).
R2 (20kf2) limits input current to the variable
gain cell. This current should not exceed an
AC peak value of ± 140iJA. Again, an external
resistor has to be placed in series with R2 if
the input voltage to the variable gain cell
exceeds ± 2.8V (i.e., 20k X 140iJA).

NOTES:
The NE572 differs from the 570/571 in that:
1. There is no internal op amp.
2. The attack and release times are programmed separately.

SYSTEM LEVELS OF A
COMPLETE COMPANDING
SYSTEM
Figure 10 demonstrates the compressing and
expanding functions:

[The purpose of these DC biasing equations
is to allow the designer to set the output
halfway between the supply rails for largest
headroom (usually some positive voltage and
ground).]
CDC acts as an AC shunt to ground to totally
remove the DC biasing resistors from the AC
gain equation.
CF caps are AC signal coupling caps.
CRECT acts as
directly affects
circuit. There is
fast attack and

THD ~ (1 pF ICRECT)(1 kHzlfreq.) X 0.2%

the rectifier's filter cap and
the response time of the
a trade-off, though, between
decay times and distortion.

The time constant is: 10k X CRECT

Point A represents a wide dynamic range
signal with a maximum amplitude of + 16dB
and minimum amplitude of -80dB.
Point B represents the compressor output
showing a 2:1 reduction in dynamic range
(-40dB is increased to -20dB, for example).
Point B can also be seen as the dynamiC
range of a transmission medium. Transmission noise is present at the -60dB level from
Point B to Point C.
Point C represents the input signal to the
expandor.
Point D represents the output of the expandor. The Signal transformation from Point C to
D represents a 1:2 expansion.

The total harmonic distortion (THD) is approximated by:

NE570J571ISA571 SYSTEM LEVEL

[]'h
YRMS

[ ]2

COMPRESSION

4.BY

3.IV

EXPANDOR
'oUT

-- -- --

A IN (COMPRESSOR
_ _ OUT)
B

.16dB

l

REL LEVEL

INPUT TO"G
ANORECT
(EXPANDOR
c IN)

+16.0
+12.0

+16
+12

OdS

775mV

-2OdB

775mV

-20

-20

-4OdB

7.75mV

-40

-40

-&OdB

'775pV

-60

-60

-SOdB

77.5pV

-60

-60

0.0

Figure 10. System Levels of a Complete Companding System

February 1987

dBM

0

~

~

ABS LEVEL

DB

4-354

Application Note

Signetics Linear Products

Compandor Cookbook

AN176

WHAT IS COMPANDING??
Shown here are some scope pictures of what
three functions of the compandor look like in
the kitchen, responding to tone bursts of
varying amplitudes.

..
i

Automatic L.:evel Control
(Smail-Signal Input)

Automatic Level Control
(Large-Signal Input)
Figure 11

February 1987

4-355

Signetics Linear Products

Application Note

AN176

Compandor Cookbook

APPLICATION BOARD
Shown below is the schematic (Figure 12) for
Signetics' NE570/571 evaluation/demo
board. This board provides one channel of
Expansion and one channel of Compression
(which can be switched to Automatic Level
Control).

;+

+

1""~
20K

"G
33K

Roc

36K

SHOWN AS
COMPRESSOR
ALC
(SPDT SWITCH)

~ r'f.

+
*10,F

> ......:>-.........._

(OPTIONAL DE-EMPHASIS)
,..._ _..

......j-::J+

~!.E~1r

10""

(OPTIONAL DE-EMPHASIS)

14

EXPANDOR
INPUT

(OPTIONAL
PRE-EMPHASIS)

Figure 12

February 1987

4-356

20K

12

12K

Signetics

NE570j571jSA571
Compandor
Product Specification

Linear Products

PIN CONFIGURATION

DESCRIPTION

FEATURES

The NE570/571 is a versatile low cost
dual gain control circuit in which either
channel may be used as a dynamic
range compressor or expand or. Each
channel has a full-wave rectifier to detect the average value of the signal, a
linerarized temperature-compensated
variable gain cell, and an operational
amplifier.

• Complete compressor and
expandor in one IC
• Temperature compensated
• Greater than 110dB dynamic
range

The NE570/571 is well suited for use in
cellular radio and radio communications
systems, modems, telephone, and satellite broadcast/receive audio systems.

CIRCUIT DESCRIPTION
The NE570/571 compander building
blocks, as shown in the block diagram,
are a full-wave rectifier, a variable gain
cell, an operational amplifier and a bias
system. The arrangement of these
blocks in the IG result in a circuit which
can perform well with few external components, yet can be adapted to many
diverse applications.
The full-wave rectifier rectifies the input
current which flows from the rectifier
input, to an internal summing node
which is biased at VREF. The rectified
current is averaged on an external filter
capacitor tied to the GRECT terminal, and
the average value of the input current
controls the gain of the variable gain
cell. The gain will thus be proportional to
the average value of the input signal for
capacitively-coupled voltage inputs as
shown in the following equation. Note
that for capacitively-coupled inputs there
is no offset voltage capable of producing
a gain error. The only error will come
from the bias current of the rectifier
(supplied internally) which is less than
O.1JJA.

D, F, N Packages 1

• Operates down to 6VDC
• System levels adjustable with
external components
• Distortion may be trimmed out

II

APPLICATIONS
• Cellular radio
• Telephone trunk compandor570
• Telephone subscriber
compandor - 571
• High level limiter
• Low level expandor - noise gate
• Dynamic noise reduction systems
• Voltage-controlled amplifier

NOTE:
1. SOL - Released in Large SO Package Only.

• Dynamic filters

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

o to
o to
o to
o to
o to

16-Pin Cerdip
16-Pin Plastic DIP
16-Pin Plastic SOL
16-Pin Cerdip
16-Pin Plastic Cerdip

ORDER CODE

+70°C

NE570F

+70°C

NE570N

+70°C

NE571D

+70°C

NE571F

+70°C

NE571N

16·Pin Cerdip

_40°C to + 85°C

SA571F

16·Pin Plastic DIP

_40°C to + 85°C

SA571N

BLOCK DIAGRAM
R3

R2 20K

INVERTER IN

R3
20K

output

Rl 10K

REef IN

O---WIr-----1

R4
30K

V REF
1.8V

or
G )vlNlavg

R,
November 14, 1986

4-357

853-0812 86558

Signetics Linear Products

Product Specification

NE570j571jSA571

Compander

ABSOLUTE MAXIMUM RATINGS
SYMBOL

Vcc

TA

Po

RATING

UNIT

24
18

Voc

o to +70
-40 to +85

°C
°C

400

mW

PARAMETER

Positive supply
570
571
Operating ambient temperature range
NE
SA
Power dissipation

DC ELECTRICAL CHARACTERISTICS TA = 25°C, Vcc = 15V. Except where indicated, the 571 specifications are identical to
those of the 570.
NE/SA571 5

NE570
SYMBOL

PARAMETER

TEST CONDITIONS

UNIT
Min

Vee

Supply voltage

Icc

Supply current

lOUT

Output current capability

SR

Output slew rate
Gain cell distortion2

24

6

3.2

4.8

Untrimmed
Trimmed

1.7
Untrimmed
No signal, 15Hz _ 20kHz1
-1
-40°C < T < 70°C
DoC < T < 70°C

0.3
0.05

1.0

±5

±15

1.8

1.9

±20

±50

20

45

0

+1

±0.1
±0.1

±0.2

-40°C < T < 70°C
O°C < T < 70°C

+2, -25 + 10, -40
±5
±10

Resistor drift4

-40°C < T < 70°C
O°C < T < 70°C

+8, -0
+1.-0

Rectifier input,
V2 = +6dBm, VI = OdB

±O.2

V2 = -30dBm, VI

+0.2

18

V

3.2

4.8

mA
mA

0.5
0.1

1.65

-1.5

V/Jls

2.0

%
%

±5

±15

1.8

1.95

V

±30

± 100

mV

20

60

JlV

0

+1.5

dBm

± 0.1
±0.1

±0.4

dB

+2, -25 +20, -50
±5
±20

mV
%

dB

= OdB

Channel separation

-0.5, +1

60

NOTES:
1. Input to V, and V2 grounded.
2. Measured at OdBm, 1kHz.
3. Expandor AC input change from no Signal to OdBm.
4. Relative to value at TA = 25°C.
5. Electrical characteristics for the SA571 only are specified over -40 to +85°C temperature range.

November 14, 1986

Max

±.5

Reference drift4

Tracking error (measured
relative to value at
unity gain) equals
[Yo - Vo (unity gain)]
dB - V2dBm

Typ

±20
± .5

Unity gain level
Gain change2, 4

Min

±20

Resistor tolerance

Expandor output noise

Max

6
No signal

Internal reference voltage
Output DC shift3

Typ

4-358

+0.2
60

-1, +1.5
dB

Signetics linear Products

Product Specification

NE570j571jSA571

Compandor

The speed with which gain changes to follow
changes in input signal levels is determined
by the rectifier filter capacitor. A small capacitor will yield rapid response but will not fully
filter low frequency signals. Any ripple on the
gain control signal will modulate the signal
passing through the variable gain cell. In an
expandor or compressor application, this
would lead to third harmonic distortion, so
there is a trade-off to be made between fast
attack and decay times and distortion. For
step changes in amplitude, the change in gain
with time is shown by this equation.
G(t) ~ (Giniti.1 - Glin.l) .-tlT

+ Glin.l; T

~

10k X GRECT

The variable gain cell is a current-in, currentout device with the ratio lOUT/liN controlled by
the rectifier. liN is the current which flows
from the LlG input to an internal summing
node biased at VREF. The following equation
applies for capacitively-coupled inputs. The
output current, lOUT, is fed to the summing
node of the op amp.
VIN - VREF

VIN

R2

R2

IIN~----~-

A compensation scheme built into the LlG cell
compensates for temperature and cancels

out odd harmonic distortion. The only distortion which remains is even harmonics, and
they exist only because of internal offset
voltages. The THO trim terminal provides a
means for nulling the internal offsets for low
distortion operation.

TYPICAL PERFORMANCE
CHARACTERISTICS

~

w

~

The operational amplifier (which is internally
compensated) has the non-inverting input
tied to VREF , and the inverting input connected to the AG cell output as well as brought
out externally. A resistor, R3, is brought out
from the summing node and allows compressor or expandor gain to be determined only by
internal components.

....5
:0

o

a:

o
o
z

.."
~

a:

o

The output stage is capable of ± 20mA output
current. This allows a + 13dBm (3.5VRMS)
output into a 300n load which, with a series
resistor and proper transformer, can result in
+ 13dBm with a 600n output impedance.

~

w

~

....
:0

~

II:

o

A bandgap reference provides the reference
voltage for all summing nodes, a regulated
supply voltage for the rectifier and AG cell,
and a bias current for the AG cell. The low
tempco of this type of reference provides very
stable biasing over a wide temperature range.

:flII:'"

~
o

u

-30 -20
-10
0 +10
COMPRESSOR OUTPUT lEVEl
OR
EXPANDOR INPUT lEVEl/dBm}

The typical performance characteristics illustration shows the basic input-output transfer
curve for basic compressor or expandor circuits.

Basic Input-Output Transfer Curve

TYPICAL TEST CIRCUIT
VCC=lSV

O"I

I'OPF

'3

Vo

1,16

5,12

T2
-=-

November 14, 1986

4-359

8.2K

-=-

8.9

1200

PF

Signetics Linear Products

Product Specification

NE570j571jSA571

Compander

INTRODUCTION
Much interest has been expressed in high
performance electronic gain control circuits.
For non-critical applications, an integrated
circuit operational transconductance amplifier
can be used, but when high-performance is
required, one has to resort to complex discrete circuitry with many expensive, wellmatched components. This paper describes
an inexpensive integrated circuit, the NE570
Compandor, which offers a pair of high performance gain control circuits featuring low
distortion ( < 0.1 %), high signal-to-noise ratio
(90dB), and wide dynamic range (110dB).

CIRCUIT BACKGROUND
The NE570 Compandor was originally designed to satisfy the requirements of the
telephone system. When several telephone
channels are multiplexed onto a common
line, the resulting signal-to-noise ratio is poor
and companding is used to allow a wider
dynamic range to be passed through the
channel. Figure 1 graphically shows what a
compandor can do for the signal-to-noise
ratio of a restricted dynamic range channel.
The input level range of + 20 to -aOdB is
shown undergoing a 2-to-l compression
where a 2dB input level change is compressed into a 1dB output level change by the
compressor. The original 100dB of dynamic
range is thus compressed to a 50dB range for
transmission through a restricted dynamic
range channel. A complementary expansion
on the receiving end restores the original
signal levels and reduces the channel noise
by as much as 45dB.
The significant circuits in a compressor or
expandor are the rectifier and the gain control
element. The phone system requires a simple
full-wave averaging rectifier with good accuracy, since the rectifier accuracy determines the
(input) output level tracking accuracy. The
gain cell determines the distortion and noise
characteristics, and the phone system specifications here are very loose. These specs
could have been met with a simple operational transconductance multiplier, or OTA, but
the gain of an OTA is proportional to temperature and this is very undesirable. Therefore, a
linearized transconductance multiplier was
designed which is insensitive to temperature
and offers low noise and low distortion performance. These features make the circuit useful in audio and data systems as well as in
telecommunications systems.

provides a gain control current, IG, for the
variable gain (.e.G) cell. The output of the .e.G
cell is a current which is fed to the summing
node of the operational amplifier. Resistors
are provided to establish circuit gain and set
the output DC bias.

I

~
:i

IE
8:

INPUT

I

LEVEL

OUTPUT

LEVEL

+2~+20

...

I

0••

---='

---

-~-~:
Figure 1. Restricted Dynamic Range
Channel

THD TRIM

R,

tNY. IN

The circuit is intended for use in single power
supply systems, so the internal summing
nodes must be biased at some voltage above
ground. An internal band gap voltage reference provides a very stable, low noise 1.8V
reference denoted VREF. The non-inverting
input of the op amp is tied to VREF, and the
summing nodes of the rectifier and .e.G cell
(located at the right of R1 and R2) have the
same potential. The THD trim pin is also at
the VREF potential.
Figure S shows how the circuit is hooked up
to realize an expandor. The input signal, VIN,
is applied to the inputs of both the rectifier
and the .e.G cell. When the input signal drops
by 6dB, the gain control current will drop by a
factor of 2, and so the gain will drop 6dB. The
output level at VOUT will thus drop 12dB,
giving us the desired 2-to-l expansion.
Figure 4 shows the hook-up for a compressor. This is essentially an expandor placed in
the feedback loop of the op amp. The .e.G cell
is setup to provide AC feedback only, so a
separate DC feedback loop is provided by the
two Roc and CDC. The values of Roc will
determine the DC bias at the output of the op
amp. The output will bias to:
VOUT DC

= 1 + RDC1 + Roc2
R4

Yee PIN 13
GND. PIN 4

C RECT

VREF

=(

1 + Roc TOT) 1.aV
SDk

Figure 2. Chip Block Diagram
(1 of 2 Channels)

R,

·CIN1

R,

·{N.2. . . .R~'

.---L----t

NOTES:

BASIC CIRCUIT HOOK-UP AND
OPERATION

GAIN _ 2 Ra VIN (avg.)

Figure 2 shows the block diagram of one half
of the chip, (there are two identical channels
on the IC). The full-wave averaging rectifier

"External components

November 14, 1986

18

~

R1 R2 Ie
140"A

Figure 3. Basic Expandor

4-360

Signetics Linear Products

Product Specification

NE570j571jSA571

Compandor

The output of the expandor will bias up to:
R3
Your DC= 1 +- VREF
R4
20k )
VREF= ( 1 + - 1.8V=3.0V
30k

..
,-,..

The output will bias to 3.0V when the internal
resistors are used. External resistors may be
placed in series with R3, (which will affect the
gain), or in parallel with R4 to raise the DC
bias to any desired value.

C

,-,

:J-----'f------......-t--W'lr----<> V,N

TC11881S

F
NOTE:

C1N ,

VIN avg
IG=2~

R,

o--jl-'ll..........~--1

Figure 6. Simplified Rectifier Schematic

V,N

then mirrored with a gain of 2 to become IG,
the gain control current.

NOTES:
j,

GAIN - (

)

2 Rs YIN (avg)

I. - 140"A
*external components

Figure 4. Basic Compressor

y.

Figure 5. Rectifier Concept

CIRCUIT DETAILS - RECTIFIER
Figure 5 shows the concept behind the fullwave averaging rectifier. The input current to
the summing node of the op amp, VINR 1, is
supplied by the output of the op amp. If we
can mirror the op amp output current into a
unipolar current, we will have an ideal rectifier. The output current is averaged by R5, CR,
which set the averaging time constant, and
November 14, 1986

Figure 6 shows the rectifier circuit in more
detail. The op amp is a one-stage op amp,
biased so that only one output device is on at
a time. The non-inverting input, (the base of
01), which is shown grounded, is actually tied
to the internal 1.8V VREF. The inverting input
is tied to the op amp output, (the emitters of
05 and 06), and the input summing resistor
R1. The single diode between the bases of 05
and 06 assures that only one device is on at
a time. To detect the output current of the op
amp, we simply use the collector currents of
the output devices 05 and 06' 06 will conduct
when the input swings positive and 05 conducts when the input swings negative. The
collector currents will be in error by the a of
05 or 06 on negative or positive signal
swings, respectively. ICs such as this have
typical NPN {3s of 200 and PNP {3s of 40. The
a's of 0.995 and 0.975 will produce errors of
0.5% on negative swings and 2.5% on positive swings. The 1.5% average of these
errors yields a mere 0.13dB gain error.
At very low input signal levels the bias current
of 02, (typically 50nA), will become significant
as it must be supplied by 05' Another low
level error can be caused by DC coupling into
the rectifier. If an offset voltage exists between the VIN input pin and the base of O2,
an error current of Vos/R1 will be generated.
A mere 1mV of offset will cause an input
current of 1~OnA which will produce twice the
error of the input bias current. For highest
accuracy, the rectifier should be coupled into
capacitively. At high input levels the {3 of the
PNP 06 will begin to suffer, and there will be
an increasing error until the circuit saturates.

4-361

Saturation can be avoided by limiting the
current into the rectifier input to 25011A. If
necessary, an external resistor may be
placed in series with R1 to limit the current to
this value. Figure 7 shows the rectifier accuracy vs input level at a frequency of 1kHz.

.,r---r---r---r----,

-,~---~~~-~-~*---+--~
RECTIFIER INPUT dam
OPQ7BSOS

Figure 7. Rectifier Accuracy

At very high frequencies, the response of the
rectifier will fall off. The roll-off will be more
pronounced at lower input levels due to the
increasing amount of gain required to switch
between 05 or 06 conducting. The rectifier
frequency response for input levels of OdBm,
-20dBm, and -40dBm is shown in Figure 8.
The response at all three levels is flat to well
above the audio range.

Signetics Linear Products

Product Specification

Compandor

NE570/571/SA571

FREQUENCY (Hz)

Figure 8. Rectifier Frequency
Response vs Input Level

VARIABLE GAIN CELL
Figure 9 is a diagram 01 the variable gain cell.
This is a linerarized two-quadrant transconductance multiplier. 01. 02 and the op amp
provide a predistorted drive signal for the gain
control pair. Os and 04' The gain is controlled
by IG and a current mirror provides the output
current.
The op amp maintains the base and collector
of 0 1 at ground potential (VREF) by controlling
the base of 02. The input current liN
( = VIN/R2) is thus forced to flow through 0 1
along with the current 110 so ICl = 11 + liN·
Since 12 has been set at twice the value of 11.
the current through 02 is:
12 - (11 + liN)

The key to the circuit is that this same
predistorted drive signal is applied to the gain
control pair, Os and 04' When two differential
pairs of transistors have the same signal
applied, their collector current ratios will be
identical regardless of the magnitude of the
currents. This gives us:

IC2

Ics

=

NOTE:

Figure 9. Simplified Ll.G Cell Schematic

This equation is linear and temperature-insensitive, but it assumes ideal transistors.

= 11 -liN = IC2'

The op amp has thus forced a linear current
swing between 01 and 02 by providing the
proper drive to the base of 02' This drive
signal will be linear for small signals, but very
non-linear for large signals, since it is compensating for the non-linearity of the differential pair, 01 and 02, under large signal conditions.

ICl = IC4

y-

11 + liN
11 - liN

plus the relationships IG = Ics + IC4 and
lOUT = IC4 - Ics will yield the multiplier transfer
function,

November 14, 1986

... -

operating level of OdBm, a 1mV offset will
yield 0.34% of second harmonic distortion.
Most circuits are somewhat better than this,
which means our overall offsets are typically
about hmV. The distortion is not affected by
the magnitude of the gain control current, and
it does not increase as the gain is changed.
This second harmonic distortion could be
eliminated by making perfect transistors, but
since that would be difficult, we have had to
resort to other methods. A trim pin has been
provided to allow trimming of the internal
offsets to zero, which effectively eliminated
second harmonic distortion. Figure 11 shows
the simple trim network required.
Vee

INPUT LEVEL (dBm)

Figure 10. Ll.G Cell Distortion
vs Offset Voltage
3,6V

If the transistors are not perfectly matched, a
parabolic, non-linearity is generated, which
results in second harmonic distortion. Figure
10 gives an indication of the magnitude of the
distortion caused by a given input level and
offset voltage. The distortion is linearly proportional to the magnitude of the offset and
the input level. Saturation of the gain cell
occurs at a + 8dBm level. At a nominal

4-362

UK
~20K

To THO Trim

T, .

200pF

*
Figure 11. THO Trim Network

Signetics Linear Products

Product Specification

Compandor

NE570j571jSA571

Figure 12 shows the noise performance of
the LlG cell. The maximum output level before clipping occurs in the gain cell is plotted
along with the output noise in a 20kHz
bandwidth. Note that the noise drops as the
gain is reduced for the first 20dB of gain
reduction. At high gains, the signal to noise
ratio is 90dB, and the total dynamic range
from maximum signal to minimum noise is
110dB.
Control signal feedthrough is generated in the
gain cell by imperfect device matching and
mismatches in the current sources, 11 and 12.
When no input signal is present, changing IG
will cause a small output signal. The distortion
trim is effective in nulling out any control
signal feedthrough, but in general, the null for
minimum feedthrough will be different than
the null in distortion. The control signal feedthrough can be trimmed independently of
distortion by tying a current source to the LlG
input pin. This effectively trims 11. Figure 13
shows such a trim network.

Vee

A - .ELEeT FOA )

uv
410K

lOOK

~ TOPIN30R 14

come very significant. Figure 15 shows the
effects of temperature on the diffused resistors which are normally used in integrated
circuits, and the ion-implanted resistors which
are used in this circuit. Over the critical O°C to
+ 70°C temperature range, there is a 10-to-l
improvement in drift from a 5 % change for
the diffused resistors, to a 0.5% change for
the implemented resistors. The implanted
resistors have another advantage in that they
can be made 1t7 the size of the diffused
resistors due to the higher resistivity. This
saves a significant amount of chip area.

Figure 13. Control Signal Feedthrough
Trim

II

OPERATIONAL AMPLIFIER
The main op amp shown in the chip block
diagram is equivalent to a 741 with a 1MHz
bandwidth. Figure 14 shows the basic circuit.
Split collectors are used in the input pair to
reduce gM, so that a small compensation
capacitor of just 10pF may be used. The
output stage, although capable of output
currents in excess of 20mA, is biased for a
low quiescent current to conserve power.
When driving heavy loads, this leads to a
small amount of crossover distortion.

I

Figure 14. Operational Amplifier

1.15

RESISTORS

_00

NOISE IN

20KHI

ew

_100'----'----'----'----'--......
_40

_20
yeA GAIN (dB)

Figure 12. Dynamic Range of NE570

November 14, 1986

Inspection of the gain equations in Figures 3
and 4 will show that the basic compressor
and expandor circuit gains may be set entirely
by resistor ratios and the internal voltage
reference. Thus, any form of resistors that
match well would suffice for these simple
hook-ups, and absolute accuracy and temperature coefficient would be of no importance. However, as one starts to modify the
gain equation with external resistors, the
internal resistor accuracy and tempco be-

4-363

1Kn fO

lOWTC
'MPUNTED
RESISTOR

-40

.

TEMPERATlU'E

Figure 15. Resistance vs Temperature

Signetics

NEjSA572
Programmable Analog
Compandor
Product Specification

Linear Products

DESCRIPTION
The NE572 is a dual-channel, high-performance gain control circuit in which
either channel may be used for dynamic
range compression or expansion. Each
channel has a full-wave rectifier to detect the average value of input signal, a
linearized, temperature-compensated
variable gain cell (.e.G) and a dynamic
time constant buffer. The buffer permits
independent control of dynamic attack
and recovery time with minimum external components and improved low frequency gain control ripple distortion over
previous compandors.
The NE572 is intended for noise reduction in high-performance audio systems.
It can also be used in a wide range of
communication systems and video recording applications.

FEATURES
• Independent control of attack
and recovery time
• Improved low frequency gain
control ripple
• Complementary gain compression
and expansion with external op
amp
• Wide dynamic range - greater
than 110dB
• Temperature-compensated gain
control
• Low distortion gain cell
• Low nOise - 6IJ.V typical
• Wide supply voltage range6V-22V
• System level adjustable with
external components

ORDERING INFORMATION
DESCRIPTION
16-Pin Plastic SO
16-Pin Plastic DIP

TEMPERATURE RANGE

o to
o to

ORDER CODE

+70°C

NE572D

+70°C

NE572N

16-Pin Plastic SO

-40°C to + 85°C

SA572D

16-Pin Cerdip

-40°C to + 85°C

SA572F

18-Pin Plastic DIP

-40°C to + 85°C

SA572N

PIN CONFIGURATION
D, N Packages1
TRACK TRIM It.

1

RECOY. CAP. A

2

15 TRACK TRIM B

REer.IN A

3

14 REeov. CAP. B

ATTACK CAP It.

4

THDTRIM It.

6

12

.lG IN A

7

GROUNO

8

ATTACK CAP B

TOP VIEW
NOTE:
1. D package released in large SO (SOL) package
only.

APPLICATIONS
• Dynamic noise reduction system
• Voltage control amplifier
• Stereo expandor
• Automatic level control
• High-level limiter
• Low-level noise gate
• State variable filter

BLOCK DIAGRAM

(7,9)-+.......,,'......._ - .

r-_ _ _ _ _ _ _ _ _ _ _ _ _ _

~(5."1

r--"'--..,

(15,10)

.-__+--_+-+(1.151
(3,131+-+-+-;

(16)

(81

March 18, 1986

(4,12)

(2.14)

4-364

853-0813 82891

Signetics linear Products

Product Specification

Programmable Analog Compand or

NEjSA572

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

Vcc

Supply voltage

TA

Operating temperature range
NE572
SA572

RATING

UNIT

22

Voe

o to +70
-40 to +85

'C

500

mW

Power dissipation

Po

DC ELECTRICAL CHARACTERISTICS Standard test conditions (unless otherwise noted) Vee -15V, TA = 25'C; Expandor
mode (see Test Circuit). Input signals at unity gain level (OdB) = 100mVRMS at 1kHz;
Vj = V2; R2 = 3.3kn; Ra = 17.3kn.
NE572
SYMBOL

PARAMETER

UNIT
Min

Vee

Supply voltage

lee

Supply current

THD
THD
THD

No signal output noise
DC level shift
(untrimmed)

6

Tracking error (measured
relative to value at unity
gainoutput) =
[Va - Va (unity gain)]
dB-V2 (dBm)
Channel crosstalk
PSRR

Power supply rejection
ratio

March 18, 1986

Max

Min

22

6

Typ

22

Voe
rnA

2.5

2.7

Voe

0.2

1.0

%

2.5

2.7

1kHz CA = 1.0!,F

0.2

1.0

1kHz CR = 10!,F

0.05

0.05

%

100Hz

0.25

0.25

%

Input to Vj and V2 grounded
(20 -20kHz)

6

25

6

25

!'V

Input change from no signal to
100mVRMS

±20

±50

±20

±50

mV

0

+ 1.5

dB

0.7

3

%

-2.5
+1.6

dB

2.3

-1

0

+1

Vj = V2 = 400mV

0.7

3.0

Rectifier input
V2 =+6dB, Vj=OdB
V2 = -30dB, Vj = OdB

±0.2
±0.5

200mVRMS into channel A,
measured output on channel B
120Hz

60

-1.5

±0.2
±0.5

-1.5
+0.8
60

70

4-365

2.3

Max

6.3

6

Unity gain level
Large-signal distortion

Typ

No signal

Internal voltage
reference
Total harmonic distortion
(untrimmed)
Total harmonic distortion
(trimmed)
Total harmonic distortion
(trimmed)

SA572

TEST CONDITIONS

dB
70

dB

Signetics Linear Products

Product Specification

NEjSA572

Programmable Analog Compandor

TEST CIRCUIT
1000

.1.u F

-15V

(5,11)

CR

=

10pF

CA

= lpF

>-4---oVo

J
J

(6,10j
BUFFER

,a,

(4,12\

(1,15)

2.2"F 3.3K(3,13)
V2o-1r-~~---T---;

AUDIO SIGNAL PROCESSING IC
COMBINES VCA AND FAST
ATTACK/SLOW RECOVERY
LEVEL SENSOR
In high-performance audio gain control applications, it is desirable to independently control the attack and recovery time of the gain
control signal. This is true, for example, in
compandor applications for noise reduction.
In high end systems the input signal is usually
split into two or more frequency bands to
optimize the dynamic behavior for each band.
This reduces low frequency distortion due to
control signal ripple, phase distortion, high
frequency channel overload and noise modulation. Because of the expense in hardware,
multiple band signal processing up to now
was limited to professional audio applications.
With the introduction of the Signetics NE572
this high-performance noise reduction concept becomes feasible for consumer hi fi
applications. The NE572 is a dual channel
gain control IC. Each channel has a linearized, temperature-compensated gain cell and
an improved level sensor. In conjunction with
an external low noise op amp for current-tovoltage conversion, the VCA features low
distortion, low noise and wide dynamic range.

March 18, 1986

100~!

t-:-~-----------+-4~>Mor-- +15V
(16)

The novel level sensor which provides gain
control current for the VCA gives lower gain
control ripple and independent control of fast
attack, slow recovery dynamic response. An
attack capacitor CA with an internal 10k
resistor RA defines the attack time tAo The
recovery time tR of a tone burst is defined by
a recovery capacitor CR and an internal I Ok
resistor RR. Typical attack time of 4ms for the
high-frequency spectrum and 40ms for the
low frequency band can be obtained with
O.IIlF and 1.01lF attack capacitors, respectively. Recovery time of 200ms can be obtained with a 4.71lF external capacitor. With
the recovery capacitor added in the level
sensor, the gain control ripple for low frequency signals is much lower than that of a
simple RC ripple filter. As a result, the residual third harmonic distortion of low frequency
signal in a two quad transconductance amplifier is greatly improved. With the 1.01lF attack
capacitor and 4.71lF recovery capacitor for a
100Hz signal, the third harmonic distortion is
improved by more than 10dB over the simple
RC ripple filter with a single 1.01lF attack and
recovery capacitor, while the attack time
remains the same.
The NE572 is assembled in a standard 16-pin
dual in-line plastic package and in oversized

4-366

SOL package. It operates over a wide supply
range from 6V to 22V. Supply current is less
than 6mA. The NE572 is designed for consumer application over a temperature range
0- 70°C. The SA572 is intended for applications from -40°C to +85°C.

NE572 BASIC APPLICATIONS
Description
The NE572 consists of two linearized, temperature-compensated gain cells (~G), each
with a full-wave rectifier and a buffer amplifier
as shown in the block diagram. The two
channels share a 2.5V common bias reference derived from the power supply but
otherwise operate independently. Because of
inherent low distortion, low noise and the
capability to linearize large signals, a wide
dynamic range can be obtained. The buffer
amplifiers are provided to permit control of
attack time and recovery time independent of
each other. Partitioned as shown in the block
diagram, the IC allows flexibility in the deSign
of system levels that optimize DC shift, ripple
distortion, tracking accuracy and noise floor
for a wide range of application requirements.

Signetics Linear Products

Product Specification

NE/SA572

Programmable Analog Compander

Gain Cell
Figure 1 shows the circuit configuration of the
gain cell. Bases of the differential pairs
01 - 02 and 03 - 0 4 are both tied to the
output and inputs of OPA A 1. The negative
feedback through 01 holds the VBE of
01 - 02 and the VBE of 03 - 04 equal. The
following relationship can be derived from the
transistor model equation in the forward active region.

v+

+

(V BE = Vr In IC/IS)

= VT

In( 11

~slIN ) _ VT

In(

12-11~-IIN )(2)

VIN
where liN = R1
R1 = 6.8k.Q
11 = 140"A
12 = 280"A
10 is the differential output current of the gain
cell and IG is the gain control current of the
gain cell.
If all transistors 01 through 04 are of the
same size, equation (2) can be simplified to:

The first term of Equation 3 shows the
multiplier relationship of a linearized two
quadrant transconductance amplifier. The
second term is the gain control feedthrough
due to the mismatch of devices. In the design,
this has been minimized by large matched
devices and careful layout. Offset voltage is
caused by the device mismatch and it leads
to even harmonic distortion. The offset voltage can be trimmed out by feeding a current
source within ± 251lA into the THO trim pin.

March 18, 1986

Vin

Figure 1. Basic Gain Cell Schematic
The residual distortion is third harmonic distortion and is caused by gain control ripple. In
a compandor system, available control of fast
attack and slow recovery improve ripple distortion significantly. At the unity gain level of
100mV, the gain cell gives THO (total harmonic distortion) of 0.17% typo Output noise
with no input signals is only 6pN in the audio
spectrum (10Hz - 20kHz). The output current
10 must feed the virtual ground input of an
operational amplifier with a resistor from output to inverting input. The non-inverting input
of the operational amplifier has to be biased
at VREF if the output current 10 is DC coupled.

Rectifier
The rectifier is a full-wave design as shown in
Figure 2. The input voltage is converted to
current through the input resistor R2 and
turns on either 05 or 06 depending on the

4-367

signal polarity. Oeadband of the voltage to
current converter is reduced by the loop gain
of the gain block A2. If AC coupling is used,
the rectifier error comes only from input bias
current of gain block A 2. The input bias
current is typically about 70nA. Frequency
response of the gain block A2 also causes
second-order error at high frequency. The
collector current of 06 is mirrored and
summed at the collector of 05 to form the full
wave rectified output current IR. The rectifier
transfer function is
VIN- VREF
IR=--R2

(4)

If VIN is AC-coupled, then the equation will be
reduced to:
VIN(AVG)
IRAC=--R2

Signetics Linear Products

Product Specification

NEjSA572

Programmable Analog Compandor

The internal bias scheme limits the maximum
output current IR to be around 300f£A. Within
a ± 1dB error band the input range of the
rectifier is about 52dB.

v+

Buffer Amplifier

VREF

0-----,

07

1--------- -----j

I
I
I
I

II

R2

v;"

I
1
I

06

I

II

L_______________ I

Figure 2. Simplified Rectifier Schematic

In audio systems, it is desirable to have fast
attack time and slow recovery time for a tone
burst input. The fast attack time reduces
transient channel overload but also causes
low-frequency ripple distortion. The low-frequency ripple distortion can be improved with
the slow recovery time. If different attack
times are implemented in corresponding frequency spectrums in a split band audio system, high quality performance can be
achieved. The buffer amplifier is designed to
make this feature available with minimum
external components. Referring to Figure 3,
the rectifier output current is mirrored into the
input and output of the unipolar buffer amplifier A3 through 08, 09 and 010. Diodes D11
and D12 improve tracking accuracy and provide common-mode bias for A3' For a positive-going input signal, the buffer amplifier
acts like a voltage-follower. Therefore, the
output impedance of A3 makes the contribution of capacitor CR to attack time insignificant. Neglecting diode impedance, the gain
Ga(t) for ~G can be expressed as follows:
-t
Ga(t) = (GaINT - GaFNLl eTA + GaFNL
GalNT = Initial Gain
GaFNL
TA

=

= RA

Final Gain
• CA

= 10k'

CA

where T A is the attack time constant and RA
is a 10k internal resistor. Diode D15 opens the
feedback loop of A3 for a negative·going
signal if the value of capacitor CR is larger
than capacitor CA. The recovery time depends only on CR • RR. If the diode impedance is assumed negligible, the dynamic gain
GR (t) for ~G is expressed as follows.
-t
GR(t)
TR
CR

CA

I

TRACKING
TRIM

= RR

INT - GR FNLl e TR + GR FNL

• CR

= 10k

• CR

where TR is the recovery time constant and
RR is a 10k internal resistor. The gain control
current is mirrored to the gain cell through
014' The low level gain errors due to input
bias current of A2 and A3 can be trimmed
through the tracking trim pin into A3 with a
current source of ± 3f£A.

I

Figure 3. Buffer Amplifier Schematic

March 18, 1986

= (GR

4-368

Signetlcs Linear Products

Product Specification

NEjSA572

Programmable Analog Compandor

A4

17,3K

CIN2

CIH1

VIN

(7.91

o---j

Al

>-+---0 VOUT

S.8K

2.2~F

2.2.u F

A.
lOOK
CIN3
2.2j.1F

':"
A2

3.3K
(3.13)

TC11961S

Figure 4. Basic Expandor Schematic

Basic Expandor
Figure 4 shows an application of the circuit as
a simple expandor. The gain expression of
the system is given by
VOUT = ~ • R3 • VIN(AVG)
VIN
(11

11

R2 • R1

(5)

= 140/JA)

Both the resistors R1 and R2 are tied to
internal summing nodes. R1 is a 6.Bk internal
resistor. The maximum input current into the
gain cell can be as large as 140/JA. This
corresponds to a voltage level of 140/JA •
6.8k = 952mV peak. The input peak current

March 18, 1986

into the rectifier is limited to 300/JA by the
internal bias system. Note that the value of
R1 can be increased to accommodate higher
input level. R2 and R3 are external resistors. It
is easy to adjust the ratio of R3/R2 for
desirable system voltage and current levels.
A small R2 results in higher gain control
current and smaller static and dynamic tracking error. However, an impedance buffer A1
may be necessary if the input is voltage drive
with large source impedance.
The gain cell output current feeds the summing node of the external OPA A2. R3 and A2
convert the gain cell output current to the
output voltage. In high-performance applications, A2 has to be low-noise, high-speed and

4·369

wide band so that the high-performance output of the gain cell will not be degraded. The
non-inverting input of A2 can be biased at the
low noise internal reference Pin 6 or 10.
Resistor R4 is used to bias up the output DC
level of A2 for maximum swing. The output

D~o:: ::E:2 1
(is

9
:;
R4

b)Y_VB

~

(6)

R4

VB can be tied to a regulated power supply for
a dual supply system ,and be grounded for a
single supply system. CA sets the attack time
constant and CR sets the recovery time
constant.

Signetics Linear Products

Product Specification

NEjSA572

Programmable Analog Compandor

Basic Compressor
Figure 5 shows the hook-up of the circuit as a
compressor. The IC is put in the feedback
loop of the OPA A1. The system gain expression is as follows:

9,1K

(7)

ROC.

OOCl

04

J.

9.1K

CDC
10J,lF

CIN1

VIN

<>-----!I-...J\IVV---i-----I
2.2fJF

:>-----~------oVOUT

1:!K

RDC1, RDC2, and CDC form a DC feedback for
A1. The output DC level of Al is given by

VODC = VREF

(7'9)1

( 1 + RDCl R+4RDC2 )

CIN2

2.2J.lF

(8)
CINl
2.2/.lF

The zener diodes Dl and D2 are used for
channel overload protection.

Basic Compandor System
The above basic compressor and expandor
can be applied to systems such as tape/disc
noise reduction, digital audio, bucket brigade
delay lines. Additional system design techniques such as bandlimiting, band splitting,
pre-emphasis, de-emphasis and equalization
are easy to incorporate. The IC is a versatile
functional block to achieve a high performance audio system. Figure 6 shows the
system level diagram for reference.

March 18, 1986

3.3K

O.

(3,13)

Figure 5. Basic Compressor Schematic

4-370

Signetics Linear Products

Product Specification

NE/SA572

Programmable Analog Compandor

[
VRMS

3.0V

547.6MV
400MV

100MV

10MV

, MV

100,1.1'1

COMPRESSION
IN

f

[

REL LEVEL

dB

EXPANDOR

ABS LEVEL

dBM

OUT

~

INPUT TO ll.G
AND ReCT

/

--------

------

/

~

~

~

10.uV

Figure 6. NE572 System Level

March 1B, 19B6

r

4-371

+29.54

+11.76

+14.77
+12.0

-3.00
-5.78

0.0

-17.78

-20

-37.78

-40

-57.78

-60

-77.78

-80

-97.78

II

Signetics

AN175
Automatic Level Control Using
the NE572
Application Note

Linear Products

NE572 AUTOMATIC LEVEL CONTROL

2.z,.F

lOOK

9.1K

9.1K

V+
17.3K

VIN

o--.....---If:..---"'Y'I.-------~--=_I
2.21lF

fl'

~~l~V~O~UT~DC~--~--~+ r------ov~

TOTHD+---~~-----~--~
TRIM PIN
lK

2.2,F

OF 572
PIN 6

Roc, + Roc, )

VODC "" VREF ( 1 + ---R-,---

OUTPUT LEVEL = ( R'R'18)
2Rs

(

VIN

WHERE:

A4 = 100k
RO()1 = Roc2 = 9.1k
VREF = 2.5V

WHERE:

At'" 6.ak (Internal)
R, = S.Sk
R3'" 17.3k

)

VIN(avg)

18 = l40!'A
ATTACK TIME = (10k) CA
RECOVERY TIME - (10k) CR
TO LIMIT THE GAIN AT VERY LOW INPUT LEVELS. ADD Rx:
GAIN MAX. ""

~ X R2 X Ie

11

2Y2

(FOR SINE WAVES)

2R,
NOTE:

Pin numbers are for side A of the NE572.

February 1987

VIN

V1N(avg)

---=-=1.11

4-372

NE575

Signetics

Low Voltage Compandor
Preliminary Specification

Linear Products

DESCRIPTION

FEATURES

The NE575 is a dual gain-control circuit
designed for low voltage applications.
The NE575's channel 1 is an expand or,
while channel 2 can be configured either
for expandor, compressor, or automatic
level controller (ALC) application.

• Operating voltage range from 3
to 7V
• Reference voltage of
100mVRMS = OdB
• One dedicated summing op amp
per channel and two extra
uncommitted op amps
• soon drive capability
• Single or split supply operation
• Wide input/output swing
capability.

PIN CONFIGURATION
NE575 D, N Packages

APPLICATIONS
•
•
•
•
•
•

Portable communications
Cellular radio
Cordless telephone
Consumer audio
Portable broadcast mixers
Wireless microphones

TOP VIEW

• Modems
• Electric organs

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

o to
o to

20-Pin Plastic DIP
20-Pin Plastic SO

ORDER CODE

+70'C

NE575N

+70'C

NE575D

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

Vcc

Supply voltage

TA

Operating temperature range

TSTG

Storage temperature range

February 1987

RATING

UNIT

8

V

-40 to +85

'C

-65 to + 150

'C

4-373

Preliminary Specification

Signetics Linear Products

Low Voltage Compandor

DC ELECTRICAL CHARACTERISTICS

NE575

T A = 25°C, OdB = 100mV, expander mode, Vcc = 5V, Figure 1, unless otherwise
specified.
LIMITS

SYMBOL

PARAMETER

UNIT

TEST CONDITIONS
Min

Typ

Max

3

5

7

V

3

4

5.5

mA

1kHz, OdB, BW = 3.5kHz

0.13

1.0

%

BW = 20kHz, Rs = OQ

6

20

JlV

For compandor, including summing amplifier
Vcc

Supply voltage 1

Icc

Supply current

RL

Summing amp output load

THD

Total harmonic distortion

eno

Output voltage noise

OdB

Unity gain level

Vos

Output voltage offset
Output DC shift
Tracking error
Crosstalk

No signal

kQ

10

1kHz

-1.0

1.0

dB

no signal

-100

100

mV

no signal to OdB

-50

1kHz, + 6dB to -30dB

-0.5

10

-80

1kHz, OdB, CREF = 220JlF

50

mV

+0.5

dB

-65

dB

For operational amplifier
Vo

Output swing

Vp.p, RL = 10kQ

RL

Output load

1kHz

CMR

Input common-mode range

CMRR

Common-mode rejection ratio

Is

Input bias current

Vos

Input offset voltage

Q

600
0
60

VIN = 0.5V - 4.5V

V

Vcc-OA Vcc- 0.2

Vcc

-0.3

V
dB

80
0.3

JlA

10

mV

-10

3

80

90

dB

1

V/Jls
MHz

AVOL

Open-loop gain

RL=10kQ

SR

Slew rate

unity gain

GBW

Bandwidth

unity gain

3

eni

Input voltage noise

BW=20kHz

2.5

JlV

PSRR

Power supply rejection ratio

1kHz, 250mV

60

dB

NOTE:
1. The Ie remains functional down to 2V.

February 1987

4-374

Signetics Linear Products

Preliminary Specification

Low Voltage Compandor

NE575

C15
O.1$o!F

~-=-

C14

GND

10l-lF

r--r:.....,.-::::::-+,~ VIN

VOUT

R4
200

RECTIFIER
4.3k

RECTIFIER
4.3k

C6
10j.lF
VIN

14

o---j t-+,---..

J

13
R8

30k
R7

12

11

GAIN CEll

NOTE,
Left channel in expander mode; right channel in compressor mode.
For additional information, call the factory.

Figure 1. Typical Application

February 1987

4-375

30k

Signetics

Section 5
Data Communications

Linear Products

INDEX
LINE DRIVERS/RECEIVERS
Symbols and Definitions for Line Drivers.......................................................
MC1488
Quad Line Driver................................................................
MC1489/A
Quad Line Receivers...........................................................
AN113
Using the MC148B/14B9 Line Drivers and Receivers .................
NE5170
Octal Line Driver...
.....................................................
NE5180/81
Octal Line Receiver .................................. .................. ........
MODEMS
NE5050
AN1951
NE5080
NE5081
AN195
AN1950

Power Line Modem ............................................................
NE5050: Power Line Modem Application Board Cookbook..........
High-Speed FSK Modem Transmitter (IEEE 802.4) ....................
High-Speed FSK Modem Receiver {IEEE 802.4)...... ..............
Applications Using the NE5080/5081 .... ........ .................... ......
Application of NE5080 and NE5081 With Frequency Deviation
Reduction...... ...... ......... ... .. .... ...... ......... .. ............. ....... ... .. .

FIBER OPTICS
NE/SA/SE5212 Transimpedance Amplifier.....................................................

5-3
5-4
5-8
5-11
5-14
5-21

5-26
5-30
5-44
5-48
5-52
5-60

5-63

Signetics

Symbols and Definitions for
line Drivers

Linear Products

Differential Output Voltage (Vo
or '10 , VT or 'IT)

Input High Threshold Voltage
(VTH)

For a differential line driver (i.e., an RS-422
driver) this is the differential output voltage for
an input voltage which is a logic HIGH (Va) or
LOW (Va). Va is usually measured with no
applied output load while VT is the differential
output voltage with a specified output load.

For a line receiver: the differential input voltage at the transmission line input above
which the output is in a defined logic state.

Enable
For line drivers and receivers having an
ENABLE (or ENABLE) input, the application
of a specified logic voltage to this input will
force the outputs into a high resistance (HighZ) state. In this state, the circuit has a minimal
loading effect on the transmission or bus line
being driven by the output.

Failsafe (FS)
For line receivers having a FAILSAFE (FS)
input, the application of specified voltages to
this input will force the outputs to correspondingly specified logic states, VOFS (defined
below), when fault conditions occur on the
transmission line.

Failsafe Output Voltage (VO FS )
For line receivers: the voltage to which the
outputs are forced when specified fault conditions occur on the transmission line and when
a specified voltage is applied to the FAILSAFE (FS) input.

Hysteresis (VH)
For line receivers: the difference between the
high and low threshold voltages, VTH and VTl
(defined below).

Input Current (lIN)

Input High Voltage (VIH)
The range of input voltages recognized by a
logic input as a logic HIGH.

Input Low Current (IlL>

Input Low Threshold Voltage
(VTL>

Output Short-Circuit Current
(los)

For a line receiver: the differential input voltage below which the output is in a defined
logic state.

Input Low Voltage (VIL>
The range of input voltages recognized by a
logic input as a logic LOW.

Input Resistance (RIN)
For a line receiver: the DC resistance of the
transmission line input over a specified input
voltage range.

Mode
For line drivers having a MODE input the
application of specified voltages to this input
will force the driver outputs to comply with
correspondingly specified EIA transmission
standards, e.g., RS-232 or RS-423.

Open-Circuit Input Voltage
(Vloe)

Input Clamp Voltage (VcL>

Output Current High-Z (10)

Input High Current (IIH)

February 1987

Output Leakage Current (ICEX)
The current flowing into or out of an output
when no power is applied to the circuit. ICEX is
specified at a particular applied output voltage and input conditions.

Output Resistance (ROUT)

For a line receiver: the voltage to which the
transmission line input of the circuit reverts
when no external connection is made at this
input.

The current flowing into or out of a logic input
when a specified logic HIGH voltage is applied to that input.

The LOW voltage at an output (for a driver or
receiver) for specified load conditions, i.e., Rl
or lOUT, and input voltages.

The current flowing into or out of a logic input
when a specified logic LOW voltage is applied
to that input.

For a line receiver: the current flowing into the
transmission line input at a specified input
voltage.
For a line driver: the input voltage applied to
an input below which the driver clamps this
voltage. VCl is specified for a particular current flowing from the driver into the voltage
source.

Output Low Voltage (VoL>

The current flowing into or out of an output
when that output is in a High-Z state (see
ENABLE definition). 10 is specified at a particular applied output Voltage.

Output High Voltage (V OH )
The HIGH voltage at an output (for a driver or
receiver) for specified load conditions, i.e., Rl
or lOUT, and input voltages.

5-3

For a line driver: the output resistance over a
specified output voltage range.

The current flowing into or out of an output
when the output is connected to the generator circuit ground for a line receiver or digital
ground for a line driver.

Output Unbalance Voltage
(IVOHI-lvOLI, IVTI-IVT~
For a line driver: the difference between the
absolute values of VOH and Valor VT and VT.

Output Offset Voltage (Vos or
'los)
For a differential line driver, i.e. RS-422, the
difference between the actual voltage at the
center of the output load and the generator
circuit ground. Vas is measured with VT at the
output and Vas with VT at the output.

Propagation Delay (tpxx)
The time delay between specified reference
points on the input and output waveforms of a
line driver or receiver. The symbol X can be
H, L or Z specifying HIGH, LOW or High-Z,
respectively; i.e., tplz is the propagation delay
for the output of a line driver to change from
an output LOW to a High-Z state after the
application of a signal to the ENABLE input.

Rise and Fall Times (tR and tF)
For a line driver: the time delays between the
10% and 90% points on the rising and falling
output waveforms following a change in the
logic voltage at the input.

MC1488

Signetics

Quad Line Driver
Product Specification

Linear Products

DESCRIPTION

FEATURES

The MC1488 is a quad line driver which
converts standard DTLlTTL input logic
levels through one stage of inversion to
output levels which meet EIA Standard
No. RS-232C and CCITT Recommendation V.24.

• Current limited output: ± 10mA
Typ
• Power-off source impedance:
300n min
• Simple slew rate control with
external capacitor
• Flexible operating supply range
• Inputs are DTL/TTL compatible

PIN CONFIGURATION

APPLICATIONS
• Computer port driver
• Digital transmission over long
lines
• Slew rate control
• TTL/DTL to MOS translation

0, F, N Packages

Vee 1
INPUT1

2

OUTPUT 1

3

INPUT 2A

4

INPUT 28

5

OUTPUT2

6

9

INPUT3A

GNO

7

8

OUTPUT3

'1

OUTPUT 4

TOP VIEW

CIRCUIT SCHEMATIC
v+
R2
6.2K

R1
B.2K
D1

V

..... 02

INPUT
INPUT

""

R3
70<>

D2

D3
,

.. D9

RB
3001l
OUTPUT

D4

--

D6~ ,

~

DS

R4
3.6K

"

DB

01>-":'

v'

..... 03

V

'"

04

05.........

,rt

RS
10K

R6
7K

R7
700

v1/4 CIRCUIT

November 14, 1966

5-4

653-0933 66552

Product Specification

Signetics Linear Products

MC1488

Quad Line Driver

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

o to
o to
o to

14-Pin Plastic SO
14-Pin Plastic DIP
14-Pin Ceramic DIP

ORDER CODE

+75'C

MC1488D

+75'C

MC1488N

+75'C

MC1488F

ABSOLUTE MAXIMUM RATINGS
SYMBOL

Vee

PARAMETER

RATING

UNIT

Supply voltage V+

+15

V

V-

-15

V

-15 «VIN « 7.0

V

±15

V

1190
1420
1040

mW
mW
mW

VIN

Input voltage

VOUT

Output voltage

PD

Maximum power dissipation,
(still-air)1
F package
N package
D package

TA

= 25'C

TA

Operating ambient temperature range

TSTG

Storage temperature range

TSOLD

Lead soldering temperature (10sec max)

NOTE:
1. Derate above
F package
N package
D package

o to

+75

'C

300

'C

25'e, at the following rates:
at 9.5mW I'e.
at 11.4mW I'C.
at 8.3mW I'e.

November 14, 1986

'C

-65 to +150

5-5

Product Specification

Signetics Linear Products

MC1488

Quad Line Driver

DC AND AC ELECTRICAL CHARACTERISTICS v+ = + 9.0V

± 1%, V- = -9.0V ± 1%, TA = O'C to + 75'C, unless otherwise
specifed. All typicals are for V+ = 9.0V, V- = -9.0V, and TA = 25'C1.

LIMITS
SYMBOL

PARAMETER

UNIT

TEST CONDITIONS
Min

VIH
VIL

Logic "0" input current
Logic "1" input current

VOH

High level output voltage

VOL

Low level output voltage

Isc+

High level output
short-circuit current

Isc-

Low level output
short-circuit current

ROUT

Output resistance

1+

1-

VIN = OV
VIN = +5.0V
V+ = 9.0V
V- = -9.0V

Typ

Max

-1.0
0.005

-1.6
10.0

mA
/lA

6.0

7.0

V

9.0

10.5

V

-6.0

-6.B

V

-9.0

-10.5

V

VOUT= OV
VIN = O.BV

-6.0

-10.0

-12.0

mA

VOUT= OV
VIN = 1.9V

5.0

10.0

12.0

mA

V+ =V- =OV
Vo uT =±2V

300

RL = 3.0kQ
VIN = O.BV

V+ = 13.2V
V- = -13.2V
V+ = 9.0V
V- = -9.0V

RL = 3.0kQ
VIN = 1.9V

V+ = 13.2V
V- = -13.2V

Q

VIN = 1.9V

V+ = 9.0V, V- = -9.0V
V+ = 12V, V- =-12V
V+ = 15V, V- = -15V

15.0
19.0
25.0

20.0
25.0
34.0

mA
mA
mA

VIN = O.BV

V+ = 9.0V, V- = -9.0V
V+ = 12V, V- = -12V
V+ = 15V, V- = -15V

4.5
5.5
B.O

6.0
7.0
12.0

mA
mA
mA

VIN = 1.9V

V+ = 9.0V, V- = -9.0V
V+ = 12V, V- = -12V
V+ = 15V, V- = -15V

-13.0
-1B.0
-25.0

-17.0
-23.0
-34.0

mA
mA
mA

VIN = O.BV

V+ = 9.0V, V- = -9.0V
V+ = 12V, V- = -12V
V+ = 15V, V- =-15V

-1
-1
-0.01

-15
-15
-2.5

mA

1190
1420
1040

mW
mW
mW

Positive supply current
(output open)

Negative supply current
(output open)

!1A
!1A

Po

Maximum power dissipation, TA = 25'C (still-air)2
F package
N package
D package

tp01

Propagation delay to "1"

RL = 3.0kQ, CL = 15pF, T A = 25'C

275

560

ns

tpoo

Propagation delay to "0"

RL = 3.0kQ, CL = 15pF, TA = 25'C

70

175

ns

tR

Rise time

RL

CL = 15pF, TA = 25'C

75

100

ns

tF

Fall time

= 3.0kQ,
RL = 3.0kQ,

CL = 15pF, T A = 25'C

40

75

ns

NOTE:
1. Voltage values shown are with respect to network ground terminal. Positive current is defined as current into the referenced pin.
2. Derate above 25"C, at the following rates:

rc.
rc.

F package a1 9.5mW
N package a1 11.4mW
o package at B.3mWrC.

November 14, 19B6

5-6

Signetics Linear Products

Product Specification

Quad Line Driver

MC1488

TYPICAL PERFORMANCE CHARACTERISTICS

:c
S

I-

z

w
a:
a:
::>
u

..
I-

15

I.l.

12

\

9 1\
6
\

3
0

::>

-3

I-

-6

::>

0

I

\

V+ =9Y)'
V-=-9V

\
\

t\ -

-15

-16 -12 - 8 - 4

0

6

12

!

1/4 MC1489J

MCl489A

CArE

-j--

INTERNAL DATA
TERMINAL
EQUIPMENT

\
4

p-

--«-i:y
.

\

:}D-+~

1/4 MC1488

T2UDTL

\

\

- ......

INTERCONNECTING

-9

.9 -12

=::t. ....
T 2UDTL

V+ -12V
-12V
V-

16

Vo OUTPUT VOLTAGE (V)

*

SIGNAL GROUND

-=-

NOTE:
*Optional for noise filtering

Output Voltage and Current-Limiting
Characteristics

AC LOAD CIRCUIT

RS-232C Data Transmission

APPLICATIONS

TYPICAL APPLICATIONS

By connecting a capacitor to each driver
output the slew rate can be controlled utilizing
the output current-limiting characteristics of
the MC1488. For a set slew rate the appropriate capacitor value may be calculated using
the following relationship

+12V
MOS
OUTPUT
-10VTQ
-O.4V

DTU

TTL
INPUT
10K

C ~ IsdAT/AV)
NOTE:
*CL includes probe and jig capacitance.

SWITCHING WAVEFORMS

where C is the required capacitor. Isc is the
short-circuit current value. and AV/AT is the
slew rate.
RS-232C specifies that the output slew rate
must not exceed 30V / I1s. Using the worstcase output short-circuit current of 12mA in
the above equation. calculations result in a
required capacitor of 400pF connected to
each output.

-12V

-12V

DTL/TTL-to-MOS Translator

1r
m
+12V

/4MC1466

DTLI

TTL

INPUT

HTL
OUTPUT
-O.7V TO

+10V

-12V

NOTE:
tR and tF are measured between 10% and 90% of
the output waveform.

DTL/TTL-to-HTL Translator
+12V

DTU

TTL
INPUT

/4MCl486

RTL
OUTPUT
-O.7V TO

+3.7V

-12V

+ 3.0V

DTL/TTL-to-RTL Translator

November 14. 1986

5-7

•

MC1489/MC1489A

Signefics

Quad Line Receivers
Product Specification

Linear Products
DESCRIPTION

FEATURES

The MC1489/MC1489A are quad line
receivers designed to interface data terminal equipment with data communications equipment. They are constructed
on a single monolithic silicon chip.
These devices satisfy the specifications
of EIA standard No. RS-232C.

• Four totally separate receivers
per package
• Programmable threshold
• Built-in input threshold hysteresis
• "Fail safe" operating mode
• Inputs withstand ± 30V

PIN CONFIGURATION
D, F, N Package

APPLICATIONS
• Computer port inputs
• Modems
• Eliminating noise in digital
circuitry
• MOS-to-TTL/OTL translation

RESPONSE
CONfROl

~

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

o to
o to
o to
o to
o to
o to

14-Pin Plastic DIP
14-Pin Plastic DIP
14-Pin Cerdip
14-Pin Cerdip
14-Pin Plastic SO
14-Pin Plastic SO

ORDER CODE

+70°C

MC1489N

+70°C

MC1489AN

+70°C

MC1489F

+70°C

MC1489AF

+70°C

MC1489D

+70°C

MC1489AD

EQUIVALENT SCHEMATIC
'cc

(14 OF UNIT SHOWN)

,K

5K

'K

r---o

RF

RESPONSE
co"n~ol..

OUTPUT

--K
INPUT ""-

~

.

V

""

~

10K

"NO
LD06411S

NOTES:
1. MC1489: R,

~

10k!1

2. MC1489A: RF" 2kn

November 14, 1986

5-8

853-0934 86552

Signetics linear Products

Product Specification

Quad Line Receivers

MC1489/MC1489A

ABSOLUTE MAXIMUM RATINGS
SYMBOL

VOLTAGE WAVEFORMS

PARAMETER

RATING

UNIT

10

V

----"

Vce

Power supply voltage

VIN

Input voltage range

±30

V

lOUT

Output load current

20

mA

INPUT
ouTPUT

Maximum power dissipation,
TA = 25°C (still-air) 1
F package
N package
D package

Po

TA

Operating temperature range

TSTG

Storage temperature range

1190
1420
1040

mW
mW
mW

o to +75

°C

-65 to +150

°C

~
"
I
I
-11-"
--1

DW

1- "
90

NOTE:
1. Derate above 25°C, at the following rates:

F package at g,5mW I'C
N package at 11.4mW I'C
D package at 8.3mW I'C

DC ELECTRICAL CHARACTERISTICS

Vee=5.0V ±1%, 0°C-

INTERCONNECTING
114MC14891

TTUOTl

-

--

TTl,OTL

)o--t------..---+--C><>--:[ .....)0--

.....

CABLE

Ir - -

MC1489A

-c(-~-----<:>(]--+----'-----t--c(
-.j--

DA T A

I

1,4 Me 1489
SIGNAL GROUND

~~~e,:,~~~E

'H>o-f"-r-[:'
"'""

MOSlOGIC

L _ _ .....J

114MC1488

Me 1489A

o

~
MODEM

eOUIPMENT

NOTE:
*Optional for noise filtering

RS-232C Data Transmission

November 14, 1986

I [r\
I
..,

MOS-to-TTL/DTL Translator

5-10

Signetics

AN113
Using the MC1488/1489 Line
Drivers and Receivers
Application Note

Linear Products

LINE DRIVERS AND RECEIVERS
Many types of line drivers and receivers are
available today. Each device has been designed to meet specific criteria. For instance,
the device may be extremely wide-band or be
intended for use in party line systems. Some
include built-in hysteresis in the receiver while
others do not.

The EIA Standard
The Electronic Industries Association (EIA)
has produced a number of specifications
dealing with the transmission of data between
data terminal and communications equipment. One of these is EIA Standard RS-232C,
which delineates much information about signallevels and hardware configurations in data
systems.

MC1488/1489
As line driver and receiver, the MC1488 and
MC1489 meet or exceed the RS-232C specification.
Standard RS-232C defines, the voltage level
as being from 5 to 15V with positive voltage
representing a logic O. The MC1488 meets
these requirements when loaded with resistors from 3k to 7k.l1.
Output slew rates are limited by RS-232C to
30Vl /-IS. To accomplish this specification, the
MC1488 is loaded at its output by capacitance as shown by the typical hook-up diagram of Figure 1. A graph of slew rate vs
output capacitance is given in Figure 2. For
the standard 30V / /-IS, a capacitance of 400pF
is selected.

February 1987

The short-circuit current charges the capacitance with the relationship
IscLlT
c=-LlV

Where C is the required capacitor, Isc is the
short-circuit current value, and LlV/ LlT is the
slew rate.
USing the worst-case output short-circuit current of 12mA in the above equation, calculations result in a required capacitor of 400pF
connected to each output to limit the output
slew rate to 30V / /-IS in accordance with the
EIA standard.
The EIA standard also states that output
shorts to any other conductor of the cable
must not damage the driver. Thus, the
MC1488 is designed such that the output will
withstand shorts to other conductors indefinitely even if these conductors are at worstcase voltage levels. In addition to output
protection, the MC1488 includes a 300.11,
resistor to ensure that the output impedance
of the driver will be at least 300.11, even if the
power supply is turned off. In cases where
power supply malfunction produces a low
impedance to ground, the 300.11 resistors are
shorted to ground also. Output shorts then
can cause excessive power dissipation. To
prevent this, series diodes should be included
in both supply lines as pictured in Figure 3.
The companion receiver, MC1489, is also
designed to meet RS-232C specifications for
receivers. It must detect a voltage from ± 3 to
± 25V as logic signals but cannot generate an
input differential voltage of greater than 2V

5-11

should its inputs become open circuited.
Noise and spurious signals are rejected by
incorporating positive feedback internally to
produce hysteresis. Featured also in the receiver is an external response node so that
the threshold may be externally varied to fit
the application. Figure 4 shows the shift in
high and low trip points as a function of the
programming resistance.

APPLICATIONS
The design of the MC1488 and MC1489
makes them very versatile with many possible
applications. The MC1488 output current limiting enables the user to define the output
voltage levels independent of supply voltages. Figure 5 shows the MC1488 as a TTLto-MOS Translator, while Figures 6 and 7
illustrate TTL-to-HTL and TTL-to-MOS Translators.
The MC1489 response control node allows
the user to modify the input threshold voltage
levels. This is accomplished by adding a
resistor between the response control pin
and an external power supply. Figure 4 shows
the shift thus provided. This feature and the
fact that the inputs are designed to withstand
± 30V permit the use of the MC1489 for level
translation as shown in the MOS-to-TTL
Translator of Figure 8. This feature is also
useful for level shifting, as illustrated in Figure
9.
The response control node can also be used
to filter out high frequency, high energy noise
pulses. Figures 10 and 11 give typical noise
pulse rejection curves for various sized external capacitors.

I

Signetics Linear Products

Application Note

AN113

Using the MC1488/1489 Line Drivers and Receivers

,
,

I I

,

"
1-,,"
,°r<-5V
''"
g
~ ,,
~

" :'J r- "
'"

111';

':sT~

I--'r.

r- r--''"sv r-

"

-=-

o
>

vTI-1

f

§

'.0

,

l-

vi L' V'H\

I

.,
Figure 1. Typical Line Driver-Receiver Application

.1.0
VIN INPUT VOLTAGE [Vdel

,
,

l

,
,
,

:~
~l~

1--1- ~

-

"
'"
~5T~

}
~

,

I

I

,

I-o

CAPACITANCE (PF)

- - - - -r - -

(? 14
'-"-1
I MCl488L I
I r-

O'r:_)c>-t-<)
c.. t'~ I ~
CrT->- -~.,-

-r -)oJ.n
~l ~.::. I·

0- I

~t~_)o1·()
LT

.,J

9' ~"

~I
VEE

0---1. .--<>-----...... - - - - - ~ - -

Figure 3. Protection From Power Supply Malfunction

February 1987

_1.0

.2.0

"-

_30

;ill

'4.0

\!IN INPUT VOL TAGE lWei

Figure 2. Output Slew Rate vs Load Capacitance

Vee o----I*"~~------1~

"

"=,,,VTH

5-12

Figure 4. Hysteresis as a Function of
Programming Resistance

Signetics Linear Products

Application Note

AN113

Using the MC1488/1489 Line Drivers and Receivers

+12V

MOS
OUTPUT
-10V TO
-0.4V

TTL
INPUT
10K

-12V

-12V

Figure 5. TTL-to-MOS Translator

NOTE,
1. V2 9V

L

H

-5 to -6V

-5 to -6V

";;-9V

H

X

High-Z

High-Z

High-Z

NOTES:

1. Vcc-+lOV and VEE--10V; RL -3kil
2. Vcc-+12V and VEE=-12V; RL-3kil

ORDERING CODE
DESCRIPTION

28-Pin Plastic DIP
28-Pin PLCC
24-Pin SO package

RSL Ne Ne NC NC I GND
-MODE

TEMPERATURE RANGE

o to
o to
o to

ORDER CODE

+70·C

NE5170N

+70·C

NE5170A

+70·C

NE5170D

TOP VIEW

D Package

lOPVJEW

February 1987

5-14

Signetics Linear Products

Preliminary Specification

Octal Line Driver

NE5170

ABSOLUTE MAXIMUM RATINGS
RATING

UNIT

Vee

SYMBOL

Supply voltage and + MODE

PARAMETER

15

V

VEE

Supply voltage and - MODE

-15

V

lOUT

Output current 1

± 150

mA

-t.5 to +7

V

VIN

Input voltage (Enable, Data)

VOUT

Output voltage2
Minimum slew resistor 3

PD

Power dissipation

±15

V

1

kn

1200

mW

DC ELECTRICAL CHARACTERISTICS Vee=10V ±10%; VEE=-10V ±10%; ±MODES = OV; RSL= 2kn, 0°C 4kn

RSL

8

12

RSL

0.8

1.2

0.06

0.14

use either RL = 450n, CL = 50pF or RL = 3kn, CL = 2500pF.

AC PARAMETER TEST CIRCUIT AND WAVEFORMS
+ 10V

Vee
VOUT

RSL

RSL

-10V

r-

:~
ov

VOUT

~
I
I
I

I

I

I

I

I
11V

:

:

1

VOL ___ .J.._I'--:--_ _~r'!

: :t

-I

t- tpZL

t:

1- tpLZ

NOTES:
1. See AC electrical characteristics table for values of RSL, RL and CL.
2. VIN pulse: Frequency = 1kHz, duty cycle = 50%, ZOUT = 50n, tr = tl '" 1Ons.

February 1987

5-16

-_---<>

1-.....

V,N

V/IlS

OUTPUT

Preliminary Specification

Signetics Linear Products

NE5170

Octal line Driver

SLEW RATE PROGRAMMING
Slew rate for the NE5170 is set using a single
external resistor connected between the RSL
pin and ground. Adjustment is made according to the formula:
20
RSL (in kn) = - - Slew Rate
where the slew rate is in V I Jls. The slew
resistor can vary between 2 and 200kn which
gives a slew rate range of 10 to 0.1 VI JlS. This
adjustment of the slew rate allows tailoring
output characteristics to recommendations
for cable length and data rate found in EIA

standard RS-423A. Approximations for cable
length and data rate are given by:
Max. data rate (in kb/s) = 300/t
Cable length (in feet)

= 100

X t

where t is the rise time in microseconds. The
absolute maximum data rate is 100kb/s and
the absolute maximum cable length is 4000
feel.

OUTPUT MODE PROGRAMMING

levels. The low output mode meets the specifications of EIA standards RS-423A and RS232C. The high output mode meets the specifications of RS-232C only, since higher output
voltages result from programming this mode.
The high output mode provides the greater
output voltages where higher attenuation levels must be tolerated. Programming the high
output mode is accomplished by connecting
the +MODE pin to Vee and the -MODE pin
to VEE. The low output mode results when
both of these pins are connected to ground.

The NE5170 has two programmable output
modes which provide different output voltage

APPLICATION

r-------------,I
I

+v,
-v

I
I
I

r

L...J

I
I
I

I
I

I
I

i.

TIE TO GROUND FOR
~ RS232C

I

I
r.... _ _ _ _ _ _ _VEE
_ _ _ _ _ .JI

I
I
I

_ _ _ _ _ _ _ _ _ _ _ _ _ .JI

• MODE PINS CONNECTED FOR
PROPER OUTPUT LEVEL

Figure 1. RS-232C/RS-423A Data Transmission

February 1987

I

5·17

Signetics Linear Products

Preliminary Specification

NE5170

Octal line Driver

INPUT O-t-f4---t:=--*-~1-+

Figure 2. Input Stage Schematic

February 1987

5-18

Signetics Linear Products

Preliminary Specification

Octal Line Driver

NE5170

NE5170

Vee

, . - - - - - - - - i f - - - - i 1-_---+--0 OUTPUT

Figure 3. Output Stage Schematic

February 1987

5-19

Signetics Linear Products

Preliminary Specification

NE5170

Octal Line Driver

45

MODE=9ND;RsL =2kQ;
IN=H; EN:L;OUT=NO LOAD

41

r-

:if

g

-,1

E

I--- -

O'C

"z

33

I
I

29 -

j!~
"I'

.......

.1::11

::12

.J
- VEE-O.SV

(V =

±13

~

Vee AND VEE (V)

Figure 4. Typical Icc and lEE
Voltages

VS

Supply

-400

-600 _,

RL =450Q-

-5.5

I

-6.0

Figure 10. Typical Output Low Voltage
vs Temperature

20

6.0

40

30

50

v~ = ~9V/RsL ~ 2JQ, thw ~OD:E+

~
x. 5.0
~

-4 Vs =:t:9V. ::t:11V,
LDWMODE

,

-8

HIGHMOD~

TA

Figure 5. Typical Input Current vs Input
Voltage

800

.1 I I. I I
-

O'C

100

"

16

20

V +MOoe(V)

Figure 6. Typical + MODE Current vs
+ MODE Voltage

February 1987

/-- VSi'T' j"V,ll.Oi M,DE

-

TA =25'ci RsL I= 2~Q; l~puf=0:8V

±10V.JlWMODE,0·C~'~A ~ 70'C

10

~

1\

~
iil

I I I I I

70 Ge

8

20 VS=

It
a:

-

70

Figure 11. Typical Output High Voltage
vs Temperature

10

I

.J

50

1

Vs= ±9V, HIGH MODE

:-

I
I

4.0

=250C;R~L =kk2;IINPUT=2V

Vs = :t13V. HIGH MODE

Vcc +O.5V

r-

-

Figure 8. Typical Output Low Voltage
vs Load Current

(V! = ~'0J;Rs~ =2~Q)

o
o

Vs= ±13\1,

HIGH MODE

-12

..!AL =4502

4.5

Vs= ±9V,

-10

NO~

--

-2

1./

70

50

-1000

5.5

(

r-

tti- r-

-800

I

10

-2

800

"I

~

tOL (mA)

o

o

0

-200

I

~-5.0

2

:lOJ; R I =2~Q)
I

~
g

Figure 7. Typical - MODE Current vs
-MODE Voltage

v~= ~'0J.0.d..TA~70JC

200

l_1!.

-400

I

25

400

-200

~.

I

I--- -

v~= :t.,9V;ASl =2kQ,LOWMODE_ r-

0.0
-4.5

I

70~C
±10

0

/

701·C

O'C

Icc

±9

-5

I I(

70;C

ltl

'jl"

-10

I

37

-4.0

V_MODEM

-15

-20

I--- -

-~

-~

-~

-~

-ID

0.2

o

o

IOH(mA)

Figure 9. Typical Output High Voltage
vs Load Current

5-20

0.1

1

10

20

RSL (kQ)

"

100 200

Figure 12. Typical Slew Rate vs RSL

NE5180/NE5181

Signetics

Octal Differential Line
Receivers
Preliminary Specification

Linear Products
DESCRIPTION

FEATURES

The NE5180 and NE5181 are octal line
receivers designed to interface data terminal equipment with data communications equipment. These devices meet
the requirements of EIA standards RS232C, RS-423A, RS-422A, and CCITT
V.10, V.11, V.28, X.26 and X.27. The
NE5180 is intended for use where the
data transmission rate is up to 200 kb/ s.
The NE5181 covers the entire range of
data rates up to 10 Mb/s. The difference
in data rates for the two devices results
from the input filtering of the NE5180.
These devices also provide a failsafe
feature which protects against certain
input fault conditions.

• Meets EIA RS-232C/423A1422A
and CCITT V.10, V.11, V.28

•
•
•
•

Vee
Ho
H+

Failsafe feature
Input noise filter (NE5180 only)
Internal hysteresis
Available in SMD PLCC

HGo
G+
GFS,

APPLICATIONS

Fo

• High-speed modems
• High-speed parallel
communications
• Computer 110 ports
• Logic level translation

Co

D+

LOGIC
OUTPUT

X

H

X

L

> 200my 1
YIO < -200my 1

F+

•
I

F-

FAILSAFE
INPUT

YID

Both inputs open or grounded

N Package

• Single + 5V supply - TTL
compatible outputs
• Differential inputs withstand
±25V

FUNCTION TABLE
INPUT

PIN CONFIGURATIONS

Eo

Do

E+

GND

E-

I,

TOP VIEW

A Package
B- Ao A+ A- Vee Ho H+

OY

L

H-

Yee

H

Go

NOTE:

G+

1. VIO is defined as the

non~inverting

terminal input voltage minus the inverting terminal input voltage.

G-

ORDERING INFORMATION
DESCRIPTION

28-Pin Plastic DIP
28-Pin Plastic DIP
28-Pin PLCC
28-Pin PLCC

February 1987

FS,

TEMPERATURE RANGE

o to
o to
o to
o to

Fo

ORDER CODE

F+

+70·C

NE5t80N

+70·C

NE5181 N

+ 70·C

NE5180A

0+ 00 GND E- E+ Eo F-

+70·C

NE5181A

TOP VIEW

5-21

Signetics Linear Products

Preliminary Specification

NE5180/NE5181

Octal Differential line Receivers

ABSOLUTE MAXIMUM RATINGS TA = + 25'C
Your

SYMBOL

PARAMETER

RATING

UNIT

BOO

mW

Power dissipation

PD
Vcc

Supply voltage

7

V

VCM

Common-mode range

±15

V

VID

Differential input voltage

±25

V

ISINK

Output sink current

50

mA

VFs

Failsafe voltage

los

Output short-circuit time

-0.3 to Vee

V

1

sec

FS=Vcc

FS=GNO

Figure 1. VII> VIh, VH Definitions

DC ELECTRICAL CHARACTERISTICS Vee = + 5V ± 5%, O'C < TA < + 70'C, input common-mode range
NE5180
SYMBOL

PARAMETER

VOFS

NE5181

TEST CONDITIONS

UNIT
Min

RIN

± 7V

DC input resistance

3V < IVIN I <25V

Failsafe output voltage

Inputs open or
shorted to
GND

3

I 0<

lOUT < BmA, Vfallsafe = OV

I 0> lOUT> -400/JA,

Max

Min

7

3

0.45

Max

7

kn

0.45
V

Vfallsafe = Vee

2.7

2.7

Rs =01

0.2

0.2

Rs = 500 1

0.4

0.4

VTH

Differential input high 4
threshold

VOUT> 2.7V,
lOUT = -440/JA

VII

Differential input low4
threshold

VOUT < 0.45V,
lOUT = BmA

VH

Hysteresis4

FS = OV or Vee (See Figure 1 )

Viae

Open-circuit input voltage

2

2

V

CI

Input capacitance

30

30

pF

VOH

High level output voltage

RS=01

-0.2

-0.2

Rs = 500 1

-0.4

-0.4

50

2.7

VID = lV, lOUT = -440/JA
lOUT = 4mA2

VOL

Low level output voltage

VID = -lV

los

Short-circuit output current

VID = lV, Note 3

lee

Supply current

4.75V  1kV typical),
line impedance modulation, and other factors,
have prohibited its use as an effective medium for transmitting data and control signals.
The NE5050 Power Line Modem (PLM) has
been designed to overcome these problems
while affording the user the flexibility of tailoring the design to his/her own needs. The
PLM can be used to transmit over power lines
or twisted-pair cables using two forms of
modulation - carrier on/off ASK (Amplitude
Shift-Keying) and non-coherent FSK (Frequency Shift-Keying). To use it in the FSK
mode, two devices will be required for each
transceiver in order to bandpass and generate the two different frequencies representing
logical 0 and 1. If one of the two frequencies
used fails, the remaining frequency can be
used in the ASK mode. The applications
referred to in this cookbook only refer to the
single-carrier ASK form. Some of the features
of the IC include:
Llsten-Whlle-Talk
The modem is always in the receive mode,
even when transmitting (it receives its own
signal). This capability permits RX and TX
remote functionality testing for each system
node since it requires no other transceivers.
In the receive mode, the modem receives
carrier signals from other transmitters. In the
transmit mode, the IC transmits an ASK
carrier to the other receivers, including its
own. It is up to the user to design protocol to
arbitrate ownership of the line. In some protocols, such as in General Electric's HOMENET, the listen-while-talk feature is not desired
and so the receiver is disabled during transmission mode.
On-Chip Collision Detection
The listen-while-talk capability enables a controller to perform CSMA/CD (Carrier Sense,
Multiple Access/Collision Detect) functions.
To summarize (for further information, the
reader is referred to IEEE 802.3 and to
general articles describing ETHERNET or
other probabilistic network protocols), any

5-30

node can access the line to transmit signals
at any time provided the line is not being
used. The procedure is as follows. A receiver
listens to the line to see if there are any
carriers present (Carrier Sense). Every receiver is also listening to the line (hence, Multiple
Access). If a transmitter is on, each node
waits until the line is free before transmitting.
Priorities may be established by the controller. A collision is detected if, while transmitting a message, an incoming transmission
originating from another node is detected.
The PLM performs a similar operation for
both dense and rare data traffic situations. In
dense data traffic, the RX data output
(RXOUT) does not have time to go into the
standby (low power consumption, inverted
logic mode). In this case, the RXOUT is in
positive logic (carrier on = 1, carrier off = 0).
A collision is detected at the local node when
the local TX is off and the local RXOUT = 1.
Therefore, a remote carrier is present and
has been detected, so abort local transmission. The line is busy. Wait until the line is
clear.
In rare data traffic, the RXOUT is usually in the
standby mode. In this case, the RXOUT logic
mode is inverted due to a designed-in offset
present in the AM rejection and impulse filter
circuits. A "10" logic sequence from the local
TX insures proper RX offset adjustment (the
preamble contains the first two "10" bits) and
collision detection can be performed with the
next "10" bits. The collision detection proceeds as in the dense data traffic case. The
transition time from the last received bit" 1"
to the standby mode is typically 4 seconds
and this time is independent of the data rate.
This enables long strings of "O's" to be
transmitted and received.
To eliminate the standby mode and to have
the modem in the receive-data mode at all
times, the bias at Pin 9 should be altered. A
1OMf2 resistor from Pin 9 to a potential of
2.2V DC will perform this change. The 2.2V
potential may be generated between two
resistors: 1Mf2 from Vee = 12V and 220kf2
to ground.

Power Supply Decoupling (C1
and C2)
Capacitor C1 = 0.11lF at Pin 1 decouples the
supply voltage, Vee. The capaCitor
C2 = 0.11lF at Pin 14 is optional and decoupies the supply for the oscillator section. This

Signetics Linear Products

Application Note

AN1951

NE5050 Power Line Modem Application Board Cookbook

GND

PNP

OUT,

IN,

FEEDBACK

NPN

VCc /2:LC

LC

CFO

RXoUT

10
C HPF

Figure 1_ Block Diagram

essential for clean operation and should be
placed as close as possible to the IC, between Pins 1 and 18,

AC Line Coupling
The line transformer, a Toko America 707VXT1002N, has a primary-to-secondary coil ratio, L1 :L2, of 1:1. One end of coil L1 goes to
the power line via line capacitor CLINE. The
secondary signal is tapped off between L2
and L3 and then goes to the receive input (Pin
20.) The other turn ratio is L1 :L3 at 1:4. The L2
secondary is connected between Pins 1 (Vee)
and 20 (RXIN). It carries about 1mA DC
current into Pin 20 for biasing. The L2 + L3
secondary is tuned to the carrier frequency by
a tuning capacitor CruNE = 6.8pF. This transformer is suitable only for data rates up to
10kbits/sec because of envelope distortion.
To tune the transformer for maximum sensitivity, connect a SNC "T" connector to the
output of the waveform generator. One output
should go to an oscilloscope and the other
should be connected to the prongs of the
power cord of the board (make sure ground is
also connected to one prong). Then send the
100% AM modulated pulse train (ASK) to the
board. The carrier envelope is a square-wave
pattern. Tune the transformer for maximum
carrier amplitude. To do this take a jewelhead screwdriver and adjust the transformer
core. Maximum sensitivity is reached at maximum amplitude at the carrier frequency.
Another manufacturer that provides good
transformers for both power line and twistedpair communication is AlE Magnetics (Address and telephone numbers for TOKO and
AlE Magnetics are listed in the External
Components Section).
February 1987

Line and Tuning Capacitors
(CLINE and CTUNE)
CLINE = 1/1F AC-couples the transformer to
the power line and is rated to withstand 600V.
Its main function is to filter out the 60 and
120Hz signals from the line power and to
pass only the higher frequency carrier signals.
CLINE and the primary inductance of the
transformer act as a voltage divider that
attenuates 60Hz signals by 100dS. Line voltage signals are less than a millivolt on the
secondary of the coupling transformer. Remember to discharge this capacitor before
removing the insulating backplane and
changing components.
CruNE = 6.8nF tunes the transformer secondary winding to the carrier frequency (100kHz).
Make sure to change this capacitor in addition to the LCs of the oscillator and bandpass filter sections when changing the carrier
frequency.

TRANSCEIVER EXTERNAL
COMPONENTS
Figure 1 is a block diagram of the NE5050. It
comes in a 20-pin DIP (Dual In-Place package) in both plastic and SO (Small Outline).
This section describes the external components that must be added and the characteristics to expect at those pins.

frequency. The input amplifier bandpass characteristic has an upper -3dS frequency internally fixed. The lower -3dS frequency is set
by CHPF. CHPF actually suppresses the lower
order harmonics. With CHPF = 100nF, 60 and
120Hz are rejected more than 40dS (see
Figure 2). For lower values of CHPF, this
rejection increases along the frequency spectrum. For a 1nF capacitor, amplifier response
has large peaking near 500kHz. Response for
values of 10, 100, and 1000nF are also
shown over the frequency range
0.Q1 - 100MHz.
CHPF is connected from Pin 2 to ground. For
carrier frequencies above 100kHz, typical
values for CHPF are between 2 and 20nF. The
amplifier has differential outputs (Pins 3 and
6). The DC voltage at these pins is 4.6V.
Inter-Stage Bandpass Filter R 1, R2,
CSPF, LSPF (Pins 3, 4, 5, 6)

If all necessary bandpass filtering is performed in the line-coupling network, then the
SPF between input amplifier output and AM
detector input is not needed. It is also possible to bypass use of the filter in most twistedpair applications. Otherwise, for ASK operation, LBPF and CBPF should match the LC tank
components Lose and Case of the oscillator
in order to have effective carrier sense. The
carrier frequency is simply defined as
1

Receiver
Input Filter CHPF (Pin 2)
The input amplifier limits its output signals to
1.2Vp_p differential. On Pin 20, the maximum
input carrier signal can be 70Vp_p, centered at
Vee. The amplifier gain is 24dS at the carrier

5-31

The bandpass characteristics are governed
by the following equations relating 3dS bandwidth to carrier frequency WC;XR and components R1, R2 = R, LBPF , and CBPF .

•

Application Note

Signetics Linear Products

AN1951

NE5050 Power Line Modem Application Board Cookbook

reduced data rate, increase COET (see Figure
60
50

4).

If COET is removed altogether, a reduction in
Signal delay should be observed (full-wave
rectification). There will still be a Signal if the
impulse capacitor is connected. Removing
both COET and CIMP should eliminate signal
delay entirely.

40

iii'

30

~

20

~
ffi

10
0
-10

§
0.-20
!i_ 30

l_F
1OO_F
,1OnF" "
-lnF" X

-40

-50
-60
0-01

y/ /
k' /
/
y
/ /

X

..\.

\
\

/

/' X Y /
>( / '
/
. / / L ;Y

\

Probing at this point (Pins 7 and 8) should
reveal a square wave with rising edges following a 1 - exp(-tlRCOET) type of curve. Similarly, the falling edge should show an
(exp(-tlRCOET)) type of characteristic. Probing on the complementary pin will just show
the inversion of the signal. This should be
expected since just the charging and discharging of the detection capacitor are being
observed.

1\

\. J\ \
_\
\.
1.0'

to'

1.0"

1.0

FREQUENCY (Hz)
Figure 2. Receiver AmpUfler Gain vs Frequency for Different Values of CHPF

x LSPF)
(2 X R)

(WCXR 2

BW- 3d S =

tions. For more details on alternative BPFs,
see the section on High Performance Industrial Operation.

1
BW-3dB = (CBPF X 2 X R)

These equations can easily be manipulated to
express the Quality factor, Q:
BW-3dS = (WCXR X LSPF)
Q

(2 X R)

wCXR

1

BW_3dS = _ _ _ _ _ _ __
WCXR

(WCXR X CBPF X 2 X R)

Q

Since this is a passive filter, a good deal of
signal attenuation should be expected. If
there is trouble getting signals through, consider shorting out the bandpass by shorting
Pin 3 to Pin 4 and Pin 5 to Pin 6. If this does
not work, trace signal from RXIN (Pin 20) and
follow through.
Depending on the filtering configuration, Pins
4 and 5, the AM detection input requires DC
biasing. If no DC path is provided from Pin 3
to 4 and from 6 to 5 (series capacitors
present for DC open-circuit), then the network
in Figure 3 can be used.
Active bandpass filters may be used if gain is
desired in the signal. This allows more room
for tweaking. Remember, the goal is to bandpass the broadband signal (WCXR = 100kHz
for the industrial operation) and not the baseband signal (1 kbits/s for the same application) as can be seen from the above equaRl
lk
PIN3 ""

R2

lk

PINe

*~.'';.''F

I~

PIN4

AM Detection COET (Pins 7 and 8)
The capacitor COET is the load across the
collectors of a Gilbert multiplier cell (Pins 7
and 8) that is being multiplied by itself. So
compared signals are always in phase and
demodulated output is a function of carrier
amplitude (hence, detects AM signals), bias
current, and collector load. (Internally there
are resistors in the collectors of the cell so
the part will run without COET included.) Since
it is the load, it has to be charged and
discharged, and thus delays the transition of
the signal. COET introduces a delay in Signal
transmission because of its integrating action.
The combination of COET and the collector
resistors provides an RC low-pass filtering
action on the received Signal. The carrier
(broadband) is filtered out and only the envelope (baseband) is passed. Consequently,
COET provides the limiting value for the data
rate. The 4.7nF value is fine for 1kbitlsec
operation, but, if an increased data rate is
desired, the value of the capacitor should be
reduced. Similarly, for a longer delay and

If the received signal remains at the zero
state after a 1-to-0 (on-to-off) transition for
more than 4 seconds, the RXOUT pin will drift
to the logic High level and stay there until the
signal changes state again. This is known as
the standby mode. This feature can be defeated by externally applying a 2.2V DC signal
(see HOMENET application). Any protocol
should take this feature into account if it does
not externally defeat the feature through the
hardware.

60
~

60

III

40

ffi
a:

30

S~

iii
Iii

20

II

10

'Ii

LBPF

S40"H
PIN5

0
10- 3

101

Figure 3. Slngle·Pole Bandpass Filter
For 100kHz Operation

10"

10'

10'

TIME{j.sl

TC10540S

February 1987

AM Rejection CAM (Pin 9)
The AM rejection circuit tracks the average
DC value of the envelope by adding or
subtracting a series voltage to the voltage on
the COET' (It operates as a negative feedback
voltage mechanism for changes on the AM
detector load by the additional DC components on the line.) AM rejection is better than
40dB. CAM = 0.1 MF typical for 40dB rejection
for 120Hz AM. This value will suffice for most
power line applications. For a different case,
look at the Twisted-Pair Applications.

Figure 4. Comparative Delay of AM Detector for Different Values of COET

5·32

Application Note

Signetics Linear Products

NE5050 Power line Modem Application Board Cookbook

Impulse Rejection CIMP (Pin 10)
This capacitor allows the device to absorb the
line transients that sometimes reach peak
values of several thousand volts. It also
reduces the effect of the glitches caused by
different line loads. CIMP is charged or discharged with constant current from the comparator which causes the voltage variation at
Pin 10 to be of constant slope versus time.
Narrow current impulses will not last long
enough to fully charge or discharge CIMP
(lCIMP = CIMP X (t.V / t.T).) The baud rate depends on the size of C1MP. Typically, rejected
impulse width ,,:; C1MP x 35kn (sec)":; minimum data width.

level of AC feedback to the oscillator. It would
only be important in the wideband operation
since it provides a reference for the other end
of the differential pair.) The design equation
for the Wo is (wo should equal WCXR):
1

Wo = v'Lose x CEQ
(Wo

= 27lio)

where CEQ is given by
CFO X CFl
CEQ = COSC + - - - CFO

+ C F1

The delay in recovering data that is introduced by this stage is
tDELAY

= CIMP x

35kn.

If this point is probed, a square wave with a
well-defined slope on the rising and falling
edges should be seen. The slope is a function
of the output current of the comparator and
the capacitance on this pin (lCIMP and CIMP).
Logic Output RpULL (Pin 11)
This is an open-collector output and needs a
pull-up resistor to let it swing to a High value.
The listed value of 10kn is fine. It can be
decreased for a maximum IOL = 10mA. Also
shown in the diagram is an optional supply
VLOGIC = + 5V provided by the user to give
TTL-level compatibility. Otherwise, the output
should swing all the way to + 12V and all the
way down to ground.

The point can be probed while the signal is
transmitted to see if the IC is receiving its own
transmission. Carrier feedthrough may be
seen on the output signal.

Transmitter
The transmitter input (TX 1N) is at Pin 19. A
logic "1" enables the line driver and sends
the carrier on the line. A logic "0" disables
the carrier, which constitutes the on/off Amplitude Shift-Keying. When in the receive
mode, this pin should be grounded. Make
sure that the TX 1N levels are TTL compatible.
Signals that are more than one VBE (0.7V)
below ground turn on a diode that disables
the transmitter. External components to be
set for the transmitter are as follows:
Carrier Frequency (Rose, Cosc, Losc,
CFO, CFIl
The carrier frequency is set internally by a
differential-pair Colpitts Oscillator. To set the
frequency externally, apply the signal to LC
(Pin 13). Pin 13 is the input for external
operation and the load for use of the onboard oscillator.

If an external carrier is not desired, set the
oscillator frequency by the 5 external components listed above. (Note: CFl = 0 in this
application. Increasing it merely raises the
February 1987

Carrier leakage in the off state is minimal and
should have no effect on the receive input,
RXIH (Pin 20).
Output Stage (01, 02, REI, RE2)
The line driver is a class AB push-pull output
stage with optional external complementary
transistor pair for increased current drive
capability. The TX output impedance is 40kn
in the off state (RXON' receive mode) and less
than 2n in the on state (TXoN' transmit
mode).

By itself, the NE5050 is capable of driving a
consumer line impedance of 50n without the
drive transistors 01 and 02. To do this, set
REI = RE2 = 10n, placing REI between Pins
15 and 16, and RE2 between Pins 16 and 17;
select RDRIVE = 50n. The voltage divider effect is evident.
With the external drive tranSistors, however,
the PLM is capable of driving an industria/line
impedance of 1on. Merely set REI =
RE2 = 1n and set RDRIVE = 1on.
Feedback (RFeeDBAcK)
To increase the amplitude of the transmitter,
add a feedback resistor in the driver amplifier
feedback path at Pin 16. RFEEDBACK = 75kn
is fine for Vcc = + 15V operation. For
VCC = + 12V, use a 22kn resistor. If you are
not using external drive transistors and are
using Vcc = + 12V, then use a 56kn resistor.
Transmitter Drive (RDRlve, CORIVel
RDRIVE and CORIVE provide impedance
matching for the output of the driver for
coupling back through the transformer.
RORIVE provides the real component and
CORIVE the complex. RDRIVE should be set to
50n for consumer applications; with no external transistors needed (set REI and RE2 as
above), or for industrial applications, use
RORIVE = Ion with the drive transistors, setting REI and RE2 as indicated.

5-33

AN1951

INDUSTRIAL APPLICATION
Electrical Hazards to the User
WARNING: ELECTRICAL SHOCK
HAZARDI DO NOT PROCEED UNTIL
YOU HA VE READ THIS SECTION !
In addition to being a supply of 11 OV AC, the
power line is a near-infinite source of current
and it only takes 100mA to kill a human being.
(It takes about 80mA to fibrillate the heart and
give a serious shock. Approach the board
testing as though you were going to repair a
television set.) So remember, 110V of AC line
voltage is present on the line cord, the line
coupling capaCitor (CLINE), and on the transformer primary. Please exercise extreme caution when using these boards. Even if the
cord is not plugged into the AC power line,
CLINE can retain charge. After being unplugged, if touched before discharged, it can
give a severe electric shock.
Certain measures have been made to protect
the user from being exposed to the power
line. A silicone resin has been applied to the
line cord on the top of the board and a mylar
plate has been attached via four nuts to the
bottom of the board. Before changing components, please use the following procedure:
1. Unplug the cord from the AC line. Always
use one hand when plugging or unplugging the cord. A good procedure to follow
would be to set the board down first and
then plug it in with the same hand,
keeping the other in your pocket. Holding
the board in one hand (exposed AC) and
the plug in the other could turn you into
the load if you are careless.
2. Discharge the coupling capacitor by holding the unplugged cord by the insulated
portion of the plug and then short the
plug prongs with an insulated screwdriver. Be sure to hold the screwdriver by its
insulated handle. As you touch the
screwdriver to the prongs, you should
hear a slight 'pop' from the discharge. If
you don't hear the pop, it could be an
indication that the line capacitor is bad.
NOTE:
Transient protection must be incorporated between
Pins 1 and 20 when following this procedure (i.e.
8ack-to-Back zeners or transient absorbers).

3.

Remove the plastiC nuts, screws, and the
mylar plate.

4.

After changing components and soldering, replace the nuts and mylar plate.
NEVER operate the board or plug it into
the AC line without the cover. It is very
easy to leave a wire or a piece of solder
on the bench and short the AC line when
you set the board down. This is a possible fire hazard and will usually trip the
circuit breaker for your area, killing the

Signetics Linear Products

Application Note

NE5050 Power line Modem Application Board Cookbook

power in the area. (This actually happened while testing application boards.)
Do not attempt to remove the silicone from
the line cord on the top of the board. This
isolates you from the line while probing the
component side. Do not defeat this safety
feature.

• Increase ASK data rate to 500kbit/sec
• Increase CHPF to 0.1 !-IF; use low carrier
frequencies and low data rates
• Sweep the carrier down to DC
• Decrease the ASK data rate
• Observe the general limitations of the
IC modem

Do not operate on metallic or other types of
conductive surfaces. Always operate with the
mylar plate on the backplane of the board.
Refer to # 4 above for what can happen if
you leave the board off.

Transmitter - Replace the 50n resistor,
RDRIVE, with a 10n, hw resistor. Monitor
prongs of cord on oscilloscope. Tests could
then be performed that are similar to those
done on the receiver:

Do not keep drinks or liquids in the area. A
spilled drink can be disastrous.

• Inject TIL and CMOS data at TX1N (Pin
19)

NOTE:
Signetics provides these NE5050 Power Line Mo-

dem Application Boards for design and development
purposes only. Signetics assumes no liability and

makes no guarantees regarding the performance of

these boards. By acceptance of these demo boards,
the user agrees to follow the instructions described
in this manual and releases Signetics from any
liability and claims resulting from use of these
boards including but not limited to third party claims.

Observing NE5050 Performance
Without the AC Line
To see the NE5050 board in operation before
plugging it into the power line or to use it in a
twisted-pair application, use the following procedures for observation of each section.
Receiver - Turn the transmitter, TX, off by
grounding TXIN (Pin 19). If this isn't done, the
signal coming will be from the local oscillator.
The line-coupling transformer and the bandpass filter can be removed to permit broadband operation. (The filtering action of the
transformer with CTUNE is no longer needed.)
Replace the line-coupling transformer secondary with a 50n resistor. Connect Pin 20 of
the IC to the line-coupling capacitor, CTUNE.
Inject ASK input signals at the cord prongs
from a 50n generator. Connect the signal
side to one prong and the ground side to the
other. Now run the following checks:
• Sweep the carrier frequency
• Change the carrier amplitude (sensitivity
specified to 1mVRMs typical; guaranteed
minimum 3.5mVRMS over -40'C to
+ 85'C, the industrial temperature range)
• Change the data rate; observe the
theoretical maximum data rate ratio to
the carrier frequency (1 bit! cycle)
• Sweep Vee from 10 to 18V
• Remove and replace CDET (AM detector
cap) and CIMP (impulse filter cap) and
observe RXOUT (Pin 11)
• Decrease CHPF (input low-pass filter) to
1nF for maximum sensitivity at
fc = 300kHz
• Sweep the carrier frequency from 100Hz
to 500kHz
February 1987

• Sweep Vcc
• Observe the TX output (4Vp_p into a
10n load, RL, connected between
RDRIVE and ground)
• Open TXIN and observe the THO (total
harmonic distortion) of the unmodulated
carrier
• Ground TX1N and observe the -90dB
carrier suppression at TXOUT and at the
prongs
• Check the RXOUT pin to make sure that
it is always receiving what it is sending
(for CSMAlCD testing)

Observing AC Line
Transmission
To observe full data transmission, reconnect
the line-coupling transformer, bandpass filter,
and the initial values for capacitors CIPF,
CIMP, and CAM.
Take two boards, setting one up as the
transmitter and the other as the receiver.
Supply + 12V to + 15V and ground to each of
them. On the receiver, short the TXIN to
ground. Attach a pulse generator to the TXIN
of the transmitter, remembering to connect
the ground of the generator to the ground of
the board. Review safety precautions before
plugging into AC line.
Receiver sensitivity is 1mVRMS. It's recommended to start with about 4Vp_p to ensure a
strong square wave for transmission. To center the bandpass of the transformer to the
incoming carrier frequency, adjust the transformer coupling with a jewel head screwdriver.
To monitor the receiver, connect oscilloscope
probes to the following circuit points:
• RXIN (Pin 20, AC line signal with noise)
• OUT1 and OUT2 differentially (Pins 3
and 6, RX amplifier output)
• CDET1 and CDET2 differentially (Pins 7
and 8, AM detector output; the device
can also be operated with this capaCitor
removed. Observe reduction in delay.)
• CAMREJ (Pin 9, AM rejection)

5-34

AN1951

• C1MPREJ (Pin 10, impulse filter; as with
the detector capacitor, the device can
be operated without this part. There will
also be a reduction in the delay.)
• RXOUT (Pin 11, receive data output)
Loud, high power-consuming electrical equipment could be set up nearby to produce inband disturbances, such as impulses. Also,
switch fluorescent lights on and off to see the
effect of the transients on the data transmission. To transmit the data, inject TTL signals
(CMOS signals are fine because they typically
swing from positive to negative rails. TIL
thresholds are typically O.BV for logic 0 and
2.0V for logic 1) into the TXIN (Pin 19) of the
other modem located nearby. Make sure that
the signals do not go below ground; if they go
more than one diode drop below ground, an
internal diode turns on and redirects any
signal from TXIN into the substrate of the
device. So if just injecting a pulse train is
desired, choose a pulse generator that has
TTL output rather than the symmetrical output that swings both positive and negative.
After observing these signals, gradually separate the distance between the TX modem and
the RX modem, trying different electrical
outlets on the same floor, different floors, and
different buildings.
Potential Sources of Interference
There are several sources of signal interference to consider. Among the most important
and most likely to occur are the following:
Impulse noise - This form of interference is
caused by electrical impulses present on the
line. It is present in the baseband and in the
frequency interval (WCARRIER ± 2 X WDATA)
used for data communications. Because the
frequency spectrum of a delta (Dirac) impulse
is continuous, it would be present in any
band. (A delta Dirac impulse is defined to be
of infinite amplitude and zero time duration.
Thus, its Fourier transform would give it an
infinite bandwidth with value unity.)
This translates into a carrier of short duration
in the receiver. If data carrier bursts are
longer than the impulse bursts, it is possible
to filter out narrow data by low-pass filtering
(integrating) or by the constant charging and
discharging of a capacitor (time domain filtering). Observe the waveform at Pin 10 to see
this.
Distributor transformer attenuation - The
transformers that separate domestic dwellings or different floors in a factory offer safety
features for the people in the buildings, but
can also attenuate signals trying to pass
through. The maximum attenuation between
any two locations within the same house is
around 50dB in the 10 - 550kHz range.
House-to-house attenuation could be from

Signetics Linear Products

Application Note

NE5050 Power Line Modem Application Board Cookbook

10dB for the same distribution transformer to
30dB for separate transformers.
In residential areas, the power line network
should not extend beyond the building. Highfrequency blocking may be necessary to
implement this separation. Consult the EIA
(Electrical Industries Association) for up-todate information on how to implement the
blocking. The consensus is that the blocking
should be done at the electric power meter.

CW (Continuous Wave) interference This type of interference is usually caused by
tones present on the AC line. They can be
generated by mercury-vapor fluorescent
lamps. If in the frequency band of the receiver, they may affect the received data and can
cause bit errors. The CW interference has
spectral components at multiples of 60kHz. It
is amplitude-modulated by a 120Hz envelope.
Line impedance modulation - The impedance of the AC power line varies according to
the number and power consumption requirements of the various equipment connected to
the line. 120Hz impedance modulation also
occurs as a result of rectification at 60Hz.
Different conditions exist, of course, for the
residential and the industrial environments.
The effect of the impedance modulation is
best illustrated by observing the waveforms
on Pins 7 and 8 (AM detection) and on Pin 9
(AM rejection). The data signal varies in
amplitude because of the varying impedance
on the line. The AM rejection circuit forces
the comparator to track the DC average of
the demodulated data and keeps the compar-

ator from changing states. This can be envisioned as a 50mV "window" (comparator
threshold) "surfing" on the input waveform.
A good example of the kinds of noise on the
power line and how the NE5050 eliminates
them is shown in Figure 5.
The top trace shows the signal at Pin 20,
RX 1N . The signal has already come from the
line, and gone through the line capacitor and
coupling transformer. If the trace is followed
from left to right, three squares over show the
effects of Continuous Wave interference.
These signals start to produce an amplitude
variation where the signal should clearly be
cut off. It also starts to distort the logic 1-to-0
and 0-to-1 transitions. At about the seventh
block, the effects of impedance modulation
on the signal can be seen. What should
clearly be a square-shaped signal is now
distorted into jagged edges of increasing
magnitude.
The second trace is the output of the singlepole bandpass filter and the input of the AM
detector (Pins 4 and 5). Aft er RXIN, the signal
was amplified and then filtered before coming
out of Pins 3 and 6 and going into the bandpass filter. At the end of the Signal there is
some ringing, and in the third block the
effects of the impedance modulation still
show slight amplitude variations.
Trace three shows the output of the slicing
comparator at the impulse rejection range.
The slope of the Signal is directly related to
CIMP. At this point the signal has now gone
through the AM detector and the AM rejector.
AM rejection was successful since the impedance modulation effects do not show up on
the third block.
The bottom trace shows the output, RXOUT,
at Pin 11. Resistor RpULL connects Pin 11 to
the logic High voltage. This signal is a square
wave, just the output of the flip-flop that was
fed internally by the comparator. Comparing
the top and bottom traces, a delay is evident.
This is caused by the charging of the AM
detection and the impulse rejection capacitors.

Figure 5. Oscilloscope Traces of RXIN,
Output of Bandpass Filter,
Impulse Rejection, and RXOUT

February 1987

Troubleshooting Board Problems
Because all components, discrete or integrated, are not exactly the same, always expect

5-35

AN1951

to see a difference in performance as different components are used. Not every application board is the same in the sense that the
frequency, filter Q, transmitted power, etc.
vary ± 10%; otherwise, they are all fully functional. To help solve eventual problems, a list
of cures has been accumulated for different
situations. Short of doing a pin-far-pin, partfor-part test, these are some of the things that
can be done to get the system running prior
to identifying the specific problem.
Assuming that the setup is configured in the
send/receive mode and connected to the
power line, there are three possible solutions
to use to get the signal through.

Increase power supply - Bringing the power supply of the part to about + 15V may
reduce the total harmonic distortion (THO) of
the transmitter if the driver swings more than
8Vp_p. For higher voltage swing, increase
RFEEDBACK for lower negative feedback. This
also increases the swing of the voltage output
of the transmitter. Sending out a larger Signal
over the power lines increases the signal to
noise ratio.
[To operate the board at supply voltages in
excess of + 15V (but not beyond + 18V),
connect an 82kn resistor between Pin 1
(Vccl and Pin 15 (feedback) to create a DC
bias at this point so that the upper drive
transistor will not break down. This is a
process limitation.]

Reducing or shorting output resistor
RORIVE - This 10n resistor drops the transmit voltage by a little. Reducing or bypassing
this resistor increases the voltage sent over
the AC lines. The overall effect is similar to
solution # 1.
Bypassing the bandpass filter - Although
this is usually done only in wideband applications, it is possible that the loss of signal
occurs because the signal is being filtered
out. That may occur because of BPF or
oscillator component skew. The carrier may
be filtered out instead of the noise. In removing the BPF, more noise is introduced because of the wider frequency band, but, once
the signal is identified, the BPF can be
reconfigured to pass the carrier frequency in
the center of its bandwidth.

Signetics Linear Products

Application Note

NE5050 Power Line Modem Application Board Cookbook

AN1951

r-------------------------------------,-----------------------------~---o+~c=+~v

01
NPN

TRANSMIT
DATA
INPUT

Re.

0---+-------------,

GNPCF1

RE,

1

1

~~LL

CFO
27pF

Cose

--0 +VLOGtC = +5V

FANOUT

RECEIVE
DATA
OUTPUT

AC LINE: 120VRMS
PLUG: CARRIER 110

1

vee

2

c HPF

C1

C H. .

Io.1/-1F

I4.7nF

":,,GND

,::,GND

3
OUT1

IN,

R1
1k
OPF

540~~bRDC

4

5
IN,

LSPF

•

OUT2

•

7

com

R2
1k
OPF

Cm

C OET2

4.7nF

~'::F

9
CAM REJ

Io.1

co~
ft

'::' GND

10

CIMPREJ

C'MP

110nF
'::' GND

Figure 6. 100kHz Industrial Application
Figure 6 is the schematic of the 100kHz
Industrial Application described earlier. From
left to right, the coupling network feeds into
the receiver section on the bottom of the
chip. (The external components are summarized later.) The receive data output is pulled
up via RpULL = 1Ok~l A minimum current of
10mA sets the voltage drop across RpULL.
Another voltage supply VLOGIC is shown if the
user wants to have the output sent at TTL
levels.

February 1987

Across the top (of Figure 6) is the transmitter
section and, going from right to left, the
oscillator network, the class AS output stage
(note feedback resistor RFEEDBACK), and the
drive section. The LC values on the oscillator
network should match those on the bandpass
filter in the receiver. The drive stage feeds
into the coupling network and back into the
receive section. This enables the on-chip
collision detection with listen-while-talking capability. This effect can be cancelled although

5-36

the transmitter will still be connected to the
receiver. This is shown in the HOMENET
application.
NOTE:
For practical implementation, high voltage transient
protection must be added between Pins 1 and 20.
This may be implemented by fast zener diodes
back-lo-back between Pins 1 and 20 (15V, 2W).

Application Note

Signetics Linear Products

NE5050 Power line Modem Application Board Cookbook

AN1951

LIST OF EXTERNAL COMPONENTS
NE5050 Typical Industrial Operation;
100kHz AC Line Impedance = 10n

Printed Circuit Board Component Listing
TYPE

TRANSISTORS
01
02

NPN,
PNP,

2N5977
2N5974

2N5979
2N5976

2N6121
2N6124

IC PIN NO

2N6122
2N6125

2N6290
2N6109

15
17

For higher output current, try higher ~ power transistors or complementary Darlington pairs.
RESISTORS

VALUE

IC PIN NO

RORIVE
RFEEOSACK
Rosc
RpULL
R1
R2
RE1
RE2

10n
(variable) 75kn (15V)/22kn (12V)
not used
10kn
1kn
1kn
1n
1n

20/16
16
13/14
11
3/4
6/5
15/16
16/17

CAPACITORS

VALUE

IC PIN NO

CAM
COET
COR1VE
CLINE
CHPF
CSPF
Cose
CIMP
CrUNE
C1
C2
CFO
CF1

0.11'F
4.7nF
11'F
11'F/600V
4.7nF
4.7nF
4.7nF
10nF
6.8nF
O.II'F
O.II'F
47pF
Not used

9

L1 + L3 secondary
Vee decoupling
Vee/2 decoupling
Oscillator feedback
Oscillator feedback

INDUCTORS

VALUE

LSPF
Lose
L1 transformer primary
L2 transformer secondary
L3 transformer secondary

540l'H Roe
540l'H Roe
1N turns
1N turns
4N turns

(L 1, L2, and L3 are one transformer

-

20/16

AC line
2
4/5
13/14
10
1
14
12/13
12
IC PIN NO

< 8n
< an

TOKO AMERICA part # 707VX-T1002N)

Transformer Manufacturers:
Toko America Inc.
5520 West Touhy Avenue
Skokie, IL 60077
Tel. (312) 677-3640
Calif. Tel. (408) 996-7575
AlE Magnetics
A Division of Vernitron Corporation
701 Murfreesboro Road
Nashville, TN 37210
Tel. (615) 244-9024
Advance Transformer Company
2950 Northwestern Avenue
Chicago, IL 60618
(312) 267-8100

February 1987

7/8

5-37

4/5
13/14
AC line
1120

•

';!,;

Signetics Linear Products

Application Note

NE5050 Power line Modem Application Board Cookbook

HIGH·PERFORMANCE
INDUSTRIAL APPLICATION
In a hostile environment, the carrier frequency and filtering scheme must be judiciously
chosen. This is usually done over the fre·
quency domain and after a thorough charac·
terization of the environment it is designed
for. The carrier frequency is then chosen to
be in the range of least interference. To
ensure the suppression of out·ol-band signals, whether it is noise or other carrier
frequencies (for a multi-carrier system, see
the Multicarrier Operation section), a high Q
filter with large stopband suppression is desirable. This suggests the use of multi-pole
passive filters or active filters. The problem in
using multi-pole passive filters is that the
passive elements tend to over·attenuate the
signal.
The configuration shown in Figure 7 illustrates one alternative to the single·pole filter
given in the normal 100kHz industrial operation. The problem presented was that certain
fluorescent light bulbs added significant interference to line transmission and caused bit·
error·rate problems. The light bulbs produce
spectral components at 60 and 120kHz that

contribute to impedance modulation effects in
that range. With a carrier near 100kHz, the
single·pole passive bandpass filter with its
6dS/octave roll·off did not provide sufficient
stopband suppression to get around the
spikes at 120kHz. The solution was to move
the carrier to a higher frequency (260kHz)
beyond the effect of the lights and to select a
filter with a much higher Q in order to elimi·
nate as much noise as possible in the spec·
trum near the carrier.
The outputs of the il)put amplifier are Pins 3
and 6 which feed into the high-Q ceramic
filters. The ones used are Toko 262Cs with a
center frequency of 262kHz. These filters
have a SW of greater than 8kHz and an
insertion loss 01 6dS. Given the center frequency and SW, the Q is approximately 32.
The outputs 01 the ceramic filters then feed
into the two-pole LC lilter on the right part of
the diagram. C1, L1, C4, and L2 provide the
center frequency.
Resistors R1, R2, R3A, R4A, R5A, R6A, R3,
and R4 provide DC biasing to the middle of
the supply range, 6V. Resistors R3 and R4
buffer the NE592 Differential Amplifier, and
C2 and C3 AC·couple the signal to the

AN1951

second LC tank which is buffered by R7 and
R8. The NE592 is used to amplify the signal
which has been attenuated by the ceramic
filter and the input resistors. The NE592 has
an adjustable gain, in this case, the gain
(differential) has been set to 200. (This is the
middle of the gain range and should be
adjusted to give the desired signaL) The
output is then sent to the input of the AM
detector, Pins 4 and 5.
There are additional changes to be made for
the high-performance application. Case and
Lose have been changed to 1nF and 390"H
to match the change made in the bandpass
filter. CTUNE has been changed to 1nF for the
same reason. CIMP has been raised to 12nF
to provide a suppression of impulses with
duration under 450"s.
The filter shown in this example should by no
means be taken as the best possible exam·
pie. It was only tailored for the application and
environmental conditions in Signetics' labora·
tory. Any conventional filter with a differential
input and output can be used. In most cases,
the cost of ex1ernal components to the user
and the amount of available space on the
board will be the limiting factors.

. - - - - -......> - - -.....- - -.....- - - - 0 Vee = +12V

Rl
100k

CERAMIC FILTERS

R3A
lOOk

RSA
lOOk
C2
O.I"F

R3
15k

RS
lOOk
R7
12k

PIN 4

PIN3
Cl
'nF

L2

Ll
390"H

390"H
PINS

PINS

R4
15k
R2
lOOk

R4A
lOOk

RSA
lOOk

RS
100k

-=Figure 7. Ceramic Filter With Two-Pole Filter for High-Performance Industrial Operation (Fe = 260kHz)

February 1987

5-38

Application Note

Signetics Linear Products

AN1951

NE5050 Power line Modem Application Board Cookbook

OTHER APPLICATIONS

CONSUMER OPERATION

On the following pages are several applications for the NE5050 that demonstrate its
flexibility. As mentioned in the disclaimer,
these do not denote the maximum performance of the part, they just describe potential
applications.

The consumer application is similar to the
industrial operation outlined earlier, except
that it uses a drive resistor of 50n instead of
10n. Use the same safety precautions, outlined under Electrical Hazards to the User.

A major difference between this application
and that of the industrial environment is the
lack of external drive transistors for the transmitter.

r--------------------------------------------------------------------1---O+ VCC=+12V
GNV'<>se
TRANSMIT
D~Ao---r-----------_,
INPUT
CLINE

CTUNE

1,.F/600V

6.8nF

]"

O.1~F

GNnCF1

540~~bRoc

CORNE

1.F

~~Ll

CFO

Cosc

FANOUT

27pF
RDRIVE

50
RXIN

20

,.

GND
18

RFEEDBACK

75k

RE2
10
PNP
17

FEEDBACK
18

4.7nF

RE,
10

Vee l
NPN 2:LC
15

R'if
ADJ

,.

RECEIVE
DATA

OUTPUT
LC

13

CFO
12

RXoOT
11

I

AC LINE: 120VRMS
PLUG: CARRIER 110

1

vee

I oC1.

1/-tF

-=- GND

2
C HPF

C HPF

14.7nF

-= GND

3
OUT1

R1
10k
BPF

•

IN,

5

6

7

IN,

OUT2

C OETl

L BPF

540,.H/R oc

<8Q

R2
10k
BPF

C BPF

4.7nF

Figure 8. 100kHz Consumer Operation

February 1987

5-39

COET
4.7nF

8
COET2

9

10

CAM REJ

CIMP REJ

CAM

C 1MP

Io.1~F

14.7nF

":'" GND

-=- GND

i~tI.:.•

Signetics Linear Products

Application Note

AN1951

NE5050 Power line Modem Application Board Cookbook

SPLIT-SECONDARY OPERATION
This operation is similar to the industrial
operation except that the transmitted signal is
sent on a separate secondary winding. Note

that the turns ratios are 10:40 for the received
signal. The turns ratio for the transmitted
signal back to the line is 1: 1O. For this
application, the transmitted input is not being

received back into the device, so collision
detection is not used. This is to be expected
since TXOUT and RX'N are transmitted and
received on different secondaries.

r-----------------~--------------~-O+VCC=+12V

--o+VWG1C ;:::+5V
TRANSMIT

~Tho-~------~

INPUT

.-----+__

~RX,N

'"

27pF

4.7nF

r---+-----~~~I~----~--~/

~

cFe

COS<

~l:EDBACK

RDmve

RECEIVE
DATA

FEED·

Vcc l

OUTPUT

TX,N

GND

PNP

BACK

NPN 2:lC

RXoUT

19

18

17

16

15

n

14

'S\~V

AC LINE: 120VRMS
PLUG: CARRIER 110 10

LINE DRIVE
AMPLIFIER
L1

CrUNE

6.8nF

1

Vee

2
C",.

3

4

OUT,

IN,

R1

Io 1
C1
.1.1/F

C HPF

-= aND

-= GND

4.7 nF

10k
BPF

•

IN,

LSPF

540.IIH/Aoc

<80

•

OUT2

'.k

BPF

;,~~

5-40

8
C DET2

•

CAM REJ

,.

CIMPREJ

R'

Figure 9, Split-Secondary Operation

February 19B7

7
CDET1

COET
4.7nF

. CAM

I o.

1I-1 F

-= GND

C1MP

14.7nF
";'GND

Signetics Linear Products

Application Note

NE5050 Power Line Modem Application Board Cookbook

1

2

3

Vee

C ...,

OUT1

•

IN,

5
IN,

•

OUT 2

7
Corn

•

C DET2

9
CAM REJ

AN1951

10
CIMPREJ

..
I

ro.

C_
I1nF/o.1j.1F

":" GND

-:-GND

C1
11-1 F

CD.,
ronF

C 1MP

Io.1/AF

CAM

110nF

-::-GND

":" GND

Figure 10. Wide-Band Operation

WIDE-BAND OPERATION
For wide-band operation, note in Figure 10
that the bandpass filter is not utilized and the
output of the input amplifier is shorted directly
to the AM detector to permit all frequencies to
pass through. Also note the absence of any
transformer coils. The receive input and the
transmit output are just AC-coupled to their
respective sources and destinations. The external-carrier oscillator input is AC-coupled
directly to Pin 13 to the LC tank input It goes
through a 50n resistor to Pin 14. Pin 12 has a
capacitor to ground to prevent the Colpitts
oscillator from building up oscillations itself.
This application is ideal for testing the frequency response of the receiver and transmitter. For single frequencies, the 50n resistor between Pin 13 and Pin 14 can be
replaced with a tuned LC tank circuit

MULTICARRIER OPERATION
This application enables use of multiple
points on the network without interference
from adjacent transceivers using the same
medium. Set up the boards as in the consum-

February 1987

Figure 11. Multiple Carrier Operation
er or industrial applications, but use different
values for the carrier frequency and the bandpass filter. It is suggested that each carrier be
separated as much as possible over the
working range of the NE5050. The frequencies should not be multiple integers of each
other. This ensures that any harmonics will be

5-41

suppressed far enough not to interfere with
other carriers in the spectrum of operation.
In this type of application, the stopband
suppression of the bandpass filters plays a
large role in the efficiency of carrier transmission, so active filters should be considered.

Signetics Linear Products

Application Note

NE5050 Power line Modem Application Board Cookbook

AN1951

,------------------,....--------------.....,--0

+Vcc= +12V

GN~CF1

-=-

TRANSMIT

DA~o-~~----------,

INPUT

1

2

Vee

C HPF

3
OUT,

R.,

RE,

1

1

5
IN,

4
IN,

OpF
RPULl

10k
FANOUT

CFO
27pF

8
OUT2

7
COEn

8
Com

9
CAM REJ

10
CIMPREJ

L 8PF

C HPF

C1

Io.1J.1F

14.7nF

":" GND

":" GND

Rl
Uk

R2

S.1k
BPF

BPF

COET

4.7nf

CaPF

RAM2
10M

RAMI
1M

R1MP

SOk
RAM3

220k

Figure 12. HOMENET Operation at 120kHz

GENERAL ELECTRIC'S
HOMENET OPERATION 1
HOMENET is a software package copyrighted by General Electric Company for the
purposes of power line and twisted-pair communication in a residential environment. The
software package is called the HOMENET
Link Layer and is compatible with the X-tO
Home Control System manufactured by eSR
and GE.
A working diagram is shown in Figure 12.
Technical highlights are as follows:
1. The receiver is disabled while .In the
transmit mode. This is done by having the
transmit input drive a NPN transistor.
When turned on, it discharges the impulse capacitor and pulls the comparator
output Low (Pin 10). The flip-flop cannot
change state. When the data is low, the
oscillator is suppressed and no carrier is
detected.
2. HOMENET wants the signal inverted and
with an open collector so the user can

February 1987

3.

pick the logic voltage for the receive
output (typically + 5V).
In order to prevent the receive output
from going into the standby mode (typically 4 seconds after a TXIN 1-to-0 transition, the RXOUT pin will drift High), the AM
rejection pin is externally biased to 2.2V
DC with the resistors shown to prevent
the comparator from triggering.

NOTE:
1. HOMENET is a trademark of the General Electric
Corporation. The HOMENET Link Layer is available as a software package with the Commodore
64 Personal Computer. Current version number
available by contacting: The Industry Standards
Staff, General Electric Corporation, Fairfield, CT

06431.

TWISTED-PAIR APPLICATIONS
Data transmission over twisted-pair cable enables much higher data rates because the
media is usually free of the noise and impedance modulation problems of the power line.

5-42

Transmission over longer distances is also
possible. Many of the same reasons can be
applied to coaxial cable. The NE5050 provides an easy interface for twisted-pair operation.
Figure 13 shows the characteristics of the
cable used. Four rolls of cable were used.
Each roll had over a kilometer of cable which
was linked together to create about 15,000
feet of media. The operation is straightforward and is shown in the schematic in Figure
14.
This version has no external drive transistors
and has no drive resistor. The receive input
comes directly from the end of the secondary
(no tuning capacitor); the tap is left unconnected. The other end of the secondary is
biased to the power supply. The transformer
made by AI E MagnetiCS connects itself to the
twisted-pair wire. The center tap is grounded
to the shield of the cable. Only a single-pole
filter is used. The AlE transformer was
chosen because it enabled the high transmission rates.

Signetics Linear Products

Application Note

AN1951

NE5050 Power line Modem Application Board Cookbook

A

A'

S

S'
G'

G

CAB =33nF/1000 FT
CAQ=CBG =60nFI1000FT
RAA '= Rss '=2SQ/1OOO FT

Raa'=18211OOOFT

Figure 13. Parameters of Shielded Twisted-Pair Cable

, ________________________________-,-0
GN~
-=02

GND
TRANSMIT

Re,

RE,

10

10

CORIVE

MAGNETICS

+"""""I"F

,.

TX 1N

RX,N

390,H

CFO
27pF

RFEEDBACK
.. k

TRANSFORMER,-I_ _ _t-__

20

lose

I,F

O--ir------,

DATA
INPUT
AI.

+VCC'" +12V

/'FEEDaND

PNP

18

17

,.

BACK

NPN

''!
. ,

15

"

SHIELDED

LINE DRIVE
AMPLIFIER

TWISTED-PAIR
CABLE
318<>733

1

2

3

4

Vee

C_

OUT,

IN,

,.
R1

I

CHPF

C1

1.uF

-;"'GND

SPF

LBPF

390,H

5
IN,

•

OUT2

•

7

CDET1

10
CIMP REJ

9
CAMRPJ

CD£T'

R2
1k

BPF

110nF

CDEr
180pF

-;"'GND

CAM

14.7nF
":" GND

I

C 1MP

470pF

":" OND

CaPF

UnF

Figure 14. Twisted-Pair Operation: 15,OOOft Unequalized Cable at 20kbits/ sec
Faster transmission is possible if the cable
lengths are shortened. As a rule of thumb,
shortening the cable enables a doubling of
the transmission rates provided it doesn't
exceed the part's (or the transformer's)
broadband limitations. Remember, when
changing the data rate, CAM has to be adjusted accordingly. Because of the less noisy
environment, high-voltage transients are absent and C'MP plays less of a role in maintaining a lower bit-error-rate. It will, however,
keep the rate-limiting effect outlined earlier.

February 1987

An additional case was performed in the lab
incorporating the following changes:
1. Pin 2 has a 10IlF capacitor in series with
a 2.2kn resistor. The resistor was added
to reduce the ringing effects on the RX,N,
Pin 20, due to the response of components at higher data rates and higher
carrier frequencies. The components will
cause the parts to ring. (The transformer
is a potential source. The IC will not ring
unaided.)
2.

R1 = R2 = 1kn, CBPF
LBPF = Lose = 390llH

5-43

= Cosc = 470pF,

3.
4.

CDET = 68pF
CAM = 1.5nF

5.
6.

C'MP = 12pF
Connect a 10n resistor between the
ends of the primary of the transformer
(AlE Magnetics 318-0733). This resistor
shunts the two twisted wires.

Performance under these changes resulted in
a 100kbits/sec data rate over 3,000 feet of
shielded twisted-pair wire using a carrier frequency of 370kHz.

NE5080

Signetics

High-Speed FSK Modem
Transmitter
Preliminary Specification
Linear Products

DESCRIPTION
The NE5080 is the transmitter chip, of a
two-chip set, designed to be the heart of
an FSK modem. (The NE5081 is the
receiver chip.) The chips are compatible
with the IEEE 802.4 standard for a
"Single-Channel Phase-ContinuousFSK Bus." The specifications shown in
this data sheet are those guaranteed
when the transmitter is tuned for the
frequencies given in the 802 standard.
However, both the NE5080 and the
NE5081 may be used at other frequencies. The ratio of logic high to logic low
frequencies remains fixed at 1.67 to 1.00
at any center frequency.

PIN CONFIGURATION

FEATURES
•
•
•
•

Meets IEEE 802.4 standard
Data rates to several Megabaud
Half- or full-duplex operation
Jabber function on-chip

N Package

JABBER FLAG

APPLICATIONS
•
•
•
•
•

2

15

:~~~i: TOR

JABBER

CONTROL

Local Area Networks
Polnt-to-point communications
Factory automation
Process control
Office automation

Vee,

4

TRANSMIT

GATE
FSK OUTPUT

6

CABLE GND

7

TOP VIEW

ORDERING CODE
DESCRIPTION

16·Pin Plastic DIP

TEMPERATURE
RANGE

ORDER CODE

O'C to +70'C

NE5080N

BLOCK DIAGRAM
R1

2.1K

+5V

C1

I~;~~

o-.:.:14'i-__--I

r-:;:;;;;-l------+L-o

TRANSMIT
GATE

February 1987

JABBER FLAG

c.--!t----==l-->-......----==---=::-----I~L_=:::...J--r_--i

5-44

TRANSMITTER
FSK OUTPUT

Signetics Linear Products

Preliminary Specification

High-Speed FSK Modem Transmitter

GENERAL DESCRIPTION
The NE5080 is designed to transmit high
frequency asynchronous data on coaxial cable, at rates from DC to 2M baud (see Note
1). The chip accepts serial data and transmits
it as a periodic signal whose frequency depends on whether the data is high or low.
The device is meant to operate at a frequency of 6.25MHz for a logic high and 3.75MHz
for a logic low (see Note 2). The frequency is
set up by external trimming components;
however, the ratio of the high and low frequencies is set internally and cannot be
altered.
The FSK output can be turned off by use of
the transmit gate pin. When turned off, the
transmitter has a high output impedance and
the oscillator is disabled.
The length of time a transmitter can transmit
can be controlled by the use of the Jabber
control pin (see description of Jabber Control
Pin).

ABSOLUTE MAXIMUM RATINGS
SYMBOL

1.

2.

3.

Use the current to charge a capacitor.
When the voltage across the cap gets to
approximately 1AV, the transmitter will
turn off. A logic low applied to Pin 3 will
reset the Jabber function; an open collector output should be used for this purpose. A logic high applied to the pin will
disable the transmitter.
Use to externally sense the current and
have external circuitry to control the
length of time the transmitter is on.
The pin can be tied to ground and is then
not active. Transmission is then controlled solely by the signal at the transmit
gate pin.

PARAMETER

VCC1
VCC2

Supply voltage

VIN

Input voltage range (Data, Gate)

PD

Power dissipation

TA

Operating temperature range

TJ

Max junction temperature

TSTG

Storage temperature range

TSOLD

Lead temperature (soldering, 10sec)

RATING

UNIT

+6

V

-0.3 to +Vcc

V

800

mW

o to +70

°c
°c
°c
°c

+150
-65 to + 150
300

NE5080 PIN FUNCTION
r------,----------------------------,

FUNCTION

PIN

OSC 1: one end of the external capacitor used to set the
carrier frequency
2

Jabber Flag: this pin goes to a logic high if the
transmitter attempts to transmit for a longer time than
allowed by the Jabber control function

3

Jabber Control: used to control transmit time. See note on
Jabber function

4

VCC1:

5

Transmit Gate: a logic flow on this pin will enable the
transmitter; a logic high will disable it

Jabber Control Pin
During the time the transmitter is transmitting,
this pin sources a current. This current can be
used to set the maximum time that the
transmitter can be on. There are three options that can be used:

NE5080

voltage supply

6

Transmitter FSK Output

7

Cable Ground: the shield of the coax cable should be
connected to this pin and to Pin 11

8

VCC2:

9

No Connection

Connect to Pin 4 close to device

10

No Connection

11

Ground 2:

12

OSC 3: a variable resistor between this point and ground is
used to set the carrier frequencies

connect to Analog ground close to device

13

Ground 1:

Jabber Flag Pin

14

Data Input

This pin will go to a logic high when the
Jabber Control pin is used to shut off the
transmitter. It will latch and can be reset by
applying a logic low to the Jabber Control pin.

15

Regulator Bypass: a bypass capacitor between this pin and
VCC1 is required for the internal voltage regulator function

16

OSC 2: one end of a capacitor that is between Pin 1 and
Pin 16 and is used to set the carrier frequency

NOTES:

1. The NE5080 is capable of transmitting up to
1M baud of differential Manchester code at a
center frequency of SMHz.

2. Although the chip is designed to meet the requirements of IEEE standard 802.4 (TokenPassing Single.Channel Phase-Continuous-FSK
Bus), it can be used at other frequencies.
See "Determining Component Values."

February 1987

5-45

connect to Analog close to device

I

Signetics Linear Products

Preliminary Specification

NE5080

High-Speed FSK Modem Transmitter

DC ELECTRICAL CHARACTERISTICS

Vcc,

4.75 - 5.25V, TA =

2=

o·c

to + 70·C.
LIMITS

SYMBOL

PARAMETER

UNIT

TEST CONDITIONS
Min

Typ

Max

f,

Output frequency (Logic high)

Data input > 2.0V (See Note 1)

6.17

6.25

6.33

fo

Output frequency (Logic low)

Data input ,;;; O.BV (See Note 1)

3.67

3.75

3.B3

MHz

Vo

Output amplitude

Data input > 2.0V or ,;;; O.BV
Output Load = 37.50

0.5

1.0

VRMS

100

MHz

kO

ROFF

Output impedance (gated off)

Transmit gate >2.0V

RON

Output impedance (gated on)

Transmit gate ';;;O.BV

37.5

0

Co

Output capacitance

Transmit gate > 2.0V or ,;;; O.BV

10

pF

VF

Feedthrough

Transmit gate > 2.0V
2.0MHz sq. wave (TIL levels) input

1

mVRMS

IJ

Jabber current

Transmit gate ,;;; O.BV
Input > 2.0V or ,;;; O.BV

1.25

Icc

Supply current

Vcc, connected to VCC2

75

VIH
VIL
IIH
IlL

Data Input
Logic high
Logic low
Input current
Input current

Input high voltage
Input low voltage
VIN = 2.4V
VIN = O.4V

2.0

VIH
VIL
IIH
IlL

Transmit gate
Logic high
Logic low
Input current
Input current

Input high voltage
Input low voltage
VG = 2.4V
VG = O.4V

2.0

VOH
VOL

Jabber flag
Logic high
Logic low

IOH = -400JJ.A
IOL = 4.0mA

2.4

VIH
VIL

Jabber control
Logic high
Logic low

Input high voltage
Input low voltage

2.0

JJ.A
100

mA

Logic levels
V
V

O.B
40
-1.6

mA

O.B
40
-1.6

V
V
JJ.A
mA

0.4

V
V

O.B

V
V

JJ.A

NOTE:
1. Tuned per instructions in Applications section.

AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL

PARAMETER

TO

FROM

TEST CONDITIONS

Setup time

Data in

Gate on

Figure 1

tA

Delay time

Output freq.
change

Data transition

Figure 2

t8

Delay time

Output
disabled

Gate off

Figure 3

tc

Delay time

Output
disabled

Jabber control

Delay time

Jabber flag

Jabber control

ts

tD

Jabber control reset
Pulse width (Logic low)

February 19B7

UNIT

Min

Typ

2

0.1

JJ.s
150

ns

2

JJ.s

Figure 4

100

ns

Figure 5

100

ns

0.4

100

5-46

Max

ns

Signetics linear Products

Preliminary Specification

High-Speed FSK Modem Transmitter

NE5080

TIMING DIAGRAMS

TRANSMITTER
GATE

JABBER CONTROL

=ltcl""-

-----II
,

I

---Ln'-___

_15_

VALID DATA

OUTPUT

DATA INPUT - - - - - - - : . . '

JVW-

Figure 4. Delay Time, Ie
Figure 1. Selup Time, Is

JABBER CONTROL

DATA INPUT
JABBER FLAG

OUTPUT

I,

Figure 5. Delay Time, 10

Figure 2. Delay Time, IA

TRANSM~~~

---=I

---.....I

1B

r-

I

I
OUTPUT

'V\N-

Figure 3. Delay Time, IB

February 1987

5-47

NE5081

Signetics

High-Speed FSK Modem
Receiver
Preliminary Specification

Linear Products

DESCRIPTION

FEATURES

The NE5081 is the receiver chip of a
two-chip set designed to operate as an
FSK modem (the NE5080 is the transmitter chip). The chips are compatible
with the IEEE 802.4 standard for a
"Single-Channel Phase-ContinuousFSK Bus." The specifications given in
this data sheet are those guaranteed
when the receiver is tuned to the frequencies in the 802 standard. However,
the receiver will work at other frequencies.

•
•
•
•

PIN CONFIGURATION

Meets IEEE 802.4 standard
Data rates to several Megabaud
Half- or full-duplex operation
Low bit rate error (10- 12 typical)

N Package

FSK INPUT
INPUT BYPASS

APPLICATIONS
•
•
•
•
•

ANALOG GNO

Local Area Networks
Point-to-point communications
Factory automation
Process control
Office automation
VCC2

DESCRIPTION

9

INPUT
LEVEL

ORDERING INFORMATION

DATA OUTPUT

flAG

TEMPERATURE RANGE

o to

20-Pin Plastic DIP

INPUT
DETECTION TIMING
INPUT
DETECTION TIMING
INPUT
LEVEL DETECTION
INPUT LEVEL
DETECT
OIGITAl GNO

TOP VIEW

ORDER CODE

NE5081N

+70'C

BLOCK DIAGRAM
5V
L1

C7

Note: Either
LlorC7is
variable.

R4

1

13

-r--==-,I-,J.!!---o

t-___-L.....;)-.....

LEVEL FLAG

DIGITALGND

12

February 1987

OUTPUT DATA

_ _ _ _ _ _~~::::~Jr~~--oINPUT

L..-

5-48

Signetlcs Linear Products

Preliminary Specification

NE5081

High-Speed FSK Modem Receiver

ABSOLUTE MAXIMUM RATINGS T A = 25'C
SYMBOL

PARAMETER

VCC1
VCC2

Supply voltage

VIN

Input voltage range

100

Output (Data, Level detect)
Max sink current

Po

Maximum power dissipation, TA = 25'C, (still-air) 1
N package

TA

Operating temperature range

TSTG

Storage temperature range

TSOLO

RATING

UNIT

+6

V

-0.3 to
+Vcc

V

20

mA

1690

mW

o to

+70

'C

-65 to +150

'C

Lead soldering temperature (10 sec. max)

300

'C

Max differential voltage between
analog and digital grounds

100

mV

NOTE:

1. Derate above 25'C as follows:
N package at 13.5mW/'C.

DC ELECTRICAL CHARACTERISTICS VCC1 2 = 4.75 - 5.25V. Ex1ernal LC circuit tuned to 5MHz. Input level detect set at
16mVRMS, TA = O'C + 70'C.

SYMBOL

PARAMETER

TEST CONDITIONS

UNIT

Min

Typ

Max

to

Logic Low Frequency

Ex1ernal LC tuned to 5MHz

3.67

3.75

3.83

MHz

t1

Logic High Frequency

Ex1ernal LC tuned to 5MHz

6.17

6.25

6.33

MHz

INOL

Minimum Input Detect Level

Minimum input level that is detected as
carrier (See Note 2 in General Description)

5

50

mVRMS

VOL
VOH
VOH

Logic Levels:
Data Output
Data Output
Data Output

0.4

V
V
V

0.4

V
V

50

mA

VOL
VOH

IOL = 4.0mA VIN > 16mVRMS Freq = fo
IOH = -4001lA VIN> 16mVRMS Freq = t1
IOH = -400/lA VIN < 5mVRMS Freq = to

2.4
2.4

IOL = 4.0mA VIN = OVRMS
IOH = -400/lA VIN > 16mV

2.4

Input Detect Flag
Vcc

Icc
BER

February 1987

Supply Current
Bit Error Rate

= 5.25V (VCC1 connected to VCC2)
VIN = 1.0VRMS Freq = 11 or to

Input Signal> 16mVRMS
maximum in-band noise = 1.6mVRMS

5-49

10- 12

I~."·
,oj

LIMITS

10- 9

Signetics Linear Products

Preliminary Specification

NE5081

High-Speed FSK Modem Receiver

AC ELECTRICAL CHARACTERISTICS
SYMBOL

PARAMETER

TO

FROM

TEST
CONDITIONS

ts

Delay Time

Input Level
Detect Flag

Input On

Figure 1

tc

Delay Time

Input Level
Detect Flag

Input Oft

Figure 1

tD

Delay Time

Output
Enabled

Input On

Figure 2

tE

Delay Time

Output
Disabled

Input Oft

Figure 2

Carrier

Required Delay

GENERAL DESCRIPTION
The NE5081 will accept an FSK-encoded
signal and provide the demodulated digital
data at the output. It is optimized to work at
frequencies specified in IEEE 802.4 - Token-Passing Single-Channel Phase-Continuous-FSK Bus- (i.e .• 3.75MHz and 6.25MHz).
However, it will work at other frequencies. 1
Its normal acceptable input signal level range
is from 16mVRMS to 1VRMS. This can be
adjusted. 3
The receiver will yield an undetected "Bit
Error Rate" of 10- 9 or lower when receiving
signals with a 20dB signal-to-noise ratio. It
has a maximum output Jitter of ± 40ns. 3
NOTES:
1. The receiver can be tuned to accept different

Turn Oft

have been optimized for 3.7SMHz and 6.2SMHz.
See "Determining Component Values" for use at
other frequencies.

2. Input Level Detect
This is a method of turning off the output of the
receiver when the input signal falls below an
acceptable level. This level is adjustable within
the range given in the electrical specification
section. The purpose of this function is to mini~
mize the effect of noise on receiver performance
and to indicate when there is an acceptable signal
present at the input. All specifications given in this
data sheet are with the input level detection set at

16mVRMS·
3. Jitter (Definition)
This is a measure of the ability of the receiver to
accurately reproduce the timing of its FSK-coded
digital input. The spec indicates the error band in
the timing of a logic level change.

February 1987

UNIT
Min

0.5

0.5
2

Typ

Max

0.05

1

)J.s

1.5

2.5

)J.s

2

)J.s

2.5

)J.s

1.5

)J.s

NE5081 PIN FUNCTION
PIN
1

2
3
4

FUNCTION
VCC1: Should be connected to the 5V supply and Pin 9
CT: One end of an ex1ernal capaCitor that is used to tune the receiver
LT: One end of an indicator that is used to tune the receiver
MT: The junction of the capacitor and inductor used for tuning the
receiver

5
6
7
8
9
10

11

frequencies by adjustment of the LC circuit shown

in Figure 7. However, the external components

Valid Data
End

LIMITS

12
13 and
14
15

16

17
18

19
20

F2)
F1
Pins 5, 6, 7, 8 are used for a low-pass filter to remove carrier
F3
harmonics from the data output
F4
VCC2: Connect to Pin 1 (see Pin 1 function) close to the device
Input Level Flag: This pin is used to indicate when there is a signal
at the input that is greater than the level set by the input level
detection circuitry. A logiC high indicates an input greater than the
set level
Data Output: Supplies T2L level data that corresponds to the FSK
input received
Digital Ground: Should be connected to digital ground
Input Level Detect: These pins are used to set the level of input
signal that the device will accept as valid
Input Detection Timing: An ex1ernal capacitor between this pin and
ground is used to determine the time from carrier turn-off to output
disable
Input Detection Timing: Same as Pin 15, except that a resistor goes
between this pin and ground. The values of the C and R depend
on the carrier frequency. The values given in this data sheet are
for a 5MHz carrier center frequency
Analog Ground: Connect to analog ground close to the device
Input Bypass: A capacitor between this pin and ground is used to
bypass the input bias circuitry
Input: The FSK signal from the cable goes to this pin
No Connection

5-50

Signetics Linear Products

Preliminary Specification

High-Speed FSK Modem Receiver

NE5081

TIMING DIAGRAMS
Fa. F,

16mVRMS

111!ll ilil l l lil l l ...-1- -

INPUT

'I

II

TB -"--.: ~..-

Te ---..~ ~.

INPUT lEVEl
~ETECT

OUTPUT _ _ _ _....

Figure 1. Delay Time, tB, tc

Fo. F 1

INPUT

--illlllilllllilllllilillll...-1- :-+--.
-1;..---I

I

TD-------:

I

I

TE - -. . : ) . -

,..

DATA OUH'UT

16mV RMS

VALID DATA·

Figure 2. Delay Time, to, tE

February 1987

5-51

Signetics

AN195
Applications Using the

NE5080, NE5081
Application Note
Linear Products

APPLICATIONS
Figure 1 shows a block diagram of the
NE5080 and NE5081 in a simple point-topoint communications scheme. Pin 5 of the
NE5080 is grounded to permanently enable
transmission; grounding Pin 3 disables the
jabber function.
An example of a communications system
block diagram using the NE5080 and the
NE5081 (as in a modem) is shown in Figure 2.
The jabber function is active in this system.
The NE5080 Jabber Flag (Pin 2) goes high
when the capacitor at Pin 3 of the NE5080
charges to about lAV. This fault condition

will interrupt the Transmission Controller,
which will cease transmitting and write to the
proper address for the decoder to put out a
signal to discharge the capacitor. The Controller will then pass the token to the next
node.

NE5081 receives the FSK signal and converts it to a digital data stream corresponding
to the data sent by the NE5080. Pin 10 of the
NE5081 goes high when the signal at its input
is above the threshold set by the potentiometer between Pins 13 and 14 of the NE5081.

The transmission medium can be any1hing
from a twisted pair to a fiber optic link. The

OATAIN

>-

NES080
TRANSMITTER

FSK TRANSMISSION

NES08,
RECEIVER

1---+ DATA OUT

~5
AF037616

Figure 1_ Polnt-to-Polnt Communications

SERIAL
DATA OUT
TRANSMISSION
CONTROLLER

NE508,

SERIAL
..'",'_ _-+lDATA IN
RECEIVER
CONTROLLER
.''''0_ _.... DATA
VALID

Figure 2. Communications System Block Diagram

February 1987

5-52

Signetics Linear Products

Application Note

Applications Using the NE5080, NE5081

AN195

C13
0.0047 JJ.F

NE5080

xxa

3.5 pF

100

C12

0.0047 "F

100

NOTE:
In applications using twisted-pair lines where noise pick-up may be excessive, it is recommended that the twisted-pair be driven differentially.

Figure 3_ Modem Using a Twisted-Pair Transmission Line

DC-to-2 Megabaud Modem
Using the NE5080 and NE5081

4.

Either 1 or 2 above operated on two
cables in the full-duplex mode.

modems attached to the cable, and the
carrier frequency.

The NE5080 and NE5081 are designed to be
used together as an asynchronous modem.
They employ FSK modulation at high carrier
frequencies, plus filtering to reject EMI and
RFI noise that is frequently encountered in
industrial and commercial environments. Figures 4 and 5 show full- and half-duplex
modems.

The 30dS dynamic range of modems built
using the NE5080 and NE5081 makes it
possible to attach them at any point on the
cable without any gain adjustment. There is
no problem with proximity to other similar
modems.

Typical operation can be 100 modems randomly spaced on up to 2000 meters of RG-11
(foam) cable with a center frequency of
5MHz.

The distance that can be driven varies with
the type of cables used, the number of

In point-to-point operation, one can drive
further. Table 1 gives obtainable distances
when different carrier frequencies and cables
are used.

The carrier frequency is externally adjustable
and can range from 50kHz to over 20M Hz.
The modem can be used in a number of
ways:
1. Multidrop party line of data transmitting
and receiving devices (local area networks).
2. Point-to-point operation connecting just
two transmitting/receiving devices.
3.

Either of the above operated on one
cable in the half-duplex mode.

February 1987

Table 1_ Transmission Distance for a Single Receiver as a
Function of Center Frequency and Cable Type
CABLE

CARRIER
FREQUENCY

MAXIMUM
DATA RATE

RG-59

RG-11 (Foam)

T4412J

T4750J

1MHz

0.5 Megabaud

6000 Ft

21000 Ft

33000 Ft

50000 Ft

3MHz

1.0 Megabaud

5000 Ft

12000 Ft

20000 Ft

32000 Ft

5MHz

2.0 Megabaud

4200 Ft

9500 Ft

15000 Ft

25000 Ft

5-53

II

Signetics Linear Products

Application Note

AN195

Applications Using the NE5080, NE5081

-1 14

.!O"'A"'TA"-!!IN'-_ _ _
GATE IN

NE5080

JABBER FLAG

C5

C2
O.47J.tF

O.tJ.tF

r--------+-*-~-~+sv

DATA OUT

INPUT lEVEL FLAG

Cl0
240pF

EXTERNAL COMPONENTS SHOWN HERE ARE FOR 5MHz CARRIER

Figure 4. NESOBO and NESOB1 Connected as a Full-Duplex Modem

~D~A~TA~IN'__ _ _~14

FSK
OUTPUT

GATE IN
NES080

JABBER FLAG

C2
O.47J.

-<

"Q.

(;-

~
.....

<6"

~

:
~

0

-+
o·
::::I

en

C

en

+5V

:j"

+5V

(Q
O.1~F

-+

t~J...
DATA IN

TRANSMIT
GATE

::J"

(J)

~F

"
......, F'BEA CABLE ,

JABBER
FLAG

Z
m

AI

NES080
,..

0'1
0
00

~ II'A
,

..

PIN

DIODE

p

25 pF

O.0111F

Z
m

100
O.47~F

(J1

0,

'00

0'1
0
00

500

a>

...::.

IlpF
-5V

Figure 11. Simplex Fiber-Optic System

»

Ll

»
z

"Q.
0"

0'1

m

...::.
-0

80"
::J

z

0

Application Note

Signetics Linear Products

Applications Using the NE5080, NE5081

AN195

vcc,o-------t

NC

C7A
3-12pF 1.L---L~rY""o""_'"

CONTROL

C5

15

C2

o.47;F ___-I

N
E
5
0

N
E

13

5

o
8
o

FSK~C4

'

O.1.u:F

R55K

-=-

Rl

R2
500

-=-

GROUND

-=R'
lK

13

+

12
GROUNDl

-=10

GROUND

11

DATA
NC

GROUND 2

OUTPUT

INPUT LEVEL
FLAG

-=-

NC

II

' - - -.......

NOTE,

NOTE,

See NE5080 and NESOB1 Block Diagram(s)

Signetics NE50BO/NE5081 Evaluation Board

.,

J. CONTROL JABBER

\
X GATE

ti·~c,.

..
·:"11
.,.

•
•
ecm..,
CI

•

• ••

• c• • •

D~:'

I!!JII!tIl:li
NE5080/NE5081
EVALUATION
'it BOARD

• -.....ao-.

':

•

GOO

II

-..-

••

•

INPUT

•

LEVEL

Figure 12. Components and Layout Used for Evaluation Board

February 1987

FSK
INPUT

15

11

V CC2 o--~----I

C16

-=-

,.

1

DATA
INPUT

2.1K

10

I-=

l00pF

16

8

12

0.0047~F 6

-=-

+5V

O.'~

,.

~

¥

:l

17

JABBER

CABLE
GROUND

C12

18

JABBER
FLAG

OUTPUT

C13

IO.OO4

19

5-59

Ccn

•

•

FLAG

\
DATA OUT

Signetics

AN1950
Application of NE5080 and
NE5081 With Frequency
Deviation Reduction

Linear Products

Application Note

Author: Prasanna M. Shah

INTRODUCTION
Application note AN195 discusses numerous
applications of NE5080 and NE5081 in pointto-point, half-duplex and full-duplex communi-

12

CURRENT AND
VOLTAGE
REFERENCE

cations using coaxial, twisted-wire pair, and
fiber optic cables. It also discusses several
aspects about tuning the transmitter and
receiver at various center frequencies and
board layout precautions. In this application

note, the transmitter and receiver chips themselves are discussed. Following the brief
circuit description, a few novel application
ideas are discussed.

3-STATE
OUTPUT
BUFFER

TRANSMISSION
GATING AND
JABBER CONTROL

FSK
OUTPUT

Res
-::DATA IN

14

TTL INPUT
BUFFER AND
SWITCH DRIVER

TRIANGLE
TO SINE
CONVERTER

CURRENT·
CONTROLLED
OSCILLATOR

1.51

16

Figure 1. NE5080 Block Diagram

TRANSMITTER
The block diagram of the transmitter NE5080
is shown in Figure 1. The transmitter is
composed of the following six major building
blocks: a TTL input buffer and switch driver, a
current controller oscillator, a triangle-to-sine
wave converter, a 3-state output buffer, and
transmission gating and jabber control circuitry. It also has an on-chip voltage regulator
that provides current and voltage references
to the various building blocks of the circuit.
The transmitter center frequency can be adjusted by selecting the values of the tuning
capacitor, Co. The switch driver circuitry
switches the current sources I in and out of
Pins 1 and 16. This effectively changes the
total average charging and discharging cur-

February 1987

rent into Co from 1.51 to 2.51, which causes
the output to shift from one frequency to
another. This soft switching action keeps the
output phase continuous and eliminates discontinuities. The ratio oi the two output frequencies is equal to the ratio of the total
average current charging and discharging Co.
Since the values of the internal current
sources are fixed, it produces a constant
frequency ratio of 1.66. An external modification for changing this ratio through extra
components is discussed later.
The triangle-to-sine wave converter circuitry
converts the output of the current-controlled
oscillator inlo a sine wave with about 2%
distortion. The transmission gating and jabber
control circuitry controls the FSK output
through the 3-state output buffer. The trans-

5-60

mit gate, when held high, will inhibit the
transmission by putting the output buffer into
the high impedance state. It also turns off the
current-controlled oscillator, thus minimizing
any feedthrough to the output.
The jabber control function is similar to the
transmit gate, but the transmission time can
be programmed through an external capacitor. There is a small current sourced to the
jabber control pin, which charges up the
capaCitor. When the voltage on the capacitor
reaches a preset threshold level, the transmission is stopped. This is a failsafe feature
provided to restrict an errant transmitter or
the NE5080 itself from tying up the network.
In pOint-to-point communications, the jabber
control can be disabled by connecting the
jabber control pin to ground.

Application Note

Signetics Linear Products

Application of NE5080 and NE5081 With
Frequency Deviation Reduction
RECEIVER
The receiver block diagram shown in Figure 2
is composed of the following seven major
building blocks: an input limiter, a phase
shifter, an analog multiplier, a low-pass filter,
a comparator, an input level detector, and a
TTL output buffer. The input limiter limits the
FSK input signal eliminating any amplitude
variations.
The Land C tank circuit of the phase shifter is
tuned to resonate with the incoming carrier

The low-pass filter is a simple second-order
Butterworth filter which eliminates the carrier
frequency and higher-order intermodulation
frequencies, and gives the baseband data
which is equivalent to the signal modulated by

C1

2

I

19

r

LIMITER

I

t
INPUT
LEVEL
DETECTOR

L
I

the transmitter. The comparator makes the
decision based on the output of the low-pass
filter with reference to a threshold voltage.
The TTL buffers provide the output data at
TTL levels. The input detection level can be
adjusted through the external resistor to set
the threshold for minimum input level. If the
input level falls below the set threshold, the
output buffers are disabled, preventing the
noise from being interpreted as data.

center frequency. A quadrature detection
scheme is used to demodulate the data. The
balanced analog multiplier processes the incoming signal with its phase-shifted carrier
frequency and generates signals with baseband data and other higher order harmonics.

L1

rr--~

FSK
IN

AN1950

1

-I

,~

4

3

5
PHASE SHIFTER

'----+

LOW-PASS
FILTER

6

7

MULTIPLIER

R1

T C2

8

I

LnFigure 2

February 1987

±
C4

t

5-61

L

t

C3
JA

COMPARATOR

11

DATA
OUT

14

INPUT
LEVEL
DETEC

TTL BUFFERS

I

.~

Signetics Linear Products

Application Note

Application of NE5080 and NE5081 With
Frequency Deviation Reduction

AN1950

APPLICATIONS
NE5080 AND NE5081 chip se1 encompasses
a broad spectrum of data rates and facilitates
economical modem design for various applications. The transmitter can be tuned to
various center frequencies for different data
rates. The wide dynamic range of the receiver
and the excellent drive capability of the transmitter make it possible to drive long distances
without any signal repeaters. The transmitter
is not limited to transmitting on coaxial cable
only; it can also drive a twisted-wire pair and
optical fibers. All these salient features are
discussed in greater detail in AN195.
The major focus of this application note is on
reducing the frequency deviation. The reduction in frequency ratio can be achieved by
bringing the two frequencies fo and f 1 closer
together. This will reduce the overall bandwidth utilized by the modem because the
main lobe in the spectrum becomes narrower.
This gain in bandwidth reduction is offset by a
slight increase in the probability of a bit error
due to poor noise margin. As explained in the
transmitter block diagram section of this application note, the frequency of the oscillator
is controlled by the charging and discharging
current into Co. The two oscillating frequencies can be brought close together either by
lowering the higher frequency f 1 or by raising
the lower frequency fo. Figure 3 shows the
technique for raising the lower frequency fo.
When the logic input is a '1', the two diodes
are reversed biased. In this situation, the
capacitor is charged and discharged by the
current from the internal current sources. As
the logic input changes to a '0', the two
diodes are forward biased. This will increase
the available current from the internal current
sources that are charging and discharging the
capacitor Co, thus resulting in a higher frequency of oscillation than would be obtained
otherwise. The value of resistor R will determine the amount of excess current available,
which will affect the ratio of the higher frequency to the lower frequency (f1/fo).
Figure 4 gives a graph of the deviation ratio
versus the resistor value R for different values of oscillator capacitor Co. It can be seen
from the graph that the deviation ratio remains constant for a fixed value of resistor R

February 1987

14
NE5080

Vee
1

16

Co

DATA

INPUT 0..R

R

1N916

.. 1N916

Figure 3

1.8

if'

,..; ..

1.6

!£'
0

iia:
>

~

1.4

"z

'

....

--

f.l ..

W

---. Co =33pF
........ Co =56pF

::J

S
a:

...

...
-to

1.2

--.Co =l30pF

Co =500pF
-~0~4.~n~ I
--II

1.0
10.0

1.0

100.0
RESISTOR R (IN kQ)

1.0E3

Figure 4
over a wide range of capacitor values Co. It
should be noted that the effective data rates
will be lower when the frequency deviation is
reduced. A similar scheme can also be applied to increase the frequency ratio and
thereby increase the data rate, but this will be
done at the cost of extra bandwidth. Using

5-62

appropriate filters for the transmitters and
receivers, a frequency division multiplexing
(FDM) can be achieved for more efficient
usage of the most expensive resource, namely the coaxial cable.

NEjSAjSE5212

Signetics

Transimpedance Amplifier
Preliminary Specification

Linear Products

DESCRIPTION

FEATURES

The NE/SAlSE5212 is a low noise differential output amplifier, particularly
suitable for signal recovery in fiber-optic
receivers and in any other applications
where very low signal levels obtained
from high impedance sources need to
be amplified.

•
•
•
•
•
•
•

PIN CONFIGURATION

Extremely low noise: 2.5pAlv!Hi
Single 5V supply
Large bandwidth: 150MHz
Differential outputs
Low input/output impedances
High power supply rejection ratio
14kS1 differential transresistance

APPLICATIONS
•
•
•
•
•

Fiber-optic receivers
Wideband gain block
General purpose instrumentation
Sensor preamplifiers
Single-ended to differential
conversion

• Low noise RF amplifiers

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

o to
o to
o to

8-Pin Plastic DIP
8-Pin Plastic SO
8-Pin Ceramic DIP

ORDER CODE

+ 70'C

NE5212N

+70'C

NE5212D8

+70'C

NE5212FE

8-Pin Plastic SO

-40'C to + 85'C

8-Pin Plastic DI P

-40'C to + 85'C

SA5212N

8-Pin Ceramic DIP

-40'C to + 85'C

SA5212FE

SA5212D8

8-Pin Plastic DIP

-55'C to + 125'C

SE5212N

8-Pin Ceramic DIP

-55'C to + 125'C

SE5212FE

ABSOLUTE MAXIMUM RATINGS
RATING
SYMBOL

PARAMETER

TJ
TSTG

Temperature Range
Operating ambient
Operating junction
Storage

Vee

Power Supply

TA

February 1987

UNIT
NE5212

SA5212

SE5212

o to 70
-55 to 150
-65 to 150

-40 to 85
-55 to 150
-65 to 150

-55 to 125
-55 to 150
-65 to 150

'C
'C
'C

6

6

6

V

5-63

N, FE, D-8 Packages

IINma GND,

vee 2

7

OUT (-)

GND,

3

6

GND 2

GND,

4

5

OUT (+)

Signetics Linear Products

Preliminary Specification

Transimpedance Amplifier

NE/SA/SE5212

RECOMMENDED OPERATING CONDITIONS
SYMBOL

TA

TJ

Vce

PARAMETER

RATING

UNIT

Ambient temperature ranges
NE Grade
SA Grade
SE Grade

o to 70
-40 to 85
-55 to 125

°C
°C
°C

Junction temperature ranges
NE Grade
SA Grade
SE Grade

o to 90
-40 to 105
-55 to 145

°C
°C
°C

4.5 to 5.5

V

Supply voltage range

DC ELECTRICAL CHARACTERISTICS Minimum and Maximum limits apply over operating temperature range at Vcc = 5V.
unless otherwise specified. Typical data applies at Vee = 5V and TA = 25°C.
NE5212
SYMBOL

PARAMETER

SA/SE5212

TEST CONDITIONS

UNIT
Min

Typ

Max

Min

Typ

Max

VIN

Input bias voltage

0.6

0.8

0.95

0.55

0.8

1.05

VO±

Output bias voltage

2.8

3.3

3.7

2.5

3.3

3.8

V

Vas

Output offset voltage

0

80

0

120

mV

32

33

mA

V

lee

Supply current

21

26

20

26

3

4

3

4

mA

lOMAX

Output sink/source current

18

Maximum input current (2% linearity)

±60

±80

±40

±80

J1A

IMAX

Maximum input current overload
threshold

±80

± 120

±60

± 120

J1A

1100
750
750

mW

PD

Maximum power 1 dissipation
B-pin plastic DIP
B-pin plastic SO
B-pin Cerdip

1100
750
750

NOTE:
1: Package
B-pin
B-pin
B-pin

thermal resistances are as follows:
plastic DIP: 110°C/W
plastic SO: 160°C/W
Cerdip: 165°C/W

February 19B7

5-64

Preliminary Specification

Signetics Linear Products

NE/SA/SE5212

Transimpedance Amplifier

AC ELECTRICAL CHARACTERISTICS

Minimum and Maximum limits apply over operating temperature range at Vee = 5V,
unless otherwise specilied. Typical data applies at Vee = 5V and TA = 25'C.
SAlSE5212

NE5212
SYMBOL

PARAMETER

UNIT

TEST CONDITIONS
Min

Typ

Max

Min

Typ

Max

RT

T ransresistance
(Differential output)

1= 10MHz, RL = inl

9.8

14

18.2

9.0

14

19

kn

Ro

Output resistance
(Differential output)

1= 10MHz

14

30

42

14

30

46

n

RT

Transresistance
(Single-ended output)

1= 10MHz, RL = inf

4.9

7

9.1

4.5

7

9.5

kn

Ro

Output resistance
(Single-ended output)

f = 10MHz

7

15

21

7

15

23

n

13dB

Bandwidth (-3dB)

RIN

Input resistance

CIN

Input capacitance

f:J.R/f:J.V

T ransresistance power
supply sensitivity

f:J.R I f:J.T

Test Circuit 1
D package,
TA = 25'C
N, F packages,
TA = 25'C

120

120
100
75

MHz

100

110

143

10

15

70

MHz

110

150

n

10

18

pF

f:J.Vee = 5 ± 0.5V

9.6

9.6

%N

Transresistance ambient
temperature sensitivity

D package
f:J.TA = TA MAX- TA MIN

0.05

0.05

%;oC

IN

Input RMS noise current
spectral density

Test Circuit 2
I = 10MHz TA = 25'C

2.5

2.5

pA/YHz

IT

Input RMS noise current

f:J.I = 100MHz, TA = 25'C
Test Circuit 2

30

30

nA

PSRR

Power supply rejection ratio 3
Vecl = VCC2

Any package
1=0.1MHz1,2
Test Circuit 3
f:J.Vcc = 0.1V

33

dB

PSRR

Power supply rejection ratio
(ECl conliguration)

Any package
1=0.1MHz1 ,2
Test Circuit 4

23

dB

Vo MAX

Maximum output voltage swing
differential

3.2

Vp.p

RL = info

26

33

23

2.4

3.2

NOTES:
1. Circuit board layout dependent at higher frequencies. For best performance use RF filter in Vee lines.
2. VCC1 and VCC2 are internally connected in all a-pin packages.
3. Output referenced.

February 1987

5-65

20

1.7

Signetics Linear Products

Preliminary Specification

Transimpedance Amplifier

HP3577A NETWORK ANALYZER

NEjSAjSE5212

DIFFERENTIAL

SINGLE-ENDED
VOUT
Rt • - - R =$21 KR

V,N

Ao =Zo

HP8568B SPECTRUM ANALYZER

Atll Your R=2xS21KR
V,N

I'-:r:i22 I

+ S22 ~ 33

Ro

822 1
=2Zo 11+
-:r:i22
- SS

NC

a. Test Circuit 1

b. Test Circuil 2

HP3577A NETWORK ANALYZER

HP3577AB S-PARAMETER TEST SET
PORT'

PORT 2

TEKTRONIX

015-046
CURRENT PROBE

16
'--'I/II'r--+
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _..... CAL.

TRANSFORMER
NH0300HB

c. Test Circuit 3
Figure 1. Test Circuits

February 1987

5-66

~
UNBAL

TEST

Signetics Linear Products

Preliminary Specification

Transimpedance Amplifier

NE/SA/SE5212

.• .,

HP3snA NETWORK ANALYZER

• •

HP3577AB S·PARAMETER TEST SET
PORT 1

QNDI

TEKTRONIX

015-G46
CURRENT PROBE

to#F

=¥o.,.Fl

PORT2

~

,.

CAL.

QND,I GND, 33
OUT
IN 0-

DUT

33

lr,F
"
I.F

100
BAL.

TRANSFORMER
NH0300HB

>-

~

TEST

UNBAL.

OUT

Vee

.L

I

"I

II

a. Test Circuit 4
Figure 1. Test Circuits

PRECAUTIONS
As with any high·frequency device, some
precautions must be observed in order to
enjoy reliable performance. First of these is
use of a well·regulated power supply. The
supply must be capable of supplying varying
amounts of current without significantly

February 1987

changing the voltage level. Next, of course, is
proper power supply bypassing consisting of
a good quality O.1I1F high·frequency capacitor
in parallel with a 10l1F tantalum capacitor.
Some applications require an RF choke in
series with the power supply line. These
components should be mounted as close to

5-67

the device pins as possible with the shortest
leads possible.
Seperate analog and digital ground leads
should be maintained and printed circuit
board ground plane should be employed
whenever possible.

Signetics Linear Products

Preliminary Specification

Transimpedance Amplifier

NEjSAjSE5212

BASIC CONFIGURATION
+5V

A trans-resistance amplifier is a current-tovoltage converter. The forward transfer function then is defined as voltage out divided by
current in, and is stated in ohms. The lower
the source resistance, the higher the gain.
The NE5212 has a differential transresistance of 14kQ typically and a single-ended
transresistance of 7kQ typically. The device
has two outputs: inverting and non-inverting.
The output voltage in the differential output
mode is twice that of the output voltage in the
single-ended mode. Although the device can
be used without coupling capacitors, more
care is required to avoid upsetting the internal
bias nodes of the device. Figure 2 shows
some basic configurations.

I->

r-Z

0UT

1111<

2.4>

+5V

Figure 3. Variable Gain Circuit

R =560

IN

a. Non-Inverting 20dB Amplifier
+5V

gate of the 80210 OM08 FET. The series
resistance of the FET changes with this
output voltage which in turn changes the gain
of the NE5212. This circuit has a distortion of
less than 1% and a 25dB range, from
-42.2dBm to -15.9dBm at 50MHz, and a
45dB range, from -60dBm to -14.9dBm at
10MHz with 0 to lV of control voltage at Vc.

16MHz CRYSTAL OSCILLATOR

b. Inverting 20dB Amplifier

Figure 4 shows a 16MHz crystal oscillator
operating in the series resonant mode using
the NE5212. The non-inverting input is fed
back to the input of the NE5212 in series with
a 2pF capacitor. The output is taken from the
inverting output.

+5V

DIGITAL FIBER-OPTIC
TRANSMITTER/RECEIVER
Figures 5a and b show a fiber-optic transmitter using off-the-shelf components and the

V'No--!

c. Differential 20dB Amplifier
Figure 2

February 1987

The receiver shown in Figure 5b uses the
NE5212, the 8ignetics 10116 EeL line receiver, and a Hewlett-Packard HFBR-2208 PIN.
The circuit is a capacitor-coupled receiver
and utilizes positive feedback in the last stage
to provide the hysteresis. The amount of
hysteresis can be tailored to the individual
application by changing the values of the
feedback resistors to maintain the desired
balance between noise immunity and sensitivity. At room temperature, the circuit operates at 50Mbaud with a BER of 1OE-1 0 and
over the automotive temperature range at
40Mbaud with a BER of 10E-9. Higher speed
experimental diodes have been used to operate this circuit at 220M baud with a BER of
1OE-l0.
The cost of the transmitter/receiver pair is
about $50 with the standard parts.

VARIABLE GAIN
Figure 3 shows a variable gain circuit using
the NE5212 and the NE5230 low voltage op
amp. This op amp is configured in a noninverting gain of five. The output drives the

NE5212. The circuit uses a 8ignetics TIL line
driver, 74F3037, and a Hewlett·Packard
HFBR-1404 LEO. This combination is nearly
ideal because LEOs are harder to turn off
quickly than on, and because the unequal
drive capabilities of the TTL totem-pole output configuration complement each other.
This pre-bias current and the speed-up capacitor Significantly decrease the transition
times. The circuit will has rise and fall times of
3ns. It operates over the automotive temperature range at 170Mbaud. The design formulas
presented here can be used to optimize the
speed for other devices.

Figure 4. 16MHz Crystal Oscillator

5-68

Signetics

Section 6
Telecommunications

Linear Products

INDEX
TELEPHONY
NE5900
PCD3310
PCD33111
3312
PCD3315
PCD3360
TEA1046A
TEA1060/61
TEA1067
AN1942
AN1943
TEA1068
TEA1075
TEA1080

Call Progress Decoder.........................................................
Pulse and DTMF Dialer With Redial.......................................

6-3
6-10

DTMF/Modem/Musical Tone Generator.. ..... ..... .... ....... .... ..... ...
CMOS Redial and Repertory Dialer ....................................... .
Programmable Multi-Tone Telephone Ringer ............................ .
Transmission Interface With DTMF ........................................ .
Versatile Telephone Transmission Circuits With Dialer Interface ... .
Low Voltage Transmission IC With Dialer Interface ................... .
Application of the Low Voltage Versatile Transmission Circuit ..... .
Supply of Peripheral Circuits With the TEA 1067 Speech Circuit ... .
Versatile Telephone Transmission Circuit ................................ .
DTMF Generator for Telephone Dialing .................................. .
Supply IC for Telephone Set Peripherals ................................ .

6-24
6-37
6-45
6-53
6-65
6-76
6-88
6-108
6-114
6-125
6-135

Signetics

NE5900
Call Progress Decoder
Product Specification

Linear Products

DESCRIPTION
The NE5900 call progress decoder
(CPD) is a low cost, low power CMOS
integrated circuit designed to interface
with a microprocessor-controlled smart
telephone capable of making preprogrammed telephone calls. The call progress decoder provides information to
permit microprocessor decisions whether to initiate, continue, or terminate calls.
A tri-state, 3-bit output code indicates
the presence of dial tone, audible ringback, busy signal, or reorder tones.
A front-end bandpass filter is accomplished with switched capacitors. The
bandshaped signal is detected and the
cadence is measured prior to output
decoding. In addition to the three data
bits, a buffered bandpass output and
envelope output are available. All logic
inputs and outputs can interface with
LSTTL, CMOS, and NMOS.
Circuit features include low power consumption and easy application. Few and

inexpensive external components are
required. A typical application requires a
3.58MHz crystal or clock, 470kn resistor, and two bypass capacitors. The
NE5900 is effective where traditional call
progress tones, PBX tones, and precision call progress tones must be correctly interpreted with a single circuit.

• PBXs
• Security equipment
•
•
•
•

Auto dialers
Answering machines
Remote diagnostics
Pay telephones

PIN CONFIGURATION

FEATURES

0' and N Packages

• Fully decoded tri-state call
progress status output
• Works with traditional, precision,
or PBX call progress tones
• Low power consumption
• Low cost 3.58MHz crystal or
clock

INPUT

1

V REF

2

15

EXT ClOCK
IN/XTAL1

14

~~~LOG

~~IAS:t~E
ENVELOPE
BIT 1

• No calibration or adjustment
• Interfaces with LSTTL, CMOS,
NMOS

COUNTIN
PROGRESS

• Easy application

TOP VIEW
NOTE:
1. SOL - Released in large SO package only.

APPLICATIONS
• Modems

BLOCK DIAGRAM CPO
ANAlOG OUT

OV

VREF

5V

TRI-STATE
ENABLE

INPUT
ENVELOPE

EXT ClOCK
IN/XTAL1

Bill

8112

XTAL2

BIT 3

TEST
IN

May 8, 1986

CLEAR
IN

6-3

COUNT IN
PROGRESS

DATA
VALID

853-0842 83667

I

Product Specification

Signetics Linear Products

NE5900

Call Progress Decoder

ORDERING INFORMATION
DESCRIPTION

AMBIENT TEMPERATURE

o to
o to

16-Pin Plastic SOL
16-Pin Plastic DIP

ORDER CODE

+70·C

NE5900D

+70·C

NE5900N

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

RATING

UNITS

9

V

Logic control input voltages

-0.3 to + 16

V

VIN

All other input voltages 1

-0.3 to Vcc
+0.3

V

VOUT

Output voltages

-0.3 to Vcc
+0.3

V

TSTG

Storage temperature range

-65 to +150

·C

TA

Operating temperature range

o to +70

·C

VDD

Power supply voltage

VIN

TSOLD

Lead soldering temperature (1 Os)

+300

·C

TJ

Junction temperature

+150

·C

NOTE:
1. Includes Pin 3 - Ex1 Clock In

May 8, 1986

6-4

Signetics Linear Products

Product Specification

Call Progress Decoder

DC ELECTRICAL CHARACTERISTICS

NE5900

Unless otherwise stated, VDD = + 5.0V; Pin 3 fosc = 3.5BMHz; Ambient
Temperature = a to + 70°C. Pin 5 = OV, Pin 14 = VDD .
LIMITS

SYMBOL

PARAMETER

UNIT

TEST CONDITONS
Min

Typ

Max

4.5

5.0

5.5

V

Power supply voltage

Pin 16
Pin 14 = VDD
Pins 5, 6 = OV

Quiescent current

As above with no output loads.

2.0

4.0

mA

Input threshold

Pin 1 level, frequency = 460Hz,
VDC = VREF Output Pin 13 = VDD

-39

-35

dB 1

Signal rejection

Pin 1 level, 300Hz frequency,
VDC=VREF Output Pin 13 = OV

-50

dB 1

Low frequency2 rejection

Pin 1 frequency, OdB max.,
VDC = VREF Output Pin 13 = OV

lBO

Hz

High frequency2 rejection

Pin 1 frequency OdS max.,
VDC = VREF Output Pin 13 = OV

BOO

VIH

Logic 1 input voltage

Pins 6, 14

2.0

15

VIL

Logic

Pins 6, 14

0

O.B

V

IHL

Logic 1 input current

Pins 3, 6, 14 = VDD

-1.0

1.0

Jl.A

VDD

a input

voltage

Hz
V

IlL

Logic 0 input current

Pins 3, 6, 14 = OV

-1.0

1.0

jJ.A

VIH

Logic 1 input voltage

Pin 3 External Clock In/XTAL

VDD-l

VDD

V

VIL

Logic 0 input voltage

Pin 3 External Clock In/XTAL

0

1.0

V

0

0.4

V

VDD

V

3.0

Jl.A

10.5

dB

1.0

dBmo

VOL

Logic

voltage

ISINK = 1.6mA
Pins 7, 9, 10, 11, 12, 13

VOH

Logic 1 output voltage

ISOURCE = 0.5mA
Pins 7, 9, 10, 11, 12, 13

loz

Tri-state leakage

VOUT = VDD or OV
Pins 10, 11, 12, 13
Pin 14 = OV

Filter output gain

Input Pin 1, 460Hz - 20dB,
VDC = VREF Output Pin 15,
RLOAD= lMn

Filter frequency response

As above from 300Hz to 630Hz,
referenced to 460Hz

a output

VDD - 0.4

-3.0

6.5

8.5

-1.0

Input impedance2

Pin 1, frequency = 460Hz

VREF

Reference voltage

Pin 2, VDD = 5V

RREF

Reference resistance

Pin 2

5

n

Envelope response time

Time from removal or application
of 460Hz - 20dB (VDc = VREF on
Pin 1) to response of Pin 13

38

ms

NOTES:
1. OdB = O.775VRMS.

2. By design; not tested.

May 8, 1986

6-5

1
2.4

Mn
2.5

2.6

V

Signetics linear Products

Product Specification

Call Progress Decoder

The NES900 uses the signal in the call
progress tone passband and the cadence or
interrupt rate of the signal to determine which
call progress tone is present.
Figure 1 shows a detailed block diagram of
the NES900.
The signal input from the phone line is
coupled through a 470kn resistor which,
together with two internal capacitors and an
internal resistor, form an anti-aliasing filter.
This passive low pass filter strongly rejects
AM radio interference. Insertion loss is typically 1.SdB at 460Hz. The 470kn resistor
also provides protection from line transients.
The input (Pin 1) DC voltage can be derived
from VREF (Pin 2) or allowed to self-bias
through a series coupling capacitor (10nF
minimum).
Following this is a switched capaCitor bandpass filter which accepts call progress tones
and inhibits tones not in the call progress
band of 300Hz to 630Hz. The bandpass limits
are determined by the input clock frequency
of 3.SBMHz. An on-board inverter between
Pins 3 and 4 can be used either as a crystal
oscillator or as a buffer for an external
3.SBMHz clock signal. The switched capacitor
filters provide typical rejection of greater than
40dB for frequencies below 120Hz and above
1.6kHz.

INPUT

NE5900

The decoder responds to signals between
300Hz and 630Hz with a threshold of -39dB
typical (OdB = O.77SVRMS). The decoder will
not respond to any signals below -SOdB or to
tones up to OdB which are below 1BOHz or
above BOO Hz. Dropouts of 20ms or bursts of
only 20ms duration are ignored. A gap of
40ms or a valid tone of 40ms is detected.
The buffered output of the switched capacitor
filter is available at the analog output, Pin 1S.
A logic output representing the detected envelope of this signal is available at the envelope output, Pin 13.
At the start of an in-band tone (envelope
output goes high), a 2.3-second interval is
timed out. Transitions of the envelope during
this interval are counted to determine the
signal present. At 2.3 seconds, the three bits
of data representing this decision are stored
in the latch and appear at the outputs. A data
valid signal goes high at this time, signaling
that the data bits, Pins 10- 12, can be read.
The output code is as follows:
PIN 12 PIN 11 PIN 10
DIAL TONE
RINGING SIGNAL
BUSY SIGNAL
REORDER TONE
OVERFLOW

o

o

o
o

o

o

o

o
o

The overflow condition occurs in the event
that too many transitions occur during the
2.3-second interval. This can result from
noise, voice, or other line disturbances not
normally present during the post-dialing interval. Note that the end of dial tone is interpreted as a valid ringing signal.
The clear input resets all internal registers
and the output latch, and is to be set low after
the completion of dialing. The clear input
should be pulsed high for proper operation.
Recommended pulse width is between O.2J.ls
and 20ms. If clear is held high when envelope
is high, a false output pulse (Pin 13) can result
when clear is returned low.
For applications where dialing is done by a
person rather than by a microprocessor, an
uncertainty exists about the number of digits
to be dialed (local vs long distance). In such
situations it is possible to clear the NES900
by application of the DTMF signal or dial
pulses to the clear pin (Pin 6). When dialing is
complete, the device is cleared and ready to
respond to the next call progress unit.
Enable is held at SV to enable Pins 10, 11, 12,
and 13. When enable is brought low, data
valid is also set low. Enable must remain high
while the data is being read. The test pin is for
production test only and must be kept low in
all user applications.

>-------- ~~~lDG

L;><>---i

- .....-o<-,sv
XTAL2

-____--Ir---<>Ci ~:~~I~TE
ENVELOPE

t------«--=>

COUNT IN
PROGRESS
DATA VALID

BIT 1

--~L........"BIT2

BIT 3

Figure 1. Detailed Block Diagram CPO

May B, 1986

6-6

Signetics Linear Products

Product Specification

NE5900

Call Progress Decoder

Figure 2 shows a typical application of the call
progress decoder.
In this application only one external component is needed and no microprocessor activity other than clear is required.

Figure 3 shows the recommended direct
interface to the telephone line. Bus connection is possible by utilizing tri-state, and internal timing is accomplished with a 3.5SMHz
crystal.

TO EAR-PIECE

I

3.58MHz IN
'0nF470k

-l
1
~

The designer can utilize the input signal,
clock, bus, or microprocessor interface which
best serves the application. Figure 4 gives a
typical timing diagram for the application of
Figures 2 and 3.

LJ>'.>--------1

t - -......-o.Cl

5V

t-----<:4-:>

ENVELOPE

LJ>'.>--------1

__

BIT 1

2

10nF:r:

BIT 2

:

=

I

t-----<:oI-:>

OPTIONAL
CAPACITIVE
INPUT

BIT 3
INTERRUPT

START
CLEAR

Figure 2. Typical Application

IN1

C1

C>o-f
10nF

IN2

C2

D>--l10nF

R5
R1

16

5V

470kQ
15

100k

4

R2

,.

ENABLE

13

ENVELOPE

5
100k

12

100k
R3
100k

R6
10M

11

0

} DECODED
OUTPUTS TO
PROCESSOR

10
3.S8MHz

INTERRUPT

START
CLEAR

Figure 3. Typical Two-Wire Application

May S, 1986

6-7

.1
I

NE5900

Signetics Linear Products

Product Specification

NE5900

Call Progress Decoder

INPUT

CLEAR

ENVELOPE - -_ _ _ _ _ _ _..,..

1 -2,27 SECONOS-l

...-----.

DATA VALID

I ,,' SECONDS I
BIT 1

BIT 2

BIT 3

TYPICAL

u

COUNTIN~

PROGRESS

Figure 4

May 8, 1986

6-8

u

Signetics linear Products

Product Specification

NE5900

Call Progress Decoder

TYPICAL PERFORMANCE CHARACTERISTICS

Power Supply Current vs VDO

5

3.0

~ 2.5

z

'J'

~

l....

2.0

zw

./

1.5

0:
0:

1.0

::>

0.5

..
'"

w

/""

::>

"~

4

.!5!5

V

0

3

z
~

c

s

\

2

4.0

5.0

4.S

5.5

0.0

z

ii: -2.5

1

2

3

0

4

;: -5.0

i!i

~ -7.5

V

::>

"
I-

~-10.0

-15.0

0

/

/

\9

,;

~

~
w

ill
5

OUTPUT VOLTAGE (PIN 13)

-20

/
-'nJ
-60

100

5

Typical Threshold
-20

\

~

w

iti-35
....
z

0:-40

{"

-45

-so

1000

--

300

/

./'

350

400

450

500

550

600

',",,'

650

FREQUENCY (Hz)
OP06681S

6-9

•

-25

fii'-30

FREQUENCY (40 TO 4000Hz)
OPQ6671S

May 8, 1986

2
3
4
OUTPUT VOLTAGE (PIN 13)

1

OP06661S

CD

l!.
~

~2:

4

oV
0

5

\

~

0:

3

D

z

V
2

/

OPOS651S

~

1

10

Filter Frequency Response

/.

:fE

/

V

INPUT VOLTAGE (PIN 3)

/

~

--

20

.."55

\

1

0

Output Voltage Current Curve
Digital Output High

" -12.5

w

0:
0:

OP06640S

0

30

V

::>

SUPPLY VOLTAGE(VDol(PIN 16)

....

'z"

iJj

0
3.5

40

....
Z

\r--....

0.0
3.0

-

~

\

~

"g~

so

""'\

z

/""

V

Output Voltage Current Curve
Digital Output Low

Voltage Transfer Curve

OP15220S

"

Signetics

PCD3310
Pulse and DTMF Dialer With
Redial
Product Specification

Linear Products

PIN CONFIGURATIONS

DESCRIPTION

FEATURES

The PC03310 is a single-chip silicongate CMOS integrated circuit with an onchip oscillator for a 3.58MHz crystal. It is
a dual-standard dialing circuit for either
pulse dialing (PO) or dual-tone multifrequency (DTMF) dialing.

• PD and DTMF dialing.
• 23-digit capacity for redial
operation (cursor method)
• Memory clear and electronic
notepad
• Mixed mode dialing (start with
PD and end with DTMF dialing)
• Dual redial buffers for PABX and
public calls
• Four extra function keys:
program, flash, redial and PD-toDTMF (mixed dialing)

Input data is derived from any standard
matrix keypad for dialing in either OP or
DTMF mode. Numbers of up to 23 digits
can be retained in RAM for redial and
notepad facilities.
In OTMF mode, bursts as well as pauses
are timed to a minimum in manual dialing, the maximum depending on the key
depression time.

• DTMF timing:
- manual dialing-minimum
duration for bursts and pauses
- redialing-calibrated timing
• On-chip voltage reference for
supply, and temperature
independent tone output
• On-chip filtering for low output
distortion (CEPT CS 203
compatible)
• On-chip oscillator with low cost
3.58MHz TV color-burst crystal
• Uses standard single-contact or
double-contact (common left
open) keypad
• Keyboard entries fully debounced
at both edges
• Flash (register recall) output

N Package

TOP VIEW

D Package

APPLICATIONS
• Single standard telephone sets
• Dual standard telephone sets

TOP VIEW

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE
RANGE

ORDER CODE

20-Pin Plastic DIP (SOT-146)

-25·C to + 70·C

PCD3310PN

28-Pin Plastic SO (SO-28; SOT-136A)

-25·C to + 70·C

PCD3310TD

December 2, 1986

6-10

853-1042 86701

Signetics Linear Products

Product Specification

PCD3310

Pulse and DTMF Dialer With Redial

BLOCK DIAGRAM

21 DPIFLO
PCD3310

POIDTMF

C

A

M

D
D

A
I
N
R
E
G

OUTPUT
TR
E E

MG
P I

I
S
T
E

o E
IA

D

EW

E

0
D
I
N

G

Os
RT
AE

E
R

P R

R
E
S
S
C

R

0
U
N
T

27

II D

T I

R R

ci

5

o T
N E
T
R
0

Vas

L
L

E

~R

TONE

NOTE:
1. Pins 4, 6, 7, 11, 18, and 25 are not connected.

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

VDD

Supply voltage range

IDD

Supply current

±11o ±Io

DC current into any input or output

VI

All input voltages

PTOT

Total power dissipation

RATING

UNIT

-0.6 to 6

V

50

mA

10

mA

-0.6V to VDD + 0.8

V

300

mW

Po

Power dissipation per output

50

mW

TSTG

Storage temperature range

-65 to + 150

·C

TA

Operating ambient temperature range

-25 to +70

·C

December 2. 1986

VDD

6-11

Signetics Linear Products

Product Specification

Pulse and DTMF Dialer With Redial

DC AND AC ELECTRICAL CHARACTERISTICS

PCD3310

VDD = 3V; Vss = OV; crystal parameters: fose = 3.579545MHz; Rs = 50n
max.; TA = -25°C to + 75°C, unless otherwise specified.
LIMITS

SYMBOL

PARAMETER

UNIT
Min

Typ

Max

Supply
VDO

Operating supply voltage

2.5

6.0

V

VDOO

Standby supply voltage

1.8

6.0

V

looe
IODP
IDDF
IDOF

Operating supply current
conversation mode (oscillator ON)
pulse dialing or flash
OTMF dialing (tone ON)
OTMF dialing (tone OFF)

100
200
1.2
200

!J.A
mA
!J.A

5

JJ.A

V

IDDO

Standby supply current 1 (OSCillator OFF)
at VDD = 1.8V; TA = 25°C

JJ.A

INPUTS
VIL

Input voltage LOW (any pin)

0

0.3VDD

VIH

Input voltage HIGH (any pin)

0.7VDD

VDD

V

IIILI

Input leakage current; CE

1

JJ.A

2

kn

Keyboard inputs
RKON

Keyboard ON resistance

RKOFF

Keyboard OFF resistance

500

10L
10L

Output sink current at VOL = Vss + 0.5V
M1, M1, M2, OP/FLO, CF, FLO
PO/OTMF2

0.7

-IOH
-IOH
-IOH

Output source current at VOH
M1, M1, M2, OP/FLO, CF
PO/OTMF2
FL03

kn

OUTPUTS

= VOO -

1

mA
mA

0.5V
0.6
1
100

mA
mA
nA

TIMING AND FREQUENCY
ioN

Clock start-up time

4

ms

tE

Oebounce time

12

ms

tRO

Reset delay time

160

ms

fCT

Confidence tone frequency

330

Hz

TONE output (see Figure 9) at VDO = 2.5 to 6V
VHG(RMS)
VLG(RMS)

OTMF output voltage levels (RMS value)
HIGH group
LOW group

158
125

ll.f/f

Frequency deviation

-0.6

VOC

OC voltage level

IZol

Output impedance

ll.VG

Pre-emphasis of group

THO

Total harmonic distortion4 at TA = 25°C

December 2, 1986

192
150

205
160

mV
mV

+0.6

%

0.1

0.5

kn

2.1

2.35

dB

V

Y2VOD

1.85

-25

6-12

dB

Signetics Linear Products

Product Specification

Pulse and DTMF Dialer With Redial

PCD3310

DC AND AC ELECTRICAL CHARACTERISTICS (Continued)

VD D = 3V; vss = OV; crystal parameters:
lose = 3.579545MHz; Rs = 50n max.; TA
+ 75°C, unless otherwise specified.

= _25°C

to

LIMITS
SYMBOL

PARAMETER

UNIT
Min

Typ

Max

Transmission and pause time

tT, tp

Manual dialing

68

tT, tp

Redialing

68

70

72

ms

tFL

Flash pulse duration

98

100

102

ms

tFLH

Flash hold-over time

33

ms

tH

Hold-over time (muting on M1)

80

ms

ms

Pulse dialing (PO)

fop

Dialing pulse frequency

10

Hz

tiD

Inter-digit pause

840

ms

ts

Break timeS

67

ms

tM

Make timeS

33

ms

NOTES:
1. Crystal connected between

2.

< Il0mAI

ascI

and OSCO; CE at VS8 and all other pins open·circuit.

dynamic current to set/reset PD/DTMF pin (mixed mode).

3. Flash inactive; YOH = Vss.

4. Related to the level of the LOW group frequency component (CEPT CS 203).
5. Mark-ta-space ratio 2: 1.

II

December 2, 1986

6-13

Signetics Linear Products

Product Specification

Pulse and DTMF Dialer With Redial

FUNCTIONAL DESCRIPTION
Power Supply (VDD; VSS)
The positive supply of the circuit (V DO) must
meet the voltage requirements as indicated in
the characteristics.
To avoid undefined states of the device when
powered-on, an internal reset circuit clears
the control logic and counters.
If Voo drops below the minimum standby
supply voltage of I.BV the power-on reset
circuit inhibits redialing after hook-off.
The power-on reset signal has the highest
priority. It blocks and resets the complete
circuit without delay regardless of the state of
chip enable input (CE).

Clock Oscillator (OSCI, OSCO)
The time base for the PCD3310 for both PD
and DTMF modes is a crystal-controlled onchip oscillator which is completed by connecting a 3.58MHz crystal between the ascI
and OSCO pins.

Chip Enable (CE)
The CE input enables the circuit and is used
to initialize the IC.
CE = LOW provides the static standby condition. In this state the clock oscillator is disabled, all registers and logic are reset with the
exception of the Write Address Counter
(WAC) and Temporary Write Address Counter
(TWAC) which point to the last entered digit
(Figure 3). The keyboard input is inhibited, but
data previously entered is saved in the redial
register as long as Voo is higher than
VOOO(MIN)'

PCD3310

The current drawn is 1000 (standby current)
and serves to retain data in the redial register
during hook-on.
CE = HIGH activates the clock oscillator and
the circuit changes from static standby condition to the conversation mode. The current
consumption is loDe until the first digit is
entered from the keyboard. Then a dialing or
redialing operation starts. The operating current is loop if in the pulse dialing mode, or
100F if the DTMF dialing mode is selected.
If the CE input is taken to a LOW level for
more than time tRO (see Figures 7a, 7b and
timing data), an internal reset pulse will be
generated at the end of the tRO period. The
system changes to the static standby state.
Short CE pulses of < tRo will not affect the
operation of the circuit, and reset pulses are
not produced.

Mode Selection (PD/DTMF)

The transmission time is calibrated for redial.
In manual operation the duration of bursts
and pauses is the actual pushbutton depress
time, but not less than the minimum transmission time (tT) or minimum pause time (tp).
Mixed Mode
When the PD/DTMF pin is open-circuit, the
mixed mode is selected. After activation of
CE or FL (flash) the circuit starts as a pulse
dialer and remains in this state until a nonnumeric (A, B, C, D, *, #) or the" > .. key is
activated. Then the circuit changes over to
DTMF dialing and remains there until FL is
activated or, after a static standby condition,
CE is re-activated.
A connection between PD/DTMF pin and
Voo also initiates DTMF dialing. Chip enable,
FL, or a connection of PD/DTMF pin to Vss
sets the circuit back to pulse dialing.

Keyboard Inputs/Outputs

PO Mode
If PD/DTMF = Vss, the pulse mode is selected. Entries of non-numeric keys are neglected; they are not stored in the redial register
nor transmitted.
DTMF mode
If PD/DTMF = Voo, the dual tone multi-frequency dialing mode is selected. Each nonfunction pushbutton activated corresponds to
a combination of two tones, each one out of
four possible LOW and HIGH group frequencies. The frequencies are transmitted with a
constant amplitude, regardless of power supply variations, and filtered off harmonic content to fulfill the CEPT CS 203 recommendations.

The sense column inputs COL I to COL 4
and the scanning row outputs ROW I to
ROW 5 of the PCD3310 are directly connected to the keyboard as shown in Figure 2.
All keyboard entries are debounced on both
the leading and trailing edges for approximately time tE as shown in Figure 7. Each
entry is tested for validity.
When a pushbutton is pressed, keyboard
scanning starts and only returns to the sense
mode after release of the pushbutton.
Row 5 of the keyboard contains the following
special function keys:
• P
memory clear and programming
(notepad)
• FL
flash or register recall

R

FLD
NOTE:
Where: tFlRC ~ RC

a.

b.
Figure 1. Flash Pulse Duration Setting

December 2, 1986

6-14

Product Specification

Signetics Linear Products

Pulse and DTMF Dialer With Redial

PCD3310

Table 1. Frequency Tolerance of the Output Tones for DTMF
Signaling
ROWI
COLUMN
Row
Row
Row
Row

FREQUENCY DEVIATION

STANDARD
FREQUENCY Hz

TONE OUTPUT
FREQUENCY Hz 1

697
770
852
941

697.90
770.46
850.45
943.23

+0.13
+0.06
-0.18
+0.24

+0.90
+0.46
-1.55
+2.23

1209
1336
1477
1633

1206.45
1341.66
1482.21
1638.24

-0.21
+0.42
+0.35
+0.32

-2.55
+5.66
+5.21
+5.25

1
2
3
4

Call
Col 2
Col 3
Col 4

%

Hz

redial procedure with the "Flash" inserted
telephone number). The counter of the reset
delay time is held during the period of tFL'

COLUMNS

I I I I
'---

1

2

3

A

4

5

6

B

7

6

•

C

*

0

#

0

FL

R

>

P

KEYBOARD

Figure 2. Keyboard Organization
• R

• >

redial
change of dial mode from PD to
DTMF in mixed dialing mode

In pulse dialing mode, the valid keys are the
10 numeric pushbuttons (0 to 9). The non·
numeric keys (A, B, C, D, " #) have no effect
on the dialing or the redial storage. Valid
function keys are P, FL and R.
In DTMF mode all non·function keys are valid.
They are transmitted as a dual tone combina·
tion and at the same time stored in the redial
register. Valid function keys are P, FL and R.
In mixed mode all key entries are valid and
executed accordingly.

Flash Duration Control (FLO)
Flash (or register recall) is activated by the FL
key and can be used in DTMF and pulse
dialing mode. Pressing the FL pushbutton will
produce a timed line·break of 100ms (min.) at
the DP /FLO output. During the conversation
mode this flash pulse entry will act as a chip
enable. This flash pulse duration (tFd is
calibrated and can be prolonged with an
external resistor and capacitor connected to
the FLO input! output (see Figure 1).
The flash pulse resets the read address
counter (RAC). Later redial is possible (see
December 2, 1986

Inverted output of M1. In the PCD3310P it is
only available as a bonding option of M1.

Strobe Output (M2)
Active HIGH output during actual dialing; I.e.,
during break or make time in pulse dialing, or
during tone ON/OFF in DTMF dialing. Avail·
able only in 28'pin surface mount device.

Confidence Tone Output (CF)
When any of the keys are activated, a square
wave is generated and appears at this output
to serve as an acoustic feedback for the user.

DIALING PROCEDURES
Dialing

NOTE:
1. Tone output frequency when using a 3.579545MHz crystal.

ROWS

Mute Output (M1)

TONE OUTPUT (DTMF mode)
The single and dual tones which are provided
at the TONE output are filtered by an on·chip
switched·capacitor filter, followed by an on·
chip active RC low·pass filter.
Therefore, the total harmonic distortion of the
DTMF tones fulfills the CEPT CS 203 recom·
mendations. An on·chip reference voltage
provides output·tone levels independent of
the supply voltage. Table 1 shows the fre·
quency tolerance of the output tones for
DTMF signaling.
When the DTMF mode is selected, output
tones are timed in manual dialing with a
minimum duration of bursts and pauses, and
in redial with a calibrated timing. Single tones
may be generated for test purposes
(CE = HIGH). Each row and column has one
corresponding frequency. High group fre·
quencies are generated by connecting the
column to Vss. Low group frequencies are
generated by forcing the row to VDD. The
single·tone frequency will be transmitted duro
ing activation time, but it is neither calibrated
nor stored.

Dial Pulse and Flash Output
(DP/FLO)
This is a combined output which provides
control signals for proper timing in pulse
dialing or for a calibrated break in both dialing
modes (flash or register recall).

Mute Output (M1)
During pulse dialing the mute output becomes
active HIGH for the period of the inter·digit
pause, break time and make time. It remains
at this level until the last digit is pulsed out.
During DTMF dialing the mute output be·
comes active HIGH for the period of tone
transmission and remains at this level until
the end of hold·over time. It is also active
HIGH during flash and flash hold·over time.

6-15

After CE has risen to VDD. the oscillator starts
running and the Read Address Counter (RAC)
is set to the first address (Figure 3). By
entering the first valid digit, the Temporary
Write Address Counter (TW AC) will be set to
the first address, the decoded digit will be
stored in the register and the TWAC incre·
mented to the next address. Any subsequent
keyboard entry will be decoded and stored in
the redial register after validation. The first 5
valid entries have no effect on the main
register and its associated write address
counter. After the sixth valid digit is entered,
TWAC indicates an overflow condition. The
data from the temporary register will be
copied into the 5 least significant places of
the main register and TWAC into the WAC. All
following digits (including the sixth digit) will
be stored in the main register (a total of not
more than 23). If more than 23 digits are
entered, redial will be inhibited. If not more
than 5 digits are entered, only the temporary
register and the associated TWAC are affect·
ed. All entries are debounced on both the
leading and trailing edges for at least time tE
as shown in Figure 7. Each entry is tested for
validity before being deposited in the redial
register.
• In DTMF mode all non·function keys
are valid
• In PO mode only numeric keys are valid
Simultaneous to their acceptance and carre·
sponding to the selected mode (PD, DTMF,
or mixed), the entries are transmitted as PD
pulse trains or as DTMF frequencies in accor·
dance with postal requirements. Non·numeric
entries are neglected during pulse dialing;
they are neither stored nor transmitted.

Redialing
After CE has risen to VDD, the oscillator starts
running and the Read Address Counter (RAC)
is set to the first address to be sent. The
PCD3310 is in the conversation mode.
If "R" is the first keyboard entry, the circuit
starts redialing the contents of the temporary
register. If the overflow flag of the TW AC was

I

Signetics linear Products

Product Specification

Pulse and DTMF Dialer With Redial

set in the previous dialing, the redialing continues in the main register. If the flag was not
set, the number residing in the temporary
register will only be redialed until the temporary read and write registers are equal.
Before pressing "R," a dialing sequence with
up to 4 digits is possible. If the digits are equal
to the corresponding ones in the main register, then redial starts in the main register until
the last digit stored is transmitted.
Timing in the DTMF mode is calibrated for
both tone bursts and pauses.

PCD3310

In mixed mode, only the first part entered (the
pulse dialed part of the stored number) can
be redialed.
During redial, keyboard entries (function or
non-function) are not accepted until the circuit returns to the conversation mode after
completion of redialing.
No redial activity takes place if one of the
following events occurs:
• Power on reset
• Memory clear ("P" without successive
data entry)
• Memory overflow (more than 23 valid
data entries)

Notepad
The redial register can also be used as a
notepad. In conversation mode, a number
with up to 23 digits can be entered and stored
for redialing. By activating the program key
(P) the WAC and TWAC pointers are reset.
This acts like a memory clear (redial is
inhibited). Afterwards, by entering and storing
any digits. redialing will be possible after flash
or hook on and off.
During notepad programming, the numbers
entered will neither be transmitted nor is the
mute active; only the confidence tone is
generated.

ADDRESSED THROUGH
POINTERS W OR R

ADDRESSED THROUGH
TEMPORARV POINTERS W OR R

MAIN REGISTER

WRITE ADDRESS COUNTER (WAC)

READ ADDRESS COUNTER (RAC)

TEMPORARV REGISTER

I

TEMPDRARV WRITE ADDRESS
COUNTER (TWAC)

:==============:

L
_ _ _ _ _ _ _ _..I

TEMPORARV ADDRESS COUNTER

ADDRESS COUNTER

Figure 3. Program Memory Map

December 2, 1986

I

6-16

Signetics Linear Products

Product Specification

PCD3310

Pulse and DTMF Dialer With Redial

PUBLIC EXCHANGE
DIAL

REDIAL

•

--

CONVERSATION
MODE

STANDBY
MODE

PULSE OR
TONE OUT

Figure 4a. Public Exchange PD/DTMF Mode

•

December 2, 1986

6-17

Signetics Linear Products

Product Specification

Pulse and DTMF Dialer With Redial

PCD3310

PABX
, . - - - - - I F INTERNAL NUMBER .. 5 DIGITS - - - - - ,
DIAL EXTERNAL NUMBER

REDIAL EXTERNAL NUMBER (1)

DIAL INTERNAL NUMBER

REDIAL INTERNAL NUMBER

NOTE:
1. If [access digit(s)

+ external number] < 23 digits.

Figure 4b. PABX PD/DTMF Mode

December 2, 1986

6-18

Signetics Linear Products

Product Specification

Pulse and DTMF Dialer With Redial

PCD3310

DIAL

L----r:===~_

PULSE DIALING

SET IN PULSE DfAUNG

PULSEQUT

r---+------

AUTOMATIC SWITCH TO DTMF OR MANUAL BY

DTMF DIALING
TONE-OUT

REDIAL

PULSE DIALING

4627530
IF TOTAL
(PO + DTMF)
:=> 23 DIGITS

PULSE OUT

Figure 5. PD/DTMF Mixed-Mode Dialing

December 2, 1986

6-19

G

Signetics Linear Products

Product Specification

PCD3310

Pulse and DTMF Dialer With Redial

NOTE PAD PROGRAM

NO DIALING - NO MUTING

MEMORY CLEAR

FLASH

NO
REDIALING

REDIAL
(SEE PABX PROCEDURE)

Figure 6. Notepad/Memory Clear, Flash; Independent of Dialing Mode

December 2, 1986

6-20

Signetics Linear Products

Product Specification

Pulse and DTMF Dialer With Redial

KEYBOARD
ENTRY

PCD3310

-+----'

Ml

M2

DPIFLO

---_I_--

/ 4 - - . - - + - / 4 - - - - - - - - - - , D l A L I N G M O D E - - - - - - - - - - - ; *__

CONVERSATION
MODE

DTMF--- - - - - - - - - -

STATIC
STANDBY
MODE

_________________ _

Figure 7a. Timing Diagram for Dialing Mode Defined by PD/DTMF Selection Pin; Pulse Dialing (PD/DTMF = VSS )

CEJ

KEYBOARD
ENTRY

,I
----!

Ml

M2

e

----.;1
DTMF

DPIFLO

;-1_ _-,

;--1-r.----+------

VNNJ

Figure 7b. Timing Diagram for Dialing Mode Defined by PD/DTMF Selection Pin; DTMF Dialing (PD/DTMF

December 2. 1986

6-21

= VDD)

Signetics Linear Products

Product Specification

Pulse and DTMF Dialer With Redial

KEYBOARD
ENTRY

PCD3310

I

------l~.

DPIFLO

DTMF

M1

M2

PDIDTMF
PULSE DIALING ...t-----jf----l..
~ OTMF DIALING

Figure 7c. Timing Diagram for Dialing Mode Defined by PD/DTMF Selection Pin; Pulse Dialing (Mixed Mode)

CE

--.J

KEYBOARD
ENTRY _ _ _ _----!

R

M1 _ _ _ _ _~

DIAL TONE

DTMF

Figure 8. Timing Diagram Showing REDIAL Where PABX Access Digits are the First Keyboard Entries;
DTMF Dialing With PD/DTMF = Voo

I

VDD
PCD3310

>1",F

TONE

Voo

I

~I

~~

10k

LD06940S

Figure 9. Tone Output Test Circuit

December 2, 1986

6-22

Signetics Linear Products

Product Specification

Pulse and DTMF Dialer With Redial

PCD3310

'z,'· ... M

,..()..,

'Z,'· ... M

"13

l_

+

A8YJAETRlCAl I4OH-IlFEDANCE NtUTB FOR
ELEcntET IICROPHQtrE8 (TEA1011)

1~

TO Vas

'--1

I

DYNAIE Ate) IlACIt£TlC 1KROPttDIIE8 (1'!A1010)

+'--' +-

:
I

8v.ETRICAL LOW·IlPEDANCE IrPUT8 FOR

+'-" +

~

10j.lF
lOY

S1l

r==:-+-----,

~::

IOnf
1%

..
Uk

H*,...-l--"CE=-!18
BAStl

014
(')

13
DTMF
17
AGe

16

"Vee

14

11

AlB

10

"
11

TONE.
10k 110nF

l00nF

e

~.--~----~----~

tOO}o'F 2.2nF
lOY

100nF

TO

ROWS

Vee
PCD3310

410k

..

'"

1l0k

D.
FLO 16

410k

11ZX79/Cl0
410k

10M

NOTES,
1. Automatic line compenstion obtained by connecting A6 to Vss.
2. The value of resistor R14 is determined by the required level at LN and the DTMF gain of the TEA1060.

Figure 10. Application Diagram of the Full Electronic Basic Telephone Set

December 2, 1986

6-23

ROWI

8 ROW3
7 ROW4

' ....F

UNE

I:
5

10

"

ISa"/DTMF
SEt.ECTPIN

7

3 A.
8 8

8 9 C
0 # D

P FL R

>

Signetics

PCD3311/12
DTMF/Modem/Musical-Toner
Generators
Product Specification

Linear Products

PIN CONFIGURATIONS

DESCRIPTION

FEATURES

The PCD3311 and PCD3312 are singlechip silicon gate CMOS integrated circuits. They are intended to provide dualtone multi-frequency (DTMF) combinations required for tone dialing systems in
telephone sets which contain a microcontroller for the control functions.

• Stabilized output voltage level
• Low output distortion with onchip filtering (CEPT CS203
compatible)
• Latched inputs for data bus
applications
• 12C bus compatible
• Mode select input (selection of
parallel or serial data input)
• MODEM and melody tone
generators

The various audio output frequencies
are generated from an on-chip 3.58MHz
quartz crystal-controlled oscillator.
The devices can interface directly to all
standard microcontrollers by accepting a
binary-coded parallel input or serial data
input (1 2C bus).
With their on-chip voltage reference the
PCD3311 and PCD3312 provide constant output amplitudes which are independent of the operating supply voltage
and ambient temperature.

N Package

TOP VIEW

D, N Packages

APPLICATION
• Microcontrolled telephone sets

An on-chip filtering system assures a
very low total harmonic distortion in
accordance with the CEPT CS203 recommendations.

TOP VIEW

In addition to the standard DTMF frequencies, the devices provide 12 MODEM frequencies (300 to 1200 bits per
second) used in simplex MODEM applications and two octaves of musical
scale in steps of semitones.

ORDERING INFORMATION
TEMPERATURE RANGE

ORDER CODE

14-Pin Plastic DIP (SOT-27k, M, T)

-25'C to + 70'C

PCD3311PN

16-Pin Plastic SO (SO-16L; SOT-162A)

-25'C to + 70'C

PCD3311TD

8-Pin Plastic DIP (SOT-97A)

-25'C to + 70'C

PCD3312PN

8-Pin Plastic SO (VSO-8; SOT-176)

-25'C to + 70'C

PCD3312TD

DESCRIPTION

December 2, 1986

6-24

853-1033 86700

Signetics Linear Products

Product Specification

PCD3311/12

DTMF/Modem/Musical-Toner Generators

BLOCK DIAGRAM
OSCI

osco

MODE

0,
12

(14)

11

(12)

10

(11)

0,
0,

°1 /SDA
Do /SCl

STROBE

SWITCHED-

INPUT

0,

CAPACITOR
LOW-PASS
FILTER

CONTROL
LOGIC

9

(10)

8

(9)

I

(6)

5

RESISTORI

~~~~:~ 1-_+-6(;...7:0) TONE
FILTER

TONE GENERATOR
PCD3311
PC03312

7(8)

NOTE'
The pin numbers in parentheses refer to the PCD3311 TO; Pins 5 and 13 are NC.

ABSOLUTE MAXIMUM RATINGS
LIMITS
PARAMETER

SYMBOL

UNIT
Min

Max

VDD

Supply voltage range

-0.8

+8.0

VI

Input voltage range (any input)

-0.8

VDD + 0.8

V

±II

DC input current (any input)

10

mA
mA

V

±Io

DC output current (any output)

10

±IDD; ± Iss

Supply current

50

mA

Po

Power dissipation per output

50

mW

300

mW

PTOT

Total power dissipation per package

TA

Operating ambient temperature range

-25

+70

·C

TSTG

Storage temperature range

-65

+150

·C

December 2, 1986

6·25

•

Signetics Linear Products

Product Specification

DTMF/Modem/Musical-Toner Generators

DC AND AC ELECTRICAL CHARACTERISTICS

PCD3311/12

VDD = 2.5 to 6V; vss = OV; crystal parameters: fosc = 3.579 545MHz,
Rs MAX = 50n; TA = -25°C to + 70°C, unless otherwise specified.
LIMITS

SYMBOL

PARAMETER

UNIT
Min

VDD

Operating supply voltage

IDD
IDD
IOD

Operating supply current 1 oscillator ON; VDD
no output tone
single output tone
dual output tone

IDDO

Static standby current 1
oscillator OFF

Typ

2.5

Max
6.0

V

100
1.0
1.2

p.A
rnA
rnA

3

p.A

= 3V
50
0.5
0.6

Inputs/outputs (SDA)
Do to D5; MODE; STROBE
Vil

Input voltage LOW

VIH

Input voltage HIGH

0

0.3 X VDD

0.7 X VDD

V

VDD

V

300

nA

100

kHz

D2 to D5; MODE; STROBE; Ao
-Ill

PUll-down input current, VI

= VDD

30

150

SCL (Do); SDA (D,)
10l

Output current LOW (SDA), VOL = O.4V

fSCl

Clock frequency (see Figure 7)

rnA

3

= Vss

CI

Input capacitance; VI

tl

Allowable input spike pulse width

7

pF

100

ns

205
160

mV
mV

2.35

dB

TONE output (See Figure 11)
VHG(RMS)
VlG(RMS)

DTMF output voltage levels (RMS values)
HIGH group
LOW group

VDc

DC voltage level

f;.VG

Pre-emphasis of group

THO
THO

Total harmonic distortion, T A = 25°C
dual tone 2
modem tone3

-25
-29

IZol

Output impedance

0.1

158
125

192
150

h
1.85

V

Voo

2.10

dB
dB
0.5

kn

VDD-VSS

V

OSCI input
Vosc(p.P)
Timing (VDD

Maximum allowable amplitude at OSCI

= 3V)

tOSC(ON)

Oscillator start-up time

tTONE(ON)

TONE start-up time 4

tSTR

STROBE pulse width 5

400

ns

tDS

Data setup time 5

150

ns

tDH

Data hold time 5

100

ns

3

ms

0.5

ms

NOTES:
1.
2.
3.
4.
5.

Crystal is connected between ascI and oseo; Do/Sel and D 1 /SDA via a resistance of 5.6kn to VDD; all other pins left open.
Related to the level of the lOW group frequency component (CEPT CS203).
Related to the level of the fundamental frequency.
Oscillator must be running.
Values are referenced to the 10% and 90% levels of the relevant pulse amplitudes, with a total voltage swing from Vss to VOD.

December 2, 1986

6-26

Signetics Linear Products

Product Specification

DTMF/Modem/Musical-Toner Generators

FUNCTIONAL DESCRIPTION
Clock/Oscillator (OSCI and
OSCO)
The timebase for the PCD3311 and PCD3312
is a crystal-controlled oscillator with a
3.5BMHz quartz crystal connected between
OSCI and OSCO. Alternatively, the OSCI
input can be driven from an external clock.

Table 1_ Ds and D4 in Accordance With the Selected Application
D5

D4

0
0
1
1

0
1
0
1

APPLICATION

DTMF single tones; standby; melody tones
DTMF dual tones (all 16 combinations)
MODEM tones; standby; melody tones
Melody tones

NOTES:

1 - H - HIGH voltage level
LOW voltage level

Mode Select (MODE)

o- L -

This input selects the data input mode. When
connected to Voo, data can be received in
the parallel mode (only for the PCD3311), or,
when connected to Vss or left open, data can
be received via the serial 12C bus (for both
PCD3311 and PCD3312).

mode) is provided at the TONE output. The
output remains unchanged until the negativegoing edge of the next STROBE pulse (for
new data) is received.

Parallel mode can only be obtained for the
PCD3311 by setting MODE input HIGH.

Data Inputs (Do, D10 D2, D3, D4
and Ds)
Inputs Do and D, have no internal pull-down
or pull-up resistors and must not be left open
in any application. Inputs D2 to D5 have
internal pull-down. D5 and D4 are used to
select between DTMF dual, DTMF single,
MODEM and melody tones (see Table 1). D3
to Do select the combination of the tones for
DTMF or single-tone itself.

Strobe Input (STROBE, only for
the PCD3311)
This input (with internal pull-down) allows the
loading of parallel data into Do to D5 when
MODE is HIGH.
The data inputs must be stable preceding the
positive-going edge of the strobe pulse (active HIGH). Input data are loaded at the
negative-going edge of the strobe pulse and
then the corresponding tone (or standby

December 2, 19B6

PCD3311/12

Serial mode can only be obtained for the
PCD3311 by setting MODE input lOW.

Serial Clock and Data Inputs
(SCl and SDA)
SCl and SDA are combined with Do and D1,
respectively. For the PCD3311, the selection
of SCl and SDA is controlled by the MODE
input. SCl and SDA are serial clock and data
lines according to the 12C bus specification
(see CHARACTERISTICS OF THE 12C BUS).
Both inputs must be pulled-up externally to

voo·
Address Input (Ao)
Ao is the slave address input and it identifies
the device when up to two PCD3311 or
PCD3312 devices are connected to the same
12C bus. In any case, Ao must be connected
to Voo or Vss.

12C Bus Data Configuration (see
Figure 2)
The PCD3311 and PCD3312 are always slave
receivers in the 12C bus configuration (R/iN
bit = 0).

6-27

The slave address consists of 7 bits in the
serial mode for the PCD3311 as well as for
the PCD3312, where the least significant bit is
selectable by hardware on input Ao and the
other more significant bits are internally fixed.
In the serial mode the same input codes are
used as in the parallel mode (see Tables 2, 3,
4, and 5). D6 and D7 are don't care (X) bits.

Tone Output (TONE)
The single and the dual tones which are
provided at the TONE output are filtered by
an on-chip switched-capacitor filter, followed
by an active RC low-pass filter. Therefore, the
total harmonic distortion of the DTMF tones
fulfils the CEPT CS203 recommendations. An
on-chip reference voltage provides outputtone levels independent of the supply voltage. Table 3 shows the frequency tolerance
of the output tones for DTMF signalling;
Tables 4 and 5 for the modem and melody
tones.

Power-On Reset
In order to avoid undefined states of the
devices when the power is switched ON, an
internal reset circuit sets them to the standby
mode (oscillator OFF).

Signetics Linear Products

Product Specification

DTMF/Modem/Musical-Toner Generators

STROBE

PCD3311/12

--:"';;~f

0,

0,

03

0,

0,

r--

tTONE

---+---~----

TONE

OSCILLATOR OFF

OSCILLATOR ON
NO OUTPUT TONE

I

OSCILLATOR ON
OUTPUT TONES

Figure 1. Timing Diagram Showing Control Possibilities of the Oscillator and the TONE Output (e.g., 770Hz + 1477Hz)
in the Parallel Mode (MODE = HIGH)

ACKNOWLEDGE

ACKNOWLEDGE
FROM SLAVE

FROM SLAVE

RiW

MSB

s

D

AD

X

SLAVE ADDRESS

X

05

D4

03

DATA

Figure 2. 12 C Bus Data Format

December 2, 1986

6-28

0201

INTERNAL STROBE
FOR DATA LATCHING

Signetics Linear Products

Product Specification

PCD3311/12

DTMF /Modem/Musical-Toner Generators

Table 2. Input Data for Control (No Output Tone; TONE at VDD)
Os

04

03

02

01

Do

HEX

OSCILLATOR

X
X
X
X

0
0
0
0

0
0
0
0

0
0
0
0

0
0
1
1

0
1
0
1

00/20
01/21
02/22
03/23

ON
OFF
OFF
OFF

NOTES:
1 - H - HIGH voltage level
L - LOW voltage level
X = don't care

o-

Table 3. Input Data for DTMF
Os

04

03

02

01

Do

HEX

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

08
09
OA
OB
OC
00
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
10
1E
1F

SYMBOL

STANDARD
FREQUENCY
(Hz)

TONE
OUTPUT
FREQ. (Hz)l

697
770
852
941
1209
1336
1477
1633
941 + 1336
697+1209
697+1336
697 + 1477
770+1209
770 + 1336
770 + 1477
852 + 1209
852+1336
852 + 1477
697 + 1633
770+1633
852+1633
941 + 1633
941 + 1209
941 + 1477

0
1
2
3
4
5
6
7
8
9
A
B
C
0

.

#

697.90
770.46
850.45
943.23
1206.45
1341.66
1482.21
1638.24

FREQUENCY DEVIATION
%

+0.13
+0.06
-0.18
+0.24
-0.21
+0.42
+0.35
+0.32

Hz

+0.90
+0.46
-1.55
+2.23
-2.55
+5.66
+5.21
+5.24

Table 4. Input Data for MODEM Frequencies

Os

1
1
1
1
1
1
1
1
1
1
1
1

04

0
0
0
0
0
0
0
0
0
0
0
0

03

0
0
0
0
1
1
1
1
1
1
1
1

02

1
1
1
1
0
0
0
0
1
1
1
1

01

0
0
1
1
0
0
1
1
0
0
1
1

Do

0
1
0
1
0
1
0
1
0
1
0
1

HEX

24
25
26
27
28
29
2A
2B
2C
20
2E
2F

STANDARD
FREQUENCY (Hz)

1300
2100
1200
2200
980
1180
1070
1270
1650
1850
2025
2225

NOTES:
1.Tone output frequency when using a 3.579 545MHz crystal.
1 - H - HIGH voltage level
o = L = LOW voltage level

December 2, 1986

6-29

TONE
OUTPUT
FREQ. (Hz)l

1296.94
2103.14
1197.17
2192.01
978.82
1179.03
1073.33
1265.30
1655.66
1852.77
2021.20
2223.32

FREQUENCY
DEVIATION

%

Hz

-0.24
+0.15
-0.24
-0.36
-0.12
-0.08
+0.31
-0.37
+0.34
+0.15
-0.19
-0.08

-3.06
+3.14
-2.83
-7.99
-1.18
-0.97
+3.33
-4.70
+5.66
+2.77
-3.80
-1.68

REMARKS

V.23
Bell 202
V.21
Bell 103
V.21
Bell 103

Signetics Linear Products

Product Specification

PCD3311/12

DTMF/Modem/Musical-Toner Generators

Table 5. Input Data for Melody Tones
05

04

03

02

01

Do

HEX

NOTE

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
0
1
1
0
0

1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
0
1
0
0
0
0
0
0

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
0

0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
0
0
0
1
1
1

0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
0
1
0
1
1
1
0
1

30
31
32
33
34
35
36
37
38
39
3A
29
36
3C
3D
OE
3E
2C
3F
04
05
25
2F
06
07

D#5
E5
F5
F#5
G5
G#5
A5
A#5
65
C6
C#6
D6
D#6
E6
F6
F#6
G6
G#6
A6
A#6
66
C7
C#7
D7
D#7

STANDARD
FREQUENCY (Hz)1

622.3
659.3
698.5
740.0
784.0
830.6
880.0
932.3
987.8
1046.5
1108.7
1174.7
1244.5
1318.5
1396.9
1480.0
1568.0
1661.2
1760.0
1864.7
1975.5
2093.0
2217.5
2349.3
2489.0

TONE OUTPUT
FREQUENCY (Hz)2

622.5
659.5
697.9
741.1
782.1
832.3
879.3
931.9
985.0
1044.5
1111.7
1179.0
1245.1
1318.9
1402.1
1482.2
1572.0
1655.7
1768.5
1875.1
1970.0
2103.1
2223.3
2358.1
2470.4

NOTES:

1. Standard scale based on A4 ~ 440Hz.
2. Tone output frequency when using a 3.579 545MHz crystal.
1 ~ H ~ HIGH voltage level
o ~ L ~ LOW voltage level

CHARACTERISTICS OF THE 12C
BUS
The 12 C bus is for 2-way. 2-line communication between different ICs or modules. The
two lines are a serial data line (SDA) and a
serial clock line (SCl). 60th lines must be
connected to a positive supply via a pull-up
resistor when connected to the output stages
of a device. Data transfer may be initiated
only when the bus is not busy.

i rr:::~
seL~---"--

SOA

1

!
I

I
I
:

I

DATA LINE
STABLE:
DATA VALID

I

I CHANGE I
I OF DATA I
: ALLOWED, :

Figure 3. Bit Transfer

Bit Transfer
One data bit is transferred during each clock
pulse. The data on the SDA line must remain
stable during the HIGH period of the clock
pulse, as changes in the data line at this time
will be interpreted as control signals.

--~-:
SOA

is defined as the start condition (S). A lOWto-HIGH transition of the data line while the
clock is HIGH is defined as the stop condition

Start and Stop Conditions
60th data and clock lines remain HIGH when
the bus is not busy. A HIGH-to-lOW transition of the data line, while the clock is HIGH,

r=-_-_~

(P).

:--;.t---

i \.....:___.J.L--_______
..Jio.
\.-----t:...I1 i
I
I

I
I

I

I

...JI

sel --

- - \... _ _
L ___ J

I
I

! i
p

I

STOP CONDITION

Figure 4. Definition of Start and Stop Conditions
December 2, 1986

1

L ___ ...l

START CONDITION

6-30

SOA

I
I

seL

Signetics Linear Products

Product Specification

DTMF/Modem/Musical-Toner Generators

System Configuration
A device generating a message is a "transmitter"; a device receiving a message is the
"receiver". The device that controls the message is the" master" and the devices which
are controlled by the master are the
"slaves".

Acknowledge
The number of data bytes transferred between the start and stop conditions from
transmitter to receiver is not limited. Each

PCD3311/12

byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level
put on the bus by the transmitter, whereas the
master generates an extra acknowledge related clock pulse. A slave receiver which is
addressed must generate an acknowledge
after the reception of each byte. Also, a
master must generate an acknowledge after
the reception of each byte that has been
clocked out of the slave transmitter. The
device that acknowledges has to pull down

the SDA line during the acknowledge clock
pulse; so that the SDA line is stable LOW
during the HIGH period of the acknowledge
related clock pulse, setup and hold times
must be taken into account. A master receiver must Signal an end of data to the transmitter by not generating an acknowledge on the
last byte that has been clocked out of the
slave. In this event the transmitter must leave
the data line HIGH to enable the master to
generate to stop condition.

SDA------~----------~----------~----------~----------~---

~L--~--4_------~~~----~~_+------~--+_~----._~~-

Figure 5. System Configuration

CLOCK PULSE FOR
ACKNOWLEDGEMENT

START
CONDITION

I
I
sel FROM
MASTER

--~

I

I
I

I
I

DATA OUTPUT
BY TRANSMITTER

""1 I
I
S

X'--_)(~~)(_.-J7

DATA OUTPUT

BY RECEIVER

Figure 6. Acknowledgment on the 12C Bus

December 2, 1986

6-31

I

II

Signetics Linear Products

Product Specification

DTMF jModemjMusical-Toner Generators

Timing Specifications
Within the 12C bus specifications, a highspeed mode and a low-speed mode are
defined. The ICs operate in both modes, and
the timing requirements are as follows:

PCD3311j12

High-Speed Mode
Masters generate a bus clock with a maximum frequency of 100kHz. Detailed timing is
shown in Figure 7.

SDA

SCL

SDA

Where:

teuF

t~tLOwmin

tHO; ISTA

t;;;..tHIGHmin

tLOWmin

4.71JS

IH1GHmin

'''''

tsu; ISlA
tHO; IOAT
tsu; IOAT

t;;;..tLOwmin
t~O/.lS
t~250ns
t~1J.lS

'R

'tsu;tsro
F

t ";;;;300n5
t#ILOWmin

The minimum time the bus must be free before a new transmission can start
Start condition hold time
Clock LOW period
Clock HIGH period
Start condition setup time, only valid for repeated start code
Data hold time
Data setup time
Rise time of both the SDA and Sel line
Fall time of both the $DA and Sel line
Stop condition setup time

NOTE,
All the timing values refer to VIH and V1L levels with a voltage swing of Vss, to Voo-

Figure 7. Timing of the High-Speed Mode

SDA

I
\
\J -\.....J::7\..-~-~
'--'I
\._,
\._"

L-.J
I----....--J L....-.....J l.....---J
START
ADDRESS
Rm
ACK
CONDITION

'---D"'-~-A--~l ~

S~T ~ ~ ~
CONDITION

Where:
Clock tLOWmin
4.711S
tHIGH min
4 fJ.s
The dashed Une is the acknowledgment of the receiver
Mark-to-space ratio
1 : 1 (LOW-to-HIGH)
Maximum number of bytes
unrestricted
allowed by generation of STOP condition
Premature termination of transfer
Acknowledge clock bit
must be provided by the master

Figure 8. Complete Data Transfer in the High-Speed Mode

December 2, 1986

6-32

~

Signetics Linear Products

Product Specification

DTMF/Modem/Musical-Toner Generators

Low-Speed Mode
Masters generate a bus clock with a maximum frequency of 2kHz; a minimum LOW

PCD3311/12

period of 105/ls and a minimum HIGH period
of 3651's. The mark-Io-space ralio is 1:3

LOW-Io-HIGH. Delailed liming is shown in
Figure 9.

SOA

'F
SCL
~-----tHIGH-----I~

SOA

Where:
tauF

t ~ 105ps (tLOWmin)
t ~ 3651-15 (tHIGHmin)
130pS±25}1S

tHO; STA
tLOW

tsu: STA

390J.tS±25ps
130ps ± 2S.us2

tHO; OAT

t;;;'

tHIGH

tsu;

Ops
t;;;' 250n5

OAT

t<

IR
IF

l,us

t < 300ns
130/lS±25/1S

tsu; 510

NOTES:
1. AJI the timing values refer to V1H and VIL levels with a voltage swing of Vss to VDD. For definitions see high-speed mode.

2. Only valid for repeated start code.

Figure 9_ Timing of the Low-Speed Mode
I

SOA \

1 . . - ._ _ _ _

_

\ r

.JJ

--V\I\/

SCL~-~

LI_ _ _ _ _ _ _ _ _ _ _ _ _

START
CONDITION

START BYTE

II

==-:X_R/W~X

~L-

___

~

DUMMY
ACKNOWLEDGE

~

REPEATED
START
CONDITION

~--------~"
ADDRESS

ACKNOWLEDGE

~

STOP
CONDITION

Where:

Clock tLOWmin
tHJGHmin

Mark-ta-space ratio

Start byte
Maximum number of bytes
Premature termination of transfer
Acknowledge clock bit

130p.s± 25p.s
390p.s± 25p.s
,,3 (LOW-Io-HIGH)

0000 0001
6
not allowed
must be provided by master

NOTES:
The general characteristics and detailed specification of the 12C bus are described in a separate data sheet (serial data buses) in handbook, "Ies for Digital Systems in Radio,
Audio and Video Equipment".

Figure 10_ Complete Data Transfer in the Low-Speed Mode

December 2, 1986

6-33

Signetics Linear Products

Product Specification

PCD3311/12

DTMF/Modem/Musical-Toner Generators

1.6

TA = -25'C ....
1.2

b..

/

10k

~

~

V

+25'C/
+70'C/

0.4

Figure 12. Standby Supply Current as a
Function 01 Supply Voltage; Oscillator OFF

Figure 11. TONE Output Test Circuit

300

1.5

-2~'C

TA 1=

+2~'C,

+70"C
200

J-2~'C,

TA

~~

+25:C,
+70'C,

J~

......::

0.5

~~

~ IP'"

o
o

~~

~~

/. W

100

/

~ "?

~~

0

4
Voo (V)

4
VDD (V)

Figure 13. Operating Supply Current as a Function 01
Supply Voltage; Oscillator ON; No Output at TONE

Figure 14. Operating Supply Current as a Function 01
Supply Voltage; Oscillator ON; Dual-Tone at TONE

-11

TA=~

/~

V;io'c
/K
V
/I

-

--=: r-- -.......

J

,If!

-14

~~~:g- ~GR~UP

°iC

+7
-~

--r--=t::::::

0

v, (V)

VDD (V)

Figure 15. Pull-Down Input Current as a Function 01 Input
Voltage; VDD = 3V

December 2. 1986

HldH GRdup

+2S"C

+70'C-

iE. -13

J

o
o

T~ = -25'C

-12

Figure 16. DTMF Output Voltage Levels as a Function 01
Operating Supply Voltage; RL = lMn

6-34

Signetics Linear Products

Product Specification

PCD3311/12

DTMF/Modem/Musical-Toner Generators

0.4

!

It

-20

.=

r"'"

-2S'C

lirt

r--..

-0.4

.-

lin

-0.8

.0"

.0'

-80

III
.04

J.J
\/IJII

.0"

Y 'Y

II

'\
r-

J

CS203

-.-

.A

h

V I\A/\I
IH

AA A
~\ ' \AII , AI

!

fir

"1.

A,

r

1'\ II AI
'V ~ IV' \I V'I;Jr" 'W'{1 W ~" ~vT
1\ In I

-'00 o
FREQUENCY (kHz)

Figure 17. Dual-Tone Output Voltage
Level as a Function of Output Load
Resistance

Figure 18. Typical Frequency Spectrum of a Dual-Tone Signal After Flat-Band
Amplification of 6dB

MUTE
GENERAL
PURPOSE
MICROCONTROLLER
(4- OR 1I-81T)

STROBE

DATA BUS

Do
PCD33"

TONE

0,

II

II
Figure 19. PCD3311 Driven by a Microcontroller With Parallel Data Bus

December 2, 1986

6-35

Signetics Linear Products

Product Specification

DTMF/Modem/Musical-Toner Generators

PCD3311/12

MUTE
TELEPHONY
MICROCONTROLLER
PCD3343

TONE

II

II
NOTE:

The PCD3343 is a single-chip 8·bit microcontroller with 3k ROM/224 RAM bytes.
The same application is possible with the PCD3811 with MODE = Vss.

Figure 20. PCD3312 Driven by Telephony Mlcrocontrolier PCD3343 With Serial I/O (1 2C Bus)

December 2, 1986

6·36

PCD3315

Signetics

CMOS Redial and Repertory
Dialer
Product Specification

Linear Products
DESCRIPTION
The PCD3315 is a single-chip CMOS
dialer IC for telephone sets. It has two
dialing modes: pulse dialing (PD), and
dual-tone multi-frequency (DTMF) when
used in conjunction with tone generator
PCD3312. In addition to manual dialing,
it also features several automatic functions, such as redial, extended redial,
note-pad, and repertory dial.

FEATURES
• Pulse dialing
• DTMF dial control of tone
generator PCD3312
•
•
•
•
•

Redial
Extended redial
Electronic notepad
Ten repertory dial numbers
18-digit capacity for each
autodial memory

• 12 C compatible
• Maximum of 36 digits per call
• Flash or register recall

• Uses standard 4 X 4 keyboard
(single- or double-contact)
• Four extra function keys:
program/autodial, flash, redial,
access pause
• Access pause generation and
termination
• Automatic PABX-diglt recognition
resulting in an access pause
insertion
• Hold input and access pause
output (APO) to adjust the
duration of the access pause
and facilitate use of tone
recognizers
• Four diode or strap functions:
general/German, access pause
time, reset delay time, general:
mark-space ratio/German:
prepulse
• Manual reset of autodlal RAM
• On-chip power-on reset
• Programmed for improved noise
immunity

• Feature phones

ORDERING INFORMATION
DESCRIPTION

28-Pin Plastic SO package
(SO-28; SOT-136A)

January 14, 1987

TEMPERATURE RANGE

'ORDER CODE

- 25°C to + 70°C

PCD3315PN

- 25°C to + 70°C

PCD3315TD

6-37

N, D Packages

TOP VIEW
DESCRIPTION
PIN NO. SYMBOL
Ie
Internally connected
Ie
Internally connected
Internally connected
Ie

9
10
11
12
13

APPLICATION

28-Pin Plastic DIP (SOT-117D)

PIN CONFIGURATIONS

14
15
16
17
19
19
20
21
22
23
24
25
26
27
28

ROW 2
1l
ROW
ROW 3
ROW 4
ROW 5
DIODE
APO

RND

Scanning row keyboard outputs

Diode option output
Access*pause output
Hold input
Chip-enable input

CE
PO/DTMF Input to select pulse or DTMF
Vss
XTAL1j
XTAL2
RESET

COL
1)
COL 2
COL 3
COL 4
DP/FL
M1
SDA
SeL
Ie
Ie
Voo

dialing
Negative supply
Crystal pins
Reset input/output
Sense column keyboard inputs

Dialing pulse and flash output
Muting output
Serial data
Serial clock
lnternal1y connected
lnternal1y connected
Positive supply

853-1146 87202

..
!
I

Signetics Linear Products

Product Specification

CMOS Redial and Repertory Dialer

PCD3315

BLOCK DIAGRAM OF FEATURE PHONE

...

...

Vss

600

""

KEYBOARD

LN
HOOK

-4

~>-

LINE

Vee

MD-

Voo

CE

~

MUTE

-

TEA1060

PC03315

~MF

TtJ-

I--

m~
V..

PO

3.58 MHz

V••

~

INTERRUPTER

W

DP/FLASH
SCL

YJ;,;-

SDA

OSCI

PCD3312

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

VDD

Supply voltage (Pin 28)

VI

All input voltages

± 110 ± 10

DC current into any input or output

RATING

UNIT

-0.8 to +8

V

0.8 to Voo + 0.8

V

10

rnA

500

mW

50

mW

PTOT

Total power dissipation

Po

Power dissipation per output

TSTG

Storage temperature range

-65 to +150

·C

TA

Operating ambient temperature range

-25 to +70

·C

TJ

Operating junction temperature

125

·C

OJA

Thermal resistance uunction-to-ambient)
for SOT-117D
for SOT-136A

120
150

·C/W
·C/W

January 14, 1987

6-38

1

2

3

4

5

6

B

7

8

9

C

0

#

0

PL

R

AP

P

A

IIII
-

Ww

~~

5;i
,",w
H
:E

?<
....
w
Q
t-

w
w

If>
II:

:!::=

Product Specification

Signetics Linear Products

CMOS Redial and Repertory Dialer

DC ELECTRICAL CHARACTERISTICS

PCD3315

VDD = 2.5 to 6V; Vss = OV; TA = -25 to + 70°C; all voltages with respect to Vss;
I = 3.58MHz with Rs = 50.11, unless otherwise specilied.

LIMITS
SYMBOL

UNIT

PARAMETER
Min

VDD
VDD

100
100
100
100
100

Supply voltage
operating
STOP mode lor RAM retention 1

Typ

2.5
1.0

Supply current
dialing mode
at Voo = 3V
conversation mode
at VD D =3V
STOP mode2
at Voo = 1.8V; TA = 25°C
at VO D = 1.8V; TA = 55°C
at Voo = 1.8V; TA = 70°C

Max
6
6

500

Jl.A

Ji.A

270
1.2

V
V

2.5
5
10

Jl.A
Jl.A

Ji.A

RESET I/O
VRESET

Switching level

10L

Sink current at Voo

1.2

> VRESET

1.5

7

V
Jl.A

Inputs
VIL

Input voltage lOW

0

0.3Voo

V

VIH

Input voltage HIGH

0.7VOD

VDO

V

± IlL

Input leakage current at Vss

1

Jl.A

< VI < VDD

Outputs
VOL

Output voltage lOW at VI = Vss or VOD; 110 I < 1Jl.A

10L

Output sink current lOW at VDD = 3V; Vo = O.4V

0.6

-IOH
-IOH

Pull-up output source current HIGH (except SOA, SCl)
at Voo = 3V; Vo = 0.9VDO
at Voo = 3V; Vo = Vss

10

0.05
1.5

NOTES:
1. Because RAM is cleared if POR is activated by software, this value must be max. VAESET.

2. Crystal connected between XTALI and XTAL2; SCl and SOA pulled to Voo via S.6k!'! resistor; CE and PD/OTMF at Vss.

January 14, 1987

6-39

V
mA

200

Jl.A
Jl.A

Signetics Linear Products

Product Specification

CMOS Redial and Repertory Dialer

FUNCTIONAL DESCRIPTION

Dialing Pulse and Flash Output
(DP/Fl)

Power Supply (VDD; VSS)
The minimum supply voltage and supply current depend on the operating modes:
• Standby
• Conversation
• Dialing

This output drives the line interrupter circuit.
In pulse dialing mode, it controls the timing for
the line interrupter. This output also provides
a "Flash" pulse which generates a 95ms line
break. In the German version, this "Flash"
occurs only in the DTMF dialing mode.

(see Operational Description)

Chip Enable Input (CE)

Oscillator (XTAl1; XTAl2)

The CE input is used for hook-detection.
Hook-off will result in CE = HIGH. This will
change the circuit state from standby to
operational mode and also initialize the circuit.
When the circuit detects a line break longer
than the reset delay time, it will switch the IC
to the standby mode. This essentially
achieves a low standby current during hookon. During access pauses, the reset delay
time is longer because the telephone line
supply is switched over, which may result in
longer line drops.

The timebase for the PCD3315 is a crystalcontrolled oscillator with a 3.58MHz quartz
crystal connected between XTAL1 and
XTAl2. The oscillator will run when the
CE = HIGH. The output XTAl2 can drive the
oscillator input of the PCD3312 via a capacitor.

Keyboard Inputs/Outputs (COL
1 to 4; ROW 1 to 5)
The sense column COL 1 to COL 4 and the
scanning row outputs ROW 1· to ROW 4 are
directly connected to a 4 x 4 single-contact
keyboard matrix. An extra row (ROW 5) is
added to address four additional function
keys that are required for autodial functions.
The keyboard organization is shown in Figure
1. Keyboard entries are valid 20ms (debounce time) after the leading edge and until
20ms after the trailing edge of the keyboard
entry.
In pulse dialing mode, the valid keys are the
10 numeric keys (0 to 9). The 6 non-numeric
keys (A, B, C, D, " #) have no effect on the
dialing and are ignored.
In DTMF dialing mode, the 10 numeric keys
and the 6 non-numeric keys are valid.

Diode Option Output (DIODE)
An extra row is added to the keyboard matrix
to provide several selections:
• Access pause duration
• Reset delay time
• Mark/space ratio or prepulse yes/no
• General or German version
ROWS

5

4

3

1

1

L~
'--

2

3

Serial Data (SDA); Serial Clock
(SCl)
The serial 1/0 lines SDA and SCl are used to
control the PCD3312 in the DTMF dialing
mode (see Figure 4). Both outputs require
external pull-up resistors.

Dialing Mode Selection Input
(PD/DTMF)
This input selects the dialing mode:
• PD/DTMF = lOW selects pulse dialing
• PD/DTMF = HIGH selects DTMF dialing

Reset Input/Output (RESET)
When the reset input is active High, it can be
used to initialize the IC. In normal application,
this is achieved by the CE input. Reset is also
an output of the internal power-on reset
circuit, which generates a reset pulse if Voo
drops below 1.3V (typ.).

OPERATIONAL DESCRIPTION
The PCD3315 has 3 operating modes:
• Standby
• Conversation

• During access pauses; Mute = HIGH
during the mute hold-over time

Standby Mode

• During flash; Mute = HIGH
• During programming

Hold Input (HOLD); Access
Pause Output (APO)
The hold input suspends dialing after completion of the current digit, or in pulse dialing
during the inter-digit pause.
The hold function facilitates an extra time
delay during dialing under the control of
external circuitry, i.e., a dialing tone recognizer.

• Dialing
When the chip enable input (CE) is lOW, the
IC is in the standby mode. The oscillator is
switched off and the IC requires only a
standby current (1.2J.lA typ.) for memory retention.
The circuit will leave the standby mode and
enter the conversation mode O.5ms after CE
becomes High.

Conversation Mode
In this mode, the IC is active in order to scan
the keyboard entries. Mute and dialing pins
are inactive. The current consumption is
270).lA (typ.) at Voo = 3V.

Dialing Mode
The IC will be switched to the fully-operational mode in the following circumstances:
• A valid keyboard entry

4

I I I
2

3

A

4

5

6

B

• Programming mode

7

8

9

C

The current consumption is 500).lA (typ.) at
Voo = 3V.

0

IF

D

FL

R

AP

P

• Dialing mode

DIAUNG
TONE

KEYBOARD
TB03310S

Figure 1. Keyboard Organization
January 14, 1987

controlled by the access pause output (APO)
directly, or indirectly via a dialing tone recognizer (see Figure 2). The APO output will go
lOW when an access pause is recognized.

• In DTMF dialing mode; Mute = HIGH
during DTMF bursts plus hold-over time

In the hold state (HOLD = lOW), the muting
output is also lOW, thus the IC is in the
conversation mode. The HOLD input can be

COLUMNS

2

Mute Output (M1)
This output is active
• In pulse dialing mode; Mute = HIGH
during interdigit pause plus dialing
pulses

PCD3315

Figure 2. Automatic Variation
of Length of an Access Pause
Under the Control of a Dialing
Tone Recognizer

6-40

The PCD3315 has two dialing modes:
• Pulse dialing direct via DPIFl output
• DTMF dialing via PCD3312 using the serial
1/0 lines SDA and SCl

Pulse Dialing
The timing sequence for pulse dialing is
shown in Figure 3a. Output DP/Fl starts with

Product Specification

Signetics Linear Products

CMOS Redial and Repertory Dialer

an inter-digit pause, followed by a sequence
of pulses corresponding to the digit for transmission. The dialing frequency is fixed at
10Hz; the break and make times are 60ms
and 40ms, respectively.
In the general version with diode option, the
user can also select break and make times of
67ms and 33ms, respectively.
The muting pulse will overlap the total dialing
sequence. After dialing, the muting output
(M 1) goes LOW and the circuit is switched to
the conversation mode.
DTMF Dialing
The timing sequence for DTMF dialing is
shown in Figure 3b. The PCD3312 generates
the selected DTMF tones via the serial 1/0
lines SDA and SCL. These tones are transmitted with minimum tone burst durations of
70.70ms (for the German version 80.80ms).
The maximum tone burst duration is equal to
the key depression time.
After dialing, the muting output goes LOW
after a hold-over time of 80ms, and the circuit
is switched to the conversation mode.

Normal Dialing
The IC has a working register with a maximum capacity of 18 positions. Entries in these
positions may be:
• 10 numeric digits 0 to 9
• Manually-programmed access pauses
• 6 non-numeric special keys (*, #, A, B,
C, D) in DTMF mode
If none of the special keys has been pressed,
the contents of the working register will be
stored automatically in the Redial Buffer.
The number of digits can be extended to a
maximum of 36, but this will result in a redial
memory clear after hook-on. This is also valid
for manual dialing after automatic dialing.

In addition to manual dialing, the IC provides
the following automatic functions:
• Redial of the last manually-dialed
number (German version) or
Redial of the last-dialed number
(general version)

There are four ways to terminate an access
pause:
• HOLD, APO pins directly interconnected;
after a fixed time delay of 3 or 5s in
pulse dialing; 1.5 or 2.5s in DTMF
dialing. The fixed time delay is
determined by a diode strap

• Extended redial
• Electronic notepad
• Maximum of 10 repertory dialing
numbers

• HOLD, APO pins interconnected via an
RC network; after a fixed time delay of
3 or 5s in pulse dialing; 1.5 or 2.5s in
DTMF dialing - plus an additional time
delay determined by the RC values

The maximum capacity of the registers for
these numbers is also 18 positions. The 6
non-numeric digits (*, #, A, B, C, D) will not
be stored.

• APO pin enables a dialing tone
recognizer, which controls the HOLD
input (see Figure 2)

Automatic Dialing

During the access pause, the muting output
remains active during hold-over time. In order
to handle longer line drops during access
pauses, the PCD3315 automatically switches
to the maximum reset delay time of 320ms.

• R redial
• AP manual access pause entry
Besides the operational procedure for automatic dialing, there are also procedures for
programming these numbers into the memory
(see Table 1).

The PCD3315 will detect pre-programmed
PABX digits and insert an access pause in the
dialing sequence. The reserved capacity is for
two different PABX numbers with a maximum
of 2 digits each.

Access Pause

There are three ways to enter an access
pause:
• At manual dialing by pressing the AP
key

Table 1_ Keying Procedures for Dial and Program Operation

Where:
P =: Press and
P == Press and
R = Press and
TN =: Telephone

OPERATION

R
P-R
P-R
pod
Automatic
Hook-on
2, 5, 8, 0
Hook-off
2, 5, 8, 0

release P~key
keep P-key pressed
release R-key
number

January 14, 1987

PABX Digits

Program procedure: P - R - d1, d2 R d3 d4'

During a dialing sequence, it may be necessary to insert a wait time to ensure correct
dialing. A dialing sequence can always be
interrupted by the HOLD input through an
access pause recognition, which results in a
fixed time delay.

• Recognition of PABX digits, after which
an automatic access pause will be
inserted

MODE

• HOLD input connected to VDD; no
access pause

To achieve these automatic dialing functions,
an extra row of the keyboard is required
which contains the following special function
keys:
• P programmingl automatic dialing
• FL flash or register recall

• At auto dialing by recognition of the
AP-code in the memory

Redial
Extended redial
Notepad
Repertory dial
PABX digits
Reset autodial
RAM

PCD3315

PROGRAM

Automatic
TN'P
Dial-P-P-TN-P
P-d'TN
P'R-d1 (d2) R d3 (d4)

d ~ Digit 0 to 9
2, 5, 8, 0 ~ Press and keep pressed keys 2, 5, 8, and 0
2, 5, 8, 0 ~ Release keys 2, 5, 8, and 0

6-41

Notepad
In the conversation mode, the notepad procedure will overwrite the extended redial buffer,
without dialing-out digits. After hook-off, this
number can be recalled through the extended
redial buffer.
Store procedure
Dial

P -P -TN P
P-R

Flash (see Figure 3b)
Flash or register recall is activated by the
flash key which results in a timed line break at
output pin DP/FL. This line break is of a fixed
95ms duration in both pulse and DTMF dialing modes. In the German version, it is only
applicable to the DTMF mode.

Product Specification

Signetics Linear Products

CMOS Redial and Repertory Dialer

In the dialing procedure, a flash entry will
initialize the IC and, thus, the working register
which acts like a chip enable procedure.

Memory Clear
A built-in, manual total-memory clear to facilitate resetting of the autodial RAM after servicing, maintenance, or telephone set delivery
exists.
Procedure: hook-on, press, and keep depressed keys 2, 5, 8, 0; hook-off, release keys
2, 5, 8, o.

PCD3315

Program Security

Diode Options

Security measures are incorporated in the IC
to avoid incorrect dialing operations and
hang-ups.
The program has a built-in RAM check procedure to protect the autodial numbers stored in
the RAM. If one or more bits of this RAM are
changed during standby, or the battery falls
below 1.3V (typ.), this will result in a memory
clear to avoid subsequent incorrect dialing.

There are 4 different diode or strap options
which are an extension of the keyboard
matrix. Addressing is via the 4 columns and
diode pins.
There are two possibilities:
• Without diode
• With diode (cathode on row-side)
The built-in selections are shown in Table 2.

Table 2. Diode Option Selections
COLUMN

DESCRIPTION

4
1
1
2
2
3

WITHOUT DIODE

Version
Break, make-time
Prepulse
Access pause
Access pause
Reset delay time

WITH DIODE

German
60, 40ms
No
3s
1.5s
160ms

General
67, 33ms
Yes
5s
2.5s
320ms

REMARKS

General version
German version
Pulse dialing
DTMF dialing

Table 3. Timing Date, General Version
TYP
SYMBOL

PARAMETER

MIN

UNIT
Without Diode

With Diode

tAOS

Reset delay time

160

320

ms

tAOS

Reset delay time during access pause

320

320

ms

tos

Keyboard debounce time

20

20

ms

tFL

Flash time

95

95

ms

Pulse dialing

fo

Dial frequency

tS/M

Break/make time

10

10

Hz

60/40

67/33

ms
ms

tlOP

Interdigit pause

840

840

tAP

Access pause

3

5

s

tH

Mute hold-over time (only during access pause)

1

1

s

DTMF dialing

tT

Tone transmission time

tp

Tone pause time

tH

Mute hold-over time during dialing

tH

Mute hold-over time during access pause

tAP

Access pause

January 14, 1987

70 or key-down time

ms

70

6·42

ms
150

150

ms

1

1

s

1.5

2.5

s

Product Specification

Signetics Linear Products

CMOS Redial and Repertory Dialer

PCD3315

Table 4. Timing Data, German Version
TYP
SYMBOL

PARAMETER

MIN

UNIT
Without Diode

With Diode

tRDS

Reset delay time

160

320

ms

tRDS

Reset delay time during access pause

320

320

ms

tDS

Keyboard debounce time

20

20

ms

Pulse dialing
fD

Dial frequency

tSIM

Breakl make time

10

10

Hz

60/40

60/40

ms
ms

tlDP

Interdigit pause

840

840

tAP

Access pause

3

5

s

tH

Mute hold-over time (only during access pause)

1

3

s

tpp

Prepulse time

20

ms

DTMF dialing

tr

Tone transmission time

tp

Tone pause time

tH

Mute hold-over time during dialing

tH

Mute hold-over time during access pause

tAP
tFL

80 or key-down time

ms

80

ms
160

160

1

1

ms
s

Access pause

1.5

2.5

s

Flash time

95

95

ms

II

tOB

KEYBOARD

ENTRY

-i---' I

I"

-~--------

I

'I" I -I

'----'-->CONTACT BOUNCE TIME +20ms

L____+ - - _

Ml

DP/FL

1---.--<*'>----------- DIALING MODE - - - - - - - - - -. .1------1.....-STATIC
CONVERSATION
MODE

CONVERSATION
MODE (AWAIT
DIALING TONE)

MODE

Figure 3a. Timing Diagram for Pulse Dialing Mode, Defined by PD/DTMF = LOW (Vss)

January 14, 1987

STANDBY

6-43

Signetics Linear Products

Product Specification

CMOS Redial and Repertory Dialer

Ht

RDS

U

1r---------i
CE -.l

(NO EFFECT)

PCD3315

-

,
I

KEY~~~~~ _ _ _ _~

M1

DTMF

OP/FL

----------------------------------------~
Figure 3b. Timing Diagram for DTMF Dialing Mode, Defined by PD/DTMF = HIGH (Voo)

January 14, 1967;

6-44

PCD3360

Signetics

Programmable Multi-Tone
Telephone Ringer
Product Specification
Linear Products

DESCRIPTION

FEATURES

The PCD3360 are CMOS integrated circuits, designed to replace the electromechanical bell in telephone sets. They
meet most postal requirements, particularly with tone sequence possibilities and
input frequency selectivity. Output signals for a loudspeaker or for a piezoelectric (PXE) transducer are provided. In the
former application, no audio transformer
is required since the loudspeaker is
driven in class D.

• Output signals for electrodynamic transducer (loudspeaker)
or for piezoelectric transducer
(PXE)

NOTE:
Tone sequences (up to 16 tones long). impedance
settings and automatic swell levels are mask pro~
grammable for customized versions.

PIN CONFIGURATION
D, N Packages

• 7 basic frequencies (tones) and a
pause
• 4 selectable tone sequences
• 4 selectable repetition rates

• 3 selectable impedance settings
• 3-step automatic swell
(loudspeaker only)
• Delta-modulated output signal
that approximates a sinewave
(loudspeaker only)

TOP VIEW

PIN NO. SYMBOL
POE
RR2
RR1
OSC
VDD
TONE

• Input frequency discriminator
with selectable upper and lower
frequency limits
• Output for optical signal

OPT
OM

9
10

APPLICATION

11

• Telephone hand sets

,.

12
13

ORDERING INFORMATION

15
16

DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

16-Pin Plastic DIP (SOT·38)

-25'C to + 75'C

PCD3360PN

16-Pin Plastic SO
(SO·16L; SOT·162A)

-25'C to + 75'C

PCD3360TD

IS2
IS1
Vss
TS2
TS1
FDI
FL

FH

DESCRIPTION

Frequency discriminator enable
Repetition rate selection
Oscillator
Positive supply
Tone output
Optical signal output
Drive mode selection

Impedance setting and
automatic swell
Negative supply
Tone sequence selection
Frequency discriminator input
Lower frequency limit selection
Upper frequency limit selection

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

Voo

Supply voltage range

100

±II>
±Io

RATING

UNIT

-0.8 to +9

V

Supply current

50

rnA

DC current into any input or output

10

rnA

VI

All input voltages

PTOT

Total power dissipation

-0.8V to Voo + 0.8

V

300

mW

Po

Total dissipation per output

50

mW

TSTG

Storage temperature range

-65 to +150

'C

TA

Operating ambient temperature range

-25 to +70

'C

December 2, 1986

6-45

853-1034 86700

II

Signetics Linear Products

Product Specification

Programmable Multi-Tone Telephone Ringer

PCD3360

BLOCK DIAGRAM
fCK

= 32kHz
(TONE PATTERN)

OSC

(32kHz PULSES)

OUTPUT
CIRCUIT

TONE

+----+--0 OPT

1---+--0 FDE

lSI

December 2, 1986

IS2

RRI RR2

6-46

TSI TS2

DM

FDI

FL

FH

Signetics Linear Products

Product Specification

Programmable Multi·Tone Telephone Ringer

DC ELECTRICAL CHARACTERISTICS

PCD3360

VDD = 6V; vss = 0; lose = 64kHz; TA = -25·C to+ 70·C; valid enable conditions at
FDI and FDE, unless otherwise specified,
LIMITS

SYMBOL

UNIT

PARAMETER
Min

Typ

Max

Supply

8.0

V

5.7

V

VDD

Operating supply voltage

VSB

Standby supply voltage 1

VAS

Supply voltage for automatic swell reset 2

IDD

Operating supply current

100

120

I1A

ISB

Standby supply current3
at VDD < VSB

4

8

I1A

VSB+O.l
TSD

4.8

V

0.5VSB

Inputs

Vil

Input voltage LOW (any pin)

0

O.3VDD

V

VIH

Input voltage HIGH (any pin)

0.7VDD

VDD

V

Pull-down circuits of inputs
Ril
IIH

FDE, RR1, RR2, DM, IS1, IS2, TS1, TS2, FL, FH
Pull-down resistance with input at Vss
Pull-down current with input at VDD

ISl
ISH
Isx

Pull-down circuit of FDI
Pull-down current with VFDI = 0.3VDD
Pull down current with VFDI = 0.7VDD
Pull-down current with VDD < VSB

± lis

Current into input FDI4

20
0.1
TSD

20
0.1
0.1

kf2

I1A
TSD

I1A
I1A
I1A

0.2

mA

Outputs (TONE, OPT)

IOl

Output sink current at Val = 0.5V

1

2

mA

-IOH

Output source current at VOH = VDD - 0.5V

1

2

mA

AC ELECTRICAL CHARACTERISTICS

VD D = BV; Vss = 0; fose = 64kHz; T A = -25 to + 70·C; valid enable conditions at FDI
and FDE, unless otherwise specified.
LIMITS

SYMBOL

UNIT

PARAMETER
Min

tD(on)

Switch-on delay
(with FDE = LOW and ringing frequency within limits set by FL and
FH)5

tD(off)

Switch-off delay (with FDE = LOW)
at FL= LOW
at FL= HIGH

fose

Oscillator frequency at Rose = 365kf2; Case = 56pF6

t.fose

Frequency variation at VDD = 5.7 to 8.0V

tD(off)

Typ

1

TSD

64

NOTES:
1. For Voo < VSB the circuit is in standby.
2. At V DD = VAS the automatic swell register is reset.
3. The standby supply current is measured with aU inputs and outputs open~circuit with the exception of asc.
4. The current lis is clamped to Voo and to Vss by two internal diodes. Correct operation is ensured with VFDI > Voo or VFDI
maximum value of lis is not exceeded. (The input FDI has an extended HIGH and LOW input voltage range.)
5. The switch-on delay is measured in cycles of incoming ringing frequency.
6. Lead lengths of Rose and Case to be kept to a minimum.

December 2, 1986

6-47

Max

1.5

ms

75

ms

112.5

ms

TSD

kHz

1

%

< Vss.

provided the

I

Signetics Linear Products

Product Specification

Programmable Multi-Tone Telephone Ringer

PCD3360

FUNCTIONAL DESCRIPTION
Supply Pins (VDD and Vss)

FOE

If the supply voltage (V DD) drops below the
standby voltage (Vss), the oscillator and most
other functions are switched off and the
supply current is reduced to the standby
current (Iss). The automatic swell register
retains its information until VDD drops further
to a value VAS at which reset occurs.

RR'
RR2
OM
181
1$2
TS'
TS2
FL

SELECTION
PINS

FH

Oscillator (OSC)
The 64kHz oscillator is operated via an externa resistor and capacitor connected to pin
ose. The oscillator signal is divided by two to
provide the 32kHz internal system clock.

Selection Pins (FDE, RR2, RR1,
DM, IS2, IS1, TS2, TS1, FL and
FH)
These pins are pulled down internally by a
pull-down current IIH when they are connected to VDD, and by a pull-down resistance RIL
when they are connected to Vss (see Figure
1). Thus, when the pins are open-circuit, they
are defined LOW. Therefore, only a singlecontact switch is required to connect the pins
to VDD; yet the supply current is only marginally increased as IIH is very small.

Frequency Discriminator Circuit
(Pins FDE and FDI)
The frequency discriminator circuit prevents
the ringer being activated by dial pulses,
speech or other unqualified signals.
The circuit is enabled or disabled by input
FOE.
When FOE is HIGH, FOI acts as a logic
enable input.
The circuit will produce tone sequences provided FOI is HIGH and VDD exceeds Vss.

PCD3360

v~s

NOTE,
1. Transistor resistance

=

All when switched on.

Figure 1. Input Circuit of Selection Pins
6) and an internal sink current that is switched
from 20pA (typ.) for FOI = LOW to < O. lilA
for FOI = HIGH. Excess current entering FOI
via R2 is absorbed to internal diodes clamped
to VDD and Vss·

Selection of Frequency
Discriminator Limits (FL and
FH)

The tone sequences are repeated continuously provided the enable conditions at inputs
FOE and FOI are valid and VD D > Vs B; the
first sequence always starts with the first tone
shown in Figure 3.

Table 1. Selection of Lower
Frequency Discriminator Limits
(fosc 64kHz)

Selection of Repetition Rates
(RR1 and RR2)

=

When FOE is LOW, FOI acts as the frequency
discriminator input.

FL INPUT
STATE

The circuit will produce tone sequences provided VDD exceeds Vss and the signal at FOI
fulfills the conditions set by FL and FH.

LOW
HIGH

20
13.33

The circuit will continue to produce tone
sequences provided the time between subsequent falling edges or between subsequent
rising edges remains within the limits set by
FL and FH. Because two edges are required
for detection, either positive or negative, the
switch-on delay will vary between t and 1.5
cycles of the incoming ringing frequency.
FOI has a Schmitt trigger action; the levels
are set by an external resistor R2 (see Figure
December 2, 1986

Four tone sequences are programmed in the
internal ROM (see Figure 3). Inputs TSt and
TS2 determine which tone sequence is selected and output at pin TONE. The sequences are mask-programmable with any
length up to 16 time intervals.

With the frequency discriminator enabled
(VDD > Vss and FDE = LOW) the lower and
upper limits of the input frequency are set by
inputs FL and FH as shown by Tables 1 and
2, respectively.

LOWER
DISCRIMINATOR
LIMIT (Hz)

When the frequency discriminator is enabled
(VDD > Vss and FOE = LOW) the circuit will
start to produce tone sequences after two
rising or two falling edges have occurred at
FDI. The time between these edges must be
within the limits set by FL and FH.

their corresponding internal ROM tone code
in Figure 2.

Table 2. Selection of Upper
Frequency Discriminator Limits
(fosc 64kHz)

=

FH INPUT
STATE

UPPER
DISCRIMINATOR
LIMIT (Hz)

LOW
HIGH

60
30

Selection of Tone Sequences
(TS1 and TS2)
A tone sequence is composed of 15 or 16
equal time intervals. Each time interval may
be filled with one of seven available tones or
with a pause; these are shown together with

6-48

The duration of a time interval within a tone
sequence is determined by the state of inputs
RRI and RR2 as shown in Table 3. The
resultant variation of repetition rate acts as a
distinguishing feature between adjacent telephones.

Table 3. Duration of Time
Intervals (fosc 64kHz)

=

INPUT STATE
RRI

RR2

TIME INTERVAL
(ms)

L
L
H
H

L
H
L
H

15
30
45
60

The repetition rate variation can be extended
by mask-programming (for customer defined
versions) the same tone combination for all 4
tone sequences, but with a different number
of time intervals per tone. Thus the repetition
rate can be selected from 16 values by inputs
RR1, RR2, TSI and TS2.

Product Specification

Signetics Linear Products

Programmable Multi-Tone Telephone Ringer

Drive Mode Selection (OM)

PCD3360

¥It :e=f?j

The output signal at pin TONE can be selected for application with electro-dynamic or
piezoelectric transducers. An example of both
signals, for a tone frequency of 667Hz, is
shown in Figure 4.
TONE KEY

Loudspeaker Mode
In the loudspeaker mode (OM = LOW), pin
TONE outputs a delta-modulated signal that
approximates a sinewave sampled at a rate
of 32kHz. The output pulse duration is determined by pins lSI and IS2. The resultant
acoustic spectrum is aurally more acceptable
and has greater penetration than a square
wave spectrum because more power is concentrated at the fundamental frequency.

FREQUENCY RATIO

PXE Mode
In the PXE mode (OM = HIGH), pin TONE
outputs a square wave. In this mode the
ringer impedance and sound pressure level
are determined by the characteristics (e.g.,
the size) of the PXE transducer; inputs lSI
and IS2 are inactive.

TS2

FREQUENCY (Hz)

~

C

0

E

G

B

C

533

600

667

800

1000

1067

1333

10

12

15

16

20

TONE CODe

Figure 2. Available Tones and Their Corresponding Internal ROM Tone Code

TONE SEQUENCE OUTPUT AT PIN TONE

PIN STATE

Setting of Impedance, Sound
Pressure Level and Automatic
Swell (IS1 and IS2)

With OM = LOW (loudspeaker mode), inputs
lSI and IS2 determine the pulse duration of
the output signal and thereby the DC resistance Rxy (seen at points x and y in Figure 6)
and also the Sound Pressure Level (SPL).
The selection of 3 impedance settings and
automatic swell is shown in Table 4.

TS1

rONECODE

3

3

3

4

4

4

2

2

2

7

7

7

6

6

6

rONECODE

1

3

1

3

1

3

1

3

1

3

1

3

1

3

1

rONECODE

4

5

4

5

4

5

4

5

4

5

4

5

4

5

4

5

rONECODE

4

4

4

0

4

4

4

0

4

4

4

4

4

4

0

0

Figure 3_ Tone Sequences Mask-Programmed in the PCD3360

Table 4. Setting of Pulse Duration and Automatic Swell (OM
INPUT STATE
FUNCTION
IS1

IS2

L

L

L
H
H

H
L
H

Automatic
Swell

Constant
Level

=LOW)

RINGING BURST PULSE DURATION (/1s)
NUMBER (N)
Harm
Fund
1
2
>2

1.8
2.6
3.9
2.6
3.6
5.0

1.6

Rxy
(k!1)

ZI
(k!1)

SPL
(dBr)

40
20
5

TBD
17.5
7

TBD
-4
0

20
10
5

17.5
10.5
7

-4
TBD
0

Where:

1. Typical pulse duration values of the fundamental and harmonic frequencies are for fose = 64kHz and fCK = 32kHz.
2. SPL is the relative Sound Pressure Level, and OdSr is defined as the SPL for lSI = IS2 = HIGH.
3. Values of the DC resistance Axy. bell impedance (ZI) and SPL are valid for a value of input voltage VI = 40VRMS in Figure 6.

December 2, 1986

6-49

Signetics Linear Products

Product Specification

Programmable Multi-Tone Telephone Ringer

Setting of Impedance, Sound
Pressure Level and Automatic
Swell
When pins 151 and 152 are both LOW, the
circuit operates in the automatic swell mode.
The 5PL then increases in three steps so that
the maximum level is reached for the third
ringing burst.
Each time VDD drops below V AS, the automatic swell register is reset and the next ringing
burst is considered as N = 1 (see Table 4).
A buffer capacitor C3 (see Figure 6) must
hold V DD > VAS during the time between two
consecutive ringing bursts of a series.
For each of the other three combinations of
pins 151 and 152, the pulse duration has a
constant value. Thus, the ringer' can be designed so that the impedance represented at
the telephone line will comply with postal
requirements that vary in relation to parallel or
series connections of more than one ringer.
To satisfy some applications, a harmonic
signal is added to the fundamental frequency
in the last step of the automatic swell mode.
The pulses representing this harmonic signal
are interleaved with the pulses of the fundamental signal (see Figure 5). The difference in
pulse duration shown in Table 4, is chosen so
that the harmonic level is 10dB below the
fundamental level.
The harmonic frequency range is from 2kHz to
3.2kHz. The individual harmonic frequencies
for the seven tone codes and the relative
fundamental frequencies are shown in Table
5.

Table 5_ Harmonic Frequency In
Relation to Tone Code and
Fundamental Frequency
FREQUENCY (Hz)

TONE
CODE

Fundamental

Harmonic

1
2
3
4
5
6
7

533
600
667
800
1000
1067
1333

3200
2400
2667
3200
2000
2133
2667

Using a single mask it is possible to program
the following:
• Addition of harmonics in all the other
input states of 151 and 152
• All pulse duration values
• Other even harmonic frequencies.

Optical Output (OPT)
The OPT output is designed to drive an
optical signal transducer or lamp. It is LOW
when the ringer circuit is enabled and HIGH
when the ringer circuit is disabled. This output
can also be used to switch the transmitter ON
and OFF in the base of a cordless telephone
set.

APPLICATION INFORMATION
Application of the PCD3360 in a telephone
ringer circuit together with a loudspeaker is
shown in Figure 6.
The threshold levels VH and VL of the frequency discriminator circuit are determined
by:
• The logic threshold of input FDI (0.5VDD
typo 3.4V for VDD = 6.8V)
• The pull-down current of input FDI
(20jlA typo for FDI < 3.4V)
• The value of R2 (680 kn in Figure 6)
For a positive slope, the voltage at R2 must
exceed the value VH before FDI will become
HIGH; VH is the sum of the input threshold
and the voltage drop across R2, thus:

December 2, 1986

6-50

PCD3360

V H = 3.4

+ (680

X 103) X (20 X 10- 6) = 17V.

For a negative slope, the voltage at R2 must
decrease below the value VL before FDI will
become LOW. Because the current into FDI
is negligible with FDI = HIGH, the voltage
drop across R2 can be discounted, thus
VL

= 3.4V.

The minimum operating voltage across C3 is
17.7V which is determined by:
• The minimum operating voltage of the
PCD3360 (5.7V)
• The supply current of the PCD3360
(120jlA maximum)
• The value of R3 (100kn in Figure 6)
The total switch-on delay equals approximately the time required to charge the supply
capacitor C3 to the minimum operating value,
plus the specified switch-on delay of the
PCD3360.
The high operating voltage combined with the
class D output stage ensures optimal energy
conversion and thereby a high sound level.
The design can easily be optimized for parallel or series connection of more than one
ringer. The diode bridge, zener diode (D1)
and resistor R1 protect the ringer against
transients up to 5kV. During these surges the
voltage on the 68V zener diode (BZW03) can
rise to 100V; the DM05 transistor B5T72
(TR1) has a maximum-drain source voltage of
100V. Up to 220V, 50Hz can be applied to the
AlB terminals without damaging the ringer.
The choke (U) in series with the son loudspeaker increases the sound pressure level
by approximately 3dB by suppression of the
32kHz carrier frequency and its sidebands.
The flyback diode BAX18A (D2) is a fast type
with low forward voltage to obtain high efficiency.
Application of the PCD3360 together with a
PXE transducer is shown in Figure 7. The only
significant difference between Figure 6 and
Figure 7 is the output stage. Two B5T72
transistors provide an output voltage swing
almost equal to the voltage at C3. Pins 151
and 152 are inoperative because DM = HIGH.
Volume control is possible using resistor Rv.

Signetics Linear Products

Product Specification

Programmable Multi-Tone Telephone Ringer

PCD3360

DEVELOPMENT SAMPLE DATA

OM

= HIGH

I
I
I

(PXE)

t FUND

OM

= LOW
(LSP)

= 48 )( 31.25 "" i500p.s

---J-,-~, ~+~~ttttj~[[ITttttt~~:~~~b-,-,-,-,-,s
.~.~, __ dJ~,J, H~1ttt
-I L..
10

40

30

20

48

31.25MS

___ l::~PULSE HAS ADURATION OF',
NOTE:
For fosc

= 64kHz,

to provide fCK

= 32kHz.

Figure 4. Fundamental Signal (667Hz) at Pin TONE

(LSP)

OM"" LOW

1,111,11111,111111111111111111111111,11,111.1.111"
---.1
1
0 LtHAAM "" 12 )( 31.25': 375,.,.s
. ..

___
NOTE:
For fosc

t FUND "" 48 )( 31.25

l~L:~DURATION =',

= 64kHz,

to provide fCK

20

___

r~L:~URATION

'=

'" JI,I,I,IJ", ,1,111,11111,11111
30

40

150011$

='H

= 32kHz.

Figure 5. Fundamental Signal (667Hz) + Harmonic Signal (2667Hz) at Pin TONE

December 2,. 1986

6-51

48
..

1

-ll31.25,us

•

Product Specification

Signetics Linear Products

PCD3360

Programmable Multi-Tone Telephone Ringer

x
Dl
BZW03

-C68

son

R3

lOOk

C2

D2
SAX18

10nF

D3
BZX79

-C6V8

AlB

~

t

lN5060
(4x)

+--NII'-+-+-+--+-t FDI
680k

Rl

PCD3360

OSC

TONE

1-->"" ,+..,
BST72

BIA-1
l~F

+

R2

Z,
-V,
Cl

C3
10,u.F

lk
(SW)

y

-=

V~I~__~____~____~
Figure 6. Transformerless Electronic Ringer With PCD3360 and a Loudspeaker

Dl

RS

R3

BZW03

-C6S

lOOk

C2

lOOk

10nF

TR2

+

lN5060

AlB----<~

(4x)
C4

SSpF
R2

+--NII'-+-+-+--+-t FDI
C1

Rl

680k

OSC

BIA -1l-VV\,-t_...J
lJ.1.F

(~~

365k

c:::::::J

PXE
TRANS-

DUCER

Figure 7. PCD3360 Ringer With PXE Transducer

December 2, 1986

6-52

TEA1046

Signetics

Transmission Interface With

DTMF
Product Specification

Linear Products
DESCRIPTION

FEATURES

This integrated circuit is a dual-tone
multi-frequency (OTMF) generator and a
speech transmission circuit on a single
chip_ It supplies frequency combinations
in accordance with CCITT recommendations for use in push-button telephones.
It can be operated with a single contact
keyboard or via a direct interface with a
microcomputer. 12L technology allows
digital and analog functions to be implemented on the same chip.

• Stabilized DTMF levels to be set
externally
• Wide operating range of line
current and temperature

The speech-transmission part incorporates microphone and telephone amplifiers, anti-sidetone, and line adaption. The
microphone inputs, suitable for different
types of transducers, are symmetrical to
allow long cable connections with good
immunity against radio-frequency interferences.

PIN CONFIGURATION

• No individual DTMF level
adjustments required
• Microcomputer-compatible logic
inputs
• Gain setting for microphone and
receiver amplifiers
• Internally-generated electronic
muting
• Low spreads on amplifier gains
• Low number of external
components
TOP VIEW
PIN NO. SYMBOL

The logic inputs contain an interface
circuit to guarantee well-defined states
and on and off resistance of the keyboard contacts.

ORDER CODE

24-Pin Plastic DIP (SOT-l0l)

-25°C to + 85°C

TEA1046PN

24-Pin Ceramic DIP (SOT-149)

-25°C to +85°C

TEA1046PF

ABSOLUTE MAXIMUM RATINGS
Icc

PARAMETER
Supply current

< 250MS)

RATING

UNIT

150

mA

850

mA

Is

Surge current (tp

TA

Operating ambient temperature range

-25 to +85

°C

TSTG

Storage temperature range

-65 to + 150

°C

TJ

Junction temperature

150

°C

January 14, 1987

VL
VN 1
VS
TI
TO

IC

TEMPERATURE RANGE

SYMBOL

1
2
3

8
9

ORDERING INFORMATION
DESCRIPTION

N, F Packages

6-53

10
11
12
13

14
15
16
17

18
19
20
21
22
23

24

ZI
AT

F,
F,
VN,
VREF
MIC1

M1C 2
ROW4
ROW3
ROW2
TLS
ROW1

COL1
COL2
COL3

COL4
OSC

DESCRIPTION
Positive line voltage
Negative line voltage
Voltage stabilizer filter
T elephana amplifier input
Telephone amplifier output
Internally connected
Impedance setting input
Anti-sidetone output
Second filter
First filter
Negative line voltage
Reference vOltage output
Microphone input (pos.)
Microphone input (neg.)
Row input 941Hz/BCD input
Row input 852Hz/BCD input
Row input 770Hz/BCD input
DTMF level setting
Row input 697Hz/BCD input
Column input 1209Hz/mute input
Column input 1336Hz/mute input
Column input 1477Hz/enable
input
Column input 1633Hz/mute input
Oscillator input

853-114287202

Signetlcs Linear Products

Product Specification

Transmission Interface With DTMF

TEA1046

BLOCK DIAGRAM

ROW 1
ROW 2
ROW 3
ROW 4

-- r--- , -r-19

-.:!17

15

--

-

23

COL 4
COL 3

COL 2
COL 1

r-

~l-

i----

I
N
T
E
R
F
A
C
E

I

:

'---

~

-

""I
I

--

~

-

f--

+3 (4)

r--

+3

[>

f-

- ~-

I-

<3

[>

7I
f-l-

F

t
l - I""""

OAC

t
I

18

OTMF
REF.

TLS

ACTIVE
OUTPUT STAGE

r--

[>

~I

8
1

[>
DC
REGULATOR

....

4

~
3

h-

FJ;

f--

~

7

I

5

TELEPHONE
AMPLIFIER

6~

I
VAEF

-=-

fVN 1

IC

6-54

21

$

t>i) -

~

T1

January 14, 1987

10
OAC

-'-

J

BUFFER

9

VL

I

t

MICROPHONE
AMPLIFIER

AT

18
SCALER

...

I

..!!
14

,..- f--

+m

-I""""

OSCIL·
LATOR

14
SCALER

t

MUTE

CSC

-

+n

r!-

G
I
C

r---I-r----

- r-

7I

0

f----

21

2! I-

I
N
P
U
T
L

r-- I12-

TO

Product Specification

Signetics linear Products

TEA1046

Transmission Interface With DTMF

DC ELECTRICAL CHARACTERISTICS TA = 25°C; IL = 15mA, unless otherwise specified. See also Figure 9.
LIMITS
SYMBOL

UNIT

PARAMETER
Min

Typ

Max

4.5
4.7
5.0

4.8
5.0
5.4

5.1
5.3
S.5

Supply

VL
VL
VL

Line voltage DC
IL = t5mA
IL = 50mA
IL = 100mA

TC

Temperature coefficient

IL

Line current range

Vs
Vs

Stabilized voltage (Pin 3)
IL=15mA
IL = 100mA

3.3
3.8

V
V

VREF

Reference voltage (Pin 12)

1.0

V

kn

-8
10

V
V
V
mVrC

120

mA

Microphone

R113-14

Input resistance (symmetrical)

4

RI13

Input resistance (asymmetrical)

22

AM

Voltage amplification f = 800Hz; RL = soon

TC

Temperature coefficient IL = 50mA; TA = -5 to +45°C

CMRR

Common-mode rejection ratio

dt

Distortion at VL = 3dBm

VNO

Noise output voltage
ZL = soon; psophometrically weighted (P53 curve)

~M

48

50

kn
52

TBD

dB
dB
dB

SO
2

%

-70

dBmp

Amplification reduction during dialing

70

dB

Voltage amplification, microphone to
anti-sidetone output (RAT = 3.9kn)

25.8

dB

Antl-sldetone

AAT

Transmitter output stage

RI

Dynamic resistance setting range

Ll.Zo

Variation over line current RI = SOOn

BRL
BRL

Balance return loss from 300 up to 3400Hz
at soon (RZI = 75n, CL = 10nF)
at 900n (Rzi = 120n, CL = 30nF)

600

900
100

n
n

20
20

dB
dB

Telephone amplifier

AT

Voltage amplification RT = 350n

~T/f

Amplification variation f = 300 to 3400Hz

0

~T/T

Amplification variation T = - 5 to + 45°C

0

dB

Vo(P-P)

Output voltage swing (dT = 10%)

1300

mV

Zo

Output impedance

ZI

Input impedance

do

Output distortion level < - 7dBV

VNO (RMS)

Output noise voltage psophometrically weighted (P53 curve)

1M

Bias current

January 14, 1987

18

20

5

22

dB

10

100

6-55

3.5

n
kn
%

2

3

dB

500

MV

4

mA

II
I

Signetics Linear Products

Product Specification

Transmission Interface With DTMF

TEA1046

DC ELECTRICAL CHARACTERISTICS (Continued) TA = 25'C; IL = 15mA, unless otherwise specified. See also Figure 9.

I

LIMITS
SYMBOL

PARAMETER
Min

Typ

UNIT

Max

DTMF generator
Tone frequencies
low tones (row inputs)

high tones (column inputs)

697
770
852
941

Hz
Hz
Hz
Hz

1209
1336
1477
1633

Hz
Hz
Hz
Hz

.:lfD
.:lfD

Dividing error
crystal frequency
crystal frequency

VLG
VHG

Tone output level
IL> 10mA
lower tones
higher tones

VLG
VHG

Tone output level
IL> 12mA
lower tones
higher tones

.:lVo

Tolerance on output level over temp. and current range

-2

.:lVHG

Pre-emphasis higher tones over temp. and current range

1.3

tD

Tone delay after key actuation

10

tD

Switch delay time speech/mute after key release

10

J1S

tSB

Switch bounce elimination

2

ms

= 4.78MHz
= 3.58MHz

-0.04
-0.25

+0.11
-0.05

-11
-9

-11
-9

2

%
%

dBm
dBm

-6
-4

dBm
dBm

2

dB

2.7

dB

J1S

Keyboard inputs
RKOFF

Contact off resistance

RKON

Contact on resistance

VIL
VIH
IlL
IIH

Lower frequency inputs (ROW1, 2, 3, 4)
voltage LOW
voltage HIGH
current (DC) at VIL
current (DC) at VIH

TBD

VIL
VIH
IlL
IIH

Higher frequency inputs (COL 1, 2, 3, 4)
voltage LOW
voltage HIGH
current (DC) at VIL
current (DC) at VIH

TBD

January 14, 1987

kQ

250

6-56

0.7
1.7
20

10

kQ

TBD

V
V
p.A
p.A

1000

0.3
1.0

TBF

20

1000

V
V
p.A
p.A

Signetics Linear Products

Product Specification

TEA1046

Transmission Interface With DTMF

FUNCTIONAL DESCRIPTION

Active Output Stage

Voltage Regulator (Figure 1)

The amplifier consists of a voltage-to-current
converter with a class-A output stage. Because of the feedback from the line to the
input, the circuit acts as a dynamic resistance
(Ra). This resistance can be adjusted by the
external resistor Rzio and the value can be
found by:

Different line lengths and feeding bridge resistances of the exchange cause a large line
current range to supply this circuit. As all
functions on this chip are working within a
total current of 10mA, the rest of the line
current is shunted by the voltage regulator
circuit. It regulates the voltage drop over the
circuit on a nominal level of 4,8V.
The capacitor connected to input VS provides
a low-pass filter function to avoid influence of
the audio signals on the line.
The static behavior of the voltage regulator is
expressed by:

where Va = 4.8V at TA = 25°C and
R13 = 5n, II = 10mA.
The dynamic impedance of the regulator is
equivalent to a resistor in series with a
simulated inductor:
Zr(w) = REO + jwLEO
where REO = R13 = 5n
LEQ""5H(Cvs = 68J.lF).
By connecting a resistor parallel to R12, the
DC level (VLl can be decreased. A resistor
parallel to CVS increases the level (see Figure
1). This is with respect to limited values. The
shunt regulator contains a thyristor which
short-circuits R12 for a short period during
the switch-on time. This reduces the overshoot voltage to only 1V above the level set
by the regulator.

AM(RMA * 0)
22+ RMA
.
...c:.:.:....:.:::..:....-'. = - - - (RMA In kn)
AM(RMA = 0) 22+ 11 RMA

RA = 8.93 X RZI(n)
The total dynamic resistance, Rio equals RA,
parallel with the resistance Rp of all other
circuit parts, which value is approximately
7kn.
With RZI = 75n, RA = 670n and RI = 610n.
For RZI = 120n, RA = 1070n and RI = 900n.

Microphone Amplifier

VL = Va + (lL -II) R13

impedance in this asymmetrical mode is
22kn. If attenuation of the amplification is
required, the value of RMA is given by:

Pins 13 and 14, respectively, are the noninverting and inverting inputs for the microphone. The purely symmetrical inputs are
suitable for low-ohmic dynamic or magnetic
capsules. The input impedance equals 4kn.
The voltage amplification from microphone
input to Pin 1 (VLl is 50dB, and if a lower gain
is required, the attenuation for a series resistor RMS will be:
•
AM(RMS*O)

4

AM(RMS = 0)

4+ RMS

Telephone Amplifier and AntiSidetone Network
This amplifier is a non-inverting fixed-feedback amplifier with a class-A output stage.
The gain is fixed and measures 20dB from Pin
4 (TI) to Pin 5 (TO). The output is intended to
drive capsules ZT of nom. 350n. For ZT
smaller than 350n, the maximum output
voltage swing is determined by the bias
current of 3.5mA and ZT. For ZT greater than
350n, the maximum voltage swing is determined internally. The received line signal is
attenuated by the anti-sidetone network and
can be adjusted by RAT. The amplification
from the line to the telephone output is given
by:

(RMS in kn)
Zs is the impedance of the anti-sidetone network
ZT is the capsule impedance
Ro is the amplifier output resistance

AM=I~~1
The microphone amplifier also has an excellent behavior for connection of an electret
microphone with built-in FET source-follower.
In this condition, Pin 14 is decoupled for AC
and the amplifier is driven at Pin 13. The input

Optimum sidetone suppression is obtained as
Zs (RA1' RA2, and CAl equals:

R12

t
IL

10-141lmA

R13

3

Vs

+

Figure 1. Voltage Regulator Principle
January 14, 1987

6-57

Signetics Linear Products

Product Specification

TEA1046

Transmission Interface With DTMF

ZL = line terminating impedance
RI = output stage impedancellpassive circuit
impedance
K=237

MIC,

In the application of Figure 12, the network is
optimized for 5km of twisted copper wire (¢
O.5mm) cable with a DC resistance of 176!21
km. The sidetone suppression in the range
from 0 - 10km is at least 10dB compared to
the case when no compensation is applied.

.------1 f-___1.:..4'MIc"

Keyboard Inputs

R MS

'-_.....__"'1<,..,...__.;..14,

Mlc"

NOTE:
Resistor RMP may be used to lower the microphone
termination resistance.

Figure 2. Symmetrical Microphone
Connection

January 14, 1987

Inputs for the logic control are compatible
with different types of keyboard. Using a
keyboard, tone combinations are generated:
• by connecting one of the row inputs to
one of the column inputs by means of
a single switch of the matrix
• or by applying a dual·contact keyboard
having its common row contact tied to
ground and the common column contact
tied to VREF
An anti-bounce circuit eliminates the switch
bounce for up to 2ms. Two-key roll-over is
provided by blocking other inputs as soon as
one key is pressed. Single tones can be
generated if the column input is connected to
VREF, or the row input to ground. The inputs
for the keyboard connections can be used for
direct connection to a microcomputer.

6-58

' - _ - - '_ _ _...L.._ _....,

VN,

Figure 3. Electret Microphone Circuit
If the column inputs are interconnected and
made HIGH (= VREF), the row inputs are
changed to another mode, allowing the circuit
to be driven by 4-bit data plus an enable
signal. In this mode, it is also possible to
connect a separate mute enable signal on
inputs COl1, 2, and 4, and a tone enable
input on COl3.

Signetics Linear Products

Product Specification

TEA1046

Transmission Interface With DTMF

MICROCOMPUTER MODE TRUTH TABLE
ROW

COLUMN

1

2

3

4

H

H

H

X

X

X

TONES
(Hz)

SYMBOL

1,2,4

3

H

L

L

-

-

X

H

L

-

-

H

H

H

H

H

H

697/1209

1

H

H

H

L

H

H

697/1336

2

H

H

L

H

H

H

697/1477

3

H

H

L

L

H

H

697/1633

A

H

L

H

H

H

H

770/1209

4

H

L

H

L

H

H

770/1336

5

H

L

L

H

H

H

770/1477

6

H

L

L

L

H

H

770/1633

B

L

H

H

H

H

H

852/1209

7

L

H

H

L

H

H

852/1336

8

L

H

L

H

H

H

852/1477

9

L

H

L

L

H

H

852/1633

C

L

L

H

H

H

H

941/1209

L

L

H

L

H

H

941/1336

0

L

L

L

H

H

H

941/1477

#

L

L

L

L

H

H

941/1633

D

.

MUTE

off
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on

1/0,

ROW 1

uo"
uo.

ROW 2

1/°4

ROW,

ROW 3

MICROCOMPUTER

TEA1046
MUTE

= ENABLE

COL 1

110s

uo"

-

t-t--

COL 3

'---

COLo

COL 2

Figure 4. Microcomputer Mode; All Column Inputs Interconnected

January 14. 1987

6-59

Signetics Linear Products

Product Specification

Transmission Interface With DTMF

ROW 1.
ROW 2.
ROW 3.
OR
ROW 4
COL 1
COL 2
COL 3
AND
COL 4

TEA1046

X

X

X

I

\

I

\'---

LINE
SIGNAL
SPEECH

DTMF

SPEECH

DTMF

SPEECH

Figure 5. Tone/Speech Waveform in Circuit Diagram (Figure 4)

1/°1

ROW 1

I/O,

ROW 2

110,

ROW 3

1/°4

ROW 4

MICROCOMPUTER

TEA1046
MUTE
COL 1

1/°5

-

COL 2

ENABLE
I/O.

COL 3

-

COL 4

Figure 6. Microcomputer Mode; Column Inputs COL 1, 2, and 3 Interconnected

ROW 1.

::~~:J(~

____

>e:

-J)(~______J)(~______J)(~_______

COL 1

\ ......_ -

COL2~

C:~

COL3~

\

\'----

LINE
SIGNAL
SPEECH

DTMF

SILENCE

DTMF

SILENCE SPEECH

Figure 7. Tone/Speech Waveform in Circuit Diagram (Figure 6)

January 14. 1987

6·60

Signetics Linear Products

Product Specification

Transmission Interface With DTMF

TEA1046

Dial Tone Generator
The crystal oscillator frequency is twelve or
nine times the clock frequency; i.e.,
4.7B2720MHz or 3.579545MHz (mask option). The CCITT recommends that the tones
should be within 1.5% of the specified frequencies. Many authorities, however, require
a closer tolerance. The application using a
crystal of 4.7BMHz gives a maximum dividing
error of 0.11 %, while for an application with a
3.5BMHz crystal the error is 0.25% maximum.
The output from the dividers for the higher
and the lower frequency tones are symmetrical square wave pulses which contain considerable odd-numbered harmonics. The lowerorder odd-numbered harmonics (11th and
less) are eliminated by synthesizing the tone
frequencies as crude stepped sine wave
approximations. Each half cycle of the tone
waveform comprises seven discrete amplitudes for the higher frequency tone. Each
amplitude increment is generated by switching on and off an individual current source for
the duration of each step of the sine wave.
The frequency of the tones is varied by
changing the duration of each step. This
circuit allows the connecting of two low-pass
first-order filters to Pins 9 and 10 if CEPT 203
recommendations have to be achieved.

ROW1~
I
I

I

I

ROW2~
I

I

ROW3~
I

I

I

I

I

I

I

I
I

I
I

I
I

I
I

I

ROW 4

COL3~
COL1'2'4~
UNE'
SIGNAL

M.~UUlllUI

V

I
I
I

A.I\.
'It' ..

V ~

SPEECH

DTMF SILENCE SPEECH

Figure 8. Waveform Tones 697/1336Hz (Dialing Number 2)

The second filter is also used for filtering the
microphone signal. If lower requirements for
the distortion can be applied, the filter at Pin
10 can be deleted. In that case, the filter at
Pin 9 must have a lower cut-off frequency
(1 BOOHz) to achieve a correct pre-emphasis,
since the roll-off of the filters is compensated
internally.

January 14, 19B7

I
I

6-61

Signetics Linear Products

Product Specification

Transmission Interface With DTMF

TEA1046

:::--.
:::--.

ROW4
15
VL

R0W2

ROwa
18

17

1~W1

1

23 C0L4

-22 COL3

1M

~oJI~
10,~F

+
1OO"F

F,

:::--.

21 COL2

OSC 24

20 COLI

:::--.

MIG,

~1

9

TEA1046

II

"" VM

14 MIC,

~
IL
1O-14OmA

RTLS

600

':'

33"F

~,l

TLS 18

'--

22nF

-

TI

4

2

3
Vs

CL
lOnF

F~

7
ZI

8
AT

RZI

Uk

+
88"F

'V VT1

f

+

12

10

VREF

F,

VN,

T

I

V'IO

l

9'~

33 "F

NOTES:

Figure 9. Test Circuit for MlHlsurlng Amplifier Voltage Gains and Frequencies and
Levels of DTMF Generator; X = 3.58 or 4.78MHz

January 14, 1987

6-62

350

Product Specification

Signetics Linear Products

TEA1046

Transmission Interface With DTMF

600

RrLsMIN

1
~

~

!!1
g

500

r.------'~......o:::--+---

-5

~~

I

RrLS MAX 300 \

I
-10

-----1

,:'

~1----r-----jL.OiW-F-R-EQt-U-E-NtCy--="""t----;;;;;Jt:::=-r-j 200
:
TONE GROUP
I

35

40

45

55

80

S5

Figure 10. DTMF Level Selection; the Curve Is Valid for a Dynamic Impedance of 600n (Rzi = 75n)

SOME VALUES:
LOW
(dBm)

HIGH
(dBm)

RTLS
(kn)

-6

-4

35.2

-8

-6

44.8

-11

-9

62.6

$

v,

r--- LOGIC

f--LOGIC
5k

5k

ROW1

CO....

VN

VN

lD07230S

LD07220S

a. ROW1, 2, 3 and 4

b. COL1, 2, 3 and 4
Figure 11. Configuration Inputs

January 14, 1987

v,

6-63

Signetics Linear Products

Product Specification

Transmission Interface With DTMF

TEA1046

COL4
VL

COL1

COLS
22

23

20

1

19

ROW!

0000

17 ROW2
Rx~M)

0ITI[Il[!]

16 ROW3

OSC 24

0[!][!]@]

15 ROW4

000~

IC 6

RLP

18

;~

13 MIt:,
F2

9
TEA1046
14 MIC,

VN2 11

CL
lOnF

C.

1nF

5 TO
+

RA2
56k

CAT

2.2nF

On
22nF

TI 4

2 VN,
3

7

VS

ZI

AT

+c""
88_F

RZI

RAY·

8

12

10

VREF

F1

Cpo

lOnF

+c.,.

33_F
~

Figure 12. Application Diagram TEA1046. Using Dynamic Transducers, RMS, RAT, RZI and RTLS
Determined by Transducers and System Requirements

January 14, 1987

6-64

Signetics

TEA1060j61
Versatile Telephone
Transmission Circuits With
Dialer Interface

Linear Products

Product Specification

DESCRIPTION
The TEA1060 and TEA1061 are bipolar
integrated circuits performing all speech
and line interface functions required in
fully electronic telephone sets. The circuits internally perform electronic
switching between dialing and speech.

FEATURES
• Voltage regulator with adjustable
static resistance
• Provides supply for external
circuitry
• Symmetrical low-impedance
inputs for dynamic and magnetic
microphones (TEA 1060)
• Symmetrical high-impedance
inputs for piezoelectric
microphone (TEA1061)

• Asymmetrical high-impedance
input for electret microphone
(TEA1061)
• DTMF signal input
• Mute input for pulse or DTMF
dialing
• Power down input for pulse dial
or register recall
• Receiving amplifier for magnetic,
dynamic or piezoelectric
earpieces
• Large amplification setting range
on all amplifiers
• Line loss compensation faCility,
line current dependent
• Gain control adaptable to
exchange supply

PIN CONFIGURATION
N Package
SLPE

Vee
MUTE
DTMF
PO
IR

TOP VIEW
PIN NO.

1

SYMBOL

LN
GAS,
GAS2
OR-

APPLICATION

OR+

• Electronic telephone sets

GAR

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

18-Pin Plastic DIP (SOT-l02A)

-25 to + 75°C

TEA1060PN

18-Pin Plastic DIP (SOT-l02A)

-25 to +75°C

TEA1061PN

ABSOLUTE MAXIMUM RATINGS
SYMBOL

RATING

UNIT

VLN

Positive line voltage

13.2

V

IUNE(Av)
IUNE(S)
IUNE(SM)

Line current
average
non-repetitive (tMAX = 100 hours)
non-repetitive peak (tMAX = 1ms)

140
250
1

rnA
rnA
A

Vcc + 0.7
0.7

V
V

V
-V

PARAMETER

Voltage on all other pins

PTOT

Total power dissipation

TSTG

Storage temperature range

TA

Operating ambient temperature range

December 2. 1986

640

mW

-65 to +150

°C

-25 to +75

°C

6-65

9
10
11
12
13
14
15
16
17
18

MICMIC+
STAB
VEE
IR
PD
DTMF
MUTE

Vee
REG
AGe
SLPE

DESCRIPTION
Positive line terminal
Gain adjustment;
transmitting amplifier
Gain adjustment;
transmitting amplifier
Inverting output;
receiving amplifier
Non-inverting output;
receiving amplifier
Gain adjustment;
receiving amplifier
Inverting microphone input
Non-inverting microphone input
Current stabilizer
Negative line terminal
Receiving amplifier input
Power·down input
Dual·tone multi·frequency input
Mute input
Positive supply decoupling
Voltage regulator decoupling
Automatic gain control input
Slope (DC resistance)
adjustment

853-1049 86702

I

Signetics linear Products

Product Specification

Versatile Telephone Transmission Circuits
With Dialer Interface

TEA1060j61

BLOCK DIAGRAM
LN
15

IR~l1+--------r--------------i

r----------t-t-QGAA

MIC+

GAS,
MIC-

13

GAS,

01MF

MUTE

PO

"
12

,.

18

REG

AGe

SfAB

NOTES:
The blocks marked "dB" are attenuators.
The block marked (1) is only present in the TEA1061.

December 2, 1986

6-66

SLPE

Signetics Linear Products

Product Specification

Versatile Telephone Transmission Circuits
With Dialer Interface

TEA1060j61

DC ELECTRICAL CHARACTERISTICS IUNE = 10 to 140mA; VEE = OV; f = BOO Hz; TA = 25°C, unless otherwise specified.
LIMITS
SYMBOL

PARAMETER

UNIT
Min

Typ

Max

4.15

4.15
4.35
6.0

4.55
7

V
V
V

-4

-2

0

mVI"C

0.96
50

1.25

mA
p.A

Supply: LN and Vee (Pins 1 and 15)
V LN
VLN
VLN

Voltage drop over circuit
at IUNE = 5mA
at IUNE = 15mA
at IUNE = 100mA

DoVLN/DoT

Variation with temperature at IUNE

Icc
Icc

Supply current
at Vcc = 2.BV; PD
at Vcc = 2.BV; PD

= 15mA

= LOW
= HIGH

Microphone inputs MIC+ and MIC-

IZlsl
IZlsl

Input impedance
TEA1060
TEA1061

4
20

kn
kn

a

Standard deviation on input impedance

12

%

kCMR

Common-mode rejection ratio; TEA 1060

BO

dB

AVD
AVD

Voltage amplification at
IUNE = 15mA; R7 = 6Bkn
TEA1060
TEA1061

DoAvDI Dof

Variation with frequency
at f = 300 to 3400Hz

±0.2

dB

D.AvDI DoT

Variation with temperature at
IUNE = 50mA; TA = -25 to + 75°C

±0.5

dB

51
37

52
3B

53
39

dB
dB

Dual-tone multi-frequency input DTMF

IZlsl

Input impedance

20

kn

a

Standard deviation on input impedance

12

%

AVD

Voltage amplification
at IUNE = 15mA; R7

D.AvDI Llf

Variation with frequency
at f = 300 to 3400Hz

±0.2

dB

D.AvDI LIT

Variation with temperature at
IUNE = 50mA; T A = -25 to + 75°C

±0.5

dB

= 6Bkn

25

26

27

dB

Gain adjustment (Pins GAS1 and GAS2)

D.AVD

Amplification variation with R7, transmitting amplifier

-B

+B

dB

Transmitting amplifier output LN

= 15mA;

VLN(RMS)
VLN(RMS)

Output voltage at IUNE
dTOT = 2%
dToT = 10%

VNO(RMS)

Noise output voltage
at IUNE = 15mA; R7 = 66kn
psophometrically weighted (P53 curve)

1.4

2.3
2.6

V
V

-70

dBmp

20

kn

Receiving amplifier input IR

IZlsl

December 2, 1966

Input impedance

6-67

II
I

Signetics Linear Products

Product Specification

Versatile Telephone Transmission Circuits
With Dialer Interface

TEA1060j61

DC ELECTRICAL CHARACTERISTICS (Continued) ILiNE = 10 to 140mA; VEE = OV; f = 800Hz; TA = 25'C, unless
otherwise specified.
LIMITS
SYMBOL

PARAMETER

UNIT
Min

Typ

Max

Receiving amplifier outputs QR+ and QRIZosl

Output impedance; single-ended

Avo
Avo

Voltage amplification
at ILiNE = 15mA; R4 = 100kn;
single-ended; RL = 300.11
differential; RL = 600.11

4

t:.Avo/ l1f

Variation with frequency,
at f = 300 to 3400Hz

to.2

dB

t:.Avo/ l1T

Variation with temperature at
ILiNE = 50mA;TA = -25 to + 75'C

to.5

dB

VO(RMS)
VO(RMS)
VO(RMS)

Output voltage at Icc = 0; dTOT = 2%; sine wave drive
single-ended; RL = 150.11
single-ended; RL = 450.11
differential; CL = 47nF + RL = loon; f = 3400Hz

0.38
0.52
1.0

V
V
V

VNO(RMS)
VNO(RMS)

Noise output voltage
at ILiNE = 15mA; R4 = 100kn;
psophometrically weighted (P53 curve)
single-ended; RL = 300.11
differential; RL = 600.11

50
100

MV
MV

24
30

0.3
0.4
0.8

25
31

.11

26
32

dB
dB

Gain adjustment (Pin GAR)
Amplification variation with R4, receiving amplifier

-8

+8

dB

VIH
VIL

Input voltage
HIGH
LOW

1.5

Vcc
0.3

V
V

IMUTE

Input current

8

15

MA

-l1Avo

Reduction of voltage amplification from
MIC+ and MIG- to LN at MUTE = HIGH

70

dB

AVD

Voltage amplification from DTMF to QR+ or QR- at
MUTE = HIGH; single-ended load;
RL = 300.11

-18

dB

t:.Avo
MUTE input

Power-down input PO
VIH
V1L

Input voltage
HIGH
LOW

Ipo

Input current

1.5
5

Vcc
0.3

V
V

10

!lA

Automatic gain control input AGe
-t:.Avo

Amplification control range

6

dB

ILiNE

Highest line current for maximum amplification at
R6 = 110kn

22

mA

ILiNE

Lowest line current for minimum amplification at
R6 = 110kn

60

mA

December 2, 1986

6-68

Signetics Linear Products

Product Specification

Versatile Telephone Transmission Circuits
With Dialer Interface
FUNCTIONAL DESCRIPTION
Supply: Vee, LN, SLPE, REG
and STAB
The circuit and its peripheral circuits usually
are supplied from the telephone line. The
circuit develops its own supply voltage at Vcc
and regulates its voltage drop. The supply
voltage Vcc may also be used to supply
external peripheral circuits, e.g., dialing and
control circuits.
The supply has to be decoupled by connecting a smoothing capacitor between Vcc and
VEE; the internal voltage regulator has to be
decoupled by a capacitor from REG to VEE.
An internal current stabilizer is set by a
resistor of 3.6k11 between STAB and VEE.
The DC current flowing into the set is determined by the exchange supply voltage,
VEXCH, the feeding bridge resistance REXCH,
the DC resistance of the subscriber line RLiNE
and the DC voltage on the subscriber set (see
Figure 1).

phones. Its input impedance is 2 X 4k11 and
its voltage amplification is typically 52dB.
The TEA 1061 is intended for a piezoelectric
microphone or an electret microphone with
built-in FET source follower. Its input impedance is 2 X 20k11 and its voltage amplification is typically 38dB.
The arrangements with the microphone types
mentioned are shown in Figure 3.
The amplification of the microphone amplifier
in both types can be adjusted over a range of
± 8dB to suit the sensitivity of the transducer
used. The amplification is proportional to
external resistor R7 connected between
GAS 1 and GAS2.
An external capacitor C6 of 100pF between
GAS 1 and SLPE is required to ensure stability. A larger value may be chosen to obtain a
first-order low-pass filter. The cut-off frequency corresponds with the time constant
R7 X C6.

Mute Input MUTE

If the line current ILiNE exceeds the current
Icc + 0.5mA required by the circuit itself
(lcc"'1mA), plus the current Icc required by
the peripheral circuits connected to Vcc, then
the voltage regulator diverts the excess current via LN.

A HIGH level at MUTE enables the DTMF
input and inhibits the microphone inputs and
the receiving amplifier, a LOW level or an
open circuit does the reverse. Switching the
mute input will cause negligible clicks at the
telephone outputs and on the line.

The voltage regulator adjusts the average
voltage on LN to:

Dual-Tone Multi-Frequency Input
DTMF

VLN = VREF + ISLPE X R9
= VREF + (ILiNE - Icc - 0.5.10- 3 - Icel
X R9.

When the DTMF input is enabled, dialing
tones may be sent onto the line. The voltage
amplification from DTM F to LN is typically
26dB and varies with R7 in the same way as
the amplification of the microphone amplifier.
The signalling tones can be heard in the
earpiece at a low level (confidence tone).

VREF being an internally-generated temperature-compensated reference voltage of 4.1 V
and R9 being an external resistor connected
between SLPE and VEE. Under normal conditions ISLPE > Icc + 0.5mA + Icc. The static
behavior of the circuit then equals a 4.1 V
voltage regulator diode with an internal resistance R9. In the audio frequency range the
dynamic impedance equals R1.
The current Icc available from Vee for supplying peripheral circuits depends on external
components, and on the line current. Figure 2
shows this current for Vcc = 3V min., this
being the minimum supply voltage for most
CMOS circuits including a diode voltage drop
for an enable diode. If MUTE is LOW, the
available current is further reduced when the
receiving amplifier is driven.

Microphone Inputs MIC + and
MIC - and Gain Adjustment
Pins GAS 1 and GAS 2
The TEA 1060 and TEA 1061 have symmetrical microphone inputs.
The TEA1060 is intended for low-sensitivity,
low-impedance dynamic or magnetic micro-

December 2, 1986

Receiving Amplifier: IR, QR + ,
OR- and GAR
The receiving amplifier has one input IR and
two complementary outputs, a non-inverting
output OR + and an inverting output OR - .
These outputs may be used for single-ended
or for differential drive, depending on the
sensitivity and type of earpiece used (see
Figure 6). Amplification from IR to OR + is
typically 25dB. This will be sufficient for lowimpedance magnetic or dynamic earpieces;
these are suited for single-ended drive. By
using both outputs (differential drive) the
amplification is increased by 6dB. This makes
differential drive possible, which is required
for high-impedance dynamic, magnetic and
piezoelectric earpieces with load impedances
exceeding 45011.
The output voltage of the receiving amplifier
is specified for continuous-wave drive. The
maximum output voltage will be higher under
speech conditions, where the ratio of peak
and RMS value is higher.

6-69

TEA1060/61

The amplification of the receiving amplifier
can be adjusted over a range of + 8dB to suit
the sensitivity of the transducer used. The
amplification is proportional to external resistor R4 connected from GAR to OR + .
Two external capacitors C4 = 100pF and
C7 = 10 X C4 = 1nF are necessary to ensure
stability. A larger value of C4 may be chosen
to obtain a first-order, low-pass filter. The
"cut-off" frequency corresponds with the
time constant R4 X C4.

Automatic Gain Control Input
AGC
Automatic line loss compensation will be
obtained by connecting a resistor R6 from
AGC to VEE. This automatic gain control
varies the amplification of the microphone
amplifier and the receiving amplifier in accordance with the DC line current. The control
range is 6dB. This corresponds with a line
length of 5km for a 0.5mm diameter copper
twisted-pair cable with a DC resistance of
17611/km and an average attenuation of
1.2dB/km.
Resistor R6 should be chosen in accordance
with the exchange supply voltage and its
feeding bridge resistance (see Figure 5 and
Table 1). Different values of R6 give the same
ratio of line currents for begin and end of the
control range.
If automatic line loss compensation is not
required AGC may be left open. The amplifiers then all give their maximum amplification
as specified.

Power-Down Input PD
During pulse dialing or register recall (timed
loop break) the telephone line is interrupted;
as a consequence, it provides no supply for
the transmission circuit. These gaps have to
be bridged by the charge in the smoothing
capacitor C1. The requirements on this capacitor are relaxed by applying a HIGH level
to the PD input, which reduces the supply
current from typically 1mA to typically 50p.A.
A HIGH level at PD further disconnects the
capacitor at REG, with the effect that the
circuit's impedance equals a 4.1 V voltage
regulator diode with an internal resistance
equal to R9. This results in rectangular current waveforms in pulse dialing and register
recall. When this facility is not required PD
may be left open.

Side-Tone Suppression
Suppression of the transmitted signal in the
earpiece is obtained by the anti-side-tone
network consisting of R2, R3, R8 and ZSAL
(see Figure 8). Maximum compensation is
obtained when ZSAL/k equals the line impedance ZLiNE as seen by the set (scale factor
k=Rs/R1)'

•

Signetics Linear Products

Product Specification

Versatile Telephone Transmission Circuits
With Dialer Interface
In practice ZLiNE varies strongly with line
length and cable type; consequently, an average value has to be chosen for ZBAL. The
suppression further depends on the accuracy

RL.INE

with which ZBAL/k equals the average line
impedance.
The anti-side-tone network attenuates the
signal from the line. With R8 = 390n and

IUNE

Rl

ISLPE +O.SmA

ec

I

vee

1

DC

lo.smA

+

AC

C1

REG

VEXCH

STAB
ISLPE

RS

,.
8_ _ _

r

Icc

LN

TEA1060
TEA1061

R9 = 20n the attenuation is 32dB. The attenuation is nearly flat over the audio-frequency
range.

--,
15

REXCH

TEA1060j61

SLPE

VEE

18

10

b

0.•

PERIPHERAL
CIRCUITS

i

I

R9

~

Jl

I

_J

VoeM
NOTE:
Curve "a" is valid when the receiving amplifier is
not driven or when MUTE"" HIGH; curve "b" is valid when MUTE"" LOW and the receiving amplifier is
driven, VO(RMS) "" 150mV. RL"" 150n.

Figure 2. Maximum Current Icc
Available from Vee for External
(Peripheral) Circuitry With Vee;;' 3V

Figure 1. Supply Arrangement

r--.....,,....-~MIC+

......M.-----=-t MIC+

'--"'-~'-IMIC-

L..VV\,.----=-t MIC-

NOTE:
The resistor marked (1) may be connected to lower the
terminating impedance.

a. Magnetic or Dynamic
Microphone, TEA1060

b. Electret Microphone, TEA 1061
Figure 3. Alternative Microphone Arrangements

December 2, 1986

6-70

c. Piezoelectric Microphone
TEA1061

Signetlcs Linear Products

Product Specification

Versatile Telephone Transmission Circuits
With Dialer Interface

::~05

QR+[]

V ~ 10

QR+[)5
QR-

QR+

(1)

4

QR-

TEA1060/61

D

QR-

b. Dynamic Telephone With
More Than 450n Impedance

4
LD07090S

LOO7061S

a. Dynamic Telephone With
Less Than 450n Impedance

O
(2)

NOTE,

NOTE,

The resistor marked (1) may be
connected to obtain an appropriate
acoustic frequency characteristic.

The resistor marked (2) is required to
increase the phase margin.

c. Magnetic Telephone With
More Than 450n Impedance

d. Piezoelectric Telephone

Figure 4. Alternative Receiver Arrangements

R6=~

\\

""'"

\ \'\ f'\.
\ r\'\

r-46.7kQ\~\ ~OkQ~kQ
l 1\ \ \
-6
20

40

60

R9=-20Q

80

120

100

140

180

ILlN,frnA)

II
I

Figure 5. Variation of Amplification With Line Current, With R6 as a Parameter

Table 1. Values of Resistor R6 for optimum Line Loss
Compensation, for Various Usual Values of
Exchange Supply Voltage VEXCH and Exchange Feeding
Bridge Resistance REXCH
REXCH (n)
400

600

800

1000

X
68
93.1
120

X
60.4
82
102

R6 (kn)

VEXCH (V)

December 2, 1986

24
36
48
60

61.9
100
140
X

48.7
78.7
110
X

6-71

Signetics Unear Products

Product Specification

Versatile Telephone Transmission Circuits
With Dialer Interface

TEA1060j61

R1
620

~

IR

l~'F

1,

1'5

Vee

LN

QR-

~

Vo
8

~v,

MIC+
QR+

7

GAR

TEA1060
TEA1061

6

GAS,

10 TO 14IlmA

2
R7
68k

~

PD

v••
10

'V

lr

MUTE

+
10~F

bC4

lnF

~.F

I.......o.~

600

lOOk T'OOPF

DTMF

+C1

RL

R4

MIC-

13
..;

5

REG

AGC

16

STAB

17

9

GAS"
SLPE

~

:h:

PF

18

V,

T

+ C3

R6

4.7.F

R5

3.6k

R9

20

NOTES:
Voltage amplification is defined as: Avo"" 20 log IVoIVIl
For measuring the amplification from MIC+ and MIC -. the MUTE input should be LOW or open; for measuring the DTMF input, MUTE should be HIGH.
Inputs not under test should be open.

Figure 6. Test Circuit for Defining Voltage Amplification of MIC+, MIC- and DTMF Inputs

December 2, 1986

6-72

Signetics Linear Products

Product Specification

Versatile Telephone Transmission Circuits
With Dialer Interface

TEA1060/61

R1
620

15
11

LN

Vee

IR

QR-

Zl
MIC+

10jAF

I

Vo

600

QR+
R4
100k

MICGAR

TEA1060
TEA1061

13
DTMF

+

C7
1nF

C1
100,.F

10 TO 140mA
GAS,

14
MUTE

R7
12

PO

V••
10

REG

AGC

16

STAB

17

4.71J.F

GAS,
SLPE
18

+
C3

C6
100pF

R6

R5
3.6k

R9
20

NOTE:

Voltage amplifictaion is defined as: Avo'" 20 log IVolVl1.

Figure 7. Test Circuit for Defining Voltage Amplification of the Receiving Amplifier

December 2, 1986

6-73

II

Signetics linear Products

Product Specification

Versatile Telephone Transmission Circuits
With Dialer Interface

TEA1060j61

APPLICATION INFORMATION
R1
620

R10
13

R2

os

130k 100nF

LN

11 IR
R3

a92.

RI1

4 QR13
QR+

C4
100pF
8

FROM DIAl

AND

TEA1067

CONTROL CIRCUITS
GAR

S MIC+

MICSLPE

,.

R8
380

.....

G....

C8
100pF

GAS,

R7

,.

REG

AGe

STAB

17

R8

VEE
10

AS
3.8.

R9
20

NOTE:
The bridge to the left, the zener diode and Al0 limit the current into the circuit and the voltage across the circuit during line transients. Pulse dialing or register fecall require a different
protection arrangement.

Figure 8. Typical Application of the TEA1060 or TEA1061, Shown Here With a Piezoelectric Earpiece and DTMF Dialing

December 2, 1986

6·74

Signetics Linear Products

Product Specification

Versatile Telephone Transmission Circuits
With Dialer Interface

TEA1060j61

APPLICATION INFORMATION (Continued)

LN

Vee

DTMF ....- - - - - ; DTMF
TEA1060

DTMF

MUTE 1------1 M

DIALER

TEA1061
PO

FL

VEE

TELEPHONE
LINE
8ST76

NOTE:

The dashed lines show an optional flash (register recall by timed loop break).

a. DTMF Set With a CMOS DTMF Dialing Circuit

Voo
DTMF

TEAUO
TEA1061

MUTE
PO

PCD3320
FAMILY

M

DP

I ,'

V..

V"

TELEPHONE

0

LINE

,\'.'i

i

b. Pulse Dial Set With One of the PCD3320 Family of CMOS Interrupted Current-Loop Dialing Circuits

LN

Vee

voo

OTMF
TEA1060
TEA1061

MUTe
PO

VE,

M

PCD3340

DP/Fl
V..

TELEPHONE
LINE

I'C

DTMf

PCD3312

c. Dual-Standard (Pulse and DTMF) Feature Phone With the PCD3340 CMOS Telephone Controller
and the PCD3312 CMOS DTMF Generator With 12C Bus
Figure 9. Typical Applications of the TEA1060 or TEA1061 (Simplified)

December 2, 1986

6-75

TEA1067

Signetics

Ie

Low Voltage Transmission
With Dialer Interface
Product Specification

Linear Products

DESCRIPTION
The TEA 1067 is a bipolar integrated
circuit performing all speech and line
interface functions required in fully electronic telephone sets. It performs electronic switching between dialing and
speech. The circuit is able to operate
down to DC line voltage of 1.6V (with
reduced performance) to facilitate the
use of more telephone sets in parallel.

FEATURES
• Low DC line voltage; operates
down to 1.6V (excluding polarity
guard)
• Voltage regulator with adjustable
static resistance
• Provides supply with limited
current for external circuitry
• Symmetrical high-impedance
inputs (64kn) for dynamic,
magnetic or piezoelectric
microphones

• Asymmetrical high-impedance
input (32kn) for electret
microphone
• DTMF signal input with
confidence tone
• Mute input for pulse or DTMF
dialing
• Power down input for pulse dial
or register recall
• Receiving amplifier for magnetic,
dynamic or piezoelectric
earpieces
• Large amplification setting range
on microphone and earpiece
amplifiers
• Line loss compensation faCility,
line current dependent
(microphone and earpiece
amplifiers)
• Gain control adaptable to
exchange supply
• Possibility to adjust the DC line
voltage

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

18-Pin Plastic DIP (SOT-102HE)

TEA1067PN

PIN CONFIGURATION
N Package

vee
MUTE
OTMF
PO

TOP VIEW
C011540$

PIN NO. SYMBOL
LN
GAS 1

GAS2
QRQR+
GAR

9
10
11
12
13
14
15
16
17
18

MIGMIC+
STAB

V"

IR
PO
OTMF
MUTE

Vee
REG
AGe
SLPE

DESCRIPTION
Positive line terminal
Gain adjustment; transmitting
amplifier
Gain adjustment; transmitting
amplifier
Inverting output; receiving amplifier
Non-inverting; receiving amplifier
Gain adjustment; receiving
amplifier
Inverting microphone input
Non-inverting microphone input
Current stabilizer
Negative line terminal
Receiving amplifier input
Power-down input
Dual-tone multi-frequency input
Mute input
Positive supply decoupling
Voltage regulator decoupling
Automatic gain control input
Slope (DC resistance) adjustment

ABSOLUTE MAXIMUM RATINGS
SYMBOL

RATING

UNIT

VLN

Positive line voltage continuous

PARAMETER

12

V

VLN

Repetitive line voltage during
switch-on or line interruption

13.2

V

VLN

Repetitive peak line voltage
tplP = 1ms/5s; R10 = 13Q;
R9 = 20Q (see Figure 8)

28

V

IUNE

Line current

140

mA

VI
-VI

Voltage on all other pins

Vee + 0.7
0.7

V
V

PTOT

Total power dissipation

TSTG

Storage temperature range

TA

Operating ambient temperature range

December 2, 1986

640

mW

-65 to + 150

°C

-25 to +75

°C

6-76

853-1041 86701

Signetics Linear Products

Product Specification

TEA1067

low Voltage Transmission Ie With Dialer Interface

BLOCK DIAGRAM
LN

Vee
15

IRo-+-------~------------~

r----------r-+-oG~

r--t-t-o OR+
r--t-t-o OR-

MIC+ o-:.+_------~----------+_~

.------+-+=-<>...,

MIC-

o-:.t-------+----------+-+--I

OTMF

<>-'t-------+----I

MUTE

<>-'-'t-------+------------+--------------------.J

'------+_+-O GAS,

PO

18

V"

December 2, 1986

REG

AGC

srAB

6-77

.LPO

II

Signetics Linear Products

Product Specification

Low Voltage Transmission Ie With Dialer Interface

TEA1067

DC ELECTRICAL CHARACTERISTICS IUNE = 11 to 140mA; VEE = OV; f = 800Hz; TA = 25°C, unless otherwise specified.
LIMITS
SYMBOL

PARAMETER

UNIT
Min

Typ

1.75
2.25
3.55
3.65
4.9

1.6
2.0
2.8
3.8
3.90
5.6

Max

Supply: LN and Vcc (Pins 1 and 15)

VLN
VLN
VLN
VLN
VLN
VLN
VLN

Voltage drop over circuit; between Pin 1
and Pin 10 = VLN; microphone inputs open
at IUNE
at IUNE = 4mA
at IUNE = 7mA
at IUNE = 11mA
at IUNE = 15mA
at IUNE = 100mA
at IUNE = 140mA

2.25
3.35
4.05
4.15
6.5
7.5

V
V
V
V
V
V
V

~VLN/~T

Variation with temperature at IUNE = 15mA

-3

-1

1

mV/oC

VLN
VLN

Voltage drop over circuit with external resistor RVA
at IUNE = 15mA
RVA (Pin 1 to Pin 16) = 68kn
RVA (Pin 16 to Pin 18) = 39kn

3.1
4.2

3.4
4.5

3.7
4.8

V
V

Icc
Icc

Supply current Icc; current into Pin 15
PD = LOW (Pin 12); Vcc = 2.8V
PD = HIGH (Pin 12); Vcc = 2.8V

1.0
55

1.35
82

mA

Icc

Current available from Pin 15 to supply peripheral circuits at IUNE = 15mA
Vee;;' 2.2V; Mute = High

1.4

1.8

51
25.5

64
32

!-LA
mA

Microphone Inputs MIC+ and MIC- (Pins 7 and 8)

Izisl
Izisl

Input impedance
differential (between Pins 7 and 8)
single-ended (Pin 7 or WRT VEE)

CMRR

Common-mode rejection ratio

Avo

Voltage amplification (from Pins 7 - 6 to Pin 1) at
IUNE = 15mA; R7 = 68kn

~vD/~f

Variation with frequency at f

~vD/~T

Variation with temperature at IUNE

77
36.5

82

= 300

to 3400Hz

= 50mA;

TA

= -25

kn
kn
dB

51

52

53

dB

-0.5

±0.2

+0.5

dB

TBD

to + 75°C

dB

Dual-tone multi-frequency Input DTMF (Pin 13)

IZlsl

Input impedance

TBD

20.7

TBD

kn

Avo

Voltage amplification (from Pin 13 to Pin 1) at
IUNE = 15mA; R7 = 68kU

24.5

25.5

26.5

dB

~vD/~f

Variation with frequency
f = 300 to 3400Hz

-0.5

±0.2

+0.5

dB

~vD/~T

Variation with temperature at
IUNE = 50mA;TA = -25 to + 75°C

±0.2

dB

Gain adjustment GAS1 and GAS2 (Pins 2 and 3)
~VD

Amplification variation with R7 (connected between Pins 2 and 3)
transmitting amplifier

-8

0

dB

Sending amplifier output LN (Pin 1)
VLN(RMS)
VLN(RMS)
VLN(RMS)
VLN(RMS)

Output voltage at IUNE = 15mA;
dTaT = 2%
dTOT = 10%
at IUNE = 4mA; dTOT = 10%
at IUNE = 7mA; dTOT = 10%

VNO(RMS)

Noise output voltage, IUNE = 15mA; R7 = 66kn; 200n between Pins 7 and 6;
psophometrically weighted (P53 curve)

December 2, 1986

1.9

6-78

1.9
2.2
0.6
1.4

V
V
V
V

-72

dBmp

Signetics Linear Products

Product Specification

Low Voltage Transmission Ie With Dialer Interface

TEA1067

DC ELECTRICAL CHARACTERISTICS (Continued) ILiNE = 11 to 140mA; VEE = OV; f = 800Hz; TA = 25°C, unless
otherwise specified.
LIMITS
SYMBOL

PARAMETER

UNIT
Min

Typ

Max

TBD

20

TBD

Receiving amplifier input IR (Pin 11)

IZlsl

Input impedance

kn

Receiving amplifier outputs QR+ and QR- (Pins 5 and 4)

IZosl

Output impedance; single-ended

Avo
Avo

Voltage amplification from Pin 11 to Pins 4 - 5 at ILiNE
single-ended; RL = 300n (from Pin 11 to Pins 4 - 5)
differential; RL = 600n (from Pin 11 to Pins 4 - 5)

Avo/ Af

Variation with frequency, f

AAvo/ AT

Variation with temperature
ILiNE = SOmA; TA = -25 to + 75°C

VO(RMS)
VO(RMS)
VO(RMS)

Output voltage at Icc = 0; dTOT = 2%;
sine wave drive; R4 = 100kn
single-ended; RL = 150n
single-ended; RL = 450n
differential; CL = 47nF (100n series resistors);
f = 3400Hz

VO(RMS)
VO(RMS)

Output voltage at Icc = 0; dTOT = 10%;
sine wave drive; R4 = 100kn; RL = 150n
ILiNE = 4mA
ILiNE = 7mA

VNO(RMS)
VNO(RMS)

Noise output voltage
ILiNE = 15mA; R4 = 100kn; Pin 11 open
psophometrically weighted (P53 curve)
single-ended; RL = 300n
differential; RL = 600n

= 300

4

= 15mA;

R4

to 3400Hz

n

= 100kn;
30
36

31
37

32
38

dB
dB

-0.5

±0.3

+0.5

dB

±0.2

dB

0.25
0.45

0.29
0.55

V
V

0.65

0.80

V

15
130

mV
mV

50
100

IN
/lV

Gain adjustment GAR (Pin 6)

AAvo

Amplification variation with R4 (connected between Pins 6 and 5),
receiving amplifier

-11

+8

dB

1.5

Vcc
0.3

V
V

15

!1A

MUTE input (Pin 14)
VIH
VIL

Input voltage
HIGH
LOW

IMUTE

Input current

8

AAvo

Reduction of voltage amplification from MIC+ (Pin 7) and MIC(Pin 8) to LN at MUTE = HIGH

70

Avo

Voltage amplification from DTMF (Pin 13) to QR+ (Pin 5) or
QR- (Pin 4) at MUTE = HIGH, single-ended load RL = 300n

December 2, 1986

6-79

-21

-19

dB

-17

dB

Signetics Linear Products

Product Specification

low Voltage Transmission Ie With Dialer Interface

TEA1067

DC ELECTRICAL CHARACTERISTICS (Continued) IUNE = 11 to 140mA; VEE = OV; f = 800Hz; TA = 25°C, unless
otherwise specified.
LIMITS
SYMBOL

UNIT

PARAMETER
Min

Typ

Max

Power-down input PO (Pin 12)
VIH
VIL

Input voltage
HIGH
LOW

IpD

Input current (into Pin 12)

1.5
5

Vec
0.3

V
V

10

IlA

Automatic gain control input AGe (Pin 17)

AVD

Controlling the gain from Pin 11 to Pins 4 - 5 and the gain
from Pins 7 - 8 to Pin 1; R6 = 11 OkQ (between Pins 17 and 10)
amplification control range

-6

dB

IUNE

Highest line current for maximum amplification

22

mA

IUNE

Lowest line current for minimum amplification

60

mA

December 2, 1986

6-80

Signetics Linear Products

Product Specification

low Voltage Transmission Ie With Dialer Interface

FUNCTIONAL DESCRIPTION
Supply: Vee, LN, SLPE, REG
and STAB
The circuit and its peripheral circuits usually
are supplied from the telephone line. The
circuit develops its own supply voltage at Vcc
and regulates its voltage drop. The supply
voltage Vcc may also be used to supply
external peripheral circuits, e.g., dialing and
control circuits.
The supply has to be decoupled by connecting a smoothing capacitor between Vcc and
VEE; the internal voltage regulator has to be
decoupled by a capacitor from REG to VEE.
An internal current stabilizer is set by a
resistor of 3.6kr! between STAB and VEE.
The DC current flowing into the set is determined by the exchange supply voltage VEXCH,
the feeding bridge resistance REXCH, the DC
resistance of the subscriber line RUNE and
the DC voltage on the subscriber set (see
Figure 1).
If the line current IUNE exceeds the current
Icc + 0.5mA required by the circuit itself
(Icc~ 1mAl, plus the current Icc required by
the peripheral circuits connected to Vcc, then
the voltage regulator diverts the excess current via LN.
The voltage regulator adjusts the average
voltage on LN to:
VLN = VREF + ISLPE X R9
= VREF + (IUNE -Icc - 0.5 X 10- 3 -Icd
X R9.
VREF being an internally-generated temperature-compensated reference voltage of 3.6V
and R9 being an external resistor connected
between SLPE and VEE. The preferred value
of R9 is 20r!. Changing R9 will have influence
on microphone gain, DTMF gain, gain control
characteristics, side tone, maximum output
swing on LN and on the DC characteristic
(especially in the low voltage part). Under
normal conditions ISLPE }> Icc + 0.5mA
+ Icc. The static behavior of the circuit then
equals a 3.6V voltage regulator diode with an
internal resistance R9. In the audio frequency
range the dynamic impedance equalS R1.
The internal reference voltage can be adjusted by means of an eX1ernal resistor RVA· RVA
(1 - 16) connected between pins LN and
REG will decrease the internal reference
voltage. RVA (16-18) connected between
REG and SLPE will increase the internal
reference voltage.
At line currents below 9mA the internal reference voltage is automatically adjusted to a
lower value (Typ. 1,6V at 1mAl. This means
that the operation of more telephone sets in
parallel is possible with DC line voltages
(excluding the polarity guard) down to an
December 2, 1986

absolute minimum voltage of 1.6V. At line
currents below 9mA the circuit has limited
sending and receiving levels.
The current Icc available from Vcc for supplying peripheral circuits depends on external
components and on the line current. Figure 4
shows this current for Vce > 2.2V minimum. If
MUTE is LOW, the available current is further
reduced when the receiving amplifier is driven. To increase the supply possibilities, the
supply IC TEA 1080 can be connected in
parallel with R1 (Figure 9c). An alternative is
to set the DC line voltage to a higher value by
means of an external resistor RVA (16 - 18)
connected between REG and SLPE.

Microphone Inputs MIC + and
MIC - and Gain Pins: GAS1 and
GAS 2
The TEA 1067 has symmetrical microphone
inputs. Its input impedance is 64kr!
(2 X 32kr!) and its voltage amplification is
typo 52dB. Either dynamic, magnetic, piezoelectric microphones or an electret microphone with built-in FET source-follower can
be used.
The arrangements with the microphone types
mentioned are shown in Figure 3.
The amplification of the microphone amplifier
can be adjusted between 44dB to 52dB to
suit the sensitivity of the transducer used. The
amplification is proportional to external resistor R7 connected between GAS 1 and GAS 2 .
An amplification more than 52dB is possible
(up to 60dB); however, in that case, the
spread of the DC voltage (VLN) will increase
and the minimum voltage at 11 mA
(VLN = 3.55V) cannot be guaranteed. An external capacitor C6 of 100pF between GAS1
and SLPE is required to ensure stability. A
larger value may be chosen to obtain a firstorder low-pass filter.
The cut-off frequency corresponds with the
time constant R7 X C6.

Mute Input: MUTE
A HIGH level at MUTE enables the DTMF
input and inhibits the microphone inputs and
the receiving amplifier input; a LOW level or
an open circuit does the reverse. Switching
the mute input will cause negligible clicks at
the telephone outputs and on the line. In case
the line current drops below 6mA (parallel
operation of more sets) the circuit is always in
speech condition independent of the DC level
applied to the MUTE input.

Dual-Tone Multi-Frequency Input
DTMF
When the DTMF input is enabled, dialing
tones may be sent onto the line. The voltage
amplification from DTMF to LN is typo 25.5dB
and varies with R7 in the same way as the
amplification of the microphone amplifier. The

6-81

TEA1067

signaling tones can be heard in the earpiece
at a low level (confidence tone).

Receiving Amplifier: IR, OR + ,
OR-and GAR
The receiving amplifier has one input IR and
two complementary outputs, a non-inverting
output OR + and an inverting output OR - .
These outputs may be used for single-ended
or for differential drive, depending on the
sensitivity and type of earpiece used (see
Figure 4). Amplification from IR to OR + is
typo 31dB. This will be sufficient for lowimpedance magnetic or dynamic earpieces;
these are suited for single-ended drive. By
using both outputs (differential drive) the
amplification is increased by 6dB and differential drive becomes possible. This feature
can be used in case the earpiece impedance
exceeds 450r! (high-impedance dynamic,
magnetic or piezoelectric earpieces).
The output voltage of the receiving amplifier
is specified for continuous-wave drive. The
maximum output voltage will be higher under
speech conditions, where the ratio of peak
and RMS value is higher.
The amplification of the receiving amplifier
can be adjusted between 20 and 39dB with
single-ended drive and between 26 and 45dB
in case of differential drive to suit the sensitivity of the transducer used. The amplification is
proportional to external resistor R4 connected from GAR to OR + .
Two external capacitors C4 = 100pF and
C7 = 1a X C4 = 1n F are necessary to ensure
stability. A larger value of C4 may be chosen
to obtain a first-order low-pass filter. The
"cut-off" frequency corresponds with the
time constant R4 X C4.

Automatic Gain Control Input
AGC
Automatic line loss compensation will be
obtained by connecting a resistor R6 from
AGC to VEE. This automatic gain control
varies the amplification of the microphone
amplifier and the receiving amplifier in accordance with the DC line current. The control
range is 6dB. This corresponds with a line
length of 5km for a 0.5mm diameter copper
twisted-pair cable with a DC resistance of
176r!/km and an average attenuation of
1.2dB/km.
Resistor R6 should be chosen in accordance
with the exchange supply voltage and its
feeding bridge resistance (see Figure 5 and
Table 1). Different values of R6 give the same
ratio of line currents for begin and end of the
control range. If automatic line loss compensation is not required AGC may be left open.
The amplifiers then all give their maximum
amplification as specified.

•

Signetics Linear Products

Product Specification

TEA1067

Low Voltage Transmission Ie With Dialer Interface

Power-Down Input PD

Side-Tone Suppression

During pulse dialing or register recall (timed
loop break) the telephone line is interrupted;
as a consequence. it provides no supply for
the transmission circuit and the peripherals
connected to Vee. These gaps have to be
bridged by the charge in the smoothing capacitor C1. The requirements on this capacitor are relaxed by applying a HIGH level to
the PD input during the time of the loop break.
which reduces the supply current from typically 1mA to typically 55/IA.

Suppression of the transmitted signal in the
earpiece is obtained by the anti-side-tone
network consisting of R1 ZUNE. R2. R3. RB.
R9 and ZeAL (see Figure B). Maximum compensation is obtained when the following
conditions are fulfilled:

A HIGH level at PD further disconnects the
capacitor at REG. with the effect that the'
voltage stabilizer will have no switch-on delay
after line interruptions. This results in no
contribution of the IC to the current waveform
during pulse dialing or register recall. When
this facility is not required. PD may be left
open.

RllNE

a) R9 X R2 = R1(R3 + [RBIIZeAl))
b) [ZeAL/(ZeAL + RB)]

= [ZUNE/

To obtain optimum side-tone-suppression.
condition b) has to be fulfilled resulting in:
ZeAL = (RB/R1)ZUNE = k,ZUNE
Where k is a scale factor; k = (RB/R1).
Scale factor k (value of RB) must be chosen
to meet the following criteria:

Rl

'LINE

ISLPE +O.5mA

IN

TEA1067

Vee

10.smA
C1

STAB

SLPE

VEE

18

10

RS

I~

!\
I~

\
1\

PERIPHERAL
CIRCUITS

\!\
\i\

1

I
I
_J

'SLPE

C3

The anti-side-tone network as used in the
standard application (Figure B) attenuates the
signal from the line with 32dB. The attenuation is nearly flat over the audio-frequency
range. Instead of the above described special
bridge. the conventional Wheatstone bridge
configuration can be used as an alternative
anti-side-tone circuit. Both bridges can be
used with either a resistive set impedance or
with a complex set impedance.

ec

AC

REG

In practice ZUNE varies strongly with the line
length and cable type; consequently. an average value has to be chosen for ZSAL' The
suppression further depends on the accuracy
with which ZSAL/k equals the average line
impedance.

r
I
1

DC

VEXCH

• I ZBALIIR81 <{ R3
• IZSAL + RBI <{ R9

--,
Icc
15

R EXCH

(ZUNE + R1)]

If fixed values are chosen for R1. R2. R3 and
R9. then condition a) will always be fulfilled
provided that I RBIIZBAL I <{ R3.

• compatibility with a standard capacitor
from the E6 or E12 range for ZeAL

R9

2
Vcc(V)

NOTES:
a) "" 1,BmA

b)

=

1.35mA

'UNE"" 15mA at VLN '" 3.9V

R1 ,;;: 620n and R9 "" 20n

Figure 1. Supply Arrangement

Curve (a) is valid when the receiving amplifier is not
driven or when MUTE", HIGH,

Curve (b) is valid when MUTE = LOW and the receiving amplifier is driven; VO(RMS)" 150mV, RL == 150n

asymmetrical. The supply possibilities can be increased simpy by setting the voltage drop over the
circuit VLN to a higher value by means of resistor RVA

(16-18).

Figure 2. Typical Current Icc Available
from Vec for Peripheral Circuitry With
Vec> = 2.2V

December 2. 1986

6-82

Signetics Linear Products

Product Specification

Low Voltage Transmission Ie With Dialer Interface

TEA1067

.---t---=-I MIC +

,.....Wlrl~--I

'---"'---'-f MIC-

.....W_~--IMIC-

MIC+

NOTE:
The resistor marked (1) may be connected to lower the
terminating impedance. In case of sensitive microphone
types a resistor attenuator can be used to prevent overloading of the microphone inputs.

a. Magnetic or Dynamic
Microphone

b. Electret Microphone

c. Piezoelectric Microphone

Figure 3. Alternative Microphone Arrangements

'''0 'TJ 0

~'O

QR+

=

QR-

vee

10

OR- 4

QR-

QR-

4

LD01090S

NOTE:
The resistor marked (1) may be
connected to prevent distortion
(inductive load).

a. Dynamic Telephone With
Less Than 450[2 Impedance

NOTE:
The resistor marked (2) is required to
increase the phase margin (capacitive
load).

c. Magnetic Telephone With
More Than 450[2 Impedance

b. Dynamic Telephone With
More Than 450[2 Impedance

d. Piezoelectric Telephone

Figure 4. Alternative Receiver Arrangements

.""-"\\
\

iii' -2
S

1

-4

r----

R6=oo

\"

78.7""\ ~Ok~kQ
\

-6
20

40

\
60

R9=20Q

80

100

120

140

160

IUNE(mA)

Figure 5. Variation of Amplification With Line Current With RS as a Parameter

December 2. 1986

6-83

Signetics Linear Products

Product Specification

TEA1067

Low Voltage Transmission Ie With Dialer Interface

Table 1. Values of Resistor R6 for Optimum Line Loss
Compensation, for Various Usual Values of Exchange
Supply Voltage VEXCH and Exchange Feeding Bridge
Resistance REXCH.
REXCH (n)
400

600

1000

800
R6 (kn)

VEXCH
(V)

36

100

78.7

X

X

48

140

110

93.1

82

60

X

X

120

102

NOTE:

R9

~20n

R1
620

l,s
~

1,

Vee

IR

LN

QR-

~

l'00"F
Vo

8

9
VI

QR+
7

1S
+

MIC+

S

RL
BOO

R4

:::LC4
lOOk T'00 PF

MICGAR

TEA1067

H-

6

OTMF

1nF

C1

IOO"F

--o~
+
:: IO"F

GAS,

10 TO 140mA

2

MUTE
R7

68k

o---E.

::b?GIOOpF

3

PO
VEE

10

REG

AGe

16

17

STAB

GAS"
SLPE

9

18

-

"" V,

T

+ CS

R6

4.7"F

RS
S.6k

R9
20

NOTE:
Voltage amplification is defined as: Avo = 2010g lVolVJl For measuring the amplification from MIC+ and MIC-, the MUTE input should be LOW or open; for measuring the DTMF input,

MUTE should be HIGH. Inputs not under test should be open.

Figure 6. Test Circuit for Defining Voltage Amplification of MIC+. MIC- and DTMF Inputs

December 2, 1986

6-84

Signetics Linear Products

Product Specification

low Voltage Transmission Ie With Dialer Interface

TEA1067

R1
620

1S
11

IN

Vee

IR

QRZl

MIC+

lO~F

I

Va

QR+

MICGAR

TEA1067
13
+

600
R'
100k

C7
1nF

OTMF

C1

10 TO 140mA

100J,lF

l'

GAS,
MUTE
R7

12

PO
V••

10

AGC

REG

STAB

17

16

100pF

GAS,
SlPE
18

+
C3
4.7j.1F

C6

R6

R5
3.6k

R9
20

NOTE:
Voltage amplification is defined as: Avo = 20109 IVolVl1.

Figure 7. Test Circuit for Defining Voltage Amplification of the Receiving Amplifier

December 2, 1986

6-85

•

Product Specification

Signetics Linear Products

TEA1067

Low Voltage Transmission Ie With Dialer Interface

R1
620

R10
13

R2
C5
130k 100nF
R3
3.92k

11

R11

LN

IR

4 QR13
OR+

C.

,

FROMDfAL

TEA1067

100pF

AND
CONTROL CIRCUITS

GAR

S MIC+

MICSLPE

V__
GAS,

G....

1a

Ra
390

e8
100pF

REG

AIle
17

16

R7

.8

STAB
9

10

.5

3.8k

e3

4.7J.1F

.....

R9
20

NOTE:
The bridge to the left, the zener diode and R1D limit the current and the voltage into the circuit during line transients. Pulse dialing or register recall require a different protection
arrangement. By means of resistor (R16_18) the DC line voltage can be set 10 a higher value.

Figure 8. Typical Application of the TEA 1067, Shown Here With a Piezoelectric Earpiece and DTMF Dialing

December 2, 1986

6-86

Signetics Linear Products

Product Specification

low Voltage Transmission Ie With Dialer Interface

LN

Vee

TEA1067

TEA1067

Voo

DTMF

OTMF

MUTE

M

PO

-.,.-I

PC03310

FL

I

TELEPHONE
LINE

I

____________ ..JI
NOTE:
The dashed lines show an optional flash (register recall by timed loop break).

a. DTMF-Pulse Set With CMOS-Bilingual Dialing Circuit PCD3310

Vee

voo

DTMF

TEA1067

MUTE
PO

VEE

M

PCD3320
FAMILY

DP
Vss

TELEPHONE
LINE

0

b. Pulse Dial Set With One of the PCD3320 Family of CMOS Interrupted Current-Loop Dialing Circuits

Voo
DTMF

TEA1067

MUTE
PD

VEE

M

PCD3343

DPIFL
Vss

TELEPHONE
LINE

,'e
DTMF

PCD3312

NOTE:
Supply is provided by the TEA 1080 supply circuit.

c. Dual-Standard (Pulse and DTMF) Feature Phone With the PCD334~ CMOS Telephone Controller
and the PCD3312 CMOS DTMF General With I C Bus
Figure 9. Typical Applications of the TEA 1067 (Simplified)

December 2, 1986

6-87

Signetics

AN1942
Application of the Low Voltage
Versatile Transmission Circuit
Application Note

Linear Products

INTRODUCTION
The TEAl OB7 is a speech/transmission circuit for analog telephone sets. It has been
developed to fulfill requirements for the North
American Telephony specifications. The circuit enables parallel operation with classical
telephone sets.
Additional features of the TEAl OB7 are as
follows:
• High-ohmic microphone inputs and high
gain microphone amplifier which can be
adapted to every type of microphone.
• Improved receiving amplifier (high gain;
low noise).
• Lower DC voltage in the normal
operating range (IUNE > 11 mAl. Meets
USA DC requirement BV at 20mA
(RS470) with a normal diode bridge
having lAV voltage drop.
The circuit permits fully electronic telephone
sets to be designed for virtually any kind of
speech transducer and set-impedance. Although the IC has been designed primarily for
the increasingly-used common-line interface
systems (with internal electronic switching
between dialing and speech condition), it is
also suitable for systems with separated
speech and dialing parts (with a two-wire
connection between the dialing part in the
base and the speech part in the handset). It
can be used with either complex or real setimpedances in either the special anti-sidetone bridge or the Wheatstone bridge configuration. All the interface functions between
microphone and earphone transducers, the
telephone line, and the dialing circuits are
incorporated on-chip.
A supply connection with limited current (because of the low voltage drop across the
circuit) for peripherals is provided. The supply
possibilities can be extended considerably by
means of a special supply IC TEAl 080, or
more simply by setting the line voltage to a
higher value "by means of an external resistor.
Some alternatives to increase the supply
possibilities are given. Also, a straight-forward
design procedure is given to be able to adjust
all necessary parameters in the most convenient order (Appendix 1).

February 1987

DESCRIPTION OF THE CIRCUIT
Block Diagram
The block diagram of the TEAl OB7 is shown
in Figure 2. The internal functions are as
follows:
• Voltage regulator with low voltage drop and
adjustable static resistance. The voltage
drop can be adjusted externally by approximately plus or minus O.BV.

GAS"

REG

QR-

Vee

QR+

PD

• Low DC operating voltage; down to an
absolute minimum of typical I.BV excluding
the polarity guard.

IR

STAB

• Supply connection for driving peripheral
circuits. The capabilities of the supply depend on the DC voltage setting of the
voltage regulator, on external components,
and on the available line current.

~~

• Microphone amplifier with adjustable gain,
and frequency roll-off with adjustable cutoff frequency.

4
5
6
7

e

SYMBOL
LN
GAS1
GAS2
QR-

QR+
GAR

MIC-

10

MIC+
STAB
VEE

11

IR

12

PO
OTMF
MUTE
Vee
REG

16
17

AGe

• DTMF input

18

SLPE

• Earpiece amplifier with two complementary
outputs suitable for magnetic, dynamic, or
piezoelectric earpieces. It has a large gain
setting range and adjustable cut-off frequency.
• Line loss compensation facility dependent
on line current for microphone and earpiece amplifiers. The DTMF amplifier is not
affected by this facility. The control curve
has been optimized for BOOn feeding
bridge and is adaptable for various exchange supply voltages.
• Mute input to inhibit the microphone and
earpiece amplifier during dialing and to
enable the DTMF input and confidencetone.

6-88

'--_---I,

VEE

TOP VIEW

• High-impedance symmetrical microphone
inputs suitable for dynamic, magnetic, and
piezoelectric microphones. Electret microphones with a source-follower or preamplifier can be connected in asymmetrical
mode.

• Confidence tone in the earpiece during
DTMF dialing.

MUTE
DTMF

9

13
14
15

DESCRIPTION

Positive line terminal
Gain adjustment; transmitting amplifier
Gain adjustment; transmitting amplifier
Inverting output; receiving amplifier
Non-inverting output; receiving amplifier
Gain adjustment; receiving amplifier
Inverting microphone input
Non-inverting microphone input
Current stabilizer
Negative line terminal
Receiving amplifier input
Power-down input
Dual-tone multi-frequency input
Mute input
Positive supply decoupling
Voltage regulator decoupling
Automatic gain control input
Slope (DC resistance) adjustment

Figure 1. Pin Configuration
• Power-down input to minimize the internal
supply current of the IC during line interrupts, for example: during pulse dialing or
register recall (flash). The voltage regulator
capacitor is disconnected to prevent startup delays after line interruptions so as to
minimize the contribution of the IC to the
shape of the current pulses during pulse
dialing.
The anti-sidetone circuit is implemented outside the IC by means of discrete components
and allows maximum flexibility of circuit design.
The pinning is shown in Figure 1 together with
a list of the pin functions. These abbreviations
are used throughout the chapters that follow.
Figure 3 shows the basic application diagram.

Signetics Linear Products

Application Note

Application of the Low Voltage Versatile Transmission Circuit

11

tRo-i---------t-----------------i

AN1942

,------------+-+~ GAR

1---+-+--0 QR+
1---+-+--0 QR-

MtC. O-i---------t------------i----i

,-------+-+--0 GAS,

MtC- o-+--------t------------i--t--I

oTMF

13

0-+---------1----1

L----i--I-~

GAS,

14
MUTEo-i---------t------------t-------------------~

PO

12
0-+_-1

•
10

VEE

18

REG

AGC

STAB

Figure 2. Block Diagram

February 1987

6·89

SLPE

Signetics Linear Products

Application Note

Application of the low Voltage Versatile Transmission Circuit

AN1942

Rl

620
Cl

R2
130K

RIO

100~F

IS
LN

CS

13

11

Vee

+

IR

100nF

QRDTMF

13
FROM
DIAL
AND
CONTROL
CIRCUITS

QR+
C.

TEA1067

100pF

MUTE

I.

GAR
PO

r-T-:-;==~=----~M'C+

12

RVA{16-18)

r-_..J>.,10,,4-r-_,

'--------'-IMIC.

I

$LPE

I

GAS1

181

GAS2

3

_oJ

R8

I
I

REG

I

L_

STAB

AGC

16

17

VEE

9

10

R7

390

+ C3
4.7p.F

C6

R5
3.SK

R6

ZBAl

R9

100 pF

201l

NOTE:
The Zener between Pin 1 and Pin 18 is optional and can be used to obtain symmectrical clipping of the sending signal.

Figure 3. Basic Application Diagram

Supply Considerations
Supply and Set Impedance
The IC is supplied with current from the
telephone line; the general supply arrangement is shown in Figure 4. The equivalent
impedance of the circuit is shown in Figure 5.
The artificial inductor LEO = Rp'Rg'C3

RL.INE

R1

'LINE

-I
15
R EXCH

With Rg =20.11

LN

TEA1067

I

vee

lo.smA
AC

C1

Rp = 16.2kQ (internal resistor;
tolerance ± 20%)

= 1.52H.

C3 not only influences the value of LEO, but
also determines start-up time of the DC
voltage regulator. The value of C3 has been
chosen to give optimum start up time of the
circuit. This means that the voltage regulator
starts up after the smoothing capacitor at Vec
has been charged.

February 19B7

1

DC

C3 = 4.7J.lF

This results in a typical LEQ

lice

lee

'SLPE +O.5mA

V EXCH

REG

STAB

SLPE

VEE

18

10

' SlPE

C3

R5

R9

PERIPHERAL
CIRCUITS

i

I
I

~-_ _-4_~____~__~_ _~~_J

Figure 4. Supply Arrangement

6-90

Signetics Linear Products

Application Note

Application of the Low Voltage Versatile Transmission Circuit

ur-----,------r-----,

LNo---t---t----,

10 1------+-----+---IRg(Q)

R1

R,

LEQ ... ~.Rp.~

VREF

REG

Vee

R.

C1
100,.

20

V~o---4---4---'

Figure 5. Equivalent Impedance
A different value for LEQ can be obtained
either by changing Ca (taking into account a
different start-up time) or, although not recommended, by changing the value of Rg. The
latter has influence on several parameters;
this will be discussed later.
In the audio frequency range, the impedance
of the whole circuit is determined by R or,
"
more exactly, by the value of R, II Rp.
The network R, C, provides a smoothed voltage Vcc both for the IC itself (typical
Icc = 1mA at Vcc = 2.BV) and also for the
peripheral circuits (lp). Typical Icc versus Vcc
is shown in Figure 6; normal operating condition and power down condition are shown.
1.5

.ili
...
'"
.

IC~

:l

oS

0:
0:

/"

1.0

/

::>
0

~

.......... V

::>

z~

V ......

0.5

......- i-'A
.......... ,.....a

l.----icc x10-

0:

15

150

50
ILlNE(mA)

Figure 7. DC Characteristics
With line currents in excess of ITH' the voltage
drop across the integrated circuit is VLN,
where

in which VREF

= internal reference voltage

of 3.6V
ISLPE = IUNE -Icc -O.SmA -Ip
ITH = threshold current low
voltage part (typ. 9mA)
The internal reference voltage is temperature-compensated, giving a low temperature
coefficient of the line voltage VLN; typically
about -1mV/k at IUNE = 1SmA.
Normally ISLPE}>lcc+ O.SmA + Ip, which
means that the equivalent circuit for DC
conditions, where IUNE exceeds the threshold
current ITH' equals that of a 3.6V regulator
diode in series with a resistor Rg (see Figure
S).

~

o

o

3

AN1942

The typical DC voltage VLN is shown in Figure
7 as a function of line current. The slope of
the graph is determined by Rg.
Changing Rg - Note that Rg also shifts the
low-voltage threshold current ITH. Furthermore, Rg determines microphone gain and
DTMF gain, shifts the gain-control characteristic and, in case its value exceeds 30n, it
decreases the maximum output swing on LN
(especially at high line currents and high
ambient temperature). Also, the sidetone will
be affected because Rg is a branch of the
anti-sidetone bridge; the bridge must be rebalanced if its value is changed. The preferred value of Rg is 20n and this value is
used in the basic application circuit as described in this report. However, choosing
another value for Rg can sometimes be
necessary, e.g., to rebalance the anti-sidetone circuit when a set impedance different
from 600n is chosen.
Increasing DC Slope
Increasing the slope of the DC characteristic
can be done by inserting a resistor between
Pin 1 (LN) and node [R" R2 , R,0) (Figure 3).
This resistor does not have influence on the
set impedance. However, the maximum output swing on the line is decreased slightly.
Another alternative is simply increasing the
protection resistor R10 (Figure 3).
Adjusting the DC Voltage Drop
If necessary, the voltage drop across the
circuit (V LN) can be increased by means of an
external resistor (RVAI16 -18]) connected between Pin 16 (REG) and Pin 18 (SLPE). In
fact, the external resistor RVA sets the internal reference voltage VREF = VLN-SLPE of the
voltage stabilizer. This resistor causes a
slightly increased spread in the voltage drop
and a slightly different temperature coefficient. With RVAI16-18] = 39kn, Figure 8

5

VeeM
NOTES:
A. Normal operating condition; PO"" Low.
B. Power down condition; PD "" High.

Figure 6. Internal Supply Current
Icc = f(Vce)
Supply of the Integrated Circuit
The direct current which flows into the set is
determined by the exchange supply voltage
(VEXCH), the resistance of the feeding bridge
(REXCH), the DC resistance of the subscriber
line (RUNE) and the DC voltage across the
subscriber set including the polarity guard.
If the line current exceeds the value given by
(Icc + O.SmA + Ip), then the voltage regulator
diverts the excess current through LN (see
Figure 4).

O~~--~~----~~~~------~--~--~
o 39
100
200 INFINITE 200
100 68
RvAI18-18) (1<2)

RvA~-18)(I<2)

NOTE:
With line currents between 11 and 140mA.
DC Voltage: VLN = VLN-SLPE + (IUNE-1 .5mA)A9

Figure 8. Internal Reference Voltage VLN-SLPE vs Resistor RVA
February 1987

6-91

Signetics Linear Products

Application Note

Application of the low Voltage Versatile Transmission Circuit

shows that VREF = 4.2V, resulting in
VLN = 4.5V ± O.3V at IUNE = 15mA.
A decrease in the voltage drop VLN can be
obtained by means of an external resistor
RVA[1 _ 16] connected between Pin 1 (LN) and
Pin 16 (REG). Figure 8 shows that with
RVA[1 -161 = 68kn, VREF = 3.15V, a voltage
drop VLN = 3.4V ± O.3V at IUNE = 15mA is
obtained.
Of course, choosing a modified voltage drop
across the circuit will have influence on several parameters: maximum output swing of
sending and receiving amplifiers and supply
current available for peripherals. Decreasing
the voltage drop by means of RVA[1 -16] will
lower the set impedance slightly.
Parallel Operation
At line currents below the low-voltage threshold current ITH (typically 9mA), the internal
reference voltage is automatically adjusted to
a lower value. At 1mA a typical voltage drop
of 1.6V is obtained. This means that the
operation of the circuit with more telephone
sets in parallel is possible with line voltages
down to an absolute minimum of typically

,,/'

Vcc~2.9V

V

swing in the low-voltage range. Furthermore,
the supply point for peripherals is degraded.
2.5

....... ""1\ A) MUTE

·....· ....f\

N" ..... Ar4 t r

r-rrr ~'\N)'

m 2

.. - . B)0.8mA,2.5V

0.5

\. .Al0.s5mA.2.9V

1.5

I I
... )0.1mA,2.9'
3.0 3.5
4.0

2.5

2.0

Vcc(V)

NOTES:
-Speech Condition: VLN "" 1.4VAMS (d

< 2%)

VQR+ "'" 150mV across 150n

single ended load (d
-Mute Condition: VLN =

< 2%)

WRMS

Figure 9. Typical Current Icc
Available From Vcc at ILiNE = 15mA;
VLN = 3.9V; T A = 25°C
1.6V. Of course, the sending and receiving

amplifiers have reduced gain and output

V

II r---.- t;--...

.LE·

:'

Vcc ):2.2V

..

.-Vcc >2.2V

............

.../

...........

..../
o

o

o

20

40

80

80

100 120 140

o

.

../

20

vcc ):2.9V

40

80

80

100 120 140

IUNE{mA)

ILlNE(mA)

Figure 10. Typical Current Icc and Corresponding Vcc vs Line Current in
Speech Condition. Signal Conditions as in Figure 9

/'

~~

r

,,/'

V~>2.2~

V

-

/
,/

I--Vcc~2.2V

o

o

__
40 80

OL-~~

20

40

80

80

IUNE(mA)

100

120

140

o

20

~-L

__~~~

80

100 120 140

luNE(mA)

Figure 11. Typical Current Icc and Corresponding Vcc vs Line Current in Mute
Condition; Signal Conditions as in Figure 9
February 1987

AN1942

6-92

Supply to Peripheral Circuits
The voltage available at Pin 15 (Vcd can be
used to supply peripheral circuits such as
pulse dialer, DTMF dialer, or a microcomputer
with its own peripherals; an electret microphone with a source-follower or preamplifier
can also be powered from Vcc.
However, the current Icc and the voltage Vcc
which are available from the circuit in the
basic application (Figure 3) are limited and
are dependent on the values of external
components of the IC and on the actually
available line current. Figure 9 shows the
typical available current Icc versus Vee at a
line current of 15mA. The typical available
current and the corresponding voltage Vee as
a function of line current are shown in Figure
10 for the speech condition and in Figure 11
for the mute condition; parameters are the
same as in Figure 9.
It is shown clearly that the lowest power is
available at minimum line current. At higher
values of line current, the typical values of
available Icc and Vcc are both increased.
The limit on Icc is then imposed by the
requirement to maintain at least the minimum
permitted voltage between Pin 15 (V cd and
Pin 18 (SLPE) (minimum instantaneous voltage: Vcc - VS LPE ;;' 1.5V). In case this condition is not met, the maximum possible sending level on LN will be limited.
If the assumption is made that 15mA is the
minimum line current under normal operating
conditions, some figures can be given. The
available current Icc is determined by the
minimum supply voltage required for the peripheral circuits. For most CMOS circuits the
minimum supply voltage will be 2.5V. The
typical available current Icc = 1.25mA at
Vcc = 2.5V; worst-case lee> 0.9mA. In
speech condition, the available current depends strongly on the received signal level
because of the class-S receiving amplifier
output stage; with an extremely high and
continuous drive of the receiving amplifier,
the available current will be typically 0.8mA.
In practice, however, the receiving amplifier
will not be driven continuously and the available supply current will be higher under normal speech conditions. This means that the
power available from the supply point in the
standard application is sufficient for low-power circuits such as pulse dialers and preamplifiers for electret microphones. Most CMOS
DTMF dialers can be powered under typical
conditions; however, under worst-case conditions of both TEA 1067 and tone dialer, the
available power may not be sufficient.
In cases where a battery is used for memory
retaining, an enable diode will become necessary between V cc and the power pin of the

Signetics Linear Products

Application Note

Application of the low Voltage Versatile Transmission Circuit

.------+

. - - - - -.... +

--«

AlB

AlB 0 - -.....

B/Ao-------l------'

B/Ao--~----_t----~

NOTES:
a. 4~Diode Solution typo O.5V Less Drop
b. 6-Diode Solution typo 1V Less Drop

Figure 12. Schottky Diode Polarity Guard With Protection Giving Less Voltage
Drop Than a Normal 1.4V Polarity Guard

..... .....,
~.

2.5

~

1

,\~.~~ UJ2.~V

....... .....

••.

B)SPEEC~\
1.5

I I I I

1\ ...

... B)1.7mA,2.5V

\.\- • A)1.45mA, 2.9V

jl

r\.

I I I

B) 1 mA, 2.9V

r\ "

0.5

\\
1.5

2.5

3.5

T
1

4

Vcc(V)

NOTE:
Signal conditions as in Figure 9.

Figure 13. Typical Current Icc
Available From Vcc at ILiNE 15mA
With Increased Line Voltage by
Means of RVA[16.l8] 39kn

=

=

peripheral circuit to prevent discharge of the
battery. Taking into account a voltage drop
for a Schottky enable diode (BAT85:
VF < 0.32V at 25'C and 1rnA), the minimum
value of Vcc we need is about 2.9V. This
results in a typical available current of
0.55mA in mute condition (worst case
Ip ~ 0.2mA). This is not sufficient to power a
microcontroller and a DTMF dialer (e.g.,
PCD3315 and PCD3312) simultaneously.
Several possibilities to improve the supply of
the TEAl 067 are given in the following paragraph. In AN1943 a separate overview is
given to solve the supply problem of
TEA 1067 and still meet the RS470 requirements at the same time.
Extending the Supply Possibilities
Several methods exist to extend the supply
possibilities. All of them have advantages and
also disadvantages. These methods are discussed below.
Increasing the Line Voltage - In cases
where this is allowed, the supply problems
can be overcome simply by setting the volt-

\

\

100

200

LN

"-

........

300

400

...........

=3.9 V

r--- r-r-- r--

500

600

Compromise Between Set Impedance and
Supply - The TEAl 067 gives a very good
balance return loss (BRL) with respect to a
600n reference impedance. In cases where
the margin with respect to the requirements
for BRL is rather high, it is possible to reduce
the AC set impedance to such a value that
the BRL requirement still is fulfilled safely. In
this way a considerable increase of the supply possibilities is obtained.
Figure 14 shows the typical available supply
current with Vee = 2.9V and Vee = 2.5V as a
function of Rl in mute condition with
IUNE = 15mA and VLN = 3.9V. Furthermore,
Figure 15 shows the measured BRL-figures at

sJoHz

~~

20

-

700

R,(Q)

600

10

/

I

I) ~ ~

o

o

200

400

600

600

R,(Q)

Figure 14. Typical Supply Current Icc as a Function of the
Supply Resistor Rl (in Mute Condition)
February 1987

An alternative way to meet the requirements
of RS470 is to increase the line voltage into
the conditionally acceptable region at the
moments when this is allowed. The voltage is
switched back into the acceptable region in
those cases where this is required; e.g.,
during pulse-dialing and during the hook-on to
hook-off transition. This is described extensively in AN1943.

.If\.

'" ""
o

Increasing the voltage drop across the circuit
can be obtained by means of an external
resistor RVA[16-1S]. With RVAI16-1S] = 39kn
the typical available Icc and Vee are shown in
Figure 13 with VLN ~ 4.45V and
IUNE = 15mA. Taking into account the spread
on the voltage drop VLN, it can be calculated
that the minimum available power is
Ice ~ 1.1mA at Vce = 2.9V and 1.75mA at
Vee = 2.5V in mute condition.

~INE=15mA

~ .........

o

age drop across the circuit to a higher value .
Of course, the line voltage is also increased
then. If a higher line voltage is not allowed
(e.g., requirement RS470), this can be corrected in sets with DTMF dialing only (without
flash) by using a polarity guard with Schottky
diodes resulting in a lower voltage drop
across the polarity guard. This is shown in
Figure 12. More information can be found in
AN1943.

30

\Vcd~2.5V
~cc~2.9V

AN1942

6·93

Figure 15. Balance Return Loss as a
Function of Rl

•

Signetics Linear Products

Application Note

Application of the Low Voltage Versatile Transmission Circuit

300Hz, at SOOHz, and at 3400Hz as a function
of R,.

small correction factor (normally around 1dB)
for the total DTMF gain is introduced.

Note that lowering of R, will have influence
also on sending gain (microphone and DTMF),
on the maximum possible sending signal on the
line at low line currents, and on the balancing of
the anti-sidetone bridge. The sending gain normally can be corrected easily. The following
section on Anti-Sidetone Circuits shows how
the anti-sidetone bridge can be rebalanced by
decreasing Rg or R2.

Inductor In Parallel With R, - If the above
described methods cannot be used, a supply
arrangement as shown in Figure 17 is possible. An inductor in parallel with R, extends
the supply possibilities. The value of this
inductor must be more than 2.5H in order not
to influence the BRL-figures much. In practice
a BRL;;' 20dB at f = 500Hz can be realized.
The maximum series resistance of the inductor depends on the maximum current Ip and
the minimum required voltage Vee. For example, with Vee;;' 3.5V and Ip;;' 3mA, the maximum series resistance of the inductor is
RL = 180n. However, to avoid the need for
an excessively large and expensive inductor,
an electronic solution is more favourable for
currents Ip in excess of about 3mA. Also, for
currents less than 3mA an electronic solution
can be used in case a discrete inductor is not
desirable.

RC Smoothing Filter Between LN and
SLPE - For relatively small supply currents,
an RC filter between Pin 1 (LN) and Pin 18
(SLPE) can be used to power peripherals. An
advantage of this method is that the internally-generated reference voltage is used, which
is rather constant (temperature compensated) and has a relatively low spread. Furthermore, no influence is to be expected on setimpedance (BRL), sending gain, and on the
gain control characteristics.
This configuration is shown in Figure 16. With
RL1 = 300n, CRL = 220j.lF and IRL = 2mA,
the supply voltage across the peripheral load
RL2 measures about 3V ± 0.2SV.
A disadvantage is that a higher line current is
necessary for the same output swing of the
transmit output stage on the line, because of
the dissipation of the AC signal in RL"
Furthermore, a problem is that the TEAl 067
and the peripherals do not have a common
reference. The reference used for the peripherals is SLPE; the TEA 1067 reference is VEE.
This means that level shifters are necessary
between the logical inputs Pin 14 (MUTE) and
Pin 12 (PD) of the TEAl 067, and the logical
outputs of the peripheral IC's. Furthermore, a

Electronic Inductor - The TEA 1080 special
supply circuit comprising an artificial inductor
(about 10H) can be used in combination with
the TEA 1067 to extend the supply possibilities to very high values, depending on the
available line current and line voltage. This
combination is very suitable for listen-in and
handsfree applications where a relatively
large power is needed.
In this report two possible combinations of
TEA 1060 and TEAl 080 are described; the
TEA 1080 is either connected between LN
and the common reference VEE or between
LN and a different reference SLPE. Both
methods have their own merits.
An electronic inductor can also be realized by
means of off-the-shelf components (e.g., op

Icc

IRL

Ie

IUNE

-~l

Rp
RL1

I

VRL

I

CRL
R7

C3
5LPE

YE

RL2

I
I

____ J

R1

Ze,NE

vee

C1

VEXCH

R9
VEE

Figure 16, Equivalent Circuit Diagram of the Transmit/DC Regulator Stage of the
TEA1067 With Supply Part Connected Between LN
February 1987

6-94

AN1942

amp TCA520 + 3 resistors + 2 capacitors + 2
transistors + 1 diode); this is shown in Figure
18.
Parallel Operation With a Classical Set In case a classical telephone set is connected in parallel with the TEAl 060/61 /66T /68
on a loop with low line current, the line
voltage will drop below the zener voltage of
the voltage stabilizer of the transmission
circuil. For example, with a 200n classical set
on a 20mA loop the line voltage will drop to
about 3.8V; this means that the voltage inside
the polarity guard will be about 2.6V. The
TEAl 067, however, automatically decreases
its zener voltage in case the current coming
from the line drops below the threshold
current ITH (typ. 9mA). This means that the
transmit output stage will operate down to
very low voltages. For example, with the
200n classical set connected in parallel to a
TEA1067 with 20mA available line current,
the line voltage will drop to 3.2V leaving 4mA
of line current for the TEA 1067 at a voltage of
2V at the power pin of the TEAl 067 inside
the polarity guard. We assumed that the
current used for the peripherals can be neglected at such a low voltage (Vee has a
value around 1.6V); this means that in sets
containing a microcontroller and battery, the
controller will run on the battery; in basic tone
dial sets the DTMF dialer will be in an
unspecified condition and normally this is a
low-power stand-by condition as long as no
key is pressed. In case a key is pressed,
normally distorted dial tones are generated.
In sets where peripherals are connected to
Vee that also consume current under lowvoltage conditions, this will cause worse performance of the TEAl 067 during parallel
operation under minimum conditions, unless
the peripherals are switched into a low-power
condition in case the line voltage drops below
a predetermined val~.e,.

Microphone Amplifier
The TEAl 067 has symmetrical high impedance microphone inputs. The input impedance is typically 64kn (2 X 32kn) with tolerances of ± 20%. With this high input impedance it is possible to determine the matching
of several microphone types very accurately
by means of external components. The circuit
is suitable for dynamic, magnetic, or piezoelectric microphones with symmetrical drive;
electret microphones with built-in source follower or preamplifier can be used in asymmetrical mode.
To obtain optimum noise performance, the
microphone inputs must be loaded. The
equivalent noise-voltage (psophometrically
weighted; P53-curve) at the microphone input
is typically 0.65j.lV(RMS)P with 8.2kn across
the microphone inputs. With 200n across the

Signetics Linear Products

Application Note

Application of the Low Voltage Versatile Transmission Circuit

R1

----,

RI = R1 II 16.2kn, the dynamic impedance of
the circuit RL = load resistance at LN
during the measurement; normally
600.11.
rD

= dynamic resistance of the internal circuit-

Rs

= 3.65kn; fixed external resistor determin-

ry (3.47kn)

I
I
I

6

TEA1067

TELEPHONE
LINE

C1
STAB

SLPE

PERIPHERAL
CIRCUITS

y

VEE

I
I
I
L--_---<>-------'-_--'-_~--~---..J
C3

R5

R9

Figure 17. Increased Supply Capability by Means
of an Inductor in Parallel With R1

R61
68k
C62

33pF

R63
15

R1
620

LN
TEA1067

Figure 18. Circuit Diagram of an Electronic Inductor Realized
With Off-the-Shelf Components
inputs. the equivalent noise at the input
measures typically 0.45IN(RMS)P'
The internal microphone preamplifier accepts
signals up to 17mVRMS for a 2% level of total
harmonic distortion (dTOT = 2%) because of
the internal soft limiting. This means that the
minimum possible gain of the microphone
amplifier measured between the inputs and
the line is 44dB with Clipping of the line signal
being determined fully by the transmit output
stage. In case a lower gain is necessary, the
input Signal must be attenuated before entering the preamplifier; otherwise, the input
stage will be overloaded and cause extra
distortion (soft clipping) of the line signal. The
arrangements with several microphone types
are shown in Figure 19.
February 1987

In case asymmetrical drive of the microphone
inputs is used, care should be taken that both
inputs MIC+ and MIC- see equal impedances to the common; otherwise, residual line
Signals present on the supply point (Vecl will
cause inaccuracy in gain, and sometimes
(with a large DC-blocking capacitor connected to MIC-) even low-frequency hicking (motorboating) may occur.
The gain of the microphone amplifier is given
by the following equation (see Figure 3):

AN1942

ing the current in an internal current
stabilizer.
If, for a practical circuit such as shown in
Figure 3, we insert in the above equation the
following realistic values: R7 = 68.1 kn,
Rs = 3.65kn, Rg = 20.11, R1 = 620.11, and
RL = 600.11, then: 2010gAm = 52 ± 1dB.
For various microphone sensitivities, the gain
can be set between 44dB and 52dB by
means of R7; this takes values between 25kn
and 68.1 kn . The microphone gain is shown
as a function of R7 in Figure 20. An amplification of more than 52dB is possible (up to a
maximum of 60dB); however, in that case the
minimum specified DC voltage of VLN at
11 mA (VLN;;' 3.55V) cannot be guaranteed
any more. Also, the specified DC voltages at
7mA and 4mA will show more spread. This is
caused by the internal offset voltage of the
microphone input stage, which causes an
offset onto the low-voltage threshold current
of the DC characteristic. The effect of this
offset depends on the microphone gain that
has been set by means of R7. With a microphone gain of 52dB (R7 = 68.1 kn) and a
standard deviation (sigma) of the offset voltage of the input stage of ± 0.5mV, it can be
calculated that the threshold current ITH is
between about 7 and 11 mA (3'sigma). The
DC voltage at 11 mA is specified to guarantee
that the DC voltage in the normal operating
range (ILiNE > 11 mAl is not influenced by this
spread with a microphone gain of 52dB.
It will be clear that any different choice of Rg
(static resistance of the DC characteristic) will
directly influence the gain of the transmitting
channel. The value of Rg also has influence
on the DC characteristic (slope, ITH), the gain
control characteristic, and on the maximum
output swing on the output pin LN. Also, the
balancing of the anti-sidetone circuit will be
affected, necessitating rebalancing of the
bridge.
The value used in the basic application diagram is 20.11. If this value is to be changed,
the consequences should be considered
carefully and the design procedure as given in
Appendix 1 must be followed.

Am = 1.356 X R7 + rD X
RI RL
Rs Rg
RI + RL

In case the line current is sufficient, clipping
of the output Signal at Pin 1 (LN) normally
happens when the internal output transistor
saturates:

where,

(VLN - VSLPE

6-95

= 0.9V).

Signetics Linear Products

Application Note

Application of the Low Voltage Versatile Transmission Circuit

AN1942

.....M,-----'i MIC +

r--~--':~MIC+

.....>1\1\.._--"-1 MIC-

L-.-"'--':~MIC-

NOTE:
The resister marked (1) may be connected to lower
the terminating impedance.

a. Magnetic or Dynamic Microphone

b. Electret Microphone

c: Piezoelectric Microphone

Figure 19. Alternative Microphone Arrangements
gives f3dB = 23kHz with R7 = 68.1 kO and
C6 = 100pF.

54 , . - - , -......T"T"T'TT=ccrTTT1 27.5
52 .....

JLEJNdE±lld~L .•.Rg~
,20

25.5

5Oi--i-+-++-HI+-bfHftttltl23.5
48
21.5
./
III
6f
6f 48 i--I-+-+-I7'H-I7'f+Io'FI-:39
19.5 ~

1----+-H-+-H4-t-t.J.1fi-~

~

44

17.5

42 i--I-+-+>+-b'F-+++++ItttltllS.5
40

13.5

38

11.5

.!

Parallel Operation
In case of parallel operation of sets, the
operating voltage of the TEAl 067 can drop

below the internal reference voltage and the
circuit automatically adjusts this voltage to a
lower value. Of course, this will have influence on the performance of the microphone
amplifier.

1Or---,---,---,---,----r-----,---,a5
-::::::---..... ~
....••••• d=2%

38 '-_"---'--'-....I.."-'-'-.L..I.,",,!.J..UJ.J.J 9.5
10
20
30 40 50 60 : 60 100

~-;::::..--

.... .. .....

88.11c2

2.5

.... -"

~ ~-

Figure 20. Microphone Gain and DTMF
Gain as Function of R7

-

2

-

1.5

-

1

....

l

J

0.5

oL-__-L____L-__

This means that the sine wave clips at the
bottom. The top of the sine wave can only be
clipped by the zener diode at Pin 1 (LN) or by
lack of collector current in the output transistor (low line current).

In Figure 21 the maximum output swing of the
transmit output stage is shown as a function
of the DC line voltage VLN at IUNE = 15mA.

Stability and Frequency Roil-off.
The 1OOpF external capacitor C6 connected
between GAS 1 and SLPE is necessary for
ensuring the stability of the transmitting amplifier. Larger values can be applied, and
these will then operate as a first-order lowpass filter, for which the cut-off frequency is
determined by the time constant R7C6 . This
February 1987

____

~

__

~

____

~

__

~

2

Figure 21. Maximum Output Swing Transmit Output Stage as a
Function of DC Voltage VLN (I LINE '" 15mA)

At low line currents. the top part of the output
sine wave is clipped because the output
stage runs out of current.
In case of sufficient line current. symmetrical
clipping at the line output LN can be obtained
by using a 6.8V zener diode between LN (Pin
1) and SLPE (Pin 18) of the TEA 1067 (Figure
3).

~

2.5
d=10%

2

./

....

l

/'"

......

/ _ .......

.................

d=2%

1.5

J

...1
'V/........··
h

0.5

.,/

o'

10<"'"

0
0

15

20

Figure 22. Maximum Output Voltage of the Transmitting Output Stage vs
ILiNE In Low Line Current Range

6·96

Signetics Linear Products

Application Note

Application of the low Voltage Versatile Transmission Circuit

In Figure 22 the maximum output voltage at
Pin 1 (LN) is shown with a 3000. AC load (the
resistor determining the set impedance
R1 = soon is in parallel with the 3000.) as a
function of line current that is actually flowing
into the TEA10S7. This represents one telephone set with a SOon AC impedance being
connected in parallel with the TEA 1OS7
(SOOn load representing the telephone line
being already present). Transmit gain is 52dB
in case of a normal soon load; however, with
a soon set in parallel, gain decreases with
about 3.5dB. The maximum output swing is
not determined by the DC voltage at Pin 1,
but by the available current in the output
stage of the TEA 1OS7.

of Figure 3 with a 100llF, 25V capacitor. The
following typical values with respect to 25°C
were found:

+s

I

Ii>
~ ~1__--~--~___1~~~~--~

Figure 28 shows the receive gain as a function of the DC line voltage VLN. Gain decrease starts at about VLN = 3V; at VLN = 2V,
the gain has been decreased by about 13dB.
The results are valid for a typical sample in
the basic application circuit of Figure 3.
Changing components will have influence on
the results.

Confidence Tone
During DTMF dialing, the dialing tones can be
heard at a low level in the earpiece. The level

6-98

Figure 27. Maximum Output Swing
Receiving Amplifier vs
VLN in Low Voltage Range
of the tones at the receiving output depends
on the gain that has been set for the receiving

Signetics Linear Products

Application Note

Application of the Low Voltage Versatile Transmission Circuit

+5

~ \~~.

-1

iii"
~

(

iii"
} -5

50:

...z

1
rJ

"

/

-20

-6

\

10

20

40

30

~
"- "v,

-1

36V,

&i'

~

-2

...z

-3

Below a specific value of line current,
ILlNE.START, the gain is equal to the values
calculated with the formulas given before. If
the current ILiNE-START is exceeded, the gain
of both of the controlled amplifiers decreases
as a function of increasing DC line current.
Gain control stops when another value of line
current (ILiNE-STOP) is exceeded. The gain
control range of both amplifiers is typically
6dB. This corresponds with a line length of
5km of 0.5mm diameter copper twisted-pair
cable with a DC resistance of 176!Ukm and
an average AC attenuation of 1.2dB/km. The
slope of the gain control characteristic has
been chosen to give an optimum tracking
between the line attenuation and the required
amplifier gain (typical error';; O.BdB) for a
system with a 2 X 300n feeding bridge. In
case lines with different parameters are used,
February 1987

--

o

80

70

90

z
:;: -4

"

-5
-8

.~VEXCHANGE

,,

'-

,
'~ '-', ~
j'k'\ , 14Or""~

0

When the resistor R6 is connected between
AGC and VEE, line current·dependent gain
control of both the microphone amplifier and
the receiving amplifier becomes operative;
the DTMF amplifier is not affected.

80

GAIN CONTROL
- - CABLE LENGTH

,,~

0:

0

The gain figures of the microphone amplifier
and the receiving amplifier which was derived
in the preceding chapters are applicable only
when the AGC is inoperative: that is, with Pin
17 (AGC) not connected (open circuit).

50

Figure 29. Gain Control Characteristics; 600n Feeding Bridge

0

Line Current-Dependent Gain
Control

-

1\', '~~
o

amplifier, and on the tone level applied to the
DTMF input.

in which AT is a general term for telephone
gain and this can be replaced by either ATA
(single·ended drive) or ATS (symmetrical
drive). This is shown in Figure 24.

-

'\

ILlNE(mA)

Figure 28. Typical Receive Gain vs
VLN in Low Voltage Range

20 10gACT ~ 2010gAT - 50dB

-

78r'~ "~r\ ~.

v",(V)

The gain ACT between the DTMF input and
the receiving output is given by:

-

~

,\ '

-5

1

\

\

z
:;: -4

-10
-15

\\

-3

0
0

_ GAIN CONTROL
- - CABLE LENGTH

I
VEXCHANGE

'\. I~

-2

AN1942

o

10

20

30

40

"'\ "'1"---

50

80

-

"',---

70

Ro

-

80

o
90

Figure 30. Gain Control Characteristics; 400n Feeding Bridge
a small additional tracking error will be introduced.

the typical tracking error that can be expected
is';; 1.2dB.

Correction for Exchange Supply Voltage
The value of resistor R6 must be chosen in
accordance with the supply voltage in the
exchange. In Figure 29 the control curves are
shown for VEXCH ~ 36V and 4BV with a feeding bridge resistance of 2 X 300n.

Figure 30 shows the control curves for a
400n feeding bridge with exchange supply
voltages of 36V and 48V. Figure 31 shows
the characteristics for an BOOn bridge of 4BV
and SOY. In Figure 32, the results for a 1kn
bridge are shown at the same voltages.

Also, the calculated relationship between line
length and line current is shown in Figure 29.
These ideal curves have been calculated with
the assumption that an increased voltage
drop across the circuit has been set
(VLN ~ 4.45V at 15mA; RVAI16 -18] ~ 39kn)
and assuming a polarity guard with 1.4V
voltage drop. Other parameters will give
slightly different results, giving slightly different optimum values for R6.

The optimum values of R6 for the various
values of exchange supply voltage and exchange feeding bridge resistance, with a 1.4V
diode bridge, Rg ~ 20n, and increased line
voltage VLN ~ 4.45V at 15mA (RVAI16-18j
~ 39kn) are given in Table 1.

Correction for Feeding Bridge
Resistance
If the feeding bridge in the exchange has a
resistance other than 600n, R6 must be
adjusted. This will introduce a minor increase
in tracking error because the slope of the gain
control curve has been optimized for a 600n
feeding bridge. With a 1000n feeding bridge,

6-99

In case a value for Rg is used different from
20n, the value for R6 must be adapted.

II
I

Signetics Linear Products

Application Note

Application of the Low Voltage Versatile Transmission Circuit

AN1942

Table 1
REXCH

-,

400

600

36

100

78.7

48

140

110

60

-51--+--+-

1000

800

Rs (knl with R9

VEXCH(Vl

= 20n
93.1

82

120

102

NOTES:
,. VLN - 4.45V at IUNE -,5mA; RVA['6.'8]- 39k
2. In case a value for Rg is used different from 20n the value for R6 must be adapted.

-6~~--L-~-~~~~O
W
~
~
M
00

ro

IUNE(mA)

Figure 31. Gain Control Characteristics;
BOOn Feeding Bridge

LN

R,

R2

MICROPHONE AMPLIFIER

AND

-,

OUTPUT MAGE

iD
~ -2

E

6

0
a;

...z

8z

3
-3
2

:;: -4

"

L-~

:I:

SLPE

5z

R8

~
w

...
1!"'

R9

ZSAL

__~~~~~~~O

20

~

~

M

00

ro

a. Special TEA 1060 Family Anti-Sidetone Bridge

ILlNE(mA)

Figure 32. Gain Control Characteristics;
1000n Feeding Bridge

LN

MICROPHONE AMPLIFIER
AND
OUTPUT MAGE

Anti-Sidetone Circuit
The anti·sidetone circuit takes care that the
microphone signals available on the line out·
put LN are suppressed sufficiently before
they enter the receiving amplifier input IR.
This is necessary because otherwise these
signals would be reproduced as sidetone with
an unacceptable high level in the telephone
transducer. The anti·sidetone circuit takes the
signal which is available at Pin 18 (SLPE) and
uses it to compensate the microphone signal
at the input IR (Pin 11) of the receiving
amplifier.
The design of the anti-sidetone circuit initially
depends on whether the special TEA 1060family bridge or the more conventional
Wheatstone bridge is to be used. Both structures are shown in Figure 33. For the
TEA1060-family bridge in Figure 33a, the
bridge components are R, II ZUNE, R2, R3,
Ra, Rg, and ZSAl. For the Wheatstone bridge
in Figure 33b, the comparable bridge components are R, II ZUNE, Ra, Rg, RA, and ZSAl·
Both types can be used either with a resistive
set impedance or with a complex set impedFebruary 1987

z..L

R1

SLPE

VEE
R8

+
R9

RA

b. Wheatstone Bridge
Figure 33. Anti-Sidetone Circuits
ance. A brief comparison of both bridge
structures and the two types of set impedance is given in the next paragraphs.

If fixed values are chosen for R" R2, R3, and
Rg, condition 'a' will always be fulfilled provided that IRail ZSAl I~ R3.

TEA1060-Family Bridge
The equivalent circuit of the TEAl 060-family
bridge is shown in Figure 34. Optimum suppression of the sidetone signal is obtained
when the following conditions are fulfilled:

To obtain optimum sidetone suppression,
condition b has to be fulfilled, resulting in:

a. RgR2

= R,

(R3 + [Rail ZSAl])

b. [ZSAl/(ZSAl + Ra)] = [ZLINE/(ZUNE + R,l]

6-100

ZSAl = (Ra/R,)'ZUNE = k'ZUNE
where k is a scale factor: k

= (RalR,)

Scale factor k (in fact the value of Ra) must
be chosen to meet the following criteria:

Application Note

Signetics Linear Products

Application of the Low Voltage Versatile Transmission Circuit

either with a resistive set impedance or with a
complex set impedance.

LN

Furthermore, the attenuation of the bridge for
the received Signal is independent of the
value that has been chosen for ZSAl once the
set impedance has been fixed and condition
'a' is fulfilled. Thus, readjustment of receive
gain is not necessary in many cases.

ZuNE

SLPE

ZeAL

Figure 34. Equivalent Circuit of TEA 1060 Family Anli-Sidetone Bridge
• compatibility with a standard capacitor
from the ES(IlF) or E'2(pF) range for ZSAl
• IZSAlll Ral ..:'R3 necessary to fulfill condition a to ensure correct
operation of the anti-sidetone circuit
• IZSAl + Ral;;' Rg to avoid influence on
microphone gain
In practice ZLiNE varies strongly with the line
length and line type. Consequently, a value
for ZSAl has to be chosen that corresponds
to an average line length giving satisfactory
sidetone suppression with short and long
lines. The suppression further depends on
the accuracy with which ZSAl equals this
average line impedance.
in the basic application of Figure 3, ZSAl has
been optimized for a line length of 5km
0.5mm diameter copper twisted pair with an
average attenuation of 1.2dB/km, a DC resistance of 176[Ukm .and a capacitance of
38nF Ikm. The corresponding impedance can
be approximated by:
Scale factor k has been chosen according to
the criteria mentioned before, resulting in
k = 0.636. So ZSAl and Ra can be calculated
resulting in the following practical values:
R" = 13011, R'2 = 82011, C'2 = 220nF, and
Ra = 39011.
This results in a roughly equal sidetone level
(acoustically measured) at Okm line and with
a 10km line with the line current-dependent
gain control activated. In case no AGC is
1265

2tO

~~

TC19990S

Figure 35. Equivalent Line Impedance
for Optimum Sidetone Suppression

February 1987

AN1942

used, the sidetone has to be optimized for a
shorter line length in order to obtain equal
(acoustical) sidetone levels at Okm and at
10km line length. Of course, overall sidetone
suppression is worse in that case compared
to the situation where AGC is activated. In
practice, normally a compromise is chosen
between loudness of the set and sidetone
level; this means that sending and receiving
gain will be reduced somewhat.
The attenuation of the received line signal
between LN and IR can be derived from:
VIR

RTII R3

VlN

R2 + (RTII R3)

where RT is the input impedance of the
receiving amplifier (typically 20kl1). This attenuation is about 32dB with the basic application as shown in Figure 3. Frequency
dependence of the input attenuation is negligible in the audio frequency range. However,
a frequency roll-off can be obtained by means
of a capacitor connected between IR and VEE
to prevent high frequency components from
entering the receiving amplifier.
Complex Set Impedance
Complex set impedances can be realized by
using a complex network instead of R" and
normally the bridge can be rebalanced by
readjusting the values of Ra and ZSAl, and
either R2 or Rg. Changing Rg also has consequences on other parameters and the range
of possible values is limited. Therefore, the
design procedure as given in Appendix 1
should be considered. Changing R2 has influence on the attenuation of the received signal
between LN and IR; this necessitates a
readjustment of the receiving gain. Note that
changing R, also has influence on the capabilities of the supply for peripherals.
The TEA 1060 family bridge configuration has
the advantage of an almost flat transfer
function in the audio frequency range between LN and the receiving amplifier input IR,

6-101

Disadvantages include the need for a relatively large capacitor (about 200nF) in ZSAl, and
the need for an extra resistor on top of those
required by the Wheatstone bridge. Calculation of new values is also sometimes considered to be more difficult, particularly in case
of complex set impedances.
In some cases, calculating the optimum condition is not very useful because a compromise must be chosen to meet sidetone requirements in several conditions. In those
cases a more practical and probably faster
method is using an empirical method: doing
acoustical measurements and hustling components ZSAl and Ra until the requirements
are met.
Wheatstone Bridge
The conditions in the Wheatstone bridge
(equivalent circuit in Figure 36) for optimum
sidetone suppression are given by:

provided that Ral Rg

>> 1.

Also, for this bridge type a value for ZSAl has
to be chosen that corresponds with an average line length.
The attenuation of the received line Signal
between LN and IR is given by:
VIR

Rail RTII RA

VlN

ZSAl + (Rail RTII RA)

Where RT = input impedance of the receiving
amplifier at IR, typically 20kl1.
A practical circuit could have the following
values: Ra = 82011, R, = 62011, and ZSAl
optimized for the line impedance as shown in
Figure 35. With RA = infinite and a 600n load
at the line, the attenuation varies typically
from about 24dB to 27.5dB over the normal
audio frequency range; the lower attenuation
occurs at the upper frequencies. RA is used
to adjust the bridge attenuation; its value
does not have influence on the balancing of
the bridge.
Complex Set Impedance
If complex set impedances are used with the
Wheatstone bridge, it can be rebalanced by
adapting the values of ZSAl. However, the
frequency dependence of the transfer function between LN and IR will increase.

.~
I

I

Signetics Linear Products

Application Note

Application of the Low Voltage Versatile Transmission Circuit

Capacitor types suitable for high frequencies
must be used, such as ceramic types. In
Figure A 1 they have been added to the basic
application circuil: Cs and Cg at the microphone inputs, C10 at the receiving input IR,
C13 at the supply point Vee, and C11 at the
transmitter output LN. All of the capacitors
are connected to the common VEE.

IR

SlPE

Figure 36. Equivalent Circuit of Wheatstone Bridge Anti-Sidestone Circuit
The Wheatstone bridge offers the advantages of needing one less resistor compared
to the special TEAl 060-family bridge, and
only a small capacitor (about 10nF) is needed
in ZBAl. Furthermore, the values are calculated rather easily with either resistive set impedances or complex set impedances.
Disadvantages are the dependence of the
attenuation of the bridge on the value chosen
for ZBAl, and also the frequency-dependence
of that attenuation. This necessitates a readjustment of the receive gain.

Mute Input
Electronic switching between dialing and
speech can be obtained by controlling the
MUTE input at Pin 14. If a high level (;;' 1.5V,
.;; 15/lA) is applied to the MUTE input, then
both the microphone and receiving amplifier
inputs are inhibited, and the DTMF input is
Simultaneously enabled. The converse situation, with DTMF inhibited and the microphone
and earpiece amplifier both enabled, is obtained by either applying a low-level input
( .;; 0.3V) to MUTE, or by leaving the MUTE
input open. The internal switching takes place
with negligible clicking at the earpiece outputs
and on the line.
If the supply voltage at Vee drops below
Vee = 2V (in the case of no external load at
Vee: VlN < 2.5V and ILiNE < 6mA), the mute
function becomes inoperative and the circuit
will be in a condition where signals applied to
either the microphone inputs or the DTMF
input will be sent onto the line. However,
under these low voltage conditions, only oc·
curring during parallel operation of sets under
worst case conditions, dialing normally will
not take place.

Power-Down Input
The power-down input PD at Pin 12 is available for use in pulse dialing and in register
recall applications, in which the telephone
line is interrupted. During these interrupts, the
telephone set is without continuous power
and the transmission IC and the peripheral
circuits must be supplied by the charge availFebruary 1987

AN1942

able in the smoothing capacitor C1 connected
to Vee (Pin 15) in Figure 3. The discharge
time of this capacitor will be longer in case
the power-down function is used; this results
in less ripple on Vee.
When a high-level input ( ;;. 1.5V, .;; 10/lA) is
applied to the PD pin, the internal supply
current is reduced from about 1mA to typically 55/lA at Vee = 2.8V. Furthermore, the voltage regulator capacitor C3 at REG (Pin 16) is
internally disconnected to prevent it from
being discharged during line interrupts. This
means that after each line interrupt, the
voltage regulator is able to start without delay
at the same DC line voltage as before the
interrupt. This minimizes the contribution of
the IC to the shape of the current pulses
during pulse dialing. Of course, in case of a
highly inductive character of the exchange
feeding bridge, the inductors mainly determine current waveform. Under these conditions, the voltage regulator may show some
switch-on delay because of the active character of the transmission circuit (the exchange
inductors determine the current resulting in
voltage overshoot at the line connection (LN)
of the IC).
In case the voltage drop across the circuit is
increased by means of RVA(16 -lS), the power-down function will be affected. This results
in a different shape of the current pulses.

Immunity to RF Signals
In a strong radio frequency electromagnetic
field, it is possible for common-mode amplitude modulated RF signals to be present on
the alb lines. These common-mode signals
can sometimes become differential-mode signals as a result of asymmetrical parasitic
capacitances to ground; this may occur, for
example, through the hand of the subscriber
holding the handset. Steps have to be taken
to avoid the possibility of these signals being
detected and the low-frequency modulation
appearing as unwanted signal at the earpiece
or on the line. Small discrete capacitors are
necessary to suppress the unwanted RF
signals before they can enter the circuit.

6-102

Furthermore, the layout of the printed circuit
board may have influence on RF immunity.
The copper ground area should be kept as
large as possible. Ground loops must be
avoided and traces must be kept as short as
possible. RFI-capacitors must be mounted as
close as possible to the IC pins.
In practice, it has been shown that two
inductors (chokes with a value between
200/lH and 1mH) in series with the alb lines
improve RF immunity considerably. It has
been shown also in practice that a so-called
"guard ring" (closed copper ring) around the
circuit gives a considerable improvement
against radiated magnetic fields.
Because the TEA 1067 has a very high microphone input impedance, it is possible to use
low-pass filtering in series with both microphone inputs, without affecting gain accuracy.
The RC filter should be positioned as close as
possible to Pins 7 (MIC-) and 8 (MIC+). A
low-ohmic termination across the microphone
inputs will reduce pick-up of unwanted RF
signals via the handset cord.

Polarity Guard and Transient
Suppression
There is a possibility that the transmission IC
is destroyed by excessive current surges on
the telephone lines if no proper measures are
taken. The type of protection differs for sets
with only DTMF dialing or sets with either
pulse-dialing or DTMF dialing with "flash"
(register recall by means of a timed line
interrupt).
With DTMF dialing only, the bridge rectifier,
which normally acts as a polarity guard, can
also incorporate two voltage reference diodes
(such as BZWI4). Under normal operating
conditions, one of the two voltage reference
diodes conducts while the other is nonconducting. If the voltage across the set
temporarily exceeds the reference voltage of
the previously mentioned non-conducting diode, it will conduct and limit the voltage
across the set. The maximum permissible
voltage across the transmission circuit is 12V
continuously and is determined by the collector-emitter breakdown voltage of the IC process used. During switch-on and line interrupts, the maximum permissible voltage is
13.2V allowing the use of a 12V voltage
reference diode in the polarity guard.

Signetics Linear Products

Application Note

Application of the low Voltage Versatile Transmission Circuit

application of the TEA 1067 with an interrupter circuit.

5.GE+1
4.5E+l

"-

3.5E+l

Iii' 3.OE+1
2.SE+1

2.OE+l

l.GE+l

'""'

V

~

1.5E+l

Hints for Printed Circuit Board
Layout

-'"

4.GE+l

..E

./'

V

Care must be taken to avoid having the large
line current flowing into common ground
traces to which sensitive points are connected .

I'-...
i'"-

For this reason, resistors Rg (connected between STAB and VEE) and Rs (connected
between AGC and VEE) must be situated on
the PCB close to Pin 10 (VEE).

.,/"

O.5E+O
o.oE+O
l.oE+2

1.0E+4

l.oE+3
FREQUENCY (Hz)

NOTE:Z_zo

BRL =

--

z +Zo

AN1942

with Zo =

soon

Figure 37. Balance Return Loss (BRL) as a Function of Frequency

Also, the ground connection of the earpiece
should preferably be realized at a point where
no large line current is flowing.
The copper tracks connecting R7 and R4 to
the corresponding IC pins should be kept as
short as possible.
The ground connection of all RFI capacitors
should be made by means of the largest
possible copper planes. RFI capacitors must
be connected as close as possible to the pins
that have to be decoupled.

+J

The ground plane on the circuit board must
be kept as large as possible.

PERFORMANCE
-Lr-~-4--+--+--r-~-4--+--+~~4--4--+--H~r-,+L

Some measurements have been done with
the basic application circuit, including RFI
capacitors as shown in Figure A 1. This gives
an indication of the performance of the
TEA1067.

Balance Return Loss
The result of the balance return loss measurement (BRL) is shown in Figure 37. The
impedance of the circuit is shown in Figure
38.
Different values chosen for C3 and for Rg will
have influence on the impedance and the
BRL of the circuit. Remember that C3 and Rg
also determine some other parameters.

-J

Figure 38. Polar Plot of Impedance Between AlB Connections
Further protection is offered by the resistor
Rl0 in series with the bridge rectifier, which
limits the current that can be drawn by the IC.
The maximum allowed transient voltage on
the circuit, including the protection resistor
RlO being 13n and with Rg = 20n, is 28V
during 1ms with a repetition time of 5sec. This
corresponds with a 50A surge onto the
BZW14 zener diodes used in the polarity
guard.
For DTMF dialing with flash, or for pulse
dialing, a different protection arrangement is
necessary because, during line interruption,
the line current must be zero. This means that
the bridge rectifier must be able to withstand
February 1987

a relatively high voltage, on the order of
200V. A polarity guard using four diodes with
type number BAS11 is appropriate for this
purpose. Protection against line current
surges can then be obtained by means of a
suitable VDR connected between the alb
lines in front of the polarity guard. The speech
circuit is protected against overvoltages that
may occur, for example, during switching·in,
by means of a 12V regulator diode connected
between LN and VEE, or in case a current
limiter is used (e.g., combined with the inter·
rupter), by a 6.8V voltage regulator diode
connected between LN and SLPE. The latter
method also provides symmetrical clipping of
the sending signal. Figure A2 shows an

6-103

Frequency Characteristics
Figure 39 shows the frequency characteristic
of the sending channel measured between
microphone inputs and the transmitter output
LN with a 600n load. The microphone gain is
set by means of R7 to 52dB (R7 = 68.1 kn).
The upper cut-off frequency is about 24kHz
(mainly determined by the time constant
R7CS)'
Note that if a complex set impedance has
been chosen, it will have influence on the
frequency characteristic.
Figure 40 shows the frequency characteristic
of the receiving channel measured between
LN and the QR+ output loaded with 150n
(single-ended drive; 10IlF DC-blocking capacitor). With R4 = 100kn, the transfer ratio

Signetics Linear Products

Application Note

Application of the Low Voltage Versatile Transmission Circuit

83

-65

~S2.8

..,-117

~52.4
52

V

/

/

./

/"

,/

-65

40

-0.5

~-~

r-..
J

-2

~-2.6

/

~ -3

/

:I:

-4

./
./

-77

11)2

Figure 39. Frequency Characteristic
of Microphone Amplifier

~

-75

.;

/200Q

> -83

FREQUENCY (Hz)

" -3.5

~

.;

/

~ -81

5111)2

....

-73

~-79

:IE 51.2

z
~

Ii:

3

~

w 51.8

51.4

I.;

./1-

I::

~52.2
51.6

~kQ

"' -71

w

~
~

_R~IC+,~'C-

"
i-a

~ 52.6

~

AN1942

I

~-4.5
w
a: -5
-5.5
11)2

11)2

FREQUENCY (Hz)

Figure 40. Frequency Characteristic
of the Receiving Channel

-30

-31

Iii"

...... ~

~

-33

-34

10'
FREQUENCY (Hz)

Figure 41. Frequency Characteristic
of the Anti-Sidetone Circuit
Between LN and IR

February 1987

44

48

48

50

52

54

A" (dB)

Figure 42. Frequency Characteristic
of the Electrical Sidetone at
Okm Line Length

Figure 43. Psophometrically-Welghted
Noise on the Line LN VB
Microphone Gain

is -1 dB at 1kHz. The lower cut·off frequency
is 120Hz and is determined in this case by the
time constant RLC2 of the load resistor RL
and the DC·blocking capacitor C2 . The upper
cut·off frequency is about 9.5kHz and is
determined partly by R4C4 (15kHz) and partly
by the cut-off frequency of the anti-sidetone
circuit (18kHz).

because both amplifiers (microphone and
receive) are affected by the gain control
function.

The frequency response of the anti-sidetone
circuit (LN to IR) is given in Figure 41. The
cut-off frequency is about 18kHz. This is
mainly obtained by the 2.2nF capacitor connected between IR and VEE (necessary for
RF immunity).
The transfer ratio as a function of frequency
measured from the microphone inputs to a
150n asymmetrical load at the receive output
QR+ (10!,F DC blocking capacitor) is shown
in Figure 42. This represents the electrical
sidetone at Okm of telephone line (600n load
at LN). The measured sending signal at LN is
shown also. The signal at the receive output
with the same line signal in receiving condition is shown also in Figure 42.

~

z -32

42

FREQUENCY (Hz)

The difference between wanted receive signal and principally unwanted sidetone at the
receive output is in fact the electrical sidetone
suppression. This means that for this application the electrical sidetone suppression at
Okm of line length is about 7.3dB at 1kHz.
The result depends strongly on the balancing
of the anti-sidetone circuit. In this case, the
balance impedance ZSAL has been optimized
for 5km line length with O.5mm diameter,
176n/km and 38nF Ikm.
Electrical sidetone suppression is not dependent on whether gain control is used or not,

6-104

Noise
Typical noise psophometrically (P53 curve)
measured on the line LN with a 600n load is
given as a function of microphone gain in
Figure 43. The microphone input is loaded
with a 200n resistor or 8.2kn.
Psophometrical noise at the receive output
(single-ended 300n load) as a function of
microphone gain is shown in Figure 44. Parameters are the receive gain and the resistor
across the microphone inputs.
NOTE:

For information on discrete semiconductors used in
this application note, contact Amperex Electronic

Corp., Smithfield, RI, (401) 232-0500.
,I

.., -71

'"

I

r- RM,c +. j'C-

~ -73

E

~ -75

i

-77

r-- -18.2kQ
-\"

.. -79

l,.-

~

+ -81

a:

0-83

'"g-as

-:: -87

-89

P.r. -ldB

~

P.r.= -7dB

I
40

42

t-=44

.-.--

V

V
V

./

","

8.2kQ

200Q

).;

~ ... t'

.........

--

48

48

;;

200Q

50

52

54

A" (dB)
Figure 44. Psophometrically Weighted
Noise at the Receiver Output
vs Microphone Gain

Signetics Linear Products

Application Note

Application of the Low Voltage Versatile Transmission Circuit

AN1942

APPENDIX I
Component

, -________
.. Set impedance real or complex?

t

(Re)-balancing anti-sidetone bridge
(Rg: recommended value 20n)

t

DC characteristic
DC slope
Maximum line voltage
type of polarity guard

[

..

sUPPIJ for

Schottky diodes
Active bridge
Normal diodes

peripherals

t
1....1 -_ _ _ _ _ _ Compromise
t

BRL/ Supply

RC-smoothing filter between LN and SLPE
(level shifters for logical inputs)

t
t
Gain control start/stop
t
Microphone gain
t
Upper cut-off frequency microphone amplifier
t
Lower cut-off frequency microphone amplifier
t
DTMF input level adjustment
t
Receive gain: single-ended or symmetrical
t
Upper cut-off frequency receiving amplifier
t

....1--_ _ _ _ _ _ TEA 1 OBO necessary or (artificial) inductor?

Rs
R7

Attenuator at microphone inputs
Cs
Capacitor(s) at microphone inputs
Attenuator at DTMF input

Lower cut-off frequency receiving amplifier

Adjusting Parameters for the TEA 1060 Family

February 19B7

6-105

Signetics· Linear Products

Application Note

Application of the Low Voltage Versatile Transmission Circuit

AN1942

R1
620

RlO
13

15

LN

Vee

11
IR

ew
BZX79
6V8

2.2nF
OR-

13
OR+

OTMF
MUTE

TEA1067

,.
12

GAR

AlB

PO

MIC+

B/Ao----+-----'

MIC16

REG

SLPE

GAS1

18

2

1---

I

STAB

AGe

17

VEE
10

R7
e6
100pF

ZBAL

I
I

GAS2

e3
4.7j.!F

R9

20

SS.1k

R6

R5

3.6k

I

NOTE:

RFI capacitors are marked with an asterisk.

Figure A1. Basic Application Diagram of TEA1067 in Sets With DTMF Dialing

February 1987

6-106

C14

+

\-0
FROM DIAL
l
CONTROL CIRCUITS

Signetics Linear Products

Application Note

Application of the Low Voltage Versatile Transmission Circuit

TELEPHONE

[AlB

LINE

B/A04--+-...I

R6

R"

R2B

3.6k

R25

470k

OZx79
lOY

R24

R23

<10k

10M

NOTE:
RFr capacitors are marked with an asterisk.

Figure A2. Basic Application Diagram of TEA 1067 in Sets With Combined Pulse and
Tone Dialing Including Interrupter With Interface

February 1987

6-107

AN1942

Signetics

AN1943
Supply of Peripheral Circuits
With the TEA 1067 Speech
Circuit

Linear Products

INTRODUCTION
The telephony line interface and speech
transmission circuits TEA 106011 have been
in use for several years now. They contain all
interface circuitry required to connect transducers and dialers to a telephone line.
A lot of components such as dialers and
computers have been developed which can
be interfaced to the TEA1060/1 easily. These
components are powered by the supply point
of the TEA1060/1.
To meet the North American Telephony requirements RS-470, the new speech circuit
TEA 1067 has been developed. TEA 1067 operates at a lower line voltage, which enables
it to operate in parallel with the conventional
telephone sets (unlike the TEA 1060/1).
However, a lower line voltage and the possibility of connecting conventional telephone
sets in parallel have potentially severe effects
on the supply capabilities of the speech
circuit.
This application report contains some proposals to realize optimal connection of peripherals to the TEA 1067 speech circuit.

Application Note

incoming call. The upper limit of this
region is determined by the ability of
the telephone set to draw adequate
current for proper pull-up of central
office relays.
After this one-second period for incoming
calls, and during DTMF-dialing, and after
called-party answer on outgoing calls (where
the relays are required only to hold their
energized state), operation may fall within the
conditionally acceptable region of Figure 1.

JNACCEPTABL~
I REGION
I

(26, 10.4)

(.o,t/'

I

CONDITIONALLY ACCEPTA~
REGION
(26, 7.8)
(2O,~_

IACCEPTABLEI

REGION

I

I

10

20

30

LOOPCURRENT(mA)

Figure 1. DC Voltage vs Current
Characteristics

NORTH AMERICAN TELEPHONY
REQUIREMENTS RS-470 FOR
TELEPHONE SETS IN USA
Telephone sets used in the USA (and also in
some Far East countries) have to fulfill some
special demands which are described in the
RS-470 requirements. The points of importance for PhilipS speech circuits are:
• It is allowed to connect more telephone
sets in parallel. RS-470 doesn't specify
details, but it seems to be that
electronic speech circuits must remain
operative (at least at a reduced
performance) if a conventional (carbon
microphone) telephone set is connected
in parallel on a subscriber loop, having
the minimum line current of 20mA. For
measurements, a reasonable
replacement for such a conventional
telephone set seems to be a 200n
resistor.
• The off-hook tip-to-ring DC voltage
versus current characteristics must be in
the acceptable region of Figure 1 during
the on-hook to off-hook transition, and
during the make-interval of rotary dial
pulses on outgoing calls, and for at
least one second after answer of an
February 1987

It is desired that the off-hook tip-to-ring impedance of the telephone set be 600n
across the 200 - 3200Hz band. More specifically, the balance return loss (measured
against 600n) shall be greater than 3.5dB for
the 200 - 3200Hz band and greater than
7.0dB for the 500 - 2500Hz band.

EFFECTS OF RS-470 ON
PHILIPS SPEECH CIRCUITS
Under normal operation, the minimum line
current which can occur according to the RS470 requirements is 20mA. The minimum
supply capabilities of the supply point of the
TEA 106011 are according to Figure 2a.
Most Philips CMOS peripherals require a
minimum supply voltage of 2.5V. Taking into
account OAV as the forward voltage drop of a
Schottky enable diode (BAT85: VF < 320mV
at 25°C and 1mAl, the minimum allowable
voltage of the supply point of the TEA1060/1
is 2.9V. At this voltage the minimum available
supply current is 1.2mA, according to Figure
2a, which is enough to power a CMOS
microcontroller (e.g., PCD3315) and a DTMF
generator (PCD3312).

6-108

However, there are two problems with the
TEA1060/1 with respect to the RS-470 requirements.
The first problem concerns the parallel connection of conventional telephone sets and
TEA1060/1 sets at low line currents. Taking a
resistance of 200n for the parallel set, the
line voltage at 20mA line current will drop to
about 3.8V (assuming 1mA remaining current
for the TEA1060/1) or 2.3V after the polarity
guard. The transmitting stage of the
TEA1060/1 doesn't function at such low
voltages. In order to keep the transmitting
amplifier operating at such low line voltages
(with a reduced performance), the TEA 1067
has been designed.
Second, the maximum line voltage of the
TEA 1060/1, excluding the interrupter circuit,
measures 6.35V at 20mA [maximum line
voltage at 20mA (4.75V), plus temperature
effects (assume 0.1V), plus polarity guard
voltage drop (assume 1.5V)], which is 0.35V
too much (see Figure 1). Therefore, the line
voltage of the TEA 1067 has been decreased
by 0.55V with respect to the TEA 1060/1.
However, both measures have severe implications for the architecture advised by
Philips/Signetics hitherto.
If a 200n telephone set is connected in
parallel with a TEA 1067 set on a 20mA loop,
the supply voltage for peripherals will decrease to less than 2V. In applications with
the TEA1060/1, Philips/Signetics advises
their customers to use a MOSFET of the type
BST76A as an interrupter switch. Since the
gate-source threshold voltage of this type of
FET can be as high as 2.7V, problems can be
expected when used in a TEA 1067 set with a
200n parallel set - it can't be guaranteed
that the interrupter switch remains conducting. Therefore, a bipolar interrupter will be
described which doesn't have this problem.
The problems that occur with the supply of
peripherals in this case will be illustrated later.
Furthermore, due to the reduced line voltage
of the TEA 1067, the supply capabilities of its
supply pOint are considerably reduced with
respect to the TEA1060/1 (see Figure 2b). At
2.9V, a minimum supply current of only
300l'A can be guaranteed. This is not enough
to power a microcontroller and a DTMF dialer
(e.g., PCD3315 + PCD3312) simultaneously.
Some suggestions to overcome this problem
will be given later.

Signetics Linear Products

Application Note

Supply of Peripheral Circuits With the TEA1067 Speech Circuit

...s

AN1943

effect. In the next section it will be shown that
this measure adversely affects the supply
capabilities of the TEAl 067.

t

[......-----4~---_+~-----+----_i

INCREASING THE SUPPLY
CAPABILITIES OF THE TEA1067

0.5 [......------l--~'<-_+_+--~.......- + - - - - _ l

The bottleneck in the supply problems of the
TEA 1067 is in the 620Q resistor connected
between the pins LN and VCC of the
TEA 1067 (Figure 3). It determines the supply
capabilities of the TEA 1067 as well as the AC
impedance of the circuit. A reduction of the

1.0

ffi

a:
a:
::>
o

~
..

Use of an Inductor

iil

3.5

2.5

SUPPLY VOLTAGE IV) ...

resistance therefore results in improved sup-

Figure 2. Minimum Supply Current Available for Peripherals as a Function of
Supply Voltage of TEA 1060/1 (A) and TEA 1067 (8) at 20mA Line Current

If this DC resistance can be reduced while
maintaining the 600Q impedance for AC, the
supply problem can be solved. This can be
realized by means of an inductor connected
in parallel with the 620Q.

A/B~---------,---------,

There are two possibilities to realize a practical inductor:
• Use of a coil (Figure 5a)
• Use of an electronic inductor (e.g.,
TEA 1080 supply IC (Figure 5b),
(discrete) gyrator circuit)

Vee

+

11
BC547

Use of a Schottky Diode
Polarity Guard

SLPE

In case only DTMF dialing is used (without
FLASH), no interrupter circuit is required and,
therefore, no transients due to line current

20

IB/A-t

interruptions can occur. This makes it possi-

ble to realize protection with rugged lowvoltage zener diodes (e.g., Philips BZW14
with a maximum voltage during transients of
28V). At such low voltages, the high voltage
diodes required in the polarity guard (e.g.,
BASll which can stand 300V) normally can
be replaced by low-voltage Schottky diodes
(e.g., BAT86 which can stand 50V) resulting
in a lower voltage drop over the polarity
guard. In Figure 6, two possible configurations are given.

~gure 3. Circuit Diagram of Low-Voltage Interrupter
A LOW-VOLTAGE
INTERRUPTER
In Figure 3 the circuit diagram of an interrupter is given which operates at input voltages
down to lV.
The circuitry around T2 and T3 is commonly
used already in telephony applications and
needs no further explanation. The interface
function between this interrupter and the
pulse dialer is performed by transistor Tl and
resistor R4. Using transistors of the type
2N5401 and 2N5551 allows operation up to
150V. In case higher voltages occur, a voltage limiting device (e.g., a VDR) has to be
used in front of the circuitry. No current
limiting function is accomplished in this circuit.
In Figure 4 the typical voltage drop over the
interrupter (VEe of T3) is given as a function
of loop current using a 2.2kQ resistor for R3.
A lower resistance lowers the voltage drop at
high line currents, but also reduces the current which is left for the TEAl 067.
February 1987

ply capabilities, but also in poorer BRL figures.

/

V

V

1

I--I-20

30

v

40

In Figure 6a the voltage gain (due to a lower
voltage drop) is about 0.5V; in Figure 6b it is
about 1.0V.

II
50

60

70

80

IUNE(mA)-

Figure 4. Voltage Drop VEe of T3 as a
Function of Line Current
Since R3 is connected in parallel with the
600Q impedance of the TEAl 067 circuitry,
the total set impedance is now lower than
600Q. Using 2.2kQ for R3, the TEAl 067
impedance must be increased to approximately 850Q in order to compensate for this

6-109

It is possible now to increase the line voltage
of the TEA1067 by 0.5 or 1.0V, thus increasing the supply capabilities of the TEAl 067.
(The increase will measure 0.5V /
620Q = 0.8mA in Figure 6a or 1.6mA in
Figure 6b.
Increase of the line voltage of the TEAl 067
can be achieved by means of an external
resistor between the pins REG and SLPE. In
Figure 7 the relation between this resistance
and the resulting typical line voltage for a line
current of 20mA is given.

Signetics Linear Products

Application Note

Supply of Peripheral Circuits With the TEA1067 Speech Circuit

4.7~F

AN1943

1.2

lOOk

i• 1\
1.0

tzw

o.a

0:
0:

"~
......

0.8

...

0.4

iilw

.

\
\

(,)

'\

~

i'\.

i'-

j

0.2

o

"r--..

3SO 400 4SO SOD 5SO 600 &SO 700 750 600
SUPPLY RESISTANCE (2) +-

TEA1067

a. Coli

b. TEA10S0

Figure S. Calculated Minimum Supply
Current Available at the Supply
Point of the TEA1067, at a Voltage
of 2.9V, Assuming a Subscriber Line
of 20mA, as a Function
of the Supply Resistance

Figure 5. Examples of Increasing the Supply Capabilities of the TEA 1067
600

/
AlB

AlB

//

0---<.--«

2xBZW14

BIA

/

---+-----'

o----+--.....J

BIA 0 - -....

,/

/

V

b. 6-Diode Solution With 1.0V Gain
(Due to a Lower Voltage Drop)

t

>SiD

20iz
a:

~

15 :::

I

/
10

300

a. 4-Diode Solution With 0.5V Gain
(Due to a Lower Voltage Drop)

30

350 400 450 500 550 600 650 700 750 800
SUPPLY RESISfANCE(2)

Figure 6. Schottky Diode Polarity Guard With Protection
the TEA1067. Besides, it has a minor influ·
ence on the power·down function of the
TEAl 067.

Two Other Methods

\
I\.
I'...
4

o

.............

50

100

RR£G.S1.PE (k2) +Figure 7. Typical Line Voltage
(VLN - VEE) as a Function of RREG-SLPE
at a Line Current of 20mA
However, this resistor causes a slightly increased spread in the voltage drop and a
slightly modified temperature coefficient of
February 1987

In principle, the RS-470 requirements give
two alternative ways to come out of the
supply problems of the TEAl 067:
1) The TEAl 067 itself fulfills the balance
return loss figures required with a large
margin. Accepting a smaller margin by
means of decreasing the AC impedance
will result in an increase of the supply
capabilities.
2) The most severe supply problem occurs
when a DTMF dialer must be operative.
But in that case, operation in the conditionally acceptable region of Figure 1 is
allowed! This lightens the supply problems considerably.
In Figure 8, the minimum supply capabilities
of the TEA 1067 are given as a function of the
supply resistor of the TEA1067. A subscriber
line having the minimum line current of 20mA

6-110

Figure 9. Calculated Total Set
Impedance and BRL as a Function
of the Supply Resistor of the
TEA 1067 (Including Influence of
2.2kn Interrupter)
is assumed here. Assuming the use of a
bipolar interrupter having a resistance of
2.2kn (which is connected in parallel to the
TEAl 067), the resulting set impedance and
BRL are given in Figure 9.
As can be seen in Figure 8, the supply
capabilities of the TEAl 067 equal those of
the TEAl 060/ 1 if a supply resistor of 380n
(instead of the 620n used for the TEAl 060/
1) is used. The resulting total set impedance
will be 320n, resulting in a BRL of about
10dB (see Figure 9). This still fulfills the RS470 requirements (> 7dB between 500 and
2000Hz) with a safe margin.
However, change of the 620n resistor of the
TEA1067 results not only in a change of AC
impedance and an improvement of the supply
point, but also in a change of microphone
gain (which depends linearly on the load

Signetics linear Products

Application Note

Supply of Peripheral Circuits With the TEA1067 Speech Circuit

AN1943

620

LN

Vee

;

LN

+

vee

+

loo"F
TEA1067

TEA1067

REG

,.t

REG
\..tC557
VEE

lOOk
VEE

SLPE
R
20

SLPE

SC547

+

lOOk

~

+
4.7"F"f;

4.7f.1F
20

a. HIGH

= Normal

Voltage, LOW

= Increased

Voltage

b. HIGH

=Increased Voltage, LOW =Normal Voltage

Figure 1O. Circuit to Increase the Line Voltage Temporarily
impedance) and in a change of the driving
range of the transmitting stage. Besides,
rebalancing the anti-sidetone bridge will become necessary.

620

AlB
LN

If a better BRL is required, it is possible to use
one of the circuits given in Figure 10. In these
circuits the supply resistor is increased again,
resulting in better BRL figures, but also in
reduced supply capabilities.

TEA1067
REG

VEE

February 1987

SLPE

D1

t...,

.......

SAW62

T1

DP

BCSS7
R
20

+

4.7,.,F

R2

+

100",F

SIA

The switching transistor can be driven directly
by a mute signal generated by a OTMF
generator, resulting in the nominal line voltage except for the time OTMF tones are
generated, This approach makes it possible
to dimension the supply resistor in such a way
that it can power all peripherals excluding the
OTMF dialer. In case of OTMF dialing, the line
voltage will be increased, resulting in enough
supply current for the OTMF dialer, too.

If a dial pulse or a flash signal is applied to
01, Cl is discharged rapidly via 01, thus
bringing back the line voltage into the acceptable region of Figure 1.

C1

l"F

However, if maximum supply current is required (i.e., during OTMF dialing), the line
voltage can be increased by activating the
transistor, thus giving a higher maximum supply current. Resistor R increases the line
voltage according to the principle described
previously and in Figure 7,

It is also possible to drive the transistor
automatically, according to the circuit given in
Figure 11. Immediately after going off-hook,
Tl is switched off until Cl is charged to Vcc
(VREG - 0.6V) via R2. Until then, the line
voltage will fall into the acceptable region of
Figure 1. After this period, the line voltage will
be increased and will fall into the conditionally
acceptable region of Figure 1.

Vee

Figure 11. Circuit Which Increases Line Voltage
if This is Allowed According to RS·470

>

>

a. After Initial Switch·On

b. During and After Pulse Dialing

Figure 12. Line Voltage as a Function of Time

6·111

Signetics Linear Products

Application Note

Supply of Peripheral Circuits With the TEA1067 Speech Circuit

AN1943

620

AlB

B/A

-:h

LN

®ALTER

I

Vee
DTMF

MK5380

;1-J\

"nI'

MUTE

TEA1067 MUTE

VEE

Voo
DTMF

Vss
KEYBOARD

REG
SLPE

rook

.tk
8C547 ...

20

+

4.7j.4F

+
100j.4F

Figure 13. TEA 1067 Used in Combination With a 5380 DTMF Dialer
Notice that the power-down function of the
TEA 1067 remains fully operative in this case.
since the connection between the pins REG
and SLPE is now removed.
In Figure 12, the line voltage after initial
switch-on and during and after pulse dialing is
shown.

TWO PRACTICAL EXAMPLES
In the preceding text we have considered
several possibilities to increase the supply
capabilities of the TEA 1067. Now we will look
at two practical examples.
The use of a TEA1067 with a CMOS DTMF
dialer (5380 in this case) will be considered.
Later, the use of a TEA 1067 with the
PCD3315 repertory dialer and PCD3312
DTMF dialer will be discussed.

TEA1067 Plus MK5380 CMOS
DTMF Dialer
The schematic circuit of this combination is
shown in Figure 13.

February 1987

Since an MK5380 in standby mode consumes
only 150llA maximally at 2.5V, it can be
powered directly from the TEA 1067 supply
pOint using the standard supply resistor of
620n when the telephone set is in its speech
mode.
However, in the dial mode, the supply current
of an MK5380 can be as high as 2mA at 2.5V,
while the TEA 1067 can deliver only 1mA at
this voltage (Figure 2). Therefore, in the dial
mode an increase of the line voltage of
1mA X 620n is required. This will result in a
voltage over the telephone set that falls in the
conditionally acceptable region of Figure 1
which is allowed during DTMF dialing. This
increase of voltage can be achieved according to the circuit given in Figure 10b using a
resistor of 39kn (Figure 7) between pin REG
of the TEA 1067 and the collector of the
BC547. The transistor can be controlled directly by the MUTE signal of the 5380.
As an alternative. the 39kn resistor can be
connected directly between the pins REG

6-112

and SLPE of the TEA 1067 in combination
with the Schottky diode bridge of Figure 6b.
This will also result in a line voltage which is
in the acceptable region of Figure 1.
If a conventional telephone set is connected
in parallel to the circuit of Figure 13. the
supply voltage for the 5380 dialer can drop to
below 2V. Since its minimum supply voltage is
2.5V. proper DTMF tones generation can't be
guaranteed under these circumstances.

TEA1067 Plus PCD3315 and
PCD3312
Since it is not allowed to have a line voltage
which falls into the conditionally acceptable
region of Figure 1 during pulse dialing, it is not
possible to use the approach described previously here. Therefore. the prinCiple of Figure
11 has been chosen for this example. In
Figure 14, the schematic diagram of the
circuitry used is shown.

Signetics Linear Products

Application Note

Supply of Peripheral Circuits With the TEA1067 Speech Circuit

~2N5401

1SOk

~85

470

AlB

BIA

+

"-'

f

/-

Vee PO
TEA1067

r-K

M_

2.2k

REG

K2N5551

470k

OP

~

3v

PCD3315

_M
Vss

+

jEOISlJi?-

-

r

BC547

....
VDD

CE

IN

1SOk

BAW62

~~

1.F

AN1943

20

1.12

+

4.7J.lF

+

L1

::: 1OO.F

SOA

I VDD

I

SCl

PCD3312
Vss

I
Figure 14. TEA1067 Used With PCD3315 and PCD3312
The minimum supply voltage of the PCD3315
and the PCD3312 is 2.5V. Since the
PCD3315 has to be powered via a series
(Schottky) diode, the minimum supply point
voltage of the TEA1067 allowed is 2.9V. At
this voltage the TEA 1067 can deliver only
300l'A (Figure 2). Although the maximum
supply current of the PCD3315 during pulse
dialing is not specified yet, 7001lA seems to
be a reasonable value. According to Figure 8,
this can be reached by using a supply resistor
of 470n instead of 602n. Using a bipolar
interrupter with an impedance of 2.2kn, this
will result in a balance return loss of still 13dB
according to Figure 9.
In the case of DTMF dialing, the PCD3312
must also be powered. This can be achieved

February 1987

by increasing the line voltage of the
TEA1067. The maximum operating current of
the PCD3312 is specified as 1.2mA at 3.0V.
Using a supply resistor of 470n, an extra
1.2mA can be gained by increasing the line
voltage with 1.2mA X 470n = 0.6V. This results in a resistor of 39kn between pins REG
and SLPE of the TEA 1067.
Since the supply resistor in Figure 14 has
been reduced from 620n to 470n, a lot of
components around the TEA 1067 have to be
adapted to the new situation. The sending
gains and the sidetone are especially influenced by this measure.
If a conventional telephone set is connected
in parallel with the circuit of Figure 14, the
supply point voltage might drop to below 2V.

6-113

As a result, the PCD3312 receives a too-low
supply voltage, and improper generation of
DTMF tones might occur. For the PCD3315,
however, there won't be a problem. If the
supply point voltage drops too far, it simply
continues to operate on battery power (unless the CE voltage becomes too low). Of
course, the lifetime of the battery will be
decreased considerably in this way.
NOTE:
For information on discrete semiconductors used in
this application note, contact Amperex Electronic
Corp. Smithfield, RI. (401) 232-0500.
This application note was originally published as
Laboratory Report ETI8602, in April 1986. The
report was written by J.Y. Tiggelen at C.A.B.-ELCOMA, The Netherlands.

TEA1068

Signetics

Versatile Telephone
Transmission Circuit
Product Specification

Linear Products

DESCRIPTION
The TEA 1068 is a bipolar integrated
circuit performing all speech and line
interface functions required in fully-electronic telephone sets. The circuit internally performs electronic switching between dialing and speech.

FEATURES
• Voltage regulator with adjustable
static resistance
• Provides supply for external
circuitry
• Symmetrical high-impedance
inputs (64kU) for dynamic,
magnetic or piezoelectric
microphones
• Asymmetrical high-impedance
Input (32kU) for electret
microphone
• DTMF signal input with
confidence tone

• Mute input for pulse or DTMF
dialing
• Power-down input for pulse dial
or register recall
• Receiving amplifier for magnetic,
dynamic or piezoelectric
earpieces
• Large amplification setting range
on microphone and earpiece
amplifiers
• Line loss compensation facility,
line current dependent for
microphone and receiving
amplifiers
• Gain control adaptable to
exchange supply
• Possibility to adjust the DC line
voltage

DTMF
PD
IR

TOP VIEW
oo11540S

PIN NO. SYMBOL
LN

Positive line connection
Gain adjustment connection,

GAS2

sending ampUfier
Gain adjustment connection,

sending amplifier

OR+

• Electronic telephone sets

GAR

TEMPERATURE RANGE

ORDER CODE

-25'C to + 75'C

TEA1068PN

ABSOLUTE MAXIMUM RATINGS
RATING

UNIT

12

V

VLN

Positive line voltage (DC)

VLN

Repetitive line voltage during switch-on
or line interruption

13.2

V

VLNRM

Repetitive peak line voltage
tplP = 1ms/5s;
R 10 = 130; Rg = 200 (see Figure 8)

28

V

IUNE

line current

VI
-VI

Voltage on all other pins

PTOT

Total power dissipation

TSTG

Storage temperature range

TA

Operating ambient temperature range

140

rnA

Vcc +0.7
0.7

V
V

640

mW

-65 to + 150

'c
'c

-25 to +75

6-114

Inverting output, receiving
amplifier
Non-inverting output, receiving

amplifier

DESCRIPTION

PARAMETER

DESCRIPTION

GAS 1

APPLICATION

t8-Pin Plastic DIP (SOT-102HE)

December 2, 1986

N Package

OR-

ORDERING INFORMATION

SYMBOL

PIN CONFIGURATION

7
8
9
10
11
12
13
14
15

MIC+

MICSTAB
VEE

IR
PD
DTMF
MUTE
Vee

16

REG

17
18

AGC
SLPE

Gain adjustment connection,
receiving amplifier
Non-inverting microphone input

Inverting microphone input
Current stabilizer connection
Negative line connection
Receiving amplifier input
Power-down input
Dual-tone multi-frequency input
Mute input
Positive supply decoupling
connection
Voltage regulator decoupling
connection
Automatic gain control input
Slope (DC resistance)
adjustment connection

853-1050 86702

Product Specification

Signetics Linear Products

TEA1068

Versatile Telephone Transmission Circuit

BLOCK DIAGRAM
LN
1

15

11

6

~n_-

IR

GAR

0......

L-

TEA1068

-

I> r-

0

W

5

-

r--

+

QR+

+

I>

4

L-

8
MIC+

+

-

,- ~

7

-

MIC-

L-

-

13

r-

dB

OTMF

+

I>

;--

2

rL
U-

~

0

;-- +

L-

I>

r---K
3

I

14
MUTE
12
PO

I
I

SUPPLYANO
REFERENCE

CONTROL
CURRENT

",....

+

~

CURRENT
REFERENCE

I
10

b

'6

REG

December 2, 1986

17
AGC

b
9

STAB

6-115

18
SLPE

QR-

Product Specilication

Signetics Linear Products

TEA1068

Versatile Telephone Transmission Circuit

DC ELECTRICAL CHARACTERISTICS IUNE =

11 = 10 to 140mA; VEE = Vl0 = OV; I = 800Hz; R9 = 20!"l; TA = 25'C, unless
otherwise specified.

LIMITS
SYMBOL

PARAMETER

UNIT
Min

Typ

Max

3.95
4.20
5.4

4.25
4.45
6.1

4.55
4.70
7
8

V
V
V
V

-4

-2

0

mV/'C

3.45
4.65

3.80
5.0

4.10
5.35

V
V

0.96
55

1.30
82

mA
JlA

64
32

77
38.5

k!"l
k!"l

Supply: LN and Vee (Pins 1 and 15)

VLN
VLN
VLN
VLN
AVLN/AT

Voltage drop over circuit V1 -10
microphone inputs open
at IUNE = 5mA
at IUNE = 15mA
at IUNE = 100mA
at IUNE = 140mA
Variation with temperature
IUNE = 15mA

VLN
VLN

Voltage drop over circuit
at IUNE = 15mA
RVA = R1 - 16 = 68k!"l
RVA = R16-18 = 39k!"l

Icc
lee

Supply current
PD (Pin 12) = LOW; Vee = 2.8V
PD (Pin 12) = HIGH; Vee = 2.8V

Microphone inputs MIC+ and MIC- (Pins 8 and 7)
!lIS!
!lIS!

Input impedance
differential (between Pins 7 and 8)
single-ended (Pins 7 - 10 or Pins 8 - 10)

51
25.5

CMRR

Common-mode rejection ratio

Avo

Voltage amplification (Pins 7, 8-1) at IUNE = 15mA; R7 = 68k!"l

!:>.Avo/AI

Variation with frequency at I = 300 to 3400Hz

!:>.Avo/AT

Variation with temperature at IUNE = 50mA; TA = -25'C to + 75'C

dB

82
51

52

53

dB

-0.5

±0.2

+0.5

dB

±0.2

dB

Dual-tone multi-frequency Input DTMF (Pin 13)
!lIS!

Input impedance

16.8

20.7

24.6

k!"l

Avo

Voltage amplification at IUNE = 15mA; R7 = 68k!"l

24.5

25.5

26.5

dB

!:>.Avo/AI

Variation with frequency at f = 300 to 3400Hz

-0.5

±0.2

+0.5

dB

!:>.AvD/AT

Variation with temperature at IUNE = 50mA; TA = -25'C to + 75'C

±0.2

dB

Gain adjustment GAS 1 and GAS2 (Pins 2 and 3)
!:>.Avo

Amplilication variation with R7 transmitting amplifier

-8

+8

dB

Transmitting amplifier output LN (Pin 1)
VLN(RMS)
VLN(RMS)

Output voltage at IUNE = 15mA;
dTOT=2%
dTOT = 10%

VNO(RMS)

Noise output voltage
IUNE = 15mA; R7 = 68k!"l; R7 - 8 = 200!"l
psophometrically weighted (P53 curve)

December 2, 1986

1.9

6-116

2.3
2.6

V
V

-72

dBmp

Signetics Linear Products

Product Specification

Versatile Telephone Transmission Circuit

TEA1068

DC ELECTRICAL CHARACTERISTICS (Continued) IUNE = I, = 10 to 140mA; VEE = V10 = OV; f = BOOHz; R9 = 20n;
TA = 25°C, unless otherwise specified.
LIMITS
SYMBOL

PARAMETER

UNIT
Min

Typ

Max

16.5

20.4

24.3

Receiving amplifier input IR (Pin 11)

IZ,sl

Input impedance

kn

Receiving amplifier outputs QR+ and QR- (Pins 5 and 4)

IZosl

Output impedance; single-ended

Avo
Avo

Voltage amplification from Pin 11 to Pins 4 or 5
IUNE = 15mA; R4 = 100kn;
single-ended; RL = 300n
differential; RL = 600n

/).Avo/ L\f

Variation with frequency, f

/).Avo/ L\T

Variation with temperature at IUNE

VO(RMS)
VO(RMS)
VO(RMS)

Output voltage at Icc = 0; dTOT = 2%;
R4 = 100kn; sine-wave drive
single-ended; RL = 150n
single-ended; RL = 450n
differential; CL = 47nF; (100n series resistor); f

VNO(RMS)
VNO(RMS)

Noise output voltage at IUNE = 15mA; R4
Pin 11 = IR = open
Psophometrically weighted (P53 curve)
single-ended; RL = 300n
differential; RL = 600n

= 300

4

to 3400Hz

= 50 rnA;

TA

= -25

24
30

25
31

26
32

dB
dB

-0.5

±0.2

+0.5

dB

±0.2

dB

0.3

0.38

V

0.4
O.B

0.52
1.0

V
V

50
100

pV
pV

to + 75°C

= 3400Hz

n

= 100kn;

Gain adjustment GAR (Pin 6)
/).Avo

Amplification variation
with R4 between Pins 6 and 5 receiving amplifier

-8

+B

dB

1.5

Vcc
0.3

V
V

15

pA

MUTE input (Pin 14)
V,H
V,L

Input voltage
HIGH
LOW

IMUTE

Input current

B

Avo

Reduction of voltage amplification
MIC+and MIC- to LN at MUTE = HIGH

70

Avo

Voltage amplification from
DTMF to QR+ or QR- to LN at MUTE
R4 = 100kn; RL single-ended = 300n

= HIGH

-21

-19

dB

-17

dB

Vcc
0.3

V
V

10

pA

Power-down input PO (Pin 12)
V,H
V,L

Input voltage
HIGH
LOW

Ipo

Input current

1.5
5

Automatic gain control AGe (Pin 17)
- /).Avo

IUNE
IUNE

December 2, 19B6

Controlling the gain from Pin 11 to Pins 4 and 5
and the gain from Pins 7 and B to Pin 1
R6 = 11 Okn; connected between Pins 17 and 10
Amplification control range
Highest line current for AMAX
Lowest line current for AMIN

6-117

6

dB

22
60

rnA
rnA

Signetics Linear Products

Product Specification

Versatile Telephone Transmission Circuit

FUNCTIONAL DESCRIPTION
Supply: Vee, LN, SLPE, REG
and STAB
The circuit and its peripheral circuits usually
are supplied from the telephone line. The
circuit develops its own supply voltage at Vee
and regulates its voltage drop. The supply
voltage Vce may also be used to supply
external peripheral circuits, e.g., dialing and
control circuits.
The supply has to be decoupled by connecting a smoothing capacitor between Vee and
VEE; the internal voltage regulator has to be
decoupled by a capacitor from REG to VEE.
An internal current stabilizer is set by a
resistor of 3.6kQ between STAB and VEE.
The DC current flowing into the set is determined by the exchange supply voltage VExeH,
the feeding bridge resistance RExeH, the DC
resistance of the subscriber line RUNE and
the DC voltage on the subscriber set (see
Figure 1).
If the line current IUNE exceeds the current
lee + 0.5mA required by the circuit itself, (lee
ca. 1mAl, plus the current Ip required by the
peripheral circuits connected to Vee, then the
voltage regulator diverts the excess current
via LN.
The voltage regulator adjusts the average
voltage on LN to:
VLN = VREF + ISLPE X R9
= VREF + (IUNE -lee - 0.5 X 10- 3 -led
X R9
VREF being an internally-generated temperature-compensated reference voltage of 4.2V
and R9 being an external resistor connected
between SLPE and VEE. The preferred value
of R9 is 20Q. Changing R9 will have influence
on microphone gain, DTMF gain, gain control
characteristics, side tone and maximum output swing on LN.
Under normal conditions ISLPE ~ lee +
0.5mA + lee. The static behavior of the circuit
then equals a 4.2V voltage regulator diode
with an internal resistance R9. In the audio
frequency range the dynamic impedance
equals Rl.
The internal reference voltage can be adjusted by means of an external resistor RVA. This
resistor connected between LN (Pin 1) and
REG (Pin 16) will decrease the internal reference voltage. RVA connected between REG
(Pin 16) and SLPE (Pin 18) will increase the
internal reference voltage. The current lee
available from Vee for supplying peripheral
circuits depends on external components and
on the line current. Figure 2 shows this
current for Vee> 2.2V and for Vee> 3V. Of
which 3V being the minimum supply voltage
for most CMOS circuits including a diode
December 2, 1986

voltage drop for an enable diode. If MUTE is
LOW the available current is further reduced
when the receiving amplifier is driven.

Microphone Inputs MIC+ and
MIC- and Gain Adjustment Pins
GAS 1 and GAS 2
The TEA 1068 has symmetrical microphone
inputs. Its input impedance is 64kQ
(2 X 32kQ) and its voltage amplification is
typical 52dB. Either dynamic, magnetic, piezoelectric microphones or an electret microphone with built-in FET source-follower can
be used.
The arrangements with the microphone types
mentioned are shown in Figure 3.
The amplification of the microphone amplifier
can be adjusted over a range of + or -8dB to
suit the sensitivity of the transducer used. The
amplification is proportional to external resistor R7 connected between GAS1 and GAS 2 .
An external capacitor C6 of 100pF between
GAS1 and SLPE is required to ensure stability. A larger value may be chosen to obtain a
first-order low-pass filter. The cut-off frequency corresponds with the time constant
R7 X C6.

Mute Input MUTE
A HIGH level at MUTE enables the DTMF
input and inhibits the microphone inputs and
the receiving amplifier input; a LOW level or
an open-circuit does the reverse. Switching
the mute input will cause negligible clicks at
the telephone outputs and on the line.

Dual-Tone Multi-Frequency Input
DTMF
When the DTMF input is enabled, dialing
tones may be sent onto the line. The voltage
amplification from DTMF to LN is typically.
25.5dB and varies with R7 in the same way as
the amplification of the microphone amplifier.
The signaling tones can be heard in the
earpiece at a low level (confidence tono).

Receiving Amplifier: IR, QR+,
QR- and GAR
The receiving amplifier has one input IR and
two complementary outputs, a non-inverting
output OR+ and an inverting output OR-.
These outputs may be used for single-ended
or for differential drive, depending on the
sensitivity and type of earpiece used (see
Figure 4). Amplification from IR to OR+ is typo
25dB. This will be sufficient for low-impedance magnetic or dynamic earpieces; these
are suited for single-ended drive. By using
both outputs (differential drive) the amplification is increased by 6dB and this makes
differential drive possible. This feature can be
used in case the earpiece impedance exceeds 450Q (high-impedance dynamic, magnetic or piezoelectric earpieces).

6-118

TEA1068

The output voltage of the receiving amplifier
is specified for continuous-wave drive. The
maximum output voltage will be higher under
speech conditions, where the ratio of peak
and RMS value is higher.
The amplification of the receiving amplifier
can be adjusted over a range of + and -8dB
to suit the sensitivity of the transducer used.
The amplification is proportional to external
resistor R4 connected from GAR to OR+.
Two external capacitors C4 (100pF) and C7
(lOX C4 = 1nF) are necessary to ensure
stability. A larger value of C4 may be chosen
to obtain a first-order low-pass filter. The cutoff frequency corresponds with the time constant R4 X C4.

Automatic Gain Control Input
AGC
Automatic line loss compensation will be
obtained by connecting a resistor R6 from
AGC to VEE. This automatic gain control
varies the amplification of the microphone
amplifier and the receiving amplifier in accordance with the DC line current. The control
range is 6dB. This corresponds with a line
length of 5km for a 0.5mm diameter copper
twisted-pair cable with a DC resistance of
176Q/km and an average attenuation of
1.2dB/km.
Resistor R6 should be chosen in accordance
with the exchange supply voltage and its
feeding bridge resistance (see Figure 5 and
Table 1). Different values of R6 give the same
ratio of line currents for begin and end of the
control range.
If automatic line loss compensation is not
required, AGC may be .left open. The amplifiers then all give their maximum amplification
as specified.

Power-Down Input PO
During pulse dialing or register recall (timed
loop break), the telephone line is interrupted;
as a consequence, it provides no supply for
the transmission circuit and the peripherals
connected to Vee. These gaps have to be
bridged by the charge in the smoothing capacitor C1. The requirements on this capacitor are relaxed by applying a HIGH level to
the PD input during the time of the loop break,
which reduces the supply current from typically 1mA to typically 55!1A.
A HIGH level at PD further disconnects the
capacitor at REG, with the effect that the
voltage stabilizer will have no switch-on delay
after line interruptions. This results in no
contribution of the IC to the current waveform
during pulse dialing or register recall. When
this facility is not required PD may be left
open.

Product Specification

Signetics Linear Products

TEA1068

Versatile Telephone Transmission Circuit

Side-Tone Suppression
Suppression of the transmitted signal in the
earpiece is obtained by the anti-side-tone
network consisting of R til ZUNE, R2, R3, RB,
R9 and ZSAL (see Figure B). Maximum compensation is obtained when the following
conditions are fulfilled:
a) A9.A2 = At (A3 + [ABIIZSAL])
b) [ZSAL/(ZSAL + RB)] = [ZUNE/(ZUNE + At)].

ISLPE +O.5mA

--,

lice

Icc
15

ReXCH

LN

TEA1068

I

Vee

1

DC

lo.smA

If fixed values are chosen for Rt, R2, R3 and
R9, then condition a) will always be fulfilled
provided that I RBII ZSALI  2.2V and Vee> 3V

6-119

•

Product Specification

Signetics Linear Products

TEA1068

Versatile Telephone Transmission Circuit

r'VIIIMt--"" MIC +

'--'w........~--'-I MIC-

NOTE:

The resistor marked (1) may be connected to lower
the terminating impedance. In case of sensitive microphone types, a resistor attenuator can be used to prevent overloading of the microphone inputs.

a. Magnetic or Dynamic
Microphone

c. Piezoelectric Microphone

b. Electret Microphone
Figure 3. Alternative Microphone Arrangements

QR+O(l)

QR+

QR+O
QR- 4

QR+

[]
QR-

VEE 10

0
(2)

=

QR-

4

QR-

4
LD07081S

4
LD07090S

LD070SOS

NOTE:
The resistor marked (1) may be
connected to prevent distortion
(inductive load)

a. Dynamic Telephone With
Less Than 450Q Impedance

NOTE:
The resistor marked (2) is required to
increase the phase margin (capacitive
load)

c. Magnetic Telephone With
More Than 450Q Impedance

b. Dynamic Telephone With
More Than 450Q Impedance

d. Piezoelectric Telephone

Figure 4. Alternative Receiver Arrangements

R6=oo

\ .'\.."'\ \'" '\..
\ \'\..

r-48'7f\~\ ~Ok~kQ
\

-6
20

\
40

\

\

R9=20Q

100

60

120

140

160

Figure 5. Variation of Amplification With Line Current, With RS as a Parameter

December 2, 1966

6-120

Product Specification

Signetics Linear Products

TEA1068

Versatile Telephone Transmission Circuit

Table 1. Values of Resistor RS for Optimum Line Loss
Compensation, for Various Usual Values of Exchange
Supply Voltage VEXCH and Exchange Feeding Bridge
Resistance REXCH.
REXCH (n)
400

600

1000

800
R6 (kn)

VEXCH
(V)

24

61.9

48.7

X

X

36

100

78.7

68

60.4

48

140

110

93.1

82

60

X

X

120

102

NOTE:
R9 ~ 20!1
R1
820

11S

~

11

Vee

IR

LN

QR-

1100"F

~

Vo

8

~V'

MIC+
QR+

7

R'

MICGAR

TEA1068

13

+

10~F

0---2!.

lOOk

lC4
T~~F

RL
600

C7

lnF
GAS,

10 TO 140mA

2

MUTE

R7
68k

:

~~~PF

3

PD
VEE

10
'V

6

DTMF

+C1
100j.lF

-<>~

5

REG
16

AGC

STAB

17

9

GASo
SLPE

r---

18

V,

+C3

R6

I'·7"F

R5
3.6k

R9
20

NOTES:
Voltage amplification is defined as: AVD "" 20 log IVoNII.
For measuring the amplification from MIC+ and MIG-, the MUTE input should be LOW or open; for measuring the DTMF input, MUTE should be HIGH.
Inputs not under test should be open.

Figure 6. Test Circuit for Defining Voltage Amplification of MIC +, MIC- and DTMF Inputs

December 2, 1986

6-121

•

Signetics Linear Products

Product Specification

Versatile Telephone Transmission Circuit

TEA1068

R.
620

IUNE

\.

\'5

11

LN

Vee

IR

QR-

lm"F

4

Zl
l'D"F

o-----.!
~

V,

MIC+

QR+
MIC-

:~~"F

GAR

TEA.D68

6

I

Vo
600

R4

'V

~

5
mk

C4

T~~F
C7
.nF

OTMF

IOTO.40mA

2

~

GAS,
MUTE
R7

~

PO

VEE

'0

REG
.6

:~~LF

AGC

STAB

.7

R6

9

RS
3.6k

GAS,
SLPE

lC6
mpF

3

t---

.6

R9
20

NOTE,
Voltage amplification is defined as: AVD = 2010g IVoNI!.

Figure 7. Test Circuit for Defining Voltage Amplification of the Receiving Amplifier

December 2, 1986

6-122

Signetics Linear Products

Product Specification

Versatile Telephone Transmission Circuit

TEA1068

APPLICATION INFORMATION
R1
820

R10
13

R2
130k

C5
100nF

11

LN
IR
+

Rll
QR13
DTMF
QR+
14

C4
100pF

MUTE

TEA1068

GAR

FROM DIAL
AND
CONTROL
CIRCUITS

12
PD
MIC+

MICSLPE

AS

GAS,

GAS,

18

AGC

REG
16

380
R7

CB

+C3

4.7.F

STAB

17
RS

VEE

10

AS
Uk

lOOpF

R9

20

NOTES:
The bridge to the left, the zener diode and Al0 limit the current and the voltage into the circuit during the transients.
Pulse dialing or register recall require a different protection arangement.

Figure 8. Typical Application of the TEA 1068, Shown Here With a Piezoelectric Earpiece and DTMF Dialing

December 2, 1986

6-123

Product Specification

Signetics Linear Products

TEA1068

Versatile Telephone Transmission Circuit

DTMF ...- - - - - 1 DTMF
TEA1068

DTMF
DIALER

MUTE ,. .- - - - - 1 M
PO ...-

TELEPHONE
LINE

......---1 FL

I

____________ ..JI
NOTE:
The dashed lines show an optional flash (register recall by times loop back)

a. DTMF Set With a CMOS DTMF Dialing Circuit

DTMF
PCD3320
FAMILY

MUTE 1-+-----1 M
PO ,. .-

......---1 DP

TELEPHONE
LINE

b. Pulse Dial Set With One of the PCD3320 Family of CMOS Interupted Current Loop Dialing Circuits

Vee

Voo

OTMF
TEA1068

MUTE
PO

V••

M

PC03343

OP/FL

Vss

TELEPHONE
LINE
I'C

BST76

OTMF
PC03312

c. Dual-Standard (Pulse and DTMF) Feature Phone With the PCD3343 CMOS Telephone Controller
and the PCD3312 CMOS DTMF Generator With 12 C Bus
Figure 9. Typical Applications of the TEA 1068 (Simplified)

December 2. 1986

6-124

TEA1075

Signetics

DTMF Generator for Telephone
Dialing
Product Specification
Linear Products

PIN CONFIGURATION

DESCRIPTION

FEATURES

This integrated circuit is a dual-tone
multi-frequency (OTMF) generator with
line interface for use in pushbutton telephone sets containing an electronic
speech circuit or a conventional hybrid
transformer. The Ie contains a mute
switch handling the full line current,
which allows two-wire connection between dial and speech parts. The logic
inputs can be operated with a single
contact keyboard or via a direct interface
with a microcomputer. 12L technology
allows digital and analog functions to be
implemented on the same chip. The line
interface incorporates a filter amplifier,
an output stage and a voltage stabilizer
all of which are switched off when the
speech circuit is connected to the line.
The tone generator is supplied by a
temperature compensated current stabilizer and is to be driven by a 3.58MHz
crystal.

• Two-wire connection between
dial and speech parts allowed
• Wide operating line current and
temperature range
• Operating voltage down to 1.7V
• No individual tone level
adjustment required
• Few external components
required
• All mute functions on-Chip
• Common inputs for keyboard and
microcomputer
• Temperature and line current
independent signal levels
• All pins protected against
electrostatic discharges
• On-chip output stage and line
regulator
• Single tone generation possibility

The logic inputs contain an interface
circuit to guarantee well-defined states
of the keyboard.

N Package

TOP VIEW
PIN NO. SYMBOL DESCRIPTION

VN

Negative line voltage

Fa

Filter output

ROW2

Row input 770 Hz/BCD input
Row input 852 Hz/BCD input

ROW3
MUTE

Z,

Mute switch

AOW4
ROW1

Impedance setting terminal
Row input 941 Hz/BCD input
Row input 697 Hz/BCD input

F,

Filter input

APPLICATIONS

10
11

DAC

NS

DTMF level setting

Noise suppression input

• Push button telephone set
• Hybrid telephone set

12
13

OSC
COL1
COL2
COL4
COL3
Vs
VL

Oscillator input

14

15
16
17
18

Column
Column
Column
Column
Voltage
Positive

input 1209Hz/mute input
input 1336Hz/mute input
input 1633Hz/mute input
input 1477Hz/enable input
stabilizer filter
line voltage

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

18-Pin Plastic DIP (SOT-102HE)

-25'C to + 70'C

TEA1075PN

ABSOLUTE MAXIMUM RATINGS
RATING

UNIT

Icc

Supply current

150

mA

Is

Surge current (tp < 25OIlS)

1000

mA

TA

Operating ambient temperature range

-25 to +70

'C

TSTG

Storage temperature range

-65 to + 150

'C

Voltage on any pin

(VN - 0.3) to
(VL +0.3)

V

SYMBOL

V,

PARAMETER

VL_N

Line voltage

10

V

PD

Power dissipation

750

mW

November 14, 1986

6-125

853-0981 86556

Signetics Linear Products

Product Specification

TEA1075

DTMF Generator for Telephone Dialing

BLOCK DIAGRAM

ROW 1
ROW 2
ROW 3
ROW 4
COL 4
COL 3
COL 2
COL 1

OSC

V,

15

...-+.;,;1°;""0 DAC

INTERFACE

18
14
13

12

OSCII"
LATOR

MUTE

+9

18

17

VN
DC
REGULATOR

Vs

F,

11
NS

November 14, 1986

6-126

Z,

Fo

Signetics Linear Products

Product Specification

DTMF Generator for Telephone Dialing

TEA1075

DC AND AC ELECTRICAL CHARACTERISTICS TA = 25°C; IL = 15mA; f = 1kHz, unless otherwise specified. See also
Figure 12.
LIMITS
SYMBOL

DESCRIPTION

UNIT
Min

Typ

Max

Supply

VL
VL
VL

Line voltage DC (operating mode)
IL = 15mA
IL = 50mA
IL = 120mA

VL

Line voltage DC (standby mode)

Tc

Temperature coefficient

IL

Line current range

3.3
3.7
4.5

V
V
V
-6.5

10

V
mV/oC

-8
120

mA

Transmitter output stage

RI
RI

Dynamic resistance setting range
Pin 6 open
Pin 6 connected to VN

flZo

Variation over line current RI = 600n

100

n

ATL

Gain

TBD

dB

BRL
BRL

Balance return loss from 300 up to 3400Hz
at 600n
at 900n (C L = 30nF)

dTOT

Total harmonic distortion with respect
to total output level (second-order filter)

900
600

n
n

20
20

dB
dB
-40

-25

dB

-0.31

-0.1

%

-11
-9

-8
-6

dBm
dBm

-11
-9

-6
-4

dBm
dBm

-2

2

dB

3

dB

5

ms

DTMF generator
~fD

Dividing error crystal frequency = 3.579545MHz

VLG
VHG

Tone output level (adjustable)
IL> 10mA
Lower tones
Higher tones
IL> 12mA
Lower tones
Higher tones

~VO

Tolerance on output level over temp. and current range

~VHG

Pre-emphasis higher tones/lower tones
over temp. and current range

td

Tone delay after key actuation

tsb

Switch bounce elimination

VLG
VHG

1

2

2

ms

Mute

IMSS

Mute output sink current (no key pressed)

VMT(Sat)

Saturation voltage (IMS = 75mA)

VMT

Maximum voltage (voltage set by speech part)

ISTB

Standby current (VL = 4.5V)

tD

Switch delay after key release

RM

Resistance

November 14, 1986

150

2

120

mA

500

mV

10

V

2.5

mA

10
10

6-127

/JS
kn

•

Product Specification

Signetics Linear Products

TEA1075

DTMF Generator for Telephone Dialing

DC AND AC ELECTRICAL CHARACTERISTICS (Continued)

TA = 25°C; IL = 15mA; f = 1kHz, unless otherwise
specified. See also Figure 12.
LIMITS

SYMBOL

UNIT

DESCRIPTION
Min

Typ

Max

Keyboard inputs (microcomputer inputs)
Contact off resistance

RKON

Contact on resistance

VIL
V1H
IILD

Lower frequency inputs (ROW1, 2, 3, 4)
voltage LOW
voltage HIGH
current (DC) at VIL dial mode

VIL
VIH
IIHD

Higher frequency inputs (COL 1, 2, 3, 4)
voltage LOW
voltage HIGH
current (DC) at VIH dial mode

FUNCTIONAL DESCRIPTION
Voltage Regulator
The voltage regulator switches on as a keyboard button is pressed. It regulates the
voltage drop across the IC to a nominal level
of 3.3V, shunting excess line current to maintain a working current of 8mA within the chip.
The voltage regulator switches off voltage
level when the keyboard switch is released.
The capacitor connected to input Vs provides
a low-pass filter function to avoid influence of
audio signals on the line. For a short period
during switch-on time the capacitor is directly
connected to the line to reduce overshoot
voltages to only 1V above the voltage set by
the regulator.
In order to adapt the nominal DC level to the
level as set by the speech circuit, a resistor
can be connected either between VL and Vs
or between VN and Vs. This will decrease or
increase the level respectively. During the
time the device is in the stand-by mode the
voltage stabilizer circuit will conduct again as
the DC line voltage set by the speech part
achieves 6.0V. Part of the line current then
will flow through this stabilizer.

10

kn

1.1

V
V

1.5
30

J.LA
0.5

0.9
30

Active Output Stage
The transmitter amplifier consists of a voltage
to current converter with a class-A output
stage. The circuit acts as a dynamic resistance (Ral because of the feedback from the
line to the input. This impedance can be set
by output 21 at Pin 6:
R. = 900n if Pin 6 is left open
R. = 600n if Pin 6 is connected to VN (Pin 1).
The impedance is extremely high as long as
no key is depressed (standby mode).
Figure 1 shows the connection of the dial
circuit with a speech circuit TEA1060/61. All
mute functions are performed by internal
switches. Pressing any keyboard pushbutton
switches the TEA 1075 to operating mode and
isolates the speech circuit from the line.
The line adaption then is taken over by the
dial circuit which causes:
• line voltage to be set by the voltage
regulator TEA 1075
• impedance to be set by the active
output stage TEA 1075
• audio output stage to be connected to
the line for DTMF tone transmission.

VN MUTE

Figure 1. Muting System

6-128

V
V
pA

During the standby mode (no key pressed)
the voltage on the line is set by the speech
circuit. The minimum DC operating voltage of
the dial circuit for guaranteed detection of
push button operation on the keyboard is
2.5V. The impedance is approximately 10kn
and the current consumption 2mA. The
standby current is used for the logic part as
well as driving current for the internal mute
switch which can switch the full line current
available.

OSC and DTMF Generator

Speech Muting

TEA1075

November 14, 1986

kn

300

RKOFF

The crystal oscillator frequency (3.579
545MHz) is divided by a factor of nine to give
the clock frequency. A maximum division
error of 0.31 % is achieved in the TEA1075;
CCITT recommendations are that tones
should be within 1.5% of the specified frequencies.
A bias resistor of 1 to 4.7Mn must be
connected between the oscillator input and
Vee. An external frequency generator can be
connected instead of a crystal (Figure 3).
The output from the dividers for the higher
and the lower frequency tones are symmetrical square wave pulses which contain consid-

Product Specification

Signetics Linear Products

TEA1075

DTMF Generator for Telephone Dialing

8V

~
c:::::J

12

LTEA1075

osc

Figure 2. Quartz Crystal Oscillator

~

Filter and DTMF Level

8V

~

12

~

LTEA1075

osc

Figure 3. External Frequency Generator

Deviation of ROWand COLUMN
Frequencies

ROWI
ROW2
ROW3
ROW4

COLI
COL2
COL3
COL4

approximations. Each half·cycle of the tone
waveform comprises seven discrete ampli·
tudes for the lower frequency tone and nine
for the higher frequency tone. Each amplitude
increment is generated by switching on and
off an individual current source for the dura·
tion of each step of the sine wave. The
frequency of the tones is varied by changing
the duration of each step. This circuit allows
the connection of a first·or second·order
filter, depending on the distortion requirements (see filter and DTFM level).

FREQ.
(Hz)

DEVIATION
(%)

REAL
(Hz)

697
770
852
941

-0.24
-0.28
-0.25
-0.31

695.33
767.81
849.84
938.04

FREQ.
(Hz)

DEVIATION
(%)

REAL
(Hz)

1209
1337
1477
1633

-0.31
-0.10
-0.27
-0.18

1205.23
1334.66
1473.06
1630.03

The output current from the DAC causes a
voltage drop across RTLS at Pin 10. At this
point the signal path is broken to allow
insertion of filter components in series with
the amplifier input at Pin 9. The output of this
amplifier is brought out to Pin 2 to allow
connection of filter components in the feedback path to provide additional attenuation of
the higher-order odd harmonics of the tone
frequencies.
The output amplitude of the tones is directly
proportional to the value of RTLS and can
therefore be adjusted to meet specific requirements. Figure 4 shows the output level
as a function of RTLS and Ra = 600n. If
Ra = gOOn, RTLS must be divided by 1.25.

Keyboard Inputs
Inputs for the logic control are compatible
with different types of keyboards. Using a
keyboard, tone combinations are generated:
• by connecting one of the row inputs to
one of the column inputs by means of
a single switch of the matrix, or
• by applying a dual contact keyboard
having its common row contact tied to
VN and the common column contact via
68kj.l to VL.
Single tones can be generated by connecting
a row input to VN (Pin 1) or one of the column
inputs to VL (Pin 18) through a 68kn resistor.
An anti-bounce circuit eliminates switch
bounce.

Microcomputer Mode
The inputs for the keyboard connections can
be used for direct connection to a microcomputer. If the column inputs are interconnected
and made 'HIGH' (> 1V or ICD = 30MA) the
row inputs are changed to another mode,
allowing the circuit to be driven by 4-bit data
plus an enable Signal. In this mode, it is
possible to connect a separate mute enable
signal on inputs COLI, 2 and 4 and a tone
enable input on COL3.

When RTLS is selected for the required tone
level (CFI can be calculated to avoid too
much influence of the filter characteristic on
the pre-emphasis parameter), the time constant for a single pole filter is:

I

RTLS'CFI = 26j.ls (see Figure 14).
If higher attenuation is required, a secondorder filter can be applied. The time constant
for such is:
RTLS 'CFO = RFS 'CFI = 46j.ls (see Figure
13).

erable odd·numbered harmonics. The lower·
order odd·numbered harmonics (11th and
less) are eliminated by synthesizing the tone
frequencies as crude stepped sine wave
-4

I I
I I
I I

-5

.,E
~

ill

~w

I
I
I

500

V

LOW FREQUENCY TONE GROUP

-8

....-

-7

z -8

g

-9
-10
-11

I-""

....-

400

V

V

~

,.-

S
~

...... fo""

,.V

I
I

I-""

Rns(k)

Figure 4. DTMF Level Selection

6-129

>!.

V
LOW FREQUENCY TONE GROUP

5

November 14, 1986

....-

300

I I

I
200
7

I

Signetics Linear Products

Product Specification

TEA1075

DTMF Generator for Telephone Dialing

--~--------------VL

,--.LOGIC
5k

COL,

-~---"M----+

------------~----VN

-----------~----VN

Figure 6. Configuration of Row
Inputs

Figure 5. Configuration of Column
Inputs

TRUTH TABLE MICROCOMPUTER MODE
ROW

COLUMN

1

2

3

4

1, 2, 4

3

H

H

H

H

X

X

X

X

H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L

H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L

H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L

H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L

L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

NOTE:
1. Mute "on"

= switch

November 14, 1986

TONES
(Hz)

697/1209
697/1336
697/1477
697/1633
770/1209
770/1336
770/1477
770/1633
852/1209
852/1336
852/1477
852/1633
941/1209
941/1336
941/1477
941/1633

open.

6-130

SYMBOL

1
2
3

A
4
5
6
B
7
8
9
C

.
0

#
D

MUTE 1

off
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on
on

Signetics Linear Products

Product Specification

DTMF Generator for Telephone Dialing

ROW>

TEA1075

r----\

~

--/r

I
I

I
I

I
I

I
I

I
I

I
I

II

I
I

I

I

I
I

I
I

ROW2~
ROW3~
I

ROW4

I

COL3

COL1'2'4~
I
I

LlNE~11

SIGNAL

SPEECH

DTMF

SIL.

I

SPEECH

Figure 7. Waveform Tones 69711336Hz (Dialing Number 2)

MICRO·

1101

ROW!

1/02

ROW2

1103

ROW3

1104

ROW1,

=ENABLE

~~~-----'

COL1

> - - - COl2

1/06

-

LINE
SIGNAL

> - - - COl3

-

SPEECH

COl4

Figure 8. Microcomputer Mode;
All Column Inputs Interconnected

DTMF

SPEECH

OTMF

SPEECH

Figure 9. Tone/Speech Waveform
in Circuit Diagram (Figure 8)

ROW1.

X

=g:~:)(- - - - '

1101

ROw>

1102

ROW2

1103

ROW3

COl2

1104

ROW4

~g~~

Rg~4

COL1

MICRO.

:

COL3

TEA1075
MUTE

1105

X

\"' _ _ _.1. \"'.- - -...." - -

COl1
COl2

ROW4

COMPUTER

X

=g:~:~
Rg~4 - - - - " _ _ _...J

X

X

)(

\"' _ _ _.1 \",_ _ _.1 \ " , - - -

I

TEA1075

COMPUTER

1105

MUTE

COL1

COL3

~ COl2

1106

ENABLE

COl3

LINE

SIGNAL

' - - COL4

SPEECH

Figure 10. Microcomputer Mode; Column Inputs
COL 1, 2 and 4 Interconnected
November 14, 1986

DTMF

SILENCE

DTMF

Figure 11. Tone/Speech Waveform
in Circuit Diagram (Figure 10)

6-131

SIL.

SPEECH

Signetics Linear Products

Product Specification

TEA1075

DTMF Generator for Telephone Dialing

15

T
1

VL

600

ROW2

1M
IL

VOUT

100.F

16

16

ROW3

3.58MHz

12

'"'v

ROW4

OSC

1G-120mA
15nF

TEA1075
10.F

5

MUTE

--,----

10
CAC

1
VN

F,

VMTII~----~----+---~
~~mA

NOTE:

RrLS

I I
VTLO

VTU

Figure 12. Test Circuit Measuring Amplifier Voltage Gain (ATLl Frequencies and Tone Output Levels of the Generator

November 14. 1986

6-132

z

en

~

0

!,

S.

....
or
<1>

(j)
(I)
::J
(I)

gl

m

+
] 68.F

COL2

"0
:::r
0

COL1
15

1,6

1,4

1,3

BZX79C10

8

ROW1

3

ROW2

4

ROW3

18

LINE

TEA1075

17 ROW4

~

5

w

17

w

J

10

mrnmm
mmrnrn

O.1/lF

111

mmrn@J

~

390

::J
(I)

0

t::::::

TEA1060
TEA1061

Ell2Jill@J

P

181

10

~

0.
c::

-t
(I)
(I)

T

COL3

£l

-

620

12

rx

... a
0
...0
...0

-

COL4

:::>

."

~

~

cO'

-t

0"

I

I

::J
(Q

C FO
10JjF

RTlS

3.6

NOTE:
Dial and speech functions are completely separated so line interlace is done either by TEA 1075 or TEA 1060. The diagram shows a complete DTMF telephone set including protection.
Both circuits are set to an impedance of BOOn.

"a0.
c::

-t

<:l-

..:..

16o

>
o

•

Figure 13. Application Diagram TEA 1075 Using a Second-Order Filter for Low Harmonic Distortion (CEPT TICS 34-08)

"'-J

01

en

8g:::>

en

0
-I

!I

~

'TI

(j)
CD

o·
:::J

~

fX
c:

:::J
(I)

8
."

::J

(3

-

c

CD
.....
0
0
.....

Q.

£t

0'
.....

COL4

-I

COL3

CD
CD

"C

';j

I

BZX79C1O

mlIlrn~

18
3

LINE

~I

mrnrnl!l

mrnrnl£l

TEA1075

~1

t"~¥

ROW2

El(1)[!1

1m

I~

!!O
BAT85
(2x)

0
::J
CD

0

c·
:r
<0

+
1O.F

CFI

1 1

RrLS

CARBON
MICROPHONE

, ·u--...1 _ _ _ _----L.---1--.J
CCT=15nF'

NOTES:
1. GeT connected only if confidence tone is desired.
2. The diagram shows a complete OTMF set including protection.

."

8.
-I

~

~

o

-.....I

Figure 14. Application Diagram TEA1075 Using a Single Pole Filter

01

~

en

~

s:

o·
:::J

TEA1080

Signetics

Supply Ie for Telephone Set
Peripherals
Product Specification

Linear Products

DESCRIPTION

FEATURES

The TEA 1080 is a bipolar integrated
circuit intended for use in line-powered
telephone sets to supply peripheral circuits for extended dialing and/or loudspeaking facilities.

• High input impedance for audio
signals
• High output current
• Large audio signal handling
• Low distortion
• Two modes of operation:
- regulated output voltage
- constant DC voltage drop in
series with a resistor between
line and output terminal

The Ie uses a part of the surplus of the
line current sinked normally in the voltage regulator of the applied speech/
transmission circuit.

PIN CONFIGURATION

LN08ER
VN 2

7 SO

AD 3

6 VA

RD 4

5 IF

TOP VIEW
C0013718

PIN NO. SYMBOL

LN

SO

Positive line terminal
Negative line terminal
Amplifier decoupling
Regulator input
Input low-pass filter
Output vOltage adjustment
Supply output

EA

Supply terminal of the internal

VN

AD
AD

• Low number of external
components

DESCRIPTION

IF
VA

circuit

APPLICATION
• Telephone hand sets

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

8-Pin Plastic DIP (SOT-97A)

-25·C to + 70·C

TEA1080PN

.~

BLOCK DIAGRAM
ER

!

LNo--t--~~~----~-------1--------------~--;

r-;:;-l-----f.--t
ADo--+-------+-----------t

TR2

L----+------~--------~r_ooo

A3

<1

....~----------------------~----~r_o~

""-_

TEA1080

December 2, 1986

6-135

853-1040 86701

Signetics Linear Products

Supply

Ie

Product Specification

TEA1080

for Telephone Set Peripherals

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

RATING

UNIT

10

V

VN - 0.5 to VLN + 0.5

V

t20

mA

Current into terminals
IF, VA, RD and AD

-1 to +1

mA

PTOT

Total power dissipation

See derating curve, Figure 1

TSTG

Storage temperature range

TA

Operating ambient temperature
range

TJ

Junction temperature

VLN

Positive line voltage (DC)

V

Voltage on all other terminals

11

Input current (DC)

15. 6. 4, 3

800

r-r-r.

800

1,\

-

I

200

-40 to +125

'C

-25 to +70

'C

+125

'C

1\
1\

I

"\

I
I

o

20

40

80

80

100

120

140
OP11690S

8JA

Thermal resistance from
junction to ambient in free-air

typ 120

'C/W

Figure 1. Power Derating Curve

DC ELECTRICAL CHARACTERISTICS VLN = SV; VLN(RMS) = 100mV; 10 = SmA; f = 1kHz; RI = 100kn; Rv = 7Skn; CI = 4.7j.lF;
TA = 2S'C, unless otherwise specified (see Figures 13 and 14)
LIMITS
SYMBOL

PARAMETER

UNIT
Min

Typ

Max

VLN

Operating line voltage (DC)

2.S

10

V

vLN

Momentary line voltage

1.7

10

V

Rv= 75kn
11
11
11
11

Input current
VLN = 0
VLN(RMS) = 100mV
VLN(RMS) = 1.5V
VLN(RMS) = 1.5V; 10 = 15mA

Vo

Output voltage

AVo/AT

Variation with temperature

AVo

Variation over output current and line voltage range

Is

Control current

S.7
5.7
7.5
24

mA
mA
mA
mA

3

V

0.2

mV/oC

TBD

mV

20

j.tA

5.7
6
'11
33

mA
mA
mA
mA

Rv not applied
11
11
11
11

Input current
VLN = 0
VLN(RMS) = 100mV
VLN(RMS) = 1.5V
VLN(RMS) = 1.5V; 10 = 15mA

VLN"VO

Voltage drop

10

Output current

0.6

R1-8

Series resistance (internal)

Izil

Input impedance

liNT

Internal supply current, 10 = OmA
Line voltage (AC), d

VNO(RMS)

Noise voltage; VLN

tST

Start time

< 2%;

= OmV;

FUNCTIONAL DESCRIPTION
The TEA 1080 is the interface between the
telephone line and the peripheral devices
which have to be supplied. The circuit can be

= 4V
= 600n;

VLN
RL

P53 curve

connected directly to the telephone line (via
the diode bridge) because of its high input
impedance. An inductor function is obtained

6-136

mA

20

n

0.7

mA

8

VLN(RMS)

December 2, 1986

V
30

n

1.5

V

TBD

dBm

TBD

ms

by amplifier A 1, resistor R1 _ 8 and external
low-pass RC filter.
Amplifier A2 controls both transistors Tl and
T2. To avoid a large increase of the distortion,

Product Specification

Signetics Linear Products

Supply

Ie

for Telephone Set Peripherals

the input current will flow to ground (via T2)
during the time that the momentary line
voltage drops below the output voltage.
The internal circuitry is biased by a temperature and line voltage compensated reference
current source.

Supply LN and VN
(Pins 1 and 2)
The input terminals LN and VN can be
connected directly to the line. The minimum
required DC line voltage at the input is given
by:
VLN MIN ~ I, X R,_s+ VLN MIN+ VLNIP)

2 X Is X Rv

Input Impedance IF and ER
(Pins 5 and 8)

as soon as the line voltage
VLN > 2'Is'Rv + 1,'R,_s + 0.5
The control current Is is typical 20pA.

Input Current 11 and Output 10
The minimum line current (ISET). available for
the telephone set must be sufficient to cover
the specified minimum line current (ILN MIN)
of the speech transmission IC and the maximum input current (I, MAX) required by the
application of the TEA 1080.
ISET ~ ILN MIN + I, MAX·
At VLN IRMS) < 150mV the input current I,
can be approximated by:

in which:
I,
R, _ s
VLN MIN

Vo~

TEA1080

input current
~ internal series resistance
~ minimum momentary line
voltage (1.8V at 10 ~ 5mA)
VLNIP) ~ required peak level of AC
line voltage
~

The internal current (lINT) consumption is
typical 0.7mA to 10=OmA and VLN = 5V and
will be maximum lmA at VLN = 10V.

Output Voltage SO and VA
(Pins 7 and 6)
The output SO (Pin 7) supplies the peripheral
circuits. The circuit includes two modes for
regulation of the output voltage:
Without external resistor Rv. (See Figures 2
and 15). the output voltage is expressed by

(mA)

I, = liNT + k'io

in which:
liNT = internal supply current
(0.7mA at VLN = 5V)
= correction factor which depends
on the output current
= 0.04 for 10 = lmA
= 0.12 for 10 = 30mA
For large line signals the AC line voltage may
drop below Va + OAV. The instantaneous
current flows from LN to SO (Pin 1 to Pin 7)
into the output load during the time
VLN > Va + OAV and will be internally rerouted to VN (Pin 2) during the time
VLN < Va + OAV in order to prevent distortion
of the line signal.
The input current for VLN IRMS) = IV and
without Rv can be approximated by:

Va = VLN - (I, X R, _ s + 0.5)
in which:
VLN = line voltage
I, = input current
R, _ s = internal series resistance
(typ. 20n)

If Rv is not applied. the ratio between input
current I, and output current 10 is shown in
Figure 5 for different line signal levels.

With external resistor Rv. connected between
SO and VA (see Figures 2 and 15), the output
voltage will be regulated at a constant level of

When Rv is applied, the ratio 1,110 is given in
Figure 6 for VLN = 4V and in Figure 7 for
VLN ~ 5V.

(mA)

The equivalent circuit diagram for small AC
signals is shown in Figure 4. The input
impedance is mainly determined by the negative input impedance ZI which is 10kn in
parallel with LI'LI ~ CI'RI'R,_s = 10H if
CI =4.?,.lF, RI=100kn and R'_8=20n.
CI is connected to Pin 1 and to Pin 5; RI is
connected to Pin 5 and to Pin 7.
The absolute value of the input impedance for
audio frequencies is more than 8n with
LI = 10H.

Decoupling IF and AD (See
Figure 13)
An external capacitor C, = 27pF between ER
(Pin 8) and AD (Pin 3) is required to ensure
stability. Capacitor Cd (68pF) between AD
(Pin 3) and VN (Pin 2) limits the distortion at
high output currents and high line levels.

AC Behavior
Rv Not Applied
The voltage drop VLN - Va between LN (Pin
1) and SO (Pin 7) as a function of AC line
Signal for different output currents is given in
Figure 8 while Figure 9 presents the AC line
voltage for 2% distortion as a function of the
output current for some DC line voltages.
Ry Connected (75kn)
Figures 10 and 11 show the decrease of the
output voltage, relative to Va at 10 = 0 as a
function of the AC line signal if the DC output
voltage is 3V and if the DC line voltage is 4
and 5V respectively. The AC line Signal for
2% distortion as a function of the output
current is shown in Figure 12.

10
R1~8

~=530mA

~
o
o

~

V

l/'

l/'

~='~k~

V

j/

t

Figure 2, Output Voltage vs Line
Voltage for Application Without Rv

December 2. 1986

so

Z,

vN

752

1,-t 30 A

10

L,

_rvvv-.

/'

LN

o

+~

,0

o

Figure 3, Output Voltage vs
Line Voltage (Rv = 75 or 100kn)

6-137

Figure 4, Equivalent Circuit Diagram
for Small Signals

Product Specification

Signetics Linear Products

Ie

Supply

2.5

lJ

>~

1

2.S

~~ah~i

V

-I l\.

r--- -5~

o

~

/ I

....---,--,--,,....,...,...,r"'n..,---,

1.5

/--+-I--f-+

V

!X

)

la=30mA

J~

1.6

TEA1080

for Telephone Set Peripherals

!
1
0.1

D.2

0.2
QPl1720S

NOTE:

NOTE:
VLN "" 5V, Vo"" 3V,

NOTE:
Rv = 75kO, VlN "" 4V. Vo = 3V.

Av is not applied.

Figure 5. Ratio of Input and Output
Current as a Function of AC Line
Voltage

Figure 6. Ratio of Input and Output
Current as a Function of AC Line
Voltage

Figure 7. Ratio of Input and Output
Current as a Function of AC Line
Voltage

800

II

400

IE

!

I~-~~A

0.5

1---+-+--1--=""":---1---1

~

VLN =3V

L

I,;>
...

200

../

0.2

10

-

30

20

V

~~-

p

la(mA)
NOTE:
drOT "" 2%; Rv not applied.

NOTE:
Rv is not applied.

Figure 8. Voltage Drop Between Input
and Output Voltage as a Function of
AC Line Voltage

120

80

II
T

1S A

1

40

sU
1

o

0.1

-

~

II

10130(~J

I

-.......
~

N

'-.....

~

'-.....

/

,//
.7

NOTE:
Rv ~ 75k!}, VLN - SV, Vo -.3V.

Figure 11. Output Voltage Drop as s
Function of AC Line Voltage

0.1

o

10

NOTE:
Rv"" 75kn and Vo -

20

30

av.
Figure 12. AC Line Voltage as a
Function of Output Current

6-138

=

4V, vo"" 3V.

Figure 10. Output Voltage Drop as a
Function of AC Line Voltage

l'j,

D.2

December 2, 1986

NOTE:
Rv"" 75kO, VLN

Figure 9. AC Line Voltage as a
Function of Output Current

Signetics Linear Products

Supply

Ie

Product Specification

for Telephone Set Peripherals

TEA1080

.2.~--~~A~r---~----------~~'r--~-----------'
600

v

E,

NOTE:

Vo versus VLN (with and without Rv), AC line voltage = vLN. internal supply current = tiNT. noise output voltage = vno.

Figure 13. Test Circuit Diagram DC Characteristics

VA
VLN

V

I

Rv

so
10

+

NOTE:
11 versus VLN (for different 10), input impedance = ZI. line distortion vs vLN and 10, start time"" 1ST.

Figure 14. Test Circuit Diagram AC Characteristics

SPEECH!
TRANSM.

CIRCUIT

Figure 15. Application Circuit Diagram

December 2, 1986

6-139

•

Signetics

Section 7
Radio/Audio

Linear Products

INDEX
RADIO CIRCUITS
AM Radio
TDA1072A
AN1961
TEA5550
TEA5570

AM Receiver Circuit ........................................................... .
Integrated AM TDA1072A Receiver ....................................... .
AM Radio Circuit.................. . ........................................... .
AM/FM Radio Receiver Circuit ............................................. .

7-3
7-15
7-26
7-34

FM Radio
TDA1001B
TDA7000
AN192
AN193
TDA7010
TDA7021
TEA5560
TEA6000

Interference Suppressor ...................................................... . 7-43
Single-Chip FM Radio Circuit ............................................... . 7-49
A Complete FM Radio on a Chip ......................................... . 7-54
TDA7000 for Narrow Band FM Reception .............................. . 7-69
FM Radio Circuit (SO Package) ............................................ . 7-85
Single-Chip FM Radio Circuit ............................................... . 7-90
FM/IF System .................................................................. . 7-96
FM IF System and Computer Interface (MUSTI) Circuit ............. . 7-104

Stereo Decoder
LM1870
TDA 1005A
TDA 1578A
TDA7040
TDA5580
TDA5581
{lA758
AN191

Stereo Demodulator With Blend ............................................ .
Frequency Multiplex PLL Stereo Decoder ............................... .
PLL Stereo Decoder .......................................................... .
Low Voltage PLL Stereo Decoder ......................................... .
PLL Stereo Decoder .......................................................... .
PLL Stereo Decoder .......................................................... .
FM Stereo Multiplex Decoder, Phase-Locked Loop ................... .
Stereo Decoder Applications Using the {lA758 ......................... .

7-114
7-119
7-129
7-138
7-144
7-147
7-154
7-159

AUDIO CIRCUITS
Preamplifiers
NE542
AN190
TDA1522

Dual Low-Noise Preamplifier................................................. 7-167
Applications of Low-Noise Stereo Amplifiers: NE542 .................. 7-171
Stereo Cassette Preamplifier................................................. 7-174

Tone/Volume/Switching
TDA 1029
TDA1074A
TDA1524A
TDA3810
TDA8440
TEA6300

Stereo Audio Switch ...........................................................
DC-Controlled Dual Potentiometer Circuit.................................
Stereo Audio Control...........................................................
Spatial, Stereo, Pseudo-Stereo Processor ................................
Video and Audio Switch IC ..................................................
Digitally-Controlled Tone, Volume, and Fader Control Circuit ........

7-180
7-189
7-196
7-204
7-210
7-216

II
~

I

Signetics Linear Products

Contents

Section 7 Radio/Audio

Dolby
NE5240
NE645/646
NE648/649
NE650

Dolby Digital Audio Decoder.................................................
Dolby Noise Reduction Circuit...............................................
Low Voltage Dolby Noise Reduction Circuit .............................
Dolby B-Type Noise Reduction Circuit.....................................

7-226
7-230
7-235
7-240

Power Amplifiers

Symbols and Definitions for Audio Power Amplifiers........................................
6W Audio Amplifier With Preamplifier ......................................
2 to 6W Audio Power Amplifier With Preamplifier ......................
4W Audio Amplifier With DC Volume Control ...........................
Audio Amplifier With TDA1013A ............................................
1 to 4W Audio Amplifier With Preamplifier ...............................
12W Audio Amplifier With Preamplifier ....................................
2 X 12W Audio Amplifier ......................................................
Car Radio Audio Power Amplifier up to 24W With the TDA1510 ..
12 to 20W Audio Amplifier ...................................................
40W High Performance Hi-Fi Amplifier ....................................
24W BTL Audio Amplifier .....................................................
Car Radio Audio Power Amplifiers up to 20W With the
TDA1515 ..........................................................................
20W Hi-Fi Audio Amplifier....................................................
TDA1520A
20W Hi-Fi Power Amplifier With the TDA1520A ........................
AN149
2X 12 Hi-Fi Audio Power Amplifier .........................................
TDA1521
5W Audio Amplifier.............................................................
TDA2611A
Low Voltage Mono/Stereo Power Amplifier..............................
TDA7050

TDA10l0A
TDA10llA
TDA1013A
AN148
TDA1015
TDA1020
TDA1510
AN1491
TDA1512
TDA 1514
TDA1515A
AN1481

7-245
7-246
7-251
7-255
7-258
7-267
7-272
7-276
7-280
7-288
7-293
7-296
7-300
7-307
7-312
7-317
7-322
7-326

COMPACT DISK
SAA7210
SAA7220
TDA1540
TDA1541
TDA5708
TDA5709

Decoder for Compact Disc Digital Audio System.......................
Digital Filter for Compact Disc Digital Audio System..................
14-Bit DAC (Serial Output) ...................................................
Dual 16-Bit Digital-to-Analog Converter....................................
Photo Diode Signal Processor...............................................
Radial Error Signal Processor...............................................

7-329
7-343
7-355
7-360
7-366
7-368

TDA1072A

Signetics

AM Receiver Circuit
Product Specification

Linear Products
DESCRIPTION

FEATURES

The TDA 1072A integrated AM receiver
circuit performs the active function and
part of the filtering function of an AM
radio receiver. It is intended for use in
mains-fed home receivers and car radios. The circuit can be used for oscillator
frequencies up to 50MHz and can handle RF signals up to 500mV. RF radiation and sensitivity to interference are
minimized by an almost symmetrical design. The voltage-controlled oscillator
provides signals with extremely low distortion and high spectral purity over the
whole frequency range even when tuning with variable capacitance diodes. If
required, band switching diodes can
easily be applied. Selectivity is obtained
using a block filter before the IF amplifier.

• Inputs protected against damage
by static discharge
• Gain-controlled RF stage
• Double-balanced mixer
• Separately buffered, voltagecontrolled and temperaturecompensated oscillator, designed
for simple coils
• Gain-controlled IF stage with
wide AGC range
• Full-wave, balanced envelope
detector
• Internal generation of AGC
voltage with possibility of
second-order filtering
• Buffered field-strength indicator
driver with short-circuit
protection
• AF preamplifier with possibilities
for simple AF filtering
• ElectroniC standby switch

PIN CONFIGURATION
N Package

-,___...r- LEVEL INDICATOR
lOP VIEW

APPLICATIONS
• AM receiver
• Communications receiver

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

o to

16-Pin Plastic DIP

ORDER CODE

+70'C

I

TDA1072AN

ABSOLUTE MAXIMUM RATINGS
SYMBOL

= V13-16

PARAMETER

RATING

UNIT

Supply voltage

20

V

PTOT

Total power dissipation

875

mW

V14-15

Input voltage

Vce

V14-16, V15-16

12

V

Vee

V

1114 1, 1115 1

Input current

200

mA

TA

Operating ambient temperature range

-40 to +80

'C

TSTG

Storage temperature range

-65 to + 150

'C

TJ

Junction temperature

OJA

Thermal resistance from junction to ambient

November 14, 1986

7-3

+ 125

'C

80

'C/W

853-0965 86551

Signetics Linear Products

Product Specification

TDA1072A

AM Receiver Circuit

BLOCK DIAGRAM

C13

lOnF

I~nF...c-1
-=-

-=-C14
3.3nF

RS
12k

...c-1
CIS
-=-At. =lM lOOn:

+

NOTES:
1. Coil Data: TOKO sample no. 7XNS·A7523DY; L1: N1/N2::::12/32; 00=65; 09=57.
2. Filter Data: ZF;; 7000 at R3-4 = 3kn; ZI = 4.8kn.

November 14, 1986

7-4

r I

VO(Af)

Product Spec iIi cation

Signetics Linear Products

AM Receiver Circuit

TDA1072A

DC ELECTRICAL CHARACTERISTICS

Vcc = V13-16 = 8.5V; T A = 25°C; II = 1MHz; fM = 400Hz; m = 30%; IIF = 460kHz;
measured in Block Diagram and Test Circuit, unless otherwise specified.
LIMITS

SYMBOL

UNIT

PARAMETER
Min

Typ

Max

Supplies
VCC=V13-16

Supply voltage

7.5

8.5

18

V

Icc = 113

Supply current

15

23

30

rnA

RF stage and mixer
V14-16,
V15-16

Input voltage (DC value)

R14-16,
R15-16
C14 - 16,
C15-16

RF input impedance at VI

< 300llV

R14 - 16,
R15 - 16
C14-16,
C15 - 16

RF input impedance at VI

> 10mV

V

5.5

kQ

25

pF

8

kQ

22

pF

6

kQ
pF

6.5

mAN

500

R1- 16
C1-16

IF output impedance

11NI

Conversion transconductance belore start 01 AGC

V1- 13(P.P)

Maximum IF output voltage, inductive coupling to Pin 1

11

VI(RMS)

Vcc /2

5

V

DC value 01 output current (Pin 1) at VI = OV

1.2

mA

AGC range of input stage

30

dB

500

mV

RF signal handling capability:
input voltage lor THD = 3% at m = 80%

Oscillator
losc

Frequency range

V11 -12

Oscillator amplitude (Pins 11 to 12)

0.6

R12 - 11 (EXT)

External load impedance

R12 - 11 (EXT)

External load impedance for no oscillation

RR

Ripple rejection at VCC(RMS) = 100mV; Ip = 100Hz
(RR = 20 log [V13-16N11-16])

55

V11-16

Source voltage lor switching diodes (6 X VSE)

4.2

-111

DC output current (lor switching diodes)

.1V11 _ 16

Change 01 output voltage at
.1111 = 20mA (switch to maximum load)

130
0.5

0

60

MHz

150

mV

200

kQ

60

Q
dB
V

20
0.5

mA
V

Buffered oscillator output
V10- 16

DC output voltage

0.7

V

V10-16(P-P)

Output signal amplitude

320

mV

RlO

Output impedance

170

-110(PEAK)

Output current

November 14, 1986

Q
3

7-5

mA

•

Signetics Linear Products

Product Specification

AM Receiver Circuit

TDA1072A

DC ELECTRICAL CHARACTERISTICS (Continued) vec = V1a - 16 = 8.5V; TA = 25°C; fl = 1MHz; fM = 400Hz; m = 30%;
flF = 460kHz; measured in Block Diagram and Test Circuit.
unless otherwise specified.
LIMITS
SYMBOL

PARAMETER

UNIT
Min

Typ

Max

IF, AGe, and AF stages
Va- 16•
V4-16

DC input voltage

2.0
2.4

Ra-4

3

V
3.9

kn

IF input impedance
7

pF

90

mV

Voltage gain before start of AGC

68

dB

flVa_4

AGC range of IF stages; change of
Va _ 4 for 1dB change of VO(AF);
Va_4 (REF) = 75mV

55

dB

VO(AF)

AF output voltage at Va _ 4(IF)

VO(AF)

AF output voltage at Va _ 4(IF)

IZol

AF output impedance (Pin 6)

Ca-4
Va_4

IF input voltage for THD

Va- 41V6-16

= 3%

at m = 80%

= 50/JV
= 1mV

130

mV

310

mV

3.5

kn

Indicator driver
V9-16

Output voltage at VI

V9- 16

Output voltage at VI

RL(9)

Load resistance

= OmV; RL(9) = 2.7kn
= 500mV; RL(9) = 2.7kn

2.5

20

150

2.8

3.1

1.5

mV
V
kn

Standby switch
V2- 16
V2- 16
-12
112 I

Switching threshold at Vee = 7.5 to 18V; TA
on-voltage
off-voltage
on-current at V2_16-0V
off - current at V2-16 = 20V

November 14. 1986

= -40

to +80°C
0
3.5

7-6

2.0
20
200
10

V
V

IJ.A
IJ.A

Signetics Linear Products

Product Specification

AM Receiver Circuit

TDA1072A

OPERATING CHARACTERISTICS Vee ~ 8.5V; fl ~ lMHz; m ~ 30%; fM

~ 400Hz; TA ~ 25'C, unless otherwise specified.

LIMITS
SYMBOL

PARAMETER

UNIT
MIN

TYP

MAX

RF sensitivity

VI

RF input required for S + N/N

~

6dB

1.5

IlV

VI

RF input required lor S + N/N

~

26dB

15

IlV

VI

RF input required lor S + N/N

~

46dB

150

IlV

VI

RF input at start 01 AGC

30

IlV

RF large signal handling

VI

RF input at THO

~

3%; m ~ 80%

500

mV

VI

RF input at THO

~

3%; m ~ 30%

700

mV

VI

RF input at THO

~

10%; m ~ 30%

900

mV

86

dB

91

dB

AGe range
!!NI

Change 01 VI lor 1dB change 01 VO(AF); VI(REF) ~ 500mV

b.VI

Change of VI for 6dB change 01 VO(AF); VI(REF)

~

500mV

Output signal
VO(AF)

AF output voltage at VI

~

41lV; m ~ 80%

VO(AF)

AF output voltage at VI

~

1mV

dTOT

THO at VI

~

1mY; m ~ 80%

dTOT

THO at VI

~

500mV; m

(S + N)/N

Signal-Io-noise ralio at VI

RR

Ripple rejection at VI ~ 2mV; VCC(RMS)
(RR ~ 20 log [VCCIVO(AF)])

130
240

310

mV
390

mV

0.5

%

1

%

58

dB

38

dB

37
44

dB
dB

~IF

IF suppression at RF inpul
lor symmetrical input
lor asymmetrical input

40
40

dB
dB

11 (OSC)
11 (20SC)

Residual oscillator signal at mixer output
at lose
at 2 x lose

1
1.1

IlA
Il A

~

30%
~

100mV
~

100mV; Ip

~

100Hz

Unwanted signals

~21F
~31F

~IF

Suppression 01 IF whistles at VI
AF signal 01 m ~ 30%
at IJ "'2 X IIF
at fJ '" 3 X IIF

November 14, 1986

~

151lV; m ~ 0% related 10

7-7

I

Signetics Linear Products

Product Specification

AM Receiver Circuit

FUNCTIONAL DESCRIPTION
Gain-Controlled RF Stage and
Mixer
The differential amplifier in the RF stage
employs an AGC negative feedback network
to provide a wide dynamic range. Very good
cross-modulation behavior is achieved by
AGC delays at the various signal stages.
Large signals are handled with low distortion
and the signal-to-noise ratio of small signals
is improved. Low noise working is achieved in
the differential amplifier by using transistors
with low base resistance.
A double-balanced mixer provides the IF
output signal to Pin 1.

Oscillator
The differential amplifier oscillator is temperature-compensated and is suitable for simple
coil connection. The oscillator is voltagecontrolled and has little distortion or spurious
radiation. It is specially suitable for electronic
tuning using variable capacitance diodes.
Band switching diodes can easily be applied
using the stabilized voltage V11- 16. An extra

TDA1072A

buffered oscillator output (Pin 10) is available
for driving a synthesizer. If this is not needed,
resistor RL(10) can be omitted.

Gain-Controlled IF Amplifier
This amplifier comprises two cascaded, variable-gain differential amplifier stages coupled
by a band-pass filter. Both stages are gaincontrolled by the AGC negative feedback
network.

Detector
The full-wave, balanced envelope detector
has very low distortion over a wide dynamic
range. Residual IF carrier is blocked from the
signal path by an internal low-pass filter.

AF Preamplifier
This stage preamplifies the audio frequency
output signal. The amplifier output has an
emitter-follower with a series resistor which,
together with an external capacitor, yields the
required low-pass for AF filtering.

AGC Amplifier
The AGC amplifier provides a control voltage
which is proportional to the carrier amplitude.
Second-order filtering of the AGC voltage

achieves signals with very little distortion,
even at low audio frequencies. This method
of filtering also gives fast AGC settling time
which is advantageous for electronic search
tuning. The AGC settling time can be further
reduced by using capacitors of smaller value
in the external filter (C16 and C17). The AGC
voltage is fed to the RF and IF stages via
suitable AGe delays. The capacitor at Pin 7
can be omitted for low-cost applications.

Field Strength Indicator Output
A buffered voltage source provides a highlevel field strength output signal which has
good linearity for logarithmic input signals
over the whole dynamic range. If the field
strength information is not needed, RL(9) can
be omitted.

Standby Switch
This switch is primarily intended for AM/FM
band switching. During standby mode the
oscillator, mixer, and AF preamplifier are
switched off.

Short-Circuit Protection
All pins have short-circuit protection to
ground.

lOOnF
27MHz 12pF(I)

33pF

S+N
N

S!N

OH 1--1'--11-,--,

is"

~

220

k"

zSI ..

V

+z

L

22

II)

1-,

V

20

(2)

11

12

18

I"

-60

40

THD

V

N

o
o

l'--20

j::::;

V

I

60

60

100

120

20

40

60

V
80

100

0
120

VI (dB,..V)

V,(dB"V)

NOTES:
1. Capacitor values depend on crystal type.
2. Coil Data: 9 windings of 0.1 mm dia laminated Cu
wire on TOKO coil set 7K 199CN; 00 = 80.

Figure 1. Oscillator Circuit Using
Quartz Crystal; Center
Frequency = 27M Hz

November 14, 1986

Figure 2. AF Output as a Function of
RF Input in the Test Circuit;
f, = 1MHz; fM = 400Hz; m = 30%

7-8

Figure 3. Total Harmonic Distortion
and (5 + N)/N as Functions of
RF Input in the Test Circuit;
m = 30% for (5 + N)/N Curve
and m = 80% for THO Curve

Signetics Linear Products

Product Specification

AM Receiver Circuit

TDA1072A

10

C7_16-2.2~F

........... ~18=O_F

"

~

0.1

10

20

100

200

1000

2000

Figure 4. Total Harmonic Distortion as a Function of Modulation Frequency at VI = 5mV; m = 80%; Measured in the Test
Circuit With C7 -16(EXT) = O/lF and 2.2/lF

1/

1/

,.~z
V

1/

/
/

/
o
o

20

40

60

60

100

120

Vo(dB_V)
NOTES:

With IF filter
With AF filter
With IF and AF filters

Figure 5. Indicator Driver Voltage as a Function of
RF Input in the Test Circuit

November 14, 1986

Figure 6. Typical Frequency Response Curves From Test
Circuits Showing the Effect of Filtering

7-9

•

Signetics Linear Products

Product Specification

AM Receiver Circuit

TDA1072A

Figure 7. Car Radio Application With Inductive Tuning

S+N(m=30%)

i-'

"
80

N

80

40

20

100

120

Figure 8. AF Output as a Function of RF Input Using the Circuit of Figure 7 With That of the Test Circuit

40

I

120

80

o

10

20

30

40

106

80

70

68

NOTES:
1. Wanted signal (V'AEW. VRFW): " = 1MHz; tM "" 400Hz; m:= 30%.
2. Unwanted signal (V'AEU. VRFU: f, = 900kHz; fM = 400Hz; m = 30%.
3. Effective selectivity of input tuned circuit = 21 dB.
4. Curve is for wanted Vo(AFjlunwanted Vo(AF)=20dB: VRFW. VRFU are signals at the aerial input, V'AEW, V'AEU are signals at the unloaded output of the aerial.

Figure 9. Suppression of Cross-Modulation as a Function of Input Signal, Measured in the Circuit of Figure 7
With the Input Circuit as Shown in Figure 11

November 14, 1986

7-10

Signetics Linear Products

Product Specification

AM Receiver Circuit

~VWA~ED

TDA1072A

r----,

POWER
SPLITTER
Ro

I
I

VRFW
V RFU

AERIAL

II

50

(FIG.

I
I

V'AEW
V'AEU
lORADlO
, - - . INPUT CIRCUIT

n I
I
I

I

L ___ .J

~VUNWA~ED

TC12970S

Figure 10. Input Circuit to Show Cross-Modulation Suppression (see Figure 9)

lOOH-tlftfHlH-+tI+Hll-t+H-!lHt-l

s

(801-Hl-HttHl-+t-tttHtt--++++++ttI---j

.J

4OHH+ttHtH-l+I+HlI-t-t+l+ttll-l

Li

80

\

$"801-t-+HttHl-+t-tttHtt--++++++ttI---j

I
.,zi+ z 40

N

V

1\

1\

20

201-f+HttHl-+t-tttHtt--++++++ttI---j

><

I-"
o
10

100 200

I-"

V

20

o

"

VTHD

40

80

100

o
120

Iz."..nl(kll)
Figure 11. Oscillator Amplitude as a
FunC1lon of Pins 11, 12 Impedance
In the Circuit of Figure 7

Figure 12. Total Harmonic Distortion and (S + N)/N as Functions of RF Input
Using the Circuit of Figure 7 With That of Test Circuit

•
November 14, 1986

7-11

Signetics Linear Products

Product Specification

AM Receiver Circuit

TDA1072A

L- •••••

!'t.

.'

~IJ-40

~~\

1,2,3/

1\' ".

;

'/
/1/4
1,2
-80

4

3

-100

2

\

-1

-10

3

,N

10

100

Figure 13. Forward Transfer Impedance as a Function of Intermediate Frequency for Filters 1 to 4 Shown in Figure 14,
Center Frequency = 455kHz

Table 1. Data for IF Filters Shown in Figure 14
UNIT

4

FILTER NO.

1

2

Coil data

Ll

L1

Ll

L2

Ll

Value of C
Nl: N2
Diameter of Cu
laminated wire

3900
12:32

430
13:(33 + 66)

3900
15:31

4700
29:29

3900
13:31

pF

0.09
65 (typ.)

0.08
50

0.09
75

0.08
60

0.09
75

mm

00

Schematic1
of
windings
Toko order no.

3

IV G32

:v

7XNS - A7523DY

L7PES - A0060BTG

SFZ455A
4
3
4.2
24

SFZ455A
4
3
4.2
24

4.8
57
0.70
3.6
35
52
63

3.8
40
0.67
3.8
31
49
58

~

66
33

IV G31 V
7XNS-A7518DY

C 29
•

(Nl)
(N2)
7XNS-A7521AIH

:v

G31

7XNS-A7519DY

Resonators
Murata Type
D (typical value)
AG, AL
Bandwidth (- 3d B)
S9kHz

SFZ455A
4
3
4.2
24

SFT455B
6
3
4.5
38

dB
k.l1
kHz
dB

Filter data
ZI
OB
ZF
Bandwidth (- 3dB)
S9kHz
S18kHz
S27kHz

4.2
18(L2)

52(L1)
0.68
3.6
36
54
66

4.8
55
0.68
4.0
42
64
74

NOTE:
1. The beginning of an arrow indicates the beginning of a winding; N1 is always the inner winding, N2 the outer winding.
2. Criterium for adjustment is ZF = maximum (Optimum Selectivity curve at center frequency fo = 455kHz). See also figure 13.

November 14, 1986

7-12

k.l1
k.l1
kHz
dB
dB
dB

Signetics Linear Products

Product Specification

AM Receiver Circuit

TDA1072A

3k

3k

lOOpF

lOOpF

3k

NOTE:

For filter data, refer to Table 1.

Figure 14. IF Filter Variants Applied to the Test Circuit

November 14, 1986

7·13

•

Product Specification

Signetics Linear Products

TDA1072A

AM Receiver Circuit

+
47J.1.F

*'

2.2k

470pF

.DOk

VTUNo-"""-'M~-1>----t---1t---""?"-t-""'1r-"---'
10k
lOOnF

22
BB112

lOOnF~

lOOnF*

2..2k

lOnF

r---~I-olosc

lOOnF

.-----ovIND
2.7k

12

11

10

5mH

lOOk

12k

100

*lOnF
srANDBV SWRCH

NOTES:

1. Values of capacitors depend on the selected group of capacitive diodes BB112.
2. For IF filter and coil data refer to Block Diagram.
3. The circuit includes pre-stage AGe optimized for good large-signal handling.

Figure 15. Car Radio Application With Capacitive Diode Tuning and Electronic MW/LW Switching

November 14, 1986

7-14

Signetics

AN1961
Integrated AM TDA1072A
Receiver
Application Note

Linear Products

Successor to the well-known TDA 1072, the
TDA 1072A is an inexpensive integrated AM
radio circuit that performs all the active functions between the aerial and the audio power
amplifier. Its ability to handle a wide dynamic
range of input signals and its low distortion
make the TDA 1072A suitable for use in a
wide range of car radios, domestic radios,
and tuners. The TDA 1072A brings the
TDA 1072 right up-to-date to meet present
trends in the design of the AM section of a
radio, such as varicap diode tuning, AM
stereo facility, and electronic search tuning.
Performance improvements include a 6dB
increase in sensitivity over most of the input
signal operating range, and 55dB ripple rejection between the supply voltage and the
oscillator output.
With the TDA 1072A, designers have complete freedom of choice in tuning method,
gain and selectivity, since none of the aerial
circuit has been integrated. And the
TDA 1072A is ideal for use with low-cost
hybrid IF filters.
Semi-professional and professional applications outside the AM broadcast bands using
local oscillator frequencies up to 60MHz and
down to ultrasound frequencies are also possible.
The main features of the TDA 1072A are:
• High sensitivity: 15pV aerial input for
26dB signal-to-noise ratio, m = 0.3
• Large signal handling capability, low
distortion and high signal-to-noise ratio
• Particularly suitable for use with varicap
diode tuning owing to a constant lowlevel output voltage (typ. 130mVRMS)
from the local oscillator
• Separate buffered local oscillator output
(320mVp.p, Pin 10) for digital frequency
synthesizers
• Internal AGC circuit with fast settling
time - essential in electronic search
tuning - and low distortion at low
modulation frequencies
• Logarithmic field strength output for
simple generation of stop pulses and
for driving a signal strength indicator or
meter
• Internal standby switch operated by
logic levels
• Requires very few peripheral
components
• Operates from supply voltages between
7.5 and 18V
February 1987

• Ambient operating temperature: -40·C
to +so·c.

CIRCUIT AND PERFORMANCE
Figure 1 shows the block diagram of the
TDA 1072A. Although basically similar to its
predecessor, the TDA 1072A offers:
• 6dB improvement in signal-to-noise ratio
owing to redesigned input circuitry
• 55dB improvement in ripple rejection
owing to redesigned oscillator circuitry
• New field strength curve optimized for
LED bar indicators and easy stop pulse
generation with selectable level.
The main differences in performance between the two circuits are given in Table 1.

RF Input
A redesigned input circuit gives a SdB improvement in signal-to-noise over most of the
operating range (see Figures 2 and 3). To
obtain the full improvement, the source impedance of the RF input circuit should be
reduced from I.Skn (TDA 1072) to 1kn
(fl = 1MHz), the latter value being a compromise between large signal capability (low
cross modulation) of permeability-tuned circuits and sensitivity.
In addition, this value allows low-impedance
electronically-tuned RF input stages with
FETs (especially those used as source-followers) to be used. Moreover, it allows a
home radio frame antenna to be connected
to the TDA 1072A without using a FET. The
antenna forms part of the RF input circuit coil,
which is a transformer directly connected to
the RF input of the TDA 1072A.
The input impedance at 1MHz (Pins 14 and
IS, both surge-protected) is 5.5kn II 22pF
for an RF input < 3001N; Skn II 22pF for an
input > 10mV.
Tuning behavior of the TDA 1072 and
TDA1072A is different owing to the former's
proportional AGC and the latter's more integrating AGC. With the TDA 1072, the optimal
tuning position could be identified by the rapid
increase of noise with detuning. With the
TDA 1072A, the noise only increases slowly
with detuning. This is advantageous in mechanically-tuned radios since slight detuning
(due to vibration, temperature) produces only
a small increase in noise and distortion.
For optimal tuning and sensitivity at very low
RF input signals, a 220nF metal foil capacitor

7-15

should be connected between Pin 5 and
ground. This replaces the 470nF electrolytic
capacitor needed with the TDA 1072.

Local Oscillator
The voltage-controlled oscillator provides signals of low distortion and high spectral purity
even when tuned with varicap diodes. It
delivers an almost constant output of typically
130mV for impedances from 500n to 200kn.
Internal temperature compensation circuitry
ensures ultra stable signals even on short
waves. Only a few external components are
required to complete the oscillator.
An additional buffered oscillator output is
provided (Pin 10, 320mV p•p; 200mV
TDA 1072) for use in synthesizer-tuned radios.
The oscillator of the TDA 1072A is DC referenced to ground (V11 = 4.2V, i.e., 6V BE) unlike the TDA 1072 which was DC-referenced
to the supply (V 11 = V13 -1.4V). This new
arrangement has improved the ripple rejection between the supply voltage and the DC
oscillator voltage by 55dB. Hence, frequency
modulation of the oscillator signal due to
supply voltage ripple is minimized.
NOTE:
There should always be a DC connection between Pins 11 and 12 (usually a coil or resistor)
owing to internal biasing. For stability, a 100nF
capacitor should be connected between Pin 11
and ground.

In order to use band-switching diodes as well
as transistors with the TDA 1072A, Pin 11 can
switch up to 20mA.

Mixer
A double-balanced mixer is used to generate
the IF Signal. The mixer output (Pin 1) is the
collector of a transistor pair which requires a
positive DC voltage. Since a resistive load
would reduce the maximum IF output signal,
an inductor should be used in the coupling
circuit to the IF amplifier.
High IF gain allows the IF selectivity to be
provided by an external hybrid or ceramic
filter. Hybrid IF filters are recommended for
reasons of cost. These should have a transfer
impedance of
Z21 = V34" 1 = 700n,
and an input impedance between 3kn and
5kn to prevent overloading the mixer.

•

Signetics linear Products

Application Note

Integrated AM IDA 1072A Receiver

AN1961

LOCAL OSCILLATOR
lOnF

~------If---

'esc

2.2k

22
+VBo-~~1--t~-------------t---------t-----,
16

15

14

. - - - - - - - -......- - - - - - - V1ND
2.7k

13

11

12

v,

25

170

10

9

220

TDA1072A

....--

I

I

I 3 9nF

1.

I
I
IL

__

Figure 1. TDA1072A and Test Circuit

IF Amplifier and Detector

AGe Amplifier

The IF amplifier comprises two cascaded
differential amplifier stages with independent
gain control.

This amplifier provides a control voltage proportional to the carrier amplitude. Secondorder filtering of the AGe voltage gives low
distortion over the whole range of amplitudes
(even at low modulation frequencies) in addition to fast settling time of the AGe - essential when this signal is used to derive stop
pulses in electronic search tuning. The values
of the capacitors (Pins 7 and 8) in the external
filter shown in Figure 1 provide a compromise
between short settling time and low distortion.
Both capacitors should be positioned close to
the Ie and should be connected to a main
ground to avoid coupling ground currents. In
low cost sets, the capacitor at Pin 7 can be
omitted.

The low noise full·wave balanced envelope
detector provides a linear low distortion out·
put over a wide dynamic range. Residual IF
carrier is blocked from the signal path by an
internal low-pass filter.

AF Preamplifier
The emitter-follower output with an internal
series resistor enables external low-pass filtering of the AF signal to be designed as
required.
NOTE:
In applications with ferrite rod aerials, the
external capacitors should be close to the
to minimize IF interference.

February 1987

Ie

An 86dB AGe control range holds the level of
the AM, IF signal constant (within 1dB) over a
broad range of RF input levels. In AM stereo

7-16

systems, this simplifies the matrixing of the
stereo difference signal.

Field Strength Indicator Outputl
Stop Pulse Generation
A buffered De output which is a logarithmic
function of aerial input voltage over the full
dynamic range is available for driving a field
strength indicator or for generating stop pulses in search-tuning systems (Figure 4). The
field strength curve of the TDA 1072A (Figure
5) has been optimized for LED indicator
drivers, but can still be used with meters. Up
to. 2mA may be drawn (Pin 9); and with an
input of 500mV between Pins 14 and 15, the
typical field strength output is 2.8V.
A diode is incorporated in the output stage so
that a common indicator can be used to
display FM and AM field strengths without the
need for a switch.

Signetics Linear Products

Application Note

Integrated AM IDA 1072A Receiver

AN1961

Table 1. Performance of the TDA1072A and TDA1072
SYMBOL

TDA1072A

TDA1072

UNIT

VI
VI
VI
VI

Sensitivity (see also Figure 3):
RF input voltage 1 for
(5 + N)/N = 6dB
(5 + N)/N = 26dB
(5 + N)/N = 46dB
start of AGC

1.5
15
150
30

2.2
30
550
14

J1V
J1V
J1V
J1V

VI
VI
VI

Large signal handling:
maximum RF input voltage (Pins 14 and 15)
dTOT = 3%, m = 0.8
dTOT = 3%, m = 0.3
dTOT = 10%, m = 0.3

500
700
900

600
800
1200

mV
mV
mV

dVI
dVI

AGC control range
for a 6dB change of Va
1dB change of Va

91
86

91

dB
dB

VO IAF)
dTOT
fosc

-111 max.
dV 11 /dV 13

PARAMETER

AF output voltage at VI = 1mV, fl = 1MHz, m = 0.3 and
fM = 400Hz THD of AF output voltage (see Figure 3)
VI = 500mV; m = 0.3

310
1% (m

= 0.3)

0.6-602
20
55
114

Oscillator frequency range
Oscillator output current
Ripple rejection
Field strength indication range

300
1.8% (m

mV

= 0.8)

0.6-60
15
0
114

MHz
mA
dB
dB

NOTES:
All values are typical and measured in the circuit of Figure 1 unless otherwise specified.
1. Vcc=8.5V (TDA1072A), 15V (TDA1072); fl=lMHz, fM=400Hz; m=O.3.
2. Operation at < O.6MHz possible.

•
February 1987

7-17

Signetics Linear Products

Application Note

Integrated AM TDA1072A Receiver

56

AN1961

15pF

t,

BOpF

J
12

100nF

11

TDA1072A

(FIG. 1)

-,

r---I

I

I
I

I 430pF
I
I
I
IL___ _

SFZ460A

I

I
I
I
I
I
I
I
IF FILTER
_________________
JI

Figure 2. Aerial Local Oscillator Circuits for a Permeability-Tuned Medium-Wave Car Radio Whose Performance is
Shown in Figure 3

February 1987

7-18

Signetics Linear Products

Application Note

Integrated AM TDA1072A Receiver

AN1961

Internal Supply Voltage
An internal hum filter is completed by connecting a 471'F electrolytic capacitor to Pin
13. The connections from the capacitor to Pin
13 and to the IF filter should be short.

-10

APPLICATIONS

\...::

-20

.,>-

------

TDA1072

~

S+N
(m= 0.3)

TDA1072A

26dB

-30

:!!.

Existing designs using the TDA 1072 can
usually be upgraded using the TDA 1072A.
However, some circuits may have to be
modified owing to different DC levels (Table
2) and the new field strength curve.

0

>

-so
-80
-70

Figures 6 to 11 give an indication of the
applications possible with the TDA 1072A.

Table 2_ Difference in DC
Voltages Between the TDA1072A
and TDA1072, Supply 8_5V
PIN

TDA1072A

TDA1072

10
11 & 12
14 & 15

10.7
4.2
4.2

4.5
7.2
2.7

-40

I
I
\

l

Q

j:

,,
I

\
, TDA1072

V
I

3

I

I

---

\

NOTE:
All other voltages remain unaltered.

l

I

/,
m =0.8.,.:"'::

V,N (V)
NOTE:
fM "" 400Hz; Vee == 8,5V.

Figure 3_ Performance of the AM Section of the Car Radio Circuitry
Shown in Figure 2

Vee

R2

Rl

STOP-PULSE
OUTPUT

TDA1072A

-----..1

FIELD-STRENGTH
INDICATOR
OUTPUT

Figure 4_ Simple Stop Pulse Generation Circuit

February 1987

7-19

•

Application Note

Signetics Linear Products

Integrated AM TDA1072A Receiver

AN1961

o~~~~-----L----~~----~----~----~
10-8
10-5
10-4
10-3
10-2
10-1
V,N (V)
NOTE:
11 = 1MHz, 1M = 0, m "" 0, Vee = 8.SV.

Figure 5. Field Strength Indication Voltage Characteristic for the
Circuit of Figure 3

3.3pF

90pF,

t

39pF

J
15

14

12

100nF

11

TOA1072A

(FIG. 1)

NOTE:
Permeability tuning coil: Hopf VM BC2.4.2A.

Figure 6. Aerial and Local Oscillator Circuits for a Permeability-Tuned Car Radio With Input Band-Pass Filter

February 1987

7-20

Signetics Linear Products

Application Note

Integrated AM TDA1072A Receiver

AN1961

TOK07p·7BR
179J.1.H
Q = 85

56t

121

33pf

22pF

•

C1: lOpF TO 510pF
C2: 12pF TO 442pF
15

14

22

12

11

TDA1072A
(FIG. 1)

Figure 7. Aerial and Local Oscillator Circuits for a Variable·Capacitor Tuned Medium-Wave Domestic Radio

February 1987

7-21

Signetics Linear Products

Application Note

Integrated AM TDA1072A Receiver

AN1961

v. ________~u~--1_----_1--v~~~=--u~v------------------------------~----~----~----------------__,
v~:~ -------------i------;---------------~----,

1.2k

3._
100

NOTE:
The diode-tuned RF preamplifier provides large signal handling capability, For strong aerial signals, TR1 loads the antenna, keeping the gate vortage of the BF410D and the
AC voltage across the varicap diodes low (130mV for RF input signals exceeding 5V). The slope of the AGe is set by Ra and the onset of gain control by Rb' Because the
RF gain control is derived from the output of the tuned RF preamplifier, there is no masking of desired weak signals situated close to strong ones.

Figure 8. A Varlcap Diode-Tuned Long-/Medlum-Wave Car Radio With AGC for Large Signal Handling Capability

February 1987

7-22

Signetics Linear Products

Application Note

Integrated AM TDA1072A Receiver

AN1961

TUNING VOLTAGE
0.5VTO BV

Uk

10k

lOOk
(SEE INSET)

lnF

L2

L3

75t

9t

Q= 130

51t

100nF

+

22

390

22

BF245B

Ll. L2. L3:
TOKO lOSE 161 XN

l00nF
15

14

12

11
TOKO 10EZ·RBR

r--r--...,

TDA1072A
(FIG. I}

22

TO

TO

PIN 12

PIN 11

INSET
NOTE:
For high Q and aerial decoupling, a BF245B FET is used.

Figure 9. Aerial and Local Oscillator Circuits for a Varicap Diode-Tuned Medium-Wave Domestic Radio

February 1987

7-23

Signetics Linear Products

Application Note

Integrated AM TDA1072A Receiver

AN1961

BB112

ULTRASOUND

INPUT

22

12

11

TDA1072A
(FIG. 1)

------,

r--

I
I

I

10nF

I
I
I
I
I
I

I

I
l 'OnF
I
I
I

IL.. _ _

I

_ _ _ _ _ _ _ _ _ _ _ _ ...JI

Vee (PIN 13)

NOTE:
The IF filter is tuned to 60kHz. The Ie oscillator is tuned by a varicap diode to between 25 and 35kHz.

Figure 10. Receiver for 25kHz to 35kHz Transmissions Such as Those Used In Doppler Rangefinders

February 1987

7-24

Signetics Linear Products

Application Note

Integrated AM lDA1072A Receiver

AN1961

26.5MHz

D~'2pF*

470pF

.220

TDA1072A
(AG.1)

--,

r---

I
I

I

I

I
I

I

II 3...,F

I

2.7k

I

I
I

I
I
IL __ _

100nF
IF FilTER

I
-=

I
I

I
I

-----------------~

Vcc(PIN 13)

NOTE:

A crystal Oscillator is used so that a narrOW-band hybrid IF filter can be used.

Figure 11. Aerial and Local Oscillator Circuits for a 27M Hz Receiver for Remote for Remote Control of Garage Doors,
Projectors, Curtains, etc.

REFERENCES
1.

2.

3.

"Integrated AM Radio TDA1072," Philips
Elcoma Technical Note 146, ordering
code 9396 014 60011.
JANSEN, W. and KANOW, W., "AM Stereo - A New Dimension for Car Radios,"
Electronic Components and Applications,
Vol. 3, No.4, Aug. 1981, also available as
an offprint: Philips Elcoma Technical Publication 034, ordering code 9396 020
40011.
BAHNSEN, B.P. and GARSKAMP, A.,
"Integrated Circuits for Car Radios,"

February 1967

Electronic Components and Applications,
Vol. 3, No.2, Feb. 1961, also available as
an offprint: Philips Elcoma Technical Publication 002, ordering code 9396 017
00011.

4.

KANOW, W. and SIEWERT, I., "Integrated Circuits for Hi-Fi Radios and Tuners,"
Electronic Components and Applications,
Vol. 4, No. I, Nov. 1961, also available as
an offprint: Philips Elcoma Technical Publication 040, ordering code 9396 021
10011.

7-25

5.

6.

"Single variable capacitance diode for
AM Car Radios," Electronic Components
and Applications, Vol. 4, No.4, Aug.
1962, also available as an offprint: Philips
Elcoma Technical Publication 076, ordering code 9396 036 20011.
BAHNSEN, B.P., "Voltage-controlled tuning of AM radios," Electronic Components and Applications, Vol. 2, No.2,
Feb. 1960.

Previously published as Technical Publication
152, Elcoma, February 5, 1965, The Netherlands.

•

TEA5550

Signetics

AM Radio Circuit
Product Specification

Linear Products

DESCRIPTION
The TEA5550 is an AM radio circuit,
primarily intended for use in car radios.
The Ie can reduce the costs in a car
radio.

FEATURES
• Minimum periphery
• No extra RF prestage is
necessary
• Ceramic IF filter is used
• Simple on/off switching method
allows Inexpensive band
switching in AM/FM radios
• Double-balanced mixer with large
signal handling range and
common-mode rejection
properties

• 'One-pin' oscillator, permitting
the use of variable capaCitance
diode tuning
• IF amplifier, designed for ceramic
filters
• AM envelope detector
• AGC stages
• Voltage stabilizer, for supplying
the internal circuit current and
an external current up to 20mA
• Simple DC switch for AM/FM
radios

PIN CONFIGURATION
N Package
RF INPUT 1
BYPASS
CAPACITOR

MIXER
OUTPUT

11
GROUMD 7

g~~81~~=G

10 AUDIO OUTPUT

TOP VIEW

APPLICATIONS
• Car radio
• Communications AM radio

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

16-Pin Plastic DIP (SOT-38)

o to

ORDER CODE

70°C

TEA5550N

ABSOLUTE MAXIMUM RATINGS
PARAMETER I

SYMBOL

Vcc

Supply voltages
Pin 8 Va-16
Pin 3 VS_16
Non-repetitive peak output current
(Pin 9)

RATING

UNIT

24
24

V
V

100

mA

PTOT

Total power dissipation

1100

mW

TSTG

Storage temperature range

-65 to +150

°C

TA

Operating ambient temperature range

-30 to +85

°C

NOTE:
1. Pins 4, 5, 12, and 13 are notallowed to be connected.

November 14, 1986

7-26

853-0982 86551

Signetics Linear Products

Product Specification

TEA5550

AM Radio Circuit

BLOCK DIAGRAM
IF
INPUT

MIXER OUTPUT

DOUBLE

IF AMPUFIER

BALANCED
...XER

10 AUDIO

OUTPUT
2.7k

5.61<
DETECTOR

11
TEA5550

+

INTERNAL SUPPLY

VOLTAGE

r--1>--+---t=o Vee

CONTROLLED
RF AMPLIFIER

,.

OSCILLATOR

STAND-BY SWITCH

15

TO OSCILLATOR
CIRCUITRY

November 14, 1986

7-27

VOLTAGE
STABIUZER

Signetics Linear Products

Product Specification

TEA5550

AM Radio Circuit

DC ELECTRICAL CHARACTERISTICS at VI = 0; Vce = 14.4V; TA = 25'C, measured in Figure 1.
LIMITS
SYMBOL

PARAMETER

TEST CONDITIONS

UNITS
Min

Vee

Supply voltage range (unstabilized) I

Vee

Voltage at Pin 9; -Ig = 0; V9_ 16 = VSTAB

18

V

8.7

9.2

V

50
300

mV

Voltage at Pin 10; VlO_16

1.1

V

Voltage at Pins 1 and 2; VI-16 = V2-16

5.0

V

Voltage at Pin 15; V15 _ 16
ITOT

Max

10.2
8

Change in stabilization voltage (Pin 9)
at -lg=O to 20mA; AV9_16=AVSTAB
at Vee = 10.2 to 14.4V; AV9_16 = AVSTAB

Typ

VSTAB

Total supply current; -Ig = 0

20

mA

Current drain
Pin 3
Pin 15

1
0.2

mA
mA

Current supplied from Pin 9

20

mA

Power consumption; -Ig = 0

300

mW

NOTE:

1. A stabilized supply voltage of 7.5 to 9V can also be applied at Pin 9 (Pin 8 short-circuited to Pin 9).

November 14, 1986

7-28

Signetics Linear Products

Product Specification

TEA5550

AM Radio Circuit

AC ELECTRICAL CHARACTERISTICS Vcc = 14.4V, TA = 25'C; RF condition: fl = lMHz, m = 0.3, fM = 1kHz; transfer
impedance 01 the IF lilter ZTR = VS/i3 = 850U (loaded with 3kU); measured in
Figure 1, unless otherwise specified.
LIMITS
SYMBOL

PARAMETER

UNIT

TEST CONDITIONS
Min

VI

RF input voltage;

VI

RF sensitivity at Rs = 25U lor:
S + N/N = 6dS

6.5

/lV
/lV

8
16
160
350

/lV
/lV
/lV
/lV
/lV

Input conductance at Pin 1
VI = O.lmV
VI = 100mV

0.2
0.1

ms
ms

S + N/N = 20dS

VI
VI
VI

S + N/N = 26dS
S + N/N = 46dS
S + NIN = 50dS

gie

1.5

Max

1.3

VI

gie

Vo=30mV

Typ

20

gie

Input conductance at Pin 6

0.3

ms

Coe

Output capacitance at Pin 15

20

pF

VI1
VI2

AGC range; change of RF input voltage for 10dS
change 01 AF output voltage (reference VI1 = 200mV)

86

dS

Vo

AF output voltage
VI = 10mV

180

mV
mV

/lVo

Spread of AF output voltage

±2

dS

~ol

AF output impedance (Pin 10)

2.7

kU

140

Total harmonic distortion at m = 0.8
VI = 16/lV
over most 01 the AGC range (see also
Figures 2 and 9)
VI = 25mV

THO
THO
THO

2.5
1.2

RF signal handling capability
THO = 10%; m = 0.8

%

3.5

%

400

mV
mV
dS"
dS"

350
20

ex

IF suppression at Vo = 30mV

35

Vose

Oscillator voltage
V9_16 = 8V; lose = 1468kHz; V15-8

250

NOTE:
V;a
. .
. .
*0: = 20 log - , where: Via IS Input voltage at f = 468kHz and Vib IS Input voltage at f = 1MHz.
Vib

November 14, 1986

7-29

%

300

mV

•

Signetics Linear Products

Product Specification

AM Radio Circuit

TEA5550

R3

Vee +

100

22nF

C9

R5

(PIN 8) O--"'VVIf-~

r---

p!l~
22nC:

L __
CIS

22nF

10

C14b

TEA5550

I10nF

Rl
50
15

"':"

+
Vcc

NOTES:

Coli Data
L1 - 471lH; 00 - 100; N'.3" 35 (O.1posyn) SA?

L2" O.64mH; 00 - 110; catalog no. 3122 138 91481
N1-3 = 146
N'_2'" 33
N2•3 "" 113
N4-6=9
The transfer impedance of the IF filter is: ZTR = v6/ia "" 8500 (RL"" 3kO).

Figure 1. AM Test Circuit

November 14, 1986

7-30

= 10.2 TO 18V)

~~
":"

Signetics Linear Products

Product Specification

TEA5550

AM Radio Circuit

TYPICAL PERFORMANCE (measured in Figures 3 and 4) Vcc=14.4V; TA =25°C; aerial signal conditions: fo=1MHz; m=0.3;
fM = 1kHz.

SYMBOL

PARAMETER

FIGURE 3
SINGLE-TUNING

FIGURE 4
DOUBLE-TUNING

UNIT

VI
VI

RF input voltage for:
S + N/N = 6dB
S + N/N = 26dB

4
47

4
49

jJ.V
jJ.V

Vo

AF output voltage (RL = R6 = 22kQ)
VI=1mV

160

160

mV

Signal-to-noise ratio
VI= 1mV

> 50

>50

dB

AGC range; change of RF input voltage
for 10dB change of AF output voltage
(reference Vll = 200mV); see Figures 2 and 9

88

88

dB

RF signal handling capability
THO < 10%; m = 0.8; see Figures 2 and 9

1.5

1.5

V

THO

Total harmonic distortion (over most of
the AGC range); m = 0.8; see Figures 2 and 9

1.2

1.2

%

Vosc

Oscillator voltage measured across the tank circuit

250

250

mV

S9

Total selectivity (RF and IF)

44

46

dB

B3d8

Total bandwidth (RF and IF)

4.1

4.4

kHz

0:

IF suppression at VI = 20jJ.V
tuned frequency = 600kHz
= 1600kHz

55
58

75
85

dB
dB

Image rejection at VI = 20jJ.V
tuned frequency = 600kHz
= 1000kHz
= 1400kHz

50
46
42

72
68
64

dB
dB
dB

-40
-48

-40
-48

dB
dB

SIN
Vil IV12

VI

0:

Whistle at VI = 5mV
2 X IF tweet
3 X IF tweet

APPLICATION INFORMATION
Figures 3 and 4 show the circuit diagrams of
single-tuned and double-tuned AM channels,

November 14, 1986

respectively, using the TEA5550 and an RF
tuning unit (type ALPS). The IF filter consists

7-31

of a single-tuned coil in combination with a
ceramic filter (type SFT468).

•

Product Specification

Signetics Linear Products

TEA5550

AM Radio Circuit

10

10'

10

lc

i=

10'

V,(~V)

NOTE:
Also shown is the total harmonic distortion (THO). These curves are for a single-tuned AM channel; the dummy aerial is as shown in Figure 3; fo = 1MHz; 1m = 1kHz; m = 0.3
(unless otherwise specified)

Figure 2. Typical Signal and Noise Output Voltages (Vo is AF Output Voltage) as a Function of the Input Voltage V,

DUMMY AERIAL
SIGNAL
GENERATOR

C2

AERIAL
INPUT

flF~r-

R2

vee +

100

D

Cll
22nF

C13

R3
2.2k

(PINS)

r------

e19
22nF

10

I
I
I
I
I
I
I
I
I
I

TEA5550

11

15

+

elS~

I10nF

r:-:~

-=-

":'

e17
100J.l.F

:;;J; (25V)

I

VSTAB

I
I
IL ___________ _

C12
240pF

I

C14
470nF

+
(Vee

= 10.2 TO lSV)

AM
TO PINS OF
THE TEA5560
NOTES:
Coil data: L1, L2
Tuning coils; ALPS unit MMK IIEII (for coil connections see Figure 4)
." Trimming coil (4.7pH); catalog number 3122 138 27460
L3
L4
Padding coil (200J.l.H); catalog number 3111 118 23510
L5
"" IF coil; catalog number 3122
S is AM/FM switch; for printed circuit board see Figures 4 and 5.

Figure 3. Typical Application Circuit Diagram for a Single-Tuned AM Channel In Car Radio Receivers Using the TEA5550

November 14, 1966

7-32

Product Specification

Signetics Linear Products

TEA5550

AM Radio Circuit

DUMMY AERIAL
SERIAL
INPUT

C16

C16

C22

10

TEA5550

15

C1

11

50
pF

+

r~I~~
C20
100~F

C15Y

r--uu...JG--.,__....._--+22nF

22nF

I(25V)

VSTAB

+

r

C17
4 •7 JJ.F

+

C19

r33JJ.F

+

(Vce

= 10.2 TO 16V)

FM

TO PIN 5 OF

BA3l7

THE TOA5560
NOTES:

Coil data: L1a. L1b. L2
L3
L4
L5

"" Tuning coils; ALPS unit MMK IIEII (for coil connections see Figure 7)
Trimming coil (4.7I1H); catalog number 3122 138 27460
Padding coil (200pH); catalog number 3111 118 23510
IF coil; catalog number 3122 138 91481

=
=
=

S is AM/FM switch; for printed circuit board see Figures 7 and 8.

Figure 4. Typical Application Circuit Diagram for a Double-Tuned AM Channel in Car Radio Receivers Using the TEA5550

I
NOTE:

Also shown is the total harmonic distortion (THO). These curves are for a double-tuned AM channel; the dummy aerial is shown in Figure 6; fo = 1MHz; fM = 1kHz; m = 0.3
(unless ntherwise specified).

Figure 5. Typical Signal and Noise Output Voltages (Vo is AF Output Voltage) as a Function of the Input Voltage VI

November 14, 1986

7-33

TEA5570

Signetics

AMjFM Radio Receiver Circuit
Product Specification

Linear Products

DESCRIPTION
The TEA5570 is a monolithic integrated
radio circuit for use in portable receivers
and clock radios. The Ie is also applicable to mains-fed AM and AM/FM receivers and car radio-receivers. Apart from
the AM/FM switch function, the Ie incorporates for AM a double-balanced mixer,
'one-pin' oscillator, IF amplifier with AGe
and detector, and a level detector for
tuning indication. The FM circuitry comprises IF stages with a symmetrical limiter for a ratio detector. A level detector
for mono/ stereo switch information and/
or indication completes the FM part.

FEATURES
• Simple DC switching for AM to
FM by only one DC contact to
ground (no switch contacts In
the IF channel, AF or level
detector outputs)
• AM and FM gain control
• Low current consumption
(hOT = 6mA)
• Low voltage operation (Vee = 2.7
to 9V)
• Ability to handle large AM
signals; good IF suppression
• Applicable for Inductive,
capacitive and diode tuning
• Double smoothing of AGC line
• Short-wave range up to 30MHz
• Lumped or distributed IF
selectivity with coil andlor
ceramic filters

PIN CONF.IGURATION

N Package
INPUTFMIF 1

1

GROUND

INPUT AM 2

1

AMDETOUT

OSCADJ.

14

2~~~~F

1

=~~IF

1

LEVEL DETECTOR

3

MIXER OUT 4
OUTFMIF 6
INPUT
AM/FMIF

10 ~~IMITER

FMLlMITER
-,._ _ _....r- IN
TOPYIEW

• AM and AGC output voltage
control
• Distribution of PCB wiring
provides good frequency stability
• Economic design for 'AM only'
receivers

BLOCK DIAGRAM

14

V,

o-!l-...l.----r~~_,

INDICATORI

1-....._-+.:.:'2:0 ~~~~R

OSC'L-°4----T--L.::.J

LATOR
ADJUST

OUTPUT

16

November 14, 1986

7-34

853-0984 86551

Signetics Linear Products

Product Specification

TEA5570

AMjFM Radio Receiver Circuit

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

-30·C to + 85·C

TEA5570N

16-Pin Plastic DIP

ABSOLUTE MAXIMUM RATINGS
RATING

UNITS

Vee=V7-16

SYMBOL

Supply voltage (Pin 7)

PARAMETER

12

V

Vn-16

Voltage at Pins 4, 5, 9, and 10 to Pin
16 (ground)

12

V

VS-16

Voltage range at Pin 8

15

Current into Pin 5

Vee± 0.5

V

3

mA

PTOT

Total power dissipation

see Figure 1

TSTG

Storage temperature range

-65 to + 150

·C

TA

Operating ambient temperature range

-30 to +85

·C

DC ELECTRICAL CHARACTERISTICS Vee = 6V; TA = 25·C; measured in Figure 9, unless otherwise specified.
LIMITS
PARAMETER

SYMBOL

UNIT

Min

Typ

Max

2.4

5.4

9.0

Supply (Pin 7)
Vee = V7- 16

Supply voltage

V

Voltages
Vl-16
Vl - 16
V2,3-16
V6-16
Vll-16
V13-16
V14-16

at
at
at
at
at
at
at

Pin 1 (FM)
Pin 1; -11 = 501lA (FM)
Pins 2 and 3 (AM)
Pin 6
Pin 11
Pin 13
Pin 14

1.42
1.28
1.42
0.7
1.4
0.7
4.3

V
V
V
V
V
V
V

Currents
17

Supply current

8.2

mA

-11

Current supplied from Pin 1 (FM)

4.2

6.2

50

-112

Current supplied from Pin 12

20

-1 15

Current supplied from Pin 15

30

IlA
IlA
IlA

14

Current into Pin 4 (AM)

0.6

mA

15

Current into Pin 5 (FM)4

0.35

mA

Is

Current into Pin 8 (AM)

0.3

mA

19,10

Current into Pins 9, 10 (FM)

0.65

mA

114

Current into Pin 14

0.4

mA

P

Power consumption

40

mW

November 14, 1986

7-35

•

Product Specification

Signetics Linear Products

TEA5570

AMjFM Radio Receiver Circuit

AC ELECTRICAL CHARACTERISTICS Vee = 6V;

TA = 25'C; RF condition: fl = 1MHz, m = 0.3, fM = 1kHz; transfer
impedance of the IF lilter IzTR 1= v6/14 = 2.7k; measured in Figure 9, unless
otherwise specified.
LIMITS

VI
VI
VI
VI

RF sensitivity (Pin 2)
at Vo = 30mV
at S + N/N = 6dB
at S + N/N = 26dB
at S + NIN = 50dB

VI

Signal handling (THO";; 10% at m = 0.8)

Va

AF output voltage at VI

THO

UNIT

PARAMETER

SYMBOL

IF suppression at Va

VS-16

Oscillator voltage (Pin 8)3
at fose = 1455kHz

112

Indicator current (Pin 12) at VI

Max

3.5

5.0
1.3
16
1

7.0

100

125

mV

0.5
1.0
4.0

2.5
10

%
%
%

80

= 0.3)

= 30mV2

ex

Typ

p.V
p.V
p.V
mV

20

mV

200

= 1mV

Total harmonic distortion
at VI = 100p.V to 100mV (m
at VI = 2mV (m = 0.8)
at VI = 200mV (m = 0.8)

Min

26
120

= 1mV

35

dB

160

200

mV

200

230

p.A

AC ELECTRICAL CHARACTERISTICS Vee = 6V;

TA = 25'C; IF condition: II = 10.7MHz, .::l.1 = ±22.5kHz, 1M
impedance of the IF filter IzTRI = v6/1s = 275n; measured in Figure
otherwise specified.

= 1kHz;

9,

transfer
unless

LIMITS
SYMBOL

PARAMETER

UNIT
Min

Typ

Max

90

110
6
1

130

p.V
p.V
mV

80

100

125

mV

IF part

VI
VI
VI

IF sensitivity (adjustable)4
Input voltage
at -3dB before limiting
at S + N/N = 26dB
at S + NIN = 65dB

= 1mV

Va

AF output voltage at VI

THO

Total harmonic distortion at VI

AMS

AM suppressions

= 1mV

0.3

%

50

dB

IndicatorIlevel detector (Pin 12)
112

Indicator current

250

V12-16
V12 - 16

OC output voltage
at VI = 300p.V
at VI = 2mV

0.25
1.0

325

p.A

V
V

AM to FM switch
-13

Switching current at V3 _ 16 < tV

400

NOTES:

1. Oscillator operates at V7 - 16 > 2.25V.
V
2. IF suppression is delined as the ratio " = 20 log ...!!. where: VI1 is the input voltage at I = 455kHz and VI2 is the input voltage at I = 1MHz.
VI2
3. Oscillator voltage at Pin 8 can be preset by Rose (see Figure 9).
4. Maximum current into Pin 5 can be adjusted by Rl (see Figure 9).
V3- 16
15 = R1-13 when V3 -16 = 800mV; 13 = 400jlA.
5. AM suppression is measured with 1M = 1kHz, m = 0.3 lor AM; 1M = 400Hz, AI = ± 22.5kHz lor FM.

November 14, 1986

7-36

p.A

Signetics Linear Products

Product Specification

TEA5570

AMjFM Radio Receiver Circuit

FACILITY ADAPTATION
Facility adaptation is achieved as follows (see Figure 9):

1.2

1\

OJ!

\

\

OA

\

o

-&0

Facility

Component

FM sensitivity

R1 fixes the current at Pin 5 (15 = - - - 400J.lA)
(gain adjustable ± 10dB)4
Rl
R11 and coil tapping
Rose
R7. R11
R7

AM
AM
AM
AM

V3-16

sensitivity
oscillator biasing
output voltage
AGe setting

\

100

150

Figure 1. Power Derating Curve

s+NI
(fu- 1kHz;M-o.3)

r--~ r+illftrEf
-20

J

,...r--.r--.

~E~R~NbE LEVel

Iii'

jdB.1OOmv

l!.

~

+'

1-,

-40

-80

\

""" NI

THD(MJOJI)-

-4

"

......

,-

-8

-fL

-20

NOTES:
1. AGe range (figure of merit, FOM).
2. Measured at 'I" 1MHz in Test Circuit Figure 9.

NOTES:
- - Sensitivity (VI) at Vo = 30mV; m = 0.3.
- - - - Output voltage {Vol at VI = 2mV; m = 0.3.
Measured at 11 = 1MHz in Test Circuit Figure 9.

Figure 2. Signal, Noise, and Distortion as a Function of
Input Voltage (VI)

November 14. 1986

Figure 3. Sensitivity (VI), Output Voltage (Vo), as a
Function of Temperature Behavior TA

7-37

II

Signetics Linear Products

Product Specification

TEA5570

AMjFM Radio Receiver Circuit

-.-_..-

/

-4
l~"

Ii" -8
:g.

v

-12

S+N

... v

....

(AI- ±225kHzj

/
-20

V-

Ii"
:g.
~

~EVkL

/

1/

REtERkNbE
OdB=1OOmV

-40

:

..l
-18

-80

-20

40

4

2

THD ...... ........... N
(AI=
±225kHzj

o

120

80

VccM
NOTES:
- - - Sensitivity (VI) at Vo "" 30V; m == 0.3: 6V application.
•••••••••• Sensitivity (VI) at Vo"" 30mV; m ... 0.3: 4.5V application.
- - - - Output voltage (Vo) at VI- O.2mV; m" 0.3.
Measured at fl- 1MHz in Test Circuit Figure 9. for application Vee = 6V.
Also shown is the sensitivity for Vee == 4.5V application (Figure 15).

NOTE:
Measured at I, = 10.7MHz in Test Circuit Figure 9.

Figure 4. Sensitivity (VI) and Output Voltage (Vo) as a
Function of Supply Voltage (Vecl

Figure 5. Signal, Noise, and Distortion as a Function of
Input Voltage (VI)

1.6

3110

f--

'"
-

I~~
~-

-2

...... .....

-4

-

\
\

-4
-8

0

.....

1\

I

100

/
oV
o

-20

-20

2

II

/

Ii" -8
:g.

-18

j

AM

200

-12

\.

IFM

/

/

V
20

1.0

80

o

80

4

VccM

O,P092BOS

NOTES:
NOTES:
- - - Sensitivity at - 3dS limiting.
- - - - Output voltage (Vo) at VI=1mV;
~f "" ±22kHz.
Measured at fl- 10.7MHz in Test Circuit FIgUre 9.

Figure 6. Sensitivity (VI) Output
Voltage (Vo) as a Function of
Temperature Behavior (TA)

November 14. 1986

- - - Sensitivity at -3dS limiting: Vee = 6V
application.
•••••••••• Sensitivity at -3dS limiting: Vee = 4.5V
application.
- - - - Output voltage (Vo) at VI = 1mV;
~f = ± 22.5kHz.
(Vo) as a function 01 supply voltage (Vee).
Measured at '1"" 10.7MHz in Test Circuit Figure 9.

Figure 7. Sensitivity (VI) and
Output Voltage

7-38

NOTES:
AM fl = 1MHz; (VI). Measured in
Figure 9; Vcc=6V; R12_16=5k.

Figure 8. Indicator Output Current
(1,2) and DC Output Voltage (V,2-16)

Signetics Linear Products

Product Specification

AMjFM Radio Receiver Circuit

TEA5570

R8
88

R3

100
C5

56pF

+

R8
2.7k

C4

110nF

R5

T

~\.)

C10
lOO "F

880

C9

1100nF

AM INPUT
CI

J~f1~11

r
:

0

C2~

'22nF

I,..L
":::"

R9

18k

R10
18k

!:::-::!:=.....~

TEA5570

6~ FMIN~fl
YSiGNAL

.L

-=

50

GENERATOR

13

R,
1.1k

INDICAlOR

NOTES,
Coil Data
The transfer impedance of the IF filter is:
AM: IZTRI=V6/i4=2.7kn (SFZ 455A).

FM: IZTRI=vSIi5=27sn (SFE 10.7 MS).
See also Figures 10, 11, 12, and 13.

Figure 9. Test Circuit

FM IF Coils (Figure 9)

AM IF Coils (Figure 9)

NOTES,
N1 = 73
N2 = 73
N3 =
9
C16 = 1BOpF (internal)
Wire = O.07mm dia.
TOKO sample no. 7 MC-7P

Figure 10. IF Bandpass Filter (L 1)

November 14, 1986

NOTES,
N1 "" 90
N2 = 7
Wire = O.07mm dia.
TOKO sample no. 7 BR-7P

Figure 11. Oscillator Coil (L2)

7-39

NOTES,
N1 = 5
N2 = 5
N3 = 4
C19 = 82pF (internal)
Wire = 0.1 mm dis.
TOKO sample no. 119 AN-7P

Figure 12. Primary Ratio Detector
Coli (L3)

•

!

Signetics Linear Products

Product Specification

TEA5570

AMjFM Radio Receiver Circuit

NOTES,
N1 = 2
N2 = 6
N3 = 6
C20 = 68pF (internal)
Wire"" 0.1 mm dia.
TOKO sample no. 119 AN-7P

Figure 13. Secondary Ratio Detector
Coil (L4)

APPLICATION INFORMATION Figures 14 and 16 show the circuit diagrams for the application of 6V AM MW/LW, and 4.5V
AM/FM channels, respectively, using the TEA5570. Figure 15 shows the circuitry for the
TEA5570.

15
C10

13.9nF

R3
5k

TEA5S70

12
C3

*22nF
...

_ "_
' _ m m _ _' "

16

C4

~'fJ ~~-~• I .
I

I

I
_
L_:
__________________________ ..JI

"::"

vs

Coli Data

l3

L4

l5

Nl
N2
N3
C
N1
N2
C
Nl
N2

-

73
73

=
9
'" 180pF
... 146
=
9
- 180pF

-

90
6

Figure 14. Typical Application Circuit for 6V AM MW/LW Reception Using the TEA5570

November 14, 1986

7-40

DEfECTOR

"::"--0 OUTPUT

Product Specification

Signetics Linear Products

TEA5570

AM/FM Radio Receiver Circuit

rO
r;;Fii
IF
1

~

"I

,~

5.6k

MIXER

r

2.2k

":"'

~

2

~

x~~

L...-r--

,1

14

6

4

5

IF

~

~?J,.

~

i...--

i...--

FM-=

S.6k

I

.
-=

DECOUPLING LINE

5.1k

,~

lj' Sf
DETECTOR

OSCILLATOR
SWITCHING
CIRCUIT

~~FlER

DETECTOR

-S3

*r

-54

I

~
-=
15

*

111111111

S3!
54

12

AGCAMPS

.....TEA5570

-=

~6

8

Figure 15. TEA5570 Circuit Diagram

November 14, 1986

1

82

5.1k

0- g
~

.. 13 ..

~

t t t t

Is

-=

'""'l

-

LIMITER

CURRENT
STABILIZER
CIRCUIT

,~

J

,~

~/-

V

-=

I

7

~
AM

~

AMPUFIER

11

10

I.

;

I

3

9

13

7-41

•
,.
•••

Signetics Linear Products

Product Specification

TEA5570

AMjFM Radio Receiver Circuit

M

M

~

A

r.=~'---------~-----¥~----~------~r-~----------~r-~---¥~-----o~~

Ctt
220pF

R7
10k

Nl
M
10k

C7
1nF

R1
470k

AFC
(lOFM

FRONl'END)
14

13
15

TEA5570

12

(t---+--'

16

'-::I

R10
47k

DETEC10R
OUTPUT

I
I

I

I
I

I

: ____________________
~
L

Coil Data
L2 N1
N2
N3

C
L3

N1
N2
N3

L4

N1
N2
N1
N2
N3
N1
N2
N3
N4

C
L5

L6

C

I ' -....~>-_.J

~

--=
=

-

3
8
1
82pF
33
113
9
180pF
90
6
33
113
9
50
50
4.5
6.5
82pF

--

...

=
-

Figure 16. Typical Application Circuit for 4.5V AM/FM Reception Using the TEA5570 With Coils and
Single-tuned Ratio Detector (With Silicon Diodes)

November 14. 1986

7-42

TDA1001B, BT

Signetics

Interference Suppressor
Product Specification

Linear Products
DESCRIPTION
The TDA 1001 B is a monolithic integrated circuit for suppressing interference
and noise in FM mono and stereo receivers.

FEATURES
• Active low-pass and high-pass
filters
• Interference pulse detector with
adjustable and controllable
response sensitivity

• Noise detector designed for FM
IF amplifiers with ratio detectors
or quadrature detectors
• Schmitt trigger for generating an
interference suppression pulse
• Active pilot tone generation
(19kHz)
• Internal voltage stabilization

APPLICATIONS
• FM mono and stereo receivers
• Noise suppression

PIN CONFIGURATION
N, D Packages
INPUT

GROUND

1

HIGH PASS

BUFFER
OllT

ALTER IN

HIGH PASS
FlLTEROUl

LOW PASS

AMP IN

LOW PASS

THRESHOLD

AMP OUT

SUP.COMP

5

AF OUTPUT

6

11 THRESHOLD
10 ~\W PULSE

PILOT

TONE IN
PilOT

TONE OllT "'"IL-_ _ _r-'

TOP VIEW

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

16-Pin Plastic DIP (SOT-38)

o to 70 0 e

TDA1001BN

l6-Pin Plastic SO
(50-16; SOT-l09A)

o to 70 0 e

TDA1001BTD

ORDER CODE

BLOCK DIAGRAM

•
AF 0l1TPUT

November 14, 1986

7-43

853-0962 86551

Signetics Linear Products

Product Specification

Interference Suppressor

TDA1001B, BT

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

Vcc

Supply voltage (Pin 9)

VIN

Input voltage (Pin 1)

lOUT
-lOUT

Output current (Pin 6)

PD

Total power dissipation

RATING

UNIT

18

V

Vce

V

1
15

mA
mA

see derating
curves Figure 3

TSTG

Storage temperature range

-65 to +150

·C

TA

Operating ambient temperature range

-30 to +80

·C

DC ELECTRICAL CHARACTERISTICS Vee = 12V; TA = 25·C, unless otherwise specified
LIMITS
SYMBOL

UNIT

PARAMETER
Min

Typ

Max

Input stage

IZll l

Input impedance (Pin 1) f = 40kHz

45

Rll

Input resistance (Pin 1) with pin 2 not connected

600

111

Input bias current (Pin 1) Vl-16 = 4.8V

R02

Output resistance (Pin 2)
unloaded

low-ohmic

R2-16

Internal emitter resistance

5.6

6

kn
kn
15

p.A

kn

Low-pass amplifier

RI3

Input resistance (Pin 3)

113

Input bias current (Pin 3)

7

p.A

R04

Output resistance (Pin 4)

5

n

Av

Voltage gain (V41V3)

10

Mn

1.1

V

Suppression pulse stage

los5

Input offset current at Pin 5 during the suppression time ts

50

200

nA

Output stage

R06

Output resistance (Pin 6)

R6-16

Internal emitter resistance

low-ohmic
6

kn

G15/6

Current gain (15116)

85

dB

Pilot tone generation (19kHz)

IZlsl

Input impedance (Pin 8)

IZ071

Output impedance (Pin 7) Pin 8 open

150

1

107

Output bias current (Pin 7)

0.7

GI7/S

Current gain (17/Is)

n
kn

1

1.3

3

mA
mA

High-pass amplifier

RI15

Input resistance (Pin 15)

ISIAS15

Input bias current (Pin 15)

7

p.A

R014

Output resistance (Pin 14)

5

n

AV14/15

Voltage gain (V14/15)

November 14, 1986

10

Mn

1.4

7-44

V

Signetics Linear Products

Product Specification

Interference Suppressor

DC ELECTRICAL CHARACTERISTICS

TDA1001B, BT

(Continued) vee = 12V; TA = 25'C, unless otherwise specified.

J

LIMITS
SYMBOL

PARAMETER
Min

Typ

Max

1.5

2.0

2.5

I

UNIT

AGe amplifier; interference and noise detectors
R13 - 14

Internal resistance (Pins 13 and 14)

±V14int m
±V 14n m

Operational threshold voltage (uncontrolled); peak value (Pin 14)
01 the interference pulse detector
01 the noise detector

V11 -1SM

Output voltage (peak value; Pin 11)

5.2

5.6

6.4

V

112M

Output control current (Pin 12) (peak value)

150

200

250

p.A

1012

Output bias current (Pin 12)

2.5

6

p.A

V12 - 9
or:

Input threshold voltage lor onset 01 control (Pin 12)
(VI(tr)O + 3d B)

360

425
0.66VBE

500

mV
mV

15
6.5

kS1
mV
mV

Suppression pulse generation (Schmitt trigger)
V11 -1S
V11 - tS

Switching threshold (Pin 11)
1: gate disabled
2: gate enabled

3.2
2.0
1.2

Ll.V11 - t6

Switching hysteresis

10s11

Input offset current (Pin 11)

1010M

Output current (Pin 10) gate disabled; peak value

IR10

Reverse output current (Pin 10)

V1O - tS

Sensitivity (Pin 10)

APPLICATION INFORMATION

0.6

1

V
V
V
100

nA

1.4

mA

2

p.A

2.5
Vec

= 12V;

TA

= 25'C; I = 1kHz,

V

unless otherwise specilied.
LIMITS

PARAMETER

SYMBOL

UNIT
Min

Typ

Max

Vcc

Supply voltage range (Pin 9)

7.5

12

16

V

Icc

Quiescent supply current (Pin 9)

10

14

18

mA

Signal path
V1- 1S

DC input voltage (Pin 1)

1z111

Input impedance (Pin 1); I

VS- 1S

DC output voltage (Pin 6)

Ros

Ou1put resistance (Pin 6)

4.5

= 40kHz

2.4

Av6/1

Voltage gain (VSIV1)
- 3dB point 01 low-pass lilter

VI(P_P)

Sensitivity lor THO

VS- 1S(P-P)

Residual interference pulse after suppression (see Figure 4);
Pin 7 to ground; VI(TR)M = 100mV; (peak-to-peak value)

cc int

Interference suppression at R13 = 0;5, S VI(RMS) = 30mV;
I = 19kHz (sine wave); V1(TR)M = 60mV; Ir = 400Hz

November 14, 1986

kS1
2.8

V

low-ohmic

1(-3dB)

< 0.5%

V

35

0

(peak-to-peak value)

1.2

7·45

0.5

1

kHz

1.8

V
3

20

dB

70

30

mV
dB

Product Specification

Signetics Linear Products

TDA1001B, BT

Interference Suppressor

APPLICATION INFORMATION (Continued)

Vee = 12V; TA=25°C; f=1kHz, unless otherwise specified.

LIMITS
SYMBOL

UNIT

PARAMETER
Min

Typ

Max

8
18

11
28.5
1

14
40

Interference processing
Input signal at Pin 1; output signal at Pin 10

VI(TR)M
VI(TR)M

Suppression pulse threshold voltage; control function OFF
(Pin 9 connected to Pin 12); RMS value 1
measured with sinewave input signal
f= 120kHz; -V 1O - 9 > 1V
at R13 =
at R13=2.7k.l1
voltage difference for safe triggering/non-triggering (RMS
value) measured with interference pulses
f = 400Hz (see Figure 4); peak value
at R13 =
at R13 = 2.7k.l1

ts

Suppression pulse duration 2

VI(TR)RMS
VI(TR)RMS
AVI(RMS)

On

on

19
45

mV
mV
mV

mV
mV

24

27

30

p.s

2.3

3.3
8.2

4.3

mV
mV

Noise threshold feedback control 1, 3

VNI(RMS)
VNI(RMS)

Noise input voltage (RMS value)
f = 120kHz sinewave
for V 12 - 9 = 300mV
at R13 =
at R13 = 2.7k.l1
for V12-9 = 425mV (VI(TR)O + 3d B)
at R13 =
at R13 = 2.7k.l1
for V12 _ 9 = 560mV (VI(TR)O + 20dB)
at R13 =
at R13 = 2.7k.l1

V06(RMS)
V06(RMS)

Amplification control voltage by interference intensity4
VI(RMS) = 50mV; f = 19kHz;
VI(TR)M = 300mV; RMS value
at repetition frequency fR = 1kHz
at repetition frequency fR = 16kHz

VNI(RMS)
VNI(RMS)
VNI(RMS)
VNI(RMS)

On
On

7.3
16.5

On

33

45
107

49
45

mV
mV
57

mV
mV

56
65

mV
mV

NOTES:

1. The interference suppression and noise feedback control thresholds can be determined by R13 or a capacitive voltage divider at the input of the high-pass filter
and they are defined by the following formulae:

VI(TR) = (1 + R13/Rs X VI(TR)O in which Rs = 2krl;
VNI = (1 + R13/Rs X VNIO in which Rs = 2krl.
2. The suppression pulse dura1ion is determined by C11

=

2.2nF and R11

=

6.Skrl.

3. The characteristics of the noise feedback control is determined by R12 (and R10).
4. The feedback control of the interfence suppression threshold at higher repetition frequencies is determined by R10 (and R12).
5. The 19kHz generator can be adjusted with R7-16 (and R7-8). Adjustable is not required if components with small tolerances are used, e.g., .6..R

< 1%

and

<1.<2%.
6.

Measuring conditions:

The peak output noise voltage (VNO. CCITI filter) shall be measured at the output with a deemphasizing time t = 50!,s (R
of OdS is Va INT with the 19kHz generator short-circuited (Pin 7 grounded).

November 14, 1986

7-46

= 5krl, C = 10nF); the reference value

Signetics Linear Products

Product Specification

Interference Suppressor

1DA1001B, B1

1

1--

ro-- ~

"

t\.
"

0.5

~

'\
100

50

"'

150

NOTES:
- - - I n plastic DIP package (TDA1001B)
- - -In plastic SO package (TDA1 001 BT); mounted on a ceramic substrate of 50 X 15 x O.7mm.

Figure 1. Power Derating Curves

±V~tr) M

(mY)

SQUARE·WAVE
INPUT VOLTAGE

SUPPRESSION
PULSE (TRIGGER)
OUTPUT

V, ....

I
I

t. =27iJ.S

(y)

..I

-1.5

OVER SHOOT OF THE
LOW-f'ASS FILTER
OUTPUT
VOLTAGE

V6-16
(my)

-1
-2

OFFSET VOLTAGE
AND DRIFT

10

20

30

40

TlME(p.o)
NOTE:
At the input (Pin 1) a square wave is applied with a duration of ITR = 10jl5 and with rise and fall times tA "" IF'" 10n5.

Figure 2. Measuring Signal for Inter1erence Suppression

November 14, 1986

7-47

50

Signetics Linear Products

Product Specification

TDA1001B, BT

Interference Suppressor

HIGH-PASS FILTER

Y,

TOYce

4.7pF

(10 TO 18Yl

t

91k

22k

':'

~,t

220£1

Uk

cn

220nF

2.2nF

lanF

82

15k
1110

16

15

13

14

TOYce

10

TDA1001B

l20k

(R~o-jl-~+--_-J
4.7"F

.---_ _ _---1

3.9

68

::;J;PF

nF

6.8nF

1.5k

82k

r
Yo

3.9

2.1k

nFI
":'"

"';"

18kHz FILTER
LOW-PASS FILTER

Figure 3. Application Circuit Diagram

November 14, 1986

7·48

2.2k

Vee

TDA7000

Signetics

Single-Chip FM Radio Circuit
Product Specification

Linear Products

FEATURES

DESCRIPTION
The TDA7000 is a monolithic integrated
circuit for mono FM portable radios
where a minimum of peripheral components is important (small dimensions
and low costs).
The IC has an FLL (Frequency-Locked
Loop) system with an intermediate frequency of 70kHz. The IF selectivity is
obtained by active RC filters. The only
function which needs tuning is the resonant circuit for the oscillator which selects the reception frequency. Spurious
reception is avoided by means of a mute
circuit, which also eliminates weak, noisy
input signals. Special precautions are
taken to meet the radiation requirements.

PIN CONFIGURATION

• RF input stage
•
•
•
•
•
•

N Package

Mixer
Local oscillator
IF amplifier/limiter
Phase demodulator
Mute detector
Mute switch

18 g~~RELATOR

MUTING
CAP
AUDIO
FREQOUT
NOISE
SOURCE
lDOP
FILTER CAP

APPLICATIONS

17 DEMODCAP

12 :;~MITER

1"INT
CAP (1'0 PIN 9)

• Mono FM Portable Radios

2NIJ INT

11

CAP

• LAN
• Data Receivers
• SeA Receiver

15f INT

CAP (1'0 PIN 7)

L--_---'

10

~LTERCAP
W~~IN11)

TOP VIEW

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

18·Pin Plastic DIP (SOT-102HE)

o to

ORDER CODE

+70·C

TDA7000N

ABSOLUTE MAXIMUM RATINGS
PARAMETER

SYMBOL

RATING

UNIT

12

V

Vee-0.5 to
Vee + 0.5

V

Vee

Supply voltage (Pin 5)

V6 - 5

Oscillator voltage (Pin 6)

PTOT

Total power dissipation

See derating curve Figure 1

TSTG

Storage temperature range

-55 to + 150

TA

Operating ambient temperature range

October 10, 1986

o to

+60

7-49

•

·C
·C

853-0893 85938

Signetics Linear Products

Product Specification

TDA7000

Single-Chip FM Radio Circuit

BLOCK DIAGRAM
RF INPUT

11

10

IF FILTER
12K

4.7K

2.2K

Cy

Cs

2.2K

__

(+~~~O-~--~----------~----+-------------+---------------------------~---------- ~
AF OUTPUT

October 10, 1986

7·50

Signetics Linear Products

Product Specification

TDA7000

Single-Chip FM Radio Circuit

DC ELECTRICAL CHARACTERISTICS Vce - 4.5V; TA - 25°C; measured in Figure 3, unless otherwise specified.
LIMITS
PARAMETER

SYMBOL

Vee

Supply voltage

TEST CONDITIONS

UNIT

(Pin 5)

Min

Typ

Max

2.7

4.5

10

V

Icc

Supply current

Vec -4.5V

8

rnA

Ie

Oscillator current

(Pin 6)

280

iJ.A

V14 - 16

Voltage

(Pin 14)

1.35

V

12

Output current

(Pin 2)

60

iJ.A

V2-16

Output voltage

(Pin 2) RL - 22kn

1.3

V

AC ELECTRICAL CHARACTERISTICS Vec - 4.5V; TA - 25°C; measured in Figure 3 (mute switch open, enabled);
IRF - 96MHz (tuned to max. signal at 5pN EMF) modulated with 111 - ± 22.5kHz; 1M - 1kHz; EMF - 0.2mV (EMF voltage at a source
impedance 01 75n); RMS noise voltage measured unweighted (I - 300Hz to 20kHz), unless otherwise specified.
LIMITS
SYMBOL

PARAMETER

TEST CONDITIONS

UNIT
Min

-3dB limiting; muting disabled
EMF

Sensitivity (see Figure 2)
(EMF voltage)

EMF

Signal handling (EMF voltage)

SIN

Signal-to-noise ratio

THD

Total harmonic distortion

THD

6

SIN = 26dB

5.5

< 10%;

AM suppression 01 output voltage

RR

Ripple rejection

V6-S(RMS)

Oscillator voltage (RMS value)

I1fose

Variation 01 oscillator Irequency

S+300

I1f

= ± 75kHz

I1f = ± 22.5kHz

dB

= 1kHz)

(Pin 6)

= 1V)

50

dB

10

dB

250

mV

60

kHzlV

45
Selectivity

dB
35
±300

kHz

I1Vo = 3dB
measured with pre-emphasis
(t = 501lS)

10

kHz

RL = 22kn

75

AFC range

BW

Audio bandwidth

Vo RMS

AF output voltage (RMS value)

RL

mV

60

%

S-300
I1fRF

200

2.3

(ratio 01 the AM output signal referred to
the FM output signal)
FM signal: 1M = 1kHz; I1f = ± 75kHz
AM signal: 1M = 1kHz; m = 80%

Supply voltage (I1Vee

IlV

0.7

= ±75kHz

(I1Vee = 100mV; I

Max

1.5

-3dB muting

I1f

AMS

Typ

Load resistance

= 4.5V
Vee = 9.0V
Vee

mV
22
47

kn

NOTES:
1. The muting system can be disabled by feeding a current of about 20pA into Pin 1.
2. The interstation noise level can be decreased by choosing a low-value capacitor at Pin 3. Silent tuning can be achieved by omitting this capacitor.

October 10, 1986

7-51

Signetics Linear Products

Product Specification

TDA7000

Single-Chip FM Radio Circuit

- 1.5

'\
\.

\

'\
\

0.5

\

'\

o
100

-50

150

Figure 1. Power Derating Curve

siN

y

'I

i'0-20 '2"-- J 1

--

>

~
-1

-40

"

THO

Ne

.BE

,/

-80
10-8

10-5

10-4

10-3

10-2

10-1

EMF(V)otRs = 750

NOTES:

1. The muting system can be disabled by feeding a current of about 20iJA into Pin 1.
2. The interstation noise level can be decreased by choosing a low-value capacitor at Pin 3. Silent tuning can be achieved by omitting this capacitor.
Conditions: OdS = 75mV; fAF = 96MHz
for 5 + N curve: af == ± 22.5kHz 'M - 1kHz
for THO CUNe: ~f'" ± 75kHz 1M = 1 kHz

Figure 2. AF Output Voltage (Va) and Total Harmonic Distortion (THO) as a Function of the EMF Input Voltage (EMF)
With a Source Impedance (Rs) of 7S!l: (1) Muting System Enabled; (2) Muting System Disabled

October 10, 1986

7-52

Signetics Linear Products

Product Specification

TDA7000

Single-Chip FM Radio Circuit

220pF

330pF

17

18
CORRELATOR

2.7K

1.4V

IF FILTER
12K

UK

2.2K

ENABLED

2.2K

DISABLED

Cv

Cs

VCCo-~MU~T=E~S~W=IT~C~H~-t----------~--~~----------~-------------------------4------------~
AF OUTPUT

Figure 3_ Test Circuit

October 10, 1986

7-53

Signefics

AN192
A Complete FM Radio on a
Chip
Application Note

Linear Products

Authors: W.H.A. Van Dooremolen and
M. Hufschmidt
Until now, the almost total integration of an
FM radio has been prevented by the need for
LC tuned circuits in the RF, IF, local oscillator
and demodulator stages. An obvious way to
eliminate the coils in the IF and demodulator
stages is to reduce the normally used intermediate frequency of 10. 7MHz to a frequency
that can be tuned by active RC filters, the op
amps and resistors of which can be integrated. An IF of zero deems to be ideal because it
eliminates spurious signals such as repeat
spots and image response, but it would not
allow the IF signal to be limited prior to
demodulation, resulting in poor signal-tonoise ratio and no AM suppression. With an
IF of 70kHz, these problems are overcome
and the image frequency occurs about
halfway between the desired signal and the
center of the adjacent channel. However, the
IF image signal must be suppressed and, in
common with conventional FM radios, there

is also a need to suppress interstation noise
and noise when tuned to a weak signal.
Spurious responses above and below the
center frequency of the desired station (side
tunings), and harmonic distortion in the event
of very inaccurate tuning must also be eliminated.
We have now developed a mono FM reception system which is suitable for almost total
integration. It uses an active 70kHz IF filter
and a unique correlation muting circuit for
suppressing spurious signals such as side
responses caused by the flanks of the demodulator S-curve. With such a low IF, distortion would occur with the ± 75kHz IF swing
due to received signals with maximum modulation. The maximum IF swing is therefore
compressed to ± 15kHz by controlling the
local oscillator in a frequency-locked loop
(FLL). The combined action of the muting

circuit and the FLL also suppresses image
response.
The new circuit is the TDA7000 which integrates a mono FM radio all the way from the
aerial input to the audio output. External to
the IC are only one tunable LC circuit for the
local oscillator, a few inexpensive ceramic
plate capacitors and one resistor. The
TDA7000 dramatically reduces assembly and
post-production alignment costs because
only the oscillator circuit needs adjustment
during manufacture to set the limits of the
tuned frequency band. The complete FM
radio can be made small enough to fit inside a
calculator, cigarette lighter, key-ring fob or
even a slim watch. The TDA7000 can also be
used as receiver in equipment such as cordless telephones, CB radios, radio-controlled
models, paging systems, the sound channel
of a TV set or other FM demodulating systems.

A Laboratory Model of the TDA7000 in a Complete FM Radio. Also Shown is the TDA7010T
in the SO Package Against a CM Scale

February 1987

7-54

Signetics Linear Products

Application Note

A Complete FM Radio on a Chip

Using the TDA7000 results in significant improvements for all classes of FM radio. For
simpler portables, the small size, lack of IF
coils, easy assembly and low power consumption are not the only attractive features.
The unique correlation muting system and the
FLL make it very easy to tune, even when
using a tiny tuning knob. For higher-performance portables and clock radios, variablecapacitance diode tuning and station presetting facilities are often required. These are
easily provided with the TDA 7000 because
there are no variable tuned circuits in the RF
signal path. Only the local oscillator needs to
be tuned, so tracking and distortion problems
are eliminated.

AN192

BRIEF DATA
SYMBOL

DESCRIPTION

TYP

MAX

UNIT

Typical supply voltage

4.5

V

lee

Typical supply current

8

mA

fRF

RF input frequency range

VRF-3dB

sensitivity for -3dS limiting EMF
with Zs = 75n, mute disabled

1.5

p.V

VRF

Maximum signal input for
THD < 10%, fl.f = ±75kHz
EMF with Zs = 75n

200

mV

Vo

Audio output (RMS) with
RL = 22kn, fl.f = ±22.5kHz

75

mV

The TDA 7000 is available in either an 18-lead
plastic DIP package (TDA7000), or in a 16-pin
SO package (TDA7010T). Future developments will include reducing the present supply voltage (4.5V typ.), and the introduction of
FM stereo and AM/FM versions.

February 1987

MIN

Vee

7-55

1.5

110

MHz

Signetlcs linear Products

Application Note

A Complete FM Radio on a Chip

AN192

vp

1+4,5V)

39
pF

C12
150pF

ell
3.3nF

130 nH

,---

15

14

ClO

13

12

11

1,4V

loon

o

111

700n

I
o

I
o

I
I

TDA7000

~R_R~~R
mute control

MUTE

I.F
FILTER

LOOP

FILTER

C7

C1

C4

150nF

10nF

3,3 nF

Lf. output

NOTES:
1. These pins are not used in the SO package version (TDA7010T) AP "" All-Pass filter.
2. L2 is printed on the experimental PCB (Figure 12),
L1 - Toka Mel0S No.S14 HNE 150013513.
C 20 = Toka NO.2A-1SBT-R01.

Figure 1. The TDA7000 as a Variable Capacitor-Tuned FM Broadcast Receiver

February 1987

7-56

10

C8
180pF

Signetics Linear Products

Application Note

AN192

A Complete FM Radio on a Chip

CIRCUIT DESCRIPTION
As shown in Figure 1, the TDA7000 consists
of a local oscillator and a mixer, a two-stage
active IF filter followed by an IF limiter/
amplifier, a quadrature FM demodulator, and
an audio muting circuit controlled by an IF
waveform correlator. The conversion gain of
the mixer, together with the high gain of the IF
limiter/amplifier, provides AVC action and
effective suppression of AM signals. The RF
input to the TDA7000 for -3dB limiting is
1.5!,V. In a conventional portable radio, limiting at such a low RF input level would cause
instability because higher harmonics of the
clipped IF signal would be radiated to the
aerial. With the low IF used with the
TDA7000, the radiation is negligible.
To prevent distortion with the low IF used with
the TDA7000, it is necessary to restrict the IF
deviation due to heavily modulated RF signals to ± 15kHz. This is achieved with a
frequency-locked loop (FLL) in which the
output .from the FM demodulator shifts the
local oscillator frequency in inverse proportion to the IF deviation due to modulation.

Active IF Filter
The first section of the IF filter (AF1A) is a
second-order low-pass Sail en-Key circuit with
its cut-off frequency determined by internal
2.2k!1 resistors and external capacitors C7
and Ca. The second section (AF1 B) consists
of a first-order bandpass filter with the lower
limit of the passband determined by an internal 4.7k!1 resistor and external capacitor C .
"
The upper limit of the passband is determined
by an internal 4.7k!1 resistor and external
capacitor C1Q. The final section of the IF filter
consists of a first-order low-pass network
comprising an internal 12k!1 resistor and
external capacitor C,2' The overall IF filter
therefore consists of a fourth-order low-pass
section and a first-order high-pass section.
Design equations for the filter are given in
Figure 2. Figure 3 shows the measured response for the filter.

AF1A

>-C:::J--Q12

C7
~---~---~,~,---v-~

Sallen-Key circuit
ASK=--.-9-with a = 2R,Ca
2
1 +Jwa-w b
b=R,2C7Ca
1
Vb
_
With 10 = 21rA,v'lC7C8) and Q = - ; - = O.5V ~

;c,

A
SK

9

1+(j~X01)-vJ

'""

:7,

For ~ = 3.3nF. Ca "" 180pF; Q = 2.1 and 10 = 94kHz

Bandpass circuit

1
Asp "'" 1

+ iwC 10R z

X

1

jwC 1 ,R z
+ jwC 11 R 2 + jwCl0R2
1

1

for f LP = - - and f HP

211H2C,O

f LP

+ JwC l0R2

1

=-211"R2C'1

1

ABP=;;X (1+j

~)(1-j¥)+1

For Cl0 = 330pF, en "" 3.3nF, fLP = 103kHz, fHp::: 10.3kHz

Low-Pas. circuit
1
ALP=---1 + jwC12Ra
1
forfLP=--

211'C12Ra

1
ALP = 1 +j

'*'

For C12 "" 150pf:

fLP =

8804kHz.

Figure 2. IF Filter of the TDA7000

FM Demodulator
The quadrature FM demodulator M2 converts
the IF variations due to modulation into an
audio frequency voltage. It has a conversion
gain of -3.6V /MHz and requires phase quadrature inputs from the IF limiter/amplifier. As
shown in Figure 4, the 90· phase shift is
provided by an active all-pass filter which has
about unity gain at all frequencies but can
provide a variable phase shift, dependent on
the value of external capacitor C,7.

February 1987

ap

SaHen - Key filter

7-57

LP

Signetics Linear Products

Application Note

A Complete FM Radio on a Chip

AN192

+ lO r-------r-------r-------,-------,-------,

I

Vo/Vi

IdS)

°h~-ci---+---+---+_--___i
-10r---+~--t---_+---~--___i

-20~--+-~~+_---~---+---___i

-40~'------~------+----~~~-----+------~

-60r----+------+------+------+--~~

200

300

Figure 3. Measured Response of the IF Filter

'---------... to correlator

17

lC,'7
With R2-0
¢ = -2tan-'wR,C 17
for ¢=-90°,

1

C17=~=

wR,

227pF

for fL ,.. 70kHz
To improve the performanace of the all-pass filter
with the amplitude-limited IF waveform. R2 has been
added.
Since this influences the phase angle. the value of
en must be increased by 45%, i.e., to 330pF for
flF = 70kHz.

Figure 4. FM Demodulator Phase Shift Circuit (All-Pass Filter)

February 1987

7-58

IF Swing Compression With the
FLL
With a nominal IF as low as 70kHz, severe
harmonic distortion of the audio output would
occur with an IF deviation of ± 75kHz due to
full modulation of a received FM broadcast
signal. The FLL of the TDA 7000 is therefore
used to compress the IF swing by using th'e
audio output from the FM demodulator to shift
the local oscillator frequency in opposition to
the IF deviation. The principle is illustrated in
Figure 5, which shows how an IF deviation of
75kHz is compressed to about 15kHz. The
THD is thus limited to 0.7% with ± 22.5kHz
modulation, and to 2.3% with ± 75kHz modulation.

Correlation Muting System With
Open FLL
A well-known difference between FM and AM
is that, for FM, each station is received in at
least three tuning positions. Figure 6 shows
the frequency spectrum of the output from
the demodulator of a typical portable FM
radio receiving an RF carrier frequency-modulated with a tone of constant frequency and
amplitude. In addition to the audio response
at the correct tuning point in the center of
Figure 6, there are two side responses due to
the flanks of the demodulator S-curve. Because the flanks of the S-curve are nonlinear, the side responses have increased
harmonic distortion. In Figure 6, the frequency and intensity of the side responses are
functions of the signal strength, and they are
separated from the correct tuning point by
amplitude minima. However, in practice, the
amplitude minima are not well defined because the modulation frequency and index
are not constant and, moreover, the side
response of adjacent channels often overlap.
High performance FM radios incorporate
squelch systems such as signal strengthdependent muting and tuning deviation-dependent muting to suppress side responses.
They also have a tuning meter to facilitate
correct tuning. Although the TDA7000 is
mainly intended for use in portables and clock
radios, it incorporates a very effective new
correlation muting system which suppresses
interstation noise and spurious responses
due to detuning to the flanks of the demodulator S-curve. The muting system is controlled
by a circuit which determines the correlation
between the waveform of the IF signal and an
inverted version of it which is delayed (phaseshifted) by half the period of the nominal IF
(180°). A noise generator works in conjunction with the muting system to give an audible
indication of incorrect tuning.

Signetics Linear Products

Application Note

A Complete FM Radio on a Chip

-'"

F.M.

--

DEMODULATOR

fif

MIXER AND
LF. AMPLIFIER

AN192

Va'
r-r--

(CONVERSION

GAIN 0,.

-3,6V/MHz I

et7 ±

t

3300F

'OK

1
eel

VOLTAGE-

lOOP AMPLIFIER

CONTAOLLED

560

LOCAL
Cdiode

osc.

(SLOPE S ,.
-l.14pF/v~

A L • -1.06

Co =

CEXT + eSTRAY + CoroDE with open loop = 49pF at fa = 96MHz
ALSfo
Feedback factor (j = - 2Co
Open-loop conversion gain = 0 = -3.eV/MHz
D
Closed-loop conversion gain = ~ "" O.6aV/MHz for fa = 96MHz

open-loop gain
Modulation compression factor K =

closed-loop gain

3.eVIMHz
- - - - '" 5

-

O.684V/MHz

dfRF

L\ftF""K"
for 6.fRF = 75kHz, dfose ~ 60kHz, AflF ~ 15kHz

.6f!f"'85~70=15kH2

f'ose t f ,
Afosc",SOkHz

f if "" 70kHz

.1
tLf rf -75kHz

I

I.
f'if'" 85 kHz

I.
I
I
95,9

95,93

95,99....

96

96,075

Figure 5. IF Swing Compression with the FLL

February 1987

7-59

96,1

Signetics Linear Products

Application Note

A Complete FM Radio on a Chip

~I
~I
V.,j

I
I

I
Val

I
I

I

""I

AN192

200kHz

r--t

••
-• •
-• .
•

Vrf·l0mV

ImV

100lolV

-• ••

I

10llV

3.V

I

Vaf

I

I
Vaf

Vaf

I
I
I
II

1.51lV

~
'-'-'

-----,
I.V

~

enlarged in
I, vertal
direction

Do

'--------

O.1Io1V

____ J

tuned frequency

Figure 6. Audio Signal of a Typical Portable Radio as a Function of Tuned
Frequency With RF Input as a Parameter. The Modulation
and Amplitude are Both Constant

February 1987

7-60

Signetics Linear Products

Application Note

A Complete FM Radio on a Chip

Figure 7 illustrates the function of the muting
system. Signal IF' is derived by delaying the
IF signal by half the period of the nominal IF
and inverting it. With correct tuning as shown
in Figure 7a, the waveforms of the two signals
are identical, resulting in large correlation. In
this situation, the audio signal is not muted.
With detuning as shown in Figure 7b, Signal
IF' is phase-shifted with respect to the IF
signal. The correlation between the two
waveforms is therefore small and the audio
output is muted. Figure 7c shows that, because of the low Q of the IF filter, noise
causes considerable fluctuations of the period of the IF signal waveform. There is then
small correlation between the two waveforms
and the audio is muted. The correlation muting system thus suppresses noise and side
responses due to detuning to the flanks of the
demodulator S-curve. Since the mute threshold is much lower than that obtained with
most other currently-used muting systems,
this muting system is ideal for portable radios
which must often receive signals with a level
only slightly above the input noise.
As shown in Figure 8, the correlation muting
circuit consists of all-pass filter AP2 connected in series with FM demodulator all-pass
filter API and adjusted by an external capacitor to provide a total phase shift of 180'. The
output from AP2 is applied to mixer M3 which
determines the correlation between the undelayed limited IF signal at one of its inputs and
the delayed and inverted version of it at its
other input. The output from mixer M3 controls a muting circuit which feeds the demodulated audio signal to the output when the
correlation is high, or feeds the output from a
noise source to the output to give an audible
indication of incorrect tuning when the correlation is low. The switching of the muting
circuit is progressive (soft muting) to prevent
the generation of annoying audio transients.
The output from mixer M3 is available externally at Pin 1 and can also used to drive a
detuning indicator.

AN192

large
correlation
with

correct

I.F:

tuning

LF.

small

correlation
due to

JLJlS
JLJlS

(a)

JLf1JL
JUU1

(b)

deluning

I.F.'

very small

I.F.

JLJLJ

I.F.'

~

correlation
due to

noise

(e)

Figure 7_ Function of the Correlation Muting System

F.M.
DEMODULATOR
ALL-PASS
FILTER
I Fig. 4)

18

--_ _

TOA70QO
(Fig. 1)

pin 6

300kll
Ov

--4.-------+----------------+

pin 16

Figure 14. Variable-Capacitance Diode Tuning for the Local Oscillator. Additional
Measures Must be Taken to Ensure Temperature Stability

Circuit With Variable-Capacitance
Diode Tuning
Since it is only necessary to tune the local
oscillator coil, it is very simple to modify the
circuit of Figure 1 for variable-capacitance
diode tuning, The modifications are shown in
Figure 14, A circuit board layout for the
modified receiver and a photograph of a
complete laboratory model are shown in Figure 15,

Narrow-Band FM Receiver
The TDA 7000 can also be used for reception
of narrowband FM signals, In this case, the
local oscillator is crystal-controlled (as shown
in Figure 16) and there is therefore hardly any
compression of the IF swing by the FLL The
deviation of the transmitted carrier frequency
due to modulation must therefore be limited
to prevent severe distortion of the demodulated audio signal.

a.f. output

ov

L2

NOTE:
This is the same PC Board as shown in Figure 12.

Figure 15. Circuit Board Layout and Complete Model of a TDA7000 Radio With Variable-Capacitance Diode Tuning

February 1987

7-66

Signetics Linear Products

Application Note

A Complete FM Radio on a Chip

AN192

Lf. input

+4,5 V
C15

18

C23
220pF

13

17

12

TDA7000

"

10

(lee Fig. 1)

The component values in Figure 16 result in
an IF of 4.5kHz and an IF bandwidth of 5kHz
(Figure 17). If the IF is multiplied by N, the
values of capacitors C17 and C,a in the all·
pass filters and the values of filter capacitors
C7 , Ca, C, o, Cll , and C'2 must be multiplied
by lIN. For improved IF selectivity to achieve
greater adjacent channel attenuation, sec·
ond-order networks can be used in place of
C'0 and C ll .
In this circuit the detuning noise generator is
not used. Since the circuit is mainly for
reception of audio signals, the audio output
must be passed through a low-pass Chebyshev filter to suppress IF harmonics.

C1
150nF

AUDIO AMPLIFIER AND
DETUNING INDICATOR
CIRCUITS
Audio output stages suitable for use with the
TDA7000 are shown in Figures 18 and 19.
Figure 20 shows how the muting signal can
be used to operate an LED to give an
indication of detuning.

Figure 16. A Narrow-Band FM Receiver With a Crystal-Controlled Local Oscillator

20 109

i

V.

'20~
+10

(dB)

01F===~~:;;e+
-10

- 20

I

r

-3+
_OOt
-50

-600~------~--------~lb~-------'~~~-f-(-kH-,-)~2'0

Figure 17. IF Selectivity for the Narrow-Band FM Receiver

February 1987

7-67

Signetics Linear Products

Application Note

A Complete FM Radio on a Chip

AN192

+3V----------~--------,

65n
earpiece

ee550e

~v----~--+---------4

PO ·O,4mW,d-l0%
quiescent current. 4 mA

NOTE:
1. These components replace R2 and C2 in Figure 1.

Figure 18. A 0.4mW Transistor Audio Output Stage Without Volume Control for
Driving an Earpiece

+4.5 V
to pin 5

TOA7000

22n
~

220.F

~;

5

8

from pin 2

3

~~..o'"
r-

7

9

TDA7000
1)
1)

22.n

4.7
nF

5,6kn

(109)

4

"-.J

6

220Jlf

2

POWER

AMP

VA

+~I4,7

1

n
8n

10?.nF
"

TO. ,.

F

1.8 nF:~

ov

NOTE:
1. These components replace C2 and R2 in Figure 1. Po = 250mW. d=10% quiescent current=8mA.

Figure 19. An Integrated 250mW Audio Output Stage

from pin
3V1
of the
TOA7000
+
(F~1)

=:J
470 kn

ACKNOWLEDGEMENTS

REFERENCE

The authors wish to acknowledge the infor·
mation provided by D. Kasperkovitz and H.v.
Rumpt for incorporation in this article.

KANOW, W. and SIEWERT, I., 'Integrated
circuits lor hi·li radios and tuners', Electronic
Components and Applications, Vol. 4, No. I,
November 198 I, pp. 11 to 27.

Bessa
~

ov
Figure 20. A Detunlng Indicator Driven
by the Mute Signal From the TDA7000

February 1987

7-68

Signetics

AN193
TDA7000 for Narrow-Band
FM Reception
Application Note

Linear Products

Author: W. V. Dooremolen

INTRODUCTION
Today's cordless telephone sets make use of
duplex communication with carrier frequencies of about 1.7MHz and 49MHz.

1.7MHz

• In the base unit incoming telephone
information is frequency-modulated on a
1.7MHz carrier.
• This 1.7MHz signal is radiated via the
AC mains line of the base unit.
• The remote unit receives this signal via
a ferrite bar antenna.
• The remote unit transmits the call
signals and speech information from the
user at 49MHz via a telescopic
antenna.
• The base unit receives this 49MHz FMmodulated signal via a telescopic aerial.

Today's Remote Unit Receivers
In cordless telephone sets, a normal superheterodyne receiver is used for the 1.7MHz
handset. The suppression of the adjacent
channel at, e.g., 30kHz, must be 50dB, and
the bandwidth of the channel must be
6 - 10kHz for good reception. Therefore, an
IF frequency of 455kHz is chosen. Since at
this frequency there are ceramic filters with a
bandwidth of 9kHz (AM filters), the 1.7MHz is
mixed down to 455kHz with an oscillator
frequency of 2.155MHz. Now there is an
image reception at 2.61 MHz. To suppress
this image sufficiently, there must be at least
two RF filter sections at the input of the
receiver.
The ceramic IF filter with its subharmonics is
bad for far-off selectivity, so there must be an
extra LC filter added between the mixer
output and the ceramic filter.
After the selectivity there is a hard limiter for
AGC function and suppression of AM.
Next, there is an FM detector which must be
accurate because it must detect a swing of
± 2.5kHz at 455kHz; therefore, it must be
tuned.

February 1987

2.155MHz

Figure 1. Remote-unit Receiver: 1.7MHz

Figure 1 shows the block diagram which
fulfills this principal. The total number of
alignment points of this receiver is then 5:
2 RF filters
1 Oscillator
1 IF filter
1 FM detector
5 Alignments

A Remote Unit Receiver With
TDA7000
The remote unit receiver (see Figure 2) has
as its main component the IC TDA 7000,
which contains mixer, oscillator, IF amplifiers,
a demodulator, and squelch functions.
To avoid expensive filtering (and expensive
filter-adjustments) in RF, IF, and demodulator
stages, the TDA7000 mixes the incoming
signal to such a low IF frequency that filtering
can be realized by active RC filters, in which
the active part and the Rs are integrated.
To select the incoming frequency, only one
tuned circuit is necessary: the oscillator tank
circuit. The frequency of this circuit can be set
by a crystal.

IMAGE RECEPTION
For today's concept, a number of expensive
components are necessary to suppress the

7-69

image sufficiently. The suppression of the
image is very important because the signal at
the image can be much larger than the
wanted signal and there is no correlation
between the image and the wanted signal.
In a concept with 455kHz IF frequency, the
1.7MHz receiver has image reception at
2.155MHz. In the TDA7000 receiver, the IF
frequency is set at 5kHz. Then the 1.7MHz
receiver (with 1.695MHz oscillator frequency)
has image reception at 1.69MHz, which is at
10kHz from the required frequency (see Fig·
ure 3).
An IF frequency of 5kHz has been chosen
because;
• this frequency is so low, there will be
no neighboring channel reception at the
image frequency.
• this frequency is not so low that at
maximum deviation (maximum
modulation) distortion could occur
(folding distortion, caused by the higherorder bessel functions)
• this frequency gives the opportunity to
obtain the required neighboring channel
suppression with minimum components
in the IF selectivity.

•

Signetics Linear Products

Application Note

AN193

TDA7000 for Narrow-Band FM Reception

+Vs

+

1

NE5535

NeS535

[> [>
A.F.FtLTER

A.F.AMPL

TALK

o

STANDBY

pi
Figure 2

CIRCUIT DESCRIPTION
(see Figure 2)
When a remote unit is at "power-on" in the
"standby" position, it is ready to receive a
"bell signal". A bell signal coming through
the telephone line will set the base unit in the
mode of transmitting a 1.7MHz signal, modulated with, e.g., 0.75kHz with ± 3kHz deviation.

/
/
/
/

/

The AF output of the demodulator (Pin 4) is
fed to the AF filter and AF amplifier NE5535.

The RF Input Circuit
As the image reception is an in-channel
problem, solved by the choice of IF frequency
and IF selectivity, the RF input filter is only
required for stopband selectivity (a far-off
February 1987

+I

,
I
I
I
I
I
I

The ferrite antenna of the remote unit receives this Signal and feeds it to the mixer,
where it is converted into a 5kHz IF signal.
Before the RF signal enters the mixer (at Pins
13 and 14) it passes RF selectivity, taking
care of good suppression of unwanted signals from, e.g., TV or radio broadcast frequencies. The IF signal from the mixer output
passes IF selectivity (Pins 7 to 12) and the IF
amplifier/limiter (Pin 15), from which the output is supplied to a quadrature demodulator
(Pin 17). Due to the low IF frequency, cheap
capacitors can be used for both IF selectivity
and the phase shift for the quadrature demodulator.

/

/

r---

/

~
'.F

"MAGE

-5kHZ/DIV.

'OSC
OP01101$

Figure 3
selectivity to suppress unwanted large signals
from, e.g., radio broadcast transmitters).
In a remote unit receiver at 1.7MHz, this filter
is at the ferrite rod. Figure 4 shows the
bandpass behavior of such a filter at 1. 7MHz.

The Mixer
The mixer conversion gain depends on the
level of the oscillator voltage as shown in
Figure 5, so the required oscillator voltage at
Pin 6 is 200mVRMS.

7-70

The Oscillator
To obtain the required frequency stability in a
cordless telephone set, where adjacent channels are at 20 or 30kHz, crystal oscillators are
commonly used.
The crystal oscillator circuits usable for this
kind of application always need an LC-tuned
resonant circuit to suppress the other modes
of the crystal. In this type of oscillator (see
Figure 6 as an example) the crystal is in the
feedback line of the oscillator amplifier. Inte-

Signetics Linear Products

Application Note

TDA7000 for Narrow-Band FM Reception

AN193

gration of such an amplifier should give a 2pin oscillator.

,-

The TDA7000 contains a 1-pin oscillator. An
amplifier with current output develops a voltage across the load impedance.

I

a=:n;n950
13

-5

-I.

Voltage feedback is internal to the IC.

,~

-'5

To obtain a crystal oscillator with the
TDA 7000 1-pin concept, a parallel circuit
configuration as shown in Figure 7 has to be
used.

i

L-_

-00

L1~2.3mH

-25
-30

Explanation of this circuit:
a. Without the parallel resistor RpFigure 8 shows the relevant part of the
equivalent circuit. There are three frequencies where the circuit is in resonance (see Figure 9, and the frequency
response for "impedance" and "phase",
shown in Figure 10). The real part of the
highest possible oscillation frequency
dominates, and, as there is also a zerocrossing of the imaginary part, this highest frequency will be the oscillator frequency. However, this frequency (fpAR) is
not crystal-controlled; it is the LC oscillation, in which the parasitic capacitance of
the crystal contributes.
b. With parallel resistor RpThe frequency response (in" amplitude"
and "phase") of the oscillator circuit of
Figure 7 with Rp is given in Figure 11. As
the resistor value of Rp is large related to
the value of the crystal series resistance
R, or R3, the influence of Rp at crystal
resonances is negligible. So, at crystal
resonance (see Figure 9b), R3 causes a
circuit damping

-35

......

,..

1.2

1.6

1.7

I

-.

1

~

-t

I
I

-...

1""'-

""

I

-6
-7

-6
-9

-I.
200

100

300

400

500
600
Vosc(mV)

700

800

900

1000

1100

Figure 5. Relative Mixer Conversion Gain
RO • ROAM PING
=-",---::c=.=== Rc
RO + RoAMPING

(C )2.

Thus a damping resistor parallel to the crystal
(Figure 7) damps the parasitic LC oscillation
at the highest frequency. (Moreover, the
imaginary part of the impedance at this frequency shows incorrect zero-crossing.)

February 1987

I"--..

-S

1

Figure 6

I
fosc "" 1.7MHz

1

ROAM PING = _ . Rp' C,2. Rp 1 + 2
W2
C,

+

I

TDA7000 AT

where

R.

•..

'.0

1.8

Figure 4

However, at the higher LC-oscillation frequency fpAR (see Figure 9c), Rp reduces the
circuit impedance Ro to

Q

1.4

Ia(MHz)

R=~'R3'C,2+R3
(1+~)~
W2
C,

Jf------iDt-------,

40

Taking care that Rp l!> RSERIES, the resistor is
too large to have influence on the crystal
resonances. Then with the impedance Rc at
the parasitic resonance lower than R at

7-71

crystal resonance, oscillation will only take
place at the required crystal frequency, where
impedance is maximum and phase is correct
(in this example, at third-overtone resonance).
Remarks:
a. It is advised to avoid inductive or capacitive coupling of the oscillator tank circuit
with the RF input circuit by careful positioning of the components for these circuits and by avoiding common supply or
ground connections.

The IF Amplifier
Selectivity
Normal selectivity in the TDA7000 is a fourthorder low-pass and a first-order high-pass

Signetics linear Products

Application Note

TDA7000 for Narrow-Band FM Reception

AN193

filter. This selectivity can be split up in a
Sallen and Key section (Pins 7, B, 9), a
bandpass filter (Pins 10, 11), and a first-order
low-pass filter (Pin 12).
Some possibilities for obtaining required selectivity are given:
a.

In the basic application circuit, Figure
12a, the total filter has a bandwidth of
7kHz and gives a selectivity at 25kHz IF
frequency of 42dB.
In this filter the lower limit of the passband is determined by the value of C4 at
Pin 11, where C3 at Pin 10 determines
the upper limit of the bandpass filter
section.

b.

To obtain a higher selectivity, there is the
possibility of adding a coil in series with
the capacitor between Pin 11 and
ground. The so-obtained fifth-order filter
has a selectivity at 25kHz of 57dB (see
Figure 12b).

c.

If this selectivity is still too small, there is
a possibility of increasing the 25kHz selectivity to 65dB by adding a coil in series
with the capacitor at Pin 11 to ground. In
this application, where at 5kHz IF frequency an adjacent channel at -30kHz
will cause a (30- 5) = 25kHz interfering IF
frequency, the pole of the last-mentioned
LC filter (trap function) is at 25kHz (see
Figure 12c).

For cordless telephone sets with channels at
15kHz distance, the filter characteristics are
optimum as shown in the curves in Figure 13,
in which case the filters are dimensioned for
5kHz IF bandwidth (instead of 7kHz). So for
this narrow channel spacing application, the
required selectivity is obtained by reducing
the I F bandwidth; this at the cost of up to 2dB
loss in sensitivity.
NOTE:
At 5kHz IF frequency adjacent channels at ± 15kHz
give undesired IF frequencies of 20kHz and 10kHz,
respectively.

LimiterI Amplifier
The high gain of the limiterI amplifier provides
A VC action and effective suppression of AM
modulation. DC feedback of the limiter is
decoupled at Pin 15.

The Signal Demodulator
The signal demodulator is a quadrature
modulator driven by the IF signal from
limiter and by a phase-shifted IF signal
rived from an all-pass filter (see Figure

dethe
de14).

This filter has a capacitor connected at Pin 17
which fixes the IF frequency. The IF frequency is where a 90 degree phase shift takes
care of the center position in the demodulator
output characteristics (see Figure 15, showing the demodulator output (at Pin 4) as a
function of the frequency, at 1mV input signal).
February 19B7

Figure 7

The AF Output Stage

RF Pre-Stage at 46MHz

The signal demodulator output is available at
Pin 4, where a capacitor, C, serves for elimination of IF harmonics. This capacitor also
influences the audio frequency response. The
output from this stage, available at Pin 2, has
an audio frequency response as shown in
Figure 16, curve a. The output at Pin 2 can be
muted.

For better quality receivers at 46MHz, an RF
pre-stage can be added (see Figure 21) to
improve the noise figure. Without this transistor, a noise figure F = 11dB was found. With a
transistor (BFY 90) with RC coupling at 3mA,
F = 7dB or at 6mA F = 6dB.
With a transistor stage having an LC-tuned
circuit, one can obtain F = 7dB at 1= 0.3mA.

Output Signal Filtering

NOTE:

Output signal filtering is required to suppress
the IF harmonics and interference products of
these harmonics with the higher-order bessel
components of the modulation. Active filtering with operational amplifiers has been used
(see Figure 17). The frequency response of
such a filter is given in Figure 16, Curve b, for
an active second-order filter with an additional passive RC filter.

The noise figure includes

Output Amplification
The dimensioning of the operational amplifier
of Figure 17a results in no amplification of the
AF signal. In case amplification of this op amp
is required, a feedback resistor and an RC
filter at the reverse input can be added (see
Figure 17b, for about 30dB amplification).

MEASUREMENTS
For sensitivity, signal handling, and noise
behavior information in a standard application
as shown in Figure 18, the signal and noise
output as a function of input signal has been
measured at 1.7MHz, at 400Hz modulation
where the deviation is ± 2.5kHz (see Figure
19). As a result the S+ N/N ratio is as given in
Figure 19, Curve 3.

APPENDIX
RF-Tuned Input Circuit at
46MHz
In Figure 20 a filter is given which matches at
46MHz a 750 aerial to the input of the
TDA7000. Extra suppression of RF frequencies outside the passband has been obtained
by a trap function.

7-72

jmage~nois8.

An LC Oscillator at 1.7MHz
An LC oscillator can be designed with or
without AFC. If for better stability external
AFC is required, one can make use of the DC
output of the signal demodulator, which delivers BOmV /kHz at a DC level of 0.65V to
+ supply. An LC oscillator as shown in Figure
22a, using a capacitor with a temperature
coefficient of -150ppm, gives an oscillator
signal of 190mV, with a temperature stability
of 1kHz/50°.
With the use of AFC, as shown in Figure 22b,
one can further improve the stability, as AFC
reduces the influence of frequency changes
in the transmitter (due to temperature influence or aging). The given circutt gives a
factor 2 reduction. Note that the temperature
behavior of the AFC diode has to be compensated. In Figure 22b, with BB405B having a
capacitance of 1BpF at the reverse voltage
V4 = 0.7V, the temperature coefficient of the
capaCitor C has to be - 200ppm.

AF Output Possibilities
The AF output from the signal demodulator,
available at Pin 4, depends on the slope of
the demodulator as shown in Figure 15. The
TDA7000 AF output is also available at Pin 2
(see Figure 23). The important difference
between the output at Pin 2 and the output at
Pin 4 is that the Pin 4 output is amplified and
limited before it is led to Pin 2 (see Figure 24).
Moreover, the Pin 2 output is controlled by
the mute function, a mute which operates in
case the received signal is bad as far as
noise and distortion are concerned.

Signetics Linear Products

Application Note

TDA7000 for Narrow-Band FM Reception

AN193

I

--m

I

±
T

?

r

;>

A,

R.

I

Ao

c,

l

I

a.

b.
Figure 8

..
c.

At fpAR

reo,,,,,,,

Figure 9
The Pin 2 output delivers a higher AF signal;
however, the AF output spectrum shows
more mixing products between IF harmonics
and modulation trequency harmonics. This is
due to the "limited output situation" at Pin 2.
In narrow-band application with relatively
large deviation these products are so high
that extra AF output filtering is required and,
moreover, the IF center frequency has to be
higher compared to the concept, using AF
output at Pin 4.

So for those sets where the mute! squelch
function of the TDA7000 is not used, and the
higher AF output is not required, the use of
the AF output at Pin 4 is advised, giving less
interfering products and simplified AF output
filtering.

February 1987

Squelch and Squelch Indication
The TDA 7000 contains a mute function, controlled by a "waveform correlator", based on
the exactness of the IF frequency.
The correlation circuit uses the IF frequency
and an inverted version of it, which is delayed
(phase-shifted) by halt the period of nominal
IF. The phase shift depends on the value of
the capacitor at Pin 18 (see Figure 23).
This mute also operates at low field strength
levels, where the noise in the IF signal
indicates bad signal definition. (The correlation between IF signal and the inverted
phase-shifted version is small due to fluctuations caused by noise; see Figure 25.) This
field strength-dependent mute behavior is
shown in Figure 26, Curve 2, measured at full

7-73

mute operation. The AF output is not "fastswitched" by the mut~ function, but there is a
"progressive (soft muting) switch". This soft
muting reduces the audio output signal at low
field strength levels, without degradation of
the audio output signal under these conditions.
The capacitor, C at Pin 1 (see Figure 23)
"
determines the time constant for the mute
action.
Part operation of the mute is also a possibility
(as shown by Figure 26, Curve 3) by circuiting
a resistor in parallel with the mute capacitor
at Pin 1.
In Figure 26 the small signal behavior with the
mute disabled has been given also (see
Curve 1).

•

Signetics Linear Products

Application Note

TDA7000 for Narrow-Band FM Reception

One can make use of the mute output signal,
available at Pin 1, to indicate squelch situation by an LED (see Figure 27). Operation of
the mute by means of an external DC voltage
(see Figure 28) is also possible.

AN193

6/DIY.
80

Bell Signal Operation
To avoid tone decoder filters and tone decoder rectifiers for bell signal transmission, use
can be made of the mute information in the
TDA7000 to obtain a bell signal without the
transmission of a bell pilot signal.
With a handset receiver as shown in Figure
23 in the "standby" position, the high mute
output level turns amplifier 1 off via transistor
T1 until a correct IF frequency is obtained.
This situation appears at the moment that a
bell signal switches the base unit in transmission mode. If the transmitted field strength is
high enough to be received above a certain
noise level, the mute level output goes down;
T1 will be closed and amplifier 1 starts
operating. However, due to feedback, this
amplifier starts oscillating at a low frequency
(a frequency dependent on the filter concept).
This low-frequency signal serves for bell signal information at the loudspeaker.
Switching the handset to "tlllk" position will
stop oscillation. Then amplifier 1 serves to
amplify normal speech information.

FREQUENCY

a. 1-Pln Crystal Oscillator

lOG/DIY.
800

Mute at Dialing
During dial operation, the key-pulser IC delivers a mute voltage. This voltage can be used
to mute the AF amplifier, e.g., via T1 of the
bell signal circuit/amplifier (see Figure 23).

CONCLUSIONS
The application of the TDA7000 in the remote
unit (handset) as narrow-band FM receiver is
very attractive, as the TDA7000 reduces
assembly and post-production alignment
costs. The only tunable circuit is the oscillator
circuit, which can be a simple crystal-controlled tank circuit.
A TDA7000 with:
• fifth-order IF filter
• third-order AF output filter

lpar
FREQUENCY

• matched input circuit
• crystal oscillator tank circuit
• disabled mute circuit
gives a sensitivity of 2.51J.V for 20dB signal-tonoise ratio, at adjacent channel selectivity of
40dB (at 15kHz) in cordless telephone application at 1.7MHz.
The TDA7000 circuit is:
• without an RF pre-stage
• without RF-tuned circuits
• without oscillator transistor (and its
components)

February 1987

lG

b. 1-Pin Crystal Oscillator
Figure 10
• without LC or ceramic filters in IF and
demodulator.
For improved performance, the TDA7000 circuit can be expanded:
• with an RF pre-stage and RF selectivity
• with higher-order IF filtering
• with mute/ squelch function.

7-74

For reduced performance the TDA7000 circuit can be simplified:
• to LC-tuned oscillator
• to lower-order IF filter
• to bell signal operation without pilot
transmission.

Application Note

Signetics Linear Products

TDA7000 for Narrow-Band FM Reception

AN193

&IDlY.
80

600
Rp=250Cl

FREQUENCY

a. 1-Pln Crystal Oscillator
(R 00, 250, 60)

=

FREQUENCY
0ft0(NI31S

b. 1-Pin Crystal Oscillator
(R 00, 250, 60)

=

Figure 11

February 1987

7-75

Signetics Linear Products

Application Note

AN193

TDA7000 for Narrow-Band FM Reception

10dB1D1V
40

Rs
A,

12K
R2:::2.2K

Aa R4=4.7K

-40

C,
C2

1.3nF
68nF

Ca

3nF

C4
C5

47nF
3.3nF

.oK

0
FREQUENCY 5l

"""MuTE"

l

700K

IF LIMITER

~LATOR

MUTE CONTROL

:

700K

AP

L

y

1 V

10K

1

9

~

-~

6

7

c_+
~

Cp

"

~~

"
C.

8

Signetics Linear Products

Product Specification

FM Radio Circuit (SO Package)

TDA7010T

DC ELECTRICAL CHARACTERISTICS vee = 4.5V; TA = 25°C: measured in Figure 3, unless otherwise specified.
LIMITS
PARAMETER

SYMBOL

TEST CONDITION

Vee

Supply voltage

(Pin 4)

lee

Supply current

Vee = 4.5V

UNIT
Min

Typ

Max

2.7

4.5

10

V

8

mA

p.A

15

Oscillator current

(Pin 5)

280

V12-14

Voltage

(Pin (2)

1.35

V

12

Output current

(Pin 2)

60

p.A

V2-14

Output voltage

(Pin 2) RL = 22kf2

1.3

V

AC ELECTRICAL CHARACTERISTICS Vee = 4.5V; TA = 25°C; measured in Figure 3 (mute switch open, enabled);
fRF = 96MHz (tuned to max. signal at 5p.V EMF) modulated with Af = ±22.5kHz; fM = 1kHz; EMF = 0.2mV (EMF voltage at a source
impedance of 75f2); RMS noise voltage measured unweighted (I = 300Hz to 20kHz), unless otherwise specified.
LIMITS
SYMBOL

PARAMETER

TEST CONDITION

UNIT
Min

EMF

Sensitivity (see Figure 2)
(EMF voltage)

-3dB limiting; muting disabled

1.5

-3dB muting

6

SIN = 26dB
EMF

Signal handling (EMF voltage)

SIN

Signal-to-noise ratio

THD

Total harmonic distortion

AMS

AM suppression of output voltage

Typ

THD

< 10%;

Af = ± 75kHz

Max

p.V

5.5
200

mV

60

dB

Af = ± 22.5kHz
Af = ±75kHz

0.7
2.3

%
%

(ratio of the AM output signal referred to the
FM output signal)
FM signal: fM = 1kHz; Af = ± 75kHz
AM signal: fM = 1kHz; m = 80%

50

dB

RR

Ripple rejection

(AVee = 100mV; f = 1kHz)

10

dB

V5-4RMS

Oscillator voltage (RMS value)

(Pin 5)

250

mV

Afase

Variation of oscillator frequency

Supply voltage (AVee = IV)

60

kHzlV

5+300

Selectivity

43

dB

28

5-300

AfRF

AFC range

B

Audio bandwidth

Va RMS

AF output voltage (RMS value)

RL

±300

kHz

AVo = 3dB Measured with pre-emphasis
(t = 50p.s)

10

kHz

RL = 2kf2

75

Load resistance

October 10, 1986

7-87

mV

Vcc=4.5V

22

Vee = 9.0V

47

kf2

II

Signetics Linear Products

Product Specification

FM Radio Circuit (SO Package)

TDA7010T

0,4

0.3

\

1\
1\

0.'

\

o

50
TAC'C)

-50

'50

'00

Figure 1. Power Derating Curve

Rf'X

sL

I

I

2

V;

I

2

iii

-20

~

~

V,I'

b-..

-40

-60

I

" 'No-

THO

-80
10- 6

10- 5

40
I

I

I

NOISE

I
10- 4

I

I

,

10-3
EMF (V)

at

R2

I

10-2

I

I

t

I

x

.
0

10-1

,

0

= 75 n

NOTE:
1. The muting syatem can be disabled by leedlng a current of about 20pA Into Pin 1.

= 75mVi fRF = 9&MHz
~f = ± 22.5kHz: 1M = 1kHz
for THO curve: dt = ± 75kHz: 1M = 1kHz

Conditions: 0 dB

for S + N curve:

Figure 2. AF Output Voltage (Vo) and Total Harmonic Distortion (THO) as a Function of the EMF Input Voltage (EMF)
With a Source Impedance (Rs) of 7S.n: (1) Muting System Enabled; (2) Muting nystem Disabled

October 10, 1986

7·88

Product Specification

Signetics Linear Products

TDA7010T

FM Radio Circuit (SO Package)

'rl~EMF !

f1
J:220PF

-!::'80PF
75

r,p

330pF

220pF

14-

15

16

220pF ~

100nF

2.7K

10K

10K

~

IF FILTER

L

x

<1-

~

H>

-(1'22K

3

4.7K

-

13.6K

r""MuTE

2

cr4.7K

LOOP
FILTER

I
I

f
Vee

10nF

~

I .....

2.2K

1>-

2.2K

r

I I
1-;:,. .

VCO

... I

4

5

~
Cp

6

~i"F

7

8

180pF

10nFf

I~

~~
Vee
MUTE SWITCH

AFOUTPUT

Figure 3. Test Circuit

October 10, 1986

12K

MIXER

Vee

700K

'--

{>

J

='50
nF

11V

IF LIMITER

~LATOR

MUTE CONTROL

~ENABLED '9 DISABLED

700K

~:71-

AP

L

10K

9

11 10

13 12

~

CORRELATOR

1

3.9nF

7-89

Cs

II

TDA7021T

Signetics

Single-Chip FM Radio Circuit
Preliminary Specification

Linear Products
DESCRIPTION
The TDA7021T integrated radio receiver
circuit is for portable radios, stereo as
well as mono, where a minimum of
periphery is important in terms of small
dimensions and low cost. It is fully compatible for applications using the lowvoltage micro tuning system IC (MTS).
The IC has a frequency-locked loop
(FLL) system with an intermediate frequency of 76kHz. The selectivity is obtained by active RC filters. The only
function to be tuned is the resonant
frequency of the oscillator. Interstation
noise as well as noise from receiving
weak signals is reduced by a correlation
mute system.
Special precautions have been taken to
meet local oscillator radiation requirements. Because of the low intermediate
frequency, low pass filtering of the MUX
signal is required to avoid noise when
receiving stereo. 50kHz roll-off compensation, needed because of the low pass
characteristic of the FLL, is performed
by the integrated LF amplifier. For mono
application this amplifier can be used to
directly drive an earphone. The field
strength detector enables field strengthdependent channel separation control.

FEATURES

PIN CONFIGURATION

• RF input stage
• Mixer
• Local oscillator
~ IF ampliflerllimiter
• Frequency detector
• Mute circuit
• MTS compatible
• Loop amplifier
• Internal reference circuit
• LF amplifier for
- mono earphone amplifier or
-MUX filter
• Field strength-dependent channel
separation control facility

APPLICATIONS
• FM radios
• Stereo
• Mono

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

16-Pin Plastic SO

o to +70·C

TDA7021TD

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

Vee

Supply voltage (Pin 4)

V6·S

Oscillator voltage (Pin 5)

T stg

RATING

UNIT

7

V

Vee - 0.5 to Vee + 0.5

V

Storage temperature range

-55 to + 150

·C

TA

Operating ambient temperature range

-10 to +70

·C

8JA

Thermal resistance
From junction to ambient

300

·C/W

February 1987

7-90

DEMOD OUT

1

GROUND

3

FILTER CAP

6

11 FILTER CAP

FILTER CAP

7

10 FILTER CAP

SIGNAL
FILTER CAP ..8'"t-_ _ _.r"' STRENGTH

TOP VIEW

Signetlcs Linear Products

Preliminary Specification

TDA7021T

Single-Chip FM Radio Circuit

BLOCK DIAGRAM
FIELD

r
16

17.51<

STRENGTH

RFINPUT

MUXOUT

1
15

14

12

13

11

521<

170J,LA

+
13k

O.9V

*6OF

F

700

700

4.7k

v~~~~------~~~~-----+------------6------------+-+~--------6---------------~

DC ELECTRICAL CHARACTERISTICS Vee = 3V, TA = 25'C, unless otherwise specified.
PARAMETER

SYMBOL

MIN

TYP

MAX

1.8

3.0

6

UNIT

Vee

Supply voltage (Pin 4)

lee

Supply current at Vee = 3V

6.3

rnA

V

15

Oscillator current (Pin 5)

250

p.A

V,3.3

Voltage at Pin 13

0.9

V

V,4-3

Output voltage (Pin 14)

1.3

V

February 1987

7-91

•

Preliminary Specification

Signetics Linear Products

TDA7021T

Single-Chip FM Radio Circuit

Vcc = 3V, TA = 25°C; measured in Figure 5; IRF = 96MHz modulated with
til = ± 22.5kHz; 1M = 1kHz; EMF = 300p.V (EMF voltage at a source impedance 01
75n); RMS noise voltage measured unweighted (I = 300Hz to 20kHz), unless
otherwise specilied.

AC ELECTRICAL CHARACTERISTICS
(MONO OPERATION)

LIMITS
PARAMETER

SYMBOL

UNIT
Min

EMF

Sensitivity (see Figure 2)
(EMF voltage)
lor -3dB limiting; muting disabled lor -3dB
muting lor SIN = 26dB

EMF

Signal handling (EMF voltage) lor THO
til = ± 75kHz

< 10%;

Typ

Max

4.0
5.0
7

p.V
p.V
p.V

200
60

mV

SIN

Signal-to-noise ratio

60

dB

THO

Total harmonic distortion
at til = ± 22.5kHz
at til = ± 75kHz

0.7
2.3

%
%

AMS

AM suppression 01 output voltage
(ratio 01 AM signal: 1M = 1kHz;
m = 80% to FM signal: 1M = 1kHz;
at til = ± 75kHz)

50

dB

30

dB

250

mV

5
0.2

kHzIV
kHz/oC

RR

Ripple rejection (tiVcc = 100mV; I

V5-3(RMS)

Oscillator voltage (Pin 5) RMS value
Variation 01 oscillator Irequency

tiloscl tiCp
tilosel ti T

with supply voltage (tiVce
with temperature

S+300
S-300

Selectivity (without modulation;
Test Circuit, Figure 7)

30
46

dB
dB

± tilRF

AFC range

160

kHz

± tilRF

Mute range

120

kHz

BW

Audio bandwidth at tiVo = 3dB
measured with pre-emphasis (t = 50p.s)

10

kHz

VO(RMS)

AF output voltage (RMS value) at
RL (Pin 14) = loon; Pin 16 open

90

mV

lo(oG)
IO(Ac)

AF output current
MAX. OC load
MAX. AC load lor THO

= 1kHz)

= tV)

-100

= 10%;

AC ELECTRICAL CHARACTERISTICS
(STEREO OPERATION)

peak value

+100
3

p.A
mA

Vee = 3V, TA = 25'C; measured in Figure 6, IRF = 96MHz modulated with pilot
til = ± 6.75kHz and AF signal til = ± 22.5kHz; 1M = 1kHz; EMF = 1mV (EMF voltage
at a source impedance 01 75n); RMS noise voltage measured unweighted
(I = 300Hz to 20kHz), unless otherwise specilied.
LIMITS

SYMBOL

PARAMETER

UNIT
Min

Typ

Max

EMF

Sensitivity (Figure 2) (EMF voltage) lor SIN = 46dB

300

p.V

SIN

Signal-to-noise ratio

53

dB

-

LEVEl
DETEClOR

J

2.7k
.".

T

I Dir~R I
~
I
V,

r

8

=-N~
4

7-97

VsrAB

({ ~.
5

v,
Uk

DC OUTPUT
(LEVEL DETEClOR)

November 14, 1986

u

6.8k

TEA5560

>--

MUTING

3

t

~

3nlIF

2nd IF
AMPLIFIER

,----r- V,

V2

VOIl'AGE
STABIUZER

.".

STANDBY
INPUT

Signetics Linear Products

Product Specification

TEA5560

FMjlF System

DC ELECTRICAL CHARACTERISTICS Vcc = 14.4V; TA = 25°C; measured in Figure 1, unless otherwise specified.
LIMITS
SYMBOL

UNIT

PARAMETER
Min

Typ

Max

10.2

14.4

18.0

V

Pin 8; - la = 02
Pin 8 when - la increases from 0 to 15mA
Pin 8 when Vee reduces from 14.4V to 10.2V
Pin 8 when Vee increases from 14.4V to 18.0V
Pin 4 (level detector)
Pins 1, 2 and 3

7.5

8.0
200

8.5
300
1.0
200
100

V
mV
V
mV
mV
V

=0

15

Supply (Pin 6)

Vcc

= V6-9

Supply voltage I

Voltages

Va_9

t:N a_9
t:N a_9
V4 -9
VI, 2, 3-9

at
at
at
at
at
at

2.4

Currents

ITOT

Total supply current; -Ia

-Ia

Current supplied from Pin 8

IS8

Stand-by current; VS-9

15

Current into Pin 5

17

Current into Pin 7

=0

20

30

rnA

15

rnA

8

11

14

rnA

1.0

1.5

2.0

rnA

3.0

rnA

300

mW

Power consumption

Pe

-Ia

=0

NOTES:
1. A stabilized supply voltage of 7 to 9V can also be applied at Pins 5 and 6 (linked); for this application Pin 8 must not be connected.
2. The temperature coefficient of the stabilized voltage at Pin a is typically - 2.3mVlOC.

November 14, 1986

7-98

Signetics Linear Products

Product Specification

TEA5560

FMjlF System

AC ELECTRICAL CHARACTERISTICS Vcc=14.4V; TA = 25°C; VI=lmV; fo=10.7MHz; fl.f=±22.5kHz; fM=lkHz. unless
otherwise specified.
LIMITS
SYMBOL

PARAMETER

UNIT
Min

Typ

Max

105

150

210

40

45
65
78
80

dB
dB
dB
dB

IF part and ratio detector
Sensitivity
at - 3dB belore limiting (Pin 1);
(without muting) 1

JiV

SIN

Signal-to-noise S+ NIS measured in
a bandwidth of 60Hz to 15kHz
at VI = 20p.V
at VI = 150JiV
at VI= lmV
at VI = 10mV

Vo
Vo

AF output voltage
fl.1 = ± 22.5kHz
fl.1 = ±75kHz

200
600

mV
mV

THO
THO

Total harmonic distortion
fl.1 = ± 22.5kHz
fl.1 = ±75kHz

0.3
2.0

%
%

AMS
AMS
AMS

AM suppression
1M = 1kHz; m = 0.3 (lor AM)
1M = 70kHz; fl.1 = ± 22.5kHz (lor FM)
at VI = 150p.V
at VI = lmV
at VI = 10mV

40
50
55

dB
dB
dB

1.9
2.8
3.5
5.0
5.7

V
V
V
V
V

15

dB

SIN
SIN
SIN

Level detector circuit
V4 _ 9
V4 - 9
V4 _9
V4 - 9
V4 - 9

OC output voltage (Pin 4)
at VI = 200p.V
at VI = 500p.V
at VI = lmV
at VI =3mV
at VI = 10mV

Muting circuit (see also Figure 4)
/Ir_+
C4

C6

*lOOnF*22nF
C1

2.2nF
R1
50

50

TEAS560

SfANOBY

SWITCH

DC CONTROL VOLTAGE / "
(FOR SMO

s:

~
-+

::>

~

g
::>
(i)

8
-0

(J)

a0-

3

g-

c

O

12

:J

111
TEA6000

0.

()
0

3

"0

c-+
(J)

....

S"
-+
(J)

~

0

(]I

v

~ rs~~ro~.~

~-

------ ------

:

~------------~

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Signetics linear Products

Product Specification

TEA6000

FM IF System and Computer Interface (MUSTI) Circuit

DC ELECTRICAL CHARACTERISTICS VCCl = VCC2 = 8.4V; TA = 25'C, unless otherwise specilied.
LIMITS
SYMBOL

PARAMETER

UNIT
Min

Typ

Max

7.6
7.6

8.4
8.4

9.2
9.2

VCCl
VCC2

Supply voltage
Pin 2
Pin 12

ICCl
ICC2

Supply current AM mode
Pin 2
Pin 12

18.5
17.4

rnA
rnA

ICCl
Icc2

Supply current FM mode
Pin 2
Pin 12

19.2
16.4

rnA
rnA

PD

Power dissipation

350

mW

V
V

AC ELECTRICAL CHARACTERISTICS VCCl =VCC2 = 8.4V; V16-l0 = 1mV;I= 10.7MHz; AI = 22.5kHz; 1M = 1kHz, unless
otherwise specilied.
LIMITS
SYMBOL

PARAMETER

UNIT
Min

V'(FM)

Sensitivity
at -3dB belore limiting

SIN
SIN
SIN
SIN

Signal-to-noise ratio, FM input
V, = 20/1V
V, = 150/1V
V, = 1mV
V, = 10mV

VNO
VNO

Typ

Max

150

/1V

46
64
76
80

dB
dB
dB
dB

Noise output voltage
V, = OV; with muting, switch S1 on
V, = OV; without muting, S1 off

55
420

/1V
/1V

Vo
Vo

Audio output voltage
AI = 22.5kHz
AI = 75kHz

170
520

mV
mV

AMS
AMS
AMS
AMS

AM suppression ratio 01 the AM output signal relerred to the FM signal (m = 0.3)
V, = 150/1V
V,= 1mV
V,= 10mV
V, = 100mV

46
62
58
60

dB
dB
dB
dB

VL

Level detector output voltage (Figure 3)
R13_l0=4.7kn; V, =10mV, FM mode

6.2

V

VL(FM)
VL(FM)
VL(FM)
VL(FM)

Level detector output voltage slope R13-l0 adjusted in FM mode lor
VL = 5.5V at V, = 10mV; 1= 10.7MHz
V, = OV (Pin 16)
V, = 140/1V
V, = 1mV
V, =3mV

130
1.3
2.7
4.4

mV
V
V
V

VL(AM)
VL(AM)
VL(AM)

R13. l0
V, =
V, =
V, =

200
1.4
2.7

November 14, 1986

40

adjusted in FM mode (see above)
OV, I = 460kHz (Pin 18)
1mV, I = 460kHz (Pin 18)
10mV, I = 460kHz (Pin 18)

7-106

.

mV
V
V

Signetics Linear Products

Product Specification

TEA6000

FM IF System and Computer Interface (MUSTI) Circuit

AC ELECTRICAL CHARACTERISTICS

(Continued) VCC1 = VCC2 = 8.4V; V, 6-,0 = 1mV; f = 10.7MHz; Llf = 22.5kHz;
fM = 1kHz, unless otherwise specified.

SYMBOL

LIMITS

PARAMETER

Min

Typ

Max

UNIT

VI(AM)
VI(FM)
RIN

Frequency counter sensitivity
AM input voltage (Pin 18)
FM input voltage (Pin 16)
AM input impedance

VIH
VIL
IIH
IlL
lACK
fl MAX

BUS inputs
SDA and SCL (Pins 9 and 8)
Input voltage HIGH
Input voltage LOW
Input current HIGH
Input current LOW
Acknowledge sink current
Maximum input frequency

VOH
VOL

Output voltage SDA
HIGH; 4kn to 8.4V
LOW; I =2mA

RIN
CIN

AID converter (Pins 5 and 13)
Input resistance
Input capacitance

VT
VT
VT
VT
VT
VT
VT

Trip levels, sensitivity bit ,HIGH
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7

0.6
1.06
1.38
1.84
2.14
2.55
2.97

V
V
V
V
V
V
V

VT
VT
VT
VT
VT
VT
VT

Trip levels, sensitivity bit LOW
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7

0.96
1.78
2.44
3.26
3.92
4.63
5.38

V
V
V
V
V

fREF

Crystal oscillator (see Figure 5)
Reference frequency

Av
IBIAS
10
10
V7(P.P)

Operational amplifier (Pins 6 and 7)
Voltage gain
Input bias current
Output sink current at Vo = 1V
Output source current at Vo = 7.4V
Output voltage swing

tGATE'
tGATE'
tGATE'
tGATE'
fS(AM)2
fS(FM)2

60
80
30

3.0
-0.3

VCC1
1.5
10
10
2

100

TBD
TBD

32

5.5

NOTES:

1. tGATE has to be multiplied by 32,000/32,768 for an fREF of 2'5 Hz.
2. fs has to be multiplied by 32,768/32,000 for an fREF of 2'5Hz.

7·107

TBD
TBD

32.768
104
30
0.2
10
5.5

V
V

!1A
!1A

-

mA
kHz

0.4

V
V

TBD
TBD

kn
pF

8.0

Frequency measuring system measuring windows; fREF = 32 or 40kHz
AM
Window "0" (LOW)
Window "1" (HIGH)
FM
Window "0" (LOW)
Window "1" (HIGH)
Resolution frequency counter
AM
FM

November 14, 1986

/lV
/lV
kn

V
V
40

kHz

100

nA
mA
mA
V

4
8

ms
ms

20
40

ms
ms

250
6.4

Hz
kHz

II

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~
3

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m

~

AM
(kHz)
428.25
428.75
429.0.0.
429.25
429.50.
439.75
430..0.0.
430..25
430..50.
430..75

431.0.0.
431.25
431.50.
431.75
432.0.0.

o
ex>

READ

OUT

FM
(MHz)

1 ··------1 ------1 --------1
428.50.

~

"T1

s::

Table 1. Reference Frequency 32,000Hz (SAA 1057)

432.25
432.50.
432.75
433.0.0.
433.25
433.50.
433.75
434.0.0.
434.25
434.50.
434.75
435.0.0.
435.25
435.50.
435.75
436.0.0.

436.25
436.50.
436.75
437.0.0.
437.25
437.50.

437.75
438.00.
438.25
438.50.
438.75
439.00
439.25
439.50.
439.75
440..00

440..25
440.50.
440.75

'DO.'
'0.1'
'0.2'
'0.3'
'0.4'
'0.5'
'0.6'
'0.1'
'08'
'0.9'
'QA'
'QB'
'DC'
'DD'
'QE'
'QF'
'10.'
'11'
'12'
'13'
'14'
'15'
'16'
'11'
'18'
'19'
'1A'
'1B'
'1C'
'1D'
'1E'
'1F'
'20.'
'21'
'22'
'23'
'24'
'25'
'26'
'27'
'28'
'29'
'2A'
'2B'
'2C'
'2D'
'2E'
'2F'
'30.'
'31'
'32'

9.888
9.894
9.90.1
9.90.7
9.914
9.920.
9.926
9.933
9.939
9.946
9.952
9.958
9.965
9.971
9.978
9.984
9.990.

9.997
10..0.0.3

10..0.10.
10..0.16
10..0.22

10..0.29
10..035
10..0.42
10..0.48

10..0.54
10..0.61
10..0.67
10..0.74
10..0.80.
10..0.86

10..0.93
10.0.99
10..10.6
10..112

10..118
10..125

10..131
10..138
10..144
10.150.
10..157
10.163
10..170.

10..176
10..182
10..189
10..195
10..20.2
10..208

AM
(kHz)

READ

OUT

FM
(MHz)

1 --------1 ------1 --------1
441.0.0.

441.25
441.50.
441.75
442.0.0.
442.25
442.50.
442.75
443.00
443.25
443.50.
443.75
444.0.0.
444.25
444.50.
444.75
441.0.0.
441.25
441.50.
441.75
442.0.0.
442.25
442.50.
442.75
443.0.0.

443.25
443.50.
443.75
444.0.0.
444.25
444.50.
444.75
449.0.0.
449.25
449.50.
449.75
450..0.0.
450..25
450..50.
450.75
451.0.0.
451.25
451.50.
451.75
452.0.0.
452.25
452.50.
452.75
453.0.0.
453.25
453.50.

'33'
'34'
'35'
'36'
'31'

'38'
'39'
'3A'
'3B'
'3C'
'3D'
'3E'
'3F'
'40.'
'41'
'42'
'43'
'44'
'45'
'46'
'41'

'48'
'49'
'4A'
'4B'
'4C'
'4D'
'4E'
'4F'
'50.'

'51'
'52'
'53'
'54'
'55'
'56'
'51'

'58'
'59'
'5A'
'5B'
'SC'
'5D'
'5E'
'5F'
'60.'
'61'
'62'
'63'
'64'
'65'

10..214
10..221
10..227

10..234
10..240.
10..246
10..253

10..259
10..266

AM
(kHz)
453.75

'66'

454.0.0.

'61'

454.25
454.50.

454.75
455.0.0.
455.25
455.50.
455.75
456.0.0.

10..285

456.50.

10..291
10..298

456.75
457.0.0.
457.25
457.50.
457.75
458.0.0.
458.25
458.50.
458.75

10.30.4

10..330.
10..336
10..342
10..349

10..355

456.25

459.0.0.

459.25
459.50.
459.75

10..362
10..368
10..374

460..0.0.

10..381

460..25

10..387

460..50.

10..394
10..40.0.

460..75
461.0.0.
461.25
461.50.
461.75
462.0.0.
462.25

10..40.6

10..413
10..419

10..426
10.432
10..438
10..445
10..451
10..458
10..464
10..470.
10..477
10..483
10..490.
10..496
10.50.2
10..509
10.515
10.522
10.528
10..534

OUT

FM
(MHz)

1 --------1 ------1 --------1

10.272
10..278

10..310.
10..317
10..323

READ

462.50.

462.75
463.0.0.
463.25
463.50.
463.75
464.0.0.
464.25
464.50
464.75
465.00.
465.25
465.50
465.75
466.00
466.25

AM
(kHz)
466.50.

'68'
'69'
'6A'
'6B'
'6C'
'6D'
'6E'
'6F'
70.'
71'
72'
'73'
74'
'75'
76'

10..554
10..560
10..566
10..573
10..579

467.0.0.

71'

10..650.

470..25
470..50.
470..75

10..656

471.0.0.

10..662
10..669

471.50.

78'
79'
'7A'
'7B'
'7C'
7D'
'7E'
7F'
'80.'
'81'
'82'
'83'
'84'
'85'
'86'
'81'

'88'
'89'
'8A'
'8B'
'8C'
'8D'
'8E'
'8F'
'90.'
'91'
'92'
'93'
'94'
'95'
'96'
'91'

'98'

466.75
467.25
467.50.
A67.75
468.0.0.

10..592
10..598
10..60.5
10..611

468.25
468.50.
468.75
469.0.0.
469.25

10..618

469.50.

10.624
10..630.
10..637
10..643

469.75

10..675
10..682
10.688
10..694
10..70.1
10..70.7
10..714
10..720.
10..726
10..733
10..739

OUT

FM
(MHz)

1 --------1 ------1 --------1

10..541
10..547

10..586

READ

470..0.0.

471.25
471.75
472.0.0.

472.25
472.50.

472.75
473.0.0.

473.25
473.50.

473.75
474.0.0.
474.25

10..746

474.50.

10..752
10.758
10..765
10..771
10.778
10..784
10..790.
10..797
10..80.3
10..810
10.816
10..822
10.829
10..835
10.842
10..848
10.854
10..861

474.75
475.0.0.
475.25
475.50.
475.75
476.0.0.
476.25
476.50.
476.75
477.0.0
477.25
477.50.
477.75
488.0.0.
488.25
478.50.
478.75
479.0.0.

'99'
'9A'
'9B'
'9C'
'9D'
'9E'
'9F'
'AD'
'A1'
'A2'
'A3'
'A4'
'AS'
'A6'
'AT
'A8'
'A9'
'AA'
'AB'
'AC'
'AD'
'AE'
'AF'
'BD'
'B1'
'B2'
'B3'
'B4'
'B5'
'B6'
'BT
'B8'
'B9'
'BA'
'BB'
'BC'
'BD'
'BE'
'BF'
'Co.'
'C1'
'C2'
'C3'
'C4'
'C5'
'C6'
'CT
'C8'
'C9'
'CA'
'CB'

10..867
10..874

AM
(kHz)
479.25
479.50.

10..976
10..982
10..989
10..995
11.0.0.2
11.0.0.8
11.0.14

485.0.0.

11.0.21

11.0.66
11.0.72

485.25
485.50.
485.75
486.0.0.
486.25
486.50.
486.75
487.0.0.
487.25

11.0.78

487.50.

10..970.

11.0.27
11.0.34
11.0.40

11.0.46
11.0.53
11.0.59

11.0.85
11.0.91
11.0.98
11.10.4
11.110.
11.117
11.123
11.130.
11.136
11.142
11.149
11.155
11.162
11.168
11.174
11.181
11.187

OUT

FM
(MHz)

487.75
488.0.0.

488.25
488.50.

488.75
489.0.0.
489.25
489.50.
489.75
490.0.0.
490..25
490..50.
490..75
491.0.0
491.25
491.50
491.75

'CC'
'CD'
'CE'
'CF'
'DO.'
'D1'
'D2'
'D3'
'D4'
'D5'
'D6'
'DT
'D8'
'D9'
'DA'
'DB'
'DC'
'DD'
'DE'
'DF'
'EO.'
'E1'
'E2'
'E3'
'E4'
'E5'
'E6'
'ET
'E8'
'E9'
'EA'
'EB'
'EC'
'ED'
'EE'
'EF'
'FQ'
'F1'
'F2'
'F3'
'F4'
'F5'
'F6'
'FT
'F8'
'F9'
'FA'
'FB'
'FC'
'FD'
'FE'

"T1

en

-

11.194

-<
en

11.20.0

( I)

11.20.6
11.213
11.219
11.226
11.232
11.238
11.245
11.251
11.258
11.264
11.270
11.277
11.283
11.290.
11.296
11.30.2
11.30.9
11.315
11.322
11.328
11.334
11.341
11.347
11.354

3

1 ---·----1 ------1 --------1
479.75
480..0.0.
480..25
480..50.
480..75
481.0.0.
481.25
481.50.
481.75
482.0.0.
482.25
482.50.
482.75
483.0.0.
483.25
483.50.
483.75
484.0.0.
484.25
484.50.
484.75

10..880.
10..886
10..893
10..899
10.90.6
10..912
10.918
10..925
10..931
10..938
10..944
10..950.
10..957
10..963

READ

11.360.

11.366
11.373
11.379
11.386
11.392
11.398
11.405
11.411
11.418
11.424
11.430.
11.437
11.443
11.450.
11.456
11.462
11.469
11.475
11.482
11.488
11.494
11.501
11.50.7
11.514

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3

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"T1

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Table 2. Reference Frequency 32,768Hz (2 15 Hz)
AM
(kHz)

READ

OUT

FM
(MHz)

1 ·-------1 ------1 --------1
438.53
438.78
439.04
439.30
439.55
439.81
440.05
440.30
440.65
440.80
441.15
441.30
441.69
441.90
442.15
442.40
442.62
442.88
443.14
443.39
443.65
443.90
444.16
444.42
444.67
444.93
445.18
445.44
445.70
445.95
446.21
446.46
446.72
446.98
447.23
447.49
447.74
448.00
448.26
448.51
448.77
449.02
449.28
449.54
449.79
450.05
450.30
450.56
450.82
451.07
451.33

'00'
'01'
'02'
'03'
'04'
'05'
'06'
'01'
'08'
'09'
'OA'
'OB'
'OC'
'00'
'OE'
'OF'
'10'
'11'
'12'
'13'
'14'
'15'
'16'
'11'
'18'
'19'
'lA'
'lB'
'lC'
'10'
'lE'
'lF'
'20'
'21'
'22'
'23'
'24'
'25'
'26'
'21'
'28'
'29'
'2A'
'2B'
'2C'
'20'
'2E'
'2F'
'30'
'31'
'32'

10.125
10.132
10.138
10.145
10.152
10.158
10.126
10.133
10.139
10.146
10.152
10.158
10.165
10.171
10.178
10.184
10.230
10.237
10.243
10.250
10.256
10.263
10.269
10.276
10.283
10.289
10.296
10.302
10.309
10.315
10.322
10.328
10.335
10.342
10.348
10.355
10.361
10.368
10.374
10.381
10.387
10.394
10.401
10.407
10.414
10.420
10.427
10.433
10.440
10.446
10.453

AM
(kHz)

READ

OUT

FM
(MHz)

1 --------1 ------1 --------1
451.58
451.25
452.10
452.35
452.61
452.86
453.50
453.75
453.00
453.25
454.50
454.75
454.00
454.25
455.50
455.75
455.68
455.94
456.19
456.45
456.70
456.96
457.22
457.47
457.73
457.98
458.24
458.50
458.75
459.01
459.26
459.52
459.78
460.03
460.29
460.54
460.80
461.06
461.31
461.57
461.82
462.08
462.34
462.59
462.85
463.10
463.36
463.62
463.87
464.13
464.38

'33'
'34'
'35'
'36'
'31'
'38'
'39'
'3A'
'3B'
'3C'
'3~'

'3E'
'3F'
'40'
'41'
'42'
'43'
'44'
'45'
'46'
'41'
'48'
'49'
'4A'
'4B'
'4C'
'40'
'4E'
'4F'
'50'
'51'
'52'
'53'
'54'
'55'
'56'
'57'
'58'
'59'
'5A'
'5B'
'5C'
'50'
'5E'
'5F'
'60'
'61'
'62'
'63'
'64'
'65'

10.460
10.466
10.473
10.479
10.486
10.492
10.453
10.459
10.466
10.472
10.478
10.485
10.491
10.498
10.404
10.410
10.564
10.571
10.578
10.584
10.591
10.597
10.604
10.610
10.617
10.623
10.630
10.636
10.643
10.650
10.656
10.663
10.669
10.676
10.682
10.689
10.695
10.702
10.709
10.715
10.722
10.728
10.735
10.741
10.748
10.754
10.761
10.768
10.774
10.781
10.787

•

AM
(kHz)

READ

OUT

FM
(MHz)

1 --------1 ------1 --------1
464.64
464.90
465.15
465.41
464.66
465.92
455.25
455.50
455.75
456.00
456.25
456.50
456.75
457.00
457.25
457.50
457.75
458.00
458.25
458.50
458.75
459.00
459.25
459.50
459.75
460.00
460.25
460.50
460.75
461.00
461.25
461.50
472.83
473.09
473.34
473.60
473.86
474.11
474.37
474.62
474.88
475.14
475.39
475.65
475.90
476.16
476.42
476.67
476.93
477.18
477.44

'66'
'61'

'68'
'69'
'6A'
'6B'
'6C'
'60'
'6E'
'6F'
'70'
'71'
'72'
'73'
'74'
'75'
'76'
'71'
'78'
'79'
'7A'
'7B'
'7C'
'70'
'7E'
'7F'
'80'
'81'
'82'
'83'
'84'
'85'
'86'
'81'
'88'
'89'
'8A'
'8B'
'8C'
'80'
'8E'
'8F'
'90'
'91'
'92'
'93'
'94'
'95'
'96'
'91'
'98'

10.794
10.800
10.807
10.813
10.820
10.873
10.879
10.886
10.892
10.898
10.805
10.811
10.818
10.824
10.830
10.837
10.843
10.950
10.956
10.962
10.969
10.975
10.982
10.988
10.994
10.901
10.907
10.914
10.920
10.926
10.933
10.939
11.003
11.010
11.017
11.023
11.030
11.036
11.043
11.049
11.056
11.062
11.069
11.076
11.082
11.089
11.095
11.102
11.108
11.115
11.121

AM
(kHz)

READ

OUT

FM
(MHz)

1 --·-----1 ------1 --------1
477.70
477.95
478.21
478.46
478.72
467.75
468.00
468.25
468.50
468.75
469.00
469.25
469.50
469.75
470.00
470.25
470.50
470.75
471.00
471.25
471.50
471.75
472.00
472.25
472.50
472.75
473.00
473.25
473.50
473.75
474.00
474.25
485.89
486.14
486.40
486.66
486.91
487.17
487.42
487.68
487.94
488.19
488.45
488.70
488.96
489.22
489.47
489.73
489.98
490.24
490.50

'99'
'9A'
'9B'
'9C'
'90'
'9E'
'9F'
'AO'
'A1'
'A2'
'A3'
'A4'
'A5'
'A6'
'AT
'A8'
'A9'
'M'
'AB'
'AC'
'AD'
'AE'
'AF'
'BO'
'Bl'
'B2'
'B3'
'B4'
'B5'
'B6'
'BT
'B8'
'B9'
'BA'
'BB'
'BC'
'BO'
'BE'
'BF'
'CO'
'Cl'
'C2'

'ca'
'C4'
'C5'
'C6'
'CT
'C8'
'C9'
'CA'
'CB'

10.867
10.874
10.880
10.886
10.893
10.899
10.906
10.912
10.918
10.925
10.931
10.938
10.944
10.950
10.957
10.963
10.970
10.976
10.982
10.989
10.995
11.002
11.008
11.014
11.021
11.027
11.034
11.040
11.046
11.053
11.059
11.066
11.338
11.344
11.351
11.357
11.364
11.370
11.377
11.364
11.390
11.397
11.403
11.410
11.416
11.423
11.429
11.436
11.443
11.449
11.456

AM
(kHz)

READ

OUT

FM
(MHz)

1 --------1 ------1 --------1
479.25
479.50
479.75
480.00
480.25
480.50
480.75
481.00
481.25
481.50
481.75
482.00
482.25
482.50
482.75
483.00
483.25
483.50
483.75
484.00
484.25
484.50
484.75
485.00
485.25
485.50
485.75
486.00
486.25
486.50
486.75
487.00
498.94
499.20
499.46
499.71
499.97
500.22
500.48
500.74
500.99
501.25
501.50
501.76
501.02
502.27
502.53
502.78
502.04
503.30
503.55

- - - - _ .. _ - - - -

'CC'
'CD'
'CE'
'CF'
'~O'

'01'
'02'
'03'
'04'
'OS'
'06'
'01'
'08'
'09'
'DA'
'DB'
'DC'
'~O'

'DE'
'OF'
'EO'
'E1'
'E2'
'E3'
'E4'
'E5'
'E6'
'ET
'E8'
'E9'
'EA'
'EB'
'EC'
'ED'
'EE'
'EF'
'FO'
'Fl'
'F2'
'F3'
'F4'
'F5'
'F6'
'FT
'F8'
'F9'
'FA'
'FB'
'FC'
'FO'
'FE'

11.194
11.200
11.206
11.213
11.219
11.226
11.232
11.238
11.245
11.251
11.258
11.264
11.270
11.277
11.283
11.290
11.296
11.302
11.309
11.315
11.322
11.328
11.334
11.341
11.347
11.354
11.360
11.366
11.373
11.379
11.386
11.392
11.672
11.679
11.685
11.692
11.698
11.705
11.711
11.718
11.724
11.731
11.737
11.744
11.751
11.757
11.764
11.770
11.777
11.783
11.790

"T1

~
en

CD

3

cO
:J

~
~

c:

:J

CD

Q

~

Q.

c:

g-

O

:J
Q.

()
0

3

u

-

c

C....D

S"

CD
~
0
0

CD

..-.

s:

c

en
-I

.=:;

()

,5"

c::;:

~
-I

~

o
o
o

~

i
g

Signetics Linear Products

Product Specification

FM IF System and Computer Interface (MUSTI) Circuit

FUNCTIONAL DESCRIPTION
The IF SECTION consists of three balanced
differential stages with separated FM and AM
inputs, directly coupled by emitter-followers.
The last stage also has separated outputs,
which are intended for driving a ratio detector
and the frequency measuring system.
The last two stages are coupled via low-value
capacitors to two LEVEL DETECTORS which
generate a signal-dependent DC current for
controlling channel separation and frequency
response of a stereo decoder, multi path detector circuitry, AGC, and the internal ADC.
The IF MUTING circuit has been incorporated
to decrease the interstation noise by about
15dB.
The 3-bit AID CONVERTER has two inputs,
which are selected via two multiplexed analog
switches. One of these switches is internally
connected to the level detector output but
can also serve as an external input, as the
level detector output can be switched off. The
outputs of the ADC are converted to a Gray
code, latched, and reconverted to a binary
code to obtain glitch-free output data. The
sensitivity of both inputs can be selected
independently via software on two levels.
The reference for the ADC is derived from a
BAND-GAP STABILIZER circuit. Multipath

distortion on FM will generate an AM modulation on the DC voltage from the level detectors. This AM modulation can be filtered and
rectified to obtain a multipath-dependent DC
voltage. This voltage can be applied to the
other input of the ADC.
To facilitate filtering, an OPERATIONAL AMPLIFIER (OPA) is incorporated on the chip.
The typical circuit diagram for a multipath
filter is given in Figure 3.
The FREQUENCY COUNTER is preceded by
a 7-stage prescaler for FM, and FMI AM
selector stage and a divider by 1 or 2. The
actual counter is a presettable and resettable
8-stage counter with a 3-stage data disable
overflow counter which can be switched off.
The eight significant output bits are situated
symmetrically around 10.7MHz and 460kHz
when the external timebase source is used
(e.g., SAA1057). See Table 1.
The reference for the TIMEBASE is primarily
thought to be the SAA 1057. This circuit
generates from its 4MHz crystal oscillator a
32 or 40kHz signal. This signal is buffered
and applied to the timebase circuitry (mode I).
The circuit diagram for this mode I is given in
Figure 4a.
In the timebase, the selection is made for
reference frequency (32 to 40kHz), FM or AM

mode and the width of the measuring window,
all under software control. Accuracy ± h bit
when the window is set to wide (see Figure 1)
and ± 1 bit when set to narrow. A special
feature is the synchronization of the measuring cycle with the input DATA of the 12C bus,
meaning the measuring cycle starts immediately after a "WRITE" instruction via the 12C
bus.
For those who do not use the SAA 1057 as
reference, a 2 15Hz crystal (32,768Hz) can be
connected to the reference inputs directly,
obtaining a quartz-oscillator reference. See
Figure 4b for the circuit diagram for this mode

II.
When the circuit is used in mode II a correction has to be made to the values of window
width and resolution as the cheap watch
crystals differ by about 2.4 % from the frequency generated by the SAA 1057 (32,768
and 32,000kHz, respectively) See Table 2.
Communication between MUSTI and the microcomputer is accomplished via the two-wire
bidirectional 12 C bus (slave transceiver version), the SDA (serial data), and SCL (serial
clock).
To prevent crosstalk between the digital and
analog parts of the circuit, the power supply
lines are fully isolated.

1'H

SOA

SCL

FUNCTION

ADDRESS

INPUT DATA

\ \

START

WRITEACKN

Figure 1. Input Data Format Waveforms

INPUT BITS
BIT

1
2
3
4
5
6
7
8

FUNCTION
Reference frequency
Sensitivity ADC2
Sensitivity ADC1
Level detector output
AM/FM
Overflow counter
Measuring window
Test mode

November 14, 1986

"0"

"1"

REFERENCE TO
FIGURE 1

32kHz
LOW
LOW
off
AM
off
narrow
off

40kHz
HIGH
HIGH
on
FM
on
wide
on

A
B
C
D
E
F
G
H

7-110

TEA6000

Signetics Linear Products

Product Specification

TEA6000

FM IF System and. Computer Interface (MUSTI) Circuit

SDA

SCL

ADDRESS

OUTPUT DATABVTE1

START

OUTPUT DATABVTE2

READ ACKN

ACKN

Figure 2. Output Data Format Waveforms

OUTPUT
LEVEL DETE~OR......~_....._ _....._ _13~

1
I

4.7k

30k

*

TEA6000

10nF

X1 = 216 Hz
327
(

3

2.2nF

300k

~300km;,

TEA6000

a.

TEA6000

MUL~~1~ 0 - -.....- - -..

33P~F
mk
=~L
SOmV

I'V

102V

b.
Figure 4. Oscillator/Buffer Circuits. X1

7-111

PF

300k

3

Figure 3. Multipath Detector Circuit

November 14. 1986

~

-r

=215Hz (32,768Hz)

Signetics Linear Products

Product Specification

TEA6000

FM IF System and Computer Interface (MUSTI) Circuit

I

=
FOR

I

22nF

!ceo
~2~_-----1~~V~____--OV~=&AY

~ ~I-:-+-----'''-I
(F~ 1 1
T. 18

1

22nF

16

v,

so

so

.,..

330

.

15

17

300k
33pF

10
TEA6000

r--.....-~,........I--o OSCILLAlOR

14

DX1-2"Hz

t-

13

PF

270
~----~~----os~

300k

MULnPATH

LEVEL

lSOk

NOTES,
L1 ~ 3122 138 2021/TOKO 85 ACS-4238 A
L2 >: 3122 138 2022/TOKO 85 ACS-42BO SEJ

S open = without muting
S closed = with muting

}

for measuring purpose only.

Germanium diodes AA119 are required in the 1est circuit only. In a complete FM channel (inclusive FM front end) the silicon diodes BA281 are recommended,

Figure 5. MUSTI Test and Application Circuit

November 14, 1986

7·112

Signetics Linear Products

Product Specification

FM IF System and Computer Interface (MUSTJ) Circuit

TEA6000

..,--

FMV

/
/
AM

V

./'
/

..,-

o

10

Figure 6. Level Detector Output as a Function of Input Voltage

IlL

I III

_h1.~~o ~

~
~~~.
~

..-::~

1

I

. ...... ... ".
'

26dB

63dB

..

'

......

BOdB
AM SUPPRESSION:
M=Q.3

......J....

/

-

l ....··· .........

-100
1

10

NOTE:
11

=

10.7MHz; £\.f = 22.5kHz; fMOD = 1kHz; OdB

=

245mV

Figure 7. Signal-to-Noise Ratio as a Function of FM Input Voltage

II

November 14, 1986

7-113

Signetics

LM1870
Stereo Demodulator With Blend
Product Specification

Linear Products
DESCRIPTION

FEATURES

The LM1870 combination FM Stereo
Demodulator and Blend Circuit is a PLL
circuit with a DC control pin whose
purpose is to reduce switching noise by
decreasing separation under low signal
amplitude conditions. The part is designed specifically for automobile applications where fluctuating signal strength
can cause demodulation noise.

• Stereo blend control
• Wide input dynamic range
• Low total harmonic distortion
• veo disable function
• Monophonic override pin
• Supply range 7V - 15V

PIN CONFIGURATION
N Package

QUICK MONO 1

APPLICATIONS
•
•
•
•

20

~~~~:8fNTROl

PLllNPUT 2

Auto radios
High-fidelity tuners
High·performance portable radios
Electronic tuned radios

V+ 3

111 8LENDFILTER

't~b6Ikla= 4

17 BLEND FILTER

'~'k':t~ ~=~SJ8rN\

LAMP FILTER 5

18

lOOP FILTER 6

1&

LOOP FILTER 7

14

yeo TUNING

8

13 LEFT OUTPUT

veo TUNING

9

12 RIGHT OUTPUT

~~~,~~ts
G~\'llp~=s&

11 LAMP DRIVER

TOP VIEW

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

o to +70°C

LM1870N

20-Pin Plastic DIP

TYPICAL APPLICATION AND TEST CIRCUIT
12V

e1'

O.01I'F

VLAMP

Rl1

180

CONTROL
VOLTAGE

2W
/l/LED
LEFT OUl

1

211

RIGHT OUT

COMPOSITE
INPUT

V·

November 14, 1986

7·114

853-0931 86551

Signetics Linear Products

Product Specification

Stereo Demodulator With Blend

LM1870

ABSOLUTE MAXIMUM RATINGS
SYMBOL

RATING

UNIT

Vee

Supply voltage, Pin 3

PARAMETER

15

V

VOUT

Lamp driver voltage, Pin 11

18

V

VOUT

Output voltage, Pins 12, 13 supply off

7

V

VOUT

Quick mono input (Pin 20)

VOUT

Blend input (Pin 20)

TA

Operating temperature range

PD

Power dissipation

TSTG

Storage temperature range

TSOLD

Lead soldering temperature (10 sec. max)

V + (Pin 3)
V

15

o to

+70

'C

1

W

-65 to +150

'C

300

'c

DC ELECTRICAL CHARACTERISTICS TA = 25'C, V +

= 8V, unless otherwise noted (Figure 1).

LIMITS
SYMBOL

PARAMETER

TEST CONDITIONS

UNIT
Min

Vee

Operating supply voltage

lee

Supply current

PSRR

7

Typ

Max

8

15

V

26

45

mA

Input DC voltage

Pin 19

4

V

Input DC voltage

Pin 2

1.8

V

Supply rejection
Lamp leakage current
Lamp saturation voltage
VCO stop voltage

veo

stop current

15
Lamp off, Pin 11

= 16V

Lamp on, Pin 11 @ 75mA
Voltage @ Pin 4 to stop
Pin 4

veo

= 0.2V

Blend input bias current
Quick mono switch voltage
Quick mono bias current
Output leakage

November 14, 1986

0.2

30

dB

0.1

100

1.4

2.0

0.4

p.A

V
V

-30

-100

p.A

-2

-20

p.A

4

V

Pin 1 = 8V

2

p.A

Pin 12 or 13 = 6.5V, Pin 3 = OV

0.1

7-115

20

p.A

•

Product Specification

Signetics Linear Products

LM1870

Stereo Demodulator With Blend

AUDIO ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL

PARAMETER

UNIT

TEST CONDITIONS
Min

-1

+2
0.25

%

±0.4

± 1.5

dB

Mono to stereo

±O.1

± 1.0

dB

Pin 20 ;;'1.1V

45
±1OO

mV

1kHz

Mono THD

1kHz @ 200mVRMS

Channel balance
Gain shift
Channel separation
Output DC shift
RIN

Input resistance

ROUT

Output resistance
Ultrasonic rejection
SCA rejection

SIN

Signal-to-noise ratio

Max

0.05

Mono gain

-4

Typ

30

±15

Mono to stereo
Pin 19

20

dB

dB

40

kn

Pin 12, 13

65

200

19kHz + 38kHz

30

dB

n

(Note 2)

70

dB

1kHz @ 200mVRMS Mono

68

dB

PLL ELECTRICAL CHARACTERISTICS
LIMITS
PARAMETER

SYMBOL

TEST CONDITIONS

UNIT
Min

Lamp ON voltage

19kHz on Pin 2

Lamp OFF voltage

19kHz on Pin 2

2.5

Lamp hysteresis

RIN

Max

15

20

5

25mVRMS on Pin 2

Hold in range

25mVRMS on Pin 2

±2

Pin 2

8

TEST CONDITIONS
(Pin 20 from 1.1V to 0.2V)

Min

±4

mV
mV

10

Capture range

Input resistance

Typ

dB
±6

%

±12

%

14

kn

BLEND ELECTRICAL CHARACTERISTICS
SYMBOL

PARAMETER

LIMITS
UNIT
Typ

Max

Stereo gain change

1kHz L = -R input

-25

-35

Mono gain change

1kHz L = R input
10kHz L = R input

-1.5
-8

-0.5
-14

0.5
-20

dB
dB

±40

± 100

mV

Output DC shift

November 14, 1986

7-116

dB

Product Specification

Signetics Linear Products

Stereo Demodulator With Blend

LM1870

TYPICAL PERFORMANCE CHARACTERISTICS
Gain Change vs Temperature

..

S
w

il

1.0

;!

Ci

,

1

o

~19,'00

r-..

0

!!J<:

::119,000

,

.....

8,8,900
>

20

50

75

9

7

~

g

- ---

10

....

S
o

8

--

"i5
§ 19,000 I" r-.
:f
o

"> 18,900

z
9

:;:0:

~z

o
-<

,.o'"
-0,5 ~

t

is:

20

PilOT
LEVEL

ii
S

.....

40

~
~

III

27

""

.."

-- --

~

28

III

25

19K
FREQUENCY (Hz)

a

V

,.,

~

-4

o

2.5

November 14, 1986

20K

3.0

CURRENt}-

~~

~"

2.5

0

2.0

::

1.5

LIMIT

V

>

/

z

./

0.5

8

9

10

11

12

13 14

15

o

o

so

100

150

200

250

300

PIN11 CURRENT(mA)

Total Harmonic Distortion vs
Input Level
1.•

70

>
g
ill

/
RL > 9.1k
NOT
RECOMMENDED
FOR Vs .. 8V

7.5
10 12.5
LOAD RESISTOR (kO)

:E
w

Lamp On/Off vs Resistance
Pin4to5

.~

-2

19K

Lamp Driver Voltage vs Current

SUPPLY VOLTAGE (V)

/

-8

18K

veo FREQUENCY (Hz)

80

iz

30

is: 1.0

/

RL > 1.5k
NOT
RECOMMENDED

K r-..

4.0

7

Gain vs RL (Pins 14, 15)

2o~V

v~

3.5

.oK

t=1kHz

c-b~V'

40

75

24
18K

75

20

25
50
TEMPERATURE (Oe)

..

0:
0:

50

z

30

28

50

Separation vs VCO Tuning

-

50

"....
z
w

10

25

TEMPERATURE (OC)

Supply Current vs Supply Voltage

g

50

30

-1.0

-25

30

80

15

~

0.5

18,800

15

...

80

20
-25

75

70

§

13 14

~

III

80

40

12

S

Capture Range vs Pilot Level

;

10 11

Separation vs Temperature

..

o
25
50
TEMPERATURE (OC)

-25

"

<

'"
;,9,100

80

-

OFF

is:

ill

1.0

SUPPLY VOLTAGE (V)

ON

15

>

>
g

,.'"

-1.0

18,800

25

Lamp On/Off vs Temperature

w

o

-o.S ~

TEMPERATURE (OC)

~

Q

r-...

~

,.

19,200

i

-2
-25

;

~

w

r-....

-1

~

~

0.5

>-

!;!

"az
"

VCO Temperature Stability

VCO Supply Sensitivity
19,200

80

~;::;---

10kHz

50

;

40

§

30

is: 20
10

o
10k

l/1kH.

ON

1""o~.......

1111
lOOk

0.01

1M

EXT. RESISTANCE PIN 4 TO 5 (0)

o

Q.2

0.4

0.5

o.a

1.0

MONO INPUT LEVEL (Vrme)

1.2

II

Signetics Linear Products

Product Specification

Stereo Demodulator With Blend

LM1870

TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Total Harmonic Distortion vs Frequency

Separation vs Frequency

0.4

I
I

m
t; 0.3
~
o
~

0.2

V

lE

.

Q

:z:

l

50

0.5

!

Power Supply Rejection Ratio vs
Frequency

z

0

i~

.

30

50 100 200 500 lk

2k

~

40

Ul

30

20

a:

10

=
~

VIN-SOOmV
OUTPUT (ULTRASONICS) FILTERED

...~

o
50 100 200 500 lk

5k 10k 15k

1-++++~~-+-+-H-++1fH

50

UJ

0.1

o

5

r-

40

iii

:s

80 r--'-..,..."..TT11rr--.--r"T1-rnm

2k 3k 10k 15k

FR#!++tt4=tiittttl

20 1--++++tttlt--t-+-H-tttH
101--++++tttlt--t-+-H-tttH

L + R Frequency Response With Blend
Control

FReQUENCY (HZ)

L - R Gain vs Blend Control

Typical Radio Quieting Characteristic

10

10
R16=12~,

iii

~-10 t-+-t-1f--+-+-1~f'--1

~

a: - 20

~

- 30

Rl6=6h ../ V V
~R16:.1.~k
;-20 r-I-~
11 ~ V

~-3O

~ -40

1-t--+-++-I--+--+---1

-70

0.2

0.4

0.8

RFINPUT!.y)

VB

10

IIIIt!til

1U
><

PIN 20 VOLTAGE

t:

10

1

L - R Gain and Separation
RF Input Level With Blend

Blend Filter Response

II)

-50

1.0

~~j~EBL~ND

MONO
NOISE

BLEND CONTROL VOLTAGE (y)

10

"

L-R
GAIN

\

SEPARATION·

-40

-40

I...\":.!

-50
lk

2k 3k 5k

10k 20k

-50

50k lOOk

1

FREQUENCY (HZ)

November 14, 1966

0.6

"

1\

-40

o

STEREO
NOISE

\

13-30
a:

10
RFINPUT!.y)

7-118

j

REC11URED JUDIO

1\. . r,

~-20
~

-80

_ 40 L-.1-...L....-'----L--'---'----'----'
50 100 200 500 lk 2k Sk 10k 15k
FREQUENCY (HZ)

;-10
.

.

r'\ V

-50

V"

1- 10

I/:V V i'R16=3k

a:

1-+--+-1f--

START OF LIMITING

I) ~ V!A"'T

ii':" 10

10k

lk

FREQUENCY (HZ)

FREQUENCY (HZ)

100

100

lOA 1OOSAI 1OOSAl

Signetics

Frequency Multiplex PLL Stereo
Decoder
Product Specification

Linear Products

DESCRIPTION
The TDA1005A is a high quality PLL
stereo decoder based on the frequencydivision multiplex (FDM) principle, performing:
- Excellent ACI (Adjacent Channel Interference) and SCA (Storecast)
rejection
- Very low BFC (Beat-Frequency Components) distortion in the higher frequency region

FEATURES
• With simplified peripheral
circuitry the circuit can perform
as a time-division multiplex (TOM)
decoder for use in economic
medium and low-class apparatus
• Extra pin for smooth mono/
stereo take-over without "clicks"

• Automatic mono/stereo switching
(minimum switching level is
16mV) controlled by both pilot
signal and field strength level
• Low distortion in the loop
resonance frequency region
("" 300Hz; THO = 0.2% typ.)
• External adjustment for obtaining
optimum channel separation in
the complete receiver
• Internal amplification: TOM, 7dB;
FDM, 10dB
• Driver for stereo indicator lamp
• Externally switchable: yeO-off or
mono condition
• Guaranteed veo capture range
( > 3.5% or 2.7kHz)

PIN CONFIGURATION
SYNCDEMOD
COMP
STEREO IN

2

RIGHT OUT 3

LEFT OUT 4
MONO IN

PlLDrLEVEL

2 ~~:iDET

5

11 :UIl'IPLEX

TAKE-OVER

10 PREAMP

9 ~'iliASEDET

--...----'TOP VIEW

APPLICATIONS
• ear radios
• Mono/stereo

BLOCK DIAGRAM

•
,.
NUX INPUT

November 14, 1986

STEREO
INDICATOR

PILOT MONO/STEREO
LEVEL
SWITCH

7-119

AFOUTPtITS

853-0963 86551

Product Specification

Signetics Linear Products

IDA 1OOSAI 1OOSAI

Frequency Multiplex PLL Stereo Decoder

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

o to
o to

16-Pin Plastic DIP (SOT-38)
16-Pin Plastic SO (SO-16; SOT-109A)

ORDER CODE

70'C

TDA1005AN

70'C

TDA1005ATD

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

RATING

UNIT

Vcc

Supply voltage

18

V

V , 5-,6

Indicator lamp voltage

22

V

V , 4-,6

Mono/stereo switching voltage

4

V

1'5

Indicator lamp current

100

mA

1'5M

Indicator lamp turn-on current
(peak value)

200

mA

Po

Total power dissipation

TSTG

Storage temperature

see derating curve Figure 1
-65 to +150

'C

TA

Operating ambient temperature
(see also Figure 2)

-25 to + 150

'C

DC ELECTRICAL CHARACTERISTICS TA = 25'C; Vec = 15V, unless otherwise specified.
LIMITS
PARAMETER

SYMBOL

UNIT
Min

Vee

Supply voltage range

Is

Total current (except indicator lamp)

Po

Power dissipation (operating) at lamp current 1'5 = 100mA;
VS_16=18V

Typ

Max

8

V,5 - ,6

Saturation voltage of lamp driver
at 1'5 = 100mA

V,5 - ,6

Maximum lamp driver voltage

V,4 - ,6
V , 4-,6
V , 4-,6

Switching voltage
to mono
to stereo
hysteresis

V

18

mA

21

mW

570

0.9

V
22

V

0.65

V
V
V

1.2
0.2

NOTES:

1. At supply voltages of 8 to t 1V. resistors of 5.6k have to be connected from ground to Pins 2 and 3.
2. Maximum voltage for safe operation: V,4 - ,6 < 4V.

AC ELECTRICAL CHARACTERISTICS TA = 25'C; Vce = 15V, unless otherwise specified. See also Figures 5 and 6.
TDM
SYMBOL
ex

Channel separation 1. 2; see Figures 11 and 12

2,3

FM - IF roll-off correction range 1.2
VI(P_P)

Input MUX-voltage; L = 1; R = 1 for THD

Izil

Input impedance

Av

Voltage gain per channel " 2

±AAv

Channel balance 1. 2

V2 - 16(RMS)
V3-t6(RMS)

Output voltage (RMS value)
L=1;R=1 ' • 2

November 14, 1986

FDM

PIN

PARAMETER

UNIT
Min

Typ

40

50

48

< 0.35% 1.2

11
11

Max

Min

Typ

45

55

kHz

50

35

7

7·120

0.61
0.61

1

V

50

kSl

10
1

2
3

dB

72
1

35

Max

dB
1

0.97
0.97

dB
V
V

Signetics Linear Products

Product Specification

TDA 1aaSAI 1aaSAT

Frequency Multiplex PLL Stereo Decoder

AC ELECTRICAL CHARACTERISTICS (Continued) TA = 25°C; Vee = 15V, unless otherwise specified. See also
Figures 5 and 6.

SYMBOL

PARAMETER

PIN

Izol

Output impedance3

2,3

THO
THO
THO

Total harmonic distortion; see Figures 14 and 15
fM = 1kHz (all conditions) 1
IM=1kHz; L=l; R=11
1M = 300Hz to 10kHz

2, 3
2,3
2,3
2,3

cx 19
cx 19
cx3S
cx3S
cxS7
cxS7
cx76

Carrier suppression
I = 19kHz; without notch lilter1
I = 19kHz; with notch lilter1. 9
I = 38kHz; without notch lilter1
I = 38kHz; with notch lilter1, 9
I = 57kHz; without notch lilter1
I = 57kHz; with notch Iilter 1, 9
I = 76kHz; without notch lilter 1
ACI rejection
at 1= 114kHz4
at I = 190kHz4

2, 3

cx67

SCA rejection at I = 67kHzS

2, 3

RR

Ripple rejection; I = 100Hz;
VCC(RMS) = 200mV

0: 114

"190

TOM
Max

Min

Typ

Max

4

5.6

7

4

5.6

7

kfl

0.35

%
%
%

0.35
0.2

0.1

36
60

36
60

40
72

V,
V,
AV,
V6- 16
V6-16

Smooth take-over circuit
lull monoS
lull stereoS

dB
dB
dB
dB
dB
dB

38
72
46
59
80

56
61
75

52
55

70
74

dB
dB

90

dB

50

50

dB

76

76

kHz

3.5

3.5

%

450.10- 6
200.10- 6

450.10- 6
200.10- 6

0C-- l
°C- l

85
40

Stereo/mono switch
when equal to 19kHz pilot-tone threshold voltage;
adjustable
with R13_S 7
when equal to threshold voltage at R13 _S = 620kfl
lor switching to stereo
lor switching to mono
hysteresisS

V,

0.1

0.2

Temperature coellicient
uncompensated6
compensated6

-TC
±TC

UNIT

Typ

VCO; adjustable with R7 -16
nominal Irequency6
capture range (deviation from 76kHz center
frequency) 19kHz pilot signal 01 32mV6

Ivco

FOM

Min

40

11

10

100

10

100

mV

11
11
11

7

16
5

7

16
5

mV
mV
dB

0.65

V
V

6
6

2.5

2.5
0.65

1.3

1.3

NOTES:
1.
2.
3.
4.

V,(p.P) = 1V (MUX signal with 8% pilot level).
1M = 1kHz.
At supply voltages of 8 to 11V, resistors of 5.6kn have to be connected from ground to Pins 2 and 3.
Measured with a composite input signal: L = R; 1M = 1kHz; 90% M-signa/; 9% pilot signal; 1% spurious signal of 110kHz (for cx,14) or 186kHz (for
CX ,90)·

ACI suppression is deli ned as: 20 log

Vo (at 4kHz)
Vo (at 1kHz)

.

5. Measured with a composite input signal: L = R; 1M = 1kHz; 80% S-signal; 9% pilot signal; 10% SCA carrier (67kHz); d13
6. See also Figures 4 and 5; compensated with RC network on Pin 7.
7. Adjustable with R13-S; see 'also Figure 17; for field strength-dependent input (Pin 14) see next page.

8. I!.V,

= 20

log

V 11 _ 16 (mono/stereo)

.

V l1 -16 (stereo/mono)

For additional circuitry on Pin 6 see Figures 4 and 5.
9. For example of notch filter see Figure 3.

November 14, 1986

7-121

= 20

log Vo (at 9kHz)
Vo (at 1kHz)

•

Signetics Linear Products

Product Specification

Frequency Multiplex PLL Stereo Decoder

lDA 1005AI 1005Al

+1SV

2000

R1

f\

i

.s1000

~

"1\

0

+50

R7
100
TR1
R4

R5

3.3k

3.3k
C5

LMUX

r'OUTPUT

'\
0
-25

4701<

+100

R2
470k

1\

R3
3.3k

C2

C4

2nF

82pF

R8
2k

10l'F

(TO PIN 11
TDA1005A)

GND

+150

TA("C)
OP06770

Figure 2. Active Filter Circuit Diagram

Figure 1. Power Derating Curve

veo

then remains operational so this possi·
bility cannot be used with AM reception.

APPLICATION NOTES
Switching-Off the VCO
If the internal gain is used with AM reception,
the veo can be switched off by connecting
Pin 9 via a 100kn resistor to ground (no HF
signal on the leads), or connecting Pin 7 to
ground.

Mono Button
The decoder can be switched to the mono
position by connecting Pin 12 to ground. The

Economic Periphery
For a fixed stereo switching level of .;; 16mV,
a resistor of 620kn can be connected be·
tween Pin 13 and positive supply ( + ) instead
of a potentiometer in series with a resistor.
The 10kn resistor connected in parallel with
the stereo indicator lamp can be omitted.
However, some TDA 1005A circuits will switch
to mono during lamp failure.

The 10"F capacitor in series with a 1kn
resistor at Pin 9 can be decreased to a 1"F
capacitor, bearing in mind that the distortion
will increase, especially around loop reso·
nance.
A MUX input filter is not needed, if IF roll·off
starts at a frequency of 62kHz.

Notch Filter
If attention has to be paid for suppression of
the 57kHz signal (TWS = Traffic Warning
System) and the 19kHz signal, an input filter
can be used as shown in Figure 3.

+15V

1~2

MUX

INPUT

6.BnF

6.8nF

18k

NOTES:
1. Transistor to achieve low impedance driving of notch filter.
2. 33nF will give common mode suppression of 19kHz.
3. Coil: TOKO 10 PA, 700 turns, tPO.07mm Cu; case type: P06-0144; drumcore:
AN01-0021; base 5 pins type: 07-0084-02; cor

Figure 3. Example of Using a 19kHz Tuned Notch Filter (for Other Input Structures see Figures 8 through 11)

November 14, 1986

7-122

Signetics Linear Products

Product Specification

Frequency Multiplex PLL Stereo Decoder

IDA 1DDSAI 1DDSAI

PILOT LEVEL
+l5VO---------------1--.----~~----._--~----_4~----_,

R12

10k

MUX~NPUTVOLTAGE

4.7JLF

4.7k

'Dbt---+---,

NOTEI

r---1r-----o

Vl(P_p)=1V~'

:r:

MONO/STEREO SWITCH
V14-18 < O.65V: STEREO
VI 4-16 > 1.2V: MONO

560pF

TDA100SA

o..::..-r--"",---o ~~~UTPUT

GE·DIODE

C9

V~~~!8><1~3~V~:g OO--f~I4+-••

IlnF

SMOOTH TAKE-OVER

L-----1r--1--+--o~~~OUTPUT
Rl
(METAL
FILM)

Cl0
lnFI

18k
(1%)

+

Cl

C6

3.3~CJ

(MICROPOCO)I 560pF R2
NOTE 2
4.7k

-::-

7.SnF

T

R4

lk
Rll

VCO FREQUENCY
RS
1.51<

1.51<

1

Cll

33 nF

Coil data:
L1 L2 "" 2.6mH
Q1-2 = 35; QMIN = 30

~;~~: ~~~~ !~~:~ scrambled wound with wire diameter O.09mm, E3_4
X 100%
E1_2

= 82%

NOTES:

~: ~~: ~~~:o~:~ ~~~~~t~rS h~~e :~~~~:r:t~~e 1~e~~:~t ~~r~2~~~o~f~f;~;~1g~~~U~-~).
3.

tn

simplified circuits a fixed resistor (e.g. 620k) can be used for a guaranteed switching level of ..-;;;; 16mV.

4. Either the LED circuit or an external stereo indicator can be used.

Figure 4. Basic Application Circuit of a Frequency-Division Multiplex (FDM) Stereo Decoder

November 14, 1986

7-123

Signetics Linear Products

Product Specification

Frequency Multiplex Pll Stereo Decoder

IDA 1aasAI 1aaSAI

PILOT lEVEL
+IWo---------------~~~--~~----1_--~------t_----_,

R9

10k

+-=.:;::-~o =~~DlCATOR
4.7/LF

4.7k NOTE 1
J
V~p_P) = IV ~ 1

.---If------o

MUX-INPUT VOLTAGE

V,._,. <>

MONO/STEREO SWITCH
0.65V: STEREO
V 14_ 18

1.2V: MONO

~56OpF
TDA1005A

GE-DIODE
V6-1S

<

@

O.65V: MONO 0

Vl- 16 > 1.3V: STEREO

L---r-------------1-~~~~0~

SMOOTH TAKE-OVER

L----I-----...-+-o:~~OUTPUT
C8
Rl

(M~~
Cl
(MICROPOCO)
NOTE 2

I560pF
-

tOnF,J:

4.7J.LF

18k
(1%)

C9

Il0nF

RS
1.8k

R2
4.7k

--

veo FREQUENCY

NOTES:
1. For other input structures see Figures 7 to 11, shown here with RC-filter (Figure 8).
2. Micropoco capacitor has a temperature coefficient of 125.10- 6 ±60.10- 6"C- 1.
3, In simplified circuits a fixed resistor (e.g. 620k) can be used for a guaranteed switching level of
4. Either the LED circuit or an external stereo indicator can be used.

-< 16mV.

Figure 5. Basic Application Circuit of a Time-Division Multiplex (TOM) Stereo Decoder

4.7"I'

4.7"I'

Mux~.7k

MUX.....J.

INPUT ""I

INPUT

IPF

580

TDA1005A

TDA100SA

Figure 7. Input Structure With RC Filter for Achieving
IF RoII·Off (typ. 62kHz)

Figure 6. Input Structure Without Filtering

November 14, 1986

7-124

Signetics Linear Products

Product Specification

Frequency Multiplex PLL Stereo Decoder

IDA 1OOSAI 1OOSAI

IN=~O
I ~+.z: f- °1

!

T33nF~.
A

TO PIN 12
TDA1005A

10k

TO PIN 11
TDA1005A

15k

Figure 8. Input Structure With 19kHz Notch Filter

+15V

MUX
INPUT

4.7~F

I--

TO PIN 11
TDA100SA

TO PIN 12
TDA100SA

15k

Figure 9. Input Structure With Buffer Stage and 19kHz Notch Filter
(to Achieve Low Impedance Driving of Notch Filter; see Figure 3)

+15V

IN~~

4 7k
o-_-'VI
.I'r-_-t--+-t:"
4.7~F

L---- TO PIN 11
.------- TDA1005A

TO PIN 12
TDA100SA

15k

Figure 10. Input Structure With RC-Fllter, Buffer Stage, and 19kHz Notch Filter

November 14, 1986

7-125

•

Signetics Linear Products

Product Specification

lOA 1DDSAI 1DDSAl

Frequency Multiplex PLL Stereo Decoder

60

50

--

f·

I--

1-..........

------

IJHU

TYr~mr
............ I I II
.m~

'i~
\ ~~

30

.....

1,

WITHOUT IF
FILTER

WITHOUT IF
FILTER

I
Wlj Ii

FIL~EIR

10
I (kHz)

NOTES:
1. RCfilter for simulating the IF roll-off (typ. 62kHz).
2, - - Time-division multiplex system; adjusted at 1kHz (R4 in Figure 5).
3. - - - Frequency-division multiplex system; adjusted at 1 and 5kHz (R4 and R10 in Figure 4).
Conditions: Vee -15V; VI(P-Pl'" 1V.

Figure 11. Channel Separation as a Function of Frequency

100

75

i50
•

25

/
0.5

Figure 12. Channel Separation at f

November 14, 1986

= 1kHz

"\TYP

1Is-,. (kfi)

\.

"

1,0

1.5

as a Function of Resistance Between Pins 5 and 10 for a TOM System

7-126

Signetics Linear Products

Product Specification

Frequency Multiplex Pll Stereo Decoder

IDA 1005A/ 1005AI

OA

0.3

"#

a 0.2
~

TYP

0.1

10
I(Hz)

NOTES:
- - - TOM System
- - FOM System

Figure 13. Distortion as a Function of Audio Frequency; R = 1; L = 0; Vcc = 15V; V2-16 = V3-16 = 1VRMS

o

l(kHz)

o

10

30

20

26kHz
(LOWER SIDEBAND)

I

ii' -20
:!!.

40

,l

12kHz

A

19kHz

(PILOT)

J

,

JkHz
(SUB-CARRIER)
-60

~ .L LJlI--

-80

W

""'-

~L .....J

f-..A.-

""-

~

~

.

(1)

-lDO

o

B

m -20

:!!.

(2)

fi

-ortJ -40

-60

U~

-80

-

~ I--'

.....J ....

....L

(1)
-IDO

o

10

20

30

40

I(kHz)

NOTES:
1. Audible interferences (BFC-distortion) and desired 12kHz signal.
VSFG

2. dBFC = 20 log - - - .
V(at 12kHz)

Figure 14. Spectrum at the Decoder Outputs; A for TOM; B for FDM VI(P_P) = 1V; R = 1; L = 0;
m = 90% for f = 12kHz; m=10% for f = 19kHz

November 14, 1986

7-127

Signetics Linear Products

Product Specification

Frequency Multiplex PLL Stereo Decoder

IDA 1005AI 1005AI

r-------,--------,--------,

+10

-10~

______

~

______

~

______

o

~

150

NOTE:
Vee'" 15V; .6.fvco "'- fveo - 76kHz where: fveo "" modulated, free·running oscillator frequency; AfycO
is switched on.

=

maximum fveo deviation which will be captured if pilot signal (Pin 11)

Figure 15. Typical Values of the Capture Range of the Oscillator as a Function of the Pilot
Threshold Voltage at MUX Input

10'

10'

;;:

S

TYP

,;10

1
1000

0

Figure 16. Pilot Input Voltage Switching Level (Stereo 'On') as a Function of Resistance Between Pins 8 and 13

60

/'"

40

/

VTYP
20

o

/

V

/
1.5

0.5

Figure 17. Channel Separation as a Function of V6.16 at 1kHz (Smooth Take-Over)

November 14, 1966

7-128

TDA1578A

Signetics

PLL Stereo Decoder
Product Specification

Linear Products
DESCRIPTION
The TDA 1578A is a PLL stereo decoder
based on the time-division multiplex principle.

FEATURES
• Adjustable input and output
voltage levels
• Automatic mono/stereo switching
with hysteresis, controlled by
both pilot signal and field
strength level
• Analog control of mono/stereo
changeover

•
•
•
•

Pilot indicator driver
Analog muting control
Muting indicator driver
Oscillator with decoupled
frequency measurement output
• Electronic smoothing of the
supply voltage

PIN CONFIGURATION
N Package
LEFT
FEEDBACK
RIGHT
FEEDBACK
RIGHT OUT
VCO IN!
MODESEL

LEFT OUT
MODESEL
PHASE
DETOUT

APPLICATION

COMP

• PLL decoder

VCOCOMP

TOP VIEW

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

o to

18-Pin Plastic DIP

+70°C

ORDER CODE
TDA1578AN

PlLALTER

VO<.

3.3nF

3.3nF
VoR

Vee = 15V

v..,s

(0 !'o~4V) VuttrE

Vee

z

15V

NOTE,
Values given in parentheses are for Vee = 8.5V.

Block Diagram With External Components; Used as Test Circuit

November 14, 1986

7-129

853-0971 86551

I

Signetics Linear Products

Product Specification

TDA1578A

PLL Stereo Decoder

ABSOLUTE MAXIMUM RATINGS
SYMBOL

RATING

PARAMETER

UNITS

Vcc

Supply voltage (Pin 8)

20

VIN

Input voltages (Pins 3, 4 and 5)

V

o to 12

V

VOUT

Indicator driver output voltage

24

V

lOUT

Indicator driver output current

30

mA

Po

Total power dissipation at TA = 25·C

1.2

W

TSTG

Storage temperature range

-65 to + 150

·C

TA

Operating ambient temperature range

-30 to +80

·C

()CA

Thermal resistance from crystal to
ambient

80

·C/W

DC ELECTRICAL CHARACTERISTICS

SYMBOL

Input signal: m=100% {Ll.f = ±75kHz); pilot signal: m=9% (Ll.f=±6.75kHz);
Modulation frequency: 1kHz; V 3 _ 5 = V4 _ 5 = OV;
De-emphasizing time: t = 50/1s; oscillator adjusted to fosc at a pilot voltage VI = OV;
TA = 25 ·C, unless otherwise specified.
Vee
(V)

PARAMETER

LIMITS

UNIT

Min

Typ

Max

7.5

8.5

18

V

40

mA
mA

Vcc

Supply voltage range (Pin 8)

Icc
Icc

Supply current (except
output and indicator) Pin 8

8.5
15

21
30

VMUX(P-P)
VMUX(P,P)

Nominal multiplex input
voltage (peak-to-peak value)
RI = 47k!1

8.5
15

0.5
1.0

V
V

Overdrive reserve of input
at THD= 1%
at THD = 0.3%

8.5
15

6
6

dB
dB

0.75
1.5
1.2
2.4

V
V
V
V

VO(RMS)
VO(RMS)
VO(RMS)
VO(RMS)

AF output voltage (RMS value; mono without pilot)
R15-18 = R16 -17 = 15k!1
R15 - 18 = R16 - 17 = 24k!1

8.5
15
8.5
15

Overdrive reserve of output 1
R15 - 18 = R16 - 17 = 24k!1
±Ll.VolVo

Spread in output voltage levels1

±Ll.V15_161V0

Difference of output voltage levels1

Ro

Output resistance 1

3
3

3

dB
dB

1

dB

low-ohmic

±Io

Available output current Pins 15 and 16 1

V15;16-7

Modulation range at output (unloaded) 1

10

Internal current limiting1

V15;16-7
V15;16-7

DC output voltage
R15 - 18 = R16-17 = 24k!1

8.5
15

-1 17;18
-117;18

DC current
(Pins 17 and 18)

8.5
15

a;
a;

Channel separation
at V 4 _ 5 =OV

8.5
15

THD
THD

Total harmonic distortion

8.5
15

0.1
0.04

SIN
SIN

Signal-to-noise ratio
f = 20Hz to 16kHz

8.5
15

87
90

November 14, 1986

1

mA

7-130

3.6
7.0

32
39

1 to V9_7-1

V

15

mA

4.1
7.7

4.6
8.4

V
V

33
23

/1A
/1 A

50
50

dB
dB
0.3
0.1

%
%
dB
dB

Signetics Linear Products

Product Specification

Pll Stereo Decoder

TDA1578A

DC ELECTRICAL CHARACTERISTICS (Continued) Input signal: m = 100% (Af = ± 75kHz); pilot signal: m = 9%
(AI = ±6.75kHz); Modulation Irequency: 1kHz; V3 _s = V4_S = OV;
De-emphasizing time: t = 501lS; oscillator adjusted to lose at a pilot
voltage VI = OV; TA = 25'C, unless otherwise specilied.

SYMBOL

Vcc
(V)

PARAMETER

LIMITS
UNIT
Min

Typ

Max

"'S7(VWF)

Carrier and harmonic suppression at the output
pilot Signal; I = 19kHz1
subcarrier; 1= 38kHz1
1= 57kHz 1
1= 76kHz1
intermodulation 1
1M = 10kHz;
spurious signal Is = 1kHz
PLL-lilter Figure 11
PLL-lilter Figure 21
1M = 13kHz;
spurious signal Is = 1kHz 1
traffic radio (VWF)2;
1= 57kHz 1

70

dB

"'67

SCA (Subsidiary Communications Authorization);
1= 67kHz4,1

70

dB

ACI (Adjacent Channel Interference)3
f= 114kHzl
1= 190kHz1

80
52

dB
dB

43

dB

"'19
"'38
"'S7
"'76

"'2
"'2
"'3

cx 114
0:190

40

Ripple rejection at the output; I = 100Hz;
VeC(RMS) = 100mV (Pin 8)1

40

RRtOO
V9 _ 7

Voltage on lilter capacitor without external load 1

R9 _8

Source resistance 1

32
50
46
60

dB
dB
dB
dB

50
70

dB
dB

75

dB

V

Vee- O.25
6

8

10

kU

21
43
15
30

30
61

6
12

mV
mV
mV
mV

Mono/stereo control
VI(P_P)
VI(P_P)
VI(P_P)
VI(P_P)

Pilot threshold voltages (peak-to-peak values)
lor stereo 'ON'
lor mono 'ON'

8.5
15
8.5
15

AVI

Switch hysteresis
VIONIVIOFF 1

3

dB

tSTON
tMON

Switching time at C14 _ 7 = 0.221lF
lor stereo 'ON,1
lor mono 'ONol

15
27

ms
ms

External mono/stereo controlS (see Figure 12)
V14 - 7
V14 - 7
or: -V4- S'

Switching voltage lor
external mono control

8.5
15

-V4_S
-V4-S
AV4_s '
-V4-S
-V4- 5

Control voltage lor channel separation: '" = 6dB

8.5
15

120
130

8.5
15

70
80

mV
mV
mV
mV
mV

8.5
15
8.5
15

240
270
220
250

mV
mV
mV
mV

-V4_S
-V4-5
-V4- 5
-V4_S
AV4_7

November 14, 1986

0.7
1.4
315

±20
'" = 26dB
Control voltage
lor mono 'ON'
lor stereo 'ON'
Control voltage difference lor'" = 6dB; stereo 'ON'

7·131

8.5

80

100

120

V
V
mV

mV

•

Signetics Linear Products

Product Specification

PLL Stereo Decoder

TDA1578A

DC ELECTRICAL CHARACTERISTICS (Continued) Input signal: m = 100% (Af = ± 75kHz); pilot signal: m = 9%

(Af = ± 6.75kHz); Modulation frequency: 1kHz; V3_5 = V4 _ 5 = OV;
De-emphasizing time: t = 501lS; oscillator adjusted to fosc at a pilot
voltage VI = OV; TA = 25°C, unless otherwise specified.

SYMBOL

Vee
(V)

PARAMETER

LIMITS
UNIT
Min

Typ

Max

Muting circuitS (see Figure 13)
-V3- 5
-V3-5
AV3_5'
-V3- 5
-V3-5

Control voltage for an
attenuation:  50}.tA for Vee"" B.5V) and 10 < 1mA.

Figure 3

30

40

./

/

/
30

V

1

/

Jl

/

/

20

/
10

I/

/
o

10
Vee (V)

10

o

20

=

Figure 5. Supply Current Consumption at V9-7

100

0.3

I/~o~

50

f

........

o
o

/LJ)=O

o.1
.........

........

..... V
10

0

20

L= -R

/

......

Vee (V)

=Vee

I

0.2

C
.5
~

20

10
Vee (V)

Figure 4. Signal Handling Range at the Input for ISNOM
(± 75kHz); V9-7 Vee

;.::

V

10

--

",
20

../ "

.~ r. . .
30

-+-NOM.

40

1
50

(±7SkHz)
10(14') (,08980S

Figure 6. DC Current in the Feedback
Loop of the Output Amplifier

November 14, 1986

Figure 7. Total Harmonic Distortion (THO) as a Function of
the Peak-to-Peak Input Current at Pin 6; Vee = 15V;
fM = 1kHz; V3 - 6 = V4_5 = OV

7-134

Product Specification

Signetics Linear Products

Pll Stereo Decoder

TDA1578A

D.'
11

0.3

lC

F~

~~~~~L~~~~-H~m

0.2

i!'
D.'

,--

o

:::--

D.'
ty(kHz)

DL-LL~lliL-L~llW~-U~ill

0.01

'0

0.1

10

NOTES:
_ _ Mono.
- - - Stereo; L""-R; 91% +9% pilot signal.
Vee = 15V
i6{P _ P} =

21.5/1A

Figure 8. Total Harmonic Distortion (THO) as a function
of the Modulation Frequency (fM)

Figure 9. Channel Separation ('"'"

12

>

...00:

10
8

.......-

.
.'"

-+-

LAMP ON

I

,/

z

C

r--

0:

'"::>
0:

-=;::AMP OFF

~

8

'"
0

4
2
0
-40 -20

8

20

40

80

TEMPERATURE - ·C

November 14. 1986

80

-1.0

iii0

-2.0
-80 -40-20

8 I-Vt'2V.1.
4

TA=- _40°C

2
0

~
~

!?'-

~

.....
'~

-2
-4

--

//

100

......"

+85°C

I
I

10

20

30

40

80

40 80

80 100

z
2
....
c0:

80

70

50

T,,_25°C
V.12V
'-1kHz

"-

V

:
...

30

'"zz
cx

20

i-- -INPUT SIGNAL = 30mVrms

0

10

r- -

40

0
-2.0

MULTIPLEX SIGNAL
(L=1. R=O. PILOT OFF) =
150mVrme

-1.0

0

1.0

OSCILLATOR FREE RUNNING
FREQUENCY ERROR - %

PILOT LEVEL - mVrms
OP09350S

7-157

80

III

+8S·C

50

.,...

.

+25·C>i~
0

20

OP09330S

I

_40°C .......~ .......

-6

0

TEMPERATURE - ·C

Channel Separation vs
Oscillator Free-Running
Frequency Error

v:::l---

.....~_

........

-1.5

0.,,,,,,,,

+25·C;-1~

-.8
0

0

Capture Ranges vs
Pilot Level

I

-v l.'2J

800

-

0
-0.5

..........'"

. . . .V

0

0.5

z

0

./

0:

C

T.-25·C

10

0

1.0

'"::>
...'"0:0:

V

0
lE

Vl'2~

1.5

'",..0

I

is
0

2.0

I
a:
0
a:
a:

T._25·C
V.12V

III

C.0.47.F

10

Oscillator Free-Running
Frequency Error vs Ambient
Temperature

Harmonic Distortion vs
Input Level

OP0938OS

2.0

•

Signetics Unear Products

Product Specification

MA758

FM Stereo Multiplex Decoder, Phase-locked loop

TEST CIRCUIT AND TYPICAL APPLICATION
V+"+12V

Cs
O.33j.1F

COMPOSITE
MULTIPLEX
UNIT

"3

21 kn

LEO
STEREO

INDICATOR

"4

LAMP

SkU
OSCILLATOR
AOJ

LEFT

OUTPUT

~t::U~

.....- ; - - - - - - - j

(TQPVIEWI

NOTE:
Tolerance on resistors is ±5% and tolerance on capacitors is ±20%, unless otherwise specified. C1 tolerance=+10Q%; -20%, Cs tolerance=±1% in test circuit and
±5% in typical applications. R3 tolerance=±1%, R4 tolerance=±10%, R1 and R2 tolerance=±1% in Test Circuit and ±5% in Typical Application.

November 14, 1986

7·158

Signetics

AN191
Stereo Decoder Applications
Using the J.LA758
Application Note

Linear Products

INTRODUCTION
The phase-locked loop (PLL) has been used
for many years in consumer equipment. Due
to the nature of FM Stereo Multiplex Systems,
where prime importance is the channel separation, discrete systems lacked the tracking
ability over wide temperature and voltage
ranges to be done economically.
The development of the monolithic PLL and
improvements in IC processing have made
the Phase-Locked Loop FM Stereo Multiplexer Decoder a reality.

MAJOR ADVANTAGES
The economic advantages in using the PLL
multiplex decoding system are not only cost
reduction, by eliminating peripheral components, but the man-hour cost reduction by
eliminating turning coils, thereby eliminating
tedious alignment procedures.
The cost advantages are extremely significant and are in addition to the following:
• 45dB channel separation
• Automatic stereo/mono switching
• Stereo indicator lamp driver with current
limiting
• High impedance input -low impedance
outputs
• 70dB SCA rejection (subsidiary carrier
authorization)
• One adjustment for complete alignment
• 10V to 16V supply voltage range

FM STEREO MULTIPLEX
SUBCARRIER AND PILOT
The two (2) basic signals differentiating an
FM stereo multiplex signal from an FM mon-

February 1987

aural signal are the 19kHz pilot and the
38kHz subcarrier. The frequency and phase
relationship of these signals is well defined.

p.A758 is suitable for all line-operated and
automotive FM Stereo Receivers.

Earlier systems had to reconstruct the 38kHz
subcarrier by using the 19kHz pilot. This
system required frequency multipliers and
selective filters (coils). Since maximum channel separation is directly related to proper
phasing, alignment procedures were extremely critical and therefore expensive. In addition,
long-term stability and performance were degraded due to component aging, and temperature.

REFERENCING THE BLOCK
DIAGRAM

Use of the PLL as the multiplex decoder
eliminated these shortcomings since the
phase accuracy of the 38kHz signal is limited
only by the loop gain of the system and the
free-running oscillator stability. Both of these
parameters are easily controlled, providing
easy, rapid adjustment and excellent longterm stability.

GENERAL DESCRIPTION
The p.A 758 is a monolithic Phase-Locked
Loop FM Stereo Multiplex decoder using the
16-lead DIP N package. This integrated circuit
decodes an FM Stereo Multiplex Signal into
Right and Left audio channels while inherently suppressing SCA information when it is
contained in the composite input signal. Internal functions include automatic mono-stereo
mode switching and drive for an external
lamp to indicate stereo mode operation.
The J1.A758 operates over a wide supply
voltage range and uses a low number of
external components. It has only one control
to adjust a potentiometer to set oscillator
frequency. No external coils are required. The

7-159

The upper row of blocks comprises the PLL
which regenerates the 38kHz subcarrier, necessary for multiplex signal demodulation. The
basic 76kHz generator is VOltage-controlled,
and is divided by two to insure a 50 % duty
cycle 38kHz internally-generated signal. This
symmetry is necessary for maximum left/right
channel separation and SCA rejection (bandcentered at 67kHz). Dividing the 38kHz by
two generates the 19kHz signal necessary to
lock on to the incoming pilot signal. A second
19kHz signal is generated which is in quadrature to the first internally-generated 19kHz
signal and in phase with the pilot. This second 19kHz is mixed in a quadrature (synchronous) phase detector to operate the stereo
switch and lamp driver circuity.
When ~a stereo signal is present, the stereo
switch enables the stereo demodulator, and
when a stereo signal is not present, the
demodulator is disabled, allowing the system
to reach optimum noise performance.

FUNCTIONAL OPERATION
To aid in understanding the system operation,
the J1.A758 equivalent circuit has been broken
down into subsections as follows (see Figure
2):

II
III
IV
V
VI

Buffer Amplifier and Bias Supplies
Demodulator
Stereo Switch and Lamp Driver
Voltage-Controlled Oscillator
Frequency Dividers
Pilot Phase and Amplitude Detectors

•

i

(/)

ci'

U>

r:r

....eD
CD

j

0
0
CD

~
.....

()

O

Q.

y'

I
DETECTOR
INPUT

_L

SWITCH FILTER

LOOP FILTER

v'"

OUTPUT

~

~~r
c
~

(1)

Q
"U

aDc
0

ur

»

9

1.0

"0
"0

.4

0"
0

I
I

-+

0"
::J

.21

fA

c:

I

fA

I

(Q

-u

~

CD
....

OSCILLATOR Re NETWORK

.I

~I

cO"

S"

.9kHzTEST

-+

LEFT CHANNEL
OUTPUT

CD

L-------------------------t-----t-----------------------------~====~~--_rl~· ~GN~
4_
\ -__-+1_

2

II
• -: I

---It---'L

T

___
LEFT CHANNEL

~I

\----1-- ~~~ANNEL
'--_....J
.J

-

3

DE-EMPHASIS

"::J

$.

"

(11

00

RIGHT CHANNEL
DE.fIIPHASIS

}>

D

Figure 1. Block Diagram

»
z

"Q.

..:..

<)"

-0

z

..:..

~
~

~

Application Note

Signetics Linear Products

Stereo Decoder Applications Using the pA758

AN191

I

I

I
I
I
I
I
I
I

I
I
I
I

-:--l
I
I

I
I

I
I

I
I
I

I
I

I •

I ~
I ~
I •

I ~
I

~

:l
1,* HI'

February 1987

7-161

•

Signetics Linear Products

Application Note

Stereo Decoder Applications Using the pA758

I. Buffer Amplifier and Bias
Supplies (Figure 3)

COMPOStTE
MULTIPLEX

The zener diode, Z, and its associated transistors generate a 6V internal voltage reference source. From this 6V reference, additional bias levels are established via resistors
R3, R4, and R5. In addition, transistor Q7 acts
as the control source for several current
mirrors; Q11 in the Buffer Amplifier, Q43 and
Q44 in the Stereo Switch and Lamp Driver
(III) and Q67 and Q73 in the Voltage Controlled Oscillator (IV).

AN191

•

INPUT

V'

--~--------------4r--~--~--~-------,

Z1

The input Buffer Amplifier (Q8, Q9) level
shifts the composite multiplex input signal to
2 levels each in phase with each other.

'SV

Transistors Q10-Q13 amplify this same signal by the ratio of:
R14
A=R13
This amplified signal, the gain of which is
independent of supply voltage variation, is fed
to the Pilot Phase and Amplitude Detectors
(VI).

AMPliFIED
MULTIPLEX

SIGNAL TO
DETECTORS

II. Demodulator (Figure 4)
The basic demodulator, Q25 - Q30, is a fullybalanced detector similar to standard phaselocked loop types. The addition of resistors
R29, R30, and R31 introduces a small offset
to allow a small multiplex signal in the collector of Q30. This Signal compensates the
crosstalk components inherent to the synchronous switching demodulation process.

"'O.7V

TO DEMODULATOR

Figure 3. Input Buffer! Amplifier and Bias Supply

021

VMOO

'22

'21

022

.23

H2'

022

lEFT

-,

lEFT
OUTPUT

DE EMPHASIS

RIGHT
OUTPUT

..L.

T

.".

Va = (V+ + VMOO) - (VSE + V01 +
[R22 lAd + VMOO)
where VSE = base-emitter voltage across
Q22 and Q23

(HIGH)

COMPOSITE

Switching to the left and right channels is
accomplished through Q25 and Q26 when
the 38kHz drive is present at their bases. This
occurs when Q33 is "on." When Q33 is off, a
DC bias is placed at the bases of Q25 and
Q26 through resistors R32 and R33, this
automatically converts the system to monophonic operation.
Supply voltage rejection is accomplished at
the demodulator outputs by converting the
audio to current supplies in Q23 and Q24.
The voltage developed across PNP transistors is

(LOW)

MULTiPlEX SIGNAl

.".

.,;:.

(HIGH)

= modulation on the power line
COMPOSITE

MULTIPLEX

= diode drop in D21
(R22)IAC= voltage drop due to current in
the demodulator

(LOW)

_

Simplifying the above reduces to
Ve = V+ - (VSE + V01 + R22 lAC)

...... INPUTS
(1)
Figure 4. Demodulator

February 1987

7-162

180

STEREO/MONO
SWITCH

Signetics Linear Products

Application Note

Stereo Decoder Applications Using the pA758

AN191
,I

The output voltage developed is
V+

VOUT

=

(~)REXT
R21

(2)

',v - - - - t - - - - - ,

."

where REXT = external resistor

."

A4.

A48

STEReo
INDICATOR
LAMP

The output voltage at Pins 4 and 5 are
provided through 1.3k resistors driven by
emitter-followers Q21 and Q24.

ilL Stereo Switch and Lamp
Driver (Figure 5)
The pilot amplitude detector differential voltage is sensed by the differential amplifier Q41
and Q42. This pair, in conjunction with their
load resistors (R41, R42), controls amplifiers
Q45, Q46. Positive feedback action is
achieved through Q47, R50, Q50 and R46
(which turns off Q44).
The turn-on threshold is the differential input
voltage required to overcome the offset voltage required to overcome the offset voltage
in R43 times the current summation of IR44
and 'R45 . When the lamp is on, Q44 is off and
the differential voltage across R43 is reduced
by the amount (IR45 X IR43), which means a
lower turn-off voltage is required. This voltage
difference is referred to as the switch hysteresis.

INPUT FROM
PflOT AMPLITUDE
DETECTOR

(-)

t--t-~Q4.

...

.43

(.) ----+-------1
Q49

·0.7V

,l-----+-+---+

...

_--~-:-~_ _ _;:~

A51

R45

STEREO/MONO
CONTROL
TO DEMOOULATOR

Transistors Q48 senses the current across
R51 which therefore controls the maximum
current in the Stereo Indicator Lamp.

TC07950S

Figure 5. Stereo Switch and Lamp Driver
(3)

071

IV. Voltage-Controlled Oscillator
(Figure 6)

I

The basic oscillator Q71 - Q79 is an RC
relaxation type which generates a positive
low duty cycle, 76kHz output. The frequency
is established by Equations 4 and 5.
The control voltage from the phase detector
into the transconductance amplifier
Q61 - Q69 converts the differential error to a
bidirectional single-ended current drive to the
oscillator.
Voltage on the capacitor is compared with the
set voltages by the differential input stage
Q71, Q72. This feeds Q74, Q75. The output
of Q75 drives a PNP inverter, Q76, (whose
action eliminates power supply modulation as
described in the demodulator section of this
note), when these set limits are reached the
direction of charge reverses.

(+)-i--+-+-,

CONTROL VOLTAGE
FROM
PHASE OETECTOR (

-J

+0.7V

-i---lir"""---+-i--i;.

.'4
'":' RS'
lk H

r-¥rOSCILLATOR

r-!!

FREQUENCY ~

I

::;:

*

Figure 6. Voltage-Controlled Oscillator (VCO)

February 1987

7-163

.,.

."

I

Application Note

Signetics Linear Products

Stereo Decoder Applications Using the 1lA758

Lower set voltage is set by R79, R80, and the
regulated 6V supply. The upper set voltage
(VH) involves two (2) additional resistors R77
and R78 and is established when 076 turns
on 077. Both set levels are referenced to the
regulated 6V supply and are therefore dependent only on resistor ratios. (Proper design
layout should also eliminate temperature variations.)
Capacitor charging is through 078 and R8
and discharging through the external fixed
resistor.
Equations 4 and 5 of Figure 7 are first-order
expressions for the change and discharge
periods.
079 supplies a positive output pulse necessary to operate the 38kHz dividers.

V. Frequency Dividers
(Figure 8)
Transistors 091 through 094 form a simple
divide-by-two circuit which converts the pulse
output from the 76kHz oscillator to a 38kHz
square wave.
The divider changes state during the positive
excursion of the input pulse supplied from the
emitter of 079 in the oscillator. Initially, when
the input is low, 091 and 092 are OFF and
we may arbitrarily assume 093 is ON and
094 is OFF.
As the potential on the input rises, 091 starts
conduction before 092 because the emitter
of 091 is at a lower potential than the emitter
of 092. (The emitter of 091 is connected
through R95 to the collector of 093 which is
in saturation, whereas the emitter of 092 is at

AN191

v s ------------------------------------------------------

.E'

VOLTAGES

~"I--I- ' , - - - l
NOTES:
Basic timing equations:

VS-VL

t1 = R81 C 1n----

(Equation 4)

VS-VH

VH
t2 = RC 1n(Equation 5)
VL
where A and C are external components on Lead 15, RB1 is on the chip, and VH and VL are
set voltages which are a fixed percentage of Vs, the internally-regulated 6V supply.

Figure 7. Oscillator Waveforms
the VSE(ON) potential of 093). Since 091 is
ON, the current from both R92 and R93 flows
through the emitter of 091 into R95. As this
current increases, the rising voltage at the
emitter of 091 turns 094 ON which removes
base drive to 093 and turns it OFF, thus
producing a change-of-state in the divider.
Even though the relative potentials at the
emitters of 091 and 092 are now reversed,
current continues to flow in 091 for the
duration of the positive input because 092 is
held OFF by 091. When the input returns to a
low potential, 091 turns OFF. The divider

remains in its present state until driven by the
next positive-going input.
Oppositely phased 38kHz outputs to the demodulator are taken from the collectors of
093 and 094. Transistors 095 and 096 are
used to drive the two 38kHz dividers.
The 38kHz Ouadrature Divider has an identical configuration to the 76kHz divider. A
change-of-state occurs with each positive
excursion of the 38kHz input signal from the
emitter of 096.

38kHz OUTPUTS
TO DEMOOULATOR

,eo'

76kHz
INPUT

r-----------------~--t_~--~--~~--------------------~------~------------~~·.v

270"

Figure 8. Frequency Dividers

February 1987

7-164

'so'

Application Note

Signetics Linear Products

Stereo Decoder Applications Using the pA758

The 38kHz in-phase divider contains a bistable pair, 0113 and 0114, steered by inputs
into 0111 and 0112, (a 38kHz input from the
collector of 095, and 19kHz inputs from the
bases of 0103 and 0104). If the 19kHz input
to the base of 0111 is high when the 76kHz
divider turns 095 ON, 0111 conducts and
removes drive to 0114, changing the state of
the bistable pair, 0113 and 0114. The bistable remains in this state until the next 38kHz
turn on of 095 which, this time, turns 0112
ON, removes drive to 0113 and resets the
bistable pair. The resulting 19kHz output from
0113 and 0114 is at 90 0 to the quadrature
divider output with no ambiguity in phasing.

270"

180"

19kHz INPUTS

R132

19kHz
TEST SIGNAL

"
r-=,-+t--=,.---------- (.)

((-)------~~~+i~~~
·) _____

'-+JVlt.-......------- ( • )

+'w~.J

PHASE
DETECTOR
OUTPUT

VI. Pilot Phase and Amplitude
Detectors

AMPLITUDE

OETeCTOR
OUTPUT

13

J····""""······I~···..
:.·.·.·.•.·11.·.·.•...1

The pilot phase detector and pilot amplitude
detector, as shown in Figure 9, are synchronous, balanced chopper types which develop
differential output signals across external filters. Back·to·back NPN transistor pairs are
used for each switch to insure minimum drop
regardless of signal polarity without reliance
on inverse NPN beta characteristics.
The chopper transistors (0121 through 0(24)
in the phase detector are driven from the
38kHz Ouadrature Divider through transistors
0125 and 0126. The input signal is supplied
from lead 12 through resistors R125 and
R126. A differential output is developed
across the loop filter, comprised of resistors
R123 and R124 and the external RC network
between leads 13 and 14.

AN191

lOOP FILTER

.

DeTECTOR
INPUT

10

9!

l.·········I~········.1
SWITCH FILTER

Figure 9. Pilot Phase and Amplitude Detectors

V... • ... 12V

"

~r5"_Ft-________-i
COMPOSITE

MULTIPLEX
UNIT

'3

21 kH
LEO

STEREO

The pilot amplitude detector (0131 through
0(36), has an identical configuration to the
phase detector. Since it operates with drive
which is in phase with the pilot signal (90 0
from the drive to the phase detector), its
output is proportional to the amplitude of the
pilot component of the multiplex signal. The
differential output at leads 9 and 10 is filtered
by the external capaCitor on these two leads.

",

5kO

OSCILLATOR

O~~~T

AOJ

--+---------1

A reference 19kHz square wave signal is
taken from the collector of drive transistor
0136 through resistor R137 to lead 11. It has
the same phasing as the pilot contained in
the multiplex input signal.

I
nOPVIEW)

NOTE;
Tolerance on resistors is ± 5% and tolerance on capacitors is ± 20% unless otherwise specified.
C1 Tolerance"'" + 100%, -20%
C6 Tolerance=±1% in test circuit and ±5% in typical application
R3 Tolerance = ± 1 %
R4 Tolerance = ± 10%
R1 and R2 To!erances = ± 1 % in test circuit and ± 5% in typical application

Figure 10. Test Circuit 1 and Typical Application

February 1987

7·165

Signetics Linear Products

Application Note

Stereo Decoder Applications Using the pA758

Channel Separation as a Function
of Audio Frequency

Channel Separation as a Function
of Oscillator Free-Running
Frequency Error

AN191

Capture Range as a Function
of Pilot Level

I I !
,I

I

AI

I

I

VI '"
!
i
TA : 2l>"C

-V"I2V

......-

I
! I
I !

'T"' i

Total Harmonic Distortion as a
Function of Input Level

1,,·1.0

.

,.,'>v

!~
,

I

I'

! 1/

,

V

i

/

......-v
, .....-

,/'

/'

JOmv"",

"U~ lOPl £~ Sh~NAl

IL" 11l·0.PK01OFf\·
150",Y",.. ,

Lamp Turn-On and TurnOff Sensitivity as a Function
of Ambient Temperature

I

!

i I
IN~UTSIGlA~

!

c-)",-L

.

P'LOTOff

"-

,

I
I

,

!

i
,

Oscillator Free-Running Frequency
Error as a Function of
Ambient Temperature

L-

~"~,,,

I

I--

!

I

!
I

~OF:.!.

I

1

I

i

I

!

!

!

i

I

I

,

I

i

I

I,

!

,

,
,

i

I

I

I

!

I

!
I

Figure 11. Typical Performance Curves for the pA.758 (Test Circuit 1 Unless Otherwise Specified)

February 1987

7-166

!

I

i

I ! I
[.....,' !

I

!

!

,,

I

I

V,

I ! I

_,.t!

I

1!

I

NE542

Signetics

Dual low-Noise Preamplifier
Product Specification

Linear Products

DESCRIPTION

FEATURES

The NE542 is a dual preamplifier for the
amplification of low level signals in applications requiring optimum noise performance. Each of the two amplifiers is
completely independent, with individual
internal power supply decoupler-regulator, providing 110dS supply rejection
and 70dS channel separation. Other
outstanding features include high gain
(104dS), large output voltage swing
(Vcc-2Vp_p), and internal compensation
to 10dS. The NE542 operates from a
single supply across a range of 9 to 24V.

• Low noise - O.7IlV total input
nOise
• High gain -104dB open-loop
• Single supply operation
• Wide supply range g to 24V
• Power supply rejection 110dB
• Large output voltage swing
(Vcc- 2V p_p)
• Wide bandwidth 15MHz unity
gain
• Power bandwidth 100kHz (15V p_p)
• Internally-compensated (stable at
10dB)
• Short-circuit protected
• High slew rate 5V I /lS

The NE542 is ideal for use in stereo
phono, tape, or microphone preamps
and other applications requiring low
noise amplification of small signals.

PIN CONFIGURATION

N Package
+ I N ( l ) O a +IN(2)
-IN (1) 2
7 -IN(2)
OND

3

8 Vce
5 OUTPUT (2)

OUTPUT (1) 4

TOP VIEW

APPLICATIONS
• Tape preamplifier
• Phono preamplifier
• Microphone preamplifier

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

o to

8-Pin Plastic DIP

ORDER CODE

+70·C

NE542N

EQUIVALENT CIRCUIT

,----I
I
I
I
I

I

RJ

I

01

I

I

I

,

,

I
I
I
I

I
I

I
I
Z1

L ___ -L _ _ _

November 14, 1986

II

----I
I

I

14,5)

I
_

7-167

I
I
_ _ _ _ .L _ _ _ _ -.l

853-0946 86554

Signetlcs linear Products

Product Specification

NE542

Dual low-Noise Preamplifier

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

RATING

UNIT

Vcc

Supply voltage

+24

V

Po

Power dissipation

500

mW

TA

Operating ambient temperature range

TSTG

Storage temperature range

-65 to + 150

°C

TSOLD

Lead soldering temperature
(10sec max)

+300

°C

o to

+70

°C

DC ELECTRICAL CHARACTERISTICS TA = 25°C; Vcc = 14V, unless otherwise specilied.
LIMITS
PARAMETER

SYMBOL

UNIT

TEST CONDITIONS
Min

Vce

Supply voltage

Icc

Supply current

RIN

Input resistance
Positive input
Negative input

ROUT

Output resistance

Typ

9
Vee = 9 to 18V, RL =

9

00

Open-loop

Max

24

V

15

mA

100
200

kn
kn

150

n

AC ELECTRICAL CHARACTERISTICS TA = 25°C; Vee = 14V, unless otherwise specilied.
LIMITS
PARAMETER

SYMBOL

TEST CONDITIONS

UNIT
Min

Av

Voltage gain

liN

Negative Input current

lOUT

Output current

VOUT

Output voltage swing

SR

Small signal bandwidth
Slew rate

Paw

Power bandwidth

VIN

Maximum input voltage

PSRR

Power supply rejection ratio

THO

Total harmonic distortion

Channel separation

Total equivalent input noise

Noise ligure

November 14, 1986

Open-loop

Typ

Max

160,000

VIV
0.5

Source
Sink (linear operation)

8
2

14
3

Vee -2.5

Vee -2

V

15
5

MHz
V/p.s

100

15Vp.p
Linear operation, < 2.5 % distortion

kHz
300

1=60, 120Hz
I = 1kHz

I = 1kHz

mA
mA

100
110
40

mVRMS
dB
dB

70

dB

40dB gain, I = 1kHz

0.1

0.3

%

Rs = 600n, 100 - 10,000Hz

0.7

1.2

P.VRMS

Rs = 50kn, 10- 10,000Hz
Rs = 20kn, 10 -10,000Hz
Rs = 10kn, 10 - 10,000Hz
Rs = 5kn, 10- 10,000Hz

1.2
1.2
1.5
2.4

7-168

dB
dB
dB
dB

Product Specification

Signetics Linear Products

NE542

Dual Low-Noise Preamplifier

TYPICAL PERFORMANCE CHARACTERISTICS
Large-Signal Frequency Response
> 22
20

..

~c~~2:I~tOR;:O~_

l

I

i'"

Gain vs Temperature

r-------r------,--------,

115

f----f-----I----j

!g

18

z

12

~

11

10

:

~

\

:>
0

\

~ •

110

\

-- -

11

I

14

...>

13
12

18

~
0

Vee vs lee

120

l

I-----f-----I----j

-

10

I

f-

-

]

> 105

I----f------l----j

100

L-----~2~.------~~~----~7S.

ci

'""

'-.

~

1k

1,Ok

lOOk

1M

10M

1.1
1.0

VCC=12V

L

~
0
In

I

'"

0.3

10

2.

PSRR vs Frequency
110

90
80

l

~

/

1\

90
80

r:~\
~OO.FdI

70 I-

10

z

~



150

30

165

20

180

10

10M

r::::;;~~====+===~

100

.,...

45

PHASE

60

'-~

Voltage Gain vs Supply Voltage

30

'\.

70

\

Av·'000
10

15

\.

/

FREOUENCY - Hz

o
lOOk

24

20

100k

Hz

20
10

L

FREQUENCY -

"""

100

22

./

120

110

""
:e

~

Gain and Phase Response

120

....

i.
z
z
c

V

10k

FREQUENCY -

SUPPLY VOLTAGE - V

100

1k

100

80

~

""B

o
20

/

_B/ Y

~

0.1

0

"~

NAB EQUIVALENT

0.'
0.2

,.

70

z

0.5

C

/

!1l

0.8

0

20

v------

80

0.7

I

18

Channel Separation

0.8

~

z

18

to

0.9

/

14

SUPPLY VOLTAGE - V

% Distortion

/

10

12

TEMPERATURE _ °C

Peak-to-Peak Output Voltage
Swing vs Vee

V

10

100M

FREQUENCY - Hz

,.

,.

25

20

SUPPLY VOLTAGE -

V

•

,

Signetics linear Products

Product Specification

Dual low-Noise Preamplifier

NE542

TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Noise Voltage vs Frequency

Noise Current vs Frequency

Pulse Response

16
NOTE: Rs=SOk

NOTE: Rs=O

AV=10

14

(j.e

12
N

Z

~

10

z

:>

i!

"" "

'>

~

0.6

~

0.4

~

i"-

100

lk
FREQUENCY -

10k

\

~

i-

0.2

\

100

Hz

lk
FREQUENCY -

-1

10k

-20-1~

0

10 20

Hz

TYPICAL APPLICATIONS

O.5VRMS

Typical Tape Playback Amplifier

Audio Mixer
Vee = +18V

12V

:>,-+-,--,---0 OUT
+--+---+--"---;

8800pF
91k

Two-Pole Fast Turn-On NAB Tape Preamp

RIAA Magnetic Phono Preamp

NOTE:
All resistor values are typical and in ohms.

November 14, 1986

7-170

30

4050 60

TIME - fAs

70

80

AN190

Signetics

Applications of Low Noise
Stereo Amplifiers: NE542
Application Note

Linear Products

Introduction
Stereo preamplifiers have come into greater
and greater demand with the increased usage
of tape recorders. With stereophonic recording systems, the need increased to have
multiple devices in the same package to
insure greater thermal tracking and packing
density, without sacrificing performance.
The NE542 qualifies as a low noise dual
preamplifier. The NE542 is an 8-pin dual inline device.
This device has greater than 100dB openloop gain and (15 - 20) MHz gain bandwidth
product. In selecting the proper "low noise"
preamplifier, several factors must be considered.
1. Frequency shaping characteristic required.
2. Closed-loop response with respect to a
system reference level.
3. Response of the record/playback head.
4. System distortion requirements.
5.

Response of the tape used.

Known as the NAB equalization curve, the
standard deemphasis employs attenuation
from the turnover frequency of 50Hz to the
turnover frequency of 3180Hz for 7.51ps recording. The slower recording speed of
3.751ps employs turnover frequencies of
50Hz and 1326Hz. These curves are shown
in Figure 1. A reference level of 800lN head
sensitivity at 1kHz is also used by the NAB.

STEREO PREAMPLIFICATION
The voltage level appearing at the output of
tape playback heads and some phono cartridges are too small to be useful without a
(72) 4 0

5
(32) 30

Z

"

2S

RIAA standards call for a maximum recording
velocity of 21 cm/sec for stereo discs. This
worst-case velocity describes a limit for the
preamplifier gain because the input signal at
this velocity is maximum.

NAB TAPE EQUALIZATION
Recording and playback characteristics of
magnetiC tape and record/playback heads
are not flat but exhibit a loss at high frequencies and a boost at lower frequencies. To
obtain an overall flat frequency response and
improved signal-to-noise ratio, the audio signals are equalized by boosting the higher
frequencies in amplitude before recording.
Playback amplifiers must exhibit bass boost
to remove the effects of pre-emphasis for an
overall flat response.

February 1987

71/2 IPS
TURN OVER FREQUENCIES
50HZ, 3180Hz

\
--"'\
\

NE542 DEVICE DESCRIPTION
The NE542 is a dual low noise amplifier with
104dB open-loop gain produced by two stages of voltage gain followed by one stage of
current gain.

riME CONSTANTS

31801-11

so"'

~

In the design of low noise devices, special
attention must be focused on the input stage.
If differential topography is used, the stage
should be designed so that one of the differential transistors is turned off. This reduces
the noise contribution by a factor of 1.4 since
only one transistor is producing noise. Current sources and mirrors cannot be used for
biasing loads because active elements will
contribute more noise.

--J,7SIPS
TURN OVER FREQUENCY
50Hz. 1326Hz
\ , \ IME CONSTANTS

,\

~

~

(52) 20

~

5

\

3tBOps

"''''

\1\

5

'\

(32) 0

10

-

\'

(42) 10

The following will deal with Items 1, 2, and 4.
When approaching the design criteria of Item
2, the designer should be concerned with the
open-loop device characteristics. These characteristics will aid in determining the maximum boost available, knowing that a specific
loop gain (open-loop gain minus closed-loop
gain) will be necessary to keep the system
distortion low and maintain the output impedance of the" low noise" preamplifier constant
over the required operating frequency range.

large amount of low noise preamplification. In
addition to providing low noise amplification,
the preamplifier should possess enough
open-loop gain so that the RIAA and NAB
equalization curves can be produced in the
feedback networks of the amplifier. The following paragraphs describe the characteristics and applications of the 542. This device
provides a matched pair of amplifiers which
have been specifically designed to minimize
amplifier noise and maximize signal-to-noise
ratio.

100

lK

lOt(

lOOK

FREQUENCY (Hz)

Implementing these observations, the first
gain stage of the NE542 is pictured with the
complete schematic in Figure 2.

Figure 1. Tape Equalization Curves

Vee

r-----

-------,
I

I

I
I
I
I
I

I

ftl

I

I

01

I

I

I
I

I
I
I

I

Z1

I
I
I

I

I

I
_ _ _ _ .l.. _ _ _ _ .-J

1

L ___ ....l.. _ _ _
NOTE:
All resistor values are in

-

n.
Figure 2. Equivalent Schematic NE542

7-171

Signetics Linear Products

Application Note

Applications of Low Noise Stereo Amplifiers: NE542

AN190

Although the differential input configuration
degrades the noise performance slightly, using differential inputs has the advantage of
higher input impedance, allowing smaller capaCitors and larger resistors to be used to
achieve the RIAA and NAB curves.

vee

o

The second stage is a common-emitter amplifier (Qs) with a current source load (Q6). The
Darlington emitter-follower Q3 - Q4 provides
level shifting and current gain to the commonemitter stage (Qs) and the output current sink
(Q7). The voltage gain of the second stage is
approximately 2000, making the total gain of
the amplifier typically 160,000 in the differential input configuration.

"'•.s'----.....-o.svrms
2.2M

II
NOTE:
All resistor values are in

1500pF

n.

Figure 7. Typical NAB Record
Preamplifier

February 1987

621(

Figure 8. Typical Tape Playback
Amplifier

7-173

AN190

TDA1522

Signetics

Stereo Cassette Preamplifier
Product Specification

Linear Products

DESCRIPTION

• Head input at DC ground that
eliminates the input coupling
capacitor
• Minimal external component
requirement
• Stability down to a gain of 30dB
• Low input noise
• Low distortion
• DC input current < 2J.lA
• Wide supply voltage range

The TDA 1522 is a playback amplifier for
car radio/cassette players.

FEATURES
• Two independent amplifiers with
open-loop gain of typo 90dB
• Internal DC feedback via a
140kn resistor from output to
feedback point
• AC characteristics that can be
determined externally by an RC
network
• Electronic onloff switching with
transient suppression for switchon

PIN CONFIGURATION
U Package
1 OUTPUT 1

3 INVERTING INPUT 1

4 NON·INVERTING INPUT 1
5 GROUND
8 NON·INVERTING INPUT 2
7 INVERnNG INPUT 2

APPLICATIONS
• Cassette deck
• Preamplifier

lOP VIEW

BLOCK DIAGRAM
R102
8.2

C1III
22nF

R101
S.6k

TDA1522

FEEDBACK 1
RFB1

CC2

+lO"FF
OUTPUT2 Vo>
MUTE 0----.....1
R12
-: 4.7k
140k
FEEDBACK 2

ROO2
8.2

COOl

R2O!
S.6k

22nF

V+

November 6, 1986

7-174

853-0920 86396

Signetics Linear Products

Product Specification

TDA1522

Stereo Cassette Preamplifier

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

-30°C to + 85°C

TDA1522U

9-Pin Plastic SIP, (SOT-t42)

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

Vee

Supply voltage range (Pin 8)

PTOT

Power dissipation

IFB

Feedback current (Pins 3 and 7)

TSTG

Storage temperature range

TA

Operating ambient temperature range

RATING

UNIT

7.5 to 23

V

800

mW

10

mA

-65 to + 150

°C

-30 to +85

°C

NOTE:
All pins except 3 and 7 (feedback) can be connected to Vee (Pin 8) or ground (Pin 5).

DC ELECTRICAL CHARACTERISTICS Vee = 8.5V; TA = 25°C, unless otherwise specified.
LIMITS
SYMBOL

PARAMETER

UNIT
Min

Typ

Max

Supply (Pin 8)

Vee

Supply voltage range

lee

Supply current

7.5

23

V

5

mA

1.6

p.V

5

nV/YHz

Inputs (Pin 4 or 6)

VN(RMS)

Noise input voltage (unweighted; RMS value)
at / = 20Hz to 20kHz 1

VN

Noise input voltage at Rs

IN

Noise input current at /

-14; -16

DC input current at Pins 4 and 6

= 0; / = 1kHz 1,
= 1kHz 1, 3

2

1.2

pAlYHz
2

p.A

Outputs (Pin 1 or 9)

Vo
Vo
-10

Output voltage
at VI = 0.3mV; / = 315Hz
at THD = 1 %; / = 1kHz

0.72

V
V

10

mA

3.7

V

700
1200
1600

p.V
p.V
p.V

1800

I1V

1,0

Output source current
at V2 - 5> ;;" 7.5V; mute OFF

5

Vo

DC output voltage

VN(RMS)
VN(M)
VN(M)

Noise output voltage (weighted) at Rs
as DIN A (RMS value)
as CCID (peak value)
as CCIR (peak value)

VN(M)

Noise output voltage (unweighted) at Rs
as DIN 45405 (peak value)

= 300n;

Ls

= 300n;

= 80mH

Ls

= 80mH

Mute on/off characteristics (Pin 2)4

VM

Mute ON voltage at mute switch closed

1M

Mute ON current at mute switch closed or V2 _ 5

VM

Mute OFF voltage at mute switch open

0

= OV

1
2.7

7,5

V
p.A

Vee

V

Impedance

= 1kHz5
at f = 1kHz5

IZI!

Input impedance at /

IZol

Output impedance

November 6, 1986

200

kn
1

7-175

kn

Signetics Linear Products

Product Specification

TDA1522

Stereo Cassette Preamplifier

DC ELECTRICAL CHARACTERISTICS (Continued) vcc = 8.5V; TA = 25°C, unless otherwise specified.
LIMITS
SYMBOL

PARAMETER

UNIT
Min

Typ

Max

100

140

180

General

RFB

Internal feedback resistorS

Av

Open.loop voltage gain at f

ex

Channel separation at Rs

RR

Power supply ripple rejection at VCC(RMS) = 0.1V; f = 100Hz7

THD

Total harmonic distortion at f

= 315Hz 5

= 10kn;

90

Ls = 06

= 1kHz;

Va

45

= 0.72V8

NOTES:
1. Measured in Figure 1

2.
3.
4.
5.
6.
7.

See also Figure 3
See also Figure 4
See also Figure 2
Applies to each amplifier
Frequency range 300Hz to 20kHz
Referred to the input

e.

Measured selective

November 6, 1986

7-176

90

kn
dB
dB

95

dB

0.05

%

Signetics Linear Products

Product Specification

TDA1522

Stereo Cassette Preamplifier

C101

R101

R102
8.2

lO_F

9.1k

+
+

C102

~ 1OOO_F
TDA1522

FEEDBACK 1
RFBt

:"T'·
Cel

Vn

RL1

-= 4.7k

RS1

4.7k

-=

Rs.

:'!-'.

4.7k

cO2

v,.

RL2

-= 4.7k

140k
FEEDBACK 2
R202

R201

8.2

9.1k

C201

lO_F

+
+

C202

~1OOO_F

v+

Figure 1. Test Circuit for Noise Measurement

I--'

-20

•

-~

1/
I

-80

-100

o

Figure 2. Muting Depth as a Function of Control Voltage at Pin 2

November 6, 1986

7-177

Signetics Linear Products

Product Specification

TDA1522

Stereo Cassette Preamplifier

20

'00

I'

II

i'

'0

Rs=10k

r-.

III
Sk

r-.

r-.

=jJ-.o

10

-20

•'0

.02

.0'

.0'

r

0.'

10'

1-L...L.ULlllll:~u..ul!JL..L.I..llllJlLLU.I.illII

10

1()2

FREQUENCY (Hz)

103

104

-30
'0

105

.02

.0'

Figure 3. Noise Input Voltage as a
Function of Frequency

Figure 4. Noise Input Current as a
Function of Frequency

R102

8.,

.0'

Figure 5. Frequency Response Curve
for the Circuit in Block Diagram

C101
22nF

R.01
5.6k

TDA1522
FEEDBACK 1
RFB1

CCt

:F
"OUTPUT'
r - VOl
RL1
-::- 4.7k

Ce2

F OUTPUT, VO,
:O"rR"
-::- 4.7k

+

' 33Mn).

December 2, 1986

7-182

V
V
p.A
p.A

Signetics Linear Products

Product Specification

TDA1029

Stereo Audio Switch

SWITCH CONTROL
SWITCHED·ON
INPUTS

CONTROL VOLTAGES
INTERCONNECTED PINS

V II - 16

V12-16

V13-16

11·1
11-2
11-3
11-4

1 -15, 5 - 9
2-15,6-9
3-15,7-9
4-15,8-9

H
H
H
L

H
H
L
H

H

1-4,11-4
1-4, 11-4
1-4,11-4
1-3,11-3

4-15,8-9
4-15,8-9
4-15,8-9
3-15,7-9

L
L
L
H

L
H
L
L

1·1,
1·2,
1-3,
1-4,

l
H
H
H
L
L

l

NOTE:
In the case of offset control, an internal blocking circuit of the switch control ensures that not more
than one input will be switched on at a time. In that case safe switching~through is obtained at

VSL <1.5V.

APPLICATION INFORMATION Vcc=20V; TA = 25°C; Rs=47kQ; CI=O.l"F; RBIAS=470kQ; RL=4.7kQ; CL=100pF, unless
otherwise specified.
LIMITS
PARAMETER

SYMBOL

UNIT

Min
Voltage gain

Av

.:lV9-16;
.:lV1S- 16

)

Output voltage variation when switching the inputs
Total harmonic distortion
over most of signal range (see Figure 4)
VI = 5V; 1= 1kHz
VI = 5V; 1 = 20Hz to 20kHz

VO(RMS)

Output signal handling
draT = 0.1 %; 1= 1kHz (RMS value)

VN(RMS)

f = 20Hz to 20kHz (RMS value)

.:lV9-16;
.:lV1S-16

10

Noise output voltage (weighted)
f = 20Hz to 20kHz (in accordance with DIN 45405)

dB
100

0.01
0.02
0.03
5.0

Noise output voltage (unweighted)

)

Max

-15

dTOT
dTOT
draT

VN

Typ

mV

%
%
%

5.3

V

5

"V

12

"V

Amplitude response 1
VI = 5V; f = 20Hz to 20kHz; CI = 0.22"F

0.1

dB

cr

Crosstalk between a switched-on input and a non-switched-on
input; measured at the output at f = 1kHz2

75

dB

cr

Crosstalk between switched-on inputs and the outputs 01 the
other channels2

90

dB

NOTES:
1. The lower cut-off frequency depends on values of RSIAS and C 1•
2. Depends on external circuitry and Rs. The value will be fixed mostly by capacitive crosstalk of the external components.

December 2, 1986

7·183

Signetics Linear Products

Product Specification

TDA1029

Stereo Audio Switch

j

z.. =IM21/1OOpF

0.6

I----j--+---''-t---I-..:-.--R-d
\.

0.4

t--i--j--j--+--t-t---lI

--z..
......

=4.7k21/100p~......

'1

0.2

1

I"\.'

r-

r-

o L...:.±;.:...::::;
.•..:..:3;
•• ''::'::::=::::i:E'':';;'''=:'''±'..:::
....::±
...:=.

'::::1"

10

10'

10

10'
I (Hz)

o

I (Hz)

NOTES:

- - f=1kHz
.......... f = 20kHz

Figure 1. Equivalent Input
Noise Current

30

Figure 3. Total Harmonic Distortion as
a Function of RMS Output Voltage

Figure 2. Equivalent Input
Noise Voltage

1=I~HZ

f--- dror =1%

/AX

RL =00
20

/

~

~

./'

,/

:::'
10

L
o I..-5

--

-I-

..!MS

15

-_

...

---

1-'--

/"

VV

--

MIN
25

1
1

10

Vee (V)

NOTES:
Av ... 1dB; f = 20Hz to 20kHz

- - VN (output)

Figure 4. Output Voltage as a Function
of Supply Voltage

December 2, 1986

- - - - VN (Rs)·

Figure 5. Noise Output Voltage as a Function of Input Resistance

7-184

Signetics Linear Products

Product Specification

TDA1029

Stereo Audio Switch

Input Protection Circuit and Indication

Unused Signal Inputs
Any unused inputs must be connected to a
DC (bias) voltage, which is within the DC input
voltage range; e.g., unused inputs can be
connected directly to Pin 10.

Vee
TDA_

v,

Circuits With Standby Operation

0-...,.,1,--+---+-1

The control inputs (Pins 11, 12 and 13) are
high-ohmic at VSH .;; 20V(ISH';; 1/lA, as well
as when the supply voltage (Pin 14) is
switched off.

+

«OSV) O--,--

Z2

Z2

Co

V'tR~o-;+
Z3

Z3

12

17

13

18

Co

+ I---l:I:)B
Z3

Z4

Z4

TDA1074A

NOTES,
IC1 (at Pin 9) and 102 (at Pin 10) are control input currents; VC1 (at Pin 9) and VC2 (at Pin 10) are control input voltages with respect to VREF = VCCI2 at Pin 8; Zl "" Z2 "" Z3 "" Z4'" 22k!l;
the input generator resistance RG >= eon; the output load resistance RL == 4.7k.Q; the coupling capacitors at the inputs and outputs are CI'" 2.2p.F and Co = 10p.F, respectively.

December 2. 1986

7-190

Product Specification

Signetics Linear Products

TDA1074A

DC-Controlled Dual Potentiometer Circuit

ABSOLUTE MAXIMUM RATINGS
SYMBOL

Vee

RATING

UNIT

Supply voltage (Pin 11)

PARAMETER

23

V

Control voltages (Pins 9 and 10)

1

V

Input voltage ranges (with respect to Pin
18) at Pins 3, 4, 5, 6, 13, 14, 15, 16

VI

o to

V

Vcc

PTOT

Total power dissipation

800

mW

TSTG

Storage temperature range

-65 to +150

°C

TA

Operating ambient temperature range

-30 to +80

°C

8CRA

Thermal resistance Irom crystal to ambient

80

°C/W

APPLICATION INFORMATION
Treble and Bass Control Circuit

VCC = 20V; T A = 25°C; measured in Figure 1; RG = 60n; RL
unless otherwise specilied.

> 4.7kn; CL < 30pF; I = 1kHz; with a linear Irequency response (VC1

= VC2 = OV),

LIMITS
SYMBOL

UNIT

PARAMETER
Min

Typ

22

Max

Icc

Supply current (without load)

14

I

Frequency response (-ldB) VC1 = VC2 = OV

10

Av'

Voltage gain at linear Irequency response (VC1 = VC2 = OV)

0

dB

flAv'

Gain variation at I = 1kHz at maximum bass/treble boost or
cut at ±VC1 = ±VC2 = 120mV

±1

dB

Bass boost at 40Hz (rei. 1kHz) VC2 = 120mV

17.5

dB

Bass cut at 40Hz (rei. 1kHz) -VC2 = 120mV

17.5

dB

Treble boost at 16kHz (rei. 1kHz) VC1 = 120mV

16

dB

Treble cut at 16kHz (rei. 1kHz) -VC1 = 120mV

16

dB

0.002
0.005

%
%

THO
THO

Total harmonic distortion at VO(RMS) = 300mV
I = 1kHz (measured selectively)
I = 20Hz to 20kHz
at VO(RMS) = 5V
I = 1kHz
I = 20Hz to 20kHz

VI, VO(RMS)

Signal level at THO = 0.7% (input and output)

BW

Power bandwidth at relerence level VO(RMS) = 5V (-3dB);
THO = 0.1%

THO
THO

0.015
0.05
5.5

30
20,000

0.1
0.1

mA
Hz

%
%

6.2

V

40

kHz

VNO(RMS)
VNO(M)

Output noise voltages
(signal plus noise (RMS value); I = 20Hz to 20kHz
noise (peak value); weighted to DIN 45405; CCITT lilter

75
160

o:CT
o:CT

Crosstalk attenuation (stereo)
I = 1kHz
I = 20Hz to 20kHz

86
80

dB
dB

-o:CT

Control voltage cross-talk to the outputs at I = 1kHz;
VC1(RMS) = VC2(RMS) = lmV

20

dB

0:100

Ripple rejection at 1= 100Hz; VCC(RMS)

46

dB

December 2, 1986

< 200mV

7-191

230

p.V
p.V

•

Signetics Linear Products

Product Specification

TDA1074A

DC-Controlled Dual Potentiometer Circuit

(+~~
eak

eak

lk

lk

lOOnF

y.

-:

..c-J...lOO,F

-:

-:
18

11

4.1jJ.F

+ (25V)

+ (4V)
12k

10

1A: TREBLE (LEFI)
18: TREBLE (RIGHT)

2A: BASS (LEFT)
28: BASE(RIGHT}

2.2,F

Y~..,
(

L

1.SnF

+

39k

39k

1BOk
22,F
..... Vo 2A
L

39k
INPUTS

+
1.8nF

RL;a,.4.7k

12k
33nF

2.2,P'

14

~~+

39k

15

Ol/TPUTSlO
POWER AMPUFJER

39k
39k

1BOk
12

22,F

17

+

1.SnF

12k
13

18
TDAlOl'IA

I-- VoR

R
RLOIa4.7k

33nF

12k
4.7.,F
(4V)

Figure 1. Application Diagram for Treble and Bass Control

December 2, 1986

7-192

Product Specification

Signetics Linear Products

TDA1074A

DC-Controlled Dual Potentiometer Circuit

APPLICATION INFORMATION (Continued)

II
II

20
BASS

10

~

iii

:s

"

TREBLE

"""~

.... ""

~

-10

~

--

..... 1'==

:::::,...

f-'

-20
20

10'
1(Hz)

Figure 2. Frequency Response Curves; Voltage Gain (Treble and Bass) as a Function of Frequency

20

20

.......

f-

V

10

10

V

V

iii

:s

>

:s

"

I

-10

!/
-10

/
-20

/

iii

:1

'"

V

/

II

/

1-.......

I-f-

-20

-1SO -100 -so

so

100

-1SO -100 -SO

150

so

100

1SO

VC1 (mV)

VC2 (mV)

Figure 3. Control Curve; Voltage Gain (Bass) as a
Function of the Control Voltage (VC2); f = 40Hz

Figure 4. Control Curve; Voltage Gain (Treble) as a
Function of the Control Voltage (VC1); f 16kHz

=

TDA1074A
Curve No.

Value of R

10kll
100k,Q

220kll
470kll

1MIl

(V+=2OV)

+

of; ..
1k

*lOOnF

Figure 6. Circuit Diagram for
Measuring Curves In Figure 5

Figure 5. Voltage Gain (Av = Vo/V I) Control Curves as a Function of the Angle
of Rotation (cc) of a Linear Potentiometer (R); (for Curve Numbers
see Table Above); f = 40Hz to 16kHz

December 2. 1986

7-193

II

Product Specification

Signetics Linear Products

TDA1074A

DC-Controlled Dual Potentiometer Circuit

APPLICATION INFORMATION (Continued)

,-------------------------,
0.2

f

V

/

1-

0"

,

--

REFERENCE
LEVEL

-3dB

/

_f!\I~ ....

o ........

o

o

-

~

/
V

-0.1

10

20

........

J..- .... ~

o

o

30

0.1

vee (V)

10

100

• (kHz)
NOTES:

_ _ f=1kHz
NOTES:
THD = 0.7%;

f;c 1kHz; Vel"" Ve2 "" av.

----- ••• f'" 20kHz
Vee"" 20V; RL:C 4.7kU; VC1 ;: Ve2 '" OV
(Linear AvrOT = 1)

Figure 7. Output Signal Level as a
Function of Vee

Figure 8. Total Harmonic Distortions
as a Function of the Output Level

NOTES:

Reference Level is 5V (RMS)

Figure 9. Power Bandwidth at
THD=0.1%

100

90

iI
:£
t;

80

i

70

.........

80

50
10

103
I (Hz)

NOTE:

Linear treble/bass setting (VC1 = Ve2 = OV); VI"'" 5V; RG'" 60Q; RL"" 4.7k.Q,

Figure 10. Crosstalk as a Function of Frequency

Application Recommendations
1.

a.

If one or more electronic potentiometers
in an Ie are not used, the following is
recommended:
Unused signal inputs of an electronic
potentiometer should be connected to

December 2, 1986

b.
2.

the associated output, e.g., Pins 3 and 4
to Pin 2.
Unused control voltage inputs should be
connected directly to Pin 8 (VREF).
Where more than one TDA 1074A Ie are
used in an application, Pins 1 can be
connected together; however, Pins 8

7-194

3.

4.

(VREF) may not be connected together
directly.
Additional circuitry for limiting the frequency response in the ultrasonic range
is shown in Figure 11.
Alternative circuitry for limiting the gain of
the treble control circuit in the ultrasonic
range is shown in Figure 12.

Signetics Linear Products

Product Specification

DC-Controlled Dual Potentiometer Circuit

TDA1074A

FROM PIN
7(12)

1
+

12k
4~5)

lOOk

TDA1074A

33n

2~7)

OUTPUT
120pF
NOTE 1

12k

3(18)

NOTE,
1. L3db= 110kHz at linear setting

Figure 11. Circuit Diagram for Frequency Response Limiting

TO PIN
4~5)

Yo
1.8nF

Y,o-j +
39k

I

RS1

39k

5~)

I

39k

39k

7~2)

TDA1074A

i~2

T~8nF

8(13)

I

NOTES,
For RS1 = RS2 = 3.3kn; L3dB~1MHz at linear setting
For RS1 = RS2 = On; L 3dS :2o'100kHz at linear setting

Figure 12. Circuit Diagram for Limiting Gain of Treble Control Circuit

December 2, 1986

7-195

TDA1524A

Signetics

Stereo Audio Control
Product Specification

Linear Products
DESCRIPTION

FEATURES

The device is designed as an active
stereo tone/volume control for car radios, TV receivers and audio equipment. It
includes functions for bass and treble
control, volume control with built-in contour (can be switched off) and balance.
All these functions can be controlled by
DC voltages or by single linear potentiometers. The bass and treble responses
are defined by a single capacitor per
control per channel.

• Few external components
necessary

PIN CONFIGURATION

• Low noise due to internal gain
• Bass emphasis can be increased
by a double-pole low-pass filter
• Wide power supply voltage range

VOLUME
CONTROL
17
16
INPUT(R) 4

egrT~~L
ro'itr~gi.

15 INPUT(L)

APPLICATIONS

BASS CAP (R) 5

14 BASS CAP (L)

• Hi-Fi radio
• Auto radio

BASS CAP (R) 6
TREBLE
CAP(R)
OUTPUT(R) 8

12

6'l~'t)E

10

~~';J\.'ifOL

• TV
• Audio systems

BASS
CONTROL
TOP VIEW

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDERING CODE

18·Pin Plastic DIP (SOT-102CS)

-30°C to +80°C

TDA1524AN

December 2, 1986

N Package

7-196

853-1048 86702

Signetics Linear Products

Product Specification

Stereo Audio Control

TDA1524A

BLOCK DIAGRAM AND APPLICATION CIRCUIT WITH SINGLE-POLE FILTER

left
output

RL

~

l-~-l
14

~~1;q,; 11~

-±-

[P

~15

2

4.7 K

TDA1S24A

-

+-

-(

l -I -

bass

~
CONTROLLED
AMPLIFIER

I

I

VOLUME/BALANCE
CONTROL VOLTAGE

AMPLifiER

CONVERTER

00"""'"
->-

i

JJ

volume

BASS & TREBLE

Gr

-

~

t

~~6

8

7

111

150F

TREBLE

BASS

CONTROL
VOLTAGE

CONTROL
VOLTAGE
CONVERTER

CONVERTER

[p [t>
t

J

1

18

~

,.

i

--

10

9

200

~;~
right
OUtput

4:i~
_'~~J:
K

-::-

conto

t
!

...-:

volume

NOTE:
Series resistor is recommended in the event of the capacitive loads exceeding 200 pF.

December 2, 1986

f""l100#F
+

treble

VOLUME

[P

"

3
SUPPLY

-- ~;'~~{

I
~4I-

~OF

200

12

BASS & TREBLE

VOLUME

CONTROLLED
AMPLIFIER

_t

13

v+

-=-

4.7 J.lF

7-197

4:~_

l~~I

4J t -

l~~I

treble

Vt-

l~~I

b,,,

linear

Product Specification

Signetics Linear Products

TDA1524A

Stereo Audio Control

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

Vcc = V3-18

Supply voltage

ProT

Total power dissipation

TSTG
TA

RATING

UNIT

20

V

1200

mW

Storage temperature range

-65 to + 150

°C

Operating ambient temperature range

-30 to +BO

°C

DC ELECTRICAL CHARACTERISTICS Vee = 12V; TA = 25°C; measured in Block Diagram; RG';;; 600n; RL ;;>4.7kn;
CL .;;; 200pF, unless otherwise specified.
LIMITS
SYMBOL

UNIT

PARAMETER
Min

Typ

Max

Supply (Pin 3)

Vee = V3- 16

Supply voltage

7.5

Icc = 13
ICC = 13
Icc = 13

Supply current
at Vee = B.5V
at Vee = 12V
at Vee = 15V

16.5

V

19
25
30

27
35
43

36
45
56

rnA
rnA
rnA

V4• 15-18
V4• 15-16
V4, 15-18

DC input
at Vee
at Vee
at Vee

3.B
5.3
6.5

4.25
5.9
7.3

4.7
6.6
B.2

V
V
V

DC output levels (Pins Band 11)
under all control voltage conditions
with DC feedback (Figure 2)
at Vce = B.5V
at Vce = 12V
at Vee = 15V

V8,11-18
V8,11-1B
V8,11-18

3.3
4.6
5.7

4.25
6.0
7.5

5.2
7.4
9.3

V
V
V

V17 -18

Internal potentiometer supply voltage at Vce = 8.5V

3.5

3.75

4.0

V

-117
-117

Contour on/off switch (control by 117)
contour (switch open)
linear (switch open)

1.5

0.5
10

rnA
rnA

levels (Pins 4 and 15)
= B.5V
= 12V
= 15V

Pin 17

Application without internal potentiometer
supply voltage at Vee ;;>1O.BV
(contour cannot be switched off)
V17 -18

Voltage range forced to Pin 17

4.5

Vee/2- VBE

V

V1, 9, 10. 16
V1, 9. 10, 16

DC control voltage range for volume,
bass, treble and balance
(Pins I, 9, 10 and 16, respectively)
at V17-18=5V
using internal supply

1.0
0.25

4.25
3.8

V
V

-11,9,10, 16

Input current of control inputs (Pins 1, 9, 10 and 16)

5

p.A

December 2, 1986

7-198

Signeties Linear Products

Product Specification

TDA1524A

Stereo Audio Control

AC ELECTRICAL CHARACTERISTICS Vee=V3_1s=8.5V; TA=25'C; measured in Block Diagram; contour switch closed
(linear position); volume, balance, bass, and treble controls in mid-position;
RG .;; 600n; RL ;;;' 4.7kn; CL .;; 200pF; I = 1kHz, unless otherwise specilied.
LIMITS
SYMBOL

PARAMETER

UNIT
Min

Typ

Max

20.5

21.5

23

90

100

dB

-40

dB

Control range

Av MAX

Maximum gain 01 volume (Figure 4)

!lAy

Volume control range; Av MAXI Ay MIN

!lAy

Balance control range; Ay = OdB (Figure 5)

!lAy

Bass control range at 40Hz (Figure 6)

±12

±15

dB

!lAy

Treble control range at 16kHz (Figure 7)

±12

±15

dB

Contour characteristics

dB

see Figures 8 and 9

Signal Inputs, outputs

R14.15
RI4,15

Input resistance; Pins 4 and 151
at gain 01 volume control: Av = 20dB
Ay =-40dB

R08,ll

Output resistance (Pins 8 and 11)

10

kn
kn

160
300

n

Signal processing

PSRR

Power supply ripple rejection
at VeC(RMS)';; 200 mY; 1= 100Hz; Ay = OdB

35

50

dB



"

-10

-

--

...... ~

~

II-"
-20
10

10"

e::::
,r--

t-:::
~

10"

I (Hz)
NOTES:
With single-pole filter; Vee = B.5V.
See Block Diagram

Figure 10. Tone Control Frequency Response Curves; Voltage Gain (Av)
as a Function of Audio Input Frequency
December 2, 1986

7-202

Signetics Linear Products

Product Specification

Stereo Audio Control

TDA1524A

3SO
20

......
...... ~
......

-

..

V

-

~

"

S

-40

"e;.

i'--

:::

1SO
100

so

10'

10

200

0

;::

/

-

2SO

3
iii

~

-20

300

2
3

-60

!(Hz)

1/
I--"V
1/

1

-40

-20

20

40

60

Gv(dB)

NOTES:
With double*pole filter; Vee = 8.5V.
See Block Diagram

Figure 11. Tone Control Frequency Response Curves; Voltage Gain (Av)
as a Function of Audio Input Frequency

NOTES:
1. Vee == 15V.

2. Vee == 12V.
3. Vee = 8.5V.
f = 20Hz to 20kHz.
See Block Diagram

Figure 14. Noise Output Voltage
(VNO(RMS); Unweighted); as a Function
of Voltage Gain (Av)
0.4

to

VI =

~

I--

0.2

>- F::i<:

r-:::::

;::>'"

o

0.2V
0.5V

,

1.oV
1.4V

10'

10

!(Hz)
NOTES:
Vee == 8.SV ....olume control voltage gain at

Vo

Ay=20 log -=OdS.
V,

II

See Block Diagram

Figure 12. Total Harmonic Distortion (THO); as a Function
of Audio Input Frequency

0.41------+-----+------+------1

#

"

~ 02~--~~----~~-------4~~~~--_+~-~----~

OL-______

o

~

M

________

~

_________ J_ _ _ _ _ _ _ _

U

~

~

U

Vo(V)
NOTES:
Vee"" 8.5V; fl = 1kHz.
See Block Diagram

Figure 13. Total Harmonic Distortion (THO) as a Function
of Output Voltage (Vo)

December 2, 1986

7-203

TDA3810

Signetics

Spatial, Stereo, Pseudo-Stereo
Processor
Product Specification

Linear Products

PIN CONFIGURATION

DESCRIPTION

FEATURES

The TDA3810 is an integrated circuit
which can provide three switched functions for radio and television equipment:
spatial sound from a stereo source,
stereo sound from a stereo source,
pseudo-stereo sound from a mono
source.

• Three switched functions:
- Spatial
- Stereo
- Pseudo-stereo
• Muting circuit prevents LED
flickering
• LED driving outputs (Pins 7 and 8)
• TIL compatible inputs for
selecting operating mode

APPLICATIONS
• Radio
• Television
• Audio systems

N Package
VREF

1

18 Voo

LEFT
CHANIN
LEFT CHAN
BUFFER OUT
LEFT CHAN

17

~~,m'N

16

:L(W1~~t~

15 ~~~~,m~N

SPATIALFB

LEFT CHAN
PSEUDO FB
LEFT
CHAN OUT
SPATIAL
INDDRIVER
PSEUDO
INDDRIVER

14
13

~~~~1g~~
~~A~OUT

TOP VIEW

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

-20'C to + 70'C

TDA381ON

18-Pin Plastic DIP

ABSOLUTE MAXIMUM RATINGS
PARAMETER

SYMBOL

RATING

UNIT

Vcc

Supply voltage (Pin 18)

18

V

Icc

Supply current (Pin 18)

12

mA
'C

T5TG

Storage temperature range

-65 to + 150

TA

Operating ambient temperature range

-20 to +70

'C

OCRA

Thermal resistance from crystal to ambient

80

'C/W

TRUTH TABLE

Pin 11

Pin 12

LED
SPATIAL
Pin 7

HIGH
HIGH
LOW

LOW
HIGH
X

Off
On
Off

CONTROL INPUT STATE
MODE
Mono pseudo-stereo
Spatial stereo
Stereo

LED
PSEUDO
Pin 8
On
Off
Off

NOTES:
LOW = 0 to O.8V (the less positive voltage)
HIGH= 2V to Vee (the more positive voltage)
= state is don't care

X

November 14, 1986

7-204

853-0975 86556

Signetics Linear Products

Product Specification

TDA3810

Spatial, Stereo, Pseudo-Stereo Processor

BLOCK DIAGRAM
Pi" 6
20K
(1)

r-

15K

Pin 6

Vee
18

3.9nF .L

T

10K

L_
LEFT
OUTPUT

+

f-o

4.7,uF

r
Vs

10K

MUTE

1

100 +
_F
.471'F

+

":"

RIGHT
OUTPUT
13

15

(1)
3.9nF

4•7_F

+

f-o

4.7~F

r..L

T

L

10K

Pin 13

16K
SPATIAL
":"

ft-

11K

J

PSEUDO
";"

Pi" 13

22K
20K

22K

16K

18K

~22nF

NOTE:
1. Recommended in spatial mode for correction of high frequency (optimal performance).

November 14, 1986

":"

lOOK

7-205

1-0 Pin 6
10nF

•

I
I

Signetics Linear Products

Product Specification

TDA3810

Spatial, Stereo, Pseudo-Stereo Processor

DC ELECTRICAL CHARACTERISTICS vcc = 12V; TA = 25°C; Test circuit Figure 1 stereo mode (Pin 11 to ground), unless
otherwise specified.
LIMITS
SYMBOL

PARAMETER

TEST CONDITIONS

UNIT
Typ

Min
Vcc

Supply voltage range

Icc

Supply current

Vs

Reference voltage

VI(RMS)

Input voltage

RI

Input resistance

4.5

Pin 18

5.3
Pin 2 or 17, THO

Av

Voltage gain VOIVI
Channel separation (R/L)

THO

Total harmonic distortion

RR

Power supply ripple rejection

VN(RMS)

Noise output voltage

f

= 40

16.5

V

6

12

rnA

6

6.7

V

= 0.2%

2

Pin 2 or 17

cc

Max

to 16000Hz; VO(RMS)

V

50

75

kfl

0

dB

60

70

dB

= 1V

(Unweighted) left and right output

0.1

%

50

dB

10

MV

Spatial mode (Pins 11 and 12 HIGH)
cc

Antiphase crosstalk

Av

Voltage gain

%

50
1.4

2.4

dB

3.4

PSEUDO-STEREO MODE
SYMBOL

I

PARAMETER

I

TEST CONDITIONS

LIMITS
I
I
I Min I TyplMaxl

UNIT

Control inputs (Pins 11 and 12)
RI
-II

II nput resistance

JSwitching current

I

I

I

I

70

kfl

I

120 I

j

35

I 100 I

J1A

I

12

I

15

I

rnA

I

6

I

V

I

LED drivers (Pins 7 and 8)

-10

I Output current for LED

I

I

VF

I Forward voltage

I

I

NOTE:

1. The quality and strength of the

November 14, 1986

pseudo~stereo

effect is determined by external filter components.

7-206

10

I

Signetics Linear Products

Product Specification

Spatial, Stereo, Pseudo-Stereo Processor

TDA3810

r

'0

-

~
~

;'"

,-"

z -'0

:c
~
~

/

-20

BANDPASS FILTER

!

-30

'"

I I

'0'

:\V
\

If

MONO

i'-.. . .

\.LrEAR CHANiEL

I

PSE~'

I!

I

DOUBLM.FILTER

'0'

'04

'03

'02

FILTER CHtNEL PSEUDO

I(Hz)

Vcc= ... 12V
.47,.F

'OK

'2K

,.
MONO
INPUT

LEFT
OUTPUT
4.7,.F

0---1 1---.----::+.....,....,
O.1/-1F

+

f-o

>SOK

47j.4F
MUTE

VS/2

STEREO

+~
100/oiF

+~

.---!'-.....,
'0

>SDK

4.7J.(f
13

,7
'2
SPATIAl!
PSEUDO

'o~nF

16K

SPATIAL

100K

l"K

22K

-

24K

22K

Figure 1. Pseudo Filter I

November 14, 1986

7-207

PSEUDO

+,

f-o

RIGHT
OUTPUT

•

Signetlcs Linear Products

Product Specification

TDA3810

Spatial, Stereo, Pseudo-Stereo Processor

10

,fiLTER

~?

I"""'"

/

V

"

BANjASS FrEi
-30
101

~~TtR

~

V

\

lHNELPSEUDOl

PSEUDO

........ r--.,

!I

............

V

DOUBLe,.T·FILTER

103

102

105

I(Hz)

UnF

(1)

r-lf--,
10K

Vcc= +12V

33K

33K

18

LEFT
INPUT

LEFT

<>--j I-+--=-......-l

OUTPUT
4.7;.1F

O.1;.1F

+f-o
>50K
MUTe

9

VSf2

47/-/F

+~
1oo.uF

+~

STEREO ...----""-......
10
>50K

4.7,uF

13

RIGHT
INPUT

RIGHT
OUTPUT

<>--j Hf--:,""7.......~
0.1,101F
12
18K

l"K

22K

SPATIAL!
PSEUDO

.47/1F

10~nF

16K

82K

20K

22K

10K

Figure 2. Pseudo Filter II

November 14, 1966

""

+\-0

7-208

Signetics Linear Products

Product Specification

TDA3810

Spatial, Stereo, Pseudo-Stereo Processor

'0

Ir!IL ER HANNEL PSEUDO

......

.........

y~

/

r"\

BANiASS FifER

IIV

...........

\ I
IV

!r- LINEAR CHANNEL PSEUDO
MONO

~~

"---

DOUBLE-T-FILTER

-30
10'

102

,04

'03

'05

!(Hz)

3.IInF (1)

r-1l-i
,OK

Vcc= .'2V
15K

20K
0.22"FJ;:

18

LEFT
INPUT

LEFT
OUTPUT
4.7",F

o-j 1-+--:-.......-1

O.'_F

+

f-o

>SOK
MUTE

VSi2

":"

47jJF

+~
'OO_F

+~

'0

-=-

>5OK
4.7j.1F

13

RIGHT
OUTPUT

RIGHT
INPUT

o-j r-1-:''""7t-~
o.'_F
'2

16K

l"K

UK

-

SPATIAU
PSEUDO

.47;.F

IS!;-PsnF

'8K

'OOK

":"

":"

SPATIAL

PSEUDO

20K

UK

10K

Figure 3. Pseudo Filter III

November 14, 1986

+f-o

7-209

TDA8440

Signetics

Video and Audio Switch

Ie

Product Specification

Linear Products

DESCRIPTION

FEATURES

The TDA8440 is a versatile video/audio
switch, intended to be used in applications equipped with video/audio inputs.

• Combined analog and digital
circuitry gives maximum flexibility
in channel switching
• 3-State switches for all channels
• Selectable gain for the video
channels
• Sub-addressing facility
• 12C bus or non-1 2C bus mode
(controlled by DC voltages)
• Slave receiver in the 12C bus
mode
• External OFF command
• System expansion possible up to
7 devices (14 sources)
• Static short-circuit proof outputs

It provides two 3-State switches for audio channels and one 3-State switch for
the video channel and a video amplifier
with selectable gain (times 1 or times 2).
The integrated circuit can be controlled
via a bidirectional 12C bus or it can be
controlled directly by DC switching signals. Sufficient sub-addressing is provided for the 12C bus mode.

PIN CONFIGURATION

N Package
VIDEOIlIN 1
OFF
FUNCTION IN
VIDEO IINPUT 3

AUDIOI.IN

5

AUDIOII.IN 7
BYPASS

8

AUDIO lAIN 9

L--_---'
lOP VIEW

APPLICATIONS
• TVRO
• Video and audio switching
• Television
• CATV

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

o to 70·C

TDA8440N

18-Pin Plastic DIP (SOT-l02)

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

RATING

UNIT

14

V

Vec

Supply voltage Pin 15

VSDA
VseL
VOFF
Vso
VS1
VS2

Input
Pin
Pin
Pin
Pin
Pin
Pin

-1 16

Video output current Pin 16

50

rnA

TSTG

Storage temperature range

-65 to + 150

·C

TA

Operating ambient temperature range

TJ

Junction temperature

I)JA

Thermal resistance from junction to
ambient in free-air

February 12, 1987

voltage
17
18
2
11
13
6

-0.3
-0.3
-0.3
-0.3
-0.3
-0.3

to
to
to
to
to
to

Vee
Vee
Vee
Vee
Vee
Vee

o to

+ 0.3
+ 0.3
+0.3
+0.3
+0.3
+0.3

+70

V
V
V
V
V
V

·C

+150

·C

50

·C/W

7-210

853-1172 87583

Product Specification

Signetics Linear Products

Video and Audio Switch

Ie

TDA8440

BLOCK DIAGRAM AND TEST CIRCUIT

rl-:-+--I--I
1k

AUDIOI,

AUDIO ".

VIDEOI

+

1k

11
~---So

O.47 /AF

14

O.41J.1f

-=-

75

100nF

TAUDIOBOUT

1k
13

I-----s,

r~-I--I

16

"'e--If-----.,-...

rl--+--I
"':'"

10j.4F

+

rl--:-+-+--I
1k

75

AUDlOAOUT

fk

O.47~F 10

":"

"::'"

VIDEO II

1k

r--r

12 10l'F

rl-:-+-+--I
-=-

AUDIOI.

9

rl--:-+-+--I
":'

AUDIOII,

O.47"F

VIDEO OUT

100nF

1101F

J..'-----II

1-=-----50

+

17
18

OFF

SOA

}

I'CBUS

L...;~~.J--T-- SCL
15

I----t-'------

Vee

NOTE:
so, 81, 52, and OFF (Pins 11, 13, 6, and 2) connected to Vee or GNO. If more than 1 device is used, the outputs and Pin 8 (bias decoupling of the audio inputs) may be connected in
parallel.

February 12, 1987

7-211

•

I

Signetics Linear Products

Product Specification

Video and Audio Switch

Ie

TDA8440

DC ELECTRICAL CHARACTERISTICS TA = 25°C; Vee = 12V, unless otherwise specified.
LIMITS
SYMBOL

UNIT

PARAMETER
Min

Typ

Max

Supply

V,5-4

Supply voltage

1'5

Supply current (without load)

10

13.2

V

37

50

mA

Video switch

C,C3

Input coupling capacitor

100

A3-'S
A3_'S

Voltage gain (times 1; SCL = L)
(times 2; SCL = H)

-1
+5

0
+6

+1
+7

dB
dB

nF

A,_,s
A,_,s

Voltage gain (times 1; SCL = L)
(times 2; SCL = H)

-1
+5

0
+6

+1
+7

dB
dB

V3-4

Input video signal amplitude (gain times 1)

4.5

V

V'_4

Input video signal amplitude (gain times 1)

4.5

Z,6_4

Output impedance

Z,6_4

Output impedance in 'OFF' state

7

Isolation (off-state) (fo

= 5MHz)

V
S1

100

kS1

60

dB

SIS + N

Signal-to-noise ratio 2

60

V,6_4

Output top-sync level

2.4

G

Differential gain

V'6_4

Minimum crosstalk attenuation 1

60

RR

Supply voltage rejection 3

36

dB

BW

Bandwidth (ldB)

10

MHz

cc

Crosstalk attenuation for interference caused by bus signals
(source impedance 75S1)

60

db

dB
2.8

3.2

V

3

%
dB

Audio switch IIA" and liB"

V9_4 (RMS)
V,O-4 (RMS)
V5-4 (RMS)
V7_4 (RMS)
Z9_4
Z1O-4
Z5_4
Z7_4

2
2
2
2

Input signal level
50
50
50
50

Input impedance

Output impedance

Z'4-4

Output impedance (off-state)

100
-1
-1
-1
-1

V9_'2
V'O_'2
V5-'4
V7_'4

Voltage gain

SIS + N

Signal-to-noise ratio4

THO

Total harmonic distortionS

February 12, 1987

kS1
kS1
kS1
kS1
10
10

Z'2_4
Z,4-4

Isolation (off-state) (f

100
100
100
100

= 20kHz)

S1
S1
kS1

0
0
0
0

+1
+1
+1
+1

90

dB
dB
dB
dB
dB

90

dB
0.1

7-212

V
V
V
V

%

Signetics linear Products

Product Specification

Video and Audio Switch

Ie

TDA8440

DC ELECTRICAL CHARACTERISTICS (Continued) TA = 25"C; Vec = 12V, unless otherwise specified.
LIMITS
SYMBOL

UNIT

PARAMETER
Min
Crosstalk attenuation for interferences
caused by video signals5
Weighted
Unweighted

a:
a:

Typ

Max

80
80

dB
dB

Crosstalk attenuation for interferences caused by sinusoidal
sound signals 5

80

dB

Crosstalk attenuation for interferences caused by the bus
signal (weighted) (source impedance = 1kn)

80

dB

RR

Supply voltage rejection

50

dB

BW

Bandwidth (-1 dB)

50

kHz

a:

12C bus Inputs/outputs SOA (Pin 17) and SCl (Pin 18)
VIH

Input voltage HIGH

3

Vcc

V

VIL

Input voltage lOW

-0.3

+ 1.5

V

IIH

Input current HIGH 7

10

p.A

IlL

Input current lOW7

10

p.A

VOL

Output voltage LOW at IOL = 3mA

0.4

IOL

Maximum output sink current

CI

Capacitance of SOA and SCl inputs, Pins 17 and 18

V
mA

5
10

pF

V

Sub-address Inputs So (Pin 11), S, (Pin 13), S2 (Pin 6)
VIH

Input voltage HIGH

3

Vee

VIL

Input voltage lOW

-0.3

+0.4

V

IIH

Input current HIGH

10

p.A

IlL

Input current lOW

-50

0

p.A

V

OFF input (Pin 2)
VIH

Input voltage HIGH

+3

Vee

VIL

Input voltage lOW

-0.3

+0.4

V

IIH

Input current HIGH

20

p.A

IlL

Input current lOW

2

p.A

-10

NOTES:
1. Caused by drive on any other input at maximum level, measured in B = 5MHz, source impedance for the used input 75n,
VOUT
crosstalk = 2010g - - - .
VIN

2. SIN

= 2010g

max

Vo video noise (P - PI (2V).
Vo noise RMS B = 5MHz

3. Supply voltage ripple rejection
4. SIN

= 2010g

= 2010g

Vo nominal (0.5V)
Vo noise B = 20kHz

VA supply
VA on output

at I

= max.

'OOkHz.

.

5. Caused by drive of any other input at maximum level, measured in 8 == 20kHz, source impedance of the used input = 1kn,
crosstalk

= 2010g

VOUT

- - - according to DIN 45405 (CCIR 468).
VIN max

6. I = 20Hz to 20kHz.
7. Also il the supply is switched off.

February 12, 1987

7-213

I

II
,

Signetics linear Products

Product Specification

Ie

Video and ·Audio Switch

TDA8440

AC ELECTRICAL CHARACTERISTICS 12C bus load conditions are as follows: 4k!1 pull-up resistor to +5V; 200pF to GND.
All values are referred to VIH = 3V and VIL = t.5V.
LIMITS
SYMBOL

UNIT

PARAMETER
Min

Max

tBUF

Bus free before start

4

j.lS

ts

(STA)

Start condition setup time

4

JJS

tH

(STA)

Start condition hold time

4

j.lS

tLOW

SCl. SDA lOW period

4

JJS

tHIGH

SCl. HIGH period

4

tR

SCl. SDA rise time

1

JJS

tF

SCl. SDA fall time

0.3

JJS

JJS

ts

(OAT)

Data setup time (write)

1

tH

(OAT)

Data hold time (write)

1

ts

(CAC)

Acknowledge (from TDA8440) setup time

tH

(CAC)

Acknowledge (from TDA8440) hold time

0

j.lS

ts

(STO)

Stop condition setup time

4

j.ls

Table 1. Sub-Addressing
SUB-ADDRESS
S2

Typ

S,

So

l
l
l
l
H
H
H

l
l
H
H
l
l
H

l
H
l
H
l
H
l

H

H

H

A2

A,

Ao

0
0
0
0
1
1
1

0
0
1
1
0
0
1

0
1
0
1
0
1
0

non 12C
addressable

FUNCTIONAL DESCRIPTION
The TOA8440 is a monolithic system of
switches and can be used in CTV receivers
equipped with an auxiliary video/audio plug.
The IC incorporates 3-State switches which
comprise:
a) An electronic video switch with selectable
gain (times 1 or times 2) for switching
between an internal video signal (from the
IF amplifier) with an auxiliary input signal.

February 12. 1987

j.lS
j.ls
2

b) Two electronic audio switches. for two
sound channels (stereo or dual language).
for switching between internal audio
sources and signals from the auxiliary video/audio plug.
A selection can be made between two input
signals and an OFF-state. The OFF-state is
necessary if more than one TOA8440 device
is used.
The SOA and SCl pins can be connected to
the 12C bus or to DC switching voltages.
Inputs So (Pin 11). S, (Pin 13). and S2 (Pin 6)
are used for selection of sub-addresses or
switching to the non-1 2C mode. Inputs So. S,.
and S2 can be connected to the supply
voltage (H) or to ground (l). In this way. no
peripheral components are required for selection.

NON-1 2C BUS CONTROL
If the TDA8440 switching device has to be
operated via the auxiliary video/audio plug.
inputs S2. S,. and So must be connected to
the supply line (12V).

7-214

j.ls

The sources (internal and external) and the
gain of the video amplifier can be selected via
the SOA and SCl pins with the switching
voltage from the auxiliary video/audio plug:
• Sources I are selected if SOA = 12V
(external source)
• Sources II are selected if SOA = OV (TV
mode)
• Video amplifier gain is 2 X if SCl = 12V
(external source)
• Video amplifier gain is 1
(TV mode)

x

if SCl

= OV

If more than one TDA8440 device is used in
the non-1 2C bus system. the OFF pin can be
used to switch off the desired devices. This
can be done via the 12V switching voltage on
the plug.
• All switches are in the OFF position if
OFF = H (12V)
• All switches are in the selected position
via SDA and SCl pins if OFF = l (OV)

12C BUS CONTROL
Detailed information on the 12C bus is available on request.

Product Specification

Signetics Linear Products

Ie

Video and Audio Switch

TDA8440

Table 2_ TDA8440 12C Bus Protocol
Do

= start

:

~

AC

STO

condition

1 Fixed

address bits

=1

sub-address bit, fixed via S2 input
sub-address bit, fixed via S1 input
= sub-address bit, fixed via So input
= read/write bit (has to be 0, only write mode allowed)
= acknowledge bit (= 0) generated by the TDA8440
= 1 audio I. is selected to audio output a
= 0 audio I. is not selected
= 1 audio II. is selected to audio output a
= 0 audio II. is not selected
= 1 audio Ib is selected to audio output b
= 0 audio Ib output is not selected
= 1 audio lib is selected to audio output b
= 0 audio lib is not selected
= 1 video I is selected to video output
= 0 video I is not selected
= 1 video II is selected to video output
= 0 video II is not selected
= 1 video amplifier gain is times 2
= 0 video amplifier gain is times 1
= 1 OFF-input inactive
= 0 OFF-input active
= stop condition
=
=

Do/OFF Gating
OFF input

DO

o (off

input active)

0

H
L

1 (off input inactive)
1

H
L

OFF FUNCTION
With the OFF input all outputs can be
switched off (high-ohmic mode), depending
on the value of Do.

Power-on Reset
The circuit is provided with a power-on reset
function.

Outputs
OFF
In accordance with last defined
D7 - D1 (may be entered while
OFF = HIGH)
In accordance with D7 - D1
In accordance with D7 - D1
When the power supply is switched on, an
internal pulse will be generated that will reset
the internal memory So. In the initial state all
the switches will be in the off position and the
OFF input is active (D7 - Do = 0), (1 2C mode).
In the non-1 2C mode, positions are defined via
SDA and SCL input voltages.

SDA
(WRITE)

SCL

Figure 1. ,2C Bus Timing Diagram
February 12, 1987

7·215

When the power supply decreases below 5V,
a pulse will be generated and the internal
memory will be reset. The behavior of the
switches will be the same as described
above.

II

TEA6300

Signetics

Digitally-Controlled Tone,
Volume, and Fader Control
Circuit
Linear Products

Preliminary Specification
PIN CONFIGURATION

DESCRIPTION

FEATURES

The TEA6300 is a single-chip l2C buscontrolled tone, volume, loudness, and
fader control circuit ideal for audio signal
processing in an automotive entertainment environment. The TEA6300 provides three stereo source input selector
switching, volume, loudness, tone, and
fader (front/rear) controls. The active
tone control functions are determined by
two capacitors along with on-chip op
amps which keep external component
counts to a minimum.

• Source selector for three stereo
inputs
• Low noise and distortion
• Volume and balance control;
Control range of 86dB in 2dB
steps
• Bass and treble control from
+ 15dB (treble + 12dB) to -12dB
in 3dB steps
• Fader control from OdB to -30dB
in 2dB steps

N Package

BR1
BAO
INRA

• Fast muting
• Low noise suitable for DOLBY®

INLB

NR

ELFI

• Signal handling suitable for
compact disc
• Pop-free onloff switching
• 28-pin package

INLC
QSL
INL
TOP VIEW

APPLICATIONS

00133408

PIN NO.
1
2
3
4
5

• Auto radio
• Audio systems
• TV

• Remote control audio systems

SYMBOL
SDA
GNDB
aLR
aLF
Tl
Bl1
BlO

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

28-Pin Plastic DIP (SOT-117BE)

-40°C to + 85°C

TEA6300N

8

9

INLA
IC

Vee

Supply voltage (Pins 27 - 18)

16

V

PTOT

Maximum power dissipation

2

W

10
11
12
13
14
15
16
17
18
19
20
21
22

TSTG

Storage temperature range

-55 to + 150

°C

23

BR1

TA

Operating ambient temperature range

-40 to +85

°C

24

TR

25

aRF
aRR

ABSOLUTE MAXIMUM RATINGS
PARAMETER

SYMBOL

RATING

UNIT

26
27
28

February 1987

7-216

INLB
ElFI
INLC
aSL
INl
INR
aSR
INRC
GND
INRB
VREF
INRA
BRO

Vee
SCl

DESCRIPTION
Data input/output
Ground for BUS terminals
Output left rear
Output left front
Termination for treble control
capacitor left channel
Termination for bass control
capacitor left channel
Termination for bass control
capacitor left channel
Input left source A
Internal connected
Input left source B
Electronic filtering for supply
Input left source C
Output source selector left
Input left control part
Input right control part
Output source selector right
Input right source C
Ground
Input right source B
Reference voltage (Y2 Vce)
Input right source A
Termination for bass control
capacitor right channel
Termination for bass control
capacitor right channel
Termination for treble control
capacitor right channel
Output right front
Output right rear
Supply voltage
Clock input

Signetics Linear Products

Preliminary Specification

Digitally-Controlled Tone, Volume, and Fader Control Circuit

TEA6300

BLOCK DIAGRAM

OSl INl

IC

BlO

Bll

TL

13

8

7

8

5

14

TEA8300

2.2"F

4.7~F

(h)

INCA

'e--r>--l-oF-+:-I1--o 0LF

o--f 1-::+:-+.,

INLBo--;

+

4.7_F

....--[>--t--F'"""":+::-II--o O'R

IN,c 0--; 1-:+--"=+-...1
INRA

o---i I-:+--=+--.

INRBO--;
INRC

Vee

+

o--t 1-:+""":''"1-...1

()---..,-----t
27

VREF()--...~.:;:20+---_-t

28

1 2

22

23

BRO

BRI

24
TR

---

SCl GNDB
SDA
I'CBUS

II

February 1987

7·217

Preliminary Specification

Signetics Linear Products

Digitally-Controlled Tone, Volume, and Fader Control Circuit

FUNCTIONAL DESCRIPTION
The input selector selects three stereo channels, e.g., RF part (AM/FM), recorder and
compact disk. As the outputs of the source
selector as well as the inputs of the main
control part are available, additional circuits
like compander- and equalizer systems may
be inserted into the signal path. The AC
signal setting is performed by resistor chains
in combination with multi-input operational
amplifiers. The advantage of this principle is

the combination of low noise, low distortion,
and a high dynamic range for the circuit.
The separated volume controls of the left and
the right channel make the balance control
possible. The range and the characteristic of
the balance is software-programmable by
setting an extra bass (and optional treble)
control, depending on the actual volume position, the loudness function, performed by
software in a microcomputer controlling both
the switching points and the ranges. Because
the TEA6300 has four outputs, a low-level

DC ELECTRICAL CHARACTERISTICS

SYMBOL

Vee = 8.5V; Rs
specified.

= 600n;

RL

Supply voltage

lee

Supply current

fader is included. The fader control is independent of the volume control and an extra
mute position for the front or the rear or for all
channels is built in. The last function may be
used for muting during preset selection. For
pop-free switching, on and off, an extra pop
suppression circuitry is built in. As all switching and control functions are controllable via
the two-wire 12 C bus. no external interface
between the microcomputer and the
TEA6300 is required. The on-chip power-on
reset sets the TEA6300 into the general mute
mode.

= 10kn; f = 1kHz;

TA = 25°C (Figure 6), unless otherwise

LIMITS

PARAMETER

Vee

TEA6300

UNIT

Min

Typ

Max

7.0

8.5

13.2

26

= 0.5

VREF

Internal reference voltage (Pin 20) VREF

Av

Maximum gain bass and treble linear, fader off

VO(RMS)
VO(RMS)

Output level
for PMAX at the output stage
for start of clipping

VI(RMS)

Input sensitivity at Vo

fR

Frequency response
bass and treble linear;
roll-off frequency -1 dB

35

 10kn

0

VB INTIVREF

Internal bias voltage

1

VI(RMS)
VI(RMS)

Maximum input level
THD< 0.5%
THD < 0.5%; Vce = 7.5V

THD

Total harmonic distortion
VI = 500mV; RL = 10kn

0.1

Nw

Noise voltage weighted CCIR 468-2, quasi peak

20

MV

Va

DC offset voltage between any inputs

10

mV

50

65

kn

100

150

1.65
1.5

9

V
V
%

Control part

(Source selector disconnected, source resistance 600n)
ZI

Input impedance

Zo

Output impedance

35

RL

Admissible output load resistance

10

CL

Admissible output load capacity

0

VI(RMS)

Maximum input voltage
THD < 0.5%; G = -10dB;
bass and treble linear

2.0

Nw
Nw
Nw
Nw

Noise voltage weighted acc CCIR 468-2, quasi peak,
bass and treble linear, fader off
gain 20dB
gain OdB
gain -66dB
mute position

110
25
19
11

Continuous control range

86

dB

2

dB

n
kn

1000

pF

V

220
50
38
22

MV
MV
MV
MV

Volume control
Ge

Step resolution
AG.

Attenuator set error
(G = +20 to -50dB)

2

dB

AG.

Attenuator set error
(G = +20 to -66dB)

3

dB

2

dB

AG t

Gain tracking error balance in mid position,
bass and treble linear

exM

Mute attenuation

February 1987

80

7-219

dB

Preliminary Specification

Signetlcs Linear Products

Digitally-Controlled Tone, Volume, and Fader Control Circuit

TEA6300

DC ELECTRICAL CHARACTERISTICS (Continued) Vee=8.5V; Rs = 6000; RL=10kO; f=lkHz; TA=25·C (Figure 6),
unless otherwise specified.

I

LIMITS
SYMBOL

PARAMETER

UNIT

Min

Typ

Max

14
11

15
12

16
13

dB
dB

0.5

dB

13
13
15

dB
dB
dB

Bass control
Gb
-Gb

Bass control range
f = 40Hz; maximum boost
f = 40Hz; maximum attenuation
Step resolution

dB

3

Step error
Treble control
Gt
-Gt
Gt

Treble control range
f = 15kHz; maximum boost
f = 15kHz; maximum attenuation
f > 15kHz; maximum boost

11
11

Step resolution

12
12

dB

3

Step error

0.5

dB

Fader control
Gf

Continuous attenuation fader control range

30

dB

Step resolution

2

dB
1.5

Attenuator set error
CCM

Mute attenuation

80

dB
dB

Digital part

VIH
VIL

Bus terminals
Input voltage
HIGH
LOW

3
-0.3

12
1.5

V
V

IIH
IlL

Input current
HIGH
LOW

-10
-10

10
10

p.A
p.A

VOL

Output voltage LOW
IL=3mA

0.4

V

AC Characteristics according to the 12 C Bus specification
Power·on Reset
When RESET is active the GMU (general mute) bit is set and
the BUS receiver is in RESET pOSition
Vee
Vee

Increasing supply voltage
start of reset
end of reset

5.2

6.0

2.5
6.8

V
V

Vee

Decreasing supply voltage
start of reset

4.2

5.0

5.8

V

NOTES:
1. The indicated values for output power assume a 6W power amp, with 20dB gain, connected to the output of the circuit. Signal.to-noise ratios exclude noise
contribution of the power amplifier.

2. Signal·lo·noise ratios on a CCIR 468·2 average reading meter are 4.SdB better than on CCIR 468·2 quasi peak.

February 1987

7·220

Preliminary Specification

Signetics Linear Products

Digitally-Controlled Tone, Volume, and Fader Control Circuit

TEA6300

12C BUS FORMAT
S

A

SLAVE ADDRESS

SUB-ADDRESS

S
= start condition
SLAVE ADDRESS = 1000 0000
A
= acknowledge, generated by the slave

P

A

DATA

A

SUB-ADDRESS = see Table 1
DATA
= see Table 1
P
= STOP condition

If more than 1 byte DATA is transmitted, then auto-increment of the sub-address is performed.

Table 1
DATA

SUB-ADDRESS

FUNCTION

Volume left
Volume right
Bass
Treble
Fader
Switch

00000000
00000001
00000010
00000011
00000100
00000101

07

06

05

04

03

02

01

DO

X
X
X
X
X
GMU

X
X
X
X
X
X

VL5
VR5
X
X
MFN
X

VL4
VR4
X
X
FGH
X

VL3
VR3
BA3
TR3
FA3
X

VL2
VR2
BA2
TR2
FA2
SGC

VL1
VR1
BA1
TR1
FA1
SGB

VLO
VRO
BAO
TRO
FAO
SCA

NOTES:

Function of the bits:
VLO to VL5
VRO to VR5
BAO to BA3
TRO to TR3
FAO to FA3
FCH
MFN
SCA to SCC

Volume control left
Volume control right
Bass control
Treble control
Fader control
Select fader channel (front or rear)

GMU

Mute control (general mute) for the outputs OLF, OLR, ORF and ORR
Do not care bits (1 during testing)

X

Mute control of the selected fader channel (front or rear)
Source selector control

Table 2. Bass Setting

Table 3. Treble Setting
DATA

G

DATA

G

(dB)

BA3

BA2

BAl

BAD

(dB)

TR3

TR2

TR1

TRO

+15
+15
+15
+15
+12
+ 9
+ 6
+ 3
0
- 3
- 6
- 9
-12
-12
-12
-12

1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0

1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0

1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

+12
+12
+12
+12
+12
+ 9
+ 6
+ 3
0
- 3
- 6

1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0

1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0

1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

February 1967

- 9
-12
-12
-12
-12

7-221

I

Signetlcs linear Products

Preliminary Specification

TEA6300

Digitally-Controlled Tone, Volume, and Fader Control Circuit

Table 4. Volume Setting LEFT
G
(dB)

Table 5. Volume Setting RIGHT
DATA

G
(dB)

DATA
VR5 VR4

VR3

VR2 VR1

VL5

VL4

VL3

VL2

VL1

VLO

20
16
16
14
12
10
6
6
4
2
0
- 2
- 4
- 6
- 6
-10
-12
-14
-16
-16
-20
-22
-24
-26
-28
-30
-32
-34
-36
-36
-40
-42
-44
-46
-46
-50
-52
-54
-56
-58
-60
-62
-64
-66
mute left
mute left

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0

1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0

1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

20
16
16
14
12
10
8
6
4
2
0
- 2
- 4
- 6
- 6
-10
-12
-14
-16
-18
-20
-22
-24
-26
-28
-30
-32
-34
-36
-36
-40
-42
-44
-46
-48
-50
-52
-54
-56
-58
-60
-62
-64
-66
mute right
mute right

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0

1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0

1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

mute left

0

0

0

0

0

0

mute right

0

0

0

0

0

0

February 1967

7-222

VRO

Signetics Linear Products

Preliminary Specification

TEA6300

Digitally-Controlled Tone, Volume, and Fader Control Circuit

Table 6. Fader Function
SETTING

DATA

Front/Rear
dB
dB

a
a

a

- 2
- 4
- 6
- 8
-10
-12
-14
-16
-18
-20
-22
-24
-26
-28
-30

0

0

a
0
0

a
0

a
0

a
0
0
0
0
0
0

MFN FCH FA3 FA2 FA1
1
0

1
1

fader off
1
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

fader front
1
1
1
1
1
1
1
0
1
a
1
0
1
0
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
mute front
1
1

-60

0

0

1

-80

0

a

1

0

DATA

SETTING

MFN FCH FA3 FA2 FA1

1
1

1
1

0
0

a
0

1
0

0
0

1
0

a

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

- 2
- 4
- 6
- 6
-10
-12
-14
-16
-16
-20
-22
-24
-26
-26
-30

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0

1

a

a

1
1
0
0
1
1

1

a
0
1
1
0
0

0

Front/Rear
dB
dB

FAO

a
1
0
1

a
1
0
1
0
1
0

fader off
1
1
1
1

0
0
0

fader rear
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
0
0
0
0
0
0
0
a 0
mute rear
1
1

a
0
0

a

1

0

0

-60

a

0

0

a

0

-80

0

a

0

0

FAO

1
1

1
1

1

a

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

1

0

0

0

a
0
1
1
0
0
1
1
0
0
1
1
0

Table 7
DATA

SELECTED INPUTS
Data
Data
Data
INLC.
Data
INLB.
INLA.
Data

not admissible
not admissible
not admissible
INRC
not admissible
INRB
INRA
not admissible

February 1987

SCC

SCB

SCA

1
1
1
1
0
0
0
0

1
1
0
0
1
1

1
0
1

a
0

MUTE
DATA
CONTROL GMU

a
1
0
1
0

7-223

Active

1

Passive

0

REMARKS
Outputs OLF. OLR. ORF and ORR are
muted
No general mute

Signetics Unear Products

Preliminary Specification

Digitally-Controlled Tone, Volume, and Fader Control Circuit

15

"

10

"

.....

I-5

I-:::
-"/

-10

---

-15
10

10'
I (Hz)

Figure 1. Bass Control

15

/

10

---

.~

!-5

--

-10

...........

-15
10

10'
I (Hz)

Figure 2. Treble Control

160
WITH SOURCE SELECTOR

140

I

/

120

/

Ilil
/,

y

LAST STEP

IV

rIrrr

-/CON
L

-80

-50

-40

-30

-20

-10

10

40
20

20

GAIN (dB)

Figure 3. Output Noise Voltage (CCIR 468·2 Weighted; Quasi Peak)

February 1967

7·224

TEA6300

Signetics Linear Products

Preliminary Specification

Digitally-Controlled Tone, Volume, and Fader Control Circuit

TEA6300

90

V.-SOOmV

80

.....

70

V1=50mV

-

50
40

./

NOTE:
VI MIN = 50mV; Vo = 500mV for PMAX.

30
O.lmW

O.lW

10mW

lmW

lW

lOW

Po

Figure 4. Signal-to-Noise Ratio (CCIR 468-2 Weighted; Quasi Peak) With
a 6W Power Amplifier (Gain 20dB) Without Noise Contribution of
the Power Amplifier (See Figure 6)

330nF

I+

IN C RIGHT 0 2.2.F

I+
l..2.F I +

IN BRIGHT; 2.2.F

":"2.2 F

INARIGHT~ +

15

14

16

13

17

12 2.2.:

j----o IN CLEFT

18

11 100. :

~

19

10 2.2.F+

~ IN B LEFT

20

~
OUT RIGHT FRONT ~4.7.F I +
(8~C.Ji

~

8 2.2"F+

33nF

+

5.6nF

24
25
2B

27
2B

f---o INALEFT

TEA6300

23

5.6nF

OUT RIGHT REAR

1-'------0 NC

21
22

33nF

330nF

~
4

4.7 F

":"
"+ I----<>
OUT LEFT FRONT

3

4.7"~

I----<> OUTLEFT REAR

t=-------o GNOB

1-'------0 SOA

L-~========~-----o~L
Figure 6. Test and Application Circuit

February 1987

7-225

Figure 5. Recommended Level Diagram

NE5240

Signetics

Dolby Digital Audio Decoder
Preliminary Specification

Linear Products

DESCRIPTION
The NE5240 is a two channel decoder
for the Dolby Digital Audio System. 'The
IC includes input latches to separate two
channels of audio and control data, a
precision internal voltage reference, and
digital/analog signal processing circuitry
for each channel. The IC design is implemented in a bipolar process to achieve
low noise, low distortion, and wide dynamic range.
NOTE:
.. Available only to licensees of Dolby Laboratories
Licensing Corporation, San Francisco, from whom
licensing and applications information must be ob-

tained. Dolby is a registered trademark of Dolby
Laboratories Licensing Corporation, San Francisco,
California.

FEATURES
• Wide dynamic range - 85dB
• Low distortion 0.05% @ 1kHz,
-10dB
• TTL and CMOS compatible logic
inputs
• Audio bandwidth - 30Hz to
15kHz
APPLICATIONS
• High quality digital transmission
of audio data
• Satellite reception
• Cable TV
• Microwave distribution systems

ORDERING INFORMATION
DESCRIPTION
28-Pin SO
28-Pin Plastic DIP

February 1987

TEMPERATURE RANGE

ORDER CODE

o to +70'C
o to +70'C

NE5240D
NE5240N

7-226

PIN CONFIGURATION
N, D Packages
MULTOUT*·

MULTOUT' 1
ANALOG
SUPPLY VOLT
VARIABLE

ANAlOGGND
VARIABLE

IMPEDANCE··

IMPEDANCE"

OUT"
SUM NODE' 5
INTERNAL
AMPLIFIER'
SUDINGBAND
BUFFERIN*
SLIDING BAND
BUFFER OUT'
SfEPSIZE
BUFFER IN'
SfEPSIZE

24 SUMNQDEu

BUFFEROUT*

19

W$~~l'N ..
ru~~~gUT"

LOGIC
SUPPLY
SfEPSlZE
DATA IN
AUDIO
DATAIN
SUDINGBAND
DATA IN

1

DIGITAL GND

23

l:~~,~MR
SLIDING BAND
BUFFERIN u
SLIDING BAND
BUFFER OUT"

20

EXT RES
REFVOLT

lOP VIEW

Signetics Linear Products

Preliminary Specification

Dolby Digital Audio Decoder

NE5240

BLOCK DIAGRAM
A.
UK

A2
43K

C.
C2
O.47J.1F;J; 47nF

A3
360K

J;

R.S
S.'K

C3
4.7nF;:J;

R4 4.3K RS 43K RS 360K

"

18

.9

21

NOTE:

I

One channel of the application shown with external components.

February 1987

7-227

Preliminary Specification

Signetics Linear Products

NE5240

Dolby Digital Audio Decoder

ABSOLUTE MAXIMUM RATINGS
SYMBOL

RATING

UNIT

Vs

Analog supply voltage

PARAMETER

+15

V

Voo

Logic supply voltage

+7

TA

Operating ambient temperature range

TSTG

Storage temperature range

TSOLO

Lead temperature (soldering, 60see)

o to

V
·C

+70

-65 to +150

·C

+300

·C

DC ELECTRICAL CHARACTERISTICS All specifications are at T A = 25·C, Vee = 12V, Voo = 5V.
LIMITS
PARAMETER

SYMBOL

UNIT

TEST CONDITIONS
Min

Typ

Max

Vee

Analog voltage supply range

10

12

14

Voo

Logic voltage supply range

4.5

5

5.5

V

lee

Supply current

10

24

35

mA

5

12

18

mA

= 12V
Voo = 5V

Vee

V

100

Supply current

VIH

Input voltage high

2

5

V

VIL

Input voltage low

0

0.8

V

IlL

Input current low

10

100

IIH

Input current high

1

100

iJ.A
iJ.A

= 4.5V

Voo

ts

Setup time

150

tH

Hold time

150

18

Input buffers, Pins 7, 9, 20, 22

RL

Summing amp output load

Vos

Output offset voltage

Vos

Output offset change

VREF

Reference voltage

February 1987

VIN

ns
ns

= 2.0V

100

W.

5

10%-S8D-70%
5.5

7·228

nA

0.1

0.6

V

±5

±20

mV

0.5Vee

6.5

V

Signetics Linear Products

Preliminary Specification

Dolby Digital Audio Decoder

NE5240

AC ELECTRICAL CHARACTERISTICS
LIMITS

Vo

TEST CONDITIONS2

PARAMETER

SYMBOL

Full-Scale output. OdB

f = 100Hz

Absolute output level

f = 1kHz. SSD = 40%

= 1kHz.

UNIT
Min

Typ

93

118

Max

1.8

VRMS
150

mVRMS
dB

Channel balance

f

20%-SSD-70%

-1.5

1.5

Step-Size linearity

f = 1kHz. 20%-SSD-70%

-1.5

1.5

dB

Step-Size linearity

f = 100Hz. SSD = 90%

-2.5

1.0

dB

fR

Frequency response

f = 2kHz. SBD = 10%

-1.0

1.0

dB

fR

Frequency response

f = 5kHz. SBD = 20%

-1.0

1.0

dB

fR

Frequency response

f = 7kHz. SBD = 30%

-1.0

1.0

dB

fR

Frequency response

f = 8kHz. SBD = 40%

-1.0

1.0

dB

fR

Frequency response

f = 10kHz. SBD = 50%

-1.0

1.0

dB

fR

Frequency response
(all WRT 100Hz)

f = 12kHz, SBD = 60%
f = 14kHz, SBD = 70%

-1.0
-1.5

1.0
1.5

dB
dB

SSD = 70%, CCIRI ARM

80

SIN

Dynamic range

THD

Harmonic distortion

f = 1kHz, -3dB

0.1

0.5

%

THD

Harmonic distortion
Channel separation

f= 1kHz, -10dB
f = 1kHz, OdB

0.05
75

0.2

%
dB

PSRR

Power supply rejection ratio 1

f = 1kHz

60

85

60

dB

dB

NOTES:

1. PSRR depends on value of capaCitor on Pin 16.
2. The duty cycle of SSD and SBD control data is 10%, unless otherwise noted.

•
February 1987

7-229

NE645/646

Signetics

Dolby Noise Reduction Circuit
Product Specification

Linear Products

PIN CONFIGURATION

DESCRIPTION

FEATURES

The NE645/646 is a monolithic audio
noise reduction circuit designed as a
direct replacement device for the
NE645B/NE646B in Dolby' B-Type
noise reduction systems. The NE6451
646 is used to reduce the level of
background noise introduced during recording and playback of audio signals on
magnetic tape, and to improve the noise
level in FM broadcast reception. This
circuit is available only to licensees of
Dolby Laboratories Licensing Corporation, San Francisco, California.

• Accurate record mode frequency
response
• Excellent frequency response
tracking with temperature and
Vec ± 0.4 dB. typical
• Excellent back-to-back dynamic
response - DC shift less than
20mV typical
• Improved stability of all op amps
• High reliability packaging

NOTE:
*T.M. Dolby Laboratories licensing Corporation.

N Package

APPLICATIONS
• Tape decks
• Dolby surround sound system

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

o to
o to

16-Pin Plastic DIP
16-Pin Plastic DIP

ORDER CODE

+70·C

NE645N

+70·C

NE646N

BLOCK DIAGRAM
16

November 14, 1986

7-230

853-0952 86554

Signetics Linear Products

Product Specification

NE645j646

Dolby Noise Reduction Circuit

ABSOLUTE MAXIMUM RATINGS
SYMBOL

RATING

UNIT

24

V

o to +70
-65 to +150

'C
'C

+300

'C

PARAMETER

Vee

Supply voltage

TA
TSTG

Temperature range
Operating ambient
Storage

TSOLD

Lead soldering temperature
(10sec max)

DC ELECTRICAL CHARACTERISTICS Vee = 12V, f = 20Hz to 20kHz. All levels referenced to 580mVRMS (OdB) at
Pin 3, TA = + 25'C, unless otherwise specified.
NE645
SYMBOL

PARAMETER

UNIT
Min

Vee

Supply Voltage Range

lee

Supply Current

Av

Voltage gain (Pins 5 - 3)

Av

Voltage gain (Pins 3 - 7)
Distortion
THO, 2nd and 3rd
harmonic
Signal handling 1
(Vee = 12V)

SIN

Signal-to-noise rati0 2

Typ

8
Vee
f

= 12V

= 1kHz (Pins 6 and 2 connected)
f = 1kHz, 0 dB at Pin 3, noise
reduction out

f

24.5
-0.5

f = 20Hz-l0 kHz, OdB
= 20Hz -10 kHz, + 10dB

Max

Min

20

8

Typ

Max

20

V

16

24

mA

16

24

26

27.5

24.5

26

27.5

dB

0

+0.5

-0.5

0

+0.5

dB

0.05
0.15

0.1
0.3

0.05
0.2

0.2
0.5

%
%

1% dist at 1kHz

+12

+15

+12

+15

dB

Record mode
Playback mode

67

72
82

64
74

72
82

dB
dB

Record mode
Frequency response
(at Pin 7) referenced
to encode monitor point
(Pin 3)

f

OdB
-20dB
-30dB

-1
-1.5
0
+1
0
+1.5
-16.6 -15.6 -14.6 -17.1 -15.6 -14.1
-23.5 -22.5 -21.5 -24.0 -22.5 -21.0

dB
dB
dB

-0.7 +0.3 +1.3 -1.2 +0.3 +1.8
-17.8 -16.8 -15.8 -18.3 -16.8 -15.3
-22.8 -21.8 -20.8 -23.3 -21.8 -20.3
-30.2 -29.7 -28.7 -30.2 -29.7 -28.2

dB
dB
dB
dB

-0.3 +0.7 +1.7 -0.8 +0.7 +2.2
-18.3 -17.3 -16.3 -18.8 -17.3 -15.8
-24.5 -23.5 -22.5 -25.0 -23.5 -22.0

dB
dB
dB

= 5kHz
OdB
-20dB
-30dB
-40dB

f

77

= l.4kHz

f

= 20kHz
OdB
-20dB
-30dB

Back-to-back frequency
response

NE646

TEST CONDITIONS

Using typical record mode .5
frequency response test points

-1

0

+1

-1.5

0

+1.5

dB

RIN

Input resistance

Pin 5
Pin 2

35
3.1

50
4.2

65
5.3

35
3.1

50
4.2

65
5.3

kn
kn

ROUT

Output resistance

Pin 6
Pin 3
Pin 7

1.9

2.4
80
80

3.1
120
120

1.9

2.4
80
80

3.1
120
120

kn
n
n

Back-to-back frequency
response shift
vs temperature
vs supply voltage

O'C to +70'C
8-20V

±OA
±OA

NOTES:
1. See maximum Signal handling versus supply voltage characteristics.
2. All noise levels afe measured CCIR/ARM weighted using a 10k source with respect to Dolby level. See Dolby Laboratories Bulletin 19.

November 14, 1986

7-231

±OA
±OA

dB
dB

Signetics Linear Products

Product Specification

NE645/646

Dolby Noise Reduction Circuit

TYPICAL PERFORMANCE CHARACTERISTICS
THO

VB

Frequency Record Mode

THO

1.0

!

VB

Frequency Record Mode

1.0

!z

~::EiW

~

!z

;:.d~2~

i -

0.1

z

odBt:tt:t
Vcc-12V

!.! 0.1

g
!II

-I'-

'z"

!.! 0.1

z

ia:

0
lE

0
lE

a:

a:

C

C

....

%

g...

:l!

~

%

....

j!

g

0.01

0.01

0.01
100

lK

10K

VB

THO vs Frequency
Noise Reduction (NR) Off

,.1 kHz

Vcc· '2V

~

:1

0.1

~

,

i

g

u

~

~ 0.01
-20

-10

+10

cc· .12\j

I

.......

20

!z

I

):

1%tHD
I
RECORD MODE
18 r-1 kHz

III

....
0

'"
...li!.::>
...::>

+10 B

0.1

16

.

14

/

0

I

12

0.01

,,/

V
./

/v

III

Od

V

10

lK

100

+20

10K

Maximum Signal Handling
VS Supply Voltage

1.0

1.0

u

1K
FREQUENCY (Hz)

FREQUENCY (Hz)

Output Record Mode

!z

~

100

10K

1K

100

FREQUENCY (Hz)

THO

Frequency Play Mode

;:
a:

;:
a:

~2

VS

0

0

Ii:

THO
1.0

10K

FREQUENCY (Hz)

OUTPUT (dB)

8

10

12

14

18

18

Vee - SUPPLY VOLTAGE (VOLTS)
OPt0120S

Supply Current VB
Supply Voltage
20

1...
z

'"a:a:

::>

15

u

..~

V' ~

.--....-

::>

I

~

10

10

12

14

18

18

Vee - SUPPLY VOLTAGE (VOLTS)

APPLICATION INFORMATION
The NE645/646 is a direct replacement for
the NE645B/646B. The NE645/646 incorpo-

November 14, 1986

rates improved design techniques to insure
excellent performance required in Dolby B
and C Type Audio Noise Reduction Systems.
Critical component values are unchanged

7-232

except for C309 on Pin 1 which is now an
optional component in specific applications
defined by Dolby Laboratories. All circuit
parameters are guaranteed at 12V Vee.

Product Specification

Signetics Linear Products

NE645/646

Dolby Noise Reduction Circuit

DOLBY ENCODER Output for constant level input (single tone frequency response)
Input Level (dB)
Frequency
(kHz)

0
(Dolby
Level)

-5

-10

-15

-20

-25

-30

-35

-40

0.1

0

0.1

0

0.1

0

0

0

0

0

0.14

0

0.2

0.2

0.2

0.2

0.2

0.1

0.2

0.1

0.2

0

0.3

0.4

0.5

0.5

0.6

0.6

0.5

0.5

0.3

0

0.3

0.6

1.1

1.3

1.3

1.3

1.3

1.3

2.0

2.1

2.2

2.3

2.1

0.4
0.5

0

0.3

0.8

1.8

2.6

0.6
0.7

a

0.4

0.9

2.1

3.5

0.8

2.9

2.9

3.0

2.9

3.6

3.7

3.8

3.7

4.3

4.4

4.5

4.4

4.8

5.0

5.3

5.1

5.6

5.8

5.6

6.1

6.3

6.2

0.9

a

0.4

1.0

2.3

4.2

5.7

6.9

7.1

7.1

1.4

0

0.3

0.9

2.3

4.4

6.6

7.5

7.7

7.7
8.9

1.0
1.2

2.0

0.1

0.4

0.9

2.2

4.3

7.0

8.5

8.9

3.0

0.2

0.6

0.9

1.9

3.9

6.6

8.8

9.7

9.7

5.0

0.3

0.6

1.0

1.7

3.2

5.4

8.2

10.0

10.3
10.4

7.0

0.3

0.6

1.0

1.7

2.8

4.7

7.3

9.7

10.0

0.4

0.7

1.1

1.7

2.6

4.2

6.5

9.1

10.4

14.0

0.5

0.8

1.1

1.8

2.7

4.4

6.5

8.7

10.3

20.0

0.7

0.7

1.2

1.9

2.7

4.4

6.5

8.7

10.3

NOTE:
The figures given in this table are the average response of many of Dolby Laboratories' professional encoders, and are not intended to be taken as required

consumer equipment performance characteristics. Thus, no inference should be drawn on the tolerances which licensees must retain in consumer equipment. The
figures can, however, be used to plot typical characteristics,

November 14, 1986

7-233

Signetics Linear Products

Product Specification

NE645/646

Dolby Noise Reduction Circuit

TEST CIRCUIT

C20II
lOI'F
15YDC

E.C>----~~---1~:~~
+.

'l:.:.J

0 dB

,.

R30I

1.

14 R304
270K

C20II

C304

470pF

rO,047Jl.F

'"

ROO'

,,,

3.3K

NOTE:
An resistors standard and are measured in

November 14, 1986

n.

"Optional capacitor in specific applications defined by Dolby Laboratories.

7-234

C306

J,0.1,11F
R305

'10'

..
COO7

JO.33I'F

NE648/649

Signetics

Low Voltage Dolby Noise
Reduction Circuit
Product Specification
Linear Products

DESCRIPTION
The NE648/649 is an audio nOise reduction circuit designed for use in low voltage entertainment systems. The circuit
is used to reduce the level of background noise introduced during the recording and playback of audio signals on
magnetic tape and improve the noise
Dolby is a trademark of Dolby Laboratories Licensing Corporation

level in FM broadcast reception. The
circuit is intended for use in automotive
and portable cassette DolbyTM B-Type
noise reduction systems. This circuit is
available only to licensees of Dolby Laboratories Licensing Corp., San Francisco.

PIN CONFIGURATION
N Package

FEATURE
• Low voltage operation

APPLICATION
• Tape decks

ORDERING INFORMATION
TEMPERATURE RANGE

ORDER CODE

16-Pin Plastic DIP

DESCRIPTION

o to +70°C

NE648N

16-Pin Plastic DIP

o to +70°C

NE649N

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

Vce

Supply voltage

TA

RATING

UNIT

16

V

Operating temperature range

-40 to +85

°C

TSTG

Storage temperature range

-65 to +150

°C

TSOLD

Lead soldering temperature 10sec max

+300

°C

BLOCK DIAGRAM

February 20, 1987

II

,.

7-235

853-1193 87692

Signetics Linear Products

Product Specification

NE648/649

Low Voltage Dolby Noise Reduction Circuit

DC ELECTRICAL CHARACTERISTICS vee = 9V, f = 20Hz to 20kHz. All levels referenced to 580mVRMS (OdB) at Pin 3,
TA

= + 25°C,

unless otherwise specified.
NE648

SYMBOL

Vee

PARAMETER

Supply voltage range 3
Minimum voltage supply
for
8dB headroom
10dB headroom

Icc

Supply Current

Icc

Supply Current1

Av

Voltage gain (Pins 5 - 3)

Av

Voltage gain (Pins 3 - 7)
Distortion

NE649

TEST CONDITIONS

f = 1.4kHz
THD< 1%

UNIT
Min

Typ

Max

Min

Typ

Max

6

9

14

6

9

14

6.5
7.5

6.5
7.5
11

18

V
V
11

20
f = 1kHz
(Pins 6 and 2 connected)

f

= 1kHz,

OdB at Pin 3,
noise reduction out

V

18

mA

20

mA

24.5

26

27.5

24.5

26

27.5

dB

-0.5

0

+0.5

-0.5

0

+0.5

dB

0.05
0.2

0.1
0.3

0.05
0.2

0.2
0.5

%
%

f = 20kHz to 10kHz, OdB
f = 20Hz to 10kHz, + 10dB

Signal Handling
(See Performance Characteristics)

SIN

Signal-to-noise rati0 2

Record
(Pins 6 and 2 connected)
Playback
(Pins 6 and 2 connected)
If = 1.4kHz
OdB
-20dB
-30dB

Record mode frequency
response (at Pin 7)
referenced to encode
monitor point (Pin 3)

f

64

72

dB

77

B2

74

82

dB

-1.5
0
+1
-15.6 -14.6 -17.1
-22.5 -21.5 -24.0

0
+1.5
-15.6 -14.1
-22.5 -21.0

dB
dB
dB

-0.7
+0.3 +1.8
+0.3 +1.3 -1.2
-17.8 -16.8 -15.8 -18.3 -16.8 -15.3
-22.8 -21.8 -20.8 -23.3 -21.8 -20.3
-30.2 -29.7 -28.7 -30.2 -29.7 -28.2

dB
dB
dB
dB

-0.3 +0.7
-18.3 -17.3
-24.5 -23.5

+2.2
-15.8
-22.0

dB
dB
dB

= 5kHz

= 20kHz
OdB
-20dB
-30dB

Back-to-back frequency
response

72

-1
-16.6
-23.5

OdB
-20dB
-30dB
-40dB
f

67

Using typical record mode
response

RIN

Input resistance

Pin 5
Pin 2

ROUT

Output resistance

Pin 6
Pin 3
Pin 7

+1.7
-16.3
-22.5

-O.B +0.7
-1B.8 -17.3
-25.0 -23.5

± 1.0

± 1.5

db

35
3.1

50
4.2

65
5.3

35
3.1

50
4.2

65
5.3

kn
kn

1.9

2.4
80
BO

3.1
120
120

1.9

2.4
BO
80

3.1
120
120

kn
n
n

Record mode frequency
response shift
vs temperature
vs Vee

o to 70°C
-40 to 85°C
6 to 14V

±0.3
±0.5
0.2

NOTES:
1. With electronic switching.

2. All noise levels are measured CCIR/ARM weighted using a 10k source wtth respect to Dolby level. See Dolby Laboratories Bulletin t9.
3. The circuit will function as low as Vee = 4.5V (i.e .• output signal present). See graphs of Icc and signal handling vs Vee.

February 20, 1987

7-236

dB
dB
dBN

Signetics Linear Products

Product Specification

NE648/649

low Voltage Dolby Noise Reduction Circuit

TYPICAL PERFORMANCE CHARACTERISTICS
(+ 10dB) THO vs Frequency

(OdB) THO vs Frequency

1.0

1.0

at

at

9V,

Q'o. 1

Q O. 1
....

i!:

:I:

loV

6V
9V

100

lK
FREQUENCY (Hz)

.....-:: .:v

0.01
100

0.01
10K

~
14V

lK
FREQUENCY (Hz)

10K

Maximum Signal Handling
vs Supply Voltage for
1% THO (Record)

Current vs Supply Voltage
17

15

> 15
40°C

13

..

J.o~1

::;;r
+1000~

1

II 11

+ 25°C

l!

9

:s
....

7

ai

~

!;
~
:>

1

0-1

8

10

12

14

16

-3

18

VccM

6

8

10

12

14

16

SUPPLY VOLTAGE (V)

II

February 20, 1987

7-237

Signetics Linear Products

Product Specification

NE648/649

Low Voltage Dolby Noise Reduction Circuit

DOLBY ENCODER Output for constant level input (single tone frequency· response)
INPUT LEVEL (dB)
FREQUENCY
(kHz)

0
(DOLBY
LEVEL)

-5

-10

-15

-20

-25

-30

-35

-40

0.1

0

0.1

0

0.1

0

0

0

0

0

0.14

0

0.2

0.2

0.2

0.2

0.2

0.1

0.2

0.1

0.2

0

0.3

0.4

0.5

0.5

0.6

0.6

0.5

0.5

0.3

0

0.3

0.6

1.1

1.3

1.3

1.3

1.3

1.3

2.0

2.1

2.2

2.3

2.1

0.4
0.5

0

0.3

O.B

1.B

2.6

0.6
0.7

0

0.4

0.9

2.1

3.5

0.8

2.9

2.9

3.0

2.9

3.6

3.7

3.8

3.7

4.3

4.4

4.5

4.4

4.8

5.0

5.3

5.1

5.6

5.8

5.6

6.1

6.3

6.2

0.9
1.0

0

0.4

1.0

2.3

4.2

5.7

6.9

7.1

7.1

0

0.3

0.9

2.3

4.4

6.6

7.5

7.7

7.7
8.9

1.2
1.4
2.0

0.1

0.4

0.9

2.2

4.3

7.0

8.5

8.9

3.0

0.2

0.6

0.9

1.9

3.9

6.6

8.B

9.7

9.7

5.0

0.3

0.6

1.0

1.7

3.2

5.4

8.2

10.0

10.3

7.0

0.3

0.6

1.0

1.7

2.8

4.7

7.3

9.7

10.4

10.0

0.4

0.7

1.1

1.7

2.6

4.2

6.5

9.1

10.4

14.0

0.5

0.8

1.1

1.8

2.7

4.4

6.5

8.7

10.3

20.0

0.7

0.7

1.2

1.9

2.7

4.4

6.5

8.7

10.3

NOTE:
The figures given in this table are the average response of many of Dolby Laboratories' professional encoders, and are not intended to be taken as required

consumer equipment performance characteristics. Thus, no inference should be drawn on the tolerance which licensees must retain in consumer equipment. The
figures can, however, be used to plot typical characteristics.

February 20, 1987

7·238

Signetics Linear Products

Product Specification

NE648/649

Low Voltage Dolby Noise Reduction Circuit

TEST CIRCUIT

C206
10~F

15VDC

C>----~~--~~:~~
·*R309

"
C202

220I'F
15VDC

+

:;J;
r--t-"t-------i
13

• 308
180

C304
rOo047PF

.%

.301
3.3K
1%

February 20, 1987

7-239

14 R3D4
270•

C308

1.
C307

Io.1,11F IOo33I'F

NE650

Signetics

Dolby B-Type Noise Reduction
Circuit
Product Specification
Linear Products

DESCRIPTION
The NE650 is a monolithic audio noise
reduction circuit designed for use in
Dolby™S-Type noise reduction systems. The NE650 is used to reduce the
level of background noise introduced
during recording and playback of audio
signals on magnetic tape.

The NE650 features excellent dynamic
characteristics over a wide range of
operating conditions and is pin-compatible with NE645/646. This circuit is available only to licensees of Dolby Laboratories Licensing Corp., San Francisco.

PIN CONFIGURATION
N Package

Dolby is a trademark of Dolby laboratories licensing Corporation.

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

o to

16-Pin Plastic DIP

ORDER CODE

NE650N

+70'C

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

Vce

Supply voltage

TA
TSTG

Temperature range
Operating ambient
Storage

TSOlD

Lead soldering temperature (10 sec. max)

RATING

UNIT

24

V

o to +70
-65 to + 150

'C
'C

+300

'C

BLOCK DIAGRAM
16

November 14, 1986

7-240

853-0953 86554

Signetics Linear Products

Product Specification

NE650

Dolby B-Type Noise Reduction Circuit

DC ELECTRICAL CHARACTERISTICS Vcc = 12V, f = 20Hz to 20kHz. All levels referenced to 580mVRMS(Odb) at Pin 3,
TA = + 25°G, unless otherwise noted.
NE6S0
PARAMETER

SYMBOL

UNIT

TEST CONDITIONS
Min

Typ

Vee

Supply voltage range

Icc

Supply current

Av

Voltage gain (Pins 5 - 3)

f = 1kHz (Pins 6 and 2 connected)

25.5

Av

Voltage gain (Pins 3 - 7)

f = kHz, OdB at Pin 3, noise reduction out

-0.5

Av

Voltage gain (Pins 2 - 3)

f = 1kHz

13

f=20Hz to 10kHz, OdB
f=20Hz to 10kHz, + 10dB

0.05
0.15

Distortion
THO: 2nd and 3rd harmonic
Signal handling
SIN

Signal-to-noise ratio'
Back-to-back frequency response

Record mode frequency response
(at Pin 7) referenced to encode
monitor point (Pin 3)

8
Electronic switching on

Max

20

V

24

rnA

26

26.5

dB

0

+0.5

dB

16

dB
0.1
0.3

%
%

1% distortion at 1kHz

+12

+15

dB

Record mode
Playback mode

68
78

72
82

dB
dB

to.5

dB

Using typical record mode response
f = 104kHz
OdB
-20dB
-30dB

-0.5
-16.1
-23.5

0
-15.6
-22.5

+0.5
-15.1
-21.5

dB
dB
dB

f = 5kHz
OdB
-20dB
-30dB
-40dB

-0.7
-17.3
-22.3
-30.2

+0.3
-16.8
-21.8
-29.7

+1.3
-16.3
-21.3
-29.2

dB
dB
dB
dB

f = 20kHz
OdB
-20dB
-30dB

-0.3
-18.3
-24.5

+0.7
-17.3
-23.5

+ 1.7
-16.3
-22.5

dB
dB
dB

RIN

Input resistance

Pin 5
Pin 2

35
3.1

50
4.2

65
5.3

kS1
kS1

Output resistance

Pin 6
Pin 3
Pin 7

1.9

ROUT

204
80
80

3.1
120
120

kS1
S1
S1

Back-to-back frequency response
shift
vs TA
vs Vee

OOG to -70 o G
8 to 20V

tOA
tOA

NOTE:
1r All noise levels are measured CCIRI ARM weighted using a 10k source with respect to Dolby level. See Dolby Laboratories Bulletin 19.

November 14, 1986

7-241

dB
dB

Signetics Linear Products

Product Specification

Dolby B-Type Noise Reduction Circuit

NE650

PERFORMANCE CHARACTERISTICS
THO vs Frequency Record Mode

THO vs Frequency Record Mode

~::~
1~ ~~~~~~~~~~~~
~

l

It-H-t

z

e
l!l

lz

;:CO~~

i
"!.!

~

!.!0.111
.

.

~...

THO vs Frequency Play Mode

1.0

-

0.1

z

1"--1"-

~

!
:z:

§
0.01 '---'---'-..J...J...u.w.._-,---,--,u..L.ll.U
100
1K
10K

~

0.01

Maximum Signal Handling vs
Supply Voltage
20

1.0

,., kHz
Vcc· 12V

~

z

0

~

... 0.01
-20

-10

18
~

+10

16

:>

14

:>

0

12

I I

I

0.01

+20

10K

FREQUENCY (Hz)
OP10110S

20

~

8

V

~

10
Vee -

12

14

18

SUPPLY VOLTAGE (VOLTS)

7-242

V

/

8

10
Yee -

Supply Current vs
Supply Voltage

~

V

10

1K

100

V
./

/

l!.

Oda

OUTPUT (dB)

November 14, 1986

1% fHD
r-~ECORD MODe
1kHz

~

....
.....

g
+10 8

I

,/

c

g

I

Vee· 1~~

~ 0.1

:E

:z:

lz

I

II

0.1

10K

FREQUENCY (Hz)

THO vs Frequency
Noise Reduction (NR) Off

1.0

lz

!.!

1K

FREQUENCY (Hz)

THO vs Output Record Mode

i
.

10K

1K

100

FREQUENCY (Hz)

18

12

14

16

SUPPLY VOLTAGE (YOLTS)

18

Signetics Linear Products

Product Specification

Dolby B-Type Noise Reduction Circuit

NE650

DOLBY ENCODER Output for constant level input (single tone frequency response)
Input Level (dB)
Frequency
(kHz)

0
(Dolby
Level)

-5

-10

-15

-20

-25

-30

-35

-40

0.1

0

0.1

a

0.1

0

0

0

0

0

0.14

0

0.2

0.2

0.2

0.2

0.2

0.1

0.2

0.1

0.2

0

0.3

0.4

0.5

0.5

0.6

0.6

0.5

0.5

0.3

0

0.3

0.6

1.1

1.3

1.3

1.3

1.3

1.3

2.0

2.1

2.2

2.3

2.1

2.9

2.9

3.0

2.9

3.6

3.7

3.B

3.7

0.4
0.5

0

0.3

0.8

1.8

2.6

0.6
0.7

0

0.4

0.9

2.1

3.5

0.8

4.3

4.4

4.5

4.4

4.8

5.0

5.3

5.1

5.6

5.8

5.6

5.7

6.1

6.3

6.2

6.9

7.1

7.1

6.6

7.5

7.7

7.7
8.9

0.9
1.0

0

0.4

1.0

2.3

4.2

1.2
1.4

a

0.3

0.9

2.3

4.4

2.0

0.1

0.4

0.9

2.2

4.3

7.0

8.5

8.9

3.0

0.2

0.6

0.9

1.9

3.9

6.6

8.8

9.7

9.7

5.0

0.3

0.6

1.0

1.7

3.2

5.4

B.2

10.0

10.3

7.0

0.3

0.6

1.0

1.7

2.8

4.7

7.3

9.7

10.4

10.0

0.4

0.7

1.1

1.7

2.6

4.2

6.5

9.1

10.4

14.0

0.5

0.8

1.1

1.8

2.7

4.4

6.5

8.7

10.3

20.0

0.7

0.7

1.2

1.9

2.7

4.4

6.5

8.7

10.3

NOTE:
The figures given in this table are the average response of many' of Dolby Laboratories' professional encoders, and are not intended to be taken as required

consumer equipment performance characteristics. Thus, no inference should be drawn on the tolerance which licensees must retain in consumer equipment. The
figures can, however, be used to plot typical characteristics.

November 14, 1986

7·243

Signetics Linear Products

Product Specification

NE650

Dolby B-Type Noise Reduction Circuit

TEST CIRCUIT

C206
10.l'F
15VDC

+

EKC>----~~--~~:~~

---c.J

OdB

R309
'K

C2GB

r .%

C304

1

O,047/LF

470pF

R30'

3.3K

,%

NOTES:

All resistors standard and are measured in n.
*Optional capacitor in specific applications defined by Dolby Laboratories.

November 14, 1986

7-244

C306

C307

JO.1I'F JO.3314F
R30'

,10K

Signetics

Symbols and Definitions for
Audio Power Amplifiers

Linear Products

Bridge-Tied Load (BTL)

Noise Output Voltage (VN(RMS»

Ripple Rejection (RR)

An application where the outputs of two
amplifiers are tied to opposite ends of a
load (speaker) thereby increasing the
output power level to the load.

The output noise voltage for a given set
of conditions.

The measure of the amplifier's ability to
reject influences of power supply voltage
variations (ripple).

Output Power

Channel Separation

The power available to the load for a
given set of conditions.

The measure of one monolithic amplifier's ability to reject signals being processed by other amplifier(s).

The maximum instantaneous current
available from the amplifier output.

Input Sensitivity

Repetitive Peak Output Current

The minimum signal magnitude required
to drive the output to a given output
power level.

Peak Output Current

The maximum operating current available from the amplifier output.

Signal-to-Noise Ratio (SIN)
The ratio of recoverable signal level to
the noise level generated by the amplifier.

Standby Current (lse)
The supply current drawn by the device
when operated with no load.

Total Harmonic Distortion (THO)
The measure of the amplifier's ability to
amplify only the input signal without
introducing any harmonic interference.

II

February 1987

7-245

TDA1010A

Signetics

6W Audio Amplifier With
Preamplifier
Product Specification

Linear Products

DESCRIPTION

FEATURES

The TDA1010A is a monolithic integrated class-B audio amplifier circuit in a 9lead single in-line (SIP) plastic package.
The device is primarily developed as a
6W car radio amplifier for use with 4S1
and 2S1 load impedances.

• Single in-line (SIP) construction
for easy mounting
• Separated preamplifier and power
amplifier
• High output power
• Low cost external components
• Good ripple rejection
• Thermal protection

PIN CONFIGURATION

APPLICATIONS
• Stereo power amplifier
• Television
•
•
•
•

POWER AMP GROUND

1

POWER AMP OUTPUT

2

POWER AMP Vee

3

COMPENSATION

4

PREAMPVcc

5

POWER AMP INPUT

6

PREAMP OUTPUT

7

PREAMP INPUT

6

PREAMP GROUND

9
lOP VIEW

Radios
Intercom
Alarms
Modems

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE
TDA1010AU

9-Pin Plastic SIP (SOT-11 OS)

TEST CIRCUIT
C2

r

100nF

R1 330k

+

TC13970S

November 6, 1986

7-246

•

853-0912 86388

Signetics Linear Products

Product Specification

6W Audio Amplifier With Preamplifier

TDA1010A

HEATSINK DESIGN
Assume Vcc = 14.4V; RL = 20; TA = 60°C
maximum; thermal shutdown starts at
TJ = 150°C. The maximum sinewave dissipation in a 20 load is about 5.2W. The maximum dissipation for music drive will be about
75% of the worst-case sinewave dissipation,
so this will be 3.9W. Consequently, the total
resistance from junction to ambient

10

\

\
\

\

fjJA = fjJTAB + fjTABH + fjHA

\
o

-25 0

150-60

\

=- - = 23°C/W.
3.9

150

Since fjJTAB
Figure 1. Power Derating Curve

fjHA

= 23 -

= 10°C/W

(10 + 1)

and OrABH

= l°C/W,

= 12°C/W.

ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
RATING

UNIT

Vcc (MAX)

Supply voltage

24

V

Icc

Peak output current

5

A

Icc (Rep)

Repetitive peak output current

3

A

PTOT

Total power dissipation

SYMBOL

PARAMETER

see derating curve in Figure 1

TSTG

Storage temperature

-65 to +150

°C

TA

Operating ambient temperature

-25 to + 150

°C

tsc

AC short-circuit duration of load during sinewave drive;
without heatsink at Vce = 14.4V

max. 100

hours

DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL

UNIT

PARAMETER
Min

Vcc

Supply voltage range

IORM

Repetitive peak output current

ITOT

Total quiescent current at Vee

November 6, 1986

Typ

6

Max
24
3

=

14.4V

31

7-247

V
A
mA

I

Signetics linear Products

Product Specification

6W Audio Amplifier With Preamplifier

AC ELECTRICAL CHARACTERISTICS

TDA1010A

TA = 25°C; Vcc=14.4V; RL=40; f=1kHz, unless otherwise specified.

LIMITS
SYMBOL

UNIT

PARAMETER
Min

Po
Po
Po
Po
Po

Vee = 14.4V;
Vee = 14.4V;
Vee = 14.4V;
Vee = 14.4V;
Vee = 14.4V;
resistor of

RL = 201
RL = 401,2
RL = 801
RL = 40; without bootstrap
RL = 20; with additional bootstrap
2200 between Pins 3 and 4

5.9

Typ
6.4
6.2
3.4
5.7

W
W
W
W

9

W

AVI
AV2
Av TOT

Voltage gain
preamplifier3
power amplifier
total amplifier

dTOT

Total harmonic distortion at Po = 1W

0.2

11

Efficiency at Po = 6W

75

B

Frequency response (-3dB)

Izil
Izil

Input impedance
preamplifier4
power amplifier5

20
14

IZol

Output impedance of preamplifier; Pin 75

14

VO(RMS)

Output voltage preamplifier (RMS value)
dTOT < 1% (Pin 7)3

0.7

VN(RMS)
VN(RMS)

Noise output voltage (RMS value)6
Rs=OO
Rs=8.2kO

RR
RR

Ripple rejection at f = 1kHz to 10kHz7
at f = 100Hz; C2 = 1/lF

VI

Sensitivity for Po = 5.8W

10

mV

14(RMS)

Bootstrap current at onset of clipping; Pin 4 (RMS value)

30

mA

21
27
51

24
30
54

80Hz

%
%

30
20

40
26

kO
kO

20

26

kO
V

0.3
0.7
42
37

7·248

dB
dB
dB

kHz

mV
mV
dB
dB

Measured with an ideal coupling capacitor to the speaker load.
Up to Po'; SW: dTOT'; 1%.
Measured with a load impedance of 20kfl.
Independent of load impedance of preamplifier.
Output impedance of preamplifier (Izol) is correlated (within 10%) with the input impedance (I ZI b of the power amplifier.
Unweighted RMS noise voltage measured at a bandwidth of 60Hz to 15kHz (12dB/octave).
Ripple rejection measured with a source impedance between 0 and 2kfl (maximum ripple amplnude: 2V).
The tab must be electrically floating or connected to the substrate (Pin 9).

November 6, 1986

27
33
57

15

NOTES;

1.
2.
S.
4.
5.
6.
7.
8.

Max

Signetlcs Linear Products

Product Specification

TDA1010A

6W Audio Amplifier With Preamplifier

30

I

RL =
212
412
812

10 1-t-t-+-+-I-'~'YiH--l

~
10

-5

o
o

1(13

10

I (Hz)

NOTES:
Solid lines indicate the power across the load.
dashed lines that available at Pin 2 of the
TDA 1010. RL'" 2ro1) has been measured with an
additional 220n bootstrap resistor between Pins 3
and 4, Measurements were made at f - 1kHz.

=

=

drOT'" 10%, TA - 25°C.

A)2"

VV

,. ,. '",.
... ...... ,
... .r-',
,. r.:::.. r'"

,;

,

10

7.5

RL~812
2~

ck

••

,

50

75

100

."
,

Figure 6. Thermal Resistance from
Heatslnk to Ambient of a 1.5mm
Thick Bright Aluminum Heatsink
as a Function of the Single-sided
Area of the Heatslnk With the Total
Power Dissipation as a Parameter

100
80

~

.D I-- -

.
80

~

20

o
o

I

QP10710S

NOTE:

2.5

~

For RL - 2.0 an external bootstrap resistor of 220.0
has been used; typical values. Vee -14.4V;

~

I-1kHz.

1
10

NOTES:
Solid lines indicate the power across the load,
dashed lines that available at Pin 2 of the
TDA1010. Rl - 20(1) has been measured with an
additional 2200 bootstrap resistor between Pins 3

Figure 5. Total Power Dissipation
(Solid Lines) and the Efficiency
(Dashed Lines) of the
Test Circuit; a Function of the
Output Power With the Load
Impedance as a Parameter

and 4. Measurements were made at f,.. 1kHz,
Vcc- 14.4V

Figure 3. Total Harmonic Distortion
In the Test Circuit as a Function
of the Output Power with the Load
Impedance as a Parameter;
Typical Values

November 6, 1986

25

Pror=
t--2W

I--sw

HEATSINK AREA (cm2)

Figure 4. Frequency Characteristics
of the Test Circuit for Three Values
of Load Impedance. Po
Relative to OdB 1W; Vee 14.4V

Figure 2. Output Power of the Test
Circuit as a Function of the Supply
Voltage with the Load Impedance as
a Parameter; Typical Velues

"r--.. ~ r-...
-- r- f=::

7-249

•

Signetics Linear Products

Product Specification

6W Audio Amplifier With Preamplifier

C2
100nF

TDA1010A

R1330k

~~--~~--~----~--4---~+

VOWME

RS
22k

V,

...

Uk
7 C3
100nF

en

C4
1nF

180nF

Figure 7. Complete Mono Audio Amplifier of a Radio

November 6, 1986

7-250

TDA1011A

Signetics

2 to 6W Audio Power Amplifier
With Preamplifier
Product Specification

Linear Products

DESCRIPTION
The TDA1011A is a monolithic integrated audio amplifier circuit in a 9-lead
single in-line (SIP) plastic package. The
device is especially designed for portable radio and recorder applications and
delivers up to 4W in a 4U load impedance. The device can deliver up to 6W
into 4U at 16V loaded supply in mainsfed applications. The maximum permissible supply voltage of 24V makes this
circuit very suitable for DC and AC
apparatus, while the low applicable supply voltage of 5.4V permits 9V applications. The power amplifier has an inverted input! output which makes the circuit
optimal for applications with active tone
control and spatial stereo.

FEATURES
• Single in-line (SIP) construction,
for easy mounting
• Separated preamplifier and power
amplifier
• High· output power
• Thermal protection
• High input Impedance
• Low current drain
• Limited noise behavior at radio
frequencies

PIN CONFIGURATION
POWER AMP GROUND 1
POWER AMP OUTPUT 2
POWERAMPVcc 3
COMPENSAnON

4

PREAMPVcc
POWER AMP INPUT
PREAMP OUTPUT 7
PREAMP INPUT 8
PREAMP GROUND 8

APPLICATIONS
• Radios
• Television
• Intercom
• Modems
• Alarms

lOP VIEW
CD11220S

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

9-Pin Plastic SIP (SOT·nOB)

-25·C to + 150·C

TDA1011A

TEST CIRCUIT

!1

100nF

AI
330k

II

+
TDA10llA

November 6, 1986

7-251

853-0913 86389

Signetics Linear Products

Product Specification

2 to 6W Audio Power Amplifier With Preamplifier

TDA1011A

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

UNIT

RATING

Vcc

Supply voltage

24

V

10M

Peak output current

3

A

ProT

Total power dissipation

TSTG

Storage temperature range

see derating curve Figure 1
-65 to + 150

TA

Operating ambient temperature range

-25 to +150

·C

tsc

AC short-circuit duration of load during sine wave drive;
Vce = 12V

100

hours drive;
Vcc = 12V

·C

DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL

PARAMETER

UNIT
Min

Vee

Supply voltage range

10RM

Repetitive peak output current

ITOT

Total quiescent current at Vee = 12V

November 6, 1986

Typ

5.4

14

7-252

Max
20

V

2

A

22

rnA

Signetlcs Linear Products

Product Specification

TDA1011A

2 to 6W Audio Power Amplifier With Preamplifier

AC ELECTRICAL CHARACTERISTICS TA = 25·C; Vce = 12V; RL = 4n; f = 1kHz, unless otherwise specified; see also Test
Circuit.

SYMBOL

LIMITS

PARAMETER

Po
Po
Po
Po
Po

AF output power dTOT = 10% with bootstrap:
Vee = 16V; RL = 4n
Vcc = 12V; RL = 4n
Vec=9V; RL=4n
Vee = 6V; RL = 4n without bootstrap:
Vee = 12V; RL = 4n

AV1
AV2
Av TOT

Voltage gain:
preamplifier2
power amplifier3
total amplifierS

dTOT

Total harmonic distortion at Po = 1.5W

Min

Typ

3.6

6.5
4.2
2.3
1.0
3.5

21

23
2.9
52
0.3

B

Frequency response; -3dB4

Izl1 1
Iz01 1

Input impedance preamplifie,s
Output impedance preamplifier

VO(RMS)

Output voltage preamplifier (RMS value)
dTOT < 1%2

VN(RMS)
VN(RMS)

Noise output voltage (RMS value)6
Rs=On
Rs = 10kn

VN(RMS)

Noise output voltage at 1 = 500kHz (RMS value)
B = 5kHz; Rs = On

RR
RR

Ripple rejection6
1= 1 to 10kHz
1 = 100Hz; C2 = l/lF

60Hz

UNIT
Max
W
W
W
W
W
25

dB
dB
dB

0.3
1

%
%

15kHz

100

200

V

1.2
0.5
0.8

mV
mV

8

/lV

42

dB
dB

35

14(RMS)

Bootstrap current at onset 01 clipping; Pin 4 (RMS value)

19B

Standby current at maximum Vee B

kn
kn

1

35

mA
100

/lA

NOTES:
1. Measured with an ideal coupling capacitor to the speaker load.

2.
3.
4.
5.
6.
7.

Measured with a load resistor of 20kn.
Measured with R2 = 20kn.
Measured at Po = 1W; the frequency response is mainly determined by Cl and C3 for the low frequencies and by C4 for the high frequencies.
Independent of load impedance Of preamplifier.
Unweighted RMS noise voltage measured at a bandwidth of 60Hz to 15kHz (12dB/octave).
Ripple rejection measured with a source impedance between 0 and 2kn (maximum ripple amplitude: 2V).

8. The total current when disconnecting Pin 5 or short-circuited to ground (Pin 9).

9. The tab must be electrically floating or connected to the substrate (Pin 9).

November 6, 1986

7-253

I

Signetics Linear Products

Product Specification

2 to 6W Audio Power Amplifier With Preamplifier

HEATSINK DESIGN
= 12V; RL = 4n; TM = 60°C
= 3.8W.

Assume Vee
maximum; Po

7.5

The maximum sinewave dissipation is 1.8W.

\

!

1
2.5

TDA1011A

"

WITHOUT

~EATSINK

~

o

-25 0

+50

The derating of 10°C/W of the package
requires the following external heatsink (for
sinewave drive):

\~NFINITE
HEATSINK

~

+100
TA('C)

+150

IIJA = IIJTAB

+ IITABH + IIHA

150-60

= - - - = 50°C/W.

1.8
Since IIJTAB = 10°C/W and ~ABH
IIHA = 50-(10 + 1) = 39°C/W.

+200

J=

Figure 1. Power Derating Curve

L

.
Rl

!

rP 2.5

+-----~~----~----------~------~----~~+

~1

I

/I
II

It

v

I~

10
15
Vee (V)

vIce

RL

~

40

= l°C/W,

40

20

25

NOTES:
drOT "" 10%; typical values. The available output
power is 5% higher when measured at Pin 2 (due to
series resistance of C1). *

Figure 5. Output Power Across RL
as a Function of Supply
Voltage with Bootstrap
Figure 2. Circuit Diagram of a 4W Amplifier

10

40

7.5

10'

ll~I~L

.-t

Iljr

I

-I

V

12V

..
o

o

....V

V

16V

I

vee (V)

20

1\

Lk~

10
10

• (MHz)

Po(W)

NOTES:
- with bootstrap; - - - without bootstrap;
f ... 1kHz; typical values. The available output

power is 5% higher when measured at Pin 2
(due to series resistance of C10).

Figure 4. Total Harmonic Distortion as
a Function of Output Power Across RL

November 6, 1986

10

, I
I

30

Figure 3. Total Quiescent Current as a
Function of Supply Voltage

J

I

, ,i ,i

2.5

;
10

"\

~-

I

'14V
TVP

I

7-254

NOTES:
Curve A: total amplifier; CUIV8 B; power amplifier;
B "'" 5kHz: As'" 0; typical values.

Figure 6. Noise Output Voltage as a
Function of Frequency

TDA1013A

Signetics

4W Audio Amplifier With DC
Volume Control
Product Specification

Linear Products

DESCRIPTION

FEATURES

The TDA1013A is a monolithic integrated 4W audio amplifier circuit with DC
volume control in a 9-pin single in-line
(SIP) plastic package. The wide supply
voltage range makes this circuit very
suitable for applications such as television receivers and record players.

•
•
•
•

The DC volume control stage has a
logarithmic control characteristic with a
range of more than BOdS. Control can
be obtained by means of a variable DC
voltage between 3.5 and BV.

PIN CONFIGURATION

DC volume control
SIP package
Low distortion
Logarithmic control

U Package
9

APPLICATIONS
•
•
•
•
•

Computers
Intercom
AM/FM Radio
Television
Modems

The audio amplifier has a well-defined
open-loop gain and a fixed integrated
closed-loop gain. This offers an optimum
in number of external components, performance and stability.

DC CONTROL AMP GROUND

8

DC CONTROL AMP INPUT

7

CONTROL VOLTAGE

8

DC CONTROL AMP OUTPUT

5

POWER AMP INPUT

•

BYPASS

2

POWER AMP OUTPUT

1

POWER AMP GROUND

TOP VIEW

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

9-Pin Plastic SIP (SOT-ll0B)

-25°C to + 150°C

TDA1013AU

BLOCK DIAGRAM
~C,
-

1/J.F

-

R"

220K
+----~

__ _____o+vp
~

TDA1013A

C,
O.1#F

<>-11---..--+---\
...L

C9
22QpFT

+-+:------i
C6

O.1,u.F

C4
O.1j.tf

RS
3.3

R3

S.6K

R,
56n

1.8K

CS
1.5IJ.F

+vp

November 6, 1986

7-255

853-0914 86390

I

Product Specification

Signetics Linear Products

4W Audio Amplifier With DC Volume Control

TDA1013A

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

RATING

UNITS

Vcc

Supply voltage

35

V

108M

Non-repetitive peak output current

3

A

IORM

Repetitive peak output current

T8TG

Storage temperature range

TJ

Junction temperature range

PTOT

Total power dissipation

1.5

A

-65 to +150

'c

-25 to +150

'C

see derating curve, Figure 2

DC AND AC ELECTRICAL CHARACTERISTICS Vee = 18V; RL = 8n; f = 1kHz; TA = 25'C, unless otherwise specilied.
LIMITS
PARAMETER

SYMBOL

UNIT
Min

Vcc

Supply voltage

ITOT

Total quiescent current

Typ

Max

35

15
35

Vn

Noise output voltage (see note)

V,

Total sensitivity (DC control at maximum gain)
lor Po = 2.5W

I

Frequency response (-3dB)

38

55

35Hz

V
mA

1.4

mV

69

mV

20

kHz

Audio amplifier

1.5

IORM

Repetitive peak output current

Po

Output power at dTOT = 10%

dTOT

Total harmonic distortion at Po = 2.5W

0.5

Av

Voltage gain

30

dB

V,

Sensitivity lor Po = 2.5W

125

mV

Iz,1

Input impedance (Pin 5)

250

kn

4

100

4.5

A
W

1

%

DC volume control unit

Gain control range (see Figure 1)

80

VI
V,

Signal handling at dTOT < 1%
(DC control at OdB)
sensitivity lor Vo = 125mV at maximum voltage gain

1.2

Iz,1
IZal

Input impedance (Pin 8)

100

250

Output impedance (Pin 6)

100

200

'"

November 6, 1986

~

SkU and DC control at minimum gain.

7-256

V
mV

55

NOTE:
Measured in a bandwidth according to 'EC 179 curve 'A'; Rs

dB

kn
400

n

Product Specification

Signetics Linear Products

TDA1013A

4W Audio Amplifier With DC Volume Control

HEATSINK DESIGN

I
'I'
,;- 5

"

/

~

/
/

.......

.......

/v

I'....

+20

~

4

~

(JJA

/

.............
3

Assume Vcc = l8V; RL = 8n; T A = 60°C
(maximum); TJ = 150°C (maximum); for a 4W
application into an 8n load, the maximum
dissipation is about 2.5W. The thermal resis·
tance from junction to ambient can be ex·
pressed as:

~

~

~

~

o(dB)

M

U

" (mA)

= (JJTAB + (JTABH + (JHA

_T=-J.:;,M::.,:A:.:,X_-_T:.c,A.:;Mc:.AX::..: __
15_0_-_6_0 = 36 0 C/W.
PMAX

2.5

OP\12eOS

NOTE:
VI at Pin 7.

Since (JJTAB = 9°C/W and ~ABH = l°C/W,
(JHA = 36 - (9 + 1) = 26°C/W.

Figure 1. Typical Values Gain Control

1\
....... .........

..........
o

o

50

\

.......
... .......~

100

150

NOTE:
_ _ Infinite heatsink
- - - - Without heatsink

Figure 2. Power Derating Curve

•
November 6, 1986

7-257

AN148

Signetics

Audio Amplifier With TDA1013A
Application Note

Linear Products

Author: D. Udo

ABSTRACT
The 9-pin SOT -11 DB-encapsulated
TDA10l3A is an audio power amplifier that
has a DC volume control on-board. The
device is designed for audio amplifier applications in TV sound channels.
At a supply voltage of l8V, the output power
is about 4.4W into an 80, loudspeaker.

ELECTRONIC
FILTER

..-:-_ _ _-<}

INPUT ~---=+--I

:R>-F-¢ OUTPUT

The gain control range is > 80dB with a DC
control voltage from 8 to 3.5V.

TDA1013A

Some basic information of the TDA 1013A is
dealt with in this application note. Detailed
performance properties are given for an 18V
into 80, application.

DC VOLUME
CONTROL

Figure 1

INTRODUCTION
The TDA 1013A has two functions: a DC
volume control and audio power amplifier.
Some performance characteristics are:
• Supply voltage range
15 - 35V
• Max. repetitive peak current
1.5A
• Max. non-repetitive peak current
3A
•
•
•
•

IIJTAB
9'C
IIJA
45'C
Input impedance ,(Pins 5 and 8) 100kn
Output impedance (Pin 6)
2000, (typ.)

• Voltage gain DC control part
(Pins 8 to 6)

7dB

• Voltage gain power amplifier
(Pins 5 to 2)

30dB

APPLICATION CIRCUIT
The complete application circuit is given in
Figure 1. With high input impedance, Cg is
necessary to filter-out RF input interferences.
R3 in combination with Cs is used to limit the
AF frequency bandwidth. The 470j.lF power
supply decoupling capacitor is C1Q.

February 1987

SUPPLY VOLTAGE

7-258

Signetics Linear Products

Application Note

Audio Amplifier With TDA1013A

AN148

R4
220K
~-----4------~---------o+Vp

Cl0

~ 470~F

TDA1013A

C,
O.1~F

o---j 1-.---+=----1
C9

..L

220pFi

Hf::---l

C4
O.1,1.1F

RS

R2

R3

3.3

8n

S.6K
R2

56n

CS

1.5,1.1F

+Vp

Figure 2. Block Diagram and External Components

February 1987

7-259

Signetics Linear Products

Application Note

Audio Amplifier With TDA1013A

AN148

MEASUREMENTS
Various measurements made in the circuit of
Figure 1 are given. If not otherwise stated, the
measurements are done at Vee = 18V,
RL = 8n, f = 1kHz and TA = 25°C.

50

I

I

,,'"

......

----~---

Quiescent Current Consumption
The quiescent current as a function of Vee is
given in Figure 3. At Vec = 18V the maximum
spread on 20 samples is indicated by arrows.

Midtap Voltage
The midtap voltage VA versus Vcc at output
Pin 2 is shown in Figure 4.

Output Power and Dissipation
20

• J..

•

1.

15

20

25

30

35

Vp SUPPLY VOLTAGE (V)
0PQ0790S

Figure 3. Quiescent Current

Vcc

VB

25

•
5

V~

•
..... ...""

.., A

••

10

~
15

...............

20

25

30

Vp SUPPlY VOLTAGE (V)

Figure 4. Midtap Voltage vs Vcc

February 1987

/

7-260

35

The output power lor d = 10% as a lunction
01 Vee at Pin 2 and across the 8n loudspeaker load is given in Figure 5. The upper curve
gives the worst-case sinewave dissipation.
The dissipation versus output power for
Vee = 18V is given in Figure 6.

Distortion
The total harmoniC distortion as a function 01
Po is shown in Figure 7 for signal frequencies
01 1 and 10kHz (DC control voltage at Pin 7 is
constant 8V). In Figure 8 the same curve is
given lor I = 1kHz but now the output power
is reduced by the DC control voltage (at
d = 10% Voc Pin 7 = 8V). The distortion for
2.5W output power versus frequency is given
in Figure 11. In Figure 9, the distortion of the
DC gain-controlled preamplifier as a function
01 the signal excursion at Pin 6 is shown lor a
DC control voltage (VDe Pin 7) 01 8V.

Signetics linear Products

Application Note

Audio Amplifier With TDA1013A

AN148

Gain Control
'0

t"" 1kHz,
RL=<80

J=

10010, VCONTRL PIN 7 = 8V

" .......

8

/'

..~

~

..

o

o

WORST-CASE
DISSIPATION ---,

6

.;;:;;--

"
/-:.-~

~///

t--OUTPUT
ACROSSRL

<~ V
;,://

The power bandwidth (d = 10%) is given in
Figure 13. The low frequency behavior is
determined by the value of the output electro·
lytic C7 .

POWER Po

~

Supply Voltage Ripple Rejection

~

<

J..

00

15

17.5

Frequency Characteristic
The frequency characteristic is presented in
Figure 12. The - 3dS bandwidth is from 32Hz
to 20kHz.

Power Bandwidth

"'/'/

",;% ~OUTPUT
,/

4

/~UTPUT AT
PIN 2

The typical overall voltage gain (Voc Pin
7 = 8V) is 38dS. The gain control curve
versus the DC control voltage on Pin 7 is
shown in Figure 10.

20

22.5

25

VpSUPPLY VOLTAGE (V)

Figure 5. Output Power and Dissipation vs Vee

27.

The supply voltage ripple rejection versus
frequency is shown in Figure 14 for Rs = 0
and 10kn. Ripple voltage on Pin 3 is
SOOmVRMS·

Noise Behavior
The A-weighted, IEC 179 standard, signal-tonoise ratio at maximum gain (VDC Pin 7 = 8V)
is 68dS at Rs = on and related to Po = 2.SW.
Increasing Rs has hardly any influence on this
noise level. Typical SIN is 74dS.

4

,st.

Vp =
VCONTROL PlJ 7 = 8V
t='kHz,RL=8!l

",/

I!

",....-

----

i-

I

PO(w)

Figure 6. Dissipation vs Po

February 1987

CONCLUSION
The TDA1013A is a suitable IC as an audio
amplifier in TV receivers. It delivers an output
power of about 4.4W in RL = 8n at
Vce = 18V. An 80dS DC gain control is incorporated.

7-261

I

Application Note

Signetics Linear Products

AN148

Audio Amplifier With TDA1013A

12

10

!

Vp=18V
VCONTAOL = 8V = CONSTANT

.:.z
o

I

a

I

~

10kHz

--

--- -,

01-'
0.1

~
-,.;:: VJ

_1kHz

10

PO(W)

Figure 7. Distortion vs Po

12

10

:I

Vp=18V.'=1_
VCONTROl.

=BV at Po =4.4W

8

6

I
IV

4

2

./

"""

0
0,1

10

PO(W)

Figure 8

February 1967

7-262

Signetics linear Products

Application Note

Audio Amplifier With TDA1013A

AN148

6

5
Vp =18V, I =1kHz
VCONTROL =8V
4

lc

3

2

J

o
o

~

/

2

4

NO R.M.S. (AT PIN 6)

Figure 9. Distortion of Control Amplifier at Pin 6

February 1987

7-263

•

I

Signetics Linear Products

Application Note

Audio Amplifier With TDA1013A

AN148

I
v

'" ~
Vp = lav; VCONTROL PIN 7 = IV
O=10%.RL=80

I

1

II
1
10Hz

100Hz

1kHz

10kHz

FREQUENCY

Figure 10. TYPical Control Curve DC Control Voltage at Pin 7

vp=L III
=
VCONTROL

IV

2

j

1

1\

0
10Hz

V

I't100Hz

1kHz

100kHz

FREQUENCY

Figure 11. Distortion at Po

February 1987

=2.SW vs Frequency (At Pin 2 of IC)

7-264

Signetics Linear Products

Application Note

Audio Amplifier With TDA1013A

i

i

/

AN148

""1\

I

II

-5

a.

REFERENCE LEVEL Po
VCONTROL = 8V

=lW

-10

-1 5

10Hz

100Hz

10kHz

1kHz

100kHz

FREQUENCY

Figure 12. Frequency Characteristic

5

4

V

'\

~

3
Vp = 18V; VCONTROL PIN 7 = 8V
D=IO%,RL=80

/

I

II
1

10Hz

100Hz

1kHz

10kHz

FREQUENCY

Figure 13. Power Bandwidth

February 1987

7-265

100kHz

Signetics Linear Products

Application Note

Audio Amplifier With TDA1013A

50

AN148

NtLWll1

VCONTROL PIN 7 = 8V

r---. ~

40

I'

/V

r'--

/

~,=O!l
10k!!

0

>
0
10Hz

100Hz

1kHz

10kHz

FREQUENCY

Figure 14. Ripple Rejection vs Frequency

February 1987

7-266

100kHz

TDA1015

Signetics

1 to 4W Audio Amplifier With
Preamplifier
Product Specification

Linear Products

PIN CONFIGURATION

DESCRIPTION

FEATURES

The TDA1015 is a monolithic integrated
1 to 4W audio amplifier with preamplifier
circuit in a g-pin single in-line (SIP)
plastiC package. The device is especially
designed for low voltage applications
and delivers up to 4W in a 4.n load
impedance.

• Single in-line (SIP) construction
for easy mounting

U Package

• Separated preamplifier and power
amplifier

9 PREAMP GROUND

• High output power

7

PREAMP OUTPUT

• Thermal protection

6

POWER AMP INPUT

PREAMP INPUT

• High input impedance

PREAMP vcc
COMPENSATION

• Low current drain
• Limited nOise behavior at radio
frequencies

2

POWER AMP vcc
POWER AMP OUTPUT

APPLICATIONS

1

POWER AMP GROUND

• Intercoms
• Tape recorders and players

TOP VIEW

• AM/FM radio
• Alarms
• Speech synthesizer output
• Telephone amplifier

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

9-Pin Plastic 51 P (SOT-11 OS)

-25°C to + 150°C

TDA1015U

TEST CIRCUIT

II

RIPPLE VOLTAGE
METER

R1
300k

i

TDA101S

r

C1

lOOnF

v,

November 6, 1966

C3

lOOnF

7-267

853-0915 86391

Signetics Linear Products

Product Specification

1 to 4W Audio Amplifier With Preamplifier

TDA1015

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

RATING

UNIT

Vee

Supply voltage

18

V

10M

Peak output current

2.5

A

PTOT

Total power dissipation

see derating curve, Figure 1

TSTG

Storage temperature range

-65 to +150

·C

TA

Operating ambient temperature range

-25 to +150

·C

tse

AC short-circuit duration of load during
sine-wave drive; Vee = 12V

100

hours

DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL

UNIT

PARAMETER
Min

Vee

Supply voltage range

IORM

Repetitive peak output current

ITOT

Total quiescent current at Vcc = 12V

Typ

3.6

14

Max

18

V

2

A

25

mA

AC ELECTRICAL CHARACTERISTICS TA = 2S·C; Vee = 12V; RL = 4n; f = 1kHz, unless otherwise specified; see also Figure 2.
LIMITS
PARAMETER

SYMBOL

UNIT
Min

Typ

Max

Po
Po
Po
Po

AF output power at dTOT = 10% 1 with bootstrap:
Vee = 12V; RL = 4n
Vee = 9V; RL = 4n
Vee = 6V; RL = 4n
Vee = 12V; RL = 4n without booststrap

4.2
2.3
1.0
3.0

W
W
W
W

AVI
AV2
Av TOT

Voltage gain:
Preamplifier2
Power amplifier
Total amplifier

23
29
52

55

dB
dB
dB

dTOT

Total harmonic distortion at Po = 1.5W

0.3

1.0

%

B

Frequency response -3dB3

15

kHz

Izl1 1
Izl21
Iz01 1

Input impedance
Preamplifier4
Power amplifier
Output impedance preamplifier

VO(RMS)

Output voltage preamplifier (RMS value) dTOT < 1 %2

Vn(RMS)

Noise output voltage (RMS value)5
Rs = On
Rs = 10kn
Noise output voltage at f = 500kHz (RMS value)
B = 5kHz; Rs = on

RR

Ripple rejection 6 f = 100Hz

Vn(RMS)
Vn(RMS)

49

60Hz
100

200
20
1

kn
kn
kn

0.8

V

0.2
0.5

mV
mV

8

IlV

38

dB

NOTES:
1. Measured with an ideal coupling capacitor to the speaker load.
2. Measured with a load resistor of 20kQ.

3.
4.
5.
6.
7.

Measured at Po = lW; the frequency response is mainly determined by Cl and C3 for the low frequencies and by C4 for the high frequencies.
Independent of load impedance of preamplifier.
Unweighted RMS noise voltage measured at a bandwidth of 60Hz to 15kHz (12dB/octave).
Ripple rejection measured with a source impedance between 0 and 2kll (maximum ripple amplitude: 2V).
The tab must be electrically floating or connected to the substrate (Pin 9).

November 6, 1986

7-268

Product Specification

Signetics Linear Products

TDA1015

1 to 4W Audio Amplifier With Preamplifier

HEATSINK DESIGN
Assume Vee
maximum.

,~J=l
r-....

-25 0

()JA

+100

+1110

Figure 1. Power Derating Curve

r.-~----~~----~------~~~-----------9+

+010
88O,..F

A3

4.7

C5
t8nF

Figure 2. Circuit Diagram of a 1 to 4W Amplifier

40

20

/'

V/

o

o

10

20

30

Figure 3. Total Quleacent Cu"ent aa a Function of Supply Voltage

November 6, 1986

= 4r!;

TA

= 45'C

+ ()TABH + ()HA = - - 1.B

Where ()JA of the package is 45'C/W, no
external heatsink is required.

T.(°C)

fj

= ()JTAB

= 5B'C/W

"rr I'-~
+110

RL

The maximum sine·wave dissipation is 1.BW.
150-45

"WJT~I'-1\

o

= 12V;

7·269

Vee

Signetics Linear Products

Product Specification

1 to 4W Audio Amplifier With Preamplifier

10

v

I=~M

cCt: I

7.5

9l i

I
I
I
I
I
I

~

I
2.5

I
I

10

'~

1=I~Hz

~P

r-

40

V

1OQ'Hz

r-..

12V

-10

ilb

o

60

1

I

I
I
I

TDA1015

10- 2

10

20

-20
10

10'

11)3

o

10'

1

10

FREQUENCY (Hz)

R2(k2)

NOTE:

NOTES:

Po Relative to OdS == 1W; Vee"" 12V; RL ==

_ _ With Bootstrap;
- - - - Without Bootstrap;
f "" 1kHz; typical values.

NOTE:
Rs = 0; Typical Values.

Figure 6. Voltage Gain as a
Function of Frequency

Figure 8. Ripple Rejection as a
Function of R2 (see Figure 2)

10

600

The available output power is 5% higher when
measured at Pin 2 (due to series resistance of
Cl0).

Figure 4. Total Harmonic Distortion as
a Function of Output Power Across RL

4n.

r-. b

Rs=B.2kQ

7.5
400

RL =4Q

II II

200

VV

o

:~ ~
o

l!

~V

o
10

TYP

102

10'

15

20

VCc(V)

Po"" 1W; Vee = 12V; AL = 4!1

o

1

10
R2(k2)

NOTE:
Measured according to A-Curve; capacitor C5 is
adapted for obtaining a constant bandwidth.

Figure 7. Total Harmonic Distortion as
a Function of Frequency

NOTES:
1. dTOT "" 10%; Typical Values.
2. The available output power is 5% higher when
measured at Pin 2 (due to series resistance of
Cl0).

Figure 5. Output Power Across RL as a
Function of Supply Voltage With
Bootstrap

November 6, 1986

10'

FREQUENCY (Hz)

NOTE:

10

I"

1"-

2.5

8Q

2.5

~
~s=O

7-270

Figure 9. Noise Output Voltage as a
Function of R2 (see Figure 2)

Signetics Linear Products

Product Specification

1 to 4W Audio Amplifier With Preamplifier

TDA1015

60

-

l'

A

'\

~ r--

40

20

\

1\
10-1

o
10

FREQUENCY (MHz)

NOTE:
Curve a: total amplifier; curve b; power amplifier;
B "" 5kHz; Rs "" 0; typical values.

1

10
R2(1 V1Q. then 111 must be :;;;;; 10mA.
2. Closed-loop vollage gain can be chosen between 32 and 56dB (BTL), and is delermined by external components.
3. Frequency response externally fixed.
4. The inpul impedance in Ihe lesl circuil (Figure 3) is typically 100kU.
5. Supply vollage ripple rejection measured wilh a source impedance of oU (maximum ripple amplilude: 2V).
6. Oulpul power is measured direclly at the output pins of the Ie.
7. Closed-loop voltage gain can be chosen between 26 and 50dS (stereo), and is determined by external components.
8. A resistor of 56kft between Pins 3 and 7 to reach symmetrical clipping.
9. Wilhoul boolslrap the t OOpF capacilor between Pins 5 and 6 (or 8 and 9) can be omilled. Pins 6, 8 and 10 have 10 be inlerconnected.

November 14, 1986

7-278

Signetics Linear Products

Product Specification

2 X 12W Audio Amplifier

TDA1510

lOOk

lOOk

~~~-O~~~----+------1~--~--OVcc

.);(1)

.,.-I

..L

100p,F

+

4.7

lOOk

lOOk

4.7p.F
+
2k

Figure 2. Test and Application Circuit Bridge-Tied Load (BTL)

lOOk

lOOk

r-~~-o-1~~---+------'----1~~Vcc

~(1)
...l..

TDA1510

lOOk

lOOk

O.1/-tF
lk

lk
4.7H

+
4.7JJ.F

Figure 3. Test and Application Circuit Stereo Mode

November 14, 1986

7-279

•

Signetics

AN1491
Car Radio Audio Power
Amplifier up to 24W With the
TDA1510

Linear Products

Author: F. A. Peiser
The TDA 1510 is a power amplifier for car
radio applications. It contains two identical
amplifiers which can be used for stereo or
BTL applications. The circuit consists of a 13lead SIP-to-DIP plastic power package (SOT141B) with a 0Jc<,3·CfW.
Car radio ICs require protection from hostile
environmental conditions. Therefore, several
protection circuits are built-in:
• AC short-circuit to ground
• Power supply overvoltage protection
• Thermal shutdown
• Low offset voltage between the two
outputs (important in BTL)
• Large open-loop gain
• Good ripple rejection
• Low standby current

CIRCUIT DESCRIPTION
General
The TDA1510 contains two identical amplifiers with differential input stages. It can be
used for stereo or bridge applications.

Signal Path
The collectors of the non-inverting PNP input
transistors are coupled to the Class A driver
stages which drive the Class B output stages.
The Class A driver transistors are frequency-

February 1987

limited by a Miller capacitor. This improves
the stability and overall noise behavior.

transistor breakdown voltage is thereby increased to VCER "" 50V.

Protection Circuits

Thermal Shutdown
To safeguard the circuit against high temperatures, a thermal shutdown protection circuit
has been built into both amplifiers. When the
die temperature exceeds 150·C, a transistor
begins to turn on and thereby decreases the
drive current to the power transistors.

SOAR Protection
To improve the reliability during overdrive
conditions and short-circuiting, both amplifiers have a Safe Operating Area Region
(SOAR) protection circuit for the upper output
stage. The base current of the output transistor is limited, based on the voltage and
current applied to the output transistor. The
protection area lies between 5AfOV and OAf
20V, thus limiting the signal excursion of
these stages to its allowable boundaries including AC short-circuiting to ground. When a
continuous short-circuit condition exists, the
chip temperature can rise above 150·C. At
that point, the thermal shutdown circuit becomes operative.

Special attention has been paid to the layout
of the output transistors to avoid current
crowding.
Power Supply Overvoltage Protection
The power supply overvoltage protection circuit is activated when the difference between
output voltage and Vcc is about 18V. Then, a
low impedance is switched across the base
and emitter of the upper Darlington output
transistor. This offers a low impedance between base and emitter. The upper Darlington

7-280

Special Features
A special feature of the TDA1510 is the low
current ( <, 2mA) standby switch option. Because of the low switching current
( <, O.8mA), an inexpensive switch can be
used.
This switch must be connected between Pin
11 and the positive supply line. It can also be
used as a mute facility by disconnecting Pin
11 from the supply voltage.
Both amplifiers have bootstrap facilities at
Pins 6 and 8. When these pins are not used,
the internal bootstrap resistors have to be
short-circuited by connecting Pins 6 and 8 to
Vec·
To optimize the output voltage for maximum
output power without bootstrap, a resistor of
56kQ must be connected between Pin 3 and
common ground.
The supply ripple voltage can be smoothed
by decoupling Pin 3 to ground.

Signeties Linear Products

Car Radio Audio Power Amplifier
up to 24W With the TDA1510

AN1491

BOOSTER APPLICATION
Principle of BTL
The output power of an amplifier is determined by the supply voltage. the loudspeaker
impedance. and the voltage losses in the
output stage. Higher output power in car
radios can be obtained by:
a) decreasing the loudspeaker impedance:
(two speakers in parallel)

R3

R7

RS

B

A

b) a bridge-tied load (BTL) circuit.
Decreasing the loudspeaker impedance far
below 2n is impractical because of high
losses in the loudspeaker wires and the high
capacitance values of the output electrolytics.
The only practical car radio circuit solution for
higher output powers is BTL operation.
The basic principle of the BTL circuit is shown
in Figure 1. This figure shows only the output
stages. Both channels are antiphase driven.
During the first half-period of the sine wave
excursion T 1 and T4 are conducting. and in
the second half-period T2 and T3 are conducting.
The output swing across the load resistor has
a peak-to-peak amplitude of two times Vee.
The ideal average output power when clipping equals (Vec)2

2
POIDEAL =~

(1)

At Vee = 14.4V and RL = 4n POIDEAL = 26W
Because of voltage losses in the output stage
of the TDA1510. the practical measured output power is 24W at d = 10% and 18W at
d= 0.5%.

The AC sine wave Va across the load is
IVoll + IV021.
The overall voltage gain becomes:
Av

Assuming point A as virtual ground. the noninverting amplifier 1 multiplies the input signal

5

= - ( :: ) •VI

2.

3.

4.

5.

7.

Filter C9 - Rs must be as close as possible to Pin 13 and the input ground. The
specific filter is necessary to improve the
overall stability.
The supply decoupling capacitors
ClO - C l l must be mounted as close as
possible to Pins 10 and 7.
The supply ripple smoothing capacitor C2
and capacitor C8 must be connected to
the input ground.
To avoid ground loops. the input and
output ground must be kept separate.
For stability. it is recommended that a
22n resistor with short leads be placed in
series with Pin 11.
The inputs are very sensitive to interferences and must be shielded from the rest
of the circuit.

Performance Measurements
In the application circuit of Figure 2. several
measurements are made. Unless otherwise
specified. the measurements are made at
Vee = 14.4V; RL = 4n; f = 1 kHz and
TA = 2SoC. The supply wires to the DC voltage source are a twisted-pair.

(3)

Output voltage - The output voltage. VA.
measured between Pins 5-7 and 9-7 as a
function of Vee. is given in Figure 4.
The offset voltage between Pins 5 and 9 is
typically 2mV (maximum limit: 50mV).
Output power - The output power as a
function of Vee for d = 0.5% and d = 10% is
given in Figure S.
Harmonic distortion - The distortion as a
function of the output power at f = 1kHz and
f = 20kHz is given in Figure 6. In Figure 7 the
distortion as a function of frequency is given
at Po= lOW.
Input impedance - The input impedance is
mainly determined by resistor Rl (see Figure
2) In this application. Rl = 100kn. To minimize offset voltage. it is necessary that
Rl = R3 and R2 = R7. For resistor values
higher than 100kns. the offset voltage can
increase due to differences in base currents.
Voltage gain - Previously it was derived
that the closed-loop amplification in BTL
equals:

In this application Av "" 100 X = 40dB.
The open-loop gain of the TDA 1510 is 80dB.
It is possible to reduce the voltage gain down
to 32dB (without instability) by increasing RS.
Frequency characteristic - In Figure 8 the
relative voltage gain. Av. is given as a function of the frequency (reference level
Po= 2.4W).
Power bandwidth - The relative output
power as a function of the frequency for
d = O.S% and d = 10% is given in Figure 9.
Power diSSipation - The power dissipation
as a function of the output power is given in
Figure 10.
For a worst-case sine wave dissipation of
11.8W. the external heatsink must have a

NOTE,
* Since point '8' is a virtual input for amplifier 2.

February 1987

(S)

Design Criteria

A part of the output signal. V01-.i.e .•

V02 = -( : : ) • ( R3: RS ) • ( R3:SRS )Vl

(4)

The basic application circuit diagram is given
in Figure 2.
Important design criteria of the printed circuit
board:
1. The Boucherot filters C4 - R4 and Cs - R6
must be mounted as close as possible to
the output Pins 5 and 9 and ground (Pin
7).

6.

R3 + R5 '
is amplified by inverting amplifier 2 with a
factor R7 IRS.· For maximum output voltage.
R3 and R7 must have equal values.
R3 + R5
In this case Val = - - _ . VI and because
R3 = R7.
R5
(2)

VI

R7
R7
In practice. 2 • RS~I. so Av = 2 • RS

VI by a factor ( R3 :5R5 )

Val ·R 5

IVoll + IV021

VI

R7 + RS R7
R7
=~+RS=2· R5+ 1

Amplification
The series drive principle of the BTL amplifier
can be seen from the circuit that follows.

Va

= - = -=-'---=-

Quiescent current consumption - In Figure 3 the total quiescent current consumption
is given as a function of the supply voltage
Vee. The maximum guaranteed value at
Vee = 14.4V is 1SOmA.

7-281

•

I

Signetics Linear Products

Car Radio Audio Power Amplifier
up to 24W With the TDA1510
thermal resistance of 4.4°G/W (for derivation
see Appendix I).
Supply voltage ripple rejection (SVRR) The SVRR as a function of the frequency is
given in Figure 11.
Noise - The noise output voltage with
Rs = 10kn, and measured according to the
lEG 179 A-curve, is 250/J.V.
Stability - The TDA 1510 is stable for each
kind of load, down to 32dB.

STEREO
The Stereo Application
The basic stereo application circuit diagram is
given in Figure 12.
Important design criteria for the layout of the
stereo print are the same as those for the
BTL print regarding Boucherot filters, supply
decoupling capacitor and the capacitor for
the supply voltage ripple rejection.

Performance Measurements
In the application circuit of Figure 12 several
measurements are made. If not otherwise
specified, the measurements are made at
Vcc = 14.4V; R1 = 4n; f = 1 kHz and
TA = 25°G.
Quiescent current and output voltage The quiescent current consumption is identical to that given for the BTL circuit (see
Figure 3). The same holds for the output
voltages at Pins 5 and 9 (see Figure 4).
Output power - The output power versus
the supply voltage is given in Figure 13 for
RL = 1.6n, 2n, 3.2n and 4n for a constant
distortion level of 10%.
In Figure 14 the same characteristics are
given for 0.5% distortion.
Using the circuit without bootstrap capacitors
Ga and G7, the output voltage must be cor-

February 1987

AN1491

rected to have symmetrical clipping. To do
this a 56kn resistor has to be connected
between Pin 3 and the input ground; Pins 5
and B must be connected to + Vcc.
The output power at the output pins is now
5.7W (4n load) and 10.5W (2n load).
Distortion - In Figure 15 the distortion as a
function of the output power is given for
RL = 4n at 1 and 20kHz.
The same characteristics are given in Figure
16 for RL = 2n.
Input impedance - The input impedances
are mainly determined by resistors Rl and
R5.
In this application R1 = 100kn (see Figure
12).

Noise - The noise output voltages, measured according to lEG 179 A-curve are 90llV
and 170/J.V at Rs = 0 and 10kn, respectively.
Channel separation - The channel separation at Po = 1Wand Rs = 10kn is 60dB.
Stability - The TDA 151 0 is stable for each
kind of complex load down to 26dB of gain.

APPENDIX
Heatsink Design
The TDA1510 has a BJC of 3°C/W.
Assume: Vcc = 14.4V, RL
TAMAX = 60°C.

= 4n

and

From Figure 10 it can be seen that the
maximum sine wave power dissipation with a
4n load is '" 11.8W in BTL.

Voltage gain - The closed-loop voltage
gain is determined by the feedback resistors
R2 and R3 and R7 and RB, in this case: 40dB.
It is possible to reduce the voltage gain down
to 26dB (without instabilities) by increasing
R2 and RB.

The total required thermal resistance becomes:
150-60
BJA = - - = 7.6°C/W
11.B

Frequency characteristics - The voltage
gain Av as a function of the frequency at
Po = lW is given in Figure 17.

When using a thermal compound, BCH is
approximately 0.2°C/W,

Power bandwidth - In Figure lB the output
power is given as a function of the frequency
for d = 0.5% and 10%.
Power disSipation - The total power dissipation of the two channels as a function of
the output power per channel is given in
Figure 19 for RL = 2n and 4n.
The worst-case power dissipation in stereo is
the same as in the BTL circuit.
The external heatsink must also have a
thermal resistance of 4.4°G/W.
Supply voltage ripple rejection (SVRR) The SVRR of both channels is 55dB from
100Hz to 20kHz.

7-282

BJA = BJC + BCH + BHA

it follows:
BHA = 7.6 - (3 + 0.2) = 4.4°C/W
From these measurements it appears that the
maximum power dissipation with music drive
is about 75% of the worst-case sine wave
power disSipation. Then the maximum practical power dissipation becomes B.BoG/W with
a 4n load in BTL.
This gives:
150-60
BJA = - - = 10.2°C/W
B.B
and the heatsink thermal resistance:
BHA = 10.2 - (3 + 0.2)'" 7°C/W

Signetics Linear Products

Car Radio Audio Power Amplifier
up to 24W With the TDA1510

AN1491

INTERNAL CIRCUIT BLOCK DIAGRAM

.----1~----~----~------~------------~~--_i------~--~10

--,
t

11

I

12
'---+--1---013

.--------------"t-----vcc

v
NOTE:

I

(14.4)'

(Vccv2)'

--2-

POIDEAL = - R l-- ' - - 4 -

~

26W measured at f= 1kHz; d = 10% Po

= 24W

Figure 1. Output Stage BTL

February 1987

7-283

Signetics Linear Products

Car Radio Audio Power Amplifier
up to 24W With the TDA1510

AN1491

R2

R1

S,
Vee

J

C2
R9

11

10

C1

V,

C8

12

O---;! ...........-+-1

~

13
C9
R8

.".

R7

R3

RS

C6

Figure 2. TDA1510 Bridge Application

120

TA

II ..

l100
ffi
§CJ

S
8

~

~

Rb

+2S'C
~

\01<1\

~'~---+----~----r-~'~"9'"

Lr---~~--t---j-------j

v

80

Lf-----f-"~~I===--r=-----j

V

60

-.,:,---+-----;,---;,----;

V

40

SUPPLYVQLTAGE~

-2

w

~g

.....

-3

10'

102

10"'

70

z

0:

102

10'

"

40

w

~

30

~

20

g
8:
iJ!

0.1

1

10

100

FREQUENCY (kHz)

Figure 11. Supply Voltage Ripple
Rejection vs Frequency

February 1987

lOS

o

2.5

5

7.5

10 12.5 15 17.5 20 22.5

OUTPUT POWER ('II)

Figure 10. Power Dissipation
vs Output Power

I

Vcc=14.~I~RL =4Q,Rs=OQ

50

10'

Figure 9. Power Bandwidth

60

W

ii:

t---..

/

if
FREQUENCY (Hz)

Figure 8. Frequency Characteristic

......

II

I

10

FREQUENCY (Hz)

or

-2

r- i'--

-3

10

:s

V

Po "kHz)=24W

-1

::>
0

-4

V~C=j4.4V:R)4Q

12

IIIIII

d=1O%

w

~

~
iil

Po "kHz)=18W
d=O.S%

10'

FREQUENCY (Hz)

Figure 6. Total Harmonic Distortion
vs Output Power

Figure 5. Output Power
vs Supply Voltage

10'

102

OUTPUT POWER ('II)

7-285

Signetics Linear Products

Car Radio Audio Power Amplifier
up to 24W With the TDA1510

AN1491

R1

RS

C1

12

v, o---j ~_-I--I

C11

I-r--.......--I/---O V,

TDA1510

13

R3

R7

R8

R2

C10

C2

Figure 12. TDA 151 0 Stereo Application

20

12
f=1kHz,d=1O%

J/

16

RL=22.11"

~ 14
;

12

~

10

10

d=0.5%
f=1kHz

RL -1.6~

/.V

>J.
~I?'

'/
~

'"

~

~ 'd

RL=42

~~ ~~ .....
::>'"

:::>'

0

.I A r

IY /
RL -a22

I
o

r2~

RL=1.82J

18

A
~

~~

RL =32Q

RLt2

6789101112131415161718

4681012141618

POWER SUPPLY VOLTAGE (V)

POWER SUPPLY VOLTAGE (V)

Figure 13. Output Power
vs Supply Voltage

February 1987

Figure 14. Output Power
vs Supply Voltage

7-286

Vc~~~~J.~:~~~

lz

g

I<

~

0.8

20kHz 1kHz

~

0.6

l-

!Ii::<

0.4

f--

lE

~

0.2

10- 1

10"

10'

OUTPUT POWER (W)

Figure 15. Total Harmonic Distortion
vs Output Power

Signetics Linear Products

Car Radio Audio Power Amplifier
up to 24W With the TDA1510

Vcc..'~AV,R~~~'Q

~

Vee "",14.4V, RL =4Q

z

/

0

Ii

~

~

o.a

1kHz

20kHz

Po=1W

0••

:s

-1

~ -2~+H~-rH*mr++Hffi*-hH~

~

.55

-2

g~ -3ri+fi~-rH*mr++Hffi*-hHfflffl

0,4

0,2

r-..
yP

a::
w

-3

0

-4

t10-'

IE

I:s -1riTn~-rH*mr++Hffifr-hH~
z

0

I:c
~

AN1491

10'

10'

10

OUTPUT POWER (W)

Figure 16. Total Harmonic Distortion
vs Output Power

10'

11)3

FREQUENCY (Hz)

Figure 17. Frequency Characteristic

10'

10

10S

FREQUENCY (Hz)

Figure 18. Power Bandwidth

VC~=1~4V,I=1~HZ

/

~

I""--

r--.. RL 122

/

--

......
I'R(4

2

1

024681012
OUTPUT POWER (W)

Figure 19. Total Power Dissipation
VB Output Power Per Channel
NOTE:
Originally published as Report No. NBA8107, N.V. Philips Application Laboratory, December 17, 1981, Nijmegen, The Netherlands.

February 1987

7-287

•

TDA1512

Signetics

12 to 20W Audio Amplifier
Product Specification

Linear Products

DESCRIPTION

FEATURES

The TDA1512 is a monolithic integrated
hi-fi audio power amplifier designed for
asymmetrical power supplies.

• Thermal protection
• Low intermodulation distortion
• Low transient intermodulation
distortion
• Built·in output current limiter
• Low Input offset voltage
• Output stage with low cross·over
distortion
• Single in·line (SIP) power
package

PIN CONFIGURATION
QU, U Packages
9

NON-INVERTING INPUT

8

l~C~U~'l~~rD

7 COMPENSATION

6

GROUND POTENTIAL

5

OUTPUT

4 POSITIVE SUPPLY (Vee)
3

APPLICATIONS

1

• Television
• Radio receivers
• Hi·fi power amp

~~ll'~T~6 TO PIN 8

2 RIPPLE REJECTION

l~~~ra~CMNPUT

TOP VIEW

ORDERING INFORMATION

TEMPERATURE
RANGE

ORDER CODE

9-Pin Plastic SIP (SOT-131B)

-25·C to +150·C

TDA1512U

9-Pin Plastic SIP-bent-to-DIP Plastic
Power (SOT-157B)

- 25·C to + 150·C

TDA1512QU

DESCRIPTION

ABSOLUTE MAXIMUM RATINGS

SYMBOL

RATING

UNIT

Vee

Supply voltage

PARAMETER

35

V

IORM

Repetitive peak output current

3.2

A

IOSM

Non-repetitive peak output current

5

A

PTOT

Total power dissipation

TSTG

Storage temperature

-55 to + 150

·C

TA

Operating ambient temperature

-25 to +150

·C

tsc

AC short-circuit duration of load
during full-load sine-wave drive
RL = 0; Vee = 30V with RI = 4Q

100

hours

typo 3

·C/W
·C/W

OJMB

Thermal resistance
from junction to mounting base

November 6, 1986

See derating curve Figure 1

';;4

7-288

853-0917 86393

Product Specification

Signetics Linear Products

TDA1512

12 to 20W Audio Amplifier

THERMAL
SHUTDOWN

5
(OUTPUT)
9O---~-----------+--

__________

~

(-INPUT)

1o----'f--I:

(.,NPUT)

CURRENT
LIMITER

Simplified Internal Circuit Diagram

November 6, 1986

7-289

Signetics Linear Products

Product Specification

12 to ·20W Audio Amplifier

TDA1512

DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL

UNIT

PARAMETER
Min

Vce

Supply voltage range

ITOT

Total quiescent current at Vee = 25V

Typ

15

Max

35

V
mA

65

AC ELECTRICAL CHARACTERISTICS vee = 25V; RL = 4n; 1= 1kHz; TA = 25°C; measured in Test Circuit 01 Figure 2,
unless otherwise specilied.
LIMITS
SYMBOL

UNIT

PARAMETER
Min

Po

Output power
sine-wave power at dTOT = 0.7%
RL =4n
RL =8n
music power at Vee = 32V
RL = 4n; dTOT = 0.7%
RL = 4n; dTOT = 10%
RL = 8n; dTOT = 0.7%
RL = 8n; dTOT = 10%

B

Power bandwidth; -1.5dB; dTOT = 0.7%

Avo
Ave

Voltage gain
open-loop
closed-loop

RIN

Input resistance (Pin 1)
Input resistance of Test Circuit (Figure 2)

VIN

Typ

Max

13
7

W
W

21
25
12
15

W
W
W
W
16

40Hz
74
30

dB
dB

20

kn
kn

16
210

mV
mV

100

Input sensitivity
for Po = 50mW
lor Po = 10W

kHz

Signal-to-noise ratio
at Po = 50mW; Rs = 2kn;
I = 20Hz to 20kHz; unweighted

SIN

68

weighted; measured according to IEC 173 (A-curve)

dB
76

RR

Ripple rejection at I = 100Hz

50

dTOT

Total harmonic distortion at Po = 10W

0.1

Ro

Output resistance (Pin 5)

0.1

November 6, 1986

7-290

dB
dB
0.3

%
n

Product Specification

Signetics Linear Products

12 to 20W Audio Amplifier

TDA1512

20

i

;-

'" ,

10

\

'\

,

'"
o

-25

\
"\

150

NOTES:

- - mounted on infinite heatsink.
- - - - mounted on heatsink of S"C/W

Figure 1. Power Derating Curves

r-~r-----------------------------------~--+v~

TDA1512

20k
THERMAL

PROTECTION

6.8pF

INPUT~ ..________~----~----------~
(Rs! -----.

+

I

680

CURRENT
LIMITER

20k

I~
Figure 2. Test Circuit

November 6, 1986

7-291

RL

I

Signetics Linear Products

Product Specification

12 to 20W Audio Amplifier

TDA1512

40r------r------,------,

o~

10

____

~

______

~

____

20

~

40

NOTES:

____ draT'" 0.7%.
- - - -dTOT '"

10%.

Figure 3. Ouput Power as a Function of the Supply Voltage; f

= 1kHz

W~l JJJJ
J

J II

1 kHz

0.75

~

~ 0.5

...

0.25

o
10-1

10

10'

Figure 4. Total Harmonic Distortion as a Function of Output Power

November 6, 1986

7-292

TDA1514

Signetics

40W High-Performance Hi-Fi
Amplifier
Product Specification
Linear Products

DESCRIPTION
The TDA 1514 integrated circuit is a hi-fi
power amplifier for use as a building
block in radio, TV and audio recorder
applications. The high performance of
the IC meets the requirements of digital
sources (e.g. compact disc equipment).
The circuit is totally protected, the two
output transistors both having thermal
and SOA protection. The circuit also has
a mute function that can be arranged to
operate for a period after power-on with
a delay time fixed by external components.
The device is intended for symmetrical
power supplies, but an asymmetrical
supply may also be used.
The theoretical maximum power dissipation with a stabilized power supply is
(Vee - VN)2/21T2RL = 19W, where Vee =
+ 27.5V, VN = -27.5V and RL = sn.

Considering, for example, a maximum
ambient temperature of 50°C and a
maximum junction temperature of
150°C, the total thermal resistance JA is
(150 - 50)/19 = 5.3°C/W. Since the
thermal resistance of the SOT-131A encapsulation is < 1SC/W, the thermal
resistance required of the heatsink is
< 3.SoC/W. Thus the maximum output
power, and therefore the music power
output, is limited only by the supply
voltage and not by the heatsink.

PIN CONFIGURATION
U Package

e

9

COMPENSATION

7

MUTe TIME CONSTANT

5

OUTPUT

3

BOOTSTRAP

2 GROUND
1

FEATURES
•
•
•
•
•
•

Thermal protection
Low THO
SOA protection
Mute time delay
Short·circuit protected
High power output

NON-INVERTING INPUT

8

INVERTING INPUT (FEEDBACK)

TOP VIEW

APPLICATIONS
•
•
•
•

Hi·Fi amplifier
Radio
Television
Motor driver

BLOCK DIAGRAM
+V~O-~r----------------------1------~-1~

VOST•

8

•

8 7

: • .----'-I-H

R2

880

November 6, 1986

7-293

853-0918 86394

Signetics Linear Products

Product Specification

40W High-Performance Hi-Fi Amplifier

TDA1514

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

9-Pin Plastic SIP (SOT-131A)

-25'C to +150'C

TDA1514U

40

IN~INIT~._

\

30

"-

HEATSINK

"-

1\
\

"-

HEATSlN~

~ 9Jc =3.8'C/W

10

~

o

\

"'- ~\

-25 0

150

Figure 1. Power Derating Curve

ABSOLUTE MAXIMUM RATINGS
RATING

UNIT

+Vee to -Vee

Supply voltage (Pin 6 to Pin 4)

60

V

VesTA

Bootstrap voltage (Pin 7 to Pin 4)

70

V

10

Output current (repetitive peak)

4.0

A

TA

Operating ambient temperature range

-25 to + 150

TSTG

Storage temperature range

-65 to +150

'c
'c

Po

Power dissipation

See Figure 1

tpR

Thermal shut-down protection time

1

hour

tse

Short-circuit protection time 1

10

min

VM

Mute voltage (Pin 3 to Pin 4)

7

V

SYMBOL

PARAMETER

NOTE:
1. Driven by a pink-noise voltage.
Symmetrical power supply: AC and DC short·circuit protected.
Asymmetrical power supply: AC short~circuit protected.

November 6, 1986

7-294

Signetics Linear Products

Product Specification

TDA1514

40W High-Performance Hi-Fi Amplifier

DC ELECTRICAL CHARACTERISTICS + Vce = + 27.5V; -Vee = -27.5V; AL = 8n; f = 1kHz; TA = 25°C, unless otherwise
specified.
LIMITS
SYMBOL

UNIT

PARAMETER

Min

Typ

+Vee to -Vee

Supply voltage range (Pin 6 to Pin 4)

15

IOMmax

Maximum output current (peak value)

3.2

ITOT

Total quiescent current

30

60

Po
Po
Po

Output power with THO
at Vee- VN = 55V
at Vee- VN = 44V
at Vee- VN = 32V

37

40
25

THO

Total harmonic distortion at Po

B
dV/dt

Slew rate

Ave

Closed-loop voltage gain2

Avo

Open-loop voltage gain

ZI

Input impedance 3

(S + N)/N

SIN related to Po

Vos

Input offset voltage

60

V

90

rnA

12.5

W
W
W

-80

dB

A

= -60dB:

= 32W
Intermodulation distortion at Po = 32W 1
Power bandwidth (- 3dB) at THO = -60dB

diM

Max

-90
-80

29.2

dB

20 to 25k

Hz

15

VIps

29.7

30.2

dB

85

dB

1

= 4mW4

Mn

80

dB
3

±IIO(8)

Input offset bias current

B+18

Input bias current

Zo

Output impedance

AA

Supply voltage ripple rejection at
ripple frequency = 100Hz;
ripple voltage (AMS value) = 500mV;
source resistance = 2kn

tM

Mute time 5

VM(on)

Mute on voltage (Pin 3 to Pin 4)

0

VM(off)

Mute off voltage (Pin 3 to Pin 4)

6

12TOT

Quiescent current into Pin 26

mV

0.2

1

pA

1

5

pA

0.1

n

70

dB

1.25

s
5
7

20

NOTES:
1.
2.
3.
4.

Measured with two superimposed signals of 50Hz and 7kHz with an amplitude relationship of 4:1.
The closed-loop gain is determined by external resistors and is variable between 20 and 46dB.
The input impedance in the test circuit is determined by the bias resistor R 1.
The noise voltage at the output is measured in the band 20Hz to 20kHz and source resistance Rs

= 2kn.

5. Determined by R4 and Cl.
6. The quiescent current into Pin 2 determines (with the value of R4) the minimum power supply voltage at which the mute function remains in
operation: +Vcc-VN=12TOT X R4+VM(ON)max'

November 6, 1986

7-295

V
V
pA

II

TDA1515A

Signetics

24W BTL Audio Amplifier
Product Specification

Linear Products

DESCRIPTION
The TDA1515 is a monolithic integrated
class-B output amplifier in a 13-pin single in-line (SIP) plastic power package.
The device is primarily developed for car
radio applications, and also to drive lowimpedance loads (down to 1.6n). At a
supply voltage Vee = 14.4V, an output
power of 21W can be delivered into a
4n BTL (Bridge-Tied Load), or, when
used as stereo amplifier, it delivers
2 X 11W into 2n or 2 X 6.5W into 4n.

FEATURES
• Flexibility in use - mono BTL as
well as stereo
• High output power
• Low offset voltage at the output
(important for BTL)
• Large usable gain variation
• Very good ripple rejection

PIN CONFIGURATION

• Internal limited bandwidth for
high frequencies
• Low standby current possibility
(typ. 1j.LA), to simplify required
switches; TTL drive possible
• Low number and small-sized
external components
• High reliability
• Load dump protection
• AC and DC short-circuit safe to
ground up to Vee = 18V
• Thermal protection
• Speaker protection in bridge
configuration
• SOAR protection
• Outputs short-circuit safe to
ground in BTL
• Reverse-polarity safe

o Package
1 INVERTING INPUT 1
2

NON-INVERTING INPUT 1

3

~~~~~~gLTAGE RIPPLE

4

LOUDSPEAKER PROTECTION

6

BOOTSTRAP 1

7

GROUND; SUBSTRATE

8

BOOTSTRAP 2

SUPPLY VOLTAGE (+VcC>
11

STANDBY SWITCHING
NON·INVERTING INPUT 2
INVERTING INPUT 2

APPLICATIONS
• Car radio applications
• Drive low impedance loads
• Stereo amplifier

BLOCK DIAGRAM
8

6

r-----~-----+----~------~--------------~----_r------~---o10

11

<

--,

•
I

12

'---j---t--o 13

LOUD·
SPEAKER
PROT.

4

November 14, 1986

7·296

9

853-0967 86554

Signetics Linear Products

Product Specification

24W BTL Audio Amplifier

TDA1515A

HEATSINK DESIGN EXAMPLE
20

Ul

The derating of 3"C/W of the encapsulation
requires the following external heatsink (for
sine·wave drive):

II I

16

Infinite
Heatalnk

~ 12

21W BTL (4Q) or 2 X llW stereo (2Q)
maximum sine wave dissipation: 12W

tlC_A

TA = 65"C maximum

• K/W

6

~ 8
11 K/W

150-65
8HA = -1-2--3 = 4"C/W.

i'o

1\
i'o
o

2 X 6.5W stereo (4Q) maximum sine wave
dissipation: 6W

11\
-20

0

20

40

60 80 100 120 140 160
TA('C)

TA = 65"C maximum
150-65
8HA =--6--3 = 11"C/W.

Figure 1. Power Derating Curves

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

o to

13·Pin Plastic SIP (SOT·141B)

ORDER CODE

+70"C

TDA1515AD

ABSOLUTE MAXIMUM RATINGS
SYMBOL

RATING

UNIT

Vee

Supply voltage; operating (Pin 10)

DESCRIPTION

18

V

Vee

Supply voltage; non·operating

28

V

Vee

Supply voltage; during 50ms (load dump protection)

45

V

10M

Peak output current

6

A

Total power dissipation

see derating
curve Fig. 1

TSTG

Storage temperature range

-65 to +150

°C

Te

Crystal temperature

150

°C

AC and DC short·circuit safe voltage

18

V

Reverse polarity

10

V

PTOT

DC ELECTRICAL CHARACTERISTICS
SYMBOL

PARAMETER

MIN

Vee

Supply voltage range (Pin 10)

IORM

Repetitive peak output current

ITOT

Total quiescent current

V"
V"

Switching level 11: OFF
ON

lzOFFI

Impedance between Pins 10 and 6; 10 and B
(standby position V" < 1.8V)

TYP

6

MAX

UNIT

18

V

4

A

75

mA

1.8
3

V
V

100

kQ

75

IS8

Standby current at V 11 = 0 to O.BV

1

100

pA

Iso

Switch·on current (Pin 11) at V"  5kn if V11 > V10.
Closed-loop voltage gain can be chosen between 32 and 56dB (BTL), and is determined by external components.
Frequency response externally fixed.
The input impedance in the test circuit (Figure 3) is typically 100kn.
Supply voltage ripple rejection measured with a source impedance of on (maximum ripple amplitude: 2V).
Output power is measured directly at the output pins of the Ie.
Closed-loop voltage gain can be chosen between 26 and SOdB (stereo), and is determined by external components.
A resistor of 56kn between Pins 3 and 7 to reach symmetrical clipping.
Without bootstrap the 100"F capacitor between Pins 5 and 6 (8 and 9) can be omitted. Pins 6, 8 and 10 have to be interconnected.

November 14, 1986

kHz

=20Hz to 20kHz

NOTES:
1.
2.
3.
4.
S.
6.
7.
8.
9.

6
10

7-298

Signetics Linear Products

Product Specification

24W BTL Audio Amplifier

TDA1515A

+
lOOK

O.l/-lF

1K
4.7

Figure 3. Testl Application Circuit Stereo

November 14, 1986

7-299

Signetics

AN1481
Car Radio Audio Power
Amplifiers up to 20W With the
TDA1515

Linear Products

Application Note

Authors: F. Peiser
J. Sips
The TDA 1515 is a power amplifier for car
radio applications. It contains two identical
amplifiers which can be utilized for BTL or
stereo applications. The TDA1515 is available in a 13-lead single in-line plastic power
package with' 8Je of .;; 3°C/W.

thermal shutdown circuits become operative.
Special attention has been paid to the layout
of the output transistors to avoid current
crowding.

Car radios require protection from hostile
automotive environmental conditions; therefore, several. protection circuits are built into
the TDA1515:
• AC and DC short-circuit to ground
• Power supply over voltage

The power supply over voltage protection
circuit is activated when the difference between output voltage and Vee is about 1BV.
Then, a low impedance is switched between
the base and emitter of the upper Darlington
output transistor. The upper Darlington transistor breakdown voltage is thereby increased
to VeER"" 50V.

• Thermal shutdown
• Speaker protection in bridge
configuration

Power Supply Over Voltage
Protection

Thermal Shutdown

Other features of the TDA 1515 include:
• Low offset voltage
• Large gain selection range
• Good ripple protection
• Low standby current
• Standby control with TTL levels

To safeguard the IC against high temperatures, thermal shutdown protection circuits
have been built into both amplifiers. When the
die temperature exceeds 150°C, a transistor
begins to turn on and thereby decreases the
drive current to the power transistor. A second thermal shutdown protection circuit protects the output transistors against hot spot
temperatures.

CIRCUIT DESCRIPTION

Loudspeaker Protection in BTL

The TDA 1515 contains two identical amplifiers with differential input stages. It can be
used for stereo or bridge applications.

Signal Path
The collectors of the non-inverting PNP input
transistors are coupled to the Class A driver
stages which drive the Class B output stages.
The Class A driver transistors are frequencylimited by a Miller capacitor. This improves
the stability and overall noise behavior.

Protection Circuits
To improve the reliability where the overdrive
condition exists and when short circuiting,
both amplifiers have a Safe Operating Area
Region (SOAR) protection circuit for the upper output stage. The base current of the
output transistor is limited, based on the
voltage and current applied to the output
transistor. The SOAR lies between 5A/OV
and OAl20V. Due to the SOAR protection
circuit, it is possible to limit the signal excursion of these stages to their allowable boundaries. Therefore, AC and DC short-circuiting
to ground will not damage the device.
With continuous short circuit, the chip temperature can rise above 150°C. At that point, the
February 19B7

The loudspeaker protection in BTL starts
operating when the DC offset voltage between the output Pins 5 and 9 exceeds W.
An internal comparator circuit controls the
deviating DC output voltage. The maximum
DC current through the loudspeaker is therefore limited to a safe value for the speaker
(",,250mA for a 4n speaker).
Due to the RC time (about 1 second with
47J.IF) at Pin 4, the DC current-limiting protection circuit is inoperative during switching on
and short-circuiting for one second.

Special Features
A special feature of the TDA1515 is a mute
function. When Pin 11 is taken below 1.BV,
mute is on. When it is taken above 3V, mute
is off.
Both amplifiers have bootstrapping capabilities at Pins Sand B. When these pins are not
used, the internal bootstrap resistors must be
short-circuited by connecting Pins Sand B to
Vee. To avoid poor ripple rejection in the
standby mode, the bootstrap resistor is internally switched off. To optimize the output
voltage for maximum output power without

7-300

bootstrap, a resistor of 5Skn must be connected between Pin 3 and common ground.
The supply ripple voltage can be smoothed
by decoupling Pin 3 to ground.

BOOSTER APPLICATION
Principle of BTL
The principle of the BTL circuit is shown in
Figure 1. This figure shows only the output
stages. Both channels are antiphase driven.
During the first half-period of the sine wave
excursion, T 1 and T4 are conducting, and in
the second half-period T2 and T3 are conducting. The output swing across the load
resistor has a peak-to-peak amplitude of two
times Vee.
The ideal average output power at clipping
Vee 2
equals

2
Po ideal = - RL

(1)

At Vee =.14.4V and RL = 4n Po ideal = 2SW. Because of voltage losses in the
output stage of the TDA 1515 and due to
wiring of the board, the practical measured
output power on the board is 20.5W.
Measured on the pins of the IC, the output
power becomes 21W.

Amplification
The overall voltage gain in the amplification
circuit becomes:
IVoll+ IVoll1
Vo
Av=VI
RS
RS
-=2--+ 1
R5
R5

RS+R5

---> +

(assuming R3 = RS)

R5

(2)

RS
In practice 2- R5 »1,
RS
therefore Ay = 2 -R5'

(3)

Design Criteria
The basic application circuit diagram is given
in Figure 2.

Application Note

Signetics Linear Products

Car Radio Audio Power Amplifiers
up to 20W With the TDA1515

AN1481

AMPLIFICATION CIRCUIT

STEREO
The Stereo Application
The basic stereo application circuit diagram is
given in Figure 12.
DeSign criteria for the layout of the stereo
application are the same as those given in the
Design Criteria Section. Component leads are
as short as possible for the power supply
decoupling capacitor, and the capacitor for
the supply voltage ripple rejection.

Important design criteria of the PC board:
1. The Boucherotfilter C4 - R4 must be
mounted as close as possible between the
output Pins 5 and 9.
2. Filter Cg - R7 must be as close as possible
between Pin 13 and the input ground. The
specific filter is necessary to improve overall stability.
3. The supply decoupling capacitors
C10 - C11 must be mounted as close as
possible between Pins 10 and 7.
4. The supply ripple smoothing capacitor C2
and capacitor Cs must be connected to the
input ground.
5. Separate input and output grounds must be
maintained.
6. With the high input impedance at Pin 11, it
is recommended to decouple Pin 11 with a
100nF capacitor to ground to guarantee a
good standby switching behavior.

Performance Measurements
In the application circuit of Figure 2, several
measurements are done. If not otherwise
stated, the measurements are given at
Vee = 14.4V on the PC board connections;
RL = 4n; f = 1kHz and TA = 25'C.
The power supply wires are a twisted-pair.
a) Quiescent current consumption
In Figure 3 the total quiescent current
consumption is given as a function of the
supply voltage Vee. The maximum guaranteed value at Vee = 14.4V is 12SmA. In
standby position of S the quiescent current
is "'1 pA (.;; 0.2mA).
b) Output voltage
The output voltage measured between
Pins 5 - 7 and 9 - 7 as a function of Vee is
given in Figure 4. The offset voltage between Pins 5 and 9 is typically 2mV (maximum limit: 50mV).
c) Output power
The output power as a function of Vee for
d = 0.5% and d = 10% is given in Figure 5
(Power losses across the PC board are

February 1987

"'0.5W at d = 10% and "'0.25W at
d = 0.5% level and Vee = 14.4V).
d) Harmonic distortion
The distortion as a function of the output
power at f = 1kHz and f = 20kHz is given in
Figure 6. In Figure 7, the distortion as a
function of frequency is given at Po = 1W.
e) Input impedance
The input impedance is mainly determined
by resistor R1 (see Figure 2). In our application: 100kn. To minimize offset voltage,
it is necessary that R1 = R3 and R2 = Rs.
For resistor values higher than some
100k!1s the offset voltage can increase
due to differences in base currents.
f) Voltage gain
In the Applications section it is derived that
the closed-loop amplification in BTL equals:

In our application Av = 100 x (40dB). The
open-loop gain of the TDA 1515 is 75dB. It
is possible to reduce the voltage gain down
to 32dB (without instability) by increasing
R5.
g) Frequency characteristics
In Figure 8 the relative voltage gain Av is
given as a function of the frequency (reference level Po 10dB below 20W).
h) Power bandwidth
The relative output power as a function of
the frequency for d = 0.5% and d = 10% is
given in Figure 9.
i) Power dissipation
The power dissipation as a function of the
output power is given in Figure 10. For a
worst-case sine wave dissipation of
"'11.5W, the external heatsink must have a
thermal resistance of 4.6'C/W.
j) Supply Voltage Ripple Rejection (SVRR)
The SVRR as a function of the frequency is
given in Figure 11.
k) Noise
The noise output voltage with Rs = 10kn
and measured according to the IEC 179 Acurve is 250p.V.

7-301

Performance Measurements
In the application circuit of Figure 12, several
measurements are done. If not otherwise
stated, the results of the measurements are
given at Vee = 14.4V; R1 = 4n; f = 1kHz and
TA = 25'C. (Vee measured on the PC board
connections).
a) The quiescent current consumption and
output voltage are identical to those given
for the BTL circuit above.
b) Output power
The output power versus the supply voltage is given in Figure 13 for RL = 1.6, 2,
3.2, and 4n, respectively, for a constant
distortion level of 10%. (The power losses
due to the output electrolytic are about
0.3W, while the losses across the PC
board traces are'" 0.25W at Vee = 14.4V
and RL = 2n). In Figure 14, the same
characteristics are given for 0.5% distortion.
Using the circuit without bootstrap capacitors C3 and C7, the output voltage must be
corrected to have symmetrical clipping.
Therefore a 56kn resistor has to be connected between Pin 3 and the input
ground; Pins 5 and 8 must be interconnected to + Vee.
The output power at the output pins is now
5.3W (4n load) and 6.5W (2n load).
c) Distortion
In Figure 15 the distortion as a function of
the output power is given for RL = 4n at 1
and 20kHz, while in Figure 16 it is shown
for RL = 2n. The total harmonic distortion
versus frequency for RL = 2 and 4n is
given in Figure 17.
d) Input impedance
The input impedances are mainly determined by resistor R1 and R5 (100kn).
e) Voltage gain
The closed-loop voltage gain is determined
by the feedback resistors R2 - R3 and
R7 - Rs, in this case 40dB. It is possible to
reduce the voltage gain down to 26dB
(without instabilities) by increasing R2 and
Rs·
f) Frequency characteristics
The relative voltage gain as a function of

Signetics Linear Products

Application Note

Car Radio Audio Power Amplifiers
up to 20W With the TDA1515
the frequency at Po = 1W is given in Figure
18.
g) Power bandwidth
In Figure 19 the relative output power is
given as a function of the frequency for
d=1% and 10%.
h) Power dissipation
The total power dissipation of the two
channels as a function of the output power
per channel is given in Figure 20 for RL = 2
and 4ft The worst-case power dissipation
in stereo is the same as in the BTL circuit.
The external heatsink must also have a
thermal resistance of 4.6°C/W.

AN1481

i) Supply Voltage Ripple Rejection (SVRR)
The SVRR as a function of the frequency is
given in Figure 21.

From Figure 10 it follows that the maximum
sine wave power dissipation with a 4Q load is
"'11.5W in BTl.

j)Noise
The noise output voltages, measured according to IEC 179 A-curve are 90 and
170p.V at Rs = 0 and 10kQ, respectively.

The total required thermal resistance becomes:

k) Channel separation
The channel separation at Po = 1W,
f = 1kHz and Rs = 10kQ is 60dB.

150-60
()JA = - - - = 7.8°C/W
11.5

When using thermal compound ()CH is about
0.2°C/W it follows:

APPENDIX I
Heatsink Design
The TDA1515 has a ()JC of 3°C/W

()HA = 7.8 - (3 + 0.2) = 4.6°C/W

Assume: VCC = 14.4V, RL = 4Q, TA = 60°C.

INTERNAL CIRCUIT BLOCK DIAGRAM

~~=I----r------1-------r-----r---------'-------r------,----o10

12

'---t--+---G13

February 1987

7-302

Application Note

Signetlcs Linear Products

Car Radio Audio Power Amplifiers
up to 20W With the lDA 1515

AN1481

r-----------------~~---------Vp

(14.4)'
NOTE:
(VccN2)' - 2 Po ideal .. - - = - - ... 26W (measured at f"" 1kHz; d "" 10%; PO'" 20.5W)
AL
4

Figure 1. Output Stage BTL

Al

R2

IQ

il

C12

C1

V1o-j

r-

S

=:=cs

-:;:

3

11

±

10

2

12
TDA1515

I

1

II

r--....

./
6

13

C8

1
C9

5

8

9

RL
~

C3

" ~C4 z:::! R4

R5

ji-

Figure 2. TDA 1515 Bridge Application

7-303

7

C7

R6

R3

February 1987

Cl0

AT

-=-

Signetlcs Linear Products

Application Note

Car Radio Audio Power Amplifiers
up to 20W With the TDA1515

120

AN1481

12

30

10

25

f

V ...

v-

~

1l0"

.....
!;

o -"
o

./

::>
0

1/

20

./

>

V

10

12

14

16

18

o

20

4

V

~

0

/

1•

::>

!;

10

0

/'

V1~1I\4.4~ ~ I ~ ~~

~

I~~~z

•

~ 0.6

10

12

14

16

18

o

20

~

~V

V

10

6

12

14

16

18

SUPPLY VOLTAGE (V)

Figure 5. Output Power
vs Supply Voltage

Figure 4. Output Voltage
vs Supply Voltage

Figure 3. Quiescent Current
vs Power Supply Voltage

l

8

SUPPLY VOLTAGE (V)

POWER SUPPLY VOLTAGE (V)

~ 0.8

.....
..

.~

lL 'A=O.5%

UJ

Vo

p

20

II:

/

d=l~~

V
8

4

~

./

UJ

~ lkHZ,IRL = 4~

Yee - 1•.'Y. RL = 4ll,
Po = 2W AT 1kHz

~ 111111

1kHz

~

:i: 0.4

~

;l

0.2

~

/

o

10-1

100
10'
OUTPUT POWER (W)

O~~~~~~~UW~~~

10'

10

10'

1()3
10'
FREQUENCY (Hz)

10'

10

10'
10'
104
FREQUENCY (Hz)

OPOS610S

Figure 6. Total Harmonic Distortion
vs Output Power

Figure 7. Total Harmonic Distortion
vs Frequency

.,_

2

d

1-

r

/"

= 10%

0

1

2

.. -3

8

I---6-l-ttttHI-+l-ttttHI-+H-HtHI-+t-H1tfl

A
1-"-I-H-HttIt-I-H-ItllIt-f-tl-tttlit-f-tl-/IItH

6

I'--- t'....

Lo

I

103
104
FREQUENCY (Hz)

10'

0

t~ lIJl!ll. R~ Jlll~~1 = o~
I-

i3

II:

/

~
10'

70

l!.

i

50

~
"g

40

it
w

4

10

Figure 8. Frequency Characteristic

Vee

~

= 14.4V. RL = 40, f = 1kHz

I

1

I

10

15

20

OUTPUT POWER (W)

25

8:
iii:

30
0.1

1\

1\
10

100

FREQUENCY (kHz)
OPOB650S

Figure 9. Power Bandwidth

February 1987

Figure 10. Power Dissipation
vs Output Power

7-304

Figure 11. Supply Voltage Ripple
Rejection vs Frequency

Signetics Linear Products

Application Note

Car Radio Audio Power Amplifiers
up to 20W With the TDA1515

AN1481

RS

Rl

C~4_ -o-_s~-......- ......t -......-ovcc
....L.

:r.

12

Cl

Cll

.......,I-+"-+-if--ov~

v" o--j 1--4--=+--1"""'"
TDA1S1S

13

C7
R7

R3
C9

R8

R2

RL

Cl0

C2

Figure 12. TDA1515 Stereo Application

20
f

18
16

~

l'

'"

12

..~

= 1kHz. d = 10%

C--tR~ J2~

10

.....,~

I I I

!:i

RL = 40_

~

o

~
o

I
...::V\

= 1.61l
RL = 3.21l ...
RL

~;(

~

II

//

k'

~;..-

~~
po

o

6

10

12

14

16

18

SUPPLY VOLTAGE (Vee)

SUPPLY VOLTAGE (Y)

Figure 13. Output Power vs Supply Voltage

February 1987

Figure 14. Output Power vs Supply Voltage

7-305

Signetics Linear Products

Application Note

Car Radio Audio Power Amplifiers
up to 20W With the TDA1515

Vee ;1;'~.4V, ~~I~I~li

l

r

1

~

20kHz

a

11 1

v~~ ~1~~.4J. ~~I~lIkn

i!.
z

~

2LU II\kl

~ 0.8

1kHz

AN1481

r

1S

~ 0.6

..

a

:r

t! 0.2

f:!

RL =2n

10'

10-1
10"
10
OUTPUT POWER (W)

OUTPUT POWER (W)

V
v.:

~ 0.2

:r

r-

0.2

100

~ OA

i
r-

....
g
...

10-1

~

II 0.3

['\

:r

"

....

='~~

zO.5

1S

!i 0.4

~ 0.4

Po

1

g
...

RL -4n

0.1

10

102

111

103
104
FREQUENCY (Hz)

OPOB7DOS

Figure 15. Total Harmonic Distortion
vs Output Power

Figure 16. Total Harmonic Distortion
vs Output Power

Figure 17. Total Harmonic Distortion
vs Frequency

Vee = 14.4V. RL - 4li.
Po'" 1W AT 1kHz

Vee:: 14.4V, f = ,!!.H.,!-

V

-1~H4~~~~~~~-+~~

~ -3i--'~~~~~~~~-+~~

102

103
10'
FREQUENCY (Hz)

~20

i'

I

L2 i--'H4W~~~~~~-+~1\Hll
10

RL

~

-"'"
10

102

103
10'
FREQUENCY (Hz)

I-- ~L=4n
,

o
o

10

12

POWER OUTPUT (W)
OP06730S

Figure 18. Frequency Characteristic

~

~

70

vJ= UW1t

60

14,!.l~llllln

V

OJ
a:

i

=

Figure 19. Power Bandwidth

r'\

50

w

"g~
~

8:

~

40

V

30
100

1000

10,000

100,000

FREQUENCY (Hz)

Figure 21. Supply Voltage Ripple
Relection vs Frequency

February 1987

7·306

Figure 20. Total Power Dissipation
vs Output Power per Chsnnel

TDA1520A

Signetics

20W Hi-Fi Audio Amplifier
Product Specification

Linear Products

DESCRIPTION

FEATURES

The TDA 1520A is a 20W hi-fi audio
power amplifier designed for asymmetricalor symmetrical power supplies.

• Low input offset voltage
• Output stage with low cross-over
distortion
• Single in-line (SIP) power
package
• AC short-circuit protected
• Very low internal thermal
resistance
• Thermal protection
• Very low intermodulation
distortion
• Very low transient
Intermodulatlon distortion
• Complete SOA protection

PIN CONFIGURATION
U Package
1

NON-INVERTING INPUT

2

INPUT GROUND

3

COMPENSATION

4

NEGATIVE SUPPLY (GROUND)

(SUBSTRATE)

5

OUTPUT

6

POSITIVE SUPPLY {Vee>

7

NOT CONNECTED

8

RIPPLE REJECTION

9

INVERTING INPUT

(FEEDBACK)

TOP VIEW

APPLICATIONS
• Hi-fi audio power amplifier
• Motor driver
• Power op amp

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

9-Pin Plastic SIP (SOT-131A)

-25'C to + 150'C

TDA1520AU

9-Pin Plastic SIP (SOT-157A)

-25'C to +150'C

TDA1520AQU

•

ABSOLUTE MAXIMUM RATINGS
PARAMETER

SYMBOL

RATING

UNIT

Vce

Supply voltage

50

V

10RM

Repetitive peak output current

4

A

IOSM

Non-repetitive peak output current

5

A

PTOT

Total power dissipation

see derating curve Figure 1

TSTG

Storage temperature range

-65 to +150

TA

Operating ambient temperature range

-25 to +150

'c
'c

tse

Duration of AC short-circuit of load
(RL = On)
during full-load sine-wave drive at:
Vs = ± 20V (symmetrical) and
RSUPPL Y = 0 n; or
Vs = 35V (asymmetrical) and
RSUPPL Y ;;;. 4n

max. 100

hours

2

'C/W

OJMB

Thermal resistance from junction to
mounting base

November 6, 1986

7-307

853-0919 86395

Signetics Linear Products

Product Specification

20W Hi-Fi Audio Amplifier

TDA1520A

SIMPLIFIED INTERNAL CIRCUIT DIAGRAM

81

o

o
o
RA

T4

,r--,,

,,,
,,
6-r
,

8

- ---'V\I'v----

1

,,

~

RB

I

,I

,,
,
I

'2

November 6, 1986

,,
,

"'T"

_; __

~r-~

____ ______ __ __
~

~

~

~~~~

_____

~,

~

+,,

,
,

I

'

:

~-----+--~--~:~~

~
:'

~

......,
1

4

7-308

'I

Signetics Linear Products

Product Specification

20W Hi-Fi Audio Amplifier

TDA1520A

DC ELECTRICAL CHARACTERISTICS
LIMITS
PARAMETER

SYMBOL

UNIT
Min

Vec

Supply voltage range

Typ

Max

50

V

70

70
105

mA
mA

3.2

A

15
~

ITOT

Total quiescent current at Vee

33V

IORM

Minimum guaranteed output current (peak value)

AC ELECTRICAL CHARACTERISTICS Vee ~ 33V: RL ~ 4n: f ~ 1kHz: TA ~ 25°C: measured in Test Circuit 01 Figure 2,
unless otherwise specilied.
LIMITS
PARAMETER

SYMBOL

UNIT
Min

Output power
sine-wave power at dTOT
Po

RL
RL
RL

1

~ 4n
~
~

4n
an: Vec

~

~

22
(Figure 4)

W
W
W

20
20

Power bandwidth at dTOT

AyO
Aye

Voltage gain
open-loop
closed-loop

~

0.5% Irom Po

~

50mW to 10W

kHz

20Hz
74
30

R1-8~~)

RIN

Internal resistance 01 Pin 1 (at

RIN

Input resistance 01 Test Circuit at Pin 1 (Figure 2)

V1N

Input sensitivity lor Po

~

~

RR

Ripple rejection at I

Total harmonic distortion at Po

100Hz: Rs

Ro

Output resistance (Pin 5)

Vo

Input offset voltage

~

Mn
20

kn

260

mV

76
aD

dB
dB

On

60

dB

16W

0.01

%

16W

dTOT

dB
dB

1

Signal-to-noise ratio
at Po ~ 50mW: RSOURCE ~ 2kn
I ~ 20Hz to 20kHz, unweighted:
weighted, measured according to IEC 179 (A-curve)
~

0.01
1

dTIM

Transient intermodulation distortion at Po

diM

Intermodulation distortion at Po

SR

Slew rate

November 6, 1986

Max

0.5%

42V

B

SIN

Typ

~

~

10W

0.011

10W

7-309

n
100

mV
%

0.01

%

9

VIliS

•

Signetics Linear Products

Product Specification

20W Hi-Fi Audio Amplifier

TDA1520A

50

. . +v.

..-------------~h

Ptot

(WI
40

.+

,

30

C

~

I',

,

1\
\
~,

20

\

10

o

-25

'~ .\
50

'\

1

NOTES:

C4
680"

_ _ Mounted on infinite heatsink
- - - Mounted on heatsink of 2.3°C/W

R'

Figure 1. Power Derating Curves

270

Figure 2. Test and Application Circuit

~r-r--------'----------r---------'---------'

~~+----------~---------4~~-------+~---------1

FREQ.=1kHz
DTOT = 0.5%

10r-+-----------~_,~----~~--------_+----------_1

10

~

40

Vs(V)

Figure 3. Output Power vs Supply Voltage VcclV)

November 6, 1986

7-310

50

22OO~F

Signetics Linear Products

Product Specification

20W Hi-Fi Audio Amplifier

TDA1520A

1.2

0.3

,

d tot
1%)

1.0
V,,,, 33Y
RL=4n
FREQ. = 1kHz

0.2

0.8

i:

~

o. 1

0."

V
0."

o

0.1

0
0.1

1.0

100

10
Po(W)

Figure 4. Total Harmonic Distortion (dlol)

November 6, 1986

10

f (kHz) 100
OPt066OS

0.2

7-311

Figure 5. Total Harmonic Distortion
(dlol) vs Operating Frequency
(f) at Vee = 33V, RL = 4!2,
Po = 10W (Constant)

AN149

Signetics

20W Hi-Fi Power Amplifier With
the TDA1520A
Application Note
Linear Products

Author: D. Udo

ABSTRACT
The TDA1520A single operational hi-fi power
amplifier is intended for audio and television
applications.
The circuit can deliver output power up to
20W into 4n and Bn loudspeakers operating
either from symmetrical or asymmetrical power supplies.
The 9-lead SOT 131A power encapsulation
combines good thermal behavior
(8JMB ';;; 2°C/W) with a reliable simple mounting to external heatsinks (screw or clip
mounting).
The IC has several internal protection circuits
to allow misloading conditions.

package SOT 131A is intended for use as
class-B hi-fi power amplifier.

INTERNAL CIRCUIT
DESCRIPTION

Some performance specifications are shown
below.

The internal circuit block diagram of the
TDA 1520A is shown in Figure 1.

- Supply voltage range
- Minimum guaranteed
output current
- Maximum non-repetitive
output peak current
- Maximum operating
ambient temperature
- Thermal resistance 8JC
Input impedance at Pin 1

The input amplifier is a Darlington-coupled
PNP differential stage (Tl - T4) having an
BOOIlA current source SI. DC biasing for Tl
can be derived from the internal voltage
bleeder RA - RB.

15 - 50V
3.2A
5A
150°C

';;;2°C/W
>IMn

The TDA 1520A can be powered with symmetrical and asymmetrical power supplies.
This application note shows applications with
asymmetrical power supplies.

INTRODUCTION

In our application with asymmetrical power
supply, the DC biasing is made with an
external resistor between Pin 1 and Pin B.
The external resistance between Pin 1 and
Pin B must be limited to 100 kn for offset
voltage reasons. The current drive to the
class-A driver stage (T7 - TB) is obtained
from the current mirror circuit of T5 - T6.
The DC current source S2 (5mA), for the
class-A stage T7 - TB flows through the three
series diodes D, to adjust and stabilize the
quiescent current of the output stage.

The TDA 1520A integrated operational amplifier in the 9-lead single-in-line plastic power

Sl

o
o
o
RA
T4

r---

B

----JVVv----

1

1

,

1

I

1
I

1

RB

I

1

I

..l!
..,....
I
1

I
I

1

I

1

1
1
12

-'...,
1
I
I

- ; - ---'VVv-

rr+__--II-_ _ _......_

~

+

I
1

1
I

I

I

,

1

~~:-+--i:...
~
..,....

¢1
:
1

~ __ J

!
Figure 1. Internal Circuit Block Diagram

February 19B7

....._....,._-+5-- _ -- --:

7-312

Signetics Linear Products

Application Note

AN149

20W Hi-Fi Power Amplifier With the TDA1520A

;--------r---+t------- ------.,----------------c-s4HI- 1 mn. The input impedance of the

Slew Rate
The slew rate of the amplifier is 6VI iJ.s.

Supply Voltage Ripple Rejection
The supply voltage ripple rejection at
f = 100Hz, is 58dS (Rs = 0).

Gain

The input sensitivity for Po = lOW is 210mV.
The closed-loop gain measured at f = 1kHz is
30dS. The closed-loop gain can be varied by
resistors Rl and R3.

Short-Circuit Behavior
AG short-circuiting is possible during 60 sec,
measured with sine wave drive f ;;. 40Hz into
clipping at a supply voltage of 30V and with a
supply series resistance of 4n.

Noise
The weighted signal-to-noise ratio at
Po = 50mW and Rs = 2 kn is 60dS measured according to lEG 179 (A-curve).

Measuring under the same conditions but
with pink noise drive, according to lEG 2681C, AG short-circuiting is allowed up to 15
minutes.

The unweighted noise (f = 20Hz - 20kHz) is
76dS.

Turn-on and -off Behavior
With the extra network the turn-off behavior
of the TDA 1520A can be improved.

Measured according to CGIR 466 peak value
(also new DIN 45405 standard) this signal-tonoise ratio is 66dS.
30

'50

'00

20

V

Fe

/

~

~

•

0

"

0

o

20

10

30

40

0

50

/
o

10

20

VsIV)

/

30

.

40

Vs(Vl
OPOO910

Figure 4_ Mldtap Voltage vsSupply Voltage

Figure 3_ Quiescent Current vs Supply Voltage

12

,.
Vs"'42V

Vs"'33V

o.

.

it

l

~

!! o.

/;

.

PO=10W

••

02

.

02

,.'

AL=8n

...

RL=40
Pc=10W

0

10'

10'

.

,

10'

'0'

'"

10'
FREQ.(Hz)

1'"

FREQ.(Hz)

Figure 5_ Distortion vs Frequency

February 1987

Figure 6_ Distortion

7-314

VB

Frequency

.

,

Signetics Linear Products

Application Note

20W Hi-Fi Power Amplifier With the TDA1520A

AN149

Va"'42V
RL=8{):
FftEQ... 'ktU:

Ys=33V

Rl=4Cl
FREO.""1kH.z

Po(W)

Po(W)

Figure 7. Distortion vs Output Power

Figure 8. Distortion vs Output Power

vJv ll1

vJv ll1

.

RL"'80

RL=4tl
PolfOd8=20W
DTOT = 0.5'10

.

•
! -,

II

I
-4

,

"

V

,

I

,

Po.OtlS=20W
DrOT = O.5"Ao

I
II

I

I

-4

,"

'"

,

"

FREQ.(Hz)

Figure 9. Power Bandwidth

'"

'"

Figure 10. Power Bandwidth

I

I

Vs=42V

V$"'33V

1--t-+-t-:l+fttt--t-++-t-H+tt~~;~n"4:1t-H++tt1

Rv"4n
V";VI2=4:t
f1=50Hor
12= 711Hz

.

,,.

FREQ. (Hz)

" = 50Hz

U-7kHt

II
II

..

II

!

/

0
0.'

Po(W)

Po(W)

Figure 11. 1M Distortion vs Output Power

February 1987

Figure 12. 1M Distortion vs Output Power

7-315

•

Signetics Linear Products

Application Note

20W Hi-Fi Power Amplifier With the TDA1520A

AN149

,

,

,,11111

,

,,~L IIII

,

RL=4n
PoATOd8=2.2W

RL=8!l
PoATOdB"'2.2W

,

0

,

,

I

,

,

I{

,/"

,

I

'"

'"

I

'I

i

/

I II

I

/"

' I

I ,

,

,

'"

"

FREQ(HI.)

'"

FREQ (Hz)

Figure 13. Frequency Response at Po = 2.2W

")'

.
0

~/

0

/

/

Figure 14. Frequency Response at Po = 2.2W

I

,

Vs=33Y
RL"'4!l
FREQ."'1kti1:

,1' RL""8H

/

1---

fREQ.= 1kHz
DToT=O.5%

l/

V-

,
Po{W)

'Is (VI

Figure 15. Output Power vs Supply Voltage

Figure 16. Power Dissipation vs Output Power

'18=42'1
RL",en
"REQ..= 1kHz

'V

~

-

---I

00

,

I
Po(W)

"

'Is (V)

Figure 17. Power Dissipation vs Output Power

February 1987

Figure 18. Worst-Case Power Dissipation
vs Supply Voltage

7-316

".

TDA1521

Signetics

2 X 12 Hi-Fi Audio Power
Amplifier
Product Specification

Linear Products

DESCRIPTION

FEATURES

The TDA1521 is a dual hi-fi audio power
amplifier in a 9-lead single in-line (SIL-9)
plastic power package. The device is
especially designed for mains-fed applications (e.g., stereo TV sound and stereo radio).

• Requires very few external
components

PIN CONFIGURATION

• Input muted during power-on and
-off (no switch-on or switch-off
sounds)
• Low offset voltage between
output and ground
• Excellent gain balance between
channels
• Hi-fi according to lEe 268 and
DIN 45500
• Short-circuit-proof
• Thermally protected

TOP VIEW

APPLICATIONS

PIN NO.

1

2

• Stereo
• TV sound

GND
OUT1

Ground
Output 1
Negative supply

OUT2

+Voc
INV2
-INV2

ORDERING INFORMATION
TEMPERATURE RANGE

DESCRIPTION

Non-inverting input 1
Inverting input 1

-Vee

• Radio

DESCRIPTION

SYMBOL

-INV1
INV1

Output 2
Positive supply
Inverting input 2
Non-inverting input 2

ORDER CODE

9-Pin Plastic SIP (SOT-131 B)

TDA1521U

•
November 14, 1966

7-317

653-0966 66554

I

Signetics Linear Products

Product Specification

2 X 12 Hi-Fi Audio Power Amplifier

TDA1521

BLOCK DIAGRAM
+Vcc

680

INV1
-INVI
20k
OUTI

+Vcc

10k

GND
VREF 1

-Vee
20k
OUT2

-INV2
680
INV2

-Vee

November 14, 1986

7-318

Signetics Linear Products

Product Specification

2 X 12 Hi-Fi Audio Power Amplifier

FUNCTIONAL DESCRIPTION
This hi-fi stereo power amplifier is designed
for mains-fed applications. The circuit is optimal for symmetrical power supplies but it is
also well suited to asymmetrical power supply
systems. An output power of 2 X 12W
(THD = 0.5%) can be delivered into an an
load with a symmetrical power supply of
± 16V.

TDA1521

The gain is fixed internally at 30d8, but can
be changed externally if required. Internal
gain fixing gives low gain spread and very
good balance between the amplifiers (0.2d8).
A special feature is an input mute circuit
which provides suppression of unwanted signals at the inputs during switching on and off.
This circuit disconnects the non-inverting inputs when the supply voltage is below ± 6V,

while allowing the amplifiers to remain in their
DC operating condition.
Two thermal protection circuits are provided,
one monitors the average junction temperature and the other the instantaneous temperature of the power transistors. 80th protection circuits activate at 150·C, allowing safe
operation to a maximum junction temperature
of 150·C without added distortion.

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

RATING

UNIT

+20

V

4

A

Vee=Vs.7-3

Supply voltage (Pins 5 and 7)

IOSM

Non-repetitive peak output current (Pins 4 and 6)

PTOT

Total power dissipation

see Figure 1

TSTG

Storage temperature range

-65 to +150

·C

TI

Junction temperature

+150

·C

1

hour

tse

Short-circuit time:
outputs short-circuited to ground
Symmetrical power supply
Asymmetrical power supply;
Vee < 'V
(unloaded);
RI ~*n

OJC

Thermal resistance from junction to case

tse

1

hour

25

·C/W

HEATSINK DESIGN EXAMPLE
20

1n!lnlte

15

\
~HA ;;;;:

3.3'e/W

\

~

I

Heat.lnk -

\
\\
\.\

o
-25

With derating of 2.5·C/W, the value of heatsink thermal resistance is calculated as follows: given RL = an and Vee = ± 16V, the
measured maximum dissipation is 14.6 W;
then, for a maximum ambient temperature of
65·C, the required thermal resistance of the
heatsink is
150-65

OHA = - - - -

14.6

2.5 = 3.3·C/W

"
150

Figure 1. Power Derating Curve

November 14, 19a6

7-319

II

Signetics Linear Products

Product Specification

2 X 12 Hi-Fi Audio Power Amplifier

TDA1521

DC ELECTRICAL CHARACTERISTICS
SYMBOL

PARAMETER

Vee

Supply voltage range

10RM

Repetitive peak output current

CONDITIONS

MIN

TYP

MAX

±16

±20

UNIT
V

2.2

A

Operating mode: symmetrical power supply; test circuit as per Figure 2; Vee = ± 16V; RL = an; T A = 25°C; f = 1kHz
±7.5

Vee

Supply voltage range

ITOT

Total quiescent current

without RL

Po
Po

Output power

THO = 0.5%
THO= 10%

THO

Total harmonic distortion

Po=6W

B

Power bandwidth 1

THO =0.5%

Gv

Voltage gain

Ll.Gv

Gain balance

VNO(RMS)

Noise output voltage (RMS value); unweighted
(20Hz to 20kHz)

IZil

Input impedance

RR

Ripple rejection 2

00

Channel separation

46

liB

Input bias current

VOFF

DC output offset voltage

10

±16

±20

V

50

·

mA

12
15

W
W

.

0.2

29

31

30
0.2

Rs= 2kn

Rs=On

%

20Hz to 20kHz
dB
dB

70

140

I1V

14

20

26

kn

40

60

dB

70

dB

0.3
WRT GNO

I1A

20

200

mV

Input mute mode: symmetrical power supply; test circuit as per Figure 2; Vec = ± 4V; RL = an; T A = 25°C; f = 1kHz
±2

Vee

Supply voltage

ITOT

Total quiescent current

without RL

VOUT

Output voltage

VI = 600mV

VNO(RMS)

Noise output voltage (RMS value); unweighted
(20Hz to 20kHz)

Rs= 2kn

RR

Ripple rejection 2

VOF F

DC output offset voltage

±5.a

1.8

·

mV

70

140

I1V

20

200

mV

·

mA

35
WRT GNO

V
mA

30

dB

Operating mode: asymmetrical power supply; test circuit as per Figure 3; Vee = ± 4V; RL = 8n; TA = 25°C; f = 1kHz
ITOT

Total quiescent current

50
THO=0.5%
THO= 10%

Po
Po

Output power

THO

Total harmonic distortion

Po=4W

B

Power bandwidth

THO= 0.5%1

Gv

Voltage gain

Ll.Gv

Gain balance

VNO(RMS)

Noise output voltage (RMS value); unweighted
(20Hz to 20kHz)

5

6
8.5

.

40Hz
29

30

0.2

%

20

kHz

31

dB

0.2
Rs=2kn

140

I1V

26

kn

~il

Input impedance

14

20

Ripple rejection 2

40

50

00

Channel separation

Rs=On

40

NOTES:
I. Power bandwidlh at Po MAX -3dS.
2. Ripple rejection at As = On, f = 100Hz to 20kHz; ripple voltage = 200mV (AMS value) applied to positive or negative supply rail.

7-320

dB

70

RR

November 14, 1986

W
W

dB
dB

Signetics Linear Products

Product Specification

2 X 12 Hi-Fi Audio Power Amplifier

TDA1521

+Vcc

,g
T

20k

680

I
I

-4:-

I
I
I

RL

I

=8

I
.1.

T

I
I
RL

I
I

=8

rJ....1

":"

~":"

I

T

I

' - - - - - - - - - - - - -....-...L...-o-Vee

Figure 2. Test and Application Circuit; Symmetrical Power Supply

R,
Vee r------------.-~~~--oVs

1.J;

680

"
I

201<

I

~*

220nF

V,

o----j

.ok
INTERNAL 1f2Vcc

+
100~FI
20k

TDA1521

200nF

V,

o----j

680

Figure 3. Test and Application Circuit; Asymmetrical Power Supply

November 14. 1986

7-321

•

TDA2611A

Signetics

5W Audio Amplifier
Product Specification

Linear Products
DESCRIPTION

FEATURES

The TDA2611 A is a 5W audio amplifier
in a 9-pin single in-line (SIP) plastic
package.

• Possibility for increasing the
input impedance
• Single in-line (SIP) construction
for easy mounting
• Extremely low number of
external components
• Thermal protection
• Well-defined open-loop gain
circuitry with simple quiescent
current setting and fixed
integrated closed-loop gain

PIN CONFIGURATION
U Package

APPLICATIONS
•
•
•
•

TV
Radio
Record player
Communication receiver

TOP VIEW

• Alarms

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

9-Pin Plastic SIP (SOT-1108)

-25°C to + 150°C

TDA2611AU

TEST CIRCUIT
r---------~----_Q+

NOTES:

Pin 3 not connected.
Input impedance can be increased by applying C and A between Pins 5 and 9 (see also Figures 4 and 5).

November 6, 1986

7-322

853-0921 86397

Signetics Linear Products

Product Specification

5W Audio Amplifier

TDA2611A

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

Vee

Supply voltage

108M

Non-repetitive peak output current

IORM

Repetitive peak output current

RATING

UNIT

35

V

3

A

1.5

A

Total power dissipation

see derating
curves
Figure 1

T8TG

Storage temperature range

-65 to + 150

'C

TA

Operating ambient temperature range

-25 to + 150

'C

PTOT

HEATSINK EXAMPLE
Assume Vee = 18V; RL = 8n; T A = 60'C
maximum; TJ = 150'C (max. for a 4W application into an 8n load, the maximum dissipation is about 2.2W). The thermal resistance
from junction to ambient can be expressed
as:

150-60
OHA = - - - = 41'C/W.
2.2
o~--~----~----~--~
100
150
-50

SinceOJTAS = 11'C/W and
(hASH = 1'C/W,
OHA = 41 - (11 + 1) = 29'C/W.

Figure 1. Power Derating Curves

DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL

UNIT

PARAMETER
Min

Vee

Supply voltage range

IORM

Repetitive peak output current

ITOT

Total quiescent current at Vee = 18V

November 6, 1986

Typ

6

25

7-323

Max

35

V

1.5

A

25

mA

I

Signetics Linear Products

Product Specification

5W Audio Amplifier

TDA2611A

AC ELECTRICAL CHARACTERISTICS TA = 25'C; vee = 18V; RL = 8n; f = 1kHz, unless otherwise specified;
see also Figure 2.
LIMITS
SYMBOL

PARAMETER

UNIT

TEST CONDITIONS
Min

Po

AF output power at dTOT = 10%
Vce = 18V; RL = 8n
Vee = 12V; Rl = 8n
Vee = 8.3V; Rl = 8n
Vee = 20V; RL = 8n
Vee = 25V; Rl = 15n

dTOT

Total harmonic distortion at Po

Typ

Max

4

W
W
W
W
W
W

4.5
1.7
0.65
6
5

= 2W

1

Frequency response

0.3

%

15

kHz

IZII

Input impedance

45

VN

Noise output voltage at Rs = 5kn;
B = 60Hz to 15kH z

0.2

0.5

mV
mV

VI

Sensitivity for Po

55

66

mV
mV

= 2.5W

44

kn'

NOTE:
1. Input impedance can be increased by applying C and R between Pins 5 and 9 (see also Figures 4 and 5).

10

15 ----Nor

TYPICAL VALUES' , ,
RL =8QjVcc =18V
- - RL =15Q;Vcc=2SV

GUARANTEED
IN VIEW OF
IORM=1.5A

I
I

7.5

I
I
I

10 I------+---.''---,I-~

I
I

2.5

o

10'

1\

1/1
~

A

~~~

B

~
10

o~-=~----~------~

o

~

~

o
10

VccM

Figure 2. Total Harmonic Distortion
as a Function of Output Power

Figure 3. Output Power as a Function
of Supply Voltage

1D"

102

1D'

FREQUENCY (Hz)
NOTES:

Curve a for C" 1p.F, R ... on;
Curve b for C = 1p.F. R = 1kn;
C2 = 10pF; typical values.

Figure 4. Input Impedance as a
Function of Frequency

November 6, 1986

7-324

Signetics Linear Products

Product Specification

5W Audio Amplifier

TDA2611A

~ Jc~I~~V;R~ ~1k~;li~1k~Z

10' _ _

••••• Vcc =18V;RL =82;f=1kHz

v

7
~

I

o

1

10'

R(Q)

NOTE,

NOTE,

C = 1J1F, f = 1kHz.

Po =: 3.5W; f:: 1kHz.

Figure 5. Input Impedance as a
Function of R (n) in Test Circuit

0

--

""'.......

.,,-

....

100

50

Figure 6. Total Harmonic Distortion as
a Function of Rs(n) in the Test Circuit

j,/
..-

APPLICATION INFORMATION
~

..

'

10
R1
220k

V,

VOLUME

+

t-----<>vcc

+

lONE

Figure 7. Total Power Dissipation and
Efficiency as a Function of
Output Power

10

C9
22O.F

7.5

RL

82

j

I

5

I
2.5

II

Figure 8. Ceramic Pick-Up Amplifier Circuit

""""

-

10-1

I

VI"
10

NOTES,
_ _ with tone control

- - - without tone control; in circuit of Figure 8;
typical values.

Figure 9. Total Harmonic Distortion as
a Function of Output Power

November 6, 1986

7-325

TDA7050T

Signetics

low Voltage Mono/Stereo
Power Amplifier
Product Specification

Linear Products

DESCRIPTION

FEATURES

The TDA7050T is a low voltage audio
amplifier for small radios with headphones (such as watch, pen and pocket
radios) in mono (bridge-tied load) or
stereo applications.

• Limited to battery supply
application only (Typ. 3 and 4V)
• Operates with supply Yoltage
down to 1.6V
• No external components required
• Very low quiescent current
• Fixed integrated gain of 26dB,
floating differential input
• Flexibility in use - mono BTL as
well as stereo
• Small dimension of encapsulation

PIN CONFIGURATION

0

N, 0 Packages

N?~~~l,

INV INPUT,
INVINPUT2

2

8 Vee
7 OUTPUT,

3

OUTPUT2

N?J'I;~~ 4

5 GROUND
TOP VIEW

APPLICATIONS
•
•
•
•
•

Portable radio
Personal computer
Speech syntheSis
Telephone
Modem

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

8-Pin Plastic SO Package
(SOT-96A; SO-8)

o to

+70·C

TDA7050TD

8-Pin Plastic DIP (SOT-97A)

o to

+70·C

TDA7050TN

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

Vcc

Supply voltage

10M

Peak output current

PTOT

Total power dissipation

TSTG

Storage temperature range

Tc

Crystal temperature

tsc

AC and DC short-circuit duration at
Vcc = 3.0V (during mishandling)

October 10, 1986

RATING

UNIT

6

V

150

mA

see derating
curve, Figure 1
-55 to +150

·C

100

·C

5

s

7·326

853-0896 85941

Signetics Linear Products

Product Specilication

TDA7050T

Low Voltage Mono/Stereo Power Amplifier

DC ELECTRICAL CHARACTERISTICS Vec = 3V; I = 1kHz; RL = 32n; TA = 25°C, unless otherwise specified.
SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

Supply
Vee

Supply voltage

ITOT

Total quiescent current

1.6
3.2

6.0

V

4

mA

Bridge-tied load application (BTL); see Figure 4
Po
Po

Output powerI
Vce = 3.0V; dlot = 10%
Vee = 4.5V; 

Q
-u

aDc

f}

()
17

~ MSC

"0
0

1-8
ADA7

15_

CAS
RAS

.!!.,.RIW
12-14,16

0104
11 -MUTE

,------,
I
I

-.,J

~

FLAG PROCESSOR

~

37

___.._OMS
38

I

--..CLAB
39

I
I
I

~WSAB

38

2.

=+

0

»
C

a.
C)"

eEP/PES

GENERATOR

,.

21

Z1
CEFM

0

<6"

.....
3

I
I

CRI

0

(i)"
(")

CD

I

SAA72tO

EFAB

Q.

~
en

I
I

L_

0

3

Voo

Vss

VeB
(DECOUPUNG

-u

ONLY)

8.

~
""-J

J\)

..:.

•

o

§.

1il'"
o

8g:
:::J

Product Specification

Signetics Linear Products

SAA7210

Decoder for Compact Disc Digital Audio System

DC AND AC ELECTRICAL CHARACTERISTICS Voo = 4.5 to 5.5V; Vss = OV; TA = -20°C to + 70°C, unless otherwise
specified.
LIMITS
UNIT

PARAMETER

SYMBOL

Min

Typ

Max

Supply
Voo
100

4.5

Supply voltage (Pin 40)
Supply current (Pin 40)

5.0

5.5

V

200

TBF

mA

Inputs
01-04, QCL
VIL

Input voltage LOW

-0.3

+0.6

V

VIH

Input voltage HIGH

2.0

Voo + 0.5

V

±ILI

Input leakage current

10

IlA

CI

Input capacitance

7

pF

V

MUTE, CRI
VIL

Input voltage LOW

-0.3

+0.6

VIH

Input voltage HIGH

2.0

Voo + 0.5

V

IZII

Internal pull-up impedance at VI = OV

TBF

TBF

kn

CI

Input capacitance

7

pF

V

50

QRA,SWAB
VIL

Input voltage LOW

-0.3

+0.8

2.0

Voo + 0.5

V

7

pF

VIH

Input voltage HIGH

CI

Input capacitance

Izil

Internal pull-up impedance at VI = OV

5

10

kn

HFO
VIL

Input voltage LOW

-0.3

+0.6

V

VIH

Input voltage HIGH

2.0

clamped

V

VCL

Input clamping voltage at II = 1001lA

±Is

Input source current

100

}JA

CI

Input capacitance

Izil

Internal pull-up impedance at VI = OV

3

V

7
50

pF
kn

Outputs
A1-A8, R/W, 01-04, CAS, RAS, CEFM, QOATA, DEEM, SOAB, SCAB, EFAB, OAAB, CLAB, WSAB
VOL

Output voltage LOW at -IOL = 1.6mA

0

0.4

VOH

Output voltage HIGH at IOH = 0.2mA

2.4

Voo

V
V

CL

Load capacitance

50

pF

MSC (open-drain)
VOL

Output voltage LOW at -IOL = lmA

CL

Load capacitance

0

0.2

V

50

pF

SWAB, QRA (open drain)
VOL

Output voltage LOW at -IOL = 1.6mA

CL

Load capacitance

RL

Internal load resistance

February 24, 1967

0

5

7-332

0.4

V

50

pF
kn

Signetics Linear Products

Product Specification

Decoder for Compact Disc Digital Audio System

SAA7210

DC AND AC ELECTRICAL CHARACTERISTICS (Continued) voo = 4.5 to 5.5V; vss = OV; TA = -20°C to + 70°C,
unless otherwise specified.
LIMITS
SYMBOL

PARAMETER
Min

Typ

Max

I
I

UNIT

Analog circuits
Data slicer Input HFI
VI(P-Pl

AC input voltage range (peak-to-peak value)

0.25

2.5

V

Izil
Izil

Input impedance
normal (HFD HIGH)
disabled (HFD LOW)

TBF
TBF

TBF
TBF

kQ
kQ

CI

Input capacitance

7

pF

TBF

!.LA

Output FB
10

Output current at VFB

= 2V

TBF

100

Phase detector
Output PD/OC
IZol

Output impedance

ex

Control range 1

G

Gain factor

TBF

Input reference current

500

kQ

TBF
±2.1

rad
mA/rad

Input IREF
IREF

TBF

!.LA

Fine frequency detector
Output PD/OC
IZol

Output impedance

2

kQ

I

kQ

TBF

MHzlV

Coarse frequency detector
Output PD/OC2
IZol

Output impedance

Voltage-controlled oscillator
Input PD/OC
Kosc

Oscillator constant

Crystal oscillator
Input XTAL 1I0utput XTAL2
GM
Gv

Mutual conductance at 100kHz
Small-signal voltage gain (Gv

= GM

X Ro)

1.5

ms

3.5

VIV

CI

Input capacitance

10

pF

CFB

Feedback capacitance

5

pF

Co

Output capacitance

10

pF

±Iu

Input leakage current

10

IlA

V

Slave clock mode
VIL

Input voltage LOW

-0.3

0.8

VIH

Input voltage HIGH

2.4

Voo + 0.5

V

tR

Input rise time3

20

ns

tF

Input fall time3

20

ns

tHIGH

Input High time at 1.5V (relative to clock period)

55

%

February 24, 1987

45

7·333

Signetics Linear Products

Product Specification

SM7210

Decoder for Compact Disc Digital Audio System

DC AND AC ELECTRICAL CHARACTERISTICS (Continued) voo = 4.5 to 5.5V; Vss = OV; TA = -20·e to + 70·e,
unless otherwise specified.
LIMITS
PARAMETER

SYMBOL

UNIT
Min

Typ

Max

10.16

11.2896

12.42

MHz

fXTAL/2
4

8.6436

fXTAL
15

MHz
MHz

Timing characteristics
fXTAL

Operating frequency (XTAL)

fVC01
fVC02

Operating frequency (VeO)
coarse frequency detector inactive
no input Pin 25 (HFI)

Outputs (see Figures 6 and 7)
CEFM 4
tR

Output rise time

20

ns

tF

Output fall time

20

ns

tHIGH

Output High time

50

ns

DAAB, CLAB, WSAB, EFAB4 (data to B-chip; 12S format)
tR

Output rise time

20

ns

tF

Output fall time

20

ns

DAAB, WSAB, EFAB to CLAB
tsu; tOAT

Data setup time

100

ns

100

ns

CLAB to DAAB, WSAB, EFAB
tHD; tDAT

Data hold time

SDAB, SCAB, DEEM4 (subcoding outputs)
tR

Output rise time

20

ns

tF

Output fall time

20

ns

SDAB to SCAB
tsu;
tSOAT

Subcoding data setup time

100

ns

100

ns

SCAB to SDAB
tHO;
tSOAT

Subcoding data hold time

SWAB 4
tR

Output rise time

1

flS

tF

Output fall time

100

ns

Output duty factor

February 24, 1987

50

7-334

%

Signetics Linear Products

Product Specification

SAA721 0

Decoder for Compact Disc Digital Audio System

DC AND AC ELECTRICAL CHARACTERISTICS (Continued) VDD = 4.5 to 5.5V; vss = OV; TA = -20·C to + 70·C,
unless otherwise specified.
LIMITS
SYMBOL

UNIT

PARAMETER
Min

Typ

Max

Q-channel I/O (see Figures 10 and 11)
QRA, QCL, QDATA

Access time 5
tACC; N

normal mode

0

tACC; F

refresh mode

13.3

13.3 +
n X 13.3
n X 13.3

ms

500

ns

ms

tDACK

OCL to ORA acknowledge delay

tHD; A

OCL to ORA request hold time

500

ns

tCK;

LOW

OCL clock input LOW time

500

ns

tCK; HIGH

OCL clock input HIGH time

500

tDD

OCL to ODATA delay time

tHD; ACC

Data hold time before new frame is accessed

tACK

Acknowledge time

2.3

180·
1.1 rad=--.
(3.14)
2. Coarse frequency detector output PO/OC active for VCO frequencies

> fXTAL

3. Aeference levels = 0.5V and 2.5V.

= 50pF.

5. Q-channel access times dependent on cyclic redundancy check (CAG).

February 24, 1987

7-335

fXTAL

and

< -2- .

ns
ms

10.8

NOTES:

4. Output rise and fall times measured with load capacitance (CJ

ns
500

ms

Signeties Linear Products

Product Specification

Decoder for Compact Disc Digital Audio System

SAA721 0

"I

1 FRAME::;: 588 CHANNEL BITS
31

SYNC

11 CHANNEL BITS

11 CHANNEL BITS

I...o_------

32

MAY BE INVERTED - - - - - - -....-14-

I_

14 BIT EFM WORD

---.1-

NOTE:
(1) = merging and low frequency suppression bits.

Figure 1. Data Input Signal

FUNCTIONAL DESCRIPTION

Demodulation
Data read from the disc is amplified and
filtered externally and then converted into a
clean digital Signal by the data slicer. The
data slicer is an adaptive level detector which
relies on the nature of the eight-to-fourteen
modulation system (EFM) to determine the
optimum slicing level. When a signal drop-out
is detected (via the HFD input, or internally
when a data run length violation is detected)
the feedback (FB) to the data slicer is disabled to stop drift of the slicing level.
Two frequency detectors, a phase detector,
and a voltage-controlled oscillator (VCO)
form an internal phase-locked loop (PLL)
system. The voltage-controlled oscillator
(VCO) runs at twice the input data rate
(typically at 8.6436MHz), its frequency being
dependent on the voltage at Pin 22 (PDfOC).
One of the frequency detectors compares the
VCO frequency with that of the crystal clock
to provide coarse frequency-control signals
which pull the VCO to within the capture
range of fine frequency control. Signals for
fine frequency control are provided by the
second frequency detector which uses data
run length violations to pull the VCO within
the capture range of the PLL. When the
system is phase-locked, the frequency detector output stage is disabled via a lock indication signal. The VCO output is divided by two
to provide the main demodulator clock signal
which is compared with the incoming data in
the phase detector. The output of the phase
detector, which is combined internally with
the frequency detector outputs at Pin 22 (PDf

February 24, 1987

OC), is a positive and negative current pulse
with a net charge that is dependent on the
phase error. The current amplitude is determined by the current source connected to Pin
23 (lREF).
The demodulator uses a double timing system to protect the EFM decoder from erroneous sync patterns in the data. The protected
divide-by-588 master counter is reset only if a
sync pattern occurs exactly one frame after a
previous sync pattern (sync coincidence) or if
the new sync pattern occurs within a safe
window determined by the divide-by-588 master counter. If track jumping occurs, the divide-by-588 master counter is allowed to freerun to minimize interference to the motor
speed controller; this is achieved by taking
the CRI input (Pin 28) Low to inhibit the reset
signal.
The sync coincidence pulse is also used to
reset the lock indication counter and disable
the output from the fine frequency detector. If
the system goes out of lock, the sync pulses
cease and the lock indication counter counts
frame periods. After 63 frame periods with no
sync coincidence pulse, the lock indication
counter enables the frequency detector output.
The EFM decoder converts each symbol (14
bits of disc data + 3 merging bits) into one of
256 8-bit digital words which are then passed
across the clock interface to the subcoding
section. An additional output from the decoder senses one of two extra symbol patterns
which indicate a subcoding frame sync. This
signal, together with a data strobe and two
error flags, is also passed across the clock

7·336

interface. The error flags are derived from the
HFD input and from detected run length
violations.

Subcoding
The subcoding section has four main functions
• a-channel processor
• De-emphasis output
• Pause (P-bit) output
• Serial subcoding output to B-chip
The a-channel processor accumulates a subcoding word of 96 bits from the a·bit of
successive subcoding symbols, performs a
cyclic redundancy check (CRC) using 16 bits
and then outputs the remaining 80 bits to a
microprocessor on an external clock. The de·
emphasis signal (DEEM) is derived from one
bit of the CRC-checked a-channel. The
DEEM output (Pin 32) is additionally protected by a debounce circuit.
The P·bit from the subcoding symbol, also
protected by a debounce circuit, is output via
the serial subcoding signal (SDAB) at Pin 34.
The protected timing used for the EFM decoder makes this output unreliable during
track jumping.
The serial output to the B-chip consists of a
burst of 10 bits of data clocked by a burst
clock (SCAB). The 10 bits are made up from
subcoding signal bits a to W, the a·channel
parity check flag, a demodulator error flag
and the subcoding sync signal. At the end of
the clock burst, this output delivers the de·
bounced P-bit signal which can be read
externally on the rising edge of SWAB at Pin
33 (see Figure 2).

Signetics Linear Products

Product Specification

SAA7210

Decoder for Compact Disc Digital Audio System

CRC ERROR BIT

SUBCODING ERROR FLAG
(NOT USED SAA7220)

SYNC (ACTIVE LOW)

\
SOAB

P-BIT

SCAB

2.8224 MHz BURST CLOCK
SUBCODE WORD FREQUENCY =7.35 kHz

Figure 2. Typical Subcoding Waveform Outputs

Pre-FIFO
The 10 bits (6 bits of symbol data + 2 error
flag bits) which are passed from the demodulator across the clock interface to the subcoding section are also fed to the pre-FIFO with
the addition of two timing signals. These two
timing signals indicate:

therefore, in each access cycle, a row address (RAS Pin 9) is set up first and then
three 4-bit nibbles are accessed using sequential column addresses (CAS Pin 15). As
only 10 bits are used for each symbol (including flags), the fourth nibble is not accessible.

(1) That a new data symbol is valid

There are 4 different modes of RAM access:
• WRITE 1

(2) Whether the new data symbol is the first
symbol of a frame.

• READ 1
• WRITE 2

The pre-FIFO stores up to 4 symbols (including flags) and acts as a time buffer between
data input and data output. Data passes into
the pre-FI FO at the rate of 32 symbols per
demodulator frame and the symbols are
called from the pre-FI FO into RAM storage at
the rate of 32 symbols per error-correction
frame. The timing, organized by the master
controller, allows up to 40 attempts to write
32 symbols into the RAM per error-correction
frame. The 6 extra attempts allow for transient changes in clock frequency (e.g., pitch
control).

• READ 2
During WRITE I, data is taken from pre-FIFO
at regular intervals and written into one half of
the RAM. This half of the RAM acts as the
main FIFO and has a capacity of up to 64
frames. During READ I, the 32 symbols of
the next frame due out are read from the
FIFO. The numerical difference between the
WRITE 1 and READ 1 addresses is used to
control the speed of the disc drive motor.

This section controls the flow of data between the external RAM and the error corrector. Each symbol of data passes through the
error corrector two times (correction processes Cl and C2) before entering the concealment section.

When a frame of data has been read from the
FIFO it is stored in a buffer RAM until it can
be accepted by the CI RC error correction
system. At this time the error correcting
strategy of the CIRC decoder for the frame is
determined by the flag processor. The frame
for correction is then loaded into the decoder
one symbol at a time and the 32 symbols
from the previous correction are returned to
the buffer RAM.

The RAM interface uses the full crystal frequency of 11.2MHz to determine the RAM
access waveforms (the main clock for the
system is 5.6MHz). One RAM access (READ
or WRITE) uses 12 crystal clock cycles which
is approximately 1j.tS. The timing (see Figure
4) is based upon the specification for the
dynamic 16k X 4-bit RAM (4416). This RAM
requires multiplexed address signals and

After the first correction (Cl), only 28 of the
symbols are required per frame. The symbols
are stored in the buffer RAM together with
new flags generated after the correction cycle
by the flag updating logic. This partiallycorrected frame is then passed to the external RAM by a WRITE 2 instruction. The deinterleaving process is carried out during this
second passage through the external RAM.

Data Control

February 24, 1987

7-337

The WRITE 2 and READ 2 addresses for
each symbol provide the correct delay of 108
frames for the first symbol and zero delay for
the last symbol.
After execution of the READ 2 instruction, the
frame of 28 symbols is again stored in the
buffer RAM pending readiness of the CIRC
decoder and calculation of decoding strategy.
Following the second correction (C2), 24
symbols including unreliable data flags (URD)
are stored in the buffer RAM and then output
to the concealment section at regular intervals.

Flag Processing
Flag processing is carried out in two parts as
follows:
• Flag strategy logic
• Flag updating logic.
While a frame of data from the external
memory is being written into the buffer RAM,
the error flags associated with that frame are
counted. Two bits are used for the flags, thus
"good" data (flags ~ 00) and three levels of
error can be indicated.
The optimum strategy to be used by the CIRC
error corrector is determined by the 2-bit flag
information used by the flag strategy logic
ROM in conjunction with its associated arithmetic unit (ALU). The flags for the Cl correction are generated in the demodulator and
are based on detected signal drop-outs and
data run length violations. Updating of the
flags after Cl is dependent on the CIRC
decoder correction of that frame. The updated flags are used to determine the C2
strategy. After C2 correction a single flag
(URD) is generated to accompany the data
into the concealment section.

Signetics linear Products

Product Specification

Decoder for Compact Disc Digital Audio System

SAA721 0

LEFT SAMPLE

RIGHT SAMPLE

-------~
I

DAAB

=

+ ______________L_E_FT_E_R_R_O_R_FL_A_G_________________ ~

EFAB __________....J¥\.____

1

I

RIGHTERROR FLAG

I
I
J.~-~I

----

WSAB----""'\\

I'

I
I

I

I
_-LJL.J1S

I

CLAB

1-1.----,,·_------1_1

2.8224 MHz

Figure 3. Typical Waveform Outputs to B·Chlp or CAC

CRYSTAL
CLOCK

I

I

I

ADDRESS

I

~~----RO-W----....J)(\.----C-OL-U-M-N-'--....J)(\,---C-0-L-UM-N-2----J)(r---C-O-L-U-M-N-3--~~r-----R-O-W------~
I

I

-RAS -'l~

\ \.____________________________________________....J.11I

\\.----

I

I

Ir--------

RiW

DATA
(WRITE)

_+-_____________' '-__-+________, .....____________-' . . ____________

0

I

J>------------------------1

DATA,
(READ)

1"".-----------

>--------<

I

>--------<

)------------------

RAM ACCESS CYCLE (6 SYSTEM CLOCK CYCLES· 1.063., NOMINAL) - - - - - - - - _ . \

Figure 4. RAM Timing Waveforms: Timing Based on RAM TMS4416;

February 24. 1987

0

~--------------'

7·338

G Input

to RAM Held Low

Product Specification

Signetics Linear Products

Decoder for Compact Disc Digital Audio System

symbol memory. From these syndromes errors can be detected and corrected.

CIRC Decoding
Data on the compact disc is encoded according to a cross-interleaved Reed-Solomon
code (CIRC) and this decoder exploits fully
the error-correction capabilities of the code.

Microcoded Correction Processing
The processor uses an Arithmetic Logic Unit
(ALU) which includes a multiplier based on
logarithms. The correction algorithm follows
the microcode program stored in a ROM.

Decoding is performed in two cycles, and in
each cycle the CIRC decoder corrects data in
accordance with the following formula:

Concealment
This section combines 8-bit data symbols into
left and right stereo channels. Each channel
has a 16-bit capacity and holds two symbols
(a stereo sample). The channels operate
independently. A concealment operation is
performed when a URD flag accompanies
either symbol in a stereo sample. If a single
erroneous sample is flagged between two
'good' samples then linear interpolation is
used to replace the erroneous value. If two or
more successive samples are flagged, a sample-and-hold is applied and the last of the
erroneous samples is interpolated to a value
between that of the hold and that of the
following 'good' sample.

2t + e = 4
where:
e = the number of erasures (erroneous
symbols whose position is known).
t

= allowed number of additional failures
which the decoder program has to find.

The flag processor pOints to the erasure
symbols and tells the CI RC decoder how
many additional failures are allowed. If the
error corrector is presented with more than
the maximum it will stop and flag all symbols
as unreliable.
The CIRC decoder is comprised of two sections: Syndrome formation and micro-coded
correction processing.

If MUTE is requested, the data in each
channel is attenuated to zero in 15 successive divide-by-two steps. At the end of a mute
period, the output is incremented to the first

Syndrome Formation
Four correction syndromes are calculated
while the frame of data is being written into a

SAA7210

'good' value in two steps using the interpola-

tor.
All erroneous data supplied to the concealment section continues to be flagged when it
is output to the B-chip where it receives
additional and more efficient concealment.

Motor Speed Control (see
Figure 5)
The motor speed control (MSC) output from
Pin t 7 is a pulse width modulated signal. The
duty factor of the pulse width modulation is
calculated from the difference in numerical
value between the WRITE 1 and READ 1
addresses, the difference being nominally
half of the FIFO space. The calculation is
performed at a rate of 88.2kHz.
The duty factor of MSC varies in 62 steps
from 1.6% (FIFO full) to 98.4% (FIFO empty).
When a motor-start signal is detected (via
SWAB/SSM) the duty factor is forced to
98.4 % for 0.2 seconds followed by a normal,
calculated signal. After a motor-stop signal is
detected, the duty factor is forced to 1.6% for
0.2 seconds followed by a continuous 50%
duty factor. A change in motor-start/-stop
status occurring within the 0.2 second periods
overrides the previous condition and resets
the data control timer.

MEAN
PWM
OUTPUT
SIGNAL

o

1

•:

16

1

'I'1

32

I

40

':

FIFO FULL

NOMINAL

WINHIBIT

WORKING

48

I 56
:2

FR~ES OF

163

s;'

RAM SPACE

FIFO EMPTY UNOCCUPIED

R INHIBIT

POINT

Figure 5. Motor Speed Control

IF

I.

CLAB

DAAB
WSAB
EFAB

NOTE:
Reference Levels = O.BV and 2.0V

Figure 6. Typical Data Output Waveforms to B·Chip or DAC

February 24, 1987

7·339

•

Product Specification

Signetics linear Products

Decoder for Compact Disc Digital Audio System

SAA721 0

SCAB

SDAB

SWAB

NOTES:
1. Reference levels for SCAB and SOAS = O.BV and 2.0V
2. Reference levels for SWAB = a.sv and 4.0V

Figure 7. Typical Subcoding Data Output Waveforms

CODEDNRZ-1

0

1

0

0

1

0

0

0

1

0

0

0

0

0

1

0

0

0

0

DECODED EOUIVALENT

ORLJ
Figure 8. Non·Return to Zero (NRZ) Representation

Table 1. Codes Used to Define Subcoding Frame Sync
8·BIT NRZ OATA SYMBOL

14·BIT EQUIVALENT COOE WORO

01

02

03

04

05

06

07

08

Cl

C2

C3

C4

C5

C6

C7

C8

C9

Cl0

Cll

C12

C13

C14

x
x

0
1

0
1

1
1

1
1

1
1

1
0

1
1

0
0

0

1
0

0
0

0
0

0
0

0
0

0
0

0
0

0
1

0
0

0
0

0
1

1
0

P

0

R

S

T

U

V

W

0

NOTE:

Where: X = don't care state.

APPLICATION INFORMATION

EFM Encoding System
The Eight·to·Fourteen Modulation (EFM)
code used in the Compact Disc Digital Audio
system is designed to restrict the bandwidth
of the data on the disc and to present a DC
free signal to the demodulator. In this modula·
tion system, the data run length between
transitions is;;;' 3 clock periods and";; 11
clock periods. The number of bits per symbol
is 17, including three merging and low fre·
quency suppression bits which also assist in
the removal of the DC content.

February 24, 19B7

The conversion from B·bit, non·return·to·zero
(NRZ) symbols to equivalent 14-bit code
words is shown in Table 2, C1 is the first bit of
a 14-bit code word read from the disc and 01
is the Most Significant Bit (MSB) of the data
sent to the error corrector. The 14-bit code
words are given in NRZ-I representation in
which a logic 1 means a transition at the
beginning of that bit from HIGH-to-LOW or
LOW-to-HIGH (see Figure B),
The codes shown in Table 2 cover the normal
256 possibilities for an B-bit data symbol.
There are other combinations of 14-bit codes

7-340

which, although they obey the EFM rules for
maximum and minimum run length (T MAX,
TMIN), produce unspecified data output symbols, Two of these extra codes are used in
the subcoding data to define a subcoding
frame sync and are as shown in Table 1,
When a subcoding frame sync is detected,
the P-bit (Pause-bit) of the data is ignored by
the debounce circuitry, The remaining bits (0
to W) are not specified in the system but
always appear at the serial output as shown
in Table 1,

Signetics linear Products

Product Specification

SAA7210

Decoder for Compact Disc Digital Audio System

Table 2. EFM Code Conversion
NO.

DNZ DATA
SYMBOL
01

0
1
2
3
4
5
6
7
8
9
1a
11
to
119
12a
121
122
123
124
125
126
127

EQUIVALENT CODE WORD
08

C1

NO.

C14

01

0 0 0 0 000
oa 0 0 0 0 0
a a 0 a a a 1
00000 0 1
a a a a a 1 a
a 0 a 0 a 1 0
oa 0 a 0 1 1
a a a a a 1 1
oa a a 1 a a
a a a 0 1 o a
a a 0 a 1 a 1

0
1
a
1
a
1
a
1
a
1
a

0
1
1
1
a
0
a
a
a
1
1

1 a a
o0 0
oa 1
000
1 0 a
a 0 a
a a 1
a 1 a
1 a a
a o a
a a 1

1
0
0
1
a
a
a
a
1
a
a

0 o a
1 0 0
a 0 0
o0 0
1 0 a
1 a 0
a a a
1 a a
a 0 1
a a 1
a a 1

0 a
oa
oa
o0
a a
1 a
a a
a a
a a
o0 a
a a a

a 0 a
000
0 0 0
000
a a a
a 0 a
a 0 a
a a a
a a a
0 a 0
0 0 0

a
a
a
a
a
a
0
a

a
1
a
1
a
1
a
1

a
a
1
1
a
a
a
a

1
0
0
a
1
0
a
a

1
1
a
1
a
1
0
a

a a a
a 0 1
o0 a
0 a 0
0 a a
a a a
o 0 0
a a a

a a a
0 a 1
o0 0
a 0 0
a a a
a a a
a 0 a
a a a

a
a
0
0
a
a
0
0

1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1

a
a
a
a
1
1
1
1

a
a
1
1
a
a
1
1

a
a
a
0
a
a
a
1

0
a
1
0
a
a
1
a

Subcoding Microprocessor
Handshaking Protocol (see
Figures 9, 10, and 11)

1
0
1
1
a
a
1
a
a

1
a
1
1
1
1
1
1

EQUIVALENT CODE WORD

DNZ DATA
SYMBOL

a
a
0
0
a
a
0
a

128
129
130
131
132
133
134
135
136
137
138
139
to
247
248
249
25a
251
252
253
254
255

C1

08

oa
oa

1
1
1
1
1
1
1
1
1
1
1

a
a
0 0 0
0 0 0
a 0 a
0 a 0
a a 0
a a a
a a a
a 0 a
000

a
0
0
0
0
0
a
a
1
1
a

a
0
0
o
1
1
1
1
a
a
o

0
0
1
1
a
a
1
1
a
a
1

0
1
a
1
a
1
a
1
a
1
0

0
1
1
1
0
0
a
a
a
1
1

1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1

a
a
a
0
1
1
1
1

0
a
1
1
a
a
1
1

a
1
a
1
a
1
0
1

a
1
1
1
a
a
o

1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1

o

C14

1

o0

1
a
a
0
1
a
o

a
a
a
1
a
a
a

1
a
a
0
1
a
0
0

a
a
0
0
0
a
a
1

a
a
1
0
a
a
1

1 0 a 0
o1 0 0
o0 0 0
1 000
a 1 a a
a 0 a a
0 a a a
0 1 0 a
1 a a 1
a a a 1
a a a 1

1
1
1
1
1
1
1
1
0
a
a

0
0
0
a
a
a
a
a
a
a

o

0
0
0
a
a
a
a
0
0
a
a

0
0
0
a
0
a
a
a
a
a
a

0
0
0
a
a
a
0
0
a
a
a

1
1
1
1
1
1
1
1
1
1
1

a
a
1
0
0
a
1
0

1
a
a
1
a
1
a
a

a
a
a
a
0
a
a
0

1
1
1
1
1
1
1
1

a
a
a
0
0
a
a
o

a
a
a
0
0
0
a
0

1
1
1
1
1
1
1
1

a
a
a
0
0
a
a
a

o0 0
o0 1
0 o 0

a
a
0
0
a
a
0
o

0
a
a
a
a
a
a
0

a
a
0
0
a
a
0
a

SAA7210

MICROPROCESSOR

The QRA line is normally held LOW by the
microprocessor.
When the microprocessor needs data (Request) it releases the QRA line and allows it
to be pulled HIGH by the pull-up resistor in
the SAA721a.

As soon as the microprocessor has received
sufficient data (not necessarily 80 bits), it
pulls the QRA line LOW again. The SAA7210
now disables the QDATA output and resumes
collecting new O-channel data.

February 24, 1987

30

ODATA

29

OCL

31

-;-

The SAA721a is continuously collecting Qchannel data, and when it detects that QRA is
HIGH, it holds the first frame of Q-channel
data for which the Cyclic Redundancy Check
(CRG) is 'good'. Then the SAA721a pulls
QRA LOW to tell the microprocessor that the
data is ready (Acknowledge) and enables the
QDATA output.
When the microprocessor detects a QRA
LOW signal, it generates a clock signal (QCL)
to shift the data out from the SAA7210 to the
microprocessor via the QDATA output. The
first negative edge of QCL also resets the
acknowledge signal and thus releases the
QRA line.

ORA

DATA
ENABLE
CLOCK

Figure 9. Microprocessor Handshaking Protocol
If the microprocessor does not generate a
OCL Signal within 1a.8ms from the start of the
acknowledge (ORA LOW), the SAA721a resets the acknowledge Signal and allows the
ORA line to go HIGH again. The microprocessor still has 2.3ms to accept the data, which
allows for a long propagation delay in the
microprocessor. After a further 13.33ms the
SAA 7210 will have received a new frame of
O-channel data and, provided the CRC is

7-341

,good', will give a fresh acknowledge Signal.
This refreshing process is repeated until the
microprocessor accepts the data or stops the
request.
When the microprocessor has a requirement
to hold the data for a long period before
acceptance, it prevents the refreshing process by setting OCL LOW after any acknowledge signal.

•

Signetics Linear Products

Product Specification

SAA721 0

Decoder for Compact Disc Digital Audio System

DATA REQUEST
(MICROPROCESSOR
INTERNAL SIGNAL)

11

L
__________

i
:

INTERNAL SIGNAL)

ORA _ _ _ _ _ _

~r----l~1

I-Io..cK

_ _ _ _ _ _ __

~(r--------------~~----------

I

~n=-!j' ~i=-

---------~i~----~~

i
ODATA

....;~

________

I

QCL

lI

I

(SAA7210 _ _ _ _ _ _ _ _......
ACKNOWLEDGE

HIGH IMPEDANCE

IJ

--;';;';;';';;;;;;';:;';";;;=--i\

~ r-~D
~ HIGH IMPEDANCE
~~====.;.;..-

01

Figure 10. Q-Channel Timing Waveforms (Normal Mode)

1•._____________________________--11r--

DATA REOUEST - - - - ,
(MICROPROCESSOR
INTERNAL SIGNAL)

ACKNOWLEDGE
(SAA7210
INTERNAL SIGNAL)

. . .____

~----In

-----.....1

ORA
lACK

-------1--1

OCL

ODA

---------~{~_____________
01 ____________

I

•

THIS WILL REPEAT
UNTIL OCL GOES LOW

j}__{
I

01

~

•

WF19180S

Figure 11. Q-Channel Timing Waveforms (Refresh Mode)

February 24, 1987

7-342

SAA7220

Signetics

Digital Filter for Compact Disc
Digital Audio System
Product Specification
Linear Products

DESCRIPTION
The SAA7220 is a stereo interpolating
digital filter designed for the Compact
Disc Digital Audio system. For descriptive purposes, the SAA7220 is referred
to as the B-chip and the SAA7210 as the
A-chip.

FEATURES
• 16-bit serial data input (two's
complement)
• Interpolated data replaces
erroneous data samples
• -12dB attenuation via the active
Low attenuation input control
(ATSB)

• Smoothed transitions before and
after muting
• Two identical finite impulse
response transversal filters each
with a sampling rate of four
times that of the normal digital
audio data
• Digital audio output of 32-bit
words transmitted in biphasemark code
• 12S data transfer between
SAA7210 and 16-bit dual DAC
(TDA1541)

DESCRIPTION

TOP VIEW

TEMPERATURE RANGE

ORDER CODE

-20·C to + 70·C

SAA7220N

ABSOLUTE MAXIMUM RATINGS
SYMBOL

N Package

APPLICATIONS
• Compact disc digital audio
system
• Digital filter

ORDERING INFORMATION
24-Pin Plastic DIP

PIN CONFIGURATION

RATING

UNIT

Voo

Supply voltage range (Pin 24)

PARAMETER

-0.5 to + 7.0

V

VI

Maximum input voltage range

-0.5 to VDO + 0.5

V

TSTG

Storage temperature range

-65 to +150

·C

-20 to +70

·C

-1000 to + 1000

V

TA

Operating ambient temperature range

YES

Electrostatic handling 1

NOTES:
All outputs are short-circuit protected except the crystal oscillator output.

1. Equivalent to discharging a 100pF capacitor through a 1.5!2 series resistor with a rise time of 15ns.

PIN NO. SYMBOL
DESCRIPTION
WSAB Word select: input from A-chip.
CLAB Clock: input from A-chip; has an
internal pull-up.
DMB Data: input from A-Chip.
EFAB
Error flag: Active-High input from Achip indicating unreliable data. This
input has an internal pull-down.
Not connected.
NC
SCAB Subcode clock: a 10-bit burst clock
2.82 24MHz (typical) input which
synchronizes the subcode data. This
input has an internal pull-up.
7 SDAB Subcode Data: a 10-bit burst of
data, including flags and sync bits
serially input from the A-chip once
per frame clocked by burst clock
input SCAB (see Figure 6). This
input has an internal pull-down.
NC
Not connected.
XSYS System clock output: 11.2896MHz
(typical) output to DAG and to A-chip
as slave clock input.
10 XOUT Crystal oscillator output: drive
output to clock crystal (11.2896MHz
typical).
11 XIN
Crystal oscillator Input: input from
crystal oscillator or slave clock.
12 Vss
Ground: circuit ground potential.
13 TEST Test Input: this input has an internal
pull-down. In normal operation Pin 13
should be open circuit or connected
to Vss.
14 DOBM Digital audio output: this output
contains digital audio samples which
have received interpolation,
attenuation, and muting, plus
subcode data. Transmission is by
biphase-mark code.
15 DABD Data: this output which is fed to the
DAC, together with its clock (CLBD)

~~~f;~~ t~el~~ ~s~~~~u~~~~s,

December 2, 1986

7-343

16
17
18
19
20
21
22

CLBD
NC
WSBD
NC
NC
NC
ATSB

23

!;!iJS§

24

VDD

Figure 5).
Clock: output to DAC.
Not connected.
Word select: output to DAG.
Not connected.
Not connected.
Not connected.
Attenuation: when Active-Low, this
control input provides -12dB
attenuation. This input has an
internal pull-up.
Mute: Active-Low control input with
internal pull-up.
Power supply: positive supply
voltage (+ 5V).

853-1056 86703

•

Signetics Linear Products

Product Specification

Digital Filter for Compact Disc Digital Audio System

SAA7220

BLOCK DIAGRAM
Voo (+5V)

WSAB~~::::::::::~

CLAB C
DAAB 0-7+-----+1

EFAB

r

__~~::::~;:::~_ _ _ _ _~1~8~

l __~~::::~::::------~1~6~

-+______

L-~~~~~~_ _ _ _ _~_ _ _~_ _

12
Vss

December 2, 1986

13
TEST

14
SCAB

SOAB

7-344

DOBM

~~~~~~

_____

WSBD

CLBD

~1=5~DABD

Signetics Linear Products

Product Specification

SAA7220

Digital Filter for Compact Disc Digital Audio System

DC AND AC ELECTRICAL CHARACTERISTICS

VDD = 4.5 to 5.5V; Vss
otherwise specified.

= OV;

TA = _20°C to + 70°C, unless

LIMITS
SYMBOL

PARAMETER

UNIT
Min

Typ

Max

5.0

5.5

Supply
VDD

Supply voltage (Pin 24)

IDD

Supply current (Pin 24)

4.5

V
mA

180

Inputs
WSAB, DAAB
VIL

Input voltage Low

-0.3

+0.8

VIH

Input voltage High

2.0

Voo + 0.5

V

III

Input leakage current

-10

+10

}1A

CI

Input capacitance

7

pF

a

V

EFAB, SDAB 1
VIL

Input voltage Low

-0.3

+0.8

V

VIH

Input voltage High

2.0

Voo + 0.5

V

III
III

Input leakage current
at VI = OV
at VI = Voo

-10
+50

}1A
}1A

CI

Input capacitance

7

pF

CLAB, SCAB, ATSB, MUSB 2
VIL

Input voltage Low

-0.3

+0.8

V

VIH

Input voltage High

2.0

VOO + 0.5

V

III
III

Input leakage current
at VI = OV
at VI = VOD

-30
+10

}1A
}1A

CI

Input capacitance

7

pF

Crystal oscillator (see Figure 7)
Input XIN
Output XOUT
GM

Mutual conductance at 100kHz

Av

Small-signal voltage gain (Av

CI

Input capacitance

10

CFB

Feedback capacitance

5

pF

Co

Output capacitance

10

pF

III

Input leakage current

+10

}1A

= GM

1.5
X Ro)

mAN

VN

3.5

-10

a

pF

Slave clock mode
VI(P,Pl

Input voltage3 (peak-to-peak value)

3.0

Voo + 0.5

V

VIL

Input voltage Low 3

a

1

V

3.0

V DO + 0.5

V

20

ns

20

ns

65

%

VIH

Input voltage High 3

tR

Input rise time 4

tF

Input fall time 4

tHIGH

Input High time at 2V (relative to clock period)

December 2, 1986

7-345

35

Signetics Linear Products

Product Specification

SAA7220

Digital Filter for Compact Disc Digital Audio System

DC AND AC ELECTRICAL CHARACTERISTICS (Continued)

VDD = 4.5 to 5.5V; Vss = OV; TA = -20'C to
unless otherwise specified.

+ 70'C,

LIMITS
SYMBOL

PARAMETER

UNIT
Min

Typ

Max

Outputs
DABD, CLBD, WSBD

VOL

Output voltage Low at IOL = 1.6mA

VOH

Output voltage High at -IOH

CL

Load capacitance

0

= 0.2mA

2.4

0.4

V

VDD

V

50

pF

XSYS5

VOL

Output voltage Low

0

VOH

Output voltage High

2.4

CL

Load capacitance

0.4

V

VDD

V

50

pF

0.6

V

DOBM

VL(P-P)

Voltage across a 75[2 load via attenuator; see Figure 8
(peak-to-peak value)

0.4

NOTES:
1. Inputs EFAB and SDAB both have internal pull-downs.
2. Inputs CLAB, SCAB, ATSB, and MUSB have internal pull-ups.
3. The minimum peak-te-peak voltage can be reduced to 2V if the output XSYS is not being used. Similarly VIH can be reduced to 2.4V (min.). All other levels remain
the same.
4. Reference levels = 10% and 90%.
5. The output current conditions are dependent on the drive conditions. When a crystal oscillator is being used, the output current capability is IOL
IOH = -O.2mA. But if a slave input is being used, the output currents afe reduced to IOL = + O.2mA; IOH = -O.2mA.

= + 1.6mA;

6. Reference levels = O.SV and 2.0V.
7. The signal CLAB can run at either 2.SMHz (~4 system clock) or 1.4MHz (~8 system clock) under typical conditions. It does not have a minimum or maximum
frequency, but is limited to being ~4 or ~8 of the system clock frequency.
8. Input setup and hold times measured with respect to clock input from A-chip (CLAB). Reference levels ~ O.SV and 2.0V.
9. Input setup and hold times measured with respect to subcode burst clock input from A-chip (SCAB). Reference levels ~ O.SV and 2.0V.
10. Output setup and hold times measured with respect to system clock output (XSYS).
11. Output setup and hold times measured with respect to clock output (CLBD).
12. Output rise and fall times measured between the 10% and 90% levels; the data bit pulse width measured at the 50% level.

December 2, 1986

7-346

Signetics Linear Products

Product Specification

Digital Filter for Compact Disc Digital Audio System

SAA7220

FROM TIMING
AND CONTROL
FROM LEFT
ERROR

REGISTER

SCAB

FROM RIGHT ; - - - - - - - - - ,
ERROR
REGISTER

.:6t-<~-40n.
DATA __ ~==

CP

-I --

Ji£Y ~'i1n~~f~~~

~

-

'..!

I

\"I

LE > 35n. > 35n.

LSB_.IS:..

"-'

>5: -- ~
>40n.

Figure 3. Format of Input Signals

November 14. 1986

22

~~~~"Jt

7-358

Signetics Linear Products

Product Specification

14-Bit DAC (Serial Output)

+5V

-5V

TDA1540TD, P

-17V

1 nF
2.5 K

22pF
DATA

CP
LE

22f.,"'''---4-j

1

15

28

17

TDA1540

Figure 4. Application Circuit

November 14, 1986

7-359

TDA1541

Signetics

Dual 16-Bit Digital-to-Analog
Converter
Product Specification

Linear Products
DESCRIPTION

FEATURES

The TDA 1541 is a monolithic integrated
dual 16-bit digital-to-analog converter
(DAC) designed lor use in hi-Ii digital
audio equipment such as compact disc
players, digital tape, or cassette recorders.

• Selectable input format: offset
binary or two's complement
• Internal timing and control circuit
• TTL-compatible digital inputs
• High maximum input bit rate and
fast settling time
• 6Mbits/s data rate
• Low linearity error (l'2 LSB typ.)
• Fast settling (11.1s typ.)

PIN CONFIGURATION
N Package

APPLICATIONS
• Compact disc players
• Digital audio tape, and cassette
recorders and players
• Waveform generation

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

-20°C to + 70°C

TDA1541N

28-Pin Plastic DIP

TOP VIEW

ABSOLUTE MAXIMUM RATINGS
SYMBOL

PARAMETER

RATING

UNIT

+7
-7

VDD
VDDI
VDD2

Supply voltage ranges
Pin 28
Pin 26
Pin 15

-17

V
V
V

TJ

Junction temperature range

-55 to +150

°C

TSTG

Storage temperature range

-65 to +150

°C

TA

Operating ambient temperature range

-20 to +70

°C

YES

Electrostatic handling 1

-1000 to + 1000

V

NOTE:

1. Discharging a 250pF capacitor through a 1kn series resistor.

February 12, 1987

7-360

853-1171 87583

Signetics Linear Products

Product Specification

Dual 16-Bit Digital-to-Analog Converter

TDA1541

BLOCK DIAGRAM
25

r----------------------------------------------------------------r-O

f----If-o

AOL
LEFT OUT

AOR
RIGHT OUT

BCKo-:r----------~r_--~--------_t

CONTROL
&
TIMING

Oil

TWC

27

LE

,

DIGITAL
GROUND

February 12, 1987

7-361

II)

Signetics Linear Products

Product Specification

TDA1541

Dual 16-Bit Digital-to-Analog Converter

DC AND AC ELECTRICAL CHARACTERISTICS VDD = + 5V; VDD1 = -5V; VD02 = -15V; TA = + 25'C; measured in Figure
1, unless otherwise specified.
LIMITS
SYMBOL

UNIT

PARAMETER
Min

Typ

Max

4.0
4.5
14

5.0
5.0
15

6.0
6.0
16

V
V
V

60
75
60

mA
mA
mA

Supply

Voo
-V001
-V002

Supply voltage ranges
Pin 28
Pin 26
Pin 15

100
-1001
-1002

Supply currents
Pin 28
Pin 26
Pin 15

45
45
25

Resolution

16

bits

Inputs

IlL
IIH

input current (Pin 3 and Pin 4)
digital inputs LOW « 0.8V)
digital inputs HIGH (> 2.0V)

TBD
TBD

mA
iJA

ISCK
fSCK
fOAT
Iws

Input frequency
at clock input (Pin 4)
at clock input (Pin 2)
at data inputs (Pin 3 and Pin 4)
at word select input (Pin 1)

6
6
6
200

MHz
MHz
MHz
kHz

CI

Input capacitance of digital inputs

12

pF

Oscillator

losc

Oscillator frequency with internal capacitor

150

200

250

kHz

Analog outputs (AOL; AOR)

VOC

Output voltage compliance

IFS

Full-scale current

±Izs

Zero-scale current

TBD

nA

TCFS

Full-scale temperature coefficient
TA =-20 to +70'C

±200

ppm/'C

E1
E1

Linearity error integral
at TA = 25'C
at TA =-20 to +70'C

0.5
TBD

LSB
LSB

E01
E01

Linearity error differential
at TA = 25'C
at TA=-20 to +70'C

0.5
TBD

SIN

Signal-to-noise ratio + THD1

tcs

Settling time to ± 1 LSB

ex

Channel separation

TBD
3.4

90

80

4.0

TBD

mV

4.6

mA

1

95

LSB
LSB
dB

1

iJs

TBD

dB

-5V

LEI

WS
CONTROL
&
TIMING

:h-=-

TDAl541

15 nF

DATARI
SCK

ADDRESS POINTER
28

Oil
TWC

27

Voo

F-'---<>+5V
LE

22
nF

14

Figure 1. Typical Application

February 12, 1987

VOD2

j=----o-15V

7-364

DIGITAL
GROUND

Signetics Linear Products

Product Specification

Dual 16-Bit Digital-to-Analog Converter

TDA1541

WS

SCK

BCK

DATA

Figure 2. Format of Input Signals; Time Multiplexed at tSCK

= tBCK

(1 2 S Format)

ws

SCK

BCK

DATA

Figure 3. Format of Input Signals; Time Multiplexed at fSCK

=2 X

fBCK

LE--~--~~------~~~-------------I.-tFBRL

t:tRBfL

BCK

DATAL

LSB

DATAR

LSB

Figure 4. Format of Input Signals; Simultaneous Data

February 12, 1987

7-365

MSB

•

TDA5708

Signetics

Photo Diode Signal Processor
Product Specification

Linear Products

DESCRIPTION
The TDA5708 is a bipolar integrated
circuit designed for use in compact disc
players with a single spot read-out system. It amplifies the photo diode signals
and processes the error signals for the
focus and radial control network.

FEATURES
• Data amplifier with equalizer and
AGC
• Offset-free preamplifier with AGC
for the servo signals
• Track loss and drop-out
detection
• Normalizing focus error output
signal to minimize radial error
interference
• Laser supply amplifier and
reference source
• Possibility for car application
• Single and dual supply
application
• TIL compatible digital inputl
outputs
APPLICATION
• Compact disc player

PIN CONFIGURATION
N Package

TOPYIEW

PIN NO. SYMBOL
DEC

DESCRIPTION
Oecoupling bias current HF

part.

ORDERING INFORMATION
DESCRIPTION

V ••

TEMPERATURE RANGE

ORDER CODE

-30·C to +85·C

TDA5708N

28-Pin Plastic DIP (SOT-117)

HFIN

GCHF
FE

ABSOLUTE MAXIMUM RATINGS
PARAMETER

SYMBOL

FELAG

RATING

UNIT

Voo
VGNO
V LM

Supply voltage ranges
Pin 28-Pin 2
Pin 15-Pin 2
Pin 16 (open-loop)

-0.3 to +13
-0.3 to +13
Vss to Voo

V
V
V

-65 to +150

·C

-30 to +85

·C

150

·C

TSTG

Storage temperature range

TA

Operating ambient temperature range

TJ

Operating junction temperature

November 14, 1986

7-366

7,8

04, D3

9, 10

01,02

11

AE,

'2

AE2

13

GCLF

14

LPF

15

GNO

16
17
18
19
20

f[

LM
LO

HFD
Sl

21

AD

22

BEQ

23

BGC

24
25
26
27

DOOS
SC
DET

28

Voo

HFOUT

Negative supply connection
(also substrate connection).
HF current input.

Gain control input of HF
amplifier. Current output from
HF amplitude detector.
Current output of normalized,
switched focus error signal.
Current output of switched
focus error signal, intended for
lag network.
LF photo diode current input.
LF photo diode current input.
Summation of amplified
currents D1 and D2.
Summation of amplified
currents D3 and D4.
Gain control input of LF
amplifiers. Current output from
LF amplitude detector.
Low-pass filter for IRET, used in
track loss (TL) detector and LF
control part (IRET" IRE1 + 'RE2)·
Laser supply ground. Logic
ground.
Laser monitor diode input.
Laser amplifier current output.
Track loss.
High frequency detector output.
On/off control, laser supply
and focus circuitry.
Ready signal output; starting up
procedure finished.
Bias current input for equalizer
and HF input parts.
Bias current input for HF
output part and LF gain
control, TL and FE circuitry.
Drop out detector suppression.
Starting up input.
HF detector voltage input.
HF amplifier and equalizer
voltage output.
Positive supply voltage.

853-0978 86556

Signetics Linear Products

Product Specification

TDA5708

Photo Diode Signal Processor

BLOCK DIAGRAM
V..
YDD
V..
RIEQ

RIGC

8I!Q

lIGe

22

23

I

Hf..
3

GCHF

V.. ~~~4t--'__+-__-4

LPf

v"~r-~Mi4

________________________'

1-__.... .;,18__0

'/[

24

1+---+---0 I5'OlII

13

~--------~~-------;--~Gai

~MNG L~~~~11+______________~
~

PHcmlDIODI!./RE.

R~O-~U~

__________________

I

v..

~

3

RD

r
Detail Specification Supplied Upon Request
November 14, 1986

7-367

TDA5709

Signefics

Radial Error Signal Processor
Product Specification

Linear Products

DESCRIPTION

FEATURES

The TDA5709 is a bipolar integrated
circuit which provides control signals for
the radial motor. These control signals
are generated from radial error signals
received from a photo diode signal processor (TDA570B), and velocity control
signals from the control processor.

• Tracking error processor with
automatic asymmetry control
• AGe circuitry with automatic
start-up and wobble generator
• Tracking control for fast
forward/reverse scan, search,
repeat and pause functions
•. TTL compatible digital input/
output
• Digitized tracking error signal
• Possibility for car application

PIN CONFIGURATION
N Package

C OSC1
C OSC2
V REF

Rose
B3
B2
B1

v••

DAe

APPLICATION
• Compact disc players

TOP VIEW

PIN NO. SYMBOL

ORDERING INFORMATION
DESCRIPTION

1
TEMPERATURE RANGE

ORDER CODE

-30°C to +85°C

TDA5709N

20-Pin Plastic DIP (SOT-146)

RE2
CHPF

REDIG
COFFSET

CAGe

ABSOLUTE MAXIMUM RATINGS
SYMBOL

UNIT

Supply voltage range (VDD - VBB)
Pin 6- Pin 11

-0.3 to + 13

V

TSTG

Storage temperature range

-65 to +150

°C

10

DAC

TA

Operating ambient temperature range

-30 to +85

°C

11

V••

Positive supply voltage
Current output of amplified
(RE2 - RE j ) input currents
Voltage output of integrated
(RE 2 - RE 1) input currents
Integrator capacitor for
(REl - RE2) input currents
Current output for track jumping
(31J2 bits)
Negative supply connection (also
substrate connection)

,.1315

12

80
B1
82
83

16

Rosc

17

VAEF

REOUT
RELAG

TJ

Operating junction temperature

150

°C

8JA

Thermal resistance from junction to
ambient

72

°C/W

CLAG

18
19
20

November 14, 1986

signal

Voo

RATING

VDD- VBB

PARAMETER

7-368

RE,

Input control bits for off, catch,
play status, and DAC output
current

J

COSC2
Cosel

DESCRIPTION
Input for amplified currents from
photo diodes 01 and D2
High"pass filter for RE1 and RE2,
used for radial offset control
Digital output of sign (RE2 - REj)
Offset control input for radial
offset
Gain control Input for radial error

J

Biasing resistor for oscillator
frequency and internal amplitude
Intermediate supply voltage
Frequency setting capacitors for
oscillator
Input for amplified currents from
photo-diodes D3 and D4

853-0979 86556

Signetics Linear Products

Product Specification

Radial Error Signal Processor

TDA5709

BLOCK DIAGRAM

>----+'--oRE our

J---~~,~-~r-OREUG

:0
I

L -_ _......,.'

0-_-+:""

RE,<>-'=+-------j-"t..__-l
8

TEST

NC

ABSOLUTE MAXIMUM RATINGS
RATING

UNIT

Voo

Supply voltage 1

PARAMETER

-0.3 to 7.5

V

VI

Input voltage 1

-0.3 to 7.5

V

Vo

Output voltage 1

-0.3 to 7.5

V

TA

Operating ambient temperature range

-40 to +85

TSTG

Storage temperature range

-55 to + 125

°c
°c

SYMBOL

NOTE:
1. Any pin with respect to Vss.

February 1987

8-7

II

Signetics Linear Products

Objective Specification

CMOS Male/Female Speech Synthesizer

DC AND AC ELECTRICAL CHARACTERISTICS

PCF8200

TA = _45°C to + 85°C; supply voltage (Voo to Vss)
respect to Vss, unless otherwise specified.

= 4.5V

to 5.5V with

LIMITS
SYMBOL

PARAMETER

UNIT
Min

Typ

Max

4.5

5.0

TBD

Supply
Voo

Supply voltage

100

Supply current

10

rnA

IOO(SB)

Standby current

200

IlA

V

Inputs CEN, RN/W, WN, OSCI
VIH

Input voltage HIGH

2.0

Voo

V

VIL

Input voltage LOW

0

0.8

V

IIR

Input leakage current VIN

10

IlA

tRF

Rise and fall times 1

50

ns

CI

Input capacitance

7

pF

=0

10 5.5V

-10

PARALLEL MODE
Input Characteristics (DO to 07)
VIH

Input voltage HIGH

2.0

Voo

V

VIL

Input voltage LOW

0

0.8

V

IIR

Input leakage current (VIN

-10

10

IlA

CI

Input capacitance

7

pF

=0

to 5.5V, output off)

Output Characteristics (05 to 07 only)
VaH

Output voltage HIGH (lOH

VOL

Output voltage LOW (IOL

= -1 001lA)
= 3.2mA)

3.5

Voo

V

0

0.4

V

CL

Load capacitance

80

pF

tRF

Rise and fall times2

50

ns

SERIAL MOOE
Input Characteristics (SOA and SOL)
VIH

Input voltage HIGH

3.0

Voo

V

VIL

Input voltage LOW

0

1.5

V

IIR

Input leakage current
(VIN = 0 to 5.5V, output off)

-10

10

IlA

CI

Input capacitance

10

pF

0.4

V

TBD

MHz

Output Characteristics (SOA only, open·drain)
VOL

Output voltage LOW (IOL

= 3mA)

0

OSCILLATOR
Crystal frequency

TBD

VREF

Reference voltage

1.9

IIR

Input leakage current

fXTAL

6

VREF

February 1987

Voo-1.5
1.25

TBD

8·8

V

Objective Specification

Signetics Linear Products

CMOS Male jFemale Speech Synthesizer

PCF8200

DC AND AC ELECTRICAL CHARACTERISTICS (Continued) TA = -45"C to +85"C; supply voltage (Voo to
Vss) = 4.5V to 5.5V with respect to Vss. unless
otherwise specified.
LIMITS
SYMBOL

PARAMETER

UNIT
Min

Typ

Max

Outputs REQN. BUSY

= 1001lA)
= 3.2mA)

V

3.5

Voo

0

0.4

V

Load capacitance

80

pF

Rise and fall times 2

50

ns

VOH

Output voltage HIGH (IOH

Val

Output voltage LOW (IOl

Cl
tRF
OUT

VOUT

Output voltage

1.34 X VAEF

0.66 X VREF

Minimum external load

V

600

n

Timing characteristics 3

tWR

Write enable

200

ns

tos

Data setup for write

150

ns

tOH

Data hold for write

30

ns

tAD

Read enable

200

too

Data delay for read 1

150

ns

tOF

Data floating for read 1

150

ns

tcs

Control setup

0

tCH

Control hold

0

tRN

REO new (new byte of the same speech frame)

tRV

REO Valid

tRH

REO Hold

ns

ns
ns
TBD

liS

0

ns
250

TBD

ns

NOTES:
1. Levels greater than 2V for a '1' or less than O.BY for a '0' are reached with a load of one TIL input and 50pF.

2. Rise and fall times between O.6V and 2.2V levels.
3. Timing reference level is 1.5V; supply 5V ± 10%; temperature range of _40DC to 85°C.

•
February 1987

8-9

Objective Specification

Signetics Linear Products

PCF8200

CMOS Male/Female Speech Synthesizer

FUNCTIONAL DESCRIPTION
The synthesizer has been designed for a
vocal tract modelling technique of voice synthesis. An excitation signal is fed to a series
of resonators. Each resonator simulates one
of the formants in the original speech. It is
controlled by two parameters, one for the
resonant frequency and one for the bandwidth. Five formants are needed for male
speech and four for female speech. The
output of this system is defined by the excitation signal, the amplitude values and the
resonator settings. By periodic updating of all
parameters very high quality speech can be
produced.

OPERATION
Speech characteristics change quite slowly;
therefore, the control parameters for the

speech synthesizer can be adequately updated every few tens of milliseconds with
interpolation during the interval to ensure a
smooth changeover from one parameter value to the next. In the PCF8200 the standardframe duration can be set to 8.8, 10.4, 12.8 or
17.6 milliseconds with the speed option,
speaking speed, in the command register.
The duration of each individual speech frame
is programmable to be 1, 2, 3 or 5 times the
standard frame duration.
The excitation signal is a random noise
source for unvoiced sounds and a programmable pulse generator for voiced sounds.
Both sources have an amplitude modulator
which is updated 8 times in one speech-frame
by linear interpolation. The pitch is updated
every 1;8 of a standard frame.

The excitation signal is filtered with a five
formant filter for male speech and a four
formant filter for female speech. The formant
filter is a cascade of all second-order sections. The control parameters, formant-frequency and formant-bandwidth, are updated
eight times per speech frame by linear interpolation. A block diagram of the formant
synthesizer is shown in Figure 1The filter output is upsampled to 80kHz and
filtered with a digital low-pass filter. Before
the signal is digital to analog converted
(DAC), with an 11-bit switched capacitor DAC,
the signal is multiplied with a DAC-amplitude
factor. The use of a digital filter means that no
external audio filtering is required for lowmedium applications and minimal filtering is
required for those applications requiring very
high quality speech.

Table 1. Frame Duration as a Function of Speed-Option
(FS1, FSO) and Frame-Duration (FD1, FDO).
10

01

00

11

FS1, FSO

00

8.8

10.4

12.8

17.6

ms

01

17.6

20.8

25.6

35.2

ms

10

26.4

31.2

38.4

52.8

ms

11

44.0

52.0

64.0

88.0

ms

FD1, FDO

AN

SPEECH
OUT

PULSE
GENERATOR

Figure 1. Block Diagram of Formant Synthesizer

February 1987

8-10

Signetics Linear Products

Objective Specification

CMOS Male/Female Speech Synthesizer

DATA FORMAT
Three types of format are used for data
transfer to the synthesizer.

DAC Amplitude Factor
The DAC amplitude factor is one byte, which
is used to optimize the digital speech signal to
the 11-bit DAC. It is the first byte after a STOP
or a BADSTOP or Voo on. Table 2 indicates
the amplitude factor.

Start Pitch
The second byte after a STOP or BADSTOP,
or Voo on is the start pitch. It is a one-byte
start value for the on-chip pitch-period generator.
The frame data is a five-byte block which
contains the filter and source information.
The frame data bits are organized as shown
in Figure 2.

PCF8200

Table 2. DAC Amplitude Factor
BYTE

FACTOR

01110000
10110000
00110000
11010000
01010000
10010000
00010000
11100000
01100000
10100000
00100000
11000000
01000000
10000000
00000000
11110000

dB

3.5
10.88
3.25
10.24
9.54
3.0
2.75
8.97
7.96
2.5
2.25
7.04
2.0
6.02
1.75
4.86
1.5
3.52
1.25
1.94
1.0
0.00
-2.50
0.75
0.5
-6.02
-12.04
0.25
0.0
HEX code FO is not allowed as a DAC amplitude

Frame Data
Pitch increment! decrement value
Amplitude
Frame duration
Frequency of 1st formant
Frequency of 2nd formant
Frequency of 3rd formant
Frequency of 4th formant
Frequency of 5th formant
Bandwidth of 1st formant
Bandwidth of 2nd formant
Bandwidth of 3rd formant
Bandwidth of 4th formant
Bandwidth of 5th formant

07
Bl

BVTEol

BYTEll

21

FOI

BVTE31

FOO

BVTE

BVTul

+

FS

:

I

~3

~

I

F3

I
F4

NOTE:
It is not allowed to set byte 0 to the hexidecimal value EO.

Figure 2. Format of Frame-Data

February 1987

8-11

!

Objective Specification

Signetics Linear Products

CMOS Male/Female Speech Synthesizer

CONTROL FORMAT
Command Write

PCF8200

BYTEol

FSO, FS1 Speed Option

BYTE·I

FS1

FSO

SPEECH
SPEED

STANDARD
FRAME
DURATION

0
0
1
1

0
1
0
1

100%
123%
145%
73%

12.Bms
10.4ms
B.8ms
17.6ms

"EO"

STOP

Status Read
Three status bits can be read out at any time
without a preceding byte (EO). This is shown
in Figure 4.
REON = 1 No data required
= 0 Synthesizer requesting new data
BUSY = 1 Busy (an utterance is pronounced)
= 0 Idle; REON will set to 1; (the
synthesizer is in STOP or BADSTOP mode)
STOP

The STOP bit is the same as the
stop bit written to the synthesizer
during a command write.
STOP = I, BUSY = 0 (stopped by
the user).
STOP = 0, BUSY = 0 (BADSTOP
because the data was not sent in
time).
Aiter initial power-up the status/command
register is set to the following status:
FSO, FSI = 0 Standard-frame duration of
t2.8ms
MN/F

= 0 Male quantization table

STOP

=1

February 1987

FS'

FSO

DO

D7
REQN

BUSY

STOP

x

x

Figure 4. Status Read

MN/F = 0 male quantization table
= 1 female quantization table
STOP = 1 stop; repeat last complete frame
with amplitude = 0 (no excitation
signal)
= 0 if the frame data is not sent within
the duration of a half frame, there
will be a BADSTOP:
1. REON = 1; STOP = 0
2. Repeat last frame with amplitude = 0
3. BUSY=O

MN/F

Figure 3. Control Write: First Byte Fixed, Second Byte Control

MN/F, Male/Female Option

STOP

I
I

DO

D7

A command write consists of two bytes, and it
may occur before a data block. The four bits
which can be written are shown in Figure 3.

BUSY

= 0 Idle

POWER-UP

REON

= 1 No data required

The synthesizer will be set to power-up on a
parallel-write sequence.

INTERFACE PROTOCOL
Data can be written to the synthesizer when
REON = 0, or when REON = 1 and BUSY = O.
Figure 5 shows the interiace protocol of the
synthesizer.
In parallel mode the synthesizer is activated
by sending the DAC-amplitude factor. In serial
mode the DAC-amplitude factor can be sent
as soon as the synthesizer is powered-up.
The 12C transmitter/receiver will then acknowledge. When the request for the pitchbyte occurs, the byte must be provided within
the duration of a hal! standard frame. I! the
byte is not provided in time, a BADSTOP will
be generated.
During each data write operation, the status
bit REON will be set to 'I'. Within a frame
data block, it disappears within a few microseconds, asking for the next byte of that
block. I! the bytes of frame data are not
provided within the time-duration of a hal!
frame, a BADSTOP will be generated.

12C ADDRESS
On chip there is an 12 C slave receiver/
transmitter with the address:

PAR mode: The input latches are active so
they can receive the first byte
SER mode: The 12 C transmitter/receiver will
not acknowledge until the synthesizer has powered-up. To power
up the synthesizer, a parallel
write sequence (Figure 7) must
be made to the synthesizer by
using external logic for the control lines; at least one line must
be toggled, CEN, while WN = 0
and RN/W = 1.
The synthesizer can be set to
permanent power-up by hardwired control pins (CEN = 0, RN/
W= 1, WN =0).

POWER-DOWN MODE
When BUSY = 0 the synthesizer will be set to
power-down. In the power-down mode the
status/command register will be retained.
In power-down mode the clock-oscillator is
switched off. After initial Voo the synthesizer
is in power-down mode.

SERN/PAR
SERN/PAR is hard-wired to Voo or Vss.

76543210

o0

1 0 0 00 R/W

HANDLING
All inputs and outputs are protected against
electrostatic charge under normal handling
conditions.

8-12

Signetics Linear Products

Objective Specification

CMOS Male/Female Speech Synthesizer

PCF8200

Figure 5. Interface Protocol

Timing Diagrams
The control signals CEo R/W and W have
been specified to enable easy interface to

most microprocessors and microcomputers.
For instance. with connection to an MAB8048

microcomputer. the R/W and W inputs can
be used as the RD and WR strobe inputs.

TYPICAL CONNECTION OF CONTROL SIGNALS
CE = O - - - - - . O R - - - - - - w =0

W~CE~
iiiw-------,

\'---

February 1987

8-13

II
I

Signetics Linear Products

Objective Specification

PCF8200

CMOS Male/Female Speech Synthesizer

CE
CEUSED
ASST~BE
Woo

{
RIW

IW
RIW USED AS
{
READ STROBE

CE-o
W

~--------t-~--~~r-----Figure 6. Read Timing

CEUSED{CE

ASST~BE

WOo

IIIW

~~~~~f~ ----~
CE-O

W

D~D7

1'----'

_ _ _ _~_~j-~~~~

____

DATA
WRITE

Figure 7. Write Timing

ADDRESS

)I

VOICE
ROM

DJ

DATA

I'--

DATA

MICROPROCESSOR

OUT
CEN. RNIW. WN
REQN
BUSY
PCF8200

-

SYNTHESIZER

Figure 8. Typical Application Configuration with Parallel Interface

February 1987

8-14

Objective Specification

Signetics Linear Products

PCF8200

CMOS Male/Female Speech Synthesizer

ADDRESS

"I
)I
'I

VOICE
ROM

UJ

DATA

"MICROPROCESSOR

SDA

1"<:

OUT

SCL
PCFB200

-

SYNTHESIZIR

Figure 9. Typical Application Configuration with Series Interface

VREF I - -....---+---~47 nF

PCF8200
SYNTHESIZER

RL =25fl

Po = 140 mW
(PEAK)

Figure 10. An Example of an Output Configuration

PCF8200

PCF8200

TTL
CLOCK

Figure 11. Oscillator Clock Configurations

NC

..
I

February 1987

8-15

SAA1099

Signetics

Stereo Sound Generator for
Sound Effects and Music
Synthesis
Linear Products

Product Specification

DESCRIPTION

FEATURES

The SAA 1099 is a monolithic integrated
circuit designed for generation of stereo
sound effects and music synthesis.

• Six frequency generatorseight octaves per generator;
256 tones per octave
•
•
•
•
•

PIN CONFIGURATION
N Package
VDD

Two noise generators
Six noise/frequency mixers
Twelve amplitude controllers
Two envelope controllers
Two 6-channel mixers/current
sink analog output stages

• TTL input compatible
• Readily interfaces to S-bit
microcontroller
• Minimal peripheral components
• Simple output filtering

07
06

AD

05
04
03
02
01
00
TOPV1EW
CD11500S

PIN NO. SYMBOL

DESCRIPTION

WR

APPLICATIONS
•
•
•
•

Consumer games systems
Home computers
Electronic organs
Arcade games

• Toys
• Chimes/alarm clocks

ORDERING INFORMATION
DESCRIPTION

TEMPERATURE RANGE

18-Pin Plastic DIP (SOT-102CS)

o to

ORDER CODE

+70°C

SAA1099PN

ABSOLUTE MAXIMUM RATINGS
SYMBOL

RATING

UNIT

VDD

Supply voltage (Pin 18)

PARAMETER

-0.3 to + 7.5

V

VI
VI

Maximum input voltage
at VDD = 4.5 to 5.5V

-0.3 to +7.5
-0.5 to 7.5

V
V

10

Maximum output current

10

mA

PTOT

Total power dissipation

450

mW

-65 to + 125

°C

TSTG

Storage temperature range

TA

Operating ambient temperature range

YES

Electrostatic handling 1

o to

+70

-1000 to + 1000

°C

10-17
18

Write Enable: Active-LOW input
which operates in conjunction
with CS and AO to allow writing
to the internal registers.
CS
Chip Select: Active-LOW input
to identify valid ~ inputs to
the chip. This input also
operates in conjunction with
WR and AO to allow writing to
the internal registers.
AO
Controll Address select: input
used in conjunction with WR
and i3'S to load data to the
control register (AO = 0) or the
address buffer (AO = 1).
OUTR
Right channel output: a ?-level
current sink analog output for
the 'right' component. This pin
requires an external load
resistor.
OUTl
Left channel output: a 7-level
current sink analog output for
the 'left' component. This pin
requires an external load
resistor.
Reference current supply:
IREF
used to bias the current sink
outputs.
DTACK Data Transfer Acknowledge:
open-drain output. Active-LOW
to acknowledge successful data
transfer. On completion of the
cycle DTACK is set to inactive.
elK
Clock: input for an externallygenerated clock at a nominal
frequency of 6MHz.
Ground: OV.
vss
00-07 Data: Data bus input.
Power supply: + 5V typical.
VDD

V

NOTE:

1. Equivalent to discharging a 250pF capacitor through a 1kn series resistor.

November 21. 1986

8-16

853-0989 86656

Signetics Linear Products

Product Specification

Stereo Sound Generator for
Sound Effects and Music Synthesis

SAA1099

BLOCK DIAGRAM
VDD
(+5 V

AO

CTACK

TYP.)

Vss

LEFT
OUTPUT

01
02

D:~:

03

INPUT

04

1"
05

o.
07

10
11
12

,.

13

LINE
DRIVERS

,.

8

15

17

TO FREQUENCY ANO

NOISE REGISTERS

RIGHT

INTERNAL

elK

OUTPUT

CLOCKS
(4 MHz)

II
November 21, 1986

8-17

Signetics Linear Products

Product Specification

Stereo Sound Generator for
Sound Effects and Music Synthesis

SAA1099

DC ELECTRICAL CHARACTERISTICS Voo = 5V; TA = 0 to 70·C, unless otherwise specified.

I

LIMITS

SYMBOL

PARAMETER

UNIT

Min

Typ

Max

4.5

5.0

5.5

V

55

90

mA

250

400

iJ.A
V

Supply
Voo

Supply voltage

100

Supply current

IREF

Reference current 1

100

Inputs
VIH

Input voltage HIGH

2.0

6.0

Vil

Input voltage LOW

-0.5

0.8

V

±Iu

Input leakage current

10

iJ.A

CI

Input capacitance

10

pF

0.4
6.0
10
150
10

V
V
pF
pF

iJ.A

90
85

125
120

%
%
%
%

Outputs
VOL
V7- 9
Co
Cl
-ILO

DTACK (open-drainf
Output voltage LOW at IOl = 3.2mA
Voltage on Pin 7 (OFF state)
Output capacitance (OFF state)
Load capacitance
Output leakage current (OFF state)

0
-0.3

Audio outputs (Pins 4 and 5)
1011REF
los/6 X IREF

With fixed IREF3
One channel on
Six channels on

101/IREF
los/6 X IREF
101
los

With IREF = 250I1A; Rl = 1.lkn (±5%)
One channel on
Six channels on
Output current one channel on
Output current six channels on

95
90
238
1.38

115
110
288
1.65

mA

101
los

With resistor supplying IREF 4
Output current one channel on
Output current six channels on

155
0.94

270
1.65

I1A
mA

600
10

iJ.A

Rl

Load resistance

-ILO

DC leakage current all channels off

± lOMAX

Maximum current difference betWeen left and right
current sinks5

SIN

Signal-to-noise ratioS

November 21, 1986

n

15
TBD

8-18

iJ.A

%
dB

Signetics Linear Products

Product Specification

Stereo Sound Generator for
Sound Effects and Music Synthesis

SAA1099

AC ELECTRICAL CHARACTERISTICS Voo = 5V; TA = a to 70°C; liming measuremenls laken al 2.0V for a logic 1 and
0.8V for a logic 0, unless olherwise specified (see waveforms Figures 1 and 2).
LIMITS
SYMBOL

PARAMETER

UNIT
Min

Typ

Max

Bus interface timing (see Figure 1)
lAse

AO selup lime 10 CS fall

0

ns

Icsw

CS LOW 10 WR fall

30

ns

tAsw

AO selup lime 10 WR fall

50

ns

IWL

WR LOW lime

100

ns

Issw

Data bus valid 10 WR rise

100

IOFW

DTACK fall delay from WR fall 7

0

IAHW

AO hold lime from WR HIGH

a

ICHW

CS hold time from WR

0

ns

IOHW

Data bus hold time from WR HIGH

a
a

ns

HIGH

ns
85

ns
ns

IORW

DTACK rise delay from WR HIGH

ICY

Bus cycle timeS

2CP

100

ICY

Bus cycle lime 9

8CP

ns

Clock input liming (see Figure 2)
leLK

Clock period

120

tHIGH

Clock LOW lime

55

125

255

ns

ns

lLOW

Clock HIGH lime

55

ns

NOTES:

1. Using an external constant current generator to provide a nominal IREF or external resistor connected to Voo.
2. This output is short-circuit protected to Voo and Vss.

3. Measured with IREF a constant value between 100 and 400!lA; load resistance (RL) allowed to match E24 (5%) in all applications via:
0.27775± 0.03611

RL=-----IREF
4. Measured with RREF = 10kn (± 5%) connected between IREF and Voo; RL = 820n (± 5%); OUTR and OUTL short-circuit protected to Vss.
5. Left and right outputs must be driven with identical configuration.
6. Sample tested value only.
7. This timing parameter only applies when no wait states are required; otherwise, parameter is invalid.
S. The minimum bus cycle time of two clock periods is for loading all registers except the amplitude registers.
9. The minimum bus cycle time of eight clock periods is for loading the amplitude registers. In a system using DTACK it is possible to achieve minimum times of
500ns. Without DTACK the parameter given must be used.

)
tAHW-----i

*-tASCTfcswtASW

r-~L--L

tasw

'oHw

.~"-

November 21, 1986

:1
toRW

Figure 1. Bus Interface Waveforms

8-19

:t

tCHW

•
I

Product Specification

Signetics Linear Products

Stereo Sound Generator for
Sound Effects and Music Synthesis

SAA1099

The following sections provide a detailed
functional description of the SAA 1099 as
shown in the block diagram.

Each mixer channel has one of the frequency
generator outputs fed to it. Three channels
use noise generator 0 and the other three use
noise generator 1.

Frequency Generators

Amplitude Controllers

Six frequency generators can each select one
of 8 octaves and one of 256 tones within an
octave. A total frequency range of 30Hz to
7.74kHz is available. The outputs may also
control noise or envelope generators. All
frequency generators have an enable bit
which switches them on and off, making it
possible to preselect a tone and to make it
inaudible when required.

Each of the six channel outputs from the
mixer is split up into a right and left component giving effectively twelve amplitude controllers. An amplitude of 16 possible levels is
assigned to each of the twelve signals. With
this configuration a stereo effect can be
achieved by varying only the amplitude component. The moving of a sound from one
channel to the other requires, per tone, only
one update of the amplitude register contents.

FUNCTIONAL DESCRIPTION

The frequency ranges per octave are:
Octave
Frequency range
30Hz to 60Hz
o
60Hz to 122Hz
2
122Hz to 244Hz
3
244Hz to 488Hz
4
489Hz to 976Hz
5
978Hz to 1.95kHz
6
1.95kHz to 3.90kHz
7
3.91kHz to 7.81kHz

Noise Generators

When an envelope generator is used, the
amplitude levels are restricted. The number
of levels available is then reduced to eight.
This is achieved by disabling the least significant bit (LSB) of the amplitude control.

Envelope Controllers
Two of the six tone generators are under
envelope control. This applies to both the left
and right outputs from the tone generator.

The two noise generators both have a pro·
grammable output. This may be a software
controlled noise via one of the frequency
controlled generators or one of three predefined noises. There is no tone produced by
the frequency generator when it is controlling
the noise generator. The noise produced is
based on double the frequency generator
output, i.e., a range of 61 Hz to 15.6kHz. In the
event of a pre-defined noise being chosen,
the output of noise generator 0 can be mixed
with frequency generator 0, 1 .and 2; and the
output of noise generator 1 can be mixed with
frequency generator 3, 4, and 5. In order to
produce an equal level of noise and tone
outputs (when both are mixed) the amplitude
of the tone is increased. The three predefined noises are based on a clock frequency of 7.8kHz, 15.6kHz or 31.2SkHz.

The envelope has the following eight possible
modes:
• Amplitude is zero

Noise/Frequency Mixers

There is also the capability of controlling the
'right' component of the channel with inverse
of the 'left' component, which remains as
programmed.

There are six noiselfrequency mixers, each
with four selections:
• Channel off
• Frequency only

• Single attack
• Single decay
• Single attack-decay (triangular)
• Maximum amplitude
• Continuous attack
• Continuous decay
• Continuous attack-decay
The timing of the envelope controllers is
programmable using one of the frequency
generators (see Block Diagram). When the
envelope mode is selected for a channel its
control resolution is halved for that channel
from 16 levels to 8 levels by rounding down to
the nearest even level.

• Noise only
• Noise and frequency

November 21, 1986

8-20

A direct enable permits the start of an envelope to be defined, and also allows termination of an envelope at any time. The envelope
rate may be controlled by a frequency channel (see Block Diagram), or by the microprocessor writing to the address buffer register. If
the frequency channel controlled is OFF
(NE = FE = 0) the envelope will appear at the
output, which provides an alternative 'nonsquare' tone capability. In this event, the
frequency will be the envelope rate which,
provided the rate is from the frequency channel, will be a maximum of 1kHz. Higher
frequencies of up to 2kHz can be obtained by
the envelope resolution being halved from 16
levels to 8 levels. Rates quoted are based on
the input of an 8MHz clock.

Six-Channel Mixers/Current Sink
Analog Output Stages
Six channels are mixed together by the two
mixers, allowing each one to control one of
six equally weighted current sinks to provide a
seven level analog output.

Command/Control Select
In order to simplify the microprocessor interface, the command and control information is
multiplexed. To select a register in order to
control frequencies, amplitudes, etc., the
command register has to be loaded. The
contents of this register determine to which
register the data is written in the next control
cycle. If a continuous update of the control
register is necessary, only the control information has to be written (the command
information does not change).
If the command/control select (AD) is logic 0,
the byte transfer is control; if AO is logic 1, the
byte transfer is command.

Interface to Microprocessor
The SAA 1099 is a data bus based I/O
peripheral. Depending on the value of the
command/control signal (AD) the CS and WR
signals control the data transfer from the
microprocessor to the SAA1099. The data
transfer acknowledge (DTACK) indicates that
the data transfer is completed. When, during
the write cycle, the microprocessor recognizes the DTACK, the bus cycle will be
completed by the processor.

Signetics Linear Products

Product Specification

Stereo Sound Generator for
Sound Effects and Music Synthesis

SAA1099

elK

Figure 2. Clock Input Waveform

APPLICATION INFORMATION
Device Operation
The SAA 1099 uses pulse-width modulation to
achieve amplitude and envelope levels. The
twelve signals are mixed in an analog format
(6 'left' and 6 'right') before leaving the chip.
The amplitude and envelope signals chop the
output at a minimum rate of 62.5kHz, compared with the highest tone output of
7.74kHz. Simple external low-pass filtering is
used to remove the high frequency components.
Rates quoted are based on the input of an
8M Hz clock.
A data bus-based write only structure is used
to load the on-board registers. The data bus
is used to load the address for a register, and
subsequently the data to that register. Once
the address is loaded, multiple data loads to
that register can be performed.

The selection of address or data is made by
the single address bit AO, as shown in register
maps Table 1 and Table 2.
The bus control signals WR and CS are
designed to be compatible with a wide range
of microprocessors. A OTACK output is included to optimize the interface with an
S68000 series microprocessor. In most bus
cycles OTACK will be returned immediately.
This applies to all register address load cycles and all except amplitude data load cycles. With respect to amplitude data, a number of wait cycles may need to be performed,
depending on the time since the previous
amplitude load. OTACK will indicate the number of required waits.

Register Description (See
Tables 2 and 3)
The amplitudes are assigned with 'left' and
'right' components in the same byte, on a
channel-by-channel basis. The spare locations that are left between blocks of registers

is to allow for future expansion. and should be
written as zeroes. The tone within an octave
is defined by eight bits and the octave by
three bits. Note that octaves are paired (0/1,
2/3, etc.). The frequency and noise enables
are grouped together for ease of programming. The controls for noise 'color' (clock
rate) are grouped in one byte.
The envelope registers are positioned in adjacent locations. There are two types of envelope controls: direct acting controls and buffered controls. The direct acting controls always take immediate effect, and are:
• Envelope enable (reset)
• Envelope resolution (16/8 level)
The buffered controls are acted upon only at
the times shown in Figure 3 and control
selection of:
• Envelope clock source
• Waveform type
• Inverted/non-inverted 'right' component

Table 1. External Memory Map
SELECT
AO

0
1

DATA BUS INPUTS
OPERATIONS

07

06

05

04

03

02

01

DO

07
X

06
X

05
X

04
A4

03
A3

02
A2

01
Al

DO
AO

Oata for internal registers
Internal register address

NOTE:
Where X = don't care state.

•
November 21, 1986

8-21

Signetics Linear Products

Product Specification

Stereo Sound Generator for
Sound Effects and Music Synthesis

SAA1099

Table 2. Internal Register Map
REGISTER
ADDRESS

DATA BUS INPUTS
OPERATIONS

07

06

05

04

03

02

01

DO

00
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
OF
10
11
12
13
14
15
16

AR03
1
2
3
4
5
X
X
F07
1
2
3
4
F57
X
X
X
X
X
X
X
X
X

AR02
1
2
3
4
5
X
X
F06
1
2
3
4
F56
X
X
012
032
052
X
X
X
X

AROl
1
2
3
4
5
X
X
F05
1
2
3
4
F55
X
X
011
031
051
X
FE5
NE5
Nll

AROO
1
2
3
4
5
X
X
F04
1
2
3
4
F54
X
X
010
030
050
X
FE4
NE4
Nl0

AL03
1
2
3
4
5
X
X
F03
1
2
3
4
F53
X
X
X
X
X
X
FE3
NE3
X

AL02
1
2
3
4
5
X
X
F02
1
2
3
4
F52
X
X
002
022
042
X
FE2
NE2
X

ALOl
1
2
3
4
5
X
X
FOl
1
2
3
4
F51
X
X
001
021
041
X
FEl
NEl
NOl

ALOO
1
2
3
4
5
X
X
FOO
1
2
3
4
F50
X
X
000
020
040
X
FEO
NEO
NOO

17
18
19
lA
lB
lC

X
E07
E17
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X

X
E05
E15
X
X
X
X
X
X

X
E04
E14
X
X
X
X
X
X

X
E03
E13
X
X
X
X
X
X

X
E02
E12
X
X
X
X
X
X

X
EOl
E11
X
X
X
X
X
X

X
EOO
El0
X
X
SE
X
X
X

10
lE
IF

Amplitude
Amplitude
Amplitude
Amplitude
Amplitude
Amplitude

0
1
2
3
4
5

right channel; left channel
right/left
right/left
right/left
right/left
right/left

Frequency
Frequency
Frequency
Frequency
Frequency
Frequency

of
of
of
of
of
of

8-22

0
1
2
3
4
5

Octave 1; octave 0
Octave 3; octave 2
Octave 5; octave 4
Frequency enable
Noise enable
Noise generator 1;
Noise generator 0
Envelope generator 0
Envelope generator 1

Sound enable (all channels)

NOTE:
Where:
All don't cares (X) should be written as zeroes.
00 to 1F block of registers repeats eight times in the block between addresses 00 to FF (full internal memory map).

November 21, 1986

tone
tone
tone
tone
tone
tone

Product Specification

Signetics Linear Products

Stereo Sound Generator for
Sound Effects and Music Synthesis

SAA1099

Table 3. Register Description
BIT

DESCRIPTION

ARn3; ARn2;
ARn1; ARnO
(n = 0.5)

4 bits for amplitude control
of right channel
o 0 0 0 minimum amplitude (off)
1 1 1 1 maximum amplitude

ALn3; ALn2;
ALn1; ALnO
(n = 0.5)

4 bits
of left
o0 0
1 1 1

for amplitude control
channel
0 minimum amplitude (off)
1 maximum amplitude

Fn7 to FnO
(n = 0.5)

8 bits
of the
o0 0
1 1 1

for frequency control
six frequency generators
0 0 0 0 0 lowest frequency
1 1 1 1 1 highest frequency

On2; On1;
OnO
(n = 0.5)

3 bits for octave control

FEn
(n = 0.5)

Frequency enable bit (one tone per generator)
FEn = 0 indicates that frequency 'n' is off

NEn
(n = 0.5)

Noise enable bit (one tone per generator)
NEn = 0 indicates that noise 'n' is off

Nn1; NnO
(n = 0.1)

2 bits for noise generator control.
These bits select the noise generator rate (noise 'color')
Nn1 NnO Clock frequency (kHz)
0
0 31.3
0
1 15.6
1
0
7.6
1
1 61 to 15.6 (frequency generator 0/2)

000 lowest octave
001
01 0
o 1 1
01 1
1 00
1 o1
1 1 0
111 highest octave

(30Hz to 60Hz)
(60Hz to 122Hz)
(122Hz to 244Hz)
(244Hz to 488Hz)
(244Hz to 488Hz)
(489Hz to 976Hz)
(978Hz to 1.95kHz)
(1.95kHz to 3.90kHz)
(3.91 kHz to 7.81 kHz)

•
November 21, 1986

8-23

Signetics Linear Products

Product Specification

Stereo Sound Generator for
Sound Effects and Music Synthesis

SAA1099

Table 3. Register Description (Continued)
BIT

En7;
En5 to EnO
(n = 0.1)

SE

DESCRIPTION

7 bits for envelope control
EnO
o Left and right component have the same envelope
1 Right component has inverse of envelope that is applied to
left component
En3 En2 En2
0
0
0
Zero amplitude
0
0
1
Maximum amplitude
0
1
0
Single decay
1
1
Repetitive decay
0
1
0
0
Single triangular
0
1
Repetitive triangular
1
0
Single attack
1
1
1
1
1
Repetitive attack
En4
0 4 bits for envelope control (maximum frequency = 976Hz)
1 3 bits for envelope control (maximum frequency = 1.95kHz)
En5
0 Internal envelope clock (frequency generator 1 or 4)
1 External envelope clock (address write pulse)
En7
0 Reset (no envelope control)
1 Envelope control enable
SE sound enable for all channels
(reset on power-up to 0)
0 All channels disabled
1 All channels enabled

NOTE:
All rates given are based on the input of an 8MHz clock.

November 21, 1986

8-24

Signetics Linear Products

Product Specification

Stereo Sound Generator for
Sound Effects and Music Synthesis

ENVELOPE

ENVELOPE

GENERATOR INACTIVE
(EN7 • 0)

GENERATOR ACTIVE
(EN7 1)

~

EN3

EN2

EN1

o

0

SAA1099

ENO

__________

=________

~l

~

_"B(2)
~===========~

A

B

(2)

c

~~==~==r===:r==~ (2)
D

G

H

NOTES:
1. The level at this time is under amplitude control only (En7 = 0; no envelope).
2. When the generator is active (En7 = 1) the maximum level possible is 1~16 of the amplitude level, rounded down to the nearest eight. When the generator is inactive (En = 0) the level
will be 11f16 of the amplitude level.
3. After position (3) the buffered controls will be acted upon when loaded.
4. At position (4) the buffered controls will be acted upon if already loaded.
5. Waveforms 'a' to 'h' show the left channel (EnD = 0; left and right components have the same envelope.)
Waveform 'j' shows the right channel (EnD = 1; right component inverse of envelope applied to left).

Figure 3. Envelope Waveforms

November 21, 1986

8-25

•

Signetics Linear Products

Product Specification

Stereo Sound Generator for
Sound Effects and Music Synthesis

Voo

.

CLOCK
GENERATOR

SAA1099

RREF

Rl

Rl
OUTPUT

OUTPUT

CLK (8 MHz)

I

6

5 DUTl

8

J

I

WR 1

LOS

\

[> r-

LEFT CHANNEL
OUTPUT

'---

5TACK

7
SAA1099

10-17

OUTPUT

00-07

~

r

CPU

ADDRESS
ADDRESS

DECODER

40UTR

2

cs

r-

J

I 1

Figure 4. Typical Application Circuit Diagram

November 21, 1966

~R

FILTERS
18

8-26

±I

[>
'----

RIGHT CHANNEL

t--- OUTPUT

Signetics

Section 9
Packaging Information

Linear Products

INDEX
Substrate Design Guidelines for Surface Mounted Devices................................
Test and Repair ......................................................................................
Fluxing and Cleaning................................................................................
Thermal Considerations for Surface-Mounted Devices ......................................
Package Outlines for Prefixes ADC, AM, CA, DAC, LF, LM, MC,

9-3
9-14
9-17
9-22

~~E_~~~

...................................................................

~

Package Outlines for Prefixes HEF, OM, MEA, PCD, PCF, PNA,
SM, SAB, SAF, TBA, TCA, TDA, TDD and TEA...........................................

9-52

Signetics

Substrate Design Guidelines for
Surface-Mounted Devices

Linear Products

INTRODUCTION
SMD technology embodies a totally new automated circuit assem~ly process using a
new generation of elebronic components:
surface-mounted devices (SMDs). Smaller
than conventional components, SMDs are
placed onto the surface of the substrate, not
through it like leaded components. And from
this, the fundamental difference between
SMD assembly and conventional throughhole component assembly arises; SMD component positioning is relative, not absolute.
When a through-hole (leaded) component is
inserted into a PCB, either the leads go
through the holes, or they don't. An SMD,
however, is placed onto the substrate surface, its position only relative to the solderlands, and placement accuracy is therefore
influenced by variations in the substrate track
pattern, component size, and placement machine accuracy.
Other factors influence the layout of SMD
substrates. For example, will the board be a
mixed-print (a combination of through-hole
components and SMDS) or an all-SMD design? Will SMDs be on one side of the
substrate or both? And there are process
considerations, such as: what type of machine will place the components and how will
they be soldered?
Using our expertise in the world of SMD
technology, this section draws upon applied
research in the area of substrate design and
manufacture, and presents the basic guidelines to assist the designer in making the
transition from conventional through-hole
PCB assembly to SMD substrate manufacture.

Designing With SMD
SMD technology is penetrating rapidly into all
areas of modern electronic equipment manufacture - in professional, industrial, and consumer applications. Boards are made with
conventional print-and-etch PCBs, multilayer
boards with thick film ceramic substrates, and
with a host of new materials specially developed for SMD assembly.
However, before substrate layout can be
attempted, footprints for all components must
be defined. Such a footprint will include the
combination of patterns for the copper solderlands, the solder resist, and, possibly, the
solder paste. So the deSign of a substrate
breaks down into two distinct areas: the SMD
footprint definition, and the layout and track
routing for SMDs on the substrate.
February 1987

Each of these areas is treated individually;
first, the general aspects of SMD technology,
including substrate configurations, placement
machines, and soldering techniques, are discussed.

Substrate Configurations
SMD substrate assembly configurations are
classified as:
Type I - Total surface mount (all-SMD);
substrates with no through-hole components
at all. SMDs of all types (SM integrated
circuits, discrete semiconductors, and passive devices) can be mounted either on one
side, or both sides, of the substrate. See
Figure 1a.
Type IIA - Double-sided mixed-print; substrates with both through-hole components
and SMDs of all types on the top, and smaller
SMDs (transistors and passives) on the bottom. See Figure 1b.
Type liB - Underside attachment mixedprint; the top of the substrate is dedicated
exclusively to through-hole components, with
smaller SMDs (transistor and passives) on
the bottom. See Figure 1c.
Although the all-SMD substrate will ultimately
be the cheapest and smallest variation as
there are no through-hole components, it's
the mixed-print substrate that many manufacturers will be looking to in the immediate
future, for this technique enjoys most of the
advantages of SMD assembly and overcomes the problem of non-availability of
some components in surface-mounted form.
The underside attachment variation of the
mixed-print (type liB - which can be thought
of as a conventional through-hole assembly
with SMDs on the solder side) has the added
advantages of only requiring a single-sided,
print-and-etch PCB and of using the established wave soldering technique. The all-SMD
and mixed-print assembly with SMDs on both
sides require reflow or combination wave!
reflow soldering, and, in most cases, a double-sided or multilayer substrate.
The relatively small size of most SMD assemblies compared with equivalent through-hole
designs means that circuits can often be
repeated several times on a single substrate.
This multiple-circuit substrate technique
(shown in Figure 2) further increases production efficiency.

9-3

a. Type I - Total Surface-Mount
(all-SMD) Substrates

l=~

Ij \l;;/!~~

b. Type IIA - Mixed-Print
(Double-Sided) Substrate

c. Type liB - Mixed-Print (Underside
Attachment) Substrate
Figure 1

•[r.=.Y.="ap.=.CU
0··0
··0
•• ~ II
~ .. ··0
~

[?-=~-=!:{?-=-~
0·-0
.. i .. ·-0
i .. ·-0
~

0::;=6=~=~.
OF07100s

Figure 2. Multiple-Circuit Substrate

Mixed Prints
The possibility of using a partitioned design
should be investigated when considering the
mixed-print substrate option. For this, part of
the circuit would be an all-SMD substrate, and
the remainder a conventional through-hole

II

Signetics Linear Products

Substrate Design Guidelines for Surface-Mounted Devices

PCB or mixed-print substrate. This allows the
circuit to be broken down into, for example,
high and low power sections, or high and low
frequency sections.

Automated SMD Placement
Machines
The selection of automated SMD placement
machines for manufacturing requirements is
an issue reaching far beyond the scope of
this section. However, as a guide, the four
main placement techniques are outlined.
They are:
In-Line Placement - a system with a series
of dedicated pick-and-place units, each placing a single SMD in a preset position on the
substrate. Generally used for small circuits
with few components. See Figure 3a.

a_ In-line Placement

b. Sequential Placement

Sequential Placement - a single pick-andplace unit sequentially places SMDs onto the
substrate. The substrate is positioned below
the pick-and-place unit using a computercontrolled X-Y moving table (a "software
programmable" machine). See Figure 3b.
Simultaneous Placement - places all
SMDs in a single operation. A placement
module (or station), with a number of pickand-place units, takes an array of SMDs from
the packaging medium and simultaneously
places them on the substrate. The pick and
place units are guided to their substrate
location by a program plate (a "hardware
programmable" machine), or by softwarecontrolled X-Y movement of substrate and/or
pick-and-place units. See Figure 3c.
Sequential/Simultaneous Placement - a
complete array of SM Ds is transferred in a
single operation, but the pick-and-place units
within each placement module can place all
devices simultaneously, or individually (sequentially). Positioning of the SMDs is software-controlled by moving the substrate on
an X-Y moving table, by X-Y movement of the
pick-and-place units, or by a combination of
both. See Figure 3d.
All four techniques, although differing in detail, use the same two basic steps: picking the
SMD from the packaging medium (tape, magazine, or hopper) and placing it on the substrate. In all cases, the exact location of each
SMD must be programmed into the automated placement machine.

Soldering Techniques
The SMD-populated substrate is soldered by
conventional wave soldering, reflow soldering, or a combination of both wave and reflow
soldering. These techniques are covered at
length in another publication entitled SMD
Soldering Techniques, but, briefly, they can
be described as follows:
Wave Soldering - the conventional method
of soldering through-hole component assemFebruary 1987

c. Simultaneous Placement

d. Sequential/Simultaneous Placement
Figure 3

blies where the substrate passes over a wave
(or more often, two waves) of molten solder.
This technique is favored for mixed-print assemblies with through-hole components on
the top of the substrate, and SMDs on the
bottom.
Reflow Soldering - a technique originally
developed for thick-film hybrid circuits using a
solder paste or cream (a suspension of fine
solder particles in a sticky resin-flux base)
applied to the substrate which, after component placement, is heated and causes the
solder to melt and coalesce. This method is
predominantly used for Type I (all-SMD) assemblies.
Combination Wave/Refiow Soldering - a
sequential process using both the foregoing
techniques to overcome the problems of
soldering a double-sided mixed-print substrate with SMDs and through-hole components on the top, and SMDs only on the
bottom. (Type liB).

Footprint Definition
An SMD footprint, as shown in Figure 4,
consists of:
• A pattern for the (copper) solderlands
• A pattern for the solder resist

9-4

• If applicable, a pattern for the solder
cream.
The design for the footprint can be represented as a set of nominal coordinates and
dimensions. In practice, the actual coordinates of each pattern will be distributed
around these nominal values due to positioning and processing tolerances. Therefore, the
coordinates are stochastic; the actual values
form a probability distribution, with a mean
value (the nominal value) and a standard
deviation.
The coordinates of the SMD are also stochastic. This is due to the tolerances of the
actual component dimensions and the positional errors of the automated placement
machine.
The relative positions of solderland, solder
resist pattern, and SMD, are not arbitrary. A
number of requirements may be formulated
concerning clearances and overlaps. These
include:
• Limiting factors in the production of the
patterns (for example, the spacing
between solderlands or tracks has a
minimum value)

Signetics Linear Products

Substrate Design Guidelines for Surface-Mounted Devices

• Maximizes the number of tracks
between adjacent solderlands.
The final SMD footprint design also depends
on the soldering process to be used. The
requirements for a wave-soldered substrate
differ from those for a reflow-soldered substrate, so each is discussed individually.

Footprints for Wave Soldering
To determine the footprint of an SMD for a
wave-soldered substrate, consider four main
interactive factors:
• The component dimensions plus
tolerances - determined by the
component manufacturer
• The substrate metallization - positional
tolerance of the solderland with respect
to a reference point on the substrate

Figure 4. Component Lead, Solder
Land, Solder Resist, and Solder
Cream "Footprint"
• Requirements concerning the soldering
process (for example, the solderlands
must be free of solder resist)
• Requirements concerning the quality of
the solder joint (for example, the
solderland must protrude from the SMD
metallization to allow an appropriate
solder meniscus)
Mathematical elaboration of these require·
ments and substitution of values for all toler·
ances and other parameters lead to a set of
inequalities that have to be solved simulta·
neously. To do this manually using worst·
case design is not considered realistic. A
better approach is to use a statistical analysis; although this requires a complex computer program, it can be done.
Such an approach may deliver more than one
solution, and, if this is so, then the optimal
solution must be determined. Optimization is
achieved by setting the following objective find the solution that:
• Minimizes the area occupied by the
footprint

c:=:::{>

• The solder resist - positional tolerance
of the solder resist pattern with respect
to the same reference point
• The placement tolerance - the ability of
an automated placement machine to
accurately pOSition the SMD on the
substrate.
The coordinates of patterns and SMDs have
to meet a number of requirements. Some of
these have a general validity (the minimum
overlap of SMD metallization and solderland)
and available space for solder meniscus.
Others are specifically required to allow successful wave soldering. One has to take into
account factors like the "shadow effect"
(missing of joints due to high component
bodies), the risk of solder bridging, and the
available space for a dot of adhesive.

The "Shadow Effect"
In wave soldering, the way in which the
substrate addresses the wave is important.
Unlike wave soldering of conventional printed
boards where there are no component bodies
to restrict the wave's freedom to traverse
across the whole surface, wave soldering of
SMD substrates is inhibited by the presence
of SMDs on the solder-side of the board. The
solder is forced around and over the SMDs as
shown in Figure Sa, and the surface tension
EXTENDED

of the molten solder prevents its reaching the
far end of the component, resulting in a dryjOint downstream of the solder flow. This is
known as the "shadow effect."
The shadow effect becomes critical with high
component bodies. However, wetting of the
solderlands during wave soldering can be
improved by enlarging each land as shown in
Figure 5b. The extended substrate metallization makes contact with the solder and allows
it to flow back and around the component
metallization to form the joint.
The use of the dual-wave soldering technique
also partially alleviates this problem because
the first, turbulent wave has sufficient upward
pressure to force solder onto the component
metallization, and the second, smooth wave
"washes" the substrate to form good fillets of
solder. Similarly, oil on the surface of the
solder wave lowers the surface tension,
(which lessens the shadow effect), but this
technique introduces problems of contaminants in the solder when the oil decomposes.

Footprint Orientation
The orientation of SO (small outline) and VSO
(very small outline) ICs is critical on wavesoldered substrates for the prevention of
solder bridge formation. Optimum solder penetration is achieved when the central axis of
the IC is parallel to the flow of solder as
shown in Figure 6a. The SO package may
also be transversely oriented, as shown in
Figure 6b, but this is totally unacceptable for
the VSO package.

Solder Thieves
Even with parallel mounted SO and VSO
packages, solder bridges have a tendency to
form on the leads downstream of the solder
flow. The use of solder thieves (small squares
of substrate metallization), shown in Figure 7
for a 40-pin VSO, further reduces the likelihood of solder-bridge formation.

....

~

~

a. Surface Tension Can Prevent the Molten Solder
From Reaching the Downstream End of the SMD,
Known as the "Shadow Effect"

DIRECT:

SOLDER FLOW

b. Extending the Solder Lands to Overcome the
Shadow Effect
Figure 5

February 1987

SUBSTRATE

~~w
7~~~

SUBSTRATE

9-5

II

Signetics Linear Products

Substrate Design Guidelines for Surface-Mounted Devices

~=F+=~=+~+=~=+~~;J

Iii;

For bonding small outline (SO) ICs to the
substrate, two dots of adhesive are sufficient
for SO·8, ·14, and ·16 packages, but the SOL·
20, ·24, ·28, and VSO·40 packages need
three dots. The through·tracks (or dummy
tracks) must be positioned beneath the IC
accordingly to support the adhesive dots.

c=>

FLOW
DIRECTION

DIRECTION
FLOW

C>A+B

a. Parallel Orientation for SO
and VSO Packages

b. Transverse Orientation for
SO Packages Only
Figure 6

g
{t _:

+

SUBSTRATE
DIRECTION

210

~ SOLD~~~ANDS
SOLDER THIEF

-1'1Figure 7. Example of Solder Thieves
for VSO-40 Footprints (Dims in mm)

sOle

Figure 8. Misaligned Placement of SO
Package Increases the Possibility of
Solder Bridging

Placement Inaccuracy
Another major cause of solder bridges on SO
ICs and plastic leaded chip carriers (PLCCs)
is a slight misalignment as shown in Figure 8.
The close spacing of the leads on these
devices means that any inaccuracy in place·
ment drastically reduces the space between

February 1987

adjacent pins and solderlands, thus increas·
ing the chance of solder bridges forming.

Dummy Tracks for Adhesive
Application
For wave soldering, an adhesive to affix
components to the substrate is required. This
is necessary to hold the SMDs in place
between the placement operation and the
soldering process (this technique is covered
at length in another publication entitled Adhe·
sive Application and Curing).
The amount of adhesive applied is critical for
two reasons: first, the adhesive dot must be
high enough to reach the SMD, and, second,
there mustn't be too much adhesive which
could foul the solderland and prevent the
formation of a solder joint. The three parame·
ters governing the height of the adhesive dot
are shown in Figure 9. Although this diagram
illustrates that the minimum requirement is
C > A + B, in practice, C > 2(A + B) is more
realistic for the formation of a good strong
bond.
Taking these parameters in turn, the sub·
strate metallization height (A) can range from
about 35"m for a normal print·and·etch PCB
to 135"m for a plated through·hole board.
And the component metallization height (B)
(on 1206·size passive devices, for example)
may differ by several tens of microns. There·
fore, A + B can vary considerably, but it is
desirable to keep the dot height (C) constant
for anyone substrate.
The solution to this apparent problem is to
route a track under the device as shown in
Figure 10. This will eliminate the substrate
metallization height (A) from the adhesive
dot-height criteria. Quite often, the high com·
ponent density of SMD substrates necessi·
tates the routing of tracks between solder·
lands, and, where it does not, a short dummy
track should be introduced.

9-6

SUBSTRATE

NOTES:
A "" Substrate metallization height
B "" SMD metallization height
C = Height of adhesive dot

Figure 9. Adhesive Dot Height Criteria

Footprints for Reflow Soldering
To determine the footprint of an SMD for a
reflow·soldered substrate. there are now five
interactive factors to consider: the four that
affect the wave solder footprints (although
the solder resist may be omitted), plus an
additional factor relating to the solder cream
application (the positional tolerance of the
screen·printed solder cream with respect to
the solderlands).

Solder Cream Application
In reflow soldering, the solder cream (or
paste) is applied by pressure syringe dispens·
ing or by screen printing. For industrial pur·
poses, screen printing is the favored tech·
nique because it is much faster than dispens·
ing.

Screen Printing
A stainless steel mesh coated with emulsion
(except for the solderland pattern where
cream is required) is placed over the sub·
strate. A squeegee passes across the screen
and forces solder cream through the uncoat·
ed areas of the mesh and onto the solderland. As a result, dots of solder cream of a
given height and density (in mg/mm2) are
produced.
There is an optimum amount of solder cream
for each joint. For example, the solder cream
requirements for the C1206 SM capacitor are
around 1.5mg per end; the SO IC requires
.
between 0.5 and 0.75mg per lead.
The solder cream density, combined with the
required amount of solder, makes a demand
upon the area of the solderland (in mm2). The
footprint dimensions for the solder cream
pattern are typically identical to those for the
solderlands.

Signetics Linear Products

Substrate Design Guidelines for Surface-Mounted Devices

DUMMY-TRACK [
OR
TROUGH-TRACK ~

1

t
r=:b I

]

1°r-

C

II

r==::---o
C>B

Figure 10. Through-Track or Dummy
Track to Modify Dot Height Criteria

Floating
One phenomenon sometimes observed on
reflow·soldered substrates is that known as
"floating" (or "swimming"). This occurs
when the solder paste reflows, and the force
exerted by the surface tension of the now
molten solder "pulls" the SMD to the center
of the solderland.
When the solder reflows at both ends simulta·
neously, the swimming phenomenon results
in the SMD self·centering on the footprint as
the forces of surface tension fight for equilibri·
urn. Although this effect can remove minor
positional errors, it's not a dependable fea·
ture and cannot be relied upon. Components
must always be positioned as accurately as
possible.

-

ooi/omm~ I
I I -+E-t.-

DF07220S

INCHES

INCHES
PACKAGE
OUTLINE

SO·8, 14, 16
SOL-1B, 20, 24, 28

I

B

A

I .155

.310

C

0

E

.275 .060 .024 .050
.450

.070

.024

.050

PACKAGE
OUTLINE
VSO-40
VSO-56

PACKAGE
OUTLINE
SO SMALL
so LARGE

I
I

A
4.0
7.8

B

C

0

E

7.0

1.5
1.8

.6
.6

1.27
1.27

11.4

A

B

C

o

.32

.536

.108

.02

,030

.46

.676

.108

.02

.030

METRIC (mm)

METRIC (mm)
PACKAGE
OUTLINE

VSO-40
VSO·56

A

B

C

0

8.0

13.4

11.5

16.9

2.7
2.7

.5
.5

.762
.75

Figure 12. Footprints for V50 ICs

METRIC (mm)
PACKAGE
OUTLINE

I

A

B

C

0

E

SOL·8

I

9.0

13.2

2.1

.6

1.27

PACKAGE
OUTLINE

I

A

B

C

0

E

.36

.528

.084

.024

.050

Footprint Dimensions
The following diagrams (Fig. 11 to 19) show
footprint dimensions for SO ICs, the VSO·40
package, PLCC packages, and the range of
surface· mounted transistors, diodes, resis·
tors, and capacitors. All dimensions given are
based on the criteria discussed in these
guidelines.

r

DOD~~Dl

INCHES

SOLoS

_!

Figure 11. Footprints for 50 ICs

Please note - these footprints are based on
our experience with both experimental and
actual production substrates and are repro·
duced for guidance only. Research is con·
stantly going on to cover all SMDs currently
available and those planned for in the future,
and data will be published when in it becomes
available.
PACKAGE
OUTLINE
PLCC·20
PLCC-2B
PLCC·44
PLCC·52

PLCC-68
PLCC·84
PLCC·32

A

B

C

INCHES
0
E

.260 .440.090 .024 .050
.360 .540.090
.560.740.090
.660 .840.090
.8601.040.090
1.0601.240.090
.360 .540.090

.024 .050
.024 .050
.024 .050
.024 .050

G

.260 .440
.360 .540
.560 .740
.660 .840
.860 1.040

.024

.050 1.060 1.240

.024

.050

.460

.640

Figure 13. Footprints for PLCCs

February 1987

9-7

Signetics Linear Products

Substrate Design Guidelines for Surface-Mounted Devices

~:~

r -1

r---ll

~c"I~-:-·I·c~

A

o+-$-0+1 0-+-01
TF

-to=ti

~B

DF07280S

~:~

~c~
DF07250S

B

A

INCHES

INCHES
0
C

F

SOT·23

I

Reflow
Wave

0.104 0.028 0.044 0.104
1 0 .048
0.032 0.136 0.052 0.052 0.048 0.152

SOT·23

I

R.flow
Wave

11.2
0.8

B

A

E

METRIC (mm)
C
0

2.6
3.4

0.7
1.3

1.1
1.3

E

F

2.6
1.2

3.8

-

Figure 14. Footprints for SOT-23
Transistors

0-011
B

INCHES
E
0

A

SOT·143

2.6

F

METRIC (mm)
C
0
E
F

0.7

1.2

0.9

1.1

G

H

G

0.9 2,0

H

I

0.096
0.10

0.208
0.2

0.056
0.05

0.056
0.08

I

A

METRIC (mm)
B
C

2.4
2.5

5.2
5.0

SOO~80

Reflow

Wave

I

0

1.4
1.25

1.4
2.0

C0805
R/C1206
C1210
C1808
C1812
C2220

SIZE

INCHES
A
B

C

0

0.08 X 0.05
0.128 x 0.064
0.128 X 0.1
0.18 X 0.08
0.18 x 0.128
0.228 X 0.2

0.032 0.136
0.072 0.184
0.072 0.184
0.112 0.248
0.112 0.248
0.16 0.296

0.052
0.056
0.056
0.068
0.068
0.068

0.056
0.068
0,104
0.084
0.132
0.204

SIZE

METRIC (mm)
A
B

C

0

1.3
1.4
1.4
1.7
1.7
1.7

1.4
1.7
2.6
2.1
3.3
5.1

2.0 X 1.25
3.2 X 1.6
3.2 x 2.5
4.5 X 2.0
4.5 x 3.2
5.7 x 5.0

0.8
1.8
1.8
2.8
2.8
4.0

3.4
4.6
4.6
6.2
8.2
7.4

Figure 18. Footprints for ReflowSoldered Surface-Mounted Resistors
and Ceramic Multilayer Capacitors

9-8

PACKAGE
OUTLINE 1 A
SOT·89

I

B

OF07260S

INCHES
C
D
E

F

G

0.08 0.1840.1040.0480.0320.0280.152

~~~~~~EI

A

B

SOT·89

2.0

4.6

I

METRIC (mm)
C
D
E
2.6

1.2

0.8

F

G

0.7

3.8

Figure 16. Footprints for ReflowSoldered SOT-89 Transistors

_IE I

1.1

Figure 17. Footprints for ReflowSoldered SOT-143 Transistors

February 1987

Reflow

COOE

0.104 0.0280.0480.0360.0440.0360.1160.044

~~~~~~EI

I

C

0

COOE

OF07290S

B

C

C0805
R/C1206
C1210
C1808
C1812
C2220

~H~
A

B

o-t- 01

lEG

I

A

~c -I- :-+-c~

D_,O+l
-II
SOT-143

I

Figure 15. Footprints for SOD-80
Diodes

~B+-:-+-B~

PACKAGE
OUTLINE I

SOD-8fl

Wave

o~ rnJ
01&
OJ
be -I·
:~_e-J

OFD73DOS

INCHES
SIZE
A
B
C
0
E
I
COB05
10.08 X 1.050.0480.1440.048 0.048 0.Q16
R/C1206 0.128 X .0640.08 0.1920.056 0.056 0.020

COOE
C0805
R/C1206

I
I

SIZE
2.0 X 1.25
3.2 X .6

METRIC (mm)
A
B
C
1.2
2.0

3.6
4,8

1.2
1.4

0

E

1.2
1.4

0.4
0.5

Figure 19. Footprints for WaveSoldered Surface-Mounted Resistors
and Ceramic Multilayer Capacitors

Signetics Linear Products

Substrate Design Guidelines for Surface-Mounted Devices

Layout Considerations
Component orientation plays an important
role in obtaining consistent solder-joint quality. The substrate layout shown in Figure 20
will result in significantly better solder joints
than a substrate with SMO resistors and
capacitors positioned parallel to the solder
flow.

bdbd bdbd

Component Pitch
The minimum component pitch is governed
by the maximum width of the component and
the minimum distance between adjacent
components. When defining the maximum
component width, the rotational accuracy of
the placement machine must also be considered. Figure 21 shows how the effective width
of the SMO is increased when the component
is rotated with respect to the footprint by
angle <1>0. (For clarity, the rotation is exaggerated in the illustration.)

SOLOER

FLOW

r::J bd

The minimum permissible distance between
adjacent SMOs is a figure based upon the
gap required to avoid solder-bridging during
the wave soldering process. Figure 22 shows
how this distance and the maximum component width are combined to derive the basic
expression for calculating the minimum pitch
(FMIN)'
As a guide, the recommended minimum
pitches for various combinations of two sizes
of SMOs, the R/C1206 and COB05 (R or C
designating resistor or capacitor respectively;
the number referring to the component size),
are given in Table 1. These figures are
statistically derived under certain assumed
boundary conditions as follows:
• POSitioning error (t.p)± 0.3mm; (± 0.012")
• Pattern accuracy (t.q)± 0.3mm;
(±0.012")

[d

SUBSTRATE

DIRECTION

~

L-----V

Figure 20. Recommended Component Orientation for Wave-Soldered Substrates

• Rotational accuracy (

••

tit

•

•
• ,

--

TYPICAL
10.0 mm

I
$l-

S

DF07400S

Figure 25. Substrate "Lanes"
From Use of a Simultaneous
Placement Machine
Placement of the 10 components in the lane
on the right of the substrate shown will
require a machine with 10 placement modules (or ten passes beneath a single placement module). an inefficient process considering that there are no more than three SMDs
in any other lane.

February 1987

Figure 26a shows the recommended approach for positioning test-paints in tracks
close to components. and Figure 26b shows
an acceptable (though not recommended)
alternative where the solderland is extended
to accommodate the test pin. This latter
method avoids sacrificing too much board
space. thus maintaining a high-density layout.
but can introduce the problem of components
moving ("floating") when reflow-soldered.
The approach shown in Figure 26c is totally
unacceptable since the pressure applied by
the test pin can make an open-circuit
soldered joint appear to be good. and. more
importantly. the test pin can damage the
metallization on the component. particularly
with small SMDs.

a. RECOMMENDED Test Point
Location Close to an SMD

b. Acceptable Test Point Location

CAD Systems for SMD
Substrate Layout
At present. about half of all PCBs are laid out
using computer-aided design (CAD) techniques. and this proportion is expected to rise
to over 90% by 1988. Of the many current
CAD systems available for designing PCB
layouts for conventional through-hole components and ICs in DIL packages. few are SMDcompatible. and systems dedicated exclusively to SMD substrate layout are still comparatively rare. There are two main reasons
for this: some CAD suppliers are waiting for
SMD technology to fully mature before updating their systems to cater to SMD-Ioaded
substrates. and others are holding back until
standard package outlines are fully defined.
However. updating CAD systems used for
through-hole printed boards is not simply a
case of substituting SMD footprints for conventional component footprints. since SMDpopulated substrates impose far tougher restraints on PCB layout and require a total
rethink of the layout programs. For example.
systems must deal with higher component
densities. finer track widths. devices on both
sides of the substrate (possibly occupying
corresponding positions on opposite sides).
and even SMDs under conventional DILs on
the same side of the substrate.
The amount of reworking that a program
requires depends on whether it's an interactive (manual) system. or one with fully automatic routing and placement capabilities. For

9-11

c. UNACCEPTABLE Test Point
Location
Figure 26
interactive systems. where the user positions
the components and routes the tracks manually on-screen. program modifications will be
minimal. Automatic systems. however. must
contend with the stricter design rules for SMD
substrate layout. For example. many autorouting programs assume that every solderland is a plated through-hole and. therefore.
can be used as a via hole. This is not
applicable for SMD-populated substrates.
CAD programs base the substrate layout on a
regular grid. This method. analogous to drawing the layout on graph paper. must have the
grid lines on a pitch that is no larger than the
smallest component or feature (track width.
pitch. and so on). For conventional DIL
boards. this is typically 0.635mm (0.025"). but
with the much smaller SMDs. a grid spacing
of 0.0254mm (0.001") is required. Consequently. for the same area of substrate. a
CAD system based on this finer grid requires

I

Signetics Linear Products

Substrate Design Guidelines for Surface-Mounted Devices

a resolution more than 600 times greater than
that required for conventional-layout CAD
systems.
To handle this, extra memory capacity can be
added, or the allowable substrate area can be
limited. In fact, the small size of SMDs, and
the high-density layouts possible, generally
result in a smaller substrate. However, highdensity layout gives rise to additional complications not directly related to the SMD substrate design guidelines. Most CAD systems,
for instance, cannot always completely route
all interconnects, and some traces have to be
routed manually. This can be particularly
difficult with the fewer via holes and smaller
component spacing of SMD boards.
Ideally, the CAD program should have a
"tear-up and start again" algorithm that allows it to restart autorouting if a previous

February 1987

attempt reaches a position where no further
traces can be routed before an acceptable
percentage of interconnects (and this percentage must first be determined) have been
made. This minimizes the manual reworking
required.

CAE/CAD/CAM Interaction
Computer-aided production of printed boards
has evolved from what was initially only a
computer-aided manufacturing process
(CAM - digitizing a manually-generated layout and using a photoplotter to produce the
artwork) to fully-interactive computer-aided
engineering, design, and manufacture using a
common database. Figure 27 illustrates how
this multi-dimensional interaction is particularly well-suited to SMD-populated substrate
manufacture in its highly-automated environment of pick-and-place assembly machines
and test equipment.

9-12

Using a fully-integrated system, linked by
local area network to a central database, will
make it possible to use the initial computeraided engineering (CAE - schematic design,
logic verification, and fault simulation) in the
generation of the final test patterns at the end
of the development process. These test patterns can then be used with the automatic
test equiprnent (ATE) for functional testing of
the finished substrates.
Such a system is particularly useful for testing
SMD-populated substrates, as their high component density and fewer via-holes make incircuit testing (" bed of nails" approach) difficult. Consequently, manufacturers are turning
to functional testing as an alternative. These
aspects are covered in another publication
entitled Functional Testing and Repair.

Signetics Linear Products

Substrate Design Guidelines for Surface-Mounted Devices

CAD
SOFTWARE

CAM

MANUFACTURE

CAE

SOFTWARE~~'f--I~==~1r~P===~~lr~==~L-~__r-~r====~L-~\~====~~~==~~~~~~

LOCAL AREA NETWORK

HARDWARE

Figure 27. The Software-Hardware Interaction for the Computer-Aided Engineering, Design,
and Manufacture of SMD Substrates

I
February 1987

9-13

I

Signetics

Test and Repair

Linear Products

AN INTRODUCTION
The key questions that must be asked of any
electronic circuit are" does it work, and will it
continue to do so over a specified period of
time?" Until zero-defect soldering is
achieved, and all components are guaranteed
serviceable by the vendors, manufacturers
can only answer these questions by carrying
out some form of test on the finished product.
The types of tests, and the depth to which
they are carried out, are determined by the
complexity of the circuit and the customer's
requirements. The amount of rework to be
performed on the circuit will depend on the
results of these tests and the degree of
reliability demanded. The criteria are true of
all electronic assemblies, and the test engineer must formulate test schedules accordingly.
Substrates loaded with surface mounted devices (SMDs), however, pose additional problems to the test engineer. The devices are
much smaller, and substrate population density is greater, leading to difficulty in accessing all circuit nodes and test points. Also SMD
substrate layout deSigns often have fewer via
and component lead holes, so test points
may not all be on one side of the substrate
and double-sided test fixtures become necessary.
To achieve the high throughput rates made
possible by using highly automated SMD
placement machines and volume soldering
techniques, automatic testing becomes a necessity. Visual inspection of the finished substrate by trained inspectors can normally
detect about 90 % of defects. With the correct
combination of automatic test equipment, the
remainder can be eliminated. In this publication, we hope to provide the manufacturer
with information to enable him to evaluate
and select the best combination of test equipment and the most effective test methods for
his product.

BARE-BOARD TESTING
Although SMD substrates will undoubtedly be
smaller than conventional through-hole substrates and have less space between conductors, the principles of bare-board testing
remain the same. Many of the testers already
in use can, with little or no modification, be
used for SMD substrates. As this is already a
well-established and well-documented practice, it will not be discussed further in this
publication, but it is recommended that bareFebruary 1987

board testing always be used as the first step
in assuring board integrity.

POST-ASSEMBLY TESTING
Testing densely populated substrates is no
easy task, as the components may occupy
both sides of the board and cover many of
the circuit nodes (see Figure 1 for the three
main types of SMD-populated substrates).
Unlike conventional substrates, on which all
test points are usually accessible from the
bottom, SMD assemblies must be designed
from the start with the siting of test points in
mind. Probing SMD substrates is particularly
difficult owing to the very close spacing of
components and conductors.
Mixed print or all-SMD assemblies with components on both sides further aggravate the
testing problems, as not all test pOints are
present on the same side of the board.
Although two-sided test fixtures are feasible,
they are expensive and require considerable
time to build.
The application of a test probe to the top of
an SMD termination could damage it, and
probe pressure on a poor or open solder jOint
can force contact and thus allow a defective
joint to be assessed as good. Figure 2a
illustrates the recommended siting of test
points close to SMD terminations, and Figure
2b shows an alternative, though not recommended, option. Here, problems could arise
from reflow soldering (solder migrating from
the jOint) unless the test pOint area is separated from the solder land area with a stripe of
solder resist. Excessive mechanical pressure
caused by too many probes concentrated in a
small area may also result in substrate damage.
It is good practice for substrates to have test
points on a regular grid so that conventional,
rather than custom, testers may be used. If
the substrate has tall components or heatsinks, the test points must be located far
enough away to allow the probes to make
good contact. All test points should be solder
coated to provide good electrical contact. Via
holes may also be used as test points, but the
holes must be filled with solder to prevent the
probe from sticking.

AUTOMATIC TEST EQUIPMENT
(ATE)
As manufacturers strive to increase production, the question becomes not whether to

9-14

I

a. Type I - Total Surface Mount
(AII-SMD) Substrates

b. Type IIA - Mixed Print
(Double-Sided) Substrate

c. Type liB - Mixed Print
(Underside Attachment) Substrate
Figure 1
use automatic test engineering (ATE), but
which ATE system to use and how much to
spend on it. Because of the rapid fall in price
of computers, memories, and peripherals,
today's low-cost ATE equals the performance
of the high·cost equipment of just two or
three years ago. For factory automation, manufacturers must consider many factors, such
as production volume, product complexity,
and availability of skilled personnel.
One question is whether the ATE system can
be used not only for production testing but
also for service and repair to reduce the high
cost of keeping a substrate inventory in the
field. Another is whether assembly and process-induced faults represent a significant
percentage of production defects, rather than
out-of-tolerance components. These questions need to be answered before deciding on
the type of ATE system required.

Signetics Linear Products

Test and Repair

of an in-circuit tester alone, improves the
throughput rate.

'(:1

FAUL"';..~

DETECTION
100

:

IN·CIRCUIT

~

CIRCurT
TESTER

:: J '

i
I

a. Recommended Location
of Test Points Close to SMDs

30

.

WEEKS

~ 65%

I

40

TESTER

TESTER

ANA~LYZ~~;RO~I~~~~G PROBO'~

SHORT.

70

0'"

FUNCTIONAL

IN-CIRCUIT

~

PROGRA'!"~~G

GRAMMING
TIME
9 MONTHS

If manufacturing faults and analog compo-

TIME 4 DAYS

35%
PROGRAMMING
TIME 6 HOURS

20

10jo

k -________________________

~

Figure 3. Bar Chart Showing a
Comparison of Percent Fault Detection
and Programming Time for
Various ATE Systems
design can, however, often eliminate the

need for double·sided test probe fixtures.

b. Acceptable, Though
Not Recommended, Location of
Test Points Close to SMDs

In-circuit testers power the assembly and
check for open or short-circuits, circuit pa·
rameters, and can pinpoint defective components. They can provide around 90% fault
coverage, but are more expensive than shortcircuit testers and programming can take
more than six weeks.
In-circuit analyzers are relatively simple to
program and can detect manufacturing-in·
duced faults in one third of the time required
by an in-circuit tester. Fault coverage is
between 50 % and 90 %. Because they do not
power the assembly, they cannot detect digital logic faults, unlike an in-circuit tester or
functional tester.

c. Unacceptable Location
of Test Points Close to SMDs
Figure 2
Several systems are currently available to the
manufacturer, including short·circuit testers,
in-circuit testers, in-circuit analyzers, and
functional testers. Figure 3 shows a bar·chart
giving a comparison of percent fault detection
and programming time for various ATE systems.
A loaded-board, short·circuit tester takes
from two to six hours to program and its
effective fault coverage is between 35% and
65%. It has the advantage of being operationally fast and comparatively inexpensive. On
the negative side, however, it is limited to the
detection of short-circuits and may require a
double-sided, bed-of-nails test fixture (see
Figure 4), which for SMD substrates may be
expensive and take time to produce. Careful

February 1987

Combining a short-circuit tester with a functional tester produces even more dramatic
results. If most defects are manufacturingproduced shorts, the use of a short-circuit
tester to relieve the functional tester of this
task can increase throughput five-fold while
maintaining a fault coverage of up to 98%.

Functional testers, on the other hand, check
the assembly's performance and simply
make a go or no-go decision. Either the
assembly performs its required function or it
does not. They are much more expensive, but
their fault coverage is between 80% and
98%. Their major disadvantages, apart from
cost, are that they cannot locate defective
components, and programming for a highcapacity system can take as long as nine
months.

nent defects are responsible for the majority
of failures, a relatively low·cost, in-circuit
analyzer can be used in tandem with an incircuit tester or functional tester to reduce
testing costs and improve throughput. The incircuit analyzer is three times faster than an
in-circuit tester in detecting manufacturinginduced faults, offers test and diagnostics
usually within 10 seconds each, and is relatively simple to program. But because it is
unpowered, an in-circuit analyzer cannot test
digital logic faults; either an in-circuit tester or
functional tester following the in-circuit analyzer must be used to locate this type of
defect.

POLLUTED POWER SUPPLIES
Today's electronic components and the
equipment used to test them are susceptible
to electrical noise. Erroneous measurements
on pass-or-fail tests could lower test throughput or, even more seriously, allow defective
products to pass inspection. Semiconductor
chips under test can also be damaged or
destroyed as high-energy pulses or line-voltage surges stress the fine-line geometrics
separating individual cells.
Noise pulses can be either in the normal (lineto-line) mode or common (Iine-to-ground)
mode. Common-mode electrical noise poses
a special threat to modern electronic circuitry
since the safety ground line to which common-mode noise is referenced is often used
as the system's logic reference point. Since
parasitic capacitance exists between safety
ground and the reference point, at high frequencies these paints are essentially tied
together, allowing noise to directly enter the
system's logic.

ATE Systems
An analysis of defects on a finished substrate
will determine which combination of ATE will
best meet the test requirements with regard
to fault coverage and throughput rate.
If most defects are short-circuits, a loaded-

board short-circuit tester, in tandem with an
in-circuit tester, will pre-screen the substrate
for short-circuits twice as fast as the in-circuit
tester. This allows more time for the in-circuit
tester to handle the more complex test requirements. This combination of ATE, instead

9-15

MANUAL REPAIR
The repair of SMD-populated substrates will
entail either the resoldering of individual joints
and the removal of shorts or the replacement
of defective components.
The reworking of defective joints will invariably involve the use of a manual soldering
iron. Bits are commercially available in a
variety of shapes, including speCial hollow
bits used for desoldering and for the removal
of solder bridges. The criteria for the inspec-

II

Signetics Linear Products

Test and Repair

SPRING· LOADED
TEST PRODS

Figure 4. Double-Sided, Bed-ol-Nails Test Fixture
Using air pressure, the center pin of the collet
then pushes the PLCC into contact with the
substrate where it is maintained with the
correct amount of force. Heat is then applied
through the walls of the collet to reflow the
solder paste. The center pin maintains pressure on the PLCC until the solder has solidified, then the center pin is raised and the
replacement is complete.

VACUUM
PIPETTE

r

HEAO

MOr

SUBSTRATE

Figure 5. Heated Collet lor the Removal and Replacement of Multi-Leaded SMDs
(a PLCC Is Shown Here)
tion of reworked soldered joints are the same
as those for machine soldering.
Special care must be taken when reworking
or replacing electrostatic sensitive devices.
Soldering irons should be well grounded via a
safety resistor of minimum 100kst. The
ground connection to the soldering iron
should be welded rather than clamped. This
is because oxidation occurs beneath the
clamp, thus isolating the ground connection.
Voltage spikes caused by the switching of the
iron can be avoided by using either continuously-powered irons, or irons that switch only
at zero voltage on the AC sine curve.
To remove defective leadless SMDs, a variety
of soldering iron bits are available that will
apply the correct amount of heat to both ends
of the component simultaneously and allow it
to be removed from the substrate. If the
substrate has been wave soldered, an adhesive will have been used, and the bond can

February 1987

be broken by twisting the bit. Any adhesive
residue must then be removed. The same
tool is then used to place and solder the new
component, using either solder cream or
resin-cored solder.
When a multi-leaded component, such as a
plastic leaded chip carrier (PLCC), has to be
removed, a heated collet can be used (see
Figure 5). The collet is positioned over the
PLCC, heat is applied to the leads and solder
lands automatically until the solder reflows.
The collet, complete with the PLCC, is then
raised by vacuum. Solder cream is then reapplied to the solder lands by hand. No
adhesive is required in this operation.
The collet is positioned over the replacement
PLCC, which is held in place by the slight
spring pressure of the PLCC leads against the
walls of the collet. The collet, complete with
PLCC, is then raised pneumatically and positioned over the solder lands.

9-16

Another method, well-suited to densely populated 5MD substrates, uses a stream of
heated air, directed onto the SMD terminations. Once the solder has been reflowed, the
component can be removed with the aid of
tweezers. While the hot air is being directed
onto the component, cooler air is played onto
the bottom of the substrate to protect it from
heat damage. During removal, the component should be twisted sideways slightly in
order to break the surface tension of the
solder and any adhesive bond between the
component and the substrate. This prevents
damage to the substrate when the component is lifted.
To fit a new component, the solder lands are
first retinned and fluxed, the new component
accurately placed, and the solder rellowed
with hot air. Substituting superheated argon,
nitrogen, or a mixture of nitrogen and hydrogen for the hot air stream removes any risk of
contaminating or oxidizing the solder.
Focused infrared light has also been used
successfully to rellow the solder on densely
populated substrates.
In general, the equipment and procedures
used for the replacement of PLCCs can be
used for lead less ceramic chip carriers
(LCCCs) and small·outline packages (SO
ICs). SO ICs are somewhat easier to replace,
as the leads are more accessible and only on
two sides of the component.

Signetics

Fluxing and Cleaning

Linear Products

INTRODUCTION
The adoption of mass soldering techniques
by the electronics industry was prompted not
only by economics, and a requirement for
high throughput levels, but also by the need
for a consistent standard of quality and reliability in the finished product unattainable by
using manual methods. With surface-mounted device (SMD) assembly, this need is even
greater.
The quality of the end-product depends on
the measures taken during the design and
manufacturing stages. The foundations of a
high-quality electronic circuit are laid with
good design, and with correct choice of
components and substrate configuration. It is,
however, at the manufacturing stage where
the greatest number of variables, both with
respect to materials and techniques, have to
be optimized to produce high-quality soldering, a prerequisite for reliability.
Of the two most commonly-used soldering
techniques, wave and reflow, wave soldering
is by far the most widely used and understood. Many factors influence the outcome of
the soldering operation, some relating to the
soldering process itself, and others to the
condition of components and substrate to
which they are to be attached. These must be
collectively assessed to ensure high-quality
soldering.
One of the most important, most neglected,
and least understood of these processes is
the choice and application of flux. This section outlines the fluxing options available, and
discusses the various cleaning techniques
that may be required, for SMD substrate
assembly.

FLUXES
Populating a substrate involves the soldering
of a variety of terminations simultaneously. In
one operation, a mixture of tinned copper,
tin/lead-or gold-plated nickel-iron, palladiumsilver, tin/lead-plated nickel-barrier, and even
materials like Kovar, each possessing varying
degrees of solderability, must be attached to
a common substrate using a single solder
alloy.
It is for this reason that the choice of the flux
is so important. The correct flux will remove
surface oxides, prevent reoxidization, help to
transfer heat from source to jOint area, and
leave non-corrosive, or easily removable corrosive residues on the substrate. It will also
February 1987

improve wettability of the solder joint surfaces.
The wettability of a metal surface is its ability
to promote the formation of an alloy at its
interface with the solder to ensure a strong,
low-resistance joint.
However, the use of flux does not eliminate
the need for adequate surface preparation.
This is very important in the soldering of SMD
substrates, where any temptation to use a
highly-active flux in order to promote rapid
wetting of ill-prepared surfaces should be
avoided because it can cause serious problems later when the corrosive flux residues
have to be removed. Consequently, optimum
solderability is an essential factor for SMD
substrate assembly.
Flux is applied before the wave soldering
process, and during the reflow soldering process (where flux and solder are combined in a
solder cream). By coating both bare metal
and solder, flux retards atmospheric oxidization which would otherwise be intensified at
soldering temperature. In the areas where the
oxide film has been removed, a direct metalto-metal contact is established with one lowenergy interface. It is from this point of
contact that the solder will flow.

Types of Flux
There are two main characteristics of flux.
The first is efficacy-its ability to promote
wetting of surfaces by solder within a specified time. Closely related to this is the activity
of the flux, that is, its ability to chemically
clean the surfaces.

ed in varying quantities to increase it. These
take the form of either organic acids, or
organic salts that are chemically active at
soldering temperatures. It is therefore convenient to classify the colophony-based fluxes
by their activator content.

Non-Activated Rosin (R) Flux
These fluxes are formed from pure colophony
in a suitable solvent, usually isopropanol or
ethyl alcohol. Efficacy is low and cleaning
action is weak. Their uses in electronic soldering are limited to easily-wettable materials
with a high level of solderability. They are
used mainly on circuits where no risk of
corrosion can be tolerated, even after prolonged use (implanted cardiac pacemakers,
for example). Their flux residues are noncorrosive and can remain on the substrate,
where they will provide good insulation.

Rosin, Mildly-Activated (RMA)
Flux
These fluxes are also composed of colophony in a solvent, but with the addition of
activators, either in the form of di-basic organic acids (such as succinc acid), or organic
salts (such as dimethylammonium chloride or
diethylammonium chloride). It is customary to
express
the amount of added activator as mass percent of the chlorine ion on the colophony
content, as the activator-to-colophony ratio
determines the activity, and, hence, the corrosivity. In the case of RMA activated with
organic salts, this is only some tenths of one
percent.

Organic Soluble Fluxes

When organic acids are used, a higher percentage of activator must be added to produce the same efficacy as organic salts, so
frequently both salts and acids are added.
The cleaning action of RMA fluxes is stronger
than that of the R type, although the corrosivity of the residues is usually acceptable.
These residues may be left on the substrate
as they form a useful insulating layer on the
metal surfaces. This layer can, however,
impede the penetration of test probes at a
later stage.

Most of the fluxes soluble in organic liquids
are based on colophony or rosin (a natural
product obtained from pine sap that has been
distilled to remove the turpentine content).
Solid colophony is difficult to apply to a
substrate during machine soldering, so it is
dissolved in a thinning agent, usually an
alcohol. It has a very low efficacy, and hence
limited cleaning power, so activators are add-

The RA fluxes are similar to the RMA fluxes,
but contain a higher proportion of activators.
They are used mainly when component or
substrate solderability is poor and corrosionrisk requirements are less stringent. However,
as good solderability is considered essential
for SMD assembly, highly-activated rosin fluxes should not be necessary. The removal of

The second is the corrosivity of the flux, or
rather the corrosivity of its residues remaining
on the substrate after soldering. This is again
linked to the activity; the more active the flux,
the more corrosive are its residues.
Although there are many different fluxes
available, and many more being developed,
they fall into two basic categories; those with
residues soluble in organic liquids, and those
with residues soluble in water.

9-17

Rosin, Activated (RA) Flux

I

Signetlcs Linear Products

Fluxing and Cleaning

flux residues is optional and usually dependent upon the working environment of the
finished product and the customer's requirements.

Water-Soluble Fluxes
The water-soluble fluxes are generally used
to provide high fluxing activity. Their residues
are more corrosive and more conductive than
the rosin-based fluxes, and, consequently,
must always be removed from the finished
substrate. Although termed water soluble, this
does not necessarily imply that they contain
water; they may also contain alcohols or
glycols. It is the flux residues that are water
soluble. The usual composition of a watersoluble flux is shown below.
1. A chemically-active component for cleaning the surfaces.
2. A wetting agent to promote the spreading
of flux constituents.
3. A solvent to provide even distribution.
4. Substances such as glycols or watersoluble polymers to keep the activator in
close contact with the metal surfaces.
Although these substances can be dissolved
in water, other solvents are generally used, as
water has a tendency to spatter during soldering. Solvents with higher boiling points,
such as ethylene glycol or polyethylene glycol
are preferred.

Water-Soluble Fluxes With
Inorganic Salts
These are based on inorganic salts such as
zinc chloride, or ammonium chloride, or inorganic acids such as hydrochloric. Those with
zinc or ammonium chloride must be followed
by very stringent cleaning procedures as any
halide salts remaining on the substrate will
cause severe corrosion. These fluxes are
generally used for non-electrical soldering.
Although the hydrazine halides are among
the best active fluxing agents known, they are
highly suspect from a health point of view and
are therefore no longer used by flux manufacturers.

Water-Soluble Fluxes With
Organic Salts
These fluxes are based on organic hydrohalides such as dimethylammonium chloride,
cyclo hexalamine hydrochloride, and aniline
hydrochloride, and also on the hydrohalides
of organic acids. Fluxes with organic halides
usually contain vehicles such as glycerol or
polyethylene glycol, and non-ionic surfaceactive agents such as nonylphenol polyoxyethylene. Some of the vehicles, such as the
polyethylene glycols, can degrade the insulation resistance of epoxy substrate material
and, by rendering the substrate hydrophilic,
make it susceptible to electrical leakage in
high-humidity environments.
February 1987

Water-Soluble Fluxes With
Organic Acids
Based on acids such as lactic, melonic, or
citric, these fluxes are used when the presence of any halide is prohibited. However,
their fluxing action is weak, and high acid
concentrations have to be used. On the other
hand, they have the advantage that the flux
residues can be left on the substrate for some
time before washing without the risk of severe
corrosion.

Solder Creams
For reflow soldering, both the solder and the
flux are applied to the substrate before soldering and can be in the form of solder
creams (or pastes), preforms, electro-deposit,
or a layer of solder applied to the conductors
by dipping. For SMD reflow soldering, solder
cream is generally used.
Solder cream is a suspension of solder particles in flux to which special compounds have
been added to improve the rheological properties. The shape of the particles is important
and normally spherical particles are used,
although non-spherical particles are now being added, particularly in very fine-line soldering.
In principle, the same fluxes are used in
solder creams as for wave soldering. However, due to the relatively large surface area of
the solder particles (which can oxidize), more
effective fluxing is required and, in general,
solder creams contain a higher percentage of
activators than the liquid fluxes. The drying of
the solder paste during preheating (after component placement) is an important stage as it
reduces any tendency for components to
become displaced during soldering.

Flux Selection
Choosing an appropriate flux is of prime
importance to the soldering system for the
production of high-quality, reliable joints.
When solderability is good, a mildly-activated
flux will be adequate, but when solderability is
poorer, a more effective, more active flux will
be required. The choice of flux, moreover, will
be influenced by the cleaning facilities available, and if, in fact, cleaning is even feasible.

choice will be between an RA or an RMA
rosin-based flux.

Application of Flux
Three basic factors determine the method of
applying flux; the soldering process (wave or
reflow), the type of substrate being processed
(all-SMD or mixed print), and the type of flux.
For wave soldering, the flux must be applied
in liquid form before soldering. While it is
possible to apply the flux at a separate fluxing
station, with the high throughput rates demanded to maximize the benefits of SMD
technology, today's wave-soldering machines
incorporate an integral fluxing station prior to
the preheat stage. This enables the preheat
stage to be used to dry the flux as well as
preheat the substrate to minimize thermal
shock.
The most commonly-used methods of applying flux for wave soldering are by foam, wave,
or spray.

Foam Fluxing
Foam flux is generated by forcing low-pressure clean air through an aerator immersed in
liquid flux (see Figure 1). The fine bubbles
produced by the aerator are guided to the
surface by a chimney-shaped nozzle. The
substrates are passed across the top of the
nozzle so that the solder side comes in
contact with the foam and an even layer of
flux is applied. As the bubbles burst, flux
penetrates any plated-through holes in the
substrate.

Wave Fluxing
A double-sided wave can also be used to
apply flux, where the washing action of the
wave deposits a layer of flux on the solder
side of the substrate (see Figure 2). Waveheight control is essential and a soft, wipe-off
brush should be incorporated on the exit side
of the fluxing station to remove excess flux
from the substrate.

With water-soluble fluxes, aqueous cleaning
of the substrate after soldering is mandatory.
If thorough cleaning is not carried out, severe
problems may arise in the field, due to corrosion or short circuits caused by too low a
surface resistance of the conductive residues.
For rosin-based fluxes, the need for cleaning
will depend on the activity of the flux. Mildlyactivated rosin residues can, in most cases,
remain on the substrate where they will afford
protection and insulation. In practice, for the
great majority of electronic circuits, the

9-18

AERATOR

COMPRESSED AIR

Figure 1. Schematic Diagram
of Foam Fluxer

Signetics Linear Products

Fluxing and Cleaning

PREHEATING
Preheating the substrate before soldering
serves several purposes. It dries the flux to
evaporate most of the solvent, thus increasing the viscosity. "the viscosity is too low, the
flux may be prematurely expelled from the
substrate by the molten solder. This can
result in poor wetting of the surfaces, and
solder spatter.

IMPELLER

Figure 2. Schematic Diagram
of Wave Fluxer

Spray Fluxing
Several methods of spray fluxing exist; the
most common involves a mesh drum rotating
in liquid flux. Air is blown into the drum which,
when passing through the fine mesh, directs
a spray of flux onto the underside of the
substrate (see Figure 3). Four parameters
affect the amount of flux deposited: conveyor
speed, drum rotation, air pressure, and flux
density. The thickness of the flux layer can be
controlled using these parameters, and can
vary between 1 and 101'm.
The advantages and disadvantages of these
three flux application techniques are outlined
in Table 1.

Flux Density
One of the main control factors for fluxes
used in machine soldering is the flux density.
This provides an indication of the solids
content of the flux, and is dependent on the
nature of the solvents used. Automatic con·
trol systems, which monitor flux density and
inject more solvent as required, are commer·
cially available, and it is relatively simple to
incorporate them into the fluxing system.

Drying the flux also accelerates the chemical
action of the flux on the surfaces, and so
speeds up the soldering process. During the
preheating stage, substrate and components
are heated to between 80·C and 90·C (solvent-based fluxes) or to between 100·C and
110·C (water-based systems). This reduces
the thermal shock when the substrate makes
contact with the molten solder, and minimizes
any likelihood of the substrate warping.
The most common methods of preheating
are: convection heating with forced air, radiation heating using coils, infrared quartz lamps
or heated panels, or a combination of both
convection and radiation. The use of forced
air has the added advantage of being more
effective for the removal of evaporated solvent. Optimum preheat temperature and duration will depend on the nature and design of
the substrate and the composition of the flux.
Figure 4 shows a typical method of preheat
temperature control. The desired temperature
is set on the control panel, and the microprocessor regulates preheater No. 1 to provide
approximately 60% of the required heat. The
IR detector scans the substrate immediately
following No. 1 heater and reads the surface
temperature. By taking into account the surface temperature, conveyor speed, and the
thermal characteristics of the substrate, the
microprocessor then calculates the amount
of additional heat required to be provided by
heater No. 2 in order to attain the preset
temperature. In this way, each substrate will
have the same surface temperature on reaching the solder bath.

POSTSOLDERING CLEANING

ROTATING DRUM

Figure 3. Schematic Diagram
of Spray Fluxer

February 1987

Now that worldwide efforts in both commercial and industrial electronics are converting
old designs from conventional assembly to
surface mounting, or a combination of both, it
can also be expected that high-volume cleaning systems will convert from in-line aqueous
cleaners to in-line solvent cleaners or in-line
saponification systems (a technique that uses
an alkaline material in water to react with the
rosin so that it becomes water soluble).
These systems may, however, become subject to environmental objections, and new
governmental restrictions on the use of halogenated hydrocarbons.

9-19

The major reason for this is that the watersoluble flux residues, containing a higher
concentration of activators, or showing hygroscopic behavior, are much more difficult to
remove from SMD-populated substrates than
rosin-based flux residues. This is primarily
because the higher surface tension of water,
compared to solvents, makes it difficult for
the cleaning agents to penetrate beneath
SMDs, especially the larger ones, with their
greatly reduced off-contact distance (the distance between component and substrate).
Postsoldering cleaning removes any contamination, such as surface deposits, inclusions,
occlusions, or absorbed matter which may
degrade to an unacceptable level the chemical, physical, or electrical properties of the
assembly. The types of contaminant on substrates that can produce either electrical or
mechanical failure over short or prolonged
periods are shown in Table 2.
All these contaminants, regardless of their
origin, fall into one of two groups: polar and
non-polar.

Polar Contaminants
Polar contaminants are compounds that dissociate into free ions which are very good
conductors in water, quite capable of causing
circuit failures. They are also very reactive
with metals and produce corrosive reactions.
It is essential that polar contaminants be
removed from the substrates.

Non-Polar Contaminants
Non-polar contaminants are compounds that
do not dissociate into free ions or carry an
electrical current and are generally good
insulators. Rosin is a typical example of a
non-polar contaminant. In most cases, nonpolar contamination does not contribute to
corrosion or electrical failure and may be left
on the substrate. It may, however, impede
functional testing by probes and prevent good
conformal coat adhesion.

Solvents
The solvents currently used for the postsoldering cleaning of substrates are normally
organic based and are covered by three
classifications: hydrophobic, hydrophillic, and
azeotropes of hydrophobic/hydrophillic
blends.
Azeotropic solvents are mixtures of two or
more different solvents which behave like a
single liquid insomuch that the vapor produced by evaporation has the same composition as the liquid, which has a constant boiling
point between the boiling pOints of the two
solvents that form the azeotrope. The basic
ingredients of the azeotropic solvents are
combined with alcohols and stabilizers.
These stabilizers, such as nitromethane, are
included to prevent corrosive reaction be-

Signetics Linear Products

Fluxing and Cleaning

Table 1. Advantages and Disadvantages of Flux Application Methods
Method

Advantages

Disadvantages

Foam
Fluxing

• Compatible with continuous
soldering process
• Foam crest height not
critical
• Suitable for mixed-print
substrates

• Not all fluxes have good foaming
capabilities
• Losses throught evaporation may
be appreciable
• Prolonged preheating because of
high boiling point of solvents

Wave
Fluxing

• Can be used with any
liquid flux

• Wave crest height is critical to
ensure good contact with bottom
of substrate without
contaminating the top

• Compatible with continuous
soldering process
• Suitable for denselypopulated mixed print
Spray
fluxing

• Can be used with most
liquid fluxes
• Short preheat time if
appropriate alcohol
solvents are used
• Layer thickness is
controllable

tween the metallization of the substrate and
the basic solvents.
Hydrophobic solvents do not mix with water
at concentrations exceeding 0.2%, and consequently have little effect on ionic contamination. They can be used to remove nonpolar contaminants such as rosin, oils, and
greases.
Hydrophillic solvents do mix with water and
can dissolve both polar and non-polar contamination, but at different rates. To overcome these differences, azeotropes of the
various solvents are formulated to maximize
the dissolving action for all types of contamination.

Solvent Cleaning
Two types of solvent cleaning systems are in
use today: batch and conveyorized systems,
either of which can be used for high-volume
production. In both systems, the contaminated substrates are immersed in the boiling
solvents, and ultrasonic baths or brushes may
also be used to further improve the cleaning
capabilities.
The washing of rosin-based fluxes offers
advantages and disadvantages. Washed substrates can usually be inserted into racks
easier, as there will be no residues on their
edges; test probes can make better contact
without a rosin layer on the test points, and
the removal of the residues makes it easier to
visually examine the soldered joints. On the
other hand, washing equipment is expensive,
and so are the solvents, and some solvents
present a health or environmental hazard if
not correctly dealt with.
February 1987

• High flux losses due to nonrecoverable spray
• System requires frequent
cleaning

and conform to local regulations. Today, the
problem of noxious fumes is unlikely to concern the cleaning station, as all commercial
systems are equipped to condense the vapors back into the system. In the future,
however, it can be expected that a much
lower degree of escape of noxious fumes
from any system will be allowed, and all
systems may have to be reviewed.
Certain fluxes, particularly some water-soluble ones, contain highly aggressive substances, and must not be allowed to come
into contact with the skin or eyes. Any contamination should immediately be removed
with plenty of clean, fresh water. Deionized
water should also be readily available as an
eye-wash. Should contamination occur, a
qualified medical practitioner should be consulted. Protective clothing should be worn
during cleaning or maintenance of the fluxing
station.

Conclusion

Aqueous Cleaning
For high-volume production, special machines have been developed in which the
substrates are conveyor-fed through the various stages of spraying, washing, rinsing, and
drying. The final rinse water is blown from the
substrates to prevent any deposits from the
water being left on the substrate.
Where water-soluble fluxes have been used
in the soldering process, substrate cleaning is
mandatory. For the rosin-based fluxes, it is
optional, and is often at the discretion of the
customer.

Conformal Coatings
A conformal, or protective coating on the
substrate, applied at the end of processing,
prevents or minimizes the effects of humidity
and protects the substrate from contamination by airborne dust particles. Substrates
that are to be provided with a conformal
coating (dependent on the environmental
conditions to which the substrate will be
subjected) must first be washed.

Environmental and Ecological
Aspects of Fluxes and Solvents
Fumes and vapors produced during soldering
processes, or during cleaning, will not, under
normal Circumstances, present a health hazard, if relevant health and safety regulations
are observed.
Fumes originating from colophony can cause
respiratory problems, so an efficient fumeextraction system is essential. The extraction
system must cover the fluxing, preheating,
and soldering stations, remain operational for
at least one hour after machine shutdown,

9-20

SMD technology imposes tougher restraints
on fluxing and cleaning of substrate assemblies. Traditionally, rosin-based fluxes have
been used in electronic soldering where residues were considered "safe" and could be
left on the board. However, increased SMD
packing density, fine-line tracks, and more
rigid specifications have resulted in changes
to this basic philosophy.
There is now a demand for surfaces free from
residues; test probes are more efficient when
they do not have to penetrate rosin flux
residues, and conformal coating and board
inspection benefit from the absence of such
residues.
Cleaning also poses problems for SMD substrates. The close proximity of component
and substrate means that solvents cannot
effectively clean beneath devices. Components must also be compatible with the cleaning process. They must, for example, be
resistant to the solvents used and to the
temperatures of the cleaning process. They
must also be sealed to prevent cleaning fluids
from entering the devices and degrading
performance.
So, eliminating the need for cleaning is better
than poor or incomplete cleaning. And in a
well-balanced system, mildly-activated rosinbased fluxes, leaving only non-corrosive residues, can be successfully used for SMD
substrate soldering without subsequent
cleaning.
Much research into fluxes and solder creams
is presently being done - for example, the
production of synthetic resin, with qualities
superior to colophony at a lower cost. Another area of research is that of solder creams
with non-melting additives, such as lead or
ceramic spheres, that increase the distance

Signetics Linear Products

Fluxing and Cleaning

fR

DETECTOR

CONVEYOR
DRIVE
MOTOR

TEMPERATURE SET
CONTROL PANEL

Figure 4. Schematic Diagram of a Typical Controlled Preheat System

Table 2. Substrate Contaminants
Contaminant
Organic compounds
Inorganic insoluble compounds
Organo·metallic compounds
Inorganic soluble compounds
Particle matter

Origin
Fluxes, solder mask
Photo·resists, substrate processing
Fluxes, substrate processing
Fluxes
Dust, fingerprints

between component and substrate, thus
making it easier for cleaning fluids to pene·
trate beneath the component. It also in·
creases the joint's ability to withstand thermal
cycling.
Rosin·free and halide·free fluxes are also
being developed with similar activities to con·
ventional rosin· based fluxes. These new
types will combine the "safety" of rosin
fluxes with easier removal in conventional
solvents. Using non·polar materials, ionizable
or corrosive residues are eliminated, and the
need for cleaning immediately after soldering
is avoided.

I
February 1987

9-21

Signetics

Thermal Considerations for
Surface-Mounted Devices

Linear Products

INTRODUCTION
Thermal characteristics of integrated circuit
(IC) packages have always been a major
consideration to both producers and users of
electronics products. This is because an increase in junction temperature (TJ) can have
an adverse effect on the long-term operating
life of an IC. As will be shown in this section,
the advantages realized by miniaturization
can often have trade-offs in terms of increased junction temperatures. Some of the
VARIABLES affecting TJ are controlled by
the PRODUCER of the IC, while others are
controlled by the USER and the ENVIRONMENT in which the device is used.
With the increased use of Surface-Mount
Device (SMD) technology, management of

thermal characteristics remains a valid concern, not only because the SMD packages
are much smaller, but also because the
thermal energy is concentrated more densely
on the printed wiring board (PW8). For these
reasons, the designer and manufacturer of
surface-mount assemblies (SMAs) must be
more aware of all the variables affecting TJ.

POWER DISSIPATION
Power dissipation (PD), varies from one device to another and can be obtained by
multiplying Vcc Max by typical Icc. Since Icc
decreases with an increase in temperature,
maximum Icc values are not used.

THERMAL RESISTANCE
The ability of the package to conduct this
heat from the chip to the environment is
expressed in terms of thermal resistance. The
term normally used is Theta JA (8JA)· 8JA is
often separated into two components: thermal resistance from the junction to case, and
the thermal resistance from the case to
ambient. 8JA represents the total resistance
to heat flow from the chip to ambient and is
expressed as follows:

8JC + 8CA

~

8JA

JUNCTION TEMPERATURE (TJ)
Junction temperature (TJ) is the temperature
of a powered IC measured by Signetics at the

illWJ.
1fTml
so LEAD FRAME

DIP LEADFRAME

DIP LEADFRAME

b. PLCC-68 Leadframe Compared
to a 64-Pin DIP Leadframe

a. SO-14 Leadframe Compared
to a 14-Pin DIP Leadframe
Figure 1
February 1987

9-22

Signetics Linear Products

Thermal Considerations for Surface-Mounted Devices

substrate diode. When the chip is powered,
the heat generated causes the T J to rise
above the ambient temperature (TA)' TJ is
calculated by multiplying the power dissipation of the device by the thermal resistance of
the package and adding the ambient temperature to the result.
TJ = (Po X ()JA)

+ TA

FACTORS AFFECTING fJJA
There are several factors which affect the
thermal resistance of any IC package. Effective thermal management demands a sound
understanding of all these variables. Package
variables include the leadframe design and
materials, the plastic used to encapsulate the
device, and, to a lesser extent, other variables such as the die size and die attach
methods. Other factors that have a significant
impact on the ()JA include the substrate upon
which the IC is mounted, the density of the
layout, the air-gap between the package and
the substrate, the number and length of
traces on the board, the use of thermallyconductive epoxies, and external cooling
methods.
PACKAGE CONSIDERATIONS
Studies with dual in-line plastic (DIP) packages over the years have shown the value of
proper leadframe design in achieving minimum thermal resistance. SM D leadframes
are smaller than their DIP counterparts (see
Figures 1a and 1b). Because the same die is
used in each of the packages, the die-pad, or
flag, must be at least as large in the SO as in
the DIP.
While the size and shape of the leads have a
measurable effect on ()JA, the design factors
that have the most significant effect are the
die-pad size and the tie-bar size. With design
constraints caused by both miniaturization
and the need to assemble packages in an
automated environment, the internal design
of an SMD is much different than in a DIP.
However, the design is one that strikes a
balance between the need to miniaturize, the
need to automate the assembly of the package, and the need to obtain optimum thermal
characteristics.
lEAD FRAME MATERIAL is one of the more
important factors in thermal management.
For years, the DIP leadframes were constructed out of Alloy-42. These leadframes
met the producers' and users' specifications
in quality and reliability. However, three to five
years ago the leadframe material of DIPs was
changed from Alloy-42 to Copper (ClF) in
order to provide reduced ()JA and extend the
reliable temperature-operating range. While
this change has already taken place for the
DIP, it is still taking place for the SO package.
February 1987

Signetics began making 14-pin SO packages
with ClF in April 1984 and completed conversion to ClF for all SO packages by 1985. As
is shown in Figures 10 through 14, the
change to ClF is producing dramatic results
in the ()JA of SO packages. All PlCCs are
assembled with copper leadframes.
The MOLDING COMPOUND is another factor
in thermal management. The compound used
by Signetics and Philips is the same high
purity epoxy used in DIP packages (at present, HC-l0, Type II). This reduces corrosion
caused by impurities and moisture.
OTHER FACTORS often considered are the
die-size, die-attach methods, and wire bonding. Tests have shown that die size has a
minor effect on ()JA (see Figures 10 through
14).
While there is a difference between the
thermal resistance of the silver-filled adhesive
used for die attach and a gold silicon eutectic
die attach, the thickness of this layer (1 - 2
mils) is so small it makes the difference
insignificant.
Gold-wire bonding in the range of 1.0 to 1.3
mils does not provide a significant thermal
path in any package.
In summary, the SMD leadframe is much
smaller than in a DIP and, out of necessity, is
designed differently; however, the SMD package offers an adequate ()JA for all moderate
power devices. Further, the change to ClF
will reduce the ()JA even more, lowering the TJ
and providing an even greater margin of
reliability.

Test Method
Signetics uses what is commonly called the
TSP (temperature-sensitive parameter) method. This method meets Mil-STD 883C, Method 1012.1. The basic idea of this method is to
use the forward voltage drop of a calibrated
diode to measure the change in junction
temperature due to a known power dissipation. The thermal resistance can be calculated using the following equation:

Test Procedure
TSP Calibration
The TSP diode is calibrated using a constanttemperature oil bath and constant-current
power supply. The calibration temperatures
used are typically 25°C and 75°C and are
measured to an accuracy of ± 0.1 °c. The
calibration current must be kept low to avoid
significant junction heating; data given here
used constant currents of either 1.0mA or
3.0mA. The temperature coefficient (K-Factor) is calculated using the following equation:

Where: K = Temperature Coefficient ('C/mV)
T2 = Higher Test Temperature (0C)
T1 = lower Test Temperature (OC)
VF2 = Forward Voltage at IF and T2
VF1 = Forward Voltage at IF and T1
IF = Constant Forward Measurement Current
(See Figure 2)

SIGNETICS' THERMAL
RESISTANCE
MEASUREMENTS - SMD
PACKAGES
The graphs illustrated in this application note
show the thermal resistance of Signetics'
SMD devices. These graphs give the relationship between ()JA uunction-to-ambient) or ()JC
uunction-to-case) and the device die size.
Data is also provided showing the difference
between still air (natural convection cooling)
and air flow (forced cooling) ambients. All ()JA
tests were run with the SMD device soldered
to test boards. It is important to recognize
that the test board is an essential part of the
test environment and that boards of different
sizes, trace layouts, or compositions may give
different results from this data. Each SMD
user should compare his system to the
Signetics test system and determine if the
data is appropriate or needs adjustment for
his application.

9-23

Figure 2_ Forward Voltage - Junction
Temperature Characteristics of a
Semiconductor Junction Operating at
a Constant Current. The K Factor is
the Reciprocal of the Slope

Thermal Resistance
Measurement
The thermal resistance is measured by applying a sequence of constant current and
constant voltage pulses to the device under
test. The constant current pulse (same current at which the TSP was calibrated) is used
to measure the forward voltage of the TSP.
The constant voltage pulse is used to heat
the part. The measurement pulse is very short

I

Signetics Linear Products

Thermal Considerations for Surface-Mounted Devices

(less than 1% of cycle) compared to the
heating pulse (greater than 99% of cycle) to
minimize junction cooling during measurement. This cycle starts at ambient temperature and continues until steady-state conditions are reached. The thermal resistance
can then be calculated using the following
equation:
0JA

= .:lTJ = K(VFA -

VFS)
VH X IH

PD
Where: VFA

= Forward Voltage of TSP at Am-

VFS

= Forward Voltage of TSP at

bient Temperature (mV)
Steady-State Temperature
(mV)

= Heating Voltage (V)
= Heating Current (A)
Test Ambient
VH
IH

0JA Tests
All 0JA test data collected in this application
note was obtained with the SMD devices
soldered to either Philips SO Thermal Resistance Test Boards or Signetics PLCC Thermal Resistance Test Boards with the following parameters:
Board size

- SO Small
1.12" X 0.75" X 0.059"
- SO Large:
1.58" X 0.75" X 0.059"
-PLCC:
2.24" X 2.24" X 0.062"

Board Material- Glass epoxy, FR-4 type
with 1oz. sq.ft. copper solder coated
Board Trace Configuration - See Figure 3.
SO devices are set at 8 - 9mil stand-off and
SO boards use one connection pin per device
lead. PLCC boards generally use 2 - 4 connection pins regardless of device lead count.
Figure 5 shows a cross-section of an SO part
soldered to test board, and Figure 4 shows
typical board/device assemblies ready for 0JA
Test.
The still-air tests were run in a box having a
volume of 1 cubic foot of air at room temperature. The air-flow tests were run in a 4" X 4"
cross-section by 26" long wind tunnel with air
at room temperature. All devices were
soldered on test boards and held in a horizontal test position. The test boards were held in
a Textool ZIF socket with 0.16" stand-off.
Figure 6 shows the air-flow test setup.
0JC Tests
The IJJC test is run by holding the test device
against an "infinite" heat sink (water-cooled
block approximately 4" X 7" X 0.75") to give

February 1987

Figure 4. Device/Board Assemblies
a 0CA (case-to-ambient) approaching zero.
The copper heat sink is held at a constant
temperature ("'20°C) and monitored with a
thermocouple (0.040" diameter sheath,
grounded junction type K) mounted flush with
heat-sink surface and centered below die in
the test device. Figure 7 shows the 0JC test
mounting for a PLCC device.
SO devices are mounted with the bottom of
the package held against the heat sink. This
is achieved by bending the device leads
straight out from the package body. Two
small wires are soldered to the appropriate
leads for tester connection. Thermal grease
is used between the test device and heat sink
to assure good thermal coupling.
PLCC devices are mounted with the top of
the package held against the heat sink. A

9-24

n

TESTDEVlCE

PART srAN[).()FF
TEsrBOARD
PLASTIC PIN
SUPPORT
CONNECTION
PINS

Figure 5. Cross-Section of Test Device
Soldered to Test Board
small spacer is used between the hold-down
mechanism and PLCC bottom pedestal.
Small hook-up wires and thermal grease are
used as with the SO setup. Figure 7 shows
the PLCC mounting.

Signetics Linear Products

Thermal Considerations for Surface-Mounted Devices
--------------------,-"--------------

so DEVICES

PlCC DEVICES

~AIRFLOW

~A'RFLDW

TEST DEVICE

/ ,---TESTBOARD

~

TESf BOARD STAN[).()FF

_

TEXTOOL ZlF SOCKET

TH ERMOCOUPLE

SUPPORT
BOARD

SO Devices

DATA PRESENTATION
The data presented in this application note
was run at constant power dissipation for
each package type. The power dissipation
used is given under Test Conditions for each
graph. Higher or lower power dissipation will
have a slight effect on thermal resistance.
The general trend of thermal resistance decreasing with increasing power is common to
all packages. Figure B shows the average
effect of power dissipation on SMD 8JA.

Example: Determine approximate junction
temperature of SOL-20 at 0.5W dissipation using 10,000 sq. mil die
and copper leadframe in still air and
200 LFPM air-flow ambients. Given
TA = 30'C,

Thermal Calculations
The approximate junction temperature can be
calculated using the following equation:
TJ = (8JA X PD) + TA

= Junction

Temperature ('G)

8JA = Thermal Resistance Junctionto-Ambient ('C/W)
PD

Answer: BB'C/W

@

TA = Temperature of Ambient ('G)

3. Determine 8JA @ 0.5W in 200
LFPM air flow from Average Effect of Air Flow on SMD 8JA,
Figure 9.

0.7W

From Figure 9: 200 LFPM air flow
gives 14% decrease in 8JA
Answer:
91 'C/W - (91 X 0.14)

Percent change in Power
0.5W-0.7W

Answer:
TJ (still-air)
= (91'C/W X 0.5W) + 30
= 76'C
TJ (200 LFPM)
= (7B'C/W x 0.5W) + 30
= 69'C

= -2B.6%

EFFECTIVE RANGE
so: O.3to1.0W
PLCC: 0.5 to 2.0W

~'"

= 78'C/W

4. Calculate approximate junction
temperature

X 100

0.7W

\

~

...

".z

1\

:I:

<>
...z<> -2
a:

I-

r-:.

c - 5 ~If'.~::";':::::':::::;'

~

~ -10 ~'F~~~,-t---j-+-+-+-I--I

........

..

w -4

I'

-6
-8
-ro-~-~o

~

~

ro

Wl00l~l~

PERCENT CHANGE IN POWER

= Power

Dissipation at a TJ
(Vee x leel (W)

Answer:
88'C/W + (88 X 0.035)
= 91 'C/W @ 0.5W

2. Determine 8JA @ 0.5W using Average Effect of Power Dissipation
on AMD 8JA, Figure B.

SO devices are currently available in both
copper or alloy 42 leadframes; however,
Signetics is converting to copper only. PLCC
devices are only available using copper leadframes.
The average lowering effect of air flow on
SMD 8JA is shown in Figure 9.

From Figure B:
28.6% change in power gives
3.5% increase in 8JA

1. Find 8JA for SOL-20 using 10,000
sq. mil die and copper leadframe
from typical 8JA data - SOL-20
graph.

Thermal resistance can also be affected by
slight variations in internal leadframe design
such as pad size. Larger pads give slightly
lower thermal resistance for the same size
die. The data presented represents the typical Signetics leadframel die combinations
with large die on large pads and small die on
small pads. The effect of leadframe design is
within the ± 15% accuracy of these graphs.

Where: TJ

Figure 7. 8JC Test Setup
With PLCC Device

PLCC Devices
Figure 6. Air-Flow Test Setup

~ -15 1--t\~ISl.oI.-'t"'--k+
;! - ~ 1-+-\f---I~Ib..+-I-~"'-.f--+--j
<>
~ - 25 f--+--f''d--P'R~-.d-

ffi -30 ~+-++=>.t:
.. - 35

"'I-.2"j--H

I-+-+---t-Y'--P'....

-~

Figure 8. Average Effect of Power
Dissipation on SMD 8JA

- 4S '---'--'-.!-.J.......L-..L-..J........L....L...J

o

100 200 300

~o

BOO

roo

700 800 BOO 1000

AIR FLDW (LFPM)

Figure 9. Average Effect of Air Flow
on SMD 8JA

February 19B7

9-25

I

Signetics Linear Products

Thermal Considerations for Surface-Mounted Devices

Typical BJA Data SO-8'
300

- ~

250

1)tpical BJA Data SO-14'

Ll421 LJDF~Mi

1)tpical BJA Data SO-16'
300

300

~l'-

-

250

f-- ~

COPPER LEAD FRAME

LLILJDF~Ml

~'-

250

I-

r- ••~~..l r r ' M E

COPPER LEADFRAME

COPPER

100

100

100

50

50

50

o

o
0'23456789'0

012345878910

DIE SIZE (SO MILS x 1000)

DIE SIZE (SO MILS x 1000)

1)tplcal BJA Data SOI.-16 2

o

1)tpical8JA Data SOL-243

1)tplcal BJA Data SOl.-20 3
300

300

250

250

250
200

200

-

~

.$l 150

....... ~LOY 42 LEADFRj"ME

J

j"

r;;

~Y

100

100
COPiER LiDFRAjE

J

42 LEADFRtME

ALLOY

100

510152025
DIE SIZE (SO MILS x 1000)

30

o

o

o

10

15

20

25

30

o

DIE SIZE (SQ MILS x 1000)

NOTES:
1. TEST CONDITIONS:

1)tplcal8JA Data SOL·28 3
300

Still air
O.SW

Test ambient:
Power dissipation:
Test fixture:
Accuracy:

250

Philips PCB (1.12" X 0.75" X 0.059")
±15%

2. TEST CONDITIONS:

200

Still air
O.5W

Test ambient:
Power dissipation:
Test fixture:
Accuracy:

100 l - I--

ALLOY

42 LEADFRAME,-- f-

COPPER LEADFRAME

50

o

5

10 15 20

~

30

~

~

Philips PCB (1.58" x 0.75" x 0.059")
±15%

3. TEST CONDITIONS:
Still air
O.7W

Test ambient:
Power dissipation:
Test fixture:
Accuracy:

Philips PCB (1.58"

x 0.75"

X 0.059")

±15%

% 50

DIE SIZE (SO MILS x 1000)

Figure 10. Typical SMD Thermal (IiJA) Characteristics

February 1987

9..26

42 LEADFRAME

-

COPPER LEADFRAME

50

50

o

150

COPPER LEADFRAME

50

o

012345678910
DIE SIZE (SO MILS x 1000)

300

o

L~DFRAME

510152025
DIE SIZE (SO MILS x 1000)

30

Signetics Linear Products

Thermal Considerations for Surface-Mounted Devices

TypicalBJA Data PLCC·28 1

TypicalBJA Data PLCC-20 1

100

100

90

90

90

80

80

......

70

70

~ 80

~ 80

50

50

E

~

~

......

-

90

ro
~

~

50

~40

30

30

30

20

20

20

10

10

o

o

051015202530354045505560

DIE SIZE (SQ MILS x 1000)

DIE SIZE (SO MILS x 1000)

o

100

9Or-+-+-~-r-r-+-+~~~

90

90

8Or-+-+-~-r-r-+-+~~~

80

80

ro

ro

ro

!80I-t-t-t-t-f-..,H---I---I-l
E50I-t-+-+++-+-+--+-l-l
40

t-t-t---f"t-i-I==I=4==I==l

~

~c

80

3Or-+-+-~-r-r-+-+~~~

30

20

20

r-+-~-r-+~--r-+-+--r~

10

10

o

0

o

10

20 30 40

50

60

ro

80

90

100

Still air

Accuracy:

±15%

TAB BONDED

I I I

WIRE BONDED

10
0

~~~~x~

NOTES,
1. TEST CONDITIONS,
Test ambient:
Power dissipation:
Test fixture:

-

50

O? 40

10

20 30 40

50 60 70 80

90

0

100

0

~~~~x~

2. TEST CONDITIONS,
Test ambient:
Power dissipation:
Test fixture:

0.7SW
Signetics PCB

(2.24" X 2.24" X 0.062")

Accuracy:

10 20 30 40 50 60 70 80 90 100

TyplcalBJA Data PLCC-84 3

100

r-+-+--r-r-+~--r-+-+-~

o

DIE SIZE (SO MILS x 1000)

lYplcal BJA Data PLCC-68 2

TypicalBJA Data PLCC·S2 1

I--

10

051015202530354045505560

,..,..r,;-,-,-,-,-,-..,-,

100

-

80

40

~~ 40

~~

TypicalBJA Data PLCC·44 1

100

10

20 30 40

50 80 70 80

90 100

~~~~x~

Signetics PCB

3. TEST CONDITIONS,
Test ambient
Power dissipation:
Test fixture:

Still air
1.5W
Signatjcs PCB

(2.24" x 2.24" X 0.062")
±15%

Accuracy:

(2.24" X 2.24" X 0.062")
±15%

Still air

1.0W

Figure 11. Typical SMD Thermal

(OJA)

Characteristics

•
February 1987

9-27

Signetics Linear Products

Thermal Considerations for Surface-Mounted Devices

lYPical 8JC Data 50·14 1

Typical8Jc Data 50-8 1

so
46

40

C6PPER LEADFRAME

35

-

50

45

45

40
35
COPPER LEADFRAME

~ 30

~

Typical8JC Data 80.16 1

50

30

40

-

~
~

25

:;'20

,;' 20

~~

20

15

15

15

10

10

10

~

25

so

~

Typical8Jc Data 5OL·16 1

o

012345678910
DIE SIZE (SO MILS x 1000)

so

'!yplcal8JC Data 5OL·20 2

so

46

40

40

40

35

35

35

~K

~

COPPER LEADFRAME -

25

25

~~

20

0

20

30

~

15

15

10

10

o

o

10

15

DIE SIZE (sa MILS

so

20

25

30

o

x 1000)

45

--

o

35

~ 30
~ 25 t<:o~ 20

..... f'.~PER LEADFRAME- r--

~
0

~~

20
15
10

15

20
25
DIE SIZE (SO MILS x 1000)

30

O.5W
"Infinite" heat sink
±15%

O.7W
"Infinite" heat sink
±15%

3. TEST CONDITIONS:
Power dissipation:
Test fixture:

1.0W
"Infinite" heat sink
±15%

Accuracy:

10

~

20 25 30 35 40 46

so

DIE SIZE (SO MILS x 1000)
OPO:z57O$

Figure 12. Typical SMD Thermal (OJc) Characteristics

February 1987

9-28

-

COPPER LEADFRAME

15

o

lYPical8JC Data 80L·24 3

25

10

o

012345678910
DIE SIZE (Sa MILS x 1000)

30

o
10

2. TEST CONDITIONS:
Power dissipation:
Test fixture:
Accuracy:

40

~

~ ~PPER LEADFRAME- -

NOTES:
1. TEST CONDITIONS:
Power dissipation:
Test fixture:
Accuracy:

Typical 8JC Data 501.-28 3

- -

45

46

~ 30

P

o

012345678910
DIE SIZE (sa MILS x 1000)

COPPER LEADFRAME

0

0

o

f- -

30

25

~

-

35

o

10

15

20

25

DIE SIZE (sa MILS x 1000)

30

Signetics linear Products

Thermal Considerations for Surface-Mounted Devices

Typical8Jc Data PLCC·2S 2

Typical 8JC Data PLCC.20 1
50
45

40

...

35

i

~

~

" I"""-r-r-.

30
25

~

50

45

45

40

40

35

35

r"\

30

~

25

~~

20

"

20

Typical 8JC Data PLCC-44 2

50

~

I"

......

30

~ 25

"

q;> 20

15

15

15

10

10

10

o

o

051015202530354045505560
DIE SIZE (SO MILS

x

o

051015202530354045505560

1000)

1}rplcal 8JC Data PLCC-52 2

Typical 8JC Data PLCC.84 3

Typical 8JC Data PlCC-68 3
50

45

45

40

40

35

1-+-+-+-+-+-+-+++-1

i

30

I-t--H--I-+-+-+-+-+-i

~

25 1-++-4-+-+-+-+---,+-+--1

~

25

~

25

20 1-++-4-+-+-+-+-+-+--1

q;>

20

q;>

20

15 t-t-HI-t=F~,,*,+:::j
101-+-+-+-4-1--+-+-+-+--1
0L-L-L-L-~~~~~~

10 20 30 40 50 60 70 80 90 100
DIE SIZE (SO MILS x 1000)

35

i

"

35

!

30

"

30

~

15
10

o

10 20 30 40 50 60 70 80 90 100
DIE SIZE (SO MILS x 1000)

50

451-t-t-t-t-I--I--HH:-I
401-t-t-t--t--I--I--HH:-I

o

o

DIE SIZE (SO MILS x 1000)

5Or-~-r-r-'-'--r-~~-r,

~

1'- b

TA~ONDED

wiRE
.. ~

15

~oNIDED- r- r-

10

o

10 20 30 40 50 60 70 80 90 100
DIE SIZE (SO MILS x 1000)

o

o

10 20 30 40 50 80 70 80 90 100
DIE SIZE (sa MILS x 1000)

NOTES:
1. TEST CONDITIONS:

Power dissipation:
Test fixture:
Accuracy:
2. TEST CONDITIONS:
Power dissipation:
Test fixture:

O.75W
"Infinite" heat sink
±15%

Accuracy:

1.0W
"infinite" heat sink
±15%

3. TEST CONDITIONS:
Power dissipation:
Test fixture:

2.0W
"Infinite" heat sink

Accuracy:

±15%

Figure 13. Typical SMD Thermal (OJc) Characteristics

II
February 1987

9-29

Signetics Linear Products

Thermal Considerations for Surface-Mounted Devices

Effect of Device Stand-Off
on SO OJA 1

Effect of Board Size
on SO OJA 2

88

Effect of Trace Length on
28-Lead PLCC OJA 3

220

87

95

90

210

86
85

j'

!'

84

E. 83

~~ 180

81
80

79

190

E

 .003)
.180:1: .07

853-0174 88070

14·PIN PLASTIC SO (0 PACKAGE)
NOTES:
1. Package dimensions conform to JEDEC specification
MS-012-AB for standard small outline (SO) package, 14
leads, 3.75mm (.150") body width {issue A, June 1985}.
2. Controlling dimensions are in mm. Inch dimensions in
parentheses.
3. Dimensions and tolerancing per ANSI Y14.5M- 1982.
4. "T", "0" and "E" are reference datums on the molded
body and do not include mold flash or protrusions. Mold
flash or protrusions shall not exceed .15mm (.006") on
any side.
5. Pin numbers start with pin # 1 and continue
counterclockwise to pin # 14 when viewed from top.
6. Signetics ordering code for a product packaged in a
plastic small outline (SO) package is the suffix 0 after
the product number.

t

4.00 (.157)

I+IE ®I .25

(.010)

® 1

r

(.061 •.008)
~

m
§I.10 ('OO4j
.49 (.019)
.35 (.014)

1.1 T1E1D®I

.25 (.010) @

1

L-~~

I

.25 (.010)
.19(.007)

853-0175 88068

February 1987

.50 (.020) x45°
.25 (.010)

9-37

(.007 •.003)
.180:1:.07

8

0

(.025 •.006)
.635 :1:.15

I

Signetics Linear Products

For Prefixes ADC, AM, CA, DAC, LF, LM,
MC, NE, SA, SE, SG, pA, ULN

Package Outlines

16-PIN PLASTIC SO (D PACKAGE)
r--+t1o®t .10 (.004)

~

NOTES:
1. Package dimensions conform to JEDEC specification
MS-012-AC for standard small outline (SO) package, 16
leads, 3.7Smm (.150") body width (issue A, June 1985).
2. Controlling dimensions are in rnm. Inch dimensions in

~;,---------r

i

parentheses.
3. Dimensions and tolsrancing per ANSI Y14.SM- 1982.

(.236

:I:

4. "T", "0" and "E" are reference datums on the molded

.006)

-s;-::;-r

body and do not include mold flash or protrusions. Mold
flash or protrusions shall not exceed .1Smm (.006") on
any side.
5. Pin numbers start with pin #1 and continue
counterclockwise to pin #16 when viewed from top.
6. Signatjes ordering code for a product packaged in a
plastic small outline (SO) package is the suffix Dafter
the product number.

t.tE®t .25 (.010) ® t

m

'
L
--J

lr

~

L - n = .(.010)
25

:::8)

&~~H~H~~H~H~~H~~M~D~~utia (;":~
§.10(.00~1
~~~ ~
.49 (.019)
.35 (.014)

-1+1 T 1E lo®1 .25

.50 (.020) x45°

I
.25 (.010)
.19 (.007)

(.oi§JiJ

~

-==f
(.007 dlO3)
.180:t.07

(.025 •.006)
.635;1:,15

853-0005 88069

16-PIN PLASTIC SOL (0 PACKAGE)
~D®I.'0 (.004)~

'~

I

10.65 (.419)
10.2<) (.404)
1.IE®I·25 (.010) ® 1

U,.27 (.050)

NOTES:
1. Package dimensions conform to JEDEC specification
MS'()13-AA for standard small outline (SO) package, 16
leads, 7.50mm (.300") body width (issue A, June 1985),
2. Controlling dimensions are in mm. Inch dimensions in
parentheses.
3. Dimensions and tolerancing per ANSI Y14.5M-1982.
4. "T', "D" and "E" are reference datums on the molded
body and do not include mold flash or protrusions. Mold
flash or protrusions shall not exceed .15mm (.006") on
any side.
5. Pin numbers start with pin #1 and continue
counterclockwise to pin # 16 when viewed from top.
6. Signetics ordering code for a product packaged in a
plastic small outline (SO) package is the suffix Dafter
the product number.

r

esc

-O-r-----~----- ~~~~:;~:~

.75 (.030) X45°
.50 (.020)

I

2.65 (.104)

[iJ

g

I
---l

.10 (.004) 1

L

2.35 (.093)
/

.32 (.013)
.23 (.009)

.49 (.019) -1+1 T 1 Elo®I.25 (.010) @
.35 (.014)

853-0171 81218

February 1987

9-38

.10 (.004)

0.86 (.034)

Signetics Linear Products

For Prefixes ADC, AM, CA, DAC, LF, LM,
MC, NE, SA, SE, SG, pA, ULN

Package Outlines

20-PIN PLASTIC SOL (0 PACKAGE)
I+lo@1 .10 (.004) I

NOTES:
1. Package dimensions conform to JEDEC specification
MS·013·AC for standard small outline (SO) package, 20
leads, 7.50mm (.300' ') body width (issue A, June 1985).
2. Controlling dimensions are in mm. Inch dimensions in

11

parentheses.
3. Dimensions and tolsrancing per ANSI Y14.SM-1982.
4. "T". "DO! and "E" afe reference datums on the molded
body and do not include mold flash or protrusions. Mold
flash or protrusions shall not exceed .1Smm (.006") on
any side.
5. Pin numbers start with pin # 1 and continue
counterclockwise to pin #20 when viewed from top.
6. Signetics ordering code for a product packaged in a
plastiC small outline (SO) package is the suffix 0 after
the product number.

10,65 (.419)
10.26 (.404)

7.40 (.291)

I

i+!E@! .25 (.010)

m

®

I

I

U , . 2 7 (.050)

r·

esc

13.00 (.512)

7 5 (.030) X45
.50 (.020)

-o-r---~-------- '2.60 (.496)

0

I

2.65 (.104)

!¢l.'0 (.004)

I

I

---I

L

2.35 (.093)
I

.49 (.0'9)

:35(.014)

1.07 (.042)

'+!TIElo@I.25(.010)@

.86 (.034)

.23 (.009)

853·0172 81219

24-PIN PLASTIC SOL (0 PACKAGE)

11

I

10.65 (.419)

7.60 (.299)

'0.26 (.404)

7.40 (.29')

I
m
j

-0

-r-----t--------

ffIE@I.25 (.010) @

I

NOTES:
1. Package dimensions conform to JEOEC specification
MS-013-AO for standard small outline (SO) package, 24
leads, 7.50mm (.300") body width (issue A, June 1985).
2. Controlling dimensions are in mm. Inch dimensions in
parentheses.
3. Dimensions and tolerancing per ANSI Y14.5M- 1982.
4. "T", "0" and "E" are reference datums on the molded
body and do not include mold flash or protrusions. Mold
flash or protrusions shall not exceed .15mm (.006") on
any side.
5. Pin numbers start with pin #1 and continue
counterclockwise to pin #24 when viewed from top.
6. Signetics ordering code for a product packaged in a
plastic small outline (SO) package is the suffix Dafter
the product number.

·
r
l

'5.60 (.6'4)
, 5.20 (.596)

7 5 (.030) X45
.50 (.020)

0

~

I

2.65 (.'04)
2.35 (.093)

t

853..()17:3 81220

February 1987

9-39

.32 (.0'3)

.30 (.0'2)

'.07 (.042)

.23 (.009)

.'0 (.004)

.86 (.034)

Signetics Linear Products

For Prefixes ADC, AM, CA, DAC, LF, LM,
MC, NE, SA, SE, SG, pA, ULN

Package Outlines

28-PIN PLASTIC SOL (D PACKAGE)

Iij! ID®I .10 (.004) I

NOTES:
1, Package dimensions conform to JEDEC specification
MS-013·AE for standard small outline (SO) package, 28
leads, 7.50mm (.300") body width (issue A, June 1985).
2. Controlling dimensions are in mm. Inch dimensions in

parentheses.
3. Dimensions and tolerancing per ANSI Y14.5M-1982.
4. "T", liD" and "E" are reference datums on the molded
body and do not include mold flash or protrusions. Mold
flash or protrusions shall not exceed .15mm (.006") on
any side.
5. Pin numbers start with pin #1 and continue
counterclockwise to pin #28 when viewed from top.
6. Signetics ordering code for a product packaged in a
plastic small ouUine (SO) package is the suffix Dafter
the product number.

7.60 (.299)
7.40 (.291)

r·

W,.27 (.050) BSC
18.10 (.713)
17.70 (.897)

-D-

75 (.030) X45"

.so (.020)

ffi~

t

2.65 (.104)
2.35 (.093)

T eo..>;(·",OO4:::)!..J'X
hlJ=..::.,

t

I
.32 (.013)
.23 (.009)

853-0006 81217

4-PIN HERMETIC TO-72 HEADER (E PACKAGE)

February 1987

9-40

~L-

_ _- - '

.30 (.012)
.10 (.004)

Signetics Linear Products

For Prefixes ADC, AM, CA, DAC, LF, LM,
MC, NE, SA, SE, SG, pA, ULN

Package Outlines

a-PIN CERDIP (FE PACKAGE)
.055 (1.40)
.030 (.76)

I l

NOTES:
1. Controlling dimension: inches. Millimeters are shown in

.055 (1.40)
.030 (.76)

parentheses .
2. Dimensions and tolerancing per ANSI Y14.SM - 1982.
3. "T", "0", and "E" are reference datums on the body
and include allowance for glass overrun and meniscus on
the seal line, and lid to base mismatch.
4. These dimensions measured with the leads constrained
to be perpendicular to plane T.
5. Pin numbers start with pin # 1 and continue
counterclockwise to pin #8 when viewed from the top.

i - - - - j - - . 1 0 0 (2.54) SSC

J L . 0 2 3 (.58)---itITIE lo®I.010 (.254)
.015 (.38)
853-0580 81594

14-PIN CERDIP (F PACKAGE)

1

NOTES:
1. Controlling dimension: inches. Millimeters are shown in
parentheses .
2. Dimensions and tolsrancing per ANSI Y14.5M - 1982.
3. "T", "0", and "E" are reference datums on the body
and include allowance for glass overrun and meniscus on
the seal line, and lid to base mismatch.
4. These dimensions measured with the leads constrained
to be perpendicular to plane T.
5. Pin numbers start with pin #1 and continue
counterclockwise to pin # 14 when viewed from the top .

.110 (2.79)
.050 (1.27)

rr

.320 (8.13)

.290 (7.37)
(NOTE 4)

,:

1
I
H

!

~
-l

J L · 0 2 3 (.58)--,-j$jTIElo®I.010 (.254)
.015 (.38)
853-0581 81594

February 1987

9-41

.30&W62)
(NOTE 4)
.395 (10.03)
.300 (7.62)

1~
t-

Signetics Linear Products

For Prefixes ADC, AM, CA, DAC, LF, LM,
MC, NE, SA, SE, SG, pA, ULN

Package Outlines

16-PIN CERDIP (F PACKAGE)

1[

NorES:
1. Controlling dimension: inches. Millimeters are shown in

.060 (1.52)
.012 (.30)

parentheses.
2. Dimensions and tolerancing per ANSI Y14.5M -

1982.

3. "T", "0", and "E" are reference datums on the body
and include allowance for glass overrun and meniscus on
the seal line, and lid to base mismatch.

_~~~~..L.!>...<::y!

4. These dimensions measured with the leads constrained
to be perpendicular to plane T.
5. Pin numbers start with pin # 1 and continue
counterclockwise to pin # 16 when viewed from the top.

.306 (7.77)
.245 (6.22)

~~+=~~~~~~

J L ' 0 2 3 (.58)-t®rIE lo®I.Ol0 (.254)
.015 (.38)
853·0582 81594

18-PIN CERDIP (F PACKAGE)
NOTES:
1. Controlling dimension: inches. Millimeters are shown in

parentheses.
2. Dimensions and tolerancing per ANSI Y14.5M - 1982.
3. "T", "D", and "E" are reference datums on the body
and include allowance for glass overrun and meniscus on
the seal line, and lid to base mismatch.
4. These dimensions measured with the leads constrained
to be perpendicular to plane T.
5. Pin numbers start with pin #1 and continue
counterclockwise to pin # 18 when viewed from the top.

,320 (8.13)
,290 (7,37)
(NOTE 4)

~

, :

j

C

J L ' 0 2 3 (.58)-i$I rl Elo@j.Ol0 (.254)

853-0583 81594

February 1987

.30g~.62)
~
(NOTE 4)

.395 (10,03)
.300 (7,62)

.015 (.38)

9·42

i"

Signetics Linear Products

For Prefixes ADC, AM, CA, DAC, LF, LM,
MC, NE, SA, SE, SG, pA, ULN

Package Outlines

20-PIN CERDIP (F PACKAGE)

I---

I

.078 (1.98)
.012 (.30)

NOTES:

1

1. Controlling dimension: inches. Millimeters afe shown in
parentheses.
2. Dimensions and tolerancing per ANSI Y14.SM - 1982.
3. "T", "D", and "E" are reference datums on the body
and include allowance for glass overrun and meniscus on
the seal line, and lid to base mismatch.
4. These dimensions measured with the leads constrained
to be perpendicular to plane T.
5. Pin numbers start with pin # 1 and continue
counterclockwise to pin #20 when viewed from the top.

-0-

J L . 0 2 3 (.58)-1$1 TIE ID@i.D10 (.254)
.015 (.38)
853-0584 81594

22-PIN CERDIP (F PACKAGE)

1

r

.060 (1.52)
.028 (.71)

'---~~~~~""-'I
.399 (10.14)

:J_:r
JL

1. Controlling dimension: inches. Millimeters are shown in
parentheses.
2. Dimensions and tolerancing per ANSI Y14.5M - 1982.
3. "T", "0", and "E" are reference datums on the body
and include allowance for glass overrun and meniscus on
the seal line, and lid to base mismatch.
4. These dimensions measured with the leads constrained
to be perpendicular to plane T .
5. Pin numbers start with pin # 1 and continue
counterclockwise to pin #22 when viewed from the top.

.070 (1.78)

.420 (10.67)

.050 (1.27)

.390 (7.36)
(NOTE 4)

•

.023 (.58)--l$ITIEID@I.010(.254)
.015 (.38)

853-0585 81594

February 1987

NOTES:

9-43

I

Signetics Linear Products

For Prefixes ADC, AM, CA, DAC, LF, LM,
MC, NE, SA, SE, SG, pA, ULN

Package Outlines

24-PIN CERDIP (F PACKAGE)
NOTES:
1. Controlling dimension: inches. Millimeters are shown in

parentheses.
2. Dimensions and tolerancing per ANSI Y14.SM - 1982.
3. "T", "0", and "E" are reference datums on the body
and include allowance for glass overrun and meniscus on
the seal line, and lid to base mismatch.
4. These dimensions measured with the leads constrained
to be perpendicular to plane T.
5. Pin numbers start with pin # 1 and continue
counterclockwise to pin #24 when viewed from the top.

.620 (15.75)
.175 (4.45)
.145 (3.68)

.590 (14.99)
(NOTE 4)

853·0588 84221

r·

28-PIN CERDIP (F PACKAGE)
ooe

(2.4O)

SEE NOTE.

.()4()(1.G2)

NOTES:
1. Controlling dimension: inches. Millimeters are shown in
parentheses.
2. Dimensions and tolerancing per ANSI Y14.5M - 1982.
3. "T", "D", and "E" are reference datums on the body
and include allowance for glass overrun and meniscus on
the seal line, and lid to base mismatch.
4. These dimensions measured with the leads constrained
to be perpendicular to plane T.
6. Pin numbers start with pin # 1 and continue
counterclockwise to pin #28 when viewed from the top.
6. Denotes window location for EPROM Products.

PIN #1

JL

.100(2.54)BSC

.o-f--+------

1.485(S7.72)

1.4-40(38.58)
.176 {4.45}

~

.620 {15.75)J
.590 (14.98)
(NOlE 4)

, '

853-0589 84000

February 1987

9-44

Signetics Linear Products

For Prefixes ADC, AM, CA, DAC, LF, LM,
MC, NE, SA, SE, SG, pA, ULN

lr

Package Outlines

20-PIN PGA (G PACKAGE)
·5..

l~
lr~tll~
X .025
.015 (.84)
(.38)

h
45-

x~
.035 ( .89)

PIN #1

(3 CORNERS)

.055 (1.40)

~

NOTES:
1. Package dimensions conform to Mil-M-38510, outline NO.
C - 2, 20 leads, square ceramic leadless chip carrier.
2. Controlling dimension: inches, millimeters are shown in
parenthesis.
3. Dimension and tolerancing per ANSI Y14.SM - 1982.
4. This dimension represents the minimum spacing between

l

the comer contact pads. These corner pads may have a
,020 inch by 45 degree maximum chamfer to accomplish
the .015 minimum spacing .
5. Pin numbers start with pin #1 and continue
counterclockwise to pin #20 when viewed from the top.
6. Signetics order code for product packaged in a CCCL is
the suffix "G" after the product number.

.360 (9.14)

.M'r8'S)

~

4-l

~

.015(.38)
--TYP.

.003 (.08)

.360 (9.14)
.345 (8.76)

l

'O'" (.71) TYP.-J

.022 (.56)

~

.083 (1.60)

l.-

J

.085 (2.16) 'TYP•
.066 (1.65)
.015 (.38) MIN.

I'" CORNERS)
853~0063

82276

8-PIN HERMETIC TO-S HEADER (H PACKAGE)

114 (045) INSULATOR

0.38 (.015)
0.48 (.019) OIA

'O:ii'TOl6r
8 LEAOS

February 1987

9-45

Signetics Linear Products

For Prefixes ADC, AM, CA, DAC, LF, LM,
MC, NE, SA, SE, SG, /lA, ULN

Package Outlines

10-PIN HERMETIC TO-S/100 HEADER SHORT CAN (H PACKAGE)

10-PIN HERMETIC TO-S/100 HEADER TALL CAN (H PACKAGE)

T~'76(030)

+

6.48 L25S)

0.51 (.020)

I

5.97"T.2"35i

1.14 {.04S1 INS

~38 (,015)

14.28 (.562)

~

1.02 (.0401
0.74 e029)

February 1987

9-46

TOR
ULA

Signetics linear Products

For Prefixes ADC, AM, CA, DAC, LF, LM,
MC, NE, SA, SE, SG, pA, ULN

Package Outlines

16-PIN HERMETIC SDIP (I PACKAGE)

II ~[~~]~l~
I
20.70 C8lS)

r-- ~~:: i:~~~)l

1.65 (.06S)
0.51 (,020) I

12.45 (.490)

1.40 (.055)
0.63 (.025)

-I

8.13 (.320)
7.37 (.2901

I

-1-i-rrkdFirr~~~~m?~~~~ii3.~~~I~.'~~~)·f:~~::~-LTr
~
(Note

T

13.(.005) MIN

0.31 (,0121
_ - L_ _

~

0T0T00ii"
8.74 (.344)
7.11 (.280)

8-PIN PLASTIC PDIP (N PACKAGE)
NOTES:
1. Controlling dimension: inches. Metric are shown in
parentheses.
2. Package dimensions conform to JEDEC specification
MS-001-AB for standard dual in-line (DIP) package .300
inch row spacing (PLASTIC) 6 leads (issue B. 7/85)
3. Dimensions and tolerancing per ANSI Y14. 5M-1982.
4. "T", "D" and "E" are reference datums on the molded
body and do not include mold flash or protrusions. Mold
flash or protrusions shall not exceed .010 inch (.25mm)
on any side.
5. These dimensions measured with the leads constrained
to be perpendicular to plane T.
6. Pin numbers start with pin # 1 and continue
counterclockwise to pin #8 when viewed from the top .

.245 (6.22)

!I-r-!-....,....,..,~~

~r

I

•100 (2.54) (BSG)

---I

.376 (.955)
.365 (.930)
.064 (1.63)
.045 (1.14)

-0

CORNER
LEAD
OPTION

r-

(4 PLACES)

.322 (8.18)

.300 (7.62) (NOTE 5)

.125 (3.18)

~

~
PLANE

.035

J

f,

ii

(.S:i9)
.:

.020 (.51)

Bse
.300 (7.62)
(NOTE 5)

.022 (.56)
.017 (.43)

4iT1 E io@

.010 (.25) @

I

.015 (.38)
.010 (.25)

.395 (10.03)
.300 ( 7.62)

853·0404 81230

I
February 1987

9-47

I

Signetics Linear Products

For Prefixes ADC, AM, CA, DAC, IF, lM,
MC, NE, SA, SE, SG, pA, UlN

Package Outlines

14-PIN PLASTIC DIP (N PACKAGE)
NOTES:
1. Controlling dimension: inches. Metric are shown in
parentheses.
2. Package dimensions conform to JEDEC specification
MS-001-AC for standard dual in-line (DIP) package .300
inch row spacing (PLASTIC) 14 leads (issue B. 7/85)
3. Dimensions and tolerancing per ANSI Y14. 5M-1982.
4. "T", "0" and "E" are reference datums on the molded
body and do not include mold flash or protrusions. Mold
flash or protrusions shall not exceed .010 inch (.25mm)
on any side.
5. These dimensions measured with the leads constrained
to be perpendicular to plane T.
6. Pin numbers start with pin # 1 and continue
counterclockwise to pin #14 when viewed from the top.

.255 (6.46)
.245 (S.22)

PIN#1

~~:,::J.--l

.746 (16.95)
.064 (1.63)
.045 (1.14)

.125 (3.16)

:i15(2.92j
PLANE
~

(.8~9)
II

.035
.020 (.51)

.136 (3.51)

..f+lTIEID®I,010 (.2S) ijl

esc

.015 (.38)

.300 (7.62)
(NOTE 5)
.385 (10.03)

.010 (.25)

.300 ( 7.62)

.120 (3.05)

653·0405 61231

16-PIN PLASTIC DIP (N PACKAGE)
Os

E
-

IN#l

D

.004 .10)

NOTES:
1. Controlling dimension: inches. Metric are shown in
parentheses.
2. Package dimensions conform to JEDEC specification
MS-001-AA for standard dual in-line (DIP) package .300
inch row spacing (PLASTIC) 16 leads (issue B. 7/85)
3. Dimensions and tolerancing per ANSI Y14. 5M-1982.
4. "T", "0" and HE" are reference datums on the molded
body and do not include mold flash or protrusions. Mold
flash or protrusions shall not exceed .010 inch (.25mm)
on any side.
5. These dimensions measured with the leads constrained
to be perpendicular to plane T.
6. Pin numbers start with pin # 1 and continue
counterclockwise to pin #16 when viewed from the top.

.255(6.46)

!brrT':'T"T"T'"T"T"T'TT..,...,..,~~.22)

:,:;~~J

.746 (18.95)
.064 (1.63)

CORNER

LEAD

.322 (6.18)
.300 (7.62)
(NOTE 5)

OPTION

.045 (1.14)

(4 PLACES)

J

.125 (3,18)

:11512.92l

~
PLANE

.136 (3.51)
.120 (3.05)

-liTle!OO)j

010 (.25)

$ I

:~: ~.:J;:~:II
.015 (.38)

.010 (.25)

853·0406 .,232

February 1987

9-48

esc
.300 (7.62)
(NOTE 5)
.395 (10.03)

:3oOi7.62i

~\\

Signetics Linear Products

For Prefixes ADC, AM, CA, DAC, LF, LM,
MC, NE, SA, SE, SG, pA, ULN

Package Outlines

18-PIN PLASTIC DIP (N PACKAGE)
s .004 .10

NOTES:

1. Controlling dimension: inches. Metric are shown in
parentheses.

E
-E

J

2. Package dimensions conform to JEDEC specification
MS-001-AD for standard dual in-line (DIP) package .300
inch row spacing (PLASTIC) 18 leads (issue B. 7/85)
3. Dimensions and tolerancing per ANSI Y14. 5M-1982.
4. "T", "0" and "E" are reference datums on the molded
body and do not include mold flash or protrusions. Mold
flash or protrusions shall not exceed .010 inch (.25mm)
on any side.
5. These dimensions measured with the leads constrained
to be perpendicular to plane T.
6. Pin numbers start with pin # 1 and continue
counterclockwise to pin # 18 when viewed from the top .

.255 (6.48)

!'-r""T"'T""T"''''''1''"T'''''T'''T''''T"'T""T'''''''''T'I~6.22)

PIN#1

EO!B__+ ____ ':~2;:)50~

PLANE
~

JL

.915 (23.24)
.064 (1.63)

.322 (8.18)

.045 (1.14)

.300 (7.62)
(NOTE 5)

8SC
.300 (7.62)

.138 (3.51)

(NOTE 5)

.120 (3.05)

.395 (10.03)

.022 (.56) ...j+JTIEID®J .010 (.25) @I
.017 (.43)

.300 ( 7.62)

853-0407 81233

20-PIN PLASTIC DIP (N PACKAGE)
D

.004

.10
NOTES:

1. Controlling dimension: inches. Metric are shown in
parentheses.
2. Package dimensions conform to JEDEC specification
MS-001-AE for standard dual in-line (DIP) package .300
inch row spacing (PLASTIC) 20 leads (issue 8. 7/85)
3. Dimensions and tolerancing per ANSI Y14. SM-1982.
4. "T", "D" and "E" are reference datums on the molded
body and do not include mold flash or protrusions. Mold
flash or protrusions shall not exceed .010 inch (.2Smm)
on any side.
5. These dimensions measured with the leads constrained
to be perpendicular to plane T.
6. Pin numbers start with pin # 1 and continue
counterclockwise to pin #20 when viewed from the top.

PIN#1

.100 (2.54) SSC

E-QoJ---j------

1.057 (28.85)

~

~
.045 (1.14)

n1----------,~
.160 (4.06)

PLANE
~

sse
.138 (3.51)
.120 (3.05)

-&lTleiD@J! . .Q1o (.25) $1

:3OO(7.62i

853-0408 81234

February 1987

.300 (7.62)
(NOTe 5)
.395 (10.03)

9-49

I

Signetics Linear Products

For Prefixes ADC, AM, CA, DAC, LF, LM,
MC, NE, SA, SE, SG, pA, ULN

Package Outlines

22-PIN PLASTIC DIP (N PACKAGE)
OS .004 (0.10)

NOTES:

1. Controlling dimension: inches. Metric are shown in
parentheses.

I

.355 (9.02)

..L--~"'F:"FT;"F'Ff"T'''Fi'''''-;-FT'''Fl""i'''''F'Ff''T''Fi~ ~(8.
I

LL-.'00 (2.54) BSe
1.110 (28.19)

·0·

1.095 (27.81)

2. Package dimensions conform to JEDEC specification
MS-Ol0~AA for standard dual in·line (DIP) package .400
inch row spacing (PLASTIC) 22 leads (issue A. 7/85)
3. Dimensions and tolsrancing per ANSI Y14. 5M-1982.
4. "T", "0" and "E" afe reference datums on the molded
body and do not include mold flash or protrusions. Mold
flash or protrusions shall not exceed .010 inch (.25mm)
on any side.
5. These dimensions measured with the leads constrained
to be perpendicular to plane T.
6. Pin numbers start with pin #1 and continue
counterclockwise to pin #22 when viewed from the top.

76)

"~]

_

.064 (1.63)
.045 (1.14)

.422 (10.72) _
.400 (10.'!?)

.190 (4.83)

(NOTE 5)

.155 (3.94)

.165 (4.19)

.145 (3 .6_8:..)--+.,,---,.,---,

41

\

\.~

~==t'I.\'--_----'i f,

~:~I ::g8~:!! BSe

.138 (3.51)

.400 (10.16)
(NOTE 5)

.120 (3.05)

-1+1 TIE 1000 .01 0

(.25)

.015 (.38)

@I

_

.010 (.25)

.495 (12.57)

--J.~I

----!

400 (10.16)

853-0409 81235

24-PIN PLASTIC DIP (N PACKAGE)
s .004 .10

NOTES:

I

:J

1. Controlling dimension: inches. Metric are shown in
parentheses.
2. Package dimensions conform to JEDEC specification
MS-011-AA for standard dual in-line (DIP) package .600
inch row spacing (PLASTIC) 24 leads (issue B. 7/85)
3. Dimensions and tolerancing per ANSI Y14. 5M-1982.
4. "T", "0" and "E" are reference datums on the molded
body and do not include mold flash or protrusions. Mold
flash or protrusions shall not exceed .010 inch (.25mm)
on anY,side .
S. These dimensions measured with the leads constrained
to be perpendicular to plane T.
6. Pin numbers start with pin # 1 and continue
counterclockwise to pin #24 when viewed from the top.

555 (14.10)
.545 (13.84)

'~~F'FFl7F'i~

[fpiijIN[40l--+-1lf

~.'00 (2.54) BSC
O[}--+-----~:!:::~:::
.064 (1.63)

.155 (3.94)

.045 (1.14)

145 (3.68)

~

~~O\l:t=~:
'\- ~"~=-I'1

PLANE

.138 (3.51)

(NOTE 5)

.120 (3.05)

-f+ITlEIb: or sign 1

February 1987

9-60

10

8, ) -

Signetics Linear Products

For Prefixes HEF, OM, MEA, PCO, PCF, PNA,
SAA, SAB, SAF, TBA, TCA, TOA, TOO, TEA

Package Outlines

16-PIN PLASTIC DIP WITH INTERNAL HEAT SPREADER (SOT-38WE-2)
_ - -_ _ 22mcx _ _ _ __

",
~I

~I,

/;.1)(

-1°,51

~

i

-=--.!:;~(2~
I'

I
__ ' .0,32

I

I

"~

mOl(

I ___

~~_'

1_ _

~

_ _ _I

;,5 __
8,3

16-PIN PLASTIC QIP (SOT-58)
_----_22mclC

----~

I_~~
I
I_~_I

7

February 1987

9-61

Signetics Linear Products

For Prefixes HEF, OM, MEA, PCD, PCF, PNA,
SAA, SAB, SAF, TBA, TCA, TDA, TDD, TEA

Package Outlines

16-PIN CERDIP (SOT-74A, B, C)
------19,94max------

--t

side view

5,08

max

top view

16-PIN METAL CERDIP (SOT-84B)

_

I
I 0,30

,
~

0,20

;~~:--Iml ~I

top

February 1987

9·62

v,~w

Signetics Linear Products

For Prefixes HEF, OM, MEA, PCO, PCF, PNA,
SAA, SAB, SAF, TBA, TCA, TOA, TOO, TEA

Package Outlines

18-PIN METAL CERDIP (SOT-8S8)
_-----

23.4max-----_

side view

I

- ..La.3D
II 0,20
II

!
'";~~:-~_I

top view

18-PIN PLASTIC DIP (SOT-102A)
I_----_~

23,5mo)( - - - - - - -

side view

I

...... ,Lo,n
II

II
1I

mox

~

i-[Z@_i,

-~~--

top view

(4)

I
February 19B7

9-63

r

Signetics Linear Products

For Prefixes HEF, OM, MEA, PCO, PCF, PNA,
SM, SAB, SAF, TBA, TCA, TOA, TOO, TEA

Package Outlines

18-PIN PLASTIC DIP (SOT-102C)
22molC

-8,25.m'' -1
Iffij

----~

1

"de

".W

I

+~:

1_8.25_1
7,50

top view

18-PIN PLASTIC DIP (SOT-102CS)
22mQx

----~

side view

II
"

I
I

!

'3,4.9

I .

-

~:

O.85~

~~~:

\j

y

. ;_ _.,_
1___1_1

j

';--~-_;i

1~9.5_1

mQ'

8.'

top "iew

February 1987

9-64

Signetics Linear Products

For Prefixes HEF, OM, MEA, PCD, PCF, PNA,
SAA, SAB, SAF, TBA, TCA, TDA, TOO, TEA

Package Outlines

18-PIN PLASTIC DIP (SOT-102G)
_ - - - - - 25.4mc)( - - - - - _

side "jew

_[mJ_i,

)-~:~-

top view

18-PIN CERDIP (SOT-133A, B)
, - - - - - - - 23,6max - - - - - _

- S , 2 5 max-I

--t

1

5,08

max

#

'O.~8 I

---, min ,
076(21

_.=.J

t -

1
1

I,

.. ~ 0,32
, :1 0,23

I
I.

t ---------666
~6 (5 2)

.

.

;

~

I

:'
"

1,1,

-u
1.27 __
mex

.

side view

[7,62]
10,0

7,6

J

.

top view

66

i

I
February 1987

9-65

Signetics Linear Products

For Prefixes HEF, OM, MEA, PCO, PCF, PNA,
SM, SAS, SAF, TBA, TCA, TOA, TOO, TEA

Package Outlines

20-PIN PLASTIC DIP (SOT-146)
~-------

2111\CX ------~~I
side view

20-PIN CERDIP (SOT-152B, C)

1-,'------- 2 5 , 4 m a x - - - - - - - - ,_ __

-8,25

max-, . .
stde view

t

max

5,08

I

3,4
2,9
I

'

(:

,

032
1+-:,' 0:23

":,1

i-lilll-f ,

1,27_

_ _ _ 10,0 _ _ _

max

7,6

top view

February 1987

~

9-66

Signetics Linear Products

For Prefixes HEF, OM, MEA, PCO, PCF, PNA,
SM, SAB, SAF, TBA, TCA, TOA, TOO, TEA

Package Outlines

20-PIN METAL CERDIP (SOT-154B)
2S.8mox - - - - - - - side view

top view

20-PINPLASTIC DIP (SOT-116)
,-.---------------

29~K-________

II:: I
.-.

side view
5.1

-f"
I '.36

3.43

3·L
I

I

I

..•

;

mex

,
•.•

~

•..•

... lm~xi--I-I-'-I-I-j--l-l-l-1

---~----;
11,17

top

February 1987

9-67

I

•_ _ _ _ _ 12.45 _ _ _ _ _ 1

IIU~W

Signetics Linear Products

For Prefixes HEF, OM, MEA, PCD, PCF, PNA,
SM, SAB, SAF, TBA, TCA, TDA, TOO, TEA

Package Outlines

22-PIN METAL CERDIP (SOT-118B)
r----------

-'O,9ma, ~

28,Oma,

j1- 10.05 max : : : { /

------~-.!

side view

0,30

0,20

top view

T~·~~·~~·I·-·-·--·-·

22-PIN CERDIP (SOT-134A)
,---------21,94max - - - - - - - _
side view

5,08

::'-_......,.....-I

,I

II
,

~

~

O--;~15J- rrml_1

top view

February 1987

9-68

Signetics Linear Products

For Prefixes HEF, OM, MEA, PCD, PCF, PNA,

Package Outlines

SAA, SAB, SAF, TBA, TCA, TDA, TDD, TEA
24·PIN METAL CERDIP (SOT·S6A)
,_ _ _ _ _ _ _

__

31,OOrM.~-----_

t..I i

mvnvnn~~e:
~~~

t

-~~

24·PIN CERDIP (SOT-94)
r--------- """"--------

February 1987

9·69

lZ.g0m~

Signetics Linear Products

For Prefixes HEF, OM, MEA, PCO, PCF, PNA,
SAA, SAB, SAF, TBA, TCA, TOA, TOO, TEA

Package Outlines

24-PIN PLASTIC DIP WITH INTERNAL HEAT SPREADER (SOT-101A, B)

F-:~:::-I

,-------12rnox - - - - - - _

side "jew

I
, '----+------'

i
I

"

0,32

m..

~--­

,---tOIl

~i:~~ - - - -

~,.w

(4)

28-PIN METAL CERDIP (SOT-87A)

I

j

I

36,OOmCl"

r~ VVVVVVVHV H~~
_I~i-

February 1987

__ ,~I_

9-70

,

,

I

II

~O.lO

,

-.

15

0,>0

~

i

1_ _ _ ~ _ _ _.1

me"

Signetics linear Products

For Prefixes HEF, OM, MEA, PCO, PCF, PNA,
SAA, SAB, SAF, TBA, TCA, TOA, TOO, TEA

Package Outlines

28-PIN METAL CERDIP (SOT-87B)
-------

36me, - - - - - - _

"'-~
~-g:;g
~
I~~

l(ii"~21M2~6g-"~r~2"~20d'~1

TO'-T.'-"~,, ",p

.ii'--".

rl
1

2

J

I..

5

6

1

8

9

10

l'

12

13

_ _ _'

';0.

14

28-PIN PLASTIC DIP (SOT-117)
, - - - - - - - - 36mQx - - - - - -_ _

sid. vi.w

'---

i~:~~---

top ..... w

(4 )

I
February 1987

9-71

Signetics Linear Products

For Prefixes HEF, OM, MEA, PCD, PCF, PNA,
SAA, SAB, SAF, TBA, TCA, TDA, TDD, TEA

Package Outlines

28-PIN PLASTIC DIP (SOT-117D)

'----IlillI----

,----- :~:~~ - - - -

28-PIN CERDIP (SOT-135A)
38,11\'lQX - - -_ _ _ _ _ _- ,

side! view

;to

'5 ..i- - - -

~

----,

P001400$

February 1987

9·72

Signetics Linear Products

For Prefixes HEF, OM, MEA, PCO, PCF, PNA,
SAA, SAB, SAF, TBA, TCA, TOA, TOO, TEA

Package Outlines

40-PIN METAL CERDIP (SOT-SS)

- - - - - - - - - - - - - "_"'.0' - - - - - - -______

r-'2.9C",Q·~1

40-PIN METAL CERDIP (SOT-SSB)

I_ _ _

U

39

~

31

36

35

34

33

32

31

21

26

25

24

23

22

~

-~------------t--------- r----------

16

17

HI

19

top

21

~_-_I

~i.w

r--

20

I
February 1987

9-73

Signetics Linear Products

For Prefixes HEF, OM, MEA, PCO, PCF, PNA,
SAA, SAB, SAF, TBA, TCA, TOA, TOO, TEA

Package Outlines

40-PIN PLASTIC DIP (SOT-129)
IO;,a",o,o _ __

j
,~.

I

u

?

~

!.

::;-t
~:r;; !

.

.

,

-

~5i_

-

-

,~I

.

• ...

.'. 38~ .
,

.::;:;;,~,

..

I

,

1

:

0.53 __

_, [gj '-

mt;. . . .

I

I
1107~

-

.'C.1S4

m

(4)

40-PIN CERDIP (SOT-14S)

::

'--------'--'---~ "
.... ,.1; 032

I
::

[_0_."__ rrm-:: ___
'--'--- :~:~b ---"--'

February 1987

9-74

Signetlcs Linear Products

For Prefixes HEF, OM, MEA, PCO, PCF, PNA,
SAA, SAB, SAF, TBA, TCA, TOA, TOO, TEA

Package Outlines

8-PIN PLASTIC SO (D PACKAGE) (50-8, SOT-96A)
NOTES:

D@ .10 (.004)

1. Package dimensions conform to JEDEC specification
MS-012-AA for standard small outline (SO) package, 8
leads, 3.75mm (.150") body width (issue A, June 1985).
2. Controlling dimensions are in mm. Inch dimensions in
parentheses.

3, Dimensions and tolerancing per ANSI Y14.5M- 1982.
4. "T", "0" and "E" are reference datums on the molded
body and do not include mold flash or protrusions. Mold
flash or protrusions shall not exceed .15mm (.006") on
any side.
5. Pin numbers start with pin #1 and continue
counterclockwise to pin #8 when viewed from top.
6. Signetics ordering code for a product packaged in a
plastic small outline (SO) package is the suffix Dafter
the product number.

-+----1-1.27 (.050)

esc

r

I

19 .10 (.004) I
l . 4 9 (.019)
.35 (.014)

-1-+ITlelo@1

.25 (.010)
80

~E~

(.051> .008)
~

m

.50 (.020) <45 0

.25 (.010) ~

I

I

.25 (.010)
.19 (.007)

(.025 •.005)
.635:1:.15

(.007 •.000)
.180 •.07

853-0174 8e070

8-PIN PLASTIC SO (VSO-8, SOT-176)
1

_ ',.0 _
105"

, - - 9,0 max - - ,

7,6max-1

1

~

min

0)5t~2'35
max
. . .I

:

.0,49:

1'1

-,

27
'
max

.o,3~i '1~"'lo" CEll

_I ~;,~ 1-I

7,6 max - - I

1,1

,;i{1j :::; -

t

-"'lt~.o,'5
~ 1,7).__
min

!15

:

I

~

'I

0,22
0,15

- - - - 12,4 max - - - -

~

top view

1--'-,
40 2,0 .

i

max I

,__1_'

_ _ 8,0 max

February 1987

I

-_I

9-75

Signetics Linear Products

For Prefixes HEF, OM, MEA, PCO, PCF,PNA,
SAA, SAB, SAF, TBA, TCA, TOA, TOO, TEA

Package Outlines

14-PIN PLASTIC SO (0 PACKAGE) (50-14, SOT-108A)
o®

NOTES:
1. Package dimensions conform to JEDEC specification
MS~012-AB for standard small outline (SO) package, 14

.'0 (.004)

leads, 3.7Smm (.150") body width (issue A, June 1985).
2. Controlling dimensions are in mm. Inch dimensions in

parentheses.
3. Dimensions and tolerancing per ANSI Y14.SM- 1982.

4. "T", "0" and "E" are reference datums on the molded

(.236 •.006)
---e;:15

body and do not include mold flash or protrusions. Mold
flash or protrusions shall not exceed .15mm (.006") on

any side.
5. Pin numbers start with pin # 1 and continue
counterclockwise to pin # 14 when viewed from top.
6. Signetics ordering code for a product packaged in a
plastic small outline (SO) package is the suffix 0 after
the product number.

r

L-~~

(.06' •.008)
~

m

!¢>I.,o (.004)
.49 (.0'9)
.35 (.0'4)

.,..-1

.50 (.020) x45'
.25 (.0'0)
8'

I

TI.e .
10®1
.

.25 (.010) @ 1
.

.25 (.0'0)
.'9 (.007)

16-PIN PLASTIC SO (0 PACKAGE) (50-16, SOT-109A)
~O®I.'O

(.004)

~

NOTES:
1. Package dimensions conform to JEOEC specification

----.-1

i

MS-012·AC for standard small outline (SO) package, 16
leads, 3.7Smm (.150") body width (issue A, June 1985).
2. Controlling dimensions are in mm. Inch dimensions in
parentheses.
3. Dimensions and tolerancing per ANSI Y14.5M-1982.
4. "T", "0" and "E" are reference datums on the molded
body and do not include mold flash or protrusions. Mold
flash or protrusions shall not exceed .15mm (.006") on
any side.
5. Pin numbers start with pin # 1 and continue
counterclockwise to pin # 16 when viewed from top.
6. Signetics ordering code for a product packaged in a
plastic small outline (SO) package is the suffix 0 after
the product number.

,;,1_

(.236 •.006)

--,-;:;s

1.le®I.25 (.0'0) ® 1

Iii

PIN#,

.
~

',.27 (.050)

-0-

RJ

B·'o (.004.1..1

esc

'0.00 (.394)
---9.80 (.386)

----1

Lr-~~~~~~~~::\
fh...,
M M H hH H H

fL-

--J

-~-

.49 (.0'9)
.35 (.0'4)

(.06' •.008)
1.55 • .20

~

,..-1 T 1e 10®1 .25

(.~'iL.1iJ

r

8'

~~~J1

I

.25 (.0'0)
.'9(.007)

853-0005 88069

February 1987

.50 (.020) x45'
.25 (.0'0)

9-76

(.007 ••003)

(.025 ± .008)

~

.635:t.15

Signetics Linear Products

For Prefixes HEF, OM, MEA, PCD, PCF, PNA,
SAA, SAB, SAF, TBA, TCA, TDA, TDD, TEA

Package Outlines

16-PIN PLASTIC SOL (0 PACKAGE) (SOL-16, SOT-162A)
~O®I.'0

(.004)

~

NOTES:
1. Package dimensions conform to JEDEC specification
MS-013-AA for standard small outline (SO) package, 16
leads, 7.50mm (.300") body width (issue A, June 1985),
2. Controlling dimensions are in mm. Inch dimensions in

I

parentheses.
3. Dimensions and tolerancing per ANSI Y14.5M-1982.
4. "T", "0" and "E" are reference datums on the molded
body and do not include mold flash or protrusions. Mold
flash or protrusions shall not exceed .15mm (.006") on
any side.
5. Pin numbers start with pin # 1 and continue
counterclockwise to pin # 16 when viewed from top.
6. Signetics ordering code for a product packaged in a
plastic small outline (SO) package is the suffix 0 after
the product number.

7.40 (.291)

I

tB

!

r

U,.27 (.050) esc

-O-r-----+------ ;~:~~;~~

.75 (.030) X45°
.50 (.020)

i

I

2.65 (.104)

m

I

1¢>I.10 (.004) I

~

L

2.35 (.093)

!

.49 (.019) -H.IT I Elo®1 .25 (.010) @.I
.35 (.014)

.23 (.009)

.30 (.012)

1.07 (.042)

.10 (.004)

0.86 (.034)

853-0171 81218

20-PIN PLASTIC SOL (0 PACKAGE) (SOL-20, SOT-163A)
1+lo®I.1O (.004) I

NOTES:

11

10.65 (.419)
10.26 (.404)

7.40 (.291)

!.:E®~ .25 (.010)

I

m
I

®

I

1. Package dimensions conform to JEDEC specification
MS·013·AC for standard small outline (SO) package, 20
leads, 7.50mm (.300") body width (issue A, June 1985).
2. Controlling dimensions are in mm. Inch dimensions in
parentheses.
3. Dimensions and tolerancing per ANSI Y14.5M·1982.
4. "T", "0" and "E" are reference datums on the molded
body and do not include mold flash or protrusions. Mold
flash or protrusions shall not exceed ,15mm (.006") on
any side.
5. Pin numbers start with pin # 1 and continue
counterclockwise to pin #20 when viewed from top.
6. Signetics ordering code for a product packaged in a
plastic small outline (SO) package is the suffix 0 after
the product number.

lr

13.00 (.512)
12.60 (.496)

·75 (.030) X45°
.50 (.020)

~

t

2.65 (.104)

L

I
---l

19.10 (.004) I

:::::~:::

'.!T1eio®I.25(.010)@

.23 (.009)

853-0172 82948

February 1987

80

2.35 (.093)
t

9-77

.30 (.012)

1.07 (.042)

.10 (.004)

.86 (.034)

I

I

Signetics Linear Products

For Prefixes HEF, OM, MEA, PCD, PCF, PNA,
SAA, SAB,SAF, TBA, TCA, TDA, TDD, TEA

Package Outlines

24-PIN PLASTIC SOL (0 PACKAGE) (SOL-24, SOT-137A)
O® .10 (.004)

NOTES:
1. Package dimensions conform to JEDEC specification
MS·013-AD for standard small outline (SO) package, 24
leads, 7.50mm (.300") body width (issue A, June 1985).
2. Controlling dimensions are in mm. Inch dimensions in

11

parentheses.

3. Dimensions and tolerancing per ANSI Y14.5M-1982.
4. lOT", "0" and "E" are reference datums on the molded
body and do not include mold flash or protrusions. Mold
flash or protrusions shall not exceed .1Smm (.006") on
any side.
S. Pin numbers start with pin #1 and continue
counterclockwise to pin #24 when viewed from top.
6. Signetics ordering code for a product packaged in a
plastic small outline (SO) package is the suffix Dafter
the product number.

10.65 (.419)
10.26 (.404)

7.40 (.291)

I+IE@I.25 (.010) @

1

m

I

I

"O"~--~~---------

r·

15.60 (.614)
15.20 (.598)

75 (.030) X45'
.50 (.020)

I

\91

.10 (.004)

I
----.J

I

2.65 (.104)

L

2.35 (.093)
I

::: ~:~::: -1.1 TIE 10@1

.25 (.010) @

!

.32 (.013)

.30 (.012)

1.07 (.042)

.23 (.009)

.10 (.004)

.86 (.034)

853-0173 82949

28-PIN PLASTIC SOL (0 PACKAGE) (SOL-28, SOT-136A)
lijiI0®1·10 (.004)

I

NOTES:
1. Package dimensions conform to JEDEC specification
MS·013·AE for standard small outline (SO) package, 28
leads, 7.50mm (.300") body width (issue A, June 1985).
2. Controlling dimensions are in mm. Inch dimensions in
parentheses.
3. Dimensions and tolerancing per ANSI YI4.SM·1982.
4. "T", "D" and "E" are reference datums on the molded
body and do not include mold flash or protrusions. Mold
flash or protrusions shall not exceed .15mm (.006") on
any side.
5. Pin numbers start with pin # 1 and continue
counterclockwise to pin #28 when viewed from top.
6. Signetjes ordering code for a product packaged in a
plastic small outline (SO) package is the suffix Dafter
the product number.

7.60 (.299)
7.40 (.291)

r·

U,.27 (.050) SSC

"O"~----~------------

18.10 (.713)
17.70 (.697)

75 (.030) X45'

.50 (.020)

t

I
---I

© .10 (.004) I

2.65 (.104)
2.35 (.093)

L

::: ::~:::

I

853·0006 81217

February 1987

t=~'--------'
.32 (.013)
.23 (.009)

-i.IT!EI0@!25(.010)® !

9-78

.30 (.012)
.10 (.004)

1.07 (.042)
.86 (.034)

8'

-Fl-==:!::

Signetics Linear Products

For Prefixes HEF, OM, MEA, PCD, PCF, PNA,
SAA, SAB, SAF, TBA, TCA, TDA, TOO, TEA

Package Outlines

40-PIN PLASTIC SO (VSO-40, SOT-158A)

-I 1.1.I--s.oma'--I
r--I
rr?ii9-\ ,__ ~
~c~

7,6mox---1

'I

~--I~+I

_'.71~

-

LJ

+

t O,!5

1,5

~--

0.22/
0,15

m,n
12,3

mQX

________ 1

top view

~-- 16,0 max

___

I

40-PIN PLASTIC SO (OPPOSITE BENT LEADS) (VSO-40, SOT-158B)

-I ~a4, 1-.. o,~5

1--9 0

_I~

1s.sma'--1

, mml
~:~~_~'.
-t

--

.

7·

,
-!1~7
. 1. max max
1

__

-,-,

g.~~

7

0.45ma,

.4~IO"@i

max

11

, maxi

max--I

7.5 ma'-I

1rl9 ,m~b
_'I"S71~
1.

MI

0.22
1°,15

- - - 1 2 , 3 m a x - - -1

@mj

~
-F:-:-

__

40

:!
12~1.;'
I
I

I

~:I:~~
21

top vIew

I

maUx

,

,_1_,

I: -== -- - : - "
1_ _-

I

I

15.0ma, _ _ _ I

II
February 1967

9-79

Signetics

Section 10
Sales Offices

Linear Products

INDEX
Sales Office Listing..................................................................................

10-3

I
I

I

Signetics Linear Products

Sales Offices

SIGNETICS
HEADQUARTERS
811 East Arques Avenue
P.O. Box 3409
Sunnyvale,
California 94088-3409
Phone: (408) 991-2000
ALABAMA
Huntsville
Phone: (205) 830-4001
ARIZONA
Phoenix
Phone: (602) 265-4444
CALIFORNIA
Canoga Park
Phone: (818) 340-1431
Irvine
Phone: (714) 833-8980
(213) 588-3281
Los Angeles
Phone: (213) 670-1101
San Diego
Phone: (619) 560-0242
Sunnyvale
'"'t~, ,~.-.
Phone: (408) 991-3737
COLORADO
Aurora
Phone: (303) 751-5011
FLORIDA
Clearwater
Phone: (813) 796-7086
Ft. Lauderdale
Phone: (305) 486-6300
GEORGIA
Atlanta
Phone: (404) 953·0067
ILLINOIS
Itasca
Phone: (312) 250-0050
INDIANA
Kokomo
Phone: (317) 453-6462
KANSAS
Overland Park
Phone: (913) 469-4005
MASSACHUSETTS
Littleton
Phone: (617) 486-8411
MICHIGAN
Farmington Hills
Phone: (313) 476-1610
MINNESOTA
Edina
Phone: (612) 835-7455

February 1987

NEW JERSEY
Parsippany
Phone: (201) 334-4405
NEW YORK
Hauppauge
Phone: (516) 348-7877
Wappingers Falls
Phone: (914) 297-4074
NORTH CAROLINA
Cary
Phone: (919) 481-0400
OHIO
Worthington
Phone: (614) 888-7143
OREGON
Portland
Phone: (503) 297-5592
PENNSYLVANIA
Plymouth Meeting
Phone: (215) 825-4404
TENNESSEE
Greeneville
Phone: (615) 639-0251
TEXAS
Austin
Phone: (512) 339-9944
Richardson
Phone: (214) 644-3500
CANADA
SIGNETICS CANADA, LTD.
Etoblcoke, Ontario
Phone: (416) 626-6676
Nepean, Ontario
Signetics, Canada, Ltd.
Phone: (613) 726-9576

REPRESENTATIVES
ARIZONA
Scottsdale
Thom Luke Sales, Inc.
Phone: (602) 941-1901
CALIFORNIA
Santa Clara
Magna Sales
Phone: (408) 727-8753
CONNECTICUT
Brookfield
M & M Associates
Phone: (203) 775-6888
FLORIDA
Clearwater
Sigma Technical Associates
Phone: (813) 791-0271
Ft. Lauderdale
Sigma Technical Associates
Phone: (305) 731-5995

ILLINOIS
Hoffman Estates
Micro-Tex, Inc.
Phone: (312) 382-3001

PENNSYLVANIA
Pittsburgh
Covert & Newman
Phone: (412) 531-2002

INDIANA
Indianapolis
Mohrfield Marketing Inc.
Phone: (317) 546-6969

Willow Grove
Delta Technical Sales Inc.
Phone: (215) 657-7250

MARYLAND
Glen Burnie
Third Wave Solutions, Inc.
Phone: (301) 787-0220
MASSACHUSETTS
Needham Heights
Com-Sales, Inc.
Phone: (617) 444-8071
Kanan Associates
Phone: (617) 449-7400
MICHIGAN
Bloomfield Hills
Enco Marketing
Phone: (313) 642-0203
MINNESOTA
Eden Prairie
High Technology Sales
Phone: (612) 944-7274
NEW JERSEY
East Hanover
Emtec Sales, Inc.
Phone: (201) 428-0600
NEW MEXICO
Albuquerque
F.P. Sales
Phone: (505) 345-5553
NEW YORK
Ithaca
Bob Dean, Inc.
Phone: (607) 257-1111
OHIO
Cleveland
Covert & Newman
Phone: (216) 663-3331
Dayton
Covert & Newman
Phone: (513) 439-5788
Worthington
Covert & Newman
Phone: (614) 888-2442
OKLAHOMA
Tulsa
Jerry Robinson and
Associates
Phone: (918) 665-3562
OREGON
Hillsboro
Western Technical Sales
Phone: (503) 640-4621

10-3

TEXAS
Houston
OM Sales
Phone: (713) 789-4426
UTAH
Salt Lake City
Electrodyne
Phone: (801) 486-3801
WASHINGTON
Bellevue
Western Technical Sales
Phone: (206) 641-3900
Spokane
Western Technical Sales
Phone: (509) 922-7600
WISCONSIN
Waukesha
Micro-Tex, Inc.
Phone: (414) 542-5352
CANADA
Burnaby, British Columbia
Tech-Trek, Ltd.
Phone: (604) 439-1367
Mississauga, Ontario
Tech-Trek, Ltd.
Phone: (416) 238-0366
Nepean, Ontario
Tech-Trek, Ltd.
Phone: (613) 726-9562
Richmond, British Columbia
Tech-Trek, Ltd.
Phone: (604) 271-3149
Ville SI. Laurent, Quebec
Tech-Trek, Ltd.
Phone: (514) 337-7540

DISTRIBUTORS
Contact one of our
local distributors:
Anthem Electronics
Arrow Electronics
Avnet Electronics
Hamilton/ Avnet Electronics
Lionex Corporation
Schweber Electronics
Summit Distributors
Quality Components
Wyle LEMG
Zentronics, Ltd.
I

II

Signetics Linear Products

Sales Offices

FOR SIGNETICS
PRODUCTS
WORLDWIDE:
ARGENTINA
Philips Argentina S.A.
Buenos Aires
Phone: 54·1-541·7141
AUSTRALIA
Philips Electronic
Components and Materials,
Ltd.
Artarmon, N.S.W.
Phone: 61-2-439-3322
AUSTRIA
Osterrichische Philips
Bauelemente
Wien
Phone: 43-222-62-91-11
BELGIUM
N.V. Philips & MBLE
Bruxelles
Phone: 32-2-5-23-00-00
BRAZIL
Philips Do Brasil, Ltda.
Sao Paulo
Phone: 55-11-211-2600
CHILE
Philips Chilena S.A.
Santiago
Phone: 56-02-077-3816
COLOMBIA
Iprelenso, Ltda.
Bogota
Phone: 57-1-2497624
DENMARK
Mlnlwatt AlS
Copenhagen S
Phone: 45-1-54-11-33
FINLAND
Oy Philips Ab
Helsinki
Phone: 358-0-172-71

FRANCE
R.T.C. La RadiotechniqueCompelec
Paris
Phone: 33-1-43-38-80-00

KOREA
Philips Industries, Ltd.
Seoul
Phone: 82-2-794-5011/2/3
14/5

GERMANY
Valvo
Hamburg
Phone: 49·40·3-296-1

MEXICO
Electronlca S.A. de C.V.
Toluca
Phone: (721) 613-00

GREECE
Philips Hellenique S.A.
Athens
Phone: 30-1-9-21-5111

NETHERLANDS
Philips Nederland B.V.
Eindhoven
Phone: 31-40-793-333

HONG KONG
Philips Hong Kong, Ltd.
Kwai Chung
Phone: 852-0-245-121

NEW ZEALAND
Philips New Zealand Ltd.
Auckland
Phone: 64·9-605914

INDIA
Peico Electronics & Elect.
Ltd.
Bombay
Phone: 91-22-493-8721

NORWAY
Norsk A/S Philips
Oslo
Phone: 47-2-68-02-00

INDONESIA
P.T. Philips-Ralin Electronics
Jakarta Selatan
Phone: 62-21-512-572
IRELAND
Philips Electrical Ltd.
Dublin
Phone: 353-1-69-33-55
ISRAEL
Rapac Electronics, Ltd.
Tel Aviv
Phone: 972-3-477115
ITALY
Philips S.p.A.
Milano
Phone: 39-2-67-52-1
JAPAN
Nlkon Philips Corp.
Tokyo
Phone: 81-3-448-5617
Signetlcs Japan Ltd.
Phone: 81-3-230-1521/2

PERU
Cadesa
Lima
Phone: 51-14-319253
PHILIPPINES
Philips Industrial Dev., Inc.
Makati
Phone: 63-2-868951-9
PORTUGAL
Philips Portuguesa SARL
Lisbon
Phone: 351-1-65-71-85
SINGAPORE
Philips Project Dev. Pte., Ltd.
Singapore
Phone: 65-350-2000
SOUTH AFRICA
E.D.A.C. (PTY), Ltd.
Joubert Park
Phone: 27-11-402-4600

Effective 2-24-87

February 1987

10-4

SPAIN
Miniwatt S.A.
Barcelona
Phone: 34-3-301-63-12
SWEDEN
Philips Komponenter A.B.
Stockholm
Phone: 46-8-782-10-00
SWITZERLAND
Philips A.G.
Zurich
Phone: 41·1-488-2211
TAIWAN
Philips Taiwan, Ltd.
Taipei
Phone: 886-2-712-0500
THAILAND
Philips Electrical Co.
of Thailand Ltd.
Bangkok
Phone: 66-2-233-6330-9
TURKEY
Turk Philips
Tlcaret A.S.
Istanbul
Phone: 90-11-43-59-10
UNITED KINGDOM
Mullard, Ltd.
London
Phone: 44-1-580-6633
UNITED STATES
Signetlcs International Corp.
Sunnyvale, California
Phone: (408) 991-2000
URUGUAY
Luzllectron, S.A.
Montevideo
Phone: 598-91-56-41/42
143/44
VENEZUELA
Magnetica, S.A.
Caracas
Phone: 58-2-241-7509

Signetics
a sub sidiary of U.S. Philips Cofporotion
Signeftcs Cofporotion
811 E. Arques Avenue
PO. Box 3409
Sunnyvale, California 94088-3409
Telephone 408 1991-2000

© Copyright
98-2000-000

1987 Signetics Corporation
Printed in USA6132/ RRD / 60MFP0487
1136 pages



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