298 139_Double_Density_Disc_Controller_System_Manual_1979 139 Double Density Disc Controller System Manual 1979
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298-139_Double_Density_Disc_Controller_System_Manual_1979 298-139_Double_Density_Disc_Controller_System_Manual_1979
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DOUBL.E DENSITY
DISC CONTROLLER
SYSTEM MANUAL
298-139
THE DIGITAL GROUP
DOUBLE DENSITY DISC CONTROLLER SYSTEM MANUAL
(C) 1979 BY
THE DIGITAL GROUP
"Reproduction in any part or form of the contents of this
document or its accompanying cassette tape or disk, except
for the personal use of the original purchaser, is strictly
forbidden without the expressed written consent and
permission of The Digital Group, Inc."
TABLE OF CONTENTS
Section
Page
CHAPTER 1
CHAPTER
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
INTRODUCTION ..•....•••••..•••••...•.........•..•..••.....•.•
2 ASSEMBLING THE CONTROLLER •••••.•.••••...•...••••..••...•••.•
INTRODUCTION... ..•...•... .•••..••.•.... .•. ••.•.•. •.•. .•.. .•••••
PRELIMINARY INSPECTION .••.•••••••...•....•.•..•.•••••...••••...
RESISTOR INSTALLATION ...••••••••..•..•••.•.•••••...•...•.•••.•.
INTEGRATED CIRCUIT SOCKET INSTALLATION •....•...•..•.......•...•
CAPACITOR INSTALLATION ....••.••.•...•...••••......•..•••..••...
REMAINING COMPONENT INSTALLATION ....•....•.•...•••.....•.••••.•
BOARD ADDRESS JUMPER INSTALLATION .••.••.•..•...•••...•........•
HEAD LOAD MOTOR-ON JUMPER ••••.•••....••.•••••...•..••.•...••.•.
FINAL INSPECTION AND CLEANING •••....•.•.•..•..•••••....•.••.•.•
CHAPTER 3
TESTING/TROUBLESHOOTING ••.•••....•.•.••••...•••••..••..•..••
2
2
2
3
4
6
7
8
8
9
10
3.1
INTRODUCTION
••..•.•••••••••••.•••.•...•.••.•.•.•••.....•..••••.
10
3.2
3.3
3.4
3.5
3.6
3.7
3.8
GENERAL- POWER SUPPLIES AND CAPACITORS .••••.....•••.•..•..•.••
THE POWER-ON RESET AND LOW VOLTAGE CIRCUIT .•••.••.••..••..•....
USING HMON/2 FOR TESTING •.•...•••••.•••••••••.••.•••..•.••..•..
BOARD SELECT AND GATING CIRCUITS •...••.•••.••••••••..•...••..•.
DEVICE ATTRIBUTE, VCO AND CLOCK CIRCUITS •••••.••.•••..•.•••••..
TIMING ELEMENT AND DISC I/O BUFFER CIRCUITS .•••.••••.•..•••..••
BRINGING UP THE 1791 IC ••••••••••••.••.••••••••••••..•.•••...•.
10
10
12
12
14
16
20
CHAPTER 4
THEORY OF OPERATION .•••••..•••••••••..•••.•••••••..•••••.•.•
26
4.1
INTRODUCTION...................................................
26
4.2
4.3
4.4
PORT LABEL DEFINITIONS .•••.••••••••.•••••••..••••••....••..•••.
POrIER-ON RESET AND LOW VOLTAGE CIRCUIT •.•••.•••.•.••••.••....••
ADDRESS DECODE AND CPU I/O BUFFERS ••••.••••.••.••••..•.•.•.•.•.
26
27
28
4.5
WAIT LOGIC • . . • . . . • • . • . . . • . • • . . • • • . . • • . . . • • . . . • . . . . . . . . . . . . . • . • .
SEL PORT LOGIC ••••••••••••••••••••••••••••••••••••••••••.••••••
30
4.7 WRITE PRECOMPENSATION CIRCUIT •••.•••....••••..••.•.••.•••..••••
4.8 DELAY AND READY LOGIC •••••••••••..•..••.••.•.•••••••••.•.••••••
4.9 CONTROLLER CLOCK CIRCUIT ••••.•••••••••.•••••.•••.••••••••••..•.
4.10 VCO PHASE LOCKED LOOP •••••.••••.•.•••••••••.••••••.••.•••••.•.
4. 11 DISC I/O BUFFERING •••.•••.•.•••••....•.•••.•.•.••••.••.••...••
35
36
38
39
42
4.6
4. 12
POWER SUPPLIES
4.13
INTERRUPTS
32
••••••••••••••••••••••••••••••••••••••••••••••••
44
.•••.•••••.•.••••••••••••••.•••••••••••••.••••••••••
45
CHAPTER 5 1791 PRODUCT SPECIFICATION ••••••••..••••••••.•••••..••••••••
5.1 INTRODUCTION TO WD1791 PRODUCT SPECIFICATION...................
5.2 1791 PRODUCT SPECIFICATION ••.••••••••••••••••••••••••.••.••••••
46
46
49
CHAPTER 6 SAMPLE DRIVER PROGRAM ••••.•••••••..•.•••..•....•.•••.••••••.
6. 1 INTRODUCTION. • . • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •
6.2 SAMPLE DRIVER CODE ••••••••.••••••••.••••••.•••••.••••••.•••••••
50
CHAPTER 7
SAMPLE FORMAT PROGRAM ••••.••••••.•••••••.••••••••..••••.••••
60
INTRODUCTION ••••.••••••••••••••••••••••••••••••••••••••••••••••
F 0 BM ATe 0 DE. • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •
60
7.1
7•2
-
i
-
50
51
60
TABLE OF CONTENTS
Section
Page
APPENDIX A
PARTS LIST BY VALUE
APPENDIX B
PARTS LIST BY LABEL
· ...................................... .
69
APPENDIX C
DRIVE ATTRIBUTE SOCKET DEFINITION •••..••••••.•••.•••.•••••.
72
APPENDIX D
BOARD ADDRESSING
...........................................
73
APPENDIX E
ONE SHOT TIMINGS
74
APPENDIX F
WRITE PRECOMPENSATION TIMING DIAGRAM.......................
75
APPENDIX G
WAIT LOGIC TIMING DIAGRAM .••.•......•..•.•.•..•...•...•.••.
76
APPENDIX H
SCHEMATIC •....•..••...•..••••••••••....••••.••••••.••.••.••
77
APPENDIX I
PARTS PLACEMENT DIAGRAM ......•.......••.•••.•..••••......••
78
APPENDIX
SOFTWARE COMPATIBILITY (OLD VS NEW) ••...•••••.••••••••.•.••
79
APPENDIX K
APPLICATION NOTE #1
80
APPENDIX L
APPLICATION NOTE #2
81
J
APPENDIX M APPLICATION NOTE #3
6t
'5 /.-P1;/~/ ilJ }. fhyflt1:J/ IJn:1'J
· ......................................
.
/11411-i /IP!e f) /(,eifr;
· ......................................
.
e
!JYIV-G
· ......................................
.
,
us/ft.,
If
· ......................................
.
111.'2"7 '111hz..
·)...,
......................................
.
15
APPENDIX N
APPLICATION NOTE #4
APPENDIX 0
APPLICATION NOTE #5
APPENDIX P
APPLICATION NOTE #6
APPENDIX Q
APPLICATION NOTE #7
APPENDIX R
APPLICATION NOTE #8 • !'(.;~~i.L. ':;77.
APPENDIX S
APPLICATION NOTE #9
A-tfvllt,~f.c. Ol(/~/
"""te)""19 dot+ T1'1!11.~ p1~
tJVlvt'f
~ ~~~!~ .................. .
82
83
84
85
86
87
88
I
APPENDIX T
J:.VlI#f.QVqc tJVtl/~J
APPLICATION NOTE '10 . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
-
ii -
90
CHAPTER 1:
DOUBLE DENSITY SYSTEM MANUAL
INTRODUCTION
CHAPTER 1
INTRODUCTION
The DIGITAL GROUP DOUBLE DENSITY CONTROLLER MANUAL is a comprehensive set
of documentation that
allows the user to Assemble,
Test, Troubleshoot, and
Install the
Board
in
his
system.
Each section of
the manual contains
ordered concise instructions for getting the user up fast and reliably.
An Installation Manual
assembled.
All
he
needs
getting the board up_
is included
for the
user who bought the board
to
do
is consult
the
Installation Manual for
For the
kit
builder, the
Assembly and
Testing
sections are provided.
Along with the Installation Manual, the kit builder will find the Controller
board easy to build.
Also included
in the
documentation is
the
Hardware Monitor Manual and
Cassette.
This Monitor is
very powerful
in aiding the user to
Test and
Diagnose problems that
might occur in assembly and
testing.
The Assembled
Board purchaser might wish
to perform some of the
Diagnostics provided in
HMON to
continue to monitor the reliability of the System.
You might think
of the Diagnostics in HMON as a "Memory Test" for the Controller.
-
1 -
DOUBLE DENSITY SYSTEM MANUAL
CHAPTER 2: ASSEMBLING THE CONTROLLER;
CHAPTER 2
ASSEMBLING THE CONTROLLER
2.1
INTRODUCTION
Estimated Construction Time: 4-8 Hours
To build the Digital Group
following tools and equipment:
Dual Density Floppy Card, you
will need the
Fine tipped low wattage soldering iron (25 watt is ideal)
Solder 60/40 RESIN core wire solder, 20-30 gauge
DO NOT USE ACID CORE SOLDER (SEE OUR WARRANTY POLICY)
Diagonal cutters, small ~icro-shear preferred
Long-nosed plier~
flux remover or Alcohol
small brush
Volt-Ohmmeter (20K Ohms per VOLT or better)
15 Mhz Dual Trace Triggered Sweep Oscilloscope
Before you start to assemble the board, take a little time to inspect the
P.C.
board.
Check to see if there are any shorts on the top side of the
board under where the Integrated Circuit sockets will be placed.
Once the
Sockets are in place, it will be very difficult to find shorts in this area.
Also,
read through the entire assembly procedure before starting to
familiarize yourself with the proceedure.
2.2
PRELIMINARY INSPECTION
) Remove all parts from their bags and plastic rails.
( ) Sort the components into individual values. (cupcake trays
are good for this)
( ) Verify that all parts are there by checking them off of
the PARTS LIST in APPENDIX A
( ) Remove the Parts Placement Diagram from APPENDIX I
and place it conveniently in front of you.
- 2 -
DOUBLE DENSITY SYSTEM MANUAL
2.3
CHAPTER 2: ASSEMBLING THE CONTROLLER
RESISTOR INSTALLATION
NOTE: All resistors are mounted on .4 inch centers.
(If you have a lead bender, by all means use it.)
(vr'Insert the following Resistors into the board:
(
)
R42
47 Ohm
(yel-vio-blk)
)
R30 , R3 1
1 20 Ohm
(brn-red-brn)
)
R12,R13,R14
150 Ohm
(brn-grn-brn)
(
)
R15,R17
150 Ohm
(
)
R22
270 Ohm
(red-vio-brn)
(
)
R25
330 Ohm
(org-org-brn)
)
Turn the board over at this time and solder in these
Resistors.
~nsert
the following Resistors into the board:
R33 , R3 7
470 Ohm
R49 , R5 0
470 Ohm
R28,R36
1k
Ohm
R38
1K
Ohm
R9,R18,R19
2.2K Ohm
) R20,R21
(
(yel-vio-brn)
(brn-blk-red)
(red-red-red)
2.2K Ohm
Turn the board over at this time and solder in these
Resistors.
(If'Insert the following Resistors into the board:
( ) R27, R3 4 , R3 9
) R7
2.2K Ohm
(red-red-red)
2.7K Ohm (red-vio-red)
( ) R44, R4 5
3.3K Ohm (org-org-red)
( ) R29
3.9K Ohm (org-whi-red)
- 3 -
DOUBLE-DENSITY SYSTEM MANUAL
(
(I,
CHAPTER 2: ASSEMBLING THE CONTROLLER
)
R43
4.7K Ohm (yel-vio-red)
)
R46
5.6K Ohm (grn-blu-red)
)
R6 ,R1 0
6.8K Ohm (blu-gry-red)
)
R4
7.5K Ohm (vio-grn-red)
)
R8
9. 1K Ohm (whi-brn-red)
)
Turn the board over at this time and solder in these
Resistors.
Insert the following Resistors into the board:
( ) R23, R2 4 , R3 2
10K Ohm
( ) R40, R41 , R4 7
10K Ohm
( ) R48
1 OK Ohm
(brn-blk-org)
(
R5
11 K Ohm (brn-brn-org)
(
R2
15K Ohm (brn-grn-org)
(
R11
27K Ohm (red-vio-org)
(
R1
33K Ohm (org-org-org)
(
R3
820K Ohm
(
Turn the board over at this time and solder in these
Resistors.
2.4
(gry-red-yel)
INTEGRATED CIRCUIT SOCKET INSTALLATION
If you received SAE sockets with your kit, DO NOT REMOVE the white strips
on the bottom of the socket.
locat~
(;) Install the following IC Sockets at this time by inserting the socket
and SLIGHTLY bending two diagonally opposing corner pins outwards to hold
the socket onto the board.
(
IC3,IC9,IC22
8 Pin Socket
( ) IC50,51,52
8 Pin Socket
( ) IC53
8 Pin Socket
- 4 -
DOUBLE DENSITY SYSTEM MANUAL
CHAPTER 2: ASSEMBLING THE CONTROLLER
(~rn
the board over at this time and solder in the
8 Pin Sockets.
( . / Install the following IC Socke ts at this time by inserting the socke t
and SLIGHTLY bending two diagonally opposing corner pins outwards to hold
the socket onto the board.
IC2,IC5,IC6,IC7 14 Pin Socket
(
(
)
IC14,IC15,IC16
14 Pin Socket
IC17,IC18,IC19
14 Pin Socket
IC20,IC21,IC23
14 Pin Soc ke t
(
)
IC24,IC27,IC30
14 Pin Soc ke t
(
)
IC31,IC32,IC34
14 Pin Socket
(
)
IC35,IC36,IC38
14 Pin Socket
(
)
IC39,IC40,IC46
14 Pin Socket
(
)
IC48,49
14 Pin Soc ke t
)
Turn the board over at this time and solder in the
14 Pin Sockets.
(~Install
the following IC Sockets at this time by inserting the socket
and SLIGHTLY bending two diagonally opposing qorner pins outwards to hold
the socket onto the board.
(
(
)
IC 1 , IC4 , IC8
16 Pin Sockets
IC10,IC11,IC12
16 Pin Sockets
IC13,IC25,IC26
16 Pin Sockets
IC28,IC33,IC37
16 Pin Sockets
16 Pin Sockets
(
)
IC41 , IC4 5
(
)
Turn the board over at this time and solder in the
16 Pin Sockets.
(~nstall
the following Ie Sockets at this time by inserting the socket
and SLIGHTLY bending two diagonally opposing corner pins outwards to hold
the socket onto the board.
-
5 -
DOUBLE DENSITY SYSTEM MANUAL
( ) IC42,IC43,IC44
CHAPTER 2: ASSEMBLING THE CONTROLLER
20 Pin Sockets
NOTE: No 20 Pin Socket will be installed in IC Position 47.
( ) IC29
40 Pin Socket
(~Turn
the board over at this time and solder in the
20 and 40 Pin Sockets.
2.5
CAPACITOR INSTALLATION
Insert the following Capacitors into the board and then bending the leads
slightly enough to hold the Capacitor in place.
( ) Insert the following Capacitors into the board:
) C10,C11,C12
50pf Silver Mica
( ) C13,C14,C34
50pf Silver Mica
(
t~"'"'-C 5 3
36pf Silver Mica
(
~66
180pf Silver Mica (could be marked 181)
(~2'C74
220pf Silver Mica (could be marked 221)
( .1J65
680pf Silver Mica (could be marked 681)
(4 C32,C54
(~rn the
10dopf Silver Mica (could be marked 102)
board over at this time and solder in these
Capacitors.
(~nsert
the following Capacitors into the board:
( ~ C7 0 , C7 3
."
. 0 1 Dis c Ce r am i c
( ...., C49,C50
.01 1 0% Mylar
(/J" C4 8
.022 10% Mylar
( / C15
.022 10% Disc Ceramic
(~Turn
the board over at this time and solder in these
Capacitors.
- 6 -
DOUBLE DENSITY SYSTEM MANUAL
CHAPTER 2: ASSEMBLING THE CONTROLLER
( ) Insert the following Capacitors into the board. Be sure
to check the Parts Placement Diagram and PC board
for the correct orientation of the + end of the capacitors.
/"
(t...%
C40,C42,C43
4.7uf Tantalum (Obse rv e Polarity)
'/c68
4.7uf Tantalum ( Observe Polarity)
(/c9,C61,C62
10uf Tantalum
(Observe Polarity)
(,/( C71
10uf Tantalum
(Observe Polarity)
22uf Tantalum
(Observe Polarity)
.
-
/
C16,C39
(v}"
~
( ..}-'''C72
./
100uf' Tantalum (Observe Polarity)
/'
«(( Turn
the board over at this time and solder in these
Capacitors.
Insert the following Capacitors into the board:
(/)' C1-C8
.1uf Disc Ceramic
( ;( C17-C31
.1uf Disc Ceramic
{.t1
(/'
Insert the following Capacitors into the board:
( 1 C33 ,C35-C38
• 1 uf Disc Ceramic
{ ,{ C41 ,C44-47
• 1 uf Disc Ceramic
{ / ' C51 ,C55-C60
• 1 uf Disc Ceramic
(/C63,C64,C67
• 1 uf Disc Ceram i c
( /C69,C75
• 1 uf Disc Ceramic
(/'f
2.6
Turn the board over at thi's time and solder in these
Capacitors.
Turn the board over at this time and solder in these
Capacitors.
REMAINING COMPONENT INSTALLATION
(~ert
the remaining components into the board:
- 7 -
CHAPTER 2: ASSEMBLING THE CONTROLLER
DOUBLE DENSITY SYSTEM MANUAL
(~D1,D3,D4
(~D2
(/t;'
1N4148 Diode (save the leads for later)
1N4731A Zener Diode (.5 in. Centers)
22uh Choke (red-red-blk) looks like 2W resistor
5K Ohm 10 Turn Trim-Pot
4.000 Mhz Crystal
L~Fr
(~Turn
the board over at this time and solder in the /;
last of the components. Be sure to solder the /1'"
crystal as quickly as possible to mini'mize heat'.
$:
buildup.
2.7
(I '-'
f'
li8 (") ~
-
\
"0cJ~l:::-T )
L..f
b- 5~'
ff\,\CA)
?L. ( C iO-/q c., '3~
BOARD ADDRESS JUMPER INSTALLATION
(~Using
To 1)0
v~..tL \ 22\A h C~\~)
the leads saved from the
1N4148 Diodes:
~'. (TIt>..
'PIN
3~ 't:~~~
(~Form five jumper wires bent on .3 in. spacing.
(
/) Install the Port Addres sing jumpers into the jumper pads at
IC Position 47 as follows:
.//"~
(
-) Pin 1 to Pin 20
(/r
Pin 4 to Pin 17
( - ) Pin 5 to Pin 16
(
2.8
,
f
Pin 8 to Pin 13
(~)
Pin 10 to Pin 11
(Y
Solder in these jumpers and trim the excess leads.
HEAD LOAD MOTOR-ON JUMPER
If you intend to use the Disc Controller on Mini
cabling installed OR you intend to run both Mini
the DSS-INT1 cabling, install the following:
Drives with the DSM-INT1
and Standard drives with
( ) Install a small jumper wire between the pads near
the 36 Pin edge connector pins 18 and 19.
- 8 -
II
DOUBLE DENSITY SYSTEM MANUAL
2.9
CHAPTER 2: ASSEMBLING THE CONTROLLER
FINAL INSPECTION AND CLEANING
All components that are to be soldered onto the board have been soldered
in.
The only parts that should be left over at this time should be the
Integrated Circuits and 7 1N4148 Diodes.
These parts will be installed
during testing.
You should now look over your work and check for obvious
shorts, solder splashes and unsoldered pins. After you are satisfied that
no glaring shorts or opens exist,
clean the board in commercial board
cleaner or alcohol.
( ) Inspect the board for obvious solder shorts, solder
splashes, and unsoldered pins.
( ) Clean the board in commercial board cleaner or alcohol.
( ) Re-inspect the board for shorts and unsoldered pins again.
( ) Be sure that all solder jOints are clean and SHINY.
( ) RE-SOLDER any jOints that appear dull in finish.
( ) Reclean the board if joints needed retouching.
You have completed the assembly phase of construction.
Go to the
Installation Manual now and perform any CPU modifications that are required.
If you presently have a single density Controller (DSS-INT1 or DS~-INT1) and
you have a spare slot on the I/O Bus, you should parallel the connections on
Pins 34 and 36 of the 36 Pin edge connector to this spare slot. Some of the
testing could be done with your old controller installed along with the new
Double Density Controller.
If this is the first Disc Controller to be
installed in your system,
perform all required cabling at this time. You
don't need to parallel a slot if this is your first disc system. After you
have installed all required modifications and cabling you should take a
break.
The next thing we will do is test the Double Density Controller.
Proceed to the next chapter.
- 9 -
CHAPTER 3: TESTING/TROUBLESHOOTING
DOUBLE DENSITY SYSTEM MANUAL
CHAPTER 3
TESTING/TROUBLESHOOTING
3.1
INTRODUCTION
The Double Density Disc Controller is not a difficult board to troubleshoot.
The board was designed to be modular. The following tests check out each
section to the degree that the section should work.
Each test will also
give the user the ability to check further into the circuitry should the
test results be negative.
In general, if there is
the theory of operation
the problem lies.
3.2
GENERAL-
a problem in one section,
the user should consult
for that section to get a better idea as to where
POWER SUPPLIES AND CAPACITORS
Before power is applied to the disc controller board all of the power supply
traces should be tested. This is to ensure that shorts or reversed Tantalum
capacitors will not destroy the computers power supplies.
NO integrated
circuits should be installed on the disc controller board for this test.
(1). With an Ohmmeter, check the +5, +12, and -5 volt power
supplies with respect to ground and the other supplies.
There should be no direct shorts ( resistance less than 25
Ohms ) to ground or any other supply. Be sure to check these
measurements by reversing the leads of the Ohmmeter.
(2). If the above test was successful, recheck the polarity of
all Tantalum and Electrolytic capacitors.
If there was a
short between any power supply and ground or between any
supply find the cause of this short before proceeding.
(3). Insert the disc controller (less Integrated Circuits) into
the computer and apply power. Check to see that there are no
power supply failures.
Now, just leave the disc controller
inserted and the power on for about five minutes. If a
capacitor was installed incorrectly it will probabily fail in
this time period (it's better for it to fail now rather than
when all the Integrated Circuits are installed).
3.3
THE POWER-ON RESET AND LOW VOLTAGE CIRCUIT
-
10 -
DOUBLE DENSITY SYSTEM MANUAL
CHAPTER 3: TESTING/TROUBLESHOOTING
The Power-on reset circuit will now be tested.
This circuit holds the 1791
IC and
the write gate inactive during power up and during a power loss.
If
this circuit fails to operate the controller board will not function at all.
The cont~oller board may be inserted into any I/O slot for this test.
(1). Install the following IC:
IC34 (LM3302).
Insert the disc
controller board in the computer and apply power.
Adjust the
Computer +5 Volt supply for +5 Volts at the top of the Disc
Controller card.
The tolerance is + or - 5%. Do NOT use the
extender cards for this setting.
(2). Now, place the disc controller up on extender boards if you
have them. Apply power again and see if the output of IC34
pins 1 and 2 are high.
If not, check the +12 volt power
supply and then recheck the +5 volt supply.
If the +12 volt
supply failed (crow-barred) check all components associated
with that supply.
If the +5 volt supply was low, readjust
that supply and start the test allover again.
Correct
polarity of diodes D1
through D4 are critical to the
operation of this circuit.
Check to see if these diodes are
installed correctly.
(3). Observe the
output of
IC34 pins 1 and 2
with an
oscilloscope. During powerup,
IC34 pin 2 will hold low for
approximately 50 milliseconds.
If this level is not present,
check for shorts or bad polarity of capacitor C62.
Also, the
LM3302 could be bad.
(4). Now with the oscilloscope in place reduce the computer +5
volt supply until IC34 pin 1 goes low.
Note that this
voltage should be arround 4.3 volts.
If this voltage is
above 4.3 volts replace Zener D2 or Diode D1.
If the voltage
is below 4.3 volts,
check or replace the Zener D2 , or the
LM3302.
Retest if necessary.
(above or below means 10%
either way)
(5). Readjust the computer +5 Volt power supply to +5 volts as in
Step 1.
NOw, attach one probe to the +5 Volt supply and the
other to IC34 Pins 1 or 2, then cycle the AC power on and
off.
AC trigger the scope to when the +5 Volt supply starts
to go low.
Observe that the output of IC34 Pins 1 and 2 go
low prior to the total loss of the +5 volt power supply.
(Note that IC34 Pins 1 and 2 output goes low when the +5 Volt
supply passes through 4.3 Volts.)
(6). Now,
place one scope probe on the +12 Volt power supply.
Place the other on the +12 Volt supply Pin 3 of IC34.
Cycle
the AC power again and note that the +12 Volt "storage"
circuit comprised of C61,
R42 and D4 remains charged after
the standard +12 Volt supply discharges.
then remove the
scope probe from the +12 Volt supply and place it on the +5
- 11 -
DOUBLE DENSITY SYSTEM MANUAL
CHAPTER 3: TESTING/TROUBLESHOOTING
Volt supply.
Note also that while cycling the
AC power the
+5 Vol t
supply discharges to 0 while the 'voltage on IC34 Pin
3 is still above +5 Volts.
The +5 Volt supply discharge rate
is a function of the load of your
particular system, but it
should discharge in less than one second.
If this is not the
case, check
the polarity of D4 and C61.
Also
be sure.that
the value of R42 is correct.
3.4
USING HMON/2 FOR TESTING
Most of
the following
tests will use
the HMON/2 Hardware monitor for
exercising the controller board.
The user should read the HMON/2 Manual and
familiarize
himself with
the operation of this monitor.
HMON/2 has
been
used to adjust all the sections of the Dual Density Controller board.
The
only secton that the
monitor can't diagnose is the
Phase locked loop.
It
should
be noted
that using
the
INP-:CON function, the
user can
generate a
single repetitive pulse train that any "good" scope can sync to.
These pulses occur at approximately a 10 millisecond rate.
Use of the DELay
function can extend
these pulses
to allow the user.to trigger all of the
timing elements on
the board.
In one of
the sections we will use this
technique to check all the controller to disc
buffers and timing elements.
When an example is given there will be no explanation of the command or how
to terminate it.
The user should read the rest
of the test procedure and
then go back to the HMON/2 Manual and reread the functions used exclusively
for testing.
Be sure that you know how to STOP any function that we will be
using.
We will be
reloading
the
HMON/2 cassette
three or four
times.
If you
presently have a
Single density disc system or a Phideck system, you may
want to load in HMON/2 at this time and
save it on disk or cassette.
The
Double Density Controller board may be
tested in
the slot next to the
intended slot for most of the tests.
This can be accomplished by installing
temporary motherboard
jumpers from
the intended slot to this
new slot for
both
the
Int and Wait lines.
Remember, you can load HMON/2 through any
operating system except for the last test, which requires you to connect the
Double Density Controller to the actual disc drives.
3.5
BOARD SELECT AND GATING CIRCUITS
In this section we will test
all of
the, address gating and port
select
logic.
We will also test the wait logic here.
The first test will check to
see if any shorts exist in the output data enable and the wait enable lines.
If there is a problem here, the computer will not function as the controller
board will either interfear with
the computers I/O bus or
the Wait line.
Should the user have dynamic memory, the holding of the Wait line will cause
memory loss.
We will next test the Input/Output gating logic to see if the
- 12 ...
DOUBLE DENSITY SYSTEM MANUAL
CHAPTER 3: TESTING/TROUBLESHOOTING
board can be accessed.
Then, the wait logic will
be tested to see if the
wait timeout timer and the entire wait circuit functions properly.
(1). Install all IC's EXCEPT the following:
IC37, and IC44.
ICB,
IC9, IC22, IC29,
Check to
see
(2). Insert the
disc controller and apply power.
that all of
the power supplies are operating and that no IC
is getting excessively hot to the touch.
(3). With either a scope or a voltmeter, check the following:
(a). Pins 1 and 19 of IC44 are at a constant high level.
(b). Pin 15 of IC37 is also at a constant high level.
If either of these signals is low, there is a problem in the address select
or wait logic.
At this point the user should start back tracking from these
pins to find the source of the problem.
(4). Now remove power from the system and install IC's 37 and 44.
(Be sure
that
the Wait
jumper and Int
jumper on
the
motherboard are in place)
(5). Read
in the disc diagnostic tape
execute the HMON/2 with option 6.
using
The following
tests will
establish whether
generation logic are functioning properly.
the
the "ZEn ROM and
address decoding and wait
Most of the tests will have visual outputs to
the screen.
You should stop
with the
testing and start scoping the board when your outputs do not agree
with the examples.
(6). First we will
see if the board responds to the
Execute the following program:
computer.
:OUT-54,0:INP-54:0UT-54,377:INP-54 (cr)
The computer should respond with:
INPUT PORT 054
INPUT PORT 054
= 304
= 307
received,
go on to
step 7.
If both inputs
If this
is the
result you
selected.
Check IC's 16, 31, 33, 45.
resulted in a 000, the board was not
the
strobe
pulse
labeled RE4
on the
This
test
should have generated
schematic.
To aid in testing this section, re-execute the above test but
This will cause the test to be repeated
place a "CON" statement at the end.
- 13 -
DOUBLE DENSITY SYSTEM MANUAL
CHAPTER 3: TESTING/TROUBLESHOOTING
at speeds a
scope will sync to.
If the result of the test was not 000 but
something else, check the problem bits in IC's 30, 41, 42, 43 and 44.
(7). Now we'll see if the wait logic is operable.
Temporarily
short pins 38 and 39 of the IC29 to ground.
(Jumper IC29-39
to
IC29-3 and
IC29-38 to
IC29-20.) (Use
the
hookup wire
supplied.) Then try the following:
:SET-.10000 (cr)
:OUT-57,0:NEX:MES-/DONE/ (cr)
Time the length of the second line above.(app 25 sec) Th
:SET-.10000 (cr)
:OUT-53,0:NEX:MES-/DONE/ (cr)
The second test should execute about 1.5 seconds faster.
If this was true
proceed to step 8.
If the tests ran at the same speed, there is a problem
with the wait
logic.
Check, to see if the CPU mods have been installed and
their associated jumpers on the motherboard are there.
If this is not the
problem then read
the theory of operation of
the wait logic and check IC's
2, 7, 15, 17, 25, 36.
(8). We
apparently have some
communication with the controller
board at this
time.
Remove
power and insert all the IC's
EXCEPT IC29, the 1791.
3.6
DEVICE ATTRIBUTE, veo AND CLOCK CIRCUITS
In this section we will check out the Attribute selection circuts, the Phase
locked loop
and the Basic 1791 clock circuit.
The attribute circuit will
also test
some of the input/output buffer lines.
Any shorts on these lines
could
cause problems for the
1791 IC.
We will also
set the free running
frequency of
the Phase locked loop.
This adjustment is
the most critical
adjustment to be made and should be done carefully.
Once the adjustment has
been made,
we will change
the
attributes
for
device
and
check the
switching of different sections of the loop.
If a
problem arises in this
circuit,
a
careful examination of the
rest of this circuit is in order.
Finally, we will check
the Basic clock frequency of
the 1791 and check to
see if it switches properly for each attribute.
°
(1). Install
the
controller board
and reload HMON/2.
on its extender boards again
(2). Get two of the 1N4148 diodes that were supplied and bend the
leads to fit the .3" spaced socket.
(3). Please
refer
to APPENDIX
C on
-
DEVICE
14 -
ATTRIBUTES for the
DOUBLE DENSITY SYSTEM MANUAL
CHAPTER 3: TESTING/TROUBLESHOOTING
following:
(a). Start HMON/2 with option 6.
(b). The following program will be run for all 4 drives.
This is done by replacing the word "DATA" in the
OUT-54,"DATA" with the following: 0, 1, 2, 3.
In each
case the user should place a diode in each of the 4
possible positions for that drive and observe the
results on the screen.
(c). Run the following program for each drive:
:OUT-54,DATA:INP-54:CON (cr)
The results obtained should conform to the following
table:
DATA
POSITION
POSITION
POSITION
POSITION
0
300
344
324
314
1
301
345
325
315
2
302
346
326
316
3
303
347
327
317
------------1---------2---------3---------4-----
If any of the above results were incorrect, study the data pattern for all
tests and check the associated bits on the controller board.
Now we will set and check out the VCO basic free running frequency.
(2). The VCO free running frequency is set as follows:
(a). Place a diode in the Single/Double density position for
device O.
(b). Select this
instruction.
(c). Observe the
oscilloscope.
~
device
clock
by
executing
period
at
IC29
a
OUT-54,0
Pin
26 with
(cr)
an
(d). Adjust Pot R35 for a square wave with a period
usec high and 2 usec low. Tolerance is: +5% -0%.
of 2
(e). With a
3 of
voltmeter, measure
the DC voltage at Pin
- 15 -
DOUBLE DENSITY SYSTEM MANUAL
CHAPTER 3: TESTING/TROUBLESHOOTING
ICB. Make a note of this voltage on
later reference.
the schematic for
(3). Now we will check the operation of the loop.
(a). Remove the diode installed in the Single/Double de~sity
position for device O. Observe that the clock period at
IC29 Pin 26 just halved.
(1 usee high and 1 usec low)
(b). Now install the diode in the Mini/Standard position for
device O. Observe that the period doubled to 2 usec
high and 2 usec low.
(c). Install the second diode. in the Single/Double density
position for device O.
Observe that the clock period
doubled again to 4 usec high and 4 usec low.
If any of the above observations didntt occur, back
to where the problem exists.
track from IC29 Pin 26
(3). We will now test the fixed clock frequency for the 1791 IC.
This is either a 1 Mhz or 2Mhz clock applied to Pin 24 of
IC29.
(a). With the 2 diodes still installed from the above test,
observe that the period of the clock on IC29 Pin 24 is
500 nsec high and 500 nsec low.
(b). Now remove the 2 diodes and observe that the period of
the clock on Pin 24 of IC29 just halved to 250 nsec high
and 250 nsec low.
If you didn't
and 49.
3.1
observe the
2 different periods as above,
check IC's 19, 20
TIMING ELEMENT AND DISC I/O BUFFER CIRCUITS
In the following section we will check to see that all the timing elements
are operating properly. For example, if the drive change one-shot fails to
function,
all disc copying may fail
due to improper settle time.
Other
timing element failures could cause: loss of input data, improper write
timing, no motor startup delay or excessive wait states.
We will use the
strobe feature mentioned above to "fire" the timing elements and also to see
if a clear path exists for other Disc I/O Buffers.
(1). For all the tests we will use the input strobe of IC29 Pin
4. Use the hookup wire supplied to form jumpers fOr these
- 16 -
DOUBLE DENSITY SYSTEM MANUAL
CHAPTER 3: TESTING/TROUBLESHOOTING
tests.
If any of these tests fail, trace
through the logic
from
IC29
Pin 4 to the source of the problem.
Now let's
generate the repeatable strobe by executing the following:
OUT-54,0 (cr)
INP-50:CON (cr)
(2). First let's test the lines to the disc:
(a). Jumper IC29 Pins 4 and 15.
(b). Observe that
IC29 Pin 15.
the signal
at IC40 Pin 5 Is
the same as
(c). Now jumper IC29 Pins 4 and 16.
(d). Observe that
IC29 Pin 16.
the signal
at IC40 Pin 2 is
the same as
(f). Observe that
the signal
at IC39 Pin 5 is
the signal on IC29 Pin 28.
the same as
(e). Jumper IC29 Pins 4 and 28.
(g). Observe that the
signal at IC38 Pin 13
the signal on IC29 Pin 28.
is the same as
(h). Jumper IC29 Pins 4 and 30.
(i). Observe that
the signal
at IC38 Pin 2 is
The signal on IC29 Pin 30.
the same as
(3). Next we will test the head load delay timer.
There are two
ways this timer may be fired, we will test both.
(a). Reinstall the jumper from IC29 Pins 4 and 28.
(b). stop
the
following:
program
presently
running
and
type
the
INP-50:DEL-.100:CON (cr)
(c). Observe that the
negative going pulse at IC4
between 35 and 45 milliseconds.
(d). Now Stop the
following:
program that
is
OUT-54,20:DEL-.100:CON (cr)
(e). Jumper IC29 Pins 28 and 39.
-
17 -
Pin 4 is
executing and type the
DOUBLE DENSITY SYSTEM MANUAL
(f). Observe that the
CHAPTER 3: TESTING/TROUBLESHOOTING
pulse on IC4 Pin 4
is the same as in
( c) •
(4). We will
now check the wait timeout timer.
This may be aQne
,u i tho u t t e eu &e-~-O"f-~:t'U'm-p-e-p...s..-. J wt fNI/1-t:-v Ie -J'f 1;'1 S J
Now enter:
INP-51:CON (cr)
OUT-50,013:MAC-0 (cr)
The user should hear
the drive step to track
desending sequence of numbers from 377 to 000.
0 while the screen displays a
If you did not
get these results, first be
sure the device select light on
the drive
callie on.
If it did, again, manually spin the stepper motor shaft
to force
the head
to the center of the
disc.
Try the test again.
If the
numbers do appear desending on the screen but the drive does not step, check
all lines
corresponding to DIR STEP TKOO DSO and HLOAD.
If the numbers are
not decending on the screen, check the TKOO line first.
If this line is low
while the
device select light is on, we still don't have good communication
with the
1791 IC.
Check IC29 Pin 24 for a 2Mhz signal if Standard drive or
a 1Mhz signal for a Mini drive.
If the clock line is ok then the problem" is
'still in
the data
or port select logic.
Remove
the drive from the system
and
then remove
the 1791
IC and return to the
addressing section of this
manual.
(11). Assuming
diskette.
that
all is
well so
far,
its time to format
(a).
Place
an "expendable"
the door.
(b).
Carefully place a scope probe on Pin 2 of IC38.
Gate)
a
diskette in the drive and close
-
22 -
(Write
CHAPTER 3: TESTING/TROUBLESHOOTING
DOUBLE DENSITY SYSTEM MANUAL
(c). By now the drive select light should have gone out.
J) it hasn't, chec.k ~~e INDEX line for problems.
{f;r:J Sbv-t- H - rtr/AI B{i c!ft(v-? S- {fiJI( - v til ..,ctf vvvt ~ Cflf('p.., {, I)
(~). Here we GO!
Type the following:
If
FOR-O (cr)
The head should
have loaded and the drive should be stepping.
no responce, check the HLT logic and its associated IC's.
If there was
If the drive IS
stepping, check to see that
the signal on IC 38 Pih 2 Is a
square wave of 166/200 ms
up 166/200 ms down (std/mini).
If that is so,
we're probably formatting the disc.
To be sure:
(e). Wait for the format to finish and the head to unload.
(f). Carefully place
(Write Data)
the
scope probe
on Pin
5
of IC38.
(g). Retype the FOR-O (cr) instruction.
See that the signal on Pin 5 of IC38 is a series of 250ns pulses occuring at
a
2/4us rate
(std/mini).
If
these pulses are absent check
the Write
Precompensation circuit, IC's 12, 13, 14, 16 and 30.
(12). Seems we can format.
let's see if the controller can read.
(a). Type the following command:
RAT-3:RET (cr)
(b). You are now back in the Suding Operating System.
(c). Now enter HMON/2 at Option 5.
(d). You should hear the
drive restore to track 0
the introduction message.
(e). Let's see if it can read.
GED - 0 ,1
and see
Type:
(c r )
(f). The
system should
full of 345's.
respond with
a screen (128 bytes)
If the system went away, check the Interrupt lines you installed on the CPU
and ~otherboard
plus the wait logic.
If the system came back with an error
(CRC RNF IDF ), check the data separator in the following way:
Issue the following command:
- 23 -
DOUBLE DENSITY SYSTEM MANUAL
CHAPTER 3: TESTING/TROUBLESHOOTING
TRK-O (cr)
Place one scope lead
on IC25 Pin 12 and
the other on IC29 Pin 26.
Trigger
on
the
IC25 pin
first.
You
should see a series of
200ns pulses on IC25
separated
by
2/4us (std/mini).
The other
trace
should be a overlapping
square
wave
180 Degrees
out of
phase with the pulses.
There
is a 250ns
allowable
"jitter"
in
the Square
wave with
respect
to the pulses.
Now
switch
triggering and
see
that
the
square
wave stops
overlapping
and
measures 2/4us
up and
2/4us down (std/mini).
There is
an allowable error
here but
the timing
should be within 5%.
If -the square wave has a severe
"accordian" appearance to
it the loop is not
locking.
Remove the diskette
and
readjust
the VCO
Free
Running
Frequency,
(as
done before
in Sec
1.7-(2)), if incorrect.
Tole~ance is +5% and -0%.
Reinstall the diskette
and see
if the
problem clears itself.
If not,
there is a problem in some
part of the
loop_
Go read the theory
of operation of the VCO Phase locked
loop and check IC's 6, 7, 8, 9, 10, 11, 15, 17 21, 24, 35 and 25.
(13). If you
received a screen full of 345's, it looks as if the
controller reads.
But, let's be sure.
Type:
RES:VER (cr)
Allow the drive to step through all tracks and return with:
DONE
Now type:
DEC:ERA:STA (cr)
The screen
should
erase
and the
Disc Status
Table
should be displayed.
There should be 01001/00720 (std/mini) reads with no errors logged.
(14). The last test will be to see if the controller can read and
write successfully.
Type the following:
RES:ERA:RND (cr)
HMON/2 will now do 100 random read/writes.
Wait for:
DONE
Now letts look at the Disc Log Table again by typing:
ERA:STA (cr)
The table should now show 100 reads and 100 writes with no errors.
If the above tests were successfull, The Board 'is in operating condition and
you should read
the Theory of Operation and
the rest of the documentation.
You might
want
to test
the board
further
at this time.
Read
the tests
available
in the
HMON/2 Manual
and try some of them.
The Disc Log Table
-
24 -
CHAPTER 3: TESTING/TROUBLESHOOTING
DOUBLE DEN SITY ,SYSTEM MANUAL
will keep
track of
the
performance
examined as these tests execute.
of the
- 25 -
hardware
and signals can be
CHAPTER 4: THEORY OF OPERATION
DOUBLE DENSITY SYSTEM MANUAL
CHAPTER 4
THEORY OF OPERATION
4.1
INTRODUCTION
The Theory of Operation is broken into 13 sections,
each covering a
different portion of the circuitry.
There is a partial schematic next to
each section so that the user may view that section as he reads the theory.
As far as terminology is concerned, points on the schematic that are
labelled with a signal name, will be called by that name. For points on the
schematic that are not labelled, the IC and its associated pin number will
be used (IC29 Pin 4 will be written as IC29-4).
If an IC has more than one
function the IC will be broken into parts, ie, IC13a.
There are many inputs and outputs of gates that require pullups.
When a
pullup resistor in used to pull up gates in different areas on the
schematic, that pullup resistor appears in both areas. Don't be confused
when you see numerous resisitor numbers repeated.
Also, all resistors in
the RPACK labeled IC26 are called out on the schematic as R26-(Pin Number).
4.2
PORT LABEL DEFINITIONS
The controller occupies eight consecutive I/O addresses.
Of these, six
are used.
The base address must start on an address that is a multiple of
eight.
There are 32 such locations that the controller board can occupy.
For the Theory of Operation and for the Software Listings, we will fix this
base address as 050Q or 028H.
All references to these ports could be either
numeric or by their software label.
The following table should aid the user
in determining the ports.
PORT
INPUT DESCRIPTION
OUTPUT DESCRIPTION
050
051
052
053
054
055
056
057
STAT- 1791 STATUS
TRACK- CURRENT TRACK
SECTOR- DESIRED SECTOR
AVAIL BUT NOT USED
SEL- NUMEROUS FLAGS
NOT USED
NOT USED
WAIT- USER DATA PORT
CMND- 1791 COMMAND
TRACK- CURRENT TRACK
SECTOR- DESIRED SECTOR
DATA- SEEK DATA
SEL- DEVICE SELECT
NOT USED
NOT USED
WAIT- USER DATA PORT
------------------------------------------------------ -~-----
FIGURE 1.
- 26 -
CHAPTER 4: THEORY OF OPERATION
DOUBLE DENSITY SYSTEM MANUAL
4.3
POWER-ON RESET AND LOW VOLTAGE CIRCUIT
The Power-On Reset and Low Voltage Circuit monitors the computer's +5
Volt line.
It forces the 1791 into Master Reset on powerup and during any
other time that the +5 Volt line decays below +4.3 Volts.
This
This circuitry also inhibits Write Gate during these occasions.
prevents the controller from accidentally writing over portions of the
diskette.
This circuit consists of IC34,
a Quad
associated resistors, capacitors and diodes.
Comparator (2
used),
and its
During powerup the output IC34-2. has control of the circuit.
The
sequence of events are as follows: D%rhas allowed C62 to discharge rapidly,
insuring that
on the initial (or subsequent) powerup, C62 will be
discharged. When power is applied, C62 begins to charge through R37.
At
this time IC34-5 (the positive input) tracks the capacitor.
R28 and R29
form a voltage
divider that sets the negative
compare voltage at
approximately 4.0 Volts.
Until this voltage is exceeded on the positive
input IC34-5,
the output IC34-2 remains low.
The Capacitor, C62 takes
approximately 50 milliseconds to charge to a voltage above 4.0 Volts.
This
keeps the output IC34-2 low for this time which forces a Master Reset into
the 1791 IC.
It also keeps the Write gate IC38-3 inactive.
During a voltage fluctuation on the +5 Volt supply that falls below +4.3
Volts, comparator output IC34-1 becomes active. The sequence of events is
as follows: The positive input of the comparator IC34-7 tracks the +5 volt
supply through R38.
The negative comparator input,
IC3~-6, Has a fixed
reference voltage of +4.3 Volts set by the Zener diode rijP.
R37 provides
constant current through the Zener. When +12 Volts is lost, blocking diode
D;t, along with cap~citor C73, temporarily provide the current for the
reference Zener,
D;.r. When the +5 Volt supply drops below the reference
voltage on IC34-6, the comparator output IC34-1 goes low, again forcing the
1791 IC into Master Reset and inhibiting the Write Gate.
To insure that the outputs of the comparators remain active during a
normal system power down,
capacitor C61,
along with blocking diode, D~~
combine to supply the voltage and current for IC34.
Resistor R42 insures a
constant charging rate for C61.
- 27 -
+12
03
1N4148
+5
R37
470
+58
R28
+5
R43
4.7K
01
1N4148
R42
47
1K
R36
1K
6
4
I
1
f\)
-..:J
::.>
I
R29
3.9K
+
"+
5
C62
10
10
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POWER-ON RESET AND LOW VOLTAGE CIRCUIT
FIGURE 2
MR
DOUBLE DENSITY SYSTEM MANUAL
4.4
CHAPTER 4:
THEORY OF OPERATION
ADDRESS DECODE AND CPU I/O BUFFERS
The Address Decode
and I/O Buffer circuit enables the computer
information to and from the Double Density Disc Controller board.
In order for the
met:
board to be accessed,
the
to pass
following conditions must be
O~\D\it~
1. The upper five address lines must match the selected base address.
2. The three lower address lines must be in the range of 0 through 4 or7.
3. Either I/O READ or I/O WRITE must be active low.
When these conditions are met the board can be accessed for read or write.
ADDRESS GATING
The addressing operation happens as follows: The upper five address lines
are presented
to
IC46
where
the
user selects
which
section in the I/O
address space
he wishes
the board to occupy.
This
is done by selectively
inverting the
proper
lines in
IC46.
Once
this
has been done, when
the
computer sends
this address to the board, IC4B-B will go low.
This line is
the Conditional Board Select (CBS) signal and is gated to the following: 1.
To the
I/O Buffer Control Gate IC16-12.
2.
To
the enable input of IC33,
the
Port Select Decoder.
The
lower three addresses are presented
to the
port
decoder
through Latch IC45.
Also the
lower
two address lines are
buffered in
IC1Bc,d and
presented to the Controller IC29.
IC33 generates
all the
conditional port
select gating.
If the lower
three address lines
are between 0 and 3, IC33 gates on IC32-B which in turn is inverted in IC17.
This inverted
Controller Select(CS)
signal partially enables ICts 18a and
18b.
If the
lower three address lines were
decoded in IC33 to be equal to
4, The RW4 signal is generated which partially enables ICts 31a and 31b.
If
the
lower
three address
lines were
decoded to be 7, The
SEVEN signal is
generated.
This SEVEN signal is passed to the Wait logic.
We have at the
present selected one of three
things.
We have generated
the CS Signal or the RW4 signal or the SEVEN signal.
We have also partially
enabled the I/O buffer control gate.
I/O READ
Now, if
this is
a I/O
READ operation, the computer will
lower the I/O
READ line.
This
line is
presented to
four gates.
First it will
fully
enable the I/O buffer control gate IC16-13 which will cause the input buffer
IC43 to turn off and then 'the output
buffer IC44 to turn on.
Second it is
combined with RW4 in IC31a.
Third, ,it will combine with CS in IC18a.
If the RW4
signal was active, I/O READ combines with RW4 to generate the
RE4 signal
at the
output of IC31a.
This signal
enables octal buffer IC42
onto
the I/O bus allowing
the ,computer to read the
data in the D Latches
IC41,
the
drive attribute
bits,
and
the
two
status signals
from
the
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15
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-31-
+5
DOUBLE DENSITY SYSTEM MANUAL
4.6
CHAPTER 4:
THEORY OF OPERATION
SEL PORT LOGIC
The SEL
Port
logic
contains all
drive
select,
side
select,
board
interrupt
enable, and drive
change
logic.
The
drive select
bits
are
read/write.
The side select bit is read/write only if that particular drive
is jumpered as present.
The board interrupt enable bit and the drive change
bit are write only.
All bits except the drive
change bit are stored in D
type Latch IC41.
There are three drive attribute bits associated with the SEL Port.
These
bits
set
up the
drive's attributes
according to the diode matrix.
This
matrix allows each
drive to be of a
different size or density or number of
sides.
DRIVE SELECT CIRCUITRY
The lower two bits of the SEL port are the Drive Select bits.
These bits
are presented
to the
drive select decoder, IC28, where
a Two Line to Four
Line decode takes
place twice.
The first, in
IC28a, is used to select the
correct
drive when
the head
is loaded.
This decoder provides
the drives
with the Drive Select signal through inverter IC27 and Open Collector Driver
IC39.
The second
set of decoding,
IC28b,
is active
all
the time and
provides the
diode matrix with one crosspoint per drive.
These crosspoints
are labeled
1 through 4 on the schematic and correspond to drives 1 through
4 that
may be attached to the controller.
The crosspoints provide a ground
for the diodes that would be installed to select certain attributes.
SIDE SELECT CIRCUITRY
The Side
Select bit
is the
third bit.
This bit is
sent to the drives
through
Open Collector Driver IC40d.
The Side
Select
line, IC41-3, is
logically ORed in IC31d with the "A" column of the diode matrix before being
read back by the computer through Octal buffer IC42.
Placing a diode in the
"A" column for the selected drive causes resistor R18 to be pulled low by an
output
of IC28b.
This low
allows the output of IC31d
to track the input
IC31-13.
If
no
diode was
installed in
the
"A" column for the
selected
drive,
resistor
R18
presents
a
constant
one
to
the
output of
IC31d
regardless of the condition of the Side Select D Latch IC41.
The software selects the
bottom side of a particular drive by writing a
zero to
the side
select bit.
If upon reading
back this bit, the software
finds that
it
has changed
to a
one,
it can be assumed
that no drive is
present for this particular drive number.
DRIVE CHANGE CIRCUITRY
The Drive Change
signal is
generated by the combination of WE4 and the
fifth
bit
of the
SEL Port
in IC16-10.
This signal is
a one microsecond
positive
strobe and
is Write
only.
The drive change strobe
triggers the
-
32 -
DOUBLE DENSITY SYSTEM MANUAL
head load
~)
CHAPTER 4: THEORY OF OPERATION
delay one shot IC4-4 if the head was already loaded.
1
(See Figure
BOARD INTERRUPT CIRCUITRY
The top output
bit is the Board Interrupt Enable bit.
This bit is write
only.
When
set to a one,
this signal allows the interrupt generated by
INTRQ or DRQ in IC36b,c
to be gated through Open
Collector driver IC40c.
Specific causes for interrupts are discussed in the 1791 section.
ATTRIBUTE SELECT LOGIC
The Drive
Attribute Logic
performs all
logic
switching to convert the
controller board
from different
densities and
different size diskettes.
There
are four
attributes that
are selected by the diode matrix for each
drive.
These are:
A.
B.
C.
D.
Drive Present (explained in Side Circuitry).
Single or Double Density.
Mini or Standard Drive.
One or Two Sided.
Three of
these attributes
are presented
through five of the SEL Port through IC42.
to the computer on bits
three
The first of these attributes is the Single/Double Density attribute.
To
generate the Double attribute, no diode is placed in the "B" column for the
selected drive.
This causes resistor R19 to pull up the "B" crosspoint for
the selected drive.
In turn, IC30b inverts this high to generate a low SID
Signal.
The
SID
signal is gated with other
portions of the circuit
to
select Double
density.
This signal is also presented to Octal buffer IC42.
If a diode
is installed
in the "B" column in
the matrix for the selected
drive, the line
from IC28b pulls down resistor
R19, which is then inverted
through IC30b
to produce
a high SID signal.
This
high SID signal is then
gated to other portions of the circuit to select Single Density.
The second
of
these
attributes
is
the
Mini/Standard attribute.
To
generate the Standard attribute,
no diode is placed in
the tIC" column for
the selected drive.
This causes resistor R20 to pull up the "C" crosspoint
for the selected drive.
This in turn generates
a high STD signal attached
to R20.
IC30a invert this high level to generate a low MIN signal.
Both of
these signals are gated with other portions
of
the circuit to select a
Standard drive.
The output of IC30a is presented to Octal buffer IC42.
If
a diode is installed in the "C" column in the matrix for the selected drive,
the line
from
IC28b pulls down resistor
R20,
which generates a low STD
signal.
This
low is
inverted in IC30a to generate the high MIN signal.
Both these
signals are gated to other portions of
the circuit to select a
Mini drive.
The third
attribute
is the
Side attribute.
- 33 -
To
select a single Sided
DOUBLE DENSITY SYSTEM MANUAL
CHAPTER 4: THEORY OF OPERATION
drive, no diode is installed in the "D" column for the selected drive.
This
causes resistor R21 to pull up the input of inverter IC30e.
The low output
of IC30e is passed to Octal buffer IC42 to be read by the computer as single
sided. If a diode was placed in the "D" column of the selected drive, the
output of IC28b will pull down resistor R21. This low is inverted by IC30e
and passed to Octal buffer IC42 to be read by the computer as double sided.
OTHER SEL PORT SIGNALS
Two other read only signals are accessable by reading the SEL port.
These are status outputs of the controller IC29.
The INTRQ output IC29-39
is passed to the tOP.)it of Octal buffer IC42 while the DRQ output IC29-38
is presented to the '1si~th. bit(PVof Octal buffer IC42.
These two signals will
be explained in the 1791 section.
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10-
SEL PORT LOGIC
FIGURE 5
- 34 -
8
>SIDE
34
CHAPTER 4: THEORY OF OPERATION
DOUBLE DENSITY SYSTEM MANUAL
4.7
WRITE PRECOMPENSATION CIRCUIT
The Write
Precompensation Circuit
generates the proper amount of
compensation to the Write Data pulse for reliable Double Density operation.
This is done by selecting one out of the three one-shots to be fired for the
correct length of time.
The original Write Data pulse is delayed a fixed
amount of time for Nominal Data timing.
For an Early Write data pulse, the
original Write Data pulse is generated 150 nanoseconds earlier than a
Nominal Data pulse. For a Late Write data pulse,
the original Write Data
pulse is delayed 150 nanoseconds after the Nominal Data pulse.
Three signals from the controller IC29 are required to operate the Write
Precompensation Circuit. These are Early, Late and Write Data. The Early
and Late signals are valid prior to the leading edge of each Write Data
pulse.
The Early signal IC29-17 is passed directly to the negative edge
enable input of the Early one shot IC13b.
The Late signal IC29-18 is passed
directly to the negative edge enable input of the Late one shot IC12a. Both
the Early and Late signals are NORed in IC16b to produce the negative edge
enable signal for
the Nominal one shot IC13a.
Note that under normal
operating conditions,
the combination of Early and Late being high at the
same time is not possible. The Write Data pulses are inverted by IC30c to
produce a negative pulse.
This negative pulse is presented to the negative
edge trigger input of Early, Nominal and Late one shots IC13b, IC13a, and
IC12a. Whichever oneshot has its negative edge enable input high will fire
at this time. This pulse in NANDed in IC14 to trigger the Write Data one
shot IC12b on the falling edge.
This one shot produces a positive going 250
nanosecond Write Data pulse that is presented to the drives through Open
Collector Inverting Driver IC38b.
30C
5
WD
S
WD
NOM
7404
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74LS221 (300NS)
11
3
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74LS221
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WRITE PRECOMPENSATION CIRCUIT
FIGURE 6
- 35 -
DOUBLE DENSITY SYSTEM MANUAL
4.8
CHAPTER 4: THEORY OF OPERATION
DELAY AND READY LOGIC
The delay logic performs three delay functions.
included in this section.
The READY logic is also
MINI MOTOR DELAY TIMER
The first delay is the motor timeout timer for. Mini drives.
This timer
IC3 acts as a retriggerable one shot.
The timer is enabled by the MIN
signal on Pin 4.
The timer is triggered by one of the four port enable
strobes RE, WE, RE4, WE4 through IC14. Once triggered, capacitor C9 charges
through resistor R3. When further accesses are made to the board,
IC14
pulses high. These high pulses are used to partially discharge capacitor C9
through two Open collector Inverters IC21c,d.
This discharge pulse is one
micro second in duration and many of these pulses are required to maintain a
low voltage on capacitor C9.
It should be noted then,
that the motor on
timer requires HEAVY board usage to maintain the mini motors in the on
state.
MINI MOTOR STARTUP DELAY TIMER
The second timer is the mini motor startup timer IC4b.
This timer
inhibits the controller IC29 from reading or writing until the mini motors
are up to speed.
The only time this timer fires is when a rising edge is
generated by the mini motor timer starting.
If the selected drive is a Mini
drive, the STD signal is low. This signal is presented to the positive edge
trigger enable input IC4-9. The rising edge of IC3-3 generates a negative
going pulse out of IC4-12. This negative going pulse is ANDed with the Head
load delay timer in IC15a to produce a low on IC29-23 whenever a delay in
reading or writing to the disc is required.
HEAD LOAD DELAY TIMER
The third timer is the head load delay timer.
This timer inhibits
reading or writing to the disc whenever the head has been loaded and the
head settling time has not expired.
The head load delay timer can be
triggered in one of two ways.
The first way is when the controller IC29-28
(HLD) goes high signifing that the head is to be loaded.
On this occasion,
IC4-1
is low.
The rising edge HLD into 'IC4-2 causes the one shot to
trigger. This generates a low output pulse on IC4-4 which is ANDed with the
mini motor startup timer in IC15a. The output of IC15a generates a low on
IC29-23 causing reading or writing to the disc to be inhibited.
The second way the head load timer may be triggered is when the head is
loaded and a drive change pulse is issued. When the head is loaded, HLD
presents a high to IC4-2.
This high level is also equivalent to the
negative edge enable required by the negative edge trigger input to trigger.
When a drive change pulse is generated in IC16c (DR CHG), the negative edge
of this pulse triggers the Head load timer. The drive change pulse only
will trigger the head load timer when the HLD signal is active high.
- 36 -
CHAPTER 4: THEORY OF OPERATION
DOUBLE DENSITY SYSTEM MANUAL
READY LOGIC
The Ready logic performs three tasks.
It allows the Ready line from a
Standard drive to be inverted and gated to the controller IC29-32 whenever
the head is loaded.
It prevents the Ready line to the controller IC29-32
from going Not Ready whenever the head is not loaded.
It also presents a
constant Ready to the controller whenever the controller is using Mini
drives.
IC5 performs all the Ready logic functions.
IC5a,b,d combine to form an
AND OR circuit.
One input to the AND OR is through IC5c.
The two inputs to
IC5c are the high true head load (HLD)
signal and the low true Drive Ready
signal from 36 Pin edge connector Pin 8.
Resistor R17 terminates the Drive
Ready signal.
The only time a Not Ready signal is Presented to the IC5-4
input to the AND OR circuit is when the drive is Not Ready (IC5-9 high) and
the HLD signal to IC5-10 is high.
This causes the output of the AND OR gate
to go low if IC5-5 was high.
In order for IC5-5 to be high, IC5d must have
a low on its input, which is the MIN signal.
This case would be true if the
STD signal has .high (selecting Standard drives).
If the MIN signal was
high, its inversion through IC5d disables the Standard drive ready line and
produces a constant high on the output of the AND OR gate by placing a low
on IC5-2.
+15
+5
DELAY AND READY LOGIC
FIGURE 7
7438
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-37-
DOUBLE DENSITY SYSTEM MANUAL
4.9
CHAPTER 4: THEORY OF OPERATION
CONTROLLER CLOCK CIRCUIT
The controller clock circuit generates and switches the system clock
between the two frequencies required for Mini and Standard drives. The
clock frequency for Standard drives is 2 Mhz and the the clock frequency for
Mini drives is 1 Mhz.
A 4 Mhz clock signal is generated by the TTL oscillator IC49. D type
Flip Flop IC20a divides this 4Mhz clock by 2 before it is presented to D
Flip Flop IC20b where it is divided by 2 again. The Q output of IC20a is
presented to IC19b which is acting as a two to one line decoder. The Q
output of IC20a is presented to IC19d.
The 2 Mhz clock is passed to the
controller IC29-24 through IC19b,c when the STD signal is high. The 1 Mhz
clock is passed through IC19d,c when the MIN signal is high.
The 2 Mhz signal
clocking of IC2.
from IC20a is also presented
to the Wait logic for the
~----------------------------------2MHZ
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4MHZ
7400
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470
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2MHZ
' - - - - - - - - - - - - - - - - - - - - - - - - - MIN
CONTROLLER CLOCK CIRCUIT
FlGURE8
- 38 -
STD
DOUBLE DENSITY SYSTEM MANUAL
4.10
CHAPTER 4:
THEORY OF OPERATION
VCO PHASE LOCKED LOOP
The VCO Phase Locked Loop is comprised of six sections.
1.
2.
3.
4.
5.
6.
These are:
Phase Comparator
Loop Filter (switchable)
Amplifier
Low Pass Filter
Voltage Controlled Oscillator
Divider Chain
PHASE COMPARATOR
The Phase Comparator
determines the
phase error of the input
frequency
(Data) against
the present VCO frequency and generates a difference voltage
used to
change
the frequency
of the
VCO
towards the incoming Read
Data
frequency.
Read Data from
the disc
is buffered
by IC37d.
The Read Data line is
terminated by
resistor R15.
The buffered Read Data is
presented to IC25b
where
the
input pulse
is shortened
to 200 nanoseconds.
The Q output of
IC25b is sent
to the controller IC29-27 as
the RD pulses.
The Q output of
IC25b is presented
to the clock input of
IC35b.
IC35b, a D type Flip Flop
performs a divide
by two on the data.
This converts the input data from a
pulse to either
a rising edge or a
falling edge.
This divided by two data
is presented to
D type Flip Flop IC35a.
Here the Data is clocked with the
2X
VCO frequency.
A phase
comparison is made between the
2X VCO and the
input
data
in IC6b.
This
comparison is
inverted
in
IC17e and
then
reinverted in
IC21f to
produce the Pump Up signal.
The Pump Up signal is
also ANDed with the 1X VCO signal in IC15d and then presented to the D input
Of D type Flip Flop IC24b.
This Flip Flop is clocked by the 2X VCO signal.
The Q output of IC24b is inverted in IC21e to produce the Pump Down signal.
LOOP FILTER
The Loop Filter generates the
lock, range and steady state
Phase error
constants of the system.
It has two extra cap~citors that are switched into
operation to
change
the characteristics of the
loop
for different data
rates.
-
39 -
DOUBLE DENSITY SYSTEM MANUAL
CHAPTER 4: THEORY OF OPERATION
The Pump Up and
Pump Down signals are
combined at the
junction of
resistors R40, R32,' and R33.
The steady state bias point of this junction
is 2.5
Volts.
The
Pump Up and Pump Down signals vary this voltage in
proportion to
the frequency difference between the incoming data pulses and
the 1X VCO frequency.
Loop filtering is done in resistor R33 and Capacitors
C48,
C4g and
C50.
In Double Density Standard mode, both C48 and C50 are
gated off by
the two lows presented to
the inputs of IC's 15b and 6c.
The
two lows are
the MIN and SID signals
produced in the diode matrix.
In the
Single Density Standard and Double Density Mini mode, only capacitor C48 is
gated off.
In this case, one of the two signals MIN or SID is low.
One of
these lows inhibits one input of AND gate IC15b.
Capacitor C50 is gated on
by one
of these signals also
through IC6c.
The last case is the Single
Density Mini.
Here, capacitor
C48 is gated on and
capacitor C48 is gated
off.
In Single Density Mini,
both MIN and
SID are active high.
This
enables AND gate IC15b and disables XOR gate IC6c.
These capacitors modify
the natural
frequency of the loop to accomodate the different data rates of
the above types of drives.
LOOP AMPLIFIER
The Amplifier is used
have a high slew rate.
to adjust overall loop gain.
This Amplifier must
The Loop Amplifier is a noninverting high slew rate Operational Amplifier
with a gain of +2.1.
The input resistance is
the parallel combination of
R41 and R47.
The feedback resistor is R46.
The negative input is biased at
2.5 Volts
to adjust
for the steady state input bias from the Loop Filter.
This steady state bias is passed to the next stage.
LOW PASS FILTER
The Low pass filter is used to remove high frequencies introduced by the
digital
phase comparitor.
It is
also used to reduce the
response of the
loop to instantanious variations in the input data stream.
The Low Pass Filter is a 2 Pole Butterworth Active filter.
The cutoff
frequency
of
this filter
is approximately 150 Khz.
The Low Pass Filter
consists of ICg a LM741 , capacitors C65 and C66, plus resistors R44 and R45.
It is a noninverting type filter.
VCO
The VCO is ~he basic clock for the loop.
Mhz/Volt
constant
and a Frequency input
achieve lock.
It has a Range input to set the
to vary the output frequency
to
The VCO
is a Texas
Instruments 74S124 Dual VCO IC.
Its free
running
frequency is set by the Range input and capacitor C53.
The output frequency
is 8Mhz.
Capacitor C54
filters the Frequency control input
to remove any
high frequency
noise generated by the TTL circuits nearby.
The 8Mhz output
- 40 -
CHAPTER 4: THEORY bF OPERATION
DOUBLE DENSITY SYSTEM MANUAL
on ICB-7 is sent
required for the
disabled.
t~
the Divider Chain
Phase Comparitor.
to provide the 1X and 2X VCO signals
The second VCO section of ICB is
DIVIDER CHAIN
The Divider Chain provides different divide rates for the different data
rates used in the controller.
It also provides the controller IC29 with the
1BO degree out of phase bit rate clock required for data separation.
The Divider Chain receives its input from ICB-7 the VCO.
This BMhz
signal is first divided by two in D type Flip Flop IC7b.
The output of IC7b
is a 4 Mhz signal presented to the Binary divider IC10.
IC10 divides this 4
Mhz signal into the different 1X and 2X VCO signals required.
IC11 is a
Dual four line to one lin~ multiplexer.
The output of IC11b is the 1X VCO
signal. The output of ICl1b is the 2X VCO signal.
The multiplexer is
switched by the SID and MlN diode matrix signals.
The output periods of
IC11 for different SID and MIN signals are tabulated below.
SID
MIN
0
1
1
1
0
1
DRIVE TYPE
:tC11a
IC11b
D.D.
D.D. MIN
S.D. STD
S.D. MIN
1
2 us
2 us
4 us
.5
1 us
1 us
2 us
---------------------------------------------------------us
us
0
0
STD
The output of IC11b is first limited to a period of BOO ns low and BOO ns
high by IC1.
This prevents exceeding the limits imposed by the controller
IC29 on its RCLK input IC29-26 (see 1791
operating specs).
This signal is
then divided by two to generate the 1BO degree out of phase RCLK signal, in
IC24a.
The RCLK signal is pre~~ted to the controller IC29-26.
- 41 -
DOUBLE DENSITY SYSTEM MANUAL
4.11
CHAPTER 4:
THEORY OF OPERATION
DISC I/O BUFFERING
The Disc I/O signals and the IRQ signal buffering will be discussed here.
There are three
Status signals from the drive that are buffered by parts
of IC37.
These are:
The Write
Protect
Signal
enters the
controller board
on 36 Pin edge
lconnector Pin
9.
This
line
is
terminated by
resistor
R12.
The Write
Protect signal
is buffered
in IC37a and is presented
to the WP controller
input IC29-36.
The Index signal
enters the controller board on 36 Pin edge conector Pin
5.
This line
is terminated by resistor R13.
The Index signal is buffered
in IC37b and then presented to the IP controller input IC29-33.
The Track 0 signal
enters the controller board on 36 Pin edge connector
Pin 12.
This
line is
terminated by resistor R14.
The
Track 0 signal is
buffered in IC37c and then presented to the TROO controller input IC29-34.
There are four
controller outputs that are inverted and buffered by Open
Collector IC38.
These are:
The Write Gate
signal is conditioned by the Master Reset signal in IC38a
before being sent to the drives on 36 Pin edge connector Pin 7.
The Write Data signal
is sent to the drives
through IC38b.
leaves the board on 36 Pin edge connector Pin 10.
This signal
The Motor On signal from IC3-3 is conditioned by the MIN signal in IC38c
before being sent to the drives on 36 Pin edge connector Pin 19.
The Head
Load signal
is conditioned
by the STD signal in
being sent to the drives on 36 Pin edge connector Pin 18.
IC38d before
The Drive Select signals DS1, DS2, DS3, and DS4 are inverted and buffered
by IC39b,c,d,a before being sent to the drives in 36 Pin edge connector Pins
13, 23, 24, and 25 respectivly.
There are
are:
three drive
lines and
one CPU line buffered in
The Direction line is
buffered in IC40a before being
on 36 Pin edge connector Pin 15.
The step signal is
buffered in IC40b before being
36 Pin edge connector Pin 6.
-
42 -
IC40.
These
sent to the drives
sent to the drives on
+5
7486
I PHASE
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FIGURE 11
CHAPTER 4: THEORY OF OPERATION
DOUBLE DENSITY SYSTEM MANUAL
The Side signal is buffered in IC40d before being
36 Pin edge connector Pin 21.
sent to the drives on
The IRQ signal is buffered in IC40c before being sent to
Interrupt Socket Pin 8 through 36 Pin edge connector Pin 34.
- 43 -
the
CPU
DOUBLE DENSITY SYSTEM MANUAL
4.12
CHAPTER 4: THEORY OF OPERATION
POWER SUPPLIES
The +12 Volt supply for the board enters on 22 Pin edge connector Pin 22.
It provides +12 Volts to the controller IC29, The Amplifier IC22, the Low
Pass Filter IC9 and to the Comparator IC34.
It is filtered by capacitors
C38, C59, C63, C68 and C69.
The -5 Volt supply for the board enters on 22 Pin edge connector Pin B.
It provides -5 Volts to the Amplifier IC22 and the Low Pass Filter le9.
It
is filtered by capacitors C41, C42, c60 and C64.
The +5 Volt supply for the board enters on 22 Pin edge connector Pins 1
and A.
This supply provides all +5 Volts to the TTL integrated circuits and
to the pullup resistors.
The +5 Volt supply is also filtered by inductor L1
and then provides the +5b Voltage for the VCO section.
The +5 volts is
filtered by numerous tantalum and disc ceramic capacitors.
- 44 -
DOUBLE DENSITY SYSTEM MANUAL
4.13
CHAPTER 4: THEORY OF OPERATION
INTERRUPTS
The Digital Group Double Density Controller board uses a scheme of
Interrupts that you probably have never seen before. This type of interrupt
uses Interrupt Mode Zero (aOaO) to jam an instruction into the zao. This
instruction is a LD A,A. This instruction is jammed onto the bus through
the CPU Vector Interrupt Socket Pin a (bit 7). When CPU Interrupts are
enabled, pulling down one of the Vector lines causes an Interrupt to occur.
When the zaO acknowledges the interrupt, a Vector of 177Q or 7FH is jammed
onto the bus.
In Interrupt Mode Zero,
this Vector is taken as an
instruction and is executed by the CPU as if this instruction was fetched
from memory.
After execution, the program counter is incremented as in any
instruction, and normal processing continues.
In the Digital Group Double Density Controller Software for reading or
writing a sector, this interrupt scheme is used. When the controller board
needs to read or write a sector:
1. Controller Board interrupts are enabled.
2. Read or Write command is issued.
3. CPU Mode Zero Interrupts are enabled.
4. Halt instruction executed. (Refresh working)
5. Controller Board issues an Interrupt.
6. The LD
A,A instruction executed instead of Halt.
7. Read or Write data is done using Wait logic.
a.
Controller Board interrupts disabled.
9. Software returns to calling program.
-
45 -
DOUBLE DENSITY SYSTEM MANUAL
CHAPTER 5: 1791 PRODUCT SPECIFICATION
CHAPTER 5
1791 PRODUCT SPECIFICATION
5.1
INTRODUCTION TO WD1791 PRODUCT SPECIFICATION
We should review some of the curcuitry of the controller board
reading the 1791 Product Specification.
before
The 1791 IC is equivalent in architecture to many of the microprocessors
in use today.
It has a fixed instruction set and executes instructions as
they are given to it. These instructions take longer to execute than a
normal microprocessor instruction, but these instructions are more powerfull
than most microprocessor instructions.
When an Instruction is given,
the
1791 resets the INTRQ flag (if set) and then sets its busy flag.
Upon
completion of the instruction, the 1791 resets its busy flag and then sets
the INTRQ flag.
This latter flag is available for testing as the top bit in
the SEL Port.
It is STRONGLY recommended that the software test the INTRQ
bit while waiting for instruction completion.
Each instruction has a
functions.
These are :
field in that instruction that
performs specific
1. Load the head at the start of the operation.
~~'--IJ\d\t)....\lI.-J'-.~
"-~ VV''b'(
}6~
10 , ~
V ~\~}
2. Verify for the correct track when done.
~
~
1I"vfA' 4.
/l
~,
tt'" ~ \,} t~Y'
3. Update the internal track register when done.
,.,\~c;v~
- ~t:,r~\ ~
J
,} J IJ
S t epa t asp e c i f i c rat e •
'}i \~\ J~
Read or Write multiple sectors.
I
".}
. \t' \~o
I
&:-..{
J\
6. Write with Deleted or Regular Address Mark.
7. 15 millisecond delay or not.
'\
\I
I' .
(
'>
\~
J'
'\..'l
Ir ~\~
~
\
~
t::
..~
(i
\
'/~) G-\\
~
~JJ.f
I
~ ~'-~~\l''" /r(),:"
' ')
-.. , ,"---" "l
With the hardware configuration of the Digital Group Double Density.~
Controller Board one of these optional bits is NO LONGER OPTIONAL. The Head ~
load bit in all Step, Seek and Restore Instructions MUST be SET. One of the
conditions for drive select in the hardware is that the head must be loaded.
Also some of the bits have to be used correctly.
these bits and how they should be used.
Here is a summary of
The Verify bit should be used at the users option.
It verifys the
position of the head after a Seek, Step or Restore by reading the first ID
field it encounters on the Track.
UNDER NO CIRCUMSTANCES should the user
- 46 -
DOUBLE DENSITY SYSTEM MANUAL
CHAPTER 5: 1791 PRODUCT SPECIFICATION
have the verify bit ON during a DISK FORMAT operation. It should also be
noted here that on a Seek, Step or Restore Instruction that had the Verify
bit RESET,
no step settle time is added to the Instruction.
That is, the
user must now wait the drive manufacturers specified Step Settle Time BEFORE
issuing a Read Sector or Write Sector Instruction.
The Update bit is used to increment/decrement the Track register in the
1791. Presently no software provided by the Digital Group uses this bit.
All Stepping operations are done with the Seek Instruction and this
Instruction automaticlly updates the Track Register.
The Step Rate bits are used to set the step rate to one of four available
rates. These bits should be set closest (equal or above) to the drive
manufacturers specified step rates.
The Read or Write Multiple Sector bit allows the user to read or write
entire tracks of data to/from memory with only one Instruction. This bit is
not presently used in any of the Digital Group software. It is recommended
that the user NOT try this option until he has MASTERED the theory behind
the Interrupt/Halt data transfer scheme used in the software.
The Write with
bit is fine for
concerned.
Deleted Data Mark bit should always be set to zero.
This
IBM but it serves no usefull purpose as far as we are
Another bit that should always be set to zero is the 15 millisecond delay
bit.
This bit is left over from the 1771 IC and since then the Read and
Write Sector flowcharts have changed.
If this bit is set, only one sector
per revolution can be read if you are reading sectors sequentially.
(See
the 1791 flowcharts for a better explanation.)
Other bits that have not been implemented in the Digital Group software
are Interrupt Instruction bits 0 through 3. The user might find a use for
these bits after he becomes familiar with the system. We recommend that the
Interrupt Instruction be executed with all these bits off.
A brief explanation of the 1791 internal registers is also in order.
The first register is the Command/Status Register.
This is the register
that all Instructions are written to and all Status is read from.
Reading
this register resets the INTRQ bit in the SEL Port. Since this bit is used
to generate CPU Interrupts it is recommended that all software read the
status register after command completion to clear the INTRQ bit whether or
not the status is needed.
The second register is the Current Track Register.
This register should
only be written to when changing drives.
It can be read at any time to see
what Track the head is presently under.
The third register is the Requested Sector Register.
This register
should be loaded with the desired Sector prior to the issuance of a Read or
Write Sector Instruction.
- 47 -
DOUBLE DENSITY SYSTEM MANUAL
CHAPTER 5: 1791 PRODUCT SPECIFICATION
The fourth register is the Data Register.
This register is used to hold
the requested Track during a Seek Instruction. It could also be used for
read or write data bytes during Read or Write Sector Instructions.
The way
the hardware of the Digital Group Double Density Controller is setup, this
data transfer operation will be done through the Wait Port which is actually
this register but with wait states added.
Keep this
information
Specification Section.
in
mind
when
- 48 -
you
read
the
1791
Product
DOUBLE DENSITY SYSTEM MANUAL
5.2
CHAPTER 5: 1791 PRODUCT SPECIFICATION
1791 PRODUCT SPECIFICATION
- 49 -
DOUBLE DENSITY SYSTEM MANUAL
CHAPTER 6: SAMPLE DRIVER PROGRAM
CHAPTER 6
SAMPLE DRIVER PROGRAM
6.1
INTRODUCTION
The Digital Group Double Density Disc Controller Sample Driver has three
entry points used by the calling program.
The INITialization routine (INIT) fills the Drive Attribute Table and
restores all drives that are present to Track O.
This routine should be
called upon powerup and whenever a Drive Attribute change is made.
In DISKMON V3.00, INIT
through location 340 000.
is called
every time
the
system is restarted
In OASIS V5.3D,
a variation of this routine reinitializes only the drive
specified in a tMOUNTt or tATTACHt Command.
You can assume that the INIT Routine destroys all registers.
The Read Block(s) Routine (DSKRD) reads a specified number of blocks
starting at the START BLOCK into memory. On entry the registers should be:
A=
BC=
DE=
HL=
UNIT NUMBER
BLOCK COUNT (256 Bytes/Block)
START BLOCK (0 through Maximum-1)
START BUFFER ADDRESS
On a good read the registers are:
A=
BC=
DE=
HL=
On
a
0 (Zero Flag=1)
UNKNOvlN
LAST TRACK AND SECTOR READ
START BUFFER ADDRESS
bad read the registers are:
A=
BC=
DE=
HL=
ERROR CODE (Zero Flag=O)
UNKNOWN
TRACK AND SECTOR OF ERROR (For errors 3-6)
START BUFFER ADDRESS
The Write Block(s) routine (DSKWRT) uses the same parameters as the Read
Block(s) routine EXCEPT the direction of data is reversed.
The error codes returned to the calling program are as follows:
- 50 -
DOUBLE DENSITY SYSTEM MANUAL
CHAPTER 6: SAMPLE DRIVER PROGRAM
1. DRIVE NUMBER TOO LARGE
2. DRIVE NOT PRESENT
3.
4.
5.
6.
SEEK ERROR
BAD TRACK NUMBER
READ ERROR
WRITE ERROR
The user can get more information from the controller Status port on a
Read or Write Error.
If a Read or Write error occurs, the user should read
the controller status register if he needs more information.
The typical
errors read from the Status register are:
2XX
004
006
010
020
030
=
=
=
=
=
=
DRIVE NOT READY
DATA TRANSFER ERROR
DATA TRANSFER ERROR
DATA CRC ERROR
RECORD NOT FOUND
ID FIELD CRC ERROR
Any others signify
such.
6.2
controller hardware problems and should
be expressed as
SAMPLE DRIVER CODE
1;
2;
3;
4;
5;
6;
7;
8;
9;
10;
11;
Sample Driver for the Digital Group Double Dens
Controller using the LD A,A Interrupt Scheme.
(C) 1979 by The Digital Group
Written by Larry Williams
Last Revision 04/11/79
MAIN READ/WRITE LOOP
12;
13;
14;
15;
16;
17;
18;
19 ;
20;
21 ;
0000
0001
0003
0005
0006
0007
F5
F680
1802
F5
97
32F501
22 DSKWRT:
23
24
25 DSKRD:
26
27 RDvl RA:
output:
input:
AF=
BC=
DE=
HL=
PUSH
OR
JR
PUSH
SUB
LD
Unit Number
Block Count
Start Block
Buffer Start
AF
200Q
RDWRA
AF
A
(RDWR),A
- 51 -
error output:
AF=O Z=1
AF= ERR CODE
BC= Destroyed
DE= Last Tr/Se
HL= Buffer Start
Save the Unit Number
Set top bit for Write
Go around read entry Point
Save the Unit Number
get zero for read
Save the Read/Write Flag
Z=
DOUBLE DENSITY SYSTEM MANUAL
OOOA
OOOB
OOOD
OOOE
0010
0014
0015
0016
0017
0018
001B
001D
0020
0022
0023
0024
0027
0028
0029
002C
002E
002F
0032
0034
0035
0036
0037
0038
0039
003B
003E
0040
0041
F3
ED46
F1
DDE5
DD2AF301
E5
EB
50
59
CDBAOO
2028
CDOC01
2023
E3
D5
3AF501
07
F5
D46F01
2015
F1
DC9A01
2010
D1
E3
2B
7C
B5
280A
CD5A01
28DD
E3
1802
0043
0044
0045
0046
0048
0049
004B
004D
004F
0050
E1
D1
E1
DDE1
F5
DB2C
E66F
D32C
F1
C9
28
29
30
31
32
33
34
35
36
37
38
39 RDWRB:
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
6 1;
62;
63 ERROR3:
64· ERROR2:
65 ERROR1:
66
67
68
69
70
71
72
73;
74;
75;
76;
77;
78;
79;
CHAPTER 6: SAMPLE DRIVER PROGRAM
DI
IMO
POP AF
PUSH IX
LD I X, ( UNIT P. TR)
PUSH HL
EX
DE,HL
LD
D,B
LD
E,C
CALL SETUP
JR
NZ,ERROR1
CALL SEEK
JR
NZ,ERROR1
EX
(SP),HL
PUSH DE
LD
A,(RDWR)
RLCA
PUSH AF
CALL NC,READS
JR
NZ,ERROR3
POP AF
CALL C,WRITES
JR
NZ,ERROR2
POP DE
(SP),HL
EX
DEC HL
LD
A,H
OR
L
JR
Z,ERROR1
CALL INC SEC
JR
Z,RDWRB
(SP),HL
EX
JR
ERROR1
disable further interrupts
Set to 8080 type interrupt
Get the Unit Number back
Save IX in case used.
Get current unit pointer
Save Buffer address on stack
Get start Record Number to H
Upper half of Bolcks to D
Lower half of blocks to E
Select the unit convert Tr/S
Nonzero is a error
get to the right track
nonzero is error
get addr to HL blocks to (sp
Save Tracke and sectors
Get read/write flag
put bit 7 into carry
save flags
Read if no carry
error exit if nonzero
get flags back
it is write if carry
error exit if nonzero
get Track and sector back
trade blocks in HL for mem a
one less block
top half blocks to A
see if H=L=O
zero is OK no error exit
get the next sector number
no errors ,get another sector
get mem adr back to HL
error exit with nonzero
POP
POP
POP
POP
PUSH
IN
AND
OUT
POP
RET
get RDWR flag off stack
get Track and Sector back
get back real HL
and IX
save error code if any
get unit number
mask off interrupt en bit
disable board interrupts
get error code back if any
Go back to calling routine
HL
DE
HL
IX
AF
A,(SEL)
157 Q
(SEL),A
AF
INITIALIZE ROUTINE
- 52 -
DOUBLE DENSITY SYSTEM MANUAL
0051 0600
0053 DD21DA01
0051 DDE5
005·9 18
005A D32C
005C DB2C
005E CB51
0060 DD3605FF
0064 203D.
0066 CB6F
0068 2E80
006A 2002
006C 2EOO
006E DD1504
00111605
0013 211A4D
0016 CB61
0018 280B
001A 1604
001C 211228
001F CB5F
0081 2802
0083 2623
0085 DD1401
0088 CB5F
008A 2802
008C CB25
008E DD1500
0091 DD1102
0094 DD1203
0091 18
0098 F608
009A D32C
009C CDC501
009F DD360500
00A3 110600
00A6 DD19
00A8 04
00A9 CB50
OOAB 28AC
OOAD 91
OOAE 32F201
00B1 D32C
00B3 DDE1
00B5 DD22F301
00B9 C9
CHAPTER 6: SAMPLE DRIVER PROGRAM
80 ; This routine initializes all parameters in the Disc
81 ; Parameter table. It should be called upon powerup and any
82; time the user wishes to change Drive Attributes.
83;
84;
85 INIT:
start with drive 0
LD
B,O
first table entry
86
IX,DSO
LD
save it for later also
PUSH IX
81
get
drive number to A
88 INITA:
LD
A,B
SEL
)
,
A
(
OUT
select
that drive
89
get
Attributes
for that driv
A, ( S EL)
IN
90
see if Side came back zero
BIT 2,A
91
set no drive there to be sur
(IX+5),OFFH
92
LD
JR
NZ,INITX
of
came back one •.• no drive
93
Single Density? One=S.D.
BIT 5,A
94
L,128D
Single Density Sector length
LD
95
Brif
Single Density
96
NZ,INITB
JR
Double
Density Length (256)
L,O
LD
91
save
sector
length in table
(IX+4)
,
L
98 INITB:
LD
LD
D,STDSTEP
step rate for Standard Drive
99
100
Standard Tracks and Sectors
LD
HL,STDTRSE
101
BIT 4,A
See if Standard or Mini
zero
is Standard Drive
102
Z,INITC
JR
D, MIN STEP
step rate Mini Drive
LD
103
One Sided MINI Track and Sec
104
HL,MINI1SID
LD
see if 2 sided Mini
BIT 3,A
105
1 06
Brif only 1 Sided
JR
Z,INITC
LD
2 sided Mini is Different
H,MINI2SID
101
108 INITC:
Save Number of Tracks
(IX+1),H
LD
Check for 2 sided again
BIT 3,A
109
110
1 sided branches
JR
Z,INITD
SLA L
double sectors for 2 sided
111
save maximum Sectors
11 2 INI TD :
LD
(IX+O),L
LD
(IX+2),A
Save copy of Attribute Bits
113
114
Save step rate
LD
(IX+3),D
LD
115 INITR:
A,B
get Unit number back in A
or in the drive change bit
116
OR
DRICHG
select the drive again
OUT ( SEL) , A
111
Get this drive to Track Zero
118
CALL RESTORE
set current track to zero
LD
(IX+5) ,0
119
the table increment
120 INITX:
LD
DE,6
add in the increment
1 21
ADD IX,DE
get to next drive
122
INC B
got to four yet ?
BIT 2,B
1 23
no go test another
124
Z,INITA
JR
get a zero in A
SUB A
125
set current unit as zero
1 26
(UNIT),A
LD
make sure controller matches
OUT ( SEL) ,A
121
get DSO pointer back
1 28
POP IX
save current unit pointer
LD (UNITPTR) , IX
1 29
done initializing all avail
RET
130
131 ;
- 53 -
DOUBLE DENSITY SYSTEM MANUAL
CHAPTER 6: SAMPLE DRIVER PROGRAM,
132 ;
133 ;
134 ;
SETUP ROUTINE
135 ;
136 ; This routine checks drive validity first, then changes
137 ; drives if requir~d. Lastly, it converts block number and
138 ; start block to number of sectors and startng sector.
139 ;
140 ;
14 1 ;
OOBA
OOBC
OOBE
OOCO
00C1
00C2
00C3
00C6
00C7
00C9
OOCA
OOCB
OOCD
OOCF
00D1
00D5
00D8
00D9
OODB
OODC
OODE
OODF
00E3
00E6
00E8
00E9
OOEB
OOED
OOEE
OOEF
OOFO
00F1
00F5
00F7
00F8
00F9
OOFA
OOFB
OOFC
OOFD
0100
0102
FE04
3804
3E01
B7
C9
E5
21F201
BE
2816
D5
77
F608
D32C
E603
DD21D401
110600
3C
DD19
3D
20FB
D1
DD22F301
DD7E05
D329
3C
2005
3E02
B7
E1
C9
E1
DDCB026E
2804
29
EB
29
EB
97
47
DD4EOO
ED42
3C
142
1 43
144
145
146
147
148
149
150
1 51
152
1 53
154
155
156
1 57
158
159
160
16 1
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
1 80
1 81
182
1 83
SETUP:
SETUPA:
SETUPB:
SETUPC:
SETUPD:
SETUPE:
DIVIDE:
CP
4
JR
C,SETUPA
LD
A, 1
OR
A
RET
PUSH HL
LD
HL,UNIT
(HL)
CP
JR
Z,SETUPC
PUSH DE
( HL) , A
LD
OR
DRICHG
OUT ( SEL ) , A
AND 3
LD
IX,DSO-6
LD
DE,6
INC A
ADD IX,DE
DEC A
JR
NZ,SETUPB
POP DE
LD (UNITPTR),IX
LD
A,(IX+5)
OUT (TRACK),A
INC A
JR
NZ,SETUPD
LD
A,2
OR
A
POP HL
RET
POP HL
BIT 5,(IX+2)
JR
Z,SETUPE
ADD HL,HL
DE,HL
EX
ADD HL,HL
DE,HL
EX
SUB A
LD
B,A
LD
C,(IX+O)
SBC HL,BC
INC A
- 54 -
see if valid drive
carry is ok
INVALID DRIVE NUMBER
set nonzero
go back with error
save start record
see if same drive
zero is same drive
don't mess with unitptr
save blocks for a moment
save new unit number
or in the drive change bit
change the controller to new
get back fresh unit number
table base address less 6
table increment
for once thru the loop for s
add in the table increment
for each unit number
not done until unit is zero
get blocks back
current unit ptr
get current track for this u
update the controller
see if was OFFH
unit is there branch
NO DRIVE PRESENT
set nonzero
get start record back
go back with error
get starting block back
see if double density
if double no add needed
double start block for secto
swap around
double blocks for sectors
get back in order
get a zero
into B also
get number od sectors
divide start block by sector
new track
DOUBLE DENSITY SYSTEM MANUAL
0103
0105
0106
0107
0108
0109
010A
30FB
09
3D
2C
67
EB
1858
1 84
1 85
186
187
188
189
190
1 91 ;
CHAPTER 6: SAMPLE DRIVER PROGRAM
JR
ADD
DEC
INC
LD
EX
JR
NC,DIVIDE
HL,BC
A
L
H,A
DE,HL
SETUPX
not done until overfolw
get remainder back
for extra time thru loop
sectors start at one
track to H
put trlse in DE blocks in HL
setup exit code shared by ot
192;
193 ;
194 ;
SEEK ROUTINE
195 ;
196 ;
197 ; The seek routine gets the head of the selected drive to
198; the correct track. It then performs the logical to
199 ; physical sector mapping if 2 sided.
200;
201 ;
010C
010E
010F
0111
0115
0116
0118
011B
011D
011F
0121
0122
012!l
0126
0128
012A
012C
012E
012F
0130
0133
0135
0139
013A
013C
013E
01111
0142
0143
0145
0111-6
0147
0148
DB29
BA
2824
ED4BF501
7A
D32B
DD7E03
F618
D328
DB2C
87
30FB
DB28
E6 1 8
280B
3E03
1002
B7
C9
CDC501
18EO
DDCB025E
4B
0680
280D
DD7EOO
OF
BB
3006
4F
7B
91
4F
202;
203 SEEK:
204
205
206
207 SEEKA:
208
209
IN
CP
JR
LD
LD
OUT
LD
210
OR
211
212 SEEKB:
OUT
IN
ADD
JR
IN
AND
JR
LD
DJNZ
OR
RET
CALL
JR
BIT
LD
LD
JR
LD
RRCA
CP
JR
LD
LD
SUB
LD
213
214
215
216
217
218
219
220
221
222 SEEKC:
223
224 SEEKD:
225
226
227
228
229
230
231
232
233
234
235
A,(TRACK)
D
Z,SEEKD
BC,(RTRY-1)
A,D
(DATA),A
A,(IX+3)
SEEKCOM
(CMND),A
A,(SEL)
A
NC,SEEKB
A,(STAT)
SEEKMASK
Z,SEEKD
A,3
SEEKC
A
RESTORE
SEEKA
3,(IX+2)
C,E
B,BOTMASK
Z,NOTTOP
A,(IX+O)
E
NC,NOTTOP
C,A
A,E
C
C,A
- 55 -
Get current track
same as requested ?
Brif same
get retry count into B
get requested track to A
put to controller
get the step rate
or in the seek command
issue seek command
wait for completion (bit 7)
into carry
not done if no carry
get status of completed seek
mask only wanted bits
zero is good seek
SEEK ERROR
go to seekc if retrys left
set nonzero
nonzero error exit
get home for reference
try allover again
see if 2 sided
put sector in C
interrupt and side mask in B
Brif NOT 2 sided
get maximum sectors
divide them by 2
still on bottom?
if no carry still on bottom
save dividing line for toplb
get oversized sector in A
subtract dividing line secto
put new sector in C
DOUBLE DENSITY SYSTEM MANUAL
0149
014B
014D
014F
0150
0152
0153
0155
015,8
0159
0684
DB2C
E603
BO
D32C
79
D32A
DD7205
97
C9
015A DD7EOO
015D 1C
015E 93
015F 30F7
01611E01
0163 14
0164 DD7E01
0167 3D
0168 92
0169 30ED
016 B 3 EO 4
016D B7
016 E C9
016F ED5BF601
CHAPTER 6: SAMPLE DRIVER PROGRAM
B,TOPMASK
LD
interrupt and new side mask
236
A,(SEL)
IN
get unit number in A
237 NOTTOP:
AND 3
238
mask unwanted bits
OR
B
or in interrupt and side inf
239
OUT (SEL),A
enable interrupts and put si
240
get the sector number
LD
A,C
241
OUT (SECTOR),A
to controller
242
( IX+5) , D
save new current track numbe
LD
243
244 SEEKXA:
SUB A
get a zero
RET
shared return code
245
246 ;
247;
248;
INCREMENT SECTOR ROUTINE
249;
250;
251 ;
252; The increment sector routine bumps the sector by one and
253; checks for overflow. If overflow exists, track is
254; incremented and then checked for out of bounds.
255;
256 ;
257;
A,(IX+O)
get maximum sectors to A
258 INCSEC:
LD
for next sector
INC E
259
SUB E
(max sector-sector)
260
good number exit with a zero
NC,SEEKXA
JR
261
bumped past start this 1 aga
E,1
262
LD
INC D
next track
263 INCSED:
264 SETU PX:
A,(IX+1)
get max tracks
LD
DEC A
for 0 to max-1 not 1 to max
265
SUB D
see if overflow
266
NC,SEEKXA
good number exit with a zero
JR
267
268
LD
A,4
BAD TRACK NUMBER
set nonzero
OR
A
269
RET
return from INCSEC or SETUP
270
271 ;
272;
273;
READ SINGLE SECTOR ROUTINE
274;
275;
276; The read single sector routine reads a single sector and
277; then returns. Based on the following:
278;
output: error output:
input:
279;
AF=
don't
Care
AF=O
Z=1
AF=err Z=O
280;
BC:
"Destroyed
BC=
don't
Care
281 ;
DE= Tr/Se
DE= Tr/Se
282;
HL= buffer+lengh HL= buffer ad
HL=
buffer
addr
283;
284;
285;
286;
get retry count to E
DE,(RTRY)
LD
287 READS:
- 56 -
CHAPTER 6: SAMPLE DRIVER PROGRAM
DOUBLE DENSITY SYSTEM MANUAL
0173 E5
0174 3E88
0176 D328
0178 OE2F
017A DD4604
017D FB
017E 76
017F EDB2
0181 DB2C
0183 87
0184 3802
018610F9
0188 DB28
018A E69F
018C 2808
018E 1D
018F E1
019020E1
0192 3E05
0194 B7
0195 C9
0196
0197
0198
0199
E3
E1
97
C9
288 READA:
289
290
291
292
293 READB:
294
295
296 READC:
297
298
299
300 READD:
301
302
303
304
305
306
307
308
309;
310 RDWRX:
311
312
313
314 ;
31 5 ;
316;
317;
PUSH
LD
OUT
LD
LD
EI
HALT
INIR
IN
ADD
JR
DJNZ
IN
AND
JR
DEC
POP
JR
LD
OR
RET
EX
POP
SUB
RET
HL
A, READ COM
(CMND),A
C,vlAIT
B,(IX+4)
A,(SEL)
A
C,READD
READC
A,(STAT)
READMASK
Z, RDvlRX
E
HL
NZ,READA
A,5
A
(SP) ,HL
HL
A
save buffer start address
get the read sector command
issue to controller
wait port number to C
sector length to B
enable interrupts
refresh until first byte rea
get all the bytes to memory
get completion flag (bit 7)
into carry
when done carry is one
wait only 256 times for flag
get read sector status
mask only wanted bits
if no errors use common exit
retry again ?
get start buffer address
if nonzero retry
READ ERROR
get nonzero
go back with error
swap buffer+length for buffe
get incremented in HL
get a zero
return from READS or WRITES
WRITE SINGLE SECTOR ROUTINE
318 ;
019A
019E
019F
01A1
01A3
01A5
01A8
01A9
01AA
01AC
01AD
01AE
01BO
01B2
01B3
01B5
01B7
ED5BF601
E5
3EA8
D328
OE2F
DD4604
FB
76
EDA3
FB
76
EDB3
DB2C
87
3802
10F9
DB28
319; The Write single sector routine uses the same structure
320; as the read sector routine.
321 ;
322;
get retry count to E
DE,(RTRY)
LD
323 WRITES:
save start buffer address
PUSH HL
324 WRITEA:
get
the write sector command
A,WRITECOM
LD
325
issue
it to the controller
(CMND),A
OUT
326
get
the
wait port to C
LD
C,WAIT
327
get
the
sector length
B,(IX+4)
LD
328
enable
interrupts
EI
329 WRITEB:
•
refresh until first byte nee
HALT
330
put the first byte
OUTI
331
enable
interrupts again
EI
332
refresh
until rest needed
HALT
333
write
the
rest of the sector
OTIR
334
wait
for
crc
write
A,(SEL)
IN
335 WRITEC:
completion
flag
into carry
ADD
A
336
if
complete
Branch
C,WRITED
JR
337
only wait 256 for completion
DJNZ WRITEC
338
get write sector status
A,(STAT)
IN
339 WRITED:
- 57 -
DOUBLE DENSITY SYST!M MANUAL
01B9
01BB
01 BD
01BE
01BF
01C1
01C3
01C4
E69F
28D9
1D
E1
20DD
3E06
B7
C9
01C5
01c8
01CA
01CC
01CE
01DO
01D1
01D3
01D7
01D9
DD7E03
E603
F608
D328
DB2C
87
30FB
DD360500
DB28
C9
01DA
01DB
01DC
01DD
01DE
01DF
01EO
01E6
01EC
00
00
00
00
00
FF
00000000
00000000
00000000
01F2 00
01F3 DA01
01F5 00
01F6 0200
CHAPTER 6: SAMPLE DRIVER PROGRAM
AND WRITMASK
340
mask only wanted bits
JR
Z,RDWRX
341
if zero no errors use com ex
DEC E
342
retry again ?
POP HL
get start buffer address
343
JR
NZ,WRITEA
344
no try again
LD
A,6
WRITE ERROR
345
OR
A
se t nonzero
346
go back with error
RET
347
348;
349;
350;
RESTORE ROUTINE
351 ;
352;
353; This routine gets the selected drive back to track zero.
354; It also updates the current track pointer.
355;
356;
Get the step rate
357 RESTORE: LD
A,(IX+3)
AND 3
remove the verify bit if set
358
OR
RESTCOM
or in the restore command
359
OUT (CMND),A
360
issue the restore to control
361 RESTA:
A,(SEL)
IN
get completion bit
ADD A
into carry
362
JR
NC,RESTA
not done until carry
363
update the current track poi
LD
(IX+5),O
364
A,(STAT)
IN
read to clear the completion
365
RET
just return no error checkin
366
367;
368;
369;
DRIVE PARAMETER TABLES
370;
371 ;
372;
373;
DC
374 DSO:
MAXIMUM SECTOR
DRIVE
DC
375
MAXIMUM TRACK
DRIVE
DC
376
ATTRIBUTE FLAGS DRIVE
DC
377
STEP RATE
DRIVE
DC
378
SECTOR LENGTH
DRIVE
DC
OFFH
, CURRENT TRACK
379
DRIVE
DC
380 DS1:
O,O,O,O,O,OFFH ; DRIVE 1
DC
O,O,O,O,O,OFFH ; DRIVE 2
381 DS2:
DC
O,O,O,O,O,OFFH ; DRIVE 3
382 DS3:
383;
CURRENT UNIT NUMBER
384 UNIT:
DC
(D
SO)
CURRENT UNIT TABLE POINTER
385 UNITPTR: DC
386 ;
READ/WRITE COMMAND STORAGE
DC
387 RDWR:
( 2)
RETRY COUNT
DC
388 RTRY:
389;
390;
°°°
°
°
°°°
°°
°
°
°
391 ;
- 58 -
DOUBLE DENSITY SYSTEM MANUAL
0028
0028
0028
0029
002A
002B
002C
002F
4D1A
2812
0023
0018
0008
0088
OOA8
009F
009F
0018
0005
0004
0008
0080
0084
0000
392;
393;
394;
395;
396 PORT:
397 STAT:
398 CMND:
399 TRACK:
400 SECTOR:
401 DATA:
402 SEL:
403 WAIT:
404 STDTRSE:
405 MIN 11 SID:
406 MINI2SID:
407 SEEKCOM:
4 0 8 RES TC0 l1 :
409 READCOM:
410 WRITECOM:
411 READMASK:
412 WRITMASK:
413 SEEKMASK
414 STDSTEP:
415 MINSTEP:
416 DRICHG:
417 BOTMASK:
418 TOPMASK:
419
CHAPTER 6: SAMPLE DRIVER PROGRAM
SYSTEM EQUATES
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
END
050Q
PORT
PORT
PORT+1
PORT+2
PORT+3
PORT+4
PORT+7
77*256+26
40*256+18
35
030Q
010Q
210Q
250Q
237Q
237Q
030Q
5
4
10 Q
200Q
204Q
BASE ADDRESS OF CONTROLLER
CONTROLLER STATUS PORT
CONTROLLER COMMAND PORT
CONTROLER CURRENT TRACK PORT
CONTROLLER REQUESTED SECTOR
CONTROLLER DATA PORT
SELECT AND STATUS PORT
CONTROLLER WAIT DATA PORT
STANDARD TRACKS AND SECTORS
MINI 1SIDED TRACK AND SECTOR
MINI 2SIDED TRACKS
CONTROLLER SEEK COMMAND
CONTROLLER RESTORE COMMAND
CONTROLLER READ SECTOR COMMA
CONTROLLER WRITE SECTOR COMM
CONTROLLER READ ERROR MASK
CONTROLLER WRITE ERROR MASK
CONTROLLER SEEK ERROR' MASK
STANDARD DRIVE STEP RATE
MINI DRIVE STEP RATE (MPI)
DRIVE CHANGE BIT
INTERRUPT ENABLE AND BOTTOM
INTERRUPT ENABLE AND TOP MAS
thats all folks
- 59 -
DOUBLE DENSITY SYSTEM MANUAL
CHAPTER 7: SAMPLE FORMAT PROGRAM
CHAPTER 7
SAMPLE FORMAT PROGRAM
7.1
INTRODUCTION
The Format Program is a callable Subroutine that formats a diskette.
On
entry the accumulator contains the drive number (0-3).
No prompt message is
given to avoid clobbering drive O. There is no error exit and the Format
routine assumes that the calling program has verified that the drive
actually exists.
A track is formatted by first arranging all the bytes for that track in
first.
~his
includes all Gap, ID, and Data Fields.
The track is
then written to the disc during a single revolution.
m~mory
For Double Density Standard drives, this track buffer is 11K bytes long.
Therefore,
to run the Format Program,
the user requires at least 11.25K
bytes of continuous memory PLUS whatever memory the calling program
requires.
The Format Program for DISKMON V3.00 is the same as the sample Format
Program except that there is a front end for swap messages for drive zero.
The Format Program for OASIS V5.3D uses the same table driven formatter,
but is more extensive (more Bells and Whistles)
than the sample Format
Program.
7.2
FORMAT CODE
1
2 ;
3 ;Sample Format Program for the Digital Group
4 ;Double Density Controller Board
5 ,
6 ; (C) 1979 by The Digital Group
7 ,
8 ;Written by:
9 ;Larry Williams
10
11
12
0000
0002
0003
0005
0007
FE04
DO
F610
D32C
DB2C
13 FORMAT:
14
15
16
17
18
19
CP
RET
OR
OUT
IN
4
NC
DRICHG
( SEL ) , A
A,(SEL)
be sure its a valid drive
go back if GE 4
flip drive change bit
select the desired drive
get back the attributes
Mini INIT routine to find max tracks and sectors
20
- 60 -
DOUBLE DENSITY SYSTEM MANUAL
0009
OOOC
OOOE
0010
0013
0015
0017
0019
001C
001D
0020
0023
0025
0027
0029
002B
002C
002D
002E
002F
0030
0031
0034
0035
0036
0037
0038
0039
003A
003D
003F
0042
0043
0046
0047
004A
004D
001~
E
004F
0052
0053
0055
0056
0058
005B
005D
005F
0061
0062
0064
211 A4 D
CB67
2809
211228
CB5F
2802
2623
32DB01
2C
22D701
21DC01
E630
CB2F
CB2F
0600
4F
09
5E
23
56
EB
22D301
EB
23
5E
23
56
EB
22D501
ED62
22D901
EB
CDEDOO
D5
CD8 800
CDC COO
01
14
3A0801
BA
2811
7A
032B
320A01
3E1B
D328
DB2C
87
30FB
18EO
21 INIT:
22
23
24
25
26
27
28 INITA:
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
FORMC:
FORMD:
SEEK:
SEEKA:
CHAPTER 7: SAMPLE FORMAT PROGRAM
LD
BIT
JR
LO
BIT
JR
1.0
HL,STDTRSE
4,A
Z,INITA
HL,MINI1S1
3,A
Z,INITA
H,MINI2SI
(ATTR),A
LO
INC L
LD (NSECTS),HL
LO
HL,GAPTAB
AND 60Q
SRA A
SRA A
B,O
LD
C,A
LD
HL,BC
ADD
E , ( HL)
LD
INC HL
D , ( HL)
LD
EX
OE,HL
(TEMP2),HL
LD
DE,HL
EX
INC HL
E, ( HL)
LD
INC HL
LD
D,(HL)
OE,HL
EX
(TEMP1),HL
LD
SBC HL,HL
LD
(SIDE),HL
EX
DE,HL
CALL RESTORE
PUSH DE
CALL FORMIN
CALL WRITETR
POP DE
INC D
A,(NTRKS)
LD
CP
D
JR
Z,FORMX
A,D
LD
OUT (DATA),A
(TRACKS),A
LD
A,SEEKCOM
LD
OUT (CMND) , A
A,(SEL)
IN
ADD A
NC,SEEKA
JR
FORMD
JR
- 61 -
get standard track and sector
see if standard
Brif standard
get Mini 1sided track and sect
see if 2 sided
Brif 1 sided
tracks different for 2 sided
save the attributes
get one extra sector
save the tracks and sectors
get gaptable address's
mask only SID and MIS
divide by 2
divide by 2
get upper half to zero
get lower half from A
add in offset
get lower half of gaptab
for next
get upper half of gaptab
put gaptab in hI
save gaptab addr in temp2
get offset back in HL
for nex t
get lower half of sectab
for next
get upper half of sectab
sectab addr in HL
save sectab addr in temp1
get pair of zeros
zero side and track temps
get a zero to D
get this drive to track 0
save current track
format the buffer
write the buffer
get current track back
for next track
get maximum tracks
see if done
done with one side
get the new track
to controller
save it for formatting
slow seek with no verify
issue the command
wait for completion (bit 7)
into carry
no carry is not done
go for another track
DOUBLE DENSITY SYSTEM MANUAL
0066
0069
006A
006C
006F
0071
0073
0075
0077
0079
007B
007D
0080
0082
3AD901
B7
2018
3ADB01
CB5F
2811
DB2C
E603
F604
D32C
3E01
32D901
1600
18BF
0084 CDEDOO
0087 c9
CHAPTER 7: SAMPLE FORMAT PROGRAM
A,(SIDE)
see if just formatted top
LD
73 FORMX:
see if a one
OR
A
74
JR
NZ,FORMXX
if
one were all done
75
get
attributes again
LD
A,(ATTR)
76
BIT
see
if realy 2 sided
3,A
77
if
1
sided we have to be done
JR
Z,FORMXX
78
A,(SEL)
get
device
number
IN
79
mask
out
all
rest
AND
80
3
OR
81
or in top side
4
select top side
82
OUT (SEL),A
LD
new
side
A, 1
83
84
save it in the side temp
(SIDE),A
LD
start with track zero again
LD
D,O
85
FORMC
go restore and then format
86
JR
87
88
get the drive back to track 0
CALL RESTORE
89 FORHXX:
go back to calling program
RET
90
91
92
93 ,
94 ;Track data generation routine
95 ,
loop count
LD
C, 1
96 FORM IN:
get gaptab address
HL,(TENP2)
LD
97
the track format buffer
DE,BUFFER
LD
98
IY is the sectab pointer
IY,(TEMP1)
LD
99
put Gap4b into buffer
CALL PUT IT
100
save the start of sectors
PUSH HL
101 FORML:
put Gap3 into buffer
CALL PUTIT
102
103
Fill The ID field
104
105
get the current track number
A,(TRACKS)
106
LD
into buffer
(DE) , A
LD
1 07
for next
INC DE
108
get the current side number
A,(SIDE)
LD
1 09
into buffer
LD
(DE),A
11 0
for next
INC DE
111
get the mapped sector
A,(IY+O)
LD
11 2
(DE),A
into buffer
LD
113
for next sector
INC IY
114
for nex t
INC DE
115
put rest of ID and DATA field
CALL PUTIT
116
117
11 8
next sector
INC C
119
get max sectors+1
A,(NSECTS)
LD
120
same ?
CP
C
1 21
done with data field if zero
Z,FORMIX
JR
122
get pointer back to Gap3
POP HL
1 23
go for another sector
FORML
124
JR
.
.
0088
008A
008D
0090
0094
0097
0098
OE01
2AD301
11EC01
FD2AD501
CDBFOO
E5
CDBFOO
009B
009E
009F
00 AO
00A3
00 A4
00A5
00 A8
00A9
OOAB
OOAC
3ADA01
12
13
3 AD 901
12
13
FD7EOO
DOAF
OOBO
00B3
00B4
00 B6
00B7
OC
3AD701
B9
2803
12
FD23
13
CDBFOO
E1
18DE
- 62 -
CHAPTER 7: SAMPLE FORMAT PROGRAM
DOUBLE DENSITY SYSTEM MANUAL
00B9
OOBA
OOBB
OOBE
E3
E1
CDBFOO
C9
125 FORMIX:
1 26
127
1 28
1 29
130
1 31
132
EX
(SP),HL
POP HL
CALL PUTIT
RET
throwaway top entry on stack
like this
now format Gap4a to index hole
done with a track
Putit routine
133 ;Gets byte pairs from Gaptab. First byte is count
DOBF 46
23
00 co
OOC1
00C2
OOC3
OOC4
OOC5
00 C6
OOC7
OOC8
ooeA
aoee
ooeF
00D2
OOD5
OOD7
00D9
OODB
OODC
OODE
OOEO
OOE2
OOE3
OOE6
00E8
OOEg
OOEC
7E
23
80
C8
90
12
13
10FC
18F3
012FOO
21EC01
112BCO
3EF4
D328
DB2C
A2
28FB
EDA3
DB2C
A2
CAEOOO
EDB3
1D
C2E600
cg
134
135
136
137
138
139
140
1 41
142
1 43
144
145
146
147
148
149
150
1 51
152
1 53
154
155
1 56
157
158
159
160
161
162
163
164
165
166
167
168
169
170
;and second byte is value. If both are zero, stop.
PUTIT:
LD
INC
LD
INC
ADD
RET
B, ( HL)
HL
A,(HL)
HL
B
Z
get repeat count
for second byte
get value
for next
see if both zero
go back if both zero
restore value
start putting the value
for next
until B is zero
go for another byte pair
SUB
B
LOOPIT:
LD
INC
DJNZ
JR
(DE),A
DE
LOOPIT
PUTIT
,
Write Track routine
,
;Writes 11,00P bytes to drive whether or not the
;drive requires that many.
.,
WRITETR: LD
LD
LD
LD
OUT
WRITEA:
IN
AND
JR
OUTI
WRITEB:
IN
AND
JP
vlRI TEC:
OTIR
DEC
JP
RET
BC,WAIT
HL,BUFFER
DE,MASK
A,WTRKCOM
(CMND),A
A,(SEL)
D
Z,WRITEA
A,(SEL)
D
Z,WRITEB
E
NZ,WRITEC
wait port to C
where the data is
data ready mask and loop count
the write track command
issue to controller
wait for first byte
see if ready
wait until first is ready
put first byte
wait for the rest
fast check
faster that JR
put a bunch of bytes
256 times E
not done yet
put all bytes and then some
171
172
Restore routine
174
175
A,RESTCOM
176 RESTORE: LD
173
OOED 3EOB
- 63 -
restore command
DOUBLE DENSITY SYSTEM MANUAL
OOEF
OOF1
OOF3
OOF4
OOF6
OOF8
D328
DB2C
87
30FB
DB28
C9
OOF9
0103
010D
0117
OEFF0600
08FF0600
01F70BFF
01F70000
0121
012B
0135
013F
0149
1C4EOCOO
0000104E
00000101
03F501FB
004E004E
014F
0159
0163
016D
28FF0600
060001FE
OBFF0600
1BFFOOOO
0177
0181
018B
0195
019F
504EOCOO
OOOOOCOO
010101F7
01FB0040
004E004E
01A7 01020304
01B4 OEOF1011
01C1 010A020B
01CA OE060F07
01D3 0000
177
178
179
1 80
1 81
1 82
1 83
184
185
186
1 87
188
189
1 90
1 91
192
1 93
194
195
1 96
1 97
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
RESTA:
CHAPTER 7: SAMPLE FORMAT PROGRAM
OU T
IN
ADD
JR
IN
RET
,
( CMND) , A
A,(SEL)
A
NC,RESTA
A,(STAT)
to controller
wait for completion
into carry
not done yet
clear completion flag
go back
The Gap and Sector Tables
;All data following MUST be in this order I!!
,
NINI:
DC
DC
DC
DC
014,255,006,000,001,252,014,255,000,000
008,255,006,000,001,254,000,000,001,000
001,247,011,255,006,000,001,251,128,229
001,247,000,000,000,255,128,255,000,000
DC
DC
DC
DC
DC
028 , 078, 01 2 ,
003 ,246 , 001 ,252 , 028 , 078
000,000,016,078,008,000,003,245,001,254
000,000,001,001,001,247,022,078,012,000
003,245,001,251,000,064,001,247,000,000
000,078,000,078,000,000
STD:
DC
DC
DC
DC
040 , 255 , 006 , 0 0 , 001 , 252 , 026 , 255 ,
000
006,000,001,254,000,000,001,000,001,247
011,255,006,000,001,251,128,229,001,247
027,255,000,000,128,255,000,255,000,000
STDD:
DC
DC
DC
DC
DC
080,078,012,000,003,246,001,252,050,078
000,000,012,000,003,245,001,254,000,000
001,001,001,247,022,078,012,000,003,245
001,251,000,064,001,247,054,078,000,000
000,078,000,078,128,078,000,000
SECA:
DC
DC
01,02,03,04,05,06,07,08,09,10,11,12,13
1 4 , 1 5 , 1 6 , 1 7 , 1 8 , 1 9 , 2 21 , 22 , 23 , 24 , 25 , 26
DC
DC
01,10,02,11,03,12,04,13,05
14,06,15,07,16,08,17,09,18
,
NINID:
°°°,
,.
°
°°°,
°,
,
SECB:
MUST BE IN THIS ORDER
;
TEMP2 :
DC
; Gaptable pOinter
( 0)
- 64 -
-DOUBLE DENSITY SYSTEM MANUAL
01D5
01D7
01D8
01D9
01DA
01DB
0000
00
00
00
00
00
01DC 7701A701
01 E4 4F01A701
01EC
0028
0028
0028
002B
002C
002F
0010
4D1A
2812
0023
001B
OOOE
00F4
C02B
0000
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
CHAPTER 7: SAMPLE FORMAT PROGRAM
TEMP 1 :
NSECTS:
NTRKS:
SIDE
TRACKS:
ATTR:
DC
DC
DC
DC
DC
DC
( 0)
0
0
0
0
0
GAPTAB:
DC
DC
(STDD),(SECA),(MINID),(SECB)
(STD),(SECA),(MINI),(SECB)
EQU
$
Sec table pointer
max sectors+1
max tracks
side
current track
attribute bits
;
BUFFER:
; write buffer starts here
System equates
.,
PORT:
STAT:
CMND:
DATA:
SEL:
WAIT:
DRICHG:
STDTRSE:
HINI1SI:
NINI2SI:
SEEKCOM:
RESTCOM:
WTRKCON:
t-IASK:
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
END
050Q
PORT
PORT
PORT+3
PORT+4
PORT+7
20Q
77 *256 +26
40 * 256 +18
35
33Q
13Q
364Q
192*256 +43
- 65 -
controller base address
controller status port
controller command port
controller data port
select and side port
data wait port
drive change bit
standard track and sector
mini track and sector 1 sided
mini track 2 sided
seek slow no verify
restore slow no verify
write track command
wait mask and loop count
APPENDIX A
PARTS LIST BY VALUE
DIGITAL GROUP DOUBLE DENSITY DISK CONTROLLER PARTS LIST
LABEL
DESCRIPTION
QUANTITY
PART II
IC19
7400 quad 2-input NAND
74LSOO quad 2-input NAND
IC5
IC16
74LS02 quad 2-input NOR
IC27,30,46,49 7404 hex inverter
7406 hex inverter O.C.
IC21
IC15
74LS08 quad 2-input AND
IC23
7408 quad 2-input AND
IC17
74LS14 hex inverter S.T.
IC14
7420 dual 4-input NAND
IC36
74LS27 triple 3-input NOR
IC32,48
7430 eight input NAND
IC18,31
7432 quad 2-input OR
IC38,39,40
7438 quad 2-input NAND O.C.
IC33
7442 binary to decimal conv.
IC2,7,20,24,35 7474 dual D Flip Flop
IC45
7475 quad latch
IC6
7486 quad Exclusive OR
IC1,4,25
74123 Dual One Shot (TI)
74S124 Dual VCO (TI)
IC8
IC28
74139 dual 2 to 4 Demult.
IC11
74153 dual 4 to 1 Mult.
IC10
74161 Binary counter
IC41
74175 quad D Latch
IC12,13
74LS221 dual One Shot (TI)
IC44
81LS95/97 Octal Buffer
IC42,43
81LS96/98 Octal Buffer Inv.
IC37
74367
Hex buffer
IC34
LM3302 quad Comparitor
IC3
NE555 Timer
IC9
LM741 Op Amp
IC22
LM31B Op Amp
IC29
FD1791-1 Controller Ie
1
1
1
4
1
1
2
1
1
1
2
2
3
1
5
1
1
3
1
1
1
1
1
2
1
2
1
1
1
1
1
075-000
075-046
075-048
075-004
075-005
075-081
075-007
075-075
075-011
075-071
075-012
075-013
075-014
075-016
075-019
075-020
075-021
075-029
075-076
075-077
075-034
075-072
075-040
075-078
075-074
075-073
075-044
078-006
078-002
078-004
078-015
073-031
R42
R30,31
R12,13,14
R15,17
R22
R25
R33,37,49,50
R28,36,38
R9,18,19,20
R21,27,34,39
1
2
001-006
001-074
001-011
47 Ohm 1/4w Resistor
120 Ohm 1/4w Resistor
150 Ohm 1/4w Resistor
5
270 Ohm 1/4w Resistor
330 Ohm 1/4w Resistor
470 Ohm 1/4w Resistor
lK Ohm 1/4w Resistor
2.2K Ohm Resistor
1
1
4
3
8
-66-
001-015
001-016
001-018
001-025
001 -029
DOUBLE DENSITY SYSTEM MANUAL
LABEL
IC26
R7
R44,45
R29
R43
R46
R6 ,10
R4
R8
R23,24,32,40
R41 ,47,48
R5
R2
R11
R1
R3
R35
APPENDIX A: PARTS LIST BY VALUE
DESCRIPTION
2.2K
2.7K
3.3K
3.9K
4.7K
5.6K
6.8K
7.5K
9. 1 K
10K
Ohm
Ohm
Ohm
Ohm
Ohm
Ohm
Ohm
Ohm
Ohm
Ohm
QUANTITY
RPACK
1/4w Resistor
1/4w Resistor
1/4w Resistor
1/4w Resistor
1/4w Resistor
1/4w Resistor
1/4w Resistor
1/4w Resistor
1/4w Resistor
1
1
2
1
1
1
2
1
1
7
11K Ohm 1/4w Resistor
15K Ohm 1/4w Resistor
27K Ohm 1/4w Resistor
33K Ohm 1/4w Resistor
820K Ohm 1/4w Resistor
5K 10 Turn Trim-Pot
D1,3,4,5-20
D2
1
6
018-002
1
1
2
1
2
2
2
1
1
4
4
2
1
45
018-006
018-012
018-004
018-015
018-000
014-002
016-028
016-029
014-021
010-002
010-003
010-008
010-009
014-003
1
1N4148 Diode
1N4731A 4.3V Zener Diode
- 67 -
008-002
001-030
001-052
001-078
001-032
001-034
001-035
001-053
001-054
001-037
001-079
001-039
001-008
001-041
001-080
005-013
1
1
1
1
C10,11,12,13 50pf Silver Mica Capacitor
C14,34
C53
36pf Silver Mica Capacitor
C66
180pf Silver Mica Capacitor
C52,74
220pf Silver Mica Capacitor
C65
680pf Silver Mica Capacitor
C32,54
1000pf Silver Mica Capacitor
C70,73
.01uf Disc Capacitor
C49,50
.01uf 10% Mylar Capacitor
C48
.022uf 10% Mylar Capacitor
C15
.022uf 10% Disc Capacitor
C40,42,43,68 4.7uf Tantalum Capacitor
C9,61,62,71
10uf Tantalum Capacitor
C16,39
22uf Tantalum Capacitor
C72
100uf Tantalum Capacitor
C1-8,17-31,33
.1uf Disc Ceramic Capacitor
C35-38,41,44-47
C51 ,55-60,63,64
C67,69,75
PART II
10
1
040-006
040-025
DOUBLE DENSITY SYSTEM MANUAL
LABEL
APPENDIX A: PARTS LIST BY VALUE
DESCRIPTION
QUANTITY
PART II
X1
4.000 Mhz Crystal
030-011
L1
22uh Choke
055-004
8 Pin Socket
7
060-000
14 Pin Socket
27
060-001
16 Pin Socket
14
060-002
20 Pin Socket
3
060-013
40 Pin Socket
060-006
PC Board
090-078
1130 Wire
1124 Solid Wire
3'
1'
110-010
110-050
System Hanual
Installation Manual
Hmon/2 Users Manual
Hmon/2 Cassette
1
1
1
1
298-139
298-140
296-088
299-917
CPU MODIFICATION KIT
R7
D1,D2,D3
22K Ohm 1/4w Resistor
1N4148 Diode
1130 wire
1
3
2'
- 68 -
001-040
040-006
560-003
APPENDIX A
PARTS LIST BY LABEL
INTEGRATED CIRCUITS
LABEL
- -- ----IC1
IC2
IC3
IC4
IC5
IC6
IC7
IC8
IC9
IC10
IC 11
IC12
IC13
IC14
IC15
IC16
IC17
DESC
--- 74123
7474
NE555
74123
74LSOO
7486
7474
74S124
LM741
74161
74153
74LS221
74LS221
7420
74LS08
74LS02
74LS14
LABEL
...- --- -IC18
IC19
IC20
IC21
IC22
IC23
IC24
IC25
IC26
IC27
IC28
IC29
IC30
IC31
IC32
IC33
IC34
DESC
- - --
7432
7400
7474
7406
Ll1318
7408
7474
74123
2.2RP
7404
74139
1791-1
7404
7432
7430
7442
LM3302
LABEL
DESC
IC35
IC36
IC37
IC38
IC39
Ic40
IC41
IC42
IC43
IC44
IC45
IC46
IC47
IC48
IC49
7474
74LS27
74367
7438
7438
7438
74175
81LS96/98
81LS96/98
81LS95/97
7475
7404
NOT USED
7430
7404
---- - - ---
- - --
RESISTORS
LABEL
=====
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
DESC
- - -33K
15K
820K
7.5K
11 K
6.8K
2.7K
9. 1 K
2.2K
6.8K
27K
150
150
150
150
NOT USED
150
LABEL
- -- ----R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
R32
R33
R34
DESC
- - --
2.2K
2.2K
2.2K
2.2K
270
10K
10K
330
2.2RP
2.2K
1K
3.9K
120
120
10K
470
2.2K
LABEL
----- --R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
-69-
DESC
- - --
5K POT
1K
470
1K
2.2K
1 OK
10K
47
4.7K
3.3K
3.3K
5.6K
10K
1 OK
470
470
DOUBLE DENSITY SYSTEM MANUAL
APPENDIX B: PARTS LIST BY LABEL
CAPACITORS
LABEL
-- - ----C1
C2
C3
Cll
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
DESC
- - --
•1
•1
•1
•1
•1
•1
•1
•1
10
50
50
50
50
50
.022
22
•1
•1
•1
•1
•1
•1
•1
•1
•1
uf
uf
uf
uf
uf
uf
uf
uf
uf
pf
pf
pf
pf
pf
uf
uf
uf
uf
uf
uf
uf
uf
uf
uf
uf
LABEL
- --
------
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
C41
c42
C43
C44
C45
C46
C47
C48
C49
C50
DESC
---•1
•1
•1
•1
•1
•1
1000
•1
50
•1
•1
•1
•1
22
4.7
•1
4.7
4.7
•1
•1
•1
•1
.022
.01
.01
uf
uf
uf
uf
uf
uf
pf
uf
pf
uf
uf
uf
uf
uf
uf
uf
uf
uf
uf
uf
uf
uf
uf
uf
uf
LABEL
.. __ .... -
---- ..
C51
C52
C53
C54
C55
C56
C57
C58
C59
C60
C61
C62
C63
C64
C65
C66
C67
C68
C69
C70
C71
C72
C73
C74
C75
DESC
- _....
•1
220
36
1000
•1
•1
•1
•1
•1
•1
10
10
•1
•1
680
1 80
•1
4.7
•1
.01
10
100
.01
220
•1
uf
pf
pf
pf
uf
uf
uf
uf
uf
uf
uf
uf
uf
uf
pf
pf
uf
uf
uf
uf
uf
uf
uf
pf
uf
DIODES
LABEL
DESC
LABEL
DESC
LABEL
D1
D2
D3
D4
1N4148
1N4731A
1N4148
1N4148
D5
D6
D7
D8
1N4148
1N4148
1N4148
1N4148
D9
D10
- - - --
- - --
-- -- ---
- - --
------ ---
- 70 -
DESC
.. - _..
1N4148
1N4148
APPENDIX B: PARTS LIST BY LABEL
DOUBLE DENSITY SYSTEM MANUAL
IC SOCKETS
LABEL
-
----- ---
IC1
IC2
IC3
IC4
Ie5
IC6
IC7
IC8
IC9
IC10
IC11
IC12
IC13
IC14
IC15
IC16
IC17
IC18
DESC
- - --
16
14
8
16
14
14
14
16
8
16
16
16
16
14
14
14
14
14
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
LABEL
-----
IC19
IC20
IC21
IC22
IC23
IC24
IC25
IC26
IC27
IC28
IC29
IC30
IC31
IC32
IC33
IC34
IC35
IC36
DESC
----
14
14
14
8
14
14
16
16
14
16
40
14
14
14
16
14
14
14
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
LABEL
------ --IC37
IC38
IC39
IC40
IC41
IC42
IC43
IC44
IC45
IC46
IC47
IC48
IC49
,IC50
Ie51
IC52
IC53
MISC
LABEL
---------
DESC
----
X1
4.000 Mhz XTAL
L1
22 uh Choke
- 71 -
DESC
-
---
16
14
14
14
16
20
20
20
16
14
NOT
14
14
8
8
8
8
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
USED
Pin
Pin
Pin
Pin
Pin
Pin
DOUBLE DENSITY SYSTEM
~ANUAL
APPENDIX C: DRIVE ATTRIBUTE SOCKET DEFINITION
APPENDIX C
DRIVE ATTRIBUTE SOCKE·T DEFIN I TION
There are four 8 Pin Sockets for selecting drive attributes for the four
possible drives. The Sockets are numbered IC50, 51, 52, 53 on the Component
Placement Diagram.
On the Printed Circuit board, they are labeled 1, 2, 3,
and 4. The socket numbers correspond to drives DS1 through DS4.
The following table shows which diodes are to be installed for each
particular attribute. Diodes should be bent on .3" centers and then
installed with the band to the right.
(As viewed from the component side.)
BOARD LABEL
-----------
SCHEMATIC LABEL
---------------
DIODE
-----
NO DIODE
---------------
EN
A
DRIVE PRESENT
NO DRIVE
SD
B
SINGLE DENSITY
DOUBLE DENSITY
MS
C
MINI DRIVE
2S
D
2 SIDED
- 72 -
STANDARD DRIVE
1 SIDED
APPENDIX D: BOARD ADDRESSING
UBLE DENSITY SYSTEM MANUAL
APPENDIX D
BOARD ADDRESSING
The board is
addressed
by
jumpering
the
true or
address line A3-A7 to IC48 through jumper pads at IC47.
complement
of each
To select the base
address, first, write down the
binary equivalent for
each address bit
A3-A7.
Then place a jumper
in the true position for each
address line where
the binary value is a
one.
Next, place a jumper in the
complement position for each address line where the binary value was a zero.
Example:
To Select the Base address of 050Q:
A7
A6
o
o
A5
A4
A3
o
1
Then jumper: A5 and A3
true
Then jumper A7 A6 and A4 complement
This should look like the following:
Ie POSITION
47
20
/~TRUE~
A3
"'-O---COMPLEMENT
~
/~TRUE~
A4/
""0----
COMPLEMENT
/~
A5/
""C>-
~
TRUE----O
COMPLEMENT----o
~TRUE~
A6/'
""O----COMPLEMENT - - - - - 0
/~ TRUE-----<>
A7
""0-10
COMPLEMENT - - - - - 0
11
All Digital Group Software expects the Base Address of the Double Density
Controller board to be 050Q or 28H.
-
73 -
DOUBLE DENSITY SYSTEM MANUAL
APPENDIX E: ONE SHOT TIMINGS
APPENDIX E
ONE SHOT TIMINGS
The following is a table of the One Shot timings and their tolerance:
--
IC
R VALUE
-------------
--------------
C VALUE
IC1
R8 g. 1K
C74 220 pf
IC3
R3 820K
IC4
OUTPUT PIN
----------
TIME
TOL
- - --
---
13
800 ns
+-10%
cg 10uf
3
10 sec
+-20%
R1 33K
C72 100uf
12
1 sec
+-20%
IC4
R2 15K
C71 10 uf
4
35 ms
+-10%
IC12
R5 11K
C11 50 pf
4
450 ns
+-10%
IC12
R6 6.8K
C12 50 pf
5
250 ns
+-10%
IC13
R4 7.5K
C10 50 pf
4
300 ns
+-10%
IC13
R7 2.7K
C13 50 pf
12
150 ns
+-10%
IC25
R10 6.8K
C14 50 pf
5 , 12
200 ns
+-10%
IC25
R11 27K
C15 50 pf
4
160 us
+-20%
- 74 -
DOUBLE DENSITY SYSTEM MANUALAPPENDIX F: WRITE PRECOMPENSATION TIMING DIAGRAM
APPENDIX F
WRITE PRECOMPENSATION TIMING DIAGRAM
The following timing
shots IC12 and IC13.
diagram shows the relationship between the four one
WRITE PRECOMPENSATION
I E r - - - TIME Dependent on Drive type
Scale 770 ns/in
---~~(
IC30-6 WD
1~?9-17
Early
iC29-18 Late
IC16-4 Nom
IC13-12
Early-delayed
IC12-4
--- - - -
Late-delayed
IC13-4
Nom-delayed
:
IC14-6
IC12-5
WD-delayed
38-6 Wo-delayed
LJ
f
LJ
I
ON Precompensated
heoretical Write Data
f
W
~
I
r-r
I
I
Late 450 ns
or 150 ns
shift from nominal
Early 150 ns
or -150ns sh ift
from nominal
- 75 -
Nominal 300 ns shift
DOUBLE DENSITY SYSTEM MANUAL
APPENDIX G: WAIT LOGIC TIMING DIAGRAM
APPENDIX G
WAIT LOGIC TIMING DIAGRAM
The following
timing diagram shows the
logic, controller select, and the wait line.
relation~hip
between the wait
WAIT LOGIC
Scale 770 ns/in
160,us MAX
IC33-9 Seven
~--~-~~.-----------{ 1 - - - - - - - - - ...
~-
Ie 17-4 Seven
r---------[
f----------;
IC19-3 RW
r----------{
5----------< \---l~--+--..,
IC7-9 WAIT EN
IC2-5 CYC
IC23-11
IC36-12
IC20-52MHZ
RE or WE
IC37-13 WAIT
* ORO CAUSED
- 76 -
DOUBLE DENSITY SYSTEM MANUAL APPENDIX J: SOFTWARE COMPATIBILITY (OLD VS NEW)
APPENDIX J
SOFTWARE COMPATIBILITY (OLD VS NEW)
- 79 -
DOUBLE DENSITY SYSTEM MANUAL
APPENDIX K: APPLICATION NOTE #1
APPENDIX K
APPLICATION NOTE #1
USING INTERRUPTS
Care should be exercised when using interrupts simultaniously with the
Digital Group Double Density Controller Board.
If you are using interrupts, be sure that the circuits that can generate
these interrupts are disabled before entering the Disc Driver.
The High on
IC40 Pin 10 can be used to disable other board interrupts.
Also remember that the Disc Driver returns with interrupts
Interrupt Mode Zero selected.
disabled and
If you call the Disc Driver from numerous locations, it might be wise to
modify the Disc Driver to perform the other interrupt disables.
This can be
done by disabling the other interrupts just after the Disc Driver enables
its board interrupt.
Your reenable code should be placed after
the Disc
Driver disables its board interrupts.
- 80 -
~DOUBLE
DENSITY SYSTEM MANUAL
APPENDIX L: APPLICATION NOTE #2
APPENDIX L
APPLICATION NOTE #2
OPTIMIZING TIMING VALUES
The Digital Group Double Density Controller Board has some timings that
are a tradeoff between Standard and Mini Drives. These are the wait timeout
and the head load delay.
The Write Precompensation circuit is not needed if
the user is not going to be running Standard Double Density.
If you are going to run Mini Drives exclusivly, the Write Precompensation
circuit should be disabled. To do this:
1. Lift IC12 Pin 5 from its socket.
2. Jumper IC29 Pin 31 to IC38 Pin 5.
Also, if you are to run Mini Drives only,
to the manufacturers specs.
set the head load delay timer
If you are going to run Standard drives only, you should reduce the Wait
timeout timer. This can be done by using the procedures outlined in the
Testing Section. Set the Wait Timeout Timer to 2.5 times the slowest Byte
rate to be used.
- 81 -
DOUBLE DENSITY SYSTEM MANUAL
APPENDIX M: APPLICATION NOTE #3
APPENDIX M
APPLICATION NOTE #3
3 LOGICAL TO 2 PHYSICAL DRIVES
If you have a
two drive system and want to run the second drive in both
single and double density, this procedure might help.
Select the second drive as both DS2 and DS3.
This is done by placing a
black shorting plug on both DS2 and DS3 at
the drive.
Now,
on the
controller board,
Select drive DS2 as present and single density.
Select
drive DS3 as present and double density.
For Diskmon, you can operate the system by just
changing the drive number you use.
Example:
changing media and then
1.Have the Single density media in drive 1.
2. Perform a D#1 command.
3. Now place the double density media on drive 1.
4. Perform a D#2 command.
For OASIS, the above type logic also works but, after
the media, 'MOUNT' the new media every time.
- 82 -
you have changed
APPENDIX N: APPLICATION NOTE #4
DOUBLE DENSITY SYSTEM MANUAL
APPENDIX N
APPLICATION NOTE #4
MULTI HOLE DISKETTES
The Digital Group Double Density
single and multi-hole diskettes.
This can be accomplished
accordingly.
Controller Borad will operate on
by changing
the BOOIB01
jumper on your
both
drive
Should you forget to change from 800 to B01
some unusual things happen.
If
the controller is requested
to read or write a
sector and this sector
appears before 10 sector holes go by,
it
will read or write
it without
error.
But
if the
requested read
or write sector is farther
around the
diskette than 10 sector holes a RECORD NOT FOUND error is generated.
Therefore, if the
reliability of your system just changed, and
you are
switching between single and multi-hole diskettes, CHECK THE BOOIB01 JUMPER.
- B3 -
APPENDIX 0: APPLICATION NOTE #5
DOUBLE DENSITY SYSTEM MANUAL
APPENDIX 0
APPLICATION NOTE #5
BRINGING OUT THE DRIVE ATTRIBUTE DIODES
The Drive Attribute diodes may be brought out to an external set of
switches and diodes.
This is done by cutting in half a 16 pin header
socket.
Ribbon cable should be used to bring out
the desired attributes.
Maximum length of this cable can vary but, try to keep
the cable short.
Study the following schematic for construction tips:
Ribbon cable
EXTERNAL BOX
8 pin header
1N4148 (4)
Present (closed)
1
Single (closed)
Mint (closed)
2 Sided (closed)
Bringing out the drive attribute diodes
-
84 -
~DOUBLE
APPENDIX P: APPLICATION NOTE 16
DENSITY SYSTEM MANUAL
APPENDIX P
APPLICATION NOTE 16
USING MORE THAN 4 DRIVES
The Digital Group Double Density Controller was designed for only 4
drives. This can be modified to 8 drives by external circuitry. Expanding
to 8 drives isn't without sacrifice though, the user will loose the side bit
to get to 8 Drives.
The following schematic shows a typical method for
getting to 8 drives:
- 85 -
APPENDIX Q: APPLICATION NOTE #7
DOUBLE DENSITY SYSTEM MANUAL
APPENDIX Q
APPLICATION NOTE #7
2.5 MHZ VS 4 MHZ
At this
writing (4/79)
the Digital
Group does NOT support a
4 Mhz Z8D
System.
The Digital
Group Double Density Controller
board
has
been
thoroughly tested
at 4 Mhz.
It was found during this testing that the wait
logic release was too fast for 4 Mhz operation.
To fix this problem, 1/2 of
IC2
was
used
to
delay the
release
of wait
to meet 4 Mhz
operating
conditions.
To
operate
the
controller
board
at
4 Mhz
requires
the
following:
(1).
Cut the default jumper trace to the right of
IC2.
(2). Install a jumper wire to the other pad near
IC2.
It might be noted here that the present Dynamic Memory board will NOT run
at 4 Mhz due to insufficient T(ras) Precharge time during M1.
- 86 -
DOUBLE DENSITY SYSTEM MANUAL
APPENDIX R: APPLICATION NOTE #8
APPENDIX R
APPLICATION NOTE #8
DYNAMIC MEMORY AND REFRESH
The following is a table of the different refresh
different types of drives, during a sector data transfer.
and OTIR instructions):
DRIVE TYPE
----------
STANDARD DOUBLE DENSITY
REFRESH PULSES
----------------------------
2 per 16 us
'REFRESH RATE (1 28)
-----------------0.5 ms
STANDARD SINGLE DENSITY
2 per 32 us
1 .0 ms
MINI DOUBLE DENSITY
2 per 32 us
1 .0 ms
MINI SINGLE DENSITY
2 per 64 us
2.0 ms
----------
-------------_ _----------...
rates, for the
(using the INIR
-----~-----------------------------
Note that the Mini single density requires a full 2.0 ms to refresh all
128 columns. Some of the Digital Group Dynamic boards shipped prior to 3/79
had Integrated Circuits that did not meet the 2.0 ms refresh rate at all
temperatures.
If the user has a Dynamic Memory board with Fairchild 4027-7 IC's, AND
intends tp run Mini Standard Density, a memory test is in order.
Perform alternate memory writes, followed by heavy disc accesses, then
followed by memory reads 7 to verify the data written in the memory is still
valid.
Try this test at high temperatures. That is, a temperature that is
slightly above the temperature you expect your system to operate at
normally.
Note: We don't expect
of the situation.
you to have problems but,
- 87 -
we want you to be aware
DOUBLE DENSITY SYSTEM MANUAL
APPENDIX S: APPLICATION NOTE
#9~
APPENDIX S
APPLICATION NOTE #9
SHUGART DRIVE SYMMETRY ADJUST
If you experience an abnormal amount of read errors during double density
operation and your free running VCO is set properly (tol: +5% and -0%), your
drive might need a symmetry adjustment.
To perform the adjustment, you will need the following:
(1). HMON/2 Monitor
(2). 15 Mhz Triggered Sweep Oscilloscope
(3). Shugart Maintainance Manual
What we will be doing is alternately writing a pattern of all ones and
then all zeros onto the media. We will then check for bit jitter between
alternating bits.
The purpose is not to remove the jitter completely (would
be nice though) but to distribute the jitter equally between the one and the
zero patterns.
If you have any problems during this adjustment,
PLEASE
Digital Group Repair Department before continuing.
(You could
symmetry so bad that no reading is possible at all.)
Proceedure:
(1). Load HMON/2 and execute option 5.
(2). Place an "expendable" diskette in the drive to be
adjusted.
(3). Select the desired drive with the following:
(a). Execute: OUT-54,(drive number 0-3)
(cr)
(4). Get the selected drive to Track 76 by the following:
(a). Execute: TRK-114 (cr)
(b). Wait for the stepping to finish.
(c). Execute: Control C
- 88 -
consult the
mess up the
APPENDIX S: APPLICATION NOTE #9
DOUBLE DENSITY SYSTEM MANUAL
(5). Trigger the scope on the r1s1ng edge of test point
16. Also, observe the pattern on test point 16 for
all of the following. (Vert Amplitude 1V per cm)
(6 ) • The ONE Pattern:
( a) • Execute: ONE:TRK-114 (cr)
( b ) • Set sweep to 1us per cm.
( c) • Observe the jitter on 2nd and 4th pulses.
( d ) • Adjust R57 to minimumize the jitter.
( e ) • Execute: Control C.
( 7) . The ZERO Pattern:
( a) • Execute: ZER:TRK-114 (cr)
( b ) • Set sweep to 2us per cm.
( c ) • Observe the jitter on 2nd and 4th pulses.
( d ) • Adjust R57 to minimumize the jitter.
( e ) • Execute: Control C
(8). Repeat steps 6 and 7 alternately until the jitter is
eliminated completely or is evenly distributed
between the One and Zero Pattern.
(9). If you can't get the jitter below 300 ns,
consult the Digital Group Repair Department.
(10). Reformat the diskette as Track 76 is blown.
- 89 ..,
DOUBLE DENSITY SYSTEM MANUAL
APPENDIX T: APPLICATION NOTE #10
APPENDIX T
APPLICATION NOTE #10
INNOVEX DRIVES
It is unknown
density.
at
this
time
if
the Innovex
drive
will handle double
For single density though, the. Digital Group Double Density Controller
will operate with one modification.
The Controller board lacks the Track Greater that 43 Signal. It should
be noted that the Innovex drives lack the Side signal. To provide the TG43
signal to the Innovex drives, we must disable the Side logic to the drive
and enable the TG43 signal. Somewhat by choice, the side signal is present
on the very line that the Innovex requires the TG43 signal.
To switch
these, perform the following:
(1). Cut the trace
leadi~g
to IC40 Pin 13.
(2). Jumper the TG43 signal from IC29-29 to IC40-13.
This Modification removes the Side signal from Controller 36 Pin ed8
connector Pin 21 and in its place substitutes the TG43 signal.
- 90 -
WESTERN DIGITAL
c
o
R
P
o
R
T
A
o
/
N
FD1791A/B Floppy Disk Formatter/Controller
FEATURES
• SOFT SECTOR FORMAT COMPATIBILITY
• AUTOMATIC TRACK SEEK WITH VERIFICATION
• ACCOMMODATES SINGLE AND DOUBLE
DENSITY FORMATS
IBM 3740 Single Density (FM)
IBM System 34 Double Density (MFM)
• READ MODE
Single/Multiple Record Read with Automatic
Search or Entire Track Read
Selectable 128 Byte or Variable Length Record
• WRITE MODE
Single/Multiple Record Write with Automatic
Sector Search
Entire Track Write for Diskette Initialization
• PROGRAMMABLE CONTROLS
Selectable Track to Track Stepping Time
Selectable Head Settling and Head Engage Times
• SYSTEM COMPATIBILITY
Double Buffering of Data 8 Bit Bi-Directional
Bus for Data, Control and Status
DMA or Programmed Data Transfers
All Inputs and Outputs are TTL Compatible
On-chip Track and Sector Registers Comprehensive Status Information
• WRITE PRECOMPENSATION (MFM AND FM)
• WINDOW EXTENSION (IN MFM)
• INCORPORATES ENCODING/DECODING
AND ADDRESS MARK CIRCUITRY
APPLICATIONS
FLOPPY DISK DRIVE INTERFACE
SINGLE OR MULTIPLE DRIVE CONTROLLER/
FORMATTER
NEW MINI-FLOPPY CONTROLLER
compatibility, the FD1771, FD1781, and FD1791
designs were made as close as possible with the
computer interface, instruction set, and I/O
registers being identical. Also, head load control is
identical. In each case, the actual pin assignments
vary by only a few pins from anyone to another.
The processor interface consists of an 8-bit bidirectional bus for data, status, and control word
transfers. The FD1791 is set up to operate on a
multiplexed bus with other bus-oriented devices.
The FD1791 is fabricated in N-channel Silicon Gate
MOS technology and is TTL compatible on all
inputs and outputs.
NC
INTRa
CS
ORa
RE
5'5'EN
Wi5RT
AO
Al
6
IP
DAL 0
TROO
5AL1
WF
DAL 2
READY
B
DAL 3
10
DAL 4
11
5AL'5
12
5AL6
13
DAL 7
14
RAW READ
STEP
15
RCLK
DIRC
16
EARLY
17
LATE
18
GENERAL DESCRIPTION
The FD1791 is a MOS LSI device which performs
the functions of a Floppy Disk Formatter/Controller
in a single chip implementation. The FD1791,
which can be considered the end result of both the
FD1771 and FD1781 designs, is IBM 3740 compatible in single density mode (FM) and System 34
compatible in Double Density Mode (MFM). The
FD1791 contains all the features of its predecessor
the FD1771, plus the added features necessary to
read/write and format a double density diskette.
These include address mark detection, FM and
MFM encode and decode logic, window extension,
and write precompensation. In order to maintain
V DO (+ 12V)
WE
(GND)
WD
WG
TG43
HLD
RG
24
CLK
HLT
MR
19
22
V SS
20
21
PIN CONNECTIONS
TEST
VCC
Command Register (CR)-This 8-bit register ho.lds
the co.mmand presently being executed. This register sho.uld no.t be Io.aded when the device is busy
unless the executio.n o.f the current co.mmand is to.
be o.verridden. This latter actio.n results in an interrupt. The co.mmand register can be Io.aded fro.m the
DAL, but no.t read o.nto. the DAL.
Status Register (STR)-This 8-bit register ho.lds
device Status info.rmatio.n. The meaning o.f the
Status bits is a functio.n o.f the contents o.f the
Co.mmand Register. This register can be read o.nto.
the DAL, but no.t Io.aded fro.m the DAL.
CRC Logic-This Io.gic is used to check or to
generate the 16-bit Cyclic Redundancy Check
(CRC). The polynomial is: G(x) =X 16 + X12 + x 5 + 1.
The CRC includes all information starting with the
address mark and up to the CRC characters. The
CRC register is preset to ones prio.r to data being
shifted through the circuit.
Arithmetic/Logic Unit (ALU)-The ALU is a serial
comparator, incrementer, and decrementer and is
used for register modification and comparisons
with the disk reco.rded ID field.
ORGANIZATION
Timing and Control-All computer and Floppy Disk
Interface controls are generated through this logic.
The internal device timing is generated fro.m an
external crystal clock.
The Flo.ppy Disk Fo.rmatter blo.ck.diagram is illustrated o.n page 3. The primary sectio.ns include the
parallel pro.cesso.r interface and the Flo.ppy
Disk interface.
Data Shift Register-This 8-bit register assembles
serial data fro.m the Read Data input (RAW READ)
during Read o.peratio.ns and transfers serial data to.
the Write Data o.utput during Write o.peratio.ns.
The FD1791 has two different modes of operation
according to the state of DDEN. When DDEN = 0
double density (MFM) is assumed. When DDEN = 1,
single density (FM) is assumed.
Data Register-This 8-bit register is used as a
ho.lding register during Disk Read and Write o.peratio.ns. In Disk Read o.peratio.ns the assembled data
byte is transferred in parallel to the Data Register
fro.m the Data Shift Register. In Disk Write o.peratio.ns info.rmatio.n is transferred in parallel fro.m the
Data Register to. the Data Shift Register.
AM Detector-The address mark detector detects
ID, data and index address marks during read and
write operations.
When executing the Seek co.mmand the Data Register ho.lds the address o.f the desired Track po.sitio.n.
This register can be Io.aded fro.m the DAL and gated
o.nto. the DAL under pro.cesso.r co.ntro.l.
k'
RAW READ
>
DATA 181
RCLK
RG
AO
-"'
LATE
A1
0
Track Register-This 8-bit register ho.lds the track
number o.f the current Read/Write head po.sitio.n. It
is incremented by o.ne every time the head is
stepped in (to.wards track 76) and decremented by
o.ne when the head is stepped out (to.wards track
00). The co.ntents o.f the register are co.mpared with
the reco.rded track number in the ID field during disk
Read, Write, and Verify o.peratio.ns. The Track Register can be Io.aded fro.m o.r transferred to. the DAL.
This Register sho.uld no.t be Io.aded when this device
is busy.
.
cs
C
EARLY
0
-
P
P
Y
WE
..
MR
I
N
WG
FLOPPY DISK
CONTROLLER
FORMATTER
WF
'5
?
<>
ORO
Sector Register (SR)-This 8-bit register ho.lds the
address o.f the desired secto.r po.sitio.n. The co.ntents
o.f the register are co.mpared with the reco.rded
secto.r number in the ID field during disk Read o.r·
Write o.peratio.ns. The Secto.r Register co.ntents can
be Io.aded fro.m o.r transferred to. the DAL. This
register sho.uld no.t be Io.aded when the device is
busy.
0
R
I
READY
E
?
STEP
ClIRC
FD1791
--'"
I~
-=
HLD
1J
HL:;""" + 5
V 5S
1
V DO
I
+ 12
V CC
I
+ 5V
1791 SYSTEM BLOCK DIAGRAM
2
v
TG43
INTRO
CLK
TROO
W
<> 10K
?
10K?
0
I
S
K
WPRT
T
E
R
F
A
C
E
F
L
wo
RE
M
P
U
T
E
.R
ONE SHOT
(IF USEDI
I
DATA OUT
BUFFERS
!
STATUS
REG
ALU
~-~
WRITE DATA
(TO DISK)
'---------------(
RCLK
WG
TG43
INTRa
WPRT
--:---
WP
iP
CS
TROO
AO
COMPUTER
INTERFACE
CONTROL
CONTROL
PLA
CONTROL
(230 X 16)
CONTROL
.
DISK
INTERFACT
CONTROL
Al
READY
STEP
DIRC
EARLY
LATE
RG
HLD
HLT
-
FD1791 BLOCK DIAGRAM
PROCESSOR INTERFACE
A1-AO
0 0
0 1
1 0
The interface to the processor is accomplished
through the eight Data Access Lines (DAL) and
associated control signals. The DAL are used to
transfer Data, Status, and Control words out of, or
into the FD1791. The DAL are three state buffers
that are enabled as output drivers when Chip Select
(CS) and Read Enable (RE) are acti~(low 10Qic
state) or act as input receivers when CS and Wnte
Enable (WE) are active.
1
1
READ (RE)
Status Register
WRITE (WE)
Track Register
Command Register
Track Register
Sector Register
Data Register
Sector Register
Data Register
During Direct Memory Access (DMA) types of data
transfers between the Data Register of the FD1791
and the processor, the Data Request (ORO) output
is used in Data Transfer control. This signal also
appears as status bit 1 during Read and Write
operations.
When transfer of data with the Floppy Disk Controller is required by the host processor, the device
address is decoded and CS is made low. The leastsignificant address bits A1 and AO, combined with
the signals RE during a Read operation or WE
during a Write operation are interpreted as selecting
the following registers:
On Disk Read operations the Data Request is activated (set high) when an assembled serial input
byte is transferred in parallel to the Data Register.
This bit is cleared when the Data Register is read by
3
after the head is loaded against the media. The track
number from th~ first encountered ID Field is
compared against the contents of the Track Register. If the track numbers compare and the ID Field
Cyclic Redundancy Check (CRC) is correct, the
verify operation is complete and an INTRa is
generated with no errors. The FD1791 must find an
ID field with correct track number and correct CRC
within 5 revolutions of the media; otherwise the seek
error is set and an INTRa is generated.
the processor. If the Data Register is read after one
or more characters are lost, by having new data
transferrd into the register prior to processor
readout, the lost Data bit is set in the Status
Register. The Read operation contin'ues until the
end of sector is reached.
On Disk Write operations the Data Request is
activated when the Data Register transfers its
contents to the .Data Shift Register, and requires a
new data byte. It is reset when the Data Register is
loaded with new data by the processor. If new data is
not loaded at the time the next serial byte is required
by the Floppy Disk, a byte of zeroes is written on the
diskette and the lost Data bit is set in the Status
Register.
Table 1. STEPPING RATES
ClK
2 MHz
5i5EN
0
R1 RO TEST=1
At the completion of every command an INTRa is
generated. INTRa is reset by either reading the
status register or by loading the command register
with a new command. In addition, INTRQ is generated if a Force Interrupt command condition is
met.
0
0
3 ms
2 MHz
1 MHz
TEST=1
TEST=1
1 MHz
2 MHz
1 MHz
TEST=1
0
TEST=O
TEST=O
3 ms
6 ms
6 ms
Approx.
Approx.
12 ms
12 ms
200 J.l.s
400 J.I.S
0
1
6 ms
6 ms
1
0
10 ms
10 ms
20 ms
20 ms
1
1
.15 ms
15 ms
30 ms
30 ms
FLOPPY DISK INTERFACE
The 1791 has two modes of operation according to
the state of DDEN (Pin 37). When DDEN =1, single
density is selected. In either case, the ClK input
(Pin 24) is at 2 MHz. However, when interfacing with
the mini-floppy, the ClK input is set at 1 MHz for
both single density and double density. When the
clock is at 2 MHz, the stepping rates of 3,6, 10, and
15 ms are obtainable. When ClK equals 1 MHz these
times are doubled.
The Head load (HlD) output controls the movement of the read/write head against the media. HlD
is activated at the beginning of a Type I command if
the h flag is set (h = 1), at the end of the Type I
command if the verify flag (V =1), or upon receipt of
any Type II or III command. Once HlD is active it
remains active until either a Type I command is
received with (h =0 and V =0); or if the FD1791 is in
an idle state (non-busy) and 15 index pulses have
occu rred, it is reset.
HEAD POSITIONING
Head load Timing (Hl T) is an input to the FD1791
which is used for the head engage time. When
Hl T = 1, the FD1791 assumes the head is completely
engaged. The head engage time is typically 30 to
100 ms depending on drive. The low to high transition on HlD is typically used to fire a one shot. The
output of the one shot is then used for HlT and
supplied as an input to the FD1791.
Four commands cause positioning of the ReadWrite head (see Command Section). The period of
each positioning step is specified by the r field in
bits 1 and 0 of the command word. After the last
directional step an additional 15 milliseconds of
head settling time takes place if the Verify flag is set
in Type I commands. Note that this time doubles to
30 ms for a 1 MHz clock. If TEST =0, there is zero
settling time. There is also a 15 ms head settling time
if the E flag is set in any Type 2 or 3 command.
The rates (shown in Table 1) can be applied to a
St~p-Direction Motor through the device interface.
Step-A 2 Ils (MFM) or 4 Ils (FM) pulse is provided
as an output to the drive. For every step pulse
issued, the drive moves one track location in a direction determined by the direction output.
HLY IFROMONE :,HOT,
HEAD lOAD TIMING
Direction (DIRC)-The Direction signal is active
high when stepping in and low when stepping out.
The Direction signal is valid 12 Ils before the first
stepping pulse is generated.
When both HlD and Hl T are true, the FD1791 will
then read from or write to the media. The "and" of
HlD and HlT appears as a status bit in Type I status.
In summary for the Type I commands: if h =0 and
V =0, HlD is reset. If h =1 and V =0, HlD is set at the
beginning of the command and HlT is not sampled
nor is there an internal 15 ms delay. If h =0 and V =1,
HlD is set near the end of the command, an internal
15 ms occurs, and the FD1791 waits for HlT to be
When a Seek, Step or Restore command is executed
an optional verification of Read-Write head position
can be performed by setting bit 2 (V =1) in the command word to a logic 1. The verification operation
begins at the end of the 15 millisecond settling time
4
true. If h = 1 and V = 1, HLD is set at the beginning of
the command. Near the end of the' command, after
all the steps have been issued, an internal 15 ms
delay occurs and the FD1791 then waits for HLT to
occur.
Writing is inhibited when the Write Protect input is a
logic low, in which case any Write command is
immediately terminated, an interrupt is generated
and the Write Protect status bit is set. The Write
Fault input, when activated, signifies a writing fault
condition detected in disk drive electronics such as
failure to detect write current flow when the Write
Gate is activated. On detection of this fault the
FD1791 terminates the current command, and sets
the Write Fault bit (bit 5) in the Status Word. The
Write Fault input should be made inactive when the
Write Gate output becomes inactive.
For Type II and III commands with E flag off, HLD is
made active and HLT is sampled until true, with E
flag on HLD is made active, an internal 15 ms delay
occurs and then HLT is sampled until true.
For write operation, the FD1791 provides Write Gate
(Pin 30) and Write Data (Pin 31) outputs. Write data
consists of a series of 500 ns pulses in FM (DDEN = 1)
and 250 ns pulses in MFM (DDEN = 0). Write Data
provides the unique address marks in both formats.
DISK READ OPERATIONS
Sector lengths of 128, 256, 512 or 1024 are obtainable in either FM or MFM formats. For FM, DDEN
should be placed to logical "1." For MFM formats,
DDEN should be placed to a logical "0." Sector
lengths are determined at format time by a special
byte in the "ID" field. If this Sector Length byte in the
ID field is zero, then the sector length is 128 bytes. If
01 then 256 bytes. If 02, then 512 bytes. If 03, then the
sector length is 1024 bytes. The number of sectors
per track as far as the FD1791 is concerned can be
from 1 to 255 sectors. The number of tracks as far as
the FD1791 is concerned is from 0 to 255 tracks. For
IBM 3740 compatibility, sector lengths are 128 bytes
with 26 sectors per track. For System 34 compatibility
(MFM), sector lengths are 256 bytes/sector with 26
sectors/track; or lengths of 1024 bytes/sector with 8
sectors/track.
Also during write, t~o additional signals are provided for write precompensation. These are EARLY
(Pin 17) and LATE (Pin 18). EARLY is active true
when the WD pulse appearing on (Pin 30) is to be
written early. EARLY is valid for the duration of the
pulse. LATE is active true when the WD pulse is to be
written late. If both are low when a WD pulse is
present, the WD pulse is to be written at nominal.
Since write precompensation values vary from disk
manufacturer to disk manufacturer, the actual value
is determined by several one shots or delay lines
which are located external to the FD1791. The write
precompensation signals EARLY and LATE are
valid in both FM and MFM formats.
For read operations, the FD1791 requires RAW
READ Data (Pin 27) signal which is a 250 ns pulse
per flux transition and a Read cloCk (RCLK) signal
to indicate flux transition spacings. The RCLK (Pin
26) signal is provided by some drives but if not it may
be derived externally by Phase lock loop, one shots,
or counter techniques. In addition, a Read Gate
Signal is provided as an output (Pin 25) which
informs some phase lock loops when to acquire
synchronization. When reading from the media in
FM, RG is made true when 2 bytes of zeroes are
detected. The FD1791 must find an address mark
within the next 10 bytes; otherwise RG is reset and
the search for 2 bytes of zeroes begins all over
again. If an address mark is found within 10 bytes,
RG remains true as long as the FD1791 is deriving
any useful information from the data stream. Similarly for MFM, RG is made active true when 4 bytes
of "00" or "FF" are detected. The FD1791 must find
an address mark within the next 16 bytes, otherwise
RG is reset and search resumes.
Whenever a Read or Write command (Type II or III)
is received the FD1791 samples the Ready input. If
this input is logic low the command is not executed
and an interrupt is generated. The Seek or Step
Type I commands are performed regardless of the
state of the Ready input. Also, whenever a Type II or
III command is received, the TG43 signal output is
updated.
COMMAND DESCRIPTION
The FD1791 will accept eleven commands. Command words should only be loaded in the Command
Register when the Busy status bit is off (Status bit 0).
The one exception is the Force Interrupt command.
Whenever a command is being executed, the Busy
status bit is set. When a command is completed, an
interrupt is generated and the Busy status bit is
reset. The Status Register indicates whether the
completed command encountered an error or was
fault free. For ease of discussion, commands are
divided into four types. Commands and types are
summarized in Table 2.
DISK WRITE OPERATION
When writing is to take place on the diskette the
Write Gate (WG) output is activated, allowing current to flow into the Read/Write head. As a precaution to erroneous writing the first data byte must be
loaded into the Data Register in response to a Data
Request from the FD1791 before the Write Gate
signal can be activated.
TYPE I COMMANDS
The Type I Commands include the Restore, Seek,
Step, Step-In, and Step-Out commands. Each of the
Type I Commands contains a rate field (rOrl), which
determines the stepping motor rate as defined in
Table 1.
5
Table 2. COMMAND SUMMARY
Table 5. FLAG SUMMARY
BITS
Seek
0 0 0 0 h V rl ro
0 0 0 1 h V rl ro
Step
0 0 1 u h V rl ro
Step In
Read Command
0 1 o u h V rl ro
0 1 1 u h V rl ro
1 0 0 m X--E 0 0
Write Command
1 0 1 mX E X ao
Read Address
Restore
Step Out
I
Read Track
1 1 0 0 0 1 o 0
1 1 1 0 0 1 0 X
I
Write Track
1 1 1 1 0 1 0 0
Force I nterrrupt
1 1 0 1 b b II 10
V
TYPE IV
765 4 3 2 1 0
TYPE COMMAND
Ii = Interrupt Condition flags (Bits 3-0)
10 = 1, Not-Ready to Ready Transition
11 = 1, Ready to Not-Ready Transition
12 = 1, Index Pulse
13 = 1, Immediate Interrupt
The Type 1 Commands contain a head load flag (h)
which determines if the head is to be loaded at the
beginning of the command. If h = 1, the head is
loaded at the beginning of the command (HLD
output is made active). If h = 0, HLD is deactivated.
Once the head is loaded, the head will remain
engaged until the FD1791 receives a command that
specifically disengages the head. If the FD1791 is
idle (busy = 0) for 15 revolutions of the disk, the head
will be automatically disengaged (HLD made
inactive).
X = Don't care
Note: Bits shown in TRUE form.
The Type I Commands also contain a verification
(V) flag which determines if a verification operation
is to take place on the destination track. If V = 1, a
verification is performed, if V = 0, no verification is
performed.
Table 3. FLAG SUMMARY
~
TYPE I
During verification, the head is loaded and after an
internal 15 ms delay, the HL T input is sampled.
When HL T is active (logic true), the first encountered 10 field is read off the disk. The track address
of the ID field is read off the disk. The track address
of the I D field is then compared to the Track
Register; if there is a match and a valid 10 CRC, the
verification is complete, an interrupt is generated
and the Busy status bit is reset. If there is not a
match but there is valid 10 CRC, an interrupt is
generated, and Seek Error Status bit (Status bit 4) is
set and the Busy status bit is reset. If there is a match
but not a valid CRC, the CRC error status bit is set
(Status bit 3), and the next encountered 10 field is
read from the disk for the verification operation. If
an 10 field with a valid CRC cannot be found after
four revolutions of the disk, the FD1791 terminates
the operation and sends an interrupt, (INTRQ).
h = Head Load Flag (Bit 3)
h = 1, Load head at beginning
h = 0, Unload head at beginning
V
= Verify
flag (Bit 2)
V = 1, Verify on last track
V = 0, No verify
rlro
= Stepping
m9tor rate (Bits 1-0)
Refer to Table 1 for rate summary
u = Update flag (Bit 4)
u = 1, Update Track register
u = 0, No update
The Step, Step-I n, and Step-Out commands contain
an Update flag (U). When U = 1, the track register is
updated by one for each step. When U = 0, the track
register is not updated.
Table 4. FLAG SUMMARY
TYPE II
m
= Multiple Record
flag (Bit 4)
RESTORE (SEEK TRACK 0)
m = 0, Single Record
m = 1, Multiple Records
ao
= Data Address
Upon receipt of this command the Track 00 (TROO)
input is sampled. If TROO is active low indicating
the Read-Write head is positioned over track 0, the
Track Register is loaded with zeroes and an interrupt is generated. If TROO is not active low, stepping pulses (pins 15 to 16) at a rate specified by the
rlro field are issued until the TROO input is activated. At this time the TR is loaded with zeroes and
an interrupt is generated. If the TROO input does not
go active low after 255 stepping pulses, the FD1791
Mark (Bit 0)
ao = 0, FB (Data Mark)
ao = 1, Fa (Deleted Data Mark)
E = 15 ms Delay
E = 1, 15 ms delay
E = 0, no 15 ms delay
6
terminates operation, interrupts, and sets the Seek
error status bit. Note that the Restore command is
executed when M R goes from an active to an
inactive state. A verification operation takes place if
the V flag is set. The h bit allows the head to be
loaded at the start of command.
STEP
Upon receipt of this command, the FD1791 issues
one stepping pulse to the disk drive. The stepping
motor directio'n is the same as in the previous step
command. After a delay determined by the rlrO field,
a verification takes place if the V flag is on. If the u
flag is on, the TR is updated. The h bit allows the
head to be loaded at the start of the com mand. An
interrupt is generated at the completion of the
command.
.
SEEK
This command assumes that the Track Register
contains the track number of the current position of
the Read-Write head and the Data Register contains
the desired track number. The FD1791 will update
the Track register and issue stepping pulses in the
appropriate direction until the contents of the Track
register are equal to the contents of the data register
(the desired track location). A verification operation
takes place if the V flag is on. The h bit allows the
head to be loaded at the start of the command. An
interrupt is generated at the completion of the
command.
STEP-IN
Upon receipt of this command,' the FD1791 issues
one stepping pulse in the direction towards track 76.
If the u flag is on, the Track Register is incremented
by one. After a delay determined by the rlrO field, a
verification takes place if the V flag is on. The h bit
allows the head to be loaded at the start of the
command. An interrupt is generated at the completion of the command.
TYPE I COMMAND FLOW
TYPE I COMMAND FLOW
7
STEP-OUT
Upon receipt of this command, the F01791 issues
one stepping pulse in the direction towards track O.
If the u flag is on, the TR is decremented by one.
After a delay determined by the rlro field, a verification takes place if the V flag is on. The h bit allows
thee start of the command. An interrupt is generated
at the completion of the command.
TYPE II COMMANDS
The type II Commands include the Read Sector (s)
and Wrii.e Sector (s) commands. Prior to loading the
Type II Command into the Command Register, the
computer must load the Sector Register with the
desired sector number. Upon receipt of the Type II
command, the busy status Bit is set. If the E flag = 1
(this is the normal case) HLD is made active and
HL T is sampled after a 15 msec delay. If the E flag is
0, the head is loaded and HL T sampled with no 15
msec delay. The 10 field and Data Field format are
-shown below.
When an 10 field is located on the disk, the F01791
compares the Track number of the 10 field with the
Track Register. If there is not a match, the next
encountered 10 field is read and a comparison is
again made. If there was a match, the Sector
Number of the 10 field is compared with the Sector
Register. If there is not a Sector match, the next
encountered 10 field is read off the disk and comparisons again made. If the 10 field CRC is correct,
the data field is then located and wi II be either
written into, or read from depending upon the
command. The FD1791 must find an I D field with a
Track number, Sector number, and CRG within four
revolutions of the disk; otherwise, the Record not
found status bit is set (Status bit 3) and the command is terminated with an interrupt.
Sector Length
Field (hex)
00
01
02
03
N umber of Bytes
in Sector (decimal)
128
256
512
1024
Each of the Type II Commands contains an (m) flag
which determines if multiple records (sectors) are to
be read or written, depending upon the command. If
m = 0, a single sector is read or written and an
interrupt is generated at the completion of the
command. If m = 1, multiple records are read or
written with the sector register internally updated so
that an address verification can occur on the next
record. The FD1791 will continue to read or write
multiple records and update the sector register until
the sector register exceeds the number of sectors
on the track or until the Force Interrupt command is
loaded into the Command Register, which terminates the command and generates an interrupt.
READ COMMAND
Upon receipt of the Read command, the head is
loaded, the Busy status bit set, and when an I D field
is encountered that has the correct track number,
correct sector number, and correct CRC, the data
field is presented to the computer. The Data Address Mark of the data field must be found within 30
bytes in single density and 43 bytes in double
density of the last ID field CRC byte; if not, the
Record Not Found status bit is set and the operation
is terminated.
NOTE IF TEST - 0 THERE IS NO 15MS DELAY
IF TEST = 1 AND eLK' 1 MHz THERE IS A 30MS DELAY
TYPE I COMMAND FLOW
8
GAP
III
DATA
AM
CRC
2
10 FIELD
In MFM only, lOAM and DATA AM are preceded by three bytes of A1 with clock transition between bits 4 and
5 missing.
TYPE II COMMAND
NOTE
i'f'T"ET,i
il'TfST
in'putted to the computer. If there is a CRC error at
the end of the data field, the CRC error status bit is
set, and the command is terminated (even if it is a
multiple record command).
rHERL IS NO 15MS DELAY
I AND eLK
I MHz THERE IS 30MS DELAY
'J
TYPE II COMMAND
At the end of the Read operation, the type of Data
Address Mark encountered in the data field is
recorded in the Status Register (Bit 5) as shown
below:
When the first character or byte of the data field has
been shifted through the DSR, it is transferred to the
DR, and ORO is generated. When the next byte is
accumulated in the DSR, it is transferred to the DR
and another ORO is generated. If the Computer has
not read the previous contents of the DR before a
new character is transferred that character is lost
and the Lost Data Status bit is set. This sequence
continues until the complete data field has been
STATUS
BIT 5
1
o
9
Deleted Data Mark
Data Mark
The FD1791 then writes the data field and generates
DRO's to the computer. If the DRO is not serviced in
time for continuous writing the Lost Data Status Bit
is set and a byte of zeros is written on the disk. The
command is not terminated. After the last data byte
has been written on the disk, the two-byte CRC is
computed internally and written on the disk followed by one byte of logic ones in FM or 4F in MFM.
The WG output is then deactivated.
WRITE COMMAND
Upon receipt of the Write command, the head is
loaded (HLD active) and the Busy status bit is set.
When an I D field ts encountered that has the correct
track number, correct sector number, and correct
CRC, a DRO is generated. The FD1791 counts off 11
bytes in single density and 22 bytes in double
density. from the C~C .field and the Write Gate (WG)
output IS made active If the DRO is serviced (Le., the
DR has been loaded by the computer). If DRO has
not been serviced, the command is terminated and
the Lost Data status bit is set. If the ORO has been
serviced, the WG is made active and six bytes of
zeros in single density and 12 bytes in double
density are then written on the disk. At this time the
Data Address Mark is then written on the disk as
determined by the ao field, of the command as shown
below:
Data Address Mark (Bit O)
1
o
Deleted Data Mark
Data Mark
INTRQ, RESET BUSY
SET RE,CORD-NOT FOUND
NO
TYPE II COMMAND
NO
TYPE III COMMANDS
READ ADDRESS
Upon receipt of the Read Address command the
head is loaded and the Busy Status Bit is set.' The
n~xt encoyntered I D field is then read in from the
diSk, and the six data bytes of the ID field are
assembled and transferred to the DR, and a DRO is
generated for each byte. The six bytes of the I D field
are shown below:
INTRQ, RESET BUSY
SET CRC ERROR
TYPE II COMMAND
10
TRACK
ADDR
SIDE
NUMBER
SECTOR
ADDRESS
SECTOR
LENGTH
CRC
2
CRC
2
1
2
3
4
5
6
starts with the leading edge of the first encountered
index pulse and continues until the next index
pulse, at which time the interrupt is activated. The
Data Request is activated immediately upon receiving the command, but writing will not start until after
the first byte has been loaded into the Data Register.
If the DR has not been loaded by the time the index
pulse is encountered the operation is terminated
making the device Not Busy, the Lost Data Status
Bit is set, and the Interrupt is activated. If a byte is
not present in the DR when needed, a byte of zefOS
is substituted. Address Marks and CRC characters
are written on the disk by detecting certain data byte
patterns in the outgoing data stream as shown in the
table below. The CRC generator is initialized when
any data byte from Fa to FE is about to be transferred from the DR to the DSR in FM or by receipt of
F5 in MFM.
Although the CRC characters are transferred to the
computer, the FD1791 checks for validity and the
CRC error status bit is set if there is a CRC error. The
Track Address of the 10 field is written into the
sector register. At the end of the operation an
interrupt is generated and the Busy Status is reset.
READ TRACK
Upon receipt of the Read Track command, the head
is loaded and the Busy Status bit is set. Reading
starts with the leading edge of the first encountered
index mark and continues until the next index pulse.
As each byte is assembled it is transferred to the
Data Register and the Data Request is generated for
each byte. No CRC checking is performed. Gaps are
included in the input data stream. The accu mulation
of bytes is synchronized to each Address Mark
encountered. Upon completion of the command,
the interrupt is activated.
WRITE TRACK
Upon receipt of the Write Track command, the head
is loaded and the Busy Status bit is set. Writing
YES
(MFM)
WRITE 2 CRC
CHARS elK" FF
WRITEFC
ClK" D7
WRITE FD. FE OR
F8-FB. ClK " C7
INITIALIZE CRC
TY~E
TYPE III COMMAND WRITE TRACK
11
III COMMAND WRITE TRACK
CONTROL BYTES FOR INITIALIZATION
FD1791 INTERPRETATION
IN MFM (DDEN = 0)
FD1791 INTERPRETATION
IN FM (DDEN = 1)
DATA PATTERN
IN DR (HEX)
Write 00 thru F4, in MFM
Write A1 * in MFM, Preset CRC
Write C2** in MFM
Generate 2 CRC bytes
Write Fa thru FB, in MFM
Write FC in MFM
Write FD in MFM
Write FE in MFM
Write FF in MFM
Write 00 thru F4 with Clk = FF
Not Allowed
Not Allowed
Generate 2 CRC bytes
Write Fa thru FB, Clk = C7, Preset CRC
Write FC with Clk = D7
Write FD with Clk = FF
Write FE, Clk = C7, Preset CRC
Write FF with Clk = FF
00 thru F4
F5
F6
F7
Fa thru FB
FC
FD
FE
FF
*Missing clock transition between bits 4 and 5
**Missing clock transition between bits 3 and 4
TYPE IV COMMAND
the rest of the status bits are updated or cleared for
the new command. If the Force Interrupt Command
is received when there is a current command under
execution, the Busy status bit ts reset, and the rest of
the status bits are unchanged. If the Force Interrupt
command is received when there is not a current
command under execution, the Busy Status bit is
reset and the rest of the status bits are updated or
cleared. I n this case, Status reflects the Type I
commands.
FORCE INTERRUPT
This command can be loaded into the command
register at any time. If there is a current command
under execution (Busy Status Bit set), the command
will be terminated and an interrupt will be generated
when the condition specified in the 10 through 13 field
is detected. The interrupt conditions are shown
below:
10= Not-Ready-To-Ready Transition
11 = Ready-To-Not-Ready Transition
b = Every Index Pulse
b = Immediate Interrupt
The format of the Status Register is shown below:
NOTE: If 10 - 13 = 0, there is no interrupt generated
but the current command is terminated and
busy is reset. This is the Qnly command that
will clear the immediate- -interrupt.
(BITS)
7
S7
6
S6
5
85
4
84
3
2
1
0
S3
S2
S1
SO
STATUS DESCRIPTION
k
Upon receipt of ~hy command, except the Force
Interrupt command, the Busy Status bit is set and
Status varies according to the type of command
executed as shown in Table 6.
Table 6. STATUS REGISTER SUMMARY
BIT
S7
S6
ALL TYPE I
COMMANDS
NOT READY
READ
ADDRESS
NOT READY
WRITE
-P~OTEQL_
S5
HEAD
1'1
83
stU- K
G- J( tlld f\
READ
WRITE
TRACK
NOT READY NOT READY
READ
NOT READY
0
0
~ ! CU7\ ()
WRITE
0
J't fJ ~ ~
-"--..,
'11:' €[:ff"rr
- - ER_QIEGI
WRITE
TRACK
NOT READY
WRITE
PROTr=rT
0
0
WRITE FAULT WRITE FAULT
.~ECORD NOT\ 111-----------0----~ 1${t1l\ ~ AJir~Ai~---' FOUND
0
0
82
81
CRC ERROR
TRACK 0
INDEX
CRC ERROR
LOST DATA
LOST DATA
DRO
SO
BUSY
BUSY
CRC ERROR
CRC ERROR
LOST DATA
0
LOST DATA
DRO
0
LOST DATA
DRO
DRO
DRO
BUSY
BUSY
BUSY
BUSY
12
STATUS FOR TYPE I COMMANDS
BIT NAME
MEANING
S7 NOT READY
This bit when set indicates the drive is not ready. When reset it indicates that the drive
is ready. This bit is an inverted copy of the Ready input and logically cored' with MR.
When set, indicates Write Protect is activated. This bit is an inverted copy of WRPT
input.
When set, it indicates the head is loaded 'and engaged. This bit is a logical "and" or
HLD and HLT signals.
When set, the desired track was not verified. This bit is reset to 0 when updated.
When set, indicates Read Write head is positioned to Track O. This bit is an inverted
copy of the TROO input.
When set, indicates index mark detected from drive. This bit is an inverted copyofthe
IPinput.
When set command is in progress. When reset no command is in progress.
S6 PROTECTED
S5 HEAD LOADED
S4 SeEK ERROR
S2 TRACK 00
S1 INDEX
SO BUSY
STATUS BITS FOR TYPE II AND III COMMANDS
BIT NAME
MEANING
87 NOT READY
This bit when set indicates the drive is not ready. When reset,itindicates that the drive
is ready. This bit is an ,inverted copy of the Ready input and ·oredt·withMR. The Type It
and III Commands will not execute unless the drive isreadv~
S6 WRITE PROTECT On Read Record: Not Used. On Read Track: Not Used. On any Write: It indicates a
Write Protect. This bit is reset when updated.
85 RECORD TYPE! On Read Record: It indicates the record-type code from dat~ field address mark. On
WRITE FAULT
Read Track: Not Used.iOn any Write: It indicates a Write Fault. This bit is reset when
updated.
" .
S4 RECORD NOT
FOUND
S3 CRe ERROR
S2 LOST OAT A
81 DATA REQVEST
80 BUSY
When set, it indicates that'the desired track and sector were inot found. This bit'is
reset when updated.
If S4 is set, an error is found in one or more.O fields; otherwise·it indicates error indata,
field. This bit is reset wherf updated.
When set, it indicates thecQm,puter did not respond to ORO in one byte time. This bi.t is
reset to zero when update"d..
"
< '
This bit is a copy of the D'RQ output. When set, it indicates ttle OR is fuU ona Read •
Operation or theOA isetn,plyon a Write operation. This bit is 'reset tozero;when
updated.
' ,
.
When set, commanQi~;U"~'r:,x~ution. When reset, no command is under execution.
be written on the disk, a data request is generated.
This sequence continues from one index mark to
the next index mark. Normally, whatever data pattern appears in the data register is written on the
disk with a normal clock pattern. However, if the
FD1791 detects a data pattern on F5 thru FE in the
data register, this is interpreted as data address
marks with miSSing clocks or CRC generation. For
instance, in FM an FE pattern will be interpreted as
an 10 address mark (DATA-FE, CLK-C7) and the
CRC will be initialized. An F7 pattern will generate
two CRC characters in FM or MFM. As a consequence, the patterns F5 thru FE must not appear in
the gaps, data fields, or 10 fields. Also, CRC's must
be generated by an F7 pattern.
FORMATTING THE DISK
(Refer to section on Type III commands for flow
diagrams.)
Formatting the disk is a relatively simple task when
operating programmed lID or when operating under
DMA control with a large amount of memory. When
operating under DMA with limited amount of memory, formatting is a more difficult task. This is
because gaps as well as data must be provided at the
computer interface.
Formatting the disk is accomplished by positioning
the RIW head over the desired track number and
issuing the Write Track command. Upon receipt of
the Write Track command, the FD1791 raises the
data request signal. At this point in time, the user
loads the data register with desired data to be
written on the disk. For every byte of information to
Disks may be formatted in IBM 3740 or System 34
formats with sector lengths of 128,256,512, or 1024
bytes.
1~
user must issue the Write Track command and load
the data register with the following values. For every
byte to be written, there is one data request.
IBM 3740 FORMAT-128 BYTES/SECTOR
Shown below is the IBM single-density fOrmat with
128 bytes/sector. In order to format a diskette, the
user must issue the Write Track command, and load
the data register with the following values. For every
byte to be written, there is one data request.
80
12
HEX VALUE OF
BYTE WRITTEN
NUMBER
OF BYTES
*
NUMBER
OF BYTES
4E
00
F6
FC
4E
00
F5
FE
Track Number (0 thru 4C)
Side Number (0 or 1)
Sector Number (0 thru 1A)
01
F7
4E
00
F5
FB
40
F7
4E
3
FF
00
FC (I ndex Mark)
FF
(,~1/
00
FE (10 Adress Mark)
Track Number
00
Sector Number (1 thru 1A)
00
F7 (2 CRC's written)
FF
] (,?~~
00
FB (Data Address Mark)
Data (IBM uses E5)
F7 (2 CRC's written)
FF
FF
40
6
1
26
6
1
1
1
1
1
1
11
6
1
128
1
27
247**
J
1
50
12
*
3
1
1
1
1
1
1
22
12
3
1
256
1
54
598**
1~~~
*Write bracketed field 26 times
**Continue writing until FD1791 interrupts out.
Approx. 247 bytes.
HEX VALUE OF
BYTE WRITTEN
*Write bracketed field 26 times.
**Continue writing until FD1791 interrupts out.
Approx. 598 bytes.
IBM SYSTEM 34 FORMAT256 BYTES/SECTOR
Shown below is the IBM dual-density format with
256 bytes/sector. In order to format a diskette, the
PHYSICAl INDf x
46 BYTES FM
92 BYTES MFM
H
~ INDEX ADDRESS MARl<
GAP -4
PHE INDEX
110 HYTf FM
14-4 BYTl', MfM
C2""
GAP '2
10 GAP
'\ BYTES
DATA
FIELD
RECORO
MFM
GAP 3
DATA GAP
10
33 BYTE FM
RECORD
66 ByTE MPM
NO 2
DATA
RECORD
NO ~)
GAP '2
DATA OR
DELETED
DATA
ADDRESS
USER DATA
CRC
CRe
BYTE 1
BYTe '2
MARK
'MISSING CLOCK TRANSITION
BETWEEN 8ITS -4 AND 5
,
I
I
GAP '2
I
I
I
··MISSING CLOCK TRANSITION
BETWEEN BITS 3 AND 4
I
FM
MFM
~llBYTES-+ 6 BYTES
22 BYTES
,
WRITE GATE TURN ON FDA UPDATE
OF NEXT DATA FIELD
--
12 BYTES
0
3
H
:
1 BYTE
!----32BYTES----j
0
1 BYTE
,
3
L
-.-I
IBM TRACK FORMAT
14
WRITE TUAN OFF FOR UPDATE
OF PREVIOUS DATA FIELD
NON-IBM FORMATS
REFERENCES:
Variations in the I BM format are possible to a limited
extent if the following requirements are met: sector
size must be a choice of 128, 256, 512 or 1024 bytes;
gap size must be according to the following table.
Note that the Index Mark is not required by the
FD1791.
1. IBM Diskette OEM Information GA21-9190-1
2. SA900 IBM Compatibility Reference ManualShugart Associates.
3. IBM Two-Sided Diskette OEM Information
GA21-9257-1
ELECTRICAL CHARACTERISTICS
MFM
16 bytes 4E
MAXIMUM RATINGS
Gap I
FM
16 bytes FF
Gap II
*
11 bytes FF
6 bytes 00
22 bytes 4E
12 bytes 00
3 bytes A1
Max. Voltage to Any Input With
Respect to Vss
Operating Temperature
O°C to 70°C
Gap III
**
10 bytes FF
4 bytes 00
16 bytes 4E
8 bytes 00
3 bytes A1
Storage Temperature
-55°C to +125°C
Gap IV
16 bytes FF
16 bytes 4E
VDD With Respect to Vss (Ground) +15 to -0.3V
OPERATING CHARACTERISTICS (DC)
T A = 0° C to 70° C, VDD = +12.0V ±.6V,
Vss = OV , Vee =+5V ±.25V
VDD = 10 ma Nominal, Vee = 35 ma Nominal
*Byte counts must be exact.
**Byte counts are minimum, except exactly 3 bytes
of A 1 must be written.
SYMBOL
ILl
CHARACTERISTIC
Input Leakage
ILo
V IH
Output Leakage
Input High Voltage
VIL
Input Low Voltage (all
VOH
Output High Voltage
VOL
Output Low Voltage
+15 to -0.3V
MIN.
TYPE.
MAX.
10
UNITS
p.A
10
p.A
2.6
CONDITIONS
V IN = VDD
VOUT = V DD
V
0.8
2.8
V
V
0.4
V
10 = 100 p.A
10 = 1.6 mA
NOTE: Pin l' is normally connected to substrate with internal back bias generator. Be sure not to connect anything to Pin 1.
TIMING CHARACTERISTICS
TA = O°C to 70°C, VDD = + 12V ± .6V, Vss =OV, Vee =+5V±.25V
NOTE:
Timings are given for 2 MHz Clock. For those timings noted, values will double when chip is operated
at 1 MHz.
READ OPERATIONS
SYMBOL
TYP.
MAX.
UNITS
CHARACTERISTIC
MIN.
TSET
Setup ADDR & CS to RE
100
nsec
THLD
Hold ADDR & CS from RE
10
nsec
TRE
RE Pulse Width
500
nsec
TORR
ORa Reset from RE
TIRR
INTRa Reset from RE
TDACC
Data Access from RE
TDOH
Data Hold From RE
~OO.
50
15
CONDITIONS
C L = 25 pf
500
nsec
3000
nsec
350
nsec
C L = 25 pf
nsec
C L = 25 pf
150
See Note
16' OR 32' u S - - -
1--------- ~
-I
16' OR 32' uS ----_~
ORU VOL
VOH
[lRO VOL
INTRU
f--:----+-------...
INTRQ
tSERVICE
VOL
AO A I CS
Af) A 1
(~S
Ii II
I
VII
WI
-
I
'SET
I
DAI
DATA VAilI'
~1E:.AD
DATAVAIID
WRITt DATA
1l'iATi
OOH~
OA TA
IIlUrHI1~
TRI
~TATEDI
NOTE
1
CS
NOTE
MAY BE PERMANENTLY TIED LOW IF DESIRED
'TIME DOUBLES WHEN CLOCK
lMHl
t SERVICE (WORST CASEI
'FM - 235 LIS
'MFM
11 SuS
t SERVICE (WORST CASEI
275 uS
"FM
'MFM
135 uS
READ ENABLE TIMING
Cs
1
MAY BE PERMANENTL Y TIED LOW IF DESIRED
2 WHENWRITINGDATAINTOSECTOR TRACK ORDATA
REGISTER USER CANNOT READ THIS REGISTER UNTIL
AT lEAST 4 "SEC IN MFM AFTER THE RISING EDGE OF WE
WHEN WRITING INTO THE COMMAND REGISTER STATUS
IS NOT VALID UNTIL SOME 12 "SEC IN FM 6 "SEC IN MFM
lATER THESE TIMES ARE DOUBLED WHEN ClK' 1 MHz
'TIME DOUBLES WHEN CLOCK
lMHz
WRITE ENABLE TIMING
WRITE OPERATIONS
SYMBOL
TSET
CHARACTERISTIC
Setup AD DR & CS to WE
THLD
Hold ADDR & CS from WE
TWE
WE Pulse Width
TORR
ORO Reset from WE
TIRR
INTRa Reset from WE
TDS
Data Setup to WE
TDH
Data Hold from WE
MIN.
TYP.
MAX.
UNITS
100
nsec
10
nsec
350
nsec
500
500
nsec
3000
nsec
250
nsec
20
nsec
CONDITIONS
See Note
MISCELLANEOUS TIMING:
SYMBOL
CHARACTERISTIC
MIN.
TYP.
MAX.
UNITS
TCD l
Clock Duty (low)
230
nsec
TCD 2
Clock Duty (high)
200
nsec
TSTP
Step Pulse Output
2 or 4
J,Lsec
TDIR
Dir Setup to Step
12
J,Lsec
TMR
Master Reset Pulse Width
50
J,Lsec
TIP
Index Pulse Width
10
J,Lsec
TWF
Write Fault Pulse Width
10
J,Lsec
16
CONDITIONS
See Note
IIpW - - - - {
RAW
READ
J---
250 ns • 50
'~I
j}-_ _ _.....,
U
Lf
I
WF
l
II----
RCLK
•I•
l-
It'
Id
Tb'
MR ~)-------'II --~5
/ - - TMR
-I
Tc'
-tTWj-~
NOMINAL
5"
5"
DDEN
0
1
0
1
VIH
---1
I-TCYC~
"USER NEED NOT CONCERN HIMSElF
WHETHER THESE PULSES ARE CLOCK
OR DATA, THE FDI791 WILL
ASCERTAIN THIS
OR IN OTHER
WORDS, RCLK MAY BE INVERTED
MODE
MFM
FM
MFM
FM
VIH
CLKLlL
HOO n~,
tc ' 40 ns
DISKETTE
8"
8"
VIH
--1
.-
I
----1
, NOMINAL
ABS(lIIJH VAL UES
HOD n,
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74LS02 ~
SELO
,.
,-+t____
41
07C1--~F'''-8---H+H-++-+
rrh.
L.!4rOTtt1111rrr--;=======~~__~A~E:£.__J
~
81LS98
~~
50~141~
:.~~
+0
~
~
22
13
421~
4
303
rf.J..
::,,';!," -~II
_~
~
~
~
~
c>-----4r----.T...----<>O
1 co. ...l± C8.
".J.1 J 4.7
'D ••:.
74
3
1
c>---r""--C4-2-r"---"--":
C
+5
2.2K
Q
12
+5
~5
161CwLA~
7404
7~
+6
~
.8p~~
.gJ:31~~
TEST E.~I
~~.
~'4""k'·
')2210 4
rt------,-+5:R5
~WI~ 11K
'"
R26-2
1~
+5
:a'
~ 12
n
7
221Ci
4
2:
L...::4 123 ~,~':
V,
~
-5
"l"
180r
4_5
LM741
A47
R28-11
7408
6 S 21 4 C48
SID --+Lb~
.01
7406
10 ~ ~
5
+..
~fl ~L
'~~PT_ 1~~157
1
FREO
2
8 t-t
C5"~__~.. S 112
t!
sap
7_4_~______'_'____·_~_2
+5
veo
4
+58
~ 1~4 ~
<>-~'!>----!
~:"*
2 a
S 740'
D 7
8MHZ
R;"NQE~Ai?-t ~~~'ift"~ -,§'.....
9
5
6
MR
1
.
R2T
+_5__f_J
_____________________________
I·' J:t.
1"4.7
044
C43
""'0
:3.£]'
1
•
,
,
0.
CLK
• 17!-'·'-"'HW"'--+--+____-'
74LS14
r;:::==:::.....
"'
~:':~!:;
, .,.
3;
~ rl~f-
+5
"4
R34
.
7404 2 D~OQ 6
74a
,..L" r:r:-~
.9
49
,'":,2,
'T
:7:9
:::
R34
9
7404
DIODE
BCD ,
+5
J
J
_
H
13 49
MATRIX
12
3 49
4
------------H--------------'
6
II
6
+6
L...-.,,--
'"
~
6
SiDE
21
::... ""
':~~ ~~~"
12 D20Q'-'.'----.!.~:"'-:Jr--'9·'
11 10
,,74..0 8
9
19
8
: '8
•
"
03.
R2:8
:;:
1K
4
,
~~414B
FI:;
,
:~~
_
3
34
2
_+ C6. +,.
+1Or L";;302
~2
11
037
470
- ~+"N';:8
C61+L.
'Orr
+
~:V~
'N4731\
1
='= ~J:
T
J
8
3
9
...,,8'--__+-"'3'1] 39
:lV7
~'O'
7
+5
'3. 12
~!6
:
~3'>"_-+_---+
...
+'2
R,": LM3302
6
,,36
74LS27 ""
1~.....
..
'0 40
11
+:5"
+6
G40
'----
INTE
SPARE Ie LIST
4.7
IC
1
6
16
17
23
26
1'YPE-FUNCTION
74123- one shot
7486-XOR
74LS02-NOR
74LS14-INV
7408-AND
2.2K Resistors
SECTIONS NOT USED
9,10,11
1,2,3
1,2,3
12,13
1,2,3,4,5,6
4,12,13
CONTRACT NO
THE DIGITAL GROUP
30
31
34
46
49
7404-INV
7432-0R
3302-COMP
7404-INV
7404-INV
12,13
8,9,10
12,13
1,2,8,9,10,11
LAST IC: 49
LAST RESISTOR: R50. R16
not used
LAST CAPACITOR: C75
LAST DIODE: D4
Diii
r __________+~"_1L.:.O"..)O
0 .~
. . . . STEP
~.~
+12
,~
LOAD ,.
A28-'O 7438
r------+~-"~_i1.0'
=
,N4,,0 0'
INTAO
J:.
11
38
+15
c_---..----'L.
__....-__.......2~...~-r----<>: + 58
1
7438
~~m
13
12
RCLK
+6
1~
3
21 38 ~
"WGATE
f!L-'
m.
6
5
'----
R20-11
ItI
-;:=========================~=====~=tt:ttI~~.
~a_\:"""'-MOTOFlON19
r _________
I
12
02+ 6-11
MIN
:
: .... r:. . .
~ °.40 •
I ~rQ1:3 3 7~
7
: '2 0 •
'0 221
A
~
LM318
_'OK
13
+5
_
~
r-k.
120
"
R26-11
~t~l~
,~12I~~e.8K
," '2 16
;
7420
4
• 221.1o~~
. 14
R26-11
10
_.-
+58
~~;
'2 0240 • ":; '~~ ~;:
74 PHAS: 406
COMPARITOR
"ux
+5
R8
+.
R8
"6-1'
YriJ
lbMIN
II
+.
~1 <1
0
~~~ til;-\~-t--------------,
•
-0
+$
2YK
0
MUX
II
EP 7
+5~
,-R.,-OK 10
:
470
f--<>+'. e'9
03t
.0'1"
+0
'''rr.~~LY
9
1
::"rrLT:R
8 r--
120
12~e6
0'8-2
::: s"
~r14
~2__-+____--I'1f--41____---,
,..-.'-f----I------L-------,
~
r+-t-____t---__-"2x"-"Vee"O____++_
DIVIDER
.•~: ~~
5 Db 10 0h~
+5
R9
e DO~
00~I-F"""--,1
R26-S
;4.7 I.'
A.1
"~"V
I ~~8'i------~~===+-_______
27
'\" • ________:..4
B
150
L __
C05
~l-'-'-------------,
,. -
41
"7::~'2 ~
+12
+12
~
1
~
C
''.?,'
~~:.
.~:'
13
~
L
J'
,:~
3
II
"
112 74153
PHASE
R'.-O COMPARIlOR
~
o
rb~
+,
R28-5
rL
• '8 4
ll~I ,t'+~·~~~~~~~L~~Y==dL=d+;:J[[~
120 D41_ 11
~
K
443
HO
7~14
7486
....
RC: f'~"'-:-O-++-H-t------t-t-----+1f-J
CLK ~
HLlf.!':!.j'--+++++-----HI----f-l
vee
4
R14
-f_-,-7~'7.
""TRKO 12
.
'1" ~
--------.J
~
r---f--"0q '0 I 160
'iIDA'TA"17
~ 017
1
Lt+----------------------HH-t--------------------------------+------+-------.......
1~
"..;.5050-fr-'::J READV 8
..
+
• ,-_______________
H~L:D~·~·==[t!11~~~~Jl--J1~~~~--------------~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
RD
'--_-+_.=...Q7
~
,
R46
+5
~
6
5
~
"
11 ~
t2
5
"'N
V-
T643
Di---------------------+-----------r--+------t-t-r-----+-t--tl-----~~~_L.;.,8/
3 JI-..! os
11
[-h"f"
+
e
t~ 7420
f--M- •
-~2'4
0'
33K
'OCO~~2
r
5 ~
2
3
8
R3
, 555 7
820K
7404
[;d..
rfr~ltt~[~~~~~~~~~~~~~~~~~~~~~~~~jMO~'~OR~O:Nj~~]~~~~~~~Jj~t~~t::::~J:i~[:l::J~:~j~il
~ ~T_.
'~.
;:~ 2".ti'::; ".~~:" ~'. ::
>:
~
~
",---~
____--",A6'--"-o' 1'"
• 0 a'O "0
r4-- 74LS14
~r,-:4-0-4-'0-=::'-1-"-o: E-L~_·____-++t--........-~~-~t=.=-=-=-=--"'R-W~.~--~ II
Ae
I
+5
.IT
r
11 74
0'
'3 r-;=============~
1~r.,.:' It ,OK
R2e.2
r---------------....J
14
+ 15
r-·D'"R"CH"'O.-----------....J
I
,-='-'-"'=-------------"'-{> 4
+.
~123
1
3
~
B33~~.:=+==4't::.2j
8
91 8
~ 47 .r;;-~ ~"·-'TT-71..:=;4'-7.::.~r·---'2.,r"-0
4-;'-'2-,-i~ _____ ~
':
+~
~r:;--t----';','-I7430
A
16
15
I
+s
____________________________________________________________-,
+.
h
ORAWN
APPROVALS
CHECKED
Err
;;f:':w-
DATE
DOUBLE DENSITY DISK CONTROLLER
5/3/79
5/23/79
SIZE I COOE 10ENT NO. IORAWING NO
D
SCALE
090-078-B
NONE
SHEET 1
OF'
7438
•
D53
Ds4
100
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