8.4.3a_Transient_Behavior_of_a_High_Speed_Tunnel Diode_Switching_Circuit_1963 8.4.3a Transient Behavior Of A High Speed Tunnel Diode Switching Circuit 1963
8.4.3a_Transient_Behavior_of_a_High_Speed_Tunnel-Diode_Switching_Circuit_1963 8.4.3a_Transient_Behavior_of_a_High_Speed_Tunnel-Diode_Switching_Circuit_1963
User Manual: 8.4.3a_Transient_Behavior_of_a_High_Speed_Tunnel-Diode_Switching_Circuit_1963
Open the PDF directly: View PDF 
.
Page Count: 12
| Download | |
| Open PDF In Browser | View PDF |
- . - ~' -~J''''' :.~;..t>.~' . '.' ' "t' • ~-. >. ~~. ' . , .-. ~ ~: <' :~ • ' ~. 'I~ • '/t. ~:;;, • _ ~ ..~.,~ A STUDY OF THE TRANSIENT BEHAVIOR OF A HIGH SPEED TUNNEL-DIODE SWITCHING CIRCUIT USING AN ANALOG COMPUTER by GEORGE HANNAUER Electronic Associates, Inc. TABLE OF CONTENTS Page Section I ANALYSIS OF SWITCHING CIRCUIT . . . . . . . . . . . . . . . . . . 2 II THE MATHEMATICAL MODEL . . . . . . . . . . . . . . . . . . . . . 4 III THE COMPUTER PROGRAM . . . . . . . . . . . . . . . . . . . . . . . 5 Solving for the Derivatives il and i2 . . . . . . . . . . . . . .. Generation of the Characteristic Curve . . . . . . . . . . . .. Circuit Diagram, Figure 4 . . . . . . . . . . . . . . . . . . . . . Potentiometer Sheet, Figure 5 . . . . . . . . . . . . . . . . . .. Amplifier Sheet, Figure 6 . . . . . . . . . . . . . . . . . . . . .. Tables.... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 6 7 8 8 a. b. c. Summary of Variables, Table 2 . . . . . . . . . . . . . . . Summary of Units Used, Table 3. . . . . . . . . . . . . .. Summary of Parameter Values. Table 4. . . . . . . . .. 9 9 9 Static Check Calculations . . . . . . . . . . . . . . . . . . . . . . 9 IV RESULTS AND CONCLUSIONS. . . . . . . . . . . . . . . . . . . . .. 10 V REFERENCES. . . . . . . . . . . . . . . . . . . . • . . . . . . . . . .. 12 A. B. C. D. E. F. G. Printe d in U. S. A. 1 Bulletin Number ALAC- 6348 TABLE OF CONTENTS Section Page I ANALYSIS OF SWITCHING cmCUIT .•.•••••••••••••• 1 IT THE MATHEMATICAL MODEL ..••••.•..•.•••••.•• 3 ill THE COMPUTER PROGRAM ••••••••••••••••••.•• 3 A. B. C. D. E. Solving for the Derivatives 11 and 12 • • Generation of the Characteristic Curve Circuit Diagram, Figure 4 • • • • • • • • Potentiometer Sheet, Figure 5. • • • • • Amplifier Sheet, Figure 6. • • • • • • • • • • • • • 3 4 5 6 7 F. Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 a. b. c. Summary of Variables, Table 2 • • • • • • • • • • • • • • Summary of Units Used, Table 3 • • • • • • • • • • • • • Summary of Parameter Values, Table 4 • • • • • • • • 8 8 8 Static Check Calculations ••• ; • • • • • • • • • • • • • • • • • 8 IV RESULTS AND CONCLUSIONS •••••••••••••••••••• 9 V REFERENCES • • • • • • • • . . • • • . • • • . • • • • • • • • • • • • • 10 G. • . • • • . • • • • . • • • • • • • • • • • • • • • • • • • . • • • • • • • • • • • • • • • • • • • . • • • • A STUDY OF THE TRANSIENT BEHAVIOR OF A HIGH SPEED TUNNEL-DIODE SWITCHING CIRCUIT USING AN ANALOG COMPUTER by GEORGE HANNAUER Electronic Associates, Inc. Assume V+ and V_are initially zero and that V + gradually increases while V_decreases, such that V+ + V_ = O. Then the operating point of each diode will move from the origin in Figure 2 along the characteristic curve toward the peak. The voltage at the junction will remain zero, as before. After the peak has been passed, the voltages and currents for the two diodes should remain identical (by symmetry), and the voltage at the junction should remain zero. However, since the diodes are now in their negative resistance region, this equilibrium will prove extremely unstable. I. ANALYSIS OF SWITCHING CIRCUIT The switching circuit is best understood by reference to the simplified schematic drawing in Figure 1. The voltages V+ and V_are bias voltages provided by an external source, and are assumed to be equal in magnitude and opposite in polarity. The tunnel diodes TD1 and TD2 are identical. If no inputs or loads are connected to the circuit, the same current will flow through both diodes. If the volt-ampere curve of the diodes always exhibits a positive resistance characteristic, the voltage drops across the diodes will be identical, and the voltage at the juncture of the diodes will be zero. Figure 1. Simplified Schematic for Tunnel-Diode Switching Circuit Suppose, for instance, that the circuit is unbalanced by a small positive voltage at the input terminal. Then tunnel diode #2 will have a slightly greater voltage across it than tunnel diode #1, and as the bias voltage increases, tunnel diode #2 will pass its peak first. Further increases in the voltage across TD2 will result in a decrease in the current through it, and hence a decrease in the current through TD1 as well. Since TDI is still in its positive resistance region, a decrease in its current will decrease its voltage drop, increasing the voltage drop across TD2 (since the tunnel diodes are acting as a voltage divider, and the sum of their voltage drops must equal 2V +). It follows that TD2 will move rapidly through its negative resistance region, at a speed limited only by circuit reactances, and stabilize somewhere in the positive resistance region above 300 millivolts, while TDI stabilizes in the positive resistance region below 60 millivolts. The characteristic curve of a typical tunnel diode is given in Figure 2. Note that the slope is negative over the greater portion of the operating range (from about 60 to 300 millivolts). The existence of this negative resistance region means that the equilibrium described in the preceding paragraph will be unstable. A very slight disturbance will upset the summetry described above, causing a very much larger voltage to appear across one diode than across the other. This sensitivity to small input disturbances enables the circuit to function as a high-gain high-speed switch. Since most of the voltage drop between the two bias sources appears across TD2, it follows that the voltage at the junction (the output voltage) will be positive. A positive input voltage will therefore produce a positive output voltage. The output voltage will be of the same order of magnitude as the bias voltage V+, while the input voltage need only be large enough to overcome any inherent imbalance in the diode characteristics. The input voltage can thus be made very small, and the gain of the circuit is limited only by the closeness of the match between diode characteristics and between TDI Vin V out ~TD2---~ LOAD V- 1 ....... en ~ en a.. 0 > IJJ ...J CD 10- I- 0:: IJJ W 0:: 0:: I:) :z 6 :) 0... U :2: 0 IJJ 0 u 4 r---I ~ .... 0 L--I 50 ...J ...J « 0:: ~ « 2 0 5 30 20 ...J IJJ Z :z 10 :) I- 0 0 0 50 100 150 250 200 300 Vo = TUNNEL DIODE VOLTAGE 0 +1 +2 +3 +4 [VO/50] +5 t +6 350 400 450 500 ( MILLIVOLTS) +7 +8 . +9 +10 COMPUTER VARIABLE ( VOLTS) Figure 2. Tunnel-Diode Characteristic Curve the positive and negative power supplies. If the input and output voltages are equal in magnitude, as is the case with cascaded logic elements of similar design, high gain means that very large resistors can be used, resulting in very large fan-in and fan-out figures. be large enough to unbalance a symmetric circuit. If all components were perfectly matched, the slightest input disturbance would unbalance the circuit in the proper direction, and the theoretical gain would be infinite. In practice, the gain will be limited by component tolerances. An estimate of the gain (or, equivalently, the fan-in/fan-out capability) of the circuit can be made from a static analysis of the tunnel-diode characteristic and a knowledge of circuit tolerances. Such an analysis has been made by Chow (4) who predicted large gains for closely matched diodes. In high-speed logic and arithmetic circuits, the voltages V+ and V_will be out-of-phase alternating voltages with approximately sinusoidal waveshapes, D-C levels will be superimposed on these sinusoids and, in most applications, this bias will just equal the amplitude of oscillation assuring that the bias voltages do not change sign. The alternating bias voltages will then serve as a "clock," supplying the necessary timing signals for high-speed arithmetic and logic. An output can be obtained only during that part of the bias cycle when the bias voltage is large enough to switch one of the diodes into its negative resistance region. The attractiveness of this circuit for digital applications lies in the fact that the input need only The above analysis is essentially static. For design purposes, a dynamiC analysis, which takes circuit reactances into account, is necessary for at least two reasons: 1. A knowledge of the switching time is necessary to determine the maximum clock frequency (i.e., the maximum rate of information transfer) at which the system can be operated. 2 2. Since the circuit contains two negative-resistance elements, it may well prOve unstable. Instead of the switching behavior described above, the system may break into oscillations. = VI . (5) 2 I -I 1 Dl (6) 1 (7) 2 I -I 2 D2 f(V D ) 1 (8) 1 f(V D ) 2 (9) = (I1-I2+Iin)RL V out (10) IC = IC ID = ID 2 2 12 r 2+L 212 -M \+VD2-Vout R. (11) In Equation 11 was omitted for the purposes of this simulation, and replaced by the assumption that the input current lin was constant, Values from 0.5 up to 2.0 rna, were tried. The assumption of constant input current implies a constant-current source, which is not very realistic. This simplification is not necessary, and equation 11 could be programmed directly by adding one additional summer and one inverter to the analog circuit, The simplification was made in the present study so that the results could be compared directly with Herzog's digital solution (Ref. 2), since Herzog also made this assumption. The equations describing the system are given below. These equations are straightforward applications of Kirchoff's laws and the known properties of resistors, capaCitors, and inductors, They may be written down immediately upon inspection of Figure 3, -V V. -V In out Equations 1 and 2 are Kirchoff voltage equations for the two major loops, Equation 3 is simply the statement that the bias or "clock" voltages are out-of-phase sinusoids with DC levels superimposed, Equations 4 and 5 state the basic voltampere relation of a capacitor, and 6 and 7 are Kirchoff current equations, Equations 8 and 9 state the characteristic relation between voltage and current in the tunnel diodes (see Figure 2). On the computer, these curves will be represented by function generators. Equations 10 and 11 are, of course, statements of Ohm's Law. II, THE MATHEMATICAL MODEL (2) = - VD Experimentation with the actual circuit is possible, but extremely difficult due to the high frequencies inVOlved (the range of clock frequencies to be investigated is from 100 to 1000 mc.). The basic Simplicity of the equivalent circuit makes it easy to write equations to describe the system and thus study the mathematical model (the equations) rather than the system itself, (1) (3) 1 I C2 C2 1 . Figure 3. Equivalent Circuit Showing Reactances . . . • EDC-A sin wt (4) In II r 1+ L1 11- M 12+VD +V out = 1 I C 1 C1 1. VI 2 = - VD Both the stability and the switching time will depend primarily on the inevitable circuit reactances. Figure 3 shows the equivalent circuit for the system, with circuit reactances and external loading taken into account. The prinCipal reactances involved are lead inductance and case inductance (which may be lumped together) and diode shunt capacitance. Provision is also included for coupling the leads together with mutual'inductance, which would correspond to dressing the power supply leads close together during construction. A moderate amount of coupling proves to have a beneficial effect on switching time when the circuit is operated at high frequencies. -V III. THE COMPUTER PROGRAM 1 A. Solving for the Derivatives i1 and i2 The first step in deriving a computer program is 3 to solve all differential equations for the highest derivatives. This has already been done in equations 4 and 5, but equations 1 and 2 contain the derivatives i1 and i 2 , and each ~erivat~ve appears in both equations. To solve for 11 and 12, we must treat these as a simultaneous system of two equations in two unknowns. This system maybe solved by determinants, but the resulting computer circuit would be unnecessarily complex. A far simpler approach is to solve equation 1 for i1 and equation 2 for i 2 , giving • 1 • I =-(V-I r+MI-V -V ) 1 L1 1 1 1 2 D lout i2 1 L2 = -(-V • -I r +MI·-V +V ) 2 2 2 1 D2 out t:ional power. This expression, which was obtained . from a separate digital computer run by curvefitting, can be programmed with standard subroutines. On an analog computer, the best approach is straightforward use of a standard function generator. The diode function generator (DFG) uses biased diode networks to approximate a curve by straightline segments. On the TR-48 variable-breakpoint DFG, eleven segments are available. The breakpoints (corners) of the curve may be varied so as to group many short straight-line segments together where the graph curves most sharply and use fewer segments where the graph is straighter. In this way, an over-all accuracy of about 1% is maintained for this particular curve. (1 *) (2*) TABLE 1 SETUP TABLE FOR VARIABLE DFG These equations give i1 in terms of i2 and vice versa. Programming them directly leads to an algebraic loop (a loop with no integrators), and since this is a two-amplifier loop, positive feedback is present. For stability, we must have a loop gain of less than one (Ref 5). By inspection of the circuit, it is easily seen that the loop gain is M2 /L1 1,2' Since this is always less than one on physical grou~ds, t~e loop is stable and the correct values of 11 and 12 may be obtained without determinants (Reference 6). B. Generating the Characteristic Curve INPUT (VOLTS) OUTPUT (VOLTS) 0.00 0.35 0.85 1. 10 1. 45 2.85 3.85 6.20 7.90 8.55 9.00 9.50 0.00 5.81 9.34 9.93 9.36 3.67 1. 69 0.89 1.56 3.20 6.75 12.00 The tunnel-diode characteristic in Figure 2 presents a problem in function generation no matter which simulation method is used. On adigitalcomputer, the function values can be stored in main memory in tabular form, perhaps with an interpolation subroutine to fill in the gaps between tabulated values. If enough values and/or a sufficiently sophisticated interpolation scheme are stored, a tremendous demand is made upon the memory, If the digital computer is not called upon to solve the dynamic equations as well, this is an acceptable technique. This was the approach used by Axelrod (3). The simulation was essentially analog, with the digital cOP.juter serving only as 11 function generator. Table 1 gives the appropriate breakpoints and the corresponding function values. Note that one of the DFG's must accept the input -VDl/50 and produce the output + ID1/5. Its input-output graph will look like Figure 2 reflected around the vertical axis. The appropriate table is obtained from Table 1 by making all the input voltages negative. The second DFG accepts positive inputs and produces negative outputs; its graph looks like Figure 2 reflected around the horizontal axis. Herzog (4) uses a digital computer for the entire problem. The characteristic curve is represented by an analytic expression of four terms involving a polynomial, two exponential functions and afrac- The volt-ampere curve in Figure 2 requires very sharp changes of slope. Since these sharp slopes exceed the capabilities of the DFG, apotentiometer must be placed in the feedback path of the output amplifier to increase the gain of the DFG. 4 I 100C I /3 -10 TEST ~ /10/3 I -10 04 +10 TEST +1 02 ")---.------110 -10 TEST --L +10 eC ; r - - - - ' - - - - / II ~ R -10 TEST r2 /10 L-~------------~16~------------------------~ I IOOC 2 /3 Figure 4. Analog Computer Circuit Diagram ELECTRONIC EDUCATION TR-48 a ASSOCIATES TRAINING INC. GROUP POTENTIOMETER ASSIGNMENT SHEET POO- P29 b/llfn~ DATE PROBLEM SETTING STATIC CHECK PARAMETER DESCRIPTION POT NO 02 2 L, /5 2L·L/5 'l M/5 03 2M/5" 04 I/IO{J 05 06 1/ RL I IN /50 07 I/IOOC, 08 1/100 Cl (3 I.('A07 00 01 09 10 - f-.- II W/f3 w/(3 12 ___4-1/3 13 ~ -- SETTING RUN NUMBER I NOTES POT NO .160 +0.166 00 -0.1340·00 0.00 -0· 20 -0.02 +0.20 01 -0.97 07 +0.97 -6.40 -1·88 08 ·160 0.000 0·000 .020 .125 .020 .200 .200 .640 .188 B STATIC CHECK OUTPUT V0LTAGE Tu~N5:l= DIQQE 02 03 04 05 06 ARTIFICIAL I.e. TEST ONI.Y 09 10 ·188 -1,20 ·800 +0.83 ·800 -0·67 II 12 13 14 14 15 rl/IO .300 -1.50 15 16 rl. /10 A/500 Eoc /500 ·300 +1.50 ·250 +1.60 16 17 18 ,260 ·260 -2.60 17 18 19 19 1/50 I 1(0) I/SO Ill. (0) I Iisoo VOl (0) I/SOO IVp2. (0) I 20 21 22 r- 23 .500 -5.00 .500 +5.00 20 ·100 t1.00 22 .100 -/.00 23 21 24 24 25 'Izo .050 +0.49 25 26 '/lO .050 -0.49 26 27 27 28 28 l>< SWITCH # I LEFT 29 M654 Figure 5. Potentiometer Assignment Sheet 6 ELECTRONIC ASSOCIATES INC. EDUCATION a TRAINING GROUP TR -48 AMPLIFIER ASSIGNMENT SHEET DATE _--=b...L..I---,'IL-0_3_ _ _ _ __ AOO- A23 PROBLEM _TlJ..!Uo.!.!N~N!.:!..IE=...!-L~D~I~Q~D..!:::E'___ _ STATIC CHECK AMP NO. OUTPUT VARIABLE FB CALCUl.ATED CHECK PT. OUTPUT t9.84 01 H +ID,/5 02 I +t 03 - - 10 sin 04 H - 11 /200 +1 ·0375 05 H + 12./ 200 - 0.8375 06 J j -10 cos wt tl.20 -10.00 tlO sin wt +1.88 +6·40 07 08 +0.20 +10.00 . wt -6.40 use INPUT RESISTORS WITH PART OF DFG 09 H -I Dl /5 -g.84- 10 - -Ills -5.00 II - +Il/S +5.00 12 2: + Iel/S -4.84- 13 I -Ic2. /5 +4.84- 14 / -VDI /50 f +V0 2 Iso 15 . +9.68 -1.00 -9.68 +1.00 16 2 VJ.. _-'1'1 50- 50 17 H -VOUT/SO -0.16 18 - V2/SO -1.00 f I +II/S -8.30 +5.00 -I2/5 t6.10 -5.00 +1.00 19 20 21 OUTPUT USE INPUT REOSISTOR5 WITH 04- PART OF DFG 00 NOTES MEASURED CHECI( PT. 22 23 M653 Figure 6. Amplifier Assignment Sheet 7 OJ TABLE 2 SUMMARY OF VARIABLES Original Variable Max Value Scale factor : Scaled Variable 500 mv 1 Volt/mv 50 J~ l50 50 rna 1 5 Volt/rna Tl l5 I 50 rna 1 5 Volt/rna ~~ I] 2000 mains 1 200 50 rna 1 5 {3 Volt/mains = +50 rJC 8 ohms C2 10- 2 nanofarads L2 = 0.4 nanohenry For static check calculations, convenient values are selected for all integrator output signals (in this case II, 12, VDl' and VD2) and for the driving functions, VI, V2 , and lin' These values may be chosen arbitrarily, but they should be small enough to avoid amplifier overloads and large enough to provide amplifier output signals that can be measured with reasonable accuracy. The values cho sen were: VD2 iJ r 2 = 3 ohms M ~v'LT I. 1. 0 mao A 130 millivolts Edc 130 millivolts f 150 megacycles/second = 0.15 cycles/nanosecond w 27rf = 0.9425 radians/no S. G. Sun1mary of Static Check Conditions 12 = +25 rna. ] TABLE 4 SUMMARY OF PARAMETERS The use of the somewhat unusual units for inductance and capf!-citance gu~rantees that the equations I = CV and V = LI will hold in this system of units. VDl = +50 mv. D 5 seconds machine time 1 nanosecond problem time Voltage: millivolts Current: milliamps Resistance: ohms Inductance: nanohenries (10- 9 henry) Capacitance: nanofarads (10- 9 farad) Time: nanoseconds (10- 9 sec) II = +25 rna. ;L200 ~Il :l? Volt/rna TABLE 3. SUMMARY OF UNITS OF MEASUREMENT USED Note: . [1 V] In mv. 8 1 2 Try M = 0 for first run. Probable maximum value around O. 2 nanohenry. VI = +50 mv. VI = L1 i1 - Mi2 lin = + 1.0 mao -V2 = L2i2 -Mil Solving by determinants: Parameter values are the same as those for the first run. The values for all variables may be calculated from equations 1 - 10. These values are given below. = +49.2 ID1 = +49.2 mao ID2 IC1 = -24.2 mao IC2 = -24.2 mao = -207.50 milliamps/nanosecond 12 = -167.50 milliamps/nanosecond. . L L _M 2 1 2 h =.0.4 nanohenry and M = 0.2 nanohenry, then II = 12 + 250.0 milliamps/nanosecond. The output of amplifier 04 should be -i l /200 = -1.25 volts, and the output of amplifier 05 should be + 1.25 volts. IV. RESULTS AND CONCLUSIONS = -2420 millivolts/nanosecond .II 1 If we let VI = 50 mv, V2 = -50 mv, Ll = mao The derivatives may be calculated from equations 1 *, 2*, 4, and 5. These are: VD2 1 2 L 1 L 2 -M Vout = +8 mv. "D1 = -L V +MV • V1 L 2-MV 2 II = 2 The switching transients and output wave shape s for constant input current are shown ih Figures 7 and 8. Note in particular that at 300 megacycles the output voltage goes through an initial oscillation before switching. The output is high for only a short period of time late in the bias cycle. At 150 megacycles, the output rises much more sharply and gives a good waveshape. All variables that have been calculated can now be translated into amplifier output voltages. These voltages appear on the amplifier assignment sheet. They may be checked against values calculated on the circuit diagram (to check the programming and scaling) and later checked against actual measured voltages on the computer (to check the patching and the functioning of the components). The checkpoints should also be calculated and measured for integrators. (The checkpoint of an integrator is minus the sum of its input voltages. It may be read out by patching the summing junction of the integrator temporarily to the summing junction of a summing amplifier that is not being used in the problem). These calculated values are also tabulated in the amplifier assignment sheet. 200 100 f:z 150mc BIAS VOLTAGE_ 2 3 4 5 6 7 B time - nanoseconds The initial condition voltages marked "Test" are for static test purposes only, and not forthe actual run. They should be removed prior to the first run. Figure 7. Output Wave shape of Switching Circuit at 150 Megacycle Clock Frequency Note that the static test value of the mutual ind1lctance M is zero. This value was chosen to break the algebraic loop in the static test mode, since otherwise it would be very hard to troubleshoot. However, this static test value does not check the algebraic loop itself, and a supplementary test should be included with M f. O. For this supplementary test, we may as well assume that the artificial initial conditions on voltages and currents are zero, since this part of the circuit has already been checked by the main static check. Eqaations 1 and 2 then become: 200 100 2 3 4 6 7 time - nanoseconds Figure 8. Output Wave shape at 300 Megacycle Clock Frequency 9 B only 50 milliseconds -- effectively zero solution time as far as the operator is concerned. Operation at 300 megacycles is possible, but marginal. Further experimentation with the model indicates that for reliable operation with sufficiently large fan in/fan out capability the circuit should not be operated above about 200 or 250 megacycles. c. Even more important than running time per se is the time required to obtain meaningful and useful results. The output of the analog unit is a continuous graph, drawn in ink on 11 x 17" paper . . . a form of output which an engineer can readily observe and interpret. By contrast, the digital results were obtained from an on-line printer, and considerable manual effort was required to translate these results into graphical form. It is significant that a preliminarypencil-and-paper analysis indicated that the system ought to operate at frequencies up to 1000 megacycles. A circuit designed to operate at this frequency would not function properly and would be extremely hard to troubleshoot, due to the circuit loading of the measuring devices. The computer solution facilitates fundamental understanding of the nature of the switching process, as well as providing actual solutions. The ease of parameter changing on the analog computer makes it especially easy to investigate the trade-off between gain (Le. fan in/fan out capability) and frequency. Of course, on-line devices are available for producing graphical readout from a digital computer. Some of Herzog's graphical results were obtained by oscilloscope photography. Although this method eliminates the tedium of point-plotting, it ismessy and time-consuming, and offers limited resolution. Perhaps the best form of readout (certainly the most convenient) involves the use of a digital-toanalog converter and an analog X- Y plotter. While this method is acceptable, it requires expensive conversion eqUipment to translate the data into analog voltages for plotting. Such conversion equipment is unnecessary with the TR-48 computer since the signal is an analog voltage in the first place. The results agree quite well with Herzog's digital simulation, using the Edsac II computer at Cambridge University, and for further analysis of the results, the reader is referred to Herzog's paper (2). It is instructive to compare the two simulations from the point of view of flexibility and convenience. a, The digital program requires the equations to be written as a set of first-order equations, solved for the highest derivatives, and t11en converted into algebraic equations by the Runge-Kutta or a'similar integration scheme. While standard software is available in many installations to simplify this task, it is completely eliminated in an analog similation, since the analog solves differential equations ~ differential equations, b. The running time for the Edsac II was, according to Herzog, about three minutes per solution, as opposed to 25 seconds on the TR-48 computer -- a speed advantage of seven to one. Nothingprecludes running even faster than this, since the components are operating well within their frequency-response limitations. The solution also can be run in repetitive operation, in which case the solution takes d. Since only about half of the computing capacity of the TR-48 computer is used, the simulation can easily be expanded to take additional effects into account. Herzog's equations assumed a constant current input and ignored the fact that the load is not purely resistive. These simplifications could easily be removed on an analog simulation by addition of a few more amplifiers and potentiometers. On a digital computer, any additional complexity in the equations would increase the running time. An attractive alternative, for example, would be to simulate an additional tunnel-diode circuit on the analog computer and feed the output of the first into the second. This would enable the designer to determine how flat the output wave shape of the first cirCuit would have to be in order to trigger the second successfully. V. REFERENCES 1. Gibson, J.J. "An Analysis of the Effects of Reactances on the Performance of the Tunnel-Diode Balanced Pair Logic Circuit" RCA Review, December, 1962, p. 457. ~'o.~~rzog, G.B. "Tunnel-Diode Balanced Pair Switching Analysis" RCA Review, June, 1962, Vol. XXIII, 3. Axelrod, Barber and Rosenheim "&>me New High-Speed Tunnel-diode Logic Circuits" mM Journal April, 1962. ' 4. Chow, W.F. "TWillel-Diode Digital Circuits" IRE Transactions on Electronic Computers Vol EC 9 September, 1960, page 295. ' • , 5. Rogers, A.E. and T.W. Connolly, "Analog Computation in Engineering Design" McGraw-Hill 1960 Chapter 6, ' , 6. Hannauer, G., "Algebraic Loops", E&T Memo #22, Electronic ASSOCiates, Inc., P.O. Box 582, Princeton, N.J, r 10 ELECTRONIC ASSOCIATES, INC. Long Branch, New Jersey ADVANCED SYSTEMS ANALYSIS AND COMPUTATION SERVICES/ANALOG COMPUTERS/HYBRID ANALOG-DIGITAL COMPUTATION EQUIPMENT/SIMULATION SYSTEMS/ SCIENTIFIC AND LABORATORY INSTRUMENTS/INDUSTRIAL PROCESS CONTROl SYSTEMS/PHOTOGRAMMETRIC EQUIPMENT/RANGE INSTRUMENTATION SYSTEMS/TEST AND CHECK-OUT SYSTEMS/MILITARY AND INDUSTRIAL RESEARCH AND DEVElOPMENT SERVICES/FIELD ENGINEERING AND EQUIPMENT MAINTENANCE SERVICES.
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37 Create Date : 2014:12:14 18:44:05-08:00 Modify Date : 2014:12:14 18:07:31-08:00 Metadata Date : 2014:12:14 18:07:31-08:00 Producer : Adobe Acrobat 9.55 Paper Capture Plug-in Format : application/pdf Document ID : uuid:61d3c5d7-4f8d-7748-ac1f-dd9d3cf31d23 Instance ID : uuid:0399babc-9cc7-ad49-aa17-9a5d85103639 Page Layout : SinglePage Page Mode : UseNone Page Count : 12EXIF Metadata provided by EXIF.tools