# A22 6881 2_360 40_func Char 2 360 40 Func

### A22-6881-2_360-40_funcChar A22-6881-2_360-40_funcChar

User Manual: A22-6881-2_360-40_funcChar

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File No. S360-01
Form A22-6881-2

Systems Reference Library

IBM System/360 Model 40
Functional Characteristics
This manual presents the organization, characteristics, functions
and features unique to the IBM System/360 Model 40. Major
areas described are system structure, generalized information
flow, standard and optional features, system control panel, instruction timings, and channel characteristics and functional
evaluation.
Descriptions of specific input!output devices used with the
IBM System/360 Model 40 appear in separate publications. Configurators for the IBM 2040 Processing Unit and I/O devices are
available. See IBM System/360 Bibliography, Form A22-6822.
It is assumed that the reader has a knowledge of the System/
360 as defined in the IBM System/360 Principles of Operation,
Form A22-6821 and the IBM System Summary, Form A22-6810.

SECOND EDITION

This is a major revision of, and obsoletes, Forms A22-6881-0 and A22-6881-1, and Tech.
data in channel evaluation factors, autopolling data for IBM 2702, revision of 2702 worksheet example; an additional load limits table on multpilexer in burst mode is included,
as is channel-to-channel feature information. Address switching has been clarified, all
instruction timings (including floating-point) have been revised. An index has been added.
Changes to the text are indicated by a vertical line to the left of the change; revised
illustrations are denoted by the symbol • to the left of the caption.
Significant changes or additions to the specifications contained in this publication are continually being made. When using this publication in connection with the operation of IBM
equipment, check the latest SRL Newsletter for revisions or contact the local IBM branch
office.

Requests for copies of mM publications should be made to your
sentative or to the IBM branch office serving your locality.

mM

repre-

This manual has been prepared by the IBM Systems Development Division,
Product Publications, Dept. B98, P.O. Box 390, Poughkeepsie, N.Y. 12602. A
form is provided at the back of this publication for readers' comments. If the
form has been removed, comments may be sent to the above address.

Contents

5

System Description ........ .......................................................
2040 Processing Unit ................................................................
Main Storage .........................................................................
Arithmetic Logic Unit ..........................................................
Local storage ........... f..............................................................
General Registers ..................................................................
Floating-Point Registers ......................................................
Channels ....................................................................................
Channel-to-Channel Feature ................................ ...............
Multiplexer Channel................ ...........................
Selector Channel ........ .... .................................. ...................
System Control Panel .. .... .. .. .. .. .. .. .. .. .... ................. .................
Instruction Configurations
...... .......... ........ ....... ..................
Interruption Times
............... .........................................
External Interruption ............................................................
Supervisor Call Interruption
.....................................
Program Interruption ................ ...............................
... ..... .. ........ .
Machine Check Interruption
I/O Interruption
... ..... ........ .......................................

5
5
7
7
7
7
7
7
7
7
9
9
9
9
9
9
9
9
9

System Control PaneL............................. ............................
System Control Functions ....................................................
System Reset .......................................................................
......................................
Store and Display
... ............................... .......
System Control Panel Controls
.... ...... ..... ..................
Operator Controls .. ......... .....
.. .. .. .. .......... ...
Operator Intervention Controls
Key Switch and Meters ............... ................. ...................

10
10
10
10
11
11
11
13
17

Channel Characteristics and Functional Evaluation...
General Channel Information
.. ................ ..
Channel Control ................ ..
...................... ......
Channel Registers
......................................
Chaining ............ ...... .................................................
Fetching Channel Command Words
Data Chaining in Gaps
Late Command Chaining
..................

18
18
18
19
19
19
20
20
20

Channel Implementation ........... ............................ .
21
Channel Priority
....................... ..
21
........... 21
Multiplexer Subchannels .............................. ..

Concurrent Input/Output Capabilities ..........................
Conventions for Satisfactory Channel Programs ................

22
22
22
25

Overrun Test Exception
.............................
Overrun Test Procedures ....................................................
One Channel Overrun Tests
..... ..........
Two Channel Overrun Tests
........ ...................

26
26
27
27
27

Multiplex Mode Considerations ..............................................
Device Waiting Time
................... ..............................
Device Pri.ority on Multiplexer Channel ........... ................
Interference from Priority Devices .......... .....................
Multiplex Mode Evaluation Procedure . .....
.................
Worksheet Entries for 2821 .....
. ................
IBM 2702 Considerations ... ................ .......
Special Analysis of 2702 Performance ................
..
Synchronization Tendency of Buffer Servicing.

30
30
30
30
30
31
34
35
35
36
39

Channel Interference with CPU .
Channel Interference Procedure
Available CPU Time Example

41
41
41

System/360 Model 40 Instruction Times ................
Timing Considerations
.. .......... ..........
Timing Assumptions ..... ..
...... .. ............ ................ ....
Average Times ...... ...............................................
Legend for System/360 Timing ( Average Times)
Fixed and Floating-Point Arithmetic, Logical and
Branching Operations
.. .. ..................
Execute Instruction
.............................................
Convert Instructions
........... ..............
Binary Shift Operations
......................................
Variable Field Length Instructions - Average Times
Input/Output Operations
..............................
Variable Field Length Instructions - Timing Formulas Detailed Times ............. ................... ........ .. ... .. .. .. ..
Legend for System/360 Timing (Detail VFL Times)

44
44
44
44
50

Appendix ....................... .
Index ...................................... .

50
51
51
51
52
53
53
54

.. ......................................... 57

....... 111

IBM System/360 Model 40

System Description

The IBM System/360 Model 40 is one of a series of
models of compatible, general purpose, data processing systems designed for commercial, scientific, communications or control applications. The Model 40 includes the advantages, characteristics and functional
logic established for the System/360, as defined in the
IBM System/360 Principles of Operation, Form
A22-6821.
The basic structure of a System/360 Model 40 consists of a 2040 Processing Unit, main storage, and multiplexer channel with input/output devices attached to
the channel through control units (Figure 1). There
are five models of the Model 40 termed D40, E40,
F4.D, G40 and H40. These five models differ only in
the amount of main storage required with a 2040 Processing Unit. The significant differences are:
IBM SYSTEM/
360 MODEL

PROCESSING
UNIT
MODEL

D40

2040D

E40

2040E

F40

2040F

G40

2040G

H40

2040H

DESCRIPTION

16,384 bytes of main storage
16 multiplexer subchannels
32,768 bytes of main storage
32 multiplexer subchannels
65,536 bytes of main storage
64 multiplexer subchannels
131,072 bytes of main storage
128 multiplexer sub channels
262,144 bytes of main storage
128 multiplexer subchannels

The system control panel is located at one end of
the 2040 Processing Unit. Standard features for any
System/360 Model 40 include:
Multiplexer channel
Standard instruction set
Interval timer

Optional features for any Model 40 system include:
Decimal arithmetic instruction set
Floating-point arithmetic instruction set
Storage protection (store protection only)
Direct control
Selector channels (one or two)
1401/1460 Compatibility feature
141017010 Compatibility feature
1052 Adapter, 1052 Printer-Keyboard (console typewriter)
Emergency power-off control (multisystem)

The 1401/1460 compatibility feature is optional for
models E40, F40, G40, and H40. The 1311 compatibility feature is available with the 1401/1460 compatibility feature for models F40, G40, and H40.
The 1410/7010 compatibility feature is optional for

models F40, G40, and H40. The 1311 compatibility
feature is available with the 1410/7010 compatibility
feature.
A variety of control units and input/output devices
are available for use with the Model 40. Descriptions
of specific input/output devices appear in separate
publications. Configurators for the I/O devices and
system components are also available. See IBM System/360 Bibliography, Form A22-6822.

2040 Processing Unit
The 2040 Processing Unit contains the facilities for
addressing main storage, for fetching or storing information, for arithmetic and logical processing of data,
for sequencing instructions in the desired order, and
for initiating the communication between storage and
external devices. The 2040H occupies more floor space
than the other models; otherwise the five models of
the 2040 Processor Unit vary only in the capacity of
the main storage unit.
The 2040 Processing Unit contains the following major components:
Main storage
Arithmetic-logic unit
Local storage
General registers
Floating-point registers

Mutiplexer channel
Selector channels
System control panel

Main Storage

Main storage is available in five storage capacities as
previously listed. The main storage read/write cycle
locations are consecutively numbered starting with
zero. An addreSSing exception is recognized when any
part of an operand is located beyond the maximum
available installed main storage capacity.
The Model 40 transfers information between main
storage and the processing unit in units of two bytes.
The storage function in main storage is possible on a
one byte or a two byte basis in one storage cycle.
Main storage has a small extension of special channel
storage. This special channel storage is not accessible
by the problem programmer and is used to store the
control and status information for each subchannel
attached to the multiplexer channel. The number of
these special channel storage locations determines the
number of subchannels available to the multiplexer
channel.
System Description

5

Main Starage Cycle: 2.5 Microsecands

IBM 2040 Processing Unit
Storage bytes obtained per access: Two

System
Model

Bytes

Multiplexer Subchannels

16,384
32,768
65,536
131,072
262,144

D40
E40
F40
G40
H40

(

16
32
64
128
128
Storage Protection
(Store Only)

Instruction Sets *
(

Universal

)

'------

8
Up to Eight
Control
Units!
Addresses up to 144, 160, 192, or 256 I/O devices, depending On 2040 model
Multiplex Mode: Concurrent I/O operations with overlapped processing'
Burst Mode: Single I/o operation without overlapped processing

Emergency Power-Off Control
(Multisystem Operation)
IBM 1401/1460 Compatibility
(with E40,F40,G40, and H400nly)
On Models F, G, and H specify
Feature #9710 for 1311 Disk

Up to Eight
Control
Units t
First Selector Channel
Addresses up to 256 I/O devices, one at a time
Operates in burst mode with overlapped processing

Up to Eight
Control
Units+

Direct Control:
External Interrupt

Second Selector Channe I
Addresses up to 256 I/O devices, one at a time
Operates in burst mode with overlapped processing

NOTES:

* The Universal Instruction Set includes the two storage protection instructions, plus the following subsets: Standard, Commercial,and Scientific

t

t

A Channel-to-Channel Adapter option (one per 2040) permits interconnection of two channels. One channel position can connect to one
channel position on any other IBM System/360 channel. Only one Channel-ta-Channel Adapter needed per connection; it counts as a
control unit on each channel.
Input/Output Control Units and devices are shown on the IBM System/360 Input/Output Configurator, Form A22-6823 .

• Figure 1. IBM System/360 Model 40 Configurator

6

Arithmetic-Logic Unit

The arithmetic-logic unit contains a one byte wide
adder-subtractor which operates with either hexadecimal or decimal values. It is capable of producing
both arithmetic and logical combinations of the input
data streams. Cycle time is 0.625 microseconds.
Local Storage

Local storage consists of a small high-speed core storage unit providing registers for fixed-point and floating-point storage, for channel operations, for dumping
of the 2040 Processing Unit working registers by error
conditions and I/O interrupts, and for general working
storage. Only the general registers and the floatingpoint registers are addressable by the main program.
Local storage cycle time is 1.25 microseconds with access to two bytes. The storage cycle time can be split
cycled on occasions giving an effective access of 0.625
microseconds.
General Registers

The 16 general registers are used in address arithmetic
and indexing, and as accumulators in fixed-point arithmetic and logical operations. The general-purpose registers have a capacity of one word. For some operations,
two adjacent registers can be coupled together, providing a double word capacity. The general registers
are implemented in local storage and have a cycle
time of 1.25 microseconds per two bytes.
Floating-Point Registers

Four floating-point registers are available for floatingpoint operations. These registers are two words in
length and can contain either a short (one word) or
a long (two word) floating-point operand. The floating point registers are implemented in local storage and
have a cycle time of 1.25 microseconds per two bytes.

vices and permits data processing to proceed concurrently with I/O operations. Data are transferred a byte
at a time between the I/O device and the channel. Data
transfers between the channel and storage are parallel
by two bytes (half word) for selector channels, and
serial by byte for the multiplexer channel. See Figure 2.
For efficiency, the channels are integrated with the
processing unit and share many of its facilities. For
example, the channels utilize the same read only storage for control, and use the CPU data paths for handling nearly all data and control information. A standard
I/O interface provides a uniform method of attaching;
I/O control units to all channels, making the Model 40
devices.
Channel-to-Channel Feature

A channel-to-channel adapter is available as an optional feature. The adapter permits communication
between two System/360 channels, thus providing the
capability for interconnection of two processing units.
The adapter uses one control unit position on each of
the two channels. This feature is required on only one
of the two connected channels. Only one channel-tochannel adapter can be installed on a Model 40.
If, at any time during a channel-to-channel adapter
operation initiated by a Model 40 multiplexer channel,
the other system fails to respond to the Model 40
within 32 seconds, the Model 40 channel disconnects
and generates a machine-check interruption condition.
The other system's failure to respond could be caused
by its power being off, its operation in the stopped
state, or by its channel being masked against an I/O
interruption; i.e., a data transfer request or an attention condition initiated by the Model 40 is not recognized by the other system within 32 seconds.
Multiplexer Channel

The control function of the Model 40 is achieved by
the use of a read only storage (ROS). The ROS is self
of a nondestructive nature used to control the functions of data flow, and instruction execution. ROS is not
directly addressable by the main program. :Modification of the unit is made by physically changing the
ROS unit.

Channels
The channel directs the flow of information between
the I/O devices and main storage. It relieves the CPU
of the task of communicating directly with the I/O de-

The multiplexer channel is a standard feature of the
Model 40. This channel is capable of controlling several low to medium speed I/O units concurrently in
multiplex mode or a single high-speed unit in burst
mode.
The channel facility necessary to sustain an I/O operation with an I/O device is called a subchannel. The
number of multiplexer subchannels is determined by
the size of the main storage unit. See Figure 2. In the
multiplex mode, the multiplexer channel sustains concurrent I/O operations on several subchannels. Bytes
of data are interleaved and transmitted to or from the
selected I/O devices and to or from the desired locations in main storage. A maximum of eight control
units may be attached to the multiplexer channel.
System Description

7

ROS
Micro-Coded Sequencing
Control

Selector Channel

Buffer

Main Storage

Multiplexer Channel
Control Storage
Control
Buffer .....f-S_e_l_e_c_to_r_C_ha_n_n_e_I-I~

Working Registers and
Electronic Switches

Local Storage
General Registers
Floating-Point Registers
Selector Channel
Control Storage
Working Registers

Multiplexer Channel

o

A = One byte wide data path
B = Two byte wide data path

Data Width

Access/Speed/Rate

16

1 word

1.25 RjW cycle/16 bits

4

2 words

1.25 RjW cycle/16 bits

1 byte

0.625 microsecond

Capacity/Number
General registers
Floating-point registers
Local storage

1.25 microsecond RjW cycle*

0.625 microsecond Rd cycle

Basic machine cycle

0.625 microsecond

Multiplexer channel
Burst mode
Multiplex mode

1 Qyte
1 byte

Selector channel

2 bytes

Data transfers
Processor to storage
Storage to storage
Selector channel to processor
Multiplexer channel to processor
Control unit to channel

2
2
2
1
1

bytes
bytes
bytes
byte
byte

* Can be split cycled on occasions giving effective access of 0.625 microseconds .

• Figure 2. Model 40 Data Flow Diagram and System Statistics

8

}

In burst mode, the multiplexer channel sustains
one I/O operation on one sub channel. Only one I/O
device can be selected at a time and no other device
on the multiplexer channel can transfer data until the
selected I/O activity has been terminated.

of the interruption. The following information gives
the interruption times for the five classes of interruptions, with examples when applicable, to show how the
interruption times can vary.
External Interruption

Selector Channel

One or two selector channels are available, as optional
features, for the Model 40. The selector channel operates in burst mode only, although up to eight control
units can be attached and the channel has the facilities
for addressing up to 256 devices. Only one I/O device
may be selected at a time on a selector channel. No
other I/O device on the selector channel can transfer
data until the selected activity has been terminated.

External interruption extends from the time the external interruption is discovered to the next instruction. The time is 25.63 microseconds.
Supervisor Call Interruption

Supervisor call interruption extends from the time the
supervisor call interruption is discovered to the next
instruction. The time is 23.75 microseconds.
Program Interruption

System Control Panel

The system control panel located on one end of the
2040 Processing Unit provides the switches, the keys
and the lights necessary to operate, monitor and control the Model 40. The need for operator manipulation
of manual controls is held to a minimum by the system
design and the governing supervisory program. A detailed description of operator functions provided by
the switches, keys and lights of the control panel is
located in the system control panel section of this
manual.
I nstruction Configurations
The Model 40 is available with many different instruction configurations. The minimum configuration is the
standard instruction set. The standard instruction set,
with the addition of the decimal feature, comprises
the commercial instruction set. The standard instruction set, with the addition of the floating-point feature,
comprises the scientific instruction set. The standard
instruction set, with the decimal feature, floating-point
feature and storage protection feature composes the
universal instruction set.
Descriptions of all instructions are found in the IBM
System/360 Principles of Operation~ Form A22-6821.
Timing information for each of the instructions is
found in the instruction timing information section of
this manual.
Interruption Times
Interruption times vary for the class of interruption
and the type of instruction being executed at the time

Program interruption extends from the time the program interruption is discovered to the next instruction.
The program interruption time is equal to or less than
the following time, plus the instruction time.
20.63 microseconds after an RR or RX instruction.
20.00 microseconds after an RS or SS instruction.

Examples: Time assumes base register not equal to
O. Add 1.25 microseconds to total time if an RX instruction is indexed.
1. Invalid Operations
00
23.75 fJ-S
4D
29.38 fJ-s
CO
23.13 fJ-s
D8
31.25 fJ-s
FO
32.50 fJ-s
2. RX fixed-point full word
28.23 fJ-s
3. Odd or invalid instruction addresses
24.38 fJ-s
Machine Check Interruption

Machine check interruption time extends from the time
the machine check interruption is discovered to the
next instruction. The time is 572 microseconds and includes scan out and reset time.
I/O Interruption
I/O interruption time depends on the type of
ruption and the type of channel.
MULTIPLEXER
CHANNEL

I/O

inter-

SELECTOR
CHANNEL

+

Device end
56.88+ Ul p,s· 60.0 U 1 p,s·
40.63 p,s
Channel end
60.63 p,s
40.63 p,s
Program Controlled Interruption 61.88 p,s
(PCI)
(!See timing chart legend U 1.

System Description

9

System Control Panel

The system control panel contains the switches and
lights necessary to operate, display, and control the
system. The system consists of the CPU, storage, channels, on-line control units, and I/O devices. Off-line
control units and I/O devices, although a part of the
system environment, are not considered part of the
system proper.
System controls are logically divided into three
classes: operator control, operator intervention, and
customer engineer control. This section of the manual discusses the system control functions provided by
the system control panel as well as the purpose and
use of the switches and lights on the panel.

System Control Functions
U sing the control panel, the operator can perform
these system control functions:
1. Reset the system.
2. Store and display information in storage and
registers.
System Reset

The system reset function resets the CPU, channels, and
on-line, nonshared control units and I/O devices.
The CPU is placed in the stopped state and all pending interruptions are eliminated. The parity of the general and floating-point registers, as well as the parity
of the psw are corrected. All error-status indicators are
reset to zero.
In general, the system is placed in such a state that
processing can be initiated without the occurrence of
machine checks, except those caused by subsequent
machine malfunction.
The reset state for a control unit or device is described in the appropriate System Reference Library
(SRL) publication. A system reset signal from a CPU
resets only the functions in a shared control unit or
device belonging to that CPU. Any function pertaining
to another CPU remains undisturbed.
The system reset function is performed when the system reset key is pressed, when initial program loading is initiated, or when a power-on sequence is performed.
10

Programming Notes

If a system reset occurs in the middle of an operation,
the contents of the psw and of the result registers or
storage locations are unpredictable. If the CPU is in the
wait state when the system reset is performed, and I/O
is not working, this uncertainty is eliminated.
A system reset does not correct parity in storage but
does correct parity in the registers. Because a machine
check occurs when information with incorrect parity is
used, the incorrect information should be replaced by
Store and Display

The store and display function permits manual intervention in the progress of a program. The storing and/
or displaying data may be provided by a supervisor
program in conjunction with proper I/O equipment
and the interrupt key.
In the absence of an appropriate supervisor program,
the controls on the operator intervention panel allow
direct storage and display of data. This is done
by placing the CPU in the stopped state, and subsequently storing and/or displaying information in main
storage, in general and floating-point registers, and in
the instruction-address part of the psw. The stopped
state is achieved at the end of the current instruction
when the stop key is pressed, when single instruction
execution is specified, or when a preset address is
reached. The store and display function is then
achieved through the store and display keys, the
address switches, the data switches and the storage
select switch. Once the desired intervention is completed, the CPU can be started again.
All basic store and display functions can be simulated by a supervisor program. The stopping and starting of the CPU in itself does not cause any alteration in
program execution other than the time element involved in the transition from operating to stopped
state.
Machine checks occurring during store and display
functions do not log immediately, but create a pending
log condition that can be removed by a system reset or
check reset. The error condition, when not masked off,
forces a log-out and a subsequent machine check interruption when the CPU is returned to the operating
state.

Initial program loading (IPL) is provided for the initiation of processing when the contents of storage or the
psware not suitable for further processing.
Pressing the load key causes a system reset, turns on
the load light, turns off the manual light, and subsequently initiates a read operation from the selected
input device. When reading is completed satisfactorily,
the IPL psw is obtained, the CPU starts operating, and
the load light is turned off.
System reset suspends all instruction processing, interruptions, and timer updating and also resets all
channels, on-line nonshared control units, and I/O devices. The contents of general and floating-pOint registers remain unchanged.
When IPL is initiated, the selected input device starts
locations 0-23. Storage protection, program controlled
interruption, and a possible incorrect length indication are ignored. The double word read into location 8
is used as the channel command word (ccw) for a
subsequent I/O operation. When chaining is specified
in this ccw, the operation proceeds with the ccw in
location 16. Either command chaining or data chaining may be specified.
After the input operation is performed, the I/O address is stored in bits 21-31 of the first word in storage.
Bi~s 16-20 are made zero. Bits 0-15 remain unchanged.
The CPU subsequently fetches the double word in
location 0 as a new psw and proceeds under control of
the new psw. The load light is turned off. When the
I/O operations and psw loading are not completed satisfactorily, the CPU idles, and the load light remains on.
Programming Notes

Initial program loading resembles a start I/O that specifies the I/O device selected in the load-unit switches
and a zero protection key. The ccw for this start I/O
is simulated by CPU circuitry, and contains a read command, zero data address, a byte count of 24, chain
command flag on, suppress-length-indication flag on,
program-controlled-interruption flag off, chain-data
flag off and skip flag off. The ccw has a virtual address
of zero.
the first six words of storage. Since the remainder of
the IPL program may be placed in any desired section
of storage, the areas of storage reserved for the timer
and psw's may be preserved.
If the selected input device is a disk, the IPL information is read from track O.

The selected input device may be a channel-tochannel adapter connecting the channels of two cpu's.
After a system reset is performed, and a read command
is issued to the adapter by the requesting CPU, the
That CPU then should issue the write command necessary to load a program into main storage of the requesting CPU.
When the psw placed in location 0 has bit 14 set to
one, the CPU goes into the wait state after the IPL procedure (the manual, system, and load lights are off, and
the wait light is on). Interruptions that become pending during IPL are taken before instruction execution.

System Control Panel Controls
System controls are divided into three logical groups
identified as operator control, operator intervention
and customer engineer control. Figure 3 shows the
operator controls located in areas labeled Band H
and operator intervention controls in areas F and G of
the system control panel. The customer engineer will
use all controls, but the controls in areas C and D
are intended primarily for customer engineer use.
Operator Controls

Sections Band H of the system control panel contain
the controls required by the operator when the CPU is
operating under full supervisor control. Under supervisor control, a minimum of direct manual intervention
is required because the supervisor performs operations
such as store and display.
The main functions provided by the operator controls are the control and indication of power, the indication of system status, operator to machine communication and initial program loading. The controls in area
H are identical in all models of the System/360.
The following table lists all operator controls and indicators by name and their implementation. All operator controls except the emergency pull switch are located in the area labeled H of the control panel shown
in Figure 3. The emergency pull switch is located in
area B.
NAME

IMPLEMENTATION

Emergency Pull
Pull switch
Power On
Key, backlighted
Power Off
Key
Key
Interrupt
Three rotary switches
Key
Light
Wait
Manual
Light
Light
System
Light
Test
Light
NOTE: All keys have momentary action.
System Control Panel

11

Figure 3. Model 40 System Control Panel

Emergency

Pulling this switch turns off all power beyond the
power-entry terminal on every unit that is part of the
system or that can be switched onto the system. (Exception: In the CPU, primary power is available within
the unit at CBl.) Therefore, the switch controls the
12

system proper and all off-line and shared control units
and 110 devices.
The switch latches in the out position and can be restored to its in position by maintenance personnel only.
When the emergency pull switch is in the out position, the power-on key is ineffective.

Power On

Programming Notes

This key is pressed to initiate the power-on sequence
of the system.
As part of the power-on sequence, a system reset is
performed in such a manner that the system performs
no instructions or I/O operations until explicitly directed. The contents of main storage, including the protection keys, remain preserved.
The power-on key is backlighted to indicate when
the power-on sequence is completed. The key is effective only when the emergency pull switch is in the in
position.

The states indicated by the wait and manual lights
are independent of each other; however, the state of
the system light is not independent of the state of these
two lights because of the definition of the running condition for the meters. The following table shows possible conditions when power is on:

Power Off

The power-off key is pressed to initiate the power-off
sequence of the system.
The contents of main storage and its protection keys
are preserved, provided that the CPU is in the stopped
state. The key is effective while power is on the system.

~

SYSTEM
LIGHT

MANUAL
LIGHT

WAIT
LIGHT

Off
Off
Off
Off

Off
Off
On
On

Off
On
Off
On

On
On
On
On

Off
Off
On
On

Off
On
Off
On

CPU
STATE
011<

Wait
Stopped
Stopped,
wait
Running
Wait
Stopped
Stopped,
wait

I/O
STATE

•

Not working
Not working
Not working
U ndetennined
Working
\'\lorking
\'\lorking

Abnormal condition

Test
Interrupt

The interrupt key is pressed to request an external interruption.
The interruption is taken when not masked off and
when the CPU is not stopped. Otherwise, the interruption request remains pending. Bit 25 in the interruption-code portion of the current psw is made 1 to indicate that the interrupt key is the source of the external
interruption. The key is effective while power is on the
system.

Three rotary switches provide the 11 rightmost bits of
The leftmost rotary switch has eight positions labeled 0-7 used for the channel address. The other two
I6-position rotary switches are labeled with the hexadecimal characters 0-9, A-F, and are used for the unit

The key is effective while power is on the system.
Wait

The wait light is on when the

CPU

The test light is on when a manual control is not in its
normal position or when a maintenance function is
being performed for CPU, channels, or storage.
Any abnormal switch setting on the system control
panel or on any separate maintenance panel for the
CPU, storage, or channels that can affect the normal
operation of a program causes the test light to be on.
The following switches cause the test light to be on
if any are not in their normal position:
Rate switch not to process
Diagnostic control switch not to off
Address compare switch not to process
Channel test switch not to off
Reverse data parity switch on
Display lever switch not set to ROBAR
MPX store switch on
Disable interval timer switch on
CPU check switch not to process
Key-operated meter switch to CE
Any manual interface switch on
DSAB IRPT switch on

The test light may be on when one or more diagnostic function under control of DIAGNOSE is activated or
when certain abnormal circuit breaker or thermal conditions occur.
The test light does not reflect the state of marginal
voltage controls.

is in the wait state.

The manual light is on when the CPU is in the stopped
state. Several of the manual controls are effective only
when the CPU is stopped (manual light on).

is turned on when the load key is pressed and is turned

System

Operator Intervention Controls

The system light is on when the CPU usage meter or
customer engineer meter is running.

Sections G and F of the system control panel contain
the controls required for the operator to intervene in

Manual

System ContrOl Panel

13

normal programmed operation. These controls are intermixed with the customer engineer controls. Only
operator intervention controls are described in detail.
Operator intervention controls provide the system
reset and the store and display functions.
The following table lists all intervention controls
and indicators by name and their implementation.
NAME

IMPLEMENTATION

System Reset
Check Reset
Stop
Rate
Start
Storage Select
Data
Store
Display
Log-Out
PSW Restart
CPU Check
NOTE: All keys have momentary

Key
Key
Key
Rotary switch
Key
Rotary switch
Lever switches
Lever switches
Key
Key
Key
Key
Rotary switch
Rotary switch
action.

System Reset

The system reset key is pressed to cause a system reset;
it is effective while power is on the system. A system
reset resets CPU, channels, and control units to their
initial state. All CPU and channel error indicators are
reset to the no-error state. The CPU is placed in the
stopped state, and all pending interruptions are
eliminated.
Check. Reset

The check reset key resets all CPU and channel error
indicators to the no-error state. The check reset function can thus be considered a subset of the system
reset function.
Check reset can be performed regardless of the setting of the rate switch. Error indicators remaining on
after check reset must be cleared at the error source
by use of appropriate manual controls.
Stop

The stop key causes the CPU to enter the stopped state
and turns on the manual light. (The CPU first completes the instruction being executed at the time the
stop signal is recognized, and processes all pending
unmasked interruptions.) Any I/O operation in progress is completed, while the CPU is in the (manual)
stop state. The key is effective while power is on the
system.
Pressing the stop key has no effect when a continuous string of interruptions is performed or when the
CPU is unable to complete an instruction because of
machine malfunction.
14

Rate

This three-position rotary switch is used to indicate the
manner in which instructions are to 'be performed. The
position of the switch should be changed only while
the CPU is in the stopped state. Otherwise, unpredictable results may occur. The rate switch positions and
their effects are:
Process: The system starts operating at normal speed
when the start key is pressed. The test light is on when
the rate switch is not set to PROCESS.
Insn Step (Instruction Step): The system executes
one instruction each time the start key is pressed. After
each instruction is executed, all pending interruptions
not masked off are taken. The CPU then returns to the
stopped state. The timer is not updated when the
switch is in this position.
Any instruction can be executed with the rate switch
set to INSN STEP. Input/output operations are completed to the interruption point. When the CPU is in the
wait state, no instruction is performed, but pending
interruptions, if any, are taken before the CPU returns
Single Cycle: The system executes one machine cycle
each time the start key is pressed. Single cycle operates
with I/O equipment to the point of initiation of the
asynchronous operation. The asynchronous operation
begins the next time the start key is pressed and runs
to completion. The single cycle position is primarily
for customer engineer use.
Start

The start key is pressed to start instruction execution
as specified by the rate switch. The key is effective
only while the CPu is in the stopped state.
Pressing the start key after a normal stop causes
instruction processing to continue as if no stop had
occurred, provided that the rate switch is in the PROCESS or INSN STEP position. Pressing the start key after
system reset without first introducing a new instruction address may yield unpredictable results.
Storage Select

This six-position rotary switch indicates whether the
contents of main storage or one of a variety of registers
are to be displayed or replaced by new data. The actual
lever switches. The switch is active only in the stopped
state (manual light on). The storage select switch has
the following settings:
MS (Main Storage): Selects a main storage location

GP (General Register): Selects a general register
specified by the register-select address switches.
FP (Floating Point): Selects a floating-point register
specified by the register-select address switches.
IC (Instruction Counter): Automatically selects the
instruction counter register (instruction address in
the psw).
PSW (Program Status Word): Selects the register
containing the current program status word.
SP (Storage Protection): Selects the storage protection key register.

When used with the storage select switch, the 18
address lever switches provide a means of manually
addressing a location in storage. Correct parity is
automatically generated.
Addressing Main Storage: When the storage select
switch is set to the MS position, the 18 address switches
are used to manually address a main storage location.
When main storage is being addressed, the 18
switches represent the 18 low-order bits of a 24 bit
binary address. Because the Model 40 has a maximum
of 262,144 bytes of main storage, these 18 switches are
sufficient for addressing all main storage locations.
The rightmost switch is the units position. Because
data, in main storage, are stored or displayed a half
word at a time, the units position address switch is
not involved in determining the address.
When an address switch is in the down position it
represents a 1 bit; when in the center or restored position it represents a bit. The setting of the address
switches in the correct order of 1 and positions is
used to represent the low-order positions of a 24 bit
binary number to address main storage.
The address switches are color coded to help identify
Selecting the General and Floating-Point Registers:
Four lever switches, a subset of the address switches,
are used to select one of 16 general registers (0-15)
or one of four floating-point registers (0, 2, 4, 6) when
used with the proper setting of the storage select
switch.
With the storage select switch set to the GP position,
a general (purpose) register is selected by setting its
number (0-15) into the four register select switches
located in positions 0, 1, 2, and 3 of byte 1. Information is displayed or stored a half word at a time for
the general registers. Address switch 7, located in byte
1, is used to select the register half word. When the
address switch is set in the
position (center), it
selects the first half word; when set in the 1 position
( down), it selects the second half word. Address
switches 4, 5, and 6 of byte 1 are not used.

°

°

°

o 1 2 345 6 7
o 1 1 1 x x x 0 1st half word general register 7
o 1 1 1 x x x 1 2nd half word general register 7
1 1 0 1 x x x 0 1st half word general register 13
1 1 0 1 x x x 1 2nd half word general register 13
x = no effect

When the storage select switch is set to FP (floatingpoint) position, a floating-point register is selected by
setting its number (0, 2, 4, or 6) into the four register
select switches located in positions 0, 1, 2, and 3 of
byte 1.
Information is stored or displayed one half word at
a time for the floating-point registers. Address switches
6 and 7 of byte 1 are used to select the required half
word. Address switches 4 and 5 of byte 1 are not used.
xII x x x 0 0
xII x x x 0 1
xII x x x 1 0
xII x x xII

byte 1 .

o

1st half word 2nd half word 3rd half word 4th half word -

FP register 6
FP register 6
FP register 6
FP register 6

Selecting the Program Status Word (PSW): The psw
is contained in two words occupying four locations in
local storage. psw information is displayed or stored
a half word at a time; thus, four operations are required to store or display the data of a psw.
The psw half word is selected by setting the storage
select switch in the psw position, and by setting the
number 0, 1, 2, or 3 into address switches 6 and 7
switches 0, 1, 2, 3, 4, and 5 of byte 1 are not used.
x x x x x x 0 0 1st PSW half word
x x x x x x 0 1 2nd PSW half word
x x x x x x 1 0 3rd PSW half word
x x x x x x I I 4th PSW half word

Selecting the Instruction Counter (IC): Setting the
storage select switch to the Ie position automatically
selects the instruction counter. The register select
switches are not required. See "Store" and "Display."
Selecting the Storage Protection Register: Setting
the storage select switch to the sp position automatically selects the storage protection register (psw protec
tion key data). The register select switches are not
required. See "Store" and "Display."
Data Switches

The storage data switches (upper group of 18 switches
in panel F) are used to represent the data to be stored
in the location indicated by the storage select switch
and the address switches. Correct data parity is automatically generated.
System Control Panel

15

The storage data switches can be used to represent
a half word of information. The two leftmost switches
are not used as part of the half word for customer
store functions. A storage data switch in the down
position represents a 1 bit and in the center position
a 0 bit.
Store

The store key is pressed to store information in the
location specified by the storage select switch and
address switches. The key is effective only while the
CPU is in the stopped state.
When the store key is pressed, the number indicated
by the data switches is placed in the specified location
in main or local storage or in a general or floating-point
register. Storage protection is ignored. When the location designated by the address switches and storage
select switch is not available, data is not stored.
When the storage select switch is set to MS, pressing
the store key stores the data bytes represented by the
data switches into the main storage location indicated
by the address switches. The data bytes stored are displayed in the 18 (16 data plus two parity) storage
switches is displayed in the storage address lights.
When the storage select switch is set to GP, pressing the store key stores the data bytes represented by
the data switches into the general register half word
bytes stored are displayed in the storage data lights,
is displayed in the storage address lights.
When the storage select switch is set to FP, pressing the store key stores the data bytes represented by
the data switches into the floating-point register half
data bytes stored are displayed in the storag~ data
switches is displayed in the storage address lights.
When the storage select switch is set to IC, pressing
the store key places the address indicated by the 18
portion of the psw. The instruction address stored is
dispJayed in the storage address lights.
When the storage select key is set to psw, pressing
the store key places the data bytes represented by the
data switches into the psw half word addressed by
the register select switches. The data bytes stored are
displayed in the 16 storage data lights, and the address
generated by the register select switches is displayed
When the storage select key is set to SP, pressing
the store key stores the data bytes represented by the
16

data switches into the storage protection register (psw
protection key area). The data stored is displayed in
the storage data lights.
Display

The display key is pressed to display information in
the location specified by the storage select switch and
The specified data in main or local storage or in a
general or floating-point register is displayed in the
storage data lights.
When the designated location is not available, the
displayed information is unpredictable.
The key is effective only while the CPU is in the
stopped state.
Log-Out

A ROS microprogram, log-out, is automatically executed on detection of any CPU or channel error or on
depressing the log-out key. Log-out is the technique
of recording in main storage, the status of the CPU and
channels existing immediately prior to the initiation
of the log-out. The log-out area of main storage is at
locations 128-384.
On completion of the log-out microprogram, the
CPU checkout microprogram is automatically executed.
The checkout microprogram tests and diagnoses large
sections of the CPU. Any error detected by the checkout microprogram or any machine error occurring during the execution of the checkout microprogram will
result in an immediate stop.
Successful execution of the checkout microprogram
is followed by a system reset and a machine interruption. The machine interruption stores the current psw
in the machine check old psw location (48) of main
storage and loads the psw from the machine check new
psw location (112) of main storage. The system at this
point is returned to an operating state.
The checkout microprogram, following a log-out
operation, helps to guarantee the validity of the logout information. If a log-out occurred, and the CPU
is not returned to an operating state following the
checkout microprogram, the validity of the log-out
information could be in question.
The CPU checkout microprogram is executed under
the following conditions:
After depression of system reset key
After depression of the load key
After depression of start key with diagnostic control set to CPU
Immediately after a log-out operation
PSW Restart

A psw is loaded from storage location zero and the
is changed from stopped to operating state.

CPU

The address compare switch provides a means of stopping the CPU on a successful address comparison. The
process position of the switch is the normal operating
position. Only the stop on MS position concerns operator intervention. The remainder of the switch positions are for customer engineer use.
The address compare switch can be manipulated
without disrupting CPU operation other than by causing the address-comparison stop. When the switch is
set to any position except PROCESS, the test light is on.
Stop on MS (Main Storage): When the instruction
or data fetching mechanism accesses a main storage
keys, the processor enters the stopped state at the
completion of the current machine instruction.
Programming Note

When an address not used in the program is selected
in the address switches, the CPU runs as if the addresscompare switch was set to PROCESS.
CPU Check

The CPU check rotary switch provides selective control
of the system upon error.
Process Position: In the normal processing mode,

if the machine check mask bit in the psw is on, the
processor will pause on an error, a log-out will occur,
followed by system reset with a CPU checkout and a
machine-check interruption.
Stop Position: On error detection, the CPU stops.
CPU is interruptible.
Disable Position: On error detection, the error checking indication is still active but machine operation continues without log-out.
Check Restart Position: On error detection, the
checker is activated and error latch is set. System reset, CPU checkout, and machine-check interruption
follow.
Key Switch and Meters

The customer usage (cpu) meter and the CE meter are
on panel G of the system control panel. The CE key
switch controls which of these meters is to be run
while the system is in operation; i.e., initiating, executing, or completing instructions including 110 and
assignable unit operations. The test light is turned on
when the key (meter) switch is in the CE meter position. (For other conditions, see "Test.") The system
light, located on panel H, indicates when the system
is in operation.

System Control Panel

17

Channel Characteristics and Functional Evaluation

This channel section has three purposes. It specifies:
1. Model 40 channel implementation.
2. How to determine whether the I/O devices required to run concurrently by a particular application
will perform satisfactorily.
3. How to determine the available CPU time during
I/O operations.

General Channel Information
IBM System/360 channels transfer data between core
storage and I/O devices under control of a channel
program executed independently of the CPU program.
The Model 40 CPU is free to resume the CPU program
after initiating an I/O operation, except for burst
mode operation of the multiplexer channel.
Model 40 channels may run concurrently, within the
data transfer rate and channel programming conventions specified in this manual.
A major feature of the channels is their common
I/O interface connection to all System/360 input/output control units. The I/O interface provides for attachment of a variety of I/O devices to a channel.
At the end of an I/O operation, the channel signals
an I/O interruption request to the CPU. If not masked
off, an I/O interruption occurs that places the I/O new
psw in control of the CPU. \\Then I/O interruptions are
masked, interruption requests are queued. Until honored, an I/O interruption condition is called a pending I/O interruption.
At the end of an I/O operation, a channel has information concerning the success of the operation, or
details about any lack of success. The information is
available to the CPU program.
Each System/360 channel has facilities for performing the following functions:
Accepting an I/O instruction from the CPU
Addressing the device specified by an I/O instruction
Fetching the channel program from core storage
Decoding the channel command words that make up the channel program
Testing each channel command word (CCW) for validity
Executing CCW functions
Placing control signals on the I/O interface
Accepting control-response signals from the I/O interface
Transferring data between an I/O device and core storage
Checking parity of bytes transferred
Counting the number of bytes transferred
Accepting status information from I/O devices
Maintaining channel-status information
Signaling interruption requests to the CPU
18

Sequencing interruption requests from I/O devices
Sending status information to location 64 when an interruption
occurs
Sending status information to location 64 upon CPU request

Channel Control
IBM System/360 channels provide a common input/
output interface to all System/360 control units. All
control units are governed with six basic channel
commands and a common set of only four CPU instructions. The instructions are:
Start I/O
Test channel
Test I/O
Halt I/O
All I/O instructions set the psw condition code and
under certain conditions, all but test channel' ma;
cause a channel status word to be stored. A test channel instruction elicits information about the addressed
channel; a test I/O instruction elicits information about
a channel and a particular device. Halt I/O terminates
any operation on the addressed channel, sub channel,
or device. None of the three instructions makes use of
channel command words (ccw's).
A start I/O instruction initiates execution of one or
more I/O operations. It specifies a channel, subchannel, control unit, and I/O device. It causes the channel
to fetch the channel address word ( CAW) from location 72. The CAW contains the protection key and the
address of the first channel command word (CCW )
for the opcration. The channel fetches and executes
one or more ccw's, beginning with the first ccw specified by the CAW.
Six channel commands are used:
Write
Control
Sense
Transfer in channel
The first three are self-explanatory.
Control commands specify such operations as set
tape density, rewind tape, advance paper in a printer,
etc.
A sense command brings information from a control
unit into main storage concerning unusual conditions
detected during the last I/O operation, and detailed

A transfer in channel (TIC) command specifies the
location in main storage from which the next ccw in
the channel program is to be fetched. A TIC may not
specify another TIC. Also, the CAW may not address a
TIC.
Each ccw specifies the channel operation to be performed and, for data transfer operations, specifies contiguous locations in main storage to be used. One or
more ccw's make up a channel program that directs
a channel operation.
Channel Registers

System/360 channels maintain the following channel
control informa~!on for each I/O device selected for
operation:
Protection key (when applicable)
Identity of operation specified by command code
ccw Hags
Byte count
Channel status
A selector channel has only one set of registers for
the above information because it operates with only
one I/O device at a time.
On a multiplexer channel, the listed information
must be maintained for each sub channel in operation.
Storage for this information is provided by special
channel storage that is not directly addressable. Each
sub channel has provision in channel storage for channel register information. When a particular subchannel is selected by a start I/O instruction and a channel
program initiated, the channel storage locations for the
subchannel are loaded with the information necessary .
for operation of the subchannel.
The channel refers to channel storage in order to
communicate with a device and with main storage.
At each cessation of activity in a subchannel, its particular area in channel storage contains updated information, and the multiplexer channel is available for
operation of another subchannel. The sharing of facilities by the multiplexer channel and the CPU is shown
in Figure 4.

Figure 4. Equipment Sharing by Model 40 CPU and Multiplexer Channel

Entire ccw's, including the command code field, may
also be chained together for use in a sequence of channel operations. Such coupling is called command
chaining, and is specified by a different Hag bit in a
ccw. Command chaining provides additional control
information for operation of a device.
Data chaining has no effect on a device, as long as
the channel has sufficient time to perform both data
chaining and data transfer for the device.
In this manual, when a device is said to data chain,
it means that the channel program for the device specifies data chaining.

Chaining

A single ccw may specify contiguous locations in main
storage for a data transfer operation, or successive
ccw's may be chained together to specify a set of noncontiguous storage areas. Chaining to the next ccw
is caused by the presence of a Hag bit in a ccw.
In data chaining, the address and count information
in a new ccw is used; the command code field is ignored.

Fetching Channel Command Words

The channel must fetch a new ccw whenever a ccw
specifies data chaining, command chaining, or transfer
in channel (TIc). The extra control activity caused by
these operations takes time and diminishes a channel's
ability to do other work.
A data chaining fetch usually occurs while a channel also has a data transfer load from the same device.
Channel Characteristics and Functional Evaluation

In

The time required to fetch the new ccw necessarily
limits the interval of time available for successive data
transfers through the channel. An absence of data
chaining ordinarily permits a channel to operate with
a faster I/O device. Similarly, when a channel is not
transferring data, a data chaining operation has a
lesser impact on channel facilities.
Data Chaining in Gaps

For direct access storage devices, such as mM 2311
Storage or mM 2303 Drum Storage, formatting
write commands cause the control unit to create gaps
between count, key, and data fields on the recording
more than one of the fields may specify data chaining
to define separate areas in main storage for the fields.
The gaps on a track have significance to channel
programming considerations for direct access storage
devices. The channel does not transfer data during
the time a gap is created or passes under the readwrite head, and this time is sufficient for a Model 40
to perform a command chaining or data chaining operation.
Command chaining ordinarily occurs only during
gap time, but data chaining may occur during gap
time or while data is being transferred. A data chaining operation occurring during gap time has a lesser
impact on channel facilities than when data transfers
also occur. If a channel program for a direct access
storage device calls for data chaining only during gap
time, the device's overall load on channel facilities is
significantly less.
When a direct access device is said to data chain
in a gap, the reference is to a gap other than a gap
following a data field. The latter gap causes a device
end indication and command chaining is used in such
A device end occurring in the absence of a ccw
specifying command chaining results in termination
of the operation. When command chaining continues
the operation, the status information available at the

I Disk

20

end of the operation relates to the last operation in the
chain.
While reading, an attempt to data chain in a gap
following a data field causes an incorrect length indication in the channel status byte.
Late Command Chaining

Operation of direct access devices, such as disk storage, requires the use of command chaining. Between
certain operations, such as the search for a record
identification key and the reading of a data field on
a direct access storage device, the control unit has a
fixcd time interval during which it must receive and
execute a new command. If activity on other channel( s) causes too much delay in initiation of the operation specified by the new command, the channel
program is terminated and an I/O interruption condition occurs.

When data chaining, the beginning and ending byte
addresses and the minimum number of bytes transferred are factors in the maximum data rates that different System/360 channels can sustain. If the storage
width of larger models and the possibility of using
faster I/O devices are kept in l~lind when writing channel programs for small models, better performance will
be obtained when the programs run on larger models
or with faster I/O devices.
For example, a tape operation at a 30 kb (kilobyte)
data rate may data chain with a byte count of one on
a Model 30 with one selector channel, but the same
tape operation cannot be performed at 90 kb on a
Model 40. In this instance, the use of a larger count for
data chaining would permit the Model 40 to execute
the channel program at 90 kb.
Data chaining and other aspects of channel programming compatibility for the various models of
System/360 are discussed in "Conventions for Satisfactory Channel Programs."

Channel Implementation

The Model 40 has two types of channels. One or two
selector channels are optional; the multiplexer channel is standard.
Each selector channel provides a path for moving
data between storage and a selected I/O device. It has
its own address register and data buffers. Provision is
channel on the Model 40 has buffering to move data
to or from storage one or two bytes at a time. Data
goes to or from an I/O device one byte at a time.
All channels on the Model 40 are integrated with
the 2040 Processor and share part of the CPU facilities.
Channel operations are overlapped with CPU operations except for burst mode operations on the multiplexer channel. A multiplexer channel has a single
data path that may be monopolized by one I/O device
or shared concurrently by many selected I/O devices.
Transfer of a byte on the multiplexer channel requires
use of CPU facilities. When a single device pre-empts
multiplexer channel facilities, the operation is in burst
mode. During such operation, CPU facilities are used
for data transfer; no instruction may be executed.
As many as eight control units may be attached to
a channel. A control unit determines whether its operation on the multiplexer channel is in burst mode or in
multiplex mode. All selector channel operations are
in burst mode.
Channel Priority

Priority for allocation of Model 40 CPU facilities is in
this order:
1. Machine check interruption handling
2. Selector channel data transfer
3. Selector channel data chaining
4. Selector channel command chaining
5. Multiplexer channel operation
6. CPU operation
Selector channels 1 and 2 alternate priority, except
that selector channel 1 is favored when both request
service during a CPU cycle.
Multiplexer Subchannels

When multiple I/O devices concurrently share multiplexer channel facilities, the operations are in multiplex mode. Each device in operation is selected, one
at a time, for transfer of a byte or a few bytes to or

from main storage. Bytes from multiple devices are
interleaved together and routed to or from desired
locations in main storage. Thus, the multiplexer channel data path is used by one device for transfer of
one or a few bytes of data and then another device
uses the same data path. The sharing of the data path
makes each device to appear to the programmer as if
it lIas a data path of its own. This leads to calling a
device's share of the data path as a subchannel. Each
data path available to a programmer is called a subchannel.
The numbering scheme for multiplexer subchannels
relates to I/O device addresses; the device address assigned to each device determines the subchannel that
controls its operation. For an unshared subchannel,
one device address is used. A shared sub channel permits use of several device addresses. The devices
share a single control unit, which connects them to
the sharcd subchannel. The devices may be selected
for use one at a time, but may not be selected concurrently.
Device addresses zero to less than 128 refer uniquely
to the correspondingly numbered unshared subchannels. Devices addressed 128-255 are assigned to shared
subchannels 0-7 in eight groups of 16. For example,
subchannel zero may be used by device addresses 000
or 128-143, and subchannel 1 may be used by device
addresses 001 or 144-159, etc. Thus, each shared subchannel 0-7 has 17 different device addresses. Unshared control units may use shared subchannel addresses in the lower range; shared control units use
The maximum number of multiplexer channel device addresses is 128 in the shared range, plus the
number of uniquely addressed subchannels provided
by the system. In the listing below, the Model D40
has 16 multiplexer subchannels; eight are shared sub.
channels (addresses 0-7 and 128-255) and eight are
SHARED

UNSHARED

SUBCHANNEL

SUB CHANNEL

SUB-

I/O DEVICE

I/O DEVICE

I/O DEVICE

MODEL

CHANNELS

D40
E40
F40
G40
H40

16
32
64
128
128

0-15, 128-255
0-31, 128-255
0-63, 128-255
0-255
0-255

0-7,
0-7,
0-7,
0-7,
0-7,

128-255
128-255
128-255
128-255
128-255

8-15
8-31
8-63
8-127
8-127

Channel Implementation

21

Concurrent Input/Output Capabilities

Each I/O device in operation places a load on its channel facilities. The magnitude of a load depends on a
device's channel programming and its data transfer
rate. In this manual, numeric factors are used to relate the loads caused by operation of I/O devices to
the channel's abilities to sustain concurrent operation
of the devices.
One or more numeric factors are specified for each
I/O device and channel available with a Model 40.
The numeric factors are referenced from tables in this
manual and used in arithmetic procedures that indicate satisfactory or less than optimum operation for
specific Model 40 input/output configurations.
Several procedures are provided for evaluating a
configuration of I/O devices for concurrent operation
on Model 40 channels. Channel programming considerations are included. Use of the basic procedures will
suffice to find an indication of satisfactory operation
for most configurations; the more detailed procedures
are used only for configurations that approach or temporarily exceed Model 40 input/output capabilities.

The evaluation factors and procedures allow for a
worst case situation when the most demanding devices
in the configuration all make their heaviest demands
on Model 40 I/O capabilities at the same time. Such
a situation may not occur frequently, but it is the situation that the evaluation procedures place under
test. If a particular configuration fails to pass testing,
one or more devices may be expected to incur overrun or loss of performance during the worst case
situation.
Overrun

Overrun occurs when a channel does not accept or
transfer data within required time limits during a
loss may occur when the total channel activity initiated by the program exceeds channel capabilities.
Depending on the device, it may halt operation, or it
may continue transferring data until the end of the
block is reached;
An overrun causes a unit-check indication in the
channel status word. An I/O interruption condition is
generated at the conclusion of the operation. The
cause for the unit check is indicated by turning on
bit 5 of sense byte zero, the overrun bit, for subsequent sense and interrogation.

I

22

Loss of Performance

Overrun occurs only on unbuffered I/O devices. Buffered devices are not subject to overrun. Instead, when
buffer service is not provided within required time
limits, the device merely waits for channel service.
While it is waiting, the device is said to incur a loss
of performance.
Conventions for Satisfactory Channel Programs

Execution of a channel program causes a load on channel and system I/O facilities. Some I/O devices require
execution of a chain of commands, preparatory to
transfer of a data block. However, the impact of the
load caused by a channel program is not a simple
function of the number of commands used: the sequence in which particular types of commands appear
in a channel program is also a factor.
A type of command particularly significant to sequencing considerations are control commands that
are executed at electronic speeds, and which do not
cause any mechanical motion. Such commands are
executed as immediate operations and provide device
end in the initial status byte. When command chaining is specified in such an immediate operation, channel facilities are not disengaged from the channel program until such a chain ends or a command causing
mechanical motion or data transfer is executed. Therefore, when immediate operations with device end in
the initial status byte are chained together, fetching
and execution of the ccw's may cause a heavy load
on channel facilities. Such a load may cause excessive
delay in channel service to one or more devices in the
I/O configuration with resultant overrun or loss of
performance. For example, a chain of no-op commands can contribute heavily to a channel overload
situation that would not otherwise have occurred.
Such a programming convenience may cause a severe
overrun situation for concurrently operating devices.
Another aspect of the way in which caw sequencing
considerations affect channel capabilities is their effect
on a channel's data transfer capabilities. For example,
if a command causing data transfer does not specify
data chaining, a channel is able to transfer data at a
faster rate, without overrun, than if data chaining is
specified.
Data Chaining Considerations

A System/360 user is free to specify data chaining in
channel programs whenever he chooses to do so. The

chain, including the ccw addressed by the CAW and
the terminating ccw that does not specify any chaining.
5. The conventions do not relate to commands addressed by the CAW which do not specify any chaining.
6. The conventions relate only to the avoidance of
overrun; they do not define invalid command sequences that are rejected by a channel, such as TIC
to TIC, or that are rejected by a control unit. ccw
sequences causing command reject are specified in the
r/a device manuals.
Note that item 4 is of particular interest to r/o
programmers working on segments of a single channel
program: the rules are not susceptible to abrogation
when one segment is chained to another segment.
The channel programming conventions in this manual are recommended to System/360 users, particularly in a multi-programming environment where a
programmer is not aware of the overall load on channel facilities. Where a programmer controls or has
knowledge of all r/o activity, he may establish somewhat less restrictive channel programming conventions of his own which may be particularly suited to
his application and configuration.
Also, channel programs used infrequently, such as
error routines, may have small probability of contributing to channel overload. For such routines, deviation from the conventions may be considered, and not
found inappropriate.

channel evaluation procedures and tables in this manual provide guidance in considering data chaining operations.
The factors in Table 1 allow for data chaining on
the 2702 and as specified for other devices, with exclusion of allowance for data chaining on telegraph
controls on a 2702. The other 2702 factors in Table 1
assume a count of 32 for data chaining. (Tables 1-5
are part of the Appendix, which has been placed at
the end of this manual so that it can be removed for
easy reference.)
To obtain maximum compatibility for data chaining
channel programs, addressing resolution on double
word boundaries and byte counts of 16 or greater are
necessary. These parameters are assumed by the channel evaluation procedures in this manual. The procedures allow for computing proper priority load values for data chaining counts other than those specified
in Table l.
Relationship of Conventions and Evaluation Procedures

The evaluation procedures are premised on channel
programs having command sequences that provide efficient operation of r/o devices and avoid unnecessary
loads on channel facilities. Channel programming conventions have been established to guide r/o programmers in avoiding overrun situations.
Observance of channel programming conventions is
fundamental to the selection of an r/o configuration
that will permit concurrent operation of r/o devices
in a satisfactory manner. The channel programming
conventions described below are integral to the channel evaluation procedures. An evaluation yielding an
indication of satisfactory channel performance is not
dependable when channel programs written in violation of the conventions are used.

Classes of Commands

Scope of Conventions

1. The conventions relate to the sequence in which
certain types of commands may be executed, and not
to their sequence in main storage.
2. The conventions define four classes of commands
and the sequence in which they may be used.
3. The command sequences provided by the conventions are different for different types of devices.
Sequences are provided for these devices:
Direct access storage devices - 2302, 2311, 2321, 7320
Tape units - series 2400
Card units - 1442, 2501, 2520, 2540
Printers - 1403, 1443
Console - 1052

Sequences for other devices will appear in a subsequent publication.
4. The conventions relate to all the commands in a

I

The conventions establish four classes of commands.
Commands that always cause mechanical motion are
in one class. The other three classes encompass commands that are always executed at electronic speeds,
plus commands that are sometimes executed at electronic speeds. An example of the latter is rewind,
which is executed at electronic speed when tape is
having electronic-speed properties differ in the length
of time required for their execution.
The conventions for the different devices specify
classifications for the specific commands pertinent to
each device.
The conventions define the four classifications by
the sequence in which they may precede or follow
other commands:
Class A Commands: These commands may be
chained in any order, without restriction. Class A commands cause mechanical motion.
Class B Commands: Only one Class B command
may be chained between two Class A commands:
~
~

A
A

~
~

B
B

~
~

A
B

=

=

permissible command chaining sequence
command chaining sequence excluded
by conventions
Concurrent Input/Output Capabilities

23

A Class B command may be substituted for a Class
C or Class D command.
Class C Commands: A Class C command may appear only once in a channel program, and then only as
the first command in a channel program; a Class C
command may appear only in the location specified by
the CAW:
CAW
CAW

~
~

C
A

~
~

A
C

~
~

B.
A.

=

permissible program
excluded by conventions

= program

A Class B command may be substituted for a Class
C command:
CAW

~

B

~

A

~

B

~

A

~

B.

= permissible

program

Class D Commands: A Class D command may appear only as the last command in a channel program;
it may not specify any chaining:
CAW
CAW

~
~

X
X

~
~

X
D

~
~

D.
A.

= permissible program
= program excluded by conventions

A Class B command may be substituted for a Class
D command.
Some devices have conventions that exclude specific
sequences of commands not excluded by the classifications above.
Some of the devices have conventions that allow a
specific command sequence to be substituted for a
single command of a specified class.

Command Classifications for I/O Devices

The rules below define classifications for specific commands used with a particular device. The bit pattern
for each command code byte is specified to provide
positive identification of commands.
Commands not classified may not specify any chaining and may be placed only in the location specified
by the CAW. Each such command thus constitutes an
entire channel program in which it is the only command. The sense command is used in this manner for
all devices.
Direct Access Storage Devices: These command
classifications are valid for all devices attached to a
2841 control unit.
Class A commands (any order):
XXXX XX10
Write
}
Search
XXXX XX01
Erase
Space Record
0000 1111
0001 0011
Recalibrate
0000 0011
NoOp

24

TIC ~ SEEK

XXXX

1000 ~

SEEK ~ TIC

0000 01l1} ~
OOOX 1011

fOOOO
1000X
XXXX

0111
1011
1000

Class C commands (first ccw in program). These
command chains have the properties of a single Class
C command:
01ll} ~
Seek ~ Set F 1'le Mas k ~ TI C 0000
OOOX 1011
0001 1111 ~ XXXX

1000

Class D commands (last ccw in program):
NoOp

0000

Restore

0001

0011 (except when preceded by a formatting
write)
0111 (NoOp on other than 2311)

Excluded chains:
SEARCH ~ TIC ~ WRITE XOll 0001} ~

X010 1001
XXXX 1000 ~ 0000

X101

Data chaining may propagate through a TIC command for gap-only data:'chaining, as described in the
"Data Chaining in Gaps" section of this manual.
Series 2400 Tape Units
Class A commands (any order) :
Write
Forward space
Backspace
Write tape mark
Erase gap

XXX X
XXXX
XXXX
0011
0010
0001
0001

XX10
XX01
1100
XlII
XlII
llll
0111

Class B commands (not more than one between
Class A commands) :
TIC

XXXX

1000

Class C commands (first ccw in program):
Set Mode

XXXX

XOll

This command chain has the properties of a Single
Class C command:
Set Mode

~

TIC

XXXX

XOll

~

XXXX

1000

Class D commands (last ccw in program):
Rewind
NoOp

0000
0000
0000

0111
1111
0011

Mixed Mode Seven-Track Tape Operations: A routine may be used to select a tape unit, set its density
mode, and then TIC to a desired channel program:
510 ~ Set Mode} Class C
TIC
sequence

(Class A on 2311 only)
(NoOp may be used only when
preceded by a formatting write
0001 XX01 or 0000 0001)

Class B commands (not more than one between
Class A commands) :
TIC
SEEK

These command chains have the properties of a
single Class B command:

XXXX
fOOOO
lo00X

1000
0111
1011

The conventions require the ccw addressed by the
to be Class A.
If the tape applications involve mixed mode seventrack operations, the programmer may make provision
for placing the proper set mode command in the location addressed by the CAW before SIO is issued, or the
programmer may begin each channel program addressed by the TIC with an appropriate set mode comTIC

mand. Such an additional set mode command violates
the convention for Class C commands, and causes an
procedure in this manual by use of a set mode load
factor.
Card Units (1442, 2501, 2520, 2540)
Class A commands (any order) :
XXXX
XXXX

WRITE

XXlO
XXOI

Class B commands (not more than one between
Class A commands):
TIC

XXXX

1000

Class C commands (first ccw in program):
XXXX

CONTROL

XXII

Class D commands (last ccw in program):
XXXX

CONTROL

XX11

Printers (1403, 1443)
Class A commands (any order):
XXXX

WRITE

XX01

Class B command (not more than one between Class
A commands) :
XXXX

TIC

1000

Class C commands (first ccw in program):
XXXX

CONTROL

XX11

Class D commands (last ccw in program) :
0000

CONTROL

0011

Console (1052)
Class A commands (any order):
Write auto carriage return
Write inhibit carriage return

0000
0000
0000

1010
1001
0001

Class B commands (not more than one between
Class A commands):
XXXX

TIC

1000

Class C commands:
Not applicable

Class D commands (last ccw in program) :
XXXX

Control

XX11

Communication Adapters (2701, 2702): Data chaining with or without TIC may be used for these adapters.
Class A commands (any order):
Write
Dial
Break
Diagnostic write
Prepare
Inhibit
Search

}

XXXX

XX01

}

XXXX

XXlO

Class B commands:
Not applicable

Class C commands (first caw in program):
ControlO

xxxx

XX11

Class D commands (last ccw in program) :
Control"*

XXXX

XX11

"*For a communication network of switch-type terminals, these
two control commands are Class A:
Disable
0010
1111
Enable
0010
0111

In evaluating an I/O configuration for successful operation under worst case conditions, consideration may
need to restart an operation due to an occasional I/O
interruption may not be unduly objectionable and/or
reduction in performance of some I/O devices may be
insignificant in many applications.
Concurrent operation of multiplex mode devices important to an application may be assured by giving
them higher priority than devices having less importance, or, higher priority may reduce the frequency of
overrun or loss of performance incurred by a device.
When evaluating the performance of a system susceptible to channel overload conditions, consideration
should be given to the relative ease of restarting an
interrupted I/O operation. For example, an overrun on
a communication line coupling two cpu's is handled
punch. Preferential priority may be given to devices
that require manual intervention in response to an
overrun condition.
Some circumstances may make it desirable to place
devices with heavy load factors on the same selector
channel, rather than on separate selector channels, in
order to preclude interference with each other.
Evaluations should not ignore the characteristics of
IBM Programming Systems packages:
1. Operating System/360
2. Tape Operating System
3. Disk Operating System
4. Basic Operating System
5. Basic Programming Support
These programs will attempt to execute any start
I/O instruction for which the channel and device are
available. The programs that permit concurrent operation of more than one device on a multiplexer
channel will not, however, initiate a burst mode operation on the multiplexer channel while any device
subject to overrun is in operation on the multiplexer
channel.

Concurrent Input/Output Capabilities

25

The impact on a selector channel of a load caused by
operation of an unbuffered I/O device depends on the
device's data transfer rate and on:
Whether the device data chains
Whether the device data chains and also uses TIc'S
Whether the other selector channel data chains
The data chaining and TIC considerations give rise
to several selector channel program relationships. Provision has been made for the various situations by
specifying five different load factors for each unbuffered selector channel device. The first two load factors
relate to channel capabilities and the other three load
factors relate to the input/output capabilities of the
system:
Device under test data chains; the other device does not
data chain (C-l factor).
Device data chains; other device data chains with or without transfer in channel (TIC) operations (C-2 factor).
Device data chains and use TIC's; other device may be
performing any type of channel operation (C-3 factor).

Each device's five factors appear in Table 1. They
are arranged and identified in this left-to-right sequence of column headings:

Data

I

DC

C-I

C-2

C-3

DC
NO DC

DC
DC

DC&T
ANY

The values in the table for the two channel load
factors and the three system load factors assume a
minimum byte count of seven, with no restriction on
the byte addresses of the first and last bytes in a block.
One or more of the five load factors are used in
test procedures that ascertain whether a particular
selector channel configuration will run satisfactorily
or not. The test procedures consider operation of one
selector channel only, or concurrent operation of both
selector channels.
When both channels are desired to run concurrently, each device is tested against overloading its
channel. Maximum selector channel load handling
capabilities are specified in Table 5 for use in the test
procedures. For satisfactory operation, the applicable
channel load limit factor from Table 5 must not be
exceeded by the load computed for a device being
26

considered in a test procedure. If exceeded, overrun
is indicated.
In addition, if either or both of the pair of devices
on selector channels desired to run concurrently use
the input/output facilities of the system. For the latter test, a system load sum is computed. If it is not
greater than the system load limit factor of 100, satisfactory operation is indicated. Otherwise, overrun
is indicated.
test is performed whenever data chaining is used on
one or both channels; data chaining on one channel
has an effect on the other channel.
An exception to the preceding paragraph exists:
when the exception consideration described below is
applicable to both of a pair of devices operating concurrently, their evaluation need not include the system load sum vs system load limit test.

Overrun Test Exception
Under certain circumstances, the load on channel facilities caused by data chaining may be ignored in
testing for channel overload. It then is not a consideration in selecting a load factor or a selector channel
load limit. The exception is valid only for direct access storage devices that are programmed in a certain
way.
A channel program for direct access storage devices,
such as IDM 2311 Disk Storage, must specify command chaining and it may, of course, specify data
chaining operations. The time it takes a gap on a
track to pass a read-write head on one of these devices is sufficient for the channel to perform a data
chaining operation. Gap time occurs in such operations as "write count key and data": gap time occurs
between writing the count and the key, and between
writing the key and the data.
If the program causes data chaining to occur only
during gap time, the data chaining load on channel
facilities will not be additive to the device's data
transfer load. Therefore, data chaining that occurs
only during the gap time may be ignored in testing
the channel against overrun. This gap-only data chaining cannot be ignored, however, in testing the other
channel for overload, if the other channel is using data
chaining other than in gaps.

When both devices are direct access storage devices,
and data chaining occurs for each device only during
test need be made. It is necessary only to test each
on each other.
The overrun test exception for direct access storage
devices has four rules which are:
1. That gap-only data chaining may be ignored in
2. That gap-only data chaining on one channel may
not be ignored when testing the other channel against
overload, if the other channel is data chaining.
3. That if gap-only data chaining occurs on both
channels, neither data chaining need be considered.
4. That whenever data chaining is ignored, only the
limit is used in testing the channel receiving the benefit of the exception consideration.
Use of the overrun test exception is demonstrated
in some of "the test procedure examples given in this
manual.

Overrun Test Procedures
Two selector channel test procedures for unbuffered
devices are given: one for operation of one channel
and one for operation of two channels. They are similar; for the sake of clarity, each is presented separately,
with examples.
Each procedure has been broken into numbered
steps that facilitate discussion and illustration of examples. Once understood, the procedures may be used
rapidly, without specific attention to every numbered
step.
One Channel Overrun Tests

The test procedure for operation of only one selector
channel is performed for each device on the channel
that can be overrun.
The test procedure considers three situations:
Situation 1 No data chaining: The device's data load factor
value from Table 1 is compared with the channel
load limit of 60 from Table 5.
Situation 2 Data chaining: The device's DC load factor value
from Table 1 is compared with the channel load
limit of 50 from Table 5.
Situation 3 Data chaining and TIC: The device's DC load
factor value from Table 1 is compared with the
channel load limit of 40 from Table 5.

For satisfactory operation of the device, the load
value used in the comparison must not be greater than
the selector channel load limit specified. A failure to
pass the test indicates overrun for the device during
worst case conditions.

In the" following examples only one channel is in
operation on a Model 40. Two types of devices are attached:
IBM 2401 Model 3 Tape Unit
IBM 2311 Disk Storage

Channel programming considerations are as specified in the examples.
Situation 1 Example

Model 40 - one selector channel only.
Device - IBM 2401 Model 3, 90 kb, no chaining.
15.3.
Device load factor from Table 1
Selector channel no DC load limit
60.

=

=

The device load is not greater than the pertinent
limit; satisfactory operation is indicated.
Situation 2 Example

Model 40 - one selector channel only.
Device - IBM 2401 Model 3,62.5 kb, data chaining.
DC load factor from Table 1
11.5.
50.

=
=

The device load is not greater than the limit; satisfactory operation is indicated.
Situation 3 Example

Model 40 - one selector channel only.
Device - IBM 2311 Disk Storage, 156 kb, data chaining and
TIC.
DC load factor from Table 1
30.4.
Selector channel DC and TIC load limit
40.

=

=

The device load is not greater than the limit; satisfactory operation is indicated.
Exception

Examp/~

Model 40 - one selector channel only.
Device - IBM 2311 Disk Storage, 156 kb, data chaining and
TIC.

Channel program data chains only during gap times.
This configuration is the same as used in the Situa··
tion 3 example, but, because the direct access 2311
data chains only during gaps, the data chaining is
ignored:

=

20.3.
Selector channel no DC load limit = 60.

These factors are the same type used in a Situation
1 test. The operation performed is the same as in the
Situation 3 example, but, because data chaining is ignored, a smaller load value is compared with a larger
Two Channel Overrun Tests

The test procedure for operation of two selector channels is presented here in six numbered steps that aid
comment upon examples; in practice, attention need
not be focused on every numbered step.
The overrun test exception for direct access devices,
previously discussed, is valid.

27

The step 3 comparison of channel load to channel
load limit is performed for each device in each pair of
devices desired to run concurrently.
The step 6 comparison of system load sum to system
load limit is performed for each pair of devices desired
to run concurrently whenever either or both devices
data chain (subject to overrun test exception).

Device

CHANNEL 1
2401-3,90 kb,
DC
15.3

~~:~/+/ ;jO"J

System load case 1 ( C 1) (J

CHANNEL 2
2401-3,90 kb, Step 1
no DC
Step 2
/15.3~
Step 3
Step 4
compare
Step 5

40.7

(56.0 (15.3+40.7) ..... .
100.0
..... .

Steps in Test Procedure

Step 1. Assign device identity to each channel for
devices to be tested.
Step 2. Reference each device's data load factor from
Table 1.
Step 3. For each device that data chains, reference
Step 4. Reference each channel's channel load limit
data chaining factor from Table 5. If a device does not
limit. If a device data chains, compare its DC load
with its channel load limit. For optimum operation, the
factor selected may not exceed its channel load limit.
Otherwise, overrun is indicated for one or more devices in the I/O configuration, multiplexor channel device ( s) in operation not excepted.
If neither devi":!e data chains, the test has been completed. If either device data chains, the following steps
are performed:
Step 5. Reference each data chaining device's system
load Case 1, 2, or 3 (C1, C2, or C3), as applicable,
from Table 1.
Step 6. To each factor found in step 5, add the data
load factor from the other channel. The sum is the
Step 7. Compare each system load sum found in step
7 with the system load limit of 100.
For optimum operation, no system load sum may exceed 100. Otherwise, overrun is indicated for one or
more devices in the I/O configuration, multiplexor
channel device ( s) in operation not excepted.
Example Configuration

In the following examples, IBM 2401, Model 3 Tape
Units and IBM 2311 Disk Storage units are attached to
each selector channel.
All channel programs for the 2311 direct access storage device data chain only in gaps; the overrun test
exception will apply in the 2311 examples. Data chaining and transfer in channel considerations for the
2401-3 tape unit are as specified in the examples (DC
indicates data chaining; no DC indicates its absence).
Case 1 Example:

28

Step 6
Step 7
compare

(J From Table 1
• (J From Table 5
U(J Tested channel system load plus opposite channel data
o (J.. Fixed value
100

=

The tests indicate satisfactory operation. In the absence of data chaining on channel 2, a system load sum
is not computed for it.
If the devices exchange priority, their channel load
limits are also exchanged but are still ample. The system load sum for the data chaining 2401-3 remains the
same; brief study of the tests already performed shows
satisfactory operation for either priority arrangement.
Case 2 Example:
CHANNEL

1

CHANNEL

2

Step 1
2401-3,90kb, 2401-3,90kb,
DC
DC
Step 2
15.3",,- /15.3
Step 3
17.2).X 17.~
Step 4 compare
32.
+ + 32.
Step 5
62.2'
~2.2
Device

77.5 ,
100. I

77.5 \
100. 1-

Step 6
Step 7 compare

N either load sum exceeds the system load limit; satisfactory operation is indicated.
Case 3 Example:
CHANNEL 1
CHANNEL 2
Step 1
2401-3,90kb, 2401-3,90kb,
DC&
DC&
TIC
TIC
Step 2
15.3~ /15.3
Step 3
17.2)
~7.2)
Step 4 compare
21.6 + + 21.6
Step 5
79.3'
""79.3

Device

+"><.

94.)
100

9J.6
100

Step 6
(Compare
Steps 2&3)
Step 7 compare

Neither load sum exceeds the system load limit; satisfactory operation is indicated.
Exception Example, Both Channels:
1 CHANNEL 2
Step 1
2311, DC& 2311, DC&
TIC
TIC
Step 2
20.3)
20.)
Step 4 compare
50
40

CHANNEL

Device

Data chaining occurs only during gap time (exception consideration). Therefore, the DC load and system
need be computed.
Exception Example, One Channel:
1 CHANNEL 2
2311, DC 2401-3,90kb
Step 1
DC
Step 2
20.3"
15.3
Step 3
17.2)
..... ~"
Step 4 compare
50.
+ 32.
~62.2
Step 5

CHANNEL

Device

82.5 \
100. ...1

Again, step 1 suffices for the direct access storage
device; a system load sum is computed only for the
tape unit.
If the 2311 and 2401-3 exchange channel priority,
their channel load limits are also exchanged, but are
still ample. The system load sum for the 2401-3 remains the same; brief study of the tests already performed shows satisfactory operation for either priority
arrangement.

Step 6
Step 7 compare

29

The multiplexer channel on the Model 40 can handle
a burst mode I/O device with a Table 1 data load
factor not greater than 25. If multiplex mode devices
are in operation when a burst mode operation is initiated on the multiplexer channel, they will overrun or
lose performance when their ability to wait for channel
service is exceeded. Selector channel devices in operation are not affected, but the CPU is unavailable for halt
I/O, start I/O, or any instruction until burst mode operation of the multiplexer channel terminates. See
Table 6 for limitations on simultaneous burst mode
operations.

Multiplex Mode Considerations
Concurrent operation of I/O devices on a multiplexer
channel involves many variables:
1. Devices vary in their data transfer rates.
2. Devices have buffers varying in capacity from 1
byte to 132 bytes.
3. Devices vary in the number and type of ccw's
needed for their operation.
4. Combinations of devices on the selector channels
vary in the interference they cause.
5. The large number of I/O devices available for use
on a multiplexer channel may be combined in many
different configurations.
6. Devices in a particular configuration may be
physically connected in many different priority sequences.
The problem of determining whether a particular
multiplexer channel configuration will run concurrently
in a satisfactory manner has been reduced to arithmetic
procedures using a worksheet form and factors provided in the tables in this manual. The evaluation procedures minimize the need for judgement on the part
of the user by providing a clear-cut decision path
specified in step-by-step procedures.

A numeric factor has been computed for each multiplex mode device to specify its combined data transfer
and channel program load on multiplexer channel facilities. It is called a device load. The factors are listed
in Table 1 of this manual under the columns headed
The term, device load, refers specifically to the Table
1 values mentioned. Each device in Table 1 has other
types of load factors listed for use in considering the
30

impact of higher priority devices on lower priority
devices.
Device Waiting Time

After a multiplex mode device requests channel service,
it has a fixed length of time that it can wait for service.
If the channel provides service within this length of
time, the device operates satisfactorily. If, however,
the channel does not service the device within the device's waiting time, the device must continue waiting
(device not susceptible to overrun) or lose data and
subsequently cause an I/O interruption condition (device susceptible to overru:p.). For example, when an
IBM 1403 Printer on an overloaded multiplexer channel
fails to receive data within its particular waiting time,
it merely waits until service is provided by the multiplexer channel. The delay does not cause an interruption condition; nor is a new start 110 instruction required to select the 1403. The only effect is a lessening
operation does not receive data service within its waiting time, however, overrun occurs.
Multiplex mode device wait time factors, expressed
in milliseconds, are listed in Table 1.
Device Priority on Multiplexer Channel

Priority of devices on a multiplexer channel is determined at the time of installation by the sequence in
which they are connected to the channel. The cabling
facilities provide considerable Hexibility in physical 10cation and logical position of I/O devices.
Devices may have the priority sequence in which
they are attached to the cable (select-out line priority)
or the device most remote from the channel may be
connected to have highest priority, and the device
nearest the channel connected to have lowest priority
(select-in line priority).
Each device on the multiplexer channel cable may
be connected for selection either to the select-out line,
or to the select-in line. Thus, one or the other of the
lines is specified in establishing priority for a desired
physical layout of devices.
Priority assignments and machine room layout
should be established· during the physical planning
phase of an installation so that cables for the I/O devices may be properly specified.
A major consideration in assigning priority to multiplex mode devices is their susceptibility to overrun.
Devices are identified in this manual as being in one of
three categories:

1. Devices subject to overrun, such as magnetic tape
units.
2. Devices that require channel service to be in synchronization with their mechanical operations. For example, the IBM 2540 Card Read Punch has a fixed
mechanical cycle. Delay in channel service for such devices usually occasions additional delay due to synchronization lag.
3. Devices that do not require synchronized channel
service. An IBM 2550 Display is such a device; it is entirely electronic in nature. An IBM 1443 Printer is another device that does not require synchronized channel service; it can begin printing as soon as its buffer
is full and line spacing is completed. Any loss of performance by category 3 devices is limited to that
caused by channel delay in providing service.
Devices in the first category have need for highest
priority. The devices in the last two categories may incur lost performance on an overloaded channel, but are
not subject to overrun; their control units have data
buffers or an ability to wait for channel service. Devices in the second category, however, require higher
priority than those in the third category.
Within each category, devices are assigned decreasing priority in the order of their increasing wait time
factors; smaller wait time factors require higher priority. The factors are listed in Table 1.
When devices that operate only in burst mode, such
as magnetic tape or disk storage devices, are attached
to the multiplexer channel, they should have lower priority than multiplex mode devices. Low priority devices take longer to respond to selection than do higher
priority devices; a burst mode device need be selected
only once for an operation, but a multiplex mode device must be selected for transfer of each byte or few
bytes of data.
The control unit determines whether a device operates on the multiplexer channel in burst mode or in
multiplex mode.
Some devices, such as the IBM 2520 Card Punch, the
IBM 2701 Data Adapter Unit, and the IBM 2821 Control
Unit, may operate on a multiplexer channel in either
burst mode or in multiplex mode, as determined by the
setting of a manual switch on the control unit's customer engineer panel. Such devices are assigned priority on the multiplexer channel as specified above.
A multiplexer channel can transfer data most rapidly
in burst mode. Where an application uses only category 2 or 3 devices that have the mode choice, improved multiplexer channel efficiency may be obtained
by operating the devices in burst mode.
Table 1 specifies whether a device operates in burst
mode, in multiplex mode, or in either mode.

Interference from Priority Devices

The multiplexer channel sustains concurrent operations
in multiplex mode by servicing one device at a time.
The operating devices compete for service, and the
multiplexer channel services them in the order of their
priority.
Devices on the selector channels or higher priority
devices on the multiplexer channel may force a lower
priority multiplex mode device to wait for channel service. The former is called a priority device and the latter is called a waiting device.
When a higher priority device forces a lower priority
device to wait for channel service, the priority device
is said to interfere with the lower priority device. The
device generating interference may be on a selector
channel or on the multiplexer channel.
When more than one priority device forces a multiplex mode device to wait, each of the priority devices
generates interference. All such interference must be
considered in determining whether the waiting device
will receive channel service before its waiting time is
exceeded.
The test precedures for concurrent operation of multiplex mode devices assume that a waiting device has
made its request for channel service at the worst possible time: when the priority devices will cause maximum interference during the waiting device's waiting
time.
The channel ordinarily works its way through the
interference, and the waiting device is unaffected by
the wait. If, however, heavy interference forces the
waiting device to wait past its particular waiting time,
it will be subject to overrun, or it will continue waiting for service.

To evaluate the effect of priority device interference on
a waiting device, a numerical priority load is computed. The significance of wait time as a factor in
computing an accurate priority load is pointed up by
these facts:
1. Each multiplex mode device has a particular wait
time that is critical to its continuous operation.
2. A device's wait time is pertinent to its priority
assignment.
3. A device's wait time is related to the degree to
which it is impacted by interference from a priority
device.
4. This impact, called a priority load, is expressed
numerically as a function of a device's wait time.
Three factors are considered in determining a pri0rity load:
1. The control load cause by execution of ccw's, including chaining and transfer in channel operations.

31

2. The priority device's data transfer load.
3. The waiting time of the device being evaluated.
Note that since a priority load is a function of waiting time, a fixed priority load cannot be established
for a priority device; the priority load caused by a priority device must be computed as a function of a particular waiting devic~'s waiting time.
Ranges of Wait Times

The relationship hetween a priority device's load on
channel facilities and various waiting times is shown
in Figure 5. The abscissa relates to device waiting
times. The short waiting time shown results in a heavy
priority load; the lon~er waiting time falls in a part of
the curve showing much less priority load. The overall
impact of a priority device on a waiting device is more
intense for a waiting device with a short waiting time
than it is to a device with a long waiting time. The latter device can wait for diminishment in the priority
load on channel facilities and still obtain service within
its waiting time.
Two factors, called A and B, are provided in this
manual to relate each device's priority load curve to
different wait times. The priority load curve was considered in segments related to different wait times and
two factors ~ere computed for each curve segment.
These A and B factors are used to compute the device's
priority load in relationship to any waiting device having a wait time falling within range of wait times established for the curve segment. They are used in a
function which defines hyperbolic curves of average
load vs time, based on device/channel time relationships and ch~mnel programming considerations.
Multiple A and B Factors: Table llists A and B factors for each Model 40 input/output device. Where
Table 1 shows a hyphen for an A or a B factor a zero
value is indicated.
Some devices have only one set of A and B factors.
Other devices have more than one set. Only one set is
used in computing a priority load for the device. Each
set has an associated priority time factor that is used
to select the set of A and B factors appropriate to a
particular waiting device.
Priority Time Factors: The priority time factors in
Table 1 are used in the evaluation procedure only to
identify A and B factors for subsequent use.
As each waiting device is evaluated on a multiplex
mode worksheet, its wait time is used to select a set of
A and B factors for each priority device.
Each set of A and B factors in Table 1 has a priority
time factor next to it that specifies the beginning of a
range of wait times significant to that set of A and B
factors. The range extends from the priority time fac32

I

I
I
I

]

i

I

-----+ - I

--------~~--

I
I
I
Waiting Time - - - - -

Longer
Waiting
- - - - - - - - - - - - - - - - - _ , Time

- - - - -..
, Short Waiting Time

These ranges of
Wait Times.

T
4

. . . . . . . . . . . . are defined by these priority
time factors
t

Time

A

B

.200 to 4.77

.200

-

100

~~:7U:O 100

4.77

477.

-

100

454.

4.77

fool

A wait time factor of 6.5

falls in this range . . .
. and this set of A and B factors a re ,;gnlfkont to

0

wo;t;ng } - -

device with a wait time factor of 6.5
Rule: The largest priority time factor that is less than a waiting device's
wait time factor identifies the priority device's set of A and B factors
to be used in computing priority load.

Figure 6. Use of Priority Time Factors

tor specified for the set to the device's next larger priority time factor.
For example, a device may have three sets of A and
B values with three priority time factors specifying
three ranges of wait times. Figure 6 shows priority factors and A and B factors for such a device, as they appear in Table 1 for a 1443 N1 Printer with 13-character set.

The A and B and wait time factors in Table 1 have
been computed for use in a formula that yields the priority load which occurs when a particular priority device interferes with a particular waiting device.

The sum of the B factor and the quotient obtained
by dividing the A factor by the wait time factor is the
priority load. The arithmetic looks like this:
A/wait time

+B=

The tables in this manual provide the A, B and wait
time factors for use in the formula.
Table 1 provides priority load factors for data chaining byte counts of 20 and 100; the factors may be interpolated or extrapolated for other counts by using
a linear function of 1/count.
The procedure for arbitrary counts is:
1. Use wait time to select A and B factors for a
count of 20, compute the priority load, and call it L 20 :
A20
't tIme
'

Wal

+

B20 = L20

2. Repeat step 1 for a count of 100, and call the result L 100 :
AIOO
wait time

+

BIOO =

LIOO

3. Compute the priority load for the desired count:
LIOO

+ (~count

,25) (L20 _ LIOO)

count

As described in the section "Conventions for Satisfactory Channel Programs," additional priority load occurs when a set mode command is used in violation of
the convention for Class C commands. Such use of a
set mode command in a location other than that addressed by the CAW may be considered desirable in
mixed mode seven-track tape operations. If so, the additional priority load is allowed for in the evaluation
to the A factor selected for the tape unit. This factor of
2.5 is an approximation that lends itself to convenient
use.

A waiting multiplex mode device may be forced to
wait for channel facilities, not only by devices with
higher priority, but also by a device with lower priority
that is in operation when the waiting device requests
channel facilities. This is called a previous load and
devices. The device with lowest priority on the channel has no previous load; a zero value is used in the

These loads are developed for each waiting device
waiting device. The load sum for a waiting device
represents the total load on system channel facilities
under a worst case condition when:
1. All priority devices are causing maximum priority
2. Any lower priority device, already in operation,
is making maximum demands on channel facilities
3. The waiting device places its maximum device
A step-by-step procedure for computing load sums
is given in the section "Multiplex Mode Evaluation
Procedure."

A numeric factor of 100 has been established as the
multiplex mode channel load limit. If a load sum exceeds 100, loss of performance or overrun is indicated
during worst case situations. The amount of such loss
of performance may be computed; it is usually small
and infrequent.
Lost Performance Time

A loss of performance indicated by a load sum greater
than 100 is caused by the waiting device having been
forced to wait past its wait time. The total length of
time the device waits for channel service during a
worst case situation is computed as:
d h
I = total delay in channel service in ms
' I
muI tIp ex mo e c anne

Wait time is subtracted from the quotient to find the
amount of time lost:
total delay in ms - wait time = lost performance time in ms

By relating the amount of time lost to the device's
normal operating cycle time, the effect on performance
may be seen:
lost time
- - - - x 100 = percentage loss of performance
cycle time

For a hypothetical device having:
Wait time
20
Cycle time = 200 ms

The arithmetic is:
120 load sum x 20 wait time
100 (limit)

24 ms total delay

and,

Several load factors relating to multiplex mode operations have been described:

24 ms total delay - 20 ms wait time = 4 ms lost performance
time

and
4 lost time
- - - - - x100=
200 cycle time

2 percent loss of performance
(occurs only during worst case situations)

33

Reduced I/O device performance during worst case
situations may be inconsequential to many applications. Even where reduced I/O performance may cause
some programs to have longer run times, the situation
may be not only tolerable, but also practical and
economical.

Multiplex Mode Evaluation Procedure
This section specifies the multiplex mode evaluation
procedure. The next section provides examples of its
use. The subsequent section provides additional information. An understanding of the three sections will
suffice for evaluation of most Model 40 input/output
configurations.
For evaluation of a configuration having 2702 equipment, only as much as necessary of the subsequent
2702 sections need be read. All of the sections relate
to this section: it must be understood first.
The step-by-step procedure given below is used with
a System/360 Multiplexer Channel Worksheet, Form
X24-3407, shown in Figure 8. (Figures 8-11 are part
of the Appendix, which has been placed at the end of
this manual so that it can be removed for easy reference. )
Each step in the procedure is numbered. Most of
the steps call for an entry to be made on a Multiplexer
Channel Worksheet. Figure 9 shows where such steps
cause entries to be made. Each number in the worksheet spaces in Figure 9 refers to the numbered step
in the procedure below that causes an entry to be
made in the space. For example, the top of Figure 9
has a 1 in each of the two spaces that receive the
entries called for by step 1.
As an additional aid in seeing where entries are
made on a worksheet, Figure 10 shows factor values
referenced from Table 1 for evaluation of a configuration specified in the next section of the manual, which
discusses the Figure 10 worksheet example.
The procedure below assumes prior definition and
satisfactory evaluation of the selector channel configuration.
1. Enter system identification and date.
2. Enter identification of the device in each selector
channel group of devices that has the heaviest Table 1
selector channel evaluation procedure. These are the
selector channel priority devices that may impact waiting devices. (Where one or more devices in a selector
channel group have similar loads, but different priority
loads, it may be necessary to repeat the multiplexer
channel evaluation procedure with these other devices
entered as priority devices.)
34

3. Enter the time A B sets from Table 1 for the devices entered in step 2.
4. Arrange the multiplex mode devices proposed
for simultaneous operation into the three priority categories, 1, 2, and 3 as specified for the devices in the
column in Table 1 headed Key.
5. Assign decreasing priority to devices within each
category in the order of their increasing wait time factors, which also appear in Table 1. The device with the
smallest wait time receives highest priority.
6. Enter the devices in the priority sequence established in steps 4 and 5.
7. Enter the wait time, time, A, B, previous load, and
device load factors from Table 1 for the first device
entered in step 6.
8. Repeat step 7 for each remaining device entered
in step 6, except that the lowest priority device has no
9. Compare the wait time factor of the waiting device being evaluated to the time factor ( s) of the first
selector channel priority device; the largest time factor
that is less than the wait time factor identifies the priority device's A and B factors to be entered. (See Figure 6 for guidance.) Where a priority device has only
one set of A and B factors, it is entered.
10. Repeat step 9 for the other selector channel priority device entered in step 2.
11. (This step is performed when evaluating devices
with second or lower priority.) Repeat step 9 for multiplexer channel priority devices instead of selector
channel priority devices.
12. If step 11 has been performed, repeat it for each
remaining multiplex mode waiting device. (This step
12 is effective when evaluating waiting devices with
third or lower priority.)
13. Add the selected A factors and enter the A sum.
When a set mode load factor is necessary, increment
the A sum by 2.5.
14. Divide the A sum by the wait time factor for the
waiting device and enter the quotient.
15. Add the B values entered in step 9, the quotient
entered in step 14, and the device load and previous
16. The load sum must be less than or equal to 100
for satisfactory operation of the waiting device. If a
2702 Transmission Control has a load sum greater than
100, further evaluation is required; consult the "Load
Sums for 2702" section of this manual.
17. Evaluate the waiting device with second priority
by performing for it steps 9-16 (step 12 is not performed).
18. Perform steps 9-16 for all remaining waiting
devices.

Worksheet Example

IBM 2702 Considerotions

The following I/o configuration is evaluated for use
on a Model 40 (Figure 10) :

The IBM 2702 Communication Control may connect a
variety of communication terminals to a multiplexer
channel; 1-15 or 1-31 terminal lines may be connected.
The 2702 uses delay lines for storage of data and
control information. The information circulates in the
delay lines and may be accessed for transfer to or from
the multiplexer channel or to or from a terminal.
When priority devices force a 2702 to wait for channel service, additional delay may occur in the 2702 due
to any time required for synchronization with the delay
line. Such additional delay exists only for the 2702
and does not affect other devices on the multiplexer
channel.
A bit of information takes a certain length of time to
go once around a delay line. A 2702 with capacity for
15 terminal lines takes 0.480 milliseconds per revolution, and a 31-line 2702 has a delay line revolution time
of 0.992 milliseconds. The longer delay line can hold
attached to a 2702 has a direct bearing on how long
they can wait for channel service. Maximum waiting
time exists when only one communication line is used.
Each additional line in operation reduces the length
of time a 2702 can wait for channel service.
In addition, the data transfer speed of a terminal
affects 2702 waiting time; a high speed line cannot wait
as long for channel service as can a lower speed line.
Therefore, different wait time factors are specified in
Table 1 for the different types of terminal controls and
numbers of lines available. Table 1 also provides different wait time and device load, previous load, CPU
interference, and priority load factors for each type of
terminal control. The values in Table 1 are for all lines
operating at the same speed.

Selector Channel 1
Selector Channel 2
Multiplexer Channel

2311 Disk Storage, data chaining only
in record gaps
2400 Tape, 60 kb, no data chaining
1442-Nl Card Read Punch, card image
1442-N2 Punch, card image
1443 Printer, 39-character set
1052 Keyboard-Printer

The section "Exception Example, One Channel"
showed satisfactory operation for a similar selector
channel configuration having a greater load (the selector channel 2 tape operation was at 90 kb and used
data chaining). Therefore, satisfactory operation is indicated for the selector channel devices in this example.
Selection of the priority load factors for' the selector
channel devices in the multiplex mode evaluation assumes tape writing and gap-only data chaining on the
2311.
The 1442-N1 is evaluated for reading, which causes
a greater channel load than punching. Card image
operations are assumed for both 1442's.
The 1052 has been assigned lowest priority on an arbitrary basis.The multiplexer channel configuration is evaluated
for multiplex mode operations (Figure 10), as specified
in the preceding section of this manual. The procedure
has four parts:
1. Assign priority to devices
2. Reference factor values from Table 1
3. Enter the values found on the Multiplex Mode
Worksheet
The completed worksheet (Figure 10) shows satisfactory operation for all multiplex mode devices: no
Worksheet Entries for 2821

Each device attached to an IBM 2821 Control Unit is
evaluated as if it were a separate control unit. Each
device has its own channel service requirements and is
evaluated in a separate column on the Multiplexer
Channel Worksheet. This may cause the worksheet
evaluation procedure for some configurations to spill
over onto blank paper.
The priority sequence for 2821 devices is:
2. IBM 1402 Card Punch
3. Printer ( s)
Printer Control No.1
Printer Control No.2
Printer Control No.3

Worksheet Example With Two 2702's and a 2821

The following Model 40 I/o configuration is evaluated
in this example:
Selector Channel 1:
Selector Channel 2:
Multiplexer Channel:

2311 Disk Storage, all data chaining
in gaps
90 kb Magnetic Tape, data chaining
100 bytes
2702 - 15 1030's @ 600 bps
2702 - 31 1050's @ 14.8 bps
2540 Punching EBCD
1403-Nl Printing 1100 LPM
1403-Nl Printing 1100 LPM
1443-Nl - Printing 240 LPM - 52
character set
1052 - Console Typewriter

The selector channel evaluation example already
given in this manual indicated satisfactory operation of
the selector channel configuration. The multiplexer
channel configuration is evaluated for multiplex mode
operations by:

35

1. Assigning priority to devices.
2. Referencing factor values from Table 1.
3. Entering the values found on the M111tiplexer
Channel Worksheet.
The completed worksheet is shown in Figure 10. The
1052 has been assigned lowest priority on an arbitrary
basis.
The load sum for the IBM 1443 Printer is 116.3; loss
of performance is indicated for the 1443 during worst
The maximum length of time that channel service to
the 1443 Printer would be delayed may be computed:

conclusion that the frequency of overrun will not be
great enough to be objectionable for a particular application.
Special Analysis of 2702 Performance

waiting device load sum x waiting device wait time =
100
maximum delay in ms

Values for the 1443 are:
116.3 x 18.5
= 21.6 ms
100

The 1443 can wait 18.5 ms for its buffer to be serviced; in this worst case situation, it must wait an additional 3.1 ms (21.6 - 18.5 == 3.1). The 1443 ordinarily
prints a line in 250 ms. An increase to 253.1 ms during
a period of maximum priority loads is little more than
1 percent.
When a 2702 has it load sum in excess of 100, the
"Load Sums for 2702"~ection of this manual is pertinent.
When a 2702 contributes priority load to any device
Factors for 2702" section of this manual is pertinent.
Load Sums for 2702: Because of the variables involved, the wait time, device load, and previous load
factor values specified in Table 1 have been computed
with a conservative bias for use with a Multiplexer
Channel Worksheet. In most instances, their use in
computing 2702 load sums will give an indication of
satisfactory operation. Whenever a 2702 load sum exceeds 100, additional examination of the situation is in
order.
To this end, a special analysis procedure, unique to
the 2702 is provided in the next section of this manual.
The procedure uses a special 2702 worksheet for analysis of the situation, with resolution to a single delay
line cycle.
When the special analysis indicates satisfactory
operation of the 2702, attention may be returned to the
Multiplexer Channel Worksheet for evaluation of the
next waiting device. If, however, the special analysis
load sum still indicates an overrun, some of the communication lines may have to be connected to another
2702 in order to eliminate overrun.
In a system with a large number of terminal lines,
construction of a probabilistic model may lead to the
36

I

Whenever the Multiplexer Channel Evaluation Worksheet procedure finds a load sum greater than 100 for
an IBM 2702 Communication Control, the more sophisticated performance analysis given here may indicate
satisfactory operation. A special worksheet and special
tables, unique to the 2702, are used.
The special analysis assumes that all attached communication lines will request service during a single
delay line revolution and that a scanning sequence will
occur that gives service last of all to the highest speed
communication line. The analysis reveals whether,
considering priority loads, the number of delay line
revolutions available is sufficient for the total delay
line revolution requirements of all communication
lines.
It is seldom necessary to test every communication
line's requirements for delay line revolutions. After a
communication line tests satisfactorily, a projection is
made of both the minimum and the maximum number
of revolutions needed to service the remaining communication lines. When a projected maximum is less
than the maximum revolutions needed for the highest
speed remaining line, satisfactory operation is indicated and no further analysis is required. Similarly, if
a projected minimum is greater than the maximum
revolutions needed for the highest speed remaining
line, overrun is indicated, and the analysis is complete.
The projections are made on the 2702 Worksheet
as the procedure progresses. Figure 7 illustrates the
relationship of the two projections to the maximum
number of revolutions needed for the highest speed
line. Satisfactory operation is indicated in Figure 7
whenever an upper curve crosses the line indicating
the maximum number of revolutions before overrun.
To determine the number of delay line cycles required by a particular communication line, tables of
factor values are provided in this manual for use with
the 2702 Worksheet, Form X24-3406.
The factors are used to compute a load sum occurring during the servicing of each communication line.
by selcctor chal...el priority devices and by multiplexor channel priority devices, plus a device load factor and a previous load factor for the terminal being
tested. The various factors are entered on the 2702
Worksheet and used to compute a load sum which is
compared to the load limit specified on the worksheet
for that particular delay line revolution (first, second,
etc. ).

~

prOjected

Maximum

Operation Satisfactory

----

----------

Maximum number
of revolutions
before overrun

Projected Minimum

Special Analysis Procedure

1 2 3 4 5 6 7 8 9 10 11 12 13
Number of Communication Lines Tested

Q)

c:

:.::;

satisfactory opcration and thc analysis is complete.
A high comparison indicates a need to test the next
communication line. This is done by transferring some
of the values on the worksheet in use to a fresh 2702
Worksheet and testing the next communication line
for satisfactory operation. A load sum is computed
and compared with the load limit. Comparison results

Maximum number
of revolutions
before overrun
Projected Minimum

Number of Communication Lines Tested

• Figure 7. Projection of Delay Line Revolution Requirements

limit, the communication line under consideration requires an additional delay line revolution. The projected minimum time for service is increased one revolution and tested. If overrun is not indicated, the next
column of the 2702 Worksheet is used to compute a
new load sum which is compared, etc.
H, however, the first load sum mentioned in the
previous paragraph was not greater than the specified
load limit, adequate service is indicated for the communication line under consideration, and if it was serviced in one revolution, or if it is the last communicaton line to be considered, satisfactory operation of the
2702 is indicated. But if the communication line serviced was not the last one and was not serviced in a
single revolution, it is necessary to see if the remaining communication lines can be serviced within the
number of revolutions remaining to them. A new projecton of the maximum time for service is made.
In this analysis, no remaining communication line
will take more revolutions than the communication
line for which satisfactory service was just indicated,
so if the number of revolutions it required is multiplied by the number of remaining lines, the results
may be compared to the remaining number of revolutions available. A low or equal comparison indicates

The procedure given below is used with the 2702
Worksheet, shown in Figure 12. Each step in the procedure is numbered. Most of the steps call for an
entry to be made on the 2702 Worksheet. The numbers in the Figure 13 spaces refer to the step numbers
that cause entries to be made in the spaces. (Figures
12-16 are part of the Appendix, which has been placed
at the end of this manual so that it can be removed
for easy reference.)
The procedure is shown in flow chart form in Figure 14. It also is keyed to the numbered steps in the
procedure. Figure 15 shows the worksheet example
discussed in the next section of this manual .
The procedure for using the 2702 Worksheet is:
l. Enter the number of communication lines proposed for attachment into the number of lines space
and also into the first and second n spaces.
2. Enter 1 in the line number space.
3. Subtract the step 2 entry from the step 1 entry
and enter the remainder in the K space.
4. Consult Table 2 and find the smallest Nmax
value among the terminals proposed for attachment.
Enter the value found in the Nmax space.
5. From Table 2, enter device load and previous
load values shown for the terminal selected in step 4.
6. Enter identification of selector channel and multiplexer channel priority devices in the leftmost column
in the order of their priority (copy from the Multiplexer Channel Worksheet).
7. Enter a tl value of zero.
8. Enter zero values in the A 1 and B 1 spaces.
9. Enter a t2 value.
When j = 1, the t2 value is:
tl
.464 for a 15-line 2702
tl
.976 for a 3I-line 2702
When j > 1, the t2 value is:
for a 15-line 2702, previous t2
.480
for a 31-line 2702, previous t2
.992
10. Use the t2 value just entered to select A2 and
B2 factors from the left-hand column of the Multiplexer Channel Worksheet. The selected A's and B's
are copied from the Multiplexer Channel Worksheet
into the A 2 and B 2 spaces on the 2702 Worksheet.
The second set of time A B factors used for a pri-

+
+

+
+

37

ority 2702 with a mix of communication line speeds
may be:
a. As specified in Table 1 for the highest speed
line, or
b. As computed with the procedure given in the
"Priority Load Factors for 2702" section of this
manual.
11. This step is performed only once per worksheet:
enter the Al sum and Bl sum. (When line number ==
1, Al sum and Bl sum have zero values.)
12. This step is performed only once per worksheet:
multiply the Bl sum by the tl value and enter the
product.
13. Enter the A2 sum and B2 sum.
14. Multiply the B2 sum by the t2 value and enter
the product.
15. Subtract the Al sum from the A2 sum and enter
the A remainder.
16. Subtract the Bl product from the B2 product
and enter the B remainder.
18. The load sum is compared to the appropriate
service is indicated; go to step 22. If greater, the communication line needs another delay line revolution;
go to step 19.
19. Add 1 to the last entered n value, and enter the
sum in the next n space.
20. If the new n value is greater than the Nmax
value, no additional delay line revolution is available
for the communication line. This indicates overrun.
21. If the new n is not greater than N max, go to
step 9 and repeat the performance analysis for the
fresh delay line revolution. When j is greater than 8,
the analysis spills over to another worksheet, and each
48.0 for 15-line 2702
99.2 for 31-line 2702
22. The step 18 load sum was not greater than the
load limit, thereby indicating adequate channel service for the communication line under test. If this is
the last communication line, or if it was serviced by
the first delay line revolution (j == 1), satisfactory
operation of the 2702 is indicated. But if the communication line serviced was not the last one and was not
serviced by the first revolution (j greater than 1) add
its n value to the product of its revolution number
minus one (j - 1) times K, and enter the sum in the
space at the bottom of the worksheet, where n
(j 1) K is printed.

+

38

23. If the value just entered is not greater than the
Nmax, satisfactory operation of the 2702 is indicated.
If greater, get a fresh 2702 worksheet.
24. The number of lines entry for the fresh worksheet stays the same as it was on the old worksheet.
25. The new line number entered is 1 greater than
the old line number. The subtraction specified on the
worksheet gives a new K value entry 1 less than the
old.
26. Enter a new tl value by adding 0.048 to old t2.
27. The new tl is used to select priority device A
and B factors from the Multiplexer Channel Worksheet for entry into the Al and Bl spaces.
28. The old n value is entered into the spaces under
tl and j == 1.
29. Go to step 9.
2702 Special Analysis Example

Figure 15 shows a Multiplex Mode Worksheet evalua-

I tion of a Model 40 configuration having these

I/o

devices:
Selector Channel 1:

I

2311 Disk Storage, chaining with record
20
size
Selector Channel 2:
2311 Disk Storage, data chaining only
in record gaps
Multiplexer Channel:
2702 with 15 1030'soO running at 600 bps
2702 with 15 1030's running at 600 bps
2702 with 10 1030's running at 600 bps
2702 with 1 1030 running at 600 bps
and 10 telegraph lines (45 bps)
1443 Printer (Other devices in the multiplexer channel configuration are not
operated concurrently.)
oOData Collection System

=

Figure 15 shows an excessive load sum of 119.7 for
the 2702 having fourth priority; use of the 2702 special
analysis procedure is indicated.
Figure 16 shows the completed 2702 Worksheet
used in the special analysis. The 2702 special analysis
procedure in the preceding section of this manual was
used in making the entries.
Figure 16 (Sheet 1) shows service to be completed
for the 1030 on the fifth cycle; the projected maximum
number of cycles needed is 55, which is greater than
the Nmax of 30; a fresh 2702 Worksheet is used.
Figure 16 (Sheet 2) continues the analysis. The
Nmax factor of 30 does not' change; the procedure
assumes that if all terminals request service, the 1030
may be the last to be serviced. The Nmax factor for
the highest speed line is always used.
Figure 16 (Sheet 2) shows that the projected maximum number of revolutions needed for the remaining
telegraph lines is not greater than Nmax.
This indication of satisfactory operation for the 2702
completes the evaluation of the communication configuration for concurrent operation.

An IBM 2702 Communication Control may have terminallines attached that all operate at the same speed.
Where this is the case, priority load A and B factors
used for the Multiplexer Channel Worksheet evaluation are referenced from Table 1 for the type of terminal control and number of lines attached.
An mM 2702 Communication Control may have a
configuration of terminal lines that operate at different
speeds. Where this is the case, the Table 1 priority
load factors for the highest speed line may be used.
The A and B factors are referenced for the number
of lines attached and are entered on the Multiplexer
Channel Worksheet. In so doing, the slower speed
lines receive undue weight, but if their use does not
cause any load sum to exceed 100, satisfactory operation is indicated. The disparity in line speeds may be
ignored.
If their use indicates unsatisfactory multiplexer
channel operation, however, a more accurate assessment of the situation may be made, as described below.
When A and B factors from Table 1 for a priority
2702 having more than one terminal speed are selected
for the highest speed line, their use may contribute
to an excessive load sum for a lower priority device
and a false indication of unsatisfactory operation.
More accurate time, A, and B factors may be computed for consideration in computing priority loads
for 2702's with terminal lines of different speeds attached. The computation has three basic steps:
1. Retain the first set of time A B factors already
entered on the Multiplexer Channel Worksheet for the
priority 2702.
2. Compute a new second set of time A B factors
which replace the second set already entered.
3. Use the new wait time ranges established in steps
1 and 2 immediately above to select A and B factors
for use in computing a new priority load for the 2702.
sum that is less than or equal to 100 indicates satisfactory operation for the load sum device.
Each new second set of time A B factors is computed as specified in steps 1-7 below. An example
computation is shown immediately following step 7.
1. Select from Table 3, Segment 1, a b factor for
each type of terminal. Multiply each b factor; by the
number of terminal lines having that b factor, and
add all of the products. The sum of the products is the
new B factor.
2. Subtract the new B factor, from the B factor specified in Segment 2 of Table 3. The remainder is an
intermediate value used in step 4.
Note that the set of time A B factors in Segment 2

are the same as the first (uppermost) set already entered for the priority 2702 on the Multiplexer Channel
Worksheet. This first set does not change.
3. Find the time factor for the number of lines
attached in Segment 3 of Table 3. This is the new time
factor.
4. Multiply the new time factor by the remainder
found in step 2. The product is an intermediate factor
used in step 5.
5. Add the A factor in Segment 2 of Table 3, to the
product found in step 4. The sum is the new A factor.
6. Substitute the time A B factors found in steps 3,
5, and 1 in place of the second set of time A B factors
previously entered on the Multiplexer Channel Worksheet for the priority 2702.
7. Repeat steps 1-6 for any remaining 2702 priority
devices and consider the new time A B factors in computing new load sums for the devices previously found
For example, a new second set of time A B factors
are computed for a 2702 with a mix of line speeds as
shown below.
Consider a I5-line 2702 to which is attached:
One 1030 Line - IBM Terminal Control - Type 11 @ 60 bps
Ten 1050 Lines - IBM Terminal Control - Type 1 @ 135.5
bps
Step 1. From Table 3, Segment 1
1030:
1 x .166 = .166
1050:
10 x .035
.350

=

new B = .516
Step 2. From Segment 2: B
From step 1: new B

=

12.01
.516

11.494
5.182
Step 3. For 11 lines: Time
Step 4: From step 2: Difference
11.494
Time
5.182

=

Step 5.

=
=
= 59.562

Product
From Segment 2: A
5.411
From step 4 Product = 59.562

=

=

Step 6.

new A
64.973
Previous priority load factors (from Table 1):

TIME

A

5.41
.200
58.2
5.18
TIME

A

.200
5.18

5.41
65.0

B

12.0
1.83
B

12.0
.516

Synchronization Tendency of Buffer Servicing

When evaluation of a multiplex mode configuration
shows loss of performance for several buffered devices, additional analysis may show that some of them
can be expected to have infrequent, trifling reduction
in performance, and that others will have loss in performance somewhat more often. This is because of

39

the tendency of multiple buffered devices to synchronize, to a greater or lesser extent, their use of channel
facilities. The analysis enables an estimate to be made
of how often a buffered device can be expected to
have loss in performance.
By estimating the delays involved in servicing the
device's buffers and relating the delays to the device's
requests for channel service, it may be discovered
that some of the buffered priority devices do not interfere with buffered waiting devices to the extent
premised in the evaluation procedure. The procedure
assumes a random relationship between the operations
of the various I/O devices that may not apply to buffered devices.
For example, if both of two card readers in operation request channel service at the same time, the
higher priority device will force the other device to
wait; and having once waited, the second card reader
will next request channel service after the first device
The two new requests will not coincide unless the first
card reader has been similarly delayed by some other
device. This synchronization effect tends to organize
buffered device's requests for channel service into a
sequence that enables the channel to service them on

40

a rotating basis, and a loss of performance premised
on random channel service requests may be significantly reduced.
The analysis of the synchronization effect is done by
laying out the operating cycles of the buffered devices
in their priority sequence, one below another, on a
millisecond scale. The devices that operate satisfactorily are drawn with a zero starting point. A new
starting point is established on the millisecond scale
for each device found to incur delay. The resulting
synchronization pattern may be studied to see which
buffered device priority loads may be ignored in computing new load sums.
Operation cycle times are specified in Systems Reference Library manuals for the devices.
Multiplexer channel capabilities for maintaining
performance of multiple buffered I/O dev:::!es may be
calculated through simulation with greater accuracy
when the number of characters in a line of print,
forms layout, programming requirements, etc., are
known for a particular application. On the other hand,
an application known to be cpu-limited will cause reduced input/ output performance, even though the
channels are capable of operating the I/O devices concurrently at their rated speeds.

Channel Interference with CPU

A channel operation on the Model 40 interferes with
CPU use of main storage whenever the channel requests access to main storage. Additional CPU interference is generated because the channels use some
CPU facilities. Burst mode operation of the multiplexer
channel locks out the CPU.
Each device operating in multiplex mode causes CPU
interference. The amount of CPU interference caused by
an I/O device over a period of time depends on its data
transfer rate and its channel programming. Table 4
lists the factors used to compute Model 40 channel interference with CPU.
When an application requires concurrent operation
of I/O devices, it must first be determined that the
devices will operate without overrun. This is done as
manual.
Channel Interference Procedure

After an indication of satisfactory operation has been
found, channel interference with the CPU may be computed, after which available CPU time may be computed. The procedure has three steps:
1. Examine record lengths, data transfer rates, gap
times, device operating cycle times, etc., and establish an I/O operation time span in milliseconds pertinent to the application.
2. Add the microseconds of CPU interference caused
during the I/O time span by:
a. Execution of start I/O'S
b. Execution of ccw's
c. Data transfer
d. I/O interruptions
Interference for fetching the CAW and the specified
ccw are not a factor; they are fetched during start
I/O interference time.
3. Subtract the sum of total CPU interference time in
milliseconds from the I/O time span. The difference is
the milliseconds of time available for CPU operations
during the time span.
Dividing the available CPU time by the time span
and multiplying by 100 gives the percentage of available CPU time for the application considered:
available CPU time
- - - - - - - x 100
time span

= % available CPU time

The CPU time required by a program to identify
interruptions, etc., is not considered in this manual.

An application that uses more CPU time to process
input data for output than is computed to be available
will have an actual I/O time span greater than that
found in the computation of available l."'PU time. The
increased I/O time span will result in an increase in
job time for the application that may be computed as:

+

channel interference time
CPU time needed = increased
time span
increased time span - original time span
time span increment
time span increment
- - - - - - - x 100
% increment in job time
original time span

=

=

In the rare instance where available CPU time is
computed to be zero, CPU operations are not necessar-ily precluded; the CPU may yet gain occasional access
to storage. Thus, a finding of 100 percent CPU interference cannot be depended upon to prevent execution of
a start I/O instruction that could overload the channels and cause overrun or loss of performance.
On the other hand, a computation of less than 100
percent CPU interference does not insure that the I/O
devices will run concurrently. As stated previously,
the configuration must be separately evaluated for
concurrent operations.
Available CPU Time Example
Application

Tape-to-printer operation
Configuration

The Model 40 uses a data-chaining IBM 2403 Model
2 tape unit at 800 bytes per inch (bpi) on the first
selector channel, and an IBM l403-Nl Printer on the
multiplexer channel.
Analysis

The tape read operation handles 1000-byte tape blocks
data chained into ten scattered 100-byte blocks in
main storage.
The printer may be programmed with a start I/O
for each line of print, or it may be programmed with
one start I/O and nine chained commands for each ten
lines of print. The difference in CPU interference causcd
by the two approaches is examined in the example.
Evaluation for Concurrent Operation

Overrun or loss of performance appear unlikely.
Briefly, however, these are the considerations:
Channel Interference with CPU

4]

The 2403-2, 800 bpi DC load of 11 is less than the
single selector channel DC load limit of 50; it will run
satisfactorily. Only one set of A B factors are listed
for the priority 2403-2, 800 bpi, without byte conversion and they are A == 0.98
B == 8.10. The 1403
has a wait time of 15.7.
The A/wait time
yields:

+

~
+ 8.10
15.7

is 0.64. A load sum is computed:

=

8.16
14.4
0.64

=
= 23.20

The load sum is less than 100; satisfactory concurrent operation is indicated.

The computation of available CPU time demonstrated
below uses the same four steps already described:
1. Establish I/O time span.
2. Compute channel interference with CPU.
3. Subtract sum of interference from the time span
to find available CPU time.
4. Divide available CPU time by time span to obtain
percentage of CPU time available.
The information necessary to execute step 2 is
found in Tables I and 4, and operating cycle times
for I/O devices are found in the IBM Systems Reference
Library Principles of Operation manuals for the devices.
Table 1 provides data transfer rates, gap times, and
multiplex mode CPU interference per byte in microseconds.
Table 4 provides selector channel microseconds CPU
delay per byte transferred, plus microseconds CPU
delay per ccw execution and end interruptions.
Step 1: Establish time span.
The time needed to read this 1000-byte tape record
block (24.7 ms) may be referenced directly from the
tape timing card, IBM System/360 Magnetic Tape
Record Chat'acteristics for IBM 2400 Series Magnetic
Tape Units, Form X22-6837, or computed from the
factor values for the formula on the same card:

=
=

=

+
+
+

0.0333N
0.0167N
O.OlllN

This formula, gap time plus byte time x number of
bytes, allows for both tape start and stop time.
For our example:

=

0.0167 x 1000
16.7
8.0 + 16.7
24.7 milliseconds to read each 1000 byte block

=

42

10 x 54.5

= 545 milliseconds

to print 10 lines

The tape and printer operations will be overlapped,
and the longer printer time of 545 ms is the time span
pertinent to the application configuration.
Step 2: Compute channel interference with CPU.
Tape transfer interference time is the product of
the number of bytes in the tape block multiplied by
the selector channel byte transfer CPU interference factor, 1.25 microseconds (from Table 4):
1000 x l.25

= 1250 microseconds

tape transfer interference

Tape data chaining interference time is the product
of the number of data chaining operations per record
block and the selector channel data chaining CPU interference factor, 10.625 microseconds (from Table
4) :
9 x 10.625

ference

Arithmetic for Channel Interference Example

Modell - ms per record block
16.0
Model 2 - ms per record block = 8.0
5.3
Model 3 - ms per record block
N
Number of bytes in record block

The time to print ten lines is ten times 1403 N1
print cycle time:

= 95.625

microseconds tape data chaining inter-

Printer transfer interference is found by referencing
Table I and computing the product of the number
of characters per print line times the multiplex channel byte transfer CPU interference factor, 16.5 microseconds (from Table I) times the number of print
lines handled during the time span:
100 x 16.5 x 10
ference

= 16500 microseconds printer transfer inter-

Printer command time is the product of the number
of chained commands per time span times the multiplexer channel command chaining CPU interference
factor, 68.1 microseconds (from Table 4):
9 x 68.1

= 612.9 microseconds printer command interference

Start I/O interference factors are referenced from
the instruction timing section of this manual, end interruption factors are referenced from Table 4, and
total interference time may be computed:
Tape

MICROSECONDS

~rtVO

~O

Transfer interference (as previously computed) 1250.0
Data chaining interference (as previously
computed)
95.6
Channel end with device end interruption
45.0
Printer
Start
65.0
Transfer interference
16,500.0
Command chaining interference
612.9
Channel end interruption
60.6
Device end interruption
56.9

va

Total interference time

=

18,73l.0

Step 3: Compute available CPU time in milliseconds.
Available CPU time is found by subtracting the interference time from the time span:
545. - 18.7

=

526.3 milliseconds available CPU time

Step 4: Compute available CPU time as a percentage.
The CPU interference may be expressed as a per-

centage by dividing the interference time by the time
span and multiplying by 100:
18.7/545 x 100

= 3.4 percent CPU interference

Command Chaining Efficiency

By ignoring printer data transfer interference, attention may be focused on the CPU interference caused by
channel control functions for the printer. In the example, command chaining may be eliminated if a start
I/O is used for each print line. A comparison of the
CPU interferences caused by the two methods reveals
which is more efficient, as shown below.
Printer control interference using command chaining is:

If command chaining is not used for printer operation each print line occasions a start I/O and an end
interruption, and the following arithmetic applies:

=

MICROSECONDS

Start I/O - 65 x 10
Device end - 56.88 x 10
Channel end - 60.63 x 10
Total

650.
568.8
606.3
1825.1

Printer control interference using no command
chaining is 1825.1 microseconds.
The use of a start I/O for each print-line occasions
1825.1 - 795.4 = 1029.7 microseconds additional CPU
interference. Command chaining is clearly more efficient.

MICROSECONDS

Start I/O
Command chaining
Channel end
Device end
Printer control interference using command
chaining =

65.0
612.9
60.6
56.9
795.4

Channel Interference with CPU

43

System/360 Model 40 Instruction Times

The instruction time tables presented in this bulletin
are divided into two groups:
Group 1

Group 2

This group of instruction times provides the
average time for all instructions used with the
Model 40.
This group of instruction times contains the
detailed timing formulas for all variable field
length ( VFL ) instructions used with the
Model 40.
All symbols used in the VFL formulas should
be interpreted in accordance with the Legend
for System/360 Timing.

Within each group, timings are provided for instruction execution when instructions and data are
located in processor storage. All times are given in
microseconds. Complete information for each instruction is included in the publication IBA1 System/360
Principles of Operation, Form A22-6821. Standard
System/360 Timing Legends have been provided,
therefore all legends listed may not apply to the
Model 40.
Timing Considerations

The following conditions (unless otherwise noted)
were used in the development of these instruction
time tables (both groups).
1. The time required for indexing by a base register
is included in the times given. For those instructions
that may be double indexed (indicated by one or two
asterisks in the instruction name column), an additional 1.25 microsecond (one asterisk) or 1.88 microsecond (two asterisks) must be added to the times
given in the table.

2. In all arithmetic operations, positive and negative operands are equally probable.
3. Each bit location has equal probability of containing bit values 0 or 1, and each bit location is independent of other bit locations.
Decimal data may contain digit values 0-9 in each
digit position with equal probability.
4. Instructions may start on even or odd halfwords
with equal probability.
5. Interruptions are not reflected in these timings.
6. All timings provided include both decoding and
execution of the instruction.

Timing Assumptions

The following assumptions (unless otherwise noted)
were used in the development of the instruction time
tables.
1. For decimal add (AP) and decimal subtract (sp)
instructions, the first operand (i.e., the destination
field) is assumed to be equal to or greater than the
length of the second operand (i.e., the source field).
2. The instruction times for the floating-point instructions depend on the number of hexadecimal
digits that are preshifted and postshifted, as well as
the number of times recomplementation of the result
occurs. Each of the floating-point instruction times
listed is an average of actual execution times. Although
each value is the most accurate that can be given, the
actual time is data-dependent.
3. The supervisor call (svc) instruction includes interruption time.

Average Times
INSTRUCITON

FORMAT

MNEMONIC

RR

AR

7.5 + 1.25G2

RX

A

11.88 + 1.25G2

SS

AP

28.75 + 1.25N 1 + 2.5M - 1.25T16

RX

CH

(Inequality determined by:)
Signs
9.38
Byte 0 or 1 10.00
10.63
Byte 2
Byte 3 or == 11.25

Compare Logical

RR

CLR

7.5

Compare Logicall>

RX

CL

11.88

Compare Logical

SI

CLI

8.75

Compare Logical

SS

CLC

12.04

Compare (Long)

RR

CDR

33.15

+ 1.25Nt + 1.25M + 1.25Tt6

+ 2.81B + 3.73Tt5

System/360 Model 40 Instruction Times

45

INSTRUCTION

FORMAT

MNEMONIC

Compare (Long) 00

RX

CD

28.80

Compare (Short)

RR

CER

11.90

Compare (Short) 00

RX

CE

16.38

Convert To Binaryo

RX

CVB

Number of Significant
Average Timl
Digits
31.88
0
31.88
1
32.19
2
36.25
3
40.31
4
46.88
5
53.44
6
60.63
7
67.81
8
77.50
9
86.56
10

Convert To Decimal 0

RX

CVD

( Subscript shows number
28.13
CVD4
40.00
CVD g
CVD2
53.75
CVDt
72.50
95.63
CVDo

Divide

Jl.R

DR

Significant Divisor Bytes
4
3
2
1

Time
188.0
192.5
143.8
156.0

Divide o

RX

D

Significant Divisor Bytes
4
3
2

Time
143.0
146.9
139.4
141.0

1.
Divide Decimal

SS

DP

13.13 + 29.06N
+ 11.25N2 (Nt -

Divide (Long)

RR

DDR

472.5

Divide (Long) 00

RX

Divide (Short)

RR

DER

136.30

Divide (Short) 00

RX

DE

141.08

Edit

SS

ED

'DD

1 -

480.65

21.25 + 3.12N + 3.44N2 - .94N4
+ .63N + 2.5SG
21.25 + 3.12N + 3.44N2 - .94N4
+ .63N + 2.5SG + 3.13MK
5

Edit and Mark

SS

EDMK

5

46

22.81N2
N2)

INSTRUCTION

FORMAT

MNEMONIC

Exclusive OR

RR

XR

7.5

Exclusive OR 0

RX

X

11.88

Exclusive OR

SI

XI

9.38

Exclusive OR

SS

XC

Execute~

RX

EX

+ 3.13N
8.13 + .625T12 + E

Halt I/O

SI

HIO

See I/O' Tables

Halve (Long)

RR

HDR

231.85

Halve (Short)

RR

HER

+ 9.4X + 7.25H2
101.16 + 3.84X + 3.75H2

Insert Character 0

RX

IC

9.38

Insert Storage Key

RR

ISK

7.5

RR

LR

7.5

RX

L

11.88

RX

LA

10.0

RR

LTR

7.5

RR

LTDR

12.5

RR

L'fER

7.5

RR

LCR

7.5

RR

LCDR

12.5

RR

LCER

7.5

RX

LH

10.63

RR

LDR

12.5

RX

LD

16.88

RS

LM

6.25

RR

LNR

7.5

RR

LNDR

12.5

RR

·LNER

7.5

RR

LPR

7.5

RR

LPDR

12.5

RR

LPER

7.5

SI

LPSW

16.25

16.88

+ 1.25G2

+ 5GR

+ 1.25G2

System/360 Model 40 Instruction Timings

47

INSTRUCTION

MNEMONIC

RR

LER

7.5

13.13 + 3.13N 1 + 1.25N2
+ 1.25N2 (LB2) + 1.25 (1- LB2) (HB2 + 1)
Case 2:

Compare Decimal-CP

22.5 + 1.25NI + 1.25M + .625
[(1-TI6) +2 (I-TI6) HB2-LBd
Compare Logical-CLC

N2
2
13.13 + 5.63Nl + 2.5 (LB 2) (N2 -1)

IfNl~

Case 1: If number of bytes compared before inequality is found to be less than or equal to N
16.26 + 5.63 NWBBI + .63 HB2
+ 4.38 HBI (1- HB 2)
Case 2: If operands are equal
14.06 + 2.81 N + .31
[3HB 1 + 6HB2 + 4LBI + 3LB2
-10 (LBt) (LB2)]

Trans/ate-TR

Divide Decimal-DP

15.63 + 6.25N + 1.88HBI + .63LBI

Subtract Decimal-SP

26.88 + 1.25N1 + 2.5M + .625
[3HBl- LBI + (1- T 16 ) + 2 (1- T16 ) HB2]

Translate and Test-TRT
EDIT-ED

28.13 + 3.12N + 1.25HBI - .63LBI + .63Ns
- .94N4 + 6.88 NWBL 2 - .63HB2 + 2.5 SG
EDIT and MARK-EDMK

28.13 + 3.12N + 1.25HBI - .63LBI + .63Ns - .94N4
+ 6.88NWBL2- .63HB2 + 2.5SG + 3.13MK
Exc:lusive OR-XC

14.38 + 3.13 N + 3.13HBI + 3.75HB2
- 3.13 (HBt) (HB2) - .63 (LBI) (LB 2)

Case 1:
Condition Code 0
15.63 + 3.75N + (4.38HB 1 + .63LB1) (1 - T 18)
Case 2:
Condition Code 1
20.63 + 3.75B + 4.38HBI - 1.88LBI
Case 3:
Condition Code 2
20.0 + 5.63N + (4.38HB 1 - .63LBI
- 1.88N) (1 - T 18 )

Move Charac:ters-MVC

14.38 + 2.5N + 2.5HBI + 3.13HB2
- 1.88 (HBl) (HB2) + .63LB2
-1.88 (LBl) (LB 2)
Move Numerics-MVN

14.38 + 3.75N + 3.13 HBI + 3.75 HB2
- 3.13 (HBI) (HB2) - .63 (LBl) (LB2)
Move with Olfset-MVO

13.75 + 5.63Nl + T 13 (2.50 - 2.5NI + 2.5N2)

Unpack-UNPK

Case 1:
If Nl > 2N2
13.13 + 1.56Nl + 2.5N2 + 1.56(LBt) NI
+ .94 (1- LB 1 ) (HBI + 2)
Case 2:
IfNl~2N2

15.94 + 2.34N1 + 1.56 (LBl) Nl + 3.44HB 1
- 4.69 (LBl) (HBl) - .31LB 1

Move Zones-MVZ

14.38 + 3.75N + 3.13HB1 + 3.75HB2
- 3.13 (HBl) (HB2) - .63 (LBI) (LB2)

24.38

+ 2.5M +

1.88HB 1

System/360 Model 40 Instruction Timings

51

Legend for System/360 Timing

This section contains legends for the timing formulas
for the cases where multiple timing formulas fr ... instructions are listed. In some cases more than Olle timing formula for an instruction may be given.
Legends Al to A4 are timing formulas for Store Multiple or Load Multiple instructions depending on
quantity of general registers and position with respect
to doubleword boundaries.
A1 : Use if the number of registers is 2, and if the operand lies on doubleword boundaries
A2 : Use if the number of registers is > 2 and even,
and if the operand lies on doubleword boundaries
A3: Use if the number of registers is even, and if the
operand does not lie on doubleword boundaries

C 1 : Use when the number converted contains eight or
less decimal digits
C 2 : Use when the number converted contains more
than eight decimal digits, but seven or less hexadecimal digits
C 3 : Use when the number converted contains more

Legends CVDo to CVD 4 are timing formulas to use
for the Convert to Decimal instruction, depending on
the number of leading zero bytes.
CVDo: Use if there are no leading zero bytes
CVD 1 : Use if there is one leading zero byte
CVD 2 : Use if there are two leading zero bytes
CVD 3 : Use if there are three leading zero bytes

A4: Use if the number of registers is odd

CVD4: Use if there are four leading zero bytes

Legends A5 and A6 are timing formulas for the Subtract Halfword instnlCtion.

Legends DI to DB are timing formulas to be used
depending on the state of the addressed channel.

A5: Use if leading 16 bits are not changed by Subtract
Halfword instruction

D 1 : Use if the multiplexer channel is busy and in the
multiplex mode

A6: Use if leading 16 bits are changed by Subtract
Halfword instruction

Legends BI to B4 are timing formulas to be used

D 2 : Use if the multiplexer channel is busy and in the
burst mode - first execution
D3: (Same as D 2 ) - executions subsequent to the first,
during the same burst mode operation

B1 : Use when addressing the multiplexer channel in
the multiplex mode

D 4: Use if the multiplexer channel is idle

B2 : Use when addressing the multiplexer channel in
the burst mode - first execution

D5: Use if the multiplexer channel has an interruption
pending

B3: (Same as B2 )

D6: Use if the selector channel is busy

- executions subsequent to the first,
during the same burst mode operation

B4 : Use when addressing the selector channel

Legends CHI to C H 4 are timing formulas to use for
Compare Halfword instruction, depending on the nature of the numbers being handled.
CH 1 : Use if signs differ

D7: Use if the selector channel is idle
DR: Use if the selector channel has an interruption
pending

Legends El to E4 are timing formulas to use for the
Execute instruction, depending on the instruction
length code and varying conditions.

CH 2 : Use if signs are alike, and the high-order 16 bits
of the first operand are significant

E 1 : Use when subject instruction is one halfword long

CH3: Use if inequality is found in byte 2

E 2 : Use when subject instruction is two halfwords
long

CH4: Use if inequality is found in byte 3, or if comparison is equal

Legends CI to C 3 are timing formulas to use for
radix (number base) conversion instructions, depending on the size of the number converted.
52

E3: Use when subject instruction is a three-halfword
character instruction
E-t: Use when subject instruction is a three-halfword
decimal instruction

Legends V 1 to V 4 are timing formulas to use for the
Move instruction, depending on the location of operand fields.
V I: Use if first and second operand fields start and
end on doubleword boundaries
V2: Use if first and second operand fields start at corresponding byte addresses within doublewords
but do not lie on doubleword boundaries
V3: Use if first and second operand fields do not start
at corresponding byte addresses within doublewords or if N < 8.
V4: Use if first and second operand fields start on
doubleword boundaries but do not end on doubleword boundaries. N must be greater than seven
to use this case.
NOTE: A byte address of a doubleword can have
the value 0, 1,2,3,4,5,6, or 7.
This section contains the legends for terms to be
used in the timing formulas for System/360.

G 5 = 0 if first operand is positive
= 1 otherwise
GR = Number of general registers loaded or stored
HBI

1 if the address of the high-order (leftmost)
byte of the first operand is odd
o otherwise

HB2

1 if the address of the high-order (leftmost)
byte of the second operand is odd
= 0 otherwise

H

number of significant (i.e., other than high-order
zeros) hexadecimal digits in the binary operand

H2

Number of high-order hexadecimal zeros in the
second operand

Hs

H2/2 if H2 is even
= H2/2 + 1 if H2 is odd

H4 = 4 - H/2 if H is even
H-l
42
if H is odd

ABV = Absolute value (i.e., unsigned value) of
NWBLI - NWBL 2
B = Total number of bytes of the first operand which
are processed (applies to instructions with a
single-length field)
E

(H4 has a minimum value of 1)
KI

Time for the subject instruction which is executed by the Execute instruction

ED = External delay

Number of zero··hexadecimal digits (both leading and imbedded) in the absolute value (recomplemented jf negative) of the factor with
a smaller absolute value. In Multiply Halfword
KI applies only to the 16 low-order bits of that
factor
1 if a guard digit is involved

F = Input! output field length specified in Transfer
110 instruction

Ll

F I = 1 if the branch operation is successful
= 0 otherwise

LBI

1 if the address of the low-order (rightmost)
byte of the first operand is odd
o otherwise

LB2

1 if the address of the low-order (rightmost)
byte of the second operand is odd
o otherwise

F2

0 if the R2 field (specified in the RR formatted
branch instruction) is zero (i.e., branch is suppresssed)
1 otherwise

G I = 1 if an overflow interruption occurs (PSW bit
36 = 1 or fixed-point divide interruption occurs
o otherwise
G 2 = 1 if overflow occurs and fixed-point interruption
is masked (PSW bit 36 = 0)
= 0 otherwise
G 3 = 0 if operand to be converted is positive
1 otherwise
G 4 = 1 if condition code is zero; i.e., all of the
selected bits are zero or mask is all zero
= 0 otherwise

ootherwise

M = greater of Nt or N2
MK = number of times the mark address is stored
in the Edit and Mark instruction
MQt

=

0 if multiplier or quotient lies on a word
boundary
= 1 otherwise

N = total number of bytes in the first operand for
those instructions with a single length field
Nt

total number of bytes in the first operand (destination)
Instruction Times

53

N2

total number of bytes in the secoIid operand
(source)

N3

total number of bytes which overlap between
the first and second operands
o for nonoverlapping fields, and for overlapping
fields where the address of the second operand
is greater than or equal to (2::) the first operand address

N4

=

total number of field separator characters in the
edit pattern

N5

=

total number of control characters in the edit
pattern

S1 = 1 if r4 = 3, or if q4 == 0
= 2 if r4 == 3 and q4 == 0
o otherwise
S2 == -1 if r4 == 0
1 if r4 == 1, and q4 == 0
o otherwise
S3

0 if r 4 == 0, and q4 =I=- 0
= 1 if r4 == 0, and q4 == 0
= 3 if r4 = 1
5 if r4 == 2 or 3

S4

=
=

N n = number of bytes of the field which lie outside of
that part of the field bounded by double words
NWBB 1 = number of word boundary crossovers for
that part of the first operand processed

0 if r4 == 0
4 if q4 == 0 and r4 == 1, or if q4 =I=- 0 and r4 == 2
= 3 if q4 == 0 and r4 == 2, or if q4 =I=- 0 and r4 == 3
== 2 if q4 == 0 and r4 == 3
5 if q4 =I=- 0 and r4 == 1

S!)

o otherwise

number of word boundary crossovers for
that part of the second operand processed
NWBL 1

number of word boundary crossovers for
the first operand (destination)

NWBL 1L 2

NWBQl
NWBR 1
q4

=

=

1 if operand is negative
o otherwise

S7 == 1 if r4 =I=- 0 and operand is negative
o otherwise

number of word boundary crossovers
for that part of the first op~rand which
consists of N2 bytes of high-order zeros

1 if the result field is recomplemented

(i.e., changes sign)

o otherwise

number of word boundary crossovers for
the second operand (source)

T 2 = 1 if the result field is zero
= 0 otherwise

number of word boundary crossovers for
the quotient field

T3 == 1ifN2<~~(N1+1)
= 0 otherwise

number of word boundary crossovers for
the remainder field

T 4 = 1 if the second operand has leading hexadecimal zeros
= 0 otherwise

quotient found by dividing the number of positions to be shifted by 4

T6

qs = quotient found by dividing the number of positions to be shifted by 8
Q4 = 1 of q4 == 0
= 0 otherwise

remainder found after dividing the number of
positions to be shifted by 4

H4

=
=

remainder when N is divided by 8

1 if r4 = 0
= 0 otherwise

SG = number of signs in the field to be edited
54

0 if N2 S 4
1 otherwise

o if N1 S

8

1 otherwise

Ts

o if fields do not overlap
1 otherwise

QS = smaller of N1 - 8 or N1 - N2

Ra

1 if the even-numbered register is zero

T9
T 11

0 if any nonzero function byte is found

= 1 otherwise
= 1 if N > ~~ (N + 1)
1

2

= 0 otherwise
T 12 == 1 if R1 field of the Execute instruction is not
zero
= 0 otherwise

o if N2

~

Nl

1 otherwise
T14

1 if NWBL 2 = 0
= 0 otherwise

T Hi = 1 if B = N and operands are equal
= 0 otherwise
TI6

TI7

= OifN I ~

N2
1 otherwise

=

N2
1 if N1 >
2
0 otherwise

TIS = 1 if N = 1
= 0 otherwise

T 19 = 1 if N 1 > 2N 2
= 0 otherwise

T 20 = 1 if signs are unlike for Add Decimal or if
signs are alike for Subtract Decimal, when second operand > Hrst operand
o otherwise
U 1 = select out delay plus device delay
U 2 = device delay for halt I/O sequence
V

absolute value (i. e., unsigned value) of N 1

X

number,of binary 1's in the fraction of the number to be halved

W

total number of doublewords in the first operand for those instructions with a single length
field

-

Instruction Times

N2

55

Appendix

--_. -

CHANNEL
INPUT/

NOMINAL

OUTPUT

DATA

DEVICE

KEY

1
CYCLE
TIME

RATE

2

3

MULTIPLEXER CHANNEL

SELECTOR

r-

CHANNEL

DC DC&'I
DC
B
A
DATA

DC

INC DEVICE IOUS
TIME

-

PREV-

WAIT

- - - ------

CPU
INTF

TIME

B

A

~

Consoles
1052
Ptrkbd

2M

Var

....

....

150ms

0.3

0.4

14.8cs

....

....

....

. .....

. .....

. ... . .

70.0

.034

.143

28.0

.200
70.0

5.63
3.06

.037

.200
2.80
.200
2.80

7.05
17.3
7.05
13.4

7.55
3.90
7.55
5.30

.200
12.5
.200
12.5

8.56

Punched Card I/O and Printers
1442-N1
EBCn
Card
Image
Punching
EBCn

1M
1M

.53kb
1.07kb

1.0

1.5

1.9

150ms

.200
2.80
.200
2.80

.800

4.20

12.5

39.0

.800

5.90

12.5

26.5

0.95

0.31
0.14
0.62
0.28

...

0.48

2M

.12kb

656ms

0.1

0.0

0.0

0.0

0.0

.200

0.75

0.01

11.0

0.30

0.90

39.0

Card
Image
1442-N2
Punching
1443-N1
Printer
13 Char
Set

2M

.24kb

656ms

0.1

0.0

0.0

0.0

0.0

.200

0.75

0.02

11.0

0.43

0.90

26.5

39 Char
Set

3M

......

0.65

8.56
0.98

Same as 1442-N1 Punching

3M

52 Char
Set

3M

63 Char
Set

3M

1.44kc

.72kc

.58kc

.48kc

100 ms

200ms

250ms

300 ms

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

.200
1.70
100.
.200
1.70
200.
.200
1.70
250.
.200
1.70
300.

10.6
18.0

......

.....

0.19
10.6

18.0

18.0
......

. ,'-

18.0
...

18.5

25.8

0.54

29.6

18.5

25.8

0.54

29.6

25.8

0.54

29.6

25.8

0.54

29.6

......

.095
10.6 18.5
. .. .. .
.076
10.6 18.5
......

.063

.200
4.77 477.
100. 454.
.200 .-, .
4.77 477 .
200. 466.
.200
4.77 477.
250 . 468.
.200
4.77 477 .
300. 469 .

100.
4.77
100 .
2.38
100.
1.90
100.
1.59

Key:
1- May be overrun
2- Will not overrun - Synchronous mechanical operation
3- Will not overrun - Asynchronous operation
-B Burst mode operation on multiplexer channel
-M Multiplex mode operation on multiplexer channel
----

Table 1. IBM System/360 Model 40 Channel Evaluation Factors

Appendix

57

CHANNEL
NOMINAL
DATA

INPUT/
OUTPUT
DEVICE

KEY

RATE

1
CYCLE
TIME

2

3

MULTIPLEXER CHANNEL

SELECTOR
CHANNEL

WAIT~'

DATA DC
DC
DC DC&T
B
A

PREV!

INC DEVICE IOUS

CPU

INTF

TIME

TIME

B

A

-f---

2821 Ctrl
Unit
2540 Card
51 Col Rd
EBCn
Column
Binary

2M

2M

EBCn

2M

Column
Binary

2M

Punch
EBcn

Column
Binary
1403 Ptr
Model 2
Std
600 LPM
DCS
750 LPM
Md13&N1
Std
1100 LPM
UCS
1400 LPM

2M

2M

3M

3M

3M

3M

1.07kb

2.13kb

1.33kb

2.67kb

.33kb

.67kb

1. 32kc
1.6.')kc

2.42kc

3.08kc

75ms

75ms

60ms

60ms

200ms

200ms

100 ms

80ms

54.5 ms

42.8 ms

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.0

.200
.480
75.0
.200
.960
75.0
.200
.480
60.0
.200
.960
60.0

21.0
10.0
9.95
20.0
19.8
10.0
9.94
20.0
19.7

.200
.480 10.0
200. 9.98
.200
.960 20.0
200. 19.9

.200
.660
100.
.200
.660
80.0
.200
.660
54.5
.200
.660
42.8

0.13
21.0 8.00

16.5
16.4

0.27
21.0

16.5
16.3

42.8

6.50

26.9

6.50

52.6

......

0.16
21.0
.....

0.33
21.0

VJ.O

14.1

.200 ......
1.75 175 .
75.0 171.
1.22 21.0 .200 ......
3.42 342 .
75.0 326.
1.50 21.0 .200 ......
1.75 175 .
60.0 170.
1.50 21.0 .200 ......
3.42 342.
60.0 324.

1.22

0.70

21.0

23.7

.....

0.05
21.0
'"

14.0

27.7 0.70

23.7

.

0.10

15.7

14.4

0.64

16.5

......

0.16
25.0

15.7

14.4

0.64

16.5

......

0.21
25.0

16.5
16.3

21.8

.....

25.0
16.5
16.4

8.00

......

0:30
25.0
.....

0.38

15.7

15.7

14.4

14.4

0.64

0.64

16.5

16.5

.200
1.98
200.
.200
3.88
200.

.200
2.26
100.
.200
2.26
80.0
.200
2.26
54.5
.200
2.26
42.8

10O.
....

2.34
10O.
....

4.5 6
10o.
....
2.9 o
10o.
. ....

5.7o

388.
381.

10O•
.....
0.9 o
10O.
....
1.94

......

10O.

......

198.
196.
......

226 .
221.

,

. ....

.....

2.2 6
100

226 .
219

2.8 3

. ...

......

100
.....
4.1 o
100

226 .
214.

5.3 o

......

226.
216

. ....
--

Key:
1- May be overrun
2- Will not overrun - Synchronous mechanical operation
3- \Vill not overrun - Asynchronous operation
-B Burst mode operation on multiplexer channel
-M Multiplex mode operation on multiplexer channel
Table 1. (continued)

Appendix

59

CHANNEL
INPUT/OUTPUT
DEVICE

NOMINAL
DATA
RATE
KEY

1

GAP OR
CYCLE
TIME

2

DC DC

DATA

DC

3
DC&T
ANY

DATA CHAINING

NO DATA
CHAINING
TIME

B

A

COUNT A
TIME

20
B

COUNT TIME
A

-

100
B
-

2400 SERIES
MAGNETIC TAPE
DENMDL SITY

1

200

BYTE

No
Yes

556

No
Yes

800

No~

Yes
2

200

556

200

1B
1B
1B

20.8kc
15.6kb
30.0kb
22.5kb

Yes

1B

11.3kb

No

No~

No

No
Yes

800

1B

5.6kb

15.0kc

Yes
556

1B

7.5kc

1B

Yes
3

1B

No

Yes
800

GAP
TIME

CONY

No~

Yes

1B
1B
1B
1B
1B
1B
1B
IB
IB
1B

41.7kc
31.3kb
60.0kb
45.0kb
22.5kc
16.9kb
62.5kc
46.9kb
90.0kb
67.5kb

20.0ms
20.0ms
20.0ms
20.0ms
16.0ms
20.0ms
10.0ms
10.0ms
10.0ms
1O.Oms
8.0ms
10.0ms
6.7ms
6.7ms
6.7ms
6.7ms
5.3ms
6.7ms

1.3
1.3
3.5
3.5
5.1
5.1
2.6
2.6
7.1
7.1

1.3
1.3
3.6
3.6

3.1
3.1

4.7
4.7

6.0
6.0

8.6 13.2 16.8
8.6 13.2 16.8

5.3 12.7 19.4 24.7
5.3 12.7 19.4 24.7
2.7
2.7

6.3
6.3

9.6 12.3
9.6 12.3

7.5 17.8 27.2 34.6
7.5 17.8 27.2 34.6

10.2 11.0 26.1 39.9 50.9
10.2 11.0 26.1 39.9 50.9
3.8
3.8

4.0
4.0

9.4 14.3 18.3
9.4 14.3 18.3

10.6 11.5 27.3 41.7 53.2
10.6 11.5 27.3 41.7 53.2
15.3 17.2 40.7 62.2 79.3
15.3 17.2 40.7 62.2 79.3

.200
2.56
.200
3.43
.200
.923
.200
1.28
.200
.640
.200
.854

2.40

.200
1.28
.200
1.70
.200
.461
.200
.614
.200
.320
.200
.426'

2/10

......

0.94

...

2.40

......

0.70
2.40

....

2.60

...

2.40
. . .. . .
2.40

......

1.95
......

3.75
2.40
2.81

...

. . . .. .
1.88

2.40
1.41

....

2.40

......

......

5.21

2.40
......

2.40
'"

.

...

3.91
....

......

1.31
0.98
. .....

3.64
......

2.73
......

5.25
......

3.93
......

2.62
...

1.97
7.29

.200 2.40
.256 1.00
.200 0.95

5.47
10.5

.200

7.88

. ..

.200
1.34
.200
.355
.200
.449
.200
.645
.200
.341
.200
.452
.200
.674
.200
.895
.200
.248
.200
.327
.200

2.40 . ....
1.05 1.01
2.40 ......
1.05 0.76
2.40 ......
1.03 2.81
2.40 . .....
1.04 2.11
2.40 . .....
1.02 4.05
2.40 ......
1.03 3.03
2.40 ......
1.04 2.02
2.40
1.04 1.52
2.40 ......
1.00 5.65
2.40 . .....
1.02 4.22
0.98 ·8.10

.200
.230

2.40
1.00

7.50

2.40

....

....

5.63

.200 2.40
.854 ...
.200 2.40
1.14 ....
.200 2.40
.307 ......
.200 2.40
.410
.200 2.40
.213
.200 2.40
.284 ....

.200 2.40
1.03 1.05
.200 2.40
1.77 1.05
.200 2.40
.355 1.02
.200 2.40
.502 1.03
.200 2.40
.267 1.00
.200 2.40
.352 1.02
.200 2.40
.523 1.03
.200 2.40
.690 1.04
.200 0.98

.....

2.81
.....

2.11
......

0.98

. .....

6.08

.200 2.40 . .....
.200 2.40
.352 1.02 3.93 .450 1.03 3.04
.200 2.40 . ..... .200 2.40 ......
.464 1.03 2.95 .597 1.04 2.28
.200 0.95 10.9 .200 0.97 8.44

7.81
......

8.2

.200

0.90

15.8

.200
.221
.200

.200

0.94

11.8

.200

.200

0.98

5.86
......

2.40
1.00
0.94

6.33
12.2

0.97

9.13

. .....

11.3
8.44

~Gap

time nine track only
Loads for seven or nine track

Key:
1- May be overrun
-B Burst mode operation on multiplexer channel
------

Table 1. (continued)

Appendix

61

CHANNEL
GAP OR

DATA
KEY

RATE

CYCLE
TIME

1B

7.5kc

20.0ms

INPUT/OUTPUT
DEVICE

NOMINAL

1

J2

DC
DC
DC

DATA

~------~

DATA CHAINING

NO DATA

3

= 20

CHAINING

DC&T

B

ANY

TIME

A

6.0

.200
3.36
.200
4.50
.200
1.21
.200
1.62
.200
.840
.200
1.12

3.15

......

..... ,

0.94

COUNT
A
TIME

= 100

COUNT
A
TIME

B

-

-----------

B

WRITING
DEN-

BYTE

MDL SITY

CONV

1

200

No
Yes

556

No
Yes

800

2

200

556

800

3

200

No~

1B
1B
1B
1B

5.6kb
20.8kc
15.6kb
30.0kb

Yes

1B

22.5kb

No

1B

15.0kc

Yes

1B

11.3kb

No

1B

41.7kc

Yes

1B

31.3kb

Noll)

1B

60.0kb

Yes

1B

No

1B

Yes

1B

45.0kb
22.5kc
16.9kb

20.0ms
20.0ms
20.0ms
16.0ms
20.0ms
1O.0ms
10.0ms
10.0ms
1O.0ms
8.0ms
10.0ms
6.7ms
6.7ms

1.3
1.3
3.5
3.5
5.1
5.1
2.6
2.6
7.1
7.1

1.3
1.3
3.6
3.6

3.1
3.1

4.7
4.7

6.0

8.6 13.2 16.8
8.6 13.2 16.8

5.3 12.7 19.4 24.7
5.3 12.7 19.4 24.7
2.7
2.7

6.3
6.3

9.6 12.3
9.6 12.3

7.5 17.8 27.2 34.6
7.5 17.8 27.2 34.6

10.2 11.0 26.1 39.9 50.9
10.2 11.0 26.1 39.9 50.8
3.8
3.8

4.0
4.0

9.4 14.3 18.3
9.4 14.3 18.3

3.15

......

......

0.70

3.15
3.15
......

800

No

IB

Yes

IB

62.5kc
46.9kb

6.7ms
6.7ms

10.6 11.5 27.3 41.7 53.2
10.6 11.5 27.3 41.7 53.2

Noll)

1B

90.0kb

5.3ms

15.3 17.2 40.7 62.2 79.3

Yes

IB

67.5kb

6.7ms

15.3 17.2 40.7 62.2 79.3

1.95

3.15

.....

.....

3.75

3.15
2.81

.200 3.15
1.68 ....
.200 3.15
2.23 .....
.200 3.15
.605 ....
.200 3.15
.806
.200 3.15
.420
.200 3.15
.560
.200 3.15
1.12
.204 3.15
1.49 ....
.200 3.15
.403 ......
.200 3.15
.538 ....
.200 3.15
.280 ....
.200 3,15
.373 .....
,

556

...

2.60

...

....

1.88
1.41
......

5.21
.....

3.91
.....

7.50
...

5.63
2.81
....

2.11

.200 3.15
1.60 1.05
.200 3.15
2.14 1.05
.200 3.15
.548 1.42
.200 3.15
.777 1.03
.200 3.15
.410 1.00
.200 3.15
.541 1.02
.200 3.15
.810 1.03
.200 3.15
1.06 1.04
.200 3.15
.298 0.98
.200 3.15
.393 1.00
.200 3.15
.210 0.95
.200 3.15
.275 0.98
.200 3.15
.542 1.02
.200 3.15
.719 1.03
.202 0.95

......
1.31
. .....

0.98
. ...

3.89
......

2.73
......

5.25
......

3.93
. .....

2.62
......

1.97
7.29
....

5.47
....

.

10.5
. ....

7.88
....

3.93
......
2.95
10.9

7.81
....

5.86

.200
.255
.200

3.15
0.98
0.95

.. .. .
8.24
15.8

.200

0.94

11.8

.200 3.15
2.08 1.05
.200 3.15
2.75 1.05
.200 3.15
.695 1.03
.200 3.15
1.00 1.04
.200 3.15
.527 1.02
.200 3.15
.700 1.03
.200 3.15
1.04 1.04
.200 3.15
1.37 1.04
.200 3.15
.382 1.00
.200 3.15
.505 1.02
.200 3.15
.268 0.98
.200 3.15
.354 1.00
.200
.697
.200
.925
.200
.258
.200
.340
.200

3.15
1.03
3.15
1.04
3.15
0.97
3.15
1.00
0.94

.200
.243

3.15
0.93

......

1.02
......

0.76
3.05
......

2.11
. .....

4.04
.....

3.43
2.02
.....

1.52
5.63
. .....

4.22
. .. . . .
8.10
. .....

6.08
. . .. . .
3.04

. .....

2.28
....

8.44
......

6.33
12.2

11.3
...

8.45

. ...

-

.

9.13
_.-

«Gap time nine track only
Loads for seven or nine track
Key:
1- May be overrun
-B Burst mode operation on multiplexer channel
-.

Table 1. (continued)

AppendIx

6:3

FNNEL

NOMINAL
DATA
KEY
RATE

INPUT/OUTPUT
DEVICE

GAP OR
CYCLE
TIME

J

1
DC

2
DC

DATA DC

3
DC&T
ANY

DATA CHAINING

NO DATA
CHAINING
TIME

A

COUNT
B

= 20

COUNT

TIME

A

B

.200
.267
.200
0
.200
0

2.4
0
1.0 5.25
1.0 10.5
0
0
1.0 10.5
0
0

=100

TIME

A

B

.200
.346

2.4
1.0

0
4.1

.200
0
.200
0

1.0
0

B.l
0

1.0
0

B.l
0

---

2400

SERIES

MAGNETIC TAPE
DEN-

BYTE

CONV'
MDL SITY

4

5

6

GAP
TIME

BOO

#

IB

30kb

16.Oms

1600

#

IB

60kb

16.0ms

10.2 11.0 26.1 39.9 50.9

BOO

#

IB

60kb

B.Oms

10.2 11.0 26.1 39.9 50.9

1600

#

800
1600

#

IB 120kb
IB 90kb
IB IBOkb

B.Oms
5.3ms

20.4 23.9 56.B B6.6 ""~
15.3 17.2 40.7 62.2 79.3
30.6 39.1

.200 2.40
0
.640
.200 2.40
0
.320
.200 2.40
.320
0
.200
0
0
.200
.200
0

0
3.75

15.0
11.3
22.5

.200
.200

1.0 21.0
1.0 15.B

.200
.200

1.0
1.0

.200

1.0

31.5

.200

1.0

16.2
12.2
24.3

BOO

.200
.B40
.200
.420
.200
.420
.200

0
3.75
0
7.5

.200
.410
.210
0

0
5.25
10.5
0

.200
.265

3.15
1.0
3.15
1.0

0
4.1
0
B.1

3.15
0
0
3.15
0
0

0
7.5
15.0

.200
0
2.00
.200
0
.200

3.15
1.0
1.0
0
1.0
0
1.0
1.0
0
1.0

.200
.530

1600

3.15
0
3.15
0

10.5
0
21.0
15.B
0
31.5

.200
.265
.200

3.15
1.0
1.0

0
B.l
16.2

.200
0
.200

1.0
0
1.0

12.2
0
24.3

#

5.3ms

5.1

5.3 12.7 19.4 24.7

~~

~~

~~

0
7.5
0
7.5

WRITING

4

5

BOO

1600
6

(All data same

BOO

.200
.2BO
.200

1600
# Data conversion not used on this model
U
--------~---.---"-.-.----

Table 1. (continued)

64

..

------~-----.-.----

0
11.3
22.5

-

iOMINAL
INPUT/OUTPUT
DEVICE

Direct Access
Storage
2302 Disk
Storage
Models 3 and 4
2303 Drum
2311 Disk
Storage
Drive Modell
2314 Direct
Access Storage
Facility
2321 Data
Cell Drive

KEY

DATA
RATE

1B

156kb

1C

303.8kb

CHANNEL
GAP OR
1
2
3
CYCLE DATA DC
DC&T
DC
DC
ANY
DC

Rotatn
Time
34.0ms 20.1 30.1 71.3

1B

156kb

17.5ms 39.1 l//# >:1>:1
25.0ms 20.3 30.4 72.1

1C

312kb

25.0ms 40.9

1B

54.7kb

50.0ms

"*~

>:1"*

>:1>:1

>:1>:1

>:1#

>:I""

>:1>:1

>:1>:1

#\t<

>:1#

NO DATA
CHAINING
A
TIME

.200

3.40

-

DATA CHAINING
B

21.3

.8

2.80

20.3

.200

2.05

41.5

.8

1.17

40.9

COUNT =20
TIME
A
B
---- r-

.200

1.60

COUNT =
TIME
A

100
B

-

---

28.9

.200

3.40

21.3

.8

1.06

22.0

7.3 10.2 24.2 36.9 47.0
---

-

iKey:
1- May be overrun
-B Burst mode operation on multiplexer channel
-C Selector channel only
_T _ _

-

Table 1. (continued)

Appendix

65

----

15 LINE

NOMINAL
INPUT/OUTPUT DEVICE

KEY

DEV

MAXIMUM

PREV
B
A

DATA
RATE

CPU
INTF

WAIT

8.3cps

29.6

116.
58.1

.016
.033

.086
.172

38.4

.049

.261

28.8

.066

.347

23.0

.083

.434

19.2

.099

.521

16.3

.117

.613

14.4

.132

.695

12.5

.152

.802

11.5

.16,1)

.869

10.5

.180

.948

9.58

.198

1.04

8.62

.220

1.16

8.14

.233

1.23

7.66

.248

1.31

31

NR

OF
LA

WAIT DEV

LINE MAXIMUM
PREV

B
A

TIME

---

-

--

Communication Equipment

2702 Transmission Ctl
IBM Term Ctl-I
75 bps

Key:

1M

1- May be overrun

.200
.200
.573
.200
1.09
.200
1.60
.200
2.11
.200
2.62
.200
3.13
.200
3.65
.200
4.16
.200
4.67
.200
5.18
.200
5.69
.200
6.21
.200
6.72
.200
7.23

6.15 .020
5.41 12.0
12.3 .040
5.41 12.0
18.4 .060
5.41 12.0
24.5 .080
5.41 12.0
30.5 .100
5.41 12.0
36.6 .120
5.41 12.0
42.6 .140
5.41 12.0
48.6 .160
5.41 12.0
54.6 0.18
5.41 12.0
60.6 .200
5.41 12.0
66.5 .220
5.41 12.0
72.4 .240
5.41 12.0
78.3 .260
5.41 12.0
84.2 .280
5.41 12.0
90.1 .300

1
2

116.
57.5

0.16
.033

.086
.174

3

38.7

.049

.259

4

28.8

.066

.348

5

22.8

.083

.439

6

18.8

.101

.531

7

15.9

.120

.631

8

13.9

.137

.721

9

12.9

.148

.776

10

10.9

.174

.918

11

9.90

.192

1.01

12

8.91

.213

1.12

13

8.91

.213

1.12

14

7.92

.240

1.26

15

6.93

.274

1.44

16

6.93

.274

1.44

17

5.94

.320

1.69

18

5.94

.320

1.69

19

5.94

.320

1.69

20

4.94

.384

2.02

21

4.94

.384

2.02

22

4.94

.384

2.02

23

4.94

.384

2.02

24

3.95

.481

2.53

25

3.95

.481

2.53

26

3.95

.481

2.53

27

3.95

.481

2.53

28

3.95

.481

2.53

29

3.95

.481

2.53

30

2.96

.642

3.38

31

2.96

.642

3.38

-M Multiplex mode operation on Multiplexer Channel

.200
.200
1.09
.200
2.11
.200
3.13
.200
4.16
.200
5.18
.200
6.21
.200
7.23
.200
8.25
.200
9.28
.200
10.3
.200
11.3
.200
12.3
.200
13.4
.200
14.4
.200
15.4
.200
16.4
.200
17.5
.200
18.5
.200
19.5
.200
20.5
.200
21.6
.200
22.6
.200
23.6
.200
24.6
.200
25.7
.200
26.7
.200
27.7
.200
28.7
.200
29.8
.200
30.8

6.15
5.78
12.3
5.78
18.3
5.78
24.3
5.78
30.3
5.78
36.3
5.78
42.2
5.78
48.0
5.78
53.9
5.78
59.6
5.78
65.4
5.78
71.1
5.78
76.7
5.78
82.4
5.78
87.9
5.78
93.5
5.78
99.0
5.78
104 .
5.78
110.
5.78
115.
5.78
121.
5.78
126.
5.78
13I.
5.78
136.
5.78
141.
5.78
147.
5.78
152.
5.78
157.
5.78
162 .
5.78
167.
5.78
172 .

.020
6.01
.040
6.01
.060
6.01
.080
6.01
.100
6.01
.120
6.01
.140
6.01
.160
6.01
.180
6.01
.200
6.01
.220
6.01
.240
6.01
.260
6.01
.280
6.01
.300
6.01
.320
6.01
.340
6.01
.360
6.01
.380
6.01
.400
6.01
.420
6.01
.440
6.01
.460
6.01
.480
6.01
.500
6.01
.520
6.01
.540
6.01
.560
6.01
.580
6.01
.600
6.01
.620

---

Table 1. (continued)
Appendix

67

15

NOMINAL

LINE MAXIMUM

31

NR

LINE MAXIMUM

~

INPUT/OUTPUT DEVICE

KEY

Communication Equipment
2702 Transmission Ctl
IBM Term Ctl-I
75 bps
1M
( with autopolling)

DATA
RATE

CPU
INTF

WAIT
TIME

8.3cps

29.6

116.

.053

58.1

.106

38.4

.160

28.8

.214

23.0

.267

19.2

.321

16.3

377

.613

14.4

.428

.695

12.5

.493

.802

11.5

.535

.869

10.5

.583

.948

9.58

.642

1.04

8.62

.713

1.16

8.14

.755

1.23

7.66

.802

1.31

DEV

PREY

A
B

.086

.200
.482
.172 .200
.577
1.47
.261 .200
1.09
2.47
.347 .200
1.60
3.46
.434 .200
2.12
4.45
.521 .200
2.63
~.44

lKey:

1- May be overrun

Table 1. (continued)

68

.200
3.14
6.43
.200
3.66
7.43
.200
4.17
8.42
.200
4.68
9.41
.200
5.19
10.4
.200
5.71
11.4
.200
6.22
12.4
.200
6.73
13.4
.200
7.25
14.4

6.12
6.33
5.41
12.1
12.6
5.41
18.1
18.9
5.41
24.1
25.1
5.41
30.0
31.3
5.41
36.0
37.4
5.41
42.0
43.5
5.41
48.0
49.5
5.41
53.9
55.5
5.41
59.9
61.5
5.41
65.9
67.5
5.41
71.9
73.3
5.41
77.8
79.2
5.41
83.8
85.0
5.41
89.8
90.8

OF
LA

.452
1
.020
12.0
2
.371
.040
12.0
3
.371
.060
12.0
4
.371
.080
12.0
5
.371
.100
12.0
6
.371
.120
12.0
7
.371
.140
12.0
8
.371
.160
12.0
9
.371
.180
12.0 10
.371
.200
12.0 11
.371
.220
12.0 12
.371
.240
12.0 13
..371
.260
12.0 14
.371
.280
12.0 15
.371
.300
16

WAIT

DEV

PREY

TIME

A

.200
.994
.200
1.09
3.01
.200
2.11
5.03
.200
3.14
7.04
.200
4.16
9.06
.200
5.19
11.1
.200
6.21
13.1
.200
7.24
15.1
.200
8.26
17.1
.200
9.29
19.1
.200
10.3
21.2
.200
11.3
23.2
.200
12.4
25.2
.200
13.4
27.2
.200
14.4
29.2
.200
15.4
31.2
.200
16.5
33.3
.200
17.5
35.3
.200
18.5
37.3
.200
19.5
39.3

6.14
6.32
5.78
12.1
12.6
5.78
18.1
18.7
5.78
24.1
24.8
5.78
30.0
30.8
5.78
36.0
36.7
5.78
42.0
42.5
5.78
47.9
48.3
5.78
53.9
54.0
5.78
59.8
59.6
5.78
65.8
65.1
5.78
71.8
70.5
5.78
77.7
75.9
5.78
83.7
81.1
5.78
89.7
86.3
5.78
95.6
91.4
5.78
102.
96.5
5.78
108.
101.
5.78
114.
106.
5.78
120.

116.

.053

.086

57.5

.107

.174

38.7

.159

.259

28.8

.214

.348

22.8

.270

.439

18.8

.327

.531

15.9

.388

.631

13.9

.443

.721

12.9

.477

.776

10.9

.564

.918

9.90

.621

1.01

8.91

.690

1.12

8.91

.690

1.12

7.92

.777

1.26

6.93

.888

1.44

6.93

.888

1.44

17

5.94

1.04

1.68

18

5.94

1.04

1.68

19

5.94

1.04

1.68

20

4.94

1.24

2.02

-M Multiplex mode operation on Multiplexer Channel

111.

B

.204
.020
6.01
.186
.040
6.01
.186
.060
6.01
.186
.080
6.01
.186
.100
6.01
.186
.120
6.01
.186
.140
6.01
.186
.160
6.01
.186
.180
6.01
.186
.200
6.01
.186
.220
6.01
.186
.240
6.01
.186
.260
6.01
.186
.280
6.01
.186
.300
6.01
.186
.320
6.01
.186
.340
6.01
.186
.360
6.01
.186
.380
6.01
.186
.400

--

15

NOMINAL
INPUT/OUTPUT DEVICE

KEY

Communication Equipment
2702 Transmission Ctl
IBM Term Ctl-I
75 bps
1M
(with autopolling)

DATA

CPU

RATE

INTF

8.3cps

29.6

WAIT
TIME

DEV

PREY

31

NR

LINE MAXIMUM
A

B

LINE MAXIMUM

DEV

PREY

TIME

A

B

21

4.94

1.24

2.02

22

4.94

1.24

2.02

23

4.94

1.24

2.02

24

3.95

1.56

2.53

25

3.95

1.56

2.53

26

3.95

1.56

2.53

27

3.95

1.56

2.53

28

3.95

1.56

2.53

29

3.95

1.56

2.53

30

2.96

2.08

3.38

31

2.96

2.08

3.38

.200
40.6
41.3
.200
21.6
43.3
.200
22.6
45.3
.200
23.6
47.4
.200
24.7
49.4
.200
25.7
51.4
.200
26.7
53.4
.200
27.7
55.4
.200
28.8
57.4
.200
29.8
59.5
.200
30.8
61.5

5.78
125.
116.
5.78
131.
120.
5.78
137.
125.
5.78
143.
129.
5.78
149.
134 .
5.78
155.
138 .
5.78
IG1.
142.
5.78
167.
146.
5.78
173.
151.
5.78
179.
155.
5.78
185.
158.

6.01
.18G
.420
6.01
.18G
.440
6.01
.18n
.4 GO
6.OJ
.18H
.480
6.OJ
.186
.500
6.OJ
.186
.520
6.01
.186
.540
6.01
.186
.560
6.01
.186
.580
6.01
.186
.600
6.01
.186
.620

WAIT

----~-

Key;

1- May be overrun

-

OF
LA

-M Multiplex mode operation on Multiplexer Channel

-

----~------

---------_._"-

-

Table 1. (continued)

Appendix

69

------

15

NOMINAL
DATA
INPUT/OUTPUT DEVICE

KEY

RATE

Communication Equipment
2702 Transmission Ctl
IBM Term Ctl-I
135.5 bps
1M 14.8cps

PREV
B
A

CPU
INTF

WAIT

DEV

TIME

29'.6

66.7
33.1

0.28
.057

.150
.302

22.1

.Q86

.453

16.3

.117

.613

12.9

.147

.773

11.0

.172

.907

9.10

.209

1.10

8.14

.233

1.23

7.18

.264

1.39

6.22

.305

1.61

5.74

.331

1.74

5.26

.361

1.90

4.78

.397

2.09

4.30

.441

2.32

4.30

.441

2.32

.200
.200
.573
.200
1.09
.200
1.60
.200
2.11
.200
2.62
.200
3.13
.200
3.65
.200
4.16
.200
4.67
.200
5.18
.200
5.69
.200
6.21
.200
6.72
.200
7.23

31

NR

LINE MAXIMUM

6.15 .035
5.41 12.0
12.3 .070
5.41 12.0
18.3 .105
5.41 12.0
24.4 .140
5.41 12.0
30.4 .175
5.41 12.0
36.3 .210
5.41 12.0
42.3 .245
5.41 12.0
48.2 .280
5.41 12.0
54.0 .315
5.41 12.0
59.9 .350
5.41 12.0
65.7 .385
5.41 12.0
71.4 .420
5.41 12.0
77.1 .455
5.41 12.0
82.8 .490
5.41 12.0
88.5 .525

DEV

LINE MAXIMUM
PREV

OF

WAIT

LA

TIME

.200
.200
1.09
.200
2.11
.200
3.13
.200
4.16
.200
5.18
.200
6.21
.200
7.23
.200
8.25
.200
9.28
.200
10.3
.200
11.3
.200
12.3
.200
13.4
.200
14.4
.200
15.4
.200
16.4
.200
17.5
.200
18.5
.200
19'.5
.200
20.5
.200
21.6
.200
22.6
.200
23.6
.200
24.6
.200
25.7
.200
26.7
.200
27.7
.200
28.7
.200
29.8
.200
30.8

1
2

66.4
32.7

.029
.058

.150
.306

3

21.8

.087

.459

4

15.9

.120

.631

5

12.9

.148

.776

6

10.9

.174

.918

7

8.91

.213

1.12

8

7.92

.240

1.26

9

6.93

.274

1.44

10

5.9

.320

1.69

11

5.94

.320

1.69

12

4.94

.384

2.02

13

4.94

.384

2.02

14

3.95

.481

2.53

15

3.95

.481

2.53

16

3.95

.481

2.53

17

2.96

.642

3.38

18

2.96

.642

3.38

19

2.96

.642

3.38

20

2.96

.642

3.38

21

2.96

.642

3.38

22

2.96

.642

3.38

23

1.97

.965

5.08

24

1.97

.965

5.08

25

1.97

.965

5.08

26

1.97

.965

5.08

27

1.97

.965

5.08

28

1.97

.965

5.08

29

1.97

.965

5.08

30

1.97

.965

5.08

31

1.97

.965

5.08

A

6.15
5.78
12.2
5.78
18.2
5.78
24.2
5.78
30.0
5.78
35.8
5.78
41.5
5.78
47.2
5.78
52.8
5.78
58.3
5.78
63.7
5.78
69.0
5.78
74.3
5.78
79.5
5.78
84.7
5.78
89.8
5.78
94.8
5.78
99.7
5.78
105.
5.78
109.
5.78
114.
5.78
119.
5.78
123.
5.78
128 .
5.78
132 .
5.78
137.
5.78
141.
5.78
145 .
5.78
149.
5.78
153.
5.78
157.

-- - - - - --

lKey:

1- May be overrun

B

1--------- f- --- -

.035
6.01
.070
6.01
.105
6.01
.140
6.01
.175
6.01
.210
6.01
.245
6.01
.280
6.01
.315
6.01
.350
6.01
.385
6.01
.420
6.01
.455
6.01
.490
6.01
.525
6.01
.560
6.01
.595
6.01
.630
6.01
.665
6.01
.700
6.01
.735
6.01
.770
6.01
.805
6.01
.840
6.01
.875
6.01
.910
6.01
.945
6.01
.980
6.01
1.02
6.01
1.05
6.01
1.09
--

-M Multiplex mode operation on MutItiplexer Channel
------

Table 1. (continued)
Appendix

7L

15

NOMINAL
DATA
INPUT/OUTPUT DEVICE

KEY

RATE

Communication Equipment
2702 Transmission Ctl
IBM Term Ctl-I
1M 14.8cps
135.5 bps
( with autopolling)

CPU
INTF

WAIT
TIME

DEV

29.6

66.7

.092

33.1

.186

22.1

.279

16.3

.377

12.9

0475

11.0

.558

9.10

.676

8.14

.755

7.18

.856

6.22

.988

5.74

1.07

5.26

1.17

4.78

1.29

4.30

1.43

4.30

1.43

LINE MAXIMUM

.150

.200
0482
.302 .200
.577
1.47
0453 .200
1.09
2047
.613 .200
1.60
3046
.773 .200
2.12
4045
.907 .200
2.63
5044
1.10 .200
3.14
6043
1.23 .200
3.66
7043
1.39 .200
4.17
8042
1.61 .200
4.68
9041
1.74 .200
5.19
lOA
1.90 .200
5.71
11.4
2.09 .200
6.22
1204
2.32 .200
6.73
1304
2.32 .200
7.25
1404

-----

Key;

1- May be overrun

Table 1. (continued)

72

--

PREY
A
B

OF
LA

WAIT

DEV

LINE MAXIMUM
PREY

TIME

A

B

.200
.994
.200
1.09
3.01
.200
2.11
5.03
.200
3.14
7.04
.200
4.16
9.06
.200
5.19
11.1
.200
6.21
13.1
.200
7.24
15.1
.200
8.26
17.1
.200
9.29
19.1
.200
10.3
21.2
.200
11.3
23.2
.200
1204
25.2
.200
1304
27.2
.200
1404
29.2
.200
1504
31.2
.200
16.5
33.3
.200
17.5
35.3
.200
18.5
37.3
.200
19.5
39.3

6.14
6.31
5.78
12.1
12.5
5.78
18.1
18.5
5.78
24.1
2404
5.78
30.0
30.1
5.78
36.0
35.7
5.78
42.0
41.2
5.78
47.9
46.5
5.78
53.9
51.7
5.78
59.8
56.7
5.78
65.8
61.6
5.78
71.8
66.3
5.78
77.7
71.0
5.78
83.7
7504
5.78
89.7
79.8
5.78
95.6
83.9
5.78
102 .
88.0
5.78
108.
91.9
5.78
114.
95.7
5.78
120.
99.3

.204
.035
6.01
.186
.070
6.01
.186
.105
6.01
.186
.140
6.01
.186
.175
6.01
.186
.210
6.01
.186
.245
6.01
.186
.280
6.01
.186
.315
6.01
.186
.350
6.01
.186
.385
6.01
.186
0420
6.01
.186
0455
6.01
.186
0490
6.01
.186
.525
6.01
.186
.560
6.01
.186
.595
6.01
.186
.630
6.01
.186
.665
6.01
.186
.700

.093

.150

32.7

.188

.306

21.8

.282

0459

19.9

.388

.631

12.9

0477

.776

10.9

.564

.918

8.91

.690

1.12

7.92

.777

1.26

6.93

.888

1.44

5.94

1.04

1.68

5.94

1.04

1.68

4.94

1.24

2.02

4.94

1.24

2.02

3.95

1.56

2.53

3.95

1.56

2.53

3.95

1.56

2.53

17

2.96

2.08

3.38

18

2.96

2.08

3.38

19

2.96

2.08

3.38

20

2.96

2.08

3.38

--

-M Multiplex mode operation on Multiplexer Channel

-

6604

1
6.12 0452
6.32 .035
2
5041 12.0
12.1 .371
12.6 .070
3
5041 12.0
18.1 .371
18.8 .105
4
5041 12.0
24.1 .371
24.9 .140
5
5041 12.0
30.0 .371
30.9 .175
6
5041 12.0
36.0 .371
36.9 .210
7
5041 12.0
42.0 .371
42.8 .245
5041 12.0
8
48.0 .371
48.6 .280
9
5041 12.0
53.9 .371
5404 .315
5041 12.0 10
59.9 .371
60.1 .350
5041 12.0 11
65.9 .371
65.7 .385
5041 12.0 12
71.9 .371
71.3 0420
5041 12.0 13
77.8 .371
76.8 0455
5041 12.0 14
83.8 .371
82.2 0490
5041 12.0 15
89.8 .371
87.6 .525
16

-----

31

NR

15

NOMINAL

INPUT/OUTPUT DEVICE

KEY

DATA

CPU

WAIT

DEV

RATE

INTF

TIME

LINE MAXIMUM
PRE V

A

B
~-~---

Communication Equipment
2702 Transmission Ctl
IBM Term Ctl-I
135.5 bps
( with autopolling)

WAIT

LA

----

1-------

---

----

TIME

A

B

.200
20.6
41.3
.200
21.6
43.3
.200
22.6
45.3
.200
23.6
47.4
.200
24.7
49.4
.200
25.7
51.4
.200
26.7
53.4
.200
27.7
55.4
.200
28.8
57.4
.200
29.8
59.5
.200
30.8
61.5

5.78
125.
103.
5.78
131.
106 .
5.78
137.
109 .
5.78
143.
112.
5.78
149.
115.
5.78
155.
118.
5.78
161.
121.
5.78
167.
123.
5.78
173.
126.
5.78
179.
128.
5.78
185.
130.

6.01
.186
.73.5
6.01
.186
.770
6.01
.186
.80,5
6.01
.186
.840
6.01
.186
.87.5
6.01
.186
.910
6.01
.186
.945
6.01
.186
.980
6.01
.186
1.02
6.01
.186
1.05
6.01
.186
1.09

21

2.96

2. 08

3.38

22

2.96

2. 08

3.38

23

1.97

3. 13

5.08

24

1.97

3. 13

5.08

25

1.97

3. 13

5.08

26

1.97

3. 13

5.08

27

1.97

3. 13

5.08

28

1.97

3. 13

5.08

29

1.97

3. 13

5.08

30

1.97

3. 13

5.08

31

1.97

3. 13

5.08

'---------

1- May be overrun

LINE MAXIMUM

-,'--,--------D EV

OF

1----- -

Key:

31

NR

~

-M Multiplex mode operation on Multiplexer Channel
--_._--_.-

Table 1. (continued)

Appendix

13

-------~--

15

NOMINAL

INPUT/OUTPUT DEVICE

KEY

DATA
RATE

Communication Equipment
2702 Transmission Ctl
IBM Term Ctl-I
1M 66.6cps
600 bps

IBM Term Ctl-II
600 bps

1M 160.0cps'

CPU
INTF

WAIT
TIME

DEV

LINE MAXIMUM

NR

PREY
B
A

OF
LA

31 LINE

MAXIMUM
~

WAIT DEV

PREY

--,..-B
A
TIME

I

-_._--

I
(with autopolling)
29.6

29.6

~

.200 6.12
.482 6.26
1.39 .200 5.41
.577 12.1
1.47 12.2
2.09 .200 5.41
1.09 18.1
2.47 17.7
2.99 .200 5.41
1.60 24.1
3.46 23.0
3.49 .200 5.41
2.12 30.0
4.45 27.8
4.19 .200 5.41
2.63 36.0
5.44 32.4
5.25 .200 5.41
3.14 42.0
6.43 36.5
7.02 .200 5.41
3.66 48.0
7.43 40.4
7.02 .200 5.41
4.17 53.9
8.42 43.9
7.02 .200 5.41
4.68 59.9
9.41 47.0
10.6 .200 5.41
5.19 65.9
10.4 49.8
10.6 .200 5.41
5.71 71.9
11.4 52.3
10.6 .200 5.41
6.22 77.8
12.4 54.4
10.6 .200 5.41
6.73 83.8
13.4 56.2
10.6 .200 5.41
7.25 89.8
14.4 57.6

.452
.174
12 .()
.37 1
.34 8
12 .o
.37 1
.522
12. o
.37 ]
.696
12. o
.37 1
.87o
12 .o
.37 1
1.04
12 .o
.37 1
1.22
12 .o
.37 1
1.39
12.o
.37 1
1.57
12. o
.37 1
1.74
12. o
.37 1
1.9 1
12. o
.37 1
2.09
12.o
.37 1
2.26
12. o
.37 1
2.44
12. o
.37 1
2.6 1

.200 6.12
.482 6.26
.200 5.41
.577 12.1
1.47 12.2
.200 5.41
1.09 18.1
2.47 17.8
.200 5.41
1.60 24.1
3.46 23.1

.452
.16 6
12,()
.37 1
.332
12. o
.37 1
.498
12. o
.37 1
.664

.695

14.4

.132

.695

.200

6.14

.174

1

14.4

.428

7.18

.264

1.39

.200
.573

5.41
12.1

12.0
.348

2

7.18

.856

4.78

.397

2.09

.200
1.09

5.41
17.9

12.0
.522

3

4.78

1.29

3.34

.568

2.99

.200
1.60

5.41
23.5

12.0
.696

4

3.34

1.84

2.86

.663

3.49

.200
2.11

5.41
28.9

12.0
.870

5

2.86

2.15

2.38

.797

4.20

.200
2.62

5.41
34.2

12.0
1.04

6

2.38

2.58

1.90

.998

5.25

.200
3.13

5.41
39'.2

12.0
1.22

7

1.90

3.23

1.42

1.33

7.02

.200
3.65

5.41
44.1

12.0
1.39

8

1.42

4.32

1.42

1.33

7.02

.200
4.16

5.41
48.8

12.0
1.57

9

1.42

4.32

1.42

1.33

7.02

.200
4.67

5.41
53.4

12.0
1.74

10

1.42

4.32

.944

2.01

10.6

.200
5.18

5.41
57.7

12.0
1.91

11

.944

6.51

.944

3.01

10.6

.200
5.69

5.41
61.9

12.0
2.09

12

.944

6.51

.944

2.01

10.6

.200
6.21

5.41
65.9

12.0
2.26

13

.944

6.51

.944

2.01

10.6

.200
6.72

5.41
69.7

12.0
2.44

14

.944

6.51

.944

2.01

10.6

.200
7.23

5.41
73.4

12.0
2.61

15

.944

6.51

14.4

.132

.695

.200

6.14

.166

1

14.4

.428

.695

7.18

.264

1.39

.200
.573

5.41
12.1

12.0
.332

2

7.18

.856

1.39

4.78

.397

2.09

.200
1.09

5.41
17.9

12.0
.498

3

4.78

1.29

2.09

3.34

.568

2.99

.200
1.60

5.41
23.5

12.0
.664

4

3.34

1.84

2.99

Key;
1- May be overrun
-M Multiplex mode operation on Multiplexer Channel

I

Table 1. (continued)

Appendix

75

r------- -

--

"----- ,------------ - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

15

NOMINAL
INPUT/OUTPUT DEVICE

KEY

Communication Equipment
2702 Transmission Ctl
IBM Term Ctl-II
600 bps

DATA
RATE

CPU
INTF

WAIT
TIME

DEV

76

NR

PREY
A
B

OF
LA

31 LINE
WAIT

DEV

PREY

MAXIMUM
A

TIME

B

--

I
( with autopolling)
2.86

.663

3.49

.200
2.11

5.41
290.

12.0
.830

5

2.86

2.15

3.49

2.38

.797

4.20

.200
2.62

5.41
34.3

12.0
.996

6

2.38

2.58

4.19

1.90

.998

5.25

.200
3.13

5.41
39.4

12.0
1.16

7

1.90

3.23

5.25

1.42

1.33

7.02

.200
3.65

5.41
44.4

12.0
1.33

8

1.42

4.32

7.02

1.42

1.33

7.02

.200
4.16

5.41
49.1

12.0
1.49

9

1.42

4.32

7.02

1.42

1.33

7.02

.200
4.67

5.41
53.7

12.0
1.66

10

1.42

4.32

7.02

.944

2.01

10.6

.200
5.18

5.41
58.2

12.0
1.83

11

.944

6.51

10.6

.944

2.01

10.6

.200
5.69

5.41
62.5

12.0
1.99

12

.944

6.51

10.6

.944

2.01

10.6

.200
6.21

5.41
66.6

12.0
2.16

13

.944

6.51

10.6

.944

2.01

10.6

.200
6.72

5.41
70.5

12.0
2.32

14

.944

6.51

10.6

.944

2.01

10.6

.200
7.23

5.41
74.2

12.0
2.49

15

.944

6.51

10.6

Key:
1- May be overrun
-M Multiplex mode operation on Multiplexer Channel
Table 1. (continued)

LINE MAXIMUM

.200
2.12
4.45
.200
2.63
5.44
.200
3.14
6.43
.200
3.66
7.43
.200
4.17
8.42
.200
4.68
9.41
.200
5.19
10.4
.200
5.71
11.4
.200
6.22
12.4
.200
6.73
13.4
.200
7.25
14.4

5.41 12.0
30.0 .371
28.0 .830
5.41 12.0
36.0 .371
32.6 .996
5.41 12.0
42.0 .371
36.9 1.16
5.41 12.0
48.0 .371
40.9 1.33
5.41 12.0
53.9 .371
44.5 1.49
5.41 12.0
59.9 .371
47.8 1.66
5.41 12.0
65.9 .371
50.7 1.83
5.41 12.0
71.9 .371
53.4 1.99
5.41 12.0
77.8 .371
55.7 2.16
5.41 12.0
83.8 .371
57.7 2.32
5.41 12.0
89.8 .371
59.3 2.49

-------

15 LINE

NOMINAL
KEY

DATA
RATE

CPU
INTF

Communication Equipment
2702 Transmission Ctl
Telegraph Ctl-I
1M
45 bps

6.0cps

29.6

INPUT/OUTPUT DEVICE

Key:

1- May be overrun

WAIT DEV

159.
79.7

.012
.024

52.8

.036

39.8

.048

31.7

.060

26.4

.072

22.5

.084

19.7

.097

17.3

.110

15.8

.120

14.4

.132

12.9

.147

12.0

.159

11.2

.172

10.5

.180

PREV
A
B

.200
.200
.573
.189 .200
1.09
.251 .200
1.60
.316 .200
2.11
.379 .200
2.62
.444 .200
3.13
.509 .200
3.65
.579 .200
4.16
.632 .200
4.67
.695 .200
5.18
.773 .200
5.69
.834 .200
6.21
.907 .200
6.72
.948 .200
7.23
.063
.126

6.15
5.41
12.3
5.41
18.4
5.41
24.5
5.41
30.6
5.41
36.7
5.41
42.8
5.41
48.8
5.41
54.9
5.41
60.9
5.41
66.9
5.41
72.9
5.41
78.9
5.41
84.9
5.41
90.8

31

NR

MAXIMUM

.013
12.0
.026
12.0
.039
12.0
.052
12.0
.065
12.0
.078
12.0
.091
12.0
.104
12.0
.117
12.0
.130
12.0
.143
12.0
.156
12.0
.169
12.0
.182
12.0
.195

OF
LA
f--

DEV
WAIT

--""-----

e---

-

LINE MAXIMUM

-

PREV

B
A
TIME

.200
.200
1.09
.200
2.11
.200
3.13
.200
4.16
.200
5.18
.200
6.21
.200
7.23
.200
8.25
.200
9.28
.200
10.3
.200
11.3
.200
12.3
.200
13.4
.200
14.4
.200
15.4
.200
16.4
.200
17.5
.200
18.5
.200
19.5
.200
20.5
.200
21.6
.200
22.6
.200
23.6
.200
24.6
.200
25.7
.200
26.7
.200
27.7
.200
28.7
.200
29.8
.200
30.8

1
2

159.
79.3

.012
.024

.063
.126

3

52.6

.036

.190

4

39.7

.048

.252

5

31.7

.060

.315

6

25.8

.074

.388

7

21.8

.087

.459

8

19.8

.096

.504

9

16.8

.113

.594

10

15.9

.120

.631

11

13.9

.137

.721

12

12.9

.148

.776

13

11.9

.160

.841

14

10.9

.174

.918

15

9.90

.192

1.01

16

8.90

.192

1.01

17

8.91

.213

1.12

18

7.92

.240

1.26

19

7.92

.240

1.26

20

7.92

.240

1.26

21

6.93

.274

1.44

22

6.93

.274

1.44

23

5.94

.320

1.69

24

5.94

.320

1.69

25

5.94

.320

1.69

26

5.94

.320

1.69

27

4.94

.384

2.02

28

4.94

.384

2.02

29

4.94

.384

2.02

30

4.94

.384

2.02

31

4.94

.384

2.02

--

6.15
5.78
12.3
5.78
18.4
5.78
24.4
5.78
30.5
5.78
36.5
5.78
42.5
5.78
48.4
5.78
54.4
5.78
60.3
5.78
66.2
5.78
72.0
5.78
77.9
5.78
83.7
5.78
89.4
5.78
95.2
5.78
101.
5.78
107.
5.78
112 .
5.78
118.
5.78
124 .
5.78
129.
5.78
135 .
5.78
140.
5.78
146.
5.78
151.
5.78
157.
5.78
162.
5.78
168.
5.78
173.
5.78
178.

.013
6.01
.026
6.01
.039
6.01
.052
6.01
.065
6.01
.078
6.01
.091
6.01
.104
6.01
.117
6.01
.130
6.01
.143
6.01
.156
6.01
.169
6.01
.182
6.01
.195
6.01
.208
6.01
.221
6.01
.234
6.01
.247
6.01
.260
6.01
.273
6.01
.286
6.01
.299
6.01
.312
6.01
.325
6.01
.338
6.01
.351
6.01
.364
6.01
.377
6.01
.390
6.01

_.4oal

-M Multiplex mode operation on Multiplexer Channel

Table 1. (continued)
Appendix

77

-------- -

15 LINE

NOMINAL
DATA
RATE

CPU
INTF

WAIT
TIME

DEV

Communication Equipment
2702 Transmission Ctl
Telegraph Ctl-I
1M
57 bps

7.5cps

29.6

125.
62.4

.015
.030

.080
.160

4f.3

.046

.242

31.2

.061

.321

24.9

.076

.401

20.6

.092

.485

17.7

.107

.564

15.3

.124

.652

13.4

.142

.745

12.5

.152

.802

11.0

.172

.907

10.1

.189

.994

9.58

.198

1.04

8.62

.220

1.16

8.14

.233

1.23

Key:

1- May be overrun

~.---

PREY
B
A

KEY

INPUT/OUTPUT DEVICE

31 LINE

NR

MAXIMUM

.200 6.15
.200 5.41
.573 12.3
.200 5.41
1.09 18.4
.200 5.41
1.60 24.5
.200 5.41
2.11 30.6
.200 5.41
2.62 36.6
.200 5.41
3.13 42.7
.200 5.41
3.65 48.7
.200 5.41
4.16 54.8
.200 5.41
4.67 60.8
.200 5.41
5.18 66.7
.200 5.41
5.69 72.7
.200 5.41
6.21 78.7
.200 5.41
6.72 84.6
.200 5.41
7.23 90.5

.016
12.0
.032
12.0
.048
12.0
.064
12.0
.080
12.0
.096
12.0
.112
12.0
.128
12.0
.144
12.0
.160
12.0
.176
12.0
.192
12.0
.208
12.0
.224
12.0
.240

OF
LA

WAIT DEV

1
2

125.
62.5

.015
0.03

3

41.6

.046

4

30.7

.062

5

24.8

.077

6

20.8

.091

7

17.8

.107

8

14.9

.128

9

13.9

.137

10

11.9

.160

11

10.9

.174

12

9.90

.192

13

8.91

.213

14

8.91

.213

15

7.92

.240

16

6.93

.274

17

6.93

.274

18

6.93

.274

19

5.94

.320

20

5.94

.320

21

5.94

.320

22

4.94

.384

23

4.94

.384

24

4.94

.384

25

4.94

.384

26

3.95

.481

27

3.95

.481

28

3.95

.481

29

3.95

.481

30

3.95

.481

31

3.95

.481

PREY

MAXIMUM

_."------

B
TIME
A

.200
0.20
1.09
.240 .200
2.11
.325 .200
3.13
.403 .200
4.16
.480 .200
5.18
.561 .200
6.21
.673 .200
7.23
.721 .200
8.25
.841 .200
9.28
.918 .200
10.3
1.01 .200
11.3
1.12 .200
12.3
1.12 .200
13.4
1.26 .200
14.4
1.44 .200
15.4
1.44 .200
16.4
1.44 .200
17.5
1.69 .200
18.5
1.69 .200
19.5
1.69 .200
20.5
2.02 .200
21.6
2.02 .200
22.6
2.02 .200
23.6
2.02 .200
24.6
2.53 .200
25.7
2.53 .200
26.7
2.53 .200
27.7
2.53 .200
28.7
2.53 .200
29.8
2.53 .200
30.8
.080
0.16

--

~

6.15
5.78
12.3
5.78
18.3
5.78
24.4
5.78
30.4
5.78
36.4
5.78
42.4
5.78
48.3
5.78
54.2
5.78
60.0
5.78
65.8
5.78
71.6
5.78
77.4
5.78
83.1
5.78
88.8
5.78
94.5
5.78
100.
5.78
106.
5.78
111.
5.78
117 .
5.78
122.
5.78
128.
5.78
133.
5.78
139.
5.78
144.
5.78
149.
5.78
155.
5.78
160.
5.78
165.
5.78
170.
5.78
175.

.016
6.01
.032
6.01
.048
6.01
.064
6.01
.080
6.01
.096
6.01
.112
6.01
.128
6.01
.144
6.01
.160
6.01
.176
6.01
.192
6.01
.208
6.01
.224
6.01
.240
6.01
.256
6.01
.272
6.01
.288
6.01
.304
6.01
.320
6.01
.336
6.01
.352
6.01
.368
6.01
.384
6.01
.400
6.01
.416
6.01
.432
6.01
.448
6.01
.464
6.01
.480
6.01
.496

----- - ----

-M Multiplex mode operation on Multiplexer Channel

I

!

Table 1. (continued)
Appendix

79

15

NOMINAL

INPUT/OUTPUT DEVICE

KEY

DATA
RATE

Communication Equipment
2702 Transmission Ctl
Telegraph Ctl-I
1M 1O.0cps
75 bps

CPU
INTF

29.6

WAIT
TIME

DEV

PRE V
A
B

_ . - ------.-

96.0
48.0

.020
.040

;104
.208

31.7

.060

.316

24.0

.079

.417

19.2

.099-

.521

15.8

.120

.632

13.4

.142

.745

12.0

.159

.834

10.5

.180

.948

9.58

.198

1.04

8.62

.220

1.16

7.66

.248

1.31

7.13

.264

1.39

6.70

.283

1.49

6.22

.305

1.61

.200
.200
.573
.200
1.09
.200
1.60
.200
2.11
.200
2.62
.200
3.13
.200
3.65
.200
4.16
.200
4.67
.200
5.18
.200
5.69
.200
6.21
.200
6.72
.200
7.23

31

NR

LINE MAXIMUM

6.15
5.41
12.3
5.41
18.4
5.41
24.5
5.41
30.5
5.41
36.6
5.41
42.6
5.41
48.6
5.41
54.6
5.41
60.5
5.41
66.5
5.41
72.4
5.41
78.3
5.41
84.1
5.41
90.0

.021
12.0
.042
12.0
.063
12.0
.084
12.0
.105
12.0
.126
12.0
.147
12.0
.168
12.0
.189
12.0
.210
12.0
.231
12.0
.252
12.0
.273
12.0
.294
12.0
.315

OF
LA

DE V
WAIT

-.---

-~--

...

--

1
2

95.2
47.6

3

31.7

4

23.8

5

18.8

6

15.9

7

12.9

8

11.9

9

9.90

10

8.91

11

7.92

12

7.92

13

6.93

14

5.94

15

5.94

16

5.94

17

4.94

18

4.94

19

4.94

20

3.95

21

3.95

22

3.95

23

3.95

24

3.95

25

2.96

26

2.96

27

2.96

28

2.96

29

2.96

30

2.96

31

2.96

I

'-----

Key:

1- May be overrun

L-.

LINE MAXIMUM

-,--

PRE V
LOA D

--"-"._-

_. __.

-

TIME

A

B

----

.02o .105
.04o .21 0

.200 6.15 .02]
.200 5.78 6.0]
1.09 12.3 .042
.06o .31 5 .200 5.78 6.OJ
2.11 18.3 .060
.08o .42 0 .200 5.78 6.m
3.13 24.3 .084
.10 1 .53 1 .200 5.78 6.01
4.16 30.3 .1Of;
.12o .63 1 .200 5.78 6.0]
5.18 36.2 .126
.148 .77 6 .200 5.78 6.OJ
6.21 42.1 .147
.16o .84 1 .200 5.78 6.01
7.23 48.0 .168
.192 1.0 1 .200 5.78 6.01
8.25 53.8 .189
.21 3 1.1 2 .200 5.78 6.01
9.28 59.6 .21.0
.24o 1.26 .200 5.78 6.0]
10.3 65.3 .231
.24o 1.2 6 .200 5.78 6.01
11.3 70.9 .252
.274 1.44 .200 5.78 6.01
12.3 76.6 .273
.32o 1.69 .200 5.78 6.01
13.4 82.2 .294
.32( 1.69 .200 5.78 6.01
14.4 87.8 .315
.32o 1.69 .200 5.78 6.01
15.4 93.2 .336
.38 4 2.02 .200 5.78 6.01
16.4 98.7 .357
.384 2.02 .200 5.78 6.01
17.5 104. .378
.38 4 2.02 .200 5.78 6.01
18.5 109 . .399
.481 2.53 .200 5.78 6.01
19.5 115 . .420
.481 2.53 .200 5.78 6.01
20.5 120. .441
.481 2.53 .200 5.78 6.01
21.6 125. .462
.481 2.53 .200 5.78 6.01
22.6 131. .483
.481 2.53 .200 5.78 6.01
23.6 136. .504
.642 3.38 .200 5.78 6.01
24.6 141. .525
.642 3.38 .200 5.78 6.01
25.7 146. .546
.642 3.38 .200 5.78 6.01
26.7 151. .567
.642 3.38 .200 5.78 6.01
27.7 156. .588
.642 3.38 .200 5.78 6.01
28.7 161. .609
.642 3.38 .200 5.78 6.01
29.8 166. .630
.642 3.38 .200 5.78 6.01
30.8 171. .651

---

--

.

-M Multiplex mode operation on Multiplexer Channel
-- -------- -

Table 1. (continued)
Appendix

I'i

j

-

15

NOMINAL

LINE MAXIMUM

NR

PREV
B
A

OF
LA

DATA
RATE

CPU
INTF

WAIT
TIME

DEV

Communication Equipment
2702 Transmission Ctl
Telegraph Ctl-II
1M 10.0cps
110 bps

29.6

96.9
48.5

.020
.039

.103
.206

32.1

.059

.311

24.0

.079

.417

19.2

.099

.521

15.8

.120

.632

13.4

.142

.745

12.0

.159

.834

10.5

.180

.948

9.58

.198

1.04

8.62

.220

1.16

7.66

.248

1.31

7.18

.264

1.39

6.70

.283

1.49

6.22

.305

1.61

INPUT/OUTPUT DEVICE

Key:

KEY

1- May be overrun

.200
.200
.573
.200
1.09
.200
1.60
.200
2.11
.200
2.62
.200
3.13
.200
3.65
.200
4.16
.200
4.67
.200
5.18
.200
5.69
.200
6.21
.200
6.72
.200
7.23

6.15
5.41
12.3
5.41
18.4
5.41
24.5
5.41
30.5
5.41
36.6
5.41
42.6
5.41
48.6
5.41
54.6
5.41
60.5
5.41
66.5
5.41
72.4
5.41
78.3
5.41
84.1
5.41
90.0

.021
12.0
.042
12.0
.063
12.0
.084
12.0
.105
12.0
.126
12.0
.147
12.0
.168
12.0
.189
12.0
.210
12.0
.231
12.0
.252
12.0
.273
12.0
.294
12.0
.315

31 LINE
WAIT DEV

PREV

MAXIMUM

-

B
A
TIME
-I-"

1
2

97.2
48.6

.020
.039

.103
.206

3

31.7

.060

.315

4

23.8

.080

.420

5

18.8

.101

.531

6

15.9

.120

.631

7

13.9

.137

.721

8

11.9

.160

.841

9

9.90

.192

1.01

10

8.91

.213

1.12

11

7.92

.240

1.26

12

7.92

.240

1.26

13

6.93

.274

1.44

14

6.93

.274

1.44

15

5.94

.320

1.69

16

5.94

.320

1.69

17

4.94

.384

2.02

18

4.94

.384

2.02

19

4.94

.384

2.02

20

3.95

.481

2.53

21

3.95

.481

2.53

22

3.95

.481

2.53

23

3.95

.481

2.53

24

3.95

.481

2.53

25

2.96

.642

3.38

26

2.96

.642

3.38

27

2.96

.642

3.38

28

2.96

.642

3.38

29

2.96

.642

3.38

30

2.96

.642

3.38

31

2.96

.642

3.38

.200
.200
1.09
.200
2.11
.200
3.13
.200
4.16
.200
5.18
.200
6.21
.200
7.23
.200
8.25
.200
9.28
.200
10.3
.200
11.3
.200
12.3
.200
13.4
.200
14.4
.200
15.4
.200
16.4
.200
17.5
.200
18.5
.200
19.5
.200
20.5
.200
21.6
.200
22.6
.200
23.6
.200
24.6
.200
25.7
.200
26.7
.200
27.7
.200
28.7
.200
29.8
.200
30.8

6.15
5.78
12.3
5.78
18.3
5.78
24.3
5.78
30.3
5.78
36.2
5.78
42.1
5.78
48.0
5.78
53.8
5.78
59.6
5.78
65.3
5.78
70.9
5.78
76.6
5.78
82.2
5.78
87.7
5.78
93.2
5.78
98.7
5.78
104.
5.78
109.
5.78
115.
5.78
120.
5.78
125.
5.78
131.
5.78
136.
5.78
141.
5.78
146.
5.78
151.
5.78
156 .
5.78
161.
5.78
166.
5.78
171.

-

.021
6.01
.042
6.01
.063
6.01
.084
6.01
.105
6.01
.126
6.01
.147
6.01
.168
6.01
.189
6.01
.210
6.01
.231
6.01
.252
6.01
.273
6.01
.294
6.01
.315
6.01
.336
6.01
.357
6.01
.378
6.01
.399
6.01
.420
6.01
.441
6.01
.462
6.01
.483
6.01
.504
6.01
.525
6.01
.546
6.01
.567
6.01
.588
6.01
.609
6.01
.630
6.01
.651

'---

-M Multiplex mode operation on Multiplexer Channel

Table 1. (continued)
Appendix

83

-

15

NOMINAL

LINE MAXIMUM

NR

PREY
A
B

OF
LA

KEY

DATA
RATE

CPU
INTF

WAIT

INPUT/OUTPUT DEVICE

TIME

DEV

50 bps

1M

6.6cps

29.6

144.
72.0

.013
.026

.069
.139

48.0

.040

.208

36.0

.053

.278

28.8

.066

.347

24.0

.079

.417

20.1

.094

.496

17.7

.107

.564

15.8

.120

.632

14.4

.132

.695

12.9

.147

.773

12.0

.159

.834

11.0

.172

.907

10.1

.189

.994

9.58

.198

1.04

.200
.200
.573
.200
1.09
.200
1.60
.200
2.11
.200
2.62
.200
3.13
.200
3.65
.200
4.16
.200
4.67
.200
5.18
.200
5.69
.200
6.21
.200
6.72
.200
7.23

6.15
5.41
12.3
5.41
18.4
5.41
24.5
5.41
30.6
5.41
36.7
5.41
42.7
5.41
48.8
5.41
54.8
5.41
60.8
5.41
66.9
5.41
72.8
5.41
78.8
5.41
84.8
5.41
90.7

.014
12.0
.028
12.0
.042
12.0
.056
12.0
.070
12.0
.084
12.0
.098
12.0
.112
12.0
.126
12.0
.140
12.0
.154
12.0
.168
12.0
.182
12.0
.196
12.0
.210

31
WAIT DEV

LINE MAXIMUM
PREY

1
2

144.
71.4

.013
.027

.070
.140

3

47.6

.040

.210

4

35.7

.053

.280

5

28.8

.066

.348

6

23.8

.080

.420

7

19.8

.096

.504

8

17.8

.107

.561

9

15.9

.120

.631

10

13.9

.137

.721

11

12.9

.148

.776

12

11.9

.160

.841

13

10.9

.174

.918

14

9.90

.192

1.01

15

8.91

.213

1.12

16

8.91

.213

1.12

17

7.92

.240

1.26

18

7.92

.240

1.26

19

6.93

.274

1.44

20

6.93

.274

1.44

21

5.94

.320

1.69

22

5.94

.320

1.69

23

5.94

.320

1.69

24

5.94

.320

1.69

25

4.94

.384

2.02

26

4.94

.384

2.02

27

4.94

.384

2.02

28

4.94

.384

2.02

29

4.94

.384

2.02

30

3.95

.481

2.53

31

3.95

.481

2.53

TIME

B

A

~.-I-

.200
.200
1.09
.200
2.11
.200
3.13
.200
4.16
.200
5.18
.200
6.20
.200
7.23
.200
8.25
.200
9.28
.200
10.3
.200
11.3
.200
12.3
.200
13.4
.200
14.4
.200
15.4
.200
16.4
.200
17.5
.200
18.5
.200
19.5
.200
20.5
.200
21.6
.200
22.6
.200
23.6
.200
24.6
.200
25.7
.200
26.7
.200
27.7
.200
28.7
.200
29.8
.200
30.8

-~

6.15
5.78
12.3
5.78
18.4
5.78
24.4
5.78
30.5
5.78
36.5
5.78
42.4
5.78
48.4
5.78
54.3
5.78
60.2
5.78
66.1
5.78
71.9
5.78
77.7
5.78
83.5
5.78
89.2
5.78
94.9
5.78
101.
5.78
106.
5.78
112 .
5.78
118.
5.78
123 .
5.78
129.
5.78
134 .
5.78
140 .
5.78
145.
5.78
151.
5.78
156.
5.78
161.
5.78
167.
5.78
172.
5.78
177.
~ -~

.014
6.01
.028
6.01
.042
6.01
.056
6.01
.070
6.01
.084
6.01
.098
6.01
.112
6.01
.126
6.01
.140
6.01
.154
6.01
.168
6.01
.182
6.01
.196
6.01
.210
6.01
.224
6.01
.238
6.01
.252
6.01
.266
6.01
.280
6.01
.294
6.01
.308
6.01
.322
6.01
.336
6.01
.350
6.01
.364
6.01
.378
6.01
.392
6.01
.406
6.01
.420
6.01
.434

--

Key:
1- May be overrun
-M Multiplex mode operation on Multiplexer Channel

J

Table 1. (continued)
Appendix

85

31

LINE

LINE

15

TERMINAL

IBM Type I
75 bps
135.5 bps
600 bps

242
139
30

IBM Type II
600 bps

30

Telegraph I
45 bps
57 bps
75 bps

332
260
200

160
126
96

Telegraph Type II
110 bps

202

98

WTC Telegraph
50 bps
75 bps

300
200

145
96

15

Segment 1

NMax
15

TERMINAL CONTROL

LINE MAX

1.9
10.0

117
67

31

LINE MAX

1.9
10.0

31

LINE MAX

LINE MAX
-~

b

CONTROL

A

TIME

IBM Type I
0.02 .200
75 bps
135.5 bps 0.035 .200
0.174 .200
600 bps
IBM Type II
600 bps
0.166 .200
Telegraph Tn e I
0.013 .200
45 bps
0.016 .200
57 bps
0.021 .200
75 bps
Telegraph Type II
110 bps
1 0 .021 .200
50 bps
10.0141.200
75 bps
0.021 .200

B

..

TIME

B

A

t
6.149 0.02 .200 6.149 0.02
6.148 0.035 .200 6.149 0.03
6.139 0.174 .200 6.139 0.17
6.140 0.166 .200 6.140 0.16
6.149 0.013 .200 6.149 0.01 3
6.149 0.016 .200 6.149 0.01 6
6.149 0.021 .200 6.149 0.02 1
6.149 0.021 .200 6.149 0.02 1
6.149 0.014 .200 6.149 0.01 4
6.149 0.021 .200 6.149 0.02 1
---

"--

--

Segment 2

Table 2. IBM System/360 Model 40 Evaluation Factors for
2702 Special Analysis

15

31 LINE MAX

LINE MAX

TIME

_A_

_B_

TIME

_A_

_B_

.200

5.411

12.01

.200

5.781

6.005

Segment 3
15

LINES

2
3
4
5
6
7
8
9
10
11
12
13
14
15

31

LINE MAX

NUMBER OF

LINE MAX
,------

NU MBEROF

NUMBER OF
TIME

LINES

0.574
1.086
1.598
2.110
2.622
3.134
3.646
4.158
4.670
5.182
5.694
6.206
6.718
7.230

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

TIME

1.086
2.110
3.134
4.158
5.182
6.206
7.230
8.254
9.278
10.302
11.326
12.350
13.374
14.398
15.422

r--

--'----

LINES

TIME

17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

16.446
17.470
18.494
19.518
20.542
21.560
22.590
23.614
24.638
25.662
26.686
,27.710
28.734
29.758
30.782

~----

- --

Table 3. IBM System/360 Model 40 Priority Load Factors for
2702

Appendix

87

Data Service
Command Chaining
if status modifier plus
Data Chaining
if TIC
Program Controlled
Interruption
Channel End Interruption
Device End or Control
Unit End Interruption

SELECTOR

MULTIPLEXER

CHANNEL

CHANNEL

1.25 /Ls/Byte
17.5 /Ls/CCW
.625 /Ls/CCW

CH" AINING SPECIFICATIONS

see Table 1 'It 'it
68.1+ Ul/LS/CC\i\T'It
1.25 /Ls/CCW

1.25 /Ls/CCW
1.25 /Ls/CCW
5.625 /Ls/TIC
7.5/Ls/TIC
10.625 /Ls/CCW 20.0 /Ls/CCW
5.0/Ls/TIC
12 ..5 /Ls/TIC
40.63 /Ls/PCI
40.63 /Ls/eaeh

61.88 /Ls/PCI
GO.63/Ls/each

NoDC

DC

60

50

One channel in operation

---------

Two channels in operation
Selector Channel 1
Selector Channel 2

50

32

41

32

--

DC & TIC
..

-

40
-

21.6
21.6

----1 __. _ _ _

-

Table 5. IBM System/360 Model 40 Selector Channel Load
qmits - with Multiplexer Channel Operating in
Byte-Multiplex Mode

45.0+Ul
56.88+ Ul
/Ls/each'it
/Ls/eaeh'lt
'ltU 1 = Select out delay + device delay
'It'itThe CPU Intf column in Table 1 lists interference caused
by multiplex mode devices in microseconds per byte of data
transferred. Burst mode operation of the multiplexer channel
causes 100 percent CPU interference.

-.--

COMBINED
SELECTOR CHANNEL
(SEL

1

& SEL

2)

MULTIPLEXER

NO DC

Table 4. IBM System/360 Model 40 CPU Interference Factors

-.

-._--

--~----

f---------. -._--

Selectur Channels
Not Operating

0

25

Selector Channels
Operating

41

16
--"-

-

Table 6. IBM System/360 Model 40 Channel Loa ~ Limits
with Multiplexer Channel Operating in Burst Mode

Appendix

H9

MULTlPLEXEIl CHANNEL WORKSHEET
DATE _ _ _ _ _ _ _ _ _ _ __

SYSTEM IDENTIFICATION _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

--..-

I

POSITION ON MULTIPLEXER CHANNEL

I
I

2

I

3

I
I

-t-------------

5

4

DEVICE

8

I

--WAITING TIME
TIME

7

6

--

I
A

B

A

B

A

B

A

B

B

A

i

A

B

!

B

A

B

A

B

A

--

SELECTOR
CHANNEL I

I

I
DEVICE

I

SELECTOR
CHANNEL 2
DEVICE

I

--- -

i

I

I

I

I
I

I

I
I

A SUM
I

I

QUOTIENT

2

...

Z
Z
~

3

DEVICE
PREVIOUS

QUOTIENT

SUM

DEVICE
PREVIOUS

V

!
~

4

Z

0

Z

0

A SUM

5

t:

2
6

7

SUM

I
A SUM
QUOTIENT
DEV:C:E

A SUM

PREVIOUS

QUOTIENT

SUM

DEVICE

I

1--+

A SUM

PREVIOUS

QUOTIENT

SUM

DEVICE

I

I

A SUM

PREVIOUS

QUOTIENT

SUM

DEVICE

.-

--

I

I

I

i
I

j

--

--

A SUM

I

i
I

I

PREVIOUS
SUM

QUOTIENT

I

DEVICE

I
I

I

A

SUM

SU~'

---

PREVIOUS

QUOTIENT I
DEVICE

I

I
• Figure 8. Example of Blank Worksheet

--

SUM

!

~---.---

-,

MULTIPLEXER CHANNEL WORKSHEET
SYSTEM IDENTIFICATION

_-'J..""--_________________

I

POSITION ON MULTIPLEXER CHANNEL

1

WAITING TIME
TIME
SELECTOR
CHANNEL 1

B

A

2

'I

6
7

DEVICE

1

DATE

4

3

I

I

5

6

7

-----t-~~-----------~------

-

!

a
B

A

i

l

8

I

<0

8

B

A

A

B

A.

I

B

A

B

i

i

A

B

A

B

B

A

,

3"

2

~

DEVICE

9,

.9,
~

SELECTOR
CHANNEL 2

2-

i
I
I

92-

I

52-

!

i

I

I

I

T

~r----

DEVICE

10?.

10"2-

98

lOs

10 8

I

I

..... 3

la,

10,

98

i

i

!

I

1

I
I

I

!

I

i
1

2

Z
Z
~

u

3

4

5

6

7

l~

13,

----

~1

8

\

\

DEVICE

7

132-

PREVIOUS

7

QUOTIENT

14?

DEVICE
PREVIOUS

15,

SUM

\

\1\

14,

"\

1\
\

II,

QUOTIENT

SUM

1 Ih
1

A SUM

1'2. ,

12.,

8

13>3,

A SUM

B

QUOTIENT

14~

152:

DEVICE

'8

PREVIOUS

8

SUM

153

\

12.z.
13 4
QUOTIENT
DEVICE
PREVIOUS

\

SUM

\

\
8, (Nu..mbe.~ Y"eS;e'C"

i

I

A SUM

t-o 'P'<"Oc...e.du..'C'e, c;"l.'e,p'b.

1='1r.:.-I-, do tI",Y<\be:c-e.d <::.+eps \o..c,ki""~ "E:.",~~'('\~t~.
['(ext, do ':.~eps s",'oo;.c...'I",fTe.cll, ,""an '2, ek.)

122..

12."

12"

12c.

12."

12c.

12(.,

12~

12~

A SUM

\448
8,

\2.3

12 3

1.30-

A SUM

QUOTIENT

\46

DEVICE

\5Lt
I

PREV,OUS

I

SUM

i

8

\3",

8

I QUOTIENT

\15 5

12 4

1'2'-t

DEVICE

PR~~~~US
SUM

A SUM

''+<0
I

1'2.5

125

I

!

8

137

A SUM

;

i

8

QUOTIENT

/L'h

I

DEVICE

8

PREVIOUS

8

i

15ro

SUM

• Figure 9. Sequence for Worksheet Entries

117

i

15 7

I

12.c:.

12."
13 8
QUOTIENT

I

12",
lL(O
A SUM

lita

DEVICE

8

SUM

158

MULTIPLEXER CHANNEL WORKSHEET
SYSTEM IDENTIFICATION

--.JM
. . . . . -=o:;..d.=..Q.=.;.1_4L..o=-____________

POSITION ON MULTIPLEXER CHANNEL

1

TIME

SELECTOR

CHA5f~L 2
~'+""
(.,0

DEViCE

...

.800

"2.~

ro:=-

.200

3.15

• LfZ.o

-

:too

7·0-5

7.'5'5"

2.80

Z·~

1"?·4

5':~C

QUOTIENT

~

u

!~

.zoo
I 'G.'?

zz

.2,00
3

8·'5'<0

-

'-\-·7""1

t.l-n

'l.OO

1.\ loto

750

L-.~

-

O~8

PREVIOUS

Ic)O

Z,.::''B

4

2Cl:~

A

[G..70

\3.4

5:~O

\3·4

£30

13.4-

5-==.a

!b.a

A SUM

QUOTIENT

1.48

Q~B

-

o·~B

417

-

433.2.

A SUM

QUOTIENT

6.19

DEVICE

.o~Lf-

-

DEVICE

O·4=.

I~:Z...

A SUM

PREVIOUS

O.~O

QUOTIENT

0.88

SUM

35,91

DEVICE

"G'5.9,

~

SUM

O.6Lt
61.3

SUM

40.30

A SUM
QUOTiENT
DEVICE

A SUM

PREVIOUS

QUOTIENT

SUM

DEVICE

I
A SUM

PREVIOUS

QUOTIENT

SUM

DEVICE

A SUM

PREVIOUS

L

8

A SUM

PREVIOUS

t:

7

I

-

PREVIOUS

5

B

6
!

IB.s
B

~:3

5

1443

\1.0
B

4

-

DEVICE

:I
Z
0

~

A

'21.~

1

2

B

3.Lto

Z311
DEVICE

A

.2.(X)

3

1442.-N a

. Boc::::.

WAITING TIME

SELECTOR
CHANNEL 1

2

f4.4-'2..-N

DEVICE

DATE _ _ _ _ _ _ _ _ _ _ __

SUM

QUOTIENT

I

DEVICE
SUM

I

MULTIPLEXER CHANNEL WORKSHEET
;YSTEM IDENTIFICATION

_--,-M~o~d~e.~1_4~o=-___________

DATE _ _ _ _ _ _ _ _ _ __

~j=PO=S=:=: =:=EO~N= MU=l=TlP=l=EX=ER= CH=A=N=NE=l= = = =;:~s:702.:_:'O=-3:0:1='s= ~_-_+,-:_Z;~ ~" ,: ; \lu.:o:c. . ~ I-oyc-~ -;!-.-=~ ~ ~-c-I;_-_-. ': '2:~54-~ O~ ~ -~ ~ :~"2.~-'S~-4~o-:=- ~p~4~ _~_~ _~+;- Ilf<:i-~-~-J~-- --- ----,~~-~=r:; 1------------14-4--~-----+!--I-O-5-8-2----j1
.944

WAITING TIME

I

1

1.97

I

1'1--0

<0.'0

\5.,'

15.7

18."

I

70·0

I

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f---::-:::-:::::-::::--t-_TI_M_E- t__

CS~;~C~~lRl

.'200

2.311

_-+___-+I _ A _ - + -_ _B_-l-_ _
A_--L_ _
B_---lI_ _A_---+I_ _B_-l-_ _
A ~----t
'2.1.~ I
I '

A

B

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8

0.

I

8

A:

8

A

I

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1
I

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7£t.z-

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QUOTIENT I

LJ-.O

5.72,

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3::>·8

157.

1.75

175.

"0·0

170.

PREVIOUS

I. o~

1

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10 • 10

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:

I

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T

I

~.b\

7'1.2.

15.78

,lo

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i

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SUM

t

j

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Z 50 i

0.0,,+

I

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Ic.o

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1~8
2.00

I

I

i

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I:

II

09'+

i

I

I

I co.=.
G.~ Co:~ "2.~ C0.~ c.'e:O c..0 0 1 2·80 I 20.3 I 2.80 I C.o.~ '-z..~ . W.3
--+----+----t-'------l-------"-----+----+----+----i-----I---I-------:
:
:
,

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CS~;~C~~R

A

1---+-------+1---1

IBM 2702 WORKSHEET
DATE

SYSTEM IDENTIFICATION

REVOLUTION

i

NUMBER OF LlNES=

=I

i

=2

i

=3

i

=4

i

=5

i

=6

i

=7

i=8

I

tl

LINE NUMBER=

=

1

t2 =

t2

=

t2

=

t2

=

t2

=

t2

=

t2

=

t2 =

SUBTRACT: K =
nmax=

AI

BI

A2

B2

A2

B2

A2

B2

SELECTOR CHANNEL I

B2

A2

I

A2

B2

B2

A2

A2

B2

A2

B2

I
:

SELECTOR CHANNEL 2

II

I

DEVICE I

I
DEVICE 2

j

I

i

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I

!

DEVICE 3
DEVICE 4
DEVICE 5

DEVICE 6
DEVICE 7
DEVICE 8
DEVICE 9
DEVICE JO
SUM A's AND B's
MULTIPLY: ti X SUM Bi

><

><

><

><

A REMAINDER
B REMAINDER

X

><

2<

1

><

i

I

!

I

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: 15 Line 2702
LIMIT

I 31 Une 2702

46.4

94.4

142.4

190.4

I

238.4

286.4

334.4

382.4

494.4

593.6

692.8

792.0

!

97.6

MAXIMUM NUMBER OF REVOLUTIONS TO COMPLETE SERVICE: n + (i - I) k

Figure 12. Example of Blank 2702 Worksheet

196.8

296.0

395.2

IBM 2702 WORKSHEET
DATE _ _ _ _ _ _ _ _ __

SYSTEM IDENTIFICATION _ _ _ _ __

1,2..lf

NUMBER 0" LlNES=
LINE NUMBER=
SUBTRACT: K=

_'2~.G=6==--_

_--"3~!,-,2!,,,,5-,-__

+ _____--=~---___:__---+
i=1

I-_R_EV_O_L_UT_IO_N
__

i =2

11

~"C..G::>

'I =

'2=

®

~

'2 =

9

i_"_3_ _ _ !__ _ _
i _"_4_ _

_ _ _

J

'2

~0>V6.~~~)

~_ _ _

i__5_____

'2"

'2

~-----+------~-L-------~~~-~~~~=------------I, '-8
1)"2.8
19 ~~

<@>

I-n_ma_x_=_-~~~~~~_4~_-_~-_~-_-_-_+_-A~I~~i--B-I--+-,,-~-.
A2

B2_~--A-2-~

B2
A2
_ _ _ _ _-+__

__
B2_ _ _ _
A_2_______
B2

_

~
-

_ _ _-_-i_"_6_

--------1

i=7

i

'2

I

-------':----------

i=8

1

'2 --

'2 =

---1---------~------~

I

I

~ -~~~~=~- :~_~~~~~~-~~-~~~~~--A-2-~~--------B-2--~

I-S_EL_EC_T_O_R_C_H,_-._~N_E_L_I _f-L_+-_4-~I-_4-_+-~-+_~--,_-~-+_~-~---~---------- --------------~----~I----L------~I------~I---~--~
~

_

-~J-=t=i -J~J~~~:=

SELECTOR CHANNEL 2
!

I

!

T

1

DEVICE I

,

I

DEVICE 2

I

i

T

DEVICE 3
DEVICE 4

<0

8,"t.l

i

10

8,"2.7

I

10'

10

10'
-,-

I

!
I

i
!

DEVICE 5
I

I

DEVICE 6

I

DEVICE 7

----

B REMAINDER

5

---

I-----------------------I----------------l--- -------------------------------

+-____5~_____________________________-----------'---------

f--:P.:.:.RE::..:V..:.:10::..:U=-=-S..::L..:.:OA-.::D=-_ _ _ _ _ _ _ _ _ _ _ _

\(~.fc...

17

1----------------=-=--------\------,,,------------------------------15 Une 2702
LIMIT

~46.4
---@~

@

~

97.6

I

94.4

142.4

.

190.4

I

r--

238.4

~-----------------~------~-------;---------------

I

196.8

296.0

395.2'

1-------------=---------+---------------+---------------------------, -------------

494.4

----

-l-

_____ - - , - - - -_ _ _ _ __ L c - -_ _ _ _ __

I
I

-- -t-------------'--------286.4
593.6

382.4
334.4
---f - - - - - - - - - - - - - - - + - - - - - - - - 692.8

792.0

j

--1
I

MAXIMUM NUMBER OF REVOLUTIONS TO COMPLETE SERVICE, n

C

(i - I) k =

'2.'2.~OPSU-T\ON ,""",,'T''''~\ c>~y)

Figure 13. Sequence for 2702 Worksheet Entries

START

Yes

Overrun

DEVICE

2702
15 line 31 Line

w
x
y

z

.464
.976
99.2
48.0
.480
.048

.992
.048

Yes

No

Operation Satisfactory

Figure 14. Flowchart for 2702 Special Analysis Worksheet Procedure

Appendix

103

MULTIPLEXER CHANNEL WORKSHEET
SYSTEM IDENTIFICATION

_t<\_o=-=d---'Q..=--I_L\o'--_____________

POSITION ON MUlTIPLEXER CHANNEL

I

DEVICE
WAITING TIME
TIME
SELECTOR
CHANNEL I
~~II

.200

A

I.G;.O

B

c.8.9

tlc.

I

DATE _ _ _ _ _ _ _ _ _ _ ___

3

2

2.70Z.J 15-1030

2.702./,5-/0=.0

.9L.fi

.91.flj-

A

B

i

2.76"2.J,o-IC~

B

B

l.bO

C8.S>

\.loO

L8~

,.bO

28.~

l...jY)

"2.0.~

"C..~

CD.~

C.e:o

A SUM

A

I

6

I

7

18.~
B

A

8

l

.

I

.94Lt

A

I

14-43

'/O-8"38~

/·4'2.

A

5

4

?7tsz/I-/o30

I

I

B

\.~O

28.9

/.bO

"Z83

z..O~

Z.g,C

(p.3,

C.SO

W2>

5.4\

/2..0

5",4 \

Ic.a

7Lf-.Z

c.5

5.4\

IZ.O

S·Yl

Ico

74-.£.

7. .t?

le.o 133.1

1.1

!

A

B

A

B

A

B

DEVICE
SELECTOR
CHANNEL 2

"l.~rr
DEVICE

:2.00

.8

3.40

'2.1.~

"Z..<2P

Le·-=:,

."2.00

5.LfI

12.·0

4-.40

7·7..::'

7Lf.L

'C.Lf9

QUOTIENT

4.,

Ic·o,

DEVICE
PREVIOUS
SUM

rr,fo.s

I

."2.=

10·41

2

3

4

7.~"'>

74.,-

G.4~

."2.00

t.:>. L\ 1

1'(,.0

4.""1

S'?:>.I

,.160

ZOO

t::;·41

t"t...o

7·-z..~

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[c..D

7.0

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A SUM

10.0

QUOTIENT

ID.l\-

DEVICE

'2..0

PREVIOUS

{O·Co

SUM

8L\.L

"(..4<::>

IS."C.<..

A SUM

QUOTIENT

10.7

~·L\I

DEVICE

1·3-

?...O.c,3.

A SUM

PREVIOUS

7.0

QUOTIENT

2\.9

~2:L

DEVICE

Z.O

LOA9
SUM

5

PREVIOUS
SUM

14-.L
GSo.[

A SUM

10.<0

QUOTIENT

15.<-

1/9,).(

DEVICE

"2.5·8

6

7

"2..,5

PREVIOUS

-

SUM

~.'-t

A SUM
QUOTIENT
DEVICE

A SUM

PREVIOUS

QUOTIENT

SUM

DEVICE

i

A SUM

PREVIOUS

QUOTIENT

SUM

DEVICE
SUM

eFigure 15. Excessive 2702 Load Sum Worksheet Example

IBM 2702 WORKSHEET

l"\o~ Yo - '?_7_0_2
_ _ _ _ __

SYSTEM IDENTIFICATION

DATE

"1:~:'1 " I:~ "~-:8:T ~-~;- ~+.,- ;, i.,·
:============:==I.=A~===:I:2=!=~=2 =o=:= :=B2:=.~=:={=.A=~= =:=G8= B2~.<: >- I~'~ t- I-.:- 2-0-t-?8-B-~9- -t- A-2- -tr-~l-"- ~-_-_t- -_~-_B-~=_= := A=2=~ ~ -B2- - - -j"~ :~'b~

1" :~4't

='9==1:'=/=A6=2

2,·4-0

ZI.3

,:

1:

Ie..-8=:> IZO·3 2...~

2.~

120.3,

;Z0-3

-z.~fZo.~

~--------------~~------+------r----~------~-----+------+-----~----~------+-----r-----

~D-EV-IC-E-I------2-7-0--G--~-C)---+--CJ--~-5--.~--14-,L--.O--~6--.4--\-+-I,--.O--4-5-.-~-I~'I-Z-.-b--+-5-.-4-J--t-12~;-r6-.-~--I-~-\-Z-.o--T-----~--DEVICE 2

'2.702

0

0

5.4-1

IZ.O

5.41

DEVICE 3

'2.702

0

0

5.LI-(

IL.o

5.4-1

i

1"'2.·0

:5.1..\-1

IG.O, 5.41

!

I'G.O

5.41

1'G.o

IG.o

5.4-\

IG.O

5·41

i

12..0

'5.4\

\"'2...0

I

-------

i
DEVICE 4
DEVICE 5
j - - - - --- r - - - - - j - - - - - -

f----=.D~EVI..:..C:.:.E..:..6_____________t------+_----_+----_I------+----_+------+_----_+------f__----_+_----__+------t--------+------t------t------+------j--------r-- ---DEVICE 7
DEVICE 8

f-----------------~------+_-----+------r__----_+_----_t------+_----___t_------t_----_t_----

- j - - - - - - j---------t-------+---- -- - j - - - - - - -

-----r----- --.-----

DEVICE 9
DEVICE 10
SUM A's AND B's

f- -:_~_~ _IPL_I:_:~:_RX_S_UM_B_i

o

a

"Z-l .Z~ aJ.::,:?- 2.0.c..~ 8'5.'"2..

><
________o__~L(-------4--0-.-0_+><-------eo---.~__j-X---'-,--'-"'G-I-.

_______

3___

c.o .Ca3

'2- \ ."2.::>

2D.l:3 8?:z. 2.J::::;:,.&:. 85.""L-

?D.&:,38S.c.

GO.to

c,;_~G_._~L--+Z _~- =~=- -

'_'::_--"_0_'

,----------_;><_--_-

_______Zo_G_-

-_-t-k2<_--_---_____
- ____

I
40.001
.9
1.9
1..91
:E:: :::
10C.~+ - CJ'021."2:>~9_0-_-~_-_ ___
f---P-RE-VI-OU:.:.S~L---=OA-D------------------------+------------~-------------+-------------+----------,-~~JI

I

'~',:,:
LIMIT

L - -_ _ _

I
I

"u~""
=31=L-i_ne=2=70=2===~-

I:!

10.1

10.0

10.0

~

:

_

~_- +i ----_I

~,731~_ I:2.'83r- ,,:~3B-'- ,,:~47 I ,:'~SS,,,,--f---;:,
-_-_97=.6======:1~---_---1-96.:-------~-~ ~
'''A

++-_-_-_-_

__

---___ ___-_-29-0.0-

~_ _ _ _ _ _ _- ' - -_ _ _ ____:_~-15 + (5-1)10 ",S5
f (i - I) k

MAXIMUM NUMBER OF REVOLUTIONS TO COMPLETE SERVICE: n

• Figure 16. IBM 2702 Special Analysis Worksheet Example (Sheet 1 of 2)

..

;

"'.,

no

~

I
_.
1__

..

_--_-_-_-_-_-_-_-_

-<:_:_:'
__-------

_-_-

1"L1."3

80.~

1.

-+~_-_- -_- _=- _,j_- -----t--~---

1

I

m.o

m .•

LI _ _ _ _ _ _ _- - - ' -_ _ _ _ _- - - ' - - -_ _ _ _- - - - " - - -_ _ _ _

-~;::n

~

_ _ _ _

~

IBM 2702 WORKSHEET
SYSTEM IDENTIFICATION _ _
N\--'--'-o""--"d""'-""e.".,1'-------4---'--"O"---_L=-:7--=O=--'2.=-_ _ _ _ _ _ _ _ __

II

NUMBER OF LlNES=
LINE NUMBER=
SUBTRACT: K =

"max =

REVOLUTION

'2

1
1=2432..

9

n=

30

A1

i = I
1
2=

i =2

i

2.89(,

DATE _ _ _ _ _ _ _ __

i

i =4

i=3

'2=3.37G

12 =

IG

n=

I

A2

I

!

"2..3., I

'.10

SELECTOR CHANNEL 2

2~1I

"E.-8

15

n=
B1

28·9
CC>.3,

15

I

I

A2

B2

I· <0
c·B

B2

A2

28~1 I.e:.

'2.8·9

"2..0-3 1

C:O-3

zB

I

I"z'.o

5·lf

12..0

5.q

1'2.0

5·Lf

(Z.O

5.4-

Ic...-o' 5.4-

12.·0

c70Z 1 S.LJ-

\e.O

S.y.

12. .0 0.4

Ic.·o

DEVICE 3

'2=

B2

n=

I

I

:

I
1

n=

n=

n=

A2

B2

A2

i

B2

i

i

i =8
12 =

B2

A2

n=

I

A2

B2

I

A2

B2

i

i

I

5-'+

2.70c

'L10Z

i =7

'2 =

!

n=

i
DEVICE 1

i =6

'2 =

,

SELECTOR CHANNEL 1

DEVICE 2

-I = 5

12 =

I

i
I

I

I

DEVICE 4

,

I

DEVICE 5

I

II

DEVICE 6

i

DEVICE 7

I

I

I

i

DEVICE 8
DEVICE 9

I

DEVICE 10

20'0 85:"2.- cO.cO 8.5·G

SUM A's AND B's

><

MULTIPLY: I; X SUM Bj

I

2..07

><

<",0.<:0

0.=

0·0

A REMAINDER
B REMAINDER

4-0-0

1.9

8s.L..

>< 2.881><

247

81. 0

I.

><

1><

><

><

><

!

1

I

!

10.0

51.9

i

I
LIMIT

15 L;ne 2702

I 31 Une 2702

46.4

!

I

10.0

92.9
i

I

94.4

142.4

97.6

!

238.4

190.4

I

286.4

334.4

,

I

-I

196.8

395.2

296.0

494.4

692.8

593.6

i
---~---

---

1
I

I

I_-

IG

382.4

--

--

I

I

j
MAXIMUM NUMBER OF REVOLUTIONS TO COMPLETE SERVICE: n + (i - 1) k =

/.9

+ (2. -/) .9 =- 2. 4

• Figure 16. IBM 2702 Special Analysis Worksheet Example (Sheet 2 of 2)

I

792.0

--

Index

Channel-to-channel
............................
............ 5,7
1052 ............................. ........................................ ................. 5
14, 17
14,15
15
Arithmetic-logic unit
.....................................
.. .... 5, 7
.. 68, 72
Autopolling (2702) ............................... ..............
Average timing formulas
.. ... . ... .. .... .. .. .. ... ........................ 44
Binary shift operations .

50

57,59
CCW chaining and fetching
19
Central processing unit time, example of determining
available ...............................................................
41
Chaining .. ... .. .. ... ... .... .. ... .. .. ... ... .. . ..... .. ... .. .. ... .. ... .. ... .. .. ............... 19
Channel
Chaining . .. .... .. ... ... . . .... .. .. .. .. .. ................................
19
Characteristics ........................
................ ..... ..... .
18
Control ............................................ .............................
18
Data chaining in gaps ..................................................
20
25
Evaluation factors ........
.. .............
57
FetchingCCW's ....................................
19
Implementation ...................
21
Late command chaining ...
.. ... .... ......
20
89
Multiplexer ...............................
..... 21
Priority .. .. .. ........ .. .. .. .. .. .. .. .. .... ..
. .. .... ... ... ...... 21
Program conventions ........... " .. .. ... .. ... .. .. .... .
22
Registers ........................ .......................... .... ... ...........
19
Selector............................
.. 5, 8, 9, 21, 26, 89
20
. ... .. ...... ...... .
.. .............. .. 5, 7
Channel interference
Evaluation procedure
41
With CPU ........................ ..
41,89
Multiplexer .. ... .. .. .... ... .. .. . ... ...
. .. . ... . ........ .
30
Selector ....................................................... .
26
Channels ..................................................................... .
7
Check reset key ..................... .
14
. ................ .
Classes of commands .
23
Command chaining
.............................. .
20
Commands, classes of ....... ............................ .
23,24
Concurrent input/ output operations
.............. .
22
Configurator, Model 40
............... .
6
Console typewriter ..................................... .
5
Control panel, system ...................... .
.5,9,10
Conventions, channel program
22
Convert instructions . " . ................... .
52
CPU check switch .......................... .
14,17
CPU time, example of determining
41
Data chaining (I/O) ..
Data chaining in gaps
Data switches
Device load in multiplex mode evaluation
Device priority in multiplex mode evaluation
Device wait time in multiplex mode evaluation .
Direct access devices channel evaluation

22
20
14,15
30
30
30
65

Direct control ............................................ .
Disk storage device channel evaluation .... .
Display key .
Drum storage device channel evaluation .

J

65
B,W
65

Emergency pull switch
Execute instruction
External interruption time

11,12
25

5"
U

lU

Fetching CCW's
Floating-point registers ...

5,7,8

General channel information
General registers .... . ... ..... .. .

18
5,7,8

IBM 2702 Transmission Control
Channel evaluation
Telegraph Ctl-I
(75 bps)
(135.5 bps)
(600 bps)
(45 bps)
(57 bps)
(75 bps)
Telegraph Ctl-II (110 bps)
Consideration of in multiplex mode evaluation.
Special analysis of performance of .
IBM 2821 Control Unit, consideration of in multiplex
mode evaluation .................................. .
Input/Output (I/O)
Instruction time .................... .
Interruption .................................................... .
Operations ... .......... .
Operations, concurrent.
Input/output devices, command classifications for
Instruction configurations
Instruction set ... ..................... ............. . .... .
Instruction times
Interference caused by priority devices .
Interference by channel
(see "Channel interference")
Interruption
Key...............
................ .
Times.
.............. .
Interval timer

67
71
75
77
78
81
83
85
35
36,87
35
11
50
9

50
22

24
£

44
31

11, 1::

Key switch and meters .

17

Late command chaining
............. .
Legend for System/360 timing .
Light
Manual
System
Test
Wait ...
............... .
Device
Key
Light

2(:

52
11, 1:'11, l~
11, l~·
11, 1~
11, l~
..:.1,

l~

~l~ 1~

lndex

III

Limits
Previous
Priority
Sum
Sums for 2702
l'nit switches
Local storage
Log-out key
i .oss of perlormance

89
33
30
33
36
11,13
26
5,7,8
14, 16
22

"\fachine check interruption
\fagnetic tape channel evaluation
'.bin storage
:\1anual light
\leters
\fultiplex mode evaluation
Deviee priority in
Device wait time in
Procedure
':\fultiplexer
Channel
Subchannels

9
61
5
11,13

Operator controls
Operator intervention controls
Optional features, Model 40
Overrun
Overrun test
Exception
Procedure
Panel, system control
Performance time, lost
Power-on/off kev
Previous load in" multiplex mode evaluation
Printer channel evaluation
Printer-keyboard
Priority, channel
Priority device
Factors for 2702 .
Formula
Priority of devices in multiplex mode evaluation
Processing unit, 2040
Processor storage (main storage)
Program interruption
PS\V restart key

112

17
30
30
30
33
33
32
34
5,7,8,21
30
5,7,21
11
13
5
22
26
27
5,9,10
33
11,13
33
57,59
5,57
21
30
39,87
32
31
30
5,7
5
9
14,16

Punched card channel evaluation
Rate switch
Reset, check
Reset, system
Scope of conventions (I/O)
SeJector channel
Special analysis of 2702 performance
Start key, .
Stop key
Storage
Local
Main
Protection
Select switch
Store key.
Store and display
Supervisor call interruption time
Sychronization (buffered I/O)
System/360 timing legend
System control function of
Store and display
System reset
System control panel
System control panel controls
Operator controls
Operator intervention controls
Key switch and meters
Light (test)
Light (wait)
System description
System light
System reset
System reset key
Test 1ight
Test, overrun .
Time, lost performance
Timing assumptions
Timing considerations
Timing legend
Typewriter
Variable-field-length instructions
.................................... ..
\Vait light
\Yait time in multiplex mode evaluation
\Vait times, ranges of
Worksheet example

57,59
13,14
5,7,8
14
10
23
5,9,21
26
36
14
14
20
5,7,8
5,8,15

5
5,7,8
14
14,16
10

9
39
............... 52
11
10
10
5,9,10
11
13
17
n,13
11,13

5
11,13

10
14
11,13
26
33
44
44
52
5,57
50
11,13
30
32
35
22

IBM System/360 Model 40
Functional Characteristics

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