Xilinx UG029 ChipScope Pro 10.1 Software And Cores User Guide Chip Scope 10 1 V10 March 24 2008

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ChipScope Pro 10.1 Software and Cores User Guide

ChipScope Pro 10.1

Software and Cores

User Guide

UG029 (v10.1) March 24, 2008

ChipScope Pro 10.1 Software and Cores User Guidewww.xilinx.com UG029 (v10.1) March 24, 2008

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contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with

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Revision History

The following table shows the revision history for this document.

Date Version Revision

04/09/02 1.0 Initial Xilinx release.

10/29/02 5.1

Added new Chapter 3, “Using the ChipScope Pro Core Inserter”;

Old Chapter 3 is new Chapter 4, “Using the ChipScope Pro Analyzer”;

Updated all chapters to be compatible with 5.1i tools;

Revised version number to be in sync with version of tools.

03/06/03 5.2 Updated all chapters to be compatible with 5.2i tools;

Updated version number to reflect version number of tools.

05/15/03 5.2.2

Chapter 1: Added the “Choice of Match Unit Counter” section to Table 1-3;

Chapter 2: Added the “Selecting Match Unit Counter Width” section; updated several

“trigger” screen shots;

Chapter 3: Added “Selecting Match Unit Counter Width” section;

Chapter 4: Updated screen shots in the “Configuring the Target Device(s)” section;

Added “Displaying Configuration Status Information” section;

Updated “Counter” section;

Added notes to the “Depth” and “Samples Per Trigger” sections;

Updated “VIO Console Window” section and most of its screen shots.

8/29/03 6.1

Updated all chapters to be compatible with 6.1i tools;

Updated version number to reflect version number of tools;

Added Chapter 5, “ChipScope Engine JTAG Tcl Interface”

02/13/04 6.2

Updated all chapters to be compatible with 6.2i tools;

Updated version number to reflect version number of tools;

Chapter 2: Added the “Generating the ATC2 Core” section;

Updated all chapters to reflect ATC2 compatibility;

Miscellaneous edits for clarity or continuity.

UG029 (v10.1) March 24, 2008 www.xilinx.comChipScope Pro 10.1 Software and Cores User Guide

06/30/04 6.3

Updated all chapters to be compatible with 6.3i tools;

Updated version number to reflect version number of tools;

Miscellaneous edits for clarity or continuity;

Added MultiPRO cable information.

10/04/04 6.3.1 Minor text corrections.

02/16/05 7.1

Updated all chapters to be compatible with 7.1i tools;

Updated version number to reflect version number of tools;

Updated ATC2 core description to include the new auto-setup and “always on” features;

Added information regarding Analyzer support on Linux and Solaris;

Added information on the client/server remote debug feature;

Added Platform Cable USB cable information;

Miscellaneous edits for clarity or continuity.

10/18/05 8.1

Updated all chapters to be compatible with 8.1i tools;

Updated version number to reflect version number of tools;

Removed support for the MultiLINX and Agilent E5904B cables;

Removed support for the ILA/ATC core.

09/18/06 8.2 Updated all chapters to be compatible with 8.2i tools;

Updated version number to reflect version number of tools.

12/01/06 9.1 Updated all chapters to be compatible with 9.1i tools;

Updated version number to reflect version number of tools.

01/10/07 9.1.01

Updated all chapters to be compatible with 9.1.01i tools;

Updated version number to reflect version number of tools;

Added “Using the Core Inserter with Command Line Implementation” in Chapter 3;

Added “System Monitor” in Chapter 4

Expanded Chapter 5, “ChipScope Engine JTAG Tcl Interface.”

05/30/07 9.2

Updated all chapters to be compatible with 9.2i tools;

Updated version numbers to reflect version number of tools;

Edits throughout to increase clarity and eliminate redundancy;

Removed Windows 2000 support;

Converted Arguments sections to tables in Chapter 5, “ChipScope Engine JTAG Tcl

Interface.”

03/24/08 10.1

Updated all chapters to be compatible with 10.1 tools.

Updated version numbers to reflect version number of tools.

Replaced the ChipScope Core Generator tool with the Xilinx CORE Generator tool.

Chapter 1, “Introduction”: Added Xilinx CORE Generator tool to Table 1-1, page 19;

Updated PC and Linux system requirements in Table 1-9, page 43 and Table 1-10,

page 43, respectively, removed “Host System Requirements for Solaris.” Chapter 4,

“Using the ChipScope Pro Analyzer”: Added “Using Multiple Platform Cable USB

Connections,” page 116 and “External Input,” page 144 section. Chapter 5, “ChipScope

Engine JTAG Tcl Interface”: Updated “Requirements,” page 149 and “CseJtag Tcl

Example,” page 194.

Date Version Revision

ChipScope Pro 10.1 Software and Cores User Guidewww.xilinx.com UG029 (v10.1) March 24, 2008

ChipScope Pro 10.1 Software and Cores User Guidewww.xilinx.com 5

UG029 (v10.1) March 24, 2008

Schedule of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Schedule of Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Preface: About This User Guide

User Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Additional Support Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Typographical Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Chapter 1: Introduction

ChipScope Pro Tools Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

ChipScope Pro Tools Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Using ChipScope Pro Cores in Embedded Processor and DSP Tool Flows . . . . . . . . 22

ChipScope Pro Cores Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

ICON Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

ILA Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

IBA/OPB Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

IBA/PLB Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

VIO Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

ATC2 Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

IBERT Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Synthesis Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Software Tools Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Communications Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Board Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Host System Requirements for Microsoft Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Host System Requirements for Linux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Software Installation and Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Chapter 2: Using the CORE Generator Tool

CORE Generator Tool Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Locating the ChipScope Pro Cores in CORE Generator. . . . . . . . . . . . . . . . . . . . . . . 46

Generating an ICON Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

General ICON Core Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Generating the Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Using the ICON Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Generating an ILA Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

ILA Core Trigger and Storage Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

ILA Core Trigger Port Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Generating the Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Using the ILA Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table of Contents

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UG029 (v10.1) March 24, 2008

Generating the VIO Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

General VIO Core Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Generating the Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Using the VIO Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Generating the ATC2 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

ATC2 Core Acquisition and State Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

ATC2 Core Pin and Signal Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

ATC2 Core ATCK and ATD Pin Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Generating the Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Using the ATC2 Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Chapter 3: Using the ChipScope Pro Core Inserter

Core Inserter Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Using the Core Inserter with ISE Project Navigator . . . . . . . . . . . . . . . . . . . . . . . . . . 69

ChipScope Definition and Connection Source File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Useful Project Navigator Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Using the Core Inserter with Command Line Implementation. . . . . . . . . . . . . . . . 72

Command Line Flow Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Create CDC Project Step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Edit CDC Project Step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Insert Cores Step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

ChipScope Pro Core Inserter Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Working with Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Specifying Input and Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Project Level Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Core Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Choosing ICON Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Choosing ILA Trigger Options and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Choosing ILA Core Capture Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Choosing ATC2 Data Capture Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Choosing Net Connections for ILA Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Adding Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Inserting Cores into Netlist. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Managing Project Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Chapter 4: Using the ChipScope Pro Analyzer

Analyzer Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Analyzer Server Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Analyzer Client Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Project Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Signal Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Message Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Main Window Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Analyzer Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Working with Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Printing Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Importing Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Exporting Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Closing and Exiting the Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Viewing Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

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UG029 (v10.1) March 24, 2008

Setting up a Server Host Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Opening a Parallel Cable Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Opening a Platform Cable USB Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Using Multiple Platform Cable USB Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Polling the Auto Core Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Configuring the Target Device(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Trigger Setup Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Waveform Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Listing Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Bus Plot Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

VIO Console Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

System Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

ChipScope Pro ILA Waveform Toolbar Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

ChipScope Pro Analyzer Command Line Options. . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Chapter 5: ChipScope Engine JTAG Tcl Interface

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

CseJtag Tcl Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Command Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

::chipscope::csejtag_session create . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

::chipscope::csejtag_session destroy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

::chipscope::csejtag_session get_api_version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

::chipscope::csejtag_session send_message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

::chipscope::csejtag_target open . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

::chipscope::csejtag_target close . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

::chipscope::csejtag_target lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

::chipscope::csejtag_target unlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

::chipscope::csejtag_target get_lock_status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

::chipscope::csejtag_target clean_locks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

::chipscope::csejtag_target flush . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

::chipscope::csejtag_target set_pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

::chipscope::csejtag_target get_pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

::chipscope::csejtag_target pulse_pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

::chipscope::csejtag_target wait_time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

::chipscope::csejtag_target get_info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

::chipscope::csejtag_tap autodetect_chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

::chipscope::csejtag_tap interrogate_chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

::chipscope::csejtag_tap get_device_count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

::chipscope::csejtag_tap set_device_count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

::chipscope::csejtag_tap get_irlength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

::chipscope::csejtag_tap set_irlength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

::chipscope::csejtag_tap get_device_idcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

::chipscope::csejtag_tap set_device_idcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

::chipscope::csejtag_tap navigate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

::chipscope::csejtag_tap shift_chain_ir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

::chipscope::csejtag_tap shift_device_ir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

::chipscope::csejtag_tap shift_chain_dr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

::chipscope::csejtag_tap shift_device_dr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

::chipscope::csejtag_db add_device_data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

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::chipscope::csejtag_db lookup_device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

::chipscope::csejtag_db get_device_name_for_idcode . . . . . . . . . . . . . . . . . . . . . . . . . 190

::chipscope::csejtag_db get_irlength_for_idcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

::chipscope::csejtag_db parse_bsdl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

::chipscope::csejtag_db parse_bsdl_file. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

CseJtag Tcl Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

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Chapter 1: Introduction

Table 1-1: ChipScope Pro Tools Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 1-2: ChipScope Pro Features and Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 1-3: Trigger Features of the ILA Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 1-4: CoreConnect OPB Protocol Violation Error Description(1) . . . . . . . . . . . . . . . 30

Table 1-5: OPB Signal Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 1-6: PLB Signal Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 1-7: Design Parameter Changes Requiring Resynthesis . . . . . . . . . . . . . . . . . . . . . . 41

Table 1-8: ChipScope Pro Download Cable Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 1-9: PC System Requirements for ChipScope Pro 10.1 Tools . . . . . . . . . . . . . . . . . . 43

Table 1-10: Linux Requirements for ChipScope Pro 9.2i Tools . . . . . . . . . . . . . . . . . . . . . . 43

Chapter 2: Using the CORE Generator Tool

Table 2-1: ILA Trigger Match Unit Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Chapter 3: Using the ChipScope Pro Core Inserter

Table 3-1: ILA Trigger Match Unit Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Chapter 4: Using the ChipScope Pro Analyzer

Table 4-1: Cores Supported by the Analyzer Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 4-2: Operating System Support for the ChipScope Pro Analyzer . . . . . . . . . . . . . 100

Table 4-3: ChipScope Pro Analyzer Server Command Line Options. . . . . . . . . . . . . . . . 100

Table 4-4: Configuration of Multiple Client Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Chapter 5: ChipScope Engine JTAG Tcl Interface

Table 5-1: CseJtag Tcl ::chipscope:: Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Table 5-2: Summary of ::chipscope::csejtag_session Subcommands . . . . . . . . . . . . . . . . 150

Table 5-3: Summary of ::chipscope::csejtag_db Subcommands . . . . . . . . . . . . . . . . . . . . 151

Table 5-4: Summary of ::chipscope::csejtag_target Subcommands. . . . . . . . . . . . . . . . . . 151

Table 5-5: Summary of ::chipscope::csejtag_tap Subcommands . . . . . . . . . . . . . . . . . . . . 152

Table 5-6: Arguments for Subcommand ::chipscope::csejtag_session create . . . . . . . . . 153

Table 5-7: Arguments for Subcommand ::chipscope::csejtag_session create . . . . . . . . . 154

Table 5-8: Arguments for Subcommand ::chipscope::csejtag_session send_message. . 156

Table 5-9: Arguments for Subcommand ::chipscope::csejtag_target open . . . . . . . . . . . 157

Table 5-10: Argument targetName and [optional args...] combinations . . . . . . . . . . . . . 157

Table 5-11: Arguments for Subcommand ::chipscope::csejtag_target close . . . . . . . . . . 159

Table 5-12: Arguments for Subcommand ::chipscope::csejtag_target lock . . . . . . . . . . . 160

Table 5-13: Arguments for Subcommand ::chipscope::csejtag_target unlock. . . . . . . . . 161

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Table 5-14: Arguments for Subcommand ::chipscope::csejtag_target get_lock_status . 162

Table 5-15: Arguments for Subcommand ::chipscope::csejtag_target clean_locks . . . . 163

Table 5-16: Arguments for Subcommand ::chipscope::csejtag_target flush . . . . . . . . . . 164

Table 5-17: Arguments for Subcommand ::chipscope::csejtag_target set_pin . . . . . . . . 165

Table 5-18: Arguments for Subcommand ::chipscope::csejtag_target get_pin . . . . . . . . 166

Table 5-19: Arguments for Subcommand ::chipscope::csejtag_target pulse_pin . . . . . . 167

Table 5-20: Arguments for Subcommand ::chipscope::csejtag_target wait_time . . . . . . 168

Table 5-21: Arguments for Subcommand ::chipscope::csejtag_target get_info . . . . . . . 169

Table 5-22: Arguments for Subcommand ::chipscope::csejtag_tap autodetect_chain . . 171

Table 5-23: Arguments for Subcommand ::chipscope::csejtag_tap interrogate_chain . 172

Table 5-24: Arguments for Subcommand ::chipscope::csejtag_tap get_device_count. . 173

Table 5-25: Arguments for Subcommand ::chipscope::csejtag_tap set_device_count. . 174

Table 5-26: Arguments for Subcommand ::chipscope::csejtag_tap get_irlength . . . . . . 175

Table 5-27: Arguments for Subcommand ::chipscope::csejtag_tap set_irlength . . . . . . 176

Table 5-28: Arguments for Subcommand ::chipscope::csejtag_tap get_device_idcode. 177

Table 5-29: Arguments for Subcommand ::chipscope::csejtag_tap set_device_idcode. 178

Table 5-30: Arguments for Subcommand ::chipscope::csejtag_tap navigate. . . . . . . . . . 179

Table 5-31: Arguments for Subcommand ::chipscope::csejtag_tap shift_chain_ir. . . . . 180

Table 5-32: Arguments for Subcommand ::chipscope::csejtag_tap shift_device_ir. . . . 182

Table 5-33: Arguments for Subcommand ::chipscope::csejtag_tap shift_chain_dr . . . . 184

Table 5-34: Arguments for Subcommand ::chipscope::csejtag_tap shift_device_dr . . . 186

Table 5-35: Arguments for Subcommand ::chipscope::csejtag_db add_device_data. . . 188

Table 5-36: Arguments for Subcommand ::chipscope::csejtag_db lookup_device . . . . 189

Table 5-37: Arguments for Subcommand ::chipscope::csejtag_db get_device_name_for_idcode

190

Table 5-38: Arguments for Subcommand ::chipscope::csejtag_db get_irlength_for_idcode 191

Table 5-39: Arguments for Subcommand ::chipscope::csejtag_db parse_bsdl . . . . . . . . 192

Table 5-40: Arguments for Subcommand ::chipscope::csejtag_db parse_bsdl_file. . . . 193

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Chapter 1: Introduction

Figure 1-1: ChipScope Pro System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 1-2: ChipScope Pro Tools Design Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 1-3: ILA Core Connection Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 1-4: ATC2 Core and System Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Chapter 2: Using the CORE Generator Tool

Figure 2-1: Locating the ChipScope Pro Cores in CORE Generator. . . . . . . . . . . . . . . . . . 46

Figure 2-2: Selecting the ICON Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 2-3: ICON Core Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 2-4: List of Generated ICON Core Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 2-5: Selecting the ILA Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 2-6: ILA Core Trigger and Storage Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 2-7: Trigger Sequencer Block Diagram (with 16 levels and 16 match units) . . . . 53

Figure 2-8: ILA Core Trigger Port Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 2-9: List of Generated ILA Core Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 2-10: Selecting the VIO Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 2-11: VIO Core General Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 2-12: List of Generated VIO Core Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 2-13: Selecting the ATC2 Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 2-14: ATC2 Core Acquisition and State Parameters . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 2-15: ATC2 Core Pin and Signal Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 2-16: ATC2 Core ATCK and ATD Pin Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 2-17: List of Generated ATC2 Core Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Chapter 3: Using the ChipScope Pro Core Inserter

Figure 3-1: Creating a New .cdc Source File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 3-2: The .cdc Source File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 3-3: Command Line Core Inserter Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 3-4: Create CDC Project Step. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 3-5: Edit CDC Project Step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 3-6: Insert Cores Step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 3-7: Blank Core Inserter Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 3-8: Core Inserter Project with Files Specified. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 3-9: Core Inserter as Launched from Project Navigator . . . . . . . . . . . . . . . . . . . . . . 78

Figure 3-10: ICON Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 3-11: ILA Core Trigger Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 3-12: Trigger Sequencer Block Diagram with 16 Levels and 16 Match Units . . . 83

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Figure 3-13: ILA Core Capture Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 3-14: ILA Core Data Same As Trigger Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 3-15: ATC2 Core STATE Mode Data Capture Settings . . . . . . . . . . . . . . . . . . . . . . 86

Figure 3-16: ATC2 Core TIMING Mode Data Capture Settings. . . . . . . . . . . . . . . . . . . . . 86

Figure 3-17: ILA Net Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 3-18: ATC2 Net Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 3-19: Select Net Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 3-20: Specifying Data Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 3-21: Core Inserter Tools Preference Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 3-22: Core Inserter ISE Integration Preference Settings. . . . . . . . . . . . . . . . . . . . . . 96

Figure 3-23: Core Inserter Miscellaneous Preference Settings . . . . . . . . . . . . . . . . . . . . . . 96

Chapter 4: Using the ChipScope Pro Analyzer

Figure 4-1: Example Token File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Figure 4-2: Example Waveform with Tokens . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Figure 4-3: Saving a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Figure 4-4: Example Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Figure 4-5: Selecting the File Print Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Figure 4-6: Print Wizard (1 of 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 4-7: Waveform Printout Footer Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 4-8: Print Wizard (2 of 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 4-9: Expanding Buses in Print Wizard (2 of 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Figure 4-10: Print Wizard (3 of 3) for Sending to a PDF File . . . . . . . . . . . . . . . . . . . . . . . 110

Figure 4-11: Print Wizard (3 of 3) for Sending to a Printer. . . . . . . . . . . . . . . . . . . . . . . . . 110

Figure 4-12: Page Setup Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Figure 4-13: Blank Signal Import Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Figure 4-14: Export Signals Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 4-15: Server Settings for Local Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 4-16: Server Settings for Remote Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 4-17: Opening a Parallel Cable Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Figure 4-18: Opening a Platform Cable USB Connection . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 4-19: Boundary Scan (JTAG) Setup Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 4-20: Advanced JTAG Chain Parameters Setup Window . . . . . . . . . . . . . . . . . . . 118

Figure 4-21: Device Menu Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 4-22: Selecting a Bitstream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 4-23: Opening a Configuration File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 4-24: Device USERCODE and IDCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 4-25: Displaying Device Configuration Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 4-26: Displaying Device Instruction Register Status . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 4-27: Opening New Unit Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 4-28: Trigger Setup Window with Only Match Functions Expanded . . . . . . . . . 122

Figure 4-29: Trigger Setup Window with All Sections Expanded . . . . . . . . . . . . . . . . . . 122

Figure 4-30: Capture Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

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Figure 4-31: Storage Qualification Condition Set to Capture All Data . . . . . . . . . . . . . . 124

Figure 4-32: Storage Qualification Condition Using Boolean Equation . . . . . . . . . . . . . 124

Figure 4-33: Setting the Match Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Figure 4-34: Setting up the Match Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Figure 4-35: Viewing the Trigger Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Figure 4-36: Setting the Trigger Condition Boolean Equation . . . . . . . . . . . . . . . . . . . . . 127

Figure 4-37: Setting the Trigger Condition Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Figure 4-38: Reordering Buses or Signals in the Waveform . . . . . . . . . . . . . . . . . . . . . . . 130

Figure 4-39: Zoom Area Using the Automatic Popup Menu . . . . . . . . . . . . . . . . . . . . . . . 131

Figure 4-40: Zoom to Sample Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Figure 4-41: Centering the Waveform on a Marker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Figure 4-42: The Listing View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Figure 4-43: The Bus Plot Window: Data vs. Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Figure 4-44: The Bus Plot Window: Data vs. Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Figure 4-45: The VIO Console Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Figure 4-46: The Type Selection Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Figure 4-47: The Pulse Train Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Figure 4-48: VIO Toolbar and Menu Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Figure 4-49: System Monitor Project Tree Node and Signal Browser . . . . . . . . . . . . . . . 141

Figure 4-50: System Monitor Console Showing Valid Sensor Data. . . . . . . . . . . . . . . . . 142

Figure 4-51: System Monitor Console Showing Invalid Sensor Data . . . . . . . . . . . . . . . 143

Figure 4-52: System Monitor Setup Logging Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Figure 4-53: Main ChipScope Pro Analyzer Toolbar Display . . . . . . . . . . . . . . . . . . . . . . 146

Chapter 5: ChipScope Engine JTAG Tcl Interface

14 www.xilinx.comChipScope Pro 10.1 Software and Cores User Guide

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UG029 (v10.1) March 24, 2008

Preface

About This User Guide

This user guide provides users with information for using the ChipScope™ Pro IP cores

and tools:

•Integrated Controller core (ICON)

•Integrated Logic Analyzer core (ILA)

•Virtual Input/Output core (VIO)

•Integrated Bit Error Ratio core (IBERT)

•Agilent Trace Core 2 (ATC2)

•Xilinx CORE Generator™ tool (replaces the ChipScope Core Generator tool)

•Core Inserter tool

•Analyzer tool

The tools integrate the IP core and key hardware components with the target design inside

Virtex™, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4, Virtex-5, Spartan™-II, Spartan-IIE,

Spartan-3, Spartan-3E, Spartan-3A, and Spartan-3A DSP devices (including the QPro™

variants of these families). In this document, these devices are referred to collectively as the

supported devices.

For detailed information on how to generate the Integrated Bit Error Ratio Tester (IBERT),

see UG213, ChipScope Pro 10.1 Serial I/O Toolkit User Guide at

http://www.xilinx.com/literature/literature-chipscope.htm.

User Guide Contents

This user guide contains the following chapters:

•Chapter 1, “Introduction,” describes the ChipScope Pro tools. These tools integrate

key logic analyzer hardware components with the target design inside the supported

devices. The tools communicate with these components and provide the designer

with a complete logic analyzer.

•Chapter 2, “Using the CORE Generator Tool,” explains how to use this tool to

generate the following ChipScope Pro cores:

♦Integrated Controller core (ICON)

♦Integrated Logic Analyzer core (ILA)

♦Virtual Input/Output core (VIO)

♦Integrated Bit Error Ratio core (IBERT)

♦Agilent Trace Core 2 (ATC2)

After generating the cores, you can use the instantiation templates (that are provided)

to quickly and easily insert the cores into VHDL or Verilog designs. After completing

16 www.xilinx.comChipScope Pro 10.1 Software and Cores User Guide

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Preface: About This User Guide

the instantiation and running synthesis, you can implement the design using the

ISE™ 10.1 implementation tools.

•Chapter 3, “Using the ChipScope Pro Core Inserter,” explains how to use this post-

synthesis tool to generate a netlist that includes the user design as well as ICON, ILA,

and ATC2 cores as needed, parameterized accordingly. The Core Inserter gives you

the flexibility to quickly and easily use the debug functionality to analyze an already

synthesized design, and without any HDL instantiation.

•Chapter 4, “Using the ChipScope Pro Analyzer,” explains how to use this tool which

interfaces directly to the ICON, ILA, IBA/OPB, IBA/PLB, VIO, IBERT, and ATC2

cores (collectively called the ChipScope Pro cores). You can configure your device,

choose triggers, setup the console, and view the results of the capture on the fly. The

data views and triggers can be manipulated in many ways, providing an easy and

intuitive interface to determine the functionality of the design.

•Chapter 5, “ChipScope Engine JTAG Tcl Interface,” explains how to use this JTAG

scripting interface which provides Tcl scripting access to the ChipScope Parallel cable

JTAG communication library. The purpose of Tcl/JTAG is to provide a simple

scripting system to access basic JTAG functions. In a few lines of Tcl script, you should

be able to scan and manipulate the JTAG chain through standard Xilinx cables.

Additional Support Resources

To search the database of silicon and software questions and answers, or to create a

technical support case in WebCase, see the Xilinx website at:

http://www.xilinx.com/support.

Typographical Conventions

This document uses the following conventions. An example illustrates each convention.

Typographical

The following typographical conventions are used in this document:

Online Document

The following conventions are used in this document:

Convention Meaning or Use Example

Italic font

References to other documents See the Virtex-5 Configuration

Guide for more information.

Emphasis in text The address (F) is asserted after

clock event 2.

Underlined Text Indicates a link to a web page http://www.xilinx.com/virtex5

Convention Meaning or Use Example

Blue text Cross-reference link to a location

in the current document

See the section “User Guide

Contents” for details.

Refer to “Title Formats” in

Chapter 1 for details.

ChipScope Pro 10.1 Software and Cores User Guidewww.xilinx.com 17

UG029 (v10.1) March 24, 2008

Typographical Conventions

Red text Cross-reference link to a location

in another document

See Figure 2-5 in the Virtex-5

FPGA User Guide.

Blue, underlined text Hyperlink to a website (URL) Go to http://www.xilinx.com

for the latest documentation.

Convention Meaning or Use Example

18 www.xilinx.comChipScope Pro 10.1 Software and Cores User Guide

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Preface: About This User Guide

ChipScope Pro 10.1 Software and Cores User Guidewww.xilinx.com 19

UG029 (v10.1) March 24, 2008

Chapter 1

Introduction

ChipScope Pro Tools Overview

As the density of FPGA devices increases, so does the impracticality of attaching test

equipment probes to these devices under test. The ChipScope™ Pro tools integrate key

logic analyzer and other test and measurement hardware components with the target

design inside the following (hereinafter called supported devices): Virtex™, Virtex-E

Virtex-II, Virtex-II Pro, Virtex-4, Virtex-5, Spartan™-II, Spartan-IIE, Spartan-3, Spartan-3E,

Spartan-3A, and Spartan-3A DSP devices (including the QPro™ variants of these families).

The tools communicate with these components and provide the designer with a robust

logic analyzer solution.

ChipScope Pro Tools Description

Table 1-1gives a brief description of the various ChipScope Pro software tools and cores.

Table 1-1: ChipScope Pro Tools Description

Tool Description

Xilinx CORE Generator™ Tool(1) Provides core generation capability for the ICON, ILA, VIO, and ATC2 cores. The

Xilinx CORE Generator is part of the ISE software tool installation.

IBERT Core Generator

Provides full design generation capability for the IBERT core. The user chooses the

RocketIO transceivers and parameters governing the design, and the Core

Generator uses the ISE™ toolset to produce a configuration file.(2)

Core Inserter Automatically inserts the ICON, ILA, and ATC2 cores into the user’s synthesized

design.

Analyzer

Provides device configuration, trigger setup, and trace display for the ILA,

IBA/OPB, IBA/PLB, VIO, and IBERT cores. The various cores provide the trigger,

control, and trace capture capability. The ICON core communicates to the dedicated

Boundary Scan pins.

Engine JTAG (CseJtag) Tcl

Scripting Interface

The CseJtag scriptable Tcl command interface makes it possible to interact with

devices in a JTAG chain from a Tcl shell(2).

Notes:

1. The ICON, ILA, VIO, and ATC2 cores are now available through the Xilinx CORE Generator tool. The ChipScope Pro Core

Generator is now only used to generate the IBERT core.

2. For detailed information on how to generate the IBERT core, see UG213, ChipScope Pro Serial I/O Toolkit User Guide a

http://www.xilinx.com/literature/literature-chipscope.htm.

3. Tcl stands for Tool Command Language. The CseJtag Tcl interface requires the Tcl shell program that is included in the ISE 10.1 tool

installation ($XILINX/bin/nt/xtclsh.exe) or in the ActiveTcl 8.4 shell available from ActiveState (www.activestate.com).

20 www.xilinx.comChipScope Pro 10.1 Software and Cores User Guide

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Chapter 1: Introduction

Figure 1-1 shows a block diagram of a ChipScope Pro system. Users can place the ICON,

ILA, VIO, and ATC2 cores (collectively called the ChipScope Pro cores) into their design by

generating the cores with the Core Generator and instantiating them into the HDL source

code. You can also insert the ICON, ILA, and ATC2 cores directly into the synthesized

design netlist using the Core Inserter tool. The design is then placed and routed using the

ISE 10.1 implementation tools. Next, the user downloads the bitstream into the device

under test and analyzes the design with the Analyzer software.

The Analyzer tool supports the following download cables for communication between

the PC and the devices in the JTAG Boundary Scan chain:

•Platform Cable USB

•Parallel Cable IV

•Parallel Cable III

•MultiPRO (JTAG mode only)

X-Ref Target - Figure 1-1

Figure 1-1: ChipScope Pro System Block Diagram

Board-Under-Test

Host Computer with

ChipScope Pro Software

JTAG

Connections

cs_pro_sys_blk_diag

ChipScope

Pro

Target Device Under Test

User

Function

User

Function

User

Function

ILA Pro

ICON Pro

ILA Pro

Parallel

Cable

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UG029 (v10.1) March 24, 2008

ChipScope Pro Tools Description

The Analyzer and cores contain many features that FPGA designers need for thoroughly

verifying their logic (Table 1-2). User-selectable data channels range from 1 to 1024 and the

sample buffer sizes range from 256 to 131,072 samples. Users can change the triggers in real

time without affecting their logic. The Analyzer leads designers through the process of

modifying triggers and analyzing the captured data.

Table 1-2: ChipScope Pro Features and Benefits

Feature Benefit

1 to 1024 user-selectable data channels Accurately captures wide data bus

functionality.

User-selectable sample buffers ranging in

size from 256 to 131,072 samples

Large sample size increases accuracy and

probability of capturing infrequent events.

Up to 16 separate trigger ports, each with a

user-selectable width of 1 to 256 channels (for

a total of up to 4096 trigger channels)

Multiple separate trigger ports increase the

flexibility of event detection and reduce the

need for sample storage.

Up to 16 separate match units per trigger

port (up to 16 total match units) for a total of

16 different comparisons per trigger

condition

Multiple match units per trigger ports

increase the flexibility of event detection

while conserving valuable resources.

All data and trigger operations are

synchronous to the user clock at rates over

500 MHz

Capable of high-speed trigger event

detection and data capture.

Trigger conditions implement either a

boolean equation or a trigger sequence of up

to 16 match functions

Can combine up to 16 trigger port match

functions using a boolean equation or a

16-level trigger sequencer.

Data storage qualification condition

implements a boolean equation of up to 16

match functions

Can combine up to 16 trigger port match

functions using a boolean equation to

determine which data samples will be

captured and stored in on-chip memory.

Trigger and storage qualification conditions

are in-system changeable without affecting

the user logic

No need to single step or stop a design for

logic analysis.

Easy-to-use graphical interface Guides users through selecting the correct

options.

Up to 15 independent ILA, IBA/OPB,

IBA/PLB, VIO or ATC2 cores per device

Can segment logic and test smaller sections

of a large design for greater accuracy.

Multiple trigger settings

Records duration and number of events

along with matches and ranges for greater

accuracy and flexibility.

Downloadable from the Xilinx Web site Tools are easily accessible from the

ChipScope Suite.

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Chapter 1: Introduction

Design Flow

The tools design flow (Figure 1-2) merges easily with any standard FPGA design flow that

uses a standard HDL synthesis tool and the ISE 10.1 implementation tools.

Using ChipScope Pro Cores in Embedded Processor and DSP Tool Flows

The cores (ICON, ILA, IBA/OPB, IBA/PLB, VIO, and ATC2) can also be used in the EDK

and System Generator for DSP tool flows for embedded processor and DSP designs,

respectively. For information on how to use the ChipScope Pro cores, see:

•EDK tool flow at:

♦Platform Studio online help and refer to Debugging Hardware Using ChipScope Pro

•System Generator for DSP tool flow at:

♦System Generator User Guide and refer to Using ChipScope Pro Analyzer for Real-

time Hardware Debugging.

X-Ref Target - Figure 1-2

Figure 1-2: ChipScope Pro Tools Design Flow

ICON, ILA,

IBA/OPB,

IBA/PLB,

VIO, or

ATC2 cores

Generate...

ICON, ILA, and/or

ATC2 cores into

synthesized design

(.ngc or EDIF netlist)

Insert...

cores into HDL

source

Instantiate...

buses and

internal signals

to cores

Connect...

design with

cores in it

Synthesize...

design

Implement...

ChipScope Pro

Core Generator

ISE

ChipScope Pro

Core Inserter

waveform

trigger

bitstream

View...

Set...

Select...

or...

design without

instantiating

ChipScope cores

Synthesize...

cspro_tools_design_flow_100505

ChipScope Pro 10.1 Software and Cores User Guidewww.xilinx.com 23

UG029 (v10.1) March 24, 2008

ChipScope Pro Cores Description

ICON Core

All of the cores use the JTAG Boundary Scan port to communicate to the host computer via

a JTAG download cable. The ICON core provides a communications path between the

JTAG Boundary Scan port of the target FPGA and up to 15 ILA, IBA/OPB, IBA/PLB, VIO,

and/or ATC2 cores (as shown in Figure 1-1, page 20). For devices not of the Virtex-4 or

Virtex-5 families, the ICON core uses either the USER1 or USER2 JTAG Boundary Scan

instructions for communication via the BSCAN_VIRTEX primitive. The unused USER1 or

USER2 scan chain of the BSCAN_VIRTEX primitive can also be exported for use in your

application, if needed.

For Virtex-4 and Virtex-5 devices, the ICON core uses any one of the USER1, USER2,

USER3 or USER4 scan chains available via the BSCAN_VIRTEX primitives. In Virtex-4 and

Virtex-5 devices, it is not necessary to export unused USER scan chains because each

BSCAN_VIRTEX primitive implements a single scan chain.

ILA Core

The ILA core is a customizable logic analyzer core that can be used to monitor any internal

signal of your design. Since the ILA core is synchronous to the design being monitored, all

design clock constraints that are applied to your design are also applied to the components

inside the ILA core. The ILA core consists of three major components:

•Trigger input and output logic:

♦Trigger input logic detects elaborate trigger events

♦Trigger output logic triggers external test equipment and other logic

•Data capture logic:

♦ILA cores capture and store trace data information using on-chip block RAM

resources

•Control and status logic:

♦Manages the operation of the ILA core

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Chapter 1: Introduction

ILA Trigger Input Logic

The triggering capabilities of the ILA core include many features that are necessary for

detecting elaborate trigger events. These features are described in Table 1-3 (which spans

multiple pages).

Table 1-3: Trigger Features of the ILA Core

Feature Description

Wide Trigger Ports Each trigger port can be 1 to 256 bits wide.

Multiple Trigger Ports

Each ILA core can have up to 16 trigger ports. The ability to

support multiple trigger ports is necessary in complex systems

where different types of signals or buses need to be monitored

using separate match units.

Multiple Match Units per

Trigger Port

Each trigger port can be connected to up to 16 match units.

This feature enables multiple comparisons to be performed on

the trigger port signals.

Boolean Equation Trigger

Condition

The trigger condition can consist of a Boolean AND or OR

equation of up to 16 match unit functions.

Multi-Level Trigger

Sequencer

The trigger condition can consist of a multi-level trigger

sequencer of up to 16 match unit functions.

Boolean Equation Storage

Qualification Condition

The storage qualification condition can consist of a Boolean

AND or OR equation of up to 16 match unit functions.

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UG029 (v10.1) March 24, 2008

ChipScope Pro Cores Description

Choice of Match Unit Types

The match unit connected to each trigger port can be one of the

following types:

•Basic comparator:

♦Performs ‘=’ and ‘<>’ comparisons.

♦Compares up to 19 bits per slice in Virtex-5 devices.

♦Compares up to 8 bits per slice in all other supported

devices.

•Basic comparator w/edges:

♦Performs ‘=’ and ‘<>’ comparisons.

♦Detects high-to-low and low-to-high bit-wise transitions.

♦Compares up to 8 bits per slice in Virtex-5 devices.

♦Compares up to 4 bits per slice in all other supported

devices.

•Extended comparator:

♦Performs ‘=’, ‘<>’, ‘>’, ‘>=’, ‘<‘, and ‘<=’ comparisons.

♦Compares up to 8 bits per slice in Virtex-5 devices.

♦Compares up to 2 bits per slice in all other supported

devices.

•Extended comparator w/edges:

♦Performs ‘=’, ‘<>’, ‘>’, ‘>=’, ‘<‘, and ‘<=’ comparisons.

♦Detects high-to-low and low-to-high bit-wise transitions.

♦Compares up to 8 bits per slice in Virtex-5 devices.

♦Compares up to 2 bits per slice in all other supported

devices.

•Range comparator:

♦Performs ‘=’, ‘<>’, ‘>’, ‘>=’, ‘<‘, ‘<=’, ‘in range’, and ‘not

in range’ comparisons.

♦Compares up to 4 bits per slice in Virtex-5 devices.

♦Compares up to 1 bit per slice in all other supported

devices.

•Range comparator w/edges:

♦Performs ‘=’, ‘<>’, ‘>’, ‘>=’, ‘<‘, ‘<=’, ‘in range’, and ‘not

in range’ comparisons.

♦Detects high-to-low and low-to-high bit-wise transitions.

♦Compares up to 4 bits per slice in Virtex-5 devices.

♦Compares up to 1bit per slice in all other supported

devices.

All match units connected to a given trigger port are the same

type.

Table 1-3: Trigger Features of the ILA Core

Feature Description

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Chapter 1: Introduction

Choice of Match Function

Event Counter

All the match units of a trigger port can be configured with an

event counter, with a selectable size of 1 to 32 bits. This counter

can be configured at run time to count events in the following

ways:

•Exactly n occurrences

♦Matches only when exactly n consecutive or non-

consecutive events occur

•At least n occurrences

♦Matches and stays asserted once n consecutive or

non-consecutive events occur

•At least n consecutive occurrences

♦Matches once n consecutive events occur, and

stays asserted until the match function is not

satisfied.

Trigger Output Port

The internal trigger condition of the ILA core can be accessed

using the optional trigger output port. This signal can be used

as a trigger for external test equipment by attaching the signal

to an output pin.

However, it can also be used by internal logic as an interrupt,

a trigger, or to cascade multiple ILA cores together.

The trigger output port will have a determined amount of

latency depending on the core type:

•ILA core = 10 clock cycles

•IBA/OPB core = 15 clock cycles

•IBA/PLB core = 10 clock cycles

The shape (level or pulse) and sense (active-High or

active-Low) of the trigger output can be controlled at run-

time.

Table 1-3: Trigger Features of the ILA Core

Feature Description

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UG029 (v10.1) March 24, 2008

ChipScope Pro Cores Description

Using Multiple Trigger Ports

The ability to monitor different kinds of signals and buses in the design requires the use of

multiple trigger ports. For example, if you are instrumenting an internal system bus in

your design that is made up of control, address, and data signals, then you could assign a

separate trigger port to monitor each signal group (as shown in Figure 1-3).

If you connected all of these different signals and buses to a single trigger port, you would

not be able to monitor for individual bit transitions on the CE, WE, and OE signals while

looking for the Address bus to be in a specified range. The flexibility of being able to

choose from different types of match units allows you to customize the ILA cores to your

triggering needs while keeping resource usage to a minimum.

X-Ref Target - Figure 1-3

Figure 1-3: ILA Core Connection Example

Match Unit M0

(Basic w/edges)

Match Unit M1

(Basic w/edges)

Match Unit M2

(Basic)

Match Unit M3

(Basic)

Match Unit M4

(Range)

Match Unit M5

(Basic w/edges)

Trigger

Condition

Storage

Qualification

Condition

Data

Capture

Control

Data

Capture

Memory

TRIG0

TRIG_OUT

TRIG1

TRIG2

TRIG3

ILA Core

Interrupt

Clock

CE, WE, OE

Address

Data

Ext. Trigger

ila_pro_connection_example_070704

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Chapter 1: Introduction

Using Trigger and Storage Qualification Conditions

The ILA, IBA/OPB, and IBA/PLB cores implement both trigger and storage qualification

condition logic. The trigger condition is a Boolean or sequential combination of events that

is detected by match unit comparators that are attached to the trigger ports of the core. The

trigger condition is used to mark a distinct point of origin in the data capture window and

can be located at the beginning, the end, or anywhere within the data capture window.

Similarly, the storage qualification condition is also a Boolean combination of events that is

detected by match unit comparators that are subsequently attached to the trigger ports of

the core. However, the storage qualification condition differs from the trigger condition in

that it evaluates trigger port match unit events to decide whether or not to capture and

store each individual data sample. The trigger and storage qualification conditions can be

used together to define when to start the capture process and what data is captured.

In the ILA core example shown in Figure 1-3, page 27, suppose you want to do the

following:

•Trigger on the first memory write cycle (CE = rising edge, WE = 1, OE = 0) to Address

= 0xFF0000;

•Capture only memory read cycles (CE = rising edge, WE = 0, OE = 1) from Address =

0x23AACC where the Data values are between 0x00000000 and 0x1000FFFF;

To implement these conditions successfully, you would need to make sure that both the

TRIG0 and TRIG1 trigger ports each have two match units attached to them: one for the

trigger condition and one for the storage qualification condition. Here is how you would

set up the trigger and storage qualification equations and each individual match unit to

satisfy the conditions above:

•Trigger Condition = M0 && M2, where:

♦M0[2:0] = CE, WE, OE = “R10” (where ‘R’ means “rising edge”)

♦M2[23:0] = Address = “FF0000”

•Storage Qualification Condition = M1 && M3 && M4, where:

♦M1[2:0] = CE, WE, OE = “R10” (where ‘R’ means “rising edge”)

♦M3[23:0] = Address = “23AACC”

♦M4[31:0] = Data = in the range of 0x00000000 through 0x1000FFFF

The triggering and storage qualification capabilities of the ILA, IBA/OPB and IBA/PLB

cores allow you to locate and capture exactly the information that you want without

wasting valuable on-chip memory resources.

ILA Trigger Output Logic

The ILA core implements a trigger output port called TRIG_OUT. The TRIG_OUT port is

the output of the trigger condition that is set up at run-time using the Analyzer. The shape

(level or pulse) and sense (active-High or active-Low) of the trigger output can also be

controlled at run-time. The latency of the TRIG_OUT port relative to the input trigger ports

is 10 clock cycles.

The TRIG_OUT port is very flexible and has many uses. You can connect the TRIG_OUT

port to a device pin in order to trigger external test equipment such as oscilloscopes and

logic analyzers. Connecting the TRIG_OUT port to an interrupt line of an embedded

PowerPC™ or MicroBlaze™ processor can be used to cause a software event to occur. You

can also connect the TRIG_OUT port of one core to a trigger input port of another core in

order to expand the trigger and data capture capabilities of your on-chip debug solution.

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ChipScope Pro Cores Description

ILA Data Capture Logic

Each ILA core can capture data using on-chip block RAM resources independently from all

other cores in the design. Each ILA core can also capture data using one of two capture

modes: Window and N samples.

Window Capture Mode

In Window capture mode, the sample buffer can be divided into one or more equal-sized

sample windows. The window capture mode uses a single trigger condition event (i.e., a

Boolean combination of the individual trigger match unit events) to collect enough data to

fill a sample window.

In the case where the depth of the sample windows is a power of 2 up to 131,072 samples,

the trigger position can be set to the beginning of the sample window (trigger first, then

collect), the end of the sample window (collect until the trigger event), or anywhere in

between.

In the other case where the window depth is not a power of 2, the trigger position can only

be set to the beginning of the sample window.

Once a sample window has been filled, the trigger condition of the ILA core is

automatically re-armed and continues to monitor for trigger condition events. This process

is repeated until all sample windows of the sample buffer are filled or the user halts the

ILA core.

N Samples Capture Mode

The N Samples capture mode is similar to the Window capture mode except for two major

differences:

•The number of samples per window can be any integer N from 1 to the sample buffer

size minus 1

•The trigger position must always be at position 0 in the window

The N sample capture mode is useful for capturing the exact number of samples needed

per trigger without wasting valuable capture storage resources.

Trigger Marks

The data sample in the sample window that coincides with a trigger event is tagged with

a trigger mark. This trigger mark tells the Analyzer the position of the trigger within the

window. This trigger mark consumes one extra bit per sample in the sample buffer.

Data Port

The ILA core provides the capability to capture data on a port that is separate from the

trigger ports that are used to perform trigger functions. This feature is useful for limiting

the amount of data to be captured to a relatively small amount since it is not always useful

to capture and view the same information that is used to trigger the core.

However, in many cases it is useful to capture and view the same data that is used to

trigger the core. In this case, you can choose for the data to consist of one or more of the

trigger ports. This feature allows you to conserve resources while providing the flexibility

to choose what trigger information is interesting enough to capture.

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Chapter 1: Introduction

ILA Control and Status Logic

The ILA contains a modest amount of control and status logic that is used to maintain the

normal operation of the core. All logic necessary to properly identify and communicate

with the ILA core is implemented by this control and status logic.

IBA/OPB Core

The IBA/OPB core is a specialized logic analyzer core specifically designed to debug

embedded systems that contain the IBM CoreConnect On-Chip Peripheral Bus (OPB). The

IBA/OPB core consists of four major components:

•A protocol violation monitor:

♦Detects and reports up to 32 violations of the IBM CoreConnect OPB bus protocol

•Trigger input and output logic:

♦Trigger input logic detects OPB bus and other user-defined events

♦Trigger output logic triggers external test equipment and other logic

•Data capture logic:

♦Captures and stores trace data information using on-chip block RAM resources

•Control and status logic:

♦Manages the operation of the IBA/OPB core

Note: A description on how to generate and use the IBA/OPB core in an embedded processor

design can be found in DS282, ChipScope OPB IBA, and the EDK Platform Studio online help.

IBA/OPB Protocol Violation Monitor Logic

The IBA/OPB core includes a protocol violation monitor that can detect up to 32 different

IBM CoreConnect OPB protocol violation errors. The protocol violations that can be

detected by the IBA/OPB core are shown in Table 1-4 (which spans multiple pages).

Table 1-4: CoreConnect OPB Protocol Violation Error Description(1)

Priority Bit Encoding Error Description

1 011010 1.19.2 OPB_DBus changed state during a write

operation before receipt of OPB_xferAck.

2 011001 1.19.1 OPB_ABus changed state during an operation

before receipt of OPB_xferAck.

3 001100 1.6.1 OPB_ABus: No Mx_Select signal active and non

zero OPB_ABus.

4 001101 1.7.1 OPB_DBus: No Mx_Select signal active and non

zero OPB_DBus.

5 010101 1.13.1 OPB_xferAck: OPB_xferAck active with no

Mx_select.

6 010110 1.13.2 OPB_xferAck: OPB_xferAck did not activate

within 16 cycles of OPB_select.

7 010111 1.15.1 OPB_errAck: OPB_errAck active with no

Mx_select.

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ChipScope Pro Cores Description

8 000100 1.4.0 OPB_retry: OPB_retry and OPB_xferAck active in

the same cycle.

9 000111 1.4.3 OPB_retry: OPB_retry active for more than a

single cycle.

10 000000 1.2.1 OPB_MxGrant: More than 1 OPB_MxGrant

signals active in same cycle.

11 000001 1.2.2 OPB_MxGrant: An OPB_MxGrant signal is active

for a non-owning master.

12 000010 1.3.1

OPB_BusLock: OPB_BusLock asserted without a

grant in the previous cycle and without

OPB_select.

13 000011 1.3.2 OPB_BusLock: Bus is locked and a master other

than bus owner has been granted the bus.

14 001000 1.4.4 OPB_retry: OPB_select remained active after a

retry cycle.

15 001001 1.4.5 OPB_retry: OPB_retry active with no Mx_select.

16 001110 1.8.1

OPB_Select: Mx_Select signal active without

having control of the bus via OPB_MxGrant or

OPB_busLock.

17 001111 1.8.2 OPB_Select: More than one Mx_Select signals

active in the same cycle.

18 010000 1.9.1 OPB_RNW: OPB_RNW high with no Mx_select.

19 011011 1.19.3 OPB_RNW changed state during an operation

before receipt of OPB_xferAck.

20 011100 1.19.4 OPB_select changed state during an operation

before receipt of OPB_xferAck.

21 011101 1.19.5 OPB_BEBus changed state during a write or read

operation before receipt of OPB_xferAck.

22 011110 1.20.3 Byte enable transfer not aligned with address

offset.

23 011111 1.20.4 Byte enable transfer initiated with non

contiguous byte enables.

24 000110 1.4.2 OPB_retry: Mx_Request from retried master

remained active after a retry cycle.

25 000101 1.4.1 OPB_retry: OPB_BusLock remained active after a

retry cycle.

26 010001 1.11.1 OPB_seqAddr: OPB_seqAddr active with no

OPB_BusLock.

27 010010 1.11.2 OPB_seqAddr: OPB_seqAddr active with no

Mx_select.

Table 1-4: CoreConnect OPB Protocol Violation Error Description(1)

Priority Bit Encoding Error Description

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Chapter 1: Introduction

The protocol violation monitor detects and reports any errors that occur on the OPB bus.

The error is reported as a 6-bit priority-encoded value that can be used as both trigger and

data to the IBA/OPB core. Priority 1 is the highest priority error and masks any other

lower priority errors, etc.

IBA/OPB Trigger Input Logic

The IBA core for the IBM CoreConnect On-Chip Peripheral Bus (IBA/OPB) is used to

monitor the CoreConnect OPB bus of embedded MicroBlaze soft processor, or

Virtex-II Pro, Virtex-4 FX, and Virtex-5 FXT PowerPC hard processor systems. Up to 16

different trigger groups can be monitored by the IBA/OPB core at any given time. The OPB

signal groups that can be monitored are described in Table 1-5, page 33 (which spans

multiple pages).

The IBA/OPB core can also implement the same trigger and storage qualification

condition equations as the ILA core. These features are described in the section called “ILA

Trigger Input Logic,” page 24.

IBA/OPB Trigger Output Logic

The IBA/OPB core implements a trigger output port called TRIG_OUT. The TRIG_OUT

port is the output of the trigger condition that is set up at run-time using the Analyzer. The

latency of the TRIG_OUT port relative to the input trigger ports is 15 clock cycles.

The TRIG_OUT port is very flexible and has many uses. For example, you can:

•Connect the TRIG_OUT port to a device pin in order to trigger external test

equipment such as oscilloscopes and logic analyzers

•Connect the TRIG_OUT port to an interrupt line of an embedded PowerPC or

MicroBlaze processor to cause a software event to occur

•Connect the TRIG_OUT port of one core to a trigger input port of another core in

order to expand the trigger and data capture capabilities of your on-chip debug

solution

28 010011 1.11.3 OPB_seqAddr: OPB_ABUS did not increment

properly during OPB_seqAddr.

29 010100 1.11.4 OPB_seqAddr: OPB_seqAddr was asserted

without a transaction boundary.

30 011000 1.16.1 OPB_ToutSup: OPB_ToutSup active with no

Mx_select.

31 001010 1.5.1 OPB_Timeout: Arbiter failed to signal

OPB_Timeout after 16 non-responding cycles.

32 001011 1.5.2 OPB_Timeout: OPB_Timeout active with no

Mx_select.

33 111111 – No errors.

Notes:

1. Refer to the OPB Bus Functional Model Toolkit User’s Manual document from IBM for more information

on these CoreConnect OPB errors.

Table 1-4: CoreConnect OPB Protocol Violation Error Description(1)

Priority Bit Encoding Error Description

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ChipScope Pro Cores Description

Table 1-5: OPB Signal Groups

Trigger Group Name Width Description

OPB_CTRL 17

OPB combined control signals, including:

•SYS_Rst

•Debug_SYS_Rst

•WDT_Rst

•OPB_Rst

•OPB_BE[3]

•OPB_BE[2]

•OPB_BE[1]

•OPB_BE[0]

•OPB_select

•OPB_xferAck

•OPB_RNW

•OPB_errAck

•OPB_timeout

•OPB_toutSup

•OPB_retry

•OPB_seqAddr

•OPB_busLock

OPB_ABUS 32 OPB address bus

OPB_DBUS 32 OPB combined data bus (logical OR of read and

write data buses)

OPB_RDDBUS 32 OPB read data bus (from slaves)

OPB_WRDBUS 32 OPB write data bus (to slaves)

OPB_Mn_CTRL 11

OPB control signals for master n, including:

•Mn_request

•OPB_MnGrant

•OPB_pendReqn

•Mn_busLock

•Mn_BE[3]

•Mn_BE[2]

•Mn_BE[1]

•Mn_BE[0]

•Mn_select

•Mn_RNW

•Mn_seqAddr

where n is the master number (0 to 15)

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Chapter 1: Introduction

The IBA/OPB core can monitor not only CoreConnect OPB bus signals, but can also

monitor generic design signals (using the TRIG_IN trigger group). This capability allows

the user to correlate events that are occurring on the CoreConnect OPB bus with events

elsewhere in the design. The IBA/OPB core can also be connected to other capture cores

using the TRIG_IN and TRIG_OUT port signals to perform cross-triggering operations

while monitoring different parts of the design.

IBA/OPB Data Capture Logic

The data capture logic capabilities of the IBA/OPB core are identical to those of the ILA

core. These features are described in “ILA Data Capture Logic,” page 29.

IBA/OPB Control and Status Logic

The IBA/OPB contains a modest amount of control and status logic that is used to

maintain the normal operation of the core. All logic necessary to properly identify and

communicate with the IBA/OPB core is implemented by this control and status logic.

OPB_SLm_CTRL 4

OPB control signals slave m, including:

•Slm_xferAck

•Slm_errAck

•Slm_toutSup

•Slm_retry

where m is the slave number (0 to 63)

OPB_PV 6 OPB protocol violation signals

TRIG_IN User-defined Generic trigger input

Table 1-5: OPB Signal Groups

Trigger Group Name Width Description

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ChipScope Pro Cores Description

IBA/PLB Core

The IBA/PLB core is a specialized logic analyzer core specifically designed to debug

embedded systems that contain the IBM CoreConnect Processor Local Bus (PLB).

Note: The IBA/PLB core is used only for PLB versions prior to PLB v46. For PLB v46 buses, a

customized ILA core (chipscope_plbv46_iba) is attached to the PLB v46 bus using the Xilinx Platform

Studio tool.

The IBA/PLB core consists of three major parts components:

•Trigger input and output logic:

♦Trigger input logic detects PLB bus and other user-defined events

♦Trigger output logic triggers external test equipment and other logic

•Data capture logic:

♦Captures and stores trace data information using on-chip block RAM resources

•Control and status logic:

♦Manages the operation of the IBA/PLB core

Note: A description on how to generate and use the IBA/PLB core in an embedded processor

design can be found in DS283, ChipScope PLB IBA, and the EDK Platform Studio online help.

IBA/PLB Trigger Input Logic

The IBA core for the IBM CoreConnect Processor Local Bus (IBA/PLB) is used to monitor

the PLB bus of embedded MicroBlaze soft processor or Virtex-II Pro, and Virtex-4 FX, and

Virtex-5 FXT PowerPC hard processor systems. Up to 16 different trigger groups can be

monitored by the IBA/PLB core at any given time. The types of PLB signal groups that can

be monitored are described in Table 1-6, page 36 (which spans multiple pages).

The IBA/PLB core can also monitor other generic design signals (using the TRIG_IN

trigger group) in addition to the PLB bus signals. This capability allows the user to

correlate events that are occurring on the PLB bus with events elsewhere in the design. The

IBA/PLB core can also be connected to other capture cores using the TRIG_IN and

TRIG_OUT port signals to perform cross-triggering operations while monitoring different

parts of the design.

The IBA/PLB core is also able to implement the same trigger and storage qualification

condition equations as the ILA core. These features are described in the section called “ILA

Trigger Input Logic,” page 24.

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Chapter 1: Introduction

Table 1-6: PLB Signal Groups

Trigger Group Name Width Description

PLB_CTRL 26

PLB bus control signals, including:

•SYS_plbReset

•PLB_abort

•PLB_BE(0)

•PLB_BE(1)

•PLB_BE(2)

•PLB_BE(3)

•PLB_BE(4)

•PLB_BE(5)

•PLB_BE(6)

•PLB_BE(7)

•PLB_busLock

•PLB_masterID(0)

•PLB_masterID(1)

•PLB_masterID(2)

•PLB_masterID(3)

•PLB_Msize(0)

•PLB_Msize(1)

•PLB_PAValid

•PLB_SAValid

•PLB_rdPrim

•PLB_RNW

•PLB_size(0)

•PLB_size(1)

•PLB_size(2)

•PLB_size(3)

•PLB_wrPrim

PLB_ABUS 32 PLB address bus

PLB_RDDBUS 64 PLB read data bus (from slaves)

PLB_WRDBUS 64 PLB write data bus (to slaves)

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ChipScope Pro Cores Description

PLB_Mn_CTRL 32

PLB control signals for master n, including:

•PLB_MnAddrAck

•PLB_Mn_Busy

•PLB_Mn_Err

•PLB_MnRdDAck

•PLB_MnRdWdAddr(0)

•PLB_MnRdWdAddr(1)

•PLB_MnRdWdAddr(2)

•PLB_MnRdWdAddr(3)

•PLB_MnRearbitrate

•PLB_MnSSize(0)

•PLB_MnSSize(1)

•PLB_Mn_WrDAck

•Mn_abort

•Mn_BE(0)

•Mn_BE(1)

•Mn_BE(2)

•Mn_BE(3)

•Mn_BE(4)

•Mn_BE(5)

•Mn_BE(6)

•Mn_BE(7)

•Mn_busLock

•Mn_MSize(0)

•Mn_MSize(1)

•Mn_priority(0)

•Mn_priority(1)

•Mn_request

•Mn_RNW

•Mn_size(0)

•Mn_size(1)

•Mn_size(2)

•Mn_size(3)

where n is the master number (0 to 15)

Table 1-6: PLB Signal Groups

Trigger Group Name Width Description

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IBA/PLB Trigger Output Logic

The IBA/PLB core implements a trigger output port called TRIG_OUT. The TRIG_OUT

port is the output of the trigger condition that is set up at run-time using the Analyzer. The

latency of the TRIG_OUT port relative to the input trigger ports is 10 clock cycles.

The TRIG_OUT port is very flexible and has many uses. You can connect the TRIG_OUT

port to a device pin in order to trigger external test equipment such as oscilloscopes and

logic analyzers. Connecting the TRIG_OUT to an interrupt line of an embedded

PowerPC 405 or MicroBlaze processor can be used to cause a software event to occur. You

can also connect the TRIG_OUT port of one core to a trigger input port of another core in

order to expand the trigger and data capture capabilities of your on-chip debug solution.

IBA/PLB Data Capture Logic

The data capture capabilities of the IBA/PLB core are identical to those of the ILA core.

These features are described in “ILA Data Capture Logic,” page 29.

IBA/PLB Control and Status Logic

The IBA/PLB core contains a modest amount of control and status logic that is used to

maintain the normal operation of the core. All logic necessary to properly identify and

communicate with the IBA/PLB core is implemented by this control and status logic.

PLB_SLm_CTRL 12

PLB control signals slave m, including:

•Slm_addrAck

•Slm_rdDAck

•Slm_rdWdAddr(0)

•Slm_rdWdAddr(1)

•Slm_rdWdAddr(2)

•Slm_rdWdAddr(3)

•Slm_rearbitrate

•Slm_SSize(0)

•Slm_SSize(1)

•Slm_wait

•Slm_wrComp

•Slm_wrDAck

where m is the slave number (0 to 15)

TRIG_IN User-defined Generic trigger input

Table 1-6: PLB Signal Groups

Trigger Group Name Width Description

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ChipScope Pro Cores Description

VIO Core

The Virtual Input/Output (VIO) core is a customizable core that can both monitor and

drive internal FPGA signals in real time. Unlike the ILA and IBA cores, no on- or off-chip

RAM is required. Four kinds of signals are available in a the VIO core:

•Asynchronous inputs:

♦These are sampled using the JTAG clock signal that is driven from the JTAG cable.

♦The input values are read back periodically and displayed in the Analyzer.

•Synchronous inputs:

♦These are sampled using the design clock.

♦The input values are read back periodically and displayed in the Analyzer.

•Asynchronous outputs:

♦These are defined by the user in the Analyzer and driven out of the core to the

surrounding design.

♦A logical 1 or 0 value can be defined for individual asynchronous outputs.

•Synchronous outputs:

♦These are defined by the user in the Analyzer, synchronized to the design clock and

driven out of the core to the surrounding design.

♦A logical 1 or 0 can be defined for individual synchronous outputs. Pulse trains of

16 clock cycles worth of 1’s and/or 0’s can also be defined for synchronous

outputs.

Activity Detectors

Every VIO core input has additional cells to capture the presence of transitions on the

input. Since the design clock will most likely be much faster than the sample period of the

Analyzer, it's possible for the signal being monitored to transition many times between

successive samples. The activity detectors capture this behavior and the results are

displayed along with the value in the Analyzer.

In the case of a synchronous input, activity cells capable of monitoring for asynchronous

and synchronous events are used. This feature can be used to detect glitches as well as

synchronous transitions on the synchronous input signal.

Pulse Trains

Every VIO synchronous output has the ability to output a static 1, a static 0, or a pulse train

of successive values. A pulse train is a 16-clock cycle sequence of 1's and 0's that drive out

of the core on successive design clock cycles. The pulse train sequence is defined in the

Analyzer and is executed only one time after it is loaded into the core.

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Chapter 1: Introduction

ATC2 Core

The Agilent Trace Core 2 (ATC2) is a customizable debug capture core that is specially

designed to work with the latest generation Agilent logic analyzers. The ATC2 core

provides external Agilent logic analyzers access to internal FPGA design nets (as shown in

Figure 1-4).

ATC2 Data Path Description

The data path of the ATC2 core consists of:

•Up to 64 run-time selectable input signal banks that connect to the user’s FPGA

design

•Up to 128 output data pins that connect to an Agilent logic analyzer’s probe

connectors

•Optional 2x time-division multiplexing (TDM) available on each output data pin that

can be used to double the width of each individual signal bank from 128 to 256 bits

•Supports both asynchronous timing and synchronous state capture modes

•Supports any valid I/O standard, drive strength, and output slew rate on each output

data pin on an individual pin-by-pin basis

•Supports any Agilent probe connection technology (for more information, see

http://www.agilent.com/find/logic)

The maximum number of data probe points available at run time is calculated as:

(64 data ports) * (128 bits per data port) * (2x TDM) = 16,384 probe points.

ATC2 Core Data Capture and Run-Time Control

The external Agilent logic analyzer is used to trigger on and capture the data that passes

through the ATC2 core. This allows you to take full advantage of the complex triggering,

deep trace memory, and system-level data correlation features of the Agilent logic analyzer

as well as the increased visibility of internal design nodes provided by the ATC2 core. The

Agilent logic analyzer is also used to control the run-time selection of the active data port

by communicating with the ATC2 core via a JTAG port connection (as shown in

Figure 1-4).

X-Ref Target - Figure 1-4

Figure 1-4: ATC2 Core and System Block Diagram

1 to 32 Banks

1x or 2x TDM

Probe

Connector

ICON Core

ATC2 Core

FPGA

PCB

User

Design

256

256 128

256

JTAG Cable

JTAG

Agilent Logic Analyzer

LPT or USB

Probes

UG029_atc2_block_diagram_020904

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Synthesis Requirements

IBERT Core

The Integrated Bit Error Ratio Tester (IBERT) core and related software to provide access to

the RocketIO multi-gigabit transceivers (MGTs) and perform bit error ratio analysis on

channels composed of these MGTs. The IBERT core is part of the ChipScope Pro Serial I/O

Toolkit and is used to debug, verify, and optimize MGT communication channels. See

UG213, ChipScope Pro 10.1 Serial I/O Toolkit User Guide at

http://www.xilinx.com/literature/literature-chipscope.htm for detailed documentation

on the features and capabilities of the tools that are specific to the exploration and debug of

designs that use the high-speed serial I/O capability of Xilinx FPGAs.

Synthesis Requirements

Users can modify many options in the ILA, IBA/OPB, IBA/PLB, VIO, and ATC2 cores

without resynthesizing. However, after changing selectable parameters (such as width of

the data port or the depth of the sample buffer), the design must be resynthesized with

new cores. Table 1-7 shows which design changes require resynthesizing.

System Requirements

Software Tools Requirements

The Xilinx CORE Generator, Core Inserter, IBERT Core Generator, and CseJTAG/Tcl tools

require that ISE 10.1 implementation tools be installed on your system. (Tcl stands for Tool

Command Language and a Tcl shell is a shell program that is used to run Tcl scripts.)

CseJTAG/Tcl requires the Tcl shell that is included in the ISE 10.1 tool installation

($XILINX/bin/nt/xtclsh.exe).

Table 1-7: Design Parameter Changes Requiring Resynthesis

Design Parameter Change Resynthesis Required

Change trigger pattern No

Running and stopping the trigger No

Enabling the external triggers No

Changing the trigger signal source No(1)

Changing the data signal source No(1)

Changing the ILA clock signal Yes

Changing the sample buffer depth Yes

Notes:

1. The ability to change existing trigger and/or data signal source is supported by the ISE 10.1 FPGA

Editor.

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Chapter 1: Introduction

Communications Requirements

The Analyzer supports the following download cables (see Table 1-8, page 42) for

communication between the PC and the devices in the JTAG Boundary Scan chain:

•Platform Cable USB

•Parallel Cable IV

•Parallel Cable III

•MultiPRO

Table 1-8: ChipScope Pro Download Cable Support

Download Cable Features

Platform Cable USB(1)

•Uses the USB port (USB 2.0 or USB 1.1) to communicate

with the Boundary Scan chain of the board-under-test

•Downloads at speeds up to 24 Mb/s throughput

•Contains an adjustable voltage interface that enables it to

communicate with systems and device I/Os operating at 5V

down to 1.5V

•Windows and Linux OS support

Parallel Cable IV(1)

•Uses the parallel port (i.e., printer port) to communicate

with the Boundary Scan chain of the board-under-test

•Downloads at speeds up to 5 Mb/s throughput

•Contains an adjustable voltage interface that enables it to

communicate with systems and device I/Os operating at 5V

down to 1.5V

•Windows and Linux OS support

Parallel Cable III

•Uses the parallel port (i.e., printer port) to communicate

with the Boundary Scan chain of the board-under-test

•Downloads at speeds up to 500 kb/s throughput

•Contains an adjustable voltage interface that enables it to

communicate with systems and device I/Os operating at 5V

down to 2.5V

•Windows and Linux OS support

MultiPRO Cable

•Uses the parallel port (i.e., printer port) to communicate

with the Boundary Scan chain of the board-under-test

•Downloads at speeds up to 5 Mb/s throughput

•Contains an adjustable voltage interface that enables it to

communicate with systems and device I/Os operating at 5V

down to 1.5V

•Windows OS support only

Notes:

1. The Parallel Cable IV, Platform Cable USB, and MultiPRO cables are available for purchase from the

Xilinx Online Store (from www.xilinx.com choose Online Store → Programming Cables).

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System Requirements

Board Requirements

For the Analyzer and download cable to work properly with the board-under-test, the

following board-level requirements must be met:

•One or more supported devices must be connected to a JTAG header that contains the

TDI, TMS, TCK, and TDO pins

•If another device would normally drive the TDI, TMS, or TDI pins of the JTAG chain

containing the target device(s), then jumpers on these signals are required to disable

these sources, preventing contention with the download cable

•If using the Parallel Cable III download cable, then VCC (2.5V-5.0V) and GND headers

must be available for powering the Parallel Cable III cable

•If using the Parallel Cable IV, MultiPRO, or Platform Cable USB download cable, then

VREF (1.5-5.0V) and GND headers must be available for connecting to the Parallel

Cable IV cable

Host System Requirements for Microsoft Windows

The Xilinx CORE Generator, IBERT Core Generator, Core Inserter, and Analyzer (client and

server modes) tools run on PC systems running the Microsoft Windows operating system

and meet the requirements outlined in Table 1-9.

Host System Requirements for Linux

The Xilinx CORE Generator, IBERT Core Generator, Core Inserter, and Analyzer tools run

on workstation systems running the Linux operating system and meet the requirements

outlined in Table 1-10.

Note: The Linux version of the 10.1 IBERT Core Generator, Core Inserter, Analyzer, and

CseJTAG/Tcl tools require that the ISE 10.1 tools are installed on the target system and that the

$XILINX environment variable is set up correctly.

Table 1-9: PC System Requirements for ChipScope Pro 10.1 Tools

OS Version Memory Java Environment

Windows XP

Professional 32-bit

64-bit 1024 MB

Java Run-time Environment version 1.5.0

(automatically included in ChipScope Pro

10.1 software installation)

Windows Vista

Business

Table 1-10: Linux Requirements for ChipScope Pro 9.2i Tools

OS Version

Memory Java Environment

Red Hat Enterprise

Linux

4 WS 32-bit

1024 MB

Java Run-time Environment version 1.5.0

(automatically included in ChipScope Pro 10.1

software installation)

5 WS

4 WS 64-bit

5 WS

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Chapter 1: Introduction

Software Installation and Licensing

For ChipScope Pro software installation and licensing instructions, refer to the ISE 10.1

Design Suite Release Notes and Installation Guide available in the ISE Documentation at

http://www.xilinx.com/support.

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UG029 (v10.1) March 24, 2008

Chapter 2

Using the CORE Generator Tool

CORE Generator Tool Overview

The Xilinx CORE Generator tool is used to generate the following cores:

•Integrated Controller (ICON)

•Integrated Logic Analyzer (ILA)

•Virtual Input/Output (VIO)

•Agilent Trace Core 2 (ATC2)

As a group, these cores are called the ChipScope Pro cores. After generating the cores, you

can use the instantiation templates (that are provided) to quickly and easily insert the cores

into their VHDL or Verilog design. After completing the instantiation and running

synthesis, you can implement the design using the ISE 10.1 implementation tools.

For more information on generating and using the:

•IBERT core, see UG213, ChipScope Pro Serial I/O Toolkit User Guide at

www.xilinx.com/literature/literature-chipscope.htm.

•IBA/OPB core in an imbedded processor design, see DS282, ChipScope OPB IBA, and

the EDK Platform Studio online help.

•IBA/PLB core in an embedded processor design, see DS283, ChipScope PLB IBA, and

the EDK Platform Studio online help.

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Chapter 2: Using the CORE Generator Tool

Locating the ChipScope Pro Cores in CORE Generator

Before you can select the ChipScope Pro cores for generation, you first need to set up a

CORE Generator project. After setting up your CORE Generator project with the

appropriate settings, you can find the ChipScope Pro cores in the CORE Generator by first

clicking on the View by Function tab in the upper left panel, then by expanding the Debug

& Verification and ChipScope Pro sections of the browser (see Figure 2-1). You can also

find the ChipScope Pro cores by using the View by Name tab.

X-Ref Target - Figure 2-1

Figure 2-1: Locating the ChipScope Pro Cores in CORE Generator

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Generating an ICON Core

The CORE Generator tool provides the ability to define and generate a customized ICON

core to use with one or more ILA, IBA/OPB, IBA/PLB, VIO, or ATC2 capture cores in HDL

designs. You can customize control ports (that is, the number of cores to be connected to

the ICON core) and customize the use of the Boundary Scan primitive component (for

example, BSCAN_VIRTEX2) that is used for JTAG communication.

After the CORE Generator tool validates the user-defined parameters, it generates a XST

netlist (*.ngc) and other files specific to the HDL language and synthesis tool associated

with the CORE Generator project. You can easily generate the netlist and code examples

for use in normal FPGA design flows.

The CORE Generator tool offers the choice to generate either an ICON, ILA, VIO, or ATC2

core. Select ICON (ChipScope Pro - Integrated Controller) core (Figure 2-2), and click the

Customize link in the right side of the window.

X-Ref Target - Figure 2-2

Figure 2-2: Selecting the ICON Core

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General ICON Core Parameters

The CORE Generator tool is used to set up the ICON core parameters (Figure 2-3).

Entering the Component Name

The Component Name field is can consist of any combination of alpha-numeric characters

in addition to the underscore symbol. However, the underscore symbol cannot be the first

character in the component name.

Entering the Number of Control Ports

The ICON core can communicate with up to 15 ILA, IBA/OPB, IBA/PLB, VIO, and ATC2

capture core units at any given time. However, individual capture core units cannot share

their control ports with any other unit. Therefore, the ICON core needs up to 15 distinct

control ports to handle this requirement. You can select the number of control ports from

the Number of Control Ports pull-down list.

Disabling the Boundary Scan Component Instance

The Boundary Scan primitive component (for example, BSCAN_VIRTEX2) is used to

communicate with the JTAG Boundary Scan logic of the target FPGA device. The

Boundary Scan component extends the JTAG test access port (TAP) interface of the FPGA

device so that up to four internal scan chains can be created. The Analyzer communicates

with the cores by using one of the internal scan chains (USER1, USER2, USER3, or USER4,

depending on the device family) provided by the Boundary Scan component.

Since cores do not use both internal scan chains of the Boundary Scan component, it is

possible to share the Boundary Scan component with other elements in the user’s design.

The Boundary Scan component can be shared with other parts of the design by using one

of two methods:

•Instantiate the Boundary Scan component inside the ICON core and include the

unused Boundary Scan scan chain signals as port signals on the ICON core interface.

X-Ref Target - Figure 2-3

Figure 2-3: ICON Core Parameters

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Generating an ICON Core

•Instantiate the Boundary Scan component somewhere else in the design and attach

either the USER1 or USER2 scan chain signals to corresponding port signals the ICON

core interface.

Note: This feature is not available for Virtex-4 and Virtex-5 devices since the BSCAN_VIRTEX

primitive in these devices only has a single USER scan port per instance.

The Boundary Scan component is instantiated inside the ICON core by default. Use the

Disable Boundary Scan Component Instance checkbox to disable the instantiation of the

Boundary Scan component.

Selecting the Boundary Scan Chain

The Analyzer can communicate with the cores using either the USER1, USER2, USER3, or

USER4 boundary scan chains. If the Boundary Scan component is instantiated inside the

ICON core, then you can select the desired scan chain from the Boundary Scan Chain pull-

down list.

Disabling JTAG Clock BUFG Insertion

If the Boundary Scan component is instantiated inside the ICON core, then it is possible to

disable the insertion of a BUFG component on the JTAG clock signal. Disabling the JTAG

clock BUFG insertion causes the implementation tools to route the JTAG clock using

normal routing resources instead of global clock routing resources. By default, this clock is

placed on a global clock resource (BUFG). To disable this BUFG insertion, check select the

Disable JTAG Clock BUFG Insertion checkbox. This should only be done if global

resources are very scarce; placing the JTAG clock on regular routing, even high-speed

backbone routing, introduces skew. Make sure the design is adequately constrained to

minimize this skew.

Enabling Unused Boundary Scan Ports

The Boundary Scan primitive for Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Spartan-II,

Spartan-IIE, Spartan-3, Spartan-3E, Spartan-3A, and Spartan-3A DSP devices (including

the QPro variants of these families) always has two sets of ports: USER1 and USER2.

The Boundary Scan primitive for Virtex-4 and Virtex-5 devices can have only one of four

sets of ports enabled at any given time: USER1, USER2, USER3, and USER4. These ports

provide an interface to the Boundary Scan TAP controller of the FPGA device.

The ICON core uses only one of the USER* scan chain ports for communication purposes,

therefore, the unused USER* port signals are available for use by other design elements,

respectively. If the Boundary Scan component is instantiated inside the ICON core, then

selecting the Enable Unused Boundary Scan Ports checkbox provides access to the

unused USER* scan chain interfaces of the Boundary Scan component.

Note: The Boundary Scan ports should be included only if the design needs them. If they are

included and not used, some synthesis tools do not connect the ICON core properly, causing errors

during the synthesis and implementation stages of development.

Note: This feature is not available for Virtex-4 and Virtex-5 devices because the BSCAN_VIRTEX

primitive in these devices only has a single USER scan port per instance.

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Generating the Core

After entering the ICON core parameters, click Finish to create the ICON core files. While

the ICON core is being generated, a progress indicator will appear. Depending on the host

computer system, it may take several minutes for the ICON core generation to complete.

After the ICON core has been generated, a list of files that are generated will appear in a

separate window (see Figure 2-4).

Using the ICON Core

To instantiate the example ICON core HDL files into your design, use the following

guidelines to connect the ICON core port signals to various signals in your design:

•Connect one of the ICON core’s unused CONTROL* port signals to a control port of

only one ILA, IBA/OPB, IBA/PLB, VIO, or ATC2 core instance in the design

•Do not leave any unused CONTROL* ports of the ICON core unconnected as this will

cause the implementation tools to report an error. Instead, use an ICON core with the

same number of CONTROL* ports as you have ILA, IBA/OPB, IBA/PLB, VIO or

ATC2 cores

X-Ref Target - Figure 2-4

Figure 2-4: List of Generated ICON Core Files

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Generating an ILA Core

The CORE Generator tool provides the ability to define and generate a customized ILA

capture core to use with HDL designs. You can customize the number, width, and

capabilities of the trigger ports. You can also customize the maximum number of data

samples stored by the ILA core, and the width of the data samples (if different from the

trigger ports).

After the CORE Generator tool validates the user-defined parameters, it generates a XST

netlist (*.ngc) and other files specific to the HDL language and synthesis tool associated

with the CORE Generator project. You can easily generate the netlist and code examples

for use in normal FPGA design flows.

The CORE Generator offers the choice to generate either an ICON, ILA, VIO, or ATC2 core.

Select ILA (ChipScope Pro - Integrated Logic Analyzer), and click the Customize link on

the right side of the window (Figure 2-5).

X-Ref Target - Figure 2-5

Figure 2-5: Selecting the ILA Core

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ILA Core Trigger and Storage Parameters

The CORE Generator tool is used to set up the ILA core parameters, including the general

trigger and storage parameters (Figure 2-6) and the trigger port parameters (Figure 2-8,

page 55).

Entering the Component Name

The Component Name field is can consist of any combination of alpha-numeric characters

in addition to the underscore symbol. However, the underscore symbol cannot be the first

character in the component name.

Selecting the Number of Trigger Ports

Each ILA core can have up to 16 separate trigger ports that can be set up independently.

After you choose a number from the Number of Trigger Ports pull-down list, a group of

options appears for each trigger port. The group of options associated with each trigger

port is labeled with TRIGn, where n is the trigger port number 0 to 15. The trigger port

options include trigger width, number of match units connected to the trigger port, and the

type of these match units.

X-Ref Target - Figure 2-6

Figure 2-6: ILA Core Trigger and Storage Parameters

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Enabling the Trigger Condition Sequencer

The trigger condition sequencer can be either a Boolean equation, or an optional trigger

sequencer that is controlled by the Max Sequence Levels pull-down list. A block diagram

of the trigger sequencer is shown in Figure 2-7.

The trigger sequencer is implemented as a simple cyclical state machine and can transition

through up to 16 states or levels before the trigger condition is satisfied. The transition

from one level to the next is caused by an event on one of the match units that is connected

to the trigger sequencer. Any match unit can be selected at run time on a per level basis to

transition from one level to the next. The trigger sequencer can be configured at run time to

transition from one level to the next on either contiguous or non-contiguous sequences of

match function events.

Using RPMs

The ILA core normally uses relationally placed macros (RPMs) to increase the performance

of the core. If the device family is Virtex-II, Virtex-II Pro, Virtex-4, Virtex-5, Spartan-3,

Spartan-3E, Spartan-3A, or Spartan-3A DSP (including the QPro variants of these families),

the usage of RPMs by the ILA core can be disabled by deselecting the Use RPMs checkbox.

It is recommended that the Use RPMs checkbox remain enabled for these device families.

Note: RPMs cannot be used with the Virtex, Virtex-E, Spartan-II, or Spartan-IIE device families

(including the QPro variants of these families).

Enabling the Trigger Output Port

The output of the ILA trigger condition module can be brought out to a port signal by

checking the Enable Trigger Output Port checkbox. The trigger output port is used to

trigger external test equipment by attaching the port signal to a device pin in the HDL

design. The trigger output port can also be attached to other logic or cores in the design to

be used as a trigger, an interrupt, or another control signal. The shape (level or pulse) and

sense (active-High or active-Low) of the trigger output can also be controlled at run-time

using the Analyzer tool. The clock latency of the ILA trigger output port is 10 clock (CLK)

cycles with respect to the trigger input ports. The Trigger Output port is reset upon

successful uploading of ILA data and/or the re-arming of the ILA core trigger logic.

Selecting the Clock Edge

The ILA unit can use either the rising or falling edges of the CLK signal to trigger and

capture data. The Sample On pull-down list is used to select either the rising or falling

edge of the CLK signal as the clock source for the ILA core.

X-Ref Target - Figure 2-7

Figure 2-7: Trigger Sequencer Block Diagram (with 16 levels and 16 match units)

Match Unit 0

Match Unit 1

Match Unit 2

Match Unit 15

Level

Match Unit 0

Match Unit 1

Match Unit 2

Match Unit 15

Level

Match Unit 0

Match Unit 1

Match Unit 2

Match Unit 15

Level

Tr i g

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Selecting the Sample Data Depth

The maximum number of data sample words that the ILA core can store in the sample

buffer is controlled by the Sample Data Depth pull-down list. The sample data depth

determines the number of data width bits contributed by each block RAM unit used by the

ILA unit.

Enabling the Storage Qualification Condition

In addition to the trigger condition, the ILA core can also implement a storage qualification

condition. The storage qualification condition is a Boolean combination of match function

events. These match function events are detected by the match unit comparators that are

subsequently attached to the trigger ports of the core. The storage qualification condition

differs from the trigger condition in that it evaluates trigger port match unit events to

decide whether or not to capture and store each individual data sample. The trigger and

storage qualification conditions can be used together to define when to start the capture

process and what data to capture. The storage qualification condition can be enabled by

checking the Enable Storage Qualification checkbox.

Selecting the Data Type

The data captured by the ILA trigger port can come from two different source types and is

controlled by the Data Same as Trigger checkbox:

•Data Same as Trigger (checked ON)

♦The data and trigger ports are identical. This mode is very common in most logic

analyzers, since you can capture and collect any data used to trigger the core.

♦Individual trigger ports can be selected to be excluded from the data port (see

Figure 2-8, page 55). If this selection is made, then the DATA input port will not be

included in the port map of the ILA core.

♦This mode conserves CLB and routing resources in the ILA core, but is limited to

a maximum aggregate data sample word width of 256 bits (or 1,024 bits for

Virtex-5 devices).

•Data Not Same as Trigger (checked OFF)

♦The data port is completely independent of the trigger ports.

♦This mode is useful when you want to limit the amount of data being captured.

♦In the case of data not same as trigger, the Data Port Width parameter needs to be

specified.

Entering the Data Port Width

The width of each data sample word stored by the ILA core is called the data width. If the

data and trigger words are independent from each other, then the maximum allowable

data width depends on the target device type and data depth. However, regardless of these

factors, the maximum allowable data width is 256 bits (or 1,024 bits for Virtex-5 devices).

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ILA Core Trigger Port Parameters

After you have set up the trigger and storage ILA core options, click Next. This takes you

to the screen in the ILA core CORE Generator tool that is used to set up the trigger port

options (Figure 2-8). A separate panel is used to specify the parameters for trigger port

enabled using the Number of Trigger Ports pull-down list shown in Figure 2-6, page 52.

Entering the Width of the Trigger Ports

The individual trigger ports are buses that are made up of individual signals or bits. The

number of bits used to compose a trigger port is called the trigger width. The width of each

trigger port can be set independently using the Trigger Port Width field. The range of

values that can be used for trigger port widths is 1 to 256.

Selecting the Number of Trigger Match Units

A match unit is a comparator that is connected to a trigger port and is used to detect events

on that trigger port. The results of one or more match units are combined together to form

what is called the overall trigger condition event that is used to control the capturing of

data. Each trigger port TRIGn can be connected to 1 to 16 match units by using the Match

Units pull-down list.

Selecting one match unit conserves resources while still allowing some flexibility in

detecting trigger events. Selecting two or more trigger match units allows a more flexible

trigger condition equation to be a combination of multiple match units. However,

increasing the number of match units per trigger port also increases the usage of logic

resources accordingly.

Note: The aggregate number of match units used in a single ILA core cannot exceed 16, regardless

of the number of trigger ports used.

X-Ref Target - Figure 2-8

Figure 2-8: ILA Core Trigger Port Options

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Selecting Match Unit Counter Width

The match unit counter is a configurable counter on the output of the each match unit in a

trigger port. This counter can be configured at run time to count a specific number of

match unit events. To include a match counter on each match unit in the trigger port, select

a counter width from 1 to 32. The match counter will not be included on each match unit if

the Counter Width pull-down list is set to Disabled. The default counter width setting is

Disabled.

Selecting the Match Unit Type

The different comparisons or match functions that can be performed by the trigger port

match units depend on the type of the match unit. Six types of match units are supported

by the ILA cores (Table 2-1, which spans multiple pages).

Use the Match Type pull-down list to select the type of match unit that applies to all match

units connected to the trigger port. However, as the functionality of the match unit

Table 2-1: ILA Trigger Match Unit Types

Type Bit

Values (1) Match Function Bits Per

Slice(2) Description

Basic 0, 1, X ‘=’, ‘<>’ Virtex-5: 19

All others: 8

Can be used for comparing data

signals where transition

detection is not important. This is

the most bit-wise economical

type of match unit.

Basic

w/edges

0, 1, X, R,

F, B ‘=’, ‘<>’ Virtex-5: 8

All others: 4

Can be used for comparing

control signals where transition

detection (e.g., low-to-high,

high-to-low, etc.) is important.

Extended 0, 1, X ‘=’, ‘<>’, ‘>’,

‘>=’, ‘<‘, ‘<=’

Virtex-5: 16

All others: 2

Can be used for comparing

address or data signals where

magnitude is important.

Extended

w/edges

0, 1, X, R,

F, B

‘=’, ‘<>’, ‘>’,

‘>=’, ‘<‘, ‘<=’

Virtex-5: 8

All others: 2

Can be used for comparing

address or data signals where a

magnitude and transition

detection are important.

Range 0, 1, X

‘=’, ‘<>’, ‘>’,

‘>=’, ‘<‘, ‘<=’,

‘in range’,

‘not in range’

Virtex-5: 8

All others: 1

Can be used for comparing

address or data signals where a

range of values is important.

Range

w/edges

0, 1, X, R,

F, B

‘=’, ‘<>’, ‘>’,

‘>=’, ‘<‘, ‘<=’,

‘in range’,

‘not in range’

Virtex-5: 4

All others: 1

Can be used for comparing

address or data signals where a

range of values and transition

detection are important.

Notes:

1. Bit values: ’0’ means “logical 0”, ‘1’ means “logical 1”, ‘X’ means “don’t care”, ‘R’ means “0-to-1

transition”, ‘F’ means “1-to-0 transition”, and ‘B’ means “any transition”

2. The Bits Per Slice value is only an approximation that is used to illustrate the relative resource

utilization of the different match unit types. It should not be used as a hard estimate of resource

utilization

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Generating an ILA Core

increases, so does the amount of resources necessary to implement that functionality. This

flexibility allows you to customize the functionality of the trigger module while keeping

resource usage in check.

Selecting the Data-Same-As-Trigger Ports

If the Data Same As Trigger checkbox is selected (Figure 2-6, page 52), then a checkbox

called Exclude Trigger Port from Data Storage appears in the trigger port options screen.

Putting a checkmark in this checkbox will cause the trigger port to be excluded from the

aggregate data port. By default, this checkbox is unchecked and the trigger port is included

in the aggregate data port. A maximum data width of 256 bits (or 1,024 bits for Virtex-5

devices) applies to the aggregate selection of trigger ports.

Generating the Core

After entering the ILA core parameters, click Finish to create the ILA core files. While the

ILA core is being generated, a progress indicator will appear. Depending on the host

computer system, it may take several minutes for the ILA core generation to complete.

After the ILA core has been generated, a list of files that are generated will appear in a

separate window (see Figure 2-9).

X-Ref Target - Figure 2-9

Figure 2-9: List of Generated ILA Core Files

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Using the ILA Core

To instantiate the example ILA core HDL files into your design, use the following

guidelines to connect the ILA core port signals to various signals in your design:

•Connect the ILA core’s CONTROL port signal to an unused control port of the ICON

core instance in the design

•Connect all unused bits of the ILA core’s data and trigger port signals to “0”. This

prevents the mapper from removing the unused trigger and/or data signals and also

avoids any DRC errors during the implementation process

•Make sure the data and trigger source signals are synchronous to the ILA clock signal

(CLK)

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Generating the VIO Core

The CORE Generator tool provides the ability to define and generate a customized VIO

core for adding virtual inputs and outputs to your HDL designs. You can customize the

virtual inputs and outputs to be synchronous to a particular clock in your design or to be

completely asynchronous with respect to any clock domain in your design. You can also

customize the number of input and output signals used by the VIO core.

After the CORE Generator tool validates the user-defined parameters, it generates an XST

netlist (*.ngc) and other files specific to the HDL language and synthesis tool associated

with the CORE Generator project. You can easily generate the netlist and code examples

for use in normal FPGA design flows.

The CORE Generator tool offers the choice to generate either an ICON, ILA, VIO, or ATC2

core. Select VIO (ChipScope Pro - Virtual Input/Output) and click the Customize link on

the right side of the window (Figure 2-10).

X-Ref Target - Figure 2-10

Figure 2-10: Selecting the VIO Core

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General VIO Core Options

The second screen is used to set up the general VIO core options (Figure 2-11).

Entering the Component Name

The Component Name field is can consist of any combination of alpha-numeric characters

in addition to the underscore symbol. However, the underscore symbol cannot be the first

character in the component name.

Asynchronous Input Signals

The VIO core will include asynchronous inputs when the Enable Asynchronous Input

Signals checkbox is enabled. When enabled, you can specify that up to 256 asynchronous

input signals should be used by entering a value in the Width text field. Asynchronous

input signals are inputs to the VIO core and can be used as outputs from your design,

regardless of the clock domain.

Asynchronous Output Signals

The VIO core will include asynchronous outputs when the Enable Asynchronous Output

Signals checkbox is enabled. When enabled, you can specify that up to 256 asynchronous

output signals should be used by entering a value in the Width text field. Asynchronous

output signals are outputs from the VIO core and can be used as inputs to your design,

regardless of the clock domain.

Synchronous Input Signals

The VIO core will include synchronous inputs when the Enable Synchronous Input

Signals checkbox is enabled. When enabled, you can specify that up to 256 synchronous

input signals should be used by entering a value in the Width text field. Synchronous input

signals are inputs to the VIO core and can be used as outputs from your design, as long as

those design signals are synchronous to the CLK signal of the VIO core.

X-Ref Target - Figure 2-11

Figure 2-11: VIO Core General Options

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Synchronous Output Signals

The VIO core will include synchronous outputs when the Enable Synchronous Output

Signals checkbox is enabled. When enabled, you can specify that up to 256 synchronous

output signals should be used by entering a value in the Width text field. Synchronous

output signals are outputs from the VIO core and can be used as inputs to your design, as

long as those design signals are synchronous to the CLK signal of the VIO core.

Inverting the Clock Edge

The VIO core can use either a non-inverted or inverted CLK signal to capture and generate

data on the synchronous input and output signals, respectively. The Invert Clock Edge

checkbox is used to invert the CLK signal that is coming into the VIO core.

Note: The clock can only be inverted if synchronous inputs and/or outputs are used.

Generating the Core

After entering the VIO core parameters, click Finish to create the VIO core files. While the

VIO core is being generated, a progress indicator will appear. Depending on the host

computer system, it may take several minutes for the VIO core generation to complete.

After the VIO core has been generated, a list of files that are generated will appear in a

separate window (see Figure 2-12).

X-Ref Target - Figure 2-12

Figure 2-12: List of Generated VIO Core Files

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Using the VIO Core

To instantiate the example VIO core HDL files into your design, use the following

guidelines to connect the VIO core port signals to various signals in your design:

•Connect the VIO core’s CONTROL port signal to an unused control port of the ICON

core instance in the design

•Connect all unused bits of the VIO core’s asynchronous and synchronous input

signals to a “0”. This prevents the mapper from removing the unused trigger and/or

data signals and also avoids any DRC errors during the implementation process

•For best results, make sure the synchronous input source signals are synchronous to

the VIO clock signal (CLK); also make sure the synchronous output sink signals are

synchronous to the VIO clock signal (CLK)

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Generating the ATC2 Core

The CORE Generator tool provides the ability to define and generate a customized ATC2

core for adding external Agilent logic analyzer capture capabilities to your HDL designs.

You can customize the number of pins (and their characteristics) to be used for external

capture as well as how many input data ports you need. You can also customize the type of

capture mode (state or timing) to be used as well as the TDM compression mode (1x or 2x).

After the CORE Generator tool validates the user-defined parameters, it generates an XST

netlist (*.ngc) and other files specific to the HDL language and synthesis tool associated

with the CORE Generator project. You can easily generate the netlist and code examples

for use in normal FPGA design flows.

The CORE Generator tool offers the choice to generate either an ICON, ILA, VIO, or ATC2

core. Select ATC2 (ChipScope Pro - Agilent Trace Core 2) and click the Customize link

in the right side of the window (Figure 2-13).

X-Ref Target - Figure 2-13

Figure 2-13: Selecting the ATC2 Core

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Chapter 2: Using the CORE Generator Tool

ATC2 Core Acquisition and State Parameters

The CORE Generator tool is used to set up the ATC2 core acquisition and state parameters

(Figure 2-14).

Entering the Component Name

The Component Name field is can consist of any combination of alpha-numeric characters

in addition to the underscore symbol. However, the underscore symbol cannot be the first

character in the component name.

Selecting the Acquisition Mode

The acquisition mode of the ATC2 core can be set to either to Timing - Asynchronous

Sampling mode for asynchronous data capture or State - Synchronous Sampling mode for

synchronous data capture to the CLK input signal. In State mode, the data path through the

ATC2 core uses pipeline flip-flops that are clocked on the CLK input port signal. In Timing

mode, the data path through the ATC2 core is composed purely of combinational logic all

the way to the output pins. Also, in Timing mode, the ATCK pin is used as an extra data

pin.

Max Frequency Range

The Max Frequency Range parameter is used to specify the maximum frequency range in

which you expect to operate the ATC2 core. The implementation of the ATC2 core will be

optimized for the maximum frequency range selection. The valid maximum frequency

ranges are 0-100 MHz, 101-200 MHz, 201-300 MHz, and 301-500 MHz. The maximum

frequency range selection only has an affect on core implementation when the acquisition

mode is set to State - Synchronous Sampling.

TDM Rate

The ATC2 core does not use on-chip memory resources to store the captured trace data.

Instead, it transmits the data to be captured by an Agilent logic analyzer that is attached to

the FPGA pins using a special probe connector. The data can be transmitted out the device

X-Ref Target - Figure 2-14

Figure 2-14: ATC2 Core Acquisition and State Parameters

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Generating the ATC2 Core

pins at the same rate as the incoming DATA port (TDM Rate = 1x) or twice the rate as the

DATA port (TDM Rate = 2x). The TDM rate can be set to “2x” only when the acquisition

mode is set to State - Synchronous Sampling.

ATC2 Core Pin and Signal Parameters

After you have set up the ATC2 core acquisition and state parameters, click Next. This

takes you to the screen in the CORE Generator tool that is used to set up the ATC2 pin and

signal parameters (Figure 2-15).

Enable Auto Setup

The Enable Auto Setup option is used to enable a feature that allows the Agilent Logic

Analyzer to automatically set up the appropriate ATC2 pin to Logic Analyzer pod

connections. This feature also allows the Agilent Logic Analyzer to automatically

determine the optimal phase and voltage sampling offsets for each ATC2 pin. This feature

is enabled by default.

Enable Always On Mode

The Enable Always On Mode parameter is used to force an ATC2 core to always enable its

internal logic and output buffers. The "Always On" mode will also force the selection of

signal bank 0 upon FPGA device configuration. This mode makes it possible to capture

events that immediately follow device configuration without having to first set up the

ATC2 core manually. This feature is disabled by default and is only available when the

acquisition mode is set to Timing mode.

ATD Pin Count

The ATC2 core can implement any number of ATD output pins in the range of 4 through

128.

X-Ref Target - Figure 2-15

Figure 2-15: ATC2 Core Pin and Signal Parameters

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Driver Endpoint Type

The Driver Endpoint Type setting is used to control whether single-ended or differential

output drivers are used on the ATCK and ATD output pins. All ATCK and ATD pins must

use the same driver endpoint type.

Pin Edit Mode

The pin edit mode is a time saving feature that allows you to change the IO Standard, Drive

and Slew Rate pin parameters on individual pins or together as a group of pins. Selecting

ATD drivers same as ATCK allows you to change the ATCK pin parameters and forces all

ATD pins to the same settings. Selecting ATD drivers different than ATCK allows you to

edit the parameters of each pin independently from one another. You need to set unique

pin locations for each individual pin regardless of the Pin Edit Mode parameter setting.

Signal Bank Count

The ATC2 core contains an internal, run-time selectable data signal bank multiplexer. The

Signal Bank Count setting is used to denote the number of data input ports or signal banks

the multiplexer will implement. The valid Signal Bank Count values are 1, 2, 4, 8, 16, 32,

and 64.

Signal Bank Width

The width of each input signal bank data port of the ATC2 core depends on the capture

mode and the TDM rate. In State mode, the width of each signal bank data port is equal to

(ATD pin count) * (TDM rate). In Timing mode, the width of each signal bank data port is

equal to (ATD pin count + 1) * (TDM rate) since the ATCK pin is used as an extra data pin.

ATC2 Core ATCK and ATD Pin Parameters

After you have set up the ATC2 core pin and signal parameters, click Next. This takes you

to the screen in the CORE Generator tool that is used to set up the ATCK and ATD pin

parameters (Figure 2-16).

X-Ref Target - Figure 2-16

Figure 2-16: ATC2 Core ATCK and ATD Pin Parameters

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Generating the ATC2 Core

The output clock (ATCK) and data (ATD) pins are instantiated inside the ATC2 core for

your convenience. This means that although you do not have to manually bring the ATCK

and ATD pins through every level of hierarchy to the top-level of your design, you do need

to specify the location and other characteristics of these pins in the Core Generator. These

pin attributes are then added to the *.ncf file of the ATC2 core. Using the settings in the

Pin Parameters table, you can control the location, I/O standard, output drive and slew

rate of each individual ATCK and ATD pin.

Pin Name

The ATC2 core has two types of output pins: ATCK and ATD. The ATCK pin is used as a

clock pin when the capture mode is set to State and is used as a data pin when the capture

mode is set to Timing. The ATD pins are always used as data pins. The names of the pins

cannot be changed.

Pin Loc

The Pin Loc column is used to set the location of the ATCK or ATD pin.

IO Standard

The IO Standard column is used to set the I/O standard of each individual ATCK or ATD

pin. The I/O standards that are available for selection depend on the device family and

driver endpoint type. The names of the I/O standards are the same as those in the

IOSTANDARD section of the Constraints Guide in the Xilinx Software Manual at

http://www.xilinx.com/support.

Drive

The Drive column setting denotes the maximum output drive current of the pin driver and

ranges from 2 to 24 mA, depending on the IO Standard selection.

Slew Rate

The Slew Rate column can be set to either FAST or SLOW for each individual ATCK or

ATD pin.

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Chapter 2: Using the CORE Generator Tool

Generating the Core

After entering the VIO core parameters, click Finish to create the VIO core files. While the

VIO core is being generated, a progress indicator will appear. Depending on the host

computer system, it may take several minutes for the VIO core generation to complete.

After the VIO core has been generated, a list of files that are generated will appear in a

separate window (see Figure 2-17).

Using the ATC2 Core

To instantiate the example ATC2 core HDL files into your design, use the following

guidelines to connect the ATC2 core port signals to various signals in your design:

•Connect the ATC2 core’s CONTROL port signal to an unused control port of the ICON

core instance in the design

•Connect all unused bits of the ATC2 core’s asynchronous and synchronous input

signals to a “0”. This prevents the mapper from removing the unused trigger and/or

data signals and also avoids any DRC errors during the implementation process

•For best results, make sure the State mode input data port signals are synchronous to

the ATC2 clock signal (CLK); this is not important for Timing mode input data port

signals

X-Ref Target - Figure 2-17

Figure 2-17: List of Generated ATC2 Core Files

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Chapter 3

Using the ChipScope Pro Core Inserter

Core Inserter Overview

The ChipScope Pro Core Inserter is a post-synthesis tool used to generate a netlist that

includes the user design as well as parameterized ICON, ILA, and ATC2 cores as needed.

The Core Inserter gives you the flexibility to quickly and easily use the debug functionality

to analyze an already synthesized design, and without any HDL instantiation.

Note: The IBA/OPB, IBA/PLB, VIO, and IBERT cores are currently not supported in the Core

Inserter tool.

Using the Core Inserter with ISE Project Navigator

This section is provided for users of the Windows or Linux versions of ChipScope Pro 10.1

and ISE 10.1.

The Core Inserter .cdc file can be added as a new source file to the Project Navigator

source file list. In addition to this, the Project Navigator tool will also recognize and invoke

the Core Inserter tool during the appropriate steps in the implementation flow. For more

information on how the Project Navigator and the Core Inserter are integrated, refer to the

Project Navigator section of the ISE Software Manuals (http://www.xilinx.com/support).

ChipScope Definition and Connection Source File

To use the Core Inserter tool to insert cores into a design processed by the ISE 10.1 Project

Navigator tool, follow these steps:

1. Add the definition and connection file (.cdc) to the project and associate it with the

appropriate design module.

a. To create a new .cdc file, select Project → New Source, then select ChipScope

Definition and Connection File and give the file a name (Figure 3-1, page 70).

Click through the remaining dialog boxes using the default settings, as needed.

Note: The ChipScope Definition and Connection File source type is only listed if Project

Navigator 10.1 detects a ChipScope Pro 10.1 installation (the respective versions must match).

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b. To add an existing .cdc file, select Project → Add Source or Project → Add

Copy of Source, then browse for the existing .cdc file.

When prompted, associate the .cdc file with the appropriate top-level design

module. The .cdc file should now be displayed in the Sources in Project window

underneath the associated design module (Figure 3-2).

2. To create the cores and complete the signal connections, double-click the .cdc file in

the Sources in Project window. This runs the Synthesis (if applicable) and Translate

processes, as necessary, and then opens the .cdc file in the Core Inserter tool.

3. Modify the cores and connections in the Core Inserter tool as necessary (as shown in

the section called “ChipScope Pro Core Inserter Features,” page 75), then close the

Core Inserter tool.

4. When the associated top-level design is implemented in Project Navigator, the cores

are automatically inserted into the design netlist as part of the Translate phase of the

flow. There is no need to set any properties to enable this to happen. The .cdc is in the

project and associated with the design module being implemented and causes the

cores to be inserted automatically.

X-Ref Target - Figure 3-1

Figure 3-1: Creating a New .cdc Source File

X-Ref Target - Figure 3-2

Figure 3-2: The .cdc Source File

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Using the Core Inserter with ISE Project Navigator

Useful Project Navigator Settings

The following are useful Project Navigator settings to help you implement a design with

cores:

1. If you use the XST synthesis tool, set the Keep Hierarchy option to Yes or Soft to

preserve the design hierarchy and prevent the XST tool from optimizing across all

levels of hierarchy in your design. Using the Keep Hierarchy option preserves the

names of nets and other recognizable components during the core insertion stage of

the flow. If you do not use the Keep Hierarchy option, some of your nets and/or

components can be combined with other logic into new components or otherwise

optimized away. To keep the design hierarchy:

a. Select Edit → Preferences to bring up the Preferences dialog box.

b. Select the Processes tab.

c. Set the Property Display Level combo box dropdown to Advanced and click OK.

d. Right-click on the Synthesize process and select the Properties... option.

e. Make sure the Keep Hierarchy option is set to Yes or Soft and click OK.

2. Prior to using the Analyzer to download your bitstream into your device, make sure

the bitstream generation options are set properly:

a. In the Project Navigator, right-click on the Generate Programming File process

and select the Properties... option.

b. Select the Startup options tab.

c. Set the FPGA Start-Up Clock dropdown to JTAG Clock.

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Chapter 3: Using the ChipScope Pro Core Inserter

Using the Core Inserter with Command Line Implementation

Command Line Flow Overview

The 10.1 Core Inserter supports a basic command line for batch core insertion. As shown in

Figure 3-3, the Core Inserter command line flow consists of three steps:

1. Create CDC Project

2. Edit CDC Project

3. Insert Cores

The Core Inserter is invoked prior to calling ngdbuild to instantiate debug cores in the

design. Nets are selected for debug using the Edit CDC Project mode to display the GUI

and save net selections to the project. After successfully implementing the design and

configuring the Xilinx device with the resulting bitstream, the Analyzer is used for in-

circuit design debug and verification. To change debug net selections or core settings after

configuration, iterate back to the Edit CDC Project step and proceed through the flow to

create a new bitstream for further debug and verification.

X-Ref Target - Figure 3-3

Figure 3-3: Command Line Core Inserter Flow

Start

Done

Design Entry

Design Synthesis

Device Programming

ChipScope Pro Core Inserter

Create CDC Project

ChipScope Pro Core

In-Circuit Verification

ChipScope Pro Core Inserter

Edit CDC Project

ChipScope Pro Core Inserter

Insert Cores

ngdbuild

map

par

bitgen

Design Implementation

inserter_cmd_line_flow_ch3_03_121306

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Using the Core Inserter with Command Line Implementation

Create CDC Project Step

The Create CDC Project step of the command line Core Inserter flow is used to create an

empty skeleton CDC project file, as shown in Figure 3-4. The command line signature for

this step is:

inserter -create <project.cdc>

Note: This step does not bring up the Core Inserter graphical user interface (GUI).

Edit CDC Project Step

The Edit CDC Project step of the command line Core Inserter flow is used to bring up the

Core Inserter GUI to edit an existing CDC project (see Figure 3-5) The ngcbuild tool is

called during this step with the specified arguments following the -ngcbuild argument.

The ngcbuild tool combines all netlists associated with the design into a single complete

NGC netlist file. This allows the Core Inserter tool to provide full debug access to all levels

and nodes in the design.

The command line signature for this step is:

inserter -edit <project.cdc> -ngcbuild [-p <partname>] [{-sd

<source_dir>}] [-dd <output_dir>] [-i] <inputdesign.{edn|ngc}>

<outputdesign.ngc>

X-Ref Target - Figure 3-4

Figure 3-4: Create CDC Project Step

inserter_create_mode_ch3_04_121306

ChipScope Pro

Core Inserter Project.cdc

X-Ref Target - Figure 3-5

Figure 3-5: Edit CDC Project Step

inserter_edit_mode_ch3_05_121306

ChipScope Pro

Core Inserter Project.cdc

Project.cdc

InputDesign

Project.cdc

Cores

OutputDesign

Cores

ngcbuild

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Chapter 3: Using the ChipScope Pro Core Inserter

Insert Cores Step

The Insert Cores step of the command line Core Inserter flow is used to insert cores into a

design based on an existing CDC project (see Figure 3-6). The ngcbuild tool is called during

this step with the specified arguments following the -ngcbuild argument. The ngcbuild

tool combines all netlists associated with the design into a single complete NGC netlist file.

The cores are inserted into this single complete netlist.

The command line signature for this step is:

inserter -insert <project.cdc> -ngcbuild [-p <partname>] [{-sd

<source_dir>}] [-dd <output_dir>] [-i] <inputdesign.{edn|ngc}>

<outputdesign.ngc>

X-Ref Target - Figure 3-6

Figure 3-6: Insert Cores Step

inserter_insert_mode_ch3_06_121306

ChipScope Pro

Core Inserter

Project.cdc

InputDesign

Project.cdc

Cores

OutputDesign

Cores

ChipScope

Cores

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ChipScope Pro Core Inserter Features

Working with Projects

Projects saved in the Core Inserter hold all relevant information about source files,

destination files, core parameters, and core settings. This allows you to store and retrieve

information about core insertion between sessions. The project file (.cdc extension) can

also be used as an input to the Analyzer to import signal names.

When the ChipScope Core Inserter is first opened, all the relevant fields are completely

blank. Using the command File → New also results in this condition (Figure 3-7).

Opening an Existing Project

To open an existing project, select it from the list of recently opened projects, or select

File → Open Project, and Browse to the project location. After you locate the project, you

can either double-click on it or click Open.

Saving Projects

If a project has changed during the course of a session, you will be prompted to save the

project upon exiting the Core Inserter. You can also save a project by selecting File → Save.

To rename the current project or save it to another filename, select File → Save As, type in

the new name, and click Save.

X-Ref Target - Figure 3-7

Figure 3-7: Blank Core Inserter Project

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Refreshing the Netlist

The Core Inserter automatically reloads the design netlist if it detects that the netlist has

changed since the last time it was loaded. However, you can force the Core Inserter to

refresh the netlist by selecting File → Refresh Netlist.

Inserting and Removing Units

You can insert new units into the project by selecting Edit → New ILA Unit or Edit → New

ATC2 Unit. You can remove a unit by selecting Edit → Remove Unit after choosing which

unit to delete.

Setting Preferences

You can set the ChipScope Core Inserter project preferences by selecting Edit →

Preferences. They are organized into three categories: Tools, ISE Integration, and

Miscellaneous. Refer to “Managing Project Preferences,” page 95 for more information

about setting these preferences.

Inserting the Cores

ICON, ILA, and ATC2 cores are inserted when the flow is completed, or by selecting

Insert →Insert Core. If all channels of all the capture cores are not connected to valid

signals, an error message results.

Exiting the Core Inserter

To exit the ChipScope Core Inserter, select File → Exit.

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ChipScope Pro Core Inserter Features

Specifying Input and Output Files

The ChipScope Core Inserter works in a step-by-step process.

1. Specify the Input Design Netlist (Figure 3-7, page 75).

2. Click Browse to navigate to the directory where the netlist resides.

3. Modify the Output Design Netlist and Output Directory fields as needed. (These fields

are automatically filled in initially.)

Figure 3-8 shows a project with input and output files specified.

Note: When the Core Inserter is invoked from the Project Navigator tool, the Input Design Netlist,

Output Design Netlist, Output Directory and Device Family fields are automatically filled in

(Figure 3-9, page 78). In this case, these fields can only be changed by the Project Navigator tool and

cannot be modified directly in the Core Inserter.

X-Ref Target - Figure 3-8

Figure 3-8: Core Inserter Project with Files Specified

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Project Level Parameters

Three project level parameters (device family, SRL16 usage, and RPM usage) must be

specified for each project.

Selecting the Target Device Family

The target FPGA device family is displayed in the Device Family field. The structure of the

ICON and capture cores are optimized for the selected device family. Use the pull-down

selection to change the device family to the desired architecture.

The default target device family is Virtex-4.

Using SRL16s

The Use SRL16s checkbox is used to select whether or not the cores will be generated

using SRL16 and SRL16E components. This option is only available for the Virtex-II,

Virtex-II Pro, Virtex-4, Virtex-5, Spartan-3, Spartan-3E, Spartan-3A, and Spartan-3A DSP

device families (including the QPro variants of these families). If the checkbox is not

selected, the SRL16 components are replaced with flip-flops and multiplexers, which

affects the size and performance of the generated cores.

The Use SRL16s checkbox is checked by default to generate cores that use the optimized

SRL16 technology.

X-Ref Target - Figure 3-9

Figure 3-9: Core Inserter as Launched from Project Navigator

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ChipScope Pro Core Inserter Features

Using RPMs

The Use RPMs checkbox is used to select whether the individual cores should be

relationally placed macros (RPMs). This option places restraints on the place-and-route tool

to optimize placement of all the logic for the core in one area. If your design uses most of

the resources in the device, these placement constraints might not be met. The Use RPMs

checkbox is checked by default in order to generate cores that are optimized for placement.

When this step is completed, click Next.

Core Utilization

The Core Utilization panel on the left side of the Core Inserter tool main window

(Figure 3-9, page 78) displays an estimated count of the look-up table (LUT), flip-flop (FF),

and block RAM (BRAM) resources that are consumed by the ChipScope cores that are

being inserted into the design netlist. The core resource utilization counts are updated

based on the selection of various core parameters that affect the makeup of the cores being

inserted into the design netlist.

Note: Note: The core utilization feature is not available for the Virtex-5 device family.

Choosing ICON Options

The first options that need to be specified are for the ICON core. The ICON core is the

controller core that connects all ILA and ATC2 cores to the JTAG boundary scan chain. The

ICON core has the parameters shown in Figure 3-10.

X-Ref Target - Figure 3-10

Figure 3-10: ICON Options

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Disabling JTAG Clock BUFG Insertion

Disabling the JTAG clock BUFG insertion causes the implementation tools to route the

JTAG clock using normal routing resources instead of global clock routing resources. By

default, this clock is placed on a global clock resource (BUFG). To disable this BUFG

insertion, check the Disable JTAG Clock BUFG Insertion checkbox.

Note: This should only be done if global resources are very scarce; placing the JTAG clock on

regular routing, even high-speed backbone routing, introduces skew. Make sure the design is

adequately constrained to minimize this skew.

After selecting the desired ICON parameters (Figure 3-10, page 79) click Next or New ILA

Unit to automatically create an ILA core and display the Select Logic Analyzer Options

window. To add a new ATC2 core instead of an ILA core, click either New ATC2 Unit.

Selecting the Boundary Scan Chain

The Analyzer can communicate with the cores using either the USER1, USER2, USER3, or

USER4 boundary scan chains. You can select the desired scan chain from the Boundary

Scan Chain pull-down list. This option is only available when targeting the Virtex-4 or

Virtex-5 device families.

Choosing ILA Trigger Options and Parameters

Notice in Figure 3-11 that a new ILA unit has been created in the device hierarchy on the

left. The next step is to set up the ILA unit. Figure 3-11 shows a sample of the first tab in the

ILA options and parameters sequence. The first tab sets up the trigger options for the ILA

core.

X-Ref Target - Figure 3-11

Figure 3-11: ILA Core Trigger Parameters

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ChipScope Pro Core Inserter Features

Selecting the Number of Trigger Ports

Each ILA core can have up to 16 separate trigger ports that can be set up independently.

After you select the number of trigger ports from the Number of Trigger Ports pull-down

list, a group of options appears for each of these ports. The group of options associated

with each trigger port is labeled with TRIGn, where n is the trigger port number 0 to 15.

The trigger port options include trigger width, number of match units connected to the

trigger port, and the type of these match units.

Entering the Width of the Trigger Ports

The individual trigger ports are buses that are made up of individual signals or bits. The

number of bits used to compose a trigger port is called the trigger width. The width of each

trigger port can be set independently using the TRIGn Trigger Width field. The range of

values that can be used for trigger port widths is 1 to 256.

Selecting the Number of Trigger Match Units

A match unit is a comparator that is connected to a trigger port and is used to detect events

on that trigger port. The results of one or more match units are combined together to form

the overall trigger condition event that is used to control data capture. Each trigger port

TRIGn can be connected to 1 to 16 match units by using the # Match Units pull-down list.

Selecting one match unit conserves resources while still allowing some flexibility in

detecting trigger events. Selecting two or more trigger match units allows a more flexible

trigger condition equation to be a combination of multiple match units. However,

increasing the number of match units per trigger port also increases the usage of logic

resources accordingly.

Note: The aggregate number of match units used in a single ILA core cannot exceed 16, regardless

of the number of trigger ports used.

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Selecting the Match Unit Type

The different comparisons or match functions that can be performed by the trigger port

match units depend on the type of the match unit. Six types of match units are supported

by the ILA core (Table 3-1).

Use the TRIGn Match Type pull-down list to select the type of match unit that will apply to

all match units connected to the trigger port. However, as the functionality of the match

unit increases, so does the amount of resources necessary to implement that functionality.

This flexibility allows you to customize the functionality of the trigger module while

keeping resource usage in check.

Table 3-1: ILA Trigger Match Unit Types

Type Bit

Values1

Match

Function

Bits Per

Slice2Description

Basic 0, 1, X ‘=’, ‘<>’ Virtex-5: 19

All others: 8

Can be used for comparing data

signals where transition detection is

not important. This is the most bit-

wise economical type of match unit.

Basic

w/edges

0, 1, X,

R, F, B ‘=’, ‘<>’ Virtex-5: 8

All others: 4

Can be used for comparing control

signals where transition detection

(e.g., low-to-high, high-to-low, etc.) is

important.

Extended 0, 1, X ‘=’, ‘<>’, ‘>’,

‘>=’, ‘<‘, ‘<=’

Virtex-5: 16

All others: 2

Can be used for comparing address or

data signals where magnitude is

important.

Extended

w/edges

0, 1, X,

R, F, B

‘=’, ‘<>’, ‘>’,

‘>=’, ‘<‘, ‘<=’

Virtex-5: 8

All others: 2

Can be used for comparing address or

data signals where a magnitude and

transition detection are important.

Range 0, 1, X

‘=’, ‘<>’, ‘>’,

‘>=’, ‘<‘, ‘<=’,

‘in range’,

‘not in range’

Virtex-5: 8

All others: 1

Can be used for comparing address or

data signals where a range of values is

important.

Range

w/edges

0, 1, X,

R, F, B

‘=’, ‘<>’, ‘>’,

‘>=’, ‘<‘, ‘<=’,

‘in range’,

‘not in range’

Virtex-5: 4

All others: 1

Can be used for comparing address or

data signals where a range of values

and transition detection are

important.

Notes:

1. Bit values: ’0’ means “logical 0”, ‘1’ means “logical 1”, ‘X’ means “don’t care”, ‘R’ means “0-to-1

transition”, ‘F’ means “1-to-0 transition”, and ‘B’ means “any transition”.

2. The Bits Per Slice value is only an approximation that is used to illustrate the relative resource

utilization of the different match unit types. It should not be used as a hard estimate of resource

utilization.

ChipScope Pro 10.1 Software and Cores User Guidewww.xilinx.com 83

UG029 (v10.1) March 24, 2008

ChipScope Pro Core Inserter Features

Selecting Match Unit Counter Width

The match unit counter is a configurable counter on the output of the each match unit in a

trigger port. This counter can be configured at run time to count a specific number of

match unit events. To include a match counter on each match unit in the trigger port, select

a counter width from 1 to 32. The match counter will not be included on each match unit if

the Counter Width combo box is set to Disabled. The default Counter Width setting is

Disabled.

Enabling the Trigger Condition Sequencer

The trigger condition sequencer is a standard Boolean equation trigger condition that can be

augmented with an optional trigger sequencer by checking the Enable Trigger

Sequencer checkbox. A block diagram of the trigger sequencer is shown in Figure 3-12.