Hazeltine_1500_Series_Maintenance_Manual_Dec77 Hazeltine 1500 Series Maintenance Manual Dec77

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Hazeltine_1500_Series_Maintenance_Manual_Dec77 Hazeltine_1500_Series_Maintenance_Manual_Dec77

User Manual: Hazeltine_1500_Series_Maintenance_Manual_Dec77

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SERIES
VIDEO DISPLAY TERMINALS
MAINTENANCE MANUAL
Part Numbers 4DTD155207
4DTD155207-1
4DTD155255
4DTD155255-1
4DTD155260
4DTD155260-1

HI-1053A
DECEMBER 1977

Hazeltine Corporation
COMPUTER TERMINAL EQUIPMENT
GREENLAWN, N.Y. 11740 (516)549-8800
TELEX 96-1435

HI-I053A

SAFETY SUMMARY

WARNING

I

Dangerous voltages (15 K vdc and 115 vac) are present in the Video
Display Terminal and may remain present in the monitor circuits
after power is removed.
cuits.

Use caution when ,vorking on internal cir-

Do not work alone.

Use caution when handling the cathode-ray tube (eg, wear safety
goggles to a void risk of implosion. The internal phospher coating
is toxic; if the tube breaks and skin or eyes are exposed to phosphor,
rinse with cold water and consult a physician.

This manual is published and distributed by Hazeltine Corp'oration, Computer Terminal Equipment Product Line. The contents of this manual are subject
to change at any time and without prior notice by
Hazeltine.
The information presented herein may
not reflect latest changes in the product. Confirmation and any required clarification of this in-'
formation can be obtained from your local Hazeltine sales representative.

Copyright 1977 by Hazeltine Corporation

HI-IOS3A
TABLE OF CONTENTS
Section

Page

1

Introduction and Description . . . . . . . . . . .
1.1 Introduction. . . . .
. ..
..
1.2 General Description. . . .
. ......
1.2.1 Model lS00. . . . . . . . . . . .
1.2.3 Model lS10. . .
. ..
1.2.11 Model lS20 . .
. •.......
1.3 Theory of Operation. • . . .
. ...
1.3.1 Introduction . . . . . . . . . . . . .
1.3.2 Data Transfer.
1.3.3 TV Refresh. . . . . .
. ...
1.3.4 Data Processing
.....
1.3.5 Reset, Interrupt and Wait Functions.
1.3.6 Serial I~put/Output . . . . . . . . .
1.3. 7 TV Synchronizer . .
.•.
1.3.8 Microprocessor. . .
. .••.•.
1.3.9 Monitor. . . . . . . .
. •.
1.3.10 Five-Volt Regulator • . . • . . . . .
1.3.11 Printer Buffer.
...
. ...

2

Site Maintenance.
2.1 Introduction
2.1.1 Scope
·
2.1.2 Test Equipment.
2.2 Checkout
2.2.1 General
2.2.2 Checkout Procedure.
· ·
2.3 Access
·
2.4 Troubleshooting.
2.4.1 Scope
·
2.4.2 Procedure
2.S Adjustments.
2.5.1 Five-Volt Regulator
2.5.2 Monitor Adjustments
2.6 Removal and Replacement. .
2.6.1 Monitor Electronics Chassis
·
2.6.2 CRT/Yoke Assembly and Video Filter.
2.7 Cleaning Video Filter.
·

···
···

. . ·
. .. ·
·

··
· ·
·
·

· ·
··
··
· ·

· ·
· ·
· ··
· ·
· · · · ·· ·
· ·· ·
· · ·
···
·
·

· ·
·
··
· ·
· ·
·
··
···
· · ·
···
·

·
·
·
·
·

· ·
··
··

·

·

2-1
2-1
2-1
2-1

·
·
·
·
·
·
·
·
·
·
·
·
·

2-1
2-2
2-10
2-10
2-10
2-lS
2-15
2-15
2-17
2-19
2-19
2-20
2-20

Repair Shop Maintenance . . . . . . . . • . . . .
3.1 Introduction
...
. ..
3.1.1 Scope
...
....
.
3.1.2 Tools and Test Equipment. . . . .
3.2 Checkout..
........
. ...
3.2.1 Monitor Electronics Chassis • . . . .
3.2.2 Five-Volt Regulator. . . . . . .
3.3 Trouble~hoooting. . . . . . . . . •
3.3.1 Monitor Electronics Chassis.
3.3.2 Five-Volt Regulator. . . . •
3.4 Repair and Replacement . . . . . . . . . . .

3-1
3-1
3-1
3-1
3-1
3-1
3-6
3-12
3-12
3-12
3-12

·

3

·
·
·
·
·
·
·
·
·
·
·
·

·
·

1-1
1-1
1-1
1-1
1-8
1-9
1-11
1-11
1-16
1-19
1-20
1-38
1-40
1-42
1-4S
1-47
1-S3
1-54

i

·
·

·
·
·

··

·

·

· ·
·
··

· · · · ·
· · ·

2~1

HI-I053A

TABLE OF CONTENTS (Cont)

4

Factory Maintenance • . . • . . • . . •
.
4.1 Introduction. . • • • • • . . • . . . . . .
4.1.1 Scope. . • . . .
•. •
.
4.1.2 Test Equipment . • . • . . . . . • • •
4.2 Checkout. . • . • . . •
•..
. •.
4.2.1 General. • • . . . •
••
4.2.2 Setup and Preliminary Adjustments . .
4.2.3 Interface Tests. . • . . • • .
.
4.2.4 Current Loop and Control Tests.
.
4.2.5 Parity Checks. • . . . • .
. ..
4.2.6 Break Check. • • •
.
4.2.7 Baud Rate Checks. . ••
. .....
4.2.8 stop Bits Check.
.....
.
4.2.9 Auxiliary Output Check.
.
4.2.10 Format Mode and Printer Buffer Check.
4.2.11 Printer Buffer Serial Output Checks.
4.3 Testing and Troubleshooting . . • . • . . . .
4.3.1 Keyboard/Logic Assembly. • .
..
4.3.2 Monitor and 5-Volt Regulator • • . . •
4.4 Alignment. • • . • . . . . . • . . . .
.

4-1
4-1
4-1
4-1
4-1
4-1
4-2
4-3
4-12
4-13
4-13
4-13
4-14
4-14
4-16
4-17
4-18
4-18
4-19
4-19

APPENDIXES
!\J~eendix

Page

A

Recommended Spare Parts List

B'

Diagrams. . • . •

c

Export Units . • •
Summary of Remote Commands . •

D

· . A-I
. . . B.-l
. . • C-l
· . D-l

LIST OF ILLUSTRATIONS
Figure

...... .......,.....r__ ____

1-1
1-2

1-3
1.-4

1-5
1-6
1-7

Controls and Indicators . • . . • •
,Swi tch S1 on Printer Buffer .
~erminal, Block Diagram.
Memory Address Structure. • • .
Character Format.
. • •
Flowcharts. • . • • . . • • • • . •
Reset, Interrupt, and wait Functions, Block
Diagram . • ~ • .
...... . .

...

ii

·
· •
·
· .
· .
· .

1-4
1-7
1-12
1-15
1-18
1";'23

· 1-39

HI-l053A

LIST OF ILLUSTRATIONS (Cant)
Figure
1-8
1-9
1-10
1-11
1-12
1-13
1-14
2-1 .
2-2
2-3
2-4
2-5
3-1
3-2
3-3
3-4
4-1
4-2
4-3
4-4

Serial Input/Output, Block Diagram • • • • •
•
TV Synchronizer, Block Diagram • • • •
• • • •
• • •
Horizontal Timing • . • '. • •
• ••
Vertical Timing . . . • . • . •
. • •
Microprocessor, Block Diagram.
• •
Printer Buffer, Block Diagram • •
• •
Parallel Printer Interface Timing
•••
•
Current Loop Interface and Full Duplex Jumper
Adapter • . • . • • • . • . . • • • • • •
Displays for Checkout Procedure • . • • • • • • •
Servicing Diagram . . • • •
• • •
Monitor Electronics Chassis • • •
.••
•
CRT/Yoke Assembly • • • • • .
•.• •
•
Size/Centering Overlay. . • . • • • • • • • • • •
Monitor Waveforms . • • • .
• ••
•• • •
Five-Volt Regulator Test Jig. •
••••
•
Test Setup Diagram..
••••••
••••
Test Equipment Setup. .
• . • • • • • • • •
Test Display. • • • • • • • •
••••
••
Y Adapter Cable . . • .
• • • •
•
Serial Print Test Cable • • • • • • • • • • . • •

1-41
1-43
1-44
1-45
1-46
1-55
1-57
2-3
2-5
2-11
2-21
2-21
3-2
3-4
3-7
3-9
4-4
4-9
4 -12
4-17

LIST OF TABLES
Table
1-1
1-2
.1-3
2-1
2-2
2-3
3-1
3-2
3-3
3-4
4-1
4-2

Page
Technical Characteristics • • • • • • • •
•
Controls and Indicators • • • • • • • •
•
Terms and Abbreviations Used in Program
Flowcharts. • . • • • • • • . . • • •
•
Terminal Operation - Functions. •
•
Voltage and Resistance Data • • •
•
Troubleshooting Chart • • • • •
• • • •
•
Voltage and Resistance Data for 5-Vo!t
Regulator • • . • • • • . • • • • • • • • • • • •
Monitor Troubleshooting Chart • • • • •
•
Monitor Voltage and Waveform Data (Transistors) •
Monitor Voltage and Waveform Data
(Microcircuits and CRT) • . • • • • •
••
Limited Troubleshooting Guide • • • • •
•••
DC Voltage Usage. • • • • • • • • • • • , • • • ,

iii/ (iv blank)

1- 2
.1-5
1-21
2-12.
2-16
2-16
3-13
3-13
3-14
3-14
4-20
4-22

HI-1053A
SECTION 1
INTRODUCTION AND DESCRIPTION
1.1

INTRODUCTION

1.1.1 This manual provides maintenance instructions for the
Hazeltine 1500, 1510 and 1520 terminals. Only the domestic models
are covered in the body of the manual. Difference data for export
units is provided in Appendix C. The symbol # in the body of the
manual indicates a~ item which is different in the export units.
1.1.2 The 1500 model may have one of two logic/keyboard assemblies.
Part number 4DTD155202 is unique to the 1500. Part number
4DTD155246-( ) is a common board shared by the 1500, 1510 and 1520
(unused parts are not installed) with different dash numbers
employed for the different models. Differences between the '202
board and the common board (mostly reference designations) are
noted on the diagrams and a separate schematic is provided in
Appendix B.
1.1.3 The contents of this manual are subject to change without
prior notice and may not reflect latest changes in the product.
Confirmation and any required clarification of this information
can be obtained from your Hazeltine sales representative. Additional information is provided in the Reference Manuals.
1.2
1.2.1

GENERAL DESCRIPTION
Model 1500

The terminal is a self-contained unit with keyboard, logic,
monitor, and pow.er supplies in a single chassis. It is compatible
with a variety of interface requirements and permits extensive
remote control of display functions. Technical characteristics are
summarized in table 1-1.
1.2.2 Remote commands to the terminal must be preceded by a ~
(tilde) to identify what follows as a remote command. Exceptions
are cursor right, backspace, and tab; these do not require a leadin character. Terminal controls and indicators are listed in
table 1-2 and illustrated in figure 1-1.
1-1

HI-I053A
Table 1-1.

DISPLAY FORMAT
Screen:
Capacity:
Character Format:
Cursor:
Character Set:
#Refresh Rate:
Display:
TV Line Standard:
INTERFACE
Input/Output:
Transmission Rates:
Parity:
Character:
Modes
1500':
#1510/1520:
Printer Buffer (1520):

PHYSICAL/ENVIRONl-iENTAL DATA
Size:
Neight:
Power Required:
Temperature Range:
Humidity Range:
KEYBOARD FEATURES
Typamatic Operation:

REBOTE COMMANPS
1500/1510/1520:

Technical Characteristics

12 inch (30.5 cm) diagonal, P4 phosphor
80 characters/line x 24 lines (1920 characters)
7 x 10 dot matrix in 9 x 11 dot window
Triangle on base (I), cursor and character blink
alternately when superimposed.
(1500 units with
'202 logic board have block cursor)
94 displayable ASCII. All 128 ASCII codes can
be keyed
60 HZ, non interlace
Nhite on black or black on white (switch selected)
two display intensity levels
308 lines/frame, 264 lines displayed
EIA RS-232C compatible with l'lestern Electric type
103A modern, or 20 to 40 rnA current loop (switch
selected)
110, 300, 1200, 1800, 2400, 4800., 9600, or 19,200
baud (switch selected)
Odd, even, 1 or 0 (switch selected)
10 or 11 bits (start, seven bit ASCII, parity, one
or two stop bits), number of stop bits = two for
110 baud, = one for all others
Full duplex or half duplex
Full duplex, half duplex, format or format/
local
Parallel TTL level with strobe, or serial EIA with
strobe (switch selected), at 110, 300 or 1200 Baud
(switch selected)
15-1/2 inches (39.4 cm) wide, 13-1/2 inches
(34.3 cm) high, 20-1/2 inches (52.2 cm) deep
35 pounds (16 kg)
104 to 126 v, 60 Hz ±l%, 120 watts
10° to 40°C (50° to 104°F) operating, -20° to 65°C
(4° to 150°F) storage
5% to 90%, non-condensing
All alphanumeric, symbol, space and cursor control
keys repeat at 15 char/second rate when depressed
longer than 0.8 second
Cursor up, down, right, left, horne
'Insert line, delete line
Clear screen, clear to end of screen, clear to end of
line, clear foreground, clear to end of screen
(background)
Intensity control (set foreground, set background)
Keyboard lock, keyboard unlock
Alarm

1-2

HI-1053A
Table 1-1.

Technical Characteristics (cont)

Tab (Cursor tabs over background data to next
foreground field)
Direct cursor address, send cursor address

1510/1520:

Set format, return to switches
Set transmit mode (protected, or protected and
unprotected; and batch, page or line)
Remote transmit
Back tab
Send status (terminal sends to bit status word
defined below)

1520:

Set print mode:
(1) Remote print (causes all
data to be sent to printer starting from last
print position, or top of screen if no previous
print, and ending at cursor position when
command received) •
(2) On line print with display (all transmitted and received data printed
except commands with ~ lead in).
(3) On line
print without display (Same as (2) except
received data is not displayed, and received
commands are not executed (except terminate on
line print and send status) • Keyboard remains
active and keyboard entries are displayed)
Terminate on line print

Terminal Status Nord:
Bit

Status

0*

1 = Buffer empty

1*

1

2
3

0
0

4

1 = Parity error in previous transmission received

5

0
0

=

Printer on line
Format Hode

0
1

Half or
full duplex

1
0

Batch

1
1

Page

Line

Termination Character
6

*

0
1

CR

Always 0 for 1510

1-3

ETX

1
0

EaT

1
1

None

HI-I053A

NOTE: For Model 1500 units with the 202 Logic Board, the
ErA/CUR LOOP positions are the reverse of those shown.

POWER
SWITCH

ALPHANUMERIC
CLUSTER

BREAKER
RESET
BUTTON

FUNCTION ____ '
CLUSTER
NUMERIC
CLUSTER

CONTROLS UNDER
ACCESS PANEL

-----1510/15200NLY# ~

...----------+-----,I,--l,
a

o

POWER
ON
LED

[~~MAT

o

CONTRAST

7710068

Figure 1-1.

Controls and Indicators
1-4

HI-I053A
Table 1-2.

Controls and Indicators

Controls and Indicators Under Access Panel (figure 1-1)
One of eight switches set to on (forward) to select
desired rate.

#BAUD RATE
PARITY

One of four switches set to on (forward) to select
parity mode.
ODD or EVEN selection causes odd or even parity
bit to be generated for each character transmitted and the same parity is checked for each
character received. A parity error is indicated by an audible alarm and P E is displayed.
1 or 0 selection causes a 1 or 0 in the parity
bit position of each character transmitted.
No parity check is performed on received data.

HALF DUP/FULL

Select full or half duplex operation.

AUTO LF/CR

When AUTO LF is selected, a carriage return causes
the cursor to advance to the beginning of the
next line. A line feed causes no change in cursor
position.
When CR is selected, a carriage return causes the
cursor to move to the beginning of the present
line. A line feed causes the cursor to move down
one line.
(Overridden in FORMAT mode - AUTO LF
operation is automatic).

U/L CASE/UP

When UP case is selected, all alphabetical characters are transmitted and stored as upper case regardless of the SHIFT key position. Keyboard ALL
CAPS switch is overridden.
When U/L CASE is selected, characters are controlled
by the keyboard SHIFT or ALL CAPS keys.

STD VIDEO/REV

Selects standard display (white characters on black
screen) or reverse video (black characters on white
screen) •

EIA/CUR LOOP
(2 switches)

Enables the EIA or current loop interface.
switches must be set to same position.

CONTRAST

Adjusts contrast to operator preference.

POWER ON

Light-emitting diode (red).
is on.

Both

Indicates when power

1510/1520 ONLY

~~
CAPE/'"

FORMAT

EOM switches (2)

----

~--~.~

~

~--

------

Selects either the ASCII ESC code or '" charaC?ter'-as
the lead in for remote commands • ...
"r"

Selects format mode (if set, terminal will go to
format mode at turn on, after reset, or after
return-to-switches comm~.l1dl~'· In this mode, keyboard data is store.d~-arid displayed, but not
transmitted, yen~-Emtered. Transmission is
-co~~:g~~y send command (keyboard or remote).

__ Select charQCt~to be inserted as end-of-message
character at the end_Q! a transmission:
EOM A
g~F

EOM B
-

g~F

~~~

OFF

OFF

None

1-5

EOM--Character
'-'"

----- -'--,
"", "'- ',,_

HI-I053A
controls and Indicators (cant)

Table 1-2.

WRAPAROUND

FORMAT light
'LOCAL light

1510/1520 ONLY (cont)
~
YES: Cursor will automatic.ally wrap around from the
.... ', ... last column of one row to/the first column of the
next . . . r9w when data ~.s···~entered (except on bottom.
row in "format moder'.
NO: curso;. . . . .w:fli·,not wrap around and alarm will sound.
A carriage' return must be entered to move the cursor
to th~v'next line (or other cursor control).
//
-,
Lighted whenever terminal i's ....ip format mode. Blinks
//during batch transmissions and ~atl:r:ing "FUNCTION"
/
operation.
""~.-...........
/,'
Lighted while terminal is in local mode. " " ,
Keyboard Controls

BREAK

Causes a 200 to 250 ms interruption on transmit data
line.

RESET

Resets the keyboard lock and set foreground flags.
Display of data is inhibited while key is depressed.

CLEAR

CLEAR

:

clears entire display to foreground spaces
(In FORMAT mode, functions only when cursor
is in home position)

SCLEAR :

clears all foreground data to foreground
spaces

CCLEAR :

clears all data from, and including, cursor
position to end of line to foreground spaces

CSCLEAR:

clears all data from, and including, cursor
position to end of screen to foreground
spaces

HOME

Homes cursor to row 0 column 0

ALL CAPS

Alternate action switch. When depressed, causes all
alphabetic characters to be upper case regardless
of SHIFT key position.
When released (UP), permits upper or lower case as
controlled by SHIFT key unless internal UP CASE/U/L
switch is set for UP CASE. Data received as lower
case is displayed as lower case.

Alphanumeric Cluster

Generates codes for characters and functions as
marked.

Numeric Cluster

Duplicates same functions as corresponding keys in
alphanumeric cluster but in adding machine arrangement. Key functions are not modified by control
or shift keys.
Keyboard Controls (1510/1520 Only)

FUNCTION

~.
.

Special
S
purpose key to allow communication without
~ffecting display. After FUNCTION key is pressed
the-next character entered will be transmitted in
a two ~r-three-.. character sequence:
ESC, character keyeo·;--EOM . . .character
.
(if selected).
Nothing will' 'be stored or displayed. The FORMAT
light.-wiii blink until the trarismi~sion is completed. An erroneous entry may be ca~,celled by
aepressing the FUNCTION key a second tim~.

1-6

HI-1053A
Table 1-2.

Controls and Indicators (cant)

Keyboard Controls (1510/1520 Only) (cont)
Initiates transmission in mode for which term{~al
has been conditioned (paragraph 1.2.5)
~

D

(Fo

t Mode Only)

c SEND

cS SEND initiates page transmisiion regardless of
precondi tions .
"

.....
PRINT (1520 only)
(sSEND) (Format or
half duplex modes)

initiates line transmission )::;eg'ardless of
preconditions.."

N

LOCAL
(Functions only in
format mode)

nitiates ,tr, ansmissicin to printer when not in printer
on line mode. "A prin t symbol ([] [] ) is displayed
at present cursor position. All data from last
p~'nt
s~61 (or top of screen if no previous print)
to ~sent cursor position, except data to right of
Cll/or u , is sent to printer. Cursor is advanced
/,,'(0 start . f next line (unless on bottom line).
Puts terminal n local mode.
Input data and commands
will be ignore
y terminal (but will be sent to
printer if on line~. Terminated by a SEND or by a
second depression o'r-...LOCAL key. Used to permit formatting data without ili~~rference from received data .
.........

t

+

Move cursor up, down, righi~Qr left without affecting data stored in memory.
"'--... ... ,....

-+- +-

'-..

Insert line/delete line. Same functions on 1500
require keying ~cz and ~cs respectivelY:~~
Controls and Indicator at Rear of Chassis (figure 1-1)
Power Switch and
#Circuit Breaker

Switches AC power (down for on). Circuit breaker
button pops out when actuated (1.75 amps). Push in
to reset.
Switches on Printer Buffer (1520 only)

Sl

(figure 1-2)

Selects parallel or serial output and baud rate
(Sl-4 not used)
Parallel
Serial-110 baud
Serial-300 baud
Serial-1200 baud

Sl-1
Up
Up
Up
Down

S1-2

Sl-3

Up
Up
Down
Down

Up
Down
Down
Down

51-1

Figure 1-2.

5/-1
Switch Sl on Printer Buffer

1-7

HI-l053A

.2.3

Hodel 1510
:'

.'

/

all the features of the 1500, plus fo~~at
and

rmat/local mode capability.

shown

~n

..

table 1-1.

~te

1.2. 4

Additional remote command~ are

Additional controls are listed in table 1-2.

commands to the 1510 may use either a '"

(escape) cfiaracter as a lead in.
manual to

d~ignate

The

~

notation is

In the

\

fo~mat

\
transmitted.

but not

u~ed

ESC

in this

the lead in character but it is/to be under-

stood the ESC'must be substituted if that
1.2.5

~j/~SCII

characte~"

is selected.

mode, data is stored and dIsplayed as entered,
Transmission is initiate~ by the SEND key

\ .
or by remote command (there 1S a 10 ms delay' after remote command).
.

(fo~egrOund)

Only unprotected
terminal has been
unprotected date,

data is transmitted unless the

pre~nditioned
eithe~\lOCallY

to send both protected and
or remotely ('" +).

The terminal

will return to the send-~tiprotected-only mode after RESET, or

(~·comma).

after a remoted command to\do so
a CR or transmit symbol (I)

\

~s
\

:

not sent.

Data to the right of

The FORMAT light blinks

/

for the duration of the transm\ssion, which may be by batch, page
or line.

The batch mode is

au~'~maticallY

selected at turn-on and

\

after a RESET.

Other mOde~/fnay b'e\ se lected locally or by remote

commands:

/

\

\

//

Set line transmit =/I~ period
/

Set page transmit/=
.I

~

Return to batch /

~

Once

precondition~,

('" SO) will

c~

=

\

\\

%

the SEND key or a

,\
\\

r~mote

the selected mode of

by another command or by a RESET.

transmit command

tr~~~mission

Regardle~~

until changed

of preconditioning,

a line trans~ission will be initiated by cSE~'n, and page trans.
.
b y Ics SEND. Deta1. 1 s o
f t h e tree
h
. .ln t h e
m1SS1on
mo d es a~e glven

followin~paragraphs.
1.2.6

In batch transmission, a transmit symbol (1)\1s posted at
\

resent cursor position and data is transmltted from the
be' inning of the line following the preceding I
no prior transmit) to the new

I.

'\

(or from\.top of

The cursor is\\
\.

1-8

\,

,

HI-I053A
a~anced

to the start of the next line unless it is

al~~ady

on

the~bottom line, in which case it is placed -at the beginning of
the

~ttom
,

line.

New data may be entered immediate+y'
but the
,

followi'hg commands cannot be entered until transmi~sion is

complete~\(FORMAT

light stops blinking):

TAB, sTAB, all CLEARs,

FUNCTION, ''all SEND key funct ions, IlL, DIL, Lq,CAL.

The alarm

will sound i\f any of these keys are depresseo.!~

/

\

1.2.7

In lin~\transmission, data on the c~rsor position line is
\

/1

transmitted from the beginning of the li,rie and ends at a carriage
\
,
return or the las~ none-space charact~r on the line. The cursor

is advanced to th~start of the next/iine, with rollup if already
on the bottom line,\except no rollup will occur if the bottom

/

\

line contains a protected character (cursor will be placed at
\

I

Data ~ntry fol,I'owing send command is the

start of line).

\

.

same as batch transmission.

\

.

.\"

1.2.8 ,In page transmlsslqn, all 24 lines are transmitted and the
cursor is placed at the st,art of the bottom line.
occur.

Data C'annot be enter'ed
until the transmission is completed.
,

/:

1.2.9

No rollup will

/

"

The format/local/mode may be selected by depressing the
i

'

LOCAL key when in form~t mode. "operation is the same format mode
\

(

except no input data/lor commands '.\.iill be accepted by the terminal.
I

'..

However, if a print~r is on-line (i520 only) incoming data will be
/

transferred to the printer.

'\

The LOCAL light will be on whenever

.. I

\\

the terminal is/in that mode. Local mOd\ is terminated by any
SEND or by a second depression of the LOCAL key.

I

'

\

The J.l510 model has cursor control keys (++-H-) primarily
/
\.
for use in/format mode, al though they function\\~n full or hal f
'-,
s
duplex as)Well.
In format mode, the BACK SPACE a~d BACK SPACE
1.2.10

(OLE) wyl store the corresponding character at th~"~,ursor position
and mOle the cursor right one position.
1.2. {

Model 1520

""'"
' -,

~,

contains all the features of the 1510, plus ~,
\

with storage capacity for a full screen of

1-9

\

dat~~

HI-I053A
/l
/'~

,I

r'he printer buffer has full synchronizing capability for controlt"
~ a printer with either parallel or serial data transmission,!

,

1.2.12

Three modes of operation are avail'able:

printer on Line
/

with d'i~play, printer on line without display, and printer/Off

Pt~nter on line may be initiated from a switch on the

line.

printer

(~any

means of grounding the printer on line /'itch

input pin at"the terminal), or by remote command.

\

,

Either is
/

sufficient to k'eep the printer on line.
off line operation.

by a remote

termin~~

Both must be reset for
/
A remote on line print cori'l1nand is cancelled

on line print command ("u?)/ or by a RESET

(but the printer will\remain on li!1e (with dispiay) if the printer
\

/

on line switch input is\true (low)).
\

1.2.13

.

/
I

In both on line mbdes, all data trlnsmitted and received
\

/

on the I/O channel is also\ent to the p~{nter via the printer

buffer, except commands

prec~~ed

by a

If

Co~ands

preceded by

an ESC character are sent to th~ prin~er.

If the t~rrninal is in

format mode, a line feed is

each carriage return

ins~\:r:teqf/after

\/1
,
/\
1.2.14 The printer on line with/~i~play mo~e may be initiated by
/
\
the remote command 'V/, and on /line wi\thout display by 'V*.
In the

transwitted.

i,s' not dis~layed and the only inputs
the terminal will respond fio are send ~'tatus ('V-) and terminate
on line print ("u?). Th~eYbOard remain's\active and data entered
latter case, received data

/

\

by keyboard will be stdred and displayed. \
;/

\

1.2.15 In the off ,.l/ine mode, printing is cci~trolled by the PRINT,
/
"
key ( s SEND) or by/remote
command ('VRS).
Transfer
of data to the
/

.\

printer is sim' /Iar to batch transmission except\both protected and
unprotected

ta is printed.

".

he print symbol (DO) is posted at
position and at the next adjacent

'ble

~

cha

th~initial

charact~r positio~,

cursor

It is pos-

or the print symbol to wraparound (i.e., ocCup\\the last

cter position on a line and the first character

e following line).

pos~tion

\

1-10

\

\

of

HI-IOS3A
~

The cursor moves to the first character posi t~.~n"·"·Of the

2•

line~"following
~

the previous print symbol, or the beginl')Yng of

the scre'en if there is no intervening print symbol •.",... . . .'/
.'........~

;.".

.. -."

3.

Fiem the starting point data is transferred to the
'-"
"
printer buffer a€'a very rapid rate independent of the printer
'''-.....

rate.

/,,/'

Transfer of dat;,a to the printer,cft the print rate is under
-....

",',/'

,

control of the printer buffer.
"'.

4.

//"

/

At the end of each,<",cnaracter line a CR code followed

by a line feed code is gen~r&ted .. before reading the first character
of the following line.
print field, i t
first character

./

trans.f~'~s

of/~e
./

"

,If the cursQ,:r encounters a CR code in the
the CR and'tine feed codes before the

following line is "·read.

Single transmi t

symbols are handled in the same manner as carr.iage returns.
/'

to the right/6f a CR or I

. Y

is not sent.

"'"" a~the

//

Readout ends at the print symbol posted

'",-

Data

begin-

"

n1ng of the cycle. A eRIline feed is transmitted and the cursor
/
m~ves to the first character position on the following l{ne.

\\

",

1.3

THEORY OF OPERATION

1.3.1

Introduction

Figure 1-3 is a functional block diagram showing the relationship
of the major functional subdivisions of the terminal.

The central

element of the terminal is the microprocessor, which is connected
to the other functional circuits by a l6-bit address bus, an 8bit data bus, and four read/write control lines.

The bits on

the address bus are designated B.A[Ol through B.A[lS].
not used.
1.3.1.1

Bit 15 is

The data bus bits are designated DBIO] through DB,[7].
The program for the microprocessor is stored in a read-

only memory.

Additional temporary memory for the microprocessor

is available in a scratchpad, which is part of the same memory
used to store the display characters.

The microprocessor uses

the,scatchpad to stack data for a partially completed routine
when it jumps to a subroutine and for storing input characters
(input queue).

The memory address structure is shown in

figure 1-4.
1-11

HI-1053A

1

~

Xl / '

~"

( J; ~~

TO PRINT BUFFER
(SHEET 3)

X I
2\

~.

\.
X3

I

KEYBOARD AND
KEY
SCAN

0~ ffi~' /
f/

BlAIS]

TO PRINT
BUFFER·
(SHEET 3)

..
~

lOR (I/O READ)

~

lOW (I/O WRITE)

.1

C.

b

(10/20 ONLY)

3"

TV INT

" B.A [3]

J

..

IO~

V UNBLANK
2

f\

~

DISPLAY
MEMORY
AND
SCRATCHPAD

l CI RCU ITS
(SHEET 2)

:
I

L _____

\l-..,

J

BATCH

EOM A&B
WRAPAROUND

~

f""-

B.A[4]

b

N

......,
r-,?
a
......

CQ

.-f

III

\0

......
f""-

~

r--...l:'- --1
:
TV
I

LEAD IN (ESC/"')

~
.....

CQ

QUEUE

~SET

o

~

PROGRAM
MEMORY
(ROM)

MW (MEM WRITE)

ALL CAPSt----V-I-DE-O-----.

STATUS
LATCH

IORt

-r)

:~ECTIONS

LF /CR

R

2 f-

T

,/~

MR (MEM READ)

MICROPROCESSOR

~~

MODULE

KEYBOARD
ENCODER

I-B-.A-[O'\I-I-SJ-.J'It\~--------AD-DRE-S-S-B-U-S---------~''\)......:...-...:.---'

1

SHIFT

10~

9

Y~ __ / Y2

~!j

S~;}CH

X r--,y

~

I
Y

SWITCH

REFRESH
ADDRESS

lO

~

ItIOW

0

.I HALF/FULL

I'

UP/LOW

2

- - - - ---SERIAL 1 / 0 - - - - - - - - - ,

0

0
.......

CQ

0

COUI~TER

~~2.__-D-AT-A-S_ET-READ---Y~,-C~LEAR~~TO~S~E=N~D----~--

BXMT
REG
(10/20 ONLY)

L"";:..

STATUS
REG R2

XMIT BUFFER EMPTY

TO PRINT

BUFFER
(SHEET 3)

I/O
INTERRUPT

I

SERIAL OU':£. c.a
t-

HOLD
TV
INTERRUPT

BUS

DISABLE

....

1

;:::'
~
B.A[6,7]

2

I

...

~S

N

T

.-f

0
......
CQ

..........~

I

LI

II)

-.LOCAL

~
~

ADDRESS
l?ECODER

WRITE STATUS

...
ALAm

1

r

READ UART

STATUS
REG R3

RECEIVE DATA RESET
3
I

BREAK, REQ. TO SEND, DATA

T~RMINAL

READY

I

7704061

rigure 1-3. Terminal, Block
Diagram (Sheet 1 of 3)
1-12

TO REFRESH ADDRESS COUNTER (SHEET 1)

~

.... V UNBLANK
TO
STATUS
LATCH { .... TV INT

i

i

COUNT BUFFER ENABLE

COUNTER CLOCK
HORIZ DRIVE

TV SYNC

~

Co
TO
MICROPROCESSOR
(SHEET 1)

... TV

I....

INT
LINE
BUFFER

BUS DISABLE

LINE
COUNT

CLEAR
VIDEO
SR

VIDEO
CLOCK

CLOCK

l.:"

MONITOR

VIDEO

I--'
I
I--'

~,

\

DBI0'l07] )

r

4"

LOAD

W

FROM
DISPLAY
MEloI)RY
(SHEET 1)

....

VERT DRIVE

,

,Ir

LINE
BUFFER
AND
REGISTERS

7

,~

.

CHARACTER
GENERATOR

"
7
I
I

.

FOREGROUND

VIDEO
SHIFT

REG.

o

W
~

I CONTRAST I

..

.1
-r
Y

VIDEO
AMPL

---.

..
VIDEO

"'w
FROM KEYBOAIU) "
SWITCH MODULE
(SHEET 1)

7704062

l-3~

H
I
I--'

U1

j~REV

Figure

::x:

Terminal, Block Diagram (Sheet 2 of 3)

PRINTER BUFFER iH15201

RESET

r

I

INPUT/OUTPUT COMMANDS

-

L.

..1

'\

rr

I'

I

H

I

61

I

PRINT DATA BUS DB[O'V7]

I'''''''' . . . ~ 'I

WRITE
PRINTER
DATA

TIOR
lOW
p

WRITE
PCNTL

",
..J

M

I
C
R

~ ...... "",'?

READ
PSTAT

/L

PCNTL
REGISTER

H

P
R

I
I-'

0

U1
W
~

o

C
E
S
S

............ /

ADDRESS
I ' - - REGISTER

:::x::

0

I'-

PARALLEL OUT[7]

0

I+--

v

R

PRINTER STROBE

~

,

~.

'I.

PRINTER BUSY
SERIAL OUT
p

,LPRINTER DOWN

PSTAT
REGISTER

-

r"

Figure 1.-3.

..

PRINTER ACK
ADDRESS

111

&

SERIAL/
PARALLEL
SWITCHES

I/'

PRINTER
MEMORY
(RAM)

ADDRESS
DECODER

I/'

II'

.

"\

p

GoA[O ,11 ')

-~

~----A_

1\

~

READ
PRINTER
DATA

T

BAUD
RATE

I

"

I

flOB[O'C

PRINTER
I/O BUFFERS

2

-

---

SERIAL BUSY

ON LINE SW/OUT OF PAPER /
j

Terminal, Block Diagram (Sheet 3 of 3)

HI-1053A
HEX
- 0000

DECIMAL
0PROGRAM
MEMORY
(4096)

OFFF

1t09,!

HEX

DECIMAL
0

-

- 0000

14,207
11t,20r

07FF

14,287
11t,288
12,288

11t,335

3000

DISPLAY
MEMORY
(1920)

DISPLAY
MEMORY
(1920 )
REGISTERS
(80)
STACK
(48)

377F
- 3780
37CF
3700
37FF

377F

14,207
14,208

- 3000

12,288

PROGRAM
MEMORY
(2048)

3780

SCRATCHPAD (128)

14,335 _

QUEUE
(256)

27FF
MODEL 1500

Figure 1-4.

_ 50FF

20,735_
MODEL 1510/1520

Memory Address Structure

The 1510 and 1520 models have an additional 256 x 8 queue, used
for storage of all input characters, and for output characters
in batch transmission mode. The address structure for input/
output (I/O) is simpler since there are only five addresses.
Address bits are used to address I/O, with one or two bits low
(logic 0) designating a particular unit as follows:
Bit(s) Low

I/O Unit

Keyboard Status Latch (Read only)
Refresh Address counter (Write only)
Keyboard Encoder (Read only)
UART
I/O Status (R2 if read, R3 if write)
Batch Transmit Status Register (Read only)
Print Buffer

B.A[3]
B.A[4]
B.A[5]
B.AI6]
B.AI7]
B.AI6&7] (1510/1520)
B.AIO] (1520)

Printer Control/Status (PCNTL if write,
PSTAT if read)

B.A[l] (1520)

1-15

HI-1053A
1.3.1.2 Operation of the terminal may be divided into three major
categories: (1) data transfer, (2) TV refresh, and (3) character
processing. These operations are described in the following paragraphs, followed by a more detailed description of the more complex circuits.
1.3.2

Data Transfer

Eight types of transfer are performed:
1.
2.
3.
4.
S.
6.
(1520

keyboard to microprocessor
I/O to microprocessor
microprocessor to I/O
microprocessor to memory
memory to microprocessor
memory to video

~n1y:)

7. microprocessor to printer buffer
8. printer buffer to microprocessor
All but one are controlled by the microprocessor. Control of
transfer from display memory to the video circuits is shared by
the tv sync circuits and the microprocessor.
1.3.2.1 Keyboard to Microprocessor. Each character key is
located at a unique junction of 9 scan lines (designated X) and
10 output lines (designated Y). The keyboard encoder continuously
excites the 9 scan lines, one at a time, and looks for a signal
at the output lines. When a key is depressed a unique XY combination is recognized, which, in .combination with the control and/or
shift keys, addresses a memory location in the keyboard encoder
in which the appropriate a-bit character code is stored. When any
character is detected, a keyboard data ready (KBDR) signal is
applied to the status latch. The microprocessor periodically reads
the status latch condition (lOR and B.A[3]" low) and, when the
KBDR condition is read, enters the keyboard service routine. The
microprocessor then reads the keyboard data (lOR and B.AlS] low)
transferring the character code to the microprocessor. If the same
character is input two successive times with less than a 6 millisecond interval, it will be rejected. This prevents accidental

1-16

HI-I053A
double entries due to switch bounce.

Otherwise the character will

be processed as appropriate for the modes and switch options in
effect.
1.3.2.2

I/O to Microprocessor.

The universal asynchronous

receiver-transmitter (UART) is continuously ready to accept serial
inputs.

When a serial input is received, the UART stores it in

an input buffer and generates an I/O interrupt signal.

This causes

the microprocessor to interrupt whatever it is processing and do
a data I/O service routine.

The UART is addressed and the charac-

ter transferred to the microprocessor in parallel on the data bus
(7 bit ASCII plus a 1 for DB[7] if a parity error is detected
by the UART).

The microprocessor then updates status register R3

with a receive data reset bit, which, in turn, resets the UART
I/O interrupt signal.
1.3.2.3

Microprocessor to I/O.

When a character is ready to be

transmitted, the microprocessor enters a send character subroutine.
Status register R3 is updated with a request-to-send bit which
is transmitted via the serial I/O buffer.

The microprocessor then

reads status register R2 to determine the status of the clear-tosend, data set ready, and transmit-buffer-empty (TBMT) signals.
When the necessary conditions are met (TBMT in half duplex; data
set ready and TBMT or data set ready and clear-to-send and TBMT
in half duplex), the character is written in parallel into the
UART transmit buffer.

The UART inserts start, stop, and parity

bits and transmits the character via the serial I/O buffers.
1.3.2.4

Microprocessor to Memory.

When a new character is to be

displayed, the microprocessor addresses the display memory location
corresponding to the current cursor address (which the microprocessor keeps track of by tracking cursor movements), writes
the character into the memory location, and increments the cursor
to the next character slot.
1.3.2.5

Memory to

Microprocessor~

Any word in the program memory

or the display memory can be transferred to the microprocessor by
a memory read command along with the appropriate address as
indicated in figure 1-4.
1-17

HI-I053A
1.3.2.6

Memory to Video.

Transfer of display data to the video

circuits, which store one row of characters at a time, is
synchronized under control of the tv sync circuits.

Each charac-

ter occupies an 11 tv line window as shown in figure 1-5.

At the

beginning of line 10 of each 11 line character row, the tv sync
circuits generate a bus disable signal.

This signal causes the

microprocessor to go to a hold status.

The bus drivers are set

to the high impedance state, reserving the address and data buses
for transfer of the display data.
line buffer to load the data.

The same signal enables the

A count buffer enable (CTBEN)

signal enables the refresh address counter, which then controls
the address bus.

Eighty counter clock (CNTCLK) inputs to the

counter cause 80 consecutive characters to be transferred to the
line buffers.

At this time, the bus disable signal is discontin-

ued and control of the buses is returned to the microprocessor.
Since 11 tv lines are required to display a complete character
row, no display data transfer is required until line 10 of the
next row.

At the beginning of line 2 of each row, a tv interrupt

signal is generated.

This signal causes the microprocessor to

r - -- 0
1

-

2

3

UJ

z

-'

>

I-

4
5

6
7
8

-9
10

I

I

I

I

I

.-

I

,,

I

I

i

J

,

I
I

t

I
L -

--.-

I

1-- .

I

I

- - ---

UPPER CASE
DOT MATRIX (7X8)

I

J

I

I

j

i

-----"I

I

,

,

I
I
I

-1--- -

-

;

I

I
I

-

I

,

,

--

:
I

;

,

i

!

I
I

i

I

I

CHARACTER
WINDOW (9X11)

I

i

I

-i-I

i

-V

I

I

i

I
I

I
i

1

I
i

Ii

\

I

I

~

LOWER CASE
DOT MATRIX (7X8)
7704039

rigQre

1-5.

Chqrqcter Formqt
1-18

HI-I053A
interrupt whatever it is doing and enter a tv service routine.
The microprocessor then calculates the address, in display memory,
of the start of the next row to be refreshed (the microprocessor
counts tv interrupts to keep track of where the tv refresh is) .
This address is written into the refresh address counter in preparation for the transfer of the next row.
on the data bus DB [0

~7],

to address bits B.A[3

~

the counter [0

~

The address is transferred

but into counter locations corresponding

10].

The least significant four bits in

3] are set to O.

The resolution of the address

load is 16, which is adequate because all starting addresses are
multiples of 16 (80
1.3.3
1.3.3.1

=

16 x 5).

TV Refresh
The tv circuits block diagram is shown in sheet 2 of

figure 1-3.

Transfer of a row of characters to the line buffers

was described above.

The tv sync circuits divide and decode from

an internal 33.264 MHz oscillator to produce the various timing
signals needed to synchronize the display.

The line buffer clock

causes a new character code to be transferred from the buffers to
the character generator every 9 tv dot intervals.

The character

generator is programmed with the dot pattern for each displayable
character.

The character code, plus the decoded line count,

addresses the dot pattern for a particular line of the character.
The dot pattern is then transferred in parallel to the video
shift register.

The video shift register clocks the video serially

through the video amplifier to the monitor.

The video amplifier

output is at medium intensity for background characters, and high
intensity for foreground characters, determined by the most
significant bit of the character code in the line buffer.
1.3.3.2

At the end of each line and during vertical' retrace, a

clear video shift register (CLR VID SR) signal clears the shift
register and disables the video amplifier input.

This signal is

a composite of either horizontal or vertical blanking.

The charac-

ter codes stored in the line buffers are recirculated eleven times
(line number 0 through 10) and a new row is loaded at line ten.

1-19

HI-I053A
1.3.4
1.3.4.1

Data Processing
All data processing is performed by the microprocessor

by performing the program stored in program memory.

consists of four primary modules
Filter~

(Executiv~,

The program

Keyboard Service,

and Initialize), an interrupt subroutine, and several

detail subroutines.
shown in figure 1-6.

Flow Charts for the model 1500 program are
Table 1-3 explains abbreviations used in

the flow charts.
1.3.4.2

The overall program flow is shown on sheet 1 of

figure 1-6.

At power turn-on, or when the RESET button is pressed,

the initialize routine is performed.

This clears old data from

storage and sets up the microprocessor initial conditions.

The

screen is cleared for a power up reset, but not for a pushbutton
reset.

The executive routine is then entered.

This program

causes the processor to look for work, and is repeated continuously
until interrupted by an "interrupt" input.
the INTRP subroutine to be performed.
interrupt, it services the

t~

An interrupt causes

If the interrupt is a tv

refresh function described in

paragraph 1.3.3; if it is an I/O interrupt, it transfers an I/O
character to the input queue.

Data in the processor registers is

pushed into the scratchpad while the interrupt is serviced.

After

the interrupt, the data from the scratchpad is popped back into
the registers and the interrupted routine is resumed.
service may be interrupted by a tv interrupt.

An I/O

In this case, the

I/O data is pushed down, the tv refresh is serviced, and the I/O
servicing is resumed.

When the EXEC routine is performed, the

queue is checked for a character to be processed.
is available, the filter module is entered.

If a character

This module performs

the actions appropriate for the particular character, calling
subroutines as necessary.

When the filter routine is concluded,

the executive routine restarts.

If no character is in the queue,

the keyboard is checked ,(unless in keyboard lock condition).

If a

keyboard character is available, the KBSVC (keyboard service)
routine is performed.
tion.

This routine includes double-entry preven-

If a key is held down, only one entry will be made until

1-20

HI-1053A
Table 1-3.

Terms and Abbreviations Used in Program Flowcharts

Abbreviation/Name

Description or Usage

ALCNT
Alarm Count

Used to time audible alarm. Set to 20 when BEL character
is decoded or a parity error is detected. Decremented
by each vertical unblank.

BKCNTR
Break Counter

Used to time break. Set to 14 when BREAK key is decoded.
Decremented by vertical unblanking.

CA

Flag raised when request-to-send is output (EIA CA signal).

CADDR
Cursor Address

Refresh memory location corresponding to present cursor
position.

CI

Set when cursor is over a character other than space.
Used to control interchange of cursor and character.

Cursor Interchange
Flag
CICNT
Cursor Interchange
Counter

Used to time interchange of cursor and character. Set to
20 when cursor is moved to character position and to 10
each time an interchange is implemented.
Decremented by
each vertical unblank.

CURSX, CURSY
Cursor X and Cursor
Y address

Character number (X) and row number (Y) of present cursor
position as measured from left or top of display.

CX

Set when X part of direct cursor address command has been
implemented. Used to indicate that next address will
be Y.

Flag
EOC
End of character

Signal from UART when last bit of a character has been
transmitted from serial output buffer. Used to determine start of delay at end of half duplex transmission.

FLAG 1, FLAG 2 (1500)
Flag Registers No. 1
and No. 2

Number 1 stores Lead In, RA, CX, CI, Pass 1, Pass 2,
Foreground, and KBLOK flags.
Number 2 stores CA, Alarm,
Break, and data ready reset flags.

FLAGS 1 through 7
(1510/1520)

Status flags.

KBCNT
Keyboard Count

Used to track time a key is held down. Set to 48 on 1st
pass (delay) and to 4 on 2nd pass (repeat rate).
Decremented by each vertical unblank.
Reset when key
released.

KBLOK F
Keyboard Lock Flag

Set by keyboard lock character (~cU).
Reset by keyboard
unlock command or initialize module. Keyboard will not
be read when set.

KCHAR
Keyboard Character

Last keyboard character. Used for comparison with present
keyboard character to determine if same or new character.

LEADP
Queue leading
pointer

Address in buffer at which next I/O character is to be
stored.
Incremented as each character is stored.
Reset
when end of buffer is reached.
See TRALP.

LOP

Number of rows, from start of refresh memory to memory
location of top line of display. Used with RLP to
calculate starting memory address for next line to
be refreshed.
Incremented with each rollup.

Line zero pointer

PASS 1, 2
Keyboard pass flags

Indicates number of consecutive times the same character
is read from keyboard. Used to prevent double entries
and control typarnatic operation.

RA
Read cursor address flag
RLP
Refresh Line' Pointer

Set when a command to send cursor address is received.
Number of the next row to be
each tv interrupt. Reset to
Used to control the starting
address counter at the start

1-21

refreshed.
Incremented at
0 each vertical retrace.
point of the refresh memory
of each row.

HI-I053A
Table 1-3. Terms and Abbreviations Used
in Program Flowcharts (cont)
Abbreviation/Name
Description or Usage
---~~~~~~~----------+--------------------------~-------------------------------------------------------~~-----~~
TAB PASS 1
Set during tab. Used to limit search for background
foreground (unprotected) field.
Signal
from UART indicating that serial output buffer
TBMT
is empty.
Transmit buffer
empty
Register (located in scratchpad) used for temporary
TMPST
storage during a particular routine.
Temporary storage,_
register
Address in buffer of oldest I/O character not processed.
TRALP
Incremented as character is stored.
Queue trailing pointer
Count
used to control blinking of FORMAT lamp during
XCNT
transmit.

approximately 0.8 second (48 vertical unblankings) and typamatic
operation will then be performed.
of figure 1-6.

The routine is shown on sheet 4

The tables noted in the flow chart are conversion

charts for lower case to upper case and keyboard encoder to ASCII.
On completion of the keyboard service, the executive routine is
restarted.

The subroutines used to implement the various terminal

functions are shown in the flow charts.

In reading the flow charts,

the following terms and conventions should be understood.
o

A (D) or (H) following a number indicates decimal or
hexi-decimal notation.

o

A module (sheets 1 through 4) ends with an exit which
specifies the routine to start next.

A subroutine ends

with a "return" which exits to the point from which the
subroutine was called.
o

A "call" inserts the subroutine called into the flow of
the calling routine.

The calling routine is resumed

when the subroutine is completed.
the routine.

A "jump" terminates

If the jump is to a subroutine, the exit

from the subroutine resumes the routine from which the
calling routine was called.

1-22

HI-1053A
Executive and Index
MNEMONIC
ADJCP
CBEOS
CHOME
CISAV
CLEFT
CLEOL
CLEOS
CLFG
CLSCR
CR
CURDN
CURMA
CURUP
DLINE
EXEC

FUNCTION

SHT

Adjust cursor position 8
Clear to end-of-screen 6
(background)
Home cursor
7
Save character in
8
cursor interchange
register
7
Cursor left
6
Clear to end-of-line
Clear to end-of-screen 6
15
Clear foreground
6
Clear screen
Carriage return
10
Cursor down
7
Cursor memory adjust
8
Cursor up
7
9
Delete line
Executive
1

FUNCTION

SHT

Filter
Foreground Tab
Insert line
Initialize
Transfer character to
input queue
Interrupt
Keyboard service
Line feed
Pointer
Direct cursor address
Rollup
Send cursor address
Send character to
UART
Calculate Y memory
address

3
15

MNEMONIC
FILTER
FTAB
ILINE
INITIALIZE
IN QU
INTRP
KBSVC
LF
PTR
RADDR
ROLUP
SADDR
SEND CHAR
YMA

POWER
UP

PUSHBUTTON
RESET

INTERRUPT

INITIALIZE

I EXECUTiVE

I

IL _ _ _._ _ _
7704052

Figure 1-6.

Flowcharts (Sheet 1 of 16)
1-23

9

2
13
5
4
10
6

11
9

13
12
14

HI-1053A
Initfalize
- - ...... _. .. _.
~

RST0 :
INITIALIZE

SET RLP

="
SET LEADP =
TRALP = B8CH)
SET BKCNTR,
KBCNT, ALCNT,
KCHAR, CICNT,
FLAG!, FLAG2,
TEMPS-r: = s
F

HDUPL:
SET r5RR, !ITt
TO 1; eA, CD BRK,
TV8LNK TO ,

SET ORR, BELL
CA TO 1;' BRK
CD, TVBLNK TO

e

F

SET
BACKGROUND
FLAG

FOR USE WITH
AUTO TEST EQUIP

JUMP TO
TEST PROG

Figure 1-6.

7704055

Flowcharts (Sheet 2 of 16)
1-24

UONLY:
QCHAR

! '"
T

::I:

H

I

.....

o

.....

U1
W
~

I

N
U1

RLIOP:
RESET LI.
RA. CX FLAGS
CALL
RAODR

LOOKUP TABLE
ENQ CALL SADDR
AC" CALL RACK
VT
CALL CURON
Ff
CALL CURUP
DC 1 CALL ROC 1
OC2 CALL CHOME
DC} CALL DLINE
NAK CALL .WAIe
EM
CALL REM
sua CALL ILINE
FS
CALL CLSCR
GS
CALL CLEOS
51
CALL CLEOL
US
CALL RUS
ETB CALL CBEOS
fLSE CALL ROUT

" .... a

Figure 1-6.

Flowcharts (Sheet 3 of 16)

HI-1053A
Keyboard Service
TYPO:
T

NEWCH:

F

RESET PASS1,
PASS2

SET PASS2

EXEC

T

T

F

FUNC:

CONVERT CHAR
WITH TABU

F

CALL SEND
SEND CHAR

CALL
CALL CHOME

SET BKCNT = 14(0)
INVOKE BRK
CALL SETPT

CALL CLSCR
CALL CLEOL
CALL CLEOS
CALL CLFG

INVOKE
CURSOR UP
INVOKE
CURSOR HOME
INVOKE
CLR SCREEN
INVOKE
CLR END OF LI NE
INVOKE
CLR END OF SCR
INVOICE
CLR FOREGROUND

KEXIT:

Figure 1-6"

Flowcharts (Sheet 4 of 16)
1-26

HI-1053A

Interrupt

F

FINI:

7704054

Figure 1-6.

Flowcharts (Sheet 5 of 16)
1-27

HI-I053A
Clear Screen and Pointer

no....

Figure 1-6.

Flowcharts (Sheet 6 of 16)
1-28

CURUP

CURON

)

~-

F

n

F

~

t1

Ul

0
~

t1

F

I

t-.)

~

ADD CHANGE
TO CURSX

\0

0

c::

CD

T

UPDATE
CURSX

=

JUMP
CURMA
7704011

Figure

1-6~

Flowcharts (Sheet 7 of 16)

::c

H
I

~

0
U1
eN

)I

HI-I053A
Cursor Interchange Save and Cursor Memory Adjust

CURMA

CISAV

CALCULATE NEW
CADDR FOR CX"
CY LOCATION

CLEAR CI FLAG

T·

STORE
IN CADDR
ADJCP:
MOVE CHAR @
RAM CADDR TO
[CIC]

MOV [crc] TO
DISPL RAM
(CADDR)

RETURN

MOVE CURSOR
CHAR TO RAM
CADDR

T

SET cr FLAG

SET CICNT

= 20

RETURN
7704057

Figure 1-6.

Flowcharts (Sheet 8 of 16)
1-30

HI-I053A

Rollup and Insert/Delete Line

INCREHENT
fLAG

VECTI
VECT2
UNEP
ENDP

COHPL:
CLEAI! LINE
POINTED TO BY
LAST VECTl

(fRO" ADDR) USES
REGISTERS H, L
(TO ADDR) USES
REGISTERS D, !
NUMBER Of LINE
TO B! HOVED
LINE NO. WHICH
DETU"INES END
Of LOOP

".ton

Figure 1-6.

Flowcharts (Sheet 9 of 16)
1-31

HI-1053A

Carriage Return/Line Feed

CAll CISAV

T
F

JU~1P

SET PTR
ADDR
OF END OF NEXT
lINE

CURMA

SET STOP COUNT
OF
NEXT lINE

= BEGINNING

CYCll:
t-10VE ASC I I
SPACE CODE
TO PTR ADDR

DECREMENT
POINTER

=

CR/lF SWITCH
1
CR = CR+LF
IF = NOTHING
CR/lF SWITCH
J
CR
CR
LF = LF

=

=

INCREMENT
L~P

Figu~e ~-6~

Flowcharts (Sheet
1-32

lO of 16)

770.0 . .

HI-I053A
Direct Cursor Address

RADDR:
DIRECT CURS
ADDRESS

INPUT BYTE IN
REGISTER A

!
CALL CISAV

-l
GET INPUT BYTE

i
F

T

CX FLAG
I?

=

~

T

DOY:

,

'III

MASK WITH IF(H)

INPUT<96?
F
SUBTRACT 96
FROM INPUT

F

VALUE '>23?

.

iT"

NOCHG:

..

VALUE '>79?

f

SET TO 23

T

SET TO 79
NOSET:

MOVE TO CY

!

MOVE TO CX

...

~

!

...

RESET RA, CX,
LEAD IN FLAGS

!

!
......

SET CX FLAG

CALL CURMA

RETURN
7704045

Figure 1-6.

Flowcharts (Sheet 11

1-33

of~16)

HI-1053A
Send Character

SEND:
CHARACTER

RAISE REQUEST
TO SEND AND
SET CA FLAG

F

FULL DUPL?

CHARACTER PASSED
IN REGISTER 8

T

T

TRYAG:
CLEAR TO
T
SEND? (C8)

F

F

MOV CHAR
TO UART

F

T

DELAY GOOus
F

T

F

F
DELAY lrns

RESET RTS

& CA FLAG

RETURN
7704046

Figure 1-6.

Flowcharts (Sheet 12 of 16)
1-34

HI-I053A
Send Cursor Address and Queue

SADDR:

INQU:

SEND
ADDRESS

MOVE CHARACTER
TO ADDRESS
POINTED TO
BY LEADP

l
DELAY
30ms

INCREMENT
POINTER

~
GET CURSX

F

i
F

T

SET POINTER
TO START OF
BUFFER

CURSX < 321
~

,

ADD 6,,(H)
RETURN
.........

CALL SEND

...""'

!
GET CURSY

!
ADD 60(H)

!
CALL SEND

~
MAKE tCRt &
CALL SEND

!
RETURN
7704047

Figure 1-6.

Flowcharts (Sheet 13 of 16)
1-35

HI-I053A
Y Memory Address

YMA:
GET MEM ,ADDR
FROM LINE NO.

CALL PTR

INPUT LINE NO.
IN REGISTER B

(L~P +·LINE NO·)MODULO

24 X 5

REVERSE 2
HEX DIGITS
IN BYTE

MOVE LSB TO
STORAGE 1 WITH
3(H) AS AN MSB
(HI BYTE ADDR)
MOVE MSB TO
STORAGE +1
WITH 0 AS
AN LSB
(LO BYTE ADDR

RETURN

XI6

THE CALCULATED ADDRESS IS
RETURNED IN REGISTERS H, L
770404.

Figure 1-6.

Flowcharts (Sheet 14 of 16)
1-36

HI-1053A
Clear Foreground

CLFG:
CLEAR
FOREGROUND
CALL
CISAV
SET PTR = 30~0(H)
SET CNTR = 192~·
T

F

MOVE FG SrAC~
TO MEMORY

INCREMENT
POINTER
DECREMENT
COUNT

= 0?

F

T

SET CURSX,
CURSY = ~
DETERMINE
NEW CADDR

7704050

Figure 1-6.

Flowcharts (Sheet 15 of 16)
1-37

HI-I053A
Foreground Tab

F
T

RETURN

JUMP CURMA

Figure 1-6.

1.3.5
1.3.5.1

Flowcharts (Sheet 16 of 16)

Reset, Interrupt and Wait Functions
Figure 1-7 is a block diagram summarizing the reset,

interrupt, and wait functions.

At power turn on, the +5 volt

supply charges a capacitor at an input pin of the clock generator
and driver.

This input triggers a PU RESET output which resets

the pushbutton reset flip-flop (U47), resets the microprocessor,
refresh address counter, printer buffer video circuits, UART, and
control status register, and sets the bus ready flip-flop (U62).
The RESET button has the same effect, except the pushbutton reset
flip-flop is set.

This status is transmitted to the microprocessor

via the status latch, allowing the microprocessor to distinguish
between a power up reset and a pushbutton reset (the screen is
cleared for a power up reset but not for a pushbutton reset).

1-38

RESET

CLOCK
GEN &
DRIVER
U8

PU RESET
S

FF
U52
(U47)

DB[2]
STATUS
LATCH
U50
(U45)

B.A[l]

REFRESH
ADDRESS
COUNTER
Ul
US
U7

TV

SYNC

CONTROL
STATUS
U69
(U64)

FF
U67
(U62)
EN

KEYBOARD
ENCODER
USS

B ROY

K/B BUS ACTIVE

:I:
H

I

~

~

I

o

\0

U1
W

w

~

B.A[S]
B.A[6,7]

I/O
ADDR
DECODER
U46
(U42)

L--~""';""---'

Ito WAI

K/ B

READY

Q
B WAIT

= TEST POINT

AT PIN N
LOCATION U77
lU48)

REF DES IN PARENTHESES APPLIES FOR
PART NO. 4DTD15S202 WHERE DIFFERENT
HOLD

7710056

Figure 1-7.

Reset, Interrupt, and Wait Functions, Block Diagram

HI-l053A
1.3.5.2

As long as the B RDY (bus ready) signal is present, the

clock generator and driver applies a ready input to the microprocessor and the microprocessor runs at a rate determined by
the clock generator.

The reading gate, however, is too fast for

the keyboard encoder and UART; hence special provisions are made
for these devices.

When the keyboard encoder is enabled for a read

cycle (lOR and B.A[5] low), a K/B READY signal resets FF U67 and
interrupts the B RDY signal.
delay reading the date.

This causes the microprocessor to

When the keyboard encoder data output is

stable, it generates a K/B BUS ACTIVE signal which sets FF U67 and
restores the B RDY signal.

The microprocessor then latches the

keyboard data.
1.3.5.3

When a read UART data cycle is initiated, it generates

an I/O WAIT signal which resets FF U67 via NOR gate U55 and enables
one input to NAND gate U97.

Interruption of the B RDY signal

delays the microprocessor read cycle as described for the keyboard
above.

The microprocessor acknowledges this status by generating

a B WAIT signal.
FF U67.

This signal enables NAND gate U97 and sets

The delay involved is sufficient to ensure that the UART

data output is stable when read.
1.3.6

Serial Input/Output

1.3.6.1

The overall function of the serial I/O circuits was

described in paragraph 1.3.1
gram of the circuits.

Figure 1-8 is a detailed block dia-

The baud rate DIP switch settings are

decoded to control the clock generator operation.

The clock

generator divides the crystal frequency as required to produce
a clock frequency at 16 times the selected baud rate to drive
the UART.

When a 110 baud rate is selected, an input is applied

to the UART which causes it to insert two stop bits in each serial
output character; otherwise, one stop bit is inserted.

The UART

also inserts a parity bit and checks input parity in accordance
with the parity DIP switch selection.
1.3.6.2
any time.

Serial data and control signal inputs may be received at
Control signal status (CB,

status register 2.

ee,

CF inputs) is stored in

Data is stored in the input buffer and an I/O
1-40

J

BAUD RATE
DIP SHITCHES

l

J2

2400

REF DES IN PARENTHESES
APPLIES FO R PART NO.
4DTD155202 WHERE
DIFFERENT

PARITY
DIP
SWITCHES

I
I

~

r

-RE SET
& INT
LO GIC
..
FI G.1-7 I/O
WAIT

~~

RECEIVED
DATA

lOW

.

•

v----MHz

1

U56
(U51)

r-----...

BREAK
I

~ nEG 3

-v)

DATA
U54
(U49)

CONTROL REQ TO SEND
A
ST TUS DATA TERllINAI
U69 (U64)

f""

LOOP

CA
CD

U70
(U65)

Lr

~

.....

f""

~

REG 2
I/O STATUS

U46
(U42)

I

U57
(U52)

,...
-....

BB

-

TRMlSHIT
• BUFFER EI1PTY

READ
STATUS

PB [0, 3....7J

DATA CARRIER DET
DATA SET ROY
t.t
IA CLEAR TO SEND

I~

2
4
20

3
L--

\-IRITE
STATUS

i---

BA

FROM
CURRENT

I~

U43)

V--

.-

~

\O!RITE
DATA DATA

~-

.-

.13

1~0 CURRENT

1

-.

LARt1
SPI

SERIAL
IN

~

C8SI; III I CASE

ROY

I' ~

READY
SESET

l~EAD

III

16X CLK

SERIAL OUT

DB

RCVD DATA AVAIL

V LOCALDECODER
ADDRESS
-.

I-(NOT USED)

OUTPUT
BUFFER

--

END OF
CHAR

I DB [6,7f\

_
lOR

2 STOP
BITS

PARITY
ERROR

•

I
I

CLOCK GEN
Y2
U45 (U41) 5.0688

umvenSAL
ASYNCHRONOUS
RECEIVER-TRANSMITTER

DB [0 . . . 6]

TCl

~4

-..

.-.

\ TRANSMIT
DATA
vi

U47
(U43

ENCODER
U45 (U39)

ENCODER
U44 (UltO)

I/O
jNTERRUPT
TO
MICROPROCES SOR .....

lOB [0-6]

I
I

III

4!

,t

8~1-'

r-

Jl
AUX r -

U47
U43

RA

4 lAuxlLIARY

...-...

AUX
Cc

OUTPUT
r-----iI BUFFEr.
U48
~
(U44)

6

8
AUX
CF ' - -

~

INPUT
BUFFER
U58
(U54)

3

L..

ro

~

.....

L..

...

CF
~

CB

..........8

6

5
'--

J2

HALF OX FULL OX

7704064

Figure 1-8.

Serial Input/Output, Block Diagram

HI-I053A
interrupt signal is applied to the microprocessor whenever a character is received.
1.3.6.3

The remaining functions are controlled by the microproces-'

sor via the local address decoder.

By the appropriate control and

address bits, the microprocessor can command anyone of four
operations as follows:
Operation

Function

Read data

Causes the received data in the UART
input buffer to be transferred to the
microprocessor (along with a parity
error bit if an error is detected)
and causes an I/O wait as described
in paragraph 1.3.5.3.

Write data

Causes data from the microprocessor
to be transferred to the UART
transmit buffer from which it is
automatically sent as serial output.

Read status

Transfers the contents of status
register 2 (and the UART end-ofcharacter bit) to the microprocessor.

Write status
1.3.6.4

Updates status register 3.

When input data is read, the microprocessor transmits a

data ready reset bit to register 3, which clears the UART input
buffer.

Register 3 also stores the control outputs (request to

send and data ready), the break, and the alarm (BEL) controls.
1.3.7
1.3.7.1

TV Synchronizer
The overall function of the TV sync circuits was described

in paragraph 1.3.1.
the circuits.

The horizontal circuits are shown on the top half

of the diagram.
flop generate

Figure 1-9 is a detailed block diagram of

t~e

The 33.264 MHz oscillator and divde-by-two flip16.632 MHz video clock.

This is the dot fre-

quency (one pulse for each of the nine horizontal resolution
elements of each character (figure 1-5).

1-42

The divide-by-nine shift

HI-1053A
VIDEO CLK

r

!I
33.264 MHZ
OSCILLATOR ~
Y3 U98 (U87)

f2
FF
U104
(U86)

DOT
CTR
t9
SR
UI05
(U88)

I

ft. .....

If
\\

\\

o

1-+

\

U77-6
(U48-8)

I,

\

3 :

\

.I

(II)
~~

DOT .....
NOOT .....

DOT
CT
REG
r----,
U99
(U81) r

r

--

LINE BUFFER CLK .....

U89
(U60)

H MEM SLOT DLYD

I

I

II

I

I

I

CHAR
CTR
U91
UIOO
-(U69)
(U70)

4

/+
/

/

7

--;-.

HORIZ
SYNC
PROM
U90 (U71)
& DECODER
U78 (U72)

RESET

H DRIVE .....
r

HOR UB

) U89 ~
(U60)

VIDEO BUS

9

-

5

r

-

~

( gO)

19

--

U75
I~ (U89)

I

01

U72

;-~

I

./

I~

ROW CTR
LINE CTR
f11
U84

'--.

......

r

U87 (U85)

LC2 3·....

24/28

f14
U95
(U90)

f2
U103
(U95)

U

CLEAR!

4"~

0=

---.

r

If
B RESET

,

REG

VERT

15L

TIMING
GATES

30L

....-

VERT
UNBLANK
DLYD
REG
U102
(U95)

VERT
DRIVE
- REG
U87
----..
(U85)

VERT DR ... TO VIDEO
.
AND STATUS REG 1 _

~-

2L/3L

4
{

REF DES AND PIN NOS. IN PARENTHESES
APPLY TO PART NO. 4DTD155202

VERT UB ..... TO STATUS
.
REG 1

...

~

TEST POINT
PIN N
LOCATION U59 (U48)

-

~

UNBLANKED ROW

r.

I

FROM
KEYBOARD

VERT
UNBLANKING

BUS' DISABLE .....
. Ta MICROPROCESSOR
. AND VIDEO
U77-4
(U48-18)
CNT
U76
CLK .... Ta DISPLAY MEMORY
(U83

U77-2 ~
(U48-13 )

LINE 10 OF EACH

0

--

CTB EN ..... Ta DISPLAY MEMORY

(U89)

,

RT HAND MARGIN

J

r"

J U75

J100

(U83

!

CLR VID SR .....

U77-8 .
(U48-6)

(

U76

DISABLE

TO VIDEO

-

f

\

~761

....

TV INT ...

.. TO

MICROPROCESSOR

LC2 0""LC2 3... TO VIDEO

..

7704059

Figure 1-9. TV Synchronizer,
Block Diagram
1-43

HI-I053A
register outputs are decoded by the dot count register to produce
dot, Ndot and line buffer clock outputs during selected portions
of each character window.

A character counter output selects

addresses in the horizontal sync prom, and the decoded prom outputs are the basic horizontal sync signals.

The timing is shown

in figure 1-10.
1.3.7.2

The right hand margin outputs of the horizontal section

are counted by the vertical section to generate the vertical sync
signals.

A divide-by-eleven counter counts the eleven lines in

each character window.

An output at line 10 of each II-line char-

acter row enables the bus disable signal (which puts the microprocessor in the hold condition and enables the refresh address
counter output), and the CNT CLK,signal (which is the clocking
signal for the refresh address counter).

This synchronizes

transfer of a new row of characters from the display memory to
3
the video line buffers. The line count (LC20 ~ LC2 ) is also used
by the video line buffers to load a new input on line 10, and to
recirculate data on 'lines 0 through 10.

CHARACTER COUNTER

99 100 0 1 2 3 4 5

RESET (U59-10)

92 9394 95

84 85 8687 88

I

I

~------------~f~f----------I----~~~t-------

I

~~'----------~~~~s--------

VID BUS

~--~Jf~--------~

H MEM SLOT DLYD

~------~Sf~--------

H UNBLANK

~----~f~f-------~--~u~----------~

H DRIVE
------------------~H~------------~
{S

R HAND MARGIN

----------~H----------~~J

i

COLUMN NO.

1

2

77 78 79 80

i
-../

I
I

~541

ns
7704041

Figure 1-10.

Horizontal Timing
1-44

HI-l053A
1.3.7.3

The line counter output is divided by 28 and decoded to

form the vertical sync signals.
1.3.8

Microprocessor

1.3.8.1
cuits.

Timing is shown in figure 1-11.

Figure 1-12 is a block diagram of the microprocessor cirBasic

~l

and

~2

clocks are, generated by the clock gene-

rator to drive the microprocessor chip.

These clock pulses occur

at a 2 MHz rate and a nominal 10 volts (9.4 volts minimum).

The

clock generator also generates a power-up reset signal, triggered
by the charging of an external capacitor, and synchronizes the
bus ready signal to the microprocessor.
1.3.8.2

During the first part of a processor cycle, synchronous

with the STSTB (status strobe) signal, a status word appears on
the microprocessor data bus.

This indicates the type of cycle to

be performed and is stored in the system controller status latch.
Depending on the type of operation to be performed, the gating
1

3

5

7

9

024

6

8

RHM(U83-3)

I I I

I

I I I

TV INT

I

RHM

TV INT

11

12

13

I

14

15

16

I

I

t
o

I

10

20 40

60

80

100

120

140

160

180

200

240
280
220
260
300

I I I I II I I I I I I I I I I I I I I I I I I

263

- - - - -I

V UNBLANK

307

L

-V DRIVE
14.29 ms

----.I -.f 1.-- 0 • 8

ms

7704063

Figure 1-11.

Vertical Timing

1-45

18 MHz

SYNC

ED

---,

rI

I
I

I

+9

~lt~

A

~21~--

BUS

1S

~------~~======~----~====~--~~2

B WAIT

I

MICRO-

I

I
I

A O- _ ' " ADDRESS

I

I
B ROY ROY IN

__ _

~------~~~~~~~~~~------~~1

r----- ----,

PROCESSOR

U33
(U31)

I

I

~----~~~~Y~I----__------------------~READY
I
I

I

BI - DIRECTIONAL

BUS DRIVERS

I fl---..I....--I"\.

DATA

" , _ -__J

BUS

::r:

~--.. RESET

I
RESET

I

I

H
I

INT HOLD

I

......

o

U1
W
~

I
I
_ _ _ _ _ -.1

FROM

MR

I/O INT

s~:{ ; ': ; S "'~;: ';I :'; S'; ;AB ;" LE~

I
1.-.______-1-__________________- . - N

+-_______

I.-._ _ _

~

A
Y

HW

I--~~-.

G

lOR

lOW
_ _- - '

BUS EN

I SYSTEM

INT A

CONTROLLER G

L.~~!!!.8 _ _ _ _

I

-.1

+l2V
7704060

Figure 1-12.

Microprocessor Block Diagram

HI-I053A
array generates a.memory write or I/O write output synchronous
with the microprocessor WR (write) signal, or a memory read or I/O
read signal synchronous with the microprocessor DBIN (data bus
input) signal.

The gating array also controls the direction of

the bus drivers and generates an INTA (interrupt acknowledge)
signal when the microprocessor status word indicates an interrupt.
The interrrupt occurs in response to an external interrupt input
to the microprocessor.
1.3.8.3

A bus disable input to the microprocessor causes it to

go into the hold condition.

The microprocessor then generates a

HLDA (hold acknowledge) signal which is also used as a bus enable/
disable control.
devices.

The address and data bus drivers are 3-state

During the hold status, they are in the high impedance

state, permitting other devices to control the address and data
buses.

This feature, called direct memory access, is used during

tv refresh to permit direct transfer from refresh memory to the'
line buffer.
1.3. 9

Honi tor" (F igure B-4)

1.3.9.1

Low-Voltage Regulator.

The low-voltage regulator proces-

ses input ac power, converts it to a highly regulated dc voltage,
and supplies this voltage to all circuitry in the monitor.

The

regulator output voltage also determines the raster width for the
crt display.

Primary ac power (98 vac, 60 Hz, nominal) is received

from a secondary winding in the power transformer.

This voltage

is rectified by U3, filtered by C26A, and subsequently regulated
by the circuitry described below.
1.3.9.1.1

The regulator circuit is a closed loop feedback ampli-

fier, with high open loop gain for stability, and current amplification to provide adequate power to drive the remaining monitor
electronics.

A reference voltage is established by resistor R55

and zener diode VR3 at the high impedance port of operational
amplifier U2.

Because of the large open loop gain of U2, this

same voltage is reflected, by means of a virtual ground between
pins 2 and 3 of U2, at pin 3 of U2.

1-47

Feedback network R56, R57,

HI-I053A
and R58 then determine the magnitude of the regulated voltage
(amplifier gain) at the emitter of output transistor Q7.
1.3.9.1.2

Amplifier U2 and transistor Q9 provide open loop

voltage gain and voltage translation of the input reference voltage.

Transistors Q7 and Q8, connected as a Darlington amplifier,

provide current and power gain for uplivery to the monitor circuitry.
Resistors R51 and R52 provide bias for amplifier U2.
and R50 provide bias for the transistors.
emitter degeneration for the Darlington.

Resistors R49

Resistor R54 provides
Capacitor C27 provides

frequency compensation for amplifier stability and capacitor C26B
provides dynamic load filtering for the regulated output.
1.3.9.1.3

Dynamic operation of this amplifier is as follows.

An

instantaneous increase of the output voltage increases the voltage
at the arm of potentiometer R57.

The difference between this volt-

age and the reference voltage at pin 2 of U2 is amplified by difference amplifier U2 whose output then increases base drive and
collector current in transistor Q9.

This increase in current then

tends to starve, or turn-off, transistors Q8 and Q9.

Therefore,

the emitter current of Q7 decreases which, in turn, tends to
decrease the output· voltage such that stable circuit operation for
varying circuit loads is maintained.
1.3.9.1.4

Potentiometer R57 permits adjustment of the output

voltage and is used to establish correct raster width on the crt
display.

Fuse F2 provides protection in case of fault or failure

conditions in the monitor electronics.
1.3.9.2

Video Amplifier.

The video signal originates in the

logic, is routed through an operator-controlled contrast potentiometer, and enters the monitor on pin 8 of the monitor input
connector PI with a ground return reference at pin 5 of Pl.

The

video signal is terminated on the pc board by R75 and is then processed by transistors QlO and Qll connected as a cascode amplifier
with a nominal dc gain of 25, controlled by resistors R65, R66, and
R67.

Capacitor C30 provides high frequency peaking of the video

signal to permit a uniform brightness presentation on the crt of
both single dots and horizontal bars within an alphanumeric

1-48

HI-I053A
character.

The output video signal at the collector of transistor

QIO is coupled to the crt cathode through inductor L5 and through
resistor R69 which is located in the crt socket assembly.

L5

provides further peaking of the signal; R69 provides crt flashover
protection for the video amplifier circuitry.

A spark gap at the

socket provides further flashover protection.

Resistor R64 and

capacitor C29 provide decoupling of the B+ line.

Resistors

R63 and R74, capacitor C2B, and Zener diode VR5 provide base drive
and a low source impedance for the upper transistor of the cascode.
1.3.9.3

Horizontal Deflection.

The horizontal deflection ampli-

fier provides deflection yoke drive to move the crt electron beam
across the screen.

The deflection is a closed loop system

consisting of an AFC circuit and drive output stage.

The system

is closed because the output (flyback pulse) is fed back to the
AFC circuit for phase comparison with the incoming synchronization
pulses.
1.3.9.3.1

The AFC circuit portion of the horizontal deflection

comprises Q13, U2 and their associated components.
the logic board is TTL, positive-going.

The sync from

Q13 is used to invert the

sync since U2 requires a TTL negative-going input at pin 3.

Q13

also serves as a buffer between the deflection and the logic board.
U2 contains a regulator, phase comparator, voltage-controlled
oscillator, and an output pulse width controller.

The internal

regulator voltage is measured at pin 6 of U2 (B.6 V nominal) and
provides oscillator stability during environmental change, power
supply drift, and component tolerance drift.

The voltage-contrplled

oscillator is set nominally by adjustment of R5.

R5, in conjunc-

tion with R6, R7, RB and Cl, determines the oscillator's freerunning frequency (no sync.input).

The filter, composed of R9,

R12, C2 and C3, filters the voltage that controls the oscillator.
The ammlitude of the control voltage is proportional to the difference in phase of the feedback signal (flyback in this case) and
the'input sync.

The flyback pulse is integrated by R13 and C6 to

produce a sweep at the horizontal rate.

,

C5 ac-couples the sweep

into the phase detector for comparison against the incoming sync.

1-49

HI-l053A
The output pulse width at pin 1 of U2 is determined by the ratio
of RIO and Rll.

The pulse is routed to Ql to drive the primary

of pulse transformer T2.

The secondary of T2 supplies base drive

for Q2, the horizontal output transistor.
1.3.9.3.2

The output stage is a flyback deflection system.

The

description starts at the time the sweep has reached the right
portion of the crt and is ready for flyback initiation.

Q2 is

conducting at this time and the yoke current is sweeping negatively.

The sync pulse (already described), coupled by T2, turns Q2

off.

The yoke, which no longer has a discharge path, now dumps

it's energy into flyback capacitor Cll.

The yoke and Cll act as

a tank circuit and ring at the frequency determined by their
values.

The ring causes the voltage at Q2 collector to increase

to approximately 600 V.

When the voltage returns to ground

potential and attempts to ring negatively, diode CRI turn on to
clamp the negative excursions.

At this point, the yoke current

has again returned to its positive extreme (left side of crt)
and the sweep starts again.

Approximately half way through the

sweep, Q2 turns on again, CRI turns off and the sweep continues
until the sync pulse initiates flyback again.
compensate for losses in the yoke.

~12

Coil L2 is used to

and R18 damp any spurious

C3l is the "8" correction capacitor and·

ringing within L2.

compensates for geometrical non-linearities caused by crt faceplace curvature.

Power for the system is supplied by the 70 V

regulator via the flybac* transformer, T3.

Adjustment of the

regulator voltage controls the width of the horizontal sweep.
Increasing the voltage increases the size of the sweep.
1.3.9.4

CRT Electrode Drives.

All crt electrode potentials

(except video) are derived from the horizontal deflection flyback
voltage, as follows.
a.

CRT Anode Voltage.

The horizontal pulse at the

collector of Q2 is applied to the primary of the flyback
former (pin 5 of T3).

trans~

This pulse is stepped up, through transfor-

mer action, to a magnitude of 15,000 volts, is then rectified by
CR4 and applied to the crt anode.
1-50

HI-l053A
b.

DC Focus Voltage.

The horizontal pulse at the collec-

tor of Q2 is rectified by diode CR2 and applied to one end of
focus potentiometer R22.

The horizontal pulse is also ac-coupled

and rectified by Cl4 and CR3 and applied to the other end of R22.
The wiper voltage of R22 is then applied, through R2l, to the crt
focus electrode.

This circuitry establishes the dc focus voltage

for the crt and can be varied from approximately -400 volts to
+500 volts to achieve optimum focus.
c.

Dynamic Focus.

A tapped voltage from the primary of

T3 is ac-coupled and resonated by action of L3 and Cl7.

A

sinusoidal voltage at the horizontal frequency is developed at
Cl7 and the voltage phase and amplitude is controlled by varying
L3.

This ac voltage is summed with the dc focus voltage to

produce a composite focus potential. to optimize focus over the
entire crt display.
d.

G2 Voltage.

This voltage is developed in a fashion

similar to the dc focus voltage.

The horizontal flyback pulse is

rectified by CR3, filtered by R23, Cl6, and R24, and applied to
the second crt grid.
e.

Gl Voltage.

The voltage applied to this first (control)

crt grid is used to control raster background brightness.

Voltage

is applied to both ends of brightness potentiometer R26 and is
limited in value by resistors R25 and R27, such that the total Gl
voltage range is from approximately -90 volts to +30 volts.

A

vertical blanking signal is also coupled into this electrode.
The vertical blanking signal is discussed in paragraph 1.3.9.5.
f.

Filaments.

A primary tap on flyback transformer, T3,

is used to drive the crt filament electrodes.

The voltage

developed is 6.3 vac.
g.

Spark Gaps.

Each electrode discussed in paragraphs b.

through f. above has a series swamping resistor separating it from
its drive circuit.

Each of these electrodes also has a spark

gap returned to ground.

The purpose of these spark gaps and

1-51

HI-I053A
resistors is to divert and limit occassional crt flashover energy,
thereby preventing monitor failures.
1.3.9.5

Vertical Deflection.

The vertical deflection supplies

the yoke with the necessary current to drive the crt electron
beam from the top to the bottom of the display.

Q14 and Q3 pro-

vide the vertical integrator with the proper sync signal and also
with the capability to free-run (no sync applied).

Q14 provides

buffering between the deflection circuit and the logic board and
also translates the sync level to a value that is usable by Q3.
Q3 is programmable unijunction transistor.

Q3 remains in a non-

conductive state until the voltage on its gate (connected to R32)
is exceeded by the voltage on its anode (connected to R37).

When

the anode voltage exceeds the gate voltage, Q3 turns on and
conduct from anode to cathode.

The voltage at the anode is con-

trolled by the charging of C19 and C32 through R37 and R36
a positive temperature coefficient resistor).
form is the sweep generating waveform.

(R36 is

This charging wave-

As the sweep reaches a

predetermined value, adjustable by R36 (vertical height control)
the sync pulse at the gate causes the gate voltage to drop below
the anode voltage.

Q3 turns on, thereby discharging C19 and C32

to the level determined by CR6 and CR7.

Q3 runs off and the

cycle begins again.
1.3.9.5.1

In the case where sync is absent, the level at Q3 gate

is determined by R3l and R33.

The anode sweep waveform charges

to this value, Q3 turns on as defined previously, and the system
oscillates independently.
1.3.9.5.2

The sweep waveform generated by R36, R37, C19 and C32

is applied to the base of Q4.

Darlington transistor Q4 drives the

vertical output transistor, Q5, and the linearity correction network, consisting of R38, C20, R39 and R40.

The linearity

correction network feeds a portion of the output waveform determined by R39, linearity control, back to the junction of C19 and
C32.

Resistor elements in this network are high stability film

resistors.

This signal causes the generated sweep to assume the

1-52

HI-I053A
characteristic "S" shape and corrects for,non-linearity caused
by crt screen geometry.
1.3.9.5.3

The output transistor Q5 provides the necessary current

amplification to drive the yoke.
yoke and ensures that

t~e

C22 couples the sweep to the

sweep is centered around ground potential.

L4 provides the necessary current required to drive the output
system.

R44 and VDR-l damp the flyback voltage created when the

vertical sweep retraces.VR2, R43, and RB3 supply the low voltage/
current section with the dc power required for their operation.
1.3.9.5.4

The blanking signal is derived by using the vertical

flyback at Q5 collector to turn Q6 on.
amplitude of the blanking pulse.

R47 and R4B determine the

C24 ac-couples the blanking

pulses to the control grid where they are summed with a dc
potential supplied by R25, R26, R27 and RBI.

R26 is used to

adjust the level of the voltage at the blanking grid and thereby
adjusts display brightness.
1.3.ro

Five-Volt Regulator (Figure B-3)

1.3.10.1

The II-volt ac input from the power transformer is

rectified by CR3 to supply the regulator circuits.

Power for

regulator integrated circuit AI, filtered by Cl and Rl, is applied
to pins 7 and B.

The

regu~ator

integrated circuit generates a

7.15 volt reference voltage at pin 4.

A fraction of this voltage,

'divided by RIO and Rll, is applied to pin 3 as the reference level
(approx 4.2 vdc) for voltage comparison.

A fraction of the output

voltage at terminal 4, divided by RB and R9, is applied to VI pin 2.
The voltages at pins 2 and 3 are compared to determine the output
at pin 6.

If the voltage at pin 2 increases, the output at pin 6

is reduced, reducing the conduction through series transistors Ql
and Q4 and reducing the output voltage.

If the voltage at pin 2

decreases, the output at pin 6 increases, raising the output
voltage.

..

R6 and C3 provide frequency compensation for the regula-

tor integrated circuit.
1.3.10.2

If the output current from the regulator increases, the

base voltage at Ql and Q4 rises in order to maintain the output

1-53

HI-I053A
voltage.

A fraction of the base voltages developed across R3 is

applied to Al pin 10 via R4 and Rl9.

Potentiometer R19 is ad-

justed so that the current limit feature of Al is triggered when
the output current exceeds normal by 20 percent.

The output at

Al pin 6 is then lowered, reducing the output current of the
regulator.
1.3.10.3

Q2 and Q3 provide overvoltage protection.

~f

the regu-

lator output voltage rises, the full increase appears at the
emitter of Q2.
of Q2.

Only a fraction of the increase appears at the base

Potentiometer R18 is adjusted so that Q2 conducts suffi-

ciently to trigger the gate of Q3 if the output voltage reaches
+6 vdc. Q3 then conducts, 'cutting off the output.
1.3.11
1.3.11.1

Printer Buffer (Figure 1-13)
The printer buffer includes a 2048 word random access

memory and a microprocessor to buffer and control transfer of
data to a printer in parallel or serial format.

The microprocessor

has an I/O expander which is used to increase the number of input/
output ports available to the processor.

Under control of the P2

and PROG (program) signals, parallel words can be transferred via
the remaining four ports of the expander.

The microprocessor in

the printer buffer handles addressing differently than the one in
the terminal logic.

The least significant eight bits are output

on the data bus, along with an ALE (address latch enable), and are
held in the address register.

The most significant bits are then

output with a read or write command.

The processor program is

stored in ROM on the microprocessor chip.
1.3.11.2

Data is transferred between the terminal and printer

buffer under control of the two microprocessors as follows:

Data

to the ,printer buffer is put on the terminal data bus

along

D[0~6]

with a write command which the address decoder translates to a
write print data command.

This command gates the data into the

input buffer and sets a flip-flop, which generates a Tl input to
the microprocessor, denoting data present in the input buffer.
The printer buffer microprocessor, in turn, generates the appropriate commands to transfer the word on the printer buffer data
1-54

HI-1053A

B RESET

Y1

r---------,

ADDRESS
DECODER
U15 U20

I
I

6 MHz

I

I
I

r - -~*-t

--. S

I
L.,.. .. - - - . T - - 1
J

_I_OW
_ _~
..

TO/FROM TERMINAL

M.A[O] ---.

ADDRESS
DECODER
U21

I

I

I

I

I

I
I
I

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I

I
I

I

I

1

I

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-12V
GND

M
I
C
R

r-

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Q~----------------------~T1

U7

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,:(

Cl

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,:(

8

,:(

Cl

8

Z
H
p::

M.A[l] ......

+12V

rO~

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,:(

8

~

+sv

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1

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Q
U7
R

___________________~_T~

8

Z
H
p::

Po.

~

Cl

H

,:(

~

~

p::

OUTPUT

1

INPUT

DB7

DECODER
U4
U3

BANK 1
WRITE ENABLE

P

All

R

RD

o

WR

C

'J

E

U11"'U14
A

It

VI'--MA-0-"'-MA--7- - - j

ADDRESS
REG ISTER
U17

II

D [0"'6]

DATA BUS DBlO"'7]

t

~

INPUT
..------,;/ BUFF ER
D7"
U23

J

L..--_o"\.1

i

y

S
~----j ALE

0

R

PROGRAM
r,1Er.,0 RY

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,

f~__US~
_0
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I

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DECODER 14-----jPSEN.'"i P2~ PROG
l
U8 U3 ~
~Jl--A~-=---=--=--=~_---"-_~....:s?
AS, A9, MAIO
J

I1_ _U18
U19 ~~
J
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>
.7

L ___

I
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Sl

, - - --I
I

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EXPANDER
U9

WRITE PCNTL

SPARE
) PARALLEL
I/O

1
1

L

J

(SPARE)

d

}

READ PSTAT

I.-.-

D[0"'3]

~

PRINTER
STROBE

Os..J
U7
ACK

u16

I
-.-l

PRINTER
- -[0-"'-6-]--t-.\\ CONTROL
DB
'------"'11./
REG
U22

_.-I',

'r---v'
110

L

,_
~

Iv~,------------------)

I

TO/FROM PRINTER

t--,.

.II

I

SERIAL

~~~______~O_UT__~~

)

LINES
I INDICATE
1 DEVICES
I NOT USED
I FOR
I MODEL 1520

PD{0"'6]
~------~~----------~y

LI~__~~~~~I~~Jt~___~,

It

I DOTTED

PI

S

MAS, MA9

RAf1

~~

~

o

A10

BANK 0

.

~

Po.

~

8

r~

PRINTER
STATUS
REG
'--__U=2=5__-->r--

PRINTER
DOWN

~~---BU-S-Y-

~ 0----U1

SERIAL
BUSY

ON LINE SW
OUT OF PAPER

SPARE
ON LINE LT....

~~~~~---------------------------------------~
7710057

Figure 1-13. Printer Buffer,
Block Diagram
1-55

HI-l05.3A

bus, and reset the flip-flop.

The terminal may also read printer

status from the printer status register or transfer a control
word to the printer control register via the terminal data bus.
1.3.11.3

Parallel output to the printer is directly from the

microprocessor at TTL levels, accompanied by a printer strobe.
The strobe sets a flip-flop which inhibits further transmission
until an ACK (acknowledge)

from the printer resets the flip-flop.

Timing is shown in figure 1-14.

A busy signal from the printer

will also inhibit transmission, and if it persists for 6 seconds
the microprocessor does not send a "buffer empty" bit via the
printer status register.

Parallel operation is selected by

switch 81-1,2,3 (a dip switch on the circuit board).

The rate

of transmission is determined by the availability of data in the
buffer and the rate at which it is acknowledged by the printer.
1.3.11.4

8erial output to the printer is transmitted via a TTL

to EIA level buffer at a rate of 110, 300 or 1200 baud, selected
by 81-3 and 81-1,2.
microprocessor.

Timing is accomplished by a timer in the

Transmission is inhibited if the serial busy

signal from the printer is present.
1.3.11.5

The following capabilities of the printer buffer are not

used in the model 1520:
A seven bit parallel input output port is available at the
I/O expander.
An external program memory for the microprocessor.
An output buffer for transferring data to the terminal data
bus.

1-56

HI-1053A

x_---t::\---____>C

D_
ATA _

I

I
I

I
I
I

=t .~

*100 ---,
J1S
I

--------~'--

:~~~~:r

~~ -J

I

I

Jf-

!f~--------------------------

10

~

~

:

I

I

I
I

:

I

~ ~lS

printer_B_U_Sy_ _......:_ _ _ _

psU_____
I

I

I

--~----,L
Acknowledge
.

. *1£ Acknowledge is grounded, data access is initiated
from drop in Printer Busy.

Figure 1-14. Parallel Printer Interface Timing

1-57/(1-58 blank)

HI-1053A
SECTION 2
SITE MAINTENANCE
2.1

INTRODUCTION

2.1.1

Scope

This Section provides troubleshooting, adjustment and replacement
procedures for servicing terminals at the user's site.

Recommended

spares are listed in Appendix A.
2.1.2

Test Equipment

A standard Hazeltine serviceman's kit containing the following items
is

reco~~ended

for site maintenance.

Hand tools
Alignment tools
Volt-Ohmmeter, digital
Spare parts allocation (refer to Appendix A)
2.2
2.2.1

CHECKOUT
General

When the presence of a fault in the terminal is obvious (dead terminal, bad display, etc) refer to the troubleshooting procedure,
paragraph 2.4.

Otherwise confirm that the fault is in the terminal,

and not in the line interface or computer.

If more than one ter-

minal is available at the site, this may be accomplished by interchanging terminals.

If the fault involves only full duplex opera-

tion, or received data only, and only one terminal is available,
proceed as follows:
NOTE
For the model 1500 when operating at rates
of 2400 baud of higher, some fill characters from the computer may be required
'to permit proper response to remote commands
without loss of data {refer to the Reference

2-1

HI-I053A
Manual). Failures of this nature cannot be
duplicated with a single terminal; only
substitution will confirm or eliminate
the terminal as the cause of the failure.
This may be done by substituting a spare
keyboard/logic assembly (after checking
voltages in accordance with paragraph
2.4.2) if a second terminal is not available.
a.

Connect the current loop adapter for half duplex opera-

as shown in figure 2-l(b) or connect a jumper adapter as shown in figure 2-I(c). This routes the terminal output data back to the terminal
as input data.
b.

Set the power swi tch on and check that the red POvvER

au

indicator is lit.
c.

Set the HALF DUP/FULL switch to FULL.

d.

Set the EIA/CUR LOOP switches to CUR LOOP, if a current loop

adapter is used, or to EIA if a jumper adapter is used.
e.

Perform those portions of the checkout procedure, paragraph

2.2.2, necessary to confirm or eliminate the terminal as the cause of
the faul t.
2.2.2

Checkout Procedure

Perform the following checkout procedure to verify proper operation
of the terminal following repair.

Portions of the procedure may be

used as necessary to confirm the existence of a fault.

If the in-

stallation does not provide for full duplex operation, omit that part
of the procedure.

If the installation uses only full duplex, omit

the half duplex part.
2.2.2.1

Setup.

Several options are available depending on the type

of installation and the nature of the problem.

As a checkout of the

terminal, it is preferable that the test be performed with the terminal installed in the normal manner for the site.

In order to check

input/output operation fully in half duplex operation, it will be
necessary to store the data generated by the terminal and then
retransmit it to the terminal.

In order to isolate the terminal

2-2

HI-I053A

,-----,
COMPUTER

I

I VSI
I Y
I
I

1

I
I

VS2

l--+

OUT

0

3

4

o

I

[±J

CURRENT
LOOP
ADAPTER

I

L _____ lI

IN

21

lOUT

}IN

18

B

2

TERMINAL

2!>

19

(0) FOUR-WIRE
(FULL DUPLEX)

EIA/CL
CONNECTOR

a) Four-Wire (Full Duplex)
COM PUTER

r:-----;1
VOLTAGE SOURCE
I~

I

o
o
Cill}

I

- +

3

I

I
I
I
I
I
IL _____ JI

.1

I

2

21

}OUT
CURRENT
LOOP

TERMINAL

25

ADAPTER
IN

18
19

B

EIA/CL
CONNECTOR

(b) TWO -WIRE
(HALF DUPLEX)

b) Two-Wire (Half Duplex)

C~
Figure 2-1.

__\...J~3~~4~~5
\"'J
2__

__

~6~_____~2,O__)

\~_-----,l
c) Jumper Adapter

OB25P CONNECTOR
EIA FEMALE HOUSING
WITH MALE PINS.

Current Loop Interface and Full Duplex Jumper Adapter

from the interface and/or to minimize interference with system
operation during troubleshooting, the following setups may be used.
a.

Full Duplex.

Connect the current loop adapter as shown

in b of figure 2-1, and select current loop operation, or connect a
jumper adapter (c of figure 2-1) to the EIA/CL connector, and select
EIA operation.
b.

Half Duplex.

connections.

The terminal operates with no external data

This is satisfactory for checking keyboard operation,

response, and display, but cannot verify proper transmitted data or
proper response to received data.

The terminal may also be connected

back-to-back with another terminal if an adapter, as shown in figure 4-3, is available.

Use the second terminal to verify that pro'"

per data is transmitted, and to generate inputs to the terminal
under test.

2-3

HI-I053A
2.2.2.2

Operational Check.

The following operational checkout pro-

cedures are to be used either to verify a fault or to check out a
terminal after repair.

It is not necessary to fully exercise

function in each instance.

every

The extent of the test is left to the

technician's judgment depending on the nature of the complaint, the
type of repair action taken, and the modes of operation used at the
site.

Keystrokes involving use of the shift or control keys are

preceded by a superscript c, s, or both.

Thus, CS O indicates that

the 0 key is to be struck while holding both the CTRL and SHIFT keys
down.
a.

Preliminary
1.

Set up the terminal in accordance with paragraph

2.

Set the power switch to on and check that the red

2.2.2.1.

POWER ON indicator is lit.

Check that the screen is clear with the

cursor at the home position within 1 minute.
3.

Verify that all switch selections conform with the

norm for the installation (refer to table 1-2).
4.

Adjust CONTRAST control to obtain suitable display.
NOTE

For 1510/1520 models, substitute ESC
for s~ if that option is selected.
b.

Half Duplex
1.

Set the HALF DUP/FULL switch to HALF DUP.

2.

Type the following sequence as a quick check of

terminal operation (use the alphanumeric cluster keys for some numbers, and the numeric cluster for some numbers):
1
c

a

S

tV

space

S

2
s"

v

space

tV

cQ c

space

6 (release ALL CAPS)

space

s

C
'V

Y

4

S

s·

w
b

3

H

p

tV

S

'V

(set ALL CAPS)

HOME

2-4

sBACK SPACE

7

BACK SPACE

HI-1053A
The display should appear as in figure 2-2(a). Underlined areas
should be in high intensity. The cursor and the character "7"
should interchange three times per second.
Change the STD VIDEO/REV switch setting and check
that the video is reversed.
3.

CORNER OF DISPLAY--.....~I

\il

-l[Z)

H
34

2

SA6bp
H
-.-

(a)

I

- 7111

H
2

34

SA6bp
H

(b)

7704102

Figure 2-2.

Displays for Checkout Procedure
2-5

HI-IOS3
4.

Type

c

CLEAR.

Check that the characters 7 and Hare

cleared from the top line and the cursor does not move.
NOTE
If the preceding data is recorded
and played back to the terminal,
the display should appear as shown
in figure 2-2(b).
5.

Type s~ c s .

Check that the top row is deleted and

all others move up one row.

s

Cursor should be at the home position.

6.

Type

7.

Type sCLEAR.

LINE FEED.

The display should not change.

Check that the intensified spaces and

"H" are cleared to foreground spaces.

The cursor should be at the

home position.
8.

Type s~ C z Q W E R T Y BACK SPACE.

The characters

"q w e r t y" should appear on the top row with the cursor superimposed on the "y".

9.

Type

All other characters should drop one row.

s

~

c

x.

The "y" and all characters after i t

should be cleared to spaces.
10.

The cursor should not move.

Hold the RETURN key (if the AUTO LF mode is sel-

ected) or the LINE FEED key (if the CR mode is selected) down to
move the cursor to the bottom row of the screen.
11.

Press the RETURN or LINE FEED key one more time,

followed by any character.

The character typed should appear on

the bottom row and the top row should be cleared.
12.

Press the CLEAR key.

The screen should be cleared

to foreground spaces and the cursor should be at the home position.
13.

Type s~ CS O

a

s

s~ C u

d

d.

Only the intensi-

fied characters "a" and "s" should appear on the screen (the keyboard should be locked out).
14.

Press the BREAK key.

The display should not

change and the keyboard should remain locked out.
15.

Press the RESET key.

The screen should be blanked

briefly and then the original display should reappear.
2-6

The key-

HI-l053A
board should be unlocked and typed characters should appear at
low intensity.
16.
c.

16.

Type

c

g.

The audible alarm should sound.

Full Duplex
1.

Set the HALF DUP/FULL switch to FULL.
NOTE
The results of the following procedures
depend upon all characters generated by
the terminal being echoed back to the
input.

This may be accomplished with

the setup shown in figure 2-l(b) or
with a jumper connector as shown in
figure 2-l(c).

If the terminal is

checked out on line in a system which
does not always echo back the generated
characters, different responses will be
obtained.
2.

Perform steps 2 and 3 of the half duplex proce-

dure given in paragraph b above.
3.

Type TAB twice.

The cursor should move over the

first "H" and then 'over the first intensified space.

4.

Type

s ~ c L BACK SPACE

c CLEAR.

Check

that the

"7" and "H" are deleted from the top line and the cursor is in the
position formerly occupied by the"7".
5.

Perform steps 5 through 8 of the half duplex pro-

cedure given in paragraph b above.

6.

Type

be cleared to spaces.
7.

c

x.

The "y" and all characters after it should

The cursor should not move.

Perform steps 10 through 16 of the half duplex pro-

cedure given in paragraph b above.

2-7

HI-I053A

d.

Format Mode (1510/1520 only)
1.

Make the following switch settings:
WRAPAROUND:

YES

ESC/~:

Norm for installation

FORMAT:

Off

EOM A&B:

Norm for installation

2.

Type a half row of characters.

3.

Type s~s# and check that the FORMAT LED comes on.

4.

Depress and hold any character.

Check that

characters appear in foreground intensity and the display wraps
around at the right hand margine.
5.

Press CLEAR.

The display should not change.
NOTE

If a jumper adapter, as in figure 2-1 c, is
being used, disconnect it.
6.

Press SEND.

A transmit symbol (I) should appear

at the present cursor position and the cursor should advance to
the start of the next line.
7.

Press t.

B.

Press cCLEAR.

9.

Press

The cursor should move up one line.
The line the cursor is on should

be cleared.

s

CLEAR.

All foreground characters should

be cleared.
10. Press HOME and CLEAR.

The cursor should home and

the screen should be cleared.
11. Press RESET.
e.

s

The FORMAT LED should go out.

Printer Buffer (1520 only)
1.

Put the printer on line (by switch or by typing

2.

Enter some random characters on the top line.

~/).

Check that the characters are printed.

2-B

HI-I053A

s s

#.

3.

Type

4.

Enter some random characters followed by RETURN.

5.

Hold any character key down to fill the screen.

~

The FORMAT LED should come on.

The cursor should stop at the end of the bottom row and the alarm
should sound.
6.

Move the cursor to the top line and to the right

of the carriage return entered in step 4.

Enter a few additional

characters.
7.

Move the cursor to the last character position

on the bottom row and press spRINT.
8.
A print symbol

The alarm should sound.

Move the cursor left one character and type spRINT.

(II)

should appear at the cursor position, the cur-

sor should move to the start of the bottom row, and all data preceding

II

should be printed except the characters to the right

of the carriage return on the top line.
the FORMAT

LED~stops

Characters typed after

blinking should appear on screen even if

printing is not completed.
NOTE
If the printer automatically
does a carriage return/line
feed at the end of an 80 character row, the resulting printout should be double spaced
from the second row down for
step 8, but single spaced for
step 9.
9.

Type SEND.

All foreground data should be printed

except the bottom row and data to the right of the carriage return
on the top row.

2-9

HI-I053 A
2.3

I

ACCESS

WARNING

I

Dangerous' voltages (15 K vdc and 115 vac) are
present in the terminal, and high voltage may
be retained in the monitor circuits after
power is removed.

Exercise caution when work-

ing within the unit.
2.3.1

To gain access to the internal components, reach under the

unit and release two captive screws at the front corners, and two
captive screws at the sides approximately in line with the crt face.
Then release two captive screws at the upper part of the back of
the unit.

The cover, including the' monitor may be lifted off the

base assembly.

The wiring allows sufficient slack to lay the cover

upside down alongside the base, facilitating access to the monitor
components.

The keyboard/logic assembly is secured only by
one screw near the input/output connectors.
Do not turn the base assembly over once the
screws securing the cover are released.
2.3.2

The power transformer, printer buffer and 5-volt regulator are

loca·ted under the keyboard/logic assembly.

Disconnect all connectors

to logic board, remove the screw securing the logic board to the base,
and life the board up at the rear to gain access to these units.
2.4
2.4.1

TROUBLESHOOTING
Scope

This section provides troubleshooting data to aid in isolating a
fault to one of seven removable subassemblies. The relationship of
the sub-assemblies

1S

shown in figure 2-3.

Since all keyboard,

logic, and input/output functions are performed by the keyboard/logic
assembly, no further isolation is required in these areas.

Use the

checkout procedures of paragraph 2.2.2.as necessary to confirm or
eliminate the terminal as the cause of a fault.
2-10

Table 2-1 defines

HI-1053A

,-----I

P4 J4

A _

~--------------------------------------------------------------------------------------_,r_~_1r

1

pa
Ja

J

PUSH
[ TO RESET

-.J

~\.------l'-----11If---i---....-----i

CIRCUIT

JI02 PI02

3

lBRFAKER

U
-I

-12V
REGULATOR

-SV

Tl

2

- BRl +

~

o
~~ REG~~roR I I

~-

- - R19

A

lOVER Vi
PROTECT

RIa

5 VDC
REG. ASSY

OVERVOLTAGE
THRESHOLD

I

V DRIVE

r

I~~
J, "'-I- t-

I

I

I

I

7fJ

A
TOR--J~V>-~--.----------~---1

J3 ,....P3

VERTICAL

r----L-o_S_C_ILLA
__

VERTICAL DEFLECTION

.......

TWISTED
PAIRS

PIOl JIOl
VIDEO

+SV

~, /I
-t- /I

rt-

+70VDC

@

I

PI Jl

REGUIATOR

1---_---'

1
I

R39
LINEARITY

SIZE

I

MICROPROCESSOR

3
+12V

PROGRAM
ROM

r--~HDRIvE
f-+- I - - t - - , - - - i
f-+-

I

POWER
ON

'---r
, - -til

DISPIAY
RAM

~

I

CiJ

lM al
I~ ~

t-------f

II[\r

REFRESH
ADDR. CTR

l-'-

rv-

o
I

CONTRAST

-L

.... 1-

I

I
I

I
I

HORIZONTAL
OSCILLATOR

~

L..--.-..--,-_-.I
I

~

V

RS

I

t-

JS PS S.--------~
lSKV
~___~ h~
T3
~~~~-~~-H--~

c:l> HORIZ
HOLD

BRIGHTNESS
NETWORK

HORIZONTAL DEFLECTION

r--I~~>-;-----~~-----~

VIDEO

I

I ~- ~
+70V,
--..

FLY BACK

~
4

'---7-'-"-'F-I-IAM--I EN'l'

SUPPLY

R22

STATIC~
FOCUS

P7
r-

:

J7

I

®

o

KEYBOARD

TEST POINT

ENCODER

1

OVERVOLTAGE
THRESHOLD

+SV ADJ

ADJ
(WIDTH)

Y

1

FOLDBACK
ADJ

SYNC

R36

~

-----

+70V

(1'1 VERT

(J}) Ra
0/ +SV ADJ

FO~CK VLJ

TV

1

o~

F2

RS7:
SERIAL
INPUT/
OUTPUT

L-----.J

~~2

II

REGUIATOR

I

*YL..-_REG_+_~..,.~_V_TO_R---,fiP

~

r1

-MONIToR!
ASSEMBLY I

KEYBOARD/LOG IC GNO
CIRCUIT BOARD l

l2V +~12V

-1

H

r

FOCUS
NETWORK

R26
BRIGHTNESS

~ .... rJ4 ~4

r-L3

DYNAMIC
FOCUS

P6

1------~

'--

L..---j

I

0

YOKE

t",/

~

CRT

KEYBOARD

+j5V_",<
!o-

\

TEST POINT LOCATIONS
Test
Point

--

A'\.H

1

2
3

"
5

Logic Bd
Logic Bd
4DTD155202
4DTD155246- ( )
Refer t:o Table 2-2
U48-24
Edge Conn - 4
U48-22
Edge Conn - 29
U48-23
Edge Conn - 3
Edge Conn - 32
Edge Conn - 47, 48, ':9
Edge Conn - 49
Edge Conn - 20, 21

j
(

1

I
--

PRINTER BUFFER

I

(81520 ONLY)

I

MONITOR CIRCUIT BOARD
l
PRINTER CONN

c:b

I

J

_I
7704069

Figure 2-3.

Servicing Diagram
2-11

HI-1053A
Table 2-1.

Terminal Operation
Functions
Part One ~ Model 1500

HALF DUPLEX
KEY
STROKE (S)

CHAR(S)
SENT

DO FUNCTION
WHEN KEYED

DO FUNCTION
WHEN RECEIVED

FULL DUPLEX
CHAR(S)
DO FUNCTION
SENT
WHEN RECEIVED

Direct Cursor
Address I

'" c Q

'DCI
"

No

Yes

'\,

Read Cursor
Address

'" c E

'"ENQ

No

Yes 2

'ENQ
"

Yes 2

Horne Cursor

HOME

No

Yes

If preceded
by '"

'DC2
"

Yes

Up Cursor

sLINE
FEED

No

Yes

If preceded
by

'FF
"

Yes

Down Cursor

'" c K

'"VT

No

Yes

'"VT

Yes

Left Cursor

BACK
SPACE

No

Yes

Yes

BS

Yes

Right Cursor

sBACK
SPACE

No

Yes

Yes

OLE

Yes

Foreground Tab

TAB

HT

Yes

Yes

HT

Yes

Clear Screen

CLEAR

No

Yes

If preceded
by '"

'FS
"

Yes

Set Background

'" c Y

'"EM

Yes

Yes

'EM
"

Yes

Set Foreground

'"

cS

'"US

Yes

Yes

'US
"

Audible Alarm

.c G

BEL

Yes

Yes

BEL

Yes

Keyboard Lock

'"

'"NAK

Yes

Yes

'NAK
"

Yes

Keyboard Unlock

'" c F

Yes

'"ACK

Yes

FUNCTION

C

O

u

Yes

DCI

'"

'"

ACK.

...
Yes

Delete Line

'" C s

'"DC3

Yes

Yes

'DC3
"

Yes

Insert Line

'" C z

'"SUB

Yes

Yes

'SUB
"

Yes

Clear to end-'
of-line

cCLEAR

No

Yes

If preceded
by '"

'"S1

Yes

Clear to endof-screen

cSCLEAR

No

Yes

If preceded
by '"

'CAN
"

Yes

Clear Foreground

sCLEAR

No

Yes

If preceded
by '"

'"GS

Yes

'"

Yes

If preceded
by '"

ETB

Yes

Clear to end-of
screen (background)

'" C

w

ETB

2-12

HI-l053A
Table 2-1. Terminal Operation
Functions
Part Two - Models 1510 and 1520

Key
Stroke(s)

Function
Direct Cursor
Address
Read Cursor
Address
Home Cursor

Char(s)
Sent
tV

Half Duplex
Do When
Keyed
No

Do When
Received

Full I
Duplex
Char (s)
Sent

Yes

tV

DCI

HOME

Format
When
Keyed
Store

DCl

tV

Store
tV ENQ
Do

tV

No

Yes

tV

ENO
No

Yes

Yes

tV

No

Yes

If prec.
by tV

tV

Yes

tV

2

ENO

DCl

DC2
Up Cursor

or
sLINE
FEED
t

Down Cursor
Left Cursor

No
a)
b)

BACK
SPACE

Right Cursor a)
b)

Foreground Tab
Clear Screen
Clear-to-endof':" line
Clear-to-endof-screen
Clear foreground

SBACK
SPACE
TAB
CLEAR

cSCLEAR

Clear-to-end-of
screen (bkgnd)
Set Background

No
BS

Yes
Yes

If prec.
by tV
Yes
Yes

No
DLE

Yes
Yes

Yes
Yes

DLE
DLE

HT
No

Yes
Yes

HT

No

Yes

Yes
If Prec.
by tV
If prec.
by tV
If prec.
by tV
If prec.
by tV
If prec.
by tV
Yes

No

Yes

No

Yes

tV

Yes

ETB
tV

Yes

tV

US
BEL

Audible alarm
Keyboard Lock

tV

NAK
Keyboard unlock

Yes
Yes
Yes

Yes
Yes
Yes
Yes

tV

ACK
Delete line

tV

Back tab
Send status

tV

STAB·
tV

hyphen

Print (1520 only)
Function

FUNCTION
A/N Char

SUB
DC4
Status
Word
No

Do
Store
BS
Do
Store
DLE

BS
BS

*Do
*Do if
home
*Do

tV

FS
tV

SI
*Do

tV

CAN

."GS

*Do

tV

*Store
tV ETB
Store
tV EM
Store
tV US

ETB
tV

tV

US
BEL
tV

NAK

i

Do
Store
tV NAK

tV

ACK
Yes

Yes

tV

*Do

DC3

DC3
Insert line

Do

VT

EM

EM
Set foreground

Do

FF

Yes
Yes
Yes

Yes
Yes
Yes

tV

SUB
DC4

*Do
*Do
Store
tV

Yes

ESC
A/N char
EOM

2-13

-

No

*00

ESC
A/N Char
EOM

*Send ESC
A/N Char
EOM

HI-1053A

Notes for Tables 2-1 Part One
1.

Function must be followed by X and Y coordinates.
Cursor X and Y coordinates will be senti followed by CR.
3. The following ASCII codes will be sent when the indicated keyes) are struck. Nothing
will be displayed when sent, and no action will be taken if received.
Code: NUL
SOH
STX
ETX
EOT
SO
RS
DC4
SYN
ESC
DEL
Key:
cp
cA
cB
Cc
cD
cN
cSN sTAB C v
ESC
DEL
If the AUTO LF/CR switch is set to AUTO LF, depressing the RETURN switch causes the CR
4.
and LF codes to be sent, in either half or full duplex, and both operations are executed. Both operations will be performed if a CR is received. The LINE FEED key
will cause a LF to be sent, but nothing will be displayed and no operation will be
performed when sent or .if received •.
If CR is selected, a CR will be sent when the RETURN key is depressed. The cursor will
move to the beginning of the present line when the character is sent or received. A LF
will be sent the LINE FEED key is depressed. The cursor will move down one row when the
character is sent or received.
5. All characters/functions will be repeated at a rate of 15 per second if the keyes) is depressed longer than 3/4 second (typamatic operation) except: HOME, all CLEAR functions,
and the BREAK key.
6. The BREAK key causes a 250 ms interruption in output. Received data and the auxiliary output are not affected.
Cursor
7. Cursor Up/Down will not be performed if the cursor is on the top/bottom row.
right/left commands will cause cursor wraparound if the cursor is at the edge of the
screen.
2.

Notes for Table 2·-1 Part Two
1.
2.

3.
4.

All functions are performed when command is received (or echoed) in full duplex.
All functions are performed when command is received in format mode (including clear
screen regardless of cursor position). Functions noted with an * will not be
performed if received or keyed during a transmission.
The following keystrokes will cause an alarm. in half or full duplex: SEND, c
,
SEND
cS SEND , LOCAL
Substitute ESC for ~ in all cases if that option is selected by switch.

2-14

HI-I053A
the normal terminal outputs, displays, and response to inputs.
moval and replacement procedures
2.4.2

~re

Re-

given in paragraph 2.6.

Procedure

Tables 2-2 and 2-3 provide information to assist in isolating faults
to replaceable subassemblies.

Check the voltage inputs before re-

placing the keyboard/logic assembly or the monitor electronics to
ensure that a fault in the power circuits is not the cause of a problem.

No-load voltages are given to enable isolation of an undervolt-

age condition between the source and a overload condition in the load.
Disconnect the load from the source to check.

Input resistances are

given to aid in troubleshooting when power cannot safely be applied.
Check with power off and the input disconnected. When a fault is isolated to the monitor, and it is not. obvious weather the fault is in
the electronics chassis or the crt yoke assembly, further isolation
may be done by sUbstitution.
2.5
2.5.1

ADJUSTMENTS
Five-Volt Regulator.

Adjust the 5-volt regulator (refer to figure 2-3) as follows:
NOTE
Do not change the setting of R18 or R19 at
the site.

Additional test equipment is re-

quired to make these adjustments.
a.
r~gulator

with power off, disconnect the lead from terminal 4 of the
assembly.

b.

Connect a voltmeter between terminal 4 and chassis ground.

c.

Turn power on.

d.

Adjust +5 V potentiometer R8 for a 5.20 vdc indication.

e.

Turn power off and reconnect the lead to terminal 4.

2-15

HI-I053A
Table 2-2.

'1'P

Voltage and Resistance Data

No Load Voltage

Normal

Test Point

Impedance

n max.

A

Tl terminals 1 & 2

115 ±12 vac

Same

4

Bl

5 V rgltr CR3-l/E2

10 vac

11 vac

5000 n if CR3-l+; 3000 n
initially, >lOK after
capacitor charges if E2+

B2

CR3-3/E2

10 vac

11 vac

3000 n initially, >lOK
after capacitor charges
if CR3-3+; 5000 n if E2+

5.2
±0.25 vdc

5.2 vdc at
5 V rgltr
E4 & E5
15 vac at
JI02-l, -6

6 n (Pl02-2 +)
14 11 (Pl02-4 +)

15 vac at
Jl02-3, -6
80 vac at
J8-2, -3
gray, white

5000
5000
>15K
>15K

+5 V Test connector
pins 49 & 32
C

l

BRI (IV), Test
connector
pin 32

14 vac

C2
D

14 vac

U3

75 vac

5000 n (Pl02-l +)
5000 n (PI02-6 +)

n (Pl02-3 +)
n (P102-6 +)
(P8-2 +)
(P8-3 +)

PRINTER BUFFER BOARD
E

J2-l8/J2-73

-12 vdc

F

J2-l6/J2-73

+12 vdc

G

J2-l9/J2-73

+5.2 ±0.2S
vdc

H

J2-73

GND

NOTE
Impedance values will vary depending on the voltages used by the meter.
They are provided primarily as an aid in isolating catastrophic failures.

Table 2-3.
TROUBLE

Troubleshooting Chart
ISOLATION PROCEDURE

Circuit Breaker Tips

with no power connected, check input impedance at test
points B through D (figure 2-3 and Table 2-3). If no
fault is found, replace TI.

Dead Terminal

Check voltages at test points A through D and +5 vdc
(figure 2-3 and table 2-3).

No Display

1. Check FI on monitor circuit board.
2. Check voltage at test point D (figure 2-3· and
table 2-3).
3. Type cG. The alarm should sound for 1/3 second.
If missing or excessively long or short, keyboard/
logic assembly is faulty.
4. Adjust brightness control R26.
If no raster
appears, monitor is faulty.
5. If another terminal is available, connect cover
and monitor assembly to faulty terminal (J10I and P8
of monitor to P10I and J8 of keyboard/logic assembly)
to isolate fault between monitor and keyboard/logic
assembly.

Distorted Display

Align monitor in accordance with paragraph 2.5.2.

2-16

HI-1053A
f.

Turn power on and check for 5.2 ±O.25 volts across

capacitor e68.

2.5.2

Monitor Adjustments

Adjust the monitor as follows:
a.

Preliminary

Turn power on.
2. Set the STD VIDEO/REV switch to STD VIDEO, and the
HALF DUP/FULL switch to HALF DUP.
1.

3. Adjust BRIGHT control R26 until the raster is just
extinguished.
(All adjustments are located along the back edge of
the monitor circuit board.) This adjustment should be made within 1
minute of turn on.
4. Type several full rows of characters spaced from
top to bottom of the screen.
S. Adjust the CONTRAST control for suitable contrast.
b.

Vertical Adjustments

Adjust VERT SIZE control R36 for desired height.
2. Adjust VERT LIN control R39 for best vertical lineReadjust R36 as required.
1.

arity.

c.

Horizontal Adjustments

1. Adjust BRIGHT control R26 until the edge of the
raster can be seen.
2. Adjust HORIZ HOLD control R5 clockwise until sync
is lost.
3. Adjust R5 slowly counterclockwise until sync is
just restored. Note the position of the adjustment.
4. Adjust R5 counterclockwise until sync is lost again.
5. Adjust RS clockwise until sync is just restored.
6. Set R5 midway between the points noted in steps 3
and S.
7. Measure the gap between the 80th character on the
top line and the right edge of the raster. If the gap is less than
1/16 inch, proceed as follows:
2-17

(a)

Adjust HORIZ HOLD control slowly clockwise and

watch the 80th character.for a 1/8 inch jump to the left.
(b)

If the horizontal hold cannot be adjusted so

the gap is 1/16 inch or greater without loosing sync, replace the
monitor electronics.
8.

Readjust BRIGHT control R26 until the raster is

just extinguished.
9.

Turn power off and on.

nize within 2 seconds.

The monitor should synchro-

Readjust R26 if necessary.
NOTE

R57 also adjusts the B+ supply for
monitor electronics.

If any subse-

quent change is made, repeat other
adjustments.
d.

Centering.

If the display is not properly centered, it

may be repositioned by rotating the ring magnets behind the deflection yoke.
NOTE
(1)

The ring magnets should not be used

to offset the raster from the nominal center position because it will degrade the
resolution of the display.
(2)

The HORIZ HOLD control should not be

used to adjust video centering within the
raster.

The control is to be left in the

center of the pull-in points in order to
maintain horizontal sync.
e.

Focus Adjustment
1.

Adjust dynamic focus control L3 (located near

FOCUS potentiometer R22) for 150 volts rms at the junction of CIS
and L3.
2.

Adjust static FOCUS potentiometer for best over-

all focus at normal contrast level.
2-18

HI-I053A

2.6

REMOVAL AND REPLACEMENT

2.6.1

Monitor Electronics Chassis
WARNING

I

Hazardous voltage may be present in the CRT
anode circuit. The anode lead must be discharged before working on the CRT or monitor
circuit board.
To remove the electronics chassis, refer to figure 2-5 and
proceed as follows:
2.6.1.1

a. Disconnect the anode lead from the side of the crt (pull
out). Use a screwdriver to ground the anode lead to the chassis.
b. Disconnect PI from the back edge of the circuit board,
and P3 from the front edge of the board.
c. Separate flying lead connectors pa and Ja.
d. Disconnect P6 from the crt base socket.
e. Turn the cover and monitor upside down.
f. Remove and retain two screws and lock washers from each
side of the chassis.

There are connections to heat sink mounted
components between the sides of the cover
and the chassis. Use caution when removing
the chassis.
g.

Carefully lift the chassis straight up.

To replace an electronics chassis, slide it carefully into
the cover and secure the fasteners and connections shown in figure
2-4, being sure that the ground lug is secured at one corner of the
chassis.
2.6.1.2

2-19

HI-I053A
2.6.2

CRT/Yoke Assembly and Video Filter.

2.6.2.1

To remove the crt/yoke assembly, refer to figure 2-5 and

proceed as follows:
a.
Disconnect the anode connector from the side of the crt
(pullout). Use a screwdriver to ground the anode lead to the chassis.
b.

Disconnect P6 from the crt base connector.

c.

Disconnect P3 from the inside edge of the electronics

board.

WARNING

I

Use caution when handling the cathode-ray
tube to avoid risk of implosion.
ternal phosphor coating is toxic.

The inIf the

tube breaks and skin or eyes are exposed to
phosphor, rinse with cold water and consult
a physician.
d.
Remove and retain two screws and washers securing each
of two brackets to the cover.
e.

Carefully remove the crt, along with the video filter,

yoke and brackets, from the cover.
f.

Remove the ground spring from the brackets.

g.
Remove· and retain the four screws and nuts securing the
CRT to the brackets.
2.6.2.2

To replace a crt yoke assembly, proceed as follows:

a.
Secure the two brackets to the crt using the four screws
and nuts retained in step g above.
b.

Attach the ground spring to the two holes in the brackets.

c.

Place the video filter on the crt face and carefully

align the assembly with the mounting holes in the cover.
d.

Secure the fasteners and connections shown in figure 2-5,

being sure the ground lug is secured to one bracket.
2.7
2.7.1

CLEANING VIDEO FILTER
The video filter may be cleaned with a soft cloth and house-

hold glass cleaner.

2-20

HI-1053A
P3 AT INSIDE
EDGE OF PCB

ANODE LEAD

Pl

P6

TWO

SCREWS AND

J8

LOCK WASHERS EACH

SIDE

Figure 2-4.

Monitor Electronics Chassis

TWO SCREWS AND
WASHERS EACH SIDE

TOP

P6

D
7704071

Figu~e

2-5.

CRT/Yoke Assembly

2-21/(2-22 blank)

7704068

HI-1053A
SECTION 3
REPAIR SHOP MAINTENANCE
3.1
3.1.1

INTRODUCTION
Scope

This section provides checkout, troubleshooting and alignment
procedures for the monitor electronics and for the 5-volt regulator assembly.

Refer to Appendix A for recommended spare parts,

and to.Appendix B for component location and schematic diagrams.
3.1.2

Tools and Test Equipment

The following tools and test equipment are required for shop
maintenance:
Oscilloscope, Tektronix 465 or equivalent
Hot mock-up test bed
Ammeter, 0 to 15 A, dc
Variable Transformer, 0 to 140 vac, 5 A, 60 Hz
Regulator Test Jig
Standard Serviceman's Kit including:
- Hand Tools
- Alignment Tools
- Volt-Ohmmeter, digital
- Spare Parts Allocation (Refer to Appendix A)
The hot mock-up test bed is a model 1500 terminal

wi~h

parent size/centering overlay as shown in figure 3-1.

a transThe regu-

lator test jig is shown in figure 3-3.
3.2
3.2.1

CHECKOUT
Monitor Electronics Chassis

The following checkout procedure may be used to determine the
condition of an electronics chassis returned for repair, or to
verify proper operation following repair and adjustment.

The

procedures include adjustments required to make the unit ready
for use.
3-1

HI-1053A
0.09 IN,
(2.29 MM)
TYP

0.12 IN
(3.05 MM)
TYP

.-1 _ _ _---.1

T

T

5.82 IN
(148 MM)

-1

t4-----------t---- (219
8.57 I N .
MM)

CENTERING

~GUIDES

(4)

SIZE'
DELIMITERS

ILLUSTRATION NOT TO SCALE

Figure 3-1.

Size/Centering Overlay

3.2.1.1 Setup. Connect the chassis to the hot mock-up test bed
and perform the following preliminary steps:
1. Set WIDTH potentiometer R57 fully clockwise.
2. Set L3 (dynamic focus coil) for maximum inductance
(slug completely within coil form).
3. Set the FULL DUP/HALF switch to HALF, and the NORM
VID/REV switch to NORM VID.
4. Set the power switch to on.
NOTE: The first nine steps of the checkout
procedure should be performed within 3 minutes
of turn on.
3.2.1.2 Checkout Procedure. Perform the entire procedure to
check out a chassis after repair. For troubleshooting, omit
those alignment procedures unrelated to the fault.
1. Enter four full rows of H characters on the first,
ninth, seventeenth and twenty fourth (bottom) rows.

3-2

HI-1053A
2.

Adjust BRIGHTNESS control R26 until both the video

and raster are visible.
3.

Adjust HORIZ HOLD control R5 slowly clockwise until

sync is lost.
4•

Adjust HORIZ HOLD control R5 slowly counterclockwise

until sync is just restored. Note the control position.
5 . Adjust HORIZ HOLD control R5 counterclockwise until
sync is lost.
6.

Adjust HORIZ HOLD control R5 slowly clockwise until

sync is just restored.
7•

Set HORIZ HOLD control R5 midway between the posi-

tions of steps 6 and 4.
S.

Measure the gap between the right edge of the SOth

character on the top row and the edge of the raster.
must be equal to or greater than 1/16 inch.

The gap

If not, adjust HORIZ

HOLD control R5 slowly clockwise and watch the SOth character for
a l/S inch jump to left.
9.
disappears.

Recheck the gap width.

Adjust BRIGHTNESS control R26 until the raster just
Do not readjust the BRIGHTNESS control for the remainder

of the checkout procedure.
10.

Adjust WIDTH control R57 so the width of the display

falls within the size delimiters on the overlay.

The outside edge

of the His may touch the outer delimiters but must not fall outside
either the right or left hand outer delimiter.

The outer edge of

the HiS may just touch the inside delimiters but must not fall
entirely inside the inner delimiters.
NOTE:

Adjust the yolk ring magnets if required

to center the display within the centering guides
on the overlay.

Do not adjust HORIZ HOLD control

to improve display centering.
11.

Using a lOX probe, connect the ac-coupled oscillo-

scope input to the junction of R21, C1S and L3.

The waveform

should correspond to T of figure 3-2, and the peak-to-peak amplitude must be between 160 and 240 volts.

3-3

HI-I053A

- OV
- OV

A

0.2V/DIV
I O].lS/DIV

- OV

SOY/DIY
10].lS/DIV

B

c

IV/DIV
10].lS/DIV

- OV

- OV
- OV

o

100V/DIV
10].lS/DIV

2V/DIV
2ms/DIV

E

F

2V/DIV
2ms/DIV

- OV
- OV

G

100V/DIV
2ms/DIV

~

OV

lOY/DIY
2ms/DIV

H

2V/DIV
2ms/DIV

- OV
- OV

J

20V/DIV
10].lS/DIV

- OV

O.SV/DIV
10].ls/DIV

f<

L

0.2V/DIV
1 O].ls/DIV
7704104

Figure 3-2.

Monitor Waveforms
3-4

(Sheet 1 of 2)

HI-1053A

- OV

- OV
- OV

IV/DIV

M

2V/DIV

N

10~S/DIV

o

200~s/DIV

2V/DIV
200~S/DIV

- OV
- OV

- OV

p

0.5V/DIV

5V/DIV

Q

200~s/DIV

10~S/DIV

IV/DIV

R

10~s/DIV

- OV

- APPROX
65V

s

lOY/DIY

50V/DIV

T

200~S/DIV

20~s/DIV

u

lOY/DIY
10~s/DIV

- OV

v

lOY/DIY
10~S/DIV

7704105

Figure 3-2.

Monitor Waveforms (Sheet 2 of 2)
3-5

HI-I053A
12.

Adjust FOCUS control R22 for best overall focus.

13.

Adjust VERT SIZE control R36 and VERT LIN control R39

to optimize the vertical size of the display,

The outer edges of

the top and bottom rows of H's may touch, but must not extend beyond the outer size delimiters.

The outer edges of the H's may

touch, but may not lie entirely inside the inner size delimiters.
14.

Repeat steps 10 through 13 as required until all

size requirements are met simultaneously.
15.

Check that the display characters are of uniform

size over,the display area.

This check is made by comparing the

size of characters in the left column with those in the right
column, and those on the top row with those on the bottom row.
The width and height of adjacent characters must not differ by
an amount equal to one line spacing.

The width and height of

characters at opposite edges of the display must not differ by
an amount equal to two line spaces.
16.

Check that the voltage between R55 (lead nearest

edge of board) and the ground lug is between +65 and +75 vdc.
17.

Enter a # character in the eighth row from the

top and sixteen character positions from the left side of the
display.
18.

Adjust the CONTRAST control for normal contrast.

19.

Adjust FOCUS control R22 to optimize focus of the

# character.
20.

Check that a dark area is clearly discernible be-

tween the dots making up the two vertical strokes of the character.
3.2.2
3.2.2.1

Five-Volt Regulator
Setup.
1.

Set up the regulator for testing as follows:

Connect the regulator to the test jig (figure 3-3)

as shown in figure 3-4.
2.

3.

Set the test jig switches as follows:
LOAD SELECT switch

- NO LOAD

TEST MODE switch

- TEST

POWER switch

- OFF

Set the variable transformers for a nominal 120 vac.

HI-I053A

I tHI1SSIS

'sl

I REfit<

~fT
I
'-LIAJE~

_.-0--.

tlJRD

__

2,22

71

~---o---...

10

_ - ( \ - - -...

II

J--~--4-----411

12

GND
\

fi~

)

TP7
Awe

~--o

®®TP8
)0

r

~

Off 8fT

TEST

/y) 0 DE

J4

K/

~c

IItJPUT '(!AlSPL.IITElJ Pfll))

Dvm
+

SCOPE

+ -

f(

oc

ODTPDT
",,w LIIJD
-.1.tJ il//I)

r'I-JltRh1lM
t::::J...,rAL£ fIJI}
'IFtJ'j(.lMO
LtJlIO JElEt'T

flHJG :/118

FfJST()N
CLIPS

J5

NOTES:
/" KEEP DC WI/(INC liS SHORT itS pass IBL e:
2. DC WIRIAIC TIE PtJIAJTS fiRE TO BE

tYlld

TEST.II 9 5?

;j&r-------~ 1l;~S7

J8

r:!P. TEST

rp9

oZ:JV IHAO • :9t/flJ.!'

FflSTtJN

1"0--------

Awr; #10

0

J2.

fie

PWR SUPPLY

9

RET

CLIPS

7

IJ)/RJAJG
DC I1/IRIA)C

O/~tI

ell

P{)lDER

KI

'ifLJO
1.1;70

At.

f(S

I

NO LOIID
3.1J1l L{)I}D
S2
AJtJRIfJ L{)I1D
~IJLL L(}/JO
/2tJ % LtJ/JO
LtJIJD SELECT

0

1J.4?.D.
75W

RI

/(4
~.53D.

.Za

75JV

MIJ)

R2
1.4Ct~

50tl/

3. SET RES/c5T()R VRLUES BY eOAlAJEeTING
fl)) 1IfT)/l}£TER 8ETHJEEAI TPS /lAiD TPt;,,?
fJPPL YIA/C 5. Z7S IItJLT.! nCRtJSJ J~ /lA!O
J5, RNIJ THEN fJDJUJTIAlG E/lCH RESISTtJR
TO YIELD THE F()LL{}/iJ/A/C tuRREAJTS:
RES/STaR
CLlRREAlT

f(2
. £3
R4

RS

o B

3R
3.~R

/tJfJ
10.5/1

2~ POWER
77IJ7tJl4-

Figure 3~3. Five-Volt Regulator
Test Jig (Sheet 1 of 2)

3-7

HI-1053A

r··----~~~----------r-----------------------~--------------._--------------------_r

ITEM

QTY

IDENT.

1

2

R5, R4

Slide-Wire Resistor
o to 1 ohm, 150W

Ohmite

l156A (150W)

2

2

R3, R2

Slide-Wire Resistor
o to 2 ohm, 50W

Allied

8801203 (0-2 ohm)

3

1

R1

Fixed Resistor
0.2 ohm, lOW

Dale

RS-lO 0.2 ohm, lOW

a

3

H. H. Smith

257-0

b

4

-Red

H. H. Smith

257-2

c
d

3

2

TP8,
10, 12
TP6, 7
9, 11
TP1, 4
TP2, 3

-White
-Green

H. H. smith
H. H. Smith

257-9
257-5

5

1

Sl

Rocker Switch, AC

6

1

S2

Non-Shorting Rotary
Switch, 2 Pole, 8
Position, 15 A at 5 V

Centra1ab

JV9033

7

1

Chassis

15" x 17" x 6" Chassis

Bud

ACl429

8

1

Line
Cord

Line Cord, 6 ft.

9

1

F1

Fuseho1der and 2 A Fuse

10

1

K1

Relay, DPDT, 10 A,
120 VAC Coil

11

1

XK1

Socket, Octal (for K1)

12

1

S3

13

1

T1

DESCRIPTION

4

MANUFACTURER

5 Way Binding Posts:
-Black

PART NUMBER

HKP/AGC2A
P &B

KRPllAG

Switch, 3PST, 10 A
at 120 VAC

Cutler-Hammer

7590K73C27

Transformer

Hazeltine

3DTD893042

C77021

Figure 3-3.

Five-Volt Regulator Test Jig (Sheet 2 of 2)
3-8

HI-l'053A

115 VAC
60 HZ

L.,

. -,

~

.

AC1

~r

I

I

CT1

•

AC2

:J

IN
OSCILLOSCOPE
GND

+

,.

•

CT2

.".

~

-

+

AC VOLT METER
VARIABLE h
TRANSFORMER

-

-

+

I

I

--

DIGITAL
VOLTMETER

VOLTMETER
0-15 VAC

+

~

-

+

TEST JIG
(FIG. 3-3)

AC

RET

+

~{~

:~3

5-VOLT
REGULATOR

•
-

+"""

AMMETER

AC

J

-

PWR
SUPPLY

SCOPE

DVM

LINE
CORD

~

DC
POWER
SUPPLY

-

~

NOTE

+

-

AMMETER

-

:t:

NOTE:
USE A MAXIMUM
OF 1 FT
#10 AWG WIRE
7704066

Figure 3-4.
4.

Test setup Diagram

Set overvoltage threshold potentiometer

Rla fully

clockwise and overcurrent potentiometer R19 fully counterclockwise.
3.2.2.2

Checkout Procedure.

Perform the entire procedure to

check out and align the unit after repair.

For troubleshooting,

omit those adjustments unrelated to the fault.
a.

Adjustment Range

1. Set the test jig POWER switch to ON and adjust the
variable transformer for an 11.0 ±0.5 vac indication across jacks
ACl/CTl and across AC2/CT2.
2.

Adjust 5V ADJ potentiometer R8 over its entire range

and note that the indication at the DVM jacks varies from 4.95 vdc
or less to 5.45 vdc or greater.
b.

Load Regulation
1.

Adjust variable transformer for 10.5 ±O.l vac across

ACl/CTl and across AC2/CT2.
2.

Adjust R8 for 5.20 ±0.25 ·vdc at the DVM jacks.
3-9

HI-I053A
3.

Set the LOAD SELECT switch to 3.0 A and note that

the dc voltage does not change by more than ±0.042 vdc.
4.

Set the LOAD SELECT switch to NO LOAD.

5.

Adjust variable transformer for 11.5 ±O.l vac

across ACl/CTl and across AC2/CT2.
6.

Adjust R8 for 5.20 ±0.25 vdc at the DVM jacks.

7.

Set the LOAD SELECT switch to 3.0 A.

Check that

the dc voltage does not change by more than ±0.042 vdc.
c.

Line Regulation
1.

Adjust R8 for 5.20 ±0.25 vdc at the DVM jacks.

2.

Adjust variable transformer to vary the voltage

across ACl/CTl from 10.50 vac to 11.50 vac and check that the
output voltage does not vary by more than 0.008 vdc.
d.

Ripple
1.

Adjust the varia?le transformer for 11.0 ±0.5 vac

across ACl/CTl and across AC2/CT2.
2.

Set the LOAD SELECT switch to 3.0 A.

3.

Adjust R8 for 5.20 ±0.2S vdc across the DVM jacks.

4.

Connect an oscilloscope across the SCOPE jacks, ac

coupled, with vertical sensitivity set for 5 mV/cm.
5.

Adjust variable transformer to vary the voltage at

ACl/CTl from 10.50 vac to 11.50 vac.

Check that ripple does not

exceed 5 mV peak-to-peak at any point.
e.

Overvoltage Threshold Adjustment
1.

Set the LOAD SELECT switch to NO LOAD and the TEST

MODE switch to OVP SET.
2.

Connect a dc power supply across the PWR SUPPLY

terminals and set it for a 6.0 vdc indication across the DVM
terminals.
3.

Turn overvoltage threshold potentiometer R18 slowly

counterclockwise until the dc voltage indication just
4.

drop~.

Set the dc power supply for 0 volt output and turn

its ac power switch off and then on (or disconnect and reconnect
power cord if power supply has no switch).
5.

Slowly increase the dc power supply output while

watching-the DVM.

Check that the voltage rises to 6.0 ±O.l vdc

and then drops.
3-10

HI-l053A
6.
f.

Repeat step 4.

Foldback Adjustment
1.

set the TEST MODE switch to TEST and the LOAD

SELECTOR switch to NORM LOAD.
2.

Adjust the variable transformer for 11.0 ±O.S vac

across ACl/CTl and across AC2/CT2.
3.

Connect an ammeter across the AMMETER jacks.

The

indication should be 3.6 ±O.l amps dc.
4.

Turn foldback adjust potentiometer R19 slowly clock-

wise until the current just drops to 3.4 ±O.l amps.
5.

Set R8 fully clockwise.

6.

Set the LOAD SELECT switch to NO LOAD and then back

to NORM LOAD.

7.
ammeter.

The overcurrent trip should no longer be activated.
Turn R8 slowly counterclockwise while watching the

The current should rise to 3.6 ±O.l amp dc, then drop

slightly.
8.
g.

Repeat steps 5 and 6.

Final Voltage Setting
1.

Adjust the variable transformer for 11.0 ±O.S vac

across ACl/CTl and across AC2/CT2.
2.

Set the LOAD SELECT switch to 3.0 A.

3.

Adjust R8 for a 5.20 vdc indication at the DVM

jacks.
h.

Hard Turn On
1.

Set the variable transformer for 11.5 vac across

2.

Set the POWER switch off and on several times • . Check

ACl/CTl.
that the voltage at the DVM jacks returns to 5.20 ±0.25 vdc each
time power is turned on.
3.

Set the LOAD SELECT switch to NO LOAD and repeat

step 2.
3.2.2.3

RTV application.

After all tests and adjustments are

completed, apply a drop of fast curing RTV on Rl8 and Rl9.

3-11

HI-I053A
3.3
3.3.1

TROUBLESHOOTING
Monitor Electronics Chassis (figure B-4)

The setup and procedure given in paragraph 3.2.1 may be used
when troubleshooting the monitor electronics chassis.

Table 3-2

is a troubleshooting chart, and tables 3-3 and 3-4 provide voltage
and waveform data for use in troubleshooting the monitor electronics.
A spare flyback transformer may be substituted without disassembly.
Connect P5 to J5 on the circuit board, flying lead connector J7
to P7, and connect the CRT anode lead.
3.3.2

Five Volt Regtilator (figure B-3)

The setup and procedure given in paragraph 3.2.2 may be used when
troubleshooting the regulator.

Table 3-1 lists normal voltage and

resistance values at key points.

The resistance values are for a

regulator with no input or output connections.

Voltages are given

for normal operating conditions.
3.4

REPAIR AND REPLACEMENT

I

WARNING

I

Hazardous voltage may remain present in the
CRT anode circuit after power is removed,
and must be discharged before working on the
CRT or monitor circuit board.

Disconnect the

anode lead from the side of the tube and use
a screwdriver to ground it to the chassis.
All components of the monitor, and of the 5-volt regulator are
directly accessible.

Refer to Appendix A for part numbers of

components not readily available.

When replacing the flyback

transformer, discard the shipping bracket and two nuts supplied.
Use the nuts removed from the transformer replaced.
title to the threads and torque to 5 ±l inch pounds.

Apply lockWhen re-

placing chassis-mounted transistors, apply a thin film of thermal
compound, Hazeltine part ntmber IDTD460003, to the mating chassis
and transistor surfaces.

3-12

HI-l053A
Table 3-1.

Voltage and Resistance Data for 5 Volt Regulator

TEST POINTS
(+),

NORMAL VALUE·

(-)

CR3-l, E2

5000 ohms

E2, CR3-l

3000 ohms initially,
>10 K after C6 charges

CR3-3, E2

5000 ·ohms

E2, CR3-3

3000 ohms initially,
>10 K after C6 charges

E4, E5

600 ohms

AI-I, E5

5.2 ±0.25 vdc

Al-2, Al-3

<0.1 vdc

Al-4, Al-5

6.8 to 7.5 vdc

Al-7 & 8, Al-5

7.9 vdc

Al-9, Al-5

7.9 vdc

Al-6, Al-IO

6.7 vdc

Table 3-2.

Monitor Troubleshooting Chart
POSSIBLE REMEDY

SYMPTOM
1.

No picture, no raster

Check F2, Q7, Q2, Q5. If
filaments are lit, Q2 is
operational.

2.

No video

Check QlO

3.

Picture tears

Check Q13, Ul

4.

Picture rolls

Check Q14, Q3

5.

Bright horizontal line

Check Q3, Q4, Q5

6.

Very bright pictureJ
contrast control has
no effect

Check QlO, Qll

3-13

HI-IOS3
Table 3-3.

Monitor Voltage and Waveform Data
(Transistors)
,

REF
DES

FUNCTION

BASE

Ql

Horiz drive

Waveform A

0 vdc

Waveform B

Q2

Horiz output

Waveform C

0 vdc

Waveform D

Q3

Vert
oscillator

(GATE)
Similar to
Waveform N

(CATHODE)
+1.2 vdc

(ANODE)
Waveform E

Q4

Vert drive

Waveform E

Waveform F

+12 vdc

Q5

Vert output

Waveform F

Same as Waveform F except
baseline is
0.7 V lower

Waveform G

Q6

Vert blanking

Similar to
Waveform G,
less amplitude

o vdc

Waveform H

Q7

Series
regulator

+72 vdc

+71 vdc

Waveform I

Q8

Pwr supply
driver

+73 vdc

+72 vdc

+100 vdc similar to Waveform I

Q9

Pwr supply
pre-driver

+16 vdc

+15 vdc

+73 vdc

QIO

Video output

+6.2 vdc

+5.6 vdc

Waveform J

Qll

Video

Input video

Waveform K

+5.6 vdc

Q13

Horiz buffer

Waveform L

0 vdc

Waveform M

Q14

Vert buffer

Waveform N

Waveform 0

Waveform P

..

EMITTER

COLLECTOR

'-

-,

Table 3-4. Monitor Voltage and Waveform Data
(Microcircuits and CRT)
REF
DES
Ul

U2

P6

PIN NUMBER

FUNCTION
Horiz
Oscillator

Pwr Supply
ampl

CRT
socket

1

Waveform A
5
+3.2 vdc
1

No conn
5
No conn
1
0 vdc
5
0 vdc

NOTE:

2
0 vdc
6
+8.4 vdc

3
Waveform M
7
Waveform R

4
Waveform

2
+6.2 vdc
6
+16 vdc

3
+6.2 vdc
7
+30 vdc

4
0 vdc
8
No conn

2
Waveform S
(variable de
level)
6
Same as Pin 2

3
5.20 vdc

4
Waveform T

7.
Waveform U

8
Waveform V

See figure 3-2 for waveforms

3-14

. ".

e

Q

+3.6 vdc

HI-1053A
SECTION 4
FACTORY MAINTENANCE
4 .. 1

INTRODUCTION

4.1.1

Scope

This section covers checkout and repair of the keyboard/logic assembly
and checkout of a complete terminal after repair.

Maintenance of the

5-volt regulator and the monitor are covered in Section 3.

Refer to

Appendix A for recommended spare parts, and to Appendix B for sche- .
matic diagrams.
4.1.2

Test Equipment

The following items of test equipment, or equivalent, are required for
factory maintenance:
Equipment

Manufacturer

Part Number

Oscilloscope

Tektronix

465

Frequency Counter

Hewlett Packard

5300A/5302A

Automatic Card Tester

Fairchild Technology Systems

Century 200

Hot Mock-up Test Bed

Hazeltine Corp.

Interface Fixture

Hazeltine Corp.

lE-22973

Master Video Display Terminal

Hazeltine Corp.

Modular One, modified for Type I
turn-on and U/L
case display

Printer

Hazeltine Corp.

Thermal Printer

The hot mock-up test bed is a model 1520 terminal with a transparent
size/centering overlay as shown in figure 3-1.
4.2
4.2.1

CHECKOUT
General

The following procedure may.be used to che,ck out the keyboard/logic
assembly after repair, or to check out a complete terminal.

Connect

-the keyboard/logic assembly to be tested in a hot mock-up test bed.

4-1

HI-IOS3A
4.2.2

setup and Preliminary Adjustments
1.

Make the following preliminary settings:
1510/1520 only
Position

switch

Position

Switch

BAUD RATE

9600

ESCAPE/'"

PARITY

EVEN

FORMAT

Off

HALF DUP/FULL

HALF DUP

EOM A & B

OFF

AUTO LF/CR

AUTO LF

WRAPAROUND

YES

U/L CASE/UP

U/L CASE

STD VID/REV

STD VID

EIA/CUR LOOP

EIA (2 switches)

I

WARNING

I

Dangerous voltages (15 K vdc and 115 vac)
are present i~ the terminal, and high voltage
may be retained in the monitor circuits after
power is removed. Exercise caution when workingwithin the unit.
2.

Connect the power plug to a 115 volt 60 Hz source and set

the power switch to on.
3.

Check that the POWER ON LED is' on.

4.

Check the voltage between the following points and El

(ground terminal adjacent to JI01) •
'·202
board

Voltage

U48-22

-29

-12.0 ±0.2 vdc

U48-23

-3

+12.0 ±0.2 vdc

U48-24

-4

-5.0 ±0.2 vdc

C68(+)
5.

'246 test
connector

-20

&

-21

+5.2 ±0.25 vdc

Type four full rows of characters evenly spaced from the

top to the bottom of the display.
6.

Adjust the monitor BRIGHT control R26 until the raster is

just visible.

7.

If necess,ary, touch up the monitor HORIZ HOLD, R5; VERT

SIZE, R36; and WIDTH, R57 to obtain proper size and synchronization.

4-2

HI-l053A
8. Verify that the display can be adjusted for proper size
and centering as described in paragraph 3.2~1.2.
9.

Adjust BRIGHT control R26 until the raster just disap-

pears.
10.
4.2.3

Set the power switch of off.

Interface tests
1.

Connect the test equipment as shown in figure 4-1.

2.

Set the AUTO LF/CR switch to CR.

3.

Engage the ALL CAPS switch.

4.

Set the interface fixture switches as follows:

5.

6.

Switch

Setting

202C/SYNC

202C

CB

Hi

CC

Hi

CF

Hi

Current Loop

Off

Set the master terminal controls as follows:
Switch

Setting

Baud Rate

9600

Parity

Even

Video

Normal

Stop Bits

1

Duplex

Full

LF/CR Auto

Disable

U/C Only

Disable

Power

On

The checkout procedure follows in tabular format.

Perform

the actions listed in the first two columns for the .unit under test
and the master terminal.

Check that the results listed in the third

and fourth columns of the table occur.

Use of the control and/or shift

keys is indicated by a superscript "C" or "S" preceding the character.
Thus, cSA requires striking the A keY'while holding· the CTRL and SHIFT
keys down.

Spaces between keystrokes in the table are included for

clarity; they have no significance and are not to be typed.
space is required
it is spelled out.
.
\

4-3

When a

HI-1053A

HISOO
TERMINAL

Jl

J2

J2

JI08
MASTER
TERMINAL

INTERFACE
FIXTURE

OSCILLOSCOPE

COUNTER

a~

INTERFACE TEST SETUP

Y ADAPTER (FIG. 4-3)
Jl

HISOO

>-----( SAME AS ABOVE

TERMINAL
J2

b~

AUXILIARY OUTPUT TEST SETUP
7704067

Figure 4-1.

Test Equipment setup
4-4

HI-I053A
ACTION
UNIT UNDER TEST (UUT)
MASTER TERMINAL

RESULT
UNIT UNDER TEST

MASTER TERMINAL

Power on

POWER ON LED on
Screen clear
Cursor home
Video synchronized
within 1 minute

Enter: 1 2 3 4 5 6 7

1 2 3 4 5 6 7 8 9 O-A\
appear on screen

1234567890-1\\

No change

QWERTYUIOP@[ appear on screen

Continuous stream of
A's, continued on
second line when end
of first line is
reached

Same as UUT

8 9 0 - ,.., \

HALF DUPjFULL to FULL
Enter: QWERTYUIOP@[HALF DUP/FULL switch to HALF
Depress and hold the A key
until more than 80 A characters are entered

Depress:

RETURN

i

I
Enter:

ASDFGHJKL::]

Enter:

LINE FEED

Set AUTO LF/CR to AUTO LF
Enter: ZXCVBNM,./
Enter:

RETURN

Enter additional RETURN's
until scrolling starts.
Using the numeric cluster,
enter: 0,.123456789

Cursor returns to
first character
position of present
line. Cursor blinks
(display alternates
between character
and cursor)
ASDFGHJKL: : ]
on screen

Same as UUT

Cursor moves down
one row but maintains character
position

Same as UUT

ZXCVBNM, . j
appear on screen

Same as UUT

Cursor moves to
start of next line

Cursor moves to start
of present line

0,.123456789
appear on bottom row
of screen

0,.123456789
appear on screen

I appear

Enter:

RETURN

Display moves up
one row. Cursor
moves to first
character position
of bottom row.
Bottom row is clear.

Enter:

LINE FEED

No cursor movement

Disengage ALL CAPS key.
AUTO LFjCR to CR
Enter: QWERTYUIOP
Enter: LINE FEED

appear on screen

Lower case
qwertyuiop
appear on screen
Scrolling occurst
cursor maintains
character position

4-5

Same as UUT
No change

HI-I053A

ACTION
UNIT UNDER TEST (UUT)
MASTER TERMIUAL
En ter :

RETURN

AUTO LF/CR to AUTO LF
Enter: ASDFGHJKLZXCVBNM

RESULT
UNIT UNDER TEST

MASTER TERMINAL

Cursor moves to
first character
position. No
scrolling occurs.

Cursor moves to start of
next row

Lower case
asdfghjklzxcvbnm
appear on screen

Same as UUT

With the left SHIFT key
depressed, enter:
! " # $ %&/ () 0 = 'V::

appear on screen

!"tS%&/()=:
appear on screen

With the right SHIF~ key
depressed, enter:
QWERTYUIOP' {
ASDFGHJKL+*}
ZXCVBNM<>?

QWERTYUIOP'{
ADFGHJKL+*}
ZXCVBNM<>?
appear on screen

QWERTYUIOP'{
ASDFGHJKL+*}
ZXCVBNM<>?
appear on screen

U/L CASE/UP to UP

!"#$%&/()=:

Press each alpha
and numeric key

Upper case alpha
characters, and
numbers appear
on screen

Depress SHIFT
and each alpha
and numeric key

Upper case alpha
characters and
symbols as marked
over numeric keys
on master are
displayed
Upper case characters appear on
screen

Press each alpha key

U/L CASE/UP to U/L CASE
Engage ALL CAPS key

Enter some random alpha
characters

Upper case characters
appear on screen

Depress and hold the
A key

A'S appear on
screen

Depress and hold the
S key without releasing the A key
Release the A key

No change

sequentially depress
and hold the A Sand
D keys.
Release the A key
Release. the S key
Release the D key
Depress:

Same as UUT

CLEAR

AUTO LF/CR to CR
Enter: 1 2 RETURN
LINE FEED 3

SiS appear on
screen

Same as OUT

A's appear on
screen
SiS appear on
screen
D's appear on
screen

Same as UUT

Screen clears,
cursor homes

No change

1 2

Same as UUT

3 appear on
screen

4-6

Same as UUT

HI-I053A
ACTION
MASTER TERMINAL
UNIT UNDER TEST (UUT)

nESULT
UNIT UNDER TEST

MASTER TERMINAL

Enter:

BACK SPACE

Cursor moves one
position to left. Display is unchanged

Same as UUT

Enter:

BACK SPACE

Cursor moves up one
line and over to last
column

Same as UUT

Enter:

HOME

Cursor homes

No action

Enter:

BACK SPACE

No action

Cursor moves one position to left

Enter:

sBACK SPACE

Cursor moves right
one position

No action

Enter:

LINE FEED

Cursor moves down
onp. line

No action

Enter:

SLINE FEED

Cursor moves up
one line

No action

Data is cleared from
cursor position thru
end of top row

No action

Data is cleared from
cursor position thru
end of screen

No action

Entire screen is
cleared

No action

No action

1 2

Enter random characters
on three full rows including the top and bottom rows. Position the
cursor near the middle
of the top row. Enter:
cCLEAR.

Enter:

Position the
cursor near
the middle of
the top row

cSCLEAR

Enter random characters
on the top and bottom
rows. Move cursor to
end of screen
Enter:

CLEAR

HALF DUP/FULL to FULL
Enter:

1 2 RETURN

LINE FEED

3 appear on screen

3

Enter:

BACK SPACE

Cursor moves left one
position. Display is
unchanged

Cursor moves left one
position. Display is
unchanged

Enter:

BACK SPACE

No action

Cursor moves to last
character position and
up one line

Enter:

HOME

No action

Cursor homes

Enter:

LINE FEED

No action

Cursor moves down one
line

Enter:

SLINE FEED

No action

Cursor moves up one
line

Enter:

s",
s

Enter:

Co
Cx
'"

No action

FB indicator comes on

No action

Fa indicator goes out

C77024

4-7

HI-I053A
ACTION
UNIT UNDER TEST (UUT)
MASTER TERMINAL

Enter:

sCLEAR

Enter:

CLEAR

Enter FMAT mode
and Half Duplex.
Enter some foreground data on
the screen.
Exit FMAT and
enter some background data

RESULT
U"NIT UNo"ER TEST

MASTER TERMINAL

No action

Foreground data is
cleared

No action

Entire screen is cleared

DISPLAY MEMORY TESTS
HALF DUP/FULL TO HALF DUP

Enter:

BAUD to 9600'

Fill screen
with u's

PARITY TO EVEN

HOME

Move cursor to
end of screen
and press: SEND
Enter:

Su and hold

Screen fills with U's
Screen fills with U's
except last character
position in bottom row
U appears, scrolling
occurs

Repeat the above procedure except set the
CHARACTER SELECT switch to *

Same as above except asterisks are displayed
instead of U's

RAM ADDRESS LINES AND REMOTE CURSOR ADDRESS CHECKS
Enter each of
the following
sequences:
CLR UNPRO RESET
~

~
~
~

~

Co

Co
Co
Co
Co
Co

c A cSPACE A

B is displayed

cD cSPACE C

C is displayed

c H cSPACE D

D is displayed

c p cSPACE E

E is displayed

SPACE cSPACE F

Co @ cSPACE G
~ Co ~ A H
~ Co c p C I
~ Co SPACE F J
~ Co cs o L K
~ Co / L L
~ Co 7 L M
'" Co ; L N
~ Co s= L 0
~ .c o s> L P
~ Co s? L 0
~ Co @ L R
~ Co Co S S
~ Co CS O V T

Co

A is displayed

c B cSPACE B

~

~

Note that none of the
previous characters
is affected as each
character is displayed.

0 W

F is displayed
G is displayed
H is displayed
I is displayed
J

is displayed

K is displayed
L is displayed
M is displayed
N is displayed

o

is displayed

P is displayed

o

is displayed

R is displayed
S is displayed
T is displayed
Cursor moves to line
24, column 80 screen
should look like
figure 4-2
C77025

4-8

1

AS

2

C

9

17

33

D

E

F

4 ------- - --- -- --- - - -

:I
---- i

I

65
G

H

I

I

7 -------- ------- -- ------- - --- - - -- - - --- - -

13

49

--1

32

48

56

60

K

L

K

H

I

N

\D

III

\D

OPQR

·
•
·

::c
H

•

.e.

I
I
I

I

\D

I

~

0
U1
tAl

I

t

>'

16

20

S

23

I-

24

t

I

7704072

Figure 4-2.

Test Display

HI-I053A
ACTION
UNIT UNDER TEST (UUT)

RESULT
MASTER TERMU!AL

UNIT UNDER TEST

REMOTE COMMANDS CHECK
c
~
No action
E

MASTER TERMINAL

-.-------------------------r------------~----r_--------------------,_--------------------------

Enter:

Enter random characters
to verify keyboard lock
and unlock. Do .not go
beyond end of first row

Enter:

~

Enter:

.~

Enter:

~

c

R
cK
c

L

Enter:

cp

Enter:

c

Enter:
Enter:

~

H

Cu

RESET
cF

~

Enter:

~

Cs

o w is displayed

Cursor homes
Cursor moves down
one row
Cursor moves up
one row
Cursor moves right
one character
Cursor moves left
one character
Keyboard is locked
out

No change when characters
are typed on UUT

Keyboard is unlocked

Characters appear when
typed on UUT

First row is deleted
Other rows move up
Bottom row is all
spaces

-

Enter:
A A A A appear on
first row. Display
moves down one row
Enter:

c H ~ cs~ Cursor moves left
one character.
First row changes
to A A A

Enter:

~ Co

CS O L
~

C

-

Bottom half of
screen is cleared

x

Enter:

~ cS L

Entire screen is
cleared

Enter:

cG

Alarm sounds

Enter:· ~ CS O A
A ~ cy

A A appear in high
intensity and B B
in low intensity

B B

Enter:

~ cs O

C C

Press RESET

STD VID/REV to REV

u

Enter:

n"

Enter:

D D

C

C C appear in high
inte!nsity
Keyboard is locked
out
Keyboard is unlocked
D D appear in low
intensity

-

Background is low
intensity. A A and
C C are black on
high intensity
background. B Band
D D are black on low
intensity background

-

4-10

HI-1053A

ACTION
UNIT UNDER TEST (UUT)
MASTER TERMINAL

RESULT
UNIT UNDER TEST

MASTER TERMINAL

No change

Screen is cleared

A A and C Care
cleared

No change

HALF DUP/FULL to FULL
En ter: CLEAR
Using FMAT mode,
enter some foreground data and
some background
data
HALF DUP/FULL to HALF DUP
Enter: sCLEAR
HOME cursor.
Using FMAT mode,
enter: A A in
high intensity,
B B in low intensity, C C in
high and D D in
low intensity
Enter: CLEAR s'" CS O A
A S'V c y B B s'" cS O' C C
S'V Cy D D
Enter:

HOME

Enter:

TAB

Enter:

TAB

A A and C C appear
in high intensity
and B Band D D
in low intensity
Enter:

HOME

Cursor homes

Cursor homes

Enter:

TAB

No action
Cursor moves to
first C

Cursor moves to first C

Cursor. moves to
first A'
No action

Enter: s'" sTAB
Enter: '" cS M

A A·and CC are
cleared

4-11

Cursor moves to first A

HI-lOS3A

4.2.4

Current Loop and Control Checks
1.

Set the CB switch on the interface fixture to Low.

2.

Type some random characters on the terminal under test and

check that there is no response at the master
3.

terminal~

On the interface fixture, set the CB switch to Hi, and the

Current Loop switch to 20 rnA.
4.

Set the EIA/CUR LOOP switches (2) on the unit under test-

to CUR LOOP.
S.
Set the HALF DUP/FULL switch to FULL.

6.

Type some random characters on the unit under test and check

that they appear on the screen.

AMP 206584

AUX
EIA

EIA MALE
HOUSING WITH
2 FEMALE PINS

r-

~

4

6
8-'

11

7

7

1

1

L-.....,.I

EIA FEMALE
HOUSING WITH
MALE-PINS

EIA

~

6

6

8

8

5

5

3

3
20
'--

23
L..-,.I

.......- - - - - 1

FT

..

----~

7704070

Figure 4-3.

Y Adapter Cable
4-12

HI-I053A
4.2.5

Parity Checks
1.

Set the Current Loop switch on the interface fixture to Off.

2.

Set the HALF DUP/FULL switch on the unit under test to HALF DUP.

3.

For each line below, set the parity switches on the unit

under test and the master terminal as indicated, make the keyboard
entrys listed, and check for the proper results:
Parity Setting
UUT

Master

Keyboard Entry
UUT

Result

Master

UUT

Master

EVEN

EVEN

T U

T U

EVEN

ODD

T U

P

EVEN

ODD

T U

? ?

ODD

T U

T ?

EVEN

T U

? U

EVEN

T U

T ?

T U

? U

T U

T U

0
0

1

I

E

P

E

I!

1

4.2.6

lODD

ODD

ODD

ODD

ODD

ODD

EVEN

.

T U

T U

T U

P

E

P

E

Break Check
1.

On the interface fixture, set the EIA Monitor switch to

BA, and connect an oscilloscope to the Output jack.
2.

Check that a 225 ±25 millisecond positive pulse appears

each time the BREAK key is pressed, and the voltage goes from -10 ±2
volts to +10 ±2 volts.
3.

Change the setting of the HALF DUP/FULL switch and repeat

step 2.
4.2.7

Baud Rate Checks
1.

Set up the counter for frequency measurement.

2.

Set each of the BAUD switches, one at a time, and check

for the proper frequency indication:

4-13

HI-I053A

4.2.8

BAUD Switch

Frequency (KHz)

19.2 K

302.592 to 311.808

9600

151.296 to 155.904

4800

75.648 to

77.952

2400

37.8'24 to

38.976

1800

28.368 to

29.239

1200

18.912 to

19.488

300

4.728 to

4.872

110

1.734 to

1.786

Stop Bits Check

1.
2.

Set the Scope Select switch on the interface fixture to, BA.
.
s
Press and hold ? and check for the 110 baud wavefor.m as

shown below.
3.

Set the BAUD switches for 300 baud.

4.

Press arid hold s? and check for the 300 baud waveform shown

below.

110

+12 V
Baud
-12 V

l

19
.

63 ms

~---------------------------------~

II)S

I

27

1I1S

~--------------

+12 V
23 ms

300 Baud
-12 V

4.2.9

Auxiliary Output Check
1.

Connect a

nyn

adapter cable (figure ·4-3) as shown in

figure 4-1(b).
2.

Set the unit under test HALF DUP/FULL switch to FULL,

and BAUD switches for 300 baud.

4-14

I

HI-l053A
3.

Set the interface fixture CC and CF switches to Hi.

4.

Set up the master terminal for Full Duplex operation and

300 baud.
5.

Check that the CA, SA, and CD lights on the interface fix-

ture are on.
6.

Enter random characters on the unit under test and check

that no characters appear on the master screen.

7.

Enter some random characters on the master keyboard and

check that they appear on the master screen and the CA, SA, and CD
lights go on.
8.

Set the unit under test BAUD switches for 1800.

9.

Set the interface fixture CC and CF switches to Low.

Check that the CA, SA, and CD lights are off.
10.

Set the unit under test BAUD switches for 300.

11.

Set the interface fixture CC and CF switches to Hi.

12.

Type some random characters on the unit 'under test and

check that they appear on the master screen.
13.

Type some random

character~

on the master keyboard and

check that they appear on the unit under test screen.
4.2.10

Format Mode and Printer Buffer Check (1510/1520 only).
1.

Connect a thermal printer to the terminal PRINTER connector.

Omit the printer and ignore steps concerning print functions if checking a 1510 terminal.
2.

Set Switches as follows:

switch

Position

Switch

Position

BAUD RATE

9600

ESCAPE/'"

ESCAPE

PARITY

EVEN

FORMAT

HALF DUP/FULL

HALF

EO~

AUTO LF/CR

AUTO LF

WRAPAROUND

Off
OFF
ON .
NO

U/L CASE/UP

U/L CASE

Printer Buffer

EIA/CUR LOOP

EIA (2 switches)

4-15

Sl-l, -2
-3 Up

&

HI-I053A
3.

Set up the master terminal and interface fixture in accord-

ance with paragraph 4.2.3 steps 4 and 5.

ACTION
UNIT UNDER TEST (UUT)
MASTER TERMINAL

RESULT
UUT OR PRINTER

Turn power on

POWER ON LED on
Screen clear
Cursor home

Press and hold any character key

Characters appear
until end of first
row. Cursor stops
at last position
of first row.
No change

Enter: ESC (hyphen)

! appears on screen

FORMAT. LED on
Screen clears
Cursor homes

WRAPAROUND to YES
Enter: QWerty •••

QWERTY ••• appears
in foreground
in tens i ty and
wraparound occurs.
I appears at cursor position. Cursor moves to next
line.
II appears at cursor position.
QWERTY •••
••• Y is printed.
No change

••• y

Enter: ESC c N

Enter: ESC cS N

Enter ESC (hyphen)

No change

QWerty ••• appears on
screen
No change

) appears (followed by
EOT which may be displayed as CD).

Printer On-Line
light comes on.

Enter ESC /
Enter some random
characters and press
SEND

Characters are
printed.
Enter some random characters

Press RESET

Characters continue on
second row.

(followed by EOT which
may be displayed as CD)

Enter: ESC #
ESC cSL

F.:lter: ESC ?

MASTER TERMINAL

Characters are displayed and printed.
LOCAL LED is on.
Printer On-Line
light goes out.
LOCAL and FORMAT
LEOs go out.

4-16

Characters are displayed

HI-1053A

4.2.11

Printer Buffer Serial Output Checks (1520 only).
1.

Connect the PRINTER .output connector to EIA/CL connector

J2 with a cable as sh.own in figure 4-4.
2.

Select 110 baud, zero parity, and FORMAT mode at the terminal

and set the printer buffer switches as follows:

Sl-1 and Sl-2, Up; Sl-3,

Down.
3.

Turn power on and enter some random characters on the

4.

Press spRINT.

screen.
The print symbol should appear on the top

line and the characters duplicated on the second line in background
intensity.
5.

Set printer buffer switch Sl-2 down, and the terminal

BAUD RATE switches for 300.
.
s
6. Press PRINT. The second line should be repeated on line
3.

7.

Set printer buffer switch Sl-l down, and the terminal

BAUD RATE switches for 1200.
8.

Press spRINT.

The third line should be repeated on line

4.

PRINTER

EIA/CL
~

r--

1

I

3

3

7

5

.-

L

7

DB25P CONNECTORS

II

EIA FEMALE HOUSINGS
WITH MALE PINS

6
8
12

20
L-.-/

'-7801026

Figure 4-4.

Serial Print Test Cable
4-17

HI-1053A
4.3

TESTING AND TROUBLESHOOTING

4.3.1

Keyboard/Logic Assembly and

4.3.1.1

P~inter

Buffer.

Test and troubleshoot'the keyboard/logic assembly and the

printer buffer using the Automatic Card Tester and the appropriate
adapter and tape set.
4.3.1.2

The following guide is furnished as an aid to limited

troubleshooting of the keyboard/logic assembly and printer buffer
with a multimeter and oscilloscope, and should permit a technician
with a thorough knowledge of the theory of operation to isolate the
cause of a majority of logic failures.

Reference designations are

for the '246-() boards, with the '202 board designations in parentheses.

The dc power distribution should be checked (figure 2-3)

before logic circuit troubleshooting.
2
With two exceptions, all logic levels are positive T L:

4.3.1.3

Zero
One

= 0.0 to 0.4 vdc
= 2.4 to 5 vdc

The exceptions are:
a.

EIA inputs at U58 (U54) and outputs from U70 (U65) in

the serial I/O area and inputs to Ul and outputs from U2 on the'
printer buffer board:
Zero = +10 vdc
One
b.

=

Control Signals, True

-10 vdc

False

=
=

+10 vdc
-10 vdc

Clock signals from U8 to the microprocessor U3l, which

are nominally 10 volts (9.4 min.) at 2 MHz (see figure 1-12).
4.3.1.4

Use table 4-1 as a guide to the probable area at fault.

After checking dc supply voltage levels, look first for a steady
high or low level logic signal which should be changing for the
mode of operation in effect.

The most common modes of failure in

integrated circuits result in a constant high or low at an output.
If this condition is found, the chip which is the source of the
signal is more likely to be at fault than the chip or chips which
receive the ,signal.

4-18

HI-1053A
Monitor and 5-volt regulator
The monitor and 5-volt regulator are covered in Section 3.
4.3.2

ALIGNMENT
The keyboard/logic assembly and printer buffer require no alignment.
Alignment of the monitor and the 5-volt regulator are covered in
Section 3.
4.4

4-19

HI-I053A
Table 4-1.

Limited Troubleshooting Guide
GENERAL NOTES

1.

Ref. designations are for '246-( ) boards with '202 board
designations following in parentheses when different.

2.

It is assumed that power distribution has been checked and
fault has been isolated to the keyboard/logic assembly and/
or printer buffer.

3.

Simple faults which can be isolated from the schematic alone
are not covered. Note that simple failures can result in
major malfunctions (e.g. terminal in wrong mode due to selector switch failure or failure of a register).

4.

The guide is limited to troubleshooting which can be performed with a multimeter and oscilloscope.

Trouble

Probable Cause

No video. POWER ON LED
and monitor OK

a.
b.

Display shakey, flashing or missing dots, or
raster but no characters

Video module

Video Module
TV Synchronizer

~

After turn-on, the
top 12 lines, and
the first 68 chars.
on line 13 are
stored in the low address block of memory
U24-U3l (U22-U29) and
the balance of the
screen in Ull-U18
(U9-U16). After
scrolling begins the
locations change.

Type c G• Alarm should sound for 1/3 s.
If missing, or exc~ssively long or short,
fault is probably in TV sync module (see
fig. 1-10 and 1-11). Otherwise fault is
probably in video module. Trace back
from U7l (U75) with scope. Output from
U7l should be 60 ns pulses at 3 v for
foreground and 2 v for background
Data from character generator U83 (U78)
is loaded into U93 (U77) when S/L (pin
15 of U93 (U77) is low. When S/L goes
high data is shifted out of U93 (U77) in
parallel on leading edge of clock at pin
7. A full TV line of data is read into
line buffer U63/U64 (U67/U57) via U66/
U65 (U68/U58) when sync bus d1sable is
low, and recirculated on the trailing
edge of the LBC when sync bus d1sable is
high. Faults confined to a particular
line or lines (e.g. all characters display fault in third line) is characteristic of failure in character line
counter area U84.

NOTE
Entering a stream of background Su
characters (code 01010101) and foreground s* characters (code 10101010)
will fully exercise all bits of the
video module.

Wrong character on
screen from keyboard

Remarks

a. Same error in char.
transmitted:
Keyboard
Keyboard encoder
b. Transmitted char.
OK:
Char. gen U83
(U78)
Display memory

4-20

K/B encoder output is transferred to
data bus when KBR5Y U60 pin 4 (U55 pin
4) goes low. If fault is consistent
over screen (e.g. keying B results in
displaying A anywhere on screen) fault
is probably in character generator. If
fault is confined to certain display locations and moves when scrolling occurs,
fault is probably in memory

HI-1053A

l'able 4-1.

Limited Troubleshooting Guide (Cont)
Probable Cause

Trouble

Remarks

Garbage characters
on screen at turn on.
Cannot clear.

a. Power distribution
b. ,Display memory
c. Microprocessor
module
d. Program memory

a. Check dc voltage at pins listed in
table 4-2
b. If characters scroll, fault is
probably in memory (see note in preceding en try) •
c/d. Full isolation between ROM and
microprocessor module is not practical
without special equipment. However,
peripheral causes can be eliminated.
Check for presence of clock/timing
signals (ref. to para. 4.3.1.3 b).
Holding the RESET button down will
keep the microprocessor and refresh
address counter off the address and
data busses to permit checking for
shorts on the busses.

Constant reverse video
or no ~everse video

a.
b.

a. Pin 8 of test socket U38 (pin 10
of U35A) should be low for reverse
video and high for normal video
b. U92/U94 (U76/U80)

Display is foreground
only or background
only

a. Transmission of
protected data only
can be selected
b. Transmission of
protected data only
cannot be selected

a. Foreground/background bit not being latched by U62 (U56)
b. Ull/U24 (U9/U22)

Constant character
window for entire
display

Character generator

U83 (U78)

Vertical bars on
screen.
Cannot clear

Character generator

U83 (U78)

Some keyboard characters cannot be
entered properly,
others OK

Keyboard
Keyboard encoder

If the problem characters have a common x or Y coordinate, trace that signal. Scan is generated (x) at encoder
U60 (U55) and returned (y) when key is
depressed. If keyboard lockout occurs
(holding a problem key down prevents
entry of a character which can otherwise be keyed) fault is probably in the
encoder.

No cursor or video.
Transmitted characters

TV synchronizer
Refresh address
counter
Microprocessor module

Refer to para. 1.3.7 and figs. 1-10 and
1-11

Display rolls. Data
can be entered.

TV synchronizer

Check for vertical drive at J101-3

S2
Video module

4-21

I

HI-I053A
Table 4-1.

Limi ted Troubleshooting Guide. (Cont )
Probable Cause

Remarks

No transmitted data
or wrong data transmitted

Serial I/O module or
interface

. If data is displayed in full duplex
with jumper (fig. 2-1 c) but not transmitted in half duplex, check clear-tosend (CB) and data set ready (CC) at
J2-5 and -6. One of these inputs ~ust
be true (high) to enable half duplex
transmission (ref. to para 4.3.1.3 a).
If data cannot be transmitted in any'
mode, trace back the data signal (BA)
from J2-2 (EIA) or J2-2l/-25 (cur loop).
Check baud rate (para. 4.2.7).

No received data or
wrong data received

Serial I/O module

Trouble

Trace received data (BB) from J2-3. Each
input character should cause an RDA high
at U54 (U49) pin 19. Character should
be on data bus when RDE goes low at pin

4.
Wrong or missing characters in batch and/or
page transmissioris.
Other t~ansmissions OK.

RAM

U36, U37

PRINT function does
not work. Data senti
received printed OK
when printer is online

Microprocessor
ROM
Printer buffer memory

If printer rate is equal to or greater
than the terminal baud rate, the printer
buffer memory will not be required in
on-line mode but will be used for PRINT
function

Data sent/received
not printed when
printer is on line.
PRINT function OK.

Interface

Check for printer on line signal high at
U25 pin 2 of printer buffer

No data printed.
Transmission & display OK

Printer buffer or
interface

a.

Table 4-2.

Serial Printer:
Check serial printer busy false
(high) at Jl-49 (ref. para. 4.3.1.3 a).
Check baud rate of output at Jl-24.
b. Parallel Printer:
Check par printer busy false (low)
at Jl-25 and printer out of paper false
(low) at Jl-26

DC Voltage Usage

+12 VDC
Ref. Des.
'202
'246-( )

-12 VDC
Pin

Ref
'246-( )

28

U63/U64

U8

8080
8224

9

U54

U57/U67
U49

U20

U18

8228

23*

U70/U48

U44/U65

MC1488

1

--

U78

MCM6570

3

U60

U55

AY5-3600

27

U45

U4l

COM5016

9

01
U74

2N2222

C**

U33

U3l

U8

01
U8l
U70/U48

U65/U44

Type

3409
AY5-l0l3

2

Type

Pin
12

-5 VDC

U30

opto-iso. 5'***
MC1488

Des.
'202

14

U3l

8080

11

U78

MCM6570

1*

*-3 vdc via R45/R46

*via R17(R13) lK
**via R53(R43) 150
***via R92(R44) 5.6K

4-22

HI-I053A
APPENDIX A
RECOMMENDED SPARE PARTS LIST
The following is a listing of recommended spare parts, consisting
primarily of parts designed or programmed especially for the terminal, and parts not readily available. Refer to the schematic diagrams in Appendix B for type numbers or values for other components.
Items recommended to support site and shop maintenance are indicated
by an X in the appropriate column.. Recommended quantities are shown
for support of I to 25 units and 26 to 50 units at the factory or
depot level.

A-l

HI-I053A
Table A-I.

Spare Parts List

1

Level
Ref
Des

Usable
On Code·

Hazelti.ne
Part No.

Description

Site
Maint

Shop Factory/De?c-:.
Maint 1-25 26-50

Major Assemblies

-

1DTD1552l3
A,B
C

4DTD1552l5
4DTD1552l5-l
lDTD702l24
30'1'0155206
4DTD155202
or
4DTD155246-1
4DTD155246-2
4DTD155205
4DTD155251
IDTD702134

Tl

-

-

Al
A2
B,C

-

-

C

CRT, Yoke and Video
Filter
5-V Regulator Assembly
5-V Regulator Assembly
Power Transformer
Switch Bracket Assembly
Keyboard/Logic Assembly

X

X

X
X
X
X
X

X

Keyboard/Logic Assembly
Monitor Chassis Assembly
Printer Buffer Board
Video Fi! ter

X
X
X
X

1

1

1
1
1

2
2
2

1

2

1
1

2
2

1
1

1

I:
~

2

Components and Subassemblies/Honitor

-

4DTD155192
lSPS271472
lSPS430013-5
IDTD702108
IDTD702114
lSPS351B45

C26
F2
T2
T3
U3
Al

-

U31
U39
U41
U49
U44,U65
U54
U55
U71
U7B

-

-

U8
U11-U1B
U24-U31
U20
U22
U23
U36,U37
U33
U43
U45
U54
U48,U70
USB
U60
U90
UB3

-

X

X
X
X

X
X
X

1

2

5
1
1
1

1
5
2
1
2

lSPS431001
lSPS912797
lSPS9100Bl-3

Circuit Breaker
Clock Generator
~Iemory

1
1
1

I
r
I

i

I

B,C
B,C

Al
A2, B,C

lSPS71279B
1DTD702127

System Controller
Program ROM

1
1

lSPS9l2781
ISPS910155
lSPS702129
lSPS912799
lSPS910B02
lSPS91007l**
lSPS910072."
IDTD702130
IDTD70212B
1DTD702122
IDTD702145

RJ\....!

1
1
1
1

:.ucroprocessor unit
Baud Rate PROB
Baud Rate Generator
UART
EIA Line Driver
EIA Line Receiver
Keyboard Encoder
Horizontal PRO:·!
Character Generator
Character ROM

I

I

2
2

1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2

1
1

2
2

1

Components/Printer Buffer
C
C

lSPS912B13
lSPS912B14

Microprocessor Unit
I/O Expander

·Usab1e on Codes
A
Al
A2
B
C

:

2
2
2

j
US
U9

!

I

Components/Chassis and Logic Board

A2, B, C

UB
U9-U16
U22-U29
ulB
U20

Honitor Board
Capacitor
Fuse
Transformer
Flyback Tra~sformer
Rectifier

Model 1500
Keyboard/Logic Assembly 4DTDlS5202
Keyboard/Logic Assembly 4DTDlS5246-1
Model 1510
Model 1520

·*A1so U2 on Printer Buffer
·**A1so Ul on Printer Buffer
C'77019

1\-2

I

I

HI-1053A
APPENDIX B
DIAGRAMS
This section contains an exploded view of the terminal, showing
the location of chassis-mounted parts, an interconnection diagram,
and schematic diagrams of all circuits in the terminal.
Figure

Title

B-1

Terminal, Exploded View

B-2

Interconnection Diagram •

• • •

B-4

B-3

Five-Volt Regulator, Schematic Diagram • •

B-5

B-4

Monitor, Schematic Diagram • • • • • • • •

B-6

B-5

Logic/Keyboard Assembly Part No. 4DTD155202,
Schematic Diagram • • • • • •
••..••

B-7

Logic/Keyboard Assembly, Part No. 4DTD155202 1
Parts Location. • • • • • • • • • • • •
• • •

B-16

Five-Volt Regu+ator, Parts Location • • • • •

B-17

Logic/Keyboard Assembly Part No. 4DTD155246-( ),
Schematic Diagram • • • • • • • • • • • • . • • •

B-18

B-9

Printer Buffer, Schematic Diagram • • • • • • • •

B-27

B-lO

Logic/Keyboard Assembly Part No. 4DTD155246-l,
Parts Location~ . • • • • • • • • • • • • • • • •

B-28

Logic/Keyboard Assembly Part No. 4DTD155246-2,
Parts Location . • • • • • • • • • • • • • • • • •

B-29

B-6

B-7
B-8

B-ll

B-2

B-1

HI-1053A

COVER AND
MONITOR
ASSEMBLY
(SHEET 2)

L

I

\ -1 I
P102

\ ~I

))~

"/
('

I

I

PRINTER
CONNECTOR*
POWER
............--SWITCH
Sl
CIRCUIT
BREAKER

*H1520 ONLY
7704103

Figure B-1.

Terminal," Exploded View (Sheet 1 of 2)

B-2

HI-1053A

FLY BACK
TRANSFORMER
T3

1I~ r,,!'
r
I

(~t..

I

...

Q2 -----+l----r-~

Q5

7704074

Figure B-1. Terminal, Exploded View (Sheet 2 of 2)
B-3

HI-I053A

AJIP I- ".80101·0
.JSOS70-.J

~

__________ ~ _

~
~... Z

..;,.I+~-:i

: 3

~

r--_ _ _ _ _

~

,----- -

~~

~----------~_3~; :~/-------~~

:::ra

-

I
____________________________________________

N~
1

1.1 D AJ !To R..

1f55 EA./ ~~ 'I

~r-~--------~

~7

I , UJ

____------__rh
~

-t..AMP /--ISQ700-0
~soS'I-J

.--

I

EI

I

01

I,

11-----15

..

5

IS IS

~-------+----------------------~N
L.-._ _ _ _-I

PIf'IMARY

//SI//I(J:t/()~
r- - ,

~~--------------~_

,

\ t=.RH.1J

FI1STON

) Wl4lu

I

FE~RLE

I
,440LDEIJ

U,~A~

VoL .4PPf..'(NC[)
,3 WIRE J.IN~· CO'D

I

--:1',

MU METAL- _
61-11~Lt> IF Re-QO

,

to

I

I

TJ

I

.1

35~22'"

3532Z4
35J ZZ.3
~ S~ '213-~
~ S32.1~-(.

a"S,?> 2.' S

AM~

AMP l-~ ~0700-0
AMP 350570 -.3
Aj.{p 3505""-.3

J8
PB

8

W/lr

/86,At/6£
ZC-22 GAU~

PI~p e-b"101ab-1.

PS)P3 (CON11\C.,...s)

z- t.~o lab-2

~~( CC"-l"AC..I~)

II

II

blb~

Figure B-2.

ft-j

Interconnection
Diagram
B-4

r-'-'

~J

1'->S)
PB (~,.vs)

PlD

:--

Yet.
91--+~:::::=--'J--I
7
I~R/{
I~ ~-4-==::':":':"4--1 2
RiD
16~---+-;~:-f--I 3
SLUe
/(, .........~;..;..;...;~-I
4
8wN

'---

~

8wII

VI()I.ET

/r ~IN

(Stu:: LL)

eORRO

18

'--__________
"" Ii' ~

(~HELL..)

L06IC.

'I

~mr-(JAlJ

D~SI

17

MOIJITCJ~

I;/-

Ct;"A/rR.tf.L
61?otlAllJ

1-'1 fr07ol-o

Q5~r---In

L'J6S
BOAAO

18 G,fv<$oe

~I\JD~_~.

20

BI./iG

--

SPs. ;;

.-------~'l()

J4. P4-

i..VG

=
3512ZS-

12

wl'T~

"
~-----~~---+--,
7

L..----~)2

III

I
I

8~()u)AI

(,

5S

t=RST-or.JS

TO tw\~E
Of\) Pc.

,

4 4

Q2

6',fEEN'
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POSITION

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Figure C-2.

Interconnection Diagram,
Dwg 4DTD964406
C-3

HI-I053A

U80

IC

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Figure C-3. Serial I/O, Schematic
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HI-1OS3A
C.S Where a terminal does not have a character used as a cursor
address or remote command, that character which generates the
same code must be sUbstituted as listed in the accompanying table.

u.s.

Denmark

En;lanc!

france

Germany

Spain

SWeden

~

I

#

Italy

1

§

9

Jlf:..

0

A

0

"

0

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tJ

~

1

l

§

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u

,
e.

l

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fR

~

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:i

a:

"
u.

oe

0

..

0
0

~

••
u

e

@

[

}

a

"

0

..
A

N

..
0

0
0

a

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$

C-S/(C-6 blank)

,

n

HI-1053A

APPENDIX D
SUMMARY OF REMOTE COMMANDS
(ALL MODELS)
REMOTE
COMMANDS

LEAD-IN*
REQD (X)

KEY STROKE

..

ASCII
CODE

DECIMAL
'"

Home Cursor

X

Control-R

DC2

18

Up Cursor

X

FF

12

Down Cursor

X

Shift-Line Feed
Control-K

VT

11

Left Cursor

Back Space

BS

8

Right Cursor

Shift-Backspace

DLE

16
17,X,Y

Address Cursor

X

Control-Q

DCl,X,Y

Read Cursor Address

X

Control-E

ENQ

Clear Screen

X

Control/Shift-L

FS

28

Clear Foreground

X

Control/Shift-M

GS

29

Clear to End-of-Line

X

Control-O

SI

15

Clear to End-ofScreen

X

Control-X

CAN

Clear to End-ofScreen background spaces

X

Control-W

ETB

23

Background Follows

X

Control-Y

EM

25

Foreground Follows

X

Control/Shift-O

US

31

Delete Line

X

Control-S

DC3

19

Insert Line

X

Control-Z

SUB

26

Keyboard Lock

X

Control-U

NAK

21

Keyboard Unlock

X

Control-F

ACK

6

Audible Alarm

Control-G

7

Tab

Tab

BEL
HT

*Lead-in Code

=

ASCII ~, Decimal 126

D-l

5

i

24

9

HI-I053A
SUMMARY OF REMOTE COMMANDS
1510/1520 ONLY
LEAD-IN*
REQD (X)

REMOTE
COMMANDS

KEY STROKE

ASCII
CODE

DECIMAL

Set Format Mode

X

#

#

35

Return to
S\\7i tches * *
(Format, Half,
Full)

X

.$

$

36

Batch Transmit**

X

%

37

Line Transmit

X

.

%

.Page Transmit

X

(

Unprotected**

X

,

,

Protected and
Unprotected

X

+

+

43

Back Tab

X

c

DC4

20

Send status

X

-

-

45

Remote Xmit

X

c

SO

14

Non Stored Return

X

CR

13

RS

30

I
.

,

T

N
Return

(period) .

46
40

(

(comma)

44

Remote Print
1520, ONLY
Remote Print

X

cS

On-line PrintDisplay

X

/

/

47

On-line PrintNo Display

X

*

*

42

?

?

63

Printer Off

~ine**

X

I

N

* Lead-in Code - ASCII ~, column 7, row 14 - DECIMAL 126
or
= ASCII ESC, column 1, row 14 - DECIMAL 27
**Defau1t condition at turn on or after reset

D-2



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