Compal LA B541P Schematics. Www.s Manuals.com. R0.1 Schematics

User Manual: Motherboard Compal LA-B541P ZAR00 Delray 17 - Schematics. Free.

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Page Count: 68

A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
BOM P/N :
PCB NO :
COMPAL CONFIDENTIAL
MODEL NAME :
Delray 17
REV : 0.1 (X00)
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
@ : Nopop Component
CONN@ : Connector Component
GPIO MAP:
ZAR00
LA-B541P
i5 - 4319TQ31L01 (HSW)
i7 - 4319TQ31L02 (HSW)
PXDP@,CXDP@ : Total debug Component (pop them until ST)
2014.01.13
GPIO map rev 3.6C
Power CKT: 0108
EMC@ : EMI/ESD/RF part
TB@ : Thunderbolt function
Layout Dell logo
COPYRIGHT 2014
ALL RIGHT RESERVED
REV: X00
PWB: XXXXX
DATE: 1403-06
Broadwell H-type (2 chip)
BDW@ : HSW_BDW compatibility circuit
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Cover Sheet
1 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Cover Sheet
1 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Cover Sheet
1 67Monday, January 13, 2014
Compal Electronics, Inc.
Part
Number
Description
DAA0008R000 PCB 178 LA-B541P REV0 MB
PCB_178_LA-B541P_REV0_MB
Part
Number Description
DAA0008R000 PCB 178 LA-B541P REV0 MB
PCB_178_LA-B541P_REV0_MB
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
1.5V DDRIII 1333 /1600 /1866MHz (Overclocking)
(DDRIII) Memory Bus
DPA
DP_D
64M 4K sector
32M 4K sector
PCIE BUS
Lane x4
DELL CONFIDENTIAL/PROPRIETARY
Intel Clarkville
WGI218LM
LAN switch
RJ45
SDXC
Micro SIM Card
E-Dock
1st HDD Conn.
USB 3.0 Conn
Left Side
Digital Camera
Touch screen
Audio Codec
ALC3235
Universal Jack
Array MIC Jack
Int. Speaker
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
P.29
eDP MUX
PS8331
P.30
eDP Panel
Conn
P.31
DP 1.2
Conn
P.6~12
P.13~16BANK 0, 1, 2, 3, 4 ,5 ,6 ,7
DDRIII-DIMM X4
P.17
MXM Conn.
TYPE B
P.18~26
Intel
Lynx Point
BGA
695 Pins
Intel
Broadwell
BGA CPU
1364 Pins
(H type)
M.2 Card slot_2
WWAN/LTE/HCA/
Cache P.42
M.2 Card slot_1
WLAN/BT/WiGig
P.42
OZ777FJ2LN-B
SD4.0/MMC
P.42
M.2 Card slot_3
SSD/HCA/Cache
P.43
Free Fall Sensor
P.40
P.39
PI3L720ZHEX
Current Monitor
INA219AIDCNRG4
P.28
LNG3DMTR
P.50
Discrete TPM
AT97SC3205
SMSC SIO
ECE5048
SMSC KBC
MEC5085
P.51
FAN CONN KB/TP CONN
P.53
P.48
W25Q64FVSSIQ
W25Q32FVSSIQ
P.21
P.21
P.45
2nd HDD Conn.
P.46
ODD Conn.
USB 3.0 Conn
Left Side
P.30
P.30
On I/O board
Port 3 Port 7
Port 1
Port 4
SATA Port 5
USB Port 5 USB Port 4
Docking LAN
SATA Port 2
USB2 Port 3
DAI
RGB
LAN
USB3.0 Port 3
LPC
Docking DP
Docking DP
SATA Port 0
SATA Port 3
SATA Port 1
USB3 Port 5
USB3 Port 1
USB2 Port 8
USB2 Port 11
On I/O board
Lane x2
On I/O board
LPC BUS
BC BUS
CRT
eDP
CRT
SPI
FDI x2 DMI x4 gen 2
SATA3.0
SATA2.0
USB2.0
USB3.0
HD Audio
PEG x16 (Gen3)
PS8338B
DP SW
P.31
Fingerprint
CONN
On USH/B
BRCM5882
TPM 1.2
USB Port 7
FP_USB
TDA8034HN
Smart Card
NFC
DP_A
DP_B
DP_C
P.41
P.39
P.45
P.45
DDID
PEG
P.41
USB2 Port 2
USB2 Port 6
USB 3.0 Conn
Left Side
USB2 Port 0
USB 3.0 Repeater
PS8713B
USB 3.0 Repeater
PS8713B
USB3 Port 6
USB2 Port 9
Port 2
TBT
TBT
Conn
Port 5, Port 6
PCIE
PS8713B
USB 3.0 Repeater
USB3 Port 2
P.47
USB2 Port 1
USB 3.0 Conn
Right Side
PS8713B
USB 3.0 Repeater
P.47
USB Charger
HDMI 1.4a
Conn P.38 PS8339
DP/HDMI
DEMUX
Docking DP Port2
P.38
P.32 - 34
P.33
P.7
P.7
P.8
TPS2544
USB Power Share
P.47
Port 8
USB Port 10
SATA Port 4
P.27
P.7
P.7
P.8
P.6
P.6
P.5
P.4
P.4
P.4
BCM20793
DPC
P.35
CRT switch
MAX14885
CRT
CRT (MXM)
Docking RGB
P.35
CRT Conn
Docking DP Port1 P.37
PS8338
P.42
DP MUX
PS8331
P.36
DDID
DPB
M.2
WiGig
Conn
DP DEMUX
RFID
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Block Diagram
2 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Block Diagram
2 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Block Diagram
2 67Monday, January 13, 2014
Compal Electronics, Inc.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PM TABLE
DELL CONFIDENTIAL/PROPRIETARY
PCI EXPRESS
Lane 1
DESTINATION
Lane 2
Lane 3
Lane 4
POWER STATES
S0 (Full ON) / M0
SLP
S3#
SLP
S5#
HIGH
Signal
State
SLP
S4#
HIGH HIGH HIGH
S4
STATE#
ALWAYS
PLANE
ON
M
PLANE
ON
SUS
PLANE
RUN
PLANE
CLOCKS
ON ON ON
S3 (Suspend to RAM) / M1 LOW HIGH HIGH HIGH ON ON ON OFF
S4 (Suspend to DISK) / M1 ON ON OFF
SLP
M#
HIGH
HIGH
LOW HIGH HIGHLOW
S5 (SOFT OFF) / M1 ON ON OFFLOW LOW HIGHLOW
S3 (Suspend to RAM) / M-OFF
S5 (SOFT OFF) / M-OFF
LOW HIGH HIGH HIGH LOW ON ONOFF OFF OFF
LOW LOW LOW LOW ON OFF OFF OFF OFF
LOW LOW LOW LOW LOW ON OFF OFF OFF OFF
S4 (Suspend to DISK) / M-OFF HIGH
Lane 5
Lane 6
+3.3V_M +3.3V_M
(M-OFF)
ON
ON
ON
ON
OFF
OFF
OFFOFF
+3.3V_SUS
+5V_ALW
+5V_RUN
+3.3V_ALW_PCH
+1.35V_MEM
S0
S3
S5 S4/AC don't exist
ON
power
plane
S5 S4/AC
State
OFFON
ON
ON
ON ON
OFF
OFF
OFF
OFFOFF
+3.3V_RTC_LDO
+1.05V_M
M.2 Slot-2 (WWAN/LTE/HCA)
8
9
10
11
2
3
1
4
USB PORT#
0
DESTINATION
6
5
7
PCH
Lane 7
Lane 8
12
13
LOW
LOW
OFF
OFF
+1.05V_M
OFF
OFF
OFF
+3.3V_RUN
+0.675V_DDR_VTT
+1.5V_RUN
+VCC_CORE
+1.05V_RUN
0
1
BIO
NA
USH
IO Board- JUSB1 (Ext Left Side)
JUSB1 (Ext Right Side)
IO Board- JUSB2 (Ext Left Side)
Stack up
Docking USB3.0
NA
USH
Docking USB 2.0
M.2 Slot-3 (SSD/HCA/Cache)
Camera
NA
Touch Screen
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
M.2 Slot-1 (WLAN/BT/WiGig)
Port 1
USB3.0 DESTINATION
Docking
Port 2
Port 3
Port 4
Port 5
Port 6
HDD 1
SATA
SATA 0
DESTINATION
SATA 1
SATA 2
SATA 3
SATA 4
SATA 5
Dock
ODD
HDD 2
JUSB1 (Ext Right Side)
IO Board- JUSB1
IO Board- JUSB2
NA
+3.3V_ALW
+PWR_SRC_S
+PWR_SRC
+3.3V_MXM
+5V_MXM
+MXM_PWR_SRC
IO Board- JUSB3 (Ext Left Side)
10/100/1G LOM
M.2 Slot-3 (SSD/HCA/Cache)
MMI(Card reader)
M.2 Slot-2 (WWAN/LTE/HCA)
TBT-1
M.2 Slot-1 (WLAN/BT/WiGig)
TBT-2
M.2 Slot-1 (WLAN/BT/WiGig)
M.2 Slot-2
M.2 Slot-3
IO Board- JUSB3
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Index and Config.
3 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Index and Config.
3 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Index and Config.
3 67Monday, January 13, 2014
Compal Electronics, Inc.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+3.3V_WLAN
+LCDVDD
+3.3V_WWAN
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
+VCC_CORE
(PU500)
ISL95812
+5V_USB3
BATTERY
+PWR_SRC
ADAPTER
FDC654P +BL_PWR_SRC
EN_INVPWR
CHARGER
+3.3V_ALW
TPS51225
+5V_ALW
ALWON
TPS22966
+3.3V_SUS
RUN_ON
+5V_HDD
(Q21)
(PU101)
(U63)
+1.35V_MEM
RT8207
(PU200)
+1.05V_M
+0.675V_DDR_VTT
A_ON
TPS51212
(PU300)
+3.3V_M
A_ON
AUX_EN_WOWL
(Q24)
DMG2301U
CCD_OFF
+CAMERA_VDD
SI4835DDY +MXM_PWR_SRC
3.3V_RUN_GFX_ON
(Q186)
3.3V_WWAN_EN
+5V_RUN
+3.3V_RUN
+V_DDR_REF
IMVP_VR_ON
RUN_ON
SI4164DY
(Q63)
+1.05V_RUN
RUN_ON
+5V_USB1
LCD_VCC_TEST_EN
MXM_ENVDD
ENVDD_PCH
(U6)
TPS2560
+5V_MOD
Docking
(U49)
TPS22965
(U43)
TPS22966
(U40)
TPS22966
(U37)
TPS22966
(U42) APL3512ABI
(U33)
TPS22966
1.05V_0.8V_PWROK
SIO_SLP_A#
SIO_SLP_S4#
APL5930
(PU400)
+1.5V_RUN
+3.3V_LAN
+3.3V_ALW_PCH
SIO_SLP_LAN#
PCH_ALW_ON
NVRAM_PWR_EN
+3.3V_SSD
3.3V_RUN_GFX_ON
+5V_MXM
SIO_SLP_WLAN#
TPS22965
(U34)
+3.3V_MXM
3.3V_RUN_GFX_ON
SIO_SLP_S3#
MODC_EN
SIO_SLP_A#
SIO_SLP_S4#
+5V_ALW
(UI1)
TPS2544
USB_PWR_EN2#
+5V_USB_PWR1
+5V_USB2
(U9)
TPS2560
IO Board
(PU600)
RT9297 +12VS_TB
TBT_HV_EN
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Power Rail
4 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Power Rail
4 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Power Rail
4 67Monday, January 13, 2014
Compal Electronics, Inc.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
K6N11
200
DIMM1
202
DIMM2
200
202
A50
B53
1D
B6A5
+3.3V_ALW_PCH
B49
B48
2.2K
2.2K
31
28
B50
1G
1G
A47
1C
1C
B59
A56
+3.3V_ALW
2.2K
2.2K
100 ohm
100 ohm BATTERY
CONN
7
6
SMBUS Address [0x16]
PBAT_SMBCLK
PBAT_SMBDAT
1D
+3.3V_ALW
129
127
SMBUS Address
2.2K
DOCK_LCD_SMBCLK
DOCK_LCD_SMBDAT
DOCKING
2.2K
B4
A3
1A
1A
1E
1E
2.2K
2.2K
SMBUS Address [0xC8]
LOM
USH
KBC
+3.3V_SUS
USH_SMBCLK
USH_SMBDAT
U11
R10
1H
1H
MEC 5085
MEM_SMBDATA
53
51
SMBUS Address [TBD]
XDP1
SMBUS Address [TBD]
XDP2
53
51
68
70
GPU_SMBCLK
GPU_SMBDAT
MXM SMBUS Address [TBD]
+3.3V_RUN
@2.2K
@2.2K
SML1_SMBDATA
PCH
SML1_SMBCLK
MEM_SMBCLK
+3.3V_ALW_PCH
2.2K
2.2K
U8
R7
CHARGER_SMBCLK
CHARGER_SMBDAT
Charger SMBUS Address [0xFF]
+3.3V_LAN
2.2K
2.2K
LAN_SMBCLK
LAN_SMBDATA
DMN66D0LDW
DMN66D0LDW
APR_EC: 0x48
SPR_EC: 0x70
MSLICE_EC: 0x72
USB: 0x59
AUDIO: 0x34
SLICE_BATTERY: 0x17
SLICE_CHARGER: 0x13
SMBUS Address [0x9a]
SMBUS Address
SMB_ADM1032: 0x98
SMB_DIAG_DUMP: 0x04
SMB_DIAG_DUMP2: 0x05
SMB_BLACKTOP: 0x60
5
6
SMBUS Address [0xa4]
9
8
+3.3V_ALW
2.2K
2.2K
SMBUS Address [A0h]
A0h --> 1010 0000
SMBUS Address [A4h]
A4h --> 1010 0100
DIMM3
200
SMBUS Address [A4h]
A4h --> 1010 0100
202
DIMM4
200
202
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
SMBUS Address [A0h]
A0h --> 1010 0000
DMN66D0LDW
DMN66D0LDW
6
SMBUS Address [TBD]
LNG3DMTR
4
+3.3V_RUN
2.2K
2.2K
Difference with Diesel
Difference with Diesel
remove EXP card
remove WWAN
eDP Panel
DMN66D0LDW
DMN66D0LDW
SMBUS Address [TBD]
20
21
Difference with Diesel
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
SMBUS Bolck Diagram
5 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
SMBUS Bolck Diagram
5 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
SMBUS Bolck Diagram
5 67Monday, January 13, 2014
Compal Electronics, Inc.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
CAD Note:
Trace width=12 mils ,Spacing=15mil
Max length= 400 mils.
PEG_COMP
PEG_COMP
PEG_CRX_GTX_C_P[0..15]
PEG_CRX_GTX_N10
PEG_CRX_GTX_N4
PEG_CRX_GTX_N13
PEG_CRX_GTX_N7
PEG_CRX_GTX_N6
PEG_CRX_GTX_N2
PEG_CRX_GTX_N1
PEG_CRX_GTX_N15
PEG_CRX_GTX_N5
PEG_CRX_GTX_N9
PEG_CRX_GTX_N14
PEG_CRX_GTX_N8
PEG_CRX_GTX_N12
PEG_CRX_GTX_N3
PEG_CRX_GTX_N0
PEG_CRX_GTX_N11
PEG_CRX_GTX_P13
PEG_CRX_GTX_P0
PEG_CRX_GTX_P5
PEG_CRX_GTX_P6
PEG_CRX_GTX_P2
PEG_CRX_GTX_P8
PEG_CRX_GTX_P4
PEG_CRX_GTX_P3
PEG_CRX_GTX_P7
PEG_CRX_GTX_P9
PEG_CRX_GTX_P15
PEG_CRX_GTX_P14
PEG_CRX_GTX_P10
PEG_CRX_GTX_P11
PEG_CRX_GTX_P12
PEG_CRX_GTX_P1
PEG_CTX_GRX_C_N14
PEG_CTX_GRX_C_N7
PEG_CTX_GRX_C_N0
PEG_CTX_GRX_C_N3
PEG_CTX_GRX_C_N1
PEG_CTX_GRX_C_N4
PEG_CTX_GRX_C_N8
PEG_CTX_GRX_C_N5
PEG_CTX_GRX_C_N2
PEG_CTX_GRX_C_N6
PEG_CTX_GRX_C_N9
PEG_CTX_GRX_C_N12
PEG_CTX_GRX_C_P1
PEG_CTX_GRX_C_P2
PEG_CTX_GRX_C_N15
PEG_CTX_GRX_C_N10
PEG_CTX_GRX_C_P0
PEG_CTX_GRX_C_N11
PEG_CTX_GRX_C_N13
PEG_CTX_GRX_C_P3
PEG_CTX_GRX_C_P8
PEG_CTX_GRX_C_P11
PEG_CTX_GRX_C_P14
PEG_CTX_GRX_C_P5
PEG_CTX_GRX_C_P10
PEG_CTX_GRX_C_P4
PEG_CTX_GRX_C_P12
PEG_CTX_GRX_C_P15
PEG_CTX_GRX_C_P6
PEG_CTX_GRX_C_P7
PEG_CTX_GRX_C_P9
PEG_CTX_GRX_C_P13
PEG_CTX_GRX_P[0..15]
PEG_CTX_GRX_N[0..15]
PEG_CRX_GTX_C_N0
PEG_CRX_GTX_C_P0
PEG_CRX_GTX_C_N1
PEG_CRX_GTX_C_P1
PEG_CRX_GTX_C_P2
PEG_CRX_GTX_C_N2
PEG_CRX_GTX_C_N3
PEG_CRX_GTX_C_N4
PEG_CRX_GTX_C_P3
PEG_CRX_GTX_C_P4
PEG_CRX_GTX_C_N5
PEG_CRX_GTX_C_N6
PEG_CRX_GTX_C_N7
PEG_CRX_GTX_C_P5
PEG_CRX_GTX_C_P7
PEG_CRX_GTX_C_P6
PEG_CRX_GTX_C_N8
PEG_CRX_GTX_C_N9
PEG_CRX_GTX_C_N10
PEG_CRX_GTX_C_P8
PEG_CRX_GTX_C_P9
PEG_CRX_GTX_C_N11
PEG_CRX_GTX_C_P12
PEG_CRX_GTX_C_N12
PEG_CRX_GTX_C_P11
PEG_CRX_GTX_C_P10
PEG_CRX_GTX_C_P13
PEG_CRX_GTX_C_N13
PEG_CRX_GTX_C_N14
PEG_CRX_GTX_C_N15
PEG_CRX_GTX_C_P14
PEG_CRX_GTX_C_P15
PEG_CTX_GRX_N0
PEG_CTX_GRX_N1
PEG_CTX_GRX_N2
PEG_CTX_GRX_N3
PEG_CTX_GRX_N4
PEG_CTX_GRX_N5
PEG_CTX_GRX_N7
PEG_CTX_GRX_N6
PEG_CTX_GRX_N8
PEG_CTX_GRX_N9
PEG_CTX_GRX_N12
PEG_CTX_GRX_N11
PEG_CTX_GRX_N10
PEG_CTX_GRX_N13
PEG_CTX_GRX_N14
PEG_CTX_GRX_N15
PEG_CTX_GRX_P0
PEG_CTX_GRX_P1
PEG_CTX_GRX_P2
PEG_CTX_GRX_P3
PEG_CTX_GRX_P4
PEG_CTX_GRX_P5
PEG_CTX_GRX_P6
PEG_CTX_GRX_P7
PEG_CRX_GTX_C_N[0..15]
PEG_CTX_GRX_P8
PEG_CTX_GRX_P9
PEG_CTX_GRX_P10
PEG_CTX_GRX_P11
PEG_CTX_GRX_P12
PEG_CTX_GRX_P13
PEG_CTX_GRX_P14
PEG_CTX_GRX_P15
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CTX_PRX_N0
DMI_CRX_PTX_N2
DMI_CTX_PRX_P2
DMI_CTX_PRX_P1
DMI_CRX_PTX_N0
DMI_CRX_PTX_P0
DMI_CRX_PTX_N3
DMI_CTX_PRX_N3
DMI_CRX_PTX_P3
DMI_CTX_PRX_P3
DMI_CTX_PRX_P0
DMI_CTX_PRX_N1
DMI_CRX_PTX_N1
DMI_CTX_PRX_N2
+VCOMP_OUT
PEG_CTX_GRX_N[0..15] <17>
PEG_CTX_GRX_P[0..15] <17>
PEG_CRX_GTX_C_P[0..15] <17>
PEG_CRX_GTX_C_N[0..15] <17>
DMI_CRX_PTX_P0<19>
DMI_CRX_PTX_N3<19>
DMI_CRX_PTX_P1<19>
DMI_CRX_PTX_N1<19>
DMI_CRX_PTX_P3<19>
DMI_CRX_PTX_N2<19>
DMI_CRX_PTX_P2<19>
DMI_CRX_PTX_N0<19>
DMI_CTX_PRX_N0<19>
DMI_CTX_PRX_N1<19>
DMI_CTX_PRX_N2<19>
DMI_CTX_PRX_N3<19>
DMI_CTX_PRX_P0<19>
DMI_CTX_PRX_P1<19>
DMI_CTX_PRX_P2<19>
DMI_CTX_PRX_P3<19>
FDI_CSYNC<19>
FDI_INT<19>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Broadwell (1/7)
6 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Broadwell (1/7)
6 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Broadwell (1/7)
6 67Monday, January 13, 2014
Compal Electronics, Inc.
CC75 0.22U_0402_16V7KCC75 0.22U_0402_16V7K
12
CC47 0.22U_0402_16V7KCC47 0.22U_0402_16V7K
12
CC8 0.22U_0402_16V7KCC8 0.22U_0402_16V7K
12
CC17 0.22U_0402_16V7KCC17 0.22U_0402_16V7K
12
CC58 0.22U_0402_16V7KCC58 0.22U_0402_16V7K
12
CC48 0.22U_0402_16V7KCC48 0.22U_0402_16V7K
12
CC9 0.22U_0402_16V7KCC9 0.22U_0402_16V7K
12
CC62 0.22U_0402_16V7KCC62 0.22U_0402_16V7K
12
CC26 0.22U_0402_16V7KCC26 0.22U_0402_16V7K
12
CC76 0.22U_0402_16V7KCC76 0.22U_0402_16V7K
12
CC23 0.22U_0402_16V7KCC23 0.22U_0402_16V7K
12
CC63 0.22U_0402_16V7KCC63 0.22U_0402_16V7K
12
CC72 0.22U_0402_16V7KCC72 0.22U_0402_16V7K
12
CC27 0.22U_0402_16V7KCC27 0.22U_0402_16V7K
12
CC45 0.22U_0402_16V7KCC45 0.22U_0402_16V7K
12
CC5 0.22U_0402_16V7KCC5 0.22U_0402_16V7K
12
CC20 0.22U_0402_16V7KCC20 0.22U_0402_16V7K
12
CC73 0.22U_0402_16V7KCC73 0.22U_0402_16V7K
12
CC3 0.22U_0402_16V7KCC3 0.22U_0402_16V7K
12
CC24 0.22U_0402_16V7KCC24 0.22U_0402_16V7K
12
CC6 0.22U_0402_16V7KCC6 0.22U_0402_16V7K
12
CC2 0.22U_0402_16V7KCC2 0.22U_0402_16V7K
12
PEG
DMI
FDI
HASWELL_BGA
1 OF 12
CPU1A
HASWELL_BGA1364
PEG
DMI
FDI
HASWELL_BGA
1 OF 12
CPU1A
HASWELL_BGA1364
PEG_RCOMP AH6
PEG_RXN0 E10
PEG_RXN1 C10
PEG_RXN2 B10
PEG_RXN3 E9
PEG_RXN4 D9
PEG_RXN5 B9
PEG_RXN6 L5
PEG_RXN8 M4
PEG_RXN7 L2
PEG_RXN9 L4
PEG_RXN10 M2
PEG_RXN11 V5
PEG_RXN12 V4
PEG_RXN13 V1
PEG_RXN14 Y3
PEG_RXP0 F10
PEG_RXN15 Y2
PEG_RXP1 D10
PEG_RXP2 A10
PEG_RXP3 F9
PEG_RXP5 A9
PEG_RXP4 C9
PEG_RXP7 L1
PEG_RXP6 M5
PEG_RXP8 M3
PEG_RXP10 M1
PEG_RXP9 L3
PEG_RXP11 Y5
PEG_RXP12 V3
PEG_RXP13 V2
PEG_RXP15 Y1
PEG_RXP14 Y4
PEG_TXN0 B6
PEG_TXN1 C5
PEG_TXN2 E6
PEG_TXN5 E3
PEG_TXN7 G3
PEG_TXN6 J5
PEG_TXN8 J3
PEG_TXN9 J2
PEG_TXN10 T6
PEG_TXN11 R6
PEG_TXN12 R2
PEG_TXN13 R4
PEG_TXN14 T4
PEG_TXN15 T1
PEG_TXP1 B5
PEG_TXP0 C6
PEG_TXP2 D6
PEG_TXP3 E4
PEG_TXP4 G5
PEG_TXP5 E2
PEG_TXP6 J6
PEG_TXP7 G2
PEG_TXP9 J1
PEG_TXP8 J4
PEG_TXP10 T5
PEG_TXP11 R5
PEG_TXP12 R1
PEG_TXP14 T3
PEG_TXP13 R3
PEG_TXP15 T2
DMI_RXN1
AB3
DMI_RXP0
AB1
DMI_RXP1
AB4
DMI_TXN2
AG4
FDI_CSYNC
F11
DMI_TXP1
AF3
DMI_RXN3
AC1 DMI_RXN2
AC3
DMI_RXN0
AB2
DISP_INT
F12
DMI_TXP3
AG1 DMI_TXP2
AG3
DMI_TXP0
AF1
DMI_TXN3
AG2
DMI_TXN1
AF4 DMI_TXN0
AF2
DMI_RXP3
AC2 DMI_RXP2
AC4
PEG_TXN4 G4
PEG_TXN3 D4
CC70 0.22U_0402_16V7KCC70 0.22U_0402_16V7K
12
CC12 0.22U_0402_16V7KCC12 0.22U_0402_16V7K
12
CC16 0.22U_0402_16V7KCC16 0.22U_0402_16V7K
12
CC54 0.22U_0402_16V7KCC54 0.22U_0402_16V7K
12
CC25 0.22U_0402_16V7KCC25 0.22U_0402_16V7K
12
CC50 0.22U_0402_16V7KCC50 0.22U_0402_16V7K
12
CC11 0.22U_0402_16V7KCC11 0.22U_0402_16V7K
12
CC46 0.22U_0402_16V7KCC46 0.22U_0402_16V7K
12
CC15 0.22U_0402_16V7KCC15 0.22U_0402_16V7K
12
CC56 0.22U_0402_16V7KCC56 0.22U_0402_16V7K
12
CC68 0.22U_0402_16V7KCC68 0.22U_0402_16V7K
12
CC7 0.22U_0402_16V7KCC7 0.22U_0402_16V7K
12
CC55 0.22U_0402_16V7KCC55 0.22U_0402_16V7K
12
CC28 0.22U_0402_16V7KCC28 0.22U_0402_16V7K
12
CC53 0.22U_0402_16V7KCC53 0.22U_0402_16V7K
12
CC69 0.22U_0402_16V7KCC69 0.22U_0402_16V7K
12
CC10 0.22U_0402_16V7KCC10 0.22U_0402_16V7K
12
CC31 0.22U_0402_16V7KCC31 0.22U_0402_16V7K
12
CC29 0.22U_0402_16V7KCC29 0.22U_0402_16V7K
12
CC52 0.22U_0402_16V7KCC52 0.22U_0402_16V7K
12
CC21 0.22U_0402_16V7KCC21 0.22U_0402_16V7K
12
CC64 0.22U_0402_16V7KCC64 0.22U_0402_16V7K
12
CC49 0.22U_0402_16V7KCC49 0.22U_0402_16V7K
12
CC57 0.22U_0402_16V7KCC57 0.22U_0402_16V7K
12
CC74 0.22U_0402_16V7KCC74 0.22U_0402_16V7K
12
CC19 0.22U_0402_16V7KCC19 0.22U_0402_16V7K
12
CC30 0.22U_0402_16V7KCC30 0.22U_0402_16V7K
12
CC59 0.22U_0402_16V7KCC59 0.22U_0402_16V7K
12
CC60 0.22U_0402_16V7KCC60 0.22U_0402_16V7K
12
CC61 0.22U_0402_16V7KCC61 0.22U_0402_16V7K
12
CC71 0.22U_0402_16V7KCC71 0.22U_0402_16V7K
12
CC18 0.22U_0402_16V7KCC18 0.22U_0402_16V7K
12
CC14 0.22U_0402_16V7KCC14 0.22U_0402_16V7K
12
CC67 0.22U_0402_16V7KCC67 0.22U_0402_16V7K
12
CC44 0.22U_0402_16V7KCC44 0.22U_0402_16V7K
12
RC224.9_0402_1% RC224.9_0402_1%
12
CC32 0.22U_0402_16V7KCC32 0.22U_0402_16V7K
12
CC13 0.22U_0402_16V7KCC13 0.22U_0402_16V7K
12
CC77 0.22U_0402_16V7KCC77 0.22U_0402_16V7K
12
CC51 0.22U_0402_16V7KCC51 0.22U_0402_16V7K
12
CC22 0.22U_0402_16V7KCC22 0.22U_0402_16V7K
12
CC4 0.22U_0402_16V7KCC4 0.22U_0402_16V7K
12
CC1 0.22U_0402_16V7KCC1 0.22U_0402_16V7K
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Buffered reset to CPU
CAD Note:
PLACE PULL-UP RESISTOR WITHIN 2 INCH OF THE CPU
PU/PD for JTAG signals
SM_DRAMPWROK with DDR Power Gating Topology
CAD Note:
Trace width=12~15 mil, Spcing=20 mils
Max trace length= 500 mil
DDR3L COMPENSATION SIGNALS
Place near JXDP1
CAD Note:
Avoid stub in the PWRGD path
while placing resistors RC25 & RC130
For ESD concern, please put near CPU
CIS LINK OK
CIS LINK OK
RC5 need to close to JCPU1
place RC129 near CPU
Difference with Diesel
Remove +1.05V_RUN to +VCCST circuit
for rPGA usage.
Difference with Diesel
follow E6 common boot code.
CIS link OK
Difference with Diesel
PM_DRAM_PWRGD_CPU
XDP_TDI_R
XDP_TDO_R
XDP_TRST#_R
XDP_TCLK_R
XDP_TMS_R
XDP_PRDY#_R
XDP_PREQ#_R
RUNPW ROK_R
XDP_OBS3_R
XDP_OBS5_R
XDP_OBS2_R
XDP_OBS1_R
XDP_OBS4_R
XDP_OBS6_R
XDP_OBS7_R
XDP_TDO
SM_RCOMP1
SM_RCOMP2
SM_RCOMP0
H_CATERR#
H_PROCHOT#
SM_RCOMP1
PCH_PLTRST#_BUF CPU_PLTRST#_R
XDP_DBRESET#_R
XDP_TCLK_R
XDP_TMS_R
XDP_TRST#_R
XDP_TDO_R
XDP_TDI_R
XDP_PREQ#_R
VCCPWRGOOD_0_R
XDP_TDI
RESET_OUT#_XDP
SM_RCOMP2
SM_RCOMP0
DDR3_DRAMRST#_CPU
PM_DRAM_PWRGD_A
XDP_DBRESET#XDP_DBRESET#_R
RUNPW ROK_R
PM_DRAM_PWRGD_CPURUNPW ROK_AND
1.35V_SUS_PW RGD
RUNPW ROK_R
PM_DRAM_PWRGD_A
XDP_TRST#
XDP_TCLK
XDP_TMS
XDP_PRDY#
XDP_PREQ#
H_THERMTRIP#
RUNPW ROK_AND
XDP_PREQ# XDP_PRDY#
H_CPUPWRGD_XDP H_CPUPWRGD
CFD_PWRBTN#_XDP CPU_PW R_DEBUG_R
RESET_OUT#_XDP
XDP_RST#_RCPU_PLTRST#_R XDP_DBRESET#
XDP_TDO
XDP_TRST# XDP_TDI
XDP_TMS
XDP_TCLK
XDP_OBS0_R
CPU_DPLL#
CPU_DPLL
CPU_SSC_DPLL#
CPU_SSC_DPLL
CPU_DMI
CPU_DMI#
CPU_PLTRST#_R
VCCPWRGOOD_0_R
H_PM_SYNC
PM_DRAM_PWRGD_CPU
H_PROCHOT#_R
H_THERMTRIP#_R
PECI_EC
H_CATERR#
CPU_DETECT#
CFG3
CFG3
+VCCIO_OUT
+1.05V_RUN
+VCCIO_OUT
+1.05V_RUN
+3.3V_RUN
+3.3V_ALW_PCH
+3.3V_RUN
+1.35V_MEM
+PCH_VCCDSW 3_3
+PCH_VCCDSW 3_3
+1.05V_RUN
+VCCIO_OUT
XDP_DBRESET# <18,19>
PCH_PLTRST#<18,19>
CPU_PLTRST#<23>
DDR3_DRAMRST#_CPU <13>
RUNPW ROK<50,51>
DDR_HVREF_RST_PCH<13,15,21>
1.35V_SUS_PW RGD<57>
PM_DRAM_PWRGD<19>
RUN_ON_ENABLE#<51,54>
SIO_PWRBTN#_R<18,19> CPU_PWR_DEBUG <11>
RESET_OUT#<11,18,19,51>
H_CPUPWRGD<23>
H_PM_SYNC<19>
CLK_CPU_DMI<20>
CLK_CPU_DMI#<20>
CLK_CPU_SSC_DPLL#<20>
CLK_CPU_SSC_DPLL<20>
CLK_CPU_DPLL#<20>
CLK_CPU_DPLL<20>
H_THERMTRIP#<23,51>
H_PROCHOT#<51,61,62>
PECI_EC<51>
CPU_DETECT#<50>
CFG3 <10>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Broadwell (2/7)
7 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Broadwell (2/7)
7 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Broadwell (2/7)
7 67Monday, January 13, 2014
Compal Electronics, Inc.
RC46 6.8K_0402_5%@RC46 6.8K_0402_5%@
12
RC88 0_0402_5%@RC88 0_0402_5%@
12
G
D
S
QC1
L2N7002WT1G_SC-70-3
@
G
D
S
QC1
L2N7002WT1G_SC-70-3
@
2
13
CC65
0.1U_0402_25V6K
CXDP@ CC65
0.1U_0402_25V6K
CXDP@
1
2
RC28 0_0402_5%@RC28 0_0402_5%@
12
RC35 51_0402_1%RC35 51_0402_1%
12
RC21 0_0402_5%CXDP@ RC21 0_0402_5%CXDP@
1 2
RC10 43_0402_5%@RC10 43_0402_5%@
1 2
T169PAD~D @T169PAD~D @
UC2
74AHC1G09GW_TSSOP5~D
UC2
74AHC1G09GW_TSSOP5~D
B
1
A
2
G
3
O4
P5
RC5 1K_0402_1%CXDP@ RC5 1K_0402_1%CXDP@
12
RC40 51_0402_1%RC40 51_0402_1%
12
RC41 51_0402_1%RC41 51_0402_1%
12
RC24 0_0402_5%CXDP@ RC24 0_0402_5%CXDP@
1 2
T170PAD~D @T170PAD~D @
RC23 0_0402_5%CXDP@ RC23 0_0402_5%CXDP@
1 2
RC62 0_0402_5%CXDP@ RC62 0_0402_5%CXDP@
1 2
UC1
SN74LVC1G07DCKR_SC70-5~D
@UC1
SN74LVC1G07DCKR_SC70-5~D
@
NC
1
A
2
G
3
Y4
P5
RC101 0_0402_5%@RC101 0_0402_5%@
12
G
D
S
QC2
DMN65D8LW -7_SOT323-3
@
G
D
S
QC2
DMN65D8LW -7_SOT323-3
@
2
1 3
MISC
THERMAL CLOCK
JTAG
DDR3L
HASWELL_BGA
PWR
2 OF 12
CPU1B
HASWELL_BGA1364
MISC
THERMAL CLOCK
JTAG
DDR3L
HASWELL_BGA
PWR
2 OF 12
CPU1B
HASWELL_BGA1364
PLTRSTIN
L54
SM_RCOMP0 BB51
SM_RCOMP1 BB53
SM_RCOMP2 BB52
SM_DRAMRST BE51
DPLL_REF_CLKP
AE6
PM_SYNC
D52
SM_DRAMPWROK
AP48
THERMTRIP
D53
PWRGOOD
F50
SSC_DPLL_REF_CLKP
Y6
DPLL_REF_CLKN
AC6
BCLKN
AB6
BCLKP
AA6
SSC_DPLL_REF_CLKN
V6
BPM#7 P51
BPM#6 U51
BPM#5 P53
BPM#3 N50
BPM#4 R49
BPM#2 P49
BPM#1 R50
BPM#0 R51
DBR F53
TDO M49
TRST M53
TDI N49
TMS M51
TCK N54
PREQ N52
PRDY N53
PROCHOT
E50
PECI
G51 CATERR
G50
PROC_DETECT
C51
RC48 0_0402_5%CXDP@ RC48 0_0402_5%CXDP@
1 2
T171PAD~D @T171PAD~D @
RC9 0_0402_5%@RC9 0_0402_5%@
1 2
RC32 51_0402_1%@RC32 51_0402_1%@
12
RC89 0_0402_5%@RC89 0_0402_5%@
12
RC51 0_0402_5%@RC51 0_0402_5%@
12
RC103 0_0402_5%@RC103 0_0402_5%@
12
RC57 56_0402_5%RC57 56_0402_5%
1 2
T172PAD~D @T172PAD~D @
RC56 0_0402_5%CXDP@ RC56 0_0402_5%CXDP@
1 2
RC52 0_0402_5%@RC52 0_0402_5%@
12
RC129 0_0402_5%@RC129 0_0402_5%@
1 2
RC55 75_0402_1%RC55 75_0402_1%
1 2
RC50 0_0402_5%CXDP@ RC50 0_0402_5%CXDP@
1 2
T173PAD~D @T173PAD~D @
RC124 1K_0402_1%@RC124 1K_0402_1%@
1 2
RC22 0_0402_5%@RC22 0_0402_5%@
12
RC27 51_0402_1%@RC27 51_0402_1%@
12
JXDP1
ACES_50559-02601-001
CONN@
JXDP1
ACES_50559-02601-001
CONN@
11
2
233
4
455
6
677
8
899
10
10 11 11
12
12 13 13
14
14 15 15
16
16 17 17
18
18 19 19
20
20 21 21
22
22 23 23
24
24 25 25
26
26
GND 27
GND 29
GND
28 GND
30
RC126 100_0402_1%@RC126 100_0402_1%@
1 2
T174PAD~D @T174PAD~D @
RC104 0_0402_5%@RC104 0_0402_5%@
12
CC156
0.1U_0402_25V6K
@CC156
0.1U_0402_25V6K
@
1 2
RC54 0_0402_5%@RC54 0_0402_5%@
12
RC13 0_0402_5%@RC13 0_0402_5%@
12
RC18 100K_0402_5%RC18 100K_0402_5%
1 2
RC53 0_0402_5%@RC53 0_0402_5%@
12
RC47 100K_0402_5%@RC47 100K_0402_5%@
1 2
RC131
1K_0402_1%
@RC131
1K_0402_1%
@
12
RC11
20K_0402_5%
@
RC11
20K_0402_5%
@
12
T167PAD~D @T167PAD~D @
RC19 1K_0402_1%RC19 1K_0402_1%
12
RC17
1K_0402_1%
@
RC17
1K_0402_1%
@
12
RC43 0_0402_5%@RC43 0_0402_5%@
12
CC140
0.1U_0402_25V6K
@
CC140
0.1U_0402_25V6K
@
1
2
RC6 0_0402_5%CXDP@ RC6 0_0402_5%CXDP@
1 2
CC66
1U_0402_6.3V6K
CC66
1U_0402_6.3V6K
1
2
RC16
1.8K_0402_1%
RC16
1.8K_0402_1%
12
RC8 1K_0402_1%CXDP@ RC8 1K_0402_1%CXDP@
1 2
RC15 0_0402_5%@RC15 0_0402_5%@
12
CC138
0.01U_0402_16V7K
CC138
0.01U_0402_16V7K
1
2
RC49 100_0402_1%RC49 100_0402_1%
1 2
RC44 62_0402_5%RC44 62_0402_5%
1 2
RC20
39_0402_5%
@RC20
39_0402_5%
@
1 2
RC130
10K_0402_5%
RC130
10K_0402_5%
12
RC64 0_0402_5%CXDP@ RC64 0_0402_5%CXDP@
1 2
RC25 0_0402_5%@RC25 0_0402_5%@
1 2
RC128 49.9_0402_1%@RC128 49.9_0402_1%@
1 2
T168PAD~D @T168PAD~D @
RC42 100_0402_1%RC42 100_0402_1%
1 2
RC26 0_0402_5%@RC26 0_0402_5%@
12
RC14
3.3K_0402_1%
RC14
3.3K_0402_1%
12
RC29 51_0402_1%@RC29 51_0402_1%@
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D59
DDR_A_D31
DDR_A_D9
DDR_A_D50
DDR_A_D42
DDR_A_D29
DDR_A_D51
DDR_A_D46
DDR_A_D36
DDR_A_D18
DDR_A_D58
DDR_A_D55
DDR_A_D14
DDR_A_D24
DDR_A_D8
DDR_A_D63
DDR_A_D49
DDR_A_D41
DDR_A_D34
DDR_A_D28
DDR_A_D25
DDR_A_D35
DDR_A_D17
DDR_A_D57
DDR_A_D54
DDR_A_D22
DDR_A_D21
DDR_A_D23
DDR_A_D7
DDR_A_D62
DDR_A_D48
DDR_A_D40
DDR_A_D33
DDR_A_D27
DDR_A_D44
DDR_A_D16
DDR_A_D56
DDR_A_D53
DDR_A_D45
DDR_A_D38
DDR_A_D20
DDR_A_D60
DDR_A_D61
DDR_A_D47
DDR_A_D39
DDR_A_D32
DDR_A_D26
DDR_A_D10
DDR_A_D43
DDR_A_D15
DDR_A_D11
DDR_A_D52
DDR_A_D37
DDR_A_D30
DDR_A_D19
DDR_A_D13
DDR_A_D12
DDR_CKE0_DIMM2
DDR_CKE1_DIMM2
M_CLK_DDR#0
M_CLK_DDR1
M_CLK_DDR0
M_CLK_DDR#1
DDR_CKE4_DIMM1
DDR_CKE5_DIMM1
M_CLK_DDR#4
M_CLK_DDR5
M_CLK_DDR4
M_CLK_DDR#5
DDR_CS1_DIMM2#
DDR_CS0_DIMM2#
M_ODT1
M_ODT0
DDR_A_BS1
DDR_A_BS2
DDR_A_BS0
DDR_CS5_DIMM1#
DDR_CS4_DIMM1#
M_ODT5
M_ODT4
DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
DDR_A_MA0
DDR_A_MA1
DDR_A_MA3
DDR_A_MA7
DDR_A_MA8
DDR_A_MA13
DDR_A_MA2
DDR_A_MA14
DDR_A_MA5
DDR_A_MA10
DDR_A_MA4
DDR_A_MA11
DDR_A_MA9
DDR_A_MA6
DDR_A_MA12
DDR_A_MA15
DDR_A_DQS#5
DDR_A_DQS#2
DDR_A_DQS#7
DDR_A_DQS#1
DDR_A_DQS#0
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#6
DDR_A_DQS7
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS5
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS0
DDR_A_DQS6
DDR_B_D29
DDR_B_D59
DDR_B_D50
DDR_B_D49
DDR_B_D13
DDR_B_D11
DDR_B_D19
DDR_B_D14
DDR_B_D3
DDR_B_D55
DDR_B_D47
DDR_B_D52
DDR_B_D44
DDR_B_D41
DDR_B_D8
DDR_B_D5
DDR_B_D56
DDR_B_D48
DDR_B_D38
DDR_B_D35
DDR_B_D26
DDR_B_D25
DDR_B_D4
DDR_B_D63
DDR_B_D34
DDR_B_D32
DDR_B_D10
DDR_B_D17
DDR_B_D51
DDR_B_D40
DDR_B_D36
DDR_B_D31
DDR_B_D21
DDR_B_D20
DDR_B_D15
DDR_B_D7
DDR_B_D62
DDR_B_D46
DDR_B_D42
DDR_B_D18
DDR_B_D12
DDR_B_D1
DDR_B_D53
DDR_B_D37
DDR_B_D22
DDR_B_D57
DDR_B_D27
DDR_B_D54
DDR_B_D45
DDR_B_D39
DDR_B_D30
DDR_B_D9
DDR_B_D60
DDR_B_D58
DDR_B_D33
DDR_B_D0
DDR_B_D61
DDR_B_D43
DDR_B_D28
DDR_B_D23
DDR_B_D24
DDR_B_D16
DDR_B_D6
DDR_B_D2
DDR_CKE6_DIMM3
DDR_CKE7_DIMM3
M_CLK_DDR7
M_CLK_DDR#7
M_CLK_DDR#6
M_CLK_DDR6
DDR_CKE2_DIMM4
DDR_CKE3_DIMM4
DDR_CS2_DIMM4#
DDR_CS3_DIMM4#
DDR_CS6_DIMM3#
DDR_CS7_DIMM3#
M_CLK_DDR3
M_CLK_DDR#3
M_CLK_DDR#2
M_CLK_DDR2
DDR_B_BS2
DDR_B_BS1
DDR_B_BS0
M_ODT2
M_ODT3
M_ODT6
M_ODT7
DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
DDR_B_MA10
DDR_B_MA9
DDR_B_MA14
DDR_B_MA5
DDR_B_MA13
DDR_B_MA11
DDR_B_MA7
DDR_B_MA2
DDR_B_MA0
DDR_B_MA6
DDR_B_MA1
DDR_B_MA12
DDR_B_MA4
DDR_B_MA8
DDR_B_MA3
DDR_B_MA15
DDR_B_DQS#3
DDR_B_DQS#6
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#0
DDR_B_DQS#5
DDR_B_DQS#4
DDR_B_DQS#7
DDR_B_DQS3
DDR_B_DQS2
DDR_B_DQS7
DDR_B_DQS4
DDR_B_DQS1
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS0
+SM_VREF
+SA_DIMM_VREFDQ
+SB_DIMM_VREFDQ
DDR_A_D[0..63]<13,14>
DDR_CKE0_DIMM2 <14>
DDR_CKE1_DIMM2 <14>
M_CLK_DDR0 <14>
M_CLK_DDR#0 <14>
M_CLK_DDR1 <14>
M_CLK_DDR#1 <14>
DDR_CKE4_DIMM1 <13>
DDR_CKE5_DIMM1 <13>
M_CLK_DDR4 <13>
M_CLK_DDR#4 <13>
M_CLK_DDR5 <13>
M_CLK_DDR#5 <13>
DDR_A_BS0 <13,14>
DDR_A_BS1 <13,14>
DDR_A_BS2 <13,14>
DDR_CS0_DIMM2# <14>
DDR_CS1_DIMM2# <14>
M_ODT0 <14>
M_ODT1 <14>
DDR_CS4_DIMM1# <13>
DDR_CS5_DIMM1# <13>
M_ODT4 <13>
M_ODT5 <13>
DDR_A_CAS# <13,14>
DDR_A_WE# <13,14>
DDR_A_RAS# <13,14>
DDR_A_MA[0..15] <13,14>
DDR_A_DQS#[0..7] <13,14>
DDR_A_DQS[0..7] <13,14>
DDR_B_D[0..63]<15,16>
DDR_CS3_DIMM4# <16>
DDR_CS2_DIMM4# <16>
DDR_CKE3_DIMM4 <16>
DDR_CKE2_DIMM4 <16>
M_CLK_DDR#2 <16>
M_CLK_DDR2 <16>
M_CLK_DDR#3 <16>
M_CLK_DDR3 <16>
DDR_CKE7_DIMM3 <15>
DDR_CKE6_DIMM3 <15>
M_CLK_DDR#6 <15>
M_CLK_DDR6 <15>
M_CLK_DDR#7 <15>
M_CLK_DDR7 <15>
DDR_CS7_DIMM3# <15>
DDR_CS6_DIMM3# <15>
M_ODT3 <16>
M_ODT2 <16>
DDR_B_BS2 <15,16>
DDR_B_BS1 <15,16>
DDR_B_BS0 <15,16>
M_ODT7 <15>
M_ODT6 <15>
DDR_B_CAS# <15,16>
DDR_B_WE# <15,16>
DDR_B_RAS# <15,16>
DDR_B_MA[0..15] <15,16>
DDR_B_DQS#[0..7] <15,16>
DDR_B_DQS[0..7] <15,16>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Broadwell (3/7)
8 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Broadwell (3/7)
8 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Broadwell (3/7)
8 67Monday, January 13, 2014
Compal Electronics, Inc.
T60 PAD~D@T60 PAD~D@T64 PAD~D@T64 PAD~D@
HASWELL_BGA
3 OF 12
CPU1C
HASWELL_BGA1364
HASWELL_BGA
3 OF 12
CPU1C
HASWELL_BGA1364
SA_BS0 BC20
SA_ODT3 BD17
SA_BS1 BD21
SA_WE BF21
SA_ODT2 BF17
SA_CS#3 BD16
SA_CS#2 BE17
SA_CS#1 BC17
SA_CS#0 BE16
SA_CKE3 BD34
SA_CKE1 BF34
SA_CKN1 BD25
SA_DQ6
AK52
SA_DQ7
AK53
SA_DQ8
AN54
SA_DQ9
AN52
SA_DQ10
AR51
SA_DQ12
AN53 SA_DQ11
AR53
SA_DQ13
AN51
SA_DQ15
AR54 SA_DQ14
AR52
SA_DQ16
AV52
SA_DQ17
AV53
SA_DQ18
AY52
SA_DQ20
AV51 SA_DQ19
AY51
SA_DQ21
AV54
SA_DQ22
AY54
SA_DQ23
AY53
SA_DQ25
AY49 SA_DQ24
AY47
SA_DQ26
BA47
SA_DQ27
BA45
SA_DQ28
AY45
SA_DQ30
BA49 SA_DQ29
AY43
SA_DQ31
BA43
SA_DQ32
BF14
SA_DQ33
BC14
SA_DQ35
BF11 SA_DQ34
BC11
SA_DQ38
BD11 SA_DQ37
BD14 SA_DQ36
BE14
SA_DQ39
BE11
SA_DQ40
BC9
SA_DQ41
BE9
SA_DQ42
BE6
SA_DQ44
BD9
SA_DQ49
BC2
SA_DQ50
AW3
SA_DQ51
AW2
SA_DQ53
BB2 SA_DQ52
BB3
SA_DQ54
AW4
SA_DQ55
AW1
SA_DQ56
AU3
SA_DQ57
AU1
SA_DQ58
AR1
SA_DQ59
AR4
SA_DQ61
AU4 SA_DQ60
AU2
SA_DQ63
AR3 SA_DQ62
AR2
SA_DIMM_VREFDQ
AR6 SM_VREF
AM6
SB_DIMM_VREFDQ
AN6
RSVD
BC53
SA_CK1 BC25
SA_CKE0 BE34
SA_CKE2 BC34
SA_ODT0 BC16
SA_MA2 BF28
SA_MA1 BD27
SA_MA0 BD28
SA_MA3 BE28
SA_MA4 BF32
SA_MA5 BC27
SA_MA6 BF27
SA_MA7 BC28
SA_MA9 BC32
SA_MA8 BE27
SA_MA10 BD20
SA_MA12 BC31
SA_MA11 BF31
SA_MA14 BE32
SA_MA13 BE20
SA_DQSN3 AY46
SA_DQSN2 AW52
SA_DQSN5 BE7
SA_DQSN7 AT2
SA_DQS0 AJ53
SA_ODT1 BF16
SA_DQ48
BB4 SA_DQ47
BD6 SA_DQ46
BE5 SA_DQ45
BF9
SA_DQ43
BC6
SA_CK2 BF23
SA_CKN2 BE23
SA_CKN3 BD23
SA_CK3 BC23
SA_CK0 BF25
SA_CKN0 BE25
RSVD BD31
SA_BS2 BD32
VSS BC21
SA_RAS BF20
SA_CAS BE21
SA_DQ0
AH54
SA_DQ1
AH52
SA_DQ2
AK51
SA_DQ3
AK54
SA_DQ4
AH53
SA_DQ5
AH51
SA_MA15 BE31
SA_DQSN0 AJ52
SA_DQSN1 AP53
SA_DQSN4 BD12
SA_DQSN6 BA3
SA_DQS1 AP52
SA_DQS2 AW53
SA_DQS3 BA46
SA_DQS4 BE12
SA_DQS5 BD7
SA_DQS6 BA2
SA_DQS7 AT3
RSVD BA40
RSVD AY40
RSVD BA39
RSVD AY39
RSVD AV40
RSVD AU40
RSVD AV39
RSVD AU39
RSVD AW40
RSVD AW39
HASWELL_BGA
4 OF 12
CPU1D
HASWELL_BGA1364
HASWELL_BGA
4 OF 12
CPU1D
HASWELL_BGA1364
SB_CS#1 AY19
SB_CS#2 AU19
SB_CS#3 AW20
SB_ODT0 AY20
SB_ODT1 BA19
SB_ODT2 AV19
SB_ODT3 AW19
SB_CS#0 BA20
SB_DQS3 BE43
SB_DQS4 AW15
SB_DQS2 BE48
SB_DQSN5 AW10
SB_MA5 AY32
SB_MA3 AV30
SB_MA1 AW30
SB_WE AW23
SB_CK1 AV26
SB_CKE0 AU36
SB_CK0 AV27
SB_CKN0 AW27
RSVD AY36
SB_DQ62
AK2
SB_DQ63
AK3
SB_DQ60
AM1
SB_DQ61
AM4
SB_DQ59
AK4
SB_DQ57
AM3
SB_DQ58
AK1
SB_DQ56
AM2 SB_DQ55
AY6 SB_DQ54
AU6
SB_DQ52
AV8
SB_DQ53
AY8
SB_DQ51
BA6 SB_DQ50
AV6 SB_DQ49
BA8 SB_DQ48
AU8 SB_DQ47
AV10 SB_DQ46
AY10 SB_DQ45
BA12 SB_DQ44
AV12
SB_DQ42
BA10
SB_DQ43
AU10
SB_DQ41
AY12 SB_DQ40
AU12 SB_DQ39
AU15 SB_DQ38
AY15 SB_DQ37
AV16 SB_DQ36
AY16
SB_DQ34
BA15
SB_DQ35
AV15
SB_DQ33
AU16 SB_DQ32
BA16 SB_DQ31
BE42
SB_DQ29
BC44
SB_DQ30
BD42
SB_DQ28
BF44
SB_DQ26
BC42
SB_DQ27
BF42
SB_DQ24
BE44
SB_DQ25
BD44
SB_DQ23
BF47 SB_DQ22
BE47 SB_DQ21
BD50
SB_DQ19
BC47
SB_DQ20
BD49
SB_DQ18
BD47 SB_DQ17
BE49 SB_DQ16
BC49 SB_DQ15
AV49 SB_DQ14
AV47 SB_DQ13
AU45
SB_DQ11
AV45
SB_DQ12
AU43
SB_DQ10
AV43 SB_DQ9
AU49 SB_DQ8
AU47 SB_DQ7
AE53 SB_DQ6
AE52 SB_DQ5
AC51 SB_DQ4
AC53 SB_DQ3
AE54 SB_DQ2
AE51 SB_DQ1
AC52
SB_DQSN7 AL2
SB_DQSN6 AW8
SB_DQSN0 AD52
SB_MA15 BA35
SB_MA14 AW36
SB_MA13 AU20
SB_MA12 AW35
SB_MA10 AU23
SB_MA9 AU32
SB_MA8 BA32
SB_MA7 AV32
SB_MA6 AT30
SB_MA4 AW32
SB_MA2 AY30
SB_MA0 BA30
SB_CAS AV20
SB_BS1 BA23
SB_CK3 AY27
SB_CKN3 BA27
SB_CKE2 AV35
SB_CK2 AY26
SB_CKN2 BA26
SB_CKE1 AU35
SB_CKN1 AW26
SB_BS2 BA36
VSS AU30
SB_DQSN4 AW16
SB_DQSN3 BD43
SB_DQSN2 BD48
SB_DQSN1 AU46
SB_DQS1 AV46
SB_DQS0 AD53
RSVD BE38
RSVD BD39
SB_MA11 AY35
SB_CKE3 AV36
SB_DQ0
AC54
SB_BS0 AY23
SB_RAS AV23
RSVD BD37
RSVD BC37
SB_DQS5 AW12
SB_DQS6 AW6
SB_DQS7 AL3
RSVD BD38
RSVD BE37
RSVD BC39
RSVD BF37
RSVD BE39
RSVD BF39
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
CAD Note:Trace width=20 mils ,Spacing=25mil,
Max length=100 mils.
COMPENSATION PU FOR eDP
HPD INVERSION FOR EDP
EDP_COMP
EDP_HPD#
DPD_CPU_LANE_P1
DPD_CPU_LANE_N0
DPD_CPU_LANE_P0
DPD_CPU_LANE_N1
DPD_CPU_LANE_N3
DPD_CPU_LANE_P3
DPD_CPU_LANE_N2
DPD_CPU_LANE_P2
EDP_COMP
EDP_HPD#
CPU_EDP_AUX
CPU_EDP_AUX#
CPU_EDP_LANE_N0
CPU_EDP_LANE_N1
CPU_EDP_LANE_P0
CPU_EDP_LANE_P1
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
+VCOMP_OUT
+VCCIO_OUT
CPU_EDP_HPD<29>
DPD_CPU_LANE_N0<36>
DPD_CPU_LANE_P0<36>
DPD_CPU_LANE_N1<36>
DPD_CPU_LANE_P1<36>
DPD_CPU_LANE_N2<36>
DPD_CPU_LANE_P2<36>
DPD_CPU_LANE_N3<36>
DPD_CPU_LANE_P3<36>
CPU_EDP_AUX <29>
CPU_EDP_AUX# <29>
CPU_EDP_LANE_N0 <29>
CPU_EDP_LANE_N1 <29>
CPU_EDP_LANE_P0 <29>
CPU_EDP_LANE_P1 <29>
FDI_CTX_PRX_N1 <19>
FDI_CTX_PRX_N0 <19>
FDI_CTX_PRX_P1 <19>
FDI_CTX_PRX_P0 <19>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Broadwell (4/7)
9 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Broadwell (4/7)
9 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Broadwell (4/7)
9 67Monday, January 13, 2014
Compal Electronics, Inc.
RC75
100K_0402_5%
RC75
100K_0402_5%
12
HASWELL_BGA
10 OF 12
CPU1J
HASWELL_BGA1364
HASWELL_BGA
10 OF 12
CPU1J
HASWELL_BGA1364
EDP_DISP_UTIL E12
DDIB_TXN3
A24
DDIB_TXP3
B24
DDIC_TXN0
C21
DDIC_TXN1
A21
EDP_HPD E14
EDP_AUXP F14
EDP_TXN0 C14
EDP_TXP1 B12
EDP_TXN1 A12
EDP_TXP0 D14
EDP_RCOMP AG6
FDI_TXN0 C12
FDI_TXP0 D12
FDI_TXN1 A14
FDI_TXP1 B14
DDIB_TXN0
C25
DDIB_TXP0
D25
DDIB_TXN1
A25
DDIB_TXN2
C24 DDIB_TXP1
B25
DDIB_TXP2
D24
DDIC_TXP0
D21
DDIC_TXP1
B21
DDIC_TXN2
C20
DDIC_TXP2
D20
DDIC_TXN3
A20
DDIC_TXP3
B20
DDID_TXN2
C16
DDID_TXP2
D16
DDID_TXN3
A16
DDID_TXP3
B16
DDID_TXN0
C17
DDID_TXP0
D17
DDID_TXN1
A17
DDID_TXP1
B17
EDP_AUXN F15
T69PAD~D @T69PAD~D @
RC124.9_0402_1% RC124.9_0402_1%
12
G
D
S
QC6
LBSS138LT1G_SOT-23-3
G
D
S
QC6
LBSS138LT1G_SOT-23-3
2
13
RC65
10K_0402_5%
RC65
10K_0402_5%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
PEG Static Lane Reversal - CFG2 is for the 16x
CFG2
1:(Default) Normal Operation; Lane #
definition matches socket pin map definition
0:Lane Reversed
CFG4
1 : Disabled; No Physical Display Port
attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
Display Port Presence Strap
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled
CFG[6:5]
PCIE Port Bifurcation Straps
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
1: (Default) PEG Train immediately
following xxRESETB de assertion
CFG7
PEG DEFER TRAINING
0: PEG Wait for BIOS for training
CFG STRAPS for CPU
CFG7
CFG_RCOMP
H_CPU_RSVD
H_CPU_TESTLO
CFG4
CFG6
CFG5
CFG2
CFG_RCOMP
H_CPU_TESTLO
H_CPU_RSVD
CFG10
CFG11
CFG14
CFG15
CFG1
CFG2
CFG0
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG12
CFG13
CFG17
CFG19
CFG16
CFG18
BE54_BD54
BE2_BF2
BE3_BF3
C3_B2
C1_C2
C1_C2
B3_A3
BE1_BD1
A52_B52
B54_C54
A52_B52
BE54_BD54
BE1_BD1
BE2_BF2
B3_A3
A53_B53
A53_B53
BE3_BF3
BE52_BF52
BE53_BF53
BE53_BF53
BE52_BF52
C3_B2
B54_C54
+VCC_CORE
CFG3<7>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Broadwell (5/7)
10 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Broadwell (5/7)
10 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Broadwell (5/7)
10 67Monday, January 13, 2014
Compal Electronics, Inc.
T138PAD~D @T138PAD~D @
RC58 49.9_0402_1%RC58 49.9_0402_1%
12
HASWELL_BGA
11 OF 12
CPU1K
HASWELL_BGA1364
HASWELL_BGA
11 OF 12
CPU1K
HASWELL_BGA1364
RSVD_TP F1
RSVD_TP G12
RSVD_TP G10
VSS H54
VSS H53
RSVD_TP
BE4
RSVD_TP
BD3
RSVD_TP
G24
CFG0
AG49
CFG15
R52 CFG14
R53 CFG13
V54 CFG12
U53 CFG11
W53 CFG10
Y53 CFG9
Y54 CFG8
Y49 CFG7
W51 CFG6
V51 CFG5
AB49 CFG4
Y50 CFG3
AE49 CFG2
AC49 CFG1
AD49
RSVD
L49
RSVD
E5
RSVD
L50
RSVD F8
RSVD AL6
RSVD AU26
RSVD BD4
RSVD BC4
RSVD AM48
RSVD AU27
RSVD B50
RSVD AH49
CFG19 V52
CFG17 Y51
CFG18 V53
CFG_RCOMP R54
CFG16 Y52
RSVD_TP A6
RSVD_TP A5
RSVD_TP E1
RSVD_TP
L51
RSVD_TP
F24
RSVD_TP
F25
RSVD H50
RSVD G53
RSVD N51
VSS H51
VSS H52
VSS
G19
VSS
F51
RSVD_TP
G21
RSVD_TP
G6 RSVD_TP
F6
RSVD F16
RSVD_TP
L53 RSVD_TP
L52
VCC
F22 VSS
F52
TESTLOW_F20
F20
TESTLOW_F21
F21
T93PAD~D @T93PAD~D @
T128PAD~D@T128PAD~D@
T101PAD~D @T101PAD~D @
T76 PAD~D@T76 PAD~D@
T137PAD~D @T137PAD~D @
T90 PAD~D@T90 PAD~D@
T89PAD~D @T89PAD~D @
T127PAD~D@T127PAD~D@
T94PAD~D @T94PAD~D @
RC77
1K_0402_1%
RC77
1K_0402_1%
12
T180PAD~D@T180PAD~D@
T139PAD~D @T139PAD~D @
T103PAD~D@T103PAD~D@
T78PAD~D @T78PAD~D @
T135PAD~D@T135PAD~D@
T70 PAD~D@T70 PAD~D@
T86PAD~D @T86PAD~D @
T140PAD~D @T140PAD~D @
T97PAD~D @T97PAD~D @
RC86
1K_0402_1%
@RC86
1K_0402_1%
@
12
T71 PAD~D@T71 PAD~D@
T166PAD~D@T166PAD~D@
T72 PAD~D@T72 PAD~D@
T105PAD~D@T105PAD~D@
T99PAD~D @T99PAD~D @
T106PAD~D@T106PAD~D@
T88PAD~D @T88PAD~D @
T79PAD~D @T79PAD~D @
RC83
1K_0402_1%
@RC83
1K_0402_1%
@
12
T102PAD~D @T102PAD~D @
T87PAD~D @T87PAD~D @
T107PAD~D@T107PAD~D@
T81 PAD~D@T81 PAD~D@
T114PAD~D @
T114PAD~D @
T179PAD~D@T179PAD~D@
RC76
1K_0402_1%
@
RC76
1K_0402_1%
@
12
RC59 49.9_0402_1%RC59 49.9_0402_1%
12
RC45 49.9_0402_1%RC45 49.9_0402_1%
12
T108PAD~D@T108PAD~D@
T82 PAD~D@T82 PAD~D@
T100PAD~D @T100PAD~D @
T84 PAD~D@T84 PAD~D@
T73 PAD~D@T73 PAD~D@
T109PAD~D@T109PAD~D@
T95PAD~D @T95PAD~D @
T83 PAD~D@T83 PAD~D@
T74 PAD~D@T74 PAD~D@
T91PAD~D @T91PAD~D @
T111PAD~D@T111PAD~D@
T177PAD~D@T177PAD~D@
T136PAD~D @T136PAD~D @
T164PAD~D @
T164PAD~D @
T104PAD~D@T104PAD~D@
HASWELL_BGA
12 OF 12
CPU1L
HASWELL_BGA1364
HASWELL_BGA
12 OF 12
CPU1L
HASWELL_BGA1364
RSVD BF51
RSVD BF52
RSVD BF53
RSVD C1
RSVD C2
RSVD C3
RSVD D1
RSVD C54
RSVD D54
RSVD AN35
RSVD AN37
RSVD AF9
RSVD AE9
RSVD G14
RSVD G17
RSVD AD45
RSVD AG45
RSVD
A4 RSVD
A3
RSVD
A53
RSVD
A51
RSVD
A52
RSVD
B2
RSVD
B52
RSVD
B53
RSVD
B3
RSVD
B54
RSVD
BC1
RSVD
BC54
RSVD
BD1
RSVD
BE1 RSVD
BD54
RSVD
BE2
RSVD
BE52 RSVD
BE3
RSVD
BE54 RSVD
BE53
RSVD
BF2
RSVD
BF4 RSVD
BF3
T80 PAD~D@T80 PAD~D@
T116PAD~D@T116PAD~D@
T117PAD~D@T117PAD~D@
T98PAD~D @T98PAD~D @
T92 PAD~D@T92 PAD~D@
T85 PAD~D@T85 PAD~D@
T178PAD~D@T178PAD~D@
T161PAD~D @
T161PAD~D @
T119PAD~D@T119PAD~D@
T96PAD~D @T96PAD~D @
RC85
1K_0402_1%
@RC85
1K_0402_1%
@
12
T75 PAD~D@T75 PAD~D@
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
CAD Note: Place the PU resistors close to CPU
RC63 close to CPU 300 - 1500mils
RESISTOR STUFFING OPTIONS ARE
PROVIDED FOR TESTING PURPOSES
VDDQ DECOUPLING
SVID ALERT
SVID DATA
VCC_SENSE
CAD Note: RC68 SHOULD BE PLACED CLOSE TO CPU
CAD Note: Place the PU resistors close to CPU
RC60 close to CPU 300 - 1500mils
CAD Note: RC67 SHOULD BE PLACED CLOSE TO CPU
55A
Difference with Diesel
Difference with Diesel (follow HSW-BGA CRB Rev 0.7)
HSW_BDW
compatibility CKT
HSW_BDW compatibility CKT
HSW_BDW
compatibility CKT
RC105 X
HSW BDW
V
V
CC137 X
CC173 X
V
HSW_BDW compatibility CKT
RC72
RC73
V
V
X
X
place CC173 close to CPU
VSSSENSE
CPU_PWR_DEBUG
VSSSENSE_R
VIDSOUT
VCCSENSE VCCSENSE_R
H_CPU_SVIDALRT#
FC_D3
IVR_ERROR
IST_TRIGGER
CPU_PWR_DEBUG
VIDSOUT
VIDSCLK
H_CPU_SVIDALRT#
VCCSENSE_R
RESET_OUT#
FC_D3
+1.05V_RUN
+VCCIO_OUT
+VCCIO_OUT
+1.05V_RUN
+VCC_CORE
+VCCIO_OUT
+1.35V_MEM
+1.05V_RUN +VCCIO2PCH
+VCC_CORE +VCC_CORE
+VCC_CORE
+1.35V_MEM
+VCC_CORE
+VCOMP_OUT
+VCCIO_OUT
+VCC_CORE
+VCCIO2PCH
+VCCIO2PCH
VIDALERT_N<61>
VIDSOUT<61>
VCCSENSE<61>
VSSSENSE<61> VSSSENSE_R <12>
VIDSCLK<61>
RESET_OUT# <18,19,51,7>
CPU_PWR_DEBUG<7>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Broadwell (6/7)
11 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Broadwell (6/7)
11 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Broadwell (6/7)
11 67Monday, January 13, 2014
Compal Electronics, Inc.
HASWELL_BGA
5 OF 12
CPU1E
HASWELL_BGA1364
HASWELL_BGA
5 OF 12
CPU1E
HASWELL_BGA1364
VDDQ
BB30
VDDQ
BB31
VCC F46
VCC F45
VCC F43
VDDQ
BE22
VDDQ
BD30
RSVD
J17
RSVD
J21
VDDQ
BE18
VDDQ
BD22
VDDQ
AW29
VDDQ
BD26
VDDQ
BD33
VCC
AA9 VCC
AA8 VCC
AA47 VCC
AA46 VCC
A48 VCC
A46 VCC
A45 VCC
A43 VCC
A42 VCC
A39 VCC
A38 VCC
A36
VSS
AD50
VSS
AM50
VSS
AB50 VSS
AP49
VSS
AK49 VSS
AG50 VSS
AJ49 VSS
AN49 VSS
V50 RSVD_TP
W49 RSVD_TP
AM49 RSVD_TP
U49 RSVD_TP
V49 VSS
E52 PWR_DEBUG
F19 VSS
B51
VIDSOUT
J50 VIDSCLK
J52 VIDALERT
J53
RSVD
AR49 RSVD
J12 RSVD
W9 RSVD
AN33 VCOMP_OUT
AK6 RSVD
F17 VCCIO_OUT
D51 RSVD
AH9 VCC_SENSE
C50
RSVD
AN18 RSVD
AN22 VCC
M6 VCC
L6 RSVD
AN31
VDDQ
BE33 VDDQ
BE30 VDDQ
BE26
VDDQ
BB36 VDDQ
BB34
VDDQ
BB27 VDDQ
BB26 VDDQ
BB22 VDDQ
BB21 VDDQ
AY18 VDDQ
AW33
VDDQ
AW25 VDDQ
AW22 VDDQ
AV37 VDDQ
AT36 VDDQ
AT32 VDDQ
AT27 VDDQ
AT23 VDDQ
AT19 VDDQ
AT13 VDDQ
AR33 VDDQ
AR31 VDDQ
AR29
RSVD
J31 RSVD
J26
VCC H29
VCC H27
VCC H26
VCC H20
VCC H19
VCC H18
VCC H17
VCC H16
VCC H14
VCC H13
VCC H12
VCC H11
VCC G48
VCC G46
VCC G45
VCC G43
VCC G42
VCC G39
VCC G38
VCC G36
VCC G31
VCC G34
VCC G32
VCC G27
VCC G29
VCC F48
VCC F42
VCC F39
VCC F38
VCC F36
VCC F34
VCC F32
VCC F31
VCC F28
VCC F27
VCC E48
VCC E46
VCC E45
VCC E43
VCC E42
VCC E39
VCC E38
VCC E36
VCC E34
VCC E32
VCC E31
VCC E28
VCC E27
VCC D48
VCC D46
VCC D45
VCC D43
VCC D42
VCC D39
VCC D38
VCC D36
VCC D34
VCC D32
VCC D31
VCC D28
VCC D27
VCC C48
VCC C46
VCC C45
VCC C43
VCC C42
VCC C28
VCC C27
VCC B48
VCC B46
VCC B45
VCC B43
VCC H21
VCC H23
VCC H24
VCC H25
FC_D5 D5
FC_D3 D3
VSS
AJ50
VSS
AP50
VCC C31
VCC C32
VCC C34
VCC C36
VCC C38
VCC C39
CC161
10U_0603_6.3V6M~D
@CC161
10U_0603_6.3V6M~D
@
1
2
CC83
1U_0402_6.3V6K~D
@CC83
1U_0402_6.3V6K~D
@
1
2
T160 PAD~D@T160 PAD~D@
CC84
1U_0402_6.3V6K~D
CC84
1U_0402_6.3V6K~D
1
2
CC164
10U_0603_6.3V6M~D
@CC164
10U_0603_6.3V6M~D
@
1
2
T154 PAD~D@T154 PAD~D@
RC63
130_0402_1%
RC63
130_0402_1%
12
RC68 0_0402_5%@RC68 0_0402_5%@
12
CC85
1U_0402_6.3V6K~D
CC85
1U_0402_6.3V6K~D
1
2
CC168
10U_0603_6.3V6M~D
@CC168
10U_0603_6.3V6M~D
@
1
2
T153 PAD~D@T153 PAD~D@
CC86
1U_0402_6.3V6K~D
@CC86
1U_0402_6.3V6K~D
@
1
2
CC163
10U_0603_6.3V6M~D
CC163
10U_0603_6.3V6M~D
1
2
T113 PAD~D@T113 PAD~D@
CC87
1U_0402_6.3V6K~D
CC87
1U_0402_6.3V6K~D
1
2
+
CC172
330U_D2_2VM_R6M
+
CC172
330U_D2_2VM_R6M
1
2
CC166
10U_0603_6.3V6M~D
@CC166
10U_0603_6.3V6M~D
@
1
2
T110 PAD~D@T110 PAD~D@
CC88
1U_0402_6.3V6K~D
@CC88
1U_0402_6.3V6K~D
@
1
2
T112 PAD~D@T112 PAD~D@
T115 PAD~D@T115 PAD~D@
T77 PAD~D@T77 PAD~D@
RC72
2.67K_0402_1%
BDW@
RC72
2.67K_0402_1%
BDW@
12
T152 PAD~D@T152 PAD~D@
T162 PAD~D@T162 PAD~D@
CC137
22U_0805_6.3V6M
BDW@CC137
22U_0805_6.3V6M
BDW@
1
2
T151 PAD~D@T151 PAD~D@
RC73
6.04K_0402_1%
BDW@
RC73
6.04K_0402_1%
BDW@
12
T163 PAD~D@T163 PAD~D@
CC43
1U_0402_6.3V6K~D
@CC43
1U_0402_6.3V6K~D
@
1
2
RC69
150_0402_1%
RC69
150_0402_1%
12
CC171
10U_0603_6.3V6M~D
CC171
10U_0603_6.3V6M~D
1
2
RC71
10K_0402_5%
@
RC71
10K_0402_5%
@
12
T157 PAD~D@T157 PAD~D@
CC80
1U_0402_6.3V6K~D
@CC80
1U_0402_6.3V6K~D
@
1
2
CC165
10U_0603_6.3V6M~D
CC165
10U_0603_6.3V6M~D
1
2
T158 PAD~D@T158 PAD~D@
CC81
1U_0402_6.3V6K~D
@CC81
1U_0402_6.3V6K~D
@
1
2
HASWELL_BGA
6 OF 12
CPU1F
HASWELL_BGA1364
HASWELL_BGA
6 OF 12
CPU1F
HASWELL_BGA1364
VCC H34
VCC H33
VCC H37
VCC H36
VCC H38
VCC H40
VCC H39
VCC H42
VCC H43
VCC H45
VCC H46
VCC H48
VCC H8
VCC H9
VCC J10
VCC J14
VCC J19
VCC J24
VCC J33
VCC J29
VCC J36
VCC J37
VCC J38
VCC J39
VCC J40
VCC J42
VCC J43
VCC J45
VCC J48
VCC J46
VCC J8
VCC J9
VCC K38
VCC K40
VCC K43
VCC K44
VCC K46
VCC K45
VCC K48
VCC K8
VCC K9
VCC L38
VCC L37
VCC L40
VCC L39
VCC L42
VCC L44
VCC L43
VCC L46
VCC L47
VCC L8
VCC M38
VCC M37
VCC M39
VCC M40
VCC M42
VCC M43
VCC M44
VCC M45
VCC M8
VCC M46
VCC M9
VCC N37
VCC N38
VCC N39
VCC N40
VCC N42
VCC N43
VCC N44
VCC N47
VCC N46
VCC N8
VCC N9
VCC P45
VCC P46
VCC P8
VCC R46
VCC R8
VCC R47
VCC R9
VCC T45
VCC T46
VCC U47
VCC U46
VCC U8
VCC U9
VCC V45
VCC V8
VCC V46
VCC W46
VCC W47
VCC W8
VCC Y46
VCC Y45
VCC A27
VCC Y8
VCC A28
VCC A31
VCC A32
VCC A34
VCC B28
VCC B27
VCC B31
VCC B32
VCC B34
VCC B38
VCC B36
VCC B39
VCC B42
VCC
AB46
VCC
AB8
VCC
AC47
VCC
AC9 VCC
AC8
VCC
AD46
VCC
AD8
VCC
AE46
VCC
AE47
VCC
AE8
VCC
AF8
VCC
AG46
VCC
AG8
VCC
AH46
VCC
AH47
VCC
AH8
VCC
AJ46 VCC
AJ45
VCC
AK46
VCC
AK47
VCC
AK8
VCC
AL45
VCC
AL46
VCC
AL8
VCC
AL9
VCC
AM46
VCC
AM8 VCC
AM47
VCC
AM9
VCC
AN10
VCC
AN12
VCC
AN13
VCC
AN14
VCC
AN15
VCC
AN17 VCC
AN16
VCC
AN19
VCC
AN20
VCC
AN21
VCC
AN24 VCC
AN23
VCC
AN26 VCC
AN25
VCC
AN27
VCC
AN30 VCC
AN29
VCC
AN32
VCC
AN34
VCC
AN36
VCC
AN39 VCC
AN38
VCC
AN40
VCC
AN41
VCC
AN42
VCC
AN43
VCC
AN44
VCC
AN45
VCC
AN8 VCC
AN46
VCC
AN9
VCC
AP10
VCC
AP12
VCC
AP13
VCC
AP14
VCC
AP15
VCC
AP16
VCC
AP17
VCC
AP19 VCC
AP18
VCC
AP20
VCC
AP21
VCC
AP22
VCC
AP23
VCC
AP24
VCC
AP25
VCC
AP27 VCC
AP26
VCC
AP29
VCC
AP30
VCC
AP31
VCC
AP33 VCC
AP32
VCC
AP34
VCC
AP35
VCC
AP36
VCC
AP38 VCC
AP37
VCC
AP39
VCC
AP40
VCC
AP41
VCC
AP43 VCC
AP42
VCC
AP46 VCC
AP44
VCC
AP47
VCC
AP8
VCC
AP9
VCC
AR35
VCC
AR39 VCC
AR37
VCC
AR41
VCC
AR43
VCC
AR45
VCC
H30 VCC
AR46
VCC
H31
VCC
H32
VCC
AC46
VCC
AB45
RC105 0_0603_5%BDW@RC105 0_0603_5%BDW@
12
RC66
100_0402_1%
RC66
100_0402_1%
12
CC170
10U_0603_6.3V6M~D
@CC170
10U_0603_6.3V6M~D
@
1
2
RC6143_0402_5% RC6143_0402_5%
12
RC67 0_0402_5%@RC67 0_0402_5%@
12
CC82
1U_0402_6.3V6K~D
@CC82
1U_0402_6.3V6K~D
@
1
2
CC173
0.1U_0402_10V7K
BDW@CC173
0.1U_0402_10V7K
BDW@
1
2
RC60
75_0402_1%
RC60
75_0402_1%
12
T159 PAD~D@T159 PAD~D@
RC70
100_0402_1%
RC70
100_0402_1%
12
RC4 0_0603_5%@RC4 0_0603_5%@
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
VSSSENSE_R <11>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Broadwell (7/7)
12 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Broadwell (7/7)
12 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Broadwell (7/7)
12 67Monday, January 13, 2014
Compal Electronics, Inc.
HASWELL_BGA
9 OF 12
CPU1I
HASWELL_BGA1364
HASWELL_BGA
9 OF 12
CPU1I
HASWELL_BGA1364
VSS G20
VSS G23
VSS G25
VSS G40
VSS G30
VSS G26
VSS G33
VSS G37
VSS G7
VSS G44
VSS G49
VSS G52
VSS G54
VSS G8
VSS H7
VSS G9
VSS H44
VSS H49
VSS J44
VSS K1
VSS J7
VSS J49
VSS J51
VSS J54
VSS K6
VSS K5
VSS K2
VSS K3
VSS K4
VSS M48
VSS L9
VSS K7
VSS L48
VSS L7
VSS N48
VSS M7
VSS M50
VSS M52
VSS M54
VSS P4
VSS P3
VSS N7
VSS P1
VSS P2
VSS P54
VSS P5
VSS P48
VSS P50
VSS P52
VSS T48
VSS P6
VSS P7
VSS R48
VSS R7
VSS U1
VSS U48
VSS U2
VSS U3
VSS U4
VSS U5
VSS U6
VSS U50
VSS U52
VSS U54
VSS U7
VSS W50
VSS W48
VSS V48
VSS V7
VSS V9
VSS Y7
VSS Y48
VSS W52
VSS W54
VSS W7
VSS Y9
VSS AR22
VSS AB48
VSS P9
VSS G18
VSS_NCTF A49
VSS_NCTF A50
VSS_NCTF A8
VSS_NCTF BB54
VSS_NCTF BB1
VSS_NCTF B4
VSS_NCTF BA1
VSS_NCTF BA54
VSS_NCTF BF50
VSS_NCTF BD2
VSS_NCTF BD53
VSS_NCTF BF49
VSS_NCTF BF5
VSS_NCTF F54
VSS_NCTF D2
VSS_NCTF C53
VSS_NCTF BF6
VSS_NCTF E54
VSS_NCTF G1
VSS_SENSE D50
VSS
BC10
VSS
BC12
VSS
BC15
VSS
BC30
VSS
BC18
VSS
BC22
VSS
BC26
VSS
BC3
VSS
BC43
VSS
BC33
VSS
BC36
VSS
BC38
VSS
BC41
VSS
BC46
VSS
BC52
VSS
BC48
VSS
BC5
VSS
BC50
VSS
BC7
VSS
BD41 VSS
BD36
VSS
BD10
VSS
BD15
VSS
BD18
VSS
BE15 VSS
BE10
VSS
BD46
VSS
BD5
VSS
BD51
VSS
BF12 VSS
BF10
VSS
BE36
VSS
BE41
VSS
BE46
VSS
BF30 VSS
BF26
VSS
BF15
VSS
BF18
VSS
BF22
VSS
BF43 VSS
BF41
VSS
BF33
VSS
BF36
VSS
BF38
VSS
C15
VSS
BF48 VSS
BF46
VSS
BF7
VSS
C11
VSS
C33
VSS
C19
VSS
C22
VSS
C26
VSS
C30
VSS
C37
VSS
C49
VSS
C4
VSS
C40
VSS
C44
VSS
C52
VSS
D19
VSS
C8
VSS
D11
VSS
D15
VSS
D22
VSS
D40 VSS
D37
VSS
D26
VSS
D30
VSS
D33
VSS
E15 VSS
E11
VSS
D44
VSS
D49
VSS
D8
VSS
E21 VSS
E20
VSS
E16
VSS
E17
VSS
E19
VSS
E30 VSS
E26
VSS
E22
VSS
E24
VSS
E25
VSS
E49 VSS
E44
VSS
E33
VSS
E37
VSS
E40
VSS
F26
VSS
E51
VSS
E53
VSS
E8
VSS
F2
VSS
F4
VSS
F30 VSS
F3
VSS
F33
VSS
F37
VSS
F40
VSS
G11
VSS
F44
VSS
F49
VSS
F5
VSS
G13
VSS
G16
HASWELL_BGA
7 OF 12
CPU1G
HASWELL_BGA1364
HASWELL_BGA
7 OF 12
CPU1G
HASWELL_BGA1364
VSS AT4
VSS AT39
VSS AT35
VSS AT33
VSS AT26
VSS AT25
VSS AT18
VSS AT10
VSS AT1
VSS AR9
VSS AR8
VSS AR7
VSS AR50
VSS AR5
VSS AR48
VSS AR26
VSS AR24
VSS AR20
VSS AR18
VSS AR16
VSS AR14
VSS AR12
VSS AP7
VSS AP54
VSS AP51
VSS AN7
VSS AN50
VSS AN5
VSS AN48
VSS AN4
VSS AN3
VSS AN2
VSS AN1
VSS AM7
VSS AM54
VSS AM53
VSS AM52
VSS AM51
VSS AM5
VSS AL7
VSS AL5
VSS AL48
VSS AL4
VSS AL1
VSS AK9
VSS AK7
VSS AK50
VSS AK5
VSS AK48
VSS AJ54
VSS AJ51
VSS AJ48
VSS
AH7 VSS
AH50 VSS
AH5 VSS
AH48 VSS
AH4 VSS
AH3 VSS
AH2
VSS
AG7 VSS
AG54 VSS
AG53 VSS
AG52 VSS
AG51 VSS
AG5 VSS
AG48 VSS
AF7 VSS
AF6 VSS
AF5 VSS
AE7 VSS
AE50 VSS
AE5 VSS
AE48 VSS
AE4 VSS
AE3 VSS
AE2 VSS
AE1 VSS
AD9 VSS
AD7 VSS
AD54 VSS
AD51 VSS
AD48 VSS
AC7 VSS
AC50 VSS
AC5 VSS
AC48 VSS
AB9 VSS
AB7 VSS
AB54 VSS
AB53 VSS
AB52 VSS
AB51 VSS
AB5 VSS
AA7 VSS
AA5 VSS
AA48 VSS
AA4 VSS
AA3 VSS
AA2 VSS
AA1 VSS
A44 VSS
A40 VSS
A37 VSS
A33 VSS
A30 VSS
A26 VSS
A22 VSS
A19 VSS
A15 VSS
A11
VSS AT37
VSS AT29
VSS AT22
VSS AT20
VSS AT16
VSS AT12
VSS AT15
VSS
AG9
VSS
AH1
HASWELL_BGA
8 OF 12
CPU1H
HASWELL_BGA1364
HASWELL_BGA
8 OF 12
CPU1H
HASWELL_BGA1364
VSS BB9
VSS BB7
VSS BB6
VSS BB5
VSS BB49
VSS BB48
VSS BB47
VSS BB46
VSS BB44
VSS BB43
VSS BB42
VSS BB39
VSS BB38
VSS BB33
VSS BB32
VSS BB25
VSS BB20
VSS BB14
VSS BB11
VSS BB10
VSS BA53
VSS BA52
VSS BA51
VSS BA50
VSS BA5
VSS BA42
VSS BA4
VSS BA37
VSS BA33
VSS BA29
VSS BA25
VSS BA22
VSS BA18
VSS BA13
VSS B8
VSS B49
VSS B44
VSS B40
VSS B37
VSS B33
VSS B30
VSS B26
VSS B22
VSS B19
VSS B15
VSS B11
VSS AY9
VSS AY50
VSS
AY42 VSS
AY37 VSS
AY33 VSS
AY29 VSS
AY25 VSS
AY22 VSS
AY13 VSS
AW9 VSS
AW54 VSS
AW51 VSS
AW50 VSS
AW5 VSS
AW49 VSS
AW47 VSS
AW46 VSS
AW45 VSS
AW43 VSS
AW42 VSS
AW37 VSS
AW18 VSS
AW13 VSS
AV9 VSS
AV50 VSS
AV5 VSS
AV42 VSS
AV4 VSS
AV33 VSS
AV3 VSS
AV29 VSS
AV25 VSS
AV22 VSS
AV2 VSS
AV18 VSS
AV13 VSS
AV1 VSS
AU9 VSS
AU5 VSS
AU42 VSS
AU37 VSS
AU33 VSS
AU29 VSS
AU25 VSS
AU22 VSS
AU18 VSS
AU13 VSS
AT9 VSS
AT8 VSS
AT6 VSS
AT54 VSS
AT53 VSS
AT52 VSS
AT51 VSS
AT50 VSS
AT5 VSS
AT49 VSS
AT47 VSS
AT46 VSS
AT45 VSS
AT43 VSS
AT42 VSS
AT40
VSS BB41
VSS BB37
VSS BB28
VSS BB23
VSS BB18
VSS BB17
VSS BB16
VSS BB15
VSS BB12
VSS BA9
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Layout Note:
Place near JDIMM1.203,204
All VREF traces should
have 10 mil trace width
0
0
1
DIMM2
1
0
1
DIMM1 0
DIMM4
DIMM3
SA0
1
SA1
Populate RD1, De-Populate RD2 for Intel DDR3
VREFDQ multiple methods M1
Populate RD2, De-Populate RD1 for Intel DDR3
VREFDQ multiple methods M3
DIMM Select
CPU
JDIMM1 JDIMM3
JDIMM2 JDIMM4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
JDIMM1 STD Type H=9.2
*
Top Side
Bottom Side
CD14 change to SGA20331E10
A
D
B
C
DIMM1_SA1
DIMM1_SA0
DDR_A_MA0
DDR_A_MA2
DDR_A_MA14
M_CLK_DDR#5
DDR_A_MA4
DDR_A_MA7
DDR_A_MA6
M_CLK_DDR5
DDR_A_MA11
DDR_A_BS1
DDR_A_RAS#
DDR_A_MA15
M_ODT5
M_ODT4
DDR_A_D0
DDR_A_D4
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_D22
DDR_A_D15
DDR_A_D23
DDR_A_D28
DDR_A_D27
DDR_A_D11
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D54
DDR_A_D50
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_D41
DDR_A_DQS#7
DDR_A_D34
DDR_A_DQS7
DDR_A_D5
DDR_A_D1
DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS#3
DDR_A_DQS3
DDR3_DRAMRST#_R
DDR_A_D29
DDR_A_D18
DDR_A_D19
DDR_A_D31
DDR_A_D14
DDR_A_D10
DDR_A_MA5
DDR_A_MA10
DDR_A_MA1
DDR_A_MA3
DDR_A_MA13
DDR_A_BS0
DDR_A_MA9
DDR_A_MA12
DDR_A_MA8
DDR_A_WE#
DDR_A_BS2
M_CLK_DDR#4
M_CLK_DDR4
DDR_A_CAS#
DIMM1_SA1
DDR_A_D39
DIMM1_SA0
DDR_A_D55
DDR_A_D51
DDR_A_DQS4
DDR_A_DQS6
DDR_A_DQS#4
DDR_A_DQS#6
DDR_A_D7
DDR_A_D6
DDR_A_D9
DDR_A_D8
DDR_A_D2
DDR_A_D3
DDR_A_D13
DDR_A_D12
DDR_A_D20
DDR_A_D21 DDR_A_D17
DDR_A_D16
DDR_A_D24
DDR_A_D26DDR_A_D30
DDR_A_D25
DDR_A_D33
DDR_A_D32
DDR_A_D37
DDR_A_D36
DDR_A_D35
DDR_A_D38
DDR_A_D45 DDR_A_D40
DDR_A_D44
DDR_A_D47
DDR_A_D46
DDR_A_D43
DDR_A_D42
DDR_A_D53
DDR_A_D49 DDR_A_D48
DDR_A_D52
DDR_A_D57
DDR_A_D56
DDR_A_D58
DDR_A_D62
DDR_A_D60
DDR_A_D61
DDR_A_D63
DDR_A_D59
DDR_HVREF_RST_PCH
DDR_HVREF_RST_PCH
+1.35V_MEM
+0.675V_DDR_VTT
+1.35V_MEM
+3.3V_RUN
+1.35V_MEM
+DIMM1_VREF_DQ
+V_DDR_REF
+DIMM1_VREF_CA
+SM_VREF_DIMM
+0.675V_DDR_VTT
+1.35V_MEM
+0.675V_DDR_VTT
+3.3V_RUN
+SA_DIMM1_VREFDQ
+1.35V_MEM
+SA_DIMM1_VREFDQ
+1.35V_MEM
+SM_VREF_DIMM
+SM_VREF_Q
+SA_DIMM_VREFDQ_Q+SA_DIMM_VREFDQ
+SM_VREF
DDR_A_DQS[0..7]<14,8>
DDR_A_D[0..63]<14,8>
DDR_A_DQS#[0..7]<14,8>
DDR_A_MA[0..15]<14,8>
M_CLK_DDR5 <8>
DDR_A_RAS# <14,8>
M_ODT5 <8>
DDR_A_BS1 <14,8>
DDR_CKE5_DIMM1 <8>
M_CLK_DDR#5 <8>
M_ODT4 <8>
DDR_CS4_DIMM1# <8>
DDR_CKE4_DIMM1<8>
DDR_A_BS2<14,8>
DDR_CS5_DIMM1#<8>
DDR_A_CAS#<14,8>
DDR_A_WE#<14,8>
M_CLK_DDR4<8>
M_CLK_DDR#4<8>
DDR_A_BS0<14,8>
DDR_XDP_WAN_SMBCLK <14,15,16,18,21,45>
DDR_XDP_WAN_SMBDAT <14,15,16,18,21,45>
DDR3_DRAMRST#_R <14,15,16>
DDR_HVREF_RST_PCH<15,21,7>
DDR3_DRAMRST#_CPU<7>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
DDRIII-SODIMM SLOT1
13 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
DDRIII-SODIMM SLOT1
13 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
DDRIII-SODIMM SLOT1
13 67Monday, January 13, 2014
Compal Electronics, Inc.
CD4
1U_0402_6.3V6K
CD4
1U_0402_6.3V6K
1
2
CD89
0.022U_0402_16V7K
CD89
0.022U_0402_16V7K
1
2
CD20
1U_0402_6.3V6K
CD20
1U_0402_6.3V6K
1
2
RD9 0_0402_5%@RD9 0_0402_5%@
1 2
+
CD14
330U_SX_2VY
+
CD14
330U_SX_2VY
1
2
RD10 0_0402_5%@RD10 0_0402_5%@
1 2
CD22
2.2U_0402_6.3V6M
@CD22
2.2U_0402_6.3V6M
@
1
2
QD6A
DMN66D0LDW-7_SOT363-6
@QD6A
DMN66D0LDW-7_SOT363-6
@
61
2
CD5
1U_0402_6.3V6K
CD5
1U_0402_6.3V6K
1
2
RC109
24.9_0402_1%
RC109
24.9_0402_1%
12
RD41 2_0402_1%RD41 2_0402_1%
1 2
CD1
2.2U_0402_6.3V6M
@CD1
2.2U_0402_6.3V6M
@
1
2
RD47
1K_0402_1%
RD47
1K_0402_1%
12
CD18
1U_0402_6.3V6K
CD18
1U_0402_6.3V6K
1
2
RD1 0_0402_5%@RD1 0_0402_5%@
1 2
CD15
2.2U_0402_6.3V6M
@CD15
2.2U_0402_6.3V6M
@
1
2
CD12
10U_0603_6.3V6M
CD12
10U_0603_6.3V6M
1
2
RC110
24.9_0402_1%
RC110
24.9_0402_1%
12
CD90
0.022U_0402_16V7K
CD90
0.022U_0402_16V7K
1
2
RD46
1K_0402_1%
RD46
1K_0402_1%
12
CD11
10U_0603_6.3V6M
CD11
10U_0603_6.3V6M
1
2
CD8
10U_0603_6.3V6M
CD8
10U_0603_6.3V6M
1
2
CD21
0.1U_0402_16V4Z
CD21
0.1U_0402_16V4Z
1
2
G
D
S
QD7
L2N7002WT1G_SC-70-3
@
G
D
S
QD7
L2N7002WT1G_SC-70-3
@
2
13
CD6
0.1U_0402_16V4Z
CD6
0.1U_0402_16V4Z
1
2
RD44
1K_0402_1%
RD44
1K_0402_1%
12
RD2 0_0402_5%@RD2 0_0402_5%@
1 2
CD19
1U_0402_6.3V6K
CD19
1U_0402_6.3V6K
1
2
CD10
10U_0603_6.3V6M
CD10
10U_0603_6.3V6M
1
2
CD9
10U_0603_6.3V6M
CD9
10U_0603_6.3V6M
1
2
RD8
0_0402_5%
@RD8
0_0402_5%
@
1 2
JDIMM1 CONN@
TYCO_2-2013310-1
JDIMM1 CONN@
TYCO_2-2013310-1
VREF_DQ
1VSS1 2
VSS2
3DQ4 4
DQ0
5DQ5 6
DQ1
7VSS3 8
VSS4
9DQS#0 10
DM0
11 DQS0 12
VSS5
13 VSS6 14
DQ2
15 DQ6 16
DQ3
17 DQ7 18
VSS7
19 VSS8 20
DQ8
21 DQ12 22
DQ9
23 DQ13 24
VSS9
25 VSS10 26
DQS#1
27 DM1 28
DQS1
29 RESET# 30
VSS11
31 VSS12 32
DQ10
33 DQ14 34
DQ11
35 DQ15 36
VSS13
37 VSS14 38
DQ16
39 DQ20 40
DQ17
41 DQ21 42
VSS15
43 VSS16 44
DQS#2
45 DM2 46
DQS2
47 VSS17 48
VSS18
49 DQ22 50
DQ18
51 DQ23 52
DQ19
53 VSS19 54
VSS20
55 DQ28 56
DQ24
57 DQ29 58
DQ25
59 VSS21 60
VSS22
61 DQS#3 62
DM3
63 DQS3 64
VSS23
65 VSS24 66
DQ26
67 DQ30 68
DQ27
69 DQ31 70
VSS25
71 VSS26 72
A12/BC#
83 A11 84
A9
85 A7 86
VDD5
87 VDD6 88
A8
89 A6 90
CKE0
73 CKE1 74
VDD1
75 VDD2 76
NC1
77 A15 78
BA2
79 A14 80
VDD3
81 VDD4 82
A5
91 A4 92
VDD7
93 VDD8 94
A3
95 A2 96
A1
97 A0 98
VDD9
99 VDD10 100
CK0
101 CK1 102
CK0#
103 CK1# 104
VDD11
105 VDD12 106
A10/AP
107 BA1 108
BA0
109 RAS# 110
VDD13
111 VDD14 112
WE#
113 S0# 114
CAS#
115 ODT0 116
VDD15
117 VDD16 118
A13
119 ODT1 120
S1#
121 NC2 122
VDD17
123 VDD18 124
NCTEST
125 VREF_CA 126
VSS27
127 VSS28 128
DQ32
129 DQ36 130
DQ33
131 DQ37 132
VSS29
133 VSS30 134
DQS#4
135 DM4 136
DQS4
137 VSS31 138
VSS32
139 DQ38 140
DQ34
141 DQ39 142
DQ35
143 VSS33 144
VSS34
145 DQ44 146
DQ40
147 DQ45 148
DQ41
149 VSS35 150
VSS36
151 DQS#5 152
DM5
153 DQS5 154
VSS37
155 VSS38 156
DQ42
157 DQ46 158
DQ43
159 DQ47 160
VSS39
161 VSS40 162
DQ48
163 DQ52 164
DQ49
165 DQ53 166
VSS41
167 VSS42 168
DQS#6
169 DM6 170
DQS6
171 VSS43 172
VSS44
173 DQ54 174
DQ50
175 DQ55 176
DQ51
177 VSS45 178
VSS46
179 DQ60 180
DQ56
181 DQ61 182
DQ57
183 VSS47 184
VSS48
185 DQS#7 186
DM7
187 DQS7 188
VSS49
189 VSS50 190
DQ58
191 DQ62 192
DQ59
193 DQ63 194
VSS51
195 VSS52 196
SA0
197 EVENT# 198
VDDSPD
199 SDA 200
SA1
201 SCL 202
VTT1
203 VTT2 204
G1
205 G2 206
RD6 0_0402_5%@RD6 0_0402_5%@
1 2
CD2
1U_0402_6.3V6K
CD2
1U_0402_6.3V6K
1
2
CD13
10U_0603_6.3V6M
@CD13
10U_0603_6.3V6M
@
1
2
CD3
1U_0402_6.3V6K
CD3
1U_0402_6.3V6K
1
2
RD43
1K_0402_1%
RD43
1K_0402_1%
12
CD16
0.1U_0402_16V4Z
CD16
0.1U_0402_16V4Z
1
2
CD7
10U_0603_6.3V6M
CD7
10U_0603_6.3V6M
1
2
RD13
0_0402_5%
@RD13
0_0402_5%
@
1 2
RD45 2_0402_1%RD45 2_0402_1%
1 2
RD7 0_0402_5%@RD7 0_0402_5%@
1 2
CD17
1U_0402_6.3V6K
CD17
1U_0402_6.3V6K
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Layout Note:
Place near JDIMM2.Pin 203,204
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
JDIMM2 STD Type H=5.2
All VREF traces should
have 10 mil trace width
0
0
1
DIMM2
1
0
1
DIMM1 0
DIMM4
DIMM3
SA0
1
SA1
DIMM Select
*
CD36 change to SGA20331E10
CPU
JDIMM2
JDIMM1
A
D
B
C
JDIMM4
Top Side
Bottom Side
JDIMM3
DIMM2_SA0
DIMM2_SA1
DDR_A_MA5
DDR_A_MA10
DDR_A_MA1
DDR_A_MA3
DDR_A_MA13
DDR_A_BS0
DDR_A_MA9
DDR_A_MA12
DDR_A_MA8
DDR_A_WE#
DDR_A_BS2
M_CLK_DDR0
DIMM2_SA1
DIMM2_SA0
DDR_A_DQS4
DDR_A_DQS6
DDR_A_DQS#4
DDR_A_DQS#6
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS#7
DDR_A_DQS7
M_CLK_DDR#0
DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_MA2
DDR_A_MA0
DDR_A_MA4
M_CLK_DDR#1
DDR_A_MA14
DDR_A_MA6
DDR_A_MA7
DDR_A_MA11
M_CLK_DDR1
DDR_A_BS1
DDR_A_MA15
DDR_A_RAS#
M_ODT1
M_ODT0DDR_A_CAS#
DDR_A_D5
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D13
DDR_A_D12
DDR_A_D17
DDR_A_D16
DDR_A_D14
DDR_A_D10
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D26
DDR_A_D29
DDR_A_D31
DDR_A_D0
DDR_A_D4
DDR_A_D15
DDR_A_D11
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D30
DDR_A_D25
DDR_A_D33
DDR_A_D32
DDR_A_D41
DDR_A_D34
DDR_A_D40
DDR_A_D38
DDR_A_D48
DDR_A_D52
DDR_A_D43
DDR_A_D42
DDR_A_D54
DDR_A_D50
DDR_A_D61
DDR_A_D60
DDR_A_D59
DDR_A_D63
DDR_A_D27
DDR_A_D28
DDR_A_D6
DDR_A_D9
DDR_A_D7
DDR_A_D8
DDR_A_D37
DDR_A_D36
DDR_A_D44
DDR_A_D35
DDR_A_D39
DDR_A_D45
DDR_A_D53
DDR_A_D49
DDR_A_D47
DDR_A_D46
DDR_A_D55
DDR_A_D57
DDR_A_D56
DDR_A_D51
DDR_A_D58
DDR_A_D62
+0.675V_DDR_VTT
+1.35V_MEM
+1.35V_MEM
+3.3V_RUN
+0.675V_DDR_VTT +0.675V_DDR_VTT
+1.35V_MEM
+DIMM2_VREF_CA
+1.35V_MEM
+DIMM2_VREF_DQ
+SM_VREF_DIMM
+V_DDR_REF
+SA_DIMM1_VREFDQ
DDR_A_DQS[0..7]<13,8>
DDR_A_D[0..63]<13,8>
DDR_A_DQS#[0..7]<13,8>
DDR_A_MA[0..15]<13,8>
DDR_CKE0_DIMM2<8>
DDR_A_BS2<13,8>
DDR_CS1_DIMM2#<8>
DDR_A_CAS#<13,8>
DDR_A_WE#<13,8>
M_CLK_DDR0<8>
M_CLK_DDR#0<8>
DDR_A_BS0<13,8>
DDR_XDP_WAN_SMBCLK <13,15,16,18,21,45>
DDR_XDP_WAN_SMBDAT <13,15,16,18,21,45>
DDR3_DRAMRST#_R <13,15,16>
M_CLK_DDR1 <8>
DDR_A_RAS# <13,8>
DDR_A_BS1 <13,8>
M_ODT1 <8>
DDR_CKE1_DIMM2 <8>
M_CLK_DDR#1 <8>
DDR_CS0_DIMM2# <8>
M_ODT0 <8>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
DDRIII-SODIMM SLOT2
14 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
DDRIII-SODIMM SLOT2
14 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
DDRIII-SODIMM SLOT2
14 67Monday, January 13, 2014
Compal Electronics, Inc.
CD35
10U_0603_6.3V6M
@CD35
10U_0603_6.3V6M
@
1
2
CD34
10U_0603_6.3V6M
CD34
10U_0603_6.3V6M
1
2
RD16 0_0402_5%@RD16 0_0402_5%@
1 2
CD30
10U_0603_6.3V6M
CD30
10U_0603_6.3V6M
1
2
CD44
2.2U_0402_6.3V6M
@
CD44
2.2U_0402_6.3V6M
@
1
2
+
CD36
330U_SX_2VY
+
CD36
330U_SX_2VY
1
2
CD43
0.1U_0402_16V4Z
CD43
0.1U_0402_16V4Z
1
2
CD25
1U_0402_6.3V6K
CD25
1U_0402_6.3V6K
1
2
CD39
1U_0402_6.3V6K
CD39
1U_0402_6.3V6K
1
2
CD32
10U_0603_6.3V6M
CD32
10U_0603_6.3V6M
1
2
RD15 0_0402_5%@RD15 0_0402_5%@
1 2
CD38
1U_0402_6.3V6K
CD38
1U_0402_6.3V6K
1
2
CD41
2.2U_0402_6.3V6M
@
CD41
2.2U_0402_6.3V6M
@
1
2
CD33
10U_0603_6.3V6M
CD33
10U_0603_6.3V6M
1
2
CD26
1U_0402_6.3V6K
CD26
1U_0402_6.3V6K
1
2
CD27
1U_0402_6.3V6K
CD27
1U_0402_6.3V6K
1
2
RD14 0_0402_5%@RD14 0_0402_5%@
1 2
CD28
1U_0402_6.3V6K
CD28
1U_0402_6.3V6K
1
2
CD24
0.1U_0402_16V4Z
CD24
0.1U_0402_16V4Z
1
2
RD20
0_0402_5%
@RD20
0_0402_5%
@
1 2
RD19
0_0402_5%
@RD19
0_0402_5%
@
1 2
CD40
1U_0402_6.3V6K
CD40
1U_0402_6.3V6K
1
2
CD42
0.1U_0402_16V4Z
CD42
0.1U_0402_16V4Z
1
2
CD29
10U_0603_6.3V6M
CD29
10U_0603_6.3V6M
1
2
CD37
1U_0402_6.3V6K
CD37
1U_0402_6.3V6K
1
2
CD23
2.2U_0402_6.3V6M
@
CD23
2.2U_0402_6.3V6M
@
1
2
JDIMM2
TYCO_2-2013289-1~D
CONN@JDIMM2
TYCO_2-2013289-1~D
CONN@
VREF_DQ
1VSS1 2
VSS2
3DQ4 4
DQ0
5DQ5 6
DQ1
7VSS3 8
VSS4
9DQS#0 10
DM0
11 DQS0 12
VSS5
13 VSS6 14
DQ2
15 DQ6 16
DQ3
17 DQ7 18
VSS7
19 VSS8 20
DQ8
21 DQ12 22
DQ9
23 DQ13 24
VSS9
25 VSS10 26
DQS#1
27 DM1 28
DQS1
29 RESET# 30
VSS11
31 VSS12 32
DQ10
33 DQ14 34
DQ11
35 DQ15 36
VSS13
37 VSS14 38
DQ16
39 DQ20 40
DQ17
41 DQ21 42
VSS15
43 VSS16 44
DQS#2
45 DM2 46
DQS2
47 VSS17 48
VSS18
49 DQ22 50
DQ18
51 DQ23 52
DQ19
53 VSS19 54
VSS20
55 DQ28 56
DQ24
57 DQ29 58
DQ25
59 VSS21 60
VSS22
61 DQS#3 62
DM3
63 DQS3 64
VSS23
65 VSS24 66
DQ26
67 DQ30 68
DQ27
69 DQ31 70
VSS25
71 VSS26 72
A12/BC#
83 A11 84
A9
85 A7 86
VDD5
87 VDD6 88
A8
89 A6 90
CKE0
73 CKE1 74
VDD1
75 VDD2 76
NC1
77 A15 78
BA2
79 A14 80
VDD3
81 VDD4 82
A5
91 A4 92
VDD7
93 VDD8 94
A3
95 A2 96
A1
97 A0 98
VDD9
99 VDD10 100
CK0
101 CK1 102
CK0#
103 CK1# 104
VDD11
105 VDD12 106
A10/AP
107 BA1 108
BA0
109 RAS# 110
VDD13
111 VDD14 112
WE#
113 S0# 114
CAS#
115 ODT0 116
VDD15
117 VDD16 118
A13
119 ODT1 120
S1#
121 NC2 122
VDD17
123 VDD18 124
NCTEST
125 VREF_CA 126
VSS27
127 VSS28 128
DQ32
129 DQ36 130
DQ33
131 DQ37 132
VSS29
133 VSS30 134
DQS#4
135 DM4 136
DQS4
137 VSS31 138
VSS32
139 DQ38 140
DQ34
141 DQ39 142
DQ35
143 VSS33 144
VSS34
145 DQ44 146
DQ40
147 DQ45 148
DQ41
149 VSS35 150
VSS36
151 DQS#5 152
DM5
153 DQS5 154
VSS37
155 VSS38 156
DQ42
157 DQ46 158
DQ43
159 DQ47 160
VSS39
161 VSS40 162
DQ48
163 DQ52 164
DQ49
165 DQ53 166
VSS41
167 VSS42 168
DQS#6
169 DM6 170
DQS6
171 VSS43 172
VSS44
173 DQ54 174
DQ50
175 DQ55 176
DQ51
177 VSS45 178
VSS46
179 DQ60 180
DQ56
181 DQ61 182
DQ57
183 VSS47 184
VSS48
185 DQS#7 186
DM7
187 DQS7 188
VSS49
189 VSS50 190
DQ58
191 DQ62 192
DQ59
193 DQ63 194
VSS51
195 VSS52 196
SA0
197 EVENT# 198
VDDSPD
199 SDA 200
SA1
201 SCL 202
VTT1
203 VTT2 204
G1
205 G2 206
CD31
10U_0603_6.3V6M
CD31
10U_0603_6.3V6M
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Layout Note:
Place near JDIMM3.Pin 203,204
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
JDIMM3 STD Type H=5.2
All VREF traces should
have 10 mil trace width
0
0
1
DIMM2
1
0
1
DIMM1 0
DIMM4
DIMM3
SA0
1
SA1
DIMM Select
*
CPU
JDIMM2
JDIMM1
A
D
B
C
JDIMM4
Top Side
Bottom Side
JDIMM3
DIMM3_SA0
DIMM3_SA1
DDR3_DRAMRST#_R
DDR_B_MA7
DDR_B_MA14
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA11
DDR_B_MA0
DDR_B_MA15
M_ODT6
DDR_B_BS1
M_ODT7
M_CLK_DDR7
DDR_B_RAS#
M_CLK_DDR#7
DIMM3_SA1
DIMM3_SA0
DDR_B_BS2
DDR_B_MA3
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA1
M_CLK_DDR6
M_CLK_DDR#6
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDR_B_D6
DDR_B_D9
DDR_B_D1
DDR_B_D29
DDR_B_D5
DDR_B_D30
DDR_B_D0
DDR_B_D7
DDR_B_D8
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D11
DDR_B_D13
DDR_B_D21
DDR_B_D20
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D31
DDR_B_D17
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D16
DDR_B_D10
DDR_B_D28
DDR_B_D27
DDR_B_D12
DDR_B_D26
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D25
DDR_B_D2
DDR_B_D3
DDR_B_D24
DDR_B_D19
DDR_B_D18
DDR_B_D14
DDR_B_D22
DDR_B_D23
DDR_B_D15
DDR_B_D4
DDR_B_D54
DDR_B_D51
DDR_B_DQS5
DDR_B_D39
DDR_B_DQS#5
DDR_B_D42
DDR_B_D61
DDR_B_D60
DDR_B_D59
DDR_B_D63
DDR_B_DQS7
DDR_B_DQS#7
DDR_B_D58
DDR_B_D62
DDR_B_D47
DDR_B_D46
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_D53
DDR_B_D48
DDR_B_D56
DDR_B_D57
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_D33
DDR_B_D37
DDR_B_D34
DDR_B_D38
DDR_B_D52
DDR_B_D49
DDR_B_D36
DDR_B_D32
DDR_B_D35
DDR_B_D43
DDR_B_D50
DDR_B_D55
DDR_B_D45
DDR_B_D41
DDR_B_D40
DDR_B_D44
DDR_HVREF_RST_PCH
+1.35V_MEM
+1.35V_MEM
+0.675V_DDR_VTT
+3.3V_RUN
+DIMM3_VREF_CA
+0.675V_DDR_VTT
+1.35V_MEM+1.35V_MEM
+3.3V_RUN
+0.675V_DDR_VTT
+DIMM3_VREF_DQ
+SM_VREF_DIMM
+V_DDR_REF
+SB_DIMM2_VREFDQ
+SB_DIMM_VREFDQ_Q +1.35V_MEM
+SB_DIMM2_VREFDQ
+SB_DIMM_VREFDQ
DDR_B_D[0..63]<16,8>
DDR_B_DQS[0..7]<16,8>
DDR_B_MA[0..15]<16,8>
DDR_B_DQS#[0..7]<16,8>
DDR3_DRAMRST#_R <13,14,16>
DDR_XDP_WAN_SMBCLK <13,14,16,18,21,45>
DDR_XDP_WAN_SMBDAT <13,14,16,18,21,45>
DDR_CKE7_DIMM3 <8>
DDR_B_RAS# <16,8>
DDR_B_BS1 <16,8>
M_ODT6 <8>
DDR_CS6_DIMM3# <8>
M_CLK_DDR7 <8>
M_CLK_DDR#7 <8>
M_ODT7 <8>
DDR_B_CAS#<16,8>
DDR_B_WE#<16,8>
DDR_CKE6_DIMM3<8>
DDR_B_BS0<16,8>
DDR_B_BS2<16,8>
DDR_CS7_DIMM3#<8>
M_CLK_DDR6<8>
M_CLK_DDR#6<8>
DDR_HVREF_RST_PCH<13,21,7>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
DDRIII-SODIMM SLOT3
15 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
DDRIII-SODIMM SLOT3
15 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
DDRIII-SODIMM SLOT3
15 67Monday, January 13, 2014
Compal Electronics, Inc.
RD24 0_0402_5%@RD24 0_0402_5%@
1 2
CD61
1U_0402_6.3V6K
CD61
1U_0402_6.3V6K
1
2
CD54
10U_0603_6.3V6M
CD54
10U_0603_6.3V6M
1
2
CD55
10U_0603_6.3V6M
CD55
10U_0603_6.3V6M
1
2
CD59
1U_0402_6.3V6K
CD59
1U_0402_6.3V6K
1
2
JDIMM3
TYCO_2-2013289-1~D
CONN@JDIMM3
TYCO_2-2013289-1~D
CONN@
VREF_DQ
1VSS1 2
VSS2
3DQ4 4
DQ0
5DQ5 6
DQ1
7VSS3 8
VSS4
9DQS#0 10
DM0
11 DQS0 12
VSS5
13 VSS6 14
DQ2
15 DQ6 16
DQ3
17 DQ7 18
VSS7
19 VSS8 20
DQ8
21 DQ12 22
DQ9
23 DQ13 24
VSS9
25 VSS10 26
DQS#1
27 DM1 28
DQS1
29 RESET# 30
VSS11
31 VSS12 32
DQ10
33 DQ14 34
DQ11
35 DQ15 36
VSS13
37 VSS14 38
DQ16
39 DQ20 40
DQ17
41 DQ21 42
VSS15
43 VSS16 44
DQS#2
45 DM2 46
DQS2
47 VSS17 48
VSS18
49 DQ22 50
DQ18
51 DQ23 52
DQ19
53 VSS19 54
VSS20
55 DQ28 56
DQ24
57 DQ29 58
DQ25
59 VSS21 60
VSS22
61 DQS#3 62
DM3
63 DQS3 64
VSS23
65 VSS24 66
DQ26
67 DQ30 68
DQ27
69 DQ31 70
VSS25
71 VSS26 72
A12/BC#
83 A11 84
A9
85 A7 86
VDD5
87 VDD6 88
A8
89 A6 90
CKE0
73 CKE1 74
VDD1
75 VDD2 76
NC1
77 A15 78
BA2
79 A14 80
VDD3
81 VDD4 82
A5
91 A4 92
VDD7
93 VDD8 94
A3
95 A2 96
A1
97 A0 98
VDD9
99 VDD10 100
CK0
101 CK1 102
CK0#
103 CK1# 104
VDD11
105 VDD12 106
A10/AP
107 BA1 108
BA0
109 RAS# 110
VDD13
111 VDD14 112
WE#
113 S0# 114
CAS#
115 ODT0 116
VDD15
117 VDD16 118
A13
119 ODT1 120
S1#
121 NC2 122
VDD17
123 VDD18 124
NCTEST
125 VREF_CA 126
VSS27
127 VSS28 128
DQ32
129 DQ36 130
DQ33
131 DQ37 132
VSS29
133 VSS30 134
DQS#4
135 DM4 136
DQS4
137 VSS31 138
VSS32
139 DQ38 140
DQ34
141 DQ39 142
DQ35
143 VSS33 144
VSS34
145 DQ44 146
DQ40
147 DQ45 148
DQ41
149 VSS35 150
VSS36
151 DQS#5 152
DM5
153 DQS5 154
VSS37
155 VSS38 156
DQ42
157 DQ46 158
DQ43
159 DQ47 160
VSS39
161 VSS40 162
DQ48
163 DQ52 164
DQ49
165 DQ53 166
VSS41
167 VSS42 168
DQS#6
169 DM6 170
DQS6
171 VSS43 172
VSS44
173 DQ54 174
DQ50
175 DQ55 176
DQ51
177 VSS45 178
VSS46
179 DQ60 180
DQ56
181 DQ61 182
DQ57
183 VSS47 184
VSS48
185 DQS#7 186
DM7
187 DQS7 188
VSS49
189 VSS50 190
DQ58
191 DQ62 192
DQ59
193 DQ63 194
VSS51
195 VSS52 196
SA0
197 EVENT# 198
VDDSPD
199 SDA 200
SA1
201 SCL 202
VTT1
203 VTT2 204
G1
205 G2 206
CD91
0.022U_0402_16V7K
CD91
0.022U_0402_16V7K
1
2
CD64
0.1U_0402_16V4Z
CD64
0.1U_0402_16V4Z
1
2
RD50
1K_0402_1%
RD50
1K_0402_1%
12
CD66
2.2U_0402_6.3V6M
@CD66
2.2U_0402_6.3V6M
@
1
2
RD23 0_0402_5%@RD23 0_0402_5%@
1 2
CD52
10U_0603_6.3V6M
CD52
10U_0603_6.3V6M
1
2
QD6B
DMN66D0LDW-7_SOT363-6
@QD6B
DMN66D0LDW-7_SOT363-6
@
3
5
4
CD50
1U_0402_6.3V6K
CD50
1U_0402_6.3V6K
1
2
CD46
1U_0402_6.3V6K
CD46
1U_0402_6.3V6K
1
2
CD51
10U_0603_6.3V6M
CD51
10U_0603_6.3V6M
1
2
+
CD58
330U_SX_2VY
@
+
CD58
330U_SX_2VY
@
1
2
CD48
1U_0402_6.3V6K
CD48
1U_0402_6.3V6K
1
2
RC111
24.9_0402_1%
RC111
24.9_0402_1%
12
CD65
0.1U_0402_16V4Z
CD65
0.1U_0402_16V4Z
1
2
RD26
0_0402_5%
@RD26
0_0402_5%
@
1 2
CD57
10U_0603_6.3V6M
@CD57
10U_0603_6.3V6M
@
1
2
CD45
0.1U_0402_16V4Z
CD45
0.1U_0402_16V4Z
1
2
RD11 0_0402_5%@RD11 0_0402_5%@
1 2
RD49
1K_0402_1%
RD49
1K_0402_1%
12
CD62
1U_0402_6.3V6K
CD62
1U_0402_6.3V6K
1
2
CD49
2.2U_0402_6.3V6M
@CD49
2.2U_0402_6.3V6M
@
1
2
CD63
2.2U_0402_6.3V6M
@CD63
2.2U_0402_6.3V6M
@
1
2
CD47
1U_0402_6.3V6K
CD47
1U_0402_6.3V6K
1
2
CD56
10U_0603_6.3V6M
CD56
10U_0603_6.3V6M
1
2
RD27
0_0402_5%
@RD27
0_0402_5%
@
1 2
CD60
1U_0402_6.3V6K
CD60
1U_0402_6.3V6K
1
2
CD53
10U_0603_6.3V6M
CD53
10U_0603_6.3V6M
1
2
RD48 2_0402_1%RD48 2_0402_1%
1 2
RD25 0_0402_5%@RD25 0_0402_5%@
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Layout Note:
Place near JDIMM4.Pin 203,204
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
JDIMM4 REV Type H=5.2
All VREF traces should
have 10 mil trace width
0
0
1
DIMM2
1
0
1
DIMM1 0
DIMM4
DIMM3
SA0
1
SA1
DIMM Select
*
CPU
JDIMM2
JDIMM1
A
D
B
C
JDIMM4
Top Side
Bottom Side
JDIMM3
DIMM4_SA0
DIMM4_SA1
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_DQS#2
DDR_B_DQS2
DDR3_DRAMRST#_R
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_MA7
DDR_B_MA14
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA11
DDR_B_MA0
DDR_B_MA15
M_ODT2
DDR_B_BS1
M_ODT3
M_CLK_DDR3
DDR_B_RAS#
M_CLK_DDR#3
DIMM4_SA1
DIMM4_SA0
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_BS2
DDR_B_MA3
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA1
M_CLK_DDR2
M_CLK_DDR#2
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDR_B_D1
DDR_B_D5
DDR_B_D6
DDR_B_D2
DDR_B_D14
DDR_B_D15
DDR_B_D17
DDR_B_D16
DDR_B_D10
DDR_B_D12
DDR_B_D28
DDR_B_D25
DDR_B_D19
DDR_B_D18
DDR_B_D27
DDR_B_D26
DDR_B_D0
DDR_B_D4
DDR_B_D9
DDR_B_D7
DDR_B_D8
DDR_B_D3
DDR_B_D11
DDR_B_D13
DDR_B_D21
DDR_B_D20
DDR_B_D29
DDR_B_D24
DDR_B_D22
DDR_B_D23
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D36
DDR_B_D39
DDR_B_D35
DDR_B_D41
DDR_B_D45
DDR_B_D42
DDR_B_D52
DDR_B_D49
DDR_B_D43
DDR_B_D51
DDR_B_D54
DDR_B_D60
DDR_B_D61
DDR_B_D63
DDR_B_D59
DDR_B_D37
DDR_B_D33
DDR_B_D38
DDR_B_D34
DDR_B_D44
DDR_B_D40
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D53
DDR_B_D57
DDR_B_D56
DDR_B_D55
DDR_B_D50
DDR_B_D62
DDR_B_D58
+3.3V_RUN
+1.35V_MEM
+1.35V_MEM
+0.675V_DDR_VTT
+DIMM4_VREF_DQ
+DIMM4_VREF_CA
+0.675V_DDR_VTT
+1.35V_MEM+1.35V_MEM
+3.3V_RUN
+0.675V_DDR_VTT
+SM_VREF_DIMM
+V_DDR_REF
+SB_DIMM2_VREFDQ
DDR_B_D[0..63]<15,8>
DDR_B_DQS[0..7]<15,8>
DDR_B_MA[0..15]<15,8>
DDR_B_DQS#[0..7]<15,8>
DDR3_DRAMRST#_R <13,14,15>
DDR_CKE3_DIMM4 <8>
DDR_B_RAS# <15,8>
DDR_B_BS1 <15,8>
M_ODT2 <8>
DDR_CS2_DIMM4# <8>
M_CLK_DDR3 <8>
M_CLK_DDR#3 <8>
M_ODT3 <8>
DDR_B_CAS#<15,8>
DDR_B_WE#<15,8>
DDR_CKE2_DIMM4<8>
DDR_B_BS0<15,8>
DDR_B_BS2<15,8>
DDR_CS3_DIMM4#<8>
M_CLK_DDR2<8>
M_CLK_DDR#2<8>
DDR_XDP_WAN_SMBCLK <13,14,15,18,21,45>
DDR_XDP_WAN_SMBDAT <13,14,15,18,21,45>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
DDRIII-SODIMM SLOT4
16 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
DDRIII-SODIMM SLOT4
16 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
DDRIII-SODIMM SLOT4
16 67Monday, January 13, 2014
Compal Electronics, Inc.
CD69
1U_0402_6.3V6K
CD69
1U_0402_6.3V6K
1
2
CD84
1U_0402_6.3V6K
CD84
1U_0402_6.3V6K
1
2
CD82
1U_0402_6.3V6K
CD82
1U_0402_6.3V6K
1
2
RD33 0_0402_5%@RD33 0_0402_5%@
1 2
RD36
0_0402_5%
@RD36
0_0402_5%
@
1 2
CD72
1U_0402_6.3V6K
CD72
1U_0402_6.3V6K
1
2
CD81
1U_0402_6.3V6K
CD81
1U_0402_6.3V6K
1
2
JDIMM4
TYCO_2-2013290-1
CONN@JDIMM4
TYCO_2-2013290-1
CONN@
VREF_DQ
1VSS1 2
VSS2
3DQ4 4
DQ0
5DQ5 6
DQ1
7VSS3 8
VSS4
9DQS#0 10
DM0
11 DQS0 12
VSS5
13 VSS6 14
DQ2
15 DQ6 16
DQ3
17 DQ7 18
VSS7
19 VSS8 20
DQ8
21 DQ12 22
DQ9
23 DQ13 24
VSS9
25 VSS10 26
DQS#1
27 DM1 28
DQS1
29 RESET# 30
VSS11
31 VSS12 32
DQ10
33 DQ14 34
DQ11
35 DQ15 36
VSS13
37 VSS14 38
DQ16
39 DQ20 40
DQ17
41 DQ21 42
VSS15
43 VSS16 44
DQS#2
45 DM2 46
DQS2
47 VSS17 48
VSS18
49 DQ22 50
DQ18
51 DQ23 52
DQ19
53 VSS19 54
VSS20
55 DQ28 56
DQ24
57 DQ29 58
DQ25
59 VSS21 60
VSS22
61 DQS#3 62
DM3
63 DQS3 64
VSS23
65 VSS24 66
DQ26
67 DQ30 68
DQ27
69 DQ31 70
VSS25
71 VSS26 72
A12/BC#
83 A11 84
A9
85 A7 86
VDD5
87 VDD6 88
A8
89 A6 90
CKE0
73 CKE1 74
VDD1
75 VDD2 76
NC1
77 A15 78
BA2
79 A14 80
VDD3
81 VDD4 82
A5
91 A4 92
VDD7
93 VDD8 94
A3
95 A2 96
A1
97 A0 98
VDD9
99 VDD10 100
CK0
101 CK1 102
CK0#
103 CK1# 104
VDD11
105 VDD12 106
A10/AP
107 BA1 108
BA0
109 RAS# 110
VDD13
111 VDD14 112
WE#
113 S0# 114
CAS#
115 ODT0 116
VDD15
117 VDD16 118
A13
119 ODT1 120
S1#
121 NC2 122
VDD17
123 VDD18 124
NCTEST
125 VREF_CA 126
VSS27
127 VSS28 128
DQ32
129 DQ36 130
DQ33
131 DQ37 132
VSS29
133 VSS30 134
DQS#4
135 DM4 136
DQS4
137 VSS31 138
VSS32
139 DQ38 140
DQ34
141 DQ39 142
DQ35
143 VSS33 144
VSS34
145 DQ44 146
DQ40
147 DQ45 148
DQ41
149 VSS35 150
VSS36
151 DQS#5 152
DM5
153 DQS5 154
VSS37
155 VSS38 156
DQ42
157 DQ46 158
DQ43
159 DQ47 160
VSS39
161 VSS40 162
DQ48
163 DQ52 164
DQ49
165 DQ53 166
VSS41
167 VSS42 168
DQS#6
169 DM6 170
DQS6
171 VSS43 172
VSS44
173 DQ54 174
DQ50
175 DQ55 176
DQ51
177 VSS45 178
VSS46
179 DQ60 180
DQ56
181 DQ61 182
DQ57
183 VSS47 184
VSS48
185 DQS#7 186
DM7
187 DQS7 188
VSS49
189 VSS50 190
DQ58
191 DQ62 192
DQ59
193 DQ63 194
VSS51
195 VSS52 196
SA0
197 EVENT# 198
VDDSPD
199 SDA 200
SA1
201 SCL 202
VTT1
203 VTT2 204
G1
205 G2 206
CD78
10U_0603_6.3V6M
CD78
10U_0603_6.3V6M
1
2
CD74
10U_0603_6.3V6M
CD74
10U_0603_6.3V6M
1
2
RD37
0_0402_5%
@RD37
0_0402_5%
@
1 2
CD70
1U_0402_6.3V6K
CD70
1U_0402_6.3V6K
1
2
CD67
2.2U_0402_6.3V6M
@
CD67
2.2U_0402_6.3V6M
@
1
2
CD86
0.1U_0402_16V4Z
CD86
0.1U_0402_16V4Z
1
2
CD68
0.1U_0402_16V4Z
CD68
0.1U_0402_16V4Z
1
2
RD32 0_0402_5%@RD32 0_0402_5%@
1 2
CD79
10U_0603_6.3V6M
@CD79
10U_0603_6.3V6M
@
1
2
CD73
10U_0603_6.3V6M
CD73
10U_0603_6.3V6M
1
2
+
CD80
330U_SX_2VY
+
CD80
330U_SX_2VY
1
2
CD83
1U_0402_6.3V6K
CD83
1U_0402_6.3V6K
1
2
CD87
0.1U_0402_16V4Z
CD87
0.1U_0402_16V4Z
1
2
CD76
10U_0603_6.3V6M
CD76
10U_0603_6.3V6M
1
2
CD75
10U_0603_6.3V6M
CD75
10U_0603_6.3V6M
1
2
CD85
2.2U_0402_6.3V6M
@
CD85
2.2U_0402_6.3V6M
@
1
2
CD71
1U_0402_6.3V6K
CD71
1U_0402_6.3V6K
1
2
CD88
2.2U_0402_6.3V6M
@
CD88
2.2U_0402_6.3V6M
@
1
2
RD34 0_0402_5%@RD34 0_0402_5%@
1 2
CD77
10U_0603_6.3V6M
CD77
10U_0603_6.3V6M
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
SYSTEM
40mil(1A)
400mil(10A)
100mil(2.5A, 5VIA)
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
WiGig/
Docking DP port 1
MB_DP/TBT
MB_HDMI/
Docking DP port 2 eDP MUX
CRT
LInk CIS
LInk CIS
PCB Footprint: JAE_MM70-314-310B1-1-R3_310P-S
MXM_PIN80_R for 3D function usage (JMXM1_pin 80).
Remove DYN_TURB_GPU_PWR_ALRT#
pin 71, 73: Remove MXM_LVDS_DDC
GPU_SMBCLK_R
MXM_OVERT#
MXM_DPC_P2
CLK_PCIE_VGA#
MXM_DPA_P2
MXM_DPA_N2
MXM_DPC_P1
MXM_DPC_N0
MXM_EDP_AUX#
MXM_EDP_AUX
MXM_EDP_LANE_N2
MXM_EDP_LANE_P2
MXM_EDP_LANE_N3
MXM_EDP_LANE_P3
MXM_EDP_LANE_N1
MXM_EDP_LANE_P1
MXM_EDP_LANE_N0
MXM_EDP_LANE_P0
MXM_CRT_HSYNC
MXM_CRT_VSYNC
MXM_DPA_P0
CLK_PCIE_VGA
MXM_DPA_P3
MXM_DPA_N3
MXM_DPC_P3
MXM_DPC_N3
MXM_DPC_P0
MXM_CRT_BLU
MXM_CRT_GRN
MXM_CRT_RED
MXM_DPC_N2
MXM_DPA_P1
MXM_DPA_N1
MXM_CLK_REQ#
DGPU_PEX_RST#
MXM_PRESENTL#
MXM_DPB_AUX
MXM_DPC_AUX
MXM_DPC_AUX#
MXM_DPB_AUX#
MXM_DPB_P1
MXM_DPB_N1
MXM_DPB_N2
MXM_DPB_N3
MXM_DPB_P3
MXM_DPB_P2
MXM_DPB_N0
MXM_DPB_P0
MXM_EDP_HPD
MXM_DPC_N1
MXM_DPA_N0
MXM_PWR_LEVEL
PEG_CRX_GTX_C_N[0..15]
PEG_CRX_GTX_C_P[0..15]
PEG_CTX_GRX_P[0..15]
PEG_CTX_GRX_N[0..15]
GPU_SMBDAT_R
DGPU_PWROK
GPU_SMBCLK_R
MXM_CRT_DDC_DAT
MXM_CRT_DDC_CLK
GPU_SMBDAT_R
DGPU_PWROK
DGPU_PEX_RST#
MXM_OVERT#
MXM_ALERT#
MXM_ALERT#
PEG_CRX_GTX_C_N2
PEG_CRX_GTX_C_P2
PEG_CRX_GTX_C_N1
PEG_CRX_GTX_C_P1
PEG_CRX_GTX_C_N0
PEG_CRX_GTX_C_P0
PEG_CTX_GRX_N2
PEG_CTX_GRX_P2
PEG_CTX_GRX_N1
PEG_CTX_GRX_P1
PEG_CTX_GRX_N0
PEG_CTX_GRX_P0
PEG_CRX_GTX_C_N5
PEG_CRX_GTX_C_P5
PEG_CRX_GTX_C_N4
PEG_CRX_GTX_C_P4
PEG_CRX_GTX_C_N7
PEG_CRX_GTX_C_P7
PEG_CRX_GTX_C_N6
PEG_CRX_GTX_C_P6
PEG_CRX_GTX_C_N15
PEG_CRX_GTX_C_P15
PEG_CRX_GTX_C_N14
PEG_CRX_GTX_C_P14
PEG_CRX_GTX_C_N3
PEG_CRX_GTX_C_P3
PEG_CRX_GTX_C_N13
PEG_CRX_GTX_C_P13
PEG_CRX_GTX_C_N12
PEG_CRX_GTX_C_P12
PEG_CRX_GTX_C_N9
PEG_CRX_GTX_C_P9
PEG_CRX_GTX_C_N8
PEG_CRX_GTX_C_P8
PEG_CRX_GTX_C_N11
PEG_CRX_GTX_C_P11
PEG_CRX_GTX_C_N10
PEG_CRX_GTX_C_P10
PEG_CTX_GRX_N3
PEG_CTX_GRX_P3
PEG_CTX_GRX_N13
PEG_CTX_GRX_P13
PEG_CTX_GRX_N12
PEG_CTX_GRX_P12
PEG_CTX_GRX_N11
PEG_CTX_GRX_P11
PEG_CTX_GRX_N10
PEG_CTX_GRX_P10
PEG_CTX_GRX_N15
PEG_CTX_GRX_N9
PEG_CTX_GRX_P9
PEG_CTX_GRX_N8
PEG_CTX_GRX_P8
PEG_CTX_GRX_N7
PEG_CTX_GRX_P7
PEG_CTX_GRX_N6
PEG_CTX_GRX_P6
PEG_CTX_GRX_P15
PEG_CTX_GRX_N14
PEG_CTX_GRX_P14
PEG_CTX_GRX_N5
PEG_CTX_GRX_P5
PEG_CTX_GRX_N4
PEG_CTX_GRX_P4
MXM_CLK_REQ#
MXM_DPB_HPD
MXM_DPA_HPD
MXM_DPC_HPD
MXM_DPA_AUX#
MXM_DPA_AUX
MXM_PWR_LEVEL
DGPU_PWROK DGPU_PWROK DGPU_PWROK
MXM_DPA_HPD_GATE
MXM_DPA_HPD_GATE
MXM_DPC_HPD_GATE
MXM_DPC_HPD_GATE
DGPU_PEX_RST#
MXM_DPB_HPD_GATE
MXM_DPB_HPD_GATE
MXM_RSVD1
MXM_RSVD2
MXM_RSVD1
MXM_RSVD2
+3.3V_MXM
+3.3V_MXM
+MXM_PWR_SRC
+3.3V_MXM
+MXM_PWR_SRC
+3.3V_MXM
+3.3V_MXM
+5V_MXM
+5V_MXM
+3.3V_MXM +3.3V_ALW
+3.3V_MXM
+3.3V_MXM
+3.3V_MXM
+3.3V_ALW
+3.3V_MXM
+3.3V_MXM +3.3V_MXM
+3.3V_ALW
GPU_SMBDAT <51>
GPU_SMBCLK <51>
MXM_DPA_P0<31>
MXM_DPA_N0<31>
MXM_DPA_P1<31>
MXM_DPA_N1<31>
MXM_EDP_LANE_N1 <29>
MXM_EDP_LANE_P1 <29>
MXM_DPC_P2<38>
MXM_DPC_N2<38>
MXM_DPC_P3<38>
MXM_DPC_N3<38>
MXM_DPB_P1 <36>
MXM_DPC_AUX#<38>
MXM_CRT_VSYNC <35>
MXM_DPB_P2 <36>
MXM_DPB_N2 <36>
MXM_CRT_DDC_DAT <35>
MXM_CRT_HSYNC <35>
MXM_EDP_AUX <29>
MXM_EDP_LANE_N0 <29>
MXM_EDP_LANE_P0 <29>
MXM_EDP_AUX# <29>
MXM_DPC_P0<38>
MXM_DPC_N0<38>
MXM_EDP_LANE_N2 <29>
MXM_EDP_LANE_P2 <29>
MXM_PRESENTL#<23>
MXM_DPB_N0 <36>
MXM_CRT_DDC_CLK <35>
MXM_DPC_P1<38>
MXM_DPC_N1<38>
MXM_DPB_AUX <36>
DGPU_PWR_EN <19>
MXM_DPB_AUX# <36>
MXM_DPB_P3 <36>
MXM_DPB_N3 <36>
MXM_DPA_P2<31>
MXM_DPA_N2<31>
MXM_DPA_P3<31>
MXM_DPA_N3<31>
MXM_DPB_P0 <36>
CLK_PCIE_VGA#<20>
CLK_PCIE_VGA<20>
MXM_EDP_HPD <29>
MXM_DPB_N1 <36>
MXM_CRT_RED <35>
MXM_CRT_GRN <35>
MXM_CRT_BLU <35>
PEG_CRX_GTX_C_N[0..15]<6>
PEG_CTX_GRX_N[0..15]<6>
PEG_CTX_GRX_P[0..15]<6>
PEG_CRX_GTX_C_P[0..15]<6>
MXM_ENVDD<30>
MXM_PANEL_BKEN<30>
MXM_BIA_PWM<30>
MXM_EDP_LANE_N3 <29>
MXM_EDP_LANE_P3 <29>
MXM_DPC_AUX<38>
DGPU_HOLD_RST# <19>
PLTRST_GPU# <19>
MXM_PRESENTR# <23>
PCIE_WAKE# <32,42,50>
DGPU_THERMTRIP# <51>
DGPU_ALERT# <50>
MXM_DP_HDMI_HPD <50>
MXM_DPA_AUX#<31>
MXM_DPA_AUX<31>
GPU_PWR_LEVEL <50>
ACAV_IN <51,62,63>
MXM_DPA_HPD <31>MXM_DPC_HPD <38>MXM_DPB_HPD <36>
DGPU_PWROK<23,50>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
MXM
17 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
MXM
17 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
MXM
17 67Monday, January 13, 2014
Compal Electronics, Inc.
R5 4.3K_0402_5%@R5 4.3K_0402_5%@
1 2
R519
100K_0402_5%
@R519
100K_0402_5%
@
1 2
R1970 0_0402_5%@R1970 0_0402_5%@
1 2
JMXM1B
JAE_MM70-314-310B1-1-R300
CONN@JMXM1B
JAE_MM70-314-310B1-1-R300
CONN@
GND
163 GND 162
GND
169 GND 168
GND
175 GND 174
GND
181 GND 180
VGA_DDC_DAT 186
PEX_RX2#
165
PEX_RX1#
171
PEX_RX0#
177
PEX_TX2# 164
PEX_TX1# 170
PEX_TX0# 176
PEX_RX0
179
PEX_RX1
173
PEX_RX2
167
PEX_TX0 178
PEX_TX1 172
PEX_TX2 166
PEX_REFCLK#
183 PEX_CLK_REQ# 182
PEX_REFCLK
185 PEX_RST# 184
GND
187
RSVD
189 VGA_DDC_CLK 188
VGA_VSYNC 190
VGA_HSYNC 192
VGA_RED 196
VGA_GREEN 198
GND 202
GND 208
GND 214
GND 220
LVDS_LTX1# 222
LVDS_LTX2# 216
LVDS_LTX3# 210
LVDS_LCLK# 204
GND 226
GND 232
GND 238
GND 244
LVDS_LTX0# 228
DP_D_L0# 234
DP_D_L1# 240
DP_D_L2# 246
DP_D_L2 248
DP_D_L1 242
DP_D_L0 236
LVDS_LTX0 230
LVDS_LTX1 224
LVDS_LTX2 218
LVDS_LTX3 212
LVDS_LCLK 206
VGA_BLUE 200
GND 194
RSVD
191
RSVD
197
GND
203
GND
209
GND
215
GND
221
GND
227
GND
233
GND
239
GND
245
LVDS_UCLK#
199
LVDS_UTX3#
205
LVDS_UTX2#
211
LVDS_UTX1#
217
RSVD
193
RSVD
195
LVDS_UTX1
219
LVDS_UTX2
213
LVDS_UTX3
207
LVDS_UCLK
201
LVDS_UTX0#
223
DP_C_L0#
229
DP_C_L1#
235
DP_C_L2#
241
LVDS_UTX0
225
DP_C_L0
231
DP_C_L1
237
DP_C_L2
243
DP_C_L3#
247
DP_C_L3
249
GND
251
DP_C_AUX#
253 GND 250
DP_D_L3# 252
DP_C_AUX
255 DP_D_L3 254
RSVD
257 GND 256
RSVD
259 DP_D_AUX# 258
RSVD
261 DP_D_AUX 260
RSVD
263 DP_C_HPD 262
RSVD
265 DP_D_HPD 264
RSVD
267 RSVD 266
RSVD
269 RSVD 268
RSVD
271 RSVD 270
RSVD
273 GND 272
RSVD
275 DP_B_L0# 274
RSVD
277 DP_B_L0 276
RSVD
279
DP_A_L0
285
DP_A_L1
291
DP_A_L2
297
DP_A_L3
303
GND
305
DP_A_AUX#
307
DP_A_AUX
309
PRSNT_L#
310
GND
281
GND
287
GND
293
GND
299
GND 278
GND 284
GND 290
GND 296
DP_B_HPD 302
DP_A_HPD 304
3V3 306
3V3 308
DP_B_L1# 280
DP_B_L2# 286
DP_B_L3# 292
DP_B_AUX# 298
DP_A_L0#
283
DP_A_L1#
289
DP_A_L3#
301
DP_A_L2#
295
DP_B_AUX 300
DP_B_L3 294
DP_B_L2 288
DP_B_L1 282
GND
311 GND 312
R10
10K_0402_5%
R10
10K_0402_5%
12
R3 4.3K_0402_5%@R3 4.3K_0402_5%@
1 2
C96
0.1U_0402_10V7K
@C96
0.1U_0402_10V7K
@
1 2
R6 0_0402_5%@R6 0_0402_5%@
1 2
C8
0.1U_0402_16V4Z
C8
0.1U_0402_16V4Z
1
2
R1978 10K_0402_5%R1978 10K_0402_5%
1 2
R11
10K_0402_5%
R11
10K_0402_5%
12
R135
100K_0402_5%
R135
100K_0402_5%
12
R37
100K_0402_5%
R37
100K_0402_5%
12
C95
0.1U_0402_10V7K
@C95
0.1U_0402_10V7K
@
1 2
C90
0.1U_0402_10V7K
@C90
0.1U_0402_10V7K
@
1 2
G
D
S
Q5
DMN65D8LW-7_SOT323-3
G
D
S
Q5
DMN65D8LW-7_SOT323-3
2
13
R1972 0_0402_5%@R1972 0_0402_5%@
1 2
U16
74AHC1G09GW_TSSOP5~D
U16
74AHC1G09GW_TSSOP5~D
B1
A2
G
3
O
4
P5
Q295B
DMN66D0LDW-7_SOT363-6
Q295B
DMN66D0LDW-7_SOT363-6
3
5
4
D8
RB751VM-40TE-17_SOD323-2
D8
RB751VM-40TE-17_SOD323-2
2 1
T175PAD~D @T175PAD~D @
R38
750_0402_1%
R38
750_0402_1%
12
G
D
S
Q4
DMN65D8LW-7_SOT323-3
G
D
S
Q4
DMN65D8LW-7_SOT323-3
2
13
R60
100K_0402_5%
@R60
100K_0402_5%
@
12
D18
RB751VM-40TE-17_SOD323-2
D18
RB751VM-40TE-17_SOD323-2
2 1
U17
74AHC1G09GW_TSSOP5~D
U17
74AHC1G09GW_TSSOP5~D
B1
A2
G
3
O
4
P5
D7
RB751VM-40TE-17_SOD323-2
D7
RB751VM-40TE-17_SOD323-2
2 1
C328
10U_0603_6.3VAM
C328
10U_0603_6.3VAM
1
2
R1979 0_0402_5%@R1979 0_0402_5%@
1 2
R758
100K_0402_5%
@R758
100K_0402_5%
@
12
R1977 10K_0402_5%R1977 10K_0402_5%
1 2
C332
10U_0603_6.3V6M
C332
10U_0603_6.3V6M
1
2
R1971 0_0402_5%@R1971 0_0402_5%@
1 2
C1
0.1U_0603_25V7K
C1
0.1U_0603_25V7K
1
2
C92
0.1U_0402_10V7K
@C92
0.1U_0402_10V7K
@
1 2
R2
4.7K_0402_5%
@
R2
4.7K_0402_5%
@
12
R51
100K_0402_5%
R51
100K_0402_5%
12
R1
4.7K_0402_5%
@
R1
4.7K_0402_5%
@
12
E1 E2
E3 E4
JMXM1A
JAE_MM70-314-310B1-1-R300
CONN@
E1 E2
E3 E4
JMXM1A
JAE_MM70-314-310B1-1-R300
CONN@
PRSNT_R# 38
WAKE# 40
PWR_GOOD 42
PWR_EN 44
RSVD 46
RSVD 48
RSVD 50
RSVD 52
PWR_LEVEL 54
TH_OVERT# 56
TH_ALERT# 58
TH_PWM 60
GPIO0 62
GPIO1 64
GPIO2 66
SMB_DAT 68
SMB_CLK 70
GND 72
OEM 74
OEM 76
OEM 78
OEM 80
GND 82
PEX_TX15# 84
PEX_TX15 86
GND 88
PEX_TX14# 90
PEX_TX14 92
GND 94
PEX_TX13# 96
PEX_TX13 98
GND 100
PEX_TX12# 102
PEX_TX12 104
GND 106
PEX_TX11# 108
PEX_TX11 110
GND 112
PEX_TX10# 114
PEX_TX10 116
GND 118
PEX_TX9# 120
PEX_TX9 122
GND 124
PEX_TX8# 126
PEX_TX8 128
GND 130
PEX_TX7# 132
PEX_TX7 134
GND 136
PEX_TX6# 138
PEX_TX6 140
GND 142
PEX_TX5# 144
PEX_TX5 146
GND 148
PEX_TX4# 150
PEX_TX4 152
GND 154
PEX_TX3# 156
PEX_TX3 158
GND 160
PWR_SRC
1
5V
37
5V
39
5V
41
5V
43
5V
45
GND
47
GND
49
GND
51
GND
53
PEX_STD_SW#
55
VGA_DISABLE#
57
PNL_PWR_EN
59
PNL_BL_EN
61
PNL_BL_PWM
63
HDMI_CEC
65
DVI_HPD
67
LVDS_DDC_DAT
69
LVDS_DDC_CLK
71
GND
73
OEM
75
OEM
77
OEM
79
OEM
81
GND
83
PEX_RX15#
85
PEX_RX15
87
GND
89
PEX_RX14#
91
PEX_RX14
93
GND
95
PEX_RX13#
97
PEX_RX13
99
GND
101
PEX_RX12#
103
PEX_RX12
105
GND
107
PEX_RX11#
109
PEX_RX11
111
GND
113
PEX_RX10#
115
PEX_RX10
117
GND
119
PEX_RX9#
121
PEX_RX9
123
GND
125
PEX_RX8#
127
PEX_RX8
129
GND
131
PEX_RX7#
133
PEX_RX7
135
GND
137
PEX_RX6#
139
PEX_RX6
141
GND
143
PEX_RX5#
145
PEX_RX5
147
GND
149
PEX_RX4#
151
PEX_RX4
153
GND
155
PEX_RX3#
157
PEX_RX3
159
GND
161
PWR_SRC
3
PWR_SRC
5
PWR_SRC
7
PWR_SRC
9
PWR_SRC
11
PWR_SRC
13
PWR_SRC
15
PWR_SRC
17
GND
33
GND
19
GND
25 GND
23
GND
29
GND
21
GND
27
GND
35
GND
31
PWR_SRC 10
PWR_SRC 2
PWR_SRC 18
PWR_SRC 14
PWR_SRC 16
PWR_SRC 6
PWR_SRC 12
PWR_SRC 8
PWR_SRC 4
GND 20
GND 26
GND 22
GND 36
GND 32
GND 30
GND 34
GND 24
GND 28
C4
68P_0402_50V8J
C4
68P_0402_50V8J
1
2
U27
SN74AHC1G08DCKR_SC70-5
U27
SN74AHC1G08DCKR_SC70-5
IN1 1
IN2 2
G
3
O
4
P5
C94
0.1U_0402_10V7K
@C94
0.1U_0402_10V7K
@
1 2
T176 PAD~D@T176 PAD~D@
U14
SN74AHC1G08DCKR_SC70-5
U14
SN74AHC1G08DCKR_SC70-5
IN1 1
IN2 2
G
3
O
4
P5
R4
10K_0402_5%
R4
10K_0402_5%
12
R19 0_0402_5%@R19 0_0402_5%@
1 2
U25
SN74AHC1G08DCKR_SC70-5
U25
SN74AHC1G08DCKR_SC70-5
IN1 1
IN2 2
G
3
O
4
P5
Q295A
DMN66D0LDW-7_SOT363-6
Q295A
DMN66D0LDW-7_SOT363-6
61
2
C2
10U_0805_25VAK
C2
10U_0805_25VAK
1
2
C3
680P_0603_50V7K
C3
680P_0603_50V7K
1
2
C7
0.1U_0402_16V7K
C7
0.1U_0402_16V7K
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CMOS place near DIMM
DELL CONFIDENTIAL/PROPRIETARY
HDA for Codec
DISABLED WHEN LOW (DEFAULT)
ENABLED WHEN HIGH
NO REBOOT STRAP
LOW = DESABLED (DEFAULT)
HIGH = ENABLED
FLASH DESCRIPTOR SECURITY OVERRIDE
PCH XDP
High - Enable Internal VRs
Low - Enable External VRs
INTVRMEN - INTEGRATED SUS 1.05V VRM
ENABLE
CMOS setting
Shunt Clear CMOS
Keep CMOS
TPM setting
Shunt Clear ME RTC Registers
Keep ME RTC Registers
ME_CLR1
Open
CMOS_CLR1
Open
SATA Impedance Compensation
CAD note:
Place the resistor within 500 mils of the PCH. Avoid
routing next to clock pins.
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
HDD1
Change PN from SA00005NE2L to SA00006P30L
M.2 Slot-2
ODD
HDD2
DOCK
M.2 Slot-3
ME_FWP PCH has internal 20K PD.
(suspend power rail)
Service Mode Switch:
Add a switch to ME_FWP signal to unlock the ME region and
allow the entire region of the SPI flash to be updated using FPT.
FLASH DESCRIPTOR SECURITY OVERRIDE
LOW = ENABLE (DEFAULT) -->Pin1 & Pin3 short
HIGH = DISABLE (ME can update) -->Pin2 & Pin3 short
PT,ST pop R3728 and SW2; MP pop RC301
ME_FWP PCH has internal 20K PD.
(suspend power rail)
PCH_RTCX1
PCH_RTCX2
PCH_RTCRST#
PCH_INTVRMEN
INTRUDER#
SRTCRST#
PCH_AZ_RST#
PCH_AZ_CODEC_SDIN0
PCH_AZ_BITCLK
PCH_AZ_SDOUT
SPKR
PCH_AZ_SYNC
ME_FW P
PCH_GPIO33
+3.3V_ALW_PCH_JTAG
PCH_JTAG_TDI
PCH_JTAG_TMS
PCH_JTAG_TDO
PCH_JTAG_TCK
PCH_TP25
PCH_JTAG_RST
SATA_COMP
SATA_ACT#
HDD1_DET#
SATA_IREF
PCH_AZ_SDOUT
PCH_AZ_RST#
PCH_AZ_SYNC
PCH_AZ_BITCLK
SPKR
PCH_GPIO33
XDP_FN15
PCH_PWRBTN#_XDP
DDR_XDP_WAN_SMBDAT_R2
DDR_XDP_WAN_SMBCLK_R2
XDP_DBRESET#
PCH_JTAG_TDO
PCH_JTAG_TDI
PCH_JTAG_TMSPCH_JTAG_TCK
XDP_FN0
XDP_FN1
XDP_FN2
XDP_FN3
XDP_FN4
XDP_FN5
XDP_FN6
XDP_FN7
XDP_FN16
XDP_FN17
XDP_FN8
XDP_FN9
XDP_FN10
XDP_FN11
XDP_FN12
XDP_FN13
XDP_FN14
SATA4_PCIE1#
SSD_SATA5_PCIE2#
USB_OC4#_R
USB_OC2#
USB_OC5#
USB_OC3#
SIO_EXT_SMI#
USB_OC6#
USB_OC0#_R
USB_OC1#_R
XDP_FN8
XDP_FN9
XDP_FN11
XDP_FN10
XDP_FN12
XDP_FN13
XDP_FN14
HDD1_DET#
XDP_FN15
XDP_FN16
XDP_FN17
BBS_BIT0_R
PCH_GPIO36
HDD2_DET#
LANCLK_REQ#
CARDCLK_REQ#
PCH_GPIO35
SIO_EXT_WAKE#
XDP_FN2
XDP_FN1
XDP_FN4
XDP_FN6
XDP_FN5
XDP_FN3
XDP_FN0
XDP_FN7
PCH_RSMRST#_Q RSMRST#_XDP
HDD1_DET#
PCH_RTCX1_R
PCH_AZ_SDOUT
PCH_INTVRMEN
PCH_JTAG_RST_R
SATA_COMP
RSMRST#_XDP
RESET_OUT# RESET_OUT#_R
RESET_OUT#_R
PCH_AZ_SYNC
PCH_JTAG_RST
PCH_GPIO13
PCH_GPIO13
BBS_BIT0_R
BBS_BIT0_R
ME_FW P
ME_FW PME_FWP_EC
ME_FW P
+RTC_CELL
+3.3V_ALW_PCH
+1.5V_RUN
+3.3V_RUN
+3.3V_ALW_PCH
+3.3V_ALW_PCH
+3.3V_ALW_PCH
+3.3V_RUN+3.3V_ALW_PCH
+RTC_CELL
+1.05V_RUN
+1.5V_RUN
+3.3V_RUN
+3.3V_ALW_PCH
+3.3V_ALW_PCH
PCH_AZ_CODEC_SDIN0<49>
SPKR<49>
SATA_ACT# <52>
HDD1_DET# <18,45>
PCH_AZ_CODEC_SYNC<49>
PCH_AZ_CODEC_SDOUT<49>
PCH_AZ_CODEC_RST#<49>
PCH_AZ_CODEC_BITCLK<49>
XDP_DBRESET# <19,7>
SIO_PWRBTN#_R<19,7>
HDD1_DET#<18,45>
SIO_EXT_WAKE#<23,51>
CARDCLK_REQ#<20,49>
USB_OC3#<22>
USB_OC2#<22,49>
PCH_GPIO35<23>
USB_OC6#<22>
USB_OC5#<22>
USB_OC4#_R<22>
SIO_EXT_SMI#<22,51>
USB_OC1#_R<22>
USB_OC0#_R<22>
PCH_RSMRST#_Q<19,53>
DDR_XDP_WAN_SMBCLK<13,14,15,16,21,45>
DDR_XDP_WAN_SMBDAT<13,14,15,16,21,45>
RESET_OUT#<11,19,51,7>
PCH_GPIO36<23>
HDD2_DET#<23,45>
SATA4_PCIE1#<23,50>
SSD_SATA5_PCIE2#<23,51>
LANCLK_REQ#<20,39>
SATA_PRX_DTX_N0_C <45>
SATA_PTX_DRX_P0_C <45>
SATA_PTX_DRX_N0_C <45>
SATA_PRX_DTX_P0_C <45>
PCH_RTCRST#<41>
PCIE_PRX_SATATX_P4 <42>
PCIE_PTX_SATARX_N4 <42>
PCIE_PTX_SATARX_P4 <42>
PCIE_PRX_SATATX_N4 <42>
SATA_ODD_PRX_DTX_P1_C <46>
SATA_ODD_PTX_DRX_N1_C <46>
SATA_ODD_PTX_DRX_P1_C <46>
SATA_ODD_PRX_DTX_N1_C <46>
SATA_PTX_DRX_P3_C <45>
SATA_PRX_DTX_P3_C <45>
SATA_PRX_DTX_N3_C <45>
SATA_PTX_DRX_N3_C <45>
SATA_PRX_DKTX_P2_C <48>
SATA_PRX_DKTX_N2_C <48>
SATA_PTX_DKRX_P2_C <48>
SATA_PTX_DKRX_N2_C <48>
PCIE_PRX_SATATX_P5 <43>
PCIE_PTX_SATARX_N5 <43>
PCIE_PTX_SATARX_P5 <43>
PCIE_PRX_SATATX_N5 <43>
PCH_SATA_MOD_EN# <50>
PCH_PLTRST# <19,7>
ME_FW P_EC<51>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
PCH (1/9)
18 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
PCH (1/9)
18 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
PCH (1/9)
18 67Monday, January 13, 2014
Compal Electronics, Inc.
RH3710K_0402_5% RH3710K_0402_5%
1 2
RH41 1K_0402_1%@RH41 1K_0402_1%@
1 2
RH63 33_0402_5%RH63 33_0402_5%
1 2
RH35 1K_0402_1%@RH35 1K_0402_1%@
1 2
RH44 20K_0402_5%RH44 20K_0402_5%
1 2
RH577.5K_0402_1% RH577.5K_0402_1%
1 2
RH32 0_0402_5%@RH32 0_0402_5%@
1 2
RH47 51_0402_1%RH47 51_0402_1%
12
T59 PAD~D@T59 PAD~D@
RH55
100_0402_1%
RH55
100_0402_1%
12
RH9 0_0402_5%PXDP@ RH9 0_0402_5%PXDP@
1 2
RH18
330K_0402_1%
@RH18
330K_0402_1%
@
12
RH12 0_0402_5%PXDP@ RH12 0_0402_5%PXDP@
1 2
RH31 0_0402_5%PXDP@ RH31 0_0402_5%PXDP@
1 2
RH24 0_0402_5%PXDP@ RH24 0_0402_5%PXDP@
1 2
RH28 0_0402_5%PXDP@ RH28 0_0402_5%PXDP@
1 2
RH3610K_0402_5% RH3610K_0402_5%
1 2
RH3 0_0402_5%PXDP@ RH3 0_0402_5%PXDP@
1 2
RH22 0_0402_5%PXDP@ RH22 0_0402_5%PXDP@
1 2
RH59 33_0402_5%RH59 33_0402_5%
1 2
RH14 0_0402_5%PXDP@ RH14 0_0402_5%PXDP@
1 2
CH7 1U_0402_6.3VAKCH7 1U_0402_6.3VAK
1 2
RH13 0_0402_5%PXDP@ RH13 0_0402_5%PXDP@
1 2
RH5
330K_0402_1%
RH5
330K_0402_1%
12
RH45 1K_0402_1%RH45 1K_0402_1%
1 2
RH26 1K_0402_1%PXDP@ RH26 1K_0402_1%PXDP@
1 2
RH61 33_0402_5%RH61 33_0402_5%
1 2
RH8 0_0402_5%PXDP@ RH8 0_0402_5%PXDP@
1 2
CMOS1 SHORT PADS~D
@
CMOS1 SHORT PADS~D
@
1
122
YH1
32.768KHZ_12.5PF_Q13FC1350000
YH1
32.768KHZ_12.5PF_Q13FC1350000
12
RH43 1M_0402_5%RH43 1M_0402_5%
1 2
RC301@0_0402_5%RC301@0_0402_5%
12
RH11 0_0402_5%PXDP@ RH11 0_0402_5%PXDP@
1 2
RH4 0_0402_5%PXDP@ RH4 0_0402_5%PXDP@
1 2
RH39
10M_0402_5%
RH39
10M_0402_5%
12
RH48 210_0402_1%RH48 210_0402_1%
1 2
RH34 10K_0402_5%@RH34 10K_0402_5%@
1 2
RH6 0_0402_5%PXDP@ RH6 0_0402_5%PXDP@
1 2
JTAGRTC AZALIA
SATA
LPT_PCH_M_EDS
1 OF 11
UH1A
JTAGRTC AZALIA
SATA
LPT_PCH_M_EDS
1 OF 11
UH1A
TP20
AB6
TP25
F8
TP9 BA2
TP22
C26
RTCX1
B5
SATA_RXN_1 BC10
SATA_RXP_1 BE10
JTAG_TDI
AE2
JTAG_TDO
AD3
JTAG_TMS
AD1
JTAG_TCK
AB3
HDA_SDO
A24
HDA_SDI2
G22
HDA_SDI3
F22
HDA_SDI1
K22
HDA_SDI0
L22
RTCRST#
D9
INTRUDER#
A8
INTVRMEN
G10
SRTCRST#
B9
RTCX2
B4
SATA_IREF BD4
SATA0GP/GPIO21 AT1
SATA1GP/GPIO19 AU2
SATALED# AP3
SATA_RCOMP AY5
SATA_TXP5/PETP2 AR15
SATA_RXP5/PERP2 BE14
SATA_TXN5/PETN2 AP15
SATA_RXN5/PERN2 BC14
SATA_TXP4/PETP1 AW15
SATA_TXN4/PETN1 AV15
SATA_RXP4/PERP1 BB13
SATA_RXN4/PERN1 BD13
SATA_TXP_3 AT13
SATA_RXP_3 BE12
SATA_TXN_3 AR13
SATA_RXN_3 BC12
SATA_TXP_2 AW13
SATA_TXN_2 AY13
SATA_RXN_2 BB9
SATA_RXP_2 BD9
SATA_TXP_1 AW10
SATA_TXN_1 AV10
SATA_TXP_0 AY8
SATA_TXN_0 AW 8
SATA_RXP_0 BE8
SATA_RXN_0 BC8
HDA_RST#
C24
SPKR
AL10
HDA_SYNC
A22
HDA_BCLK
B25
HDA_DOCK_RST#/GPIO13
C22
DOCKEN#/GPIO33
B17
TP8 BB2
RH52 210_0402_1%RH52 210_0402_1%
1 2
RH54
100_0402_1%
RH54
100_0402_1%
12
RH50 210_0402_1%RH50 210_0402_1%
1 2
G
D
S
QH5
BSS138-G_SOT23-3
G
D
S
QH5
BSS138-G_SOT23-3
2
1 3
RH25 0_0402_5%PXDP@ RH25 0_0402_5%PXDP@
1 2
T57PAD~D @T57PAD~D @
RH27 1K_0402_1%PXDP@ RH27 1K_0402_1%PXDP@
1 2
RH19 0_0402_5%PXDP@ RH19 0_0402_5%PXDP@
1 2
R3728
1K_0402_5%
R3728
1K_0402_5%
12
R793
1K_0402_1%
@R793
1K_0402_1%
@
12
RH30 0_0402_5%PXDP@ RH30 0_0402_5%PXDP@
1 2
RH60 10K_0402_5%RH60 10K_0402_5%
1 2
RH7 0_0402_5%PXDP@ RH7 0_0402_5%PXDP@
1 2
RH46
0_0603_5%
PXDP@ RH46
0_0603_5%
PXDP@
12
CH5
18P_0402_50V8J
CH5
18P_0402_50V8J
1 2
CH4
18P_0402_50V8J
CH4
18P_0402_50V8J
1 2
RH53 0_0402_5%@RH53 0_0402_5%@
1 2
RH10 0_0402_5%PXDP@ RH10 0_0402_5%PXDP@
1 2
SW2
SS3-CMFTQR9_3P
SW2
SS3-CMFTQR9_3P
A
1
B
2
C
3
G1
4
G2
5
RH20 0_0402_5%PXDP@ RH20 0_0402_5%PXDP@
1 2
RH42 20K_0402_5%RH42 20K_0402_5%
1 2
RH38 0_0402_5%@RH38 0_0402_5%@
1 2
RH16 0_0402_5%PXDP@ RH16 0_0402_5%PXDP@
1 2
RH65 33_0402_5%EMC@ RH65 33_0402_5%EMC@
1 2
T58PAD~D @T58PAD~D @
RH56
100_0402_1%
RH56
100_0402_1%
12
RH17 0_0402_5%PXDP@ RH17 0_0402_5%PXDP@
1 2
JXDP2
SAMTE_BSH-030-01-L-D-A CONN@
JXDP2
SAMTE_BSH-030-01-L-D-A CONN@
GND0
1
OBSFN_A0
3
OBSFN_A1
5
GND2
7
OBSDATA_A0
9
OBSDATA_A1
11
GND4
13
OBSDATA_A2
15
OBSDATA_A3
17
GND6
19
OBSFN_B0
21
OBSFN_B1
23
GND8
25
OBSDATA_B0
27
OBSDATA_B1
29
GND10
31
OBSDATA_B2
33
OBSDATA_B3
35
GND12
37
PWRGOOD/HOOK0
39
HOOK1
41
VCC_OBS_AB
43
HOOK2
45
HOOK3
47
GND14
49
SDA
51
SCL
53
TCK1
55
TCK0
57
GND16
59
GND1 2
OBSFN_C0 4
OBSFN_C1 6
GND3 8
OBSDATA_C0 10
OBSDATA_C1 12
GND5 14
OBSDATA_C2 16
OBSDATA_C3 18
GND7 20
OBSFN_D0 22
OBSFN_D1 24
GND9 26
OBSDATA_D0 28
OBSDATA_D1 30
GND11 32
OBSDATA_D2 34
OBSDATA_D3 36
GND13 38
ITPCLK/HOOK4 40
ITPCLK#/HOOK5 42
VCC_OBS_CD 44
RESET#/HOOK6 46
DBR#/HOOK7 48
GND15 50
TD0 52
TRST# 54
TDI 56
TMS 58
GND17 60
CH2
0.1U_0402_25V6K
PXDP@
CH2
0.1U_0402_25V6K
PXDP@
1
2
RH40 10K_0402_5%RH40 10K_0402_5%
1 2
RH510_0402_5% @RH510_0402_5% @
12
CH9
15P_0402_50V8J
EMC@ CH9
15P_0402_50V8J
EMC@
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
0 1 Reserved (NAND)
1 0
11 SPI
SATA_SLPD
(BBS_BIT0)
Boot BIOS Strap
BBS_BIT1 Boot BIOS Location
*
00 LPC
HIGH = ENABLED (DEFAULT)
LOW = DISABLED
DSWODVREN - ON DIE DSW VR ENABLE
STP_A16OVR
A16 SWAP OVERRIDE STRAP
LOW = A16 SWAP OVERRIDE
HIGH = DEFAULT
PCI
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
GPIO51 has internal pull up.
CIS LINK OK
CIS LINK OK
Remove DGPU_PWR_EN inverter circuit.
follow E6 common boot code.
Remove
Diesel connect to TPM
Remove CPPE#
Remove
USB_MCARD1_DET#
DMI_CRX_PTX_N1
DMI_CRX_PTX_P0
DMI_CRX_PTX_P3
DMI_CTX_PRX_P0
DMI_CRX_PTX_N2
DMI_CRX_PTX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P3
DMI_CRX_PTX_P2
DMI_CTX_PRX_N1
DMI_CRX_PTX_N0
DMI_CTX_PRX_N0
DMI_CTX_PRX_P1
DMI_CRX_PTX_N3
DMI_IREF
DMI_RCOMP
PM_DRAM_PWRGD_R
PCH_BATLOW #
RESET_OUT#
PCH_RI#
SUSACK#_R
AC_PRESENT
PCH_PWROK
SIO_PWRBTN#_R
PM_APWROK_R
PCH_RSMRST#_RPCH_RSMRST#_Q
ME_SUS_PWR_ACK_R
SYS_RESET#
PCH_DPWROK PCH_RSMRST#_R
ME_SUS_PWR_ACK_R SUSACK#_R
SUS_STAT#/LPCPD#
PCH_RI#
ME_RESET#
SYS_RESET#
ME_RESET#
ME_SUS_PWR_ACK
CLKRUN#
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CSYNC
FDI_INT
FDI_IREF
FDI_RCOMP
DSW ODVREN
SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_S3#
SIO_SLP_A#
SUSCLK_R
PCH_DPWROK
PCH_PCIE_WAKE#
SIO_SLP_SUS#
SUS_STAT#/LPCPD#
SIO_SLP_LAN#
H_PM_SYNC
CLKRUN#
PCH_CRT_BLU
PCH_CRT_GRN
PCH_CRT_RED
PCH_CRT_DDC_CLK
PCH_CRT_DDC_DAT
HSYNC
VSYNC
CRT_IREF
PCI_PIRQA#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQB#
LCD_CBL_DET#
CAM_MIC_CBL_DET#
PCH_GPIO3
FFS_PCH_INT
PCH_PLTRST#
PCH_GPIO55
BBS_BIT1
LCD_CBL_DET#
CAM_MIC_CBL_DET#
PCH_GPIO3
PM_APWROK
PM_APWROK_R
PCH_GPIO55
ENVDD_PCH
PANEL_BKEN_PCH
BIA_PWM_PCH
BBS_BIT1
DSW ODVREN
PCH_PLTRST#
PCH_PLTRST#_EC
PCH_CRT_BLU
PCH_CRT_GRN
PCH_CRT_RED
SIO_SLP_WLAN#
ENVDD_PCH
FDI_CTX_PRX_N1
FDI_CTX_PRX_N0
DGPU_HOLD_RST#
DGPU_HOLD_RST#
SIO_SLP_A#
PCH_CRT_DDC_CLK
PCH_CRT_DDC_DAT
PCH_DDPD_CTRLCLK
PCH_DDPD_CTRLDATA
DGPU_PWR_EN
PCH_PCIE_WAKE#
SIO_SLP_LAN#
PCH_PCIE_WAKE#
PCH_DDPD_CTRLDATA
PCH_DDPD_CTRLCLK
PCH_DDPD_AUX
PCH_DDPD_AUX#
DPD_PCH_HPD
PCH_RSMRST#_Q
PCI_PIRQC#
PCI_PIRQA#
PCI_PIRQD#
PCI_PIRQB#
DGPU_PWR_EN
+1.5V_RUN
+1.5V_RUN
+PCH_VCCDSW 3_3
+3.3V_ALW_PCH
+3.3V_RUN
+3.3V_RUN
+1.5V_RUN
+1.5V_RUN
+3.3V_RUN
+3.3V_ALW2
+RTC_CELL
+3.3V_RUN
+PCH_VCCDSW 3_3
DMI_CTX_PRX_P0<6>
DMI_CTX_PRX_P3<6>
DMI_CRX_PTX_N0<6>
DMI_CTX_PRX_P1<6>
DMI_CTX_PRX_P2<6>
DMI_CRX_PTX_N2<6>
DMI_CRX_PTX_N1<6>
DMI_CTX_PRX_N1<6>
DMI_CTX_PRX_N0<6>
DMI_CRX_PTX_N3<6>
DMI_CRX_PTX_P0<6>
DMI_CTX_PRX_N3<6>
DMI_CTX_PRX_N2<6>
DMI_CRX_PTX_P3<6>
DMI_CRX_PTX_P2<6>
DMI_CRX_PTX_P1<6>
SIO_PWRBTN#<51>
SIO_PWRBTN#_R<18,7>
SUSACK#<51>
AC_PRESENT<51>
ME_SUS_PWR_ACK<51>
PCH_RSMRST#_Q<18,53>
PM_DRAM_PWRGD<7>
XDP_DBRESET#<18,7>
FDI_CTX_PRX_N0 <9>
FDI_CTX_PRX_N1 <9>
FDI_CTX_PRX_P0 <9>
FDI_CTX_PRX_P1 <9>
PCH_DPWROK <51>
PCH_PCIE_WAKE# <51>
SIO_SLP_S4# <41,51,54,57>
SIO_SLP_S3# <32,41,51,54>
SIO_SLP_S5# <32,41,51>
SIO_SLP_A# <41,51,54,58>
SIO_SLP_LAN# <39,51>
SIO_SLP_SUS# <51>
CLKRUN# <50,51>
PCH_CRT_BLU<35>
PCH_CRT_GRN<35>
PCH_CRT_RED<35>
PCH_CRT_HSYNC<35>
PCH_CRT_VSYNC<35>
PCH_CRT_DDC_DAT<35>
PCH_CRT_DDC_CLK<35>
LCD_CBL_DET# <30>
CAM_MIC_CBL_DET# <30>
HDD_FALL_INT <45>
PLTRST_LAN# <39>
PLTRST_USH# <41>
PLTRST_MMI# <49>
FDI_CSYNC <6>
FDI_INT <6>
H_PM_SYNC <7>
ENVDD_PCH<30,51>
PCH_PLTRST#_EC <41,42,43,50,51>
PCH_PLTRST#<18,7>
SIO_SLP_WLAN#<44,50>
PM_APWROK<51>
PLTRST_GPU# <17>
SYS_RESET# <41>
BIA_PWM_PCH<30>
PANEL_BKEN_PCH<30>
DGPU_HOLD_RST#<17>
PCH_DDPD_CTRLDATA <36>
PCH_DDPD_CTRLCLK <36>
DPD_PCH_HPD <36>
PCH_DDPD_AUX# <36>
PCH_DDPD_AUX <36>
PLTRST_TBT# <32>
DGPU_PWR_EN<17>
PCH_PWROK<61>
RESET_OUT#<11,18,51,7>
SUSCLK <42,43>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
PCH (2/9)
19 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
PCH (2/9)
19 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
PCH (2/9)
19 67Monday, January 13, 2014
Compal Electronics, Inc.
RH1488.2K_0402_5% @RH1488.2K_0402_5% @
12
RH1090_0402_5% @RH1090_0402_5% @
12
RH93 8.2K_0402_5%@RH93 8.2K_0402_5%@
1 2
RH115 150_0402_1%RH115 150_0402_1%
1 2
RH66@0_0402_5%RH66@0_0402_5%
1 2
T65 PAD~D@T65 PAD~D@
RH1290_0402_5% @RH1290_0402_5% @
12
T118 PAD~D @
T118 PAD~D @
RH80 10K_0402_5%@RH80 10K_0402_5%@
1 2
RH89 10K_0402_5%RH89 10K_0402_5%
1 2
UC3
74AHC1G09GW_TSSOP5~D
@UC3
74AHC1G09GW_TSSOP5~D
@
B
1
A
2
G
3
O4
P5
UH2
NL17SZ08DFT2G_SC70
UH2
NL17SZ08DFT2G_SC70
IN B
1
IN A
2OUT Y 4
VCC 5
GND
3
RH1140_0402_5% @RH1140_0402_5% @
12
RH105 0_0402_5%@RH105 0_0402_5%@
1 2
UH3
NL17SZ08DFT2G_SC70
UH3
NL17SZ08DFT2G_SC70
B
1
A
2
G
3
O4
P5
RH101 0_0402_5%@RH101 0_0402_5%@
1 2
RH259 0_0402_5%@RH259 0_0402_5%@
1 2
RH75 10K_0402_5%RH75 10K_0402_5%
1 2
CH12
0.1U_0402_25V7K
@CH12
0.1U_0402_25V7K
@
1 2
RH7710K_0402_5% RH7710K_0402_5%
12
T145 PAD~D @
T145 PAD~D @
LPT_PCH_M_EDS
DMI
Management
FDI
System Power
4 OF 11
UH1B
LPT_PCH_M_EDS
DMI
Management
FDI
System Power
4 OF 11
UH1B
TP21
AB10
TP10 AW44
TP16 AV43
TP12
AW17
TP17 AU42
TP7
AV17
TP5 AY45
TP13 AU44
SUSWARN#/SUSPWRNACK/GPIO30
J4
DMI_IREF
BE16
DMI_RCOMP
AY17
FDI_RCOMP AR44
SLP_WLAN#/GPIO29
D2
DRAMPWROK
H3
APWROK
AB7
PWROK
F10
SYS_RESET#
AM1
DMI_RXP_2
AR17
DMI_RXP_3
AW20
DMI_TXN_0
BD21
DMI_TXN_1
BE20
SLP_LAN# G5
PMSYNCH AY3
SLP_SUS# F1
SLP_A# F3
SLP_S3# H1
SLP_S4# C6
SLP_S5#/GPIO63 Y7
SUSCLK/GPIO62 Y6
SUS_STAT#/GPIO61 U7
CLKRUN# AN7
WAKE# K3
DPWROK L13
FDI_IREF AT45
FDI_CSYNC AL39
FDI_RXP_1 AL36
FDI_RXP_0 AJ36
FDI_RXN_1 AL35
FDI_RXN_0 AJ35
ACPRESENT/GPIO31
E6
SYS_PWROK
AD7
SUSACK#
R6
DMI_TXP_2
BB17
DMI_TXP_0
BB21
DMI_RXP_1
AP20
DMI_RXN_2
AP17
DMI_TXP_3
BC18
DMI_TXP_1
BC20
DMI_TXN_3
BE18 DMI_TXN_2
BD17
DMI_RXP_0
AY22
DMI_RXN_3
AV20
PWRBTN#
K1
RI#
N4
BATLOW#/GPIO72
K7
RSMRST#
J2
FDI_INT AL40
DSWVRMEN C8
DMI_RXN_1
AR20 DMI_RXN_0
AW22
TP15 AV45
RH100 7.5K_0402_1%RH100 7.5K_0402_1%
1 2
CH10
0.1U_0402_25V6K
@CH10
0.1U_0402_25V6K
@
1 2
RH330 10K_0402_5%RH330 10K_0402_5%
1 2
T130PAD~D @T130PAD~D @
RH91 0_0402_5%@RH91 0_0402_5%@
1 2
RH84 10K_0402_5%RH84 10K_0402_5%
1 2
RH112 8.2K_0402_5%RH112 8.2K_0402_5%
1 2
RH73 10K_0402_5%@RH73 10K_0402_5%@
1 2
T132PAD~D @T132PAD~D @
RH119
1K_0402_1%
@RH119
1K_0402_1%
@
12
PCI
DISPLAY
LVDSCRT
LPT_PCH_M_EDS
5 OF 11
UH1E
PCI
DISPLAY
LVDSCRT
LPT_PCH_M_EDS
5 OF 11
UH1E
EDP_BKLTCTL
N36
VGA_BLUE
T45
DAC_IREF
U40
VGA_IRTN
U39
EDP_BKLTEN
K36
EDP_VDDEN
G36
PIRQA#
H20
PIRQB#
L20
PIRQC#
K17
PIRQD#
M20
GPIO50
A12
GPIO52
B13
GPIO54
C12
GPIO51
C10
GPIO53
A10
GPIO55
AL6
DDPB_CTRLCLK R40
DDPB_CTRLDATA R39
DDPC_CTRLCLK R35
DDPC_CTRLDATA R36
DDPD_CTRLCLK N40
DDPD_CTRLDATA N38
DDPB_AUXN H45
DDPC_AUXN K43
DDPD_AUXN J42
DDPB_AUXP H43
DDPC_AUXP K45
DDPD_AUXP J44
DDPB_HPD K40
DDPC_HPD K38
DDPD_HPD H39
PIRQE#/GPIO2 G17
PIRQH#/GPIO5 M15
PME# AD10
PLTRST# Y11
PIRQG#/GPIO4 L15
PIRQF#/GPIO3 F17
VGA_VSYNC
N44
VGA_HSYNC
N42
VGA_DDC_DATA
M45
VGA_DDC_CLK
M43
VGA_RED
V45
VGA_GREEN
U44
R97 2.2K_0402_5%
@
R97 2.2K_0402_5%
@
1 2
RH76
1K_0402_1%
@RH76
1K_0402_1%
@
12
RH1100_0402_5% @RH1100_0402_5% @
12
T129 PAD~D @
T129 PAD~D @
T133PAD~D @T133PAD~D @
RH95 20_0402_1%RH95 20_0402_1%
1 2
RH79 0_0402_5%@RH79 0_0402_5%@
1 2
T134PAD~D @T134PAD~D @
RH118 100K_0402_5%RH118 100K_0402_5%
1 2
RH117 150_0402_1%RH117 150_0402_1%
1 2
RH96 0_0402_5%@RH96 0_0402_5%@
12
RH258 0_0402_5%@RH258 0_0402_5%@
1 2
RH90 8.2K_0402_5%RH90 8.2K_0402_5%
1 2
T131PAD~D @T131PAD~D @
RH98 0_0402_5%@RH98 0_0402_5%@
12
T141 PAD~D@T141 PAD~D@
RH94 20_0402_1%RH94 20_0402_1%
1 2
R126 2.2K_0402_5%R126 2.2K_0402_5%
1 2
RH87 0_0402_5%@RH87 0_0402_5%@
1 2
RH997.5K_0402_1% RH997.5K_0402_1%
12
RH8610K_0402_5% RH8610K_0402_5%
12
RH88 10K_0402_5%@RH88 10K_0402_5%@
1 2
T146 PAD~D @
T146 PAD~D @
R128 2.2K_0402_5%R128 2.2K_0402_5%
1 2
RH67
330K_0402_1%
RH67
330K_0402_1%
1 2
RH1110_0402_5% @RH1110_0402_5% @
12
RH104 0_0402_5%@RH104 0_0402_5%@
1 2
RPH1
8.2K_8P4R_5%
RPH1
8.2K_8P4R_5%
1 8
2 7
3 6
4 5
RH70 8.2K_0402_5%@RH70 8.2K_0402_5%@
12
T144 PAD~D@T144 PAD~D@
RH97 649_0402_1%RH97 649_0402_1%
1 2
RH8310K_0402_5% RH8310K_0402_5%
12
RH106 0_0402_5%@RH106 0_0402_5%@
12
R3731 0_0402_5%
@R3731 0_0402_5%
@
1 2
CH11
0.1U_0402_25V7K
@CH11
0.1U_0402_25V7K
@
1 2
T67 PAD~D@T67 PAD~D@
RH116 150_0402_1%RH116 150_0402_1%
1 2
R125 2.2K_0402_5%
@
R125 2.2K_0402_5%
@
1 2
RH78 10K_0402_5%RH78 10K_0402_5%
1 2
T66PAD~D @T66PAD~D @
RH81
330K_0402_1%
@RH81
330K_0402_1%
@
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCIECLK REQ Pull UP Power Rail:
SUS Rail : 0 3 4 5 6 7
Core Rail: 1 2
CLOCK TERMINATION for FCIM and need close to PCH
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
10/100/1G LAN
WLAN (M.2 card slot 1)
MMI
TBT
if can place closed or not suggest use 8P4R
WiGig (M.2 card slot 1)
M.2 card slot 2
M.2 card slot 3
Difference with Diesel
Remove CLK_PCI_TPM (C40),
JETWAY_CLK14M (F39)
Remove cap Remove cap
PEG_B_CLKRQ#
PCI_LOOPBACKOUT
PCI_MEC
PCI_5048
CLK_PCI_LOOPBACK
PCI_DOCK
CLK_PCI_MECCLK_PCI_5048
CLK_CPU_DMI
CLK_CPU_DMI#
CLK_BUF_DOT96
CLK_BUF_DOT96#
CLK_BUF_CKSSCD
CLK_BUF_CKSSCD#
CLK_BUF_DMI#
CLK_BUF_BCLK
CLK_BUF_DMI
CLK_BUF_BCLK#
CLK_PCH_14M
CLK_PCI_LOOPBACK
CLK_PCH_14M
CLK_80H
SIO_14M
ICLK_IREF
PCH_CLK_BIASREF
CLK_CPU_SSC_DPLL
CLK_CPU_SSC_DPLL#
CLK_CPU_DPLL
CLK_CPU_DPLL#
XTAL25_IN
CLK_PCIE_VGA
CLK_PCIE_VGA#
GFX_CLK_REQ#
PCIE_TBT
PCIE_TBT#
TBT_PCIECLK_REQ#
PCIE_WLAN
PCIE_WLAN#
WLANCLK_REQ#
PCIE_WIGIG
PCIE_WIGIG#
WIGIGCLK_REQ#
GFX_CLK_REQ#
CLK_PCI_LOOPBACK
CLK_BUF_DMI
CLK_BUF_DMI#
CLK_BUF_BCLK
CLK_BUF_BCLK#
CLK_BUF_DOT96#
CLK_BUF_DOT96
CLK_BUF_CKSSCD
CLK_BUF_CKSSCD#CARDCLK_REQ#
PCIE_CARD
PCIE_CARD#
LANCLK_REQ#
PCIE_LAN
PCIE_LAN#
NGFF2_CLK_REQ#
NGFF3_CLK_REQ#
XTAL25_OUT
CLK_PCI_DOCK CLK_SIO_14M CLK_PCI_LPDEBUG
+1.5V_RUN
+1.5V_RUN
+3.3V_ALW_PCH
+3.3V_ALW_PCH
+3.3V_ALW_PCH
+3.3V_ALW_PCH
+3.3V_ALW_PCH
+3.3V_ALW_PCH
+3.3V_RUN
+3.3V_RUN
+3.3V_ALW_PCH
+3.3V_ALW_PCH
CLK_PCI_MEC<51>
CLK_PCI_5048<50>
CLK_PCI_DOCK<48>
CLK_CPU_DMI# <7>
CLK_CPU_DMI <7>
CLK_SIO_14M <50>
CLK_PCI_LPDEBUG <51>
CLK_CPU_SSC_DPLL# <7>
CLK_CPU_SSC_DPLL <7>
CLK_CPU_DPLL# <7>
CLK_CPU_DPLL <7>
CLK_PCIE_VGA <17>
CLK_PCIE_VGA# <17>
CLK_PCIE_TBT<32>
CLK_PCIE_TBT#<32>
TBT_PCIECLK_REQ#<32>
CLK_PCIE_WLAN<42>
CLK_PCIE_WLAN#<42>
WLANCLK_REQ#<42>
CLK_PCIE_WIGIG<42>
CLK_PCIE_WIGIG#<42>
WIGIGCLK_REQ#<42>
3.3V_RUN_GFX_ON<44,50,54>
CARDCLK_REQ#<18,49>
CLK_PCIE_CARD<49>
CLK_PCIE_CARD#<49>
LANCLK_REQ#<18,39>
CLK_PCIE_LAN<39>
CLK_PCIE_LAN#<39>
CLK_PCIE_NGFF2<42>
CLK_PCIE_NGFF2#<42>
NGFF2_CLK_REQ#<42>
CLK_PCIE_NGFF3<43>
CLK_PCIE_NGFF3#<43>
NGFF3_CLK_REQ#<43>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
PCH (3/9)
20 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
PCH (3/9)
20 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
PCH (3/9)
20 67Monday, January 13, 2014
Compal Electronics, Inc.
RH162 22_0402_5%EMC@RH162 22_0402_5%EMC@ 12
RH128
10K_0402_5%
RH128
10K_0402_5%
1 2
RH152
0_0402_5%
RH152
0_0402_5%
12
LPT_PCH_M_EDS
CLOCK SIGNAL
2 OF 11
UH1C
LPT_PCH_M_EDS
CLOCK SIGNAL
2 OF 11
UH1C
PCIECLKRQ4#/GPIO26
V3 CLKOUT_PCIE_P_4
AF45
CLKOUT_PCIE_P_5
AE42
PCIECLKRQ5#/GPIO44
AA2
CLKOUT_PCIE_N_6
AB40
CLKOUT_PCIE_P_6
AB39
PCIECLKRQ6#/GPIO45
AE4
CLKOUT_PCIE_N_7
AJ44
CLKOUT_PCIE_P_7
AJ42
CLKOUTFLEX2/GPIO66 F36
CLKIN_SATA BE6
CLKIN_GND AR24
CLKIN_DMI AY24
PCIECLKRQ1#/GPIO18
AF1
CLKOUT_DP AJ40
CLKOUT_DMI AF39
CLKOUT_PCIE_N_0
Y43
CLKOUT_PCIE_P_0
Y45
CLKOUT_PEG_B Y39
CLKOUT_PEG_A AB35
PCIECLKRQ0#/GPIO73
AB1
CLKOUT_PEG_A_P AB36
PEGA_CLKRQ#/GPIO47 AF6
CLKOUT_PEG_B_P Y38
PEGB_CLKRQ#/GPIO56 U4
CLKOUT_PCIE_P_1
AA42
CLKOUT_PCIE_N_2
AB43
CLKOUT_ITPXDP
AH43
XTAL25_IN AM43
XTAL25_OUT AL44
CLKOUTFLEX0/GPIO64 C40
CLKOUTFLEX1/GPIO65 F38
DIFFCLK_BIASREF AN44
ICLK_IREF AM45
CLKOUTFLEX3/GPIO67 F39
CLKIN_33MHZLOOPBACK D17
REFCLK14IN F45
CLKIN_SATA_P BC6
CLKIN_DOT96P G33
CLKIN_DOT96N H33
CLKIN_GND_P AT24
CLKIN_DMI_P AW24
CLKOUT_DP_P AJ39
CLKOUT_DMI_P AF40
CLKOUT_PCIE_N_1
AA44
PCIECLKRQ7#/GPIO46
Y3
CLKOUT_ITPXDP_P
AH45
CLKOUT_33MHZ1
E44
CLKOUT_33MHZ0
D44
CLKOUT_33MHZ2
B42
CLKOUT_33MHZ3
F41
CLKOUT_33MHZ4
A40
CLKOUT_PCIE_N_4
AF43
CLKOUT_PCIE_N_3
AD43
CLKOUT_PCIE_P_3
AD45
PCIECLKRQ3#/GPIO25
T3
CLKOUT_PCIE_N5
AE44
CLKOUT_DPNS_P AF36
CLKOUT_DPNS AF35
PCIECLKRQ2#/GPIO20/SMI#
AF3
CLKOUT_PCIE_P_2
AB45
TP19 AD39
TP18 AD38 T148PAD~D @T148PAD~D @
RH13010K_0402_5% RH13010K_0402_5%
12
RH167 10K_0402_5%RH167 10K_0402_5%
1 2
RH145 10K_0402_5%RH145 10K_0402_5%
12
RH124 10K_0402_5%RH124 10K_0402_5%
12
RH82 0_0402_5%@RH82 0_0402_5%@12
RH160 22_0402_5%EMC@RH160 22_0402_5%EMC@ 12
CH79
12P_0402_50V8J
CH79
12P_0402_50V8J
1
2
CH83
12P_0402_50V8J
CH83
12P_0402_50V8J
1
2
RH122 0_0402_5%@RH122 0_0402_5%@12
RH125 10K_0402_5%RH125 10K_0402_5%
12
RH127 0_0402_5%@RH127 0_0402_5%@12
RH137 0_0402_5%@RH137 0_0402_5%@12
RH144 0_0402_5%@RH144 0_0402_5%@12
RH150 10K_0402_5%RH150 10K_0402_5%
1 2
CH15
10P_0402_50V8J
@
CH15
10P_0402_50V8J
@
1
2
RH139 0_0402_5%@RH139 0_0402_5%@12
RH142 0_0402_5%@RH142 0_0402_5%@12
RH126 0_0402_5%@RH126 0_0402_5%@12
RH158 22_0402_5%EMC@RH158 22_0402_5%EMC@ 12
RH146 10K_0402_5%RH146 10K_0402_5%
1 2
RH1630_0402_5% @RH1630_0402_5% @
1 2
T147PAD~D @T147PAD~D @
RH1657.5K_0402_1% RH1657.5K_0402_1%
1 2
RPH3
10K_8P4R_5%
RPH3
10K_8P4R_5%
1 8
2 7
3 6
4 5
RH169 10K_0402_5%RH169 10K_0402_5%
1 2
RH123 10K_0402_5%RH123 10K_0402_5%
12
RH121 0_0402_5%@RH121 0_0402_5%@12
RH153 1M_0402_5%RH153 1M_0402_5%
1 2
RH164 22_0402_5%EMC@RH164 22_0402_5%EMC@ 12
CH14
12P_0402_50V8J
CH14
12P_0402_50V8J
1
2
RH151 10K_0402_5%RH151 10K_0402_5%
1 2
RH329 10K_0402_5%RH329 10K_0402_5%
12
RH147 10K_0402_5%RH147 10K_0402_5%
12
RH159 22_0402_5%EMC@RH159 22_0402_5%EMC@ 12
RH157 22_0402_5%EMC@RH157 22_0402_5%EMC@ 12
RH92 0_0402_5%@RH92 0_0402_5%@12
RH120 10K_0402_5%RH120 10K_0402_5%
1 2
CH76
12P_0402_50V8J
CH76
12P_0402_50V8J
1
2
YH2
25MHZ_10PF_Q22FA2380049900
YH2
25MHZ_10PF_Q22FA2380049900
IN 1
GND 2
OUT
3
GND
4
CH13
12P_0402_50V8J
CH13
12P_0402_50V8J
1
2
CH77
10P_0402_50V8J
@CH77
10P_0402_50V8J
@
1
2
RH140 10K_0402_5%RH140 10K_0402_5%
12
G
D
S
QH3
L2N7002WT1G_SC-70-3
G
D
S
QH3
L2N7002WT1G_SC-70-3
2
13
CH16
12P_0402_50V8J
CH16
12P_0402_50V8J
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
200 MIL SO8
64Mb Flash ROM
32Mb Flash ROM
200 MIL SO8
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
CIS LINK OK
CIS LINK OK
remove SPI_WP#_SEL
remove SPI_WP#_SEL
Remove TEMP_ALERT#.
CIS link OK
Intel request.
PU to always power
SPI_CLK64
SPI_DO64 SPI_PCH_DO
SPI_PCH_CLK
SPI_PCH_DO
SPI_PCH_CLKSPI_CLK32
SPI_DO32
MEM_SMBCLK
MEM_SMBDATA
PCH_SMB_ALERT#
LAN_SMBCLK
LAN_SMBDATA
DDR_HVREF_RST_PCH
SML1_SMBCLK
SML1_SMBDATA
PCH_CL_RST1#
PCH_CL_CLK1
PCH_CL_DATA1
MEM_SMBDATA
LAN_SMBCLK
LAN_SMBDATA
MEM_SMBCLK
PCH_TD_IREF
IRQ_SERIRQ
PCH_SPI_DIN
PCH_SPI_CLK
PCH_SPI_DO
PCH_SPI_CS1#
PCH_SPI_CS0#
SPI_PCH_CS1#
SPI_PCH_CLK
SPI_PCH_DIN
SPI_PCH_DO
SPI_PCH_CS0#
PCH_SPI_DO2
SPI_PCH_DO2
PCH_SPI_DO3
SPI_PCH_DO3
SPI_PCH_DO2_64
SPI_PCH_DO2_32
SPI_PCH_DO3_64
SPI_PCH_DO3_32
SPI_PCH_DO3SPI_PCH_DO3_32
SPI_PCH_DO3SPI_PCH_DO3_64
PCH_SMB_ALERT#
DDR_HVREF_RST_PCH
PCH_SPI_CS1#
PCH_SPI_DO
PCH_SPI_DO3
PCH_SPI_DIN
LPC_LAD3
PCH_SPI_DO2
LPC_LAD1
LPC_LFRAME#
PCH_SPI_CLK
LPC_LAD2
IRQ_SERIRQ
PCH_SPI_CS0#
LPC_LDRQ1#
LPC_LAD0
SPI_CLK64SPI_CLK32
SPI_PCH_DO2_64SPI_PCH_DO2
SPI_PCH_DIN SPI_DIN64
SPI_PCH_CS0# SPI_PCH_CS0#_R
SPI_PCH_DO2
SPI_DIN32SPI_PCH_DIN
SPI_PCH_CS1# SPI_PCH_CS1#_R
SPI_PCH_DO2_32
MEM_SMBCLK
MEM_SMBDATA
SML1_SMBCLK
SML1_SMBDATA
PCH_SPI_CS2#
GPIO74
GPIO74
+3.3V_SPI
+3.3V_SPI
+3.3V_ALW_PCH
+3.3V_RUN
+3.3V_RUN
+3.3V_M
+3.3V_SPI
+3.3V_SPI
+3.3V_SPI
LPC_LAD0<50,51>
LPC_LAD1<50,51>
LPC_LAD2<50,51>
LPC_LAD3<50,51>
LPC_LDRQ1#<50>
PCH_CL_DATA1 <42>
PCH_CL_CLK1 <42>
PCH_CL_RST1# <42>
SML1_SMBDATA <51>
LAN_SMBDATA <39>
LAN_SMBCLK <39>
SML1_SMBCLK <51>
DDR_XDP_WAN_SMBDAT <13,14,15,16,18,45>
DDR_XDP_WAN_SMBCLK <13,14,15,16,18,45>
LPC_LFRAME#<50,51>
IRQ_SERIRQ<50,51>
DDR_HVREF_RST_PCH <13,15,7>
PCH_SPI_CLK<41>
PCH_SPI_CS2#<41>
PCH_SPI_DO<41>
PCH_SPI_DIN<41>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
PCH (4/9)
21 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
PCH (4/9)
21 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
PCH (4/9)
21 67Monday, January 13, 2014
Compal Electronics, Inc.
R3667 33_0402_5%R3667 33_0402_5%
1 2
T121PAD~D @T121PAD~D @
RH1790_0402_5% RH1790_0402_5%
12
R897 33_0402_5%EMC@R897 33_0402_5%EMC@ 1 2
R3664 1K_0402_5%R3664 1K_0402_5%
1 2
RH33110K_0402_5% RH33110K_0402_5%
12
CE1
27P_0402_50V8J
@
CE1
27P_0402_50V8J
@
1
2
R3668 1K_0402_5%R3668 1K_0402_5%
1 2
R3670 33_0402_5%R3670 33_0402_5%
1 2
RH168 10K_0402_5%RH168 10K_0402_5%
1 2
RPH5
2.2K_0804_8P4R_5%
RPH5
2.2K_0804_8P4R_5%
1 8
2 7
3 6
4 5
R936 47_0402_5%R936 47_0402_5%
1 2
R7 47_0402_5%R7 47_0402_5%
1 2
JSPI1
CONN@
E-T_6712K-Y20N-07L
JSPI1
CONN@
E-T_6712K-Y20N-07L
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
GND1
21
GND2
22
C1216
0.1U_0402_25V6K
C1216
0.1U_0402_25V6K
1 2
RH1770_0402_5% RH1770_0402_5%
12
RH1820_0402_5% RH1820_0402_5%
12
R8 33_0402_5%R8 33_0402_5%
1 2
RH185 0_0402_5%RH185 0_0402_5%
12
T120PAD~D @T120PAD~D @
U53
W25Q32FVSSIQ_SO8
U53
W25Q32FVSSIQ_SO8
CLK 6
GND
4DI/IO0 5
DO/IO1
2
/WP/IO2
3
VCC 8
/HOLD/IO3 7
/CS
1
T149PAD~D @T149PAD~D @
R9 33_0402_5%R9 33_0402_5%
1 2
RH1840_0402_5% RH1840_0402_5%
12
T150PAD~D @T150PAD~D @
U52
W25Q64FVSSIQ_SO8
U52
W25Q64FVSSIQ_SO8
CLK 6
GND
4DI(IO0) 5
DO(IO1)
2
/WP(IO2)
3
VCC 8
/HOLD(IO3) 7
/CS
1
RH1830_0402_5% RH1830_0402_5%
12
RH1780_0402_5% RH1780_0402_5%
12
RE2
33_0402_5%
@
RE2
33_0402_5%
@
12
RH16610K_0402_5% RH16610K_0402_5%
12
QH4A
DMN66D0LDW-7_SOT363-6
QH4A
DMN66D0LDW-7_SOT363-6
6 1
2
RH174499_0402_1% RH174499_0402_1% 12
RH176 8.2K_0402_1%RH176 8.2K_0402_1%
1 2
RH1810_0402_5% RH1810_0402_5%
12
C746
0.1U_0402_25V6K
C746
0.1U_0402_25V6K
1 2
RH175499_0402_1% RH175499_0402_1% 12
R901 33_0402_5%R901 33_0402_5%
1 2
R3666 1K_0402_5%R3666 1K_0402_5%
1 2
RH1701K_0402_1% RH1701K_0402_1%
12
R899 33_0402_5%EMC@R899 33_0402_5%EMC@ 1 2
R3665 1K_0402_5%R3665 1K_0402_5%
1 2
CE2
27P_0402_50V8J
@
CE2
27P_0402_50V8J
@
1
2
QH4B
DMN66D0LDW-7_SOT363-6
QH4B
DMN66D0LDW-7_SOT363-6
3
5
4
R3669 33_0402_5%R3669 33_0402_5%
1 2
RE1
33_0402_5%
@
RE1
33_0402_5%
@
12
R895 33_0402_5%R895 33_0402_5%
1 2
LPT_PCH_M_EDS
SMBus
C-Link
Thermal
SPI
LPC
3 OF 11
UH1D
LPT_PCH_M_EDS
SMBus
C-Link
Thermal
SPI
LPC
3 OF 11
UH1D
SML1ALERT#/PCHHOT#/GPIO74 H6
SPI_IO3
AJ2
SPI_MISO
AH3
SPI_IO2
AJ4
SPI_MOSI
AH1
SPI_CS2#
AJ10
SPI_CS1#
AL7
SPI_CS0#
AJ7
SPI_CLK
AJ11
LDRQ1#/GPIO23
G20
SERIRQ
AL11
LDRQ0#
D21
LFRAME#
B21
LAD_3
C18
LAD_2
A18
LAD_1
C20
LAD_0
A20
TD_IREF AY43
CL_DATA AF10
CL_RST# AF7
CL_CLK AF11
SML1DATA/GPIO75 N11
SML1CLK/GPIO58 K6
SML0DATA R7
SML0CLK U8
SML0ALERT#/GPIO60 N8
SMBDATA U11
SMBCLK R10
SMBALERT#/GPIO11 N7
TP2 BC45
TP4 BE43
TP1 BA45
TP3 BE44
R900 33_0402_5%R900 33_0402_5%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
----->MLK DOCK
----->USH
----->M.2 Slot-1 (WLAN/BT/WiGig)
----->MLK DOCK
----->Right Side
----->Left Side JUSB3
----->M.2 Slot-2 (WWAN/LTE/HCA)
CAD NOTE:
Route single-end 50-ohms and max 500-mils length.
Avoid routing next to clock pins or under stitching capacitors.
Recommended minimum spacing to other signal traces is 15 mils.
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
----->Left Side JUSB1
WIGIG
----->Right Side
----->Left Side JUSB3
----->Left Side JUSB1
----->Left Side JUSB2
PN change to SD30910020L
PN change to SD30910020L
----->Left Side JUSB2
TBT-2
TBT-1
WLAN
----->Camera
----->M.2 Slot-3 (SSD/HCA/Cache)
----->Touch Screen
10/100/1G LAN
MLK DOCK
MMI
USB3RN2
USB3RP2
USB3TN2
USB3TP2
USB3RN1
USB3RP1
USB3TN1
USB3TP1
SIO_EXT_SMI#
USB_OC4#_R
USB_OC2#
USB_OC3#
USB_OC5#
USB_OC6#
USB_OC0#_R
USB_OC1#_R
USBP9+
USBP0-
USBP0+
USBP3+
USBP5+
USBP7+
USBP3-
USBP1-
USBP9-
USBP5-
USBP7-
USBP4-
USBP2+
USBP4+
USBP2-
USBP1+
USBP6+
USBP6-
USBRBIAS
PCH_PCIE_IREF
PCH_PCIE_RCOMP
USBRBIAS
PCIE_PRX_WIGIGTX_P8
PCIE_PRX_WIGIGTX_N8
PCIE_PTX_WIGIGRX_N8
PCIE_PTX_WIGIGRX_P8
USB3RN6
USB3TN6
USB3RP6
USB3TP6
USB3RP3
USB3RN3
USB3TN3
USB3TP3
USB3RN5
USB3TN5
USB3RP5
USB3TP5
PCIE_PRX_TBTX_P6
PCIE_PTX_TBRX_P6
PCIE_PTX_TBRX_N6
PCIE_PRX_TBTX_N6
PCIE_PRX_TBTX_N5
PCIE_PRX_TBTX_P5
PCIE_PTX_TBRX_P5
PCIE_PTX_TBRX_N5
PCIE_PRX_WLANTX_N7
PCIE_PTX_WLANRX_P7
PCIE_PTX_WLANRX_N7
PCIE_PRX_WLANTX_P7
USB_OC5#
USB_OC2#
USB_OC1#_R
USB_OC0#_R
USB_OC4#_R
USB_OC3#
USB_OC6#
SIO_EXT_SMI#
USBP8+
USBP8-
USBP10+
USBP10-
USBP11+
USBP11-
PCIE_PRX_GLANTX_P3
PCIE_PTX_GLANRX_N3
PCIE_PRX_GLANTX_N3
PCIE_PTX_GLANRX_P3
PCIE_PRX_MMITX_P4
PCIE_PRX_MMITX_N4
PCIE_PTX_MMIRX_P4
PCIE_PTX_MMIRX_N4
+3.3V_ALW_PCH
+1.5V_RUN
+1.5V_RUN
USB3RN1 <49>
USB3RN2 <47>
USB3RP2 <47>
USB3TN2 <47>
USB3TP2 <47>
USB3RP1 <49>
USB3TN1 <49>
USB3TP1 <49>
USBP4+ <42>
USBP5- <42>
USBP3+ <48>
USBP5+ <42>
USBP4- <42>
USBP3- <48>
USBP2+ <49>
USBP2- <49>
USBP1+ <47>
USBP1- <47>
USBP0- <49>
USBP0+ <49>
USBP7+ <41>
USBP7- <41>
USBP9+ <49>
USBP9- <49>
USB_OC0# <47>
USBP6- <48>
USBP6+ <48>
USB_OC1# <49>
USB_OC0#_R <18>
USB_OC1#_R <18>
USB_OC2# <18,49>
USB_OC3# <18>
USB_OC4# <49>
USB_OC5# <18>
USB_OC6# <18>
SIO_EXT_SMI# <18,51>
USB_OC4#_R <18>
PCIE_PTX_WIGIGRX_N8<42>
PCIE_PRX_WIGIGTX_P8<42>
PCIE_PTX_WIGIGRX_P8<42>
PCIE_PRX_WIGIGTX_N8<42>
USB3RN6 <49>
USB3RP6 <49>
USB3TN6 <49>
USB3TP6 <49>
USB3RN5 <49>
USB3RP5 <49>
USB3TN5 <49>
USB3TP5 <49>
PCIE_PRX_TBTX_N6<32>
PCIE_PTX_TBRX_P6<32>
PCIE_PTX_TBRX_N6<32>
PCIE_PRX_TBTX_P6<32>
PCIE_PRX_TBTX_P5<32>
PCIE_PRX_TBTX_N5<32>
PCIE_PTX_TBRX_P5<32>
PCIE_PTX_TBRX_N5<32>
USB3RN3<48>
USB3RP3<48>
USB3TN3<48>
USB3TP3<48>
PCIE_PRX_WLANTX_P7<42>
PCIE_PRX_WLANTX_N7<42>
PCIE_PTX_WLANRX_N7<42>
PCIE_PTX_WLANRX_P7<42>
USBP8- <30>
USBP8+ <30>
USBP10+ <43>
USBP10- <43>
USBP11+ <30>
USBP11- <30>
PCIE_PTX_GLANRX_N3<39>
PCIE_PRX_GLANTX_P3<39>
PCIE_PTX_GLANRX_P3<39>
PCIE_PRX_GLANTX_N3<39>
PCIE_PRX_MMITX_N4<49>
PCIE_PRX_MMITX_P4<49>
PCIE_PTX_MMIRX_P4<49>
PCIE_PTX_MMIRX_N4<49>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
PCH (5/9)
22 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
PCH (5/9)
22 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
PCH (5/9)
22 67Monday, January 13, 2014
Compal Electronics, Inc.
T123PAD~D @T123PAD~D @RH188 0_0402_5%@RH188 0_0402_5%@
1 2
RH191 0_0402_5%@RH191 0_0402_5%@1 2
T122PAD~D @T122PAD~D @
RH192 7.5K_0402_1%RH192 7.5K_0402_1%
1 2
T125 PAD~D@T125 PAD~D@
RPH7
10K_8P4R_5%
RPH7
10K_8P4R_5%
1 8
2 7
3 6
4 5
T124 PAD~D@T124 PAD~D@
LPT_PCH_M_EDS
USB
PCIe
9 OF 11
UH1I
LPT_PCH_M_EDS
USB
PCIe
9 OF 11
UH1I
USB3TP6 BE28
USB3TN6 BD27
USB3RP6 AP29
USB3RN6 AR29
USB3TP5 BC26
USB3TN5 BE26
USB3RP5 AV29
USB3RN5 AW29
PETP1/USB3TP3
BC32
PERP2/USB3RP4
AR31
PETP2/USB3TP4
BB33
USB3TP2 BC24
PETN2/USB3TN4
BD33
PERN2/USB3RN4
AT31
PETN1/USB3TN3
BE32
PERP1/USB3RP3
AY31 PERN1/USB3RN3
AW31
PERN_3
AW33
PERP_3
AY33
PETN_3
BE34
PETN_4
BE36
PERN_5
AW36
PERP_5
AV36
PETN_5
BD37
PERP_6
AW38
PETN_6
BC38
PERN_7
AT40
USB2N13 F24
USB2P13 G24
USB2N12 G26
USB2P12 F26
USB2P11 C28
USB2N11 A28
USB2P10 D29
USB2P9 C30
USB2N10 B29
USB2N9 A30
USB2P8 C32
USB2N8 A32
USB2N7 G29
USB2P7 H29
USB2P6 L31
USB2N6 K31
USB2P5 G31
USB2P4 D33
USB2N5 F31
USB2N4 B33
USB2P3 C34
USB2N3 A34
USB2P2 C36
USB2N2 A36
USB2P1 C38
USB2N1 A38
USB2P0 D37
USB2N0 B37
PETP_8
BD41
PCIE_IREF
BE30
PCIE_RCOMP
BD29
PETP_3
BC34
PERN_4
AT33
PERP_4
AR33
PETP_4
BC36
PETP_5
BB37
PERN_6
AY38
PETP_6
BE38
PERP_7
AT39
PETN_7
BE40
PETP_7
BC40
PERN_8
AN38
PERP_8
AN39
PETN_8
BD42
USB3RN1 AR26
USB3RP1 AP26
USB3TN1 BE24
USB3TP1 BD23
USB3RN2 AW26
USB3RP2 AV26
USB3TN2 BD25
USBRBIAS# K24
USBRBIAS K26
OC0#/GPIO59 P3
OC1#/GPIO40 V1
OC2#/GPIO41 U2
OC3#/GPIO42 P1
OC4#/GPIO43 M3
OC5#/GPIO9 T1
OC6#/GPIO10 N2
OC7#/GPIO14 M1
TP23 L33
TP6
BB29
TP11
BC30
TP24 M33
RH187
22.6_0402_1%
RH187
22.6_0402_1%
12
RPH6
10K_8P4R_5%
RPH6
10K_8P4R_5%
1 8
2 7
3 6
4 5
RH189 0_0402_5%@RH189 0_0402_5%@1 2
RH190 0_0402_5%@RH190 0_0402_5%@1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
ENABLED - HIGH(DEFAULT)
DISABLED - LOW
PLL ON DIE VR ENABLE
SATA2GP/GPIO36 , SATA3GP/GPIO37 SAMPLED AT RISING EDGE OF PWROK.
WEAK INTERNAL PULL-DOWN.(WEAK INTERNAL PULL-DOWN IS DISABLED AFTER
PLRST_N DE-ASSERTS).
NOTE: THIS SIGNAL SHOLD NOT BE PULLED HIGH WHEN STRAP IS SAMPLED.
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Support Deep S3 mode
Fixed Signals Muxed
Signals Fixed Signals Muxed
Signals Fixed Signals
USB3
1
USB3
2
USB3
5
USB3
6
USB3
3
USB3
4
PCIE
1
PCIE
2
PCIE
3
PCIE
4
PCIE
5
PCIE
6
PCIE
7
PCIE
8
SATA
4
SATA
5
PCIE
1
PCIE
2
SATA
0
SATA
1
SATA
2
SATA
3
(00) (00) (00) (00)
(01) (01) (01) (01)
GPIO16 GPIO49
0: PCIE1 0: PCIE2
1: SATA4 1: SATA5
00b or 01b: Assign muxed signal to desired port
10b: Reserved
11b: Assign desired port based on GPIO
Note: GPIO strap option is only
available for SATA/PCIE muxed
signals to support
mSATA/mini PCIE port switching
difference with Diesel
Remove SIO_A20GATE
difference with Diesel
Remove SLP_ME_CSW_DEV#
Remove SLP_ME_CSW_DEV#
change from EC wake# to
LAN_wake#
Remove 0.1uF cap from PCH_AV1
Remove 56 ohm from PCH_AV1
HSW_BDW compatibility CKT
RH206 X
HSW BDW
V
for TBT GPIO pin
for TBT GPIO pin
Remove TBT_CIO_PLUG_EVENT#,
due to double PU.
TPM_ID1
TBT_CIO_PLUG_EVENT#
TBT_FORCE_PWR
USH_DET#
SATA4_PCIE1#
SIO_EXT_WAKE#
PCH_GPIO35
PM_LANPHY_ENABLE
TPM_PIRQ#
PCH_GPIO24
TPM_ID0
FFS_INT2
KB_DET#
KB_DET#
PCH_GPIO36
CONTACTLESS_DET#
PCH_GPIO71
H_CPUPWRGD
SIO_RCIN#
CPU_PLTRST#
TP_VSS_NCTF
SIO_EXT_WAKE#
PCH_GPIO36
SSD_SATA5_PCIE2#
PCH_GPIO36
SSD_SATA5_PCIE2#
MXM_PRESENTL#
PCH_GPIO69
SATA4_PCIE1#
SATA4_PCIE1#
HDD2_DET#
HDD2_DET#
TPM_ID1
PCH_GPIO24
PM_LANPHY_ENABLE
PCH_GPIO34
MXM_PRESENTR#
HDD2_DET#
PCH_GPIO35
SIO_RCIN#
TPM_PIRQ#
TPM_ID0
PCH_GPIO34
SIO_EXT_SCI#
PCH_GPIO71
USH_DET#
MXM_PRESENTR#
PCH_GPIO69
CONTACTLESS_DET#
MXM_PRESENTL#
H_THERMTRIP#_PCH
SSD_SATA5_PCIE2#
H_THERMTRIP#H_THERMTRIP#_PCH
LAN_WAKE#
+3.3V_RUN
+3.3V_ALW_PCH
+3.3V_RUN
+3.3V_RUN
+PCH_VCCDSW3_3
+1.05V_RUN
PM_LANPHY_ENABLE<39>
SIO_EXT_SCI#<51>
PCH_GPIO35<18>
FFS_INT2<45>
KB_DET#<53>
SIO_EXT_WAKE#<18,51>
PCH_GPIO36<18>
USH_DET#<41>
CONTACTLESS_DET#<41>
H_CPUPWRGD <7>
SIO_RCIN# <51>
CPU_PLTRST# <7>
SATA4_PCIE1#<18,50>
MXM_PRESENTL#<17>
DGPU_PWROK<17,50>
MXM_PRESENTR#<17>
TPM_PIRQ#<41>
HDD2_DET#<18,45>
SSD_SATA5_PCIE2#<18,51>
LAN_WAKE#<39,51>
H_THERMTRIP# <51,7>
TBT_CIO_PLUG_EVENT#<32>
TBT_FORCE_PWR<32>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
PCH (6/9)
23 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
PCH (6/9)
23 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
PCH (6/9)
23 67Monday, January 13, 2014
Compal Electronics, Inc.
RH224 10K_0402_5%RH224 10K_0402_5%
1 2
RH195 0_0402_5%@RH195 0_0402_5%@
1 2
RPH10
10K_8P4R_5%
RPH10
10K_8P4R_5%
1 8
2 7
3 6
4 5
RH231 10K_0402_5%@RH231 10K_0402_5%@
12
RH206 1K_0402_1%~DBDW@RH206 1K_0402_1%~DBDW@
1 2
RH230 10K_0402_5%RH230 10K_0402_5%
12
RH219 0_0402_5%@RH219 0_0402_5%@
1 2
RH225 10K_0402_5%RH225 10K_0402_5%
12
RH229 1K_0402_1%RH229 1K_0402_1%
12
LPT_PCH_M_EDS
NCTF
CPU/Misc
GPIO
6 OF 11
UH1F
LPT_PCH_M_EDS
NCTF
CPU/Misc
GPIO
6 OF 11
UH1F
TACH6/GPIO70
G13
TACH7/GPIO71
H15
VSS BA1
VSS BC1
VSS N10
VSS A2
VSS BD45
VSS BD2
VSS BD44
VSS BD1
VSS B45
VSS B2
VSS B1
VSS A44
VSS A41
LAN_PHY_PWR_CTRL/GPIO12
K13
GPIO15
AB11
VSS A43
VSS A4
VSS E45
VSS E1
VSS D1
VSS BE3
VSS BE2
TACH4/GPIO68
C16
GPIO57
U12
SDATAOUT1/GPIO48
AN4
GPIO35/NMI#
AP1
GPIO28
AD11
GPIO34
AN6
GPIO27
R11
GPIO24
Y10
SCLOCK/GPIO22
BB4
TACH3/GPIO7
G15
TACH1/GPIO1
F13
PLTRST_PROC# AU4
THRMTRIP# AV1
PROCPWRGD AV3
RCIN# AT6
PECI AY1
SATA5GP/GPIO49
AK3
VSS B44
TACH5/GPIO69
D13
SATA3GP/GPIO37
AK1
SATA2GP/GPIO36
AT3
VSS
A5 VSS
C45 VSS
BE5 VSS
BE41
SDATAOUT0/GPIO39
AM3
SLOAD/GPIO38
AT7
TACH0/GPIO17
C14
SATA4GP/GPIO16
AN2
GPIO8
Y1
TACH2/GPIO6
A14
BMBUSY#/GPIO0
AT8
TP14 AN10
RH172 390_0402_5%RH172 390_0402_5%
1 2
RPH9
10K_8P4R_5%
RPH9
10K_8P4R_5%
1 8
2 7
3 6
4 5
T126PAD~D @T126PAD~D @
RH213 10K_0402_5%RH213 10K_0402_5%
12
RH200 20K_0402_5%RH200 20K_0402_5%
1 2
RPH8
10K_8P4R_5%
RPH8
10K_8P4R_5%
1 8
2 7
3 6
4 5
RH228 1K_0402_1%@RH228 1K_0402_1%@
12
RH216 10K_0402_5%RH216 10K_0402_5%
12
RH227 10K_0402_5%@RH227 10K_0402_5%@
12
RH212 10K_0402_5%RH212 10K_0402_5%
12
RH210 10K_0402_5%RH210 10K_0402_5%
12
RH226 10K_0402_5%@RH226 10K_0402_5%@
12
RH208 10K_0402_5%RH208 10K_0402_5%
12
RH217 10K_0402_5%RH217 10K_0402_5%
12
RH214 10K_0402_5%RH214 10K_0402_5%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
PCH Power Rail Table
Voltage Rail Voltage S0 Iccmax Current (A)
VCC 1.05V 1.29 A
VCCIO 1.05V 3.629 A
VCCADAC1_5 1.5V 0.070 A
VCCADAC3_3 0.0133 A3.3V
VCCCLK 0.306 A1.05V
VCCCLK3_3 0.055 A3.3V
VCCVRM 0.179 A1.5V
VCC3_3 3.3V 0.133 A
VCCASW 1.05V 0.67 A
VCCSUSHDA 3.3V 0.01 A
VCCSPI 3.3V 0.022 A
VCCSUS3_3 3.3V 0.261 A
VCCDSW3_3 3.3V 0.015 A
V_PROC_IO 1.05V 0.004 A
+PCH_VCCDSW
+VCCADAC
+PCH_USB_DCPSUS1
+PCH_VCCDSW_R
+PCH_VCCDSW
+PCH_USB_DCPSUS3
+PCH_USB_DCPSUS3
+PCH_USB_DCPSUS1
+3.3V_RUN
+1.05V_RUN
+1.05V_RUN
+1.05V_RUN
+1.05V_M
+1.5V_RUN
+1.05V_RUN
+1.05V_M
+1.5V_RUN
+1.5V_RUN
+1.05V_M
+3.3V_RUN
+3.3V_ALW_PCH
+1.5V_RUN
+1.5V_RUN
+1.05V_RUN
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
PCH (7/9)
24 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
PCH (7/9)
24 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
PCH (7/9)
24 67Monday, January 13, 2014
Compal Electronics, Inc.
+
CH60
330U_SX_2VY
@
+
CH60
330U_SX_2VY
@
1
2
CH20
10U_0603_6.3VAM
CH20
10U_0603_6.3VAM
1
2
CH25
1U_0402_6.3VAK
CH25
1U_0402_6.3VAK
1
2
CH19
0.1U_0402_10V7K
CH19
0.1U_0402_10V7K
1
2
RH2340_0402_5% @RH2340_0402_5% @
12
CH37
1U_0402_6.3VAK
CH37
1U_0402_6.3VAK
1
2
CH30
1U_0402_6.3VAK
CH30
1U_0402_6.3VAK
1
2
CH38
10U_0603_6.3V6M
CH38
10U_0603_6.3V6M
1
2
RH232 5.11_0402_1%RH232 5.11_0402_1%
1 2
LH1
BLM18PG181SN1D_2P
LH1
BLM18PG181SN1D_2P
12
CH24
1U_0402_6.3VAK
CH24
1U_0402_6.3VAK
1
2
CH35
1U_0402_6.3VAK
CH35
1U_0402_6.3VAK
1
2
CH29
1U_0402_6.3VAK
CH29
1U_0402_6.3VAK
1
2
CH22
1U_0402_6.3VAK
CH22
1U_0402_6.3VAK
1
2
CH21
10U_0603_6.3VAM
CH21
10U_0603_6.3VAM
1
2
CH28
22U_0805_6.3VAM
CH28
22U_0805_6.3VAM
1
2
CH23
1U_0402_6.3VAK
CH23
1U_0402_6.3VAK
1
2
CH33
10U_0603_6.3VAM
@CH33
10U_0603_6.3VAM
@
1
2
CH31
10U_0603_6.3VAM
@CH31
10U_0603_6.3VAM
@
1
2
CH36
1U_0402_6.3VAK
CH36
1U_0402_6.3VAK
1
2
CH18
0.01U_0402_16V7K
CH18
0.01U_0402_16V7K
1
2
CH32
10U_0603_6.3VAM
@CH32
10U_0603_6.3VAM
@
1
2
CH26
10U_0603_6.3VAM
@CH26
10U_0603_6.3VAM
@
1
2
CH40
1U_0402_6.3VAK
CH40
1U_0402_6.3VAK
1
2
CH27
0.1U_0402_10V7K
CH27
0.1U_0402_10V7K
1
2
RH2360_0603_5% @RH2360_0603_5% @
1 2
LPT_PCH_M_EDS
Core
PCIe/DMI
VCCMPHY
USB3
HVCMOS
FDI
CRT DAC
SATA
7 OF 11
UH1G
LPT_PCH_M_EDS
Core
PCIe/DMI
VCCMPHY
USB3
HVCMOS
FDI
CRT DAC
SATA
7 OF 11
UH1G
VCCVRM AN11
VCC
AE18
VCC
AE22
VCCASW
U20
VCCASW
U22
VCCASW
U24
VCCASW
V22
VCCASW
V24
VCCASW
Y18
VCCASW
Y20
VCCASW
Y22
VCCADAC1_5 P45
VSS P43
VCCADACBG3_3 M31
VCCVRM BB44
VCCIO AN34
VCCIO AN35
VCC3_3_R30 R30
VCC3_3_R32 R32
DCPSUS1 Y12
VCCSUS3_3 AJ30
VCCSUS3_3 AJ32
DCPSUS3 AJ26
DCPSUS3 AJ28
VCCIO AK20
VCCVRM AK26
VCCVRM AK28
VCCIO AK18
VCCVRM BE22
VCCIO AM22
VCCIO AP22
VCCIO AR22
VCCIO AT22
VCCASW
V18
VCCASW
V20
VCCASW
U18 VCCASW
AA18 DCPSUSBYP
U14
VCC
Y26 VCC
AG24 VCC
AG22 VCC
AG20
VCC
AA24
VCC
AA26
VCC
AD20
VCC
AD24 VCC
AD22
VCC
AD26
VCC
AD28
VCCIO AK22
VCCIO AM20
VCCIO AM18
VCC
AG18 VCC
AE26 VCC
AE24
VCC
AE20
CH39
1U_0402_6.3VAK
@CH39
1U_0402_6.3VAK
@
1
2
CH41
10U_0603_6.3VAM
@CH41
10U_0603_6.3VAM
@
1
2
CH34
1U_0402_6.3VAK
CH34
1U_0402_6.3VAK
1
2
CH42
1U_0402_6.3VAK
@CH42
1U_0402_6.3VAK
@
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Place near pin Y32,AA30,AA32 Place near pin AD34 Place near pin AD35,AD36
Place near pin AG30,AG32,AE30,AE32
Place near pin M29 Place near pin L29 Place near pin L26,M26 Place near pin U32,V32
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Place near pin AP45
V_PROC_IO 1.05V 0.004 A
VCCADAC3_3 0.0133 A3.3V
VCCCLK 0.306 A1.05V
VCCCLK3_3 0.055 A
Voltage Rail
3.3V
VCCVRM 0.179 A1.5V
Voltage S0 Iccmax Current (A)
VCC3_3 3.3V 0.133 A
VCCASW 1.05V 0.67 A
VCCSUSHDA 3.3V 0.01 A
VCCSPI 3.3V 0.022 A
PCH Power Rail Table
VCCSUS3_3 3.3V 0.261 A
VCC 1.05V 1.29 A
VCCIO 1.05V 3.629 A
VCCDSW3_3 3.3V 0.015 A
VCCADAC1_5 1.5V 0.070 A
Support DEEP SX: populated RH238/RH246, de-populated RH237/RH240
+PCH_USB_DCPSUS2
+PCH_VCCDSW3_3
+PCH_VCCSST
+PCH_DCPRTC
+PCH_VCCCFUSE
+PCH_VCCCFUSE
+PCH_USB_DCPSUS2
+PCH_VCC
+PCH_VCC+PCH_VCC
+3.3V_VCCPRTCSUS
+1.05V_RUN
+3.3V_RUN
+1.5V_RUN
+3.3V_RUN
+3.3V_ALW_PCH
+3.3V_ALW
+3.3V_RUN
+1.05V_RUN
+3.3V_ALW_PCH
+3.3V_M
+3.3V_RUN
+1.05V_M
+1.5V_RUN
+1.05V_RUN
+1.05V_RUN +PCH_VCCCLK
+PCH_VCCCLK
+PCH_VCCCLK
+PCH_VCCCLK3_3
+PCH_VCCCLK3_3
+RTC_CELL
+3.3V_ALW_PCH
+1.05V_M
+3.3V_RUN
+1.05V_RUN
+3.3V_ALW_PCH
+PCH_VCCDSW3_3
+VCCIO2PCH
+VCCIO2PCH
+3.3V_VCCPRTCSUS
+3.3V_ALW
+3.3V_ALW_PCH
+1.05V_RUN +1.05V_RUN_VCC
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
PCH (8/9)
25 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
PCH (8/9)
25 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
PCH (8/9)
25 67Monday, January 13, 2014
Compal Electronics, Inc.
CH47
0.1U_0402_10V7K
CH47
0.1U_0402_10V7K
1
2
RH2460_0603_5% @RH2460_0603_5% @
12
CH54
0.1U_0402_10V7K
CH54
0.1U_0402_10V7K
1 2
CH74
1U_0402_6.3VAK
CH74
1U_0402_6.3VAK
1
2
RH244 0_0805_5%@RH244 0_0805_5%@
1 2
CH58
1U_0402_6.3VAK
@CH58
1U_0402_6.3VAK
@
1
2
CH71
1U_0402_6.3VAK
CH71
1U_0402_6.3VAK
1
2
RH2380_0603_5% @RH2380_0603_5% @
12
CH51
0.1U_0402_10V7K
CH51
0.1U_0402_10V7K
1
2
CH81
1U_0402_6.3VAK
CH81
1U_0402_6.3VAK
1
2
CH45
0.1U_0402_10V7K
CH45
0.1U_0402_10V7K
1
2
CH59
1U_0402_6.3VAK
CH59
1U_0402_6.3VAK
1
2
RH245 0_0805_5%RH245 0_0805_5%
1 2
CH70
1U_0402_6.3VAK
CH70
1U_0402_6.3VAK
1
2
RH2420_0805_5% @RH2420_0805_5% @
12
CH82
0.1U_0402_10V7K
CH82
0.1U_0402_10V7K
1
2
RH2400_0603_5% @RH2400_0603_5% @
12
CH73
1U_0402_6.3VAK
CH73
1U_0402_6.3VAK
1
2
LH2
4.7UH_LQM18FN4R7M00D_20%
LH2
4.7UH_LQM18FN4R7M00D_20%
1 2
CH66
1U_0402_6.3VAK
CH66
1U_0402_6.3VAK
1
2
RH239 0_0402_5%@RH239 0_0402_5%@
1 2
RH2370_0603_5% @RH2370_0603_5% @
12
CH69
1U_0402_6.3VAK
CH69
1U_0402_6.3VAK
1
2
RH241 0_0603_5%@RH241 0_0603_5%@
1 2
CH49
0.1U_0402_10V7K
CH49
0.1U_0402_10V7K
1
2
CH72
1U_0402_6.3VAK
CH72
1U_0402_6.3VAK
1
2
CH44
0.1U_0402_10V7K
CH44
0.1U_0402_10V7K
1
2
CH50
1U_0402_6.3VAK
CH50
1U_0402_6.3VAK
1
2
CH55
0.1U_0402_10V7K
CH55
0.1U_0402_10V7K
1
2
CH64
1U_0402_6.3V6K
CH64
1U_0402_6.3V6K
1
2
CH56
0.1U_0402_10V7K
CH56
0.1U_0402_10V7K
1
2
CH52
10U_0603_6.3V6M
CH52
10U_0603_6.3V6M
1
2
CH67
1U_0402_6.3VAK
CH67
1U_0402_6.3VAK
1
2
CH65
0.1U_0402_10V7K
CH65
0.1U_0402_10V7K
1
2
CH75
1U_0402_6.3VAK
CH75
1U_0402_6.3VAK
1
2
RH2430_0805_5% @RH2430_0805_5% @
12
CH46 0.1U_0402_10V7KCH46 0.1U_0402_10V7K
1 2
CH57
1U_0402_6.3V6K
CH57
1U_0402_6.3V6K
1
2
CH53
1U_0402_6.3VAK
CH53
1U_0402_6.3VAK
1
2
CH43
0.1U_0402_10V7K
CH43
0.1U_0402_10V7K
1
2
CH68
1U_0402_6.3VAK
@CH68
1U_0402_6.3VAK
@
1
2
SPI
USB
GPIO/LPC
Azalia
RTC
CPU
Thermal
ICC
LPT_PCH_M_EDS
8 OF 11
UH1H
SPI
USB
GPIO/LPC
Azalia
RTC
CPU
Thermal
ICC
LPT_PCH_M_EDS
8 OF 11
UH1H
VCCSUS3_3
R24
VCCVRM
AF34
VCC
AP45
VCC3_3 AK32
VCCASW R18
VCCASW L17
VCC P20
VCC P18
VCCSPI AD12
V_PROC_IO AJ14
V_PROC_IO AJ12
DCPRTC P16
DCPRTC P14
VCCRTC A6
VCCSUS3_3 K8
VCCSUSHDA A26
VCCIO U36
VCC3_3 AG14
VCC3_3 AF12
VCC3_3 AE14
DCPSST AA14
VCCDSW3_3 A16
VCCSUS3_3 R22
VCCSUS3_3 R20
VCCCLK
AE32 VCCCLK
AE30
VCCCLK
AD36
VCCCLK
AG32 VCCCLK
AG30
VCCCLK
AD35
VCCCLK
AA32 VCCCLK
AA30
VCCCLK
AD34
VCCCLK3_3
V32 VCCCLK3_3
U32
VCCCLK3_3
M26 VCCCLK3_3
L26
VCCCLK3_3
L29
VCCCLK3_3
M29
VCCCLK
Y32
VCCIO
V28
VCCIO
V30
VCCIO
U30
VCC3_3
L24
VCCUSBPLL
U35
VSS
M24
VCCSUS3_3
U26 VCCSUS3_3
R28 VCCSUS3_3
R26
VCC3_3 AK30
VCCVRM AW40
DCPSUS2
Y35
VCCIO
Y30
CH63
10U_0603_6.3V6M
CH63
10U_0603_6.3V6M
1
2
CH48
0.1U_0402_10V7K
CH48
0.1U_0402_10V7K
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
PCH (9/9)
26 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
PCH (9/9)
26 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
PCH (9/9)
26 67Monday, January 13, 2014
Compal Electronics, Inc.
LPT_PCH_M_EDS
10 OF 11
UH1J
LPT_PCH_M_EDS
10 OF 11
UH1J
VSS
AV31
VSS
BB25
VSS
AV40
VSS
AV33
VSS
AV13 VSS
D42
VSS
AT36
VSS
AT26 VSS
AT20 VSS
AT17
VSS
AT29
VSS
AV24
VSS N12
VSS N39
VSS N35
VSS N6
VSS P24
VSS P22
VSS P30
VSS P28
VSS P26
VSS P32
VSS R12
VSS R2
VSS R16
VSS R14
VSS R38
VSS R34
VSS R44
VSS T43
VSS R8
VSS U16
VSS U10
VSS U28
VSS U34
VSS U38
VSS U6
VSS U42
VSS V14
VSS V16
VSS V26
VSS W44
VSS W2
VSS V43
VSS Y16
VSS Y14
VSS Y24
VSS Y34
VSS Y28
VSS Y40
VSS Y36
VSS Y8
VSS
AT38
VSS
F43
VSS
AT15 VSS
AT10 VSS
AK16 VSS
AR2 VSS
AP43
VSS
AP24
VSS
AN40 VSS
AN36
VSS
AM30 VSS
AM28
VSS M22
VSS M17
VSS L44
VSS L2
VSS K39
VSS
B15 VSS
B11 VSS
AY7 VSS
AY29 VSS
AY26 VSS
AY20 VSS
AY15 VSS
AY10
VSS
AW2 VSS
AV6
VSS
AP31
VSS
AP13 VSS
AN8
VSS
AM32
VSS
AM26 VSS
AM24 VSS
AM14 VSS
AL8 VSS
AL38 VSS
AL34
VSS
AN42
VSS
AM16
VSS
AV22
LPT_PCH_M_EDS
11 OF 11
UH1K
LPT_PCH_M_EDS
11 OF 11
UH1K
VSS D4
VSS BC16
VSS G2
VSS G38
VSS G44
VSS G8
VSS H10
VSS H13
VSS
AB8
VSS BD31
VSS BD35
VSS BD39
VSS BD7
VSS AV7
VSS F20
VSS F33
VSS
AA16
VSS H36
VSS H26
VSS H17
VSS H22
VSS H24
VSS F29
VSS F15
VSS D25
VSS
AC2
VSS
AB38
VSS
AJ20 VSS
AJ18
VSS
AJ24 VSS
AJ22
VSS K33
VSS K29
VSS K20
VSS K15
VSS K10
VSS H7
VSS H40
VSS H31
VSS AT43
VSS AY36
VSS BD19
VSS BD15
VSS BD11
VSS BA40
VSS B7
VSS B39
VSS B35
VSS B31
VSS B27
VSS B23
VSS B19
VSS
AL2 VSS
AL12 VSS
AK45 VSS
AK43 VSS
AK24 VSS
AK14 VSS
AJ8 VSS
AJ6 VSS
AJ38 VSS
AJ34
VSS
AJ16
VSS
AG16 VSS
AF8 VSS
AF38 VSS
AE28 VSS
AE16 VSS
AD8
VSS
AD16 VSS
AD14 VSS
AC44
VSS
AB34 VSS
AB12 VSS
AA4 VSS
AA28 VSS
AA22 VSS
AA20
VSS
AG44 VSS
AG28 VSS
AG26 VSS
AG2
VSS
AD32 VSS
AD30 VSS
AD18
VSS
BB42 VSS
BC22
VSS BC28
VSS
AD6 VSS
AD40
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
MXM FAN
CPU FAN
Link CIS OK
Link CIS OK
Difference with Diesel
C330 change to 0603
due to height limitation.
FAN1_PWM
FAN2_PWM_D
FAN1_TACH_FB
FAN2_TACH_FB
FAN2_PWM_D
FAN2_PWM
FAN2_TACH_FB
FAN1_TACH_FB
FAN1_PWM
+3.3V_RUN
+5V_RUN
+5V_RUN
FAN1_TACH_FB<51>
FAN1_PWM<51>
FAN2_PWM<51>
FAN2_TACH_FB<51>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
FAN control
27 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
FAN control
27 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
FAN control
27 67Monday, January 13, 2014
Compal Electronics, Inc.
C370
0.1U_0402_25V6K
C370
0.1U_0402_25V6K
1
2
JFAN1
ACES_50271-0040N-001
CONN@
JFAN1
ACES_50271-0040N-001
CONN@
1
1
2
2
3
3
4
4
GND1
5
GND2
6
R40510K_0402_5% R40510K_0402_5%
12
R213 0_0603_5%@R213 0_0603_5%@
12
R40310K_0402_5% R40310K_0402_5%
12
R40910K_0402_5% @R40910K_0402_5% @
12
R40810K_0402_5% R40810K_0402_5%
12
10U_0805_10V6K
C329
10U_0805_10V6K
C329
1
2
JFAN2
ACES_50271-0040N-001
CONN@
JFAN2
ACES_50271-0040N-001
CONN@
1
1
2
2
3
3
4
4
GND1
5
GND2
6
C364
0.1U_0402_25V6K
C364
0.1U_0402_25V6K
1
2
R40710K_0402_5% R40710K_0402_5%
12
C330
10U_0603_6.3V6M
C330
10U_0603_6.3V6M
1
2
D90
RB751S40T1_SOD523-2
D90
RB751S40T1_SOD523-2
21
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
Remove current sensor Monitor (HW solution)
Remove current sensor Monitor (SW solution)
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Current Sensor
28 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Current Sensor
28 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Current Sensor
28 67Monday, January 13, 2014
Compal Electronics, Inc.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
CIS LINK OK
INy_PEQ = Programmable input equalization levels
L: default, LEQ, compensate channel loss up to 11.5dB @ HBR2
H: HEQ, compensate channel loss up to 14.5dB @ HBR2
M: LLEQ, compensate channel loss up to 8.5dB @ HBR2
INy_AEQ# = Automatic EQ disable
L: Automatic EQ enable (default)
H: Automatic EQ disable
PI0 = Auto test enable
L: Auto test disable & input offset cancellation enable (default)
H: Auto test enable & input offset cancellation enable
M: Auto test disable & input offset cancellation disable
PC0 = AUX interception disable
L: AUX interception enable, driver configuration is set by link training (default)
H: AUX interception disable, driver output with fixed 800mV and 0dB
M: AUX interception disable, driver output with fixed 400mV and 0dB
PC1 = Output swing adjustment
L: default
H: +20%
M: -16.7%
eDP Conn
CPU
MXM
for DP Lane bus layout routing smoothly.
DGPU_SELECT
LCD_EDP_HPD
LCD_EDP_LANE_P0
LCD_EDP_LANE_N0
LCD_EDP_LANE_P1
LCD_EDP_LANE_N1
LCD_EDP_LANE_P2
LCD_EDP_LANE_N2
LCD_EDP_LANE_P3
LCD_EDP_LANE_N3
EDP_MUX_PC0
EDP_MUX_PC1
EDP_IN1_AEQ#
EDP_IN2_AEQ#
EDP_IN2_PEQ
EDP_IN1_PEQ
EDP_MUX_PC1
EDP_MUX_PC0
EDP_MUX_PI0
EDP_MUX_PC1
EDP_MUX_PC0
EDP_MUX_PI0
EDP_IN1_PEQ
EDP_IN2_PEQ
MUX_REXT
MUX_CET
EDP_MUX_PI0
MUX_CET
EDP_IN2_PEQ
EDP_IN1_PEQ
EDP_IN1_AEQ#
EDP_IN2_AEQ#
LCD_EDP_AUX
LCD_EDP_AUX#
MXM_EDP_LANE_P1
MXM_EDP_LANE_N1
MXM_EDP_LANE_P2
MXM_EDP_LANE_N2
MXM_EDP_LANE_P0
MXM_EDP_LANE_P3
MXM_EDP_LANE_N3
MXM_EDP_LANE_N0
MXM_EDP_LANE_P1_C
MXM_EDP_LANE_N1_C
MXM_EDP_LANE_P2_C
MXM_EDP_LANE_N2_C
MXM_EDP_LANE_P0_C
MXM_EDP_LANE_P3_C
MXM_EDP_LANE_N3_C
MXM_EDP_LANE_N0_C
MXM_EDP_AUX_C
MXM_EDP_AUX#_C
MXM_EDP_AUX
MXM_EDP_AUX#
CPU_EDP_LANE_P0
CPU_EDP_LANE_N0
CPU_EDP_LANE_N1
CPU_EDP_LANE_P1
CPU_EDP_LANE_N1_C
CPU_EDP_LANE_P0_C
CPU_EDP_LANE_N0_C
CPU_EDP_LANE_P1_C
CPU_EDP_AUX#_C
CPU_EDP_AUX_C
CPU_EDP_AUX#
CPU_EDP_AUX
MXM_EDP_HPD
CPU_EDP_HPD
DGPU_SELECT
DGPU_SELECT#
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
LCD_EDP_LANE_P0 <30>
LCD_EDP_LANE_P1 <30>
LCD_EDP_LANE_N0 <30>
LCD_EDP_LANE_N1 <30>
LCD_EDP_LANE_P2 <30>
LCD_EDP_LANE_N2 <30>
LCD_EDP_LANE_P3 <30>
LCD_EDP_LANE_N3 <30>
LCD_EDP_AUX <30>
LCD_EDP_AUX# <30>
LCD_EDP_HPD <30>
MXM_EDP_LANE_P0<17>
MXM_EDP_LANE_N0<17>
MXM_EDP_LANE_P1<17>
MXM_EDP_LANE_N1<17>
MXM_EDP_LANE_P2<17>
MXM_EDP_LANE_N2<17>
MXM_EDP_LANE_P3<17>
MXM_EDP_LANE_N3<17>
MXM_EDP_AUX#<17>
MXM_EDP_AUX<17>
CPU_EDP_LANE_P0<9>
CPU_EDP_LANE_N0<9>
CPU_EDP_LANE_P1<9>
CPU_EDP_LANE_N1<9>
CPU_EDP_AUX<9>
CPU_EDP_AUX#<9>
MXM_EDP_HPD<17>
CPU_EDP_HPD<9>
DGPU_SELECT# <30,35,50>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
eDP MUX (PS8331)
29 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
eDP MUX (PS8331)
29 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
eDP MUX (PS8331)
29 67Monday, January 13, 2014
Compal Electronics, Inc.
R142 4.7K_0402_5%@R142 4.7K_0402_5%@
1 2
C537 0.1U_0402_10V6KC537 0.1U_0402_10V6K
1 2
R100 4.7K_0402_5%@R100 4.7K_0402_5%@
1 2
C563 0.1U_0402_10V6KC563 0.1U_0402_10V6K
1 2
C562 0.1U_0402_10V6KC562 0.1U_0402_10V6K
1 2
U630
PS8331BQFN60GTR-A0_QFN60_5X9
U630
PS8331BQFN60GTR-A0_QFN60_5X9
IN1_D2p
6
IN1_D2n
7
IN1_AEQ#
59
IN1_D3p
9
IN1_D3n
10
IN1_HPD
3
IN2_D0p
11
IN2_D0n
12
IN2_HPD
13
IN2_D1p
14
IN2_D1n
15
GND 57
IN2_D2p
16
IN2_D2n
17
OUT_AUXp_SCL 32
OUT_AUXn_SDA 31
REXT 34
CEXT 47
IN2_D3n
20 IN2_D3p
19
OUT_D0p 46
OUT_D0n 45
PD 50
OUT_D1p 43
OUT_D1n 42
I2C_CTL_EN 53
OUT2_D2p 40
OUT2_D2n 39
OUT_D3p 37
OUT_D3n 36
VDD33
26
OUT_HPD 44
CA_DET 48
GND 41
IN2_PEQ/SCL_CTL
51
IN1_PEQ/SDA_CTL
52
IN2_AEQ#
58
IN1_D0p
1
IN1_D0n
2
VDD33
21
IN1_D1p
4
IN1_D1n
5
Epad 61
IN1_SDA
22 IN1_SCL
23
IN2_SDA
24 IN2_SCL
25
IN1_AUXn
27 IN1_AUXp
28
IN2_AUXn
29 IN2_AUXp
30
SW 54
GND 33
GND 18
GND 8
VDD33
35
VDD33
49
VDD33
60
PI0 56
PC0 38
PC1 55
C500
0.1U_0402_16V4Z
C500
0.1U_0402_16V4Z
1
2
R137 4.7K_0402_5%@R137 4.7K_0402_5%@
1 2
R3722 1M_0402_5%R3722 1M_0402_5%
1 2
C564 0.1U_0402_10V6KC564 0.1U_0402_10V6K
1 2
R127 4.7K_0402_5%@R127 4.7K_0402_5%@
1 2
C502
0.1U_0402_16V4Z
C502
0.1U_0402_16V4Z
1
2
C567 0.1U_0402_10V6KC567 0.1U_0402_10V6K
1 2
C549 0.1U_0402_10V6KC549 0.1U_0402_10V6K
1 2
C566 0.1U_0402_10V6KC566 0.1U_0402_10V6K
1 2
C501
0.1U_0402_16V4Z
C501
0.1U_0402_16V4Z
1
2
C568 0.1U_0402_10V6KC568 0.1U_0402_10V6K
1 2
C556 0.1U_0402_10V6KC556 0.1U_0402_10V6K
1 2
C784
4.7U_0603_6.3V6K
C784
4.7U_0603_6.3V6K
1
2
R133 4.7K_0402_5%@R133 4.7K_0402_5%@
1 2
R109 4.7K_0402_5%@R109 4.7K_0402_5%@
1 2
C554
0.1U_0402_16V4Z
C554
0.1U_0402_16V4Z
1
2
R143 4.7K_0402_5%@R143 4.7K_0402_5%@
1 2
RV46 0_0402_5%@RV46 0_0402_5%@
1 2
C98 2.2U_0402_6.3V6MC98 2.2U_0402_6.3V6M
12
C557 0.1U_0402_10V6KC557 0.1U_0402_10V6K
1 2
RV47
10K_0402_5%
RV47
10K_0402_5%
12
RV48
8.2K_0402_5%
RV48
8.2K_0402_5%
12
R140 4.7K_0402_5%@R140 4.7K_0402_5%@
1 2
R138 4.7K_0402_5%@R138 4.7K_0402_5%@
1 2
R101
4.99K_0402_1%
R101
4.99K_0402_1%
1 2
C555 0.1U_0402_10V6KC555 0.1U_0402_10V6K
1 2
C561 0.1U_0402_10V6KC561 0.1U_0402_10V6K
1 2
G
D
S
QV1
DMN65D8LW-7_SOT323-3
G
D
S
QV1
DMN65D8LW-7_SOT323-3
2
13
C559 0.1U_0402_10V6KC559 0.1U_0402_10V6K
1 2
C558 0.1U_0402_10V6KC558 0.1U_0402_10V6K
1 2
R139 4.7K_0402_5%@R139 4.7K_0402_5%@
1 2
R136 4.7K_0402_5%@R136 4.7K_0402_5%@
1 2
R141 4.7K_0402_5%@R141 4.7K_0402_5%@
1 2
C565 0.1U_0402_10V6KC565 0.1U_0402_10V6K
1 2
C560 0.1U_0402_10V6KC560 0.1U_0402_10V6K
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Panel backlight power control by EC
DELL CONFIDENTIAL/PROPRIETARY
40mil
40mil
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Touch Screen
Close to JEDP1
Webcam PWR CTRL
LInk CIS
EMC request change main source
to SM070001N00
EMC request change main source
to SM070002J00
LCD Power
Difference with Diesel
Difference with Diesel
Difference with Diesel
Daisy Chain with Docking SMBus
Difference with Diesel
Close to JTS1
Close to JEDP1
Close to JEDP1
CIS link OK
C300 change to 0603
due to height limitation.
D21 change to H: 1.1mm
due to height limitation.
D22 change to H: 1.1mm
due to height limitation.
Follow P5_17 TS spec about 140mA (+5V_RUN)
DISP_ON
USBP8_D+
PWR_SRC_ON
USBP11_D+
USBP11_D-
USBP8_D-
BIA_PWM
TOUCH_SCREEN_PD#
LCD_EDP_HPD
LCD_EDP_AUX
LCD_EDP_AUX#
USBP8_D+
USBP8_D-
BIA_PWM
DISP_ON
LCD_EDP_LANE_P0_C
LCD_EDP_LANE_N0_C
LCD_EDP_LANE_P1_C
LCD_EDP_LANE_N1_C
LCD_EDP_LANE_P2_C
LCD_EDP_LANE_N2_C
LCD_EDP_LANE_P3_C
LCD_EDP_LANE_N3_C
LCD_EDP_AUX_C
LCD_EDP_AUX#_C
DOCK_LCD_SMBCLK_Q
DOCK_LCD_SMBDAT_Q
USBP11_D-
USBP11_D+
TOUCH_SCREEN_PD#
USBP11_D+
USBP11_D-
DMIC0
DMIC_CLK
LCD_EDP_HPD
DOCK_LCD_SMBCLK_Q
DOCK_LCD_SMBDAT_Q
+PWR_SRC +BL_PWR_SRC
+CAMERA_VDD
+3.3V_RUN
+BL_PWR_SRC +LCDVDD
+3.3V_RUN
+3.3V_ALW
+3.3V_RUN
+BL_PWR_SRC
+LCDVDD
+LCDVDD +3.3V_ALW
+LCDVDD
+CAMERA_VDD
+3.3V_RUN
+LCDVDD
+5V_RUN
EN_INVPWR<51>
USBP8-<22>
USBP8+<22>
BIA_PWM_EC <51>
PANEL_BKEN_EC <50>
BIA_PWM_PCH <19>
MXM_PANEL_BKEN <17>
CCD_OFF <50>
USBP11-<22>
USBP11+<22>
MXM_BIA_PWM <17>
DGPU_SELECT#<29,35,50>
DMIC_CLK <49>
DMIC0 <49>
CAM_MIC_CBL_DET# <19>
LCD_CBL_DET# <19>
LCD_TST <50>
LCD_EDP_LANE_P0 <29>
LCD_EDP_LANE_N0 <29>
LCD_EDP_LANE_P1 <29>
LCD_EDP_LANE_N1 <29>
LCD_EDP_LANE_P2 <29>
LCD_EDP_LANE_N2 <29>
LCD_EDP_LANE_P3 <29>
LCD_EDP_LANE_N3 <29>
LCD_EDP_AUX# <29>
LCD_EDP_AUX <29>
LCD_EDP_HPD <29>
TOUCH_SCREEN_PD#<50>
LCD_VCC_TEST_EN<50>
MXM_ENVDD<17>
PANEL_BKEN_PCH <19>
ENVDD_PCH<19,51>
DOCK_LCD_SMBDAT <48,51>
DOCK_LCD_SMBCLK <48,51>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
eDP / CAM / TS
30 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
eDP / CAM / TS
30 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
eDP / CAM / TS
30 67Monday, January 13, 2014
Compal Electronics, Inc.
D71
RB751VM-40TE-17_SOD323-2
D71
RB751VM-40TE-17_SOD323-2
21
C3790.1U_0402_10V6K C3790.1U_0402_10V6K
12
C248
0.1U_0402_10V7K
C248
0.1U_0402_10V7K
1 2
D68
RB751VM-40TE-17_SOD323-2
D68
RB751VM-40TE-17_SOD323-2
21
D69
RB751VM-40TE-17_SOD323-2
D69
RB751VM-40TE-17_SOD323-2
21
D65
RB751VM-40TE-17_SOD323-2
D65
RB751VM-40TE-17_SOD323-2
21
C301
0.1U_0402_25V6K
C301
0.1U_0402_25V6K
1
2
U33
APL3512ABI-TRG_SOT23-5
U33
APL3512ABI-TRG_SOT23-5
VIN 5
SS 4
VOUT
1
EN
3
GND
2
R429 0_0402_5%@R429 0_0402_5%@
1 2
C300
10U_0603_6.3V6M
@C300
10U_0603_6.3V6M
@
1
2
C298
0.1U_0402_25V6K
C298
0.1U_0402_25V6K
1
2
R1137
10K_0402_5%
R1137
10K_0402_5%
12
C3800.1U_0402_10V6K C3800.1U_0402_10V6K
12
D93
BAT54CW_SOT323-3
D93
BAT54CW_SOT323-3
1
2
3
R339100K_0402_5% R339100K_0402_5%
12
D22
PESD5V0U2BT_SOT23-3
@EMC@
D22
PESD5V0U2BT_SOT23-3
@EMC@
2
3
1
QV2B
DMN66D0LDW -7_SOT363-6
@QV2B
DMN66D0LDW -7_SOT363-6
@
3
5
4
C3720.1U_0402_10V6K C3720.1U_0402_10V6K
12
JTS1
ACES_50228-0067N-001
CONN@
JTS1
ACES_50228-0067N-001
CONN@
1
1
2
2
3
3
4
4
5
5
6
6
GND
7
GND
8
L10 DLW21SN121SQ2L_4P
EMC@
L10 DLW21SN121SQ2L_4P
EMC@
1
1
4
433
22
C249
0.1U_0603_50V7K
C249
0.1U_0603_50V7K
1
2
R427 0_0402_5%@R427 0_0402_5%@
1 2
C296
0.1U_0603_50V7K
C296
0.1U_0603_50V7K
1
2
D92
RB751VM-40TE-17_SOD323-2
D92
RB751VM-40TE-17_SOD323-2
2 1
C3730.1U_0402_10V6K C3730.1U_0402_10V6K
12
R222100K_0402_5% R222100K_0402_5%
12
C3740.1U_0402_10V6K C3740.1U_0402_10V6K
12
C3750.1U_0402_10V6K C3750.1U_0402_10V6K
12
D20
L30ESDL5V0C3-2_SOT23-3
@EMC@ D20
L30ESDL5V0C3-2_SOT23-3
@EMC@
1
2
3
U3
TC7SH125FU_SSOP5
U3
TC7SH125FU_SSOP5
A2
Y
4
P5
G
3
OE# 1
G
D
S
Q22
DMN65D8LW -7_SOT323-3
G
D
S
Q22
DMN65D8LW -7_SOT323-3
2
1 3
S
G
D
Q21
FDC654P-G_SSOT-6
S
G
D
Q21
FDC654P-G_SSOT-6
3
6
2
4 5
1
R336100K_0402_5% R336100K_0402_5%
12
C3710.1U_0402_10V6K C3710.1U_0402_10V6K
12
JEDP1
ACES_50398-04041-001
CONN@
JEDP1
ACES_50398-04041-001
CONN@
11
22
33
44
55
66
77
88
99
10 10
11 11
12 12
13 13
14 14
15 15
16 16
17 17
18 18
19 19
20 20
21 21
22 22
23 23
24 24
25 25
26 26
27 27
28 28
29 29
30 30
31 31
32 32
33 33
34 34
35 35
36 36
37 37
38 38
39 39
40 40
G1
41 G2
42 G3
43 G4
44 G5
45
C299
0.1U_0402_25V6K
C299
0.1U_0402_25V6K
1
2
R426 100K_0402_5%@R426 100K_0402_5%@
12
R208 0_0603_5%@EMC@R208 0_0603_5%@EMC@
12
G
D
S
Q24
DMG2301U-7_SOT23-3
G
D
S
Q24
DMG2301U-7_SOT23-3
2
13
R1034.7K_0402_5% R1034.7K_0402_5%
12
R428 0_0402_5%@R428 0_0402_5%@
1 2
L11
LPF0805F2SF-900T04 _4P
@EMC@ L11
LPF0805F2SF-900T04 _4P
@EMC@
1
1
4
433
22
C396
10U_0603_6.3V6M
@C396
10U_0603_6.3V6M
@
12
C3770.1U_0402_10V6K C3770.1U_0402_10V6K
12
QV2A
DMN66D0LDW -7_SOT363-6
@QV2A
DMN66D0LDW -7_SOT363-6
@
61
2
R1138
100K_0402_5%
R1138
100K_0402_5%
12
C3760.1U_0402_10V6K C3760.1U_0402_10V6K
12
C297
1U_1206_50V7K
C297
1U_1206_50V7K
1
2
D64
RB751VM-40TE-17_SOD323-2
D64
RB751VM-40TE-17_SOD323-2
21
R423 47K_0402_5%R423 47K_0402_5%
1 2
R422
100K_0402_5%
R422
100K_0402_5%
12
C310
0.1U_0402_25V6K
@C310
0.1U_0402_25V6K
@
1
2
D66
RB751VM-40TE-17_SOD323-2
D66
RB751VM-40TE-17_SOD323-2
21
D21
PESD5V0U2BT_SOT23-3
@EMC@ D21
PESD5V0U2BT_SOT23-3
@EMC@
2
3
1
R430 0_0402_5%@R430 0_0402_5%@
1 2
R3727
100K_0402_5%
R3727
100K_0402_5%
12
C3780.1U_0402_10V6K C3780.1U_0402_10V6K
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Port switching control or priority configuration. Internal pull down ~150KΩ, 3.3V I/O
For Control Switching Mode (CFG0 = L):
SW = L: Port1 is selected (default)
SW = H: Port2 is selected
CV62 CV90 close to pin30 &57
CV66,CV69,CV70 close to pin5,21,51
MXM DP_A Dongle DDC
Difference with Diesel
TBT
MB_DP
For Automatic Switching Mode (CFG0 = H): (By OUT1_HPD and OUT2_HPD)
SW = L: Port1 has higher priority when both ports are plugged (default)
SW = H: Port2 has higher priority when both ports are plugged
V
CFG0
V
SW
H L
MXM
MB_DP will have higher priority over TBT.
Doc: Dell Graphics Behavior Specification Addendum for Nvidia Optimus
Implementatio for Delray.092
CIS link OK
MB_DP_DEMUX_CA_DET_Q
MXM_DPA_AUX
MXM_DPA_AUX#
MB_DP_DEMUX_CA_DET
MB_DP_RP_P0
MB_DP_RP_N0
MB_DP_RP_P1
MB_DP_RP_N1
MB_DP_RP_P2
MB_DP_RP_N2
MB_DP_RP_P3
MB_DP_RP_N3
MB_DP_RP_AUX
MB_DP_RP_AUX#
MB_DP_HPD
MB_DP_CA_DET
MXM_DPA_P0_C
MXM_DPA_N0_C
MXM_DPA_P1_C
MXM_DPA_N1_C
MXM_DPA_P2_C
MXM_DPA_N2_C
MXM_DPA_P3_C
MXM_DPA_N3_C
MXM_DPA_AUX_C
MXM_DPA_AUX#_C
MB_DEMUX_P1
MB_DEMUX_P0
MB_DEMUX_PC21
MB_DEMUX_PC20
MB_DEMUX_PC11
MB_DEMUX_PC10
MB_DEMUX_PEQ
MB_DEMUX_PEQ
MB_DEMUX_PC21
MB_DEMUX_PC20
MB_DEMUX_PC11
MB_DEMUX_PC10
MB_DEMUX_P1
MB_DEMUX_SW
MB_DEMUX_CFG0
MB_DEMUX_P0
MB_DEMUX_CFG0
MB_DEMUX_SW
MB_DP_RP_N3_C
MB_DP_RP_P3_C
MB_DP_RP_N2_C
MB_DP_RP_P2_C
MB_DP_RP_N1_C
MB_DP_RP_P1_C
MB_DP_HPD
MB_DP_RP_N0_C
MB_DP_CA_DET
MB_DP_RP_P0_C
DP_MB_P14
MB_DP_RP_AUX
MB_DP_RP_AUX#
DP_MB_P14
MB_DP_CA_DET
MB_DP_DEMUX_CA_DET
MB_DP_RP_P1
MB_DP_RP_N1
MB_DP_RP_N0
MB_DP_RP_P0
MB_DP_RP_P2
MB_DP_RP_N2
MB_DP_RP_N3
MB_DP_RP_P3
MB_DP_RP_AUX#
MB_DP_RP_AUX
+5V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+DP_VCC
+3.3V_RUN
+3.3V_RUN
TBT_DP_P2 <32>
TBT_DP_P3 <32>
TBT_DP_N3 <32>
TBT_DP_N2 <32>
TBT_DP_P0 <32>
TBT_DP_P1 <32>
TBT_DP_N1 <32>
TBT_DP_N0 <32>
TBT_DP_AUX# <32,33>
TBT_DP_AUX <32,33>
TBT_DP_HPD <32>
MXM_DPA_P3<17>
MXM_DPA_N0<17>
MXM_DPA_P0<17>
MXM_DPA_N1<17>
MXM_DPA_P1<17>
MXM_DPA_N2<17>
MXM_DPA_P2<17>
MXM_DPA_N3<17>
MXM_DPA_AUX#<17>
MXM_DPA_AUX<17>
MXM_DPA_HPD<17>
TBT_CONFIG1_BUF <32,33>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
DP SW (PS8338) & DP Conn
31 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
DP SW (PS8338) & DP Conn
31 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
DP SW (PS8338) & DP Conn
31 67Monday, January 13, 2014
Compal Electronics, Inc.
R2151
4.7K_0402_5%
R2151
4.7K_0402_5%
1 2
C281 0.1U_0402_10V6KC281 0.1U_0402_10V6K
1 2
R59100K_0402_5% R59100K_0402_5%
12
CV24 0.1U_0402_25V6CV24 0.1U_0402_25V6
1 2
C1332
0.01U_0402_16V7K
C1332
0.01U_0402_16V7K
1
2
CV18 0.1U_0402_25V6CV18 0.1U_0402_25V6
1 2
RV20
4.7K_0402_5%
@
RV20
4.7K_0402_5%
@
12
R2152
100K_0402_5%
R2152
100K_0402_5%
12
R2157
4.7K_0402_5%
R2157
4.7K_0402_5%
1 2
C282 0.1U_0402_10V6KC282 0.1U_0402_10V6K
1 2
CV15
0.1U_0402_25V6
CV15
0.1U_0402_25V6
12
CV25 0.1U_0402_25V6CV25 0.1U_0402_25V6
1 2
CV16 0.1U_0402_25V6CV16 0.1U_0402_25V6
1 2
RV16
4.7K_0402_5%
@
RV16
4.7K_0402_5%
@
12
C1408 0.1U_0402_10V6KC1408 0.1U_0402_10V6K
1 2
CV19 0.1U_0402_25V6CV19 0.1U_0402_25V6
1 2
RV21
4.7K_0402_5%
@
RV21
4.7K_0402_5%
@
12
C1407 0.1U_0402_10V6KC1407 0.1U_0402_10V6K
1 2
CV17 0.1U_0402_25V6CV17 0.1U_0402_25V6
1 2
RV1 4.7K_0402_5%RV1 4.7K_0402_5%
1 2
JDP1
FOX_3V11211-N1YD7-7H
CONN@
JDP1
FOX_3V11211-N1YD7-7H
CONN@
LANE0+
1LANE0_shield
2LANE0-
3LANE1+
4LANE1_shield
5LANE1-
6LANE2+
7LANE2_shield
8LANE2-
9LANE3+
10 LANE3_shield
11 LANE3-
12 CA_DET
13 GND
14 AUX_CH+
15 GND
16 AUX_CH-
17 HP_DET
18 RTN
19
GND 21
GND 22
GND 23
GND 24
DP_PWR
20
RV17
4.7K_0402_5%
@
RV17
4.7K_0402_5%
@
12
Q336A
DMN66D0LDW-7_SOT363-6
Q336A
DMN66D0LDW-7_SOT363-6
61
2
C286 0.1U_0402_10V6KC286 0.1U_0402_10V6K
1 2
CV20 0.1U_0402_25V6CV20 0.1U_0402_25V6
1 2
CV13
0.01U_0402_16V7K
CV13
0.01U_0402_16V7K
12
C313
0.01U_0402_16V7K
C313
0.01U_0402_16V7K
1
2
CV26
2.2U_0402_6.3V6M
CV26
2.2U_0402_6.3V6M
12
Q335A
DMN66D0LDW-7_SOT363-6
Q335A
DMN66D0LDW-7_SOT363-6
61
2
C280 0.1U_0402_10V6KC280 0.1U_0402_10V6K
1 2
RV2 4.7K_0402_5%RV2 4.7K_0402_5%
1 2
RV22
4.7K_0402_5%
@
RV22
4.7K_0402_5%
@
12
Q335B
DMN66D0LDW-7_SOT363-6
Q335B
DMN66D0LDW-7_SOT363-6
3
5
4
CV21 0.1U_0402_25V6CV21 0.1U_0402_25V6
1 2
RV3 4.7K_0402_5%
@
RV3 4.7K_0402_5%
@
1 2
RV18
4.7K_0402_5%
@
RV18
4.7K_0402_5%
@
12
RV10
4.7K_0402_5%
@
RV10
4.7K_0402_5%
@
12
CV22 0.1U_0402_25V6CV22 0.1U_0402_25V6
1 2
U30
AP2337SA-7_SOT23-3
U30
AP2337SA-7_SOT23-3
IN 1
GND
2
OUT
3
RV11
4.7K_0402_5%
@
RV11
4.7K_0402_5%
@
12
CV23 0.1U_0402_25V6CV23 0.1U_0402_25V6
1 2
RV12
4.7K_0402_5%
@
RV12
4.7K_0402_5%
@
12
R2153
100K_0402_5%
R2153
100K_0402_5%
12
UV1
PS8338BQFN60GTR-A0_QFN60_5X9
UV1
PS8338BQFN60GTR-A0_QFN60_5X9
VDD33
5
IN_D0n
7
IN_D2p
12
IN_D2n
13
IN_D3p
15
IN_D3n
16
IN_D1p
9
IN_D1n
10
IN_D0p
6
VDD33
21
VDD33
30
VDD33
51
VDD33
57
GND
19 GND
11
PC21
53 PC20
54 PC11
55 PC10
56 CFG1
58 CFG0
59
OUT1_D0p 50
OUT1_D0n 49
OUT1_D1p 47
OUT1_D1n 46
OUT1_D2p 45
OUT1_D2n 44
OUT1_D3p 42
OUT1_D3n 41
IN_CA_DET
4
IN_HPD
3
I2C_CTL_EN
2
Pl1/SCL_CTL
1
IN_AUXp
24
IN_AUXn
25
OUT2_D0p 40
OUT2_D0n 39
OUT2_D1p 37
OUT2_D1n 36
OUT2_D2p 35
OUT2_D2n 34
OUT2_D3p 32
OUT2_D3n 31
OUT1_AUXp_SCL 26
OUT1_AUXn_SDA 27
OUT2_AUXp_SCL 28
OUT2_AUXn_SDA 29
OUT1_CA_DET 43
OUT1_HPD 48
OUT2_CA_DET 33
OUT2_HPD 38
PEQ 8
CEXT 17
GND
52
IN_DDC_SCL
22
IN_DDC_SDA
23
Pl0/SDA_CTL
60
PAD(GND)
61
PD 14
REXT 20
SW 18
R56100K_0402_5% R56100K_0402_5%
12
RV13
4.7K_0402_5%
@
RV13
4.7K_0402_5%
@
12
C279 0.1U_0402_10V6KC279 0.1U_0402_10V6K
1 2
CV12
0.1U_0402_25V6
CV12
0.1U_0402_25V6
12
C482
10U_0805_10V6K
C482
10U_0805_10V6K
1
2
R621M_0402_5% R621M_0402_5%
12
RV14
4.7K_0402_5%
@
RV14
4.7K_0402_5%
@
12
CV14
0.1U_0402_25V6
CV14
0.1U_0402_25V6
12
RV19
4.99K_0402_1%
RV19
4.99K_0402_1%
12
C283 0.1U_0402_10V6KC283 0.1U_0402_10V6K
1 2
R8015.1M_0603_1% R8015.1M_0603_1%
12
RV15
4.7K_0402_5%
@
RV15
4.7K_0402_5%
@
12
Q336B
DMN66D0LDW-7_SOT363-6
Q336B
DMN66D0LDW-7_SOT363-6
3
5
4
CV11
0.01U_0402_16V7K
CV11
0.01U_0402_16V7K
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Remove BATT low CKT
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DPSRC_3_P
DPSRC_3_N
Lane N/P Swap configuration
Lane N/P Swap
TBT_RSENSE
TBT_RBIAS
TBT_ROM_CLK
PLTRST_TBT#
TBT_ROM_WP#
TBT_ROM_CS#
TBT_ROM_DO
TBT_ROM_DI
TBT_ROM_HOLD#
TBT_SLP_S5#_BUFF
TBT_DP_P0_C
TBT_DP_N0_C
TBT_DP_N1_C
TBT_DP_P2_C
TBT_DP_N2_C
TBT_DP_N3_C
TBT_DP_P3_C
TBT_DP_AUX_C
TBT_DP_AUX#_C
CLK_PCIE_TBT#
CLK_PCIE_TBT
TBT_PCIECLK_REQ#
TBT_ROM_CS#
TBT_ROM_DO
TBT_ROM_DI
TBT_ROM_CLK
TBT_JTAG_TDO
TBT_JTAG_TCK
TBT_JTAG_TMS
TBT_JTAG_TDI
TBT_JTAG_TDO
TBT_JTAG_TCK
TBT_JTAG_TMS
TBT_JTAG_TDI
TBT_TEST_EN
TBT_TEST_PWRG
TBT_DP_HPD
TBT_CIO_TX_P0_C
TBT_CIO_TX_N0_CTBT_CIO_TX_N0
TBT_CIO_TX_P0
TBT_CIO_RX_P0
TBT_CIO_RX_N0
TBT_CIO_RX_P0_C
TBT_CIO_RX_N0_C
TBT_CIO_TX_P1_C
TBT_CIO_TX_N1_CTBT_CIO_TX_N1
TBT_CIO_TX_P1
TBT_CIO_RX_P1TBT_CIO_RX_P1_C
TBT_CIO_RX_N1TBT_CIO_RX_N1_C
TBT_CONFIG1_BUF
TBT_CONFIG2_BUF
TBT_LSRX
TBT_LSTX
DP_TBT_ML3_N
DP_TBT_ML3_P
DP_TBT_ML3_N_C
DP_TBT_ML3_P_C
DP_TBT_ML1_P
DP_TBT_ML1_N
DP_TBT_ML1_P_C
DP_TBT_ML1_N_C
DPSRC_HPD
DPSRC_AUX_C
DPSRC_AUX#_C
DPSRC_AUX
DPSRC_AUX#
TBT_HV_EN
TBT_CIO_SEL
TBT_DP_PWRDN
TBT_DP_PWRDN
XTAL_25_IN
XTAL_25_OUT
TBT_CIO_PLUG_EVENT#
TBT_CIO_PLUG_EVENT#
EN_CIO_PWR#
EN_CIO_PWR#
TBT_WAKE#
TBT_HV_EN
TBT_SLP_S3#_BUFF
TBT_RTD3_PWR_EN
TBT_FORCE_PWR
TBT_BATLOW#_BUFF
TBT_POC_RST#
TBT_SLP_S3#_BUFF
TBT_DP_P1_C
TBT_RTD3_PWR_EN
TBT_FORCE_PWR
TBT_CIO_SEL
PCIE_PRX_TBTX_N5_C
PCIE_PRX_TBTX_P5_C
PCIE_PTX_TBRX_P6_C
PCIE_PTX_TBRX_N6_C
PCIE_PTX_TBRX_P5_C
PCIE_PTX_TBRX_N5_C
PCIE_PRX_TBTX_P6_C
PCIE_PRX_TBTX_N6_C
TBT_POC_RST#
XTAL_25_OUT_R
TBT_BATLOW#_BUFF
+3.3V_TBT_LC+3.3V_TBT_LC
+3.3V_TBT_LC
+3.3V_TBT
+3.3V_TBT
+3.3V_TBT +3.3V_TBT
+3.3V_TBT_LC
+3.3V_TBT
TBT_DP_N0<31>
TBT_DP_P0<31>
TBT_DP_N1<31>
TBT_DP_P1<31>
TBT_DP_N2<31>
TBT_DP_P2<31>
TBT_DP_N3<31>
TBT_DP_P3<31>
TBT_DP_AUX#<31,33>
TBT_DP_AUX<31,33>
TBT_DP_HPD<31>
PLTRST_TBT#<19>
CLK_PCIE_TBT<20>
CLK_PCIE_TBT#<20>
TBT_PCIECLK_REQ#<20>
TBT_CONFIG2_BUF <33>
TBT_CONFIG1_BUF <31,33>
TBT_LSRX <33>
TBT_CIO_RX_P0 <33>
TBT_CIO_TX_P0_C <33>
TBT_CIO_TX_N0_C <33>
TBT_CIO_RX_N0 <33>
TBT_CIO_RX_P1 <33>
TBT_CIO_TX_P1_C <33>
TBT_CIO_TX_N1_C <33>
TBT_CIO_RX_N1 <33>
TBT_LSTX <33>
DP_TBT_ML3_N_C <33>
DP_TBT_ML3_P_C <33>
DP_TBT_ML1_P_C <33>
DP_TBT_ML1_N_C <33>
DPSRC_HPD <33>
DPSRC_AUX#_C <33>
DPSRC_AUX_C <33>
TBT_HV_EN <60>
TBT_CIO_SEL <33>
TBT_DP_PWRDN <33>
EN_CIO_PWR# <34>
TBT_CIO_PLUG_EVENT# <23>
SIO_SLP_S3# <19,41,51,54>
TBT_FORCE_PWR <23>
SIO_SLP_S5# <19,41,51>
TBT_SLP_S5#_BUFF<33>
PCIE_WAKE# <17,42,50>
PCIE_PRX_TBTX_N5<22>
PCIE_PRX_TBTX_P5<22>
PCIE_PTX_TBRX_P6<22>
PCIE_PTX_TBRX_N6<22>
PCIE_PTX_TBRX_P5<22>
PCIE_PTX_TBRX_N5<22>
PCIE_PRX_TBTX_N6<22>
PCIE_PRX_TBTX_P6<22>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
BWD-TBT-LP(1/3) DP,PCIE
32 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
BWD-TBT-LP(1/3) DP,PCIE
32 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
BWD-TBT-LP(1/3) DP,PCIE
32 67Monday, January 13, 2014
Compal Electronics, Inc.
C609 0.1U_0402_10V7KTB@C609 0.1U_0402_10V7KTB@ 1 2
RT10 3.3K_0402_5%TB@RT10 3.3K_0402_5%TB@
12
CT39 0.22U_0402_10V6KTB@CT39 0.22U_0402_10V6KTB@ 1 2
R770
10K_0402_5%
TB@ R770
10K_0402_5%
TB@
12
RT102 10K_0402_5%TB@RT102 10K_0402_5%TB@ 1 2
C1413 0.1U_0402_10V6KTB@C1413 0.1U_0402_10V6KTB@ 1 2
C620 0.1U_0402_10V7KTB@C620 0.1U_0402_10V7KTB@ 1 2
CT42 0.47U_0402_6.3V6KTB@CT42 0.47U_0402_6.3V6KTB@ 1 2
C616 0.1U_0402_10V7KTB@C616 0.1U_0402_10V7KTB@ 1 2
CT32 0.22U_0402_10V6KTB@CT32 0.22U_0402_10V6KTB@ 1 2
CT41 0.1U_0402_10V6KTB@CT41 0.1U_0402_10V6KTB@ 12
C351 0.1U_0402_10V6KTB@C351 0.1U_0402_10V6KTB@ 1 2
CT153
.1U_0402_16V7K
TB@ CT153
.1U_0402_16V7K
TB@
12
YT1
25MHZ_18PF_X3G025000DI1H-H
TB@YT1
25MHZ_18PF_X3G025000DI1H-H
TB@
IN 1
GND 2
OUT
3
GND
4
UT2
W25X40CLSSIG_SO8
TB@UT2
W25X40CLSSIG_SO8
TB@
CS# 1
DO(IO1) 2
WP# 3
GND 4
DI(IO0)
5CLK
6HOLD#
7VCC
8
C602 0.1U_0402_10V7KTB@C602 0.1U_0402_10V7KTB@ 1 2
CT33 0.22U_0402_10V6KTB@CT33 0.22U_0402_10V6KTB@ 1 2
C353 0.1U_0402_10V6KTB@C353 0.1U_0402_10V6KTB@ 1 2
CT1
.1U_0402_16V7K
TB@ CT1
.1U_0402_16V7K
TB@
12
R777
10K_0402_5%
TB@ R777
10K_0402_5%
TB@
12
C1412 0.1U_0402_10V6KTB@C1412 0.1U_0402_10V6KTB@ 1 2
R780
10K_0402_5%
TB@ R780
10K_0402_5%
TB@
12
CT52
20P_0402_50V8
TB@CT52
20P_0402_50V8
TB@
12
C625 0.1U_0402_10V7KTB@C625 0.1U_0402_10V7KTB@ 1 2
C599 0.1U_0402_10V7KTB@C599 0.1U_0402_10V7KTB@ 1 2
CT44 0.47U_0402_6.3V6KTB@CT44 0.47U_0402_6.3V6KTB@ 1 2
R778
10K_0402_5%
TB@ R778
10K_0402_5%
TB@
12
RT101 10K_0402_5%TB@RT101 10K_0402_5%TB@ 1 2
RT4
100K_0402_5%
TB@ RT4
100K_0402_5%
TB@
12
RT2 100K_0402_5%TB@RT2 100K_0402_5%TB@
1 2
PCIe
TBT Port
DP_Port
UT1B
DSL5110-QFW9-A0_FSSCP185_8X8~D
TB@
PCIe
TBT Port
DP_Port
UT1B
DSL5110-QFW9-A0_FSSCP185_8X8~D
TB@
CIO1_TX_P_DPSRC_2_P H17
CIO1_TX_N_DPSRC_2_N G17
CIO0_TX_P_DPSRC_0_P E17
CIO0_TX_N_DPSRC_0_N D17
PERP_0
R13
PERN_0
N13
PERP_1
R15
PERN_1
N15
PETP_0
T9
PETN_0
T10
PETP_1
T12
PETN_1
T13
REFCLK_100_IN_P
N16
REFCLK_100_IN_N
N17
POC_RST_N M1
CIO0_RX_N F14
CIO0_RX_P G14
CIO1_RX_P K14
CIO1_RX_N J14
PCIE_CLKREQ_OD_N
R2 LSTX J2
LSRX H1
DP_SNK0_0_P
B12
DP_SNK0_0_N
A12
DP_SNK0_1_P
B10
DP_SNK0_1_N
A10
DP_SNK0_2_P
B8
DP_SNK0_2_N
A8
DP_SNK0_3_P
B6
DP_SNK0_3_N
A6
DP_SNK0_AUX_P
D2
DP_SNK0_AUX_N
D1
DPSNK0_HPD
T3
XTAL_25_IN S16
XTAL_25_OUT R17
RSENSE L16
RBIAS L17
EE_DI
T4
EE_DO
T6
EE_CS_N
S6
EE_CLK
S5
TDI
P2
TMS
S3
TCK
R1
TDO
S4
MONDC0
T16
MONDC1
T17
MONOBSP
T15
MONOBSN
S15
TEST_EN
L2
TEST_PWR_GOOD
N1
THERMDA
T7
RSVD1_GND
T1
RTD3_PWR_EN L1
SLP_S3# M2
PERST_N_OD
S7
FORCE_PWR H2
WAKE_N_OD S2
DPSRC_3_N A16
DPSRC_3_P B16
DPSRC_1_P B14
DPSRC_1_N A14
CONFIG1 J1
CONFIG2 G2
DPSRC_AUX_P E2
DPSRC_AUX_N E1
DPSRC_HPD F2
HV_EN K1
CIO_SEL F1
DP_PWRDN K2
CIO_PLUG_EVENT_N_OD P1
EN_CIO_PWR_N_OD N2
BATLOW_N_OD G1
SVR_AMON
E7
RSVD2_GND
K4
RSVD
T5
CT43 0.47U_0402_6.3V6KTB@CT43 0.47U_0402_6.3V6KTB@ 1 2
CT54
20P_0402_50V8
TB@CT54
20P_0402_50V8
TB@
12
CT155
2700P_0402_50V7K
TB@ CT155
2700P_0402_50V7K
TB@
12
RT103 10K_0402_5%TB@RT103 10K_0402_5%TB@ 1 2
C354 0.1U_0402_10V6KTB@C354 0.1U_0402_10V6KTB@ 1 2
R767
10K_0402_5%
TB@ R767
10K_0402_5%
TB@
12
C1415 0.1U_0402_10V6KTB@C1415 0.1U_0402_10V6KTB@ 1 2
RT5
31.6K_0402_1%~D
TB@ RT5
31.6K_0402_1%~D
TB@
12
UT12
74LVC1G17GW_TSSOP5
TB@ UT12
74LVC1G17GW_TSSOP5
TB@
O
4I2
P5
G
3
NC
1
R769
10K_0402_5%
TB@ R769
10K_0402_5%
TB@
12
R784 100_0402_1%TB@R784 100_0402_1%TB@
1 2
R3729
10K_0402_5%
TB@ R3729
10K_0402_5%
TB@
12
CT40 0.1U_0402_10V6KTB@CT40 0.1U_0402_10V6KTB@ 12
CT154
.1U_0402_16V7K
TB@ CT154
.1U_0402_16V7K
TB@
12
CT28 0.22U_0402_10V6KTB@CT28 0.22U_0402_10V6KTB@ 1 2
R766
10K_0402_5%
TB@ R766
10K_0402_5%
TB@
12
CT151
.1U_0402_16V7K
TB@ CT151
.1U_0402_16V7K
TB@
12
CT37 0.22U_0402_10V6KTB@CT37 0.22U_0402_10V6KTB@ 1 2
R792
10K_0402_5%
TB@R792
10K_0402_5%
TB@
12
CT29 0.22U_0402_10V6KTB@CT29 0.22U_0402_10V6KTB@ 1 2
RPT5
10K_0804_8P4R_5%
TB@ RPT5
10K_0804_8P4R_5%
TB@
1 8
2 7
3 6
4 5
C624 0.1U_0402_10V7KTB@C624 0.1U_0402_10V7KTB@ 1 2
R783 10K_0402_5%TB@R783 10K_0402_5%TB@
1 2
CT36 0.22U_0402_10V6KTB@CT36 0.22U_0402_10V6KTB@ 1 2
R790
10K_0402_5%
TB@R790
10K_0402_5%
TB@
12
C355 0.1U_0402_10V6KTB@C355 0.1U_0402_10V6KTB@ 1 2
CT50 0.47U_0402_6.3V6KTB@CT50 0.47U_0402_6.3V6KTB@ 1 2
C352 0.1U_0402_10V6KTB@C352 0.1U_0402_10V6KTB@ 1 2
RT26 0_0402_5%TB@RT26 0_0402_5%TB@
1 2
RT25 1K_0402_1%TB@RT25 1K_0402_1%TB@
12
C600 0.1U_0402_10V7KTB@C600 0.1U_0402_10V7KTB@ 1 2
C365 0.1U_0402_10V6KTB@C365 0.1U_0402_10V6KTB@ 1 2
CT38 0.22U_0402_10V6KTB@CT38 0.22U_0402_10V6KTB@ 1 2
UT3
TPS3895ADRYT_SON6
TB@UT3
TPS3895ADRYT_SON6
TB@
VCC
6
EN
1
OUT 4
GND 2
SENSE
3
CT
5
R11450_0402_5% TB@R11450_0402_5% TB@
12
UT14
74LVC1G17GW_TSSOP5
TB@ UT14
74LVC1G17GW_TSSOP5
TB@
O
4I2
P5
G
3
NC
1
C363 0.1U_0402_10V6KTB@C363 0.1U_0402_10V6KTB@ 1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Design guide:
1*100u
1*22u
1*0.1u
EN
0 0
HV_EN OUT
OPEN
V3P3
VHV
0 1
1 0
1 1
OPEN
Current design (12V) = 1.06A
Current design (3V) = 1.18A
CIS link OK
2012/10/18 INTEL: this 12.1 ohm is still required
for JAE or Lintes TBT connector
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
TBT_CONFIG2_RC
TBT_CIO_RX_N0
TBT_CONFIG1_RC
TBT_CIO_RX_P0
TPS22980_HV_EN
ISET_V3P3
ISET_S3
ISET_S0
TPS22980_HV_EN
UT6_S0
TBT_CIO_TX_P0_C
TBT_CIO_TX_N0_C
TBT_CIO_TX_P1_C
TBT_CIO_TX_N1_C
DP_TBT_ML3_P_C
DP_TBT_ML3_N_C
TBT_SLP_S5#_BUFF
TBT_AUX_CHP
TBT_AUX_CHN
TBT_CONFIG1_RC
TBT_HPD
DP_LSTX_ML1_P
DP_LSRX_ML1_N
TBT_DP_PWRDN
TBT_CIO_SEL
TBT_CIO_RX_P1
TBT_CIO_RX_N1
DPSRC_AUX_C
DPSRC_AUX#_C
TBT_DP_AUX
TBT_DP_AUX#
DP_TBT_ML1_P_C
DP_TBT_ML1_N_C
DPSRC_HPD
TBT_CONFIG1_BUF
TBT_LSRX
TBT_LSTX
TBT_HPD
TBT_CIO_TX_P0_C
TBT_CIO_TX_N0_C
TBT_CIO_RX_P0
TBT_CIO_RX_N0
DP_LSTX_ML1_P
DP_LSRX_ML1_N
DP_TBT_ML3_P_C
DP_TBT_ML3_N_C
TBT_CIO_TX_P1_C
TBT_CIO_TX_N1_C
TBT_AUX_CHP
TBT_AUX_CHN
TBT_DP_AUX
TBT_DP_AUX#
+12VS_TB
+3.3V_TBT
+12VS_TB
+3.3V_TBT
+3.3V_TBT
+3.3V_TBT
+3.3V_TBT
+VCC3V3_SW_TBT
+VCC_TBT
+VCC3V3_SW_TBT
+3.3V_TBT_LC
+VCC_TBT
+VCC3V3_SW_TBT
TBT_CONFIG2_BUF<32>
TBT_SLP_S5#_BUFF<32>
TBT_DP_PWRDN <32>
TBT_CIO_SEL <32>
TBT_CIO_RX_P1<32>
TBT_CIO_RX_N1<32>
DPSRC_AUX#_C<32>
DPSRC_AUX_C<32>
TBT_DP_AUX#<31,32>
TBT_DP_AUX<31,32>
DP_TBT_ML1_P_C<32>
DP_TBT_ML1_N_C<32>
DPSRC_HPD<32>
TBT_LSTX<32>
TBT_LSRX<32>
TBT_CONFIG1_BUF<31,32>
TBT_CIO_TX_P0_C<32>
TBT_CIO_TX_N0_C<32>
TBT_CIO_RX_P0<32>
TBT_CIO_RX_N0<32>
DP_TBT_ML3_P_C<32>
DP_TBT_ML3_N_C<32>
TBT_CIO_TX_P1_C<32>
TBT_CIO_TX_N1_C<32>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
BWD-TBT-LP(2/3) HOST,mDP
33 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
BWD-TBT-LP(2/3) HOST,mDP
33 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
BWD-TBT-LP(2/3) HOST,mDP
33 67Monday, January 13, 2014
Compal Electronics, Inc.
CT56
330P_0402_50V7K
TB@CT56
330P_0402_50V7K
TB@
12
QT353A
DMN66D0LDW-7_SOT363-6
TB@ QT353A
DMN66D0LDW-7_SOT363-6
TB@
61
2
RT45 470K_0402_5%TB@RT45 470K_0402_5%TB@
1 2
AUX
MUX
2:1
S
Control
DP
MUX
2:1
S
HIGH= DDC
HIGH= LSXX
LOW = AUX
LOW = DPX
10G
MUX
2:1
E
UT11
CBTL05024BS_HVQFN24_3X3
TB@
AUX
MUX
2:1
S
Control
DP
MUX
2:1
S
HIGH= DDC
HIGH= LSXX
LOW = AUX
LOW = DPX
10G
MUX
2:1
E
UT11
CBTL05024BS_HVQFN24_3X3
TB@
AUXIO_EN 24
AUX+
2
AUX-
1
DDC_DAT
4DDC_CLK
5
CA_DETOUT
16
DP+
11
DP-
10
LSTX
14
LSRX
13
DP_PD 6
HPDOUT
12
AUXIO+ 22
AUXIO- 23
CA_DET 18
DPMLO+ 19
DPMLO- 20
GND
9
GND
21
TPAD
25
HPD 17
VDD 3
TB_ENA 15
TB-
7TB+
8
RT49 470K_0402_5%TB@RT49 470K_0402_5%TB@
1 2
RT48 470K_0402_5%TB@RT48 470K_0402_5%TB@
1 2
QT353B
DMN66D0LDW-7_SOT363-6
TB@ QT353B
DMN66D0LDW-7_SOT363-6
TB@
3
5
4
RT96
35.7K_0402_1%
TB@ RT96
35.7K_0402_1%
TB@
12
CT132
.1U_0402_16V7K
TB@ CT132
.1U_0402_16V7K
TB@
12
CT160
10U_0805_25V6K
TB@ CT160
10U_0805_25V6K
TB@
12
CT159
10U_0805_10V4Z
TB@ CT159
10U_0805_10V4Z
TB@
1
2
CT51
0.47U_0402_6.3V6K
TB@CT51
0.47U_0402_6.3V6K
TB@
12
RT7 100K_0402_5%TB@RT7 100K_0402_5%TB@
1 2
RT50 470K_0402_5%TB@RT50 470K_0402_5%TB@
1 2
CT142
4.7U_0805_25V6-K
TB@ CT142
4.7U_0805_25V6-K
TB@
12
RT61
1K_0402_5%
TB@ RT61
1K_0402_5%
TB@
1 2
RT65
1M_0402_5%
TB@ RT65
1M_0402_5%
TB@
1 2
RT94
35.7K_0402_1%
TB@ RT94
35.7K_0402_1%
TB@
12
+
CT133
100U_B2_6.3VM_R35M
TB@
+
CT133
100U_B2_6.3VM_R35M
TB@
1
2
RT104 4.7K_0402_5%TB@RT104 4.7K_0402_5%TB@
12
CT131
.1U_0402_16V7K
TB@ CT131
.1U_0402_16V7K
TB@
12
RT100
10K_0402_5%
TB@ RT100
10K_0402_5%
TB@
12
CT129
.1U_0402_16V7K
TB@ CT129
.1U_0402_16V7K
TB@
12
RT105 4.7K_0402_5%TB@RT105 4.7K_0402_5%TB@
12
RT54
100K_0402_5%
TB@ RT54
100K_0402_5%
TB@
12
RT60
1K_0402_5%
TB@ RT60
1K_0402_5%
TB@
1 2
RT47 470K_0402_5%TB@RT47 470K_0402_5%TB@
1 2
CT158
.1U_0402_16V7K
TB@ CT158
.1U_0402_16V7K
TB@
12
JTHB1
LOTES_GAP-ADIS0008-P005A01
CONN@
JTHB1
LOTES_GAP-ADIS0008-P005A01
CONN@
PWR_IN
1
HPD_GND
2
TBT_HD2CA_0+
3
TBT_CA2HD_0+
4
TBT_HD2CA_0-
5
TBT_CA2HD_0-
6
GND
7
GND
8
LSTX
9
RESERVED
10
LSRX
11
RESERVED
12
GND
13
GND
14
TBT_HD2CA_1+
15
TBT_CA2HD_1+
16
TBT_HD2CA_1-
17
TBT_CA2HD_1-
18
RETURN
19
PWR_OUT
20 G21
G22
UT6
TPS22981RGPR_QFN20_4X4
TB@UT6
TPS22981RGPR_QFN20_4X4
TB@
EN
5
GND
3GND
2
FAULTZ
4
GND
1
HV_EN
11
S0
17
ISET_V3P3
8
ISET_S0
10 ISET_S3
9
OUT 12
OUT 14
V3P3OUT 18
GND 15
ENHVU 16
GND
13
TPad
21
V3P3 19
V3P3 20
VHV 6
VHV 7
CT150
.1U_0402_16V7K
TB@ CT150
.1U_0402_16V7K
TB@
12
CT55
330P_0402_50V7K
TB@CT55
330P_0402_50V7K
TB@
12
CT45 0.01U_0402_16V7KTB@CT45 0.01U_0402_16V7KTB@
1 2
RT46 470K_0402_5%TB@RT46 470K_0402_5%TB@
1 2
CT49
0.01U_0402_16V7K
TB@CT49
0.01U_0402_16V7K
TB@
12
RT98 10K_0402_5%TB@RT98 10K_0402_5%TB@
1 2
CT134
22U_0805_6.3VAM
TB@ CT134
22U_0805_6.3VAM
TB@
12
RT99
10K_0402_5%
TB@ RT99
10K_0402_5%
TB@
12
RT95
35.7K_0402_1%
TB@ RT95
35.7K_0402_1%
TB@
12
CT46 0.01U_0402_16V7KTB@CT46 0.01U_0402_16V7KTB@
1 2
CT53
0.01U_0402_16V7K
TB@CT53
0.01U_0402_16V7K
TB@
12
RT66
12.1_0402_1%
TB@ RT66
12.1_0402_1%
TB@
12
UT9
74LVC1G17GW_TSSOP5
TB@ UT9
74LVC1G17GW_TSSOP5
TB@
O
4I2
P5
G
3
NC
1
CT127
0.01U_0402_16V7K
TB@CT127
0.01U_0402_16V7K
TB@
12
RT64
1M_0402_5%
TB@ RT64
1M_0402_5%
TB@
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
TBT Power circuit
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
+1.0_TBT_SVR_OUT
+1.05V_CIO_U39
EN_CIO_PWR_EN
TBT_PWR_EN
+1.05V_RDV_DECAP
+3.3V_RDV_DECAP
+3.3V_TBT_LC
+1.05V_TBT_CIO
+1.05V_TBT_SVR
+1.05V_TBT_SVR
+1.05V_TBT_CIO
+3.3V_TBT
+3.3V_TBT
+1.05V_TBT_SVR
+3.3V_TBT
+3.3V_ALW
+5V_ALW
+3.3V_TBT_PWR
EN_CIO_PWR#<32>
TBT_PWR_EN<50>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
BWD-TBT-LP(3/3) VCC/VSS
34 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
BWD-TBT-LP(3/3) VCC/VSS
34 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
BWD-TBT-LP(3/3) VCC/VSS
34 67Monday, January 13, 2014
Compal Electronics, Inc.
CT140
1U_0402_6.3V6K
TB@ CT140
1U_0402_6.3V6K
TB@
12
LT702 0.68UH_PHT25201B-R68MS_2.97A_20%TB@LT702 0.68UH_PHT25201B-R68MS_2.97A_20%TB@ 1 2
CT145
1U_0402_6.3V6K
TB@ CT145
1U_0402_6.3V6K
TB@
12
CT156
10U_0805_10V4Z
TB@ CT156
10U_0805_10V4Z
TB@
1
2
CT114
1U_0402_6.3V6K
TB@ CT114
1U_0402_6.3V6K
TB@
12
CT137
1U_0402_6.3V6K
TB@ CT137
1U_0402_6.3V6K
TB@
12
CT164
10U_0805_10V4Z
TB@ CT164
10U_0805_10V4Z
TB@
1
2
CT116
1U_0402_6.3V6K
TB@ CT116
1U_0402_6.3V6K
TB@
12
C1417
470P_0402_50V7K
TB@C1417
470P_0402_50V7K
TB@
1
2
CT161
10U_0805_10V4Z
TB@ CT161
10U_0805_10V4Z
TB@
1
2
CT165
10U_0805_10V4Z
TB@ CT165
10U_0805_10V4Z
TB@
1
2
CT115
1U_0402_6.3V6K
TB@ CT115
1U_0402_6.3V6K
TB@
12
INOUTINOUT
UT1A
DSL5110-QFW9-A0_FSSCP185_8X8~D
TB@
INOUTINOUT
UT1A
DSL5110-QFW9-A0_FSSCP185_8X8~D
TB@
VSSPE P17
VSSPE P14
VSSPE
P11
VSSPE
B9
VSSPE
A13 VSSPE
A11
VSSPE P16
VSSPE
B11
VSSPE
B13
VSSPE
B17
VSSPE
E13
VSSPE
F16
VSSPE
G16
VSSPE
J16
VSSPE
K13
VSSPE
A17
VSSPE
B5
VSSPE
D10
VSSPE
E16
VSSPE
M16 VSSPE
L14
VCC1P0_SVR_ANA M17
VSSPE
L13
VSSPE R16
VSSPE S8
VSSPE
K16
VCC3P3 E4
VCC3P3 G4
VSS C1
VSS S1
VSS C2
VSS T2
VSS L4
VSSPE
A5
VSSPE
A7
VSSPE
A9
VSSPE
A15
VSSPE
B15
VSSPE
D8
VSSPE
G13
VSSPE
H14
VSSPE
B7
VSSPE S9
VSSPE S10
VSSPE S11
VSSPE S12
VSSPE S13
VSSPE S14
VSSPE S17
VSSPE T8
VSSPE T11
SVR_VCC3P3 A4
SVR_VCC3P3 B4
SVR_IND B1
SVR_VSS A3
SVR_VSS B3
SVR_IND A1
VCC3P3_RDV_DP_AUX
D5
VCC1P0_RDV_ANA
E8
VCC1P0_RDV_ANA
E10
VCC1P0_RDV_ANA
D14
VCC1P0_RDV_ANA
H13
VSS G5
VSS G7
VSS K7
VSS L7
VCC1P0_RDV_ANA
N10
VCC1P0_RDV_ANA
P10
VCC3P3A E5
SVR_VCC1P0 H10
SVR_VCC1P0 H8
SVR_VCC1P0 H5
VCC1P0_RDV_DECAP
G8
VCC1P0_RDV_DECAP
G10
VCC1P0_RDV_DECAP
E11
VCC1P0_RDV_DECAP
D13
VCC1P0_RDV_DPAUX
H4
VCC3P3_RDV_DP
D7
VCC3P3_RDV_DP
D11
VCC3P3_LC
N4
VSSPE
E14
VSSPE
N11
VSS N7
VSS P7
VSS K10
VSS L10
VSS G11
VSS H11
VSS L11
SVR_VCC3P3 D4
VCC1P0_CIO H7
VCC1P0_CIO K5
VCC1P0_CIO K8
VCC1P0_CIO L5
VCC1P0_CIO L8
VCC1P0_CIO N5
VCC1P0_CIO N8
VCC1P0_CIO P5
VCC1P0_CIO P8
VCC1P0_RDV_DECAP
K11
VCC3P3_RDV_CIO
K17
VCC3P3_RDV_DECAP
P4
SVR_IND B2
SVR_VSS A2
VSSPE
C16
VSSPE
C17
VSSPE
F17
VSSPE
J17
VSSPE T14
CT128
10U_0805_10V4Z
TB@ CT128
10U_0805_10V4Z
TB@
1
2
CT130
10U_0805_10V4Z
TB@ CT130
10U_0805_10V4Z
TB@
1
2
CT138
1U_0402_6.3V6K
TB@ CT138
1U_0402_6.3V6K
TB@
12
CT146
1U_0402_6.3V6K
TB@ CT146
1U_0402_6.3V6K
TB@
12
CT144
1U_0402_6.3V6K
TB@ CT144
1U_0402_6.3V6K
TB@
12
DT92
NSR1020MW2T1G_SOD323-2
TB@DT92
NSR1020MW2T1G_SOD323-2
TB@
2 1
CT141
1U_0402_6.3V6K
TB@ CT141
1U_0402_6.3V6K
TB@
12
CT120
10U_0805_10V4Z
TB@ CT120
10U_0805_10V4Z
TB@
1
2
CT147
1U_0402_6.3V6K
TB@ CT147
1U_0402_6.3V6K
TB@
12
CT122
1U_0402_6.3V6K
TB@ CT122
1U_0402_6.3V6K
TB@
12
CT162
10U_0805_10V4Z
TB@ CT162
10U_0805_10V4Z
TB@
1
2
C1416
10U_0805_10V4Z
TB@C1416
10U_0805_10V4Z
TB@
1
2
PJP12
PAD-OPEN1x1m
PJP@
PJP12
PAD-OPEN1x1m
PJP@
12
CT148
1U_0402_6.3V6K
TB@ CT148
1U_0402_6.3V6K
TB@
12
CT121
1U_0402_6.3V6K
TB@ CT121
1U_0402_6.3V6K
TB@
12
RT6
100K_0402_5%
TB@ RT6
100K_0402_5%
TB@
1 2
CT135
1U_0402_6.3V6K
TB@ CT135
1U_0402_6.3V6K
TB@
12
CT126
1U_0402_6.3V6K
TB@ CT126
1U_0402_6.3V6K
TB@
12
G
D
S
QT56
DMN65D8LW-7_SOT323-3
TB@
G
D
S
QT56
DMN65D8LW-7_SOT323-3
TB@
2
13
CT149
1U_0402_6.3V6K
TB@ CT149
1U_0402_6.3V6K
TB@
12
CT123
1U_0402_6.3V6K
TB@ CT123
1U_0402_6.3V6K
TB@
12
PJP603
JUMP_43X79
PJP@
PJP603
JUMP_43X79
PJP@
11
2
2
CT139
1U_0402_6.3V6K
TB@ CT139
1U_0402_6.3V6K
TB@
12
CT136
1U_0402_6.3V6K
TB@ CT136
1U_0402_6.3V6K
TB@
12
CT124
1U_0402_6.3V6K
TB@ CT124
1U_0402_6.3V6K
TB@
12
CT117
1U_0402_6.3V6K
TB@ CT117
1U_0402_6.3V6K
TB@
12
CT143
10U_0805_10V4Z
TB@ CT143
10U_0805_10V4Z
TB@
1
2
CT125
1U_0402_6.3V6K
TB@ CT125
1U_0402_6.3V6K
TB@
12
CT118
1U_0402_6.3V6K
TB@ CT118
1U_0402_6.3V6K
TB@
12
CT166
10U_0805_10V4Z
TB@ CT166
10U_0805_10V4Z
TB@
1
2
U633
TPS22965DSGR_SON8_2X2~D
TB@U633
TPS22965DSGR_SON8_2X2~D
TB@
VIN
1
VIN
2
ON
3
VBIAS
4
VOUT 7
VOUT 8
CT
6GND 5
GND 9
CT119
1U_0402_6.3V6K
TB@ CT119
1U_0402_6.3V6K
TB@
12
UT39
TPS22920YZPR_BGA8
TB@UT39
TPS22920YZPR_BGA8
TB@
VOUT A1
VOUT B1
VOUT C1
GND D1
VIN
A2
VIN
B2
VIN
C2
ON
D2
CT163
10U_0805_10V4Z
TB@ CT163
10U_0805_10V4Z
TB@
1
2
CT113
1U_0402_6.3V6K
TB@ CT113
1U_0402_6.3V6K
TB@
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Channel A (MXM)
Channel B (PCH)
Port 1 (MB_CRT)
Port 2 (Dock_CRT)
DSC mode output to MB VGA
CRT_SWITCH DGPU_SELECT# EDID_SELECT#
REDA to RED1
GRNA to GRN1
BLUA to BLU1
SHA to SH1
SVA to SV1
DSC mode output to docking VGA
UMA mode output to MB VGA
UMA mode output to docking VGA
1
0
0
REDA to RED2
GRNA to GRN2
BLUA to BLU2
SHA to SH2
SVA to SV2
SDAA to SDA2
SCLA to SCL2
0
1
1
0
1
1
1
SDAA to SDA1
SCLA to SCL1
0
Output
0
REDB to RED2
GRNB to GRN2
BLUB to BLU2
SDAB to SDA2
SCLB to SCL2
SHB to SH2
SVB to SV2
SHB to SH1
SVB to SV1
REDB to RED1
GRNB to GRN1
BLUB to BLU1
SDAB to SDA1
SCLB to SCL1
Difference with Diesel
CIS link OK
CRT_SWITCH
GREEN_CRT
BLUE_CRT
VSYNC_L
HSYNC_L
GREEN_CRT_L
BLUE_CRT_L
RED_CRT RED_CRT_L
DAT_DDC2_CRT
CLK_DDC2_CRT
+CRT_VCC
CLK_DDC2_CRT
DAT_DDC2_CRT
M_ID2#
CRT_EN
DAT_DDC2_CRT
CLK_DDC2_CRT
BLUE_CRT
RED_CRT
GREEN_CRT
VSYNC_BUFCRT_SWITCH
HSYNC_BUF
CRT_11
HSYNC_BUF
VSYNC_BUF
+CRT_VCC
+CRT_VCC
+3.3V_RUN
+3.3V_RUN
+5V_RUN
+5V_RUN
PCH_CRT_DDC_CLK<19>
PCH_CRT_RED<19>
PCH_CRT_GRN<19>
PCH_CRT_BLU<19>
RED_DOCK <48>
GREEN_DOCK <48>
BLUE_DOCK <48>
DAT_DDC2_DOCK <48>
CLK_DDC2_DOCK <48>
HSYNC_DOCK <48>
VSYNC_DOCK <48>
CRT_SWITCH<50>
EDID_SELECT#<50>
DGPU_SELECT#<29,30,50>
MXM_CRT_VSYNC<17>
MXM_CRT_HSYNC<17>
MXM_CRT_RED<17>
MXM_CRT_GRN<17>
MXM_CRT_BLU<17>
MXM_CRT_DDC_CLK<17>
MXM_CRT_DDC_DAT<17>
PCH_CRT_DDC_DAT<19>
PCH_CRT_VSYNC<19>
PCH_CRT_HSYNC<19>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
VGA CONN
35 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
VGA CONN
35 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
VGA CONN
35 67Monday, January 13, 2014
Compal Electronics, Inc.
L5
BLM15AG121SN1D_L0402_2P
EMC@
L5
BLM15AG121SN1D_L0402_2P
EMC@
1 2
L3 BLM15BB220SN1D_2PEMC@ L3 BLM15BB220SN1D_2PEMC@
1 2
R53
150_0402_1%
R53
150_0402_1%
12
U6
AP2330W-7_SC59-3
U6
AP2330W-7_SC59-3
GND
2
OUT
3
IN 1
T61
PAD~D
@T61
PAD~D
@
C19
22P_0402_50V8J
@
C19
22P_0402_50V8J
@
1
2
C1181
1U_0402_6.3V6K
C1181
1U_0402_6.3V6K
1
2
L1 BLM15BB220SN1D_2PEMC@ L1 BLM15BB220SN1D_2PEMC@
1 2
L4
BLM15AG121SN1D_L0402_2P
EMC@
L4
BLM15AG121SN1D_L0402_2P
EMC@
1 2
R54
150_0402_1%
R54
150_0402_1%
12
R48
2.2K_0402_5%
@
R48
2.2K_0402_5%
@
12
C15
0.1U_0402_16V4Z
C15
0.1U_0402_16V4Z
1
2
R55
150_0402_1%
R55
150_0402_1%
12
R50
1K_0402_5%
@R50
1K_0402_5%
@
12
R47
2.2K_0402_5%
@
R47
2.2K_0402_5%
@
12
C13
10P_0402_50V8J
C13
10P_0402_50V8J
1
2
C1182
1U_0603_10V7K
C1182
1U_0603_10V7K
1
2
C20
22P_0402_50V8J
C20
22P_0402_50V8J
1
2
C18
22P_0402_50V8J
@
C18
22P_0402_50V8J
@
1
2
C23
22P_0402_50V8J
C23
22P_0402_50V8J
1
2
R421 100K_0402_5%R421 100K_0402_5%
1 2
C22
22P_0402_50V8J
C22
22P_0402_50V8J
1
2
C14
1U_0402_6.3V6K
C14
1U_0402_6.3V6K
1
2
G
G
G
G
JCRT1
SUYIN_070449HR015M223ZR
CONN@
G
G
G
G
JCRT1
SUYIN_070449HR015M223ZR
CONN@
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
16
17
18
19
C21
10P_0402_50V8J
C21
10P_0402_50V8J
1
2
MAX14885E
U19
MAX14885EETL+T_TQFN40_5X5~D
MAX14885E
U19
MAX14885EETL+T_TQFN40_5X5~D
SVA
4
SCL1 35
SDA1 34
SDAB
16
S10
39
SH1 37
BLUA
9
SHA
3
BLUB
19
SV1 36
SV2 27
GRN2 23
BLU1 31
SHB
13
GRNA
8
SH2 28
SDA2 25
GRNB
18
SCLB
15
S00
1
RED1 33
S01
40
NC 12
GND
30
GRN1 32
GND
20
GND
10
RED2 24
BLU2 22
SCLA
5
SDAA
6
SVB
14
REDB
17 REDA
7
S11
38
SCL2 26
EN
2
VCC 29
VCC 21
VL 11
GPAD
41
L2 BLM15BB220SN1D_2PEMC@ L2 BLM15BB220SN1D_2PEMC@
1 2
R52
1K_0402_5%
@R52
1K_0402_5%
@
12
C12
10P_0402_50V8J
C12
10P_0402_50V8J
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
CIS LINK OK
DOCK DPD (PORT1) DDC-before PS8331
9/21
INy_PEQ = Programmable input equalization levels
L: default, LEQ, compensate channel loss up to 11.5dB @ HBR2
H: HEQ, compensate channel loss up to 14.5dB @ HBR2
M: LLEQ, compensate channel loss up to 8.5dB @ HBR2
INy_AEQ# = Automatic EQ disable
L: Automatic EQ enable (default)
H: Automatic EQ disable
PI0 = Auto test enable
L: Auto test disable & input offset cancellation enable (default)
H: Auto test enable & input offset cancellation enable
M: Auto test disable & input offset cancellation disable
PC0 = AUX interception disable
L: AUX interception enable, driver configuration is set by link training (default)
H: AUX interception disable, driver output with fixed 800mV and 0dB
M: AUX interception disable, driver output with fixed 400mV and 0dB
PC1 = Output swing adjustment
L: default
H: +20%
M: -16.7%
CPU
MXM
To DEMUX
(PS8338)
DP1_MUX_P0
DP1_MUX_N0
DP1_MUX_P1
DP1_MUX_N1
DP1_MUX_P2
DP1_MUX_N2
DP1_MUX_P3
DP1_MUX_N3
DP1_MUX_AUX
DP1_MUX_AUX#
DP1_MUX_HPD
DP1_MUX_PC1
DP1_MUX_PC0
DP1_MUX_PI0
DP1_MUX_PC1
DP1_MUX_PC0
DP1_MUX_PI0
DP1_MUX_REXT
DP1_MUX_CEXT
DP1_MUX_CA_DET
DP1_MUX_IN2_PEQ
DP1_MUX_IN1_PEQ
DP1_MUX_IN1_AEQ#
DP1_MUX_IN2_AEQ#
DP1_MUX_PC0
DP1_MUX_PC1
DP1_MUX_IN1_AEQ#
DP1_MUX_IN2_AEQ#
DP1_MUX_IN2_PEQ
DP1_MUX_IN1_PEQ
DP1_MUX_IN1_PEQ
DP1_MUX_IN2_PEQ
DP1_MUX_PI0
DP1_MUX_CEXT
PBA_GPU_SEL#
MXM_DPB_P1
MXM_DPB_N1
MXM_DPB_P2
MXM_DPB_N2
MXM_DPB_P0
MXM_DPB_P3
MXM_DPB_N3
MXM_DPB_N0
MXM_DPB_P1_C
MXM_DPB_N1_C
MXM_DPB_P2_C
MXM_DPB_N2_C
MXM_DPB_P0_C
MXM_DPB_P3_C
MXM_DPB_N3_C
MXM_DPB_N0_C
MXM_DPB_AUX_C
MXM_DPB_AUX#_C
MXM_DPB_AUX
MXM_DPB_AUX#
PCH_DDPD_AUX#_C
PCH_DDPD_AUX_C
PCH_DDPD_AUX#
PCH_DDPD_AUX
PCH_DDPD_CTRLCLK
PCH_DDPD_CTRLDATA
DPD_PCH_HPD
MXM_DPB_HPD
DPD_CPU_LANE_P3
DPD_CPU_LANE_P0
DPD_CPU_LANE_N3
DPD_CPU_LANE_N0
DPD_CPU_LANE_P2
DPD_CPU_LANE_N1
DPD_CPU_LANE_N2
DPD_CPU_LANE_P1
DPD_CPU_LANE_P3_C
DPD_CPU_LANE_N1_C
DPD_CPU_LANE_P0_C
DPD_CPU_LANE_N3_C
DPD_CPU_LANE_P2_C
DPD_CPU_LANE_N0_C
DPD_CPU_LANE_N2_C
DPD_CPU_LANE_P1_C
MXM_DPB_AUX
MXM_DPB_AUX#
DP1_MUX_CA_DET
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN+5V_RUN
DP1_MUX_P0 <37>
DP1_MUX_P1 <37>
DP1_MUX_N0 <37>
DP1_MUX_N1 <37>
DP1_MUX_P2 <37>
DP1_MUX_N2 <37>
DP1_MUX_P3 <37>
DP1_MUX_N3 <37>
DP1_MUX_AUX <37>
DP1_MUX_AUX# <37>
DP1_MUX_HPD <37>
DP1_MUX_CA_DET <37>
PBA_GPU_SEL# <50>
MXM_DPB_P0<17>
MXM_DPB_N0<17>
MXM_DPB_P1<17>
MXM_DPB_N1<17>
MXM_DPB_P2<17>
MXM_DPB_N2<17>
MXM_DPB_P3<17>
MXM_DPB_N3<17>
MXM_DPB_AUX#<17>
MXM_DPB_AUX<17>
PCH_DDPD_AUX<19>
PCH_DDPD_AUX#<19>
PCH_DDPD_CTRLCLK<19>
PCH_DDPD_CTRLDATA<19>
DPD_PCH_HPD<19>
MXM_DPB_HPD<17>
DPD_CPU_LANE_P0<9>
DPD_CPU_LANE_N0<9>
DPD_CPU_LANE_P1<9>
DPD_CPU_LANE_N1<9>
DPD_CPU_LANE_P2<9>
DPD_CPU_LANE_N2<9>
DPD_CPU_LANE_N3<9>
DPD_CPU_LANE_P3<9>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
MXM/CPU MUX(PS8331)
36 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
MXM/CPU MUX(PS8331)
36 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
MXM/CPU MUX(PS8331)
36 67Monday, January 13, 2014
Compal Electronics, Inc.
C532 0.1U_0402_10V6KC532 0.1U_0402_10V6K
1 2
C527 0.1U_0402_10V6KC527 0.1U_0402_10V6K
1 2
R124 4.7K_0402_5%@R124 4.7K_0402_5%@
1 2
C516 0.1U_0402_10V6KC516 0.1U_0402_10V6K
1 2
R116 4.7K_0402_5%@R116 4.7K_0402_5%@
1 2
R115 4.7K_0402_5%@R115 4.7K_0402_5%@
1 2
C519 0.1U_0402_10V6KC519 0.1U_0402_10V6K
1 2
C528 0.1U_0402_10V6KC528 0.1U_0402_10V6K
1 2
R118 4.7K_0402_5%@R118 4.7K_0402_5%@
1 2
R121 4.7K_0402_5%@R121 4.7K_0402_5%@
1 2
R722
100K_0402_5%
R722
100K_0402_5%
12
C783
4.7U_0603_6.3V6K
C783
4.7U_0603_6.3V6K
1
2
C525 0.1U_0402_10V6KC525 0.1U_0402_10V6K
1 2
C524 0.1U_0402_10V6KC524 0.1U_0402_10V6K
1 2
C515 0.1U_0402_10V6KC515 0.1U_0402_10V6K
1 2
C517 0.1U_0402_10V6KC517 0.1U_0402_10V6K
1 2
C521 0.1U_0402_10V6KC521 0.1U_0402_10V6K
1 2
C495
0.1U_0402_16V4Z
C495
0.1U_0402_16V4Z
1
2
C533 0.1U_0402_10V6KC533 0.1U_0402_10V6K
1 2
Q343A
DMN66D0LDW-7_SOT363-6
Q343A
DMN66D0LDW-7_SOT363-6
61
2
C530 0.1U_0402_10V6KC530 0.1U_0402_10V6K
1 2
C494
0.1U_0402_16V4Z
C494
0.1U_0402_16V4Z
1
2
C523 0.1U_0402_10V6KC523 0.1U_0402_10V6K
1 2
R119 4.7K_0402_5%@R119 4.7K_0402_5%@
1 2
C529 0.1U_0402_10V6KC529 0.1U_0402_10V6K
1 2
Q347B
DMN66D0LDW-7_SOT363-6
Q347B
DMN66D0LDW-7_SOT363-6
3
5
4
R117 4.7K_0402_5%@R117 4.7K_0402_5%@
1 2
C531 0.1U_0402_10V6KC531 0.1U_0402_10V6K
1 2
C504
0.1U_0402_16V4Z
C504
0.1U_0402_16V4Z
1
2
R122 4.7K_0402_5%@R122 4.7K_0402_5%@
1 2
U629
PS8331BQFN60GTR-A0_QFN60_5X9
U629
PS8331BQFN60GTR-A0_QFN60_5X9
IN1_D2p
6
IN1_D2n
7
IN1_AEQ#
59
IN1_D3p
9
IN1_D3n
10
IN1_HPD
3
IN2_D0p
11
IN2_D0n
12
IN2_HPD
13
IN2_D1p
14
IN2_D1n
15
GND 57
IN2_D2p
16
IN2_D2n
17
OUT_AUXp_SCL 32
OUT_AUXn_SDA 31
REXT 34
CEXT 47
IN2_D3n
20 IN2_D3p
19
OUT_D0p 46
OUT_D0n 45
PD 50
OUT_D1p 43
OUT_D1n 42
I2C_CTL_EN 53
OUT2_D2p 40
OUT2_D2n 39
OUT_D3p 37
OUT_D3n 36
VDD33
26
OUT_HPD 44
CA_DET 48
GND 41
IN2_PEQ/SCL_CTL
51
IN1_PEQ/SDA_CTL
52
IN2_AEQ#
58
IN1_D0p
1
IN1_D0n
2
VDD33
21
IN1_D1p
4
IN1_D1n
5
Epad 61
IN1_SDA
22 IN1_SCL
23
IN2_SDA
24 IN2_SCL
25
IN1_AUXn
27 IN1_AUXp
28
IN2_AUXn
29 IN2_AUXp
30
SW 54
GND 33
GND 18
GND 8
VDD33
35
VDD33
49
VDD33
60
PI0 56
PC0 38
PC1 55
Q347A
DMN66D0LDW-7_SOT363-6
Q347A
DMN66D0LDW-7_SOT363-6
61
2
C522 0.1U_0402_10V6KC522 0.1U_0402_10V6K
1 2
R96
4.99K_0402_1%
R96
4.99K_0402_1%
1 2
R129 4.7K_0402_5%R129 4.7K_0402_5%
1 2
C520 0.1U_0402_10V6KC520 0.1U_0402_10V6K
1 2
C97 2.2U_0402_6.3V6MC97 2.2U_0402_6.3V6M
12
R721
100K_0402_5%
R721
100K_0402_5%
12
R123 4.7K_0402_5%@R123 4.7K_0402_5%@
1 2
R99 4.7K_0402_5%@R99 4.7K_0402_5%@
1 2
Q343B
DMN66D0LDW-7_SOT363-6
Q343B
DMN66D0LDW-7_SOT363-6
3
5
4
C534 0.1U_0402_10V6KC534 0.1U_0402_10V6K
1 2
C499
0.1U_0402_16V4Z
C499
0.1U_0402_16V4Z
1
2
R98 4.7K_0402_5%@R98 4.7K_0402_5%@
1 2
C518 0.1U_0402_10V6KC518 0.1U_0402_10V6K
1 2
R132 4.7K_0402_5%R132 4.7K_0402_5%
1 2
R120 4.7K_0402_5%@R120 4.7K_0402_5%@
1 2
C526 0.1U_0402_10V6KC526 0.1U_0402_10V6K
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DOCK DPD (PORT1) DDC
Dock has high priority when both ports plugged
CV62 CV90 close to pin30 &57
CV66,CV69,CV70 close to pin5,21,51
Port switching control or priority configuration. Internal pull down ~150KΩ, 3.3V I/O
For Control Switching Mode (CFG0 = L):
SW = L: Port1 is selected (default)
SW = H: Port2 is selected
For Automatic Switching Mode (CFG0 = H): (By OUT1_HPD and OUT2_HPD)
SW = L: Port1 has higher priority when both ports are plugged (default)
SW = H: Port2 has higher priority when both ports are plugged
V
CFG0
VSW
H L
Docking
WiGig
From MUX
(PS8331)
DPD_CA_DET_Q
DP1_MUX_AUX
DP1_MUX_AUX#
DPD_CA_DET
W IGIG_AUX
W IGIG_AUX#
W IGIG_CA_DE T
W IGIG_CA_DE T
DP1_MUX_P0_C
DP1_MUX_N0_C
DP1_MUX_P1_C
DP1_MUX_N1_C
DP1_MUX_P2_C
DP1_MUX_N2_C
DP1_MUX_P3_C
DP1_MUX_N3_C
DP1_DEMUX_PI1
DP1_DEMUX_PI0
DP1_DEMUX_PC21
DP1_DEMUX_PC20
DP1_DEMUX_PC11
DP1_DEMUX_PC10
DP1_DEMUX_PEQDP1_DEMUX_PEQ
DP1_DEMUX_PC21
DP1_DEMUX_PC20
DP1_DEMUX_PC11
DP1_DEMUX_PC10
DP1_DEMUX_PI1
DP1_DEMUX_SW
DP1_DEMUX_CFG0
DP1_DEMUX_PI0
DP1_DEMUX_CFG0
DP1_DEMUX_SW
DPD_CA_DET_Q
DPD_DOCK_AUX
DPD_DOCK_AUX#
DP1_MUX_CA_DET
DPD_GPU_LANE_P0
DPD_GPU_LANE_N0
DPD_GPU_LANE_P1
DPD_GPU_LANE_N1
DPD_GPU_LANE_P2
DPD_GPU_LANE_N2
DPD_GPU_LANE_N3
DPD_GPU_LANE_P3
DPD_DOCK_AUX
DPD_DOCK_AUX#
DPD_GPU_HPD
DPD_CA_DET
+5V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
WIGIG_LANE_P0 <42>
WIGIG_LANE_P1 <42>
WIGIG_LANE_N1 <42>
WIGIG_LANE_N0 <42>
WIGIG_LANE_P2 <42>
WIGIG_LANE_P3 <42>
WIGIG_LANE_N3 <42>
WIGIG_LANE_N2 <42>
WIGIG_AUX# <42>
WIGIG_AUX <42>
WIGIG_HPD <42>
DP1_MUX_P3<36>
DP1_MUX_N0<36>
DP1_MUX_P0<36>
DP1_MUX_N1<36>
DP1_MUX_P1<36>
DP1_MUX_N2<36>
DP1_MUX_P2<36>
DP1_MUX_N3<36>
DP1_MUX_AUX#<36>
DP1_MUX_AUX<36>
DP1_MUX_CA_DET<36>
DP1_MUX_HPD<36>
DPD_GPU_LANE_P0 <48>
DPD_GPU_LANE_N0 <48>
DPD_GPU_LANE_P1 <48>
DPD_GPU_LANE_N1 <48>
DPD_GPU_LANE_P2 <48>
DPD_GPU_LANE_N2 <48>
DPD_GPU_LANE_P3 <48>
DPD_GPU_LANE_N3 <48>
DPD_DOCK_AUX <48>
DPD_DOCK_AUX# <48>
DPD_GPU_HPD <48>
DPD_CA_DET <48>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
DP DeMUX (PS8338)
37 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
DP DeMUX (PS8338)
37 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
DP DeMUX (PS8338)
37 67Monday, January 13, 2014
Compal Electronics, Inc.
RV36
4.7K_0402_5%
@
RV36
4.7K_0402_5%
@
12
CV34 0.1U_0402_25V6CV34 0.1U_0402_25V6
1 2
Q355B
DMN66D0LDW-7_SOT363-6
Q355B
DMN66D0LDW-7_SOT363-6
3
5
4
RV37
4.7K_0402_5%
@
RV37
4.7K_0402_5%
@
12
CV35 0.1U_0402_25V6CV35 0.1U_0402_25V6
1 2
RV38
4.7K_0402_5%
@
RV38
4.7K_0402_5%
@
12
RV42 4.7K_0402_5%RV42 4.7K_0402_5%
1 2
CV36 0.1U_0402_25V6CV36 0.1U_0402_25V6
1 2
RV39
4.7K_0402_5%
@
RV39
4.7K_0402_5%
@
12
RV43 4.7K_0402_5%
@
RV43 4.7K_0402_5%
@
1 2
CV37 0.1U_0402_25V6CV37 0.1U_0402_25V6
1 2
R2197
100K_0402_5%
R2197
100K_0402_5%
12
CV42
2.2U_0402_6.3V6M
CV42
2.2U_0402_6.3V6M
12
CV27
0.01U_0402_16V7K
CV27
0.01U_0402_16V7K
12
RV29
4.7K_0402_5%
@
RV29
4.7K_0402_5%
@
12
RV44 4.7K_0402_5%
@
RV44 4.7K_0402_5%
@
1 2
CV38 0.1U_0402_25V6CV38 0.1U_0402_25V6
1 2
Q353B
DMN66D0LDW-7_SOT363-6
Q353B
DMN66D0LDW-7_SOT363-6
3
5
4
RV40
4.7K_0402_5%
@
RV40
4.7K_0402_5%
@
12
RV30
4.7K_0402_5%
@
RV30
4.7K_0402_5%
@
12
RV45 1M_0402_5%RV45 1M_0402_5%
1 2
R2196
4.7K_0402_5%
R2196
4.7K_0402_5%
12
Q353A
DMN66D0LDW-7_SOT363-6
Q353A
DMN66D0LDW-7_SOT363-6
61
2
CV39 0.1U_0402_25V6CV39 0.1U_0402_25V6
1 2
RV31
4.7K_0402_5%
@
RV31
4.7K_0402_5%
@
12
UV2
PS8338BQFN60GTR-A0_QFN60_5X9
UV2
PS8338BQFN60GTR-A0_QFN60_5X9
VDD33
5
IN_D0n
7
IN_D2p
12
IN_D2n
13
IN_D3p
15
IN_D3n
16
IN_D1p
9
IN_D1n
10
IN_D0p
6
VDD33
21
VDD33
30
VDD33
51
VDD33
57
GND
19 GND
11
PC21
53 PC20
54 PC11
55 PC10
56 CFG1
58 CFG0
59
OUT1_D0p 50
OUT1_D0n 49
OUT1_D1p 47
OUT1_D1n 46
OUT1_D2p 45
OUT1_D2n 44
OUT1_D3p 42
OUT1_D3n 41
IN_CA_DET
4
IN_HPD
3
I2C_CTL_EN
2
Pl1/SCL_CTL
1
IN_AUXp
24
IN_AUXn
25
OUT2_D0p 40
OUT2_D0n 39
OUT2_D1p 37
OUT2_D1n 36
OUT2_D2p 35
OUT2_D2n 34
OUT2_D3p 32
OUT2_D3n 31
OUT1_AUXp_SCL 26
OUT1_AUXn_SDA 27
OUT2_AUXp_SCL 28
OUT2_AUXn_SDA 29
OUT1_CA_DET 43
OUT1_HPD 48
OUT2_CA_DET 33
OUT2_HPD 38
PEQ 8
CEXT 17
GND
52
IN_DDC_SCL
22
IN_DDC_SDA
23
Pl0/SDA_CTL
60
PAD(GND)
61
PD 14
REXT 20
SW 18
Q355A
DMN66D0LDW-7_SOT363-6
Q355A
DMN66D0LDW-7_SOT363-6
61
2
RV32
4.7K_0402_5%
@
RV32
4.7K_0402_5%
@
12
R2194
4.7K_0402_5%
R2194
4.7K_0402_5%
12
CV28
0.1U_0402_25V6
CV28
0.1U_0402_25V6
12
RV33
4.7K_0402_5%
@
RV33
4.7K_0402_5%
@
12
CV29
0.1U_0402_25V6
CV29
0.1U_0402_25V6
12
R2195
4.7K_0402_5%
R2195
4.7K_0402_5%
12
RV41
4.99K_0402_1%
RV41
4.99K_0402_1%
12
RV34
4.7K_0402_5%
@
RV34
4.7K_0402_5%
@
12
CV30
0.01U_0402_16V7K
CV30
0.01U_0402_16V7K
12
R2189
100K_0402_5%
R2189
100K_0402_5%
12
RV25 100K_0402_5%RV25 100K_0402_5%
1 2
Q357B
DMN66D0LDW-7_SOT363-6
Q357B
DMN66D0LDW-7_SOT363-6
3
5
4
R2198
4.7K_0402_5%
R2198
4.7K_0402_5%
12
RV28 1M_0402_5%RV28 1M_0402_5%
1 2
CV32 0.1U_0402_25V6CV32 0.1U_0402_25V6
1 2
RV35
4.7K_0402_5%
@
RV35
4.7K_0402_5%
@
12
C1344
0.01U_0402_16V7K
C1344
0.01U_0402_16V7K
1
2
CV31
0.1U_0402_25V6
CV31
0.1U_0402_25V6
12
CV33 0.1U_0402_25V6CV33 0.1U_0402_25V6
1 2
Q357A
DMN66D0LDW-7_SOT363-6
Q357A
DMN66D0LDW-7_SOT363-6
61
2
RV26 100K_0402_5%RV26 100K_0402_5%
1 2
2
2
1
1
B B
A A
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
CIS LINK OK
For Control Switching:
SW = L: DP output is selected
SW = H: TMDS output is selected
DOCK DPC (PORT2) DDC
MODE = L: Control Switching Mode, HDMI ID disable
= H: Automatic Switching Mode, HDMI ID disable
= M: Automatic Switching Mode, HDMI ID enable
TMDS_RT = L: Standard open drain driver
= H: Open drain driver with termination resistors
TMDS_DDCBUF = L: DDC pass through
= H: DDC active buffer
= M: DDC pass through with 40 kohm pull up resistor
DP_CFG1 = L: default, auto test disable & input offset cancellation enable
= H: auto test enable & input offset cancellation enable
= M: auto test disable & input offset cancellation disable
PEQ = L: default, LEQ, compensate channel loss up to 12dB @ HBR2
= H: HEQ, compensate channel loss up to 15dB @ HBR2
= M: LLEQ, compensate channel loss up to 5dB @ HBR2
TMDS_PRE = L: no pre-emphasis
= H: 1.5dB pre-emphasis
= M: 3.0dB pre-emphasis
DP_CFG0 = L: default, automatic EQ enable & AUX interception enable
= H: automatic EQ disable & AUX interception enable
= M: automatic EQ disable & AUX interception disable, no pre-emphasis, 800mVpp swing
EMI request reserve C(3.3pF) for HDMI signals.
EMI request non-pop R451~R456,R458,R459 and
pop L19,L23~25 and HDMI EA have verify it.
Docking DP2
MB_HDMI
MXM
Difference with Diesel
TMDS_RT
internal 150K ohm PD.
Remove 10K ohm
CIS link OK
MXM_DPC_P3
TMDSE_CON_N1
MXM_DPC_P0
MXM_DPC_P1
MXM_DPC_N2
MXM_DPC_P2
MXM_DPC_N3
MXM_DPC_N1
MXM_DPC_N0
TMDSE_CON_P1
HDMI_SDA_SINK
MXM_DPC_P2_C
MXM_DPC_N1_C
MXM_DPC_P1_C
MXM_DPC_N0_C
MXM_DPC_P0_C
MXM_DPC_P3_C
MXM_DPC_N2_C
TMDSE_CON_CLK#
DPC_GPU_HPD
HDMI_HPD_SINK
HDMI_CEC
TMDSE_CON_N0
TMDSE_CON_CLK#
HDMI_SCL_SINK
TMDSE_CON_P1
TMDSE_CON_N1
TMDSE_CON_P2
TMDSE_CON_CLK
HDMI_SDA_SINK
TMDSE_CON_P0
TMDSE_CON_N2
HDMI_HPD_SINK
HDMI_CEC
TMDSE_CON_CLK
DPC_CA_DET
REXT3 REXT3
TMDSE_CON_N2
DP_CFG1
HDMI_SCL_SINK
TMDSE_CON_P2
MXM_DPC_HPD
CEXT
HDMI_SCL_SINK
HDMI_SDA_SINK
TMDSE_RP_N0
TMDSE_RP_N1
TMDSE_RP_P0
TMDSE_RP_P1
TMDSE_RP_CLK#
TMDSE_RP_CLK
DOCKED#
CEXT
TMDSE_RP_N2
TMDSE_RP_P2
HDMI_HPD_SINK
TMDS_DDCBUF
MODE
DOCKED#
DPC_ DOCK_S W _AUX
TMDS_RT
DPC_DOCK_LANE_N3
DPC_DOCK_LANE_P3
DPC_ DOCK_S W _AUX #
DPC_DOCK_LANE_N1
DPC_DOCK_LANE_N2
DPC_DOCK_LANE_P2
TMDS_P RE
DPC_DOCK_LANE_N0
PEQ
DPC_DOCK_LANE_P1
DP_CFG0
DPC_DOCK_LANE_P0
DPC_CA_DET
DPC_DOCK_AUX_Q
MXM_DPC_AUX
MXM_DPC_AUX#
DPC_CA_DET
TMDSE_CON_CLK
TMDSE_CON_N0
TMDSE_CON_P0
TMDSE_CON_CLK#
MODE
DP_CFG0
MODE
DP_CFG0
TMDS_P RE
TMDS_DDCBUF
TMDS_P RE
TMDS_DDCBUF
PEQ
PEQ
TMDS_RT
DP_CFG1
DP_CFG1
DPC_DOCK_AUX_Q
DPC_ DOCK_S W _AUX #
DPC_ DOCK_S W _AUX
TMDSE_RP_CLK#
TMDSE_RP_CLK
TMDSE_RP_P0
TMDSE_CON_N0
TMDSE_CON_P0
TMDSE_RP_N0
TMDSE_RP_N1
TMDSE_CON_P1
TMDSE_CON_N1
TMDSE_RP_P1
TMDSE_RP_P2
TMDSE_CON_N2
TMDSE_CON_P2
TMDSE_RP_N2
MXM_DPC_AUX_C
MXM_DPC_AUX#_C
MXM_DPC_N3_C
+VDISPLAY_VCC
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+5V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+VDISPLAY_VCC
+5V_RUN
DPC_DOCK_LANE_P1 <48>
DPC_DOCK_LANE_N0 <48>
DPC_DOCK_LANE_P0 <48>
DPC_DOCK_LANE_P2 <48>
DPC_DOCK_LANE_N2 <48>
MXM_DPC_HPD<17>
DPC_DOCK_LANE_N1 <48>
DPC_ DOCK_S W _AUX <48>
DPC_DOCK_LANE_N3 <48>
DPC_DOCK_LANE_P3 <48>
DPC_CA_DET <48>
DOCKED<39,50>
DPC_ DOCK_S W _AUX # <48>
MXM_DPC_P1<17>
MXM_DPC_N0<17>
MXM_DPC_P0<17>
MXM_DPC_N2<17>
MXM_DPC_P2<17>
MXM_DPC_N1<17>
MXM_DPC_AUX<17>
MXM_DPC_AUX#<17>
MXM_DPC_N3<17>
MXM_DPC_P3<17>
DPC_GPU_HPD <48>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
HDMI CONN
38 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
HDMI CONN
38 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
HDMI CONN
38 67Monday, January 13, 2014
Compal Electronics, Inc.
G
D
S
Q328
DMN6 5D8LW -7_ SOT323-3
G
D
S
Q328
DMN6 5D8LW -7_ SOT323-3
2
13
C548 0.1U_0402_10V6KC548 0.1U_0402_10V6K
1 2
C1335
3.3P_0402_50V8C
@
C1335
3.3P_0402_50V8C
@
1
2
C546 0.1U_0402_10V6KC546 0.1U_0402_10V6K
1 2
C1333
0.01U_0402_16V7K
C1333
0.01U_0402_16V7K
1
2
Q352B
DMN66D0LDW-7_SOT363-6
Q352B
DMN66D0LDW-7_SOT363-6
3
5
4
R814.7K_0402_5% @R814.7K_0402_5% @
12
C540 0.1U_0402_10V6KC540 0.1U_0402_10V6K
1 2
R462 1.5K_0402_5%R462 1.5K_0402_5%
1 2
R764.7K_0402_5% @R764.7K_0402_5% @
12
R2188
100K_0402_5%
R2188
100K_0402_5%
12
C1338
3.3P_0402_50V8C
@
C1338
3.3P_0402_50V8C
@
1
2
C418
0.1U_0402_16V4Z
C418
0.1U_0402_16V4Z
1
2
R794.7K_0402_5% @R794.7K_0402_5% @
12
L24EMC@
DLW21HN900HQ2L_4P
L24EMC@
DLW21HN900HQ2L_4P
1
1
4
433
22
R521
10K_0402_5%
R521
10K_0402_5%
12
C445
0.1U_0402_16V4Z
@
C445
0.1U_0402_16V4Z
@
1
2
C420
0.1U_0402_16V4Z
C420
0.1U_0402_16V4Z
1
2
Q350B
DMN66D0LDW-7_SOT363-6
Q350B
DMN66D0LDW-7_SOT363-6
3
5
4
C1336
3.3P_0402_50V8C
@
C1336
3.3P_0402_50V8C
@
1
2
C535 0.1U_0402_10V6KC535 0.1U_0402_10V6K
1 2
L19EMC@
DLW21HN900HQ2L_4P
L19EMC@
DLW21HN900HQ2L_4P
1
1
4
433
22
U5
AP2330W-7_SC59-3
U5
AP2330W-7_SC59-3
GND
2
OUT
3
IN 1
C1339
3.3P_0402_50V8C
@
C1339
3.3P_0402_50V8C
@
1
2
R2163
100K_0402_5%
R2163
100K_0402_5%
12
R754.7K_0402_5% R754.7K_0402_5%
12
C551 0.1U_0402_10V6KC551 0.1U_0402_10V6K
1 2
R451 0_0402_5%@R451 0_0402_5%@
1 2
Q350A
DMN66D0LDW-7_SOT363-6
Q350A
DMN66D0LDW-7_SOT363-6
61
2
R459 0_0402_5%@R459 0_0402_5%@
1 2
C1340
3.3P_0402_50V8C
@
C1340
3.3P_0402_50V8C
@
1
2
Q352A
DMN66D0LDW-7_SOT363-6
Q352A
DMN66D0LDW-7_SOT363-6
61
2
R1128100K_0402_5% @R1128100K_0402_5% @
1 2
C550 0.1U_0402_10V6KC550 0.1U_0402_10V6K
1 2
Part Number Description
RO0000002HM HDMI W/Logo:RO0000002HM
HDMI46@
Part Number Description
RO0000002HM HDMI W/Logo:RO0000002HM
HDMI46@
C545 0.1U_0402_10V6KC545 0.1U_0402_10V6K
1 2
R453 0_0402_5%@R453 0_0402_5%@
1 2
R834.7K_0402_5% @R834.7K_0402_5% @
12
C1404 0.1U_0402_10V6KC1404 0.1U_0402_10V6K
1 2
Q351B
DMN66D0LDW-7_SOT363-6
Q351B
DMN66D0LDW-7_SOT363-6
3
5
4
R854.7K_0402_5% R854.7K_0402_5%
12
R87
4.99K_0402_1%
R87
4.99K_0402_1%
1 2
C419
0.1U_0402_16V4Z
C419
0.1U_0402_16V4Z
1
2
R844.7K_0402_5% @R844.7K_0402_5% @
12
R465 1.5K_0402_5%R465 1.5K_0402_5%
1 2
C768
4.7U_0603_6.3V6K
C768
4.7U_0603_6.3V6K
1
2
R864.7K_0402_5% R864.7K_0402_5%
12
R884.7K_0402_5% @R884.7K_0402_5% @
12
R2155
4.7K_0402_5%
R2155
4.7K_0402_5%
12
C1405 0.1U_0402_10V6KC1405 0.1U_0402_10V6K
1 2
R774.7K_0402_5% @R774.7K_0402_5% @
12
L25EMC@
DLW21HN900HQ2L_4P
L25EMC@
DLW21HN900HQ2L_4P
1
1
4
433
22
C87
2.2U_0402_6.3V6M
C87
2.2U_0402_6.3V6M
1
2
JHDMI1
CONCR_099BAAC19BBLCNF-A1
CONN@
JHDMI1
CONCR_099BAAC19BBLCNF-A1
CONN@
D2+
1D2_shield
2D2-
3D1+
4D1_shield
5D1-
6D0+
7D0_shield
8D0-
9CK+
10 CK_shield
11 CK-
12 CEC
13 Reserved
14 SCL
15 SDA
16 DDC/CEC_GND
17 +5V
18 HP_DET
19
GND 20
GND 21
GND 22
GND 23
R458 0_0402_5%@R458 0_0402_5%@
1 2
R116510K_0402_5% R116510K_0402_5%
1 2
R2156
4.7K_0402_5%
R2156
4.7K_0402_5%
12
R454 0_0402_5%@R454 0_0402_5%@
1 2
L23EMC@
DLW21HN900HQ2L_4P
L23EMC@
DLW21HN900HQ2L_4P
1
1
4
433
22
R455 0_0402_5%@R455 0_0402_5%@
1 2
R456 0_0402_5%@R456 0_0402_5%@
1 2
R2161
4.7K_0402_5%
R2161
4.7K_0402_5%
12
C1342
3.3P_0402_50V8C
@
C1342
3.3P_0402_50V8C
@
1
2
Q351A
DMN66D0LDW-7_SOT363-6
Q351A
DMN66D0LDW-7_SOT363-6
61
2
R784.7K_0402_5% R784.7K_0402_5%
12
C1334
3.3P_0402_50V8C
@
C1334
3.3P_0402_50V8C
@
1
2
U21
PS8339BQFN56GTR2-A0_QFN56_7X7
U21
PS8339BQFN56GTR2-A0_QFN56_7X7
SW/SDA_CTL
45
DP_CFG1 29
IN_D0p
3
IN_D0n
4
IN_D1p
6
IN_D1n
7
VDD33
41
IN_D2p
9
IN_D2n
10
TMDS_HPD 17
IN_D3p
12
IN_D3n
13
VDD33
14
MODE
53
TMDS_CLKn 15
TMDS_SDA 47
TMDS_SCL 48
DP_CA_DET 42
PD
46
IN_CA_DET
11
TMDS_RT 23
CEXT
1
IN_AUXn
51 IN_AUXp
52
PEQ
8
DP_CFG0/SCL_CTL
44
TMDS_CLKp 16
VDD33
56
DP_AUXp_SCL 55
TMDS_DDCBUF
2
TMDS_CH0p 19
TMDS_CH0n 18
TMDS_PRE 20
TMDS_CH1p 22
TMDS_CH1n 21
DP_D0p 40
DP_D0n 39
VDD33
28
DP_D1p 37
DP_D1n 36
DP_AUXn_SDA 54
DP_D2p 34
DP_D2n 33
GND 26
DP_D3p 31
DP_D3n 30
GND 43
IN_DDC_SDA
49 IN_DDC_SCL
50
REXT
27
I2C_CTL_EN
38
GND 35
TMDS_CH2n 24
TMDS_CH2p 25
IN_HPD
5
Thermal/GND 57
DP_HPD 32
R804.7K_0402_5% @R804.7K_0402_5% @
12
C552 0.1U_0402_10V6KC552 0.1U_0402_10V6K
1 2
C46
0.1U_0402_10V7K
C46
0.1U_0402_10V7K
1
2
C1337
3.3P_0402_50V8C
@
C1337
3.3P_0402_50V8C
@
1
2
R4951M_0402_5% R4951M_0402_5%
12
10U_0805_10V6K
C47
10U_0805_10V6K
C47
1
2
R2162
4.7K_0402_5%
R2162
4.7K_0402_5%
12
R894.7K_0402_5% R894.7K_0402_5%
12
R452 0_0402_5%@R452 0_0402_5%@
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
SMBus Device Address 0xC8
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Place C462, C463 and L29 close to U31
Place C1178 close to pin5
Idc min=500mA
DCR=100m ohm
Note: +1.0V_LAN will work at 0.95V to 1.15V
LAN ANALOG SWITCH
TO DOCK
Layout Notice : Place bead as
close PI3L720 as possible
DOCKEDFROM NIC 1: TO DOCK
0: TO RJ45
CIS LINK OK
Difference with Diesel
+3.3V_LAN Source
+3.3V_ALW_PCH Source
Intel request.
Intel request: Remove 10uF
XTALO
LOM_SPD100LED_ORG#
LOM_SPD10LED_GRN#
DOCK_LOM_TRD0-
DOCK_LOM_TRD1+
DOCK_LOM_TRD1-
DOCK_LOM_TRD2-
DOCK_LOM_TRD2+
DOCK_LOM_TRD3-
DOCK_LOM_TRD3+
DOCK_LOM_TRD0+
LOM_SPD10LED_GRN#
LOM_SPD100LED_ORG#
REGCTL_PNP10
CLK_PCIE_LAN
CLK_PCIE_LAN#
PCIE_PRX_GLANTX_P3_C
PCIE_PRX_GLANTX_N3_C
LAN_TX1-
LAN_TX1+
LAN_TX2+
LAN_TX2-
LAN_TX3-
LAN_TX0-
LAN_TX0+
LAN_TX3+
LOM_ACTLED_YEL#
REGCTL_PNP10
LOM_SPD10LED_GRN#
LOM_SPD100LED_ORG#
DOCK_LOM_SPD100LED_ORG#
DOCK_LOM_SPD10LED_GRN#
LED_10_GRN#
LED_100_ORG#
+3.3V_LAN_OUT
DOCK_LOM_ACTLED_YEL#
LAN_ACTLED_YEL#
TP_LAN_JTAG_TMS
TP_LAN_JTAG_TCK
SW_LAN_TX0-
SW_LAN_TX0+
SW_LAN_TX1-
SW_LAN_TX1+
SW_LAN_TX2+
SW_LAN_TX2-
SW_LAN_TX3-
SW_LAN_TX3+
LAN_TX1-R
LAN_TX1+R
LAN_TX1-
LAN_TX1+
LAN_TX2-R
LAN_TX2+RLAN_TX2+
LAN_TX2-
LAN_TX3-R
LAN_TX3+RLAN_TX3+
LAN_TX3-
LAN_TX0-RLAN_TX0-
LAN_TX0+RLAN_TX0+
PCIE_PTX_GLANRX_N3_C
PCIE_PTX_GLANRX_P3_C
LOM_ACTLED_YEL#
TP_LAN_JTAG_TDI
TP_LAN_JTAG_TDO
TP_LAN_JTAG_TMS
TP_LAN_JTAG_TCK
XTALI
LAN_DISABLE#_R
LAN_TEST_EN
RES_BIAS
XTALI
XTALOXTALO_R
LAN_DISABLE#_R
LAN_W AKE#_R
+RSVD_VCC3P3_2
VCT_LAN_R1
LAN_W AKE#_R
SYS_LED_MASK#
SYS_LED_MASK#
SYS_LED_MASK#
LAN_ACTLED_YEL#
LED_100_ORG# LED_10_GRN#
+3.3V_LAN_PWR
+0.9V_LAN
+0.9V_LAN
+0.9V_LAN
+3.3V_LAN
+3.3V_LAN
+3.3V_LAN
+3.3V_LAN
+3.3V_LAN
+3.3V_LAN
+3.3V_LAN
+3.3V_LAN
+3.3V_LAN_PWR
+3.3V_ALW_PCH+3.3V_ALW_PCH_PWR
+3.3V_LAN
+3.3V_ALW
+5V_ALW
+3.3V_ALW
DOCK_LOM_TRD0- <48>
DOCK_LOM_TRD1+ <48>
DOCK_LOM_TRD1- <48>
DOCK_LOM_TRD2- <48>
DOCK_LOM_TRD2+ <48>
DOCK_LOM_TRD3- <48>
DOCK_LOM_TRD3+ <48>
DOCK_LOM_TRD0+ <48>
SW_LAN_TX0- <40>
SW_LAN_TX0+ <40>
SW_LAN_TX1- <40>
SW_LAN_TX1+ <40>
SW_LAN_TX2+ <40>
SW_LAN_TX2- <40>
SW_LAN_TX3- <40>
SW_LAN_TX3+ <40>
LANCLK_REQ#<18,20>
PLTRST_LAN#<19>
CLK_PCIE_LAN#<20>
CLK_PCIE_LAN<20>
PCIE_PRX_GLANTX_P3<22>
PCIE_PRX_GLANTX_N3<22>
DOCKED<38,50>
DOCK_LOM_ACTLED_YEL# <48>
DOCK_LOM_SPD100LED_ORG# <48>
DOCK_LOM_SPD10LED_GRN# <48>
LAN_SMBDATA<21>
LAN_SMBCLK<21>
PCIE_PTX_GLANRX_N3<22>
PCIE_PTX_GLANRX_P3<22>
WLAN_LAN_DISBL# <50>
LAN_DISABLE#_R<50>
PM_LANPHY_ENABLE<23>
LAN_W AKE#<23,51>
SYS_LED_MASK# <50,52>
LAN_ACTLED_YEL#_Q <40>
LED_100_ORG#_Q <40> LED_10_GRN#_Q <40>
PCH_ALW _ON<51>
SIO_SLP_LAN#<19,51>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
LAN/LAN SW
39 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
LAN/LAN SW
39 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
LAN/LAN SW
39 67Monday, January 13, 2014
Compal Electronics, Inc.
L67 12NH_0603CS-120EJTS_5%L67 12NH_0603CS-120EJTS_5%
1 2
R554 4.7K_0402_5%R554 4.7K_0402_5%
12
R549
10K_0402_5%
@
R549
10K_0402_5%
@
12
C547
470P_0402_50V7K
C547
470P_0402_50V7K
1
2
C474
0.1U_0402_25V6K
C474
0.1U_0402_25V6K
1
2
T143 PAD~D@T143 PAD~D@
C460 0.1U_0402_10V7KC460 0.1U_0402_10V7K
1 2
C467
0.1U_0402_10V7K
C467
0.1U_0402_10V7K
1
2
R562
3.01K_0402_1%
R562
3.01K_0402_1%
12
L68 12NH_0603CS-120EJTS_5%L68 12NH_0603CS-120EJTS_5%
1 2
L63 12NH_0603CS-120EJTS_5%L63 12NH_0603CS-120EJTS_5%
1 2
R561
1K_0402_1%
R561
1K_0402_1%
12
C1177
22U_0805_6.3V6M
C1177
22U_0805_6.3V6M
1
2
C469
0.1U_0402_10V7K
C469
0.1U_0402_10V7K
1
2
C462
10U_0603_6.3V6M
C462
10U_0603_6.3V6M
1
2
C478
0.1U_0402_10V7K
@C478
0.1U_0402_10V7K
@
1 2
R546 10K_0402_5%@R546 10K_0402_5%@
1 2
C466
0.1U_0402_10V7K
C466
0.1U_0402_10V7K
1
2
L69 12NH_0603CS-120EJTS_5%L69 12NH_0603CS-120EJTS_5%
1 2
C459 0.1U_0402_10V7KC459 0.1U_0402_10V7K
12
L64 12NH_0603CS-120EJTS_5%L64 12NH_0603CS-120EJTS_5%
1 2
PJP93
JUMP_43X79
@PJP93
JUMP_43X79
@
11
2
2
U63
TPS22966DPUR_SON14_2X3~D
U63
TPS22966DPUR_SON14_2X3~D
GND 11
VIN2
6
VBIAS
4
ON2
5
VOUT2 9
VIN2
7
CT1 12
VOUT1 14
VOUT2 8
VOUT1 13
VIN1
2
ON1
3
VIN1
1
CT2 10
GPAD 15
U15
TC7SH08FU_SSOP5~D
U15
TC7SH08FU_SSOP5~D
B
1
A
2
G
3
O4
P5
R209@0_0603_1%R209@0_0603_1%
1 2
C473
0.1U_0402_25V6K
C473
0.1U_0402_25V6K
1
2
C1418
0.1U_0402_10V7K
C1418
0.1U_0402_10V7K
1
2
PCIE
MDI
SMBUS
JTAG LED
U31
WGI218LM-QQ89-B0_QFN48_6X6~D
PCIE
MDI
SMBUS
JTAG LED
U31
WGI218LM-QQ89-B0_QFN48_6X6~D
RSVD_VCC3P3_1 1
LANWAKE_N
2
LAN_DISABLE_N
3
VDD3P3_4 4
VDD3P3_IN 5
SVR_EN_N 6
CTRL0P9 7
VDD0P9_8 8
XTAL_OUT
9
XTAL_IN
10
VDD0P9_11 11
RBIAS
12
MDI_PLUS0 13
MDI_MINUS0 14
VDD3P3_15 15
VDD0P9_16 16
MDI_PLUS1 17
MDI_MINUS1 18
VDD3P3_19 19
MDI_PLUS2 20
MDI_MINUS2 21
VDD0P9_22 22
MDI_PLUS3 23
MDI_MINUS3 24
LED2
25
LED0
26
LED1
27
SMB_CLK
28
VDD3P3_29 29
TEST_EN
30
SMB_DATA
31
JTAG_TDI
32
JTAG_TMS
33 JTAG_TDO
34
JTAG_TCK
35
PE_RST_N
36
VDD0P9_37 37
PETp
38
PETn
39
VDD0P9_40 40
PERp
41
PERn
42
VDD0P9_43 43
PE_CLKP
44
PE_CLKN
45
VDD0P9_46 46
VDD0P9_47 47
CLK_REQ_N
48
VSS_EPAD 49
PJP95
JUMP_43X79
@PJP95
JUMP_43X79
@
11
2
2
T142 PAD~D@T142 PAD~D@
R557
10K_0402_5%
@R557
10K_0402_5%
@
12
C421
10U_0603_6.3V6M
C421
10U_0603_6.3V6M
1
2
L29
4.7UH_BRC2012T4R7MD_20%
L29
4.7UH_BRC2012T4R7MD_20%
1 2
L70 12NH_0603CS-120EJTS_5%L70 12NH_0603CS-120EJTS_5%
1 2
L65 12NH_0603CS-120EJTS_5%L65 12NH_0603CS-120EJTS_5%
1 2
C470
22P_0402_50V8J
C470
22P_0402_50V8J
1
2
Y3
25MHZ_18PF_X3G025000DI1H-H
Y3
25MHZ_18PF_X3G025000DI1H-H
IN 1
GND 2
OUT
3
GND
4
C1178
22U_0805_6.3V6M
C1178
22U_0805_6.3V6M
1
2
C471
27P_0402_50V8J
C471
27P_0402_50V8J
1
2
R558 0_0402_5%@R558 0_0402_5%@
1 2
G
D
S
Q327
L2N7002WT1G_SC-70-3
G
D
S
Q327
L2N7002WT1G_SC-70-3
2
13
Q325A
DMN66D0LDW -7_SOT363-6
Q325A
DMN66D0LDW -7_SOT363-6
61
2
R545 10K_0402_5%@R545 10K_0402_5%@
1 2
C458 0.1U_0402_10V7KC458 0.1U_0402_10V7K
12
C463
0.1U_0402_10V7K
C463
0.1U_0402_10V7K
1
2
L66 12NH_0603CS-120EJTS_5%L66 12NH_0603CS-120EJTS_5%
1 2
C464
1U_0603_10V7K
C464
1U_0603_10V7K
1
2
C472
0.1U_0402_25V6K
C472
0.1U_0402_25V6K
1
2
C422
470P_0402_50V7K
C422
470P_0402_50V7K
1
2
R555 0_0402_5%@R555 0_0402_5%@
1 2
R553 4.7K_0402_5%@R553 4.7K_0402_5%@
12
C468
0.1U_0402_10V7K
C468
0.1U_0402_10V7K
1
2
U32
PI3L720ZHEX_TQFN42_9X3P5~D
U32
PI3L720ZHEX_TQFN42_9X3P5~D
SEL
13
A0+
2
A0-
3
A1+
6
A1-
7
A2+
9
A2-
10
A3+
11
B0+ 38
C0+ 36
B0- 37
C0- 35
B1+ 34
C1+ 32
B1- 33
C1- 31
B2+ 29
C2+ 27
B2- 28
C2- 26
B3+ 25
C3+ 23
B3- 24
C3- 22
A3-
12
LEDA0
15
LEDA1
16
LEDA2
42
LEDB0 17
LEDC0 19
LEDB1 18
LEDC1 20
LEDB2 41
LEDC2 40
PAD_GND
43
VDD 1
VDD 4
VDD 8
VDD 14
VDD 21
VDD 30
VDD 39
PD
5
R1144 0_0402_5%@R1144 0_0402_5%@
1 2
Q325B
DMN66D0LDW -7_SOT363-6
Q325B
DMN66D0LDW -7_SOT363-6
3
5
4
R556 0_0402_5%@R556 0_0402_5%@
1 2
C461 0.1U_0402_10V7KC461 0.1U_0402_10V7K
1 2
R559 4.7K_0402_5%@R559 4.7K_0402_5%@
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
+3.3V_LAN/+3.3V_LAN_LOM:20mils
GND CHASSIS
Close to JLOM1
LInk CIS
For IEEE EA request
Placement close to T156
change TAIMAG to be main source
SW_LAN_TX2-
SW_LAN_TX3-
SW_LAN_TX0-
SW_LAN_TX0+
+TRM_CT3
+TRM_CT4
SW_LAN_TX1-
SW_LAN_TX1+
+TRM_CT1
+TRM_CT2
SW_LAN_TX2+
SW_LAN_TX3+
NB_LAN_TX1-
NB_LAN_TX1+
NB_LAN_TX0-
NB_LAN_TX0+
Z2807
Z2808
Z2806
Z2805
GND_CHASSIS
NB_LAN_TX3-
NB_LAN_TX3+
NB_LAN_TX2-
NB_LAN_TX2+
NB_LAN_TX3-
NB_LAN_TX3+
NB_LAN_TX1-_R
NB_LAN_TX2-
NB_LAN_TX2+
NB_LAN_TX1+_R
NB_LAN_TX0-_R
NB_LAN_TX0+_R
NB_LAN_TX0+ NB_LAN_TX0+_R
NB_LAN_TX0-
NB_LAN_TX1+
NB_LAN_TX1-
NB_LAN_TX0-_R
NB_LAN_TX1+_R
NB_LAN_TX1-_R
+3.3V_LAN
+3.3V_LAN
SW_LAN_TX0+<39>
SW_LAN_TX0-<39>
SW_LAN_TX1+<39>
SW_LAN_TX1-<39>
SW_LAN_TX2+<39>
SW_LAN_TX2-<39>
SW_LAN_TX3+<39>
SW_LAN_TX3-<39>
LED_100_ORG#_Q<39>
LED_10_GRN#_Q<39>
LAN_ACTLED_YEL#_Q<39>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
RJ45
40 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
RJ45
40 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
RJ45
40 67Monday, January 13, 2014
Compal Electronics, Inc.
R1167 150_0402_5%R1167 150_0402_5%
1 2
JLOM1
SANTA_130454-H
CONN@
JLOM1
SANTA_130454-H
CONN@
PR1-
2
PR1+
1
PR2+
3
PR3+
4
PR3-
5
PR2-
6
PR4+
7
PR4-
8
LED+
9
Green_LED-
10
Yellow_LED+
12
Yellow_LED-
13
SHLD1 14
SHLD2 15
ORANGE_LED-
11
C479
0.47U_0603_10V7K
C479
0.47U_0603_10V7K
1
2
R572 75_0402_1%R572 75_0402_1%
12
R1171 150_0402_5%R1171 150_0402_5%
1 2
C480
0.47U_0603_10V7K
C480
0.47U_0603_10V7K
1
2
R571 75_0402_1%R571 75_0402_1%
12
1:1
1:1
1:1
1:1
T156
350uH_IH-115-F
1:1
1:1
1:1
1:1
T156
350uH_IH-115-F
TD1-
2
TDCT1
3
TDCT2
4
TD2+
5
TD2-
6
TD3+
7
TD3-
8
TDCT3
9
TDCT4
10
TD4+
11
TD4-
12 TX4- 13
TXCT3 16
TX3+ 18
TX2- 19
TX2+ 20
TXCT2 21
TXCT1 22
TX1- 23
TX4+ 14
TXCT4 15
TX3- 17
TD1+
1TX1+ 24
C484
0.47U_0603_10V7K
C484
0.47U_0603_10V7K
1
2
R573 75_0402_1%R573 75_0402_1%
12
R1170 150_0402_5%R1170 150_0402_5%
1 2
C485 150P_1808_3KV8J
EMC@ C485 150P_1808_3KV8J
EMC@
1 2
C481
1U_0603_10V6K
C481
1U_0603_10V6K
1
2
R575 0_0402_5%@R575 0_0402_5%@
1 2
C486
0.47U_0603_10V7K
C486
0.47U_0603_10V7K
1
2
R574 75_0402_1%R574 75_0402_1%
12
R576 0_0402_5%@R576 0_0402_5%@
1 2
C483
0.1U_0402_10V7K
C483
0.1U_0402_10V7K
1
2
R577 0_0402_5%@R577 0_0402_5%@
1 2
C1167
470P_0402_50V7K
C1167
470P_0402_50V7K
1
2
R578 0_0402_5%@R578 0_0402_5%@
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
Close to JUSH1
Intel Management Engine Test Suite
Check ME about wire to board PN
ESD request
Difference with Diesel
Difference with Diesel
CIS link OK
15: SIO_SLP_S0# for MCP only
USH_PWR_STATE#
USH_SMBCLK
USH_SMBDAT
SPI_DINTPM
SPI_DOTPM
SPI_CLKTPM
PCH_SPI_CS2#_R
SPI_CLKTPM
PLTRST_USH#
+3.3V_RUN
+3.3V_SUS
+3.3V_SUS
+3.3V_SUS+3.3V_RUN+5V_RUN
+5V_RUN
+PCH_VCCDSW3_3
+3.3V_ALW_PCH
+3.3V_M
+3.3V_M_TPM
+3.3V_M_TPM
+PCH_VCCDSW3_3
BCM5882_ALERT#<50>
USBP7-<22>
USBP7+<22>
USH_SMBDAT<51>
PLTRST_USH#<19>
USH_PWR_STATE#<50>
CONTACTLESS_DET#<23>
USH_SMBCLK<51>
PCH_PLTRST#_EC<19,42,43,50,51>
PCH_SPI_DIN<21>
PCH_SPI_DO<21>
PCH_SPI_CLK<21>
PCH_SPI_CS2#<21>
USH_DET#<23>
SIO_SLP_S3#<19,32,51,54>
SIO_SLP_S4#<19,51,54,57>
SIO_SLP_A#<19,51,54,58>
SYS_RESET#<19>
POWER_SW#_MB<49,51>
PCH_RTCRST#<18>
SIO_SLP_S5#<19,32,51>
TPM_PIRQ#<23>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
TPM/USH
41 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
TPM/USH
41 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
TPM/USH
41 67Monday, January 13, 2014
Compal Electronics, Inc.
RZ9 2.2K_0402_5%RZ9 2.2K_0402_5%
1 2
CZ7
2200P_0402_50V7K
CZ7
2200P_0402_50V7K
12
JAPS1
CONN@
ACES_50506-01841-P01
JAPS1
CONN@
ACES_50506-01841-P01
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
GND
19
GND
20
JUSH1
ACES_50559-02001-001
CONN@
JUSH1
ACES_50559-02001-001
CONN@
1
1
2 2
2
3
3
4 4
4
5
5
6 6
6
7
7
8 8
8
9
9
10 10
10
11
11
12 12
12
13
13
14 14
14
15
15
16 16
16
17
17
18 18
18
G1 21
G2 22
G3 23
G4 24
19
19
20 20
20
RZ10 1M_0402_5%RZ10 1M_0402_5%
1 2
RZ29 33_0402_5%RZ29 33_0402_5%
1 2
CZ4@
0.1U_0402_25V6
CZ4@
0.1U_0402_25V6
12
RZ30 33_0402_5%RZ30 33_0402_5%
1 2
CZ57
0.047U_0402_16V4Z
CZ57
0.047U_0402_16V4Z
1
2
PJP11
PJP@
PAD-OPEN1x1m
PJP11
PJP@
PAD-OPEN1x1m
1 2
CZ6
2200P_0402_50V7K
CZ6
2200P_0402_50V7K
12
CZ11
@
0.1U_0402_25V6
CZ11
@
0.1U_0402_25V6
12
CZ9
@EMC@
0.1U_0402_25V6
CZ9
@EMC@
0.1U_0402_25V6
12
RZ26 33_0402_5%RZ26 33_0402_5%
1 2
RZ17 0_0402_5%RZ17 0_0402_5%
1 2
CZ5
4700P_0402_25V7K
CZ5
4700P_0402_25V7K
12
RZ35
33_0402_5%
@EMC@
RZ35
33_0402_5%
@EMC@
1 2
RZ8 2.2K_0402_5%RZ8 2.2K_0402_5%
1 2
CZ10
@
0.1U_0402_25V6
CZ10
@
0.1U_0402_25V6
12
UZ1
AT97SC3205_TSSOP28~D
UZ1
AT97SC3205_TSSOP28~D
GPIO_3 17
PIRQ#
20
MOSI
23 MISO
26
SPI_CLK
21
SPI_CS#
22
SPI_RST#
16
NBO_5 27
NBO_4 15
PP/GPIO 7
GPIO_1 1
GPIO_2 2
GPIO-Express-00 6
TESTI 8
TESTBI 9
VCC
10
VCC
19
VCC
24
GND
4GND
11 GND
18 GND
25
VCC
3
NBO_1 5
V_BAT 12
NBO_2 13
NBO_3 14
NBO_6 28
CZ12
@
0.1U_0402_25V6
CZ12
@
0.1U_0402_25V6
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
WWAN/LTE/HCA/Cache
C615 footprint change to C_APXK2R5ARA331MF451
SIM Card Push-Push
0
CONFIG_0
NGFF slot_2 Key B
1
1
CONFIG_2
0
0
1
Module Type
SSD-SATA
WWAN
HCA-PCIE
WLAN/BT/WiGig
NGFF slot_1 Key A
For RF Team request
CIS link OK
C613 change to 0603
due to height limitation.
CIS link OK
CIS link OK
STATE #
0
8
14
CONFIG_1
0
0
0
CONFIG_3
0
0
1
1 NA15 1 11
WWAN_LED# WIRELESS_LED#
PCIE_PTX_SATARX_N4_C
PCIE_PTX_SATARX_P4_C
WWAN_LED#
WWAN_RADIO_DIS#_R
HW_GPS_DISABLE#_R
PCH_PLTRST#_EC
UIM_RESET
UIM_CLK
UIM_DATA
WWAN_RADIO_DIS#_R
HW_GPS_DISABLE#_R
BT_RADIO_DIS#_R
WLAN_WIGIG60GHZ_DIS#_R
BT_LED#
WLAN_LED#
WIGIG_LANE_P2_C
PCIE_WAKE#
WLAN_WIGIG60GHZ_DIS#_R
BT_RADIO_DIS#_R
PCH_PLTRST#_EC
BT_LED#
WLAN_LED#
WIGIG_LANE_N3_C
WIGIG_LANE_P3_C
WIGIG_LANE_N2_C
WIGIG_AUX#_C
WIGIG_AUX_C
WIGIG_LANE_N1_C
WIGIG_LANE_P1_C
WIGIG_LANE_N0_C
WIGIG_LANE_P0_C
PCIE_PTX_WIGIGRX_N8_C
PCIE_PTX_WIGIGRX_P8_C
PCIE_WAKE#
PCH_PLTRST#_EC
PCIE_PTX_WLANRX_P7_C
PCIE_PTX_WLANRX_N7_C
WWAN_PWR_EN
PCIE_WAKE#
UIM_RESET
UIM_CLK
UIM_DATA
UIM_DATA
UIM_RESET
UIM_CLK
WWAN_PWR_EN
+3.3V_WWAN
+3.3V_WWAN
+3.3V_WWAN
+3.3V_WWAN
+SIM_PWR
+3.3V_WLAN
+3.3V_WLAN
+3.3V_WLAN
+SIM_PWR
NGFF_CONFIG_3<50>
NGFF_CONFIG_0<50>
NGFF_CONFIG_1<50>
NGFF_CONFIG_2<50>
PCIE_PRX_SATATX_P4<18>
PCIE_PRX_SATATX_N4<18>
PCIE_PTX_SATARX_P4<18>
PCIE_PTX_SATARX_N4<18>
USBP5+<22>
USBP5-<22>
SUSCLK <19,42,43>
WWAN_RADIO_DIS# <50>
HW_GPS_DISABLE# <50>
BT_RADIO_DIS# <50>
WLAN_WIGIG60GHZ_DIS# <50>
WIGIG_LANE_N2<37>
WIGIG_LANE_P3<37>
WIGIG_LANE_N3<37>
WIGIG_LANE_P2<37>
WIGIG_AUX# <37>
WIGIG_LANE_N0 <37>
WIGIG_LANE_P1 <37>
WIGIG_LANE_N1 <37>
WIGIG_AUX <37>
WIGIG_LANE_P0 <37>
PCH_CL_RST1# <21>
PCH_CL_DATA1 <21>
PCH_CL_CLK1 <21>
SUSCLK <19,42,43>
PCIE_WAKE#<17,32,50>
PCH_PLTRST#_EC <19,41,43,50,51>
PCIE_PTX_WIGIGRX_P8<22>
PCIE_PRX_WIGIGTX_N8<22>
PCIE_PTX_WIGIGRX_N8<22>
PCIE_PRX_WIGIGTX_P8<22>
CLK_PCIE_WIGIG<20>
CLK_PCIE_WIGIG#<20>
WIGIGCLK_REQ# <20>
WIGIG_HPD<37>
USBP4-<22>
USBP4+<22>
PCIE_PTX_WLANRX_P7<22>
PCIE_PTX_WLANRX_N7<22>
PCIE_PRX_WLANTX_P7<22>
PCIE_PRX_WLANTX_N7<22>
WLANCLK_REQ#<20>
CLK_PCIE_WLAN<20>
CLK_PCIE_WLAN#<20>
WIRELESS_LED# <50,52>
CLK_PCIE_NGFF2#<20>
CLK_PCIE_NGFF2<20>
NGFF2_CLK_REQ# <20>
WWAN_WAKE#<50>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
M.2 Card-1/2
42 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
M.2 Card-1/2
42 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
M.2 Card-1/2
42 67Monday, January 13, 2014
Compal Electronics, Inc.
C612
33P_0402_50V8J
EMC@ C612
33P_0402_50V8J
EMC@
1
2
CV1 0.1U_0402_25V6CV1 0.1U_0402_25V6
1 2
Q124B
DMN66D0LDW-7_SOT363-6
Q124B
DMN66D0LDW-7_SOT363-6
3
5
4
CV100.1U_0402_25V6 CV100.1U_0402_25V6
12
D31RB751S40T1G_SOD523-2 D31RB751S40T1G_SOD523-2
12
CV7 0.1U_0402_25V6CV7 0.1U_0402_25V6
1 2
C605
0.047U_0402_16V4Z
C605
0.047U_0402_16V4Z
1
2
C604
0.047U_0402_16V4Z
C604
0.047U_0402_16V4Z
1
2
CV90.1U_0402_25V6 CV90.1U_0402_25V6
12
RZ3 0_0402_5%RZ3 0_0402_5%
1 2
C611
0.047U_0402_16V4Z
EMC@ C611
0.047U_0402_16V4Z
EMC@
1
2
D36RB751S40T1G_SOD523-2 D36RB751S40T1G_SOD523-2
12
CV2 0.1U_0402_25V6CV2 0.1U_0402_25V6
1 2
C607
0.1U_0402_25V6K
C607
0.1U_0402_25V6K
1
2
+
C1176
330U_D2E_6.3VM_R25
@
+
C1176
330U_D2E_6.3VM_R25
@
1
2
C1356
1U_0402_6.3V6K
C1356
1U_0402_6.3V6K
12
JNGFF2
CONN@
FOX_AS0BC21-S48BB-7H
JNGFF2
CONN@
FOX_AS0BC21-S48BB-7H
1
122
3
344
5
566
7
788
9
910 10
11
11
12 12
13
13 14 14
15
15 16 16
17
17 18 18
19
19 20 20
53
53 54 54
55
55 56 56
57
57 58 58
59
59 60 60
61
61 62 62
63
63 64 64
65
65 66 66
67
67
21
21 22 22
23
23 24 24
25
25 26 26
27
27 28 28
29
29 30 30
31
31 32 32
33
33 34 34
35
35 36 36
37
37 38 38
39
39 40 40
41
41 42 42
43
43 44 44
45
45 46 46
47
47 48 48
49
49 50 50
51
51 52 52
GND 68
GND
69
R705
100K_0402_5%
R705
100K_0402_5%
1 2
DZ2
RB751S40T1G_SOD523-2
DZ2
RB751S40T1G_SOD523-2
12
CV5 0.1U_0402_25V6CV5 0.1U_0402_25V6
1 2
R718
100K_0402_5%
R718
100K_0402_5%
1 2
CZ1 0.1U_0402_10V7KCZ1 0.1U_0402_10V7K
1 2
CZ59 0.1U_0402_10V7KCZ59 0.1U_0402_10V7K
1 2
JSIM1
T-SOL_159-1000302602
CONN@
JSIM1
T-SOL_159-1000302602
CONN@
DETECT 1
NC
2
NC 3
I/O
4
CLK 5
VPP
6
RST 7
GND
8
VCC 9
NC
10
GND 11
GND
12
GND 13
GND
14
GND 15
GND
16
GND 17
GND
18
CZ3 0.1U_0402_10V7KCZ3 0.1U_0402_10V7K
1 2
CZ2 0.1U_0402_10V7KCZ2 0.1U_0402_10V7K
1 2
+
C615
330U_D2E_6.3VM_R25~D
EMC@
+
C615
330U_D2E_6.3VM_R25~D
EMC@
1
2
CZ65
33P_0402_50V8J
@EMC@
CZ65
33P_0402_50V8J
@EMC@
12
C614
33P_0402_50V8J
EMC@ C614
33P_0402_50V8J
EMC@
1
2
CZ60 0.1U_0402_10V7KCZ60 0.1U_0402_10V7K
1 2
C606
0.1U_0402_25V6K
C606
0.1U_0402_25V6K
1
2
JNGFF1
CONN@
FOX_AS0BC21-S48BA-7H
JNGFF1
CONN@
FOX_AS0BC21-S48BA-7H
1
122
3
344
5
566
7
7
88
9
910 10
11
11 12 12
13
13 14 14
15
15 16 16
17
17 18 18
19
19 20 20
53
53 54 54
55
55 56 56
57
57 58 58
59
59 60 60
61
61 62 62
63
63 64 64
65
65 66 66
67
67
21
21 22 22
23
23 24 24
25
25 26 26
27
27 28 28
29
29 30 30
31
31 32 32
33
33 34 34
35
35 36 36
37
37 38 38
39
39 40 40
41
41 42 42
43
43 44 44
45
45 46 46
47
47 48 48
49
49 50 50
51
51 52 52
GND 68
GND
69
CZ66
33P_0402_50V8J
@EMC@
CZ66
33P_0402_50V8J
@EMC@
12
C610
0.047U_0402_16V4Z
EMC@ C610
0.047U_0402_16V4Z
EMC@
1
2
CZ58 0.1U_0402_10V7KCZ58 0.1U_0402_10V7K
1 2
CV40.1U_0402_25V6 CV40.1U_0402_25V6
12
CZ67
33P_0402_50V8J
@EMC@
CZ67
33P_0402_50V8J
@EMC@
12
G
D
S
Q77
DMN65D8LW-7_SOT323-3
G
D
S
Q77
DMN65D8LW-7_SOT323-3
2
13
CV30.1U_0402_25V6 CV30.1U_0402_25V6
12
Q124A
DMN66D0LDW-7_SOT363-6
Q124A
DMN66D0LDW-7_SOT363-6
61
2
C613
22U_0603_6.3V6M
EMC@ C613
22U_0603_6.3V6M
EMC@
12
+
C1402
330U_D2E_6.3VM_R25
+
C1402
330U_D2E_6.3VM_R25
1
2
CV80.1U_0402_25V6 CV80.1U_0402_25V6
12
R719
100K_0402_5%
R719
100K_0402_5%
1 2
CV60.1U_0402_25V6 CV60.1U_0402_25V6
12
C603
0.1U_0402_25V6K
@C603
0.1U_0402_25V6K
@
1
2
DZ1
RB751S40T1G_SOD523-2
DZ1
RB751S40T1G_SOD523-2
12
C608
4.7U_0603_6.3V6K
C608
4.7U_0603_6.3V6K
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
NGFF slot_3 Key B
SSD/HCA/Cache
STATE #
0 0
CONFIG_0 Module Type
SSD-SATA
HCA-PCIE14 1
CIS link OK
PCIE_PTX_SATARX_N5_C
PCIE_PTX_SATARX_P5_C
+3.3V_SSD
+3.3V_SSD
PCIE_PRX_SATATX_P5<18>
PCIE_PRX_SATATX_N5<18>
PCIE_PTX_SATARX_P5<18>
PCIE_PTX_SATARX_N5<18>
USBP10+<22>
USBP10-<22>
SUSCLK <19,42>
CLK_PCIE_NGFF3#<20>
CLK_PCIE_NGFF3<20>
NGFF3_CLK_REQ# <20>
PCH_PLTRST#_EC <19,41,42,50,51>
SLOT3_CONFIG_0<50>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
M.2 Card-2/2
43 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
M.2 Card-2/2
43 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
M.2 Card-2/2
43 67Monday, January 13, 2014
Compal Electronics, Inc.
C622
22U_0805_6.3VAM
C622
22U_0805_6.3VAM
1
2
JNGFF3
CONN@
FOX_AS0BC21-S48BB-7H
JNGFF3
CONN@
FOX_AS0BC21-S48BB-7H
1
122
3
344
5
566
7
788
9
910 10
11
11
12 12
13
13 14 14
15
15 16 16
17
17 18 18
19
19 20 20
53
53 54 54
55
55 56 56
57
57 58 58
59
59 60 60
61
61 62 62
63
63 64 64
65
65 66 66
67
67
21
21 22 22
23
23 24 24
25
25 26 26
27
27 28 28
29
29 30 30
31
31 32 32
33
33 34 34
35
35 36 36
37
37 38 38
39
39 40 40
41
41 42 42
43
43 44 44
45
45 46 46
47
47 48 48
49
49 50 50
51
51 52 52
GND 68
GND
69
C618
33P_0402_50V8J
C618
33P_0402_50V8J
1
2
C623
0.047U_0402_16V4Z
C623
0.047U_0402_16V4Z
1
2
+
C619
330U_V_6.3VM
@
+
C619
330U_V_6.3VM
@
1
2
C621
0.047U_0402_16V4Z
C621
0.047U_0402_16V4Z
1
2
CZ61 0.1U_0402_10V7KCZ61 0.1U_0402_10V7K
1 2
C617
33P_0402_50V8J
C617
33P_0402_50V8J
1
2
CZ13 0.1U_0402_10V7KCZ13 0.1U_0402_10V7K
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Power Control for M.2 slot 2.
Difference with Diesel
Power Control for M.2 slot 1.
& +3.3V_RUN Source
Power Control for M.2 slot 3.
& +5V_MXM Source
+3.3V_RUN_PWR
+3.3V_WLAN_PWR
AUX_EN_WOWL_R
NVRAM_PWR_EN
+3.3V_SSD_PWR
+5V_MXM_PWR
+3.3V_ALW +3.3V_WWAN
+5V_ALW
+5V_ALW +3.3V_RUN_PWR +3.3V_RUN
+3.3V_ALW
+3.3V_WLAN_PWR +3.3V_WLAN
+3.3V_ALW
+5V_ALW
+5V_ALW
+3.3V_ALW
+3.3V_SSD_PWR +3.3V_SSD
+5V_MXM+5V_MXM_PWR
3.3V_WWAN_EN<50>AUX_EN_WOWL<50>
SIO_SLP_WLAN#<19,50>
RUN_ON<51,54>
3.3V_RUN_GFX_ON<20,50,54>
NVRAM_PWR_EN<50>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
M.2 Card PWR
44 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
M.2 Card PWR
44 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
M.2 Card PWR
44 67Monday, January 13, 2014
Compal Electronics, Inc.
RZ510_0402_5% RZ510_0402_5%
1 2
C762
10U_0603_6.3V6M
C762
10U_0603_6.3V6M
1
2
CZ87
100P_0402_50V8J
@CZ87
100P_0402_50V8J
@
1
2
C450
10U_0603_6.3V6M
C450
10U_0603_6.3V6M
1
2
R720
100K_0402_5%
R720
100K_0402_5%
12
C538
470P_0402_50V7K
C538
470P_0402_50V7K
1
2
R820 0_0402_5%@R820 0_0402_5%@
1 2
C437
470P_0402_50V7K
C437
470P_0402_50V7K
1
2
R723
100K_0402_5%
R723
100K_0402_5%
12
R739
100K_0402_5%
@
R739
100K_0402_5%
@
12
PJP98
JUMP_43X79
@PJP98
JUMP_43X79
@
11
2
2
C357
10U_0603_6.3V6M
C357
10U_0603_6.3V6M
1
2
PJP99
JUMP_43X79
@PJP99
JUMP_43X79
@
11
2
2
C542
470P_0402_50V7K
C542
470P_0402_50V7K
1
2
U43
TPS22965DSGR_SON8_2X2~D
U43
TPS22965DSGR_SON8_2X2~D
VIN
1
VIN
2
ON
3
VBIAS
4
VOUT 7
VOUT 8
CT
6GND 5
GND 9
C436
3300P_0402_50V7-K
C436
3300P_0402_50V7-K
1
2
PJP97
JUMP_43X79
@PJP97
JUMP_43X79
@
11
2
2
U49
TPS22966DPUR_SON14_2X3~D
U49
TPS22966DPUR_SON14_2X3~D
GND 11
VIN2
6
VBIAS
4
ON2
5
VOUT2 9
VIN2
7
CT1 12
VOUT1 14
VOUT2 8
VOUT1 13
VIN1
2
ON1
3
VIN1
1
CT2 10
GPAD 15
C536
10U_0603_6.3V6M
C536
10U_0603_6.3V6M
1
2
PJP91
JUMP_43X79
@PJP91
JUMP_43X79
@
11
2
2
U42
TPS22966DPUR_SON14_2X3~D
U42
TPS22966DPUR_SON14_2X3~D
GND 11
VIN2
6
VBIAS
4
ON2
5
VOUT2 9
VIN2
7
CT1 12
VOUT1 14
VOUT2 8
VOUT1 13
VIN1
2
ON1
3
VIN1
1
CT2 10
GPAD 15
C541
470P_0402_50V7K
C541
470P_0402_50V7K
1
2
R840 0_0402_5%@R840 0_0402_5%@
1 2
C764
10U_0603_6.3V6M
C764
10U_0603_6.3V6M
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Free Fall Sensor
Main SATA +5V Default
HDD1 CONN HDD2 CONN
Pleace near HDD1 CONN Pleace near HDD1 CONN
Pleace near HDD2 CONN Pleace near HDD2 CONN
Main SATA +5V Default
LInk CIS
LInk CIS
SHORT DEFAULT
HDD PWR
CIS LINK OK
C5 change to 0603
due to height limitation.
C498 change to 0603
due to height limitation.
DDR_XDP_WAN_SMBDAT
DDR_XDP_WAN_SMBCLK
FFS_INT2_Q
HDD_FALL_INT
HDD_FALL_INT
FFS_INT2
FFS_INT2_Q
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
SATA_PTX_DRX_P0
SATA_PTX_DRX_N0
HDD1_DET#
FFS_INT2_Q
SATA_PRX_DTX_N3
SATA_PRX_DTX_P3
SATA_PTX_DRX_P3
SATA_PTX_DRX_N3
HDD2_DET#
FFS_INT2
+5V_HDD
+5V_HDD
+5V_HDD
+3.3V_RUN +3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+5V_HDD
+5V_HDD
+3.3V_RUN
+5V_HDD +5V_RUN
+3.3V_RUN
+3.3V_RUN
FFS_INT2<23>
HDD1_DET#<18>
HDD_FALL_INT<19>
DDR_XDP_WAN_SMBCLK<13,14,15,16,18,21>
DDR_XDP_WAN_SMBDAT<13,14,15,16,18,21>
HDD2_DET#<18,23>
SATA_PTX_DRX_P3_C<18>
SATA_PTX_DRX_N3_C<18>
SATA_PRX_DTX_P3_C<18>
SATA_PRX_DTX_N3_C<18>
SATA_PTX_DRX_P0_C<18>
SATA_PTX_DRX_N0_C<18>
SATA_PRX_DTX_P0_C<18>
SATA_PRX_DTX_N0_C<18>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
HDD CONN
45 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
HDD CONN
45 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
HDD CONN
45 67Monday, January 13, 2014
Compal Electronics, Inc.
C392
10U_0603_6.3V6M
C392
10U_0603_6.3V6M
1
2
PJP3
JUMP_43X79
PJP@
PJP3
JUMP_43X79
PJP@
1
122
C412 0.01U_0402_16V7KC412 0.01U_0402_16V7K
12
C413 0.01U_0402_16V7KC413 0.01U_0402_16V7K
12
R513
100K_0402_5%
R513
100K_0402_5%
12
C414 0.01U_0402_16V7KC414 0.01U_0402_16V7K
12
C383 0.01U_0402_16V7KC383 0.01U_0402_16V7K
12
C407
0.1U_0402_25V6K
@C407
0.1U_0402_25V6K
@
1
2
JSATA1
OCTEK_SAT-22PDAB
CONN@
JSATA1
OCTEK_SAT-22PDAB
CONN@
GND1 23
GND2 24
GND
1
RX+
2
RX-
3
GND
4
TX-
5
TX+
6
GND
7
3.3V
8
3.3V
9
3.3V
10
GND
11
GND
12
GND
13
5V
14
5V
15
5V
16
GND
17
Reserved
18
GND
19
12V
20
12V
21
12V
22
C385 0.01U_0402_16V7KC385 0.01U_0402_16V7K
12
C391
0.1U_0402_25V6K
C391
0.1U_0402_25V6K
1
2
C404
0.1U_0402_25V6K
@C404
0.1U_0402_25V6K
@
1
2
C384 0.01U_0402_16V7KC384 0.01U_0402_16V7K
12
R1635 0_0402_5%@R1635 0_0402_5%@
1 2
C406
0.1U_0402_25V6K
C406
0.1U_0402_25V6K
1
2
C411 0.01U_0402_16V7KC411 0.01U_0402_16V7K
12
C498
22U_0603_6.3V6M
C498
22U_0603_6.3V6M
12
R1636 0_0402_5%@R1636 0_0402_5%@
1 2
C409
1000P_0402_50V7K
C409
1000P_0402_50V7K
1
2
C395
1000P_0402_50V7K
C395
1000P_0402_50V7K
1
2
R504 100K_0402_5%R504 100K_0402_5%
1 2
LNG3DM
U88
LNG3DMTR_LGA16_3X3~D
LNG3DM
U88
LNG3DMTR_LGA16_3X3~D
VDD_IO
1
NC 2
NC 3
SCL/SPC
4
GND 5
VDD
14
CS
8
INT 1
11
INT 2
9
RES 10
GND 12
SDO/SA0
7
SDA / SDI / SDO
6
RES 13
RES 16
RES 15
R501 10K_0402_5%R501 10K_0402_5%
1 2
JSATA2
OCTEK_SAT-22PDAB
CONN@
JSATA2
OCTEK_SAT-22PDAB
CONN@
GND1 23
GND2 24
GND
1
RX+
2
RX-
3
GND
4
TX-
5
TX+
6
GND
7
3.3V
8
3.3V
9
3.3V
10
GND
11
GND
12
GND
13
5V
14
5V
15
5V
16
GND
17
Reserved
18
GND
19
12V
20
12V
21
12V
22
C408
0.1U_0402_25V6K
@C408
0.1U_0402_25V6K
@
1
2
C386 0.01U_0402_16V7KC386 0.01U_0402_16V7K
12
Q29B
DMN66D0LDW-7_SOT363-6
Q29B
DMN66D0LDW-7_SOT363-6
3
5
4
C415
0.1U_0402_25V6K
C415
0.1U_0402_25V6K
1
2
R506
100K_0402_5%
@R506
100K_0402_5%
@
12
C403
0.1U_0402_25V6K
@C403
0.1U_0402_25V6K
@
1
2
C5
10U_0603_6.3V6M
C5
10U_0603_6.3V6M
1
2
R503 100K_0402_5%R503 100K_0402_5%
1 2
R502 10K_0402_5%R502 10K_0402_5%
1 2
Q29A
DMN66D0LDW-7_SOT363-6
Q29A
DMN66D0LDW-7_SOT363-6
61
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Pleace near ODD CONN
Combine +5VMOD with +5V_RUN
ODD CONN
CIS link OK
SATA_ODD_PTX_DRX_N1
SATA_ODD_PTX_DRX_P1
SATA_ODD_PRX_DTX_P1
SATA_ODD_PRX_DTX_N1
MOD_MD
ZODD_WAKE#
ZODD_WAKE#MOD_MD
MOD_MD
MODC_EN#
MODC_EN#
MODC_EN
+5V_MOD
+5V_MOD
+3.3V_ALW_PCH
+3.3V_ALW
DEVICE_DET#<50>
SATA_ODD_PTX_DRX_P1_C<18>
SATA_ODD_PTX_DRX_N1_C<18>
SATA_ODD_PRX_DTX_N1_C<18>
SATA_ODD_PRX_DTX_P1_C<18>
ZODD_WAKE# <50>
MODC_EN<50,54>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
ODD CONN
46 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
ODD CONN
46 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
ODD CONN
46 67Monday, January 13, 2014
Compal Electronics, Inc.
Q81B
DMN66D0LDW-7_SOT363-6
Q81B
DMN66D0LDW-7_SOT363-6
3
5
4
C432 0.01U_0402_16V7KC432 0.01U_0402_16V7K
12
Q81A
DMN66D0LDW-7_SOT363-6
Q81A
DMN66D0LDW-7_SOT363-6
61
2
C428
1000P_0402_50V7K
C428
1000P_0402_50V7K
1
2
C433 0.01U_0402_16V7KC433 0.01U_0402_16V7K
12
C430 0.01U_0402_16V7KC430 0.01U_0402_16V7K
12
C429
0.1U_0402_16V4Z
C429
0.1U_0402_16V4Z
1
2
C434 0.01U_0402_16V7KC434 0.01U_0402_16V7K
12
R796 10K_0402_5%R796 10K_0402_5%
1 2
R515
100K_0402_5%
R515
100K_0402_5%
12
R520 10K_0402_5%R520 10K_0402_5%
1 2
JODD1
SANTA_201901-1
CONN@
JODD1
SANTA_201901-1
CONN@
GND
1
A+
2
A-
3
GND
4
B-
5
B+
6
GND
7
DP
8
+5V
9
+5V
10
MD
11
GND
12
GND
13 GND 14
GND 15
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
Close to JUSB2
For ESD request
Recommended EQA_EQ1
0
0
1
A_EQ0
1
B_EQ0 B_EQ1
1
0
0
1
loss up to 13dB1
0
0
1 loss up to 7.5dB
0
0
1
1
Both A_EQ&B_EQ have internal pull-down 150k
loss up to 9.5dB
loss up to 4.5dB
Parade_PS8713B
Reserve for USB3 reconnect issue from S3 to S0
LInk CIS ok
CPN: SA00005OR20
MPN: PS8713BTQFN24GTR2-A1
PCB footprint: PS8713BTQFN24GTR2_TQFN24_4X4
SHORT DEFAULT
OC[3:0]# for Device 29 (Port 0 - 7)
OC[7:4]# for Device 26 (Port 8 - 13)
Difference with Diesel
CIS link OK
Remove SLG55594
Remove TPS2560
USB3_RX2_P_D+
USB3_RX2_N_D-
USB3_TX2_P_D+
USB3_TX2_N_D-
USBP1_D-
USBP1_D+ USBP1_R_D+
USBP1_R_D-
USB3RN2_RP USB3RN2_C
USB3RP2_C
+USB1_repeater_VDD
USB1_TEST
USB1_TEST
USB1_B_EQ1
USB1_B_EQ1
USB1_B_DE0
USB1_B_DE0
USB3TN2_C
USB3TP2_C
USB1_B_EQ0
USB1_B_DE1
USB1_B_EQ0
USB1_B_DE1
USB1_A_EQ1
USB3TP2_RP
USB3TN2_RP
USB1_A_EQ1
USB3TP2_RP_C
USB3TN2_RP_C
USB1_A_DE0
USB1_A_DE0
USB1_A_EQ0
USB1_A_EQ0
USB1_A_DE1
USB1_A_DE1
USB3RP2_RP
PW RS HARE_ EN#
USB3RN2_RP_R
USB3RP2_RP_R
USBP1_D-
USBP1_D+
ILIM_SEL
USB3_RX2_P_D+
USB3RN2_RP
USB3RP2_RP
USB3TN2_RP
USB3TP2_RP
USB3_RX2_N_D-
USB3_TX2_P_D+
USB3_TX2_N_D-
USB3_RX2_N_D- USB3_RX2_N_D-
USB3_RX2_P_D+ USB3_RX2_P_D+
USB3_TX2_N_D- USB3_TX2_N_D-
USB3_TX2_P_D+ USB3_TX2_P_D+
PW RS HARE_ EN#
USB _PW R_S HR_VB US_E N
USBP1_R_D+
USBP1_R_D-
+5V _USB_ PW R1
+5V _USB_ PW R1
+3.3V_RUN+USB1_repeater_VDD
+3.3V_ALW
+5V _USB_ PW R1
+5V_ALW
+5V_ALW
+5V_ALW
USB3TP2<22>
USB3TN2<22>
USB3RP2 <22>
USB3RN2 <22>
USBP1+<22>
USBP1-<22>
USB _PW R_S HR_EN #<51 >
USB _PW R_S HR_VB US_E N< 50>
USB_OC0#<22>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
USB3.0
47 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
USB3.0
47 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
USB3.0
47 67Monday, January 13, 2014
Compal Electronics, Inc.
C1378 0.1U_0402_10V7KC1378 0.1U_0402_10V7K
12
RI1
10K_0402_5%
RI1
10K_0402_5%
12
U632
PS8713BTQFN24GTR2_TQFN24_4X4
U632
PS8713BTQFN24GTR2_TQFN24_4X4
VDD
1
A_EQ1/SDA_CTL
15
A_DE0/SCL_CTL
16
TEST
14
A_INp
19
VDD
13
GPAD 25
A_INn
20
GND 10
I2C_EN
24 GND 21
A_DE1/NC
18 A_EQ0/NC
17
REXT
7PD#
5
B_DE1/NC 6
A_OUTn 11
A_OUTp 12
B_DE0/I2C_ADDR0 3
B_EQ0/NC 2
B_INn
8B_INp
9B_OUTp 22
B_OUTn 23
B_EQ1/I2C_ADDR1 4
G
D
S
Q348
DMG2301U-7_SOT23-3
@
G
D
S
Q348
DMG2301U-7_SOT23-3
@
2
1 3
R3691 4.7K_0402_5%@R3691 4.7K_0402_5%@
1 2
R3687 0_0402_5%@R3687 0_0402_5%@
1 2
R3692 4.7K_0402_5%@R3692 4.7K_0402_5%@
1 2
JUSB1
LOTES_GAP-AUSB0041-P005A
CONN@
JUSB1
LOTES_GAP-AUSB0041-P005A
CONN@
SSTX-
8
SSTX+
9GND 12
GND 13
VBUS
1
D+
3D-
2
GND
4
SSRX-
5
SSRX+
6
GND
7GND 10
GND 11
R753 0_0402_5%@R753 0_0402_5%@
1 2
R3694 4.7K_0402_5%@R3694 4.7K_0402_5%@
1 2
R3690 4.7K_0402_5%@R3690 4.7K_0402_5%@
1 2
C1374 0.1U_0402_10V7KC1374 0.1U_0402_10V7K
12
R3693 4.7K_0402_5%@R3693 4.7K_0402_5%@
1 2
R3688 4.7K_0402_5%@R3688 4.7K_0402_5%@
1 2
C1377 0.1U_0402_10V7KC1377 0.1U_0402_10V7K
12
+
C323
150U_D2_6.3VY_R15M~D
+
C323
150U_D2_6.3VY_R15M~D
1
2
L43EMC@
DLW21HN900HQ2L_4P
L43EMC@
DLW21HN900HQ2L_4P
11
44
3
3
2
2
R3704
4.99K_0402_1%
R3704
4.99K_0402_1%
1 2
C1375 0.1U_0402_10V7KC1375 0.1U_0402_10V7K
12
R3689 4.7K_0402_5%@R3689 4.7K_0402_5%@
1 2
UI1
TPS254 4RTER_W QF N16_3X 3
UI1
TPS254 4RTER_W QF N16_3X 3
IN
1
NC 9
FAULT#
13
ILIM_SEL
4
EN
5
CTL1
6
CTL2
7
CTL3
8
OUT 12
DP_IN 10
DM_IN 11
DM_OUT
2
DP_OUT
3
ILIM_LO 15
ILIM_HI 16
GND 14
GNDP 17
R3698 0_0402_5%@R3698 0_0402_5%@
1 2
C794
10U_0603_6.3V6M
C794
10U_0603_6.3V6M
1
2
R3695 4.7K_0402_5%@R3695 4.7K_0402_5%@
1 2
L44EMC@
DLW21HN900HQ2L_4P
L44EMC@
DLW21HN900HQ2L_4P
11
44
3
3
2
2
PJP96
PAD-OPEN1x1m
PJP@
PJP96
PAD-OPEN1x1m
PJP@
12
R816
100K_0402_5%
@R816
100K_0402_5%
@
1 2
R3705
0_0402_5%
@
R3705
0_0402_5%
@
1 2
R750 0_0402_5%@R750 0_0402_5%@
1 2
C1373
0.1U_0402_16V4Z
C1373
0.1U_0402_16V4Z
1
2
G
D
S
Q55
DMN65D8LW-7_SOT323-3
@
G
D
S
Q55
DMN65D8LW-7_SOT323-3
@
2
13
D16
TVW DF100 4AD0_ DFN9
EMC@ D16
TVW DF100 4AD0_ DFN9
EMC@
4
5
1
6
2
7
9
8
3
L41
OCE2012120YZF_4P
EMC@ L41
OCE2012120YZF_4P
EMC@
12
3 4
R751 0_0402_5%@R751 0_0402_5%@
1 2
C1372
0.01U_0402_16V7K
C1372
0.01U_0402_16V7K
1
2
C1379 0.1U_0402_10V7KC1379 0.1U_0402_10V7K
12
C1376 0.1U_0402_10V7KC1376 0.1U_0402_10V7K
12
R3696 4.7K_0402_5%@R3696 4.7K_0402_5%@
1 2
R754 0_0402_5%@R754 0_0402_5%@
1 2
D17
L30ESDL5V0C3-2_SOT23-3
EMC@ D17
L30ESDL5V0C3-2_SOT23-3
EMC@
1
2
3
R3697 0_0402_5%@R3697 0_0402_5%@
1 2
R3703
2K_0402_5%
@
R3703
2K_0402_5%
@
1 2
RI2
22.1K_0402_1%
RI2
22.1K_0402_1%
12
R764 0_0402_5%@R764 0_0402_5%@
1 2
R752 0_0402_5%@R752 0_0402_5%@
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DOCK_DET_1
Close to DOCK
Its for Enhance ESD on dock issue.
Close to DOCK
Its for Enhance ESD on dock issue.
audio not transfer to DP display if
play movie when attached external DP display
EMI request add 33ohm for DOCK DVI signals.
System hangs after hot dock.
CIS LINK OK
Dock DPC (Port 2)
DPD_GPU_HPD
CLK_PCI_DOCK
DOCK_DET_R#
DOCK_DET#
DPD_GPU_HPD
DPC_GPU_HPD
SATA_PRX_DKTX_P2
SATA_PRX_DKTX_N2
DAI_BCLK#
DPC_DOCK_SW_AUX
DPC_DOCK_SW_AUX#
SATA_PTX_DKRX_P2
SATA_PTX_DKRX_N2
DPD_DOCK_AUX
DPD_DOCK_AUX#
RED_DOCK
GREEN_DOCK
BLUE_DOCK
DPD_DOCK_LANE_P0
DPD_DOCK_LANE_N0
DPD_DOCK_LANE_P1
DPD_DOCK_LANE_N1
DPD_DOCK_LANE_P2
DPD_DOCK_LANE_N2
DPD_DOCK_LANE_P3
DPD_DOCK_LANE_N3
DPC_DOCK_LANE_C_P0
DPC_DOCK_LANE_C_N0
DPC_DOCK_LANE_C_N1
DPC_DOCK_LANE_C_P1
DPC_DOCK_LANE_C_N2
DPC_DOCK_LANE_C_P2
DPC_DOCK_LANE_C_N3
DPC_DOCK_LANE_C_P3
DPC_GPU_HPD
DPC_DOCK_LANE_P0_R
DPC_DOCK_LANE_N1_R
DPC_DOCK_LANE_N3_R
DPC_DOCK_LANE_P3_R
DPC_DOCK_LANE_N0_R
DPC_DOCK_LANE_P1_R
DPC_DOCK_LANE_N2_R
DPC_DOCK_LANE_P2_R
DPD_DOCK_LANE_P3_R
DPD_DOCK_LANE_N1_R
DPD_DOCK_LANE_P0_R
DPD_DOCK_LANE_N3_R
DPD_DOCK_LANE_P2_R
DPD_DOCK_LANE_N0_R
DPD_DOCK_LANE_N2_R
DPD_DOCK_LANE_P1_R
DPD_CA_DET
DAI_12MHZ#
+DOCK_PWR_BAR
+DOCK_PWR_BAR
+LOM_VCT
+NBDOCK_DC_IN_SS
+3.3V_ALW
+LOM_VCT
DPD_GPU_HPD<37> DPC_GPU_HPD <38>
USBP3+ <22>
USBP3- <22>
DOCK_AC_OFF <63>
RED_DOCK<35>
BLUE_DOCK<35>
GREEN_DOCK<35>
VSYNC_DOCK<35>
DAT_MSE<51>
CLK_MSE<51>
DAI_BCLK#<49>
DAI_LRCK#<49>
DAI_DI<49>
DAI_DO#<49>
DAI_12MHZ#<49>
D_LAD1<50>
D_LAD0<50>
D_LAD2<50>
D_LAD3<50>
D_LFRAME#<50>
D_CLKRUN#<50>
D_SERIRQ<50>
D_DLDRQ1#<50>
CLK_PCI_DOCK<20>
DOCK_LCD_SMBCLK<30,51>
DOCK_LCD_SMBDAT<30,51>
DOCK_SMB_ALERT#<50,55>
DOCK_PSID<55>
DOCK_PWR_BTN#<51>
DOCK_LOM_SPD10LED_GRN#<39>
HSYNC_DOCK<35>
DOCK_LOM_SPD100LED_ORG# <39>
DAT_KBD <51>
CLK_KBD <51>
DOCK_LOM_TRD0+ <39>
DOCK_LOM_TRD0- <39>
DOCK_LOM_TRD2- <39>
DOCK_LOM_TRD2+ <39>
ACAV_DOCK_SRC# <63>
CLK_DDC2_DOCK <35>
DAT_DDC2_DOCK <35>
SATA_PTX_DKRX_P2_C <18>
SATA_PTX_DKRX_N2_C <18>
SATA_PRX_DKTX_P2_C <18>
BREATH_LED# <51,52>
DOCK_LOM_ACTLED_YEL# <39>
DOCK_LOM_TRD1- <39>
DOCK_LOM_TRD1+ <39>
DOCK_LOM_TRD3- <39>
DOCK_LOM_TRD3+ <39>
DOCK_DCIN_IS+ <62>
DOCK_DCIN_IS- <62>
DOCK_POR_RST# <51>
SATA_PRX_DKTX_N2_C <18>
USBP6- <22>
USBP6+ <22>
SLICE_BAT_PRES#<50,55,63> DOCK_DET# <50>
DPC_DOCK_SW_AUX <38>
DPC_DOCK_SW_AUX# <38>
DPC_CA_DET <38>DPD_CA_DET<37>
DPD_DOCK_AUX#<37>
DPD_DOCK_AUX<37>
USB3RN3 <22>
USB3RP3 <22>
USB3TN3 <22>
USB3TP3 <22>
DPD_GPU_LANE_P0<37>
DPD_GPU_LANE_N0<37>
DPD_GPU_LANE_P1<37>
DPD_GPU_LANE_N1<37>
DPD_GPU_LANE_P2<37>
DPD_GPU_LANE_N2<37>
DPD_GPU_LANE_P3<37>
DPD_GPU_LANE_N3<37>
DPC_DOCK_LANE_P2 <38>
DPC_DOCK_LANE_N2 <38>
DPC_DOCK_LANE_P0 <38>
DPC_DOCK_LANE_N0 <38>
DPC_DOCK_LANE_P3 <38>
DPC_DOCK_LANE_N3 <38>
DPC_DOCK_LANE_P1 <38>
DPC_DOCK_LANE_N1 <38>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Docking
48 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Docking
48 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Docking
48 67Monday, January 13, 2014
Compal Electronics, Inc.
R757
100K_0402_5%
R757
100K_0402_5%
12
C695
0.033U_0402_16V7K
@C695
0.033U_0402_16V7K
@
1
2
C696
0.033U_0402_16V7K
@C696
0.033U_0402_16V7K
@
1
2
C703
0.1U_0603_50V7K
@
C703
0.1U_0603_50V7K
@
1
2
R2171 33_0402_5%EMC@ R2171 33_0402_5%EMC@
1 2
C4410.1U_0402_10V7K C4410.1U_0402_10V7K
1 2
C701
1U_0402_6.3V6K
@C701
1U_0402_6.3V6K
@
1
2
JDOCK1
JAE_WD2F144WB5R400
CONN@JDOCK1
JAE_WD2F144WB5R400
CONN@
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
53
55
55
57
57
59
59
61
61
63
63
65
65
67
67
69
69
71
71
73
73
75
75
77
77
79
79
81
81
83
83
85
85
87
87
89
89
91
91
93
93
95
95
97
97
99
99
101
101
103
103
105
105
107
107
109
109
111
111
113
113
115
115
117
117
119
119
121
121
123
123
125
125
127
127
129
129
131
131
133
133
135
135
137
137
22
44
66
88
10 10
12 12
14 14
16 16
18 18
20 20
22 22
24 24
26 26
28 28
30 30
32 32
34 34
36 36
38 38
40 40
42 42
44 44
46 46
48 48
50 50
52 52
54 54
56 56
58 58
60 60
62 62
64 64
66 66
68 68
70 70
72 72
74 74
76 76
78 78
80 80
82 82
84 84
86 86
88 88
90 90
92 92
94 94
96 96
98 98
100 100
102 102
104 104
106 106
108 108
110 110
112 112
114 114
116 116
118 118
120 120
122 122
124 124
126 126
128 128
130 130
132 132
134 134
136 136
138 138
GND1
145
PWR1
146 PWR2 149
GND2 152
Shield_G
153
Shield_G
154
Shield_G
155
Shield_G
156
Shield_G
157
Shield_G
158
139
139 140 140
141
141 142 142
143
143 144 144
PWR1
147
PWR1
148
PWR2 150
PWR2 151
Shield_G 159
Shield_G 160
Shield_G 161
Shield_G 162
Shield_G 163
Shield_G 164
R2160
100K_0402_5%
R2160
100K_0402_5%
12
C697 0.01U_0402_16V7KC697 0.01U_0402_16V7K
12
D33
L30ESD24VC3-2_SOT23-3
@D33
L30ESD24VC3-2_SOT23-3
@
1
2
3
C698 0.01U_0402_16V7KC698 0.01U_0402_16V7K
12
C702
0.1U_0603_50V7K
@
C702
0.1U_0603_50V7K
@
1
2
R2165 33_0402_5%EMC@ R2165 33_0402_5%EMC@
1 2
C4380.1U_0402_10V7K C4380.1U_0402_10V7K
1 2
C4400.1U_0402_10V7K C4400.1U_0402_10V7K
1 2
R2174 33_0402_5%EMC@ R2174 33_0402_5%EMC@
1 2
R2177 33_0402_5%EMC@ R2177 33_0402_5%EMC@
1 2
C426 0.1U_0402_10V7KC426 0.1U_0402_10V7K
12
R2167 33_0402_5%EMC@ R2167 33_0402_5%EMC@
1 2
C366 0.1U_0402_10V7KC366 0.1U_0402_10V7K
12
R2170 33_0402_5%EMC@ R2170 33_0402_5%EMC@
1 2
C425 0.1U_0402_10V7KC425 0.1U_0402_10V7K
12
C4440.1U_0402_10V7K C4440.1U_0402_10V7K
1 2
C4310.1U_0402_10V7K C4310.1U_0402_10V7K
1 2
R756
33_0402_5%
EMC@
R756
33_0402_5%
EMC@
12
R2176 33_0402_5%EMC@ R2176 33_0402_5%EMC@
1 2
C699 0.01U_0402_16V7KC699 0.01U_0402_16V7K
1 2
CE6
4.7U_0805_25V6-K
@CE6
4.7U_0805_25V6-K
@
1
2
RE11
10_0402_1%
EMC@
RE11
10_0402_1%
EMC@
12
CE8
4.7P_0402_50V8C
EMC@
CE8
4.7P_0402_50V8C
EMC@
1
2
C369 0.1U_0402_10V7KC369 0.1U_0402_10V7K
12
R492 1M_0402_5%R492 1M_0402_5%
1 2
R2172 33_0402_5%EMC@ R2172 33_0402_5%EMC@
1 2
C4420.1U_0402_10V7K C4420.1U_0402_10V7K
1 2
R2179 33_0402_5%EMC@ R2179 33_0402_5%EMC@
1 2
C424 0.1U_0402_10V7KC424 0.1U_0402_10V7K
12
R2168 33_0402_5%EMC@ R2168 33_0402_5%EMC@
1 2
C4390.1U_0402_10V7K C4390.1U_0402_10V7K
1 2
C4430.1U_0402_10V7K C4430.1U_0402_10V7K
1 2
C704
12P_0402_50V8J
EMC@
C704
12P_0402_50V8J
EMC@
1
2
R2173 33_0402_5%EMC@ R2173 33_0402_5%EMC@
1 2
R2164 33_0402_5%EMC@ R2164 33_0402_5%EMC@
1 2
R2175 33_0402_5%EMC@ R2175 33_0402_5%EMC@
1 2
R2178 33_0402_5%EMC@ R2178 33_0402_5%EMC@
1 2
C427 0.1U_0402_10V7KC427 0.1U_0402_10V7K
12
R2166 33_0402_5%EMC@ R2166 33_0402_5%EMC@
1 2
CE9
4.7P_0402_50V8C
EMC@
CE9
4.7P_0402_50V8C
EMC@
1
2
C700 0.01U_0402_16V7KC700 0.01U_0402_16V7K
1 2
C368 0.1U_0402_10V7KC368 0.1U_0402_10V7K
12
D32
RB751S40T1_SOD523-2
D32
RB751S40T1_SOD523-2
21
C367 0.1U_0402_10V7KC367 0.1U_0402_10V7K
12
RE12
10_0402_1%
EMC@
RE12
10_0402_1%
EMC@
12
R2169 33_0402_5%EMC@ R2169 33_0402_5%EMC@
1 2
R75510K_0402_5% R75510K_0402_5%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
WireLess ON/OFF CONN
Power Button CONN
Place on Bottom
Power Switch for debug
Link CIS OK
Difference with Diesel
Difference with Diesel
Left Side JUSB1 ----->
Left Side JUSB2----->
Left Side JUSB3----->
<----- Left Side JUSB1
<----- Left Side JUSB2
<----- Left Side JUSB3
94: remove PCIE_WAKE#
Add LID_CL#
Link CIS OK
POWER_SW#_MB
POWER_SW#_MB
+5V_ALW +3.3V_RUN +3.3V_ALW+5V_RUN
+5V_ALW
+5V_ALW
+1.5V_RUN
+RTC_CELL
+3.3V_RUN
+5V_RUN
+3.3V_ALW
POWER_SW#_MB<41,51>
BREATH_WHITE_LED<52>
PCIE_PTX_MMIRX_N4<22>
PCIE_PTX_MMIRX_P4<22>
USB3RN6<22>
USB3RP6<22>
USB3TN6<22>
USB3TP6<22>
USB3TN5<22>
USB3TP5<22>
USB3RN5<22>
USB3RP5<22>
USBP0+<22>
USBP0-<22>
PCH_AZ_CODEC_BITCLK<18>
DAI_12MHZ#<48>
PCH_AZ_CODEC_SYNC<18>
PCH_AZ_CODEC_RST#<18>
PCH_AZ_CODEC_SDIN0<18>
PCH_AZ_CODEC_SDOUT<18>
DOCK_HP_DET<50>
DOCK_MIC_DET<50>
AUD_HP_NB_SENSE<50>
PCIE_PRX_MMITX_P4<22>
PCIE_PRX_MMITX_N4<22>
USBP2- <22>
USBP2+ <22>
USB_OC1# <22>
USB_OC4# <22>
USB_OC2# <18,22>
USB_PWR_EN2# <50>
USBP9+ <22>
USBP9- <22>
USB3RN1 <22>
USB3RP1 <22>
USB3TN1 <22>
USB3TP1 <22>
DAI_DO# <48>
DAI_DI <48>
DAI_LRCK# <48>
DAI_BCLK# <48>
DMIC_CLK <30>
DMIC0 <30>
EN_I2S_NB_CODEC# <50>
AUD_NB_MUTE# <50>
BEEP <51>
SPKR <18>
CLK_PCIE_CARD# <20>
CLK_PCIE_CARD <20>
CARDCLK_REQ# <18,20>
PLTRST_MMI# <19>
LID_CL# <50,52>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
IO / PWR Button
49 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
IO / PWR Button
49 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
IO / PWR Button
49 67Monday, January 13, 2014
Compal Electronics, Inc.
JPB1
ACES_50228-0067N-001
CONN@JPB1
ACES_50228-0067N-001
CONN@
1
1
2
2
3
3
4
4
5
5
6
6
GND
7
GND
8
JIO1
FOX_QTSA1401-7011-9H
CONN@JIO1
FOX_QTSA1401-7011-9H
CONN@
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
53
55
55
57
57
59
59
61
61
63
63
65
65
67
67
69
69
71
71
73
73
75
75
77
77
79
79
81
81
83
83
85
85
87
87
89
89
91
91
93
93
95
95
97
97
99
99
101
101
103
103
105
105
107
107
109
109
111
111
113
113
115
115
117
117
119
119
121
121
123
123
125
125
127
127
129
129
131
131
133
133
135
135
137
137
22
44
66
88
10 10
12 12
14 14
16 16
18 18
20 20
22 22
24 24
26 26
28 28
30 30
32 32
34 34
36 36
38 38
40 40
42 42
44 44
46 46
48 48
50 50
52 52
54 54
56 56
58 58
60 60
62 62
64 64
66 66
68 68
70 70
72 72
74 74
76 76
78 78
80 80
82 82
84 84
86 86
88 88
90 90
92 92
94 94
96 96
98 98
100 100
102 102
104 104
106 106
108 108
110 110
112 112
114 114
116 116
118 118
120 120
122 122
124 124
126 126
128 128
130 130
132 132
134 134
136 136
138 138
139
139 140 140
GND
141 GND 142
SW1
SKRBAAE010_4P
SW1
SKRBAAE010_4P
1
3
2
4
C722
0.1U_0402_16V4Z
@
C722
0.1U_0402_16V4Z
@
1
2
C759
100P_0402_50V8J
@C759
100P_0402_50V8J
@
1
2
PWRSW1
@SHORT PADS~D
@PWRSW1
@SHORT PADS~D
@
1
122
C723
0.1U_0402_16V4Z
@
C723
0.1U_0402_16V4Z
@
1
2
C763
0.1U_0402_16V4Z
@
C763
0.1U_0402_16V4Z
@
1
2
C721
0.1U_0402_16V4Z
@
C721
0.1U_0402_16V4Z
@
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
VGA_ID0
Discrete
UMA 1
0
for eDP_DET# pull high usage (RP2_pin 5).
Remove WIRELESS_ON#/OFF
+CAP_LDO trace width 20 mils
CIS LINK OK
SHORT DEFAULT
Remove CPU_VTT_ON
B45: change DGPU_PWR_EN to PCH.
B58: Remove SLP_ME_CSW_DEV#
Remove SYS_PWROK,
SPI_WP#_SEL
WLAN_RADIO_DIS#
PROCHOT_GATE
MSATA_PCIE_PIN51
IMVP_PWRGD
SP_TPM_LPC_EN
MCARD_MISC_PWREN
TEMP_ALERT#
MASK_SATA_LED#
LPC_LDRQ0#
SLICE_BST_CHG_EN
DIS_BAT_PROCHOT#
DDR_1.35V_CNTRL0
DDR_1.35V_CNTRL1
Remove DYN_TURB_GPU_PWR_ALRT#
A46: Remove DYN_TURB_GPU_PWR_ALRT#
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Remove SP_TPM_LPC_EN
Remove SLICE_BST_CHG_EN
B51: Remove DIS_BAT_PROCHOT#
Remove "WIRELESS_ON#/OFF" PU
Remove DDR_1.35V_CNTRL1
Remove DDR_1.35V_CNTRL1
Move IMVP_VR_ON from 5048_B66 to 5085_A1
Remove R102 for double PD.
LID_CL_SIO#
DOCK_SMB_ALERT#
USB_PWR_EN2#
CLK_PCI_5048CLK_SIO_14M
VGA_ID
SYS_LED_MASK#
MXM_DP_HDMI_HPD
HW_GPS_DISABLE#
SLICE_BAT_PRES#
GPU_PWR_LEVEL
GPIOG1
LCD_TST
SLICE_BAT_ON
0.675V_DDR_VTT_ON
GPIOH6
WWAN_RADIO_DIS#
USB_PWR_SHR_VBUS_EN
DGPU_ALERT#
D_DLDRQ1#
D_SERIRQ
D_CLKRUN#
WLAN_WIGIG60GHZ_DIS#
LED_SATA_DIAG_OUT#
BT_RADIO_DIS#
SIO_SLP_WLAN#
PBA_GPU_SEL# NGFF_CONFIG_1
D_CLKRUN#
D_SERIRQ
LPC_LFRAME#
LPC_LDRQ1#
D_LAD3
D_LAD2
LPC_LAD1
LPC_LAD0
CLK_PCI_5048
BC_INT#_ECE5048
BC_CLK_ECE5048
SLICE_BAT_ON
CLK_SIO_14M
USB_PWR_EN2#
USH_PWR_STATE#
HW_GPS_DISABLE#
LCD_TST
PSID_DISABLE#
DOCKED
AUD_NB_MUTE#
RUNPWROK
LCD_VCC_TEST_EN
AUD_HP_NB_SENSE
DGPU_ALERT#
NGFF_CONFIG_2
GPIOG1
WIRELESS_LED#
DOCK_SMB_ALERT#
GPU_PWR_LEVEL
WWAN_RADIO_DIS#
3.3V_RUN_GFX_ON
DGPU_PWROK
ZODD_WAKE#
GPIO_PSID_SELECT
0.675V_DDR_VTT_ON
SATA4_PCIE1#
DOCK_HP_DET
CCD_OFF
PCIE_WAKE#
PCIE_WAKE#
NGFF_CONFIG_0
DGPU_SELECT#
TB_STAT#
GPIOH6
EC5048_TX
CLKRUN#
IRQ_SERIRQ
PCH_PLTRST#_EC
D_LFRAME#
D_DLDRQ1#
LPC_LAD3
LPC_LAD2
+CAP_LDO
D_LAD1
D_LAD0
BC_DAT_ECE5048
NVRAM_PWR_EN
SLICE_BAT_PRES#
NGFF_CONFIG_3
EC_32KHZ_ECE5048
EN_I2S_NB_CODEC#
EN_DOCK_PWR_BAR
PANEL_BKEN_EC
DOCK_DET#
3.3V_WWAN_EN
WWAN_WAKE#
WWAN_WAKE#
SYS_LED_MASK#
USB_PWR_SHR_VBUS_EN
CRT_SWITCH
LAN_DISABLE#_R
LID_CL_SIO#
TOUCH_SCREEN_PD#
VGA_ID
EDID_SELECT#
BCM5882_ALERT#
AUX_EN_WOWL
WLAN_LAN_DISBL#
MODC_EN
DOCK_MIC_DET
MXM_DP_HDMI_HPD
PCH_SATA_MOD_EN#
DEVICE_DET#
DEVICE_DET#
CPU_DETECT#
CPU_DETECT#
TBT_PWR_EN
SLOT3_CONFIG_0
MASK_SATA_LED#
NGFF_CONFIG_0
NGFF_CONFIG_1
NGFF_CONFIG_2
NGFF_CONFIG_3
SLOT3_CONFIG_0
+3.3V_ALW
+3.3V_ALW
+3.3V_RUN
+3.3V_ALW
+3.3V_ALW_U46 +3.3V_ALW
LID_CL# <49,52>
WLAN_WIGIG60GHZ_DIS#<42>
LED_SATA_DIAG_OUT# <52>
BT_RADIO_DIS#<42>
SIO_SLP_WLAN#<19,44>
PBA_GPU_SEL#<36> NGFF_CONFIG_1 <42>
D_CLKRUN# <48>
D_SERIRQ <48>
LPC_LFRAME# <21,51>
LPC_LDRQ1# <21>
D_LAD3 <48>
D_LAD2 <48>
LPC_LAD1 <21,51>
LPC_LAD0 <21,51>
CLK_PCI_5048 <20>
BC_INT#_ECE5048 <51>
BC_CLK_ECE5048 <51>
SLICE_BAT_ON<63>
CLK_SIO_14M <20>
USB_PWR_EN2#<49>
USH_PWR_STATE#<41>
HW_GPS_DISABLE#<42>
LCD_TST<30>
PSID_DISABLE#<55>
DOCKED<38,39>
AUD_NB_MUTE#<49>
RUNPWROK <51,7>
LCD_VCC_TEST_EN<30>
AUD_HP_NB_SENSE<49>
DGPU_ALERT#<17>
NGFF_CONFIG_2 <42>
WIRELESS_LED#<42,52>
DOCK_SMB_ALERT#<48,55>
GPU_PWR_LEVEL<17>
WWAN_RADIO_DIS#<42>
3.3V_RUN_GFX_ON<20,44,54>
DGPU_PWROK<17,23>
ZODD_WAKE#<46>
GPIO_PSID_SELECT <55>
0.675V_DDR_VTT_ON <57>
SATA4_PCIE1# <18,23>
DOCK_AC_OFF_EC <63>
DOCK_HP_DET <49>
CCD_OFF <30>
PCIE_WAKE# <17,32,42>
NGFF_CONFIG_0 <42>
DGPU_SELECT#<29,30,35>
TB_STAT#<62>
EC5048_TX<51>
CLKRUN# <19,51>
IRQ_SERIRQ <21,51>
PCH_PLTRST#_EC <19,41,42,43,51>
D_LFRAME# <48>
D_DLDRQ1# <48>
LPC_LAD2 <21,51>
LPC_LAD3 <21,51>
D_LAD1 <48>
D_LAD0 <48>
BC_DAT_ECE5048 <51>
NVRAM_PWR_EN<44>
SLICE_BAT_PRES#<48,55,63>
NGFF_CONFIG_3 <42>
EC_32KHZ_ECE5048 <51>
EN_I2S_NB_CODEC#<49>
EN_DOCK_PWR_BAR<63>
PANEL_BKEN_EC<30>
DOCK_DET#<48>
3.3V_WWAN_EN<44>
WWAN_WAKE#<42>
SYS_LED_MASK#<39,52>
USB_PWR_SHR_VBUS_EN<47>
CRT_SWITCH<35>
LAN_DISABLE#_R<39>
TOUCH_SCREEN_PD#<30>
EDID_SELECT#<35>
BCM5882_ALERT#<41>
AUX_EN_WOWL <44>
WLAN_LAN_DISBL# <39>
MODC_EN <46,54>
DOCK_MIC_DET <49>
MXM_DP_HDMI_HPD<17>
PCH_SATA_MOD_EN# <18>
DEVICE_DET# <46>
CPU_DETECT#<7>
TBT_PWR_EN <34>
SLOT3_CONFIG_0 <43>
MASK_SATA_LED# <52>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
SIO (ECE5048)
50 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
SIO (ECE5048)
50 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
SIO (ECE5048)
50 67Monday, January 13, 2014
Compal Electronics, Inc.
T165PAD~D @T165PAD~D @
R795
10_0402_1%
@R795
10_0402_1%
@
12
R807 10_0402_1%R807 10_0402_1%
12
R2158 100K_0402_5%R2158 100K_0402_5%
1 2
RE16 100K_0402_5%RE16 100K_0402_5%
1 2
R1125 100K_0402_5%R1125 100K_0402_5%
1 2
R763 10K_0402_5%R763 10K_0402_5%
1 2
C719
0.1U_0402_10V7K
C719
0.1U_0402_10V7K
1
2
R782 100K_0402_5%R782 100K_0402_5%
12
R804 1K_0402_1%R804 1K_0402_1%
1 2
C710
0.1U_0402_25V6K
C710
0.1U_0402_25V6K
1
2
C714
4.7U_0603_6.3V6K
C714
4.7U_0603_6.3V6K
1
2
RE14 100K_0402_5%RE14 100K_0402_5%
1 2
PJP29
PAD-OPEN1x1m
@PJP29
PAD-OPEN1x1m
@
12
RP3
100K_0804_8P4R_5%
RP3
100K_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP9
100K_0804_8P4R_5%
RP9
100K_0804_8P4R_5%
1 8
2 7
3 6
4 5
R773 10K_0402_5%R773 10K_0402_5%
1 2
C708
0.1U_0402_10V7K
C708
0.1U_0402_10V7K
1
2
C716
0.047U_0402_16V4Z
C716
0.047U_0402_16V4Z
1
2
R77510K_0402_5% R77510K_0402_5%
12
R794
10_0402_1%
@R794
10_0402_1%
@
12
R779 10K_0402_5%R779 10K_0402_5%
1 2
RE15 100K_0402_5%RE15 100K_0402_5%
1 2
R803
100K_0402_5%
R803
100K_0402_5%
12
R768 10K_0402_5%R768 10K_0402_5%
1 2
R805
100K_0402_5%
R805
100K_0402_5%
12
RP8
100K_0804_8P4R_5%
RP8
100K_0804_8P4R_5%
1 8
2 7
3 6
4 5
R800
100K_0402_5%
@R800
100K_0402_5%
@
12
RE13 100K_0402_5%RE13 100K_0402_5%
1 2
U46
DB Version 0.4
ECE5048-LZY_DQFN132_11X11~D
U46
DB Version 0.4
ECE5048-LZY_DQFN132_11X11~D
GPIOA0
B52
GPIOA1
A49
GPIOA2
B53
GPIOA3
A50
GPIOA4
B54
GPIOA5
A51
GPIOA6
B55
GPIOA7
A52
GPIOD1
B32
GPIOD2
A31
GPIOD3
B33
GPIOD4
B15
GPIOD5
A15
GPIOD6
B16
GPIOD7
A16
GPIOF7
B58 GPIOF6
A55 GPIOF5
B59 GPIOF4/TACH7
A56
GPIOL0/PWM7 B60
GPIOL1/PWM8 A57
GPIOF3/TACH8
B61 GPIOF2
A58 GPIOF1
B62 GPIOF0
A59
VCC1 B5
CAP_LDO B46
TEST_PIN B19
LAD0 A27
LAD1 A26
LAD2 B26
LAD3 B25
LFRAME# A21
LRESET# B22
PCICLK A28
CLKRUN# B20
GPIOI0 A23
LDRQ1# A22
SER_IRQ B21
14.318MHZ/GPIOM0 A32
GPIOM4/PWM6 B51
DLAD0 B29
DLAD1 B28
DLAD2 A25
DLAD3 A24
DLFRAME# B23
DCLKRUN# A19
DLDRQ1# B24
DSER_IRQ A20
PWRGD A4
OUT65 B56
VSS B27
GPIOM3/PWM4 B39
GPIOL2/PWM0 B64
VCC1 A17
VCC1 B30
VCC1 A43
VCC1 A54
BC_INT# A29
BC_DAT B31
BC_CLK A30
GPIOB0
A33
GPIOB1
B36
GPOC2
A34
GPOC3
B37
GPOC4
A35
GPOC5
B38
GPOC6/TACH4
A36
GPIOC7
A37
GPIOD0
B40
GPIOC1
A38
GPIOC0
B41
GPIOB7
A39
GPIOB6
B42
GPIOB5
A40
GPIOB4
B43
GPIOB3
A41
GPIOB2
B44
GPIOH0
B13
GPIOH1
A13
SYSOPT1/GPIOH2
A53
SYSOPT0/GPIOH3
B57
GPIOH4
B14
GPIOH5
A14
GPIOH6
B17
GPIOH7
B18
GPIOE0/RXD
A1
GPIOE1/TXD
B2
GPIOE2/RTS#
A2
GPIOE3/DSR#
B3
GPIOE4/CTS#
A3
GPIOE5/DTR#
B45
GPIOE6/RI#
A42
GPIOE7/DCD#
B4
GPIOG0/TACH5
B47
GPIOG1
A45
GPIOG2
B48
GPIOG3
A46
GPIOG4
B49
GPIOG5
A47
GPIOG6
B50
GPIOG7/TACH6
A48
GPIOK0 A8
GPIOK1/TACH3 B9
GPIOK2 B10
GPIOK3 A10
GPIOK4 B11
GPIOK5 A11
GPIOK6 B12
GPIOK7 A12
GPIOI1 B63
GPIOI2/TACH0 A60
GPIOI3 A61
GPIOI4 B65
GPIOI5 A62
GPIOI6 B66
GPIOI7 A63
GPIOJ0 B67
GPIOJ1/TACH1 A64
GPIOJ2/TACH2 A5
GPIOJ3 B6
GPIOJ4 A6
GPIOJ5 B7
GPIOJ6 A7
GPIOJ7 B8
GPIOM1 B34
CLK32/GPIOM2 B35
EP C1
GPIOL3/PWM1 B68
GPIOL4/PWM3 A9
GPIOL5/PWM2 B1
GPIOL6 A18
GPIOL7/PWM5 A44
C712
4.7P_0402_50V8C
@C712
4.7P_0402_50V8C
@
1
2
RP4
100K_0804_8P4R_5%
RP4
100K_0804_8P4R_5%
1 8
2 7
3 6
4 5
C717
0.1U_0402_10V7K
C717
0.1U_0402_10V7K
1
2
R17100K_0402_5% R17100K_0402_5%
12
C718
0.1U_0402_10V7K
C718
0.1U_0402_10V7K
1
2
C713
4.7P_0402_50V8C
@C713
4.7P_0402_50V8C
@
1
2
R759 10K_0402_5%R759 10K_0402_5%
1 2
C709
0.1U_0402_25V6K
C709
0.1U_0402_25V6K
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
R875 C744
*
BOARD_ID rise time is measured from 5%~68%.
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Place close pin A29
32 KHz Clock
Place close pin A21
Channel
DP1/DN1
DP2/DN2
DP3/DN3
DP4/DN4
Location
CPU VR
MXM(BOT)
WiGig
DIMM(TOP)
A001K
4700p
***
X01
X00
REV
4700p240K
4700p
4700p130K
33K
4700p
4700p
4.3K
2K
X02
***
1: Channel 1 will provide Thermistor Readings
0: Channel 1 will provide Diode Readings
PN change to SD309220180
PN change to SD309470180
Rest=1.33k, Tp=93degree
DP3/DN3 for SODIMM(TOP) on Q14,
place Q14 close to SODIMM(TOP) and C272 close to Q14
DP4/DN4 for WiGig on Q15,
place Q15 close to WiGig and C288 close to Q15
C292 Place near U51.A48
DN1a/DP1a for CPU VR on Q26, place Q26 close
to CPU and C339 close to Q26
DP1/DN1 for CPU OTP on Q16, place Q16 close
to CPU and C273 close to Q16.
DN2a/DP2a for MXM(BOT) on Q17, place Q17 close
to MXM(BOT) and C340 close to Q17
DP2/DN2 for MXM(TOP side) on Q27, place Q27 close
to MXM(TOP side) and C291 close to Q27.
DP1a/DN1a
DP2a/DN2a
CPU OTP
MXM(TOP)
Difference with Diesel Difference with Diesel
CIS LINK OK
15mil
ESR <2ohms
SHORT DEFAULT
C1343, C1350, C1351, C1346 Place near U51
R866 close to U51 at least 250mils
Remove LCD_SMBDAT,
LCD_SMBCLK,
CARD_SMBDAT
CARD_SMBCLK
VOL_MUTE
EMC4021_BC_DAT
EMC4021_BC_CLK
1.35V_SUS_PWRGD
VOL_DOWN
CPU1.5V_S3_GATE
SYSTEM_ID
HOST_DEBUG_RX
EC_WAKE#
1.05V_A_PWRGD
DYN_TUR_CURRNT_SET#
EMC4021_BC_INT#
remove "VOL_DOWN" PU
remove "VOL_MUTE" PU
remove "CPU1.5V_S3_GATE" PD (5085_A36)
remove SYSTEM_ID
(5085_A10)
remove "HOST_DEBUG_RX" PU (5085_B46)
remove "DYN_TUR_CURRNT_SET#" PU (5085_A35)
remove EC wake circuit.
trace width 20 mils
trace width 20 mils
CIS link OK
remove Q52
CIS link OK
remove "VOL_UP" PU
Remove THERMATRIP3# CKT.
Remove THERMATRIP3# CKT.
By pass PROCHOT CKT.
BC_DAT_ECE5048
JTAG_TDI
BC_DAT_ECE1117
JTAG_CLK
JTAG_TDO
FWP#
POWER_SW_IN#
JTAG_TMS
JTAG_RST#
PROCHOT#_EC
EC5048_TX
HOST_DEBUG_TX
MSCLK
MSDATA
MEC_XTAL2MEC_XTAL1
CLK_PCI_MEC
DOCK_POR_RST#
PCH_RSMRST#
MSDATA
RESET_OUT#
DOCK_PWR_SW#
GPU_SMBDAT
GPU_SMBCLK
BOARD_ID
VSET_5085
A_ON
THSEL_STRAP
PBAT_SMBDAT
PBAT_SMBCLK
CHARGER_SMBDAT
CHARGER_SMBCLK
EN_INVPWR
AC_PRESENT
THERMATRIP2#
VCI_IN3#
REM_DIODE1_P
REM_DIODE1_N
REM_DIODE2_N
REM_DIODE2_P
REM_DIODE4_P
REM_DIODE4_N
REM_DIODE3_N
REM_DIODE3_P
PCH_ALW_ON
DOCK_POR_RST#
PECI_EC_R
CLK_KBD
DAT_KBD
CLK_MSE
DAT_MSE
+VR_CAP
RUN_ON
RUN_ON
FAN2_PWM
FAN2_TACH_FB
+3.3V_VTR
+VTR_ADC
+RTC_CELL_VBAT
AC_DIS
I_ADPI_ADP_R
VSET_5085
SIO_SLP_S5#
BC_INT#_ECE1117
DGPU_THERMTRIP#
BC_CLK_ECE1117
DOCK_POR_RST#
FAN1_PWM
EN_INVPWR
SIO_RCIN#
IRQ_SERIRQ
CLK_PCI_MEC
DOCK_LCD_SMBCLK
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
CLKRUN#
SIO_EXT_SCI#
PCH_ALW_ON
SIO_SLP_S3#
CLK_TP_SIO
DAT_TP_SIO
CLK_KBD
CLK_MSE
DOCK_LCD_SMBDAT
MSDATA
BC_INT#_ECE5048
BC_CLK_ECE5048
PCH_PCIE_WAKE#
PROCHOT#_EC
CHARGER_SMBDAT
CHARGER_SMBCLK
PECI_EC_R
PBAT_PRES#
SML1_SMBCLK
SML1_SMBDATA
USH_SMBCLK
USH_SMBDAT
JTAG_TDI
JTAG_TMS AC_PRESENT
BAT2_LED#
PBAT_SMBCLK
PBAT_SMBDAT
SYSPWR_PRES
SIO_EXT_SMI#
MEC_XTAL2 MEC_XTAL2_R
MEC_XTAL1
DOCK_PWR_SW#
ACAV_IN
ENVDD_PCH
PM_APWROK
BAT1_LED#
BOARD_ID
REM_DIODE2_P
REM_DIODE4_N
REM_DIODE3_P
REM_DIODE1_P
REM_DIODE2_N
REM_DIODE1_N
REM_DIODE3_N
REM_DIODE4_P
BEEP
ACAV_IN_NB
BC_DAT_ECE1117
FAN1_TACH_FB
SIO_SLP_S4#
SIO_SLP_LAN#
USB_PWR_SHR_EN#
USB_PWR_SHR_EN#
RESET_OUT#
DAT_KBD
DAT_MSE
MSCLK
HOST_DEBUG_TX
BC_DAT_ECE5048
ME_FWP_EC
JTAG_RST#
GPU_SMBCLK
GPU_SMBDAT
+PECI_VREF
SIO_SLP_SUS#
JTAG_TDO
JTAG_CLK
BREATH_LED#
SIO_PWRBTN#
I_BATT
FWP#
POWER_SW_IN#
VCI_IN2#
VCI_IN2#
VCI_IN3#
SUSACK#
SSD_SATA5_PCIE2#
PS_ID
BIA_PWM_EC
PCH_PLTRST#_EC
LPC_LFRAME#
LAN_WAKE#
RUNPWROK
SIO_SLP_A#
PCH_RSMRST#
ALWON
THERMATRIP2#
THSEL_STRAP
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
PCH_PLTRST#_EC
RUNPWROK
RUNPWROK
IMVP_VR_ON
1.05V_0.8V_PWROK
DOCK_LCD_SMBCLK
DOCK_LCD_SMBDAT
+3.3V_ALW
+3.3V_ALW
+RTC_CELL
+3.3V_ALW
+RTC_CELL
+3.3V_ALW
+3.3V_ALW
+RTC_CELL
+3.3V_RUN
+3.3V_ALW
+5V_RUN +PCH_VCCDSW3_3
+3.3V_ALW
+VCCIO_OUT
+3.3V_ALW_U51
+RTC_CELL
+3.3V_ALW_U51
+3.3V_ALW +3.3V_ALW_U51
+3.3V_ALW2
+1.05V_RUN
+3.3V_RUN
+3.3V_ALW
+3.3V_RUN
+3.3V_ALW
POWER_SW#_MB <41,49>
DOCK_PWR_BTN# <48>
H_PROCHOT# <61,62,7>
H_THERMTRIP#<23,7>
EC5048_TX <50>
RUN_ON <44,54>
FAN2_PWM<27>
FAN2_TACH_FB<27>
AC_DIS <55,63>
I_ADP <62>
SIO_SLP_S5#<19,32,41>
BC_INT#_ECE1117<53>
BC_CLK_ECE1117<53>
DOCK_POR_RST#<48>
FAN1_PWM<27>
EN_INVPWR <30>
SIO_RCIN#<23>
IRQ_SERIRQ<21,50>
CLK_PCI_MEC<20>
DOCK_LCD_SMBDAT <30,48>
DOCK_LCD_SMBCLK <30,48>
LPC_LAD1<21,50>
LPC_LAD2<21,50>
LPC_LAD3<21,50>
LPC_LAD0<21,50>
CLKRUN#<19,50>
SIO_EXT_SCI#<23>
PCH_ALW_ON <39>
SIO_SLP_S3# <19,32,41,54>
PCH_DPWROK <19>
CLK_TP_SIO<53>
DAT_TP_SIO<53>
CLK_KBD<48>
CLK_MSE<48>
A_ON <54,58>
BC_INT#_ECE5048<50>
BC_CLK_ECE5048<50>
PCH_PCIE_WAKE# <19>
CHARGER_SMBCLK <62>
CHARGER_SMBDAT <62>
PECI_EC <7>
PBAT_PRES# <55,62>
SML1_SMBDATA<21>
SML1_SMBCLK<21>
USH_SMBDAT <41>
USH_SMBCLK <41>
AC_PRESENT <19>
BAT2_LED# <52>
PBAT_SMBDAT<55>
PBAT_SMBCLK<55>
SIO_EXT_SMI#<18,22>
ACAV_IN <17,62,63>
ENVDD_PCH <19,30>
ME_SUS_PWR_ACK <19>
PM_APWROK <19>
BAT1_LED# <52>
BEEP<49>
EC_32KHZ_ECE5048 <50>
ACAV_IN_NB<62,63>
BC_DAT_ECE1117<53>
FAN1_TACH_FB<27>
SIO_SLP_S4# <19,41,54,57>
SIO_SLP_LAN# <19,39>
USB_PWR_SHR_EN# <47>
RESET_OUT# <11,18,19,7>
DAT_KBD<48>
DAT_MSE<48>
BC_DAT_ECE5048<50>
ME_FWP_EC <18>
GPU_SMBDAT <17>
GPU_SMBCLK <17>
SIO_SLP_SUS# <19>
BREATH_LED# <48,52>
SIO_PWRBTN# <19>
I_BATT <62>
SUSACK# <19>
SSD_SATA5_PCIE2# <18,23>
PS_ID<55>
BIA_PWM_EC<30>
PCH_PLTRST#_EC<19,41,42,43,50>
LPC_LFRAME#<21,50>
RUNPWROK <50,7>
SIO_SLP_A# <19,41,54,58>
PCH_RSMRST# <53>
SIO_EXT_WAKE# <18,23>
ALWON <56>
LAN_WAKE# <23,39>
CLK_PCI_LPDEBUG <20>
1.05V_0.8V_PWROK <61>
1.5V_RUN_PWRGD<59>
RUN_ON_ENABLE#<54,7>
IMVP_VR_ON <61>
DGPU_THERMTRIP# <17>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
KBC (MEC5085)
51 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
KBC (MEC5085)
51 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
KBC (MEC5085)
51 67Monday, January 13, 2014
Compal Electronics, Inc.
R817 100K_0402_5%R817 100K_0402_5%
1 2
R847
10K_0402_5%
R847
10K_0402_5%
12
E
B
C
Q16
MMBT3904WT1G_SC70-3
E
B
C
Q16
MMBT3904WT1G_SC70-3
2
3 1
R861
10K_0402_5%
R861
10K_0402_5%
12
R870100K_0402_5% R870100K_0402_5%
12
C1352
1U_0402_6.3V6K
C1352
1U_0402_6.3V6K
1
2
PJP65
PAD-OPEN1x1m
PJP@
PJP65
PAD-OPEN1x1m
PJP@
1 2
R829 2.2K_0402_5%R829 2.2K_0402_5%
1 2
T155PAD~D @T155PAD~D @
C734
1U_0402_6.3V6K
C734
1U_0402_6.3V6K
1
2
C1343 2200P_0402_50V7KC1343 2200P_0402_50V7K
1 2
U50
NL17SZ08DFT2G_SC70
U50
NL17SZ08DFT2G_SC70
B
1
A
2
G
3
O4
P5
R858
10K_0402_5%
R858
10K_0402_5%
12
R864
49.9_0402_1%
R864
49.9_0402_1%
12
R834 0_0402_5%@R834 0_0402_5%@
1 2
R869 10K_0402_5%R869 10K_0402_5%
1 2
E
B
C
Q17
MMBT3904WT1G_SC70-3
E
B
C
Q17
MMBT3904WT1G_SC70-3
2
31
Y6
32.768KHZ_12.5PF_Q13FC1350000
Y6
32.768KHZ_12.5PF_Q13FC1350000
1 2
C1353
0.1U_0402_25V6K
C1353
0.1U_0402_25V6K
1
2
C720
0.1U_0402_25V6K
C720
0.1U_0402_25V6K
1 2
C320
0.1U_0402_25V6K
C320
0.1U_0402_25V6K
1
2
RP5
2.2K_8P4R_5%
RP5
2.2K_8P4R_5%
1 8
2 7
3 6
4 5
C273
100P_0402_50V8J
@C273
100P_0402_50V8J
@
1
2
C782
10U_0603_6.3V6M
C782
10U_0603_6.3V6M
1
2
E
B
C
Q14
MMBT3904WT1G_SC70-3
E
B
C
Q14
MMBT3904WT1G_SC70-3
2
3 1
C1350 2200P_0402_50V7KC1350 2200P_0402_50V7K
1 2
E
B
C
Q15
MMBT3904WT1G_SC70-3
E
B
C
Q15
MMBT3904WT1G_SC70-3
2
3 1
R425
1.33K_0402_1%
R425
1.33K_0402_1%
12
C292 47P_0402_50V8J@C292 47P_0402_50V8J@
1 2
R952 43_0402_5%R952 43_0402_5%
1 2
R836
100_0402_1%
@
R836
100_0402_1%
@
12
R872
10K_0402_5%
R872
10K_0402_5%
12
R1180@0_0402_5%R1180@0_0402_5%
1 2
C757
1U_0402_6.3V4Z
C757
1U_0402_6.3V4Z
1
2
R850
100K_0402_5%
@R850
100K_0402_5%
@
12
C339
100P_0402_50V8J
@C339
100P_0402_50V8J
@
1
2
R860
10K_0402_5%
R860
10K_0402_5%
12
C735
1U_0402_6.3V6K
C735
1U_0402_6.3V6K
1
2
C740
0.1U_0402_25V6K
C740
0.1U_0402_25V6K
1
2
R848
10K_0402_5%
R848
10K_0402_5%
12
C733
1U_0402_6.3V6K
@C733
1U_0402_6.3V6K
@
1 2
C739
0.1U_0402_25V6K
C739
0.1U_0402_25V6K
1
2
R810
100K_0402_5%
R810
100K_0402_5%
12
R3730 100K_0402_5%R3730 100K_0402_5%
1 2
C340
100P_0402_50V8J
@C340
100P_0402_50V8J
@
1
2
R1981
100K_0402_5%
R1981
100K_0402_5%
12
R825 10K_0402_5%R825 10K_0402_5%
1 2
R866 0_0402_5%@R866 0_0402_5%@
1 2
JLPDE1
ACES_50506-01041-P01
CONN@
JLPDE1
ACES_50506-01041-P01
CONN@
44
33
22
11
66
55
GND1 11
GND2 12
77
88
99
10 10
C1355
0.1U_0402_25V6K
C1355
0.1U_0402_25V6K
1
2
R799
10K_0402_5%
R799
10K_0402_5%
12
C736
0.1U_0402_25V6K
C736
0.1U_0402_25V6K
1
2
R849
10K_0402_5%
R849
10K_0402_5%
12
U51
MEC5085-LZY_DQFN132_11X11
U51
MEC5085-LZY_DQFN132_11X11
GPIO007/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA
A5
GPIO010/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK/GANG_DATA0
B6
GPIO011/nSMI
A6
GPIO030/GPTP-IN2/BCM_E_INT#/GANG_DATA7
B19 GPIO031/GPTP-OUT2/BCM_E_DAT
A18 GPIO032/BCM_E_CLK
B20
GPIO045/LSBCM_D_INT#
A19 GPIO046/LSBCM_D_DAT/GANG_STROBE
B21 GPIO047/LSBCM_D_CLK
A20
GPIO061/LPCPD#
A27
GPIO024/THSEL_STRAP B29
SER_IRQ
A28
LRESET#
B30
GPIO100/NEC_SCI
A33
GPIO110/PS2_CLK2/GPTP-IN6
A37
GPIO111/PS2_DAT2/GPTP-OUT6
B40
BGP0 B62
XTAL1
A61
XTAL2
A62
GPIO112/PS2_CLK1A
A38
GPIO113/PS2_DAT1A
B41
GPIO114/PS2_CLK0A
A39
GPIO115/PS2_DAT0A
B42
GPIO154/I2C1C_DATA/PS2_CLK1B/GANG_DATA5
B59
GPIO155/I2C1C_CLK/PS2_DAT1B/GANG_DATA6
A56
GPIO145/I2C1K_DATA/JTAG_TDI
A51
GPIO146/I2C1K_CLK/JTAG_TDO
B55
GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK
B56
GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS
A53
GPIO156/LED1/GANG_DATA1 B57
GPIO050/FAN_TACH1/GTACH0/GANG_START
B22
GPIO051/FAN_TACH2/GANG _MODE
A21
GPIO052/FAN_TACH3/GTACH1/GANG_ERROR
B23
GPIO053/PWM0
B24
GPIO054/PWM1/GPWM1
A23
GPIO055/PWM2
B25
GPIO056/PWM3/GPWM0
A24
GPIO121/BCM_A_INT#
A42 GPIO122/BCM_A_DAT
B45 GPIO123/BCM_A_CLK
A43
PCI_CLK
A29
LFRAME#
B31
LAD0
A30
LAD1
B32
LAD2
A31
LAD3
B33
CLKRUN#
A32
GPIO001/ECSPI_CS1/32KHZ_OUT B2
GPIO015/GPTP-OUT7 A8
GPIO016/GPTP-IN8 B9
GPIO017/GPTP-OUT8 A9
GPIO020/RC_ID2 B10
GPIO021/RC_ID1 A10
VCC_PWRGD B26
GPIO060/KBRST/BCM_B_INT# A25
GPIO101/ECGP_SCLK B36
GPIO102/BCM_C_INT# A34
GPIO103/ECGP_MISO B37
GPIO104/SLP_S0# A35
GPIO105/ECGP_MOSI B38
GPIO106 A36
GPIO107/NRESET_OUT B39
GPIO116/MSDATA/V2P_COUT_LO/TAP_SEL_STRAP A40
GPIO117/MSCLK/V2P_COUT_HI B43
GPIO120/UART_TX/V2P_COUT_HI1 B44
GPIO124/GPTP-OUT5/UART_RX/V2P_COUT_LO1 B46
GPIO125/GPTP-IN5/PECI_REQUEST#/GANG_BUSY A44
JTAG_RST#
B47
GPIO127/A20M A45
PROCHOT_IN#/PROCHOT_IO# A46
GPIO151/GPTP-IN4/GANG_DATA2 A54
GPIO152/GPTP-OUT4 B58
GPIO153/LED2/GANG_DATA4 A55
V_ISYS1 A57
nFWP B65
VBAT
B64
H_VTR
A22
PECI_DAT A48
VREF_PECI B51
VCI_OVRD_IN A64
VCI_IN3# B68
GPIO003/I2C1A_DATA A3
GPIO004/I2C1A_CLK B4
GPIO005/I2C1B_DATA/BCM_B_DAT A4
GPIO006/I2C1B_CLK/BCM_B_CLK B5
GPIO012/I2C1H_DATA/I2C2D_DATA B7
GPIO013/I2C1H_CLK/I2C2D_CLK/GANG_DATA3 A7
GPIO130/I2C2A_DATA/BCM_C_DAT B48
GPIO131/I2C2A_CLK/BCM_C_CLK B49
GPIO132/I2C1G_DATA A47
GPIO140/I2C1G_CLK B50
GPIO141/I2C1F_DATA/I2C2B_DATA B52
GPIO142/I2C1F_CLK/I2C2B_CLK A49
GPIO143/I2C1E_DATA B53
GPIO144/I2C1E_CLK A50
SYSPWR_PRES A59
VCI_IN2# B63
VCI_OUT A60
VCI_IN1# A63
VCI_IN0# B67
VTR_ADC
A58
GPIO157/LED0 B1
GPIO027/GPTP-OUT1 A1
DN1_DP1A/THERM B13
DP1_DN1A/VREF_T A13
VSET A17
DN2_DP2A B14
DP2_DN2A A14
VIN B15
DN3_DP3A A15
DP3_DN3A B16
VCP A12
DN4_DP4A A16
DP4_DN4A B17
THERMTRIP2# B34
GPIO002/THERMTRIP3# A2
VTR
B3
VTR
A11
VTR
A26
VTR
B35
VTR
A41
VTR
A52
AGND
B66
VSS
B11
VSS_ADC
B60
VR_CAP
B12
VSS_RO
B54
H_VSS
B18
EP
C1
GPIO026/GPTP-IN1 B28
GPIO025/UART_CLK B27
V_ISYS0 B61
GPIO014/GPTP-IN7/RC_ID3 B8
JDEG2
ACES_50506-01041-P01
CONN@
JDEG2
ACES_50506-01041-P01
CONN@
44
33
22
11
66
55
GND1 11
GND2 12
77
88
99
10 10
E
B
C
Q27
MMBT3904WT1G_SC70-3
E
B
C
Q27
MMBT3904WT1G_SC70-3
2
3 1
C1349
1U_0402_6.3V4Z
C1349
1U_0402_6.3V4Z
1
2
G
D
S
Q45
DMN65D8LW-7_SOT323-3
G
D
S
Q45
DMN65D8LW-7_SOT323-3
2
13
R808 100K_0402_5%R808 100K_0402_5%
1 2
C272
100P_0402_50V8J
@C272
100P_0402_50V8J
@
1
2
C777
0.1U_0402_25V6K
C777
0.1U_0402_25V6K
1
2
R843 8.2K_0402_5%@R843 8.2K_0402_5%@
1 2
R822 2.2K_0402_5%R822 2.2K_0402_5%
1 2
RP7
100K_0804_8P4R_5%
RP7
100K_0804_8P4R_5%
1 8
2 7
3 6
4 5
R879
10K_0402_5%
@R879
10K_0402_5%
@
1 2
R7970_0402_5% @R7970_0402_5% @
12
E
B
C
Q28
PMST3904_SOT323-3
E
B
C
Q28
PMST3904_SOT323-3
2
3 1
R1069 1K_0402_5%R1069 1K_0402_5%
1 2
C737
0.1U_0402_25V6K
C737
0.1U_0402_25V6K
1
2
R134 4.7K_0402_5%R134 4.7K_0402_5%
12
JTAG1
@SHORT PADS~D
CONN@JTAG1
@SHORT PADS~D
CONN@
11
2
2
C1348
0.1U_0402_25V6K
C1348
0.1U_0402_25V6K
1
2
R1068 0_0402_5%@R1068 0_0402_5%@
12
C288
100P_0402_50V8J
@C288
100P_0402_50V8J
@
1
2
R845 0_0402_5%@R845 0_0402_5%@
1 2
R8020_0402_5% @R8020_0402_5% @
12
R399
2.2K_0402_5%
R399
2.2K_0402_5%
1 2
C744
4700P_0402_25V7K
C744
4700P_0402_25V7K
1
2
R859
10K_0402_5%
R859
10K_0402_5%
12
R83510K_0402_5% R83510K_0402_5%
12
C1354
1U_0402_6.3V6K
@C1354
1U_0402_6.3V6K
@
1 2
R880100K_0402_5% R880100K_0402_5%
12
R432 47K_0402_5%R432 47K_0402_5%
1 2
R8412.2K_0402_5% R8412.2K_0402_5%
12
C780
0.1U_0402_25V6K
C780
0.1U_0402_25V6K
1
2
R875
240K_0402_5%~D
R875
240K_0402_5%~D
12
C327
0.1U_0402_25V6K
C327
0.1U_0402_25V6K
1
2
R818 100K_0402_5%R818 100K_0402_5%
1 2
R8382.2K_0402_5% R8382.2K_0402_5%
12
R876
100K_0402_5%
R876
100K_0402_5%
12
C781
0.1U_0402_25V6K
C781
0.1U_0402_25V6K
1
2
C743
22P_0402_50V8J
C743
22P_0402_50V8J
1
2
C747
4.7P_0402_50V8C
@C747
4.7P_0402_50V8C
@
1
2
R396
8.2K_0402_5%
R396
8.2K_0402_5%
12
R819
100K_0402_5%
R819
100K_0402_5%
12
E
B
C
Q26
MMBT3904WT1G_SC70-3
E
B
C
Q26
MMBT3904WT1G_SC70-3
2
31
C741
22P_0402_50V8J
C741
22P_0402_50V8J
1
2
C1346 2200P_0402_50V7KC1346 2200P_0402_50V7K
1 2
C779
4.7U_0603_6.3V6K
C779
4.7U_0603_6.3V6K
1
2
R892 10K_0402_5%R892 10K_0402_5%
1 2
R885
10_0402_1%
@R885
10_0402_1%
@
12
C291
100P_0402_50V8J
@C291
100P_0402_50V8J
@
1
2
C1345
0.1U_0402_25V6K
C1345
0.1U_0402_25V6K
1
2
RP6
4.7K_0804_8P4R_5%
RP6
4.7K_0804_8P4R_5%
1 8
2 7
3 6
4 5
C1351 2200P_0402_50V7KC1351 2200P_0402_50V7K
1 2
R811 10K_0402_5%R811 10K_0402_5%
1 2
R874 1K_0402_5%R874 1K_0402_5%
1 2
R814 100K_0402_5%R814 100K_0402_5%
1 2
R1985 0_0402_5%@R1985 0_0402_5%@
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
Fiducial Mark
SYS_LED_MASK# LID_CL#
Mask All LEDs (Sniffer Function)
Mask Base MB LEDs (Lid Closed)
0
1 0
X
LED Circuit Control Table
Do not Mask LEDs (Lid Opened) 11
WWAN/WLAN LED
HDD LED
Breath LED
BREATH_LED side view.
BREATH_LED TOP view.
Difference with Diesel
CIS link OK
Difference with Diesel
BATT LED
MASK_BASE_LEDS#
SYS_LED_MASK#
WLAN_LED
SYS_LED_MASK#
BREATH_LED#_Q
BREATH_WHITE_LED
LID_CL#
SATA_SIDE_LED
WLAN_LED
BATT_YELLOW_LED
BREATH_LED#_Q
BATT_WHITE_LED
BATT_YELLOW_LED
BATT_WHITE_LEDBAT2_LED#
BAT1_LED#
SYS_LED_MASK#
SATA_SIDE_LED
MASK_BASE_LEDS#
+3.3V_ALW
+3.3V_ALW
+3.3V_ALW
+5V_ALW
+5V_ALW
+5V_ALW
SYS_LED_MASK#<39,50>
LID_CL#<49,50>
LED_SATA_DIAG_OUT#<50>
BREATH_LED#<48,51>
WIRELESS_LED#<42,50>
BREATH_WHITE_LED <49>
BAT2_LED#<51>
BAT1_LED#<51>
SATA_ACT#<18>
MASK_SATA_LED#<50>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
LED / Screw hole
52 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
LED / Screw hole
52 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
LED / Screw hole
52 67Monday, January 13, 2014
Compal Electronics, Inc.
H2
H_3P8
@H2
H_3P8
@
1
H7
H_3P8
@H7
H_3P8
@
1
G
D
S
Q359
DMN65D8LW -7_SOT323-3
G
D
S
Q359
DMN65D8LW -7_SOT323-3
2
13
H5
H_3P0
@H5
H_3P0
@
1
R939 1.2K_0402_1%R939 1.2K_0402_1%
1 2
C6
0.1U_0402_16V4Z
C6
0.1U_0402_16V4Z
1
2
H1
H_3P0
@H1
H_3P0
@
1
H6
H_3P0
@H6
H_3P0
@
1
H9
H_3P8
@H9
H_3P8
@
1
H16
H_3P0
@H16
H_3P0
@
1
H8
H_3P8
@H8
H_3P8
@
1
H3
H_3P0
@H3
H_3P0
@
1
H27
H_1P2
@H27
H_1P2
@
1
H11
H_3P0
@H11
H_3P0
@
1
H26
H_1P2
@H26
H_1P2
@
1
C778
0.1U_0402_25V6K
@C778
0.1U_0402_25V6K
@
1 2
R943 150_0402_5%R943 150_0402_5%
1 2
H4
H_3P0
@H4
H_3P0
@
1
H12
H_3P8
@H12
H_3P8
@
1
FD1
FIDUCIAL MARK~D
@FD1
FIDUCIAL MARK~D
@
1
FD3
FIDUCIAL MARK~D
@FD3
FIDUCIAL MARK~D
@
1
FD4
FIDUCIAL MARK~D
@FD4
FIDUCIAL MARK~D
@
1
H17
H_3P6
@H17
H_3P6
@
1
Q74B
DMN66D0LDW -7_SOT363-6
Q74B
DMN66D0LDW -7_SOT363-6
3
5
4
FD2
FIDUCIAL MARK~D
@FD2
FIDUCIAL MARK~D
@
1
H18
H_3P0
@H18
H_3P0
@
1
D59
RB751S40T1_SOD523-2
D59
RB751S40T1_SOD523-2
21
H15
H_3P0
@H15
H_3P0
@
1
R131 150_0402_1%R131 150_0402_1%
1 2
R955 220_0402_5%R955 220_0402_5%
1 2
R956 100_0402_5%R956 100_0402_5%
1 2
Q86
PDTA114EU_SC70-3
Q86
PDTA114EU_SC70-3
2
1 3
Q74A
DMN66D0LDW -7_SOT363-6
Q74A
DMN66D0LDW -7_SOT363-6
61
2
H10
H_3P0
@H10
H_3P0
@
1
R932
10K_0402_5%
R932
10K_0402_5%
12
H24
H_3P6
@H24
H_3P6
@
1
H19
H_3P6
@H19
H_3P6
@
1
H21
H_3P0
@H21
H_3P0
@
1
G
D
S
Q78
DMN65D8LW -7_SOT323-3
G
D
S
Q78
DMN65D8LW -7_SOT323-3
2
13
D62
RB751S40T1_SOD523-2
D62
RB751S40T1_SOD523-2
21
U58
TC7SH08FU_SSOP5~D
U58
TC7SH08FU_SSOP5~D
B
1
A
2
G
3
O4
P5
H13
H_3P8
@H13
H_3P8
@
1
H14
H_3P0
@H14
H_3P0
@
1
Q79
PDTA114EU_SC70-3
Q79
PDTA114EU_SC70-3
2
1 3
H22
H_3P6X3P0
@H22
H_3P6X3P0
@
1
H28
H_3P0
@H28
H_3P0
@
1
H25
H_3P0
@H25
H_3P0
@
1
R937
100K_0402_5%
R937
100K_0402_5%
12
R130 475_0402_1%R130 475_0402_1%
1 2
JLED1
ACES_51522-01001-001
CONN@
JLED1
ACES_51522-01001-001
CONN@
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10 GND 11
GND 12
H20
H_3P0
@H20
H_3P0
@
1
H23
H_3P6
@H23
H_3P6
@
1
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
RSMRST#
Place close to JKBTP1
Keyboard
EMI depop location
Touch Pad
CIS link OK
Remove RSMRST cost down circuit.
RSMRST#
CLK_TP_SIO CLK_TP_SIO
DAT_TP_SIO
DAT_TP_SIO
+3.3V_ALW
+3.3V_ALW
+3.3V_ALW_PCH +3.3V_ALW_PCH
+5V_ALW
+5V_RUN+3.3V_ALW+3.3V_TP
+3.3V_TP
+3.3V_TP
+5V_RUN
+3.3V_ALW
+3.3V_RUN +3.3V_TP
PCH_RSMRST#<51>
PCH_RSMRST#_Q <18,19>
DAT_TP_SIO<51>
BC_CLK_ECE1117<51>
BC_INT#_ECE1117<51>
BC_DAT_ECE1117<51>
KB_DET#<23>
CLK_TP_SIO<51>
ALW_PWRGD_3V_5V<56>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
KB / TP / RSMRST#
53 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
KB / TP / RSMRST#
53 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
KB / TP / RSMRST#
53 67Monday, January 13, 2014
Compal Electronics, Inc.
U18
RT9818A-44GU3_SC70-3~D
@U18
RT9818A-44GU3_SC70-3~D
@
VCC
1
GND
2RESET# 3
RZ52 0_0402_5%
RZ52 0_0402_5%
1 2
C289
0.1U_0402_25V6K
@C289
0.1U_0402_25V6K
@
1 2
C1410@
0.1U_0402_25V6
C1410@
0.1U_0402_25V6
12
PJP16
PAD-OPEN1x1m
PJP@
PJP16
PAD-OPEN1x1m
PJP@
1 2
C1411@
0.1U_0402_25V6
C1411@
0.1U_0402_25V6
12
CZ31@EMC@
10P_0402_50V8J
CZ31@EMC@
10P_0402_50V8J
12
R1622
10K_0402_5%
@R1622
10K_0402_5%
@
1 2
C290
0.01U_0402_16V7K
@C290
0.01U_0402_16V7K
@
1
2
CZ30@EMC@
10P_0402_50V8J
CZ30@EMC@
10P_0402_50V8J
12
JKBTP1
ACES_50554-01601-001
CONN@
JKBTP1
ACES_50554-01601-001
CONN@
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
G17
G18
G19
G20
RZ18
4.7K_0402_5%
RZ18
4.7K_0402_5%
12
R1624
8.2K_0402_5%
@
R1624
8.2K_0402_5%
@
1 2
R1623 0_0402_5%@R1623 0_0402_5%@
1 2
RZ19
4.7K_0402_5%
RZ19
4.7K_0402_5%
12
R1633
10K_0402_5%
@R1633
10K_0402_5%
@
1 2
U12
NL17SZ08DFT2G_SC70
U12
NL17SZ08DFT2G_SC70
B
1
A
2
G
3
O4
P5
R1630
33_0402_5%
@R1630
33_0402_5%
@
12
C1414@
0.1U_0402_25V6
C1414@
0.1U_0402_25V6
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
MXM_PWR_SRC Source
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
+1.05V_RUN Source
+3.3V_ALW to +3.3V_MXM
+3.3V_M Source
+3.3V_SUS Source
Remove USH_PWR_ON
SUS_ON
Combine +3.3V_SSD and +5V_MXM
into M.2 card power control page
Combine +3.3V_WLAN and +3.3V_RUN
into M.2 card power control page.
Combine +3.3V_LAN and +3.3V_ALW_PCH
into LAN page
+5V_RUN Source
+5VMOD Source
Remove +PWR_SRC_S PU
3.3V_RUN_GFX_ON
+MXM_SRC_EN#
3.3V_RUN_GFX_ON
RUN_ON_ENABLE#
+1.05V_RUN_ENABLE
RUN_ON_ENABLE#
+1.05V_RUN_CHG
A_ON_R
SIO_SLP_S4#_R
+3.3V_M_PWR
+5V_RUN_PWR
+5V_MOD_PWR
RUN_ON_R
MODC_EN
+PWR_SRC_MXM
+PWR_SRC_MXM +MXM_PWR_SRC+MXM_PWR
+3.3V_ALW2
+1.05V_M +1.05V_RUN
+1.05V_RUN
+3.3V_ALW
+5V_ALW
+3.3V_ALW
+3.3V_M+3.3V_M_PWR
+3.3V_SUS+3.3V_SUS_PWR
+PWR_SRC
+3.3V_ALW
+3.3V_MXM_PWR +3.3V_MXM
+5V_ALW
+5V_RUN+5V_RUN_PWR
+5V_MOD+5V_MOD_PWR
+5V_ALW
+5V_ALW
+5V_ALW
3.3V_RUN_GFX_ON<20,44,50>
RUN_ON_ENABLE#<51,7>
RUN_ON<44,51,54>
SIO_SLP_S3#<19,32,41,51>
SIO_SLP_A#<19,41,51,58>
SIO_SLP_S4#<19,41,51,57>
A_ON<51,58>
RUN_ON<44,51,54>
MODC_EN<46,50>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Power Control
54 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Power Control
54 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Power Control
54 67Monday, January 13, 2014
Compal Electronics, Inc.
R3732 0_0402_5%R3732 0_0402_5%
1 2
Q304A
DMN66D0LDW-7_SOT363-6
Q304A
DMN66D0LDW-7_SOT363-6
61
2
C477
470P_0402_50V7K
C477
470P_0402_50V7K
1
2
C539
470P_0402_50V7K
C539
470P_0402_50V7K
1
2
R514
100K_0402_5%
R514
100K_0402_5%
12
C513
10U_0603_6.3V6M
C513
10U_0603_6.3V6M
1
2
U37
TPS22966DPUR_SON14_2X3~D
U37
TPS22966DPUR_SON14_2X3~D
GND 11
VIN2
6
VBIAS
4
ON2
5
VOUT2 9
VIN2
7
CT1 12
VOUT1 14
VOUT2 8
VOUT1 13
VIN1
2
ON1
3
VIN1
1
CT2 10
GPAD 15
PJP105
JUMP_43X79
@PJP105
JUMP_43X79
@
11
2
2
R940
100K_0402_5%
R940
100K_0402_5%
12
R762 0_0402_5%@R762 0_0402_5%@
1 2
G
D
S
Q70
DMN65D8LW-7_SOT323-3
@
G
D
S
Q70
DMN65D8LW-7_SOT323-3
@
2
13
R909
100K_0402_5%
R909
100K_0402_5%
12
R878 0_0402_5%@R878 0_0402_5%@
1 2
G
D
S
Q87
DMN65D8LW-7_SOT323-3
G
D
S
Q87
DMN65D8LW-7_SOT323-3
2
13
R925
39_0402_5%
@R925
39_0402_5%
@
12
R301
100K_0402_5%
R301
100K_0402_5%
12
PJP90
JUMP_43X79
@PJP90
JUMP_43X79
@
11
2
2
R781 0_0402_5%@R781 0_0402_5%@
1 2
C544
470P_0402_50V7K
C544
470P_0402_50V7K
1
2
C400
10U_0603_6.3V6M
C400
10U_0603_6.3V6M
1
2
R931
20K_0402_5%
R931
20K_0402_5%
12
R933
330K_0402_5%
R933
330K_0402_5%
12
C774
0.01U_0402_50V7K
C774
0.01U_0402_50V7K
1
2
C362
0.1U_0603_25V7K
@
C362
0.1U_0603_25V7K
@
1
2
C773
100P_0402_50V8J
C773
100P_0402_50V8J
1
2
U40
TPS22966DPUR_SON14_2X3~D
U40
TPS22966DPUR_SON14_2X3~D
GND 11
VIN2
6
VBIAS
4
ON2
5
VOUT2 9
VIN2
7
CT1 12
VOUT1 14
VOUT2 8
VOUT1 13
VIN1
2
ON1
3
VIN1
1
CT2 10
GPAD 15
PJP78
PAD-OPEN 4x4m
@PJP78
PAD-OPEN 4x4m
@
1 2
C767
10U_0603_6.3V6M
C767
10U_0603_6.3V6M
1
2
R935
100K_0402_5%
R935
100K_0402_5%
12
PJP94
JUMP_43X79
@PJP94
JUMP_43X79
@
11
2
2
PJP92
JUMP_43X79
@PJP92
JUMP_43X79
@
11
2
2
R944
20K_0402_5%
R944
20K_0402_5%
12
Q63
MDS1521URH_SO8
Q63
MDS1521URH_SO8
3
2
1
4
5
6
7
8
C514
10U_0805_10V4Z
C514
10U_0805_10V4Z
1
2
R881 0_0402_5%@R881 0_0402_5%@
1 2
PJP82
PAD-OPEN 4x4m
PJP@
PJP82
PAD-OPEN 4x4m
PJP@
12
R877 0_0402_5%@R877 0_0402_5%@
1 2
C772
10U_0603_6.3V6M
C772
10U_0603_6.3V6M
1
2
PJP79
PAD-OPEN 4x4m
@PJP79
PAD-OPEN 4x4m
@
1 2
C475
10U_0603_6.3V6M
C475
10U_0603_6.3V6M
1
2
C543
470P_0402_50V7K
C543
470P_0402_50V7K
1
2
U34
TPS22965DSGR_SON8_2X2~D
U34
TPS22965DSGR_SON8_2X2~D
VIN
1
VIN
2
ON
3
VBIAS
4
VOUT 7
VOUT 8
CT
6GND 5
GND 9
Q304B
DMN66D0LDW-7_SOT363-6
Q304B
DMN66D0LDW-7_SOT363-6
3
5
4
C476
470P_0402_50V7K
C476
470P_0402_50V7K
1
2
C776
10U_1206_25V6M
C776
10U_1206_25V6M
1
2
R1611
1M_0402_5%
R1611
1M_0402_5%
12
Q186
SI4835DDY-T1-E3_SO8
Q186
SI4835DDY-T1-E3_SO8
3 6
5
7
8
2
4
1
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DELL CONFIDENTIAL/PROPRIETARY
Primary Battery Connector
DC_IN+ Source
COIN RTC Battery
Move to power schematic
ESD Diodes
ESD (47.2)
EMI Part (47.1)
EMI Part (47.1)
EMI Part (47.1)
EMI Part (47.1)
EMI Part (47.1)
NB_PSID_TS5A63157
PBATT+_C
NB_PSID
+DCIN_JACK
Z4012
+DC_IN
Z4304
Z4305
Z4306
+3.3V_ALW
+5V_ALW
+DC_IN_SS
PBATT+
GND
+3.3V_ALW
+DC_IN
+5V_ALW
+COINCELL
+RTC_CELL
+3.3V_RTC_LDO
+COINCELL
+PWR_SRC
+PWR_SRC_MXM
DOCK_SMB_ALERT# <48,50>
SLICE_BAT_PRES#<48,50,63>
PSID_DISABLE# <50>
PBAT_PRES# <51,62>
PBAT_SMBDAT <51>
PBAT_SMBCLK <51>
DOCK_PSID<48> GPIO_PSID_SELECT <50>
PS_ID <51>
SOFT_START_GC <63>
AC_DIS <51,63>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
+DCIN
55 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
+DCIN
55 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
+DCIN
55 67Monday, January 13, 2014
Compal Electronics, Inc.
PL4
FBC-78-302585-L-T
EMC@ PL4
FBC-78-302585-L-T
EMC@
1 2
PQ5SI7149DP PQ5SI7149DP
3
2
4
1
5
PD2
TVNST52302AB0_SOT523-3
EMC@
PD2
TVNST52302AB0_SOT523-3
EMC@
2
3
1
PL3
BLM15BX102SN1D_2P
EMC@ PL3
BLM15BX102SN1D_2P
EMC@
12
PR2
100K_0402_5%
PR2
100K_0402_5%
12
PC9 0.022U_0603_50V7KPC9 0.022U_0603_50V7K
1 2
PC11
1000P_0402_50V7K
EMC@ PC11
1000P_0402_50V7K
EMC@
12
PC15
0.1U_0603_25V7K
@EMC@ PC15
0.1U_0603_25V7K
@EMC@
12
PC14
10U_0805_25V6K
PC14
10U_0805_25V6K
12
PQ8B
IMD2AT-108_SC74-6~D
PQ8B
IMD2AT-108_SC74-6~D
2
4 3
G
D
S
PQ2
FDV301N_G_NL_SOT23-3~D
G
D
S
PQ2
FDV301N_G_NL_SOT23-3~D
2
1 3
PR3
100_0804_8P4R_5%
PR3
100_0804_8P4R_5%
1 8
2 7
3 6
4 5
PR8
2.2K_0402_5%
PR8
2.2K_0402_5%
1 2
PD8
VZ0603M260APT_0603
@
PD8
VZ0603M260APT_0603
@
1
2
PR16
1M_0402_5%
PR16
1M_0402_5%
12
PQ8A
IMD2AT-108_SC74-6~D
PQ8A
IMD2AT-108_SC74-6~D
5
16
PR18
100K_0402_5%
PR18
100K_0402_5%
12
PJPDC1
ACES_50493-0110N-001
CONN@
PJPDC1
ACES_50493-0110N-001
CONN@
11
33
44
22
55
66
77
88
99
10 10
11 11
E
B
C
PQ3
MMST3904-7-F_SOT323-3
E
B
C
PQ3
MMST3904-7-F_SOT323-3
2
3 1
PD5
SDMK0340L-7-F_SOD323-2
PD5
SDMK0340L-7-F_SOD323-2
1 2
PL1
FBC-78-302585-L-T
EMC@ PL1
FBC-78-302585-L-T
EMC@
1 2
PR9
33_0402_5%
PR9
33_0402_5%
1 2
PR7
0_0402_5%
@PR7
0_0402_5%
@
1 2
PR11
10K_0402_1%
PR11
10K_0402_1%
12
PR19
4.7K_0805_5%
@PR19
4.7K_0805_5%
@
12
PD3
TVNST52302AB0_SOT523-3
EMC@
PD3
TVNST52302AB0_SOT523-3
EMC@
2
3
1
PL6
FBMJ4516HS720NT_2P
EMC@ PL6
FBMJ4516HS720NT_2P
EMC@
1 2
PR33
0_0402_5%
PR33
0_0402_5%
1 2
PC4
2200P_0402_50V7K
EMC@ PC4
2200P_0402_50V7K
EMC@
12
PL2
FBMJ4516HS720NT_2P
EMC@ PL2
FBMJ4516HS720NT_2P
EMC@
1 2
PD1
BAS40CW_SOT323-3
PD1
BAS40CW_SOT323-3
2
3
1
G
D
S
PQ1
NTR4502PT1G_SOT23-3
G
D
S
PQ1
NTR4502PT1G_SOT23-3
2
1 3
PC30
10U_0805_25V6K
@
PC30
10U_0805_25V6K
@
12
PR1
1K_0402_5%
PR1
1K_0402_5%
12
+
PC1
100U_25V_M
+
PC1
100U_25V_M
1
2
PBATT1
SUYIN_200045GR009M28QZR
CONN@
PBATT1
SUYIN_200045GR009M28QZR
CONN@
19
37
46
55
64
82
91
28
73
GND 10
GND 11
JRTC1
ACES_50271-0020N-001
JRTC1
ACES_50271-0020N-001
1
1
2
2
GND
3
GND
4
PC5
1500P_0402_50V7K
PC5
1500P_0402_50V7K
12
PR20
10K_0402_5%
PR20
10K_0402_5%
1 2
PR12
15K_0402_1%
PR12
15K_0402_1%
1 2
PR22
1M_0402_5%
PR22
1M_0402_5%
12
PC2
1U_0603_10V4Z
PC2
1U_0603_10V4Z
1
2
PR10
100K_0402_1%
PR10
100K_0402_1%
1 2
PU1
74LVC1G3157GW SC-88 6P MUX
PU1
74LVC1G3157GW SC-88 6P MUX
V+ 5
NC
3COM 4
GND
2
IN 6
NO
1
PR13
10K_0402_5%@
PR13
10K_0402_5%@
1 2
PC31
0.1U_0603_25V7K
@
PC31
0.1U_0603_25V7K
@
12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5VALWP
Ripple voltage -
Static load 3% / Dynamic load 5%
Frequency 300kHz
TDC 7.8 A
Peak Current 11.15 A
OCP current 13.38 A
TYP MAX
H/S Rds(on) 24mohm , 30mohm
L/S Rds(on) 10.8mohm , 13.6mohm
Choke DCR Max:11.8mohm
Choke Ityp:10A / Isat:16A
Bulk cap ESR 15mohm
3VALWP
Ripple voltage -
Static load 3% / Dynamic load 5%
Frequency 350kHz
TDC 4.5 A
Peak Current 6.5 A
OCP current 7.8 A
TYP MAX
H/S Rds(on) 24mohm , 30mohm
L/S Rds(on) 13.5mohm , 16.5mohm
Choke DCR:15.5
Bulk cap ESR 15mohm
LG_3V
SW1
PGOOD_3V_5V
BST_5V BST_5V_C
LG_5V
3V_5V_EN
BST_3V_C BST_3V
SW2
FB_5V
3V_5V_EN
UG_5V
UG_3V
SNUB_3V
SNUB_5V
FB_3V
3V_5V_EN
+3.3V_ALW2
+DC1_PWR_SRC
+5VALWP
+DC1_PWR_SRC
+DC1_PWR_SRC
+3VALWP
+5V_ALW2
+3.3V_ALW
+PWR_SRC
+3.3V_RTC_LDO
+5VALWP
+3.3V_ALW +5V_ALW
+3VALWP
ALW_PWRGD_3V_5V<53>
ALWON<51>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
+5V_ALW/3.3V_ALW
56 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
+5V_ALW/3.3V_ALW
56 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
+5V_ALW/3.3V_ALW
56 67Monday, January 13, 2014
Compal Electronics, Inc.
PQ103
FDMC7692S_MLP8-5
PQ103
FDMC7692S_MLP8-5
4
5
1
2
3
PC109
0.1U_0603_25V7K
PC109
0.1U_0603_25V7K
1 2
TPS51225CRUKR_QFN20_3X3
PU101
TPS51225CRUKR_QFN20_3X3
PU101
CS1 1
VFB1 2
VREG3 3
VFB2 4
CS2 5
EN2
6
PGOOD
7
SW2
8
VBST2
9
DRVH2
10
DRVL2
11
VIN
12
VREG5
13
VO1 14
DRVL1
15
DRVH1 16
VBST1 17
SW1 18
VCLK 19
EN1
20
PAD 21
PC114
680P_0603_50V7K
@
PC114
680P_0603_50V7K
@
12
PL101
2.2UH_7.8A_20%
PL101
2.2UH_7.8A_20%
1 2
PR100
6.49K_0402_1%
PR100
6.49K_0402_1%
1 2
PJP100
PAD-OPEN 43x118
PJP100
PAD-OPEN 43x118
1 2
PR113
2K_0402_1%
PR113
2K_0402_1%
1 2
PR109
2.2_0603_5%
PR109
2.2_0603_5%
1 2
PR101
15K_0402_1%
PR101
15K_0402_1%
1 2
PQ102
SI7716ADN-T1-GE3_POWERPAK8-5
PQ102
SI7716ADN-T1-GE3_POWERPAK8-5
4
5
1
2
3
PC117
0.1U_0603_25V7K
PC117
0.1U_0603_25V7K
12
PJP102
PAD-OPEN 43x118
PJP102
PAD-OPEN 43x118
1 2
PQ101
SIS412DN-T1-GE3_POWERPAK8-5
PQ101
SIS412DN-T1-GE3_POWERPAK8-5
4
5
1
2
3
PR102
10K_0402_1%
PR102
10K_0402_1%
1 2
PC105
2200P_0402_50V7K
EMC@ PC105
2200P_0402_50V7K
EMC@
12
PC111
680P_0603_50V7K
@PC111
680P_0603_50V7K
@
12
PC119
1U_0603_10V6K
@
PC119
1U_0603_10V6K
@
12
PC118
1U_0603_10V6K
PC118
1U_0603_10V6K
12
PC103
0.1U_0402_25V6
EMC@ PC103
0.1U_0402_25V6
EMC@
12
PR106
143K_0402_1%
PR106
143K_0402_1%
12
PL100
1UH_PCMB053T-1R0MS_7A_20%
PL100
1UH_PCMB053T-1R0MS_7A_20%
1 2
PR107
100K_0402_1%
PR107
100K_0402_1%
1 2
PC101
10U_0805_25V6K
PC101
10U_0805_25V6K
12
PC110
0.1U_0603_25V7K
PC110
0.1U_0603_25V7K
1 2
PC102
10U_0805_25V6K
PC102
10U_0805_25V6K
12
PR111
4.7_1206_5%
@PR111
4.7_1206_5%
@
12
PR104
10K_0402_1%
PR104
10K_0402_1%
1 2
PR105
86.6K_0402_1%
PR105
86.6K_0402_1%
12
PR108
0_0402_5%
PR108
0_0402_5%
1 2
PL102
3.3UH_PIMB104T-3R3MS_10A_20%
PL102
3.3UH_PIMB104T-3R3MS_10A_20%
1 2
PJP101
PAD-OPEN 43x118
PJP101
PAD-OPEN 43x118
1 2
PR103
0_0402_5%
PR103
0_0402_5%
12
+
PC115
220U_6.3V_M
X76_1@
+
PC115
220U_6.3V_M
X76_1@
1
2
PC100
1U_0603_10V6K
PC100
1U_0603_10V6K
12
PJP103
PAD-OPEN 43x118
PJP103
PAD-OPEN 43x118
1 2
+
PC113
220U_6.3V_M
X76_1@
+
PC113
220U_6.3V_M
X76_1@
1
2
PR112
4.7_1206_5%
@
PR112
4.7_1206_5%
@
12
PR110
2.2_0603_5%
PR110
2.2_0603_5%
1 2
PQ100
SIS412DN-T1-GE3_POWERPAK8-5
PQ100
SIS412DN-T1-GE3_POWERPAK8-5
4
5
1
2
3
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FB sense trace
FB sense trace
when FB pull down to GND
EMI Part (35.33)
EMI Part (35.33)
Mode S3 S5 +1.35V_MEN +V_DDR_REF +0.675V_P
S5 L L off off off
S3 L H on on off(Hi-Z)
S0 H H on on on
1.35Volt +/- 5%
TDC: 10.5 A
Peak Current: 15 A
OCP current: 18 A
Rds(on): 3.5m ohm(max)
Choke DCR 3.5mohm(max)
0.675Volt +/- 5%
TDC 1.05A
Peak Current 1.5A
OCP Current 1.8A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DELL CONFIDENTIAL/PROPRIETARY
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DH_1.35V
VLDOIN_1.35V
SW_1.35V
DL_1.35V
VDD_1.35V
S5_1.35V
+V_DDR_REF
SNUB_1.35V
BOOT_1.35V
1.35V_B+
1.35V_FB
S3_1.35V
CS_1.35V
VDDP_1.35V
1.35V_SUS_PWRGD
+1.35V_MEN_P
1.35V_B+
+PWR_SRC
+1.35V_MEN_P
+5V_ALW
+5V_ALW
+1.35V_MEN_P
+0.675V_P
+1.35V_MEN_P
+3.3V_ALW
+1.35V_MEN_P +1.35V_MEM
+0.675V_DDR_VTT
+0.675V_P
+V_DDR_REF
1.35V_SUS_PWRGD<7>
SIO_SLP_S4#<19,41,51,54>
0.675V_DDR_VTT_ON<50>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
1.35VP/0.675VSP
57 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
1.35VP/0.675VSP
57 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
1.35VP/0.675VSP
57 67Monday, January 13, 2014
Compal Electronics, Inc.
PJP203
JUMP_1x3m
PJP203
JUMP_1x3m
11
2
2
PU200
RT8207MZQW_WQFN20_3X3
PU200
RT8207MZQW_WQFN20_3X3
VTTSNS 2
FB
6
S5
8
PGOOD
10
VDDP
12
PHASE 16
BOOT 18
VTTREF 4
PGND
14
VTTGND 1
GND 3
VDDQ 5
S3
7
TON
9
VDD
11
CS
13
LGATE
15
UGATE 17
VTT 20
VLDOIN 19
PAD 21
PC204
0.1U_0402_25V6
EMC@PC204
0.1U_0402_25V6
EMC@
12
PR207
12.4K_0402_1%
PR207
12.4K_0402_1%
1 2
PJP202
PAD-OPEN1x1m
PJP202
PAD-OPEN1x1m
12
+
PC201
330U_2.5V_M
X76_1@
+
PC201
330U_2.5V_M
X76_1@
1
2
PC213
1U_0603_10V6K
PC213
1U_0603_10V6K
12
PC212
680P_0603_50V7K
@EMC@
PC212
680P_0603_50V7K
@EMC@
12
PC211 220P_0402_50V8JPC211 220P_0402_50V8J
1 2
PJP201
PAD-OPEN1x1m
PJP201
PAD-OPEN1x1m
12
PC205
2200P_0402_50V7K
EMC@PC205
2200P_0402_50V7K
EMC@
12
PC215
1U_0402_6.3VX5R
PC215
1U_0402_6.3VX5R
12
PC202
10U_0805_25V6K
@
PC202
10U_0805_25V6K
@
12
PC203
10U_0805_25V6K
PC203
10U_0805_25V6K
12
PC214
.1U_0402_16V7K
@
PC214
.1U_0402_16V7K
@
12
PC210
1U_0603_10V6K
PC210
1U_0603_10V6K
12
PC206
0.22U_0603_10V7K
PC206
0.22U_0603_10V7K
1 2
PJP204
JUMP_1x3m
PJP204
JUMP_1x3m
11
2
2
PR206
200K_0402_5%
PR206
200K_0402_5%
1 2
PC207
22U_0805_6.3VAM
PC207
22U_0805_6.3VAM
12
PR203
5.1_0603_5%
PR203
5.1_0603_5%
1 2
PR205
1M_0402_1%
PR205
1M_0402_1%
1 2
PR202
4.7_1206_5%
@EMC@
PR202
4.7_1206_5%
@EMC@
12
PR201
6.49K_0402_1%
PR201
6.49K_0402_1%
1 2
PQ202
SIRA06DP-T1_POWERPAK-SO8-5
PQ202
SIRA06DP-T1_POWERPAK-SO8-5
4
5
3
2
1
PQ201
SIR472DP-T1-GE3_POWERPAK8-5
PQ201
SIR472DP-T1-GE3_POWERPAK8-5
4
5
1
2
3
PR204
10K_0402_1%
PR204
10K_0402_1%
12
PR209
100K_0402_1%
PR209
100K_0402_1%
12
PR200
2.2_0603_5%
PR200
2.2_0603_5%
1 2
PR208
100K_0402_5%
PR208
100K_0402_5%
1 2
PL201
1.0UH_PCMB104T-1R0MH_18A_20%
PL201
1.0UH_PCMB104T-1R0MH_18A_20%
1 2
PC209
0.033U_0402_16V7K
PC209
0.033U_0402_16V7K
PJP200
PAD-OPEN 1x2m~D
PJP200
PAD-OPEN 1x2m~D
21
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
+1.05VSP
Ripple voltage -
Static load 3% / Dynamic load 5%
Frequency 290kHz
TDC 4.82A
Peak Current 6.89A
OCP current 7.5A
TYP MAX
H/S Rds(on) 24mohm , 30mohm
L/S Rds(on) 13.5mohm , 16.5mohm
Choke DCR 11mohm
Bulk cap ESR 17mohm
EMI Part (35.33)
S0 mode be high level
BST_+1.05VSP
SW _+1.05VSP
UG_+1.05VSP
LG_+1.05VSP
TRIP_+1.05VSPTRIP_+1.05VSP
EN_+1.05VSPEN_+1.05VSP
FB_+1.05VSP
RF_+1.05VSP
+1.05VSP_B+
+PWR_SRC
+5V_ALW
+1.05V_MP
+3.3V_ALW
+1.05V_MP +1.05V_M
SIO_SLP_A#<19,41,51,54>
A_ON<51,54>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
+1.05V_M
58 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
+1.05V_M
58 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
+1.05V_M
58 67Monday, January 13, 2014
Compal Electronics, Inc.
PQ303
SI7716ADN-T1-GE3_POWERPAK8-5
PQ303
SI7716ADN-T1-GE3_POWERPAK8-5
4
5
1
2
3
PR303
0_0402_5%
@PR303
0_0402_5%
@
1 2
PC306
.1U_0603_25V7K
PC306
.1U_0603_25V7K
12
PJP301
PAD-OPEN 1x2m~D
PJP301
PAD-OPEN 1x2m~D
2 1
PJP302
PAD-OPEN 1x2m~D
PJP302
PAD-OPEN 1x2m~D
2 1
PR302
84.5K_0402_1%
PR302
84.5K_0402_1%
1 2
PC309
1000P_0402_50V7K
@EMC@PC309
1000P_0402_50V7K
@EMC@
12
PR315
0_0402_5%
PR315
0_0402_5%
1 2
PC302
0.1U_0402_25V6
EMC@ PC302
0.1U_0402_25V6
EMC@
12
PJP300
PAD-OPEN 1x2m~D
PJP300
PAD-OPEN 1x2m~D
2 1
PU300
TPS51212DSCR_SON10_3X3
PU300
TPS51212DSCR_SON10_3X3
EN
3
TRIP
2
V5IN 7
DRVH 9
SW 8
DRVL 6
VBST 10
TST
5
VFB
4
PGOOD
1
TP 11
PC308
1U_0603_10V6K
PC308
1U_0603_10V6K
1 2
PC303
2200P_0402_50V7K
EMC@ PC303
2200P_0402_50V7K
EMC@
12
PC307
0.22U_0402_16V7K
PC307
0.22U_0402_16V7K
12
PQ301
SIS412DN-T1-GE3_POWERPAK8-5
PQ301
SIS412DN-T1-GE3_POWERPAK8-5
4
5
1
2
3
PR307
10K_0402_1%
PR307
10K_0402_1%
1 2
+
PC301
330U_2.5V_M
X76_1@
+
PC301
330U_2.5V_M
X76_1@
1
2
PR306
4.99K_0402_1%
PR306
4.99K_0402_1%
12
PR301
2.2_0603_5%
PR301
2.2_0603_5%
1 2
PR300
100K_0402_5%
PR300
100K_0402_5%
1 2
PR305
470K_0402_1%
PR305
470K_0402_1%
12
PR304
4.7_1206_5%
@EMC@PR304
4.7_1206_5%
@EMC@
12
PL301
1UH_11A_20%_7X7X3_M
PL301
1UH_11A_20%_7X7X3_M
1 2
PC305
10U_0805_25V6K
PC305
10U_0805_25V6K
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1.5Volt +/- 5%
TDC: 0.15A
Peak Current: 0.2 A
OCP current: 4 A
DELL CONFIDENTIAL/PROPRIETARY
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.5V_RUNP
+3.3V_RUN
+1.5V_RUN
+5V_ALW
+3.3V_RUN
+3.3V_RUN
1.5V_RUN_PWRGD<51>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
+1.5V_RUN
59 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
+1.5V_RUN
59 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
+1.5V_RUN
59 67Monday, January 13, 2014
Compal Electronics, Inc.
PJP401
PAD-OPEN1x1m
PJP401
PAD-OPEN1x1m
1 2
PC403
0.01U_0402_25V7K
PC403
0.01U_0402_25V7K
12
PR401
47K_0402_5%
@PR401
47K_0402_5%
@
12
PC402
.1U_0402_16V7K
@PC402
.1U_0402_16V7K
@
12
PR400
100K_0402_5%
PR400
100K_0402_5%
1 2
PC400
1U_0402_6.3V6K
PC400
1U_0402_6.3V6K
12
PR403
1.74K_0402_1%
PR403
1.74K_0402_1%
12
PC401
4.7U_0805_6.3V6K
PC401
4.7U_0805_6.3V6K
12
PU400
APL5930KAI-TRG_SO8
PU400
APL5930KAI-TRG_SO8
GND
1
VOUT 4
POK
7
EN
8
VCNTL 6
VIN 5
VOUT 3
FB 2
VIN 9
PC404
22U_0805_6.3V6M
PC404
22U_0805_6.3V6M
12
PJP400
PAD-OPEN1x1m
PJP400
PAD-OPEN1x1m
12
PR407
10K_0402_5%
PR407
10K_0402_5%
12
PR402
1.54K_0402_1%
PR402
1.54K_0402_1%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
12VSP_TB +/-5%
TDC 0.7A
Peak Current 1A
OCP 3A(Input)
OVP 14.4V
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DELL CONFIDENTIAL/PROPRIETARY
COMP_12VSP_TB
FB_12VSP_TB
SS_12VSP_TBFREQ_12VSP_TB
LX_12VSP_TB
EN_12VSP_TB
TBT_HV_EN<32>
+12VSP_TB
+12VS_TB
+12VSP_TB
+5V_ALW
+5V_ALW
+3.3V_ALW
+PWR_SRC
+PWR_SRC
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
12VS_TB
60 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
12VS_TB
60 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
12VS_TB
60 67Monday, January 13, 2014
Compal Electronics, Inc.
PQ601
AON7403L_DFN8-5
TB@
PQ601
AON7403L_DFN8-5
TB@
3
52
4
1
PU600
RT9297GQW_WDFN10_3X3
TB@
PU600
RT9297GQW_WDFN10_3X3
TB@
COMP 1
FB 2
EN
3
Vin
8
FREQ
9SS 10
GND
5
GND
4LX 6
LX 7
PAD
11
PR619
866_0402_1%
TB@
PR619
866_0402_1%
TB@
1 2
PC614 10U_0805_25V6K
TB@
PC614 10U_0805_25V6K
TB@
12
PR603
10K_0402_1%
TB@PR603
10K_0402_1%
TB@
1 2
PD602
SX35H_SMA2
TB@
PD602
SX35H_SMA2
TB@
2 1
PQ602B
DMN66D0LDW-7_SOT363-6
TB@ PQ602B
DMN66D0LDW-7_SOT363-6
TB@
3
5
4
PR614
402K_0402_1%
TB@
PR614
402K_0402_1%
TB@
12
PR607
49.9K_0402_1%
TB@
PR607
49.9K_0402_1%
TB@
12
PC607
10U_0805_25V6K
TB@
PC607
10U_0805_25V6K
TB@
12
PR612
86.6K_0402_1%
TB@
PR612
86.6K_0402_1%
TB@
1 2
PC616 10U_0805_25V6K
TB@
PC616 10U_0805_25V6K
TB@
12
PR611
110K_0402_1%
TB@
PR611
110K_0402_1%
TB@
1 2
PC603
0.022U_0402_25V7K
TB@
PC603
0.022U_0402_25V7K
TB@
12
PD601
SX35H_SMA2
TB@
PD601
SX35H_SMA2
TB@
2 1
PR616
10K_0402_1%
TB@
PR616
10K_0402_1%
TB@
1 2
PC617 10U_0805_25V6K
TB@
PC617 10U_0805_25V6K
TB@
12
PC613 10U_0805_25V6K
TB@
PC613 10U_0805_25V6K
TB@
12
PL601
4.7UH_5.5A_20%_7X7X3_M
TB@PL601
4.7UH_5.5A_20%_7X7X3_M
TB@
12
PR613
10K_0402_1%
TB@
PR613
10K_0402_1%
TB@
1 2
PC601
680P_0603_50V7K
@EMC@
PC601
680P_0603_50V7K
@EMC@
1 2
PC608
4700P_0402_25V7K
TB@
PC608
4700P_0402_25V7K
TB@
12
PR618
10K_0402_1%
TB@
PR618
10K_0402_1%
TB@
1 2
PR605
0_0402_5%
TB@
PR605
0_0402_5%
TB@
1 2
PJP602
PAD-OPEN1x1m
PJP602
PAD-OPEN1x1m
1 2
PU602A
LM393DR_SO8
PU602A
LM393DR_SO8
+3
-2
0
1
P
8G4
PR608
2.49K_0402_1%
TB@
PR608
2.49K_0402_1%
TB@
1 2
PR604
100K_0402_1%
@
PR604
100K_0402_1%
@
1 2
PR610
10K_0402_1%
TB@
PR610
10K_0402_1%
TB@
12
PC612 10U_0805_25V6K
TB@
PC612 10U_0805_25V6K
TB@
12
PJP601
PAD-OPEN 1x2m~D
PJP601
PAD-OPEN 1x2m~D
21
PC606
0.1U_0402_16V7K
TB@
PC606
0.1U_0402_16V7K
TB@
12
PR609
0_0402_5%TB@
PR609
0_0402_5%TB@
1 2
PC604
1500P_0402_50V7K
TB@
PC604
1500P_0402_50V7K
TB@
12
PQ602A
DMN66D0LDW-7_SOT363-6
TB@ PQ602A
DMN66D0LDW-7_SOT363-6
TB@
61
2
PC609
0.01U_0402_16V7K
TB@
PC609
0.01U_0402_16V7K
TB@
12
PR601
4.7_1206_5%
@EMC@
PR601
4.7_1206_5%
@EMC@
1 2
PC615 10U_0805_25V6K
TB@
PC615 10U_0805_25V6K
TB@
12
PC610
0.01U_0402_50V7K
@
PC610
0.01U_0402_50V7K
@
12
PC611 10U_0805_25V6K
@
PC611 10U_0805_25V6K
@
12
PC602
0.1U_0402_16V7K
@
PC602
0.1U_0402_16V7K
@
12
PR617
31.6K_0402_1%
TB@
PR617
31.6K_0402_1%
TB@
1 2
PC605
10U_0805_25V6K
TB@
PC605
10U_0805_25V6K
TB@
12
PR606
100K_0402_1%
TB@
PR606
100K_0402_1%
TB@
1 2
PR615
1.5M_0402_1%
TB@
PR615
1.5M_0402_1%
TB@
12
G
D
S
PQ604
S TR 2N7002KW 1N SOT323-3
TB@
G
D
S
PQ604
S TR 2N7002KW 1N SOT323-3
TB@
2
13
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DELL CONFIDENTIAL/PROPRIETARY
VCC_core (Base on PDDG rev 2.0)
TDC 33A
Peak Current 95A
DC Load line -1.5mV/A
Icc_Dyn_VID1 60A
OCP current 114A
DCR 0.98m ohm
Local sense put on HW site
EMI Part (47.1)
EMI Part (47.1)
VR12.5->PR509=3.24K
VR12.6->PR509=16.9K
UGATE2
PHASE2
BOOT2
UGATE2
UGATE1
BOOT2
CPU_B+
LGATE2
LGATE1
PHASE1
BOOT1
BOOT1
PHASE1
UGATE1
LGATE1
CPU_B+
VR_HOT#
LGATE2
PHASE3
CPU_B+
UGATE3
SNB_CPU_P1
SNB_CPU_P2
SNB_CPU_P3
CPU_B+
PWM3
SCLK
ALERT#
SDA
VR_ON
VCC_PGOOD
IMON
NTC
VCCSENSE
COMP
FB
ISEN3
ISEN2
ISEN1
ISUMPISUMN
ISUMN
ISUMP
ISUMN
V2N
V3N
ISEN1
ISUMP
V1N
V3N
ISEN2
ISUMN
ISUMP
ISEN3
V1N
V2N
ISUMN
BOOT3
LGATE3
PWM3
VCORE_VDDP
P3_SW
PHASE2
P1_SW
P2_SW
P3_SW_1
V3N
P2_SW_1
V2N
P1_SW_1
V1N
+VCC_CORE
+VCC_CORE
+VCC_CORE
+PWR_SRC
+VCCIO_OUT
+3.3V_RUN
+5V_ALW
+5V_ALW
+5V_ALW
H_PROCHOT#<51,62,7>
VIDSCLK<11>
VIDALERT_N<11>
VIDSOUT<11>
IMVP_VR_ON<51>
PCH_PWROK<19>
VCCSENSE<11>
VSSSENSE<11>
1.05V_0.8V_PWROK<51>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
+VCC_CORE
61 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
+VCC_CORE
61 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
+VCC_CORE
61 67Monday, January 13, 2014
Compal Electronics, Inc.
PC519
.1U_0603_25V7K
PC519
.1U_0603_25V7K
12
PR551
2.61K_0402_1%
PR551
2.61K_0402_1%
1 2
PC527
330P_0402_50V7K~D
PC527
330P_0402_50V7K~D
1 2
PR522
0_0402_5%
PR522
0_0402_5%
1 2
PR536
2.87K_0402_1%
PR536
2.87K_0402_1%
12
PC534
10U_0805_25VAK
PC534
10U_0805_25VAK
12
PR528
27.4K_0402_1%
PR528
27.4K_0402_1%
12
PR508 0_0402_5%
PR508 0_0402_5%
1 2
PR524 0_0402_5%PR524 0_0402_5%
1 2
PQ501
CSD87350Q5D_SON8~D
PQ501
CSD87350Q5D_SON8~D
1
2
5
4
6
7
3
8
PL502
0.22UH_PCME064T-R22MS_28A_20%
PL502
0.22UH_PCME064T-R22MS_28A_20%
1
3
4
2
PC532
0.1U_0603_25V7K
PC532
0.1U_0603_25V7K
1 2
PC538
0.033U_0603_25V7K
@PC538
0.033U_0603_25V7K
@
1 2
PU500
ISL95812HRZ-T_QFN32_4x4
PU500
ISL95812HRZ-T_QFN32_4x4
SCLK
1
VR_ON
2
PGOOD
3
IMON
4
VR_HOT#
5
NTC
6
COMP
7
FB
8
FB2/VSEN
9
ISEN3
10
ISEN2
11
ISEN1
12
RTN
13
ISUMN
14
ISUMP
15
VDD
16
VIN 17
BOOT1 18
UGATE1 19
PHASE1 20
LGATE1 21
PWM3 22
VDDP 23
LGATE2 24
PHASE2 25
UGATE2 26
BOOT2 27
PROG2 28
SLOPE/PROG1 30
SDA 31
ALERT# 32
PAD
33
PROG3 29
PR558
5.1M_0402_5%
PR558
5.1M_0402_5%
1 2
PR552
3.65K_0603_1%
PR552
3.65K_0603_1%
1 2
PR544
10_0402_1%
PR544
10_0402_1%
12
PR542
4.7_1206_5%
EMC@ PR542
4.7_1206_5%
EMC@
12
PR506 0_0402_5%
PR506 0_0402_5%
1 2
PR553
10K_0603_1%
PR553
10K_0603_1%
1 2
PR504 54.9_0402_1%PR504 54.9_0402_1%
12
PR503 75_0402_5%@PR503 75_0402_5%@
12
PC510
47P_0402_50V8J
PC510
47P_0402_50V8J
12
PC513
10U_0805_25VAK
PC513
10U_0805_25VAK
12
PR556
10K_0402_1%
@PR556
10K_0402_1%
@
12
PH501
10KB_0402_5%_ERTJ0ER103J
PH501
10KB_0402_5%_ERTJ0ER103J
1 2
PC522
4700P_0402_25V7K
PC522
4700P_0402_25V7K
12
PC542
330P_0402_50V7K
@PC542
330P_0402_50V7K
@
1 2
PR554
4.7_1206_5%
EMC@ PR554
4.7_1206_5%
EMC@
12
PR543
2K_0402_1%
PR543
2K_0402_1%
1 2
PC523
680P_0603_50V7K
EMC@ PC523
680P_0603_50V7K
EMC@
12
PC540
0.22U_0603_16V7K
PC540
0.22U_0603_16V7K
1 2
PC500
1U_0603_10V6K
PC500
1U_0603_10V6K
12
PC520
680P_0402_50V7K
PC520
680P_0402_50V7K
12
PR529
6.04K_0402_1%
PR529
6.04K_0402_1%
1 2
PR526
0_0402_5%
PR526
0_0402_5%
1 2
PR512
10_0402_1%
PR512
10_0402_1%
1 2
PQ502
CSD87350Q5D_SON8~D
PQ502
CSD87350Q5D_SON8~D
1
2
5
4
6
7
3
8
PR505 0_0402_5%
PR505 0_0402_5%
1 2
PC504
10U_0805_25VAK
PC504
10U_0805_25VAK
12
PC533
10U_0805_25VAK
PC533
10U_0805_25VAK
12
PC526
4700P_0402_25V7K
PC526
4700P_0402_25V7K
1 2
PR519 1.91K_0402_1%PR519 1.91K_0402_1%
12
PR533
499_0402_1%
PR533
499_0402_1%
12
PC507
680P_0603_50V7K
EMC@ PC507
680P_0603_50V7K
EMC@
12
PR525
3.83K_0402_1%
PR525
3.83K_0402_1%
1 2
PC535
10U_0805_25VAK
PC535
10U_0805_25VAK
12
PR502
2.2_0603_5%
PR502
2.2_0603_5%
12
+
PC531
100U_25V_M
+
PC531
100U_25V_M
1
2
PC528
0.15U_0402_10V6K
PC528
0.15U_0402_10V6K
1 2
PC541
0.22U_0402_6.3V6K
PC541
0.22U_0402_6.3V6K
12
PC547
.1U_0402_16V7K
PC547
.1U_0402_16V7K
12
PR500 130_0402_1%PR500 130_0402_1%
12
PC545
680P_0603_50V7K
EMC@ PC545
680P_0603_50V7K
EMC@
12
PR507
21K_0402_1%
PR507
21K_0402_1%
1 2
PR534
2.2_0603_5%
PR534
2.2_0603_5%
12
PC544
0.082U_0402_16V7K
@
PC544
0.082U_0402_16V7K
@
12
PR531
1_0402_1%
PR531
1_0402_1%
1 2
PC509
820P_0402_50V7K
PC509
820P_0402_50V7K
1 2
PC543
0.22U_0402_6.3V6K
PC543
0.22U_0402_6.3V6K
12
PR535
3.65K_0603_1%
PR535
3.65K_0603_1%
1 2
PC539
0.22U_0402_6.3V6K
PC539
0.22U_0402_6.3V6K
12
PQ500
CSD87350Q5D_SON8~D
PQ500
CSD87350Q5D_SON8~D
1
2
5
4
6
7
3
8
PR515
4.7_1206_5%
EMC@ PR515
4.7_1206_5%
EMC@
12
PR548
0_0402_5%
PR548
0_0402_5%
1 2
PR557
10K_0402_1%
@PR557
10K_0402_1%
@
12
PR541
909_0402_1%
PR541
909_0402_1%
1 2
PR518
10K_0402_1%
@PR518
10K_0402_1%
@
12
PC516
470P_0402_50V7K
EMC@ PC516
470P_0402_50V7K
EMC@
12
PR517
0_0402_5%
PR517
0_0402_5%
1 2
PR514
21K_0402_1%
PR514
21K_0402_1%
1 2
PC503
10U_0805_25VAK
PC503
10U_0805_25VAK
12
PR555
10_0402_1%
PR555
10_0402_1%
12
PC514
10U_0805_25VAK
PC514
10U_0805_25VAK
12
PC515
0.1U_0402_25V6
@EMC@ PC515
0.1U_0402_25V6
@EMC@
12
PC511
0.22U_0603_25V7K
PC511
0.22U_0603_25V7K
12
PL500
0.22UH_PCME064T-R22MS_28A_20%
PL500
0.22UH_PCME064T-R22MS_28A_20%
1
3
4
2
PC501
0.22U_0603_16V7K
PC501
0.22U_0603_16V7K
1 2
PR546
10K_0402_1%
@PR546
10K_0402_1%
@
12
PR537
576_0402_1%
PR537
576_0402_1%
12
PR520
0_0603_5%
PR520
0_0603_5%
1 2
PR509
3.24K_0402_1%
PR509
3.24K_0402_1%
1 2
PH500
470K_0402_5%_ TSM0B474J4702RE
PH500
470K_0402_5%_ TSM0B474J4702RE
12
PC546
0.01U_0402_50V7K
PC546
0.01U_0402_50V7K
1 2
PL501 0.22UH_PCME064T-R22MS_28A_20%PL501 0.22UH_PCME064T-R22MS_28A_20%
1
3
4
2
PC502
10U_0805_25VAK
PC502
10U_0805_25VAK
12
PR550
11K_0402_1%
PR550
11K_0402_1%
1 2
PR521
93.1K_0402_1%
PR521
93.1K_0402_1%
12
PC521
0.22U_0603_16V7K
PC521
0.22U_0603_16V7K
1 2
PC512
10U_0805_25VAK
PC512
10U_0805_25VAK
12
PR549
2.2_0603_5%
PR549
2.2_0603_5%
12
PR510
10K_0603_1%
PR510
10K_0603_1%
12
PR511
3.65K_0603_1%
PR511
3.65K_0603_1%
1 2
PC525
39P_0402_50V8J
PC525
39P_0402_50V8J
1 2
PR513
0_0402_5%
@PR513
0_0402_5%
@
1 2
+
PC530
100U_25V_M
+
PC530
100U_25V_M
1
2
PU501
ISL6208BCRZ-T_QFN8_2X2
PU501
ISL6208BCRZ-T_QFN8_2X2
LGATE 5
PWM
3
GND
4
UGATE 1
VCC
6
FCCM
7
PHASE 8
BOOT 2
TP
9
PR547
10K_0402_1%
@PR547
10K_0402_1%
@
12
PR539
10K_0603_1%
PR539
10K_0603_1%
1 2
+
PC529
100U_25V_M
+
PC529
100U_25V_M
1
2
PR501
0_0402_5%
PR501
0_0402_5%
1 2
PC508
1U_0603_10V6K
PC508
1U_0603_10V6K
1 2
PR545
1.5K_0402_1%
PR545
1.5K_0402_1%
1 2
PR516
10K_0402_1%
@PR516
10K_0402_1%
@
12
PL510
FBMA-L11-453215-800LMA90T_1812
EMC@ PL510
FBMA-L11-453215-800LMA90T_1812
EMC@
1 2
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
ADP_I = 20*Iadapter*Rsense
Iada=0~12.3A240W)
EMI Part (47.1)
EMI Part (35.33)
Current limit
Charger :5.12A Vilim=1.024V
8 Cell (0.8C )
Max Boost Charger :6.4A, Vilim=0.32V
EMI Part (47.1)
AC Det (typ 2.4V)
Max:17.77V
Typ :17.60V
Min :17.42V
CMP_REF=2.3V
+DC_IN>17.6V then ACAV_IN_NB high
DELL CONFIDENTIAL/PROPRIETARY
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SNUB_CHG
CHG
CSON_1
CSSN_1
CSSP_1
LX_CHG
UGATE_CHG
CSSP_2
CSSN_2
+DCIN
BQ24780_REGN
CMPOUT
CMPIN
CSOP_1
LGATE_CHG
BQ24780_REGN
CHG
CMPOUT
CMPIN
+CHAGER_SRC
+PWR_SRC
+DC_IN_SS
+SDC_IN
+VCHGR
+DOCK_PWR_BAR
+DC_IN_SS
GNDA_CHG
+SDC_IN
GNDA_CHG
GNDA_CHG
+3.3V_ALW
GNDA_CHG GNDA_CHG
+3.3V_ALW
+3.3V_ALW
+DC_IN
GNDA_CHG
GNDA_CHG
DC_BLOCK_GC <63>
CSS_GC<63>
DK_CSS_GC <63>
DOCK_DCIN_IS- <48>
DOCK_DCIN_IS+ <48>
CHARGER_SMBDAT<51>
CHARGER_SMBCLK<51>
ACAV_IN<17,51,63>
I_ADP<51>
I_BATT<51>
H_PROCHOT#<51,61,7>
PBAT_PRES#<51,55>
ACAV_IN_NB<51,63>
TB_STAT#<50,62>
TB_STAT# <50,62>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Charger
62 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Charger
62 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Charger
62 67Monday, January 13, 2014
Compal Electronics, Inc.
PR720
121K_0402_1%
PR720
121K_0402_1%
12
PR700 0_0402_5%PR700 0_0402_5%
12
PD702
SDMK0340L-7-F_SOD323-2~D
PD702
SDMK0340L-7-F_SOD323-2~D
12
PR704
1K_0402_1%
PR704
1K_0402_1%
12
PL701
4.7UH_5.5A_20%_7X7X3_M
PL701
4.7UH_5.5A_20%_7X7X3_M
1 2
PR719
316K_0402_1%
PR719
316K_0402_1%
1 2
PR728
0_0402_5%
PR728
0_0402_5%
1 2
PR761
10_0402_1%
PR761
10_0402_1%
12
PC700
0.1U_0603_25V7K
@
PC700
0.1U_0603_25V7K
@
12
PC702
1U_0603_25V6K
PC702
1U_0603_25V6K
1 2
PC705
2200P_0402_50V7K
@EMC@ PC705
2200P_0402_50V7K
@EMC@
12
PR764
46.4K_0402_1%
PR764
46.4K_0402_1%
1 2
PC703
0.1U_0402_25V6
PC703
0.1U_0402_25V6
1 2
G
D
S
PQ702
NTR4502PT1G_SOT23-3
G
D
S
PQ702
NTR4502PT1G_SOT23-3
2
13
PR723
0.01_1206_1%
PR723
0.01_1206_1%
1
3
4
2
PR737
665K_0402_1%
PR737
665K_0402_1%
12
PC720
100P_0402_50V8J
PC720
100P_0402_50V8J
1 2
PR729 0_0402_5%PR729 0_0402_5%
1 2
PC714
2.2U_0603_10V6K
PC714
2.2U_0603_10V6K
1 2
G
D
S
PQ703A
SI3993CDV
G
D
S
PQ703A
SI3993CDV
1
65
PR762
10_0402_1%
PR762
10_0402_1%
12
PR724
4.7_1206_5%
EMC@ PR724
4.7_1206_5%
EMC@
12
PQ707A
DMN66D0LDW-7_SOT363-6
PQ707A
DMN66D0LDW-7_SOT363-6
61
2
PR758 4.99K_0402_1%PR758 4.99K_0402_1%
12
PR765
2.2_0603_5%
PR765
2.2_0603_5%
1 2
PU700
BQ24780
PU700
BQ24780
HIDRV 26
SRP 20
PHASE 27
BATDRV 18
SDA
11
IDCHG
8
ACDRV 4
VCC
28
CMSRC
3
ACDET
6
SCL
12
ACOK
5
IADP
7
BTST 25
BATSRC 17
CMPIN
13
REGN 24
GND 22
ACP 2
SRN 19
ILIM 21
LODRV 23
PMON
9
PROCHOT#
10
ACN 1
CMPOUT
14
BATPRES#
15
TB_STAT#
16
PWPD
29
PR701
0.005_1206_1%
PR701
0.005_1206_1%
1
3
4
2
PC710
0.1U_0402_25V6
PC710
0.1U_0402_25V6
1 2
G
D
S
PQ700
NTR4502PT1G_SOT23-3
G
D
S
PQ700
NTR4502PT1G_SOT23-3
2
13
PC713
0.1U_0402_25V6
PC713
0.1U_0402_25V6
1 2
PC708
10U_0805_25V6K
PC708
10U_0805_25V6K
12
PR706
4.12K_0603_1%
PR706
4.12K_0603_1%
12
PC704
0.1U_0402_25V6
PC704
0.1U_0402_25V6
1 2
PC717
680P_0402_50V7K
EMC@ PC717
680P_0402_50V7K
EMC@
12
PC715
10U_0805_25V5K~D
@
PC715
10U_0805_25V5K~D
@
12
PR712
100K_0402_1%
PR712
100K_0402_1%
12
PR740
10K_0402_1%
PR740
10K_0402_1%
12
ES2AA-13-F
PD700@
ES2AA-13-F
PD700@
2 1
PR726 0_0402_5%PR726 0_0402_5%
1 2
PR716 0_0402_5%PR716 0_0402_5%
1 2
PR718
49.9K_0402_1%
PR718
49.9K_0402_1%
12
PC741
100P_0402_50V8J
PC741
100P_0402_50V8J
1 2
PR711
0_0402_5%
PR711
0_0402_5%
12
PC707
10U_0805_25V6K
PC707
10U_0805_25V6K
12
PC719
10U_0805_25V5K~D
PC719
10U_0805_25V5K~D
12
PQ704
SIR472DP-T1-GE3_POWERPAK8-5
PQ704
SIR472DP-T1-GE3_POWERPAK8-5
4
5
1
2
3
PC737
100P_0402_50V8J
PC737
100P_0402_50V8J
12
PC712
0.1U_0402_25V6
PC712
0.1U_0402_25V6
1 2
PR713
100_0402_1%
PR713
100_0402_1%
12
PC718
10U_0805_25V5K~D
PC718
10U_0805_25V5K~D
12
PR717
10_1206_5%
PR717
10_1206_5%
12
PR743
0_0402_5%
PR743
0_0402_5%
12
PR715
110_0402_1%
PR715
110_0402_1%
12
PR738
3M_0402_5%
PR738
3M_0402_5%
12
PD701
BAT54CW_SOT323-3
PD701
BAT54CW_SOT323-3
3
2
1
PR703
0_0402_5%
PR703
0_0402_5%
12
PR725 0_0402_5%PR725 0_0402_5%
1 2
PC709
1U_0603_25V6K
PC709
1U_0603_25V6K
12
PR745
100K_0402_1%
PR745
100K_0402_1%
12
PR714 0_0402_5%
PR714 0_0402_5%
12
PR709
100K_0402_1%
PR709
100K_0402_1%
12
PR757
10K_0402_5%
PR757
10K_0402_5%
12
PC711 0.1U_0402_25V4Z~DPC711 0.1U_0402_25V4Z~D
12
PR710
0_0402_5%
PR710
0_0402_5%
12
G
D
S
PQ703B
SI3993CDV
G
D
S
PQ703B
SI3993CDV
3
42
PR722
100K_0402_1%
PR722
100K_0402_1%
12
PR721 0_0402_5%PR721 0_0402_5%
1 2
PJP701
PAD-OPEN1x1m
PJP701
PAD-OPEN1x1m
1 2
PL700
1UH_PCMB053T-1R0MS_7A_20%
EMC@ PL700
1UH_PCMB053T-1R0MS_7A_20%
EMC@
12
PC706
0.1U_0603_25V7K
@EMC@ PC706
0.1U_0603_25V7K
@EMC@
12
PQ701 SI7149DPPQ701 SI7149DP
3
2
4
1
5
PC734
0.047U_0603_50V7
PC734
0.047U_0603_50V7
12
PC721
100P_0402_50V8J
PC721
100P_0402_50V8J
1 2
PR727 0_0402_5%PR727 0_0402_5%
1 2
PQ705
FDMC7692S_MLP8-5
PQ705
FDMC7692S_MLP8-5
3 5
2
4
1
PD703
MM3Z22VST1G_SOD323-2
PD703
MM3Z22VST1G_SOD323-2
12
PR760
14.7K_0402_1%
PR760
14.7K_0402_1%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
PBATT_IN_SS
DSCHRG_MOSFET_GC
BLK_MOSFET_GC
ERC1
ACAVIN
P33ALW2
ERC2
ERC3
3301_PWRSRC
STSTART_DCBLOCK_GC
BLKNG_MOSFET_GC
ACAVDK_SRC
CD3301_SDC_IN
P33ALW
CD3301_NBDOCK_DC_IN_SS
P50ALW
CD_PBATT_OFF
DK_AC_OFF
SL_BAT_PRES#
DK_AC_OFF_EN
3301_ACAV_IN_NB
DK_PWR_BAR
3301_DC_IN_SS
STSTART_DCBLOCK_GC
CD3301_DCIN
EN_DK_PWRBAR
PBATT+
+PWR_SRC
+DOCK_PWR_BAR
+DOCK_PWR_BAR
+DC_IN_SS
+DC_IN
+SDC_IN
+3.3V_ALW2
+PWR_SRC
+3.3V_ALW
+5V_ALW
+NBDOCK_DC_IN_SS
+3.3V_ALW2
+VCHGR
+3.3V_ALW2
DC_BLOCK_GC<62>
CSS_GC<62>
DK_CSS_GC<62>
SLICE_BAT_ON <50>
ACAV_IN_NB <51,62>
DOCK_AC_OFF_EC <50>
SLICE_BAT_PRES# <48,50,55,63>
EN_DOCK_PWR_BAR <50>
ACAV_IN<17,51,62>
ACAV_DOCK_SRC#<48>
DOCK_AC_OFF <48>
SOFT_START_GC<55>
AC_DIS<51,55>
SLICE_BAT_PRES#<48,50,55,63>
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Selector
63 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Selector
63 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
Selector
63 67Monday, January 13, 2014
Compal Electronics, Inc.
PD1002
PDS5100H-13_POWERDI5-3~D
PD1002
PDS5100H-13_POWERDI5-3~D
2
3
1
PR1021 0_0402_5%
PR1021 0_0402_5%
1 2
PR1018
1M_0402_5%
PR1018
1M_0402_5%
1 2
PR1005
1K_1206_5%
PR1005
1K_1206_5%
12
PR1024 0_0402_5%PR1024 0_0402_5%
1 2
PC1001
0.47U_0805_25V7K~D
PC1001
0.47U_0805_25V7K~D
12
PC1005
1U_0603_25V6K
PC1005
1U_0603_25V6K
12
PC1003
0.1U_0402_25V6
@
PC1003
0.1U_0402_25V6
@
12
PC1008
0.047U_0603_25V7K~D
PC1008
0.047U_0603_25V7K~D
12
PR1100
100K_0402_5%
PR1100
100K_0402_5%
12
PD1001 PDS5100H-13_POWERDI5-3~DPD1001 PDS5100H-13_POWERDI5-3~D
2
3
1
PR1012 0_0402_5%
PR1012 0_0402_5%
1 2
PR1029
0_0402_5%
PR1029
0_0402_5%
1 2
PC1002
2200P_0402_50V7K
@
PC1002
2200P_0402_50V7K
@
12
PR1002 0_0402_5%
PR1002 0_0402_5%
12
PR1022 0_0402_5%
PR1022 0_0402_5%
1 2
PR1020 0_0402_5%
PR1020 0_0402_5%
1 2
PQ1003 AO4407AL_SO8PQ1003 AO4407AL_SO8
3 6
5
7
8
2
4
1
PR1001
330K_0402_5%
PR1001
330K_0402_5%
12
PR1003
330K_0402_5%
PR1003
330K_0402_5%
1 2
G
D
S
PQ1011
SSM3K7002FU_SC70-3~D
G
D
S
PQ1011
SSM3K7002FU_SC70-3~D
2
13
PD1010
BAT54CW_SOT323-3
PD1010
BAT54CW_SOT323-3
3
2
1
PQ1001 SI7149DPPQ1001 SI7149DP
3
2
4
1
5
PR1008
0_0402_5%
PR1008
0_0402_5%
1 2
PC1004
1U_0603_25V6K
PC1004
1U_0603_25V6K
12
PD1100
SDMK0340L-7-F_SOD323-2
PD1100
SDMK0340L-7-F_SOD323-2
1 2
PR1014 0_0402_5%
PR1014 0_0402_5%
1 2
PR1006 0_0402_5%
PR1006 0_0402_5%
1 2
PR1011 47_0805_5%PR1011 47_0805_5%
1 2
PR1032 0_0402_5%
@PR1032 0_0402_5%
@
1 2
PR1013 100K_0402_5%PR1013 100K_0402_5%
1 2
PQ1002
SI4835DDY-T1-E3_SO8
PQ1002
SI4835DDY-T1-E3_SO8
36
5
7
8
2
4
1
PU1001
CD3301BRHHR
PU1001
CD3301BRHHR
DC_IN
1
SS_GC
2
ERC1
3
ACAVDK_SRC
4
GND
5
SDC_IN
6
DC_BLK_GC
7
ACAV_IN
8
SS_DCBLK_GC
16
CSS_GC
10
DK_CSS_GC
11
ERC3
12
ERC2
13
GND
14
PWR_SRC
15
BLKNG_MOSFET_GC 20
SL_BAT_PRES# 21
DK_AC_OFF_EN 22
GND 23
ACAV_IN_NB 24
DK_AC_OFF_EN 25
PBATT_OFF 26
P50ALW 27
PBatt+ 28
DSCHRG_MOSFET_GC 29
BLK_MOSFET_GC 30
NC 31
DK_PWRBAR 33
DC_IN_SS 34
CHARGERVR_DCIN 35
P33ALW2
9
EN_DK_PWRBAR
17
P33ALW
18
TP
37
NBDK_DCINSS 19
NC 36
GND 32
PR1009
0_0402_5%
PR1009
0_0402_5%
12
PR1017 0_0402_5%
PR1017 0_0402_5%
1 2
PR1025 0_0402_5%
PR1025 0_0402_5%
1 2
PR1015 0_0402_5%
PR1015 0_0402_5%
1 2
PR1023 0_0402_5%
PR1023 0_0402_5%
1 2
PC1009
0.1U_0402_25V6
@
PC1009
0.1U_0402_25V6
@
12
PR1028
1M_0402_5%
@PR1028
1M_0402_5%
@
1 2
PR1030
10K_0402_5%
PR1030
10K_0402_5%
12
PR1019 0_0402_5%
PR1019 0_0402_5%
1 2
G
D
S
PQ1072
NTR4502PT1G_SOT23-3
G
D
S
PQ1072
NTR4502PT1G_SOT23-3
2
13
PR1004
0_0402_5%
PR1004
0_0402_5%
12
PR1027 0_0402_5%
PR1027 0_0402_5%
1 2
PR1031
330K_0402_5%
PR1031
330K_0402_5%
1 2
PC1006
0.1U_0603_50V4Z
PC1006
0.1U_0603_50V4Z
12
PQ1004 AO4407AL_SO8PQ1004 AO4407AL_SO8
36
5
7
8
2
4
1
PR1010 0_0402_5%
PR1010 0_0402_5%
1 2
PR1016 0_0402_5%
PR1016 0_0402_5%
1 2
PC1007
0.1U_0603_25V7K
PC1007
0.1U_0603_25V7K
12
PR1007 0_0402_5%
PR1007 0_0402_5%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Based on SB PDDG rev 2.0 Table 5-2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DELL CONFIDENTIAL/PROPRIETARY
+VCC_CORE
+VCC_CORE+VCC_CORE
+VCC_CORE
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
PROCESSOR DECOUPLING
64 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
PROCESSOR DECOUPLING
64 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
PROCESSOR DECOUPLING
64 67Monday, January 13, 2014
Compal Electronics, Inc.
PC945
1U_0402_6.3V6K
PC945
1U_0402_6.3V6K
12
PC968
22U_0805_6.3VAM
PC968
22U_0805_6.3VAM
1
2
PC951
1U_0402_6.3V6K
PC951
1U_0402_6.3V6K
12
PC943
22U_0805_6.3VAM
PC943
22U_0805_6.3VAM
1
2
PC926
22U_0805_6.3VAM
PC926
22U_0805_6.3VAM
1
2
PC971
22U_0805_6.3VAM
PC971
22U_0805_6.3VAM
1
2
PC921
22U_0805_6.3VAM
PC921
22U_0805_6.3VAM
1
2
PC902
10U_0603_4VAM
PC902
10U_0603_4VAM
1
2
PC917
22U_0805_6.3VAM
PC917
22U_0805_6.3VAM
1
2
PC960
1U_0402_6.3V6K
PC960
1U_0402_6.3V6K
12
PC918
22U_0805_6.3VAM
PC918
22U_0805_6.3VAM
1
2
PC935
22U_0805_6.3VAM
PC935
22U_0805_6.3VAM
1
2
+
PC905
330U_D2_2.5VM_R6M~D
+
PC905
330U_D2_2.5VM_R6M~D
1
2
PC956
1U_0402_6.3V6K
PC956
1U_0402_6.3V6K
12
+
PC908
330U_D2_2.5VM_R6M~D
+
PC908
330U_D2_2.5VM_R6M~D
1
2
+
PC906
330U_D2_2.5VM_R6M~D
+
PC906
330U_D2_2.5VM_R6M~D
1
2
PC939
22U_0805_6.3VAM
PC939
22U_0805_6.3VAM
1
2
PC937
22U_0805_6.3VAM
PC937
22U_0805_6.3VAM
1
2
PC954
1U_0402_6.3V6K
PC954
1U_0402_6.3V6K
12
PC966
22U_0805_6.3VAM
PC966
22U_0805_6.3VAM
1
2
PC922
22U_0805_6.3VAM
PC922
22U_0805_6.3VAM
1
2
PC944
1U_0402_6.3V6K
PC944
1U_0402_6.3V6K
12
PC920
22U_0805_6.3VAM
PC920
22U_0805_6.3VAM
1
2
PC919
22U_0805_6.3VAM
PC919
22U_0805_6.3VAM
1
2
PC941
22U_0805_6.3VAM
PC941
22U_0805_6.3VAM
1
2
PC963
1U_0402_6.3V6K
PC963
1U_0402_6.3V6K
12
PC961
1U_0402_6.3V6K
PC961
1U_0402_6.3V6K
12
PC950
1U_0402_6.3V6K
PC950
1U_0402_6.3V6K
12
PC964
22U_0805_6.3VAM
PC964
22U_0805_6.3VAM
1
2
+
PC907
330U_D2_2.5VM_R6M~D
+
PC907
330U_D2_2.5VM_R6M~D
1
2
PC970
22U_0805_6.3VAM
PC970
22U_0805_6.3VAM
1
2
PC953
1U_0402_6.3V6K
PC953
1U_0402_6.3V6K
12
PC936
22U_0805_6.3VAM
PC936
22U_0805_6.3VAM
1
2
PC962
1U_0402_6.3V6K
PC962
1U_0402_6.3V6K
12
PC958
1U_0402_6.3V6K
PC958
1U_0402_6.3V6K
12
PC925
22U_0805_6.3VAM
PC925
22U_0805_6.3VAM
1
2
PC967
22U_0805_6.3VAM
PC967
22U_0805_6.3VAM
1
2
PC949
1U_0402_6.3V6K
PC949
1U_0402_6.3V6K
12
PC900
10U_0603_4VAM
PC900
10U_0603_4VAM
1
2
PC924
22U_0805_6.3VAM
PC924
22U_0805_6.3VAM
1
2
PC969
22U_0805_6.3VAM
PC969
22U_0805_6.3VAM
1
2
PC955
1U_0402_6.3V6K
PC955
1U_0402_6.3V6K
12
PC952
1U_0402_6.3V6K
PC952
1U_0402_6.3V6K
12
PC940
22U_0805_6.3VAM
PC940
22U_0805_6.3VAM
1
2
PC923
22U_0805_6.3VAM
PC923
22U_0805_6.3VAM
1
2
PC948
1U_0402_6.3V6K
PC948
1U_0402_6.3V6K
12
PC959
1U_0402_6.3V6K
PC959
1U_0402_6.3V6K
12
PC965
22U_0805_6.3VAM
PC965
22U_0805_6.3VAM
1
2
PC938
22U_0805_6.3VAM
PC938
22U_0805_6.3VAM
1
2
PC903
10U_0603_4VAM
PC903
10U_0603_4VAM
1
2
PC942
22U_0805_6.3VAM
PC942
22U_0805_6.3VAM
1
2
PC957
1U_0402_6.3V6K
PC957
1U_0402_6.3V6K
12
PC946
1U_0402_6.3V6K
PC946
1U_0402_6.3V6K
12
PC901
10U_0603_4VAM
PC901
10U_0603_4VAM
1
2
PC947
1U_0402_6.3V6K
PC947
1U_0402_6.3V6K
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
RUN_ON
+3.3V_RUNTPS22966
+5V_RUN
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
CPU
SIO 5048
+5V_ALW
+3.3V_ALW
VDDQ
VCCIO_OUT
+VCCIO_OUT
+1.35V_MEM
PCH
+1.05V_RUN
+1.05V_M
VCCASW
+1.05V_RUN
+1.05V_M
VCC
VCCIO
VCCUSBPLL
V_PROC_IO
VCCCLK
VCCADAC
VCCVRM
+3.3V_RUN
VCCSUS3_3
VCCSUSHDA
+3.3V_ALW_PCH
VCCADACBG3_3
VCC3_3_R30
VCC3_3_R32
VCC3_3
VCCCLK3_3
+1.5V_RUN
+VCC_CORE
ISL95812
IMVP_VR_ON
VCC
+VCC_CORE
RSMRST# PCH_RSMRST#_R
SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_S3#
SIO_SLP_A#
SLP_S5#
SLP_S4#
SLP_S3#
SLP_A#
5
9
RESET_OUT#
SIO_SLP_LAN#
SLP_LAN#
10
SYS_PWROK
PWROK PCH_PWROK
PM_DRAM_PWRGD_R
DRAMPWROK
SM_DRAMPWROK
PM_DRAM_PWRGD_CPU
H_CPUPWRGD PWRGOOD
H_CPUPWRGD
PROCPWRGD
PCH_PLTRST# PLTRST#
CPU_PLTRST#_R PLTRSTIN
4
5
PCH_PWROK
BC BUS
PWRBTN# SIO_PWRBTN#
SIO_SLP_LAN#
SI4164DY
+VCOMP_OUT
VCOMP_OUT
SIO_SLP_S4#
RT8207MZ
+PWR_SRC
DDR
VDDQ
+1.35V_MEM
VTT
1.35V_SUS_PWRGD
0.675V_DDR_VTT_ON
+0.675V_DDR_VTT
+3.3V_SUSTPS22966
SIO_SLP_S4#
+3.3V_ALW
+5V_HDD
MODC_EN
TPS22966
+5V_ALW
+5V_MOD
+PWR_SRC
APL5930 +1.5V_RUN
PCH_ALW_ON
TPS22966
+3.3V_ALW
+3.3V_ALW_PCH
2AC
1BAT
ADAPTER
PCH_RSMRST#
A_ON
TPS51212
+PWR_SRC
Power Button
+5V_ALW
ALWON
TPS51225
EC 5085
ALW_PWRGD_3V_5V
A_ON
+3.3V_ALW
BATTERY
3
6
6
7
+1.05V_M
+3.3V_ALW
TPS22966 +3.3V_M
PM_APWROK
RESET_OUT#
4
SIO_SLP_S5#
+3.3V_ALW
+3.3V_SSD
NVRAM_PWR_EN
TPS22966
+3.3V_ALW
+3.3V_WLAN
AUX_EN_WOWL
TPS22966
+3.3V_ALW
+3.3V_WWAN
3.3V_WWAN_EN
TPS22965
EN_INVPWR
FDC654P
+PWR_SRC
+BL_PWR_SRC
+3.3V_ALW
+LCDVDD
ENVDD_PCH
APL3512
+PWR_SRC
CPU
APWROK
PM_APWROK_R
SIO_SLP_WLAN#
SLP_WLAN#/GPIO29
PCH_DPWROK DPWROK
VCCDSW3_3
+3.3V_ALW
3
2AC
1BAT
8
7
8
16
15
13
13
12
4
11
12
14
6
Timing Diagram for S5 to S0 mode
DGPU_PWR_EN
MXM
11
15
14
1.35V_SUS_PWRGD RT8207
+3.3V_LAN
SIO_SLP_LAN#
SIO_SLP_S3#
SIO_SLP_S4#
PCH
TPS22966
PCH
LCD_VCC_TEST_EN
MXM_ENVDD
EC
MXM
VCCRTC
+RTC_CELL
+3.3_M
VCCSPI
Title
Size Document Numb er Rev
Date: Shee t of
LA-B541P
0.1
Power Sequence
65 67Mond ay, January 13, 20 14
Compal Electronics, Inc.
Title
Size Document Numb er Rev
Date: Shee t of
LA-B541P
0.1
Power Sequence
65 67Mond ay, January 13, 20 14
Compal Electronics, Inc.
Title
Size Document Numb er Rev
Date: Shee t of
LA-B541P
0.1
Power Sequence
65 67Mond ay, January 13, 20 14
Compal Electronics, Inc.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
V ersion Change L ist ( P. I. R . L ist )
V ersion Change L ist ( P. I. R . L ist )V ersion Change L ist ( P. I. R . L ist )
V ersion Change L ist ( P. I. R . L ist )
Item
ItemItem
Item Issu e D escription
Issu e D escriptionIssu e D escription
Issu e D escriptionD ate
D ateD ate
D ate R equ est
R eq uestR eq uest
R eq uest
O w n er
O w n erO w ner
O w n er Solu tion D escrip tion
Solu tion D escrip tionSolution D escription
Solu tion D escrip tion R ev.
R ev .R ev .
R ev .P a ge#
P a ge#P a ge#
P a ge# T it le
TitleT itle
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
EE P.I.R (1/4)
66 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
EE P.I.R (1/4)
66 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
EE P.I.R (1/4)
66 67Monday, January 13, 2014
Compal Electronics, Inc.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
V ersion Change L ist ( P. I. R . L ist )
V ersion Change L ist ( P. I. R . L ist )V ersion Change L ist ( P. I. R . L ist )
V ersion Change L ist ( P. I. R . L ist )
Item
ItemItem
Item Issu e D escription
Issu e D escriptionIssu e D escription
Issu e D escriptionD ate
D ateD ate
D ate R equ est
R eq uestR eq uest
R eq uest
O w n er
O w n erO w ner
O w n er Solu tion D escrip tion
Solu tion D escrip tionSolution D escription
Solu tion D escrip tion R ev.
R ev .R ev .
R ev .P a ge#
P a ge#P a ge#
P a ge# T it le
TitleT itle
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
PWR P.I.R (1/1)
67 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
PWR P.I.R (1/1)
67 67Monday, January 13, 2014
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-B541P
0.1
PWR P.I.R (1/1)
67 67Monday, January 13, 2014
Compal Electronics, Inc.
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