Getac Technology V110N RFID and NFC Module User Manual 1
Getac Technology Corporation RFID and NFC Module 1
Contents
- 1. User manual 1
- 2. User manual 2
User manual 1
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| Document Description | User manual 1 |
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| Date Submitted | 2016-01-28 00:00:00 |
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| Document Title | User manual 1 |
Product Folder Sample & Buy Tools & Software Technical Documents Support & Community Reference Design TRF7970A SLOS743K – AUGUST 2011 – REVISED APRIL 2014 TRF7970A Multiprotocol Fully Integrated 13.56-MHz RFID and Near Field Communication (NFC) Transceiver IC 1 Device Overview 1.1 Features • Supports Near Field Communication (NFC) Standards NFCIP-1 (ISO/IEC 18092) and NFCIPತ2 (ISO/IEC 21481) • Completely Integrated Protocol Handling for ISO15693, ISO18000-3, ISO14443A/B, and FeliCa™ • Integrated Encoders, Decoders, and Data Framing for NFC Initiator, Active and Passive Target Operation for All Three Bit Rates (106 kbps, 212 kbps, 424 kbps) and Card Emulation • RF Field Detector With Programmable Wake-Up Levels for NFC Passive Transponder Emulation Operation • RF Field Detector for NFC Physical Collision Avoidance. • Integrated State Machine for ISO14443A Anticollision (Broken Bytes) Operation (Transponder Emulation or NFC Passive Target) • Input Voltage Range: 2.7 VDC to 5.5 VDC 1.2 • • • • Applications Mobile Devices (Tablets, Handsets) Secure Pairing ( Bluetooth®, Wi-Fi®, Other Paired Wireless Networks) Public Transport or Event Ticketing Passport or Payment (POS) Reader Systems 1.3 • Programmable Output Power: +20 dBm (100 mW), +23 dBm (200 mW) • Programmable I/O Voltage Levels From 1.8 VDC to 5.5 VDC • Programmable System Clock Frequency Output (RF, RF/2, RF/4) from 13.56-MHz or 27.12-MHz Crystal or Oscillator • Integrated Voltage Regulator Output for Other System Components (MCU, Peripherals, Indicators), 20 mA (Max) • Programmable Modulation Depth • Dual Receiver Architecture With RSSI for Elimination of "Read Holes" and Adjacent Reader System or Ambient In-Band Noise Detection • Programmable Power Modes for Ultra Low-Power System Design (Power Down <1 µA) • Parallel or SPI Interface (With 127-Byte FIFO) • Temperature Range: –40°C to 110°C • 32-Pin QFN Package (5 mm x 5 mm) • • • • • Short-Range Wireless Communication Tasks (Firmware Updates) Product Identification or Authentication Medical Equipment or Consumables Access Control, Digital Door Locks Sharing of Electronic Business Cards Description The TRF7970A device is an integrated analog front end and data-framing device for a 13.56-MHz RFID and Near Field Communication (NFC) system. Built-in programming options make the device suitable for a wide range of applications for proximity and vicinity identification systems. The device can perform in one of three modes: RFID and NFC reader, NFC peer, or in card emulation mode. Built-in user-configurable programming options make the device suitable for a wide range of applications. The TRF7970A device is configured by selecting the desired protocol in the control registers. Direct access to all control registers allows fine tuning of various reader parameters as needed. Documentation, reference designs, EVM, and source code TI MSP430™ MCUs or ARM® MCUs are available. Device Information PART NUMBER TRF7970ARHB PACKAGE BODY SIZE VQFN (32) 5 mm x 5 mm An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TRF7970A SLOS743K – AUGUST 2011 – REVISED APRIL 2014 1.4 www.ti.com Functional Block Diagram Figure 1-1 shows the block diagram. VDD_I/O MUX RX_IN1 PHASE & AMPLITUDE DETECTOR GAIN RSSI (AUX) RF LEVEL DETECTOR RX_IN2 PHASE & AMPLITUDE DETECTOR RSSI (MAIN) I/O_1 GAIN FILTER & AGC ISO PROTOCOL HANDLING TRANSMITTER ANALOG FRONT END STATE CONTROL LOGIC [CONTROL REGISTERS & COMMAND LOGIC] DIGITIZER VDD_PA TX_OUT I/O_0 FRAMING MCU INTERFACE I/O_2 I/O_3 LEVEL SHIFTER RSSI (EXTERNAL) LOGIC 127-BYTE FIFO I/O_6 I/O_7 SYS_CLK DATA _CLK VIN SERIAL CONVERSION CRC & PARITY VSS_PA I/O_5 IRQ DECODER BIT FRAMING I/O_4 VDD_A BAND_GAP EN VSS_A EN2 DIGITAL CONTROL STATE MACHINE ASK/OOK MOD OSC_IN OSC_OUT VDD_RF VOLTAGE SUPPLY REGULATOR SYSTEMS (SUPPLY REGULATORS AND REFERENCE VOLTAGES) VSS_RF VDD_X VSS CRYSTAL OR OSCILLATOR TIMING SYSTEM VSS_D Figure 1-1. Block Diagram Device Overview Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7970A TRF7970A www.ti.com SLOS743K – AUGUST 2011 – REVISED APRIL 2014 Table of Contents Device Overview ......................................... 1 1.1 Features .............................................. 1 1.2 Applications ........................................... 1 1.3 Description ............................................ 1 1.4 Functional Block Diagram ............................ 2 Revision History ......................................... 4 Device Characteristics .................................. 5 Terminal Configuration and Functions .............. 6 4.1 Pin Assignments ...................................... 6 4.2 Terminal Functions ................................... 7 ............................................ 9 .......................... 9 5.2 Recommended Operating Conditions ................ 9 5.3 Electrical Characteristics ............................ 10 5.4 Handling Ratings .................................... 11 5.5 Thermal Characteristics ............................. 11 5.6 Switching Characteristics ........................... 11 Detailed Description ................................... 12 6.1 Overview ............................................ 12 6.2 System Block Diagram .............................. 15 6.3 Power Supplies ...................................... 15 6.4 Receiver – Analog Section .......................... 21 6.5 Receiver – Digital Section ........................... 22 6.6 Oscillator Section ................................... 27 6.7 Transmitter – Analog Section ....................... 28 Specifications 5.1 6.8 6.9 Transmitter – Digital Section ........................ 28 Transmitter – External Power Amplifier and Subcarrier Detector ................................. 29 6.10 6.11 TRF7970A IC Communication Interface ............ 30 Special Direct Mode for Improved MIFARE™ Compatibility ......................................... 48 6.12 NFC Modes.......................................... 48 6.13 Direct Commands from MCU to Reader ............ 51 6.14 Register Description ................................. 55 Application Schematic and Layout Considerations.......................................... 75 7.1 Absolute Maximum Ratings 7.2 TRF7970A Reader System Using Parallel Microcontroller Interface............................. 75 TRF7970A Reader System Using SPI With SS Mode ................................................ 76 .............................. ...... 7.5 Reader Antenna Design Guidelines ................ Device and Documentation Support ............... 8.1 Documentation Support ............................. 8.2 Community Resources .............................. 8.3 Trademarks.......................................... 8.4 Electrostatic Discharge Caution ..................... 8.5 Glossary ............................................. 7.3 Layout Considerations 77 7.4 Impedance Matching TX_Out (Pin 5) to 50 77 79 80 80 80 80 80 80 Mechanical Packaging and Orderable Information .............................................. 80 9.1 Packaging Information .............................. Table of Contents Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7970A 80 TRF7970A SLOS743K – AUGUST 2011 – REVISED APRIL 2014 www.ti.com 2 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision J (February 2014) to Revision K • • • • • • • • • • • • • • • • • • • • • • • • Page Changed Figure 1-1 to show 127-byte FIFO ...................................................................................... 2 Moved Section 3 ...................................................................................................................... 5 Changed title of Section 4 .......................................................................................................... 6 Changed title of Section 5 ........................................................................................................... 9 Added ASK/OOK and MOD to VIL and VIH ........................................................................................ 9 Moved Section 5.3 .................................................................................................................. 10 Changed VDD_A TYP value from 3.5 V to 3.4 V ................................................................................. 10 Moved Section 5.4 .................................................................................................................. 11 Added V(ESD) MIN values, test specifications, and notes ....................................................................... 11 Changed title of Section 5.5 from Dissipation Ratings to Thermal Characteristics ......................................... 11 Moved Section 5.6 .................................................................................................................. 11 Changed title of Section 6 .......................................................................................................... 12 Moved previous Section 3, Device Overview, to Section 6.1.................................................................. 12 Changed from "By default, the AGC is frozen after..." to "By default, the AGC window comparator is set after..." ... 21 Changed from "TX Pulse Length Control register (0x05)" to "TX Pulse Length Control register (0x06)" ............... 28 Changed from "18.8 s" to "18.8 µs" in the sentence that starts with "If the register contains all zeros..."............... 28 Changed Table 6-18 to match Table 6-43 ....................................................................................... 50 Changed command 0x18 to "Test internal RF" ................................................................................. 51 Changed command 0x19 to "Test external RF" ................................................................................ 51 Moved Section 6.14 ................................................................................................................. 55 Changed the sentence that starts "The AGC action is fast..." from "finishes after four subcarrier pulses" to "finishes within eight subcarrier pulses" ......................................................................................... 64 Moved Section 7..................................................................................................................... 75 Deleted previous Section 10, System Design, and moved contents to Section 7.3 through Section 7.5 ............... 77 Removed references to figure numbers in Figure 7-3 .......................................................................... 78 Revision History Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7970A TRF7970A www.ti.com SLOS743K – AUGUST 2011 – REVISED APRIL 2014 3 Device Characteristics Table 3-1 shows the supported modes of operation for the TRF7970A device. Table 3-1. Supported Modes of Operation P2P Initiator or Reader/Writer (1) Technology Bit rate (kbps) NFC-A/B (ISO14443A/B) 106, 212, 424, 848 (1) Card Emulation P2P Target Technology Bit rate (kbps) Technology Bit rate (kbps) NFC-A/B 106 NFC-A 106 NFC-F (JIS: X6319-4) 212, 424 N/A N/A NFC-F 212, 424 NFC-V (ISO15693) 6.7, 26.7 N/A N/A N/A N/A 848 kbps only applies to reader/writer mode. Device Characteristics Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7970A TRF7970A SLOS743K – AUGUST 2011 – REVISED APRIL 2014 www.ti.com 4 Terminal Configuration and Functions 4.1 Pin Assignments Figure 4-1 shows the pin assignments for the 32-pin RHB package. VDD_X OSC_IN OSC_OUT VSS_D EN SYS_CLK DATA_CLK EN2 32 31 30 29 28 27 26 25 VDD_A 24 I/0_7 VIN 23 I/0_6 VDD_RF 22 I/0_5 VDD_PA 21 I/0_4 TX_OUT 20 I/0_3 VSS_PA 19 I/0_2 VSS_RX 18 I/0_1 RX_IN1 17 I/0_0 Pad 12 13 14 15 ASK/OOK IRQ MOD VSS_A 16 VDD_I/O 11 BG RX_IN2 10 VSS Figure 4-1. 32-Pin RHB Package (Top View) Terminal Configuration and Functions Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7970A TRF7970A www.ti.com 4.2 SLOS743K – AUGUST 2011 – REVISED APRIL 2014 Terminal Functions Table 4-1 describes the signals. Table 4-1. Terminal Functions TERMINAL NAME NO. TYPE (1) DESCRIPTION VDD_A OUT Internal regulated supply (2.7 V to 3.4 V) for analog circuitry VIN SUP External supply input to chip (2.7 V to 5.5 V) VDD_RF OUT Internal regulated supply (2.7 V to 5 V), normally connected to VDD_PA (pin 4) VDD_PA INP Supply for PA; normally connected externally to VDD_RF (pin 3) TX_OUT OUT RF output (selectable output power, 100 mW or 200 mW, with VDD = 5 V) VSS_PA SUP Negative supply for PA; normally connected to circuit ground VSS_RX SUP Negative supply for RX inputs; normally connected to circuit ground RX_IN1 INP Main RX input RX_IN2 INP Auxiliary RX input VSS 10 SUP Chip substrate ground BAND_GAP 11 OUT Bandgap voltage (VBG = 1.6 V); internal analog voltage reference Selection between ASK and OOK modulation (0 = ASK, 1 = OOK) for Direct Mode 0 or 1. ASK/OOK 12 BID IRQ 13 OUT Interrupt request INP External data modulation input for Direct Mode 0 or 1 OUT Subcarrier digital data output (see registers 0x1A and 0x1B) Can be configured as an output to provide the received analog signal output. MOD 14 VSS_A 15 SUP Negative supply for internal analog circuits; connected to GND VDD_I/O 16 INP Supply for I/O communications (1.8 V to VIN) level shifter. VIN should be never exceeded. I/O_0 17 BID I/O pin for parallel communication I/O_1 18 BID I/O_2 19 BID I/O_3 20 BID I/O_4 21 BID I/O_5 22 BID I/O pin for parallel communication I/O pin for parallel communication TX Enable (in Special Direct Mode) I/O pin for parallel communication TX Data (in Special Direct Mode) I/O pin for parallel communication Slave Select signal in SPI mode I/O pin for parallel communication Data clock output in Direct Mode 1 and Special Direct Mode I/O pin for parallel communication I/O_6 23 BID MISO for serial communication (SPI) Serial bit data output in Direct Mode 1 or subcarrier signal in Direct Mode 0 I/O pin for parallel communication. I/O_7 24 BID EN2 25 INP Selection of power down mode. If EN2 is connected to VIN, then VDD_X is active during power down mode 2 (for example, to supply the MCU). DATA_CLK 26 INP Data Clock input for MCU communication (parallel and serial) OUT If EN = 1 (EN2 = don't care) the system clock for MCU is configured. Depending on the crystal that is used, options are as follows (see register 0x09): 13.56-MHz crystal: Off, 3.39 MHz, 6.78 MHz, or 13.56 MHz 27.12-MHz crystal: Off, 6.78 MHz, 13.56 MHz, or 27.12 MHz SYS_CLK 27 MOSI for serial communication (SPI) If EN = 0 and EN2 = 1, then system clock is set to 60 kHz EN 28 INP Chip enable input (If EN = 0, then chip is in sleep or power-down mode). VSS_D 29 SUP Negative supply for internal digital circuits (1) SUP = Supply, INP = Input, BID = Bidirectional, OUT = Output Terminal Configuration and Functions Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7970A TRF7970A SLOS743K – AUGUST 2011 – REVISED APRIL 2014 www.ti.com Table 4-1. Terminal Functions (continued) TERMINAL NAME OSC_OUT NO. 30 TYPE (1) DESCRIPTION OUT Crystal or oscillator output INP Crystal or oscillator input OUT Crystal oscillator output OSC_IN 31 VDD_X 32 OUT Internally regulated supply (2.7 V to 3.4 V) for digital circuit and external devices (for example, MCU) PAD SUP Chip substrate ground Thermal Pad Terminal Configuration and Functions Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7970A TRF7970A www.ti.com SLOS743K – AUGUST 2011 – REVISED APRIL 2014 5 Specifications 5.1 Absolute Maximum Ratings (1) (2) over operating free-air temperature range (unless otherwise noted) VIN Input voltage range IIN Maximum current VIN TJ (1) (2) (3) 5.2 -0.3 V to 6 V 150 mA Maximum operating virtual junction temperature Any condition 140°C Continuous operation, long-term reliability (3) 125°C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Operating Conditions are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to substrate ground terminal VSS. The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may result in reduced reliability or lifetime of the device. Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN TYP MAX UNIT VIN Operating input voltage 2.7 5.5 TA Operating ambient temperature -40 25 110 °C TJ Operating virtual junction temperature -40 25 125 °C VIL Input voltage - logic low I/O lines, IRQ, SYS_CLK, DATA_CLK, EN, EN2, ASK/OOK, MOD VIH Input voltage threshold, logic high I/O lines, IRQ, SYS_CLK, DATA_CLK, EN, EN2, ASK/OOK, MOD 0.2 x VDD_I/O 0.8 x VDD_I/O Specifications Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7970A TRF7970A SLOS743K – AUGUST 2011 – REVISED APRIL 2014 5.3 www.ti.com Electrical Characteristics TYP operating conditions are TA = 25°C, VIN = 5 V, full-power mode (unless otherwise noted) MIN and MAX operating conditions are over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.5 µA IPD1 Supply current in Power Down Mode 1 All building blocks disabled, including supplyvoltage regulators; measured after 500-ms settling time (EN = 0, EN2 = 0) IPD2 Supply current in Power Down Mode 2 (Sleep Mode) The SYS_CLK generator and VDD_X remain active to support external circuitry; measured after 100-ms settling time (EN = 0, EN2 = 1) 120 200 µA ISTBY Supply current in stand-by mode Oscillator running, supply-voltage regulators in low-consumption mode (EN = 1, EN2 = x) 1.9 3.5 mA ION1 Supply current without antenna driver current Oscillator, regulators, RX and AGC active, TX is off 10.5 14 mA ION2 Supply current – TX (half power) Oscillator, regulators, RX and AGC and TX active, POUT = 100 mW 70 78 mA ION3 Supply current – TX (full power) Oscillator, regulators, RX and AGC and TX active, POUT = 200 mW 130 150 mA VPOR Power-on reset voltage Input voltage at VIN 1.4 2.6 VBG Bandgap voltage (pin 11) Internal analog reference voltage 1.5 1.6 1.7 VDD_A Regulated output voltage for analog circuitry (pin 1) VIN = 5 V 3.1 3.4 3.8 VDD_X Regulated supply for external circuitry Output voltage pin 32, VIN = 5 V 3.1 3.4 3.8 IVDD_Xmax Maximum output current of VDD_X Output current pin 32, VIN = 5 V 20 mA RRFOUT Antenna driver output resistance RRFIN RX_IN1 and RX_IN2 input resistance VRF_INmax Maximum RF input voltage at RX_IN1 and RX_IN2 VRF_INmax should not exceed VIN VRF_INmin Minimum RF input voltage at RX_IN1 and RX_IN2 (input sensitivity) (2) fSUBCARRIER= 424 kHz 1.4 2.5 fSUBCARRIER = 848 kHz 2.1 fSYS_CLK SYS_CLK frequency In power mode 2, EN = 0, EN2 = 1 60 120 fC Carrier frequency Defined by external crystal tCRYSTAL Crystal run-in time Time until oscillator stable bit is set (register 0x0F) (3) fD_CLKmax Maximum DATA_CLK frequency (4) Depends on capacitive load on the I/O lines, recommendation is 2 MHz (4) ROUT RSYS_CLK (1) (2) (3) (4) 10 (1) Half-power mode, VIN = 2.7 V to 5.5 V 12 Full-power mode, VIN = 2.7 V to 5.5 V 10 20 3.5 25 kȍ Vpp 13.56 mVpp kHz MHz ȍ ms 10 MHz Output resistance I/O_0 to I/O_7 500 800 ȍ Output resistance RSYS_CLK 200 400 ȍ Antenna driver output resistance Measured with subcarrier signal at RX_IN1 or RX_IN2 and measured the digital output at MOD pin with register 0x1A bit 6 = 1. Depends on the crystal parameters and components Recommended DATA_CLK speed is 2 MHz. Higher data clock depends on the capacitive load. Maximum SPI clock speed should not exceed 10 MHz. This clock speed is acceptable only when external capacitive load is less than 30 pF. MISO driver has a typical output resistance of 400 ȍ (12-ns time constant when 30-pF load used). Specifications Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7970A TRF7970A www.ti.com 5.4 SLOS743K – AUGUST 2011 – REVISED APRIL 2014 Handling Ratings TSTG Storage temperature range V(ESD) Electrostatic discharge (1) (2) MAX UNIT -55 150 °C Human-Body Model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) -2 kV Charged-Device Model (CDM), per JEDEC specification JESD22-C101, all pins (2) -500 500 Machine Model (MM) -200 200 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as 2 kV may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 500 V may actually have higher performance. 5.5 (1) (2) MIN Thermal Characteristics PACKAGE șJC șJA (1) RHB (32 pin) 31°C/W 36.4°C/W POWER RATING (2) TA 25°C TA 85°C 2.7 W 1.1 W This data was taken using the JEDEC standard high-K test PCB. Power rating is determined with a junction temperature of 125°C. This is the point where distortion starts to increase substantially. Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and longterm reliability. 5.6 Switching Characteristics TYP operating conditions are TA = 25°C, VIN = 5 V, full-power mode (unless otherwise noted) MIN and MAX operating conditions are over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 250 62.5 50 UNIT tLO/HI DATA_CLK time high or low, one half of DATA_CLK at 50% duty cycle tSTE,LEAD Slave select lead time, slave select low to clock 200 ns tSTE,LAG Slave select lag time, last clock to slave select high 200 ns tSTE,DIS Slave select disable time, slave select rising edge to next slave select falling edge tSU,SI tHD,SI Depends on capacitive load on the I/O lines (1) ns 300 ns MOSI input data setup time 15 ns MOSI input data hold time 15 ns tSU,SO MISO input data setup time 15 ns tHD,SO MISO input data hold time 15 tVALID,SO MISO output data valid time (1) DATA_CLK edge to MISO valid, CL 30 pF 30 ns 50 75 ns Recommended DATA_CLK speed is 2 MHz. Higher data clock depends on the capacitive load. Maximum SPI clock speed should not exceed 10 MHz. This clock speed is acceptable only when external capacitive load is less than 30 pF. MISO driver has a typical output resistance of 400 ȍ (12-ns time constant when 30-pF load used). Specifications Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TRF7970A 11 Federal Communication Commission Interference Statement This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one of the following measures: Reorient or relocate the receiving antenna. Increase the separation between the equipment and receiver. Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. Consult the dealer or an experienced radio/TV technician for help. FCC Caution: Any changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate this equipment. This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. Radiation Exposure Statement: The product is a low power device and its output power is lower than FCC SAR exemption level. This module can be used with Product name: V110. This device is intended only for OEM integrators under the following conditions: 1) The transmitter module may not be co-located with any other transmitter or 2) antenna. The co-transmitting with other radio will need a separate evaluation. Module approval valid only when this module is installed in the tested host “Product name: V110”. As long as 2 conditions above are met, further transmitter test will not be required. However, the OEM integrator is still responsible for testing their end-product for any additional compliance requirements required with this module installed IMPORTANT NOTE: In the event that these conditions cannot be met (for example certain laptop configurations or co-location with another transmitter), then the FCC authorization is no longer considered valid and the FCC ID cannot be used on the final product. In these circumstances, the OEM integrator will be responsible for re-evaluating the end product (including the transmitter) and obtaining a separate FCC authorization. End Product Labeling The final end product must be labeled in a visible area with the following: “Contains FCC ID: QYLV110N”. The grantee's FCC ID can be used only when all FCC compliance requirements are met. Manual Information to the End User The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module in the user’s manual of the end product which integrates this module. The end user manual shall include all required regulatory information/warning as show in this manual.
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