Renesas H8S 2111B Users Manual H8S/2111B Hardware

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Revision Date: Ma
y
. 14
,
2004
16 H8S/2111B
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8S Family / H8S/2100 Series
H8S/2111B HD64F2111B
Rev.1.00
REJ09B0163-0100Z
Rev. 1.00, 05/04, page ii of xxxiv
Rev. 1.00, 05/04, page iii of xxxiv
1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corp. product best suited to the customer's application; they do not convey any license
under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or
a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-
party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corp. without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or
an authorized Renesas Technology Corp. product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising
from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means,
including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data,
diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total
system before making a final decision on the applicability of the information and products. Renesas
Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the
information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or
system that is used under circumstances in which human life is potentially at stake. Please contact
Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when
considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in
whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must
be exported under a license from the Japanese government and cannot be imported into a country
other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products
contained therein.
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and
more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.
Keep safety first in your circuit designs!
Notes regarding these materials
Rev. 1.00, 05/04, page iv of xxxiv
General Precautions on Handling of Product
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass-
through current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note: When power is first supplied, the product's state is undefined.
The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.
4. Prohibition of Access to Undefined or Reserved Addresses
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system's
operation is not guaranteed if they are accessed.
Rev. 1.00, 05/04, page v of xxxiv
Configuration of This Manual
This manual comprises the following items:
1. General Precautions on Handling of Product
2. Configuration of This Manual
3. Preface
4. Contents
5. Overview
6. Description of Functional Modules
CPU and System-Control Modules
On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
10. Main Revisions and Additions in this Edition (only for revised versions)
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
11. Index
Rev. 1.00, 05/04, page vi of xxxiv
Preface
The H8S/2111B is a microcomputer (MCU) made up of the H8S/2000 CPU employing Renesas
Technology's original architecture as its core, and the peripheral functions required to configure a
system.
The H8S/2000 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a
simple and optimized instruction set for high-speed operation. The H8S/2000 CPU can handle a
16-Mbyte linear address space.
This LSI is equipped with ROM, RAM, a 16-bit free-running timer (FRT), an 8-bit timer (TMR),
a watchdog timer (WDT), a serial communication interface (SCI), a keyboard buffer controller, a
host interface (LPC), an I2C bus interface (IIC), and I/O ports as on-chip peripheral modules,
required for system configuration.
A flash memory (F-ZTATTM*) version is available for this LSI's ROM. This provides flexibility as
it can be reprogrammed in no time to cope with all situations from the early stages of mass
production to full-scale mass production. This is particularly applicable to application devices with
specifications that will most probably change.
Note: * F-ZTATTM is a trademark of Renesas Technology Corp.
Target Users: This manual was written for users who will be using the H8S/2111B in the design
of application systems. Target users are expected to understand the fundamentals
of electrical circuits, logical circuits, and microcomputers.
Objective: This manual was written to explain the hardware functions and electrical
characteristics of the H8S/2111B to the target users.
Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a
detailed description of the instruction set.
Notes on reading this manual:
In order to understand the overall functions of the chip
Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.
In order to understand the details of the CPU's functions
Read the H8S/2600 Series, H8S/2000 Series Programming Manual.
In order to understand the details of a register when its name is known
Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in section 21,
List of Registers.
Rev. 1.00, 05/04, page vii of xxxiv
Rules: Register name: The following notation is used for cases when the same or a
similar function, e.g. serial communication interface, is
implemented on more than one channel:
XXX_N (XXX is the register name and N is the channel
number)
Bit order: The MSB is on the left and the LSB is on the right.
Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx.
Signal notation: An overbar is added to a low-active signal: xxxx
Related Manuals: The latest versions of all related manuals are available from our web site.
Please ensure you have the latest versions of all documents you require.
http://www.renesas.com/eng/
H8S/2111B manuals:
Document Title Document No.
H8S/2111B Hardware Manual This manual
H8S/2600 Series, H8S/2000 Series Programming Manual REJ09B0139
User's manuals for development tools:
Document Title Document No.
H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor
User's Manual
REJ10B0058
Microcomputer Development Environment System H8S, H8/300 Series
Simulator/Debugger User's Manual
ADE-702-282
H8S, H8/300 Series High-performance Embedded Workshop 3 Tutorial REJ10B0024
H8S, H8/300 Series High-performance Embedded Workshop 3
User's Manual
REJ10B0026
Rev. 1.00, 05/04, page viii of xxxiv
Rev. 1.00, 05/04, page ix of xxxiv
Contents
Section 1 Overview............................................................................................1
1.1 Features............................................................................................................................. 1
1.2 Internal Block Diagram..................................................................................................... 2
1.3 Pin Description.................................................................................................................. 3
1.3.1 Pin Arrangement.................................................................................................. 3
1.3.2 Pin Functions in Each Operating Mode ............................................................... 4
1.3.3 Pin Functions ....................................................................................................... 9
Section 2 CPU....................................................................................................13
2.1 Features............................................................................................................................. 13
2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU .................................. 14
2.1.2 Differences from H8/300 CPU ............................................................................ 15
2.1.3 Differences from H8/300H CPU..........................................................................15
2.2 CPU Operating Modes...................................................................................................... 16
2.2.1 Normal Mode....................................................................................................... 16
2.2.2 Advanced Mode................................................................................................... 18
2.3 Address Space...................................................................................................................20
2.4 Register Configuration...................................................................................................... 21
2.4.1 General Registers................................................................................................. 22
2.4.2 Program Counter (PC) ......................................................................................... 23
2.4.3 Extended Control Register (EXR) ....................................................................... 23
2.4.4 Condition-Code Register (CCR).......................................................................... 24
2.4.5 Initial Register Values.......................................................................................... 25
2.5 Data Formats..................................................................................................................... 26
2.5.1 General Register Data Formats............................................................................ 26
2.5.2 Memory Data Formats ......................................................................................... 28
2.6 Instruction Set................................................................................................................... 29
2.6.1 Table of Instructions Classified by Function ....................................................... 30
2.6.2 Basic Instruction Formats .................................................................................... 39
2.7 Addressing Modes and Effective Address Calculation..................................................... 40
2.7.1 Register Direct—Rn ............................................................................................ 40
2.7.2 Register Indirect—@ERn.................................................................................... 40
2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn).............. 41
2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn.. 41
2.7.5 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32.................................... 41
2.7.6 Immediate—#xx:8, #xx:16, or #xx:32................................................................. 42
2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC)....................................42
2.7.8 Memory Indirect—@@aa:8 ................................................................................ 43
2.7.9 Effective Address Calculation ............................................................................. 44
Rev. 1.00, 05/04, page x of xxxiv
2.8 Processing States...............................................................................................................46
2.9 Usage Notes...................................................................................................................... 48
2.9.1 Note on TAS Instruction Usage........................................................................... 48
2.9.2 Note on STM/LDM Instruction Usage ................................................................ 48
2.9.3 Note on Bit Manipulation Instructions ................................................................ 48
2.9.4 EEPMOV Instruction........................................................................................... 49
Section 3 MCU Operating Modes .....................................................................51
3.1 MCU Operating Mode Selection ...................................................................................... 51
3.2 Register Descriptions........................................................................................................ 52
3.2.1 Mode Control Register (MDCR) ......................................................................... 52
3.2.2 System Control Register (SYSCR)...................................................................... 53
3.2.3 Serial Timer Control Register (STCR) ................................................................ 55
3.3 Operating Mode Descriptions ........................................................................................... 56
3.3.1 Mode 2................................................................................................................. 56
3.3.2 Mode 3................................................................................................................. 56
3.4 Address Map.....................................................................................................................57
Section 4 Exception Handling...........................................................................59
4.1 Exception Handling Types and Priority............................................................................ 59
4.2 Exception Sources and Exception Vector Table............................................................... 60
4.3 Reset ................................................................................................................................. 61
4.3.1 Reset Exception Handling ................................................................................... 61
4.3.2 Interrupts after Reset............................................................................................ 62
4.3.3 On-Chip Peripheral Modules after Reset is Cancelled ........................................ 62
4.4 Interrupt Exception Handling ........................................................................................... 63
4.5 Trap Instruction Exception Handling................................................................................ 63
4.6 Stack Status after Exception Handling.............................................................................. 64
4.7 Usage Note........................................................................................................................ 65
Section 5 Interrupt Controller............................................................................67
5.1 Features............................................................................................................................. 67
5.2 Input/Output Pins.............................................................................................................. 68
5.3 Register Descriptions........................................................................................................ 69
5.3.1 Interrupt Control Registers A to C (ICRA to ICRC) ........................................... 69
5.3.2 Address Break Control Register (ABRKCR) ...................................................... 70
5.3.3 Break Address Registers A to C (BARA to BARC)............................................ 71
5.3.4 IRQ Sense Control Registers (ISCRH, ISCRL)................................................... 72
5.3.5 IRQ Enable Register (IER) .................................................................................. 73
5.3.6 IRQ Status Register (ISR).................................................................................... 73
5.3.7 Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR)
Wake-Up Event Interrupt Mask Register (WUEMRB) ....................................... 73
5.4 Interrupt Sources...............................................................................................................76
Rev. 1.00, 05/04, page xi of xxxiv
5.4.1 External Interrupts ............................................................................................... 76
5.4.2 Internal Interrupts ................................................................................................ 77
5.5 Interrupt Exception Handling Vector Table...................................................................... 78
5.6 Interrupt Control Modes and Interrupt Operation ............................................................. 80
5.6.1 Interrupt Control Mode 0..................................................................................... 80
5.6.2 Interrupt Control Mode 1..................................................................................... 82
5.6.3 Interrupt Exception Handling Sequence .............................................................. 85
5.6.4 Interrupt Response Times .................................................................................... 86
5.7 Address Break...................................................................................................................87
5.7.1 Features................................................................................................................ 87
5.7.2 Block Diagram.....................................................................................................87
5.7.3 Operation ............................................................................................................. 88
5.7.4 Usage Notes ......................................................................................................... 88
5.8 Usage Notes ...................................................................................................................... 90
5.8.1 Conflict between Interrupt Generation and Disabling ......................................... 90
5.8.2 Instructions that Disable Interrupts...................................................................... 91
5.8.3 Interrupts during Execution of EEPMOV Instruction.......................................... 91
5.8.4 IRQ Status Register (ISR).................................................................................... 91
Section 6 Bus Controller (BSC).........................................................................93
6.1 Register Descriptions ........................................................................................................ 93
6.1.1 Bus Control Register (BCR) ................................................................................ 93
6.1.2 Wait State Control Register (WSCR) .................................................................. 94
Section 7 I/O Ports.............................................................................................95
7.1 Port 1................................................................................................................................. 100
7.1.1 Port 1 Data Direction Register (P1DDR)............................................................. 100
7.1.2 Port 1 Data Register (P1DR)................................................................................ 100
7.1.3 Port 1 Pull-Up MOS Control Register (P1PCR).................................................. 101
7.1.4 Pin Functions ....................................................................................................... 101
7.1.5 Port 1 Input Pull-Up MOS................................................................................... 102
7.2 Port 2................................................................................................................................. 102
7.2.1 Port 2 Data Direction Register (P2DDR)............................................................. 102
7.2.2 Port 2 Data Register (P2DR)) .............................................................................. 103
7.2.3 Port 2 Pull-Up MOS Control Register (P2PCR).................................................. 103
7.2.4 Pin Functions ....................................................................................................... 103
7.2.5 Port 2 Input Pull-Up MOS................................................................................... 104
7.3 Port 3................................................................................................................................. 104
7.3.1 Port 3 Data Direction Register (P3DDR)............................................................. 104
7.3.2 Port 3 Data Register (P3DR)................................................................................ 105
7.3.3 Port 3 Pull-Up MOS Control Register (P3PCR).................................................. 105
7.3.4 Pin Functions ....................................................................................................... 106
7.3.5 Port 3 Input Pull-Up MOS................................................................................... 106
Rev. 1.00, 05/04, page xii of xxxiv
7.4 Port 4................................................................................................................................. 107
7.4.1 Port 4 Data Direction Register (P4DDR)............................................................. 107
7.4.2 Port 4 Data Register (P4DR) ............................................................................... 107
7.4.3 Pin Functions ....................................................................................................... 108
7.5 Port 5................................................................................................................................. 110
7.5.1 Port 5 Data Direction Register (P5DDR)............................................................. 110
7.5.2 Port 5 Data Register (P5DR) ............................................................................... 110
7.5.3 Pin Functions ....................................................................................................... 111
7.6 Port 6................................................................................................................................. 112
7.6.1 Port 6 Data Direction Register (P6DDR)............................................................. 112
7.6.2 Port 6 Data Register (P6DR) ............................................................................... 113
7.6.3 Port 6 Pull-Up MOS Control Register (KMPCR) ............................................... 113
7.6.4 System Control Register 2 (SYSCR2)................................................................. 114
7.6.5 Pin Functions ....................................................................................................... 114
7.6.6 Port 6 Input Pull-Up MOS................................................................................... 116
7.7 Port 7................................................................................................................................. 117
7.7.1 Port 7 Input Data Register (P7PIN) ..................................................................... 117
7.7.2 Pin Functions ....................................................................................................... 117
7.8 Port 8................................................................................................................................. 118
7.8.1 Port 8 Data Direction Register (P8DDR)............................................................. 118
7.8.2 Port 8 Data Register (P8DR) ............................................................................... 118
7.8.3 Pin Functions ....................................................................................................... 119
7.9 Port 9................................................................................................................................. 122
7.9.1 Port 9 Data Direction Register (P9DDR)............................................................. 122
7.9.2 Port 9 Data Register (P9DR) ............................................................................... 122
7.9.3 Pin Functions ....................................................................................................... 123
7.10 Port A................................................................................................................................ 125
7.10.1 Port A Data Direction Register (PADDR)........................................................... 125
7.10.2 Port A Output Data Register (PAODR)............................................................... 125
7.10.3 Port A Input Data Register (PAPIN) ................................................................... 126
7.10.4 Pin Functions ....................................................................................................... 126
7.10.5 Port A Input Pull-Up MOS .................................................................................. 128
7.11 Port B................................................................................................................................ 129
7.11.1 Port B Data Direction Register (PBDDR) ........................................................... 129
7.11.2 Port B Output Data Register (PBODR) ............................................................... 129
7.11.3 Port B Input Data Register (PBPIN).................................................................... 130
7.11.4 Pin Functions ....................................................................................................... 130
7.11.5 Port B Input Pull-Up MOS .................................................................................. 131
7.12 Ports C, D.......................................................................................................................... 132
7.12.1 Port C and Port D Data Direction Registers (PCDDR, PDDDR) ........................ 132
7.12.2 Port C and Port D Output Data Registers (PCODR, PDODR) ............................ 133
7.12.3 Port C and Port D Input Data Registers (PCPIN, PDPIN)................................... 133
7.12.4 Port C and Port D Nch-OD Control Register (PCNOCR, PDNOCR) ................. 134
Rev. 1.00, 05/04, page xiii of xxxiv
7.12.5 Pin Functions ....................................................................................................... 135
7.12.6 Input Pull-Up MOS in Ports C and D .................................................................. 135
7.13 Ports E, F........................................................................................................................... 136
7.13.1 Port E and Port F Data Direction Registers (PEDDR, PFDDR).......................... 136
7.13.2 Port E and Port F Output Data Registers (PEODR, PFODR).............................. 137
7.13.3 Port E and Port F Input Data Registers (PEPIN, PFPIN)..................................... 138
7.13.4 Pin Functions ....................................................................................................... 138
7.13.5 Port E and Port F Nch-OD Control Register (PENOCR, PFNOCR)................... 140
7.13.6 Pin Functions ....................................................................................................... 141
7.13.7 Input Pull-Up MOS in Ports E and F ................................................................... 141
7.14 Port G................................................................................................................................ 142
7.14.1 Port G Data Direction Register (PGDDR) ........................................................... 142
7.14.2 Port G Output Data Register (PGODR)............................................................... 143
7.14.3 Port G Input Data Register (PGPIN).................................................................... 143
7.14.4 Pin Functions ....................................................................................................... 144
7.14.5 Port G Nch-OD Control Register (PGNOCR) ..................................................... 145
7.14.6 Pin Functions ....................................................................................................... 145
Section 8 8-Bit PWM Timer (PWM).................................................................147
8.1 Features............................................................................................................................. 147
8.2 Input/Output Pins.............................................................................................................. 148
8.3 Register Descriptions ........................................................................................................ 148
8.3.1 PWM Register Select (PWSL)............................................................................. 149
8.3.2 PWM Data Registers 7 to 0 (PWDR7 to PWD0).................................................151
8.3.3 PWM Data Polarity Register A (PWDPRA) ....................................................... 151
8.3.4 PWM Output Enable Register A (PWOERA) ..................................................... 152
8.3.5 Peripheral Clock Select Register (PCSR) ............................................................ 152
8.4 Operation .......................................................................................................................... 153
8.4.1 PWM Setting Example ........................................................................................ 155
8.4.2 Diagram of PWM Used as D/A Converter .......................................................... 155
8.5 Usage Notes ...................................................................................................................... 156
8.5.1 Module Stop Mode Setting .................................................................................. 156
Section 9 16-Bit Free-Running Timer (FRT) ....................................................157
9.1 Features............................................................................................................................. 157
9.2 Input/Output Pins.............................................................................................................. 159
9.3 Register Descriptions ........................................................................................................ 159
9.3.1 Free-Running Counter (FRC) .............................................................................. 160
9.3.2 Output Compare Registers A and B (OCRA, OCRB) ......................................... 160
9.3.3 Input Capture Registers A to D (ICRA to ICRD) ................................................ 160
9.3.4 Output Compare Registers AR and AF (OCRAR, OCRAF) ............................... 161
9.3.5 Output Compare Register DM (OCRDM)........................................................... 161
9.3.6 Timer Interrupt Enable Register (TIER).............................................................. 162
Rev. 1.00, 05/04, page xiv of xxxiv
9.3.7 Timer Control/Status Register (TCSR)................................................................ 163
9.3.8 Timer Control Register (TCR)............................................................................. 166
9.3.9 Timer Output Compare Control Register (TOCR) .............................................. 167
9.4 Operation .......................................................................................................................... 169
9.4.1 Pulse Output ........................................................................................................ 169
9.5 Operation Timing.............................................................................................................. 170
9.5.1 FRC Increment Timing........................................................................................ 170
9.5.2 Output Compare Output Timing.......................................................................... 171
9.5.3 FRC Clear Timing ............................................................................................... 171
9.5.4 Input Capture Input Timing ................................................................................. 172
9.5.5 Buffered Input Capture Input Timing .................................................................. 173
9.5.6 Timing of Input Capture Flag (ICF) Setting ........................................................ 174
9.5.7 Timing of Output Compare Flag (OCF) setting................................................... 174
9.5.8 Timing of FRC Overflow Flag Setting ................................................................ 175
9.5.9 Automatic Addition Timing................................................................................. 175
9.5.10 Mask Signal Generation Timing.......................................................................... 176
9.6 Interrupt Sources...............................................................................................................177
9.7 Usage Notes...................................................................................................................... 177
9.7.1 Conflict between FRC Write and Clear ............................................................... 177
9.7.2 Conflict between FRC Write and Increment........................................................ 178
9.7.3 Conflict between OCR Write and Compare-Match ............................................. 178
9.7.4 Switching of Internal Clock and FRC Operation................................................. 180
9.7.5 Module Stop Mode Setting.................................................................................. 181
Section 10 8-Bit Timer (TMR)..........................................................................183
10.1 Features............................................................................................................................. 183
10.2 Input/Output Pins.............................................................................................................. 188
10.3 Register Descriptions........................................................................................................ 189
10.3.1 Timer Counter (TCNT)........................................................................................ 191
10.3.2 Time Constant Register A (TCORA) .................................................................. 191
10.3.3 Time Constant Register B (TCORB)................................................................... 191
10.3.4 Timer Control Register (TCR)............................................................................. 192
10.3.5 Timer Control/Status Register (TCSR)................................................................ 196
10.3.6 Time Constant Register (TCORC)....................................................................... 202
10.3.7 Input Capture Registers R and F (TICRR, TICRF, TICRR_A and TICRF_A) ... 202
10.3.8 Timer Input Select Register (TISR and TISR_B)................................................ 202
10.3.9 Timer Connection Register I (TCONRI) ............................................................. 203
10.3.10 Timer Connection Register S (TCONRS) ........................................................... 203
10.3.11 Timer XY Control Register (TCRXY) ................................................................ 204
10.3.12 Timer AB Control Register (TCRAB)................................................................. 205
10.4 Operation .......................................................................................................................... 206
10.4.1 Pulse Output ........................................................................................................ 206
10.5 Operation Timing.............................................................................................................. 207
Rev. 1.00, 05/04, page xv of xxxiv
10.5.1 TCNT Count Timing ........................................................................................... 207
10.5.2 Timing of CMFA and CMFB Setting at Compare-Match ................................... 207
10.5.3 Timing of Timer Output at Compare-Match........................................................ 208
10.5.4 Timing of Counter Clear at Compare-Match ....................................................... 208
10.5.5 TCNT External Reset Timing.............................................................................. 209
10.5.6 Timing of Overflow Flag (OVF) Setting ............................................................. 209
10.6 TMR_0 and TMR_1 Cascaded Connection...................................................................... 210
10.6.1 16-Bit Count Mode .............................................................................................. 210
10.6.2 Compare-Match Count Mode .............................................................................. 210
10.7 TMR_Y and TMR_X Cascaded Connection .................................................................... 211
10.7.1 16-Bit Count Mode .............................................................................................. 211
10.7.2 Compare-Match Count Mode .............................................................................. 211
10.7.3 Input Capture Operation ...................................................................................... 212
10.8 TMR_B and TMR_A Cascaded Connection .................................................................... 212
10.8.1 16-Bit Count Mode .............................................................................................. 212
10.8.2 Compare-Match Count Mode .............................................................................. 212
10.8.3 Input Capture Operation ...................................................................................... 213
10.9 Interrupt Sources...............................................................................................................215
10.10 Usage Notes ...................................................................................................................... 216
10.10.1 Conflict between TCNT Write and Counter Clear............................................... 216
10.10.2 Conflict between TCNT Write and Count-Up ..................................................... 216
10.10.3 Conflict between TCOR Write and Compare-Match........................................... 217
10.10.4 Conflict between Compare-Matches A and B ..................................................... 217
10.10.5 Switching of Internal Clocks and TCNT Operation............................................. 218
10.10.6 Mode Setting with Cascaded Connection ............................................................ 219
10.10.7 Module Stop Mode Setting .................................................................................. 219
Section 11 Watchdog Timer (WDT)..................................................................221
11.1 Features............................................................................................................................. 221
11.2 Input/Output Pins.............................................................................................................. 223
11.3 Register Descriptions ........................................................................................................ 223
11.3.1 Timer Counter (TCNT)........................................................................................ 223
11.3.2 Timer Control/Status Register (TCSR)................................................................ 224
11.4 Operation .......................................................................................................................... 227
11.4.1 Watchdog Timer Mode........................................................................................ 227
11.4.2 Interval Timer Mode............................................................................................ 229
11.4.3 RESO Signal Output Timing ............................................................................... 230
11.5 Interrupt Sources...............................................................................................................230
11.6 Usage Notes ...................................................................................................................... 231
11.6.1 Notes on Register Access..................................................................................... 231
11.6.2 Conflict between Timer Counter (TCNT) Write and Increment.......................... 232
11.6.3 Changing Values of CKS2 to CKS0 Bits............................................................. 232
11.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode................ 232
Rev. 1.00, 05/04, page xvi of xxxiv
11.6.5 System Reset by RESO Signal ............................................................................ 233
11.6.6 Counter Values during Transitions between High-Speed, Sub-Active,
and Watch Modes ................................................................................................ 233
Section 12 Serial Communication Interface (SCI)............................................235
12.1 Features............................................................................................................................. 235
12.2 Input/Output Pins.............................................................................................................. 236
12.3 Register Descriptions........................................................................................................ 237
12.3.1 Receive Shift Register (RSR) .............................................................................. 237
12.3.2 Receive Data Register (RDR).............................................................................. 237
12.3.3 Transmit Data Register (TDR)............................................................................. 237
12.3.4 Transmit Shift Register (TSR)............................................................................. 238
12.3.5 Serial Mode Register (SMR) ............................................................................... 238
12.3.6 Serial Control Register (SCR) ............................................................................. 239
12.3.7 Serial Status Register (SSR) ................................................................................ 241
12.3.8 Serial Interface Mode Register (SCMR).............................................................. 243
12.3.9 Bit Rate Register (BRR) ...................................................................................... 244
12.3.10 Serial Pin Select Register (SPSR)........................................................................ 249
12.4 Operation in Asynchronous Mode .................................................................................... 249
12.4.1 Data Transfer Format........................................................................................... 250
12.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode 251
12.4.3 Clock.................................................................................................................... 251
12.4.4 SCI Initialization (Asynchronous Mode)............................................................. 253
12.4.5 Data Transmission (Asynchronous Mode) .......................................................... 254
12.4.6 Serial Data Reception (Asynchronous Mode) ..................................................... 256
12.5 Multiprocessor Communication Function......................................................................... 259
12.5.1 Multiprocessor Serial Data Transmission............................................................ 260
12.5.2 Multiprocessor Serial Data Reception ................................................................. 261
12.6 Operation in Clocked Synchronous Mode ........................................................................ 264
12.6.1 Clock.................................................................................................................... 264
12.6.2 SCI Initialization (Clocked Synchronous Mode)................................................. 265
12.6.3 Serial Data Transmission (Clocked Synchronous Mode) .................................... 266
12.6.4 Serial Data Reception (Clocked Synchronous Mode) ......................................... 268
12.6.5 Simultaneous Serial Data Transmission and Reception
(Clocked Synchronous Mode) ............................................................................. 269
12.7 Interrupt Sources...............................................................................................................271
12.8 Usage Notes...................................................................................................................... 272
12.8.1 Module Stop Mode Setting .................................................................................. 272
12.8.2 Break Detection and Processing .......................................................................... 272
12.8.3 Mark State and Break Detection.......................................................................... 272
12.8.4 Receive Error Flags and Transmit Operations
(Clocked Synchronous Mode Only) .................................................................... 272
12.8.5 Relation between Writing to TDR and TDRE Flag............................................. 272
Rev. 1.00, 05/04, page xvii of xxxiv
12.8.6 SCI Operations during Mode Transitions ............................................................ 273
12.8.7 Switching from SCK Pins to Port Pins ................................................................ 276
Section 13 I2C Bus Interface (IIC) .....................................................................277
13.1 Features............................................................................................................................. 277
13.2 Input/Output Pins.............................................................................................................. 280
13.3 Register Descriptions ........................................................................................................ 281
13.3.1 I2C Bus Data Register (ICDR) ............................................................................. 282
13.3.2 Slave Address Register (SAR)............................................................................. 283
13.3.3 Second Slave Address Register (SARX) ............................................................. 284
13.3.4 I2C Bus Mode Register (ICMR)........................................................................... 286
13.3.5 I2C Bus Control Register (ICCR)......................................................................... 289
13.3.6 I2C Bus Status Register (ICSR)............................................................................ 297
13.3.7 DDC Switch Register (DDCSWR)...................................................................... 301
13.3.8 I2C Bus Extended Control Register (ICXR)......................................................... 302
13.3.9 Port G Control Register (PGCTL) ....................................................................... 306
13.4 Operation .......................................................................................................................... 307
13.4.1 I2C Bus Data Format ............................................................................................ 307
13.4.2 Initialization ......................................................................................................... 309
13.4.3 Master Transmit Operation .................................................................................. 309
13.4.4 Master Receive Operation.................................................................................... 314
13.4.5 Slave Receive Operation...................................................................................... 321
13.4.6 Slave Transmit Operation .................................................................................... 328
13.4.7 IRIC Setting Timing and SCL Control ................................................................ 331
13.4.8 Noise Canceller.................................................................................................... 334
13.4.9 Initialization of Internal State .............................................................................. 335
13.5 Interrupt Sources...............................................................................................................336
13.6 Usage Notes ...................................................................................................................... 337
13.6.1 Module Stop Mode Setting .................................................................................. 347
Section 14 Keyboard Buffer Controller.............................................................349
14.1 Features............................................................................................................................. 349
14.2 Input/Output Pins.............................................................................................................. 350
14.3 Register Descriptions ........................................................................................................ 351
14.3.1 Keyboard Control Register H (KBCRH) ............................................................. 351
14.3.2 Keyboard Control Register L (KBCRL).............................................................. 353
14.3.3 Keyboard Data Buffer Register (KBBR) ............................................................. 354
14.4 Operation .......................................................................................................................... 355
14.4.1 Receive Operation................................................................................................ 355
14.4.2 Transmit Operation .............................................................................................. 356
14.4.3 Receive Abort ...................................................................................................... 359
14.4.4 KCLKI and KDI Read Timing............................................................................. 361
14.4.5 KCLKO and KDO Write Timing......................................................................... 361
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14.4.6 KBF Setting Timing and KCLK Control............................................................. 362
14.4.7 Receive Timing.................................................................................................... 363
14.4.8 KCLK Fall Interrupt Operation ........................................................................... 364
14.5 Usage Notes...................................................................................................................... 365
14.5.1 KBIOE Setting and KCLK Falling Edge Detection ............................................ 365
14.5.2 Module Stop Mode Setting .................................................................................. 366
Section 15 Host Interface (LPC) .......................................................................369
15.1 Features............................................................................................................................. 369
15.2 Input/Output Pins.............................................................................................................. 371
15.3 Register Descriptions........................................................................................................ 372
15.3.1 Host Interface Control Registers 0 and 1 (HICR0, HICR1) ................................ 373
15.3.2 Host Interface Control Registers 2 and 3 (HICR2, HICR3) ................................ 379
15.3.3 LPC Channel 3 Address Register (LADR3)........................................................ 381
15.3.4 Input Data Registers 1 to 3 (IDR1 to IDR3) ........................................................ 382
15.3.5 Output Data Registers 1 to 3 (ODR1 to ODR3) .................................................. 383
15.3.6 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15).................................... 383
15.3.7 Status Registers 1 to 3 (STR1 to STR3) .............................................................. 383
15.3.8 SERIRQ Control Registers 0 and 1 (SIRQCR0, SIRQCR1) ............................... 389
15.3.9 Host Interface Select Register (HISEL)............................................................... 397
15.4 Operation .......................................................................................................................... 398
15.4.1 Host Interface Activation..................................................................................... 398
15.4.2 LPC I/O Cycles.................................................................................................... 399
15.4.3 A20 Gate.............................................................................................................. 400
15.4.4 Host Interface Shutdown Function (LPCPD) ...................................................... 403
15.4.5 Host Interface Serialized Interrupt Operation (SERIRQ) .................................... 407
15.4.6 Host Interface Clock Start Request (CLKRUN).................................................. 409
15.5 Interrupt Sources...............................................................................................................410
15.5.1 IBFI1, IBFI2, IBFI3, and ERRI ........................................................................... 410
15.5.2 SMI, HIRQ1, HIRQ6, HIRQ9, HIRQ10, HIRQ11, and HIRQ12 ....................... 410
15.6 Usage Notes...................................................................................................................... 413
15.6.1 Module Stop Mode Setting .................................................................................. 413
15.6.2 Notes on Using Host Interface............................................................................. 413
Section 16 A/D Converter .................................................................................413
16.1 Features............................................................................................................................. 413
16.2 Input/Output Pins.............................................................................................................. 415
16.3 Register Descriptions........................................................................................................ 416
16.3.1 A/D Data Registers A to D (ADDRA to ADDRD) ............................................. 416
16.3.2 A/D Control/Status Register (ADCSR) ............................................................... 417
16.3.3 A/D Control Register (ADCR) ............................................................................ 418
16.4 Operation .......................................................................................................................... 419
16.4.1 Single Mode......................................................................................................... 419
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16.4.2 Scan Mode ........................................................................................................... 419
16.4.3 Input Sampling and A/D Conversion Time ......................................................... 421
16.4.4 External Trigger Input Timing............................................................................. 422
16.5 Interrupt Sources...............................................................................................................423
16.6 A/D Conversion Accuracy Definitions ............................................................................. 423
16.7 Usage Notes ...................................................................................................................... 425
16.7.1 Permissible Signal Source Impedance ................................................................. 425
16.7.2 Influences on Absolute Accuracy ........................................................................ 425
16.7.3 Setting Range of Analog Power Supply and Other Pins...................................... 426
16.7.4 Notes on Board Design........................................................................................ 426
16.7.5 Notes on Noise Countermeasures ........................................................................ 426
16.7.6 Module Stop Mode Setting .................................................................................. 427
Section 17 RAM ................................................................................................429
Section 18 ROM ................................................................................................431
18.1 Features............................................................................................................................. 431
18.2 Mode Transitions .............................................................................................................. 433
18.3 Block Configuration.......................................................................................................... 436
18.4 Input/Output Pins.............................................................................................................. 437
18.5 Register Descriptions ........................................................................................................ 437
18.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 438
18.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 439
18.5.3 Erase Block Registers 1 and 2 (EBR1, EBR2) ....................................................440
18.6 Operating Modes............................................................................................................... 441
18.7 On-Board Programming Modes........................................................................................ 441
18.7.1 Boot Mode ........................................................................................................... 442
18.7.2 User Program Mode............................................................................................. 445
18.8 Flash Memory Programming/Erasing ............................................................................... 446
18.8.1 Program/Program-Verify ..................................................................................... 446
18.8.2 Erase/Erase-Verify............................................................................................... 448
18.9 Program/Erase Protection ................................................................................................. 450
18.9.1 Hardware Protection ............................................................................................ 450
18.9.2 Software Protection.............................................................................................. 450
18.9.3 Error Protection....................................................................................................450
18.10 Interrupts during Flash Memory Programming/Erasing ................................................... 451
18.11 Programmer Mode ............................................................................................................ 452
18.12 Usage Notes ...................................................................................................................... 453
Section 19 Clock Pulse Generator .....................................................................455
19.1 Oscillator........................................................................................................................... 456
19.1.1 Connecting Crystal Resonator ............................................................................. 456
19.1.2 External Clock Input Method............................................................................... 457
Rev. 1.00, 05/04, page xx of xxxiv
19.2 Duty Correction Circuit .................................................................................................... 459
19.3 Medium-Speed Clock Divider .......................................................................................... 459
19.4 Bus Master Clock Select Circuit....................................................................................... 459
19.5 Subclock Input Circuit ...................................................................................................... 460
19.6 Waveform Forming Circuit............................................................................................... 460
19.7 Clock Select Circuit .......................................................................................................... 461
19.8 Usage Notes...................................................................................................................... 461
19.8.1 Note on Resonator ............................................................................................... 461
19.8.2 Notes on Board Design........................................................................................ 461
Section 20 Power-Down Modes........................................................................463
20.1 Register Descriptions........................................................................................................ 463
20.1.1 Standby Control Register (SBYCR) .................................................................... 464
20.1.2 Low-Power Control Register (LPWRCR) ........................................................... 465
20.1.3 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL) ................... 467
20.2 Mode Transitions and LSI States...................................................................................... 468
20.3 Medium-Speed Mode ....................................................................................................... 470
20.4 Sleep Mode ....................................................................................................................... 471
20.5 Software Standby Mode.................................................................................................... 471
20.6 Hardware Standby Mode .................................................................................................. 473
20.7 Watch Mode......................................................................................................................474
20.8 Subsleep Mode.................................................................................................................. 475
20.9 Subactive Mode ................................................................................................................ 476
20.10 Module Stop Mode ........................................................................................................... 477
20.11 Direct Transitions ............................................................................................................. 477
20.12 Usage Notes...................................................................................................................... 478
20.12.1 I/O Port Status...................................................................................................... 478
20.12.2 Current Consumption when Waiting for Oscillation Stabilization ...................... 478
Section 21 List of Registers...............................................................................479
21.1 Register Addresses (Address Order)................................................................................. 480
21.2 Register Bits...................................................................................................................... 489
21.3 Register States in Each Operating Mode .......................................................................... 497
21.4 Register Select Conditions................................................................................................ 505
Section 22 Electrical Characteristics .................................................................513
22.1 Absolute Maximum Ratings ............................................................................................. 513
22.2 DC Characteristics ............................................................................................................ 514
22.3 AC Characteristics ............................................................................................................ 520
22.3.1 Clock Timing....................................................................................................... 521
22.3.2 Control Signal Timing ......................................................................................... 522
22.3.3 Timing of On-Chip Peripheral Modules .............................................................. 523
22.4 A/D Conversion Characteristics ....................................................................................... 526
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22.5 Flash Memory Characteristics .......................................................................................... 527
22.6 Usage Note........................................................................................................................ 529
22.7 Timing Chart..................................................................................................................... 529
22.7.1 Clock Timing....................................................................................................... 529
22.7.2 Control Signal Timing ......................................................................................... 531
22.7.3 On-Chip Peripheral Module Timing .................................................................... 532
Appendix .........................................................................................................537
A. I/O Port States in Each Processing State........................................................................... 537
B. Product Codes ...................................................................................................................538
C. Package Dimensions ......................................................................................................... 539
Index .........................................................................................................541
Rev. 1.00, 05/04, page xxii of xxxiv
Rev. 1.00, 05/04, page xxiii of xxxiv
Figures
Section 1 Overview
Figure 1.1 Internal Block Diagram ................................................................................................. 2
Figure 1.2 Pin Arrangement............................................................................................................ 3
Section 2 CPU
Figure 2.1 Exception Vector Table (Normal Mode)..................................................................... 17
Figure 2.2 Stack Structure in Normal Mode................................................................................. 17
Figure 2.3 Exception Vector Table (Advanced Mode).................................................................18
Figure 2.4 Stack Structure in Advanced Mode............................................................................. 19
Figure 2.5 Memory Map............................................................................................................... 20
Figure 2.6 CPU Internal Registers................................................................................................ 21
Figure 2.7 Usage of General Registers .........................................................................................22
Figure 2.8 Stack............................................................................................................................ 23
Figure 2.9 General Register Data Formats (1).............................................................................. 26
Figure 2.9 General Register Data Formats (2).............................................................................. 27
Figure 2.10 Memory Data Formats...............................................................................................28
Figure 2.11 Instruction Formats (Examples) ................................................................................ 39
Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode...................... 43
Figure 2.13 State Transitions........................................................................................................ 47
Section 3 MCU Operating Modes
Figure 3.1 Address Map for H8S/2111B-B .................................................................................. 57
Figure 3.2 Address Map for H8S/2111B-C .................................................................................. 58
Section 4 Exception Handling
Figure 4.1 Reset Sequence (Mode 3)............................................................................................61
Figure 4.2 Stack Status after Exception Handling ........................................................................ 64
Figure 4.3 Operation when SP Value is Odd................................................................................ 65
Section 5 Interrupt Controller
Figure 5.1 Block Diagram of Interrupt Controller........................................................................ 68
Figure 5.2 Relationship between Interrupts IRQ7 and IRQ6, Interrupts KIN15 to KIN0,
Interrupts WUE7 to WUE0, and Registers KMIMR, KMIMRA, and WUEMRB..... 75
Figure 5.3 Block Diagram of Interrupts IRQ7 to IRQ0................................................................ 76
Figure 5.4 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0....... 81
Figure 5.5 State Transition in Interrupt Control Mode 1 .............................................................. 82
Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 1..... 84
Figure 5.7 Interrupt Exception Handling...................................................................................... 85
Figure 5.8 Address Break Block Diagram.................................................................................... 87
Figure 5.9 Address Break Timing Example .................................................................................89
Figure 5.10 Conflict between Interrupt Generation and Disabling............................................... 90
Rev. 1.00, 05/04, page xxiv of xxxiv
Section 8 8-Bit PWM Timer (PWM)
Figure 8.1 Block Diagram of PWM Timer................................................................................. 147
Figure 8.2 Example of Additional Pulse Timing (When Upper 4 Bits of PWDR = B'1000) ..... 154
Figure 8.3 Example of PWM Setting.......................................................................................... 155
Figure 8.4 Example when PWM is Used as D/A Converter....................................................... 155
Section 9 16-Bit Free-Running Timer (FRT)
Figure 9.1 Block Diagram of 16-Bit Free-Running Timer ......................................................... 158
Figure 9.2 Example of Pulse Output........................................................................................... 169
Figure 9.3 Increment Timing with Internal Clock Source.......................................................... 170
Figure 9.4 Increment Timing with External Clock Source......................................................... 170
Figure 9.5 Timing of Output Compare A Output ....................................................................... 171
Figure 9.6 Clearing of FRC by Compare-Match A Signal ......................................................... 171
Figure 9.7 Input Capture Input Signal Timing (Usual Case)...................................................... 172
Figure 9.8 Input Capture Input Signal Timing (When ICRA to ICRD are Read) ...................... 172
Figure 9.9 Buffered Input Capture Timing................................................................................. 173
Figure 9.10 Buffered Input Capture Timing (BUFEA = 1) ........................................................ 173
Figure 9.11 Timing of Input Capture Flag (ICFA, ICFB, ICFC, or ICFD) Setting.................... 174
Figure 9.12 Timing of Output Compare Flag (OCFA or OCFB) Setting ................................... 174
Figure 9.13 Timing of Overflow Flag (OVF) Setting................................................................. 175
Figure 9.14 OCRA Automatic Addition Timing ........................................................................ 175
Figure 9.15 Timing of Input Capture Mask Signal Setting......................................................... 176
Figure 9.16 Timing of Input Capture Mask Signal Clearing ...................................................... 176
Figure 9.17 FRC Write-Clear Conflict ....................................................................................... 177
Figure 9.18 FRC Write-Increment Conflict................................................................................ 178
Figure 9.19 Conflict between OCR Write and Compare-Match
(When Automatic Addition Function is Not Used) ................................................. 179
Figure 9.20 Conflict between OCRAR/OCRAF Write and Compare-Match
(When Automatic Addition Function is Used) ........................................................ 179
Section 10 8-Bit Timer (TMR)
Figure 10.1 Block Diagram of 8-Bit Timer (TMR_0 and TMR_1)............................................ 185
Figure 10.2 Block Diagram of 8-Bit Timer (TMR_Y and TMR_X).......................................... 186
Figure 10.3 Block Diagram of 8-Bit Timer (TMR_B and TMR_A) .......................................... 187
Figure 10.4 Pulse Output Example............................................................................................. 206
Figure 10.5 Count Timing for Internal Clock Input ................................................................... 207
Figure 10.6 Count Timing for External Clock Input (Both Edges) ............................................ 207
Figure 10.7 Timing of CMF Setting at Compare-Match ............................................................ 208
Figure 10.8 Timing of Toggled Timer Output by Compare-Match A Signal............................. 208
Figure 10.9 Timing of Counter Clear by Compare-Match ......................................................... 208
Figure 10.10 Timing of Counter Clear by External Reset Input................................................. 209
Figure 10.11 Timing of OVF Flag Setting ................................................................................. 209
Figure 10.12 Timing of Input Capture Operation....................................................................... 213
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Figure 10.13 Timing of Input Capture Signal
(Input capture signal is input during TICRR and TICRF read) ............................. 213
Figure 10.14 Conflict between TCNT Write and Clear.............................................................. 216
Figure 10.15 Conflict between TCNT Write and Count-Up....................................................... 216
Figure 10.16 Conflict between TCOR Write and Compare-Match ............................................ 217
Section 11 Watchdog Timer (WDT)
Figure 11.1 Block Diagram of WDT.......................................................................................... 222
Figure 11.2 Watchdog Timer Mode (RST/NMI = 1) Operation................................................. 228
Figure 11.3 Interval Timer Mode Operation............................................................................... 229
Figure 11.4 OVF Flag Set Timing .............................................................................................. 229
Figure 11.5 Output Timing of RESO signal ............................................................................... 230
Figure 11.6 Writing to TCNT and TCSR (WDT_0)................................................................... 231
Figure 11.7 Conflict between TCNT Write and Increment ........................................................ 232
Figure 11.8 Sample Circuit for Resetting System by RESO Signal ........................................... 233
Section 12 Serial Communication Interface (SCI)
Figure 12.1 Block Diagram of SCI............................................................................................. 236
Figure 12.2 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits) ................................................. 249
Figure 12.3 Receive Data Sampling Timing in Asynchronous Mode ........................................ 251
Figure 12.4 Relation between Output Clock and Transmit Data Phase
(Asynchronous Mode) ............................................................................................ 252
Figure 12.5 Sample SCI Initialization Flowchart ....................................................................... 253
Figure 12.6 Example of SCI Transmit Operation in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit).................................................... 254
Figure 12.7 Sample Serial Transmission Flowchart ................................................................... 255
Figure 12.8 Example of SCI Receive Operation in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit).................................................... 256
Figure 12.9 Sample Serial Reception Flowchart (1)................................................................... 257
Figure 12.9 Sample Serial Reception Flowchart (2)................................................................... 258
Figure 12.10 Example of Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A).......................................... 259
Figure 12.11 Sample Multiprocessor Serial Transmission Flowchart ........................................ 260
Figure 12.12 Example of SCI Receive Operation
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) ............................. 261
Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 262
Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 263
Figure 12.14 Data Format in Clocked Synchronous Communication (LSB-First)..................... 264
Figure 12.15 Sample SCI Initialization Flowchart ..................................................................... 265
Figure 12.16 Example of SCI Transmit Operation in Clocked Synchronous Mode................... 266
Figure 12.17 Sample Serial Transmission Flowchart ................................................................. 267
Figure 12.18 Example of SCI Receive Operation in Clocked Synchronous Mode .................... 268
Figure 12.19 Sample Serial Reception Flowchart ...................................................................... 269
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Figure 12.20 Sample Flowchart of Simultaneous Serial Transmission and Reception .............. 270
Figure 12.21 Sample Flowchart for Mode Transition during Transmission............................... 274
Figure 12.22 Pin States during Transmission in Asynchronous Mode (Internal Clock) ............ 274
Figure 12.23 Pin States during Transmission in Clocked Synchronous Mode
(Internal Clock)..................................................................................................... 275
Figure 12.24 Sample Flowchart for Mode Transition during Reception .................................... 275
Figure 12.25 Switching from SCK Pins to Port Pins.................................................................. 276
Figure 12.26 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins.......... 276
Section 13 I2C Bus Interface (IIC)
Figure 13.1 Block Diagram of I2C Bus Interface ....................................................................... 278
Figure 13.2 I2C Bus Interface Connections (Example: This LSI as Master) .............................. 279
Figure 13.3 I2C Bus Data Format (I2C Bus Format)................................................................... 307
Figure 13.4 I2C Bus Data Format (Serial Format) ...................................................................... 307
Figure 13.5 I2C Bus Timing........................................................................................................ 308
Figure 13.6 Sample Flowchart for IIC Initialization .................................................................. 309
Figure 13.7 Sample Flowchart for Operations in Master Transmit Mode.................................. 310
Figure 13.8 Example of Operation Timing in Master Transmit Mode (MLS = WAIT = 0) ...... 312
Figure 13.9 Example of Stop Condition Issuance Operation Timing
in Master Transmit Mode (MLS = WAIT = 0)....................................................... 313
Figure 13.10 Sample Flowchart for Operations in Master Receive Mode (HNDS = 1)............. 314
Figure 13.11 Example of Operation Timing in Master Receive Mode
(MLS = WAIT = 0, HNDS = 1)............................................................................ 316
Figure 13.12 Example of Stop Condition Issuance Operation Timing
in Master Receive Mode (MLS = WAIT = 0, HNDS = 1) ................................... 316
Figure 13.13 Sample Flowchart for Operations in Master Receive Mode
(receiving multiple bytes) (WAIT = 1)................................................................. 317
Figure 13.14 Sample Flowchart for Operations in Master Receive Mode
(receiving a single byte) (WAIT = 1) ................................................................... 318
Figure 13.15 Example of Master Receive Mode Operation Timing
(MLS = ACKB = 0, WAIT = 1) ........................................................................... 320
Figure 13.16 Example of Stop Condition Issuance Timing in Master Receive Mode
(MLS = ACKB = 0, WAIT = 1) ........................................................................... 321
Figure 13.17 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 1) ............... 322
Figure 13.18 Example of Slave Receive Mode Operation Timing (1) (MLS = 0, HNDS= 1) ... 324
Figure 13.19 Example of Slave Receive Mode Operation Timing (2) (MLS = 0, HNDS= 1) ... 324
Figure 13.20 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 0) ............... 325
Figure 13.21 Example of Slave Receive Mode Operation Timing (1)
(MLS = ACKB = 0, HNDS = 0)........................................................................... 327
Figure 13.22 Example of Slave Receive Mode Operation Timing (2)
(MLS = ACKB = 0, HNDS = 0)........................................................................... 327
Figure 13.23 Sample Flowchart for Slave Transmit Mode......................................................... 328
Figure 13.24 Example of Slave Transmit Mode Operation Timing (MLS = 0) ......................... 330
Rev. 1.00, 05/04, page xxvii of xxxiv
Figure 13.25 IRIC Setting Timing and SCL Control (1) ............................................................ 331
Figure 13.26 IRIC Setting Timing and SCL Control (2) ............................................................ 332
Figure 13.27 IRIC Setting Timing and SCL Control (3) ............................................................ 333
Figure 13.28 Block Diagram of Noise Canceler......................................................................... 334
Figure 13.29 Notes on Reading Master Receive Data................................................................ 340
Figure 13.30 Flowchart for Start Condition Issuance Instruction for Retransmission
and Timing............................................................................................................. 341
Figure 13.31 Stop Condition Issuance Timing ........................................................................... 342
Figure 13.32 IRIC Flag Clearing Timing when WAIT = 1 ........................................................ 343
Figure 13.33 ICDR Read and ICCR Access Timing in Slave Transmit Mode........................... 344
Figure 13.34 TRS Bit Set Timing in Slave Mode.......................................................................345
Figure 13.35 Diagram of Erroneous Operation when Arbitration is Lost................................... 347
Section 14 Keyboard Buffer Controller
Figure 14.1 Block Diagram of Keyboard Buffer Controller....................................................... 349
Figure 14.2 Keyboard Buffer Controller Connection ................................................................. 350
Figure 14.3 Sample Receive Processing Flowchart.................................................................... 355
Figure 14.4 Receive Timing ....................................................................................................... 356
Figure 14.5 Sample Transmit Processing Flowchart (1)............................................................ 357
Figure 14.5 Sample Transmit Processing Flowchart (2)............................................................. 358
Figure 14.6 Transmit Timing...................................................................................................... 358
Figure 14.7 Sample Receive Abort Processing Flowchart (1)................................................... 359
Figure 14.7 Sample Receive Abort Processing Flowchart (2)................................................... 360
Figure 14.8 Receive Abort and Transmit Start
(Transmission/Reception Switchover) Timing ....................................................... 360
Figure 14.9 KCLKI and KDI Read Timing ................................................................................ 361
Figure 14.10 KCLKO and KDO Write Timing .......................................................................... 361
Figure 14.11 KBF Setting and KCLK Automatic I/O Inhibit Generation Timing ..................... 362
Figure 14.12 Receive Counter and KBBR Data Load Timing ................................................... 363
Figure 14.13 Example of KCLK Input Fall Interrupt Operation ................................................ 364
Figure 14.14 KBIOE Setting and KCLK Falling Edge Detection Timing ................................. 365
Section 15 Host Interface (LPC)
Figure 15.1 Block Diagram of LPC............................................................................................ 370
Figure 15.2 Typical LFRAME Timing....................................................................................... 400
Figure 15.3 Abort Mechanism.................................................................................................... 400
Figure 15.4 GA20 Output........................................................................................................... 401
Figure 15.5 Power-Down State Termination Timing ................................................................. 406
Figure 15.6 SERIRQ Timing...................................................................................................... 407
Figure 15.7 Clock Start Request Timing .................................................................................... 409
Figure 15.8 HIRQ Flowchart (Example of Channel 1)............................................................... 412
Rev. 1.00, 05/04, page xxviii of xxxiv
Section 16 A/D Converter
Figure 16.1 Block Diagram of A/D Converter ........................................................................... 414
Figure 16.2 Example of A/D Converter Operation
(Scan Mode, Channels AN0 to AN2 Selected)....................................................... 420
Figure 16.3 A/D Conversion Timing.......................................................................................... 421
Figure 16.4 External Trigger Input Timing ................................................................................ 422
Figure 16.5 A/D Conversion Accuracy Definitions ................................................................... 424
Figure 16.6 A/D Conversion Accuracy Definitions ................................................................... 424
Figure 16.7 Example of Analog Input Circuit ............................................................................ 425
Figure 16.8 Example of Analog Input Protection Circuit........................................................... 427
Figure 16.9 Equivalent Circuit of Analog Input Pin................................................................... 427
Section 18 ROM
Figure 18.1 Block Diagram of Flash Memory............................................................................ 432
Figure 18.2 Flash Memory State Transitions.............................................................................. 433
Figure 18.3 Boot Mode............................................................................................................... 434
Figure 18.4 User Program Mode (Example) .............................................................................. 435
Figure 18.5 Flash Memory Block Configuration........................................................................ 436
Figure 18.6 On-Chip RAM Area in Boot Mode......................................................................... 444
Figure 18.7 ID Code Area .......................................................................................................... 444
Figure 18.8 Programming/Erasing Flowchart Example in User Program Mode........................ 445
Figure 18.9 Program/Program-Verify Flowchart ....................................................................... 447
Figure 18.10 Erase/Erase-Verify Flowchart ............................................................................... 449
Figure 18.11 Memory Map in Programmer Mode...................................................................... 452
Section 19 Clock Pulse Generator
Figure 19.1 Block Diagram of Clock Pulse Generator ............................................................... 455
Figure 19.2 Typical Connection to Crystal Resonator................................................................ 456
Figure 19.3 Equivalent Circuit of Crystal Resonator.................................................................. 456
Figure 19.4 Example of External Clock Input............................................................................ 457
Figure 19.5 External Clock Input Timing................................................................................... 458
Figure 19.6 Timing of External Clock Output Stabilization Delay Time................................... 459
Figure 19.7 Subclock Input Timing............................................................................................ 460
Figure 19.8 Note on Board Design of Oscillator Circuit Section ............................................... 461
Section 20 Power-Down Modes
Figure 20.1 Mode Transition Diagram ....................................................................................... 468
Figure 20.2 Medium-Speed Mode Timing ................................................................................. 470
Figure 20.3 Application Example in Software Standby Mode ................................................... 472
Figure 20.4 Hardware Standby Mode Timing ............................................................................ 473
Section 22 Electrical Characteristics
Figure 22.1 Darlington Pair Drive Circuit (Example) ................................................................ 518
Figure 22.2 LED Drive Circuit (Example) ................................................................................. 519
Figure 22.3 Output Load Circuit ................................................................................................ 520
Rev. 1.00, 05/04, page xxix of xxxiv
Figure 22.4 Connection of VCL Capacitor................................................................................. 529
Figure 22.5 System Clock Timing.............................................................................................. 529
Figure 22.6 Oscillation Settling Timing ..................................................................................... 530
Figure 22.7 Oscillation Setting Timing (Exiting Software Standby Mode)................................530
Figure 22.8 Reset Input Timing.................................................................................................. 531
Figure 22.9 Interrupt Input Timing............................................................................................. 531
Figure 22.10 I/O Port Input/Output Timing................................................................................ 532
Figure 22.11 FRT Input/Output Timing ..................................................................................... 532
Figure 22.12 FRT Clock Input Timing....................................................................................... 532
Figure 22.13 8-Bit Timer Output Timing ................................................................................... 533
Figure 22.14 8-Bit Timer Clock Input Timing ........................................................................... 533
Figure 22.15 8-Bit Timer Reset Input Timing ............................................................................ 533
Figure 22.16 PWM, PWMX Output Timing .............................................................................. 533
Figure 22.17 SCK Clock Input Timing.......................................................................................534
Figure 22.18 SCI Input/Output Timing (Synchronous Mode).................................................... 534
Figure 22.19 A/D Converter External Trigger Input Timing...................................................... 534
Figure 22.20 WDT Output Timing (RESO) ............................................................................... 534
Figure 22.21 Keyboard Buffer Controller Timing...................................................................... 535
Figure 22.22 I2C Bus Interface Input/Output Timing ................................................................. 535
Figure 22.23 Host Interface (LPC) Timing................................................................................. 536
Figure 22.24 Tester Measurement Condition ............................................................................. 536
Appendix
Figure C.1 Package Dimensions (TFP-144) ............................................................................... 539
Rev. 1.00, 05/04, page xxx of xxxiv
Rev. 1.00, 05/04, page xxxi of xxxiv
Tables
Section 1 Overview
Table 1.1 Pin Functions in Each Operating Mode .................................................................... 4
Table 1.2 Pin Functions ............................................................................................................ 9
Section 2 CPU
Table 2.1 Instruction Classification ........................................................................................ 29
Table 2.2 Operation Notation .................................................................................................30
Table 2.3 Data Transfer Instructions.......................................................................................31
Table 2.4 Arithmetic Operations Instructions (1) ................................................................... 32
Table 2.4 Arithmetic Operations Instructions (2) ................................................................... 33
Table 2.5 Logic Operations Instructions................................................................................. 34
Table 2.6 Shift Instructions..................................................................................................... 34
Table 2.7 Bit Manipulation Instructions (1)............................................................................ 35
Table 2.7 Bit Manipulation Instructions (2)............................................................................ 36
Table 2.8 Branch Instructions................................................................................................. 37
Table 2.9 System Control Instructions.................................................................................... 38
Table 2.10 Block Data Transfer Instructions ............................................................................ 38
Table 2.11 Addressing Modes .................................................................................................. 40
Table 2.12 Absolute Address Access Ranges...........................................................................41
Table 2.13 Effective Address Calculation (1)........................................................................... 44
Table 2.13 Effective Address Calculation (2)........................................................................... 45
Section 3 MCU Operating Modes
Table 3.1 MCU Operating Mode Selection ............................................................................ 51
Section 4 Exception Handling
Table 4.1 Exception Types and Priority..................................................................................59
Table 4.2 Exception Handling Vector Table........................................................................... 60
Table 4.3 Status of CCR after Trap Instruction Exception Handling .....................................63
Section 5 Interrupt Controller
Table 5.1 Pin Configuration.................................................................................................... 68
Table 5.2 Correspondence between Interrupt Source and ICR............................................... 70
Table 5.3 Interrupt Sources, Vector Addresses, and Interrupt Priorities................................. 78
Table 5.4 Interrupt Control Modes ......................................................................................... 80
Table 5.5 Interrupt Response Times .......................................................................................86
Table 5.6 Number of States in Interrupt Handling Routine Execution Status ........................ 86
Section 7 I/O Ports
Table 7.1 Port Functions......................................................................................................... 96
Table 7.2 Input Pull-Up MOS States (Port 1)....................................................................... 102
Table 7.3 Input Pull-Up MOS States (Port 2)....................................................................... 104
Rev. 1.00, 05/04, page xxxii of xxxiv
Table 7.4 Input Pull-Up MOS States (Port 3)....................................................................... 106
Table 7.5 Input Pull-Up MOS States (Port 6)....................................................................... 116
Table 7.6 Input Pull-Up MOS States (Port A)...................................................................... 128
Table 7.7 Input Pull-Up MOS States (Port B) ...................................................................... 131
Table 7.8 Input Pull-Up MOS States (Port C and port D) .................................................... 135
Table 7.9 Input Pull-Up MOS States (Port E and port F) ..................................................... 141
Section 8 8-Bit PWM Timer (PWM)
Table 8.1 Pin Configuration.................................................................................................. 148
Table 8.2 Internal Clock Selection........................................................................................ 150
Table 8.3 Resolution, PWM Conversion Period,
and Carrier Frequency when φ = 10 MHz ............................................................ 150
Table 8.4 Duty Cycle of Basic Pulse .................................................................................... 153
Table 8.5 Position of Pulses Added to Basic Pulses ............................................................. 154
Section 9 16-Bit Free-Running Timer (FRT)
Table 9.1 Pin Configuration.................................................................................................. 159
Table 9.2 FRT Interrupt Sources .......................................................................................... 177
Table 9.3 Switching of Internal Clock and FRC Operation.................................................. 180
Section 10 8-Bit Timer (TMR)
Table 10.1 TMR Function ...................................................................................................... 184
Table 10.2 Pin Configuration.................................................................................................. 188
Table 10.3 Clock Input to TCNT and Count Condition (1).................................................... 193
Table 10.3 Clock Input to TCNT and Count Condition (2).................................................... 194
Table 10.3 Clock Input to TCNT and Count Condition (3).................................................... 195
Table 10.4 Registers Accessible by TMR_X/TMR_Y ........................................................... 204
Table 10.5 Input Capture Signal Selection ............................................................................. 214
Table 10.6 Input Capture Signal Selection ............................................................................. 214
Table 10.7 Interrupt Sources of 8-Bit Timers TMR_0, TMR_1, TMR_Y,
TMR_X TMR_B, and TMR_A ............................................................................ 215
Table 10.8 Timer Output Priorities......................................................................................... 217
Table 10.9 Switching of Internal Clocks and TCNT Operation ............................................. 218
Section 11 Watchdog Timer (WDT)
Table 11.1 Pin Configuration.................................................................................................. 223
Table 11.2 WDT Interrupt Source .......................................................................................... 230
Section 12 Serial Communication Interface (SCI)
Table 12.1 Pin Configuration.................................................................................................. 236
Table 12.2 Relationships between N Setting in BRR and Bit Rate B..................................... 244
Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ........................... 245
Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ........................... 246
Table 12.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) .......................... 247
Table 12.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) ................ 247
Table 12.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)..................... 248
Rev. 1.00, 05/04, page xxxiii of xxxiv
Table 12.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) .... 248
Table 12.8 Serial Transfer Formats (Asynchronous Mode).................................................... 250
Table 12.9 SSR Status Flags and Receive Data Handling ...................................................... 257
Table 12.10 SCI Interrupt Sources........................................................................................ 271
Section 13 I2C Bus Interface (IIC)
Table 13.1 Pin Configuration.................................................................................................. 280
Table 13.2 Communication Format ........................................................................................ 285
Table 13.3 I2C Transfer Rate .................................................................................................. 288
Table 13.4 Flags and Transfer States (Master Mode)............................................................. 294
Table 13.5 Flags and Transfer States (Slave Mode) ............................................................... 295
Table 13.5 Flags and Transfer States (Slave Mode) (cont).....................................................296
Table 13.6 I2C Bus Data Format Symbols.............................................................................. 308
Table 13.7 IIC Interrupt Sources ............................................................................................336
Table 13.8 I2C Bus Timing (SCL and SDA Outputs)............................................................. 337
Table 13.9 Permissible SCL Rise Time (tsr) Values ............................................................... 338
Table 13.10 I2C Bus Timing (with Maximum Influence of tSr/tSf)........................................ 339
Section 14 Keyboard Buffer Controller
Table 14.1 Pin Configuration.................................................................................................. 350
Section 15 Host Interface (LPC)
Table 15.1 Pin Configuration.................................................................................................. 371
Table 15.2 Register Selection ................................................................................................. 382
Table 15.3 GA20 (P81) Set/Clear Timing .............................................................................. 401
Table 15.4 Fast A20 Gate Output Signals.............................................................................. 402
Table 15.5 Scope of Host Interface Pin Shutdown ................................................................. 404
Table 15.6 Scope of Initialization in Each Host Interface Mode ............................................405
Table 15.7 Receive Complete Interrupts and Error Interrupt.................................................. 410
Table 15.8 HIRQ Setting and Clearing Conditions ................................................................ 411
Section 16 A/D Converter
Table 16.1 Pin Configuration.................................................................................................. 415
Table 16.2 Analog Input Channels and Corresponding ADDR Registers .............................. 416
Table 16.3 A/D Conversion Time (Single Mode)................................................................... 422
Section 18 ROM
Table 18.1 Differences between Boot Mode and User Program Mode .................................. 433
Table 18.2 Pin Configuration.................................................................................................. 437
Table 18.3 Operating Modes and ROM..................................................................................441
Table 18.4 On-Board Programming Mode Settings ............................................................... 441
Table 18.5 Boot Mode Operation ........................................................................................... 443
Table 18.6 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is
Possible ................................................................................................................. 444
Rev. 1.00, 05/04, page xxxiv of xxxiv
Section 19 Clock Pulse Generator
Table 19.1 Damping Resistance Values ................................................................................. 456
Table 19.2 Crystal Resonator Parameters............................................................................... 456
Table 19.3 External Clock Input Conditions .......................................................................... 458
Table 19.4 External Clock Output Stabilization Delay Time ................................................. 458
Table 19.5 Subclock Input Conditions.................................................................................... 460
Section 20 Power-Down Modes
Table 20.1 Operating Frequency and Wait Time.................................................................... 465
Table 20.2 LSI Internal States in Each Operating Mode ........................................................ 469
Section 22 Electrical Characteristics
Table 22.1 Absolute Maximum Ratings ................................................................................. 513
Table 22.2 DC Characteristics (1) .......................................................................................... 514
Table 22.2 DC Characteristics (2) .......................................................................................... 516
Table 22.2 DC Characteristics (3) When LPC Function is Used............................................ 517
Table 22.3 Permissible Output Currents................................................................................. 518
Table 22.4 Bus Drive Characteristics ..................................................................................... 519
Table 22.5 Clock Timing........................................................................................................ 521
Table 22.6 Control Signal Timing .......................................................................................... 522
Table 22.7 Timing of On-Chip Peripheral Modules (1) ......................................................... 523
Table 22.8 Keyboard Buffer Controller Timing ..................................................................... 524
Table 22.9 I2C Bus Timing ..................................................................................................... 525
Table 22.10 LPC Module Timing......................................................................................... 526
Table 22.11 A/D Conversion Characteristics
(AN5 to AN0 Input: 134/266-State Conversion) .............................................. 526
Table 22.12 Flash Memory Characteristics .......................................................................... 527
Appendix
Table A.1 I/O Port States in Each Processing State............................................................... 537
Rev. 1.00, 05/04, page 1 of 544
Section 1 Overview
1.1 Features
High-speed H8S/2000 central processing unit with an internal 16-bit architecture
Upward-compatible with H8/300 and H8/300H CPUs on an object level
Sixteen 16-bit general registers
65 basic instructions
Various peripheral functions
8-bit PWM timer (PWM)
16-bit free-running timer (FRT)
8-bit timer (TMR)
Watchdog timer (WDT)
Asynchronous or clocked synchronous serial communication interface (SCI)
I2C bus interface (IIC)
Keyboard buffer controller
Host interface (LPC)
10-bit A/D converter
Clock pulse generator
On-chip memory
ROM Model ROM RAM Remarks
F-ZTAT Version HD64F2111BVB* 64 Kbytes 2 Kbytes
HD64F2111BVC* 64 Kbytes 3 Kbytes
Note: * 3-V version product
General I/O ports
I/O pins: 114
Input-only pins: 8
Supports various power-down states
Compact package
Product Package Code Body Size Pin Pitch
H8S/2111B TQFP-144 TFP-144 18.0 × 18.0 mm 0.4 mm
Rev. 1.00, 05/04, page 2 of 544
1.2 Internal Block Diagram
P17/PW7
P16/PW6
P15/PW5
P14/PW4
P13/PW3
P12/PW2
P11/PW1
P10/PW0
P27
P26
P25
P24
P23
P22
P21
P20
PA7/KIN15/PS2CD
PA6/KIN14/PS2CC
PA5/KIN13/PS2BD
PA4/KIN12/PS2BC
PA3/KIN11/PS2AD
PA2/KIN10/PS2AC
PA1/KIN9
PA0/KIN8
P37/SERIRQ
P36/LCLK
P35/LRESET
P34/LFRAME
P33/LAD3
P32/LAD2
P31/LAD1
P30/LAD0
PB7/WUE7
PB6/WUE6
PB5/WUE5
PB4/WUE4
PB3/WUE3
PB2/WUE2
PB1/WUE1/LSCI
PB0/WUE0/LSMI
P97/SDA0
P96/φ/EXCL
P95
P94
P93
P92/IRQ0
P91/IRQ1
P90/IRQ2/ADTRG
P67/TMOX/KIN7/IRQ7
P66/FTOB/KIN6/IRQ6
P65/FTID/KIN5
P64/FTIC/KIN4
P63/FTIB/KIN3
P62/FTIA/KIN2/TMIY
P61/FTOA/KIN1
P60/FTCI/KIN0/TMIX
P47
P46
P45/TMRI1
P44/TMO1
P43/TMCI1
P42/TMRI0/SDA1
P41/TMO0
P40/TMCI0
P52/ExSCK1*/SCL0
P51/ExRxD1*
P50/ExTxD1*
X1
X2
RES
XTAL
EXTAL
VCCB
MD1
MD0
NMI
STBY
RESO
VCC
VCC
VCL
VSS
VSS
VSS
VSS
VSS
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
P77
P76
P75/AN5
P74/AN4
P73/AN3
P72/AN2
P71/AN1
P70/AN0
P86/IRQ5/SCK1/SCL1
P85/IRQ4/RxD1
P84/IRQ3/TxD1
P83/LPCPD
P82/CLKRUN
P81/GA20
P80/PME
AVref
AVCC
AVSS
PG7/ExSCLB*
PG6/ExSDAB*
PG5/ExSCLA*
PG4/ExSDAA*
PG3
PG2
PG1
PG0
PF7/TMOY*
PF6/ExTMOX*
PF5/ExTMIY*
PF4/ExTMIX*
PF3/TMOB
PF2/TMOA
PF1/TMIB
PF0/TMIA
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
H8S/2000 CPU
Interrup
controller
WDT× 2 channels
ROM
(Flash memory)
RAM
8-bit PWM
16-bit FRT
8-bit timer × 6 channels Host interfaces
(LPC)
10-bit A/D converter
SCI × 1 channel
IIC × 2 channels
Port 8 Port 7 Port G Port F Port E
Clock pulse
generator
Internal data bus
Internal address bus
Bus controller
Port APort 2Port 1Port 3Port BPort CPort D
Port 9Port 6Port 4Port 5
Note: * The program development tool (emulator) does not support this function.
Keyboard buffer
controller × 3 channels
Figure 1.1 Internal Block Diagram
Rev. 1.00, 05/04, page 3 of 544
1.3 Pin Description
1.3.1 Pin Arrangement
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
VCC
P43/TMCI1
P44/TMO1
P45/TMRI1
P46
P47
VSS
RES
MD1
MD0
NMI
STBY
VCL
P52/ExSCK1*/SCL0
P51/ExRxD1*
P50/ExTxD1*
P97/SDA0
P96/φ/ EXCL
P95
P94
P93
P92/IRQ0
P91/IRQ1
P90/IRQ2/ADTRG
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
PA7/KIN15/PS2CD
PA6/KIN14/PS2CC
PA5/KIN13/PS2BD
VCCB
P13/PW3
P14/PW4
P15/PW5
P16/PW6
P17/PW7
P20
P21
P22
P23
P24
P25
P26
P27
VSS
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
VCC
P67/TMOX/KIN7/IRQ
7
P66/FTOB/KIN6/IRQ6
P65/FTID/KIN5
P64/FTIC/KIN4
P63/FTIB/KIN3
P62/FTIA/KIN2/TMIY
P61/FTOA/KIN1
P60/FTCI/KIN0/TMIX
AVref
AVCC
P77
P76
P75/AN5
P74/AN4
P73/AN3
P72/AN2
P71/AN1
P70/AN0
AVSS
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PG0
PG1
PG2
PG3
PG4/ExSDAA*
PG5/ExSCLA*
PG6/ExSDAB*
PG7/ExSCLB*
PF0/TMIA
PF1/TMIB
PF2/TMOA
PF3/TMOB
PF4/ExTMIX*
PF5/ExTMIY*
PF6/ExTMOX*
PF7/TMOY*
VSS
PA0/KIN8
PA1/KIN9
PA2/KIN10/PS2AC
PA3/KIN11/PS2AD
PA4/KIN12/PS2BC
P12/PW2
P11/PW1
VSS
P10/PW0
PB7/WUE7
PB6/WUE6
PB5/WUE5
PB4/WUE4
PB3/WUE3
PB2/WUE2
PB1/WUE1/LSCI
PB0/WUE0/LSMI
P30/LAD0
P31/LAD1
P32/LAD2
P33/LAD3
P34/LFRAME
P35/LRESET
P36/LCLK
P37/SERIRQ
P80/PME
P81/GA20
P82/CLKRUN
P83/LPCPD
P84/IRQ3/TxD1
P85/IRQ4/RxD1
P86/IRQ5/SCK1/SCL1
P40/TMCI0
P41/TMO0
P42/TMRI0/SDA1
VSS
X1
X2
RESO
XTAL
EXTAL
TFP-144
(Top view)
Note: * The program development tool (emulator) does not support this function.
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Figure 1.2 Pin Arrangement
Rev. 1.00, 05/04, page 4 of 544
1.3.2 Pin Functions in Each Operating Mode
Table 1.1 Pin Functions in Each Operating Mode
Pin Name
Pin No. Single-Chip Modes Flash Memory
TFP-144 Mode 2, Mode 3 (EXPE = 0) Programmer Mode
1 VCC VCC
2 P43/TMCI1 NC
3 P44/TMO1 NC
4 P45/TMRI1 NC
5 P46 NC
6 P47 NC
7 VSS VSS
8 RES RES
9 MD1 VSS
10 MD0 VSS
11 NMI FA9
12 STBY VCC
13 VCL VCC
14 (N) P52/ExSCK1*/SCL0 FA18
15 P51/ExRxD1* FA17
16 P50/ExTxD1* NC
17 (N) P97/SDA0 VCC
18 P96/φ/EXCL NC
19 P95 FA16
20 P94 FA15
21 P93 WE
22 P92/IRQ0 VSS
23 P91/IRQ1 VCC
24 P90/IRQ2/ADTRG VCC
25 PE7 NC
26 PE6 NC
27 PE5 NC
28 PE4 NC
29 PE3 NC
30 PE2 NC
Rev. 1.00, 05/04, page 5 of 544
Pin Name
Pin No. Single-Chip Modes Flash Memory
TFP-144 Mode 2, Mode 3 (EXPE = 0) Programmer Mode
31 PE1 NC
32 PE0 NC
33 (B) PA7/KIN15/PS2CD NC
34 (B) PA6/KIN14/PS2CC NC
35 (B) PA5/KIN13/PS2BD NC
36 VCCB VCC
37 (B) PA4/KIN12/PS2BC NC
38 (B) PA3/KIN11/PS2AD NC
39 (B) PA2/KIN10/PS2AC NC
40 (B) PA1/KIN9 NC
41 (B) PA0/KIN8 NC
42 VSS VSS
43 PF7/TMOY* NC
44 PF6/ExTMOX* NC
45 PF5/ExTMIY* NC
46 PF4/ExTMIX* NC
47 PF3/TMOB NC
48 PF2/TMOA NC
49 PF1/TMIB NC
50 PF0/TMIA NC
51 (N) PG7/ExSCLB* NC
52 (N) PG6/ExSDAB* NC
53 (N) PG5/ExSCLA* NC
54 (N) PG4/ExSDAA* NC
55 (N) PG3 NC
56 (N) PG2 NC
57 (N) PG1 NC
58 (N) PG0 NC
59 PD7 NC
60 PD6 NC
Rev. 1.00, 05/04, page 6 of 544
Pin Name
Pin No. Single-Chip Modes Flash Memory
TFP-144 Mode 2, Mode 3 (EXPE = 0) Programmer Mode
61 PD5 NC
62 PD4 NC
63 PD3 NC
64 PD2 NC
65 PD1 NC
66 PD0 NC
67 AVSS VSS
68 P70/AN0 NC
69 P71/AN1 NC
70 P72/AN2 NC
71 P73/AN3 NC
72 P74/AN4 NC
73 P75/AN5 NC
74 P76 NC
75 P77 NC
76 AVCC VCC
77 AVref VCC
78 P60/FTCI/KIN0/TMIX NC
79 P61/FTOA/KIN1 NC
80 P62/FTIA/KIN2/TMIY NC
81 P63/FTIB/KIN3 NC
82 P64/FTIC/KIN4 NC
83 P65/FTID/KIN5 NC
84 P66/FTOB/KIN6/IRQ6 NC
85 P67/TMOX/KIN7/IRQ7 VSS
86 VCC VCC
87 PC7 NC
88 PC6 NC
89 PC5 NC
90 PC4 NC
Rev. 1.00, 05/04, page 7 of 544
Pin Name
Pin No. Single-Chip Modes Flash Memory
TFP-144 Mode 2, Mode 3 (EXPE = 0) Programmer Mode
91 PC3 NC
92 PC2 NC
93 PC1 NC
94 PC0 NC
95 VSS VSS
96 P27 CE
97 P26 FA14
98 P25 FA13
99 P24 FA12
100 P23 FA11
101 P22 FA10
102 P21 OE
103 P20 FA8
104 P17/PW7 FA7
105 P16/PW6 FA6
106 P15/PW5 FA5
107 P14/PW4 FA4
108 P13/PW3 FA3
109 P12/PW2 FA2
110 P11/PW1 FA1
111 VSS VSS
112 P10/PW0 FA0
113 PB7/WUE7 NC
114 PB6/WUE6 NC
115 PB5/WUE5 NC
116 PB4/WUE4 NC
117 PB3/WUE3 NC
118 PB2/WUE2 NC
119 PB1/WUE1/LSCI NC
120 PB0/WUE0/LSMI NC
Rev. 1.00, 05/04, page 8 of 544
Pin Name
Pin No. Single-Chip Modes Flash Memory
TFP-144 Mode 2, Mode 3 (EXPE = 0) Programmer Mode
121 P30/LAD0 FO0
122 P31/LAD1 FO1
123 P32/LAD2 FO2
124 P33/LAD3 FO3
125 P34/LFRAME FO4
126 P35/LRESET FO5
127 P36/LCLK FO6
128 P37/SERIRQ FO7
129 P80/PME NC
130 P81/GA20 NC
131 P82/CLKRUN NC
132 P83/LPCPD NC
133 P84/IRQ3/TxD1 NC
134 P85/IRQ4/RxD1 NC
135 (N) P86/IRQ5/SCK1/SCL1 NC
136 P40/TMCI0 NC
137 P41/TMO0 NC
138 (N) P42/TMRI0/SDA1 NC
139 VSS VSS
140 X1 NC
141 X2 NC
142 RESO NC
143 XTAL XTAL
144 EXTAL EXTAL
Note: The (B) in Pin No. means the VCCB drive and the (N) in Pin No. means the NMOS
push-pull/open-drain drive.
* The program development tool (emulator) does not support this function.
Rev. 1.00, 05/04, page 9 of 544
1.3.3 Pin Functions
Table 1.2 Pin Functions
Pin No.
Type Symbol TFP-144 I/O Name and Function
VCC 1, 86 Input Power supply pin. Connect the pin to the
system power supply.
VCL 13 Input Power supply pin. Connect the pin to VCC.
VCCB 36 Input The power supply for the port A input/output
buffer.
Power
VSS 7, 42, 95,
111, 139
Input Ground pin. Connect to the system power
supply (0 V).
XTAL 143 Input
EXTAL 144 Input
Pins for connection to crystal resonators. The
EXTAL pin can also input an external clock.
See section 19, Clock Pulse Generator, for
typical connection diagrams.
φ 18 Output Supplies the system clock to external
devices.
EXCL 18 Input Input a 32.768 kHz external subclock.
X1 140 Input Leave open.
Clock
X2 141 Input Leave open.
Operating
mode control
MD1
MD0
9
10
Input These pins set the operating mode. These
pins should not be changed while the MCU is
operating.
RES 8 Input Reset pin.
When this pin becomes low, the chip is reset.
RESO 142 Output Outputs reset signal to external device.
System
control
STBY 12 Input When this pin is driven low, a transition is
made to hardware standby mode.
NMI
11 Input Input pin for a nonmaskable interrupt request.Interrupt
signals
IRQ0 to
IRQ7
22 to 24,
133 to 135,
84, 85
Input These pins request a maskable interrupt.
Rev. 1.00, 05/04, page 10 of 544
Pin No.
Type Symbol TFP-144 I/O Name and Function
FTCI 78 Input The counter clock input pin.
FTOA 79 Output The output compare A output pin.
FTOB 84 Output The output compare B output pin.
FTIA 80 Input The input capture A input pin.
FTIB 81 Input The input capture B input pin.
FTIC 82 Input The input capture C input pin.
16-bit free-
running timer
(FRT)
FTID 83 Input The input capture D input pin.
TMO0
TMO1
TMOX
TMOY*
TMOA
TMOB
ExTMOX*
137
3
85
43
48
47
44
Output The waveform output pins for the output
compare function.
TMCI0
TMCI1
136
2
Input Input pins for the external clock input to
counters.
8-bit timer
(TMR_0,
TMR_1,
TMR_X,
TMR_Y,
TMR_A,
TMR_B)
TMRI0
TMRI1
138
4
Input The counter reset input pins.
8-bit timer
(TMR_X,
TMR_Y,
TMR_A,
TMR_B)
TMIX
TMIY
TMIA
TMIB
ExTMIX*
ExTMIY*
78
80
50
49
46
45
Input The counter event input and counter reset
input pins.
8-bit PWM
timer (PWM)
PW7 to
PW0
104 to 110,
112
Output PWM timer pulse output pins.
TxD1
ExTxD1*
133
16
Output Transmit data output pins.
RxD1
ExRxD1*
134
15
Input Receive data input pins.
Serial
communi-
cation
interface
(SCI_1) SCK1
ExSCK1*
135
14
Input/
Output
Clock input/output pins.
The output type is NMOS push-pull.
PS2AC
PS2BC
PS2CC
39
37
34
Input/
Output
Keyboard buffer controller synchronization
clock input/output pins.
Keyboard
buffer
controller
PS2AD
PS2BD
PS2CD
38
35
33
Input/
Output
Keyboard buffer controller data input/output
pins.
Rev. 1.00, 05/04, page 11 of 544
Pin No.
Type Symbol TFP-144 I/O Name and Function
LAD3 to
LAD0
124 to 121 Input/
Output
LPC command, address, and data
input/output pins.
LFRAME 125 Input Input pin that indicates the start of an LPC
cycle or forced termination of an abnormal
LPC cycle.
LRESET 126 Input Input pin that indicates an LPC reset.
LCLK 127 Input The LPC clock input pin.
SERIRQ 128 Input/
Output
Input/output pin for LPC serialized host
interrupts (HIRQ1, SMI, HIRQ6, HIRQ9 to
HIRQ12).
LSCI, LSMI,
PME
119, 120,
129
Input/
Output
LPC auxiliary output pins. Functionally, they
are general I/O ports.
GA20 130 Input/
Output
A20 gate control signal output pin. Output
state monitoring input is possible.
CLKRUN 131 Input/
Output
Input/output pin that requests the start of
LCLK operation when LCLK is stopped.
Host interface
(LPC)
LPCPD 132 Input Input pin that controls LPC module shutdown.
KIN0 to
KIN15
78 to 85,
41 to 37,
35 to 33
Input Matrix keyboard input pins. KIN0 to KIN15
are used as key-scan inputs, and P10 to P17
and P20 to P27 are used as key-scan
outputs. This allows a maximum 16-output ×
16-input, 256-key matrix to be configured.
Keyboard
buffer
controller
WUE0 to
WUE7
120 to 113 Input Wakeup event input pins. These pins allow
the same kind of wakeup as key-wakeup
from various sources.
AN5 to AN0 73 to 68 Input Analog input pins.
ADTRG 24 Input Pin for input of an external trigger to start A/D
conversion.
AVCC 76 Input The analog power supply pin for the A/D
converter.
When the A/D is not used, this pin should be
connected to the system power supply (+3
V).
AVref 77 Input The reference power supply pin for the A/D
converter and.
When the A/D is not used, this pin should be
connected to the system power supply (+3
V).
A/D converter
AVSS 67 Input The ground pin for the A/D converter. This
pin should be connected to the system power
supply
(0 V).
Rev. 1.00, 05/04, page 12 of 544
Pin No.
Type Symbol TFP-144 I/O Name and Function
I2C bus
interface (IIC)
SCL0
SCL1
ExSCLA*
ExSCLB*
14
135
53
51
Input/
Output
I2C clock I/O pins. The output type is NMOS
open-drain output.
SDA0
SDA1
ExSDAA*
ExSDAB*
17
138
54
52
Input/
Output
I2C data I/O pins. The output type is NMOS
open-drain output.
I/O ports P17 to P10 104 to 110,
112
Input/
Output
Eight input/output pins.
P27 to P20 96 to 103 Input/
Output
Eight input/output pins.
P37 to P30 128 to 121 Input/
Output
Eight input/output pins.
P47 to P40 6 to 2,
138 to 136
Input/
Output
Eight input/output pins.
(The output type of P42 is NMOS push-pull.)
P52 to P50 14 to 16 Input/
Output
Three input/output pins.
(The output type of P52 is NMOS push-pull.)
P67 to P60 85 to 78 Input/
Output
Eight input/output pins.
P77 to P70 75 to 68 Input Eight input pins.
P86 to P80 135 to 129 Input/
Output
Seven input/output pins.
(The output type of P86 is NMOS push-pull.)
P97 to P90 17 to 24 Input/
Output
Eight input/output pins.
(The output type of P97 is NMOS push-pull.)
PA7 to PA0 33 to 35,
37 to 41
Input/
Output
Eight input/output pins.
PB7 to PB0 113 to 120 Input/
Output
Eight input/output pins.
PC7 to PC0 87 to 94 Input/
Output
Eight input/output pins.
PD7 to PD0 59 to 66 Input/
Output
Eight input/output pins.
PE7 to PE0 25 to 32 Input/
Output
Eight input/output pins.
PF7 to PF0 43 to 50 Input/
Output
Eight input/output pins.
PG7 to PG0 51 to 58 Input/
Output
Eight input/output pins.
(The output type of PG7 to PG0 is NMOS
push-pull.)
Note: * The program development tool (emulator) does not support this function.
CPU210A_020020040200 Rev. 1.00, 05/04, page 13 of 544
Section 2 CPU
The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that
is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit
general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.
This section describes the H8S/2000 CPU. The usable modes and address spaces differ depending
on the product. For details on each product, refer to section 3, MCU Operating Modes.
2.1 Features
Upward-compatibility with H8/300 and H8/300H CPUs
Can execute H8/300 CPU and H8/300H CPU object programs
General-register architecture
Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers
Sixty-five basic instructions
8/16/32-bit arithmetic and logic instructions
Multiply and divide instructions
Powerful bit-manipulation instructions
Eight addressing modes
Register direct [Rn]
Register indirect [@ERn]
Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]
Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]
Immediate [#xx:8, #xx:16, or #xx:32]
Program-counter relative [@(d:8,PC) or @(d:16,PC)]
Memory indirect [@@aa:8]
16-Mbyte address space
Program: 16 Mbytes
Data: 16 Mbytes
High-speed operation
All frequently-used instructions are executed in one or two states
8/16/32-bit register-register add/subtract: 1 state
8 × 8-bit register-register multiply: 12 states (MULXU.B), 13 states (MULXS.B)
16 ÷ 8-bit register-register divide: 12 states (DIVXU.B)
16 × 16-bit register-register multiply: 20 states (MULXU.W), 21 states (MULXS.W)
32 ÷ 16-bit register-register divide: 20 states (DIVXU.W)
Rev. 1.00, 05/04, page 14 of 544
Two CPU operating modes
Normal mode
Advanced mode
Power-down state
Transition to power-down state by SLEEP instruction
Selectable CPU clock speed
2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU
The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.
Register configuration
The MAC register is supported only by the H8S/2600 CPU.
Basic instructions
The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the
H8S/2600 CPU.
The number of execution states of the MULXU and MULXS instructions
Execution States
Instruction Mnemonic H8S/2600 H8S/2000
MULXU.B Rs, Rd 3 12 MULXU
MULXU.W Rs, ERd 4 20
MULXS.B Rs, Rd 4 13 MULXS
MULXS.W Rs, ERd 5 21
In addition, there are differences in address space, CCR and EXR register functions, power-down
modes, etc., depending on the model.
Rev. 1.00, 05/04, page 15 of 544
2.1.2 Differences from H8/300 CPU
In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements.
More general registers and control registers
Eight 16-bit extended registers and one 8-bit control register have been added.
Expanded address space
Normal mode supports the same 64-Kbyte address space as the H8/300 CPU.
Advanced mode supports a maximum 16-Mbyte address space.
Enhanced addressing
The addressing modes have been enhanced to make effective use of the 16-Mbyte address
space.
Enhanced instructions
Addressing modes of bit-manipulation instructions have been enhanced.
Signed multiply and divide instructions have been added.
Two-bit shift and two-bit rotate instructions have been added.
Instructions for saving and restoring multiple registers have been added.
A test and set instruction has been added.
Higher speed
Basic instructions are executed twice as fast.
2.1.3 Differences from H8/300H CPU
In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements.
Additional control register
One 8-bit control register has been added.
Enhanced instructions
Addressing modes of bit-manipulation instructions have been enhanced.
Two-bit shift and two-bit rotate instructions have been added.
Instructions for saving and restoring multiple registers have been added.
A test and set instruction has been added.
Higher speed
Basic instructions are executed twice as fast.
Rev. 1.00, 05/04, page 16 of 544
2.2 CPU Operating Modes
The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a
maximum 64-Kbyte address space. Advanced mode supports a maximum 16-Mbyte address
space. The mode is selected by the LSI's mode pins.
2.2.1 Normal Mode
The exception vector table and stack have the same structure as in the H8/300 CPU in normal
mode.
Address space
Linear access to a maximum address space of 64 Kbytes is possible.
Extended registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit
segments of 32-bit registers.
When extended register En is used as a 16-bit register it can contain any value, even when the
corresponding general register (Rn) is used as an address register. (If general register Rn is
referenced in the register indirect addressing mode with pre-decrement (@–Rn) or post-
increment (@Rn+) and a carry or borrow occurs, the value in the corresponding extended
register (En) will be affected.)
Instruction set
All instructions and addressing modes can be used. Only the lower 16 bits of effective
addresses (EA) are valid.
Exception vector table and memory indirect branch addresses
In normal mode, the top area starting at H'0000 is allocated to the exception vector table. One
branch address is stored per 16 bits. The exception vector table in normal mode is shown in
figure 2.1. For details on the exception vector table, see section 4, Exception Handling.
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions
uses an 8-bit absolute address included in the instruction code to specify a memory operand
that contains a branch address. In normal mode, the operand is a 16-bit (word) operand,
providing a 16-bit branch address. Branch addresses can be stored in the top area from H'0000
to H'00FF. Note that this area is also used for the exception vector table.
Stack structure
In normal mode, when the program counter (PC) is pushed onto the stack in a subroutine call
in normal mode, and the PC and condition-code register (CCR) are pushed onto the stack in
exception handling, they are stored as shown in figure 2.2. The extended control register
(EXR) is not pushed onto the stack. For details, see section 4, Exception Handling.
Rev. 1.00, 05/04, page 17 of 544
H'0000
H'0001
H'0002
H'0003
H'0004
H'0005
H'0006
H'0007
H'0008
H'0009
H'000A
H'000B
Reset exception vector
(Reserved for system use)
Exception vector 1
Exception vector 2
Exception
vector table
(Reserved for system use)
Figure 2.1 Exception Vector Table (Normal Mode)
(a) Subroutine Branch (b) Exception Handling
PC
(16 bits)
CCR
CCR*
PC
(16 bits)
SP
Note: * Ignored when returning.
SP
Figure 2.2 Stack Structure in Normal Mode
Rev. 1.00, 05/04, page 18 of 544
2.2.2 Advanced Mode
Address space
Linear access to a maximum address space of 16 Mbytes is possible.
Extended registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers. They can also be used as the
upper 16-bit segments of 32-bit registers or address registers.
Instruction set
All instructions and addressing modes can be used.
Exception vector table and memory indirect branch addresses
In advanced mode, the top area starting at H'00000000 is allocated to the exception vector
table in 32-bit units. In each 32 bits, the upper 8 bits are ignored and a branch address is stored
in the lower 24 bits (see figure 2.3). For details on the exception vector table, see section 4,
Exception Handling.
H'00000000
H'00000003
H'00000004
H'0000000B
H'0000000C
H'00000010
H'00000008
H'00000007
Reserved
Reserved
Reserved
Reset exception vector
(Reserved for system use)
Exception vector table
Exception vector 1
(Reserved for system use)
Figure 2.3 Exception Vector Table (Advanced Mode)
Rev. 1.00, 05/04, page 19 of 544
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions
uses an 8-bit absolute address included in the instruction code to specify a memory operand
that contains a branch address. In advanced mode, the operand is a 32-bit longword operand,
providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is
regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF.
Note that the top area of this range is also used for the exception vector table.
Stack structure
In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine
call, and the PC and condition-code register (CCR) are pushed onto the stack in exception
handling, they are stored as shown in figure 2.4. The extended control register (EXR) is not
pushed onto the stack. For details, see section 4, Exception Handling.
(a) Subroutine Branch (b) Exception Handling
PC
(24 bits)
CCR
PC
(24 bits)
SP SP
Reserved
Figure 2.4 Stack Structure in Advanced Mode
Rev. 1.00, 05/04, page 20 of 544
2.3 Address Space
Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear
access to a maximum 64-Kbyte address space in normal mode, and a maximum 16-Mbyte
(architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces
differ depending on the product. For details on each product, refer to section 3, MCU Operating
Modes.
H'0000
H'FFFF
H'00000000
H'FFFFFFFF
H'00FFFFFF
64 Kbytes
16 Mbytes Program area
Data area
(b) Advanced Mode(a) Normal Mode
Not available
in this LSI
Figure 2.5 Memory Map
Rev. 1.00, 05/04, page 21 of 544
2.4 Register Configuration
The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of registers:
general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-bit
extended control register (EXR), and an 8-bit condition code register (CCR).
TI2I1I0EXR*
76543210
PC
23 0
15 0 7 0 7 0
E0
E1
E2
E3
E4
E5
E6
E7
R0H
R1H
R2H
R3H
R4H
R5H
R6H
R7H
R0L
R1L
R2L
R3L
R4L
R5L
R6L
R7L
SP:
PC:
EXR:
T:
I2 to I0:
CCR:
I:
UI:
Stack pointer
Program counter
Extended control register
Trace bit
Interrupt mask bits
Condition-code register
Interrupt mask bit
User bit or interrupt mask bit
Half-carry flag
User bit
Negative flag
Zero flag
Overflow flag
Carry flag
ER0
ER1
ER2
ER3
ER4
ER5
ER6
ER7 (SP)
IUIHUNZVC
CCR
76543210
H:
U:
N:
Z:
V:
C:
General Registers (Rn) and Extended Registers (En)
Control Registers
[Legend]
----
Note: * Does not affect operation in this LSI.
Figure 2.6 CPU Internal Registers
Rev. 1.00, 05/04, page 22 of 544
2.4.1 General Registers
The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally
alike and can be used as both address registers and data registers. When a general register is used
as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the
usage of the general registers.
When the general registers are used as 32-bit registers or address registers, they are designated by
the letters ER (ER0 to ER7).
When the general registers are used as 16-bit registers, the ER registers are divided into 16-bit
general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are
functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7)
are also referred to as extended registers.
When the general registers are used as 8-bit registers, the R registers are divided into 8-bit general
registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are
functionally equivalent, providing a maximum sixteen 8-bit registers.
The usage of each register can be selected independently.
General register ER7 has the function of the stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.8 shows the
stack.
• Address registers
• 32-bit registers
• 16-bit registers • 8-bit registers
ER registers
(ER0 to ER7)
E registers (extended registers)
(E0 to E7)
R registers
(R0 to R7)
RH registers
(R0H to R7H)
RL registers
(R0L to R7L)
Figure 2.7 Usage of General Registers
Rev. 1.00, 05/04, page 23 of 544
SP (ER7)
Free area
Stack area
Figure 2.8 Stack
2.4.2 Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched for read, the least significant PC bit is regarded as 0.)
2.4.3 Extended Control Register (EXR)
EXR does not affect operation in this LSI.
Bit Bit Name
Initial
Value R/W Description
7 T 0 R/W Trace Bit
Does not affect operation in this LSI.
6 to 3 All 1 R Reserved
These bits are always read as 1.
2 to 0 I2
I1
I0
All 1 R/W Interrupt Mask Bits 2 to 0
Do not affect operation in this LSI.
Rev. 1.00, 05/04, page 24 of 544
2.4.4 Condition-Code Register (CCR)
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be
performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V,
and C flags are used as branching conditions for conditional branch (Bcc) instructions.
Bit Bit Name
Initial
Value R/W Description
7 I 1 R/W Interrupt Mask Bit
Masks interrupts other than NMI when set to 1. NMI is
accepted regardless of the I bit setting. The I bit is set
to 1 at the start of an exception-handling sequence. For
details, refer to section 5, Interrupt Controller.
6 UI Undefined R/W User Bit or Interrupt Mask Bit
Can be written to and read from by software using the
LDC, STC, ANDC, ORC, and XORC instructions.
5 H Undefined R/W Half-Carry Flag
When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B or
NEG.B instruction is executed, this flag is set to 1 if
there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or
NEG.W instruction is executed, the H flag is set to 1 if
there is a carry or borrow at bit 11, and cleared to 0
otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L
instruction is executed, the H flag is set to 1 if there is a
carry or borrow at bit 27, and cleared to 0 otherwise.
4 U Undefined R/W User Bit
Can be written to and read from by software using the
LDC, STC, ANDC, ORC, and XORC instructions.
3 N Undefined R/W Negative Flag
Stores the value of the most significant bit of data as a
sign bit.
2 Z Undefined R/W Zero Flag
Set to 1 to indicate zero data, and cleared to 0 to
indicate non-zero data.
1 V Undefined R/W Overflow Flag
Set to 1 when an arithmetic overflow occurs, and
cleared to 0 otherwise.
Rev. 1.00, 05/04, page 25 of 544
Bit Bit Name
Initial
Value R/W Description
0 C Undefined R/W Carry Flag
Set to 1 when a carry occurs, and cleared to 0
otherwise. Used by
Add instructions, to indicate a carry
Subtract instructions, to indicate a borrow
Shift and rotate instructions, to indicate a carry
The carry flag is also used as a bit accumulator by bit
manipulation instructions.
2.4.5 Initial Register Values
The program counter (PC) among CPU internal registers is initialized when reset exception
handling loads a start address from a vector table. The trace (T) bit in EXR is cleared to 0, and the
interrupt mask (I) bits in CCR and EXR are set to 1. The other CCR bits and the general registers
are not initialized. Note that the stack pointer (ER7) is undefined. The stack pointer should
therefore be initialized by an MOV.L instruction executed immediately after a reset.
Rev. 1.00, 05/04, page 26 of 544
2.5 Data Formats
The H8S/2000 CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit
(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2,
…, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two
digits of 4-bit BCD data.
2.5.1 General Register Data Formats
Figure 2.9 shows the data formats of general registers.
70
70
MSB LSB
MSB LSB
7043
Don't care
Don't care
Don't care
704 3
70
Don't care
6543271
0
70
Don't care 65432710
Don't care
RnH
RnL
RnH
RnL
RnH
RnL
Data Type Register Number Data Image
Byte data
Byte data
4-bit BCD data
4-bit BCD data
1-bit data
1-bit data
Upper Lower
Upper Lower
Figure 2.9 General Register Data Formats (1)
Rev. 1.00, 05/04, page 27 of 544
15 0
MSB LSB
15 0
MSB LSB
31 16
MSB
15 0
LSB
En Rn
ERn:
En:
Rn:
RnH:
RnL:
MSB:
LSB :
General register ER
General register E
General register R
General register RH
General register RL
Most significant bit
Least significant bit
Data Type Data ImageRegister Number
Word data
Word data
Rn
En
Longword data
[Legend]
ERn
Figure 2.9 General Register Data Formats (2)
Rev. 1.00, 05/04, page 28 of 544
2.5.2 Memory Data Formats
Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and
longword data in memory, but word or longword data must begin at an even address. If an attempt
is made to access word or longword data at an odd address, no address error occurs but the least
significant bit of the address is regarded as 0, so the access starts at the preceding address. This
also applies to instruction fetches.
When SP (ER7) is used as an address register to access the stack, the operand size should be word
size or longword size.
70
76 543210
MSB LSB
MSB
MSB
LSB
LSB
Data Type Address
1-bit data
Byte data
Word data
Address L
Address L
Address 2M
Address 2M + 1
Longword data Address 2N
Address 2N + 1
Address 2N + 2
Address 2N + 3
Data Image
Figure 2.10 Memory Data Formats
Rev. 1.00, 05/04, page 29 of 544
2.6 Instruction Set
The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as
shown in table 2.1.
Table 2.1 Instruction Classification
Function Instructions Size Types
MOV B/W/L
POP*1, PUSH*1 W/L
LDM*5, STM*5 L
Data transfer
MOVFPE*3, MOVTPE*3 B
5
ADD, SUB, CMP, NEG B/W/L
ADDX, SUBX, DAA, DAS B
INC, DEC B/W/L
ADDS, SUBS L
MULXU, DIVXU, MULXS, DIVXS B/W
EXTU, EXTS W/L
Arithmetic
operations
TAS*4 B
19
Logic operations AND, OR, XOR, NOT B/W/L 4
Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL,
ROTXR
B/W/L 8
Bit manipulation BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST,
BAND, BIAND, BOR, BIOR, BXOR, BIXOR
B 14
Branch BCC*2, JMP, BSR, JSR, RTS 5
System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC,
NOP
— 9
Block data transfer EEPMOV 1
Total: 65
Notes: B: Byte size; W: Word size; L: Longword size.
1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-
SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn,
@-SP.
2. BCC is the general name for conditional branch instructions.
3. Cannot be used in this LSI.
4. When using the TAS instruction, use registers ER0, ER1, ER4, and ER5.
5. ER7 is not used as the register that can be saved (STM)/restored (LDM) when using
STM/LDM instruction, because ER7 is the stack pointer.
Rev. 1.00, 05/04, page 30 of 544
2.6.1 Table of Instructions Classified by Function
Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in
tables 2.3 to 2.10 is defined below.
Table 2.2 Operation Notation
Symbol Description
Rd General register (destination)*
Rs General register (source)*
Rn General register*
ERn General register (32-bit register)
(EAd) Destination operand
(EAs) Source operand
EXR Extended control register
CCR Condition-code register
N N (negative) flag in CCR
Z Z (zero) flag in CCR
V V (overflow) flag in CCR
C C (carry) flag in CCR
PC Program counter
SP Stack pointer
#IMM Immediate data
disp Displacement
+ Addition
– Subtraction
× Multiplication
÷ Division
Logical AND
Logical OR
Logical exclusive OR
Move
NOT (logical complement)
:8/:16/:24/:32 8-, 16-, 24-, or 32-bit length
Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0
to R7, E0 to E7), and 32-bit registers (ER0 to ER7).
Rev. 1.00, 05/04, page 31 of 544
Table 2.3 Data Transfer Instructions
Instruction Size*1 Function
MOV B/W/L (EAs) Rd, Rs (EAd)
Moves data between two general registers or between a general
register and memory, or moves immediate data to a general register.
MOVFPE B Cannot be used in this LSI.
MOVTPE B Cannot be used in this LSI.
POP W/L @SP+ Rn
Pops a general register from the stack. POP.W Rn is identical to
MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn
PUSH W/L Rn @-SP
Pushes a general register onto the stack. PUSH.W Rn is identical to
MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP.
LDM*2 L @SP+ Rn (register list)
Pops two or more general registers from the stack.
STM*2 L Rn (register list) @-SP
Pushes two or more general registers onto the stack.
Notes: 1. Size refers to the operand size.
B: Byte
W: Word
L: Longword
2. ER7 is not used as the register that can be saved (STM)/restored (LDM) when using
STM/LDM instruction, because ER7 is the stack pointer.
Rev. 1.00, 05/04, page 32 of 544
Table 2.4 Arithmetic Operations Instructions (1)
Instruction Size* Function
ADD
SUB
B/W/L Rd ± Rs Rd, Rd ± #IMM Rd
Performs addition or subtraction on data in two general registers, or
on immediate data and data in a general register. (Subtraction on
immediate data and data in a general register cannot be performed in
bytes. Use the SUBX or ADD instruction.)
ADDX
SUBX
B Rd ± Rs ± C Rd, Rd ± #IMM ± C Rd
Performs addition or subtraction with carry on data in two general
registers, or on immediate data and data in a general register.
INC
DEC
B/W/L Rd ± 1 Rd, Rd ± 2 Rd
Adds or subtracts the value 1 or 2 to or from data in a general
register. (Only the value 1 can be added to or subtracted from byte
operands.)
ADDS
SUBS
L Rd ± 1 Rd, Rd ± 2 Rd, Rd ± 4 Rd
Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit
register.
DAA
DAS
B Rd (decimal adjust) Rd
Decimal-adjusts an addition or subtraction result in a general register
by referring to CCR to produce 4-bit BCD data.
MULXU B/W Rd × Rs Rd
Performs unsigned multiplication on data in two general registers:
either 8 bits × 8 bits 16 bits or 16 bits × 16 bits 32 bits.
MULXS B/W Rd × Rs Rd
Performs signed multiplication on data in two general registers: either
8 bits × 8 bits 16 bits or 16 bits × 16 bits 32 bits.
DIVXU B/W Rd ÷ Rs Rd
Performs unsigned division on data in two general registers: either 16
bits ÷ 8 bits 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits
16-bit quotient and 16-bit remainder.
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
Rev. 1.00, 05/04, page 33 of 544
Table 2.4 Arithmetic Operations Instructions (2)
Instruction Size*1 Function
DIVXS B/W Rd ÷ Rs Rd
Performs signed division on data in two general registers: either 16
bits ÷ 8 bits 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits
16-bit quotient and 16-bit remainder.
CMP B/W/L Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general
register or with immediate data, and sets the CCR bits according to
the result.
NEG B/W/L 0 – Rd Rd
Takes the two's complement (arithmetic complement) of data in a
general register.
EXTU W/L Rd (zero extension) Rd
Extends the lower 8 bits of a 16-bit register to word size, or the lower
16 bits of a 32-bit register to longword size, by padding with zeros on
the left.
EXTS W/L Rd (sign extension) Rd
Extends the lower 8 bits of a 16-bit register to word size, or the lower
16 bits of a 32-bit register to longword size, by extending the sign bit.
TAS*2 B @ERd – 0, 1 (<bit 7> of @ERd)
Tests memory contents, and sets the most significant bit (bit 7) to 1.
Notes: 1. Size refers to the operand size.
B: Byte
W: Word
L: Longword
2. When using the TAS instruction, use registers ER0, ER1, ER4 and ER5.
Rev. 1.00, 05/04, page 34 of 544
Table 2.5 Logic Operations Instructions
Instruction Size* Function
AND B/W/L Rd Rs Rd, Rd #IMM Rd
Performs a logical AND operation on a general register and another
general register or immediate data.
OR B/W/L Rd Rs Rd, Rd #IMM Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
XOR B/W/L Rd Rs Rd, Rd #IMM Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
NOT B/W/L Rd Rd
Takes the one's complement (logical complement) of data in a
general register.
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
Table 2.6 Shift Instructions
Instruction Size* Function
SHAL
SHAR
B/W/L Rd (shift) Rd
Performs an arithmetic shift on data in a general register. 1-bit or 2
bit shift is possible.
SHLL
SHLR
B/W/L Rd (shift) Rd
Performs a logical shift on data in a general register. 1-bit or 2 bit
shift is possible.
ROTL
ROTR
B/W/L Rd (rotate) Rd
Rotates data in a general register. 1-bit or 2 bit rotation is possible.
ROTXL
ROTXR
B/W/L Rd (rotate) Rd
Rotates data including the carry flag in a general register. 1-bit or 2
bit rotation is possible.
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
Rev. 1.00, 05/04, page 35 of 544
Table 2.7 Bit Manipulation Instructions (1)
Instruction Size* Function
BSET B 1 (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory operand to 1.
The bit number is specified by 3-bit immediate data or the lower three
bits of a general register.
BCLR B 0 (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory operand to 0.
The bit number is specified by 3-bit immediate data or the lower three
bits of a general register.
BNOT B (<bit-No.> of <EAd>) (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory operand. The
bit number is specified by 3-bit immediate data or the lower three bits
of a general register.
BTST B (<bit-No.> of <EAd>) Z
Tests a specified bit in a general register or memory operand and
sets or clears the Z flag accordingly. The bit number is specified by
3-bit immediate data or the lower three bits of a general register.
BAND B C (<bit-No.> of <EAd>) C
Logically ANDs the carry flag with a specified bit in a general register
or memory operand and stores the result in the carry flag.
BIAND B C (<bit-No.> of <EAd>) C
Logically ANDs the carry flag with the inverse of a specified bit in a
general register or memory operand and stores the result in the carry
flag.
The bit number is specified by 3-bit immediate data.
BOR B C (<bit-No.> of <EAd>) C
Logically ORs the carry flag with a specified bit in a general register
or memory operand and stores the result in the carry flag.
BIOR B C (<bit-No.> of <EAd>) C
Logically ORs the carry flag with the inverse of a specified bit in a
general register or memory operand and stores the result in the carry
flag.
The bit number is specified by 3-bit immediate data.
Note: * Size refers to the operand size.
B: Byte
Rev. 1.00, 05/04, page 36 of 544
Table 2.7 Bit Manipulation Instructions (2)
Instruction Size* Function
BXOR B C (<bit-No.> of <EAd>) C
Logically exclusive-ORs the carry flag with a specified bit in a general
register or memory operand and stores the result in the carry flag.
BIXOR B C (<bit-No.> of <EAd>) C
Logically exclusive-ORs the carry flag with the inverse of a specified
bit in a general register or memory operand and stores the result in
the carry flag.
The bit number is specified by 3-bit immediate data.
BLD B (<bit-No.> of <EAd>) C
Transfers a specified bit in a general register or memory operand to
the carry flag.
BILD B (<bit-No.> of <EAd>) C
Transfers the inverse of a specified bit in a general register or
memory operand to the carry flag.
The bit number is specified by 3-bit immediate data.
BST B C (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in a general register
or memory operand.
BIST B C (<bit-No.>. of <EAd>)
Transfers the inverse of the carry flag value to a specified bit in a
general register or memory operand.
The bit number is specified by 3-bit immediate data.
Note: * Size refers to the operand size.
B: Byte
Rev. 1.00, 05/04, page 37 of 544
Table 2.8 Branch Instructions
Instruction Size Function
Branches to a specified address if a specified condition is true. The
branching conditions are listed below.
Mnemonic Description Condition
BRA (BT) Always (true) Always
BRN (BF) Never (false) Never
BHI High C Z = 0
BLS Low or same C Z = 1
BCC (BHS) Carry clear
(high or same)
C = 0
BCS (BLO) Carry set (low) C = 1
BNE Not equal Z = 0
BEQ Equal Z = 1
BVC Overflow clear V = 0
BVS Overflow set V = 1
BPL Plus N = 0
BMI Minus N = 1
BGE Greater or equal N V = 0
BLT Less than N V = 1
BGT Greater than Z (N V) = 0
BLE Less or equal Z (N V) = 1
Bcc —
JMP Branches unconditionally to a specified address.
BSR Branches to a subroutine at a specified address
JSR Branches to a subroutine at a specified address
RTS Returns from a subroutine
Rev. 1.00, 05/04, page 38 of 544
Table 2.9 System Control Instructions
Instruction Size* Function
TRAPA — Starts trap-instruction exception handling.
RTE Returns from an exception-handling routine.
SLEEP — Causes a transition to a power-down state.
LDC B/W (EAs) CCR, (EAs) EXR
Moves the memory operand contents or immediate data to CCR or
EXR. Although CCR and EXR are 8-bit registers, word-size transfers
are performed between them and memory. The upper 8 bits are
valid.
STC B/W CCR (EAd), EXR (EAd)
Transfers CCR or EXR contents to a general register or memory
operand. Although CCR and EXR are 8-bit registers, word-size
transfers are performed between them and memory. The upper 8 bits
are valid.
ANDC B CCR #IMM CCR, EXR #IMM EXR
Logically ANDs the CCR or EXR contents with immediate data.
ORC B CCR #IMM CCR, EXR #IMM EXR
Logically ORs the CCR or EXR contents with immediate data.
XORC B CCR #IMM CCR, EXR #IMM EXR
Logically exclusive-ORs the CCR or EXR contents with immediate
data.
NOP PC + 2 PC
Only increments the program counter.
Note: * Size refers to the operand size.
B: Byte
W: Word
Table 2.10 Block Data Transfer Instructions
Instruction Size Function
EEPMOV.B — if R4L 0 then
Repeat @ER5 + @ER6+
R4L–1 R4L
Until R4L = 0
else next;
EEPMOV.W — if R4 0 then
Repeat @ER5 + @ER6+
R4–1 R4
Until R4 = 0
else next;
Transfers a data block. Starting from the address set in ER5,
transfers data for the number of bytes set in R4L or R4 to the
address location set in ER6.
Execution of the next instruction begins as soon as the transfer is
completed.
Rev. 1.00, 05/04, page 39 of 544
2.6.2 Basic Instruction Formats
The H8S/2000 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an
operation field (op), a register field (r), an effective address extension (EA), and a condition field
(cc).
Figure 2.11 shows examples of instruction formats.
Operation field
Indicates the function of the instruction, the addressing mode, and the operation to be carried
out on the operand. The operation field always includes the first four bits of the instruction.
Some instructions have two operation fields.
Register field
Specifies a general register. Address registers are specified by 3 bits, and data registers by 3
bits or 4 bits. Some instructions have two register fields, and some have no register field.
Effective address extension
8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.
Condition field
Specifies the branching condition of Bcc instructions.
op
op rn rm
NOP, RTS
ADD.B Rn, Rm
MOV.B @(d:16, Rn), Rm
rn rm
op
EA (disp)
op cc EA (disp) BRA d:16
(1) Operation field only
(2) Operation field and register fields
(3) Operation field, register fields, and effective address extension
(4) Operation field, effective address extension, and condition field
Figure 2.11 Instruction Formats (Examples)
Rev. 1.00, 05/04, page 40 of 544
2.7 Addressing Modes and Effective Address Calculation
The H8S/2000 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses
a subset of these addressing modes.
Arithmetic and logic operations instructions can use the register direct and immediate addressing
modes. Data transfer instructions can use all addressing modes except program-counter relative
and memory indirect. Bit manipulation instructions can use register direct, register indirect, or
absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and
BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand.
Table 2.11 Addressing Modes
No. Addressing Mode Symbol
1 Register direct Rn
2 Register indirect @ERn
3 Register indirect with displacement @(d:16,ERn)/@(d:32,ERn)
4 Register indirect with post-increment
Register indirect with pre-decrement
@ERn+
@–ERn
5 Absolute address @aa:8/@aa:16/@aa:24/@aa:32
6 Immediate #xx:8/#xx:16/#xx:32
7 Program-counter relative @(d:8,PC)/@(d:16,PC)
8 Memory indirect @@aa:8
2.7.1 Register Direct—Rn
The register field of the instruction code specifies an 8-, 16-, or 32-bit general register which
contains the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7
and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.
2.7.2 Register Indirect—@ERn
The register field of the instruction code specifies an address register (ERn) which contains the
address of a memory operand. If the address is a program instruction address, the lower 24 bits are
valid and the upper 8 bits are all assumed to be 0 (H'00).
Rev. 1.00, 05/04, page 41 of 544
2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn)
A 16-bit or 32-bit displacement contained in the instruction code is added to an address register
(ERn) specified by the register field of the instruction, and the sum gives the address of a memory
operand. A 16-bit displacement is sign-extended when added.
2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn
Register Indirect with Post-Increment—@ERn+: The register field of the instruction code
specifies an address register (ERn) which contains the address of a memory operand. After the
operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the
address register. The value added is 1 for byte access, 2 for word access, and 4 for longword
access. For word or longword transfer instructions, the register value should be even.
Register Indirect with Pre-Decrement—@-ERn: The value 1, 2, or 4 is subtracted from an
address register (ERn) specified by the register field in the instruction code, and the result
becomes the address of a memory operand. The result is also stored in the address register. The
value subtracted is 1 for byte access, 2 for word access, and 4 for longword access. For word or
longword transfer instructions, the register value should be even.
2.7.5 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32
The instruction code contains the absolute address of a memory operand. The absolute address
may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long
(@aa:32). Table 2.12 indicates the accessible absolute address ranges.
To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits
(@aa:32) long. For an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (H'FFFF).
For a 16-bit absolute address, the upper 16 bits are a sign extension. For a 32-bit absolute address,
the entire address space is accessed.
A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8
bits are all assumed to be 0 (H'00).
Table 2.12 Absolute Address Access Ranges
Absolute Address Normal Mode Advanced Mode
8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF
16 bits (@aa:16) H'000000 to H'007FFF,
H'FF8000 to H'FFFFFF
Data address
32 bits (@aa:32)
Program instruction
address
24 bits (@aa:24)
H'0000 to H'FFFF
H'000000 to H'FFFFFF
Rev. 1.00, 05/04, page 42 of 544
2.7.6 Immediate—#xx:8, #xx:16, or #xx:32
The 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data contained in an instruction
code can be used directly as an operand.
The ADDS, SUBS, INC, and DEC instructions implicitly contain immediate data in their
instruction codes. Some bit manipulation instructions contain 3-bit immediate data in the
instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data
in its instruction code, specifying a vector address.
2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC)
This mode can be used by the Bcc and BSR instructions. An 8-bit or 16-bit displacement
contained in the instruction code is sign-extended to 24 bits and added to the 24-bit address
indicated by the PC value to generate a 24-bit branch address. Only the lower 24 bits of this
branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which
the displacement is added is the address of the first byte of the next instruction, so the possible
branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768 bytes (–16383 to
+16384 words) from the branch instruction. The resulting value should be an even number.
Rev. 1.00, 05/04, page 43 of 544
2.7.8 Memory Indirect—@@aa:8
This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit
absolute address specifying a memory operand which contains a branch address. The upper bits of
the 8-bit absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to
H'00FF in normal mode, H'000000 to H'0000FF in advanced mode).
In normal mode, the memory operand is a word operand and the branch address is 16 bits long. In
advanced mode, the memory operand is a longword operand, the first byte of which is assumed to
be 0 (H'00). Note that the top area of the address range in which the branch address is stored is
also used for the exception vector area. For further details, refer to section 4, Exception Handling.
If an odd address is specified in word or longword memory access, or as a branch address, the
least significant bit is regarded as 0, causing data to be accessed or the instruction code to be
fetched at the address preceding the specified address. (For further information, see section 2.5.2,
Memory Data Formats.)
Specified
by @aa:8
Specified
by @aa:8
Branch address
Branch address
Reserved
(a) Normal Mode (b) Advanced Mode
Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode
Rev. 1.00, 05/04, page 44 of 544
2.7.9 Effective Address Calculation
Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal
mode, the upper 8 bits of the effective address are ignored in order to generate a 16-bit address.
Table 2.13 Effective Address Calculation (1)
No
1
Offset
1
2
4
r
op
31 0
31 23
2
3Register indirect with displacement
@(d:16,ERn) or @(d:32,ERn)
4
r
op disp
r
op
rm
op rn
31 0
31 0
r
op
Don't care
31 23
31 0
Don't care
310
disp
31 0
31 0
31 23
31 0
Don't care
31 23
31 0
Don't care
24
24
24
24
Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)
Register direct (Rn)
General register contents
General register contents
General register contents
General register contents
Sign extension
Register indirect (@ERn)
Register indirect with post-increment or
pre-decrement
• Register indirect with post-increment @ERn+
• Register indirect with pre-decrement @-ERn
1, 2, or 4
1, 2, or 4
Operand Size
Byte
Word
Longword
Operand is general register contents.
Rev. 1.00, 05/04, page 45 of 544
Table 2.13 Effective Address Calculation (2)
No
5
op
31 23
31 0
Don't care
abs
@aa:8 7
H'FFFF
op
31 23
31 0
Don't care
@aa:16
op
@aa:24
@aa:32
abs
15
16
31 23
31 0
Don't care
31 23
31 0
Don't care
abs
op
abs
6
op IMM
#xx:8/#xx:16/#xx:32
8
24
24
24
24
Addressing Mode and Instruction Format
Absolute address
Immediate
Effective Address Calculation Effective Address (EA)
Sign extension
Operand is immediate data.
31 23
7
Program-counter relative
@(d:8,PC)/@(d:16,PC)
Memory indirect @@aa:8
31 0
Don't care
23 0
disp
0
31 23
31 0
Don't care
disp
op
23
op
8
abs
31 0
abs
H'000000
7
8
0
15 31 23
31 0
Don't care
15
H'00
16
opabs
31 0
abs
H'000000
7
8
0
31
24
24
24
PC contents
Sign
extension
Memory contents
Memory contents
Rev. 1.00, 05/04, page 46 of 544
2.8 Processing States
The H8S/2000 CPU has four main processing states: the reset state, exception handling state,
program execution state, and program stop state. Figure 2.13 indicates the state transitions.
Reset state
In this state the CPU and on-chip peripheral modules are all initialized and stopped. When the
RES input goes low, all current processing stops and the CPU enters the reset state. All
interrupts are masked in the reset state. Reset exception handling starts when the RES signal
changes from low to high. For details, refer to section 4, Exception Handling.
The reset state can also be entered by a watchdog timer overflow.
Exception-handling state
The exception-handling state is a transient state that occurs when the CPU alters the normal
processing flow due to an exception source, such as, a reset, trace, interrupt, or trap instruction.
The CPU fetches a start address (vector) from the exception vector table and branches to that
address. For further details, refer to section 4, Exception Handling.
Program execution state
In this state the CPU executes program instructions in sequence.
Program stop state
This is a power-down state in which the CPU stops operating. The program stop state occurs
when a SLEEP instruction is executed or the CPU enters hardware standby mode. For details,
refer to section 20, Power-Down Modes.
Rev. 1.00, 05/04, page 47 of 544
Program execution
state
Sleep mode
Exception-handling state
Software standby mode
RES = high
Reset state*
1
STBY = high, RES = low
Hardware standby mode*
2
Power-down state*
3
Notes: 1.
2.
3.
From any state except hardware standby mode, a transition to the reset state occurs whenever RES
goes low. A transition can also be made to the reset state when the watchdog timer overflows.
From any state, a transition to hardware standby mode occurs when STBY goes low.
The power-down state also includes watch mode, subactive mode, subsleep mode, etc. For details,
refer to section 20, Power-Down Modes.
SLEEP
instruction
with
LSON = 0,
SSBY = 0
Interrupt
request
Request for
exception
handling
End of
exception
handling
External interrupt
request
SLEEP
instruction
with
LSON = 0,
PSS = 0,
SSBY = 1
Figure 2.13 State Transitions
Rev. 1.00, 05/04, page 48 of 544
2.9 Usage Notes
2.9.1 Note on TAS Instruction Usage
When using the TAS instruction, use registers ER0, ER1, ER4 and ER5.
The TAS instruction is not generated by the Renesas Technology H8S and H8/300 series C/C++
compilers. When the TAS instruction is used as a user-defined intrinsic function, use registers
ER0, ER1, ER4 and ER5.
2.9.2 Note on STM/LDM Instruction Usage
ER7 is not used as the register that can be saved (STM)/restored (LDM) when using STM/LDM
instruction, because ER7 is the stack pointer. Two, three, or four registers can be saved/restored
by one STM/LDM instruction. The following ranges can be specified in the register list.
Two registers: ER0—ER1, ER2—ER3, or ER4—ER5
Three registers: ER0—ER2 or ER4—ER6
Four registers: ER0—ER3
The STM/LDM instruction including ER7 is not generated by the Renesas Technology H8S and
H8/300 series C/C++ compilers.
2.9.3 Note on Bit Manipulation Instructions
The BSET, BCLR, BNOT, BST, and BIST instructions read data in byte units, manipulate the
data of the target bit, and write data in byte units. Special care is required when using these
instructions in cases where a register containing a write-only bit is used or a bit is directly
manipulated for a port.
In addition, the BCLR instruction can be used to clear the flag of the internal I/O register. In this
case, if the flag to be cleared has been set to 1 by an interrupt processing routine, the flag need not
be read before executing the BCLR instruction.
Rev. 1.00, 05/04, page 49 of 544
2.9.4 EEPMOV Instruction
1. EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4L,
which starts from the address indicated by R5, to the address indicated by R6.
R6
R6 + R4L
R5
R5 + R4L
2. Set R4L and R6 so that the end address of the destination address (value of R6 + R4L) does
not exceed H'FFFF (the value of R6 must not change from H'FFFF to H'0000 during
execution).
Invalid H'FFFF
R6
R6 + R4L
R5
R5 + R4L
Rev. 1.00, 05/04, page 50 of 544
Rev. 1.00, 05/04, page 51 of 544
Section 3 MCU Operating Modes
3.1 MCU Operating Mode Selection
This LSI has two operating modes (modes 2 and 3). The operating mode is determined by the
setting of the mode pins (MD1 and MD0). Table 3.1 shows the MCU operating mode selection.
Table 3.1 lists the MCU operating modes.
Table 3.1 MCU Operating Mode Selection
MCU
Operating
Mode MD1 MD0
CPU
Operating
Mode Description On-Chip ROM
2 0 Advanced Single-chip mode
3
1
1 Normal Single-chip mode
Enabled
Modes 2 and 3 set the operation in single-chip mode.
Modes 0 and 1 cannot be used in this LSI. Thus, mode pins should be set to enable mode 2 or 3 in
normal program execution state. Mode pins should not be changed during operation.
Rev. 1.00, 05/04, page 52 of 544
3.2 Register Descriptions
The following registers are related to the operating mode.
Mode control register (MDCR)
System control register (SYSCR)
Serial timer control register (STCR)
3.2.1 Mode Control Register (MDCR)
MDCR is used to monitor the current operating mode.
Bit Bit Name
Initial
Value R/W Description
7 EXPE 0
R/W Reserved
The initial value should not be changed.
6
to
2
— All 0 R Reserved
These bits are always read as 0. These bits cannot be
modified.
1
0
MDS1
MDS0
*
*
R
R
Mode Select 1 and 0
These bits indicate the input levels at mode pins (MD1
and MD0) (the current operating mode). Bits MDS1
and MDS0 correspond to MD1 and MD0, respectively.
These bits are read-only bits and they cannot be
written to. The mode pin (MD1 and MD0) input levels
are latched into these bits when MDCR is read. These
latches are canceled by a reset.
Note: * The initial values are determined by the settings of the MD1 and MD0 pins.
Rev. 1.00, 05/04, page 53 of 544
3.2.2 System Control Register (SYSCR)
SYSCR selects a system pin function, monitors a reset source, selects the interrupt control mode
and the detection edge for NMI, pin location selection, enables or disables register access to the
on-chip peripheral modules, and enables or disables on-chip RAM address space.
Bit Bit Name
Initial
Value R/W Description
7 and 6 All 0 R/W Reserved
The initial value should not be changed.
5
4
INTM1
INTM0
0
0
R
R/W
These bits select the control mode of the interrupt
controller. For details on the interrupt control modes
and interrupt control select modes 1 and 0, see
section 5.6, Interrupt Control Modes and Interrupt
Operation.
00: Interrupt control mode 0
01: Interrupt control mode 1
10: Setting prohibited
11: Setting prohibited
3 XRST 1 R External Reset
This bit indicates the reset source. A reset is caused
by an external reset input, or when the watchdog
timer overflows.
0: A reset is caused when the watchdog timer
overflows.
1: A reset is caused by an external reset.
2 NMIEG 0 R/W NMI Edge Select
Selects the valid edge of the NMI interrupt input.
0: An interrupt is requested at the falling edge of NMI
input
1: An interrupt is requested at the rising edge of NMI
input
Rev. 1.00, 05/04, page 54 of 544
Bit Bit Name
Initial
Value R/W Description
1 HIE 0 R/W Host Interface Enable
Controls CPU access to the keyboard matrix interrupt,
input pull-up MOS control registers (KMIMR, KMPCR,
and KMIMRA), and the 8-bit timer (TMR_X and
TMR_Y) registers (TCR_X/TCR_Y, TCSR_X/TCSR_Y,
TICRR/TCORA_Y, TICRF/TCORB_Y,
TCNT_X/TCNT_Y, TCORC/TISR, TCORA_X, and
TCORB_X, TCONRI, and TCONRS).
0: In areas H'(FF)FFF0 to H'(FF)FFF7 and H'(FF)FFFC
to H'(FF)FFFF, CPU access to 8-bit timer (TMR_X
and TMR_Y) is permitted.
1: In areas H'(FF)FFF0 to H'(FF)FFF7 and H'(FF)FFFC
to H'(FF)FFFF, CPU access to keyboard matrix
interrupt and input pull-up MOS control registers is
permitted.
0 RAME 1 R/W RAM Enable
Enables or disables on-chip RAM. The RAME bit is
initialized when the reset state is released.
0: On-chip RAM is disabled
1: On-chip RAM is enabled
Rev. 1.00, 05/04, page 55 of 544
3.2.3 Serial Timer Control Register (STCR)
STCR enables or disables register access, IIC operating mode, and on-chip flash memory, and
selects the input clock of the timer counter.
Bit Bit Name
Initial
Value R/W Description
7 IICS 0 R/W I2C Extra Buffer Select
Specifies bits 7 to 4 of port A as output buffers similar
to SLC and SDA. These pins are used to implement
an I2C interface only by software.
0: PA7 to PA4 are normal input/output pins.
1: PA7 to PA4 are input/output pins enabling bus
driving.
6
5
IICX1
IICX0
0
0
R/W
R/W
I2C Transfer Rate Select 1 and 0
These bits control the IIC operation. These bits select
a transfer rate in master mode together with bits
CKS2 to CKS0 in the I2C bus mode register (ICMR).
For details on the transfer rate, refer to table 13.3.
4 IICE 0 R/W I2C Master Enable
Enables or disables CPU access for IIC registers
(ICCR, ICSR, ICDR/SARX, ICMR/SAR), and SCI
registers (SMR, BRR, SCMR).
0: SCI_1 registers are accessed in an area from
H'(FF)FF88 to H'(FF)FF89 and from H'(FF)FF8E to
H'(FF)FF8F.
1: IIC_1 registers are accessed in an area from
H'(FF)FF88 to H'(FF)FF89 and from H'(FF)FF8E to
H'(FF)FF8F.
IIC_0 registers are accessed in an area from
H'(FF)FFD8 to H'(FF)FFD9 and from H'(FF)FFDE to
H'(FF)FFDF.
Rev. 1.00, 05/04, page 56 of 544
Bit Bit Name Initial
Value R/W Description
3 FLSHE 0 R/W Flash Memory Control Register Enable
Enables or disables CPU access for flash memory
registers (FLMCR1, FLMCR2, EBR1, EBR2), control
registers in power-down state (SBYCR, LPWRCR,
MSTPCRH, MSTPCRL), and control registers of on-
chip peripheral modules (PCSR, SYSCR2).
0: Registers in power-down state and control registers
of on-chip peripheral modules are accessed in an
area from H'(FF)FF80 to H'(FF)FF87.
1: Control registers of flash memory are accessed in
an area from H'(FF)FF80 to H'(FF)FF87.
2 — 0 R/(W) Reserved
The initial value should not be changed.
1
0
ICKS1
ICKS0
0
0
R/W
R/W
Internal Clock Source Select 1, 0
These bits select a clock to be input to the timer
counter (TCNT) and a count condition together with
bits CKS2 to CKS0 in the timer control register (TCR).
For details, refer to section 10.3.4, Timer Control
Register (TCR).
3.3 Operating Mode Descriptions
3.3.1 Mode 2
The CPU can access a 16-Mbyte address space in advanced single-chip mode. The on-chip ROM
is enabled.
3.3.2 Mode 3
The CPU can access a 64-Kbyte address space in normal single-chip mode. The on-chip ROM is
enabled. The CPU can access a 56-kbyte address space in mode 3.
Rev. 1.00, 05/04, page 57 of 544
3.4 Address Map
Figures 3.1 and 3.2 show the address map in each operating mode.
Mode 2 (EXPE = 0)
Advanced mode
Single-chip mode
On-chip ROM
Internal I/O
registers 2
On-chip RAM
Internal I/O
registers 1
On-chip RAM
(128 bytes)
Internal I/O
registers 3
Reserved area
Reserved area
H'01FFFF
H'000000
H'FFE080
H'FFE880
H'FFFEFF
H'FFFFFF
H'FFFE50
H'FFFF7F
H'FFFF80
H'FFFF00
H'FFF800
H'FFFE4F
H'FFEFFF
H'00FFFF
Mode 3 (EXPE = 0)
Normal mode
Single-chip mode
H'DFFF
H'0000
On-chip ROM
Internal I/O
registers 2
On-chip RAM
Internal I/O
registers 1
H'EFFF
H'E080
H'E880
H'FEFF
H'FFFF
H'FE50
H'FF7F
H'FF80
H'FF00 On-chip RAM
(128 bytes)
Internal I/O
registers 3
H'F800
H'FE4F
Reserved area
Figure 3.1 Address Map for H8S/2111B-B
Rev. 1.00, 05/04, page 58 of 544
Mode 2 (EXPE = 0)
Advanced mode
Single-chip mode
On-chip ROM
Internal I/O
registers 2
On-chip RAM
Internal I/O
registers 1
On-chip RAM
(128 bytes)
Internal I/O
registers 3
Reserved area
Reserved area
H'01FFFF
H'000000
H'FFE080
H'FFE480
H'FFFEFF
H'FFFFFF
H'FFFE50
H'FFFF7F
H'FFFF80
H'FFFF00
H'FFF800
H'FFFE4F
H'FFEFFF
H'00FFFF
Mode 3 (EXPE = 0)
Normal mode
Single-chip mode
H'DFFF
H'0000
On-chip ROM
Internal I/O
registers 2
On-chip RAM
Internal I/O
registers 1
H'EFFF
H'E080
H'E480
H'FEFF
H'FFFF
H'FE50
H'FF7F
H'FF80
H'FF00 On-chip RAM
(128 bytes)
Internal I/O
registers 3
H'F800
H'FE4F
Reserved area
Figure 3.2 Address Map for H8S/2111B-C
Rev. 1.00, 05/04, page 59 of 544
Section 4 Exception Handling
4.1 Exception Handling Types and Priority
As table 4.1 indicates, exception handling may be caused by a reset, interrupt, direct transition, or
trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions
occur simultaneously, they are accepted and processed in order of priority.
Table 4.1 Exception Types and Priority
Priority Exception Type Start of Exception Handling
Reset Starts immediately after a low-to-high transition of the RES
pin, or when the watchdog timer overflows.
Interrupt Starts when execution of the current instruction or exception
handling ends, if an interrupt request has been issued.
Interrupt detection is not performed on completion of ANDC,
ORC, XORC, or LDC instruction execution, or on
completion of reset exception handling.
High
Direct transition Starts when a direction transition occurs as the result of
SLEEP instruction execution.
Low
Trap instruction Started by execution of a trap (TRAPA) instruction. Trap
instruction exception handling requests are accepted at all
times in program execution state.
Rev. 1.00, 05/04, page 60 of 544
4.2 Exception Sources and Exception Vector Table
Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception
sources and their vector addresses.
Table 4.2 Exception Handling Vector Table
Vector Address
Exception Source Vector Number Normal Mode Advanced Mode
Reset 0 H'0000 to H'0001 H'000000 to H'000003
Reserved for system use 1
5
H'0002 to H'0003
|
H'000A to H'000B
H'000004 to H'000007
|
H'000014 to H'000017
Direct transition 6 H'000C to H'000D H'000018 to H'00001B
External interrupt (NMI) 7 H'000E to H'000F H'00001C to H'00001F
8 H'0010 to H'0011 H'000020 to H'000023
9 H'0012 to H'0013 H'000024 to H'000027
10 H'0014 to H'0015 H'000028 to H'00002B
Trap instruction (four
sources)
11 H'0016 to H'0017 H'00002C to H'00002F
Reserved for system use 12
15
H'0018 to H'0019
|
H'001E to H'001F
H'000030 to H'000033
|
H'00003C to H'00003F
IRQ0 16 H'0020 to H'0021 H'000040 to H'000043
IRQ1 17 H'0022 to H'0023 H'000044 to H'000047
IRQ2 18 H'0024 to H'0025 H'000048 to H'00004B
IRQ3 19 H'0026 to H'0027 H'00004C to H'00004F
IRQ4 20 H'0028 to H'0029 H'000050 to H'000053
IRQ5 21 H'002A to H'002B H'000054 to H'000057
IRQ6 22 H'002C to H'002D H'000058 to H'00005B
External interrupt
IRQ7 23 H'002E to H'002F H'00005C to H'00005F
Internal interrupt* 24
111
H'0030 to H'0031
H'00DE to H'00DF
H'000060 to H'000063
H'0001BC to H'0001BF
Note: * For details on the internal interrupt vector table, see section 5.5, Interrupt Exception
Handling Vector Table.
Rev. 1.00, 05/04, page 61 of 544
4.3 Reset
A reset has the highest exception priority. When the RES pin goes low, all processing halts and
this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at
power-on. To reset the chip during operation, hold the RES pin low for at least 20 states. A reset
initializes the internal state of the CPU and the registers of on-chip peripheral modules. The chip
can also be reset by overflow of the watchdog timer. For details, see section 11, Watchdog Timer
(WDT).
4.3.1 Reset Exception Handling
When the RES pin goes high after being held low for the necessary time, this LSI starts reset
exception handling as follows:
1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized
and the I bit is set to 1 in CCR.
2. The reset exception handling vector address is read and transferred to the PC, and program
execution starts from the address indicated by the PC.
Figure 4.1 shows an example of the reset sequence.
φ
RES
Internal address bus
Internal read signal
Internal write signal
Internal data bus
Vector
fetch
(1) Reset exception handling vector address ((1) = H'0000)
(2) Start address (contents of reset exception handling vector address)
(3) Start address ((3) = (2))
(4) First program instruction
(1) (3)
High
Internal
processing
Prefetch of first program
instruction
(2) (4)
Figure 4.1 Reset Sequence (Mode 3)
Rev. 1.00, 05/04, page 62 of 544
4.3.2 Interrupts after Reset
If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.L #xx: 32, SP).
4.3.3 On-Chip Peripheral Modules after Reset is Cancelled
After a reset is cancelled, the module stop control registers (MSTPCR) are initialized, and all
modules operate in module stop mode. Therefore, the registers of on-chip peripheral modules
cannot be read from or written to. To read from and write to these registers, clear module stop
mode.
Rev. 1.00, 05/04, page 63 of 544
4.4 Interrupt Exception Handling
Interrupts are controlled by the interrupt controller. The sources to start interrupt exception
handling are external interrupt sources (NMI, IRQ7 to IRQ0, KIN15 to KIN0, and WUE7 to
WUE0) and internal interrupt sources from the on-chip peripheral modules. NMI is an interrupt
with the highest priority. For details, refer to section 5, Interrupt Controller.
Interrupt exception handling is conducted as follows:
1. The values in the program counter (PC) and condition code register (CCR) are saved to the
stack.
2. A vector address corresponding to the interrupt source is generated, the start address is loaded
from the vector table to the PC, and program execution begins from that address.
4.5 Trap Instruction Exception Handling
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state.
Trap instruction exception handling is conducted as follows:
1. The values in the program counter (PC) and condition code register (CCR) are saved to the
stack.
2. A vector address corresponding to the interrupt source is generated, the start address is loaded
from the vector table to the PC, and program execution starts from that address.
The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector
number from 0 to 3, as specified in the instruction code.
Table 4.3 shows the status of CCR after execution of trap instruction exception handling.
Table 4.3 Status of CCR after Trap Instruction Exception Handling
CCR
Interrupt Control Mode I UI
0 1
1 1 1
[Legend]
1: Set to 1
—: Retains value prior to execution
Rev. 1.00, 05/04, page 64 of 544
4.6 Stack Status after Exception Handling
Figure 4.2 shows the stack after completion of trap instruction exception handling and interrupt
exception handling.
CCR
CCR*
PC
(16 bits)
Note: Ignored on return.
Normal mode Advanced mode
CCR
PC
(24 bits)
SP SP
Figure 4.2 Stack Status after Exception Handling
Rev. 1.00, 05/04, page 65 of 544
4.7 Usage Note
When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The
stack should always be accessed in words or longwords, and the value of the stack pointer (SP:
ER7) should always be kept even.
Use the following instructions to save registers:
PUSH.W Rn (or MOV.W Rn, @-SP)
PUSH.L ERn (or MOV.L ERn, @-SP)
Use the following instructions to restore registers:
POP.W Rn (or MOV.W @SP+, Rn)
POP.L ERn (or MOV.L @SP+, ERn)
Setting SP to an odd value may lead to a malfunction. Figure 4.3 shows an example of what
happens when the SP value is odd.
SP
CCR:
PC:
R1L:
SP:
Condition code register
Program counter
General register R1L
Stack pointer
CCR
SP
SP R1L H'FFEFFA
H'FFEFFB
H'FFEFFC
H'FFEFFD
H'FFEFFF
PC PC
TRAPA instruction executed
SP set to H'FFFEFF Data saved above SP
MOV.B R1L, @-ER7 executed
Contents of CCR lost
Address
[Legend]
Note: This diagram illustrates an example in which the interrupt control mode is 0 in advanced mode.
Figure 4.3 Operation when SP Value is Odd
Rev. 1.00, 05/04, page 66 of 544
Rev. 1.00, 05/04, page 67 of 544
Section 5 Interrupt Controller
5.1 Features
Two interrupt control modes
Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the
system control register (SYSCR).
Priorities settable with ICR
An interrupt control register (ICR) is provided for setting interrupt priorities. Three priority
levels can be set for each module for all interrupts except NMI and address break.
Independent vector addresses
All interrupt sources are assigned independent vector addresses, making it unnecessary for the
source to be identified in the interrupt handling routine.
Thirty-one external interrupts
NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge
detection can be selected for NMI. Falling-edge, rising-edge, or both-edge detection, or level
sensing, can be selected for IRQ7 to IRQ0. The IRQ6 interrupt is shared by the interrupt from
the IRQ6 pin and eight external interrupt inputs (KIN7 to KIN0), and the IRQ7 interrupt is
shared by the interrupt from the IRQ7 pin and sixteen external interrupt inputs (KIN15 to
KIN8 and WUE7 to WUE0). KIN15 to KIN0 and WUE7 to WUE0 can be masked
individually by the user program.
Rev. 1.00, 05/04, page 68 of 544
SYSCR
NMI input
IRQ input
Internal
interrupt request
WOVI0 to IBFI3
NMIEG
INTM1, INTM0
NMI input
IRQ input
ISR
ISCR IER
ICR
Interrupt controller
Priority check
Interrupt
request
Vector number
I, UI CCR
CPU
ICR:
ISCR:
IER:
ISR:
Interrupt control register
IRQ sense control register
IRQ enable register
IRQ status register
KMIMR:
WUEMR:
SYSCR:
Keyboard matrix interrupt mask register
Wake-up event interrupt mask register
System control register
[Legend]
KIN and WUE
input
KMIMR
WUEMR
KIN input
WUE input
Figure 5.1 Block Diagram of Interrupt Controller
5.2 Input/Output Pins
Table 5.1 summarizes the pins of the interrupt controller.
Table 5.1 Pin Configuration
Symbol I/O Function
NMI Input Nonmaskable external interrupt
Rising edge or falling edge can be selected
IRQ7 to IRQ0 Input Maskable external interrupts
Rising edge, falling edge, both edges, or level sensing,
can be selected individually for each pin.
KIN15 to KIN0 Input Maskable external interrupts
Falling edge or level sensing can be selected.
WUE7 to WUE0 Input Maskable external interrupts
Falling edge or level sensing can be selected.
Rev. 1.00, 05/04, page 69 of 544
5.3 Register Descriptions
The interrupt controller has the following registers. For details on the system control register
(SYSCR), refer to section 3.2.2, System Control Register (SYSCR).
Interrupt control registers A to C (ICRA to ICRC)
Address break control register (ABRKCR)
Break address registers A to C (BARA to BARC)
IRQ sense control registers (ISCRH, ISCRL)
IRQ enable register (IER)
IRQ status register (ISR)
Keyboard matrix interrupt mask registers (KMIMRA, KMIMR)
Wake-up event interrupt mask register (WUEMRB)
5.3.1 Interrupt Control Registers A to C (ICRA to ICRC)
The ICR registers set interrupt control levels for interrupts other than NMI and address breaks.
The correspondence between interrupt sources and ICRA to ICRC settings is shown in table 5.2.
Bit Bit Name
Initial
Value R/W Description
7 to 0 ICRn7 to
IRCn0
All 0 R/W Interrupt Control Level
0: Corresponding interrupt source is interrupt control
level 0 (no priority)
1: Corresponding interrupt source is interrupt control
level 1 (priority)
[Legend]
n: A to C
Rev. 1.00, 05/04, page 70 of 544
Table 5.2 Correspondence between Interrupt Source and ICR
Register
Bit Bit Name ICRA ICRB ICRC
7 ICRn7 IRQ0
6 ICRn6 IRQ1 FRT SCI_1
5 ICRn5 IRQ2, IRQ3
4 ICRn4 IRQ4, IRQ5 IIC_0
3 ICRn3 IRQ6, IRQ7 TMR_0 IIC_1
2 ICRn2 TMR_1 TMR_A, TMR_B
1 ICRn1 WDT_0 TMR_X, TMR_Y LPC
0 ICRn0 WDT_1 Keyboard buffer controller
[Legend]
n: A to C
: Reserved. The write value should always be 0.
5.3.2 Address Break Control Register (ABRKCR)
ABRKCR controls the address breaks. When both the CMF flag and BIE flag are set to 1, an
address break is requested.
Bit Bit Name Initial
Value R/W Description
7 CMF 0 R Condition Match Flag
Address break source flag. Indicates that an address
specified by BARA to BARC is prefetched.
[Setting condition]
When an address specified by BARA to BARC is
prefetched while the BIE flag is set to 1.
[Clearing condition]
When an exception handling is executed for an
address break interrupt.
6
to
1
— All 0 R Reserved
These bits are always read as 0 and cannot be
modified.
0 BIE 0 R/W Break Interrupt Enable
Enables or disables address break.
0: Disabled
1: Enabled
Rev. 1.00, 05/04, page 71 of 544
5.3.3 Break Address Registers A to C (BARA to BARC)
The BAR registers specify an address that is to be a break address. An address in which the first
byte of an instruction exists should be set as a break address. In normal mode, addresses A23 to
A16 are not compared.
BARA
Bit Bit Name Initial
Value R/W Description
7
to
0
A23
to
A16
All 0 R/W Addresses 23 to 16
The A23 to A16 bits are compared with A23 to A16 in
the internal address bus.
BARB
Bit Bit Name Initial
Value R/W Description
7
to
0
A15
to
A8
All 0 R/W Addresses 15 to 8
The A15 to A8 bits are compared with A15 to A8 in the
internal address bus.
BARC
Bit Bit Name Initial
Value R/W Description
7
to
1
A7
to
A1
All 0 R/W Addresses 7 to 1
The A7 to A1 bits are compared with A7 to A1 in the
internal address bus.
0 — 0 R Reserved
This bit is always read as 0 and cannot be modified.
Rev. 1.00, 05/04, page 72 of 544
5.3.4 IRQ Sense Control Registers (ISCRH, ISCRL)
The ISCR registers select the source that generates an interrupt request at pins IRQ7 to IRQ0.
ISCRH
Bit Bit Name Initial
Value R/W Description
7
6
IRQ7SCB
IRQ7SCA
0
0
R/W
R/W
5
4
IRQ6SCB
IRQ6SCA
0
0
R/W
R/W
3
2
IRQ5SCB
IRQ5SCA
0
0
R/W
R/W
1
0
IRQ4SCB
IRQ4SCA
0
0
R/W
R/W
IRQn Sense Control B
IRQn Sense Control A
00: Interrupt request generated at low level of IRQn
input
01: Interrupt request generated at falling edge of IRQn
input
10: Interrupt request generated at rising edge of IRQn
input
11: Interrupt request generated at both falling and
rising edges of IRQn input
(n = 7 to 4)
ISCRL
Bit Bit Name Initial
Value R/W Description
7
6
IRQ3SCB
IRQ3SCA
0
0
R/W
R/W
5
4
IRQ2SCB
IRQ2SCA
0
0
R/W
R/W
3
2
IRQ1SCB
IRQ1SCA
0
0
R/W
R/W
1
0
IRQ0SCB
IRQ0SCA
0
0
R/W
R/W
IRQn Sense Control B
IRQn Sense Control A
00: Interrupt request generated at low level of IRQn
input
01: Interrupt request generated at falling edge of IRQn
input
10: Interrupt request generated at rising edge of IRQn
input
11: Interrupt request generated at both falling and
rising edges of IRQn input
(n = 3 to 0)
Rev. 1.00, 05/04, page 73 of 544
5.3.5 IRQ Enable Register (IER)
IER controls the enabling and disabling of interrupt requests IRQ7 to IRQ0.
Bit Bit Name Initial
Value R/W Description
7
6
5
4
3
2
1
0
IRQ7E
IRQ6E
IRQ5E
IRQ4E
IRQ3E
IRQ2E
IRQ1E
IRQ0E
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IRQn Enable (n = 7 to 0)
The IRQn interrupt request is enabled when this bit is
1.
5.3.6 IRQ Status Register (ISR)
The ISR register is a flag register that indicates the status of IRQ7 to IRQ0 interrupt requests.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
0
IRQ7F
IRQ6F
IRQ5F
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
0
0
0
0
0
0
0
0
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
[Setting condition]
When the interrupt source selected by the ISCR
registers occurs
[Clearing conditions]
When reading IRQnF flag when IRQnF = 1, then
writing 0 to IRQnF flag
When interrupt exception handling is executed when
low-level detection is set and IRQn input is high
(n = 7 to 0)
When IRQn interrupt exception handling is executed
when falling-edge, rising-edge, or both-edge detection
is set
Note: * Only 0 can be written, for flag clearing.
5.3.7 Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR)
Wake-Up Event Interrupt Mask Register (WUEMRB)
The KMIMRA, KMIMR, and WUEMRB registers enable or disable key-sensing interrupt inputs
(KIN15 to KIN0), and wake-up event interrupt inputs (WUE7 to WUE0).
Rev. 1.00, 05/04, page 74 of 544
KMIMRA
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
0
KMIMR15
KMIMR14
KMIMR13
KMIMR12
KMIMR11
KMIMR10
KMIMR9
KMIMR8
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Keyboard Matrix Interrupt Mask 15 to 8
These bits enable or disable a key-sensing input
interrupt request (KIN15 to KIN8).
0: Enables a key-sensing input interrupt request
1: Disables a key-sensing input interrupt request
KMIMR
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
0
KMIMR7
KMIMR6
KMIMR5
KMIMR4
KMIMR3
KMIMR2
KMIMR1
KMIMR0
1
0
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Keyboard Matrix Interrupt Mask 7 to 0
These bits enable or disable a key-sensing input
interrupt request (KIN7 to KIN0).
KMIMR6 also performs interrupt request mask control
for pin IRQ6.
0: Enables a key-sensing input interrupt request
1: Disables a key-sensing input interrupt request
WUEMRB
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
0
WUEMR7
WUEMR6
WUEMR5
WUEMR4
WUEMR3
WUEMR2
WUEMR1
WUEMR0
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Wake-Up Event Interrupt Mask 7 to 0
These bits enable or disable a wake-up event input
interrupt request (WUE7 to WUE0).
0: Enables a wake-up event input interrupt request
1: Disables a wake-up event input interrupt request
Rev. 1.00, 05/04, page 75 of 544
Figure 5.2 shows the relationship between interrupts IRQ7 and IRQ6, interrupts KIN15 to KIN0,
interrupts WUE7 to WUE0, and registers KMIMRA, KMIMR, and WUEMRB.
IRQ6 internal signal
IRQ6E
Edge level
selection
enable/disable
circuit
Edge level
selection
enable/disable
circuit
IRQ6SC
IRQ6
interrupt
KMIMR0 (initial value 1)
P60/KIN0
KMIMR5 (initial value 1)
P65/KIN5
KMIMR6 (initial value 0)
P66/KIN6/IRQ6
KMIMR7 (initial value 1)
P67/KIN7/IRQ7
IRQ7 internal signal
IRQ7E
IRQ7SC
IRQ7
interrupt
KMIMR8 (initial value 1)
PA0/KIN8
KMIMR9 (initial value 1)
PA1/KIN9
WUEMR7 (initial value 1)
PB7/WUE7
Figure 5.2 Relationship between Interrupts IRQ7 and IRQ6, Interrupts KIN15 to KIN0,
Interrupts WUE7 to WUE0, and Registers KMIMR, KMIMRA, and WUEMRB
If any of bits KMIMR15 to KMIMR8 or WUEMRB7 to WUEMRB0 is cleared to 0, interrupt
input from the IRQ7 pin will be ignored. When pins KIN7 to KIN0, KIN15 to KIN8, or WUE7 to
WUE0 are used as key-sense interrupt input pins or wakeup event interrupt input pins, either low-
level sensing or falling-edge sensing must be designated as the interrupt sense condition for the
corresponding interrupt source (IRQ6 or IRQ7).
Rev. 1.00, 05/04, page 76 of 544
5.4 Interrupt Sources
5.4.1 External Interrupts
There are four types of external interrupts: NMI, IRQ7 to IRQ0, KIN15 to KIN0 and WUE7 to
WUE0. WUE7 to WUE0 and KIN15 to KIN8 share the IRQ7 interrupt source, and KIN7 to KIN0
share the IRQ6 interrupt source. Of these, NMI, IRQ7, IRQ6, and IRQ2 to IRQ0 can be used to
restore this LSI from software standby mode.
NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU
regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG
bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling
edge on the NMI pin.
IRQ7 to IRQ0 Interrupts: Interrupts IRQ7 to IRQ0 are requested by an input signal at pins IRQ7
to IRQ0. Interrupts IRQ7 to IRQ0 have the following features:
The interrupt exception handling for interrupt requests IRQ7 to IRQ0 can be started at an
independent vector address.
Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling
edge, rising edge, or both edges, at pins IRQ7 to IRQ0.
Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER.
Interrupt control levels can be specified by the ICR settings.
The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0
by software.
The detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been
set for input or output. However, when a pin is used as an external interrupt input pin, do not clear
the corresponding DDR to 0 to use the pin as an I/O pin for another function.
A block diagram of interrupts IRQ7 to IRQ0 is shown in figure 5.3.
IRQn interrupt
request
IRQnE
IRQnF
S
R
Q
Clear signal
Edge/level
detection circuit
IRQnSCA, IRQnSCB
IRQn input
n = 7 to 0
Figure 5.3 Block Diagram of Interrupts IRQ7 to IRQ0
When pin IRQ6 is used as an IRQ6 interrupt input pin, clear the KMIMR6 bit to 0.
Rev. 1.00, 05/04, page 77 of 544
When pin IRQ7 is used as an IRQ7 interrupt pin, set all of bits KMIMR15 to KMIMR8 and
WUEMR7 to WUEMR0 to 1. If any of these bits is cleared to 0, IRQ7 interrupt input from the
IRQ7 pin will be ignored.
Since interrupt request flags IRQ7F to IRQ0F are set each time the setting condition is satisfied,
regardless of the IER setting, refer to a needed flag only.
KIN15 to KIN0 Interrupts, WUE7 to WUE0 Interrupts: Interrupts KIN15 to KIN0 and WUE7
to WUE0 are requested by an input signal at pins KIN15 to KIN0 and WUE7 to WUE0. When
pins KIN15 to KIN0 and WUE7 to WUE0 are used for key-sense input or wakeup event, clear the
corresponding KMIMR and WUEMR bits to 0 in order to enable their key-sense input and
wakeup event interrupts. Remaining unused KMIMR and WUEMR bits for key-sense input
should be set to 1 in order to disable interrupts. Interrupts WUE7 to WUE0 and KIN15 to KIN8
generate IRQ7 interrupts, and interrupts KIN7 to KIN0 generate IRQ6 interrupts. The pin
conditions for interrupt request generation, enable of interrupt requests, settings of interrupt
control levels, and status display of interrupt requests depend on each setting and display of the
IRQ7 or IRQ6 interrupt.
When pins KIN7 to KIN0, KIN15 to KIN8, or WUE7 to WUE0 are used as key-sense interrupt
input pins or wakeup event interrupt input pins, either low-level sensing or falling-edge sensing
must be designated as the interrupt sense condition for the corresponding interrupt source (IRQ6
or IRQ7).
5.4.2 Internal Interrupts
Internal interrupts issued from the on-chip peripheral modules have the following features:
1. For each on-chip peripheral module there are flags that indicate the interrupt request status,
and enable bits that individually select enabling or disabling of these interrupts. When the
enable bit for a particular interrupt source is set to 1, an interrupt request is sent to the interrupt
controller.
2. The control level for each interrupt can be set by ICR.
Rev. 1.00, 05/04, page 78 of 544
5.5 Interrupt Exception Handling Vector Table
Table 5.3 lists interrupt exception handling sources, vector addresses, and interrupt priorities. For
default priorities, the lower the vector number, the higher the priority. Modules set at the same
priority will conform to their default priorities. Priorities within a module are fixed.
An interrupt control level can be specified for a module to which an ICR bit is assigned. Interrupt
requests from modules that are set to control level 1 (priority) by the ICR bit setting and the I and
UI bits in CCR are given priority and processed before interrupt requests from modules that are set
to control level 0 (no priority).
Table 5.3 Interrupt Sources, Vector Addresses, and Interrupt Priorities
Vector Address
Origin of
Interrupt
Source Name Vector
Number Normal
Mode Advanced
Mode ICR Priority
NMI 7 H'000E H'00001C High
IRQ0 16 H'0020 H'000040 ICRA7
IRQ1 17 H'0022 H'000044 ICRA6
IRQ2
IRQ3
18
19
H'0024
H'0026
H'000048
H'00004C
ICRA5
IRQ4
IRQ5
20
21
H'0028
H'002A
H'000050
H'000054
ICRA4
External pin
IRQ6, KIN7 to KIN0
IRQ7, KIN15 to KIN8, WUE7 to
WUE0
22
23
H'002C
H'002E
H'000058
H'00005C
ICRA3
Reserved for system use 24 H'0030 H'000060
WDT_0 WOVI0 (Interval timer) 25 H'0032 H'000064 ICRA1
WDT_1 WOVI1 (Interval timer) 26 H'0034 H'000068 ICRA0
— Address break 27 H'0036 H'00006C
Reserved for system use 28
to
47
H'0038
to
H'005E
H'000070
to
H'0000BC
FRT ICIA (Input capture A)
ICIB (Input capture B)
ICIC (Input capture C)
ICID (Input capture D)
OCIA (Output compare A)
OCIB (Output compare B)
FOVI (Overflow)
Reserved for system use
48
49
50
51
52
53
54
55
H'0060
H'0062
H'0064
H'0066
H'0068
H'006A
H'006C
H'006E
H'0000C0
H'0000C4
H'0000C8
H'0000CC
H'0000D0
H'0000D4
H'0000D8
H'0000DC
ICRB6
Reserved for system use 56
to
63
H'0070
to
H'007E
H'0000E0
to
H'0000FC
Low
Rev. 1.00, 05/04, page 79 of 544
Vector Address
Origin of
Interrupt
Source Name Vector
Number Normal
Mode Advanced
Mode ICR Priority
TMR_0 CMIA0 (Compare match A)
CMIB0 (Compare match A)
OVI0 (Overflow)
Reserved for system use
64
65
66
67
H'0080
H'0082
H'0084
H'0086
H'000100
H'000104
H'000108
H'00010C
ICRB3 High
TMR_1 CMIA1 (Compare match A)
CMIB1 (Compare match B)
OVI1 (Overflow)
Reserved for system use
68
69
70
71
H'0088
H'008A
H'008C
H'008E
H'000110
H'000114
H'000118
H'00011C
ICRB2
TMR_X,
TMR_Y
CMIAY (Compare match A)
CMIBY (Compare match B)
OVIY (Overflow)
ICIX (Input capture X)
72
73
74
75
H'0090
H'0092
H'0094
H'0096
H'000120
H'000124
H'000128
H'00012C
ICRB1
Reserved for system use 76
to
83
H'0098
to
H'00A6
H'000130
to
H'00014C
SCI_1 ERI1 (Reception error 1)
RXI1 (Reception completion 1)
TXI1 (Transmission data empty 1)
TEI1 (Transmission end 1)
84
85
86
87
H'00A8
H'00AA
H'00AC
H'00AE
H'000150
H'000154
H'000158
H'00015C
ICRC6
Reserved for system use 88
to
91
H'00B0
to
H'00B6
H'000160
to
H'00016C
IIC_0 IICI0 (1-byte transmission/
reception completion)
Reserved for system use
92
93
H'00B8
H'00BA
H'000170
H'000174
ICRC4
IIC_1 IICI1 (1-byte transmission/
reception completion)
Reserved for system use
94
95
H'00BC
H'00BE
H'000178
H'00017C
ICRC3
Keyboard
buffer
controller
KBIA (Reception completion A)
KBIB (Reception completion B)
KBIC (Reception completion C)
Reserved for system use
96
97
98
99
H'00C0
H'00C2
H'00C4
H'00C6
H'000180
H'000184
H'000188
H'00018C
ICRB0
TMR_A,
TMR_B
CMIAAB (Compare match A)
CMIBAB (Compare match B)
OVIAB (Overflow)
ICIA (Input capture A)
100
101
102
103
H'00C8
H'00CA
H'00CC
H'00CE
H'000190
H'000194
H'000198
H'00019C
ICRC2
Reserved for system use 104
to
107
H'00D0
to
H'00D6
H'0001A0
to
H'0001AC
LPC ERRI (Transfer error)
IBF1 (IDR1 reception completion)
IBF2 (IDR2 reception completion)
IBF3 (IDR3 reception completion)
108
109
110
111
H'00D8
H'00DA
H'00DC
H'00DE
H'0001B0
H'0001B4
H'0001B8
H'0001BC
ICRC1
Low
Rev. 1.00, 05/04, page 80 of 544
5.6 Interrupt Control Modes and Interrupt Operation
The interrupt controller has two modes: Interrupt control mode 0 and interrupt control mode 1.
Interrupt operations differ depending on the interrupt control mode. NMI interrupts and address
break interrupts are always accepted except for in reset state or in hardware standby mode. The
interrupt control mode is selected by SYSCR. Table 5.4 shows the interrupt control modes.
Table 5.4 Interrupt Control Modes
SYSCR
Interrupt
Control
Mode INTM1 INTM0
Priority
Setting
Registers Interrupt
Mask Bits Description
0 0 ICR I Interrupt mask control is performed by
the I bit. Priority levels can be set with
ICR.
1
0
1 ICR I, UI 3-level interrupt mask control is
performed by the I bit. Priority levels
can be set with ICR.
5.6.1 Interrupt Control Mode 0
In interrupt control mode 0, interrupt requests other than NMI and address breaks are masked by
ICR and the I bit of the CCR in the CPU. Figure 5.4 shows a flowchart of the interrupt acceptance
operation.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
2. According to the interrupt control level specified in ICR, the interrupt controller only accepts
an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt
request with interrupt control level 0 (no priority). If several interrupt requests are issued, an
interrupt request with the highest priority is accepted according to the priority order, an
interrupt handling is requested to the CPU, and other interrupt requests are held pending.
3. If the I bit in CCR is set to 1, only NMI and address break interrupts are accepted by the
interrupt controller, and other interrupt requests are held pending. If the I bit is cleared to 0,
any interrupt request is accepted.
4. When the CPU accepts an interrupt request, it starts interrupt exception handling after
execution of the current instruction has been completed.
5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
6. Next, the I bit in CCR is set to 1. This masks all interrupts except for NMI and address break
interrupts.
Rev. 1.00, 05/04, page 81 of 544
7. The CPU generates a vector address for the accepted interrupt and starts execution of the
interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.
Program excution state
Interrupt generated?
NMI
An interrupt with interrupt
control level 1?
IRQ0
IRQ1
IBFI3
IRQ0
IRQ1
IBFI3
I = 0
Save PC and CCR
I 1
Read vector address
Branch to interrupt handling routine
Yes
No
Yes
Yes
Yes No
No
Yes
No
Yes No
Yes
Yes
No
No
Yes
Yes
No
Hold pending
Figure 5.4 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0
Rev. 1.00, 05/04, page 82 of 544
5.6.2 Interrupt Control Mode 1
In interrupt control mode 1, mask control is applied to three levels for IRQ and on-chip peripheral
module interrupt requests by comparing the I and UI bits in CCR in the CPU, and the ICR setting.
An interrupt request with interrupt control level 0 is accepted when the I bit in CCR is cleared
to 0. When the I bit is set to 1, the interrupt request is held pending
An interrupt request with interrupt control level 1 is accepted when the I bit or UI bit in CCR is
cleared to 0. When both I and UI bits are set to 1, the interrupt request is held pending.
For instance, the state transition when the interrupt enable bit corresponding to each interrupt is set
to 1, and ICRA to ICRC are set to H'20, H'00, and H'00, respectively (IRQ2 and IRQ3 interrupts
are set to control level 1, and other interrupts are set to control level 0) is shown below. Figure 5.5
shows a state transition diagram.
All interrupt requests are accepted when I = 0. (Priority order: NMI > IRQ2 > IRQ3 > address
break > IRQ0 > IRQ1 …)
Only NMI, IRQ2, IRQ3 and address break interrupt requests are accepted when I = 1 and UI =
0.
Only an NMI and address break interrupt request is accepted when I = 1 and UI = 1.
Only NMI and address break
interrupt requests are accepted
All interrupt requests
are accepted
Exception handling execution
or I 1, UI 1
I 0
I 1, UI 0
I 0UI 0
Exception handling
execution or UI 1
Only NMI, address break, IRQ2,
and IRQ3 interrupt requests
are accepted
Figure 5.5 State Transition in Interrupt Control Mode 1
Rev. 1.00, 05/04, page 83 of 544
Figure 5.6 shows a flowchart of the interrupt acceptance operation.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
2. According to the interrupt control level specified in ICR, the interrupt controller only accepts
an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt
request with interrupt control level 0 (no priority). If several interrupt requests are issued, an
interrupt request with the highest priority is accepted according to the priority order, an
interrupt handling is requested to the CPU, and other interrupt requests are held pending.
3. An interrupt request with interrupt control level 1 is accepted when the I bit is cleared to 0, or
when the I bit is set to 1 while the UI bit is cleared to 0.
An interrupt request with interrupt control level 0 is accepted when the I bit is cleared to 0.
When the I bit is set to 1, only an NMI or address break interrupt request is accepted, and other
interrupts are held pending.
When both the I and UI bits are set to 1, only an NMI or address break interrupt request is
accepted, and other interrupts are held pending.
When the I bit is cleared to 0, the UI bit is not affected.
4. When the CPU accepts an interrupt request, it starts interrupt exception handling after
execution of the current instruction has been completed.
5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
6. The I and UI bits in CCR are set to 1. This masks all interrupts except for an NMI or address
break interrupt.
7. The CPU generates a vector address for the accepted interrupt and starts execution of the
interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.
Rev. 1.00, 05/04, page 84 of 544
Program excution state
Interrupt generated?
NMI
An interrupt with interrupt
control level 1?
IRQ0
IRQ1
IFBFI3
IRQ0
IRQ1
IFBFI3
UI = 0
Save PC and CCR
I 1, UI 1
Read vector address
Branch to interrupt handling routine
Yes
No
Yes
Yes
Yes No
No
Yes
No
Yes No
Yes
Yes
No
No
Yes
Yes
No
Hold pending
I = 0 I = 0
Yes Yes
No
No
Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance
in Interrupt Control Mode 1
Rev. 1.00, 05/04, page 85 of 544
5.6.3 Interrupt Exception Handling Sequence
Figure 5.7 shows the interrupt exception handling sequence. The example shown is for the case
where interrupt control mode 0 is set in advanced mode, and the program area and stack area are
in on-chip memory.
(14)
(12)
(10)
(6)
(4)
(2)
(1) (5) (7) (9) (11) (13)
Prefetch of
instruction in
interrupt-handling
routine
Vector fetchStack access
Instruction
prefetch
Internal
processing
Internal
processing
Interrupt is
accepted
Interrupt level
decision and wait for
end of instruction
Interrupt
request signal
Internal
address bus
Internal read
signal
Internal write
signal
Internal
data bus
φ
(3)
(1)
(2) (4)
(3)
(5)
(7)
Instruction prefetch address (Instruction is not executed.
Address is saved as PC contents, becoming return address.)
Instruction code (not executed)
Instruction prefetch address (Instruction is not executed.)
SP – 2
SP – 4
Saved PC and CCR
Vector address
Starting address of interrupt-handling routine (contents of vector address)
Starting address of interrupt-handling routine ((13) = (10) (12))
First instruction in interrupt-handling routine
(6) (8)
(9) (11)
(10) (12)
(13)
(14)
(8)
Figure 5.7 Interrupt Exception Handling
Rev. 1.00, 05/04, page 86 of 544
5.6.4 Interrupt Response Times
Table 5.5 shows interrupt response times the intervals between generation of an interrupt request
and execution of the first instruction in the interrupt handling routine. The execution status
symbols used in table 5.5 are explained in table 5.6.
Table 5.5 Interrupt Response Times
No. Execution Status Normal Mode Advanced Mode
1 Interrupt priority determination*1 3
2 Number of wait states until executing
instruction ends*2
1 to (19 + 2·SI)
3 PC, CCR stack save 2·SK 2·SK
4 Vector fetch SI 2·SI
5 Instruction fetch*3 2·SI
6 Internal processing*4 2
Total (using on-chip memory) 11 to 31 12 to 32
Notes: 1. Two states in case of internal interrupt.
2. Refers to MULXS and DIVXS instructions.
3. Prefetch after interrupt acceptance and prefetch of interrupt handling routine.
4. Internal processing after interrupt acceptance and internal processing after vector fetch.
Table 5.6 Number of States in Interrupt Handling Routine Execution Status
Object of Access
Symbol Internal Memory
Instruction fetch SI
Branch address read SJ
Stack manipulation SK
1
Rev. 1.00, 05/04, page 87 of 544
5.7 Address Break
5.7.1 Features
This LSI can determine the specific address prefetch by the CPU to generate an address break
interrupt by setting ABRKCR and BAR. If an address break interrupt is generated, the address
break interrupt exception handling is performed.
With this function, the execution start point of a program containing a bug is detected and
execution is branched to the correcting program.
5.7.2 Block Diagram
Figure 5.8 shows a block diagram of the address break.
ABRKCRBAR
Control
logic
Comparator
Match
signal Address break
interrupt request
Internal address
Prefetch signal
(internal signal)
Figure 5.8 Address Break Block Diagram
Rev. 1.00, 05/04, page 88 of 544
5.7.3 Operation
If the CPU prefetches an address specified in BAR by setting ABRKCR and BAR, an address
break interrupt can be generated. This address break function generates an interrupt request to the
interrupt controller at prefetch, and determines the priority by the interrupt controller. When an
interrupt is accepted, an interrupt exception handling is activated after the current instruction has
been completed. Note that the interrupt mask control according to the I and UI bits in CCR of the
CPU is invalid to an address break interrupt.
To use the address break function, set each register as follows:
1. Set a break address in the A23 to A1 bits in BAR.
2. Set the BIE bit in ABRKCR to 1 to enable the address break.
When the BIE bit is cleared to 0, an address break is not requested.
When the setting conditions are satisfied, the CMF flag in ABRKCR is set to 1 to request an
interrupt. The interrupt source should be determined by the interrupt handling routine if necessary.
5.7.4 Usage Notes
1. In an address break, the break address should be an address where the first byte of the
instruction exists. Otherwise, a break condition will not be satisfied.
2. In normal mode, addresses A23 to A16 are not compared.
3. When the branch instructions (Bcc, BSR), jump instructions (JMP, JSR), RST instruction, and
RTE instruction are placed immediately prior to the address specified by BAR, a prefetch
signal to the address may be output to request an address break by executing these instruction.
It is necessary to take countermeasures: do not set a break address to an address immediately
after these instructions, or determine whether interrupt handling is performed by satisfaction of
a normal condition.
4. An address break interrupt is generated by combining the internal prefetch signal and an
address. Therefore, the timing to enter the interrupt exception handling differs according to the
instructions at the specified and at prior addresses and execution cycles.
Rev. 1.00, 05/04, page 89 of 544
Figure 5.9 shows an example of address timing.
Instruction
fetch
Address bus
Break request
signal
Break point NOP instruction is executed at break point address
H'0312 and following address H'0314.
Fetching is performed from address H'0316
after exception handling ends.
φ
Instruction
fetch
Instruction
fetch
Instruction
fetch
Instruction
fetch
Internal
operation
Internal
operation
Vector
fetch
Save
to stack
Instruction
fetch
H'0310
NOP
execution
H'0310 NOP
H'0312 NOP
H'0314 NOP
H'0316 NOP
NOP
execution
NOP
execution
Interrupt exception handling
H'0312 H'0314 H'0316 H'0318 H'0036SP-2 SP-4
(1) When a break address specified instruction is executed for one state in the program area and on-chip memory
Address bus
Break request
signal
Break point MOV instruction is executed at break point address
H'0312, and NOP instruction is not executed
at the following address H'0314.
Fetching is performed from address H'0316
after exception handling ends.
φ
Instruction
fetch
Instruction
fetch
Instruction
fetch
Internal
operation
Internal
operation
Vector
fetch
Save
to stack
Instruction
fetch
H'0310
NOP
execution
H'0310 NOP
H'0312 MOV.W #xx:16,Rd
H'0316 NOP
H'0318 NOP
MOV.W
execution Interrupt exception handling
H'0312 H'0314 H'0316 H'0318 H'0036SP-2 SP-4
(2) When a break address specified instruction is executed for two states in the program area and on-chip memory
Instruction
fetch
Instruction
fetch
Figure 5.9 Address Break Timing Example
Rev. 1.00, 05/04, page 90 of 544
5.8 Usage Notes
5.8.1 Conflict between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to disable interrupt requests, the disabling becomes
effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an
instruction such as BCLR or MOV, and if an interrupt is generated during execution of the
instruction, the interrupt concerned will still be enabled on completion of the instruction, so
interrupt exception handling for that interrupt will be executed on completion of the instruction.
However, if there is an interrupt request of higher priority than that interrupt, interrupt exception
handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be
ignored. The same rule is also applied when an interrupt source flag is cleared to 0. Figure 5.10
shows an example in which the CMIEA bit in the TMR's TCR register is cleared to 0.
The above conflict will not occur if an enable bit or interrupt source flag is cleared to 0 while the
interrupt is masked.
Internal
address bus
Internal
write signal
φ
CMIEA
CMFA
CMIA
interrupt signal
TCR write cycle
by CPU CMIA exception handling
TCR address
Figure 5.10 Conflict between Interrupt Generation and Disabling
Rev. 1.00, 05/04, page 91 of 544
5.8.2 Instructions that Disable Interrupts
The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these
instructions are executed, all interrupts including NMI are disabled and the next instruction is
always executed. When the I bit or UI bit is set by one of these instructions, the new value
becomes valid two states after execution of the instruction ends.
5.8.3 Interrupts during Execution of EEPMOV Instruction
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.
With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer
is not accepted until the move is completed.
With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt
exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this
case is the address of the next instruction. Therefore, if an interrupt is generated during execution
of an EEPMOV.W instruction, the following coding should be used.
L1: EEPMOV.W
MOV.W R4,R4
BNE L1
5.8.4 IRQ Status Register (ISR)
According to the pin status after a reset, IRQnF may be set to 1, so ISR should be read after a reset
to write 0. (n = 7 to 0)
Rev. 1.00, 05/04, page 92 of 544
Rev. 1.00, 05/04, page 93 of 544
Section 6 Bus Controller (BSC)
Since this LSI does not have an externally extended function, it does not have an on-chip bus
controller (BSC). Considering the software compatibility with similar products, you must be
careful to set appropriate values to the control registers for the bus controller.
6.1 Register Descriptions
The bus controller has the following registers.
Bus control register (BCR)
Wait state control register (WSCR)
6.1.1 Bus Control Register (BCR)
Bit Bit Name Initial
Value R/W Description
7 — 1 R/W Reserved
The initial value should not be changed.
6 ICIS0 1 R/W Idle Cycle Insertion
The initial value should not be changed.
5 BRSTRM 0 R/W Burst ROM Enable
The initial value should not be changed.
4 BRSTS1 1 R/W Burst Cycle Select 1
The initial value should not be changed.
3 BRSTS0 0 R/W Burst Cycle Select 0
The initial value should not be changed.
2 0 R/W Reserved
The initial value should not be changed.
1
0
IOS1
IOS0
1
1
R/W
R/W
IOS Select 1, 0
The initial value should not be changed.
Rev. 1.00, 05/04, page 94 of 544
6.1.2 Wait State Control Register (WSCR)
Bit Bit Name
Initial
Value R/W Description
7
6
0
0
R/W
R/W
Reserved
The initial value should not be changed.
5 ABW 1 R/W Bus Width Control
The initial value should not be changed.
4 AST 1 R/W Access State Control
The initial value should not be changed.
3
2
WMS1
WMS0
0
0
R/W
R/W
Wait Mode Select 1, 0
The initial value should not be changed.
1
0
WC1
WC0
1
1
R/W
R/W
Wait Count 1, 0
The initial value should not be changed.
Rev. 1.00, 05/04, page 95 of 544
Section 7 I/O Ports
This LSI has fifteen I/O ports (ports 1 to 6, 8, 9, and A to G), and one input-only port (port 7).
Table 7.1 is a summary of the port functions. The pins of each port also have other functions.
Each port includes a data direction register (DDR) that controls input/output (not provided for the
input-only port) and data registers (DR, ODR) that store output data.
Ports 1 to 3, 6, and A to F have on-chip input pull-up MOSs. For ports A to F, the on/off state of
the input pull-up MOS is controlled by DDR and ODR. Ports 1 to 3 and 6 have DDR and an input
pull-up MOS control register (PCR) to control the on/off state of the input pull-up MOS.
Ports 1 to 6, 8, 9, and A to F can drive a single TTL load and 30-pF capacitive load. All the I/O
ports can drive a Darlington transistor when in output mode. Ports 1, 2, and 3 can drive an LED
(10 mA sink current).
VccB, which is independent of the VCC power supply, is supplied to Port A input/output. When the
VccB voltage is 5 V, the pins on port A will be 5-V tolerant.
PA4 to PA7 of port A have bus-buffer drive capability.
P52 in port 5, P97 in port 9, P86 in port 8, P42 in port 4, and PG0 to PG 7 in port G are NMOS
push-pull outputs. P52, P97, P86, P42, and PG0 to PG 7 are thus 5-V tolerant with DC
characteristics dependent on the VCC voltage.
For the P42, P52/ExSCK1, P86/SCK1, P97 outputs, and PG0 to PG7, connect pull-up resistors to
pins to raise output-high-level voltage.
Rev. 1.00, 05/04, page 96 of 544
Table 7.1 Port Functions
Port Description Mode 2and Mode 3 I/O Status
Port 1 General I/O port also
functioning as PWM
output pins
P17/PW7
P16/PW6
P15/PW5
P14/PW4
P13/PW3
P12/PW2
P11/PW1
P10/PW0
On-chip input pull-
up MOSs
Port 2 General I/O port P27
P26
P25
P24
P23
P22
P21
P20
On-chip input pull-
up MOSs
Port 3 General I/O port also
functioning as LPC
input/output pins
P37/SERIRQ
P36/LCLK
P35/LRESET
P34/LFRAME
P33/LAD3
P32/LAD2
P31/LAD1
P30/LAD0
On-chip input pull-
up MOSs
Port 4 General I/O port also
functioning as TMR_0 and
TMR_1 input/output, and
IIC_1 input/output pins
P47
P46
P45/TMRI1
P44/TMO1
P43/TMCI1
P42/TMRI0/SDA1
P41/TMO0
P40/TMCI0
Port 5 General I/O port also
functioning as SCI_1
input/output and IIC_0
input/output pins
P52/ExSCK1*/SCL0
P51/ExRxD1*
P50/ExTxD1*
Rev. 1.00, 05/04, page 97 of 544
Port Description Mode 2and Mode 3 I/O Status
Port 6 General I/O port also
functioning as interrupt
input, FRT input/output,
TMR_X and TMR_Y
input/output, and key-
sense interrupt input
P67/TMOX/KIN7/IRQ7
P66/FTOB/KIN6/IRQ6
P65/FTID/KIN5
P64/FTIC/KIN4
P63/FTIB/KIN3
P62/FTIA/KIN2/TMIY
P61/FTOA/KIN1
P60/FTCI/KIN0/TMIX
On-chip input pull-
up MOSs
Port 7 General input port also
functioning as A/D
converter analog input
P77
P76
P75/AN5
P74/AN4
P73/AN3
P72/AN2
P71/AN1
P70/AN0
Port 8 General I/O port also
functioning as interrupt
input, SCI_1 input/output,
LPC input/output, and
IIC_1 input/output pins
P86/IRQ5/SCK1/SCL1
P85/IRQ4/RxD1
P84/IRQ3/TxD1
P83/LPCPD
P82/CLKRUN
P81/GA20
P80/PME
Port 9 General I/O port also
functioning as IIC_0
input/output, subclock
input, φ output, interrupt
input, and A/D converter
external trigger input pins
P97/SDA0
P96/φ/EXCL
P95
P94
P93
P92/IRQ0
P91/IRQ1
P90/IRQ2/ADTRG
Rev. 1.00, 05/04, page 98 of 544
Port Description Mode 2and Mode 3 I/O Status
Port A General I/O port also
functioning as key-sense
interrupt input and
keyboard buffer controller
input/output pins
PA7/KIN15/PS2CD
PA6/KIN14/PS2CC
PA5/KIN13/PS2BD
PA4/KIN12/PS2BC
PA3/KIN11/PS2AD
PA2/KIN10/PS2AC
PA1/KIN9
PA0/KIN8
On-chip input pull-
up MOSs
Port B General I/O port also
functioning as wakeup
event interrupt input and
LPC input/output pins
PB7/WUE7
PB6/WUE6
PB5/WUE5
PB4/WUE4
PB3/WUE3
PB2/WUE2
PB1/WUE1/LSCI
PB0/WUE0/LSMI
On-chip input pull-
up MOSs
Port C General I/O port PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
On-chip input pull-
up MOSs
Port D General I/O port PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
On-chip input pull-
up MOSs
Rev. 1.00, 05/04, page 99 of 544
Port Description Mode 2and Mode 3 I/O Status
Port E General I/O port PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
On-chip input pull-
up MOSs
Port F General I/O port also
functioning as TMR_X,
TMR_Y, TMR_A, and
TMR_B input/output pins
PF7/TMOY*
PF6/ExTMOX*
PF5/ExTMIY*
PF4/ExTMIX*
PF3/TMOB
PF2/TMOA
PF1/TMIB
PF0/TMIA
On-chip input pull-
up MOSs
Port G General I/O port also
functioning as IIC_1 and
IIC_0 input/output pins
PG7/ExSCLB*
PG6/ExSDAB*
PG5/ExSCLA*
PG4/ExSDAA*
PG3
PG2
PG1
PG0
Note: * The program development tool (emulator) does not support this function.
Rev. 1.00, 05/04, page 100 of 544
7.1 Port 1
Port 1 is an 8-bit I/O port. Port 1 pins also function as PWM output pins. Port 1 has the following
registers.
Port 1 data direction register (P1DDR)
Port 1 data register (P1DR)
Port 1 pull-up MOS control register (P1PCR)
7.1.1 Port 1 Data Direction Register (P1DDR)
P1DDR specifies input or output for the pins of port 1 on a bit-by-bit basis.
Bit Bit Name
Initial
Value R/W Description
7 P17DDR 0 W
6 P16DDR 0 W
5 P15DDR 0 W
4 P14DDR 0 W
3 P13DDR 0 W
2 P12DDR 0 W
1 P11DDR 0 W
0 P10DDR 0 W
The corresponding port 1 pins are output ports when
the P1DDR bits are set to 1, and input ports when the
P1DDR bits are cleared to 0.
7.1.2 Port 1 Data Register (P1DR)
P1DR stores output data for the port 1 pins.
Bit Bit Name
Initial
Value R/W Description
7 P17DR 0 R/W
6 P16DR 0 R/W
5 P15DR 0 R/W
4 P14DR 0 R/W
3 P13DR 0 R/W
2 P12DR 0 R/W
1 P11DR 0 R/W
0 P10DR 0 R/W
If a port 1 read is performed while the P1DDR bits are
set to 1, the P1DR values are read. If a port 1 read is
performed while the P1DDR bits are cleared to 0, the
pin states are read.
Rev. 1.00, 05/04, page 101 of 544
7.1.3 Port 1 Pull-Up MOS Control Register (P1PCR)
P1PCR controls the on/off state of the port 1 on-chip input pull-up MOSs.
Bit Bit Name
Initial
Value R/W Description
7 P17PCR 0 R/W
6 P16PCR 0 R/W
5 P15PCR 0 R/W
4 P14PCR 0 R/W
3 P13PCR 0 R/W
2 P12PCR 0 R/W
1 P11PCR 0 R/W
0 P10PCR 0 R/W
When a P1PCR bit is set to 1 with the input port
setting, the input pull-up MOS is turned on.
7.1.4 Pin Functions
P17/PW7 to P10/PW0
The pin function is switched as shown below according to the combination of the OEn bit in
PWOERA of PWM and the P1nDDR bit.
P1nDDR 0 1
OEn 0 1
Pin Function P17 to P10 input pins P17 to P10
output pins
PW7 to PW0
output pins
[Legend]
n = 7 to 0
Rev. 1.00, 05/04, page 102 of 544
7.1.5 Port 1 Input Pull-Up MOS
Port 1 has an on-chip input pull-up MOS function that can be controlled by software. This input
pull-up MOS function can be specified as on or off on a bit-by-bit basis.
Table 7.2 summarizes the input pull-up MOS states.
Table 7.2 Input Pull-Up MOS States (Port 1)
Reset Hardware Standby Mode Software Standby ModeIn Other Operations
Off Off On/Off On/Off
[Legend]
Off: Input pull-up MOS is always off.
On/Off: On when the pin is in the input state, P1DDR = 0, and P1PCR = 1: otherwise off.
7.2 Port 2
Port 2 is an 8-bit I/O port. Port 2 has an on-chip input pull-up MOS function that can be controlled
by software. Port 2 has the following registers.
Port 2 data direction register (P2DDR)
Port 2 data register (P2DR)
Port 2 pull-up MOS control register (P2PCR)
7.2.1 Port 2 Data Direction Register (P2DDR)
P2DDR specifies input or output for the pins of port 2 on a bit-by-bit basis.
Bit Bit Name
Initial
Value R/W Description
7 P27DDR 0 W
6 P26DDR 0 W
5 P25DDR 0 W
4 P24DDR 0 W
3 P23DDR 0 W
2 P22DDR 0 W
1 P21DDR 0 W
0 P20DDR 0 W
The corresponding port 2 pins are output ports when
P2DDR bits are set to 1, and input ports when P2DDR
bits are cleared to 0.
Rev. 1.00, 05/04, page 103 of 544
7.2.2 Port 2 Data Register (P2DR))
P2DR stores output data for port 2.
Bit Bit Name
Initial
Value R/W Description
7 P27DR 0 R/W
6 P26DR 0 R/W
5 P25DR 0 R/W
4 P24DR 0 R/W
3 P23DR 0 R/W
2 P22DR 0 R/W
1 P21DR 0 R/W
0 P20DR 0 R/W
If a port 2 read is performed while P2DDR bits are set
to 1, the P2DR values are read directly, regardless of
the actual pin states. If a port 2 read is performed while
P2DDR bits are cleared to 0, the pin states are read.
7.2.3 Port 2 Pull-Up MOS Control Register (P2PCR)
P2PCR controls the port 2 on-chip input pull-up MOSs.
Bit Bit Name
Initial
Value R/W Description
7 P27PCR 0 R/W
6 P26PCR 0 R/W
5 P25PCR 0 R/W
4 P24PCR 0 R/W
3 P23PCR 0 R/W
2 P22PCR 0 R/W
1 P21PCR 0 R/W
0 P20PCR 0 R/W
The input pull-up MOS is turned on when a P2PCR bit
is set to 1 in the input port state.
7.2.4 Pin Functions
P27, P26, P25, P24, P23, P22, P21, P20
The pin function is switched as shown below according to the state of the P2nDDR bit.
P2nDDR 0 1
Pin Function P27 to P20 input pins P27 to P20 output pins
[Legend]
n = 7 to 0
Rev. 1.00, 05/04, page 104 of 544
7.2.5 Port 2 Input Pull-Up MOS
Port 2 has an on-chip input pull-up MOS function that can be controlled by software. This input
pull-up MOS function can be specified as on or off on a bit-by-bit basis.
Table 7.3 summarizes the input pull-up MOS states.
Table 7.3 Input Pull-Up MOS States (Port 2)
Reset Hardware
Standby Mode Software
Standby Mode In Other
Operations
Off Off On/Off On/Off
[Legend]
Off: Input pull-up MOS is always off.
On/Off: On when the pin is in the input state, P2DDR = 0, and P2PCR = 1; otherwise off.
7.3 Port 3
Port 3 is an 8-bit I/O port. Port 3 pins also function as LPC input/output pins. Port 3 has the
following registers.
Port 3 data direction register (P3DDR)
Port 3 data register (P3DR)
Port 3 pull-up MOS control register (P3PCR)
7.3.1 Port 3 Data Direction Register (P3DDR)
P3DDR specifies input or output for the pins of port 3 on a bit-by-bit basis.
Bit Bit Name
Initial
Value R/W Description
7 P37DDR 0 W
6 P36DDR 0 W
5 P35DDR 0 W
4 P34DDR 0 W
3 P33DDR 0 W
2 P32DDR 0 W
1 P31DDR 0 W
0 P30DDR 0 W
The corresponding port 3 pins are output ports when
P3DDR bits are set to 1, and input ports when P3DDR
bits are cleared to 0.
Rev. 1.00, 05/04, page 105 of 544
7.3.2 Port 3 Data Register (P3DR)
P3DR stores output data of port 3.
Bit Bit Name
Initial
Value R/W Description
7 P37DR 0 R/W
6 P36DR 0 R/W
5 P35DR 0 R/W
4 P34DR 0 R/W
3 P33DR 0 R/W
2 P32DR 0 R/W
1 P31DR 0 R/W
0 P30DR 0 R/W
If a port 3 read is performed while P3DDR bits are set
to 1, the P3DR values are read directly, regardless of
the actual pin states. If a port 3 read is performed while
P3DDR bits are cleared to 0, the pin states are read.
7.3.3 Port 3 Pull-Up MOS Control Register (P3PCR)
P3PCR controls the port 3 on-chip input pull-up MOSs on a bit-by-bit basis.
Bit Bit Name
Initial
Value R/W Description
7 P37PCR 0 R/W
6 P36PCR 0 R/W
5 P35PCR 0 R/W
4 P34PCR 0 R/W
3 P33PCR 0 R/W
2 P32PCR 0 R/W
1 P31PCR 0 R/W
0 P30PCR 0 R/W
The input pull-up MOS is turned on when a P3PCR bit
is set to 1 in the input port state.
The input pull-up MOS function cannot be used when
the host interface is enabled.
Rev. 1.00, 05/04, page 106 of 544
7.3.4 Pin Functions
P37/SERIRQ, P36/LCLK, P35/LRESET, P34/LFRAME, P33/LAD3, P32/LAD2, P31/LAD1,
P30/LAD0
The pin function is switched as shown below according to the combination of the LPC3E to
LPC1E bits in HICR0 of the host interface (LPC) and the P3nDDR bit.
LPCmE All 0 Not all 0
P3nDDR 0 1 0
Pin Function P37 to P30 input pins P37 to P30 output pins LPC input/output pins
Note: The combination of bits not described in the above table must not be used.
m = 3 to 1: LPC input/output pins (SERIRQ, LCLK, LRESET, LFRAME, LAD3 to LAD0)
when at least one of LPC3E to LPC1E is set to 1.
n = 7 to 0
7.3.5 Port 3 Input Pull-Up MOS
Port 3 has an on-chip input pull-up MOS function that can be controlled by software. This input
pull-up MOS function can be specified as on or off on a bit-by-bit basis.
Table 7.4 summarizes the input pull-up MOS states.
Table 7.4 Input Pull-Up MOS States (Port 3)
Reset Hardware Standby Mode Software Standby Mode In Other Operations
Off Off On/Off On/Off
[Legend]
Off: Input pull-up MOS is always off.
On/Off: On when the pin is in the input state, P3DDR = 0, and P3PCR = 1; otherwise off.
Rev. 1.00, 05/04, page 107 of 544
7.4 Port 4
Port 4 is an 8-bit I/O port. Port 4 pins also function as TMR_0 and TMR_1 I/O pins, and the IIC_1
I/O pin. The output type of P42 is NMOS push-pull output. The output type of SDA1 is NMOS
open-drain output. Port 4 has the following registers.
Port 4 data direction register (P4DDR)
Port 4 data register (P4DR)
7.4.1 Port 4 Data Direction Register (P4DDR)
P4DDR specifies input or output for the pins of port 4 on a bit-by-bit basis.
Bit Bit Name
Initial
Value R/W Description
7 P47DDR 0 W
6 P46DDR 0 W
5 P45DDR 0 W
4 P44DDR 0 W
3 P43DDR 0 W
2 P42DDR 0 W
1 P41DDR 0 W
0 P40DDR 0 W
When a bit in P4DDR is set to 1, the corresponding pin
functions as an output port, and when cleared to 0, as
an input port.
7.4.2 Port 4 Data Register (P4DR)
P4DR stores output data for port 4.
Bit Bit Name
Initial
Value R/W Description
7 P47DR 0 R/W
6 P46DR 0 R/W
5 P45DR 0 R/W
4 P44DR 0 R/W
3 P43DR 0 R/W
2 P42DR 0 R/W
1 P41DR 0 R/W
0 P40DR 0 R/W
If a port 4 read is performed while P4DDR bits are set
to 1, the P4DR values are read directly, regardless of
the actual pin states. If a port 4 read is performed while
P4DDR bits are cleared to 0, the pin states are read.
Rev. 1.00, 05/04, page 108 of 544
7.4.3 Pin Functions
P47
The pin function is switched as shown below according to the combination of the P47DDR bit.
P47DDR 0 1
Pin Function P47 input pin P47 output pin
P46
The pin function is switched as shown below according to the combination of the P46DDR bit.
P46DDR 0 1
Pin Function P46 input pin P46 output pin
P45/TMRI1
The pin function is switched as shown below according to the combination of the P45DDR bit.
P45DDR 0 1
P45 input pin P45 output pin Pin Function
TMRI1 input pin
Note: * When bits CCLR1 and CCLR0 in TCR1 of TMR_1 are set to 1, this pin is used as the
TMRI1 input pin.
P44/TMO1
The pin function is switched as shown below according to the combination of the OS3 to OS0
bits in TCSR of TMR_1 and the P44DDR bit.
OS3 to OS0 All 0 Not all 0
P44DDR 0 1
Pin Function P44 input pin P44 output pin TMO1 output pin
Rev. 1.00, 05/04, page 109 of 544
P43/TMCI1
The pin function is switched as shown below according to the state of the P43DDR bit.
P43DDR 0 1
P43 input pin P43 output pin Pin Function
TMCI1 input pin*
Note: * When the external clock is selected by the bits CKS2 to CKS0 in TCR1 of TMR_1, this
pin is used as the TMCI1 input pin.
P42/TMRI0/SDA1
The pin function is switched as shown below according to the combination of the ICE bit in
ICCR of IIC_1, the IIC1AS and the IIC1BS bits in PGCTL*2, and the P42DDR bit.
P42ICE = ICE (IIC1AS+IIC1BS)*2
P42ICE*2 0 1
P42DDR 0 1
P42 input pin P42 output pin SDA1 I/O pin Pin Function
TMRI0 input pin*1
Note: 1. SDA1 is an NMOS-only output, and has direct bus drive capability.
When bits CCLR1 and CCLR0 in TCR0 of TMR_0 are set to 1, this pin is used as the
TMRI0 input pin. When the P42 output pin is set, the output type is NMOS push-pull
output.
2. The program development tool (emulator) does not support the function of PGCTL.
Thus P42ICE is treated as ICE.
P41/TMO0
The pin function is switched as shown below according to the combination of the OS3 to OS0
bits in TCSR of TMR_0 and the P41DDR bit.
OS3 to OS0 All 0 Not all 0
P41DDR 0 1
Pin Function P41 input pin P41 output pin TMO0 output pin
P40/TMCI0
The pin function is switched as shown below according to the state of the P40DDR bit.
P40DDR 0 1
P40 input pin P40 output pin Pin Function
TMCI0 input pin*
Note: * When an external clock is selected with bits CKS2 to CKS0 in TCR0 of TMR_0, this pin
is used as the TMCI0 input pin.
Rev. 1.00, 05/04, page 110 of 544
7.5 Port 5
Port 5 is a 3-bit I/O port. Port 5 pins also function as SCI_1 extended I/O pins, and the IIC_0 I/O
pin. P52 and ExSCK1 are NMOS push-pull outputs, and SCL0 is an NMOS open-drain output.
Port 5 has the following registers.
Port 5 data direction register (P5DDR)
Port 5 data register (P5DR)
7.5.1 Port 5 Data Direction Register (P5DDR)
P5DDR specifies input or output for the pins of port 5 on a bit-by-bit basis.
Bit Bit Name
Initial
Value R/W Description
7 to 3 All 1 Reserved
The initial value should not be changed.
2 P52DDR 0 W
1 P51DDR 0 W
0 P50DDR 0 W
The corresponding port 5 pins are output ports when
P5DDR bits are set to 1, and input ports when cleared
to 0. As SCI_1 is initialized in software standby mode,
the pin states are determined by the specifications of
ICCR, PGCTL, P5DDR, and P5DR in IIC_0.
7.5.2 Port 5 Data Register (P5DR)
P5DR stores output data for port 5 pins.
Bit Bit Name
Initial
Value R/W Description
7 to 3 All 1 Reserved
The initial value should not be changed.
2 P52DR 0 R/W
1 P51DR 0 R/W
0 P50DR 0 R/W
If a port 5 read is performed while P5DDR bits are set
to 1, the P5DR values are read directly, regardless of
the actual pin states. If a port 5 read is performed while
P5DDR bits are cleared to 0, the pin states are read.
Rev. 1.00, 05/04, page 111 of 544
7.5.3 Pin Functions
P52/ExSCK1*/SCL0
The pin function is switched as shown below according to the combination of the C/A bit in
SMR of SCI_1, the CKE0 and CKE1 bits in SCR, the SPS1 bit*1 in SPSR, the ICE bit in ICCR
of IIC_0, the IIC0AS and the IIC0BS bits in PGCTL*2, and the P52DDR bit.
P52ICE = ICE (IIC0AS+IIC0BS)*2
SPS1*1 0 1
P52ICE*2 0 1 0 1
CKE1 — 0 1 0
C/A — — 0 1 — 0
CKE0 — — 0 1 — 0
P52DDR 0 1 0 1 — —
Pin Function P52
input pin
P52
output pin
SCL0
I/O pin
P52
input pin
P52
output pin
ExSCK1*1
output pin
ExSCK1*1
output pin
ExSCK1*1
input pin
SCL0
I/O pin
Note: 1. When this pin is used as the SCL0 I/O pin by setting 1 to the SPS1 bit of SPSR, the bits
CKE1 and CKE0 in SCR of SCI_1 and the C/A bit in SMR must all be cleared to 0.
SCL0 is an NMOS open-drain output. When set as the P52 output pin or ExSCK1
output pin, this pin is an NMOS push-pull output.
2. The program development tool (emulator) does not support the function of PGCTL.
Thus P52ICE is treated as ICE.
P51/ExRxD1
The pin function is switched as shown below according to the combination of the RE bit in
SCR of SCI_1, the SPS1 bit* in SPSR, and the P51DDR bit.
SPS1* 0 1
RE — 0 1
P51DDR 0 1 0 1
Pin Function P51 input pin P51 output pin P51 input
pin
P51 output
pin
ExRxD1
input pin*
Note: * The program development tool (emulator) does not support this function.
Rev. 1.00, 05/04, page 112 of 544
P50/ExTxD1
The pin function is switched as shown below according to the combination of the TE bit in
SCR of SCI_1, the SPS1 bit* in SPSR, and the P50DDR bit.
SPS1* 0 1
TE — 0 1
P50DDR 0 1 0 1
Pin Function P50 input pin P50 output pin P50 input
pin
P50 output
pin
ExTxD1
output pin*
Note: * The program development tool (emulator) does not support this function.
7.6 Port 6
Port 6 is an 8-bit I/O port. Port 6 pins also function as the FRT I/O pins, TMR_X I/O pins,
TMR_Y input pin, key-sense interrupt input pins, and interrupt input pins. Port 6 has the following
registers.
Port 6 data direction register (P6DDR)
Port 6 data register (P6DR)
Port 6 pull-up MOS control register (KMPCR)
System control register 2 (SYSCR2)
7.6.1 Port 6 Data Direction Register (P6DDR)
P6DDR specifies input or output for the pins of port 6 on a bit-by-bit basis.
Bit Bit Name
Initial
Value R/W Description
7 P67DDR 0 W
6 P66DDR 0 W
5 P65DDR 0 W
4 P64DDR 0 W
3 P63DDR 0 W
2 P62DDR 0 W
1 P61DDR 0 W
0 P60DDR 0 W
The corresponding port 6 pins are output ports when
P6DDR bits are set to 1, and input ports when cleared
to 0.
Rev. 1.00, 05/04, page 113 of 544
7.6.2 Port 6 Data Register (P6DR)
P6DR stores output data for port 6.
Bit Bit Name
Initial
Value R/W Description
7 P67DR 0 R/W
6 P66DR 0 R/W
5 P65DR 0 R/W
4 P64DR 0 R/W
3 P63DR 0 R/W
2 P62DR 0 R/W
1 P61DR 0 R/W
0 P60DR 0 R/W
If a port 6 read is performed while P6DDR bits are set
to 1, the P6DR values are read directly, regardless of
the actual pin states. If a port 6 read is performed while
P6DDR bits are cleared to 0, the pin states are read.
7.6.3 Port 6 Pull-Up MOS Control Register (KMPCR)
KMPCR controls the port 6 on-chip input pull-up MOSs on a bit-by-bit basis.
Bit Bit Name
Initial
Value R/W Description
7 KM7PCR 0 R/W
6 KM6PCR 0 R/W
5 KM5PCR 0 R/W
4 KM4PCR 0 R/W
3 KM3PCR 0 R/W
2 KM2PCR 0 R/W
1 KM1PCR 0 R/W
0 KM0PCR 0 R/W
The input pull-up MOS is turned on when a KMPCR bit
is set to 1 with the input port setting.
Rev. 1.00, 05/04, page 114 of 544
7.6.4 System Control Register 2 (SYSCR2)
SYSCR2 is not available in this LSI although originally designed to control the port 6 operations.
Bit Bit Name
Initial
Value R/W Description
7 to 0 All 0 R/W Reserved
The initial value should not be changed.
7.6.5 Pin Functions
P67/TMOX/KIN7/IRQ7
The pin function is switched as shown below according to the combination of the OS3 to OS0
bits in TCSR of TMR_X, the IOSX bit*2 in TCRXY, and the P67DDR bit.
IOSX*2 0 1
OS3 to OS0 All 0 Not all 0
P67DDR 0 1 0 1
P67 input
pin
P67 output
pin
TMOX output
pin
P67 input pin P67 output pin Pin Function
IRQ7 input pin, KIN7 input pin*1
Notes: 1. This pin is used as the IRQ7 input pin when bit IRQ7E is set to 1 in IER. It can always
be used as the KIN7 input pin.
2. The program development tool (emulator) does not support this function.
Rev. 1.00, 05/04, page 115 of 544
P66/FTOB/KIN6/IRQ6
The pin function is switched as shown below according to the combination of the OEB bit in
TOCR of the FRT and the P66DDR bit.
OEB 0 1
P66DDR 0 1
P66 input pin P66 output pin FTOB output pin Pin Function
IRQ6 input pin, KIN6 input pin*
Note: * This pin is used as the IRQ6 input pin when bit IRQ6E is set to 1 in IER while the
KMIMR6 bit in KMIMR is 0. It can always be used as the KIN6 input pin.
P65/FTID/KIN5
P65DDR 0 1
P65 input pin P65 output pin Pin Function
FTID input pin, KIN5 input pin*
Note: * This pin can always be used as the FTID or KIN5 input pin.
P64/FTIC/KIN4
The pin function is switched as shown below according to the state of the P64DDR bit.
P64DDR 0 1
P64 input pin P64 output pin Pin Function
FTIC input pin, KIN4 input pin*
Note: * This pin can always be used as the FTIC or KIN4 input pin.
P63/FTIB/KIN3
P63DDR 0 1
P63 input pin P63 output pin Pin Function
FTIB input pin, KIN3 input pin*
Note: * This pin can always be used as the FTIB or KIN3 input pin.
P62/FTIA/KIN2/TMIY
P62DDR 0 1
P62 input pin P62 output pin Pin Function
FTIA input pin, TMIY input pin, KIN2 input pin*
Note: * This pin can always be used as the FTIA or KIN2 input pin. When the IOSY bit in
TCRXY of TMR_Y is set to 0, this pin can be used as the TMIY input pin.
Rev. 1.00, 05/04, page 116 of 544
P61/FTOA/KIN1
The pin function is switched as shown below according to the combination of the OEA bit in
TOCR of the FRT, and the P61DDR bit.
OEA 0 1
P61DDR 0 1
P61 input pin P61 output pin FTOA input pin Pin Function
KIN1 input pin*
Note: * This pin can always be used as the KIN1 input pin.
P60/FTCI/KIN0/TMIX
P60DDR 0 1
P60 input pin P60 output pin Pin Function
FTCI input pin, TMIX input pin, KIN0 input pin*
Note: * This pin is used as the FTCI input pin when an external clock is selected with bits CKS1
and CKS0 in TCR of the FRT. It can always be used as the KIN0 input pin. When the
IOSX bit in TCRXY of TMR_X is set to 0, this pin can be used as the TMIX input pin.
7.6.6 Port 6 Input Pull-Up MOS
Port 6 has an on-chip input pull-up MOS function that can be controlled by software. This input
pull-up MOS function can be specified as on or off on a bit-by-bit basis.
When a pin is designated as an on-chip peripheral module output pin, the input pull-up MOS is
always off.
Table 7.5 summarizes the input pull-up MOS states.
Table 7.5 Input Pull-Up MOS States (Port 6)
Reset Hardware Standby Mode Software Standby Mode In Other Operations
Off Off On/Off On/Off
[Legend]
Off: Input pull-up MOS is always off.
On/Off: On when the pin is in the input state, P6DDR = 0, and KMPCR = 1; otherwise off.
Rev. 1.00, 05/04, page 117 of 544
7.7 Port 7
Port 7 is an 8-bit input only port. Port 7 pins also function as the A/D converter analog input pins.
Port 7 has the following register.
Port 7 input data register (P7PIN)
7.7.1 Port 7 Input Data Register (P7PIN)
P7PIN reflects the pin states of port 7.
Bit Bit Name
Initial
Value R/W Description
7 P77PIN Undefined* R
6 P76PIN Undefined* R
5 P75PIN Undefined* R
4 P74PIN Undefined* R
3 P73PIN Undefined* R
2 P72PIN Undefined* R
1 P71PIN Undefined* R
0 P70PIN Undefined* R
When a P7PIN read is performed, the pin states are
always read. P7PIN has the same address as PBDDR;
if a write is performed, data will be written into PBDDR
and the port B setting will be changed.
Note: * Determined by the pin states of P77 to P70.
7.7.2 Pin Functions
P77, P76
Pin Function P77, P76 input pins
P75/AN5, P74/AN4, P73/AN3, P72/AN2, P71/AN1, P70/AN0
P75 to P70 input pins
Pin Function
AN5 to AN0 input pins*
Note: * These pins can always be used as the AN5 to AN0 input pins respectively.
Rev. 1.00, 05/04, page 118 of 544
7.8 Port 8
Port 8 is an 8-bit I/O port. Port 8 pins also function as SCI_1 I/O pins, the IIC_1 I/O pins, LPC I/O
pins, and interrupt input pins. The output type of P86 and SCK1 is NMOS push-pull output. The
output type of SCL1 is NMOS open-drain output and direct bus driving is enabled. Port 8 has the
following registers.
Port 8 data direction register (P8DDR)
Port 8 data register (P8DR)
7.8.1 Port 8 Data Direction Register (P8DDR)
P8DDR specifies input or output for the pins of port 8 on a bit-by-bit basis.
Bit Bit Name
Initial
Value R/W Description
7 — 1 Reserved
The initial value should not be changed.
6 P86DDR 0 W
5 P85DDR 0 W
4 P84DDR 0 W
3 P83DDR 0 W
2 P82DDR 0 W
1 P81DDR 0 W
0 P80DDR 0 W
P8DDR has the same address as PBPIN, and if read,
the port B state will be returned.
The corresponding port 8 pins are output ports when
P8DDR bits are set to 1, and input ports when cleared
to 0.
7.8.2 Port 8 Data Register (P8DR)
P8DR stores output data for the port 8 pins (P86 to P80).
Bit Bit Name
Initial
Value R/W Description
7 — 1 Reserved
The initial value should not be changed.
6 P86DR 0 R/W
5 P85DR 0 R/W
4 P84DR 0 R/W
3 P83DR 0 R/W
2 P82DR 0 R/W
1 P81DR 0 R/W
0 P80DR 0 R/W
If a port 8 read is performed while P8DDR bits are set
to 1, the P8DR values are read directly, regardless of
the actual pin states. If a port 8 read is performed while
P8DDR bits are cleared to 0, the pin states are read.
Rev. 1.00, 05/04, page 119 of 544
7.8.3 Pin Functions
P86/IRQ5/SCK1/SCL1
The pin function is switched as shown below according to the combination of the C/A bit in
SMR of SCI_1, the CKE0 and CKE1 bits in SCR, the SPS1 bit*2 in SPSR, the ICE bit in ICCR
of IIC_1, the IIC1AS and the IIC1BS bits in PGCTL*3, and the 86DDR bit.
P86ICE = ICE (IIC1AS+IIC1BS)*3
SPS1*2 0 1
P86ICE*3 0 1 0 1
CKE1 0 1 0
C/A 0 1 0
CKE0 0 1 0
P86DDR 0 1 — — — 0 1
P86
input
pin
P86
output
pin
SCK1
output
pin
SCK1
output
pin
SCK1
input
pin
SCL1
I/O pin
P86
input pin
P86
output
pin
SCL1
I/O pin
Pin Function
IRQ5 input pin*1
Notes: 1. When the IRQ5E bit in IER is set to 1, this pin is used as the IRQ5 input pin. When this
pin is used as the SCL1 I/O pin, bits CKE1 and CKE0 in SCR of SCI_1 and bit C/A in
SMR of SCI_1 must all be cleared to 0. When the P86 output pin and SCK1 output pin
are set, the output type is NMOS push-pull output. SCL1 is an NMOS-only output, and
has direct bus drive capability.
2. The program development tool (emulator) does not support this function.
3. The program development tool (emulator) does not support the function of PGCTL.
Thus P86ICE is treated as ICE.
P85/IRQ4/RxD1
The pin function is switched as shown below according to the combination of the RE bit in
SCR of SCI_1, the SPS1 bit*2 in SPSR, and the P85DDR bit.
SPS1*2 0 1
RE 0 1
P85DDR 0 1 0 1
P85 input
pin
P85 output
pin
RxD1 input
pin
P85 input pin P85 output pin Pin Function
IRQ4 input pin*1
Notes: 1. When the IRQ4E bit in IER is set to 1, this pin is used as the IRQ4 input pin.
2. The program development tool (emulator) does not support this function.
Rev. 1.00, 05/04, page 120 of 544
P84/IRQ3/TxD1
The pin function is switched as shown below according to the combination of the TE bit in
SCR of SCI_1, the SPS1 bit*2 in SPSR, and the P84DDR bit.
SPS1*2 0 1
TE 0 1
P84DDR 0 1 0 1
P84 input
pin
P84 output
pin
TxD1
output pin
P84 input pin P84 output pin Pin Function
IRQ3 input pin*1
Notes: 1. When the IRQ3E bit in IER is set to 1, this pin is used as the IRQ3 input pin.
2. The program development tool (emulator) does not support this function.
P83/LPCPD
The pin function is switched as shown below according to the state of the P83DDR bit.
P83DDR 0 1
P83 input pin P83 output pin Pin Function
LPCPD input pin*
Note: * When at least one of bits LPC3E to LPC1E is set to 1 in HICR0, this pin is used as the
LPCPD input pin.
P82/CLKRUN
The pin function is switched as shown below according to the combination of the LPC3E to
LPC1E bits in HICR0, and the P82DDR bit.
LPC3E to LPC1E All 0 Not all 0
P82DDR 0 1 0*
Pin Function P82 input pin P82 output pin CLKRUN I/O pin
Note: * When at least one of bits LPC3E to LPC1E is set to 1in HICR0, the P82DDR should be
cleared to 0.
Rev. 1.00, 05/04, page 121 of 544
P81/GA20
The pin function is switched as shown below according to the combination of the FGA20E bit
in HICR0 and the P81DDR bit.
FGA20E 0 1
P81DDR 0 1 0*
P81 input pin P81 output pin GA20 output pin Pin Function
GA20 input pin
Note: * When bit FGA20E is set to 1 in HICR0, the P81DDR bit should be cleared to 0.
P80/PME
The pin function is switched as shown below according to the combination of the PMEE bit in
HICR0 and the P80DDR bit.
PMEE 0 1
P80DDR 0 1 0*
P80 input pin P80 output pin PME output pin Pin Function
PME input pin
Note: * When bit PMEE is set to 1 in HICR0, the P80DDR bit should be cleared to 0.
Rev. 1.00, 05/04, page 122 of 544
7.9 Port 9
Port 9 is an 8-bit I/O port. Port 9 pins also function as the interrupt input pins, IIC_0 I/O pin,
subclock input pin, and system clock (φ) output pin. P97 is an NMOS push-pull output. SDA0 is
an NMOS open-drain output, and has direct bus drive capability. Port 9 has the following
registers.
Port 9 data direction register (P9DDR)
Port 9 data register (P9DR)
7.9.1 Port 9 Data Direction Register (P9DDR)
P9DDR specifies input or output for the pins of port 9 on a bit-by-bit basis.
Bit Bit Name
Initial
Value R/W Description
7 P97DDR 0 W
6 P96DDR 0 W
5 P95DDR 0 W
4 P94DDR 0 W
3 P93DDR 0 W
2 P92DDR 0 W
1 P91DDR 0 W
0 P90DDR 0 W
When the corresponding P9DDR bits are set to 1, pin
P96 functions as the φ output pin and pins P97 and
P95 to P90 become output ports. When P9DDR bits
are cleared to 0, the corresponding pins become input
ports.
7.9.2 Port 9 Data Register (P9DR)
P9DR stores output data for the port 9 pins.
Bit Bit Name
Initial
Value R/W Description
7 P97DR 0 R/W
6 P96DR Undefined* R
5 P95DR 0 R/W
4 P94DR 0 R/W
3 P93DR 0 R/W
2 P92DR 0 R/W
1 P91DR 0 R/W
0 P90DR 0 R/W
With the exception of P96, if a port 9 read is performed
while P9DDR bits are set to 1, the P9DR values are
read directly, regardless of the actual pin states. If a
port 9 read is performed while P9DDR bits are cleared
to 0, the pin states are read.
For P96, the pin state is always read.
Note: * The initial value of bit 6 is determined according to the P96 pin state.
Rev. 1.00, 05/04, page 123 of 544
7.9.3 Pin Functions
P97/SDA0
The pin function is switched as shown below according to the combination of the ICE bit in
ICCR of IIC_0, the IIC0AS and the IIC0BS bits in PGCTL*, and the P97DDR bit.
P97ICE = ICE (IIC0AS+IIC0BS)*
P97ICE* 0 1
P97DDR 0 1
Pin Function P97 input pin P97 output pin SDA0 I/O pin
Note: When this pin is set as the P97 output pin, it is an NMOS push-pull output. SDA0 is an
NMOS open-drain output, and has direct bus drive capability.
* The program development tool (emulator) does not support the function of PGCTL.
Thus P97ICE is treated as ICE.
P96/φ/EXCL
The pin function is switched as shown below according to the combination of the EXCLE bit
in LPWRCR and the P96DDR bit.
P96DDR 0 1
EXCLE 0 1 0
Pin Function P96 input pin EXCL input pin φ output pin
Note: * When this pin is used as the EXCL input pin, P96DDR should be cleared to 0.
P95
The pin function is switched as shown below according to the state of the P95DDR bit.
P95DDR 0 1
Pin Function P95 input pin P95 output pin
P94
The pin function is switched as shown below according to the state of the P94DDR bit.
P94DDR 0 1
Pin Function P94 input pin P94 output pin
P93
The pin function is switched as shown below according to the state of the P93DDR bit.
P93DDR 0 1
Pin Function P93 input pin P93 output pin
Rev. 1.00, 05/04, page 124 of 544
P92/IRQ0
The pin function is switched as shown below according to the state of the P92DDR bit.
P92DDR 0 1
P92 input pin P92 output pin Pin Function
IRQ0 input pin*
Note: * When bit IRQ0E in IER is set to 1, this pin is used as the IRQ0 input pin.
P91/IRQ1
The pin function is switched as shown below according to the state of the P91DDR bit.
P91DDR 0 1
P91 input pin P91 output pin Pin Function
IRQ1 input pin*
Note: * When bit IRQ1E in IER is set to 1, this pin is used as the IRQ1 input pin.
P90/IRQ2/ADTRG
The pin function is switched as shown below according to the state of the P90DDR bit.
P90DDR 0 1
P90 input pin P90 output pin Pin Function
IRQ2 input pin, ADTRG input pin*
Note: * When the IRQ2E bit in IER is set to 1, this pin is used as the IRQ2 input pin. When both
bits TRGS1 and TRGS0 in ADCR of the A/D converter are set to 1, this pin is used as
the AGTRG input pin.
Rev. 1.00, 05/04, page 125 of 544
7.10 Port A
Port A is an 8-bit I/O port. Port A pins also function as keyboard buffer controller I/O pins, and
key-sense interrupt input pins. Port A input/output operates by VccB power independent from the
Vcc power. Up to 5 V can be applied to port A pins if VccB power is 5 V. Port A has the
following registers. PADDR and PAPIN have the same address.
Port A data direction register (PADDR)
Port A output data register (PAODR)
Port A input data register (PAPIN)
7.10.1 Port A Data Direction Register (PADDR)
PADDR specifies input or output for the pins of port A on a bit-by-bit basis.
Bit Bit Name
Initial
Value R/W Description
7 PA7DDR 0 W
6 PA6DDR 0 W
5 PA5DDR 0 W
4 PA4DDR 0 W
3 PA3DDR 0 W
2 PA2DDR 0 W
1 PA1DDR 0 W
0 PA0DDR 0 W
The corresponding port A pins are output ports when
PADDR bits are set to 1, and input ports when
cleared to 0.
PA7 to PA2 pins are used as the keyboard buffer
controller I/O pins by setting the KBIOE bit to 1, while
the I/O direction according to PA7DDR to PA2DDR is
ignored.
PADDR has the same address as PAPIN, if read, port
A state is returned.
7.10.2 Port A Output Data Register (PAODR)
PAODR stores output data for port A.
Bit Bit Name
Initial
Value R/W Description
7 PA7ODR 0 R/W
6 PA6ODR 0 R/W
5 PA5ODR 0 R/W
4 PA4ODR 0 R/W
3 PA3ODR 0 R/W
2 PA2ODR 0 R/W
1 PA1ODR 0 R/W
0 PA0ODR 0 R/W
PAODR can always be read or written to, regardless
of the contents of PADDR.
Rev. 1.00, 05/04, page 126 of 544
7.10.3 Port A Input Data Register (PAPIN)
PAPIN indicates the port A state.
Bit Bit Name Initial Value R/W Description
7 PA7PIN Undefined* R
6 PA6PIN Undefined* R
5 PA5PIN Undefined* R
4 PA4PIN Undefined* R
3 PA3PIN Undefined* R
2 PA2PIN Undefined* R
1 PA1PIN Undefined* R
0 PA0PIN Undefined* R
Reading PAPIN always returns the pin states. PAPIN
has the same address as PADDR. If a write is
performed, the port A settings will change.
Note: * The initial value is determined according to the PA7 to PA0 pin states.
7.10.4 Pin Functions
PA7/KIN15/PS2CD
The pin function is switched as shown below according to the combination of the KBIOE bit in
KBCRH_2 of the keyboard buffer controller, and the PA7DDR bit.
KBIOE 0 1
PA7DDR 0 1
PA7 input pin PA7 output pin PS2CD output pin Pin Function
KIN15 input pin, PS2CD input pin*
Note: * When the KBIOE bit is set to 1 or the IICS bit in STCR is set to 1, this pin is an NMOS
open-drain output, and has direct bus drive capability. This pin can always be used as
the PS2CD or KIN15 input pin.
PA6/KIN14/PS2CC
The pin function is switched as shown below according to the combination of the KBIOE bit in
KBCRH_2 of the keyboard buffer controller, and the PA6DDR bit.
KBIOE 0 1
PA6DDR 0 1
PA6 input pin PA6 output pin PS2CC output pin Pin Function
KIN14 input pin, PS2CC input pin*
Note: * When the KBIOE bit is set to 1 or the IICS bit in STCR is set to 1, this pin is an NMOS
open-drain output, and has direct bus drive capability. This pin can always be used as
the PS2CC or KIN14 input pin.
Rev. 1.00, 05/04, page 127 of 544
PA5/KIN13/PS2BD
The pin function is switched as shown below according to the combination of the KBIOE bit in
KBCRH_1 of the keyboard buffer controller, and the PA5DDR bit.
KBIOE 0 1
PA5DDR 0 1
PA5 input pin PA5 output pin PS2BD output pin Pin Function
KIN13 input pin, PS2BD input pin*
Note: * When the KBIOE bit is set to 1 or the IICS bit in STCR is set to 1, this pin is an NMOS
open-drain output, and has direct bus drive capability. This pin can always be used as
the PS2BD or KIN13 input pin.
PA4/KIN12/PS2BC
The pin function is switched as shown below according to the combination of the KBIOE bit in
KBCRH_1 of the keyboard buffer controller, and the PA4DDR bit.
KBIOE 0 1
PA4DDR 0 1
PA4 input pin PA4 output pin PS2BC output pin Pin Function
KIN12 input pin, PS2BC input pin*
Note: * When the KBIOE bit is set to 1 or the IICS bit in STCR is set to 1, this pin is an NMOS
open-drain output, and has direct bus drive capability. This pin can always be used as
the PS2BC or KIN12 input pin.
PA3/KIN11/PS2AD
The pin function is switched as shown below according to the combination of the KBIOE bit in
KBCRH_0 of the keyboard buffer controller, and the PA3DDR bit.
KBIOE 0 1
PA3DDR 0 1
PA3 input pin PA3 output pin PS2AD output pin Pin Function
KIN11 input pin, PS2AD input pin*
Note: * When the KBIOE bit is set to 1, this pin is an NMOS open-drain output, and has direct
bus drive capability. This pin can always be used as the PS2AD or KIN11 input pin.
Rev. 1.00, 05/04, page 128 of 544
PA2/KIN10/PS2AC
The pin function is switched as shown below according to the combination of the KBIOE bit in
KBCRH_0 of the keyboard buffer controller, and the PA2DDR bit.
KBIOE 0 1
PA2DDR 0 1
PA2 input pin PA2 output pin PS2AC output pin Pin Function
KIN10 input pin, PS2AC input pin*
Note: * When the KBIOE bit is set to 1, this pin is an NMOS open-drain output, and has direct
bus drive capability. This pin can always be used as the PS2AC or KIN10 input pin.
PA1/KIN9, PA0/KIN8
The pin function is switched as shown below according to the state of the PAnDDR bit.
PAnDDR 0 1
PAn input pin PAn output pin Pin Function
KINm input pin*
Note: * This pin can always be used as the KINm input pin. (n = 1 or 0, m = 9 or 8)
7.10.5 Port A Input Pull-Up MOS
Port A has an on-chip input pull-up MOS function that can be controlled by software. This input
pull-up MOS function can be specified as on or off on a bit-by-bit basis.
The input pull-up MOS for pins PA7 to PA4 is always off when IICS is set to 1. When the
keyboard buffer control pin function is selected for pins PA7 to PA2, the input pull-up MOS is
always off.
Table 7.6 summarizes the input pull-up MOS states.
Table 7.6 Input Pull-Up MOS States (Port A)
Reset Hardware Standby Mode Software Standby Mode In Other Operations
Off Off On/Off On/Off
[Legend]
Off: Input pull-up MOS is always off.
On/Off: On when the pin is in the input state, PADDR = 0, and PAODR = 1; otherwise off.
Rev. 1.00, 05/04, page 129 of 544
7.11 Port B
Port B is an 8-bit I/O port. Port B pins also have LPC input/output pins, and wakeup event
interrupt input pins function. Port B has the following registers.
Port B data direction register (PBDDR)
Port B output data register (PBODR)
Port B input data register (PBPIN)
7.11.1 Port B Data Direction Register (PBDDR)
PBDDR specifies input or output for the pins of port B on a bit-by-bit basis.
Bit Bit Name Initial
Value R/W Description
7 PB7DDR 0 W
6 PB6DDR 0 W
5 PB5DDR 0 W
4 PB4DDR 0 W
3 PB3DDR 0 W
2 PB2DDR 0 W
1 PB1DDR 0 W
0 PB0DDR 0 W
PBDDR has the same address as P7PIN, and if read,
the port 7 pin states will be returned.
A port B pin becomes an output port if the
corresponding PBDDR bit is set to 1, and an input port
if the bit is cleared to 0.
7.11.2 Port B Output Data Register (PBODR)
PBODR stores output data for port B.
Bit Bit Name Initial
Value R/W Description
7 PB7ODR 0 R/W
6 PB6ODR 0 R/W
5 PB5ODR 0 R/W
4 PB4ODR 0 R/W
3 PB3ODR 0 R/W
2 PB2ODR 0 R/W
1 PB1ODR 0 R/W
0 PB0ODR 0 R/W
PBODR can always be read or written to, regardless of
the contents of PBDDR.
Rev. 1.00, 05/04, page 130 of 544
7.11.3 Port B Input Data Register (PBPIN)
PBPIN indicates the port B state.
Bit Bit Name Initial
Value R/W Description
7 PB7PIN Undefined* R
6 PB6PIN Undefined* R
5 PB5PIN Undefined* R
4 PB4PIN Undefined* R
3 PB3PIN Undefined* R
2 PB2PIN Undefined* R
1 PB1PIN Undefined* R
0 PB0PIN Undefined* R
Reading PBPIN always returns the pin states. PBPIN
has the same address as P8DDR. If a write is
performed, data will be written to P8DDR and the port
8 settings will change.
Note: * The initial value is determined according to the PB7 to PB0 pin states.
7.11.4 Pin Functions
PB7/WUE7, PB6/WUE6, PB5/WUE5, PB4/WUE4, PB3/WUE3, PB2/WUE2
The pin function is switched as shown below according to the state of the PBnDDR bit.
PBnDDR 0 1
PBn input pin PBn output pin Pin Function
WUEn input pin*
Note: * This pin can always be used as the WUEn input pin. (n = 7 to 2)
PB1/WUE1/LSCI
The pin function is switched as shown below according to the combination of the LSCIE bit in
HICR0 of the host interface (LPC) and the PB1DDR bit.
LSCIE 0 1
PB1DDR 0 1 0*1
PB1input pin PB1 output pin LSCI output pin Pin Function
WUE1 input pin*2, LSCI input pin*2
Notes: 1. When the LSCIE bit in HICR0 is set to 1, the PB1DDR bit should be cleared to 0.
2. This pin can always be used as the WUE1 or LSCI input pin.
Rev. 1.00, 05/04, page 131 of 544
PB0/WUE0/LSMI
The pin function is switched as shown below according to the combination of the LSMIE bit in
HICR0 of the host interface (LPC) and the PB0DDR bit.
LSMIE 0 1
PB0DDR 0 1 0*1
PB0 input pin PB0 output pin LSMI output pin Pin Function
WUE0 input pin*2, LSMI input pin*2
Notes: 1. When the LSMIE bit in HICR0 is set to 1, the PB0DDR bit should be cleared to 0.
2. This pin can always be used as the WUE0 or LSMI input pin.
7.11.5 Port B Input Pull-Up MOS
Port B has an on-chip input pull-up MOS function that can be controlled by software. This input
pull-up MOS function can be specified as on or off on a bit-by-bit basis.
When a pin is designated as an on-chip peripheral module output pin, the input pull-up MOS is
always off.
Table 7.7 summarizes the input pull-up MOS states.
Table 7.7 Input Pull-Up MOS States (Port B)
Reset Hardware Standby Mode Software Standby Mode In Other Operations
Off Off On/Off On/Off
[Legend]
Off: Input pull-up MOS is always off.
On/Off: On when the pin is in the input state, PBDDR = 0, and PBODR = 1; otherwise off.
Rev. 1.00, 05/04, page 132 of 544
7.12 Ports C, D
Port C and port D are two sets of 8-bit I/O ports. Port C and port D have the following registers.
Port C data direction register (PCDDR)
Port C output data register (PCODR)
Port C input data register (PCPIN)
Port C Nch-OD control register (PCNOCR)
Port D data direction register (PDDDR)
Port D output data register (PDODR)
Port D input data register (PDPIN)
Port D Nch-OD control register (PDNOCR)
7.12.1 Port C and Port D Data Direction Registers (PCDDR, PDDDR)
PCDDR and PDDDR select input or output for the pins of port C and port D on a bit-by-bit basis.
Bit Bit Name Initial
Value R/W Description
7 PC7DDR 0 W
6 PC6DDR 0 W
5 PC5DDR 0 W
4 PC4DDR 0 W
3 PC3DDR 0 W
2 PC2DDR 0 W
1 PC1DDR 0 W
0 PC0DDR 0 W
0: Port C pin is an input pin
1: Port C pin is an output pin
PCDDR has the same address as PCPIN, and if read,
the port C pin states will be returned.
Bit Bit Name Initial
Value R/W Description
7 PD7DDR 0 W
6 PD6DDR 0 W
5 PD5DDR 0 W
4 PD4DDR 0 W
3 PD3DDR 0 W
2 PD2DDR 0 W
1 PD1DDR 0 W
0 PD0DDR 0 W
0: Port D pin is an input pin
1: Port D pin is an output pin
PDDDR has the same address as PDPIN, and if read,
the port D pin states will be returned.
Rev. 1.00, 05/04, page 133 of 544
7.12.2 Port C and Port D Output Data Registers (PCODR, PDODR)
PCODR and PDODR store output data for the pins on ports C and D.
Bit Bit Name Initial
Value R/W Description
7 PC7ODR 0 R/W
6 PC6ODR 0 R/W
5 PC5ODR 0 R/W
4 PC4ODR 0 R/W
3 PC3ODR 0 R/W
2 PC2ODR 0 R/W
1 PC1ODR 0 R/W
0 PC0ODR 0 R/W
PCODR can always be read or written to, regardless of
the contents of PCDDR.
Bit Bit Name Initial
Value R/W Description
7 PD7ODR 0 R/W
6 PD6ODR 0 R/W
5 PD5ODR 0 R/W
4 PD4ODR 0 R/W
3 PD3ODR 0 R/W
2 PD2ODR 0 R/W
1 PD1ODR 0 R/W
0 PD0ODR 0 R/W
PDODR can always be read or written to, regardless of
the contents of PDDDR.
7.12.3 Port C and Port D Input Data Registers (PCPIN, PDPIN)
Reading PCPIN and PDPIN always returns the pin states.
Bit Bit Name Initial
Value R/W Description
7 PC7PIN Undefined* R
6 PC6PIN Undefined* R
5 PC5PIN Undefined* R
4 PC4PIN Undefined* R
3 PC3PIN Undefined* R
2 PC2PIN Undefined* R
1 PC1PIN Undefined* R
0 PC0PIN Undefined* R
PCPIN indicates the port C state. PCPIN has the same
address as PCDDR. If a write is performed, the port C
settings will change.
Note: * The initial value is determined according to the PC7 to PC0 pin states.
Rev. 1.00, 05/04, page 134 of 544
Bit Bit Name Initial
Value R/W Description
7 PD7PIN Undefined* R
6 PD6PIN Undefined* R
5 PD5PIN Undefined* R
4 PD4PIN Undefined* R
3 PD3PIN Undefined* R
2 PD2PIN Undefined* R
1 PD1PIN Undefined* R
0 PD0PIN Undefined* R
PDPIN indicates the port D state. PDPIN has the same
address as PDDDR. If a write is performed, the port D
settings will change.
Note: * The initial value is determined according to the PD7 to PD0 pin states.
7.12.4 Port C and Port D Nch-OD Control Register (PCNOCR, PDNOCR)
PCNOCR and PDNOCR specify the output driver type for pins on ports C and D which are
configured as outputs on a bit-by-bit basis.
Bit Bit Name
Initial
Value R/W Description
7 PC7NOCR 0 R/W
6 PC6NOCR 0 R/W
5 PC5NOCR 0 R/W
4 PC4NOCR 0 R/W
3 PC3NOCR 0 R/W
2 PC2NOCR 0 R/W
1 PC1NOCR 0 R/W
0 PC0NOCR 0 R/W
0: CMOS (p-channel driver enabled)
1: N-channel open drain (p-channel driver disabled
Bit Bit Name
Initial
Value R/W Description
7 PD7NOCR 0 R/W
6 PD6NOCR 0 R/W
5 PD5NOCR 0 R/W
4 PD4NOCR 0 R/W
3 PD3NOCR 0 R/W
2 PD2NOCR 0 R/W
1 PD1NOCR 0 R/W
0 PD0NOCR 0 R/W
0: CMOS (p-channel driver enabled)
1: N-channel open drain (p-channel driver disabled)
Rev. 1.00, 05/04, page 135 of 544
7.12.5 Pin Functions
DDR 0 1
NOCR — 0 1
ODR 0 1 0 1 0 1
N-ch. driver OFF ON OFF ON OFF
P-ch. driver OFF OFF ON OFF
Input pull-up
MOS
OFF ON OFF
Pin function Input pin Output pin
7.12.6 Input Pull-Up MOS in Ports C and D
Port C and port D have an on-chip input pull-up MOS function that can be controlled by software.
This input pull-up MOS function can be switched on or off on a bit-by-bit basis.
Table 7.8 is a summary of the input pull-up MOS states.
Table 7.8 Input Pull-Up MOS States (Port C and port D)
Reset Hardware Standby Mode Software Standby Mode Other Operations
Off Off On/Off On/Off
[Legend]
Off: Input pull-up MOS is always off.
On/Off: On when PCDDR = 0 and PCODR = 1 (PDDDR = 0 and PDODR = 1); otherwise off.
Rev. 1.00, 05/04, page 136 of 544
7.13 Ports E, F
Ports E and F are two sets of 8-bit I/O ports. Port F also functions as I/O pins for TMR_X*,
TMR_Y*, TMR_A, and TMR_B. Ports E and F have the following registers.
Port E data direction register (PEDDR)
Port E output data register (PEODR)
Port E input data register (PEPIN)
Port E Nch-OD control register (PENOCR)
Port F data direction register (PFDDR)
Port F output data register (PFODR)
Port F input data register (PFPIN)
Port F Nch-OD control register (PFNOCR)
Note: * The program development tool (emulator) does not support this function.
7.13.1 Port E and Port F Data Direction Registers (PEDDR, PFDDR)
PEDDR and PFDDR select input or output for the pins of port E and port F on a bit-by-bit basis.
Bit Bit Name
Initial
Value R/W Description
7 PE7DDR 0 W
6 PE6DDR 0 W
5 PE5DDR 0 W
4 PE4DDR 0 W
3 PE3DDR 0 W
2 PE2DDR 0 W
1 PE1DDR 0 W
0 PE0DDR 0 W
0: Port E pin is an input pin
1: Port E pin is an output pin
PEDDR has the same address as PEPIN, and if read,
the port E pin states will be returned.
Bit Bit Name
Initial
Value R/W Description
7 PF7DDR 0 W
6 PF6DDR 0 W
5 PF5DDR 0 W
4 PF4DDR 0 W
3 PF3DDR 0 W
2 PF2DDR 0 W
1 PF1DDR 0 W
0 PF0DDR 0 W
0: Port F pin is an input pin
1: Port F pin is an output pin
PFDDR has the same address as PFPIN, and if read,
the port F pin states will be returned.
Rev. 1.00, 05/04, page 137 of 544
7.13.2 Port E and Port F Output Data Registers (PEODR, PFODR)
PEODR and PFODR store output data for the pins on ports E and F.
Bit Bit Name
Initial
Value R/W Description
7 PE7ODR 0 R/W
6 PE6ODR 0 R/W
5 PE5ODR 0 R/W
4 PE4ODR 0 R/W
3 PE3ODR 0 R/W
2 PE2ODR 0 R/W
1 PE1ODR 0 R/W
0 PE0ODR 0 R/W
PEODR can always be read or written to, regardless of
the contents of PEDDR.
Bit Bit Name
Initial
Value R/W Description
7 PF7ODR 0 R/W
6 PF6ODR 0 R/W
5 PF5ODR 0 R/W
4 PF4ODR 0 R/W
3 PF3ODR 0 R/W
2 PF2ODR 0 R/W
1 PF1ODR 0 R/W
0 PF0ODR 0 R/W
PFODR can always be read or written to, regardless of
the contents of PFDDR.
Rev. 1.00, 05/04, page 138 of 544
7.13.3 Port E and Port F Input Data Registers (PEPIN, PFPIN)
Reading PEPIN and PFPIN always returns the pin states.
Bit Bit Name
Initial
Value R/W Description
7 PE7PIN Undefined* R
6 PE6PIN Undefined* R
5 PE5PIN Undefined* R
4 PE4PIN Undefined* R
3 PE3PIN Undefined* R
2 PE2PIN Undefined* R
1 PE1PIN Undefined* R
0 PE0PIN Undefined* R
PEPIN indicates the port E state. PEPIN has the same
address as PEDDR. If a write is performed, the port E
settings will change.
Note: * The initial value is determined according to the PE7 to PE0 pin states.
Bit Bit Name
Initial
Value R/W Description
7 PF7PIN Undefined* R
6 PF6PIN Undefined* R
5 PF5PIN Undefined* R
4 PF4PIN Undefined* R
3 PF3PIN Undefined* R
2 PF2PIN Undefined* R
1 PF1PIN Undefined* R
0 PF0PIN Undefined* R
PFPIN indicates the port F state. PFPIN has the same
address as PFDDR. If a write is performed, the port F
settings will change.
Note: * The initial value is determined according to the PF7 to PF0 pin states.
7.13.4 Pin Functions
PF7/TMOY
The pin function is switched as shown below according to the combination of the IOSY bit* in
TCRXY of TMT_Y, the OS3 to OS0 bits in TCSR_Y, and the PF7DDR bit.
IOSY* 0 1
OS3 to OS0 All 0 Not all 0
PF7DDR 0 1 0 1
Pin Function PF7
input pin
PF7
output pin
PF7
input pin
PF7
output pin
TMOY
output pin*
Notes: * The program development tool (emulator) does not support this function.
Rev. 1.00, 05/04, page 139 of 544
PF6/ExTMOX
The pin function is switched as shown below according to the combination of the IOSX bit* in
TCRXY of TMR_X, the OS3 to OS0 bits in TCSR_X, and the PF6DDR bit.
IOSX* 0 1
OS3 to OS0 All 0 Not all 0
PF6DDR 0 1 0 1
Pin Function PF6
input pin
PF6
output pin
PF6
input pin
PF6
output pin
ExTMOX
output pin*
Notes: * The program development tool (emulator) does not support this function.
PF5/ExTMIY
The pin function is switched as shown below according to the state of the PF5DDR bit.
PF5DDR 0 1
PF5 input pin PF5 output pin Pin Function
ExTMIY input pin *
Note: * The program development tool (emulator) does not support this function. When the
IOSY bit is set to 1, this pin can be used as the ExTMIY input pin.
PF4/ExTMIX
The pin function is switched as shown below according to the state of the PF4DDR bit.
PF4DDR 0 1
PF4 input pin PF4 output pin Pin Function
ExTMIX input pin*
Note: * The program development tool (emulator) does not support this function. When the
IOSX bit is set to 1, this pin can be used as the ExTMIX input pin.
PF3/TMOB
The pin function is switched as shown below according to the combination of the OS3 to OS0
bits in TCSR_B of TMR_B and the PF3DDR bit.
OS3 to OS0 All 0 Not all 0
PF3DDR 0 1
Pin Function PF3 input pin PF3 output pin TMOB output pin
Rev. 1.00, 05/04, page 140 of 544
PF2/TMOA
The pin function is switched as shown below according to the combination of the OS3 to OS0
bits in TCSR_A of TMR_A and the PF2DDR bit.
OS3 to OS0 All 0 Not all 0
PF3DDR 0 1
Pin Function PF2 input pin PF2 output pin TMOA output pin
PF1/TMIB
The pin function is switched as shown below according to the state of the PF1DDR bit.
PF1DDR 0 1
PF1 input pin PF1 output pin Pin Function
TMIB input pin*
Note: * This pin can always be used as the TMIB input pin.
PF0/TMIA
The pin function is switched as shown below according to the state of the PF0DDR bit.
PF0DDR 0 1
PF0 input pin PF0 output pin Pin Function
TMIA input pin*
Note: * This pin can always be used as the TMIA input pin.
7.13.5 Port E and Port F Nch-OD Control Register (PENOCR, PFNOCR)
PENOCR and PFNOCR specify the output driver type for pins on ports E and F which are
configured as outputs on a bit-by-bit basis.
Bit Bit Name
Initial
Value R/W Description
7 PE7NOCR 0 R/W
6 PE6NOCR 0 R/W
5 PE5NOCR 0 R/W
4 PE4NOCR 0 R/W
3 PE3NOCR 0 R/W
2 PE2NOCR 0 R/W
1 PE1NOCR 0 R/W
0 PE0NOCR 0 R/W
0: CMOS (p-channel driver enabled)
1: N-channel open drain (p-channel driver disabled)
Rev. 1.00, 05/04, page 141 of 544
Bit Bit Name
Initial
Value R/W Description
7 PF7NOCR 0 R/W
6 PF6NOCR 0 R/W
5 PF5NOCR 0 R/W
4 PF4NOCR 0 R/W
3 PF3NOCR 0 R/W
2 PF2NOCR 0 R/W
1 PF1NOCR 0 R/W
0 PF0NOCR 0 R/W
0: CMOS (p-channel driver enabled)
1: N-channel open drain (p-channel driver disabled)
7.13.6 Pin Functions
DDR 0 1
NOCR — 0 1
ODR 0 1 0 1 0 1
N-ch. driver OFF ON OFF ON OFF
P-ch. driver OFF OFF ON OFF
Input pull-up
MOS
OFF ON OFF
Pin function Input pin Output pin*
Note: * Includes when set as the timer output pin.
7.13.7 Input Pull-Up MOS in Ports E and F
Port E and port F have an on-chip input pull-up MOS function that can be controlled by software.
This input pull-up MOS function can be switched on or off on a bit-by-bit basis.
Table 7.9 is a summary of the input pull-up MOS states.
Table 7.9 Input Pull-Up MOS States (Port E and port F)
Reset Hardware Standby Mode Software Standby Mode Other Operations
Off Off On/Off On/Off
[Legend]
Off: Input pull-up MOS is always off.
On/Off: On when PEDDR = 0 and PEODR = 1 (PFDDR = 0 and PFODR = 1) with the pin in input
state; otherwise off.
Rev. 1.00, 05/04, page 142 of 544
7.14 Port G
Port G is an 8-bit I/O port. Port G pins also function as IIC_0 and IIC_1 I/O pins. The output type
of port G is NMOS push-pull output. The output type of ExSCLB*, ExSDAB*, ExSCLA*, and
ExSDAA* is NMOS open-drain output and the pins can directly drive the bus. Port G has the
following registers. For details of PGCTL, see section 13.3.9, Port G Control Register (PGCTL).
Port G data direction register (PGDDR)
Port G output data register (PGODR)
Port G input data register (PGPIN)
Port G Nch-OD control register (PGNOCR)
Port G control register (PGCTL)*
Note: * The program development tool (emulator) does not support this function.
7.14.1 Port G Data Direction Register (PGDDR)
PGDDR selects input or output for the pins of port G on a bit-by-bit basis.
Bit Bit Name
Initial
Value R/W Description
7 PG7DDR 0 W
6 PG6DDR 0 W
5 PG5DDR 0 W
4 PG4DDR 0 W
3 PG3DDR 0 W
2 PG2DDR 0 W
1 PG1DDR 0 W
0 PG0DDR 0 W
0: Port G pin is an input pin
1: Port G pin is an output pin
PGDDR has the same address as PGPIN, and if read,
the port G pin states will be returned.
Rev. 1.00, 05/04, page 143 of 544
7.14.2 Port G Output Data Register (PGODR)
PGODR stores output data for the pins on port G.
Bit Bit Name
Initial
Value R/W Description
7 PG7ODR 0 R/W
6 PG6ODR 0 R/W
5 PG5ODR 0 R/W
4 PG4ODR 0 R/W
3 PG3ODR 0 R/W
2 PG2ODR 0 R/W
1 PG1ODR 0 R/W
0 PG0ODR 0 R/W
PGODR can always be read or written to, regardless of
the contents of PGDDR.
7.14.3 Port G Input Data Register (PGPIN)
Reading PGPIN always returns the pin states.
Bit Bit Name
Initial
Value R/W Description
7 PG7PIN Undefined* R
6 PG6PIN Undefined* R
5 PG5PIN Undefined* R
4 PG4PIN Undefined* R
3 PG3PIN Undefined* R
2 PG2PIN Undefined* R
1 PG1PIN Undefined* R
0 PG0PIN Undefined* R
PGPIN indicates the port G state. PGPIN has the same
address as PGDDR. If a write is performed, the port G
settings will change.
Note: * The initial value is determined according to the PG7 to PG0 pin states.
Rev. 1.00, 05/04, page 144 of 544
7.14.4 Pin Functions
PG7/ExSCLB
The pin function is switched as shown below according to the combination of the IIC1BS and
the IIC0BS bits in PGCTL of the IIC* and the PG7DDR bit.
IIC1BS and IIC0BS* All 0 Not all 0
PG7DDR 0 1
Pin Function PG7 input pin PG7 output pin ExSCLB I/O pin*
Note: * The program development tool (emulator) does not support this function. The output
type of ExSCLB is NMOS open-drain output and this pin has direct bus drive capability.
PG6/ExSDAB
The pin function is switched as shown below according to the combination of the IIC1BS and
the IIC0BS bits in PGCTL of the IIC* and the PG6DDR bit.
IIC1BS and IIC0BS* All 0 Not all 0
PG6DDR 0 1
Pin Function PG6 input pin PG6 output pin ExSDAB I/O pin*
Note: * The program development tool (emulator) does not support this function. The output
type of ExSDAB is NMOS open-drain output and this pin has direct bus drive capability.
PG5/ExSCLA
The pin function is switched as shown below according to the combination of the IIC1AS and
the IIC0AS bits in PGCTL of the IIC* and the PG5DDR bit.
IIC1AS and IIC0AS* All 0 Not all 0
PG5DDR 0 1
Pin Function PG5 input pin PG5 output pin ExSCLA I/O pin*
Note: * The program development tool (emulator) does not support this function. The output
type of ExSCLA is NMOS open-drain output and this pin has direct bus drive capability.
PG4/ExSDAA
The pin function is switched as shown below according to the combination of the IIC1AS and
the IIC0AS bits in PGCTL of the IIC* and the PG4DDR bit.
IIC1AS and IIC0AS* All 0 Not all 0
PG4DDR 0 1
Pin Function PG4 input pin PG4 output pin ExSDAA I/O pin*
Note: * The program development tool (emulator) does not support this function. The output
type of ExSDAA is NMOS open-drain output and this pin has direct bus drive capability.
Rev. 1.00, 05/04, page 145 of 544
PG3, PG2, PG1, PG0
The pin function is switched as shown below according to the state of the PGnDDR bit.
PGnDDR 0 1
Pin Function PGn input pin PGn output pin
[Legend]
n = 3 to 0
7.14.5 Port G Nch-OD Control Register (PGNOCR)
PGNOCR specifies the output driver type for pins on port G which are configured as outputs on a
bit-by-bit basis.
Bit Bit Name
Initial
Value R/W Description
7 PG7NOCR 0 R/W
6 PG6NOCR 0 R/W
5 PG5NOCR 0 R/W
4 PG4NOCR 0 R/W
3 PG3NOCR 0 R/W
2 PG2NOCR 0 R/W
1 PG1NOCR 0 R/W
0 PG0NOCR 0 R/W
0: NMOS push-pull (Vcc-side n-channel driver enabled)
1: Vss-side N-channel open drain (Vcc-side N-channel
driver disabled)
7.14.6 Pin Functions
DDR 0 1
NOCR — 0 1
ODR 0 1 0 1 0 1
Vss-side N-ch. driver OFF ON OFF ON OFF
Vcc-side N-ch. driver OFF OFF ON OFF
Pin function Input pin Output pin*
Note: * Except when set as IIC I/O pin.
Rev. 1.00, 05/04, page 146 of 544
PWM0800B_000120040200 Rev. 1.00, 05/04, page 147 of 544
Section 8 8-Bit PWM Timer (PWM)
This LSI has an on-chip pulse width modulation (PWM) timer with eight outputs. Eight output
waveforms are generated from a common time base, enabling PWM output with a high carrier
frequency to be produced using pulse division. Connecting a low pass filter externally to the LSI
enables the PWM to function as an 8-bit D/A converter.
8.1 Features
Operable at a maximum carrier frequency of 625 kHz using pulse division (at 10 MHz
operation)
Duty cycles from 0 to 100% with 1/256 resolution (100% duty realized by port output)
Direct or inverted PWM output, and PWM output enable/disable control
Figure 8.1 shows a block diagram of the PWM timer.
P10/PW0
P11/PW1
P12/PW2
P13/PW3
P14/PW4
P15/PW5
P16/PW6
P17/PW7
Comparator 0
Comparator 1
Comparator 2
Comparator 3
Comparator 4
Comparator 5
Comparator 6
Comparator 7
PWDR0
PWDR1
PWDR2
PWDR3
PWDR4
PWDR5
PWDR6
PWDR7
PWSL
PWDPRA
PWOERA
P1DDR
[Legend]
Note: * The program development tool (emulator) does not support this function.
PWSL:
PWDR:
PWDPRA:
PWOERA:
PCSR:
P1DDR:
PWM register select
PWM data register
PWM data polarity register A
PWM output enable register A
Peripheral clock select register
Port 1 data direction register
PCSR
Port/PWM output control
Module
data bus
Internal
data bus
Bus interface
Select
clock
Clock
counter
Internal clock
φ
φ/8
φ/2
φ/4
φ/16
φ/256*
φ/4096*
φ/512*
φ/1024*
Figure 8.1 Block Diagram of PWM Timer
Rev. 1.00, 05/04, page 148 of 544
8.2 Input/Output Pins
Table 8.1 shows the PWM output pins.
Table 8.1 Pin Configuration
Name Abbreviation I/O Function
PWM output 7 to 0 PW7 to PW0 Output PWM timer pulse output 7 to 0
8.3 Register Descriptions
The PWM has the following registers. To access PCSR, the FLSHE bit in the serial timer control
register (STCR) must be cleared to 0. For details on the serial timer control register (STCR), see
section 3.2.3, Serial Timer Control Register (STCR).
PWM register select (PWSL)
PWM data registers 7 to 0 (PWDR7 to PWDR0)
PWM data polarity register A (PWDPRA)
PWM output enable register A (PWOERA)
Peripheral clock select register (PCSR)
Rev. 1.00, 05/04, page 149 of 544
8.3.1 PWM Register Select (PWSL)
PWSL is used to select the input clock and the PWM data register.
Bit Bit Name Initial Value R/W Description
7
6
PWCKE
PWCKS
0
0
R/W
R/W
PWM Clock Enable
PWM Clock Select
These bits, together with bits PWCKC, PWCKB and
PWCKA in PCSR, select the internal clock input to
TCNT in the PWM. For details, see table 8.2.
The resolution, PWM conversion period, and carrier
frequency depend on the selected internal clock, and
can be obtained from the following equations.
Resolution (minimum pulse width) = 1/internal clock
frequency
PWM conversion period = resolution × 256
Carrier frequency = 16/PWM conversion period
With a 10 MHz system clock (φ), the resolution, PWM
conversion period, and carrier frequency are as shown
in table 8.3.
5 — 1 R Reserved
Always read as 1 and cannot be modified.
4 — 0 R Reserved
Always read as 0 and cannot be modified.
3
2
1
0
RS3
RS2
RS1
RS0
0
0
0
0
R/W
R/W
R/W
R/W
Register Select
These bits select the PWM data register.
0000: PWDR0 selected
0001: PWDR1 selected
0010: PWDR2 selected
0011: PWDR3 selected
0100: PWDR4 selected
0101: PWDR5 selected
0110: PWDR6 selected
0111: PWDR7 selected
1xxx: No effect on operation
[Legend]
x: Don't care.
Rev. 1.00, 05/04, page 150 of 544
Table 8.2 Internal Clock Selection
PWSL PCSR
PWCKE PWCKS PWCKC PWCKB PWCKA Description
0 Clock input is disabled (Initial value)
1 0 — — — φ (system clock) is selected
1 0 0 0 φ/2 is selected
0 0 1 φ/4 is selected
0 1 0 φ/8 is selected
0 1 1 φ/16 is selected
1 0 0 φ/256 is selected*
1 0 1 φ/512 is selected*
1 1 0 φ/1024 is selected*
1 1 1 φ/4096 is selected*
Note: * The program development tool (emulator) does not support this function.
Table 8.3 Resolution, PWM Conversion Period, and Carrier Frequency when φ = 10 MHz
Internal Clock
Frequency Resolution PWM
Conversion Period Carrier Frequency
φ 100 ns 25.6 µs 625 kHz
φ/2 200 ns 51.2 µs 312.5 kHz
φ/4 400 ns 102 µs 156.3 kHz
φ/8 800 ns 205 µs 78.1 kHz
φ/16 1.6 µs 410 µs 39.1 kHz
φ/256* 25.6 µs 6.55 ms 2.4 kHz
φ/512* 51.2 µs 13.1 ms 1.2 kHz
φ/1024* 102 µs 26.2 ms 610 kHz
φ/4096* 410 µs 105 ms 152 kHz
Note: * The program development tool (emulator) does not support this function.
Rev. 1.00, 05/04, page 151 of 544
8.3.2 PWM Data Registers 7 to 0 (PWDR7 to PWD0)
PWDR are 8-bit readable/writable registers. The PWM has eight PWM data registers. Each
PWDR specifies the duty cycle of the basic pulse to be output, and the number of additional
pulses. The value set in PWDR corresponds to a 0 or 1 ratio in the conversion period. The upper
four bits specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolution of 1/16. The
lower four bits specify how many extra pulses are to be added within the conversion period
comprising 16 basic pulses. Thus, a specification of 0/256 to 255/256 is possible for 0/1 ratios
within the conversion period. For 256/256 (100%) output, port output should be used.
8.3.3 PWM Data Polarity Register A (PWDPRA)
PWDPRA selects the PWM output phase.
Bit Bit
Name Initial
Value R/W Description
7
6
5
4
3
2
1
0
OS7
OS6
OS5
OS4
OS3
OS2
OS1
OS0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Output Select 7 to 0
These bits select the PWM output phase. Bits OS7 to
OS0 correspond to outputs PW7 to PW0.
0: PWM direct output (PWDR value corresponds to high
width of output)
1: PWM inverted output (PWDR value corresponds to
low width of output)
Rev. 1.00, 05/04, page 152 of 544
8.3.4 PWM Output Enable Register A (PWOERA)
PWOERA switches between PWM output and port output.
Bit Bit
Name Initial
Value R/W Description
7
6
5
4
3
2
1
0
OE7
OE6
OE5
OE4
OE3
OE2
OE1
OE0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Output Enable 7 to 0
These bits, together with P1DDR, specify the P1n/PWn
pin state. Bits OE7 to OE0 correspond to outputs PW7
to PW0.
P1nDDR OEn: Pin state
0 x: Port input
1 0: Port output or PWM 256/256 output
1 1: PWM output (0 to 255/256 output)
[Legend]
x: Don't care
Note: n = 7 to 0
To perform PWM 256/256 output when DDR = 1 and OE = 0, the corresponding pin should be set
to port output.
DR data is output when the corresponding pin is used as port output. A value corresponding to
PWM 256/256 output is determined by the OS bit, so the value should have been set to DR
beforehand.
8.3.5 Peripheral Clock Select Register (PCSR)
PCSR selects the PWM input clock.
Bit Bit Name
Initial
Value R/W Description
7 to 4 All 0 R/W Reserved
These bits cannot be modified.
3
2
1
PWCKC*
PWCKB
PWCKA
0
0
0
R/W
R/W
R/W
PWM Clock Select C, B, A
Together with bits PWCKE and PWCKS in PWSL,
these bits select the internal clock input to the clock
counter in the PWM. For details, see table 8.2.
0 0 R/W Reserved
These bits cannot be modified.
Note: The program development tool (emulator) does not support this function.
Rev. 1.00, 05/04, page 153 of 544
8.4 Operation
The upper four bits of PWDR specify the duty cycle of the basic pulse as 0/16 to 15/16 with a
resolution of 1/16. Table 8.4 shows the duty cycles of the basic pulse.
Table 8.4 Duty Cycle of Basic Pulse
0H:
L:
123456789ABCDEF0
Upper 4 Bits Basic Pulse Waveform (Internal)
B'0000
B'0001
B'0010
B'0011
B'0100
B'0101
B'0110
B'0111
B'1000
B'1001
B'1010
B'1011
B'1100
B'1101
B'1110
B'1111
Rev. 1.00, 05/04, page 154 of 544
The lower four bits of PWDR specify the position of pulses added to the 16 basic pulses. An
additional pulse adds a high period (when OS = 0) with a width equal to the resolution before the
rising edge of a basic pulse. When the upper four bits of PWDR are B'0000, there is no rising edge
of the basic pulse, but the timing for adding pulses is the same. Table 8.5 shows the positions of
the additional pulses added to the basic pulses, and figure 8.2 shows an example of additional
pulse timing.
Table 8.5 Position of Pulses Added to Basic Pulses
Basic Pulse No.
Lower 4 Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
B'0000
B'0001 Yes
B'0010 Yes Yes
B'0011 Yes Yes Yes
B'0100 Yes Yes Yes Yes
B'0101 Yes Yes Yes Yes Yes
B'0110 Yes Yes Yes Yes Yes Yes
B'0111 Yes Yes Yes Yes Yes Yes Yes
B'1000 Yes Yes Yes Yes Yes Yes Yes Yes
B'1001 Yes Yes Yes Yes Yes Yes Yes Yes Yes
B'1010 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
B'1011 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
B'1100 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
B'1101 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
B'1110 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
B'1111 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
No additional pulse
With additional pulse
Resolution width
Additioal pulse
Figure 8.2 Example of Additional Pulse Timing (When Upper 4 Bits of PWDR = B'1000)
Rev. 1.00, 05/04, page 155 of 544
8.4.1 PWM Setting Example
: Pulse added
1-conversion cycle
Combination of the basic pulse and added pulse outputs 0/256 to 255/256 of dudty cycle as low ripple wave form.
Duty cycle
Basic
waveform
Additiona
pulse
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
127/256
128/256
129/256
130/256
PWDR
setting example
H'7F
H'80
H'81
H'82
112 pulses
128 pulses
128 pulses
128 pulses
15 pulses
0 pulses
1 pulse
2 pulses
Figure 8.3 Example of PWM Setting
8.4.2 Diagram of PWM Used as D/A Converter
Figure 8.4 shows the diagram example when using the PWM pulse as the D/A converter. Analog
signal with low ripple can be generated by connecting the low pass filter.
This LSI
Low pass filter Reference value
Resistor : 120 k
Capacitor : 0.1 µF
Figure 8.4 Example when PWM is Used as D/A Converter
Rev. 1.00, 05/04, page 156 of 544
8.5 Usage Notes
8.5.1 Module Stop Mode Setting
PWM operation can be enabled or disabled by the module stop control register. In the initial state,
PWM operation is disabled. Access to PWM registers is enabled when module stop mode is
cancelled. For details, see section 20, Power-Down Modes.
TIM8FR1A_010020020700 Rev. 1.00, 05/04, page 157 of 544
Section 9 16-Bit Free-Running Timer (FRT)
This LSI has an on-chip 16-bit free-running timer (FRT). The FRT operates on the basis of the 16-
bit free-running counter (FRC), and outputs two independent waveforms, and measures the input
pulse width and external clock periods.
9.1 Features
Selection of four clock sources
One of the three internal clocks (φ/2, φ/8, or φ/32), or an external clock input can be selected
(enabling use as an external event counter).
Two independent comparators
Two independent waveforms can be output.
Four independent input capture channels
The rising or falling edge can be selected.
Buffer modes can be specified.
Counter clearing
The free-running counters can be cleared on compare-match A.
Seven independent interrupts
Two compare-match interrupts, four input capture interrupts, and one overflow interrupt can be
requested independently.
Special functions provided by automatic addition function
The contents of OCRAR and OCRAF can be added to the contents of OCRA automatically,
enabling a periodic waveform to be generated without software intervention. The contents of
ICRD can be added automatically to the contents of OCRDM × 2, enabling input capture
operations in this interval to be restricted.
Rev. 1.00, 05/04, page 158 of 544
Figure 9.1 shows a block diagram of the FRT.
Clock selector Clock
Compare-match A
OCRA
Comparator A
Internal data bus
FRC
Comparator B
OCRB
ICRA
ICRB
ICRC
ICRD
TCSR
FTCI
FTOB
FTIA
External clock Internal clock
φ/2
φ/8
φ/32
FTIB
FTIC
FTID
FTOA
Compare-match B
Overflow
Clear
Input capture
TIER
TCR
TOCR
ICIA
ICIB
ICIC
ICID Interrupt signal
[Legend]
OCRA, OCRB
OCRAR,OCRAF
OCRDM
FRC
ICRA to ICRD
TCSR
TIER
TCR
TOCR
: Output compare register A, B (16-bit)
: Output compare register AR, AF (16-bit)
: Output compare register DM (16-bit)
: Free-running counter (16-bit)
: Input capture registers A to D (16-bit)
: Timer control/status register (8-bit)
: Timer interrupt enable register (8-bit)
: Timer control register (8-bit)
: Timer output compare control register (8-bit)
OCIA
OCIB
FOVI
OCRAR/F
OCRDM
Comparator M
Compare-match M × 1
× 2
Control logic
Module data bus
Bus interface
Figure 9.1 Block Diagram of 16-Bit Free-Running Timer
Rev. 1.00, 05/04, page 159 of 544
9.2 Input/Output Pins
Table 9.1 lists the FRT input and output pins.
Table 9.1 Pin Configuration
Name Abbreviation I/O Function
Counter clock input pin FTCI Input FRC counter clock input
Output compare A output pin FTOA Output Output compare A output
Output compare B output pin FTOB Output Output compare B output
Input capture A input pin FTIA Input Input capture A input
Input capture B input pin FTIB Input Input capture B input
Input capture C input pin FTIC Input Input capture C input
Input capture D input pin FTID Input Input capture D input
9.3 Register Descriptions
The FRT has the following registers.
Free-running counter (FRC)
Output compare register A (OCRA)
Output compare register B (OCRB)
Input capture register A (ICRA)
Input capture register B (ICRB)
Input capture register C (ICRC)
Input capture register D (ICRD)
Output compare register AR (OCRAR)
Output compare register AF (OCRAF)
Output compare register DM (OCRDM)
Timer interrupt enable register (TIER)
Timer control/status register (TCSR)
Timer control register (TCR)
Timer output compare control register (TOCR)
Note: OCRA and OCRB share the same address. Register selection is controlled by the OCRS
bit in TOCR. ICRA, ICRB, and ICRC share the same addresses with OCRAR, OCRAF,
and OCRDM. Register selection is controlled by the ICRS bit in TOCR.
Rev. 1.00, 05/04, page 160 of 544
9.3.1 Free-Running Counter (FRC)
FRC is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS1 and
CKS0 in TCR. FRC can be cleared by compare-match A. When FRC overflows from H'FFFF to
H'0000, the overflow flag bit (OVF) in TCSR is set to 1. FRC should always be accessed in 16-bit
units; cannot be accessed in 8-bit units. FRC is initialized to H'0000.
9.3.2 Output Compare Registers A and B (OCRA, OCRB)
The FRT has two output compare registers, OCRA and OCRB, each of which is a 16-bit
readable/writable register whose contents are continually compared with the value in FRC. When
a match is detected (compare-match), the corresponding output compare flag (OCFA or OCFB) is
set to 1 in TCSR. If the OEA or OEB bit in TOCR is set to 1, when the OCR and FRC values
match, the output level selected by the OLVLA or OLVLB bit in TOCR is output at the output
compare output pin (FTOA or FTOB). Following a reset, the FTOA and FTOB output levels are 0
until the first compare-match. OCR should always be accessed in 16-bit units; cannot be accessed
in 8-bit units. OCR is initialized to H'FFFF.
9.3.3 Input Capture Registers A to D (ICRA to ICRD)
The FRT has four input capture registers, ICRA to ICRD, each of which is a 16-bit read-only
register. When the rising or falling edge of the signal at an input capture input pin (FTIA to FTID)
is detected, the current FRC value is transferred to the corresponding input capture register (ICRA
to ICRD). At the same time, the corresponding input capture flag (ICFA to ICFD) in TCSR is set
to 1. The FRC contents are transferred to ICR regardless of the value of ICF. The input capture
edge is selected by the input edge select bits (IEDGA to IEDGD) in TCR.
ICRC and ICRD can be used as ICRA and ICRB buffer registers, respectively, by means of buffer
enable bits A and B (BUFEA and BUFEB) in TCR. For example, if an input capture occurs when
ICRC is specified as the ICRA buffer register, the FRC contents are transferred to ICRA, and then
transferred to the buffer register ICRC.
To ensure input capture, the input capture pulse width should be at least 1.5 system clocks (φ) for
a single edge. When triggering is enabled on both edges, the input capture pulse width should be at
least 2.5 system clocks (φ).
ICRA to ICRD should always be accessed in 16-bit units; cannot be accessed in 8-bit units. ICR is
initialized to H'0000.
Rev. 1.00, 05/04, page 161 of 544
9.3.4 Output Compare Registers AR and AF (OCRAR, OCRAF)
OCRAR and OCRAF are 16-bit readable/writable registers. When the OCRAMS bit in TOCR is
set to 1, the operation of OCRA is changed to include the use of OCRAR and OCRAF. The
contents of OCRAR and OCRAF are automatically added alternately to OCRA, and the result is
written to OCRA. The write operation is performed on the occurrence of compare-match A. In the
1st compare-match A after setting the OCRAMS bit to 1, OCRAF is added. The operation due to
compare-match A varies according to whether the compare-match follows addition of OCRAR or
OCRAF. The value of the OLVLA bit in TOCR is ignored, and 1 is output on a compare-match A
following addition of OCRAF, while 0 is output on a compare-match A following addition of
OCRAR.
When using the OCRA automatic addition function, do not select internal clock φ/2 as the FRC
input clock together with a set value of H'0001 or less for OCRAR (or OCRAF).
OCRAR and OCRAF should always be accessed in 16-bit units; cannot be accessed in 8-bit units.
OCRAR and OCRAF are initialized to H'FFFF.
9.3.5 Output Compare Register DM (OCRDM)
OCRDM is a 16-bit readable/writable register in which the upper 8 bits are fixed at H'00. When
the ICRDMS bit in TOCR is set to 1 and the contents of OCRDM are other than H'0000, the
operation of ICRD is changed to include the use of OCRDM. The point at which input capture D
occurs is taken as the start of a mask interval. Next, twice the contents of OCRDM is added to the
contents of ICRD, and the result is compared with the FRC value. The point at which the values
match is taken as the end of the mask interval. New input capture D events are disabled during the
mask interval. A mask interval is not generated when the contents of OCRDM are H'0000 while
the ICRDMS bit is set to 1.
OCRDM should always be accessed in 16-bit units; cannot be accessed in 8-bit units. OCRDM is
initialized to H'0000.
Rev. 1.00, 05/04, page 162 of 544
9.3.6 Timer Interrupt Enable Register (TIER)
TIER enables and disables interrupt requests.
Bit Bit Name
Initial
Value R/W Description
7 ICIAE 0 R/W Input Capture Interrupt A Enable
Selects whether to enable input capture interrupt A
request (ICIA) when input capture flag A (ICFA) in
TCSR is set to 1.
0: ICIA requested by ICFA is disabled
1: ICIA requested by ICFA is enabled
6 ICIBE 0 R/W Input Capture Interrupt B Enable
Selects whether to enable input capture interrupt B
request (ICIB) when input capture flag B (ICFB) in
TCSR is set to 1.
0: ICIB requested by ICFB is disabled
1: ICIB requested by ICFB is enabled
5 ICICE 0 R/W Input Capture Interrupt C Enable
Selects whether to enable input capture interrupt C
request (ICIC) when input capture flag C (ICFC) in
TCSR is set to 1.
0: ICIC requested by ICFC is disabled
1: ICIC requested by ICFC is enabled
4 ICIDE 0 R/W Input Capture Interrupt D Enable
Selects whether to enable input capture interrupt D
request (ICID) when input capture flag D (ICFD) in
TCSR is set to 1.
0: ICID requested by ICFD is disabled
1: ICID requested by ICFD is enabled
3 OCIAE 0 R/W Output Compare Interrupt A Enable
Selects whether to enable output compare interrupt A
request (OCIA) when output compare flag A (OCFA) in
TCSR is set to 1.
0: OCIA requested by OCFA is disabled
1: OCIA requested by OCFA is enabled
Rev. 1.00, 05/04, page 163 of 544
Bit Bit Name
Initial
Value R/W Description
2 OCIBE 0 R/W Output Compare Interrupt B Enable
Selects whether to enable output compare interrupt B
request (OCIB) when output compare flag B (OCFB) in
TCSR is set to 1.
0: OCIB requested by OCFB is disabled
1: OCIB requested by OCFB is enabled
1 OVIE 0 R/W Timer Overflow Interrupt Enable
Selects whether to enable a free-running timer overflow
request interrupt (FOVI) when the timer overflow flag
(OVF) in TCSR is set to 1.
0: FOVI requested by OVF is disabled
1: FOVI requested by OVF is enabled
0 — 0 R Reserved
This bit is always read as 1 and cannot be modified.
9.3.7 Timer Control/Status Register (TCSR)
TCSR is used for counter clear selection and control of interrupt request signals.
Bit Bit Name
Initial
Value R/W Description
7 ICFA 0 R/(W)* Input Capture Flag A
This status flag indicates that the FRC value has been
transferred to ICRA by means of an input capture
signal. When BUFEA = 1, ICFA indicates that the old
ICRA value has been moved into ICRC and the new
FRC value has been transferred to ICRA. Only 0 can be
written to this bit to clear the flag.
[Setting condition]
When an input capture signal causes the FRC value to
be transferred to ICRA
[Clearing condition]
Read ICFA when ICFA = 1, then write 0 to ICFA
Rev. 1.00, 05/04, page 164 of 544
Bit Bit Name
Initial
Value R/W Description
6 ICFB 0 R/(W)* Input Capture Flag B
This status flag indicates that the FRC value has been
transferred to ICRB by means of an input capture
signal. When BUFEB = 1, ICFB indicates that the old
ICRB value has been moved into ICRD and the new
FRC value has been transferred to ICRB. Only 0 can
be written to this bit to clear the flag.
[Setting condition]
When an input capture signal causes the FRC value to
be transferred to ICRB
[Clearing condition]
Read ICFB when ICFB = 1, then write 0 to ICFB
5 ICFC 0 R/(W)* Input Capture Flag C
This status flag indicates that the FRC value has been
transferred to ICRC by means of an input capture
signal. When BUFEA = 1, on occurrence of an input
capture signal specified by the IEDGC bit at the FTIC
input pin, ICFC is set but data is not transferred to
ICRC. In buffer operation, ICFC can be used as an
external interrupt signal by setting the ICICE bit to 1.
Only 0 can be written to this bit to clear the flag.
[Setting condition]
When an input capture signal is received
[Clearing condition]
Read ICFC when ICFC = 1, then write 0 to ICFC
4 ICFD 0 R/(W)* Input Capture Flag D
This status flag indicates that the FRC value has been
transferred to ICRD by means of an input capture
signal. When BUFEB = 1, on occurrence of an input
capture signal specified by the IEDGD bit at the FTID
input pin, ICFD is set but data is not transferred to
ICRD. In buffer operation, ICFD can be used as an
external interrupt signal by setting the ICIDE bit to 1.
Only 0 can be written to this bit to clear the flag.
[Setting condition]
When an input capture signal is received
[Clearing condition]
Read ICFD when ICFD = 1, then write 0 to ICFD
Rev. 1.00, 05/04, page 165 of 544
Bit Bit Name
Initial
Value R/W Description
3 OCFA 0 R/(W)* Output Compare Flag A
This status flag indicates that the FRC value matches
the OCRA value. Only 0 can be written to this bit to
clear the flag.
[Setting condition]
When FRC = OCRA
[Clearing condition]
Read OCFA when OCFA = 1, then write 0 to OCFA
2 OCFB 0 R/(W)* Output Compare Flag B
This status flag indicates that the FRC value matches
the OCRB value. Only 0 can be written to this bit to
clear the flag.
[Setting condition]
When FRC = OCRB
[Clearing condition]
Read OCFB when OCFB = 1, then write 0 to OCFB
1 OVF 0 R/(W)* Timer Overflow
This status flag indicates that the FRC has overflowed.
Only 0 can be written to this bit to clear the flag.
[Setting condition]
When FRC overflows (changes from H'FFFF to
H'0000)
[Clearing condition]
Read OVF when OVF = 1, then write 0 to OVF
0 CCLRA 0 R/W Counter Clear A
This bit selects whether the FRC is to be cleared at
compare-match A (when the FRC and OCRA values
match).
0: FRC clearing is disabled
1: FRC is cleared at compare-match A
Note: * Only 0 can be written to clear the flag.
Rev. 1.00, 05/04, page 166 of 544
9.3.8 Timer Control Register (TCR)
TCR selects the rising or falling edge of the input capture signals, enables the input capture buffer
mode, and selects the FRC clock source.
Bit Bit Name
Initial
Value R/W Description
7 IEDGA 0 R/W Input Edge Select A
Selects the rising or falling edge of the input capture A
signal (FTIA).
0: Capture on the falling edge of FTIA
1: Capture on the rising edge of FTIA
6 IEDGB 0 R/W Input Edge Select B
Selects the rising or falling edge of the input capture B
signal (FTIB).
0: Capture on the falling edge of FTIB
1: Capture on the rising edge of FTIB
5 IEDGC 0 R/W Input Edge Select C
Selects the rising or falling edge of the input capture C
signal (FTIC).
0: Capture on the falling edge of FTIC
1: Capture on the rising edge of FTIC
4 IEDGD 0 R/W Input Edge Select D
Selects the rising or falling edge of the input capture D
signal (FTID).
0: Capture on the falling edge of FTID
1: Capture on the rising edge of FTID
3 BUFEA 0 R/W Buffer Enable A
Selects whether ICRC is to be used as a buffer register
for ICRA.
0: ICRC is not used as a buffer register for ICRA
1: ICRC is used as a buffer register for ICRA
2 BUFEB 0 R/W Buffer Enable B
Selects whether ICRD is to be used as a buffer register
for ICRB.
0: ICRD is not used as a buffer register for ICRB
1: ICRD is used as a buffer register for ICRB
Rev. 1.00, 05/04, page 167 of 544
Bit Bit Name
Initial
Value R/W Description
1
0
CKS1
CKS0
0
0
R/W Clock Select 1, 0
Select clock source for FRC.
00: φ/2 internal clock source
01: φ/8 internal clock source
10: φ/32 internal clock source
11: External clock source (counting at FTCI rising edge)
9.3.9 Timer Output Compare Control Register (TOCR)
TOCR enables output from the output compare pins, selects the output levels, switches access
between output compare registers A and B, controls the ICRD and OCRA operating modes, and
switches access to input capture registers A, B, and C.
Bit Bit Name
Initial
Value R/W Description
7 ICRDMS 0 R/W Input Capture D Mode Select
Specifies whether ICRD is used in the normal operating
mode or in the operating mode using OCRDM.
0: The normal operating mode is specified for ICRD
1: The operating mode using OCRDM is specified for
ICRD
6 OCRAMS 0 R/W Output Compare A Mode Select
Specifies whether OCRA is used in the normal
operating mode or in the operating mode using OCRAR
and OCRAF.
0: The normal operating mode is specified for OCRA
1: The operating mode using OCRAR and OCRAF is
specified for OCRA
5 ICRS 0 R/W Input Capture Register Select
The same addresses are shared by ICRA and OCRAR,
by ICRB and OCRAF, and by ICRC and OCRDM. The
ICRS bit determines which registers are selected when
the shared addresses are read from or written to. The
operation of ICRA, ICRB, and ICRC is not affected.
0: ICRA, ICRB, and ICRC are selected
1: OCRAR, OCRAF, and OCRDM are selected
Rev. 1.00, 05/04, page 168 of 544
Bit Bit Name
Initial
Value R/W Description
4 OCRS 0 R/W Output Compare Register Select
OCRA and OCRB share the same address. When this
address is accessed, the OCRS bit selects which
register is accessed. The operation of OCRA or OCRB
is not affected.
0: OCRA is selected
1: OCRB is selected
3 OEA 0 R/W Output Enable A
Enables or disables output of the output compare A
output pin (FTOA).
0: Output compare A output is disabled
1: Output compare A output is enabled
2 OEB 0 R/W Output Enable B
Enables or disables output of the output compare B
output pin (FTOB).
0: Output compare B output is disabled
1: Output compare B output is enabled
1 OLVLA 0 R/W Output Level A
Selects the level to be output at the output compare A
output pin (FTOA) in response to compare-match A
(signal indicating a match between the FRC and OCRA
values). When the OCRAMS bit is 1, this bit is ignored.
0: 0 is output at compare-match A
1: 1 is output at compare-match A
0 OLVLB 0 R/W Output Level B
Selects the level to be output at the output compare B
output pin (FTOB) in response to compare-match B
(signal indicating a match between the FRC and OCRB
values).
0: 0 is output at compare-match B
1: 1 is output at compare-match B
Rev. 1.00, 05/04, page 169 of 544
9.4 Operation
9.4.1 Pulse Output
Figure 9.2 shows an example of 50%-duty pulses output with an arbitrary phase difference. When
a compare match occurs while the CCLRA bit in TCSR is set to 1, the OLVLA and OLVLB bits
are inverted by software.
H'FFFF
OCRA
OCRB
H'0000
FTOA
FTOB
Counter clear
FRC
Figure 9.2 Example of Pulse Output
Rev. 1.00, 05/04, page 170 of 544
9.5 Operation Timing
9.5.1 FRC Increment Timing
Figure 9.3 shows the FRC increment timing with an internal clock source. Figure 9.4 shows the
increment timing with an external clock source. The pulse width of the external clock signal must
be at least 1.5 system clocks (φ). The counter will not increment correctly if the pulse width is
shorter than 1.5 system clocks (φ).
φ
Internal clock
FRC input
clock
FRC N – 1 N + 1N
Figure 9.3 Increment Timing with Internal Clock Source
φ
External clock
input pin
FRC input
clock
FRC N + 1N
Figure 9.4 Increment Timing with External Clock Source
Rev. 1.00, 05/04, page 171 of 544
9.5.2 Output Compare Output Timing
A compare-match signal occurs at the last state when the FRC and OCR values match (at the
timing when the FRC updates the counter value). When a compare-match signal occurs, the level
selected by the OLVL bit in TOCR is output at the output compare pin (FTOA or FTOB). Figure
9.5 shows the timing of this operation for compare-match A.
φ
FRC
OCRA
NNN + 1 N + 1
NN
Compare-match
A signal
OLVLA
Output compare A
output pin FTOA
Clear*
Note: * Indicates instruction execution by software.
Figure 9.5 Timing of Output Compare A Output
9.5.3 FRC Clear Timing
FRC can be cleared when compare-match A occurs. Figure 9.6 shows the timing of this operation.
φ
FRC N H'0000
Compare-match
A signal
Figure 9.6 Clearing of FRC by Compare-Match A Signal
Rev. 1.00, 05/04, page 172 of 544
9.5.4 Input Capture Input Timing
The rising or falling edge can be selected for the input capture input timing by the IEDGA to
IEDGD bits in TCR. Figure 9.7 shows the usual input capture timing when the rising edge is
selected.
φ
Input capture
input pin
Input capture signal
Figure 9.7 Input Capture Input Signal Timing (Usual Case)
If ICRA to ICRAD are read when the corresponding input capture signal arrives, the internal input
capture signal is delayed by one system clock (φ). Figure 9.8 shows the timing for this case.
T1T2
Read cycle of ICRA to ICRD
φ
Input capture
input pin
Input capture signal
Figure 9.8 Input Capture Input Signal Timing (When ICRA to ICRD are Read)
Rev. 1.00, 05/04, page 173 of 544
9.5.5 Buffered Input Capture Input Timing
ICRC and ICRD can operate as buffers for ICRA and ICRB, respectively. Figure 9.9 shows how
input capture operates when ICRC is used as ICRA's buffer register (BUFEA = 1) and IEDGA and
IEDGC are set to different values (IEDGA = 0 and IEDGC = 1, or IEDGA = 1 and IEDGC = 0),
so that input capture is performed on both the rising and falling edges of FTIA.
Input capture
signal
φ
FTIA
FRC
ICRA
ICRC
n n + 1 N + 1N
Mn
mM
n
M
N
n
Figure 9.9 Buffered Input Capture Timing
Even when ICRC or ICRD is used as a buffer register, its input capture flag is set by the selected
transition of its input capture signal. For example, if ICRC is used to buffer ICRA, when the edge
transition selected by the IEDGC bit occurs on the FTIC input capture line, ICFC will be set, and
if the ICICE bit is set at this time, an interrupt will be requested. The FRC value will not be
transferred to ICRC, however. In buffered input capture, if either set of two registers to which data
will be transferred (ICRA and ICRC, or ICRB and ICRD) is being read when the input capture
input signal arrives, input capture is delayed by one system clock (φ). Figure 9.10 shows the
timing when BUFEA = 1.
Input capture
signal
FTIA
φ
T
1
T
2
CPU read cycle of ICRA or ICRC
Figure 9.10 Buffered Input Capture Timing (BUFEA = 1)
Rev. 1.00, 05/04, page 174 of 544
9.5.6 Timing of Input Capture Flag (ICF) Setting
The input capture flag, ICFA, ICFB, ICFC, or ICFD, is set to 1 by the input capture signal. The
FRC value is simultaneously transferred to the corresponding input capture register (ICRA, ICRB,
ICRC, or ICRD). Figure 9.11 shows the timing of setting the ICFA to ICFD flag.
Input capture
signal
φ
ICFA to ICFD
ICRA to ICRD
FRC
N
N
Figure 9.11 Timing of Input Capture Flag (ICFA, ICFB, ICFC, or ICFD) Setting
9.5.7 Timing of Output Compare Flag (OCF) setting
The output compare flag, OCFA or OCFB, is set to 1 by a compare-match signal generated when
the FRC value matches the OCRA or OCRB value. This compare-match signal is generated at the
last state in which the two values match, just before FRC increments to a new value. When the
FRC and OCRA or OCRB value match, the compare-match signal is not generated until the next
cycle of the clock source. Figure 9.12 shows the timing of setting the OCFA or OCFB flag.
Compare-match
signal
OCFA, OCFB
OCRA, OCRB N
FRC N N + 1
φ
Figure 9.12 Timing of Output Compare Flag (OCFA or OCFB) Setting
Rev. 1.00, 05/04, page 175 of 544
9.5.8 Timing of FRC Overflow Flag Setting
The FRC overflow flag (OVF) is set to 1 when FRC overflows (changes from H'FFFF to H'0000).
Figure 9.13 shows the timing of setting the OVF flag.
Overflow signal
FRC H'FFFF H'0000
OVF
φ
Figure 9.13 Timing of Overflow Flag (OVF) Setting
9.5.9 Automatic Addition Timing
When the OCRAMS bit in TOCR is set to 1, the contents of OCRAR and OCRAF are
automatically added to OCRA alternately, and when an OCRA compare-match occurs a write to
OCRA is performed. Figure 9.14 shows the OCRA write timing.
Compare-match
signal
OCRAR, OCRAF A
OCRA N N + A
FRC N N +1
φ
Figure 9.14 OCRA Automatic Addition Timing
Rev. 1.00, 05/04, page 176 of 544
9.5.10 Mask Signal Generation Timing
When the ICRDMS bit in TOCR is set to 1 and the contents of OCRDM are other than H'0000, a
signal that masks the ICRD input capture signal is generated. The mask signal is set by the input
capture signal. The mask signal is cleared by the sum of the ICRD contents and twice the
OCRDM contents, and an FRC compare-match. Figure 9.15 shows the timing of setting the mask
signal. Figure 9.16 shows the timing of clearing the mask signal.
Input capture
signal
Input capture
mask signal
φ
Figure 9.15 Timing of Input Capture Mask Signal Setting
Compare-match
signal
Input capture
mask signal
ICRD + OCRDM × 2 N
FRC N N + 1
φ
Figure 9.16 Timing of Input Capture Mask Signal Clearing
Rev. 1.00, 05/04, page 177 of 544
9.6 Interrupt Sources
The free-running timer can request seven interrupts: ICIA to ICID, OCIA, OCIB, and FOVI. Each
interrupt can be enabled or disabled by an enable bit in TIER. Independent signals are sent to the
interrupt controller for each interrupt. Table 9.2 lists the sources and priorities of these interrupts.
Table 9.2 FRT Interrupt Sources
Interrupt Interrupt Source Interrupt Flag Priority
ICIA Input capture of ICRA ICFA High
ICIB Input capture of ICRB ICFB
ICIC Input capture of ICRC ICFC
ICID Input capture of ICRD ICFD
OCIA Compare match of OCRA OCFA
OCIB Compare match of OCRB OCFB
FOVI Overflow of FRC OVF Low
9.7 Usage Notes
9.7.1 Conflict between FRC Write and Clear
If an internal counter clear signal is generated during the state after an FRC write cycle, the clear
signal takes priority and the write is not performed. Figure 9.17 shows the timing for this type of
conflict.
φ
Address FRC address
Internal write
signal
Counter clear
signal
FRC N H'0000
T1T2
Write cycle of FRC
Figure 9.17 FRC Write-Clear Conflict
Rev. 1.00, 05/04, page 178 of 544
9.7.2 Conflict between FRC Write and Increment
If an FRC increment pulse is generated during the state after an FRC write cycle, the write takes
priority and FRC is not incremented. Figure 9.18 shows the timing for this type of conflict.
φ
Address FRC address
Internal write
signal
FRC input
clock
Write data
FRC N M
T
1
T
2
Write cycle of FRC
Figure 9.18 FRC Write-Increment Conflict
9.7.3 Conflict between OCR Write and Compare-Match
If a compare-match occurs during the state after an OCRA or OCRB write cycle, the write takes
priority and the compare-match signal is disabled. Figure 9.19 shows the timing for this type of
conflict.
If automatic addition of OCRAR and OCRAF to OCRA is selected, and a compare-match occurs
in the cycle following the OCRA, OCRAR, and OCRAF write cycle, the OCRA, OCRAR and
OCRAF write takes priority and the compare-match signal is disabled. Consequently, the result of
the automatic addition is not written to OCRA. Figure 9.20 shows the timing for this type of
conflict.
Rev. 1.00, 05/04, page 179 of 544
φ
Address OCR address
Internal write
signal
Compare-match
signal
FRC
Write data
Disabled
OCR N M
NN + 1
T
1
T
2
Write cycle of OCR
Figure 9.19 Conflict between OCR Write and Compare-Match
(When Automatic Addition Function is Not Used)
φ
Address OCRAR (OCRAF)
address
Internal write signal
Compare-match signal
FRC
Automatic addition is not performed
because compare-match signals are disabled.
Disabled
OCR N
N N+1
OCRAR (OCRAF) Old data New data
Figure 9.20 Conflict between OCRAR/OCRAF Write and Compare-Match
(When Automatic Addition Function is Used)
Rev. 1.00, 05/04, page 180 of 544
9.7.4 Switching of Internal Clock and FRC Operation
When the internal clock is changed, the changeover may cause FRC to increment. This depends on
the time at which the clock is switched (bits CKS1 and CKS0 are rewritten), as shown in table 9.3.
When an internal clock is used, the FRC clock is generated on detection of the falling edge of the
internal clock scaled from the system clock (φ). If the clock is changed when the old source is high
and the new source is low, as in case no. 3 in table 9.3, the changeover is regarded as a falling
edge that triggers the FRC clock, and FRC is incremented. Switching between an internal clock
and external clock can also cause FRC to increment.
Table 9.3 Switching of Internal Clock and FRC Operation
No.
Timing of Switchover
by Means of CKS1
and CKS0 Bits FRC Operation
1 Switching from
low to low
Clock before
switchover
Clock after
switchover
FRC clock
FRC
CKS bit rewrite
NN + 1
2 Switching from
low to high
Clock before
switchover
Clock after
switchover
FRC clock
FRC N N + 1 N + 2
CKS bit rewrite
Rev. 1.00, 05/04, page 181 of 544
No.
Timing of Switchover
by Means of CKS1
and CKS0 Bits FRC Operation
3 Switching from
high to low
Clock before
switchover
Clock after
switchover
FRC clock
FRC
CKS bit rewrite
N N + 2
N + 1
*
4 Switching from
high to high
Clock before
switchover
Clock after
switchover
FRC clock
FRC N N + 1
CKS bit rewrite
N + 2
Note: * Generated on the assumption that the switchover is a falling edge; FRC is incremented.
9.7.5 Module Stop Mode Setting
FRT operation can be enabled or disabled using the module stop control register. The initial
setting is for FRT operation to be halted. Register access is enabled by canceling the module stop
mode. For details, refer to section 20, Power-Down Modes.
Rev. 1.00, 05/04, page 182 of 544
TIMH265B_000020040200 Rev. 1.00, 05/04, page 183 of 544
Section 10 8-Bit Timer (TMR)
This LSI has an on-chip 8-bit timer module (TMR_0, TMR_1, TMR_Y, TMR_X, TMR_B, and
TMR_A) with six channels operating on the basis of an 8-bit counter. The 8-bit timer module can
be used as a multifunction timer in a variety of applications, such as generation of counter reset,
interrupt requests, and pulse output with an arbitrary duty cycle using a compare-match signal
with two registers.
10.1 Features
Select of clock sources
The counter input clock can be six internal clocks*1 and an external clock
Select of three ways to clear the counters
The counters can be cleared on compare-match A or compare-match B, or by an external reset
signal
Timer output controlled by two compare-match signals
The timer output signal in each channel is controlled by two independent compare-match
signals, enabling the timer to be used for various applications, such as the generation of
pulse output or PWM output with an arbitrary duty cycle
Cascading of two channels
Cascading of TMR_0 and TMR_1,TMR_Y and TMR_X*2 or TMR_B and TMR_A
Operation as a 16-bit timer can be performed using TMR_0/TMR_Y/TMR_B as the upper
half and TMR_1/TMR_X/TMR_A as the lower half (16-bit count mode)
TMR_1/TMR_X/TMR_A can be used to count TMR_0/TMR_Y/TMR_B compare-match
occurrences (compare-match count mode)
Multiple interrupt sources for each cannels
Compare-match A: TMR_0, TMR_1, TMR_Y, TMR_B and TMR_A
Compare-match B: TMR_0, TMR_1, TMR_Y, TMR_B and TMR_A
Overflow: TMR_0, TMR_1, TMR_Y, TMR_B and TMR_A
Input capture: TMR_X and TMR_A
Input capture function (TMR_X and TMR_A)
Notes: 1. The program development tool (emulator) supports three internal clocks.
2. The program development tool (emulator) does not support this function.
Rev. 1.00, 05/04, page 184 of 544
Table 10.1 TMR Function
Item TMR_0 TMR_1 TMR_Y TMR_X TMR_B TMR_A
Count clock φ/2
φ/8
φ/32
φ/64
φ/256
φ/1024
φ/2
φ/8
φ/64
φ/128
φ/1024
φ/2048
φ/4
φ/256
φ/2048
φ/4096*
φ/8192*
φ/16384*
φ
φ/2
φ/4
φ/2048*
φ/4096*
φ/8192*
φ/4
φ/256
φ/2048
φ/4096
φ/8192
φ/16384
φ
φ/2
φ/4
φ/2048
φ/4096
φ/8192
I/O pins TMO0
TMCI0
TMRI0
TMO1
TMCI1
TMRI1
TMOY
TMIY/ExTMIY
(TMCIY/TMRIY)
TMOX/ExTMOX
TMIX/ExTMIX
(TMCIX/TMRIX)
TMOB
TMIB(TMCIB/
TMRIB)
TMOA
TMIA(TMCIA/
TMRIA)
Counter clear function Compare-match A
Compare-match B
External reset
Compare-match A
Compare-match B
External reset
Compare-match A
Compare-match B
External reset
Compare-match A
Compare-match B
External reset
Compare-match A
Compare-match B
External reset
Compare-match A
Compare-match B
External reset
Pulse output O O O O O O
Compare-match
output
0 output O O O O O O
1 output O O O O O O
Toggle
output
O O O O O O
Cascaded connection
16-bit count mode
O
O
O*
O*
O
O
Compare-match count mode O O* O
Input capture function O O
TCORA
compare-match
TCORA
compare-match
TCORA
compare-match
TCORA
compare-match
TCORA
compare-match
TCORB
compare-match
TCORB
compare-match
TCORB
compare-match
TCORB
compare-match
TCORB
compare-match
TCNT overflow TCNT overflow TCNT overflow TCNT overflow TCNT overflow
Interrupt source
Input capture Input capture
[Legend]
O: Enable
: Disable
Note: * The program development tool (emulator) does not support this function.
Rev. 1.00, 05/04, page 185 of 544
Figures 10.1 to 10.3 show block diagrams of 8-bit timers.
External clock
sources
Internal clock
sources
TMR_0
φ/2, φ/8, φ/32, φ/64, φ/256, φ/1024
Clock 1
Clock 0
Compare-match A1
Compare-match A0
Clear 1
Interrupt signals
CMIA0
CMIB0
OVI0
CMIA1
CMIB1
OVI1
TMO0
TMRI0
Internal bus
TCORA_0
Comparator A_0
Comparator B_0
TCORB_0
TCSR_0
TCR_0
TMCI0
TMCI1
TCNT_0
Overflow 1
Overflow 0
Compare-match B1
Compare-match B0
TMO1
TMRI1
Clock select
Control logic
Clear 0
TMR_1
φ/2, φ/8, φ/64, φ/128, φ/1024, φ/2048
[Legend]
TCORA_0:
TCORB_0:
TCNT_0:
TCSR_0:
TCR_0:
Time constant register A_0
Time constant register B_0
Timer counter_0
Timer control/status register_0
Timer control register_0
TCORA_1:
TCORB_1:
TCNT_1:
TCSR_1:
TCR_1:
Time constant register A_1
Time constant register B_1
Timer counter_1
Timer control/status register_1
Timer control register_1
TCORA_1
Comparator A_1
TCNT_1
Comparator B_1
TCORB_1
TCSR_1
TCR_1
Figure 10.1 Block Diagram of 8-Bit Timer (TMR_0 and TMR_1)
Rev. 1.00, 05/04, page 186 of 544
External clock
sources
Internal clock
sources
TMR_X
φ, φ/2, φ/4, φ/2048*, φ/4096*, φ/8192*
Clock X
Clock Y
Compare-match AX
Compare-match AY
Clear X
CMIAY
CMIBY
OVIY
ICIX
TMOY*
ExTMRIY*/TMRIY
TCORA_Y
Comparator A_Y
Comparator B_Y
TCORB_Y
TCSR_Y
TCR_Y
TCORA_X
Comparator A_X
TCNT_X
Comparator B_X
Comparator C
TCORB_X
TCORC
TICRR
TICRF
TICR
TCSR_X
TCR_X
ExTMCIY*/TMCIY
ExTMCIX*/TMCIX
TISR
TCNT_Y
Overflow X
Overflow Y
Compare- match BX
Compare-match BY
Compare-match C
Input capture
Clock
select
Internal bus
Control
logic
[Legend]
TCORA_X: Time constant register A_X
TCORB_X: Time constant register B_X
TCNT_X: Timer counter_X
TCSR_X: Timer control/status register_X
TCR_X: Timer control register_X
TICR: Input capture register
TCORC: Time constant register C
TICRR: Input capture register R
TICRF: Input capture register F
TCORA_Y: Time constant register A_Y
TCORB_Y: Time constant register B_Y
TCNT_Y: Timer counter_Y
TCSR_Y: Timer control/status register_Y
TCR_Y: Timer control register_Y
TISR: Timer input select register
Clear Y
TMR_Y
φ/4, φ/256, φ/2048, φ/4096*, φ/8192*, φ/16384*
Interrupt signals
+
ExTMOX*/TMOX
ExTMRIX*/TMRIX
**
Note: The program development tool (emulator) does not support this function.
Figure 10.2 Block Diagram of 8-Bit Timer (TMR_Y and TMR_X)
Rev. 1.00, 05/04, page 187 of 544
External clock
sources
Internal clock
sources
TMR_A
φ, φ/2, φ/4, φ/2048, φ/4096, φ/8192
Clock A
Clock B
Compare-match AA
Compare-match AB
Clear A
CMIAAB
CMIBAB
OVIAB
ICIA
TMOB
TMRIB
TCORA_B
Comparator A_B
Comparator B_B
TCORB_B
TCSR_B
TCR_B
TCORA_A
Comparator A_A
TCNT_A
Comparator B_A
TCORB_A
TICRR_A
TICRF_A
TICR_A
TCSR_A
TCR_A
TMCIB
TMCIA
TISR_A
TCNT_B
Overflow A
Overflow B
Compare- match BA
Compare-match BB
Input capture
Clock
select
Internal bus
Control
logic
[Legend]
TCORA_A: Time constant register A_A
TCORB_A: Time constant register B_A
TCNT_A: Timer counter_A
TCSR_A: Timer control/status register_A
TCR_A: Timer control register_A
TICR_A: Input capture register_A
TICRR_A: Input capture register R_A
TICRF_A: Input capture register F_A
TCORA_B: Time constant register A_B
TCORB_B: Time constant register B_B
TCNT_B: Timer counter_B
TCSR_B: Timer control/status register_B
TCR_B: Timer control register_B
TISR_B: Timer input select register_B
Clear B
TMR_B
φ/4, φ/256, φ/2048, φ/4096, φ/8192, φ/16384
Interrupt signals
TMOA
TMRIA
Figure 10.3 Block Diagram of 8-Bit Timer (TMR_B and TMR_A)
Rev. 1.00, 05/04, page 188 of 544
10.2 Input/Output Pins
Table 10.2 summarizes the input and output pins of the TMR.
Table 10.2 Pin Configuration
Channel Name Symbol I/O Function
Timer output TMO0 Output Output controlled by compare-match
Timer clock input TMCI0 Input External clock input for the counter
TMR_0
Timer reset input TMRI0 Input External reset input for the counter
Timer output TMO1 Output Output controlled by compare-match
Timer clock input TMCI1 Input External clock input for the counter
TMR_1
Timer reset input TMRI1 Input External reset input for the counter
Timer clock/
reset input
TMIY/ExTMIY*
(TMCIY/TMRIY)
Input External clock input/
external reset input for the counter
TMR_Y
Timer output TMOY* Output Output controlled by compare-match
Timer output TMOX/
ExTMOX*
Output Output controlled by compare-match TMR_X
Timer clock/
reset input
TMIX/ExTMIX*
(TMCIX/TMRIX)
Input External clock input/
external reset input for the counter
Timer clock/
reset input
TMIB
(TMCIB/TMRIB)
Input External clock input/
external reset input for the counter
TMR_B
Timer output TMOB Output Output controlled by compare-match
Timer output TMOA Output Output controlled by compare-match TMR_A
Timer clock/
reset input
TMIA
(TMCIA/TMRIA)
Input External clock input/
external reset input for the counter
Note: * The program development tool (emulator) does not support this pin.
Rev. 1.00, 05/04, page 189 of 544
10.3 Register Descriptions
The TMR has the following registers. For details on the serial timer control register, see section
3.2.3, Serial Timer Control Register (STCR).
TMR_0
Timer counter_0 (TCNT_0)
Time constant register A_0 (TCORA_0)
Time constant register B_0 (TCORB_0)
Timer control register_0 (TCR_0)
Timer control/status register_0 (TCSR_0)
TMR_1
Timer counter_1 (TCNT_1)
Time constant register A_1 (TCORA_1)
Time constant register B_1 (TCORB_1)
Timer control register_1 (TCR_1)
Timer control/status register_1 (TCSR_1)
TMR_Y
Timer counter_Y (TCNT_Y)
Time constant register A_Y (TCORA_Y)
Time constant register B_Y (TCORB_Y)
Timer control register_Y (TCR_Y)
Timer control/status register_Y (TCSR_Y)
Timer input select register (TISR)
Timer connection register S (TCONRS)
TMR_X
Timer counter_X (TCNT_X)
Time constant register A_X (TCORA_X)
Time constant register B_X (TCORB_X)
Timer control register_X (TCR_X)
Timer control/status register_X (TCSR_X)
Input capture register (TICR)
Time constant register (TCORC)
Input capture register R (TICRR)
Input capture register F (TICRF)
Timer connection register I (TCONRI)
Rev. 1.00, 05/04, page 190 of 544
For both TMR_Y and TMR_X
Timer XY control register (TCRXY)
TMR_B
Timer counter_B (TCNT_B)
Time constant register A_B (TCORA_B)
Time constant register B_B (TCORB_B)
Timer control register_B (TCR_B)
Timer control/status register_B (TCSR_B)
Timer input select register_B (TISR_B)
TMR_A
Timer counter_A (TCNT_A)
Time constant register A_A (TCORA_A)
Time constant register B_A (TCORB_A)
Timer control register_A (TCR_A)
Timer control/status register_A (TCSR_A)
Input capture register_A (TICR_A)
Input capture register R_A (TICRR_A)
Input capture register F_A (TICRF_A)
For both TMR_B and TMR_A
Timer AB control register (TCRAB)
Note: 1. Some of the registers of TMR_X and TMR_Y use the same address. The registers can
be switched by the TMRX/Y bit in TCONRS.
2. The TCRXY is not supported by the program development tool (emulator).
Rev. 1.00, 05/04, page 191 of 544
10.3.1 Timer Counter (TCNT)
Each TCNT is an 8-bit readable/writable up-counter. TCNT_0 and TCNT_1 comprise a single 16-
bit register, so they can be accessed together by word access. The clock source is selected by the
CKS2 to CKS0 bits in TCR. TCNT can be cleared by an external reset input signal, compare-
match A signal or compare-match B signal. The method of clearing can be selected by the CCLR1
and CCLR0 bits in TCR. When TCNT overflows (changes from H'FF to H'00), the OVF bit in
TCSR is set to 1. TCNT is initialized to H'00.
TCNT_Y can be accessed when the HIE bit in SYSCR is 0 and the TMRX/Y bit in TCONRS is 1.
TCNT_X can be accessed when the HIE bit in SYSCR is 0 and the TMRX/Y bit in TCONRS is 0.
10.3.2 Time Constant Register A (TCORA)
TCORA is an 8-bit readable/writable register. TCORA_0 and TCORA_1 comprise a single 16-bit
register, so they can be accessed together by word access. TCORA is continually compared with
the value in TCNT. When a match is detected, the corresponding compare-match flag A (CMFA)
in TCSR is set to 1. Note however that comparison is disabled during the T2 state of a TCORA
write cycle. The timer output from the TMO pin can be freely controlled by these compare-match
A signals and the settings of output select bits OS1 and OS0 in TCSR. TCORA is initialized to
H'FF.
TCORA_Y can be accessed when the HIE bit in SYSCR is 0 and the TMRX/Y bit in TCONRS is
1. TCORA_X can be accessed when the HIE bit in SYSCR is 0 and the TMRX/Y bit in TCONRS
is 0.
10.3.3 Time Constant Register B (TCORB)
TCORB is an 8-bit readable/writable register. TCORB_0 and TCORB_1 comprise a single 16-bit
register, so they can be accessed together by word access. TCORB is continually compared with
the value in TCNT. When a match is detected, the corresponding compare-match flag B (CMFB)
in TCSR is set to 1. Note however that comparison is disabled during the T2 state of a TCORB
write cycle. The timer output from the TMO pin can be freely controlled by these compare-match
B signals and the settings of output select bits OS3 and OS2 in TCSR. TCORB is initialized to
H'FF.
TCORB_Y can be accessed when the HIE bit in SYSCR is 0 and the TMRX/Y bit in TCONRS is
1. TCORB_X can be accessed when the HIE bit in SYSCR is 0 and the TMRX/Y bit in TCONRS
is 0.
Rev. 1.00, 05/04, page 192 of 544
10.3.4 Timer Control Register (TCR)
TCR selects the TCNT clock source and the condition by which TCNT is cleared, and
enables/disables interrupt requests.
TCR_Y can be accessed when the HIE bit in SYSCR is 0 and the TMRX/Y bit in TCONRS is 1.
TCR_X can be accessed when the HIE bit in SYSCR is 0 and the TMRX/Y bit in TCONRS is 0.
Bit Bit Name
Initial
Value R/W Description
7 CMIEB 0 R/W Compare-Match Interrupt Enable B
Selects whether the CMFB interrupt request (CMIB) is
enabled or disabled when the CMFB flag in TCSR is set
to 1. For TMR_X, a CMIB interrupt does not occur
irrespective of the value of this bit.
0: CMFB interrupt request (CMIB) is disabled
1: CMFB interrupt request (CMIB) is enabled
6 CMIEA 0 R/W Compare-Match Interrupt Enable A
Selects whether the CMFA interrupt request (CMIA) is
enabled or disabled when the CMFA flag in TCSR is set
to 1. For TMR_X, a CMIA interrupt does not occur
irrespective of the value of this bit.
0: CMFA interrupt request (CMIA) is disabled
1: CMFA interrupt request (CMIA) is enabled
5 OVIE 0 R/W Timer Overflow Interrupt Enable
Selects whether the OVF interrupt request (OVI) is
enabled or disabled when the OVF flag in TCSR is set
to 1. For TMR_X, an OVI interrupt does not occur
irrespective of the value of this bit.
0: OVF interrupt request (OVI) is disabled
1: OVF interrupt request (OVI) is enabled
4
3
CCLR1
CCLR0
0
0
R/W
R/W
Counter Clear 1, 0
These bits select the method by which the timer counter
is cleared.
00: Clearing is disabled
01: Cleared on compare-match A
10: Cleared on compare-match B
11: Cleared on rising edge of external reset input
2
1
0
CKS2
CKS1
CKS0
0
0
0
R/W
R/W
R/W
Clock Select 2 to 0
These bits select the clock input to TCNT and count
condition, together with the ICKS1 and ICKS0 bits in
STCR. For details, see table 10.3.
Rev. 1.00, 05/04, page 193 of 544
Table 10.3 Clock Input to TCNT and Count Condition (1)
TCR STCR
Channel CKS2 CKS1 CKS0 ICKS1 ICKS0
Description
0 0 0 Disables clock input
0 0 1 0 Increments at falling edge of internal clock
φ/8
0 0 1 1 Increments at falling edge of internal clock
φ/2
0 1 0 0 Increments at falling edge of internal clock
φ/64
0 1 0 1 Increments at falling edge of internal clock
φ/32
0 1 1 0 Increments at falling edge of internal clock
φ/1024
0 1 1 1 Increments at falling edge of internal clock
φ/256
TMR_0
1 0 0 Increments at overflow signal from
TCNT_1*
0 0 0 Disables clock input
0 0 1 0 Increments at falling edge of internal clock
φ/8
0 0 1 1 Increments at falling edge of internal clock
φ/2
0 1 0 0 Increments at falling edge of internal clock
φ/64
0 1 0 1 Increments at falling edge of internal clock
φ/128
0 1 1 0 Increments at falling edge of internal clock
φ/1024
0 1 1 1 Increments at falling edge of internal clock
φ/2048
TMR_1
1 0 0 Increments at compare-match A from
TCNT_0*
Common 1 0 1 Increments at rising edge of external clock
1 1 0 Increments at falling edge of external clock
1 1 1 Increments at both rising and falling edges
of external clock
Note: * If the TMR_0 clock input is set as the TCNT_1 overflow signal and the TMR_1 clock
input is set as the TCNT_0 compare-match signal simultaneously, a count-up clock
cannot be generated. These settings should not be made.
Rev. 1.00, 05/04, page 194 of 544
Table 10.3 Clock Input to TCNT and Count Condition (2)
TCR TCRXY*2
Channel CKS2 CKS1 CKS0 CKSX CKSY Description
TMR_Y 0 0 0 — 0 Disables clock input
0 0 1 — 0 Increments at φ/4
0 1 0 — 0 Increments at φ/256
0 1 1 — 0 Increments at φ/2048
1 0 0 — 0 Disables clock input
0 0 0 — 1 Disables clock input
0 0 1 — 1 Increments at φ/4096
0 1 0 — 1 Increments at φ/8192
0 1 1 — 1 Increments at φ/16384
1 0 0 1 Increments at overflow signal from
TCNT_X*1
1 0 1 Increments at rising edge of external
clock
1 1 0 Increments at falling edge of external
clock
1 1 1 Increments at both rising and falling
edges of external clock
TMR_X 0 0 0 0 Disables clock input
0 0 1 0 Increments at φ
0 1 0 0 Increments at φ/2
0 1 1 0 Increments at φ/4
1 0 0 0 Disables clock input
0 0 0 1 Disables clock input
0 0 1 1 Increments at φ/2048
0 1 0 1 Increments at φ/4096
0 1 1 1 Increments at φ/8192
1 0 0 1 Increments at compare-match A from
TCNT_Y*1
1 0 1 Increments at rising edge of external
clock
1 1 0 Increments at falling edge of external
clock
1 1 1 Increments at both rising and falling
edges of external clock
Notes: 1. If the TMR_Y clock input is set as the TCNT_X overflow signal and the TMR_X clock
input is set as the TCNT_Y compare-match signal simultaneously, a count-up clock
cannot be generated. These settings should not be made.
2. The program development tool (emulator) does not support TCRXY. Selection of the
internal clock is only available when CKSX = 0 and CKSY = 0.
Rev. 1.00, 05/04, page 195 of 544
Table 10.3 Clock Input to TCNT and Count Condition (3)
TCR TCRAB
Channel CKS2 CKS1 CKS0 CKSA CKSB Description
TMR_B 0 0 0 — 0 Disables clock input
0 0 1 — 0 Increments at φ/4
0 1 0 — 0 Increments at φ/256
0 1 1 — 0 Increments at φ/2048
1 0 0 — 0 Disables clock input
0 0 0 — 1 Disables clock input
0 0 1 — 1 Increments at φ/4096
0 1 0 — 1 Increments at φ/8192
0 1 1 — 1 Increments at φ/16384
1 0 0 1 Increments at overflow signal from
TCNT_A*
1 0 1 Increments at rising edge of external
clock
1 1 0 Increments at falling edge of external
clock
1 1 1 Increments at both rising and falling
edges of external clock
TMR_A 0 0 0 0 Disables clock input
0 0 1 0 Increments at φ
0 1 0 0 Increments at φ/2
0 1 1 0 Increments at φ/4
1 0 0 0 Disables clock input
0 0 0 1 Disables clock input
0 0 1 1 Increments at φ/2048
0 1 0 1 Increments at φ/4096
0 1 1 1 Increments at φ/8192
1 0 0 1 Increments at compare-match A from
TCNT_B*
1 0 1 Increments at rising edge of external
clock
1 1 0 Increments at falling edge of external
clock
1 1 1 Increments at both rising and falling
edges of external clock
Notes: * If the TMR_B clock input is set as the TCNT_A overflow signal and the TMR_A clock
input is set as the TCNT_B compare-match signal simultaneously, a count-up clock
cannot be generated. These settings should not be made.
Rev. 1.00, 05/04, page 196 of 544
10.3.5 Timer Control/Status Register (TCSR)
TCSR indicates the status flags and controls compare-match output.
TCSR_0
Bit Bit Name
Initial
Value R/W Description
7 CMFB 0 R/(W)* Compare-Match Flag B
[Setting condition]
When the values of TCNT_0 and TCORB_0 match
[Clearing condition]
Read CMFB when CMFB = 1, then write 0 in CMFB
6 CMFA 0 R/(W)* Compare-Match Flag A
[Setting condition]
When the values of TCNT_0 and TCORA_0 match
[Clearing condition]
Read CMFA when CMFA = 1, then write 0 in CMFA
5 OVF 0 R/(W)* Timer Overflow Flag
[Setting condition]
When TCNT_0 overflows from H'FF to H'00
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
4 ADTE 0 R/W A/D Trigger Enable
Enables or disables A/D converter start requests by
compare-match A.
0: A/D converter start requests by compare-match A are
disabled
1: A/D converter start requests by compare-match A are
enabled
3
2
OS3
OS2
0
0
R/W
R/W
Output Select 3, 2
These bits specify how the TMO0 pin output level is to
be changed by compare-match B of TCORB_0 and
TCNT_0.
00: No change
01: 0 is output
10: 1 is output
11: Output is inverted (toggle output)
1
0
OS1
OS0
0
0
R/W
R/W
Output Select 1, 0
These bits specify how the TMO0 pin output level is to
be changed by compare-match A of TCORA_0 and
TCNT_0.
00: No change
01: 0 is output
10: 1 is output
11: Output is inverted (toggle output)
Note: * Only 0 can be written, for flag clearing.
Rev. 1.00, 05/04, page 197 of 544
TCSR_1
Bit Bit Name
Initial
Value R/W Description
7 CMFB 0 R/(W)* Compare-Match Flag B
[Setting condition]
When the values of TCNT_1 and TCORB_1 match
[Clearing condition]
Read CMFB when CMFB = 1, then write 0 in CMFB
6 CMFA 0 R/(W)* Compare-Match Flag A
[Setting condition]
When the values of TCNT_1 and TCORA_1 match
[Clearing condition]
Read CMFA when CMFA = 1, then write 0 in CMFA
5 OVF 0 R/(W)* Timer Overflow Flag
[Setting condition]
When TCNT_1 overflows from H'FF to H'00
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
4 — 1 R Reserved
This bit is always read as 1 and cannot be modified.
3
2
OS3
OS2
0
0
R/W
R/W
Output Select 3, 2
These bits specify how the TMO1 pin output level is to
be changed by compare-match B of TCORB_1 and
TCNT_1.
00: No change
01: 0 is output
10: 1 is output
11: Output is inverted (toggle output)
1
0
OS1
OS0
0
0
R/W
R/W
Output Select 1, 0
These bits specify how the TMO1 pin output level is to
be changed by compare-match A of TCORA_1 and
TCNT_1.
00: No change
01: 0 is output
10: 1 is output
11: Output is inverted (toggle output)
Note: * Only 0 can be written, for flag clearing.
Rev. 1.00, 05/04, page 198 of 544
TCSR_Y
Bit Bit Name
Initial
Value R/W Description
7 CMFB 0 R/(W)*1 Compare-Match Flag B
[Setting condition]
When the values of TCNT_Y and TCORB_Y match
[Clearing condition]
Read CMFB when CMFB = 1, then write 0 in CMFB
6 CMFA 0 R/(W)*1 Compare-Match Flag A
[Setting condition]
When the values of TCNT_Y and TCORA_Y match
[Clearing condition]
Read CMFA when CMFA = 1, then write 0 in CMFA
5 OVF 0 R/(W)*1 Timer Overflow Flag
[Setting condition]
When TCNT_Y overflows from H'FF to H'00
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
4 ICIE 0 R/W Input Capture Interrupt Enable
Enables or disables the ICF interrupt request (ICIX)
when the ICF bit in TCSR_X is set to 1.
0: ICF interrupt request (ICIX) is disabled
1: ICF interrupt request (ICIX) is enabled
3
2
OS3
OS2
0
0
R/W
R/W
Output Select 3, 2
These bits specify how the TMOY pin*2 output level is to
be changed by compare-match B of TCORB_Y and
TCNT_Y.
00: No change
01: 0 is output
10: 1 is output
11: Output is inverted (toggle output)
1
0
OS1
OS0
0
0
R/W
R/W
Output Select 1, 0
These bits specify how the TMOY pin*2 output level is to
be changed by compare-match A of TCORA_Y and
TCNT_Y.
00: No change
01: 0 is output
10: 1 is output
11: Output is inverted (toggle output)
Notes: 1. Only 0 can be written, for flag clearing.
2. The program development tool (emulator) does not support this pin.
Rev. 1.00, 05/04, page 199 of 544
TCSR_X
Bit Bit Name
Initial
Value R/W Description
7 CMFB 0 R/(W)* Compare-Match Flag B
[Setting condition]
When the values of TCNT_X and TCORB_X match
[Clearing condition]
Read CMFB when CMFB = 1, then write 0 in CMFB
6 CMFA 0 R/(W)* Compare-Match Flag A
[Setting condition]
When the values of TCNT_X and TCORA_X match
[Clearing condition]
Read CMFA when CMFA = 1, then write 0 in CMFA
5 OVF 0 R/(W)* Timer Overflow Flag
[Setting condition]
When TCNT_X overflows from H'FF to H'00
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
4 ICF 0 R/(W)* Input Capture Flag
[Setting condition]
When a rising edge and falling edge is detected in the
external reset signal in that order.
[Clearing condition]
Read ICF when ICF = 1, then write 0 in ICF
3
2
OS3
OS2
0
0
R/W
R/W
Output Select 3, 2
These bits specify how the TMOX pin output level is to
be changed by compare-match B of TCORB_X and
TCNT_X.
00: No change
01: 0 is output
10: 1 is output
11: Output is inverted (toggle output)
1
0
OS1
OS0
0
0
R/W
R/W
Output Select 1, 0
These bits specify how the TMOX pin output level is to
be changed by compare-match A of TCORA_X and
TCNT_X.
00: No change
01: 0 is output
10: 1 is output
11: Output is inverted (toggle output)
Note: * Only 0 can be written, for flag clearing.
Rev. 1.00, 05/04, page 200 of 544
TCSR_B
Bit Bit Name
Initial
Value R/W Description
7 CMFB 0 R/(W)* Compare-Match Flag B
[Setting condition]
When the values of TCNT_B and TCORB_B match
[Clearing condition]
Read CMFB when CMFB = 1, then write 0 in CMFB
6 CMFA 0 R/(W)* Compare-Match Flag A
[Setting condition]
When the values of TCNT_B and TCORA_B match
[Clearing condition]
Read CMFA when CMFA = 1, then write 0 in CMFA
5 OVF 0 R/(W)* Timer Overflow Flag
[Setting condition]
When TCNT_B overflows from H'FF to H'00
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
4 ICIE 0 R/W Input Capture Interrupt Enable
Enables or disables the ICF interrupt request (ICIA)
when the ICF bit in TCSR_A is set to 1.
0: ICF interrupt request (ICIA) is disabled
1: ICF interrupt request (ICIA) is enabled
3
2
OS3
OS2
0
0
R/W
R/W
Output Select 3, 2
These bits specify how the TMOB pin output level is to
be changed by compare-match B of TCORB_B and
TCNT_B.
00: No change
01: 0 is output
10: 1 is output
11: Output is inverted (toggle output)
1
0
OS1
OS0
0
0
R/W
R/W
Output Select 1, 0
These bits specify how the TMOB pin output level is to
be changed by compare-match A of TCORA_B and
TCNT_B.
00: No change
01: 0 is output
10: 1 is output
11: Output is inverted (toggle output)
Notes: * Only 0 can be written, for flag clearing.
Rev. 1.00, 05/04, page 201 of 544
TCSR_A
Bit Bit Name
Initial
Value R/W Description
7 CMFB 0 R/(W)* Compare-Match Flag B
[Setting condition]
When the values of TCNT_A and TCORB_A match
[Clearing condition]
Read CMFB when CMFB = 1, then write 0 in CMFB
6 CMFA 0 R/(W)* Compare-Match Flag A
[Setting condition]
When the values of TCNT_A and TCORA_A match
[Clearing condition]
Read CMFA when CMFA = 1, then write 0 in CMFA
5 OVF 0 R/(W)* Timer Overflow Flag
[Setting condition]
When TCNT_A overflows from H'FF to H'00
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
4 ICF 0 R/(W)* Input Capture Flag
[Setting condition]
When a rising edge and falling edge is detected in the
external reset signal in that order.
[Clearing condition]
Read ICF when ICF = 1, then write 0 in ICF
3
2
OS3
OS2
0
0
R/W
R/W
Output Select 3, 2
These bits specify how the TMOA pin output level is to
be changed by compare-match B of TCORB_A and
TCNT_A.
00: No change
01: 0 is output
10: 1 is output
11: Output is inverted (toggle output)
1
0
OS1
OS0
0
0
R/W
R/W
Output Select 1, 0
These bits specify how the TMOA pin output level is to
be changed by compare-match A of TCORA_A and
TCNT_A.
00: No change
01: 0 is output
10: 1 is output
11: Output is inverted (toggle output)
Note: * Only 0 can be written, for flag clearing.
Rev. 1.00, 05/04, page 202 of 544
10.3.6 Time Constant Register (TCORC)
TCORC is an 8-bit readable/writable register. The sum of contents of TCORC and TICR is always
compared with TCNT. When a match is detected, a compare-match C signal is generated.
However, comparison at the T2 state in the write cycle to TCORC and at the input capture cycle of
TICR is disabled. TCORC is initialized to H'FF.
10.3.7 Input Capture Registers R and F (TICRR, TICRF, TICRR_A and TICRF_A)
TICRR and TICRF are 8-bit read-only registers. While the ICST bit in TCONRI (TCRAB) is set
to 1, the contents of TCNT are transferred at the rising edge and falling edge of the external reset
input (TMRIX and TMRIA) in that order. The ICST bit is cleared to 0 when one capture operation
ends. TICRR and TICRF are initialized to H'00.
10.3.8 Timer Input Select Register (TISR and TISR_B)
TISR permits or prohibits a signal source of external clock/reset input for the counter.
Bit Bit Name Initial
Value R/W Description
7 to 1 All 1 R/(W) Reserved
The initial value should not be changed.
0 IS 0 R/W Input Select
Selects a timer clock/reset input pin (TMIn) as the
signal source of external clock/reset input for the
TMR_n counter.
0: TMIn (TMCIn/TMRIn) is prohibited
1: TMIn (TMCIn/TMRIn) is permitted for input
Note: n = Y and B
Rev. 1.00, 05/04, page 203 of 544
10.3.9 Timer Connection Register I (TCONRI)
TCONRI controls the input capture function.
Bit Bit Name
Initial
Value R/W Description
7 to 5 All 0 R/W Reserved
The initial value should not be changed.
4 ICST 0 R/W Input Capture Start Bit
TMR_X has input capture registers (TICRR and
TICRF). TICRR and TICRF can measure the width of a
pulse by means of a single capture operation under the
control of the ICST bit. When a rising edge followed by
a falling edge is detected on TMRIX after the ICST bit
is set to 1, the contents of TCNT at those points are
captured into TICRR and TICRF, respectively, and the
ICST bit is cleared to 0.
[Clearing condition]
When a rising edge followed by a falling edge is
detected on TMRIX
[Setting condition]
When 1 is written in ICST after reading ICST = 0
3 to 0 All 0 R/W Reserved
The initial values should not be modified.
10.3.10 Timer Connection Register S (TCONRS)
TCONRS selects whether to access TMR_X or TMR_Y registers.
Bit Bit Name
Initial
Value R/W Description
7 TMR_X/Y 0 R/W TMR_X/TMR_Y Access Select
For details, see table 10.4.
0: The TMR_X registers are accessed at addresses
H'(FF)FFF0 to H'(FF)FFF5
1: The TMR_Y registers are accessed at addresses
H'(FF)FFF0 to H'(FF)FFF5
6 to 0 All 0 R/W Reserved
The initial values should not be modified.
Rev. 1.00, 05/04, page 204 of 544
Table 10.4 Registers Accessible by TMR_X/TMR_Y
TMRX/Y H'FFF0 H'FFF1 H'FFF2 H'FFF3 H'FFF4 H'FFF5 H'FFF6 H'FFF7
0 TMR_X
TCR_X
TMR_X
TCSR_X
TMR_X
TICRR
TMR_X
TICRF
TMR_X
TCNT
TMR_X
TCORC
TMR_X
TCORA_X
TMR_X
TCORB_X
1 TMR_Y
TCR_Y
TMR_Y
TCSR_Y
TMR_Y
TCORA_Y
TMR_Y
TCORB_Y
TMR_Y
TCNT_Y
TMR_Y
TISR
10.3.11 Timer XY Control Register (TCRXY)
TCRXY selects the TMR_X and TMR_Y output pins and internal clock.
Bit Bit Name
Initial
Value R/W Description
7 IOSX 0 R/W TMR_X I/O Select
0: Output to P67/TMOX and input from P60/TMIX
1: Output to PF6/ExTMOX and input from PF4/ExTMIX
6 IOSY 0 R/W TMR_Y Output Enable
0: Output to PF7/TMOY is prohibited and input from
P62/TMIY
1: Output to PF7/TMOY is permitted and input from
PF5/ExTMIY
5 CKSX 0 R/W TMR_X Clock Select
For details about selection, see the clock conditions in
table 10.3.
4 CKSY 0 R/W TMR_Y Clock Select
For details about selection, see the clock conditions in
table 10.3.
3 to 0 All 0 R/W Reserved
The initial value should not be changed.
Note: * The program development tool (emulator) does not support TCRXY.
Rev. 1.00, 05/04, page 205 of 544
10.3.12 Timer AB Control Register (TCRAB)
TCRAB selects the internal clock or controls the input capture function in the TMR_A and
TMR_B.
Bit Bit Name
Initial
Value R/W Description
7, 6 All 0 R/W Reserved
The initial value should not be modified.
5 CKSA 0 R/W TMR_A Clock Select
For details about selection, see the clock conditions in
table 10.3.
4 CKSB 0 R/W TMR_B Clock Select
For details about selection, see the clock conditions in
table 10.3.
3 ICST 0 R/W
Input Capture Start Bit
TMR_A has input capture registers (TICRR_A and
TICRF_A). TICRR and TICRF can measure the width
of a pulse by means of a single capture operation
under the control of the ICST bit. When a rising edge
followed by a falling edge is detected on TMRIA after
the ICST bit is set to 1, the contents of TCNT at those
points are captured into TICRR and TICRF,
respectively, and the ICST bit is cleared to 0.
[Clearing condition]
When a rising edge followed by a falling edge is
detected on TMRIA
[Setting condition]
When 1 is written in ICST after reading ICST = 0
2 to 0 0 R/W Reserved
The initial value should not be modified.
Note: * The program development tool (emulator) does not support TCRXY.
Rev. 1.00, 05/04, page 206 of 544
10.4 Operation
10.4.1 Pulse Output
Figure 10.4 shows an example for outputting an arbitrary duty pulse.
1. Clear the CCLR1 bit in TCR to 0 so that TCNT is cleared according to the compare match of
TCORA, and then set the CCLR0 bit to 1.
2. Set the OS3 to OS0 bits in TCSR to B'0110 so that 1 is output according to the compare match
of TCORA and 0 is output according to the compare match of TCORB.
According to the above settings, the waveforms with the TCORA cycle and TCORB pulse width
can be output without the intervention of software.
TCNT
H'FF Counter clear
TCORA
TCORB
H'00
TMO
Figure 10.4 Pulse Output Example
Rev. 1.00, 05/04, page 207 of 544
10.5 Operation Timing
10.5.1 TCNT Count Timing
Figure 10.5 shows the TCNT count timing with an internal clock source. Figure 10.6 shows the
TCNT count timing with an external clock source. The pulse width of the external clock signal
must be at least 1.5 system clocks (φ) for a single edge and at least 2.5 system clocks (φ) for both
edges. The counter will not increment correctly if the pulse width is less than these values.
φ
Internal clock
TCNT input
clock
TCNT N – 1 N N + 1
Figure 10.5 Count Timing for Internal Clock Input
φ
External clock
input pin
TCNT input
clock
TCNT N – 1 N N + 1
Figure 10.6 Count Timing for External Clock Input (Both Edges)
10.5.2 Timing of CMFA and CMFB Setting at Compare-Match
The CMFA and CMFB flags in TCSR are set to 1 by a compare-match signal generated when the
TCNT and TCOR values match. The compare-match signal is generated at the last state in which
the match is true, just when the timer counter is updated. Therefore, when TCNT and TCOR
match, the compare-match signal is not generated until the next TCNT input clock. Figure 10.7
shows the timing of CMF flag setting.
Rev. 1.00, 05/04, page 208 of 544
φ
TCNT N N + 1
TCOR N
Compare-match
signal
CMF
Figure 10.7 Timing of CMF Setting at Compare-Match
10.5.3 Timing of Timer Output at Compare-Match
When a compare-match signal occurs, the timer output changes as specified by the OS3 to OS0
bits in TCSR. Figure 10.8 shows the timing of timer output when the output is set to toggle by a
compare-match A signal.
φ
Compare-match A
signal
Timer output pin
Figure 10.8 Timing of Toggled Timer Output by Compare-Match A Signal
10.5.4 Timing of Counter Clear at Compare-Match
TCNT is cleared when compare-match A or compare-match B occurs, depending on the setting of
the CCLR1 and CCLR0 bits in TCR. Figure 10.9 shows the timing of clearing the counter by a
compare-match.
φ
N H'00
Compare-match
signal
TCNT
Figure 10.9 Timing of Counter Clear by Compare-Match
Rev. 1.00, 05/04, page 209 of 544
10.5.5 TCNT External Reset Timing
TCNT is cleared at the rising edge of an external reset input, depending on the settings of the
CCLR1 and CCLR0 bits in TCR. The width of the clearing pulse must be at least 1.5 states. Figure
10.10 shows the timing of clearing the counter by an external reset input.
φ
Clear signal
External reset
input pin
TCNT N H'00N – 1
Figure 10.10 Timing of Counter Clear by External Reset Input
10.5.6 Timing of Overflow Flag (OVF) Setting
The OVF bit in TCSR is set to 1 when the TCNT overflows (changes from H'FF to H'00). Figure
10.11 shows the timing of OVF flag setting.
φ
OVF
Overflow signal
TCNT H'FF H'00
Figure 10.11 Timing of OVF Flag Setting
Rev. 1.00, 05/04, page 210 of 544
10.6 TMR_0 and TMR_1 Cascaded Connection
If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two
channels are cascaded. With this configuration, the 16-bit count mode or compare-match count
mode is available.
10.6.1 16-Bit Count Mode
When bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit timer
with TMR_0 occupying the upper 8 bits and TMR_1 occupying the lower 8 bits.
Setting of compare-match flags
The CMF flag in TCSR_0 is set to 1 when a 16-bit compare-match occurs.
The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare-match occurs.
Counter clear specification
If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare-match,
the 16-bit counter (TCNT_0 and TCNT_1 together) is cleared when a 16-bit compare-
match occurs. The 16-bit counter (TCNT_0 and TCNT_1 together) is also cleared when
counter clear by the TMI0 pin has been set.
The settings of the CCLR1 and CCLR0 bits in TCR_1 are ignored. The lower 8 bits cannot be
cleared independently.
Pin output
Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR_0 is in accordance with
the 16-bit compare-match conditions.
Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR_1 is in accordance with
the lower 8-bit compare-match conditions.
10.6.2 Compare-Match Count Mode
When bits CKS2 to CKS0 in TCR_1 are B'100, TCNT_1 counts the occurrence of compare-match
A for TMR_0. TMR_0 and TMR_1 are controlled independently. Conditions such as setting of the
CMF flag, generation of interrupts, output from the TMO pin, and counter clearing are in
accordance with the settings for each or TMR_0 and TMR_1.
Rev. 1.00, 05/04, page 211 of 544
10.7 TMR_Y and TMR_X Cascaded Connection
If bits CKS2 to CKS0 in either TCR_Y or TCR_X are set to B'100, the 8-bit timers of the two
channels are cascaded. With this configuration, 16-bit count mode or compare-match count mode
can be selected by the settings of the CKSX and CKSY bits in TCRXY.
10.7.1 16-Bit Count Mode
When bits CKS2 to CKS0 in TCR_Y are set to B'100 and the CKSY bit in TCRXY is set to 1, the
timer functions as a single 16-bit timer with TMR_Y occupying the upper eight bits and TMR_X
occupying the lower 8 bits.
Setting of compare-match flags
The CMF flag in TCSR_Y is set to 1 when an upper 8-bit compare-match occurs.
The CMF flag in TCSR_X is set to 1 when a lower 8-bit compare-match occurs.
Counter clear specification
If the CCLR1 and CCLR0 bits in TCR_Y have been set for counter clear at compare-match,
only the upper eight bits of TCNT_Y are cleared. The upper eight bits of TCNT_Y are also
cleared when counter clear by the TMRIY pin has been set.
The settings of the CCLR1 and CCLR0 bits in TCR_X are enabled, and the lower 8 bits of
TCNT_X can be cleared by the counter.
Pin output
Control of output from the TMOY pin by bits OS3 to OS0 in TCSR_Y is in accordance with
the upper 8-bit compare-match conditions.
Control of output from the TMOX pin by bits OS3 to OS0 in TCSR_X is in accordance with
the lower 8-bit compare-match conditions.
Note: The program development tool (emulator) does not support 16-bit count mode.
10.7.2 Compare-Match Count Mode
When bits CKS2 to CKS0 in TCR_X are set to B'100 and the CKSX bit in TCRXY is set to 1,
TCNT_X counts the occurrence of compare-match A for TMR_Y. TMR_X and TMR_Y are
controlled independently. Conditions such as setting of the CMF flag, generation of interrupts,
output from the TMO pin, and counter clearing are in accordance with the settings for each
channel.
Note: The program development tool (emulator) does not support compare-match count mode.
Rev. 1.00, 05/04, page 212 of 544
10.7.3 Input Capture Operation
TMR_X has input capture registers (TICRR and TICRF). A narrow pulse width can be measured
with TICRR and TICRF, using a single capture. If the falling edge of TMRIX (TMR_X input
capture input signal) is detected after its rising edge has been detected, the value of TCNT_X at
that time is transferred to both TICRR and TICRF.
10.8 TMR_B and TMR_A Cascaded Connection
If bits CKS2 to CKS0 in either TCR_B or TCR_A are set to B'100, the 8-bit timers of the two
channels are cascaded. With this configuration, 16-bit count mode or compare-match count mode
can be selected by the settings of the CKSA and CKSB bits in TCRAB.
10.8.1 16-Bit Count Mode
When bits CKS2 to CKS0 in TCR_B are set to B'100 and the CKSB bit in TCRAB is set to 1, the
timer functions as a single 16-bit timer with TMR_B occupying the upper eight bits and TMR_A
occupying the lower 8 bits.
Setting of compare-match flags
The CMF flag in TCSR_B is set to 1 when an upper 8-bit compare-match occurs.
The CMF flag in TCSR_A is set to 1 when a lower 8-bit compare-match occurs.
Counter clear specification
If the CCLR1 and CCLR0 bits in TCR_B have been set for counter clear at compare-match,
only the upper eight bits of TCNT_B are cleared. The upper eight bits of TCNT_B are also
cleared when counter clear by the TMRIB pin has been set.
The settings of the CCLR1 and CCLR0 bits in TCR_A are enabled, and the lower 8 bits of
TCNT_A can be cleared by the counter.
Pin output
Control of output from the TMOB pin by bits OS3 to OS0 in TCSR_B is in accordance with
the upper 8-bit compare-match conditions.
Control of output from the TMOA pin by bits OS3 to OS0 in TCSR_A is in accordance with
the lower 8-bit compare-match conditions.
10.8.2 Compare-Match Count Mode
When bits CKS2 to CKS0 in TCR_A are set to B'100 and the CKSA bit in TCRAB is set to 1,
TCNT_A counts the occurrence of compare-match A for TMR_B. TMR_A and TMR_B are
controlled independently. Conditions such as setting of the CMF flag, generation of interrupts,
output from the TMO pin, and counter clearing are in accordance with the settings for each
channel.
Rev. 1.00, 05/04, page 213 of 544
10.8.3 Input Capture Operation
TMR_A has input capture registers (TICRR_A and TICRF_A). A narrow pulse width can be
measured with TICRR and TICRF, using a single capture. If the falling edge of TMRIA (TMR_A
input capture input signal) is detected after its rising edge has been detected, the value of TCNT_A
at that time is transferred to both TICRR and TICRF.
Input Capture Signal Input Timing: Figure 10.12 shows the timing of the input capture
operation.
φ
TMRIX
TMRIA
Input capture
signal
TCNT_X
TCNT_A
n
nn
m
M
m
N + 1N
N
n + 1
TICRR
TICRF
Figure 10.12 Timing of Input Capture Operation
If the input capture signal is input while TICRR and TICRF are being read, the input capture
signal is delayed by one system clock ) cycle. Figure 10.13 shows the timing of this operation.
φ
TMRIX
TMRIA
TICRR, TICRF read cycle
T1T2
Input capture
signal
Figure 10.13 Timing of Input Capture Signal
(Input capture signal is input during TICRR and TICRF read)
Rev. 1.00, 05/04, page 214 of 544
Selection of Input Capture Signal Input: TMRIX (input capture input signal of TMR_X) is
selected according to the setting of the ICST bit in TCONRI. The input capture signal selection is
shown in table 10.5.
Table 10.5 Input Capture Signal Selection
TCONRI
Bit 4
ICST
Description
0 Input capture function not used
1 TMIX pin input selection
TMRIA (input capture input signal of TMR_A) is selected according to the setting of the ICST but
in TCRAB. The input capture signal selection is shown in table 10.6.
Table 10.6 Input Capture Signal Selection
TCRAB
Bit 3
ICST
Description
0 Input capture function not used
1 TMIA pin input selection
Rev. 1.00, 05/04, page 215 of 544
10.9 Interrupt Sources
TMR_0, TMR_1, and TMR_Y can generate three types of interrupts: CMIA, CMIB, and OVI.
TMR_X can generate an ICIX interrupt. TMR_A can generate four types of interrupts, CMIA,
CMIB, OVI and ICIA. Table 10.7 shows the interrupt sources and priorities. Each interrupt source
can be enabled or disabled independently by interrupt enable bits in TCR or TCSR. Independent
signals are sent to the interrupt controller for each interrupt.
Table 10.7 Interrupt Sources of 8-Bit Timers TMR_0, TMR_1, TMR_Y, TMR_X TMR_B,
and TMR_A
Channel Name Interrupt Source Interrupt Flag
Interrupt
Priority
CMIA0 TCORA_0 compare-match CMFA High
CMIB0 TCORB_0 compare-match CMFB
TMR_0
OVI0 TCNT_0 overflow OVF
CMIA1 TCORA_1 compare-match CMFA
CMIB1 TCORB_1 compare-match CMFB
TMR_1
OVI1 TCNT_1 overflow OVF
CMIAY TCORA_Y compare-match CMFA
CMIBY TCORB_Y compare-match CMFB
TMR_Y
OVIY TCNT_Y overflow OVF
TMR_X ICIX Input capture ICF
CMIAAB TCORA_A, TCORA_B
compare-match*
CMFA
CMIBAB TCORB_A, TCORB_B
compare-match*
CMFB
TMR_B,
TMR_A
OVIAB TCNT_A, TCNT_B overflow* OVF
TMR_A ICIA Input capture ICF Low
Note: * The interrupt sources for TMR_B and TMR_A are allocated to the same vector
addresses. The bits CMIEB, CMIEA, and OVIE in TCR register of TMR_B or TMR_A
should be set to 1.
Rev. 1.00, 05/04, page 216 of 544
10.10 Usage Notes
10.10.1 Conflict between TCNT Write and Counter Clear
If a counter clear signal is generated during the T2 state of a TCNT write cycle as shown in figure
10.14, clearing takes priority and the counter write is not performed.
φ
Address TCNT address
Internal write signal
Counter clear signal
TCNT
Note: * TMR_A, TMR_B
NH'00
T
1
T
2
T
3
*
TCNT write cycle by CPU
Figure 10.14 Conflict between TCNT Write and Clear
10.10.2 Conflict between TCNT Write and Count-Up
If a count-up occurs during the T2 state of a TCNT write cycle as shown in figure 10.15, the
counter write takes priority and the counter is not incremented.
Note: * TMR_A, TMR_B
T1T2T3*
φ
Address TCNT address
Internal write signal
TCNT input clock
TCNT N M
TCNT write cycle by CPU
Counter write data
Figure 10.15 Conflict between TCNT Write and Count-Up
Rev. 1.00, 05/04, page 217 of 544
10.10.3 Conflict between TCOR Write and Compare-Match
If a compare-match occurs during the T2 state of a TCOR write cycle as shown in figure 10.16, the
TCOR write takes priority and the compare-match signal is disabled. With TMR_X, and TMR_A,
a TICR input capture conflicts with a compare-match in the same way as with a write to TCORC.
In this case also, the input capture takes priority and the compare-match signal is disabled.
φ
Address TCOR address
Internal write signal
TCNT
TCOR N M
TCOR write cycle by CPU
TCOR write data
N N + 1
Compare-match signal Disabled
Note: * TMR_A, TMR_B
T
1
T
2
T
3
*
Figure 10.16 Conflict between TCOR Write and Compare-Match
10.10.4 Conflict between Compare-Matches A and B
If compare-matches A and B occur at the same time, the operation follows the output status that is
defined for compare-match A or B, according to the priority of the timer output shown in table
10.8.
Table 10.8 Timer Output Priorities
Output Setting Priority
Toggle output High
1 output
0 output
No change Low
Rev. 1.00, 05/04, page 218 of 544
10.10.5 Switching of Internal Clocks and TCNT Operation
TCNT may increment erroneously when the internal clock is switched over. Table 10.9 shows the
relationship between the timing at which the internal clock is switched (by writing to the CKS1
and CKS0 bits) and the TCNT operation.
When the TCNT clock is generated from an internal clock, the falling edge of the internal clock
pulse is detected. If clock switching causes a change from high to low level, as shown in no. 3 in
table 10.9, a TCNT clock pulse is generated on the assumption that the switchover is a falling
edge, and TCNT is incremented.
Erroneous incrementation can also happen when switching between internal and external clocks.
Table 10.9 Switching of Internal Clocks and TCNT Operation
No.
Timing of Switchover
by Means of CKS1
and CKS0 Bits
TCNT Clock Operation
1 Clock switching from low to
low level*1
Clock before
switchover
Clock after
switchover
TCNT
clock
TCNT
CKS bit rewrite
N N + 1
2 Clock switching from low to
high level2
Clock before
switchover
Clock after
switchover
TCNT
clock
TCNT
CKS bit rewrite
N N + 1 N + 2
Rev. 1.00, 05/04, page 219 of 544
No.
Timing of Switchover
by Means of CKS1
and CKS0 Bits
TCNT Clock Operation
3 Clock switching from high
to low level3
Clock before
switchover
Clock after
switchover
TCNT
clock
TCNT
CKS bit rewrite
N N + 1 N + 2
*4
4 Clock switching from high
to high level
Clock before
switchover
Clock after
switchover
TCNT
clock
TCNT
CKS bit rewrite
N N + 1 N + 2
Notes: 1. Includes switching from low to stop, and from stop to low.
2. Includes switching from stop to high.
3. Includes switching from high to stop.
4. Generated on the assumption that the switchover is a falling edge; TCNT is
incremented.
10.10.6 Mode Setting with Cascaded Connection
If the 16-bit count mode and compare-match count mode are set simultaneously, the input clock
pulses for TCNT_0 and TCNT_1, and TCNT_X and TCNT_Y and TCNT_A and TCNT_B are
not generated, and thus the counters will stop operating. Simultaneous setting of these two modes
should therefore be avoided.
10.10.7 Module Stop Mode Setting
TMR operation can be enabled or disabled using the module stop control register. The initial
setting is for TMR operation to be halted. Register access is enabled by canceling the module stop
mode. For details, refer to section 20, Power-Down Modes.
Rev. 1.00, 05/04, page 220 of 544
WDT0102A_020020040200 Rev. 1.00, 05/04, page 221 of 544
Section 11 Watchdog Timer (WDT)
This LSI incorporates two watchdog timer channels (WDT_0 and WDT_1). The watchdog timer
can generate an internal reset signal or an internal NMI interrupt signal if a system crash prevents
the CPU from writing to the timer counter, thus allowing it to overflow. Simultaneously, it can
output an overflow signal (RESO) externally.
When this watchdog function is not needed, the WDT can be used as an interval timer. In interval
timer operation, an interval timer interrupt is generated each time the counter overflows. A block
diagram of the WDT_0 and WDT_1 is shown in figure 11.1.
11.1 Features
Selectable from eight (WDT_0) or 16 (WDT_1) counter input clocks.
Switchable between watchdog timer mode and interval timer mode
Watchdog Timer Mode:
If the counter overflows, an internal reset or an internal NMI interrupt is generated.
When the LSI is selected to be internally reset at counter overflow, a low level signal is output
from the RESO pin if the counter overflows.
Internal Timer Mode:
If the counter overflows, an internal timer interrupt (WOVI) is generated.
Rev. 1.00, 05/04, page 222 of 544
WOVI0
(Interrupt request signal)
Internal NMI
(Interrupt request signal*
2
)
RESO signal*
1
Internal reset signal*
1
TCNT_0 TCSR_0
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
Internal clock
Overflow
Interrupt
control
Reset
control
WOVI1
(Interrupt request signal)
Internal reset signal*
1
RESO signal*
1
TCNT_1 TCSR_1
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
Clock Clock
selection
Internal clock
Bus
interface
Module bus
TCSR_0 : Timer control/status register_0
TCNT_0 : Timer counter_0
TCSR_1 : Timer control/status register_1
TCNT_1 : Timer counter_1
Notes: 1. The RESO signal outputs the low level signal when the internal reset signal is
generated due to a TCNT overflow of either WDT_0 or WDT_1. The internal reset signal
first resets the WDT in which the overflow has occurred first.
2. The internal NMI interrupt signal can be independently output from either WDT_0 or WDT_1.
The interrupt controller does not distinguish the NMI interrupt request from WDT_0 from
that from WDT_1.
Internal bus
WDT_1
[Legend]
Internal NMI
(Interrupt request signal*
2
)
φSUB/2
φSUB/4
φSUB/8
φSUB/16
φSUB/32
φSUB/64
φSUB/128
φSUB/256
Overflow
Interrupt
control
Reset
control
Clock Clock
selection
Bus
interface
Module bus
Internal bus
WDT_0
Figure 11.1 Block Diagram of WDT
Rev. 1.00, 05/04, page 223 of 544
11.2 Input/Output Pins
The WDT has the pins listed in table 11.1.
Table 11.1 Pin Configuration
Name Symbol I/O Function
Reset output pin RESO Output Outputs the counter overflow signal in
watchdog timer mode
External sub-clock input pin EXCL Input Inputs the clock pulses to the WDT_1
prescaler counter
11.3 Register Descriptions
The WDT has the following registers. To prevent accidental overwriting, TCSR and TCNT have
to be written to in a method different from normal registers. For details, refer to section 11.6.1,
Notes on Register Access. For details on the system control register, refer to section 3.2.2, System
Control Register (SYSCR).
Timer counter (TCNT)
Timer control/status register (TCSR)
11.3.1 Timer Counter (TCNT)
TCNT is an 8-bit readable/writable up-counter.
TCNT is initialized to H'00 when the TME bit in the timer control/status register (TCSR) is
cleared to 0.
Rev. 1.00, 05/04, page 224 of 544
11.3.2 Timer Control/Status Register (TCSR)
TCSR selects the clock source to be input to TCNT, and the timer mode.
TCSR_0
Bit Bit Name
Initial
Value R/W Description
7 OVF 0 R/(W)*1 Overflow Flag
Indicates that TCNT has overflowed (changes from
H'FF to H'00).
[Setting condition]
When TCNT overflows (changes from H'FF to H'00)
However, when internal reset request generation is
selected in watchdog timer mode, OVF is cleared
automatically by the internal reset.
[Clearing conditions]
When TCSR is read when OVF = 1*2, then 0 is
written to OVF
When 0 is written to TME
6 WT/IT 0 R/W Timer Mode Select
Selects whether the WDT is used as a watchdog timer
or interval timer.
0: Interval timer mode
1: Watchdog timer mode
5 TME 0 R/W Timer Enable
When this bit is set to 1, TCNT starts counting.
When this bit is cleared, TCNT stops counting and is
initialized to H'00.
4 — 0 R/(W) Reserved
The initial value should not be modified.
3 RST/NMI 0 R/W Reset or NMI
Selects to request an internal reset or an NMI interrupt
when TCNT has overflowed.
0: An NMI interrupt is requested
1: An internal reset is requested
Rev. 1.00, 05/04, page 225 of 544
Bit Bit Name
Initial
Value R/W Description
2
1
0
CKS2
CKS1
CKS0
0
0
0
R/W
R/W
R/W
Clock Select 2 to 0
Selects the clock source to be input to. The overflow
frequency for φ = 10 MHz is enclosed in parentheses.
000: φ/2 (frequency: 51.2 µs)
001: φ/64 (frequency: 1.64 ms)
010: φ/128 (frequency: 3.28 ms)
011: φ/512 (frequency: 13.1 ms)
100: φ/2048 (frequency: 52.4 ms)
101: φ/8192 (frequency: 209.7 ms)
110: φ/32768 (frequency: 0.84 s)
111: φ/131072 (frequency: 3.36 s)
Notes: 1. Only 0 can be written, to clear the flag.
2. When OVF is polled with the interval timer interrupt disabled, OVF = 1 must be read at
least twice.
TCSR_1
Bit Bit Name
Initial
Value R/W Description
7 OVF 0 R/(W)*1 Overflow Flag
Indicates that TCNT has overflowed (changes from H'FF
to H'00).
[Setting condition]
When TCNT overflows (changes from H'FF to H'00)
However, when internal reset request generation is
selected in watchdog timer mode, OVF is cleared
automatically by the internal reset.
[Clearing conditions]
When TCSR is read when OVF = 1*2, then 0 is written to
OVF
When 0 is written to TME
6 WT/IT 0 R/W Timer Mode Select
Selects whether the WDT is used as a watchdog timer
or interval timer.
0: Interval timer mode
1: Watchdog timer mode
5 TME 0 R/W Timer Enable
When this bit is set to 1, TCNT starts counting.
When this bit is cleared, TCNT stops counting and is
initialized to H'00.
Rev. 1.00, 05/04, page 226 of 544
Bit Bit Name
Initial
Value R/W Description
4 PSS 0 R/W Prescaler Select
Selects the clock source to be input to TCNT.
0: Counts the divided cycle of φ–based prescaler (PSM)
1: Counts the divided cycle of φSUB–based prescaler
(PSS)
3 RST/NMI 0 R/W Reset or NMI
Selects to request an internal reset or an NMI interrupt
when TCNT has overflowed.
0: An NMI interrupt is requested
1: An internal reset is requested
2
1
0
CKS2
CKS1
CKS0
0
0
0
R/W
R/W
R/W
Clock Select 2 to 0
Selects the clock source to be input to TCNT. The
overflow cycle for φ = 10 MHz and φSUB = 32.768 kHz is
enclosed in parentheses.
When PSS = 0:
000: φ/2 (frequency: 51.2 µs)
001: φ/64 (frequency: 1.64 ms)
010: φ/128 (frequency: 3.28 ms)
011: φ/512 (frequency: 13.1 ms)
100: φ/2048 (frequency: 52.4 ms)
101: φ/8192 (frequency: 209.7 ms)
110: φ/32768 (frequency: 0.84 s)
111: φ/131072 (frequency: 3.36 s)
When PSS = 1:
000: φSUB/2 (cycle: 15.6 ms)
001: φSUB/4 (cycle: 31.3 ms)
010: φSUB/8 (cycle: 62.5 ms)
011: φSUB/16 (cycle: 125 ms)
100: φSUB/32 (cycle: 250 ms)
101: φSUB/64 (cycle: 500 ms)
110: φSUB/128 (cycle: 1 s)
111: φ/256 (cycle: 2 s)
Notes: 1. Only 0 can be written, to clear the flag.
2. When OVF is polled with the interval timer interrupt disabled, OVF = 1 must be read at
least twice.
Rev. 1.00, 05/04, page 227 of 544
11.4 Operation
11.4.1 Watchdog Timer Mode
To use the WDT as a watchdog timer, set the WT/IT bit and the TME bit in TCSR to 1. While the
WDT is used as a watchdog timer, if TCNT overflows without being rewritten because of a
system malfunction or another error, an internal reset or NMI interrupt request is generated. TCNT
does not overflow while the system is operating normally. Software must prevent TCNT
overflows by rewriting the TCNT value (normally be writing H'00) before overflows occurs.
If the RST/NMI bit of TCSR is set to 1, when the TCNT overflows, an internal reset signal for this
LSI is issued for 518 system clocks, and the low level signal is simultaneously output from the
RESO pin for 132 states, as shown in figure 11.2. If the RST/NMI bit is cleared to 0, when the
TCNT overflows, an NMI interrupt request is generated. Here, the output from the RESO pin
remains high.
An internal reset request from the watchdog timer and a reset input from the RES pin are
processed in the same vector. Reset source can be identified by the XRST bit status in SYSCR. If
a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a WDT
overflow, the RES pin reset has priority and the XRST bit in SYSCR is set to 1.
An NMI interrupt request from the watchdog timer and an interrupt request from the NMI pin are
processed in the same vector. Do not handle an NMI interrupt request from the watchdog timer
and an interrupt request from the NMI pin at the same time.
Rev. 1.00, 05/04, page 228 of 544
TCNT value
H'00 Time
H'FF
WT/IT = 1
TME = 1
Write H'00 to
TCNT
WT/IT = 1
TME = 1
Write H'00 to
TCNT
518 system clocks
Internal reset signal
[Legend]
WT/IT:
TME:
OVF:
Overflow
OVF = 1*
Timer mode select bit
Timer enable bit
Overflow flag
Note: * After the OVF bit becomes 1, it is cleared to 0 by an internal reset.
The XRST bit is also cleared to 0.
RESO signal
132 system clocks
RESO and internal
reset signals generated
Figure 11.2 Watchdog Timer Mode (RST/NMI = 1) Operation
Rev. 1.00, 05/04, page 229 of 544
11.4.2 Interval Timer Mode
When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each
time the TCNT overflows, as shown in figure 11.3. Therefore, an interrupt can be generated at
intervals.
When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is requested
at the same time the OVF bit of TCSR is set to 1. The timing is shown figure 11.4.
TCNT value
H'00 Time
H'FF
WT/IT = 0
TME = 1
WOVI
Overflow Overflow Overflow Overflow
[Legend]
WOVI : Internal timer interrupt request occurrence
WOVI WOVI WOVI
Figure 11.3 Interval Timer Mode Operation
φ
TCNT H'FF H'00
Overflow signal
(internal signal)
OVF
Figure 11.4 OVF Flag Set Timing
Rev. 1.00, 05/04, page 230 of 544
11.4.3 RESO Signal Output Timing
When TCNT overflows in watchdog timer mode, the OVF bit in TCSR is set to 1. When the
RST/NMI bit is 1 here, the internal reset signal is generated for the entire LSI. At the same time,
the low level signal is output from the RESO pin. The timing is shown in figure 11.5.
φ
TCNT H'FF H'00
132 states
518 states
Overflow signal
(internal signal)
OVF
RESO signal
Internal reset
signal
Figure 11.5 Output Timing of RESO signal
11.5 Interrupt Sources
During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI).
The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be
cleared to 0 in the interrupt handling routine.
When the NMI interrupt request is selected in watchdog timer mode, an NMI interrupt request is
generated by an overflow.
Table 11.2 WDT Interrupt Source
Name Interrupt Source Interrupt Flag
WOVI TCNT overflow OVF
Rev. 1.00, 05/04, page 231 of 544
11.6 Usage Notes
11.6.1 Notes on Register Access
The watchdog timer's registers, TCNT and TCSR differ from other registers in being more
difficult to write to. The procedures for writing to and reading from these registers are given
below.
Writing to TCNT and TCSR (Example of WDT_0): These registers must be written to by a
word transfer instruction. They cannot be written to by a byte transfer instruction.
TCNT and TCSR both have the same write address. Therefore, satisfy the relative condition
shown in figure 11.6 to write to TCNT or TCSR. To write to TCNT, the upper bytes must contain
the value H'5A and the lower bytes must contain the write data before the transfer instruction
execution. To write to TCSR, the upper bytes must contain the value H'A5 and the lower bytes
must contain the write data.
<TCNT write>
<TCSR write>
Address : H'FFA8
Address : H'FFA8
H'5A Write data
15 8 7 0
0
H'A5 Write data
15 8 7 0
0
Figure 11.6 Writing to TCNT and TCSR (WDT_0)
Reading from TCNT and TCSR (Example of WDT_0): These registers are read in the same
way as other registers. The read address is H'FFA8 for TCSR and H'FFA9 for TCNT.
Rev. 1.00, 05/04, page 232 of 544
11.6.2 Conflict between Timer Counter (TCNT) Write and Increment
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write
takes priority and the timer counter is not incremented. Figure 11.7 shows this operation.
Address
φ
Internal write signal
TCNT input clock
TCNT NM
T
1
T
2
TCNT write cycle
Counter write data
Figure 11.7 Conflict between TCNT Write and Increment
11.6.3 Changing Values of CKS2 to CKS0 Bits
If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in
the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before
changing the values of bits CKS2 to CKS0.
11.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode
If the mode is switched from watchdog timer to interval timer, while the WDT is operating, errors
could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME
bit to 0) before switching the mode.
Rev. 1.00, 05/04, page 233 of 544
11.6.5 System Reset by RESO Signal
Inputting the RESO output signal to the RESO pin of this LSI prevents the LSI from being
initialized correctly; the RESO signal must not be logically connected to the RES pin of the LSI.
To reset the entire system by the RESO signal, use the circuit as shown in figure 11.8.
RES
RESO
This LSI
Reset input
Reset signal for entire system
Figure 11.8 Sample Circuit for Resetting System by RESO Signal
11.6.6 Counter Values during Transitions between High-Speed, Sub-Active, and Watch
Modes
When developing a program with a program development tool (emulator), pay attention to the
followings.
When WDT_1 is used as a clock counter and is allowed to transit between high-speed mode and
sub-active or watch mode, the counter does not display the correct value due to internal clock
switching.
Specifically, when transiting from high-speed mode to sub-active or watch mode, that is, when the
control clock for WDT_1 switches from the main clock to the sub-clock, the counter incrementing
timing is delayed for approximately two to three clock cycles.
Similarly, when transiting from sub-active or watch mode to high-speed mode, the clock is not
supplied until stabilized internal oscillation is available because the main clock oscillator is halted
in sub-clock mode. The counter is therefore prevented from incrementing for the time specified by
the STS2 to STS0 bits in SBYCR after internal oscillation starts, thus producing counter value
differences for this time.
Special care must be taken when using WDT_1 as a clock counter. Note that no counter value
difference is produced while operated in the same mode.
Rev. 1.00, 05/04, page 234 of 544
SCI0022C_000020020800 Rev. 1.00, 05/04, page 235 of 544
Section 12 Serial Communication Interface (SCI)
This LSI has a serial communication interface (SCI). The SCI can handle both asynchronous and
clocked synchronous serial communication. Asynchronous serial data communication can be
carried out with standard asynchronous communication chips such as a Universal Asynchronous
Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). A
function is also provided for serial communication between processors (multiprocessor
communication function) in asynchronous mode.
12.1 Features
Choice of asynchronous or clocked synchronous serial communication mode
Full-duplex communication capability
The transmitter and receiver are mutually independent, enabling transmission and reception to
be executed simultaneously. Double-buffering is used in both the transmitter and the receiver,
enabling continuous transmission and continuous reception of serial data.
The on-chip baud rate generator allows any bit rate to be selected
An external clock can be selected as a transfer clock source.
Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data)
Four interrupt sources
Four interrupt sources — transmit-end, transmit-data-empty, receive-data-full, and receive
error — that can issue requests.
Asynchronous Mode:
Data length: 7 or 8 bits
Stop bit length: 1 or 2 bits
Parity: Even, odd, or none
Receive error detection: Parity, overrun, and framing errors
Break detection: Break can be detected by reading the RxD pin level directly in case of a
framing error
Clocked Synchronous Mode:
Data length: 8 bits
Receive error detection: Overrun errors
Serial data communication with other LSIs that have the clock synchronized communication
function
A block diagram of the SCI is shown in figure 12.1.
Rev. 1.00, 05/04, page 236 of 544
ExRxD*/RxD
ExTxD*/TxD
ExSCK*/SCK
Clock
φ
φ/4
φ/16
φ/64
TEI
TXI
RXI
ERI
SCMR
SSR
SCR
SMR
Transmission/
reception control
Baud rate
generator
BRR
Module data bus
RDR
TSRRSR
Parity generation
Parity check
[Legend]
RSR: Receive shift register
RDR: Receive data register
TSR: Transmit shift register
TDR: Transmit data register
SMR: Serial mode register
TDR
Bus interface
Internal data bus
External clock
SCR: Serial control register
SSR: Serial status register
SCMR: Smart card mode register
BRR: Bit rate register
Note: * The program development tool (emulator) does not support this function.
Figure 12.1 Block Diagram of SCI
12.2 Input/Output Pins
Table 12.1 shows the input/output pins for each SCI channel.
Table 12.1 Pin Configuration
Channel Symbol*1 Input/Output Function
SCK1/
ExSCK1*2
Input/Output Channel 1 clock input/output
RxD1/
ExRxD1*2
Input Channel 1 receive data input
1
TxD1/
ExTxD1*2
Output Channel 1 transmit data output
Notes: 1. Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the
channel designation.
2. The program development tool (emulator) does not support this function.
Rev. 1.00, 05/04, page 237 of 544
12.3 Register Descriptions
The SCI has the following registers.
Receive shift register (RSR)
Receive data register (RDR)
Transmit data register (TDR)
Transmit shift register (TSR)
Serial mode register (SMR)
Serial control register (SCR)
Serial status register (SSR)
Serial interface mode register (SCMR)
Bit rate register (BRR)
Serial pin select register (SPSR)*
Note: * The program development tool (emulator) does not support this function.
12.3.1 Receive Shift Register (RSR)
RSR is a shift register used to receive serial data that converts it into parallel data. When one
frame of data has been received, it is transferred to RDR automatically. RSR cannot be directly
accessed by the CPU.
12.3.2 Receive Data Register (RDR)
RDR is an 8-bit register that stores receive data. When the SCI has received one frame of serial
data, it transfers the received serial data from RSR to RDR where it is stored. After this, RSR can
receive the next data. Since RSR and RDR function as a double buffer in this way, continuous
receive operations can be performed. After confirming that the RDRF bit in SSR is set to 1, read
RDR for only once. RDR cannot be written to by the CPU. RDR is initialized to H'00.
12.3.3 Transmit Data Register (TDR)
TDR is an 8-bit register that stores transmit data. When the SCI detects that TSR is empty, it
transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered
structures of TDR and TSR enables continuous serial transmission. If the next transmit data has
already been written to TDR when one frame of data is transmitted, the SCI transfers the written
data to TSR to continue transmission. Although TDR can be read from or written to by the CPU at
all times, to achieve reliable serial transmission, write transmit data to TDR for only once after
confirming that the TDRE bit in SSR is set to 1. TDR is initialized to H'FF.
Rev. 1.00, 05/04, page 238 of 544
12.3.4 Transmit Shift Register (TSR)
TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first
transfers transmit data from TDR to TSR, then sends the data to the TxD pin. TSR cannot be
directly accessed by the CPU.
12.3.5 Serial Mode Register (SMR)
SMR is used to set the SCI's serial transfer format and select the on-chip baud rate generator clock
source.
Bit Bit Name
Initial
Value R/W Description
7 C/A 0 R/W Communication Mode
0: Asynchronous mode
1: Clocked synchronous mode
6 CHR 0 R/W Character Length (enabled only in asynchronous
mode)
0: Selects 8 bits as the data length.
1: Selects 7 bits as the data length. LSB-first is fixed
and the MSB of TDR is not transmitted in
transmission.
In clocked synchronous mode, a fixed data length of 8
bits is used.
5 PE 0 R/W Parity Enable (enabled only in asynchronous mode)
When this bit is set to 1, the parity bit is added to
transmit data before transmission, and the parity bit is
checked in reception. For a multiprocessor format,
parity bit addition and checking are not performed
regardless of the PE bit setting.
4 O/E 0 R/W Parity Mode (enabled only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity.
1: Selects odd parity.
3 STOP 0 R/W Stop Bit Length (enabled only in asynchronous mode)
Selects the stop bit length in transmission.
0: 1 stop bit
1: 2 stop bits
In reception, only the first stop bit is checked. If the
second stop bit is 0, it is treated as the start bit of the
next transmit frame.
Rev. 1.00, 05/04, page 239 of 544
Bit Bit Name
Initial
Value R/W Description
2 MP 0 R/W Multiprocessor Mode (enabled only in asynchronous
mode)
When this bit is set to 1, the multiprocessor
communication function is enabled. The PE bit and O/E
bit settings are invalid in multiprocessor mode.
1
0
CKS1
CKS0
0
0
R/W
R/W
Clock Select 1,0
These bits select the clock source for the on-chip baud
rate generator.
00: φ clock (n = 0)
01: φ/4 clock (n = 1)
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
For the relation between the bit rate register setting
and the baud rate, see section 12.3.9, Bit Rate
Register (BRR). n is the decimal display of the value of
n in BRR.
12.3.6 Serial Control Register (SCR)
SCR is a register that performs enabling or disabling of SCI transfer operations and interrupt
requests, and selection of the transfer clock source. For details on interrupt requests, refer to
section 12.7, Interrupt Sources.
Bit Bit Name
Initial
Value R/W Description
7 TIE 0 R/W Transmit Interrupt Enable
When this bit is set to 1, a TXI interrupt request is
enabled.
6 RIE 0 R/W Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt requests
are enabled.
5 TE 0 R/W Transmit Enable
When this bit is set to 1, transmission is enabled.
4 RE 0 R/W Receive Enable
When this bit is set to 1, reception is enabled.
Rev. 1.00, 05/04, page 240 of 544
Bit Bit Name
Initial
Value R/W Description
3 MPIE 0 R/W Multiprocessor Interrupt Enable (enabled only when the
MP bit in SMR is 1 in asynchronous mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of the
RDRF, FER, and ORER status flags in SSR is
disabled. On receiving data in which the multiprocessor
bit is 1, this bit is automatically cleared and normal
reception is resumed. For details, refer to section 12.5,
Multiprocessor Communication Function.
2 TEIE 0 R/W Transmit End Interrupt Enable
When this bit is set to 1, a TEI interrupt request is
enabled.
1
0
CKE1
CKE0
0
0
R/W
R/W
Clock Enable 1, 0
These bits select the clock source and SCK pin
function.
Asynchronous mode
00: Internal clock
(SCK pin functions as I/O port.)
01: Internal clock
(Outputs a clock of the same frequency as the bit
rate from the SCK pin.)
1X: External clock
(Inputs a clock with a frequency 16 times the bit
rate from the SCK pin.)
Clocked synchronous mode
0X: Internal clock (SCK pin functions as clock output.)
1X: External clock (SCK pin functions as clock input.)
[Legend]
X: Don't care
Rev. 1.00, 05/04, page 241 of 544
12.3.7 Serial Status Register (SSR)
SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE,
RDRF, ORER, PER, and FER can only be cleared.
Bit Bit Name
Initial
Value R/W Description
7 TDRE 1 R/(W)* Transmit Data Register Empty
Indicates whether TDR contains transmit data.
[Setting conditions]
When the TE bit in SCR is 0
When data is transferred from TDR to TSR and
TDR is ready for data write
[Clearing conditions]
When 0 is written to TDRE after reading TDRE = 1
6 RDRF 0 R/(W)* Receive Data Register Full
Indicates that receive data is stored in RDR.
[Setting condition]
When serial reception ends normally and receive
data is transferred from RSR to RDR
[Clearing conditions]
When 0 is written to RDRF after reading RDRF = 1
The RDRF flag is not affected and retains its previous
value when the RE bit in SCR is cleared to 0.
5 ORER 0 R/(W)* Overrun Error
[Setting condition]
When the next data is received while RDRF = 1
[Clearing condition]
When 0 is written to ORER after reading ORER = 1
4 FER 0 R/(W)* Framing Error
[Setting condition]
When the stop bit is 0
[Clearing condition]
When 0 is written to FER after reading FER = 1
In 2-stop-bit mode, only the first stop bit is checked.
Rev. 1.00, 05/04, page 242 of 544
Bit Bit Name
Initial
Value R/W Description
3 PER 0 R/(W)* Parity Error
[Setting condition]
When a parity error is detected during reception
[Clearing condition]
When 0 is written to PER after reading PER = 1
2 TEND 1 R Transmit End
[Setting conditions]
When the TE bit in SCR is 0
When TDRE = 1 at transmission of the last bit of a
1-byte serial transmit character
[Clearing conditions]
When 0 is written to TDRE after reading TDRE = 1
1 MPB 0 R Multiprocessor Bit
MPB stores the multiprocessor bit in the receive frame.
When the RE bit in SCR is cleared to 0 its previous
state is retained.
0 MPBT 0 R/W Multiprocessor Bit Transfer
MPBT stores the multiprocessor bit to be added to the
transmit frame.
Note: * Only 0 can be written, to clear the flag.
Rev. 1.00, 05/04, page 243 of 544
12.3.8 Serial Interface Mode Register (SCMR)
SCMR selects SCI functions and its format.
Bit Bit Name
Initial
Value R/W Description
7 to 4 All 1 R Reserved
These bits are always read as 1 and cannot be
modified.
3 SDIR 0 R/W Data Transfer Direction
Selects the serial/parallel conversion format.
0: TDR contents are transmitted with LSB-first.
Receive data is stored as LSB first in RDR.
1: TDR contents are transmitted with MSB-first.
Receive data is stored as MSB first in RDR.
The SDIR bit is valid only when the 8-bit data format is
used for transmission/reception; when the 7-bit data
format is used, data is always transmitted/received with
LSB-first.
2 SINV 0 R/W Data Invert
Specifies inversion of the data logic level. The SINV bit
does not affect the logic level of the parity bit. When
the parity bit is inverted, invert the O/E bit in SMR.
0: TDR contents are transmitted as they are. Receive
data is stored as it is in RDR.
1: TDR contents are inverted before being transmitted.
Receive data is stored in inverted form in RDR.
1 — 1 R Reserved
This bit is always read as 1 and cannot be modified.
0 SMIF 0 R/W Serial Communication Interface Mode Select:
0: Normal asynchronous or clocked synchronous mode
1: Reserved mode
Rev. 1.00, 05/04, page 244 of 544
12.3.9 Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 12.2 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and
clocked synchronous mode. The initial value of BRR is H'FF, and it can be read from or written to
by the CPU at all times.
Table 12.2 Relationships between N Setting in BRR and Bit Rate B
Mode Bit Rate Error
Asynchronous mode
B =
64 × 2 × (N + 1)
2n-1
φ × 106
Error (%) = {
B × 64 × 2 × (N + 1)
2n-1
φ × 10
6
- 1 } × 100
Clocked synchronous
mode
B =
64 × 2 × (N + 1)
2n-1
φ × 106
[Legend]
B: Bit rate (bit/s)
N: BRR setting for baud rate generator (0 N 255)
φ: Operating frequency (MHz)
n: Determined by the SMR settings shown in the following table.
SMR Setting
CKS1 CKS0 n
0 0 0
0 1 1
1 0 2
1 1 3
Table 12.3 shows sample N settings in BRR in normal asynchronous mode. Table 12.4 shows the
maximum bit rate settable for each frequency. Table 12.6 shows sample N settings in BRR in
clocked synchronous mode. Tables 12.5 and 12.7 show the maximum bit rates with external clock
input.
Rev. 1.00, 05/04, page 245 of 544
Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1)
Operating Frequency φ (MHz)
4 4.9152 5
Bit Rate
(bit/s) n N Error
(%) n N Error
(%) n N Error
(%)
110 2 70 0.03 2 86 0.31 2 88 –0.25
150 1 207 0.16 1 255 0.00 2 64 0.16
300 1 103 0.16 1 127 0.00 1 129 0.16
600 0 207 0.16 0 255 0.00 1 64 0.16
1200 0 103 0.16 0 127 0.00 0 129 0.16
2400 0 51 0.16 0 63 0.00 0 64 0.16
4800 0 25 0.16 0 31 0.00 0 32 –1.36
9600 0 12 0.16 0 15 0.00 0 15 1.73
19200 0 7 0.00 0 7 1.73
31250 0 3 0.00 0 4 –1.70 0 4 0.00
38400 0 3 0.00 0 3 1.73
[Legend]
—: Can be set, but there will be a degree of error.
Note: * Make the settings so that the error does not exceed 1%.
Rev. 1.00, 05/04, page 246 of 544
Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2)
Operating Frequency φ (MHz)
6 6.144 7.3728 8
Bit Rate
(bit/s) n N Error
(%) n N Error
(%) n N Error
(%) n N
Error
(%)
110 2 106 –0.44 2 108 0.08 2 130 –0.07 2 141 0.03
150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16
300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16
600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16
1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16
2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16
4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16
9600 0 19 –2.34 0 19 0.00 0 23 0.00 0 25 0.16
19200 0 9 –2.34 0 9 0.00 0 11 0.00 0 12 0.16
31250 0 5 0.00 0 5 2.40 0 7 0.00
38400 0 4 –2.34 0 4 0.00 0 5 0.00
Operating Frequency φ (MHz)
9.8304 10
Bit Rate
(bit/s) n N
Error
(%) n N Error
(%)
110 2 174 –0.26 2 177 –0.25
150 2 127 0.00 2 129 0.16
300 1 255 0.00 2 64 0.16
600 1 127 0.00 1 129 0.16
1200 0 255 0.00 1 64 0.16
2400 0 127 0.00 0 129 0.16
4800 0 63 0.00 0 64 0.16
9600 0 31 0.00 0 32 –1.36
19200 0 15 0.00 0 15 1.73
31250 0 9 –1.70 0 9 0.00
38400 0 7 0.00 0 7 1.73
[Legend]
—: Can be set, but there will be a degree of error.
Note: * Make the settings so that the error does not exceed 1%.
Rev. 1.00, 05/04, page 247 of 544
Table 12.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
φ (MHz)
Maximum
Bit Rate
(bit/s) n N φ (MHz)
Maximum
Bit Rate
(bit/s) n N
4 125000 0 0 9.8304 307200 0 0
4.9152 153600 0 0 10 312500 0 0
5 156250 0 0
6 187500 0 0
6.144 192000 0 0
7.3728 230400 0 0
8 250000 0 0
Table 12.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode)
φ (MHz) External Input
Clock (MHz) Maximum Bit
Rate (bit/s) φ (MHz) External Input
Clock (MHz) Maximum Bit
Rate (bit/s)
4 1.0000 62500 9.8304 2.4576 153600
4.9152 1.2288 76800 10 2.5000 156250
5 1.2500 78125
6 15.000 93750
6.144 1.5360 96000
7.3728 1.8432 115200
8 2.0000 125000
Rev. 1.00, 05/04, page 248 of 544
Table 12.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)
Operating Frequency φ (MHz)
4 8 10
Bit Rate
(bit/s) n N n N n N
110
250 2 249 3 124
500 2 124 2 249
1k 1 249 2 124
2.5k 1 99 1 199 1 249
5k 0 199 1 99 1 124
10k 0 99 0 199 0 249
25k 0 39 0 79 0 99
50k 0 19 0 39 0 49
100k 0 9 0 19 0 24
250k 0 3 0 7 0 9
500k 0 1* 0 3 0 4
1M 0 0 0 1
2.5M 0 0*
5M
[Legend]
Blank: Cannot be set.
—: Can be set, but there will be a degree of error.
*: Continuous transfer or reception is not possible.
Table 12.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)
φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s)
4 0.6667 666666.7
6 1.0000 1000000.0
8 1.3333 1333333.3
10 1.6667 1666666.7
Rev. 1.00, 05/04, page 249 of 544
12.3.10 Serial Pin Select Register (SPSR)
SPSR selects the serial I/O pins. SPSR should be set before initialization. Do not set during
communication.
Bit Bit
Name Initial
Value R/W Description
7 SPS1 0 R/W Serial Port Select
Selects the serial I/O pins.
0: P86/SCK1, P85/RxD1, P84/TxD1
1: P52/ExSCK1, P51/ExRxD1, P50/ExTxD1
6 to 0 All 0 R/W Reserved
The initial value should not be changed.
Note: The program development tool (emulator) does not support SPSR.
12.4 Operation in Asynchronous Mode
Figure 12.2 shows the general format for asynchronous serial communication. One frame consists
of a start bit (low level), followed by transmit/receive data, a parity bit, and finally stop bits (high
level). In asynchronous serial communication, the transmission line is usually held in the mark
state (high level). The SCI monitors the transmission line, and when it goes to the space state (low
level), recognizes a start bit and starts serial communication. Inside the SCI, the transmitter and
receiver are independent units, enabling full-duplex communication. Both the transmitter and the
receiver also have a double-buffered structure, so that data can be read or written during
transmission or reception, enabling continuous data transfer and reception.
LSB
Start
bit
MSB
Idle state
(mark state)
Stop bit
0
Transmit/receive data
D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1
11
Serial
data
Parity
bit
1 bit 1 or 2 bits7 or 8 bits 1 bit or
none
One unit of transfer data (character or frame)
Figure 12.2 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits)
Rev. 1.00, 05/04, page 250 of 544
12.4.1 Data Transfer Format
Table 12.8 shows the data transfer formats that can be used in asynchronous mode. Any of 12
transfer formats can be selected according to the SMR setting. For details on the multiprocessor
bit, refer to section 12.5, Multiprocessor Communication Function.
Table 12.8 Serial Transfer Formats (Asynchronous Mode)
PE
0
0
1
1
0
0
1
1
S 8-bit data
STOP
S 7-bit data
STOP
S 8-bit data
STOP STOP
S 8-bit data
PSTOP
S 7-bit data
STOP
P
S 8-bit data
MPB STOP
S 8-bit data
MPB STOP STOP
S 7-bit data
STOP
MPB
S 7-bit data
STOPMPB STOP
S 7-bit data
STOPSTOP
CHR
0
0
0
0
1
1
1
1
0
0
1
1
MP
0
0
0
0
0
0
0
0
1
1
1
1
STOP
0
1
0
1
0
1
0
1
0
1
0
1
SMR Settings
123456789101112
Serial Transmit/Receive Format and Frame Length
STOP
S 8-bit data
PSTOP
S 7-bit data
STOPPSTOP
Rev. 1.00, 05/04, page 251 of 544
12.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate.
In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs
internal synchronization. Since receive data is latched internally at the rising edge of the 8th pulse
of the basic clock, data is latched at the middle of each bit, as shown in figure 12.3. Thus the
reception margin in asynchronous mode is determined by formula (1) below.
M = (0.5 – ) – (1 + F) – (L – 0.5) F } × 100 [%] ... Formula (1)
2N
1
N
D – 0.5
[Legend]
M: Reception margin (%)
N : Ratio of bit rate to clock (N = 16)
D : Clock duty (D = 0.5 to 1.0)
L : Frame length (L = 9 to 12)
F : Absolute value of clock rate deviation
}
Assuming values of F = 0 and D = 0.5 in formula (1), the reception margin is determined by the
formula below.
M = {0.5 – 1/(2 × 16)} × 100 [%] = 46.875 %
However, this is only the computed value, and a margin of 20% to 30% should be allowed in
system design.
Internal
basic clock
16 clocks
8 clocks
Receive data
(RxD)
Synchronization
sampling timing
Start bit D0 D1
Data sampling
timing
15 0 7 15 00 7
Figure 12.3 Receive Data Sampling Timing in Asynchronous Mode
Rev. 1.00, 05/04, page 252 of 544
12.4.3 Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at
the SCK pin can be selected as the SCI's transfer clock, according to the setting of the C/A bit in
SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input at the SCK pin, the
clock frequency should be 16 times the bit rate used.
When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The
frequency of the clock output in this case is equal to the bit rate, and the phase is such that the
rising edge of the clock is in the middle of the transmit data, as shown in figure 12.4.
0
1 frame
D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1
SCK
TxD
Figure 12.4 Relation between Output Clock and Transmit Data Phase
(Asynchronous Mode)
Rev. 1.00, 05/04, page 253 of 544
12.4.4 SCI Initialization (Asynchronous Mode)
Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then
initialize the SCI as shown in figure 12.5. When the operating mode, transfer format, etc., is
changed, the TE and RE bits must be cleared to 0 before making the change using the following
procedure. When the TE bit is cleared to 0, the TDRE flag in SSR is set to 1. Note that clearing
the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and ORER flags in SSR,
or the contents of RDR. When an external clock is used in asynchronous mode, the clock must be
supplied even during initialization.
Wait
<Initialization completion>
Start initialization
Set data transfer/receive format in
SMR and SCMR
[1]
Set CKE1 and CKE0 bits in SCR
(TE and RE bits are 0)
No
Yes
Set value in BRR
Clear TE and RE bits in SCR to 0
[2]
[3]
Set TE and RE bits in
SCR to 1, and set RIE, TIE, TEIE,
and MPIE bits
[4]
1-bit interval elapsed?
[1] Set the clock selection in SCR.
Be sure to clear bits RIE, TIE,
TEIE, and MPIE, and bits TE and
RE, to 0.
When the clock is selected in
asynchronous mode, it is output
immediately after SCR settings are
made.
[2] Set the data transfer/receive format
in SMR and SCMR.
[3] Write a value corresponding to the
bit rate to BRR. Not necessary if
an external clock is used.
[4] Wait at least one bit interval, then
set the TE bit or RE bit in SCR to 1.
Also set the RIE, TIE, TEIE, and
MPIE bits.
Setting the TE and RE bits enables
the TxD and RxD pins to be used.
Figure 12.5 Sample SCI Initialization Flowchart
Rev. 1.00, 05/04, page 254 of 544
12.4.5 Data Transmission (Asynchronous Mode)
Figure 12.6 shows an example of the operation for transmission in asynchronous mode. In
transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR, and if it is cleared to 0, recognizes that data has been
written to TDR, and transfers the data from TDR to TSR.
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty interrupt
request (TXI) is generated. Because the TXI interrupt routine writes the next transmit data to
TDR before transmission of the current transmit data has finished, continuous transmission can
be enabled.
3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or
multiprocessor bit (may be omitted depending on the format), and stop bit.
4. The SCI checks the TDRE flag at the timing for sending the stop bit.
5. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then
serial transmission of the next frame is started.
6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the “mark
state” is entered in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI
interrupt request is generated.
Figure 12.7 shows a sample flowchart for transmission in asynchronous mode.
TDRE
TEND
0
1 frame
D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 1
11
DataStart
bit
Parity
bit
Stop
bit
Start
bit
Data Parity
bit
Stop
bit
TXI interrupt
request generated
Data written to TDR and
TDRE flag cleared to 0 in
TXI interrupt handling routine
TEI interrupt
request generated
Idle state
(mark state)
TXI interrupt
request generated
Figure 12.6 Example of SCI Transmit Operation in Asynchronous Mode (Example with 8-
Bit Data, Parity, One Stop Bit)
Rev. 1.00, 05/04, page 255 of 544
No
<End>
[1]
Yes
Initialization
Start transmission
Read TDRE flag in SSR [2]
Write transmit data to TDR
and clear TDRE flag in SSR to 0
No
Yes
No
Yes
Read TEND flag in SSR
[3]
No
Yes
[4]
Clear DR to 0 and
set DDR to 1
Clear TE bit in SCR to 0
TDRE = 1
All data transmitted?
TEND = 1
Break output?
[1] SCI initialization:
The TxD pin is automatically designated
as the transmit data output pin.
After the TE bit is set to 1, a frame of 1s
is output, and transmission is enabled.
[2] SCI status check and transmit data
write:
Read SSR and check that the TDRE flag
is set to 1, then write transmit data to
TDR and clear the TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission, read 1
from the TDRE flag to confirm that
writing is possible, then write data to
TDR, and clear the TDRE flag to 0.
[4] Break output at the end of serial
transmission:
To output a break in serial transmission,
set DDR for the port corresponding to
the TxD pin to 1, clear DR to 0, then
clear the TE bit in SCR to 0.
Figure 12.7 Sample Serial Transmission Flowchart
Rev. 1.00, 05/04, page 256 of 544
12.4.6 Serial Data Reception (Asynchronous Mode)
Figure 12.8 shows an example of the operation for reception in asynchronous mode. In serial
reception, the SCI operates as described below.
1. The SCI monitors the communication line, and if a start bit is detected, performs internal
synchronization, receives receive data in RSR, and checks the parity bit and stop bit.
2. If an overrun error (when reception of the next data is completed while the RDRF flag in SSR
is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this
time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF
flag remains to be set to 1.
3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to
RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated.
4. If a framing error (when the stop bit is 0) is detected, the FER bit in SSR is set to 1 and receive
data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt
request is generated.
5. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is
generated. Because the RXI interrupt routine reads the receive data transferred to RDR before
reception of the next receive data has finished, continuous reception can be enabled.
RDRF
FER
0
1 frame
D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 0
1 1
DataStart
bit
Parity
bit
Stop
bit
Start
bit
Data Parity
bit
Stop
bit
ERI interrupt request
generated by framing
error
Idle state
(mark state)
RDR data read and RDRF
flag cleared to 0 in RXI
interrupt handling routine
RXI interrupt
request
generated
Figure 12.8 Example of SCI Receive Operation in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit)
Table 12.9 shows the states of the SSR status flags and receive data handling when a receive error
is detected. If a receive error is detected, the RDRF flag retains its state before receiving data.
Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER,
FER, PER, and RDRF bits to 0 before resuming reception. Figure 12.9 shows a sample flow chart
for serial data reception.
Rev. 1.00, 05/04, page 257 of 544
Table 12.9 SSR Status Flags and Receive Data Handling
SSR Status Flag
RDRF* ORER FER PER Receive Data Receive Error Type
1 1 0 0 Lost Overrun error
0 0 1 0 Transferred to RDR Framing error
0 0 0 1 Transferred to RDR Parity error
1 1 1 0 Lost Overrun error + framing error
1 1 0 1 Lost Overrun error + parity error
0 0 1 1 Transferred to RDR Framing error + parity error
1 1 1 1 Lost Overrun error + framing error
+ parity error
Note: * The RDRF flag retains the state it had before data reception.
Yes
<End>
[1]
No
Initialization
Start reception
[2]
No
Yes
Read RDRF flag in SSR [4]
[5]
Clear RE bit in SCR to 0
Read ORER, PER, and
FER flags in SSR
Error processing
(Continued on next page)
[3]
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
Yes
PER FER ORER = 1
RDRF = 1
All data received?
[1] SCI initialization:
The RxD pin is automatically designated
as the receive data input pin.
[2] [3] Receive error processing and break
detection:
If a receive error occurs, read the ORER,
PER, and FER flags in SSR to identify the
error. After performing the appropriate
error processing, ensure that the ORER,
PER, and FER flags are all cleared to 0.
Reception cannot be resumed if any of
these flags are set to 1. In the case of a
framing error, a break can be detected by
reading the value of the input port
corresponding to the RxD pin.
[4] SCI status check and receive data read:
Read SSR and check that RDRF = 1, then
read the receive data in RDR and clear the
RDRF flag to 0. Transition of the RDRF
flag from 0 to 1 can also be identified by an
RXI interrupt.
[5] Serial reception continuation procedure:
To continue serial reception, before the
stop bit for the current frame is received,
read the RDRF flag, read RDR, and clear
the RDRF flag to 0.
[Legend]
: Logical OR
Figure 12.9 Sample Serial Reception Flowchart (1)
Rev. 1.00, 05/04, page 258 of 544
<End>
[3]
Error processing
Parity error processing
Yes
No
Clear ORER, PER, and
FER flags in SSR to 0
No
Yes
No
Yes
Framing error processing
No
Yes
Overrun error processing
ORER = 1
FER = 1
Break?
PER = 1
Clear RE bit in SCR to 0
Figure 12.9 Sample Serial Reception Flowchart (2)
Rev. 1.00, 05/04, page 259 of 544
12.5 Multiprocessor Communication Function
Use of the multiprocessor communication function enables data transfer to be performed among a
number of processors sharing communication lines by means of asynchronous serial
communication using the multiprocessor format, in which a multiprocessor bit is added to the
transfer data. When multiprocessor communication is carried out, each receiving station is
addressed by a unique ID code. The serial communication cycle consists of two component cycles:
an ID transmission cycle which specifies the receiving station, and a data transmission cycle for
the specified receiving station. The multiprocessor bit is used to differentiate between the ID
transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID
transmission cycle, and if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure
12.10 shows an example of inter-processor communication using the multiprocessor format. The
transmitting station first sends the ID code of the receiving station with which it wants to perform
serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data
with a 0 multiprocessor bit added. The receiving station skips data until data with a 1
multiprocessor bit is sent. When data with a 1 multiprocessor bit is received, the receiving station
compares that data with its own ID. The station whose ID matches then receives the data sent next.
Stations whose ID does not match continue to skip data until data with a 1 multiprocessor bit is
again received.
The SCI uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1,
transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags,
RDRF, FER, and ORER in SSR to 1 are prohibited until data with a 1 multiprocessor bit is
received. On reception of a receive character with a 1 multiprocessor bit, the MPB bit in SSR is set
to 1 and the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in
SCR is set to 1 at this time, an RXI interrupt is generated.
When the multiprocessor format is selected, the parity bit setting is invalid. All other bit settings
are the same as those in normal asynchronous mode. The clock used for multiprocessor
communication is the same as that in normal asynchronous mode.
Transmitting
station
Receiving
station A
Receiving
station B
Receiving
station C
Receiving
station D
(ID = 01) (ID = 02) (ID = 03) (ID = 04)
Serial communication line
Serial
data
ID transmission
cycle = receiving station
specification
Data transmission cycle =
Data transmission to
receiving station specified by ID
(MPB = 1) (MPB = 0)
H'01 H'AA
[Legend]
MPB: Multiprocessor bit
Figure 12.10 Example of Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A)
Rev. 1.00, 05/04, page 260 of 544
12.5.1 Multiprocessor Serial Data Transmission
Figure 12.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID
transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission
cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same
as those in asynchronous mode.
No
<End>
[1]
Yes
Initialization
Start transmission
Read TDRE flag in SSR [2]
Write transmit data to TDR and
set MPBT bit in SSR
No
Yes
No
Yes
Read TEND flag in SSR
[3]
No
Yes
[4]
Clear DR to 0 and set DDR to 1
Clear TE bit in SCR to 0
TDRE = 1
All data transmitted?
TEND = 1
Break output?
Clear TDRE flag to 0
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, a
frame of 1s is output, and
transmission is enabled.
[2] SCI status check and transmit
data write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR. Set the
MPBT bit in SSR to 0 or 1.
Finally, clear the TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission,
be sure to read 1 from the TDRE
flag to confirm that writing is
possible, then write data to TDR,
and then clear the TDRE flag to 0.
[4] Break output at the end of serial
transmission:
To output a break in serial
transmission, set port DDR to 1,
clear DR to 0, and then clear the
TE bit in SCR to 0.
Figure 12.11 Sample Multiprocessor Serial Transmission Flowchart
Rev. 1.00, 05/04, page 261 of 544
12.5.2 Multiprocessor Serial Data Reception
Figure 12.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit
in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data
with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is
generated at this time. All other SCI operations are the same as in asynchronous mode. Figure
12.12 shows an example of SCI operation for multiprocessor format reception.
MPIE
RDR
value
0 D0 D1 D7 1 1 0 D0 D1 D7 01
11
Data (ID1)Start
bit MPB
Stop
bit
Start
bit
Data (Data 1)
MPB
Stop
bit
Data (ID2)Start
bit
Stop
bit
Start
bit
Data (Data 2) Stop
bit
RXI interrupt
request
(multiprocessor
interrupt)
generated
Idle state
(mark state)
RDRF
RDR data read
and RDRF flag
cleared to 0 in
RXI interrupt
handling routine
If not this station’s ID,
MPIE bit is set to 1
again
RXI interrupt request is
not generated, and RDR
retains its state
ID1
(a) Data does not match station’s ID
MPIE
RDR
value
0 D0 D1 D7 1 1 0 D0 D1 D7 01
11
MPB MPB
RXI interrupt
request
(multiprocessor
interrupt)
generated
Idle state
(mark state)
RDRF
RDR data read and
RDRF flag cleared
to 0 in RXI interrupt
handling routine
Matches this station’s ID,
so reception continues, and
data is received in RXI
interrupt service routine
MPIE bit set to 1
again
ID2
(b) Data matches station’s ID
Data 2ID1
MPIE = 0
MPIE = 0
Figure 12.12 Example of SCI Receive Operation (Example with 8-Bit Data, Multiprocessor
Bit, One Stop Bit)
Rev. 1.00, 05/04, page 262 of 544
Yes
<End>
[1]
No
Initialization
Start reception
No
Yes
[4]
Clear RE bit in SCR to 0
Error processing
(Continued on
next page)
[5]
No
Yes
FER ORER = 1
RDRF = 1
All data received?
Set MPIE bit in SCR to 1 [2]
Read ORER and FER flags in SSR
Read RDRF flag in SSR [3]
Read receive data in RDR
No
Yes
This station’s ID?
Read ORER and FER flags in SSR
Yes
No
Read RDRF flag in SSR
No
Yes
FER ORER = 1
Read receive data in RDR
RDRF = 1
[1] SCI initialization:
The RxD pin is automatically designated as
the receive data input pin.
[2] ID reception cycle:
Set the MPIE bit in SCR to 1.
[3] SCI status check, ID reception and
comparison:
Read SSR and check that the RDRF flag is
set to 1, then read the receive data in RDR
and compare it with this station’s ID.
If the data is not this station’s ID, set the MPIE
bit to 1 again, and clear the RDRF flag to 0.
If the data is this station’s ID, clear the RDRF
flag to 0.
[4] SCI status check and data reception:
Read SSR and check that the RDRF flag is
set to 1, then read the data in RDR.
[5] Receive error processing and break detection:
If a receive error occurs, read the ORER and
FER flags in SSR to identify the error. After
performing the appropriate error processing,
ensure that the ORER and FER flags are all
cleared to 0.
Reception cannot be resumed if either of
these flags is set to 1.
In the case of a framing error, a break can be
detected by reading the RxD pin value.
[Legend]
: Logical OR
Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (1)
Rev. 1.00, 05/04, page 263 of 544
<End>
Error processing
Yes
No
Clear ORER, PER, and
FER flags in SSR to 0
No
Yes
No
Yes
Framing error processing
Overrun error processing
ORER = 1
FER = 1
Break?
Clear RE bit in SCR to 0
[5]
Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (2)
Rev. 1.00, 05/04, page 264 of 544
12.6 Operation in Clocked Synchronous Mode
Figure 12.14 shows the general format for clocked synchronous communication. In clocked
synchronous mode, data is transmitted or received in synchronization with clock pulses. One
character in transfer data consists of 8-bit data. In data transmission, the SCI outputs data from one
falling edge of the synchronization clock to the next. In data reception, the SCI receives data in
synchronization with the rising edge of the synchronization clock. After 8-bit data is output, the
transmission line holds the MSB state. In clocked synchronous mode, no parity or multiprocessor
bit is added. Inside the SCI, the transmitter and receiver are independent units, enabling full-
duplex communication by use of a common clock. Both the transmitter and the receiver also have
a double-buffered structure, so that the next transmit data can be written during transmission or the
previous receive data can be read during reception, enabling continuous data transfer.
Don’t
care
Don’t
care
One unit of transfer data (character or frame)
Bit 0
Serial data
Synchronization
clock
Bit 1 Bit 3 Bit 4 Bit 5
LSB MSB
Bit 2 Bit 6 Bit 7
*
*
Note: * High except in continuous transfer/reception
Figure 12.14 Data Format in Clocked Synchronous Communication (LSB-First)
12.6.1 Clock
Either an internal clock generated by the on-chip baud rate generator or an external
synchronization clock input at the SCK pin can be selected, according to the setting of the CKE1
and CKE0 bits in SCR. When the SCI is operated on an internal clock, the synchronization clock
is output from the SCK pin. Eight synchronization clock pulses are output in the transfer of one
character, and when no transfer is performed the clock is fixed high.
Rev. 1.00, 05/04, page 265 of 544
12.6.2 SCI Initialization (Clocked Synchronous Mode)
Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then
initialize the SCI as described in a sample flowchart in figure 12.15. When the operating mode,
transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the
change using the following procedure. When the TE bit is cleared to 0, the TDRE flag in SSR is
set to 1. However, clearing the RE bit to 0 does not initialize the RDRF, PER, FER, and ORER
flags in SSR, or RDR.
Wait
<Transfer start>
Start initialization
Set data transfer/receive format in
SMR and SCMR
No
Yes
Set value in BRR
Clear TE and RE bits in SCR to 0
[2]
[3]
Set TE and RE bits in SCR to 1, and
set RIE, TIE, TEIE, and MPIE bits [4]
1-bit interval elapsed?
Set CKE1 and CKE0 bits in SCR
(TE and RE bits are 0) [1]
[1] Set the clock selection in SCR. Be sure
to clear bits RIE, TIE, TEIE, and MPIE,
TE and RE to 0.
[2] Set the data transfer/receive format in
SMR and SCMR.
[3] Write a value corresponding to the bit
rate to BRR. This step is not necessary
if an external clock is used.
[4] Wait at least one bit interval, then set the
TE bit or RE bit in SCR to 1.
Also set the RIE, TIE TEIE, and MPIE
bits.
Setting the TE and RE bits enables the
TxD and RxD pins to be used.
Note: * In simultaneous transmit and receive operations, the TE and RE bits should both
be cleared
Figure 12.15 Sample SCI Initialization Flowchart
Rev. 1.00, 05/04, page 266 of 544
12.6.3 Serial Data Transmission (Clocked Synchronous Mode)
Figure 12.16 shows an example of SCI operation for transmission in clocked synchronous mode.
In serial transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to
TDR, and transfers the data from TDR to TSR.
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission. If the TIE bit in SCR is set to 1 at this time, a TXI interrupt request is generated.
Because the TXI interrupt routine writes the next transmit data to TDR before transmission of
the current transmit data has finished, continuous transmission can be enabled.
3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock
mode has been specified and synchronized with the input clock when use of an external clock
has been specified.
4. The SCI checks the TDRE flag at the timing for sending the last bit.
5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission
of the next frame is started.
6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TxD pin maintains the
output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request
is generated. The SCK pin is fixed high.
Figure 12.17 shows a sample flow chart for serial data transmission. Even if the TDRE flag is
cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1.
Make sure to clear the receive error flags to 0 before starting transmission. Note that clearing the
RE bit to 0 does not clear the receive error flags.
Transfer direction
Bit 0
Serial data
Synchronization
clock
1 frame
TDRE
TEND
Data written to TDR
and TDRE flag cleared
to 0 in TXI interrupt
handling routine
TXI interrupt
request generated
Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
TXI interrupt
request generated
TEI interrupt request
generated
Figure 12.16 Example of SCI Transmit Operation in Clocked Synchronous Mode
Rev. 1.00, 05/04, page 267 of 544
No
<End>
[1]
Yes
Initialization
Start transmission
Read TDRE flag in SSR [2]
Write transmit data to TDR and
clear TDRE flag in SSR to 0
No
Yes
No
Yes
Read TEND flag in SSR
[3]
Clear TE bit in SCR to 0
TDRE = 1
All data transmitted?
TEND = 1
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data output
pin.
[2] SCI status check and transmit data
write:
Read SSR and check that the TDRE
flag is set to 1, then write transmit data
to TDR and clear the TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
Figure 12.17 Sample Serial Transmission Flowchart
Rev. 1.00, 05/04, page 268 of 544
12.6.4 Serial Data Reception (Clocked Synchronous Mode)
Figure 12.18 shows an example of SCI operation for reception in clocked synchronous mode. In
serial reception, the SCI operates as described below.
1. The SCI performs internal initialization in synchronization with a synchronization clock input
or output, starts receiving data, and stores the receive data in RSR.
2. If an overrun error (when reception of the next data is completed while the RDRF flag is still
set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time,
an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag
remains to be set to 1.
3. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is
generated. Because the RXI interrupt routine reads the receive data transferred to RDR before
reception of the next receive data has finished, continuous reception can be enabled.
Bit 7
Serial data
Synchronization
clock
1 frame
RDRF
ORER
ERI interrupt request
generated by overrun
error
RXI interrupt
request generated
RDR data read and
RDRF flag cleared
to 0 in RXI interrupt
handling routine
RXI interrupt
request
generated
Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
Figure 12.18 Example of SCI Receive Operation in Clocked Synchronous Mode
Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER,
FER, PER, and RDRF bits to 0 before resuming reception. Figure 12.19 shows a sample flowchart
for serial data reception.
Rev. 1.00, 05/04, page 269 of 544
Yes
<End>
[1]
No
Initialization
Start reception
[2]
No
Yes
Read RDRF flag in SSR [4]
[5]
Clear RE bit in SCR to 0
Error processing
(Continued below)
[3]
Read receive data in RDR and
clear RDRF flag in SSR to 0
No
Yes
ORER = 1
RDRF = 1
All data received?
Read ORER flag in SSR
<End>
Error processing
Overrun error processing
Clear ORER flag in SSR to 0
[3]
[1] SCI initialization:
The RxD pin is automatically
designated as the receive data input
pin.
[2] [3] Receive error processing:
If a receive error occurs, read the
ORER flag in SSR, and after
performing the appropriate error
processing, clear the ORER flag to 0.
Transfer cannot be resumed if the
ORER flag is set to 1.
[4] SCI status check and receive data
read:
Read SSR and check that the RDRF
flag is set to 1, then read the receive
data in RDR and clear the RDRF flag
to 0.
Transition of the RDRF flag from 0 to
1 can also be identified by an RXI
interrupt.
[5] Serial reception continuation
procedure:
Figure 12.19 Sample Serial Reception Flowchart
12.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous
Mode)
Figure 12.20 shows a sample flowchart for simultaneous serial transmit and receive operations.
After initializing the SCI, the following procedure should be used for simultaneous serial data
transmit and receive operations. To switch from transmit mode to simultaneous transmit and
receive mode, check that the SCI has finished transmission and the TDRE and TEND flags in SSR
are set to 1, clear the TE bit in SCR to 0, and then set the TE and RE bits to 1 simultaneously with
a single instruction. To switch from receive mode to simultaneous transmit and receive mode,
check that the SCI has finished reception, and clear the RE bit to 0. Then after checking that the
RDRF bit in SSR and receive error flags (ORER, FER, and PER) are cleared to 0, set the TE and
RE bits to 1 simultaneously with a single instruction.
Rev. 1.00, 05/04, page 270 of 544
Yes
<End>
[1]
No
Initialization
Start transmission/reception
[5]
Error processing
[3]
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
Yes
ORER = 1
All data received?
[2]
Read TDRE flag in SSR
No
Yes
TDRE = 1
Write transmit data to TDR and
clear TDRE flag in SSR to 0
No
Yes
RDRF = 1
Read ORER flag in SSR
[4]
Read RDRF flag in SSR
Clear TE and RE bits in SCR to 0
[1] SCI initialization:
The TxD pin is designated as the
transmit data output pin, and the
RxD pin is designated as the
receive data input pin, enabling
simultaneous transmit and
receive operations.
[2] SCI status check and transmit
data write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR and clear
the TDRE flag to 0.
Transition of the TDRE flag from
0 to 1 can also be identified by a
TXI interrupt.
[3] Receive error processing:
If a receive error occurs, read the
ORER flag in SSR, and after
performing the appropriate error
processing, clear the ORER flag
to 0. Transmission/reception
cannot be resumed if the ORER
flag is set to 1.
[4] SCI status check and receive
data read:
Read SSR and check that the
RDRF flag is set to 1, then read
the receive data in RDR and clear
the RDRF flag to 0. Transition of
the RDRF flag from 0 to 1 can
also be identified by an RXI
interrupt.
[5] Serial transmission/reception
continuation procedure:
To continue serial transmission/
reception, before the MSB (bit 7)
of the current frame is received,
finish reading the RDRF flag,
reading RDR, and clearing the
RDRF flag to 0. Also, before the
MSB (bit 7) of the current frame is
transmitted, read 1 from the
Note: * When switching from transmit or receive operation to simultaneous transmit and receive operations,
first clear the TE bit and RE bit to 0, then set both these bits to 1 simultaneously.
Figure 12.20 Sample Flowchart of Simultaneous Serial Transmission and Reception
Rev. 1.00, 05/04, page 271 of 544
12.7 Interrupt Sources
Table 12.10 shows the interrupt sources in serial communication interface. A different interrupt
vector is assigned to each interrupt source, and individual interrupt sources can be enabled or
disabled using the enable bits in SCR.
When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag
in SSR is set to 1, a TEI interrupt request is generated.
When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER,
PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated.
A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. If a TEI
interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt has priority for
acceptance. However, note that if the TDRE and TEND flags are cleared simultaneously by the
TXI interrupt routine, the SCI cannot branch to the TEI interrupt routine later.
Table 12.10 SCI Interrupt Sources
Channel Name Interrupt Source Interrupt Flag Priority
ERI1 Receive error ORER, FER, PER
RXI1 Receive data full RDRF
TXI1 Transmit data empty TDRE
High
1
TEI1 Transmit end TEND Low
Rev. 1.00, 05/04, page 272 of 544
12.8 Usage Notes
12.8.1 Module Stop Mode Setting
SCI operation can be disabled or enabled using the module stop control register. The initial setting
is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For
details, refer to section 20, Power-Down Modes.
12.8.2 Break Detection and Processing
When framing error detection is performed, a break can be detected by reading the RxD pin value
directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag in SSR is set,
and the PER flag may also be set. Note that, since the SCI continues the receive operation even
after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again.
12.8.3 Mark State and Break Detection
When the TE bit in SCR is 0, the TxD pin is used as an I/O port whose direction (input or output)
and level are determined by DR and DDR of the port. This can be used to set the TxD pin to the
mark state (high level) or send a break during serial data transmission. To maintain the
communication line at mark state until TE is set to 1, set both DDR and DR to 1. Since the TE bit
is cleared to 0 at this point, the TxD pin becomes an I/O port, and 1 is output from the TxD pin. To
send a break during serial transmission, first set DDR to 1 and DR to 0, and then clear the TE bit
to 0. When the TE bit is cleared to 0, the transmitter is initialized regardless of the current
transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin.
12.8.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
Transmission cannot be started when a receive error flag (ORER, FER, or RER) is SSR is set to 1,
even if the TDRE flag in SSR is cleared to 0. Be sure to clear the receive error flags to 0 before
starting transmission. Note also that the receive error flags cannot be cleared to 0 even if the RE
bit in SCR is cleared to 0.
12.8.5 Relation between Writing to TDR and TDRE Flag
Data can be written to TDR irrespective of the TDRE flag status in SSR. However, if the new
data is written to TDR when the TDRE flag is 0, that is, when the previous data has not been
transferred to TSR yet, the previous data in TDR is lost. Be sure to write transmit data to TDR
after verifying that the TDRE flag is set to 1.
Rev. 1.00, 05/04, page 273 of 544
12.8.6 SCI Operations during Mode Transitions
Transmission: Before making a transition to module stop, software standby, or sub-sleep mode,
stop all transmit operations (TE = TIE = TEIE = 0). TSR, TDR, and SSR are reset. The states of
the output pins during each mode depend on the port settings, and the pins output a high-level
signal after mode cancellation. If a transition is made during data transmission, the data being
transmitted will be undefined.
To transmit data in the same transmission mode after mode cancellation, set TE to 1, read SSR,
write to TDR, clear TDRE in this order, and then start transmission. To transmit data in a
different transmission mode, initialize the SCI first.
Figure 12.21 shows a sample flowchart for mode transition during transmission. Figures 12.22
and 12.23 show the pin states during transmission.
Reception: Before making a transition to module stop, software standby, watch, sub-active, or
sub-sleep mode, stop reception (RE = 0). RSR, RDR, and SSR are reset. If a transition is made
during data reception, the data being received will be invalid.
To receive data in the same reception mode after mode cancellation, set RE to 1, and then start
reception. To receive data in a different reception mode, initialize the SCI first.
Figure 12.24 shows a sample flowchart for mode transition during reception.
Rev. 1.00, 05/04, page 274 of 544
Start transmission
Transmission
[1]
No
No
No
Yes
Yes
Yes
Read TEND flag in SSR
Make transition to software standby mode etc.
Cancel software standby mode etc.
TE = 0
Initialization TE = 1
[2]
[3]
All data transmitted?
Change operating mode?
TEND = 1
[1] Data being transmitted is lost
halfway. Data can be normally
transmitted from the CPU by
setting TE to 1, reading SSR,
writing to TDR, and clearing
TDRE to 0 after mode
cancellation.
[2] Also clear TIE and TEIE to 0
when they are 1.
[3] Module stop, watch, sub-active,
and sub-sleep modes are
included.
Figure 12.21 Sample Flowchart for Mode Transition during Transmission
TE bit
SCK
output pin
TxD
output pin
Port
input/output
Port input/output
Port
input/output
Start Stop High outputHigh output
Transmission start Transmission end
Transition to
software standby
mode
Software standby
mode cancelled
SCI TxD output
Port Port SCI
TxD output
Figure 12.22 Pin States during Transmission in Asynchronous Mode (Internal Clock)
Rev. 1.00, 05/04, page 275 of 544
TE bit
SCK
output pin
TxD
output pin Port input/output
Port
input/output
Port
input/output High output*Marking output
Transmission start Transmission end
Transition to
software standby
mode
Software standby
mode cancelled
SCI TxD output
Port Port SCI
TxD output
Last TxD bit retained
Note: * Initialized in software standby mode
Figure 12.23 Pin States during Transmission in Clocked Synchronous Mode
(Internal Clock)
Start reception
Reception
[1]
No
No
Yes
Yes
Read receive data in RDR
Read RDRF flag in SSR
Make transition to software
standby mode etc.
Cancel software standby mode etc.
RE = 0
Initialization RE = 1
[2]
Change operating mode?
RDRF = 1 [1] Data being received will be invalid.
[2] Module stop, watch, sub-active, and
sub-sleep modes are included
Figure 12.24 Sample Flowchart for Mode Transition during Reception
Rev. 1.00, 05/04, page 276 of 544
12.8.7 Switching from SCK Pins to Port Pins
When SCK pins are switched to port pins after transmission has completed, pins are enabled for
port output after outputting a low pulse of half a cycle as shown in figure 12.25.
SCK/Port
CKE0
CKE1
C/A
TE
Data
1. Transmission end
2. TE = 0
3. C/A = 0
4. Low pulse output
Bit 6 Bit 7
Low pulse of half a cycle
Figure 12.25 Switching from SCK Pins to Port Pins
To prevent the low pulse output that is generated when switching the SCK pins to the port pins,
specify the SCK pins for input (pull up the SCK/port pins externally), and follow the procedure
below with DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE1 = 0, and TE = 1.
1. End serial data transmission
2. TE bit = 0
3. CKE1 bit = 1
4. C/A bit = 0 (switch to port output)
5. CKE1 bit = 0
SCK/Port
CKE0
CKE1
C/A
TE
Data
1. Transmission end
2. TE = 0
4. C/A = 0
3. CKE1 = 1 5. CKE1 = 0
Bit 6 Bit 7
High output
Figure 12.26 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins
IFIIC60B_010020040200 Rev. 1.00, 05/04, page 277 of 544
Section 13 I2C Bus Interface (IIC)
This LSI has a two-channel I2C bus interface. The I2C bus interface conforms to and provides a
subset of the Philips I2C bus (inter-IC bus) interface functions. The register configuration that
controls the I2C bus differs partly from the Philips configuration, however.
13.1 Features
Selection of addressing format or non-addressing format
I2C bus format: addressing format with an acknowledge bit, for master/slave operation
Clocked synchronous serial format: non-addressing format without an acknowledge bit, for
master operation only
Conforms to Philips I2C bus interface (I2C bus format)
Two ways of setting slave address (I2C bus format)
Start and stop conditions generated automatically in master mode (I2C bus format)
Selection of the acknowledge output level in reception (I2C bus format)
Automatic loading of an acknowledge bit in transmission (I2C bus format)
Wait function in master mode (I2C bus format)
A wait can be inserted by driving the SCL pin low after data transfer, excluding
acknowledgement.
The wait can be cleared by clearing the interrupt flag.
Wait function (I2C bus format)
A wait request can be generated by driving the SCL pin low after data transfer.
The wait request is cleared when the next transfer becomes possible.
Interrupt sources
Data transfer end (including when a transition to transmit mode with I2C bus format occurs,
when ICDR data is transferred, or during a wait state)
Address match: When any slave address matches or the general call address is received in
slave receive mode with I2C bus format (including address reception after loss of master
arbitration)
Start condition detection (in master mode)
Stop condition detection (in slave mode)
Selection of 16 internal clocks (in master mode)
Direct bus drive (SCL/SDA pin)
Eight pins—P52/SCL0, P97/SDA0, P86/SCL1, P42/SDA1, PG4/ExSDAA, PG5/ExSCLA,
PG6/ExSDAB, and PG7/ExSCLB—(normally NMOS push-pull outputs) function as
NMOS open-drain outputs when the bus drive function is selected.
Rev. 1.00, 05/04, page 278 of 544
Selectable input/output pins*
Pins, PG4/ExSDAA, PG5/ExSCLA, PG6/ExSDAB, and PG7/ExSCLB, are selectable for
the I2C bus input/output pin in each channel.
Note: * The program development tool (emulator) does not support this function.
Figure 13.1 shows a block diagram of the I2C bus interface. Figure 13.2 shows an example of I/O
pin connections to external circuits. Since I2C bus interface I/O pins are different in structure from
normal port pins, they have different specifications for permissible applied voltages. For details,
see section 22, Electrical Characteristics.
φ
SCL
PS
Noise
canceler
Bus state
decision
circuit
Arbitration
decision
circuit
Output data
control
circuit
ICCR
Clock
control
ICXR
ICMR
ICSR
PGCTL
ICDRS
Address
comparator
SAR, SARX
SDA
Noise
canceler
Interrupt
generator Interrupt
request
Internal data bus
ICDRR
ICDRT
[Legend]
ICCR:
ICMR:
ICSR:
ICDR:
ICXR:
SAR:
SARX:
PS:
PGCTL:
I2C bus control register
I2C bus mode register
I2C bus status register
I2C bus data register
I2C bus extended control register
Slave address register
Slave address register X
Prescaler
Port G control register
ExSCLA*
ExSCLB*
ExSDAA*
ExSDAB*
Pin
selection
circuit
Pin
selection
circuit
Note: * The program development tool (emulator) does not support this function.
Figure 13.1 Block Diagram of I2C Bus Interface
Rev. 1.00, 05/04, page 279 of 544
SCL
in
SCL
out
SDA
in
SDA
out
(Slave 1)
SCL
SDA
SCL
in
SCL
out
SDA
in
SDA
out
(Slave 2)
SCL
SDA
SCL
in
SCL
out
SDA
in
SDA
out
(Master)
This LSI
SCL
SDA
V
CC
V
CC
SCL
SDA
V
DD
Figure 13.2 I2C Bus Interface Connections (Example: This LSI as Master)
Rev. 1.00, 05/04, page 280 of 544
13.2 Input/Output Pins
Table 13.1 summarizes the input/output pins used by the I2C bus interface. The serial clock I/O pin
for each channel can be selected from the three pins*. The serial data I/O pin for each channel can
be selected form the three pins*. Do not set multiple pins as the serial clock I/O pin or serial data
I/O pin for a single channel.
Note: * The program development tool (emulator) does not support this function.
Table 13.1 Pin Configuration
Channel Symbol*1 Input/Output Function
SCL0 Input/Output Serial clock input/output pin of IIC_0 0
SDA0 Input/Output Serial data input/output pin of IIC_0
SCL1 Input/Output Serial clock input/output pin of IIC_1 1
SDA1 Input/Output Serial data input/output pin of IIC_1
ExSCLA*2 Input/Output Serial clock input/output pin of IIC_0 or IIC_1
ExSDAA*2 Input/Output Serial data input/output pin of IIC_0 or IIC_1
ExSCLB*2 Input/Output Serial clock input/output pin of IIC_0 or IIC_1
ExSDAB*2 Input/Output Serial data input/output pin of IIC_0 or IIC_1
Notes: 1. In the text, the channel subscript is omitted, and only SCL and SDA are used.
2. The program development tool (emulator) does not support this function.
Rev. 1.00, 05/04, page 281 of 544
13.3 Register Descriptions
The I2C bus interface has the following registers. Registers ICDR and SARX and registers ICMR
and SAR are allocated to the same addresses. Accessible registers differ depending on the ICE bit
in ICCR. When the ICE bit is cleared to 0, SAR and SARX can be accessed, and when the ICE bit
is set to 1, ICMR and ICDR can be accessed. For details on the serial timer control register, see
section 3.2.3, Serial Timer Control Register (STCR).
I2C bus data register (ICDR)
Slave address register (SAR)
Second slave address register (SARX)
I2C bus mode register (ICMR)
I2C bus control register (ICCR)
I2C bus status register (ICSR)
DDC switch register (DDCSWR)*1
I2C bus extended control register (ICXR)
Port G control register (PGCTL)*2
Notes: 1. DDCSWR is available only for IIC_0.
2. PGCTL register is common to IIC_0 and IIC_1.
Rev. 1.00, 05/04, page 282 of 544
13.3.1 I2C Bus Data Register (ICDR)
ICDR is an 8-bit readable/writable register that is used as a transmit data register when
transmitting and a receive data register when receiving. ICDR is internally divided into a shift
register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). Data transfers among
these three registers are performed automatically in accordance with changes in the bus state, and
they affect the status of internal flags such as ICDRE and ICDRF.
In master transmit mode with the I2C bus format, writing transmit data to ICDR should be
performed after start condition detection. When the start condition is detected, previous write data
is ignored. In slave transmit mode, writing should be performed after the slave addresses match
and the TRS bit is automatically changed to 1.
If the IIC is in transmit mode (TRS = 1) and ICDRT has the next transmit data (the ICDRE flag
is 0) after successful transmission/reception of one frame of data using ICDRS, data is transferred
automatically from ICDRT to ICDRS.
If the IIC is in transmit mode (TRS = 1) and ICDRT has the next data (the ICDRE flag is 0), data
is transferred automatically from ICDRT to ICDRS, following transmission of one frame of data
using ICDRS. When the ICDRE flag is 1 and the next transmit data writing is waited, data is
transferred automatically from ICDRT to ICDRS by writing to ICDR. If I2C is in receive mode
(TRS = 0), no data is transferred from ICDRT to ICDRS. Note that data should not be written to
ICDR in receive mode.
Reading receive data from ICDR is performed after data is transferred from ICDRS to ICDRR.
If I2C is in receive mode and no previous data remains in ICDRR (the ICDRF flag is 0), data is
transferred automatically from ICDRS to ICDRR, following reception of one frame of data using
ICDRS. If additional data is received while the ICDRF flag is 1, data is transferred automatically
from ICDRS to ICDRR by reading from ICDR. In transmit mode, no data is transferred from
ICDRS to ICDRR. Always set I2C to receive mode before reading from ICDR.
If the number of bits in a frame, excluding the acknowledge bit, is less than eight, transmit data
and receive data are stored differently. Transmit data should be written justified toward the MSB
side when MLS = 0 in ICMR, and toward the LSB side when MLS = 1. Receive data bits should
be read from the LSB side when MLS = 0, and from the MSB side when MLS = 1.
ICDR can be written to and read from only when the ICE bit is set to 1 in ICCR. The initial value
of ICDR is undefined.
Rev. 1.00, 05/04, page 283 of 544
13.3.2 Slave Address Register (SAR)
SAR sets the slave address and selects the communication format. If the LSI is in slave mode with
the I2C bus format selected, when the FS bit is set to 0 and the upper 7 bits of SAR match the
upper 7 bits of the first frame received after a start condition, the LSI operates as the slave device
specified by the master device. SAR can be accessed only when the ICE bit in ICCR is cleared
to 0.
Bit Bit Name Initial Value R/W Description
7
6
5
4
3
2
1
SVA6
SVA5
SVA4
SVA3
SVA2
SVA1
SVA0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Slave Address 6 to 0
Set a slave address.
0 FS 0 R/W Format Select
Selects the communication format together with the FSX bit
in SARX. See table 13.2.
This bit should be set to 0 when general call address
recognition is performed.
Rev. 1.00, 05/04, page 284 of 544
13.3.3 Second Slave Address Register (SARX)
SARX sets the second slave address and selects the communication format. If the LSI is in slave
mode with the I2C bus format selected, when the FSX bit is set to 0 and the upper 7 bits of SARX
match the upper 7 bits of the first frame received after a start condition, the LSI operates as the
slave device specified by the master device. SARX can be accessed only when the ICE bit in
ICCR is cleared to 0.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
SVAX6
SVAX5
SVAX4
SVAX3
SVAX2
SVAX1
SVAX0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Second Slave Address 6 to 0
Set the second slave address.
0 FSX 1 R/W Format Select X
Selects the communication format together with the FS
bit in SAR. See table 13.2.
Rev. 1.00, 05/04, page 285 of 544
Table 13.2 Communication Format
SAR SARX
FS FSX Operating Mode
0 0 I2C bus format
SAR and SARX slave addresses recognized
General call address recognized
1 I2C bus format
SAR slave address recognized
SARX slave address ignored
General call address recognized
1 0 I2C bus format
SAR slave address ignored
SARX slave address recognized
General call address ignored
1 Clocked synchronous serial format
SAR and SARX slave addresses ignored
General call address ignored
I2C bus format: addressing format with an acknowledge bit
Clocked synchronous serial format: non-addressing format without an acknowledge bit, for
master mode only
Rev. 1.00, 05/04, page 286 of 544
13.3.4 I2C Bus Mode Register (ICMR)
ICMR sets the communication format and transfer rate. It can only be accessed when the ICE bit
in ICCR is set to 1.
Bit Bit Name
Initial
Value R/W Description
7 MLS 0 R/W MSB-First/LSB-First Select
0: MSB-first
1: LSB-first
Set this bit to 0 when the I2C bus format is used.
6 WAIT 0 R/W Wait Insertion Bit
This bit is valid only in master mode with the I2C bus
format.
0: Data and the acknowledge bit are transferred
consecutively with no wait inserted.
1: After the fall of the clock for the final data bit (8th
clock), the IRIC flag is set to 1 in ICCR, and a wait
state begins (with SCL at the low level). When the
IRIC flag is cleared to 0 in ICCR, the wait ends and
the acknowledge bit is transferred.
For details, see section 13.4.7, IRIC Setting Timing and
SCL Control.
5
4
3
CKS2
CKS1
CKS0
0
0
0
R/W
R/W
R/W
Transfer Clock Select 2 to 0
These bits are used only in master mode.
These bits select the required transfer rate, together with
the IICX1 (IIC_1) and IICX0 (IIC_0) bits in STCR. See
table 13.3.
Rev. 1.00, 05/04, page 287 of 544
Bit Bit Name
Initial
Value R/W Description
2
1
0
BC2
BC1
BC0
0
0
0
R/W
R/W
R/W
Bit Counter 2 to 0
These bits specify the number of bits to be transferred
next. Bit BC2 to BC0 settings should be made during an
interval between transfer frames. If bits BC2 to BC0 are
set to a value other than 000, the setting should be
made while the SCL line is low.
The bit counter is initialized to 000 when a start condition
is detected. The value returns to 000 at the end of a data
transfer.
I2C Bus Format Clocked Synchronous Serial Mode
000: 9 bits 000: 8 bits
001: 2 bits 001: 1 bits
010: 3 bits 010: 2 bits
011: 4 bits 011: 3 bits
100: 5 bits 100: 4 bits
101: 6 bits 101: 5 bits
110: 7 bits 110: 6 bits
111: 8 bits 111: 7 bits
Rev. 1.00, 05/04, page 288 of 544
Table 13.3 I2C Transfer Rate
STCR ICMR
Bits 5 and 6 Bit 5 Bit 4 Bit 3 Transfer Rate
IICX CKS2 CKS1 CKS0 Clock φ = 5 MHz φ = 8 MHz φ = 10 MHz
0 0 0 0 φ/28 179 kHz 286 kHz 357 kHz
0 0 0 1 φ/40 125 kHz 200 kHz 250 kHz
0 0 1 0 φ/48 104 kHz 167 kHz 208 kHz
0 0 1 1 φ/64 78.1 kHz 125 kHz 156 kHz
0 1 0 0 φ/80 62.5 kHz 100 kHz 125 kHz
0 1 0 1 φ/100 50.0 kHz 80.0 kHz 100 kHz
0 1 1 0 φ/112 44.6 kHz 71.4 kHz 89.3 kHz
0 1 1 1 φ/128 39.1 kHz 62.5 kHz 78.1 kHz
1 0 0 0 φ/56 89.3 kHz 143 kHz 179 kHz
1 0 0 1 φ/80 62.5 kHz 100 kHz 125 kHz
1 0 1 0 φ/96 52.1 kHz 83.3 kHz 104 kHz
1 0 1 1 φ/128 39.1 kHz 62.5 kHz 78.1 kHz
1 1 0 0 φ/160 31.3 kHz 50.0 kHz 62.5 kHz
1 1 0 1 φ/200 25.0 kHz 40.0 kHz 50.0 kHz
1 1 1 0 φ/224 22.3 kHz 35.7 kHz 44.6 kHz
1 1 1 1 φ/256 19.5 kHz 31.3 kHz 39.1 kHz
Rev. 1.00, 05/04, page 289 of 544
13.3.5 I2C Bus Control Register (ICCR)
ICCR controls the I2C bus interface and performs interrupt flag confirmation.
Bit Bit Name
Initial
Value R/W Description
7 ICE 0 R/W I2C Bus Interface Enable
0: I2C bus interface modules are stopped and I2C bus
interface module internal state is initialized. SAR and
SARX can be accessed.
1: I2C bus interface modules can perform transfer
operation, and the ports function as the SCL and SDA
input/output pins. ICMR and ICDR can be accessed.
6 IEIC 0 R/W I2C Bus Interface Interrupt Enable
0: Disables interrupts from the I2C bus interface to the
CPU
1: Enables interrupts from the I2C bus interface to the
CPU.
5
4
MST
TRS
0
0
R/W
R/W
Master/Slave Select
Transmit/Receive Select
MST TRS
0 0 : Slave receive mode
0 1 : Slave transmit mode
1 0 : Master receive mode
1 1 : Master transmit mode
Both these bits will be cleared by hardware when they
lose in a bus contention in master mode with the I2C bus
format. In slave receive mode with I2C bus format, the
R/W bit in the first frame immediately after the start
condition sets these bits in receive mode or transmit
mode automatically by hardware.
Modification of the TRS bit during transfer is deferred
until transfer is completed, and the changeover is made
after completion of the transfer.
Rev. 1.00, 05/04, page 290 of 544
Bit Bit Name
Initial
Value R/W Description
5
4
MST
TRS
0
0
R/W [MST clearing conditions]
1. When 0 is written by software
2. When lost in bus contention in I2C bus format
master mode
[MST setting conditions]
1. When 1 is written by software (for MST clearing
condition 1)
2. When 1 is written in MST after reading MST = 0 (for
MST clearing condition 2)
[TRS clearing conditions]
1. When 0 is written by software (except for TRS
setting condition 3)
2. When 0 is written in TRS after reading TRS = 1 (for
TRS setting condition 3)
3. When lost in bus contention in I2C bus format
master mode
[TRS setting conditions]
1. When 1 is written by software (except for TRS
clearing condition 3)
2. When 1 is written in TRS after reading TRS = 0 (for
TRS clearing condition 3)
3. When 1 is received as the R/W bit after the first
frame address matching in I2C bus format slave
mode
3 ACKE 0 R/W Acknowledge Bit Decision and Selection
0: The value of the acknowledge bit is ignored, and
continuous transfer is performed. The value of the
received acknowledge bit is not indicated by the
ACKB bit in ICSR, which is always 0.
1: If the received acknowledge bit is 1, continuous
transfer is halted.
Depending on the receiving device, the acknowledge bit
may be significant, in indicating completion of
processing of the received data, for instance, or may be
fixed at 1 and have no significance.
Rev. 1.00, 05/04, page 291 of 544
Bit Bit Name
Initial
Value R/W Description
2
0
BBSY
SCP
0
1
R/W*
W
Bus Busy
Start Condition/Stop Condition Prohibit
In master mode:
Writing 0 in BBSY and 0 in SCP: A stop condition is
issued
Writing 1 in BBSY and 0 in SCP: A start condition
and a restart condition are issued
In slave mode:
Writing to the BBSY flag is disabled.
[BBSY setting condition]
When the SDA level changes from high to low under the
condition of SCL = high, assuming that the start condition
has been issued.
[BBSY clearing condition]
When the SDA level changes from low to high under the
condition of SCL = high, assuming that the stop condition
has been issued.
To issue a start/stop condition, use the MOV instruction.
The I2C bus interface must be set in master transmit
mode before the issue of a start condition. Set MST to 1
and TRS to 1 before writing 1 in BBSY and 0 in SCP.
The BBSY flag can be read to check whether the I2C bus
(SCL, SDA) is busy or free.
The SCP bit is always read as 1. If 0 is written, the data
is not stored.
Note: * The value in BBSY flag does not change even if written.
Rev. 1.00, 05/04, page 292 of 544
Bit Bit
Name Initial
Value R/W Description
1 IRIC 0 R/(W)* I
2C Bus Interface Interrupt Request Flag
Indicates that the I2C bus interface has issued an
interrupt request to the CPU.
IRIC is set at different times depending on the FS bit in
SAR, the FSX bit in SARX, and the WAIT bit in ICMR.
See section 13.4.7, IRIC Setting Timing and SCL
Control. The conditions under which IRIC is set also
differ depending on the setting of the ACKE bit in ICCR.
[Setting conditions]
I2C bus format master mode:
When a start condition is detected in the bus line
state after a start condition is issued (when the
ICDRE flag is set to 1 because of first frame
transmission)
When a wait is inserted between the data and
acknowledge bit when the WAIT bit is 1 (fall of the
8th transmit/receive clock)
At the end of data transfer (rise of the 9th
transmit/receive clock while no wait is inserted)
When a slave address is received after bus
arbitration is lost (the first frame after the start
condition)
If 1 is received as the acknowledge bit (when the
ACKB bit in ICSR is set to 1) when the ACKE bit is
1
When the AL flag is set to 1 after bus arbitration is
lost while the ALIE bit is 1
I2C bus format slave mode:
When the slave address (SVA or SVAX) matches
(when the AAS or AASX flag in ICSR is set to 1)
and at the end of data transfer up to the subsequent
retransmission start condition or stop condition
detection (rise of the 9th transmit/receive clock)
When the general call address is detected (when 0
is received as the R/W bit and the ADZ flag in ICSR
is set to 1) and at the end of data reception up to
the subsequent retransmission start condition or
stop condition detection (rise of the 9th receive
clock)
If 1 is received as the acknowledge bit (when the
ACKB bit in ICSR is set to 1) while the ACKE bit is 1
When a stop condition is detected (when the STOP
or ESTP flag in ICSR is set to 1) while the STOPIM
bit is 0
Rev. 1.00, 05/04, page 293 of 544
Bit Bit Name
Initial
Value R/W Description
1 IRIC 0 R/(W)* Clocked synchronous serial format mode:
At the end of data transfer (rise of the 8th
transmit/receive)
When a start condition is detected
When the ICDRE or ICDRF flag is set to 1 in any
operating mode:
When a start condition is detected in transmit mode
(when a start condition is detected in transmit mode
and the ICDRE flag is set to 1)
When data is transferred among ICDR and buffer
(when data is transferred from ICDRT to ICDRS in
transmit mode and the ICDRE flag is set to 1, or
when data is transferred from ICDRS to ICDRR in
receive mode and the ICDRF flag is set to 1)
[Clearing conditions]
When 0 is written in IRIC after reading IRIC = 1
Note: * Only 0 can be written, to clear the flag.
When, with the I2C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags
must be checked in order to identify the source that set IRIC to 1. Although each source has a
corresponding flag, caution is needed at the end of a transfer.
When the ICDRE or ICDRF flag is set, the IRTR flag may or may not be set. The IRTR flag is not
set at the end of a data transfer up to detection of a retransmission start condition or stop condition
after a slave address (SVA) or general call address match in I2C bus format slave mode.
Tables 13.4 and 13.5 show the relationship between the flags and the transfer states.
Rev. 1.00, 05/04, page 294 of 544
Table 13.4 Flags and Transfer States (Master Mode)
MST TRS BBSY ESTP STOP IRTR AASX AL AAS ADZ ACKB ICDRF ICDRE State
1 1 0 0 0 0 0 0 0 0 0 0 Idle state (flag
clearing required)
1 1 1 0 0 1 0 0 0 0 0 — 1 Start condition
detected
1 — 1 0 0 — 0 0 0 0 — Wait state
1 1 1 0 0 — 0 0 0 0 1 — — Transmission end
(ACKE=1 and
ACKB=1)
1 1 1 0 0 1 0 0 0 0 0 — 1 Transmission end
with ICDRE=0
1 1 1 0 0 — 0 0 0 0 0 — 0 ICDR write with the
above state
1 1 1 0 0 — 0 0 0 0 0 — 1 Transmission end
with ICDRE=1
1 1 1 0 0 — 0 0 0 0 0 — 0 ICDR write with the
above state or after
start condition
detected
1 1 1 0 0 1 0 0 0 0 0 — 1 Automatic data
transfer from
ICDRT to ICDRS
with the above
state
1 0 1 0 0 1 0 0 0 0 — 1 Reception end with
ICDRF=0
1 0 1 0 0 — 0 0 0 0 — 0 ICDR read with the
above state
1 0 1 0 0 — 0 0 0 0 — 1 — Reception end with
ICDRF=1
1 0 1 0 0 — 0 0 0 0 — 0 ICDR read with the
above state
1 0 1 0 0 1 0 0 0 0 — 1 Automatic data
transfer from
ICDRS to ICDRR
with the above
state
0 0 1 0 0 — 0 1 0 0 — — — Arbitration lost
1 — 0 0 0 — 0 0 0 0 — 0 Stop condition
detected
[Legend]
0: 0-state retained
1: 1-state retained
—: Previous state retained
0: Cleared to 0
1: Set to 1
Rev. 1.00, 05/04, page 295 of 544
Table 13.5 Flags and Transfer States (Slave Mode)
MST TRS BBSY ESTP STOP IRTR AASX AL AAS ADZ ACKB ICDRF ICDRE State
0 0 0 0 0 0 0 0 0 0 0 — 0 Idle state (flag
clearing required)
0 0 1 0 0 0 0 0 0 0 0 — 1 Start condition
detected
0 1/0
*1
1 0 0 0 0 1 0 0 1 1 SAR match in first
frame
(SARXSAR)
0 0 1 0 0 0 0 — 1 1 0 1 1 General call
address match in
first frame
(SARXH’00)
0 1/0
*1
1 0 0 1 1 0 0 0 1 1 SARS match in first
frame
(SARSARX)
0 1 1 0 0 — 0 1 — — Transmission end
(ACKE=1 and
ACKB=1)
0 1 1 0 0 1/0
*1
— — — 0 0 — 1 Transmission end
with ICDRE=0
0 1 1 0 0 — 0 0 0 0 0 ICDR write with the
above state
0 1 1 0 0 — 1 0 1 Transmission end
with ICDRE=1
0 1 1 0 0 — 0 0 0 0 0 ICDR write with the
above state
0 1 1 0 0 1/0
*2
0 0 0 0 1 Automatic data
transfer from
ICDRT to ICDRS
with the above
state
0 0 1 0 0 1/0
*2
— — — — — 1 Reception end with
ICDRF=0
0 0 1 0 0 — 0 0 0 0 ICDR read with the
above state
Rev. 1.00, 05/04, page 296 of 544
Table 13.5 Flags and Transfer States (Slave Mode) (cont)
MST TRS BBSY ESTP STOP IRTR AASX AL AAS ADZ ACKB ICDRF ICDRE State
0 0 1 0 0 — 1 — Reception end with
ICDRF=1
0 0 1 0 0 — 0 0 0 0 ICDR read with the
above state
0 0 1 0 0 1/0
*2
— 0 0 0 — 1 Automatic data
transfer from
ICDRS to ICDRR
with the above
state
0 — 0 1/0
*3
0/1
*3
— — — — — — — 0 Stop condition
detected
[Legend]
0: 0-state retained
1: 1-state retained
—: Previous state retained
0: Cleared to 0
1: Set to 1
Notes: 1. Set to 1 when 1 is received as a R/W bit following an address.
2. Set to 1 when the AASX bit is set to 1.
3. When ESTP = 1, STOP is 0, or when STOP = 1, ESTP is 0.
Rev. 1.00, 05/04, page 297 of 544
13.3.6 I2C Bus Status Register (ICSR)
ICSR consists of status flags. Also see tables 13.4 and 13.5.
Bit Bit Name
Initial
Value R/W Description
7 ESTP 0 R/(W)* Error Stop Condition Detection Flag
This bit is valid in I2C bus format slave mode.
[Setting condition]
When a stop condition is detected during frame
transfer.
[Clearing conditions]
When 0 is written in ESTP after reading ESTP = 1
When the IRIC flag in ICCR is cleared to 0
6 STOP 0 R/(W)* Normal Stop Condition Detection Flag
This bit is valid in I2C bus format slave mode.
[Setting condition]
When a stop condition is detected after frame transfer
completion.
[Clearing conditions]
When 0 is written in STOP after reading STOP = 1
When the IRIC flag is cleared to 0
5 IRTR 0 R/(W)* I
2C Bus Interface Continuous Transfer Interrupt
Request Flag
Indicates that the I2C bus interface has issued an
interrupt request to the CPU, and the source is
completion of reception/transmission of one frame in
continuous transmission/reception. When the IRTR flag
is set to 1, the IRIC flag is also set to 1 at the same
time.
[Setting conditions]
I2C bus format slave mode:
When the ICDRE or ICDRF flag in ICDR is set to 1
when AASX = 1
Master mode or clocked synchronous serial format
mode with I2C bus format:
When the ICDRE or ICDRF flag is set to 1
[Clearing conditions]
When 0 is written after reading IRTR = 1
When the IRIC flag is cleared to 0 while ICE is 1
Rev. 1.00, 05/04, page 298 of 544
Bit Bit Name
Initial
Value R/W Description
4 AASX 0 R/(W)* Second Slave Address Recognition Flag
In I2C bus format slave receive mode, this flag is set to
1 if the first frame following a start condition matches
bits SVAX6 to SVAX0 in SARX.
[Setting condition]
When the second slave address is detected in slave
receive mode and FSX = 0 in SARX
[Clearing conditions]
When 0 is written in AASX after reading AASX = 1
When a start condition is detected
In master mode
3 AL 0 R/(W)* Arbitration Lost Flag
Indicates that arbitration was lost in master mode.
[Setting conditions]
When ALSL = 0
If the internal SDA and SDA pin disagree at the
rise of SCL in master transmit mode
If the internal SCL line is high at the fall of SCL in
master transmit mode
When ALSL = 1
If the internal SDA and SDA pin disagree at the
rise of SCL in master transmit mode
If the SDA pin is driven low by another device
before the I2C bus interface drives the SDA pin
low, after the start condition instruction was
executed in master transmit mode
[Clearing conditions]
When ICDR is written to (transmit mode) or read
from (receive mode)
When 0 is written in AL after reading AL = 1
Rev. 1.00, 05/04, page 299 of 544
Bit Bit Name
Initial
Value R/W Description
2 AAS 0 R/(W)* Slave Address Recognition Flag
In I2C bus format slave receive mode, this flag is set to
1 if the first frame following a start condition matches
bits SVA6 to SVA0 in SAR, or if the general call
address (H'00) is detected.
[Setting condition]
When the slave address or general call address (one
frame including a R/W bit is H’00) is detected in slave
receive mode and FS = 0 in SAR
[Clearing conditions]
When ICDR is written to (transmit mode) or read
from (receive mode)
When 0 is written in AAS after reading AAS = 1
In master mode
1 ADZ 0 R/(W)* General Call Address Recognition Flag
In I2C bus format slave receive mode, this flag is set to
1 if the first frame following a start condition is the
general call address (H'00).
[Setting condition]
When the general call address (one frame including a
R/W bit is H’00) is detected in slave receive mode and
FS = 0 or FSX = 0
[Clearing conditions]
When ICDR is written to (transmit mode) or read
from (receive mode)
When 0 is written in ADZ after reading ADZ = 1
In master mode
If a general call address is detected while FS = 1 and
FSX = 0, the ADZ flag is set to 1; however, the general
call address is not recognized (AAS flag is not set to 1).
Rev. 1.00, 05/04, page 300 of 544
Bit Bit Name Initial
Value R/W Description
0 ACKB 0 R/W Acknowledge Bit
Stores acknowledge data.
Transmit mode:
[Setting condition]
When 1 is received as the acknowledge bit when ACKE
= 1 in transmit mode
[Clearing conditions]
When 0 is received as the acknowledge bit when
ACKE = 1 in transmit mode
When 0 is written to the ACKE bit
Receive mode:
0: Returns 0 as acknowledge data after data reception
1: Returns 1 as acknowledge data after data reception
When this bit is read, the value loaded from the bus line
(returned by the receiving device) is read in
transmission (when TRS = 1). In reception (when TRS
= 0), the value set by internal software is read.
When this bit is written, acknowledge data that is
returned after receiving is rewritten regardless of the
TRS value. If bit in ICSR is written using bit-
manipulation instructions, the acknowledge data should
be re-set since the acknowledge data setting is
rewritten by the ACKB bit reading value.
Write the ACKE bit to 0 to clear the ACKB flag to 0,
before transmission is ended and a stop condition is
issued in master mode, or before transmission is ended
and SDA is released to issue a stop condition by a
master device.
Note: * Only 0 can be written to clear the flag.
Rev. 1.00, 05/04, page 301 of 544
13.3.7 DDC Switch Register (DDCSWR)
DDCSWR controls IIC internal latch clearance.
Bit Bit Name
Initial
Value R/W Description
7 to 5 All 0 R/W Reserved
The initial value should not be changed.
4 — 0 R Reserved
3
2
1
0
CLR3
CLR2
CLR1
CLR0
1
1
1
1
W*
W*
W*
W*
IIC Clear 3 to 0
Controls initialization of the internal state of IIC_0 and
IIC_1.
00--: Setting prohibited
0100: Setting prohibited
0101: IIC_0 internal latch cleared
0110: IIC_1 internal latch cleared
0111: IIC_0 and IIC_1 internal latches cleared
1---: Invalid setting
When a write operation is performed on these bits, a
clear signal is generated for the internal latch circuit of
the corresponding module, and the internal state of the
IIC module is initialized.
These bits can only be written to; they are always read
as 1. Write data to this bit is not retained.
To perform IIC clearance, bits CLR3 to CLR0 must be
written to simultaneously using an MOV instruction. Do
not use a bit manipulation instruction such as BCLR.
When clearing is required again, all the bits must be
written to in accordance with the setting.
Note: * This bit is always read as 1.
Rev. 1.00, 05/04, page 302 of 544
13.3.8 I2C Bus Extended Control Register (ICXR)
ICXR enables or disables the I2C bus interface interrupt generation and continuous receive
operation, and indicates the status of receive/transmit operations.
Bit Bit Name
Initial
Value R/W Description
7 STOPIM 0 R/W Stop Condition Interrupt Source Mask
Enables or disables the interrupt generation when the
stop condition is detected in slave mode.
0: Enables IRIC flag setting and interrupt generation
when the stop condition is detected (STOP = 1 or
ESTP = 1) in slave mode.
1: Disables IRIC flag setting and interrupt generation
when the stop condition is detected.
6 HNDS 0 R/W Handshake Receive Operation Select
Enables or disables continuous receive operation in
receive mode.
0: Enables continuous receive operation
1: Disables continuous receive operation
When the HNDS bit is cleared to 0, receive operation is
performed continuously after data has been received
successfully while ICDRF flag is 0.
When the HNDS bit is set to 1, SCL is fixed to the low
level and the next data transfer is disabled after data
has been received successfully while the ICDRF flag is
0. The bus line is released and next receive operation is
enabled by reading the receive data in ICDR.
Rev. 1.00, 05/04, page 303 of 544
Bit Bit Name
Initial
Value R/W Description
5 ICDRF 0 R Receive Data Read Request Flag
Indicates the ICDR (ICDRR) status in receive mode.
0: Indicates that the data has been already read from
ICDR (ICDRR) or ICDR is initialized.
1: Indicates that data has been received successfully
and transferred from ICDRS to ICDRR, and the data
is ready to be read out.
[Setting conditions]
When data is received successfully and transferred
from ICDRS to ICDRR.
(1) When data is received successfully while ICDRF =
0 (at the rise of the 9th clock pulse).
(2) When ICDR is read successfully in receive mode
after data was received while ICDRF = 1.
[Clearing conditions]
When ICDR (ICDRR) is read.
When 0 is written to the ICE bit.
When the IIC is internally initialized using the CLR3
to CLR0 bits in DDCSWR.
When ICDRF is set due to the condition (2) above,
ICDRF is temporarily cleared to 0 when ICDR (ICDRR)
is read; however, since data is transferred from ICDRS
to ICDRR immediately, ICDRF is set to 1 again.
Note that ICDR cannot be read successfully in transmit
mode (TRS = 1) because data is not transferred from
ICDRS to ICDRR. Be sure to read data from ICDR in
receive mode (TRS = 0).
Rev. 1.00, 05/04, page 304 of 544
Bit Bit Name Initial
Value R/W Description
4 ICDRE 0 R Transmit Data Write Request Flag
Indicates the ICDR (ICDRT) status in transmit mode.
0: Indicates that the data has been already written to
ICDR (ICDRT) or ICDR is initialized.
1: Indicates that data has been transferred from ICDRT
to ICDRS and is being transmitted, or the start
condition has been detected or transmission has
been complete, thus allowing the next data to be
written to.
[Setting conditions]
When the start condition is detected from the bus
line state with I2C bus format or serial format.
When data is transferred from ICDRT to ICDRS.
1. When data transmission completed while ICDRE
= 0 (at the rise of the 9th clock pulse).
2. When data is written to ICDR in transmit mode
after data transmission was completed while
ICDRE = 1.
[Clearing conditions]
When data is written to ICDR (ICDRT).
When the stop condition is detected with I2C bus
format or serial format.
When 0 is written to the ICE bit.
When the IIC is internally initialized using the CLR3
to CLR0 bits in DDCSWR.
Note that if the ACKE bit is set to 1 with I2C bus format
thus enabling acknowledge bit decision, ICDRE is not
set when data transmission is completed while the
acknowledge bit is 1.
When ICDRE is set due to the condition (2) above,
ICDRE is temporarily cleared to 0 when data is written to
ICDR (ICDRT); however, since data is transferred from
ICDRT to ICDRS immediately, ICDRE is set to 1 again.
Do not write data to ICDR when TRS = 0 because the
ICDRE flag value is invalid during the time.
Rev. 1.00, 05/04, page 305 of 544
Bit Bit Name
Initial
Value R/W Description
3 ALIE 0 R/W Arbitration Lost Interrupt Enable
Enables or disables IRIC flag setting and interrupt
generation when arbitration is lost.
0: Disables interrupt request when arbitration is lost.
1: Enables interrupt request when arbitration is lost.
2 ALSL 0 R/W Arbitration Lost Condition Select
Selects the condition under which arbitration is lost.
0: When the SDA pin state disagrees with the data that
IIC bus interface outputs at the rise of SCL, or when
the SCL pin is driven low by another device.
1: When the SDA pin state disagrees with the data that
IIC bus interface outputs at the rise of SCL, or when
the SDA line is driven low by another device in idle
state or after the start condition instruction was
executed.
1
0
FNC1
FNC0
0
0
R/W
R/W
Function Bit
Cancels some restrictions on usage. For details, see
section 13.6, Usage Notes.
00: Restrictions on operation remaining in effect
01: Setting prohibited
10: Setting prohibited
11: Restrictions on operation canceled
Rev. 1.00, 05/04, page 306 of 544
13.3.9 Port G Control Register (PGCTL)
PGCTL selects the input/output pin for IIC.
Bit Bit Name
Initial
Value R/W Description
7
6
IIC1BS
IIC1AS
0
0
R/W
R/W
IIC_1 Input/Output Select B, A
Selects input/output pins for IIC_1 channel
IIC1BS IIC1AS
0 0: Selects P42/SDA1 and P86/SCL1
as IIC_1 I/O pins
0 1: Selects PG4/ExSDAA and
PG5/ExSCLA as IIC_1 I/O pins*1
1 0: Selects PG6/ExSDAB and
PG7/ExSCLB as IIC_1 I/O pins*1
1 1: Setting prohibited*2
4, 5 All 0 R/W Reserved
The initial value should not be changed.
3
2
IIC0BS
IIC0AS
0
0
R/W
R/W
IIC_0 Input/Output Select B, A
Selects input/output pins for IIC_1 channel
IIC0BS IIC0AS
0 0: Selects P97/SDA0 and P52/SCL0
as IIC_0 I/O pins
0 1: Selects PG4/ExSDAA and
PG5/ExSCLA as IIC_0 I/O pins*1
1 0: Selects PG6/ExSDAB and
PG7/ExSCLB as IIC_0 I/O pins*1
1 1: Setting prohibited*2
1, 0 All 0 R/W Reserved
The initial value should not be changed.
Notes: 1. The program development tool (emulator) does not support this function.
2. If multiple pins are selected as the serial clock I/O pin or serial data I/O pin for each
channel, the operation is not guaranteed. If a single pin is selected for both channels at
the same time, the operation is not guaranteed. When pins are switched, the I2C bus
must be free.
Rev. 1.00, 05/04, page 307 of 544
13.4 Operation
The I2C bus interface has an I2C bus format and a serial format.
13.4.1 I2C Bus Data Format
The I2C bus format is an addressing format with an acknowledge bit. This is shown in figure 13.3.
The first frame following a start condition always consists of 9 bits.
The serial format is a non-addressing format with no acknowledge bit. This is shown in
figure 13.4.
Figure 13.5 shows the I2C bus timing.
The symbols used in figures 13.3 to 13.5 are explained in table 13.6.
SASLA
7n
R/WDATA A
1
1m
111
A/A
1
P
1
Transfer bit count
(n = 1 to 8)
Transfer frame count
(m 1)
S SLA
7n1 7
R/WA DATA
11
1m1
1
A/A
1
S
1
SLA R/W
1
1m2
A
1
DATA
n2
A/A
1
P
1
(a) FS = 0 or FSX = 0
(b) Start condition retransmission FS = 0 or FSX = 0
Upper row: Transfer bit count (n1, n2 = 1 to 8)
Lower row: Transfer frame count (m1, m2 1)
Figure 13.3 I2C Bus Data Format (I2C Bus Format)
S DATA
8n
DATA
1
1m
P
1
FS = 1 and FSX = 1
Transfer bit count
(n = 1 to 8)
Transfer frame count
(m 1)
Figure 13.4 I2C Bus Data Format (Serial Format)
Rev. 1.00, 05/04, page 308 of 544
SDA
SCL
S SLA R/WA
981 to 7 981 to 7 981 to 7
DATA A DATA A/A
P
Figure 13.5 I2C Bus Timing
Table 13.6 I2C Bus Data Format Symbols
Legend
S Start condition. The master device drives SDA from high to low while SCL is high.
SLA Slave address. The master device selects the slave device.
R/W Indicates the direction of data transfer: from the slave device to the master device
when R/W is 1, or from the master device to the slave device when R/W is 0
A Acknowledge. The receiving device drives SDA low to acknowledge a transfer. (The
slave device returns acknowledge in master transmit mode, and the master device
returns acknowledge in master receive mode.)
DATA Transferred data. The bit length of transferred data is set with the BC2 to BC0 bits in
ICMR. The MSB first or LSB first is switched with the MLS bit in ICMR.
P Stop condition. The master device drives SDA from low to high while SCL is high.
Rev. 1.00, 05/04, page 309 of 544
13.4.2 Initialization
Initialize the IIC by the procedure shown in figure 13.6 before starting transmission/reception of
data.
Start initialization
Set MSTP4 = 0 (IIC_0)
MSTP3 = 0 (IIC_1)
(MSTPCRL)
Set ICE = 0 in ICCR
Set ICSR
Set STCR
Cancel module stop mode
Set the first and second slave addresses and IIC communication format
(SVA6 to SVA0, FS, SVAX6 to SVAX0, and FSX)
Enable ICMR and ICDR to be accessed
Use SCL/SDA pin as an IIC port
Set transfer rate (IICX)
Enable the CPU accessing to the IIC control register and data register
Set communication format, wait insertion, and transfer rate
(MLS, WAIT, CKS2 to CKS0)
Enable interrupt
(STOPIM, HNDS, ALIE, ALSL, FNC1, and FNC0)
Set acknowledge bit (ACKB)
Set ICMR
Set ICCR
Set IICE = 1 in STCR
Set SAR and SARX
Set ICE = 1 in ICCR
Set ICXR
<< Start transmit/receive operation >>
Set interrupt enable, transfer mode, and acknowledge decision
(IEIC, MST, TRS, and ACKE)
Enable SAR and SARX to be accessed
Figure 13.6 Sample Flowchart for IIC Initialization
Note: Be sure to modify ICMR after transmit/receive operation has been completed. If ICMR is
modified during transmit/receive operation, bit counter BC2 to BC0 will be modified
erroneously, thus causing incorrect operation.
13.4.3 Master Transmit Operation
In I2C bus format master transmit mode, the master device outputs the transmit clock and transmit
data, and the slave device returns an acknowledge signal.
Figure 13.7 shows the sample flowchart for the operations in master transmit mode.
Rev. 1.00, 05/04, page 310 of 544
Start
Initialize IIC
Set MST = 1 and
TRS = 1 in ICCR
Set BBSY =1 and
SCP = 0 in ICCR
Write transmit data in ICDR
Clear IRIC flag in ICCR
No
No
Yes
Yes
Yes
Yes
No
No
[1] Initialization
[3] Select master transmit mode.
[4] Start condition issuance
[6] Set transmit data for the first byte
(slave address + R/W).
(After writing to ICDR, clear IRIC flag
continuously.)
[9] Set transmit data for the second and
subsequent bytes.
(After writing to ICDR, clear IRIC flag
continuously.)
[2] Test the status of the SCL and SDA lines.
[7] Wait for 1 byte to be transmitted.
[10] Wait for 1 byte to be transmitted.
[11] Determine end of tranfer
[12] Stop condition issuance
[8] Test the acknowledge bit
transferred from the slave device.
[5] Wait for a start condition generation
Read IRIC flag in ICCR
Read ACKB bit in ICSR
IRIC = 1?
ACKB = 0?
Transmit mode?
Write transmit data in ICDR
Clear IRIC flag in ICCR
Read IRIC flag in ICCR
Read ACKB bit in ICSR
Clear IRIC flag in ICCR
End of transmission?
or ACKB = 1?
Set BBSY = 0 and
SCP = 0 in ICCR
End
Read BBSY flag in ICCR
BBSY = 0?
Yes
No
Read IRIC flag in ICCR
IRIC = 1?
Yes
No
Yes
No IRIC = 1?
Master receive mode
Figure 13.7 Sample Flowchart for Operations in Master Transmit Mode
Rev. 1.00, 05/04, page 311 of 544
The transmission procedure and operations by which data is sequentially transmitted in
synchronization with ICDR (ICDRT) write operations, are described below.
1. Initialize the IIC as described in section 13.4.2, Initialization.
2. Read the BBSY flag in ICCR to confirm that the bus is free.
3. Set bits MST and TRS to 1 in ICCR to select master transmit mode.
4. Write 1 to BBSY and 0 to SCP in ICCR. This changes SDA from high to low when SCL is
high, and generates the start condition.
5. Then the IRIC and IRTR flags are set to 1. If the IEIC bit in ICCR has been set to 1, an
interrupt request is sent to the CPU.
6. Write the data (slave address + R/W) to ICDR.
With the I2C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the first frame
data following the start condition indicates the 7-bit slave address and transmit/receive
direction (R/W).
To determine the end of the transfer, the IRIC flag is cleared to 0. After writing to ICDR, clear
IRIC continuously so no other interrupt handling routine is executed. If the time for
transmission of one frame of data has passed before the IRIC clearing, the end of transmission
cannot be determined. The master device sequentially sends the transmission clock and the
data written to ICDR. The selected slave device (i.e. the slave device with the matching slave
address) drives SDA low at the 9th transmit clock pulse and returns an acknowledge signal.
7. When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th
transmit clock pulse. After one frame has been transmitted, SCL is automatically fixed low in
synchronization with the internal clock until the next transmit data is written.
8. Read the ACKB bit in ICSR to confirm that ACKB is cleared to 0. When the slave device has
not acknowledged (ACKB bit is 1), operate step [12] to end transmission, and retry the
transmit operation.
9. Write the transmit data to ICDR.
As indicating the end of the transfer, the IRIC flag is cleared to 0. Perform the ICDR write and
the IRIC flag clearing sequentially, just as in step [6]. Transmission of the next frame is
performed in synchronization with the internal clock.
10. When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th
transmit clock pulse. After one frame has been transmitted, SCL is automatically fixed low in
synchronization with the internal clock until the next transmit data is written.
11. Read the ACKB bit in ICSR.
Confirm that the slave device has been acknowledged (ACKB bit is 0). When there is still data
to be transmitted, go to step [9] to continue the next transmission operation. When the slave
device has not acknowledged (ACKB bit is set to 1), operate step [12] to end transmission.
Rev. 1.00, 05/04, page 312 of 544
12. Clear the IRIC flag to 0.
Write 0 to ACKE in ICCR, to clear received ACKB contents to 0.
Write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high,
and generates the stop condition.
SDA
(master output)
SDA
(slave output)
21
R/W
43658712
9
A
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6
ICDRE
IRTR
ICDRT
Note:* Data write
in ICDR
prohibited
SCL
(master output)
Start condition generation
Slave address Data 1
Data 1
[9] ICDR write [9] IRIC clear
[6] ICDR write [6] IRIC clear
[4] BBSY set to 1
SCP cleared to 0
(start condition issuance)
User processing
Interrupt
request
Interrupt
request
Address + R/W
IRIC
[7]
[5]
ICDRS
Data 1
Address + R/W
Figure 13.8 Example of Operation Timing in Master Transmit Mode (MLS = WAIT = 0)
Rev. 1.00, 05/04, page 313 of 544
SDA
(master output)
SDA
(slave output)
21436587989
A
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 0
ICDRE
IRTR
ICDR
SCL
(master output)
Start condition issuance
Data 2
[9] ICDR write [9] IRIC clear
[12] IRIC clear
[11] ACKB read [12] Set BBSY = 1and
SCP = 0
(Stop condition issuance)
IRIC
A
[10]
[7]
Data 1
Data 1 Data 2
User processing
Figure 13.9 Example of Stop Condition Issuance Operation Timing
in Master Transmit Mode (MLS = WAIT = 0)
Rev. 1.00, 05/04, page 314 of 544
13.4.4 Master Receive Operation
In I2C bus format master receive mode, the master device outputs the receive clock, receives data,
and returns an acknowledge signal. The slave device transmits data.
The master device transmits data containing the slave address and R/W (1: read) in the first frame
following the start condition issuance in master transmit mode, selects the slave device, and then
switches the mode for receive operation.
Receive Operation Using the HNDS Function (HNDS = 1):
Figure 13.10 shows the sample flowchart for the operations in master receive mode (HNDS = 1).
End
Set TRS = 0 in ICCR
Set ACKB = 1 in ICSR
Read IRIC flag in ICCR
Clear IRIC flag in ICCR
Clear IRIC flag in ICCR
Clear IRIC flag in ICCR
Set HNDS = 1 in ICXR
Set BBSY = 0 and
SCP = 0 in ICCR
IRIC = 1?
No
Yes
Yes
Read ICDR
No
[4] Clear IRIC flag.
[1] Select receive mode.
[2] Start receiving. The first read is a dummy read.
[5] Read the receive data (for the second and subsequent read)
[3] Wait for 1 byte to be received.
(Set IRIC at the rise of the 9th clock for the receive frame)
[6] Set acknowledge data for the last reception.
[10] Read the receive data.
[9] Clear IRIC flag.
[7] Read the receive data.
Dummy read to start receiving if the first frame is
the last receive data.
[11] Set stop condition issuance.
Generate stop condition.
Master receive mode
Read IRIC flag in ICCR
IRIC = 1?
No
Yes
[8] Wait for 1 byte to be received.
Set ACKB = 0 in ICSR
Is next
receive the last one?
Last receive?
Read ICDR
Read ICDR
Set TRS = 1 in ICCR
Figure 13.10 Sample Flowchart for Operations in Master Receive Mode
(HNDS = 1)
Rev. 1.00, 05/04, page 315 of 544
The reception procedure and operations using the HNDS function, by which the data reception
process is provided in 1-byte units with SCL fixed low at each data reception, are described below.
1. Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode.
Clear the ACKB bit in ICSR to 0 (acknowledge data setting).
Set the HNDS bit in ICXR to 1.
Clear the IRIC flag to 0 to determine the end of reception.
Go to step [6] to halt reception operation if the first frame is the last receive data.
2. When ICDR is read (dummy data read), reception is started, the receive clock is output in
synchronization with the internal clock, and data is received. (Data from the SDA pin is
sequentially transferred to ICDRS in synchronization with the rise of the receive clock pulses.)
3. The master device drives SDA low to return the acknowledge data at the 9th receive clock
pulse. The receive data is transferred from ICDRS to ICDRR at the rise of the 9th clock pulse,
setting the ICDRF, IRIC, and IRTR flags to 1. If the IEIC bit has been set to 1, an interrupt
request is sent to the CPU.
The master device drives SCL low from the fall of the 9th receive clock pulse to the ICDR data
reading.
4. Clear the IRIC flag to clear the wait state.
Go to step [6] to halt reception operation if the next frame is the last receive data.
5. Read ICDR receive data. This clears the ICDRF flag to 0. The master device outputs the
receive clock continuously to receive the next data.
Data can be received continuously by repeating steps [3] to [5].
6. Set the ACKB bit to 1 so as to return the acknowledge data for the last reception.
7. Read ICDR receive data. This clears the ICDRF flag to 0. The master device outputs the
receive clock to receive data.
8. When one frame of data has been received, the ICDRF, IRIC, and IRTR flags are set to 1 at the
rise of the 9th receive clock pulse.
9. Clear the IRIC flag to 0.
10. Read ICDR receive data after setting the TRS bit. This clears the ICDRF flag to 0.
11. Clear the BBSY bit and SCP bit to 0 in ICCR. This changes SDA from low to high when SCL
is high, and generates the stop condition.
Rev. 1.00, 05/04, page 316 of 544
SDA
(master output)
SDA
(slave output)
21 4
365 8
712
99
A
A
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6
IRTR
ICDRF
ICDRR
SCL
(master output)
Master transmit mode Master receive mode
Data 1
Data 1 Data 2
[1]
TRS=0
clear [2] IRIC read
(Dummy read)
[1] IRIC clear
SCL is fixed low until ICDR is read SCL is fixed low until ICDR is read
[4] IRIC clear
User processing
IRIC
[3]
[5] ICDR read
(Data 1)
Undefined value
Figure 13.11 Example of Operation Timing in Master Receive Mode
(MLS = WAIT = 0, HNDS = 1)
SDA
(master output)
SDA
(slave output)
21 4
365 8
79978
A
A
Bit 7Bit 1 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
IRIC
ICDRF
ICDRR
SCL
(master output)
Data 3
Data 2
Data 1 Data 2
Data 3
[9] IRIC clear
User processing
IRTR
[8] [3]
Bit 0
[11]
Set BBSY = 0 and
SCP = 0
(Stop condition instruction issuance)
[4] IRIC clear [7]
ICDR read
(Data 2)
[10]
ICDR read
(Data 3)
[6]
Set ACKB = 1
Bit 0
Stop condition generation
SCL is fixed low until ICDR is read
SCL is fixed low until
stop condition is issued
Figure 13.12 Example of Stop Condition Issuance Operation Timing
in Master Receive Mode (MLS = WAIT = 0, HNDS = 1)
Rev. 1.00, 05/04, page 317 of 544
Receive Operation Using the Wait Function:
Figures 13.13 and 13.14 show the sample flowcharts for the operations in master receive mode
(WAIT = 1).
Set TRS = 0 in ICCR
Set ACKB = 0 in ICSR
Set WAIT = 1 in ICMR
Yes
Yes
Yes
Clear IRIC flag in ICCR
Clear IRIC flag in ICCR
Read IRIC flag in ICCR
Is next
receive the last one?
Last receive?
IRIC = 1?
IRTR = 1?
Yes
IRTR=1?
No
No
No
No
Read IRIC flag in ICCR
IRIC=1?
No
Yes
Read ICDR
[4] Determine end of reception
[13] Determine end of reception
[1] Select receive mode.
[2] Start receiving. The first read
is a dummy read.
[3] Wait for a receive wait
(Set IRIC at the fall of the 8th clock) or,
Wait for 1 byte to be received
(Set IRIC at the rise of the 9th clock)
[12] Wait for a receive wait
(Set IRIC at the fall of the 8th clock) or,
Wait for 1 byte to be received
(Set IRIC at the rise of the 9th clock)
[5] Read the receive data.
[6] Clear IRIC flag.
(to end the wait insertion)
[15] Clear wait mode.
Clear IRIC flag.
( IRIC flag should be cleared to 0
after setting WAIT = 0.)
[17] Generate stop condition
Master receive mode
[14] Clear IRIC.
(to end the wait insertion)
[16] Read the last receive data.
[7] Set acknowledge data for the last reception.
[8] Wait for TRS setting
[9] Set TRS for stop condition issuance
[10] Read the receive data.
[11] Clear IRIC flag. (to end the wait insertion)
Read ICDR
Clear IRIC flag in ICCR
Set HNDS = 0 in ICXR
Wait for one clock pulse
Set ACKB = 1 in ICSR
Set TRS = 1 in ICCR
End
Set WAIT = 0 in ICMR
Set BBSY= 0 and SCP= 0
in ICCR
Clear IRIC flag in ICCR
Read ICDR
Clear IRIC flag in ICCR
Read ICDR
Figure 13.13 Sample Flowchart for Operations in Master Receive Mode
(receiving multiple bytes) (WAIT = 1)
Rev. 1.00, 05/04, page 318 of 544
End
Set HNDS = 0 in ICXR
Set WAIT = 0 in ICMR
Set WAIT = 0 in ICMR
Set ACKB = 0 in ICSR
Set ACKB = 1 in ICSR
Read ICDR
Clear IRIC flag in ICCR
Clear IRIC flag in ICCR
Clear IRIC flag in ICCR
Read IRIC flag in ICCR
Read ICDR
Read IRIC flag in ICCR
IRIC = 1?
Yes
No
No IRIC = 1?
Yes
[1] Select receive mode.
[2] Start receiving. The first read
is a dummy read.
[15] Clear wait mode.
Clear IRIC flag.
(IRIC flag should be cleared to 0
after setting WAIT = 0.)
[11] Clear IRIC flag.
(to end the wait insertion)
[12] Wait for 1 byte to be received.
(Set IRIC at the rise of the 9th clock)
[9] Set TRS for stop condition issuance
[7] Set acknowledge data for
the last reception.
[16] Read the last receive data
Slave receive mode
Set TRS = 0 in ICCR
Set TRS = 1 in ICCR
[17] Generate stop condition
Set BBSY = 0 and
SCP = 0 in ICCR
[3] Wait for a receive wait
(Set IRIC at the fall of the 8th clock)
Figure 13.14 Sample Flowchart for Operations in Master Receive Mode
(receiving a single byte) (WAIT = 1)
Rev. 1.00, 05/04, page 319 of 544
The reception procedure and operations using the wait function (WAIT bit), by which data is
sequentially received in synchronization with ICDR (ICDRR) read operations, are described
below.
The following describes the multiple-byte reception procedure. In single-byte reception, some
steps of the following procedure are omitted. At this time, follow the procedure shown in figure
13.14.
1. Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode.
Clear the ACKB bit in ICSR to 0 to set the acknowledge data.
Clear the HNDS bit in ICXR to 0 to cancel the handshake function.
Clear the IRIC flag to 0, and then set the WAIT bit in ICMR to 1.
2. When ICDR is read (dummy data is read), reception is started, the receive clock is output in
synchronization with the internal clock, and data is received.
3. The IRIC flag is set to 1 in either of the following cases. If the IEIC bit in ICCR has been set to
1, an interrupt request is sent to the CPU.
At the fall of the 8th receive clock pulse for one frame
SCL is automatically fixed low in synchronization with the internal clock until the IRIC
flag clearing.
At the rise of the 9th receive clock pulse for one frame
The IRTR and ICDRF flags are set to 1, indicating that one frame of data has been
received. The master device outputs the receive clock continuously to receive the next data.
4. Read the IRTR flag in ICSR.
If the IRTR flag is 0, execute step [6] to clear the IRIC flag to 0 to release the wait state.
If the IRTR flag is 1 and the next data is the last receive data, execute step [7] to halt reception.
5. If IRTR flag is 1, read ICDR receive data.
6. Clear the IRIC flag. When the flag is set as the first case in step [3], the master device outputs
the 9th clock and drives SDA low at the 9th receive clock pulse to return an acknowledge
signal.
Data can be received continuously by repeating steps [3] to [6].
7. Set the ACKB bit in ICSR to 1 so as to return the acknowledge data for the last reception.
8. After the IRIC flag is set to 1, wait for at least one clock pulse until the rise of the first clock
pulse for the next receive data.
9. Set the TRS bit in ICCR to 1 to switch from receive mode to transmit mode. The TRS bit value
becomes valid when the rising edge of the next 9th clock pulse is input.
10. Read the ICDR receive data.
11. Clear the IRIC flag to 0.
Rev. 1.00, 05/04, page 320 of 544
12. The IRIC flag is set to 1 in either of the following cases.
At the fall of the 8th receive clock pulse for one frame
SCL is automatically fixed low in synchronization with the internal clock until the IRIC
flag is cleared.
At the rise of the 9th receive clock pulse for one frame
The IRTR and ICDRF flags are set to 1, indicating that one frame of data has been
received. The master device outputs the receive clock continuously to receive the next data.
13. Read the IRTR flag in ICSR.
If the IRTR flag is 0, execute step [14] to clear the IRIC flag to 0 to release the wait state.
If the IRTR flag is 1 and data reception is complete, execute step [15] to issue the stop
condition.
14. If IRTR flag is 0, clear the IRIC flag to 0 to release the wait state.
Execute step [12] to read the IRIC flag to detect the end of reception.
15. Clear the WAIT bit in CMR to cancel the wait mode.
Then, clear the IRIC flag. Clearing of the IRIC flag should be done while WAIT = 0. (If the
WAIT bit is cleared to 0 after clearing the IRIC flag and then an instruction to issue a stop
condition is executed, the stop condition may not be issued correctly.)
16. Read the last ICDR receive data.
17. Clear the BBSY bit and SCP bit to 0 in ICCR. This changes SDA from low to high when SCL
is high, and generates the stop condition.
SDA
(master output)
SDA
(slave output)
21 214365879
Bit 7 Bit 6 Bit 7 Bit 6Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IRIC
IRTR
ICDR
SCL
(master output)
Data 1
[1] TRS cleared to 0
IRIC cleard to 0
[6] IRIC clear
[5] ICDR read
(Data 1)
[6] IRIC clear
(to end wait insertion)
User processing
Bit 5 Bit 4 Bit 3
543
9
Data 1 Data 2
[3] [3]
A
[2] ICDR read
(dummy read)
Master tansmit mode Master receive mode
A
[4]IRTR=0 [4] IRTR=1
Figure 13.15 Example of Master Receive Mode Operation Timing
(MLS = ACKB = 0, WAIT = 1)
Rev. 1.00, 05/04, page 321 of 544
SDA
(master output)
SDA
(slave output)
21 4
365 8
7998
A
A
Bit 7Bit 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
IRIC
IRTR
ICDR
SCL
(master output)
Data 3
Data 2
Data 1 Data 2
Data 3
[6] IRIC clear
[8]
Wait for one clock pulse
[11] IRIC clear [14] IRIC clear
[16] ICDR read
(Data 3)
User processing
[12]
[3]
[10] ICDR read (Data 2)
[9]
Set TRS=1
[7]
Set ACKB=1
[15]
WAIT cleared
to 0, IRIC clear
[17] Stop condition
issuance
Bit 0
Stop condition generation
[13]
IRTR=1
[13]
IRTR=0
[12]
[4]
IRTR=1
[4]
IRTR=0
[3]
Figure 13.16 Example of Stop Condition Issuance Timing in Master Receive Mode
(MLS = ACKB = 0, WAIT = 1)
13.4.5 Slave Receive Operation
In I2C bus format slave receive mode, the master device outputs the transmit clock and transmit
data, and the slave device returns an acknowledge signal.
The slave device operates as the device specified by the master device when the slave address in
the first frame following the start condition that is issued by the master device matches its own
address.
Receive Operation Using the HNDS Function (HNDS = 1):
Figure 13.17 shows the sample flowchart for the operations in slave receive mode (HNDS = 1).
Rev. 1.00, 05/04, page 322 of 544
Slave receive mode
End
Read IRIC flag in ICCR
Clear IRIC flag in ICCR
Read IRIC flag in ICCR
Read AASX, AAS and ADZ in ICSR
Read TRS in ICCR
Read IRIC flag in ICCR
Clear IRIC in ICCR
Clear IRIC flag in ICCR
Read ICDR
Read ICDR
General call address processing
* Description omitted
Set MST = 0
and TRS = 0 in ICCR
IRIC = 1?
No
Yes
Read IRIC flag in ICCR
Set ACKB = 1 in ICSR
IRIC = 1?
No
Yes
TRS = 1?
IRIC = 1?
Yes
Yes
No
Yes
No
AAS = 1
and ADZ = 1?
[1] Initialization. Select slave receive mode.
[2] Read the receive data remaining unread.
[3] to [7] Wait for one byte to be received (slave address + R/W)
[10] Read the receive data. The first read is a dummy read.
[9] Set acknowledge data for the last reception.
[8] Clear IRIC
[5] to [7] Wait for the reception to end.
[5] to [7] Wait for the reception to end or
[11] Detect stop condition.
Slave transmit mode
Last reception?
No
No
Yes
Read ICDR, clear IRIC flag
No
Yes
Initialize IIC
ICDRF = 1?
[8] Clear IRIC flag.
[8] Clear IRIC flag.
[10] Read the receive data.
Set ACKB = 0 in ICSR
and HNDS = 1 in ICXR
[12] Clear IRIC flag.
ESTP = 1 or
STOP = 1?
No
Yes
Clear IRIC in ICCR
[12] Confirm STOP bit.
Figure 13.17 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 1)
Rev. 1.00, 05/04, page 323 of 544
The reception procedure and operations using the HNDS bit function, by which data reception
process is provided in 1-byte unit with SCL being fixed low at every data reception, are described
below.
1. Initialize the IIC as described in section 13.4.2, Initialization.
Clear the MST and TRS bits to 0 to set slave receive mode, and set the HNDS bit to 1 and the
ACKB bit to 0. Clear the IRIC flag in ICCR to 0 to see the end of reception.
2. Confirm that the ICDRF flag is 0. If the ICDRF flag is set to 1, read the ICDR and then clear
the IRIC flag to 0.
3. When the start condition output by the master device is detected, the BBSY flag in ICCR is set
to 1. The master device then outputs the 7-bit slave address and transmit/receive direction
(R/W), in synchronization with the transmit clock pulses.
4. When the slave address matches in the first frame following the start condition, the device
operates as the slave device specified by the master device. If the 8th data bit (R/W) is 0, the
TRS bit remains cleared to 0, and slave receive operation is performed. If the 8th data bit
(R/W) is 1, the TRS bit is set to 1, and slave transmit operation is performed. When the slave
address does not match, receive operation is halted until the next start condition is detected.
5. At the 9th clock pulse of the receive frame, the slave device returns the data in the ACKB bit
as an acknowledge signal.
6. At the rise of the 9th clock pulse, the IRIC flag is set to 1. If the IEIC bit has been set to 1, an
interrupt request is sent to the CPU.
If the AASX bit has been set to 1, IRTR flag is also set to 1.
7. At the rise of the 9th clock pulse, the receive data is transferred from ICDRS to ICDRR,
setting the ICDRF flag to 1. The slave device drives SCL low from the fall of the 9th receive
clock pulse until data is read from ICDR.
8. Confirm that the STOP bit is cleared to 0, and clear the IRIC flag to 0.
9. If the next frame is the last receive frame, set the ACKB bit to 1.
10. If ICDR is read, the ICDRF flag is cleared to 0, releasing the SCL bus line. This enables the
master device to transfer the next data.
Receive operations can be performed continuously by repeating steps [5] to [10].
11. When the stop condition is detected (SDA is changed from low to high when SCL is high), the
BBSY flag is cleared to 0 and the STOP bit is set to 1. If the STOPIM bit has been cleared to
0, the IRIC flag is set to 1.
12. Confirm that the STOP bit is set to 1, and clear the IRIC flag to 0.
Rev. 1.00, 05/04, page 324 of 544
SDA
(master output)
SDA
(slave output)
21 214365879
Bit 7 Bit 6 Bit 7 Bit 6Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ICDRF
IRIC
ICDRS
ICDRR
SCL
(master output)
SCL
(slave output)
Address
+R/W
Address
+R/W
Undefined value
[8] IRIC clear [10] ICDR read (dummy read)
User processing
21 214365879
SCL
(Pin waveform)
Start condition generation
Slave address
Data 1
[6]
A
R/W
[7] SCL is fixed low until ICDR is read
[2] ICDR read
Interrupt
request
occurrence
Figure 13.18 Example of Slave Receive Mode Operation Timing (1)
(MLS = 0, HNDS= 1)
SDA
(master output)
SDA
(slave output)
21436587989
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 0
ICDRF
ICDRS
ICDRR
IRIC
SCL
(master output)
SCL
(slave output)
[8] IRIC clear [12] IRIC clear
[9] Set ACKB=1 [5] ICDR read (
Data (n-
1)) [10] ICDR read
(
Data (n
))
User processing
Data (n
)
Data (n-
1)
Data (n-2
)
[6] [6]
[11]
AA
Stop condition generation
[7] SCL is fixed low until ICDR is read [7] SCL is fixed low until ICDR is read
Data (n-
1)
Data (n
)
Data (n
)
[8] IRIC clear
Data (n-
1)
Figure 13.19 Example of Slave Receive Mode Operation Timing (2)
(MLS = 0, HNDS= 1)
Rev. 1.00, 05/04, page 325 of 544
Continuous Receive Operation:
Figure 13.20 shows the sample flowchart for the operations in slave receive mode (HNDS = 0).
Slave receive mode
End
Read IRIC in ICCR
Clear IRIC in ICCR
Clear IRIC in ICCR
Read AASX, AAS and ADZ in ICSR
Read TRS in ICCR
Read IRIC in ICCR
Clear IRIC in ICCR
Clear IRIC in ICCR
Read ICDR
Wait for one frame
Read ICDR
Set ACKB = 0 in ICSR
Set ACKB = 1 in ICSR
Set HNDS = 0 in ICXR
General call address processing
* Description omitted
Set MST = 0
and TRS = 0 in ICCR
IRIC = 1?
No
Yes
ICDRF = 1?
Yes
TRS = 1?
IRIC = 1?
ICDRF = 1?
Yes
Yes
No
No
Yes
No
AAS = 1
and ADZ = 1?
No
No
[1] Select slave receive mode.
[2] Read the receive data remaining unread.
[3] to [7] Wait for one byte to be received (slave address + R/W)
(Set IRIC at the rise of the 9th clock)
[9] Wait for ACKB setting and set acknowledge data
for the last reception
(after the rise of the 9th clock of (n-1)th byte data)
[15] Clear IRIC
[14] Read the last receive data
[8] Clear IRIC
[13] Clear IRIC
[10] Read the receive data. The first read is a dummy read.
[11] Wait for one byte to be received
(Set IRIC at the rise of the 9th clock)
[12] Detect stop condition
Slave transmit mode
Yes
No
No
Read ICDR
No
Yes
ICDRF = 1?
(n-2)th-byte
reception?
ESTP = 1 or
STOP = 1?
* n: Address + total number of bytes received
Figure 13.20 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 0)
Rev. 1.00, 05/04, page 326 of 544
The reception procedure and operations in slave receive are described below.
1. Initialize the IIC as described in section 13.4.2, Initialization.
Clear the MST and TRS bits to 0 to set slave receive mode, and set the HNDS and ACKB bits
to 0. Clear the IRIC flag in ICCR to 0 to see the end of reception.
2. Confirm that the ICDRF flag is 0. If the ICDRF flag is set to 1, read the ICDR and then clear
the IRIC flag to 0.
3. When the start condition output by the master device is detected, the BBSY flag in ICCR is set
to 1. The master device then outputs the 7-bit slave address and transmit/receive direction
(R/W) in synchronization with the transmit clock pulses.
4. When the slave address matches in the first frame following the start condition, the device
operates as the slave device specified by the master device. If the 8th data bit (R/W) is 0, the
TRS bit remains cleared to 0, and slave transmit operation is performed. When the slave
address does not match, receive operation is halted until the next start condition is detected.
5. At the 9th clock pulse of the receive frame, the slave device returns the data in the ACKB bit
as an acknowledge signal.
6. At the rise of the 9th clock pulse, the IRIC flag is set to 1. If the IEIC bit has been set to 1, an
interrupt request is sent to the CPU.
If the AASX bit has been set to 1, the IRTR flag is also set to 1.
7. At the rise of the 9th clock pulse, the receive data is transferred from ICDRS to ICDRR,
setting the ICDRF flag to 1.
8. Confirm that the STOP bit is cleared to 0 and clear the ICIC flag to 0.
9. If the next read data is the third last receive frame, wait for at least one frame time to set the
ACKB bit. Set the ACKB bit after the rise of the 9th clock pulse of the second last receive
frame.
10. Confirm that the ICDRF flag is set to 1 and read ICDR. This clears the ICDRF flag to 0.
11. At the rise of the 9th clock pulse or when the receive data is transferred from IRDRS to
ICDRR due to ICDR read operation, the IRIC and ICDRF flags are set to 1.
12. When the stop condition is detected (SDA is changed from low to high when SCL is high), the
BBSY flag is cleared to 0 and the STOP or ESTP flag is set to 1. If the STOPIM bit has been
cleared to 0, the IRIC flag is set to 1. In this case, execute step [14] to read the last receive
data.
13. Clear the IRIC flag to 0.
Receive operations can be performed continuously by repeating steps [9] to [13].
14. Confirm that the ICDRF flag is set to 1, and read ICDR.
15. Clear the IRIC flag.
Rev. 1.00, 05/04, page 327 of 544
SDA
(master output)
SDA
(slave output)
2143214365879
Bit 7 Bit 6 Bit 7 Bit 6 Bit 5 Bit 4Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ICDRF
ICDRS
ICDRR
IRIC
SCL
(master output)
Start condition issuance
Address+R/WData 1
Address+R/W
[8] IRIC clear
[10] ICDR read
User processing
Slave address [6]
[7]
A
R/WData 1
Figure 13.21 Example of Slave Receive Mode Operation Timing (1)
(MLS = ACKB = 0, HNDS = 0)
Start condition detection
SDA
(master output)
SDA
(slave output)
21436521436587987989
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 1 Bit 0
ICDRF
ICDRS
ICDRR
IRIC
SCL
(master output)
[9] Set ACKB = 1
[13] IRIC clear
[10] ICDR read
(Data n-2)
[10] ICDR read
(Data n-1)
[13] IRIC clear
[9] Wait for one frame
User processing
Bit 7Bit 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
Data nData n-1
Data n-1
Data n-1
Data n-2
Data n-2
Data n
Data n
Data n-2
[11]
[11] [11]
AA A
[13] IRIC clear
[14] ICDR read
(Data n)
[15] IRIC clear
[11]
Figure 13.22 Example of Slave Receive Mode Operation Timing (2)
(MLS = ACKB = 0, HNDS = 0)
Rev. 1.00, 05/04, page 328 of 544
13.4.6 Slave Transmit Operation
If the slave address matches to the address in the first frame (address reception frame) following
the start condition detection when the 8th bit data (R/W) is 1 (read), the TRS bit in ICCR is
automatically set to 1 and the mode changes to slave transmit mode.
Figure 13.23 shows the sample flowchart for the operations in slave transmit mode.
End
Write transmit data in ICDR
Clear IRIC in ICCR
Clear IRIC in ICCR
Clear ACKE to 0 in ICCR
(ACKB=0 clear)
Clear IRIC in ICCR
Read IRIC in ICCR
Read ACKB in ICSR
Set TRS = 0 in ICCR
Read ICDR
Read IRIC in ICCR
IRIC = 1?
Yes
Yes
No
No
IRIC = 1?
Yes
No
[1], [2] If the slave address matches to the address in the first frame
following the start condition detection and the R/W bit is 1
in slave recieve mode, the mode changes to slave transmit mode.
[8] Set slave receive mode.
[6] Read IRIC in ICCR
[7] Clear acknowledge bit data
[9] Dummy read (to release the SCL line).
[10]
Wait for stop condition
[3], [5] Set transmit data for the second and subsequent bytes.
[3], [4] Wait for 1 byte to be transmitted.
[4] Determine end of transfer.
Slave transmit mode
End
of transmission
(ACKB = 1)?
Clear IRIC in ICCR
Figure 13.23 Sample Flowchart for Slave Transmit Mode
Rev. 1.00, 05/04, page 329 of 544
In slave transmit mode, the slave device outputs the transmit data, while the master device outputs
the receive clock and returns an acknowledge signal. The transmission procedure and operations in
slave transmit mode are described below.
1. Initialize slave receive mode and wait for slave address reception.
2. When the slave address matches in the first frame following detection of the start condition,
the slave device drives SDA low at the 9th clock pulse and returns an acknowledge signal. If
the 8th data bit (R/W) is 1, the TRS bit in ICCR is set to 1, and the mode changes to slave
transmit mode automatically. The IRIC flag is set to 1 at the rise of the 9th clock. If the IEIC
bit in ICCR has been set to 1, an interrupt request is sent to the CPU. At the same time, the
ICDRE flag is set to 1. The slave device drives SCL low from the fall of the transmit clock
until ICDR data is written, to disable the master device to output the next transfer clock.
3. After clearing the IRIC flag to 0, write data to ICDR. At this time, the ICDRE flag is cleared to
0. The written data is transferred to ICDRS, and the ICDRE and IRIC flags are set to 1 again.
The slave device sequentially sends the data written into ICDRS in accordance with the clock
output by the master device.
The IRIC flag is cleared to 0 to detect the end of transmission. Processing from ICDR writing
to the IRIC flag clearing should be performed continuously. Prevent any other interrupt
processing from being inserted.
4. The master device drives SDA low at the 9th clock pulse, and returns an acknowledge signal.
As this acknowledge signal is stored in the ACKB bit in ICSR, this bit can be used to
determine whether the transfer operation was performed successfully. When one frame of data
has been transmitted, the IRIC flag in ICCR is set to 1 at the rise of the 9th transmit clock
pulse. When the ICDRE flag is 0, the data written into ICDR is transferred to ICDRS,
transmission starts, and the ICDRE and IRIC flags are set to 1 again. If the ICDRE flag has
been set to 1, this slave device drives SCL low from the fall of the transmit clock until data is
written to ICDR.
5. To continue transmission, write the next data to be transmitted into ICDR. The ICDRE flag is
cleared to 0. The IRIC flag is cleared to 0 to detect the end of transmission. Processing from
ICDR writing to the IRIC flag clearing should be performed continuously. Prevent any other
interrupt processing from being inserted.
Transmit operations can be performed continuously by repeating steps [4] and [5].
6. Clear the IRIC flag to 0.
7. To end transmission, clear the ACKE bit in ICCR to 0, to clear the acknowledge bit stored in
the ACKB bit to 0.
8. Clear the TRS bit to 0 for the next address reception, to set slave receive mode.
9. Dummy-read ICDR to release SDA on the slave side.
Rev. 1.00, 05/04, page 330 of 544
10. When the stop condition is detected, that is, when SDA is changed from low to high when SCL
is high, the BBSY flag in ICCR is cleared to 0 and the STOP flag in ICSR is set to 1. When the
STOPIM bit in ICXR is 0, the IRIC flag is set to 1. If the IRIC flag has been set, it is cleared
to 0.
SDA
(master output)
SDA
(slave output)
21 21436587998
Bit 7 Bit 6 Bit 5 Bit 7 Bit 6Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ICDRE
ICDR
IRIC
SCL
(master output)
Slave receive mode Slave transmit mode
[3] ICDR write
User processing
Data 1
Data 1 Data 2
Data 2
A
R/W
A
[4]
[3] IRIC clear
[3] IRIC clear
[5] IRIC clear
[5] ICDR write
[2]
Figure 13.24 Example of Slave Transmit Mode Operation Timing
(MLS = 0)
Rev. 1.00, 05/04, page 331 of 544
13.4.7 IRIC Setting Timing and SCL Control
The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the
FS bit in SAR, and the FSX bit in SARX. If the ICDRE or ICDRF flag is set to 1, SCL is
automatically held low after one frame has been transferred in synchronization with the internal
clock. Figures 13.25 to 13.27 show the IRIC set timing and SCL control.
SCL
SDA
IRIC
User processing
Clear IRIC
231A8
7
321987
When WAIT = 0, and FS = 0 or FSX = 0 (I
2
C bus format, no wait)
(a) Data transfer ends with ICDRE = 0 at transmission, or ICDRF = 0 at reception.
(b) Data transfer ends with ICDRE = 1 at transmission, or ICDRF = 1 at reception.
SCL
SDA
IRIC
User processing
Clear IRIC Clear IRICWrite to ICDR (transmit)
or read from ICDR (receive)
1A8
7
1987
Figure 13.25 IRIC Setting Timing and SCL Control (1)
Rev. 1.00, 05/04, page 332 of 544
SCL
SDA
IRIC
User processing
Clear IRIC
213A
8
123
9
8
Clear IRIC
When WAIT = 1, and FS = 0 or FSX = 0 (I
2
C bus format, wait inserted)
SCL
SDA
IRIC
User processing
Clear IRICWrite to ICDR (transmit)
or read from ICDR (receive)
1A
8
19
8
Clear IRIC
(a) Data transfer ends with ICDRE=0 at transmission, or ICDRF=0 at reception.
(b) Data transfer ends with ICDRE=1 at transmission, or ICDRF=1 at reception.
Figure 13.26 IRIC Setting Timing and SCL Control (2)
Rev. 1.00, 05/04, page 333 of 544
SCL
SDA
IRIC
User processing
Clear IRIC
187
412387
When FS = 1 and FSX = 1 (clocked synchronous serial format)
(a) Data transfer ends with ICDRE = 0 at transmission, or ICDRF = 0 at reception.
SCL
SDA
IRIC
User processing
Clear IRIC Clear IRIC
Write to ICDR (transmit)
or read from ICDR (receive)
87214
3
187
(b) Data transfer ends with ICDRE =1 at transmission, or ICDRF = 1 at reception.
Figure 13.27 IRIC Setting Timing and SCL Control (3)
Rev. 1.00, 05/04, page 334 of 544
13.4.8 Noise Canceller
The logic levels at the SCL and SDA pins are routed through noise cancellers before being latched
internally. Figure 13.28 shows a block diagram of the noise canceller.
The noise canceller consists of two cascaded latches and a match detector. The SCL (or SDA) pin
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
System clock
cycle
Sampling clock
C
DQ
Latch
C
DQ
Latch
SCL or
SDA input signal Match
detector
Internal SCL or
SDA signal
Sampling
clock
Figure 13.28 Block Diagram of Noise Canceler
Rev. 1.00, 05/04, page 335 of 544
13.4.9 Initialization of Internal State
The IIC has a function for forcible initialization of its internal state if a deadlock occurs during
communication.
Initialization is executed in accordance with the setting of bits CLR3 to CLR0 in DDCSWR or
clearing ICE bit. For details on the setting of bits CLR3 to CLR0, see section 13.3.7, DDC Switch
Register (DDCSWR).
Scope of Initialization: The initialization executed by this function covers the following items:
ICDRE and ICDRF internal flags
Transmit/receive sequencer and internal operating clock counter
Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, data
output, etc.)
The following items are not initialized:
Actual register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, ICXR (except for the ICDRE
and ICDRF flags), and PGCTL)
Internal latches used to retain register read information for setting/clearing flags in ICMR,
ICCR, and ICSR
The value of the ICMR bit counter (BC2 to BC0)
Generated interrupt sources (interrupt sources transferred to the interrupt controller)
Notes on Initialization:
Interrupt flags and interrupt sources are not cleared, and so flag clearing measures must be
taken as necessary.
Basically, other register flags are not cleared either, and so flag clearing measures must be
taken as necessary.
When initialization is executed by DDCSWR, the write data for bits CLR3 to CLR0 is not
retained. To perform IIC clearance, bits CLR3 to CLR0 must be written to simultaneously
using an MOV instruction. Do not use a bit manipulation instruction such as BCLR.
Similarly, when clearing is required again, all the bits must be written to simultaneously in
accordance with the setting.
If a flag clearing setting is made during transmission/reception, the IIC module will stop
transmitting/receiving at that point and the SCL and SDA pins will be released. When
transmission/reception is started again, register initialization, etc., must be carried out as
necessary to enable correct communication as a system.
Rev. 1.00, 05/04, page 336 of 544
The value of the BBSY bit cannot be modified directly by this module clear function, but since the
stop condition pin waveform is generated according to the state and release timing of the SCL and
SDA pins, the BBSY bit may be cleared as a result. Similarly, state switching of other bits and
flags may also have an effect.
To prevent problems caused by these factors, the following procedure should be used when
initializing the IIC state.
1. Execute initialization of the internal state according to the setting of bits CLR3 to CLR0 or
ICE bit clearing.
2. Execute a stop condition issuance instruction (write 0 to BBSY and SCP) to clear the BBSY
bit to 0, and wait for two transfer rate clock cycles.
3. Re-execute initialization of the internal state according to the setting of bits CLR3 to CLR0 or
ICE bit clearing.
4. Initialize (re-set) the IIC registers.
13.5 Interrupt Sources
The IIC has interrupt source IICI. Table 13.7 shows the interrupt sources and priority. Individual
interrupt sources can be enabled or disabled using the enable bits in ICCR, and are sent to the
interrupt controller independently.
Table 13.7 IIC Interrupt Sources
Channel Name Enable Bit Interrupt Source Interrupt Flag Priority
0 IICI0 IEIC I2C bus interface
interrupt request
IRIC High
1 IICI1 IEIC I2C bus interface
interrupt request
IRIC
Low
Rev. 1.00, 05/04, page 337 of 544
13.6 Usage Notes
1. In master mode, if an instruction to generate a start condition is issued and then an instruction
to generate a stop condition is issued before the start condition is output to the I2C bus, neither
condition will be output correctly. To output the start condition followed by the stop condition,
after issuing the instruction that generates the start condition, read DR in each I2C bus output
pin, and check that SCL and SDA are both low. The pin states can be monitored by reading
DR even if the ICE bit is set to 1. Then issue the instruction that generates the stop condition.
Note that SCL may not yet have gone low when BBSY is cleared to 0.
2. Either of the following two conditions will start the next transfer. Pay attention to these
conditions when accessing to ICDR.
Write to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from ICDRT to
ICDRS)
Read from ICDR when ICE = 1 and TRS = 0 (including automatic transfer from ICDRS to
ICDRR)
3. Table 13.8 shows the timing of SCL and SDA outputs in synchronization with the internal
clock. Timings on the bus are determined by the rise and fall times of signals affected by the
bus load capacitance, series resistance, and parallel resistance.
Table 13.8 I2C Bus Timing (SCL and SDA Outputs)
Item Symbol Output Timing Unit Notes
SCL output cycle time tSCLO 28tcyc to 256tcyc ns
SCL output high pulse width tSCLHO 0.5tSCLO ns
SCL output low pulse width tSCLLO 0.5tSCLO ns
SDA output bus free time tBUFO 0.5tSCLO – 1tcyc ns
Start condition output hold time tSTAHO 0.5tSCLO – 1tcyc ns
Retransmission start condition output
setup time
tSTASO 1tSCLO ns
Stop condition output setup time tSTOSO 0.5tSCLO + 2tcyc ns
Data output setup time (master) 1tSCLLO – 3tcyc
Data output setup time (slave)
tSDASO
1tSCLL – (6tcyc or 12tcyc*)
ns
Data output hold time tSDAHO 3tcyc ns
See figure
22.22.
Note: * 6tcyc when IICX is 0, 12tcyc when 1.
4. SCL and SDA inputs are sampled in synchronization with the internal clock. The AC timing
therefore depends on the system clock cycle tcyc, as shown in section 22, Electrical
Characteristics. Note that the I2C bus interface AC timing specifications will not be met with a
system clock frequency of less than 5 MHz.
Rev. 1.00, 05/04, page 338 of 544
5. The I2C bus interface specification for the SCL rise time tsr is 1000 ns or less (300 ns for high-
speed mode). In master mode, the I2C bus interface monitors the SCL line and synchronizes
one bit at a time during communication. If tsr (the time for SCL to go from low to VIH) exceeds
the time determined by the input clock of the I2C bus interface, the high period of SCL is
extended. The SCL rise time is determined by the pull-up resistance and load capacitance of
the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance
and load capacitance so that the SCL rise time does not exceed the values given in table 13.9.
Table 13.9 Permissible SCL Rise Time (tsr) Values
Time Indication [ns]
IICX tcyc Indication
I2C Bus
Specification
(Max.)
φ =
5 MHz
φ =
8 MHz
φ =
10 MHz
Standard mode 1000 1000 937 750 0 7.5 tcyc
High-speed mode 300 300 300 300
Standard mode 1000 1000 1000 1000 1 17.5 tcyc
High-speed mode 300 300 300 300
6. The I2C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns
and 300 ns. The I2C bus interface SCL and SDA output timing is prescribed by tcyc, as shown in
table 13.8. However, because of the rise and fall times, the I2C bus interface specifications may
not be satisfied at the maximum transfer rate. Table 13.10 shows output timing calculations for
different operating frequencies, including the worst-case influence of rise and fall times.
tBUFO fails to meet the I2C bus interface specifications at any frequency. The solution is either (a)
to provide coding to secure the necessary interval (approximately 1 µs) between issuance of a
stop condition and issuance of a start condition, or (b) to select devices whose input timing
permits this output timing for use as slave devices connected to the I2C bus.
tSCLLO in high-speed mode and tSTASO in standard mode fail to satisfy the I2C bus interface
specifications for worst-case calculations of tSr/tSf. Possible solutions that should be investigated
include (a) adjusting the rise and fall times by means of a pull-up resistor and capacitive load,
(b) reducing the transfer rate to meet the specifications, or (c) selecting devices whose input
timing permits this output timing for use as slave devices connected to the I2C bus.
Rev. 1.00, 05/04, page 339 of 544
Table 13.10 I2C Bus Timing (with Maximum Influence of tSr/tSf)
Time Indication (at Maximum Transfer Rate) [ns]
Item tcyc Indication
tSr/tSf
Influence
(Max.)
I2C Bus
Specifi-
cation
(Min.)
φ =
5 MHz
φ =
8 MHz
φ =
10 MHz
Standard mode –1000 4000 4000 4000 4000 tSCLHO 0.5 tSCLO (–tSr)
High-speed mode –300 600 950 950 950
Standard mode –250 4700 4750 4750 4750 tSCLLO 0.5 tSCLO (–tSf)
High-speed mode –250 1300 1000*1 1000*1 1000*1
Standard mode –1000 4700 3800*1 3875*1 3900*1 tBUFO 0.5 tSCLO –1 tcyc
(–tSr) High-speed mode –300 1300 750*1 825*1 850*1
Standard mode –250 4000 4550 4625 4650 tSTAHO 0.5 tSCLO –1 tcyc
(–tSf) High-speed mode –250 600 800 875 900
Standard mode –1000 4700 9000 9000 9000 tSTASO 1 tSCLO (–tSr)
High-speed mode –300 600 2200 2200 2200
Standard mode –1000 4000 4400 4250 4200 tSTOSO 0.5 tSCLO + 2 tcyc
(–tSr) High-speed mode –300 600 1350 1200 1150
Standard mode –1000 250 3100 3325 3400 tSDASO
(master)
1 tSCLLO*3 –3 tcyc
(–tSr) High-speed mode –300 100 400 625 700
Standard mode –1000 250 1300 2200 2500 tSDASO
(slave)
1 tSCLL*3
–12 tcyc*2
(–tSr) High-speed mode –300 100 –1400*1 –500*1 –200*1
Standard mode 0 0 600 375 300 tSDAHO 3 tcyc
High-speed mode 0 0 600 375 300
Notes: 1. Does not meet the I2C bus interface specification. Remedial action such as the following
is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and
fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate;
(d) select slave devices whose input timing permits this output timing.
The values in the above table will vary depending on the settings of the IICX bit and bits
CKS0 to CKS2. Depending on the frequency it may not be possible to achieve the
maximum transfer rate; therefore, whether or not the I2C bus interface specifications are
met must be determined in accordance with the actual setting conditions.
2. Value when the IICX bit is set to 1. When the IICX bit is cleared to 0, the value is (tSCLL
6tcyc).
3. Calculated using the I2C bus specification values (standard mode: 4700 ns min.; high-
speed mode: 1300 ns min.).
Rev. 1.00, 05/04, page 340 of 544
7. Notes on ICDR read at end of master reception
To halt reception at the end of a receive operation in master receive mode, set the TRS bit to 1
and write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is
high, and generates the stop condition. After this, receive data can be read by means of an
ICDR read, but if data remains in the buffer the ICDRS receive data will not be transferred to
ICDR (ICDRR), and so it will not be possible to read the second byte of data.
If it is necessary to read the second byte of data, issue the stop condition in master receive
mode (i.e. with the TRS bit cleared to 0). When reading the receive data, first confirm that the
BBSY bit in ICCR is cleared to 0, the stop condition has been generated, and the bus has been
released, then read ICDR with TRS cleared to 0.
Note that if the receive data (ICDR data) is read in the interval between execution of the
instruction for issuance of the stop condition (writing of 0 to BBSY and SCP in ICCR) and the
actual generation of the stop condition, the clock may not be output correctly in subsequent
master transmission.
Clearing of the MST bit after completion of master transmission/reception, or other modifications
of IIC control bits to change the transmit/receive operating mode or settings, must be carried out
during interval (a) in figure 13.29 (after confirming that the BBSY bit in ICCR has been cleared to
0).
SDA
SCL
Internal clock
BBSY bit
Master receive mode
ICDR read
disabled period
Bit 0 A
89
Stop condition
(a)
Start condition
Execution of instruction
for issuing stop condition
(write 0 to BBSY and SCP)
Confirmation of stop
condition issuance
(read BBSY = 0)
Start condition
issuance
Figure 13.29 Notes on Reading Master Receive Data
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to 1 in
ICXR.
Rev. 1.00, 05/04, page 341 of 544
8. Notes on start condition issuance for retransmission
Figure 13.30 shows the timing of start condition issuance for retransmission, and the timing for
subsequently writing data to ICDR, together with the corresponding flowchart. Write the
transmit data to ICDR after the start condition for retransmission is issued and then the start
condition is actually generated.
SDA
IRIC
SCL
[3] (Retransmission) Start condition instruction issuance
[4] IRIC determination
[5] ICDR write (transmit data)
[2] Determination of SCL = Low
[1] IRIC determination
Start condition generation
(retransmission)
IRIC = 1?
Yes
Clear IRIC in ICSR
Read SCL pin
Write transmit data to ICDR
Set BBSY = 1,
SCP = 0 (ICSR)
[1] [1] Wait for end of 1-byte transfer
[2] Determine whether SCL is low
[3] Issue start condition instruction for retransmission
[4] Determine whether start condition is generated or not
[5] Set transmit data (slave address + R/W)
[2]
[3]
[4]
[5]
Yes
Yes
No
No
IRIC = 1?
Yes
SCL = Low?
Start condition
issuance?
No
No
Other processing
Note:* Program so that processing from [3] to [5]
is executed continuously.
bit7ACK
9
Figure 13.30 Flowchart for Start Condition Issuance Instruction for Retransmission and
Timing
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to 1 in
ICXR.
Rev. 1.00, 05/04, page 342 of 544
9. Note on when I2C bus interface stop condition instruction is issued
In cases where the rise time of the 9th clock of SCL exceeds the stipulated value because of a
large bus load capacity or where a slave device in which a wait can be inserted by driving the
SCL pin low is used, the stop condition instruction should be issued after reading SCL after the
rise of the 9th clock pulse and determining that it is low.
Stop condition generation
SCL
IRIC
[1] SCL = low determination
VIH
[2] Stop condition instruction issuance
SDA
9th clock Secures a high period
SCL is detected as low
because the rise of the
waveform is delayed
Figure 13.31 Stop Condition Issuance Timing
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to 1 in
ICXR.
Rev. 1.00, 05/04, page 343 of 544
10. Note on IRIC flag clear when the wait function is used
If the rise time of SCL exceeds the stipulated value or a slave device in which a wait can be
inserted by driving the SCL pin low is used when the wait function is used in I2C bust interface
master mode, the IRIC flag should be cleared after determining that the SCL is low, as
described below.
If the IRIC flag is cleared to 0 when WAIT = 1 while the SCL is extending the high level time,
the SDA level may change before the SCL goes low, which may generate a start or stop
condition erroneously.
SCL
IRIC
[1] SCL = low determination
VIH
[2] IRIC clear
SDA
Secures a high period
SCL = low detected
Figure 13.32 IRIC Flag Clearing Timing when WAIT = 1
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to 1 in
ICXR.
Rev. 1.00, 05/04, page 344 of 544
11. Note on ICDR read and ICCR access in slave transmit mode
In I2C bus interface slave transmit mode, do not read ICDR or do not read/write from/to ICCR
during the time shaded in figure 13.33. However, such read and write operations cause no
problem in interrupt handling processing that is generated in synchronization with the rising
edge of the 9th clock pulse because the shaded time has passed before making the transition to
interrupt handling.
To handle interrupts securely, be sure to keep either of the following conditions.
Read ICDR data that has been received so far or read/write from/to ICCR before starting
the receive operation of the next slave address.
Monitor the BC2 to BC0 bit counter in ICMR; when the count is 000 (8th or 9th clock
pulse), wait for at least two transfer clock times in order to read ICDR or read/write from/to
ICCR during the time other than the shaded time.
Data transmission
Bit 7
Address reception
SCL
TRS bit
Waveform at problem occurrence
ICDR read and ICCR read/write are disabled
(6 system clock period)
8
R/W A
9
The rise of the 9th clock is detected
SDA
ICDR write
Figure 13.33 ICDR Read and ICCR Access Timing in Slave Transmit Mode
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to 1 in
ICXR.
Rev. 1.00, 05/04, page 345 of 544
12. Note on TRS bit setting in slave mode
In I2C bus interface slave mode, if the TRS bit value in ICCR is set after detecting the rising
edge of the 9th clock pulse or the stop condition before detecting the next rising edge on the
SCL pin (the time indicated as (a) in figure 13.34), the bit value becomes valid immediately
when it is set. However, if the TRS bit is set during the other time (the time indicated as (b) in
figure 13.34), the bit value is suspended and remains invalid until the rising edge of the 9th
clock pulse or the stop condition is detected. Therefore, when the address is received after the
restart condition is input without the stop condition, the effective TRS bit value remains 1
(transmit mode) internally and thus the acknowledge bit is not transmitted after the address has
been received at the 9th clock pulse.
To receive the address in slave mode, clear the TRS bit to 0 during the time indicated as (a) in
figure 13.34. To release the SCL low level that is held by means of the wait function in slave
mode, clear the TRS bit to and then dummy-read ICDR.
Restart condition
Data
transmission Address reception
SCL
TRS
TRS bit setting is suspended in this period
ICDR dummy read
TRS bit setting
(a) (b)
8
A
9 123 456 789
The rise of the 9th clock is detected
SDA
The rise of the 9th clock is detected
Figure 13.34 TRS Bit Set Timing in Slave Mode
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to 1 in
ICXR.
Rev. 1.00, 05/04, page 346 of 544
13. Note on ICDR read in transmit mode and ICDR write in receive mode
If ICDR is read in transmit mode (TRS = 1) or ICDR is written to in receive mode (TRS = 0),
the SCL pin may not be held low in some cases after transmit/receive operation has been
completed, thus inconveniently allowing clock pulses to be output on the SCL bus line before
ICDR is accessed correctly. To access ICDR correctly, read ICDR after setting receive mode
or write to ICDR after setting transmit mode.
14. Note on ACKE and TRS bits in slave mode
In the I2C bus interface, if 1 is received as the acknowledge bit value (ACKB = 1) in transmit
mode (TRS = 1) and then the address is received in slave mode without performing appropriate
processing, interrupt handling may start at the rising edge of the 9th clock pulse even when the
address does not match. Similarly, if the start condition or address is transmitted from the
master device in slave transmit mode (TRS = 1), the IRIC flag may be set after the ICDRE flag
is set and 1 received as the acknowledge bit value (ACKB = 1), thus causing an interrupt
source even when the address does not match.
To use the I2C bus interface module in slave mode, be sure to follow the procedures below.
A. When having received 1 as the acknowledge bit value for the last transmit data at the end
of a series of transmit operation, clear the ACKE bit in ICCR once to initialize the ACKB
bit to 0.
B. Set receive mode (TRS = 0) before the next start condition is input in slave mode.
Complete transmit operation by the procedure shown in figure 13.23, in order to switch
from slave transmit mode to slave receive mode.
15. Note on Arbitration Lost in Master Mode
The I2C bus interface recognizes the data in transmit/receive frame as an address when
arbitration is lost in master mode and a transition to slave receive mode is automatically
carried out.
When arbitration is lost not in the first frame but in the second frame or subsequent frame,
transmit/receive data that is not an address is compared with the value set in the SAR or SARX
register as an address. If the receive data matches with the address in the SAR or SARX
register, the I2C bus interface erroneously recognizes that the address call has occurred. (See
figure 13.35.)
In multi-master mode, a bus conflict could happen. When the I2C bus interface is operated in
master mode, check the state of the AL bit in the ICSR register every time after one frame of
data has been transmitted or received.
When arbitration is lost during transmitting the second frame or subsequent frame, take
avoidance measures.
Rev. 1.00, 05/04, page 347 of 544
SASLA R/W
SASLA R/WA
DATA2
SASLA R/WASLA R/W
A
DATA3
A
DATA4
DATA1
I2C bus interface
(Master transmit mode)
Transmit data match
Transmit timing match
Receive address is ignored Automatically transferred to slave
receive mode
Receive data is recognized as an
address
When the receive data matches to
the address set in the SAR or SARX
register, the I2C bus interface operates
as a slave device.
Arbitration is lost
The AL flag in ICSR is set to 1
Transmit data does not match
Other device
(Master transmit mode)
I2C bus interface
(Slave receive mode)
Data contention
Figure 13.35 Diagram of Erroneous Operation when Arbitration is Lost
Though it is prohibited in the normal I2C protocol, the same problem may occur when the MST
bit is erroneously set to 1 and a transition to master mode is occurred during data transmission
or reception in slave mode. In multi-master mode, pay attention to the setting of the MST bit
when a bus conflict may occur. In this case, the MST bit in the ICCR register should be set to 1
according to the order below.
A. Make sure that the BBSY flag in the ICCR register is 0 and the bus is free before setting
the MST bit.
B. Set the MST bit to 1.
C. To confirm that the bus was not entered to the busy state while the MST bit is being set,
check that the BBSY flag in the ICCR register is 0 immediately after the MST bit has been
set.
Note: Above restriction can be cleared by setting bits FNC1 and FNC0 in the ICXR register.
13.6.1 Module Stop Mode Setting
The IIC operation can be enabled or disabled using the module stop control register. The initial
setting is for the IIC operation to be halted. Register access is enabled by canceling module stop
mode. For details, see section 20, Power-Down Modes.
Rev. 1.00, 05/04, page 348 of 544
IFKEY10A_000020020700 Rev. 1.00, 05/04, page 349 of 544
Section 14 Keyboard Buffer Controller
This LSI has three on-chip keyboard buffer controller channels. The keyboard buffer controller is
provided with functions conforming to the PS/2 interface specifications.
Data transfer using the keyboard buffer controller employs a data line (KD) and a clock line
(KCLK), providing economical use of connectors, board surface area, etc. Figure 14.1 shows a
block diagram of the keyboard buffer controller.
14.1 Features
Conforms to PS/2 interface specifications
Direct bus drive (via the KCLK and KD pins)
Interrupt sources: on completion of data reception and on detection of clock edge
Error detection: parity error and stop bit monitoring
KD
(PS2AD,
PS2BD,
PS2CD)
KDI
KCLKI
KDO
KCLKO
Parity
Register counter value
KBI interrupt
KCLK
(PS2AC,
PS2BC,
PS2CC)
[Legend]
KD: KBC data I/O pin
KCLK: KBC clock I/O pin
KBBR: Keyboard data buffer register
KBCRH: Keyboard control register H
KBCRL: Keyboard control register L
Control
logic
KBBR
KBCRH
KBCRL
Bus interface
Internal
data bus
Module data bus
Figure 14.1 Block Diagram of Keyboard Buffer Controller
Rev. 1.00, 05/04, page 350 of 544
Figure 14.2 shows how the keyboard buffer controller is connected.
Vcc
KCLK in
KCLK out
KD in
KD out
Keyboard buffer controller
(This LSI)
System side
KCLK in
KCLK out
KD in
KD out
I/F
Keyboard side
Vcc
Clock
Data
Figure 14.2 Keyboard Buffer Controller Connection
14.2 Input/Output Pins
Table 14.1 lists the input/output pins used by the keyboard buffer controller.
Table 14.1 Pin Configuration
Channel Name Abbreviation* I/O Function
KBC clock I/O pin (KCLK0) PS2AC I/O KBC clock input/output 0
KBC data I/O pin (KD0) PS2AD I/O KBC data input/output
KBC clock I/O pin (KCLK1) PS2BC I/O KBC clock input/output 1
KBC data I/O pin (KD1) PS2BD I/O KBC data input/output
KBC clock I/O pin (KCLK2) PS2CC I/O KBC clock input/output 2
KBC data I/O pin (KD2) PS2CD I/O KBC data input/output
Note: * These are the external I/O pin names. In the text, clock I/O pins are referred to as KCLK
and data I/O pins as KD, omitting the channel designations.
Rev. 1.00, 05/04, page 351 of 544
14.3 Register Descriptions
The keyboard buffer controller has the following registers for each channel.
Keyboard control register H (KBCRH)
Keyboard control register L (KBCRL)
Keyboard data buffer register (KBBR)
14.3.1 Keyboard Control Register H (KBCRH)
KBCRH indicates the operating status of the keyboard buffer controller.
Bit Bit Name
Initial
Value R/W Description
7 KBIOE 0 R/W Keyboard In/Out Enable
Selects whether or not the keyboard buffer controller is
used.
0: The keyboard buffer controller is non-operational
(KCLK and KD signal pins have port functions)
1: The keyboard buffer controller is enabled for
transmission and reception (KCLK and KD signal
pins are in the bus drive state)
6 KCLKI 1 R/W Keyboard Clock In
Monitors the KCLK I/O pin. This bit cannot be modified.
0: KCLK I/O pin is low
1: KCLK I/O pin is high
5 KDI 1 R/W Keyboard Data In:
Monitors the KDI I/O pin. This bit cannot be modified.
0: KD I/O pin is low
1: KD I/O pin is high
4 KBFSEL 1 R/W Keyboard Buffer Register Full Select
Selects whether the KBF bit is used as the keyboard
buffer register full flag or as the KCLK fall interrupt flag.
When KBFSEL is cleared to 0, the KBE bit in KBCRL
should be cleared to 0 to disable reception.
0: KBF bit is used as KCLK fall interrupt flag
1: KBF bit is used as keyboard buffer register full flag
Rev. 1.00, 05/04, page 352 of 544
Bit Bit Name
Initial
Value R/W Description
3 KBIE 0 R/W Keyboard Interrupt Enable
Enables or disables interrupts from the keyboard buffer
controller to the CPU.
0: Interrupt requests are disabled
1: Interrupt requests are enabled
2 KBF 0 R/(W)* Keyboard Buffer Register Full
Indicates that data reception has been completed and
the received data is in KBBR.
0: [Clearing condition]
Read KBF when KBF =1, then write 0 in KBF
1: [Setting conditions]
When data has been received normally and has
been transferred to KBBR while KBFSEL = 1
(keyboard buffer register full flag)
When a KCLK falling edge is detected while
KBFSEL = 0 (KCLK interrupt flag)
1 PER 0 R/(W)* Parity Error
Indicates that an odd parity error has occurred.
0: [Clearing condition]
Read PER when PER =1, then write 0 in PER
1: [Setting condition]
When an odd parity error occurs
0 KBS 0 R Keyboard Stop
Indicates the receive data stop bit. Valid only when
KBF = 1.
0: 0 stop bit received
1: 1 stop bit received
Note: * Only 0 can be written for clearing the flag.
Rev. 1.00, 05/04, page 353 of 544
14.3.2 Keyboard Control Register L (KBCRL)
KBCRL enables the receive counter count and controls the keyboard buffer controller pin output.
Bit Bit Name Initial
Value R/W Description
7 KBE 0 R/W Keyboard Enable
Enables or disables loading of receive data into KBBR.
0: Loading of receive data into KBBR is disabled
1: Loading of receive data into KBBR is enabled
6 KCLKO 1 R/W Keyboard Clock Out
Controls KBC clock I/O pin output.
0: KBC clock I/O pin is low
1: KBC clock I/O pin is high
5 KDO 1 R/W Keyboard Data Out
Controls KBC data I/O pin output.
0: KBC data I/O pin is low
1: KBC data I/O pin is high
4 — 1 Reserved
This bit is always read as 1 and cannot be modified.
3
2
1
0
RXCR3
RXCR2
RXCR1
RXCR0
0
0
0
0
R
R
R
R
Receive Counter
These bits indicate the received data bit. Their value is
incremented on the fall of KCLK. These bits cannot be
modified.
The receive counter is initialized to 0000 by a reset and
when 0 is written in KBE. Its value returns to 0000 after
a stop bit is received.
0000: —
0001: Start bit
0010: KB0
0011: KB1
0100: KB2
0101: KB3
0110: KB4
0111: KB5
1000: KB6
1001: KB7
1010: Parity bit
1011: —
11- - : —
Rev. 1.00, 05/04, page 354 of 544
14.3.3 Keyboard Data Buffer Register (KBBR)
KBBR stores receive data. Its value is valid only when KBF = 1.
Bit Bit Name Initial
Value R/W Description
7
6
5
4
3
2
1
0
KB7
KB6
KB5
KB4
KB3
KB2
KB1
KB0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Keyboard Data 7 to 0
8-bit read only data.
Initialized to H'00 by a reset, in standby mode, watch
mode, subactive mode, subsleep mode, and module
stop mode, and when KBIOE is cleared to 0.
Rev. 1.00, 05/04, page 355 of 544
14.4 Operation
14.4.1 Receive Operation
In a receive operation, both KCLK (clock) and KD (data) are outputs on the keyboard side and
inputs on this LSI chip (system) side. KD receives a start bit, 8 data bits (LSB-first), an odd parity
bit, and a stop bit, in that order. The KD value is valid when KCLK is low. A sample receive
processing flowchart is shown in figure 14.3, and the receive timing in figure 14.4.
Start
Set KBIOE bit
Read KBCRH
KCLKI
and KDI bits both 1?
Set KBE bit
Receive enabled state
KBF = 1?
PER = 0?
KBS = 1?
Read KBBR
Receive data processing
Clear KBF flag
(receive enabled state)
Keyboard side in data
transmission state.
Execute receive abort
processing.
Error handling
[1] Set the KBIOE bit to 1 in KBCRL.
[2] Read KBCRH, and if the KCLKI
and KDI bits are both 1, set the
KBE bit (receive enabled state).
[3] Detect the start bit output on the
keyboard side and receive data in
synchronization with the fall of
KCLK.
[4] When a stop bit is received, the
keyboard buffer controller drives
KCLK low to disable keyboard
transmission (automatic I/O inhibit).
If the KBIE bit is set to 1 in KBCRH,
an interrupt request is sent to the
CPU at the same time.
[5] Perform receive data processing.
[6] Clear the KBF flag to 0 in KBCRL.
At the same time, the system
automatically drives KCLK high,
setting the receive enabled state.
The receive operation can be
continued by repeating steps [3] to [6].
[1]
[2]
[3]
[4]
[5]
[6]
Yes
No
Yes
Yes
Yes
No
No
No
Figure 14.3 Sample Receive Processing Flowchart
Rev. 1.00, 05/04, page 356 of 544
123
KCLK
(pin state)
KD
(pin state)
KCLK
(input)
KCLK
(output)
KB7 to KB0
PER
KBS
KBF
Start
bit Parity bit Stop bit
Receive processing/
error handling
Automatic I/O inhibit
Previous data Receive data
Flag cleared
910 11
701
KB0 KB1
[1] [2] [3] [4] [5] [6]
Figure 14.4 Receive Timing
14.4.2 Transmit Operation
In a transmit operation, KCLK (clock) is an output on the keyboard side, and KD (data) is an
output on the chip (system) side. KD outputs a start bit, 8 data bits (LSB-first), an odd parity bit,
and a stop bit, in that order. The KD value is valid when KCLK is high. A sample transmit
processing flowchart is shown in figure 14.5, and the transmit timing in figure 14.6.
Rev. 1.00, 05/04, page 357 of 544
Start
Set KBIOE bit
KCLKI = 0?
Read KBCRH
KCLKI
and KDI bits both
1?
Set I/O inhibit (KCLKO = 0)
KBE = 0
(KBBR reception prohibited)
KDO remains at 1
Wait
Set start bit (KDO = 0)
Set I/O inhibit (KCLKO = 1)
KCLKO remains at 0
KDO remains at 0
i = 0
Read KBCRH
Set transmit data
(KDO = D(i))
Read KBCRH
KCLKI = 1?
i = i + 1
i > 9?
Read KBCRH
KCLKI = 1?
Yes
No
i = 0 to 7: Transmit data
i = 8: Parity bit
i = 9: Stop bit
No
Yes
Yes
Yes
Yes
No
No
No
1
2
[1] Set the KBE bit to 1 in KBCRH.
[2] Read KBCRH, and if the KCLKI and KDI
bits are both 1, write 0 in the KCLKO bit
(set I/O inhibit).
[3] Write 0 in the KBE bit (prohibit KBBR
receive operation).
[4] Write 0 in the KDO bit (set start bit).
[5] Write 1 in the KCLKO bit (clear I/O inhibit).
[6] Read KBCRH, and when KCLKI = 0, set
the transmit data in the KDO bit (LSB-
first). Next, set the parity bit and stop bit in
the KDO bit.
[7] After transmitting the stop bit, read KBCRL
and confirm that KDI = 0 (receive
completed notification from the keyboard).
[8] Read KBCRH. Confirm that the KCLKI
and KDI bits are both 1.
The transmit operation can be continued by
repeating steps [2] to [8].
[1]
[2]
[3]
[4]
[5]
[6]
(Continued on
next page)
(Continued on next page)
Figure 14.5 Sample Transmit Processing Flowchart (1)
Rev. 1.00, 05/04, page 358 of 544
Read KBCRH
Transmit end state
(KCLK = high, KD = high)
Yes
Note: * To switch to reception after transmission, set KBE to 1 (KBBR receive enable) while KCLKI is low.
1
KCLKI = 0? No
KDI = 0?
Read KBCRH
KCLK = 1?
Yes
Yes
No
No Error handling
To receive operation or
transmit operation
Keyboard side in data
transmission state.
Execute receive abort
processing.
2
*
[7]
[8]
Figure 14.5 Sample Transmit Processing Flowchart (2)
1
01
01
7
7
2891011
KCLK
(pin state)
KD
(pin state)
KCLK
(output)
KD
(output)
KCLK
(input)
KD
(input)
Start bit
Start bit
Parity bit Stop bit
Parity bit Stop bit
I/O inhibit
Receive
completed
notification
[1] [2] [3] [4] [5] [6] [7] [8]
Figure 14.6 Transmit Timing
Rev. 1.00, 05/04, page 359 of 544
14.4.3 Receive Abort
This LSI (system side) can forcibly abort transmission from the device connected to it (keyboard
side) in the event of a protocol error, etc. In this case, the system holds the clock low. During
reception, the keyboard also outputs a clock for synchronization, and the clock is monitored when
the keyboard output clock is high. If the clock is low at this time, the keyboard judges that there is
an abort request from the system, and data transmission from the keyboard is aborted. Thus the
system can abort reception by holding the clock low for a certain period. A sample receive abort
processing flowchart is shown in figure 14.7, and the receive abort timing in figure 14.8.
Read KBCRL
KBF = 0?
RXCR3 to RXCR0
B'1001?
Disable receive abort
requests
Yes
Start
Receive state
Read KBCRH Processing 1
KCLKO = 0
(receive abort request)
Retransmit
command transmission
(data)?
KBE = 0
(disable KBBR reception
and clear receive counter)
Set start bit
(KDO = 0)
Clear I/O inhibit
(KCLKO = 1)
Transmit data
To transmit operation
KBE = 0
(disable KBBR reception
and clear receive counter)
KBE = 1
(enable KB operation)
Clear I/O inhibit
(KCLKO = 1)
To receive operation
[1] Read KBCRL, and if KBF = 1,
perform processing 1.
[2] Read KBCRH, and if the value of
bits RXCR3 to RXCR0 is less
than B'1001, write 0 in KCLKO to
abort reception.
If the value of bits RXCR3 to
RXCR0 is B'1001 or greater, wait
until stop bit reception is
completed, then perform receive
data processing, and proceed to
the next operation.
[3] If the value of bits RXCR3 to
RXCR0 is B'1001 or greater, the
parity bit is being received. With
the PS2 interface, a receive abort
request following parity bit
reception is disabled. Wait until
stop bit reception is completed,
perform receive data processing
and clear the KBF flag, then
proceed to the next operation.
Yes
No
No
No
Yes
[1]
[2][3]
Figure 14.7 Sample Receive Abort Processing Flowchart (1)
Rev. 1.00, 05/04, page 360 of 544
Receive data processing
Clear KBF flag
(KCLK = High)
Processing 1
Receive operation ends
normally
[1] On the system side, drive the KCLK pin low, setting
the I/O inhibit state.
[1]
Transmit enabled state.
If there is transmit data, the data is transmitted.
Figure 14.7 Sample Receive Abort Processing Flowchart (2)
Keyboard side monitors clock during
receive operation (transmit operation
as seen from keyboard), and aborts
receive operation during this period.
KCLK
(pin state)
KD
(pin state)
KCLK
(input)
KCLK
(output)
KD
(input)
KD
(output)
Reception in progress Receive abort request
Transmit operation
Start bit
Figure 14.8 Receive Abort and Transmit Start
(Transmission/Reception Switchover) Timing
Rev. 1.00, 05/04, page 361 of 544
14.4.4 KCLKI and KDI Read Timing
Figure 14.9 shows the KCLKI and KDI read timing.
T1T2
φ
*
Internal read
signal
KCLK, KD
(pin state)
KCLKI, KDI
(register)
Internal data bus
(read data)
Note: * The
φ
clock shown here is scaled by 1/N in medium-speed mode when the operating mode is active mode.
Figure 14.9 KCLKI and KDI Read Timing
14.4.5 KCLKO and KDO Write Timing
Figure 14.10 shows the KLCKO and KDO write timing and the KCLK and KD pin states.
Internal write
signal
φ
*
KCLKO, KDO
(register)
KCLK, KD
(pin state)
Note: *The
φ
clock shown here is scaled by 1/N in medium-speed mode when the operating mode is active mode.
T
1
T
2
Figure 14.10 KCLKO and KDO Write Timing
Rev. 1.00, 05/04, page 362 of 544
14.4.6 KBF Setting Timing and KCLK Control
Figure 14.11 shows the KBF setting timing and the KCLK pin states.
KCLK
(pin)
φ
*
Internal
KCLK
Falling edge
signal
RXCR3 to
RXCR0
KCLK
(output)
KBF
11th fall
Automatic I/O inhibit
B'0000B'1010
Note: *The
φ
clock shown here is scaled by 1/N in medium-speed mode when the operating
mode is active mode.
Figure 14.11 KBF Setting and KCLK Automatic I/O Inhibit Generation Timing
Rev. 1.00, 05/04, page 363 of 544
14.4.7 Receive Timing
Figure 14.12 shows the receive timing.
N + 1 N + 2N
KCLK (pin)
Note: *The φ clock shown here is scaled by 1/N in medium-speed mode when the operating mode is active
mode.
KD (pin)
Internal
KCLK (KCLKI)
Falling edge
signal
RXCR3 to
RXCR0
Internal KD
(KDI)
KBBR7 to
KBBR0
φ*
Figure 14.12 Receive Counter and KBBR Data Load Timing
Rev. 1.00, 05/04, page 364 of 544
14.4.8 KCLK Fall Interrupt Operation
In this device, clearing the KBFSEL bit to 0 in KBCRH enables the KBF bit in KBCRL to be used
as a flag for the interrupt generated by the fall of KCLK input.
Figure 14.13 shows the setting method and an example of operation.
Start
Set KBIOE
KBF = 1
(interrupt generated)
KBE = 0
(KBBR reception
disabled)
Interrupt handling
Clear KBF
KCLK pin
fall detected?
KBFSEL = 0
KBIE = 1
(KCLK falling edge
interrupts enabled)
Ye s
No
KCLK
(pin state)
KBF bit
Interrupt
generated
Interrupt
generated
Cleared
by software
Note: * The KBF setting timing is the same as the timing of KBF setting and KCLK automatic I/O inhibit bit generation in
figure 14.11. When the KBF bit is used as the KCLK input fall interrupt flag, the automatic I/O inhibit function does
not operate.
Figure 14.13 Example of KCLK Input Fall Interrupt Operation
Rev. 1.00, 05/04, page 365 of 544
14.5 Usage Notes
14.5.1 KBIOE Setting and KCLK Falling Edge Detection
When KBIOE is 0, the internal KCLK and internal KD settings are fixed at 1. Therefore, if the
KCLK pin is low when the KBIOE bit is set to 1, the edge detection circuit operates and the
KCLK falling edge is detected.
If the KBFSEL bit and KBE bit are both 0 at this time, the KBF bit is set. Figure 14.14 shows the
timing of KBIOE setting and KCLK falling edge detection.
T
1
T
2
φ
KCLK (pin)
Internal KCLK
(KCLKI)
Falling edge
signal
KBIOE
KBFSEL
KBE
KBF
Figure 14.14 KBIOE Setting and KCLK Falling Edge Detection Timing
Rev. 1.00, 05/04, page 366 of 544
14.5.2 Module Stop Mode Setting
Keyboard buffer controller operation can be enabled or disabled using the module stop control
register. The initial setting is for keyboard buffer controller operation to be halted. Register access
is enabled by canceling module stop mode. For details, refer to section 20, Power-Down Modes.
IFHSTL0A_020020040200 Rev. 1.00, 05/04, page 367 of 544
Section 15 Host Interface (LPC)
This LSI has an on-chip LPC interface.
The LPC performs serial transfer of cycle type, address, and data, synchronized with the 33 MHz
PCI clock. It uses four signal lines for address/data, and one for host interrupt requests. This LPC
module supports only I/O read cycle and I/O write cycle transfers.
It is also provided with power-down functions that can control the PCI clock and shut down the
host interface.
15.1 Features
Supports LPC interface I/O read cycles and I/O write cycles
Uses four signal lines (LAD3 to LAD0) to transfer the cycle type, address, and data.
Uses three control signals: clock (LCLK), reset (LRESET), and frame (LFRAME).
Has three register sets comprising data and status registers
The basic register set comprises three bytes: an input register (IDR), output register (ODR),
and status register (STR).
Channels 1 and 2 have fixed I/O addresses of H'60/H'64 and H'62/H'66, respectively. A fast
A20 gate function is also provided.
The I/O address can be set for channel 3. Sixteen bidirectional data register bytes can be
manipulated in addition to the basic register set.
Supports SERIRQ
Host interrupt requests are transferred serially on a single signal line (SERIRQ).
On channel 1, HIRQ1 and HIRQ12 can be generated.
On channels 2 and 3, SMI, HIRQ6, and HIRQ9 to HIRQ11 can be generated.
Operation can be switched between quiet mode and continuous mode.
The CLKRUN signal can be manipulated to restart the PCI clock (LCLK).
Eleven interrupt sources
The LPC module can be shut down by inputting the LPCPD signal.
Three pins, PME, LSMI, and LSCI, are provided for general input/output.
Rev. 1.00, 05/04, page 368 of 544
Figure 15.1 shows a block diagram of the LPC.
TWR1–15
IDR3
IDR2
IDR1
H'0060/64
H'0062/66
LADR3
SIRQCR0
SIRQCR1
TWR0MW
TWR1–15
ODR3
ODR2
ODR1
STR3
STR2
STR1
HICR0
HICR1
HICR2
HICR3
TWR0SW
LSCIE
LSCIB
LSCI input
PB1 I/O
LSMIE
LSMIB
LSMI input
PB0 I/O
PMEE
PMEB
PME input
P80 I/O
LAD0 to
LAD3
SERIRQ
CLKRUN
LSCI
LSMI
PME
GA20
LPCPD
LFRAME
LRESET
LCLK
IBFI1
IBFI2
IBFI3
ERRI
Module data bus
Cycle detection
Serial parallel conversion
Serial parallel conversion
Address match
SYNC output
Parallel serial conversion
Control logic
Internal interrupt
control
HISEL
[Legend]
HICR0 to HICR3: Host interface control registers 0 to 3
LADR3H, 3L: LPC channel 3 address register 3H and 3L
IDR1 to IDR3: Input data registers 1 to 3
ODR1 to DOR3: Output data registers 1 to 3
STR1 to STR3: Status registers 1 to 3
TWR0MW: Two-way register 0MW
TWR0SW: Two-way register 0SW
TWR1 to TWR15: Two-way data registers 1 to 15
SERIRQ0, 1: SERIEQ control registers 0 and 1
HISEL: Host interface select register
Figure 15.1 Block Diagram of LPC
Rev. 1.00, 05/04, page 369 of 544
15.2 Input/Output Pins
Table 15.1 lists the input and output pins of the LPC module.
Table 15.1 Pin Configuration
Name Abbreviation Port I/O Function
LPC address/
data 3 to 0
LAD3 to
LAD0
P33 to
P30
Input/
output
Serial (4-signal-line) transfer cycle
type/address/data signals,
synchronized with LCLK
LPC frame LFRAME P34 Input*1 Transfer cycle start and forced
termination signal
LPC reset LRESET P35 Input*1 LPC interface reset signal
LPC clock LCLK P36 Input 33 MHz PCI clock signal
Serialized interrupt request SERIRQ P37 Input/
output*1
Serialized host interrupt request
signal, synchronized with LCLK
(SMI, IRQ1, IRQ6, IRQ9 to
IRQ12)
LSCI general output LSCI PB1 Output*1, *2General output
LSMI general output LSMI PB0 Output*1, *2General output
PME general output PME P80 Output*1, *2General output
GATE A20 GA20 P81 Output*1, *2A20 gate control signal output
LPC clock run CLKRUN P82 Input/
output*1, *2
LCLK restart request signal in
case of serial host interrupt
request
LPC power-down LPCPD P83 Input*1 LPC module shutdown signal
Notes: 1. Pin state monitoring input is possible in addition to the LPC interface control
input/output function.
2. Only 0 can be output. If 1 is output, the pin goes to the high-impedance state, so an
external resistor is necessary to pull the signal up to VCC.
Rev. 1.00, 05/04, page 370 of 544
15.3 Register Descriptions
The LPC has the following registers.
Host interface control register 0 (HICR0)
Host interface control register 1 (HICR1)
Host interface control register 2 (HICR2)
Host interface control register 3 (HICR3)
LPC channel 3 address registers (LADR3H, LADR3L)
Input data register 1 (IDR1)
Output data register 1 (ODR1)
Status register 1 (STR1)
Input data register 2 (IDR2)
Output data register 2 (ODR2)
Status register 2 (STR2)
Input data register 3 (IDR3)
Output data register 3 (ODR3)
Status register 3 (STR3)
Bidirectional data registers 0 to 15 (TWR0 to TWR15)
SERIRQ control register 0 (SIRQCR0)
SERIRQ control register 1 (SIRQCR1)
Host interface select register (HISEL)
Rev. 1.00, 05/04, page 371 of 544
15.3.1 Host Interface Control Registers 0 and 1 (HICR0, HICR1)
HICR0 and HICR1 contain control bits that enable or disable host interface functions, control bits
that determine pin output and the internal state of the host interface, and status flags that monitor
the internal state of the host interface.
HICR0
R/W
Bit Bit Name
Initial
Value Slave Host Description
7
6
5
LPC3E
LPC2E
LPC1E
0
0
0
R/W
R/W
R/W
LPC Enable 3 to 1
Enable or disable the host interface function in single-
chip mode. When the host interface is enabled (one of
the three bits is set to 1), processing for data transfer
between the slave processor (this LSI) and the host
processor is performed using pins LAD3 to LAD0,
LFRAME, LRESET, LCLK, SERIRQ, CLKRUN, and
LPCPD.
LPC3E
0: LPC channel 3 operation is disabled
No address (LADR3) matches for IDR3, ODR3,
STR3, or TWR0 to TWR15
1: LPC channel 3 operation is enabled
LPC2E
0: LPC channel 2 operation is disabled
No address (H'0062, 66) matches for IDR2, ODR2,
or STR2
1: LPC channel 2 operation is enabled
LPC1E
0: LPC channel 1 operation is disabled
No address (H'0060, 64) matches for IDR1, ODR1,
or STR1
1: LPC channel 1 operation is enabled
Rev. 1.00, 05/04, page 372 of 544
R/W
Bit Bit Name
Initial
Value Slave Host Description
4 FGA20E 0 R/W Fast A20 Gate Function Enable
Enables or disables the fast A20 gate function. When
the fast A20 gate is disabled, the normal A20 gate can
be implemented by firmware operation of the P81
output.
When the fast A20 gate function is enabled, the DDR bit
for P81 must not be set to 1.
0: Fast A20 gate function disabled
Other function of pin P81 is enabled
GA20 output internal state is initialized to 1
1: Fast A20 gate function enabled
GA20 pin output is open-drain (external VCC pull-up
resistor required)
3 SDWNE 0 R/W LPC Software Shutdown Enable
Controls host interface shutdown. For details of the LPC
shutdown function, and the scope of initialization by an
LPC reset and an LPC shutdown, see section 15.4.4,
Host Interface Shutdown Function (LPCPD).
0: Normal state, LPC software shutdown setting enabled
[Clearing conditions]
Writing 0
LPC hardware reset or LPC software reset
LPC hardware shutdown release (rising edge of
LPCPD signal)
1: LPC hardware shutdown state setting enabled
Hardware shutdown state when LPCPD signal is low
[Setting condition]
Writing 1 after reading SDWNE = 0
Rev. 1.00, 05/04, page 373 of 544
R/W
Bit Bit Name
Initial
Value Slave Host Description
2 PMEE 0 R/W PME output Enable
Controls PME output in combination with the PMEB bit
in HICR1. PME pin output is open-drain, and an external
pull-up resistor is needed to pull the output up to VCC
When the PME output function is used, the DDR bit for
P80 must not be set to 1.
PMEE PMEB
0 x: PME output disabled, other function of
pin is enabled
1 0: PME output enabled, PME pin output
goes to 0 level
1 1: PME output enabled, PME pin output is
high-impedance
1 LSMIE 0 R/W LSMI output Enable
Controls LSMI output in combination with the LSMIB bit
in HICR1. LSMI pin output is open-drain, and an external
pull-up resistor is needed to pull the output up to VCC
When the LSMI output function is used, the DDR bit for
PB0 must not be set to 1.
LSMIE LSMIB
0 x: LSMI output disabled, other function of
pin is enabled
1 0: LSMI output enabled, LSMI pin output
goes to 0 level
1 1: LSMI output enabled, LSMI pin output is
high-impedance
0 LSCIE 0 R/W LSCI output Enable
Controls LSCI output in combination with the LSCIB bit
in HICR1. LSCI pin output is open-drain, and an external
pull-up resistor is needed to pull the output up to VCC
When the LSCI output function is used, the DDR bit for
PB1 must not be set to 1.
LSCIE LSCIB
0 x: LSCI output disabled, other function of
pin is enabled
1 0: LSCI output enabled, LSCI pin output
goes to 0 level
1 1: LSCI output enabled, LSCI pin output is
high-impedance
[Legend]
X: Don't care
Rev. 1.00, 05/04, page 374 of 544
HICR1
R/W
Bit Bit Name
Initial
Value
Slave Host Description
7 LPCBSY 0 R/W LPC Busy
Indicates that the host interface is processing a transfer
cycle.
0: Host interface is in transfer cycle wait state
Bus idle, or transfer cycle not subject to processing
is in progress
Cycle type or address indeterminate during transfer
cycle
[Clearing conditions]
LPC hardware reset or LPC software reset
LPC hardware shutdown or LPC software shutdown
Forced termination (abort) of transfer cycle subject
to processing
Normal termination of transfer cycle subject to
processing
1: Host interface is performing transfer cycle processing
[Setting condition]
Match of cycle type and address
6 CLKREQ 0 R LCLK Request
Indicates that the host interface's SERIRQ output is
requesting a restart of LCLK.
0: No LCLK restart request
[Clearing conditions]
LPC hardware reset or LPC software reset
LPC hardware shutdown or LPC software shutdown
SERIRQ is set to continuous mode
There are no further interrupts for transfer to the
host in quiet mode
1: LCLK restart request issued
[Setting condition]
In quiet mode, SERIRQ interrupt output becomes
necessary while LCLK is stopped
Rev. 1.00, 05/04, page 375 of 544
R/W
Bit Bit Name
Initial
Value Slave Host Description
5 IRQBSY 0 R SERIRQ Busy
Indicates that the host interface's SERIRQ signal is
engaged in transfer processing.
0: SERIRQ transfer frame wait state
[Clearing conditions]
LPC hardware reset or LPC software reset
LPC hardware shutdown or LPC software shutdown
End of SERIRQ transfer frame
1: SERIRQ transfer processing in progress
[Setting condition]
Start of SERIRQ transfer frame
4 LRSTB 0 LPC Software Reset Bit
Resets the host interface. For the scope of initialization
by an LPC reset, see section 15.4.4, Host Interface
Shutdown Function (LPCPD).
0: Normal state
[Clearing conditions]
Writing 0
LPC hardware reset
1: LPC software reset state
[Setting condition]
Writing 1 after reading LRSTB = 0
Rev. 1.00, 05/04, page 376 of 544
R/W
Bit Bit Name
Initial
Value Slave Host Description
3 SDWNB 0 R/W LPC Software Shutdown Bit
Controls host interface shutdown. For details of the LPC
shutdown function, and the scope of initialization by an
LPC reset and an LPC shutdown, see section 15.4.4,
Host Interface Shutdown Function (LPCPD).
0: Normal state
[Clearing conditions]
Writing 0
LPC hardware reset or LPC software reset
LPC hardware shutdown
LPC hardware shutdown release
(rising edge of LPCPD signal when SDWNE = 0)
1: LPC software shutdown state
[Setting condition]
Writing 1 after reading SDWNB = 0
2 PMEB 0 R/W PME Output Bit
Controls PME output in combination with the PMEE bit.
For details, refer to description on the PMEE bit in
HICR0.
1 LSMIB 0 R/W LSMI Output Bit
Controls LSMI output in combination with the LSMIE bit.
For details, refer to description on the LSMIE bit in
HICR0.
0 LSCIB 0 R/W LSCI output Bit
Controls LSCI output in combination with the LSCIE bit.
For details, refer to description on the LSCIE bit in
HICR0.
Rev. 1.00, 05/04, page 377 of 544
15.3.2 Host Interface Control Registers 2 and 3 (HICR2, HICR3)
Bits 6 to 0 in HICR2 control interrupts from the host interface (LPC) module to the slave
processor (this LSI). Bit 7 in HICR2 and HICR3 monitor host interface pin states.
The pin states can be monitored regardless of the host interface operating state or the operating
state of the functions that use pin multiplexing.
HICR2
R/W
Bit Bit Name Initial
Value Slave Host Description
7 GA20 Undefined R GA20 Pin Monitor
6 LRST 0 R/(W)* LPC Reset Interrupt Flag
This bit is a flag that generates an ERRI interrupt when
an LPC hardware reset occurs.
0: [Clearing conditions]
Writing 0 after reading LRST = 1
1: [Setting condition]
LRESET pin falling edge detection
5 SDWN 0 R/(W)* LPC Shutdown Interrupt Flag
This bit is a flag that generates an ERRI interrupt when
an LPC hardware shutdown request is generated.
0: [Clearing conditions]
Writing 0 after reading SDWN = 1
LPC hardware reset and LPC software reset
1: [Setting condition]
LPCPD pin falling edge detection
4 ABRT 0 R/(W)* LPC Abort Interrupt Flag
This bit is a flag that generates an ERRI interrupt when
a forced termination (abort) of an LPC transfer cycle
occurs.
0: [Clearing conditions]
Writing 0 after reading ABRT = 1
LPC hardware reset and LPC software reset
LPC hardware shutdown and LPC software
shutdown
1: [Setting condition]
LFRAME pin falling edge detection during LPC
transfer cycle
Rev. 1.00, 05/04, page 378 of 544
R/W
Bit Bit Name
Initial
Value Slave Host Description
3 IBFIE3 0 R/W IDR3 and TWR Receive Completion Interrupt Enable
Enables or disables IBFI3 interrupt to the slave
processor (this LSI).
0: Input data register IDR3 and TWR receive completed
interrupt requests disabled
1: [When TWRIE = 0 in LADR3]
Input data register (IDR3) receive completed interrupt
requests enabled
[When TWRIE = 1 in LADR3]
Input data register (IDR3) and TWR receive completed
interrupt requests enabled
2 IBFIE2 0 R/W IDR2 Receive Completion Interrupt Enable
Enables or disables IBFI2 interrupt to the slave
processor (this LSI).
0: Input data register (IDR2) receive completed interrupt
requests disabled
1: Input data register (IDR2) receive completed interrupt
requests enabled
1 IBFIE1 0 R/W IDR1 Receive Completion Interrupt Enable
Enables or disables IBFI1 interrupt to the slave
processor (this LSI).
0: Input data register (IDR1) receive completed interrupt
requests disabled
1: Input data register (IDR1) receive completed interrupt
requests enabled
0 ERRIE 0 R/W Error Interrupt Enable
Enables or disables ERRI interrupt to the slave
processor (this LSI).
0: Error interrupt requests disabled
1: Error interrupt requests enabled
Note: * Only 0 can be written to bits 6 to 4, to clear the flag.
HICR3
R/W
Bit Bit Name Initial Value Slave Host Description
7 LFRAME Undefined R LFRAME Pin Monitor
6 CLKRUN Undefined R CLKRUN Pin Monitor
5 SERIRQ Undefined R SERIRQ Pin Monitor
4 LRESET Undefined R LRESET Pin Monitor
3 LPCPD Undefined R LPCPD Pin Monitor
2 PME Undefined R PME Pin Monitor
1 LSMI Undefined R LSMI Pin Monitor
0 LSCI Undefined R LSCI Pin Monitor
Rev. 1.00, 05/04, page 379 of 544
15.3.3 LPC Channel 3 Address Register (LADR3)
LADR3 comprises two 8-bit readable/writable registers that perform LPC channel-3 host address
setting and control the operation of the bidirectional data registers. The contents of the address
field in LADR3 must not be changed while channel 3 is operating (while LPC3E is set to 1).
LADR3H
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Channel 3 Address Bits 15 to 8:
When LPC3E = 1, an I/O address received in an LPC
I/O cycle is compared with the contents of LADR3.
When determining an IDR3, ODR3, or STR3 address
match, bit 0 of LADR3 is regarded as 0, and the value of
bit 2 is ignored. When determining a TWR0 to TWR15
address match, bit 4 of LADR3 is inverted, and the
values of bits 3 to 0 are ignored. Register selection
according to the bits ignored in address match
determination is as shown in table 15.2.
LADR3L
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Channel 3 Address Bits 7 to 3
2 0 R/W Reserved
This bit is readable/writable, however, only 0 should be
written to this bit.
1 Bit 1 0 R/W Channel 3 Address Bit 1
0 TWRE 0 R/W Bidirectional Data Register Enable
Enables or disables bidirectional data register operation.
0: TWR operation is disabled
TWR-related I/O address match determination is
halted
1: TWR operation is enabled
Rev. 1.00, 05/04, page 380 of 544
Table 15.2 Register Selection
I/O Address
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Transfer
Cycle Host Register Selection
Bit 4 Bit 3 0 Bit 1 0 I/O write IDR3 write, C/D3 0
Bit 4 Bit 3 1 Bit 1 0 I/O write IDR3 write, C/D3 1
Bit 4 Bit 3 0 Bit 1 0 I/O read ODR3 read
Bit 4 Bit 3 1 Bit 1 0 I/O read STR3 read
Bit 4 0 0 0 0 I/O write TWR0MW write
0 0 0 1
Bit 4
1 1 1 1
I/O write TWR1 to TWR15 write
Bit 4 0 0 0 0 I/O read TWR0SW read
0 0 0 1 I/O read
Bit 4
1 1 1 1
TWR1 to TWR15 read
15.3.4 Input Data Registers 1 to 3 (IDR1 to IDR3)
The IDR registers are 8-bit read-only registers for the slave processor (this LSI), and 8-bit write-
only registers for the host processor. The registers selected from the host according to the I/O
address are shown in the following table. For information on IDR3 selection, see section 15.3.3,
LPC Channel 3 Address Register (LADR3). Data transferred in an LPC I/O write cycle is written
to the selected register. The state of bit 2 of the I/O address is latched into the C/D bit in STR, to
indicate whether the written information is a command or data. The initial values of IDR1 to IDR3
are undefined.
I/O Address
Bits 15 to 4 Bit 3 Bit 2 Bit 1 Bit 0 Transfer
Cycle Host Register Selection
0000 0000 0110 0 0 0 0 I/O write IDR1 write, C/D1 0
0000 0000 0110 0 1 0 0 I/O write IDR1 write, C/D1 1
0000 0000 0110 0 0 1 0 I/O write IDR2 write, C/D2 0
0000 0000 0110 0 1 1 0 I/O write IDR2 write, C/D2 1
Rev. 1.00, 05/04, page 381 of 544
15.3.5 Output Data Registers 1 to 3 (ODR1 to ODR3)
The ODR registers are 8-bit readable/writable registers for the slave processor (this LSI), and 8-bit
read-only registers for the host processor. The registers selected from the host according to the I/O
address are shown in the following table. For information on ODR3 selection, see section 15.3.3,
LPC Channel 3 Address Register (LADR3). In an LPC I/O read cycle, the data in the selected
register is transferred to the host. The initial values of ODR1 to ODR3 are undefined.
I/O Address
Bits 15 to 4 Bit 3 Bit 2 Bit 1 Bit 0 Transfer
Cycle Host Register Selection
0000 0000 0110 0 0 0 0 I/O read ODR1 read
0000 0000 0110 0 0 1 0 I/O read ODR2 read
15.3.6 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15)
The TWR registers are sixteen 8-bit readable/writable registers to both the slave processor (this
LSI) and the host processor. In TWR0, however, two registers (TWR0MW and TWR0SW) are
allocated to the same address for both the host address and the slave address. TWR0MW is a
write-only register for the host processor, and a read-only register for the slave processor, while
TWR0SW is a write-only register for the slave processor and a read-only register for the host
processor. When the host and slave processors begin a write, after the respective TWR0 registers
have been written to, access right arbitration for simultaneous access is performed by checking the
status flags to see if those writes were valid. For the registers selected from the host according to
the I/O address, see section 15.3.3, LPC Channel 3 Address Register (LADR3).
Data transferred in an LPC I/O write cycle is written to the selected register; in an LPC I/O read
cycle, the data in the selected register is transferred to the host. The initial values of TWR0 to
TWR15 are undefined.
15.3.7 Status Registers 1 to 3 (STR1 to STR3)
The STR registers are 8-bit registers that indicate status information during host interface
processing. Bits 3, 1, and 0 of STR1 to STR3, and bits 7 to 4 of STR3, are read-only bits for both
the host processor and the slave processor (this LSI). However, only 0 can be written to bit 0 of
STR1 to STR3 and bits 6 and 4 of STR3, from the slave processor (this LSI), in order to clear the
flags to 0. The registers selected from the host processor according to the I/O address are shown in
the following table. For information on STR3 selection, see section 15.3.3, LPC Channel 3
Address Register (LADR3). In an LPC I/O read cycle, the data in the selected register is
transferred to the host processor. The initial values of STR1 to STR3 are H'00.
Rev. 1.00, 05/04, page 382 of 544
I/O Address
Bits 15 to 4 Bit 3 Bit 2 Bit 1 Bit 0 Transfer
Cycle Host Register Selection
0000 0000 0110 0 1 0 0 I/O read STR1 read
0000 0000 0110 0 1 1 0 I/O read STR2 read
STR1
R/W
Bit Bit Name
Initial
Value Slave Host Description
7
6
5
4
DBU17
DBU16
DBU15
DBU14
0
0
0
0
R/W
R/W
R/W
R/W
R
R
R
R
Defined by User
The user can use these bits as necessary.
3 C/D1 0 R R Command/Data
When the host processor writes to an IDR register, bit 2
of the I/O address is written into this bit to indicate
whether IDR contains data or a command.
0: Contents of data register (IDR) are data
1: Contents of data register (IDR) are a command
2 DBU12 0 R/W R Defined by User
The user can use this bit as necessary.
1 IBF1 0 R R Input Buffer Full
Set to 1 when the host processor writes to IDR. This bit
is an internal interrupt source to the slave processor
(this LSI). IBF is cleared to 0 when the slave processor
reads IDR.
The IBF1 flag setting and clearing conditions are
different when the fast A20 gate is used. For details see
table 15.3.
0: [Clearing condition]
When the slave processor reads IDR
1: [Setting condition]
When the host processor writes to IDR using I/O
write cycle
0 OBF1 0 R/(W)* R Output Buffer Full
Set to 1 when the slave processor (this LSI) writes to
ODR. Cleared to 0 when the host processor reads
ODR.
0: [Clearing condition]
When the host processor reads ODR using I/O read
cycle, or the slave processor writes 0 to the OBF bit
1: [Setting condition]
When the slave processor writes to ODR
Note: * Only 0 can be written to clear the flag.
Rev. 1.00, 05/04, page 383 of 544
STR2
R/W
Bit Bit Name Initial Value Slave Host Description
7
6
5
4
DBU27
DBU26
DBU25
DBU24
0
0
0
0
R/W
R/W
R/W
R/W
R
R
R
R
Defined by User
The user can use these bits as necessary.
3 C/D2 0 R R Command/Data
When the host processor writes to an IDR register,
bit 2 of the I/O address is written into this bit to
indicate whether IDR contains data or a command.
0: Contents of data register (IDR) are data
1: Contents of data register (IDR) are a command
2 DBU22 0 R/W R Defined by User
The user can use this bit as necessary.
1 IBF2 0 R R Input Buffer Full
Set to 1 when the host processor writes to IDR. This
bit is an internal interrupt source to the slave
processor (this LSI). IBF is cleared to 0 when the
slave processor reads IDR.
The IBF1 flag setting and clearing conditions are
different when the fast A20 gate is used. For details
see table 15.3.
0: [Clearing condition]
When the slave processor reads IDR
1: [Setting condition]
When the host processor writes to IDR using I/O
write cycle
0 OBF2 0 R/(W)*R Output Buffer Full
Set to 1 when the slave processor (this LSI) writes to
ODR. Cleared to 0 when the host processor reads
ODR.
0: [Clearing condition]
When the host processor reads ODR using I/O
read cycle, or the slave processor writes 0 to the
OBF bit
1: [Setting condition]
When the slave processor writes to ODR
Note: * Only 0 can be written to clear the flag.
Rev. 1.00, 05/04, page 384 of 544
STR3 (TWRE = 1 or SELSTR3 = 0)
R/W
Bit Bit Name
Initial
Value Slave Host Description
7 IBF3B 0 R R Bidirectional Data Register Input Buffer Full
Set to 1 when the host processor writes to TWR15. This
is an internal interrupt source to the slave processor (this
LSI). IBF3B is cleared to 0 when the slave processor
reads TWR15.
0: [Clearing condition]
When the slave processor reads TWR15
1: [Setting condition]
When the host processor writes to TWR15 using I/O
write cycle
6 OBF3B 0 R/(W)* R Bidirectional Data Register Output Buffer Full
Set to 1 when the slave processor (this LSI) writes to
TWR15. OBF3B is cleared to 0 when the host processor
reads TWR15.
0: [Clearing condition]
When the host processor reads TWR15 using I/O
read cycle, or the slave processor writes 0 to the
OBF3B bit
1: [Setting condition]
When the slave processor writes to TWR15
5 MWMF 0 R R Master Write Mode Flag
Set to 1 when the host processor writes to TWR0.
MWMF is cleared to 0 when the slave processor (this
LSI) reads TWR15.
0: [Clearing condition]
When the slave processor reads TWR15
1: [Setting condition]
When the host processor writes to TWR0 using I/O
write cycle while SWMF = 0
4 SWMF 0 R/(W)* R Slave Write Mode Flag
Set to 1 when the slave processor (this LSI) writes to
TWR0. In the event of simultaneous writes by the master
and the slave, the master write has priority. SWMF is
cleared to 0 when the host reads TWR15
0: [Clearing condition]
When the host processor reads TWR15 using I/O
read cycle, or the slave processor writes 0 to the
SWMF bit
1: [Setting condition]
When the slave processor writes to TWR0 while
MWMF = 0
Rev. 1.00, 05/04, page 385 of 544
R/W
Bit Bit Name
Initial
Value Slave Host Description
3 C/D3 0 R R Command/Data
When the host processor writes to an IDR register, bit 2
of the I/O address is written into this bit to indicate
whether IDR contains data or a command.
0: Contents of data register (IDR) are data
1: Contents of data register (IDR) are a command
2 DBU32 0 R/W R Defined by User
The user can use this bit as necessary.
1 IBF3A 0 R R Input Buffer Full
Set to 1 when the host processor writes to IDR. This bit
is an internal interrupt source to the slave processor (this
LSI). IBF is cleared to 0 when the slave processor reads
IDR.
The IBF1 flag setting and clearing conditions are
different when the fast A20 gate is used. For details see
table 15.3.
0: [Clearing condition]
When the slave processor reads IDR
1: [Setting condition]
When the host processor writes to IDR using I/O
write cycle
0 OBF3A 0 R/(W)* R Output Buffer Full
Set to 1 when the slave processor (this LSI) writes to
ODR. OBF3A is cleared to 0 when the host processor
reads ODR.
0: [Clearing condition]
When the host processor reads ODR using I/O read
cycle, or the slave processor writes 0 to the OBF bit
1: [Setting condition]
When the slave processor writes to ODR
Note: * Only 0 can be written to clear the flag.
Rev. 1.00, 05/04, page 386 of 544
STR3 (TWRE = 0 and SELSTR3 = 1)
R/W
Bit Bit Name
Initial
Value Slave Host Description
7
6
5
4
DBU37
DBU36
DBU35
DBU34
0
0
0
0
R/W
R/W
R/W
R/W
R
R
R
R
Defined by User
The user can use these bits as necessary.
3 C/D3 0 R R Command/Data
When the host processor writes to an IDR register, bit 2
of the I/O address is written into this bit to indicate
whether IDR contains data or a command.
0: Contents of data register (IDR) are data
1: Contents of data register (IDR) are a command
2 DBU32 0 R/W R Defined by User
The user can use this bit as necessary.
1 IBF3A 0 R R Input Buffer Full
Set to 1 when the host processor writes to IDR. This bit
is an internal interrupt source to the slave processor (this
LSI). IBF is cleared to 0 when the slave processor reads
IDR.
The IBF1 flag setting and clearing conditions are
different when the fast A20 gate is used. For details see
table 15.3.
0: [Clearing condition]
When the slave processor reads IDR
1: [Setting condition]
When the host processor writes to IDR using I/O
write cycle
0 OBF3A 0 R/(W)* R Output Buffer Full
Set to 1 when the slave processor (this LSI) writes to
ODR. OBF3A is cleared to 0 when the host processor
reads ODR.
0: [Clearing condition]
When the host processor reads ODR using I/O read
cycle, or the slave processor writes 0 to the OBF bit
1: [Setting condition]
When the slave processor writes to ODR
Note: * Only 0 can be written to clear the flag.
Rev. 1.00, 05/04, page 387 of 544
15.3.8 SERIRQ Control Registers 0 and 1 (SIRQCR0, SIRQCR1)
The SIRQCR registers contain status bits that indicate the SERIRQ operating mode and bits that
specify SERIRQ interrupt sources.
SIRQCR0
R/W
Bit Bit Name
Initial
Value Slave Host Description
7 Q/C 0 R Quiet/Continuous Mode Flag
Indicates the mode specified by the host at the end of
an SERIRQ transfer cycle (stop frame).
0: Continuous mode
[Clearing conditions]
LPC hardware reset, LPC software reset
Specification by SERIRQ transfer cycle stop frame
1: Quiet mode
[Setting condition]
Specification by SERIRQ transfer cycle stop frame.
6 SELREQ 0 R/W Start Frame Initiation Request Select
Selects whether start frame initiation is requested when
one or more interrupt requests are cleared, or when all
interrupt requests are cleared, in quiet mode.
0: Start frame initiation is requested when all interrupt
requests are cleared in quiet mode.
1: Start frame initiation is requested when one or more
interrupt requests are cleared in quiet mode.
5 IEDIR 0 R/W Interrupt Enable Direct Mode
Specifies whether LPC channel 2 and channel 3
SERIRQ interrupt source (SMI, IRQ6, IRQ9 to IRQ11)
generation is conditional upon OBF, or is controlled only
by the host interrupt enable bit.
0: Host interrupt is requested when host interrupt enable
bit and corresponding OBF are both set to 1
1: Host interrupt is requested when host interrupt enable
bit is set to 1
Rev. 1.00, 05/04, page 388 of 544
R/W
Bit Bit Name
Initial
Value Slave Host Description
4 SMIE3B 0 R/W Host SMI Interrupt Enable 3B
Enables or disables a host SMI interrupt request when
OBF3B is set by a TWR15 write.
0: Host SMI interrupt request by OBF3B and SMIE3B is
disabled
[Clearing conditions]
Writing 0 to SMIE3B
LPC hardware reset, LPC software reset
Clearing OBF3B to 0 (when IEDIR = 0)
1: [When IEDIR = 0]
Host SMI interrupt request by setting OBF3B to 1 is
enabled
[When IEDIR = 1]
Host SMI interrupt is requested
[Setting condition]
Writing 1 after reading SMIE3B = 0
3 SMIE3A 0 R/W Host SMI Interrupt Enable 3A
Enables or disables a host SMI interrupt request when
OBF3A is set by an ODR3 write.
0: Host SMI interrupt request by OBF3A and SMIE3A is
disabled
[Clearing conditions]
Writing 0 to SMIE3A
LPC hardware reset, LPC software reset
Clearing OBF3A to 0 (when IEDIR = 0)
1: [When IEDIR = 0]
Host SMI interrupt request by setting OBF3A to 1 is
enabled
[When IEDIR = 1]
Host SMI interrupt is requested
[Setting condition]
Writing 1 after reading SMIE3A = 0
Rev. 1.00, 05/04, page 389 of 544
R/W
Bit Bit Name
Initial
Value Slave Hos
t Description
2 SMIE2 0 R/W Host SMI Interrupt Enable 2
Enables or disables a host SMI interrupt request when
OBF2 is set by an ODR2 write.
0: Host SMI interrupt request by OBF2 and SMIE2 is
disabled
[Clearing conditions]
Writing 0 to SMIE2
LPC hardware reset, LPC software reset
Clearing OBF2 to 0 (when IEDIR = 0)
1: [When IEDIR = 0]
Host SMI interrupt request by setting OBF2 to 1 is
enabled
[When IEDIR = 1]
Host SMI interrupt is requested
[Setting condition]
Writing 1 after reading SMIE2 = 0
1 IRQ12E1 0 R/W Host IRQ12 Interrupt Enable 1
Enables or disables a host IRQ12 interrupt request
when OBF1 is set by an ODR1 write.
0: Host IRQ12 interrupt request by OBF1 and IRQ12E1
is disabled
[Clearing conditions]
Writing 0 to IRQ12E1
LPC hardware reset, LPC software reset
Clearing OBF1 to 0
1: Host IRQ12 interrupt request by setting OBF1 to 1 is
enabled
[Setting condition]
Writing 1 after reading IRQ12E1 = 0
Rev. 1.00, 05/04, page 390 of 544
R/W
Bit Bit Name
Initial
Value Slave Host Description
0 IRQ1E1 0 R/W Host IRQ1 Interrupt Enable 1
Enables or disables a host IRQ1 interrupt request when
OBF1 is set by an ODR1 write.
0: Host IRQ1 interrupt request by OBF1 and IRQ1E1 is
disabled
[Clearing conditions]
Writing 0 to IRQ1E1
LPC hardware reset, LPC software reset
Clearing OBF1 to 0
1: Host IRQ1 interrupt request by setting OBF1 to 1 is
enabled
[Setting condition]
Writing 1 after reading IRQ1E1 = 0
SIRQCR1
R/W
Bit Bit Name
Initial
Value Slave Host Description
7 IRQ11E3 0 R/W Host IRQ11 Interrupt Enable 3
Enables or disables a host IRQ11 interrupt request
when OBF3A is set by an ODR3 write.
0: Host IRQ11 interrupt request by OBF3A and
IRQ11E3 is disabled
[Clearing conditions]
Writing 0 to IRQ11E3
LPC hardware reset, LPC software reset
Clearing OBF3A to 0 (when IEDIR = 0)
1: [When IEDIR = 0]
Host IRQ11 interrupt request by setting OBF3A to 1
is enabled
[When IEDIR = 1]
Host IRQ11 interrupt is requested.
[Setting condition]
Writing 1 after reading IRQ11E3 = 0
Rev. 1.00, 05/04, page 391 of 544
R/W
Bit Bit Name
Initial
Value Slave Host Description
6 IRQ10E3 0 R/W Host IRQ10 Interrupt Enable 3
Enables or disables a host IRQ10 interrupt request
when OBF3A is set by an ODR3 write.
0: Host IRQ10 interrupt request by OBF3A and
IRQ10E3 is disabled
[Clearing conditions]
Writing 0 to IRQ10E3
LPC hardware reset, LPC software reset
Clearing OB3FA to 0 (when IEDIR = 0)
1: [When IEDIR = 0]
Host IRQ10 interrupt request by setting OBF3A to 1
is enabled
[When IEDIR = 1]
Host IRQ10 interrupt is requested.
[Setting condition]
Writing 1 after reading IRQ10E3 = 0
5 IRQ9E3 0 R/W Host IRQ9 Interrupt Enable 3
Enables or disables a host IRQ9 interrupt request when
OBF3A is set by an ODR3 write.
0: Host IRQ9 interrupt request by OBF3A and IRQ9E3
is disabled
[Clearing conditions]
Writing 0 to IRQ9E3
LPC hardware reset, LPC software reset
Clearing OBF3A to 0 (when IEDIR = 0)
1: [When IEDIR = 0]
Host IRQ9 interrupt request by setting OBF3A to 1
is enabled
[When IEDIR = 1]
Host IRQ9 interrupt is requested.
[Setting condition]
Writing 1 after reading IRQ9E3 = 0
Rev. 1.00, 05/04, page 392 of 544
R/W
Bit Bit Name
Initial
Value Slave Host Description
4 IRQ6E3 0 R/W Host IRQ6 Interrupt Enable 3
Enables or disables a host IRQ6 interrupt request when
OBF3A is set by an ODR3 write.
0: Host IRQ6 interrupt request by OBF3A and IRQ6E3
is disabled
[Clearing conditions]
Writing 0 to IRQ6E3
LPC hardware reset, LPC software reset
Clearing OBF3A to 0 (when IEDIR = 0)
1: [When IEDIR = 0]
Host IRQ6 interrupt request by setting OBF3A to 1
is enabled
[When IEDIR = 1]
Host IRQ6 interrupt is requested.
[Setting condition]
Writing 1 after reading IRQ6E3 = 0
3 IRQ11E2 0 R/W Host IRQ11 Interrupt Enable 2
Enables or disables a host IRQ11 interrupt request
when OBF2 is set by an ODR2 write.
0: Host IRQ11 interrupt request by OBF2 and IRQ11E2
is disabled
[Clearing conditions]
Writing 0 to IRQ11E2
LPC hardware reset, LPC software reset
Clearing OBF2 to 0 (when IEDIR = 0)
1: [When IEDIR = 0]
Host IRQ11 interrupt request by setting OBF2 to 1 is
enabled
[When IEDIR = 1]
Host IRQ11 interrupt is requested.
[Setting condition]
Writing 1 after reading IRQ11E2 = 0
Rev. 1.00, 05/04, page 393 of 544
R/W
Bit Bit Name
Initial
Value Slave Host Description
2 IRQ10E2 0 R/W Host IRQ10 Interrupt Enable 2
Enables or disables a host IRQ10 interrupt request
when OBF2 is set by an ODR2 write.
0: Host IRQ10 interrupt request by OBF2 and IRQ10E2
is disabled
[Clearing conditions]
Writing 0 to IRQ10E2
LPC hardware reset, LPC software reset
Clearing OBF2 to 0 (when IEDIR = 0)
1: [When IEDIR = 0]
Host IRQ10 interrupt request by setting OBF2 to 1 is
enabled
[When IEDIR = 1]
Host IRQ10 interrupt is requested.
[Setting condition]
Writing 1 after reading IRQ10E2 = 0
1 IRQ9E2 0 R/W Host IRQ9 Interrupt Enable 2
Enables or disables a host IRQ9 interrupt request when
OBF2 is set by an ODR2 write.
0: Host IRQ9 interrupt request by OBF2 and IRQ9E2 is
disabled
[Clearing conditions]
Writing 0 to IRQ9E2
LPC hardware reset, LPC software reset
Clearing OBF2 to 0 (when IEDIR = 0)
1: [When IEDIR = 0]
Host IRQ9 interrupt request by setting OBF2 to 1 is
enabled
[When IEDIR = 1]
Host IRQ9 interrupt is requested.
[Setting condition]
Writing 1 after reading IRQ9E2 = 0
Rev. 1.00, 05/04, page 394 of 544
R/W
Bit Bit Name
Initial
Value
Slave Host Description
0 IRQ6E2 0 R/W Host IRQ6 Interrupt Enable 2
Enables or disables a host IRQ6 interrupt request when
OBF2 is set by an ODR2 write.
0: Host IRQ6 interrupt request by OBF2 and IRQ6E2 is
disabled
[Clearing conditions]
Writing 0 to IRQ6E2
LPC hardware reset, LPC software reset
Clearing OBF2 to 0 (when IEDIR = 0)
1: [When IEDIR = 0]
Host IRQ6 interrupt request by setting OBF2 to 1 is
enabled
[When IEDIR = 1]
Host IRQ6 interrupt is requested.
[Setting condition]
Writing 1 after reading IRQ6E2 = 0
Rev. 1.00, 05/04, page 395 of 544
15.3.9 Host Interface Select Register (HISEL)
HISEL selects the function of bits 7 to 4 in STR3 and specifies the output of the host interrupt
request signal of each frame.
R/W
Bit Bit Name Initial Value Slave Host Description
7 SELSTR3 0 W STR3 Register Function Select 3
Selects the function of bits 7 to 4 in STR3 in
combination with the TWRE bit in LADR3L. See
description on STR3 in section 15.3.7, Status
Registers 1 to 3 (STR1 to STR3), for details.
0: Bits 7 to 4 in STR3 are status bits of the host
interface.
1: [When TWRE = 1]
Bits 7 to 4 in STR3 are status bits of the host
interface.
[When TWRE = 0]
Bits 7 to 4 in STR3 are user bits.
6
5
4
3
2
1
0
SELIRQ11
SELIRQ10
SELIRQ9
SELIRQ6
SELSMI
SELIRQ12
SELIRQ1
0
0
0
0
0
1
1
W
W
W
W
W
W
W
SERIRQ Output Select
Selects the pin output status of host interrupt
requests (HIRQ11, HIRQ10, HIRQ9, HIRQ6, SMI,
HIRQ12, and HIRQ1) of the LPC.
0: [When host interrupt request is cleared]
SERIRQ pin output is in the high-impedance
state.
[When host interrupt request is set]
SERIRQ pin output is 0.
1: [When host interrupt request is cleared]
SERIRQ pin output is 0.
[When host interrupt request is set]
SERIRQ pin output is in the high-impedance
state.
Rev. 1.00, 05/04, page 396 of 544
15.4 Operation
15.4.1 Host Interface Activation
The host interface is activated by setting one of bits LPC3E to LPC1E in HICR0 to 1 in single-
chip mode. When the host interface is activated, the related I/O ports (ports 37 to 30, ports 83 and
82) function as dedicated host interface input/output pins. In addition, setting the FGA20E, PMEE,
LSMIE, and LSCIE bits to 1 adds the related I/O ports (ports 81 and 80, ports B0 and B1) to the
host interface's input/output pins.
Use the following procedure to activate the host interface after a reset release.
1. Read the signal line status and confirm that the LPC module can be connected. Also check that
the LPC module is initialized internally.
2. When using channel 3, set LADR3 to determine the channel 3 I/O address and whether
bidirectional data registers are to be used.
3. Set the enable bit (LPC3E to LPC1E) for the channel to be used.
4. Set the enable bits (GA20E, PMEE, LSMIE, and LSCIE) for the additional functions to be
used.
5. Set the selection bits for other functions (SDWNE, IEDIR).
6. As a precaution, clear the interrupt flags (LRST, SDWN, ABRT, OBF). Read IDR or TWR15
to clear IBF.
7. Set interrupt enable bits (IBFIE3 to IBFIE1, ERRIE) as necessary.
Rev. 1.00, 05/04, page 397 of 544
15.4.2 LPC I/O Cycles
There are ten kinds of LPC transfer cycle: memory read, memory write, I/O read, I/O write, DMA
read, DMA write, bus master memory read, bus master memory write, bus master I/O read, and
bus master I/O write. Of these, the chip's LPC supports only I/O read and I/O write cycles.
An LPC transfer cycle is started when the LFRAME signal goes low in the bus idle state. If the
LFRAME signal goes low when the bus is not idle, this means that a forced termination (abort) of
the LPC transfer cycle has been requested.
In an I/O read cycle or I/O write cycle, transfer is carried out using LAD3 to LAD0 in the
following order, in synchronization with LCLK. The host can be made to wait by sending back a
value other than B0000 in the slave's synchronization return cycle, but with the chip's LPC a
value of B0000 is always returned.
If the received address matches the host address in an LPC register (IDR, ODR, STR, TWR), the
host interface enters the busy state; it returns to the idle state by output of a state count 12
turnaround. Register and flag changes are made at this timing, so in the event of a transfer cycle
forced termination (abort) before state #12, registers and flags are not changed.
I/O Read Cycle I/O Write Cycle
State
Count Contents Drive
Source Value
(3 to 0) Contents Drive
Source Value
(3 to 0)
1 Start Host 0000 Start Host 0000
2 Cycle type/direction Host 0000 Cycle type/direction Host 0010
3 Address 1 Host Bits 15 to
12
Address 1 Host Bits 15 to
12
4 Address 2 Host Bits 11 to 8 Address 2 Host Bits 11 to 8
5 Address 3 Host Bits 7 to 4 Address 3 Host Bits 7 to 4
6 Address 4 Host Bits 3 to 0 Address 4 Host Bits 3 to 0
7 Turnaround
(recovery)
Host 1111 Data 1 Host Bits 3 to 0
8 Turnaround None ZZZZ Data 2 Host Bits 7 to 4
9 Synchronization Slave 0000 Turnaround
(recovery)
Host 1111
10 Data 1 Slave Bits 3 to 0 Turnaround None ZZZZ
11 Data 2 Slave Bits 7 to 4 Synchronization Slave 0000
12 Turnaround
(recovery)
Slave 1111 Turnaround
(recovery)
Slave 1111
13 Turnaround None ZZZZ Turnaround None ZZZZ
Rev. 1.00, 05/04, page 398 of 544
The timing of the LFRAME, LCLK, and LAD signals is shown in figures 15.2 and 15.3.
ADDRStart
LFRAME
LAD3–LAD0
Number of clocks
LCLK
TAR Sync Data TAR Start
Cycle type,
direction,
and size
114 12221
Figure 15.2 Typical LFRAME Timing
ADDRStart
LFRAME
LAD3–LAD0
LCLK
TAR Sync
Cycle type,
direction,
and size
Slave must stop driving
Too many Syncs
cause timeout
Master will
drive high
Figure 15.3 Abort Mechanism
15.4.3 A20 Gate
The A20 gate signal can mask address A20 to emulate an addressing mode used by personal
computers with an 8086*-family CPU. A regular-speed A20 gate signal can be output under
firmware control. The fast A20 gate function that is speeded up by hardware is enabled by setting
the FGA20E bit to 1 in HICR0.
Note: An Intel microprocessor
Rev. 1.00, 05/04, page 399 of 544
Regular A20 Gate Operation: Output of the A20 gate signal can be controlled by an H'D1
command followed by data. When the slave processor (this LSI) receives data, it normally uses an
interrupt routine activated by the IBF1 interrupt to read IDR1. At this time, firmware copies bit 1
of data following an H'D1 command and outputs it at the gate A20 pin.
Fast A20 Gate Operation: The internal state of GA20 output is initialized to 1 when FGA20E =
0. When the FGA20E bit is set to 1, P81/GA20 is used for output of a fast A20 gate signal. The
state of the P81/GA20 pin can be monitored by reading the GA20 bit in HICR2.
The initial output from this pin will be a logic 1, which is the initial value. Afterward, the host
processor can manipulate the output from this pin by sending commands and data. This function
is only available via the IDR1 register. The host interface decodes commands input from the host.
When an H'D1 host command is detected, bit 1 of the data following the host command is output
from the GA20 output pin. This operation does not depend on firmware or interrupts, and is faster
than the regular processing using interrupts. Table 15.3 shows the conditions that set and clear
GA20 (P81). Figure 15.4 shows the GA20 output in flowchart form. Table 15.4 indicates the
GA20 output signal values.
Table 15.3 GA20 (P81) Set/Clear Timing
Pin Name Setting Condition Clearing Condition
GA20 (P81) When bit 1 of the data that follows an
H'D1 host command is 1
When bit 1 of the data that follows an
H'D1 host command is 0
Start
Wait for next byte
H'D1 command
received?
Host write
Host write
Yes
No
Data byte?
No
Write bit 1 of data byte
to DR bit of P81/GA20
Yes
Figure 15.4 GA20 Output
Rev. 1.00, 05/04, page 400 of 544
Table 15.4 Fast A20 Gate Output Signals
HA0 Data/Command
Internal CPU
Interrupt Flag
(IBF) GA20
(P81) Remarks
1 H'D1 command 0 Q
0 1 data*1 0 1
1 H'FF command 0 Q (1)
Turn-on sequence
1 H'D1 command 0 Q
0 0 data*2 0 0
1 H'FF command 0 Q (0)
Turn-off sequence
1 H'D1 command 0 Q
0 1 data*1 0 1
1/0 Command other than H'FF and H'D1 1 Q (1)
Turn-on sequence
(abbreviated form)
1 H'D1 command 0 Q
0 0 data*2 0 0
1/0 Command other than H'FF and H'D1 1 Q (0)
Turn-off sequence
(abbreviated form)
1 H'D1 command 0 Q
1 Command other than H'D1 1 Q
Cancelled sequence
1 H'D1 command 0 Q
1 H'D1 command 0 Q
Retriggered
sequence
1 H'D1 command 0 Q
0 Any data 0 1/0
1 H'D1 command 0 Q (1/0)
Consecutively
executed sequences
Notes: 1. Arbitrary data with bit 1 set to 1.
2. Arbitrary data with bit 1 cleared to 0.
Rev. 1.00, 05/04, page 401 of 544
15.4.4 Host Interface Shutdown Function (LPCPD)
The host interface can be placed in the shutdown state according to the state of the LPCPD pin.
There are two kinds of host interface shutdown state: LPC hardware shutdown and LPC software
shutdown. The LPC hardware shutdown state is controlled by the LPCPD pin, while the software
shutdown state is controlled by the SDWNB bit. In both states, the host interface enters the reset
state by itself, and is no longer affected by external signals other than the LRESET and LPCPD
signals.
Placing the slave processor in sleep mode or software standby mode is effective in reducing
current dissipation in the shutdown state. If software standby mode is set, some means must be
provided for exiting software standby mode before clearing the shutdown state with the LPCPD
signal.
If the SDWNE bit has been set to 1 beforehand, the LPC hardware shutdown state is entered at the
same time as the LPCPD signal falls, and prior preparation is not possible. If the LPC software
shutdown state is set by means of the SDWNB bit, on the other hand, the LPC software shutdown
state cannot be cleared at the same time as the rise of the LPCPD signal. Taking these points into
consideration, the following operating procedure uses a combination of LPC software shutdown
and LPC hardware shutdown.
1. Clear the SDWNE bit to 0.
2. Set the ERRIE bit to 1 and wait for an interrupt by the SDWN flag.
3. When an ERRI interrupt is generated by the SDWN flag, check the host interface internal
status flags and perform any necessary processing.
4. Set the SDWNB bit to 1 to set LPC software standby mode.
5. Set the SDWNE bit to 1 and make a transition to LPC hardware standby mode. The SDWNB
bit is cleared automatically.
6. Check the state of the LPCPD signal to make sure that the LPCPD signal has not risen during
steps 3 to 5. If the signal has risen, clear SDWNE to 0 to return to the state in step 1.
7. Place the slave processor in sleep mode or software standby mode as necessary.
8. If software standby mode has been set, exit software standby mode by some means
independent of the LPC.
9. When a rising edge is detected in the LPCPD signal, the SDWNE bit is automatically cleared
to 0. If the slave processor has been placed in sleep mode, the mode is exited by means of
LRESET signal input, on completion of the LPC transfer cycle, or by some other means.
Rev. 1.00, 05/04, page 402 of 544
Table 15.5 shows the scope of the host interface pin shutdown.
Table 15.5 Scope of Host Interface Pin Shutdown
Abbreviation Port Scope of
Shutdown I/O Notes
LAD3 to LAD0 P33–P30 O I/O Hi-Z
LFRAME P34 O Input Hi-Z
LRESET P35 × Input LPC hardware reset function is active
LCLK P36 O Input Hi-Z
SERIRQ P37 O I/O Hi-Z
LSCI PB1 I/O Hi-Z, only when LSCIE = 1
LSMI PB0 I/O Hi-Z, only when LSMIE = 1
PME P80 I/O Hi-Z, only when PMEE = 1
GA20 P81 I/O Hi-Z, only when FGA20E = 1
CLKRUN P82 O I/O Hi-Z
LPCPD P83 × Input Needed to clear shutdown state
[Legend]
O: Pin that is shutdown by the shutdown function
: Pin that is shutdown only when the LPC function is selected by register setting
×: Pin that is not shutdown
In the LPC shutdown state, the LPC's internal state and some register bits are initialized. The order
of priority of LPC shutdown and reset states is as follows.
1. System reset (reset by STBY or RES pin input, or WDT0 overflow)
All register bits, including bits LPC3E to LPC1E, are initialized.
2. LPC hardware reset (reset by LRESET pin input)
LRSTB, SDWNE, and SDWNB bits are cleared to 0.
3. LPC software reset (reset by LRSTB)
SDWNE and SDWNB bits are cleared to 0.
4. LPC hardware shutdown
SDWNB bit is cleared to 0.
5. LPC software shutdown
Rev. 1.00, 05/04, page 403 of 544
The scope of the initialization in each mode is shown in table 15.6.
Table 15.6 Scope of Initialization in Each Host Interface Mode
Items Initialized
System
Reset LPC Reset
LPC
Shutdown
LPC transfer cycle sequencer (internal state), LPCBSY and
ABRT flags
Initialized Initialized Initialized
SERIRQ transfer cycle sequencer (internal state), CLKREQ and
IRQBSY flags
Initialized Initialized Initialized
Host interface flags
(IBF1, IBF2, IBF3A, IBF3B, MWMF, C/D1, C/D2, C/D3, OBF1,
OBF2, OBF3A, OBF3B, SWMF, DBU), GA20 (internal state)
Initialized Initialized Retained
Host interrupt enable bits
(IRQ1E1, IRQ12E1, SMIE2, IRQ6E2,
IRQ9E2 to IRQ11E2, SMIE3B, SMIE3A, IRQ6E3, IRQ9E3 to
IRQ11E3), Q/C flag, SELREQ bit
Initialized Initialized Retained
LRST flag Initialized
(0)
Can be
set/cleared
Can be
set/cleared
SDWN flag Initialized
(0)
Initialized
(0)
Can be
set/cleared
LRSTB bit Initialized
(0)
HR: 0
SR: 1
0 (can be set)
SDWNB bit Initialized
(0)
Initialized
(0)
HS: 0
SS: 1
SDWNE bit Initialized
(0)
Initialized
(0)
HS: 1
SS: 0 or 1
Host interface operation control bits
(LPC3E to LPC1E, FGA20E, LADR3,
IBFIE1 to IBFIE3, PMEE, PMEB, LSMIE, LSMIB, LSCIE, LSCIB,
TWRE, SELSTR3, SELIRQ1, SELSMI, SELIRQ6, SELIRQ9,
SELIRQ10, SELIRQ11, SELIRQ12)
Initialized Retained Retained
LRESET signal Input (port
function
Input Input
LPCPD signal Input Input
LAD3 to LAD0, LFRAME, LCLK, SERIRQ,
CLKRUN signals
Input Hi-Z
PME, LSMI, LSCI, GA20 signals (when function is selected) Output Hi-Z
PME, LSMI, LSCI, GA20 signals (when function is not selected) Port function Port function
Note: System reset: Reset by STBY input, RES input, or WDT overflow
LPC reset: Reset by LPC hardware reset (HR) or LPC software reset (SR)
LPC shutdown: Reset by LPC hardware shutdown (HS) or LPC software shutdown (SS)
Rev. 1.00, 05/04, page 404 of 544
Figure 15.5 shows the timing of the LPCPD and LRESET signals.
LPCPD
LRESET
LAD3–LAD0
LFRAME
LCLK
At least 30 µsAt least 100 µs
At least 60 µs
Figure 15.5 Power-Down State Termination Timing
Rev. 1.00, 05/04, page 405 of 544
15.4.5 Host Interface Serialized Interrupt Operation (SERIRQ)
A host interrupt request can be issued from the host interface by means of the SERIRQ pin. In a
host interrupt request via the SERIRQ pin, LCLK cycles are counted from the start frame of the
serialized interrupt transfer cycle generated by the host or a peripheral function, and a request
signal is generated by the frame corresponding to that interrupt. The timing is shown in figure
15.6.
IRQ1 IRQ1Host controller None None
SERIRQ
Drive source
LCLK
START
Start frame IRQ0 frame IRQ1 frame IRQ2 frame
SL
or
HHRTRST RST RST
IRQ15 Host controllerNoneNone
SERIRQ
Driver
LCLK
STARTSTOP
IOCHCK frame Stop frame Next cycleIRQ14 frame IRQ15 frame
RST RSTRST RTHI
[Legend]
H = Host control, SL = Slave control, R = Recovery, T = Turnaround, S = Sample
[Legend]
H = Host control, R = Recovery, T = Turnaround, S = Sample, I = Idle
Figure 15.6 SERIRQ Timing
The serialized interrupt transfer cycle frame configuration is as follows. Two of the states
comprising each frame are the recover state in which the SERIRQ signal is returned to the 1-level
at the end of the frame, and the turnaround state in which the SERIRQ signal is not driven. The
recover state must be driven by the host or slave processor that was driving the preceding state.
Rev. 1.00, 05/04, page 406 of 544
Serial Interrupt Transfer Cycle
Frame
Count Contents Drive
Source Number
of States Notes
0 Start Slave
Host
6 In quiet mode only, slave drive possible in first
state, then next 3 states 0-driven by host
1 IRQ0 Slave 3
2 IRQ1 Slave 3 Drive possible in LPC channel 1
3 SMI Slave 3 Drive possible in LPC channels 2 and 3
4 IRQ3 Slave 3
5 IRQ4 Slave 3
6 IRQ5 Slave 3
7 IRQ6 Slave 3 Drive possible in LPC channels 2 and 3
8 IRQ7 Slave 3
9 IRQ8 Slave 3
10 IRQ9 Slave 3 Drive possible in LPC channels 2 and 3
11 IRQ10 Slave 3 Drive possible in LPC channels 2 and 3
12 IRQ11 Slave 3 Drive possible in LPC channels 2 and 3
13 IRQ12 Slave 3 Drive possible in LPC channel 1
14 IRQ13 Slave 3
15 IRQ14 Slave 3
16 IRQ15 Slave 3
17 IOCHCK Slave 3
18 Stop Host Undefined First, 1 or more idle states, then 2 or 3 states
0-driven by host
2 states: Quiet mode next
3 states: Continuous mode next
There are two modes—continuous mode and quiet mode—for serialized interrupts. The mode
initiated in the next transfer cycle is selected by the stop frame of the serialized interrupt transfer
cycle that ended before that cycle.
In continuous mode, the host initiates host interrupt transfer cycles at regular intervals. In quiet
mode, the slave processor with interrupt sources requiring a request can also initiate an interrupt
transfer cycle, in addition to the host. In quiet mode, since the host does not necessarily initiate
interrupt transfer cycles, it is possible to suspend the clock (LCLK) supply and enter the power-
down state. In order for a slave to transfer an interrupt request in this case, a request to restart the
clock must first be issued to the host. For details see section 15.4.6, Host Interface Clock Start
Request (CLKRUN).
Rev. 1.00, 05/04, page 407 of 544
15.4.6 Host Interface Clock Start Request (CLKRUN)
A request to restart the clock (LCLK) can be sent to the host processor by means of the CLKRUN
pin. With LPC data transfer and SERIRQ in continuous mode, a clock restart is never requested
since the transfer cycles are initiated by the host. With SERIRQ in quiet mode, when a host
interrupt request is generated the CLKRUN signal is driven and a clock (LCLK) restart request is
sent to the host. The timing for this operation is shown in figure 15.7.
CLK
CLKRUN
Pull-up enable Drive by the host processor
Drive by the slave processor
1 2 3 4 5 6
Figure 15.7 Clock Start Request Timing
Cases other than SERIRQ in quiet mode when clock restart is required must be handled with a
different protocol, using the PME signal, etc.
Rev. 1.00, 05/04, page 408 of 544
15.5 Interrupt Sources
15.5.1 IBFI1, IBFI2, IBFI3, and ERRI
The host interface has four interrupt requests for the slave processor (this LSI): IBF1, IBF2, IBF3,
and ERRI. IBFI1, IBFI2, and IBFI3 are IDR receive complete interrupts for IDR1, IDR2, and
IDR3 and TWR, respectively. The ERRI interrupt indicates the occurrence of a special state such
as an LPC reset, LPC shutdown, or transfer cycle abort. An interrupt request is enabled by setting
the corresponding enable bit.
Table 15.7 Receive Complete Interrupts and Error Interrupt
Interrupt Description
IBFI1 When IBFIE1 is set to 1 and IDR1 reception is completed
IBFI2 When IBFIE2 is set to 1 and IDR2 reception is completed
IBFI3 When IBFIE3 is set to 1 and IDR3 reception is completed, or when TWRE and
IBFIE3 are set to 1 and reception is completed up to TWR15
ERRI When ERRIE is set to 1 and one of LRST, SDWN and ABRT is set to 1
15.5.2 SMI, HIRQ1, HIRQ6, HIRQ9, HIRQ10, HIRQ11, and HIRQ12
The host interface can request seven kinds of host interrupt by means of SERIRQ. HIRQ1 and
HIRQ12 are used on LPC channel 1 only, while SMI, HIRQ6, HIRQ9, HIRQ10, and HIRQ11 can
be requested from LPC channel 2 or 3.
There are two ways of clearing a host interrupt request.
When the IEDIR bit is cleared to 0 in SIRQCR0, host interrupt sources and LPC channels are all
linked to the host interrupt request enable bits. When the OBF flag is cleared to 0 by a read of
ODR or TWR15 by the host in the corresponding LPC channel, the corresponding host interrupt
enable bit is automatically cleared to 0, and the host interrupt request is cleared.
When the IEDIR bit is set to 1 in SIRQCR0, LPC channel 2 and 3 interrupt requests are dependent
only upon the host interrupt enable bits. The host interrupt enable bit is not cleared when OBF for
channel 2 or 3 is cleared. Therefore, SMIE2, SMIE3A and SMIE3B, IRQ6E2 and IRQ6E3,
IRQ9E2 and IRQ9E3, IRQ10E2 and IRQ10E3, and IRQ11E2 and IRQ11E3 lose their respective
functional differences. In order to clear a host interrupt request, it is necessary to clear the host
interrupt enable bit.
Rev. 1.00, 05/04, page 409 of 544
Table 15.8 summarizes the methods of setting and clearing these bits, and figure 15.8 shows the
processing flowchart.
Table 15.8 HIRQ Setting and Clearing Conditions
Host Interrupt Setting Condition Clearing Condition
HIRQ1
(independent
from IEDIR)
Internal CPU writes to ODR1, then reads 0
from bit IRQ1E1 and writes 1
Internal CPU writes 0 to bit
IRQ1E1, or host reads ODR1
HIRQ12
(independent
from IEDIR)
Internal CPU writes to ODR1, then reads 0
from bit IRQ12E1 and writes 1
Internal CPU writes 0 to bit
IRQ12E1, or host reads ODR1
SMI
(IEDIR = 0)
Internal CPU
writes to ODR2, then reads 0 from bit
SMIE2 and writes 1
writes to ODR3, then reads 0 from bit
SMIE3A and writes 1
writes to TWR15, then reads 0 from bit
SMIE3B and writes 1
Internal CPU
writes 0 to bit SMIE2, or host
reads ODR2
writes 0 to bit SMIE3A, or host
reads ODR3
writes 0 to bit SMIE3B, or host
reads TWR15
SMI
(IEDIR = 1)
Internal CPU
reads 0 from bit SMIE2, then writes 1
reads 0 from bit SMIE3A, then writes 1
reads 0 from bit SMIE3B, then writes 1
Internal CPU
writes 0 to bit SMIE2
writes 0 to bit SMIE3A
writes 0 to bit SMIE3B
HIRQi
(i = 6, 9, 10, 11)
(IEDIR = 0)
Internal CPU
writes to ODR2, then reads 0 from bit
IRQiE2 and writes 1
writes to ODR3, then reads 0 from bit
IRQiE3 and writes 1
Internal CPU
writes 0 to bit IRQiE2, or host
reads ODR2
CPU writes 0 to bit IRQiE3, or
host reads ODR3
HIRQi
(i = 6, 9, 10, 11)
(IEDIR = 1)
Internal CPU
reads 0 from bit IRQiE2, then writes 1
reads 0 from bit IRQiE3, then writes 1
Internal CPU
writes 0 to bit IRQiE2
writes 0 to bit IRQiE3
Rev. 1.00, 05/04, page 410 of 544
Slave CPU Master CPU
ODR1 write
Write 1 to IRQ1E1
OBF1 = 0?
Yes
No
No
Yes
All bytes
transferred?
SERIRQ IRQ1 output
SERIRQ IRQ1
source clearance
Interrupt initiation
ODR1 read
Hardware operation
Software operation
Figure 15.8 HIRQ Flowchart (Example of Channel 1)
Rev. 1.00, 05/04, page 411 of 544
15.6 Usage Notes
15.6.1 Module Stop Mode Setting
LPC operation can be enabled or disabled using the module stop control register. The initial
setting is for LPC operation to be halted. Register access is enabled by canceling module stop
mode. For details, refer to section 20, Power-Down Modes.
15.6.2 Notes on Using Host Interface
The host interface provides buffering of asynchronous data from the host processor and slave
processor (this LSI), but an interface protocol that uses the flags in STR must be followed to avoid
data contention. For example, if the host and slave processor both try to access IDR or ODR at the
same time, the data will be corrupted. To prevent simultaneous accesses, IBF and OBF must be
used to allow access only to data for which writing has finished.
Unlike the IDR and ODR registers, the transfer direction is not fixed for the bidirectional data
registers (TWR). MWMF and SWMF are provided in STR to handle this situation. After writing
to TWR0, MWMF and SWMF must be used to confirm that the write authority for TWR1 to
TWR15 has been obtained.
Table 15.9 shows host address examples for LADR3 and registers, IDR3, ODR3, STR3,
TWR0MW, TWR0SW, and TWR1 to TWR15 when LADR3 = H'A24F and LADR3 = H'3FD0.
Rev. 1.00, 05/04, page 412 of 544
Table 15.9 Host Address Example
Register Host Address when LADR3 = H'A24F Host Address when LADR3 = H'3FD0
IDR3 H'A24A and H'A24E H'3FD0 and H'3FD4
ODR3 H'A24A H'3FD0
STR3 H'A24E H'3FD4
TWR0MW H'A250 H'3FC0
TWR0SW H'A250 H'3FC0
TWR1 H'A251 H'3FC1
TWR2 H'A252 H'3FC2
TWR3 H'A253 H'3FC3
TWR4 H'A254 H'3FC4
TWR5 H'A255 H'3FC5
TWR6 H'A256 H'3FC6
TWR7 H'A257 H'3FC7
TWR8 H'A258 H'3FC8
TWR9 H'A259 H'3FC9
TWR10 H'A25A H'3FCA
TWR11 H'A25B H'3FCB
TWR12 H'A25C H'3FCC
TWR13 H'A25D H'3FCD
TWR14 H'A25E H'3FCE
TWR15 H'A25F H'3FCF
ADCMS33B_010020040200 Rev. 1.00, 05/04, page 413 of 544
Section 16 A/D Converter
This LSI includes a successive-approximation-type 10-bit A/D converter that allows up to six
analog input channels to be selected. A/D conversion for digital input is effective as a comparator
in multiple input testing.
16.1 Features
10-bit resolution
Ιnput channels: six analog input channels
Analog conversion voltage range can be specified using the reference power supply voltage
pin (AVref) as an analog reference voltage.
Conversion time: 13.4 µs per channel (at 10 MHz operation)
Two kinds of operating modes
Single mode: Single-channel A/D conversion
Scan mode: Continuous A/D conversion on 1 to 4 channels
Four data registers
Conversion results are held in a 16-bit data register for each channel
Sample and hold function
Three kinds of conversion start
Software, 8-bit timer (TMR) conversion start trigger, or external trigger signal.
Interrupt request
A/D conversion end interrupt (ADI) request can be generated
Rev. 1.00, 05/04, page 414 of 544
A block diagram of the A/D converter is shown in figure 16.1.
Module data bus
Control circuit
Internal data bus
10-bit D/A
Comparator
+
Sample-and-hold
circuit
φ/16
ADI interrupt signal
A
D
C
S
R
A
D
C
R
A
D
D
R
D
A
D
D
R
C
A
D
D
R
B
A
D
D
R
A
Successive approximations
register
[Legend]
ADCR: A/D control register
ADCSR: A/D control/status register
ADDRA: A/D data register A
ADDRB: A/D data register B
ADDRC: A/D data register C
ADDRD: A/D data register D
ADTRG
Conversion start trigger from 8-bit timer
φ/8
AVCC
AVSS
AVref
Multiplexer
Bus interface
AN0
AN1
AN2
AN3
AN4
AN5
Figure 16.1 Block Diagram of A/D Converter
Rev. 1.00, 05/04, page 415 of 544
16.2 Input/Output Pins
Table 16.1 summarizes the pins used by the A/D converter. The 6 analog input pins are divided
into two groups consisting of four channels and two channels. Analog input pins 0 to 3 (AN0 to
AN3) comprising group 0 and analog input pins 4 and 5 (AN4 and AN5) comprising group 1. The
AVcc and AVss pins are the power supply pins for the analog block in the A/D converter.
Table 16.1 Pin Configuration
Pin Name Symbol I/O Function
Analog power supply pin AVCC Input Analog block power supply and
reference voltage
Analog ground pin AVSS Input Analog block ground and reference
voltage
Reference power supply pin AVref Input Reference voltage for A/D conversion
Analog input pin 0 AN0 Input
Analog input pin 1 AN1 Input
Analog input pin 2 AN2 Input
Analog input pin 3 AN3 Input
Group 0 analog input pins
Analog input pin 4 AN4 Input
Analog input pin 5 AN5 Input
Group 1 analog input pins
A/D external trigger input pin ADTRG Input External trigger input pin for starting A/D
conversion
Rev. 1.00, 05/04, page 416 of 544
16.3 Register Descriptions
The A/D converter has the following registers.
A/D data register A (ADDRA)
A/D data register B (ADDRB)
A/D data register C (ADDRC)
A/D data register D (ADDRD)
A/D control/status register (ADCSR)
A/D control register (ADCR)
16.3.1 A/D Data Registers A to D (ADDRA to ADDRD)
There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of
A/D conversion. The ADDR registers, which store a conversion result for each channel, are shown
in table 16.2.
The converted 10-bit data is stored to bits 15 to 6. The lower 6-bit data is always read as 0.
The data bus between the CPU and the A/D converter is 8-bit width. The upper byte can be read
directly from the CPU, but the lower byte should be read via a temporary register. The temporary
register contents are transferred from the ADDR when the upper byte data is read. When reading
the ADDR, read the upper byte before lower byte or in word units.
Table 16.2 Analog Input Channels and Corresponding ADDR Registers
Analog Input Channel
Group 0 Group 1 A/D Data Register to Store A/D Conversion Results
AN0 AN4 ADDRA
An1 AN5 ADDRB
AN2 ADDRC
AN3 ADDRD
Rev. 1.00, 05/04, page 417 of 544
16.3.2 A/D Control/Status Register (ADCSR)
ADCSR controls A/D conversion operations.
Bit Bit Name
Initial
Value R/W Description
7 ADF 0 R/(W)* A/D End Flag
A status flag that indicates the end of A/D conversion.
[Setting conditions]
When A/D conversion ends in single mode
When A/D conversion ends on all channels
specified in scan mode
[Clearing conditions]
When 0 is written after reading ADF = 1
6 ADIE 0 R/W A/D Interrupt Enable
Enables ADI interrupt by ADF when this bit is set to 1
5 ADST 0 R/W A/D Start
Setting this bit to 1 starts A/D conversion. Clearing this
bit to 0 stops A/D conversion. In single mode, this bit is
cleared to 0 automatically when conversion on the
specified channel ends. In scan mode, conversion
continues sequentially on the specified channels until
this bit is cleared to 0 by software, a reset, or a
transition to standby mode or module stop mode.
4 SCAN 0 R/W Scan Mode
Selects the A/D conversion operating mode. The
setting of this bit must be made when conversion is
halted (ADST = 0).
0: Single mode
1: Scan mode
3 CKS 0 R/W Clock Select
Sets A/D conversion time. The input channel setting
must be made when conversion is halted (ADST = 0).
0: Conversion time is 266 states (max)
1: Conversion time is 134 states (max)
Switch conversion time while ADST is 0.
Rev. 1.00, 05/04, page 418 of 544
Bit Bit Name Initial
Value R/W Description
Channel Select 2 to 0
Select analog input channels. The input channel setting
must be made when conversion is halted (ADST = 0).
2
1
0
CH2
CH1
CH0
0
0
0
R/W
R/W
R/W
When SCAN = 0:
000: AN0
001: AN1
010: AN2
011: AN3
100: AN4
101: AN5
110: Setting prohibited
111: Setting prohibited
When SCAN = 1:
000: AN0
001: AN0 and AN1
010: AN0 to AN2
011: AN0 to AN3
100: AN4
101: AN4 and AN5
110: Setting prohibited
111: Setting prohibited
Note: * Only 0 can be written for clearing the flag.
16.3.3 A/D Control Register (ADCR)
ADCR enables A/D conversion started by an external trigger signal.
Bit Bit Name Initial
Value R/W Description
7
6
TRGS1
TRGS0
0
0
R/W
R/W
Timer Trigger Select 1 and 0
Enable the start of A/D conversion by a trigger signal.
Only set bits TRGS1 and TRGS0 when conversion is
halted (ADST = 0).
00: A/D conversion start by external trigger is disabled
01: A/D conversion start by external trigger is disabled
10: A/D conversion start by conversion trigger from
TMR is enabled
11: A/D conversion start by ADTRG pin is enabled
5 to 0 All 1 R Reserved
These bits are always read as 1 and cannot be
modified.
Rev. 1.00, 05/04, page 419 of 544
16.4 Operation
The A/D converter operates by successive approximation with 10-bit resolution. It has two
operating modes: single mode and scan mode. When changing the operating mode or analog input
channel, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D
conversion. The ADST bit can be set at the same time as the operating mode or analog input
channel is changed.
16.4.1 Single Mode
In single mode, A/D conversion is to be performed only once on the specified single channel.
Operations are as follows.
1. A/D conversion on the specified channel is started when the ADST bit in ADCSR is set to 1,
by software or an external trigger input.
2. When A/D conversion is completed, the result is transferred to the A/D data register
corresponding to the channel.
3. On completion of A/D conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to
1 at this time, an ADI interrupt request is generated.
4. The ADST bit remains set to 1 during A/D conversion. When conversion ends, the ADST bit is
automatically cleared to 0, and the A/D converter enters wait state.
16.4.2 Scan Mode
Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the
ADST bit is set to 1 by software, or by timer or external trigger input, A/D conversion starts on the
first channel in the group (AN0 when CH2 = 0; AN4 when CH2 = 1).
When two or more channels are selected, after conversion of the first channel ends, conversion of
the second channel (AN1 or AN5) starts immediately. A/D conversion continues cyclically on the
selected channels until the ADST bit is cleared to 0. The conversion results are transferred for
storage into the ADDR registers corresponding to the channels.
Typical operations when three channels (AN0 to AN2) are selected in scan mode are described
below.
Rev. 1.00, 05/04, page 420 of 544
Figure 16.2 shows the operation timing.
1. Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), analog input channels
AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1).
2. When A/D conversion of the first channel (AN0) is completed, the result is transferred to
ADDRA. Next, conversion of the second channel (AN1) starts automatically.
3. Conversion proceeds in the same way through the third channel (AN2).
4. When conversion of all the selected channels (AN0 to AN2) is completed, the ADF flag is set
to 1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1 at this
time, an ADI interrupt is requested after A/D conversion ends.
5. Steps 2 to 4 are repeated as long as the ADST bit remains set to 1. When the ADST bit is
cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion
starts again from the first channel (AN0).
ADST
ADF
ADDRA
ADDRB
ADDRC
ADDRD
State of channel 0 (AN0)
State of channel 1 (AN1)
State of channel 2 (AN2)
State of channel 3 (AN3)
Set*1Clear*1
Idle
Notes: 1. Vertical arrows ( ) indicate instructions executed by software.
2. Data currently being converted is ignored.
Clear*1
Idle
Idle
A/D conversion time
Idle
Continuous A/D conversion execution
A/D conversion 1
Idle Idle
Idle
Idle
Idle
Transfer
*2
A/D conversion 3
A/D conversion 2 A/D conversion 5
A/D conversion 4
A/D conversion result 1
A/D conversion result 2
A/D conversion result 3
A/D conversion result 4
Figure 16.2 Example of A/D Converter Operation
(Scan Mode, Channels AN0 to AN2 Selected)
Rev. 1.00, 05/04, page 421 of 544
16.4.3 Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (tD) passes after the ADST bit in ADCSR is set to
1, then starts A/D conversion. Figure 16.3 shows the A/D conversion timing. Table 16.3 indicates
the A/D conversion time.
As indicated in figure 16.3, the A/D conversion time (tCONV) includes tD and the input sampling time
(tSPL). The length of tD varies depending on the timing of the write access to ADCSR. The total
conversion time therefore varies within the ranges indicated in table 16.3.
In scan mode, the values given in table 16.3 apply to the first conversion time. In the second and
subsequent conversions, the conversion time is 256 state (fixed) when CKS = 0 and 128 states
(fixed) when CKS = 1.
φ
Address
Write signal
Input sampling
timing
ADF
[Legend]
(1): ADCSR write cycle
(2): ADCSR address
tD: A/D conversion start delay
tSPL: Input sampling time
tCONV: A/D conversion time
(1)
(2)
tDtSPL
tCONV
Figure 16.3 A/D Conversion Timing
Rev. 1.00, 05/04, page 422 of 544
Table 16.3 A/D Conversion Time (Single Mode)
CKS = 0 CKS = 1
Item Symbol Min. Typ. Max. Min. Typ. Max.
A/D conversion start delay
time
tD 10 — 17 6 9
Input sampling time tSPL — 63 — — 31
A/D conversion time tCONV 259 — 266 131 — 134
Note: * Values in the table indicate the number of states.
16.4.4 External Trigger Input Timing
A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to B'11 in
ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets
the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan
modes, are the same as when the ADST bit has been set to 1 by software. Figure 16.4 shows the
timing.
A/D conversion
φ
ADTRG
Internal trigger
signal
ADST
Figure 16.4 External Trigger Input Timing
Rev. 1.00, 05/04, page 423 of 544
16.5 Interrupt Sources
The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion.
Setting the ADIE bit to 1 enables ADI interrupt requests while the ADF bit in ADCSR is set to 1
after A/D conversion is completed.
16.6 A/D Conversion Accuracy Definitions
This LSI's A/D conversion accuracy definitions are given below.
Resolution
The number of A/D converter digital output codes
Quantization error
The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 16.5).
Offset error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from the minimum voltage value B'0000000000 (H'000) to
B'0000000001 (H'001) (see figure 16.6).
Full-scale error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from B'1111111110 (H'3FE) to B'1111111111 (H'3FF) (see
figure 16.6).
Nonlinearity error
The error with respect to the ideal A/D conversion characteristics between the zero voltage and
the full-scale voltage. Does not include the offset error, full-scale error, or quantization error
(see figure 16.6).
Absolute accuracy
The deviation between the digital value and the analog input value. Includes the offset error,
full-scale error, quantization error, and nonlinearity error.
Rev. 1.00, 05/04, page 424 of 544
H'001
H'000
1
1024
2
1024
1022
1024
1023
1024
FS
Quantization error
Digital output
Ideal A/D conversion
characteristic
Analog
input voltage
H'002
H'003
H'004
H'3FD
H'3FE
H'3FF
Figure 16.5 A/D Conversion Accuracy Definitions
FS
Offset error
Nonlinearity
error
Actual A/D conversion
characteristic
Analog
input voltage
Digital output
Ideal A/D conversion
characteristic
Full-scale error
Figure 16.6 A/D Conversion Accuracy Definitions
Rev. 1.00, 05/04, page 425 of 544
16.7 Usage Notes
16.7.1 Permissible Signal Source Impedance
This LSI's analog input (3-V version) is designed so that the conversion accuracy is guaranteed for
an input signal for which the signal source impedance is 5 k or less. This specification is
provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged
within the sampling time; if the sensor output impedance exceeds 5 k, charging may be
insufficient and it may not be possible to guarantee the A/D conversion accuracy. However, if a
large capacitance is provided externally in single mode, the input load will essentially comprise
only the internal input resistance of 10 k, and the signal source impedance is ignored. However,
since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog
signal with a large differential coefficient (e.g., voltage fluctuation ratio of 5 mV/µs or greater)
(see figure 16.7). When converting a high-speed analog signal or converting in scan mode, a low-
impedance buffer should be inserted.
16.7.2 Influences on Absolute Accuracy
Adding capacitance results in coupling with ground, and therefore noise in ground may adversely
affect the absolute accuracy. Be sure to make the connection to an electrically stable ground such
as AVss.
Care is also required to insure that filter circuits do not communicate with digital signals on the
mounting board, so acting as antennas.
A/D converter equivalent circuit
This LSI
20 pF
C
in
=
15 pF
10 k
to 5 k
Low-pass
filter
C to 0.1 µF
Sensor output
impedance
Sensor input
Figure 16.7 Example of Analog Input Circuit
Rev. 1.00, 05/04, page 426 of 544
16.7.3 Setting Range of Analog Power Supply and Other Pins
If conditions shown below are not met, the reliability of this LSI may be adversely affected.
Analog input voltage range
The voltage applied to analog input pin ANn during A/D conversion should be in the range
AVss ANn AVref (n = 0 to 5).
Relation between AVcc, AVss and Vcc, Vss
For the relationship between AVcc, AVss and Vcc, Vss, set AVss = Vss. If the A/D converter
is not used, the AVcc and AVss pins must on no account be left open.
AVref pin reference voltage specification range
The reference voltage of the AVref pin should be in the range AVref AVcc.
16.7.4 Notes on Board Design
In board design, digital circuitry and analog circuitry should be as mutually isolated as possible,
and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close
proximity should be avoided as far as possible. Failure to do so may result in incorrect operation
of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital
circuitry must be isolated from the analog input signals (AN0 to AN5), analog reference voltage
(AVref), and analog power supply (AVCC) by the analog ground (AVSS). Also, the analog ground
(AVSS) should be connected at one point to a stable digital ground (VSS) on the board.
16.7.5 Notes on Noise Countermeasures
A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive
surge at the analog input pins (AN0 to AN5) and analog reference voltage (AVref) should be
connected between AVcc and AVss as shown in figure 16.8. Also, the bypass capacitors
connected to AVcc and AVref , and the filter capacitor connected to AN0 to AN5, must be
connected to AVSS.
If a filter capacitor is connected, the input currents at the analog input pins (AN0 to AN5) are
averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in
scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit
in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in
the analog input pin voltage. Careful consideration is therefore required when deciding the circuit
constants.
Rev. 1.00, 05/04, page 427 of 544
AV
CC
*
1
AN0 to AN5
AV
SS
Notes: Values are reference values.
2. Rin: Input impedance
1.
*
1
Rin*
2
100
0.1 µF
0.01 µF10 µF
AV
ref
Figure 16.8 Example of Analog Input Protection Circuit
20 pF
To A/D converterAN0 to AN5
10 k
Note: * Values are reference values.
Figure 16.9 Equivalent Circuit of Analog Input Pin
16.7.6 Module Stop Mode Setting
A/D converter operation can be enabled or disabled using the module stop control register. The
initial setting is for A/D converter operation to be halted. Register access is enabled by canceling
module stop mode. For details, refer to section 20, Power-Down Modes.
Rev. 1.00, 05/04, page 428 of 544
Rev. 1.00, 05/04, page 429 of 544
Section 17 RAM
This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit
data bus, enabling one-state access by the CPU to both byte data and word data.
The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control
register (SYSCR). For details on SYSCR, refer to section 3.2.2, System Control Register
(SYSCR).
Product Classification RAM Capacitance RAM Address
Flash memory version H8S/2111B-B 2 Kbytes H'E880 to H'EFFF,
H'FF00 to H'FF7F
H8S/2111B-C 3 Kbytes H'E480 to H'EFFF,
H'FF00 to H'FF7F
Rev. 1.00, 05/04, page 430 of 544
ROMF360A_010020040200 Rev. 1.00, 05/04, page 431 of 544
Section 18 ROM
This LSI has an on-chip ROM (flash memory). The features of the flash memory are summarized
below.
A block diagram of the flash memory is shown in figure 18.1.
18.1 Features
Size
Product Classification ROM Capacitance ROM Address
H8S/2111B 64 Kbytes H'000000 to H'00FFFF (mode 2)
H'0000 to H'DFFF (mode 3)
Programming/erase methods
The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units.
The flash memory is configured as follows:
8 Kbytes × 2 blocks, 16 Kbytes × 1 block, 28 Kbytes × 1 block, and 1 Kbyte × 4 blocks
To erase the entire flash memory, each block must be erased in turn.
Programming/erase time
It takes 10 ms (typ.) to program the flash memory 128 bytes at a time; 80 µs (typ.) per 1 byte.
Erasing one block takes 100 ms (typ.).
Reprogramming capability
The flash memory can be reprogrammed up to 100 times.
Two flash memory on-board programming modes
Boot mode
User program mode
On-board programming/erasing can be done in boot mode in which the boot program built into
the chip is started for erase or programming of the entire flash memory. In user program mode,
individual blocks can be erased or programmed.
Automatic bit rate adjustment
With data transfer in boot mode, this LSI's bit rate can be automatically adjusted to match the
transfer bit rate of the host.
Programming/erasing protection
Sets protection against flash memory programming/erasing via hardware, software, or error
protection.
Rev. 1.00, 05/04, page 432 of 544
Programmer mode
In addition to on-board programming mode, programmer mode is supported to program or
erase the flash memory using a PROM programmer.
Bus interface/controller
Flash memory
(64 Kbytes)
Operating
mode
Internal address bus
Internal data bus (16 bits)
Mode pin
FLMCR2
EBR1
EBR2
FLMCR1
[Legend]
FLMCR1: Flash memory control register 1
FLMCR2: Flash memory control register 2
EBR1: Erase block register 1
EBR2: Erase block register 2
Module bus
Figure 18.1 Block Diagram of Flash Memory
Rev. 1.00, 05/04, page 433 of 544
18.2 Mode Transitions
When the mode pins are set in the reset state and a reset-start is executed, this LSI enters an
operating mode as shown in figure 18.2. In user mode, flash memory can be read but not
programmed or erased. The boot, user program, and programmer modes are provided as modes to
write and erase the flash memory.
The differences between boot mode and user program mode are shown in table 18.1. Figure 18.3
shows the boot mode and figure 18.4 shows the user program mode.
RES = 0
RES = 0
FLSHE = 1
SWE = 1
FLSHE = 0
SWE = 0 *
1
*
2
RES = 0
MD1 = 1
RES = 0
Boot mode
On-board programming mode
User
program
mode
User mode
(on-chip ROM
enabled)
Reset state
Programmer
mode
Notes: Only make a transition between user mode
and user program mode when the CPU is not
accessing the flash memory.
1. MD1 = MD0 = 0, P92 = P91 = P90 = 1
2. MD1 = MD0 = 0, P92 = 0, P91 = P90 = 1
Figure 18.2 Flash Memory State Transitions
Table 18.1 Differences between Boot Mode and User Program Mode
Boot Mode User Program Mode
Total erase Yes Yes
Block erase No Yes
Programming control program* Program/program-verify Program/program-verify
Erase/erase-verify
Note: * Should be provided by the user, in accordance with the recommended algorithm.
Rev. 1.00, 05/04, page 434 of 544
<Flash memory>
<This LSI>
<RAM>
<Host>
Programming
control program
SCI
Application
program
(old version)
Boot program
New
application program
<Flash memory>
<This LSI>
<RAM>
<Host>
SCI
Application
program
(old version)
Boot program area
New
application program
<Flash memory>
<This LSI>
<RAM>
<Host>
SCI
Flash memory
erase
Boot program
New
application program
<Flash memory>
<This LSI>
Program execution state
<RAM>
<Host>
SCI
New
application
program
Boot program
Programming
control program
Boot program area
Boot program
1. Initial state
The flash memory is erased at shipment.
The following describes how to write over
an old-version application program or data in
the flash memory. The user should prepare
the programming control program and
new application program beforehand in the host.
2. SCI communication check
When boot mode is entered, the boot program in
this LSI (originally incorporated in the chip) is started
and SCI communication is checked. Then the boot
program required for flash memory erasing is
automatically transferred to the RAM boot program
area.
3. Flash memory initialization
The erase program in the boot program area
(in RAM) is executed, and the flash memory is
initialized (to H'FF). In boot mode, total flash
memory erasure is performed, without regard to
blocks.
4. Writing new application program
The programming control program transferred from
the host to RAM via SCI communication is executed,
and the new application program in the host is written
into the flash memory.
Boot program area
Programming
control program
Programming
control program
Figure 18.3 Boot Mode
Rev. 1.00, 05/04, page 435 of 544
<Flash memory>
<This LSI>
<RAM>
<Host>
Programming/
erase control program
SCI
Boot program
New
application program
<Flash memory>
<This LSI>
<RAM>
<Host>
SCI
New
application program
<Flash memory>
<This LSI>
<RAM>
<Host>
SCI
Flash memory
erase
Boot program
New
application program
<Flash memory>
<This LSI>
Program execution state
<RAM>
<Host>
SCI
Boot program
Programming/
erase control program
Boot program
Transfer program
Application
program
(old version)
Application
program
(old version)
New
application
program
Transfer program Transfer program
Programming/
erase control program
Programming/
erase control program
Transfer program
1. Initial state
(1) The program that will transfer the programming/erase
control program from flash memory to on-chip RAM
should be written into the flash memory by the user
beforehand.
(2) The programming/erase control program should be
prepared in the host or in the flash memory.
2. Programming/erase control program transfer
The transfer program in the flash memory is executed and
the programming/erase control program is transferred to RAM.
3. Flash memory initialization
The programming/erase program in RAM is executed, and
the flash memory is initialized (to H'FF). Erasing can be
performed in block units, but not in byte units.
4. Writing new application program
Next, the new application program in the host is written into
the erased flash memory blocks. Do not write to unerased
blocks.
Figure 18.4 User Program Mode (Example)
Rev. 1.00, 05/04, page 436 of 544
18.3 Block Configuration
Figure 18.5 shows the block configuration of flash memory. The thick lines indicate erasing units,
the narrow lines indicate programming units, and the values are addresses. The flash memory is
divided into 8 Kbytes (2 blocks), 16 Kbytes (1 block), 28 Kbytes (1 block), and 1 Kbyte (4
blocks). Erasing is performed in these divided units. Programming is performed in 128-byte units
starting from an address whose lower bits are H'00 or H'80.
EB0
Erase unit: 1 Kbyte
EB1
Erase unit: 1 Kbyte
EB2
Erase unit: 1 Kbyte
EB3
Erase unit: 1 Kbyte
EB4
Erase unit: 28 Kbytes
EB5
Erase unit: 16 Kbytes
EB6
Erase unit: 8 Kbytes
EB7
Erase unit: 8 Kbytes
H'000000 H'000001 H'000002 H'00007F
H'0003FF
H'00047F
H'00087F
H'000C7F
H'00107F
H'007FFF
H'00807F
H'00BFFF
H'0007FF
H'000BFF
H'000FFF
H'00C07F
H'00DFFF
H'00E07F
H'00FFFF
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
H'000400 H'000401 H'000402
H'000800 H'000801 H'000802
H'000C00 H'000C01 H'000C02
H'001000 H'001001 H'001002
H'008000 H'008001 H'008002
H'00C000 H'00C001 H'00C002
H'00E000 H'00E001 H'00E002
H'000380 H'000381 H'000382
H'000780 H'000781 H'000782
H'000B80 H'000B81 H'000B82
H'000F80 H'000F81 H'000F82
H'007F80 H'007F81 H'007F82
H'00BF80 H'00BF81 H'00BF82
H'00DF80 H'00DF81 H'00DF82
H'00FF80 H'00FF81 H'00FF82
– – – – – – – – – – – – – –
– – – – – – – – – – – – – –
– – – – – – – – – – – – – –
– – – – – – – – – – – – – –
– – – – – – – – – – – – – –
– – – – – – – – – – – – – –
– – – – – – – – – – – – – –
– – – – – – – – – – – – – –
Figure 18.5 Flash Memory Block Configuration
Rev. 1.00, 05/04, page 437 of 544
18.4 Input/Output Pins
The flash memory is controlled by means of the pins shown in table 18.2.
Table 18.2 Pin Configuration
Pin Name I/O Function
RES Input Reset
MD1 Input Sets this LSI's operating mode
MD0 Input Sets this LSI's operating mode
P92 Input Sets this LSI's operating mode
P91 Input Sets this LSI's operating mode
P90 Input Sets this LSI's operating mode
TxD1 Output Serial transmit data output
RxD1 Input Serial receive data input
18.5 Register Descriptions
The flash memory has the following registers. To access FLMCR1, FLMCR2, EBR1, or EBR2,
the FLSHE bit in the serial/timer control register (STCR) should be set to 1. For details on the
serial/timer control register, refer to section 3.2.3, Serial Timer Control Register (STCR).
Flash memory control register 1 (FLMCR1)
Flash memory control register 2 (FLMCR2)
Erase block register 1 (EBR1)
Erase block register 2 (EBR2)
Rev. 1.00, 05/04, page 438 of 544
18.5.1 Flash Memory Control Register 1 (FLMCR1)
FLMCR1, used together with FLMCR2, makes the flash memory transit to program mode,
program-verify mode, erase mode, or erase-verify mode. For details on register setting, refer to
section 18.8, Flash Memory Programming/Erasing.FLMCR1 is initialized to H'80 by a reset, or in
hardware standby mode, software standby mode, sub-active mode, sub-sleep mode, or watch
mode.
Bit Bit Name
Initial
Value R/W Description
7 FWE 1 R Flash Write Enable
Controls programming/erasing of on-chip flash
memory. This bit is always read as 0, and cannot be
modified.
6 SWE 0 R/W Software Write Enable
When this bit is set to 1, flash memory
programming/erasing is enabled. When this bit is
cleared to 0, the EV, PV, E, and P bits in this register,
the ESU and PSU bits in FLMCR2, and all EBR1 and
EBR2 bits cannot be set to 1. Do not clear these bits
and SWE to 0 simultaneously.
5
4
0
0
R
R
Reserved
These bits are always read as 0 and cannot be
modified.
3 EV 0 R/W Erase-Verify
When this bit is set to 1 while SWE = 1, the flash
memory transits to erase-verify mode. When it is
cleared to 0, erase-verify mode is cancelled.
2 PV 0 R/W Program-Verify
When this bit is set to 1 while SWE = 1, the flash
memory transits to program-verify mode. When it is
cleared to 0, program-verify mode is cancelled.
1 E 0 R/W Erase
When this bit is set to 1 while SWE = 1 and ESU = 1,
the flash memory transits to erase mode. When it is
cleared to 0, erase mode is cancelled.
0 P 0 R/W Program
When this bit is set to 1 while SWE = 1 and PSU = 1,
the flash memory transits to program mode. When it is
cleared to 0, program mode is cancelled.
Rev. 1.00, 05/04, page 439 of 544
18.5.2 Flash Memory Control Register 2 (FLMCR2)
FLMCR2 monitors the state of flash memory programming/erasing protection (error protection)
and sets up the flash memory to transit to programming/erasing mode. FLMCR2 is initialized to
H'00 by a reset or in hardware standby mode. The ESU and PSU bits are cleared to 0 in software
standby mode, sub-active mode, sub-sleep mode, or watch mode, or when the SWE bit in
FLMCR1 is cleared to 0.
Bit Bit Name Initial
Value R/W Description
7 FLER 0 R Flash memory error
Indicates that an error has occurred during flash
memory programming/erasing. When this bit is set to 1,
flash memory goes to the error-protection state.
For details, see section 18.9.3, Error Protection.
6 to 2 All 0 R/(W) Reserved
The initial values should not be modified.
1 ESU 0 R/W Erase Setup
When this bit is set to 1 while SWE = 1, the flash
memory transits to the erase setup state. When it is
cleared to 0, the erase setup state is cancelled. Set this
bit to 1 before setting the E bit in FLMCR1 to 1.
0 PSU 0 R/W Program Setup
When this bit is set to 1 while SWE = 1, the flash
memory transits to the program setup state. When it is
cleared to 0, the program setup state is cancelled. Set
this bit to 1 before setting the P bit in FLMCR1 to 1.
Rev. 1.00, 05/04, page 440 of 544
18.5.3 Erase Block Registers 1 and 2 (EBR1, EBR2)
EBR1 and EBR2 are used to specify the flash memory erase block. EBR1 and EBR2 are
initialized to H'00 by a reset, or in hardware standby mode, software standby mode, sub-active
mode, sub-sleep mode, or watch mode, or when the SWE bit in FLMCR1 is cleared to 0. Set only
one bit to 1 at a time, otherwise all bits in EBR1 and EBR2 are automatically cleared to 0.
EBR1
Bit Bit Name Initial
Value R/W Description
7 to 0 All 0 R/(W) Reserved
The initial values should not be modified.
EBR2
Bit Bit Name Initial
Value R/W Description
7 EB7 0 R/W* When this bit is set to 1, 8 Kbytes of EB7
(H'00E000 to H'00FFFF) are to be erased.
6 EB6 0 R/W When this bit is set to 1, 8 Kbytes of EB6
(H'00C000 to H'00DFFF) are to be erased.
5 EB5 0 R/W When this bit is set to 1, 16 Kbytes of EB5
(H'008000 to H'00BFFF) are to be erased.
4 EB4 0 R/W When this bit is set to 1, 28 Kbytes of EB4
(H'001000 to H'007FFF) are to be erased.
3 EB3 0 R/W When this bit is set to 1, 1 Kbyte of EB3
(H'000C00 to H'000FFF) is to be erased.
2 EB2 0 R/W When this bit is set to 1, 1 Kbyte of EB2
(H'000800 to H'000BFF) is to be erased.
1 EB1 0 R/W When this bit is set to 1, 1 Kbyte of EB1
(H'000400 to H'0007FF) is to be erased.
0 EB0 0 R/W When this bit is set to 1, 1 Kbyte of EB0
(H'000000 to H'0003FF) is to be erased.
Note: * In normal mode, this bit is always read as 0 and cannot be modified.
Rev. 1.00, 05/04, page 441 of 544
18.6 Operating Modes
The flash memory is connected to the CPU via a 16-bit data bus, enabling byte data and word data
to be accessed in a single state. Even addresses are connected to the upper 8 bits and odd addresses
are connected to the lower 8 bits. Note that word data must start from an even address.
In normal mode (mode 3), up to 56 Kbytes of ROM can be used.
Table 18.3 Operating Modes and ROM
Operating Modes Mode Pins
MCU
Operating Mode CPU
Operating Mode Mode MD1 MD0 On-Chip ROM
Mode 2 Advanced Single-chip mode 1 0 Enabled (64 Kbytes)
Mode 3 Normal Single-chip mode 1 1 Enabled (56 Kbytes)
18.7 On-Board Programming Modes
An on-board programming mode is used to perform on-chip flash memory programming, erasing,
and verification. This LSI has two on-board programming modes: boot mode and user program
mode. Table 18.4 shows pin settings for boot mode. In user program mode, operation by software
is enabled by setting control bits. For details on flash memory mode transitions, see figure 18.2.
Table 18.4 On-Board Programming Mode Settings
Mode Setting MD1 MD0 P92 P91 P90
Boot mode 0 0 1* 1* 1*
Mode 2 (advanced mode) 1 0 User program mode
Mode 3 (normal mode) 1 1
Note: * Can be used as an I/O port after the boot mode activation.
Rev. 1.00, 05/04, page 442 of 544
18.7.1 Boot Mode
Table 18.5 shows the boot mode operations between reset end and branching to the programming
control program.
1. When boot mode is used, the flash memory programming control program must be prepared in
the host beforehand. Prepare a programming control program in accordance with the
description in section 18.8, Flash Memory Programming/Erasing. In boot mode, if any data
exists in the flash memory (except in the case that all data are 1), all blocks in the flash
memory are erased. Use boot mode at initial writing in the on-board state, or forced recovery
when user program mode cannot be executed because the program to be initiated in user
program mode was mistakenly erased.
2. The SCI_1 should be set to asynchronous mode, and the transfer format as follows: 8-bit data,
1 stop bit, and no parity.
3. When the boot program is initiated, this LSI measures the low-level period of asynchronous
SCI communication data (H'00) transmitted continuously from the host. This LSI then
calculates the bit rate of transmission from the host, and adjusts the SCI_1 bit rate to match
that of the host. The reset should end with the RxD1 pin high. The RxD1 and TxD1 pins
should be pulled up on the board if necessary. After the reset ends, it takes approximately 100
states before this LSI is ready to measure the low-level period.
4. After matching the bit rates, this LSI transmits one H'00 byte to the host to indicate the end of
bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has
been received normally, and transmit one H'55 byte to this LSI. If reception could not be
performed normally, initiate boot mode again by a reset. Depending on the host's transfer bit
rate and system clock frequency of this LSI, there will be a discrepancy between the bit rates
of the host and this LSI. To operate the SCI properly, set the host's transfer bit rate and system
clock frequency of this LSI within the ranges listed in table 18.6.
5. In boot mode, a part of the on-chip RAM area is used by the boot program. Addresses
H'FFE080 to H'FFE87F*1 is the area to which the programming control program is transferred
from the host. Note, however, that ID codes are assigned to addresses H'FFE080 to H'FFE087.
The boot program area cannot be used until the execution state in boot mode switches to the
programming control program. Figure 18.6 shows the on-chip RAM area in boot mode.
6. Before branching to the programming control program (H'FFE088 in the RAM area), this LSI
terminates transfer operations by the SCI_1 (by clearing the RE and TE bits in SCR to 0), but
the adjusted bit rate value remains set in BRR. Therefore, the programming control program
can still use it for transfer of write data or verify data with the host. The TxD1 pin is in high-
level output state. The contents of the CPU general registers are undefined immediately after
branching to the programming control program. These registers must be initialized at the
beginning of the programming control program, since the stack pointer (SP), in particular, is
used implicitly in subroutine calls, etc.
Rev. 1.00, 05/04, page 443 of 544
7. Boot mode can be cleared by a reset. Cancel the reset*2 after driving the reset pin low, waiting
at least 20 states, and then setting the mode pins. Boot mode is also cleared when a WDT
overflow occurs.
8. Do not change the mode pin input levels in boot mode.
9. All interrupts are disabled during programming or erasing of the flash memory.
Notes: 1. Some parts of this area are reserved only for boot mode and therefore should not be
used for any other purpose.
2. After reset is cancelled, mode pin input settings must satisfy the mode programming
setup time (tMDS = 4 states).
Table 18.5 Boot Mode Operation
Communications Contents
Processing Contents
Host Operation LSI Operation
Processing Contents
Continuously transmits data H'00
at specified bit rate.
Branches to boot program at reset-start.
Boot program start
Branches to programming control program
transferred to on-chip RAM and starts
execution.
H'00, H'00 . . . H'00
H'00
H'55
Transmits data H'55 when data H'00
is received error-free.
Boot program
erase error
H'FF
H'AA
Receives data H'AA.
Receives data H'AA.
H'AA
Echobacks the 2-byte data received to host.
Echobacks received data to host and also
transfers it to RAM (repeated for N times).
High-order byte and
low-order byte
Echoback
Echoback
H'XX
Transmits number of bytes (N) of
programming control program to be
transferred as 2-byte data (low-order byte
following high-order byte).
Transmits 1-byte of programming control
program (repeated for N times).
ItemBoot mode start
• Measures low-level period of receive data H'00.
• Calculates bit rate and sets it in BRR of SCI_1.
• Transmits data H'00 to host as adjustment end
indication.
Bit rate adjustment
Checks flash memory data, erases all flash
memory blocks in case of written data
existing, and transmits data H'AA to host.
(If erase could not be done, transmits data
H'FF to host and aborts operation.)
Flash memory erase
Transfer of programming
control program
After receiving data H'55, transmits data
H'AA to host.
Rev. 1.00, 05/04, page 444 of 544
Table 18.6 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is
Possible
Host Bit Rate System Clock Frequency Range of LSI
19200 bps 8 to 10 MHz
9600 bps 4 to 10 MHz
4800 bps 4 to 10 MHz
Boot program area*
2
(128 bytes)
H'FFFF7F
H'FFFF00
H'FFEFFF
H'FFE880
H'FFE088
H'FFE080
ID code area*
1
Programming control program area*
1
(2040 bytes)
Boot program area*
2
(1920 bytes)
Notes: 1. Some parts of this area are reserved only for boot mode and therefore should not be
used for any other purpose.
2. The boot program area and area which is not used cannot be used until a transition is
made to the execution state for the programming control program transferred to RAM.
Note that the contents of the boot program area in RAM are remained after a branch is
made to the programming control program.
Figure 18.6 On-Chip RAM Area in Boot Mode
In boot mode, this LSI checks the contents of the 8-byte ID code area as shown below to confirm
that the programming control program corresponds with this LSI. To originally write a
programming control program to be used in boot mode, the above 8-byte ID code must be added at
the beginning of the program.
H'FFE080
H'FFE088
3040 FE 64 66 32 31 31
Instruction codes of the programming control program
(Product ID)
Figure 18.7 ID Code Area
Rev. 1.00, 05/04, page 445 of 544
18.7.2 User Program Mode
On-board programming/erasing of an individual flash memory block can also be performed in user
program mode by branching to a user program/erase control program. The user must set branching
conditions and provide on-board means of supplying programming data. The flash memory must
contain the user program/erase control program or a program which provides the user
program/erase control program from external memory. Because the flash memory itself cannot be
read during programming/erasing, transfer the user program/erase control program to on-chip
RAM, as like in boot mode. Figure 18.8 shows a sample procedure for programming/erasing in
user program mode. Prepare a user program/erase control program in accordance with the
description in section 18.8, Flash Memory Programming/Erasing.
Ye s
No
Program/erase?
Reset-start
Branch to flash memory
application program
Transfer user program/
erase control program to RAM Branch to flash memory
application program
Branch to user program/
erase control program in RAM
Execute user program/erase control
program (flash memory rewrite)
Figure 18.8 Programming/Erasing Flowchart Example in User Program Mode
Rev. 1.00, 05/04, page 446 of 544
18.8 Flash Memory Programming/Erasing
A software method, using the CPU, is employed to program and erase flash memory in the on-
board programming modes. Depending on the FLMCR1 and FLMCR2 settings, the flash memory
operates in one of the following four modes: program mode, program-verify mode, erase mode,
and erase-verify mode. The programming control program in boot mode and the user
program/erase control program in user program mode use these operating modes in combination to
perform programming/erasing. Flash memory programming and erasing should be performed in
accordance with the descriptions in section 18.8.1, Program/Program-Verify and section 18.8.2,
Erase/Erase-Verify, respectively.
18.8.1 Program/Program-Verify
When writing data or programs to the flash memory, the program/program-verify flowchart shown
in figure 18.9 should be followed. Performing programming operations according to this flowchart
will enable data or programs to be written to the flash memory without subjecting this LSI to
voltage stress or sacrificing program data reliability.
1. Programming must be done to an empty address. Do not reprogram an address to which
programming has already been performed.
2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be
performed even if writing fewer than 128 bytes. In this case, H'FF data must be written to the
extra addresses.
3. Prepare the following data storage areas in RAM: a 128-byte programming data area, a 128-
byte reprogramming data area, and a 128-byte additional-programming data area. Perform
reprogramming data computation and additional programming data computation according to
figure 18.9.
4. Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or
additional-programming data area to the flash memory. The program address and 128-byte
data are latched in the flash memory. The lower 8 bits of the start address in the flash memory
destination area must be H'00 or H'80.
5. The time during which the P bit is set to 1 is the programming time. Figure 18.9 shows the
allowable programming times.
6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.
The overflow cycle should be longer than (y + z2 + α + β) µs.
7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 2 bits
are B'00. Verify data can be read in words from the address to which a dummy write was
performed.
8. The maximum number of repetitions of the program/program-verify sequence to the same bit
is (N).
Rev. 1.00, 05/04, page 447 of 544
START
End of programming
Set SWE bit in FLMCR1
Start of programmingWrite pulse application subroutine
Wait (x) µs
Sub-Routine Write Pulse
End Sub
Set PSU bit in FLMCR2
WDT enable
Disable WDT
Number of Writes n
1
2
3
4
5
6
7
8
9
10
11
12
13
998
999
1000
Note 7: Write Pulse Width
Write Time (z) µs
z1
z1
z1
z1
z1
z1
z2
z2
z2
z2
z2
z2
z2
z2
z2
z2
Wait (γ) µs
Set P bit in FLMCR1
Wait (z1) µs, (z2) µs or (z3) µs
Clear P bit in FLMCR1
Wait (α) µs
Clear PSU bit in FLMCR2
Wait (β) µs
n = 1
m = 0
NG
NG
NG
NG
NG
OK
OK
OK
Wait (γ) µs
Wait (ε) µs
*2
*4
*5
*1
Wait (η) µs
Apply write pulse z1 µs or z2 µs
Sub-Routine-Call
Set PV bit in FLMCR1
H'FF dummy write to verify address
Read verify data
Write data =
verify data?
*4
*3
*3
*1
Transfer reprogram data to reprogram data area
Reprogram data computation
*4
Transfer additional-programming data to
additional-programming data area
Additional-programming data computation
Clear PV bit in FLMCR1
Clear SWE bit in FLMCR1
m = 1
See Note 7 for pulse width
m = 0 ?
Increment address
Programming failure
OK
Clear SWE bit in FLMCR1
Wait (θ) µs
µs
OK
6 n?
NG
OK
6 n ?
Wait (θ) µs
n (N)?
n n + 1
Original Data
(D) Verify Data
(V) Reprogram Data
(X) Comments
Programming completed
Still in erased state; no action
Programming incomplete;
reprogram
Note:
Use a z3 µs write pulse for additional programming.
Write 128-byte data in RAM reprogram
data area consecutively to flash memory
RAM
Program data storage
area (128 bytes)
Reprogram data storage
area (128 bytes)
Additional-programming
data storage area
(128 bytes)
Store 128-byte program data in program
data area and reprogram data area
Apply write pulse (Additional programming)
128-byte
data verification completed?
Successively write 128-byte data from additional-
programming data area in RAM to flash memory
Reprogram Data Computation Table
Reprogram Data
(X')
Verify Data
(V)
Additional-
Programming Data
(Y)
1
1
1
1
0
1
0
000
1
1
Comments
Additional programming
to be executed
Additional programming
not to be executed
Additional programming
not to be executed
0
1
1
1
0
1
0
100
1
1
Additional-Programming Data Computation Table
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must be performed even if
writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
2. Verify data is read in 16-bit (word) units.
3. Even bits for which programming has been completed will be subjected to programming once again if the result of the subsequent verify operation is NG.
4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional data must be provided in RAM.
The contents of the reprogram data area and additional data area are modified as programming proceeds.
5. A write pulse of z1 µs or z2 µs is applied according to the progress of the programming operation. See Note7 for details of the pulse widths. When writing of
additional-programming data is executed, a z3 µs write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.
6. The values of x, y, z1, z2, z3, α, β, γ, ε, η, θ, and N are shown in section 22.5, Flash Memory Characteristics.
Figure 18.9 Program/Program-Verify Flowchart
Rev. 1.00, 05/04, page 448 of 544
18.8.2 Erase/Erase-Verify
When erasing flash memory, the erase/erase-verify flowchart shown in figure 18.10 should be
followed.
1. Prewriting (setting erase block data to all 0) is not necessary.
2. Erasing is performed in block units. Make only a single-block specification in erase block
registers 1 and 2 (EBR1 and EBR2). To erase multiple blocks, each block must be erased in
turn.
3. The time during which the E bit is set to 1 is the flash memory erase time.
4. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.
An overflow cycle of approximately (y + z + α + β) ms is allowed.
5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower two
bits are B'00. Verify data can be read in longwords from the address to which a dummy write
was performed.
6. If the read data is unerased, set erase mode again, and repeat the erase/erase-verify sequence as
before. The maximum number of repetitions of the erase/erase-verify sequence is N.
Rev. 1.00, 05/04, page 449 of 544
End of erasing
START
Set SWE bit in FLMCR1
Set ESU bit in FLMCR2
Set E bit in FLMCR1
Wait (x) µs
Wait (y) µs
n = 1
Set EBR1 and EBR2
Enable WDT
*4
*2
*2
*2
*2
*2
*2
*2
*2*2
*2
Wait (z) ms
Wait (α) µs
Wait (β) µs
Wait (γ) µs
Set block start address
as verify address
Wait (ε) µs
Wait (η) µs
*5
*3
Start of erasing
Clear E bit in FLMCR1
Clear ESU bit in FLMCR2
Set EV bit in FLMCR1
H'FF dummy write to verify address
Read verify data
Clear EV bit in FLMCR1
Wait (η) µs
Clear EV bit in FLMCR1
Clear SWE bit in FLMCR1
Disable WDT
End of erasing
*1
Verify data
= all "1"?
Last address
of block?
All erase blocks erased?
Erase failure
Clear SWE bit in FLMCR1
n (N) ?
NG
NG
NG NG
OK
OK
OK
OK
Increment
address
n n + 1
Wait (θ) µsWait (θ) µs
Notes: 1. Prewriting (writing 0 to all data in erased block) is not necessary.
2. The values of x, y, z, α, β, γ, ε, η, θ, and N are shown in section 22.5, Flash Memory Characteristics.
3. Verify data is read in 16-bit (word) units.
4. Set only a single bit in EBR1 and EBR2. Do not set more than one bit.
5. Erasing is performed in block units. To erase multiple blocks, each block must be erased in turn.
Figure 18.10 Erase/Erase-Verify Flowchart
Rev. 1.00, 05/04, page 450 of 544
18.9 Program/Erase Protection
There are three kinds of flash memory program/erase protection: hardware protection, software
protection, and error protection.
18.9.1 Hardware Protection
Hardware protection is a state in which programming/erasing of flash memory is forcibly disabled
or aborted by a reset (including WDT overflow reset), or a transition to hardware standby mode,
software standby mode, sub-active mode, sub-sleep mode or watch mode. Flash memory control
registers 1 and 2 (FLMCR1 and FLMCR2) and erase block registers 1 and 2 (EBR1 and EBR2)
are initialized. In a reset via the RES pin, the reset state is not entered unless the RES pin is held
low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the
RES pin low for the RES pulse width specified in the AC Characteristics section.
18.9.2 Software Protection
Software protection can be implemented against programming/erasing of all flash memory blocks
by clearing the SWE bit in FLMCR1 to 0. When software protection is in effect, setting the P or E
bit in FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase
block registers 1 and 2 (EBR1 and EBR2), erase protection can be set for individual blocks. When
EBR1 and EBR2 are set to H'00, erase protection is set for all blocks.
18.9.3 Error Protection
In error protection, an error is detected when the CPU's runaway occurs during flash memory
programming/erasing, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is aborted. Aborting the program/erase operation
prevents damage to the flash memory due to overprogramming or overerasing.
When the following errors are detected during programming/erasing of flash memory, the FLER
bit in FLMCR2 is set to 1, and the error protection state is entered.
When the flash memory of is read during programming/erasing (including vector read and
instruction fetch)
Immediately after exception handling (excluding a reset) during programming/erasing
When a SLEEP instruction is executed (transits to software standby mode, sleep mode, sub-
active mode, sub-sleep mode, or watch mode) during programming/erasing
Rev. 1.00, 05/04, page 451 of 544
The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, but program mode or erase
mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be
entered by setting the P or E bit to 1. However, because the PV and EV bit settings are retained, a
transition to verify mode can be made. The error protection state can be cancelled by a reset or in
hardware standby mode.
18.10 Interrupts during Flash Memory Programming/Erasing
In order to give the highest priority to programming/erasing operations, disable all interrupts
including NMI input during flash memory programming/erasing (the P or E bit in FlMCR1 is set
to 1) or boot program execution*1.
1. If an interrupt is generated during programming/erasing, operation in accordance with the
program/erase algorithm is not guaranteed.
2. CPU runaway may occur because normal vector reading cannot be performed in interrupt
exception handling during programming/erasing*2.
3. If an interrupt occurs during boot program execution, the normal boot mode sequence cannot
be executed.
Notes: 1. Interrupt requests must be disabled inside and outside the CPU until the programming
control program has completed programming.
2. The vector may not be read correctly for the following two reasons:
If flash memory is read while being programmed or erased (while the P or E bit in
FLMCR1 is set to 1), correct read data will not be obtained (undefined values will be
returned).
If the interrupt entry in the vector table has not been programmed yet, interrupt
exception handling will not be executed correctly.
Rev. 1.00, 05/04, page 452 of 544
18.11 Programmer Mode
In programmer mode, the on-chip flash memory can be programmed/erased by a PROM
programmer via a socket adapter, just like for a discrete flash memory. Use a PROM programmer
that supports the Renesas 64-Kbyte flash memory on-chip MCU device*. Figure 18.11 shows a
memory map in programmer mode.
Note: Set the programming voltage of the PROM programmer to 3.3V.
On-chip ROM area
MCU mode
H'000000
Programmer mode
H'00000
H'00FFFF H'0FFFF
Undefined value output
H'1FFFF
Figure 18.11 Memory Map in Programmer Mode
Rev. 1.00, 05/04, page 453 of 544
18.12 Usage Notes
The following lists notes on the use of on-board programming modes and programmer mode.
1. Perform programming/erasing with the specified voltage and timing.
If a voltage higher than the rated voltage is applied, the product may be fatally damaged. Use a
PROM programmer that supports the Renesas 64-Kbyte flash memory on-chip MCU device at
3.3 V. Do not set the programmer to HN28F101 or the programming voltage to 5.0 V.
2. Notes on power on/off
At powering on or off the Vcc power supply, fix the RES pin to low and set the flash memory
to hardware protection state. This power on/off timing must also be satisfied at a power-off and
power-on caused by a power failure and other factors.
3. Perform flash memory programming/erasing in accordance with the recommended algorithm
In the recommended algorithm, flash memory programming/erasing can be performed without
subjecting this LSI to voltage stress or sacrificing program data reliability. When setting the P
or E bit in FLMCR1 to 1, set the watchdog timer against program runaway.
4. Do not set/clear the SWE bit during program execution in the flash memory.
Do not set/clear the SWE bit during program execution in the flash memory. An interval of at
least 100 µs is necessary between program execution or data reading in flash memory and
SWE bit clearing. When the SWE bit is set to 1, flash memory data can be modified, however,
flash memory data can be read only in program-verify or erase-verify mode. Do not access the
flash memory for a purpose other than verification during programming/erasing. Do not clear
the SWE bit during programming, erasing, or verifying.
5. Do not use interrupts during flash memory programming/erasing
In order to give the highest priority to programming/erasing operation, disable all interrupts
including NMI input when the flash memory is programmed or erased.
6. Do not perform additional programming. Programming must be performed in the erased state.
Program the area with 128-byte programming-unit blocks in on-board programming or
programmer mode only once. Perform programming in the state where the programming-unit
block is fully erased.
7. Ensure that the PROM programmer is correctly attached before programming.
If the socket, socket adapter, or product index does not match the specifications, too much
current flows and the product may be damaged.
8. Do not touch the socket adapter or LSI while programming.
Touching either of these can cause contact faults and write errors.
Rev. 1.00, 05/04, page 454 of 544
Rev. 1.00, 05/04, page 455 of 544
Section 19 Clock Pulse Generator
This LSI incorporates a clock pulse generator, which generates the system clock (φ), bus master
clock, and internal clock.
The clock pulse generator consists of an oscillator, duty correction circuit, clock select circuit,
medium-speed clock divider, bus master clock select circuit, subclock input circuit, and waveform
forming circuit. Figure 19.1 shows a block diagram of the clock pulse generator.
Oscillator
Duty
correction
circuit
Clock select
circuit
Medium-
speed clock
divider Bus master
clock select
circuit
Subclock
input circuit
Waveform
forming
circuit
EXTAL
XTAL
EXCL
φ/2
to φ/32
φSUB
φ
WDT_1
count clock
System clock
to φ pin
Internal clock
to peripheral
modules
Bus master cloc
k
to CPU
Figure 19.1 Block Diagram of Clock Pulse Generator
The bus master clock is selected as either high-speed mode or medium-speed mode by software
according to the settings of the SCK2 to SCK0 bits in the standby control register. For details on
the standby control register, refer to section 20.1.1, Standby Control Register (SBYCR).
The subclock input is controlled by software according to the EXCLE bit setting in the low power
control register. For details on the low power control register, refer to section 20.1.2, Low Power
Control Register (LPWRCR).
Rev. 1.00, 05/04, page 456 of 544
19.1 Oscillator
Clock pulses can be supplied either by connecting a crystal resonator, or by providing external
clock input.
19.1.1 Connecting Crystal Resonator
Figure 19.2 shows a typical method of connecting a crystal resonator. An appropriate damping
resistance Rd, given in table 19.1, should be used. An AT-cut parallel-resonance crystal resonator
should be used.
Figure 19.3 shows the equivalent circuit of a crystal resonator. A resonator having the
characteristics given in table 19.2 should be used.
A crystal resonator with frequency identical to that of the system clock (φ) should be used.
EXTAL
XTAL
R
d
C
L2
C
L1
C
L1
= C
L2
= 10 to 22 pF
Figure 19.2 Typical Connection to Crystal Resonator
Table 19.1 Damping Resistance Values
Frequency (MHz) 4 8 10
Rd () 500 200 0
XTAL
C
L
AT-cut parallel-resonance crystal resonato
r
EXTAL
C
0
LR
s
Figure 19.3 Equivalent Circuit of Crystal Resonator
Table 19.2 Crystal Resonator Parameters
Frequency (MHz) 4 8 10
RS (max) () 120 80 70
C0 (max) (pF) 7 7 7
Rev. 1.00, 05/04, page 457 of 544
19.1.2 External Clock Input Method
Figure 19.4 shows a typical method of connecting an external clock signal. To leave the XTAL pin
open, incidental capacitance should be 10 pF or less.
To input an inverted clock to the XTAL pin, the external clock should be set to high in standby
mode, subactive mode, subsleep mode, and watch mode. External clock input conditions are
shown in table 19.3. The frequency of the external clock should be the same as that of the system
clock (φ).
EXTAL
XTAL
External clock input
Open
(a) Example of external clock input when XTAL pin left open
EXTAL
XTAL
External clock input
(b) Example of external clock input when an inverted clock is input to XTAL pin
Figure 19.4 Example of External Clock Input
Rev. 1.00, 05/04, page 458 of 544
Table 19.3 External Clock Input Conditions
VCC =3.0 to 3.6 V
Item Symbol Min Max Unit Test Conditions
External clock input pulse
width low level
tEXL 40 ns
External clock input pulse
width high level
tEXH 40 ns
External clock rising time tEXr 10 ns
External clock falling time tEXf 10 ns
Figure 19.5
0.4 0.6 tcyc φ 5 MHz Clock pulse width low level tCL
80 — ns φ < 5 MHz
0.4 0.6 tcyc φ 5 MHz Clock pulse width high
level
tCH
80 — ns φ < 5 MHz
Figure 22.5
tEXH tEXL
tEXr tEXf
VCC × 0.5
EXTAL
Figure 19.5 External Clock Input Timing
The oscillator and duty correction circuit have a function to adjust the waveform of the external
clock input that is input to the EXTAL pin. When a specified clock signal is input to the EXTAL
pin, internal clock signal output is determined after the external clock output stabilization delay
time (tDEXT) has passed. As the clock signal output is not determined during the tDEXT cycle, a reset
signal should be set to low to hold it in reset state. Table 19.4 shows the external clock output
stabilization delay time. Figure 19.6 shows the timing of the external clock output stabilization
delay time.
Table 19.4 External Clock Output Stabilization Delay Time
Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V
Item Symbol Min. Max. Unit Remarks
External clock output stabilization delay
time
tDEXT* 500 µs Figure 19.6
Note: * t
DEXT includes a RES pulse width (tRESW).
Rev. 1.00, 05/04, page 459 of 544
t
DEXT
*
RES
(Internal and external)
EXTAL
STBY
V
CC
3.0 V
V
IH
φ
Note: * The external clock output stabilization delay time (t
DEXT
) includes a RES pulse width (t
RESW
).
Figure 19.6 Timing of External Clock Output Stabilization Delay Time
19.2 Duty Correction Circuit
The duty correction circuit is valid when the oscillating frequency is 5 MHz or more. It corrects
the duty of a clock that is output from the oscillator, and generates the system clock (φ).
19.3 Medium-Speed Clock Divider
The medium-speed clock divider divides the system clock (φ), and generates φ/2, φ/4, φ/8, φ/16,
and φ/32 clocks.
19.4 Bus Master Clock Select Circuit
The bus master clock select circuit selects a clock to supply the bus master with either the system
clock (φ) or medium-speed clock (φ/2, φ/4, φ/8, φ/16, or φ/32) by the SCK2 to SCK0 bits in
SBYCR.
Rev. 1.00, 05/04, page 460 of 544
19.5 Subclock Input Circuit
The subclock input circuit controls subclock input from the EXCL pin. To use the subclock, a
32.768-kHz external clock should be input from the EXCL pin. At this time, the P96DDR bit in
P9DDR should be cleared to 0, and the EXCLE bit in LPWRCR should be set to 1.
Subclock input conditions are shown in table 19.5. When the subclock is not used, subclock input
should not be enabled.
Table 19.5 Subclock Input Conditions
Vcc = 3.0 to 3.6 V
Item Symbol Min Typ Max Unit
Measurement
Condition
Subclock input pulse width
low level
tEXCLL 15.26 µs
Subclock input pulse width
high level
tEXCLH 15.26 µs
Subclock input rising time tEXCLr — — 10 ns
Subclock input falling time tEXCLf — — 10 ns
Figure 19.7
tEXCLH tEXCLL
tEXCLr tEXCLf
VCC × 0.5
EXCL
Figure 19.7 Subclock Input Timing
19.6 Waveform Forming Circuit
To remove noise from the subclock input at the EXCL pin, the subclock is sampled by a divided φ
clock. The sampling frequency is set by the NESEL bit in LPWRCR.
The subclock is not sampled in subactive mode, subsleep mode, or watch mode.
Rev. 1.00, 05/04, page 461 of 544
19.7 Clock Select Circuit
The clock select circuit selects the system clock that is used in this LSI.
A clock generated by an oscillator to which the EXTAL and XTAL pins are input is selected as a
system clock when returning from high-speed mode, medium-speed mode, sleep mode, reset state,
or standby mode.
A subclock input from the EXCL pin is selected as a system clock in subactive mode, subsleep
mode, or watch mode. At this time, modules such as the CPU, TMR_0, TMR_1, WDT_0,
WDT_1, ports, and interrupt controller and their functions operate depending on the φSUB. The
count clock and sampling clock for each timer are divided φSUB clocks.
19.8 Usage Notes
19.8.1 Note on Resonator
Since all kinds of characteristics of the resonator are closely related to the board design by the
user, use the example of resonator connection in this document for only reference; be sure to use
an resonator that has been sufficiently evaluated by the user. Consult with the resonator
manufacturer about the resonator circuit ratings which vary depending on the stray capacitances of
the resonator and installation circuit. Make sure the voltage applied to the oscillator pins does not
exceed the maximum rating.
19.8.2 Notes on Board Design
When using a crystal resonator, the crystal resonator and its load capacitors should be placed as
close as possible to the XTAL and EXTAL pins.
Other signal lines should be routed away from the oscillator circuit to prevent inductive
interference with the correct oscillation as shown in figure 19.8.
C
L2
Signal A Signal B
C
L1
This LSI
XTAL
EXTAL
Avoid
Figure 19.8 Note on Board Design of Oscillator Circuit Section
Rev. 1.00, 05/04, page 462 of 544
Rev. 1.00, 05/04, page 463 of 544
Section 20 Power-Down Modes
For operating modes after the reset state is cancelled, this LSI has not only the normal program
execution state but also seven power-down modes in which power consumption is significantly
reduced. In addition, there is also module stop mode in which reduced power consumption can be
achieved by individually stopping on-chip peripheral modules.
Medium-speed mode
System clock frequency for the CPU operation can be selected as φ/2, φ/4, φ/8, φ/16, or φ/32.
Subactive mode
The CPU operates based on the subclock and on-chip peripheral modules other than TMR_0,
TMR_1, WDT_0, and WDT_1 stop operating.
Sleep mode
The CPU stops but on-chip peripheral modules continue operating.
Subsleep mode
The CPU and on-chip peripheral modules other than TMR_0, TMR_1, WDT_0, and WDT_1
stop operating.
Watch mode
The CPU and on-chip peripheral modules other than WDT_1 stop operating.
Software standby mode
Clock oscillation stops, and the CPU and on-chip peripheral modules stop operating.
Hardware standby mode
Clock oscillation stops, and the CPU and on-chip peripheral modules enter reset state.
Module stop mode
Independently of above operating modes, on-chip peripheral modules that are not used can be
stopped individually.
20.1 Register Descriptions
Power-down modes are controlled by the following registers. To access SBYCR, LPWRCR,
MSTPCRH, and MSTPCRL, the FLSHE bit in the serial timer control register (STCR) must be
cleared to 0. For details on STCR, see section 3.2.3, Serial Timer Control Register (STCR).
Standby control register (SBYCR)
Low power control register (LPWRCR)
Module stop control register H (MSTPCRH)
Module stop control register L (MSTPCRL)
Rev. 1.00, 05/04, page 464 of 544
20.1.1 Standby Control Register (SBYCR)
SBYCR controls power-down modes.
Bit Bit Name
Initial
Value R/W Description
7 SSBY 0 R/W Software Standby
Specifies the operating mode to be entered after
executing the SLEEP instruction.
When the SLEEP instruction is executed in high-speed
mode or medium-speed mode:
0: Shifts to sleep mode
1: Shifts to software standby mode, subactive mode, or
watch mode
When the SLEEP instruction is executed in subactive
mode:
0: Shifts to subsleep mode
1: Shifts to watch mode or high-speed mode
Note that the SSBY bit is not changed even if a mode
transition occurs by an interrupt.
6
5
4
STS2
STS1
STS0
0
0
0
R/W
R/W
R/W
Standby Timer Select 2 to 0
Selects the wait time for clock stabilization from clock
oscillation start when canceling software standby mode,
watch mode, or subactive mode. Select a wait time of 8
ms (oscillation stabilization time) or more, depending on
the operating frequency. Table 20.1 shows the
relationship between the STS2 to STS0 values and wait
time.
With an external clock, there are no specific wait
requirements. Normally the minimum value is
recommended.
3 0 R Reserved
This bit is always read as 0, and cannot be modified.
2
1
0
SCK2
SCK1
SCK0
0
0
0
R/W
R/W
R/W
System Clock Select 2 to 0
Selects a clock for the bus master in high-speed mode
or medium-speed mode.
When making a transition to subactive mode or watch
mode, SCK2 to SCK0 must be cleared to 0.
000: High-speed mode
001: Medium-speed clock: φ/2
010: Medium-speed clock: φ/4
011: Medium-speed clock: φ/8
100: Medium-speed clock: φ/16
101: Medium-speed clock: φ/32
11X: —
[Legend]
X: Don't care
Rev. 1.00, 05/04, page 465 of 544
Table 20.1 Operating Frequency and Wait Time
STS2 STS1 STS0 Wait Time 10 MHz 8 MHz 6 MHz 4 MHz Unit
0 0 0 8192 states 0.8 1.0 1.3 20.
0 0 1 16384 states 1.6 2.0 2.7 4.1
0 1 0 32768 states 3.3 4.1 5.5 8.2
0 1 1 65536 states 6.6 8.2 10.9 16.4
1 0 0 131072 states 13.1 16.4 21.8 32.8
1 0 1 262144 states 26.2 32.8 43.6 65.6
1 1 0 Reserved
1 1 1 Reserved
ms
Shaded cells indicate the recommended specification.
20.1.2 Low-Power Control Register (LPWRCR)
LPWRCR controls power-down modes.
Bit Bit Name
Initial
Value R/W Description
7 DTON 0 R/W Direct Transfer On Flag
Specifies the operating mode to be entered after
executing the SLEEP instruction.
When the SLEEP instruction is executed in high-speed
mode or medium-speed mode:
0: Shifts to sleep mode, software standby mode, or
watch mode
1: Shifts directly to subactive mode, or shifts to sleep
mode or software standby mode
When the SLEEP instruction is executed in subactive
mode:
0: Shifts to subsleep mode or watch mode
1: Shifts directly to high-speed mode, or shifts to
subsleep mode
Rev. 1.00, 05/04, page 466 of 544
Bit Bit Name
Initial
Value R/W Description
6 LSON 0 R/W Low-Speed On Flag
Specifies the operating mode to be entered after
executing the SLEEP instruction. This bit also controls
whether to shift to high-speed mode or subactive mode
when watch mode is cancelled.
When the SLEEP instruction is executed in high-speed
mode or medium-speed mode:
0: Shifts to sleep mode, software standby mode, or
watch mode
1: Shifts to watch mode or subactive mode
When the SLEEP instruction is executed in subactive
mode:
0: Shifts directly to watch mode or high-speed mode
1: Shifts to subsleep mode or watch mode
When watch mode is cancelled:
0: Shifts to high-speed mode
1: Shifts to subactive mode
5 NESEL 0 R/W
Noise Elimination Sampling Frequency Select
Selects the frequency by which the subclock (φSUB)
input from the EXCL pin is sampled using the clock (φ)
generated by the system clock pulse generator. Clear
this bit to 0 when φ is 5 MHz or more.
0: Sampling using φ/32 clock
1: Sampling using φ/4 clock
4 EXCLE 0
R/W
Subclock Input Enable
Enables/disables subclock input from the EXCL pin.
0: Disables subclock input from the EXCL pin
1: Enables subclock input from the EXCL pin
3 0 R/W Reserved
An undefined value is read from this bit. This bit should
not be set to 1.
2 to 0 All 0 R Reserved
These bits are always read as 0 and cannot be
modified.
Rev. 1.00, 05/04, page 467 of 544
20.1.3 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL)
MSTPCRH and MSTPCRL specify on-chip peripheral modules to shift to module stop mode in
module units. Each module can enter module stop mode by setting the corresponding bit to 1.
MSTPCRH
Bit Bit Name
Initial
Value R/W Corresponding Module
7 MSTP15 0*1 R/W
6 MSTP14 0*1 R/W
5 MSTP13 1 R/W 16-bit free-running timer (FRT)
4 MSTP12 1 R/W 8-bit timers (TMR_0, TMR_1)
3 MSTP11 1 R/W 8-bit PWM timer (PWM)
2 MSTP10 1*2 R/W
1 MSTP9 1 R/W A/D converter
0 MSTP8 1 R/W 8-bit timers (TMR_X, TMR_Y)
Notes: 1. Do not set this bit to 1.
2. Do not clear this bit to 0.
MSTPCRL
Bit Bit Name
Initial
Value R/W Corresponding Module
7 MSTP7 1* R/W
6 MSTP6 1 R/W Serial communication interface_1 (SCI_1)
5 MSTP5 1* R/W
4 MSTP4 1 R/W I2C bus interface_0 (IIC_0)
3 MSTP3 1 R/W I2C bus interface_1 (IIC_1)
2 MSTP2 1 R/W Keyboard buffer controller, keyboard matrix interrupt
mask register (KMIMR), keyboard matrix interrupt mask
register A (KMIMRA), port 6 pull-up MOS control register
(KMPCR)
1 MSTP1 1 R/W 8-bit timers (TMR_A, TMR_B)
0 MSTP0 1 R/W Host interface (LPC), wake-up event interrupt mask
register B (WUEMRB)
Note: * Do not clear this bit to 0.
Rev. 1.00, 05/04, page 468 of 544
20.2 Mode Transitions and LSI States
Figure 20.1 shows the enabled mode transition diagram. The mode transition from program
execution state to program halt state is performed by the SLEEP instruction. The mode transition
from program halt state to program execution state is performed by an interrupt. The STBY input
causes a mode transition from any state to hardware standby mode. The RES input causes a mode
transition from a state other than hardware standby mode to the reset state. Table 20.2 shows the
LSI internal states in each operating mode.
Program halt state
Program execution state
SCK2 to
SCK0 are
0
SCK2 to
SCK0 are
not 0
SLEEP instruction
SSBY = 1, PSS = 1,
DTON = 1, LSON = 1
Clock switching
exception handling
SLEEP instruction
SSBY = 1, PSS = 1,
DTON = 1, LSON = 0
After the oscillation
stabilization time
(STS2 to STS0), clock
switching exception
handling
SLEEP instruction
SLEEP
instruction
External
interrupt *3
Any interrupt
SLEEP
instruction
SLEEP
instruction
SLEEP instruction
Interrupt *1
LSON bit = 0
Interrupt *2
Interrupt *1
LSON bit = 1
STBY pin = High
RES pin = Low
STBY pin = Low
SSBY = 0, LSON = 0
SSBY = 1,
PSS = 0, LSON = 0
SSBY = 0,
PSS = 1, LSON = 1
SSBY = 1,
PSS = 1, DTON = 0
RES pin = High
: Transition after exception processing : Power-down mode
Reset state
High-speed mode
(main clock)
Medium-speed
mode
(main clock)
Subactive mode
(subclock)
Subsleep mode
(subclock)
Hardware
standby mode
Software
standby mode
Sleep mode
(main clock)
Watch mode
(subclock)
Notes: 1.
2.
3.
NMI, IRQ0 to IRQ2, IRQ6, IRQ7, and WDT1 interrupts
NMI, IRQ0 to IRQ7, WDT0, WDT1, TMR0, and TMR1 interrupts
NMI, IRQ0 to IRQ2, IRQ6, and IRQ7 interrupts
When a transition is made between modes by means of an interrupt, the transition cannot be made
on interrupt source generation alone. Ensure that interrupt handling is performed after accepting the
interrupt request.
Always select high-speed mode before making a transition to watch mode or sub-active mode.
Figure 20.1 Mode Transition Diagram
Rev. 1.00, 05/04, page 469 of 544
Table 20.2 LSI Internal States in Each Operating Mode
Function
High-
Speed
Medium-
Speed Sleep
Module
Stop Watch
Sub-
Active
Sub-
Sleep
Software
Standby
Hardware
Standby
System clock pulse generator Functioning Functioning Functioning Functioning Halted Halted Halted Halted Halted
Subclock pulse generator Functioning Functioning Functioning Functioning Functioning Functioning Functioning Halted Halted
Instruction
execution
Halted Halted Halted Halted Halted CPU
Registers
Functioning Medium-speed
operation
Retained
Functioning
Retained
Subclock
operation
Retained Retained Undefined
NMI
IRQ0 to IRQ7
KIN0 to KIN15
External
interrupts
WUE0 to WUE7
Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Halted
WDT_1 Subclock
operation
WDT_0
Functioning
TMR_0, TMR_1
Subclock
operation
Subclock
operation
FRT
TMR_X, TMR_Y
TMR_A, TMR_B
IIC_0
IIC_1
LPC
Functioning/H
alted
(retained)
Halted
(retained)
Halted
(retained)
Halted
(retained)
Halted
(retained)
SCI_1
PWM
Keyboard buffer
controller
Functioning Functioning Functioning
Functioning/H
alted (reset)
Halted (reset) Halted (reset) Halted (reset) Halted (reset)
Halted
(reset)
A/D
RAM Functioning Functioning Retained Functioning Retained Retained Retained
Peripheral
modules
I/O
Functioning Functioning Retained Functioning Functioning Retained High
impedance
Note: * "Halted (retained)" means that internal register values are retained. The internal state is
"operation suspended."
"Halted (reset)" means that internal register values and internal states are initialized.
In module stop mode, only modules for which a stop setting has been made are halted
(reset or retained).
Rev. 1.00, 05/04, page 470 of 544
20.3 Medium-Speed Mode
The CPU makes a transition to medium-speed mode as soon as the current bus cycle ends
according to the setting of the SCK2 to SCK0 bits in SBYCR. In medium-speed mode, the CPU
operates on the operating clock (φ/2, φ/4, φ/8, φ/16, or φ/32). On-chip peripheral modules other
than the bus masters always operate on the system clock (φ).
In medium-speed mode, a bus access is executed in the specified number of states with respect to
the bus master operating clock. For example, if φ/4 is selected as the operating clock, on-chip
memory is accessed in 4 states, and internal I/O registers in 8 states.
By clearing all of bits SCK2 to SCK0 to 0, a transition is made to high-speed mode at the end of
the current bus cycle.
If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, and the LSON
bit in LPWRCR is cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by
an interrupt, medium-speed mode is restored. When the SLEEP instruction is executed with the
SSBY bit set to 1, the LSON bit cleared to 0, and the PSS bit in TCSR (WDT_1) cleared to 0,
operation shifts to software standby mode. When software standby mode is cleared by an external
interrupt, medium-speed mode is restored.
When the RES pin is set low and medium-speed mode is cancelled, operation shifts to the reset
state. The same applies in the case of a reset caused by overflow of the watchdog timer.
When the STBY pin is driven low, medium-speed mode is cancelled and a transition is made to
hardware standby mode.
Figure 20.2 shows an example of medium-speed mode timing.
φ,
Bus master clock
peripheral module clock
Internal address bus
Internal write signal
Medium-speed mode
SBYCRSBYCR
Figure 20.2 Medium-Speed Mode Timing
Rev. 1.00, 05/04, page 471 of 544
20.4 Sleep Mode
The CPU makes a transition to sleep mode if the SLEEP instruction is executed when the SSBY
bit in SBYCR is cleared to 0 and the LSON bit in LPWRCR is cleared to 0. In sleep mode, CPU
operation stops but the peripheral modules do not stop. The contents of the CPU's internal
registers are retained.
Sleep mode is exited by any interrupt, the RES pin, or the STBY pin.
When an interrupt occurs, sleep mode is exited and interrupt exception handling starts. Sleep mode
is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the CPU.
Setting the RES pin level low cancels sleep mode and selects the reset state. After the oscillation
stabilization time has passed, driving the RES pin high causes the CPU to start reset exception
handling.
When the STBY pin level is driven low, sleep mode is cancelled and a transition is made to
hardware standby mode.
20.5 Software Standby Mode
The CPU makes a transition to software standby mode when the SLEEP instruction is executed
while the SSBY bit in SBYCR is set to 1, the LSON bit in LPWRCR is cleared to 0, and the PSS
bit in TCSR (WDT_1) is cleared to 0.
In software standby mode, the CPU, on-chip peripheral modules, and clock pulse generator all
stop. However, the contents of the CPU's internal registers, on-chip RAM data, I/O ports, and the
states of on-chip peripheral modules other than the SCI and PWM, are retained as long as the
prescribed voltage is supplied.
Software standby mode is cleared by an external interrupt (NMI, IRQ0 to IRQ2, IRQ6, or IRQ7),
the RES pin input, or STBY pin input.
When an external interrupt request signal is input, system clock oscillation starts, and after the
elapse of the time set in bits STS2 to STS0 in SBYCR, software standby mode is cleared, and
interrupt exception handling is started. When clearing software standby mode with an IRQ0 to
IRQ2, IRQ6, or IRQ7 interrupt, set the corresponding enable bit to 1 and ensure that no interrupt
with a higher priority than interrupts IRQ0 to IRQ2, IRQ6, and IRQ7 is generated. Software
standby mode cannot be cleared if an interrupt enable bit corresponding to an IRQ0 to IRQ2,
IRQ6, or IRQ7 interrupt is cleared to 0 or if the interrupt has been masked on the CPU side.
Rev. 1.00, 05/04, page 472 of 544
When the RES pin is driven low, system clock oscillation is started. At the same time as system
clock oscillation starts, the system clock is supplied to the entire LSI. Note that the RES pin must
be held low until clock oscillation stabilizes. When the RES pin goes high after clock oscillation
stabilizes, the CPU begins reset exception handling.
When the STBY pin is driven low, software standby mode is cancelled and a transition is made to
hardware standby mode.
Figure 20.3 shows an example in which a transition is made to software standby mode at the
falling edge of the NMI pin, and software standby mode is cleared at the rising edge of the NMI
pin.
In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling
edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set
to 1, and a SLEEP instruction is executed, causing a transition to software standby mode.
Software standby mode is then cleared at the rising edge of the NMI pin.
Oscillator
φ
NMI
NMIEG
SSBY
NMI exception
handling
NMIEG = 1
SSBY = 1
SLEEP instruction
Software standby mode
(power-down mode) Oscillation
stabilization
time tOSC2
NMI exception
handling
Figure 20.3 Application Example in Software Standby Mode
Rev. 1.00, 05/04, page 473 of 544
20.6 Hardware Standby Mode
The CPU makes a transition to hardware standby mode from any mode when the STBY pin is
driven low.
In hardware standby mode, all functions enter the reset state. As long as the prescribed voltage is
supplied, on-chip RAM data is retained. The I/O ports are set to the high-impedance state.
In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before
driving the STBY pin low. Do not change the state of the mode pins (MD1 and MD0) while this
LSI is in hardware standby mode.
Hardware standby mode is cleared by the STBY pin input or the RES pin input.
When the STBY pin is driven high while the RES pin is low, clock oscillation is started. Ensure
that the RES pin is held low until system clock oscillation stabilizes. When the RES pin is
subsequently driven high after the clock oscillation stabilization time has passed, reset exception
handling starts.
Figure 20.4 shows an example of hardware standby mode timing.
Oscillator
RES
STBY
Oscillation
stabilization
time
Reset
exception
handling
Figure 20.4 Hardware Standby Mode Timing
Rev. 1.00, 05/04, page 474 of 544
20.7 Watch Mode
The CPU makes a transition to watch mode when the SLEEP instruction is executed in high-speed
mode or subactive mode with the SSBY bit in SBYCR set to 1, the DTON bit in LPWRCR
cleared to 0, and the PSS bit in TCSR (WDT_1) set to 1.
In watch mode, the CPU is stopped and peripheral modules other than WDT_1 are also stopped.
The contents of the CPU's internal registers, several on-chip peripheral module registers, and on-
chip RAM data are retained and the I/O ports retain their values before transition as long as the
prescribed voltage is supplied.
Watch mode is exited by an interrupt (WOVI1, NMI, IRQ0 to IRQ2, IRQ6, or IRQ7), RES pin
input, or STBY pin input.
When an interrupt occurs, watch mode is exited and a transition is made to high-speed mode or
medium-speed mode when the LSON bit in LPWRCR cleared to 0 or to subactive mode when the
LSON bit is set to 1. When a transition is made to high-speed mode, a stable clock is supplied to
the entire LSI and interrupt exception handling starts after the time set in the STS2 to STS0 bits in
SBYCR has elapsed. In the case of an IRQ0 to IRQ2, IRQ6, or IRQ7 interrupt, watch mode is not
exited if the corresponding enable bit has been cleared to 0. In the case of interrupts from the on-
chip peripheral modules, watch mode is not exited if the interrupt enable register has been set to
disable the reception of that interrupt, or the interrupt is masked by the CPU.
When the RES pin is driven low, system clock oscillation starts. Simultaneously with the start of
system clock oscillation, the system clock is supplied to the entire LSI. Note that the RES pin must
be held low until clock oscillation is stabilized. If the RES pin is driven high after the clock
oscillation stabilization time has passed, the CPU begins reset exception handling.
If the STBY pin is driven low, the LSI enters hardware standby mode.
Rev. 1.00, 05/04, page 475 of 544
20.8 Subsleep Mode
The CPU makes a transition to subsleep mode when the SLEEP instruction is executed in
subactive mode with the SSBY bit in SBYCR cleared to 0, the LSON bit in LPWRCR set to 1,
and the PSS bit in TCSR (WDT_1) set to 1.
In subsleep mode, the CPU is stopped. Peripheral modules other than TMR_0, TMR_1, WDT_0,
and WDT_1 are also stopped. The contents of the CPU's internal registers, several on-chip
peripheral module registers, and on-chip RAM data are retained and the I/O ports retain their
values before transition as long as the prescribed voltage is supplied.
Subsleep mode is exited by an interrupt (interrupts by on-chip peripheral modules, NMI, IRQ0 to
IRQ7), the RES pin input, or the STBY pin input.
When an interrupt occurs, subsleep mode is exited and interrupt exception handling starts.
In the case of an IRQ0 to IRQ7 interrupt, subsleep mode is not exited if the corresponding enable
bit has been cleared to 0. In the case of interrupts from the on-chip peripheral modules, subsleep
mode is not exited if the interrupt enable register has been set to disable the reception of that
interrupt, or the interrupt is masked by the CPU.
When the RES pin is driven low, system clock oscillation starts. Simultaneously with the start of
system clock oscillation, the system clock is supplied to the entire LSI. Note that the RES pin must
be held low until clock oscillation is stabilized. If the RES pin is driven high after the clock
oscillation stabilization time has passed, the CPU begins reset exception handling.
If the STBY pin is driven low, the LSI enters hardware standby mode.
Rev. 1.00, 05/04, page 476 of 544
20.9 Subactive Mode
The CPU makes a transition to subactive mode when the SLEEP instruction is executed in high-
speed mode with the SSBY bit in SBYCR set to 1, the DTON bit and LSON bit in LPWRCR set
to 1, and the PSS bit in TCSR (WDT_1) set to 1. When an interrupt occurs in watch mode, and if
the LSON bit in LPWRCR is 1, a direct transition is made to subactive mode. Similarly, if an
interrupt occurs in subsleep mode, a transition is made to subactive mode.
In subactive mode, the CPU operates at a low speed based on the subclock and sequentially
executes programs. Peripheral modules other than TMR_0, TMR_1, WDT_0, and WDT_1 are
also stopped.
When operating the CPU in subactive mode, the SCK2 to SCK0 bits in SBYCR must be cleared to
0.
Subactive mode is exited by the SLEEP instruction, RES pin input, or STBY pin input.
When the SLEEP instruction is executed with the SSBY bit in SBYCR set to 1, the DTON bit in
LPWRCR cleared to 0, and the PSS bit in TCSR (WDT_1) set to 1, the CPU exits subactive mode
and a transition is made to watch mode. When the SLEEP instruction is executed with the SSBY
bit in SBYCR cleared to 0, the LSON bit in LPWRCR set to 1, and the PSS bit in TCSR (WDT_1)
set to 1, a transition is made to subsleep mode. When the SLEEP instruction is executed with the
SSBY bit in SBYCR set to 1, the DTON bit and LSON bit in LPWRCR set to 10, and the PSS bit
in TCSR (WDT_1) set to 1, a direct transition is made to high-speed mode.
For details of direct transitions, see section 20.11, Direct Transitions.
When the RES pin is driven low, system clock oscillation starts. Simultaneously with the start of
system clock oscillation, the system clock is supplied to the entire LSI. Note that the RES pin must
be held low until the clock oscillation is stabilized. If the RES pin is driven high after the clock
oscillation stabilization time has passed, the CPU begins reset exception handling.
If the STBY pin is driven low, the LSI enters hardware standby mode.
Rev. 1.00, 05/04, page 477 of 544
20.10 Module Stop Mode
Module stop mode can be individually set for each on-chip peripheral module.
When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of
the bus cycle and a transition is made to module stop mode. In turn, when the corresponding
MSTP bit is cleared to 0, module stop mode is cancelled and the module operation resumes at the
end of the bus cycle. In module stop mode, the internal states of modules other than the SCI and
PWM are retained.
After the reset state is cancelled, all modules are in module stop mode.
While an on-chip peripheral module is in module stop mode, read/write access to its registers is
disabled.
20.11 Direct Transitions
The CPU executes programs in three modes: high-speed, medium-speed, and subactive. When a
direct transition is made from high-speed mode to subactive mode, there is no interruption of
program execution. A direct transition is enabled by setting the DTON bit in LPWRCR to 1 and
then executing the SLEEP instruction. After a transition, direct transition exception handling
starts.
The CPU makes a transition to subactive mode when the SLEEP instruction is executed in high-
speed mode with the SSBY bit in SBYCR set to 1, the LSON bit and DTON bit in LPWRCR set
to 11, and the PSS bit in TSCR (WDT_1) set to 1.
To make a direct transition to high-speed mode after the time set in the STS2 to STS0 bits in
SBYCR has elapsed, execute the SLEEP instruction in subactive mode with the SSBY bit in
SBYCR set to 1, the LSON bit and DTON bit in LPWRCR set to 01, and the PSS bit in TSCR
(WDT_1) set to 1.
Rev. 1.00, 05/04, page 478 of 544
20.12 Usage Notes
20.12.1 I/O Port Status
The status of the I/O ports is retained in software standby mode. Therefore, when a high level is
output, the current consumption is not reduced by the amount of current to support the high level
output.
20.12.2 Current Consumption when Waiting for Oscillation Stabilization
The current consumption increases during oscillation stabilization.
Rev. 1.00, 05/04, page 479 of 544
Section 21 List of Registers
The register list gives information on the on-chip I/O register addresses, how the register bits are
configured, and the register states in each operating mode. The information is given as shown
below.
1. Register Addresses (address order)
Registers are listed from the lower allocation addresses.
The MSB-side address is indicated for 16-bit addresses.
Registers are classified by functional modules.
The access size is indicated.
2. Register Bits
Bit configurations of the registers are described in the same order as the Register Addresses
(address order) above.
Reserved bits are indicated by in the bit name column.
The bit number in the bit-name column indicates that the whole register is allocated as a
counter or for holding data.
16-bit registers are indicated from the bit on the MSB side.
3. Register States in Each Operating Mode
Register states are described in the same order as the Register Addresses (address order)
above.
The register states described here are for the basic operating modes. If there is a specific reset
for an on-chip peripheral module, see the section on that on-chip peripheral module.
4. Register Select Conditions
Register states are described in the same order as the Register Addresses (address order)
above.
For details on the register select conditions, see section 3.2.2, System Control Register
(SYSCR), 3.2.3, Serial Timer Control Register (STCR), 20.1.3, Module Stop Control Registers
H, L (MSTPCRH, MSTPCRL), and the register descriptions for each module.
Rev. 1.00, 05/04, page 480 of 544
21.1 Register Addresses (Address Order)
The data bus width indicates the numbers of bits by which the register is accessed.
The number of access states indicates the number of states based on the specified reference clock.
Register Name Abbreviation Number
of Bits Address Module
Data
Bus
Width
Number
of
Access
States
Timer control register_B TCR_B 8 H'FE00 TMR_B 8 3
Timer control register_A TCR_A 8 H'FE01 TMR_A 8 3
Timer control/status register_B TCSR_B 8 H'FE02 TMR_B 8 3
Timer control/status register_A TCSR_A 8 H'FE03 TMR_A 8 3
Time constant register A_B TCORA_B 8 H'FE04 TMR_B 8 3
Time constant register A_A TCORA_A 8 H'FE05 TMR_A 8 3
Time constant register B_B TCORB_B 8 H'FE06 TMR_B 8 3
Time constant register B_A TCORB_A 8 H'FE07 TMR_A 8 3
Timer counter_B TCNT_B 8 H'FE08 TMR_B 8 3
Timer counter_A TCNT_A 8 H'FE09 TMR_A 8 3
Timer input select register_B TISR_B 8 H'FE0A TMR_B 8 3
Input capture register R_A TICRR_A 8 H'FE0C TMR_A 8 3
Input capture register F_A TICRF_A 8 H'FE0D TMR_A 8 3
Timer AB control register TCRAB 8 H'FE0E TMR_A,
TMR_B
8 3
Timer XY control register* TCRXY 8 H'FE10 TMR_X,
TMR_Y
8 3
Serial pin select register* SPSR 8 H'FE12 SCI_1 8 3
Port G control register* PGCTL 8 H'FE14 IIC common 8 3
Port G open drain control register PGNOCR 8 H'FE16 PORT 8 3
Port E open drain control register PENOCR 8 H'FE18 PORT 8 3
Port F open drain control register PFNOCR 8 H'FE19 PORT 8 3
Port C open drain control register PCNOCR 8 H'FE1C PORT 8 3
Port D open drain control register PDNOCR 8 H'FE1D PORT 8 3
Bidirectional data register 0MW TWR0MW 8 H'FE20 LPC 8 3
Bidirectional data register 0SW TWR0SW 8 H'FE20 LPC 8 3
Rev. 1.00, 05/04, page 481 of 544
Register Name Abbreviation Number
of Bits Address Module
Data
Bus
Width
Number
of
Access
States
Bidirectional data register 1 TWR1 8 H'FE21 LPC 8 3
Bidirectional data register 2 TWR2 8 H'FE22 LPC 8 3
Bidirectional data register 3 TWR3 8 H'FE23 LPC 8 3
Bidirectional data register 4 TWR4 8 H'FE24 LPC 8 3
Bidirectional data register 5 TWR5 8 H'FE25 LPC 8 3
Bidirectional data register 6 TWR6 8 H'FE26 LPC 8 3
Bidirectional data register 7 TWR7 8 H'FE27 LPC 8 3
Bidirectional data register 8 TWR8 8 H'FE28 LPC 8 3
Bidirectional data register 9 TWR9 8 H'FE29 LPC 8 3
Bidirectional data register 10 TWR10 8 H'FE2A LPC 8 3
Bidirectional data register 11 TWR11 8 H'FE2B LPC 8 3
Bidirectional data register 12 TWR12 8 H'FE2C LPC 8 3
Bidirectional data register 13 TWR13 8 H'FE2D LPC 8 3
Bidirectional data register 14 TWR14 8 H'FE2E LPC 8 3
Bidirectional data register 15 TWR15 8 H'FE2F LPC 8 3
Input data register 3 IDR3 8 H'FE30 LPC 8 3
Output data register 3 ODR3 8 H'FE31 LPC 8 3
Status register 3 STR3 8 H'FE32 LPC 8 3
LPC channel address register H LADR3H 8 H'FE34 LPC 8 3
LPC channel address register L LADR3L 8 H'FE35 LPC 8 3
SERIRQ control register 0 SIRQCR0 8 H'FE36 LPC 8 3
SERIRQ control register 1 SIRQCR1 8 H'FE37 LPC 8 3
Input data register 1 IDR1 8 H'FE38 LPC 8 3
Output data register 1 ODR1 8 H'FE39 LPC 8 3
Status register 1 STR1 8 H'FE3A LPC 8 3
Input data register 2 IDR2 8 H'FE3C LPC 8 3
Output data register 2 ODR2 8 H'FE3D LPC 8 3
Status register 2 STR2 8 H'FE3E LPC 8 3
Host interface select register HISEL 8 H'FE3F LPC 8 3
Host interface control register 0 HICR0 8 H'FE40 LPC 8 3
Host interface control register 1 HICR1 8 H'FE41 LPC 8 3
Host interface control register 2 HICR2 8 H'FE42 LPC 8 3
Host interface control register 3 HICR3 8 H'FE43 LPC 8 3
Rev. 1.00, 05/04, page 482 of 544
Register Name Abbreviation Number
of Bits Address Module
Data
Bus
Width
Number
of
Access
States
Wakeup event interrupt mask register
B
WUEMRB 8 H'FE44 INT 8 3
Port G output data register PGODR 8 H'FE46 PORT 8 3
Port G input data register PGPIN 8 H'FE47
(read)
PORT 8 3
Port G data direction register PGDDR 8 H'FE47
(write)
PORT 8 3
Port E output data register PEODR 8 H'FE48 PORT 8 3
Port F output data register PFODR 8 H'FE49 PORT 8 3
Port E input data register PEPIN 8 H'FE4A
(read)
PORT 8 3
Port E data direction register PEDDR 8 H'FE4A
(write)
PORT 8 3
Port F input data register PFPIN 8 H'FE4B
(read)
PORT 8 3
Port F data direction register PFDDR 8 H'FE4B
(write)
PORT 8 3
Port C output data register PCODR 8 H'FE4C PORT 8 3
Port D output data register PDODR 8 H'FE4D PORT 8 3
Port C input data register PCPIN 8 H'FE4E
(read)
PORT 8 3
Port C data direction register PCDDR 8 H'FE4E
(write)
PORT 8 3
Port D input data register PDPIN 8 H'FE4F
(read)
PORT 8 3
Port D data direction register PDDDR 8 H'FE4F
(write)
PORT 8 3
I2C bus extended control register_0 ICXR_0 8 H'FED4 IIC_0 8 2
I2C bus extended control register_1 ICXR_1 8 H'FED5 IIC_1 8 2
Keyboard control register H_0 KBCRH_0 8 H'FED8 Keyboard
buffer
controller_0
8 2
Keyboard control register L_0 KBCRL_0 8 H'FED9 Keyboard
buffer
controller_0
8 2
Keyboard data buffer register_0 KBBR_0 8 H'FEDA Keyboard
buffer
controller_0
8 2
Rev. 1.00, 05/04, page 483 of 544
Register Name Abbreviation Number
of Bits Address Module
Data
Bus
Width
Number
of
Access
States
Keyboard control register H_1 KBCRH_1 8 H'FEDC Keyboard
buffer
controller_1
8 2
Keyboard control register L_1 KBCRL_1 8 H'FEDD Keyboard
buffer
controller_1
8 2
Keyboard data buffer register_1 KBBR_1 8 H'FEDE Keyboard
buffer
controller_1
8 2
Keyboard control register H_2 KBCRH_2 8 H'FEE0 Keyboard
buffer
controller_2
8 2
Keyboard control register L_2 KBCRL_2 8 H'FEE1 Keyboard
buffer
controller_2
8 2
Keyboard data buffer register_2 KBBR_2 8 H'FEE2 Keyboard
buffer
controller_2
8 2
DDC switch register DDCSWR 8 H'FEE6 IIC common 8 2
Interrupt control register A ICRA 8 H'FEE8 INT 8 2
Interrupt control register B ICRB 8 H'FEE9 INT 8 2
Interrupt control register C ICRC 8 H'FEEA INT 8 2
IRQ status register ISR 8 H'FEEB INT 8 2
IRQ sense control register H ISCRH 8 H'FEEC INT 8 2
IRQ sense control register L ISCRL 8 H'FEED INT 8 2
Address break control register ABRKCR 8 H'FEF4 INT 8 2
Break address register A BARA 8 H'FEF5 INT 8 2
Break address register B BARB 8 H'FEF6 INT 8 2
Break address register C BARC 8 H'FEF7 INT 8 2
Flash memory control register 1 FLMCR1 8 H'FF80 FLASH 8 2
Flash memory control register 2 FLMCR2 8 H'FF81 FLASH 8 2
Peripheral clock select register PCSR 8 H'FF82 PWM 8 2
Erase block register 1 EBR1 8 H'FF82 FLASH 8 2
System control register 2 SYSCR2 8 H'FF83 SYSTEM 8 2
Erase block register 2 EBR2 8 H'FF83 FLASH 8 2
Standby control register SBYCR 8 H'FF84 SYSTEM 8 2
Rev. 1.00, 05/04, page 484 of 544
Register Name Abbreviation Number
of Bits Address Module
Data
Bus
Width
Number
of
Access
States
Low power control register LPWRCR 8 H'FF85 SYSTEM 8 2
Module stop control register H MSTPCRH 8 H'FF86 SYSTEM 8 2
Module stop control register L MSTPCRL 8 H'FF87 SYSTEM 8 2
Serial mode register_1 SMR_1 8 H'FF88 SCI_1 8 2
I2C bus control register_1 ICCR_1 8 H'FF88 IIC_1 8 2
Bit rate register_1 BRR_1 8 H'FF89 SCI_1 8 2
I2C bus status register_1 ICSR_1 8 H'FF89 IIC_1 8 2
Serial control register_1 SCR_1 8 H'FF8A SCI_1 8 2
Transmit data register_1 TDR_1 8 H'FF8B SCI_1 8 2
Serial status register_1 SSR_1 8 H'FF8C SCI_1 8 2
Receive data register_1 RDR_1 8 H'FF8D SCI_1 8 2
Smart card mode register_1 SCMR_1 8 H'FF8E SCI_1 8 2
I2C bus data register_1 ICDR_1 8 H'FF8E IIC_1 8 2
Second slave address register_1 SARX_1 8 H'FF8E IIC_1 8 2
I2C bus mode register_1 ICMR_1 8 H'FF8F IIC_1 8 2
Slave address register_1 SAR_1 8 H'FF8F IIC_1 8 2
Timer interrupt enable register TIER 8 H'FF90 FRT 8 2
Timer control/status register TCSR 8 H'FF91 FRT 8 2
Free running counter H FRCH 8 H'FF92 FRT 8 2
Free running counter L FRCL 8 H'FF93 FRT 8 2
Output control register AH OCRAH 8 H'FF94 FRT 8 2
Output control register BH OCRBH 8 H'FF94 FRT 8 2
Output control register AL OCRAL 8 H'FF95 FRT 8 2
Output control register BL OCRBL 8 H'FF95 FRT 8 2
Timer control register TCR 8 H'FF96 FRT 8 2
Timer output compare control register TOCR 8 H'FF97 FRT 8 2
Input capture register AH ICRAH 8 H'FF98 FRT 8 2
Output control register ARH OCRARH 8 H'FF98 FRT 8 2
Input capture register AL ICRAL 8 H'FF99 FRT 8 2
Output control register ARL OCRARL 8 H'FF99 FRT 8 2
Input capture register BH ICRBH 8 H'FF9A FRT 8 2
Output control register AFH OCRAFH 8 H'FF9A FRT 8 2
Input capture register BL ICRBL 8 H'FF9B FRT 8 2
Rev. 1.00, 05/04, page 485 of 544
Register Name Abbreviation Number
of Bits Address Module
Data
Bus
Width
Number
of
Access
States
Output control register AFL OCRAFL 8 H'FF9B FRT 8 2
Input capture register CH ICRCH 8 H'FF9C FRT 8 2
Output compare register DMH OCRDMH 8 H'FF9C FRT 8 2
Input capture register CL ICRCL 8 H'FF9D FRT 8 2
Output compare register DML OCRDML 8 H'FF9D FRT 8 2
Input capture register DH ICRDH 8 H'FF9E FRT 8 2
Input capture register DL ICRDL 8 H'FF9F FRT 8 2
Timer control/status register_0 TCSR_0 8 H'FFA8 WDT_0 8 2
Timer counter_0 TCNT_0 8 H'FFA8
(write)
WDT_0 8 2
Timer counter_0 TCNT_0 8 H'FFA9
(read)
WDT_0 8 2
Port A output data register PAODR 8 H'FFAA PORT 8 2
Port A input data register PAPIN 8 H'FFAB PORT 8 2
Port A data direction register PADDR 8 H'FFAB PORT 8 2
Port 1 pull-up MOS control register P1PCR 8 H'FFAC PORT 8 2
Port 2 pull-up MOS control register P2PCR 8 H'FFAD PORT 8 2
Port 3 pull-up MOS control register P3PCR 8 H'FFAE PORT 8 2
Port 1 data direction register P1DDR 8 H'FFB0 PORT 8 2
Port 2 data direction register P2DDR 8 H'FFB1 PORT 8 2
Port 1 data register P1DR 8 H'FFB2 PORT 8 2
Port 2 data register P2DR 8 H'FFB3 PORT 8 2
Port 3 data direction register P3DDR 8 H'FFB4 PORT 8 2
Port 4 data direction register P4DDR 8 H'FFB5 PORT 8 2
Port 3 data register P3DR 8 H'FFB6 PORT 8 2
Port 4 data register P4DR 8 H'FFB7 PORT 8 2
Port 5 data direction register P5DDR 8 H'FFB8 PORT 8 2
Port 6 data direction register P6DDR 8 H'FFB9 PORT 8 2
Port 5 data register P5DR 8 H'FFBA PORT 8 2
Port 6 data register P6DR 8 H'FFBB PORT 8 2
Port B output data register PBODR 8 H'FFBC PORT 8 2
Port B input data register PBPIN 8 H'FFBD
(read)
PORT 8 2
Rev. 1.00, 05/04, page 486 of 544
Register Name Abbreviation Number
of Bits Address Module
Data
Bus
Width
Number
of
Access
States
Port 8 data direction register P8DDR 8 H'FFBD
(write)
PORT 8 2
Port 7 input data register P7PIN 8 H'FFBE
(read)
PORT 8 2
Port B data direction register PBDDR 8 H'FFBE
(write)
PORT 8 2
Port 8 data register P8DR 8 H'FFBF PORT 8 2
Port 9 data direction register P9DDR 8 H'FFC0 PORT 8 2
Port 9 data register P9DR 8 H'FFC1 PORT 8 2
Interrupt enable register IER 8 H'FFC2 INT 8 2
Serial timer control register STCR 8 H'FFC3 SYSTEM 8 2
System control register SYSCR 8 H'FFC4 SYSTEM 8 2
Mode control register MDCR 8 H'FFC5 SYSTEM 8 2
Bus control register BCR 8 H'FFC6 BSC 8 2
Wait state control register WSCR 8 H'FFC7 BSC 8 2
Timer control register_0 TCR_0 8 H'FFC8 TMR_0 8 2
Timer control register_1 TCR_1 8 H'FFC9 TMR_1 8 2
Timer control/status register_0 TCSR_0 8 H'FFCA TMR_0 8 2
Timer control/status register_1 TCSR_1 8 H'FFCB TMR_1 16 2
Time constant register A_0 TCORA_0 8 H'FFCC TMR_0 16 2
Time constant register A_1 TCORA_1 8 H'FFCD TMR_1 16 2
Time constant register B_0 TCORB_0 8 H'FFCE TMR_0 16 2
Time constant register B_1 TCORB_1 8 H'FFCF TMR_1 16 2
Timer counter_0 TCNT_0 8 H'FFD0 TMR_0 16 2
Timer counter_1 TCNT_1 8 H'FFD1 TMR_1 16 2
PWM output enable register A PWOERA 8 H'FFD3 PWM 8 2
PWM data polarity register A PWDPRA 8 H'FFD5 PWM 8 2
PWM register select PWSL 8 H'FFD6 PWM 8 2
PWM data registers 0 to 7 PWDR0 to
PWDR7
8 H'FFD7 PWM 8 2
I2C bus control register_0 ICCR_0 8 H'FFD8 IIC_0 8 2
I2C bus status register_0 ICSR_0 8 H'FFD9 IIC_0 8 2
I2C bus data register_0 ICDR_0 8 H'FFDE IIC_0 8 2
Second slave address register_0 SARX_0 8 H'FFDE IIC_0 8 2
Rev. 1.00, 05/04, page 487 of 544
Register Name Abbreviation Number
of Bits Address Module
Data
Bus
Width
Number
of
Access
States
I2C bus mode register_0 ICMR_0 8 H'FFDF IIC_0 8 2
Slave address register_0 SAR_0 8 H'FFDF IIC_0 8 2
A/D data register AH ADDRAH 8 H'FFE0 A/D
converter
8 2
A/D data register AL ADDRAL 8 H'FFE1 A/D
converter
8 2
A/D data register BH ADDRBH 8 H'FFE2 A/D
converter
8 2
A/D data register BL ADDRBL 8 H'FFE3 A/D
converter
8 2
A/D data register CH ADDRCH 8 H'FFE4 A/D
converter
8 2
A/D data register CL ADDRCL 8 H'FFE5 A/D
converter
8 2
A/D data register DH ADDRDH 8 H'FFE6 A/D
converter
8 2
A/D data register DL ADDRDL 8 H'FFE7 A/D
converter
8 2
A/D control/status register ADCSR 8 H'FFE8 A/D
converter
8 2
A/D control register ADCR 8 H'FFE9 A/D
converter
8 2
Timer control/status register_1 TCSR_1 8 H'FFEA WDT_1 8 2
Timer counter_1 TCNT_1 8 H'FFEA
(write)
WDT_1 8 2
Timer counter_1 TCNT_1 8 H'FFEB
(read)
WDT_1 8 2
Timer control register_X TCR_X 8 H'FFF0 TMR_X 16 2
Timer control register_Y TCR_Y 8 H'FFF0 TMR_Y 16 2
Keyboard matrix interrupt register 6 KMIMR 8 H'FFF1 INT 8 2
Timer control/status register_X TCSR_X 8 H'FFF1 TMR_X 16 2
Timer control/status register_Y TCSR_Y 8 H'FFF1 TMR_Y 16 2
Pull-up MOS control register KMPCR 8 H'FFF2 PORT 8 2
Input capture register R TICRR 8 H'FFF2 TMR_X 16 2
Time constant register A_Y TCORA_Y 8 H'FFF2 TMR_Y 16 2
Keyboard matrix interrupt register A KMIMRA 8 H'FFF3 INT 8 2
Rev. 1.00, 05/04, page 488 of 544
Register Name Abbreviation Number
of Bits Address Module
Data
Bus
Width
Number
of
Access
States
Input capture register F TICRF 8 H'FFF3 TMR_X 16 2
Time constant register B_Y TCORB_Y 8 H'FFF3 TMR_Y 16 2
Timer counter_X TCNT_X 8 H'FFF4 TMR_X 16 2
Timer counter_Y TCNT_Y 8 H'FFF4 TMR_Y 16 2
Timer constant register C TCORC 8 H'FFF5 TMR_X 16 2
Timer input select register TISR 8 H'FFF5 TMR_Y 16 2
Timer constant register A_X TCORA_X 8 H'FFF6 TMR_X 16 2
Timer constant register B_X TCORB_X 8 H'FFF7 TMR_X 16 2
Timer connection register I TCONRI 8 H'FFFC TMR_X 8 2
Timer connection register S TCONRS 8 H'FFFE TMR_Y 8 2
Note: * The program development tool (emulator) does not support these registers.
Rev. 1.00, 05/04, page 489 of 544
21.2 Register Bits
Register addresses and bit names of the on-chip peripheral modules are described below.
Each line covers 8 bits, and 16-bit registers are shown as 2 lines.
Register
Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
TCR_B CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0
TCR_A CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0
TCSR_B CMFB CMFA OVF ICIE OS3 OS2 OS1 OS0
TCSR_A CMFB CMFA OVF ICF OS3 OS2 OS1 OS0
TCORA_B Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TCORA_A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TCORB_B Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TCORB_A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TCNT_B Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TCNT_A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TISR_B IS
TICRR_A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TICRF_A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TCRAB CKSA CKSB ICST
TMR_A
TMR_B
TCRXY*1 IOSX IOSY CKSX CKSY TMR_X
TMR_Y
SPSR*1 SPS1 SCI_1
PGCTL*1 IIC1BS IIC1AS IC0BS IIC0AS IIC
common
PGNOCR PG7NOCR PG6NOCR PG5NOCR PG4NOCR PG3NOCR PG2NOCR PG1NOCR PG0NOCR
PENOCR PE7NOCR PE6NOCR PE5NOCR PE4NOCR PE3NOCR PE2NOCR PE1NOCR PE0NOCR
PFNOCR PF7NOCR PF6NOCR PF5NOCR PF4NOCR PF3NOCR PF2NOCR PF1NOCR PF0NOCR
PCNOCR PC7NOCR PC6NOCR PC5NOCR PC4NOCR PC3NOCR PC2NOCR PC1NOCR PC0NOCR
PDNOCR PD7NOCR PD6NOCR PD5NOCR PD4NOCR PD3NOCR PD2NOCR PD1NOCR PD0NOCR
PORT
TWR0MW Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LPC
TWR0SW Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Rev. 1.00, 05/04, page 490 of 544
Register
Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
TWR1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TWR2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TWR3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TWR4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TWR5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TWR6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TWR7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TWR8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TWR9 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TWR10 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TWR11 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TWR12 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TWR13 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TWR14 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TWR15 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IDR3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ODR3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
STR3*2 IBF3B OBF3B MWMF SWMF C/D3 DBU32 IBF3A OBF3A
STR3*3 DBU37 DBU36 DBU35 DBU34 C/D3 DBU32 IBF3A OBF3A
LADR3H Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
SIRQCR0 Q/C SELREQ IEDIR SMIE3B SMIE3A SMIE2 IRQ12E1 IRQ1E1
SIRQCR1 IRQ11E3 IRQ10E3 IRQ9E3 IRQ6E3 IRQ11E2 IRQ10E2 IRQ9E2 IRQ6E2
IDR1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
LPC
ODR1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
STR1 DBU17 DBU16 DBU15 DBU14 C/D1 DBU12 IBF1 OBF1
IDR2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ODR2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
STR2 DBU27 DBU26 DBU25 DBU24 C/D2 DBU22 IBF2 OBF2
HISEL SELSTR3 SELIRQ11 SELIRQ10 SELIRQ9 SELIRQ6 SELSMI SELIRQ12 SELIRQ1
HICR0 LPC3E LPC2E LPC1E FGA20E SDWNE PMEE LSMIE LSCIE
HICR1 LPCBSY CLKREQ IRQBSY LRSTB SDWNB PMEB LSMIB LSCIB
HICR2 GA20 LRST SDWN ABRT BFIE3 IBFIE2 IBFIE1 ERRIE
HICR3 LFRAME CLKRUN SERIRQ LRESET LPCPD PME LSMI LSCI
Rev. 1.00, 05/04, page 491 of 544
Register
Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
WUEMRB WUEMR7 WUEMR6 WUEMR5 WUEMR4 WUEMR3 WUEMR2 WUEMR1 WUEMR0 INT
PGODR PG7ODR PG6ODR PG5ODR PG4ODR PG3ODR PG2ODR PG1ODR PG0ODR
PGPIN PG7PIN PG6PIN PG5PIN PG4PIN PG3PIN PG2PIN PG1PIN PG0PIN
PGDDR PG7DDR PG6DDR PG5DDR PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR
PEODR PE7ODR PE6ODR PE5ODR PE4ODR PE3ODR PE2ODR PE1ODR PE0ODR
PFODR PF7ODR PF6ODR PF5ODR PF4ODR PF3ODR PF2ODR PF1ODR PF0ODR
PEPIN PE7PIN PE6PIN PE5PIN PE4PIN PE3PIN PE2PIN PE1PIN PE0PIN
PEDDR PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR
PFPIN PF7PIN PF6PIN PF5PIN PF4PIN PF3PIN PF2PIN PF1PIN PF0PIN
PFDDR PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR
PCODR PC7ODR PC6ODR PC5ODR PC4ODR PC3ODR PC2ODR PC1ODR PC0ODR
PDODR PD7ODR PD6ODR PD5ODR PD4ODR PD3ODR PD2ODR PD1ODR PD0ODR
PCPIN PC7PIN PC6PIN PC5PIN PC4PIN PC3PIN PC2PIN PC1PIN PC0PIN
PCDDR PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR
PDPIN PD7PIN PD6PIN PD5PIN PD4PIN PD3PIN PD2PIN PD1PIN PD0PIN
PDDDR PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR
PORT
ICXR_0 STOPIM HNDS ICDRF ICDRE ALIE ALSL FNC1 FNC0 IIC_0
ICXR_1 STOPIM HNDS ICDRF ICDRE ALIE ALSL FNC1 FNC0 IIC_1
KBCRH_0 KBIOE KCLKI KDI KBFSEL KBIE KBF PER KBS
KBCRL_0 KBE KCLKO KDO RXCR3 RXCR2 RXCR1 RXCR0
KBBR_0 KB7 KB6 KB5 KB4 KB3 KB2 KB1 KB0
Keyboard
buffer
controller
_0
KBCRH_1 KBIOE KCLKI KDI KBFSEL KBIE KBF PER KBS
KBCRL_1 KBE KCLKO KDO RXCR3 RXCR2 RXCR1 RXCR0
KBBR_1 KB7 KB6 KB5 KB4 KB3 KB2 KB1 KB0
Keyboard
buffer
controller
_1
KBCRH_2 KBIOE KCLKI KDI KBFSEL KBIE KBF PER KBS
KBCRL_2 KBE KCLKO KDO RXCR3 RXCR2 RXCR1 RXCR0
KBBR_2 KB7 KB6 KB5 KB4 KB3 KB2 KB1 KB0
Keyboard
buffer
controller
_2
DDCSWR — — — — CLR3 CLR2 CLR1 CLR0 IIC
common
Rev. 1.00, 05/04, page 492 of 544
Register
Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
ICRA ICRA7 ICRA6 ICRA5 ICRA4 ICRA3 ICRA2 ICRA1 ICRA0
ICRB ICRB7 ICRB6 ICRB5 ICRB4 ICRB3 ICRB2 ICRB1 ICRB0
ICRC ICRC7 ICRC6 ICRC5 ICRC4 ICRC3 ICRC2 ICRC1 ICRC0
ISR IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F
ISCRH IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA
ISCRL IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA
INT
ABRKCR CMF — — — — — — BIE
BARA A23 A22 A21 A20 A19 A18 A17 A16
BARB A15 A14 A13 A12 A11 A10 A9 A8
BARC A7 A6 A5 A4 A3 A2 A1 —
FLMCR1 FWE SWE — — EV PV E P
FLMCR2 FLER — — — — — ESU PSU
FLASH
PCSR — — — — PWCKC PWCKB PWCKA — PWM
EBR1 — — — — — — — — FLASH
SYSCR2 — — — — — — — — SYSTEM
EBR2 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 FLASH
SBYCR SSBY STS2 STS1 STS0 SCK2 SCK1 SCK0
LPWRCR DTON LSON NESEL EXCLE — — — —
MSTPCRH MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8
MSTPCRL MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
SYSTEM
SMR_1 C/A CHR PE O/E STOP MP CKS1 CKS0 SCI_1
ICCR_1 ICE IEIC MST TRS ACKE BBSY IRIC SCP IIC_1
BRR_1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCI_1
ICSR_1 ESTP STOP IRTR AASX AL AAS ADZ ACKB IIC_1
SCR_1 TIE RIE TE RE MPIE TEIE CKE1 CKE0
TDR_1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SSR_1 TDRE RDRF ORER FER PER TEND MPB MPBT
RDR_1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SCMR_1 — — — — SDIR SINV — SMIF
SCI_1
ICDR_1 ICDR7 ICDR6 ICDR5 ICDR4 ICDR3 ICDR2 ICDR1 ICDR0
SARX_1 SVAX6 SVAX5 SVAX4 SVAX3 SVAX2 SVAX1 SVAX0 FSX
ICMR_1 MLS WAIT CKS2 CKS1 CKS0 BC2 BC1 BC0
SAR_1 SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 FS
IIC_1
Rev. 1.00, 05/04, page 493 of 544
Register
Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
TIER ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE
TCSR ICFA ICFB ICFC ICFD OCFA OCFB OVF CCLRA
FRCH Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
FRCL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
OCRAH Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
OCRBH Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
OCRAL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
OCRBL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TCR IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB CKS1 CKS0
FRT
TOCR ICRDMS OCRAMS ICRS OCRS OEA OEB OLVLA OLVLB
ICRAH Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
OCRARH Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
ICRAL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
OCRARL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ICRBH Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
OCRAFH Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
ICRBL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
OCRAFL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ICRCH Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
OCRDMH Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
ICRCL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
OCRDML Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ICRDH Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
ICRDL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TCSR_0 OVF WT/IT TME RST/NMI CKS2 CKS1 CKS0
TCNT_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
WDT_0
Rev. 1.00, 05/04, page 494 of 544
Register
Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
PAODR PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR
PAPIN PA7PIN PA6PIN PA5PIN PA4PIN PA3PIN PA2PIN PA1PIN PA0PIN
PORT
PADDR PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR
P1PCR P17PCR P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR
P2PCR P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR
P3PCR P37PCR P36PCR P35PCR P34PCR P33PCR P32PCR P31PCR P30PCR
P1DDR P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR
P2DDR P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR
P1DR P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR
P2DR P27DR P26DR P25DR P24DR P23DR P22DR P21DR P20DR
P3DDR P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR
P4DDR P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR
P3DR P37DR P36DR P35DR P34DR P33DR P32DR P31DR P30DR
P4DR P47DR P46DR P45DR P44DR P43DR P42DR P41DR P40DR
P5DDR — — — — — P52DDR P51DDR P50DDR
P6DDR P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR
P5DR — — — — — P52DR P51DR P50DR
P6DR P67DR P66DR P65DR P64DR P63DR P62DR P61DR P60DR
PBODR PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR
PBPIN PB7PIN PB6PIN PB5PIN PB4PIN PB3PIN PB2PIN PB1PIN PB0PIN
P8DDR P86DDR P85DDR P84DDR P83DDR P82DDR P81DDR P80DDR
P7PIN P77PIN P76PIN P75PIN P74PIN P73PIN P72PIN P71PIN P70PIN
PBDDR PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR
P8DR — P86DR P85DR P84DR P83DR P82DR P81DR P80DR
P9DDR P97DDR P96DDR P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR
P9DR P97DR P96DR P95DR P94DR P93DR P92DR P91DR P90DR
IER IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E INT
STCR IICS IICX1 IICX0 IICE FLSHE ICKS1 ICKS0
SYSCR INTM1 INTM0 XRST NMIEG HIE RAME
MDCR EXPE — — — — — MDS1 MDS0
SYSTEM
BCR — ICIS0 BRSTRM BRSTS1 BRSTS0 — IOS1 IOS0
WSCR ABW AST WMS1 WMS0 WC1 WC0
BSC
Rev. 1.00, 05/04, page 495 of 544
Register
Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
TCR_0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0
TCR_1 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0
TCSR_0 CMFB CMFA OVF ADTE OS3 OS2 OS1 OS0
TMR_0,
TMR_1
TCSR_1 CMFB CMFA OVF OS3 OS2 OS1 OS0
TCORA_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TCORA_1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TCORB_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TCORB_1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TCNT_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TCNT_1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWOERA OE7 OE6 OE5 OE4 OE3 OE2 OE1 OE0
PWDPRA OS7 OS6 OS5 OS4 OS3 OS2 OS1 OS0
PWSL PWCKE PWCKS RS3 RS2 RS1 RS0
PWDR0 to
PWDR7
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWM
ICCR_0 ICE IEIC MST TRS ACKE BBSY IRIC SCP
ICSR_0 ESTP STOP IRTR AASX AL AAS ADZ ACKB
ICDR_0 ICDR7 ICDR6 ICDR5 ICDR4 ICDR3 ICDR2 ICDR1 ICDR0
SARX_0 SVAX6 SVAX5 SVAX4 SVAX3 SVAX2 SVAX1 SVAX0 FSX
ICMR_0 MLS WAIT CKS2 CKS1 CKS0 BC2 BC1 BC0
SAR_0 SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 FS
IIC_0
ADDRAH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
ADDRAL AD1 AD0 — — — — — —
ADDRBH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
ADDRBL AD1 AD0 — — — — — —
ADDRCH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
ADDRCL AD1 AD0 — — — — — —
ADDRDH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
A/D
converter
ADDRDL AD1 AD0 — — — — — —
ADCSR ADF ADIE ADST SCAN CKS CH2 CH1 CH0
ADCR TRGS1 TRGS0 — — — — — —
TCSR_1 OVF WT/IT TME PSS RST/NMI CKS2 CKS1 CKS0
TCNT_1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
WDT_1
Rev. 1.00, 05/04, page 496 of 544
Register
Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
TCR_X CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TMR_X
TCR_Y CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TMR_Y
KMIMR KMIMR7 KMIMR6 KMIMR5 KMIMR4 KMIMR3 KMIMR2 KMIMR1 KMIMR0 INT
TCSR_X CMFB CMFA OVF ICF OS3 OS2 OS1 OS0 TMR_X
TCSR_Y CMFB CMFA OVF ICIE OS3 OS2 OS1 OS0 TMR_Y
KMPCR KM7PCR KM6PCR KM5PCR KM4PCR KM3PCR KM2PCR KM1PCR KM0PCR PORT
TICRR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TMR_X
TCORA_Y Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TMR_Y
KMIMRA KMIMR15 KMIMR14 KMIMR13 KMIMR12 KMIMR11 KMIMR10 KMIMR9 KMIMR8 INT
TICRF Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TMR_X
TCORB_Y Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TMR_Y
TCNT_X Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TMR_X
TCNT_Y Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TMR_Y
TCORC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TMR_X
TISR — — — — — — — IS TMR_Y
TCORA_X Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TCORB_X Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TCONRI — — — ICST — — — —
TMR_X
TCONRS TMRX/Y — — — — — — — TMR_Y
Notes: 1. The program development tool (emulator) does not support these registers.
2. When TWRE = 1 or SELSTR3 = 0 in LADR3L
3. When TWRE = 0 and SELSTR3 = 1 in LADR3L
Rev. 1.00, 05/04, page 497 of 544
21.3 Register States in Each Operating Mode
Register
Abbrevia-
tion Reset
High-Speed/
Medium-
Speed Watch Sleep
Sub-
Active Sub-Sleep
Module
Stop
Software
Standby
Hardware
Standby Module
TCR_B Initialized Initialized
TCR_A Initialized Initialized
TCSR_B Initialized Initialized
TCSR_A Initialized Initialized
TCORA_B Initialized Initialized
TCORA_A Initialized Initialized
TCORB_B Initialized Initialized
TCORB_A Initialized Initialized
TCNT_B Initialized Initialized
TCNT_A Initialized Initialized
TISR_B Initialized Initialized
TICRR_A Initialized Initialized
TICRF_A Initialized Initialized
TCRAB Initialized Initialized
TMR_A
TMR_B
TCRXY* Initialized Initialized TMR_X,
TMR_Y
SPSR* Initialized Initialized SCI_1
PGCTL* Initialized Initialized IIC common
PGNOCR Initialized — — — — — — Initialized
PENOCR Initialized — — — — — — Initialized
PFNOCR Initialized — — — — — — Initialized
PCNOCR Initialized — — — — — — Initialized
PDNOCR Initialized — — — — — — Initialized
PORT
TWR0MW — — — — — — — LPC
TWR0SW — — — — — — —
TWR1 — — — — — — —
TWR2 — — — — — — —
TWR3 — — — — — — —
TWR4 — — — — — — —
TWR5 — — — — — — —
Rev. 1.00, 05/04, page 498 of 544
Register
Abbrevia-
tion Reset
High-Speed/
Medium-
Speed Watch Sleep
Sub-
Active Sub-Sleep
Module
Stop
Software
Standby
Hardware
Standby Module
TWR6 — — — — — — — LPC
TWR7 — — — — — — —
TWR8 — — — — — — —
TWR9 — — — — — — —
TWR10 — — — — — — —
TWR11 — — — — — — —
TWR12 — — — — — — —
TWR13 — — — — — — —
TWR14 — — — — — — —
TWR15 — — — — — — —
IDR3 — — — — — — —
ODR3 — — — — — — —
STR3 Initialized — — — — — — Initialized
LADR3H Initialized — — — — — — Initialized
LADR3L Initialized — — — — — — Initialized
SIRQCR0 Initialized — — — — — — Initialized
SIRQCR1 Initialized — — — — — — Initialized
IDR1 — — — — — — —
ODR1 — — — — — — —
STR1 Initialized — — — — — — Initialized
IDR2 — — — — — — —
ODR2 — — — — — — —
STR2 Initialized — — — — — — Initialized
HISEL Initialized — — — — — — Initialized
HICR0 Initialized — — — — — — Initialized
HICR1 Initialized — — — — — — Initialized
HICR2 Initialized — — — — — — Initialized
HICR3 — — — — — — —
Rev. 1.00, 05/04, page 499 of 544
Register
Abbrevia-
tion Reset
High-Speed/
Medium-
Speed Watch Sleep
Sub-
Active Sub-Sleep
Module
Stop
Software
Standby
Hardware
Standby Module
WUEMRB Initialized — — — — — — Initialized INT
PGODR Initialized — — — — — — Initialized
PGPIN — — — — — — —
PGDDR Initialized — — — — — — Initialized
PEODR Initialized — — — — — — Initialized
PFODR Initialized — — — — — — Initialized
PEPIN — — — — — — —
PEDDR Initialized — — — — — — Initialized
PFPIN — — — — — — —
PFDDR Initialized — — — — — — Initialized
PCODR Initialized — — — — — — Initialized
PDODR Initialized — — — — — — Initialized
PCPIN — — — — — — —
PCDDR Initialized — — — — — — Initialized
PDPIN — — — — — — —
PDDDR Initialized — — — — — — Initialized
PORT
ICXR_0 Initialized — — — — — — Initialized IIC_0
ICXR_1 Initialized — — — — — — Initialized IIC_1
KBCRH_0 Initialized Initialized — Initialized Initialized Initialized Initialized Initialized
KBCRL_0 Initialized Initialized — Initialized Initialized Initialized Initialized Initialized
KBBR_0 Initialized Initialized — Initialized Initialized Initialized Initialized Initialized
Keyboard
buffer
controller_0
KBCRH_1 Initialized Initialized — Initialized Initialized Initialized Initialized Initialized
KBCRL_1 Initialized Initialized — Initialized Initialized Initialized Initialized Initialized
KBBR_1 Initialized Initialized — Initialized Initialized Initialized Initialized Initialized
Keyboard
buffer
controller_1
KBCRH_2 Initialized Initialized — Initialized Initialized Initialized Initialized Initialized
KBCRL_2 Initialized Initialized — Initialized Initialized Initialized Initialized Initialized
KBBR_2 Initialized Initialized — Initialized Initialized Initialized Initialized Initialized
Keyboard
buffer
controller_2
DDCSWR Initialized — — — — — — Initialized IIC common
Rev. 1.00, 05/04, page 500 of 544
Register
Abbrevia-
tion Reset
High-Speed/
Medium-
Speed Watch Sleep
Sub-
Active Sub-Sleep
Module
Stop
Software
Standby
Hardware
Standby Module
ICRA Initialized — — — — — — Initialized
ICRB Initialized — — — — — — Initialized
INT
ICRC Initialized — — — — — — Initialized
ISR Initialized — — — — — — Initialized
ISCRH Initialized — — — — — — Initialized
ISCRL Initialized — — — — — — Initialized
ABRKCR Initialized — — — — — — Initialized
BARA Initialized — — — — — — Initialized
BARB Initialized — — — — — — Initialized
BARC Initialized — — — — — — Initialized
FLMCR1 Initialized Initialized — Initialized Initialized — Initialized Initialized
FLMCR2 Initialized Initialized — Initialized Initialized — Initialized Initialized
FLASH
PCSR Initialized — — — — — — Initialized PWM
EBR1 Initialized Initialized — Initialized Initialized — Initialized Initialized FLASH
SYSCR2 Initialized — — — — — — Initialized SYSTEM
EBR2 Initialized Initialized — Initialized Initialized — Initialized Initialized FLASH
SBYCR Initialized — — — — — — Initialized
LPWRCR Initialized — — — — — — Initialized
MSTPCRH Initialized — — — — — — Initialized
MSTPCRL Initialized — — — — — — Initialized
SYSTEM
SMR_1 Initialized Initialized — Initialized Initialized Initialized Initialized Initialized SCI_1
ICCR_1 Initialized — — — — — — Initialized IIC_1
BRR_1 Initialized Initialized — Initialized Initialized Initialized Initialized Initialized SCI_1
ICSR_1 Initialized — — — — — — Initialized IIC_1
SCR_1 Initialized Initialized — Initialized Initialized Initialized Initialized Initialized
TDR_1 Initialized Initialized — Initialized Initialized Initialized Initialized Initialized
SSR_1 Initialized Initialized — Initialized Initialized Initialized Initialized Initialized
RDR_1 Initialized Initialized — Initialized Initialized Initialized Initialized Initialized
SCMR_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized
SCI_1
ICDR_1 — — — — — — —
SARX_1 Initialized — — — — — — Initialized
ICMR_1 Initialized — — — — — — Initialized
SAR_1 Initialized — — — — — — Initialized
IIC_1
Rev. 1.00, 05/04, page 501 of 544
Register
Abbrevia-
tion Reset
High-Speed/
Medium-
Speed Watch Sleep
Sub-
Active Sub-Sleep
Module
Stop
Software
Standby
Hardware
Standby Module
TIER Initialized — — — — — — Initialized
TCSR Initialized — — — — — — Initialized
FRCH Initialized — — — — — — Initialized
FRCL Initialized — — — — — — Initialized
OCRAH Initialized — — — — — — Initialized
OCRBH Initialized — — — — — — Initialized
OCRAL Initialized — — — — — — Initialized
OCRBL Initialized — — — — — — Initialized
TCR Initialized — — — — — — Initialized
TOCR Initialized — — — — — — Initialized
ICRAH Initialized — — — — — — Initialized
OCRARH Initialized — — — — — — Initialized
FRT
ICRAL Initialized — — — — — — Initialized
OCRARL Initialized — — — — — — Initialized
ICRBH Initialized — — — — — — Initialized
OCRAFH Initialized — — — — — — Initialized
ICRBL Initialized — — — — — — Initialized
OCRAFL Initialized — — — — — — Initialized
ICRCH Initialized — — — — — — Initialized
OCRDMH Initialized — — — — — — Initialized
ICRCL Initialized — — — — — — Initialized
OCRDML Initialized — — — — — — Initialized
ICRDH Initialized — — — — — — Initialized
ICRDL Initialized — — — — — — Initialized
TCSR_0 Initialized — — — — — — Initialized
TCNT_0 Initialized — — — — — — Initialized
WDT_0
Rev. 1.00, 05/04, page 502 of 544
Register
Abbrevia-
tion Reset
High-Speed/
Medium-
Speed Watch Sleep
Sub-
Active Sub-Sleep
Module
Stop
Software
Standby
Hardware
Standby Module
PAODR Initialized — — — — — — Initialized
PAPIN — — — — — — —
PADDR Initialized — — — — — — Initialized
P1PCR Initialized — — — — — — Initialized
P2PCR Initialized — — — — — — Initialized
PORT
P3PCR Initialized — — — — — — Initialized
P1DDR Initialized — — — — — — Initialized
P2DDR Initialized — — — — — — Initialized
P1DR Initialized — — — — — — Initialized
P2DR Initialized — — — — — — Initialized
P3DDR Initialized — — — — — — Initialized
P4DDR Initialized — — — — — — Initialized
P3DR Initialized — — — — — — Initialized
P4DR Initialized — — — — — — Initialized
P5DDR Initialized — — — — — — Initialized
P6DDR Initialized — — — — — — Initialized
P5DR Initialized — — — — — — Initialized
P6DR Initialized — — — — — — Initialized
PBODR Initialized — — — — — — Initialized
PBPIN — — — — — — —
P8DDR Initialized — — — — — — Initialized
P7PIN — — — — — —
PBDDR Initialized — — — — — — Initialized
P8DR Initialized — — — — — — Initialized
P9DDR Initialized — — — — — — Initialized
P9DR Initialized — — — — — — Initialized
IER Initialized — — — — — — Initialized INT
STCR Initialized — — — — — — Initialized
SYSCR Initialized — — — — — — Initialized
MDCR Initialized — — — — — — Initialized
SYSTEM
BCR Initialized — — — — — — Initialized
WSCR Initialized — — — — — — Initialized
BSC
Rev. 1.00, 05/04, page 503 of 544
Register
Abbrevia-
tion Reset
High-Speed/
Medium-
Speed Watch Sleep
Sub-
Active Sub-Sleep
Module
Stop
Software
Standby
Hardware
Standby Module
TCR_0 Initialized — — — — — — Initialized
TCR_1 Initialized — — — — — — Initialized
TCSR_0 Initialized — — — — — — Initialized
TCSR_1 Initialized — — — — — — Initialized
TCORA_0 Initialized — — — — — — Initialized
TCORA_1 Initialized — — — — — — Initialized
TMR_0,
TMR_1
TCORB_0 Initialized — — — — — — Initialized
TCORB_1 Initialized — — — — — — Initialized
TCNT_0 Initialized — — — — — — Initialized
TCNT_1 Initialized — — — — — — Initialized
PWOERA Initialized — — — — — — Initialized
PWDPRA Initialized — — — — — — Initialized
PWSL Initialized Initialized — Initialized Initialized Initialized Initialized Initialized
PWDR0 to
PWDR7
Initialized Initialized — Initialized Initialized Initialized Initialized Initialized
PWM
ICCR_0 Initialized — — — — — — Initialized IIC_0
ICSR_0 Initialized — — — — — — Initialized
ICDR_0 — — — — — — —
SARX_0 Initialized — — — — — — Initialized
ICMR_0 Initialized — — — — — — Initialized
SAR_0 Initialized — — — — — — Initialized
ADDRAH Initialized Initialized — Initialized Initialized Initialized Initialized Initialized
ADDRAL Initialized Initialized — Initialized Initialized Initialized Initialized Initialized
ADDRBH Initialized Initialized — Initialized Initialized Initialized Initialized Initialized
ADDRBL Initialized Initialized — Initialized Initialized Initialized Initialized Initialized
ADDRCH Initialized Initialized — Initialized Initialized Initialized Initialized Initialized
ADDRCL Initialized Initialized — Initialized Initialized Initialized Initialized Initialized
ADDRDH Initialized Initialized — Initialized Initialized Initialized Initialized Initialized
ADDRDL Initialized Initialized — Initialized Initialized Initialized Initialized Initialized
ADCSR Initialized Initialized — Initialized Initialized Initialized Initialized Initialized
A/D
converter
ADCR Initialized Initialized — Initialized Initialized Initialized Initialized Initialized
TCSR_1 Initialized — — — — — — Initialized
TCNT_1 Initialized — — — — — — Initialized
WDT_1
Rev. 1.00, 05/04, page 504 of 544
Register
Abbrevia-
tion Reset
High-Speed/
Medium-
Speed Watch Sleep
Sub-
Active Sub-Sleep
Module
Stop
Software
Standby
Hardware
Standby Module
TCR_X Initialized — — — — — — Initialized TMR_X
TCR_Y Initialized — — — — — — Initialized TMR_Y
KMIMR Initialized — — — — — — Initialized INT
TCSR_X Initialized — — — — — — Initialized TMR_X
TCSR_Y Initialized — — — — — — Initialized TMR_Y
KMPCR Initialized — — — — — — Initialized PORT
TICRR Initialized — — — — — — Initialized TMR_X
TCORA_Y Initialized — — — — — — Initialized TMR_Y
KMIMRA Initialized — — — — — — Initialized INT
TICRF Initialized — — — — — — Initialized TMR_X
TCORB_Y Initialized — — — — — — Initialized TMR_Y
TCNT_X Initialized — — — — — — Initialized TMR_X
TCNT_Y Initialized — — — — — — Initialized TMR_Y
TCORC Initialized — — — — — — Initialized TMR_X
TISR Initialized — — — — — — Initialized TMR_Y
TCORA_X Initialized — — — — — — Initialized
TCORB_X Initialized — — — — — — Initialized
TMR_X
TCONRI Initialized — — — — — — Initialized TMR_X
TCONRS Initialized — — — — — — Initialized TMR_Y
Note: * The program development tool (emulator) does not support these registers.
Rev. 1.00, 05/04, page 505 of 544
21.4 Register Select Conditions
Lower Address Register Name Register Select Condition Module Name
H'FE00 TCR_B
H'FE01 TCR_A
H'FE02 TCSR_B
H'FE03 TCSR_A
H'FE04 TCORA_B
H'FE05 TCORA_A
H'FE06 TCORB_B
H'FE07 TCORB_A
H'FE08 TCNT_B
H'FE09 TCNT_A
H'FE0A TISR_B
H'FE0C TICRR_A
H'FE0D TICRF_A
H'FE0E TCRAB
MSTP1 = 0 TMR_A, TMR_B
H'FE10 TCRXY* No condition TMR_X, TMR_Y
H'FE12 SPSR* No condition SCL_1
H'FE14 PGCTL* No condition IIC common
H'FE16 PGNOCR
H'FE18 PENOCR
H'FE19 PFNOCR
H'FE1C PCNOCR
H'FE1D PDNOCR
No condition PORT
Rev. 1.00, 05/04, page 506 of 544
Lower Address Register Name Register Select Condition Module Name
TWR0MW
H'FE20
TWR0SW
H'FE21 TWR1
H'FE22 TWR2
H'FE23 TWR3
H'FE24 TWR4
H'FE25 TWR5
H'FE26 TWR6
H'FE27 TWR7
H'FE28 TWR8
H'FE29 TWR9
H'FE2A TWR10
H'FE2B TWR11
H'FE2C TWR12
H'FE2D TWR13
H'FE2E TWR14
H'FE2F TWR15
MSTP0 = 0 LPC
H'FE30 IDR3
H'FE31 ODR3
H'FE32 STR3
H'FE34 LADR3H
H'FE35 LADR3L
H'FE36 SIRQCR0
H'FE37 SIRQCR1
H'FE38 IDR1
H'FE39 ODR1
H'FE3A STR1
H'FE3C IDR2
H'FE3D ODR2
H'FE3E STR2
H'FE3F HISEL
H'FE40 HICR0
H'FE41 HICR1
H'FE42 HICR2
H'FE43 HICR3
Rev. 1.00, 05/04, page 507 of 544
Lower Address Register Name Register Select Condition Module Name
H'FE44 WUEMRB No condition INT
H'FE46 PGODR
H'FE47 PGPIN (read)
PGDDR (write)
H'FE48 PEODR
H'FE49 PFODR
PEPIN (read) H'FE4A
PEDDR (write)
PFPIN (read) H'FE4B
PFDDR (write)
H'FE4C PCODR
H'FE4D PDODR
No condition PORT
PCPIN (read) H'FE4E
PCDDR (write)
PDPIN (read) H'FE4F
PDDDR (write)
H'FED4 ICXR_0
H'FED5 ICXR_1
No condition IIC_0
IIC_1
H'FED8 KBCRH_0
H'FED9 KBCRL_0
H'FEDA KBBR_0
H'FEDC KBCRH_1
H'FEDD KBCRL_1
H'FEDE KBBR_1
H'FEE0 KBCRH_2
H'FEE1 KBCRL_2
H'FEE2 KBBR_2
MSTP2 = 0 Keyboard buffer
controller
H'FEE6 DDCSWR MSTP4 = 0 IIC common
Rev. 1.00, 05/04, page 508 of 544
Lower Address Register Name Register Select Condition Module Name
H'FEE8 ICRA
H'FEE9 ICRB
H'FEEA ICRC
H'FEEB ISR
H'FEEC ISCRH
H'FEED ISCRL
No condition INT
H'FEF4 ABRKCR
H'FEF5 BARA
H'FEF6 BARB
H'FEF7 BARC
H'FF80 FLMCR1 FLSHE = 1 in STCR FLASH
H'FF81 FLMCR2
H'FF82 PCSR FLSHE = 0 in STCR PWM
EBR1 FLSHE = 1 in STCR FLASH
H'FF83 SYSCR2 FLSHE = 0 in STCR SYSTEM
EBR2 FLSHE = 1 in STCR FLASH
H'FF84 SBYCR FLSHE = 0 in STCR SYSTEM
H'FF85 LPWRCR
H'FF86 MSTPCRH
H'FF87 MSTPCRL
H'FF88 ICCR_1 MSTP3 = 0, IICE = 1 in STCR IIC_1
H'FF89 ICSR_1 MSTP3 = 0, IICE = 1 in STCR
ICDR_1 ICE = 1 in ICCR1 H'FF8E
SARX_1 ICE = 0 in ICCR1
H'FF8F ICMR_1 ICE = 1 in ICCR1
SAR_1
MSTP3 = 0,
IICE = 1 in
STCR
ICE = 0 in ICCR1
H'FF90 TIER MSTP13 = 0 FRT
H'FF91 TCSR
H'FF92 FRCH
H'FF93 FRCL
Rev. 1.00, 05/04, page 509 of 544
Lower Address Register Name Register Select Condition Module Name
OCRAH OCRS = 0 in TOCR
H'FF94
OCRBH OCRS = 1 in TOCR
OCRAL OCRS = 0 in TOCR H'FF95
OCRBL OCRS = 1 in TOCR
H'FF96 TCR
H'FF97 TOCR
ICRAH ICRS = 0 in TOCR H'FF98
OCRARH
MSTP13 = 0
ICRS = 1 in TOCR
FRT
ICRAL ICRS = 0 in TOCR H'FF99
OCRARL ICRS = 1 in TOCR
ICRBH ICRS = 0 in TOCR H'FF9A
OCRAFH ICRS = 1 in TOCR
ICRBL ICRS = 0 in TOCR H'FF9B
OCRAFL ICRS = 1 in TOCR
ICRCH ICRS = 0 in TOCR H'FF9C
OCRDMH ICRS = 1 in TOCR
ICRCL ICRS = 0 in TOCR H'FF9D
OCRDML ICRS = 1 in TOCR
H'FF9E ICRDH
H'FF9F ICRDL
TCSR_0 H'FFA8
TCNT_0 (write)
H'FFA9 TCNT_0 (read)
No condition WDT_0
Rev. 1.00, 05/04, page 510 of 544
Lower Address Register Name Register Select Condition Module Name
H'FFAA PAODR No condition PORT
H'FFAB PAPIN (read)
PADDR (write)
H'FFAC P1PCR
H'FFAD P2PCR
H'FFAE P3PCR
H'FFB0 P1DDR
H'FFB1 P2DDR
H'FFB2 P1DR
H'FFB3 P2DR
H'FFB4 P3DDR
H'FFB5 P4DDR
H'FFB6 P3DR
H'FFB7 P4DR
H'FFB8 P5DDR
H'FFB9 P6DDR
H'FFBA P5DR
H'FFBB P6DR
H'FFBC PBODR
H'FFBD P8DDR (write)
PBPIN (read)
H'FFBE P7PIN (read)
PBDDR (write)
H'FFBF P8DR
H'FFC0 P9DDR
H'FFC1 P9DR
H'FFC2 IER No condition INT
H'FFC3 STCR No condition SYSTEM
H'FFC4 SYSCR
H'FFC5 MDCR
H'FFC6 BCR No condition BSC
H'FFC7 WSCR
Rev. 1.00, 05/04, page 511 of 544
Lower Address Register Name Register Select Condition Module Name
H'FFC8 TCR_0 MSTP12 = 0 TMR_0, TMR_1
H'FFC9 TCR_1
H'FFCA TCSR_0
H'FFCB TCSR_1
H'FFCC TCORA_0
H'FFCD TCORA_1
H'FFCE TCORB_0
H'FFCF TCORB_1
H'FFD0 TCNT_0
H'FFD1 TCNT_1
H'FFD3 PWOERA No condition PWM
H'FFD5 PWDPRA
H'FFD6 PWSL MSTP11 = 0
H'FFD7 PWDR0 to
PWDR7
H'FFD8 ICCR_0 MSTP4 = 0, IICE = 1 in STCR IIC_0
H'FFD9 ICSR_0
H'FFDE ICDR_0 ICE = 1 in ICCR0
SARX_0
MSTP4 = 0,
IICE = 1 in
STCR ICE = 0 in ICCR0
H'FFDF ICMR_0 ICE = 1 in ICCR0
SAR_0
MSTP4 = 0,
IICE = 1 in
STCR ICE = 0 in ICCR0
H'FFE0 ADDRAH MSTP9 = 0 A/D
H'FFE1 ADDRAL
H'FFE2 ADDRBH
H'FFE3 ADDRBL
H'FFE4 ADDRCH
H'FFE5 ADDRCL
H'FFE6 ADDRDH
H'FFE7 ADDRDL
H'FFE8 ADCSR
H'FFE9 ADCR
Rev. 1.00, 05/04, page 512 of 544
Lower Address Register Name Register Select Condition Module Name
H'FFEA TCSR_1 No condition WDT_1
TCNT_1 (write)
H’FFEB TCNT_1 (read)
H'FFF0 TCR_X TMRX/Y = 0 in
TCONRS
TMR_X
TCR_Y
MSTP8 = 0,
HIE = 0 in
SYSCR TMRX/Y = 1 in
TCONRS
TMR_Y
H'FFF1 KMIMR MSTP2 = 0, HIE = 0 in SYSCR INT
TCSR_X TMRX/Y = 0 in
TCONRS
TMR_X
TCSR_Y
MSTP8 = 0,
HIE = 0 in
SYSCR TMRX/Y = 1 in
TCONRS
TMR_Y
H'FFF2 KMPCR MSTP2 = 0, HIE = 1 in SYSCR PORT
TICRR TMRX/Y = 0 in
TCONRS
TMR_X
TCORA_Y
MSTP8 = 0,
HIE = 0 in
SYSCR TMRX/Y = 1 in
TCONRS
TMR_Y
H'FFF3 KMIMRA MSTP2 = 0, HIE = 1 in SYSCR INT
TICRF TMRX/Y = 0 in
TCONRS
TMR_X
TCORB_Y
MSTP8 = 0,
HIE = 0 in
SYSCR TMRX/Y = 1 in
TCONRS
TMR_Y
H'FFF4 TCNT_X TMRX/Y = 0 in
TCONRS
TMR_X
TCNT_Y
MSTP8 = 0,
HIE = 0 in
SYSCR TMRX/Y = 1 in
TCONRS
TMR_Y
H'FFF5 TCORC TMRX/Y = 0 in
TCONRS
TMR_X
TISR
MSTP8 = 0,
HIE = 0 in
SYSCR TMRX/Y = 1 in
TCONRS
TMR_Y
H'FFF6 TCORA_X
H'FFF7 TCORB_X
MSTP8 = 0,
HIE = 0 in
SYSCR
TMRX/Y = 0 in
TCONRS
H'FFFC TCONRI MSTP8 = 0, HIE = 0 in SYSCR
TMR_X
H'FFFE TCONRS MSTP8 = 0, HIE = 0 in SYSCR TMR_Y
Note: * The program development tool (emulator) does not support these registers.
Rev. 1.00, 05/04, page 513 of 544
Section 22 Electrical Characteristics
22.1 Absolute Maximum Ratings
Table 22.1 lists the absolute maximum ratings.
Table 22.1 Absolute Maximum Ratings
Item Symbol Value Unit
Power supply voltage VCC, VCL –0.3 to +4.3 V
I/O buffer power supply voltage VCCB –0.3 to +7.0 V
Input voltage (except ports 7, A, P97, P86, P52, P42,
and port G)
Vin –0.3 to VCC +0.3 V
Input Voltage (port A) Vin –0.3 to VCCB +0.3 V
Input voltage (P97, P86, P52, P42 and port G) Vin –0.3 to +7.0 V
Input voltage (port 7) Vin –0.3 to AVCC + 0.3 V
Reference supply voltage AVref –0.3 to AVCC + 0.3 V
Analog power supply voltage AVCC –0.3 to +4.3 V
Analog input voltage VAN –0.3 to AVCC +0.3 V
Operating temperature Topr –20 to +75 °C
Operating temperature (flash memory
programming/erasing)
Topr –20 to +75 °C
Storage temperature Tstg –55 to +125 °C
Caution: Permanent damage to the chip may result if absolute maximum ratings are exceeded.
Ensure so that the impressed voltage does not exceed 4.3 V for pins for which the
maximum rating is determined by the voltage on the VCC, AVCC, and VCL pins, or 7.0 V for
pins for which the maximum rating is determined by VCCB.
The VCC and VCL pins must be connected to the Vcc power supply.
Rev. 1.00, 05/04, page 514 of 544
22.2 DC Characteristics
Table 22.2 lists the DC characteristics. Permitted output current values and bus drive
characteristics are shown in tables 22.3 and 22.4, respectively.
Table 22.2 DC Characteristics (1)
Conditions: VCC = 3.0 V to 3.6 V*7, VCCB = 3.0 V to 5.5 V, AVCC*1 = 3.0 V to 3.6 V,
AVref*1 = 3.0 V to AVCC, VSS = AVSS*1 = 0 V, Ta = –20 to +75°C
Item Symbol Min. Typ. Max. Unit
Test
Conditions
VT
V
CC × 0.2
VCCB × 0.2
— —
VT
+ VCC × 0.7
VCCB × 0.7
Schmitt
trigger input
voltage
P67 to
P60*2,
KIN15 to KIN8,
IRQ2 to IRQ0*3,
IRQ5 to IRQ3
(1)*8
VT
+ – VT
V
CC × 0.05
VCCB × 0.05
— —
V
RES, STBY,
NMI, MD1, MD0
VCC × 0.9 VCC +0.3
EXTAL VCC × 0.7 VCC +0.3
Input high
voltage
PA7 to PA0*7
(2) VIH
VCCB × 0.7 VCCB + 0.3
V
Port 7 VCC × 0.7 AVCC + 0.3
P97, P86, P52,
P42, and Port G
(2)
VCC × 0.7 5.5
Input pins except (1)
and (2) above
VIH
VCC × 0.7 VCC + 0.3
RES, STBY,
MD1, MD0
(3) VIL –0.3 VCC × 0.1
VCCB × 0.2 VCCB = 3.0 V
to 4.0 V
PA7 to PA0 –0.3
0.8 VCCB = 4.0 V
to 5.5 V
Input low
voltage
NMI, EXTAL,
input pins except (1)
and (3) above
–0.3 — VCC × 0.2
V
VCC = 3.0 V to
3.6 V
VCC – 0.5
VCCB – 0.5
— — V IOH = –200 µA All output pins (except
P97, P86, P52, P42,
and Port G) *4, *5, *6 VCC – 1.0
VCCB – 1.0
— — V IOH = –1 mA,
(VCC = 3.0 V to
3.6 V,
VCCB = 3.0 V
to 4.5 V)
Output high
voltage
P97, P86, P52, P42,
and Port G*4
VOH
0.5 — V IOH = –200 µA
Rev. 1.00, 05/04, page 515 of 544
Item Symbol Min. Typ. Max. Unit
Test
Conditions
All output pins
(except RESO)*5
— — 0.4 V IOL = 1.6 mA
Ports 1 to 3 1.0 V IOL = 5 mA
Output low
voltage
RESO
VOL
— — 0.4 V IOL = 1.6 mA
Notes: 1. Do not leave the AVcc, AVref, and AVss pins open even if the A/D converter is not used.
Even if the A/D converter is not used, apply a value in the range 2.0 V to 3.6 V to AVCC
and AVref pins by connection to the power supply (VCC), or some other method. Ensure
that AVref AVCC.
2. P67 to P60 include peripheral module inputs multiplexed on those pins.
3. IRQ2 includes the ADTRG signal multiplexed on that pin.
4. P52/ExSCK1/SCL0, P97/SDA0, P86/SCK1/SCL1, P42/SDA1, and port G are NMOS
push-pull outputs.
When the SCL0, SDA0, SCL1, SDA1 (ICE = 1), ExSDAA, ExSCLA, ExSDAB, or
ExSCLB pin is used as an output, it is NMOS open-drain output. Therefore, an external
pull-up resistor must be connected in order to output high level.
P52/ExSCK1, P97, P86/SCK1, P42 (ICE = 0), and port G high levels are driven by
NMOS.
An external pull-up resistor is necessary to provide high-level output from ExSCK1 and
SCK1.
5. When IICS = 0, ICE = 0, and KBIOE = 0. Low-level output when the bus drive function
is selected is determined separately.
6. The port A characteristics depend on VCCB, and the other pins characteristics depend
on VCC.
7. For flash memory programming/erasure, the applicable range is VCC = 3.0 V to 3.6 V.
Rev. 1.00, 05/04, page 516 of 544
Table 22.2 DC Characteristics (2)
Conditions: VCC = 3.0 V to 3.6 V*5, VCCB = 3.0 V to 5.5 V, AVCC*1 = 3.0 V to 3.6 V,
AVref*1 = 3.0 V to AVCC, VSS = AVSS*1 = 0 V, Ta = –20 to +75°C
Item Symbol Min. Typ. Max. Unit
Test
Conditions
RES — — 10.0
STBY, NMI, MD1,
MD0 — — 1.0
Vin = 0.5 to
VCC – 0.5 V
Input
leakage
current
Port 7
Iin
— — 1.0
µA
Vin = 0.5 to
AVCC – 0.5 V
Three-state
leakage
current
(off state)
Ports 1 to 6, 8, 9,
A*4, and B to G
ITSI 1.0 µA Vin = 0.5 to
VCC – 0.5 V,
Vin = 0.5 to
VCCB – 0.5 V
Ports 1 to 3 5 150
Ports 6 and B to F 30 300
Input pull-up
MOS current
Ports A*4
–IP
30 — 600
µA Vin = 0 V,
VCC = 3.0 V
to 3.6 V
VCCB = 3.0 V
to 5.5 V
RES80 pF
NMI
(4)
— — 50 pF
Input
capacitance
Input pins except (4)
above
Cin
— — 10 pF
Vin = 0 V,
f = 1 MHz,
Ta = 25°C
Normal operation 30 40 mA f = 10 MHz
Sleep mode 20 32 mA f = 10 MHz
— 1 5.0 Ta 50°C
Current
dissipation*2
Standby mode*3
ICC
— — 20.0
µA
50°C < Ta
During A/D
conversion
— 1.2 2.0 mA Analog power
supply
current Idle
AlCC
— 0.01 5.0 µA AVCC = 2.0 V
to 3.6 V
During A/D
conversion
— 0.5 1.0 mA Reference
power supply
current Idle
Alref
— 0.01 5.0 µA AVref = 2.0 V
to AVCC
Rev. 1.00, 05/04, page 517 of 544
Item Symbol Min. Typ. Max. Unit
Test
Conditions
3.0 — 3.6 Operating
Analog power supply voltage*1 AVCC
2.0 — 3.6
V
Idle/not
used
RAM standby voltage VRAM 2.0 V
Notes: 1. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter is not used.
Even if the A/D converter is not used, apply a value in the range 2.0 V to 3.6 V to AVCC
and AVref pins by connection to the power supply (VCC), or some other method. Ensure
that AVref AVCC.
2. Current dissipation values are for VIH min = VCC – 0.2 V, VCCB – 0.2 V, and
VIL max = 0.2 V with all output pins unloaded and the on-chip pull-up MOSs in the off
state.
3. The values are for VRAM VCC < 3.0 V, VIH min = VCC– 0.2 V, VCCB – 0.2 V, and
VIL max = 0.2 V.
4. The port A characteristics depend on VCCB, and the other pins characteristics depend
on VCC.
5. For flash memory programming/erasure, the applicable range is VCC = 3.0 V to 3.6 V.
Table 22.2 DC Characteristics (3) When LPC Function is Used
Conditions: VCC = 3.0 V to 3.6 V, VCCB = 3.0 V to 5.5 V, AVCC* = 3.0 V to 3.6 V,
AVref* = 3.0 V to AVCC, VSS = AVSS*1 = 0 V, Ta = –20 to +75°C
Item Symbol Min. Max. Unit
Test
Conditions
Input high
voltage
P37 to P30,
P83 to P80,
PB1, PB0
VIH V
CC × 0.5 V
Input low
voltage
P37 to P30,
P83 to P80,
PB1, PB0
VILVCC × 0.3 V
Output high
voltage
P37, P33 to P30,
P82 to P80,
PB1, PB0
VOH V
CC × 0.9 V IOH = –0.5
mA
Output low
voltage
P37, P33 to P30,
P82 to P80,
PB1, PB0
VOL VCC × 0.1 V IOL = 1.5 mA
Note: * Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter is not used.
Even if the A/D converter is not used, apply a value in the range 2.0 V to 3.6 V to AVCC
and AVref pins by connection to the power supply (VCC), or some other method. Ensure
that AVref AVCC.
Rev. 1.00, 05/04, page 518 of 544
Table 22.3 Permissible Output Currents
Conditions: VCC = 3.0 V to 3.6 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, Ta = –20 to +75°C
Item Symbol Min. Typ. Max. Unit
SCL1, SCL0,
SDA1, SDA0,
PS2AC to PS2CC,
PS2AD to PS2CD,
PA7 to PA4,
ExSDAA, ExSCLA,
ExSDAB, ExSCLB
(bus drive function
selected)
— — 10
Ports 1, 2, 3 2
RESO1
Permissible
output
low current
(per pin)
Other output pins
IOL
— — 1
mA
Total of ports 1, 2,
and 3
— — 40 Permissible
output
low current
(total) Total of all output
pins, including the
above
IOL
— — 60
mA
Permissible
output
high current
(per pin)
All output pins –IOH — — 2 mA
Permissible
output
high current
(total)
Total of all output
pins
–IOH 30 mA
Notes: 1. To protect chip reliability, do not exceed the output current values in table 22.3.
2. When driving a Darlington pair or LED, always insert a current-limiting resistor in the
output line, as show in figures 22.1 and 22.2.
2 k
This LSI
Port
Darlington pair
Figure 22.1 Darlington Pair Drive Circuit (Example)
Rev. 1.00, 05/04, page 519 of 544
600
This LSI
Ports 1 to 3
LED
Figure 22.2 LED Drive Circuit (Example)
Table 22.4 Bus Drive Characteristics
Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, Ta = –20 to +75°C
Applicable Pins: SCL1, SCL0, SDA1, SDA0 ExSDAA, ExSCLA, ExSDAB, ExSCLB (bus
drive function selected)
Item Symbol Min. Typ. Max. Unit
Test
Conditions
VT
V
CC × 0.3 VCC = 3.0 V
to 3.6 V
VT
+ VCC × 0.7 VCC = 3.0 V
to 3.6 V
Schmitt trigger
input voltage
VT
+ – VT
V
CC × 0.05
V
VCC = 3.0 V
to 3.6 V
Input high voltage VIH V
CC × 0.7 5.5 V VCC = 3.0 V
to 3.6 V
Input low voltage VIL –0.5 VCC × 0.3 VCC = 3.0 V
to 3.6 V
VOL 0.5 V IOL = 8 mA Output low voltage
0.4 IOL = 3 mA
Input capacitance Cin 10 pF Vin = 0 V,
f = 1 MHz,
Ta = 25°C
Three-state leakage current
(off state)
| ITSI | 1.0 µA Vin = 0.5 to
VCC – 0.5 V
SCL, SDA output fall time tOf 20 + 0.1Cb 250 ns VCC = 3.0 V
to 3.6 V
Rev. 1.00, 05/04, page 520 of 544
Conditions: VCC = 3.0 V to 3.6 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, Ta = –20 to +75°C
Applicable Pins: PS2AC, PS2AD, PS2BC, PS2BD, PS2CC, PS2CD, PA7 to PA4 (bus drive
function selected)
Item Symbol Min. Typ. Max. Unit Test
Conditions
— — 0.8 IOL = 16 mA,
VCCB = 4.5 V
to 5.5 V
— — 0.5 IOL = 8 mA
Output low voltage VOL
— — 0.4
V
IOL = 3 mA
22.3 AC Characteristics
Figure 22.3 shows the test conditions for the AC characteristics.
C
Chip output pin
R
H
R
L
C = 30 pF: All output ports
R
L
= 2.4 k
R
H
= 12 k
I/O timing test levels
• Low level: 0.8 V
• High level: 2.0 V
V
CC
Figure 22.3 Output Load Circuit
Rev. 1.00, 05/04, page 521 of 544
22.3.1 Clock Timing
Table 22.5 shows the clock timing. The clock timing specified here covers clock (φ) output and
clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation settling times.
For details on external clock input (EXTAL pin and EXCL pin) timing, see section19, Clock Pulse
Generator.
Table 22.5 Clock Timing
Condition: VCC = 3.0 V to 3.6 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, φ = 4 MHz to maximum
operating frequency, Ta = –20 to +75°C
Condition
10 MHz
Item Symbol
Min. Max.
Unit Reference
Clock cycle time tcyc 100 250 ns
Clock high pulse width tCH 30 ns
Clock low pulse width tCL 30 ns
Clock rise time tCr20 ns
Clock fall time tCf20 ns
Figure 22.5
Oscillation settling time at reset (crystal) tOSC1 20 ms
Oscillation settling time in software
standby (crystal)
tOSC2 8 ms
External clock output stabilization delay
time
tDEXT 500 µs
Figure 22.6
Figure 22.7
Rev. 1.00, 05/04, page 522 of 544
22.3.2 Control Signal Timing
Table 22.6 shows the control signal timing. The only external interrupts that can operate on the
subclock (φ = 32.768 kHz) are NMI and IRQ0, 1, 2, 6, and 7.
Table 22.6 Control Signal Timing
Conditions: VCC = 3.0 V to 3.6 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, φ = 32.768 kHz, 4 MHz to
maximum operating frequency, Ta = –20 to +75°C
Condition
10 MHz
Item Symbol Min. Max. Unit
Test
Conditions
RES setup time tRESS 300 ns
RES pulse width tRESW 20 tcyc
Figure 22.8
NMI setup time (NMI) tNMIS 250 ns
NMI hold time (NMI) tNMIH 10 ns
NMI pulse width
(exiting software standby mode)
tNMIW 200 ns
IRQ setup time (IRQ7 to IRQ0) tIRQS 250 ns
IRQ hold time(IRQ7 to IRQ0) tIRQH 10 ns
IRQ pulse width
(IRQ7, IRQ6, IRQ2 to IRQ0)
(exiting software standby mode)
tIRQW 200 ns
Figure 22.9
Rev. 1.00, 05/04, page 523 of 544
22.3.3 Timing of On-Chip Peripheral Modules
Tables 22.7 to 22.10 show the on-chip peripheral module timing. The only on-chip peripheral
modules that can operate in subclock operation (φ = 32.768 kHz) are the I/O ports, external
interrupts (NMI and IRQ0, 1, 2, 6, and 7), the watchdog timer, and the 8-bit timer (channels 0 and
1).
Table 22.7 Timing of On-Chip Peripheral Modules (1)
Conditions: VCC = 3.0 V to 3.6 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, φ = 32.768 kHz*,
4 MHz to maximum operating frequency, Ta = –20 to +75°C
Condition
10 MHz
Item Symbol
Min. Max. Unit Test
Conditions
Output data delay time tPWD 100
Input data setup time tPRS 50
I/O ports
Input data hold time tPRH 50
ns Figure 22.10
Timer output delay time tFTOD 100
Timer input setup time tFTIS 50
Figure 22.11
Timer clock input setup time tFTCS 50
ns
Single edge tFTCWH 1.5
FRT
Timer clock
pulse width Both edges tFTCWL 2.5
tcyc
Figure 22.12
Timer output delay time tTMOD 100 Figure 22.13
Timer reset input setup time tTMRS 50 Figure 22.15
Timer clock input setup time tTMCS 50
ns
Single edge tTMCWH 1.5
TMR
Timer clock
pulse width Both edges tTMCWL 2.5
tcyc
Figure 22.14
PWM Pulse output delay time tPWOD 100 ns Figure 22.16
Asynchronous tScyc 4 Input clock
cycle Synchronous 6
tcyc
Input clock pulse width tSCKW 0.4 0.6 tScyc
Input clock rise time tSCKr 1.5
SCI
Input clock fall time tSCKf 1.5
tcyc
Figure 22.17
Rev. 1.00, 05/04, page 524 of 544
Condition
10 MHz
Item Symbol
Min. Max.
Unit Test
Conditions
Transmit data delay
time (synchronous)
tTXD 100 ns
Receive data setup time
(synchronous)
tRXS 100 — ns
SCI
Receive data hold time
(synchronous)
tRXH 100 — ns
Figure 22.18
A/D
converter
Trigger input setup time tTRGS 50 ns Figure 22.19
RESO output delay time tRESD 200 ns WDT
RESO output pulse
width
tRESOW 132 tcyc
Figure 22.20
Note: * Only peripheral modules that can be used in subclock operation
Table 22.8 Keyboard Buffer Controller Timing
Conditions: VCC = 3.0 V to 3.6 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, φ = 4 MHz to maximum
operating frequency, Ta = –20 to +75°C
Ratings
Item Symbol Min. Typ. Max. Unit Test
Conditions Notes
KCLK, KD output fall time tKBF 20 +
0.1Cb
— 250 ns
KCLK, KD input data hold time tKBIH 150 ns
KCLK, KD input data setup time tKBIS 150 ns
KCLK, KD output delay time tKBOD450 ns
KCLK, KD capacitive load Cb400 pF
Figure 22.21
Rev. 1.00, 05/04, page 525 of 544
Table 22.9 I2C Bus Timing
Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 5 MHz to maximum operating frequency,
Ta = –20 to +75°C
Ratings
Item Symbol Min. Typ. Max. Unit
Test
Conditions Notes
SCL input cycle time tSCL 12 — — tcyc
SCL input high pulse width tSCLH 3 — — tcyc
SCL input low pulse width tSCLL 5 — — tcyc
SCL, SDA input rise time tSr7.5* t
cyc
SCL, SDA input fall time tSf300 ns
SCL, SDA input spike pulse
elimination time
tSP1 tcyc
SDA input bus free time tBUF 5 — — tcyc
Start condition input hold time tSTAH 3 — — tcyc
Retransmission start condition
input setup time
tSTAS 3 — — tcyc
Stop condition input setup time tSTOS 3 — — tcyc
Data input setup time tSDAS 0.5 — — tcyc
Data input hold time tSDAH 0 — — ns
SCL, SDA capacitive load Cb400 pF
Figure
22.22
Note: * 17.5 tcyc can be set according to the clock selected for use by the I2C module. For
details, see section 13.6, Usage Notes.
Rev. 1.00, 05/04, page 526 of 544
Table 22.10 LPC Module Timing
Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 4 MHz to maximum operating frequency,
Ta = –20 to +75°C
Item Symbol Min. Typ. Max. Unit
Test
Conditions
Input clock cycle tLcyc 30
Input clock pulse width (H) tLCKH 11
Input clock pulse width (L) tLCKL 11
Transmit signal delay time tTXD 2 11
Transmit signal floating
delay time
tOFF 28
Receive signal setup time tRXS 7
LPC
Receive signal hold time tRXH 0
ns Figure 22.23
22.4 A/D Conversion Characteristics
Tables 22.11 list the A/D conversion characteristics.
Table 22.11 A/D Conversion Characteristics (AN5 to AN0 Input: 134/266-State Conversion)
Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, AVref = 3.0 V to AVCC,
VCCB = 3.0 V to 5.5 V, VSS = AVSS = 0 V,
φ = 4 MHz to maximum operating frequency, Ta = –20 to +75°C
Condition
10 MHz
Item Min. Typ. Max. Unit
Resolution 10 bits
Conversion time 13.4 µs
Analog input capacitance 20 pF
Permissible signal-source impedance 5 k
Nonlinearity error ±7.0 LSB
Offset error ±7.5 LSB
Full-scale error ±7.5 LSB
Quantization error ±0.5 LSB
Absolute accuracy — ±8.0 LSB
Rev. 1.00, 05/04, page 527 of 544
22.5 Flash Memory Characteristics
Table 22.12 shows the flash memory characteristics.
Table 22.12 Flash Memory Characteristics
Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, Ta = –20 to +75°C
Item Symbol Min. Typ. Max. Unit
Test
Condition
Programming time*1, *2,*4 t
P10 200 ms/
128
bytes
Erase time*1, *3,*6 t
E100 1200 ms/
block
Reprogramming count NWEC — — 100 times
Wait time after
SWE-bit setting*1
x 1 µs
Wait time after
PSU-bit setting*1
y 50 µs
z1 28 30 32 µs 1 n 6
z2 198 200 202 µs 7 n 1000
Wait time after
P-bit setting*1, *4
z3 8 10 12 µs Additional
write
Wait time after
P-bit clear*1
α 5 µs
Wait time after
PSU-bit clear*1
β 5 µs
Wait time after
PV-bit setting*1
γ 4 µs
Wait time after
dummy write*1
ε 2 µs
Wait time after
PV-bit clear*1
η 2 µs
Wait time after
SWE-bit clear*1
θ 100 — µs
Programming
Maximum
programming
count*1, *4,*5
N — — 1000 times
Rev. 1.00, 05/04, page 528 of 544
Item Symbol Min. Typ. Max. Unit
Test
Conditions
Wait time after
SWE-bit setting*1
x 1 µs
Wait time after
ESU-bit setting*1
y 100 µs
Wait time after
E-bit setting*1, *6
z 10 100 ms
Wait time after
E-bit clear*1
α 10 µs
Wait time after
ESU-bit clear*1
β 10 µs
Wait time after
EV-bit setting*1
γ 20 µs
Wait time after
dummy write*1
ε 2 µs
Wait time after
EV-bit clear*1
η 4 µs
Wait time after
SWE-bit clear*1
θ 100 — µs
Erase
Maximum erase
count*1, *6, *7
N — — 120 times
Notes: 1. Set the times according to the program/erase algorithms.
2. Programming time per 128 bytes (Shows the total period for which the P-bit in FLMCR1
is set. It does not include the programming verification time.)
3. Block erase time (Shows the total period for which the E-bit in FLMCR1 is set. It does
not include the erase verification time.)
4. Maximum programming time (tP (max))
tP (max) = (wait time after P-bit setting (z1) + (z3)) × 6
+ wait time after P-bit setting (z2) × ((N) – 6)
5. The maximum number of writes (N) should be set according to the actual set value of
z1, z2 and z3 to allow programming within the maximum programming time (tP (max)).
The wait time after P-bit setting (z1, z2, and z3) should be alternated according to the
number of writes (n) as follows:
1 n 6 z1 = 30µs, z3 = 10µs
7 n 1000 z2 = 200µs
6. Maximum erase time (tE (max))
tE (max) = Wait time after E-bit setting (z) × maximum erase count (N)
7. The maximum number of erases (N) should be set according to the actual set value of z
to allow erasing within the maximum erase time (tE (max)).
Rev. 1.00, 05/04, page 529 of 544
22.6 Usage Note
The method of connecting an external capacitor is shown in figure 22.4. Connect the system
power supply to the VCL pin together with the VCC pins.
VCL
VSS
0.01 µF10 µF
Bypass
capacitor
Vcc power supply
< Vcc = 3.0 V to 3.6 V >
Connect the Vcc power supply to the chip's VCL pin in the same way as
the VCC pins.
It is recommended that a bypass capacitor be connected to the power
supply pins. (Values are reference values.)
Figure 22.4 Connection of VCL Capacitor
22.7 Timing Chart
22.7.1 Clock Timing
The clock timings are shown below.
t
CH
t
cyc
t
Cf
t
CL
t
Cr
φ
Figure 22.5 System Clock Timing
Rev. 1.00, 05/04, page 530 of 544
tOSC1
tOSC1
EXTAL
VCC
STBY
RES
φ
tDEXT tDEXT
Figure 22.6 Oscillation Settling Timing
φ
NMI
IRQi
(i = 0, 1, 2, 6, 7)
t
OSC2
Figure 22.7 Oscillation Setting Timing (Exiting Software Standby Mode)
Rev. 1.00, 05/04, page 531 of 544
22.7.2 Control Signal Timing
The control signal timings are shown below.
tRESW
tRESS
φ
tRESS
RES
Figure 22.8 Reset Input Timing
t
IRQS
φ
t
NMIS
t
NMIH
IRQi
Edge input
(i = 7 to 0)
NMI
t
IRQS
t
IRQH
IRQi
(i = 7 to 0)
IRQi
Level input
(i = 7 to 0)
t
NMIW
t
IRQW
Figure 22.9 Interrupt Input Timing
Rev. 1.00, 05/04, page 532 of 544
22.7.3 On-Chip Peripheral Module Timing
The on-chip peripheral module timings are shown below.
φ
Ports 1 to 9, and A to G
(read)
T
2
T
1
t
PWD
t
PRH
t
PRS
Ports 1 to 6, 8, 9,
and A to G
(write)
Figure 22.10 I/O Port Input/Output Timing
φ
tFTIS
tFTOD
FTOA, FTOB
FTIA, FTIB,
FTIC, FTID
Figure 22.11 FRT Input/Output Timing
φ
tFTCS
FTCI
tFTCWH
tFTCWL
Figure 22.12 FRT Clock Input Timing
Rev. 1.00, 05/04, page 533 of 544
φ
TMO0, TMO1
TMOX, ExTMOX,
TMOY, TMOA,
TMOB
t
TMOD
Figure 22.13 8-Bit Timer Output Timing
φ
TMCI0, TMCI1
TMIX, TMIY,
ExTMIX, ExTMIY,
TMIA, TMIB
t
TMCS
t
TMCS
t
TMCWH
t
TMCWL
Figure 22.14 8-Bit Timer Clock Input Timing
φ
t
TMRS
TMRI0, TMRI1
TMIX, TMIY,
ExTMIX, ExTMIY,
TMIA, TMIB
Figure 22.15 8-Bit Timer Reset Input Timing
φ
PW7 to PW0
tPWOD
Figure 22.16 PWM, PWMX Output Timing
Rev. 1.00, 05/04, page 534 of 544
SCK1, ExSCK1
t
SCKW
t
SCKr
t
SCKf
t
Scyc
Figure 22.17 SCK Clock Input Timing
TxD1, ExTxD1
(transmit data)
RxD1, ExRxD1
(receive data)
SCK1, ExSCK1
t
RXS
t
RXH
t
TXD
Figure 22.18 SCI Input/Output Timing (Synchronous Mode)
φ
ADTRG
t
TRGS
Figure 22.19 A/D Converter External Trigger Input Timing
t
RESOW
t
RESD
t
RESD
φ
RESO
Figure 22.20 WDT Output Timing (RESO)
Rev. 1.00, 05/04, page 535 of 544
1. Reception
φ
KCLK/KD*
KCLK/KD*
t
KBIS
t
KBIH
Transmission (b)
t
KBF
2. Transmission (a)
φ
KCLK/KD*
T
1
T
2
t
KBOD
Note: φ shown here is the clock scaled by 1/N when the operating mode is active
medium-speed mode.
* KCLK: PS2AC to PS2CC
KD: PS2AD to PS2CD
Figure 22.21 Keyboard Buffer Controller Timing
SDA0,
SDA1,
ExSDAA,
ExSDAB
V
IL
V
IH
t
BUF
P*P*S*
t
STAH
t
SCLH
t
Sr
t
SCLL
t
SCL
t
Sf
t
SDAH
Sr*
t
SDAS
t
STAS
t
SP
t
STOS
Note:*S, P, and Sr indicate the following conditions.
S:
P:
Sr:
Start condition
Stop condition
Retransmission start condition
SCL0,
SCL1,
ExSCLA,
ExSCLB
Figure 22.22 I2C Bus Interface Input/Output Timing
Rev. 1.00, 05/04, page 536 of 544
LCLK
LAD3 to LAD0,
SERIRQ, CLKRUN
(Transmit signal)
LAD3 to LAD0,
SERIRQ, CLKRUN
LFRAME
(Receive signal)
tTXD
tRXH
tRXS
tOFF
LAD3 to LAD0,
SERIRQ, CLKRUN
(Transmit signal)
tLcyc
tLCKH
LCLK
tLCKL
Figure 22.23 Host Interface (LPC) Timing
Testing voltage: 0.4Vcc
50pF
Figure 22.24 Tester Measurement Condition
Rev. 1.00, 05/04, page 537 of 544
Appendix
A. I/O Port States in Each Processing State
Table A.1 I/O Port States in Each Processing State
Port Name
Pin Name Reset
Hardware
Standby
Mode
Software
Standby
Mode
Watch
Mode
Sleep
Mode
Sub-
sleep Mode
Subactive
Mode
Program
Execution
State
Port 1 T T kept kept kept kept I/O port I/O port
Port 2 T T kept kept kept kept I/O port I/O port
Port 3 T T kept kept kept kept I/O port I/O port
Port 4 T T kept kept kept kept I/O port I/O port
Port 5 T T kept kept kept kept I/O port I/O port
Port 6 T T kept kept kept kept I/O port I/O port
Port 7 T T T T T T Input port Input port
Port 8 T T kept kept kept kept I/O port I/O port
Port 97 T T kept kept kept kept I/O port I/O port
Port 96
φ
EXCL
T T [DDR = 1] H
[DDR = 0] T
EXCL input [DDR = 1]
clock output
[DDR = 0] T
EXCL input EXCL input Clock output/
EXCL input/
input port
Ports 95 to 90 T T kept kept kept kept I/O port I/O port
Port A T T kept kept kept kept I/O port I/O port
Port B T T kept kept kept kept I/O port I/O port
Ports C to G T T kept kept kept kept I/O port I/O port
[Legend]
H: High
L: Low
T: High-impedance state
kept: Input ports are in the high-impedance state (when DDR = 0 and PCR = 1, input pull-up
MOSs remain on).
Output ports maintain their previous state.
Depending on the pins, the on-chip peripheral modules may be initialized and the I/O port
function determined by DDR and DR used.
DDR: Data direction register
Rev. 1.00, 05/04, page 538 of 544
B. Product Codes
Product Type Product Code Mark Code
Package
(Package Code)
H8S/2111B-B HD64F2111BVB F2111BVTE10B
H8S/2111B-C
Flash memory version
(3 V version) HD64F2111BVC F2111BVTE10C
144-pin TQFP (TFP-144)
Rev. 1.00, 05/04, page 539 of 544
C. Package Dimensions
For package dimensions, dimensions described in Renesas Semiconductor Packages Data Book
have priority.
Package Code
JEDEC
EIAJ
Weight
(reference value)
TFP-144
Conforms
0.6 g
Unit: mm
*Dimension including the plating thickness
Base material dimension
108 73
136
0˚ – 8˚
0.08
0.07 M
18.0 ± 0.2
72
144
109
37
18.0 ± 0.2
*0.18 ± 0.05
0.4
1.20 Max
1.0
0.5 ± 0.1
16
1.00
0.10 ± 0.05
*
0.17 ± 0.05
0.16 ± 0.04
0.15 ± 0.04
1.0
Figure C.1 Package Dimensions (TFP-144)
Rev. 1.00, 05/04, page 540 of 544
Rev. 1.00, 05/04, page 541 of 544
Index
16-bit count mode................................... 210
16-bit free-running timer (FRT) ............. 157
8-bit PWM timer (PWM)........................ 147
8-bit timer (TMR)................................... 183
A/D converter ......................................... 413
A20 gate.................................................. 398
Absolute address....................................... 41
Additional pulse...................................... 154
Address map ............................................. 57
Address space ........................................... 20
Addressing modes..................................... 40
ADI......................................................... 423
Analog input channel.............................. 416
Arithmetic operations instructions............ 32
Asynchronous mode ............................... 249
Basic pulse.............................................. 153
Bcc............................................................ 37
Bit manipulation instructions.................... 35
Bit rate .................................................... 244
Block data transfer instructions ................ 38
Boot mode .............................................. 442
Branch instructions................................... 37
Break....................................................... 272
Buffered input capture input................... 173
Bus controller (BSC) ................................ 93
.................................................................. 93
Carrier frequency.................................... 149
Cascaded connection .............................. 210
Clear timing ............................................ 171
Clock pulse generator ............................. 455
Clocked synchronous mode.................... 264
CMI......................................................... 215
CMIA...................................................... 215
CMIAAB ................................................ 215
CMIAY................................................... 215
CMIB...................................................... 215
CMIBAB................................................. 215
CMIBY ................................................... 215
Compare-match count mode ...................210
Condition field .......................................... 39
Condition-code register............................. 24
Conversion time...................................... 421
Crystal resonator ..................................... 456
Data transfer instructions ..........................31
Direct transitions..................................... 477
EEPMOV instruction................................ 49
Effective address................................. 40, 44
Effective address extension....................... 39
Electrical characteristics ......................... 513
Erase/erase-verify ................................... 448
Erasing units ...........................................436
ERRI ....................................................... 408
Error protection....................................... 450
Exception handling ................................... 59
Exception handling vector table................ 60
Exception vector table...............................60
Extended control register .......................... 23
External trigger ....................................... 422
Flash memory ......................................... 431
FOV ........................................................ 177
Framing error .......................................... 256
General registers .......................................22
Hardware protection................................ 450
Hardware standby mode.......................... 473
Host interface (LPC)............................... 367
I/O ports ....................................................95
I2C bus data format ................................. 307
I2C bus interface (IIC)............................. 277
ICI ........................................................... 177
ICIA ........................................................ 215
Rev. 1.00, 05/04, page 542 of 544
ICIX........................................................ 215
IICI ......................................................... 337
Immediate................................................. 42
Increment timing .................................... 170
Input capture input.................................. 172
Input capture operation........................... 212
Instruction set ........................................... 29
Interrupt control modes ............................ 80
Interrupt controller.................................... 67
Interrupt exception handling..................... 63
Interrupt Exception handling vector table 78
Interrupt mask bit ..................................... 24
Interval timer mode ................................ 229
Keyboard buffer controller ..................... 349
Logic operations instructions.................... 34
Mark state ............................................... 272
MCU operating mode selection................ 51
MCU operating modes.............................. 51
Medium-speed mode .............................. 470
Memory indirect ....................................... 43
Mode 2...................................................... 56
Mode 3...................................................... 56
Mode pins................................................. 51
Module stop mode .................................. 477
Multiprocessor communication
function................................................... 259
NMI interrupt.................................... 76, 230
Noise canceler ........................................ 335
Note on bit manipulation instructions....... 48
OCI ......................................................... 177
On-board programming modes............... 441
Operation field.......................................... 39
Output compare output ........................... 171
Overrun error.......................................... 256
OVI......................................................... 215
OVIAB ................................................... 215
OVIY...................................................... 215
Parity error .............................................. 256
Power-down modes................................. 463
Program counter........................................ 23
Program/erase protection ........................ 450
Program/program-verify ......................... 446
Program-counter relative .......................... 42
Programmer mode................................... 452
Pulse output ............................................ 169
PWM conversion period ......................... 149
RAM ....................................................... 429
Register direct........................................... 40
Register field............................................. 39
Register indirect........................................ 40
Register indirect with displacement.......... 41
Register indirect with post-increment ....... 41
Register indirect with pre-decrement........ 41
Registers
ABRKCR.............. 70, 483, 492, 500, 508
ADCR ................. 418, 487, 495, 503, 511
ADCSR............... 417, 487, 495, 503, 511
ADDR................. 416, 487, 495, 503, 511
BAR ...................... 71, 483, 492, 500, 508
BCR ...................... 93, 486, 494, 502, 510
BRR .................................................... 244
DDCSWR ........... 301, 483, 491, 499, 507
EBR1................... 440, 483, 492, 500, 508
EBR2................... 440, 483, 492, 500, 508
FLMCR1............. 438, 483, 492, 500, 508
FLMCR2............. 439, 483, 492, 500, 508
FRC..................... 160, 484, 493, 501, 508
HICR0................. 371, 481, 490, 498, 506
HICR1................. 371, 481, 490, 498, 506
HICR2................. 377, 481, 490, 498, 506
HICR3................. 377, 481, 490, 498, 506
HISEL................. 395, 481, 490, 498, 506
ICCR................... 289, 486, 495, 503, 511
ICDR................... 282, 486, 495, 503, 511
ICMR .................. 286, 487, 495, 503, 511
ICR....................... 69, 160, 483, 484, 492,
............................ 493, 500, 501, 508, 509
ICSR ................... 297, 486, 495, 503, 511
Rev. 1.00, 05/04, page 543 of 544
ICXR....................302, 482, 491, 499, 507
IDR ......................380, 481, 490, 498, 506
IER.........................73, 486, 494, 502, 510
ISCR ......................72, 483, 492, 500, 508
ISR.........................73, 483, 492, 500, 508
KBBR ..................354, 482, 491, 499, 507
KBCR ..................351, 482, 491, 499, 507
KMIMR .................73, 487, 496, 504, 512
KMIMRA ..............73, 487, 496, 504, 512
KMPCR ...............113, 487, 496, 504, 512
LADR3 ................379, 481, 490, 498, 506
LPWRCR.............465, 484, 492, 500, 508
MDCR ...................52, 486, 494, 502, 510
MSTPCR .............467, 484, 492, 500, 508
OCR.....................160, 484, 493, 501, 509
OCRDM ............................................. 161
ODR.....................381, 481, 490, 498, 506
P1DDR ................100, 485, 494, 502, 510
P1DR ...................100, 485, 494, 502, 510
P1PCR .................101, 485, 494, 502, 510
P2DDR ................102, 485, 494, 502, 510
P2DR ...................103, 485, 494, 502, 510
P2PCR .................103, 485, 494, 502, 510
P3DDR ................104, 485, 494, 502, 510
P3DR ...................105, 485, 494, 502, 510
P3PCR .................105, 485, 494, 502, 510
P4DDR ................107, 485, 494, 502, 510
P4DR ...................107, 485, 494, 502, 510
P5DDR ................110, 485, 494, 502, 510
P5DR ...................110, 485, 494, 502, 510
P6DDR ................112, 485, 494, 502, 510
P6DR ...................113, 485, 494, 502, 510
P7PIN ..................117, 486, 494, 502, 510
P8DDR ................118, 486, 494, 502, 510
P8DR ...................118, 486, 494, 502, 510
P9DDR ................122, 486, 494, 502, 510
P9DR ...................122, 486, 494, 502, 510
PADDR................125, 485, 494, 502, 510
PAODR................125, 485, 494, 502, 510
PAPIN..................126, 485, 494, 502, 510
PBDDR................129, 486, 494, 502, 510
PBODR................129, 485, 494, 502, 510
PBPIN..................130, 485, 494, 502, 510
PCDDR ............... 132, 482, 491, 499, 507
PCNOCR ............ 134, 480, 489, 497, 505
PCODR ............... 133, 482, 491, 499, 507
PCPIN ................. 133, 482, 491, 499, 507
PCSR................... 152, 483, 492, 500, 508
PDDDR............... 132, 482, 491, 499, 507
PDNOCR ............ 134, 480, 489, 497, 505
PDODR............... 133, 482, 491, 499, 507
PDPIN................. 133, 482, 491, 499, 507
PEDDR ............... 136, 482, 491, 499, 507
PENOCR............. 140, 480, 489, 497, 505
PEODR ............... 137, 482, 491, 499, 507
PEPIN ................. 138, 482, 491, 499, 507
PFDDR................ 136, 482, 491, 499, 507
PFNOCR............. 140, 480, 489, 497, 505
PFODR................ 137, 482, 491, 499, 507
PFPIN.................. 138, 482, 491, 499, 507
PGCTL................ 306, 480, 489, 497, 505
PGDDR............... 142, 482, 491, 499, 507
PGNOCR ............ 145, 480, 489, 497, 505
PGODR............... 143, 482, 491, 499, 507
PGPIN................. 143, 482, 491, 499, 507
PWDPR............................................... 151
PWDR................. 151, 486, 495, 503, 511
PWOER .............................................. 152
PWSL.................. 149, 486, 495, 503, 511
RDR .................................................... 237
RSR..................................................... 237
SAR..................... 283, 487, 495, 503, 511
SARX.................. 284, 486, 495, 503, 511
SBYCR ............... 464, 483, 492, 500, 508
SCMR ................................................. 243
SCR..................................................... 239
SIRQCR.............. 387, 481, 490, 498, 506
SMR.................................................... 238
SPSR ................................................... 249
SSR ..................................................... 241
STCR .................... 55, 486, 494, 502, 510
STR ..................... 381, 481, 490, 498, 506
SYSCR.................. 53, 486, 494, 502, 510
SYSCR2.............. 114, 483, 492, 500, 508
TCNT................. 191, 233, 485, 486, 493,
............................. 495,501, 503, 509, 511
Rev. 1.00, 05/04, page 544 of 544
TCONRI ..............203, 488, 496, 504, 512
TCONRS .............203, 488, 496, 504, 512
TCOR ..................191, 486, 495, 503, 511
TCORC................202, 488, 496, 504, 512
TCR ....................166, 192, 484, 486, 493,
.............................495, 501, 503, 509, 511
TCRAB............................................... 205
TCRXY .............................................. 204
TCSR ..................163, 196, 224, 484, 485,
............................486, 493, 495, 501, 503,
............................................ 508, 509, 511
TDR .................................................... 237
TICRF..................202, 488, 496, 504, 512
TICRR .................202, 487, 496, 504, 512
TIER ....................162, 484, 493, 501, 508
TISR ....................202, 488, 496, 504, 512
TOCR ..................167, 484, 493, 501, 509
TSR..................................................... 238
TWR ....................381, 481, 490, 497, 506
WSCR....................94, 486, 494, 502, 510
WUEMRB .............73, 482, 491, 499, 507
Reset ......................................................... 61
Reset exception handling.......................... 61
Resolution............................................... 149
ROM ....................................................... 431
Serial communication interface (SCI)..... 235
Serial formats.......................................... 307
Shift instructions....................................... 34
Single mode ............................................ 419
Sleep mode.............................................. 471
SMI ......................................................... 409
Software protection................................. 450
Software standby mode........................... 471
Stack pointer ............................................. 22
Stack status ............................................... 64
Subactive mode....................................... 476
Subsleep mode ........................................ 475
System control instructions....................... 38
Trap instruction exception handling ......... 63
User program mode ................................ 445
Watch mode............................................ 474
Watchdog timer (WDT).......................... 221
Watchdog timer mode............................. 227
WOVI ..................................................... 230
Renesas 16-Bit Single-Chip Microcomputer
Hardware Manual
H8S/2111B
Publication Date: Rev.1.00, May 14, 2004
Published by: Sales Strategic Planning Div.
Renesas Technology Corp.
Edited by: Technical Documentation & Information Department
Renesas Kodaira Semiconductor Co., Ltd..
2004. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon 1.0
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
http://www.renesas.com
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