PALASM_2_Software_Jul87 PALASM 2 Software Jul87

User Manual: PALASM_2_Software_Jul87

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PALASM 2
USER DOCUMENTATION

HAL~,

PAL®,
PALASM®,
Monolithic Memories, Inc.

and SKINNYDlp® are registered trademarks of

Double-Density PLUSTM Interface, PLETM, PLEASMTM, ZHALTM AND PROSETM are
trademarks of Monolithic Memories, Inc,
© Copyright 1978,1981,1982,1984,1985,1986,1987

Monolithic Memories, Inc .• 2175 Mission College Blvd .• Santa Clara, CA 95054-1592
(408) 970-9700· (910) 970-9700. (910) 338-2374

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PALASM 2
USER
DOCUMENTATION

MONOLITHIC MEMORIES
2175 Mission College Blvd.
Santa Clara, CA 95054-1592
(408) 970-9700

Version 2
Revision 5C
July 1987
©1987 MONOLITHIC MEMORIES, INC.

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Copyright Notice
Copyright 1984,1985, 1986,1987 by Monolithic Memories Inc.
The copying and distribution of this manual or the PALASM
software is encouraged for the private use of the original
purchaser provided this notice is included in all copies. No
commercial resale or outside distribution rights are allowed by
this notice. This material remains the property of Monolithic
Memories Inc. All other rights reserved by Monolithic
Memories Inc., 2175 Mission College Blvd., Santa Clara, CA
95054.

Monolithic

IFJJI Memories

Trademarks
PAL, HAL, PLE, ZHAL, PALASM and PLEASM are registered
trademarks of Monolithic Memories, Inc.
PROSE is a trademark of Monolithic Memories, Inc.
VAX and VMS are registered trademarks of Digital
Equipment Corporation.
TRI-STATE is a registered trademark of National
Semiconductor Inc.
IBM, IBM-PC, XT, PC Jr., 3083, PC DOS, and VM/CMS are
trademarks of IBM Corporation.
Data I/O and ABEL are registered trademarks of Data I/O
Corporation.
UNIX is a trademark of American Telephone and Telegraph.
Omni-Programmer is a trademark of Varix Corporation.
PAL Burner is a trademark of Structured Design Inc.
Wordstar is a trademark of Micro-pro.
MS-DOS is a trademark of Microsoft Inc.
DAISY and DNIX are registered trademarks of DAISY.

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DISCLAIMER
Monolithic Memories Inc. makes no representations or
warranties with respect to the contents within and specifically
disclaims any implied warranties of merchantability or fitness
for any particular purpose. Further, Monolithic Memories Inc.
reserves the right to revise this publication and the product it
describes and to otherwise make changes to the product
without obligation of Monolithic Memories Inc. to notify any
person or organization of such revision or changes.

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Preface
Audience
This manual is intended for design engineers who use
PALASMTM 2 to program PAL TM devices. The manual assumes
that you are familiar with PAL device technology and with
PAL device programming concepts.

Using This Manual
This manual steps you through installing PALASM 2 software,
and programming a PAL device. We suggest that you work
through the examples provided while reading the manual,
before proceeding with a design case of your own. All
communication with the computer is shown in MONACO
typeface.

PALASM 1 Software
In this manual, we refer to the original PALASM software as
PALASM 1. This is to distinguish it from the newer PALASM
2 software.

Other Documents
You should have a copy of the PAL Handbook. You should
also have vendor manuals for your computer and PAL
device programmer. If you are new to PAL devices as well as
to PALASM 2 software, you should obtain the booklet
Programmable Logic: A Basic Guide for the Designer, an
excellent introduction to PAL devices that is published by Data
I/O Corporation.

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Where to Get Help
Monolithic Memories maintains an Applications Hotline to assist
in solving engineering related problems. If you are having a
problem installing or running PALASM 2 software please call
the Hotline at 800-222-9323.

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TABLE OF CONTENTS
LIST OF TABLES ......................................................... xii
LIST OF FIGURES ........................................................xiii
SOFTWARE ERRATA .................................................. ERR-1

CHAPTER 1
INTRODUCTION
THE PAL DEVICE CONCEPT ........................................ 1-1
Programmable Logic Devices ............................ 1-1
INTRODUCING PALASM 2 SOFTWARE ........................ 1-6
REFERENCES .............................................................1-7
SUPPORTED PRODUCTS ........................................... 1-9
REQUIRED EQUIPMENT .............................................. 1-11
PROGRAM AND FILE SUMMARY .................................. 1-14
PALASM 2 SOFTWARE PROGRAMS ........................... 1-14

CHAPTER 2
INSTALLING PALASM 2 SOFTWARE
INTERACTIVE MENU AND NON-MENU MODES ............ 2-2
IBM-PC/XT/AT INSTALLATION ......................................2-3
TWIN FLOPPY SET-UP ................................................. 2-4
HARD DISK INSTALLATION .......................................... 2-6
CUSTOMIZE THE INTERACTIVE MENU ........................ 2-1 0
COMPUTER<->PROGRAMMER CONNECTION ............. 2-12

CHAPTER 3
PDS SYNTAX
IN THIS CHAPTER ........................................................3-1
PDS FILE STRUCTURE ................................................ 3-2

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CHAPTER 3A
BOOLEAN EQUATION DESIGN
DECLARATION SECTION .............................................3A-1
Structure ..........................................................3A-2
SyNTAX .......................................................................3A-3
BOOLEAN EQUATION INPUT.......................................3A-8
Combinatorial Equations ...................................3A-11
Registered Equations .......................................3A-12
Functional Equations ........................................3A-14
CHECKLIST FOR BOOLEAN EQUATION
DESIGN FILES .......................................................3A-22

CHAPTER 38
STATE MACHINE DESIGN
DESIGNING FOR PROSE DEViCES ..............................3B-4
MEALY AND MOORE MACHINES .................................3B-5
STRUCTURE AND SYNTAX ..........................................3B-5
DECLARATION SECTION .............................................3B-6
STATE SECTION .........................................................3B-9
STATE MACHINE EQUATIONS .....................................3B-14
State Equations ................................................3B-16
Output Equations .............................................3B-19
POWER_UP Equation ......................................3B-21
Condition Equations ......................................... 3B-24

CHAPTER 3C
SIMULATION
SIMULATION SYNTAX OVERVIEW ............................... 3C-2
DETAILS OF THE SIMULATION SYNTAX ....................... 3C-4
KEY POINTS TO NOTE .................................................3C-11
RULES FOR STATE MACHINE SIMULATION
SyNTAX .................................................................3C-12

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CHAPTER 4
USING PALASM 2 SOFTWARE
GENERAL PROCEDURE ............................................. .4-2
DESIGN EXAMPLES ................................................... .4-10
Boolean Equation Design ................................ .4-10
State Machine Design ...................................... .4-24

APPENDIX A
INSTALLATION AND OPERATION NOTES
IBM-PC I DOS 2.10 IMPLEMENTATION ......................... A-1
VAX-VMS IMPLEMENTATION ....................................... A-6
ASCII TAPE INSTALLATION ......................................... A-1 0
VAX-UNIX INSTALLATION ............................................ A-12

APPENDIX B
PROGRAMMER NOTES
DATA I/O ...................................................................... B-1
Using DATAI/O on VAX-VMS ............................. B-6
VARIX OMNI ................................................................. B-9

APPENDIX C
DEVICE SPECIFIC SYNTAX
PAL22RX8 AND PAL22V10
Special Instructions ........................................... C-2
PAL32VX10
Special Instructions ........................................... C-3

APPENDIX D
PAL DESIGN FILE LIBRARY
PAL DESIGN FILE L1BRARY .......................................... D-1

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APPENDIX E
ERROR MESSAGES
ERRORS REPORTED BY PALASM2 ............................ E-1
ERRORS REPORTED BY XPLOT ................................. E-2
ERRORS REPORTED BY MINIMIZE .............................. E-8
ERRORS REPORTED BY PROASM-PROSIM ................ E-17
ERRORS REPORTED BY ZHAL. ................................... E-30
ERRORS REPORTED BY SIM ....................................... E-32
ERRORS REPORTED BY JEDMAN .... ,.......................... E-34

APPENDIX F
SUBMITTING A HAL DESIGN TO MMI
MASTER DEViCE ......................................................... F-1
PAL DEVICE DESIGN SPECIFICATION ......................... F-1
FUNCTIONAL TEST VECTORS .................................... F-2

APPENDIX G
PALASM 2 SYNTAX DIAGRAM
DEFINITION OF TERMS ................................................ G-2
SYNTAX DIAGRAM .......................................................G-3

APPENDIX H
SUPPLEMENTARY SOFTWARE
PALASM ...................................................................... H-1
PDSCNVT .................................................................... H-1
DIFFERENCE BETWEEN PALASM 1 AND PALASM 2
SOFTWARE SYNTAX ............................................. H-2
PC2 .............................................................................H-3

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APPENDIX I
JEDEC STANDARD NO.3
PURPOSE ................................................................... 1-1
FORMAT DEFINITIONS ................................................. 1-2
OTHER RULES ............................................................ 1-10

RELEASE NOTES
IN THIS CHAPTER ........................................................ RNSUMMARY OF ENHANCEMENTS ................................. RNPALASM 2.22 DISK AND TAPE LAYOUT ...................... RNFIXED BUGS ................................................................ RN-

INDEX

1
2
3
23

••.••••••••••••••••••••••••.••••••..•••••••••••••.••..•.•••••• 1-1

DOCUMENTATION USER RESPONSE FORM
BUG/ENHANCEMENT REPORTS

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LIST OF TABLES
1-1
1-2
2-1
2-2
2-3
3-1
3A-1
3A-2
B-1
B-2
0-1

xii

PAL and PROSE Devices Supported by PALASM 2 Software ..... 1-1 0
PAL Device Programmers Supported by PALASM 2 Software ..... 1-13
Typical Transmission Parameters ............................................... 2-14
Command to Set Transmission Parameters ................................. 2-14
Commands to Display Programmer Output on Screen ................. 2-15
PALASM 2 Software Reserved Words .......................................3-3
Basic Operators ........................................................................3A-1 0
Results of Polarity Used in Figure 3A-4 .......................................3A-19
Recommended Baud Rate ........................................................B-2
Device Family Pin Codes For DATA I/O Programmer.................... B-3
Files Located On Design Examples Disk .................................... 0-2

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LIST OF FIGURES
1-1
1-2
1-3
2-1
2-2
3-1
3A-1
3A-2
3A-3
3A-4
3A-5
3A-6
38-1
38-2
38-3
38-4
38-5
38-6
38-7
38-8
38-9
38-10
38-11
38-12
38-13
38-14
38-15
38-16
38-17
38-18
38-19
38-20
38-21
38-22
38-23
38-24

Programmable Logic Devices .................................................... 1-2
Typical Computer Configuration ................................................. 1-12
PALASM 2 Software Flow ......................................................... 1-16
The Main Menu .........................................................................2-8
MENU.SYS ..............................................................................2-10
PDS File Structure ....................................................................3-2
Declaration Structure ................................................................3A-2
Example of the Declaration Section ............................................3A-3
Overview of Equation Syntax .....................................................3A-9
Pin List and Equations Section ..................................................3A-18
Signal Combinations and Output Polarity....................................3A-20
Summary of Output Polarities .................................................... 3A-21
General Synchronous State Machine Architecture ...................... 38-2
Moore 8ehavior ........................................................................38-3
Mealy 8ehavior .........................................................................38-4
Structure of a State Machine Design File ....................................38-6
State Machine Declaration Section .............................................38-8
Structure of Default Information ................................................. 38-11
Syntax for DEFAULT_OUTPUT Statement... ..............................38-13
Syntax for DEFAULT_8RANCH Statement ................................ 38-14
State Machine Equation Operators ............................................ 38-15
Syntax of State Equations .........................................................38-16
Simple State Equation and Diagram ...........................................38-17
State Equation with No Local Default... .......................................38-18
State Equation and Diagram from Traffic Controller Design ...........38-19
Moore Machine Output Equation Syntax .................................... 38-20
Output Equation Syntax ............................................................38-20
Mealy Machine Output Equation ................................................ 38-20
Moore Machine Output Equation ...............................................38-21
Syntax for POWER_UP State Equation ......................................38-22
Moore Machine POWER_UP Equation ......................................38-23
Syntax for Mealy Machine POWER_UP Output Equation ............ 38-24
POWER_UP State and Output Equations for Mealy Machine ....... 38-24
Sample Condition Equations .....................................................38-25
Mutually Exclusive Conditions ...................................................38-26
Conflicting Conditions ...............................................................38-26

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xiii

3C-1
4-1
4-2
4-3
4-4
B-1
1-1

xiv

PRLDF Statement ....................................................................3C-12
Device Programming Flowchart ................................................. .4-3
Traffic Intersection ....................................................................4-24
Traffic Signal Controller Logic Diagram ....................................... .4-25
State Diagram of the Traffic Signal Controller............................. ..4-26
Data 1/0 <-> VAX-VMS Cable Connection ................................... B-6
a-Bit Word Definition ................................................................. 1-6

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SOFTWARE ERRATA
i 3;1 ;1
Please read this list of known bugs before you
use PALASM 2 software. The following
problems occur with PALASM 2.22.

Disk Space

Insufficient disk space causes all PALASM 2
software programs to abort.

Interactive Menu

You require DOS 3.0 or later versions to install
and run the PALASM interactive menu. Run the
software in non-menu mode if you have earlier
versions of DOS.

State Machine Design
On A PAL Device

State machine input is being beta tested on
PAL devices. Therefore, it may not be fully
functional. State machine design entry can,
however, be successfully implemented on the
PMS14R21 PROSE device.

Output Equations On
Mealy and Moore
Machines

On a Mealy machine, you must define an
output for each state equation. Currently, you
must do the same on a Moore machine as well.
Otherwise, the software will produce errors.

Run MINIMIZE Before
XPLOT

For PAL devices, you must always run the
MINIMIZE program before the assembler on a
state machine design. If the MINIMIZE program
is not run, the assembler, XPLOT, will crash
when you try to compile your design.

POWER_UP
On PMS14R21

You are allowed only one (1) state branch from
the POWER_UP state instead of four.

Brief JEDEC Output

Before running PROASM, the PROSE

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ERR·1

ERR·2

PMS14R21

... IWARE

ERRATA

aS$embler, the PALASM2 program asks you if
you want a full or brief JEDEC output file. Select
full JEDEC output. The PROSE assembler
does not produce brief JEDEC output on the
PMS14R21.

PMS14R21 Fuse
Information

The PROSE assembler, PROASM, produces
an incorrect percentage value for the number of
fuses blown in the .XPT output file.

Parentheses in
Boolean Equations

If you use parentheses in your Boolean
equations, always run the MINIMIZE program
before assembling your design. XPLOT, the
assembler, will crash if it detects parenthesized
Boolean equations.

Minimizing XOR Devices

If you use an XOR equation in a Boolean design
and run the MINIMIZE program, the XOR will be
converted into functionally equivalent AND/OR
statements.

SImulating Flies
Without Filename
Extensions

Your input filename must have an extension,
such as dilename.PDS>. Without an
extension, the file will be parsed by the syntax
checker, PALASM2, but will cause SIM, the
simulator, to crash.

EeL Devices

PALASM 2 software treats I/O pins on ECL
devices as outputs only.

PAL32VX10

In a Boolean equation deSign on the
PAL32VX10, the 3-state I/O pin is defaulted as
an output.

PAL20X8

The PAL20X8 is not a preloadable device.
PALASM 2 software allows you to emulate a
PRELOAD, but no JEDEC is produced. Also,
the device will not be programmed correctly
without a PRELOAD.

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SOFTWARE ERRATA

PALASM 2 Software
Installation on
VAX-VMS

The logical directory name PAL2$DAT must
be assigned in the directory that contains the
PALASM 2 software. Refer to page A-7 for
instructions on assigning PAL2$DAT.

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13 ;1 ;1

ERR·3

SOFTWARE

ERR-4

ERRATA

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INTRODUCTION

THE PAL DEVICE
CONCEPT
A PAL device is a fuse-programmable logic device that can be
used to implement custom logic varying in complexity from
random gates to complex arithmetic functions. The PAL device
implements the familiar sum-of-products logic by using a
programmable AND array whose output terms feed a fixed OR
array. Since the sum-of-products form can express any Boolean
transfer function, the uses of the PAL device are limited only by
the number of terms available in the AND and OR arrays. Thus,
the PAL device combines much of the flexibility of the PLA with
the low cost and easy programmability of the PROM. Moreover,
PAL devices come in different sizes so that you can choose the
size that is most cost-effective for your applications.

Programmable Logic
Devices
PAL devices are one of three main types of programmable logic
devices:
*
*
*

PAL
PROM
FPLA

Programmable Array Logic
Programmable Read-Only Memory
Field Programmable Logic Array

All three kinds of devices include an array of AND gates whose
outputs feed an OR gate. The differences occur in the location
of the programming fuses. Figure 1-1 shows the basic
architecture of each kind of programmable logic device.

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1·1

INTRODUCTION

FPLA Architecture

PROM Architecture

AABBCC

A
PRODUCT TERMS

INPUTS

>
0
0
0

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'G-B-A

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C-ii-A

v-v-v-v--

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D-~

v-v-vvv-

INPUTS

PRODUCT TERMS

D-

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OUTPUT

-rv-

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f-------rv-FIXED AND

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PROGRAMMABLE OR

~
~
~

v:v-

PAL Device Architecture

vv-

AABBCC

INPU TS

':C:

P-

I>
PRODUCT TERMS
FO
F1
F2
F3
F4
F5
F6
F7
Fa
F9
F10
F11
F12
F13
F14
F15
F16
F17

v-v-v-

v-v--

vv-

b-t

v--

~~
~

0 UTPUT
V'

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V'
V'

D-

PROGRAMMABLE
AND

FIXEO OR

Figure 1-1:
Programmable Logic Devices

1·2

,.,-v-

---f>

f----'v-

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PROGRAMMABLE
OR

0 UTPUT

INTRODUCTION

PAL devices have fuses on the inputs to the AND gates. By
selecting the fuses to blow, you choose product terms available
to the OR gate. Usually several product terms are produced and
ORed for each output.
PROM devices have fuses on the outputs of the AND gates. All
possible product terms are produced; you choose the terms to
be applied to each output by deciding which fuses to leave
intact.
FPLA devices have fuses on both the inputs and outputs of the
AND gates. This is the most general configuration for
programmable devices.

PAL Device
Configurations
The members of the PAL device family combine the following
basic configurations: combinatorial arrays, programmable I/O,
registered outputs with feedback, exclusive OR (XOR), and
programmable polarity.
Combinatorial Arrays
PAL device combinatorial arrays are available in sizes from 64 x
32 (64 input terms maximum and 32 output terms maximum) to
16 x 2. Both active-high and active-low output configurations are
available. This wide variety of inpuUoutput formats allows you to
replace many different-sized blocks of combinatorial logic with
single PAL packages.
Programmable I/O
The high-end members of the PAL device family have
programmable I/O pins. This allows a product term to directly
control an output of the device. The product term is used to
enable the three-state buffer that gates the summation term to

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1·3

INTRODUCTION

the output pin. The output is also fed back into the PAL device
as an input. Thus the PAL device drives the I/O pin when the
three-state gate is enabled; the I/O pin is an input to the PAL
device when the three-state gate is disabled. This feature can
be used to allocate available pins for I/O functions or to provide
bidirectional output pins for operations such as shifting and
rotating serial data.

Registered Outputs with
Feedback
Another feature of the high-end members of the PAL device
family is registered outputs with registered feedback. Each
product term is stored into a D-type output flip-flop on the rising
edge of the system clock. The Q output of the flip-flop can then
be gated to the output pin by enabling the active-low three-state
buffer. The Q output is fed back into the PAL device as an input
term. This feedback allows the PAL device to remember its
previous state, and the PAL device can alter its function based
upon that state. This allows the designer to configure the PAL
device as a state sequencer that can be programmed to execute
such elementary functions as count up, count down, skip, shift,
and branch. These functions can be executed by the registered
PAL device at rates of up to 65 MHz for 0 PAL devices.

XOR

PAL Devices
These PAL devices feature an exclusive OR (XOR) function.
The sum of products is segmented into two sums, which are then
XORed at the input of the D-type flip-flop. All the features of
registered PAL devices are included in the XOR PAL device.
The XOR function provides an easy implementation of the HOLD
operation used in counters and other state sequencers.

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INTRODUCTION

Programmable-Polarity
PAL Devices
Programmable-polarity PAL devices allow a single part to function
as both an active-low and an active-high part. With the polarity
fuses intact, the outputs are active-low; when the polarity fuses
are blown, the outputs are active-high. If output 1 (OUT1) is
specified as uncomplemented in the pin list, and as
uncomplemented in the equations, the output is effectively
specified as active-high and the polarity fuse is blown.
The converse is also true. If OUT1 is complemented in the pin list
(/OUT1) and complemented in the equation, the fuse will be
blown. Whenever the polarities differ between the pin list and
the logic equation, the fuse will be left intact.

Hard Array Logic
Devices
A hard array logic (HALTM) device is the mask-programmed
version of a PAL device. A HAL device is to a PAL device what a
ROM is to a PROM. A standard wafer is fabricated up to the metal
mask. Then a custom metal mask is used to fabricate aluminum
links for a HAL device instead of the programmable titaniumtungsten (Ti-W) fuse array used in a PAL device. The HAL
device is a cost-effective solution for large quantities and is
unique in that it is a gate array with a programmable prototype.
For information on submitting HAL designs to Monolithic
Memories, see Appendix F of this manual.

PROSETM Devices
The PMS14R21 programmable sequencer is the first member of
the PROSE (PROgrammable SEquencer) family. The
PMS14R21 is a high-speed, 14-input, 8-output state machine. It
consists of a 128 x 21 PROM array preceded by a 14H2 PAL
array. The PAL array is efficient for a large number of input
conditions, while the PROM array is optimal for a large number of

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1-5

INTRODUCTION

product terms and states. The combination allows a very efficient
state machine with a large number of inputs and outputs. For
more information on the PMS14R21, refer to the datasheet in
the PAL handbook.

INTRODUCING
PALASM 2
SOFTWARE
PALASM 2 software is a package that turns PAL device Design
Specification (PDS) files into data files for PAL device
programmers. PDS is a format for specifying a PAL circuit and for
creating inputs to a logic circuit. Using a text editor, you create a
PDS file that describes a PAL circuit. PALASM 2
softwareaccepts the file as input and performs a number of
functions under your control, including:
*
*
*
*

Assembling PAL Design Specifications
Generating PAL device fuse patterns in JEDEC format
Reporting errors in syntax and assembly
Allowing concise mnemonic names for long, frequently used
logic expressions through string substitution

Functional Differences
from PALASM 1
Software
We refer to the original PALASM software as PALASM 1 software
to distinguish it from the new PALASM 2 software.
PALASM 2 software is quite different from PALASM 1 software in
implementation. It is composed of several interacting programs
coupled by disk files. (Floppy based files slow interaction. We
recommend RAM or hard disks for production use.) The
principle benefit of the reorganization is the freedom from fixed
limits within the design file.
As mentioned in the feature section, the syntax of PALASM 2

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INTRODUCTION

software is significantly different from that of PALASM 1.
PALASM 2 software allows description of asynchronous devices
like the PAL20RA 10 and devices of much higher complexity
such as MegaPAL devices.
The current version of PALASM 2 software omits several
features provided within PALASM 1. They are:
*
*
*
*
*

Fault coverage prediction for test vectors.
Automatic generation of documentation.
Device signal/pinout display.
Support of the security fuse.
Printing of logic equations for each product term in a
fuse plot.

Some of these omissions represent a change in philosophy;
others will be provided in later versions of the program.
For more detail on PALASM 1 software, refer to Appendix H.

REFERENCES
For further information about using programmable logic devices,
see the following references.

Software
1. Birkner, John M., "Macros for Programmable Logic," Wescon
Professional Conference Session Record, 1982.
2.

Birkner, John M., "High Level Language for Programmable .
Array Logic," Wescon Professional Conference Session
Record, 1981.

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INTRODUCTION

Birkner, John M., Coli, Vincent J., and Sackett, David M.,
"Design Your Own Chip With PALASM, Your Personal
Computer, and a PROM Programmer," Machine Design, July
1983, pp.81-85.

Birkner, John M., "CAD Methodology Parallels Advances in
Programmable Logic."

PAL Device
1. Birkner, John M. and Coli, Vincent J., "Hard Array Logic
Provides New TTL Standards," Southcon, 1982.
2.

Birkner, John M., "CAD Methodology Parallels Advances in
Programmable Logic," Electronica 1982.

Miller, Warren, "The Philosophies of Fuse Programmable
Logic," Wescon Conference Professional Session Record,
1982.

Miller, Warren, "New Developments in Programmable Logic,"
Wescon Conference Professional Session Record, 1982.

"Programmable Logic: A Basic Guide for the Designer," Data
I/O Corporation.

Edwards, E. and Greiner, J., "Programmable Logic Matches
Gate-array Density, Eases System Design." Electronic
Design, June 14, 1984.

PAL Device
Applications
1.

1·8

Coli, Vincent J., "PAL Bumps Eight Chips from
Microprocessor Interface," Electronic Design, November 25,
1982,pp.180-182.

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INTRODUCTION

Blasco, Richard W., "PALs Shrink Audio Spectrum
Analyzer," Electronic Design, August 20, 1980.

Coli, Vincent J., "Using a PAL to Emulate the Internal State
Counter of the MMI 'S516 LSI Multiplier/Divider," The Best
of the Computer Faires, Volume VIII, 1983.

SUPPORTED
PRODUCTS
With the exception of the PAL 16A4 and the PAL 16X4 parts,
PALASM 2 software supports all Monolithic Memories PAL
devices including new PAL products such as RA (Registered
Asynchronous), RS (Registered Synchronous), MegaPAL,
ZHALTM, as well as the newest and only member of the PROSE
family of devices.
Table 1-1 lists PAL and PROSE devices supported by PALASM
2 software.

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INTRODUCTION

Table 1-1:
PAL and PROSE Devices Supported by PALASM 2 Software

1-10

20-Pin
Devices

24-Pin
Devices

PAL10H8
PAL10L8
PAL12H6
PAL12L6
PAL14H4
PAL14L4
PAL16H2
PAL16L2
PAL16L8
PAL16P8
PAL16C1
PAL16R4
PAL16R6
PAL16R8
PAL16RA8
PAL16RP4
PAL16RP6
PAL16RP8
ZHAL20

PAL6L16
PAL32R16
PAL8L14
PAL64R32
PAL12L10
PAL14L8
PAL 16L6
PAL 18L4
PAL20L2
PAL20C1
PAL20L8
PAL20L10
PAL20X4
PAL20X8
PAL20X10
PAL20R4
PAL20R6
PAL20R8
PAL20RA10
PAL20S10
PAL20RS4
PAL20RS8
PAL20RS10
PAL22V10
PAL10H20P8
PAL 10H20G8
PAL32VX10
PAL22RX8
ZHAL24

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PROSE
Devices
PMS14R21

INTRODUCTION

REQUIRED
EQUIPMENT
This section describes computers and PAL device programmers
supported by PALASM 2 software and provides information
about necessary and optional PALASM 2 programs.

Computers
PALASM 2 software operates with no user modification on the
following CPUs, provided certain minimum system requirements
are satisfied. It is usually provided as an executable program,
ready to run on any of these systems:
Minicomputers:

V AXTM under VMSTM
VAXTM under UNIXTM (Berkeley 4.2)

Microcomputers:

IBM-PCTM, -XTTM, -ATTM
under MS-DOSTM (256K RAM)

Workstations:

DAISYTM under DNIXTM 5.1

All systems must have a serial port (RS-232) for communication
with the PAL device programmer. We also recommend that
floppy disk based systems be equipped with two disk drives.
Figure 1-2 shows a typical computer configuration.

Note: Refer to the PALASM 2 software order form for the
correct part number of the version of PALASM 2 software
designed for your CPU.

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INTRODUCTION

PALASM

l}---------l

PAL device
Programmer

Figure 1-2:
Typical Computer Configuration

PAL Device
Programmers
The PAL device programmers supported by PALASM 2 software
are shown in Table 1-2.

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INTRODUCTION

Table 1-2:
PAL Device Programmers Supported by PALASM 2 Software
Products

Manufacturer

DATAVO
Model 19 with LogicPak
DATA I/O
Model 29A or B with LogicPak
Adapter: 303A-002
303A-008 AlB for 32R16
303A-023 AlB for 64R32

DATA I/O
102525 Willows Rd. N.E
P.O. Box 97046
Redmond, WA 98073-9746

STAG ZL30/PPZ

STAG Microsystems
528-5 Weddell Dr.
Sunnyvale, CA 94089

DIGELEC FAM51 or FAM52

DIGELEC
1602 Lawrence Ave. #113
Ocean, NJ 07712

KONTRON MPP80S
KONTRON MOD21

KONTRON
1230 Charleston Rd.
Mountain View, CA 94039

VARIX OMNI PROGRAMMER

VARIX
1210 East Campbell Road #100
Richardson, TX 75081

STOREY SYSTEMS P240

Storey Systems
3201 North Hwy 67, Suite H
Mesquite, TX 75150

VALLEY DATA SCIENCES 160

Valley Data Sciences
2426 Charleston Business Pk
Mountain View, CA 94043

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1-13

INTRODUCTION

PROGRAM AND
FILE SUMMARY
Following is a summary of all currently available programs. A more
detailed description of each program follows this summary.
1.

PALASM2

PALASM 2 syntax parser

MINIMIZE

Logic expander and minimizer

XPLOT,SIM

PAL device assembler and simulator

PROASM-PROSIM

PROSE device assembler and
simulator

JEDMAN

JEDEC disassembler

ZHAL

ZHAL device fit

Note: The ZHAL utility is not part of the regular package you
get when you order PALASM 2 software. You may, however,
order the ZHAL program from your local Monolithic Memories
sales office.

PALASM 2
SOFTWARE
PROGRAMS
The main PALASM 2 software programs are described in the
following pages. Figure 1-3 shows the PALASM 2 software
processing flow.

PALASM2
PALASM2 is the first program you will use in the PALASM 2
software suite. It reads and validates your input-a PLD device

1·14

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INTRODUCTION

design specification-for correct design syntax. If an error is
detected, the program attempts to indicate where in the input
description the error has occurred. Recovery is attempted after
each error in order to catch as many errors as possible on a single
run. Only if no error is detected is an intermediate specification
file generated. This file contains the input specification in a hierarchically structured form to enable easy processing by follow-on
programs. Further, it is guaranteed to be syntactically correct.
This program recognizes input descriptions for all current PAL
devices.

MINIMIZE
The MINIMIZE program gives you the option of automatically
reducing your logic equations. Minimization helps to utilize the
space on your device more efficiently and is therefore a cost
effective feature. This program automatically translates a state
machine design file to Boolean equations. Although all PAL
devices are supported for logic minimization, the program does
not work effectively on Exclusive OR devices. This is because
XOR is treated as a complex logic element and is taken out
during minimization. A warning message is displayed on the
following Exclusive Or devices: PAL22RX8, PAL32VX10,
PAL20X10, PAL20X8, PAL20X4.

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INTRODUCTION

Boolean Equation
Input File

Logic
Minimization
JEDEC
Disassembly

Simulation

Assembly

JEDEC
Output
File

Fuseplot:
Output
File

A
U

Test Vectors:
Output File

History
and Trace
Output
Files

Figure 1·3:
PALASM 2 Software Flow

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INTRODUCTION

XPLOT
XPLOT validates the architectural design of an input PAL device
description and produces fusemaps and JEDEC data for a
specified PAL device. Input is a set of Boolean equations that
has been preprocessed by the PALASM2 program. XPLOT
checks the equations for consistency and correctness for the
specified PAL device. When an error is detected, XPLOT
attempts immediate recovery. In this way, XPLOT spots as many
errors as possible on each run. Only if no errors are detected will
the output fuse maps and JEDEC data be generated. The
architectural information for each PAL device is read in from a file
containing a profile description for the specific PAL device.

Note: XPLOT will check only valid Monolithic Memories PAL
devices.

SIM
SIM checks the functionality of a PAL device design. You will run
this program after XPLOT. If the design is architecturally correct,
however, you can run SIM directly after the PALASM2 program.
SIM reads a special simulation syntax that has been
preprocessed by the PALASM2 program. It will Simulate the
operation of the PAL device you specify, calculating the output
values based on input signals through the Boolean equations
and any feedback. SIM outputs two files: a history file and a trace
file. The history file shows the values of every pin through a
simulation sequence. The trace file, which is a subset of the
history file, shows only the pins you specify in the simulation
syntax. If XPLOT has been run and a JEDEC fuse address file
has been created, then SIM will add test vectors to the JEDEC
file that duplicate the simulation sequence when the device is
tested on a programmer. All JEDEC checksums are recalculated.

Note: SIM tests only valid Monolithic Memories PAL devices.

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INTRODUCTION

PROASM-PROSIM
PROASM and PROSIM assemble and simulate PROSE device
designs. PROASM accepts both State Machine and Boolean
logic designs. Assembly and simulation are both transparent to
the user. Please note that the only PROSE device PALASM 2
software currently supports is the PMS14R21.

JEDMAN
JEDMAN offers you the option of disassembling a JEDEC file
and generating Boolean equations. You can, in effect, read a
fuseplot directly from a programmed device. JEDMAN also
recalculates checksumsand allows you to convert a PAL22V10
JEDEC file to a PAL32VX10 JEDEC file

ZHAL
The ZHAL program helps you fit your completed PAL device
design into a 20-pin or 24-pin ZHAL (Zero-standby-power CMOS
HAL) device. If you plan to opt for volume production using
Monolithic Memories ZHAL devices, ensure quick turn-around by
letting the ZHAL program match your design to make it fit into the
device. If your device fits, you may send it to Monolithic
Memories for mask processing.

Note: The ZHAL utility is not part of the regular package you
get when you order PALASM 2 software. You may, however,
order the ZHAL program from your local Monolithic Memories
sales office.

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INTRODUCTION

Supplementary
Software
Following is a summary of all currently available supplementary
software. A more detailed description of some of the
supplementary programs follows this summary.
1. PALASM

PALASM 2 interactive menu

2. PDSCNVT PALASM 1 to PALASM 2 syntax conversion
3. PC2

Programmer interface program

4. SCRSIM

Simulation waveform generation program

5. VTRACE

Sim output files to timing diagrams conversion

6. BINHEX

Binary to hexadecimal conversion

7. TIMING

Timing diagram entry program

8. PINOUT

Pinout Program

9. DECODE

Address Decoder Program

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INTRODUCTION

PALASM 2
Supplementary
Programs
Some of the supplementary programs listed on the previous
page are described below. Please note that Monolithic
Memories does not support all the programs that reside on the
supplementary disk.

PALASM
PALASM is the name of the interactive menu program that is
designed to simplify user interface to the software. The program
may be installed on an IBM-PC -XT -AT, either twin floppy or hard
disk. The user-friendly menu screens display your options on
one screen, enable the use of function keys to run all the
programs in the software suite, and allow you to view the output
as well. The PALASM menu significantly reduces your learning
curve since all you need to know is what you want to do, not how
to do it. Online help screens and message windows facilitate
easy interaction with the software.

PDSCNVT
PDSCNVT allows you to interactively convert PAL device design
specifications from the PALASM 1 format to PALASM 2
software. Input is a PALASM 1 formatted specification file, and
output is the equivalent design in PALASM 2 software syntax.

PC2
PC2 enables communication between PLD programmers and
IBMTM PC machines (-PC, -XT, -AT, etc.). It is a menu-driven
multiple-choice program that guides you through various options
for programming and checking PLDs.

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INTRODUCTION

VTRACE
VTRACE reads the trace output of the PALASM 2 software
simulator. The text-formatted data of the trace file is converted
into graphic form. VTRACE output looks very much like timing
diagrams of the simulation results.

Files
Input, output, and intermediate files (files that the software
creates but are not visible to the user) are listed below.
1. . PDS

User defined PLD design description
input.

PALASM2.TRE

PLD intermediate design description.

.PDF

PLD architecture description data.

4. .XPT

Contains PLD fuse map data.

5. .JED

Contains PLD fuse JEDEC data.

6. .HST

Contains full simulation history data.

7. . TRF

Contains user simulation trace data.

.JDC

Contains both PLD fuse JEDEC data
and JEDEC test vectors.

9. .PL2

Contains PDS file reconstructed from
JEDEC output.

10..JDM

Recalculated checksums or PAL22V10
to PAL32VX10 conversions using
JEDMAN.

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INTRODUCTION

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INSTALLING PALASM 2
SOFTWARE
This chapter tells you how to get started. Refer to the
appropriate page number for the computer and operating system
on which you are running PALASM 2 software.

IN THIS CHAPTER
If you have a...

Refer to...

IBM-PC/XT/AT

2-3

VAX-VMS

Appendix A-6

VAX-UNIX

Appendix A-12

VAX-ASCII

Appendix A-10

PALASM 2 software can be run using either an interactive menu
interface or in non-menu mode. Decide which mode you would
prefer to use. The instructions for installation include the set-up
procedure for both modes.

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IN:'; I ALLINu PALASM 2 SOFTWARE

INTERACTIVE
MENU AND NONMENU MODES
PALASM 2 software can be run using the interactive menu or in
non-menu mode.

Interactive Menu
We recommend the use of the user-friendly menu interface for
both first-time and advanced users. If you are a first-time user,
the interface will considerably reduce your learning curve.
Advanced users may also find that the menu screens facilitate
easy interaction with the software.
The interactive menu resides on your Supplementary diskette.
To use the interactive menu, you need to go through a one time
installation procedure. Once the program is successfully
installed, it will always be the first screen that is called up. You
may use the interactive menu only if you have MS-DOS 3.0 or
later versions. The interactive menu installation procedure for
each computer and operating system is described in the
following pages.

Non-Menu Mode
This is recommended for advanced users only. Also, if you do
not have MS-DOS 3.0 or later versions of MS-DOS, you must use
the software in non-menu mode. In this mode, you merely type
commands to activate programs directly from DOS. Instructions
for preparing your system to run PALASM 2 software in nonmenu mode follow in the next few pages.

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IBM-PC/XT/AT
INSTALLATION
What You Require
To install PALASM 2 software, you require.

1. An IBM-PC/XT/ATwith either twin floppy drives or a hard disk.
2.

IEII

Minimum memory of 384K bytes
to run the software in menu mode
or
minimum memory of 256 K bytes to run the
software in non-menu mode.

3. DOS 3.0 or later versions to run the software in
menu mode.
4. An IBM-DOS diskette.
5.

PALASM 2 software on regular or high density diskettes.

6. A blank diskette if you are using a twin floppy system.
Note: If your system does not have 384K bytes memory or DOS
3.0 (or later versions). you must use the software in non-menu
mode.

If you have a...

Refer to...

Twin Floppy System

Page 2-4

Hard Disk

Page 2-6

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INSTALLING PALASM 2 SOFTWARE

TWIN FLOPPY
SET-UP
A few simple steps enable you to set-up your twin floppy system
to run PALASM 2 software.

Create A Work
Diskette
First, you need to create a WORK diskette to store your design
files.
1.

Insert the IBM-DOS diskette in drive B.

Insert a blank diskette in drive A.

Note: If you have a 1.2 megabyte floppy in drive A, remember to
use a high density diskette.
3.

Enter
B:

Enter

FORMAT A:/S
Now you have a WORK diskette that contains the
COMMAND.COM file.
5.

When you see the system message

FORMAT ANOTHER?
Enter
N

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INSTALLING PALASM 2 SOFTWARE

Load The
Supplementary
Software
Now you are ready to load the Supplementary Software.
1.

Enter

Insert the Supplementary diskette in drive B.

If you wish to use PALASM 2 software's interactive menu,
enter

FLOPPY2 +MENU
Or, if you wish to use PALASM 2 software in non-menu
mode, enter

FLOPPY2 NOMENU
At this point you will see further instructions on your screen.
Follow these instructions to complete the installation. Turn to
page 2-7 to find out if the menu is properly installed.

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INSTALLING PALASM 2 SOFTWARE

HARD DISK
INSTALLATION
Follow these steps to install the software on your hard disk.
1.

Insert the Supplementary Software disk in drive A. (Use drive
A on an AT as well.)

Enter
A:

Enter
PAL2INST
Follow the instructions on your screen to complete the
installation procedure.

Reboot your system after the installation is complete.

To test that PALASM 2 software is installed in menu mode,
turn to page 2-7 for further instructions.
To use PALASM 2 software in non-menu mode, turn to page
2-9 for further instructions.

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INSTALLING PALASM 2 SOFTWARE

Interactive Menu
Run A Test Example
After you have completed the installation procedure, run a test.
1. To call up the program, enter
C: P ALASM
2.

Now you will see the first screen of the PALASM2 interactive
menu.
Next, press again.
Your screen now displays the main menu as shown in Figure

2-1.

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INSTALLING PALASM 2 SOFTWARE

PALASM V2.22 (c)MONOLITHIC MEMORIES,SANTA CLARA,CA 95054 FEB 28,1987

Input PDS file
Device

dummy

PAL20RA10

.pds
F1

Directory

DisplayDir

C:\
DOS Command

PALASM 2
F3

EdttPDS

Program Device

PALASM

F6 Install Menu

MENU
WINDOW
F7 ViewData

Supplementary

KEY MOVEMENTS
PRESS F9 FOR HELP

= exit
=refresh
= delete
= insert

... =

previous position

.. =

next position

+= next field

= previous field

= first field
= last field

STATUS: ALL OK

Figure 2·1: The Main Menu

Congratulations! You have successfully installed PALASM 2
software in interactive mode on your hard disk. Remember, to
call up PALASM 2 software, type

PALASM

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INSTALLING PALASM 2 SOFTWARE

Non-menu Mode
Modify System File
To install PALASM 2 software in non-menu mode, you must
modify the AUTOEXEC.BAT file.
1.

Open the AUTOEXEC.BAT file.

Add the following two lines to the end of the file.

IEIII

PATH :\PALASM2\PAL2;%PATH%
DPATH :\PALASM2\PDF;:\PALASM2\MSG;
:\PALASM2\SUPL;
3.

Reboot the system.

Run A Test
After you have installed PALASM 2 software in non-menu mode,
run a test. To activate each of the PALASM 2 programs, you
must type the program name. The complete list of programs is
given below.
PALASM2
MINIMIZE
XPLOT
SIM
PROASM
PROSIM
JEDMAN
For a description of each program, refer to page 1-14.
Congratulations! You have successfully installed PALASM 2
software in non-menu mode on your hard disk.

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INSTALLING PALASM 2 SOFTWARE

CUSTOMIZE THE
I NTE RA CTIVE
MENU
You may customize the interactive menuprogram with a one-time
set-up procedure so that from the main menu you can

Easily access supplementary programs

This feature enables you to go directly from the main menu to the
program of your choice without accessing DOS.
The installation procedure is stored in the file MENU.SYS. Each
time you call up the interactive menu, the software reads the file
MENU.SYS. Therefore, to customize the interactive menu, you
must modify MENU.SYS.
The format of your MENU.SYS file is shown in Figure 2-2.
C
\PAL2\

C
\SUPL\

Program
Path
Data

C
\PDF\
C
\MSG\

C
Editor
Data

\PAL2\ED

C
EXE

C
\PAL2\PC2
EXE

Programmer
Data

DUMMY

Input File
Name

PDS
$PINOUT.COM

I'--____~.

User
Customization

Figure 2·2: MENU.SYS

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INSTALLING PALASM 2 SOFTWARE

Any change you make to the file must occur after the Input File
Name (see Figure 2-2).

Add a Program to the
Supplementary
Programs List
Supplementary programs supported by Monolithic Memories can
be called up from the main menu by choosing the supplementary
program option. You may activate more programs from the main
menu by adding the program names to the menu system file
MENU.SYS. For a complete list of the supplementary programs
that you may add to the system file, refer to page 2-12.

IEJI

The procedure to add a program to the MENU.SYS file follows.
1.

Enter the text editor.

Open the MENU.SYS file.

To the end of the file, add the filename of the Supplementary
program in the following format.
$
For example, to add the program PINOUT, you enter

$PINOUT.COM
4.

Save the file.

That's all. To test the modification, call up the interactive menu
program. The Fa option will now allow you to call up the
Supplementary program you have added.

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INSTALLING PALASM 2 SOFTWARE

Software Programs On
The Supplementary
Diskette
Following are the programs for which direct access from the main
menu is not available. Turn to page 2-11 for the procedure that
allows you to call up these programs from the main menu.
SCRSIM.COM

Simulation Waveform Generation Program

VTRACE.COM

A Utility Program To Print Sim Output Files
As Timing Diagrams

BINHEX.COM

A Binary To Hexadecimal Conversion
Program

TIMING.COM

Timing Diagram Entry Program

PINOUT.COM

Pinout Program

DECODE .COM

Address Decoder Program That
Generates PALASM2 Boolean
Equations

COMPUTER<->
PROGRAMMER
CONNECTION
Because a large number of hardware combinations are possible,
this manual cannot give detailed instructions or cabling
information. Consult the manuals supplied with the computer
and the programmer. Read also the general configuration
information below for your type of computer.

IBM-PC
The usual practice with PCs is to connect the programmer to a
serial port. In MS-DOS, the serial ports have the device names

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INSTALLING PALASM 2 SOFTWARE

COM1: and COM2:. For computers using add-on boards with
serial I/O ports you may need to set switches on the board or the
PC's mother board. To use the communication commands in the
rest of this manual, you need to know the device name of the
port the programmer is connected to.

VAX Minicomputers
Many terminals such as the VT-100 have a serial port that echoes
the information displayed on the terminal screen. Connect the
programmer to this port. (Confirm interface with your computer
operations department to avoid damage to the terminal.) When
you want the information displayed on the screen to go to the
programmer as well, you just have to turn on the programmer and
put it in receive mode.

Verifying the
Communications Link
To verify the communications link, you can usually send a simple
memory dump from the PAL device programmer to the
computer. Because PAL device programmers differ in the way
that they accept data files, we can only describe a general
procedure here. Refer to the manual supplied with the PAL
device programmer for specific information.
The general procedure for establishing the communications link
is as follows:
1.

Set the transmission parameters for the programmer. Refer
to the programmer manual for specific information. Typical
parameters are shown in Table 2-1.

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INSTALLING PALASM 2 SOFTWARE

Table 2-1:
Typical Transmission Parameters

Parameter

Typical Setting

baud rate
number of data bits
number of stop bits
parity

1200, 2400, or 4800

7
1
even

Set the same transmission parameters for the computer.
The appropriate command for each operating system is
shown in Table 2-2.
Table 2-2:
Command to Set Transmission Parameters

Operating System

Co~mand

MODE (see NOTE
following)
Example: MODE
COM1 :4800,N,8,1
SET TERM

MS-DOS

VMS

Note: If you are using an IBM PC and a DATA I/O PAL programmer,
the supplementary program PC2 is an effective way to connect these
systems. PC2 sets the transmission parameters for the IBM PC and
establishes the communications link. Appendix A describes how to
verify the communications link for this combination of devices.
3.

2·14

Prepare the computer to receive information from the
programmer. The easiest way is to set the computer to
display on the terminal screen whatever is received on the
serial port. The typical procedures are shown in Table 2-3.

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INSTALLING PALASM 2 SOFTWARE

Table 2-3:
Commands to Display Programmer Output on Screen
Notes

Command

System
MS-DOS

COpy COM1: CON:

VMS

CREATEdilename>

May be COM2: on
some systems (See NOTE)
Captures programmer output in
filename. End transmission
with Z.

Note: If you are using the DATA 110 and IBM PC, use PC2 and
do Select E1 on the DATA I/O. If the DATA I/O menu appears
on the IBM screen, the communications link is working.
4.

Dump part of the RAM contents of the programmer to the
serial port. Nearly all programmers can do this. If the
communications link is working, you should see the
characters on the computer terminal screen.

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PDS SYNTAX

The first step in using PALASM 2 software is for you to create a
design file. To create your design file, you use a text editor such
as WordstarTM or EdlinTM. Your design file contains the specifications that PALASM 2 software uses to program a PAL or
PROSE device. We refer to the design file as the PAL device
Design Specification It is important to remember the acronym
PDS because it is used as the filename extension for your design
file. This chapter describes the syntax and structure for each of
the two kinds of PDS files that PALASM 2 software accepts:
Boolean equation design and state machine design.

IN THIS CHAPTER
For a description of...

Refer to page...

Boolean Equation Design

3A-1

State Machine Design

3B-1

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3·1

t'U::S ::SYNIAA

PDS FILE

STRUCTURE
Your input file may be in Boolean equation design or State
Machine design. Both kinds of input files must be named
dilename.PDS> and have the following structure.

Declaration Section

Boolean Equations
or
State Section

Simulation

Figure 3-1: PDS File Structure

This chapter provides detail on how to create both kinds of input
files using the generic PDS structure shown above. For
information on simulation, turn to Chapter 3C, Simulation.

3-2

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PDS SYNTAX

Table 3-1:
PALASM 2 Software Reserved Words

AUTHOR
BEGIN
CHECK
CHIP
CLKF
CLOCKF
CMBF
COMPANY
CONDITIONS
DATE
DECLARATION
DEFAULT_BRANCH
DEFAULT_BRANCH HOLD_STATE
DEFAULT_BRANCH NEXT_STATE
DEFAULT_OUTPUT
DO
ELSE
END
EQUATIONS
FOR
GND
IF
MASTER_RESET
MEALY_MACHINE
MOORE_MACHINE

NC
OR
OUTPUT_ENABLE
OUTPUT_HOLD
PATTERN
POWER_UP
PRLDF
REVISION
RSTF
SETF
SIMULATION
STATE
STRING
THEN
TITLE
TRACE-OFF
TRACE-ON
TRST
VCC
WHILE

All MMI programmable logic device types are reserved words; for
example, PAL16R8 and PMS14R21.

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3·3

PDS SYNTAX

3-4

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W "'emorle.

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3A. BOOLEAN
EQUATION DESIGN
DECLARATION
SECTION
Function
You use the Declaration section to document information about
the designer and part, to define pin assignments, and to define
string names.

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3A·1

BOOLEAN EQUATION DESIGN

Structure
The structure of the Declaration section is shown in Figure 3A-1.

Keyword

Data

TITLE

PATIERN

REVISION

AUTHOR

<designer's name>

COMPANY

DATE

CHIP

STRING

Figure 3A-1: Declaration Structure

CAUTION: CHIP is the only required keyword without which a
fuse plot will not be generated. If you omit any of the other key
words you will see a warning message, but the compiler will
continue to generate a fuse plot.
Figure 3A-2 shows an example of the Declaration section.

3A·2

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BOOLEAN EQUATION DESIGN

TITLE
PATTERN
AUTHOR
COMPANY
DATE

This is an example to
illustrate the syntax
ABC1234 MMI REVISION 000ABC1234
John Doe
Monolithic Memories Inc.
July 5, 1986

CHIP

PAL20RS10

;PINS 1
CLK
;PINS 7
NC

2
3
4
5
6
ONE /TWO THREE SET RESET
10
12
11
NC WRITE READ GND

8
NC

17
NC

18
NC

;PINS 13
14
15
JOE OUT1 OUT2

16
NC

;PINS 19
20
/ACK /MMI

22
23
24
NC MEMADR VCC

21
NC

STRING INITIALIZE 'RESET * ONE
STRING REQUEST '/RESET * WRITE

/TWO'
MEMADR'

Figure 3A-2: Example of the Declaration Section

SYNTAX
The following items are general rules of PDS syntax.
1.

Comments may be inserted freely, and must begin with the
semi-colon character (;).

Line length is 128 characters; all characters beyond this limit
are ignored.

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3A·3

BOOLEAN EQUATION DESIGN

Data item name length is 24 characters; further characters
are ignored.

Data identifiers can be any upper or lower case alphanumeric
text including spaces, tabs and underscores.

Do not use these special characters: ! @ # $ % " & * (
) - = + { }[] " - : " < > ? ,. The slash key (I) is used to denote
active-low signals.

All control characters (including tabs) are treated as a single
space.

Aside from these general syntactical rules, there are no special
considerations for the use of the keywords TITLE, PATTERN,
REVISION, AUTHOR, COMPANY, DATE. The keyword CHIP is a
required part of the declaration section of a PDS file. The keyword
STRING is an optional part of the declaration section with special
syntactical considerations.

CHIP
CHIP is the keyword necessary to start the pin list information.
CHIP <chip name> <device type><pin list>
Example:

CHIP OCTAL LATCH PAL10H20P8 Al, ... VCC

Chip Name
A description of the circuit. For example, OCTAL_LATCH.
Any alphanumeric word up to 14 characters containing a letter.
The <chip name> is a required parameter and must be provided
before the <device type> field is specified.

3A·4

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BOOLEAN EQUATION DESIGN

If you intend routing your design through ZHAL, you may specify
the ZHAL device of your choice here. You may specify ZHAL20,
ZHAL24, or ZHAL24_20. (ZHAL24_20 utilizes the 24-pin
architecture for a 20-pin design.) If you do not spell out a device
name in this section of your design file, the ZHAL program will
choose an appropriate one for you by default.

Device Type
The device type is the part number of the supported PAL or
PROSE device manufactured by Monolithic Memories.
PAL devices with different speed/power options are given the
same generic name. For example: PAL 16R8, PAL 16R8A,
PAL16R8A2, PAL16R8A4, and PAL16R88 all have the same
generic name PAL 16R8.

Pin List
A list of signal names that you assign to the pins of the device.
When you are assigning signal names you must keep the
following pOints in mind.
1.

Signal names cannot exceed 14 characters in length. The
first character must be a letter; the remainder may be letters,
numbers, or underscores. For example: 1, 2, 3, ... is an
illegal pin list, but p1, p2, p3, ... are legal pin lists.

Signals can be specified as active-low or active-high. Activelow signals are preceded by / (fA is an active-low signal).

Signal names are separated by spaces or commas.

Special pins of the device are assigned special names. The
power pin is assigned vee and the ground pin is assigned
GND. These names should come at the appropriate places in
the pin list. For example, in PAL20R8, pin number 24 is

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3A·5

BOOLEAN EQUATION DESIGN

VCC, and pin number 12 is GND. If any pin is not used, it
must be specified as NC (no connect).
5.

Pins are listed in the order expected for DIP (dual in-line
package), regardless of whether you are planning to
eventually program DIP, LCC or Chip Carrier devices. Any
pin reordering for other packages must be done by the
programmer or other special fixture. The PAL64R32 device
pinout is specified for an 84-pin package.

Note: Do not use the reserved words shown in Table 3-1, or the
MMI programmable logic device types as chip signal names.

String
STRING is the keyword that introduces string identifiers in the
Declaration section of the PDS file. The keyword must be
repeated for each identifier.
STRING <string name> '<text to be substituted>'
Example:

STRING LOAD ' LD * /CIN '
STRING CARRY , /LD * /SET * /SET
STRING INPUT ' Al + /A2 + A3 '

3A·6

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* CUP ,

BOOLEAN EQUATION DESIGN

String Name
The string name is a user-defined name of up to 14 alphanumeric
characters. This name has to be unique, which means that it
should not be a reserved word, one of the signal names defined
in the pin list, or one of the string names used elsewhere.

Text to be Substituted
This is any legal expression specified within single quotes.
The text to be substituted can be of any length, must follow the
syntax rules of the pin name identifiers, and must be delimited by
blanks or tabs.
To eliminate repeated typing of a frequently needed block of text
when writing the Functional Description of the circuit, you can
declare that block with an alphanumeric identifier. Then, instead
of typing the full text you can use the identifier as necessary.
You can also use previously defined string names in the string
declaration.
Example:

STRING INPUT ' Al + /A2 + A3 '
STRING OUTPUT ' LOAD * CARRY ,
You can currently use a maximum of 20 unique strings within any
design file.
String substitution is textual replacement, and the compiler does
not try to find any logical meaning to it. You should be very
specific in what you want to substitute. Using the example given,
if in the equation section there is an occurrence of

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3A·7

BOOLEAN EQUATION DESIGN

/INPUT
Then after substitution the resulting expression will be

/AI + /A2 + A3
not

(AI + /A2 + A3)

because DeMorgan Expansion is not performed on string
expressions. If the latter meaning is what you want, your string
definition should be

STRING INPUT '

(AI + /A2 + A3)

BOOLEAN
EQUATION INPUT
Function
You give all the implementation details of an application in the
Equations section of the PDS using Boolean equations. This
information will be used to generate the locations of the fuses to
be disconnected during programming of the part.

Structure
The beginning of the Equations section is denoted with the
keyword EQUATIONS. The remainder of this section consists of
Boolean equations that have the general structure:
SIGNAL NAME assignment operator TRANSFER FUNCTION
Depending on the nature of the output signal being described,
there are three basic types of equations used:

3A·8

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mill Memorle.

BOOLEAN EQUATION DESIGN

*
*
*

Combinatorial
Registered
Functional

The syntax of the Equations section, as it is applied to these
three equation types, is shown in Figure 3A-3.
CAUTION :Any signal name used in the Equations section must
be declared first in the Declaration section.

EQUATIONS
(Keyword marking the beginning of functional description)

Combinatorial Equation:
<signal> = Function «signal>, <operator»

Registered Equation:
<signal> := Function «signab, <operator»

Functional Equation:
<signal> . <sfunc>

= Function «signal>, <operator»

where
<signal>
<operator>
<stunc>

is the name of a pin from the pin list
is a basic operator ( I, *, +, :+: )
is a special function associated with the output
signal.

Figure 3A-3: Overview of Equation Syntax
The basic operators you use are shown in Table 3A-2. They
perform INVERT, AND, OR, and Exclusive-OR operations. These
operators can be used to describe any logic function on the right
side of the equation using sum-of-products form logic notation.

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3A·9

BOOLEAN EQUATION DESIGN

Table 3A-1:
Basic Operators

INVERT is used whenever a signal has to be inverted.
It precedes the signal to be inverted.
/A means not A

AND is used when ANDing two or more Boolean
variables. The operation of ANDing all the signals
results in a product term.
A * IB * C means A and (not 8) and C

OR is used when ORing two or more product terms
andlor signals.
A + IC means A or (not C)

:+:

EXCLUSIVE-OR is used when exclusive - ORing
two or more product terms and/or signals.
A :+: E means A exclusive-or E
OPERATOR PRECEDENCE:

I, * , + , :+:

The specific use of combinatorial, registered, and functional
equations will now be described.

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Memories

BOOLEAN EQUATION DESIGN

Combinatorial
Equations
Combinatorial equations are identified by the operator =.
Because combinatorial output requires no clock, outputs are
based on the inputs.
output = <product term> + <product term> +...
where
<product term> .. is composed of <signal> * <signal> * ....
<signal> is represented by a declared pin name or
complement.
Example:

CHIP POLARITY EXMPL PAL16P8
;PINS 1
A

3
C

4
D

2
7
NC

8
NC

9
NC

10
GND

;PINS 11
Y

Iz w

15
NC

;PINS 16
NC

17
NC

19
NC

20
VCC

;PINS 6

18
NC

EQUATIONS
Y

IZ
Iw
V

A
E
E

* B + IC * D
* F + IF * IE

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3A·11

BOOLEAN EQUATION DESIGN

The signal on the left of = is the output for which the equation is
described. This output signal can be active-high (output) or
active-low (/output).
On PAL devices with programmable polarity, the polarity fuse is
programmed or left intact according to the polarities given on the
left side of the equation and those used in the pin list. When
these two
polarities are the same, the fuse is programmed, giving an activehigh output. When the two polarities differ, the fuse is left intact,
leaving the output active-low.
In the example, equations for outputs Y and Z have the same
polarity as in the pin list. On a programmable-polarity part (eg.
PAL 16P8), the polarity fuse would be programmed. On an
active-low part (eg. PAL 16L8), this would be an error.
The outputs Wand V have polarities that are the reverse of those
specified in the pin list, so the polarity fuse is left intact. The
programmable-polarity feature allows you to describe the
function in either active-low or active-high state. You do not have
to transform the function using De Morgan's theorem. Refer to
page 3A-17 for more information on polarity.

Registered Equations
Registered equations are identified by the operator

:=.

These equations are described for outputs with a register. For
example: Each output of the PAL 16RP8 device is a registered
output.
output

:= <product term> + <product term> + ...

where
<product term> ..is composed of <signal> * <signal> * ....
<Signal> is represented by a declared pin name or
complement.

3A·12

IWonoIlthlt:

Memories

BOOLEAN EQUATION DESIGN

Example:

CHIP POLARITY EXMPL PAL16RP8
;PINS 1
CLK

2
A

;PINS 6

4
C

5
D

8
NC

9
NC

10
GND

;PINS 11
Y

;PINS 16
NC

17
NC

w
18
NC

15
NC

19
NC

20
VCC

EQUATIONS
Y:= A
E
E
V:=/F

Iz:=
Iw:=

*
*

B +
F +

Ic * D
IF * IE

The signal on the left side of := is the output described by the
equation.
The clock to the register in most cases is a special clock pin (e.g.,
on the PAL16RP8 device, pin number 1 is the clock pin). On
the PAL20RA1 0 device the clock is generated by a special
product term described in a CLKF functional equation on the
PAL20RA10.
The transition at the output of the register takes place on the
rising edge of the clock.
This output signal can be active-high (output) or active low
(/output).

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3A·13

BOOLEAN EQUATION DESIGN

On programmable-polarity parts, the polarity fuse is programmed
or left intact according to the polarity given on the left side of the
equation and that used in the pin list. When they are the same,
the fuse is programmed, which means the signal is not inverted;
when they differ the fuse is left intact, which means the signal is
inverted.
The programmable polarity feature allows you to describe the
function in either active-low or active-high state. You do not have
to transform the function using De Morgan's theorem.
Refer to page 3A-17 for a discussion on polarity.

Functional Equations
Certain PAL devices, such as the PAL20RA10, have the
following programmable functions for registers:

*
*
*

Set
Reset
Clock
Three-state

These functions are represented by special equations in which
the keyword of the special function is a suffix to the signal name:
<output.sfunc> = <product term>
Example:

OUT.CLKF

The left side of the equation identifies the function for the output
defined by the right side of the equation. In the example this
means that product term A * B controls the Clock function of the
output OUT. Because these functions use only a single product
term, the OR (+) operation cannot be used. Order of appearance
in a PAL Design Specification is not significant for functional
equations.

3A·14

BOOLEAN EQUATION DESIGN

The programmable functions are described below.

SETF: The programmable
SET Function
RSTF: The programmable
RESET Function
On the PAl20RA10, it is always possible to bypass the register
by making the SET and RESET product terms high. There are
two ways of doing this. One way is to be explicit, as follows:
OUT:=A + IB +D* E
OUT.SETF = VCC
OUT.RSTF = VCC
OUT.CLKF = GND

;Output defined as registered

The other way is to be implicit, as follows:
OUT = A + IB + D * E; Output defined as combinatorial
In the implicit case, the program XPlOT will take care of the
default conditions for SETF, RSTF and ClKF.
In some cases, you might not want to use the SET and RESET
functions. Being explicit:
OUT :=A+/B
OUT.SETF = GND
OUT.RSTF = GND
OUT.CLKF = ClK
Being implicit:
OUT:= A+/B
OUT.ClKF = ClK
The program XPlOT will take care of the default conditions and
program the appropriate fuses.

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3A·15

BOOLEAN EQUATION DESIGN

Default for PAL20RA 10
If the output is defined as combinatorial: the default value is
VCC. If the output is defined as registered: the default value is
GND.

CLKF: The Programmable
Clock Function
If the output is defined as combinatorial, then it is has no ClKF.
XPlOT will indicate an error if ClKF is defined.
Only the PAl20RA10 has a programmable clock. If the output
on the PAl20RA10 is defined as registered, then ClKF must be
defined. Otherwise, XPlOT will produce an error. (Define as
GND to disable.)

Defaufts
GND (clock absent)

TRST: The Programmable
Three-State Function
The default for the three-state function is VCC. You can specify
this explicitly as:
OUT :=A+B
OUT.ClKF = ClK
OUT.TRST = VCC
or implicitly by not specifying the three-state function.
The XPlOT program will program all the fuses.

3A·16

IIIIonoIIthic

miD Memories

BOOLEAN EQUATION DESIGN

Defaults

vee (output enabled)
Polarity
It is important to remember that on most programmable polarity
parts, the polarity fuse is located in front of the register and
affects the inversion of the data path. The data path is the output
of the OR gate through the polarity fuse and into the register. It
does not affect the set or reset function of the output.
If no output equation is defined, the polarity fuse is left intact.

Output Polarity
An output can be defined as active-high or active-low. To
achieve the desired polarity on an output, the signals in your
PDS design file must be defined correctly. We will now look at
the factors that determine the polarity of an output.
Two factors determine the polarity of an output:
1. The signal in the pin list.
2.

The occurrence of the same signal on the left side of the
operator in a Boolean equation.

We will discuss the relative polarity between the signal in the pin
list and the same signal in the Boolean equation.
The pin list, which is in the Declaration section of your PDS file, is
where you define pin names for the input and output pins on the
device. You write Boolean equations in the Equations section of
your PDS file.

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3A·17

BOOLEAN EQUATION DESIGN

Figure 3A-4 shows an example of the pin list and Equations
section of a PDS file.

CHIP POLARITY EX PAL16P8
;PINS 1
11

2
12

3
13

4
14

5
/15

;PINS 6
/16

7
NC

8
NC

9
NC

10
GND

Signal as
User Defined
Pin Name

;PINS

12
/01 /02

Signal in
Boolean
Equation

EQUATIONS

;PINS 16
NC

r>Q=+
/02
/03
04

11
/13
15
+ /16
15
/16

17
NC

*
*
*
*

13
03
18
NC

14
/04

15
NC

19
NC

20
VCC

12
14
16
/15

Figure 3A-4:
Pin List and Equations Section

The example in Figure 3A-4 shows that on pin 11 , while the
signal in the pin list is active-low (101), the signal in the Boolean
equation is active-high (01). This results in the output polarity
being active-low (/01). The result is summarized in Table 3A-2.

3A·18

Monolithic

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BOOLEAN EQUATION DESIGN

Table 3A-2:
Results of Polarity Used In Figure 3A-4
Output Polarity
Active-low
101

Pin List

Boolean Equation

Active-low

Active-high

101

We have just seen that the relationship between the signal in the
pin list and the signal in the Boolean equation has a direct
bearing on the polarity of the output pin. To achieve the desired
output polarity, you must define the signals in the pin list and
Boolean equation appropriately.
How is this done? The chart in Figure 3A-5 contains every
possible combination of signals in the pin list and the Boolean
equation along with the resultant polarity of the output. Use the
chart as a guide when defining signals in your PDS design file.

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3A·19

BOOLEAN EQUATION DESIGN

Boolean
Equation

""""""""""",
... ,"""""""""'"
"""""""""""""""""""""""
"""""""""""""""""""""""
"""""""""""""""""""""""
"""""""""""""""""""""""
""',.... ,"", ...,""""""""""""""'"
""~l~"""""""""~~~""'"
""
... ,"""""""',.... . """"
""'"
""
""""""""',.
"""""""""""""""""""""""
,',""""""""""""""""""""'"
"""""""""""""""""""""""
"""""""""""""',
,""", ,""'"
......
"""""""""'~"""""~"""""'"
"""""""""""""""""""""""
"""""""""""""""""""""""
"""""""""""""""""""""""
"""""""""""""""""""""""
... " ... , ... , ......,,",, ... ,""""""',
,"', ... ,"', ......,",,",
... , , ... , ...,'
,""',
,'
""......... ,"" ........., "" ...,,',, ,"",
... ,"",
,',
... " ......... , ...... ", ".........
,'
, ,",
," ",""',
,"""',
,............
,
"
...
,"",
,"""',
......
...
,",
............
, ...,
..., ","',
...... ,"',
......
,
"
,"",
...
"
,"",
...
,',
,
.........
,'"
.....................,
"
"
... " ......... , , ,
... ' ......... '. . . '~l~
"" ".... ................
,'............
. .",...~~
. . " ...,",
. .' . ."'. .,' "..........
."""
. .... .". ........ .
... "
..., .....................
"................
...... , .........
, ...............
, ......,"", ," ,,'",,
,"',
...............
,
, ,........................
,...............
............," .........,"',,...........................
, ,",
, ...............
,......""............
, " ......
,.........
,',
.........
,.........,,...,",
,
......
,
,""',
......
,
"
,',
......
,
,......,......
, ,, ............
... ,.........,, ...............,"',
, ,.........,',
, ............"" ...,,......,',
............,...............
,',......, ,
...

...

Pin List

...

.........

...

...
...

...
.........

............ ... ...... ...
.........
............
...... ......
...
...
...
.....................
..............................

...

...
............

....................................

OOm"t1~
......... , . u"
" ,. .
.........

...

~~!~!'t~t

...

..................
.........
...
...

...

......
...
...
...
...
....................................... ...... ... ..............................
....................................................................................... ....................................... ......
......
...........................
.........
.....................
......
...
...
...
...
...
......
...
...
......
......
...
...............
.........
......

Figure 3A-S:
Signal Combinations and Output Polarity

Let us try and use this chart. If we want the output polarity to be
active-high, one possible combination would be /S in the pin list
and /S in the Boolean equation.
Note: While any combination in Figure 3A-5 works on a
programmable polarity device, PALs such as PAL 16L8 and
PAL 16R4 do not accept the same polarity in both the pin list and
the Boolean equation. The combinations these devices accept
are /8 in the pin list and 8 in the Boolean equation or vice versa.
Figure 3A-6 summarizes all possible combinations.

3A-20

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BOOLEAN EQUATION DESIGN

;PINS

13
01

;PINS

19
07

14
02

15
/03

20
08

21
09

16
/04

17
05

010

011

18
06
24

vee

EQUATIONS
;For active-low output
/01:= <expression> ;01 is high in the pin list,
;low in the Boolean equation
03:= <expression> ;03 is low in the pin list,
;high in the Boolean equation
;For active-high output
02:= <expression> ;02 is high in the pin list,
;high in the Boolean equation
/04:= <expression> ;04 is low in the pin list,
;low in the Boolean equation

Figure 3A-6:
Summary of Output Polarities

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3A·21

BOOLEAN EQUATION DESIGN

CHECKLIST FOR
BOOLEAN EQUATION
DESIGN FILES
1.

Is the PAL device design file free of control characters
such as form feeds, and was it created as a clean ASCII file?

Does the keyword CHIP appear before the design name,
PAL device type, and pin-list information?

Does the keyword EQUATIONS preface all Boolean
equations used?

Have you defined all strings to be used as logical
replacements for terms in the Boolean equations?

On 20-pin PAL devices, is GND specified as pin 10 and
VCC as pin 20? On 24-pin PAL devices, is GND specified
as pin 12 and VCC as pin 24?

If you are specifying an active-low PAL device, is the Signal
name on the left-hand side of the equation the logical
opposite of the signal name specified in the pin list? Are
the signal names the same for active-high parts?

Are you within the maximum number of product terms for
any output?

Are you specifying .TRST equations for outputs with threestate buffers only?

Are you specifying .CLKF equations for PAL20RA10
designs only?

10.

3A·22

Are all comments preceded by a semicolon (;)?

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BOOLEAN EQUATION DESIGN

11 . Does the last line in your input file terminate with a hard
carriage return? (Omitting this carriage return will cause the
program to craSh.)
12. If you do NOT have any errors during assembly, check
your fuse plot and JEDEC output for the following:
a)

Is the number of product terms per equation correct?

b) With xyz.TRST=VCC specified for a three-state buffer,
are ALL fuses programmed on the three-state line? If
that output is being used as an input, are all fuses intact?
c)

For PAL devices with programmable polarity, are the
polarity fuses correct as expected?

d) For PAL devices with product-term sharing, are the
sharing fuses correct? Product-term sharing fuses are
present in the fuse plots for MegaPAL, PAL20S10,
PAL20RS4,8,10 devices as the two unlabeled columns
of fuses at the right. They allow a pair of outputs to
exclusively share a changeable fraction of the product
terms available for the bank.)
e) For PAL devices with register bypass (MegaPAL), are the
proper outputs bypassed?

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BOOLEAN EQUATION DESIGN

3A·24

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38.

STATE MACHINE
DESIGN

Note: State machine design entry is fully functional on the
PMS14R21 PROSE device. Because it is currently being beta
released for PAL devices, this chapter does not contain
references to PAL devices. Future versions of PALASM 2
software and documentation will include state machine design
entry for all Monolithic Memories PAL, PROSE, and PLS
devices.

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3B·1

STATE MACHINE DESIGN

Before discussing PALASM 2 software's state machine syntax,
we will define a state machine and its basic operation.
A state machine is a digital device that cycles through a
sequence of states in an orderly fashion. A state is a set of
values measured at different parts of the circuit.
Figure 3B-1 illustrates how a synchronous state machine is
implemented in PALASM 2 software.

,..

Input

...
::,...

....

...,...
.......

Combinatorial
Logic

Behavior

Output := function
(state, input)

Output

= function
(state, input)

.......

Mealy

State
Transition

...,....

Combinatorial
Logic

Moore

Behavior

.......

Output := function (state)

........

Output = function (state)

Output is valid after the active edge of the clock

Figure 3B-1:
General Synchronous State Machine Architecture

38·2

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STATE MACHINE DESIGN

Notice that two models are available. These are referred to as
Mealy and Moore behavior models. When the output is purely
a function of the current state, the state machine displays Moore
behavior. Refer to Figure 3B-2 for an illustration of Moore
behavior.

Output= function (state)

FIgure 3B·2:

Moore Behavior

If the output is a function of inputs, the state transition, and the
current state, the state machine displays Mealy behavior. In
Mealy mode, PALASM 2 software allows either combinatorial or
registered outputs to be declared. Refer to Figure 3B-3 for an
illustration of Mealy behavior.

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38·3

STATE MACHINE DESIGN

Output = (Out1, Out2)
Output = function (state, input)

Figure 3B-3: Mealy Behavior

The basic ingredients of a state machine design are:
*

a list of state names

a list of conditions that cause state transitions

a list of outputs

DESIGNING FOR
PROSE DEVICES
Currently, a PROSE device best implements a state machine
design. The circuitry in a PROSE device is designed to
efficiently implement a state machine definition. State machine
designs are not yet fully functional on PAL devices.

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STATE MACHINE DESIGN

MEALY AND
MOORE MACHINES
In your design, you need to indicate which type of state machine
you will use. Pages 3B-2 to 3B-4 and Figures 3B-1 to 3B-3
demonstrate both Moore and Mealy behavior. Study your device
logic diagram and decide which model is best suited to your
design.

STRUCTURE AND
SYNTAX
Now that we have gone over the concept of a state machine as it
is implemented in PALASM 2 software, we will discuss creating a
state machine design file. Your design file is created using any
text editor.
If you are familiar with the PAL design specification (PDS) using
Boolean equations, you will find the structure of the state
machine design to be very similar.
A complete state machine design begins on page 4-24. We will
step through the sections of a state machine design using parts
of the same traffic controller example.
Before you begin to create your design file, study the device's
logic diagram in the PAL Handbook. After you have studied and
understand the device circuitry, you are ready to begin creating
your design file.
Your state machine design must have the structure shown in
Figure 3B-4.

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38·5

STATE MACHINE DESIGN

Declaration Section
State Section
Default Information
State Machine Equations
Condition Equations
Simulation Section

Figure 38-4:
Structure of a State Machine Design File

We will define each section of the state machine design file
beginning with the declaration section.

DECLARATION
SECTION
Declaration Section
State Section
Default Information
State Machine Equations
Condition Equations
Simulation Section

The declaration section consists of names and titles: initial
documentation about your design. It also includes some
information about the device for which the design is intended.

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STATt:

MAt;HINI:.

UI:.::tll:lN

The structure of the declaration section for both a state machine
design and a Boolean equation design is the same. For further
detail on the structure of this section, refer to page 3A-1.
Suppose you are designing with the PMS14R21 , a PROSE
device, to design a traffic controller. Figure 3B-5 shows how the
declaration section would look.

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38·7

-=»

110\ 1 C

IVIIo\\"nll>of1:

UI:~luN

TITLE
PATTERN
REVISION
AUTHOR
COMPANY
DATE
CHIP

TRAFFIC CONTROLLER
STATE MACHINE
1
JANE ENGINEER
MONOLITHIC MEMORIES
JANUARY 30, 1987
S MACHINE PMS14R21

;PINS

1
2
CLOCK DCLOCK

3
4
5
SENl SEN2 12

;PINS

7
14

10
17

;PINS

17
18
14 15
16
13
RESET SDO REDl YELl GRNl RED2

;PINS

19
YEL2

8
15

9
16

21
20
GRN2 01

/2
00

11
SDI

12
GND

23
24
MODE VCC

Figure 38-5:
State Machine Declaration Section

In Figure 38-5, the CHIP statement consists of the following:

38·8

Required keyword: CHIP

Chip name: S_Machine

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6
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STATE MACHINE DESIGN

Device name: PMS14R21

Pin list

To completely define the pin list, refer to the circuit design in the
PAL Handbook. For each pin you intend using in your design,
you must assign a pin name in the Declaration section. Pin
names are user defined. For further information on pin names
and polarity conventions, refer to pages 3A-5 and 3A-17.

STATE SECTION
Declaration Section

State Section
Default Information
State Machine Equations
Condition Equations
Simulation Section

The state section follows the declaration section. The
information you put in the state section determines how the
device is to be physically configured.
The state section is divided into three parts:
1.

Default Information: The state section begins with the
keyword STATE. This is followed by a block of information
that tells the software what kind of machine you are
designing and the defaults to use when either the next state
or the outputs cannot be determined from the equations.

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3B·9

STATE MACHINE DESIGN

State and Output Equations: This part of the state
section contains your equations that specify what conditions
cause movement from each current state to a next state. You
also specify what local default becomes the next state if no
condition is defined.

Condition Equations: The last part of the state section
begins with the keyword CONDITIONS. This is followed by
condition equations.

We will discuss the three parts of the state section in the
following pages.

Default Information
Declaration Section
State Section
Default Information
State Machine Equations
Condition Equations
Simulation Section

The structure of the default information part of the state section is
shown in Figure 38-6.

3B·10

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STATE MACHINE DESIGN

STATE
(required keyword)
MOORE_MACHINE

MEALY_MACHINE
(default)

OUTPUT_ENABLE

MASTER_RESET
(default)

<output pin name(s»
DEFAULT_OUTPUT

DEFAULT_BRANCH

Figure 38-6:
Structure of Default Information

STATE
STATE is the required keyword marking the beginning of the
state section.

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3B·11

STATE MACHINE DESIGN

MOORE MACHINE or
MEALY MACHINE
MOORE_MACHINE or MEALY_MACHINE indicate the type of
behavior model for which you are designing. Mealy machine is
the default.

OUTPUT ENABLE or
MASTER RESET
On a PROSE device, you have two options for configuring the
outputs:
*
*

OUTPUT_ENABLE (fuse programmable)
MASTER_RESET (default)

If you select the fuse programmable OUTPUT_ENABLE option,
the ..E.resetiOutput ,Enabie (PiE) pin enables the outputs when
low, and three-states the outputs when high.
When you select the MASTER_RESET option, the

Ereset/Output Enable (PIE) pin causes all output registers to go
high asynchronously. This puts the device in POWER_UP state.
(For more information on POWER_UP, refer to page 3B-21.)

OUTPUT _HOLD
You use OUTPUT_HOLD to list those pin names whose output
registers retain their values on a transition from the current state
to the next state. This occurs only when no new value can be
determined from the output equations.

3B·12

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::iTA I t:.

IVIAvnll'fC:

UC:;;:JI\':II'O

DEFAULT_OUTPUT
The DEFAULT_OUTPUT statement lists default values for each
output pin when no value can be determined from the output
equations. The pin can default to high, low, or don't care. The
three ways to indicate what default value an output pin will have
are listed in Figure 38-7.
<pin name>

indicates that the pin
defaults to high

I<pin name>

indicates that the pin
defaults to low

%<pin name>

indicates that the pin
defaults to don't care

Figure 38-7:
Syntax for DEFAULT_OUTPUT Statement

List a pin in either the OUTPUT_HOLD or DEFAULT_OUTPUT
statements, but not in both. If a pin is listed in both statements,
the software will use the statement appearing last.

DEFAULT_BRANCH
You use DEFAULT_8RANCH to specify the state to which the
machine will go when no next state can be determined from your
design. Your three options are listed in Figure 38-8.

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3B·13

DEFAULT_BRANCH <state name>

Go to the state
specified
Hold in the current
state
Go to the next state
listed in the design file

Figure 3B·8:
Syntax for DEFAULT_BRANCH

Statement

STATE MACHINE
EQUATIONS
Declaration Section
State Section
Default Information

State Machine Equations
Condition Equations
Simulation Section

Now that we have discussed the default information, we will
discuss state machine equations. This part of the state section
consists of state transition and output equations that provide
detailed instructions on how the state machine will operate.
For each state you must define the following:
*

3B·14

State name

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STATE MAliMINI::.

UI::..::m,:I\'\I

Next states that are reachable from that state

Conditions under which a transition from that state to the
next state can occur

Outputs

State Machine
Equation Operators
State equations are formed using the operators shown in Figure
38-9.
->

state transition

next condition

+->

default state transition

Figure 3B-9:
State Machine Equation Operators

Rules for State
Machine Equations
Remember the following rules when writing your state machine
equations:
1.

Use the conditions that are defined in the CONDITIONS part
of the state section to trigger state or output transitions.
Condition equations follow the state and output equations in
the state section of your design file,

2. Do not use parentheses in your equations to
group either state names or conditions.

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I PI. II:.

IVIPl.~MINt:

Ut:::iIl:iN

State machine syntax uses three types of equations:
*

State Equations

Output Equations

Condition Equations

State Equations
State equations describe the transitions from the named state to
the next state. They may also detail the conditions that trigger
transitions.
The syntax for a state equation is shown in Figure 38-10.

Figure 38-10:
Syntax of State Equations

38·16

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STATE MACHINE DESIGN

Figure 38-11 illustrates a simple state equation with a state diagram.

STATEO:= XYZ -> STATE2 +-> STATEO

Figure 38·11:
Simple State Equation and Diagram

The equation in Figure 38-11 says: when in STATE 0, if condition XYZ is true, go to STATE 2; otherwise stay in STATE O.
STATE 0 is the local default next state.
The equation and diagram in Figure 38-12 show an example that
does not specify a local default next state.

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3B·17

STATE MACHINE DESIGN

STATE1:=

XYZ -> STATE2 + ABC -> STATE3

Figure 38-12:
State Equation with No Local Default

The equation in Figure 3B-12 says: when in STATE 1, if
condition XYZ is true, go to STATE 2, or if condition ABC is true,
go to STATE 3. Notice the absence of a local default next state.
This indicates the presence of a DEFAULT_BRANCH statement
in the default information section. The equation implies that
when neither condition XYZ nor ABC is true, go to the
DEFAULT_BRANCH next state.
Figure 3B-13 shows a diagram for an equation taken from the
traffic controller design starting on page 4-24.

3B·18

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STATE MACHINE DESIGN

80:= C3 -> 81 + CO -> 81 +
C1 -> 82 +-> 80
Figure 38-13:
State Equation and Diagram from Traffic Controller
Design

The equation in Figure 38-13 says: when in state 0 (SO), if
condition C3 is true, go to state 1; or if condition CO is true, go to
state 1; or if condition C1 is true, go to state 2; otherwise, stay in
state O.

Output Equations
Output equations describe the outputs you expect from each
state (Moore state machine) or the outputs you expect on
transitions to next states (Mealy state machine).
Moore Machine: Output:=Function (State)
Mealy Machine: Output:=Function (State, Transition)

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3B-19

STATE MACHINE DESIGN

The syntax for a Moore machine output equation is given in
Figure 38-14.

<STATE.OUTF>:=

Figure 38-14:
Moore Machine Output Equation Syntax
The syntax for a Mealy machine output equation is given in
Figure 38-15.

<STATE.OUTF>:=

Figure 38-15:
Output Equation Syntax

Figure 38-16 shows a diagram and equation for outputs on
transitions, and is therefore meant for a Mealy state machine.

STATE1.0UTF:=

XYZ

+->

Figure 38-16:
Mealy Machine Output Equation

38·20

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*
02

/02
/03

STATE

MACHIN~

U~~luN

The equation in Figure 3B-16 says: on a transition from STATE 1,
if condition XYZ is true, output 01 will be high and
output 02 will be low; and since nothing is defined for output 03,
it will be determined by the OUTPUT_HOLD and
DEFAULT_OUTPUT statements. If condition XYZ is false,
outputs 01 and 02 will be high, and output 03 will be low.

Figure 3B-17 shows an output equation and diagram for a Moore
machine taken from the traffic controller example starting on page

4-24.

SO.OUTF .- GRNl

RED2

Figure 38-17:
Moore Machine Output Equation

The equation in Figure 3B-17 says: the output expected for state
is GRN1 and RED2 are true.

POWER_UP Equation
The POWER_UP equation is the first equation of your set of
state and output equations.
The PROSE machine goes to the POWER_UP state upon
initialization. The purpose of the POWER_UP equation is to
specify what state the machine will enter during POWER_UP

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38-21

STATE MACHINE DESIGN

initialization. This is the same state the machine enters when
the.P/E pin is asserted low. (See page 38-11.)
Figure 38-18 shows the syntax for the POWER_UP state
equation.

POWER_UP := VCC -> <state name>

Figure 38-18:
Syntax for POWER_UP State Equation

You will notice that only one next state is specified. Currently,
PALASM 2 software allows only one next state from
POWER_UP.

POWER_UP For Moore
And Mealy Machines
On a Moore machine, the POWER_UP equation is a state
equation. Figure 38-19 shows an example of a POWER_UP
state equation for a Moore machine.

38·22

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STATE MACHINE DESIGN

POWER UP .-

vee ->

STATEO

Figure 3B-19:
Moore Machine POWER_UP Equation

In the example, the pin
to the specified state.

vee defines an unconditional transition

On a Mealy machine, you need to have a state and an output
equation for POWER_UP. The state equation is exactly like the
POWER_UP equation for a Moore machine.
A Moore machine does not require an output equation for the
POWER_UP state.
A Mealy machine requires an output equation to specify what
output you need on the transition to the next state. The syntax
for a Mealy machine POWER_UP output equation is shown in
Figure 38-20.

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3B·23

STATE MACHINE DESIGN

POWER_UP.OUTF:= <OUTPUT> .. .* ... <OUTPUT> ...

Figure 38-20:
Syntax for Mealy Machine POWER_UP Output
Equation

80th POWER_UP state and output equations for a Mealy
machine are shown in Figure 38-21.

POWER UP := vee -> STATEO
POWER UP.OUTF .- 01 * 02 */03

Figure 38-21:
POWER_UP State and Output Equations for Mealy
Machine

Condition Equations
Declaration Section
State Section
Default Information
State Machine Equations
Condition Equations
Simulation Section

38·24

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STATE MACHINE DESIGN

The third part of the state section is introduced by the required
keyword CONDITIONS and follows the state and output
equations. Condition equations define conditions used in the
state section. These conditions are used to determine whether
transitions occur (Moore or Mealy) and whether outputs change
(Mealy only).
Figure 38-22 shows condition equations from the traffic
controller design starting on page 4-24.

CONDITIONS
CO
Cl
C2
C3

=
=
=
=

/SENl
/SENl
SENl
SENl

*
*
*
*

/SEN2
SEN2
/SEN2
SEN2

E):I

Figure 38-22:
Sample Condition Equations
This block begins with the keyword CONDITIONS.
Next, each condition used in the state section is defined in a
condition equation. Each equation sets a condition equal to a
sum-of-products of device inputs.
Rules for Condition
Equations
1.

Do not use parentheses to group terms in your condition
equations.

2. The conditions that govern either state or output transitions
from the same current state must be mutually exclusive. If
they are not mutually exclusive, the transitions will conflict.

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3B-25

STATE MACHINE DESIGN

An example of mutually exclusive conditions is shown in
Figure 38-23.

CONDl
COND2

11 * 12 * 13
/11 * 14

Figure 38-23:
Mutually Exclusive Conditions

Conflicting conditions occur when two or more conditions may be
true at the same time. An example of conflicting conditions is
shown in Figure 38-24. Notice that conditions COND1 and
COND2 are not mutually exclusive; both conditions may
simultaneously be true when 11 is high.

CONDl
COND2

11
11

*
*

12
14

Figure 38-24:
Conflicting Conditions

Where conflicting condition equations exist and both conditions
become true, conflicting transitions result and the next state or
output will be undefined.

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STATE MACHINE DESIGN

SIMULATION
Declaration Section
State Section
Default Information
State Machine Equations
Condition Equations

Simulation Section

The simulation section is the last part of the design specification.
Simulation is discussed in Chapter 3C.

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3B·27

STATE MACHINE DESIGN

38·28

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3C.

SIMULATION

After you have defined the logic of your function in terms of
equations, you need to be able to verify that the equations do
implement the required function. Hence, simulation is a very
important part of any design cycle. The basic feature of any
simulation is the ability to give a trial set of input values to your
design and check the resulting outputs for correctness.
PALASM 2 software provides you with this ability.
In general, logiC simulation can be described using

PRLDF, SETF, CLOCKF, TRACE_ON, TRACE_OFF, and
CHECK commands.

a FOR <variable> DO loop to iterate a set of commands a
fixed number of times.

a WHILE <condition> DO loop also to iterate a set of
commands till the condition is false.

an IF <condition> THEN ELSE for conditional branching.

PALASM 2 software has an Event-Driven Simulatorsupporting all
the different PAL device architectures, both asynchronous and
synchronous. The program is designed so that internal events
generated by asynchronous/synchronous feedbacks and
external events you generate are simulated in a very realistic
way. Oscillatory conditions are also detected and reported to the
user. Conflict in the expected and the actual value of any signal
is an error, which is detected by the simulator and reported to the
user. The simulation continues from that point using the actual
value of the Signal.
The PALASM 2 software language has simulation commands
which are English-like words, thereby making the simulation

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3C·1

SIMULATION

specification very natural to read and understand. Facilities exist
for iterative looping, conditional branching, setting of signals,
checking of signal values, and selective observation of signals.
All these commands will be explained in this section. All the
simulation results are stored in two files: a history file
«filename>.HST) and a trace file «filename>.TRF). The history
file contains the values of all the Signals from the start of
simulation to the end. The trace file contains the values of the
signals mentioned in TRACE_ON statements and between
these and following TRACE_OFF statements.
The simulation results are organized in a horizontal format
resembling a timing diagram. Each page contains 40 vectors. A
maximum of 512 vectors are allowed with this release of the
simulator. Corresponding to each SETF and CLOCKF
statement in the simulation a g or c appears on the horizontal axis
in the result files. A CLOCKF statement causes the clock to go L
to H to L. The c appears over the final L. This helps you to
identify the vector corresponding to the SETF or CLOCKF
statement.

SIMULATION
SYNTAX
OVERVIEW
Our basic philosophy in writing the simulation language was to
make it easy for you to describe a function in a natural way, so
that you could in turn find it easy to comprehend the behavior of
the design from the simulation specification. PALASM 2
software simulation language is divided into two sections:
*

Directives
Structured Control

Simulation directives are commands to establish circuit inputs,
clock waveforms, check for circuit outputs and capture time
response waveforms as you find necessary.

3C·2

lIIonoIithic

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SIMULATION

The simulation section is introduced by the required keyword
SIMULATION.

Simulation DirectivesSyntax:
PRLDF
SETF
CLOCKF
CHECK
TRACE_ON
TRACE_OFF

Structured Control
Constructs-Syntax:
*

FOR <variable>:= <lower limit> TO <upper limit> DO
BEGIN <statements> END

WHILE <condition> DO
BEGIN <statements> END

IF <condition> THEN
BEGIN <statements> END
ELSE
BEGIN <statements> END

The structured control constructs are used to build up
sequences of operations that repeat or are modified as a result of
particular logic values or conditions. They provide the basic
looping and decision branching of structured high-level
programming languages. <Condition> is a Boolean expression or
a mathematical equality. The condition is true if the Boolean
expression is asserted or the mathematical equality is satisfied.

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3C-3

SIMULATION

DETAILS OF THE
SIMULATION
SYNTAX
Each of the simulation statements is described below along with
some related items necessary for their proper use.

PRLDF
PRLDF < output pin list>
Example:

PRLDF 01 /02 /03
The PRLDF statement is used primarily to assign logical values
to, or initialize, register outputs on preloadable PAL devices. The
arguments to PRLDF are registered output pin names.
Uncomplemented names cause high, while names preceded by I
cause low logic values to be assigned to the registered output
pins.
This command affects the flow of simulation differently according
to the way each registered PAL device has its preload
configured. For PAL devices that have a dedicated preload pin,
PRLDF successively disables the outputs, enables preload,
loads the registers with the required logic values, disables
preload and finally enables the outputs. For PAL devices that
have their registers preloaded with supervoltages, PRLDF loads
the output registers, with a P inserted in the clock field of the
JEDEC vector. Simulation continues with the new values. For
registered PAL devices that cannot be preloaded, PRLDF
provides a convenient way of initializing registers to desired
values. Since this cannot be done in hardware, no more test
vectors are generated in the JEDEC file. Simulation results will,
however, appear in the trace and history files.

3C·4

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SIMULATION

Points to Note
1.

Only registered output pin names are valid arguments to the
PRLOF command.

The register outputs are preloaded, not the output pins.

When PRLOF is used on a state machine, both the state and
its outputs must be preloaded.

On certain PAL devices such as the PAL20X4, the A version
of the part pre loads with supervoltages, while the standard
version does not. In these cases, preloading is performed
by the software, and a warning message is issued to you.

SETF
SETF <Signal list>
Example:

SETF AlOE B IRESET IDa Dl D2
The signal is set high (H) if it is not preceded by / otherwise it is
set low (L). In the above example A, S, 01, and 02 are all set to H
and OE, RESET, and 00 are all set to L.
The signal should only be set if you want a change from the
previous value. The simulator always remembers the last value of
all the Signals. At the start of simulation, all signals are assumed
to have a don't care value (X).
Every time a SETF statement is executed, a vector is generated
and all the equations that are affected are evaluated. Any
internally generated events are also detected and evaluated.
With some activities, many more vectors can be generated by a
single SETF statement than with others, because of feedbacks
and asynchronous events. The simulator continues this process
of generating vectors and evaluating equations until the system

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3C-S

SIMULATION

stabilizes, that is, until there are no more changes in the output
signals or no events are generated. If the system fails to stabilize
after ten iterations, then an oscillatory condition is detected, and
the simulation halts.

CLOCKF
CLOCKF <list of clock signals>
Example:

CLOCKF CLKl CLK2
The CLOCKF statement has the list of clock signals (dedicated
clock pins) to which a clock pulse is to be applied. Only the clock
pins of the device can be used in the CLOCKF statement; any
other pin is an illegal signal for this statement.
Each CLOCKF statement corresponds to a pulse going from low
to high to low. Thus two vectors are generated, and during the
positive edge transition, the new value of the registers being
clocked is transferred to the output. No action takes place for the
registers that are not clocked.
At every CLOCKF statement, internally generated events and
asynchronous events are detected; and if they are present, more
vectors are generated. The operation of CLOCKF is similar to the
SETF statement except that CLOCKF goes through a pulse
rather than a level.
Using the SETF statement, initialize the clock pin to low before
using CLOCKF:
SETF <clock pin or /clock pin>
If the clock pin has a high value at the first CLOCKF statement, an
error occurs.

3C-6

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SIMULATION

CHECK
CHECK <signal list>
Example:

CHECK QO /Ql /Q2
CHECK lets you keep track of simulation results. The signals in
the CHECK statement are the high or low output signals that you
want to check. In the above example, you want to check if 00 is
high and 01 and 02 are low. Again, a signal without I is to be
checked for high and a signal with I is to be checked for low.
Whenever a CHECK statement is executed, the simulator
compares the actual value and the expected value of a particular
signal. If they are equal then no action is taken. Otherwise, an
error is reported and the simulator continues assuming the actual
value. CHECK reports the error plaCing a? in the vector where
the error occurred as well as a vector number. The history and
trace files will contain the? at this particular location.
CHECK is a powerful statement that should be used at important
pOints in your simulation for debugging your design.

TRACE_ON <signal list>
Example:

TRACE ON JOE SET RESET DO Dl D2 D3 /QO
/Ql /Q2
This statement contains the signals that you want to have listed in
the trace file. The signals will be listed in the same order and with
the same polarity as present in the TRACE_ON statement. This
list of signals will be active until the next TRACE_OFF statement
or until the end of the simulation specification. New signals can

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3C·7

SIMULATION

be traced on after the TRACE_OFF statement. This statement
helps you group the signals more naturally for debugging
purposes. For example, all control signals can be grouped
together, then all data signals can be grouped together, and
then all output signals can be grouped together. This makes the
observation of the results in the trace fife very easy.

This statement traces off all the signals mentioned in the latest
TRACE_ON statement. After this statement, no more results are
added to the trace fife until the next TRACE_ON statement is
executed. Thus none of the results between the current
TRACE_OFF statement and the next TRACE_ON statement are
displayed in the trace fife.
This breaks your results into time frames which is critical for
debugging. It should be remembered that the history file
contains all the information generated from the start of simulation
to the end of simulation. The signals are in the same order and of
the same polarity as in the pin list of the CHIP statement.

FOR loop
FOR <index var> := <lower limit> TO <upper limit> DO
BEGIN
<statements>
END
Example:

FOR J:= 3 to 8 DO
BEGIN
SETF A /B CLOCKF elk
END

3c-a

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SIMULATION

The FOR loop allows a very powerful, repetitive execution of
statements. Many statements can be embedded in a FOR loopeven another FOR statement with a different indexing variable.
You can generate many vectors just by increasing the limits of
this loop. The <lower limit> should be less than or equal to the
<upper limit>. All the limit values should be greater than or equal
to zero. You cannot use negative values for the limits. The loop
is not executed if the conditions expressed in the limits are
equal.

IF ... THEN ... ELSE
Loop
IF <cond> THEN
BEGIN
<Statements>
END
ELSE
BEGIN
<Statements>
END

IF <cond> THEN
BEGIN
<Statements>
END

Example:

IF J= 5 THEN
BEGIN
CHECK QO
END
ELSE
BEGIN
CHECK /QO
END
There are two variations of this statement. In the first, there is an
ELSE clause, and in the second there is no ELSE clause. If
the <condition> is true the THEN clause is executed; otherwise
the ELSE clause is executed. If there is no ELSE clause, then
the simulation executes the next statement after the IF

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3C-9

SIMULATION

statement. Condition expressions cannot contain nested
parentheses.
The <condition> can be any mathematical equality (=, >, <, >=,
<=, <»
Example 1:
IF (k2) THEN
The <condition> can also be any Boolean expression.
Example 2:
IF (DRDY * /CLR) THEN
In Example 1, the condition of I less than 2 is checked. In
Example 2, the expression (DRDY * /CLR) is evaluated; if it is true
then the condition is true.

WHILE ... DO Loop
WHILE<condition>DO
BEGIN
<statements>
END
The WHILE loop allows a repetitive execution of statements that
may be controlled by evaluation of logic conditions present
within the PAL device. Many statements can be embedded in a
WHILE loop including even other looping constructs. The WHILE
loop is used to iterate a set of commands until the condition is
false.
The <condition> can be any Boolean expression of logic signals.

3C·10

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SIMULATION

KEY POINTS TO
NOTE
1 . All signals are assumed to be don't care at the start.
2.

Initialize all your control signals (like three-state, Preload and
Clock) to their default values. For example: if the 3-state pin
is not initialized to the default condition, then the simulation
will give erroneous results.

If the 3-state pin is, say, IOE then SETF OE will enable the
outputs and SETF IOE will three-state the outputs.

If the 3-state pin is, say, OE then SETF IOE will enable the
outputs and SETF OE will three-state the outputs.

Points 3 and 4 also apply to the preload pins.

6. When using PAL20RA10 remember the following points:
00:= A * B
OO.ClKF = ClK
OO.RSTF = RESET
OO.SETF = SET
SETF SET IRESET
SETF RESET ISET

;The register 00 is set to H and so
; the output pin will go l.
;The register 00 is set to l and so
; the output pin will go H.

The data path of this PAL device is treated in the normal way
because the polarity fuse is in front of the register. Any
difference in the polarity between the signal in the pin list and the
left side of the equation is taken care of by the simulator.
It is only in the case of functional events that the value of the
register and the value of the pin are inverted.

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3C·11

SIMULATION

RULES FOR STATE
MACHINE
SIMULATION
SYNTAX
These rules show the difference between Boolean equation and
state machine simulation syntax.
1.

In a Boolean equation design, you use the PRLDF, CHECK,
TRACE_ON, WHILE and IF statements to reference the
value of an output. In a state machine design, you may use
these statements to reference states as well as outputs.
Let us look at an example of a PRLDF statement used to
reference a state as well as outputs from that state. In Figure
3C-1, note that the same statement is used to PRLDF a state
and the outputs from that state.

PRLDF STATE ONE 01 /02 /03

Figure 3C-1:
PRLDF Statement
This brings us to rule #2.

3C·12

When you PRLDF a state, remember to PRLDF the outputs
associated with that state in the same PRLDF statement.
Use one PRLDF statement for one state and as many signals
as fit within 128 characters. The more PRLDF statements
you use, the more vectors the software creates.

The two history output files from simulation are
<filename>.TRF (if TRACE_ON is used) and
<filename>.HST. On the PMS14R21, these files contain
information that is not found in the output files of a Boolean
equation design: the state of the machine at each point in
the simulation.

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SIMULATION

For a complete state machine design example that includes
simulation, refer to the traffic controller specification starting on
page 4-24.

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3C·13

SIMULATION

3C·14

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USING PALASM 2
SOFTWARE

This chapter describes how to complete the process of creating a
PAL circuit after you have written your PAL device Design
Specification (PDS). In addition, a few example PDS files are
provided at the end of this chapter. A good way to begin using
the program is by trying a few example files.
Note: Example PDS files are available on an IBM-PC disk. If you
don't have a copy, contact your local Monolithic Memories sales
office.
The procedure described in this chapter refers to non-menu
mode. Menu users will find the function key options clearly
defined on the main menu.

,d (

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USING PALASM 2 SOFTWARE

GENERAL
PROCEDURE
The steps in using PALASM 2 software to create a circuit are as
follows:
1. Create the PAL Design Specification (PDS) file. Consult
chapter 3A of this manual for detailed instructions.
2.

Run the parser.

Run the minimization program (optional).

Assemble the JEDEC file.

Run the simulation program.

Download the file to the programmer.

Program and test the part.

Figure 4-1 shows a flowchart of the process.

4·2

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USING PALASM 2 SOFTWARE

CREATE INPUT (PDS) FILE

RUN SYNTAX PARSER

RUN MINIMIZATION PROGRAM
(Optional)

ASSEMBLE JEDEC FILE

RUN SIMULATION PROGRAM

DOWNLOAD FILE TO
PROGRAMMER

PROGRAM AND TEST
DEVICE

Figure 4-1:
Device Programming Flowchart

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USING PALASM 2 SOFTWARE

Step 1: Create the
PDS File
You must describe the circuit you want as a series of Boolean
equations in sum-of-products form, or in a set of state machine
equations. Part of this process is deciding on the number of
inputs and outputs that the circuit requires. Once you have this
information, choose a PAL device with the right number of
inputs, outputs, and product terms.
Using a text editor, create a PAL device design specification
(PDS) file. The file name must adhere to the conventions of the
operating system you are running PALASM 2 software on and
should end with the suffix .PDS.
Note: If you create your PDS file using a word processor (such
as WORDSTAR), use it in non-document mode. You must create
a clean ASCII file free of embedded control characters.

Step 2: Run The
Parser
1.

Insert the disk containing the executable files in drive B.
Insert the disk containing your PDS file in drive A.
Make sure that the operating system is looking at both drives
for command files. The MS-DOS command

PATH A:\;B:\;
will take care of this requirement. (If you are using a hard disk,
specify drive C instead of B.)
2.

Enter PALASM2 <CR

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USING PALASM 2 SOFTWARE

The program will prompt you to give the name of your PDS
file.
3.

Enter <filename. ext> <CR>
Enter the name of your PDS file. (Full path names are not
supported by the software. Copy the file to your directory.)

Enter Y <CR>

(Create error file.).

Enter Y <CR>

(Echo PDS to terminal.)

Enter N <CR>

(Establish compatibility with
PDSCNVT-generated files.).

Enter N <CR>

(Generate a brief fuse plot.).

The system then checks the syntax of the design file. PALASM
2 software creates an intermediate file, PALASM2.TRE, on the
default drive. Syntax errors are listed to the terminal (and to
PALASM2.ERR if 4 above is answered YES), along with an
explanation of locations and likely causes. Brief fuse plots do
not contain entries for phantom fuses and unprogrammed
product terms.

Step 3: (Optional)
Logic Minimization
Performing this step will automatically minimize your logic
equations and convert state machine language to Boolean
equations. Minimization helps you better utilize the space on
your device.
(PALASM automatically minimizes state machine designs on the
PMS14R21.)
Enter MINIMI ZE <CR> (run Minimize software)

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Note: PALASM 2 software currently supports minimization for a
limited number of devices. Please refer to Table 1-1 for a list of
supported devices.

Step 4: Assemble the
JEDEC File
Enter XPLOT <CR> (run fuse plot software)
The system now produces the fuse plot and JEDEC output files.
XPLOT reads the intermediate file PALASM2.TRE and
processes each of the equations sequentially. If any
inconsistencies between the design file and the PAL device
architecture are detected, messages will be displayed. The
resulting XPLOT and JEDEC file will be listed by name and may
be used to program PAL devices.

Optional Step:
Disassemble the
JEDEC File
(This step can be run either before or after Step 5: Simulation.
The program, however, does not currently disassemble the
Simulation part of the JEDEC file.)
Enter JEDMAN <CR> (run JEDEC disassembly program)
The system prompts you to enter your JEDEC filename. The
filename should have a .JED or .JDC extension. The next
prompt asks you if you wish to enter a new JEDEC filename. This
gives you the option of manipulating a JEDEC file that has been
used for another device.
The program presents you with three options:

4 ...6

Disassembly

Monolithic

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USING PALASM 2 SOFTWARE

This option enables you to disassemble a JEDEC file. Your
output is a Boolean equation .PDS file.
*

Recalculation of checksums

You can manipulate a JEDEC file directly using this option.
*

Conversion of PAL22V10 JEDEC to PAL32VX10 JEDEC

The program JEDMAN takes a PAL22V10 JEDEC file and
converts it to a PAL32VX10 JEDEC file.

Step 5: Simulation
Enter S IM <CR> (run simulation software)
The system next produces the history (.HST) and trace (.TRF)
files indicated by simulation commands and directives of the PDS
file. SIM also reads PALASM2.TRE, but it requires the full data
structure to begin device simulation. The simulator also reads
the JEDEC file produced by XPLOT and add simulation vectors
at the end, updating the necessary checksums (OUTPUT in
filename JDC).

Step 6: Download the
File to the
Programmer
Refer to Appendix B and your programmer manual.

Step 7: Program and
Test the Part
Refer to your programmer manual.

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USING PALASM 2 SOFTWARE

Optional Step: Route
Logic
Enter ZHAL <CR>
The program attempts to route the logic equations in a ZHAL
array. If the process is successful, an appropriate message is
given. If the process fails, you see the message FORCE
ROUTE FAILURE along with the probable cause of failure.
The message that appears on your screen when the process fails
also indicates remedies, such as rearranging the device pinout.
ZHAL devices have a limited number of product terms; hence the
reason for failure is often an overlap of product terms between
adjacent pins indicated. ZHAL processing can be done for 20pin and 24-pin devices. By default, the software counts the pins
indicated in your design file and chooses the appropriate device.
You can, however, specify the device of your choice in your
design file.

Note: The ZHAL utility is not part of the regular package you get
when you order PALASM 2 software. You may, however, order
the ZHAL program from your local Monolithic Memories sales
office.

Error Messages
Most problems with design file syntax are caught by the front-end
PALASM 2 software program. Messages such as Malformed
Variables are given along with a line number location. The
line number can be identified by observing the echo output
listing generated by the program, if this option has been
selected.
You might also find it useful to have a printed copy of error
messages. You can make one by diverting the program output to
a file and then printing that file.

4·8

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Other errors in PDS syntax are only diagnosed during
processing by one or more back-end programs. Supplying too
many or too few pin names, extra product terms, or invalid pin
usage are only diagnosed by the XPLOT program. You will
need to run each of these programs to catch all potential error
conditions. Appendix E lists all error messages generated by the
program.
All intermediate files generated by PALASM 2 software are
directed to listed drive (A:). For the input file 4CNT, the
intermediate files generated by PALASM 2 software are as
follows:
4CNT.PDS
4CNT.XPT
4CNT.JED
4CNTHST
4CNT.TRF
PALASM2.TRE
4CNT.JDC

Original user input file
Fuse plot
JEDEC file with all checksums inserted
Complete Simulation History file
Selective Trace of Simulation
Intermediate design description
Complete JEDEC file containing
Simulation vectors

Note: For designs involving the MegaPAL64R32, an
additional file with extension .vRX is generated. It contains the
specific fuse plot to be downloaded to the VARIX programmer.
A full (not brief) fuse plot must be specified for VARIX
downloading.

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USING PALASM 2 SOFTWARE

DESIGN
EXAMPLES
Boolean Equation
Design
For an example of a state machine design, turn to page 4-24.
The following examples were generated from the 4CNT.PDS
supplied on the demonstration examples disk. (Contact your
local Monolithic Memories sales office if you don't have a copy of
the examples disk.) The input file, which includes simulation
equations, is followed by history, trace, XPLOT, and JEDEC files.

Input File

Title
Pattern
Revision
Author
Company
Date

4Bit Counter
4cnt.pds
B

J. Engineer
Monolithic Memories Inc., Santa Clara, CA.
1/14/85

CHIP 4BitCounter PAL16RP4

4·10

;PINS

1
CLK

2
UP

iPINS

6
DI

;PINS

11
/OC

12
NC

13
NC

14
D

15
C

;PINS

16
B

17
A

18
NC

19
NC

20
VCC

7
CLR

3
AI

4
BI

8
LOAD

5
CI
9
NC

10
GND

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USING PALASM 2 SOFTWARE

EQUATIONS
A := /A*/B*/C*/D*/UP*/LOAD*/CLR
+ /A* B* C* D* UP*/LOAD*/CLR
+ A* B* /D* /UP*/LOAD*/CLR
+ A*/ B* C* UP*/LOAD*/CLR
+ A* /C* UP*/LOAD*/CLR
+ A* D* /UP*/LOAD*/CLR
+ LOAD*/CLR* AI
B
+
+
+
+
+

:= /B*/C*/D*/UP*/LOAD*/CLR
/B* C* D* UP*/LOAD*/CLR
B* C*/D* /LOAD*/CLR
B*/C* UP*/LOAD*/CLR
B* D*/UP*/LOAD*/CLR
LOAD*/CLR* BI

C := /C*/D*/UP*/LOAD*/CLR
+ /C* D* UP*/LOAD*/CLR
+ C*/D* UP*/LOAD*/CLR
+ C* D*/UP*/LOAD*/CLR
+ LOAD*/CLR* CI
D := /D* /LOAD*/CLR
+ LOAD*/CLR* DI

;When CLR=l, A=O.
;Else it will count
;UP or DOWN.

;New value is loaded
;when LOAD=l, CLR=O.
;When CLR=l, B=O.
;Else it will count.

;New value is loaded
;when LOAD=l, CLR=O
;When CLR=l, C=O.
;Else it will count.
;New value is loaded
;when LOAD=l,CLR=O.
; Count
;New value is loaded
;when LOAD=l, CLR=O.

SIMULATION
TRACE ON AI BI CI DI LOAD CLR UP ABC D
;Load all registers
SETF LOAD /CLR AI BI CI DI OC
CLOCKF CLK
;to HIGH and count up
SETF CLR
CLOCKF CLK

;Clear all registers

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SETF /CLR UP /LOAD

;Start counting up

FOR 1:= 1 TO 16 DO
BEGIN
CLOCKF CLK
END

;Count up 16 clock
;cycles

SETF LOAD /CLR /UP AI BI CI DI
CLOCKF
SETF /LOAD
FOR 1:= 1 TO 16 DO
BEGIN
CLOCKF CLK

;Load all registers
ito HIGH and count
; down
;Count down 16 clock
;cycles

SETF LOAD CLR AI /BI CI /DI
CLOCKF CLK

;Test setting LOAD
;and CLR on at the
;same time.

SETF /OC
TRACE OFF
;The 4-bit counter counts up or down and has the
;clear and load capability.
The clear operation
;overrides count and load. The counter counts up
;whenever CLR=low, LOAD=low,and UP=high.
It counts
;down whenever CLR=low, LOAD=low, and UP=low.

4·12

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USING PALASM 2 SOFTWARE

XPLOT File

The following fuse plot of the 4Bit_Counter is produced by
PALASM 2 software. It shows the location and condition of each
fuse in the device.
X means the fuse is intact.
- means the fuse is programmed.

PALASM XPLOT, V2.22 - MARKET RELEASE (11-19-86)
(C) - COPYRIGHT MONOLITHIC MEMORIES INC, 1986
Title
Pattern
Revision
Author
Company
Date

4Bit Counter
4cnt.pds
B
Mehrnaz Hada, Bill Hollo
Monolithic Memories Inc.
1/14/85

PAL16RP4
4BITCOUNTER
11 1111 1111 2222 2222 2233
0123 4567 8901 2345 6789 0123 4567 8901
0
1
2
3
4
5
6
7

XXXX
XXXX
XXXX
XXXX
XXX X
XXXX
XXX X
XXXX

XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX

XXXX
XXXX
XXXX
XXXX
XXXX
XXX X
XXXX
XXXX

XXXX
XXXX
XXXX
XXXX
XXXX
XXX X
XXXX
XXX X

Monolithic

XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX

XXXX
XXX X
XXXX
XXXX
XXXX
XXX X
XXXX
XXX X

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XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX

4-13

USING PALASM 2 SOFTWARE

4·14

xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx

xxxx
xxxx
xxxx
xxxx
xxx x
xxx x
xxx x
xxxx

xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx

8
9
10
11
12
13
14
15

xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx

16
17
18
19
20
21
22
23

-x-x---x--

24
25
26
27
28
29
30
31

-x-x---

-x-x
-xx-x-x
x---x--xx-x-x---x-xxxx xxxx xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxx x xxxx xxxx

-x--x--x--x--x-x--xxxx xxxx
xxxx xxxx

32
33
34
35
36
37
38
39

-x-x--x---x--

-x--x--x--x-x--xxxx xxxx
xxxx xxxx
xxxx xxxx

40
41
42

-x-x -x-x--- -x-- x--xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

---x ---x -x-x -x---x- --x- -xx- -x---x-x-- -x--xx- -x----x
x-----x -x-- -x---x- -x-x -x-x---x-- x--xxxx xxxx xxxx xxx x xxxx xxxx xxxx xxxx
---x
---x
--x--x--x--x-

---x
---x
--x--x--x-

---x
--x--x---x

-x-x
-xx-x-x
-xxx---x-xxxx xxxx xxxx xxx x xxxx xxxx
xxxx xxxx xxxx xxxx xxx x xxxx
xxxx xxxx xxxx xxx x xxxx xxxx
---x
---x
--x--x-

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xxxx
xxx x
xxx x
xxx x
xxx x

xxx x
xxxx
xxxx
xxxx
xxx x

xxxx
xxxx
xxxx
xxxx
xxxx

xxxx
xxx x
xxxx
xxxx
xxx x

xxxx xxxx xxx x
xxxx xxxx xxxx
xxx x XXXX xxxx xxxx
XXXX xxxx xxxx xxx x
XXXX xxxx xxxx xxx x
xxxx xxxx xxxx xxxx
XXXX XXXX xxxx xxx x
XXXX xxxx xxxx xxxx

xxxx
xxxx
xxx x
xxxx
xxx x
xxxx
xxxx
xxxx

xxxx
xxxx
xxx x
xxxx
xxxx
xxxx
xxxx
xxxx

xxxx XXXX
xxxx XXXX
xxx x XXXX
xxxx XXXX
xxx x XXXX
xxxx XXXX
xxxx xxxx
xxxx XXXX

XXXX xxxx
XXXX XXXX
XXXX xxxx

xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxx x

xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx

xxxx XXXX
xxx x XXXX
xxxx xxxx
xxx x xxxx
xxx x XXXX
xxx x XXXX
xxxx XXXX
xxxx xxxx

43
44
45
46
47

XXXX
XXXX
XXXX
XXXX
XXXX

48
49
50
51
52
53
54
55

XXXX
XXXX

56
57
58
59
60
61
62
63

xxxx
xxxx
xxxx
xxxx
xxxx

xxxx
xxxx
xxxx
xxxx xxxx xxxx
xxxx xxxx xxxx
XXXX xxxx xxxx
XXXX XXXX xxxx
XXXX XXXX xxxx

xxx x
xxx x
xxx x
xxxx
xxxx
xxxx
xxxx
xxxx

XXXX
XXXX
XXXX
XXXX
XXXX

OUTPUT PINS: 11111111
23456789
POLARITY FUSE: XX----XX
TOTAL FUSES BLOWN: 548

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USING PALASM 2 SOFTWARE

History File
P~LA$M

SIMULATION, V2.22 - MARKET RELEASE (11-19-86)
(C) - COPYRIGHT MONOLITHIC MEMORIES INC, 1986
PALASM SIMULATION HISTORY LISTING
Title
Pattern
Revision
Author
Company
Date

4Bit Counter
4cnt.pds
B

Mehrnaz Hada, Bill Hollo
Monolithic Memories Inc.
1/14/85

4BITCOUNTER
Page
1
g cg cg
CLK XHHLLHHLLH
UP
XXXXXXXXHH
AI
HHHHHHHHHH
BI
HHHHHHHHHH
CI
HHHHHHHHHH
DI
HHHHHHHHHH
CLR LLLLHHHHLL
LOAD HHHHHHHHLL
C;ND LLLLLLLLLL
/OC
LLLLLLLLLL
XXHHHHLLLL
D
C
XXHHHHLLLL
B
XXHHHHLLLL
A
XXHHHHLLLL
VCC HHHHHHHHHH

4-16

c c c
HLHHLHHLHH
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
LLLLLLLLLL
LLLLLLLLLL
LLLLLLLLLL
LLLLLLLLLL
HHHLLLHHHL
LLLHHHHHHL
LLLLLLLLLH
LLLLLLLLLL
HHHHHHHHHH

IWonoIIIhIc

c c c c
LHHLHHLHHL
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
LLLLLLLLLL
LLLLLLLLLL
LLLLLLLLLL
LLLLLLLLLL
LLHHHLLLHH
LLLLLHHHHH
HHHHHHHHHH
LLLLLLLLLL
HHHHHHHHHH

lIIIemorles

c c c
HHLHHLHHLH
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
LLLLLLLLLL
LLLLLLLLLL
LLLLLLLLLL
LLLLLLLLLL
HLLLHHHLLL
HLLLLLLHHH
HLLLLLLLLL
LHHHHHHHHH
HHHHHHHHHH

USING PALASM 2 SOFTWARE

4BITCOUNTER
Page
2
c c c
CLK HLHHLHHLHH
UP
HHHHHHHHHH
AI
HHHHHHHHHH
BI
HHHHHHHHHH
CI
HHHHHHHHHH
DI
HHHHHHHHHH
CLR LLLLLLLLLL
LOAD LLLLLLLLLL
GND LLLLLLLLLL
IOC
LLLLLLLLLL
D
HHHLLLHHHL
C
HHHLLLLLLH
B
LLLHHHHHHH
A
HHHHHHHHHH
VCC HHHHHHHHHH

c c cg
LHHLHHLLHH
HHHHHHHLLL
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
LLLLLLLLLL
LLLLLLLHHH
LLLLLLLLLL
LLLLLLLLLL
LLHHHLLLLH
HHHHHLLLLH
HHHHHLLLLH
HHHHHLLLLH
HHHHHHHHHH

Monolithic

cg c c
LLHHLHHLHH
LLLLLLLLLL
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
LLLLLLLLLL
HLLLLLLLLL
LLLLLLLLLL
LLLLLLLLLL
HHHLLLHHHL
HHHHHHLLLL
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH

W Memories

c c c c
LHHLHHLHHL
LLLLLLLLLL
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
LLLLLLLLLL
LLLLLLLLLL
LLLLLLLLLL
LLLLLLLLLL
LLHHHLLLHH
LLHHHHHHLL
HHLLLLLLLL
HHHHHHHHHH
HHHHHHHHHH

4·17

USING PALASM 2 SOFTWARE

4BITCOUNTER
Page
3

c
CLK
UP
AI
BI
CI
DI
CLR
LOAD
GND

IOC
D
C
B
A
VCC

4·18

HHLHHLHHLH
LLLLLLLLLL
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
LLLLLLLLLL
LLLLLLLLLL
LLLLLLLLLL
LLLLLLLLLL
HLLLHHHLLL
LLLLHHHHHH
LLLLHHHHHH
HHHHLLLLLL
HHHHHHHHHH

HLHHLHHLHH
LLLLLLLLLL
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
LLLLLLLLLL
LLLLLLLLLL
LLLLLLLLLL
LLLLLLLLLL
HHHLLLHHHL
LLLLLLHHHH
HHHHHHLLLL
LLLLLLLLLL
HHHHHHHHHH

c g

LHHLHHLHHL
LLLLLLLLLL
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
LLLLLLLLLL
LLLLLLLLLL
LLLLLLLLLL
LLLLLLLLLL
LLHHHLLLHH
HHLLLLLLHH
LLLLLLLLHH
LLLLLLLLHH
HHHHHHHHHH

...."thIolUD.......,..

LHHLL
LLLLL
HHHHH
LLLLL
HHHHH
LLLLL
HHHHH
HHHHH
LLLLL
LLLLH
HHLLZ
HHLLZ
HHLLZ
HHLLZ
HHHHH

USING PALASM 2 SOFTWARE

Trace File

PALASM SIMULATION, V2.22 - MARKET RELEASE (11-1986)
(C) - COPYRIGHT MONOLITHIC MEMORIES INC, 1986
PALASM SIMULATION SELECTIVE TRACE LISTING

Title
Pattern
Revision
Author
Company
Date

4Bit Counter
4cnt.pds
B

Mehrnaz Hada, Bill Hollo
Monolithic Memories Inc.
1/14/85

4BITCOUNTER
Page
1
g cg cg
AI
HHHHHHHHHH
BI
HHHHHHHHHH
CI
HHHHHHHHHH
DI
HHHHHHHHHH
LOAD HHHHHHHHLL
CLR LLLLHHHHLL
UP
XXXXXXXXHH
A
XXHHHHLLLL
B
XXHHHHLLLL
C
XXHHHHLLLL
D
XXHHHHLLLL

c c c
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
LLLLLLLLLL
LLLLLLLLLL
HHHHHHHHHH
LLLLLLLLLL
LLLLLLLLLH
LLLHHHHHHL
HHHLLLHHHL

Nlonol/thic

c c c c
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
LLLLLLLLLL
LLLLLLLLLL
HHHHHHHHHH
LLLLLLLLLL
HHHHHHHHHH
LLLLLHHHHH
LLHHHLLLHH

W Nlemorles

c c c
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
LLLLLLLLLL
LLLLLLLLLL
HHHHHHHHHH
LHHHHHHHHH
HLLLLLLLLL
HLLLLLLHHH
HLLLHHHLLL

4·19

USING PALASM 2 SOFTWARE

4BITCOUNTER
Page
2
c c c
AI
HHHHHHHHHH
BI
HHHHHHHHHH
CI
HHHHHHHHHH
01
HHHHHHHHHH
LOAD LLLLLLLLLL
CLR LLLLLLLLLL
UP
HHHHHHHHHH
HHHHHHHHHH
A
B
LLLHHHHHHH
C
HHHLLLLLLH
o
HHHLLLHHHL

4·20

c c cg
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
LLLLLLLHHH
LLLLLLLLLL
HHHHHHHLLL
HHHHHLLLLH
HHHHHLLLLH
HHHHHLLLLH
LLHHHLLLLH

Monolithic

cg c c
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
HLLLLLLLLL
LLLLLLLLLL
LLLLLLLLLL
HHHHHHHHHH
HHHHHHHHHH
HHHHHHLLLL
HHHLLLHHHL

"'emorles

c c c c
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
LLLLLLLLLL
LLLLLLLLLL
LLLLLLLLLL
HHHHHHHHHH
HHLLLLLLLL
LLHHHHHHLL
LLHHHLLLHH

USING PALASM 2 SOFTWARE

4BITCOUNTER
Page
3
c c c
AI
HHHHHHHHHH
BI
HHHHHHHHHH
CI
HHHHHHHHHH
DI
HHHHHHHHHH
LOAD LLLLLLLLLL
CLR LLLLLLLLLL
UP
LLLLLLLLLL
HHHHLLLLLL
A
B
LLLLHHHHHH
C
LLLLHHHHHH
D
HLLLHHHLLL

c c c
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
LLLLLLLLLL
LLLLLLLLLL
LLLLLLLLLL
LLLLLLLLLL
HHHHHHLLLL
LLLLLLHHHH
HHHLLLHHHL

Ntonollthlc

c c c c
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
LLLLLLLLLL
LLLLLLLLLL
LLLLLLLLLL
LLLLLLLLHH
LLLLLLLLHH
HHLLLLLLHH
LLHHHLLLHH

W Ntemorle.

g cg
HHHHH
LLLLL
HHHHH
LLLLL
HHHHH
HHHHH
LLLLL
HHLLZ
HHLLZ
HHLLZ
HHLLZ

4·21

USING PALASM 2 SOFTWARE

JEDEC File

PALASM XPLOT, V2.22 - MARKET RELEASE (11-19-86)
(C) - COPYRIGHT MONOLITHIC MEMORIES INC, 1986
Title
Pattern
Revision
Author
Company
Date

4Bit Counter
4cnt.pds
B

Mehrnaz Hada, Bill Hollo
Monolithic Memories Inc.
1/14/85

PAL16RP4
4BITCOUNTER*
GO*FO*
L0512 10111111111011101110101010111111*
L0544 01111111111011011101100110111111*
L0576 10111111110111011111101110111111*
L0608 11111111110111101111100110111111*
L0640 01111111110111111110101110111111*
L0672 11111111110111111101101010111111*
L0704 11110111111111111111101101111111*
L0768 10111111111111101110101010111111*
L0800 01111111111111101101100110111111*
L0832 11111111111111011101101010111111*
L0864 01111111111111011110101110111111*
L0896 10111111111111011111100110111111*
L0928 11111111011111111111101101111111*
L1024 10111111111111111110101010111111*
L1056 01111111111111111110100110111111*
L1088 01111111111111111101101010111111*
Ll120 10111111111111111101100110111111*
Ll152 11111111111101111111101101111111*
L1280 11111111111111111111101010111111*
L1312 11111111111111110111101101111111*
L2048 00111100*
V0001 CX111101XNOXXHHHHXXN*

4·22

Monolithic

W IIIIemorles

USING PALASM 2 SOFTWARE

VOOO2 CXllllllXNOXXLLLLXXN*
VOOO3 ClllllOOXNOXXHLLLXXN*
VOOO4 ClllllOOXNOXXLHLLXXN*
VOOO5 ClllllOOXNOXXHHLLXXN*
VOOO6 ClllllOOXNOXXLLHLXXN*
VOOO7 ClllllOOXNOXXHLHLXXN*
VOOO8 ClllllOOXNOXXLHHLXXN*
VOOO9 ClllllOOXNOXXHHHLXXN*
VOOlO ClllllOOXNOXXLLLHXXN*
VOOll ClllllOOXNOXXHLLHXXN*
VOOl2 ClllllOOXNOXXLHLHXXN*
VOOl3 ClllllOOXNOXXHHLHXXN*
VOOl4 ClllllOOXNOXXLLHHXXN*
VOOl5 ClllllOOXNOXXHLHHXXN*
VOOl6 ClllllOOXNOXXLHHHXXN*
VOOl7 ClllllOOXNOXXHHHHXXN*
VOOl8 ClllllOOXNOXXLLLLXXN*
VOOl9 COllllOlXNOXXHHHHXXN*
VOO20 COllllOOXNOXXLHHHXXN*
VOO2l COllllOOXNOXXHLHHXXN*
VOO22 COllllOOXNOXXLLHHXXN*
VOO23 COllllOOXNOXXHHLHXXN*
VOO24 COllllOOXNOXXLHLHXXN*
VOO25 COllllOOXNOXXHLLHXXN*
VOO26 COllllOOXNOXXLLLHXXN*
VOO27 COllllOOXNOXXHHHLXXN*
VOO28 COllllOOXNOXXLHHLXXN*
VOO29 COllllOOXNOXXHLHLXXN*
VOO30 COlllI00XNOXXLLHLXXN*
VOO3l COlIII00XNOXXHHLLXXN*
VOO32 COllllOOXNOXXLHLLXXN*
VOO33 COllllOOXNOXXHLLLXXN*
VOO34 COllllOOXNOXXLLLLXXN*
VOO35 COllllOOXNOXXHHHHXXN*
VOO36 COlOlOllXNOXXLLLLXXN*
VOO37 OOlOlOllXNlXXZZZZXXN*
C446C*
9E50

Monolithic

W lIIemories

4·23

USING PALASM 2 SOFTWARE

State Machine Design
Traffic Controller Example

We have used sections of the state machine traffic controller as
examples in Chapter 38: State Machine Design. You will now
see how the entire example is created. (Parts of this example also
appear in Monolithic Memories' Programmable Logic Handbook.)
The traffic intersection we are designing for is illustrated in Figure
4-2

RED2

YEL2

GRN2

0
0
0

RED1
YEL1
GRN1

r.r;"7'"".

•

.........
... ...

... ... ......
...

...... >

r. . . . .
/

......
... "..
... .I' ... ~l
...

...

SEN1

Figure 4-2:
Traffic Intersection

4·24

Monolithic WMemorles

SEN2

USING PALASM 2 SOFTWARE

Figure 4-2 shows two one-way streets: direction 1 and direction
2. Each direction has a signal consisting of red, yellow, and
green lamps. These lamps are activated with active-high signals:
RED1, VEL 1, GRN1 for direction one; RED2, VEl2, GRN2 for
direction 2. Also, each direction has a sensor that provides an
active-high signal indicating the presence of a vehicle. Our
controller is to manage this intersection with the sensors as
inputs and the lamps as outputs.

RED1

SEN1

RED2

SEN2
RESET

TRAFFIC
SIGNAL
CONTROllER

YEL1
YEL2
GRN1
GRN2

ClK

Figure 4-3:
Traffic Signal Controller Logic Diagram

The traffic signal controller logic diagram in Figure 4-3 includes
the system clock (elK) and an initialize or reset signal (RESET).
RESET drives the controller to the initial state you define in your
design.
In order to set up our design file, we need to spell out the
specifics of the controller. Figure 4-4 illustrates the traffic
controller with a state diagram.

/IIIonoIlthIt;

W ••morles

4·25

USING PALASM 2 SOFTWARE

vee

SEN1.SEN2

Figure 4-4:
State Diagram of the Traffic Signal Controller

4·26

Monolithic

""emorles

USING PALASM 2 SOFTWARE

Traffic Controller Design
Specification
The complete design file for the state machine traffic controller is
given below.

TITLE
PATTERN
REVISION
AUTHOR
COMPANY
DATE

TRAFFIC CONTROLLER
STATE MACHINE
1
J. ENGINEER
MONOLITHIC MEMORIES
JANUARY 30, 1987

CHIP

S MACHINE

PMS14R21

;PINS

1
CLOCK

2
DCLOCK

3
SEN1

4
SEN2

5
12

6
13

;PINS

7
14

8
15

9
16

10
17

11
SDI

12
GND

;PINS

13
RESET

14
SDO

15
RED1

16
YELl

17
GRN1

18
RED2

;PINS

19
YEL2

20
GRN2

21
01

22
00

23
MODE

24
VCC

STATE
MOORE MACHINE
MASTER RESET
DEFAULT OUTPUT /RED1 /YEL1 /GRN1 /RED2 /YEL2
/GRN2

NIonoIlthlc

W lIIIemorie.

4·27

U:::HNu t"ALA::SM 2 ::SUFTWARE

POWER UP := vee -> 80
80 := e3 -> 81
+ eo -> 81
+ e1 -> 82
+-> 80
81 := vee -> 82
82 .- vee -> 83
83 .- vee -> 84
84 .- e3 -> 85
+ eo -> 85
+ e2 -> 86
+
-> 84
->
85 := vee
86
86 := vee -> 87
87 .- vee -> 80
80.0UTF
81.0UTF
82.0UTF
83.0UTF
84.0UTF
85.0UTF
86.0UTF
87.0UTF

:=
:=
:=

GRN1
GRN1
GRN1
YELl
RED1
RED1
RED1
RED1

*
*
*
*
*
*
*
*

RED2
RED2
RED2
RED2
GRN2
GRN2
GRN2
YEL2

eONDITION8
/8EN1 * /8EN2
eo
e1
/8EN1 * 8EN2
e2
8EN1 * /8EN2
SEN1 * SEN2
e3

4·28

NIonolithiCW Memories

USING PALA5M 2 50F1WAHt:

SIMULATION
TRACE ON CLOCK SEN1 SEN2 RED1 YELl GRN1 RED2 YEL2
GRN2
SETF RESET /CLOCK
CLOCKF CLOCK ;STATE TRANSITION ONLY ON 1ST CLOCK
CHECK /RED1 /YEL1 GRN1 /YEL2 /GRN2 RED2
SETF /SEN1 /SEN2
CLOCKF CLOCK
CLOCKF CLOCK
CHECK /RED1 /YEL1 GRN1 RED2 /YEL2 /GRN2
CLOCKF CLOCK
CHECK /RED1 YELl /GRN1 RED2 /YEL2 /GRN2
CLOCKF CLOCK
CHECK RED1 /YEL1 /GRN1 /RED2 /YEL2 GRN2
CLOCKF CLOCK
CHECK RED1 /YEL1 /GRN1 /RED2 /YEL2 GRN2
CLOCKF CLOCK
CHECK RED1 GRN2
CLOCKF CLOCK
CHECK RED1 YEL2
CLOCKF CLOCK
CHECK /RED1 /YEL1 GRN1 RED2 /YEL2 /GRN2
SETF /SEN1 SEN2
CLOCKF CLOCK
CHECK /RED1 /YEL1 GRN1 RED2 /YEL2 /GRN2

IIIIonoIlthlo

W Memories

4·29

U~IN\.:i

I""ALA::iM 2

SOFTWARE

CLOCKF CLOCK
CLOCKF CLOCK
SETF SEN1 /SEN2
CLOCKF CLOCK
CLOCKF CLOCK
CHECK YEL2 RED1
CLOCKF CLOCK
CHECK GRN1 RED2
TRACE OFF
The file TRAFFIC.PDS is the name of the traffic controller design
file. After running PALASM 2 software, we get several output
files The following pages show the history file that the simulator
produces.
HISTORY FILE

PROSIM, V2.22 - MARKET RELEASE (11-19-86)
(C) - COPYRIGHT MONOLITHIC MEMORIES INC, 1986
Title
Pattern
Revision
Author
Company
Date

:TRAFFIC CONTROL
:TRAFFIC.PDS
:A
:J. Engineer
:MONOLITHIC MEM
:3/31/86 [9/30]

S MACHINE

4·30

Monolithlem Memories

USING PALASM 2 SOFTWARE

Page

CLOCK
DCLK
SEN1
SEN2
I2
I7
SDI
GND
RESET
SDO
RED1
YELl
GRN1
RED2
YEL2
GRN2
01
00
MODE
VCC

s esc
LHHLLLHHLH
XXXXXXXXXX
XXXXLLLLLL
XXXXLLLLLL
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
LLLLLLLLLL
HHHHHHHHHH
XXXXXXXXXX
HHLLLLLLLL
HHLLLLLLLL
HHHHHHHHHH
HHHHHHHHHH
HHLLLLLLLL
HHLLLLLLLL
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
HHHHHHHHHH

STATE

c c c
HLHHLHHLHH
XXXXXXXXXX
LLLLLLLLLL
LLLLLLLLLL
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
LLLLLLLLLL
HHHHHHHHHH
XXXXXXXXXX
LLLLLLHHHH
LLLHHHLLLL
HHHLLLLLLL
HHHHHHLLLL
LLLLLLLLLL
LLLLLLHHHH
XXXXXXXXXX
XXXXXXXXXX

c c c esc c
LHHLHHLHHL LLHHLHHLHH
XXXXXXXXXX XXXXXXXXXX
LLLLLLLLLL LLLLLLLLLL
LLLLLLLLLL HHHHHHHHHH
XXXXXXXXXX XXXXXXXXXX
XXXXXXXXXX XXXXXXXXXX
XXXXXXXXXX XXXXXXXXXX
LLLLLLLLLL LLLLLLLLLL
HHHHHHHHHH HHHHHHHHHH
XXXXXXXXXX XXXXXXXXXX
HHHHHHHHLL LLLLLLLLLH
LLLLLLLLLL LLLLLLHHHL
LLLLLLLLHH HHHHHHLLLL
LLLLLLLLHH HHHHHHHHHL
LLLLLHHHLL LLLLLLLLLL
HHHHHLLLLL LLLLLLLLLH
XXXXXXXXXX XXXXXXXXXX
XXXXXXXXXX xxxxxxxxxx
xxxxxxxxxx XXXXXXXXXX XXXXXXXXXX
HHHHHHHHHH HHHHHHHHHH HHHHHHHHHH

PPSSSSSSSS SSSSSSSSSS SSSSSSSSSS SSSSSSSSSS
0000000111 2223334445 5566677700 0002223334
WW

EE
RR

uu
PP

MoneIIthIeW • •""".,..

4-31

U~INU

I"'ALA~M

~UFTWARE

S MACHINE
Page : 2

CLOCK
DCLK
SEN1
SEN2
12
13
14
15
16
17
SDI
GND
RESET
SDO
RED1
YELl
GRN1
RED2
YEL2
GRN2
01
00
MODE
VCC
STATE

4·32

c s c c
LLLHHLHHLH
XXXXXXXXXX
LHHHHHHHHH
HLLLLLLLLL
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
LLLLLLLLLL
HHHHHHHHHH
XXXXXXXXXX
HHHHHHHHHH
LLLLLLLLLL
LLLLLLLLLL
LLLLLLLLLL
LLLLLLLHHH
HHHHHHHLLL
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
HHHHHHHHHH

c
HL
XX
HH
LL
XX
XX
XX
XX
XX
XX
XX
LL
HH
XX
LL
LL
HH
HH
LL
LL
XX
XX
XX
HH

SSSSSSSSSS SS
4444666777 00

MonoIlthleW Memories

APPENDIX A
INSTALLATION &
OPERATION NOTES
IBM-PC / DOS 2.10
IMPLEMENTATION
Using PALASM 2
Software
Before starting you must have a work disk that has been created
using the procedure in Chapter 2.
The example below walks you through the programming of a
PAL devicefrom start to finish. It assumes that you are working
with a 20-pin PAL device, an IBM-PC and a Data I/O Model 29.
1.

Using a text editor, create your PAL device design file,
making certain that it follows the conventions stated in
Chapter 3, or copy example 8COUNT.PDS from the
Examples disk to your work disk. (Contact your local
Monolithic Memories sales office if you do not have a copy of
the Examples disk.)
If you are using Wordstar as your text editor, a word of
caution: Wordstar files created in document mode have
control characters which PALASM 2 software may not
recognize. A quick and simple test is to TYPE (DOS
command) your file on to the screen. If you see strange
characters, PALASM 2 software will have trouble
understanding the file. Although this is not a foolproof way
of catching all control characters, it unmasks most of them.

Monolithic

Memories

A·1

IN~ lALLA IIUN

ANU

Ut"t:HA TlON

EDLIN, which is available on your DOS disk, is a simple and
effective line editor that can be used to create straight ASCII
files free from control characters.
2.

To start, insert the disk containing the program
PALASM.EXE into drive B and the disk with your WORK
diskette into drive A.
Reboot the machine. Now type:

PALASM2 <CR>
In response to the first prompt, type:

A: <filename>.PDS
This indicates that the input file, which is a design file
describing an 8-bit counter, is located on the disk in drive A.
Answer the four YIN questions as explained in Chapter 4 of
this manual.
3.

Insert the disk containing the XPLOT,EXE program in drive
B. and enter

A:>XPLOT
4.

Insert the disk containing PC2 into drive B and enter

A:>PC2
5.

Run PC2 (PALSETUP mode) to make certain the
communications parameters specified are correct. For the
Data I/O programmer, the recommended parameters are
4800 baud rate, 7 data bits, 1 stopbit and even parity. In any
event, due to limitations of the PC, do not exceed 4800
baud.

Monolithic

W Memori••

INSTALLATION

AND

O~t:HA

liON

Return to the communications part of PC2. Before pressing
F1, check to see if proper communication has been set up
with the programmer. While downloading, the most common
problem is establishing that the Data 1/0 and PC are actually
communicating. To test this quickly, on the Data 1/0, press
COpy from RAM to PORT START. If communication has
indeed been established, the contents of RAM on the Data
1/0 will now be dumped on the screen. You can now be sure
that the proper handshaking is taking place.

Next, manually enter the family pin code listed in Appendix B
of this manual. Using the DATA 1/0 keyboard, press
<COpy> from <DEVICE> to <RAM> on the Data 1/0 and,
when the programmer asks for the family pin code on the
window, key in the 4 digit code for the device you are using.
You will find the proper codes in the Data 1/0 manual.

Press <SELECT> <E> <B> <START> on the Data 1/0
keyboard. This tells the programmer to expect a JEDEC
input file. Push <F1> on the IBM-PC to begin transmission.
(Provide a filename if asked.)
The clock face on the window of the Data 1/0 should begin to
turn, indicating data transfer. After transmission has been
completed, verify that the checksum on the Data 1/0 is all
right (no error status indicated.)

If you do not wish to use PC2, a quick and dirty way to set up
the communications parameters on the PC is to type the
following with the DOS disk in drive A:

MODE COM1:4800,E,7,1,P
This has the same effect as running PC2 in setup mode.
Next, assuming the file you wish to download is
<filename>.JED, instead of running PC2 in communications
mode, type

COpy <filename>.JED COM1:

Monolithic

W Memories

A·3

IN~IALLAIIUN

AND OPERATION

Restrictions
1.

The XPLOT program needs access to PAL device Definition
Files (PDF) in order to work with the specific architectural
dependencies of individual part types. The program first
searches the default directory to locate them and then on
drive B. This will work if you place your editor, design files
and scratch files on A (the default drive) and the executable
and PDF files on drive B (two drive system). The PATH
command should be used to allow finding the executable
files on drive B as in

A> PATH A:\;B:\;
If you have an IBM-XT, place all files in a single directory on
the fixed disk and substitute drive C for B in the PATH
command. That directory should be your default location. If
the system cannot find the PDF files, it will prompt you to
insert a disk into drive B.
2.

Do not terminate the program abnormally by pressing CTRLC, BREAK, etc. when you are sending the output to a file. If
the session is terminated using CTRL-C, it may result in lost
files on your disk, since your output file will not have been
properly closed.
Suppose your output file on drive A is called OUTPUT.PRN.
If you abort your program using CTRL-C, when you look at
the directory, it will indicate that your output file contains zero
blocks:
A> DIR <CR>

OUTPUT.PRN 0 09-15-83 1:47p
Your disk, however, will contain lost files. To recover any lost
files or clusters, run CHKDSK with the IF switch using the
IBM 2.0 boot disk.

IIIonoilthic MiDlllemories

INSTALLATION AND OPERATION

Type:

A> CHKDSK B:/F
1 lost clusters in 1 chain
Convert lost chains to files
(YIN)?

362496 bytes total disk space
o bytes in 1 hidden files
216064 bytes in 2 user files
1024 bytes in 1 recovered files
145408 bytes available on disk
MS-DOS names the recovered file, FILEOOO.CHK. You can
then delete OUTPUT.PRN and rename FILEOOO.CHK as you
please.
3. The disk in drive A: should have a COMMAND.COM on it and
be formatted as a system disk. Otherwise, DOS will prompt
you to insert a COMMAND.COM disk after each program
executes.
4.

. .

All the software must be from the same release. Running
different software versions on the same data files will cause
the programs to generate a PDF failure message.

PALASM 2 Software
Files
PALASM 2 software is distributed on 51/4 inch floppy disks.
The actual allocation of files and file count on a disk may vary
with the specific release of the program due to space
considerations. In general expect files with the suffix .PDS to be
located on the Examples Disk and files with the suffix .PDF on
the Executable Disks.

Monolithic

Memories

A·5

INSTALLATION AND OPERATION

VAX-VMS
IMPLEMENTATION
Installation of
Software
1. A directory or sub-directory should be created to contain the
PALASM 2 software, if one does not already exist. For ease
of identification name it [PALASM]; all future references in
this document will use [PALASM] as the directory name.

$ CREATE/DIR [PALASM]
2.

Move to directory [PALASM]

$ SET DEFAULT [PALASM]
3.

Create a command procedure START.COM with the
following steps:

$ IN DEVICE := "MTAO:"
$ ALLOCATE 'IN_DEVICE' IN_VOLUME
$ MOUNT/DENSITY=1600/0VERRIDE=
IDENTIFICATION'IN DEVICE'
$ COPY/LOG 'IN DEVICE'INSTALL.COM
$ DISMOUNT/NOUNLOAD IN VOLUME
$ DEALLOCATE 'IN DEVICE'
$ EXIT
where MTAO: is the name of the magnetic tape drive.
4.

Remove the ring from the magnetic tape, load it on the
required drive, and set it on-line.

Execute the START command procedure:

$ @START

A·a

MonoIlth/eW.emories

INSTALLATION AND OPERATION

The command procedure will now read the file INSTALl.COM
from the magnetic tape in the [PALASM] directory.
6.

To install all the PALASM 2 software, execute the command
procedure INSTALl.COM. Type
$ @INSTALL
The following message appears
INPUT (SUB)DIRECTORY NAME TO CONTAIN
PALASM 2 SOFTWARE?:
Choose a name for the directory that will contain PALASM 2
software (e.g., PALASM) and type it at the prompt.
Next, assign the logical directory name PAL2$DAT to the
directory you chose for PALASM 2 software. Type
$ASS IGN <directory containing PALASM 2 software>
PAL2$DAT<CR>
This command procedure will read all the necessary files from
the magnetic tape and from the PALASM 2 software
executables.

To make the PALASM 2 software generally available to
users, either all users can separately execute the PALASM
2 software set-up command procedure in the user login file,
or the VAX system manager can execute this in the VAX
system login file.
Be prepared to answer the following two questions:
A.

Directory input name (e.g., [PALASM] )

Magnetic tape drive name

Monolithic ~ Memories

A·7

INSTALLATION AND OPERATION

To execute the PALASM 2 software set-up procedure input
the command

$ @DRA: [PALASM]PAL2ASS DRA: [PALASM]
where DRA: is the disk drive name.
8.

Now input the help request to display what has been set up:

$ PAL2HLP

Notes on Software
Support Procedures
The following procedures may be performed on the VAX-VMS
system only.
1.

The command procedure file PAL2ASS.COM contains
various assignments which the software will use to find runtime files and to give you easy access to PALASM 2
software, command files, test files and documentation. If
desired you can place the different elements of the PALASM
2 software suite in multiple directories, but the assignments
in the set-up file must be changed to reflect the different
directory structure. A single directory structure has been
used here to simplify description of operations.

A set of PALASM 2 software example test files has been
included in your package. A list of the examples plus a
description can be obtained with the input command

$ PAL2LIS
To run any of the examples, a command procedure is
included to execute the syntax checker and to produce fuse
maps. To execute the command procedure, input the
command

A·a

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W lIIIemorles

INSTALLATION AND OPERATION

$ PAL2EX <example name>
3.

A simplified batch procedure that runs various components
of the PALASM 2 software can be executed by using the
input command

$ PAL2
4.

A command has been included to display a list of all the
assignments and commands that are set up on execution of
the PALASM 2 software set-up procedure. To see this
information input the command

$ PAL2HLP
5.

To link each of the programs in the PALASM 2 software suite
you will use a set of commands, one for each program,
which are also shown on input of the help command
(PAL2HLP).

For users who have source files, these files have the
extensions <program name>. VMS. To compile and link
these source programs a set of command procedures exist,
one for each program:
BLDCVT.COM .... compile & link PDSCNVT
BLDFEP.COM .... compile & link PALASM2
BLDXPT.COM .... compile & link XPLOT
BLDSIM.COM .... compile & link SIM
BLDZHL.COM .... compile & link ZHAL
BLDJED.COM .... compile & link JEDMAN
BLDPRA.COM .... compile & link PROASM
BLDPRS.COM .... compile & link PROSIM

These procedures all execute the program VXPASCAL.COM
when compiling. Edit this program if you want to alter compile
times
A complete list of all the files on the VAX-VMS tapes can be

Monolithic

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A·9

INSTALLATION AND OPERATION

found in the Release Notes at the end of this manual.

ASCII TAPE
INSTALLATION
Tape Description
Your ASCII magnetic tape, which contains all the files required
by PALASM 2 software, has been formatted in the following
manner:

ASCII characters

no tape label

tape density = 1600

record size = 132 bytes

block size = 6600 bytes (50 records)

The first file on the tape contains a list of file names. (See
Release Notes.) In order to process this tape, you must provide a
utility to read the first file off the tape, extract the file names and
then copy each file from the tape renaming each with the correct
file name. The first file on the tape corresponds to the first file
name on the file name list file. Please note that the source code
on the ASCII tape is in a non-compilable form and needs
modification for the computer environment you are using.

Reading In an ASCII
Tape On a VAX-VMS
System
The following command file can be used to read in a PALASM 2
software ASCII tape on a VMS system:

$ ON CONTROL Y THEN GOTO DONE

A·10

Monolithic

!RiD Memories

INSTALLATION AND OPERATION

$ ON SEVERE ERROR THEN GO TO DONE
$ IN DEVICE := "MTAO:"
$ ALLOCATE 'IN- DEVICE' IN- VOLUME
$ MOUNT/FOREIGN/RECORDSIZE=132/
BLOCKSIZE=6600 'IN DEVICE'
$ COPY/LOG 'IN DEVICE' FILE.LST
$ OPEN/READ/ERR=DONE IPF FILE.LST
$ READ/END=DONE IPF FNAM
$ LP1:
$ READ/END=DONE IPF FNAM
$ LGO='F$LOCATE(" ", FNAM) ,
$ FILNAM := 'F$EXTRACT(O,LGO,FNAM)'
$ COPY/LOG 'IN DEVICE' 'FILNAM'
$ GOTO LPl
$ DONE
$ CLOSE IPF
$ DISMOUNT/NOUNLOAD IN VOLUME
$ DEALLOCATE 'IN DEVICE'
$ EXIT
File Description
Following is a description of the files on this tape.

Extension/Name

Description

*.SRC
*.lNC

Source code for PALASM 2 software
The global-include file data for PALASM
2 software
PALASM 2 software run-time data files
VAX-VMS command procedure to install
a PALASM 2 software VAX-VMS tape on
a VAX computer
Installation documentation
Help facility information
System logical assignments needed to
run PALASM 2 software on VAX-VMS
Procedure to execute PALASM 2

*.PDF
INSTALL.COM

README.ASC
PAL2HLP.FAC
PAL2ASS.COM
PAL2.COM

Monolithic

IFJJ] Memories

A·11

INSTALLATION AND OPERATION

BLD*.COM
LNK*.COM
VXPASCAL.COM
*.PDS
PAL2EX.LlS
PAL2EX.COM

software on the VAX-VMS
VAX-VMS procedures to compile each
source module
VAX-VMS procedures to link each
program
VAX-VMS Pascal compile module
procedure
PALASM 2 software design examples
List describing all the design examples
VAX-VMS command procedure to
execute the design examples

VAX-UNIX
INSTALLATION
What You Require
*

PALASM 2 software on a VAX-UNIX magnetic tape

Berkeley 4.2 UNIX operating system

Berkeley Pascal compiler (or any compatible compiler)

Software Installation

To install PALASM 2 software, follow these steps
1.

Create a directory or SUb-directory for PALASM 2 software.
Name it PALASM so that it is easily identifiable. To
accomplish this, enter

$ mkdir palasm

A·12

Monolithic

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INSTALLATION AND OPERATION

2. To move to the PALASM directory, type

$ cd palasm
3. Remove the ring from the magnetic tape, load it on the
appropriate drive, and set it online.

4. To read the PALASM 2 software files from the magnetic tape
to the PALASM directory you have just created, type the
command

$ tar xu

5. To complete the installation procedure, you must execute
the command procedure INSTALL.COM. Type

$ install.com
6. To make the PALASM 2 software available to general users,
each user must set a $PATH variable that searches for
commands in the PALASM directory.

Or
The UNIX system manager must place the commands in a
system directory.
Your PALASM 2 software is now ready for use on the UNIX
operating system. Below are some additional pOinters.

Command Procedures

•

To access the PALASM 2 example design files (PDS files)
along with a brief description of each, enter the command

$ cat pa12lis.doc

A·13

INSTALLATION AND OPERATION

To successfully run the example PDS files, you must
execute a command procedure. This procedure enables
you to run the syntax checker and to produce fusemaps.
Enter

$ pa12ex.com <filename>
*

You can run various parts of PALASM 2 software in batch
mode by executing the command

$ pa12.com
*

For a listing of all the commands that were set up on
execution of the PALASM 2 installation procedure, type

$ cat pa12hlp.fac
*

To create each of the programs in the PALASM 2 software
suite, type

makeall
Note: Remember to type commands in lowercase. Filenames
are read only if they are in the following format: <filename.EXT>.
Notice that the filename is in lowercase, but the extension is in
uppercase. The JEDMAN output files, however, are exceptions.
Both filename and extension must be in uppercase. For
example: <JEDMAN.EXT>.

A·14

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APPENDIX B
PROGRAMMER
NOTES
DATA 1/0
Helpful Hints
DATA I/O's EPROM revision changes Monolithic Memories
manufacturer code from "95" to "22" in the JEDEC family code.
Please check that your PIT adapter 303a-002 is rev 06 or later.
Firmware updates accept a checksum of 0000 as valid and space
before the L field data. Both of these were flagged as errors by
old Data I/O firmware: Please update your Logic Pak to rev 04 or
later. You will also notice higher programming yields from this
update.

Downloading
These notes are to be used in conjunction with the Data I/O
model 29 AlB programmer and PALASM 2 software.
1. Create a JEDEC file using PALASM 2 software. The JEDEC
file produced by the XPLOT backend module has .JED as
the extension to its filename.
2.

Using a screwdriver, set the programmer to the desired baud
rate. Twist the circular notch located at the bottom left

Monolithic

Memories

B·1

PROGRAMMER NOTES

of the back of the machine until the white arrow pOints to the
letter C. This is the recommended baud rate (4800 baud).
Codes for the other baud rates are listed in Table 8-1.

Table B·1:
Recommended Baud Rate
Code

Baud rate

5
7

300
1200
2400
4800

A
C

B·2

Power on the Data 1/0. When it finishes its self-test, press
<COpy> from <DEVICE> to <RAM> <START>. The
programmer will then ask for the device family pin code.
The codes for Monolithic Memories devices are listed in
Table 8-2.

Monolithic

W Memories

PROGRAMMER NOTES

Table B·2:
Device Family Pin Codes for DATA I/O Programmer
Device

Family Pin Code

PAL 10HB/HB-2
PAL 1OLB/LB-2
PAL 10H20GB
PAL 10H20PB
PAL 12H6/H6-2
PAL12L10
PAL 12L6/L6-2
PAL 14H4/H4-2
PAL 14L4/L4-2
PAL14LB
PAL16C1/C1-2
PAL 16H2/H2-2
PAL 16L2/L2A
PAL 16L6
PAL 16LB/LB-2/LB-4/LBA
PAL 16LBB
PAL 16PB/16RAB
PAL 16R4/R4-2/R4-4/R4A
PAL 16R6/R6-2/R6-4/R6A
PAL 16RB/RB-2/RB-4/RBA
PAL16RP4
PAL 16RP6
PAL16RPB
PAL1BL4
PAL20C1
PAL20L10

221B
2213
2242
2242
2219
2201
2214
2220
2215
2202
2221
2222
2216
2203
2217
3017
2230
2224
2224
2224
2231
2231
2231
2204
2212
2206

Monolithic

W Memorl.s

B·3

PROGRAMMER NOTES

Table B·2 (Continued):
Device Family Pin Codes for DATA 1/0 Programmer

8·4

Device

Family Pin Code

PAL20L2
PAL20L8
PAL20S10
PAL20R4
PAL20R6
PAL20R8
PAL20RA10
PAL20RS10
PAL20RS4
PAL20RS8
PAL20X10
PAL20X4
PAL20X8
PAL22RX8
PAL22V10
PAL32R16
PAL32VX10
PAL 6L16
PAL64R32
PAL8L14
PMS14R21

2205
2226
2243
2227
2227
2227
2245
2244
2246
2244
2223
2223
2223
2278
4628
2247
2277
2248
2284
2249
2258

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W l#IIemorles

PROGRAMMER NOTES

Next, run PC2 (PALSETUP mode) on your PC. Use the
following RS-232 parameters:4800 baud, 7 data bits, 1 stop
bit and even parity.
These parameters are stored in the PC2.DAT file. If you do
not wish to run PALSETUP, a quick and dirty way to modify
the parameters is to edit the PC2.DAT file directly.

Run PC2 next. You can specify the filename by using
function key F9. When it prompts you for the name of your
input file, respond with the dilename>.JED generated by
the PALASM2 program.

After specifying the filename, PC2 blanks the screen and
indicates its command options: F1 (for downloading), F2
(PALSETUP mode), F3 (VIEW toggle), F4 (CAPT mode), F9
(filename) & F10 (return to DOS). Do NOT begin
downloading yet.

To verify communications press <SELECT> <E> <1>
<START>. This will produce the Data I/O operations menu
on your screen. (You will have to enter the FAMILY/PIN code
from the IBM-PC keyboard if it has not been entered on the
programmer keyboard.)
If you are not successful in getting the Data I/O to talk to the
PC, repeat the steps above. If problems still exist, confirm
the cabling between the RS232 ports.

Next, press <SELECT> <E> <B> <START> on the Data I/O.
The window of the programmer will display a clock face.
Press F1 (IBM-PC). Downloading will begin and the clock
face should start to turn.

When downloading is completed, press F10 to exit. The
Data I/O should indicate a 4-digit fuse checksum on its
display if the process has been successful. You can now
program the part.

Monolithic

Memories

8-5

PROGRAMMER NOTES

Using DATA 1/0 on
VAX-VMS
Figure B-1 illustrates the cable connections that must be made
between a VAX-VMS system and a Data I/O programmer, plus an
example command procedure that will enable you to program on
VAX-VMS systems.

MODEL 29

VT220

********

1
2
3

*
*

*
*
*

*
*
\ ........... *
*

4
6
7

1
3
2
4

5
6
7

********

25-pinmale

9-pin female

Figure B-1:
Data I/O <-> VAX·VMS Cable Connection

To download from the VAX, do the following:
A. Model29

B·6

Copy DEV to RAM with appropriate family and pinout code.

Select EB and start.

Monolithic

W Memories

PROGRAMMER NOTES

VT220: VAX-VMS Program
To Make DATA 1/0
Connection
Monolithic Memories recommends the use of the following
program, and would like to acknowledge John Carvalho of RCA
who created it.
1. Type @PALCOPY PALNAME.JED where PALCOPY is the
name of this command procedure file.

$ON CONTROL_Y THEN EXIT
$ON ERROR THEN EXIT
$IPFNAM := 'Pl'
$IF Pl .NES."" THEN GOTO FNAMl
$INQUIRE Pl "PLEASE ENTER THE NAME
$OF THE FILE TO BE TRANSMITTED"
$IF Pl .EQS. "" THEN GOTO PALXIT
$FNAM1:
$IPFNAM := 'Pl'
$LN = 'F$LEN(IPFNAM)'
$DOT = 'F$LOCATE (".", IPFNAM) ,
$IF DOT.EQ.LN THEN
$IPFNAM:='" 'IPFNAM' . JED"
$XMTFIL:
2. Set up the VT220 for write through printer mode.

$WRITE SYS$OUTPUT "TRANSMITTING
$FILE""IPFNAM'"''
$WRITE SYS$OUTPUT"[<ESC> 51"
$TYPE 'IPFNAM'
$WRITE SYS$OUTPUT"<ESC>[4I"

Monolithic

W Memories

B·7

PROGRAMMER NOTES

Drop the VT220 out of write-through mode.

$WRITE SYS$OUTPUT "DOWNLOAD
$COMPLETE"
$OPEN/READ INDATA 'IPFNAM'
$LINEl
""
$LINE2 = ""
$LINE3 = ""
$RDLOOP:
$READ/END OF FILE=DONE INDATA LINE3
$LINEl = LINE2
$LINE2 = LINE3
$GOTO RDLOOP
$DONE:
$CLOSE INDATA
$WRITE SYS$OUTPUT "THE CHECKSUM IS:"
'LINE1' ----'LINE2'"
$PALXIT:

a·8

I6onoIIthlc W"'emorles

PROGRAMMER NOTES

VARIX OMNI
Helpful Hints
For designs involving the PAL64R32 MegaPAL device, an
additional file with extension .VRX is generated. It contains the
specific fuse plot to be downloaded to the VARIX programmer. A
full (not brief) fuse plot must be specified for VARIX downloading
when using MegaPAL devices.

Downloading
To begin, connect the Varix programmer to your PC. You must
have the parallel port card supplied by Varix installed in the PC.
Once the card is installed, connect the Varix to the PC with the
cable supplied by Varix (observe the proper connector labels:
the cable is not symmetric). You should also have revision
3.16a or later OMNI software for programming the PAL64R32,
and revision 3.18e or later OMNI software for programming
the PAL32R16 and all20-pin and 24-pin PAL devices.
1.

Turn on power to the programmer. Plug the PAL32R16 or
PAL64R32 adapter into the largest socket on the
programmer. No adapter is required for programming 20pin or 24-pin PAL devices.

Insert the Omni software diskette supplied by Varix in drive
A. Insert the diskette with the PALASM 2 fuse plot in drive
But if you are using OMNI software revision 3.16a. Insert
the diskette with JEDEC files in drive B if you are using
OMNI software revision 3.18e.

Note: The file extensions of JEDEC files must be .JED;
otherwise OMNI software will refuse to accept them, or will treat
the files as if they are fuse plots. You will need to rename any
.JDC files you wish to use.

IIIIonoIlthlc

W lIIIemories

8·9

rnvunAMMcn

NUIC~

Type OMNI <CR> . The following message is displayed:

Omni-Programmer for the IBM PC
Version x.yy Copyright (c)1984
Varix Corporation
Please select target device (or type
? for list) :
In response to this message you can either enter? to get a
list of the part codes, or a specific code such as 64R32.

For OMNI software revision 3. 16a: The help menu is
displayed after the part code is entered.
For OMNI software revision 3. 18e: The command prompt *
is displayed. Type H or M to get either the brief or the
detailed help menu respectively. Type H PROGRAM to
get the help menu for programming commands.
Note: The Varix software displays * as a command prompt. Thus
when a command has finished executing, the * is displayed.
4.

Plug a device into the proper adapter socket.

Verify that the part is blank.

For OMNI software revision 3. 16a: Type V B
For OMNI software revision 3. 18e: Type F X 0 130 to fill the
memory buffer with X; then type V 0 130 to verify that the
part on the socket is blank.
6.

Load the buffer storage in the Varix programmer with the
fuse data stored in the file that was created in PALASM 2.

For OMNI software 3. 16a: Enter L <filename>.VRX <CR>.
For OMNI software 3. 18e: Enter L <filename>.JED <CR>.

B·10

IWonoIIthlt:

u.n

Memories

PROGRAMMER NOTES

Note: You should substitute the name of the file containing
XPLOT in drive B: for filename in the command above. You don't
have to specify drive B in the command: it is already assumed by
the software.
7.

Display the contents of the Varix buffer starting at the "first
parameter" product term, for "second parameter" product
terms following. The example is set up to display the entire
contents of a buffer containing a 32R16 or 64R32 XPLOT.
Enter D 0 128 for 32R16, or D 0256 for 64R32. When this
command is executed the screen will display the product
terms contained within the buffer.
For OMNI software 3. 16a: Enter D 0 256 <CR>.
For OMNI software 3. 18e: Enter D 0 128 <CR>.

Program the PAL device. The reasoning for the
parameters is the same as in step 7; thus, to program an
entire 32R16, enter DO 128; enter D 0256 to program a
64R32.

For OMNI software 3. 16a: Enter P 0 256 <CR>.
For OMNI software 3. 18e: Enter P 0 128 <CR>.

Program the flush (bypass) fuses of the PAL device.
For OMNI software 3. 16a: Enter P F <CR>.
For OMNI software 3. 18e: Enter P F <CR>.

10.

Program the polarity fuses of the PAL device.
For OMNI software 3. 16a: Enter P 0 <CR>.
For OMNI software 3. 18e: Enter P 0 <CR>.

11. Verify that the PAL device has been programmed properly.

Monolithic

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8·11

PROGRAMMER NOTES

The parameters follow the same reasoning as in the D and
P commands.
For OMNI software 3. 16a: Enter V 0256 <CR>.
For OMNI software 3. 18e: Enter V 0128 <CR>.

While this command is executing you will see the product term
numbers displayed as each is verified as correct. If an
inconsistency occurs between what is in buffer storage and what
is in the device, the buffer and device product terms will be
displayed. If no inconsistencies are discovered, you can assume
that the part has been programmed properly.
12.

To upload the contents of the device in the socket to the
buffer RAM of the programmer:
For OMNI software 3. 16a: Enter R 0 25R coeR,>
For OMNI software 3. 18e: Enter R 0 128 <CR>.

13.

To observe the contents:
For OMNI software 3. 16a: Enter D 0 256 <CR>.
For OMNI software 3. 18e: Enter D 0 128 <CR>

14.

To exit the OMNI software:
For OMNI software 3. 16a: Enter X <CR>.
For OMNI software 3. 18e: Enter QUIT <CR>.

8·12

MonollthleW Memories

APPENDIX C
DEVICE SPECIFIC
SYNTAX
The unique architectures of the PAL22RX8, the PAL22V10, and
the PAL32VX10 devices require special syntax considerations.
This appendix provides special instructions for designing with
the three devices. Note that only Boolean equation design
instructions are included. PALASM 2.22 is being tested for state
machine design entry for PAL devices.
If your regular package of PALASM 2.22 software does not
contain a design examples disk, contact your local Monolithic
Memories sales office for a disk of design examples.

The EXAM PLES. DAT directory contains two subdirectories of
design examples:
*
*

State
Boolean

Refer to Appendix D for a list of design examples and
descriptions of the designs.

WIohollthlc W.emories

C-1

DEVICE SPECIFIC SYNTAX

PAL22RX8 AND
PAL22V10:
SPECIAL
INSTRUCTIONS
The following special syntax considerations are the same for the
PAL22RX8 and PAL22V10.

Special Syntax for
PAL22RX8 and

PAL22V10
The pin list for a PAL22RX8 includes the pin names you would
expect for this 24-pin PAL device, followed by a name used to
specify the global .SETF and .RSTF functions of the registers.
Example:

CHIP INPUT OUTPUT PAL22RX8
CLK 12 13 14 15 16 17 18 19 110 III GND
113 114 015 016 017 018 019 020 021 022
123 VCC
GLOBAL
On PAL22RX8, there is only one Exclusive-Or gate per output.
Each output equation can therefore contain at most one
Exclusive-Or function (of two terms). If you use the Exclusive-Or
in your equation, then you must not also use it as a polarity
inverter. Thus, if you define an output with an Exclusive-Or, the
polarity of the output must be the opposite of that given in the
pin list. (e.g. /015 := ... if 015 is the name used in the pin list.)
On both the PAL22RX8 and the PAL22V10 devices, you can
use the name given in the pin fist and .SETF or .RSTF to specify
the global SET and RESET functions.

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DEVICE SPECIFIC SYNTAX

GLOBAL.SETF = producCterm

Specifies the global
SET function

GLOBAL. RSTF = producUerm

Specifies the global
RESET function

Note: You are allowed to use only one product term for these
functions

PAL32VX10:
SPECIAL
INSTRUCTIONS
The PAL32VX10, also a 24-pin device, has associated with it a
number of architectural features unique in the PAL device family.
Each output has a programmable flip-flop, which can be
configured as a J-K, S-R, Tor D type. Each register can be
buried so that its contents cannot be observed directly on the
output pin. Each output has an internal Exclusive-OR gate which
can either be used as such or as a polarity inverter, depending on
the application. The XOR gate also allows the user to create the
various flip-flop types. In addition, you can set outputs as
Registered or Combinatorial (and set the register type)
dynamically, specifying the option you want through a product
term.

-.:.

Along with these special features of the PAL32VX10
architecture, there are some special rules which need to be
observed while using PALASM 2 software on this device.

Special Syntax for
PAL32VX10
The pin list for a PAL32VX10 includes the expected pin names
followed by a name used to specify the global .SETF and .RSTF
functions of the buried registers. This is followed by ten names
used to specify the buried registered nodes located at the /0

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C-3

DEVICE SPECIFIC SYNTAX

outputs of the buried registers at pins 14 through 23
respectively.
Example:

CHIP INPUT OUTPUT PAL32VX10
CLK 12 13 14 15 16 17 18 19 110 III GND
113 014 015 016 017 018 019 020 021 022
023 VCC
GLOBAL R14 R15 R16 R17 R18 R19 R20 R21
R22 R23
(The relationship between the buried registered node names
and output names in the pin list is such that R14 corresponds to
014, etc.)

Output EquationsBuried Registered
Node
When the output you want is a registered function of product
terms, you must define it this way at the buried registered node.
If you want the output to be used only for feedback, you do not
need to also define it at the output node. However, if you want
the output to be visible at the output pin, you must also define it
at the output node by specifying either Onn := Rnn or Onn :=
IRnn, depending on your polarity preference.

Note: that the output node must be defined as a function of
the buried registered node when one has been defined.

C-4

Monolithio

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DEVICE SPECIFIC SYNTAX

Output EquationOutput Node
When the output you want is a combinatorial function of product
terms, you must define it this way at the output node. In this
case, the buried registered node must not be defined.
Because there is only one ANDIOR array for each output, you
can define either the buried registered node or the output node
as a sum of products, but not both. Follow the rules above for
defining registered or combinatorial outputs, and you should
meet this requirement.
The PAL32VX10 has only one Exclusive-Or gate per output.
Each output equation can therefore contain at most one
Exclusive-Or function (of two terms). If you use the ExclusiveOr in your equation, then you must not also use it as a polarity
inverter. Thus, if you define a buried registered node or output
node with an Exclusive-Or, the polarity of the node must be the
opposite of that given in the pin list. (e.g. '/R14 := .. .' if 'R14' is
the name used in the pin list.)
You may use the name given in the pin list and .SETF or .RSTF to
specify the global SET and RESET functions.
GLOBAL.SETF = produccterm

Specifies the global SET
function.

GLOBAL.RSTF = producCterm

Specifies the global
RESET function.

Note: You are allowed to use only one product term for these
functions.

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c·s

DEVICE SPECIFIC SVNT AX

.CMBF Function
After defining an output node either as a function of a buried
registered node or as a function of product terms, you can use
the .CMBF function to override the definition selected using the
:=, = convention for registered or combinatorial output. This
provides for dynamic selection of registered or combinatorial
output.
Onn.CMBF

= VCC

specifies a fixed combinatorial output.
Onn.CMBF

= GND

specifies a fixed registered output.
Onn.CMBF

= producCterm

specifies a dynamically selected registered or combinatorial
output, depending on whether the result is high or low.
Example:

014
:= <product_term>
014.CMBF
VCC
This is a registered output, but is defined in terms of a
combinatorial equation. You need not use the .CMBF if you do
not want dynamic selection.
Note: You are allowed to use only one product term for these
functions.
Note: The Examples disk contains a complete PAL32VX10
design specification example.

e-G

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lIIIemories

APPENDIX D
PAL DESIGN FILE
LIBRARY
(Files Located on Design Examples Disk)

If your regular package of PALASM 2.22 software does not
contain a design examples disk, contact your local Monolithic
Memories sales office for a disk of design examples.
The EXAMPLES.OAT directory contains two subdirectories of
design examples:
*
*

State
Boolean

Table 0-1 lists all examples in the order they appear in the
subdirectories.
Descriptions of most of the examples follow the table.

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D·1

PAL DESIGN FILE LIBRARY

Files Located
File Name
32VX10.PDS

Table D-1:
On Design Examples Disk

Description

Device

Example of PAL32VX10 Design
Specification File

PAL32VX10

Traffic Signal Controller
OIC-02 Command Decoder
ENCODER.
4-Way Traffic Light Controller

PMS14R21
PMS14R21
PAL20R8
PMS14R21

State Subdirectory
STRAFFIC.PDS
PRODCDER.PDS
OAM3.PDS
4WAYTRAF.PDS

Boolean Subdirectory
9BITCNT.PDS
8COUNT.PDS
DCOUNT.PDS
CONTROL.PDS
OCTCOMP.PDS
3T08DMUX.PDS
CRT.PDS
PORT.PDS
BARREL.PDS
4CNT.PDS
4-16DEC.PDS
10COUNT.PDS
ADREG16.PDS
MEMIO.PDS
UPCOUNT.PDS
FLiPFLOP.PDS

D·2

9-Bit Counter
8-Bit Counter
5-Bit Down Counter
DEC PDP-11 Unibus Interrupt
Controller
Octal Comparator
3-8 Demultiplexer
CRT Controller Logic
7-Bit I/O Port with Handshake
Logic
Barrel Shifter
4-Bit Counter
4 - 16 Decoder
10-Bit Counter
16-Bit Addressable Register
PC I/O Mapper
5-Bit Up Counter
Basic Flip Flops

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PAL20X10
PAL20X8
PAL20RA10
PAL20RA10
PAL16C1
PAL16R8
PAL20RA10
PAL20RA10
PAL64R32
PAL16RP4
PAL6L16
PAL20RS10
PAL32R16
PAL8L14
PAL20RA10
PAL16RP8

PAL DESIGN FILE LIBRARY

Table D-1 (Continued):
Files Located On Design Examples Disk
File Name
MEMORY.PDS
ARBITER.PDS
LlNK.PDS
LATCH.PDS
9BITREG.PDS
10BITREG.PDS
BTRAFFIC.PDS
DCODER.PDS
K7ENC1.PDS
K7ENC2.PDS
COUNTER .PDS
B8ZSA.PDS
B8ZSB.PDS
B8ZSC.PDS
CRC6.PDS
DEC_R8.PDS
SUPER.PDS
FDP.PDS
SYNC.PDS
V32_2.PDS
TREL12.PDS
UDCOUNT.PDS
9BCASC1.PDS

Description
Memory Handshake Logic
3-Bit Arbiter
Serial Data Link Controller
Octal Latch
9-Bit Register
10-Bit Register
Traffic Signal Controller
QIC-02 Command Decoder
1/2 Rate Convolution Code
Encoder
1/2 Rate Convolution Code
Encoder
Counter
Encoder PAL-A
Encoder PAL-B
Encoder PAL-C
Error Detection PAL
Decoder PAL
Super Frame PAL for
T1 Interface
T1 Frame Detection
PAL for T1 Interface
T1 Frame Sync PAL
for T1 Interface
Trellis Encoder
Trellis Encoder
10-Bit Loadable, Even
Boundary Up/Down Counter
9-Bit Cascadable Counter, Look
Ahead Carry

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Device
PAL16RP6
PAL20RA10
PAL20RA10
PAL10H20P8
PAL20X10
PAL20X10
PAL16RP8
PAL20L8
PAL32VX10
PAL22V10
PAL22V10
PAL16R8
PAL16R6
PAL16R6
PAL20R6
PAL16R8
PAL16R6
PAL16L8
PAL20R4
PAL20RS8
PAL20RS8
PAL20X10
PAL20X10

D·3

PAL DESIGN FILE LIBRARY

Table 0-1 (Continued):
Files Located On Design Examples Disk
File Name
9BCASC2.PDS
VIDEO.PDS
BBENCODE.PDS
PIPELlNE.PDS
LlFORAM2.PDS
180DEGC.PDS
8BAPPREG.PDS
128LRAM.PDS
PORTADPT.PDS
VIDSREG.PDS
VLSYNCG.PDS
LlFORAM3.PDS

D·4

Description
9-Bit Cascadable Counter, MSD
Video Shift Register.
with Attributes
Manchester Encoder
for.Byte and Bit Inputs
Pipeline Controller for Instruction
Registers.
LIFO RAM Controller
Pattern 02 of 2 (8K DEEP)
180 -Degree Up/Down Counter
8 -Bit Successive Approximation
Register
LIFO RAM Controller
for 128-Deep Stack
M68020 32-/16-/8-Bit
Port Adaptor
Video Shift Register PAL 3 of 3
Video Line Sync Generator
RAM-Based LIFO

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Device
PAL20X10
PAL20X8
PAL22V10
PAL16R8D
PAL20X8
PAL20X10
PAL20RS10
PAL32VX10
PAL20RA10
PAL32VX10.
PAL32VX10
PAL22RX8

PAL DESIGN FILE LIBRARY

32VX10 SYNTAX
EXAMPLE
PAL32VX10

32VX10.PDS

Example on how to program Boolean equations for a
PAL32VX10 part.

STATE SYNTAX
EXAMPLES
STRAFFIC.PDS

Traffic Signal
Controller

PRODCDER.PDS QIC-02 Command
Decoder

PMS14R21

This application implements a QIC-02 command decoder using a
PROSE device, a PAL device, and a PLE device.
QAM3.PDS

ENCODER.

PAL20R8

Note: Use this file with PALASM 2 software version 2.23 or
later. Otherwise, errors will be detected with the .OUTF
equations.
4WAYTRAF.PDS

Monolithic

4-Way Traffic Light
Controller

mIFJ] Memories

PMS14R21

D-S

PAL DESIGN FILE LIBRARY

BOOLEAN
EQUATIONS
EXAMPLES
9BITCNT.PDS

9-Bit Counter

PAL20X10

The 9-bit synchronous counter has parallel load, increment, and
hold capabilities. The carry out pin (/CO) shows how to implement
a carry out using a register by antiCipated one count before the
terminal count if counting and the terminal count if loading.
Operations Table
IOC

ClK

IlD

D8-DO

08-00

Operation

H
l
l
l

X
X

l
H

Z
0
D
OPlUS 1

HI-Z
Hold
load
Increment

l
C
C

8COUNT.PDS

8-Bit Counter

PAL20X8

This 8-bit upldown counter has the hold and load capabilities. It
sets all the outputs high if SET=high. It loads new value when
SET=Iow and lOAD=high. Else it counts up if UP=high and
counts down if UP=low.

DCOUNT.PDS

5-Bit Down Counter

PAL20RA 10

CONTROL.PDS

DEC PDP-11
Unibus Interrupt
Controller

PAL20RA10

OCTCOMP.PDS

Octal Comparator

PAL16C1

The octal comparator establishes when two 8-bit data strings (A7AO) and (87-80) are equivalent (EO=H) or equivalent (NE=H).

D-6

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PAL DE::)U..iN I-ILt:. LII:SIiAIiY

3T08DMUX.PDS

3-8 Demultiplexer

PAL16R8

The 3-to-8 demultiplexer with control storage provides a
conventional 8-bit demux function combined with control storage
functions:load true, load complement, hold, toggle, polarity, clear
and preset. Five inputs(!lO,lClR,IPR,POl, TOG) select one of
six operations. The six operations are summarized in the
following operations table:
Control
IOC ClK
H
l
l
l
l
l
l

X
C
C
C
C
C
C

Functions
IClR IPR IlO
X
l
H
H
H
H
H

X
X
l
H
H
H
H

Polarity
POL TOG

X
X
X
l
l
H
H

X
X
X
H
l
X
X

X
X
X
X
X
l
H

Inputs
ABC

Outputs
07-00
Operation

X
X
X

X
X

Z
l
H
MUX
IMUX
0

HI-Z
Clear
PRESET
load true
load COMP
Hold
Tog polarity

CRT.PDS

CRT Controller Logic

PAL20RA 10

PORT.PDS

7-Bit 1/0 Port with
Handshake Logic

PAL20RA10

BARREL.PDS

Barrel Shifter

PAL64R32

The 16-bit barrel shifter will shift 16 bits of data (015-00) a
number of locations into the output pins, as specified by the
binary encoded input. Inputs are shown by O. Si are shift amount
inputs and OJ are outputs. 16 product terms in each output pair
are directed to one output; thus only 16 out of 32 output pins are
used.

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D·7

PAL DESIGN FILE LIBRARY

4CNT.PDS

4-Bit Counter

PAL16RP4

The 4-bit counter counts up or down and has the clear and load
capability. The clear operation overrides count and load. The
counter counts up when CLR=low, LOAD=low, and UP=high.

4-16DEC.PDS

4 - 16 Decoder

PAL6L16

The 4 to 16 decoder, decodes four binary decoded inputs into
one of 16 mutually exclusive outputs, whenever the two enable
lines EN1 and EN2 are high. When one or both of the enable
lines are low the outputs are all set to high values.

10COUNT.PDS

10-Bit Counter

PAL20RS10

The 1O-bit counter increments on the rising edge of the clock
input (ClK), if CNT input is high. The outputs are HIGH-Z when
the enable line (/OE) is high and enabled when the enable line
(/OE) is low. The counter is cleared (all lows) if CLR=HIGH.

ADREG16.PDS

16-Bit Addressable
Register

PAL32R16

The 16-bit addressable register loads one of 16 registers
selected by ADDR[O .. 3] with data input, DATA.

MEMIO.PDS

PC I/O Mapper

PAL8L14

Personal computers which are hardware compatible with the
ubiquitous IBM PC share this 1/0 map.

0·8

UPCOUNT.PDS

5-Bit Up Counter

PAL20RA10

FLIPFLOP.PDS

Basic Flip Flops

PAL16RP8

MEMORY.PDS

Memory Handshake Logic
PAL 16RP6

ARBITER .PDS

3-Bit Arbiter

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PAL20RA10

PAL DESIGN FILE LIBRARY

L1NK.PDS

Serial Data Link
Controller

PAL20RA10

LATCH.PDS

Octal Latch

PAL 1 OH20P8

The octal latch is an 8-bit latch with load, hold and clear capability.
Clear sets all outputs to low and overrides hold. load operation
loads inputs (00-07) into the latch. The hold operation holds the
previous values of (00-07).

9BITREG.PDS

9-Bit Register

PAL20X10

This is a design of a 9-bit register with parallel load and hold
capabilities. The operations of this register are summarized in the
following operations table:

IOC

ClK

H
l
l

IlO

08-00

1
1

H
l

X
X

10BITREG.PDS

08-00
Z
0
0

10-Bit Register

Operation
HI-Z
Hold
load

PAL20X10

The 10-bit register loads the data (09-00) on the rising edge of
the clock(ClK) into the register(09-00). The data is held in the
register until the next positive edge of the clock.

IOC

H
l
l

ClK

09-00

X
X
Z
COO

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W Memories

Operation
HI-Z
load
Hold

D·9

PAL DESIGN FILE LIBRARY

BTRAFFIC.PDS

Traffic Signal
Controller

PAL16RP8

DCODER.PDS

QIC-02 Command
Decoder

PAL20L8

This PAL is part of the QIC-02 command sequencer design. The
primary purpose of this PAL is to encode 8-bit commands into 4bit command codes. This PAL is also used to encode tape drive
status signals and to select the drive number.
K7ENC1.PDS

1/2 Rate Convolution
Code Encoder

PAL32VX10

1/2 rate convolution code encoder, constraint length (k=7). This
PAL 32VX1 0 design implements a high speed convolutional
encoder with a constraint length k=7 and rate = 1/2. This
encoder is used commonly in conjuction with a Viterbi, trellis
decoding algorithm. Applications include geostationary
satellite communication, high speed local loop bypass networks
etc.
K7ENC2.PDS

1/2 Rate Convolution
Code Encoder

PAL22V10

Convolution code encoder, constraint length (k=7). This PAL
22V10 design implements a high speed convolutional encoder
with a constraint length k=7 and rate = 1/2. This encoder is used
commonly in conjuction with a Viterbi, trellis decoding algorithm.
Applications include geostationary satellite communication, high
speed local loop bypass networks etc.
COUNTER .PDS

Counter

PAL22V10

Simulation of counter equations are a combination of active-high
or -low and register or combinatorial. Preload and global reset
functions are included.
B8ZSA.PDS

D·10

Encoder PAL-A

/IIhJno/ithlc W""emorles

PAL16R8

PAL DESIGN FILE LIBRARY

B8ZSB.PDS

Encoder PAL·B

PAL16R6

B8ZSC.PDS

Encoder PAL·C

PAL16R6

CRC6.PDS

Error Detection PAL

PAL20R6

The CRC-6 PAL performs error detection on a serial data stream.
CRC-6 PAL supports the T1 Fe standard for error detection. The
CRC result can be output either in serial or in parallel.

SUPER.PDS

Decoder PAL

PAL 16R8

Super Frame PAL for
T1 Interface

PAL16R6

This PAL counts the T1 Frames and controls the Signal Bits
extraction process, including Fly Wheeling. It also provides
various other signals which indicate the frames with Signal bits
The counter is reset with either RSTB or when frame detection is
SUNK and frame 1 occurs from two different sources (FRM1 &
SOF).
FDP.PDS

T1 Frame Detection
PAL for T1 Interface

PAL 16L8

This PAL monitors 12 193rd bits in the incoming T1 NRZ data
stream. It detects any valid Frame Patern (start of any Frame) and
the start of Frame 1.
SYNC.PDS

T1 Frame Sync PAL
for T1 Interface

PAL20R4

This PAL decides whether the T1 Interface is in Frame Sync,
Sync, or Out of Sync. It controls the Frame Sync process.

NIonoIlthlc

lIIIemories

D·11

PAL DESIGN FILE LIBRARY

TrellIs Encoder

PAL20RSS

This PAL performs the signal mapping onto the 32 state
constellation according to CCITT V.32, 9600 bps specification.
TREL 12.PDS

Trellis Encoder

PAL20RSS

This PAL performs the signal mapping onto the 32 state
constellation according to CCITT V.32, 9600 bps specification.
UDCOUNT.PDS

10-Blt Loadable,
Even Boundary
Up/Down Counter

PAL20X10.

9BCASC1.PDS

9-Bit Cascadable
Counter,.Look
Ahead Carry

PAL20X10

9BCASC2.PDS

9-Bit Cascadable
Counter, .MSD

PAL20X10

VIDEO.PDS

Video Shift Register.
with Attributes

PAL20XS

BBENCODE.PDS Manchester Encoder
PAL22V10
for. Byte and Bit Inputs

1).12

PIPELlNE.PDS

Pipeline Controller
for Instruction
Registers.

PAL 16RSD

L1FORAM2.PDS

LIFO RAM Controller
Pattern 02 of 2
(SK DEEP)

PAL20XS

1S0DEGC.PDS

1S0-Degree Up/
Down Counter

PAL20X10.

Monolithic WMemories

PAL DESIGN FILE LIBRARY

8BAPPREG.PDS 8-Bit Successive
Approximation
Register
128LRAM.PDS

LIFO RAM Controller
for 128-Deep Stack

PAL20RS10.

PAL32VX10

PORTADPT.PDS M68020 32-/16-/8- B it PAL20RA10
Port Adaptor
VIDSREG.PDS

Video Shift Register
PAL 3 of 3

PAL32VX10.

VLSYNCG.PDS

Video Line Sync
Generator

PAL32VX10

L1FORAM3.PDS

RAM-Based LIFO

PAL22RX8

Provides control and addressing for a PAL22RX8 32-locationdeep RAM-based LIFO.

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D·13

PAL DESIGN FILE LIBRARY

·0-14

lIIIonoilthlc

W lIIIemories

APPENDIX E
ERROR MESSAGES
ERRORS
REPORTED BY
PALASM2
Error Message

Error Number

1.................................. Unexpected EOF
2.................................. ldentifier name is too long
3 .................................. lIIegal character
4.................................. Malformed STRING declaration
5.................................. Variable is already declared
6.................................. lncomplete or invalid operator
7.................................. Bad for loop variable usage
8 .................................. Malformed expression
9 .................................. Expected an identifier
1O................................ Expected an operator
11 ................................ Expected =, too many strings
12 ................................ Illegal variable usage
13 ................................ Undeclared variable
14................................ Malformed variable
15 ................................ Unexpected part type
16 ................................ Unbalanced parens or brackets
17 ................................ Malformed statement
18 ................................ Missing keyword END
19 ................................ Missing keyword or section SI M
20 ................................ Missing keyword CHIP
21 ................................This array already declared
22 ................................ Expected keyword BIN
23 ................................ Expected a =
24 ................................Title not specified

INIonoIlthlc

Memories

E·1

ERROR

MESSAGES

25 ................................ Pattern not specified
26 ................................ Revision not specified
27 ................................ Author not specified
28 ................................ Company not specified
29 ................................ Date not specified
30 ................................ Missing keyword EQUATION
31 ................................ VCC, GND, NC not allowed here
32 ................................ Dangling equation found
33 ................................ Arch. defined as Mealy already
34 ................................ Arch. defined as Moore already
35 ................................ Pin defined as Reset already
36 ................................ Pin defined as Enable already
37 ................................ Missing keyword STATE
38 ................................ Missing keyword DEFAULT_BRANCH
39 ................................ Missing Argument
40 ................................ Redundant definition
41 ................................ Improper usage of setf or rstf. For
32VX10, proper usage is:
GLOBAL.setf/rstf .

ERRORS
REPORTED BY
XPLOT
XPLOT can detect a total of 52 errors (plus one warning) that are
identified uniquely by numbers. Depending on the type of error,
an error message alone appears on the terminal, or the name of
the pin where the error occurred is also reported. Once an error
is caught for an equation, further processing of that equation is
terminated, and the next equation is processed. The format for
error reporting is as follows:

E·2

ERROR NUMBER

:error number

:<name of the pin where the error
occurred>

Monolithic

W Memories

ERROR

ERROR MESSG.

MI:::::)::)Aut;::)

:error message explaining the type of
error

All the errors detected are device-related errors such as extra
pins, conflicting use of pins, extra number of product terms,
etc.

Warning Number

Warning Message

1 .............................................. CLOCK FOR THIS PIN
ASSUMED TO BE GND

Error Number

Error Message

O.................................. Unexpected end of input TRE or PAL
file, File invalid
This is caused by one of three possible
conditions:
A. XPLOT has been run on a design
that has syntax errors detected by the
frontend. (PALASM2.TRE will contain
the word ERROR).
B. The PDF orTRE file contains a
different version number from that
stored within the XPLOT program. (Rerun the PALASM 2 software frontend or
move the PDF file from the distribution
disk to where the XPLOT program can
locate it).
C. The PDF or TRE file is corrupted by
bad disk media or a disk error. (Get a
new, freshly formatted disk and repeat
processing.)

Monolithic

""emorles

E·3

t:HHUH

MESSAGES

1 .................................. This output is registered but another
output of same bank is used as
combinatorial.
2 .................................. This output is combinatorial but another
output of same bank is used as
registered.
3 .................................. This output is combinatorial but has
SET function defined
4 .................................. This output is combinatorial but has
RESET function defined
5 .................................. This output is combinatorial but has
CMBF function defined
6 .................................. This output is a combinatorial but has
CLOCK function defined
7 .................................. This output is using more than 8 product
terms
8 .................................. These outputs are using more than 16
product terms
9 .................................. The polarity of the output on the left
side of the equation should be
opposite to the polarity in the pin list
10 ................................ SET function has more than one
product term
11 ................................ This output is used as combinatorial but
is defined as registered output.
12 ................................ This output is used as registered but
is defined as a combinatorial output.
13 ................................ This output is a registered but has no
CLOCK function defined for it.
14 ................................ RESET function has more than 1
product term
15 ................................ THREE STATE function has more than
1 product term
16 ................................ CMBF function has more than 1 product
term
17 ................................ CLOCK function has more than 1
product term
18 ................................ This output is using more than 4 product
terms

E·4

Monolithic

IFJJl Memories

ERROR

MESSAGES

19 ................................ This output is using more than 7 product
terms
20 ................................ These outputs are using more than S
product terms
21 ................................ These outputs are using more than 14
product terms
22 ................................ The polarity of the output on the left side
of the equation should be same to the
polarity in the pinlist
23 ................................ This output is using more than 2 product
terms
24 ................................ This output cannot be used as a
feedback signal
25 ................................ Cannot define a simple/functional
equation for an input pin
26 ................................ This output is using more than 3 product
terms
27 ................................ This output is using more than one XOR
( :+:) term
2S ................................ This output is using more than two
product terms per one XOR term
29 ................................ This output is using more than four
product terms per one XOR term
30 ...................... : ......... This output is using more than 16
product terms
31 ................................ Pins allowed: XX Pins used: XX
32 ................................ Undefinable/unusable pin in this
equation
33 ................................ Simple/Functional equation already
defined
34 ................................ Cannot define functional equation for
this output
35 ................................ The product term XXX cannot be edited
36 ................................ Pins 23/14 do not have XOR function in
PAL20XS
37 ................................ Pins 23/22/21/14/15/16 do not have
XOR fnc. in PAL20X4
3S ................................ Programmable Combinatorial (.CMBF)
function not supported

Monolithic

W Memories

E·5

t:HHUH

Mt::S:SAuE~

39 ................................ XNOR (:*:) is not supported in any PAL
device
40 ................................ XOR (:+:) is not a legal operator for nonXOR PAL devices. e.g.
PAL16RB,PAL20S10 etc ...
41 ................................ The functional equation for this pin is
using a registered equation(:=) instead
of combinatorial equation (=).
42 ................................ PAL16A4 and PAL 16X4 are not
supported by XPLOT
43 ................................ PAL16C1 and PAL20C1 cannot have
more than one equation defined for an
output
44 ................................ Exceeded the maximum number of
tokens used per equation
4S ................................ This output is using more than 1 product
term
46 ................................ This output is using more than 6 product
terms
47 ................................ An output pin in the bank of this pin
was previously used as combinatorial.
This pin is now being used as
feedback. Output pins in
combinational bank cannot be used as
feedback.
4B ................................ An output pin in the bank of this pin
was previously used as feedback. This
pin is now being used as
combinatorial output. Output pins
used as feedback have to be
registered.
49A ............................. 20RA 10 Architectural/Application Errors
3: This output is combinatorial but has
SET function defined
4: This output is combinatorial but has
RESET function defined

E·6

"'onoIHhlcW"'emories

ERROR

MESSAGES

5: This output is combinatorial but has
CMBF function defined
6: This output is combinatorial but has
CLOCK function defined
13: This output is registered but has
no CLOCK function defined
49B ............................. Cannot have same polarity and also :+:
term in an equation
50A ............................. Token GND is not defined correctly in
pin list
50B ............................. Only one side of :+: gate can have more
than one product term
51 A .............................Token VCC is not defined correctly in
pin list
51 B ............................. Product terms already used by external
node equation
52 ................................ Product terms already used by internal
node equation
53 ................................ Registered equation for an OUTPUT pin
must only be in terms of its internal
node. Use internal nodes to define
registered equations.
54 ................................TRST equations should be defined only
as active high
55 ................................ SETF equations should be defined only
as active high
56 ................................ RSTF equations should be defined only
as active high
57 ................................ Setting >TRST=GND in a 32VX10
means that you cannot define the
output, since you have turned it off.
58 ................................ Proper usage is GLOBAl>RSTF = .. .
59 ................................ Using Xor not allowed for 22V1 0 part
60 ................................This output is using more than 10
product terms.

Monolithic IRlRD Memories

E·7

ERROR

MESSAGES

61 ................................ This output is using more than 12
product terms
62 ................................ This output is using more than 14
product terms.
63 ................................ Can not use XOR in Tristate equation
64 ................................ This part is not supported yet
65 ................................ Above PDF file not found
66 ................................ 0n IBM/PC, you cannot have the file
name without extension - more than 8
characters.
67 ................................ 0n vax, you cannot have filename
without extension - more than 11
characters
68 ................................ 8tate Machine syntax is not supported
by Xplot. Please run Expander Program
Note: For error number 68, run
MINIMIZE program, not Expander.

ERRORS
REPORTED BY
MINIMIZE
Error Number

Error Message

0010 ............................ 8imulation boolean equation missing.
0020 ............................ Boolean equation missing.
0030 ............................ lnvalid operator in boolean equation.
0040 ............................ Relational expression missing left-hand
side.
0050 ............................ Relational expression missing right-hand
side.
0060 ............................ Invalid operator in boolean equation.
0070 ............................ Relational expression missing left-hand
side.
0080 ............................ Relational expression missing right-hand
side.
0090 ............................ lnvalid operator in boolean equation.

E·8

Monolithic IFJJIltllemories

ERROR

MESSAGES

01 OO ............................ Relational expression missing left-hand
side.
011 O............................ Relational expression missing right-hand
side.
0120 ............................ lnvalid operator in boolean equation.
0130 ............................ Relational expression missing left-hand
side.
0140 ............................ Relational expression missing right-hand
side.
0150 ............................ Invalid opertor in boolean equation.
0160 ............................ Relational expression missing left-hand
side.
0170 ............................ Relational expression missing right-hand
side.
0180 ............................ lnvalid operator in boolean equation.
0190 ............................ Relational expression missing left-hand
side.
0200 ............................ Relational expression missing right-hand
side.
021 O............................ Logical operator missing left-hand side.
0220 ............................ Logical operator missing right-hand side.
0230 ............................ Logical operator missing left-hand side.
0240 ............................ Logical operator missing right-hand side.
0250 ............................ Logical operator missing left-hand side.
0260 ............................ Logical operator missing right-hand side.
0270 ............................ Logical operator missing left-hand side.
0280 ............................ Logical operator missing right-hand side.
0290 ............................ Logical operator missing operand.
0300 ............................ Logical unary operator has additional righthand side.
031 O............................ Simulation vcc has bad syntax.
0320 ............................ Simulation gnd has bad syntax.
0330 ............................ Simulation pin has bad syntax.
0340 ............................ Simulation state has bad syntax.
0350 ............................ Simulation condition has bad syntax.
0360 ............................ lIlegal Simulation boolean equation.
0370 ............................ lIlegal boolean equation.
041 O............................ Missing integer equation.
0420 ............................ Binary operator missing left-hand side.

Monolithic

W Memories

E·g

I:.HHOR

MESSAGES

0430 ............................ Binary operator missing right-hand side.
0440 ............................ Binary operator missing left-hand side.
0450 ............................ Binary operator missing right-hand side.
0460 ............................ Binary operator missing left-hand side.
0470 ............................ Binary operator missing right-hand side.
0480 ............................ Binary operator missing left-hand side.
0490 ............................ Binary operator missing right-hand side.
0500 ............................ Integer constant has bad syntax.
051 O............................ lnteger iterator has bad syntax.
0520 ............................ llIegal integer equation encountered.
0560 ............................ While statement missing boolean
equation.
0570 ............................ lf statement missing Simulation boolean
equation.
0580 ............................ If statement missing Begin.
0590 ............................ lf statement has second clause, which is
missing Begin.
0600 ............................ lf statement's second clause has bad
syntax.
061 0 ............................ For statement missing registered
assignment.
0620 ............................ For statement missing Iterator.
0630 ............................ For statement missing To.
0640 ............................ For statement's To is missing left-hand
side.
0650 ............................ For statement's To is missing right-hand
side.
0660 ............................ For statement's Iterator has bad syntax.
0670 ............................ For statement's To has bad syntax.
0680 ............................ Simulation pin has bad syntax.
0690 ............................ Simulation state has bad syntax.
0700 ............................ Simulation condition has bad syntax.
071 O............................ Simulation not missing element.
0720 ............................ Simulation not pin has bad syntax.
0730 ............................ Simulation not pin has bad syntax.
0740 ............................ Simulation not condition has bad syntax.
0750 ............................ Simulation not condition has bad syntax.
0760 ............................ Simulation list: not with state.
0770 ............................ Simulation don't care misSing element.

E-10

MonoIIthIo

W lIIIemories

ERROR

MESSAGES

0780 ............................ Simulation don't care pin has bad syntax.
0790 ............................ Simulation don't care pin has bad syntax.
0800 ............................ Simulation don't care condition has bad
syntax.
081 O............................ Simulation don't care condition has bad
syntax.
0820 ............................ Simulation don't care with illegal element.
0830 ............................ lIIegal Simulation equation.
0860 ............................ State output equation missing outf.
0870 ............................ State output equation missing State
name.
0880 ............................ State output equation missing condition.
0890 ............................ State output equation has bad syntax.
0900 ............................ State output equation has bad syntax.
091 O............................ State output equation has bad syntax.
0920 ............................ State transition equation missing State.
0930 ............................ State transition equation missing
condition.
0940 ............................ State transition equation has bad syntax.
0950 ............................ State Transition equation has bad syntax.
101 O............................ Pin equation missing left-hand side.
1020 ............................ Pin equation missing right-hand side.
1030 ............................ Pin equation has bad syntax.
1 040 ............................ Pin equation pin has bad syntax.
1050 ............................ Pin equation not has bad syntax.
1060 ............................ Pin equation Setf has bad syntax.
1070 ............................ Pin equation elk has bad syntax.
1080 ............................ Pin equation Set has bad syntax.
1090 ............................ Pin equation Reset has bad syntax.
11 OO ............................ Pin equation Trst has bad syntax.
111 O............................ Pin equation Outf has bad syntax.
1120 ............................ llIegal pin definition.
1160 ............................ State or missing left-hand side.
1170 ............................ State or missing right-hand side.
1180 ............................ State or not connected to a branch
1190 ............................ State default branch missing left-hand
side.
1200 ............................ State default branch missing right-hand
side.

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E·11

ERROR MESSAGES

1210 ............................ State default branch not connected to a
default.
1220 ............................ State next branch missing left-hand side.
1230 ............................ State next branch missing right-hand side.
1240 ............................ State and missing left-hand side.
1250 ............................ State and missing right-hand side.
1260 ............................ State don't care missing pin.
1270 ............................ State don't care has bad syntax.
1280 ............................ State don't care has bad syntax.
1290 ............................ State not missing pin.
1300 ............................ State not has bad syntax.
1310 ............................State not has bad syntax.
1320 ............................State pin has bad syntax.
1330 ............................ Illegal default for output or state value
equation.
1340 ............................ lIIegal default for state transition equation.
1350 ............................ State's state name has bad syntax.
1410 ............................ Default branch has bad syntax.
1420 ............................ Default branch has bad syntax.
1430 ............................ Default branch has bad syntax.
1440 ............................ Default branch has bad syntax.
1450 ............................ Default branch has bad syntax.
1460 ............................ Default branch has bad syntax.
1470 ............................ Default branch has bad syntax.
1480 ............................ lIIegal default branch.
1490 ............................ Default branch missing state.
1500 ............................ 0utput hold has bad syntax.
151 0............................ Def au It output has bad syntax.
1520 ............................ 0utput hold pin has bad syntax.
1530 ............................ lIIegal pin in output hold.
1540 ............................ Default output not missing pin.
1550 ............................ Default output pin has bad syntax.
1560 ............................ Default output pin has bad syntax.
1570 ............................ Default output don't care missing pin.
1580 ............................ Default output pin has bad syntax.
1590 ............................ Default output pin has bad syntax.
1600 ............................ Default output pin has bad syntax.
161 O............................ lIIegal element in default-output.
1620 ............................ lIIegal state value equation.

E·12

/IIIono/Hhlo

IFIll /IIIemorle.

ERROR

MESSAGES

1660 ............................ State value equation missing State.
1670 ............................ State value equation missing Bin or
output list.
1680 ............................ State value equation with Bin missing pin
list.
1690 ............................ State value equation has bad syntax.
1700 ............................ State value equation has bad syntax.
171 O............................ State value equation has bad syntax.
1720 ............................ State value equation is missing a pin.
1730 ............................ State value equation has bad syntax.
1740 ............................ State value equation has bad syntax.
1750 ............................ llIegal state value equation element.
1760 ............................ State value equation missing pins.
1770 ............................ Mealy-machine has bad syntax.
1780 ............................ Mealy-machine has bad syntax.
1790 ............................ Moore-machine has bad syntax.
1800 ............................ Moore-machine has bad syntax.
181 O............................ Master reset has bad syntax.
1820 ............................ Master reset has bad syntax.
1830 ............................ 0utput-enable has bad syntax.
1840 ............................ 0utput-enable has bad syntax.
1860 ............................ Equal sign defines illegal equation.
1870 ............................ Registered assignment defines illegal
equation.
1880 ............................ Equation of unknown type.
1890 ............................ Condition equation missing left-hand
side.
1900 ............................ Condition equation missing right-hand
side.
191 O............................ Condition equation has bad syntax.
1920 ............................ Condition equation has bad syntax.
1930 ............................ Equal sign missing arguements.
1940 ............................ Colon equals missing arguements.
1950 ............................ Asked to parse Null equation.
1960 ............................ Too many state tokens, power up cannot
be stored.
2010 ............................ General output error.
2020 ............................ 0utput file write error occured.
2030 ............................ Output file not open.

Monolithic

W Memories

E·13

ERROR MESSAGES

2040 ............................ 0utput file already open.
2050 ............................ Output file cannot be opened.
221 O............................ lIIegal Simulation element.
2220 ............................ lIIegal Simulation command type.
2230 ............................ ISimulation state not active.
2240 ............................ Simulate Section: Conditions aren't
allowed ... yet.
231 O............................ Txtfile cannot be opened.
2320 ............................ Nothing in txtfile.
2330 ............................ Message not in txtfile.
2340 ............................ End of txtfile reached before message.
2350 ............................ Number withough message in txtfile.
2360 ............................ Went over maximum number for txtfile.
251 O............................ Undefined value for state bit.
2520 ............................ State Value Equations must use exactly
the same state bits.
2530 ............................ Not enough columns for tree.
271 O............................ S-equation memory retrieve failed.
2720 ............................ partial memory retrieve failed.
2730 ............................ products memory retrieve failed.
2740 ............................ State value memory retrieve failed.
2750 ............................ State value additional memory retrieve
failed.
2760 ............................ Next branch memory retrieve failed.
2770 ............................ Next branch additional memory retrieve
failed.
2780 ............................ State name memory retrieve failed.
2790 ............................ State name additional memory retrieve
failed.
2800 ............................ 0utput branch memory retrieve failed.
281 O............................ Output branch additional memory retrieve
failed.
2820 ............................ State output memory retrieve failed.
2830 ............................ State output additional memory retrieve
failed.
2840 ............................ Condition memory retrieve failed.
2850 ............................ Condition additional memory retrieve
failed.
2860 ............................ Part element memory retrieve failed.

E·14

NIonoIlthic

mill Memories

ERROR

MESSAGES

2870 ............................ Part name memory retrieve failed.
2880 ............................ Sop equation memory retrieve failed.
2890 ............................ Pin memory retrieve failed.
301 O............................ Can't initialize design input file.
3020 ............................ Can't open design input file.
3030 ............................ Design input file equation read error.
3040 ............................ Can't rename design output file.
3050 ............................ Part not supported.
3060 ............................ Prose device selected, no processing
performed.
3070 ............................ Can't rename prose design file.
3080 ............................ Can't delete temporary file.
3090 ............................ IDevice: Minimize will remove XOR from
equation for 'X' part.
321 O............................ llIegal boolean equation.
3220 ............................ More signals than products count.
3230 ............................ Conditions: Circular condition
encountered.
3240 ............................ llIegal condition encountered.
3250 ............................ Equation: Illegal state.
3260 ............................ Equation: Illegal state. State is
unreached.
3270 ............................ Equation: Can't process simulate boolean
equation.
3410 ............................ Minimizer: Minimization failed.
351 O...........................• File: Read Error. Part definition file (PDF).
3520 ............................ File: Open Error. Part definition file (PDF).
361 O............................ Equations: Illegal equation in equations
section.
3620 ............................ Equations: Illegal equation suffix.
3630 ............................ Equations: Multiple equations for a node.
3640 ............................ Equations: Illegal registered equation.
401 O............................ State: Illegal equation in state section.
4020 ............................ State Transition: Last equation has a
default of next state.
4030 ............................ State: Both mealy and moore specified
(default: mealy).
4040 ............................ State: Moore machine with output
conditions.

Monolithic

W Memories

E·15

ERROR

MESSAGES

4050 ............................ State Value: Multiple equations for a state.
4060 ............................ State Transition: Multiple equations for a
state.
4070 ............................ State Transition: Multiple defaults for a
state.
4080 ............................ State Output: Multiple equations for a
state.
4090 ............................ State Output: Multiple defaults for a state.
4100 ............................ Conditions: Illegal equation in conditions
section.
4110 ............................ Conditions: Multiple equations for a
condition.
4120 ............................ State List: Illegal entry. (Entry must be a
pin.)
4130 ............................ State List: Multiple occurances of a pin.
4140 ............................ State: Unreached state(s).
4150 ............................ State: Need to automatically assign a new
state bit.
4160 ............................ State Transition: Default Branch is the
only transition.
4170 ............................ State: Unspecified state transition
equation.
4180 ............................ State: Unable to automatically assign a
new state bit.
4190 ............................ State: Device selected isn't supported for
state machines.
4200 ............................ State Transition: Undefined default next
state.
4210 ............................ State Output: Registered and
combinatorial equations are mixed.
4220 ............................ State Output: Hold specified for a
combinatorial equation.
4230 ............................ State: Moore Machine with combinatorial
outputs.
4240 ............................ State Transition: Conditions overlap.
4250 ............................ State Output: Conditions overlap.
4500 ............................ Minimizer: Memory allocation failed. Block
requested too large.

E.16

Monolithio

W Memories

ERROR

MESSAGES

4501 ............................ Minimizer: Memory allocation failed. Out of
memory.
4502 ............................ Minimizer: Memory free failed.
451 O............................ Minimizer: No solution possible (check
equations).
4511 ............................ Minimizer: Inconsistent Frequency Table.
4520 ............................ Minimizer: Cube not covered in REDUCE.
4530 ............................ Minimizer: split_select index error.
4531 ............................ Minimizer: spliCtwo_select index error.
4532 ............................ Minimizer: large_cube_index -- bestindex
-1.
4540 ............................ Minimizer: cover capacity exceeded.
45S0 ............................ Minimizer: ON and OFF sets aren't
orthogonal (check equations).

ERRORS
REPORTED BY
PROASM-PROSIM
Error Number

Error Message

101 ............................ Logically there are <integer value>
product terms which cciuld not fit into
this device.
102 .............................. Logically there are <integer value>
states which could not fit into this
device.
103 .............................. Logically there are more than <integer
value> conditions which are impossible
to fit into this device.
1 04 .............................. Logically there are more than <integer
value> states which are impossible to fit
into this device.
1OS .............................. Only one machine type is allowed in the
state section.
106 ............................ For MOORE machine, there is only one
output in each state. State <string> has
more than one output.

Monolithic

W Memories

E.17

ERROR MESSAGES

111 .............................. Number of pins in CHIP section does not
match number of pins in actual device.
112 .............................. Position of pin <pin name> should be
VCC in CHIP section.
113 .............................. Position of pin <string> should be GND
in CHIP section.
114.............................. PROASM does not support this device,
only PROSE device.
117 .............................. <string>.OUTF is specified as
combinatorial output, MUST be
REGISTERED.
118 ............................. Unrecognizable next state in state
equation <string>.
119 ............................. POWER.OUTF is not defined in this
MEALY machine. Output pattern is
<string> when you clock this device after
power up or reset.
120 .............................. Unrecognizable output in state output
equation <string>.
121 .............................. Unrecognizable condition in state
equation <string>.
122 .............................. 0nly output pin is allowed in
DEFAULT_OUTPUT statement. Pin
<string> is not.
123 ............................ Only output pin is allowed in
OUTPUT_HOLD statement. Pin
<string> is not.
124 ............................. Only HOLD_STATE, or NEXT_STATE,
or a specific state name is allowed after
DEFAULT_BRANCH statement.
125 .............................. No .CLKF/.RSTF/.SETF/.TRST are
allowed for state <string>.
126 ............................ IIlegal output equation for state <string>.
Only STATE.OUTF is allowed in the left
hand side.
127 ............................ More than 1 local default next state in
state <string>.
128 ............................ No default next state in state equation
<string>.

E·18

Nlono/Hhlc

W Nlemorles

ERROR

MESSAGES

129 ............................ Only one next state is allowed after
POWER_UP state. For MEALY model,
one output pattern is also allowed.
130 .............................. lIIegal state equation for state <string>.
131 .............................. State <string> has more than 4 next
states.
132 .............................. No .CLKF/.RSTF/.SETF/.TRST/.OUTF
are allowed after POWER_UP state, no
'I' is allowed before it either.
133 .............................. Illegal state name usage, I <string> is not
allowed.
134 .............................. State <string> has more than 4
conditions.
135 .............................. Unmatched condition in state <string>'s
output and transition equations.
136 .............................. State <string> output has more than 4
conditions.
137 .............................. 0nly Output pin is allowed in the right
hand of state.outf equation. Pin <string>
is not an output pin.
138 .............................. Conflict output specified for pin <string>
in state.outf equation.
139 ............................. More than one POWER_UP specified in
STATE section.
140 .............................. State <string> is defaulted to be the
state after power-up.
141 .............................. 0nly sum of products is allowed in the
right hand side of condition equation
<string>.
142 .............................. PROASM does not support
DeMorganizing condition. So I<string>
is not allowed.
143 .............................. No .CLKF/.RSTF/.SETF/.TRST/.OUTF
are allowed for condition <string>.
144 .............................. 0nly combinatorial condition is allowed,
':=' is not allowed in condition <string>.
145 .............................. 0nly input pin is allowed in the right
hand of condition equation. Pin <string>
is not a input pin.

Monolithic

W Memories

E·19

ERROR MESSAGES

146.............................. Not enough products available in
processing condition <string>.
161 .............................. Current device doesn't have enough
PAL product terms for this design.
162 .............................. Current device doesn't have enough
PROM locations for this design.
171 ............................. Overlapping decision in state <string>.
172 .............................. Condition <string> overlaps with its
following condition(s).
173 .............................. Fatal overlapping decision in state
<string>.
174.............................. Same condition <string> causes
branching to 2 different states.
181 .............................. There is error in accessing the
PALASM2.TRE file.
182 .............................. End of section is encountered
unexpectedly.
183 .............................. No more memory left to read in the
PALASM2.TRE file.
184.............................. A previous PALASM2.TRE file has been
opened and has not been closed.
18S .............................. PALASM2.TRE file has never been
successfully opened.
191 .............................. Prose Definition File open/close error.
192 .............................. Data accessing error in Prose Definition
File.
196 .............................. XploVJedec output file open/close error.
197 .............................. XplotlJedec write error.
198 ............................. XploVJedec output file name length is
more than <integer value>.
600 .............................. Simulator message not implemented
yet.
60S .............................. Error while initializing the error program.
610 .............................. Simulator encountered a system
allocation error while attempting to
create a dynamic data structure.
61S .............................. An error occurred while opening the
intermediate design file. The cause is
probable either incompatible simulator

E.20

ItIIonoIlthlo

Memories

ERROR MESSAGES

and frontend programs or intermediate
file does not exist.
616 .............................. An error occurred reading from
intermediate design file within the state
section.
617 .............................. An error occurred reading from
intermediate design file within the
equation section.
618 ............................. An error occurred reading from
intermediate design file within the
simulation section.
620 .............................. An error occurred within the text
handler.
621 .............................. Text message file index not found.
Probable cause is incorrect message file
for this version of the simulator.
625 .............................. Simulator could not locate PDF file for
device
626 .............................. Simulator detected an error while
reading from PDF file. Simulator
detected an unknown error when
reading from PDF file.
630 .............................. lnternal error detected within
historyltrace program. Partial History
Output.
631 ............................. Internal error detected within
history/trace program. Cannot ReInitialize History.
632 .............................. lnternal error detected within
history/trace program. Partial Trace
Output.
633 .............................. lnternal error detected within
history/trace program.History Names Not
Terminated.
634 .............................. lnternal error detected within
history/trace program. Trace Names Not
Terminated.

Monolithic WMemories

E·21

ERROR

MESSAGES

635 .............................. lnternal error detected within
history/trace program. More values
written to output than there are names.
636 .............................. Internal error detected within
history/trace program. Less values
written to output than there are names.
637 .............................. Simulator could not open history file.
638 .............................. Simulator could not open trace file.
646 ............................. Error occurred while creating history file
name.
647 ............................. Error occurred while creating trace file
name.
648 ............................. Error occurred while creating JEDEC
input file name.
649 .............................. Error occurred while creating JEDEC
output file name.
650 .............................. Simulator cannot construct file name;
name is too long.
651 .............................. Simulator encountered an unknown
device type for the PROSE device.
652 .............................. More than one clock is defined in the
PROSE PDF file. Extra clock pins will be
ignored.
653 ............................. More than one initialize/output enable
pin is defined in the PROSE PDF file.
Extra pins will be ignored.
654 .............................. Value of condition in state equation is
not boolean value.
654 ............................. Condition will be ignored.
655 .............................. Three-State control does not evaluate to
a boolean value. Control will be ignored.
656 .............................. Condition in WHILE/IF construction
does not evaluate to a boolean value.
Construction will be ignored.
657 .............................. Trace Qualifier does not evaluate to a
boolean value. Trace will be displayed.
658 .............................. Register asynchronous load does not
evaluate to a boolean value. Load will be
ignored.

E·22

Monolithic

W Memories

ERROR

MESSAGES

659 .............................. Register asynchronous reset does not
evaluate to a boolean value. Reset will
be ignored.
660 .............................. Register asynchronous set does not
evaluate to a boolean value. Set will be
ignored.
661 ............................. Register clock does not evaluate to a
boolean value. Register will be clocked
with a new value.
662 .............................. Unexpected token found when
evaluating internal PROSIM equation.
This error may indicate internal PROSIM
failure and should be reported to the
factory.
663 .............................. Simulation cycle prematurely terminated.
Circuit did not settle before simulation
cycle limit exceeded.
664 .............................. Signal value does not compare with
internal simulation value.
665 .............................. Trace output is already on. The
TRACE_OFF command will be assumed
immediately before this TRACE_ON
command.
666 .............................. Unexpected TRACE_OFF. Trace
output was not active.
667 .............................. Simulator can not SETF a state register.
You should use PRLDF to set state
value.
668 .............................. Signal can not be set through the SETF
command.
669 .............................. Signal not found or is not a boolean
Signal in SETF command.
670 .............................. There is not a state register in the
simulator to preload.
671 .............................. Signal can not be set through the
PRLDF command.
672 .............................. Signal not found or is not a boolean
signal in PRLDF command.

Monolithic

W Memories

E·23

ERROR MESSAGES

673 .............................. There is not a state register in the
simulator to check state value against.
674 ............................. Signal not found or is not a boolean
signal in CHECKF command.
675 .............................. There is not a state register in the
simulator to qualify state name against.
676 .............................. Signal not found or cannot be traced in a
TRACE_ON command.
677 ............................. The TRACE_OFF command does not
allow arguments.
678 .............................. Unexpected intermediate file data
structure encountered during the FOR
command.
679 .............................. Unexpected intermediate token
encountered in FOR command.
680 .............................. Unexpected intermediate file data
structure encountered during
construction of boolean/arithmetic
expression.
681 .............................. Unexpected intermediate token
encountered while constructing an
arithmetic expression.
682 ............................. Unexpected intermediate token
encountered while constructing a
boolean expression.
683 ............................. There is no state register defined within
the simulator to test in a boolean
equation.
684 ............................. Simulator detected an error when writing
to an history or trace file.
685 .............................. lnternal error detected within
history/trace program. Unknown Object.
686 .............................. Unexpected intermediate file data
structure encountered during
construction of terminal expression.
687 ............................. Unexpected intermediate file token
encountered while constructing a
terminal expression.

E .. 24

Monolithic

!HiD Memories

ERROR MESSAGES

688 .............................. Multiple prefixes are not allowed for
signal or state names.

689 .............................. Multiple suffixes are not allowed for
signal or state name

690 .............................. Expected signal usage is not consistent
with its earlier

690 .............................. definition
691 .............................. Simulator encountered integrity check
failure while reading from intermediate
page file.
692 .............................. Simulator does not have enough space
for state names.
693 .............................. State output element either has a suffix
or is an unexpected state value.
694 ............................. Unexpected intermediate file data
structure encountered during
construction of state output element.
69S .............................. Unexpected intermediate file data
structure encountered during
construction of next state equation.
696 .............................. Unexpected intermediate file token
encountered while constructing next
state equation.
697 .............................. Unexpected intermediate file data
structure encountered during
construction of next state or state output
equations.
698 .............................. Unexpected intermediate file data
structure encountered during
construction of left hand side of next
state or state output equations.
699 .............................. Multiple state suffixes found while
constructing state equation.
700 .............................. Unexpected intermediate file token
encountered while constructing left
hand side of a state equation.
701 .............................. Unexpected combination of token on
left hand side of state equation. The
simulator only accepts state := next state

IWonoIlthlc

W Memories

E·25

ERROR

MESSAGES

equation or\ state.OUTF = state output
equation.
702 .............................. Unexpected internal file token
encountered in state section.
703 .............................. Multiple models for state equations can
not be specified.
704 .............................. Simulator cannot implement both
initialize and enable models.
705 .............................. Too many state output default values are
specified. Extra default will be ignored.
706 .............................. Moore model only accepts default
output states. Other specifications will
be ignored.
707 .............................. Too many next state default values are
specified. Extra default will be ignored.
708 .............................. Last next state equation must have an
explicit default state specified.
Unknown next state will be assumed.
709 .............................. Unexpected internal token
encountered.
710 .............................. Unexpected intermediate file data
structure encountered during
construction of signal equation.
711 .............................. Unexpected intermediate file token
encountered while constructing signal
equation.
712 .............................. Simulator does not recognize the signal
equation type. The simulator currently
supports only the following forms: signal
= equation.
713 ............................. Signal already defined.
714 .............................. Simulator does not support registered
equations. The simulator currently
supports only the following forms signal
= equation.
715 .............................. Signal does not have a definition for this
signal. Signal cannot be set because it
is Dot at the device boundary.

E·26

Monolithic WMemorles

ERROR MESSAGES

716 .............................. Buried registers can never be
preloaded.
717 .............................. Unexpected intermediate file token
encountered within a default branch
command.
718 ............................. Simulator does not have a definition for
this signal. It will use a boolean don't
care value in its stead.
719 ............................. Unexpected intermediate file token
encountered while constructing
simulation command.
720 .............................. Prefixes (lor %) should not be used on
arguments to the OUTPUT_HOLD
command. The prefixes are being
ignored.
721 ............................. Simulator can not CLOCKF a state
register. You should use PRLDF to set
state value.
722 .............................. Signal can not be set through the
CLOCKF command.
723 .............................. Signal not found or is not a boolean
signal in CLOCKF command.
724 .............................. CLOCKF command without any
arguments. Command will not affect
simulation since there is not signal
specified to clock.
725 .............................. Simulation section not found in PROSE
device specification.
726 .............................. Buried state output can never be
preloaded.
727 ............................. TRACE_ON prefix (probably %) not
supported by simulator. Prefix will be
ignored.
728 ............................. Prose part description file (PDS file) and
part definition file (PDF file) pin counts
do not agree.
729 ............................. The Prose definition file (PDF file)
defines more than one serial diagnostic
input/output pin, serial diagnostic clock,

IIIIonoIlthlc

Memorle.

E·27

ERROR MESSAGES

serial mode control or device clock pin.
This in not supported in the present
version of the simulator.
730 .............................. The Prose definition file (PDF file) did
not define either the serial diagnostic
input/output pin, serial diagnostic clock,
serial mode control or device clock pin.
This in not supported in the present
version of the simulator.
731 .............................. The simulator only supports register
outputs on output pins of a Prose
device.
732 .............................. The simulator does not allow signals to
be defined to VCC, GND and NC pins.
733 .............................. The simulator does not allow definition
on either the serial diagnostic
input/output pin, serial diagnostic clock,
or the serial mode control.
734 .............................. The simulator detected an unknown pin
type in the Prose definition file (PDF
file) .
735 .............................. The simulator does not allow a defined
signal (an output) on an input pin.
736 .............................. The simulator does not allow a
undefined signal
(an input) on an output
,
pin.
737 .............................. The simulator has output more than 512
JEDEC vectors.
738 .............................. The simulator has detected an error
during the device simulation and is
stopping the generation of JEDEC test
vectors.
739 ............................. The simulator has detected too many
state bits for this version of the simulator.
740 .............................. The trace output was active and there
was not a TRACE_OFF command at the
end of the simulation. The simulator will
assume a TRACE_OFF.

)

E·28

IIIIonoIIthIc

Memor/e$

ERROR MESSAGES

741 ............................. Unexpected end of file encountered
while reading the JEDEC input file.
742 ............................ Too many state value bits were
encountered while reading the JEDEC
input file.
743 ............................ Unexpected delimiter between the state
value and the state name encountered
while reading the JEDEC input file.
744 ............................. The simulator could not locate a state
name defined within the JEDEC input
file with the state names defined within
the Prose device specification.
745 .............................. An illegal fuse value was encountered
while reading the
745 .............................. JEDEC input file.
746 ............................. The JEDEC input file and the Prose
definition file do not describe the same
device.
747 ............................. The simulator attempted to open the
JEDEC input file twice.
748 ............................ The simulator could not close the
JEDEC input file.
749 ............................. The simulator could not the JEDEC
output file.
750 .............................. The simulator could not close the
JEDEC output file.
751 ............................. The simulator has produced a JEDEC
test vector which is too long.
752 '" .......................... An address defined within the JEDEC
input file does not match the calculated
internal value of this address.
753 ............................. The simulator has encountered an illegal
JEDEC file format when copying the
JEDEC input file to the JEDEC output
file.

Monolithic

Memories

E·29

ERROR MESSAGES

ERRORS
REPORTED BY
ZHAL
Error Number

Error Message

124 ......................... Make sure that your design passes XPLOT
3424 ....................... Declared device pin/node count from PDS
file is <integer value>
3428 ....................... Max device pin/node count exceeded
3440 ...................... Force Route Failure: force route range is
full for device pin <integer value>
Possible solutions:
1)Try swapping pins around
2)lnterleave large and small equations
on the output pins (Adjacent pins with
large equations often fail to route)
3)Reduce equation size
redundancy if possible

by removing

4)May be possible to hand route while
keeping present device pinout
3448 ...................... Force Route Failure: equation product term
too large for pin dnteger value>
3452 ..................... Equation product term may contain a
maximum of <integer value> Signals
3456 ...................... Force Route Failure: there is no space
available for equation on device pin
<integer value>.
Remaining routing
range is insuffiCient
Possible solutions:
1)Try swapping pins around

E-30

MonoIlthloW . .morles

ERROR MESSAGES

2)lnterleave large and small equationson
the output pins (Adjacentpinswith large
equations often fail to route)
3)Reduce equation size by removing
redundancy if possible
4)May be possible to hand route while
keeping present device pinout
3460 ...................... Force route range does not exist Illegal
equation on device pin <integer value>
Design may be illegal for target device Make
sure that your design passes XPLOT
3488 ...................... Error selecting enable condition for pin
<integer value>
3492 ...................... Force Route: failed to place signal for
device pin <integer value> into array
Possible causes and solutions:
1)Maximum fan out reached on the signal.
Use new signal or hand route
2) Error in PDF: consult FAE or factory
3520 ..................... Illegal use of vee or GND keywords in
equation for device pin <integer value>
3524 ..................... Maximum number of product terms
exceeded on device pin <integer value>
3528 ..................... Maximum number of product terms allowed
in an equation is <integer value>
3532 ...................... lIlegal device pin: pin <integer value> does
not exist on target device
3536 ...................... Error in array column allocation
Error was found on signal for device pin
<integer value>

Monolithic

W Memories

E·31

ERROR MESSAGES

Possible problems and solutions:
1) High probabHity that there are too many
signals in the equation set. Modify
equation to reduce number of signals
used
2)Signal has no connect to array such as
GND or VCC.
Remove Signal from
equation set.
Note: a* la=GND, a + la=VCC
3600 ....................... Illegal condition in the PDF file for device
pin <integer value>
4000 ....................... Maximum usage exceeded, <integer
value>, of input signal
4004 ...................... Illegal ZHAL device
5000 ....................... Message file cannot be accessed
5004 ....................... No match for error code in message table
Note: The above list consists of user errors only. Other errors
you might see are likely to be internal, for which you should
contact your local FAE or the Monolithic Memories factory.

ERRORS
REPORTED BY SIM
Error Message

Error Number

o.................................. Unexpected

end of input TRE or PAL
file,fiJe invalid
1 .................................. SETFITRACE_ONI
CHECKITRACE_OFF should have
parameters
2 .................................. lIIegal parameter

E·32

IIIIonoIIth/o

Memories

ERROR MESSAGES

3.................................. lIIegal parameter after expansion
4 .................................. Cannot SETF a combinatorial output
5 ..................................This output is SETF without preload and
TRI-STATE functions active
6.................................. Can not CLOCKF this pin
7..................................The value of the clock pin is high and
CLOCKF is asserted
8 .................................. TRACE_ON command should follow
TRACE_OFF command
10 ................................ This is not a functional equation
11 ................................ Undefined equation
12 ................................ SET/RESET function asserted at the
same time PRELOAD function
13 ................................ SYSTEM OSCILLATION
14................................This pin cannot be used as an input pin
15/16 ........................... Cannot have simplelfunctional equation
for this pin
17................................ Number of vectors exceed maximum
vectors (=512)
18 ................................ No simulation commands present
19 ................................ Cannot have input pins as arguments of
CHECK statements
20 ................................ 0utput XX is SETF without tristate
function active
21 ................................ Combinatorial output cannot be
preloaded
22 ................................ Input pin cannot be preloaded. Use the
SETF command
23 ................................ CLOCK pin cannot be preloaded. Use
the CLOCKF command
24 ................................ PRLDF statement must have arguments
25 ................................ AII arguments to the PRLDF command
are invalid
26 ................................ Simulator does not support this device.
27 ................................ Cannot SETF a buried register node in
32VX10

28 ................................ Cannot CLOCKF a clock pin which is
also used as input

I6onoIIthIc

W ••morle.

E·33

ERROR MESSAGES

29 ................................ GLOBAL
Set/Reset both are high for above
output
30 ................................ The functional equation for this pin is
using a registered equation (:=) instead
of combinatorial
31 ................................ Simple equation can not be defined for
GLOBAL pin
32 ................................ Can not SETF above pin
33 ................................ Global pin can not be pre loaded
34 ................................ Set or Reset is always high
35 ................................ 0utput pin cannot be preloaded.
Preload can only be done on the buried
register nodes
36 ................................ Set/Reset are both high for above
output
37 ................................ Buried register node value missing.
32VX10 preload requires all buried
nodes to be specified
38 ................................ Missing PALASM2.TRE, cannot
simulate file. Please run your file
through PALASM2 to generate
PALASM2.TRE
39 ................................ Missing .PDF file. Please copy the .PDF
file into this directory and run again

ERRORS
REPORTED BY
JEDMAN
Error Number

Error Message

10 ................................ lnput JEDEC file cannot be opened.
20 ................................ PDF file PALPDF.PDF cannot be
opened.
30 ................................ Part name is incorrect.
40 ................................ lnput file is not a valid JEDEC file.
50 ................................ lnput file terminated prematurely.

E·34

MonolithIc

Memories

ERROR MESSAGES

60 ................................ Error file cannot be created.
70 ................................ 0utput JEDEC file cannot be created.
80 ................................ 0utput PALASM2 file cannot be
created.
90 ................................ lIIegal data in fuse field.
95 ................................ AII the JEDEC fuse data must appear in
one block.
100 .............................. No fuses specified in the input file.
105 .............................. Fuse number has been defined twice.
110 .............................. Product term SHARING is not allowed.
115 .............................. Fuse number exceeds the fuse count
permitted.
120 .............................. Data array fuse buffer size exceeded.
130 .............................. The input file is not a valid 22V10
JEDEC file.
135 .............................. Device name entered should be 22V10
for the option chosen.
145 .............................. Non-recoverable errors detected.
Program terminated.
150 .............................. lnvalid field identifier.
160 .............................. Field not valid in this context.
165 .............................. lnteger expected in the current field.
170 .............................. lIIegal specification of - <string> - field.
180 .............................. lncorrect number of fuses in the OF
field.
1O........•............•.......... lnput JEDEC file cannot be opened.
20 ................................ PDF file PALPDF.PDF cannot be
opened.
30 ................................ Part name is incorrect.
40 ................................ lnput file is not a valid JEDEC file.
50 ................................ lnput file terminated prematurely.
60 ................................ Error file cannot be created.
70 ................................ Output JEDEC file cannot be created.
80 ................................ 0utput PALASM2 file cannot be
created.
90 ................................ lIIegal data in fuse field.
95 ................................ AII the JEDEC fuse data must appear in
one block.
100 .............................. No fuses specified in the input file.

MonoIlthlcW _"",orles

E·35

t:HHUH

Mt:~~Al:it:~

105 .............................. Fuse number has been defined twice.
110 .............................. Productterm SHARING is not allowed in.
115 .............................. Fuse number exceeds the fuse count
permitted.
120 .............................. Data array fuse buffer size exceeded.
130 .............................. The input file is not a valid PAL22V10
JEDEC file.
135 .............................. Device name entered should be
PAL22V10 for the option chosen.
140 .............................. Non-recoverable errors detected.
Program terminated.
150 .............................. lnvalid field identifier.
160 .............................. Field - <string> - not valid in this context.
165 .............................. lnteger expected in the current <string> - field.
170 .............................. lIIegal specification of - <string> - field.
180 .............................. lncorrect number offuses in the OF
field.
18 ................................ Found - <integer value> -.
181 .............................. Expected - <integer value> -.
190 .............................. lncorrect number of pins in the OP field.
190 .............................. Found - <integer value> -.
191 .............................. Expected - <integer value> -.
210 .............................. lncorrect fuse checksum in the input file.
210 .............................. Found - <string> -.
211 .............................. Expected - <string>-.
220 .............................. lnvalid data - <string> - in vector field.
225 .............................. Simulation code generation not
currently supported.
230 .............................. Super-voltage will be replaced by
"PRLDF".
240 .............................. lncorrect number of logic values in
vector.
240 .............................. Found - <integer value> - entries.
241 .............................. Expected - <integer value> - entries.
250 .............................. Vector limit - <integer value>exceeded.
260 .............................. lncorrect transmission checksum.
260 .............................. Found - <string>-.

E-36

MonoIIthIo

W IfIIemorie.

ERROR

MESSAGES

261 .............................. Expected - <string> -.
270 .............................. lnvalid transmission checksum in the
input file.270 350
PROASM
Warnings issued. Check the input
JEDECfile.
500 .............................. PROASM Program successfully
completed. Check output files.
750 .............................. PROASM Input file <string>, Warnings
<integer value>
760 .............................. Errors <integer value>

NIonoInhlo

W lIIIemorie.

E·37

t:titiUti

E·38

Monolithic

MESSAGES

Memories

APPENDIX F
SUBMITTING A HAL
DESIGN TO
MONOLITHIC
MEMORIES
In order for Monolithic Memories to produce your HAL or ProPAL
devices, you need to provide Monolithic Memories Inside Sales
with a Master Device, a PAL device Design Specification in
PALASM or ABEL format, and Functional Vectors. Once these
materials have been received, a Monolithic Memories Product
Marketing Engineer will work with you to make sure that any
problems are quickly resolved, and that production begins as
soon as possible.

MASTER DEVICE
The master device is a programmed part you provide as a
reference point for Monolithic Memories testing.

PAL DEVICE
DESIGN
SPECIFICATION
You can provide the PAL device Design Specification (Logic
Equations) may be provided through the following means:

IIonoIIthIc

W Memories

'·1

;:)U CIVil I IINl.:i A

HAL

Ut:::iIGN

1 : Floppy disk or magnetic tape in formats readable by the
computers in Monolithic Memories (VAX, IBM-PC, or IBM3083).
2: A printed list of the logic equations, verified by PALASM 2
software or ABEL. The listing should be dated and signed
by its originator.
Upon receipt of your design submission Monolithic Memories will
verify the PAL device Design Specification and generate
ProPAL sample devices. The samples are sent to you for
confirmation of the pattern. (This step can be waived if you
provide logic equations on magnetic media, and stipulate that
matching the submitted master device is sufficient confirmation.)

FUNCTIONAL TEST
VECTORS
The functional vectors should consist of 20 to 40 vectors that
represent the actual operation of the device. They are used to
initiate Monolithic Memories' test vector generation (TGEN). The
functional vectors should initialize the device to a known state
within a specified number of clock cycles.
TGEN test vector generation is considered complete when fault
grading reaches a minimum of 90%. If this is not achieved, you
will be contacted for testability enhancements or a waiver.
Upon successful verification of the equations and vectors,
Monolithic Memories will send the LOGIC DESIGN/SAMPLE
APPROVAL form to you for sign off. You will at this time have the
option of reviewing the final test vectors. If you elect this option,
your approval of the TGEN-generated test pattern is confirmed
when you sign the CUSTOMER TEST PATTERN APPROVAL
form.

F·2

Monolithic

Memories

SUBMITTING A HAL DESIGN

Note: Should the test pattern simulation by PALASM 2
software differ from the simulation by TGEN, the TGEN simulation
will be used.

1IIIonoI/th/c

W Memories

F·3

HAL

F·4

IIIIonoIlthlc

U~~luN

W""eme"'es

APPENDIX G
PALASM 2
SOFTWARE SYNTAX
DIAGRAMS

Monolithic

W Memories

G·1

SYNTAX DIAGRAMS

Definition of Terms

Q·2

Monolithic

Memories

SYNTAX DIAGRAMS

Syntax Diagram

functional
description

--I~ declaration

simulation
description

Declaration

Customer
Profile

~
~ 'CHIP'

pin list

string

device
declaration

customer
--I~ profile

'TITLE'
'PATTERN'
'REVISION'
'AUTHOR'
'COMPANY'
'DATE'

1---"

J--o..lI......II~ declaration

sentence

L-r

,_-----...I

Ir---~

device)
~ pin
, . , - - . identifier ~ name
}---t'1~ _I_is_t_ .....

...

signal name

I/IIonollthic

W Memories

Q·3

SYNTAX DIAGRAMS

String Declaration

sentence

identifier

Functional Description

Equation String

signal name

Logic Equation
equation
string

signal name

lIIIonoIithlc

lIIIemories

SYNTAX DIAGRAMS

St!!t!fQuU~ul

Equation

state
name
state
name

condition

state
name

Stat! Equation

state
name

output expression

Moore

Mealy
output
expression

Condition Equation

L...-_c_~a_n!_I_:_o_n_---IK) 'L...-_es_i_~n_a~_io_n_....It---1.~

·lIIonoIithic

W Memories

0·5

SYNTAX DIAGRAMS

Simulation Description

J.:

Simulation
Commands

---t,--~cSIMULATIOjt-_.....
,.

----.t...

""\

'TRACE-ON'
'TRACE-OFF'
'CLOCKF'
'CHECK'
'SETF'
'PRLDF'
'FOR-DO'
'IF-THEN-ELSE'
'WHILE-DO'

...

I TRACE-ON
I

CHECK

...

state name

SETF

........

PRLDF

........
...

,--C_LO_C_K_F_--,I

Q·6

.....

·L-I_Sig_n_a_1n_a_m_s---I

Monolithic

W Memories

--..

signal name

SYNTAX DIAGRAMS

'FOR. .. DO'
ower
limit

upper
limit

simulation
commands

'IF ... THEN ... ELSE'

simulation
commands

comments

'WHILE. .. DO'

condition

comments

Monolithic IFl!IMemories

G·7

SYNTAX DIAGRAMS

Condition
r----tI~ identifier

state
name

equation
string

lower Limit
Upper Limit
integer

arith id

Q-8

MonoIlthio

W ••morles

APPENDIX H
SUPPLEMENTARY
SOFTWARE
The software programs described in this chapter reside on your
Supplementary disk. Some of these programs are not supported
by Monolithic Memories.

PALASM
This version of PALASM 2 software contains a new menu
interface designed for ease of use. It is especially helpful for
beginning users of PALASM 2 software. The program is on the
Supplementary diskette and you need to install it before it is
ready for use.
The program is called PALASM. For both the installation
procedure and details on how to operate the new Menu
program, turn to Chapter 2: Installing PALASM 2 Software.
Note: The old Menu program that was available in version 2.21
and all earlier versions of PALASM 2 software has been replaced
by the new enhanced Menu program. The new program is
available on PALASM 2.22 and all later versions.

PDSCNVT
PDSCNVT converts PALASM 1 software deSigns into PALASM
2 software syntax.

lI/IonoIilhic

W Memories

H·1

~U~~L~M~NIAHY

~U~IWARE

To call up the program, type

PDSCNVT
Next, supply the desired file name for conversion. The
extension .PDS has been reserved for the output file; hence
some other extension should be used for the input file: .PAL is
suggested.
PDSCNVT will successfully handle most syntax differences, but
not items 2 and 3 listed in this section. Manual correction is the
only solution. You should also correct information for the
customer profile section.
Conversion of function tables is also not fully automated.
PDSCNVT does not know any details of PAL device architecture,
such as which pins are inputs or outputs; hence it does not
produce the correct SETF and CHECKF statements. If you want
to use simulation, you must manually uncomment (remove semicolons from) those lines of the simulation section in the output
file that contain executable commands. You might begin by
removing the semicolon before the word SIMULATION. Also,
you must edit your file to remove all the output pins from the
SETF statements. It is a good idea to add CHECK statements in
your design file, wherever it is appropriate.

DIFFERENCES
BETWEEN PALASM
1 AND PALASM 2
SOFTWARE
SYNTAX
PALASM 2 software language syntax is not a true superset of the
original PALASM software syntax. In several areas, logically
correct deSigns will have to be manually edited to update them to
the new syntax. This job, while not difficult, presents several
issues:

H·2

NIonoIlthlc

W Memories

SUPPLEMENTARY SOFTWARE

PALASM 1 accepts 8 character names; PALASM 2 software
accepts 14.

Characters in the PAL device type beyond the output
designator (eg: PAL16R8A) were ignored by PALASM 1
software. They are significant and must be removed before
processing PALASM 2 software design files.

Purely numeric (1,2,5) pin identifiers were accepted in
PALASM 1, but are not legal in PALASM 2 software. A letter
(A-Z) is required as part of any pin name.

The IF (condition) was used to enable 3-state output
controls on PALASM 1 software combinational equations.
PALASM 2 software uses signal.TRST syntax for this
condition.

FUNCTION TABLE and DESCRIPTION were keywords in
PALASM 1 and marked separate sections of the design file.
PALASM 2 software uses other key words (CHIP,
SIMULATION) to parse the design file. Any of these four
terms should be avoided as user pin names.

PALASM 1 software used a fixed truth-table format for
describing inputs and outputs of chips during testing.
PALASM 2 software has a more powerful structured syntax
for describing how to do the testing. Function tables are not
currently accepted by PALASM 2 software.

PC2
Downloading of files to PAL device programmers can be
accomplished by a variety of methods on the IBM-PC. The
simplest way is to use a copy command with the output device
set to the port in use. Another method is to use a bidirectional
communications program such as PC2. PC2 replaces its
predecessors PALCOMM and PALSETUP. It offers

Monolithic WMemories

H·3

SUPPLEMENTARY SOFTWARE

the combined features of both programs along with a few
enhancements. The program is function key driven as follows:
F1 :

Send file

F2:

PALSETUP mode

F3:

VIEW switch toggle

F4:

CAPT switch toggle

F9:

New File Name

F10:

Exit

The two switches (F3 and F4) enable 2 special modes of
operation. VIEW allows you to see the JEDEC file as it is
downloaded to the programmer. CAPT saves any data sent over
the communications line to a disk file. It is especially useful to
save dumps of device fuse plots produced by the programmer
for later printing, or comparison.
When you press F2 the program begins the PALSETUP dialog
to configure the communications port. The current default data is
displayed. If no defaults are present on the disk, the program
creates a default parameter file (PC2.DAT) and allows you to alter
them. On the screen, the current parameters (COMM port, baud
rate, stop bits, etc.) are highlighted, and you can select an input
value by pressing any key on the keyboard. Press the value
(stop bits) has been selected, you are asked to confirm the
information. If confirmed, the data is saved in PC2.DAT. PC2
allows you to change file names for downloading at any time
during the session, and to download as many files as desired. If
no name is available for the downloading, a prompt is provided to
ask you for the name. Checks insure that the file exists where
indicated and is accessible.

H·4

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Memories

APPENDIX I
JEDEC STANDARD
NO. 3A
What follows is the JEDEC (Joint Electronic Devices Engineering
Council) standard format for transfer of data between data
preparation systems and programmable logic device
programmers (from JEDEC Council Ballot JCB-82-2, formulated
under the cognizance of JC-42.1 Committee on Bipolar Memory
Standardization) .

PURPOSE
The purpose of this Standard is to define a data transmission
format for transferring information between a data preparation
system and a device programmer. The information to be
transferred is divided into five categories:
1. The design specification identifier.
2. The device to be programmed.
3. Fuse links that must be blown to implement the design
specification.
4. Information to perform a structured functional test.
5. Other information.
This Standard is intended to be applicable to all programmable
logic devices.

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1·1

JEDEC STANDARD

FORMAT
DEFINITIONS
The Design
Specification
Identifier
The design specification identifier will consist of:
1. An ASCII ( STX) (02 Hex).
2.

User's name and company.

The design specification's date, part number and revision.

4. The manufacturer's part number of the programmable
device.
5. Other information.
6.

An asterisk.

An (STX) begins the transmission and is followed by ASCII
characters representing the information defined above. An *
terminates the identification information.
Example:

( STX ) J. ENGINEER LOGIC CO. 2-2-80
D.S. 018-1563A

P.N.

LOG

UAL

20L10*
/

1·2

/IIIonoillhic

Design

Memories

JEDEC STANDARD

/Spec.

Part

Number

/
Part No.
Revision

The Device to be
Programmed
An optional field is defined to specify the device being
programmed. The device can be specified by an ASCII code.
The code is preceded by a D and terminated by an asterisk (*).
Example:
( STX )

J. ENGINEER LOGIC CO. 2-2-80

D.S.
018-1563A

P.N.

LOG

UAL20LIO*D7503*

Device

Code

Fuse Information
Each device fuse link will be assigned a decimal number. These
numbers can be shown on the logic diagram of the device's data
sheet. Each numbered fuse will have two possible states. A
zero will specify a low-resistance link and a one will specify a highresistance link.

Monolithic WMemorles

1·3

JEDEC STANDARD

Fuse information can be presented in three fields. The first "F"
field is optional. This field can be used to define the default state
for links that are not defined in the second "L" field. If the "F"
field is not used, all device links must be defined in the "L" field.
The third, optional "e" field, defines a checksum.
The default state (0 or 1) for all links not defined in any "L" field
is preceded by an "F." This chosen state is followed by an
asterisk (*).
Example:

( STX ) J. ENGINEER LOGIC CO.
D.S. 018-

2-2-80

1563A
F7>

Font

P.N.

LOG

UAL20L10*D7503*
FO*
Default
State
The specific link information is preceded by an "L." The "L" is
followed immediately by a variable length decimal number that
indicates the starting fuse number of a string of data. The first 1
or 0 is preceded by a space, and the data string is terminated by
an *. Each data string can be any convenient length, and any
number of data strings can be specified. If the state of a link is
specified 2 or more times, the last state replaces preceding
entries.

1·4

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~IANLJAnU

Example:

J. ENGINEER LOGIC CO. 2-2-80

( STX

D.S.
018-1536A
P.N.

LOG

UAL

20L10
*7503*FO*LO 01010101*
L8 01010111*L1000
0101*

Link Information
For this example, fuses 16 through 999 will be assigned state 0,
and fuses 1004 through 1639 will be assigned state 0, due to
the "F" field default state. When the "F" field is used, the
receiving equipment must know the total number of fuse links.
An optional field "C" is reserved for the link information
checksum. This link information checksum is computed by
performing a 16 bit addition of 8 bit words constructed from the
specified state of each link in the device. The 8 bit words are
defined as shown in the following diagram.

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oJCUCv

;:)IANUAt1U

Word 0
Link No.

Word 1
Link No.

Word 2
Link No.

LSB

Word 137

1096

Link No.

1097
1098
1099

Last Link

Figure 1-1:
a-Bit Word Definition
The word encompassing the last link is constructed by setting
zeros for all bit locations more significant than the last link.
The 16-bit sum is expressed as 4 ASCII HEX characters. A "C"
precedes the four hex characters. The last character is followed
by an "*".
Example:

J. ENGINEER LOGIC CO. 2-2-80

( STX

D.S.
018-1563A
P.N.

1·6

LOG

Monolithic

UAL

W Memories

"'~u~v

~IANUAnU

20L10*D7503*FO*LO 01010101*
L8 01010111*L1000
0101*CF38A*
Checksum

Structured Functional
Test Information
An optional field is defined to specify one of several test
conditions for each pin of a device. A test vector is defined as N
test conditions, where N is the pin count of the device.
The ASCII variables representing test conditions are:

- Drive input low

- Drive input high

- Drive input to supervoltage #2

3-9

- Drive input to supervoltage #3-7

- Drive input low, high, low

- Drive input high, low, high

- Power pins and outputs not tested

- Test output low

- Test output high

- Test input or output for high impedance

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.II=IJ J::\,

;:),

1-\,,, U AM U

- Float input or output

The C and K driving signals are presented after other inputs are
stable. The L, H, Z tests are performed after all inputs have
stabilized, including C and K.
A test vector must be preceded by a V. The V is followed
immediately by a variable length decimal number denoting the
test vector number. This number is followed by a space, then the
test variables. The first variable in the vector is for pin 1 and the
last for pin N. The vectors will be applied to the device under test
in numeric order. If any vectors are specified 2 or more times, the
data in the last vector replaces previous data.
Example:

J. ENGINEER LOGIC CO. 2-2-80

( STX

D.S.
018-1563A
P.N.

LOG

UAL

20LI0#D7503*FO*LO 01010101*
L8 01010111*LI000
0101*CF38A*
VI
CI0III0I0I0NHLHHHHLLLLLN*V4
CIIII0II0IIN
HHHHLHHHLHLN*

1·8

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mill Memories

JEDEC STANDARD

Structured Test
Vectors
The test vector V field can be preceded by an optional P field.
The P field is used to specify the correspondence of test vector
variables to the device pin numbers. A "P" followed by a space,
then each pin number separated by a space are listed in the
desired order. The "P" field is terminated by an asterisk (*).
Example:

P 13 14 15 16 17 18 19 20 21 22 23 24
12 11 10 9 8 7 6 5 4 3 2 1*
The first variable in a test vector V will be presented to the first pin
listed in the P field. The second variable will go to the second pin
listed, etc.
If the P field is not transmitted prior to the first V field, the
standard definition is assumed, where pin 1 corresponds to the
first variable and pin N the last variable in a test vector.

Other Information
Additional optional fields may be defined using the letters G, S,
R, M, Q and T. Each field must begin with one of the above
letters and be terminated with an asterisk (*). No other
restrictions are applied. Therefore, multiple letters could be used
to specify any number of optional fields.

IIIIonoIlthlo

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1·9

JEDEC STANDARD

Ending the Format
Example:

( STX
80 D.S.

J. ENGINEER LOGIC CO. 2-2-

018-1563A
P.N.

LOG

UAL

20L10*D7503*FO*LO 01010101*
L8 01010111*L1000
0101*CF38A*
V1
C1011101010NHLHHHHLLLLLN*V4
C1111011011N
HHHHLHHHLHLN*

(ETX)

AB15

Sum-check

OTHER RULES
Carriage Returns and
Line Feeds
Carriage return characters and line feed characters can be placed
anywhere in the format to obtain maximum visibility.

1·10

Monolithic

W Memories

JEDEC STANDARD

Transportability
All receiving machines should have a "Kernel" mode to ignore all
optional fields; then the actual programming data will be
transportable. For example, as allowed in the format, optional
fields can be sent to specify additional checksums. A receiving
machine in the "kernel" mode could ignore this information yet
receive the link information required to program the device. If the
optional "F" field is used to avoid transmitting link data,
transportability could be lost. Therefore, whenever practical, data
should be transmitted for all links of the device.

Legal Characters
Only the following ASCII characters are legal. Any other
characters present in the file may result in invalid operation.
Receiving machines should be designed to ignore illegal
characters and transmitting machines should avoid sending
illegal characters.

STX

02 HEX

START OF TEXT

ETX

03 HEX

END OF TEXT

OA HEX

LINE FEED

OD HEX

CARRIAGE RETURN

All printable 20 Hex through 7E Hex inclusive characters.

Monolithic

Memories

1·11

JEDEC STANDARD

1·12

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RELEASE NOTES
PALASM 2.22
IN THIS CHAPTER
*

PALASM 2.22:

Summary of Enhancements

PALASM 2.22:

Disk and Tape Layout

PALASM 2.22:

List of Fixed Bugs

Monolithic

W Memories

RN·1

SUMMARY OF
ENHANCEMENTS
Following is a summary of enhancements in the current
release: PALASM 2.22.
Release Date: March 2, 1987

RN·2

Complete software support for PROSE

State Machine design entry

Logic Minimization

JEDEC disassembly

New easy-to-use menu interface

Supported on the VAX-UNIX operating system

Supported on DAISY workstations

Available on high density disks

MonoIUhlo

""emorle.

RELEASE

NOTES

PALASM 2.22 DISK
AND TAPE LAYOUT
The disk and tape layout outlined in the following page scan be
used to check whether you have all the necessary files to
successfully run the 2.22 version of PALASM 2 software.Below
is the disk layout. If you need the tape layout, turn to RN-8.

Disk Layout

Your package should contain the following IBM disks.

Disk #1 of 6:

PALASM2.EXE, SIM.EXE.

Disk #2 of 6:

XPLOT.EXE, JEDMAN.EXE.

Disk #3 of 6:

MINIMIZE.EXE.

Disk #4 of 6:

PROASM.EXE, PROSIM.EXE.

Disk #5 of 6:

Supplementary Software.

Disk #6 of 6:

PALASM 2 Examples

To get a listing of the files on each of your disks, insert the disk
into one of the drives in your IBM-PC/AT/XT and type

DIR
Each disk should contain the following files:

Monolithic

W Memories

RN·3

RELEASE NOTES

Disk #1 of 6:
PALASM2.EXE

SIM.EXE

(C)-COPR.TXT
P10H8.PDF
P12H6.PDF
P12L6.PDF
P14L4.PDF
P16C1.PDF
P16L2.PDF
P16L8.PDF
P16R4.PDF
P16RA8.PDF
P16RP6.PDF
P18L4.PDF
P20L 10.PDF
P20L2.PDF
P10H20G8.PDF
P20R4.PDF
P20RS10.PDF
P20X4.PDF
P22RX8.PDF
P32VX10.PDF
P6L16.PDF
P22V10.PDF
PALASM2.EXE

README
P10L8.PDF
P12L 10.PDF
P14H4.PDF
P14L8.PDF
P16H2.PDF
P16L6.PDF
P16P8.PDF
P16R6.PDF
P16RP4.PDF
P16RP8.PDF
P20C1.PDF
P20L2.PDF
P20L8.PDF
P10H20P8.PDF
P20RA10.PDF
P20X10.PDF
P20X8.PDF
P32R16.PDF
P64R32.PDF
P8L14.PDF
P16R8.PDF
SIM.EXE

50 Files

Disk #2 of 6: XPLOT.EXE
JEDMAN.EXE
(C)-COPR.TXT
P10H8.PDF
P12H6.PDF
P12L6.PDF

RN·4

README
P10L8.PDF
P12L10.PDF
P14H4.PDF

RELEASE

P14L4.PDF
P16C1.PDF
P16L2.PDF
P16L8.PDF
P16R4.PDF
P16RA8.PDF
P16RP6.PDF
P18L4.PDF
P20L10.PDF
P20L2.PDF
P10H20G8.PDF
P20R4.PDF
P20RS10.PDF
P20X4.PDF
P22RX8.PDF
P32VX10.PDF
P6L16.PDF
P22V10.PDF
XPLOT.EXE
JEDMAN.MSG
JEDMAN.DOC

NOTES

P14L8.PDF
P16H2.PDF
P16L6.PDF
P16P8.PDF
P16R6.PDF
P16RP4.PDF
P16RP8.PDF
P20C1.PDF
P20L2.PDF
P20L8.PDF
P10H20P8.PDF
P20RA10.PDF
P20X10.PDF
P20X8.PDF
P32R16.PDF
P64R32.PDF
P8L14.PDF
P16R8.PDF
PALPDF.PDF
JEDMAN.EXE

53 Files

lil:1
..

/WonoI11hIo

lU1I"mories

"N-'

RELEASE

NOTES

Disk #3 of 6:
PROASM.EXE
PROSIM.EXE
(C)-COPR.TXT
PROASM.EXE
PMS14R21.PDF

README
PROSIM.EXE
PROSE.MSG

6 Files

Disk #4 of 6:
MINIMIZE.EXE
(C)-COPR.TXT
PALPDF.PDF
MINIMIZE.MSG

README
MINIMIZE.EXE

5 Files

RN·6

IIIIonoIlthlc

miD Memories

RELEASE

NOTES

Disk #5 of 6:
SUPPLEMENTARY
SOFTWARE
README.1ST
PALASM.COM
VTRACE.COM
PRINTER.SET
TRACE.DOC
PC2.EXE
BINHEX.COM
TIMING.COM
PINOUT. DOC
SCRSIM.COM
DECODE.DOC
P2_2.SCR
P2_4.SCR
DUMMY.PDS
AUTO FLOP .BAT
MENU.SYS
31 Files

PDSCNVT.EXE
P2_1.SCR
SETUP.BAT
FXASCII.EXE
TRACE.BAT
PC2.DAT
TIMING.DOC
RIPPLE.SIG
PINOUT.COM
CONFIG.SYS
DECODE.COM
P2_3.SCR
DPATH.COM
AUTOEXEC.BAT
FLOPPY2.BAT
PAL2INST.COM

Disk #6 of 6:
PALASM 2 Examples
Refer to Appendix D for the filenames of the PAL.ASM 2 software
examples on this disk.

Monolithic

miD Memories

RN·7

RELEASE NOTES

Tape Layout
The PALASM 2 software is available on magnetic tape media for
the following computers and operating systems:
*

VAX-VMS

VAX-UNIX

For a complete listing of the files on the VAX-UNIX tape, turn to
RN-20.
Below are the three kinds of VAX-VMS tapes available:
*

Source

Executable

ASCII

The lists of files on each of the three tapes are given in the
following pages:
VAX·VMS Source Files

Directory MSAO: [ ]
INSTALL.COM
PAL2HLP.FAC
PAL2.COM
LNKFEP.COM
LNKPRA.COM
LNKSIM.COM
LNKZHL.COM
CSOPENINC.ENV
CTXTIO.ENV

lWonoIithlo

README.DOC
PAL2ASS.COM
LNKCVT.COM
LNKJED.COM
LNKPRS.COM
LNKXPT.COM
CONVINC.ENV
CTRE.ENV
EXTINC.ENV

Memories

RELEASE

FNXINC.ENV
JEDGLOBS.ENV
PAL2INC.ENV
PSFUSINC.ENV
PSPDFINC.ENV
PXSIMINC.ENV
XPLOTINC.ENV
ANDAR.OBJ
CSOPEN.OBJ
CTRE.OBJ
CTXTIO.OBJ
EXTINC.OBJ
FNXINC.OBJ
JEDCONV.OBJ
JEDFNX.OBJ
JEDGLOBS.OBJ
JEDMAN.OBJ
JEDWRITE.OBJ
PALASM2.0BJ
PARSE2.0BJ
PARSE4.0BJ
PDFONLY.OBJ
PSASM.OBJ
PSBUILD.OBJ
PSENABLE.OBJ
PSFUSINC.OBJ
PSINIT.OBJ
PSMAIN.oBJ
PSPDF.OBJ
PSSUMARY.OBJ
PSXPLOT.OBJ
PXANAL.OBJ
PXCONSTR.OBJ
PXDEBUG.OBJ
PXEXEC.OBJ
PXMAIN.oBJ
PXOUTPUT.OBJ
PXSIM.OBJ
PXSIMULA.oBJ

Monolithic

NOTES

JEDFNX.ENV
JEDINC.ENV
PDFONLY.ENV
PSINC.ENV
PSXPTINC. ENV
SIMINC.ENV
Z24.ENV
CONVINC.OBJ
CSOPENINC.OBJ
CTRESUB.OBJ
CTXTSUB.OBJ
EXTPDF.OBJ
INIT.OBJ
JEDDISASM.OBJ
JEDFUNC.OBJ
JEDINC.OBJ
JEDPARSE.OBJ
PAL2INC.OBJ
PARSE1.0BJ
PARSE3.0BJ
PARSE5.0BJ
PDSCNVT.OBJ
PSASSIGN.OBJ
PSCHECK.OBJ
PSFUSE.OBJ
PSINC.OBJ
PSJEDEC.OBJ
PSOUTPUT.OBJ
PSPDFINC.OBJ
PSWGT.OBJ
PSXPTINC.OBJ
PXARCH.OBJ
PXCYCLE.OBJ
PXERROR.OBJ
PXINPUT.OBJ
PXMEMORY.OBJ
PXPDF.OBJ
PXSIMINC.OBJ
PXSRTSTP.OBJ

W Memories

1;1:1

RN·9

RELEASE

PXSUPORT.OBJ
PXTRE.OBJ
PXVECTOR.OBJ
SCAN.OBJ
SCMD.OBJ
SEXT.OBJ
SFNODE.OBJ
SHIST1.0BJ
SIM1.0BJ
SINIT.OBJ
SMISC.OBJ
SPRLD.OBJ
STR.OBJ
SVX.oBJ
XDB.OBJ
XFNODE.oBJ
XM2.0BJ
XM4.0BJ
XPLOT.OBJ
Z24.0BJ
ZCOMPRESS.OBJ
ZERROR.OBJ
ZGLBINIT.OBJ
ZINPUTLOG.oBJ
2MBC.OBJ
ZPDFPROC.oBJ
ZREADPRO.OBJ
ZWRITEPRO.OBJ
P10H20P8.PDF
P10L8.PDF
P12L10.PDF
P14H4.PDF
P14L8.PDF
P16H2.PDF
P16L6.PDF
P16P8.PDF
P16R6.PDF
P16RA8.PDF
P16RP6.PDF

RN.10

Monolithic

NOTES

PXSYNTH.OBJ
PXTXTIO.oBJ
SANDAR.OBJ
SCHD.OBJ
SDB.OBJ
SFEQ.OBJ
SFUNC.OBJ
SIM.OBJ
SIMINC.OBJ
SINT.OBJ
SPRIM.OBJ
SRX.OBJ
STRING.OBJ
TSTDUMP.OBJ
XFEQ.OBJ
XM1.0BJ
XM3.0BJ
XM5.0BJ
XPLOTINC.OBJ
Z24MAIN.OBJ
ZDAA.OBJ
ZFORCE.OBJ
ZHAL.OBJ
ZIOPRO.OBJ
ZOUTPUTLOG.OBJ
ZPROPHYSICAL.OBJ
ZTRAVERSE.OBJ
P10H20G8.PDF
P10H8.PDF
P12H6.PDF
P12L6.PDF
P14L4.PDF
P16C1.PDF
P16L2.PDF
P16L8.PDF
P16R4.PDF
P16R8.PDF
P16RP4.PDF
P16RP8.PDF

W Memories

RELEASE

P18L4.PDF
P20C1.PDF
P20L2.PDF
P20R4.PDF
P20R8.PDF
P20RS10.PDF
P20RS8.PDF
P20X10.PDF
P20X8.PDF
P22V10.PDF
P32VX10.PDF
P6L16.PDF
PALPDF.PDF
Z20SRC.PDF
Z240BJ.PDF
Z24TAB.PDF
ZHAL24.PDF
PROSE.MSG
PAL2EX.L1S
10BITREG.PDS
20RA10.PDS
416DEC.PDS
8COUNT.PDS
9BITREG.PDS
ARBITER.PDS
CONTROL.PDS
DCOUNT.PDS
LATCH.PDS
MEMIO.PDS
OCTCOMP.PDS
P7004.PDS
TRAFFIC.PDS
VXPASCAL.COM
BLDFEP.COM
BLDPRA.COM
BLDSIM.COM
BLDXPT.COM
CONVINC.INC
CTRE.lNC

Monolithic

NOTES

P18P8.PDF
P20L10.PDF
P20L8.PDF
P20R6.PDF
P20RA10.PDF
P20RS4.PDF
P20S10.PDF
P20X4.PDF
P22RX8.PDF
P32R16.PDF
P64R32.PDF
P8L14.PDF
PMS14R21.PDF
Z20TAB.PDF2
Z24SRC.PDF
ZHAL20.PDF
JEDMAN.MSG
ZHAL24.MSG
PAL2EX.COM
10COUNT.PDS
3T08DMUX.PDS
4CNT.PDS
9BITCNT.PDS
ADREG16.PDS
BARREL.PDS
CRT.PDS
FLiPFLOP.PDS
LlNK.PDS
MEMORY.PDS
P7000.PDS
PORT.PDS
UPCOUNT.PDS
BLDCVT.COM
BLDJED.COM
BLDPRS.COM
BLDSUB.COM
BLDZHL.COM
CSOPENINC.INC
CTXTIO.INC

W MemorIes

1;1:'

Ht:Lt:ASE

EXTINC.lNC
JEDFNX.lNC
JEDINC.lNC
PDFONLV.lNC
PSGLOBAL.lNC
PSPDFINC.INC
PXGLOBAL.lNC
SIMINC.lNC
Z24.1NC
ANDARVMS
CTRESUB.VMS
EXTPDFVMS
JEDCONV.VMS
JEDFUNCVMS
JEDPARSEVMS
PALASM2.VMS
PARSE2.VMS
PARSE4VMS
PDSCNVT.VMS
PSASSIGN.vMS
PSCHECK.VMS
PSFUSEVMS
PSJEDECVMS
PSOUTPUT.VMS
PSSUMARVVMS
PSXPLOTVMS
PXARCH.VMS
PXCVCLE.VMS
PXERRORVMS
PXINPUT.VMS
PXMEMORVVMS
PXPDF.VMS
PXSIMULA.VMS
PXSUPORT.VMS
PXTRE.VMS
PXVECTORVMS
SCANVMS
SCMDVMS
SEXTVMS

RN·12

Monolithio

NOTES

FNXINC.lNC
JEDGLOBS.INC
PAL2INC.INC
PSFUSINC.INC
PSINC.INC
PSXPTINC.INC
PXSIMINC.INC
XPLOTINC.lNC
Z24GLOBAL.lNC
CSOPEN.VMS
CTXTSUB.VMS
INIT.VMS
JEDDISASM.VMS
JEDMAN.VMS
JEDWRITE.VMS
PARSE1.VMS
PARSE3.VMS
PARSES.VMS
PSASM.VMS
PSBUILD.VMS
PSENABLE.VMS
PSINIT.VMS
PSMAINVMS
PSPDF.VMS
PSWGTVMS
PXANAL.VMS
PXCONSTRVMS
PXDEBUG.VMS
PXEXEC.VMS
PXMAIN.VMS
PXOUTPUT.VMS
PXSIM.VMS
PXSRTSTP.VMS
PXSVNTH.VMS
PXTXTIO.VMS
SANDAR.VMS
SCHD.VMS
SDB.VMS
SFEQ.VMS

W Memories

RELEASE

NOTES

SFNODE.VMS
SHIST1.vMS
SIM1.VMS
SINT.VMS
SPRIM.VMS
SRX.VMS
STRING.vMS
TSTDUMP.VMS
XFEQ.VMS
XM1.VMS
XM3.vMS
XM5.VMS
Z24.VMS
ZCOMPRESS.VMS
ZERROR.VMS
ZGLBINIT.VMS
ZINPUTLOG.VMS
ZOUTPUTLOG.VMS
ZPROPHYSICAL. VMS

SFUNC.VMS
SIM.VMS
SINIT.VMS
SMISC.VMS
SPRLD.vMS
STR.VMS
SVX.VMS
XDB.VMS
XFNODE.VMS
XM2.VMS
XM4.vMS
XPLOT.VMS
Z24MAIN.VMS
ZDAA.VMS
ZFORCE.VMS
ZHAL.VMS
2MBC.VMS
ZPDFPROC.vMS
ZTRAVERSE. VMS

Total of 368 files, 3524 blocks.

VAX-VMS Executable
Files

Directory MSAO:[]
INSTALL.COM
PAL2HLP.FAC
PAL2.COM
LNKFEP.COM
LNKPRA.COM
LNKSIM.COM
LNKZHL.COM
CSOPENINC.ENV
CTXTIO.ENV

Monolithic

README.DOC
PAL2ASS.COM
LNKCVT.COM
LNKJED.COM
LNKPRS.COM
LNKXPT.COM
CONVINC.ENV
CTRE.ENV
EXTINC.ENV

W Memories

RN-13

RELEASE

NOTES

FNXINC.ENV
JEDGLOBS.ENV
PAL2INC.ENV
PSFUSINC.ENV
PSPDFINC.ENV
PXSIMINC.ENV
XPLOTINC.ENV
ANDAR.OBJ
CSOPEN.OBJ
CTRE.OBJ
CTXTIO.oBJ
EXTINC.OBJ
FNXINC.OBJ
JEDCONV.OBJ
JEDFNX.OBJ
JEDGLOBS.OBJ
JEDMAN.OBJ
JEDWRITE.OBJ
PALASM2.0BJ
PARSE2.0BJ
PARSE4.0BJ
PDFONLY.OBJ
PSASM.OBJ
PSBUILD.OBJ
PSENABLE.OBJ
PSFUSINC.OBJ
PSINIT.OBJ
PSMAIN.OBJ
PSPDF.OBJ
PSSUMARY.OBJ
PSXPLOT.OBJ
PXANAL.OBJ
PXCONSTR.OBJ
PXDEBUG.OBJ
PXEXEC.OBJ
PXMAIN.OBJ
PXOUTPUT.OBJ
PXSIM.OBJ
PXSIMULA.OBJ

RN·14

Monolithic

JEDFNX.ENV
JEDINC.ENV
PDFONLY.ENV
PSINC.ENV
PSXPTINC.ENV
SIMINC.ENV
Z24.ENV
CONVINC.OBJ
CSOPENINC.OBJ
CTRESUB.OBJ
CTXTSUB.OBJ
EXTPDF.OBJ
INIT.OBJ
JEDDISASM .OBJ
JEDFUNC.OBJ
JEDINC.OBJ
JEDPARSE.OBJ
PAL2INC.OBJ
PARSE1.0BJ
PARSE3.0BJ
PARSE5.0BJ
PDSCNVT.OBJ
PSASSIGN.OBJ
PSCHECK.OBJ
PSFUSE.OBJ
PSINC.OBJ
PSJEDEC.OBJ
PSOUTPUT.OBJ
PSPDFINC.OBJ
PSWGT.OBJ
PSXPTINC.OBJ
PXARCH.OBJ
PXCYCLE.OBJ
PXERROR.OBJ
PXINPUT.OBJ
PXMEMORY.OBJ
PXPDF.OBJ
PXSIMINC.OBJ
PXSRTSTP.OBJ

Memories

RELEASE NOTES

PXSYNTH.OBJ
PXTXTIO.OBJ
SANDAROBJ
SCHD.OBJ
SDB.OBJ
SFEO.OBJ
SFUNC.OBJ
SIM.OBJ
SIMINC.OBJ
SINT.OBJ
SPRIM.OBJ
SRX.OBJ
STRING.OBJ
TSTDUMP.OBJ
XFEO.OBJ
XM1.0BJ
XM3.0BJ
XM5.0BJ
XPLOTINC.OBJ
Z24MAIN.OBJ
ZDAA.OBJ
ZFORCE.OBJ
ZHAL.OBJ
ZIOPRO.OBJ
ZOUTPUTLOG.OBJ
ZPROPHYSICAL.OBJ
ZTRAVERSE.OBJ
P10H20G8.PDF
P10H8.PDF
P12H6.PDF
P12L6.PDF
P14L4.PDF
P16C1.PDF
P16L2.PDF
P16L8.PDF
P16R4.PDF
P16R8.PDF
P16RP4.PDF
P16RP8.PDF

PXSUPORT.OBJ
PXTRE.OBJ
PXVECTOROBJ
SCAN.OBJ
SCMD.OBJ
SEXT.OBJ
SFNODE.OBJ
SHIST1.0BJ
SIM1.0BJ
SINIT.OBJ
SMISC.OBJ
SPRLD.OBJ
STROBJ
SVX.OBJ
XDB.OBJ
XFNODE.OBJ
XM2.0BJ
XM4.0BJ
XPLOT.OBJ
Z24.0BJ
ZCOMPRESS.OBJ
ZERROROBJ
ZGLBINIT.OBJ
ZINPUTLOG.OBJ
2MBC.OBJ
ZPDFPROC.OBJ
ZREADPRO.OBJ
ZWRITEPRO.OBJ
P10H20P8.PDF
P10L8.PDF
P12L10.PDF
P14H4.PDF
P14L8.PDF
P16H2.PDF
P16L6.PDF
P16P8.PDF
P16R6.PDF
P16RA8.PDF
P16RP6.PDF

NIonoIllhlc

lIIIemorles

RN·iS

RELEASE

NOTES

P18L4.PDF
P20C1.PDF
P20l2.PDF
P20R4.PDF
P20R8.PDF
P20RS10.PDF
P20RS8.PDF
P20X10.PDF
P20X8.PDF
P22V10.PDF
P32VX10.PDF
P6L16.PDF
PALPDF.PDF
Z20SRC.PDF
Z240BJ.PDF
Z24TAB.PDF
ZHAL24.PDF
PROSE.MSG
PAL2EX.LlS
10BITREG.PDS
20RA10.PDS
416DEC.PDS
8COUNT.PDS
9BITREG.PDS
ARBITER.PDS
CONTROL.PDS
DCOUNT.PDS
LATCH.PDS
MEMIO.PDS
OCTCOMP.PDS
P7004.PDS
TRAFFIC.PDS

P18P8.PDF
P20L 1 O.PDF
P20L8.PDF
P20R6.PDF
P20RA10.PDF
P20RS4.PDF
P20S10.PDF
P20X4.PDF
P22RX8.PDF
P32R16.PDF
P64R32.PDF
P8L 14.PDF
PMS14R21.PDF
Z20TAB.PDF
Z24SRC.PDF
ZHAL20.PDF
JEDMAN.MSG
ZHAL24.MSG
PAL2EX.COM
10COUNT.PDS
3T08DMUX.PDS
4CNT.PDS
9BITCNT.PDS
ADREG16.PDS
BARREL.PDS
CRT.PDS
FLiPFLOP.PDS
LlNK.PDS
MEMORY.PDS
P7000.PDS
PORT.PDS
UPCOUNT.PDS

Total of 238 files, 1334 blocks.

RN·16

Monolithic

W Memories

RELEASE NOTES

ASCII Flies
FILE.LST
PAL2.COM
PAL2EX.COM
PAL2EX.LlS
10COUNT.PDS
3T08DMUX.PDS
4CNT.PDS
9BITCNT.PDS
ADREG16.PDS
BARREL.PDS
CRT.PDS
FLiPFLOP.PDS
LlNK.PDS
MEMORY.PDS
P7000.PDS
PORT.PDS
UPCOUNT.PDS
BLDFEP.COM
BLDPRA.COM
BLDSIM.COM
BLDXPT.COM
LNKCVT.COM
LNKJED.COM
LNKPRS.COM
LNKXPT.COM
VXPASCAL.COM
P1 OH20P8. PDF
P10L8.PDF
P12L10.PDF
P14H4.PDF
P14L8.PDF
P16H2.PDF
P16L6.PDF
P16P8.PDF
P16R6.PDF

Monolithic

README.ASC
PAL2ASS.COM
PAL2HLP.FAC
1OBITREG. PDS
20RA10.PDS
416DEC.PDS
8COUNT.PDS
9BITREG.PDS
ARBITER.PDS
CONTROL.PDS
DCOUNT.PDS
LATCH.PDS
MEMIO.PDS
OCTCOMP.PDS
P7004.PDS
TRAFFIC.PDS
BLDCVT.COM
BLDJED.COM
BLDPRS.COM
BLDSUB.COM
BLDZHL.COM
LNKFEP.COM
LNKPRA.COM
LNKSIM.COM
LNKZHL.COM
P10H20G8.PDF
P10H8.PDF
P12H6.PDF
P12L6.PDF
P14L4.PDF
P16C1.PDF
P16L2.PDF
P16L8.PDF
P16R4.PDF
P16R8.PDF

W Memories

Ii]: I

RN·17

RELEASE NOTES

P16RA8.PDF
P16RP6.PDF
P18L4.PDF
P20C1.PDF
P20L2.PDF
P20R4.PDF
P20R8.PDF
P20RS10.PDF
P20RS8.PDF
P20X10.PDF
P20X8.PDF
P22V10.PDF
P32VX10.PDF
P6L16.PDF
PALPDF.PDF
JEDMAN.MSG
ZHAL24.MSG
CSOPENINC.lNC
CTXlIO.lNC
FNXINC.INC
JEDGLOBS.INC
PAL2INC.INC
PSFUSINC.INC
PSINC.lNC
PSXPTINC.INC
PXSIMINC.lNC
XPLOTINC.INC
Z24GLOBALINC
PALASM2.SRC
PARSE2.SRC
PARSE4.SRC
PDSCNVT.SRC
STRING.SRC
XDB.SRC
XFNODE.SRC
XM2.SRC
XM4.SRC
XPLOT.SRC
SCHD.SRC

RN-i8

P16RP4.PDF
P16RP8.PDF
P18P8.PDF
P20L 10.PDF
P20L8.PDF
P20R6.PDF
P20RA 1O.PDF
P20RS4.PDF
P20S10.PDF
P20X4.PDF
P22RX8.PDF
P32R16.PDF
P64R32.PDF
P8L14.PDF
PMS14R21.PDF
PROSE.MSG
CONVINC.INC
CTRE.lNC
EXlINC.INC
JEDFNX.INC
JEDINC.lNC
PDFONLV.INC
PSGLOBALINC
PSPDFINC.INC
PXGLOBALINC
SIMINC.lNC
Z24.INC
INIT.SRC
PARSE1.SRC
PARSE3.SRC
PARSES.SRC
SCAN.SRC
ANDAR.SRC
XFEQ.SRC
XM1.SRC
XM3.SRC
XMS.SRC
SANDAR.SRC
SCMD.SRC

IIIIonoIIlhlc W.emorles

RELEASE NOTES

SDB.SRC
SFEQ.SRC
SFUNC.SRC
SIM.SRC
SIMSHELL.SRC
SINT.SRC
SPRIM.SRC
SRX.SRC
SVX.SRC
CTRESUB.SRC
UNXLlBNAM.SRC
JEDCONV.SRC
JEDFUNC.SRC
JEDPARSE.SRC

Mono/IIh/c

SEXT.SRC
SFNODE.SRC
SHIST1.SRC
SIM1.SRC
SINIT.SRC
SMISC.SRC
SPRLD.SRC
STR.SRC
CSOPEN.SRC
CTXTSUB.SRC
EXTPDF.SRC
JEDDISASM.SRC
JEDMAN.SRC
JEDWRITE.SRC

W Memories

RN·19

RELEASE

NOTES

VAX-UNIX
The complete listing of files on the VAX-UNIX tape is given
below:

RN·20

README.DOC
PAL2L1S.DOC
PAL2.COM
MAKEFILE

INSTALL. COM
PAL2EX.COM
PAL2HLP.FAC

JEDMAN.MSG
ZHAL24.MSG

PROSE.MSG

P10H20G8.PDF
P10H8.PDF
P12H6.PDF
P12L6.PDF
P14L4.PDF
P16C1.PDF
P16L2.PDF
P16L8.PDF
P16R4.PDF
P16R8.PDF
P16RP4.PDF
P16RP8.PDF
P20C1. PDF
P20L2.PDF
P20R4.PDF
P20R8.PDF
P20RS10.PDF
P20RS8.PDF
P20X10.PDF
P20X8.PDF
P22V10.PDF
P32VX10.PDF
P6L16.PDF
PALPDF.PDF
ZHAL20.PDF

P10H20P8.PDF
P10L8.PDF
P12L10.PDF
P14H4.PDF
P14L8.PDF
P16H2.PDF
P16L6.PDF
P16P8.PDF
P16R6.PDF
P16RA8.PDF
P16RP6.PDF
P18L4.PDF
P20L 10.PDF
P20L8.PDF
P20R6.PDF
P20RA 1O.PDF
P20RS4.PDF
P20S10.PDF
P20X4.PDF
P22RX8.PDF
P32R16.PDF
P64R32.PDF
P8L14.PDF
PMS14R21.PDF
ZHAL24.PDF

IIIIonoIlthlc

Memories

RELEASE NOTES

10BITREQ.PDS
20RA10.PDS
416DEC.PDS
8COUNT.PDS
9BITCNT.PDS
ADREQ16.PDS
BARREL.PDS
CRT.PDS
FLIPFLOP.PDS
L1NK.PDS
MEMORY.PDS
P7000.PDS
PORT.PDS
UPCOUNT.PDS
Z24MAIN.O
ZDAA.O
ZFORCE.O
2MBC.O
ZPROPHYSICAL.O
EXTPDF.O
JEDDISASM.O
JEDMAN.O
JEDWRITE.O
PSASM.O
PSBUILD.O
PSDUMP.O
PSFUSE.O
PSJEDEC.O
PSOUTPUT.O
PSSUMARY.O
PSXPLOT.O
PXANAL.O
PXCONSTR.O
PXERROR.O
PXINPUT.O
PXMEMORY.O
PXPDF.O
PXSIMULA.O
PXSUPORT.O

10COUNT.PDS
3T08DMUX.PDS
4CNT.PDS
8LATCH.PDS
9BITREQ.PDS
ARBITER.PDS
CONTROL.PDS
DCOUNT.PDS
LATCH.PDS
MEMIO.PDS
OCTCOMP.PDS
P7004.PDS
TRAFFIC.PDS
ZHAL.O
ZCOMPRESS.O
ZERROR.O
ZGLBINIT.O
ZPDFPROC.O
ZTRAVERSE.O
JEDCONV.O
JEDFUNC.O
JEDPARSE.O
PSASSIGN.O
PSCHECK.O
PSENABLE.O
PSINIT.O
PSMAIN.O
PSPDF.O
PSWGT.O
PXARCH.O
PXCYCLE.O
PXEXEC.O
PXMAIN.O
PXOUTPUT.O
PXSIM.O
PXSRTSTP.O
PXSYNTH.O

lIIIonoI/lh/c W.emorles

RN·21

RELEASE

PXTRE.O
PXVECTOR.O
CSOPEN.O
CTXTSUB.O
PALASM2.0
STRING.O
PARSE1.0
PARSE3.0
PARSES.O
SIM.O
SDB.O
SFEO.O
SCMD.O
SIM1.0
SINT.O
SHIST1.0
SCHD.O
SANDAR.O
SRX.O
XPLOT.O
XDB.O
XFEO.O
XM2.0
XM4.0

RN·22

Monolithic

NOTES

PXTXTIO.O
CTRESUB.O
UNXLlBNAM.O
INIT.O
SCAN.O
PARSE2.0
PARSE4.0
SINIT.O
SFNODE.O
SMISC.O
STR.O
SINT.O
SEXT.O
SPRIM.O
SFUNC.O
SPRLD.O
SVX.O
ANDAR.O
XFNODE.O
XM1.0
XM3.0
XMS.O

W Memories

RELEASE

NUTI:.~

FIXED BUGS
Since the last release, several bugs have been fixed. We
appreciate your effort in reporting problems and recommending
enhancements. For your convenience, we have included a self
addressed Bug/Enhancement Report in the manual. If you need
more forms, call our customer support hotline.
PALASM 2.22 fixed bugs are listed below. If you call in with
questions about any of these bugs, please refer to the Bug
Report number given above each bug description.

Fixed Bugs:
PALASM
Bug Report #: 805
System: IBM-PC
Version: 2.19
Reported by: Leonard Cardoza
Date received: 4/14/86
Description: If XPLOT is run after running a PROSE design
through PALASM2, a hard crash results. However, if a nonPROSE device is run through PALASM2, and PROASMPROSIM are run next, a hard crash does not occur.
Bug Report #: 807
System: IBM-PC
Version: 2.19
Reported by: Leonard Cardoza
Date received: 4/16/86
Description: If a pin name contains a _ character, PALASM2 goes
into an endless loop.

Monolithic WMemorles

RN·23

Ht:Lt:A::It:

NU I t:S

Bug Report #: 911
System: VAX-VMS
Version: 2.21
Reported by: Leonard Cardoza
Date received: 8/12/86
Description: On a PAL22V10 test, the XPLOT fusemap
contained 2 rows of fuses printed together at the bottom of the
output file, and none at the top. These correspond to the Set
and Reset lines and should be located at the top and bottom.
Bug Report #: 912
System: VAX-VMS
Version: 2.21
Reported by: Leonard Cardoza
Date received: 8/12/86
Description: On a PAL22V10 test, columns of the XPLOT fuse
array shifted by one position from where they should be. This
causes the print-out to start from the second column instead of
the first.
Bug Report #: 919
System: VAX-VMS
Version: 2.21
Reported by: Marilyn Gleason
Date received: 8/20/86
Description: Changes made to PAL22RX8 and PAL22V10 parts
cause the line numbers on the .JED and .JDC files on the
PAL32VX10 device to differ from the released version's saved
output.
Bug Report #: 928
System: IBM-PC
Version: 2.21
Reported by: Leonard Cardoza
Date received: 8/20/86
Description: If no Declaration section is included in the .PDS file,
the PALASM2 program goes into an endless loop.

RN·24

Monolithic

Memories

RELEASE

NOTES

Bug Report #: 597
System: VAX-VMS
Version: 2.15
Reported by: Marilyn Gleason
Date received: 10/2/85
Description: On a PAL20C1 test, when the chip name is longer
than fourteen characters, the PASCAL error message Array
Index Value Is Out Of Range is displayed.
Bug Report #: 714
System: VAX-VMS
Version: 2.18
Reported by: Jo-Ning Ta
Date received: 1/28/86
Description: On Prose devices, the PALASM front end does not
accept a design file where the entire Equations section is missing
or blank.
Bug Report #: 833
System: IBM-PC
Version: 2.20
Reported by: D. McCarthy
Date received: 5/15/86
Description: If a filename contains 12 characters, DOS truncates
the name. The PALASM2 program, however, does accept 12character filenames, but XPLOT does not.
Bug Report #: 863
System: IBM-PC, VAX-VMS
Version: 2.20
Reported by: Robert Steggles
Date received: 6/19/86
Description: Using the keyword EQUATIONS for state transition
conditions is confusing. Instead, create a new sub-section in the
state block called STATE_CONDITIONS.

Monolithic

W Memories

1;1: I

RN·25

Ht:Lt:A~t:

NOTES

Bug Report #: 873
System: IBM-PC
Version: 2.20
Reported by: J. Huston
Date received: 8/19/86
Description: If the software being used does not contain the
correct PDF file, XPLOT and SIM display the error Unexpected
End of . TRE or .PAL file. It would be clearer if the message said
Missing File: <filename>.
Bug Report #: 883
System: IBM-PC
Version: 2.20
Reported by: Robert Steggles
Date received: 7/2/86
Description: Although the PALASM2 program accepts an input
file from a sub directory ( for example

C:/EX2/LINK.PDS)
XPLOT and SIM crash and display a Range or Nil Check error
message.
Bug Report #: 885
System: IBM-PC
Version: 2.20
Reported by: Leonard Cardoza
Date received: 7/7/86
Description: On PAL22RX8 and PAL32VX10 devices, errors
such as PIN.SETF, PIN.RSTF, PIN.CLKF=P-TERM, and
GLOBAL.CLKF, GLOBAL.TRST, GLOBAL=P-TERM are not
detected by XPLOT.
Bug Report #: 913
System: IBM-PC
Version: 2.21
Reported by: Chris Jay
Date received: 8/13/86
Description: On the PAL32VX10 device, the error message
Setting. TRST = VCC in a 32VX10 means that... is both incorrect
and invalid. The message should say Setting. TRST = GND...

RN·26

Monolithic

W Memories

RELEASE

NOTES

Bug Report#: 917
System: VAX-VMS
Version: 2.21
Reported by: Leonard Cardoza
Date received: 8/15/86
Description: On a PAL22V10.test a stack dump caused
equations to abort, and 015.TRST and 018.TRST equations
•
were accepted when they contained the illegal character :+:.
Bug Report #: 949
System: VAX-VMS
Version: 2.21
.
ReporteJ~y: Nancy Hensley
Date receiVed: 8/28/86
Description: An incorrect part name (16RP8 instead of 16RA8)
caused a Pascal dump.
Bug Report #: 954
System: VAX-VMS
Version: 2.21
Reported by: Marilyn Gleason
Date received: 9/3/86
Description: On PAL32VX10, the 25th pin name accepts the
word GLOBAL, but does not accept any other name. However,
on PAL22RX8 and PAL22V10 other names are accepted.
Bug Report #: 970
System: VAX-VMS
Version: 2.21
Reported by: Nancy Hensley
Date received: 9/8/86
Description: If a zero length file is specified when the PALASM2
program is run, a Pascal dump occurs.

Monolithic

W Memories

RN·27

HELEASE

NOTES

Bug Report #: 990
System: IBM-PC, VAX-VMS
Version: 2.21
Reported by: S.Scard
Date received: 9/22/86
Description: When XPLOT is run on a PAL32VX10 design file,
with I/O pin as an input OUTPUT. TRST = GND in the hard code,
and with no other output equations, the message Setting. TRST
= GND ... Cannot Define The Output... is displayed.
Bug Report #: 998
System: IBM-PC, VAX-VMS
Version: 2.21
Reported by: Marilyn Gleason
Date received: 9/25/86
Description: On all devices, the EQUATIONS section should be
optional.
Bug Report #: 1005
System: VAX-VMS
Version: 2.21
Reported by: Marilyn Gleason
Date received: 10/2/86
Description: When a State Machine file that does not contain a
Simulation section is run through the PALASM2 program, error
messages are displayed.
Bug Report #: 1010
System: VAX-VMS
Version: 2.21
Reported by: Nancy Hensley
Date received: 10/7/86
Description: On a PAL part with a state machine design, an error
occurs if a condition or equation with a slash (I) before the equals
(=) sign is used. The message Missing Keyword Equation is
displayed.

RN·28

Monolithic

W Memories

RELEASE

NOTES

Bug Report #: 1013
System: VAX-VMS
Version: 2.21
Reported by: Nancy Hensley
Date received: 10/13/86
Description: If you attempt to use a Bin command in the
Equations section of a file, a PALASM2 dump occurs.
Bug Report #: 1017
System: VAX-VMS
Version: 2.21
Reported by: Nancy Hensley
Date received: 10/16/86
Description: Using XPLOT, a Bin command in Boolean
equations causes a Pascal dump.
Bug Report #: 656
System: VAX-VMS
Version: 2.18
Reported by: Mike Gzowski
Date received: 12/10/85
Description: When the keyword EQUATIONS is missing, an error
message should be displayed.
Bug Report #: 840
System: IBM-PC
Version: 2.19
Reported by: Howard Tang
Date received: 5/12/86
Description: The Stag programmer does not accept the JEDEC
files generated by PALASM2. It displays a checksum error when
the JEDEC files are loaded in.

1;1:'

IWonoIlthic

W Memories

RN·29

Ht:Lt:A~E

NOTES

Bug Report #: 959
System: VAX-VMS
Version: 2.21
Reported by: Marilyn Gleason
Date received: 10/31/86
Description: On the PALASM2.G03 test, an error message
about an extra parenthesis in a Simulation WHILE loop is
displayed. This occurs when the number of parentheses is
accurate.
Bug Report #: 1035
System: VAX-VMS
Version: 2.21
Reported by: K. Toland
Date received: 11/6/86
Description: On PAL32VX10, PALASM2 does not accept any
other pin name besides GLOBAL on the Global pin.
Bug Report #: 860
System: IBM-PC
Version: 2.20
Reported by: Leonard Cardoza
Date received: 6/6/86
Description: The JEDEC standard states that the Device Type
field is obsolete. Programmers other than Data I/O cannot
handle Device Types. Why not eliminate the D line from the
JEDEC file completely?
Bug Report #: 869
System: IBM-PC, VAX-VMS
Version: 2.20
Reported by: Marilyn Gleason
Date received: 10/31/86
Description: PALASM 2 software should support PRLD family
codes on parts that are both preloadable and non-preloadable.

RN·30

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RELEASE

NOTES

Fixed Bugs:
SIMULATOR
Bug Report #: 770
System: IBM-PC
Version: 2.19
Reported by: Leonard Cardoza
Date received: 3/19/86
Description: On PAL 16R8, SETF ClK and SETF /CLK=l on
the next line causes ClK=H in outputs instead of ClK=L. Since
the outputs then are not accurate, the device fails the verify test
on the programmer.
Bug Report #: 826
System: IBM-PC
Version: 2.19
Reported by: B. Peeters
Date received: 5/7/86
Description: When the user sets a clock pin at SETF, and then
tries to clock the clock pin, incorrect output is placed in the
JEDEC file.
Bug Report #: 896
System: IBM-PC
Version: 2.20
Reported by: Marilyn Gleason
Date received: 10/31/86
Description: On PAL16RA10 and PAL16RA8 tests, the design
will not verify as the Output Enable and Three-state equations
are evaluated incorrectly.

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Memories

RN·31

RELEASE

NOTES

Bug Report #: 898
System: IBM-PC
Version: 2.20
Reported by: leonard Cardoza
Date received: 7/24/86
Description: PAl20RA10 and PAl16RA8 do not simulate
correctly with three-states of an output used as an input. In the
.HST and .JDC file, the pin goes from Z to H, lor 0, 1 when
SETF'D.
Bug Report #: 899
System: IBM-PC, VAX-VMS
Version: 2.20
Reported by: leonard Cardoza
Date received: 7/24/86
Description: On PAl32VX10, when an output is set to threestate, any other combinatorial output set equal to that first output
should go to X. Currently, they retain their old values in .HST and
.JDC.
Bug Report #: 900
System: IBM-PC, VAX-VMS
Version: 2.21
Reported by: leonard Cardoza
Date received: 7/23/86
Description: On a PAl32VX10 test, buried registers were
preloaded. When an input was changed, however, the buried
register's output in the .HST file seemed to change without the
register having been clocked.
Bug Report #: 908
System: IBM-PC
Version: 2.21
Reported by: Chris Jay
Date received: 8/8/86
Description: On PAl32VX10, when ClK is used as an inputnot as a clock- the output is combinatorial. When you SETF ClK
or SETF IClK, however, vectors are not generated.

RN·32

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Memories

RELEASE

NOTES

Bug Report #: 909
System: VAX-VMS
Version: 2.21
Reported by: Chris Jay
Date received: 8/8/86
Description: On PAL32VX10, the clock input from the fuse array
was gated to a combinatorial output. When enabled, that output
was half the actual clock frequency, although it should have been
the same.
Bug Report #: 910
System: VAX-VMS
Version: 2.21
Reported by: Leonard Cardoza
Date received: 8/12/86
Description: On a PAL22V10 test, you find invalid check clashes
because of the second assertion of the global SETF line. Also,
SET and RESET lines for pins 13 and 14 are both high. The
register should be set correctly, instead of changed to X.
Bug Report #: 964
System: IBM-PC
Version: 2.21
Reported by: B. Hsiang
Date received: 9/3//86
Description: .JDC test vectors in PAL20X10 contain 0,1 for
outputs instead of L,H. This causes the programmer to attempt
to apply voltages to outputs.
Bug Report #: 971
System: VAX-VMS
Version: 2.21
Reported by: S. Kuang
Date received: 9/8/86
Description: The preloaded values in the PAL 16RP8 did not stay
after the preload process was done.

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I ;j ~ I
-

••• -

RN·33

RELEASE

NOTES

Bug Report #: 974
System: IBM~PC, VAX-VMS
Version: 2.21
Reported by: S. Scard
Date received: 9/9/86
Description: The PAL16R8 vectors contain 0,1 instead of L,H.
Bug Report #: 984
System: IBM-PC, VAX-VMS
Version: 2.21
Reported by: Marilyn Gleason
Date received: 9/1 0/86
Description: PAL20RA10, PAL20X10, PAL20X4, and PAL20X8
will not verify because the output pins in the JEDEC file are Z's
when the output enable pin is O. The history file is incorrect and
sems to be missing a column.
Bug Report #: 758
System: IBM-PC
Version: 2.19
Reported by: Leonard Cardoza
Date received: 2126/86
Description: You cannot write a PAL20RA10 where .TRST =
LOWoutput. All outputs stay in Z state after .TRST goes low
even when they are SETF in SIM.
Bug Report #: 875
System: IBM-PC
Version: 2.20
Reported by: Chris Jay
Date received: 6/24/86
Description: Test vector generation in the PAL24X family is
incorrect. The message says that only the B parts are
preloadable. In fact, both the A and the B parts are preloadable
and only the standard parts are not preloadable.

RN·34

RELEASE

NOTES

Bug Report #: 897
System: IBM-PC, VAX-VMS
Version: 2.21
Reported by: Leonard Cardoza
Date received: 7/23/86
Description: The file PORT.PDS leaves the outputs enabled
when the OE pin is H. However, it reverts to the enabled
condition for unknown reasons.
Bug Report #: 915
System: VAX-VMS
Version: 2.21
Reported by: Leonard Cardoza
Date received: 8/15/86
Description: On a PAL22V10 test, an incorrect error message No
Clock Pin Defined For This Device... was displayed. A more
accurate error message would be Cannot CLOCKF this pin.
Bug Report #: 916
System: VAX-VMS
Version: 2.21
Reported by: Leonard Cardoza
Date received: 8/15/86
Description: On PAL22V10, after doing the PRLDF of pins 014,
015, 016 ... 023, a message should appear which tells the user
that the JEDEC output switched off.
Bug Report #: 918
System: VAX-VMS
Version: 2.21
Reported by: Nancy Hensley
Date received: 8/15/86
Description: On a PAL22RX8 test, a loop occurs in SIM. The
repeated message is Warning #16: 015 SET RESET Both Are
High For Above Output.

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RN·35

RELEASE

NOTES

Bug Report #: 925
System: VAX-VMS
Version: 2.21
Reported by: Nancy Hensley
Date received: 8/20/86
Description: On PAL22V10 and PAL22RX8, SIM displays a
message saying that SET or RESET is always high, and then
aborts.
Bug Report #: 931
System: VAX-VMS
Version: 2.21
Reported by: Marilyn Gleason
Date received: 8/27/86
Description: PAL22V10 and PAL22RX8 need to have the
PRELOAD implemented in the code.
Bug Report #: 943
System: VAX-VMS
Version: 2.21
Reported by: Marilyn Gleason
Date received: 8/27/86
Description: On PAL20X4, PAL20R6, PAL20R4, PAL 16R8,
PAL 16R6, and PAL 16R4 warning message number seven is
displayed. It says This PAL Pre/oads Only The B Version Of The
Part For PRLDF Statements. The message should be more
generic.
Bug Report #: 944
System: VAX-VMS
Version: 2.21
Reported by: Marilyn Gleason
Date received: 8/27/86
Description: On PAL20R8, PAL20R6, PAL 16R8, PAL 16R6 and
PAL 16R4, warning message #8 is displayed. It says Registers
Initialized And JEDEC Vector Generation Turned Off. The
JEDEC vector generation should not, in fact, be turned off.

RN·36

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RELEASE

NOTES

Bug Report #: 945
System: VAX-VMS
Version: 2.21
Reported by: Marilyn Gleason
Date received: 8/27/86
Description: The PRLDF commands should work for
PAL32VX10.
Bug Report #: 947
System: IBM-PC
Version: 2.21
Reported by: Barry Seidner
Date received: 8/28/86
Description: The simulator output for the three-state condition is
incorrect.
Bug Report #: 953
System: VAX-VMS
Version: 2.21
Reported by: Marilyn Gleason
Date received: 8/29/86
Description: SIM produced a Pascal dump when the back end
program PALASM2.TRE is missing. An error message telling
the user that the file is missing should be displayed.
Bug Report #: 969
System: IBM-PC
Version: 2.21
Reported by: Theresa Shafer
Date received: 9/4/86
Description: On PAL32R16, error #16: System Oscillation
occurs after the SETF /CLR, but before the FOR loop. This
happens when all outputs with feedbacks are registered.

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RN·37

RELEASE

NOTES

Bug Report #: 989
System: VAX-VMS
Version: 2.21
Reported by: Marilyn Gleason
Date received: 9/18/86
Description: On a 32R16 test, the part failed to verify on the
programmer. This occurs when the second output enable is
High and the first is Low. The output pins for the second output
enable bank should be 1's and a's. Instead, they appear as H's in
the JEDEC file.
Bug Report #: 995
System: VAX
Version: 2.21
Reported by: Marilyn Gleason
Date received: 9/24/86
Description: A test on PAL32VX10 produces error #36:
SET/RESET Are Both High For The Above Output. This error
message is unwarranted, since both can be High on this part.
Bug Report #: 996
System: IBM-PC
Version: 2.21
Reported by: H. Nguyen
Date received: 9/24/86
Description: On PAL 16R6, using an output pin with PIN.TRST in
the equation, and no equation for the output pin causes Sim to
hang.
Bug Report #:1034
System: IBM-PC
Version: 2.21
Reported by: Marilyn Gleason
Date received: 11/11/86
Description: When the Simulator detects GLOBAL.SETF or a
GLOBAL.RSTF equations, it displays error #16: Cannot Have
Simple/Functional Equation For This Pin (Global).

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INDEX
AND
AND array 1-1
AND gates 1-1
AND operator 3A-9
ASCII Tape
how to install the software A-10
AUTOEXEC.BAT 2-9

BINHEX 1-19; 2-12
Boolean
Boolean transfer function 1-1
design file
declaration section 3A-1
equations 3A-8
syntax 3A-3
generating equations from a JEDEC file 1-18

CHECK 3C-1, 3, 7
CHIP 3A-2, 4; 38-8
CLKF 3A-14
CLOCKF 3C-1, 2, 3, 6
Combinatorial Arrays 1-3
Combinatorial Equations 3A-11
Computer<->Programmer Connection
IBM-PC 2-12
VAX 2-13

Declaration Section 3A-1
Boolean 3A-3
State 38-6
DECODE 1-19; 2-12
DEFAULT_BRANCH 38-14
DEFAULT_OUTPUT 38-13

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lID

IX-1

INDEX

EQUATIONS 3A-8
Error Messages
description 4-8
JEDMAN E-34
MINIMIZE E-8
PALASM2 E-1
PROASM-PROSIM E-17
SIM E-32
XPLOT E-2
ZHAL E-30
Examples
design examples 0-1

FOR. .. DO Loop 3C-1
FPLA
Field Programmable Logic Array 1-1
Functional Equations
CLKF 3A-16
RSTF 3A-15
SETF 3A-15
TRST 3A-16
Functional Equations 3A-14
Fusemaps (See XPLOT)

HAL Device
description of 1-5
-submitting a HAL design to MMI F-1

IBM-PC
computer<->programmer connection 2-12
IBM-PC/DOS 2.10 Implementation A-1
IF ... THEN ... ELSE Loop 3C-1
Installation
hard disk 2-6
how to install on the IBM-PC/XTIAT 2-3
how to install PALASM 2 software 2-1
interactive menu 2-7
non-menu mode 2-9
twin floppy system 2-4

IX·2

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INDEX

Interactive Menu
description of 2-2
description of PALASM 1-20
how to customize 2-10
how to install 2-7
Interactive Menu (See also PALASM) 1-20
INVERT operator 3A-9

JEDEC
download the file to the programmer 4-7
how to assemble 4-6
how to disassemble 4-6
JEDEC Standard No. 3A 1-1
JEDMAN
convert PAL22V10 to PAL32VX10 4-7
description of 1-14, 18
disassemble JEDEC 4-6
error messages E-34
recalculate checksums 4-7

MASTER_RESET 38-12
MENU.SYS 2-10
MINIMIZE
description of 1-14, 15
error messages E-8
how to use 4-5
Moore and Mealy machines 38-12

Non-menu Mode
description of 2-2
how to install 2-9

Operator Precedence 3A-10
OR
OR array 1-1
OR gate 1-1
OR operator 3A-9
OUTPUT_ENABLE 38-12
OUTPUT_HOLD 38-12

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IX-3

INDEX

PAL Device
combinatorial arrays 1·3
concept 1·1
devices supported by PALASM 2 software 1·9
product-term sharing 3A·23
programmable I/O 1·3
programmable polarity 1·5; 3A·12, 14
references 1·8
registered outputs with registered feedback 1-4
XOR 1·4
PALASM (See also Interactive Menu)
description of 1·19
PALASM 1 Software 1·6
differences from PALASM 2 software 1·6; H-2
PALASM 2 Software
asynchronous devices 1·7
differences from PALASM 1 software 1-6; H·2
how to install PALASM 2 software (See Installation)
how to use 4·1
assemble the JEDEC 4-6
create the PDS file 4·4
detailed instructions 4-9
disassemble the JEDEC 4-6
minimization 4-5
run the parser 4-4
input and output files 1·21
installation and operation
detailed instructions A·1
interactive menu H·1
introduction 1-6
program and file summary 1·14
references 1·7
required equipment
computersComputers 1·11
programmers 1·12
reserved words 3-3
simulation 3C·1
supported products 1-9
PALASM2
description of 1·14
error messages E·1

IX·4

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INDEX

PC2
description of 1-19, 20; H-3
how to use A-2
how to use with Data I/O programmer 8-5
PDS
create the PDS file 4-4
example files 4-1
file structure 3-2
introduction to 1-6
introduction to 3-1
using a text editor 4-4
PDSCNVT
description of 1-19, 20
Pin List 3A-5, 38-9
PINOUT 1-19; 2-12
PMS14R21 1-5
Pogrammable Polarity 1-5
Polarity 3A-17
POWER UP 3B-21
PROASM-PROSIM
description of 1-14, 18
error messages E-17
PRLDF 3C-1, 3, 4, 12
Product-term Sharing 3A-23
Programmable I/O 1-3
Programmable Logic Devices 1-1
Programmable Polarity 3A-12, 14
Programmer
communication between PLD programmers and IBMTM PC
(See PC2)
Data I/O B-1
how to connect to VAX-VMS B-7
how to use with VAX-VMS B-6
device family pin codes B-3
how to program and test the part 4-7
manufacturer addresses 1-13
programmers supported 1-13
VARIX OMNI B-9
Programming a Device
IBM-PC<->Data I/O A-1
MegaPAL B-9
PROM
Programmable Read-Only Memory 1-1
PROSETM Devices 1-5

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IX-5

INDEX

Registered Equations 3A-12
Registered Outputs with Feedback 1-4
Release Notes RN-1
Required Equipment
computers 1-11
PAL device programmers 1-12
RSTF 3A-15

SCRSIM 1-19; 2-12
SETF 3A-15; 3C-1, 2, 3, 5
SIM
description of 1-14, 17
error messages E-32
Simulation
commands
CHECK 3C-1
CLOCKF 3C-1
PRLDF 3C-1
SETF 3C-1
TRACE_OFF 3C-1
TRACE_ON 3C-1
constructs 3C-3
FOR loop 3C-8
IF ... THEN ... ELSE loop 3C-9
WIHLE ... DO loop 3C-10
introduction 3C-1, 2
output files
history file 3C-2
trace file 3C-2
run simulation software 4-7
syntax
CHECK 3C-7
CLOCKF 3C-6
differences between Boolean and state machine 3C-12
FOR ... DO loop 3C-1, 3, 8
IF ... THEN ... ELSE loop 3C-1, 3, 9
overview 3C-2
PRLDF 3C-4
SETF 3C-5
TRACE_OFF 3C-8
TRACE_ON 3C-7
WHILE DO loop 3C-10
WHILE. .. DO loop 3C-1, 3

IX·6

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INDEX

SIMULATION 3C-3
STATE 38-11
State Machine
creating a design file
DECLARATION section 38-6
Mealy and Moore machines 38-5
STATE section 38-9
structure and syntax 38-5
equations
condition equations 38-25
description 38-14
operators 38-15
output equations 38-19
POWER_UP 38-21
rules 38-15
state equations 38-16
Mealy and Moore Behavior 38-2
STRING 3A-6
Supplementary Software
PALASM
interactive menu H-1
PDSCNVT H-1
Supported Products 1-9
Syntax
diagrams G-1
special syntax
PAL22RX8 C-2
PAL22V10 C-2
PAL32VX10 C-3

Three-state 3A-16
programmable I/O 1-3
TIMING 1-19; 2-12
TRACE_OFF 3C-1, 2, 3, 8
TRACE_ON 3C-1, 2, 3, 7

VAX
computer<->programmer connection 2-13
VAX-UNIX
command procedures A-13
how to install the software A-12

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IX·7

INDEX

VAX-VMS
how to connect to Data 1/0 B-7
how to install the software A-6
software support procedures A-8
Volume Production
see HAL F-1
VTRACE
description of 1-19, 21
VTRACE 2-12

WHILE. .. DO Loop 3C-1

XOR
devices 1-4
minimizing 1-15
XOR operator 3A-9
XPLOT
description of 1-14
error messages E-2

ZHAL
description of 1-14, 18
error messages E-30
how to order the ZHAL program 1-14
how to use 4-7

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PLEASM
MANUAL
lM

Version 1.2H

PLEASM software documentation follows.
Your software package does not incluae
PLEASM software.
If you use PLE devices, please contact your local Monolithic
Memories representative for a copy of PLEASM software.
Monolithic

W Memories

Monolithic

Memorle.

Table of Contents

CHAPTER 1: INTRODUCTION.............................

1-1

CHAPTER 2: PROMs VS. PLEs .••.....•.••.••....•.•.....
2.1 The PROM as a Memory Element. • . • . • . . • . . • ..
2.2 The PROM as a Programmable Logic Element ...

2-1
2-1
2-3

CHAPTER 3: PLE DEVICES SUPPORTED

•.•.••••.••.•.....

3-1

CHAPTER 4: RUNNING PLEASM •.•••••.••.•..•.•••....•..

4-1

CHAPTER 5: PLEASM - AN EXAMPLE.............. .... ...

5-1

CHAPTER 6: THE SYNTAX OF PLEASM ••••••••.• •.• ..•.•••

6-1

APPENDIX A: PLEASM ON THE VAX11IVMS •••••••••••••••
A.1 PLEASM on the VAXIVMS ....................
A.2 PLEASM on the IBM PC DOS 2.0 •.•••••••••.•.

A-1
A-1
A-5

APPENDIX 8:

PROM/PLE PROGRAMMER INFORMATION •.•...

8-1

APPENDIX C:

PLEASM ERROR MESSAGES •.•.•••..•..••••

C-1

APPENDIX 0:

PLE DESIGN FILE Ll8RARY ••••••••...•.•.•••

0-1

APPENDIX E:

HELPII AND WHERE TO GET IT • . • • . • . . . . • • •.

E-1

APPENDIX F:

USER CUSTOMIZATION

F-1

IIIIonoIlthlt:

..••••..•••••••..•.•

lIIIemories

Monolithic

Memories

Inl"'UUU~t;.un

Introduction
PLEASM (Programmable Logic Element ASseMbler) is a software
package developed by Monolithic Memories, Inc. used for designing
with PROMs as Programmable Logic Elements (PLE no s). PLEASM is a
FORTRAN IV program which assembles and simulates PLE Design
Specifications. It also generates programming formats for direct
download to PROM programmers and can therefore be regarded as a
tool that reduces the design-to-production time considerably.

Key Features
•
•
•
•
•

Assembles Logic or Arithmetic equations into a PROM truth
table.
Provides INTEL HEX and ASCII HEX programming formats along
with the hex check sum.
Programming formats can be directly downloaded to standard
PROM programmers.
Simulates the Function Table, in the design equations.
Reports design errors.

The purpose of this manual is to aid the user in running PLEASM and
getting to know and understand all its capabilities. It begins with an
article that describes the wide range of PROM applications and the
motivation for developing a software tool to aid in designing these applications. The next section states the system requirements for
PLEASM. The next two sections give a detailed account of how to run
the program with an explanation of what each of the options accomplish. This is strengthened by an example where all the operations
have been performed on an input file that has the PLE specifications
for basic logic gates. The PLEASM syntax is described next. This is
best understood if this section is read in accompaniment with some of
the design examples that come with the PLEASM program. A detailed
PLE applications handbook is available.

lIIIonoIithit:

mID Me",ories

1·1

..... ..,...... "' .. ..,...
The Appendix gives some machine-specific information about PLEASM
along with details on PROM programmers, the PLE design files supplied
as examples, and user customization. An important part of the Appendix is the section on the errors detected by PLEASM. This should be
very useful when creating your own PLE designs.
The new PLEASM user should read Chapters 3 to 5 initially and then try
to run the demonstration examples. Once the user is ready to create
his own design, Chapters 2 and 6 will provide ideas and details of the
specification format. The Appendices serve to provide additional supporting information on a number of subtleties the user should be aware
of in fully utilizing the software.

1·2

Monolithic

Memories

PROMs VS. PLEs
PROMs have grown steadily in size and speed since their introduction in
1971, when Monolithic Memories introduced the world's first 1K bit
bipolar PROM. Today, 16K and 32K PROMs are readily available and
their speeds have improved such that the maximum address time
(address to output) of these devices is down to 30-40 nanoseconds,
over the complete operating temperature and vee range. This means
that PROMs can be used effectively in both high speed memory and
logic replacement applications.
The PROM implements a sum-of-products Boolean transfer function in
which any possible input (address) combination can be transferred to
any output variable (data out). Figure 2-1 shows logical structure of a
typical PROM. The input Fixed-AND array is a decoder and the output
Programmable-OR array is a decoder. It is this decoder area that is
field programmable to implement any Bo.olean transfer function.
Each output of the AND array is connected to an input of the OR array
by thin metal wire (e.g. titanium-tungsten, nichrome, platinumsilicide) which can be selectively removed from the circuit by passing a
current through it. This is referred to as .. programming" or II blowing" a
"fuse" .

2.1 The PROM as a Memory Element
Because of their high speeds, bipolar PROMs are ideal for use in
systems requiring fast Address-to-Data access times. PROM applications can be found in both the data and control paths of a system.
In data paths, PROMs are used mainly as storage elements to implement different table look-up applications such as trigonometric functions, signal processing coefficients, bootstrapping and initialization
programs, etc. In particular, the PROM can be used to advantage in
the design of digital filters and Fast Fourier Transforms. In character
generator applications, the PROM user has the flexibility of modifying
the conventional fonts to his/her particular requirements.

Monolithic

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2-1

A-S C-O=F4
A·S·C·O:F3
A·S·C·O'F2
A· B : C • 0 = F1
FUNCTION

•.

Fl F2 F3 F4

AOORESS AO A1 A2 A3

OUTPUT

01 02 03 04

--0

_1.... 0 I 1- 1

14
15

-1

1
1

1
1
1

Figure 2-1. Typical PROM Structure

In control paths, PROMs are used mainly to store microprograms.
Microprogrammed controllers may be simple PROM-register finite
state machines or they may be complex microprogrammed CPUs,
where the complete instruction set of the system resides in PROM. It is
thus possible, by using PROMs for microprogramming, to use the
same hardware to emulate the characteristics of various processors.
Since most memory applications involve storing PROM memory data in
a temporary register before it is used (pipelining), this has spawned a
new generation of PROMs with on-board D-type edge-triggered registers. These registered PROMs operate faster than discrete PROMregister combinations, and the registered PROMs also occupy less
space.

2-2

Monolithic WMemorles

Prom vs. PLI:S

2.2 The PROM as a Programmable Logic Element
The PROM implements a sum-of-products Boolean transfer function so
that any function of x inputs and y outputs may be generated in a PROM
with x addresses and y data outputs. Figure 2-2 shows the combinatorial functions available in a hypothetical 16 X 4 PROM.

rv
f-

PROGRAMM....U
OR

IV
"""'"
r<

i=::
=:
=:

=<
K

i-' f-'

?<
K

2"
PRODUCT
TERMS

=<
=<
=<
==:(.

r<
=:

- 99YY
=:

'IUD
AND

Figure 2-2. Combinatorial Functions
Available in a Hypothetical 16x4 PROM

The AND-OR structure of the PROM can be viewed as a two-level logic
circuit. The fixed AND plane contains all possible input combinations.
Each input combination is a product term and it is connected to the
output in the OR plane.

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2-3

...rom vs...LI:S
In terms of a PLE circuit, a product term is the equivalent of an AND
gate equal in size to the number of inputs. Each output is equivalent to
an OR gate connected to a/l the AND gates. Programming a fuse blows
this connection between the AND gate and the OR gate. The PROM
thus conveniently implements combinatorial logic when a large number
of input combinations are required or a large number of product terms
per output is desired.
Most applications of PLEs are in synchronous control systems where
they replace random logic or customise logic functions. In data paths,
they are used to generate complex functions such as pseudo random
number generators, ALU operations, multiplications, reciprocals, etc.

2-4

/IIIonollthlc

Memories

3. PLE Devices supponea

PLE DEVICES SUPPORTED
This version of PLEASM supports all of the present members of the PLE
family. Several soon to be released PLEs ~ are also supported. Supported PLEs are summarized in the Selection Guide below. Consult the
PLE Data Sheet for pinouts and detailed specifications.
Part
Number
PLE5P8
PLE5P8A
*PLE5P16
*PLE5P16-2
*PLE6P16
PLE6P16-2
PLE8P4
PLE8P8
PLE9P4
PLE9P8
PLE10P4
PLE10P8
PLE11P4
PLE11P8
PLE12P4
PLE12P8
*PLE13P8
PLE9R8
PLE10R8
PLE11RA8
PLE11RS8

Note:

Pins Inputs Outputs
16
5
8
16
5
8
24
16
5
24
16
5
24
6
16
24
6
16
16
8
4
20
8
8
16
9
4
20
8
9
4
18
10
24
10
8
18
11
4
24
11
8
20
12
4
24
12
8
24
13
8
24
9
8
24
10
8
24
11
8
24
11
8

Product
Terms
32
32
32
32
64
64
256
256
512
512
1024
1024
2048
2048
4096
4096
8192
512
1024
2048
2048

Output
Registers

Max

8
8
8
8

25ns
15ns
15ns
30ns
15ns
30ns
30ns
28ns
35ns
30ns
35ns
30ns
35ns
35ns
35ns
40ns
45ns
15ns
15ns
15ns
15ns

125mA
125mA
180mA
100mA
200mA
110mA
130mA
140mA
130mA
155mA
140mA
160mA
150mA
185mA
175mA
190mA
190mA
180mA
180mA
185mA
185mA

tPD

ICC

All outputs are three-state. Only Commercial Specifications
are listed. Clock to output times are given for Registered
PLEs.

• Contact MMI for availability of the following PLE parts: PLE5P16,
PLE5P16-2, PLE6P16, PLE6P16-2, and PLE13P8. The specifications
for these parts are preliminary.

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3-1

MonolithicW Memories

USER'S GUIDE TO PLEASM-PLE ASSEMBLER
VERSION 1.2H
To get started with PLEASM, turn the computer ON. Check your directory to make sure you have the files mentioned in Appendix A. Once
this has been verified, run the program as explained below with one of
the example files. Our suggestion is to start with the file P5000.PLE
which contains the PLE Design Specificat,ions for the basic logic gates.
Once the capabilities of the program have been understood, you can
work with any of the other examples or attempt to create your own
designs.

USING PLEASM
Type the system's execute command to run the program. PLEASM will
respond ...•
MONOLITHIC MEMORIES PLEASM(tm} VERSION 1.2H
(C) COPYRIOHT 1984 MONOLITHIC MEMORIES
WHAT IS THE SOURCE FILENAME (d:filename.ext) ?:P6000.PLE

At this point enter the name of the file containing the specifications for
the PLE being designed . If you are using this package for the first time,
we suggest you try out one of the design examples that was sent along
with PLEASM. PLEASM next prompts you for the name of the file you
could have the output sent to, defaulting to the console ....
OUTPUT FILENAME - PRESS <ENTER> FOR NO OUTPUT FILE 1:

If you press <enter>/<return> the output will be sent to the console
after each operation. At this point, the input file is read, and a count of
lines and characters in the file is written out to the screen. The next
prompt is for the operation you want performed and is ....
E=ECHO INPUT
H=HEX TABLE

S.SIMULATE T=TRUTH TABLE
I-INTEL HEX A-ASCII HEX

B=BRIEF TABLE
C=CATALOO Q-QUIT

ENTER OPERATION CODE:C

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4·1

You can now enter the appropriate operation code,
CASEI!.

UPPER

The various options are briefly discussed below.
E ECHO INPUT. Prints the input PLE specifications file. Useful as a
ready reference while working interactively with PLEASM.
S SIMULATE. Exercises the logic values in the optional function table
in the logic equations provided. Errors in the function table are
detected along with fairly explicit diagnostic messages. An important
point to note is that all "don't care" conditions are treated as low logic
values. This option can be successfully invoked only when a function
table is present in the input specifications.
T TRUTH TABLE. Prints out the entire binary truth table for all the Input
variables in the PLE by substitutions into the Boolean equations
specified. The output has a tabular format for ease of reading. The
program also provides a hex checksum for the entries in the truth table
at the end.
B BRIEF TABLE. Prints out the truth table only for the used input addresses in the PLE, again by substitutions Into the Boolean equations.
The output is tabulated as before, this time with a partial hex checksum
corresponding to the possibly shorter table.
H HEX TABLE. Prints out the entire truth table as before, except the
inputs and outputs are translated into hex. Also generates a tabular
format with a hex checksum.
lINTEL HEX. Generates the Intel Hex format for PROM programmers
for both 4- and a-bit data downloading. The format is shown below ....
:AABBBBOOCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCDO
AA
BBBB
C.. C
DO

starting colon marker
Record length in hex
Record start in, address in hex
Data
Hex checksum

NIonoIlthlc

/IIIemories

Here all data is sent in streams cif 16 a-bit bytes starting at OOOOH.
4-bit data is padded up with zeros in the most significant four places.
The checksum is the negative of the sum of all a-bit bytes starting at
.. AA" up to DD", modulo 256. Transmission is terminated by the
string :00000001 FF" .
II

A ASCII HEX SPACE. Generates the ASCII Hex format for PROM
programmers for 4- and a-bit data downloading. The format is
shown below ....
A

BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB BB
C

A --> Record start character (STX)
BB --> Data byte
C --> End of text character (ETX)

Data is sent in streams of 16 a-bit bytes separated by spaces. An
execute character, the ASCII period ".", is sent at the end of each
stream of data. 4-bit data is padded up with zeros in the most significant 4 places. In addition, a hex checksum is passed at the end of
the transmission.
C CATALOG. Prints a one..;line description of each option provided by
PLEASM. Always displays to the console.
CATALOG OF OPERATION CODES:
MONOLITHIC MEMORIES PLEASM(tm) VERSION 1.2H
PLEASM --PLE ASSEMBLER-- PROVIDES THE FOLLOWING OPTIONS
C
E
T
B
H

CATALOG
ECHO INPUT
TRUTH TABLE
BRIEF TABLE
HEX TABLE

PRINTS
PRINTS
PRINTS
PRINTS
PRINTS

THE PLEASM CATALOG OF OPERATIONS
THE PLE DESIGN SPECIFICATIONS
THE ENTIRE TRUTH TABLE
ONLY USED ADDRESSES IN THE TRUTH TABLE
THE TRUTH TABLE IN HEX FORK

S SIMULATE'

- EXERCISES THE FUNCTION TABLE
EQUATIONS

I INTEL HEX
A ASCII HEX

- GENERATES INTEL HEX PROGRAMMING FORMAT
- GENERATES ASCII HEX PROGRAMMING FORMAT

Q QUIT

- EXITS PLEASM

WIonoIHhlc

Memories

THE

LOGIC

Q QUIT. Exits the PLEASM program and prompts for restarting with
another input specifications file.

4·4

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5. PLEASM - An Example

ECHO
Echoes the input PLE Design Specifications file. This will help verify that
the input file has been read in correctly.
ENTER OPERATION CODE: E
PLE5P8
P5000
BASIC OATES
MMI SANTA CLARA, CALIFORNIA

PLE DESION SPECIFICATION
VINCENT COLI 01/12/84

. ADD 10 11 12 13 14
. OAT 01 02 03 04 05 06 07 08
01
02
03
04
05
06
07
08

• 10
• 110
• 10
• 10
• 110
• /10

•
•

10
10

BUFFER
INVERTER
AND OATE
OR OATE
NAND OATE
NOR GATE
EXCLUSIVE OR OATE
EXCLUSIVE NOR OATE

11 * 12 * 13 * 14
11 + I2 + 13 + 14
+/11 + II2 + 1I3 + /14
* III * /12 * /13 * /14
:+: 11 :+: 12 :+: III :+: 14
:*: 11 :*: 12 :*: 13 :*: 14

*
+

FUNCTION TABLE
10 11 12 13 14 01 02 03 04 05 06 07 08
;INPUT
;01234

BUF

LLLLL
HHHHH
HLHLH
LHLHL

L
H
H
L

OUTPUTS FROM BASIC OATES
INV AND OR NAND NOR XOR

XNOR

COMMENTS

------------------------------------------------------------------_.
H
L
L
H

L
H
L
L

L
H
H
H

H
L
H
H

H
L
L
L

L
H
H
L

ALL ZEROS
ALL ONES
ODD CHECKERBOARD
EVEN CHECKERBOARD

DESCRIPTION
THIS EXAMPLE ILLUSTRATES THE USE OF PLEs TO IMPLEMENT THE BASIC
OATES: BUFFER, INVERTER, AND OATE, OR OATE, NAND OATE, NOR OATE,
EXCLUSIVE OR OATE, AND EXCLUSIVE NOR OATE.
NOTE ALSO THAT THREE-STATE OUTPUTS ARE PROVIDED WITH ONE ACTIVE LOW
OUTPUT ENABLE CONTROL (IE).
PLEASM OENERATES THE PROM TRUTH TABLE FROM THE LOOIC EQUATIONS AND
SIMULATES THE FUNCTION TABLE IN THE LOOIC EQUATIONS.

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5-1

PLEASM - An Example

SIMULATE
This option verifies that the output entries in the Function Table
are correct for the given 800lean equations and input vectors. Any
discrepancy between the expected output value as given in the Function Table and the output value as computed from the 800lean equations is flagged as an error. The following are acceptable input entries
in the Function Table:
H - High level
L - Low level
X - Irrelevant
ENTER OPERATION CODE: S
FUNCTION TABLE
IO Il I2 I3 I4 01 02 03 04 OS 08 07 08
;INPUT
;01234

- - OUTPUTS FROM BASIC OATES
BUF INV AND OR NAND NOR XOR XNOR

COMMENTS

------------------------------------------------------------------LLLLL
L
H
H
L
L
ALL ZEROS
H
L L
HHHHH
HLHLH
LHLHL

H
H
L

L
L
H

H
L
L

H
H
H

L
H
H

L
L
L

H
H
L

PASS SIMULATION

5-2

IIIIonoIlthlo

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ALL ONES
ODD CHECKERBOARD
EVEN CHECKERBOARD

PLEASM - An Example

TRUTH TABLE
Generates an exhaustive binary truth table for all the given inputs by
substitution in the Boolean equations.
ENTER OPERATION CODE: T
BASIC GATES
.ADD 10 11 1213 14
.DAT 01 02 OS 04 00 08 07 08
ADD

AO A1 A2 A3 A4

00 01 02 03 04 OS 08 07

1
2

H
L

L
H

L
L

H
L

L
H

L
L

H
H

L
L

H
H

21
30

H
L
H

L
H
H

H
H
H

H
L
H

L
H
L

L
L
H

H
H
H

H
H
L

L
L
L

L
L
H

----------------------------------------------0
L L L L L
L H L L H H L L

-----------------------------------------------

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5-3

PLEASM • An Example

BRIEF TABLE
Prints the truth table for only the used input and output pins.
ENTER OPERATION CODE:

.ADD IO I1 I2 I3 I4
.OAT 01 02 03 04 05 06 07 08
BASIC GATES
ADO

AO A1 A2 A3 A4 00 01 02 03 04 05 06 07

-------------------------------------------0
1
2

L
H
L

L
L
H

L
L
L

L
H
L

H
L
H

L
L
L

L
H
H

H
H
H

H
L
L

L
H
H

29
30
31

H
L
H

L
H
H

H
H
H

H
L
H

L
H
L

L
L
H

H
H
H

H
H
L

L
L
L

L
L
H

--------------------------------------------

5·4

MonolithicW Memories

PLEASM • An Example

HEX TABLE
Generates the truth table with input and output vectors translated into
hex.
ENTER OPERATION CODE: H
BASIC CATES
.ADD 10 11 12 13 14
.DAT 01 02 03 04 05 08 07 08
HEX ADDRESS

HEX DATA

000

0032

001
002

0009
OODA

29
30
31

010
OlE
OlF

00111
OOlA
OOCD

ADD

NIonoIlthlo

W ••morles

5·5

PLEASM - An Example

INTEL HEX
Generates the Intel Hex programming format for downloading to a
PROM programmer.
ENTER OPERATION CODE:
:1000000032D9DA19DA191AD9DA191AD91AD9DA1940
:10001000DA191AD91AD9DA191AD9DA19DA191ACD54

:OOOOOOOlFF

5-6

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PLEASM • An Example

ASCII HEX
Generates the ASCII Hex Space programming format for downloading to a PROM programmer. with the required <STX>. <SOH>. AND
<ETX> control characters delimiting the transmission.
ENTER OPERATION COOE: A
-B-A
32 09 OA 19 OA 19 1A 09 OA 19 1A 09 1A 09 OA 19
OA 19 1A 09 1A 09 OA 19 1A 09 OA 19 OA 19 1A CO
-C

oonc

Mono/lthlc W.emorles

5·7

PLEASM - An Example

QUIT
Exits PLEASM and prompts for restarting with another input file.
ENTER OPERATION CODE: Q
RESTART PLEASM(Y/N) 7:

5-8

ItIIono/ilhlo

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6. The Syntax of PLEASM

PLE DESIGN SPECIFICATION
The PLE Design Specification is the input file used with PLEASM. It is
also the recommended data sheet format for describing the function of
a PROM, once it has acquired the unique personality of a particular
fuse pattern. This format for creating an input specifications file can
be best understood by studying the examples that come along with this
package. The format for the PLE Design Specification is:
Line 1

PLE part number, starting in column 1, followed by the
words PLE DESIGN SPECIFICATION.

Line 2

User's part number followed by the deSigner's name and
the date, starting in column 1. This may be an identifier
that defines the application and is used for reference.

Line 3

Device application name, starting in column 1.

Line 4

User's company name and address, starting in column 1.

Lines 2-4 are without formal rules and are provided for documentation
purposes.
Line 5

Address pin list, prefixed by .ADD, starting in column 1.
The pin list should be ordered LSB first"

Line 6

Data pin list, prefixed by .DAT, starting in column 1. The
pin list should be ordered LSB first.
The pin list is a sequence of symbolic names separated by
one or more spaces on one or more lines in the order of
the device pin numbers. Each symbolic name is unique
(except the unused pins which may have the same name).
All pins including power and ground must be named.
Names may use any printable characters except the
operators ';', '.', ',', '=', '.', and '+'. The prefix '/' is
used to logically complement the name.

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6-1

The Syntax of PLEASM

Line m

EQUATIONS
The transfer function of the device is expressed in the following form:
SYMBOL

= EXPRESSION

The following terms are used to construct the equations:
SYMBOL

Pin Name with optional prefix '/'

EXPRESSION

A sequence of SYMBOLS separated by
operators.

OPERATORS (in hierarchy of evaluation)
Comment follows
Dot operator (pin list or arithmetic operator follows)
ADD

Address pins (Inputs)

OAT

Data pins (Outputs)

•

Delimiter, separates binary bits (MSB first)

= Equality (combinatorial)
BOOLEAN OPERATORS
/

Complement, prefix to a pin name

AND (PRODUCT)

+ OR (SUM)

6·2

:+:

XOR (EXCLUSIVE OR)

•* •

XNOR (EXCLUSIVE NOR)

Monolithic

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The Syntax of PLEASM
ARITHMETIC OPERATORS

Line n

..*

Multiply (Arithmetic multiplication)

.+.

Plus (Arithmetic addition)

FUNCTION TABLE
The function table begins with the key word FUNCTION
TABLE, starting in column 1 of a line following the equation
list. It is followed by a pin list which may be in a different
order and polarity from the pin list in Lines 5 and 6. The pin
list is followed by a line of dashes (-'s) which is in turn
followed by a list of vectors, one vector per line. One state
must be specified for each pin name and optionally
separated by spaces.
A vector is a sequence of states listed in the same order
as the function table's pin list and followed by an optional
comment. The vector list is followed by another dashed
line.
An important restriction is that blank lines are not permitted
in the body of the function table. To separate logically distinct parts of the function table, however, comments can
be used. In other words, blank lines are permitted with a
semicolon (:) in the first column. Additionally, comments
can be placed in this line. Extra blank lines might result in
the simulator scanning past the end of the function table
and detect "_" as an error symbol, resulting in failure to
pass simulation.
A function table is optional and need be present only for
simulation to be performed. The keyword FUNCTION
TABLE, however, is necessary in the input file. This should
start in column 1, and should follow the equation list.

Monolithic

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6·3

The Syntax of PLEASM

Definition of Function Table States:

Symbol

Line 0

Definition

Input

Output

HIGH LEVEL.

Drive High

Test High

L.OW L.EVEL.

Drive L.ow

Test L.ow

IRREL.EVANT

Don't Care Condition

00 Not Test

DESCRIPTION
This begins with the keyword DESCRIPTION, starting in
column 1. The device operation and application are
described here. All the lines following the keyword
DESCRIPTION are treated as comments. Even though the
lines following may be blank, the keyword DESCRIPTION is
necessary in the input file for assembly.

An informal grammar for the input specifications file is given below:

PLE_TYPE_LINE -:> PLE<PLE PART NUMBER:> ". PLE DESIGN SPECIFICATION
PLE_PATTERN_UNE -:> <REFERENCE NUMBER FOR APPUCATlON, AUTHOR'S NAME:>

COMPANY_INFORMATlON_UNE -:> <COMPANY NAME AND APDRESS:>

EQUATION_LIST -:> <WST OF BOOLEAN EQUATIONS:>
FUNCTION TABLE

6-4

MonoIlthIcW • •morlea

The Syntax of PLEASM
FUNCTION_TABLE-':'IN_UST-> <LIST OF PINS TO BE SIMULATED>
FUNCTION_TABLE -> HILIX <ENTRIES DEFINING LOGIC VALUES FOR THE PINS>
DESCRIPTION
COMMENTS -> <COMMENTS DESCRIBING APPUCATION>
where,

[ •. )

<.. >

denote. an optional expreSilon,
denote. an Informal repre.entatlon for the expression,
denote. a keyword,

and

'I'

denote. the "OR" operator.

IMPORTANT NOTES ON PLEASM INPUT SPECIFICATIONS
1. The specifications file must contain the keywords FUNCTION
TABLE and DESCRIPTION starting in column 1 for assembly to
occur.
2.

All responses to PLEASM prompts should be in upper case.

3. The input specifications file should be entirely in upper case.
4. The number of characters in the file, the number of lines in the file,
and the number of characters in each line should be within the
limits set in the I/O initialization package. The current limits set are
9999 chars/file, 250 lines/file, and 80 chars/line.

Monolithic

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6-5

Monolithic

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Appendix A: PLEASM on the VAX11/VM5

A.1

PLEASM ON THE VAX11/VMS

The following files should be in your tape if you have the Load/Go System:
PLEASM.EXE. This is the executable file that can be invoked to assemble your input PLE specifications.
P5000.PLE through P5032.PLE. These are the example files containing
some applications. They are useful for studying how the input file
should be written, and can be run with PLEASM to provide an on-line
demonstration of how the program works. Details on the contents of
these files can be found in Appendix D.
fOINIT.FOR.User customization package for array dimensions and
I/O.

If you have ordered the Development system, you should have in addition the files:
PLEASM.FOR. This file contains the FORTRAN source for the PLEASM
program and can be compiled by any FORTRAN compiler you have at
your disposal.
lOLlS. FOR. This file contains the I/O features that make this version of
PLEASM compatible with that on the IBM PC. This will have to be linked
in with the main program during compilation.

Unloading Your Magnetic Tape under VAX/VMS
Helpful Hints
•

The volume is labelled PLEASM and is recorded in Files-11 format, 1600 BPI and 9-track magnetic tape.

•

For the neophytes who wish to learn everything there is to learn
about mag tapes and more, Digital Equipment Corporation has
published The Magnetic Tape Users' Guide (Order No. AAM539A-TE).

Monolithic

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A-1

PLEASM on the VAX ii/VMS

•

Your tape drive goes by many different names. For example,
MTAO: or MSAO:. To list all devices on your installation, type
SH DEV M<cr> when you see the $ prompt.

After loading your tape on the drive, when you see the $ prompt, type
the following:

$ ALL MTAO: TAPE
This allocates space for TAPE on device MTAO.

$ MOUNT/OVER=IDENT TAPE
This mounts the tape and overrides any tape labels. Operator
privileges are sometimes required to do this.

$ CREATE/DIR [.PLEASM]
$ SET DEFAULT [.PLEASM]
This sets up the directory appropriately.

$ COPY TAPE:*.*j* []*
This copies the tape files to your directory.

$ DISMOUNT TAPE
Dismounts tape and wraps things up.
DISREGARD THIS MARKED SECTION IF YOU HAVE THE LOAD/GO
SYSTEM II

••••••••• _- ••• __ •••••• _------_ ••• *_ •••••• _--_ •• _•• __ •• *

Compile and link the source program using the following sequence
of commands, to create the executable version:

$ FORTRAN PLEASM,IOLIB
$ LINK PLEASM,IOLIB

._ .. _._._.-.-._---_._ .... _._--------------------_ .. ---*

A-2

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PLEASM on the VAX ii/VMS

Using PLEASM
Create your PLE Design Specification file using one of your system s
editors. Then type the following:
I

$ RUN PLEASM
The program PLEASM should now run. At this point, refer to Chapter
4 for step-by-step instructions on how to use the program.

Dumping a File From the VAX11/VMS to the Data I/O
Cable Connections
The RS-232C cable that connects the VAX-11 to the Data 110 has
lines 2 and 3 reversed. The only other pins that must be connected
are pins 1 and 7.
Operating Procedures
1. Turn Data 1/0 power off.
2. Connect the Data 110 programmer to the modem and VT100 terminal as shown in Fig. A-1. 1•
3. Turn the Data 1/0 programmer on.
4. Press the "SELECT" (Data I/O).
5. Enter" EB" (Data 1I0)
6. Press the" START" (Data I/O).
7. Type "TYPE FILENAME.OAT" (VT100).
8. Press "RETURN" on the VT100.
9. Disconnect VT100 terminal from the modem and Data 1/0.

Monolithic

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A·3

PLEASM on the VAX11/VMS

10. Reconnect Data 110 to VT100 as shown in Fig. A-1.2.
11. Press the
12. Enter
13. Press

SELECT" (Data 110).

E1" (Data 1/0).

START" (Data 1/0).

14. Use VT100 keyboard in order to communicate with the Data 1/0.
PROGRAMMER

MODEM

VT100

1 0
2 0
3 0

010
020
030

0 1
0 2
o3

"
5
6
7

o" 0
050
0 6 0
0 7 0

o0 "5

PROTECTIVE GND
SEND DATA
RECEIVE DATA
RTS
CTS
DSR
SIGNAL. GND

0
0
0
0

0 6
o7

PROTECTIVE GND
SEND DATA
RECEIVE DATA

SIGNAl. GND

Figure A-1.1. Downloading from Host (VAX-11) to Programmer
(VAX Talking to Programmer and VT100)

PROGRAMMER

VT100

1 0
2 0
3 0
0
5 0
6 0
7 0

o 1
o2
o3
oo "5
o6
o .7

PROTECTIVE GND
SEND DATA
RECEIVE DATA
RTS
CTS
DSR
SIGNAl. GND

PROTECTIVE GND
SEND DATA
RECEIVE DATA

SIGNAl. GND

Figure A-1.2. Using Programmer as Host

A·4

NIonoIIth/c

W llllemori••

PLEASM on the VAX 11/VM5

A.2 PLEASM ON THE IBM PC DOS 2.0 (OR ABOVE)
Please note that for the IBM PC. system requirements are as follows:
•
•
•
•
•

8088 based microprocessor system
64K bytes minimum of memory
MS-DOS (PC-DOS) operating system
Optional text printer
1 disk drive.

The IBM PC version comes with a diskette which contains the following
files:
Disk #1:

PLEASM.EXE ( if the Load/Go system has been ·ordered)
PLEASM.FOR ( if the Development system was ordered)
P5000.PLE - P5032.PLE
PALCOM. EXE&PALSETUP. EXE

PLEASM. EXE ·is the executable version of PLEASM. PLEASM.
PLEASM.FOR is the FORTRAN source for the program.
P5000.PLE-P5032.PLE contain the example applications.
PALCOM.EXE is the program used for downloading.
PALSETUP.EXE allows the user to specify communications protocol.

I6onoIIthIcW Memories

A-5

PLEASM on the VAX ii/VMS

DISREGARD THIS MARKED SECTION IF YOU HAVE THE LOAD/GO
SYSTEM II

.........•..... ----_ ... _- ...... _.. _-------_ •.•.........

To create the executable version for the source program you have
to compile and link the source file using any FORTRAN compiler/linker you have at your disposal. The one recommended is
the Supersoft FORTRAN compiler which was used during the
development and testing of this program. For this compiler the sequence of commands to create the executable file would be (with
the compiler/linker in drive B: and the source in drive A:):
A> B:SFOR PLEASM.FOR PLEASM.REL
A> B:CNV PLEASM.REL PLEASM.OBJ/R
A> B: LINK S+SEMU+@PLEASM.RSP,PLEASM,NUL,SFLIB+MLIB"
This creates the executable file PLEASM.EXE.

-._--_._ .. _-----------------_._----*---._--_._--------*
To use PLEASM on the IBM PC, two steps are necessary:
1. Create and edit the PLE Specification File.
2. Run PLEASM.
To run PLEASM with Disk #1 in drive A, type the following when you see
the A> prompt:
A> PLEASM
At this pOint, PLEASM begins running. For step-by-step instructions on
how to use the program, please refer to Chapter 4.

A·6

Monolithic WMemorles

PLEASM on the VAX ii/VMS

General
1. Do NOT terminate the program abnormally by pressing CTRL-C,
CTRL-BREAK, etc. when you are sending the output to a file rather
than the screen. Use instead the QUIT option to terminate your
session. If the session is terminated using CTRL-C, this may result
in lost files on your disk. This is because your output file will not
have been properly closed.
2. The approximate run-times for the programs vary depending on
the size of the PLE and the length of the input specifications file.
Simulation takes between 1 and 3 minutes, while generating
programming formats could take anywhere between 3 and 10
minutes.

IIIIonoIlthlc

Memories

A·7

Monolithic

W Memories

Appendix B: PROM/PLE Programmer Information

DATA 1/0 MODEL 19 PROGRAMMER WITH UNIPAKI
UNIPAK2
Key Features
•
•

Accepts PLE HEX programming format.
Allows user limited communication via RS232 interface to computer development system.

Using the DATA 1/0 Model 19 with UniPakJUnipak2
RS232 Serial Interface
Prior to powering up the DATA I/O it is important that the RS232 interface be connected to the host computer correctly. The correct interface is described below:

Model 19
Gnd
Send
Rec
RSend
CSend
SGnd

1
2

4
5
7

Terminal
1
( )
( )

()
()

Model 19

Gnd
Rec
Send
CSend
RSend
SGnd

With Handshake

Monolithic

Gnd
Send
Rec
SGnd

Terminal

1
2
3

()

1
( )

Gnd
Rec
Send
SGnd

Without Handshake

W Memories

B-1

.... Kum' PLII: programmer Information

Turn on the DATA I/O programmer. After it finishes its self check
routine, type the following key sequence on the DATA 110 keyboard:
<LOAD>
<SELECT>
<D1>
<START>

Select device type

Prepares DATA I/O to receive data via RS232 interface port

The DATA I/O Model 19· is now ready to accept data from the computer
development system. After the file is entered, the data may be
reviewed on the terminal by typing the following on the DATA I/O:
<KEYBOARD>
<ENTER>

Sends data to remote terminal

For additional information please refer to the DATA 1/0 Model 19 users
manual.

B-2

Monolithic

Memories

PROM/PLE Programmer Information

DATA 110 MODEL 29A WITH UNIPAK/UNIPAK2
Key Features
•
•

Accepts PLE HEX programming format.
Allows interactive communication via RS232 interface to computer development system.

Using the DATA 1/0 Model 29A with UniPakJUnipak2
RS232 Serial Interface
Prior to powering up the DATA 1/0 it is important that the RS232 interface be connected to the host computer correctly. The correct interface is described below:

Terminal

Model29A
Gnd
Send
Rec
RSend
CSend
SGnd

1
2
3

1
( )
( )

()
()

4
5
7-

Model29A

Gnd
Rec
Send
CSend
RSend
SGnd

With Handshake

Gnd
Send
Rec
SGnd

1
2
3
7

Terminal

()
()

Gnd
Rec
Send
SGnd

Without Handshake

Turn on the DATA 1/0 programmer. After it finishes its self check
routine. type the following key sequence on the DATA 1/0 keyboard:
<COpy>
<DEVICE>
<RAM>
<FFCC>

Enter family and pin code

Monolithic

!HiD Memories

B·3

~HOMJ'PLI:

Programmer Information

Configure for HEX input format

Prepares DATA 110 to receive data via RS232 interface port

The DATA 110 Model 29A is now ready to accept data from the computer development system. After the file is entered. the data may be
reviewed on the terminal by typing the following on the DATA 110:
<COpy>
<PORT>
<RAM>

Send data to remote terminal

Interactive communication may be achieved by typing on the DATA
110:
<SELECT>

<FB>

Enable output port for interactive communication

For additional information please refer to the DATA 110 Model 29A
users manual.

B-4

Monolith/em Memories

PROM/PLE Programmer Information

DIGELEC MODEL UP-803 WITH FAM 12
Key Features
•
•

Accepts PLE HEX programming format.
Allows limited communication via RS232 interface to computer
development system.

Using the DIGELEC Model UP-803 with FAM 12
RS232 Serial Interface
Prior. to powering up the DIGELEC it is important that the RS232 interface be connected to the host computer correctly. The correct interface is described below:

Model UP-803
~

Gnd

TXD
RXD

2
3
4

RTS
CTS
DSR
SGnd
DTR

Terminal

1
()
()
()

()

RXD
TXD

( ) CTS

'---

Gnd

'""--

RTS
DTR
SGnd
DSR

Insure that the lab
switch is set, the serial
communication switch
setting is used, matching
baud rates are used,
and ASCII HEX format is
specified.

Monolithic W.emorletl

8·5

PROM/PLE Programmer Information

Turn on the DIGELEC programmer.
function of the UP-803 as follows:

Prepare the DATA TRANSFER

SOURCE

SERIAL INPUT

DESTINATION

RAM

DESTINATION INITIAL ADDRESS

XXXX

BLOCK LENGTH

YYYY ( FFFF if unknown )

Press the <EXECUTE> key on the UP-803.
The DIGELEC Model UP-803 is now ready to accept data from the computer development system. After the file is entered, the data may be
reviewed on the remote terminal by selecting the following on the
DIGELEC:
SOURCE

RAM

DESTINATION

SERIAL OUTPUT

Press the <EXECUTE> key on the UP-803.
For additional information on the use of the DIGELEC Model UP-803
please refer to the users manual.

B-6

MonolithIc

MemorIes

PROM/PLE Programmer Information

KONTRON MODEL MPP-80S
Key Features
•

Accepts PLE Intel HEX programming format.

•

Allows limited communication via RS232 interface to computer
development system.

Using the KONTRON Model MPP-80S
RS232 Serial Interface
Prior to powering up the KONTRON it is important that the RS232 interface be connected to the host computer correctly. The correct interface is described below:
Model UP-S03
Gnd
TXD
RXD
SGnd

1
2

Terminal

()
()

Gnd
RXD
TXD
SGnd

The baud rate, parity,
and number of startl
stop bits should be
the same for the
programmer and
terminal.

Turn on the KONTRON programmer. Prepare the DATA TRANSFER
function of the MPP-80S by performing the following:
•

Select proper device type

•

Press the white <IN> key

(Select input port)

•

Press the grey <A> key

(Select port A)

•

Enter <40> for Intel HEX format

•

Press the grey <ENTER> key

Monolithic

W Memories

8-7

PROM/PLE Programmer Information

The KONTRON Model MPP-80S is now ready to accept data from the
computer development system. After the file is entered, the data may
be reviewed on the remote terminal by selecting the following on the
KONTRON:
•

Press the white <OUT> key

(Select output port)

•

Press the grey <A> key

(Select port A)

•

Enter output format desired

•

Press the grey <ENTER> key

For additional information on the use of the KONTRON model MPP-80S
please refer to the users manual.

B-8

Monolithic

W lIIIemorles

Appendix C: PLEASM Error Messages

PLEASM ERROR MESSAGES
PLEASM detects and reports the following errors encountered while
running the program. These include incorrect file naming, syntax errors
in the input specifications file, and errors in simulation.
1. Non-existent filename specified in response to the query for the
name of the source file.
DISK 1/0 ERROR - MAYBE WRONG FILENAME 711
2. Open file named in response to query for the name of the output
file.
DISK 1/0 ERROR - MAYBE WRONG FILENAME 171
3. Input file· size in number of characters exceeds the maximum
dimensions specified in the initialization subroutine.
TOO MANY CHARACTERS IN INPUT FILE
This will probably lead to a run-time error with an output message
appropriate to your system.
4. Keyword FUNCTION TABLE missing in input specifications.
* * * KEYWORD
MINATED

FUNCTION TABLE" MISSING. ASSEMBLY TER-

5. Keyword DESCRIPTION missing in input specifications.
* * * KEYWORD" DESCRIPTION" MISSING. ASSEMBLY TERMINATED

6. Invalid PLE name in line 1 of the input specifications.
PLE PART TYPE PLE$$$$ IS INCORRECT

Monolithic

W Memories

C-1

PLEASM Error Messages

7. Number of pin names specified in the address list exceeds the
number of input pins available in the PLE being used.
• •• TOO MANY PIN NAMES IN INPUT PIN LIST •••
8. Number of pin names specified in the data list exceeds the number
of output pins available in the PLE being used.
* • * TOO MANY PIN NAMES IN OUTPUT PIN LIST * ••

9. A pin name specified in the equations or in the function table pin
list does not match any of the names declared in the address and
data pin lists.
ERROR SYMBOL = $$$$$$$$
10. The "SIMULATE" option has been invoked without a function table
being present in the input specifications.
FUNCTION TABLE MUST BE SUPPLIED IN ORDER TO PERFORM
SIMULATION
11. The number of pin names in the function table pin list exceeds the
number of pins being used in the PLE.
* * * TOO MANY PIN NAMES IN FUNCTION TABLE PIN LIST •• *

12. A symbol other than H(high). L(low). or X(don't care) has been
entered in the function table.
ERROR SYMBOL •• $.. IN LINE $$$ OF FUNCTION TABLE
13. Simulation error caused by an entry in the function table (expected) not agreeing with that evaluated from the Boolean equations (actual).
FUNCTION TABLE ERROR IN LINE $$$ PIN = $$$$$$$$ EXPECTED $
ACTUAL $
The offending line in the function table is then printed out with a
question mark in place of the incorrect entry.

C-2

Monolithic

W Memories

PLEASM Error Messages

14. Overall count of function table errors if there are one or more
simulation errors.
ERRORS IN FUNCTION TABLE = $$$$
15. PLEASM could not generate HEX programming formats for the PLE
being used.
PLEASM DOES NOT SUPPLY HEX PROGRAMMING FORMAT FOR
$$$$ BY $$ PLE DEVICES

Monolithic WNlemories

C-3

Monolithic

W Memories

Appendix D: PLE Design File Library

File
Name

Page
No.

P5000.PLE
P5001.PLE
P5002.PLE
P5003.PLE
P5004.PLE
P5005.PLE
P5006.PLE
P5007.PLE
P5008.PLE
P5009.PLE

4-4
4-6
4-8
4-10
4-12
4-13
4-15
4-18
4-19
4-21

Basic Gates
Memory Address Decoder
6-blt True/Invert and Clear/Set Logic Function
Expandable 3-to-8 Demultiplexer
Dual 2: 1 Multiplexer
Quad 2: 1 Multiplexer with Polarity Control
Hexadecimal to Seven Segment Decoder
5-blt Binary to BCD Converter
4-blt BCD to Gray Code Converter
4-blt Gray Code to BCD Converter

PLE5P8
PLE8P8
PLE8P8
PLE5P8
PLE10P4
PLE10P4
PLE5P8
PLE5P8
PLE5P8
PLE5P8

P5010.PLE
P5011.PLE
P5012.PLE
P5013.PLE
P5014.PLE

4-22
4-24
4-25
4-26
4-29

PLE8P4
PLE8P4
PLE12P4
PLE8P8
PLE11P4

P5015.PLE
P5016.PLE
P5017.PLE
P5018.PLE
P5019.PLE

4-32
N/A
4-53
4-41
4-56

8-blt Priority Encoder
4-blt Magnitude Comparator
6-blt Magnitude Comparator
8-blt Barrel Shifter
4-blt Right Shifter with Programmable
Output Polarity
8-blt Two' s Complement Conversion
Binary to Dual-digit 7 Segment Display Decoder
Arithmetic Logic Unit
4-blt Multiplier Look-up Table
Seven 1-blt Integer Row Partial Products Adder

P5020.PLE
P5021.PLE
P5022.PLE
P5023.PLE
P5024.PLE
P5025.PLE
P5026.PLE

4-57
4-58
4-59
4-42
4-44
4-47
4-50

PLE10P4
PLE12P8
PLE12P8
PLE5P8
PLE5P8
PLE5P8
PLE5P8

P5027.PLE

4-34

P5028.PLE

4-37

P5029.PLE

N/A

Five 2-blt Integer Row Partial Products Adder
Four 3-blt Integer Row Partial Products Adder
Three 4-blt Integer Row Partial Products Adder
Arc Tangent Look-up Table
Hypotenuse of a Right Triangle Look-up Table
Perimeter of a Circle Look-up Table
Period of Oscillation for a Mathematical
Pendulum Look-up Table
A Portion of Timing Generator for PAL Array
Programming
Timing Generator for PAL Security Fuse
Programming
6809 Address Decoder

P5030.PLE

N/A

PLE9P4

P5031.PLE
P5032.PLE

N/A
N/A

4-blt Magnitude Comparator with Polarity
Control
Memory Address Decoder with 16 Chip Enables
4-to-16 Demultiplexer

Title

PLE
Type

PLE8P8
PLE5P8
PLE12P8
PLE8P8
PLE8P4

PLE5P8
PLE5P8
PLE8P4

PLE5P16
PLE6P16

Note 1: Pattern numbers correspond to files found on this disk with
the same name and "PLE" extension (i.e .• P50XX.PLE).
Note 2: Page number references to the section and page number
where the PLE design specification is located in the PLE
Handbook (First Edition).

Monolithio WNlemories

D·1

-.no/"hlc

lIIemories

Appendix E: Help! And Where To Get It

HELP!!
AND WHERE TO GET IT
If you have any questions or problems, help is available from MMI in
Santa Clara, California at the following telephone number:
(408) 970-9700, Extension 6197
When you call, ask for PLEASM Applications Support. Don't forget to
take note of what version of PLEASM you have (Version 1.2H) and
state your question or problem as accurately as possible. PLEASM
Applications Support is also available from our Field Application Engineers. Consult the PLE Handbook or MMI Databook for the telephone
number of your local MMI FAE.
Additional copies of PLEASM can be ordered directly from MMI through
the IdeaLogic" Exchange:
Monolithic Memories, Inc.
IdeaLogic Exchange
Mail Stop 09-07
2175 Mission College Boulevard
Santa Clara, California 95054
(408) 970-9700, Extension 6085

Monolithic W.emorles

Monolithic

Memories

Appendix F: User Customization

Input/Output
Prior to running the program, the user has access to an 1/0 package
which can be used to specify 1/0 unit numbers and array sizes without
having to recompile the program. The variables associated with this
110 routine are explained below ••••
CPG(6000)

Maximum number of characters permitted in the input
specifications file

LLN(250)

Maximum number of lines permitted in the input
specifications file

CLN(250)

Maximum number of characters permitted per line in
the input file

CONINP

The Logical Unit Number for <READ>'s from the console

CONOUT

The Logical Unit Number for <WRITE>'s to the console

FILINP

The Logical Unit Number for <READ>'s from a named
file

FILOUT

The Logical Unit Number for <WRITE>'s to a named file

The Data Set Reference Numbers for INPUT and OUTPUT files are then
assigned as variables at the begining of the program, as follows ...•
INPUT

PLE DESIGN SPECIFICATION

RPD=FILINP

INPUT

OPERATION CODES

ROC=CONINP

OUTPUT ECHO AND TRUTH TABLE

POF=CONOUT

OUTPUT HEX AND BINARY PROGRAMMING
FORMATS

PDF=CONOUTIFILOUT

OUTPUT PROMPTS AND ERROR
MESSAGES

PMS=CONOUTIFILOUT

Monolithic

IFJJI Memories

F-1

User Customization

To perform the customization corresponding to your needs, you need
to have access to the source code which means that you should have
the Development system. These changes can help reduce the memory
requirements and facilitate 1/0.
The dimension of arrays CPG, L.LN, and CLN can be modifed by making
the appropriate changes in the subroutine 10lNIT located at the top of
the source code. This could be done to reduce memory requirements,
since the arrays are statically allocated during compilation.
The logical unit numbers for the console are fixed for any given system
and must be changed accordingly. For example, the logical unit number for reading from the console with VAXIVMS FORTRAN is 5 and for
writing to the console is 6. These numbers are different with Supersoft
FORTRAN used on the IBM-PC.
The logical unit numbers for writing and reading to and from files can
be normally allocated to be between 0 and 19 excluding those reserved
for the console.

Monolithic IFJFJ) Memories

PALASM®Software Bug/Enhancement Report
Name: ____________________ Phone: __________
Company Name:
Address:
City: _ _ _ _ _ _ _ _ _ _ __ State: _ _ _ _ _ _ Zip: _ _ _ _ _ __
Date:-1-1_
Software Version/Revision No.: _____________________
Computer/Operating System:

PAL® Device Programmers: ______________________

Observed Bug (Include Software, Hardware, Documentation):

Suggested Solution/Enhancement: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

1986 Monolithic Memories Inc

PAL® and PALASM@ are registered trademarks of Monolithic Memories.

IIIIII
BUSINESS REPLVMAIL
FIRST CLASS PERMIT NO. 523 Santa Clara 95054-1592
Postage will be paid by addressee

MONOLITHIC MEMORIES INC.
2175 MISSION COLLEGE BLVD.
SANTA CLARA, CA 95054-1592
ATTENTION: PLD Software
MAIL-STOP 10-46

NO POSTAGE
NECESSARY IF
MAILED IN THE
UNITED STATES

Documentation User Response Form
Name: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Date: ---1---1._
Company:

Revision No.: _ _ __

1. On the following scale, please rate the PALASM®2 documentation:
POOR

AVERAGE
4

GOOD

2. What do you like most about the documentation?

3. What do you dislike most about the documentation?

4. Check the items below that you would like included in the next revision:
_
_
_
_
_
_

A simple step-by-step tutorial for the first time user.
A reference section organized alphabetically for the advanced user.
A quick reference card.
An introduction to PAL® devices.
More examples.
More graphics.

5. Please add any suggestions to improve the existing documentation:

1986 Monolithic Memories Inc.

PAL@! and PALASM(I!) are registered trademarks of Monolithic Memories.

IIIIII
BUSINESS REPLV MAIL
FIRST CLASS PERMIT NO. 523 Santa Clara 95054-1592
Postage will be paid by addressee

MONOLITHIC MEMORIES INC.
2175 MISSION COLLEGE BLVD.
SANTA CLARA. CA 95054-1592
ATTENTION: PLD Software
MAIL-STOP 10-46

NO POSTAGE
NECESSARY IF
MAILEO IN THE
UNITED STATES

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