TC29x DS.book

koenigdi

TC290 / TC297 / TC298 / TC299 - Infineon Technologies

TC290 / TC297 / TC298 / TC299 BC-Step Data Sheet 3 V 1.0 2017-03 Revision History Page or Item Subjects (major changes since previous revision) V 1.0, 2017-03

Nov 11, 2011 · TC290 / TC297 / TC298 / TC299 BC-Step Data Sheet 3 V 1.0 2017-03 Revision History Page or Item Subjects (major changes since previous revision) V 1.0, 2017-03

• Google Docs
• Google Drive
• Download [pdf]



File Info : application/pdf, 459 Pages, 5.90MB

Document Document

32-Bit
Microcontroller
TC290 / TC297 / TC298 / TC299
32-Bit Single-Chip Microcontroller BC-Step
32-Bit Single-Chip Microcontroller
Data Sheet
V 1.0, 2017-03
Microcontrollers

Edition 2017-03 Published by Infineon Technologies AG 81726 Munich, Germany © 2017 Infineon Technologies AG All Rights Reserved.
Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party.
Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com)
Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

TC290 / TC297 / TC298 / TC299 BC-Step
Revision History Page or Item Subjects (major changes since previous revision) V 1.0, 2017-03
The history is documented in the last chapter

Data Sheet

3

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Table of Contents

1
2 2.1 2.1.1 2.1.2 2.1.3 2.2 2.2.1 2.2.2 2.2.3 2.3 2.3.1 2.3.2 2.3.3 2.4 2.4.1 2.4.2 2.4.3
3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.13.1 3.14 3.14.1 3.14.2 3.14.3 3.14.4 3.15 3.16 3.17 3.18 3.19 3.20 3.21 3.22 3.23 3.24

Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Package and Pinning Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 TC299x Pin Definition and Functions: BGA516 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
TC299x BGA516 Package Variant Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Emergency Stop Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Pull-Up/Pull-Down Reset Behavior of the Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 TC298x Pin Definition and Functions: BGA416 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 TC298x BGA416 Package Variant Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Emergency Stop Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Pull-Up/Pull-Down Reset Behavior of the Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 TC297x Pin Definition and Functions: BGA292 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 TC297x BGA292 Package Variant Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Emergency Stop Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 Pull-Up/Pull-Down Reset Behavior of the Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 TC29x Bare Die Pad Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 Pad Openings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 Emergency Stop Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 Pull-Up/Pull-Down Reset Behavior of the Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Electrical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 5 V / 3.3 V switchable Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 High performance LVDS Pads (LVDSH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 Medium performance LVDS Pads (LVDSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 VADC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 DSADC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 MHz Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 Back-up Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Calculating the 1.3 V Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
External Supply Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 Single Supply Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 External Supply Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 Single Supply Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 EVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 ERAY Phase Locked Loop (ERAY_PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 JTAG Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 DAP Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 ASCLIN SPI Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 ASCLIN SPI Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 QSPI Timings, Master and Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401

Data Sheet

TOC-1

V 1.0, 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

3.25 3.26 3.27 3.28 3.28.1 3.28.2 3.28.3 3.28.4 3.29 3.30 3.31 3.32 3.32.1 3.32.2 3.32.3 3.32.4 3.33 3.34 3.35 3.35.1 3.35.2 3.36
4 4.1

QSPI Timings, Master and Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406 MSC Timing 5 V Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 MSC Timing 3.3 V Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 Ethernet Interface (ETH) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
ETH Measurement Reference Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 ETH Management Signal Parameters (ETH_MDC, ETH_MDIO) . . . . . . . . . . . . . . . . . . . . . . . . . 424 ETH MII Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 ETH RMII Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 E-Ray Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 HSCT Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 Inter-IC (I2C) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432 EBU Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 BFCLKO Output Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 EBU Asynchronous Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 EBU Burst Mode Access Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 EBU Arbitration Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 CIF Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 Flash Target Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452 TC290 Carrier Tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452 Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 Changes from TC29xBB_v1.1 to TC29xBC_v1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455

Data Sheet

2

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step
Trademarks of Infineon Technologies AG AURIXTM, C166TM, CanPAKTM, CIPOSTM, CIPURSETM, EconoPACKTM, CoolMOSTM, CoolSETTM, CORECONTROLTM, CROSSAVETM, DAVETM, DI-POLTM, EasyPIMTM, EconoBRIDGETM, EconoDUALTM, EconoPIMTM, EconoPACKTM, EiceDRIVERTM, eupecTM, FCOSTM, HITFETTM, HybridPACKTM, I²RFTM, ISOFACETM, IsoPACKTM, MIPAQTM, ModSTACKTM, my-dTM, NovalithICTM, OptiMOSTM, ORIGATM, POWERCODETM; PRIMARIONTM, PrimePACKTM, PrimeSTACKTM, PRO-SILTM, PROFETTM, RASICTM, ReverSaveTM, SatRICTM, SIEGETTM, SINDRIONTM, SIPMOSTM, SmartLEWISTM, SOLID FLASHTM, TEMPFETTM, thinQ!TM, TRENCHSTOPTM, TriCoreTM.
Other Trademarks Advance Design SystemTM (ADS) of Agilent Technologies, AMBATM, ARMTM, MULTI-ICETM, KEILTM, PRIMECELLTM, REALVIEWTM, THUMBTM, µVisionTM of ARM Limited, UK. AUTOSARTM is licensed by AUTOSAR development partnership. BluetoothTM of Bluetooth SIG Inc. CAT-iqTM of DECT Forum. COLOSSUSTM, FirstGPSTM of Trimble Navigation Ltd. EMVTM of EMVCo, LLC (Visa Holdings Inc.). EPCOSTM of Epcos AG. FLEXGOTM of Microsoft Corporation. FlexRayTM is licensed by FlexRay Consortium. HYPERTERMINALTM of Hilgraeve Incorporated. IECTM of Commission Electrotechnique Internationale. IrDATM of Infrared Data Association Corporation. ISOTM of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLABTM of MathWorks, Inc. MAXIMTM of Maxim Integrated Products, Inc. MICROTECTM, NUCLEUSTM of Mentor Graphics Corporation. MIPITM of MIPI Alliance, Inc. MIPSTM of MIPS Technologies, Inc., USA. muRataTM of MURATA MANUFACTURING CO., MICROWAVE OFFICETM (MWO) of Applied Wave Research Inc., OmniVisionTM of OmniVision Technologies, Inc. OpenwaveTM Openwave Systems Inc. RED HATTM Red Hat, Inc. RFMDTM RF Micro Devices, Inc. SIRIUSTM of Sirius Satellite Radio Inc. SOLARISTM of Sun Microsystems, Inc. SPANSIONTM of Spansion LLC Ltd. SymbianTM of Symbian Software Limited. TAIYO YUDENTM of Taiyo Yuden Co. TEAKLITETM of CEVA, Inc. TEKTRONIXTM of Tektronix Inc. TOKOTM of TOKO KABUSHIKI KAISHA TA. UNIXTM of X/Open Company Limited. VERILOGTM, PALLADIUMTM of Cadence Design Systems, Inc. VLYNQTM of Texas Instruments Incorporated. VXWORKSTM, WIND RIVERTM of WIND RIVER SYSTEMS, INC. ZETEXTM of Diodes Zetex Limited. Last Trademarks Update 2011-11-11

Data Sheet

3

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Summary of Features

1

Summary of Features

The TC29x product family has the following features: · High Performance Microcontroller with three CPU cores · Two 32-bit super-scalar TriCore CPUs (TC1.6P), each having the following features:
­ Superior real-time performance ­ Strong bit handling ­ Fully integrated DSP capabilities ­ Multiply-accumulate unit able to sustain 2 MAC operations per cycle ­ up to 300 MHz operation at full temperature range ­ up to 120 / 240 Kbyte Data Scratch-Pad RAM (DSPR) ­ up to 32 Kbyte Instruction Scratch-Pad RAM (PSPR) ­ 16 / 32 Kbyte Instruction Cache (ICACHE) ­ 8 Kbyte Data Cache (DCACHE) · Lockstepped shadow cores for TC1.6P core 1 · Multiple on-chip memories ­ All embedded NVM and SRAM are ECC protected ­ up to 8 Mbyte Program Flash Memory (PFLASH) ­ up to 768 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation ­ 32 Kbyte Memory (LMU) ­ BootROM (BROM) · 128-Channel DMA Controller with safe data transfer · Sophisticated interrupt system (ECC protected) · High performance on-chip bus structure ­ 64-bit Cross Bar Interconnect (SRI) giving fast parallel access between bus masters, CPUs and memories ­ 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units ­ One bus bridge (SFI Bridge) · Safety Management Unit (SMU) handling safety monitor alarms · Memory Test Unit with ECC, Memory Initialization and MBIST functions (MTU) · Hardware I/O Monitor (IOM) for checking of digital I/O · Versatile On-chip Peripheral Units ­ Four Asynchronous/Synchronous Serial Channels (ASCLIN) with hardware LIN support (V1.3, V2.0, V2.1
and J2602) up to 50 MBaud ­ Six Queued SPI Interface Channels (QSPI) with master and slave capability up to 50 Mbit/s ­ High Speed Serial Link (HSSL) for serial inter-processor communication up to 320 Mbit/s ­ Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external power devices ­ Two MultiCAN+ Module with 6 CAN nodes and 384 free assignable message objects for high efficiency
data handling via FIFO buffering and gateway data transfer ­ 15 Single Edge Nibble Transmission (SENT) channels for connection to sensors ­ Up to two FlexRayTM modules with 2 channels (E-Ray) supporting V2.1 ­ One Generic Timer Module (GTM) providing a powerful set of digital signal filtering and timer functionality
to realize autonomous and complex Input/Output management ­ One Capture / Compare 6 module (Two kernels CCU60 and CCU61)

Data Sheet

4

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

­ One General Purpose 12 Timer Unit (GPT120) ­ Five channel Peripheral Sensor Interface conforming to V1.3 (PSI5) ­ Peripheral Sensor Interface with Serial PHY (PSI5-S) ­ Inter-Integrated Circuit Bus Interface (I2C) conforming to V2.1 ­ Optional IEEE802.3 Ethernet MAC with RMII and MII interfaces (ETH) · Versatile Successive Approximation ADC (VADC) ­ Cluster of 11 independent ADC kernels ­ Input voltage range from 0v to 5.5V (ADC supply) · Delta-Sigma ADC (DSADC) ­ Ten channels · Digital programmable I/O ports · On-chip debug support for OCDS Level 1 (CPUs, DMA, On Chip Buses) · Dedicated Emulation Device chip available ­ multi-core debugging, real time tracing, and calibration ­ Aurora Gigabit Trace Port (AGBT) on some variants ­ four/five wire JTAG (IEEE 1149.1) or DAP (Device Access Port) interface · Power Management System and on-chip regulators · Clock Generation Unit with System PLL and Flexray PLL · Embedded Voltage Regulator

Summary of Features

Data Sheet

5

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Summary of Features

Ordering Information The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies: · The derivative itself, i.e. its function set, the temperature range, and the supply voltage · The package and the type of delivery. For the available ordering codes for the TC290 / TC297 / TC298 / TC299 please refer to the "AURIXTM TC2x Data Sheet Addendum", which summarizes all available variants.

Table 1-1 Overview of TC27x Functions

Feature

CPU Core

Type

P Cores / Checker Cores

Max. Freq.

FPU

Program Flash

Size

Data Flash

Size

Cache

Instruction (P / E)

Data (P / E)

SRAM

Size TC1.6P (DSPR/PSPR)

DMA ADC DSADC GTM
Timer STM FlexRay CAN

Size LMU Channels Channels Converter Channels TIM TOM ATOM / MCS CMU / ICM PSM TBU SPE CMP / MON BRC / DPLL GPT12 CCU6 Modules Modules Channels Nodes Message Objects

TC1.6P 3 / 1
300 MHz yes
8 Mbyte 768 Kbyte 16 / 32 / 32 Kbyte
8 Kbyte 120 Kbyte / 32 Kbyte 1) 2)
240Kbyte / 32 Kbyte 240 Kbyte / 32 Kbyte
32 Kbyte 128
72 + 12 11 10 6 5 9 / 6 1 / 1 2 1 4 1 / 1 1 / 1 1 2 3 2 4 6 384

Data Sheet

6

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Summary of Features

Table 1-1 Overview of TC27x Functions (cont'd)

Feature

QSPI

Channels

6

ASCLIN

Interfaces

4

I2C

Interfaces

2

SENT

Channels

15

PSI5

Modules

5

PSI5-S

Modules

1

HSSL

Channels

1

MSC

Channels

3

Ethernet

Channels

1

ASIL

Level

up to ASIL-D

FCE

Modules

1

Safety support

SMU

1

IOM

1

Security

HSM

1

ADAS

Yes

Embedded Voltage Regulator DCDC from 5 V / 3.3 V to 1.3 V

Yes

Embedded Voltage Regulator LDO from 5 V / 3.3 V to 1.3 V

Yes

Embedded Voltage Regulator LDO from 5 V to 3.3 V

Yes

Low Power Feature Packages
I/O

Standby RAM Type
Type

Yes
LF-BGA-292-6 / PG-BGA-41626 / PG-LFBGA-516-5
5 V CMOS / 3.3 V CMOS / LVDS

Tambient

Range

-40 ... +125°C

1) Address range starts at lowest address defined in the User's Manual. For reference see the Memory Maps chapter of the User's Manual.

2) To ensure the processor cores are provided with a constant stream of instructions the Instruction Fetch Units will speculatively fetch instructions from the up to 64 bytes ahead of the current PC. If the current PC is within 64 bytes of the top of an instruction memory the Instruction Fetch Unit may attempt to speculatively fetch instruction from beyond the physical range. This may then lead to error conditions and alarms being triggered by the bus and memory systems. It is therefore recommended that the upper 64 bytes of any memory be unused for instruction storage.

Data Sheet

7

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning Definitions

2

Package and Pinning Definitions

This chapter gives a pinning of the different packages of the TC290 / TC297 / TC298 / TC299.

Data Sheet

TOC-8

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

2.1

TC299x Pin Definition and Functions: BGA516

Figure 2-1 is showing the TC299x Logic Symbol for the package variant: BGA516.

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8

7

6

54321

AK VSS VFLEXE P30.15 P30.13 P30.11 P30.9 P30.7 P30.5 P30.3 P30.1 VFLEXE P31.15 P31.13 P31.11 P31.9 P31.7 P31.5 P31.3 P31.1 VFLEXE VSS VDDM VSSM AN48 AN51 AN53 AN55 NC

NC

NC AK

AJ VEXT VSS P30.14 P30.12 P30.10 P30.8 P30.6 P30.4 P30.2 P30.0 VGATE3P P31.14 P31.12 P31.10 P31.8 P31.6 P31.4 P31.2 P31.0 VFLEXE VSS VDDM VSSM AN49 AN50 AN52 AN54 NC

NC

NC AJ

AH VEBU VEXT AG P25.0 P26.0

Top-View

NC NC AH NC NC AG

AF P25.1 P25.2

25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8

7

6

AN57 AN56 AF

AE P25.3 P25.4

AE VSS P32.3 P32.2 P32.0 P33.13 P33.11 P33.9 P33.7 P33.5 P33.3 P33.1 AN5 AN10 VAGND1 VAREF1 VDDM VSSM AN20 AN21

NC

AE

AN58 AN59 AE

AD P25.5 P25.7

AD VEXT VSS P32.4 VGATE1P P33.12 P33.10 P33.8 P33.6 P33.4 P33.2 P33.0 AN2 AN8 AN11 AN13 AN16 AN18 AN19 AN24 AN25 AD

AN61 AN60 AD

AC P25.9 P25.8

AC P23.0 VEXT

22 21 20 19 18 17 16 15 14 13 12 11 10 9

AN26 AN27 AC

AN62 AN63 AC

AB P25.11 P25.10

AB P23.2 P23.1 AB

VSS P32.7 P32.6 P33.15 P34.5 P34.3 P34.1 AN1 AN3 AN7

AN9 AN14 AN17 NC

AB AN28 AN29 AB

AN64 AN65 AB

AA P25.13 P25.12

AA P23.4 P23.3 AA P23.5 VSS P32.5 P33.14 P34.4 P34.2 VEVRSB AN0 AN4 AN6 AN12 AN15 AN22 AN30 AA VAGND2 VAREF2 AA

AN66 AN67 AA

Y P25.15 P25.14 W NC P25.6 V NC NC

Y P22.2 P22.3 Y P23.6 P23.7

19 18 17 16 15 14 13 12

AN23 AN31

Y

AN35 AN33

Y

W P22.0 P22.1 W P22.5 P22.4

W

VDD

VSS VSS VSS (AGBT (AGBT VSS
TX0P) TX0N)

VDD

W AN34 AN32 W AN37 AN39 W

V VDDP3 VDD V P22.7 P22.6

V

VDD

VSS VSS VSS VSS

VDD

V AN38 AN36

V

AN45 AN44

V

AN69 AN68 Y AN71 AN70 W NC NC V

U P24.1 P24.0 T P24.3 P24.2 R P24.5 P24.4 P P24.7 P24.6 N P24.9 P24.8 M P24.11 P24.10 L P24.13 P24.12

U XTAL1 XTAL2 U P22.9 P22.8

T

VSS TRST T P22.11 P22.10

R P21.4 P21.2 R P21.0 TMS

P P21.5 P21.3 P P21.1 TCK

N P20.0 P20.2 N P21.6 P21.7

M P20.3 P20.1 M PORST ESR1

L P20.8 P20.7 L

P20.6 ESR0

U

VSS VSS

VSS

VSS

T

(AGBT VSS VSS VSS

ERR)

NC
R (VDDPSB VSS VSS VSS
)

P

VSS VSS

VSS

VSS VSS VSS VSS VSS VSS

VSS VSS
VSS VSS (AGBT
CLKN) VSS VSS (AGBT CLKP)
VSS VSS

U

AN40 AN41 U

AN47 AN46

U

T AN42 AN43 T P00.12 P00.11 T

R P00.10 P00.8 R P00.9 P00.7 R

P P01.7 P00.6

P

P00.5 P00.4

P

N

VDD

VSS VSS VSS VSS

VDD (VDDSB)

N

P01.5 P01.6

N

P00.3 P00.2

N

M

VDD VSS

VSS

VSS

VSS

VDD (VDDSB)

M P01.3 P01.4 M P00.1 P00.0 M

19 18 17 16 15 14 13 12

P02.10 P02.11 L

P02.7 P02.8

L

P00.14 P00.15 U P00.13 NC T
NC NC R P01.14 P01.15 P P01.12 P01.13 N P01.10 P01.11 M P01.9 P01.8 L

K P24.15 P24.14

K P20.11 P20.10 K

P20.9 VSS VDDFL3 P15.5 P14.2 P12.0 P12.1 P11.0 P11.1 P11.7 P11.8 P11.13 VSS P02.9 K

P02.5 P02.6

K

P01.2 P01.1 K

J VEBU VEBU

J P20.13 P20.12 J

VSS VDDFL3 P15.7 P15.8 P14.7 P14.9 P14.10 P11.4 P11.6 P11.5 P11.14 P11.15 VFLEX VSS

J

P02.3 P02.4

J

P01.0 NC J

H VSS VSS

H P20.14 P15.2

22 21 20 19 18 17 16 15 14 13 12 11 10 9

P02.1 P02.2 H

NC NC H

G NC NC

G P15.0 VSS VDDP3 P15.3 P14.0 P14.4 P14.3 P14.6 P13.0 P13.2 P11.3 P11.10 P11.12 P10.1 P10.4 P10.5 P10.8 VEXT VSS P02.0

G

P02.14 P02.15 G

F NC NC

F

VSS VDDP3 P15.1 P15.4 P15.6 P14.1 P14.5 P14.8 P13.1 P13.3 P11.2 P11.9 P11.11 P10.0 P10.3 P10.2 P10.6 P10.7 VEXT

NC

F

P02.12 P02.13 F

E NC NC

25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8

7

6

NC NC E

D NC NC

NC NC D

C NC NC

NC NC C

B VSS VSS VDDP3 NC NC NC P15.10 P15.12 P15.14 NC

NC P14.12 P14.14 NC P13.4 P13.6 NC P13.10 P13.12 P13.14 NC NC P10.9 P10.10 NC P10.14 NC VEXT VSS NC B

A VSS VDDP3 NC

NC

NC

NC P15.11 P15.13 P15.15 NC P14.11 P14.13 P14.15 NC P13.5 P13.7 P13.9 P13.11 P13.13 P13.15 NC

NC

NC P10.11 P10.13 P10.15 NC

NC VEXT NC A

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8

7

6

54321

Figure 2-1 TC299x Logic Symbol for the package variant BGA516.

Data Sheet

TOC-9

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

2.1.1

Package and Pinning DefinitionsTC299x Pin Definition and Functions:
TC299x BGA516 Package Variant Pin Configuration

Table 2-1 Port 00 Functions

Pin

Symbol

M6

P00.0

TIN9

CTRAPA

T12HRE

INJ00

CIFD9

P00.0

TOUT9

ASCLK3

ATX3

­

TXDCAN1

­

COUT63

ETHMDIOA

Ctrl Type

I

MP /

PU1 /

VEXT

O0 O1 O2 O3 O4 O5 O6 O7 HWOU T

Function General-purpose input GTM input CCU61 input CCU60 input MSC0 input CIF input General-purpose output GTM output ASCLIN3 output ASCLIN3 output Reserved CAN node 1 output Reserved CCU60 output ETH input/output

Data Sheet

TOC-10

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-1 Port 00 Functions (cont'd)

Pin

Symbol

Ctrl

M7

P00.1

I

TIN10

ARX3E

RXDCAN1D

PSIRX0A

SENT0B

CC60INB

CC60INA

DSCIN5A

DS5NA

DSCIN7B

VADCG7.5

CIFD10

P00.1

O0

TOUT10

O1

ATX3

O2

­

O3

DSCOUT5

O4

DSCOUT7

O5

SPC0

O6

CC60

O7

N6

P00.2

I

TIN11

SENT1B

DSDIN5A

DSDIN7B

DS5PA

VADCG7.4

CIFD11

P00.2

O0

TOUT11

O1

ASCLK3

O2

TXDCANr1

O3

PSITX0

O4

TXDCAN3

O5

SLSO34

O6

COUT60

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input ASCLIN3 input CAN node 1 input PSI5 input SENT input CCU60 input CCU61 input DSADC channel 5 input DSADC positive analog input of channel channel 5, pin A DSADC channel 7 input VADC analog input channel 5 of group 7 CIF input General-purpose output GTM output ASCLIN3 output Reserved DSADC channel 5 output DSADC channel 7 output SENT output CCU61 output General-purpose input GTM input SENT input DSADC channel 5 input DSADC channel 7 input DSADC negative analog input of channel 5, pin A VADC analog input channel 4 of group 7 CIF input General-purpose output GTM output ASCLIN3 output CAN node 1 output (MultiCANr+) PSI5 output CAN node 3 output QSPI3 output CCU61 output

Data Sheet

TOC-11

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-1 Port 00 Functions (cont'd)

Pin

Symbol

Ctrl

N7

P00.3

I

TIN12

RXDCAN3A

RXDCANr1A

PSIRX1A

PSISRXA

SENT2B

CC61INB

CC61INA

DSCIN3A

VADCG7.3

DSITR5F

CIFD12

P00.3

O0

TOUT12

O1

ASLSO3

O2

­

O3

DSCOUT3

O4

­

O5

SPC2

O6

CC61

O7

P6

P00.4

I

TIN13

REQ7

SENT3B

DSDIN3A

DSSGNA

VADCG7.2

CIFD13

P00.4

O0

TOUT13

O1

PSISTX

O2

­

O3

PSITX1

O4

VADCG4BFL0

O5

SPC3

O6

COUT61

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input CAN node 3 input CAN node 1 input (MultiCANr+) PSI5 input PSI5-S input SENT input CCU60 input CCU61 input DSADC channel 3 input VADC analog input channel 3 of group 7 DSADC channel 5 input CIF input General-purpose output GTM output ASCLIN3 output Reserved DSADC channel 3 output Reserved SENT output CCU61 output General-purpose input GTM input SCU input SENT input DSADC channel 3 input DSADC channel input VADC analog input channel 2 of group 7 CIF input General-purpose output GTM output PSI5-S output Reserved PSI5 output VADC output SENT output CCU61 output

Data Sheet

TOC-12

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-1 Port 00 Functions (cont'd)

Pin

Symbol

Ctrl

P7

P00.5

I

TIN14

PSIRX2A

SENT4B

CC62INB

CC62INA

DSCIN2A

VADCG7.1

CIFD14

P00.5

O0

TOUT14

O1

DSCGPWMN

O2

SLSO33

O3

DSCOUT2

O4

VADCG4BFL1

O5

SPC4

O6

CC62

O7

P9

P00.6

I

TIN15

SENT5B

DSDIN2A

VADCG7.0

DSITR4F

CIFD15

P00.6

O0

TOUT15

O1

DSCGPWMP

O2

VADCG4BFL2

O3

PSITX2

O4

VADCEMUX10

O5

SPC5

O6

COUT62

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input PSI5 input SENT input CCU60 input CCU61 input DSADC channel 2 input VADC analog input channel 1 of group 7 CIF input General-purpose output GTM output DSADC output QSPI3 output DSADC channel 2 output VADC output SENT output CCU61 output General-purpose input GTM input SENT input DSADC channel 2 input A VADC analog input channel 0 of group 7 (with pull down diagnostics) DSADC channel 4 input F CIF input General-purpose output GTM output DSADC output VADC output PSI5 output VADC output SENT output CCU61 output

Data Sheet

TOC-13

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-1 Port 00 Functions (cont'd)

Pin

Symbol

Ctrl

R6

P00.7

I

TIN16

SENT6B

CC60INC

CCPOS0A

T12HRB

T2INA

DSCIN4A

DS4NA

VADCG6.5

CIFCLK

P00.7

O0

TOUT16

O1

­

O2

VADCG4BFL3

O3

DSCOUT4

O4

VADCEMUX11

O5

SPC6

O6

CC60

O7

R9

P00.8

I

TIN17

SENT7B

CC61INC

CCPOS1A

T13HRB

T2EUDA

DSDIN4A

DS4PA

VADCG6.4

CIFVSNC

P00.8

O0

TOUT17

O1

SLSO36

O2

­

O3

­

O4

VADCEMUX12

O5

SPC7

O6

CC61

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input SENT input CCU61 input CCU61 input CCU60 input GPT120 input DSADC channel 4 input A DSADC negative analog input channel 4, pin A VADC analog input channel 5 of group 6 CIF input General-purpose output GTM output Reserved VADC output DSADC channel 4 output VADC output SENT output CCU61 output General-purpose input GTM input SENT input CCU61 input CCU61 input CCU60 input GPT120 input DSADC channel 4 input A DSADC positive analog input of channel 4, pin A VADC analog input channel 4 of group 6 CIF input General-purpose output GTM output QSPI3 output Reserved Reserved VADC output SENT output CCU61 output

Data Sheet

TOC-14

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-1 Port 00 Functions (cont'd)

Pin

Symbol

Ctrl

R7

P00.9

I

TIN18

SENT8B

CC62INC

CCPOS2A

T13HRC

T12HRC

T4EUDA

DSCIN1A

VADCG6.3

DSITR3F

CIFHSNC

P00.9

O0

TOUT18

O1

SLSO37

O2

ARTS3

O3

DSCOUT1

O4

­

O5

SPC8

O6

CC62

O7

R10

P00.10

I

TIN19

SENT9B

DSDIN1A

VADCG6.2

P00.10

O0

TOUT19

O1

­

O2

­

O3

­

O4

­

O5

SPC9

O6

COUT63

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input SENT input CCU61 input CCU61 input CCU60 input CCU60 input GPT120 input DSADC channel 1 input A VADC analog input channel 3 of group 6 DSADC channel 3 input F CIF input General-purpose output GTM output QSPI3 output ASCLIN3 output DSADC channel 1 output Reserved SENT output CCU61 output General-purpose input GTM input SENT input DSADC channel 1 input A VADC analog input channel 2 of group 6 General-purpose output GTM output Reserved Reserved Reserved Reserved SENT output CCU61 output

Data Sheet

TOC-15

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-1 Port 00 Functions (cont'd)

Pin

Symbol

Ctrl

T6

P00.11

I

TIN20

CTRAPA

T12HRE

DSCIN0A

VADCG6.1

P00.11

O0

TOUT20

O1

­

O2

­

O3

DSCOUT0

O4

­

O5

­

O6

­

O7

T7

P00.12

I

TIN21

ACTS3A

DSDIN0A

VADCG6.0

P00.12

O0

TOUT21

O1

­

O2

­

O3

­

O4

­

O5

­

O6

COUT63

O7

T2

P00.13

I

TIN167

DSDIN6A

P00.13

O0

TOUT167

O1

­

O2

­

O3

EXTCLK1

O4

­

O5

­

O6

­

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT
MP+ / PU1 / VEXT

Function General-purpose input GTM input CCU60 input CCU61 input DSADC channel 0 input A VADC analog input channel 1 of group 6 General-purpose output GTM output Reserved Reserved DSADC channel 0 output Reserved Reserved Reserved General-purpose input GTM input ASCLIN3 input DSADC channel 0 input A VADC analog input channel 0 of group 6 General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved CCU61 output General-purpose input GTM input DSADC channel 6 input A General-purpose output GTM output Reserved Reserved SCU output Reserved Reserved Reserved

Data Sheet

TOC-16

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-1 Port 00 Functions (cont'd)

Pin

Symbol

Ctrl

U2

P00.14

I

TIN166

DSCIN6A

P00.14

O0

TOUT166

O1

­

O2

­

O3

DSCOUT6

O4

­

O5

­

O6

­

O7

U1

P00.15

I

TIN168

DSITR6F

P00.15

O0

TOUT168

O1

­

O2

­

O3

EXTCLK0

O4

­

O5

­

O6

­

O7

Type LP / PU1 / VEXT
MP+ / PU1 / VEXT

Function General-purpose input GTM input DSADC channel 6 input A General-purpose output GTM output Reserved Reserved DSADC channel 6 output Reserved Reserved Reserved General-purpose input GTM input DSADC channel 6 input F General-purpose output GTM output Reserved Reserved SCU output Reserved Reserved Reserved

Table 2-2 Port 01 Functions

Pin

Symbol

J2

P01.0

TIN155

DSITR6E

RXDCAN3F

RXDCANr1E

P01.0

TOUT155

­

­

­

­

­

­

Ctrl Type Function

I

LP /

General-purpose input

PU1 / VEXT

GTM input DSADC channel 6 input E

CAN node 3 input

CAN node 1 input (MultiCANr+)

O0

General-purpose output

O1

GTM output

O2

Reserved

O3

Reserved

O4

Reserved

O5

Reserved

O6

Reserved

O7

Reserved

Data Sheet

TOC-17

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-2 Port 01 Functions (cont'd)

Pin

Symbol

Ctrl

K1

P01.1

I

TIN159

DSITR8E

RXD1A1

SENT10B

P01.1

O0

TOUT159

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

K2

P01.2

I

TIN156

DSCIN7A

P01.2

O0

TOUT156

O1

­

O2

TXDCAN3

O3

­

O4

TXDCANr1

O5

DSCOUT7

O6

­

O7

M10

P01.3

I

TIN111

SLSI3B

DSITR7F

P01.3

O0

TOUT111

O1

­

O2

­

O3

SLSO39

O4

TXDCAN1

O5

­

O6

­

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input DSADC channel 8 input E ERAY1 input SENT input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved General-purpose input GTM input DSADC channel 7 input A General-purpose output GTM output Reserved CAN node 3 output Reserved CAN node 1 output (MultiCANr+) DSADC channel 7 output Reserved General-purpose input GTM input QSPI3 input DSADC channel 7 input F General-purpose output GTM output Reserved Reserved QSPI3 output CAN node 1 output Reserved Reserved

Data Sheet

TOC-18

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-2 Port 01 Functions (cont'd)

Pin

Symbol

Ctrl

M9

P01.4

I

TIN112

RXDCAN1C

DSITR7E

P01.4

O0

TOUT112

O1

­

O2

­

O3

SLSO310

O4

­

O5

­

O6

­

O7

N10

P01.5

I

TIN113

MRST3C

DSCIN8A

P01.5

O0

TOUT113

O1

­

O2

­

O3

MRST3

O4

­

O5

DSCOUT8

O6

­

O7

N9

P01.6

I

TIN114

MTSR3C

DSDIN8A

P01.6

O0

TOUT114

O1

­

O2

­

O3

MTSR3

O4

­

O5

­

O6

­

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT
MP / PU1 / VEXT

Function General-purpose input GTM input CAN node 1 input DSADC channel 7 input E General-purpose output GTM output Reserved Reserved QSPI3 output Reserved Reserved Reserved General-purpose input GTM input QSPI3 input DSADC channel 8 input A General-purpose output GTM output Reserved Reserved QSPI3 output Reserved DSADC channel 8 output Reserved General-purpose input GTM input QSPI3 input DSADC channel 8 input A General-purpose output GTM output Reserved Reserved QSPI3 output Reserved Reserved Reserved

Data Sheet

TOC-19

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-2 Port 01 Functions (cont'd)

Pin

Symbol

Ctrl

P10

P01.7

I

TIN115

SCLK3C

DSITR8F

P01.7

O0

TOUT115

O1

­

O2

­

O3

SCLK3

O4

­

O5

­

O6

­

O7

L1

P01.8

I

TIN162

DSDIN9A

SENT12B

ARX0C

RXDCAN0F

RXDCANr0E

RXD1B1

P01.8

O0

TOUT162

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

Type MP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input QSPI3 input DSADC channel 8 input F General-purpose output GTM output Reserved Reserved QSPI3 output Reserved Reserved Reserved General-purpose input GTM input DSADC channel 9 input A SENT input ASCLIN0 input CAN node 0 input CAN node 0 input (MultiCANr+) ERAY1 input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved

Data Sheet

TOC-20

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-2 Port 01 Functions (cont'd)

Pin

Symbol

Ctrl

L2

P01.9

I

TIN160

DSCIN9A

SENT11B

P01.9

O0

TOUT160

O1

­

O2

­

O3

­

O4

­

O5

DSCOUT9

O6

­

O7

M2

P01.10

I

TIN163

DSITR9F

SENT13B

P01.10

O0

TOUT163

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

M1

P01.11

I

TIN165

DSITR9E

SENT14B

P01.11

O0

TOUT165

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input DSADC channel 9 input A SENT input General-purpose output GTM output Reserved Reserved Reserved Reserved DSADC channel 9 output Reserved General-purpose input GTM input DSADC channel 9 input F SENT input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved General-purpose input GTM input DSADC channel 9 input E SENT input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved

Data Sheet

TOC-21

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-2 Port 01 Functions (cont'd)

Pin

Symbol

Ctrl

N2

P01.12

I

TIN158

P01.12

O0

TOUT158

O1

­

O2

­

O3

­

O4

­

O5

TXD1A

O6

­

O7

N1

P01.13

I

TIN161

P01.13

O0

TOUT161

O1

ATX0

O2

­

O3

TXDCAN0

O4

TXDCANr0

O5

TXD1B

O6

­

O7

P2

P01.14

I

TIN164

P01.14

O0

TOUT164

O1

­

O2

­

O3

­

O4

­

O5

TXEN1A

O6

­

O7

Type MP+ / PU1 / VEXT
MP+ / PU1 / VEXT
MP+ / PU1 / VEXT

Function General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved ERAY1 output Reserved General-purpose input GTM input General-purpose output GTM output ASCLIN0 output Reserved CAN node 0 output CAN node 0 output (MultiCANr+) ERAY1 output Reserved General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved ERAY1 output Reserved

Data Sheet

TOC-22

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-2 Port 01 Functions (cont'd)

Pin

Symbol

Ctrl

P1

P01.15

I

TIN157

DSDIN7A

P01.15

O0

TOUT157

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

Type
LP / PU1 / VEXT

Function General-purpose input GTM input DSADC channel 7 input A General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved

Table 2-3 Port 02 Functions

Pin

Symbol

G6

P02.0

TIN0

REQ6

ARX2G

CC60INA

CC60INB

CIFD0

P02.0

TOUT0

ATX2

SLSO31

DSCGPWMN

TXDCAN0

TXD0A

CC60

Ctrl Type Function

I

MP+ / General-purpose input

PU1 / VEXT

GTM input SCU input

ASCLIN2 input

CCU60 input

CCU61 input

CIF input

O0

General-purpose output

O1

GTM output

O2

ASCLIN2 output

O3

QSPI3 output

O4

DSADC output

O5

CAN node 0 output

O6

ERAY0 output

O7

CCU60 output

Data Sheet

TOC-23

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-3 Port 02 Functions (cont'd)

Pin

Symbol

Ctrl

H7

P02.1

I

TIN1

REQ14

ARX2B

RXDCAN0A

RXD0A2

CIFD1

P02.1

O0

TOUT1

O1

SLSO47

O2

SLSO32

O3

DSCGPWMP

O4

­

O5

­

O6

COUT60

O7

H6

P02.2

I

TIN2

CC61INA

CC61INB

CIFD2

P02.2

O0

TOUT2

O1

ATX1

O2

SLSO33

O3

PSITX0

O4

TXDCAN2

O5

TXD0B

O6

CC61

O7

Type Function

LP / PU1 General-purpose input / VEXT GTM input

SCU input

ASCLIN2 input

CAN node 0 input

ERAY0 input

CIF input

General-purpose output

GTM output

QSPI4 output

QSPI3 output

DSADC output

Reserved

Reserved

CCU60 output

MP+ / PU1 / VEXT

General-purpose input GTM input CCU60 input

CCU61 input

CIF input

General-purpose output

GTM output

ASCLIN1 output

QSPI3 output

PSI5 output

CAN node 2 output

ERAY0 output

CCU60 output

Data Sheet

TOC-24

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-3 Port 02 Functions (cont'd)

Pin

Symbol

Ctrl

J7

P02.3

I

TIN3

ARX1G

RXDCAN2B

RXD0B2

PSIRX0B

DSCIN5B

SDI11

CIFD3

P02.3

O0

TOUT3

O1

ASLSO2

O2

SLSO34

O3

DSCOUT5

O4

­

O5

­

O6

COUT61

O7

J6

P02.4

I

TIN4

SLSI3A

ECTT1

RXDCAN0D

CC62INA

CC62INB

DSDIN5B

SDA0A

CIFD4

P02.4

O0

TOUT4

O1

ASCLK2

O2

SLSO30

O3

PSISCLK

O4

SDA0

O5

TXEN0A

O6

CC62

O7

Type LP / PU1 / VEXT
MP+ / PU1 / VEXT

Function General-purpose input GTM input ASCLIN1 input CAN node 2 input ERAY0 input PSI5 input DSADC channel 5 input B MSC1 input CIF input General-purpose output GTM output ASCLIN2 output QSPI3 output DSADC channel 5 output Reserved Reserved CCU60 output General-purpose input GTM input QSPI3 input TTCAN input CAN node 0 input CCU60 input CCU61 input DSADC channel 5 input B I2C0 input CIF input General-purpose output GTM output ASCLIN2 output QSPI3 output PSI5-S output I2C0 output ERAY0 output CCU60 output

Data Sheet

TOC-25

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-3 Port 02 Functions (cont'd)

Pin

Symbol

Ctrl

K7

P02.5

I

TIN5

MRST3A

ECTT2

PSIRX1B

PSISRXB

SENT3C

DSCIN4B

SCL0A

CIFD5

P02.5

O0

TOUT5

O1

TXDCAN0

O2

MRST3

O3

DSCOUT4

O4

SCL0

O5

TXEN0B

O6

COUT62

O7

K6

P02.6

I

TIN6

MTSR3A

SENT2C

CC60INC

CCPOS0A

T12HRB

T3INA

CIFD6

DSDIN4B

DSITR5E

P02.6

O0

TOUT6

O1

PSISTX

O2

MTSR3

O3

PSITX1

O4

VADCEMUX00

O5

­

O6

CC60

O7

Type MP+ / PU1 / VEXT
MP / PU1 / VEXT

Function General-purpose input GTM input QSPI3 input TTCAN input PSI5 input PSI5-S input SENT input DSADC channel 4 input B I2C0 input CIF input General-purpose output GTM output CAN node 0 output QSPI3 output DSADC channel 4 output I2C0 output ERAY0 output CCU60 output General-purpose input GTM input QSPI3 input SENT input CCU60 input CCU60 input CCU61 input GPT120 input CIF input DSADC channel 4 input B DSADC channel 5 input E General-purpose output GTM output PSI5-S output QSPI3 output PSI5 output VADC output Reserved CCU60 output

Data Sheet

TOC-26

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-3 Port 02 Functions (cont'd)

Pin

Symbol

Ctrl

L7

P02.7

I

TIN7

SCLK3A

PSIRX2B

SENT1C

CC61INC

CCPOS1A

T13HRB

T3EUDA

CIFD7

DSCIN3B

DSITR4E

P02.7

O0

TOUT7

O1

­

O2

SCLK3

O3

DSCOUT3

O4

VADCEMUX01

O5

SPC1

O6

CC61

O7

Type
MP / PU1 / VEXT

Function General-purpose input GTM input QSPI3 input PSI5 input SENT input CCU60 input CCU60 input CCU61 input GPT120 input CIF input DSADC channel 3 input B DSADC channel 4 input E General-purpose output GTM output Reserved QSPI3 output DSADC channel 3 output VADC output SENT output CCU60 output

Data Sheet

TOC-27

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-3 Port 02 Functions (cont'd)

Pin

Symbol

Ctrl

L6

P02.8

I

TIN8

SENT0C

CC62INC

CCPOS2A

T12HRC

T13HRC

T4INA

CIFD8

DSDIN3B

DSITR3E

P02.8

O0

TOUT8

O1

SLSO35

O2

­

O3

PSITX2

O4

VADCEMUX02

O5

ETHMDC

O6

CC62

O7

K9

P02.9

I

TIN116

P02.9

O0

TOUT116

O1

ATX2

O2

­

O3

­

O4

TXDCAN1

O5

­

O6

­

O7

Type Function

LP / PU1 General-purpose input

/ VEXT

GTM input SENT input

CCU60 input

CCU60 input

CCU61 input

CCU61 input

GPT120 input

CIF input

DSADC channel 3 input B

DSADC channel 3 input E

General-purpose output

GTM output

QSPI3 output

Reserved

PSI5 output

VADC output

ETH output

CCU60 output

LP / PU1 / VEXT

General-purpose input GTM input General-purpose output

GTM output

ASCLIN2 output

Reserved

Reserved

CAN node 1 output

Reserved

Reserved

Data Sheet

TOC-28

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-3 Port 02 Functions (cont'd)

Pin

Symbol

Ctrl

L10

P02.10

I

TIN117

ARX2C

RXDCAN1E

P02.10

O0

TOUT117

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

L9

P02.11

I

TIN118

P02.11

O0

TOUT118

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

F2

P02.12

I

TIN151

P02.12

O0

TOUT151

O1

SLSO35

O2

SLSO44

O3

­

O4

­

O5

­

O6

­

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input ASCLIN2 input CAN node 1 input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved General-purpose input GTM input General-purpose output GTM output QSPI3 output QSPI4 output Reserved Reserved Reserved Reserved

Data Sheet

TOC-29

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-3 Port 02 Functions (cont'd)

Pin

Symbol

Ctrl

F1

P02.13

I

TIN153

P02.13

O0

TOUT153

O1

SLSO37

O2

SLSO46

O3

TXDCAN0

O4

TXDCANr0

O5

­

O6

­

O7

G2

P02.14

I

TIN154

RXDCAN0H

RXDCANr0D

P02.14

O0

TOUT154

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

G1

P02.15

I

TIN152

P02.15

O0

TOUT152

O1

SLSO36

O2

SLSO45

O3

­

O4

­

O5

TXEN1B

O6

­

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT
MP+ / PU1 / VEXT

Function General-purpose input GTM input General-purpose output GTM output QSPI3 output QSPI4 output CAN node 0 output CAN node 0 output (MultiCANr+) Reserved Reserved General-purpose input GTM input CAN node 0 input CAN node 0 input (MultiCANr+) General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved General-purpose input GTM input General-purpose output GTM output QSPI3 output QSPI4 output Reserved Reserved ERAY1 output Reserved

Data Sheet

TOC-30

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-4 Port 10 Functions

Pin

Symbol

F12

P10.0

TIN102

T6EUDB

P10.0

TOUT102

­

SLSO110

­

VADCG6BFL0

­

­

G12

P10.1

TIN103

MRST1A

T5EUDB

P10.1

TOUT103

MTSR1

MRST1

EN01

VADCG6BFL1

END03

­

F10

P10.2

TIN104

SCLK1A

T6INB

REQ2

RXDCAN2E

SDI01

P10.2

TOUT104

­

SCLK1

EN00

VADCG6BFL2

END02

­

Data Sheet

Ctrl Type

Function

I

LP /

General-purpose input

PU1 / VEXT

GTM input GPT120 input

O0

General-purpose output

O1

GTM output

O2

Reserved

O3

QSPI1 output

O4

Reserved

O5

VADC output

O6

Reserved

O7

Reserved

I

MP+ / General-purpose input

PU1 / VEXT

GTM input QSPI1 input

GPT120 input

O0

General-purpose output

O1

GTM output

O2

QSPI1 output

O3

QSPI1 output

O4

MSC0 output

O5

VADC output

O6

MSC0 output

O7

Reserved

I

MP /

General-purpose input

PU1 / VEXT

GTM input QSPI1 input

GPT120 input

SCU input

CAN node 2 input

MSC0 input

O0

General-purpose output

O1

GTM output

O2

Reserved

O3

QSPI1 output

O4

MSC0 output

O5

VADC output

O6

MSC0 output

O7

Reserved

TOC-31

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-4 Port 10 Functions (cont'd)

Pin

Symbol

Ctrl

F11

P10.3

I

TIN105

MTSR1A

REQ3

T5INB

P10.3

O0

TOUT105

O1

VADCG6BFL3

O2

MTSR1

O3

EN00

O4

END02

O5

TXDCAN2

O6

­

O7

G11

P10.4

I

TIN106

MTSR1C

CCPOS0C

T3INB

P10.4

O0

TOUT106

O1

­

O2

SLSO18

O3

MTSR1

O4

EN00

O5

END02

O6

­

O7

Type MP / PU1 / VEXT
MP+ / PU1 / VEXT

Function General-purpose input GTM input QSPI1 input SCU input GPT120 input General-purpose output GTM output VADC output QSPI1 output MSC0 output MSC0 output CAN node 2 output Reserved General-purpose input GTM input QSPI1 input CCU60 input GPT120 input General-purpose output GTM output Reserved QSPI1 output QSPI1 output MSC0 output MSC0 output Reserved

Data Sheet

TOC-32

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-4 Port 10 Functions (cont'd)

Pin

Symbol

Ctrl

G10

P10.5

I

TIN107

HWCFG4

RXDCANr0A

INJ01

P10.5

O0

TOUT107

O1

ATX2

O2

SLSO38

O3

SLSO19

O4

T6OUT

O5

ASLSO2

O6

PSITX3

O7

F9

P10.6

I

TIN108

ARX2D

MTSR3B

PSIRX3C

HWCFG5

P10.6

O0

TOUT108

O1

ASCLK2

O2

MTSR3

O3

T3OUT

O4

TXDCANr0

O5

MRST1

O6

VADCG7BFL0

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input SCU input CAN node 0 input (MultiCANr+) MSC0 input General-purpose output GTM output ASCLIN2 output QSPI3 output QSPI1 output GPT120 output ASCLIN2 output PSI5 output General-purpose input GTM input ASCLIN2 input QSPI3 input PSI5 input SCU input General-purpose output GTM output ASCLIN2 output QSPI3 output GPT120 output CAN node 0 output (MultiCANr+) QSPI1 output VADC output

Data Sheet

TOC-33

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-4 Port 10 Functions (cont'd)

Pin

Symbol

Ctrl

F8

P10.7

I

TIN109

ACTS2A

MRST3B

REQ4

CCPOS1C

T3EUDB

P10.7

O0

TOUT109

O1

­

O2

MRST3

O3

VADCG7BFL1

O4

TXDCANr0

O5

­

O6

­

O7

G9

P10.8

I

TIN110

SCLK3B

REQ5

CCPOS2C

T4INB

RXDCANr0B

P10.8

O0

TOUT110

O1

ARTS2

O2

SCLK3

O3

­

O4

­

O5

­

O6

­

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input ASCLIN2 input QSPI3 input SCU input CCU60 input GPT120 input General-purpose output GTM output Reserved QSPI3 output VADC output CAN node 0 output (MultiCANr+) Reserved Reserved General-purpose input GTM input QSPI3 input SCU input CCU60 input GPT120 input CAN node 0 input (MultiCANr+) General-purpose output GTM output ASCLIN2 output QSPI3 output Reserved Reserved Reserved Reserved

Data Sheet

TOC-34

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-4 Port 10 Functions (cont'd)

Pin

Symbol

Ctrl

B8

P10.9

I

TIN265

SENT10C

P10.9

O0

TOUT265

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

B7

P10.10

I

TIN266

SENT11C

P10.10

O0

TOUT266

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

A7

P10.11

I

TIN269

SENT14C

P10.11

O0

TOUT269

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input SENT input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved General-purpose input GTM input SENT input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved General-purpose input GTM input SENT input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved

Data Sheet

TOC-35

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-4 Port 10 Functions (cont'd)

Pin

Symbol

Ctrl

A6

P10.13

I

TIN268

SENT13C

P10.13

O0

TOUT268

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

B5

P10.14

I

TIN267

SENT12C

P10.14

O0

TOUT267

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

A5

P10.15

I

TIN270

P10.15

O0

TOUT270

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input SENT input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved General-purpose input GTM input SENT input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved

Data Sheet

TOC-36

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-5 Port 11 Functions

Pin

Symbol

K15

P11.0

TIN119

ARX3B

P11.0

TOUT119

ATX3

­

­

­

ETHTXD3

­

K14

P11.1

TIN120

P11.1

TOUT120

ASCLK3

ATX3

­

­

ETHTXD2

­

F15

P11.2

TIN95

P11.2

TOUT95

END03

SLSO05

SLSO15

EN01

ETHTXD1

COUT63

Ctrl Type

Function

I

MP+ /

General-purpose input

PU1 / VFLEX

GTM input ASCLIN3 input

O0

General-purpose output

O1

GTM output

O2

ASCLIN3 output

O3

Reserved

O4

Reserved

O5

Reserved

O6

ETH output

O7

Reserved

I

MP+ /

General-purpose input

PU1 /

GTM input

VFLEX

O0

General-purpose output

O1

GTM output

O2

ASCLIN3 output

O3

ASCLIN3 output

O4

Reserved

O5

Reserved

O6

ETH output

O7

Reserved

I

MPR/

General-purpose input

PU1 /

GTM input

VFLEX

O0

General-purpose output

O1

GTM output

O2

MSC0 output

O3

QSPI0 output

O4

QSPI1 output

O5

MSC0 output

O6

ETH output

O7

CCU60 output

Data Sheet

TOC-37

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-5 Port 11 Functions (cont'd)

Pin

Symbol

Ctrl

G15

P11.3

I

TIN96

MRST1B

SDI03

P11.3

O0

TOUT96

O1

­

O2

MRST1

O3

TXD0A

O4

­

O5

ETHTXD0

O6

COUT62

O7

J15

P11.4

I

TIN121

ETHRXCLKB

P11.4

O0

TOUT121

O1

ASCLK3

O2

­

O3

­

O4

­

O5

ETHTXER

O6

­

O7

J13

P11.5

I

TIN122

ETHTXCLKA

P11.5

O0

TOUT122

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

Type MPR / PU1 / VFLEX
MP+ / PU1 / VFLEX
LP / PU1 / VFLEX

Function General-purpose input GTM input QSPI1 input MSC0 input General-purpose output GTM output Reserved QSPI1 output ERAY0 output Reserved ETH output CCU60 output General-purpose input GTM input ETH input General-purpose output GTM output ASCLIN3 output Reserved Reserved Reserved ETH output Reserved General-purpose input GTM input ETH input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved

Data Sheet

TOC-38

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-5 Port 11 Functions (cont'd)

Pin

Symbol

Ctrl

J14

P11.6

I

TIN97

SCLK1B

P11.6

O0

TOUT97

O1

TXEN0B

O2

SCLK1

O3

TXEN0A

O4

FCLP0

O5

ETHTXEN

O6

COUT61

O7

K13

P11.7

I

TIN123

ETHRXD3

P11.7

O0

TOUT123

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

K12

P11.8

I

TIN124

ETHRXD2

P11.8

O0

TOUT124

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

Type MPR / PU1 / VFLEX
LP / PU1 / VFLEX
LP / PU1 / VFLEX

Function General-purpose input GTM input QSPI1 input General-purpose output GTM output ERAY0 output QSPI1 output ERAY0 output MSC0 output ETH output CCU60 output General-purpose input GTM input ETH input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved General-purpose input GTM input ETH input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved

Data Sheet

TOC-39

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-5 Port 11 Functions (cont'd)

Pin

Symbol

Ctrl

F14

P11.9

I

TIN98

MTSR1B

RXD0A1

ETHRXD1

P11.9

O0

TOUT98

O1

­

O2

MTSR1

O3

­

O4

SOP0

O5

­

O6

COUT60

O7

G14

P11.10

I

TIN99

REQ12

ARX1E

SLSI1A

RXDCAN3D

RXD0B1

ETHRXD0

SDI00

P11.10

O0

TOUT99

O1

­

O2

SLSO03

O3

SLSO13

O4

­

O5

­

O6

CC62

O7

Type MP+ / PU1 / VFLEX
LP / PU1 / VFLEX

Function General-purpose input GTM input QSPI1 input ERAY0 input ETH input General-purpose output GTM output Reserved QSPI1 output Reserved MSC0 output Reserved CCU60 output General-purpose input GTM input SCU input ASCLIN1 input QSPI1 input CAN node 3 input ERAY0 input ETH input MSC0 input General-purpose output GTM output Reserved QSPI0 output QSPI1 output Reserved Reserved CCU60 output

Data Sheet

TOC-40

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-5 Port 11 Functions (cont'd)

Pin

Symbol

Ctrl

F13

P11.11

I

TIN100

ETHCRSDVA

ETHRXDVA

ETHCRSB

P11.11

O0

TOUT100

O1

END02

O2

SLSO04

O3

SLSO14

O4

EN00

O5

TXEN0B

O6

CC61

O7

G13

P11.12

I

TIN101

ETHREFCLK

ETHTXCLKB

ETHRXCLKA

P11.12

O0

TOUT101

O1

ATX1

O2

GTMCLK2

O3

TXD0B

O4

TXDCAN3

O5

EXTCLK1

O6

CC60

O7

Type MP+ / PU1 / VFLEX
MPR / PU1 / VFLEX

Function General-purpose input GTM input ETH input ETH input ETH input General-purpose output GTM output MSC0 output QSPI0 output QSPI1 output MSC0 output ERAY0 output CCU60 output General-purpose input GTM input ETH input ETH input (Not for productive purposes) ETH input (Not for productive purposes) General-purpose output GTM output ASCLIN1 output GTM output ERAY0 output CAN node 3 output SCU output CCU60 output

Data Sheet

TOC-41

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-5 Port 11 Functions (cont'd)

Pin

Symbol

Ctrl

K11

P11.13

I

TIN125

ETHRXERA

SDA1A

P11.13

O0

TOUT125

O1

­

O2

­

O3

­

O4

­

O5

SDA1

O6

­

O7

J12

P11.14

I

TIN126

ETHCRSDVB

ETHRXDVB

ETHCRSA

SCL1A

P11.14

O0

TOUT126

O1

­

O2

­

O3

­

O4

­

O5

SCL1

O6

­

O7

J11

P11.15

I

TIN127

ETHCOL

P11.15

O0

TOUT127

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

Type LP / PU1 / VFLEX
LP / PU1 / VFLEX
LP / PU1 / VFLEX

Function General-purpose input GTM input ETH input I2C1 input General-purpose output GTM output Reserved Reserved Reserved Reserved I2C1 output Reserved General-purpose input GTM input ETH input ETH input ETH input I2C1 input General-purpose output GTM output Reserved Reserved Reserved Reserved I2C1 output Reserved General-purpose input GTM input ETH input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved

Data Sheet

TOC-42

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-6 Port 12 Functions

Pin

Symbol

K17

P12.0

TIN128

ETHRXCLKC

RXDCAN0C

P12.0

TOUT128

­

­

­

­

ETHMDC

­

K16

P12.1

TIN129

P12.1

TOUT129

ASLSO3

­

­

TXDCAN0

­

­

ETHMDIOC

Ctrl

Type

I

LP /

PU1 /

VFLEX

O0 O1 O2 O3 O4 O5 O6 O7 I
O0 O1 O2 O3 O4 O5 O6 O7 HWOU T

LP / PU1 / VFLEX

Function General-purpose input GTM input ETH input CAN node 0 input General-purpose output GTM output Reserved Reserved Reserved Reserved ETH output Reserved General-purpose input GTM input General-purpose output GTM output ASCLIN3 output Reserved Reserved CAN node 0 output Reserved Reserved ETH input/output

Table 2-7 Port 13 Functions

Pin

Symbol

Ctrl Type

Function

G17

P13.0

TIN91

P13.0

I

LVDSM_N / General-purpose input

PU1 / VEXT O0

GTM input General-purpose output

TOUT91

O1

GTM output

END03

O2

MSC0 output

SCLK2N

O3

QSPI2 output (LVDS)

EN01

O4

MSC0 output

FCLN0

O5

MSC0 output (LVDS)

FCLND0

O6

MSC0 output (LVDS)

­

O7

Reserved

Data Sheet

TOC-43

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-7 Port 13 Functions (cont'd)

Pin

Symbol

Ctrl

F17

P13.1

I

TIN92

SCL0B

P13.1

O0

TOUT92

O1

­

O2

SCLK2P

O3

­

O4

FCLP0

O5

SCL0

O6

­

O7

G16

P13.2

I

TIN93

CAPINA

SDA0B

P13.2

O0

TOUT93

O1

­

O2

MTSR2N

O3

FCLP0

O4

SON0

O5

SDA0

O6

SOND0

O7

F16

P13.3

I

TIN94

P13.3

O0

TOUT94

O1

­

O2

MTSR2P

O3

­

O4

SOP0

O5

­

O6

­

O7

Type LVDSM_P / PU1 / VEXT
LVDSM_N / PU1 / VEXT
LVDSM_P / PU1 / VEXT

Function General-purpose input GTM input I2C0 input General-purpose output GTM output Reserved QSPI2 output (LVDS) Reserved MSC0 output (LVDS) I2C0 output Reserved General-purpose input GTM input GPT120 input I2C0 input General-purpose output GTM output Reserved QSPI2 output (LVDS) MSC0 output MSC0 output (LVDS) I2C0 output MSC0 output (LVDS) General-purpose input GTM input General-purpose output GTM output Reserved QSPI2 output (LVDS) Reserved MSC0 output (LVDS) Reserved Reserved

Data Sheet

TOC-44

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-7 Port 13 Functions (cont'd)

Pin

Symbol

Ctrl

B16

P13.4

I

TIN253

PSIRX4A

P13.4

O0

TOUT253

O1

END22

O2

­

O3

EN20

O4

FCLN2

O5

FCLND2

O6

­

O7

A16

P13.5

I

TIN254

P13.5

O0

TOUT254

O1

­

O2

­

O3

­

O4

FCLP2

O5

­

O6

­

O7

B15

P13.6

I

TIN255

P13.6

O0

TOUT255

O1

­

O2

­

O3

­

O4

SON2

O5

SOND2

O6

­

O7

Type LVDSM_N / PU1 / VEXT
LVDSM_P / PU1 / VEXT
LVDSM_N / PU1 / VEXT

Function General-purpose input GTM input PSI5 input General-purpose output GTM output MSC2 output Reserved MSC2 output MSC2 output (LVDS) MSC2 output (LVDS) Reserved General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved MSC2 output (LVDS) Reserved Reserved General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved MSC2 output (LVDS) MSC2 output (LVDS) Reserved

Data Sheet

TOC-45

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-7 Port 13 Functions (cont'd)

Pin

Symbol

Ctrl

A15

P13.7

I

TIN256

P13.7

O0

TOUT256

O1

­

O2

­

O3

­

O4

SOP2

O5

­

O6

­

O7

A14

P13.9

I

TIN248

SCL1B

P13.9

O0

TOUT248

O1

ATX3

O2

SLSO55

O3

­

O4

TXDCANr1

O5

SCL1

O6

­

O7

B13

P13.10

I

TIN251

PSIRX3A

P13.10

O0

TOUT251

O1

ATX0

O2

­

O3

­

O4

­

O5

­

O6

­

O7

Type LVDSM_P / PU1 / VEXT
MP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved MSC2 output (LVDS) Reserved Reserved General-purpose input GTM input I2C1 input General-purpose output GTM output ASCLIN3 output QSPI5 output Reserved CAN node 1 output (MultiCANr+) I2C1 output Reserved General-purpose input GTM input PSI5 input General-purpose output GTM output ASCLIN0 output Reserved Reserved Reserved Reserved Reserved

Data Sheet

TOC-46

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-7 Port 13 Functions (cont'd)

Pin

Symbol

Ctrl

A13

P13.11

I

TIN250

ARX0E

P13.11

O0

TOUT250

O1

­

O2

­

O3

­

O4

PSITX3

O5

­

O6

­

O7

B12

P13.12

I

TIN249

ARX3H

RXDCANr1B

SDA1B

P13.12

O0

TOUT249

O1

­

O2

­

O3

­

O4

­

O5

SDA1

O6

­

O7

A12

P13.13

I

TIN262

PSIRX3B

INJ20

Type LP / PU1 / VEXT
LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input ASCLIN0 input General-purpose output GTM output Reserved Reserved Reserved PSI5 output Reserved Reserved General-purpose input GTM input ASCLIN3 input CAN node 1 input (MultiCANr+) I2C1 input General-purpose output GTM output Reserved Reserved Reserved Reserved I2C1 output Reserved General-purpose input GTM input PSI5 input MSC2 input

P13.13

O0

TOUT262

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved

Data Sheet

TOC-47

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-7 Port 13 Functions (cont'd)

Pin

Symbol

Ctrl

B11

P13.14

I

TIN252

P13.14

O0

TOUT252

O1

­

O2

SLSO54

O3

­

O4

­

O5

­

O6

­

O7

A11

P13.15

I

TIN264

P13.15

O0

TOUT264

O1

­

O2

­

O3

PSITX3

O4

­

O5

­

O6

­

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input General-purpose output GTM output Reserved QSPI5 output Reserved Reserved Reserved Reserved General-purpose input GTM input General-purpose output GTM output Reserved Reserved PSI5 output Reserved Reserved Reserved

Table 2-8 Port 14 Functions

Pin

Symbol

Ctrl Type Function

G21

P14.0

TIN80

SENT12D

I

MP+ / General-purpose input

PU1 / VEXT

GTM input SENT input

P14.0

O0

General-purpose output

TOUT80

O1

GTM output

ATX0

O2

ASCLIN0 output

Recommended as Boot loader pin

TXD0A

O3

ERAY0 output

TXD0B

O4

ERAY0 output

TXDCAN1

O5

CAN node 1 output Used for single pin DAP (SPD) function

ASCLK0

O6

ASCLIN0 output

COUT62

O7

CCU60 output

Data Sheet

TOC-48

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-8 Port 14 Functions (cont'd)

Pin

Symbol

Ctrl

F20

P14.1

I

TIN81

REQ15

SENT13D

ARX0A

RXDCAN1B

RXD0A3

RXD0B3

EVRWUPA

P14.1

O0

TOUT81

O1

ATX0

O2

­

O3

­

O4

­

O5

­

O6

COUT63

O7

K18

P14.2

I

TIN82

HWCFG2 EVR13

P14.2

O0

TOUT82

O1

ATX2

O2

SLSO21

O3

­

O4

­

O5

ASCLK2

O6

­

O7

Type MP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input SCU input SENT input ASCLIN0 input Recommended as Boot loader pin CAN node 1 input Used for single pin DAP (SPD) function ERAY0 input ERAY0 input SCU input General-purpose output GTM output ASCLIN0 output Recommended as Boot loader pin. Reserved Reserved Reserved Reserved CCU60 output General-purpose input GTM input SCU input Latched at cold power on reset to decide EVR13 activation. General-purpose output GTM output ASCLIN2 output QSPI2 output Reserved Reserved ASCLIN2 output Reserved

Data Sheet

TOC-49

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-8 Port 14 Functions (cont'd)

Pin

Symbol

Ctrl

G19

P14.3

I

TIN83

ARX2A

REQ10

HWCFG3_BMI

SDI02

P14.3

O0

TOUT83

O1

ATX2

O2

SLSO23

O3

ASLSO1

O4

ASLSO3

O5

­

O6

­

O7

G20

P14.4

I

TIN84

HWCFG6

P14.4

O0

TOUT84

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input ASCLIN2 input SCU input SCU input MSC0 input General-purpose output GTM output ASCLIN2 output QSPI2 output ASCLIN1 output ASCLIN3 output Reserved Reserved General-purpose input GTM input SCU input Latched at cold power on reset to decide default pad reset state (PU or HighZ). General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved

Data Sheet

TOC-50

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-8 Port 14 Functions (cont'd)

Pin

Symbol

Ctrl

F19

P14.5

I

TIN85

HWCFG1 EVR33

P14.5

O0

TOUT85

O1

­

O2

­

O3

­

O4

­

O5

TXD0B

O6

TXD1B

O7

G18

P14.6

I

TIN86

HWCFG0 DCLDO

P14.6

O0

TOUT86

O1

­

O2

SLSO22

O3

­

O4

­

O5

TXEN0B

O6

TXEN1B

O7

J18

P14.7

I

TIN87

RXD0B0

RXD1B0

P14.7

O0

TOUT87

O1

ARTS0

O2

SLSO24

O3

­

O4

­

O5

­

O6

­

O7

Type MP+ / PU1 / VEXT
MP+ / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input SCU input Latched at cold power on reset to decide EVR33 activation. General-purpose output GTM output Reserved Reserved Reserved Reserved ERAY0 output ERAY1 output General-purpose input GTM input SCU input If EVR13 active, latched at cold power on reset to decide between LDO and SMPS mode. General-purpose output GTM output Reserved QSPI2 output Reserved Reserved ERAY0 output ERAY1 output General-purpose input GTM input ERAY0 input ERAY1 input General-purpose output GTM output ASCLIN0 output QSPI2 output Reserved Reserved Reserved Reserved

Data Sheet

TOC-51

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-8 Port 14 Functions (cont'd)

Pin

Symbol

Ctrl

F18

P14.8

I

TIN88

ARX1D

RXDCAN2D

RXD0A0

RXD1A0

P14.8

O0

TOUT88

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

J17

P14.9

I

TIN89

ACTS0A

P14.9

O0

TOUT89

O1

END03

O2

EN01

O3

­

O4

TXEN0B

O5

TXEN0A

O6

TXEN1A

O7

J16

P14.10

I

TIN90

P14.10

O0

TOUT90

O1

END02

O2

EN00

O3

ATX1

O4

TXDCAN2

O5

TXD0A

O6

TXD1A

O7

Type LP / PU1 / VEXT
MP+ / PU1 / VEXT
MP+ / PU1 / VEXT

Function General-purpose input GTM input ASCLIN1 input CAN node 2 input ERAY0 input ERAY1 input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved General-purpose input GTM input ASCLIN0 input General-purpose output GTM output MSC0 output MSC0 output Reserved ERAY0 output ERAY0 output ERAY1 output General-purpose input GTM input General-purpose output GTM output MSC0 output MSC0 output ASCLIN1 output CAN node 2 output ERAY0 output ERAY1 output

Data Sheet

TOC-52

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-8 Port 14 Functions (cont'd)

Pin

Symbol

Ctrl

A20

P14.11

I

TIN258

P14.11

O0

TOUT258

O1

END20

O2

PSITX4

O3

EN22

O4

SOP2

O5

­

O6

­

O7

B19

P14.12

I

TIN261

SDI20

P14.12

O0

TOUT261

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

A19

P14.13

I

TIN260

P14.13

O0

TOUT260

O1

END23

O2

­

O3

EN21

O4

­

O5

­

O6

­

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT
MP+ / PU1 / VEXT

Function General-purpose input GTM input General-purpose output GTM output MSC2 output PSI5 output MSC2 output MSC2 output Reserved Reserved General-purpose input GTM input MSC2 input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved General-purpose input GTM input General-purpose output GTM output MSC2 output Reserved MSC2 output Reserved Reserved Reserved

Data Sheet

TOC-53

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-8 Port 14 Functions (cont'd)

Pin

Symbol

Ctrl

B18

P14.14

I

TIN259

P14.14

O0

TOUT259

O1

END22

O2

­

O3

EN20

O4

­

O5

­

O6

­

O7

A18

P14.15

I

TIN263

INJ21

P14.15

O0

TOUT263

O1

ATX1

O2

­

O3

­

O4

­

O5

­

O6

­

O7

Type MP+ / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input General-purpose output GTM output MSC2 output Reserved MSC2 output Reserved Reserved Reserved General-purpose input GTM input MSC2 output General-purpose output GTM output ASCLIN1 output Reserved Reserved Reserved Reserved Reserved

Table 2-9 Port 15 Functions

Pin

Symbol

G25

P15.0

TIN71

P15.0

TOUT71

ATX1

SLSO013

­

TXDCAN2

ASCLK1

­

Ctrl Type Function

I

LP /

General-purpose input

PU1 / GTM input

VEXT

O0

General-purpose output

O1

GTM output

O2

ASCLIN1 output

O3

QSPI0 output

O4

Reserved

O5

CAN node 2 output

O6

ASCLIN1 output

O7

Reserved

Data Sheet

TOC-54

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-9 Port 15 Functions (cont'd)

Pin

Symbol

Ctrl

F23

P15.1

I

TIN72

REQ16

ARX1A

RXDCAN2A

SLSI2B

EVRWUPB

P15.1

O0

TOUT72

O1

ATX1

O2

SLSO25

O3

­

O4

­

O5

­

O6

­

O7

H24

P15.2

I

TIN73

SLSI2A

MRST2E

SENT10D

HSIC2INA

P15.2

O0

TOUT73

O1

ATX0

O2

SLSO20

O3

­

O4

TXDCAN1

O5

ASCLK0

O6

­

O7

Type LP / PU1 / VEXT
MP / PU1 / VEXT

Function General-purpose input GTM input SCU input ASCLIN1 input CAN node 2 input QSPI2 input SCU input General-purpose output GTM output ASCLIN1 output QSPI2 output Reserved Reserved Reserved Reserved General-purpose input GTM input QSPI2 input QSPI2 input SENT input QSPI2 input General-purpose output GTM output ASCLIN0 output QSPI2 output Reserved CAN node 1 output ASCLIN0 output Reserved

Data Sheet

TOC-55

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-9 Port 15 Functions (cont'd)

Pin

Symbol

Ctrl

G22

P15.3

I

TIN74

ARX0B

SCLK2A

RXDCAN1A

HSIC2INB

P15.3

O0

TOUT74

O1

ATX0

O2

SCLK2

O3

END03

O4

EN01

O5

­

O6

­

O7

F22

P15.4

I

TIN75

MRST2A

REQ0

SCL0C

SENT11D

P15.4

O0

TOUT75

O1

ATX1

O2

MRST2

O3

­

O4

­

O5

SCL0

O6

CC62

O7

Type MP / PU1 / VEXT
MP / PU1 / VEXT

Function General-purpose input GTM input ASCLIN0 input QSPI2 input CAN node 1 input QSPI2 input General-purpose output GTM output ASCLIN0 output QSPI2 output MSC0 output MSC0 output Reserved Reserved General-purpose input GTM input QSPI2 input SCU input I2C0 input SENT input General-purpose output GTM output ASCLIN1 output QSPI2 output Reserved Reserved I2C0 output CCU60 output

Data Sheet

TOC-56

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-9 Port 15 Functions (cont'd)

Pin

Symbol

Ctrl

K19

P15.5

I

TIN76

ARX1B

MTSR2A

REQ13

SDA0C

P15.5

O0

TOUT76

O1

ATX1

O2

MTSR2

O3

END02

O4

EN00

O5

SDA0

O6

CC61

O7

F21

P15.6

I

TIN77

MTSR2B

P15.6

O0

TOUT77

O1

ATX3

O2

MTSR2

O3

SLSO53

O4

SCLK2

O5

ASCLK3

O6

CC60

O7

J20

P15.7

I

TIN78

ARX3A

MRST2B

P15.7

O0

TOUT78

O1

ATX3

O2

MRST2

O3

­

O4

­

O5

­

O6

COUT60

O7

Type MP / PU1 / VEXT
MP / PU1 / VEXT
MP / PU1 / VEXT

Function General-purpose input GTM input ASCLIN1 input QSPI2 input SCU input I2C0 input General-purpose output GTM output ASCLIN1 output QSPI2 output MSC0 output MSC0 output I2C0 output CCU60 output General-purpose input GTM input QSPI2 input General-purpose output GTM output ASCLIN3 output QSPI2 output QSPI5 output QSPI2 output ASCLIN3 output CCU60 output General-purpose input GTM input ASCLIN3 input QSPI2 input General-purpose output GTM output ASCLIN3 output QSPI2 output Reserved Reserved Reserved CCU60 output

Data Sheet

TOC-57

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-9 Port 15 Functions (cont'd)

Pin

Symbol

Ctrl

J19

P15.8

I

TIN79

SCLK2B

REQ1

P15.8

O0

TOUT79

O1

­

O2

SCLK2

O3

­

O4

­

O5

ASCLK3

O6

COUT61

O7

B24

P15.10

I

TIN242

MRST5A

P15.10

O0

TOUT242

O1

­

O2

MRST5

O3

­

O4

­

O5

­

O6

­

O7

A24

P15.11

I

TIN243

SLSI5A

P15.11

O0

TOUT243

O1

­

O2

SLSO52

O3

­

O4

­

O5

­

O6

­

O7

Type MP / PU1 / VEXT
LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input QSPI2 input SCU input General-purpose output GTM output Reserved QSPI2 output Reserved Reserved ASCLIN3 output CCU60 output General-purpose input GTM input QSPI5 input General-purpose output GTM output Reserved QSPI5 output Reserved Reserved Reserved Reserved General-purpose input GTM input QSPI5 input General-purpose output GTM output Reserved QSPI5 output Reserved Reserved Reserved Reserved

Data Sheet

TOC-58

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-9 Port 15 Functions (cont'd)

Pin

Symbol

Ctrl

B23

P15.12

I

TIN244

P15.12

O0

TOUT244

O1

­

O2

SLSO51

O3

­

O4

­

O5

­

O6

­

O7

A23

P15.13

I

TIN245

P15.13

O0

TOUT245

O1

­

O2

SLSO50

O3

­

O4

­

O5

­

O6

­

O7

B22

P15.14

I

TIN246

MTSR5A

P15.14

O0

TOUT246

O1

­

O2

MTSR5

O3

­

O4

­

O5

­

O6

­

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT
MP / PU1 / VEXT

Function General-purpose input GTM input General-purpose output GTM output Reserved QSPI5 output Reserved Reserved Reserved Reserved General-purpose input GTM input General-purpose output GTM output Reserved QSPI5 output Reserved Reserved Reserved Reserved General-purpose input GTM input QSPI5 input General-purpose output GTM output Reserved QSPI5 output Reserved Reserved Reserved Reserved

Data Sheet

TOC-59

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-9 Port 15 Functions (cont'd)

Pin

Symbol

Ctrl

A22

P15.15

I

TIN247

SCLK5A

P15.15

O0

TOUT247

O1

­

O2

SCLK5

O3

­

O4

­

O5

­

O6

­

O7

Type
MP / PU1 / VEXT

Function General-purpose input GTM input QSPI5 input General-purpose output GTM output Reserved QSPI5 output Reserved Reserved Reserved Reserved

Table 2-10 Port 20 Functions

Pin

Symbol

N25

P20.0

TIN59

RXDCAN3C

RXDCANr1C

T6EUDA

REQ9

SYSCLK

TGI0

P20.0

TOUT59

ATX3

ASCLK3

­

SYSCLK

­

­

TGO0

Ctrl Type

I

MP /

PU1 /

VEXT

O0 O1 O2 O3 O4 O5 O6 O7 HWOU T

Function General-purpose input GTM input CAN node 3 input CAN node 1 input (MultiCANr+) GPT120 input SCU input HSCT input OCDS input General-purpose output GTM output ASCLIN3 output ASCLIN3 output Reserved HSCT output Reserved Reserved OCDS; ENx

Data Sheet

TOC-60

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-10 Port 20 Functions (cont'd)

Pin

Symbol

Ctrl Type

M24

P20.1

TIN60

TGI1

I

LP /

PU1 /

VEXT

P20.1

O0

TOUT60

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

TGO1

HWOU T

N24

P20.2

I

LP /

PU1 /

VEXT

TESTMODE

P20.2

O0

­

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

M25

P20.3

TIN61

T6INA

I

LP /

PU1 /

VEXT

ARX3C

P20.3

O0

TOUT61

O1

ATX3

O2

SLSO09

O3

SLSO29

O4

TXDCAN3

O5

TXDCANr1

O6

­

O7

Function General-purpose input GTM input OCDS input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved OCDS; ENx
General-purpose input This pin is latched at power on reset release to enter test mode. OCDS input Output function not available Output function not available Output function not available Output function not available Output function not available Output function not available Output function not available Output function not available General-purpose input GTM input GPT120 input ASCLIN3 input General-purpose output GTM output ASCLIN3 output QSPI0 output QSPI2 output CAN node 3 output CAN node 1 output (MultiCANr+) Reserved

Data Sheet

TOC-61

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-10 Port 20 Functions (cont'd)

Pin

Symbol

Ctrl

L22

P20.6

I

TIN62

P20.6

O0

TOUT62

O1

ARTS1

O2

SLSO08

O3

SLSO28

O4

­

O5

WDT2LCK

O6

­

O7

L24

P20.7

I

TIN63

ACTS1A

RXDCAN0B

P20.7

O0

TOUT63

O1

­

O2

­

O3

­

O4

­

O5

WDT1LCK

O6

COUT63

O7

L25

P20.8

I

TIN64

P20.8

O0

TOUT64

O1

ASLSO1

O2

SLSO00

O3

SLSO10

O4

TXDCAN0

O5

WDT0LCK

O6

CC60

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT
MP / PU1 / VEXT

Function General-purpose input GTM input General-purpose output GTM output ASCLIN1 output QSPI0 output QSPI2 output Reserved SCU output Reserved General-purpose input GTM input ASCLIN1 input CAN node 0 input General-purpose output GTM output Reserved Reserved Reserved Reserved SCU output CCU61 output General-purpose input GTM input General-purpose output GTM output ASCLIN1 output QSPI0 output QSPI1 output CAN node 0 output SCU output CCU61 output

Data Sheet

TOC-62

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-10 Port 20 Functions (cont'd)

Pin

Symbol

Ctrl

K22

P20.9

I

TIN65

ARX1C

RXDCAN3E

REQ11

SLSI0B

P20.9

O0

TOUT65

O1

­

O2

SLSO01

O3

SLSO11

O4

­

O5

WDTSLCK

O6

CC61

O7

K24

P20.10

I

TIN66

P20.10

O0

TOUT66

O1

ATX1

O2

SLSO06

O3

SLSO27

O4

TXDCAN3

O5

ASCLK1

O6

CC62

O7

K25

P20.11

I

TIN67

SCLK0A

P20.11

O0

TOUT67

O1

­

O2

SCLK0

O3

­

O4

­

O5

­

O6

COUT60

O7

Type LP / PU1 / VEXT
MP / PU1 / VEXT
MP / PU1 / VEXT

Function General-purpose input GTM input ASCLIN1 input CAN node 3 input SCU input QSPI0 input General-purpose output GTM output Reserved QSPI0 output QSPI1 output Reserved SCU output CCU61 output General-purpose input GTM input General-purpose output GTM output ASCLIN1 output QSPI0 output QSPI2 output CAN node 3 output ASCLIN1 output CCU61 output General-purpose input GTM input QSPI0 input General-purpose output GTM output Reserved QSPI0 output Reserved Reserved Reserved CCU61 output

Data Sheet

TOC-63

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-10 Port 20 Functions (cont'd)

Pin

Symbol

Ctrl

J24

P20.12

I

TIN68

MRST0A

P20.12

O0

TOUT68

O1

­

O2

MRST0

O3

MTSR0

O4

­

O5

­

O6

COUT61

O7

J25

P20.13

I

TIN69

SLSI0A

P20.13

O0

TOUT69

O1

­

O2

SLSO02

O3

SLSO12

O4

SCLK0

O5

­

O6

COUT62

O7

H25

P20.14

I

TIN70

MTSR0A

P20.14

O0

TOUT70

O1

­

O2

MTSR0

O3

­

O4

­

O5

­

O6

­

O7

Type MP / PU1 / VEXT
MP / PU1 / VEXT
MP / PU1 / VEXT

Function General-purpose input GTM input QSPI0 input General-purpose output GTM output Reserved QSPI0 output QSPI0 output Reserved Reserved CCU61 output General-purpose input GTM input QSPI0 input General-purpose output GTM output Reserved QSPI0 output QSPI1 output QSPI0 output Reserved CCU61 output General-purpose input GTM input QSPI0 input General-purpose output GTM output Reserved QSPI0 output Reserved Reserved Reserved Reserved

Data Sheet

TOC-64

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-11 Port 21 Functions

Pin

Symbol

Ctrl

R22

P21.0

I

TIN51

MRST4DN

HOLD

P21.0

O0

TOUT51

O1

­

O2

­

O3

­

O4

­

O5

ETHMDC

O6

BAABA0

O7

HSM1

O

P22

P21.1

I

TIN52

ETHMDIOB

MRST4DP

WAIT

P21.1

O0

TOUT52

O1

­

O2

­

O3

­

O4

­

O5

ETHMDIO

O6

BREQBA1

O7

HSM2

O

Type LVDSH_N/ PU1 / VDDP3
LVDSH_P/ PU1 / VDDP3

Function General-purpose input GTM input QSPI4 input (LVDS) EBU input General-purpose output GTM output Reserved Reserved Reserved Reserved ETH output EBU output (combined for BAA and BA0) HSM output General-purpose input GTM input ETH input (Not for production purposes) QSPI4 input (LVDS) EBU input General-purpose output GTM output Reserved Reserved Reserved Reserved ETH output (Not for production purposes) EBU output (combined for BREQ and BA1) HSM output

Data Sheet

TOC-65

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-11 Port 21 Functions (cont'd)

Pin

Symbol

Ctrl

Type

R24

P21.2

TIN53

MRST2CN

I

LVDSH_N/

PU1 /

VDDP3

MRST4CN

ARX3GN

EMGSTOPB

RXDN

P21.2

O0

TOUT53

O1

ASLSO3

O2

­

O3

­

O4

ETHMDC

O5

SDRAMA8

O6

­

O7

P24

P21.3

TIN54

MRST2CP

I

LVDSH_P/

PU1 /

VDDP3

MRST4CP

ARX3GP

RXDP

P21.3

O0

TOUT54

O1

­

O2

­

O3

­

O4

­

O5

SDRAMA9

O6

­

O7

ETHMDIOD

HWOUT

Function General-purpose input GTM input QSPI2 input (LVDS) QSPI4 input (LVDS) ASCLIN3 input (LVDS) SCU input HSCT input (LVDS) General-purpose output GTM output ASCLIN3 output Reserved Reserved ETH output EBU output Reserved General-purpose input GTM input QSPI2 input (LVDS) QSPI4 input (LVDS) ASCLIN3 input (LVDS) HSCT input (LVDS) General-purpose output GTM output Reserved Reserved Reserved Reserved EBU output Reserved ETH input/output

Data Sheet

TOC-66

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-11 Port 21 Functions (cont'd)

Pin

Symbol

Ctrl

Type

R25

P21.4

TIN55

P21.4

I

LVDSH_N/

PU1 /

VDDP3 O0

TOUT55

O1

­

O2

­

O3

­

O4

­

O5

SDRAMA10

O6

­

O7

TXDN

HSCT

P25

P21.5

TIN56

P21.5

I

LVDSH_P/

PU1 /

VDDP3 O0

TOUT56

O1

ASCLK3

O2

­

O3

­

O4

­

O5

SDRAMA11

O6

­

O7

TXDP

HSCT

N22

P21.6

TIN57

ARX3F

I

A2 /

PU /

VDDP3

TGI2

TDI

T5EUDA

P21.6

O0

TOUT57

O1

ASLSO3

O2

­

O3

­

O4

SYSCLK

O5

SDRAMA12

O6

T3OUT

O7

TGO2

HWOUT

Function General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved EBU output Reserved HSCT output (LVDS) General-purpose input GTM input General-purpose output GTM output ASCLIN3 output Reserved Reserved Reserved EBU output Reserved HSCT output (LVDS) General-purpose input GTM input ASCLIN3 input OCDS input OCDS (JTAG) input GPT120 input General-purpose output GTM output ASCLIN3 output Reserved Reserved HSCT output EBU output GPT120 output OCDS; ENx

Data Sheet

TOC-67

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-11 Port 21 Functions (cont'd)

Pin

Symbol

Ctrl

N21

P21.7

I

TIN58

DAP2

Type
A2 / PU / VDDP3

TGI3 ETHRXERB T5INA P21.7 TOUT58 ATX3 ASCLK3 ­ ­ SDRAMA13 T6OUT TGO3 TDO

O0 O1 O2 O3 O4 O5 O6 O7 HWOUT

DAP2

Function General-purpose input GTM input OCDS (3-Pin DAP) input In the 3-Pin DAP mode this pin is used as DAP2. In the 2-PIN DAP mode this pin is used as P21.7 and controlled by the related port control logic OCDS input ETH input GPT120 input General-purpose output GTM output ASCLIN3 output ASCLIN3 output Reserved Reserved EBU output GPT120 output OCDS; ENx OCDS (JTAG); ENx The JTAG TDO function is overlayed with P21.7 via a double bond. In JTAG mode this pin is used as TDO, after power-on reset it is HighZ. OCDS (3-Pin DAP); ENx In the 3-Pin DAP mode this pin is used as DAP2.

Table 2-12 Port 22 Functions

Pin

Symbol

W25

P22.0

TIN47

MTSR4B

P22.0

TOUT47

ATX3N

MTSR4

SCLK4N

FCLN1

FCLND1

­

Ctrl Type

I

LVDSM_N /

PU1 /

VEXT

O0 O1 O2 O3 O4 O5 O6 O7

Function General-purpose input GTM input QSPI4 input General-purpose output GTM output ASCLIN3 output (LVDS) QSPI4 output QSPI4 output (LVDS) MSC1 output (LVDS) MSC1 output (LVDS) Reserved

Data Sheet

TOC-68

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-12 Port 22 Functions (cont'd)

Pin

Symbol

Ctrl

W24

P22.1

I

TIN48

MRST4B

P22.1

O0

TOUT48

O1

ATX3P

O2

MRST4

O3

SCLK4P

O4

FCLP1

O5

­

O6

­

O7

Y25

P22.2

I

TIN49

SLSI4B

P22.2

O0

TOUT49

O1

­

O2

SLSO43

O3

MTSR4N

O4

SON1

O5

SOND1

O6

­

O7

Y24

P22.3

I

TIN50

SCLK4B

P22.3

O0

TOUT50

O1

­

O2

SCLK4

O3

MTSR4P

O4

SOP1

O5

­

O6

­

O7

Type LVDSM_P / PU1 / VEXT
LVDSM_N / PU1 / VEXT
LVDSM_P / PU1 / VEXT

Function General-purpose input GTM input QSPI4 input General-purpose output GTM output ASCLIN3 output (LVDS) QSPI4 output QSPI4 output (LVDS) MSC1 output (LVDS) Reserved Reserved General-purpose input GTM input QSPI4 input General-purpose output GTM output Reserved QSPI4 output QSPI4 output (LVDS) MSC1 output (LVDS) MSC1 output (LVDS) Reserved General-purpose input GTM input QSPI4 input General-purpose output GTM output Reserved QSPI4 output QSPI4 output (LVDS) MSC1 output (LVDS) Reserved Reserved

Data Sheet

TOC-69

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-12 Port 22 Functions (cont'd)

Pin

Symbol

Ctrl

W21

P22.4

I

TIN130

P22.4

O0

TOUT130

O1

­

O2

­

O3

SLSO012

O4

PSITX4

O5

­

O6

­

O7

W22

P22.5

I

TIN131

MTSR0C

PSIRX4B

P22.5

O0

TOUT131

O1

­

O2

­

O3

MTSR0

O4

­

O5

­

O6

­

O7

V21

P22.6

I

TIN132

MRST0C

P22.6

O0

TOUT132

O1

­

O2

­

O3

MRST0

O4

­

O5

­

O6

­

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input General-purpose output GTM output Reserved Reserved QSPI0 output PSI5 output Reserved Reserved General-purpose input GTM input QSPI0 input PSI5 input General-purpose output GTM output Reserved Reserved QSPI0 output Reserved Reserved Reserved General-purpose input GTM input QSPI0 input General-purpose output GTM output Reserved Reserved QSPI0 output Reserved Reserved Reserved

Data Sheet

TOC-70

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-12 Port 22 Functions (cont'd)

Pin

Symbol

Ctrl

V22

P22.7

I

TIN133

SCLK0C

P22.7

O0

TOUT133

O1

­

O2

­

O3

SCLK0

O4

­

O5

­

O6

­

O7

U21

P22.8

I

TIN134

SCLK0B

P22.8

O0

TOUT134

O1

­

O2

­

O3

SCLK0

O4

­

O5

­

O6

­

O7

U22

P22.9

I

TIN135

MRST0B

P22.9

O0

TOUT135

O1

­

O2

­

O3

MRST0

O4

­

O5

­

O6

­

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input QSPI0 input General-purpose output GTM output Reserved Reserved QSPI0 output Reserved Reserved Reserved General-purpose input GTM input QSPI0 input General-purpose output GTM output Reserved Reserved QSPI0 output Reserved Reserved Reserved General-purpose input GTM input QSPI0 input General-purpose output GTM output Reserved Reserved QSPI0 output Reserved Reserved Reserved

Data Sheet

TOC-71

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-12 Port 22 Functions (cont'd)

Pin

Symbol

Ctrl

T21

P22.10

I

TIN136

MTSR0B

P22.10

O0

TOUT136

O1

­

O2

­

O3

MTSR0

O4

­

O5

­

O6

­

O7

T22

P22.11

I

TIN137

P22.11

O0

TOUT137

O1

­

O2

­

O3

SLSO010

O4

­

O5

­

O6

­

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input QSPI0 input General-purpose output GTM output Reserved Reserved QSPI0 output Reserved Reserved Reserved General-purpose input GTM input General-purpose output GTM output Reserved Reserved QSPI0 output Reserved Reserved Reserved

Table 2-13 Port 23 Functions

Pin

Symbol

Ctrl Type

Function

AC25

P23.0 TIN41 P23.0

I

LP /

General-purpose input

PU1 /

GTM input

VEXT

O0

General-purpose output

TOUT41

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

Data Sheet

TOC-72

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-13 Port 23 Functions (cont'd)

Pin

Symbol

Ctrl

AB24 P23.1

I

TIN42

SDI10

P23.1

O0

TOUT42

O1

ARTS1

O2

SLSO46

O3

GTMCLK0

O4

­

O5

EXTCLK0

O6

­

O7

AB25 P23.2

I

TIN43

P23.2

O0

TOUT43

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

AA24 P23.3

I

TIN44

INJ10

P23.3

O0

TOUT44

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

Type MP+ / PU1 / VEXT
LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input MSC1 input General-purpose output GTM output ASCLIN1 output QSPI4 output GTM output Reserved SCU output Reserved General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved General-purpose input GTM input MSC1 input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved

Data Sheet

TOC-73

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-13 Port 23 Functions (cont'd)

Pin

Symbol

Ctrl

AA25 P23.4

I

TIN45

P23.4

O0

TOUT45

O1

­

O2

SLSO45

O3

END12

O4

EN10

O5

­

O6

­

O7

AA22 P23.5

I

TIN46

P23.5

O0

TOUT46

O1

­

O2

SLSO44

O3

END13

O4

EN11

O5

­

O6

­

O7

Y22

P23.6

I

TIN138

P23.6

O0

TOUT138

O1

­

O2

­

O3

SLSO011

O4

­

O5

­

O6

­

O7

Type MP+ / PU1 / VEXT
MP+ / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input General-purpose output GTM output Reserved QSPI4 output MSC1 output MSC1 output Reserved Reserved General-purpose input GTM input General-purpose output GTM output Reserved QSPI4 output MSC1 output MSC1 output Reserved Reserved General-purpose input GTM input General-purpose output GTM output Reserved Reserved QSPI0 output Reserved Reserved Reserved

Data Sheet

TOC-74

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-13 Port 23 Functions (cont'd)

Pin

Symbol

Ctrl

Y21

P23.7

I

TIN139

P23.7

O0

TOUT139

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

Type
LP / PU1 / VEXT

Function General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved

Table 2-14 Port 24 Functions

Pin

Symbol

U29

P24.0

TIN222

P24.0

TOUT222

­

­

­

­

­

­

DQ11

A11

U30

P24.1

TIN223

P24.1

TOUT223

­

­

­

­

­

­

DQ15

A15

Ctrl Type

I

A2 /

PU1 /

VEBU O0

O1

O2

O3

O4

O5

O6

O7

HWOU T

I

A2 /

PU1 /

VEBU O0

O1

O2

O3

O4

O5

O6

O7

HWOU T

Function General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU Data Bus Line (SDRAM) EBU output General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU Data Bus Line (SDRAM) EBU output

Data Sheet

TOC-75

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-14 Port 24 Functions (cont'd)

Pin

Symbol

Ctrl Type

T29

P24.2

TIN224

P24.2

I

A2 /

PU1 /

VEBU O0

TOUT224

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

DQ14 A14

HWOU T

T30

P24.3

TIN225

P24.3

I

A2 /

PU1 /

VEBU O0

TOUT225

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

DQ13 A13

HWOU T

R29

P24.4

TIN226

P24.4

I

A2 /

PU1 /

VEBU O0

TOUT226

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

DQ9 A9

HWOU T

Function General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU Data Bus Line (SDRAM) EBU output General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU Data Bus Line (SDRAM) EBU output General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU Data Bus Line (SDRAM) EBU output

Data Sheet

TOC-76

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-14 Port 24 Functions (cont'd)

Pin

Symbol

Ctrl Type

R30

P24.5

TIN227

P24.5

I

A2 /

PU1 /

VEBU O0

TOUT227

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

DQ12 A12

HWOU T

P29

P24.6

TIN228

P24.6

I

A2 /

PU1 /

VEBU O0

TOUT228

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

DQ5 A5

HWOU T

P30

P24.7

TIN229

P24.7

I

A2 /

PU1 /

VEBU O0

TOUT229

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

DQ8 A8

HWOU T

Function General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU Data Bus Line (SDRAM) EBU output General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU Data Bus Line (SDRAM) EBU output General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU Data Bus Line (SDRAM) EBU output

Data Sheet

TOC-77

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-14 Port 24 Functions (cont'd)

Pin

Symbol

Ctrl Type

N29

P24.8

TIN230

P24.8

I

A2 /

PU1 /

VEBU O0

TOUT230

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

DQ10 A10

HWOU T

N30

P24.9

TIN231

P24.9

I

A2 /

PU1 /

VEBU O0

TOUT231

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

DQ6 A6

HWOU T

M29

P24.10

TIN232

P24.10

I

A2 /

PU1 /

VEBU O0

TOUT232

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

DQ4 A4

HWOU T

Function General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU Data Bus Line (SDRAM) EBU output General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU Data Bus Line (SDRAM) EBU output General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU Data Bus Line (SDRAM) EBU output

Data Sheet

TOC-78

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-14 Port 24 Functions (cont'd)

Pin

Symbol

Ctrl Type

M30

P24.11

TIN233

P24.11

I

A2 /

PU1 /

VEBU O0

TOUT233

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

DQ3 A3

HWOU T

L29

P24.12

TIN234

P24.12

I

A2 /

PU1 /

VEBU O0

TOUT234

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

DQ1 A1

HWOU T

L30

P24.13

TIN235

P24.13

I

A2 /

PU1 /

VEBU O0

TOUT235

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

DQ2 A2

HWOU T

Function General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU Data Bus Line (SDRAM) EBU output General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU Data Bus Line (SDRAM) EBU output General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU Data Bus Line (SDRAM) EBU output

Data Sheet

TOC-79

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-14 Port 24 Functions (cont'd)

Pin

Symbol

Ctrl Type

K29

P24.14

TIN236

P24.14

I

A2 /

PU1 /

VEBU O0

TOUT236

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

DQ0 A0

HWOU T

K30

P24.15

TIN237

P24.15

I

A2 /

PU1 /

VEBU O0

TOUT237

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

DQ7 A7

HWOU T

Function General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU Data Bus Line (SDRAM) EBU output General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU Data Bus Line (SDRAM) EBU output

Data Sheet

TOC-80

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-15 Port 25 Functions

Pin

Symbol

AG30 P25.0

TIN206

SDCLKI

P25.0

TOUT206

­

­

­

­

­

­

BFCLKO

SDCLKO

AF30 P25.1

TIN207

P25.1

TOUT207

­

­

­

­

­

­

RD

RAS

AF29 P25.2

TIN208

P25.2

TOUT208

­

­

­

­

­

­

RD/WR

WR

Ctrl Type

I

A2 /

PU1 /

VEBU

O0 O1 O2 O3 O4 O5 O6 O7 HWOU T

I

A2 /

PU1 /

VEBU O0

O1

O2

O3

O4

O5

O6

O7

HWOU T

I

A2 /

PU1 /

VEBU O0

O1

O2

O3

O4

O5

O6

O7

HWOU T

Function General-purpose input GTM input EBU input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU output EBU output General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU output EBU output General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU output EBU output

Data Sheet

TOC-81

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-15 Port 25 Functions (cont'd)

Pin

Symbol

Ctrl

AE30 P25.3

I

TIN209

HOLDA

P25.3

O0

TOUT209

O1

­

O2

­

O3

­

O4

­

O5

­

O6

BAABA0

O7

Type
A2 / PU1 / VEBU

AE29 AD30

CS2 DQM1 HOLDA P25.4 TIN210 P25.4 TOUT210 ­ ­ ­ ­ ­ ­ CS1 DQM0 P25.5 TIN211 P25.5 TOUT211 ­ ­ ­ ­ ­ ­ CS0

HWOU T

I

A2 /

PU1 /

VEBU O0

O1

O2

O3

O4

O5

O6

O7

HWOU T

I

A2 /

PU1 /

VEBU O0

O1

O2

O3

O4

O5

O6

O7

HWOU T

Function General-purpose input GTM input EBU input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved EBU output (combined for BAA and BA0) EBU output EBU output EBU output General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU output EBU output General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU output

Data Sheet

TOC-82

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-15 Port 25 Functions (cont'd)

Pin

Symbol

Ctrl Type

W29

P25.6 P25.6 TOUT212

I

A2 /

O0

PU1 /

VEBU O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

CKE

HWOU T

AD29

P25.7 TIN213 P25.7

I

A2 /

PU1 /

VEBU O0

TOUT213

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

ADV CAS

HWOU T

AC29

P25.8 TIN214 P25.8

I

A2 /

PU1 /

VEBU O0

TOUT214

O1

­

O2

­

O3

­

O4

A23

O5

SDRAMA0

O6

­

O7

BC0

HWOU

T

Function General-purpose input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU output
General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU output EBU output General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved EBU output EBU output Reserved EBU output

Data Sheet

TOC-83

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-15 Port 25 Functions (cont'd)

Pin

Symbol

Ctrl Type

AC30

P25.9 TIN215 P25.9

I

A2 /

PU1 /

VEBU O0

TOUT215

O1

­

O2

­

O3

­

O4

A22

O5

SDRAMA1

O6

­

O7

BC1

HWOU

T

AB29

P25.10 TIN216 P25.10

I

A2 /

PU1 /

VEBU O0

TOUT216

O1

­

O2

­

O3

­

O4

A21

O5

SDRAMA2

O6

­

O7

BC2

HWOU

T

AB30

P25.11 TIN217 P25.11

I

A2 /

PU1 /

VEBU O0

TOUT217

O1

­

O2

­

O3

­

O4

A20

O5

SDRAMA3

O6

­

O7

BC3

HWOU

T

Function General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved EBU output EBU output Reserved EBU output
General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved EBU output EBU output Reserved EBU output
General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved EBU output EBU output Reserved EBU output

Data Sheet

TOC-84

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-15 Port 25 Functions (cont'd)

Pin

Symbol

Ctrl Type

AA29

P25.12 TIN218 P25.12

I

A2 /

PU1 /

VEBU O0

TOUT218

O1

­

O2

­

O3

­

O4

­

O5

SDRAMA4

O6

­

O7

A19

HWOU

T

AA30

P25.13 TIN219 P25.13

I

A2 /

PU1 /

VEBU O0

TOUT219

O1

­

O2

­

O3

­

O4

­

O5

SDRAMA5

O6

­

O7

A17

HWOU

T

Y29

P25.14

TIN220

P25.14

I

A2 /

PU1 /

VEBU O0

TOUT220

O1

­

O2

­

O3

­

O4

­

O5

SDRAMA6

O6

­

O7

A18

HWOU

T

Function General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved EBU output Reserved EBU output
General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved EBU output Reserved EBU output
General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved EBU output Reserved EBU output

Data Sheet

TOC-85

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-15 Port 25 Functions (cont'd)

Pin

Symbol

Ctrl Type

Y30

P25.15

TIN221

P25.15

I

A2 /

PU1 /

VEBU O0

TOUT221

O1

­

O2

­

O3

­

O4

­

O5

SDRAMA7

O6

­

O7

A16

HWOU

T

Function General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved EBU output Reserved EBU output

Table 2-16 Port 26 Functions

Pin

Symbol

Ctrl Type

Function

AG29

P26.0 TIN212 BFCLKI

I

LP /

General-purpose input

PU1 /

GTM input

VFLEXE EBU input

P26.0

O0

General-purpose output

TOUT212

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

Data Sheet

TOC-86

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-17 Port 30 Functions

Pin

Symbol

AJ21

P30.0

TIN190

P30.0

TOUT190

­

­

­

­

­

­

AD14

AK21

P30.1 TIN191 P30.1 TOUT191 ­ ­ ­ ­ ­ ­ AD11

AJ22

P30.2 TIN192 P30.2 TOUT192 ­ ­ ­ ­ ­ ­ AD12

Ctrl Type

Function

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

O1

GTM output

O2

Reserved

O3

Reserved

O4

Reserved

O5

Reserved

O6

Reserved

O7

Reserved

HWOU T

EBU Address / Data Bus Line

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

O1

GTM output

O2

Reserved

O3

Reserved

O4

Reserved

O5

Reserved

O6

Reserved

O7

Reserved

HWOU T

EBU Address / Data Bus Line

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

O1

GTM output

O2

Reserved

O3

Reserved

O4

Reserved

O5

Reserved

O6

Reserved

O7

Reserved

HWOU T

EBU Address / Data Bus Line

Data Sheet

TOC-87

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-17 Port 30 Functions (cont'd)

Pin

Symbol

Ctrl Type

Function

AK22

P30.3 TIN193 P30.3

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT193

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD15

HWOU T

EBU Address / Data Bus Line

AJ23

P30.4 TIN194 P30.4

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT194

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD8

HWOU

EBU Address / Data Bus Line

T

AK23

P30.5 TIN195 P30.5

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT195

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD13

HWOU T

EBU Address / Data Bus Line

Data Sheet

TOC-88

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-17 Port 30 Functions (cont'd)

Pin

Symbol

Ctrl Type

Function

AJ24

P30.6 TIN196 P30.6

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT196

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD4

HWOU

EBU Address / Data Bus Line

T

AK24

P30.7 TIN197 P30.7

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT197

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD7

HWOU

EBU Address / Data Bus Line

T

AJ25

P30.8 TIN198 P30.8

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT198

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD3

HWOU

EBU Address / Data Bus Line

T

Data Sheet

TOC-89

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-17 Port 30 Functions (cont'd)

Pin

Symbol

Ctrl Type

Function

AK25

P30.9 TIN199 P30.9

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT199

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD0

HWOU

EBU Address / Data Bus Line

T

AJ26

P30.10 TIN200 P30.10

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT200

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD5

HWOU

EBU Address / Data Bus Line

T

AK26

P30.11 TIN201 P30.11

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT201

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD10

HWOU T

EBU Address / Data Bus Line

Data Sheet

TOC-90

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-17 Port 30 Functions (cont'd)

Pin

Symbol

Ctrl Type

Function

AJ27

P30.12 TIN202 P30.12

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT202

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD9

HWOU

EBU Address / Data Bus Line

T

AK27

P30.13 TIN203 P30.13

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT203

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD2

HWOU

EBU Address / Data Bus Line

T

AJ28

P30.14 TIN204 P30.14

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT204

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD1

HWOU

EBU Address / Data Bus Line

T

Data Sheet

TOC-91

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-17 Port 30 Functions (cont'd)

Pin

Symbol

Ctrl Type

Function

AK28

P30.15 TIN205 P30.15

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT205

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD6

HWOU

EBU Address / Data Bus Line

T

Table 2-18 Port 31 Functions

Pin

Symbol

AJ12

P31.0

TIN174

P31.0

TOUT174

­

­

­

­

­

­

AD30

AK12

P31.1 TIN175 P31.1 TOUT175 ­ ­ ­ ­ ­ ­ AD29

Ctrl Type

Function

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

O1

GTM output

O2

Reserved

O3

Reserved

O4

Reserved

O5

Reserved

O6

Reserved

O7

Reserved

HWOU T

EBU Address / Data Bus Line

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

O1

GTM output

O2

Reserved

O3

Reserved

O4

Reserved

O5

Reserved

O6

Reserved

O7

Reserved

HWOU T

EBU Address / Data Bus Line

Data Sheet

TOC-92

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-18 Port 31 Functions (cont'd)

Pin

Symbol

Ctrl Type

Function

AJ13

P31.2 TIN176 P31.2

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT176

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD28

HWOU T

EBU Address / Data Bus Line

AK13

P31.3 TIN177 P31.3

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT177

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD26

HWOU T

EBU Address / Data Bus Line

AJ14

P31.4 TIN178 P31.4

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT178

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD24

HWOU T

EBU Address / Data Bus Line

Data Sheet

TOC-93

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-18 Port 31 Functions (cont'd)

Pin

Symbol

Ctrl Type

Function

AK14

P31.5 TIN179 P31.5

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT179

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD23

HWOU T

EBU Address / Data Bus Line

AJ15

P31.6 TIN180 P31.6

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT180

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD20

HWOU T

EBU Address / Data Bus Line

AK15

P31.7 TIN181 P31.7

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT181

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD16

HWOU T

EBU Address / Data Bus Line

Data Sheet

TOC-94

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-18 Port 31 Functions (cont'd)

Pin

Symbol

Ctrl Type

Function

AJ16

P31.8 TIN182 P31.8

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT182

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD31

HWOU T

EBU Address / Data Bus Line

AK16

P31.9 TIN183 P31.9

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT183

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD27

HWOU T

EBU Address / Data Bus Line

AJ17

P31.10 TIN184 P31.10

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT184

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD21

HWOU T

EBU Address / Data Bus Line

Data Sheet

TOC-95

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-18 Port 31 Functions (cont'd)

Pin

Symbol

Ctrl Type

Function

AK17

P31.11 TIN185 P31.11

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT185

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD25

HWOU T

EBU Address / Data Bus Line

AJ18

P31.12 TIN186 P31.12

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT186

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD19

HWOU T

EBU Address / Data Bus Line

AK18

P31.13 TIN187 P31.13

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT187

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD22

HWOU T

EBU Address / Data Bus Line

Data Sheet

TOC-96

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-18 Port 31 Functions (cont'd)

Pin

Symbol

Ctrl Type

Function

AJ19

P31.14 TIN188 P31.14

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT188

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD18

HWOU T

EBU Address / Data Bus Line

AK19

P31.15 TIN189 P31.15

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT189

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD17

HWOU T

EBU Address / Data Bus Line

Data Sheet

TOC-97

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-19 Port 32 Functions

Pin

Symbol

Ctrl

AE22

P32.0

I

TIN36

FDEST

VGATE1N

Type
LP / PX/ VEXT

AE23 AE24

P32.0 TOUT36 ­ ­ ­ ­ ­ ­ P32.2 TIN38 ARX3D RXDCAN3B RXDCANr1D P32.2 TOUT38 ATX3 ­ ­ ­ DCDCSYNC ­ P32.3 TIN39 P32.3 TOUT39 ATX3 ­ ASCLK3 TXDCAN3 TXDCANr1 ­

O0

O1

O2

O3

O4

O5

O6

O7

I

LP /

PU1 /

VEXT

O0

O1

O2

O3

O4

O5

O6

O7

I

LP /

PU1 /

VEXT O0

O1

O2

O3

O4

O5

O6

O7

Function General-purpose input GTM input PMU input SMPS mode: analog output. External Pass Device gate control for EVR13 General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved General-purpose input GTM input ASCLIN3 input CAN node 3 input CAN node 1 input (MultiCANr+) General-purpose output GTM output ASCLIN3 output Reserved Reserved Reserved SCU output Reserved General-purpose input GTM input General-purpose output GTM output ASCLIN3 output Reserved ASCLIN3 output CAN node 3 output CAN node 1 output (MultiCANr+) Reserved

Data Sheet

TOC-98

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-19 Port 32 Functions (cont'd)

Pin

Symbol

Ctrl Type

AD23

P32.4 TIN40 ACTS1B

I

MP+ /

PU1 /

VEXT

SDI12

P32.4

O0

TOUT40

O1

­

O2

END12

O3

GTMCLK1

O4

EN10

O5

EXTCLK1

O6

COUT63

O7

AA20

P32.5 TIN140 P32.5

I

LP /

PU1 /

VEXT O0

TOUT140

O1

ATX2

O2

­

O3

­

O4

­

O5

TXDCAN2

O6

­

O7

AB20

P32.6 TGI4 TIN141

I

LP /

PU1 /

VEXT

RXDCAN2C

ARX2F

P32.6

O0

TOUT141

O1

­

O2

­

O3

SLSO212

O4

­

O5

­

O6

­

O7

TGO4

HWOU T

Function General-purpose input GTM input ASCLIN1 input MSC1 input General-purpose output GTM output Reserved MSC1 output GTM output MSC1 output SCU output CCU60 output General-purpose input GTM input General-purpose output GTM output ASCLIN2 output Reserved Reserved Reserved CAN node 2 output Reserved General-purpose input OCDS input GTM input CAN node 2 input ASCLIN2 input General-purpose output GTM output Reserved Reserved QSPI2 output Reserved Reserved Reserved OCDS; ENx

Data Sheet

TOC-99

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-19 Port 32 Functions (cont'd)

Pin

Symbol

Ctrl Type

AB21

P32.7 TIN142 TGI5

I

LP /

PU1 /

VEXT

P32.7

O0

TOUT142

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

TGO5

HWOU T

Function General-purpose input GTM input OCDS input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved OCDS; ENx

Table 2-20 Port 33 Functions

Pin

Symbol

Ctrl

AD15

P33.0

I

TIN22

DSITR0E

P33.0

O0

TOUT22

O1

­

O2

­

O3

­

O4

­

O5

VADCG2BFL0

O6

­

O7

Type
LP / PU1 / VEXT

Function General-purpose input GTM input DSADC channel 0 input E General-purpose output GTM output Reserved Reserved Reserved Reserved VADC output Reserved

Data Sheet

TOC-100

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-20 Port 33 Functions (cont'd)

Pin

Symbol

Ctrl

AE15

P33.1

I

TIN23

PSIRX0C

SENT9C

DSCIN2B

DSITR1E

P33.1

O0

TOUT23

O1

ASLSO3

O2

SCLK2

O3

DSCOUT2

O4

VADCEMUX02

O5

VADCG2BFL1

O6

­

O7

AD16

P33.2

I

TIN24

SENT8C

DSDIN2B

DSITR2E

P33.2

O0

TOUT24

O1

ASCLK3

O2

SLSO210

O3

PSITX0

O4

VADCEMUX01

O5

VADCG2BFL2

O6

­

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input PSI5 input SENT input DSADC channel 2 input B DSADC channel 1 input E General-purpose output GTM output ASCLIN3 output QSPI2 output DSADC channel 2 output VADC output VADC output Reserved General-purpose input GTM input SENT input DSADC channel 2 input B DSADC channel 2 input E General-purpose output GTM output ASCLIN3 output QSPI2 output PSI5 output VADC output VADC output Reserved

Data Sheet

TOC-101

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-20 Port 33 Functions (cont'd)

Pin

Symbol

Ctrl

AE16

P33.3

I

TIN25

PSIRX1C

SENT7C

DSCIN1B

P33.3

O0

TOUT25

O1

­

O2

­

O3

DSCOUT1

O4

VADCEMUX00

O5

VADCG2BFL3

O6

­

O7

AD17

P33.4

I

TIN26

SENT6C

CTRAPC

DSDIN1B

DSITR0F

P33.4

O0

TOUT26

O1

ARTS2

O2

SLSO212

O3

PSITX1

O4

VADCEMUX12

O5

VADCG0BFL0

O6

­

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input PSI5 input SENT input DSADC channel 1 input B General-purpose output GTM output Reserved Reserved DSADC channel 1 output VADC output VADC output Reserved General-purpose input GTM input SENT input CCU61 input DSADC channel 1 input DSADC channel 0 input F General-purpose output GTM output ASCLIN2 output QSPI2 output PSI5 output VADC output VADC output Reserved

Data Sheet

TOC-102

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-20 Port 33 Functions (cont'd)

Pin

Symbol

Ctrl

AE17

P33.5

I

TIN27

ACTS2B

PSIRX2C

PSISRXC

SENT5C

CCPOS2C

T4EUDB

DSCIN0B

DSITR1F

P33.5

O0

TOUT27

O1

SLSO07

O2

SLSO17

O3

DSCOUT0

O4

VADCEMUX11

O5

VADCG0BFL1

O6

­

O7

AD18

P33.6

I

TIN28

SENT4C

CCPOS1C

T2EUDB

DSDIN0B

DSITR2F

P33.6

O0

TOUT28

O1

ASLSO2

O2

SLSO211

O3

PSITX2

O4

VADCEMUX10

O5

VADCG1BFL0

O6

PSISTX

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input ASCLIN2 input PSI5 input PSI5-S input SENT input CCU61 input GPT120 input DSADC channel 0 input B DSADC channel 1 input F General-purpose output GTM output QSPI0 output QSPI1 output DSADC channel 0 output VADC output VADC output Reserved General-purpose input GTM input SENT input CCU61 input GPT120 input DSADC channel 0 input B DSADC channel 2 input F General-purpose output GTM output ASCLIN2 output QSPI2 output PSI5 output VADC output VADC output PSI5-S output

Data Sheet

TOC-103

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-20 Port 33 Functions (cont'd)

Pin

Symbol

Ctrl Type

AE18

P33.7 TIN29 RXDCAN0E

I

LP /

PU1 /

VEXT

REQ8

CCPOS0C

T2INB

P33.7

O0

TOUT29

O1

ASCLK2

O2

SLSO47

O3

­

O4

­

O5

VADCG1BFL1

O6

­

O7

AD19

P33.8 TIN30 ARX2E

I

MP /

HighZ /

VEXT

EMGSTOPA

P33.8

O0

TOUT30

O1

ATX2

O2

SLSO42

O3

­

O4

TXDCAN0

O5

­

O6

COUT62

O7

SMUFSP

HWOU T

AE19

P33.9 TIN31 HSIC3INA

I

LP /

PU1 /

VEXT

P33.9

O0

TOUT31

O1

ATX2

O2

SLSO41

O3

ASCLK2

O4

­

O5

­

O6

CC62

O7

Function General-purpose input GTM input CAN node 0 input SCU input CCU61 input GPT120 input General-purpose output GTM output ASCLIN2 output QSPI4 output Reserved Reserved VADC output Reserved General-purpose input GTM input ASCLIN2 input SCU input General-purpose output GTM output ASCLIN2 output QSPI4 output Reserved CAN node 0 output Reserved CCU61 output SMU
General-purpose input GTM input QSPI3 input General-purpose output GTM output ASCLIN2 output QSPI4 output ASCLIN2 output Reserved Reserved CCU61 output

Data Sheet

TOC-104

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-20 Port 33 Functions (cont'd)

Pin

Symbol

Ctrl

AD20

P33.10

I

TIN32

SLSI4A

HSIC3INB

P33.10

O0

TOUT32

O1

SLSO16

O2

SLSO40

O3

ASLSO1

O4

PSISCLK

O5

­

O6

COUT61

O7

AE20

P33.11

I

TIN33

SCLK4A

P33.11

O0

TOUT33

O1

ASCLK1

O2

SCLK4

O3

­

O4

­

O5

DSCGPWMN

O6

CC61

O7

AD21

P33.12

I

TIN34

MTSR4A

P33.12

O0

TOUT34

O1

ATX1

O2

MTSR4

O3

ASCLK1

O4

­

O5

DSCGPWMP

O6

COUT60

O7

Type MP / PU1 / VEXT
MP / PU1 / VEXT
MP / PU1 / VEXT

Function General-purpose input GTM input QSPI4 input QSPI3 input General-purpose output GTM output QSPI1 output QSPI4 output ASCLIN1 output PSI5-S output Reserved CCU61 output General-purpose input GTM input QSPI4 input General-purpose output GTM output ASCLIN1 output QSPI4 output Reserved Reserved DSADC channel output CCU61 output General-purpose input GTM input QSPI4 input General-purpose output GTM output ASCLIN1 output QSPI4 output ASCLIN1 output Reserved DSADC output CCU61 output

Data Sheet

TOC-105

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-20 Port 33 Functions (cont'd)

Pin

Symbol

Ctrl Type

AE21

P33.13 TIN35 ARX1F

I

MP /

PU1 /

VEXT

MRST4A

DSSGNB

INJ11

P33.13

O0

TOUT35

O1

ATX1

O2

MRST4

O3

SLSO26

O4

­

O5

DCDCSYNC

O6

CC60

O7

AA19

P33.14 TIN143 TGI6

I

LP /

PU1 /

VEXT

SCLK2D

P33.14

O0

TOUT143

O1

­

O2

SCLK2

O3

­

O4

­

O5

­

O6

CC62

O7

TGO6

HWOU T

Function General-purpose input GTM input ASCLIN1 input QSPI4 input DSADC channel input B MSC1 input General-purpose output GTM output ASCLIN1 output QSPI4 output QSPI2 output Reserved SCU output CCU61 output General-purpose input GTM input OCDS input QSPI2 input General-purpose output GTM output Reserved QSPI2 output Reserved Reserved Reserved CCU60 output OCDS; ENx

Data Sheet

TOC-106

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-20 Port 33 Functions (cont'd)

Pin

Symbol

Ctrl Type

AB19

P33.15 TIN144 TGI7

I

LP /

PU1 /

VEXT

P33.15

O0

TOUT144

O1

­

O2

SLSO211

O3

­

O4

­

O5

­

O6

COUT62

O7

TGO7

HWOU T

Function General-purpose input GTM input OCDS input General-purpose output GTM output Reserved QSPI2 output Reserved Reserved Reserved CCU60 output OCDS; ENx

Table 2-21 Port 34 Functions

Pin

Symbol

Ctrl

AB16

P34.1

I

TIN146

P34.1

O0

TOUT146

O1

ATX0

O2

­

O3

TXDCAN0

O4

TXDCANr0

O5

­

O6

COUT63

O7

AA17

P34.2

I

TIN147

ARX0D

RXDCAN0G

RXDCANr0C

P34.2

O0

TOUT147

O1

­

O2

­

O3

­

O4

­

O5

­

O6

CC60

O7

Data Sheet

Type LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input General-purpose output GTM output ASCLIN0 output Reserved CAN node 0 output CAN node 0 output (MultiCANr+) Reserved CCU60 output General-purpose input GTM input ASCLIN0 input CAN node 0 input CAN node 0 input (MultiCANr+) General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved CCU60 output

TOC-107

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-21 Port 34 Functions (cont'd)

Pin

Symbol

Ctrl

AB17

P34.3

I

TIN148

P34.3

O0

TOUT148

O1

­

O2

­

O3

SLSO210

O4

­

O5

­

O6

COUT60

O7

AA18

P34.4

I

TIN149

MRST2D

P34.4

O0

TOUT149

O1

­

O2

­

O3

MRST2

O4

­

O5

­

O6

CC61

O7

AB18

P34.5

I

TIN150

MTSR2D

P34.5

O0

TOUT150

O1

­

O2

­

O3

MTSR2

O4

­

O5

­

O6

COUT61

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input General-purpose output GTM output Reserved Reserved QSPI2 output Reserved Reserved CCU60 output General-purpose input GTM input QSPI2 input General-purpose output GTM output Reserved Reserved QSPI2 output Reserved Reserved CCU60 output General-purpose input GTM input QSPI2 input General-purpose output GTM output Reserved Reserved QSPI2 output Reserved Reserved CCU60 output

Data Sheet

TOC-108

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-22 Port 40 Functions

Pin

Symbol

Ctrl

AD7

P40.0

I

VADCG3.0

DS2PB

CCPOS0D

SENT0A

AD6

P40.1

I

VADCG3.1

DS2NB

CCPOS1B

SENT1A

AC7

P40.2

I

VADCG3.2

CCPOS1D

SENT2A

AC6

P40.3

I

VADCG3.3

CCPOS2B

SENT3A

W9

P40.4

I

VADCG4.0

CCPOS2D

SENT4A

Y6

P40.5

I

VADCG4.1

CCPOS0D

SENT5A

V9

P40.6

I

VADCG4.4

DS3PA

CCPOS1B

SENT6A

Type S / HighZ / VDDM
S / HighZ / VDDM
S / HighZ / VDDM
S / HighZ / VDDM
S / HighZ / VDDM
S / HighZ / VDDM
S / HighZ / VDDM

Function General-purpose input VADC analog input channel 0 of group 3 DSADC: positive analog input of channel 2, pin B CCU60 input SENT input General-purpose inpu.t VADC analog input channel 1 of group 3 (with pull down diagnostics) DSADC: negative analog input channel 2, pin B CCU60 input SENT input General-purpose inpu.t VADC analog input channel 2 of group 3 (with pull down diagnostics) CCU60 input SENT input General-purpose input VADC analog input channel 3 of group 3 (with pull down diagnostics) CCU60 input SENT input General-purpose input VADC analog input channel 0 of group 4 CCU60 input SENT input General-purpose input VADC analog input channel 1 of group 4 CCU61 input SENT input General-purpose input VADC analog input channel 4 of group 4 DSADC: positive analog input of channel 3, pin A CCU61 input SENT input

Data Sheet

TOC-109

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-22 Port 40 Functions (cont'd)

Pin

Symbol

Ctrl

W7

P40.7

I

VADCG4.5

DS3NA

CCPOS1D

SENT7A

V10

P40.8

I

VADCG4.6

DS3PB

CCPOS2B

SENT8A

W6

P40.9

I

VADCG4.7

DS3NB

CCPOS2D

SENT9A

AA1

P40.10

I

VADCG10.3

DS8NB

SENT10A

Y1

P40.11

I

VADCG10.4

DS8PA

SENT11A

Y2

P40.12

I

VADCG10.5

DS8NA

SENT12A

W1

P40.13

I

VADCG10.6

DS9PA

SENT13A

W2

P40.14

I

VADCG10.7

DS9NA

SENT14A

Type S / HighZ / VDDM
S / HighZ / VDDM
S / HighZ / VDDM
S / HighZ / VDDM
S / HighZ / VDDM
S / HighZ / VDDM
S / HighZ / VDDM
S / HighZ / VDDM

Function General-purpose input VADC analog input channel 5 of group 4 DSADC: negative analog input channel 3, pin A CCU61 input SENT input General-purpose input VADC analog input channel 6 of group 4 DSADC: positive analog input of channel 3, pin B CCU61 input SENT input General-purpose input VADC analog input channel 7 of group 4 DSADC: negative analog input channel 3, pin B CCU61 input SENT input General-purpose input VADC analog input channel 3 of group 10 DSADC: negative analog input channel 8, pin B SENT input General-purpose input VADC analog input channel 4 of group 10 DSADC: positive analog input of channel 8, pin A SENT input General-purpose input VADC analog input channel 5 of group 10 DSADC: positive analog input of channel 8, pin A SENT input General-purpose input VADC analog input channel 6 of group 10 DSADC: positive analog input of channel 9, pin A SENT input General-purpose input VADC analog input channel 7 of group 10 DSADC: positive analog input of channel 9, pin A SENT input

Data Sheet

TOC-110

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-23 Analog Inputs

Pin

Symbol

AA15

AN0

VADCG0.0

DS1PA

AB15

AN1

VADCG0.1

DS1NA

AD14

AN2

VADCG0.2

DS0PA

AB14

AN3

VADCG0.3

DS0NA

AA14

AN4

VADCG0.4

AE14

AN5

VADCG0.5

AA13

AN6

VADCG0.6

AB13

AN7

VADCG0.7

AD13 AB12 AE13 AD12

AN8 VADCG1.0 AN9 VADCG1.1 AN10 VADCG1.2 AN11 VADCG1.3

AA12 AD11 AB11 AA11

AN12 VADCG1.4 AN13 VADCG1.5 AN14 VADCG1.6 AN15 VADCG1.7

Data Sheet

Ctrl Type

Function

I

D / HighZ / Analog input 0

VDDM

VADC analog input channel 0 of group 0

DSADC: positive analog input of channel 1, pin A

I

D / HighZ / Analog input 1

VDDM

VADC analog input channel 1 of group 0

DSADC: negative analog input channel 1, pin A

I

D / HighZ / Analog input 2

VDDM

VADC analog input channel 2 of group 0

DSADC: positive analog input of channel 0, pin A

I

D / HighZ / Analog input 3

VDDM

VADC analog input channel 3 of group 0

DSADC: negative analog input channel 0, pin A

I

D / HighZ / Analog input 4

VDDM

VADC analog input channel 4 of group 0

I

D / HighZ / Analog input 5

VDDM

VADC analog input channel 5 of group 0

I

D / HighZ / Analog input 6

VDDM

VADC analog input channel 6 of group 0

I

D / HighZ / Analog input 7

VDDM

VADC analog input channel 7 of group 0 (with pull

down diagnostics)

I

D / HighZ / Analog input 8

VDDM

VADC analog input channel 0 of group 1

I

D / HighZ / Analog input 9

VDDM

VADC analog input channel 1 of group 1

I

D / HighZ / Analog input 10

VDDM

VADC analog input channel 2 of group 1

I

D / HighZ / Analog input 11

VDDM

VADC analog input channel 3 of group 1 (with pull

down diagnostics)

I

D / HighZ / Analog input 12

VDDM

VADC analog input channel 4 of group 1

I

D / HighZ / Analog input 13

VDDM

VADC analog input channel 5 of group 1

I

D / HighZ / Analog input 14

VDDM

VADC analog input channel 6 of group 1

I

D / HighZ / Analog input 15

VDDM

VADC analog input channel 7 of group 1

TOC-111

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-23 Analog Inputs (cont'd)

Pin

Symbol

Ctrl

AD10

AN16

I

VADCG2.0

AB10

AN17

I

VADCG2.1

AD9

AN18

I

VADCG2.2

AD8

AN19

I

VADCG2.3

AE8

AN20

I

VADCG2.4

DS2PA

AE7

AN21

I

VADCG2.5

DS2NA

AA10

AN22

I

VADCG2.6

Y10

AN23

I

VADCG2.7

AD7

AN24

I

VADCG3.0

DS2PB

SENT0A

AD6

AN25

I

VADCG3.1

DS2NB

SENT1A

AC7

AN26

I

VADCG3.2

SENT2A

AC6

AN27

I

VADCG3.3

SENT3A

AB7

AN28

I

VADCG3.4

Type

Function

D / HighZ / Analog input 16

VDDM

VADC analog input channel 0 of group 2

D / HighZ / Analog input 17

VDDM

VADC analog input channel 1 of group 2

D / HighZ / Analog input 18

VDDM

VADC analog input channel 2 of group 2

D / HighZ / Analog input 19

VDDM

VADC analog input channel 3 of group 2 (with pull

down diagnostics)

D / HighZ / Analog input 20

VDDM

VADC analog input channel 4 of group 2

DSADC: positive analog input of channel 2, pin A

D / HighZ / Analog input 21

VDDM

VADC analog input channel 5 of group 2

DSADC: negative analog input channel 2, pin A

D / HighZ / Analog input 22

VDDM

VADC analog input channel 6 of group 2

D / HighZ / Analog input 23

VDDM

VADC analog input channel 7 of group 2

S / HighZ / VDDM

Analog input 24 VADC analog input channel 0 of group 3 DSADC: positive analog input of channel 2, pin B

SENT input channel 0, pin A

S / HighZ / VDDM

Analog input 24
VADC analog input channel 1 of group 3 (with pull down diagnostics)

DSADC: negative analog input channel 2, pin B

SENT input channel 1, pin A

S / HighZ / VDDM

Analog input 26
VADC analog input channel 2 of group 3 (with pull down diagnostics)

SENT input channel 2, pin A

S / HighZ / VDDM

Analog input 27
VADC analog input channel 3 of group 3 (with pull down diagnostics)

SENT input channel 3, pin A

D / HighZ / Analog input 28

VDDM

VADC analog input channel 4 of group 3 (with pull

down diagnostics)

Data Sheet

TOC-112

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-23 Analog Inputs (cont'd)

Pin

Symbol

Ctrl

AB6

AN29

I

VADCG3.5

AA9

AN30

I

VADCG3.6

Y9

AN31

I

VADCG3.7

W9

AN32

I

VADCG4.0

SENT4A

Y6

AN33

I

VADCG4.1

SENT5A

W10

AN34

I

VADCG4.2

Y7

AN35

I

VADCG4.3

V9

AN36

I

VADCG4.4

DS3PA

SENT6A

W7

AN37

I

VADCG4.5

DS3NA

SENT7A

V10

AN38

I

VADCG4.6

DS3PB

SENT8A

W6

AN39

I

VADCG4.7

DS3NB

SENT9A

U10

AN40

I

VADCG5.0

U9

AN41

I

VADCG5.1

Type

Function

D / HighZ / Analog input 29

VDDM

VADC analog input channel 5 of group 3 (with pull

down diagnostics)

D / HighZ / Analog input 30

VDDM

VADC analog input channel 6 of group 3

D / HighZ / Analog input 31

VDDM

VADC analog input channel 7 of group 3

S / HighZ / VDDM

Analog input 32 VADC analog input channel 0 of group 4 SENT input channel 4, pin A

S / HighZ / VDDM

Analog input 33 VADC analog input channel 1 of group 4 SENT input channel 5, pin A

D / HighZ / Analog input 34

VDDM

VADC analog input channel 2 of group 4

D / HighZ / Analog input 35

VDDM

VADC analog input channel 3 of group 4 (with pull

down diagnostics)

S / HighZ / VDDM

Analog input 34 VADC analog input channel 4 of group 4 DSADC: positive analog input of channel 3, pin A

SENT input channel 6, pin A

S / HighZ / VDDM

Analog input 37 VADC analog input channel 5 of group 4 DSADC: negative analog input channel 3, pin A

SENT input channel 7, pin A

S / HighZ / VDDM

Analog input 38 VADC analog input channel 6 of group 4 DSADC: positive analog input of channel 3, pin B

SENT input channel 8, pin A

S / HighZ / VDDM

Analog input 39 VADC analog input channel 7 of group 4 DSADC: negative analog input channel 3, pin B

SENT input channel 9, pin A

D / HighZ / Analog input 40

VDDM

VADC analog input channel 0 of group 5

D / HighZ / Analog input 41

VDDM

VADC analog input channel 1 of group 5

Data Sheet

TOC-113

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-23 Analog Inputs (cont'd)

Pin

Symbol

Ctrl

T10

AN42

I

VADCG5.2

T9

AN43

I

VADCG5.3

V6

AN44

I

VADCG5.4

DS3PC

V7

AN45

I

VADCG5.5

DS3NC

U6

AN46

I

VADCG5.6

DS3PD

U7

AN47

I

VADCG5.7

DS3ND

AK7

AN48

I

VADCG8.0

AJ7

AN49

I

VADCG8.1

AJ6

AN50

I

VADCG8.2

AK6

AN51

I

VADCG8.3

AJ5

AN52

I

VADCG8.4

DS6PA

AK5

AN53

I

VADCG8.5

DS6NA

AJ4

AN54

I

VADCG8.6

DS6PB

AK4

AN55

I

VADCG8.7

DS6NB

AF1

AN56

I

VADCG9.0

Data Sheet

Type

Function

D / HighZ / Analog input 42

VDDM

VADC analog input channel 2 of group 5

D / HighZ / Analog input 43

VDDM

VADC analog input channel 3 of group 5 (with pull

down diagnostics)

D / HighZ / Analog input 44

VDDM

VADC analog input channel 4 of group 5

DSADC: positive analog input of channel 3, pin C

D / HighZ / Analog input 45

VDDM

VADC analog input channel 5 of group 5

DSADC: negative analog input channel 3, pin C

D / HighZ / Analog input 46

VDDM

VADC analog input channel 6 of group 5

DSADC: positive analog input of channel 3, pin D

D / HighZ / Analog input 47

VDDM

VADC analog input channel 7 of group 5

DSADC: negative analog input channel 3, pin D

D / HighZ / Analog input 48

VDDM

VADC analog input channel 0 of group 8

D / HighZ / Analog input 49

VDDM

VADC analog input channel 1 of group 8 (muxtest)

D / HighZ / Analog input 50

VDDM

VADC analog input channel 2 of group 8 (muxtest)

D / HighZ / Analog input 51

VDDM

VADC analog input channel 3 of group 8

D / HighZ / Analog input 52

VDDM

VADC analog input channel 4 of group 8

DSADC: positive analog input of channel 6, pin A

D / HighZ / Analog input 53

VDDM

VADC analog input channel 5 of group 8

DSADC: negative analog input channel 6, pin A

D / HighZ / Analog input 5

VDDM

VADC analog input channel 6 of group 8

DSADC: positive analog input of channel 6, pin B

D / HighZ / Analog input 50

VDDM

VADC analog input channel 7 of group 8

DSADC: negative analog input channel 6, pin B

D / HighZ / Analog input 56

VDDM

VADC analog input channel 0 of group 9

TOC-114

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-23 Analog Inputs (cont'd)

Pin

Symbol

Ctrl

AF2

AN57

I

VADCG9.1

AE2

AN58

I

VADCG9.2

AE1

AN59

I

VADCG9.3

AD1

AN60

I

VADCG9.4

DS7PA

AD2

AN61

I

VADCG9.5

DS7NA

AC2

AN62

I

VADCG9.6

DS7PB

AC1

AN63

I

VADCG9.7

DS7NB

AB2

AN64

I

VADCG10.0

AB1

AN65

I

VADCG10.1

AA2

AN66

I

VADCG10.2

DS8PB

AA1

AN67

I

VADCG10.3

DS8NB

SENT10A

Y1

AN68

I

VADCG10.4

DS8PA

SENT11A

Y2

AN69

I

VADCG10.5

DS8NA

SENT12A

Type

Function

D / HighZ / Analog input 57

VDDM

VADC analog input channel 1 of group 9 (muxtest)

D / HighZ / Analog input 58

VDDM

VADC analog input channel 2 of group 9 (muxtest)

D / HighZ / Analog input 59

VDDM

VADC analog input channel 3 of group 9

D / HighZ / Analog input 60

VDDM

VADC analog input channel 4 of group 9

DSADC: positive analog input of channel 7, pin A

D / HighZ / Analog input 61

VDDM

VADC analog input channel 5 of group 9

DSADC: negative analog input channel 7, pin A

D / HighZ / Analog input 62

VDDM

VADC analog input channel 6 of group 9

DSADC: positive analog input of channel 7, pin B

D / HighZ / Analog input 63

VDDM

VADC analog input channel 7 of group 9

DSADC: negative analog input channel 7, pin B

D / HighZ / Analog input 64

VDDM

VADC analog input channel 0 of group 10

D / HighZ / Analog input 65

VDDM

VADC analog input channel 1 of group 10 (muxtest)

D / HighZ / Analog input 66

VDDM

VADC analog input channel 2 of group 10 (muxtest)

DSADC: positive analog input of channel 8, pin B

S / HighZ / VDDM

Analog input 67 VADC analog input channel 3 of group 10 DSADC: negative analog input channel 8, pin B

SENT input channel 10, pin A

S / HighZ / VDDM

Analog input 68 VADC analog input channel 4 of group 10 DSADC: positive analog input of channel 8, pin A

SENT input channel 11, pin A

S / HighZ / VDDM

Analog input 69 VADC analog input channel 5 of group 10 DSADC: negative analog input channel 8, pin A

SENT input channel 12, pin A

Data Sheet

TOC-115

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-23 Analog Inputs (cont'd)

Pin

Symbol

Ctrl

W1

AN70

I

VADCG10.6

DS9PA

SENT13A

W2

AN71

I

VADCG10.7

DS9NA

SENT14A

Type S / HighZ / VDDM
S / HighZ / VDDM

Function Analog input 70 VADC analog input channel 6 of group 10 DSADC: positive analog input of channel 9, pin A SENT input channel 13, pin A Analog input 71 VADC analog input channel 7 of group 10 DSADC: negative analog input channel 9, pin A SENT input channel 14, pin A

Table 2-24 System I/O

Pin

Symbol

M22

PORST

L21

ESR0

EVRWUP

M21

ESR1

AD22

EVRWUP VGATE1P

AJ20

VGATE3P

R21

TMS

DAP1

T24

TRST

Ctrl Type

Function

I

PORST / Power On Reset Input

PD /

Additional strong PD in case of power fail.

VEXT

I/O

MP /

OD /

VEXT

External System Request Reset 0 Default configuration during and after reset is opendrain driver. The driver drives low during power-on reset. This is valid additionally after deactivation of PORST until the internal reset phase has finished. See also SCU chapter for details. Default after power-on can be different. See also SCU chapter ´Reset Control Unit´ and SCU_IOCR register description.

I

EVR Wakeup Pin

I/O

MP /

PU1 /

VEXT

External System Request Reset 1 Default NMI function. See also SCU chapter ´Reset Control Unit´ and SCU_IOCR register description.

I

EVR Wakeup Pin

O

VGATE1P / External Pass Device gate control for EVR13

- /

VEXT

O

VGATE3P / External Pass Device gate control for EVR33

- /

VEXT

I

A2 /

JTAG Module State Machine Control Input

I/O

PD /

Device Access Port Line 1

VDDP3

I

A2 /

JTAG Module Reset/Enable Input

PD /

VDDP3

Data Sheet

TOC-116

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-24 System I/O (cont'd)

Pin

Symbol

Ctrl

P21

TCK

I

DAP0

I

U25

XTAL1

I

U24

XTAL2

O

Type
A2 / PD / VDDP3
XTAL1 / - / VDDP3
XTAL2 / - / VDDP3

Function JTAG Module Clock Input Device Access Port Line 0 Main Oscillator/PLL/Clock Generator Input
Main Oscillator/PLL/Clock Generator Output

Table 2-25 Supply

Pin

Symbol

Ctrl Type Function

AE11

VAREF1

I

Vx

Positive Analog Reference Voltage 1

AE12

VAGND1

I

Vx

Negative Analog Reference Voltage 1

AA6

VAREF2

I

Vx

Positive Analog Reference Voltage 2

AA7

VAGND2

I

Vx

Negative Analog Reference Voltage 2

AE10, AJ9, AK9

VDDM

I

Vx

ADC Analog Power Supply (3.3V / 5V)

N12, M13

VDD / VDDSB I

Vx

Emulation Device: Emulation SRAM

Standby Power Supply (1.3V) (Emulation

Device only).

Production Device: VDD (1.3V).

M18, N19, V12, V19, W13, W18

VDD

I

Vx

Digital Core Power Supply (1.3V)

V24

VDD

I

Vx

Digital Core Power Supply (1.3V).

The supply pin inturn supplies the main

XTAL Oscillator/PLL (1.3V) . A higher

decoupling capacitor is therefore

recommended to the VSS pin for better

noise immunity.

A2, B3, F7, G8, AC24, AD25, VEXT AH29, AJ30

I

Vx

External Power Supply (5V / 3.3V)

A29, B28, F24, G23

VDDP3

I

Vx

Digital Power Supply for Flash (3.3V).

Can be also used as external 3.3V Power

Supply for VFLEX.

V25

VDDP3

I

Vx

Digital Power Supply for Oscillator,

LVDSH and A2 pads (3.3V).

The supply pin inturn supplies the main

XTAL Oscillator/PLL (3.3V) . A higher

decoupling capacitor is therefore

recommended to the VSS pin for better

noise immunity.

K20, J21

VDDFL3

I

Vx

Flash Power Supply (3.3V)

J10

VFLEX

I

Vx

Digital Power Supply for Flex Port Pads

(5V / 3.3V)

Data Sheet

TOC-117

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-25 Supply (cont'd) Pin AJ11, AK11, AK20, AK29

Symbol VFLEXE

J29,J30, AH30
AK8, AJ8, AE9 AA16

VEBU
VSSM VEVRSB

A30, B2, B29, B30, F25, G7, VSS G24, H29, H30, J9, J22, K10, K21, T25, AA21, AB22, AD24, AE25, AJ10, AJ29, AK10, AK30

W14, W17, V14, V15, V16, V17

VSS

U12, U13, U15, U16, U18, U19 VSS

T13, T14, T15, T16, T17, T18 VSS

R13, R14, R15, R16, R17, R18 VSS

P12, P13, P15, P16, P18, P19 VSS

M14, M15, M16, M17, N14, N15, N16, N17

VSS

W15

VSS

W16

VSS

T12

VSS

R12

VSS

T19

VSS

Ctrl Type Function

I

Vx

Digital Power Supply for EBU Flex Port

Pads

(5V / 3.3V)

I

Vx

Digital Power Supply for EBU

(3.3V)

I

Vx

Analog Ground for VDDM

I

Vx

Standby Power Supply (3.3V/5V) for the

Standby SRAM (CPU0.DSPR).

If Standby mode is not used: To be

handled like VEXT (3.3V/5V).

I

Vx

Digital Ground (outer balls)

I

Vx

Digital Ground (center balls)

I

Vx

Digital Ground (center balls)

I

Vx

Digital Ground (center balls)

I

Vx

Digital Ground (center balls)

I

Vx

Digital Ground (center balls)

I

Vx

Digital Ground (center balls)

I

Vx

Digital Ground (center balls)

This ball is used in the Emulation Device

as

AGBT TX0N

I

Vx

Digital Ground (center balls)

This ball is used in the Emulation Device

as

AGBT TX0P

I

Vx

Digital Ground (center balls)

This ball is used in the Emulation Device

as

AGBT CLKN

I

Vx

Digital Ground (center balls)

This ball is used in the Emulation Device

as

AGBT CLKP

I

Vx

Digital Ground (center balls)

This ball is used in the Emulation Device

as

AGBT ERR

Data Sheet

TOC-118

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:

Table 2-25 Supply (cont'd)

Pin

Symbol

Ctrl Type Function

AK2, AK3, AJ1, AJ2, AJ3, NC AH1, AH2, AG1, AG2, W30, V1, V2, V29, V30, T1, R1, R2, J1, H1, H2, G29, G30, F29, F30, E1, E2, E29, E30, D1, D2, D29, D30, C1, C2, C29, C30 B1, B4, B6, B9, B10, B14, B17, B20, B21, B25, B26, B27, A3, A4, A8, A9, A10, A17, A21, A25, A26, A27, A28

I

NC

Not Connected. These pins are reserved

for future extensions and shall not be

connected externally.

R19

NC / VDDPSB I

NCVDD Emulation Device: Power Supply (3.3V)

PSB for DAP/JTAG pad group. Can be

connected to VDDP or can be left

unsupplied (see document ´AurixED´ /

Aurix Emulation Devices specification.

A1, F6, AK1, AE6, AB9

NC

Production Device: This pin is not connected on package level. It can be connected on PCB level to VDDP or Ground or can be left unsupplied.

I

NC1 Not Connected.

These pins are not connected on

package level and will not be used for

future extensions.

Legend:
Column "Ctrl.":
I = Input (for GPIO port Lines with IOCR bit field Selection PCx = 0XXXB)
O = Output O0 = Output with IOCR bit field selection PCx = 1X000B O1 = Output with IOCR bit field selection PCx = 1X001B (ALT1) O2 = Output with IOCR bit field selection PCx = 1X010B (ALT2) O3 = Output with IOCR bit field selection PCx = 1X011B (ALT3) O4 = Output with IOCR bit field selection PCx = 1X100B (ALT4) O5 = Output with IOCR bit field selection PCx = 1X101B (ALT5) O6 = Output with IOCR bit field selection PCx = 1X110B (ALT6) O7 = Output with IOCR bit field selection PCx = 1X111B (ALT7)
Column "Type":
LP = Pad class LP (5V/3.3V, Class LP parameters for digital input / output and class D parameters for analog input function) MP = Pad class MP (5V/3.3V) MP+ = Pad class MP+ (5V/3.3V) MPR = Pad class MPR (5V/3.3V) A2 = Pad class A2 (3.3V)

Data Sheet

TOC-119

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC299x Pin Definition and Functions:
LVDSM = Pad class LVDSM (5V/3.3V) LVDSH = Pad class LVDSH (3.3V) S = Pad class S (Class S parameters for digital input and class D parameters for analog input function) D = Pad class D (VADC / DSADC) PU = with pull-up device connected during reset (PORST = 0) PU1 = with pull-up device connected during reset (PORST = 0)1) 2) 3) PD = with pull-down device connected during reset (PORST = 0) PD1 = with pull-down device connected during reset (PORST = 0)1) 2) 3) PX = Behavior depends on usage: PD in EVR13 SMPS Mode and PU1 in GPIO Mode OD = open drain during reset (PORST = 0) HighZ = tri-state during reset (PORST = 0) PORST = PORST input pad XTAL1 = XTAL1 input pad XTAL2 = XTAL2 input pad VGATE1P = VGATE1P VGATE3P = VGATE3P Vx = Supply NC = These pins are reserved for future extensions and shall not be connected externally NC1 = These pins are not connected on package level and will not be used for future extensions NCVDDPSB = This pin has a different functionality in an Production Device and an Emulation Device. For details pls. see Pin/Ball description of this pin. NCVDDSB = This pin has a different functionality in an Production Device and an Emulation Device. For details pls. see Pin/Ball description of this pin.
2.1.2 Emergency Stop Function
The Emergency Stop function can be used to force GPIOs (General Purpose Inputs/Outputs) via an external input signal (EMGSTOPA or EMGSTOPB) into a defined state:
· Input state and
· PU or High-Z depending on HWCFG[6] level latched during Porst active
Control of the Emergency Stop function:
· The Emergency Stop function can be enabled/disabled in the SCU (see chapter "SCU", "Emergency Stop Control")
· The Emergency Stop input signal, EMGSTOPA (P33.8) / EMGSTOPB (P21.2) , can selected in the SCU (see chapter "SCU", "Emergency Stop Control")
· On port level, each GPIO can be enabled/disabled for the Emergency Stop function via the Px_ESR (Port x Emergency Stop) registers in the port control logic (see chapter "General Purpose I/O Ports and Peripheral I/O Lines", "Emergency Stop Register").
The Emergency Stop function is available for all GPIO Ports with the following exceptions:
· Not available for P20.2 (General Purpose Input/GPI only, overlayed with Testmode)
· Not available for P40.x (analoge input ANx overlayed with GPI)
· Not available for P32.0 EVR13 SMPS mode.

1) The default state of GPIOs (Px.y) during and after PORST active is controllled via HWCFG[6] (P14.4). HWCFG[6] has a weak internal pull-up active at start-up if the pin is left unconnected.See also User´s Manual, "Introduction Chapter", "General Purpose I/O Ports and Peripheral I/O Lines", Figure: "Default state of port pins during and after reset".
2) If HWCFG[6] is left unconnected or is externally pulled high, weak internal pull-ups (PU1) / pull-downs (PD1) are active during and after reset.
3) If HWCFG[6] is connected to ground, the PD1 / PU1 pins are predominantly in HighZ during and after reset.

Data Sheet

TOC-120

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC299x Pin Definition and Functions:
· Not available for dedicated I/O without General Purpose Output function (e.g ESRx, TMS, TCK) The Emergency Stop function can be overruled on the following GPIO Ports: · P00.x and P02.x: Emergency Stop can be overruled by the 8-Bit Standby Controller (SBR), if implemented.
Overruling can be disabled via the control registers P00_SCR / P02_SCR (see chapter "General Purpose I/O Ports and Peripheral I/O Lines", P00 / P01) · P00.x: Emergency Stop can be overruled by the VADC. Overruling can be disabled via the control register P00_SCR (see chapter "General Purpose I/O Ports and Peripheral I/O Lines", P00) · P14.0 and P14.1: Emergency Stop can be overruled in the DXCPL mode (DAP over can physical layer mode). No Overruling in the DXCM (Debug over can message) mode · P21.6: Emergency Stop can be overruled in JTAG mode if this pin is used as TDI · P21.7: Emergency Stop can be overruled in JTAG or Three Pin DAP mode · P20.0: Emergency Stop can be overruled in JTAG mode if this GPIO is used as TDI · P33.8: Emergency Stop can be overruled if this pin is used as safety output pin (SMUFSP)
2.1.3 Pull-Up/Pull-Down Reset Behavior of the Pins

Table 2-26 List of Pull-Up/Pull-Down Reset Behavior of the Pins

Pins

PORST = 0

PORST = 1

all GPIOs

Pull-up if HWCFG[6] = 1 or High-Z if HWCFG[6] = 0

TDI, TESTMODE

Pull-up

PORST1)

Pull-down with IPORST relevant

Pull-down with IPDLI relevant

TRST, TCK, TMS

Pull-down

ESR0

The open-drain driver is used to drive low.2)

Pull-up3)

ESR1

Pull-up3)

TDO

Pull-up

High-Z/Pull-up4)

1) Pull-down with IPORST relevant is always activated when a primary supply monitor detects a violation. 2) Valid additionally after deactivation of PORST until the internal reset phase has finished. See the SCU chapter for details.

3) See the SCU_IOCR register description.

4) Depends on JTAG/DAP selection with TRST.

In case of leakage test (PORST = 0 and TESTMODE = 0), the pull-down of the TRST pin is switched off. In case of an user application (TESTMODE = 1), the pull-down of the TRST is always switched on.

Data Sheet

TOC-121

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

2.2

TC298x Pin Definition and Functions: BGA416

Figure 2-2 is showing the TC298x Logic Symbol for the package variant: BGA416.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 A NC P10.15 P10.11 P10.8 P11.3 P10.5 P10.2 P10.4 P10.0 P11.7 P12.0 P13.14 P13.10 P14.8 P14.12 P13.6 P13.5 VDDFL3 P14.11 P15.7 P15.4 ESR1 ESR0 P20.0 VEXT VSS A

B P02.1 P02.0 P10.13 P10.7 P11.9 P10.9 P10.3 P10.1 P11.13 P11.5 P12.1 P13.12 P13.11 P14.15 P14.14 P13.7 P13.4 VDDFL3 P14.13 P15.6 P15.2 PORST P20.2 VEXT VSS VDD B

C P02.4 P02.11 P10.14 P10.10 P11.12 P11.6 P11.15 P11.14 P11.8 P11.4 P11.1 P13.9 P14.6 P14.3 P14.10 P13.3 P13.0 P13.1 P14.9 P14.5 P14.0 P15.1 VEXT VSS VDD P21.5 C

D P02.13 P02.15 P02.12 P02.5 P11.10 P11.11 VFLEX VSS VDD P11.2 P11.0 P14.7 P14.4 VEXT VSS P15.8 P13.2 P15.3 P15.5 P14.2 P14.1 VEXT VSS VDD P21.7 P21.4 D

E P02.14 P02.2 P01.7 P02.9 E

6

78

9 10 11 12 13 14 15 16 17

18

19

20

21

E VDD TCK P21.6 VDDP3 E

F P01.0 P02.3 P01.6 P02.10 F

F TRST TMS VSS VDD F

G P01.2 P10.6 P01.4 P01.5 G

Top-View

G P21.3 P21.1 XTAL2 XTAL1 G

H P02.7 P02.6 P01.3 VDD H

H P21.2 VDDP3 VDDP3 VDDP3 H

J P01.9 P01.1 P02.8 VSS J K P01.11 P01.10 P01.8 VEXT K

10 11 12 13 14 15 16 17 K VSS VSS VSS VSS VSS VSS VSS VSS K

J P21.0 P22.1 P22.2 P22.3 J K P22.0 P23.4 P23.5 P23.6 K

L P01.15 P01.14 P01.13 P01.12 L

L VSS VSS VSS VSS VSS VSS VSS VSS

L

L

VSS P23.1 P23.2 P23.3 L

M P00.3 P00.2 P00.1 P00.0 M

M VSS VSS VSS VSS VSS VSS VSS VSS M

M VEBU P24.14 P24.15 P23.0 M

N P00.10 P00.9 P00.5 P00.4 N

P P00.12 P00.11 P00.13 P00.15 P

NC /

NC /

R VDDSB P00.14 P00.6 VDDSB R

T AN42 P00.8 P00.7 VSS T

U AN43 AN70 AN41 AN40 U

V AN71 AN68 AN37 AN36 V W AN69 AN64 AN32 VAREF2 W

N VSS VSS VSS VSS VSS VSS VSS VSS N

P

VSS (AGBT VSS CLKP)

VSS

VSS

VSS

VSS

NC VSS (VDDPSB)

P

VSS

VSS

R (AGBT VSS VSS VSS VSS VSS VSS (AGBT R

CLKN)

ERR)

T VSS VSS VSS VSS VSS VSS VSS VSS T

VSS VSS

U VSS VSS (AGBT (AGBT VSS VSS VSS VSS

U

TX0N) TX0P)

10 11 12 13 14 15 16 17

N P24.10 P24.11 P24.12 P24.13 N P VDD P24.7 P24.8 P24.9 P
R VSS P24.4 P24.5 P24.6 R T VEBU P24.1 P24.2 P24.3 T U P24.0 P25.13 P25.14 P25.15 U V VDD P25.10 P25.11 P25.12 V W VSS P25.7 P25.8 P25.9 W

Y AN65 AN60 AN33 VAGND2 Y

Y VEBU P25.3 P25.4 P25.5 Y

AA AN61 AN26 AN5 AN56 AA

AA P25.2 P25.1 P26.0 P25.0 AA

AB AN28 AN27 AN57 AN7 AB 6

78

9 10 11 12 13 14 15 16 17

18

19

AC AN29 AN4 AN16 AN8 AN0 VAGND1 AN24 AN20 P34.1 P34.2 P33.0 P33.4 P33.14 P32.4 P33.7 VEXT VGATE1P VFLEXE VSS

20

21

AB VDD P30.2 P30.7 P30.12 AB

VDD VGATE3P VFLEXE VSS P30.3 P30.8 P30.13 AC

AD AN6 AN48 AN17 AN9 AN1 VAREF1 AN25 AN21 VEVRSB P34.4 P33.1 P33.5 P33.15 P32.5 P33.8 VEXT P32.0 P31.0 P31.3 P31.6 P31.9 P31.12 P31.14 P30.4 P30.9 P30.14 AD

AE AN49 AN18 AN10 AN2 VDDM AN52 AN54 AN22 VDDM P34.5 P33.2 P33.6 P32.2 P33.10 P33.13 VEXT P32.6 P31.1 P31.4 P31.7 P31.10 P31.13 P31.15 P30.5 P30.10 P30.15 AE

AF NC AN19 AN11 AN3 VSSM AN53 AN55 AN23 VSSM P34.3 P33.3 P33.9 P32.3 P33.11 P33.12 VEXT P32.7 P31.2 P31.5 P31.8 P31.11 P30.0 P30.1 P30.6 P30.11 NC AF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Figure 2-2 TC298x Logic Symbol for the package variant BGA416.

Data Sheet

TOC-122

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

2.2.1

Package and Pinning DefinitionsTC298x Pin Definition and Functions:
TC298x BGA416 Package Variant Pin Configuration

Table 2-27 Port 00 Functions

Pin

Symbol

M4

P00.0

TIN9

CTRAPA

T12HRE

INJ00

CIFD9

P00.0

TOUT9

ASCLK3

ATX3

­

TXDCAN1

­

COUT63

ETHMDIOA

Ctrl Type

I

MP /

PU1 /

VEXT

O0 O1 O2 O3 O4 O5 O6 O7 HWOU T

Function General-purpose input GTM input CCU61 input CCU60 input MSC0 input CIF input General-purpose output GTM output ASCLIN3 output ASCLIN3 output Reserved CAN node 1 output Reserved CCU60 output ETH input/output

Data Sheet

TOC-123

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-27 Port 00 Functions (cont'd)

Pin

Symbol

Ctrl

M3

P00.1

I

TIN10

ARX3E

RXDCAN1D

PSIRX0A

SENT0B

CC60INB

CC60INA

DSCIN5A

DS5NA

DSCIN7B

VADCG7.5

CIFD10

P00.1

O0

TOUT10

O1

ATX3

O2

­

O3

DSCOUT5

O4

DSCOUT7

O5

SPC0

O6

CC60

O7

M2

P00.2

I

TIN11

SENT1B

DSDIN5A

DSDIN7B

DS5PA

VADCG7.4

CIFD11

P00.2

O0

TOUT11

O1

ASCLK3

O2

TXDCANr1

O3

PSITX0

O4

TXDCAN3

O5

SLSO34

O6

COUT60

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input ASCLIN3 input CAN node 1 input PSI5 input SENT input CCU60 input CCU61 input DSADC channel 5 input DSADC positive analog input of channel channel 5, pin A DSADC channel 7 input VADC analog input channel 5 of group 7 CIF input General-purpose output GTM output ASCLIN3 output Reserved DSADC channel 5 output DSADC channel 7 output SENT output CCU61 output General-purpose input GTM input SENT input DSADC channel 5 input DSADC channel 7 input DSADC negative analog input of channel 5, pin A VADC analog input channel 4 of group 7 CIF input General-purpose output GTM output ASCLIN3 output CAN node 1 output (MultiCANr+) PSI5 output CAN node 3 output QSPI3 output CCU61 output

Data Sheet

TOC-124

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-27 Port 00 Functions (cont'd)

Pin

Symbol

Ctrl

M1

P00.3

I

TIN12

RXDCAN3A

RXDCANr1A

PSIRX1A

PSISRXA

SENT2B

CC61INB

CC61INA

DSCIN3A

VADCG7.3

DSITR5F

CIFD12

P00.3

O0

TOUT12

O1

ASLSO3

O2

­

O3

DSCOUT3

O4

­

O5

SPC2

O6

CC61

O7

N4

P00.4

I

TIN13

REQ7

SENT3B

DSDIN3A

DSSGNA

VADCG7.2

CIFD13

P00.4

O0

TOUT13

O1

PSISTX

O2

­

O3

PSITX1

O4

VADCG4BFL0

O5

SPC3

O6

COUT61

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input CAN node 3 input CAN node 1 input (MultiCANr+) PSI5 input PSI5-S input SENT input CCU60 input CCU61 input DSADC channel 3 input VADC analog input channel 3 of group 7 DSADC channel 5 input CIF input General-purpose output GTM output ASCLIN3 output Reserved DSADC channel 3 output Reserved SENT output CCU61 output General-purpose input GTM input SCU input SENT input DSADC channel 3 input DSADC channel input VADC analog input channel 2 of group 7 CIF input General-purpose output GTM output PSI5-S output Reserved PSI5 output VADC output SENT output CCU61 output

Data Sheet

TOC-125

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-27 Port 00 Functions (cont'd)

Pin

Symbol

Ctrl

N3

P00.5

I

TIN14

PSIRX2A

SENT4B

CC62INB

CC62INA

DSCIN2A

VADCG7.1

CIFD14

P00.5

O0

TOUT14

O1

DSCGPWMN

O2

SLSO33

O3

DSCOUT2

O4

VADCG4BFL1

O5

SPC4

O6

CC62

O7

R3

P00.6

I

TIN15

SENT5B

DSDIN2A

VADCG7.0

DSITR4F

CIFD15

P00.6

O0

TOUT15

O1

DSCGPWMP

O2

VADCG4BFL2

O3

PSITX2

O4

VADCEMUX10

O5

SPC5

O6

COUT62

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input PSI5 input SENT input CCU60 input CCU61 input DSADC channel 2 input VADC analog input channel 1 of group 7 CIF input General-purpose output GTM output DSADC output QSPI3 output DSADC channel 2 output VADC output SENT output CCU61 output General-purpose input GTM input SENT input DSADC channel 2 input A VADC analog input channel 0 of group 7 (with pull down diagnostics) DSADC channel 4 input F CIF input General-purpose output GTM output DSADC output VADC output PSI5 output VADC output SENT output CCU61 output

Data Sheet

TOC-126

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-27 Port 00 Functions (cont'd)

Pin

Symbol

Ctrl

T3

P00.7

I

TIN16

SENT6B

CC60INC

CCPOS0A

T12HRB

T2INA

DSCIN4A

DS4NA

VADCG6.5

CIFCLK

P00.7

O0

TOUT16

O1

­

O2

VADCG4BFL3

O3

DSCOUT4

O4

VADCEMUX11

O5

SPC6

O6

CC60

O7

T2

P00.8

I

TIN17

SENT7B

CC61INC

CCPOS1A

T13HRB

T2EUDA

DSDIN4A

DS4PA

VADCG6.4

CIFVSNC

P00.8

O0

TOUT17

O1

SLSO36

O2

­

O3

­

O4

VADCEMUX12

O5

SPC7

O6

CC61

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input SENT input CCU61 input CCU61 input CCU60 input GPT120 input DSADC channel 4 input A DSADC negative analog input channel 4, pin A VADC analog input channel 5 of group 6 CIF input General-purpose output GTM output Reserved VADC output DSADC channel 4 output VADC output SENT output CCU61 output General-purpose input GTM input SENT input CCU61 input CCU61 input CCU60 input GPT120 input DSADC channel 4 input A DSADC positive analog input of channel 4, pin A VADC analog input channel 4 of group 6 CIF input General-purpose output GTM output QSPI3 output Reserved Reserved VADC output SENT output CCU61 output

Data Sheet

TOC-127

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-27 Port 00 Functions (cont'd)

Pin

Symbol

Ctrl

N2

P00.9

I

TIN18

SENT8B

CC62INC

CCPOS2A

T13HRC

T12HRC

T4EUDA

DSCIN1A

VADCG6.3

DSITR3F

CIFHSNC

P00.9

O0

TOUT18

O1

SLSO37

O2

ARTS3

O3

DSCOUT1

O4

­

O5

SPC8

O6

CC62

O7

N1

P00.10

I

TIN19

SENT9B

DSDIN1A

VADCG6.2

P00.10

O0

TOUT19

O1

­

O2

­

O3

­

O4

­

O5

SPC9

O6

COUT63

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input SENT input CCU61 input CCU61 input CCU60 input CCU60 input GPT120 input DSADC channel 1 input A VADC analog input channel 3 of group 6 DSADC channel 3 input F CIF input General-purpose output GTM output QSPI3 output ASCLIN3 output DSADC channel 1 output Reserved SENT output CCU61 output General-purpose input GTM input SENT input DSADC channel 1 input A VADC analog input channel 2 of group 6 General-purpose output GTM output Reserved Reserved Reserved Reserved SENT output CCU61 output

Data Sheet

TOC-128

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-27 Port 00 Functions (cont'd)

Pin

Symbol

Ctrl

P2

P00.11

I

TIN20

CTRAPA

T12HRE

DSCIN0A

VADCG6.1

P00.11

O0

TOUT20

O1

­

O2

­

O3

DSCOUT0

O4

­

O5

­

O6

­

O7

P1

P00.12

I

TIN21

ACTS3A

DSDIN0A

VADCG6.0

P00.12

O0

TOUT21

O1

­

O2

­

O3

­

O4

­

O5

­

O6

COUT63

O7

P3

P00.13

I

TIN167

DSDIN6A

P00.13

O0

TOUT167

O1

­

O2

­

O3

EXTCLK1

O4

­

O5

­

O6

­

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT
MP+ / PU1 / VEXT

Function General-purpose input GTM input CCU60 input CCU61 input DSADC channel 0 input A VADC analog input channel 1 of group 6 General-purpose output GTM output Reserved Reserved DSADC channel 0 output Reserved Reserved Reserved General-purpose input GTM input ASCLIN3 input DSADC channel 0 input A VADC analog input channel 0 of group 6 General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved CCU61 output General-purpose input GTM input DSADC channel 6 input A General-purpose output GTM output Reserved Reserved SCU output Reserved Reserved Reserved

Data Sheet

TOC-129

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-27 Port 00 Functions (cont'd)

Pin

Symbol

Ctrl

R2

P00.14

I

TIN166

DSCIN6A

P00.14

O0

TOUT166

O1

­

O2

­

O3

DSCOUT6

O4

­

O5

­

O6

­

O7

P4

P00.15

I

TIN168

DSITR6F

P00.15

O0

TOUT168

O1

­

O2

­

O3

EXTCLK0

O4

­

O5

­

O6

­

O7

Type LP / PU1 / VEXT
MP+ / PU1 / VEXT

Function General-purpose input GTM input DSADC channel 6 input A General-purpose output GTM output Reserved Reserved DSADC channel 6 output Reserved Reserved Reserved General-purpose input GTM input DSADC channel 6 input F General-purpose output GTM output Reserved Reserved SCU output Reserved Reserved Reserved

Table 2-28 Port 01 Functions

Pin

Symbol

F1

P01.0

TIN155

DSITR6E

RXDCAN3F

RXDCANr1E

P01.0

TOUT155

­

­

­

­

­

­

Ctrl Type Function

I

LP /

General-purpose input

PU1 / VEXT

GTM input DSADC channel 6 input E

CAN node 3 input

CAN node 1 input (MultiCANr+)

O0

General-purpose output

O1

GTM output

O2

Reserved

O3

Reserved

O4

Reserved

O5

Reserved

O6

Reserved

O7

Reserved

Data Sheet

TOC-130

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-28 Port 01 Functions (cont'd)

Pin

Symbol

Ctrl

J2

P01.1

I

TIN159

DSITR8E

RXD1A1

SENT10B

P01.1

O0

TOUT159

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

G1

P01.2

I

TIN156

DSCIN7A

P01.2

O0

TOUT156

O1

­

O2

TXDCAN3

O3

­

O4

TXDCANr1

O5

DSCOUT7

O6

­

O7

H3

P01.3

I

TIN111

SLSI3B

DSITR7F

P01.3

O0

TOUT111

O1

­

O2

­

O3

SLSO39

O4

TXDCAN1

O5

­

O6

­

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input DSADC channel 8 input E ERAY1 input SENT input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved General-purpose input GTM input DSADC channel 7 input A General-purpose output GTM output Reserved CAN node 3 output Reserved CAN node 1 output (MultiCANr+) DSADC channel 7 output Reserved General-purpose input GTM input QSPI3 input DSADC channel 7 input F General-purpose output GTM output Reserved Reserved QSPI3 output CAN node 1 output Reserved Reserved

Data Sheet

TOC-131

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-28 Port 01 Functions (cont'd)

Pin

Symbol

Ctrl

G3

P01.4

I

TIN112

RXDCAN1C

DSITR7E

P01.4

O0

TOUT112

O1

­

O2

­

O3

SLSO310

O4

­

O5

­

O6

­

O7

G4

P01.5

I

TIN113

MRST3C

DSCIN8A

P01.5

O0

TOUT113

O1

­

O2

­

O3

MRST3

O4

­

O5

DSCOUT8

O6

­

O7

F3

P01.6

I

TIN114

MTSR3C

DSDIN8A

P01.6

O0

TOUT114

O1

­

O2

­

O3

MTSR3

O4

­

O5

­

O6

­

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT
MP / PU1 / VEXT

Function General-purpose input GTM input CAN node 1 input DSADC channel 7 input E General-purpose output GTM output Reserved Reserved QSPI3 output Reserved Reserved Reserved General-purpose input GTM input QSPI3 input DSADC channel 8 input A General-purpose output GTM output Reserved Reserved QSPI3 output Reserved DSADC channel 8 output Reserved General-purpose input GTM input QSPI3 input DSADC channel 8 input A General-purpose output GTM output Reserved Reserved QSPI3 output Reserved Reserved Reserved

Data Sheet

TOC-132

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-28 Port 01 Functions (cont'd)

Pin

Symbol

Ctrl

E3

P01.7

I

TIN115

SCLK3C

DSITR8F

P01.7

O0

TOUT115

O1

­

O2

­

O3

SCLK3

O4

­

O5

­

O6

­

O7

K3

P01.8

I

TIN162

DSDIN9A

SENT12B

ARX0C

RXDCAN0F

RXDCANr0E

RXD1B1

P01.8

O0

TOUT162

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

Type MP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input QSPI3 input DSADC channel 8 input F General-purpose output GTM output Reserved Reserved QSPI3 output Reserved Reserved Reserved General-purpose input GTM input DSADC channel 9 input A SENT input ASCLIN0 input CAN node 0 input CAN node 0 input (MultiCANr+) ERAY1 input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved

Data Sheet

TOC-133

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-28 Port 01 Functions (cont'd)

Pin

Symbol

Ctrl

J1

P01.9

I

TIN160

DSCIN9A

SENT11B

P01.9

O0

TOUT160

O1

­

O2

­

O3

­

O4

­

O5

DSCOUT9

O6

­

O7

K2

P01.10

I

TIN163

DSITR9F

SENT13B

P01.10

O0

TOUT163

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

K1

P01.11

I

TIN165

DSITR9E

SENT14B

P01.11

O0

TOUT165

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input DSADC channel 9 input A SENT input General-purpose output GTM output Reserved Reserved Reserved Reserved DSADC channel 9 output Reserved General-purpose input GTM input DSADC channel 9 input F SENT input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved General-purpose input GTM input DSADC channel 9 input E SENT input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved

Data Sheet

TOC-134

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-28 Port 01 Functions (cont'd)

Pin

Symbol

Ctrl

L4

P01.12

I

TIN158

P01.12

O0

TOUT158

O1

­

O2

­

O3

­

O4

­

O5

TXD1A

O6

­

O7

L3

P01.13

I

TIN161

P01.13

O0

TOUT161

O1

ATX0

O2

­

O3

TXDCAN0

O4

TXDCANr0

O5

TXD1B

O6

­

O7

L2

P01.14

I

TIN164

P01.14

O0

TOUT164

O1

­

O2

­

O3

­

O4

­

O5

TXEN1A

O6

­

O7

Type MP+ / PU1 / VEXT
MP+ / PU1 / VEXT
MP+ / PU1 / VEXT

Function General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved ERAY1 output Reserved General-purpose input GTM input General-purpose output GTM output ASCLIN0 output Reserved CAN node 0 output CAN node 0 output (MultiCANr+) ERAY1 output Reserved General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved ERAY1 output Reserved

Data Sheet

TOC-135

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-28 Port 01 Functions (cont'd)

Pin

Symbol

Ctrl

L1

P01.15

I

TIN157

DSDIN7A

P01.15

O0

TOUT157

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

Type
LP / PU1 / VEXT

Function General-purpose input GTM input DSADC channel 7 input A General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved

Table 2-29 Port 02 Functions

Pin

Symbol

B2

P02.0

TIN0

REQ6

ARX2G

CC60INA

CC60INB

CIFD0

P02.0

TOUT0

ATX2

SLSO31

DSCGPWMN

TXDCAN0

TXD0A

CC60

Ctrl Type Function

I

MP+ / General-purpose input

PU1 / VEXT

GTM input SCU input

ASCLIN2 input

CCU60 input

CCU61 input

CIF input

O0

General-purpose output

O1

GTM output

O2

ASCLIN2 output

O3

QSPI3 output

O4

DSADC output

O5

CAN node 0 output

O6

ERAY0 output

O7

CCU60 output

Data Sheet

TOC-136

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-29 Port 02 Functions (cont'd)

Pin

Symbol

Ctrl

B1

P02.1

I

TIN1

REQ14

ARX2B

RXDCAN0A

RXD0A2

CIFD1

P02.1

O0

TOUT1

O1

SLSO47

O2

SLSO32

O3

DSCGPWMP

O4

­

O5

­

O6

COUT60

O7

E2

P02.2

I

TIN2

CC61INA

CC61INB

CIFD2

P02.2

O0

TOUT2

O1

ATX1

O2

SLSO33

O3

PSITX0

O4

TXDCAN2

O5

TXD0B

O6

CC61

O7

Type Function

LP / PU1 General-purpose input / VEXT GTM input

SCU input

ASCLIN2 input

CAN node 0 input

ERAY0 input

CIF input

General-purpose output

GTM output

QSPI4 output

QSPI3 output

DSADC output

Reserved

Reserved

CCU60 output

MP+ / PU1 / VEXT

General-purpose input GTM input CCU60 input

CCU61 input

CIF input

General-purpose output

GTM output

ASCLIN1 output

QSPI3 output

PSI5 output

CAN node 2 output

ERAY0 output

CCU60 output

Data Sheet

TOC-137

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-29 Port 02 Functions (cont'd)

Pin

Symbol

Ctrl

F2

P02.3

I

TIN3

ARX1G

RXDCAN2B

RXD0B2

PSIRX0B

DSCIN5B

SDI11

CIFD3

P02.3

O0

TOUT3

O1

ASLSO2

O2

SLSO34

O3

DSCOUT5

O4

­

O5

­

O6

COUT61

O7

C1

P02.4

I

TIN4

SLSI3A

ECTT1

RXDCAN0D

CC62INA

CC62INB

DSDIN5B

SDA0A

CIFD4

P02.4

O0

TOUT4

O1

ASCLK2

O2

SLSO30

O3

PSISCLK

O4

SDA0

O5

TXEN0A

O6

CC62

O7

Type LP / PU1 / VEXT
MP+ / PU1 / VEXT

Function General-purpose input GTM input ASCLIN1 input CAN node 2 input ERAY0 input PSI5 input DSADC channel 5 input B MSC1 input CIF input General-purpose output GTM output ASCLIN2 output QSPI3 output DSADC channel 5 output Reserved Reserved CCU60 output General-purpose input GTM input QSPI3 input TTCAN input CAN node 0 input CCU60 input CCU61 input DSADC channel 5 input B I2C0 input CIF input General-purpose output GTM output ASCLIN2 output QSPI3 output PSI5-S output I2C0 output ERAY0 output CCU60 output

Data Sheet

TOC-138

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-29 Port 02 Functions (cont'd)

Pin

Symbol

Ctrl

D4

P02.5

I

TIN5

MRST3A

ECTT2

PSIRX1B

PSISRXB

SENT3C

DSCIN4B

SCL0A

CIFD5

P02.5

O0

TOUT5

O1

TXDCAN0

O2

MRST3

O3

DSCOUT4

O4

SCL0

O5

TXEN0B

O6

COUT62

O7

H2

P02.6

I

TIN6

MTSR3A

SENT2C

CC60INC

CCPOS0A

T12HRB

T3INA

CIFD6

DSDIN4B

DSITR5E

P02.6

O0

TOUT6

O1

PSISTX

O2

MTSR3

O3

PSITX1

O4

VADCEMUX00

O5

­

O6

CC60

O7

Type MP+ / PU1 / VEXT
MP / PU1 / VEXT

Function General-purpose input GTM input QSPI3 input TTCAN input PSI5 input PSI5-S input SENT input DSADC channel 4 input B I2C0 input CIF input General-purpose output GTM output CAN node 0 output QSPI3 output DSADC channel 4 output I2C0 output ERAY0 output CCU60 output General-purpose input GTM input QSPI3 input SENT input CCU60 input CCU60 input CCU61 input GPT120 input CIF input DSADC channel 4 input B DSADC channel 5 input E General-purpose output GTM output PSI5-S output QSPI3 output PSI5 output VADC output Reserved CCU60 output

Data Sheet

TOC-139

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-29 Port 02 Functions (cont'd)

Pin

Symbol

Ctrl

H1

P02.7

I

TIN7

SCLK3A

PSIRX2B

SENT1C

CC61INC

CCPOS1A

T13HRB

T3EUDA

CIFD7

DSCIN3B

DSITR4E

P02.7

O0

TOUT7

O1

­

O2

SCLK3

O3

DSCOUT3

O4

VADCEMUX01

O5

SPC1

O6

CC61

O7

Type
MP / PU1 / VEXT

Function General-purpose input GTM input QSPI3 input PSI5 input SENT input CCU60 input CCU60 input CCU61 input GPT120 input CIF input DSADC channel 3 input B DSADC channel 4 input E General-purpose output GTM output Reserved QSPI3 output DSADC channel 3 output VADC output SENT output CCU60 output

Data Sheet

TOC-140

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-29 Port 02 Functions (cont'd)

Pin

Symbol

Ctrl

J3

P02.8

I

TIN8

SENT0C

CC62INC

CCPOS2A

T12HRC

T13HRC

T4INA

CIFD8

DSDIN3B

DSITR3E

P02.8

O0

TOUT8

O1

SLSO35

O2

­

O3

PSITX2

O4

VADCEMUX02

O5

ETHMDC

O6

CC62

O7

E4

P02.9

I

TIN116

P02.9

O0

TOUT116

O1

ATX2

O2

­

O3

­

O4

TXDCAN1

O5

­

O6

­

O7

Type Function

LP / PU1 General-purpose input

/ VEXT

GTM input SENT input

CCU60 input

CCU60 input

CCU61 input

CCU61 input

GPT120 input

CIF input

DSADC channel 3 input B

DSADC channel 3 input E

General-purpose output

GTM output

QSPI3 output

Reserved

PSI5 output

VADC output

ETH output

CCU60 output

LP / PU1 / VEXT

General-purpose input GTM input General-purpose output

GTM output

ASCLIN2 output

Reserved

Reserved

CAN node 1 output

Reserved

Reserved

Data Sheet

TOC-141

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-29 Port 02 Functions (cont'd)

Pin

Symbol

Ctrl

F4

P02.10

I

TIN117

ARX2C

RXDCAN1E

P02.10

O0

TOUT117

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

C2

P02.11

I

TIN118

P02.11

O0

TOUT118

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

D3

P02.12

I

TIN151

P02.12

O0

TOUT151

O1

SLSO35

O2

SLSO44

O3

­

O4

­

O5

­

O6

­

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input ASCLIN2 input CAN node 1 input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved General-purpose input GTM input General-purpose output GTM output QSPI3 output QSPI4 output Reserved Reserved Reserved Reserved

Data Sheet

TOC-142

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-29 Port 02 Functions (cont'd)

Pin

Symbol

Ctrl

D1

P02.13

I

TIN153

P02.13

O0

TOUT153

O1

SLSO37

O2

SLSO46

O3

TXDCAN0

O4

TXDCANr0

O5

­

O6

­

O7

E1

P02.14

I

TIN154

RXDCAN0H

RXDCANr0D

P02.14

O0

TOUT154

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

D2

P02.15

I

TIN152

P02.15

O0

TOUT152

O1

SLSO36

O2

SLSO45

O3

­

O4

­

O5

TXEN1B

O6

­

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT
MP+ / PU1 / VEXT

Function General-purpose input GTM input General-purpose output GTM output QSPI3 output QSPI4 output CAN node 0 output CAN node 0 output (MultiCANr+) Reserved Reserved General-purpose input GTM input CAN node 0 input CAN node 0 input (MultiCANr+) General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved General-purpose input GTM input General-purpose output GTM output QSPI3 output QSPI4 output Reserved Reserved ERAY1 output Reserved

Data Sheet

TOC-143

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-30 Port 10 Functions

Pin

Symbol

A9

P10.0

TIN102

T6EUDB

P10.0

TOUT102

­

SLSO110

­

VADCG6BFL0

­

­

B8

P10.1

TIN103

MRST1A

T5EUDB

P10.1

TOUT103

MTSR1

MRST1

EN01

VADCG6BFL1

END03

­

A7

P10.2

TIN104

SCLK1A

T6INB

REQ2

RXDCAN2E

SDI01

P10.2

TOUT104

­

SCLK1

EN00

VADCG6BFL2

END02

­

Data Sheet

Ctrl Type

Function

I

LP /

General-purpose input

PU1 / VEXT

GTM input GPT120 input

O0

General-purpose output

O1

GTM output

O2

Reserved

O3

QSPI1 output

O4

Reserved

O5

VADC output

O6

Reserved

O7

Reserved

I

MP+ / General-purpose input

PU1 / VEXT

GTM input QSPI1 input

GPT120 input

O0

General-purpose output

O1

GTM output

O2

QSPI1 output

O3

QSPI1 output

O4

MSC0 output

O5

VADC output

O6

MSC0 output

O7

Reserved

I

MP /

General-purpose input

PU1 / VEXT

GTM input QSPI1 input

GPT120 input

SCU input

CAN node 2 input

MSC0 input

O0

General-purpose output

O1

GTM output

O2

Reserved

O3

QSPI1 output

O4

MSC0 output

O5

VADC output

O6

MSC0 output

O7

Reserved

TOC-144

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-30 Port 10 Functions (cont'd)

Pin

Symbol

Ctrl

B7

P10.3

I

TIN105

MTSR1A

REQ3

T5INB

P10.3

O0

TOUT105

O1

VADCG6BFL3

O2

MTSR1

O3

EN00

O4

END02

O5

TXDCAN2

O6

­

O7

A8

P10.4

I

TIN106

MTSR1C

CCPOS0C

T3INB

P10.4

O0

TOUT106

O1

­

O2

SLSO18

O3

MTSR1

O4

EN00

O5

END02

O6

­

O7

Type MP / PU1 / VEXT
MP+ / PU1 / VEXT

Function General-purpose input GTM input QSPI1 input SCU input GPT120 input General-purpose output GTM output VADC output QSPI1 output MSC0 output MSC0 output CAN node 2 output Reserved General-purpose input GTM input QSPI1 input CCU60 input GPT120 input General-purpose output GTM output Reserved QSPI1 output QSPI1 output MSC0 output MSC0 output Reserved

Data Sheet

TOC-145

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-30 Port 10 Functions (cont'd)

Pin

Symbol

Ctrl

A6

P10.5

I

TIN107

HWCFG4

RXDCANr0A

INJ01

P10.5

O0

TOUT107

O1

ATX2

O2

SLSO38

O3

SLSO19

O4

T6OUT

O5

ASLSO2

O6

PSITX3

O7

G2

P10.6

I

TIN108

ARX2D

MTSR3B

PSIRX3C

HWCFG5

P10.6

O0

TOUT108

O1

ASCLK2

O2

MTSR3

O3

T3OUT

O4

TXDCANr0

O5

MRST1

O6

VADCG7BFL0

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input SCU input CAN node 0 input (MultiCANr+) MSC0 input General-purpose output GTM output ASCLIN2 output QSPI3 output QSPI1 output GPT120 output ASCLIN2 output PSI5 output General-purpose input GTM input ASCLIN2 input QSPI3 input PSI5 input SCU input General-purpose output GTM output ASCLIN2 output QSPI3 output GPT120 output CAN node 0 output (MultiCANr+) QSPI1 output VADC output

Data Sheet

TOC-146

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-30 Port 10 Functions (cont'd)

Pin

Symbol

Ctrl

B4

P10.7

I

TIN109

ACTS2A

MRST3B

REQ4

CCPOS1C

T3EUDB

P10.7

O0

TOUT109

O1

­

O2

MRST3

O3

VADCG7BFL1

O4

TXDCANr0

O5

­

O6

­

O7

A4

P10.8

I

TIN110

SCLK3B

REQ5

CCPOS2C

T4INB

RXDCANr0B

P10.8

O0

TOUT110

O1

ARTS2

O2

SCLK3

O3

­

O4

­

O5

­

O6

­

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input ASCLIN2 input QSPI3 input SCU input CCU60 input GPT120 input General-purpose output GTM output Reserved QSPI3 output VADC output CAN node 0 output (MultiCANr+) Reserved Reserved General-purpose input GTM input QSPI3 input SCU input CCU60 input GPT120 input CAN node 0 input (MultiCANr+) General-purpose output GTM output ASCLIN2 output QSPI3 output Reserved Reserved Reserved Reserved

Data Sheet

TOC-147

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-30 Port 10 Functions (cont'd)

Pin

Symbol

Ctrl

B6

P10.9

I

TIN265

SENT10C

P10.9

O0

TOUT265

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

C4

P10.10

I

TIN266

SENT11C

P10.10

O0

TOUT266

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

A3

P10.11

I

TIN269

SENT14C

P10.11

O0

TOUT269

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input SENT input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved General-purpose input GTM input SENT input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved General-purpose input GTM input SENT input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved

Data Sheet

TOC-148

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-30 Port 10 Functions (cont'd)

Pin

Symbol

Ctrl

B3

P10.13

I

TIN268

SENT13C

P10.13

O0

TOUT268

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

C3

P10.14

I

TIN267

SENT12C

P10.14

O0

TOUT267

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

A2

P10.15

I

TIN270

P10.15

O0

TOUT270

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input SENT input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved General-purpose input GTM input SENT input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved

Data Sheet

TOC-149

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-31 Port 11 Functions

Pin

Symbol

D11

P11.0

TIN119

ARX3B

P11.0

TOUT119

ATX3

­

­

­

ETHTXD3

­

C11

P11.1

TIN120

P11.1

TOUT120

ASCLK3

ATX3

­

­

ETHTXD2

­

D10

P11.2

TIN95

P11.2

TOUT95

END03

SLSO05

SLSO15

EN01

ETHTXD1

COUT63

Ctrl Type

Function

I

MP+ /

General-purpose input

PU1 / VFLEX

GTM input ASCLIN3 input

O0

General-purpose output

O1

GTM output

O2

ASCLIN3 output

O3

Reserved

O4

Reserved

O5

Reserved

O6

ETH output

O7

Reserved

I

MP+ /

General-purpose input

PU1 /

GTM input

VFLEX

O0

General-purpose output

O1

GTM output

O2

ASCLIN3 output

O3

ASCLIN3 output

O4

Reserved

O5

Reserved

O6

ETH output

O7

Reserved

I

MPR/

General-purpose input

PU1 /

GTM input

VFLEX

O0

General-purpose output

O1

GTM output

O2

MSC0 output

O3

QSPI0 output

O4

QSPI1 output

O5

MSC0 output

O6

ETH output

O7

CCU60 output

Data Sheet

TOC-150

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-31 Port 11 Functions (cont'd)

Pin

Symbol

Ctrl

A5

P11.3

I

TIN96

MRST1B

SDI03

P11.3

O0

TOUT96

O1

­

O2

MRST1

O3

TXD0A

O4

­

O5

ETHTXD0

O6

COUT62

O7

C10

P11.4

I

TIN121

ETHRXCLKB

P11.4

O0

TOUT121

O1

ASCLK3

O2

­

O3

­

O4

­

O5

ETHTXER

O6

­

O7

B10

P11.5

I

TIN122

ETHTXCLKA

P11.5

O0

TOUT122

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

Type MPR / PU1 / VFLEX
MP+ / PU1 / VFLEX
LP / PU1 / VFLEX

Function General-purpose input GTM input QSPI1 input MSC0 input General-purpose output GTM output Reserved QSPI1 output ERAY0 output Reserved ETH output CCU60 output General-purpose input GTM input ETH input General-purpose output GTM output ASCLIN3 output Reserved Reserved Reserved ETH output Reserved General-purpose input GTM input ETH input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved

Data Sheet

TOC-151

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-31 Port 11 Functions (cont'd)

Pin

Symbol

Ctrl

C6

P11.6

I

TIN97

SCLK1B

P11.6

O0

TOUT97

O1

TXEN0B

O2

SCLK1

O3

TXEN0A

O4

FCLP0

O5

ETHTXEN

O6

COUT61

O7

A10

P11.7

I

TIN123

ETHRXD3

P11.7

O0

TOUT123

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

C9

P11.8

I

TIN124

ETHRXD2

P11.8

O0

TOUT124

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

Type MPR / PU1 / VFLEX
LP / PU1 / VFLEX
LP / PU1 / VFLEX

Function General-purpose input GTM input QSPI1 input General-purpose output GTM output ERAY0 output QSPI1 output ERAY0 output MSC0 output ETH output CCU60 output General-purpose input GTM input ETH input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved General-purpose input GTM input ETH input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved

Data Sheet

TOC-152

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-31 Port 11 Functions (cont'd)

Pin

Symbol

Ctrl

B5

P11.9

I

TIN98

MTSR1B

RXD0A1

ETHRXD1

P11.9

O0

TOUT98

O1

­

O2

MTSR1

O3

­

O4

SOP0

O5

­

O6

COUT60

O7

D5

P11.10

I

TIN99

REQ12

ARX1E

SLSI1A

RXDCAN3D

RXD0B1

ETHRXD0

SDI00

P11.10

O0

TOUT99

O1

­

O2

SLSO03

O3

SLSO13

O4

­

O5

­

O6

CC62

O7

Type MP+ / PU1 / VFLEX
LP / PU1 / VFLEX

Function General-purpose input GTM input QSPI1 input ERAY0 input ETH input General-purpose output GTM output Reserved QSPI1 output Reserved MSC0 output Reserved CCU60 output General-purpose input GTM input SCU input ASCLIN1 input QSPI1 input CAN node 3 input ERAY0 input ETH input MSC0 input General-purpose output GTM output Reserved QSPI0 output QSPI1 output Reserved Reserved CCU60 output

Data Sheet

TOC-153

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-31 Port 11 Functions (cont'd)

Pin

Symbol

Ctrl

D6

P11.11

I

TIN100

ETHCRSDVA

ETHRXDVA

ETHCRSB

P11.11

O0

TOUT100

O1

END02

O2

SLSO04

O3

SLSO14

O4

EN00

O5

TXEN0B

O6

CC61

O7

C5

P11.12

I

TIN101

ETHREFCLK

ETHTXCLKB

ETHRXCLKA

P11.12

O0

TOUT101

O1

ATX1

O2

GTMCLK2

O3

TXD0B

O4

TXDCAN3

O5

EXTCLK1

O6

CC60

O7

Type MP+ / PU1 / VFLEX
MPR / PU1 / VFLEX

Function General-purpose input GTM input ETH input ETH input ETH input General-purpose output GTM output MSC0 output QSPI0 output QSPI1 output MSC0 output ERAY0 output CCU60 output General-purpose input GTM input ETH input ETH input (Not for productive purposes) ETH input (Not for productive purposes) General-purpose output GTM output ASCLIN1 output GTM output ERAY0 output CAN node 3 output SCU output CCU60 output

Data Sheet

TOC-154

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-31 Port 11 Functions (cont'd)

Pin

Symbol

Ctrl

B9

P11.13

I

TIN125

ETHRXERA

SDA1A

P11.13

O0

TOUT125

O1

­

O2

­

O3

­

O4

­

O5

SDA1

O6

­

O7

C8

P11.14

I

TIN126

ETHCRSDVB

ETHRXDVB

ETHCRSA

SCL1A

P11.14

O0

TOUT126

O1

­

O2

­

O3

­

O4

­

O5

SCL1

O6

­

O7

C7

P11.15

I

TIN127

ETHCOL

P11.15

O0

TOUT127

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

Type LP / PU1 / VFLEX
LP / PU1 / VFLEX
LP / PU1 / VFLEX

Function General-purpose input GTM input ETH input I2C1 input General-purpose output GTM output Reserved Reserved Reserved Reserved I2C1 output Reserved General-purpose input GTM input ETH input ETH input ETH input I2C1 input General-purpose output GTM output Reserved Reserved Reserved Reserved I2C1 output Reserved General-purpose input GTM input ETH input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved

Data Sheet

TOC-155

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-32 Port 12 Functions

Pin

Symbol

A11

P12.0

TIN128

ETHRXCLKC

RXDCAN0C

P12.0

TOUT128

­

­

­

­

ETHMDC

­

B11

P12.1

TIN129

P12.1

TOUT129

ASLSO3

­

­

TXDCAN0

­

­

ETHMDIOC

Ctrl

Type

I

LP /

PU1 /

VFLEX

O0 O1 O2 O3 O4 O5 O6 O7 I
O0 O1 O2 O3 O4 O5 O6 O7 HWOU T

LP / PU1 / VFLEX

Function General-purpose input GTM input ETH input CAN node 0 input General-purpose output GTM output Reserved Reserved Reserved Reserved ETH output Reserved General-purpose input GTM input General-purpose output GTM output ASCLIN3 output Reserved Reserved CAN node 0 output Reserved Reserved ETH input/output

Table 2-33 Port 13 Functions

Pin

Symbol

Ctrl Type

Function

C17

P13.0

TIN91

P13.0

I

LVDSM_N / General-purpose input

PU1 / VEXT O0

GTM input General-purpose output

TOUT91

O1

GTM output

END03

O2

MSC0 output

SCLK2N

O3

QSPI2 output (LVDS)

EN01

O4

MSC0 output

FCLN0

O5

MSC0 output (LVDS)

FCLND0

O6

MSC0 output (LVDS)

­

O7

Reserved

Data Sheet

TOC-156

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-33 Port 13 Functions (cont'd)

Pin

Symbol

Ctrl

C18

P13.1

I

TIN92

SCL0B

P13.1

O0

TOUT92

O1

­

O2

SCLK2P

O3

­

O4

FCLP0

O5

SCL0

O6

­

O7

D17

P13.2

I

TIN93

CAPINA

SDA0B

P13.2

O0

TOUT93

O1

­

O2

MTSR2N

O3

FCLP0

O4

SON0

O5

SDA0

O6

SOND0

O7

C16

P13.3

I

TIN94

P13.3

O0

TOUT94

O1

­

O2

MTSR2P

O3

­

O4

SOP0

O5

­

O6

­

O7

Type LVDSM_P / PU1 / VEXT
LVDSM_N / PU1 / VEXT
LVDSM_P / PU1 / VEXT

Function General-purpose input GTM input I2C0 input General-purpose output GTM output Reserved QSPI2 output (LVDS) Reserved MSC0 output (LVDS) I2C0 output Reserved General-purpose input GTM input GPT120 input I2C0 input General-purpose output GTM output Reserved QSPI2 output (LVDS) MSC0 output MSC0 output (LVDS) I2C0 output MSC0 output (LVDS) General-purpose input GTM input General-purpose output GTM output Reserved QSPI2 output (LVDS) Reserved MSC0 output (LVDS) Reserved Reserved

Data Sheet

TOC-157

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-33 Port 13 Functions (cont'd)

Pin

Symbol

Ctrl

B17

P13.4

I

TIN253

PSIRX4A

P13.4

O0

TOUT253

O1

END22

O2

­

O3

EN20

O4

FCLN2

O5

FCLND2

O6

­

O7

A17

P13.5

I

TIN254

P13.5

O0

TOUT254

O1

­

O2

­

O3

­

O4

FCLP2

O5

­

O6

­

O7

A16

P13.6

I

TIN255

P13.6

O0

TOUT255

O1

­

O2

­

O3

­

O4

SON2

O5

SOND2

O6

­

O7

Type LVDSM_N / PU1 / VEXT
LVDSM_P / PU1 / VEXT
LVDSM_N / PU1 / VEXT

Function General-purpose input GTM input PSI5 input General-purpose output GTM output MSC2 output Reserved MSC2 output MSC2 output (LVDS) MSC2 output (LVDS) Reserved General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved MSC2 output (LVDS) Reserved Reserved General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved MSC2 output (LVDS) MSC2 output (LVDS) Reserved

Data Sheet

TOC-158

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-33 Port 13 Functions (cont'd)

Pin

Symbol

Ctrl

B16

P13.7

I

TIN256

P13.7

O0

TOUT256

O1

­

O2

­

O3

­

O4

SOP2

O5

­

O6

­

O7

C12

P13.9

I

TIN248

SCL1B

P13.9

O0

TOUT248

O1

ATX3

O2

SLSO55

O3

­

O4

TXDCANr1

O5

SCL1

O6

­

O7

A13

P13.10

I

TIN251

PSIRX3A

P13.10

O0

TOUT251

O1

ATX0

O2

­

O3

­

O4

­

O5

­

O6

­

O7

Type LVDSM_P / PU1 / VEXT
MP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved MSC2 output (LVDS) Reserved Reserved General-purpose input GTM input I2C1 input General-purpose output GTM output ASCLIN3 output QSPI5 output Reserved CAN node 1 output (MultiCANr+) I2C1 output Reserved General-purpose input GTM input PSI5 input General-purpose output GTM output ASCLIN0 output Reserved Reserved Reserved Reserved Reserved

Data Sheet

TOC-159

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-33 Port 13 Functions (cont'd)

Pin

Symbol

Ctrl

B13

P13.11

I

TIN250

ARX0E

P13.11

O0

TOUT250

O1

­

O2

­

O3

­

O4

PSITX3

O5

­

O6

­

O7

B12

P13.12

I

TIN249

ARX3H

RXDCANr1B

SDA1B

P13.12

O0

TOUT249

O1

­

O2

­

O3

­

O4

­

O5

SDA1

O6

­

O7

A12

P13.14

I

TIN252

P13.14

O0

TOUT252

O1

­

O2

SLSO54

O3

­

O4

­

O5

­

O6

­

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input ASCLIN0 input General-purpose output GTM output Reserved Reserved Reserved PSI5 output Reserved Reserved General-purpose input GTM input ASCLIN3 input CAN node 1 input (MultiCANr+) I2C1 input General-purpose output GTM output Reserved Reserved Reserved Reserved I2C1 output Reserved General-purpose input GTM input General-purpose output GTM output Reserved QSPI5 output Reserved Reserved Reserved Reserved

Data Sheet

TOC-160

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-34 Port 14 Functions

Pin

Symbol

Ctrl Type Function

C21

P14.0

TIN80

SENT12D

I

MP+ / General-purpose input

PU1 / VEXT

GTM input SENT input

P14.0

O0

General-purpose output

TOUT80

O1

GTM output

ATX0

O2

ASCLIN0 output

Recommended as Boot loader pin

TXD0A

O3

ERAY0 output

TXD0B

O4

ERAY0 output

TXDCAN1

O5

CAN node 1 output Used for single pin DAP (SPD) function

ASCLK0

O6

ASCLIN0 output

COUT62

O7

CCU60 output

D21

P14.1

TIN81

REQ15

I

MP /

General-purpose input

PU1 / VEXT

GTM input SCU input

SENT13D

SENT input

ARX0A

ASCLIN0 input Recommended as Boot loader pin

RXDCAN1B

CAN node 1 input Used for single pin DAP (SPD) function

RXD0A3

ERAY0 input

RXD0B3

ERAY0 input

EVRWUPA

SCU input

P14.1

O0

General-purpose output

TOUT81

O1

GTM output

ATX0

O2

ASCLIN0 output

Recommended as Boot loader pin.

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

COUT63

O7

CCU60 output

Data Sheet

TOC-161

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-34 Port 14 Functions (cont'd)

Pin

Symbol

Ctrl

D20

P14.2

I

TIN82

HWCFG2 EVR13

P14.2

O0

TOUT82

O1

ATX2

O2

SLSO21

O3

­

O4

­

O5

ASCLK2

O6

­

O7

C14

P14.3

I

TIN83

ARX2A

REQ10

HWCFG3_BMI

SDI02

P14.3

O0

TOUT83

O1

ATX2

O2

SLSO23

O3

ASLSO1

O4

ASLSO3

O5

­

O6

­

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input SCU input Latched at cold power on reset to decide EVR13 activation. General-purpose output GTM output ASCLIN2 output QSPI2 output Reserved Reserved ASCLIN2 output Reserved General-purpose input GTM input ASCLIN2 input SCU input SCU input MSC0 input General-purpose output GTM output ASCLIN2 output QSPI2 output ASCLIN1 output ASCLIN3 output Reserved Reserved

Data Sheet

TOC-162

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-34 Port 14 Functions (cont'd)

Pin

Symbol

Ctrl

D13

P14.4

I

TIN84

HWCFG6

P14.4

O0

TOUT84

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

C20

P14.5

I

TIN85

HWCFG1 EVR33

P14.5

O0

TOUT85

O1

­

O2

­

O3

­

O4

­

O5

TXD0B

O6

TXD1B

O7

C13

P14.6

I

TIN86

HWCFG0 DCLDO

P14.6

O0

TOUT86

O1

­

O2

SLSO22

O3

­

O4

­

O5

TXEN0B

O6

TXEN1B

O7

Type LP / PU1 / VEXT
MP+ / PU1 / VEXT
MP+ / PU1 / VEXT

Function General-purpose input GTM input SCU input Latched at cold power on reset to decide default pad reset state (PU or HighZ). General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved General-purpose input GTM input SCU input Latched at cold power on reset to decide EVR33 activation. General-purpose output GTM output Reserved Reserved Reserved Reserved ERAY0 output ERAY1 output General-purpose input GTM input SCU input If EVR13 active, latched at cold power on reset to decide between LDO and SMPS mode. General-purpose output GTM output Reserved QSPI2 output Reserved Reserved ERAY0 output ERAY1 output

Data Sheet

TOC-163

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-34 Port 14 Functions (cont'd)

Pin

Symbol

Ctrl

D12

P14.7

I

TIN87

RXD0B0

RXD1B0

P14.7

O0

TOUT87

O1

ARTS0

O2

SLSO24

O3

­

O4

­

O5

­

O6

­

O7

A14

P14.8

I

TIN88

ARX1D

RXDCAN2D

RXD0A0

RXD1A0

P14.8

O0

TOUT88

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

C19

P14.9

I

TIN89

ACTS0A

P14.9

O0

TOUT89

O1

END03

O2

EN01

O3

­

O4

TXEN0B

O5

TXEN0A

O6

TXEN1A

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT
MP+ / PU1 / VEXT

Function General-purpose input GTM input ERAY0 input ERAY1 input General-purpose output GTM output ASCLIN0 output QSPI2 output Reserved Reserved Reserved Reserved General-purpose input GTM input ASCLIN1 input CAN node 2 input ERAY0 input ERAY1 input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved General-purpose input GTM input ASCLIN0 input General-purpose output GTM output MSC0 output MSC0 output Reserved ERAY0 output ERAY0 output ERAY1 output

Data Sheet

TOC-164

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-34 Port 14 Functions (cont'd)

Pin

Symbol

Ctrl

C15

P14.10

I

TIN90

P14.10

O0

TOUT90

O1

END02

O2

EN00

O3

ATX1

O4

TXDCAN2

O5

TXD0A

O6

TXD1A

O7

A19

P14.11

I

TIN258

P14.11

O0

TOUT258

O1

END20

O2

PSITX4

O3

EN22

O4

SOP2

O5

­

O6

­

O7

A15

P14.12

I

TIN261

SDI20

P14.12

O0

TOUT261

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

Type MP+ / PU1 / VEXT
LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input General-purpose output GTM output MSC0 output MSC0 output ASCLIN1 output CAN node 2 output ERAY0 output ERAY1 output General-purpose input GTM input General-purpose output GTM output MSC2 output PSI5 output MSC2 output MSC2 output Reserved Reserved General-purpose input GTM input MSC2 input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved

Data Sheet

TOC-165

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-34 Port 14 Functions (cont'd)

Pin

Symbol

Ctrl

B19

P14.13

I

TIN260

P14.13

O0

TOUT260

O1

END23

O2

­

O3

EN21

O4

­

O5

­

O6

­

O7

B15

P14.14

I

TIN259

P14.14

O0

TOUT259

O1

END22

O2

­

O3

EN20

O4

­

O5

­

O6

­

O7

B14

P14.15

I

TIN263

INJ21

P14.15

O0

TOUT263

O1

ATX1

O2

­

O3

­

O4

­

O5

­

O6

­

O7

Type MP+ / PU1 / VEXT
MP+ / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input General-purpose output GTM output MSC2 output Reserved MSC2 output Reserved Reserved Reserved General-purpose input GTM input General-purpose output GTM output MSC2 output Reserved MSC2 output Reserved Reserved Reserved General-purpose input GTM input MSC2 output General-purpose output GTM output ASCLIN1 output Reserved Reserved Reserved Reserved Reserved

Data Sheet

TOC-166

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-35 Port 15 Functions

Pin

Symbol

C22

P15.1

TIN72

REQ16

ARX1A

RXDCAN2A

SLSI2B

EVRWUPB

P15.1

TOUT72

ATX1

SLSO25

­

­

­

­

B21

P15.2

TIN73

SLSI2A

MRST2E

SENT10D

HSIC2INA

P15.2

TOUT73

ATX0

SLSO20

­

TXDCAN1

ASCLK0

­

Ctrl Type Function

I

LP /

General-purpose input

PU1 / VEXT

GTM input SCU input

ASCLIN1 input

CAN node 2 input

QSPI2 input

SCU input

O0

General-purpose output

O1

GTM output

O2

ASCLIN1 output

O3

QSPI2 output

O4

Reserved

O5

Reserved

O6

Reserved

O7

Reserved

I

MP /

General-purpose input

PU1 / VEXT

GTM input QSPI2 input

QSPI2 input

SENT input

QSPI2 input

O0

General-purpose output

O1

GTM output

O2

ASCLIN0 output

O3

QSPI2 output

O4

Reserved

O5

CAN node 1 output

O6

ASCLIN0 output

O7

Reserved

Data Sheet

TOC-167

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-35 Port 15 Functions (cont'd)

Pin

Symbol

Ctrl

D18

P15.3

I

TIN74

ARX0B

SCLK2A

RXDCAN1A

HSIC2INB

P15.3

O0

TOUT74

O1

ATX0

O2

SCLK2

O3

END03

O4

EN01

O5

­

O6

­

O7

A21

P15.4

I

TIN75

MRST2A

REQ0

SCL0C

SENT11D

P15.4

O0

TOUT75

O1

ATX1

O2

MRST2

O3

­

O4

­

O5

SCL0

O6

CC62

O7

Type MP / PU1 / VEXT
MP / PU1 / VEXT

Function General-purpose input GTM input ASCLIN0 input QSPI2 input CAN node 1 input QSPI2 input General-purpose output GTM output ASCLIN0 output QSPI2 output MSC0 output MSC0 output Reserved Reserved General-purpose input GTM input QSPI2 input SCU input I2C0 input SENT input General-purpose output GTM output ASCLIN1 output QSPI2 output Reserved Reserved I2C0 output CCU60 output

Data Sheet

TOC-168

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-35 Port 15 Functions (cont'd)

Pin

Symbol

Ctrl

D19

P15.5

I

TIN76

ARX1B

MTSR2A

REQ13

SDA0C

P15.5

O0

TOUT76

O1

ATX1

O2

MTSR2

O3

END02

O4

EN00

O5

SDA0

O6

CC61

O7

B20

P15.6

I

TIN77

MTSR2B

P15.6

O0

TOUT77

O1

ATX3

O2

MTSR2

O3

SLSO53

O4

SCLK2

O5

ASCLK3

O6

CC60

O7

A20

P15.7

I

TIN78

ARX3A

MRST2B

P15.7

O0

TOUT78

O1

ATX3

O2

MRST2

O3

­

O4

­

O5

­

O6

COUT60

O7

Type MP / PU1 / VEXT
MP / PU1 / VEXT
MP / PU1 / VEXT

Function General-purpose input GTM input ASCLIN1 input QSPI2 input SCU input I2C0 input General-purpose output GTM output ASCLIN1 output QSPI2 output MSC0 output MSC0 output I2C0 output CCU60 output General-purpose input GTM input QSPI2 input General-purpose output GTM output ASCLIN3 output QSPI2 output QSPI5 output QSPI2 output ASCLIN3 output CCU60 output General-purpose input GTM input ASCLIN3 input QSPI2 input General-purpose output GTM output ASCLIN3 output QSPI2 output Reserved Reserved Reserved CCU60 output

Data Sheet

TOC-169

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-35 Port 15 Functions (cont'd)

Pin

Symbol

Ctrl

D16

P15.8

I

TIN79

SCLK2B

REQ1

P15.8

O0

TOUT79

O1

­

O2

SCLK2

O3

­

O4

­

O5

ASCLK3

O6

COUT61

O7

Type
MP / PU1 / VEXT

Function General-purpose input GTM input QSPI2 input SCU input General-purpose output GTM output Reserved QSPI2 output Reserved Reserved ASCLIN3 output CCU60 output

Table 2-36 Port 20 Functions

Pin

Symbol

A24

P20.0

TIN59

RXDCAN3C

RXDCANr1C

T6EUDA

REQ9

SYSCLK

TGI0

P20.0

TOUT59

ATX3

ASCLK3

­

SYSCLK

­

­

TGO0

Ctrl Type

I

MP /

PU1 /

VEXT

O0 O1 O2 O3 O4 O5 O6 O7 HWOU T

Function General-purpose input GTM input CAN node 3 input CAN node 1 input (MultiCANr+) GPT120 input SCU input HSCT input OCDS input General-purpose output GTM output ASCLIN3 output ASCLIN3 output Reserved HSCT output Reserved Reserved OCDS; ENx

Data Sheet

TOC-170

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-36 Port 20 Functions (cont'd)

Pin

Symbol

Ctrl

B23

P20.2

I

TESTMODE

P20.2

O0

­

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

Type
LP / PU1 / VEXT

Function General-purpose input This pin is latched at power on reset release to enter test mode. OCDS input Output function not available Output function not available Output function not available Output function not available Output function not available Output function not available Output function not available Output function not available

Table 2-37 Port 21 Functions

Pin

Symbol

Ctrl

J23

P21.0

I

TIN51

MRST4DN

HOLD

P21.0

O0

TOUT51

O1

­

O2

­

O3

­

O4

­

O5

ETHMDC

O6

BAABA0

O7

HSM1

O

Type
LVDSH_N/ PU1 / VDDP3

Function General-purpose input GTM input QSPI4 input (LVDS) EBU input General-purpose output GTM output Reserved Reserved Reserved Reserved ETH output EBU output (combined for BAA and BA0) HSM output

Data Sheet

TOC-171

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-37 Port 21 Functions (cont'd)

Pin

Symbol

Ctrl

G24

P21.1

I

TIN52

ETHMDIOB

MRST4DP

WAIT

P21.1

O0

TOUT52

O1

­

O2

­

O3

­

O4

­

O5

ETHMDIO

O6

BREQBA1

O7

HSM2

O

H23

P21.2

I

TIN53

MRST2CN

MRST4CN

ARX3GN

EMGSTOPB

RXDN

P21.2

O0

TOUT53

O1

ASLSO3

O2

­

O3

­

O4

ETHMDC

O5

SDRAMA8

O6

­

O7

Type LVDSH_P/ PU1 / VDDP3
LVDSH_N/ PU1 / VDDP3

Function General-purpose input GTM input ETH input (Not for production purposes) QSPI4 input (LVDS) EBU input General-purpose output GTM output Reserved Reserved Reserved Reserved ETH output (Not for production purposes) EBU output (combined for BREQ and BA1) HSM output General-purpose input GTM input QSPI2 input (LVDS) QSPI4 input (LVDS) ASCLIN3 input (LVDS) SCU input HSCT input (LVDS) General-purpose output GTM output ASCLIN3 output Reserved Reserved ETH output EBU output Reserved

Data Sheet

TOC-172

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-37 Port 21 Functions (cont'd)

Pin

Symbol

Ctrl

Type

G23

P21.3

TIN54

MRST2CP

I

LVDSH_P/

PU1 /

VDDP3

MRST4CP

ARX3GP

RXDP

P21.3

O0

TOUT54

O1

­

O2

­

O3

­

O4

­

O5

SDRAMA9

O6

­

O7

ETHMDIOD

HWOUT

D26

P21.4

TIN55

P21.4

I

LVDSH_N/

PU1 /

O0

VDDP3

TOUT55

O1

­

O2

­

O3

­

O4

­

O5

SDRAMA10

O6

­

O7

TXDN

HSCT

C26

P21.5

TIN56

P21.5

I

LVDSH_P/

PU1 /

VDDP3 O0

TOUT56

O1

ASCLK3

O2

­

O3

­

O4

­

O5

SDRAMA11

O6

­

O7

TXDP

HSCT

Function General-purpose input GTM input QSPI2 input (LVDS) QSPI4 input (LVDS) ASCLIN3 input (LVDS) HSCT input (LVDS) General-purpose output GTM output Reserved Reserved Reserved Reserved EBU output Reserved ETH input/output General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved EBU output Reserved HSCT output (LVDS) General-purpose input GTM input General-purpose output GTM output ASCLIN3 output Reserved Reserved Reserved EBU output Reserved HSCT output (LVDS)

Data Sheet

TOC-173

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-37 Port 21 Functions (cont'd)

Pin

Symbol

Ctrl

Type

E25

P21.6

TIN57

ARX3F

I

A2 /

PU /

VDDP3

TGI2

TDI

T5EUDA

P21.6

O0

TOUT57

O1

ASLSO3

O2

­

O3

­

O4

SYSCLK

O5

SDRAMA12

O6

T3OUT

O7

TGO2

HWOUT

D25

P21.7

TIN58

DAP2

I

A2 /

PU /

VDDP3

TGI3 ETHRXERB T5INA P21.7 TOUT58 ATX3 ASCLK3 ­ ­ SDRAMA13 T6OUT TGO3 TDO

O0 O1 O2 O3 O4 O5 O6 O7 HWOUT

DAP2

Function General-purpose input GTM input ASCLIN3 input OCDS input OCDS (JTAG) input GPT120 input General-purpose output GTM output ASCLIN3 output Reserved Reserved HSCT output EBU output GPT120 output OCDS; ENx General-purpose input GTM input OCDS (3-Pin DAP) input In the 3-Pin DAP mode this pin is used as DAP2. In the 2-PIN DAP mode this pin is used as P21.7 and controlled by the related port control logic OCDS input ETH input GPT120 input General-purpose output GTM output ASCLIN3 output ASCLIN3 output Reserved Reserved EBU output GPT120 output OCDS; ENx OCDS (JTAG); ENx The JTAG TDO function is overlayed with P21.7 via a double bond. In JTAG mode this pin is used as TDO, after power-on reset it is HighZ. OCDS (3-Pin DAP); ENx In the 3-Pin DAP mode this pin is used as DAP2.

Data Sheet

TOC-174

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-38 Port 22 Functions

Pin

Symbol

K23

P22.0

TIN47

MTSR4B

P22.0

TOUT47

ATX3N

MTSR4

SCLK4N

FCLN1

FCLND1

­

J24

P22.1

TIN48

MRST4B

P22.1

TOUT48

ATX3P

MRST4

SCLK4P

FCLP1

­

­

J25

P22.2

TIN49

SLSI4B

P22.2

TOUT49

­

SLSO43

MTSR4N

SON1

SOND1

­

Ctrl Type

I

LVDSM_N /

PU1 /

VEXT

O0

O1

O2

O3

O4

O5

O6

O7

I

LVDSM_P /

PU1 /

VEXT

O0

O1

O2

O3

O4

O5

O6

O7

I

LVDSM_N /

PU1 /

VEXT

O0 O1 O2 O3 O4 O5 O6 O7

Function General-purpose input GTM input QSPI4 input General-purpose output GTM output ASCLIN3 output (LVDS) QSPI4 output QSPI4 output (LVDS) MSC1 output (LVDS) MSC1 output (LVDS) Reserved General-purpose input GTM input QSPI4 input General-purpose output GTM output ASCLIN3 output (LVDS) QSPI4 output QSPI4 output (LVDS) MSC1 output (LVDS) Reserved Reserved General-purpose input GTM input QSPI4 input General-purpose output GTM output Reserved QSPI4 output QSPI4 output (LVDS) MSC1 output (LVDS) MSC1 output (LVDS) Reserved

Data Sheet

TOC-175

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-38 Port 22 Functions (cont'd)

Pin

Symbol

Ctrl

J26

P22.3

I

TIN50

SCLK4B

P22.3

O0

TOUT50

O1

­

O2

SCLK4

O3

MTSR4P

O4

SOP1

O5

­

O6

­

O7

Type
LVDSM_P / PU1 / VEXT

Function General-purpose input GTM input QSPI4 input General-purpose output GTM output Reserved QSPI4 output QSPI4 output (LVDS) MSC1 output (LVDS) Reserved Reserved

Table 2-39 Port 23 Functions

Pin

Symbol

Ctrl Type

Function

M26

P23.0

TIN41

P23.0

I

LP /

General-purpose input

PU1 /

GTM input

VEXT

O0

General-purpose output

TOUT41

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

L24

P23.1

TIN42

SDI10

I

MP+ / General-purpose input

PU1 / VEXT

GTM input MSC1 input

P23.1

O0

General-purpose output

TOUT42

O1

GTM output

ARTS1

O2

ASCLIN1 output

SLSO46

O3

QSPI4 output

GTMCLK0

O4

GTM output

­

O5

Reserved

EXTCLK0

O6

SCU output

­

O7

Reserved

Data Sheet

TOC-176

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-39 Port 23 Functions (cont'd)

Pin

Symbol

Ctrl

L25

P23.2

I

TIN43

P23.2

O0

TOUT43

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

L26

P23.3

I

TIN44

INJ10

P23.3

O0

TOUT44

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

K24

P23.4

I

TIN45

P23.4

O0

TOUT45

O1

­

O2

SLSO45

O3

END12

O4

EN10

O5

­

O6

­

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT
MP+ / PU1 / VEXT

Function General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved General-purpose input GTM input MSC1 input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved General-purpose input GTM input General-purpose output GTM output Reserved QSPI4 output MSC1 output MSC1 output Reserved Reserved

Data Sheet

TOC-177

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-39 Port 23 Functions (cont'd)

Pin

Symbol

Ctrl

K25

P23.5

I

TIN46

P23.5

O0

TOUT46

O1

­

O2

SLSO44

O3

END13

O4

EN11

O5

­

O6

­

O7

K26

P23.6

I

TIN138

P23.6

O0

TOUT138

O1

­

O2

­

O3

SLSO011

O4

­

O5

­

O6

­

O7

Type MP+ / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input General-purpose output GTM output Reserved QSPI4 output MSC1 output MSC1 output Reserved Reserved General-purpose input GTM input General-purpose output GTM output Reserved Reserved QSPI0 output Reserved Reserved Reserved

Table 2-40 Port 24 Functions

Pin

Symbol

U23

P24.0

TIN222

P24.0

TOUT222

­

­

­

­

­

­

DQ11

A11

Ctrl Type

I

A2 /

PU1 /

VEBU O0

O1

O2

O3

O4

O5

O6

O7

HWOU T

Function General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU Data Bus Line (SDRAM) EBU output

Data Sheet

TOC-178

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-40 Port 24 Functions (cont'd)

Pin

Symbol

Ctrl Type

T24

P24.1

TIN223

P24.1

I

A2 /

PU1 /

VEBU O0

TOUT223

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

DQ15 A15

HWOU T

T25

P24.2

TIN224

P24.2

I

A2 /

PU1 /

VEBU O0

TOUT224

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

DQ14 A14

HWOU T

T26

P24.3

TIN225

P24.3

I

A2 /

PU1 /

VEBU O0

TOUT225

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

DQ13 A13

HWOU T

Function General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU Data Bus Line (SDRAM) EBU output General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU Data Bus Line (SDRAM) EBU output General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU Data Bus Line (SDRAM) EBU output

Data Sheet

TOC-179

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-40 Port 24 Functions (cont'd)

Pin

Symbol

Ctrl Type

R24

P24.4

TIN226

P24.4

I

A2 /

PU1 /

VEBU O0

TOUT226

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

DQ9 A9

HWOU T

R25

P24.5

TIN227

P24.5

I

A2 /

PU1 /

VEBU O0

TOUT227

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

DQ12 A12

HWOU T

R26

P24.6

TIN228

P24.6

I

A2 /

PU1 /

VEBU O0

TOUT228

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

DQ5 A5

HWOU T

Function General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU Data Bus Line (SDRAM) EBU output General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU Data Bus Line (SDRAM) EBU output General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU Data Bus Line (SDRAM) EBU output

Data Sheet

TOC-180

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-40 Port 24 Functions (cont'd)

Pin

Symbol

Ctrl Type

P24

P24.7

TIN229

P24.7

I

A2 /

PU1 /

VEBU O0

TOUT229

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

DQ8 A8

HWOU T

P25

P24.8

TIN230

P24.8

I

A2 /

PU1 /

VEBU O0

TOUT230

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

DQ10 A10

HWOU T

P26

P24.9

TIN231

P24.9

I

A2 /

PU1 /

VEBU O0

TOUT231

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

DQ6 A6

HWOU T

Function General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU Data Bus Line (SDRAM) EBU output General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU Data Bus Line (SDRAM) EBU output General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU Data Bus Line (SDRAM) EBU output

Data Sheet

TOC-181

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-40 Port 24 Functions (cont'd)

Pin

Symbol

Ctrl Type

N23

P24.10

TIN232

P24.10

I

A2 /

PU1 /

VEBU O0

TOUT232

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

DQ4 A4

HWOU T

N24

P24.11

TIN233

P24.11

I

A2 /

PU1 /

VEBU O0

TOUT233

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

DQ3 A3

HWOU T

N25

P24.12

TIN234

P24.12

I

A2 /

PU1 /

VEBU O0

TOUT234

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

DQ1 A1

HWOU T

Function General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU Data Bus Line (SDRAM) EBU output General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU Data Bus Line (SDRAM) EBU output General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU Data Bus Line (SDRAM) EBU output

Data Sheet

TOC-182

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-40 Port 24 Functions (cont'd)

Pin

Symbol

Ctrl Type

N26

P24.13

TIN235

P24.13

I

A2 /

PU1 /

VEBU O0

TOUT235

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

DQ2 A2

HWOU T

M24

P24.14

TIN236

P24.14

TOUT236

­

­

­

­

­

­

DQ0

A0

M25

P24.15

TIN237

P24.15

TOUT237

­

­

­

­

­

­

DQ7

A7

I

A2 /

PU1 /

VEBU O0

O1

O2

O3

O4

O5

O6

O7

HWOU T

I

A2 /

PU1 /

VEBU O0

O1

O2

O3

O4

O5

O6

O7

HWOU T

Function General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU Data Bus Line (SDRAM) EBU output
General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU Data Bus Line (SDRAM) EBU output General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU Data Bus Line (SDRAM) EBU output

Data Sheet

TOC-183

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-41 Port 25 Functions

Pin

Symbol

AA26 P25.0

TIN206

SDCLKI

P25.0

TOUT206

­

­

­

­

­

­

BFCLKO

SDCLKO

AA24 P25.1

TIN207

P25.1

TOUT207

­

­

­

­

­

­

RD

RAS

AA23 P25.2

TIN208

P25.2

TOUT208

­

­

­

­

­

­

RD/WR

WR

Ctrl Type

I

A2 /

PU1 /

VEBU

O0 O1 O2 O3 O4 O5 O6 O7 HWOU T

I

A2 /

PU1 /

VEBU O0

O1

O2

O3

O4

O5

O6

O7

HWOU T

I

A2 /

PU1 /

VEBU O0

O1

O2

O3

O4

O5

O6

O7

HWOU T

Function General-purpose input GTM input EBU input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU output EBU output General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU output EBU output General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU output EBU output

Data Sheet

TOC-184

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-41 Port 25 Functions (cont'd)

Pin

Symbol

Ctrl

Y24

P25.3

I

TIN209

HOLDA

P25.3

O0

TOUT209

O1

­

O2

­

O3

­

O4

­

O5

­

O6

BAABA0

O7

Type
A2 / PU1 / VEBU

CS2

DQM1

HOLDA

Y25

P25.4

TIN210

P25.4

TOUT210

­

­

­

­

­

­

CS1

DQM0

Y26

P25.5

TIN211

P25.5

TOUT211

­

­

­

­

­

­

CS0

HWOU T

I

A2 /

PU1 /

VEBU O0

O1

O2

O3

O4

O5

O6

O7

HWOU T

I

A2 /

PU1 /

VEBU O0

O1

O2

O3

O4

O5

O6

O7

HWOU T

Function General-purpose input GTM input EBU input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved EBU output (combined for BAA and BA0) EBU output EBU output EBU output General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU output EBU output General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU output

Data Sheet

TOC-185

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-41 Port 25 Functions (cont'd)

Pin

Symbol

Ctrl Type

W24

P25.7 TIN213 P25.7

I

A2 /

PU1 /

VEBU O0

TOUT213

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

ADV CAS

HWOU T

W25

P25.8 TIN214 P25.8

I

A2 /

PU1 /

VEBU O0

TOUT214

O1

­

O2

­

O3

­

O4

A23

O5

SDRAMA0

O6

­

O7

BC0

HWOU

T

W26

P25.9 TIN215 P25.9

I

A2 /

PU1 /

VEBU O0

TOUT215

O1

­

O2

­

O3

­

O4

A22

O5

SDRAMA1

O6

­

O7

BC1

HWOU

T

Function General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved EBU output EBU output General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved EBU output EBU output Reserved EBU output
General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved EBU output EBU output Reserved EBU output

Data Sheet

TOC-186

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-41 Port 25 Functions (cont'd)

Pin

Symbol

Ctrl Type

V24

P25.10

TIN216

P25.10

I

A2 /

PU1 /

VEBU O0

TOUT216

O1

­

O2

­

O3

­

O4

A21

O5

SDRAMA2

O6

­

O7

BC2

HWOU

T

V25

P25.11

TIN217

P25.11

I

A2 /

PU1 /

VEBU O0

TOUT217

O1

­

O2

­

O3

­

O4

A20

O5

SDRAMA3

O6

­

O7

BC3

HWOU

T

V26

P25.12

TIN218

P25.12

I

A2 /

PU1 /

VEBU O0

TOUT218

O1

­

O2

­

O3

­

O4

­

O5

SDRAMA4

O6

­

O7

A19

HWOU

T

Function General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved EBU output EBU output Reserved EBU output
General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved EBU output EBU output Reserved EBU output
General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved EBU output Reserved EBU output

Data Sheet

TOC-187

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-41 Port 25 Functions (cont'd)

Pin

Symbol

Ctrl Type

U24

P25.13

TIN219

P25.13

I

A2 /

PU1 /

VEBU O0

TOUT219

O1

­

O2

­

O3

­

O4

­

O5

SDRAMA5

O6

­

O7

A17

HWOU

T

U25

P25.14

TIN220

P25.14

I

A2 /

PU1 /

VEBU O0

TOUT220

O1

­

O2

­

O3

­

O4

­

O5

SDRAMA6

O6

­

O7

A18

HWOU

T

U26

P25.15

TIN221

P25.15

I

A2 /

PU1 /

VEBU O0

TOUT221

O1

­

O2

­

O3

­

O4

­

O5

SDRAMA7

O6

­

O7

A16

HWOU

T

Function General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved EBU output Reserved EBU output
General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved EBU output Reserved EBU output
General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved EBU output Reserved EBU output

Data Sheet

TOC-188

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-42 Port 26 Functions

Pin

Symbol

Ctrl Type

Function

AA25

P26.0 TIN212 BFCLKI

I

LP /

General-purpose input

PU1 /

GTM input

VFLEXE

EBU input

P26.0

O0

General-purpose output

TOUT212

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

Table 2-43 Port 30 Functions

Pin

Symbol

AF22 P30.0

TIN190

P30.0

TOUT190

­

­

­

­

­

­

AD14

AF23

P30.1 TIN191 P30.1 TOUT191 ­ ­ ­ ­ ­ ­ AD11

Ctrl Type

Function

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

O1

GTM output

O2

Reserved

O3

Reserved

O4

Reserved

O5

Reserved

O6

Reserved

O7

Reserved

HWOU T

EBU Address / Data Bus Line

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

O1

GTM output

O2

Reserved

O3

Reserved

O4

Reserved

O5

Reserved

O6

Reserved

O7

Reserved

HWOU T

EBU Address / Data Bus Line

Data Sheet

TOC-189

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-43 Port 30 Functions (cont'd)

Pin

Symbol

Ctrl Type

Function

AB24

P30.2 TIN192 P30.2

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT192

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD12

HWOU T

EBU Address / Data Bus Line

AC24

P30.3 TIN193 P30.3

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT193

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD15

HWOU T

EBU Address / Data Bus Line

AD24

P30.4 TIN194 P30.4

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT194

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD8

HWOU

EBU Address / Data Bus Line

T

Data Sheet

TOC-190

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-43 Port 30 Functions (cont'd)

Pin

Symbol

Ctrl Type

Function

AE24

P30.5 TIN195 P30.5

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT195

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD13

HWOU T

EBU Address / Data Bus Line

AF24

P30.6 TIN196 P30.6

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT196

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD4

HWOU

EBU Address / Data Bus Line

T

AB25

P30.7 TIN197 P30.7

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT197

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD7

HWOU

EBU Address / Data Bus Line

T

Data Sheet

TOC-191

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-43 Port 30 Functions (cont'd)

Pin

Symbol

Ctrl Type

Function

AC25

P30.8 TIN198 P30.8

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT198

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD3

HWOU

EBU Address / Data Bus Line

T

AD25

P30.9 TIN199 P30.9

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT199

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD0

HWOU

EBU Address / Data Bus Line

T

AE25

P30.10 TIN200 P30.10

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT200

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD5

HWOU

EBU Address / Data Bus Line

T

Data Sheet

TOC-192

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-43 Port 30 Functions (cont'd)

Pin

Symbol

Ctrl Type

Function

AF25

P30.11 TIN201 P30.11

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT201

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD10

HWOU T

EBU Address / Data Bus Line

AB26

P30.12 TIN202 P30.12

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT202

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD9

HWOU

EBU Address / Data Bus Line

T

AC26

P30.13 TIN203 P30.13

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT203

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD2

HWOU

EBU Address / Data Bus Line

T

Data Sheet

TOC-193

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-43 Port 30 Functions (cont'd)

Pin

Symbol

Ctrl Type

Function

AD26

P30.14 TIN204 P30.14

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT204

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD1

HWOU

EBU Address / Data Bus Line

T

AE26

P30.15 TIN205 P30.15

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT205

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD6

HWOU

EBU Address / Data Bus Line

T

Table 2-44 Port 31 Functions

Pin

Symbol

AD18 P31.0

TIN174

P31.0

TOUT174

­

­

­

­

­

­

AD30

Ctrl Type

Function

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

O1

GTM output

O2

Reserved

O3

Reserved

O4

Reserved

O5

Reserved

O6

Reserved

O7

Reserved

HWOU T

EBU Address / Data Bus Line

Data Sheet

TOC-194

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-44 Port 31 Functions (cont'd)

Pin

Symbol

Ctrl Type

Function

AE18

P31.1 TIN175 P31.1

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT175

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD29

HWOU T

EBU Address / Data Bus Line

AF18

P31.2 TIN176 P31.2

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT176

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD28

HWOU T

EBU Address / Data Bus Line

AD19

P31.3 TIN177 P31.3

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT177

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD26

HWOU T

EBU Address / Data Bus Line

Data Sheet

TOC-195

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-44 Port 31 Functions (cont'd)

Pin

Symbol

Ctrl Type

Function

AE19

P31.4 TIN178 P31.4

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT178

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD24

HWOU T

EBU Address / Data Bus Line

AF19

P31.5 TIN179 P31.5

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT179

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD23

HWOU T

EBU Address / Data Bus Line

AD20

P31.6 TIN180 P31.6

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT180

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD20

HWOU T

EBU Address / Data Bus Line

Data Sheet

TOC-196

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-44 Port 31 Functions (cont'd)

Pin

Symbol

Ctrl Type

Function

AE20

P31.7 TIN181 P31.7

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT181

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD16

HWOU T

EBU Address / Data Bus Line

AF20

P31.8 TIN182 P31.8

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT182

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD31

HWOU T

EBU Address / Data Bus Line

AD21

P31.9 TIN183 P31.9

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT183

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD27

HWOU T

EBU Address / Data Bus Line

Data Sheet

TOC-197

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-44 Port 31 Functions (cont'd)

Pin

Symbol

Ctrl Type

Function

AE21

P31.10 TIN184 P31.10

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT184

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD21

HWOU T

EBU Address / Data Bus Line

AF21

P31.11 TIN185 P31.11

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT185

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD25

HWOU T

EBU Address / Data Bus Line

AD22

P31.12 TIN186 P31.12

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT186

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD19

HWOU T

EBU Address / Data Bus Line

Data Sheet

TOC-198

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-44 Port 31 Functions (cont'd)

Pin

Symbol

Ctrl Type

Function

AE22

P31.13 TIN187 P31.13

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT187

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD22

HWOU T

EBU Address / Data Bus Line

AD23

P31.14 TIN188 P31.14

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT188

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD18

HWOU T

EBU Address / Data Bus Line

AE23

P31.15 TIN189 P31.15

I

MP /

General-purpose input

PU1 /

GTM input

VFLEXE

O0

General-purpose output

TOUT189

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

AD17

HWOU T

EBU Address / Data Bus Line

Data Sheet

TOC-199

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-45 Port 32 Functions

Pin

Symbol

Ctrl

AD17

P32.0

I

TIN36

FDEST

VGATE1N

Type
LP / PX/ VEXT

AE13 AF13

P32.0 TOUT36 ­ ­ ­ ­ ­ ­ P32.2 TIN38 ARX3D RXDCAN3B RXDCANr1D P32.2 TOUT38 ATX3 ­ ­ ­ DCDCSYNC ­ P32.3 TIN39 P32.3 TOUT39 ATX3 ­ ASCLK3 TXDCAN3 TXDCANr1 ­

O0

O1

O2

O3

O4

O5

O6

O7

I

LP /

PU1 /

VEXT

O0

O1

O2

O3

O4

O5

O6

O7

I

LP /

PU1 /

VEXT O0

O1

O2

O3

O4

O5

O6

O7

Function General-purpose input GTM input PMU input SMPS mode: analog output. External Pass Device gate control for EVR13 General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved General-purpose input GTM input ASCLIN3 input CAN node 3 input CAN node 1 input (MultiCANr+) General-purpose output GTM output ASCLIN3 output Reserved Reserved Reserved SCU output Reserved General-purpose input GTM input General-purpose output GTM output ASCLIN3 output Reserved ASCLIN3 output CAN node 3 output CAN node 1 output (MultiCANr+) Reserved

Data Sheet

TOC-200

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-45 Port 32 Functions (cont'd)

Pin

Symbol

Ctrl Type

AC14

P32.4 TIN40 ACTS1B

I

MP+ /

PU1 /

VEXT

SDI12

P32.4

O0

TOUT40

O1

­

O2

END12

O3

GTMCLK1

O4

EN10

O5

EXTCLK1

O6

COUT63

O7

AD14

P32.5 TIN140 P32.5

I

LP /

PU1 /

VEXT O0

TOUT140

O1

ATX2

O2

­

O3

­

O4

­

O5

TXDCAN2

O6

­

O7

AE17

P32.6 TGI4 TIN141

I

LP /

PU1 /

VEXT

RXDCAN2C

ARX2F

P32.6

O0

TOUT141

O1

­

O2

­

O3

SLSO212

O4

­

O5

­

O6

­

O7

TGO4

HWOU T

Function General-purpose input GTM input ASCLIN1 input MSC1 input General-purpose output GTM output Reserved MSC1 output GTM output MSC1 output SCU output CCU60 output General-purpose input GTM input General-purpose output GTM output ASCLIN2 output Reserved Reserved Reserved CAN node 2 output Reserved General-purpose input OCDS input GTM input CAN node 2 input ASCLIN2 input General-purpose output GTM output Reserved Reserved QSPI2 output Reserved Reserved Reserved OCDS; ENx

Data Sheet

TOC-201

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-45 Port 32 Functions (cont'd)

Pin

Symbol

Ctrl Type

AF17

P32.7 TIN142 TGI5

I

LP /

PU1 /

VEXT

P32.7

O0

TOUT142

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

TGO5

HWOU T

Function General-purpose input GTM input OCDS input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved OCDS; ENx

Table 2-46 Port 33 Functions

Pin

Symbol

Ctrl

AC11

P33.0

I

TIN22

DSITR0E

P33.0

O0

TOUT22

O1

­

O2

­

O3

­

O4

­

O5

VADCG2BFL0

O6

­

O7

Type
LP / PU1 / VEXT

Function General-purpose input GTM input DSADC channel 0 input E General-purpose output GTM output Reserved Reserved Reserved Reserved VADC output Reserved

Data Sheet

TOC-202

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-46 Port 33 Functions (cont'd)

Pin

Symbol

Ctrl

AD11

P33.1

I

TIN23

PSIRX0C

SENT9C

DSCIN2B

DSITR1E

P33.1

O0

TOUT23

O1

ASLSO3

O2

SCLK2

O3

DSCOUT2

O4

VADCEMUX02

O5

VADCG2BFL1

O6

­

O7

AE11

P33.2

I

TIN24

SENT8C

DSDIN2B

DSITR2E

P33.2

O0

TOUT24

O1

ASCLK3

O2

SLSO210

O3

PSITX0

O4

VADCEMUX01

O5

VADCG2BFL2

O6

­

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input PSI5 input SENT input DSADC channel 2 input B DSADC channel 1 input E General-purpose output GTM output ASCLIN3 output QSPI2 output DSADC channel 2 output VADC output VADC output Reserved General-purpose input GTM input SENT input DSADC channel 2 input B DSADC channel 2 input E General-purpose output GTM output ASCLIN3 output QSPI2 output PSI5 output VADC output VADC output Reserved

Data Sheet

TOC-203

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-46 Port 33 Functions (cont'd)

Pin

Symbol

Ctrl

AF11

P33.3

I

TIN25

PSIRX1C

SENT7C

DSCIN1B

P33.3

O0

TOUT25

O1

­

O2

­

O3

DSCOUT1

O4

VADCEMUX00

O5

VADCG2BFL3

O6

­

O7

AC12

P33.4

I

TIN26

SENT6C

CTRAPC

DSDIN1B

DSITR0F

P33.4

O0

TOUT26

O1

ARTS2

O2

SLSO212

O3

PSITX1

O4

VADCEMUX12

O5

VADCG0BFL0

O6

­

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input PSI5 input SENT input DSADC channel 1 input B General-purpose output GTM output Reserved Reserved DSADC channel 1 output VADC output VADC output Reserved General-purpose input GTM input SENT input CCU61 input DSADC channel 1 input DSADC channel 0 input F General-purpose output GTM output ASCLIN2 output QSPI2 output PSI5 output VADC output VADC output Reserved

Data Sheet

TOC-204

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-46 Port 33 Functions (cont'd)

Pin

Symbol

Ctrl

AD12

P33.5

I

TIN27

ACTS2B

PSIRX2C

PSISRXC

SENT5C

CCPOS2C

T4EUDB

DSCIN0B

DSITR1F

P33.5

O0

TOUT27

O1

SLSO07

O2

SLSO17

O3

DSCOUT0

O4

VADCEMUX11

O5

VADCG0BFL1

O6

­

O7

AE12

P33.6

I

TIN28

SENT4C

CCPOS1C

T2EUDB

DSDIN0B

DSITR2F

P33.6

O0

TOUT28

O1

ASLSO2

O2

SLSO211

O3

PSITX2

O4

VADCEMUX10

O5

VADCG1BFL0

O6

PSISTX

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input ASCLIN2 input PSI5 input PSI5-S input SENT input CCU61 input GPT120 input DSADC channel 0 input B DSADC channel 1 input F General-purpose output GTM output QSPI0 output QSPI1 output DSADC channel 0 output VADC output VADC output Reserved General-purpose input GTM input SENT input CCU61 input GPT120 input DSADC channel 0 input B DSADC channel 2 input F General-purpose output GTM output ASCLIN2 output QSPI2 output PSI5 output VADC output VADC output PSI5-S output

Data Sheet

TOC-205

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-46 Port 33 Functions (cont'd)

Pin

Symbol

Ctrl Type

AC15

P33.7 TIN29 RXDCAN0E

I

LP /

PU1 /

VEXT

REQ8

CCPOS0C

T2INB

P33.7

O0

TOUT29

O1

ASCLK2

O2

SLSO47

O3

­

O4

­

O5

VADCG1BFL1

O6

­

O7

AD15

P33.8 TIN30 ARX2E

I

MP /

HighZ /

VEXT

EMGSTOPA

P33.8

O0

TOUT30

O1

ATX2

O2

SLSO42

O3

­

O4

TXDCAN0

O5

­

O6

COUT62

O7

SMUFSP

HWOU T

AF12

P33.9 TIN31 HSIC3INA

I

LP /

PU1 /

VEXT

P33.9

O0

TOUT31

O1

ATX2

O2

SLSO41

O3

ASCLK2

O4

­

O5

­

O6

CC62

O7

Function General-purpose input GTM input CAN node 0 input SCU input CCU61 input GPT120 input General-purpose output GTM output ASCLIN2 output QSPI4 output Reserved Reserved VADC output Reserved General-purpose input GTM input ASCLIN2 input SCU input General-purpose output GTM output ASCLIN2 output QSPI4 output Reserved CAN node 0 output Reserved CCU61 output SMU
General-purpose input GTM input QSPI3 input General-purpose output GTM output ASCLIN2 output QSPI4 output ASCLIN2 output Reserved Reserved CCU61 output

Data Sheet

TOC-206

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-46 Port 33 Functions (cont'd)

Pin

Symbol

Ctrl

AE14

P33.10

I

TIN32

SLSI4A

HSIC3INB

P33.10

O0

TOUT32

O1

SLSO16

O2

SLSO40

O3

ASLSO1

O4

PSISCLK

O5

­

O6

COUT61

O7

AF14

P33.11

I

TIN33

SCLK4A

P33.11

O0

TOUT33

O1

ASCLK1

O2

SCLK4

O3

­

O4

­

O5

DSCGPWMN

O6

CC61

O7

AF15

P33.12

I

TIN34

MTSR4A

P33.12

O0

TOUT34

O1

ATX1

O2

MTSR4

O3

ASCLK1

O4

­

O5

DSCGPWMP

O6

COUT60

O7

Type MP / PU1 / VEXT
MP / PU1 / VEXT
MP / PU1 / VEXT

Function General-purpose input GTM input QSPI4 input QSPI3 input General-purpose output GTM output QSPI1 output QSPI4 output ASCLIN1 output PSI5-S output Reserved CCU61 output General-purpose input GTM input QSPI4 input General-purpose output GTM output ASCLIN1 output QSPI4 output Reserved Reserved DSADC channel output CCU61 output General-purpose input GTM input QSPI4 input General-purpose output GTM output ASCLIN1 output QSPI4 output ASCLIN1 output Reserved DSADC output CCU61 output

Data Sheet

TOC-207

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-46 Port 33 Functions (cont'd)

Pin

Symbol

Ctrl Type

AE15

P33.13 TIN35 ARX1F

I

MP /

PU1 /

VEXT

MRST4A

DSSGNB

INJ11

P33.13

O0

TOUT35

O1

ATX1

O2

MRST4

O3

SLSO26

O4

­

O5

DCDCSYNC

O6

CC60

O7

AC13

P33.14 TIN143 TGI6

I

LP /

PU1 /

VEXT

SCLK2D

P33.14

O0

TOUT143

O1

­

O2

SCLK2

O3

­

O4

­

O5

­

O6

CC62

O7

TGO6

HWOU T

Function General-purpose input GTM input ASCLIN1 input QSPI4 input DSADC channel input B MSC1 input General-purpose output GTM output ASCLIN1 output QSPI4 output QSPI2 output Reserved SCU output CCU61 output General-purpose input GTM input OCDS input QSPI2 input General-purpose output GTM output Reserved QSPI2 output Reserved Reserved Reserved CCU60 output OCDS; ENx

Data Sheet

TOC-208

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-46 Port 33 Functions (cont'd)

Pin

Symbol

Ctrl Type

AD13

P33.15 TIN144 TGI7

I

LP /

PU1 /

VEXT

P33.15

O0

TOUT144

O1

­

O2

SLSO211

O3

­

O4

­

O5

­

O6

COUT62

O7

TGO7

HWOU T

Function General-purpose input GTM input OCDS input General-purpose output GTM output Reserved QSPI2 output Reserved Reserved Reserved CCU60 output OCDS; ENx

Table 2-47 Port 34 Functions

Pin

Symbol

Ctrl

AC9

P34.1

I

TIN146

P34.1

O0

TOUT146

O1

ATX0

O2

­

O3

TXDCAN0

O4

TXDCANr0

O5

­

O6

COUT63

O7

AC10

P34.2

I

TIN147

ARX0D

RXDCAN0G

RXDCANr0C

P34.2

O0

TOUT147

O1

­

O2

­

O3

­

O4

­

O5

­

O6

CC60

O7

Data Sheet

Type LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input General-purpose output GTM output ASCLIN0 output Reserved CAN node 0 output CAN node 0 output (MultiCANr+) Reserved CCU60 output General-purpose input GTM input ASCLIN0 input CAN node 0 input CAN node 0 input (MultiCANr+) General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved CCU60 output

TOC-209

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-47 Port 34 Functions (cont'd)

Pin

Symbol

Ctrl

AF10

P34.3

I

TIN148

P34.3

O0

TOUT148

O1

­

O2

­

O3

SLSO210

O4

­

O5

­

O6

COUT60

O7

AD10

P34.4

I

TIN149

MRST2D

P34.4

O0

TOUT149

O1

­

O2

­

O3

MRST2

O4

­

O5

­

O6

CC61

O7

AE10

P34.5

I

TIN150

MTSR2D

P34.5

O0

TOUT150

O1

­

O2

­

O3

MTSR2

O4

­

O5

­

O6

COUT61

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input General-purpose output GTM output Reserved Reserved QSPI2 output Reserved Reserved CCU60 output General-purpose input GTM input QSPI2 input General-purpose output GTM output Reserved Reserved QSPI2 output Reserved Reserved CCU60 output General-purpose input GTM input QSPI2 input General-purpose output GTM output Reserved Reserved QSPI2 output Reserved Reserved CCU60 output

Data Sheet

TOC-210

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-48 Port 40 Functions

Pin

Symbol

Ctrl

AC7

P40.0

I

VADCG3.0

DS2PB

CCPOS0D

SENT0A

AD7

P40.1

I

VADCG3.1

DS2NB

CCPOS1B

SENT1A

AA2

P40.2

I

VADCG3.2

CCPOS1D

SENT2A

AB2

P40.3

I

VADCG3.3

CCPOS2B

SENT3A

W3

P40.4

I

VADCG4.0

CCPOS2D

SENT4A

Y3

P40.5

I

VADCG4.1

CCPOS0D

SENT5A

V4

P40.6

I

VADCG4.4

DS3PA

CCPOS1B

SENT6A

Type S / HighZ / VDDM
S / HighZ / VDDM
S / HighZ / VDDM
S / HighZ / VDDM
S / HighZ / VDDM
S / HighZ / VDDM
S / HighZ / VDDM

Function General-purpose input VADC analog input channel 0 of group 3 DSADC: positive analog input of channel 2, pin B CCU60 input SENT input General-purpose inpu.t VADC analog input channel 1 of group 3 (with pull down diagnostics) DSADC: negative analog input channel 2, pin B CCU60 input SENT input General-purpose inpu.t VADC analog input channel 2 of group 3 (with pull down diagnostics) CCU60 input SENT input General-purpose input VADC analog input channel 3 of group 3 (with pull down diagnostics) CCU60 input SENT input General-purpose input VADC analog input channel 0 of group 4 CCU60 input SENT input General-purpose input VADC analog input channel 1 of group 4 CCU61 input SENT input General-purpose input VADC analog input channel 4 of group 4 DSADC: positive analog input of channel 3, pin A CCU61 input SENT input

Data Sheet

TOC-211

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-48 Port 40 Functions (cont'd)

Pin

Symbol

Ctrl

V3

P40.7

I

VADCG4.5

DS3NA

CCPOS1D

SENT7A

V2

P40.11

I

VADCG10.4

DS8PA

SENT11A

W1

P40.12

I

VADCG10.5

DS8NA

SENT12A

U2

P40.13

I

VADCG10.6

DS9PA

SENT13A

V1

P40.14

I

VADCG10.7

DS9NA

SENT14A

Type S / HighZ / VDDM
S / HighZ / VDDM
S / HighZ / VDDM
S / HighZ / VDDM
S / HighZ / VDDM

Function General-purpose input VADC analog input channel 5 of group 4 DSADC: negative analog input channel 3, pin A CCU61 input SENT input General-purpose input VADC analog input channel 4 of group 10 DSADC: positive analog input of channel 8, pin A SENT input General-purpose input VADC analog input channel 5 of group 10 DSADC: positive analog input of channel 8, pin A SENT input General-purpose input VADC analog input channel 6 of group 10 DSADC: positive analog input of channel 9, pin A SENT input General-purpose input VADC analog input channel 7 of group 10 DSADC: positive analog input of channel 9, pin A SENT input

Table 2-49 Analog Inputs

Pin

Symbol

AC5

AN0

VADCG0.0

DS1PA

AD5

AN1

VADCG0.1

DS1NA

AE4

AN2

VADCG0.2

DS0PA

AF4

AN3

VADCG0.3

DS0NA

AC2

AN4

VADCG0.4

Ctrl Type

Function

I

D / HighZ / Analog input 0

VDDM

VADC analog input channel 0 of group 0

DSADC: positive analog input of channel 1, pin A

I

D / HighZ / Analog input 1

VDDM

VADC analog input channel 1 of group 0

DSADC: negative analog input channel 1, pin A

I

D / HighZ / Analog input 2

VDDM

VADC analog input channel 2 of group 0

DSADC: positive analog input of channel 0, pin A

I

D / HighZ / Analog input 3

VDDM

VADC analog input channel 3 of group 0

DSADC: negative analog input channel 0, pin A

I

D / HighZ / Analog input 4

VDDM

VADC analog input channel 4 of group 0

Data Sheet

TOC-212

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-49 Analog Inputs (cont'd)

Pin

Symbol

Ctrl

AA3

AN5

I

VADCG0.5

AD1

AN6

I

VADCG0.6

AB4

AN7

I

VADCG0.7

AC4

AN8

I

VADCG1.0

AD4

AN9

I

VADCG1.1

AE3

AN10

I

VADCG1.2

AF3

AN11

I

VADCG1.3

AC3

AN16

I

VADCG2.0

AD3

AN17

I

VADCG2.1

AE2

AN18

I

VADCG2.2

AF2

AN19

I

VADCG2.3

AC8

AN20

I

VADCG2.4

DS2PA

AD8

AN21

I

VADCG2.5

DS2NA

AE8

AN22

I

VADCG2.6

AF8

AN23

I

VADCG2.7

AC7

AN24

I

VADCG3.0

DS2PB

SENT0A

Type

Function

D / HighZ / Analog input 5

VDDM

VADC analog input channel 5 of group 0

D / HighZ / Analog input 6

VDDM

VADC analog input channel 6 of group 0

D / HighZ / Analog input 7

VDDM

VADC analog input channel 7 of group 0

D / HighZ / Analog input 8

VDDM

VADC analog input channel 0 of group 1

D / HighZ / Analog input 9

VDDM

VADC analog input channel 1 of group 1

D / HighZ / Analog input 10

VDDM

VADC analog input channel 2 of group 1

D / HighZ / Analog input 11

VDDM

VADC analog input channel 3 of group 1 (with pull

down diagnostics)

D / HighZ / Analog input 16

VDDM

VADC analog input channel 0 of group 2

D / HighZ / Analog input 17

VDDM

VADC analog input channel 1 of group 2

D / HighZ / Analog input 18

VDDM

VADC analog input channel 2 of group 2

D / HighZ / Analog input 19

VDDM

VADC analog input channel 3 of group 2 (with pull

down diagnostics)

D / HighZ / Analog input 20

VDDM

VADC analog input channel 4 of group 2

DSADC: positive analog input of channel 2, pin A

D / HighZ / Analog input 21

VDDM

VADC analog input channel 5 of group 2

DSADC: negative analog input channel 2, pin A

D / HighZ / Analog input 22

VDDM

VADC analog input channel 6 of group 2

D / HighZ / Analog input 23

VDDM

VADC analog input channel 7 of group 2

S / HighZ / VDDM

Analog input 24 VADC analog input channel 0 of group 3 DSADC: positive analog input of channel 2, pin B

SENT input channel 0, pin A

Data Sheet

TOC-213

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-49 Analog Inputs (cont'd)

Pin

Symbol

Ctrl

AD7

AN25

I

VADCG3.1

DS2NB

SENT1A

AA2

AN26

I

VADCG3.2

SENT2A

AB2

AN27

I

VADCG3.3

SENT3A

AB1

AN28

I

VADCG3.4

AC1

AN29

I

VADCG3.5

W3

AN32

I

VADCG4.0

SENT4A

Y3

AN33

I

VADCG4.1

SENT5A

V4

AN36

I

VADCG4.4

DS3PA

SENT6A

V3

AN37

I

VADCG4.5

DS3NA

SENT7A

U4

AN40

I

VADCG5.0

U3

AN41

I

VADCG5.1

T1

AN42

I

VADCG5.2

Type

Function

S / HighZ / VDDM

Analog input 24
VADC analog input channel 1 of group 3 (with pull down diagnostics)

DSADC: negative analog input channel 2, pin B

SENT input channel 1, pin A

S / HighZ / VDDM

Analog input 26
VADC analog input channel 2 of group 3 (with pull down diagnostics)

SENT input channel 2, pin A

S / HighZ / VDDM

Analog input 27
VADC analog input channel 3 of group 3 (with pull down diagnostics)

SENT input channel 3, pin A

D / HighZ / Analog input 28

VDDM

VADC analog input channel 4 of group 3 (with pull

down diagnostics)

D / HighZ / Analog input 29

VDDM

VADC analog input channel 5 of group 3 (with pull

down diagnostics)

S / HighZ / VDDM

Analog input 32 VADC analog input channel 0 of group 4 SENT input channel 4, pin A

S / HighZ / VDDM

Analog input 33 VADC analog input channel 1 of group 4 SENT input channel 5, pin A

S / HighZ / VDDM

Analog input 34 VADC analog input channel 4 of group 4 DSADC: positive analog input of channel 3, pin A

SENT input channel 6, pin A

S / HighZ / VDDM

Analog input 37 VADC analog input channel 5 of group 4 DSADC: negative analog input channel 3, pin A

SENT input channel 7, pin A

D / HighZ / Analog input 40

VDDM

VADC analog input channel 0 of group 5

D / HighZ / Analog input 41

VDDM

VADC analog input channel 1 of group 5

D / HighZ / Analog input 42

VDDM

VADC analog input channel 2 of group 5

Data Sheet

TOC-214

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-49 Analog Inputs (cont'd)

Pin

Symbol

Ctrl

U1

AN43

I

VADCG5.3

AD2

AN48

I

VADCG8.0

AE1

AN49

I

VADCG8.1

AE6

AN52

I

VADCG8.4

DS6PA

AF6

AN53

I

VADCG8.5

DS6NA

AE7

AN54

I

VADCG8.6

DS6PB

AF7

AN55

I

VADCG8.7

DS6NB

AA4

AN56

I

VADCG9.0

AB3

AN57

I

VADCG9.1

Y2

AN60

I

VADCG9.4

DS7PA

AA1

AN61

I

VADCG9.5

DS7NA

W2

AN64

I

VADCG10.0

Y1

AN65

I

VADCG10.1

V2

AN68

I

VADCG10.4

DS8PA

SENT11A

Type

Function

D / HighZ / Analog input 43

VDDM

VADC analog input channel 3 of group 5 (with pull

down diagnostics)

D / HighZ / Analog input 48

VDDM

VADC analog input channel 0 of group 8

D / HighZ / Analog input 49

VDDM

VADC analog input channel 1 of group 8 (muxtest)

D / HighZ / Analog input 52

VDDM

VADC analog input channel 4 of group 8

DSADC: positive analog input of channel 6, pin A

D / HighZ / Analog input 53

VDDM

VADC analog input channel 5 of group 8

DSADC: negative analog input channel 6, pin A

D / HighZ / Analog input 5

VDDM

VADC analog input channel 6 of group 8

DSADC: positive analog input of channel 6, pin B

D / HighZ / Analog input 50

VDDM

VADC analog input channel 7 of group 8

DSADC: negative analog input channel 6, pin B

D / HighZ / Analog input 56

VDDM

VADC analog input channel 0 of group 9

D / HighZ / Analog input 57

VDDM

VADC analog input channel 1 of group 9 (muxtest)

D / HighZ / Analog input 60

VDDM

VADC analog input channel 4 of group 9

DSADC: positive analog input of channel 7, pin A

D / HighZ / Analog input 61

VDDM

VADC analog input channel 5 of group 9

DSADC: negative analog input channel 7, pin A

D / HighZ / Analog input 64

VDDM

VADC analog input channel 0 of group 10

D / HighZ / Analog input 65

VDDM

VADC analog input channel 1 of group 10 (muxtest)

S / HighZ / VDDM

Analog input 68 VADC analog input channel 4 of group 10 DSADC: positive analog input of channel 8, pin A

SENT input channel 11, pin A

Data Sheet

TOC-215

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-49 Analog Inputs (cont'd)

Pin

Symbol

Ctrl

W1

AN69

I

VADCG10.5

DS8NA

SENT12A

U2

AN70

I

VADCG10.6

DS9PA

SENT13A

V1

AN71

I

VADCG10.7

DS9NA

SENT14A

Type S / HighZ / VDDM
S / HighZ / VDDM
S / HighZ / VDDM

Function Analog input 69 VADC analog input channel 5 of group 10 DSADC: negative analog input channel 8, pin A SENT input channel 12, pin A Analog input 70 VADC analog input channel 6 of group 10 DSADC: positive analog input of channel 9, pin A SENT input channel 13, pin A Analog input 71 VADC analog input channel 7 of group 10 DSADC: negative analog input channel 9, pin A SENT input channel 14, pin A

Table 2-50 System I/O

Pin

Symbol

B22

PORST

A23

ESR0

EVRWUP

A22

ESR1

AC17

EVRWUP VGATE1P

AC21

VGATE3P

F24

TMS

DAP1

Ctrl Type

Function

I

PORST / Power On Reset Input

PD /

Additional strong PD in case of power fail.

VEXT

I/O

MP /

OD /

VEXT

External System Request Reset 0 Default configuration during and after reset is opendrain driver. The driver drives low during power-on reset. This is valid additionally after deactivation of PORST until the internal reset phase has finished. See also SCU chapter for details. Default after power-on can be different. See also SCU chapter ´Reset Control Unit´ and SCU_IOCR register description.

I

EVR Wakeup Pin

I/O

MP /

PU1 /

VEXT

External System Request Reset 1 Default NMI function. See also SCU chapter ´Reset Control Unit´ and SCU_IOCR register description.

I

EVR Wakeup Pin

O

VGATE1P / External Pass Device gate control for EVR13

- /

VEXT

O

VGATE3P / External Pass Device gate control for EVR33

- /

VEXT

I

A2 /

JTAG Module State Machine Control Input

I/O

PD /

Device Access Port Line 1

VDDP3

Data Sheet

TOC-216

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-50 System I/O (cont'd)

Pin

Symbol

Ctrl

F23

TRST

I

E24

TCK

I

DAP0

I

G26

XTAL1

I

G25

XTAL2

O

Type
A2 / PD / VDDP3
A2 / PD / VDDP3
XTAL1 / - / VDDP3
XTAL2 / - / VDDP3

Function JTAG Module Reset/Enable Input
JTAG Module Clock Input Device Access Port Line 0 Main Oscillator/PLL/Clock Generator Input
Main Oscillator/PLL/Clock Generator Output

Table 2-51 Supply Pin AD6 AC6 W4 Y4 AE9, AE5 R1, R4

Symbol VAREF1 VAGND1 VAREF2 VAGND2 VDDM NC / VDDSB

P23, V23, AB23, AC20, B26, VDD C25, D9, D24, E23, H4

F26

VDD

A25, B24, C23, D14, D22, K4, VEXT AC16, AD16, AE16, AF16

H24, H25, H26

VDDP3

Ctrl Type Function

I

Vx

Positive Analog Reference Voltage 1

I

Vx

Negative Analog Reference Voltage 1

I

Vx

Positive Analog Reference Voltage 2

I

Vx

Negative Analog Reference Voltage 2

I

Vx

ADC Analog Power Supply (3.3V / 5V)

I

NCVDD Emulation Device: Emulation SRAM

SB

Standby Power Supply (1.3V) (Emulation

Device only).

Production Device: Not Connected.

I

Vx

Digital Core Power Supply (1.3V)

I

Vx

Digital Core Power Supply (1.3V).

The supply pin inturn supplies the main

XTAL Oscillator/PLL (1.3V) . A higher

decoupling capacitor is therefore

recommended to the VSS pin for better

noise immunity.

I

Vx

External Power Supply (5V / 3.3V)

I

Vx

Digital Power Supply for Flash (3.3V).

Can be also used as external 3.3V Power

Supply for VFLEX.

Data Sheet

TOC-217

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-51 Supply (cont'd) Pin E26

Symbol VDDP3

A18, B18

VDDFL3

Ctrl Type Function

I

Vx

Digital Power Supply for Oscillator,

LVDSH and A2 pads (3.3V).

The supply pin inturn supplies the main

XTAL Oscillator/PLL (3.3V) . A higher

decoupling capacitor is therefore

recommended to the VSS pin for better

noise immunity.

I

Vx

Flash Power Supply (3.3V)

D7 AC18, AC22
M23, T23, Y23 AF5, AF9

VFLEX VFLEXE
VEBU VSSM

I

Vx

Digital Power Supply for Flex Port Pads

(5V / 3.3V)

I

Vx

Digital Power Supply for EBU Flex Port

Pads

(5V / 3.3V)

I

Vx

Digital Power Supply for EBU

(3.3V)

I

Vx

Analog Ground for VDDM

AD9

VEVRSB

A26, B25, C24, D8, D15, D23, VSS F25, J4, L23, R23, T4, W23, AC19, AC23
K10, K11, K12, K13, K14, VSS K15, K16, K17, L10, L11, L12, L13, L14, L15, L16, L17

I

Vx

Standby Power Supply (3.3V/5V) for the

Standby SRAM (CPU0.DSPR).

If Standby mode is not used: To be

handled like VEXT (3.3V/5V).

I

Vx

Digital Ground (outer balls)

I

Vx

Digital Ground (center balls)

M10, M11, M12, M13, M14, VSS M15, M16, M17, N10, N11, N12, N13, N14, N15, N16, N17

I

Vx

Digital Ground (center balls)

P11, P12, P13, P14, P15, P16, VSS R11, R12, R13, R14, R15, R16

I

Vx

Digital Ground (center balls)

T10, T11, T12, T13, T14, T15, VSS T16, T17, U10, U11, U14, U15, U16, U17

I

Vx

Digital Ground (center balls)

U12

VSS

I

Vx

Digital Ground (center balls)

This ball is used in the Emulation Device

as

AGBT TX0N

Data Sheet

TOC-218

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC298x Pin Definition and Functions:

Table 2-51 Supply (cont'd)

Pin

Symbol

Ctrl Type Function

U13

VSS

I

Vx

Digital Ground (center balls)

This ball is used in the Emulation Device

as

AGBT TX0P

R10

VSS

I

Vx

Digital Ground (center balls)

This ball is used in the Emulation Device

as

AGBT CLKN

P10

VSS

I

Vx

Digital Ground (center balls)

This ball is used in the Emulation Device

as

AGBT CLKP

R17

VSS

I

Vx

Digital Ground (center balls)

This ball is used in the Emulation Device

as

AGBT ERR

P17

NC / VDDPSB I

NCVDD Emulation Device: Power Supply (3.3V)

PSB for DAP/JTAG pad group. Can be

connected to VDDP or can be left

unsupplied (see document ´AurixED´ /

Aurix Emulation Devices specification.

A1, AF1, AF26

Production Device: This pin is not connected on package level. It can be connected on PCB level to VDDP or Ground or can be left unsupplied.

NC

I

NC1 Not Connected.

These pins are not connected on

package level and will not be used for

future extensions.

Legend:
Column "Ctrl.":
I = Input (for GPIO port Lines with IOCR bit field Selection PCx = 0XXXB)
O = Output O0 = Output with IOCR bit field selection PCx = 1X000B O1 = Output with IOCR bit field selection PCx = 1X001B (ALT1) O2 = Output with IOCR bit field selection PCx = 1X010B (ALT2) O3 = Output with IOCR bit field selection PCx = 1X011B (ALT3) O4 = Output with IOCR bit field selection PCx = 1X100B (ALT4) O5 = Output with IOCR bit field selection PCx = 1X101B (ALT5) O6 = Output with IOCR bit field selection PCx = 1X110B (ALT6) O7 = Output with IOCR bit field selection PCx = 1X111B (ALT7)
Column "Type":

Data Sheet

TOC-219

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
LP = Pad class LP (5V/3.3V, Class LP parameters for digital input / output and class D parameters for analog input function) MP = Pad class MP (5V/3.3V) MP+ = Pad class MP+ (5V/3.3V) MPR = Pad class MPR (5V/3.3V) A2 = Pad class A2 (3.3V) LVDSM = Pad class LVDSM (5V/3.3V) LVDSH = Pad class LVDSH (3.3V) S = Pad class S (Class S parameters for digital input and class D parameters for analog input function) D = Pad class D (VADC / DSADC) PU = with pull-up device connected during reset (PORST = 0) PU1 = with pull-up device connected during reset (PORST = 0)1) 2) 3) PD = with pull-down device connected during reset (PORST = 0) PD1 = with pull-down device connected during reset (PORST = 0)1) 2) 3) PX = Behavior depends on usage: PD in EVR13 SMPS Mode and PU1 in GPIO Mode OD = open drain during reset (PORST = 0) HighZ = tri-state during reset (PORST = 0) PORST = PORST input pad XTAL1 = XTAL1 input pad XTAL2 = XTAL2 input pad VGATE1P = VGATE1P VGATE3P = VGATE3P Vx = Supply NC = These pins are reserved for future extensions and shall not be connected externally NC1 = These pins are not connected on package level and will not be used for future extensions NCVDDPSB = This pin has a different functionality in an Production Device and an Emulation Device. For details pls. see Pin/Ball description of this pin. NCVDDSB = This pin has a different functionality in an Production Device and an Emulation Device. For details pls. see Pin/Ball description of this pin.
2.2.2 Emergency Stop Function
The Emergency Stop function can be used to force GPIOs (General Purpose Inputs/Outputs) via an external input signal (EMGSTOPA or EMGSTOPB) into a defined state: · Input state and · PU or High-Z depending on HWCFG[6] level latched during Porst active Control of the Emergency Stop function: · The Emergency Stop function can be enabled/disabled in the SCU (see chapter "SCU", "Emergency Stop
Control") · The Emergency Stop input signal, EMGSTOPA (P33.8) / EMGSTOPB (P21.2) , can selected in the SCU (see
chapter "SCU", "Emergency Stop Control")

1) The default state of GPIOs (Px.y) during and after PORST active is controllled via HWCFG[6] (P14.4). HWCFG[6] has a weak internal pull-up active at start-up if the pin is left unconnected.See also User´s Manual, "Introduction Chapter", "General Purpose I/O Ports and Peripheral I/O Lines", Figure: "Default state of port pins during and after reset".
2) If HWCFG[6] is left unconnected or is externally pulled high, weak internal pull-ups (PU1) / pull-downs (PD1) are active during and after reset.
3) If HWCFG[6] is connected to ground, the PD1 / PU1 pins are predominantly in HighZ during and after reset.

Data Sheet

TOC-220

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC298x Pin Definition and Functions:
· On port level, each GPIO can be enabled/disabled for the Emergency Stop function via the Px_ESR (Port x Emergency Stop) registers in the port control logic (see chapter "General Purpose I/O Ports and Peripheral I/O Lines", "Emergency Stop Register").
The Emergency Stop function is available for all GPIO Ports with the following exceptions: · Not available for P20.2 (General Purpose Input/GPI only, overlayed with Testmode) · Not available for P40.x (analoge input ANx overlayed with GPI) · Not available for P32.0 EVR13 SMPS mode. · Not available for dedicated I/O without General Purpose Output function (e.g ESRx, TMS, TCK) The Emergency Stop function can be overruled on the following GPIO Ports: · P00.x and P02.x: Emergency Stop can be overruled by the 8-Bit Standby Controller (SBR), if implemented.
Overruling can be disabled via the control registers P00_SCR / P02_SCR (see chapter "General Purpose I/O Ports and Peripheral I/O Lines", P00 / P01) · P00.x: Emergency Stop can be overruled by the VADC. Overruling can be disabled via the control register P00_SCR (see chapter "General Purpose I/O Ports and Peripheral I/O Lines", P00) · P14.0 and P14.1: Emergency Stop can be overruled in the DXCPL mode (DAP over can physical layer mode). No Overruling in the DXCM (Debug over can message) mode · P21.6: Emergency Stop can be overruled in JTAG mode if this pin is used as TDI · P21.7: Emergency Stop can be overruled in JTAG or Three Pin DAP mode · P20.0: Emergency Stop can be overruled in JTAG mode if this GPIO is used as TDI · P33.8: Emergency Stop can be overruled if this pin is used as safety output pin (SMUFSP)
2.2.3 Pull-Up/Pull-Down Reset Behavior of the Pins

Table 2-52 List of Pull-Up/Pull-Down Reset Behavior of the Pins

Pins

PORST = 0

PORST = 1

all GPIOs

Pull-up if HWCFG[6] = 1 or High-Z if HWCFG[6] = 0

TDI, TESTMODE

Pull-up

PORST1)

Pull-down with IPORST relevant

Pull-down with IPDLI relevant

TRST, TCK, TMS

Pull-down

ESR0

The open-drain driver is used to drive low.2)

Pull-up3)

ESR1

Pull-up3)

TDO

Pull-up

High-Z/Pull-up4)

1) Pull-down with IPORST relevant is always activated when a primary supply monitor detects a violation. 2) Valid additionally after deactivation of PORST until the internal reset phase has finished. See the SCU chapter for details.

3) See the SCU_IOCR register description.

4) Depends on JTAG/DAP selection with TRST.

In case of leakage test (PORST = 0 and TESTMODE = 0), the pull-down of the TRST pin is switched off. In case of an user application (TESTMODE = 1), the pull-down of the TRST is always switched on.

Data Sheet

TOC-221

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

2.3

TC297x Pin Definition and Functions: BGA292

Figure 2-3 is showing the TC297x Logic Symbol for the package variant: BGA292.

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

Y VSS P32.3 P32.2 P32.0 P33.13 P33.11 P33.9 P33.7 P33.5 P33.3 P33.1 AN5 AN10 VAGND1 VAREF1 VDDM VSSM AN20 AN21

1 NC Y

W VEXT

VSS

P32.4

VGATE1 P

P33.12

P33.10

P33.8

P33.6 P33.4 P33.2 P33.0

AN2

AN8

AN11 AN13 AN16 AN18 AN19 AN24 AN25 W

V P23.0 VEXT U P23.2 P23.1

17

16

15

14

13

12

11

10

9

8

7

6

5

4

U VSS P32.7 P32.6 P33.15 P34.5 P34.3 P34.1 AN1 AN3 AN7 AN9 AN14 AN17 NC U

AN26 AN27 V AN28 AN29 U

T P23.4 P23.3 R P22.2 P22.3 P P22.0 P22.1 N VDDP3 VDD

T P23.5 VSS P32.5 P33.14 P34.4 P34.2 VEVRSB AN0 AN4 AN6 AN12 AN15 AN22 AN30 T

R P23.6 P23.7 Top-View

P P22.5 P22.4

VDD

VSS VSS VSS (AGBT (AGBT VSS
TX0P) TX0N)

VDD

N P22.7 P22.6

VDD

VSS VSS VSS VSS

VDD

AN23 AN31 R AN34 AN32 P AN38 AN36 N

VAGND2 VAREF2 T AN35 AN33 R AN37 AN39 P AN45 AN44 N

M XTAL1 XTAL2 L VSS TRST K P21.4 P21.2 J P21.5 P21.3 H P20.0 P20.2 G P20.3 P20.1 F P20.8 P20.7

M P22.9 P22.8 L P22.11 P22.10 K P21.0 TMS J P21.1 TCK H P21.6 P21.7 G PORST ESR1 F P20.6 ESR0

VSS

VSS

VSS VSS

VSS VSS

VSS

VSS

(AGBT VSS VSS VSS VSS VSS VSS (AGBT

ERR)

CLKN)

NC (VDDPSB)

VSS

VSS

VSS

VSS

VSS

VSS VSS (AGBT
CLKP)

VSS

VSS

VSS VSS

VSS VSS

VDD

VSS VSS VSS VSS

VDD (VDDSB)

VDD

VSS

VSS

VSS

VSS

VDD (VDDSB)

AN40 AN41 M AN42 AN43 L P00.10 P00.8 K P01.7 P00.6 J P01.5 P01.6 H P01.3 P01.4 G P02.10 P02.11 F

AN47 AN46 M P00.12 P00.11 L P00.9 P00.7 K P00.5 P00.4 J P00.3 P00.2 H P00.1 P00.0 G P02.7 P02.8 F

E P20.11 P20.10

E P20.9 VSS VDDFL3 P15.5 P14.2 P12.0 P12.1 P11.0 P11.1 P11.7 P11.8 P11.13 VSS P02.9 E

P02.5 P02.6 E

D P20.13 P20.12 C P20.14 P15.2

D VSS VDDFL3 P15.7 P15.8 P14.7 P14.9 P14.10 P11.4 P11.6 P11.5 P11.14 P11.15 VFLEX VSS D

17

16

15

14

13

12

11

10

9

8

7

6

5

4

P02.3 P02.4 D P02.1 P02.2 C

B P15.0 VSS VDDP3 P15.3 P14.0 P14.4 P14.3 P14.6 P13.0 P13.2 P11.3 P11.10 P11.12 P10.1 P10.4 P10.5 P10.8 VEXT VSS P02.0 B

A VSS VDDP3 P15.1 P15.4 P15.6 P14.1 P14.5 P14.8 P13.1 P13.3 P11.2 P11.9 P11.11 P10.0 P10.3 P10.2 P10.6 P10.7 VEXT

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

NC A 1

Figure 2-3 TC297x Logic Symbol for the package variant BGA292.

Data Sheet

TOC-222

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

2.3.1

Package and Pinning DefinitionsTC297x Pin Definition and Functions:
TC297x BGA292 Package Variant Pin Configuration

Table 2-53 Port 00 Functions

Pin

Symbol

G1

P00.0

TIN9

CTRAPA

T12HRE

INJ00

CIFD9

P00.0

TOUT9

ASCLK3

ATX3

­

TXDCAN1

­

COUT63

ETHMDIOA

Ctrl Type

I

MP /

PU1 /

VEXT

O0 O1 O2 O3 O4 O5 O6 O7 HWOU T

Function General-purpose input GTM input CCU61 input CCU60 input MSC0 input CIF input General-purpose output GTM output ASCLIN3 output ASCLIN3 output Reserved CAN node 1 output Reserved CCU60 output ETH input/output

Data Sheet

TOC-223

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-53 Port 00 Functions (cont'd)

Pin

Symbol

Ctrl

G2

P00.1

I

TIN10

ARX3E

RXDCAN1D

PSIRX0A

SENT0B

CC60INB

CC60INA

DSCIN5A

DS5NA

DSCIN7B

VADCG7.5

CIFD10

P00.1

O0

TOUT10

O1

ATX3

O2

­

O3

DSCOUT5

O4

DSCOUT7

O5

SPC0

O6

CC60

O7

H1

P00.2

I

TIN11

SENT1B

DSDIN5A

DSDIN7B

DS5PA

VADCG7.4

CIFD11

P00.2

O0

TOUT11

O1

ASCLK3

O2

TXDCANr1

O3

PSITX0

O4

TXDCAN3

O5

SLSO34

O6

COUT60

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input ASCLIN3 input CAN node 1 input PSI5 input SENT input CCU60 input CCU61 input DSADC channel 5 input DSADC positive analog input of channel channel 5, pin A DSADC channel 7 input VADC analog input channel 5 of group 7 CIF input General-purpose output GTM output ASCLIN3 output Reserved DSADC channel 5 output DSADC channel 7 output SENT output CCU61 output General-purpose input GTM input SENT input DSADC channel 5 input DSADC channel 7 input DSADC negative analog input of channel 5, pin A VADC analog input channel 4 of group 7 CIF input General-purpose output GTM output ASCLIN3 output CAN node 1 output (MultiCANr+) PSI5 output CAN node 3 output QSPI3 output CCU61 output

Data Sheet

TOC-224

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-53 Port 00 Functions (cont'd)

Pin

Symbol

Ctrl

H2

P00.3

I

TIN12

RXDCAN3A

RXDCANr1A

PSIRX1A

PSISRXA

SENT2B

CC61INB

CC61INA

DSCIN3A

VADCG7.3

DSITR5F

CIFD12

P00.3

O0

TOUT12

O1

ASLSO3

O2

­

O3

DSCOUT3

O4

­

O5

SPC2

O6

CC61

O7

J1

P00.4

I

TIN13

REQ7

SENT3B

DSDIN3A

DSSGNA

VADCG7.2

CIFD13

P00.4

O0

TOUT13

O1

PSISTX

O2

­

O3

PSITX1

O4

VADCG4BFL0

O5

SPC3

O6

COUT61

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input CAN node 3 input CAN node 1 input (MultiCANr+) PSI5 input PSI5-S input SENT input CCU60 input CCU61 input DSADC channel 3 input VADC analog input channel 3 of group 7 DSADC channel 5 input CIF input General-purpose output GTM output ASCLIN3 output Reserved DSADC channel 3 output Reserved SENT output CCU61 output General-purpose input GTM input SCU input SENT input DSADC channel 3 input DSADC channel input VADC analog input channel 2 of group 7 CIF input General-purpose output GTM output PSI5-S output Reserved PSI5 output VADC output SENT output CCU61 output

Data Sheet

TOC-225

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-53 Port 00 Functions (cont'd)

Pin

Symbol

Ctrl

J2

P00.5

I

TIN14

PSIRX2A

SENT4B

CC62INB

CC62INA

DSCIN2A

VADCG7.1

CIFD14

P00.5

O0

TOUT14

O1

DSCGPWMN

O2

SLSO33

O3

DSCOUT2

O4

VADCG4BFL1

O5

SPC4

O6

CC62

O7

J4

P00.6

I

TIN15

SENT5B

DSDIN2A

VADCG7.0

DSITR4F

CIFD15

P00.6

O0

TOUT15

O1

DSCGPWMP

O2

VADCG4BFL2

O3

PSITX2

O4

VADCEMUX10

O5

SPC5

O6

COUT62

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input PSI5 input SENT input CCU60 input CCU61 input DSADC channel 2 input VADC analog input channel 1 of group 7 CIF input General-purpose output GTM output DSADC output QSPI3 output DSADC channel 2 output VADC output SENT output CCU61 output General-purpose input GTM input SENT input DSADC channel 2 input A VADC analog input channel 0 of group 7 (with pull down diagnostics) DSADC channel 4 input F CIF input General-purpose output GTM output DSADC output VADC output PSI5 output VADC output SENT output CCU61 output

Data Sheet

TOC-226

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-53 Port 00 Functions (cont'd)

Pin

Symbol

Ctrl

K1

P00.7

I

TIN16

SENT6B

CC60INC

CCPOS0A

T12HRB

T2INA

DSCIN4A

DS4NA

VADCG6.5

CIFCLK

P00.7

O0

TOUT16

O1

­

O2

VADCG4BFL3

O3

DSCOUT4

O4

VADCEMUX11

O5

SPC6

O6

CC60

O7

K4

P00.8

I

TIN17

SENT7B

CC61INC

CCPOS1A

T13HRB

T2EUDA

DSDIN4A

DS4PA

VADCG6.4

CIFVSNC

P00.8

O0

TOUT17

O1

SLSO36

O2

­

O3

­

O4

VADCEMUX12

O5

SPC7

O6

CC61

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input SENT input CCU61 input CCU61 input CCU60 input GPT120 input DSADC channel 4 input A DSADC negative analog input channel 4, pin A VADC analog input channel 5 of group 6 CIF input General-purpose output GTM output Reserved VADC output DSADC channel 4 output VADC output SENT output CCU61 output General-purpose input GTM input SENT input CCU61 input CCU61 input CCU60 input GPT120 input DSADC channel 4 input A DSADC positive analog input of channel 4, pin A VADC analog input channel 4 of group 6 CIF input General-purpose output GTM output QSPI3 output Reserved Reserved VADC output SENT output CCU61 output

Data Sheet

TOC-227

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-53 Port 00 Functions (cont'd)

Pin

Symbol

Ctrl

K2

P00.9

I

TIN18

SENT8B

CC62INC

CCPOS2A

T13HRC

T12HRC

T4EUDA

DSCIN1A

VADCG6.3

DSITR3F

CIFHSNC

P00.9

O0

TOUT18

O1

SLSO37

O2

ARTS3

O3

DSCOUT1

O4

­

O5

SPC8

O6

CC62

O7

K5

P00.10

I

TIN19

SENT9B

DSDIN1A

VADCG6.2

P00.10

O0

TOUT19

O1

­

O2

­

O3

­

O4

­

O5

SPC9

O6

COUT63

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input SENT input CCU61 input CCU61 input CCU60 input CCU60 input GPT120 input DSADC channel 1 input A VADC analog input channel 3 of group 6 DSADC channel 3 input F CIF input General-purpose output GTM output QSPI3 output ASCLIN3 output DSADC channel 1 output Reserved SENT output CCU61 output General-purpose input GTM input SENT input DSADC channel 1 input A VADC analog input channel 2 of group 6 General-purpose output GTM output Reserved Reserved Reserved Reserved SENT output CCU61 output

Data Sheet

TOC-228

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-53 Port 00 Functions (cont'd)

Pin

Symbol

Ctrl

L1

P00.11

I

TIN20

CTRAPA

T12HRE

DSCIN0A

VADCG6.1

P00.11

O0

TOUT20

O1

­

O2

­

O3

DSCOUT0

O4

­

O5

­

O6

­

O7

L2

P00.12

I

TIN21

ACTS3A

DSDIN0A

VADCG6.0

P00.12

O0

TOUT21

O1

­

O2

­

O3

­

O4

­

O5

­

O6

COUT63

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input CCU60 input CCU61 input DSADC channel 0 input A VADC analog input channel 1 of group 6 General-purpose output GTM output Reserved Reserved DSADC channel 0 output Reserved Reserved Reserved General-purpose input GTM input ASCLIN3 input DSADC channel 0 input A VADC analog input channel 0 of group 6 General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved CCU61 output

Data Sheet

TOC-229

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-54 Port 01 Functions

Pin

Symbol

G5

P01.3

TIN111

SLSI3B

DSITR7F

P01.3

TOUT111

­

­

SLSO39

TXDCAN1

­

­

G4

P01.4

TIN112

RXDCAN1C

DSITR7E

P01.4

TOUT112

­

­

SLSO310

­

­

­

H5

P01.5

TIN113

MRST3C

DSCIN8A

P01.5

TOUT113

­

­

MRST3

­

DSCOUT8

­

Ctrl Type Function

I

LP /

General-purpose input

PU1 / VEXT

GTM input QSPI3 input

DSADC channel 7 input F

O0

General-purpose output

O1

GTM output

O2

Reserved

O3

Reserved

O4

QSPI3 output

O5

CAN node 1 output

O6

Reserved

O7

Reserved

I

LP /

General-purpose input

PU1 / VEXT

GTM input CAN node 1 input

DSADC channel 7 input E

O0

General-purpose output

O1

GTM output

O2

Reserved

O3

Reserved

O4

QSPI3 output

O5

Reserved

O6

Reserved

O7

Reserved

I

LP /

General-purpose input

PU1 / VEXT

GTM input QSPI3 input

DSADC channel 8 input A

O0

General-purpose output

O1

GTM output

O2

Reserved

O3

Reserved

O4

QSPI3 output

O5

Reserved

O6

DSADC channel 8 output

O7

Reserved

Data Sheet

TOC-230

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-54 Port 01 Functions (cont'd)

Pin

Symbol

Ctrl

H4

P01.6

I

TIN114

MTSR3C

DSDIN8A

P01.6

O0

TOUT114

O1

­

O2

­

O3

MTSR3

O4

­

O5

­

O6

­

O7

J5

P01.7

I

TIN115

SCLK3C

DSITR8F

P01.7

O0

TOUT115

O1

­

O2

­

O3

SCLK3

O4

­

O5

­

O6

­

O7

Type MP / PU1 / VEXT
MP / PU1 / VEXT

Function General-purpose input GTM input QSPI3 input DSADC channel 8 input A General-purpose output GTM output Reserved Reserved QSPI3 output Reserved Reserved Reserved General-purpose input GTM input QSPI3 input DSADC channel 8 input F General-purpose output GTM output Reserved Reserved QSPI3 output Reserved Reserved Reserved

Data Sheet

TOC-231

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-55 Port 02 Functions

Pin

Symbol

B1

P02.0

TIN0

REQ6

ARX2G

CC60INA

CC60INB

CIFD0

P02.0

TOUT0

ATX2

SLSO31

DSCGPWMN

TXDCAN0

TXD0A

CC60

C2

P02.1

TIN1

REQ14

ARX2B

RXDCAN0A

RXD0A2

CIFD1

P02.1

TOUT1

SLSO47

SLSO32

DSCGPWMP

­

­

COUT60

Ctrl Type Function

I

MP+ / General-purpose input

PU1 / VEXT

GTM input SCU input

ASCLIN2 input

CCU60 input

CCU61 input

CIF input

O0

General-purpose output

O1

GTM output

O2

ASCLIN2 output

O3

QSPI3 output

O4

DSADC output

O5

CAN node 0 output

O6

ERAY0 output

O7

CCU60 output

I

LP / PU1 General-purpose input

/ VEXT GTM input

SCU input

ASCLIN2 input

CAN node 0 input

ERAY0 input

CIF input

O0

General-purpose output

O1

GTM output

O2

QSPI4 output

O3

QSPI3 output

O4

DSADC output

O5

Reserved

O6

Reserved

O7

CCU60 output

Data Sheet

TOC-232

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-55 Port 02 Functions (cont'd)

Pin

Symbol

Ctrl

C1

P02.2

I

TIN2

CC61INA

CC61INB

CIFD2

P02.2

O0

TOUT2

O1

ATX1

O2

SLSO33

O3

PSITX0

O4

TXDCAN2

O5

TXD0B

O6

CC61

O7

D2

P02.3

I

TIN3

ARX1G

RXDCAN2B

RXD0B2

PSIRX0B

DSCIN5B

SDI11

CIFD3

P02.3

O0

TOUT3

O1

ASLSO2

O2

SLSO34

O3

DSCOUT5

O4

­

O5

­

O6

COUT61

O7

Type MP+ / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input CCU60 input CCU61 input CIF input General-purpose output GTM output ASCLIN1 output QSPI3 output PSI5 output CAN node 2 output ERAY0 output CCU60 output General-purpose input GTM input ASCLIN1 input CAN node 2 input ERAY0 input PSI5 input DSADC channel 5 input B MSC1 input CIF input General-purpose output GTM output ASCLIN2 output QSPI3 output DSADC channel 5 output Reserved Reserved CCU60 output

Data Sheet

TOC-233

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-55 Port 02 Functions (cont'd)

Pin

Symbol

Ctrl

D1

P02.4

I

TIN4

SLSI3A

ECTT1

RXDCAN0D

CC62INA

CC62INB

DSDIN5B

SDA0A

CIFD4

P02.4

O0

TOUT4

O1

ASCLK2

O2

SLSO30

O3

PSISCLK

O4

SDA0

O5

TXEN0A

O6

CC62

O7

E2

P02.5

I

TIN5

MRST3A

ECTT2

PSIRX1B

PSISRXB

SENT3C

DSCIN4B

SCL0A

CIFD5

P02.5

O0

TOUT5

O1

TXDCAN0

O2

MRST3

O3

DSCOUT4

O4

SCL0

O5

TXEN0B

O6

COUT62

O7

Type MP+ / PU1 / VEXT
MP+ / PU1 / VEXT

Function General-purpose input GTM input QSPI3 input TTCAN input CAN node 0 input CCU60 input CCU61 input DSADC channel 5 input B I2C0 input CIF input General-purpose output GTM output ASCLIN2 output QSPI3 output PSI5-S output I2C0 output ERAY0 output CCU60 output General-purpose input GTM input QSPI3 input TTCAN input PSI5 input PSI5-S input SENT input DSADC channel 4 input B I2C0 input CIF input General-purpose output GTM output CAN node 0 output QSPI3 output DSADC channel 4 output I2C0 output ERAY0 output CCU60 output

Data Sheet

TOC-234

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-55 Port 02 Functions (cont'd)

Pin

Symbol

Ctrl

E1

P02.6

I

TIN6

MTSR3A

SENT2C

CC60INC

CCPOS0A

T12HRB

T3INA

CIFD6

DSDIN4B

DSITR5E

P02.6

O0

TOUT6

O1

PSISTX

O2

MTSR3

O3

PSITX1

O4

VADCEMUX00

O5

­

O6

CC60

O7

Type
MP / PU1 / VEXT

Function General-purpose input GTM input QSPI3 input SENT input CCU60 input CCU60 input CCU61 input GPT120 input CIF input DSADC channel 4 input B DSADC channel 5 input E General-purpose output GTM output PSI5-S output QSPI3 output PSI5 output VADC output Reserved CCU60 output

Data Sheet

TOC-235

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-55 Port 02 Functions (cont'd)

Pin

Symbol

Ctrl

F2

P02.7

I

TIN7

SCLK3A

PSIRX2B

SENT1C

CC61INC

CCPOS1A

T13HRB

T3EUDA

CIFD7

DSCIN3B

DSITR4E

P02.7

O0

TOUT7

O1

­

O2

SCLK3

O3

DSCOUT3

O4

VADCEMUX01

O5

SPC1

O6

CC61

O7

Type
MP / PU1 / VEXT

Function General-purpose input GTM input QSPI3 input PSI5 input SENT input CCU60 input CCU60 input CCU61 input GPT120 input CIF input DSADC channel 3 input B DSADC channel 4 input E General-purpose output GTM output Reserved QSPI3 output DSADC channel 3 output VADC output SENT output CCU60 output

Data Sheet

TOC-236

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-55 Port 02 Functions (cont'd)

Pin

Symbol

Ctrl

F1

P02.8

I

TIN8

SENT0C

CC62INC

CCPOS2A

T12HRC

T13HRC

T4INA

CIFD8

DSDIN3B

DSITR3E

P02.8

O0

TOUT8

O1

SLSO35

O2

­

O3

PSITX2

O4

VADCEMUX02

O5

ETHMDC

O6

CC62

O7

E4

P02.9

I

TIN116

P02.9

O0

TOUT116

O1

ATX2

O2

­

O3

­

O4

TXDCAN1

O5

­

O6

­

O7

Type Function

LP / PU1 General-purpose input

/ VEXT

GTM input SENT input

CCU60 input

CCU60 input

CCU61 input

CCU61 input

GPT120 input

CIF input

DSADC channel 3 input B

DSADC channel 3 input E

General-purpose output

GTM output

QSPI3 output

Reserved

PSI5 output

VADC output

ETH output

CCU60 output

LP / PU1 / VEXT

General-purpose input GTM input General-purpose output

GTM output

ASCLIN2 output

Reserved

Reserved

CAN node 1 output

Reserved

Reserved

Data Sheet

TOC-237

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-55 Port 02 Functions (cont'd)

Pin

Symbol

Ctrl

F5

P02.10

I

TIN117

ARX2C

RXDCAN1E

P02.10

O0

TOUT117

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

F4

P02.11

I

TIN118

P02.11

O0

TOUT118

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input ASCLIN2 input CAN node 1 input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved

Table 2-56 Port 10 Functions

Pin

Symbol

A7

P10.0

TIN102

T6EUDB

P10.0

TOUT102

­

SLSO110

­

VADCG6BFL0

­

­

Ctrl Type

Function

I

LP /

General-purpose input

PU1 / VEXT

GTM input GPT120 input

O0

General-purpose output

O1

GTM output

O2

Reserved

O3

QSPI1 output

O4

Reserved

O5

VADC output

O6

Reserved

O7

Reserved

Data Sheet

TOC-238

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-56 Port 10 Functions (cont'd)

Pin

Symbol

Ctrl

B7

P10.1

I

TIN103

MRST1A

T5EUDB

P10.1

O0

TOUT103

O1

MTSR1

O2

MRST1

O3

EN01

O4

VADCG6BFL1

O5

END03

O6

­

O7

A5

P10.2

I

TIN104

SCLK1A

T6INB

REQ2

RXDCAN2E

SDI01

P10.2

O0

TOUT104

O1

­

O2

SCLK1

O3

EN00

O4

VADCG6BFL2

O5

END02

O6

­

O7

Type MP+ / PU1 / VEXT
MP / PU1 / VEXT

Function General-purpose input GTM input QSPI1 input GPT120 input General-purpose output GTM output QSPI1 output QSPI1 output MSC0 output VADC output MSC0 output Reserved General-purpose input GTM input QSPI1 input GPT120 input SCU input CAN node 2 input MSC0 input General-purpose output GTM output Reserved QSPI1 output MSC0 output VADC output MSC0 output Reserved

Data Sheet

TOC-239

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-56 Port 10 Functions (cont'd)

Pin

Symbol

Ctrl

A6

P10.3

I

TIN105

MTSR1A

REQ3

T5INB

P10.3

O0

TOUT105

O1

VADCG6BFL3

O2

MTSR1

O3

EN00

O4

END02

O5

TXDCAN2

O6

­

O7

B6

P10.4

I

TIN106

MTSR1C

CCPOS0C

T3INB

P10.4

O0

TOUT106

O1

­

O2

SLSO18

O3

MTSR1

O4

EN00

O5

END02

O6

­

O7

Type MP / PU1 / VEXT
MP+ / PU1 / VEXT

Function General-purpose input GTM input QSPI1 input SCU input GPT120 input General-purpose output GTM output VADC output QSPI1 output MSC0 output MSC0 output CAN node 2 output Reserved General-purpose input GTM input QSPI1 input CCU60 input GPT120 input General-purpose output GTM output Reserved QSPI1 output QSPI1 output MSC0 output MSC0 output Reserved

Data Sheet

TOC-240

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-56 Port 10 Functions (cont'd)

Pin

Symbol

Ctrl

B5

P10.5

I

TIN107

HWCFG4

RXDCANr0A

INJ01

P10.5

O0

TOUT107

O1

ATX2

O2

SLSO38

O3

SLSO19

O4

T6OUT

O5

ASLSO2

O6

PSITX3

O7

A4

P10.6

I

TIN108

ARX2D

MTSR3B

PSIRX3C

HWCFG5

P10.6

O0

TOUT108

O1

ASCLK2

O2

MTSR3

O3

T3OUT

O4

TXDCANr0

O5

MRST1

O6

VADCG7BFL0

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input SCU input CAN node 0 input (MultiCANr+) MSC0 input General-purpose output GTM output ASCLIN2 output QSPI3 output QSPI1 output GPT120 output ASCLIN2 output PSI5 output General-purpose input GTM input ASCLIN2 input QSPI3 input PSI5 input SCU input General-purpose output GTM output ASCLIN2 output QSPI3 output GPT120 output CAN node 0 output (MultiCANr+) QSPI1 output VADC output

Data Sheet

TOC-241

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-56 Port 10 Functions (cont'd)

Pin

Symbol

Ctrl

A3

P10.7

I

TIN109

ACTS2A

MRST3B

REQ4

CCPOS1C

T3EUDB

P10.7

O0

TOUT109

O1

­

O2

MRST3

O3

VADCG7BFL1

O4

TXDCANr0

O5

­

O6

­

O7

B4

P10.8

I

TIN110

SCLK3B

REQ5

CCPOS2C

T4INB

RXDCANr0B

P10.8

O0

TOUT110

O1

ARTS2

O2

SCLK3

O3

­

O4

­

O5

­

O6

­

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input ASCLIN2 input QSPI3 input SCU input CCU60 input GPT120 input General-purpose output GTM output Reserved QSPI3 output VADC output CAN node 0 output (MultiCANr+) Reserved Reserved General-purpose input GTM input QSPI3 input SCU input CCU60 input GPT120 input CAN node 0 input (MultiCANr+) General-purpose output GTM output ASCLIN2 output QSPI3 output Reserved Reserved Reserved Reserved

Data Sheet

TOC-242

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-57 Port 11 Functions

Pin

Symbol

E10

P11.0

TIN119

ARX3B

P11.0

TOUT119

ATX3

­

­

­

ETHTXD3

­

E9

P11.1

TIN120

P11.1

TOUT120

ASCLK3

ATX3

­

­

ETHTXD2

­

A10

P11.2

TIN95

P11.2

TOUT95

END03

SLSO05

SLSO15

EN01

ETHTXD1

COUT63

Ctrl Type

Function

I

MP+ /

General-purpose input

PU1 / VFLEX

GTM input ASCLIN3 input

O0

General-purpose output

O1

GTM output

O2

ASCLIN3 output

O3

Reserved

O4

Reserved

O5

Reserved

O6

ETH output

O7

Reserved

I

MP+ /

General-purpose input

PU1 /

GTM input

VFLEX

O0

General-purpose output

O1

GTM output

O2

ASCLIN3 output

O3

ASCLIN3 output

O4

Reserved

O5

Reserved

O6

ETH output

O7

Reserved

I

MPR/

General-purpose input

PU1 /

GTM input

VFLEX

O0

General-purpose output

O1

GTM output

O2

MSC0 output

O3

QSPI0 output

O4

QSPI1 output

O5

MSC0 output

O6

ETH output

O7

CCU60 output

Data Sheet

TOC-243

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-57 Port 11 Functions (cont'd)

Pin

Symbol

Ctrl

B10

P11.3

I

TIN96

MRST1B

SDI03

P11.3

O0

TOUT96

O1

­

O2

MRST1

O3

TXD0A

O4

­

O5

ETHTXD0

O6

COUT62

O7

D10

P11.4

I

TIN121

ETHRXCLKB

P11.4

O0

TOUT121

O1

ASCLK3

O2

­

O3

­

O4

­

O5

ETHTXER

O6

­

O7

D8

P11.5

I

TIN122

ETHTXCLKA

P11.5

O0

TOUT122

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

Type MPR / PU1 / VFLEX
MP+ / PU1 / VFLEX
LP / PU1 / VFLEX

Function General-purpose input GTM input QSPI1 input MSC0 input General-purpose output GTM output Reserved QSPI1 output ERAY0 output Reserved ETH output CCU60 output General-purpose input GTM input ETH input General-purpose output GTM output ASCLIN3 output Reserved Reserved Reserved ETH output Reserved General-purpose input GTM input ETH input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved

Data Sheet

TOC-244

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-57 Port 11 Functions (cont'd)

Pin

Symbol

Ctrl

D9

P11.6

I

TIN97

SCLK1B

P11.6

O0

TOUT97

O1

TXEN0B

O2

SCLK1

O3

TXEN0A

O4

FCLP0

O5

ETHTXEN

O6

COUT61

O7

E8

P11.7

I

TIN123

ETHRXD3

P11.7

O0

TOUT123

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

E7

P11.8

I

TIN124

ETHRXD2

P11.8

O0

TOUT124

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

Type MPR / PU1 / VFLEX
LP / PU1 / VFLEX
LP / PU1 / VFLEX

Function General-purpose input GTM input QSPI1 input General-purpose output GTM output ERAY0 output QSPI1 output ERAY0 output MSC0 output ETH output CCU60 output General-purpose input GTM input ETH input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved General-purpose input GTM input ETH input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved

Data Sheet

TOC-245

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-57 Port 11 Functions (cont'd)

Pin

Symbol

Ctrl

A9

P11.9

I

TIN98

MTSR1B

RXD0A1

ETHRXD1

P11.9

O0

TOUT98

O1

­

O2

MTSR1

O3

­

O4

SOP0

O5

­

O6

COUT60

O7

B9

P11.10

I

TIN99

REQ12

ARX1E

SLSI1A

RXDCAN3D

RXD0B1

ETHRXD0

SDI00

P11.10

O0

TOUT99

O1

­

O2

SLSO03

O3

SLSO13

O4

­

O5

­

O6

CC62

O7

Type MP+ / PU1 / VFLEX
LP / PU1 / VFLEX

Function General-purpose input GTM input QSPI1 input ERAY0 input ETH input General-purpose output GTM output Reserved QSPI1 output Reserved MSC0 output Reserved CCU60 output General-purpose input GTM input SCU input ASCLIN1 input QSPI1 input CAN node 3 input ERAY0 input ETH input MSC0 input General-purpose output GTM output Reserved QSPI0 output QSPI1 output Reserved Reserved CCU60 output

Data Sheet

TOC-246

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-57 Port 11 Functions (cont'd)

Pin

Symbol

Ctrl

A8

P11.11

I

TIN100

ETHCRSDVA

ETHRXDVA

ETHCRSB

P11.11

O0

TOUT100

O1

END02

O2

SLSO04

O3

SLSO14

O4

EN00

O5

TXEN0B

O6

CC61

O7

B8

P11.12

I

TIN101

ETHREFCLK

ETHTXCLKB

ETHRXCLKA

P11.12

O0

TOUT101

O1

ATX1

O2

GTMCLK2

O3

TXD0B

O4

TXDCAN3

O5

EXTCLK1

O6

CC60

O7

Type MP+ / PU1 / VFLEX
MPR / PU1 / VFLEX

Function General-purpose input GTM input ETH input ETH input ETH input General-purpose output GTM output MSC0 output QSPI0 output QSPI1 output MSC0 output ERAY0 output CCU60 output General-purpose input GTM input ETH input ETH input (Not for productive purposes) ETH input (Not for productive purposes) General-purpose output GTM output ASCLIN1 output GTM output ERAY0 output CAN node 3 output SCU output CCU60 output

Data Sheet

TOC-247

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-57 Port 11 Functions (cont'd)

Pin

Symbol

Ctrl

E6

P11.13

I

TIN125

ETHRXERA

SDA1A

P11.13

O0

TOUT125

O1

­

O2

­

O3

­

O4

­

O5

SDA1

O6

­

O7

D7

P11.14

I

TIN126

ETHCRSDVB

ETHRXDVB

ETHCRSA

SCL1A

P11.14

O0

TOUT126

O1

­

O2

­

O3

­

O4

­

O5

SCL1

O6

­

O7

D6

P11.15

I

TIN127

ETHCOL

P11.15

O0

TOUT127

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

Type LP / PU1 / VFLEX
LP / PU1 / VFLEX
LP / PU1 / VFLEX

Function General-purpose input GTM input ETH input I2C1 input General-purpose output GTM output Reserved Reserved Reserved Reserved I2C1 output Reserved General-purpose input GTM input ETH input ETH input ETH input I2C1 input General-purpose output GTM output Reserved Reserved Reserved Reserved I2C1 output Reserved General-purpose input GTM input ETH input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved

Data Sheet

TOC-248

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-58 Port 12 Functions

Pin

Symbol

E12

P12.0

TIN128

ETHRXCLKC

RXDCAN0C

P12.0

TOUT128

­

­

­

­

ETHMDC

­

E11

P12.1

TIN129

P12.1

TOUT129

ASLSO3

­

­

TXDCAN0

­

­

ETHMDIOC

Ctrl

Type

I

LP /

PU1 /

VFLEX

O0 O1 O2 O3 O4 O5 O6 O7 I
O0 O1 O2 O3 O4 O5 O6 O7 HWOU T

LP / PU1 / VFLEX

Function General-purpose input GTM input ETH input CAN node 0 input General-purpose output GTM output Reserved Reserved Reserved Reserved ETH output Reserved General-purpose input GTM input General-purpose output GTM output ASCLIN3 output Reserved Reserved CAN node 0 output Reserved Reserved ETH input/output

Table 2-59 Port 13 Functions

Pin

Symbol

Ctrl Type

Function

B12

P13.0

TIN91

P13.0

I

LVDSM_N / General-purpose input

PU1 / VEXT O0

GTM input General-purpose output

TOUT91

O1

GTM output

END03

O2

MSC0 output

SCLK2N

O3

QSPI2 output (LVDS)

EN01

O4

MSC0 output

FCLN0

O5

MSC0 output (LVDS)

FCLND0

O6

MSC0 output (LVDS)

­

O7

Reserved

Data Sheet

TOC-249

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-59 Port 13 Functions (cont'd)

Pin

Symbol

Ctrl

A12

P13.1

I

TIN92

SCL0B

P13.1

O0

TOUT92

O1

­

O2

SCLK2P

O3

­

O4

FCLP0

O5

SCL0

O6

­

O7

B11

P13.2

I

TIN93

CAPINA

SDA0B

P13.2

O0

TOUT93

O1

­

O2

MTSR2N

O3

FCLP0

O4

SON0

O5

SDA0

O6

SOND0

O7

A11

P13.3

I

TIN94

P13.3

O0

TOUT94

O1

­

O2

MTSR2P

O3

­

O4

SOP0

O5

­

O6

­

O7

Type LVDSM_P / PU1 / VEXT
LVDSM_N / PU1 / VEXT
LVDSM_P / PU1 / VEXT

Function General-purpose input GTM input I2C0 input General-purpose output GTM output Reserved QSPI2 output (LVDS) Reserved MSC0 output (LVDS) I2C0 output Reserved General-purpose input GTM input GPT120 input I2C0 input General-purpose output GTM output Reserved QSPI2 output (LVDS) MSC0 output MSC0 output (LVDS) I2C0 output MSC0 output (LVDS) General-purpose input GTM input General-purpose output GTM output Reserved QSPI2 output (LVDS) Reserved MSC0 output (LVDS) Reserved Reserved

Data Sheet

TOC-250

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-60 Port 14 Functions

Pin

Symbol

Ctrl Type Function

B16

P14.0

TIN80

SENT12D

I

MP+ / General-purpose input

PU1 / VEXT

GTM input SENT input

P14.0

O0

General-purpose output

TOUT80

O1

GTM output

ATX0

O2

ASCLIN0 output

Recommended as Boot loader pin

TXD0A

O3

ERAY0 output

TXD0B

O4

ERAY0 output

TXDCAN1

O5

CAN node 1 output Used for single pin DAP (SPD) function

ASCLK0

O6

ASCLIN0 output

COUT62

O7

CCU60 output

A15

P14.1

TIN81

REQ15

I

MP /

General-purpose input

PU1 / VEXT

GTM input SCU input

SENT13D

SENT input

ARX0A

ASCLIN0 input Recommended as Boot loader pin

RXDCAN1B

CAN node 1 input Used for single pin DAP (SPD) function

RXD0A3

ERAY0 input

RXD0B3

ERAY0 input

EVRWUPA

SCU input

P14.1

O0

General-purpose output

TOUT81

O1

GTM output

ATX0

O2

ASCLIN0 output

Recommended as Boot loader pin.

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

COUT63

O7

CCU60 output

Data Sheet

TOC-251

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-60 Port 14 Functions (cont'd)

Pin

Symbol

Ctrl

E13

P14.2

I

TIN82

HWCFG2 EVR13

P14.2

O0

TOUT82

O1

ATX2

O2

SLSO21

O3

­

O4

­

O5

ASCLK2

O6

­

O7

B14

P14.3

I

TIN83

ARX2A

REQ10

HWCFG3_BMI

SDI02

P14.3

O0

TOUT83

O1

ATX2

O2

SLSO23

O3

ASLSO1

O4

ASLSO3

O5

­

O6

­

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input SCU input Latched at cold power on reset to decide EVR13 activation. General-purpose output GTM output ASCLIN2 output QSPI2 output Reserved Reserved ASCLIN2 output Reserved General-purpose input GTM input ASCLIN2 input SCU input SCU input MSC0 input General-purpose output GTM output ASCLIN2 output QSPI2 output ASCLIN1 output ASCLIN3 output Reserved Reserved

Data Sheet

TOC-252

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-60 Port 14 Functions (cont'd)

Pin

Symbol

Ctrl

B15

P14.4

I

TIN84

HWCFG6

P14.4

O0

TOUT84

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

A14

P14.5

I

TIN85

HWCFG1 EVR33

P14.5

O0

TOUT85

O1

­

O2

­

O3

­

O4

­

O5

TXD0B

O6

TXD1B

O7

B13

P14.6

I

TIN86

HWCFG0 DCLDO

P14.6

O0

TOUT86

O1

­

O2

SLSO22

O3

­

O4

­

O5

TXEN0B

O6

TXEN1B

O7

Type LP / PU1 / VEXT
MP+ / PU1 / VEXT
MP+ / PU1 / VEXT

Function General-purpose input GTM input SCU input Latched at cold power on reset to decide default pad reset state (PU or HighZ). General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved General-purpose input GTM input SCU input Latched at cold power on reset to decide EVR33 activation. General-purpose output GTM output Reserved Reserved Reserved Reserved ERAY0 output ERAY1 output General-purpose input GTM input SCU input If EVR13 active, latched at cold power on reset to decide between LDO and SMPS mode. General-purpose output GTM output Reserved QSPI2 output Reserved Reserved ERAY0 output ERAY1 output

Data Sheet

TOC-253

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-60 Port 14 Functions (cont'd)

Pin

Symbol

Ctrl

D13

P14.7

I

TIN87

RXD0B0

RXD1B0

P14.7

O0

TOUT87

O1

ARTS0

O2

SLSO24

O3

­

O4

­

O5

­

O6

­

O7

A13

P14.8

I

TIN88

ARX1D

RXDCAN2D

RXD0A0

RXD1A0

P14.8

O0

TOUT88

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

D12

P14.9

I

TIN89

ACTS0A

P14.9

O0

TOUT89

O1

END03

O2

EN01

O3

­

O4

TXEN0B

O5

TXEN0A

O6

TXEN1A

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT
MP+ / PU1 / VEXT

Function General-purpose input GTM input ERAY0 input ERAY1 input General-purpose output GTM output ASCLIN0 output QSPI2 output Reserved Reserved Reserved Reserved General-purpose input GTM input ASCLIN1 input CAN node 2 input ERAY0 input ERAY1 input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved General-purpose input GTM input ASCLIN0 input General-purpose output GTM output MSC0 output MSC0 output Reserved ERAY0 output ERAY0 output ERAY1 output

Data Sheet

TOC-254

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-60 Port 14 Functions (cont'd)

Pin

Symbol

Ctrl

D11

P14.10

I

TIN90

P14.10

O0

TOUT90

O1

END02

O2

EN00

O3

ATX1

O4

TXDCAN2

O5

TXD0A

O6

TXD1A

O7

Type
MP+ / PU1 / VEXT

Function General-purpose input GTM input General-purpose output GTM output MSC0 output MSC0 output ASCLIN1 output CAN node 2 output ERAY0 output ERAY1 output

Table 2-61 Port 15 Functions

Pin

Symbol

B20

P15.0

TIN71

P15.0

TOUT71

ATX1

SLSO013

­

TXDCAN2

ASCLK1

­

A18

P15.1

TIN72

REQ16

ARX1A

RXDCAN2A

SLSI2B

EVRWUPB

P15.1

TOUT72

ATX1

SLSO25

­

­

­

­

Ctrl Type Function

I

LP /

General-purpose input

PU1 / GTM input

VEXT

O0

General-purpose output

O1

GTM output

O2

ASCLIN1 output

O3

QSPI0 output

O4

Reserved

O5

CAN node 2 output

O6

ASCLIN1 output

O7

Reserved

I

LP /

General-purpose input

PU1 / VEXT

GTM input SCU input

ASCLIN1 input

CAN node 2 input

QSPI2 input

SCU input

O0

General-purpose output

O1

GTM output

O2

ASCLIN1 output

O3

QSPI2 output

O4

Reserved

O5

Reserved

O6

Reserved

O7

Reserved

Data Sheet

TOC-255

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-61 Port 15 Functions (cont'd)

Pin

Symbol

Ctrl

C19

P15.2

I

TIN73

SLSI2A

MRST2E

SENT10D

HSIC2INA

P15.2

O0

TOUT73

O1

ATX0

O2

SLSO20

O3

­

O4

TXDCAN1

O5

ASCLK0

O6

­

O7

B17

P15.3

I

TIN74

ARX0B

SCLK2A

RXDCAN1A

HSIC2INB

P15.3

O0

TOUT74

O1

ATX0

O2

SCLK2

O3

END03

O4

EN01

O5

­

O6

­

O7

Type MP / PU1 / VEXT
MP / PU1 / VEXT

Function General-purpose input GTM input QSPI2 input QSPI2 input SENT input QSPI2 input General-purpose output GTM output ASCLIN0 output QSPI2 output Reserved CAN node 1 output ASCLIN0 output Reserved General-purpose input GTM input ASCLIN0 input QSPI2 input CAN node 1 input QSPI2 input General-purpose output GTM output ASCLIN0 output QSPI2 output MSC0 output MSC0 output Reserved Reserved

Data Sheet

TOC-256

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-61 Port 15 Functions (cont'd)

Pin

Symbol

Ctrl

A17

P15.4

I

TIN75

MRST2A

REQ0

SCL0C

SENT11D

P15.4

O0

TOUT75

O1

ATX1

O2

MRST2

O3

­

O4

­

O5

SCL0

O6

CC62

O7

E14

P15.5

I

TIN76

ARX1B

MTSR2A

REQ13

SDA0C

P15.5

O0

TOUT76

O1

ATX1

O2

MTSR2

O3

END02

O4

EN00

O5

SDA0

O6

CC61

O7

Type MP / PU1 / VEXT
MP / PU1 / VEXT

Function General-purpose input GTM input QSPI2 input SCU input I2C0 input SENT input General-purpose output GTM output ASCLIN1 output QSPI2 output Reserved Reserved I2C0 output CCU60 output General-purpose input GTM input ASCLIN1 input QSPI2 input SCU input I2C0 input General-purpose output GTM output ASCLIN1 output QSPI2 output MSC0 output MSC0 output I2C0 output CCU60 output

Data Sheet

TOC-257

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-61 Port 15 Functions (cont'd)

Pin

Symbol

Ctrl

A16

P15.6

I

TIN77

MTSR2B

P15.6

O0

TOUT77

O1

ATX3

O2

MTSR2

O3

SLSO53

O4

SCLK2

O5

ASCLK3

O6

CC60

O7

D15

P15.7

I

TIN78

ARX3A

MRST2B

P15.7

O0

TOUT78

O1

ATX3

O2

MRST2

O3

­

O4

­

O5

­

O6

COUT60

O7

D14

P15.8

I

TIN79

SCLK2B

REQ1

P15.8

O0

TOUT79

O1

­

O2

SCLK2

O3

­

O4

­

O5

ASCLK3

O6

COUT61

O7

Type MP / PU1 / VEXT
MP / PU1 / VEXT
MP / PU1 / VEXT

Function General-purpose input GTM input QSPI2 input General-purpose output GTM output ASCLIN3 output QSPI2 output QSPI5 output QSPI2 output ASCLIN3 output CCU60 output General-purpose input GTM input ASCLIN3 input QSPI2 input General-purpose output GTM output ASCLIN3 output QSPI2 output Reserved Reserved Reserved CCU60 output General-purpose input GTM input QSPI2 input SCU input General-purpose output GTM output Reserved QSPI2 output Reserved Reserved ASCLIN3 output CCU60 output

Data Sheet

TOC-258

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-62 Port 20 Functions

Pin

Symbol

H20

P20.0

TIN59

RXDCAN3C

RXDCANr1C

T6EUDA

REQ9

SYSCLK

TGI0

P20.0

TOUT59

ATX3

ASCLK3

­

SYSCLK

­

­

TGO0

G19

P20.1

TIN60

TGI1

P20.1

TOUT60

­

­

­

­

­

­

TGO1

Ctrl Type

I

MP /

PU1 /

VEXT

O0

O1

O2

O3

O4

O5

O6

O7

HWOU T

I

LP /

PU1 /

VEXT

O0 O1 O2 O3 O4 O5 O6 O7 HWOU T

Function General-purpose input GTM input CAN node 3 input CAN node 1 input (MultiCANr+) GPT120 input SCU input HSCT input OCDS input General-purpose output GTM output ASCLIN3 output ASCLIN3 output Reserved HSCT output Reserved Reserved OCDS; ENx
General-purpose input GTM input OCDS input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved OCDS; ENx

Data Sheet

TOC-259

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-62 Port 20 Functions (cont'd)

Pin

Symbol

Ctrl

H19

P20.2

I

TESTMODE

P20.2

O0

­

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

G20

P20.3

I

TIN61

T6INA

ARX3C

P20.3

O0

TOUT61

O1

ATX3

O2

SLSO09

O3

SLSO29

O4

TXDCAN3

O5

TXDCANr1

O6

­

O7

F17

P20.6

I

TIN62

P20.6

O0

TOUT62

O1

ARTS1

O2

SLSO08

O3

SLSO28

O4

­

O5

WDT2LCK

O6

­

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input This pin is latched at power on reset release to enter test mode. OCDS input Output function not available Output function not available Output function not available Output function not available Output function not available Output function not available Output function not available Output function not available General-purpose input GTM input GPT120 input ASCLIN3 input General-purpose output GTM output ASCLIN3 output QSPI0 output QSPI2 output CAN node 3 output CAN node 1 output (MultiCANr+) Reserved General-purpose input GTM input General-purpose output GTM output ASCLIN1 output QSPI0 output QSPI2 output Reserved SCU output Reserved

Data Sheet

TOC-260

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-62 Port 20 Functions (cont'd)

Pin

Symbol

Ctrl

F19

P20.7

I

TIN63

ACTS1A

RXDCAN0B

P20.7

O0

TOUT63

O1

­

O2

­

O3

­

O4

­

O5

WDT1LCK

O6

COUT63

O7

F20

P20.8

I

TIN64

P20.8

O0

TOUT64

O1

ASLSO1

O2

SLSO00

O3

SLSO10

O4

TXDCAN0

O5

WDT0LCK

O6

CC60

O7

E17

P20.9

I

TIN65

ARX1C

RXDCAN3E

REQ11

SLSI0B

P20.9

O0

TOUT65

O1

­

O2

SLSO01

O3

SLSO11

O4

­

O5

WDTSLCK

O6

CC61

O7

Type LP / PU1 / VEXT
MP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input ASCLIN1 input CAN node 0 input General-purpose output GTM output Reserved Reserved Reserved Reserved SCU output CCU61 output General-purpose input GTM input General-purpose output GTM output ASCLIN1 output QSPI0 output QSPI1 output CAN node 0 output SCU output CCU61 output General-purpose input GTM input ASCLIN1 input CAN node 3 input SCU input QSPI0 input General-purpose output GTM output Reserved QSPI0 output QSPI1 output Reserved SCU output CCU61 output

Data Sheet

TOC-261

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-62 Port 20 Functions (cont'd)

Pin

Symbol

Ctrl

E19

P20.10

I

TIN66

P20.10

O0

TOUT66

O1

ATX1

O2

SLSO06

O3

SLSO27

O4

TXDCAN3

O5

ASCLK1

O6

CC62

O7

E20

P20.11

I

TIN67

SCLK0A

P20.11

O0

TOUT67

O1

­

O2

SCLK0

O3

­

O4

­

O5

­

O6

COUT60

O7

D19

P20.12

I

TIN68

MRST0A

P20.12

O0

TOUT68

O1

­

O2

MRST0

O3

MTSR0

O4

­

O5

­

O6

COUT61

O7

Type MP / PU1 / VEXT
MP / PU1 / VEXT
MP / PU1 / VEXT

Function General-purpose input GTM input General-purpose output GTM output ASCLIN1 output QSPI0 output QSPI2 output CAN node 3 output ASCLIN1 output CCU61 output General-purpose input GTM input QSPI0 input General-purpose output GTM output Reserved QSPI0 output Reserved Reserved Reserved CCU61 output General-purpose input GTM input QSPI0 input General-purpose output GTM output Reserved QSPI0 output QSPI0 output Reserved Reserved CCU61 output

Data Sheet

TOC-262

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-62 Port 20 Functions (cont'd)

Pin

Symbol

Ctrl

D20

P20.13

I

TIN69

SLSI0A

P20.13

O0

TOUT69

O1

­

O2

SLSO02

O3

SLSO12

O4

SCLK0

O5

­

O6

COUT62

O7

C20

P20.14

I

TIN70

MTSR0A

P20.14

O0

TOUT70

O1

­

O2

MTSR0

O3

­

O4

­

O5

­

O6

­

O7

Type MP / PU1 / VEXT
MP / PU1 / VEXT

Function General-purpose input GTM input QSPI0 input General-purpose output GTM output Reserved QSPI0 output QSPI1 output QSPI0 output Reserved CCU61 output General-purpose input GTM input QSPI0 input General-purpose output GTM output Reserved QSPI0 output Reserved Reserved Reserved Reserved

Table 2-63 Port 21 Functions

Pin

Symbol

Ctrl

K17

P21.0

I

TIN51

MRST4DN

HOLD

P21.0

O0

TOUT51

O1

­

O2

­

O3

­

O4

­

O5

ETHMDC

O6

BAABA0

O7

HSM1

O

Data Sheet

Type
LVDSH_N/ PU1 / VDDP3

Function General-purpose input GTM input QSPI4 input (LVDS) EBU input General-purpose output GTM output Reserved Reserved Reserved Reserved ETH output EBU output (combined for BAA and BA0) HSM output

TOC-263

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-63 Port 21 Functions (cont'd)

Pin

Symbol

Ctrl

J17

P21.1

I

TIN52

ETHMDIOB

MRST4DP

WAIT

P21.1

O0

TOUT52

O1

­

O2

­

O3

­

O4

­

O5

ETHMDIO

O6

BREQBA1

O7

HSM2

O

K19

P21.2

I

TIN53

MRST2CN

MRST4CN

ARX3GN

EMGSTOPB

RXDN

P21.2

O0

TOUT53

O1

ASLSO3

O2

­

O3

­

O4

ETHMDC

O5

SDRAMA8

O6

­

O7

Type LVDSH_P/ PU1 / VDDP3
LVDSH_N/ PU1 / VDDP3

Function General-purpose input GTM input ETH input (Not for production purposes) QSPI4 input (LVDS) EBU input General-purpose output GTM output Reserved Reserved Reserved Reserved ETH output (Not for production purposes) EBU output (combined for BREQ and BA1) HSM output General-purpose input GTM input QSPI2 input (LVDS) QSPI4 input (LVDS) ASCLIN3 input (LVDS) SCU input HSCT input (LVDS) General-purpose output GTM output ASCLIN3 output Reserved Reserved ETH output EBU output Reserved

Data Sheet

TOC-264

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-63 Port 21 Functions (cont'd)

Pin

Symbol

Ctrl

Type

J19

P21.3

TIN54

MRST2CP

I

LVDSH_P/

PU1 /

VDDP3

MRST4CP

ARX3GP

RXDP

P21.3

O0

TOUT54

O1

­

O2

­

O3

­

O4

­

O5

SDRAMA9

O6

­

O7

ETHMDIOD

HWOUT

K20

P21.4

TIN55

P21.4

I

LVDSH_N/

PU1 /

O0

VDDP3

TOUT55

O1

­

O2

­

O3

­

O4

­

O5

SDRAMA10

O6

­

O7

TXDN

HSCT

J20

P21.5

TIN56

P21.5

I

LVDSH_P/

PU1 /

VDDP3 O0

TOUT56

O1

ASCLK3

O2

­

O3

­

O4

­

O5

SDRAMA11

O6

­

O7

TXDP

HSCT

Function General-purpose input GTM input QSPI2 input (LVDS) QSPI4 input (LVDS) ASCLIN3 input (LVDS) HSCT input (LVDS) General-purpose output GTM output Reserved Reserved Reserved Reserved EBU output Reserved ETH input/output General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved EBU output Reserved HSCT output (LVDS) General-purpose input GTM input General-purpose output GTM output ASCLIN3 output Reserved Reserved Reserved EBU output Reserved HSCT output (LVDS)

Data Sheet

TOC-265

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-63 Port 21 Functions (cont'd)

Pin

Symbol

Ctrl

Type

H17

P21.6

TIN57

ARX3F

I

A2 /

PU /

VDDP3

TGI2

TDI

T5EUDA

P21.6

O0

TOUT57

O1

ASLSO3

O2

­

O3

­

O4

SYSCLK

O5

SDRAMA12

O6

T3OUT

O7

TGO2

HWOUT

H16

P21.7

TIN58

DAP2

I

A2 /

PU /

VDDP3

TGI3 ETHRXERB T5INA P21.7 TOUT58 ATX3 ASCLK3 ­ ­ SDRAMA13 T6OUT TGO3 TDO

O0 O1 O2 O3 O4 O5 O6 O7 HWOUT

DAP2

Function General-purpose input GTM input ASCLIN3 input OCDS input OCDS (JTAG) input GPT120 input General-purpose output GTM output ASCLIN3 output Reserved Reserved HSCT output EBU output GPT120 output OCDS; ENx General-purpose input GTM input OCDS (3-Pin DAP) input In the 3-Pin DAP mode this pin is used as DAP2. In the 2-PIN DAP mode this pin is used as P21.7 and controlled by the related port control logic OCDS input ETH input GPT120 input General-purpose output GTM output ASCLIN3 output ASCLIN3 output Reserved Reserved EBU output GPT120 output OCDS; ENx OCDS (JTAG); ENx The JTAG TDO function is overlayed with P21.7 via a double bond. In JTAG mode this pin is used as TDO, after power-on reset it is HighZ. OCDS (3-Pin DAP); ENx In the 3-Pin DAP mode this pin is used as DAP2.

Data Sheet

TOC-266

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-64 Port 22 Functions

Pin

Symbol

P20

P22.0

TIN47

MTSR4B

P22.0

TOUT47

ATX3N

MTSR4

SCLK4N

FCLN1

FCLND1

­

P19

P22.1

TIN48

MRST4B

P22.1

TOUT48

ATX3P

MRST4

SCLK4P

FCLP1

­

­

R20

P22.2

TIN49

SLSI4B

P22.2

TOUT49

­

SLSO43

MTSR4N

SON1

SOND1

­

Ctrl Type

I

LVDSM_N /

PU1 /

VEXT

O0

O1

O2

O3

O4

O5

O6

O7

I

LVDSM_P /

PU1 /

VEXT

O0

O1

O2

O3

O4

O5

O6

O7

I

LVDSM_N /

PU1 /

VEXT

O0 O1 O2 O3 O4 O5 O6 O7

Function General-purpose input GTM input QSPI4 input General-purpose output GTM output ASCLIN3 output (LVDS) QSPI4 output QSPI4 output (LVDS) MSC1 output (LVDS) MSC1 output (LVDS) Reserved General-purpose input GTM input QSPI4 input General-purpose output GTM output ASCLIN3 output (LVDS) QSPI4 output QSPI4 output (LVDS) MSC1 output (LVDS) Reserved Reserved General-purpose input GTM input QSPI4 input General-purpose output GTM output Reserved QSPI4 output QSPI4 output (LVDS) MSC1 output (LVDS) MSC1 output (LVDS) Reserved

Data Sheet

TOC-267

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-64 Port 22 Functions (cont'd)

Pin

Symbol

Ctrl

R19

P22.3

I

TIN50

SCLK4B

P22.3

O0

TOUT50

O1

­

O2

SCLK4

O3

MTSR4P

O4

SOP1

O5

­

O6

­

O7

P16

P22.4

I

TIN130

P22.4

O0

TOUT130

O1

­

O2

­

O3

SLSO012

O4

PSITX4

O5

­

O6

­

O7

P17

P22.5

I

TIN131

MTSR0C

PSIRX4B

P22.5

O0

TOUT131

O1

­

O2

­

O3

MTSR0

O4

­

O5

­

O6

­

O7

Type LVDSM_P / PU1 / VEXT
LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input QSPI4 input General-purpose output GTM output Reserved QSPI4 output QSPI4 output (LVDS) MSC1 output (LVDS) Reserved Reserved General-purpose input GTM input General-purpose output GTM output Reserved Reserved QSPI0 output PSI5 output Reserved Reserved General-purpose input GTM input QSPI0 input PSI5 input General-purpose output GTM output Reserved Reserved QSPI0 output Reserved Reserved Reserved

Data Sheet

TOC-268

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-64 Port 22 Functions (cont'd)

Pin

Symbol

Ctrl

N16

P22.6

I

TIN132

MRST0C

P22.6

O0

TOUT132

O1

­

O2

­

O3

MRST0

O4

­

O5

­

O6

­

O7

N17

P22.7

I

TIN133

SCLK0C

P22.7

O0

TOUT133

O1

­

O2

­

O3

SCLK0

O4

­

O5

­

O6

­

O7

M16

P22.8

I

TIN134

SCLK0B

P22.8

O0

TOUT134

O1

­

O2

­

O3

SCLK0

O4

­

O5

­

O6

­

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input QSPI0 input General-purpose output GTM output Reserved Reserved QSPI0 output Reserved Reserved Reserved General-purpose input GTM input QSPI0 input General-purpose output GTM output Reserved Reserved QSPI0 output Reserved Reserved Reserved General-purpose input GTM input QSPI0 input General-purpose output GTM output Reserved Reserved QSPI0 output Reserved Reserved Reserved

Data Sheet

TOC-269

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-64 Port 22 Functions (cont'd)

Pin

Symbol

Ctrl

M17

P22.9

I

TIN135

MRST0B

P22.9

O0

TOUT135

O1

­

O2

­

O3

MRST0

O4

­

O5

­

O6

­

O7

L16

P22.10

I

TIN136

MTSR0B

P22.10

O0

TOUT136

O1

­

O2

­

O3

MTSR0

O4

­

O5

­

O6

­

O7

L17

P22.11

I

TIN137

P22.11

O0

TOUT137

O1

­

O2

­

O3

SLSO010

O4

­

O5

­

O6

­

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input QSPI0 input General-purpose output GTM output Reserved Reserved QSPI0 output Reserved Reserved Reserved General-purpose input GTM input QSPI0 input General-purpose output GTM output Reserved Reserved QSPI0 output Reserved Reserved Reserved General-purpose input GTM input General-purpose output GTM output Reserved Reserved QSPI0 output Reserved Reserved Reserved

Data Sheet

TOC-270

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-65 Port 23 Functions

Pin

Symbol

Ctrl Type

Function

V20

P23.0

TIN41

P23.0

I

LP /

General-purpose input

PU1 /

GTM input

VEXT

O0

General-purpose output

TOUT41

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

U19

P23.1

TIN42

SDI10

I

MP+ / General-purpose input

PU1 / VEXT

GTM input MSC1 input

P23.1

O0

General-purpose output

TOUT42

O1

GTM output

ARTS1

O2

ASCLIN1 output

SLSO46

O3

QSPI4 output

GTMCLK0

O4

GTM output

­

O5

Reserved

EXTCLK0

O6

SCU output

­

O7

Reserved

U20

P23.2

TIN43

P23.2

I

LP /

General-purpose input

PU1 /

GTM input

VEXT

O0

General-purpose output

TOUT43

O1

GTM output

­

O2

Reserved

­

O3

Reserved

­

O4

Reserved

­

O5

Reserved

­

O6

Reserved

­

O7

Reserved

Data Sheet

TOC-271

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-65 Port 23 Functions (cont'd)

Pin

Symbol

Ctrl

T19

P23.3

I

TIN44

INJ10

P23.3

O0

TOUT44

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

T20

P23.4

I

TIN45

P23.4

O0

TOUT45

O1

­

O2

SLSO45

O3

END12

O4

EN10

O5

­

O6

­

O7

T17

P23.5

I

TIN46

P23.5

O0

TOUT46

O1

­

O2

SLSO44

O3

END13

O4

EN11

O5

­

O6

­

O7

Type LP / PU1 / VEXT
MP+ / PU1 / VEXT
MP+ / PU1 / VEXT

Function General-purpose input GTM input MSC1 input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved General-purpose input GTM input General-purpose output GTM output Reserved QSPI4 output MSC1 output MSC1 output Reserved Reserved General-purpose input GTM input General-purpose output GTM output Reserved QSPI4 output MSC1 output MSC1 output Reserved Reserved

Data Sheet

TOC-272

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-65 Port 23 Functions (cont'd)

Pin

Symbol

Ctrl

R17

P23.6

I

TIN138

P23.6

O0

TOUT138

O1

­

O2

­

O3

SLSO011

O4

­

O5

­

O6

­

O7

R16

P23.7

I

TIN139

P23.7

O0

TOUT139

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input General-purpose output GTM output Reserved Reserved QSPI0 output Reserved Reserved Reserved General-purpose input GTM input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved

Table 2-66 Port 32 Functions

Pin

Symbol

Ctrl

Y17

P32.0

I

TIN36

FDEST

VGATE1N

Type
LP / PX/ VEXT

P32.0

O0

TOUT36

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

Function General-purpose input GTM input PMU input SMPS mode: analog output. External Pass Device gate control for EVR13 General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved

Data Sheet

TOC-273

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-66 Port 32 Functions (cont'd)

Pin

Symbol

Ctrl

Y18

P32.2

I

TIN38

ARX3D

RXDCAN3B

RXDCANr1D

P32.2

O0

TOUT38

O1

ATX3

O2

­

O3

­

O4

­

O5

DCDCSYNC

O6

­

O7

Y19

P32.3

I

TIN39

P32.3

O0

TOUT39

O1

ATX3

O2

­

O3

ASCLK3

O4

TXDCAN3

O5

TXDCANr1

O6

­

O7

W18

P32.4

I

TIN40

ACTS1B

SDI12

P32.4

O0

TOUT40

O1

­

O2

END12

O3

GTMCLK1

O4

EN10

O5

EXTCLK1

O6

COUT63

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT
MP+ / PU1 / VEXT

Function General-purpose input GTM input ASCLIN3 input CAN node 3 input CAN node 1 input (MultiCANr+) General-purpose output GTM output ASCLIN3 output Reserved Reserved Reserved SCU output Reserved General-purpose input GTM input General-purpose output GTM output ASCLIN3 output Reserved ASCLIN3 output CAN node 3 output CAN node 1 output (MultiCANr+) Reserved General-purpose input GTM input ASCLIN1 input MSC1 input General-purpose output GTM output Reserved MSC1 output GTM output MSC1 output SCU output CCU60 output

Data Sheet

TOC-274

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-66 Port 32 Functions (cont'd)

Pin

Symbol

Ctrl Type

T15

P32.5

TIN140

P32.5

I

LP /

PU1 /

VEXT O0

TOUT140

O1

ATX2

O2

­

O3

­

O4

­

O5

TXDCAN2

O6

­

O7

U15

P32.6

TGI4

TIN141

I

LP /

PU1 /

VEXT

RXDCAN2C

ARX2F

P32.6

O0

TOUT141

O1

­

O2

­

O3

SLSO212

O4

­

O5

­

O6

­

O7

TGO4

HWOU T

U16

P32.7

TIN142

TGI5

I

LP /

PU1 /

VEXT

P32.7

O0

TOUT142

O1

­

O2

­

O3

­

O4

­

O5

­

O6

­

O7

TGO5

HWOU T

Function General-purpose input GTM input General-purpose output GTM output ASCLIN2 output Reserved Reserved Reserved CAN node 2 output Reserved General-purpose input OCDS input GTM input CAN node 2 input ASCLIN2 input General-purpose output GTM output Reserved Reserved QSPI2 output Reserved Reserved Reserved OCDS; ENx
General-purpose input GTM input OCDS input General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved Reserved OCDS; ENx

Data Sheet

TOC-275

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-67 Port 33 Functions

Pin

Symbol

Ctrl

W10

P33.0

I

TIN22

DSITR0E

P33.0

O0

TOUT22

O1

­

O2

­

O3

­

O4

­

O5

VADCG2BFL0

O6

­

O7

Y10

P33.1

I

TIN23

PSIRX0C

SENT9C

DSCIN2B

DSITR1E

P33.1

O0

TOUT23

O1

ASLSO3

O2

SCLK2

O3

DSCOUT2

O4

VADCEMUX02

O5

VADCG2BFL1

O6

­

O7

W11

P33.2

I

TIN24

SENT8C

DSDIN2B

DSITR2E

P33.2

O0

TOUT24

O1

ASCLK3

O2

SLSO210

O3

PSITX0

O4

VADCEMUX01

O5

VADCG2BFL2

O6

­

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input DSADC channel 0 input E General-purpose output GTM output Reserved Reserved Reserved Reserved VADC output Reserved General-purpose input GTM input PSI5 input SENT input DSADC channel 2 input B DSADC channel 1 input E General-purpose output GTM output ASCLIN3 output QSPI2 output DSADC channel 2 output VADC output VADC output Reserved General-purpose input GTM input SENT input DSADC channel 2 input B DSADC channel 2 input E General-purpose output GTM output ASCLIN3 output QSPI2 output PSI5 output VADC output VADC output Reserved

Data Sheet

TOC-276

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-67 Port 33 Functions (cont'd)

Pin

Symbol

Ctrl

Y11

P33.3

I

TIN25

PSIRX1C

SENT7C

DSCIN1B

P33.3

O0

TOUT25

O1

­

O2

­

O3

DSCOUT1

O4

VADCEMUX00

O5

VADCG2BFL3

O6

­

O7

W12

P33.4

I

TIN26

SENT6C

CTRAPC

DSDIN1B

DSITR0F

P33.4

O0

TOUT26

O1

ARTS2

O2

SLSO212

O3

PSITX1

O4

VADCEMUX12

O5

VADCG0BFL0

O6

­

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input PSI5 input SENT input DSADC channel 1 input B General-purpose output GTM output Reserved Reserved DSADC channel 1 output VADC output VADC output Reserved General-purpose input GTM input SENT input CCU61 input DSADC channel 1 input DSADC channel 0 input F General-purpose output GTM output ASCLIN2 output QSPI2 output PSI5 output VADC output VADC output Reserved

Data Sheet

TOC-277

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-67 Port 33 Functions (cont'd)

Pin

Symbol

Ctrl

Y12

P33.5

I

TIN27

ACTS2B

PSIRX2C

PSISRXC

SENT5C

CCPOS2C

T4EUDB

DSCIN0B

DSITR1F

P33.5

O0

TOUT27

O1

SLSO07

O2

SLSO17

O3

DSCOUT0

O4

VADCEMUX11

O5

VADCG0BFL1

O6

­

O7

W13

P33.6

I

TIN28

SENT4C

CCPOS1C

T2EUDB

DSDIN0B

DSITR2F

P33.6

O0

TOUT28

O1

ASLSO2

O2

SLSO211

O3

PSITX2

O4

VADCEMUX10

O5

VADCG1BFL0

O6

PSISTX

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input ASCLIN2 input PSI5 input PSI5-S input SENT input CCU61 input GPT120 input DSADC channel 0 input B DSADC channel 1 input F General-purpose output GTM output QSPI0 output QSPI1 output DSADC channel 0 output VADC output VADC output Reserved General-purpose input GTM input SENT input CCU61 input GPT120 input DSADC channel 0 input B DSADC channel 2 input F General-purpose output GTM output ASCLIN2 output QSPI2 output PSI5 output VADC output VADC output PSI5-S output

Data Sheet

TOC-278

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-67 Port 33 Functions (cont'd)

Pin

Symbol

Ctrl Type

Y13

P33.7

TIN29

RXDCAN0E

I

LP /

PU1 /

VEXT

REQ8

CCPOS0C

T2INB

P33.7

O0

TOUT29

O1

ASCLK2

O2

SLSO47

O3

­

O4

­

O5

VADCG1BFL1

O6

­

O7

W14

P33.8 TIN30 ARX2E

I

MP /

HighZ /

VEXT

EMGSTOPA

P33.8

O0

TOUT30

O1

ATX2

O2

SLSO42

O3

­

O4

TXDCAN0

O5

­

O6

COUT62

O7

SMUFSP

HWOU T

Y14

P33.9

TIN31

HSIC3INA

I

LP /

PU1 /

VEXT

P33.9

O0

TOUT31

O1

ATX2

O2

SLSO41

O3

ASCLK2

O4

­

O5

­

O6

CC62

O7

Function General-purpose input GTM input CAN node 0 input SCU input CCU61 input GPT120 input General-purpose output GTM output ASCLIN2 output QSPI4 output Reserved Reserved VADC output Reserved General-purpose input GTM input ASCLIN2 input SCU input General-purpose output GTM output ASCLIN2 output QSPI4 output Reserved CAN node 0 output Reserved CCU61 output SMU
General-purpose input GTM input QSPI3 input General-purpose output GTM output ASCLIN2 output QSPI4 output ASCLIN2 output Reserved Reserved CCU61 output

Data Sheet

TOC-279

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-67 Port 33 Functions (cont'd)

Pin

Symbol

Ctrl

W15

P33.10

I

TIN32

SLSI4A

HSIC3INB

P33.10

O0

TOUT32

O1

SLSO16

O2

SLSO40

O3

ASLSO1

O4

PSISCLK

O5

­

O6

COUT61

O7

Y15

P33.11

I

TIN33

SCLK4A

P33.11

O0

TOUT33

O1

ASCLK1

O2

SCLK4

O3

­

O4

­

O5

DSCGPWMN

O6

CC61

O7

W16

P33.12

I

TIN34

MTSR4A

P33.12

O0

TOUT34

O1

ATX1

O2

MTSR4

O3

ASCLK1

O4

­

O5

DSCGPWMP

O6

COUT60

O7

Type MP / PU1 / VEXT
MP / PU1 / VEXT
MP / PU1 / VEXT

Function General-purpose input GTM input QSPI4 input QSPI3 input General-purpose output GTM output QSPI1 output QSPI4 output ASCLIN1 output PSI5-S output Reserved CCU61 output General-purpose input GTM input QSPI4 input General-purpose output GTM output ASCLIN1 output QSPI4 output Reserved Reserved DSADC channel output CCU61 output General-purpose input GTM input QSPI4 input General-purpose output GTM output ASCLIN1 output QSPI4 output ASCLIN1 output Reserved DSADC output CCU61 output

Data Sheet

TOC-280

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-67 Port 33 Functions (cont'd)

Pin

Symbol

Ctrl Type

Y16

P33.13

TIN35

ARX1F

I

MP /

PU1 /

VEXT

MRST4A

DSSGNB

INJ11

P33.13

O0

TOUT35

O1

ATX1

O2

MRST4

O3

SLSO26

O4

­

O5

DCDCSYNC

O6

CC60

O7

T14

P33.14

TIN143

TGI6

I

LP /

PU1 /

VEXT

SCLK2D

P33.14

O0

TOUT143

O1

­

O2

SCLK2

O3

­

O4

­

O5

­

O6

CC62

O7

TGO6

HWOU T

Function General-purpose input GTM input ASCLIN1 input QSPI4 input DSADC channel input B MSC1 input General-purpose output GTM output ASCLIN1 output QSPI4 output QSPI2 output Reserved SCU output CCU61 output General-purpose input GTM input OCDS input QSPI2 input General-purpose output GTM output Reserved QSPI2 output Reserved Reserved Reserved CCU60 output OCDS; ENx

Data Sheet

TOC-281

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-67 Port 33 Functions (cont'd)

Pin

Symbol

Ctrl Type

U14

P33.15

TIN144

TGI7

I

LP /

PU1 /

VEXT

P33.15

O0

TOUT144

O1

­

O2

SLSO211

O3

­

O4

­

O5

­

O6

COUT62

O7

TGO7

HWOU T

Function General-purpose input GTM input OCDS input General-purpose output GTM output Reserved QSPI2 output Reserved Reserved Reserved CCU60 output OCDS; ENx

Table 2-68 Port 34 Functions

Pin

Symbol

Ctrl

U11

P34.1

I

TIN146

P34.1

O0

TOUT146

O1

ATX0

O2

­

O3

TXDCAN0

O4

TXDCANr0

O5

­

O6

COUT63

O7

T12

P34.2

I

TIN147

ARX0D

RXDCAN0G

RXDCANr0C

P34.2

O0

TOUT147

O1

­

O2

­

O3

­

O4

­

O5

­

O6

CC60

O7

Data Sheet

Type LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input General-purpose output GTM output ASCLIN0 output Reserved CAN node 0 output CAN node 0 output (MultiCANr+) Reserved CCU60 output General-purpose input GTM input ASCLIN0 input CAN node 0 input CAN node 0 input (MultiCANr+) General-purpose output GTM output Reserved Reserved Reserved Reserved Reserved CCU60 output

TOC-282

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-68 Port 34 Functions (cont'd)

Pin

Symbol

Ctrl

U12

P34.3

I

TIN148

P34.3

O0

TOUT148

O1

­

O2

­

O3

SLSO210

O4

­

O5

­

O6

COUT60

O7

T13

P34.4

I

TIN149

MRST2D

P34.4

O0

TOUT149

O1

­

O2

­

O3

MRST2

O4

­

O5

­

O6

CC61

O7

U13

P34.5

I

TIN150

MTSR2D

P34.5

O0

TOUT150

O1

­

O2

­

O3

MTSR2

O4

­

O5

­

O6

COUT61

O7

Type LP / PU1 / VEXT
LP / PU1 / VEXT
LP / PU1 / VEXT

Function General-purpose input GTM input General-purpose output GTM output Reserved Reserved QSPI2 output Reserved Reserved CCU60 output General-purpose input GTM input QSPI2 input General-purpose output GTM output Reserved Reserved QSPI2 output Reserved Reserved CCU60 output General-purpose input GTM input QSPI2 input General-purpose output GTM output Reserved Reserved QSPI2 output Reserved Reserved CCU60 output

Data Sheet

TOC-283

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-69 Port 40 Functions

Pin

Symbol

Ctrl

W2

P40.0

I

VADCG3.0

DS2PB

CCPOS0D

SENT0A

W1

P40.1

I

VADCG3.1

DS2NB

CCPOS1B

SENT1A

V2

P40.2

I

VADCG3.2

CCPOS1D

SENT2A

V1

P40.3

I

VADCG3.3

CCPOS2B

SENT3A

P4

P40.4

I

VADCG4.0

CCPOS2D

SENT4A

R1

P40.5

I

VADCG4.1

CCPOS0D

SENT5A

N4

P40.6

I

VADCG4.4

DS3PA

CCPOS1B

SENT6A

Type S / HighZ / VDDM
S / HighZ / VDDM
S / HighZ / VDDM
S / HighZ / VDDM
S / HighZ / VDDM
S / HighZ / VDDM
S / HighZ / VDDM

Function General-purpose input VADC analog input channel 0 of group 3 DSADC: positive analog input of channel 2, pin B CCU60 input SENT input General-purpose inpu.t VADC analog input channel 1 of group 3 (with pull down diagnostics) DSADC: negative analog input channel 2, pin B CCU60 input SENT input General-purpose inpu.t VADC analog input channel 2 of group 3 (with pull down diagnostics) CCU60 input SENT input General-purpose input VADC analog input channel 3 of group 3 (with pull down diagnostics) CCU60 input SENT input General-purpose input VADC analog input channel 0 of group 4 CCU60 input SENT input General-purpose input VADC analog input channel 1 of group 4 CCU61 input SENT input General-purpose input VADC analog input channel 4 of group 4 DSADC: positive analog input of channel 3, pin A CCU61 input SENT input

Data Sheet

TOC-284

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-69 Port 40 Functions (cont'd)

Pin

Symbol

Ctrl

P2

P40.7

I

VADCG4.5

DS3NA

CCPOS1D

SENT7A

N5

P40.8

I

VADCG4.6

DS3PB

CCPOS2B

SENT8A

P1

P40.9

I

VADCG4.7

DS3NB

CCPOS2D

SENT9A

Type S / HighZ / VDDM
S / HighZ / VDDM
S / HighZ / VDDM

Function General-purpose input VADC analog input channel 5 of group 4 DSADC: negative analog input channel 3, pin A CCU61 input SENT input General-purpose input VADC analog input channel 6 of group 4 DSADC: positive analog input of channel 3, pin B CCU61 input SENT input General-purpose input VADC analog input channel 7 of group 4 DSADC: negative analog input channel 3, pin B CCU61 input SENT input

Table 2-70 Analog Inputs

Pin

Symbol

T10

AN0

VADCG0.0

DS1PA

U10

AN1

VADCG0.1

DS1NA

W9

AN2

VADCG0.2

DS0PA

U9

AN3

VADCG0.3

DS0NA

T9

AN4

VADCG0.4

Y9

AN5

VADCG0.5

T8

AN6

VADCG0.6

U8

AN7

VADCG0.7

Ctrl Type

Function

I

D / HighZ / Analog input 0

VDDM

VADC analog input channel 0 of group 0

DSADC: positive analog input of channel 1, pin A

I

D / HighZ / Analog input 1

VDDM

VADC analog input channel 1 of group 0

DSADC: negative analog input channel 1, pin A

I

D / HighZ / Analog input 2

VDDM

VADC analog input channel 2 of group 0

DSADC: positive analog input of channel 0, pin A

I

D / HighZ / Analog input 3

VDDM

VADC analog input channel 3 of group 0

DSADC: negative analog input channel 0, pin A

I

D / HighZ / Analog input 4

VDDM

VADC analog input channel 4 of group 0

I

D / HighZ / Analog input 5

VDDM

VADC analog input channel 5 of group 0

I

D / HighZ / Analog input 6

VDDM

VADC analog input channel 6 of group 0

I

D / HighZ / Analog input 7

VDDM

VADC analog input channel 7 of group 0

Data Sheet

TOC-285

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-70 Analog Inputs (cont'd)

Pin

Symbol

Ctrl

W8

AN8

I

VADCG1.0

U7

AN9

I

VADCG1.1

Y8

AN10

I

VADCG1.2

W7

AN11

I

VADCG1.3

T7

AN12

I

VADCG1.4

W6

AN13

I

VADCG1.5

U6

AN14

I

VADCG1.6

T6

AN15

I

VADCG1.7

W5

AN16

I

VADCG2.0

U5

AN17

I

VADCG2.1

W4

AN18

I

VADCG2.2

W3

AN19

I

VADCG2.3

Y3

AN20

I

VADCG2.4

DS2PA

Y2

AN21

I

VADCG2.5

DS2NA

T5

AN22

I

VADCG2.6

R5

AN23

I

VADCG2.7

Type

Function

D / HighZ / Analog input 8

VDDM

VADC analog input channel 0 of group 1

D / HighZ / Analog input 9

VDDM

VADC analog input channel 1 of group 1

D / HighZ / Analog input 10

VDDM

VADC analog input channel 2 of group 1

D / HighZ / Analog input 11

VDDM

VADC analog input channel 3 of group 1 (with pull

down diagnostics)

D / HighZ / Analog input 12

VDDM

VADC analog input channel 4 of group 1

D / HighZ / Analog input 13

VDDM

VADC analog input channel 5 of group 1

D / HighZ / Analog input 14

VDDM

VADC analog input channel 6 of group 1

D / HighZ / Analog input 15

VDDM

VADC analog input channel 7 of group 1

D / HighZ / Analog input 16

VDDM

VADC analog input channel 0 of group 2

D / HighZ / Analog input 17

VDDM

VADC analog input channel 1 of group 2

D / HighZ / Analog input 18

VDDM

VADC analog input channel 2 of group 2

D / HighZ / Analog input 19

VDDM

VADC analog input channel 3 of group 2 (with pull

down diagnostics)

D / HighZ / Analog input 20

VDDM

VADC analog input channel 4 of group 2

DSADC: positive analog input of channel 2, pin A

D / HighZ / Analog input 21

VDDM

VADC analog input channel 5 of group 2

DSADC: negative analog input channel 2, pin A

D / HighZ / Analog input 22

VDDM

VADC analog input channel 6 of group 2

D / HighZ / Analog input 23

VDDM

VADC analog input channel 7 of group 2

Data Sheet

TOC-286

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-70 Analog Inputs (cont'd)

Pin

Symbol

Ctrl

W2

AN24

I

VADCG3.0

DS2PB

SENT0A

W1

AN25

I

VADCG3.1

DS2NB

SENT1A

V2

AN26

I

VADCG3.2

SENT2A

V1

AN27

I

VADCG3.3

SENT3A

U2

AN28

I

VADCG3.4

U1

AN29

I

VADCG3.5

T4

AN30

I

VADCG3.6

R4

AN31

I

VADCG3.7

P4

AN32

I

VADCG4.0

SENT4A

R1

AN33

I

VADCG4.1

SENT5A

P5

AN34

I

VADCG4.2

R2

AN35

I

VADCG4.3

Type

Function

S / HighZ / VDDM

Analog input 24 VADC analog input channel 0 of group 3 DSADC: positive analog input of channel 2, pin B

SENT input channel 0, pin A

S / HighZ / VDDM

Analog input 24
VADC analog input channel 1 of group 3 (with pull down diagnostics)

DSADC: negative analog input channel 2, pin B

SENT input channel 1, pin A

S / HighZ / VDDM

Analog input 26
VADC analog input channel 2 of group 3 (with pull down diagnostics)

SENT input channel 2, pin A

S / HighZ / VDDM

Analog input 27
VADC analog input channel 3 of group 3 (with pull down diagnostics)

SENT input channel 3, pin A

D / HighZ / Analog input 28

VDDM

VADC analog input channel 4 of group 3 (with pull

down diagnostics)

D / HighZ / Analog input 29

VDDM

VADC analog input channel 5 of group 3 (with pull

down diagnostics)

D / HighZ / Analog input 30

VDDM

VADC analog input channel 6 of group 3

D / HighZ / Analog input 31

VDDM

VADC analog input channel 7 of group 3

S / HighZ / VDDM

Analog input 32 VADC analog input channel 0 of group 4 SENT input channel 4, pin A

S / HighZ / VDDM

Analog input 33 VADC analog input channel 1 of group 4 SENT input channel 5, pin A

D / HighZ / Analog input 34

VDDM

VADC analog input channel 2 of group 4

D / HighZ / Analog input 35

VDDM

VADC analog input channel 3 of group 4 (with pull

down diagnostics)

Data Sheet

TOC-287

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-70 Analog Inputs (cont'd)

Pin

Symbol

Ctrl

N4

AN36

I

VADCG4.4

DS3PA

SENT6A

P2

AN37

I

VADCG4.5

DS3NA

SENT7A

N5

AN38

I

VADCG4.6

DS3PB

SENT8A

P1

AN39

I

VADCG4.7

DS3NB

SENT9A

M5

AN40

I

VADCG5.0

M4

AN41

I

VADCG5.1

L5

AN42

I

VADCG5.2

L4

AN43

I

VADCG5.3

N1

AN44

I

VADCG5.4

DS3PC

N2

AN45

I

VADCG5.5

DS3NC

M1

AN46

I

VADCG5.6

DS3PD

M2

AN47

I

VADCG5.7

DS3ND

Type

Function

S / HighZ / VDDM

Analog input 34 VADC analog input channel 4 of group 4 DSADC: positive analog input of channel 3, pin A

SENT input channel 6, pin A

S / HighZ / VDDM

Analog input 37 VADC analog input channel 5 of group 4 DSADC: negative analog input channel 3, pin A

SENT input channel 7, pin A

S / HighZ / VDDM

Analog input 38 VADC analog input channel 6 of group 4 DSADC: positive analog input of channel 3, pin B

SENT input channel 8, pin A

S / HighZ / VDDM

Analog input 39 VADC analog input channel 7 of group 4 DSADC: negative analog input channel 3, pin B

SENT input channel 9, pin A

D / HighZ / Analog input 40

VDDM

VADC analog input channel 0 of group 5

D / HighZ / Analog input 41

VDDM

VADC analog input channel 1 of group 5

D / HighZ / Analog input 42

VDDM

VADC analog input channel 2 of group 5

D / HighZ / Analog input 43

VDDM

VADC analog input channel 3 of group 5 (with pull

down diagnostics)

D / HighZ / Analog input 44

VDDM

VADC analog input channel 4 of group 5

DSADC: positive analog input of channel 3, pin C

D / HighZ / Analog input 45

VDDM

VADC analog input channel 5 of group 5

DSADC: negative analog input channel 3, pin C

D / HighZ / Analog input 46

VDDM

VADC analog input channel 6 of group 5

DSADC: positive analog input of channel 3, pin D

D / HighZ / Analog input 47

VDDM

VADC analog input channel 7 of group 5

DSADC: negative analog input channel 3, pin D

Data Sheet

TOC-288

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-71 System I/O

Pin

Symbol

G17

PORST

F16

ESR0

EVRWUP

G16

ESR1

W17

EVRWUP VGATE1P

K16

TMS

DAP1

L19

TRST

J16

TCK

DAP0

M20

XTAL1

M19

XTAL2

Table 2-72 Supply Pin Y6
Y7

Ctrl Type

Function

I

PORST / Power On Reset Input

PD /

Additional strong PD in case of power fail.

VEXT

I/O

MP /

OD /

VEXT

External System Request Reset 0 Default configuration during and after reset is opendrain driver. The driver drives low during power-on reset. This is valid additionally after deactivation of PORST until the internal reset phase has finished. See also SCU chapter for details. Default after power-on can be different. See also SCU chapter ´Reset Control Unit´ and SCU_IOCR register description.

I

EVR Wakeup Pin

I/O

MP /

PU1 /

VEXT

External System Request Reset 1 Default NMI function. See also SCU chapter ´Reset Control Unit´ and SCU_IOCR register description.

I

EVR Wakeup Pin

O

VGATE1P / External Pass Device gate control for EVR13

- /

VEXT

I

A2 /

JTAG Module State Machine Control Input

I/O

PD /

Device Access Port Line 1

VDDP3

I

A2 /

JTAG Module Reset/Enable Input

PD /

VDDP3

I

A2 /

JTAG Module Clock Input

I

PD /

Device Access Port Line 0

VDDP3

I

XTAL1 / Main Oscillator/PLL/Clock Generator Input

- /

VDDP3

O

XTAL2 / Main Oscillator/PLL/Clock Generator Output

- /

VDDP3

Symbol VAREF1
VAGND1

Ctrl Type Function

I

Vx

Positive Analog Reference Voltage 1

I

Vx

Negative Analog Reference Voltage 1

Data Sheet

TOC-289

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-72 Supply (cont'd) Pin T1

Symbol VAREF2

Ctrl Type Function

I

Vx

Positive Analog Reference Voltage 2

T2

VAGND2

I

Vx

Negative Analog Reference Voltage 2

Y5

VDDM

I

Vx

ADC Analog Power Supply (3.3V / 5V)

G8, H7

VDD / VDDSB I

P8, P13, N7, N14, H14, G13 VDD

I

Vx

Emulation Device: Emulation SRAM

Standby Power Supply (1.3V) (Emulation

Device only).

Production Device: VDD (1.3V).

Vx

Digital Core Power Supply (1.3V)

N19 A2, B3, V19, W20

VDD VEXT

I

Vx

Digital Core Power Supply (1.3V).

The supply pin inturn supplies the main

XTAL Oscillator/PLL (1.3V) . A higher

decoupling capacitor is therefore

recommended to the VSS pin for better

noise immunity.

I

Vx

External Power Supply (5V / 3.3V)

B18, A19 N20
E15, D16

VDDP3 VDDP3
VDDFL3

I

Vx

Digital Power Supply for Flash (3.3V).

Can be also used as external 3.3V Power

Supply for VFLEX.

I

Vx

Digital Power Supply for Oscillator,

LVDSH and A2 pads (3.3V).

The supply pin inturn supplies the main

XTAL Oscillator/PLL (3.3V) . A higher

decoupling capacitor is therefore

recommended to the VSS pin for better

noise immunity.

I

Vx

Flash Power Supply (3.3V)

D5

VFLEX

I

Vx

Digital Power Supply for Flex Port Pads

(5V / 3.3V)

Y4

VSSM

I

Vx

Analog Ground for VDDM

T11

VEVRSB

B2, D4, E5, T16, U17, W19, VSS Y20, E16, D17, B19, A20, L20

I

Vx

Standby Power Supply (3.3V/5V) for the

Standby SRAM (CPU0.DSPR).

If Standby mode is not used: To be

handled like VEXT (3.3V/5V).

I

Vx

Digital Ground (outer balls)

P9, P12, N9, N10, N11, N12 VSS

I

Vx

Digital Ground (center balls)

Data Sheet

TOC-290

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-72 Supply (cont'd)

Pin

Symbol

M7, M8, M10, M11, M13, M14 VSS

Ctrl Type Function

I

Vx

Digital Ground (center balls)

L8, L9, L10, L11, L12, L13 VSS

I

Vx

Digital Ground (center balls)

K8, K9, K10, K11, K12, K13 VSS

I

Vx

Digital Ground (center balls)

J7, J8, J10, J11, J13, J14 VSS

I

Vx

Digital Ground (center balls)

H9, H10, H11, H12, G9, G10, VSS G11, G12

I

Vx

Digital Ground (center balls)

P10 P11 L7 K7 L14 K14
A1, Y1, U4 Data Sheet

VSS VSS VSS VSS VSS NC / VDDPSB
NC

I

Vx

Digital Ground (center balls)

This ball is used in the Emulation Device

as

AGBT TX0N

I

Vx

Digital Ground (center balls)

This ball is used in the Emulation Device

as

AGBT TX0P

I

Vx

Digital Ground (center balls)

This ball is used in the Emulation Device

as

AGBT CLKN

I

Vx

Digital Ground (center balls)

This ball is used in the Emulation Device

as

AGBT CLKP

I

Vx

Digital Ground (center balls)

This ball is used in the Emulation Device

as

AGBT ERR

I

NCVDD Emulation Device: Power Supply (3.3V)

PSB for DAP/JTAG pad group. Can be

connected to VDDP or can be left

unsupplied (see document ´AurixED´ /

Aurix Emulation Devices specification.

Production Device: This pin is not connected on package level. It can be connected on PCB level to VDDP or Ground or can be left unsupplied.

I

NC1 Not Connected.

These pins are not connected on

package level and will not be used for

future extensions.

TOC-291

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
Legend:
Column "Ctrl.":
I = Input (for GPIO port Lines with IOCR bit field Selection PCx = 0XXXB) O = Output O0 = Output with IOCR bit field selection PCx = 1X000B O1 = Output with IOCR bit field selection PCx = 1X001B (ALT1) O2 = Output with IOCR bit field selection PCx = 1X010B (ALT2) O3 = Output with IOCR bit field selection PCx = 1X011B (ALT3) O4 = Output with IOCR bit field selection PCx = 1X100B (ALT4) O5 = Output with IOCR bit field selection PCx = 1X101B (ALT5) O6 = Output with IOCR bit field selection PCx = 1X110B (ALT6) O7 = Output with IOCR bit field selection PCx = 1X111B (ALT7) Column "Type":
LP = Pad class LP (5V/3.3V, Class LP parameters for digital input / output and class D parameters for analog input function) MP = Pad class MP (5V/3.3V) MP+ = Pad class MP+ (5V/3.3V) MPR = Pad class MPR (5V/3.3V) A2 = Pad class A2 (3.3V) LVDSM = Pad class LVDSM (5V/3.3V) LVDSH = Pad class LVDSH (3.3V) S = Pad class S (Class S parameters for digital input and class D parameters for analog input function) D = Pad class D (VADC / DSADC) PU = with pull-up device connected during reset (PORST = 0) PU1 = with pull-up device connected during reset (PORST = 0)1) 2) 3) PD = with pull-down device connected during reset (PORST = 0) PD1 = with pull-down device connected during reset (PORST = 0)1) 2) 3) PX = Behavior depends on usage: PD in EVR13 SMPS Mode and PU1 in GPIO Mode OD = open drain during reset (PORST = 0) HighZ = tri-state during reset (PORST = 0) PORST = PORST input pad XTAL1 = XTAL1 input pad XTAL2 = XTAL2 input pad VGATE1P = VGATE1P VGATE3P = VGATE3P Vx = Supply NC = These pins are reserved for future extensions and shall not be connected externally NC1 = These pins are not connected on package level and will not be used for future extensions NCVDDPSB = This pin has a different functionality in an Production Device and an Emulation Device. For details pls. see Pin/Ball description of this pin. NCVDDSB = This pin has a different functionality in an Production Device and an Emulation Device. For details pls. see Pin/Ball description of this pin.

1) The default state of GPIOs (Px.y) during and after PORST active is controllled via HWCFG[6] (P14.4). HWCFG[6] has a weak internal pull-up active at start-up if the pin is left unconnected.See also User´s Manual, "Introduction Chapter", "General Purpose I/O Ports and Peripheral I/O Lines", Figure: "Default state of port pins during and after reset".
2) If HWCFG[6] is left unconnected or is externally pulled high, weak internal pull-ups (PU1) / pull-downs (PD1) are active during and after reset.
3) If HWCFG[6] is connected to ground, the PD1 / PU1 pins are predominantly in HighZ during and after reset.

Data Sheet

TOC-292

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC297x Pin Definition and Functions:
2.3.2 Emergency Stop Function
The Emergency Stop function can be used to force GPIOs (General Purpose Inputs/Outputs) via an external input signal (EMGSTOPA or EMGSTOPB) into a defined state: · Input state and · PU or High-Z depending on HWCFG[6] level latched during Porst active Control of the Emergency Stop function: · The Emergency Stop function can be enabled/disabled in the SCU (see chapter "SCU", "Emergency Stop
Control") · The Emergency Stop input signal, EMGSTOPA (P33.8) / EMGSTOPB (P21.2) , can selected in the SCU (see
chapter "SCU", "Emergency Stop Control") · On port level, each GPIO can be enabled/disabled for the Emergency Stop function via the Px_ESR (Port x
Emergency Stop) registers in the port control logic (see chapter "General Purpose I/O Ports and Peripheral I/O Lines", "Emergency Stop Register"). The Emergency Stop function is available for all GPIO Ports with the following exceptions: · Not available for P20.2 (General Purpose Input/GPI only, overlayed with Testmode) · Not available for P40.x (analoge input ANx overlayed with GPI) · Not available for P32.0 EVR13 SMPS mode. · Not available for dedicated I/O without General Purpose Output function (e.g ESRx, TMS, TCK) The Emergency Stop function can be overruled on the following GPIO Ports: · P00.x and P02.x: Emergency Stop can be overruled by the 8-Bit Standby Controller (SBR), if implemented. Overruling can be disabled via the control registers P00_SCR / P02_SCR (see chapter "General Purpose I/O Ports and Peripheral I/O Lines", P00 / P01) · P00.x: Emergency Stop can be overruled by the VADC. Overruling can be disabled via the control register P00_SCR (see chapter "General Purpose I/O Ports and Peripheral I/O Lines", P00) · P14.0 and P14.1: Emergency Stop can be overruled in the DXCPL mode (DAP over can physical layer mode). No Overruling in the DXCM (Debug over can message) mode · P21.6: Emergency Stop can be overruled in JTAG mode if this pin is used as TDI · P21.7: Emergency Stop can be overruled in JTAG or Three Pin DAP mode · P20.0: Emergency Stop can be overruled in JTAG mode if this GPIO is used as TDI · P33.8: Emergency Stop can be overruled if this pin is used as safety output pin (SMUFSP)
2.3.3 Pull-Up/Pull-Down Reset Behavior of the Pins

Table 2-73 List of Pull-Up/Pull-Down Reset Behavior of the Pins

Pins

PORST = 0

PORST = 1

all GPIOs

Pull-up if HWCFG[6] = 1 or High-Z if HWCFG[6] = 0

TDI, TESTMODE PORST1) TRST, TCK, TMS ESR0

Pull-up
Pull-down with IPORST relevant
Pull-down
The open-drain driver is used to drive low.2)

Pull-down with IPDLI relevant
Pull-up3)

Data Sheet

TOC-293

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC297x Pin Definition and Functions:

Table 2-73 List of Pull-Up/Pull-Down Reset Behavior of the Pins

Pins

PORST = 0

PORST = 1

ESR1

Pull-up3)

TDO

Pull-up

High-Z/Pull-up4)

1) Pull-down with IPORST relevant is always activated when a primary supply monitor detects a violation. 2) Valid additionally after deactivation of PORST until the internal reset phase has finished. See the SCU chapter for details.

3) See the SCU_IOCR register description.

4) Depends on JTAG/DAP selection with TRST.

In case of leakage test (PORST = 0 and TESTMODE = 0), the pull-down of the TRST pin is switched off. In case of an user application (TESTMODE = 1), the pull-down of the TRST is always switched on.

Data Sheet

TOC-294

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC29x Bare Die Pad Definition

2.4

TC29x Bare Die Pad Definition

The TC290 / TC297 / TC298 / TC299 BC-Step Bare Die Logic Symbol is shown in Figure 2-4.

Table 2-74 describes the pads of the TC290 / TC297 / TC298 / TC299 bare die. It describes also the mapping of VADC / DS-ADC channels to the analog inputs (ANx) and the mapping of Port functions to the pads.

The detailed description of the port functions (Px.y) can be found in the User's Manual chapter "General Purpose I/O Ports and Peripheral I/O LInes (Ports)".

Pad 366 Pad 367

Pad 234 Pad 233

Y 0.0 X

Pad 480

Pad 102

Pad 1

Pad 101

Figure 2-4 TC290 / TC297 / TC298 / TC299 Logic Symbol for the Bare Die.

Table 2-74 TC29x Bare Die Pad List

Number Pad Name

Pad Type

X

1

VEXT

Vx

-4328000

2

P15.10

LP / PU1 / VEXT -4123000

3

P15.2

MP / PU1 / VEXT -4193000

4

P15.11

LP / PU1 / VEXT -3983000

5

P15.4

MP / PU1 / VEXT -4053000

6

P15.12

LP / PU1 / VEXT -3863000

7

P15.1

LP / PU1 / VEXT -3923000

8

P15.13

LP / PU1 / VEXT -3753000

9

VSS

Vx

-3808000

10

P15.14

MP / PU1 / VEXT -3603000

11

P15.3

MP / PU1 / VEXT -3683000

12

P15.15

MP / PU1 / VEXT -3443000

Y -4295000 -4186500 -4295000 -4186500 -4295000 -4186500 -4295000 -4186500 -4295000 -4186500 -4295000 -4186500

Comment Must be bonded to VEXT GPIO GPIO GPIO GPIO GPIO GPIO GPIO Must be bonded to VSS GPIO GPIO GPIO

Data Sheet

TOC-295

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC29x Bare Die Pad Definition

Table 2-74 TC29x Bare Die Pad List (cont'd)

Number Pad Name

Pad Type

X

13

P15.5

MP / PU1 / VEXT -3523000

14

P15.6

MP / PU1 / VEXT -3283000

15

P15.7

MP / PU1 / VEXT -3363000

16

P15.8

MP / PU1 / VEXT -3153000

17

VEXT

Vx

-3218000

18

P14.1

MP / PU1 / VEXT -3073000

19

P14.0

MP+ / PU1 / VEXT

-2983000

20

P14.3

LP / PU1 / VEXT -2843000

21

P14.2

LP / PU1 / VEXT -2903000

22

P14.4

23

VSS

24

VDD

25

VSS

26

VDDFL3

27

P14.11

28

VDDFL3

29

P14.5

30

P14.12

31

P14.6

32

P14.13

33

P14.7

34

P14.14

35

VEXT

36

P14.8

37

P14.9

38

P14.15

39

P14.10

40

VDDFL3

41

VSS

42

P13.0

Data Sheet

LP / PU1 / VEXT -2733000

Vx

-2788000

Vx

-2674000

Vx

-2574000

Vx

-2505000

LP / PU1 / VEXT -2380000

Vx

-2437500

MP+ / PU1 / VEXT

-2300000

LP / PU1 / VEXT -2220000

MP+ / PU1 / VEXT

-2140000

MP+ / PU1 / VEXT

-2040000

LP / PU1 / VEXT -1960000

MP+ / PU1 / VEXT

-1880000

Vx

-1805000

LP / PU1 / VEXT -1750000

MP+ / PU1 / VEXT

-1670000

LP / PU1 / VEXT -1590000

MP+ / PU1 / VEXT

-1510000

Vx

-1410000

Vx

-1345000

LVDSM_N / PU1 -1270000 / VEXT

TOC-296

Y -4295000 -4186500 -4295000 -4186500 -4295000 -4295000 -4186500
-4186500 -4295000
-4186500 -4295000 -4295000 -4295000 -4186500 -4186500 -4295000 -4295000
-4186500 -4295000
-4186500
-4295000 -4186500
-4295000 -4186500 -4295000
-4186500 -4295000
-4186500 -4295000 -4186500

Comment GPIO GPIO GPIO GPIO Must be bonded to VEXT GPIO GPIO
GPIO Must be bonded to VEXT if EVR13 active. Must be bonded to VSS if EVR13 inactive. GPIO Must be bonded to VSS Must be bonded to VDD Must be bonded to VSS Must be bonded to VDDP3 GPIO Must be bonded to VDDP3 GPIO
GPIO GPIO
GPIO
GPIO GPIO
Must be bonded to VEXT GPIO GPIO
GPIO GPIO
Must be bonded to VDDP3 Must be bonded to VSS GPIO
V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC29x Bare Die Pad Definition

Table 2-74 TC29x Bare Die Pad List (cont'd)

Number Pad Name

Pad Type

X

43

P13.1

LVDSM_P / PU1 -940000 / VEXT

44

VEXT

Vx

-865000

45

P13.2

LVDSM_N / PU1 -790000 / VEXT

46

P13.3

LVDSM_P / PU1 -460000 / VEXT

47

VSS

Vx

-385000

48

P13.4

LVDSM_N / PU1 -310000 / VEXT

49

P13.5

LVDSM_P / PU1 20000 / VEXT

50

VEXT

Vx

95000

51

P13.6

LVDSM_N / PU1 170000 / VEXT

52

P13.7

LVDSM_P / PU1 500000 / VEXT

53

P13.11

LP / PU1 / VEXT 580000

54

P13.12

LP / PU1 / VEXT 640000

55

VDDP3

Vx

697500

56

VDDP3

Vx

765000

57

VEXT

Vx

830000

58

VEXT

Vx

880000

59

VDD

Vx

955000

60

VSS

Vx

1055000

61

P13.13

LP / PU1 / VEXT 1135000

62

P13.9

MP / PU1 / VEXT 1205000

63

P13.14

LP / PU1 / VEXT 1275000

64

VEXT

Vx

1330000

65

P13.10

LP / PU1 / VEXT 1385000

66

VDDFL3

Vx

1455000

67

VSS

Vx

1575000

68

VDDFL3

Vx

1542500

69

P13.15

LP / PU1 / VEXT 1660000

70

P12.0

LP / PU1 / VFLEX

1790000

71

P12.1

LP / PU1 / VFLEX

1850000

Y -4186500
-4295000 -4186500
-4186500
-4295000 -4186500
-4186500
-4295000 -4186500
-4186500
-4295000 -4186500 -4295000 -4186500 -4295000 -4186500 -4295000 -4295000 -4186500 -4295000 -4186500 -4295000 -4186500 -4295000 -4295000
-4186500 -4186500 -4186500
-4295000

Comment GPIO
Must be bonded to VEXT GPIO
GPIO
Must be bonded to VSS GPIO
GPIO
Must be bonded to VEXT GPIO
GPIO
GPIO GPIO Must be bonded to VDDP3 Must be bonded to VDDP3 Must be bonded to VEXT Must be bonded to VEXT Must be bonded to VDD Must be bonded to VSS GPIO GPIO GPIO Must be bonded to VEXT GPIO Must be bonded to VDDP3 Must be bonded to VSS (Double Pad / Center of Elephant Pad Opening) Must be bonded to VDDP3 GPIO GPIO
GPIO

Data Sheet

TOC-297

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC29x Bare Die Pad Definition

Table 2-74 TC29x Bare Die Pad List (cont'd)

Number Pad Name

Pad Type

72

P11.0

MP+ / PU1 / VFLEX

73

VSS

Vx

74

P11.1

MP+ / PU1 / VFLEX

75

VFLEX

Vx

X 1930000
2005000 2080000
2155000

76

P11.2

MPR/ PU1 / VFLEX

2230000

77

P11.4

MP+ / PU1 / VFLEX

2330000

78

P11.3

MPR/ PU1 / VFLEX

2430000

79

P11.5

LP / PU1 / VFLEX

2510000

80

P11.6

MPR/ PU1 / VFLEX

2590000

81

VSS

Vx

2665000

82

P11.9

MP+ / PU1 / VFLEX

2740000

83

P11.7

LP / PU1 / VFLEX

2820000

84

VFLEX

Vx

2935000

85

P11.8

86

P11.13

87

P11.10

88

P11.11

89

VSS

90

P11.12

91

P11.14

92

P11.15

93

P10.0

94

VEXT

Data Sheet

LP / PU1 / VFLEX

2880000

LP / PU1 / VFLEX

3050000

LP / PU1 / VFLEX

2990000

MP+ / PU1 / VFLEX

3130000

Vx

3215000

MPR/ PU1 / VFLEX

3300000

LP / PU1 / VFLEX

3390000

LP / PU1 / VFLEX

3460000

LP / PU1 / VEXT 3610000

Vx

3775000

TOC-298

Y -4186500 -4295000 -4186500 -4295000
-4186500 -4295000 -4186500 -4295000 -4186500 -4295000 -4186500 -4295000 -4295000
-4186500 -4295000 -4186500 -4186500 -4295000 -4186500 -4295000 -4186500 -4295000 -4295000

Comment GPIO
Must be bonded to VSS GPIO
Digital Power Supply for VFLEX Ports / Pads (5V / 3.3V) GPIO
GPIO
GPIO
GPIO
GPIO
Must be bonded to VSS GPIO
GPIO
Digital Power Supply for VFLEX Ports / Pads (5V / 3.3V) GPIO
GPIO
GPIO
GPIO
Must be bonded to VSS GPIO
GPIO
GPIO
GPIO Must be bonded to VEXT
V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC29x Bare Die Pad Definition

Table 2-74 TC29x Bare Die Pad List (cont'd)

Number Pad Name

Pad Type

X

95

P10.9

LP / PU1 / VEXT 3680000

96

P10.1

MP+ / PU1 / VEXT

3865000

97

P10.3

MP / PU1 / VEXT 3970000

98

P10.4

MP+ / PU1 / VEXT

4150000

99

P10.10

LP / PU1 / VEXT 4055000

100

P10.2

MP / PU1 / VEXT 4310000

101

P10.11

LP / PU1 / VEXT 4240000

102

P10.13

LP / PU1 / VEXT 4419500

103

VSS

Vx

4528000

104

P10.14

LP / PU1 / VEXT 4419500

105

P10.5

LP / PU1 / VEXT 4528000

106

P10.15

LP / PU1 / VEXT 4419500

107

P10.6

LP / PU1 / VEXT 4528000

108

P02.13

LP / PU1 / VEXT 4419500

109

P10.8

LP / PU1 / VEXT 4528000

110

P10.7

LP / PU1 / VEXT 4419500

111

VEXT

Vx

4528000

112

VDD

Vx

4528000

113

P02.12

LP / PU1 / VEXT 4419500

114

VSS

Vx

4528000

115

P02.0

MP+ / PU1 / VEXT

4528000

116

P02.14

LP / PU1 / VEXT 4419500

117

P02.1

LP / PU1 / VEXT 4528000

118

P02.15

MP+ / PU1 / VEXT

4419500

119

VSS

Vx

4528000

120

P02.2

MP+ / PU1 / VEXT

4419500

121

P02.3

LP / PU1 / VEXT 4528000

122

P02.4

MP+ / PU1 / VEXT

4419500

123

P02.9

LP / PU1 / VEXT 4528000

124

P02.5

MP+ / PU1 / VEXT

4419500

125

P02.10

LP / PU1 / VEXT 4528000

126

P02.6

MP / PU1 / VEXT 4419500

127

VEXT

Vx

4528000

Y -4186500 -4186500
-4295000 -4295000
-4186500 -4295000 -4186500 -4050000 -4105000 -3930000 -3990000 -3810000 -3870000 -3690000 -3750000 -3580000 -3635000 -3520000 -3360000 -3420000 -3280000
-3200000 -3140000 -3060000
-2985000 -2910000
-2830000 -2750000
-2670000 -2590000
-2510000 -2440000 -2375000

Comment GPIO GPIO
GPIO GPIO
GPIO GPIO GPIO GPIO Must be bonded to VSS GPIO GPIO GPIO GPIO GPIO GPIO GPIO Must be bonded to VEXT Must be bonded to VDD GPIO Must be bonded to VSS GPIO
GPIO GPIO GPIO
Must be bonded to VSS GPIO
GPIO GPIO
GPIO GPIO
GPIO GPIO Must be bonded to VEXT

Data Sheet

TOC-299

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC29x Bare Die Pad Definition

Table 2-74 TC29x Bare Die Pad List (cont'd)

Number Pad Name

Pad Type

X

128

P02.7

MP / PU1 / VEXT 4419500

129

P02.11

LP / PU1 / VEXT 4528000

130

P02.8

LP / PU1 / VEXT 4419500

131

VDD

Vx

4528000

132

VSS

Vx

4528000

133

P01.0

LP / PU1 / VEXT 4419500

134

VSS

Vx

4528000

135

VDD

136

P01.2

137

VSS

138

P01.1

139

P01.3

140

P01.8

141

P01.4

142

P01.9

143

P01.5

144

P01.10

145

VEXT

146

P01.11

147

P01.6

148

P01.12

149

P01.7

150

VDD

151

VSS

152

P01.13

153

VSS

154

P01.14

155

Reserved

156

P01.15

157

VEXT

158

P00.13

159

P00.0

160

P00.14

161

VSS

Data Sheet

Vx

4528000

LP / PU1 / VEXT 4419500

Vx

4528000

LP / PU1 / VEXT 4419500

LP / PU1 / VEXT 4528000

LP / PU1 / VEXT 4419500

LP / PU1 / VEXT 4528000

LP / PU1 / VEXT 4419500

LP / PU1 / VEXT 4528000

LP / PU1 / VEXT 4419500

Vx

4528000

LP / PU1 / VEXT 4419500

MP / PU1 / VEXT 4528000

MP+ / PU1 / VEXT

4419500

MP / PU1 / VEXT 4528000

Vx

4528000

Vx

4528000

MP+ / PU1 / VEXT

4419500

Vx

4528000

MP+ / PU1 / VEXT

4419500

Vx

4528000

LP / PU1 / VEXT 4419500

Vx

4528000

MP+ / PU1 / VEXT

4419500

MP / PU1 / VEXT 4528000

LP / PU1 / VEXT 4419500

Vx

4528000

TOC-300

Y -2310000 -2240000 -2180000 -2095000 -1995000 -1937500 -1910000
-1780000 -1715000 -1660000 -1605000 -1545000 -1485000 -1425000 -1365000 -1305000 -1245000 -1190000 -1135000 -1065000 -975000
-885000 -785000 -685000 -610000
-535000 -460000
-385000 -330000 -265000 -190000
-100000 -30000 25000

Comment GPIO GPIO GPIO Must be bonded to VDD Must be bonded to VSS GPIO Must be bonded to VSS (Double Pad / Center of Elephant Pad Opening) Must be bonded to VDD GPIO Must be bonded to VSS GPIO GPIO GPIO GPIO GPIO GPIO GPIO Must be bonded to VEXT GPIO GPIO GPIO
GPIO Must be bonded to VDD Must be bonded to VSS GPIO
Must be bonded to VSS GPIO
Must be bonded to VSS GPIO Must be bonded to VEXT GPIO
GPIO GPIO Must be bonded to VSS
V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC29x Bare Die Pad Definition

Table 2-74 TC29x Bare Die Pad List (cont'd)

Number Pad Name

Pad Type

162

P00.15

MP+ / PU1 / VEXT

163

P00.1 (VADC7.5 D

/ DS5NA)

164

P00.2 (VADC7.4 D

/ DS5PA)

165

P00.3 (VADC7.3) D

166

VSS

Vx

167

P00.4 (VADC7.2) D

168

P00.5 (VADC7.1) D

169

P00.6 (VADC7.0) D

170

VEXT

Vx

171

P00.7 (VADC6.5 D

/ DS4NA)

172

P00.8 (VADC6.4 D

/ DS4PA)

173

P00.9 (VADC6.3) D

174

P00.10

D

(VADC6.2)

175

P00.11

D

(VADC6.1)

176

VSS

Vx

177

P00.12

D

(VADC6.0)

178

VDD

Vx

179

VSS

Vx

180

VEXT

Vx

181

VSS

Vx

182

VDD

Vx

183

VAREF4

Vx

X 4419500
4419500
4528000
4419500 4528000 4419500 4528000 4419500 4528000 4419500
4528000
4419500 4528000
4419500
4528000 4419500
4528000 4528000 4419500 4528000 4528000 4528000

184

VAGND4

Vx

4419500

185

VDDM

Vx

186

AN47 (VADC5.7 / S

DS3ND)

187

AN46 (VADC5.6 / S

DS3PD)

188

AN45 (VADC5.5 / S

DS3NC)

4528000 4419500
4528000
4419500

Y 100000
250000
310000
370000 425000 480000 540000 600000 655000 710000
770000
830000 890000
950000
1005000 1060000
1115000 1215000 1265000 1315000 1415000 1535000
1585000
1635000 1685000
1735000
1785000

Comment GPIO
Analog input
Analog input
Analog input Must be bonded to VSS Analog input Analog input Analog input Must be bonded to VEXT Analog input
Analog input
Analog input Analog input
Analog input
Must be bonded to VSS Analog input
Must be bonded to VDD Must be bonded to VSS Must be bonded to VEXT Must be bonded to VSS Must be bonded to VDD Positive Analog Reference Voltage 4 Negative Analog Reference Voltage 4 Must be bonded to VEXT Analog input
Analog input
Analog input

Data Sheet

TOC-301

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC29x Bare Die Pad Definition

Table 2-74 TC29x Bare Die Pad List (cont'd)

Number Pad Name

Pad Type

189

AN44 (VADC5.4 / S

DS3PC)

190

AN43 (VADC5.3) D

X 4528000
4419500

191

AN42 (VADC5.2) D

192

AN41 (VADC5.1) D

193

AN40 (VADC5.0) D

194

AN38 (VADC4.6 / S

DS3PB), P40.8

(SENT8A)

195

AN39 (VADC4.7 / S

DS3NB), P40.9

(SENT9A)

196

AN36 (VADC4.4 / S

DS3PA), P40.6

(SENT6A)

197

AN37 (VADC4.5 / S

DS3NA), P40.7

(SENT7A)

198

AN34 (VADC4.2) D

199

AN35 (VADC4.3) D

4528000 4419500 4528000 4528000
4419500
4528000
4419500
4528000 4419500

200

AN32

S

(VADC4.0),

P40.4 (SENT4A)

201

AN33

S

(VADC4.1),

P40.5 (SENT5A)

202

AN70

S

(VADC10.6 /

DS9PA), P40.13

(SENT13A)

203

AN71

S

(VADC10.7 /

DS9NA), P40.14

(SENT14A)

204

AN68

S

(VADC10.4 /

DS8PA), P40.11

(SENT11A)

205

AN69

S

(VADC10.5 /

DS8NA), P40.12

(SENT12A)

4528000 4419500 4528000 4419500 4528000 4419500

Y 1835000 1885000 1935000 1985000 2035000 2135000
2085000
2235000
2185000
2335000 2285000 2435000
2385000
2535000
2485000
2635000
2585000

Comment Analog input Analog input (with pull down diagnostics) Analog input Analog input Analog input Analog input, GPI (SENT)
Analog input, GPI (SENT)
Analog input, GPI (SENT)
Analog input, GPI (SENT)
Analog input Analog input (with pull down diagnostics) Analog input, GPI (SENT)
Analog input, GPI (SENT)
Analog input, GPI (SENT)
Analog input, GPI (SENT)
Analog input, GPI (SENT)
Analog input, GPI (SENT)

Data Sheet

TOC-302

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC29x Bare Die Pad Definition

Table 2-74 TC29x Bare Die Pad List (cont'd)

Number Pad Name

Pad Type

206

VDDM

Vx

207

AN67

S

(VADC10.3 /

DS8NB), P40.10

(SENT10A)

208

VSSM

Vx

209

VSS

Vx

210

AN65

D

(VADC10.1)

211

AN66

D

(VADC10.2 /

DS8PB

212

AN63 (VADC9.7 / D

DS7NB)

213

AN64

D

(VADC10.0)

214

AN61 (VADC9.5 / D

DS7NA)

215

AN62 (VADC9.6 / D

DS7PB)

216

AN59 (VADC9.3) D

217

AN60 (VADC9.4 / D

DS7PA)

218

AN57 (VADC9.1) D

219

AN58 (VADC9.2) D

220

VAREF3

Vx

X 4528000 4419500
4528000 4419500 4528000 4419500
4528000 4419500 4528000 4419500 4528000 4419500 4528000 4419500 4528000

221

AN56 (VADC9.0) D

222

VAGND3

Vx

4419500 4528000

223

VAREF2

Vx

4419500

224

AN55 (VADC8.7 / D

DS6NB)

225

VAGND2

Vx

4528000 4419500

226

AN53 (VADC8.5 / D

DS6NA)

227

AN54 (VADC8.6 / D

DS6PB)

228

AN51 (VADC8.3) D

4528000 4419500 4528000

Y 2735000 2685000
2835000 2785000 2935000 2885000
3035000 2985000 3135000 3085000 3235000 3185000 3335000 3285000 3435000 3385000 3535000 3485000 3635000 3585000 3735000 3685000 3835000

Comment Must be bonded to VEXT Analog input, GPI (SENT)
Must be bonded to VSS Must be bonded to VSS Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input Analog input
Analog input Analog input Positive Analog Reference Voltage 3 Analog input Negative Analog Reference Voltage 3 Positive Analog Reference Voltage 2 Analog input
Negative Analog Reference Voltage 2 Analog input
Analog input
Analog input

Data Sheet

TOC-303

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC29x Bare Die Pad Definition

Table 2-74 TC29x Bare Die Pad List (cont'd)

Number Pad Name

Pad Type

229

AN52 (VADC8.4 / D

DS6PA)

230

AN49 (VADC8.1) D

231

AN50 (VADC8.2) D

232

VDDM

Vx

233

AN48 (VADC8.0) D

234

AN31 (VADC3.7) D

235

VSSM

Vx

236

AN29 (VADC3.5) D

237

AN30 (VADC3.6) D

238

AN27

S

(VADC3.3),

P40.3 (SENT3A)

239

AN28 (VADC3.4) D

240

AN25 (VADC3.1 / S

DS2NB), P40.2

(SENT1A)

241

AN26

S

(VADC3.2),

P40.2 (SENT2A)

242

AN23 (VADC2.7) D

243

AN24 (VADC3.0 / S

DS2PB), P40.0

(SENT0A)

244

AN21 (VADC2.5 / D

DS2NA)

245

AN22 (VADC2.6) D

246

AN19 (VADC2.3) D

X 4419500
4528000 4419500 4528000 4419500 4278000 4328000 4178000 4228000 4078000
4128000 3978000
4028000
3878000 3928000
3778000
3828000 3678000

247

AN20 (VADC2.4 / D

DS2PA)

248

AN17 (VADC2.1) D

249

AN18 (VADC2.2) D

250

AN15 (VADC1.7) D

251

AN16 (VADC2.0) D

252

VAGND0

Vx

3728000
3578000 3628000 3478000 3528000 3378000

253

VAGND1

Vx

3428000

254

VAREF0

Vx

3278000

Y 3785000
3960000 3897400 4085000 4022600 4186500 4295000 4186500 4295000 4186500
4295000 4186500
4295000
4186500 4295000
4186500
4295000 4186500
4295000
4186500 4295000 4186500 4295000 4186500
4295000
4186500

Comment Analog input
Analog input Analog input Must be bonded to VEXT Analog input Analog input Must be bonded to VSS Analog input Analog input Analog input (with pull down diagnostics), GPI (SENT) Analog input Analog input, GPI (SENT)
Analog input, GPI (SENT)
Analog input Analog input, GPI (SENT)
Analog input
Analog input Analog input (with pull down diagnostics) Analog input
Analog input Analog input Analog input Analog input Negative Analog Reference Voltage 0 Negative Analog Reference Voltage 1 Positive Analog Reference Voltage 0

Data Sheet

TOC-304

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC29x Bare Die Pad Definition

Table 2-74 TC29x Bare Die Pad List (cont'd)

Number Pad Name

Pad Type

255

VAREF1

Vx

X 3328000

256

VSS

Vx

257

VSSM

Vx

258

AN14 (VADC1.6) D

259

VDDM

Vx

260

AN12 (VADC1.4) D

261

AN13 (VADC1.5) D

262

AN10 (VADC1.2) D

263

AN11 (VADC1.3) D

3178000 3228000 3078000 3128000 2978000 3028000 2878000 2928000

264

AN8 (VADC1.0) D

265

AN9 (VADC1.1) D

266

AN6 (VADC0.6) D

267

AN7 (VADC0.7) D

2778000 2828000 2678000 2728000

268

AN4 (VADC0.4) D

2578000

269

AN5 (VADC0.5) D

2628000

270

AN2 (VADC0.2 / D

DS0PA)

2478000

271

AN3 (VADC0.3 / D

DS0NA)

2528000

272

AN1 (VADC0.1 / D

DS1NA)

2378000

273

VSSM

Vx

2428000

274

AN0 (VADC0.0 / D

DS1PA)

2278000

275

VDDM

Vx

2328000

276

EVR_OFF

Vx

2158000

277

P33.0

LP / PU1 / VEXT 2103000

278

VSS

Vx

2048000

279

P33.1

LP / PU1 / VEXT 1993000

280

P34.1

LP / PU1 / VEXT 1933000

281

P33.2

LP / PU1 / VEXT 1873000

282

VSS

Vx

1778000

283

VDD

Vx

1678000

284

P33.3

LP / PU1 / VEXT 1583000

285

VEXT

Vx

1509000

286

VEXT

Vx

1440000

287

P34.2

LP / PU1 / VEXT 1385000

Y 4295000
4186500 4295000 4186500 4295000 4186500 4295000 4186500 4295000
4186500 4295000 4186500 4295000
4186500 4295000 4186500
4295000
4186500
4295000 4186500
4295000 4295000 4186500 4295000 4186500 4295000 4186500 4295000 4295000 4186500 4295000 4186500 4295000

Comment Positive Analog Reference Voltage 1 Must be bonded to VSS Must be bonded to VSS Analog input Must be bonded to VEXT Analog input Analog input Analog input Analog input (with pull down diagnostics) Analog input Analog input Analog input Analog input (with pull down diagnostics) Analog input Analog input Analog input
Analog input
Analog input
Must be bonded to VSS Analog input
Must be bonded to VEXT Must be bonded to VSS GPIO Must be bonded to VSS GPIO GPIO GPIO Must be bonded to VSS Must be bonded to VDD GPIO Must be bonded to VEXT Must be bonded to VEXT GPIO

Data Sheet

TOC-305

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC29x Bare Die Pad Definition

Table 2-74 TC29x Bare Die Pad List (cont'd)

Number Pad Name

Pad Type

X

288

P33.4

LP / PU1 / VEXT 1325000

289

P34.3

LP / PU1 / VEXT 1265000

290

P33.5

LP / PU1 / VEXT 1205000

291

P34.4

LP / PU1 / VEXT 1145000

292

P33.6

LP / PU1 / VEXT 1085000

293

P34.5

LP / PU1 / VEXT 1015000

294

P33.7

LP / PU1 / VEXT 955000

295

P33.8

MP / HighZ / VEXT

885000

296

P33.9

LP / PU1 / VEXT 815000

297

VSS

Vx

760000

298

P33.10

MP / PU1 / VEXT 695000

299

P33.14

LP / PU1 / VEXT 625000

300

P33.11

MP / PU1 / VEXT 555000

301

P33.15

LP / PU1 / VEXT 485000

302

P33.12

MP / PU1 / VEXT 415000

303

P32.5

LP / PU1 / VEXT 345000

304

P33.13

MP / PU1 / VEXT 275000

305

P32.6

LP / PU1 / VEXT 205000

306

VGATE3P (LDO) VGATE3P

150000

307

VEXT

Vx

96000

308

P32.0

LP / EVR13 SMPS -> PD, GPIO -> PU1 / VEXT

37000

309

VGATE1N

VGATE1N

-18000

(SMPS)

310

VGATE1P

VGATE1P

-68000

(SMPS)

311

VGATE1P (LDO) VGATE1P

-118000

312

P32.2

LP / PU1 / VEXT -173000

313

VSS

Vx

-268000

314

VDD

Vx

-368000

315

P32.3

LP / PU1 / VEXT -463000

316

P32.7

LP / PU1 / VEXT -523000

Y 4186500 4295000 4186500 4295000 4186500 4295000 4186500 4295000
4186500 4295000 4186500 4295000 4186500 4295000 4186500 4295000 4186500 4295000 4186500 4295000 4186500
4295000
4186500
4295000 4186500 4295000 4295000 4186500 4295000

Comment GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO
GPIO Must be bonded to VSS GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO Must be bonded to VSS Must be bonded to VEXT GPIO
Must be bonded to VSS if EVR13 SMPS is not used. Must be bonded to NMOS gate if EVR13 SMPS is used. Must be bonded to VEXT if EVR13 SMPS is not used. Must be bonded to PMOS gate if EVR13 SMPS is used. VGATE1P (LDO) GPIO Must be bonded to VSS Must be bonded to VDD GPIO GPIO

Data Sheet

TOC-306

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC29x Bare Die Pad Definition

Table 2-74 TC29x Bare Die Pad List (cont'd)

Number Pad Name

Pad Type

317

P32.4

MP+ / PU1 / VEXT

318

VSS

Vx

319

P31.0

MP / PU1 / VFLEXE

320

P31.1

MP / PU1 / VFLEXE

321

P31.2

MP / PU1 / VFLEXE

322

P31.3

MP / PU1 / VFLEXE

323

VSS

Vx

324

P31.4

MP / PU1 / VFLEXE

325

P31.5

MP / PU1 / VFLEXE

326

P31.6

MP / PU1 / VFLEXE

327

P31.7

MP / PU1 / VFLEXE

328

P31.8

MP / PU1 / VFLEXE

329

VFLEXE

Vx

X -603000 -678000 -823000 -903000 -983000 -1063000 -1128000 -1193000 -1273000 -1353000 -1433000 -1513000 -1578000

330

P31.9

331

P31.10

332

P31.14

333

P31.15

334

P31.11

335

VSS

336

VDD

337

P31.12

338

VSS

339

P31.13

MP / PU1 / VFLEXE
MP / PU1 / VFLEXE
MP / PU1 / VFLEXE
MP / PU1 / VFLEXE
MP / PU1 / VFLEXE
Vx
Vx
MP / PU1 / VFLEXE
Vx
MP / PU1 / VFLEXE

-1643000
-1723000
-1803000
-1883000
-1963000
-2068000 -2168000 -2273000
-2338000 -2403000

Y 4186500 4295000 4295000 4186500 4295000 4186500 4295000 4186500 4295000 4186500 4295000 4186500 4295000 4186500 4295000 4186500 4295000 4186500 4295000 4295000 4186500 4295000 4186500

Comment GPIO
Must be bonded to VSS GPIO
GPIO
GPIO
GPIO
Must be bonded to VSS GPIO
GPIO
GPIO
GPIO
GPIO
Must be bonded to VEXT or VDDP3 GPIO
GPIO
GPIO
GPIO
GPIO
Must be bonded to VSS Must be bonded to VDD GPIO
Must be bonded to VSS GPIO

Data Sheet

TOC-307

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC29x Bare Die Pad Definition

Table 2-74 TC29x Bare Die Pad List (cont'd)

Number Pad Name

Pad Type

340

P30.0

MP / PU1 / VFLEXE

341

P30.1

MP / PU1 / VFLEXE

342

P30.2

MP / PU1 / VFLEXE

343

VFLEXE

Vx

X -2483000 -2563000 -2643000 -2788000

344

P30.3

MP / PU1 / VFLEXE

-2723000

345

VSS

Vx

-2918000

346

P30.4

MP / PU1 / VFLEXE

-2853000

347

P30.5

MP / PU1 / VFLEXE

-2983000

348

P30.6

MP / PU1 / VFLEXE

-3063000

349

P30.8

MP / PU1 / VFLEXE

-3223000

350

P30.7

MP / PU1 / VFLEXE

-3143000

351

VFLEXE

Vx

-3368000

352

P30.9

353

P30.11

354

P30.10

355

P30.15

356

P30.12

357

VSS

358

P30.13

359

P26.0

360

P30.14

361

VSS

MP / PU1 / VFLEXE
MP / PU1 / VFLEXE
MP / PU1 / VFLEXE
MP / PU1 / VFLEXE
MP / PU1 / VFLEXE
Vx
MP / PU1 / VFLEXE
LP / PU1 / VFLEXE
MP / PU1 / VFLEXE
Vx

-3303000 -3513000 -3433000 -3673000 -3593000 -3818000 -3753000 -3953000 -3883000 -4098000

Y 4295000 4186500 4295000 4295000 4186500 4295000 4186500 4186500 4295000 4295000 4186500 4295000 4186500 4295000 4186500 4295000 4186500 4295000 4186500 4295000 4186500 4295000

Comment GPIO
GPIO
GPIO
Must be bonded to VEXT or VDDP3 GPIO
Must be bonded to VSS GPIO
GPIO
GPIO
GPIO
GPIO
Must be bonded to VEXT or VDDP3 GPIO
GPIO
GPIO
GPIO
GPIO
Must be bonded to VSS GPIO
GPIO
GPIO
Must be bonded to VSS (Double Pad / Center of Elephant Pad Opening)

Data Sheet

TOC-308

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC29x Bare Die Pad Definition

Table 2-74 TC29x Bare Die Pad List (cont'd)

Number Pad Name

Pad Type

X

362

P25.0

A2 / PU1 / VEBU -4078000

363

P25.2

A2 / PU1 / VEBU -4228000

364

P25.1

A2 / PU1 / VEBU -4178000

365

P25.4

A2 / PU1 / VEBU -4338000

366

P25.3

A2 / PU1 / VEBU -4288000

367

P25.5

A2 / PU1 / VEBU -4419500

368

P25.7

A2 / PU1 / VEBU -4419500

369

VEBU

Vx

-4528000

370

P25.8

371

VSS

372

P25.10

373

P25.9

374

VSS

375

P25.11

376

VDD

377

P25.13

378

P25.12

379

P25.14

380

VEBU

A2 / PU1 / VEBU -4419500

Vx

-4528000

A2 / PU1 / VEBU -4419500

A2 / PU1 / VEBU -4528000

Vx

-4528000

A2 / PU1 / VEBU -4419500

Vx

-4528000

A2 / PU1 / VEBU -4419500

A2 / PU1 / VEBU -4528000

A2 / PU1 / VEBU -4419500

Vx

-4528000

381

P25.6

382

P25.15

383

P24.1

384

P24.0

385

P24.2

386

VSS

387

P24.4

388

P24.3

389

P24.6

390

P24.5

391

VSS

392

P24.7

393

VDD

394

P24.8

395

VEBU

A2 / PU1 / VEBU -4419500

A2 / PU1 / VEBU -4528000

A2 / PU1 / VEBU -4419500

A2 / PU1 / VEBU -4528000

A2 / PU1 / VEBU -4419500

Vx

-4528000

A2 / PU1 / VEBU -4419500

A2 / PU1 / VEBU -4528000

A2 / PU1 / VEBU -4419500

A2 / PU1 / VEBU -4528000

Vx

-4528000

A2 / PU1 / VEBU -4419500

Vx

-4528000

A2 / PU1 / VEBU -4419500

Vx

-4528000

396

P24.10

397

P24.9

A2 / PU1 / VEBU -4419500 A2 / PU1 / VEBU -4528000

Y 4186500 4295000 4186500 4295000 4186500 4105000 4005000 4055000
3905000 3955000 3805000 3855000 3755000 3605000 3655000 3505000 3555000 3405000 3455000
3305000 3355000 3205000 3255000 3105000 3155000 3005000 3055000 2905000 2955000 2845000 2685000 2745000 2585000 2635000
2485000 2535000

Comment GPIO GPIO GPIO GPIO GPIO GPIO GPIO Must be bonded to VEXT or VDDP3 GPIO Must be bonded to VSS GPIO GPIO Must be bonded to VSS GPIO Must be bonded to VDD GPIO GPIO GPIO Must be bonded to VEXT or VDDP3 GPIO GPIO GPIO GPIO GPIO Must be bonded to VSS GPIO GPIO GPIO GPIO Must be bonded to VSS GPIO Must be bonded to VDD GPIO Must be bonded to VEXT or VDDP3 GPIO GPIO

Data Sheet

TOC-309

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC29x Bare Die Pad Definition

Table 2-74 TC29x Bare Die Pad List (cont'd)

Number Pad Name

Pad Type

X

398

P24.12

A2 / PU1 / VEBU -4419500

399

P24.11

A2 / PU1 / VEBU -4528000

400

P24.13

A2 / PU1 / VEBU -4419500

401

VSS

Vx

-4528000

402

P24.15

A2 / PU1 / VEBU -4419500

403

P24.14

A2 / PU1 / VEBU -4528000

404

P23.5

MP+ / PU1 / VEXT

-4419500

405

VSS

Vx

-4528000

406

P23.0

LP / PU1 / VEXT -4419500

407

VEXT

Vx

-4528000

408

P23.1

MP+ / PU1 / VEXT

-4419500

409

VDD

Vx

-4528000

410

VSS

Vx

-4528000

411

P23.2

LP / PU1 / VEXT -4419500

412

P23.6

LP / PU1 / VEXT -4528000

413

P23.3

LP / PU1 / VEXT -4419500

414

P23.7

LP / PU1 / VEXT -4528000

415

P23.4

MP+ / PU1 / VEXT

-4419500

416

VSS

Vx

-4528000

417

P22.0

LVDSM_N / PU1 -4419500 / VEXT

418

P22.1

LVDSM_P / PU1 -4419500 / VEXT

419

VSS

Vx

-4528000

420

VDD

Vx

-4528000

421

P22.2

LVDSM_N / PU1 -4419500 / VEXT

422

P22.3

LVDSM_P / PU1 -4419500 / VEXT

423

VEXT

Vx

-4528000

424

P22.4

LP / PU1 / VEXT -4419500

425

VSS

Vx

-4528000

426

VDD

Vx

-4528000

427

P22.5

LP / PU1 / VEXT -4419500

428

P22.7

LP / PU1 / VEXT -4528000

429

P22.6

LP / PU1 / VEXT -4419500

430

VSS

Vx

-4528000

Y 2385000 2435000 2285000 2335000 2185000 2235000 2040000
1965000 1910000 1855000 1780000
1695000 1595000 1510000 1450000 1390000 1330000 1250000
1175000 1100000
770000
688000 588000 513000
183000
108000 53000 -2000 -102000 -157000 -217000 -277000 -332000

Comment GPIO GPIO GPIO Must be bonded to VSS GPIO GPIO GPIO
Must be bonded to VSS GPIO Must be bonded to VEXT GPIO
Must be bonded to VDD Must be bonded to VSS GPIO GPIO GPIO GPIO GPIO
Must be bonded to VSS GPIO
GPIO
Must be bonded to VSS Must be bonded to VDD GPIO
GPIO
Must be bonded to VEXT GPIO Must be bonded to VSS Must be bonded to VDD GPIO GPIO GPIO Must be bonded to VSS

Data Sheet

TOC-310

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC29x Bare Die Pad Definition

Table 2-74 TC29x Bare Die Pad List (cont'd)

Number Pad Name

Pad Type

X

431

P22.8

LP / PU1 / VEXT -4419500

432

P22.9

LP / PU1 / VEXT -4528000

433

P22.10

LP / PU1 / VEXT -4419500

434

P22.11

LP / PU1 / VEXT -4528000

435

VDDOSC

Vx

-4528000

436

VSSOSC

Vx

-4528000

437

XTAL1

XTAL1

-4419500

438

XTAL2

XTAL2

-4419500

439

VSSOSC

Vx

-4528000

440

VDDOSC3

Vx

-4419500

441

VDDP3

Vx

-4528000

442

P21.0

LVDSH_N / PU1 -4419500 / VDDP3

443

P21.1

LVDSH_P / PU1 -4419500 / VDDP3

444

VSSP

Vx

-4528000

445

P21.2

LVDSH_N / PU1 -4419500 / VDDP3

446

P21.3

LVDSH_P / PU1 -4419500 / VDDP3

447

VDDP3

Vx

-4528000

448

P21.4

LVDSH_N / PU1 -4419500 / VDDP3

449

VSS

Vx

-4528000

450

P21.5

LVDSH_P / PU1 -4419500 / VDDP3

451

VDD

Vx

-4528000

452

VSSP

Vx

-4528000

453

P21.6

A2 / PU / VDDP3 -4419500

454

VDDP3

Vx

-4528000

455

TMS /DAP1

A2 / PD / VDDP3 -4419500

Y -387000 -447000 -507000 -567000 -702000 -802000 -909500
-1009500
-1117000 -1167000 -1257000 -1362500
-1462500
-1525000 -1587500
-1687500
-1750000 -1824500
-2020000
-1975500
-2150000 -2260000 -2210000 -2360000 -2310000

Comment GPIO GPIO GPIO GPIO Must be bonded to VSS Must be bonded to VSS Main Oscillator/PLL/Clock Generator Input. Must be bonded to external quartz or resonator. Main Oscillator/PLL/Clock Generator Input. Must be bonded to external quartz or resonator. Must be bonded to VSS Must be bonded to VDDP3 Must be bonded to VDDP3 GPIO
GPIO
Must be bonded to VSS GPIO
GPIO
Must be bonded to VDDP3 GPIO
Must be bonded to VSS (Double Pad / Center of Elephant Pad Opening) GPIO
Must be bonded to VDD Must be bonded to VSS GPIO, TDI Must be bonded to VDDP3 JTAG Module State Machine Control Input / Device Access Port Line 1

Data Sheet

TOC-311

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC29x Bare Die Pad Definition

Table 2-74 TC29x Bare Die Pad List (cont'd)

Number Pad Name

Pad Type

X

456

TCK /DAP0

A2 / PD / VDDP3 -4528000

457

P21.7

A2 / PU / VDDP3 -4419500

458

TRST (N)

A2 / PD / VDDP3 -4419500

459

Reserved

Vx

-4528000

460

VEXT

Vx

-4528000

461

P20.0

MP / PU1 / VEXT -4419500

462

VSS

Vx

-4528000

463

P20.1

LP / PU1 / VEXT -4419500

464

PORST (N)

PORST / PD / -4528000

VEXT

465

P20.2

LP / PU1 / VEXT -4419500

466

ESR1 (N)

MP / PU1 / VEXT -4528000

/EVRWUP

467

P20.3

LP / PU1 / VEXT -4419500

468

ESR0 (N)

MP / OD

-4528000

/EVRWUP

469

P20.7

470

VEXT

471

P20.8

472

P20.6

473

P20.10

474

P20.9

475

P20.11

476

VSS

477

P20.12

478

P20.14

479

P20.13

480

P15.0

LP / PU1 / VEXT -4419500

Vx

-4528000

MP / PU1 / VEXT -4419500

LP / PU1 / VEXT -4528000

MP / PU1 / VEXT -4419500

LP / PU1 / VEXT -4528000

MP / PU1 / VEXT -4419500

Vx

-4528000

MP / PU1 / VEXT -4419500

MP / PU1 / VEXT -4528000

MP / PU1 / VEXT -4419500

LP / PU1 / VEXT -4263000

Legend: Column "Number": Running number of pads in the pad frame

Data Sheet

TOC-312

Y -2460000
-2410000 -2520000
-2650000 -2780000 -2715000 -2890000 -2835000 -3007500
-2940000
-3150000
-3080000 -3290000
-3220000 -3435000 -3370000 -3590000 -3520000 -3750000 -3680000 -3905000 -3820000 -4080000 -3990000 -4186500

Comment JTAG Module Clock Input / Device Access Port Line 0 GPIO, TDO JTAG Module Reset/Enable Input Must be bonded to VSS Must be bonded to VEXT GPIO Must be bonded to VSS GPIO Power On Reset Input. Additional strong PD in case of power fail. Testmode pin must be bonded External System Request Reset 1. Default NMI function. EVR Wakeup Pin. GPIO External System Request Reset 0. Default configuration during and after reset is open-drain driver. The driver drives low during power-on reset. EVR Wakeup Pin. GPIO Must be bonded to VEXT GPIO GPIO GPIO GPIO GPIO Must be bonded to VSS GPIO GPIO GPIO GPIO
V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC29x Bare Die Pad Definition
Column "Name": Symbolic name of the pad. The functions mapped on GPIO pads "Px.y" are described in the User's Manual chapter "General Purpose I/O Ports and Peripheral I/O LInes (Ports)" Column "Type": LP = Pad class LP (5V/3.3V, Class LP parameters for digital input / output and class D parameters for analog input function) MP = Pad class MP (5V/3.3V) MP+ = Pad class MP+ (5V/3.3V) MPR = Pad class MPR (5V/3.3V) A2 = Pad class A2 (3.3V) LVDSM = Pad class LVDSM (5V/3.3V) LVDSH = Pad class LVDSH (3.3V) S = Pad class S (Class S parameters for digital input and class D parameters for analog input function) D = Pad class D (VADC / DSADC) PU = with pull-up device connected during reset (PORST = 0) PU1 = with pull-up device connected during reset (PORST = 0)1) 2) 3) PD = with pull-down device connected during reset (PORST = 0) PD1 = with pull-down device connected during reset (PORST = 0)1) 2) 3) PX = Behavior depends on usage: PD in EVR13 SMPS Mode and PU1 in GPIO Mode OD = open drain during reset (PORST = 0) HighZ = tri-state during reset (PORST = 0) PORST = PORST input pad XTAL1 = XTAL1 input pad XTAL2 = XTAL2 input pad VGATE1P = VGATE1P VGATE3P = VGATE3P Vx = Supply NC = These pins are reserved for future extensions and shall not be connected externally NC1 = These pins are not connected on package level and will not be used for future extensions NCVDDPSB = This pin has a different functionality in an Production Device and an Emulation Device. For details pls. see Pin/Ball description of this pin. NCVDDSB = This pin has a different functionality in an Production Device and an Emulation Device. For details pls. see Pin/Ball description of this pin. Column "X" / "Y": Pad opening center coordinates
2.4.1 Pad Openings
Two different pad openings are used:

1) The default state of GPIOs (Px.y) during and after PORST active is controllled via HWCFG[6] (P14.4). HWCFG[6] has a weak internal pull-up active at start-up if the pin is left unconnected.See also User´s Manual, "Introduction Chapter", "General Purpose I/O Ports and Peripheral I/O Lines", Figure: "Default state of port pins during and after reset".
2) If HWCFG[6] is left unconnected or is externally pulled high, weak internal pull-ups are active at GPIOs (Px.y) pins during and after reset. Exceptions are P33.8 (HighZ), P40.x (default configuration during and after reset: analog inputs, port input funtion disabled), ESR0, P21.6 / P21.7 (port pins overlayed with JTAG functionality).
3) If HWCFG[6] is connected to ground, port pins are predominantly in HighZ during and after reset. Exceptions are P33.8 (HighZ), P40.x (default configuration during and after reset: analog inputs, port input funtion disabled), ESR0, P21.6 / P21.7 (port pins overlayed with JTAG functionality).

Data Sheet

TOC-313

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step
Package and Pinning DefinitionsTC29x Bare Die Pad Definition
· Standard Pad Opening is 70um x 75um where 70um is the width of the opening (width as seen from the die side) and 75um is the depth of the opening (from the die side into the silicon).
· Double Pad or Elephant Pad Opening is 130um x 75um where 130um is the width of the opening (width as seen from the die side) and 75um is the depth of the opening (from the die side into the silicon). Double Pads are used only for supply and can be identified by the words ´Double Pad´ or ´Elephant Pad´ in the Comment column.
2.4.2 Emergency Stop Function
The Emergency Stop function can be used to force GPIOs (General Purpose Inputs/Outputs) via an external input signal (EMGSTOPA or EMGSTOPB) into a defined state: · Input state and · PU or HighZ depending on HWCFG[6] level latched during Porst active Control of the Emergency Stop function: · The Emergency Stop function can be enabled/disabled in the SCU (see chapter "SCU", "Emergency Stop
Control") · The Emergency Stop input signal, EMGSTOPA (P33.8) / EMGSTOPB (P21.2) , can selected in the SCU (see
chapter "SCU", "Emergency Stop Control") · On port level, each GPIO can be enabled/disabled for the Emergency Stop function via the Px_ESR (Port x
Emergency Stop) registers in the port control logic (see chapter "General Purpose I/O Ports and Peripheral I/O Lines", "Emergency Stop Register"). The Emergency Stop function is available for all GPIO Ports with the following exceptions: · Not available for P20.2 (General Purpose Input/GPI only, overlayed with Testmode) · Not available for P40.x (analoge input ANx overlayed with GPI) · Not available for P32.0 EVR13 SMPS mode. · Not available for dedicated I/O without General Purpose Output function (e.g ESRx, TMS, TCK) The Emergency Stop function can be overruled on the following GPIO Ports: · P00.x and P02.x: Emergency Stop can be overruled by the 8-Bit Standby Controller (SBR), if implemented. Overruling can be disabled via the control registers P00_SCR / P02_SCR (see chapter "General Purpose I/O Ports and Peripheral I/O Lines", P00 / P01) · P00.x: Emergency Stop can be overruled by the VADC. Overruling can be disabled via the control register P00_SCR (see chapter "General Purpose I/O Ports and Peripheral I/O Lines", P00) · P14.0 and P14.1: Emergency Stop can be overruled in the DXCPL mode (DAP over can physical layer mode). No Overruling in the DXCM (Debug over can message) mode · P21.6: Emergency Stop can be overruled in JTAG mode if this pin is used as TDI · P21.7: Emergency Stop can be overruled in JTAG or Three Pin DAP mode · P20.0: Emergency Stop can be overruled in JTAG mode if this GPIO is used as TDI · P33.8: Emergency Stop can be overruled if this pin is used as safety output pin (SMUFSP)
2.4.3 Pull-Up/Pull-Down Reset Behavior of the Pins

Data Sheet

TOC-314

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Package and Pinning DefinitionsTC29x Bare Die Pad Definition

Table 2-75 List of Pull-Up/Pull-Down Reset Behavior of the Pins

Pins

PORST = 0

PORST = 1

all GPIOs

Pull-up if HWCFG[6] = 1 or High-Z if HWCFG[6] = 0

TDI, TESTMODE

Pull-up

PORST1)

Pull-down with IPORST relevant

Pull-down with IPDLI relevant

TRST, TCK, TMS

Pull-down

ESR0

The open-drain driver is used to drive low.2)

Pull-up3)

ESR1

Pull-up3)

TDO

Pull-up

High-Z/Pull-up4)

1) Pull-down with IPORST relevant is always activated when a primary supply monitor detects a violation. 2) Valid additionally after deactivation of PORST until the internal reset phase has finished. See the SCU chapter for details.

3) See the SCU_IOCR register description.

4) Depends on JTAG/DAP selection with TRST.

In case of leakage test (PORST = 0 and TESTMODE = 0), the pull-down of the TRST pin is switched off. In case of an user application (TESTMODE = 1), the pull-down of the TRST is always switched on.

Data Sheet

TOC-315

V 1.0 2017-03

3

Electrical Specification

TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationParameter Interpretation

3.1

Parameter Interpretation

The parameters listed in this section partly represent the characteristics of the TC290 / TC297 / TC298 / TC299 and partly its requirements on the system. To aid interpreting the parameters easily when evaluating them for a design, they are marked with an two-letter abbreviation in column "Symbol":

· CC Such parameters indicate Controller Characteristics which are a distinctive feature of the TC290 / TC297 / TC298 / TC299 and must be regarded for a system design.

· SR Such parameters indicate System Requirements which must provided by the microcontroller system in which the TC290 / TC297 / TC298 / TC299 designed in.

Data Sheet

3-316

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationAbsolute Maximum Ratings

3.2

Absolute Maximum Ratings

Stresses above the values listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the Operational Conditions of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability.

Table 3-1 Absolute Maximum Ratings

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ.

Max.

Storage Temperature

TST SR

-65

-

170

°C

upto 65h @ TJ =

150°C; upto 15h @ TJ

= 170°C

Voltage at VDD power supply VDD SR

-

-

pins with respect to VSS 1)

Voltage at VDDP3 and VDDFL3 VDDP3 SR -

-

power supply pins with respect

to VSS 1)

Voltage at VDDM, VEXT and

VDDM SR -

-

VFLEX power supply pins with

respect to VSS 1)

Voltage on any class A2 and VIN SR

-0.5

-

LVDSH input pin with respect

to VSS 1)2)

1.9

V

4.43

V

7.0

V

min(

V

VDDP3 +
0.6 , 4.23

)

Whatever is lower

Voltage on all other input pins VIN SR

-0.5

-

with respect to VSS 1)2)

Input current on any pin during IIN SR

-10

-

overload condition 3)

7.0

V

10

mA

Absolute maximum sum of all IIN SR

-100

-

input circuit currents during

overload condition 3)

100

mA

1) Valid for cumulated for up to 2.8h and pulse forms following a power supply switch on phase, where the rise and fall times are releated to the system capacities and coils.

2) Voltages below VINmin have no Impact to the device reliabiltiy as Long as the times and currents defined in section Pin Reliability in Overload for the affected pad(s) are not violated.

3) This parameter is an Absolute Maximum Rating. Exposure to Absolute Maximum Ratings for extended periods of time may damage the device.

Data Sheet

3-317

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationPin Reliability in Overload

3.3

Pin Reliability in Overload

When receiving signals from higher voltage devices, low-voltage devices experience overload currents and voltages that go beyond their own IO power supplies specification.

The following table defines overload conditions that will not cause any negative reliability impact if all the following conditions are met:

· full operation life-time (24500 h) is not exceeded

· Operating Conditions are met for

­ pad supply levels

­ temperature

If a pin current is out of the Operating Conditions but within the overload parameters, then the parameters functionality of this pin as stated in the Operating Conditions can no longer be guaranteed. Operation is still possible in most cases but with relaxed parameters.

Note: An overload condition on one or more pins does not require a reset.

Table 3-2 Overload Parameters

Parameter

Symbol

Input current on any digital pin IIN
during overload condition

Input current on LVDS pin during overload condition
Absolute maximum sum of all input circuit currents during overload condition
Input current on analog input pin during overload condition

IINLVDS IING
IINANA

Absolute sum of all ADC inputs IINSCA
during overload condition

Absolute maximum sum of all input circuit currents during overload condition

IINS

Signal voltage over/undershoot VOUS
at GPIOs

Inactive device pin current

IID

during overload condtion 2)

Sum of all inactive device pin IIDS
currents 2)

Min. -5 -15 1)
-3 -50
-3 -5 -20 -100
VSS - 2
-1 -100

Values Typ. -

Max. 5 15 1)

-

3

-

50

Unit Note / Test Condition
mA except LVDS pins mA except LVDS pins;
limited to max. 20 pulses with 1ms pulse length mA
mA

-

3

mA

-

5

mA limited to 60h over

lifetime

-

20

mA

-

100

mA

-

VEXT/FLEX V

limited to 60h over

+ 2

lifetime; Valid for LP,

MP, MP+, and MPR

pads

-

1

mA All power supply

voltages VDDx = 0

-

100

mA

Data Sheet

3-318

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationPin Reliability in Overload

Table 3-2 Overload Parameters (cont'd)

Parameter

Symbol

Min.

Overload coupling factor for digital inputs, negative 3)

KOVDN CC -

Values Typ. -

Max. 4*10-3

Unit

-

2*10-4

-

Data Sheet

-

-

1*10-2

-

-

6*10-4

-

-

1.7*10-3

-

-

2*10-2

-

-

1.5*10-2

-

-

0.3

-

-

0.93

3-319

Note / Test Condition
Overload injected on GPIO non LVDS pad and affecting neighbor A2 pads of P24.x and
P25.x; -2mA < IIN <
0mA
Overload injected on GPIO non LVDS pad and affecting neighbor LP and A2 (exept P24.x and P25.x)
pads; -2mA < IIN <
0mA
Overload injected on GPIO non LVDS pad and affecting neighbor LP and A2 pads (exept P25.2 and P25.4); -
5mA < IIN < -2mA
Overload injected on GPIO non LVDS pad and affecting neighbor LP and A2 pads; -2mA
< IIN < 0mA
Overload injected on GPIO non LVDS pad and affecting neighbor MP, MP+, and MPR
pads; -2mA < IIN <
0mA
Overload injected on GPIO non LVDS pad and affecting neighbor MP, MP+, and MPR
pads; -5mA < IIN < -
2mA
Overload injected on GPIO non LVDS pad and affecting neighbor pads P25.2 and P25.4;
-5mA < IIN < -2mA
Overload injected on LVDS pad and affecting neighbor LVDS pads
coupling between pads 21.0, 21.1,21.2 and 21.3 V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationPin Reliability in Overload

Table 3-2 Overload Parameters (cont'd)

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ.

Max.

Overload coupling factor for KOVDP CC -

-

1*10-5

digital inputs, positive 3)

Overload injected on GPIO non LVDS pad and affecting neighbor GPIO non LVDS pads

-

-

1.6*10-4

-

-

1*10-4

Overload injected on GPIO pad and affecting neighbor P32.0 pad
Overload injected on GPIO pad and affecting neighbor P32.4 and P33.12 pad

-

-

5*10-4

Overload injected on LVDS pad and affecting neighbor LVDS pads

Overload coupling factor for KOVAN CC -

-

6*10-4 4)

analog inputs, negative

Analog Inputs overlaid with class LP pads or

pull down diagnostics;

-

-

1*10-2

-1mA < IIN < 0mA
Analog Inputs overlaid

with class LP pads or

pull down diagnostics;

-

-

1*10-4

Overload coupling factor for KOVAP CC -

-

1*10-5

analog inputs, positive

-5mA < IIN < -1mA else; -5mA < IIN < 0mA 5mA < IIN < 0mA

1) Reduced VADC / DSADC result accuracy and / or GPIO input levels (VIL and VIH) can differ from specified parameters. 2) Limitations for time and supply levels specified in this section are not valid for this parameter.

3) Overload is measured as increase of pad leakage caused by injection on neighbor pad.

4) For analogue inputs overlaid with DSADC function the VCM holdbuffer shall be enabled, in case DSADCs are enabled.

Note: DSADC input pins count as analog pins as they are overlaid with VADC pins.

Table 3-3 PN-Junction Characteristics for positive Overload

Pad Type F / A2 LP / MP / MP+ LVDSM LVDSH D

IIN = 3 mA UIN = VDDP3 + 0.5 V UIN = VEXT / FLEX + 0.75 V UIN = VEXT + 0.75 V UIN = VDDP3 + 0.5 V UIN = VDDM + 0.75 V

IIN = 5 mA UIN = VDDP3 + 0.6 V UIN = VEXT / FLEX + 0.8 V
-

Data Sheet

3-320

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationPin Reliability in Overload

Table 3-4 PN-Junction Characteristics for negative Overload

Pad Type F / A2 LP / MP / MP+ LVDSM LVDSH D

IIN = -3 mA UIN = VSS - 0.5 V UIN = VSS - 0.75 V UIN = VSS - 0.75 V UIN = VSS - 0.5 V UIN = VSS - 0.75 V

IIN = -5 mA UIN = VSS - 0.6 V UIN = VSS - 0.8 V
-

Data Sheet

3-321

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationOperating Conditions

3.4

Operating Conditions

The following operating conditions must not be exceeded in order to ensure correct operation and reliability of the TC290 / TC297 / TC298 / TC299. All parameters specified in the following tables refer to these operating conditions, unless otherwise noticed.

Digital supply voltages applied to the TC290 / TC297 / TC298 / TC299 must be static regulated voltages.

All parameters specified in the following tables refer to these operating conditions (see table below), unless otherwise noticed in the Note / Test Condition column.

Table 3-5 Operating Conditions

Parameter

Symbol

Min.

SRI frequency

fSRI SR

-

-

Max System Frequency

fMAX SR

-

-

CPU0 Frequency

fCPU0 SR

-

-

CPU1 Frequency

fCPU1 SR

-

-

CPU2 Frequency

fCPU2 SR

-

-

PLL output frequency PLL_ERAY output frequency SPB frequency

fPLL SR

20

fPLLERAY SR 20

fSPB SR

-

-

ASCLIN fast frequency

fASCLINF SR -
-

ASCLIN slow frequency

fASCLINS SR -
-

Baud2 frequency

fBAUD2 SR -
-

Baud1 frequency

fBAUD1 SR -
-

FSI2 frequency

fFSI2 SR

-

-

FSI frequency

fFSI SR

-

-

GTM frequency

fGTM SR

-

-

EBU frequency

fEBU SR

-

-

Values Typ. -

Max. 270 300 1) 270 300 1) 270 300 1) 270 300 1) 270 300 1) 300 400 90 100 1) 270 300 1) 90 100 1) 270 300 1) 90 100 1) 270 300 1) 90 100 1) 90 100 1) 180 200

Unit Note / Test Condition

MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz

1.17V < VDD < 1.43V 1.235V < VDD < 1.43V 1.17V < VDD < 1.43V 1.235V < VDD < 1.43V 1.17V < VDD < 1.43V 1.235V < VDD < 1.43V 1.17V < VDD < 1.43V 1.235V < VDD < 1.43V 1.17V < VDD < 1.43V 1.235V < VDD < 1.43V
1.17V < VDD < 1.43V 1.235V < VDD < 1.43V 1.17V < VDD < 1.43V 1.235V < VDD < 1.43V 1.17V < VDD < 1.43V 1.235V < VDD < 1.43V 1.17V < VDD < 1.43V 1.235V < VDD < 1.43V 1.17V < VDD < 1.43V 1.235V < VDD < 1.43V 1.17V < VDD < 1.43V 1.235V < VDD < 1.43V 1.17V < VDD < 1.43V 1.235V < VDD < 1.43V 1.17V < VDD < 1.43V 1.235V < VDD < 1.43V 1.17V < VDD < 1.43V 1.235V < VDD < 1.43V

Data Sheet

3-322

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Table 3-5 Operating Conditions (cont'd)

Parameter

Symbol

Min.

STM frequency

fSTM SR

-

-

ERAY frequency BBB frequency MultiCAN frequency Absolute sum of short circuit currents of the device

fERAY SR

-

fBBB SR

-

fCAN SR

-

ISC_D SR -

Ambient Temperature

TA SR

-40

-40

-40

Junction Temperature

TJ SR

-40

-40

Core Supply Voltage 2)

VDD SR

1.17

ADC analog supply voltage
Digital external supply voltage for LP, MP, MP+ and LVDSM pads and EVR 5)

VDDM SR VEXT SR

2.97 2.97
4.5

Digital supply voltage for Flex VFLEX SR
port

2.97 4.5

Digital supply voltage for LVDSH and A2 pads 6)

VDDP3 SR 2.97

Flash supply voltage 3.3V 2) VDDFL3 SR 2.97

Digital ground voltage

VSS SR

Analog ground voltage for VDDM VSSM CC

Voltage to ensure defined pad VDDPPA CC
states 8)

0 -0.1 0.72 1.4

Electrical SpecificationOperating Conditions

Values Typ. -

Max. 90 100 1) 80 150 100 100

Unit Note / Test Condition

MHz MHz MHz MHz MHz mA

1.17V < VDD < 1.43V 1.235V < VDD < 1.43V

-

125

°C

valid for all SAK

products

-

150

°C

valid for all SAL

products

-

170

°C

valid for all SAL

products without

package

-

150

°C

valid for all SAK

products

-

170

°C

valid for all SAL

products

1.3

1.43 3)

V

Only required if

externally supplied

5.0

5.5 4)

V

-

4.5

V

3.3V pad parameters

are valid

5.0

5.5 4)

V

5V pad parameters are

valid

-

4.5

V

3.3V pad parameters

are valid

5.0

5.5 4)

V

5V pad parameters are

valid

3.3

3.63 7)

V

3.3V pad parameters

are valid; only required

if externally supplied

3.3

3.63

V

Only required if

externally supplied

-

-

V

0

0.1

V

-

-

V

A2 and LVDSH

-

-

V

LP, MP, MP+, MPR

and LVDSM

Data Sheet

3-323

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationOperating Conditions

Table 3-5 Operating Conditions (cont'd)

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ.

Max.

Digital supply voltage for EBU VEBU SR 2.97

3.3

3.63

V

3.3V pad parameters

are valid; only required

if externally supplied

Digital external supply voltage VEVRSB SR 2.97

-

for EVR and during Standby

mode

5.5

V

Digital supply voltage for EBU VFLEXE SR 2.97

3.3

4.5

V

3.3V pad parameters

Flex port

are valid

4.5

5.0

5.5

V

5V pad parameters are

valid

1) VDD = 1.33V +- 7.5% (with increased nominal VDD) voltage by +2.5%. 2) No external inductive load permissible if EVR is used. All VDD pins shall be connected together externally on the PCB. 3) Voltage overshoot to 1.69V is permissible, provided the duration is less than 2h cumulated. Reduced ADC accuracy and
leakage is increased.

4) Voltage overshoot to 6.5V is permissible, provided the duration is less than 2h cumulated. Reduced ADC accuracy and leakage is increased.

5) All VEXT pins shall be connected together externally on the PCB. 6) All VDDP3 pins shall be connected together externally on the PCB. 7) Voltage overshoot to 4.29V is permissible, provided the duration is less than 2h cumulated. Reduced ADC accuracy and
leakage is increased.

8) This parameter is valid under the assumption the PORST signal is constantly at low level during the power-up/power-down of VDDP3.

Data Sheet

3-324

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical Specification5 V / 3.3 V switchable Pads

3.5

5 V / 3.3 V switchable Pads

Pad classes LP, MP and MP+ support both Automotive Level (AL) or TTL level (TTL) operation. Parameters are defined for AL operation and degrade in TTL operation.

Table 3-6 Standard_Pads

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ.

Max.

Pin capacitance (digital inputs/outputs)

CIO CC

-

6

10

pF

Spike filter always blocked

tSF1 CC

-

-

80

ns

PORST only

pulse duration

Spike filter pass-through pulse tSF2 CC

220

-

-

ns

PORST only

duration

PORST pad output current 1) IPORST CC 11

-

-

mA

VEXT = 3.0V; VPORST =

0.9V; TJ = 165°C

13

-

-

mA

VEXT = 4.5V; VPORST =

1.0V

1) Pull-down with IPORST relevant is always activated when a primary supply monitor detects a violation.

Table 3-7 Class LP 5V

Parameter

Symbol

Min.

Input frequency Input Hysteresis for LP pad 1)
Input Leakage current for LP pad

fIN SR

-

-

HYSLP CC IOZLP CC

0.09 *
VEXT/FLEX
0.075 *
VEXT/FLEX
-150

-350

Input leakage current for P32.0 IOZP320 CC -4900

Values Typ. -
-
-
-

Max. 75 150 -
-
150
350 4900

-9400 -

9400

Pull-up current for LP pad

-5800 -

-12000 -

IPUHLP CC |30|

-

|43|

-

-

-

5800 12000 |107|

Unit Note / Test Condition

MHz MHz V

Hysteresis active Hysteresis inactive AL

V

TTL

nA

(0.1*VEXT/FLEX) < VIN <

(0.9*VEXT/FLEX)

nA else

nA

(0.1*VEXT/FLEX) < VIN <

(0.9*VEXT/FLEX)

nA

(0.1*VEXT/FLEX) < VIN <

(0.9*VEXT/FLEX); for TJ >

150°C

nA else

nA

else; for TJ > 150°C

µA

VIHmin; AL

µA

VIHmin; TTL

µA

VILmax; AL and TTL

Data Sheet

3-325

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical Specification5 V / 3.3 V switchable Pads

Table 3-7 Class LP 5V (cont'd)

Parameter

Symbol

Pull-down current for LP pad IPDLLP CC

On-Resistance for LP pad, weak driver 2)
On-Resistance for LP pad, medium driver 2)
Rise / fall time for LP pad 3)

RDSONLPW
CC
RDSONLPM
CC
tLP CC

Input high voltage for LP pad VIHLP SR
Input low voltage for LP pad VILLP SR
Input low / high voltage for LP VILHLP CC
pad

Min. |46| |21| 200

Values Typ. 620

Max. |100| 1040

Unit
µA µA µA Ohm

50

155

260

Ohm

-

-

-

-

-

-

-

-

(0.73*VEX -
T/FLEX)0.25

2.03 4)

-

-

-

-

-

1.85

-

95+2.1 * ns

CL

200+2.9 * ns

( CL - 50 )

25+0.5 * ns

CL

50+0.75 * ns

( CL - 50 )

-

V

-

V

(0.52*VEX V
T/FLEX)0.25

0.8 5)

V

3.0

V

Pad set-up time for LP pad

tSET_LP CC -

-

Input leakage current for P02.1 IOZ021 CC -150

-

-150

-

100

ns

1030

nA

340

nA

-420

-

-350

-

Pull down current for P32_0 pin IPDLP320 CC -

-

|41|

-

|16|

-

1100

nA

380

nA

|105|

µA

-

µA

-

µA

Note / Test Condition
VIHmin; AL and TTL VILmax; AL VILmax; TTL
PMOS/NMOS ;
IOH=0.5mA; IOL=0.5mA
PMOS/NMOS ;
IOH=2mA; IOL=2mA CL50pF; pin out
driver=weak
CL50pF; CL200pF;
pin out driver=weak
CL50pF; pin out
driver=medium
CL50pF; CL200pF;
pin out driver=medium Hysteresis active, AL
Hysteresis active, TTL Hysteresis active, AL
Hysteresis active, TTL Hysteresis inactive; not available for P14.2, P14.4, P15.1, P15.10 and P15.11
(0.1*VEXT/FLEX) < VIN < (0.9*VEXT/FLEX); TJ >
150°C
(0.1*VEXT/FLEX) < VIN < (0.9*VEXT/FLEX); TJ =
150°C
else; TJ > 150°C else; TJ = 150°C VIHmin; AL and TTL VILmax; AL VILmax; TTL

Data Sheet

3-326

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical Specification5 V / 3.3 V switchable Pads

Table 3-7 Class LP 5V (cont'd)

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ.

Max.

Pull Up Current for P32_0 pin IPUHP320 CC |25|

-

|38|

-

-

-

Short Circuit current for LP pad ISC SR

-10

-

6)

|112| 10

µA

VIHmin; AL

µA

VIHmin; TTL

µA

VILmax; AL and TTL

mA absolute max value

(PSI5)

Deviation of symmetry for rising SYM CC -

-

20

%

and falling edges

1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise.

2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged. 3) Rise / fall times are defined 10% - 90% of VEXT/FLEX. 4) VIHx = 0.27 * VEXT/FLEX + 0.545V 5) VILx = 0.17 * VEXT/FLEX 6) The values are only valid if the pad is not used during operation, otherwise ISC defines the limits for operation.

Table 3-8 Class LP 3.3V

Parameter

Symbol

Min.

Input frequency
Input Hysteresis for LP pad 1)
Input Leakage current for LP pad

fIN SR

-

-

HYSLP CC IOZLP CC

0.05 *
VEXT/FLEX
-150

-350

Input leakage current for P32.0 IOZP320 CC -4900

Values Typ. -
-
-

Max. 50 100 -
150
350 4900

-9400 -

9400

-5800 -

-12000 -

Pull-up current for LP pad

IPUHLP CC |17|

-

|19|

-

-

-

Pull-down current for LP pad IPDLLP CC -

-

|22|

-

|11|

-

On-Resistance for LP pad,

RDSONLPW 250

875

weak driver 2)

CC

5900 12000 |75| |75| 1500

Data Sheet

3-327

Unit Note / Test Condition

MHz MHz V

Hysteresis active Hysteresis inactive AL and TTL

nA
nA nA
nA
nA nA µA µA µA µA µA µA Ohm

(0.1*VEXT/FLEX) < VIN < (0.9*VEXT/FLEX)
else
(0.1*VEXT/FLEX) < VIN < (0.9*VEXT/FLEX) (0.1*VEXT/FLEX) < VIN < (0.9*VEXT/FLEX); for TJ >
150 °C
else
else; for TJ > 150°C VIHmin; AL VIHmin; TTL VILmax; AL and TTL VIHmin; AL and TTL VILmax; AL VILmax; TTL
; NMOS/PMOS ;
IOH=0.25mA; IOL=0.25mA

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical Specification5 V / 3.3 V switchable Pads

Table 3-8 Class LP 3.3V (cont'd)

Parameter

Symbol

On-Resistance for LP pad, medium driver 2)
Rise / fall time for LP pad 3)

RDSONLPM
CC
tLP CC

Input high voltage for LP pad VIHLP SR
Input low voltage for LP pad VILLP SR
Input low / high voltage for LP VILHLP CC
pad

Min. 70

Values Typ. 235

Max. 400

Unit Ohm

-

-

-

-

-

-

-

-

(0.73*VEX -
T/FLEX)0.25

1.6 4)

-

-

-

-

-

1.1

-

150+3.4 * ns
CL
320+4.5 * ns
( CL - 50 ) 30+0.8*C ns

L

70+1.1 * ( ns

CL - 50 )

-

V

-

V

(0.52*VEX V
T/FLEX)0.25

0.5 5)

V

1.9

V

Pad set-up time for LP pad

tSET_LP CC -

-

Input leakage current for P02.1 IOZ021 CC -150

-

-150

-

100

ns

920

nA

330

nA

-360

-

-350

-

Pull down current for P32_0 pin IPDLP320 CC -

-

|17|

-

|6|

-

Pull Up Current for P32_0 pin IPUHP320 CC |12|

-

|14|

-

-

-

Short Circuit current for LP pad ISC SR

-10

-

6)

Deviation of symmetry for rising SYM CC -

-

and falling edges

1000

nA

375

nA

|80|

µA

-

µA

-

µA

-

µA

-

µA

|80|

µA

10

mA

20

%

Note / Test Condition
; NMOS/PMOS ;
IOH=1mA; IOL=1mA CL50pF; pin out
driver=weak
CL50pF; CL200pF;
pin out driver=weak
CL50pF; pin out
driver=medium
CL50pF; CL200pF;
pin out driver=medium Hysteresis active, AL
Hysteresis active, TTL Hysteresis active, AL
Hysteresis active, TTL Hysteresis inactive; not available for P14.2, P14.4, P15.1, P15.10 and P15.11
(0.1*VEXT/FLEX) < VIN < (0.9*VEXT/FLEX); TJ >
150°C
(0.1*VEXT/FLEX) < VIN < (0.9*VEXT/FLEX); TJ =
150°C
else; TJ > 150°C else; TJ = 150°C VIHmin; AL and TTL VILmax; AL VILmax; TTL VIHmin; AL VIHmin; TTL VILmax; AL and TTL
absolute max value (PSI5)

Data Sheet

3-328

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical Specification5 V / 3.3 V switchable Pads

1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise.
2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged. 3) Rise / fall times are defined 10% - 90% of VEXT/FLEX. 4) VIHx = 0.27 * VEXT/FLEX + 0.545V 5) VILx = 0.17 * VEXT/FLEX 6) The values are only valid if the pad is not used during operation, otherwise ISC defines the limits for operation.

Table 3-9 Class MP 5V Parameter
Input frequency Input Hysteresis for MP pad 1)
Input Leakage current for MP pad
Pull-up current for MP pad
Pull-down current for MP pad
On-Resistance for MP pad, weak driver 2) On-Resistance for MP pad, medium driver 2) On-Resistance for MP pad, strong driver 2)

Symbol

Min.

fIN SR

-

-

HYSMP CC 0.09 * VEXT/FLEX
0.075 *
VEXT/FLEX IOZMP CC -500

IPUHMP CC
IPDLMP CC
RDSONMPW
CC
RDSONMPM
CC
RDSONMPS
CC

-1000 |30| |43| |46| |21| 200
50
20

Values Typ. -
-
-
620
155
75

Max. 75 150 -
-
500
1000 |107| |100| 1040
260
130

Unit Note / Test Condition

MHz MHz V

Hysteresis active Hysteresis inactive AL

V

TTL

nA
nA µA µA µA µA µA µA Ohm
Ohm
Ohm

(0.1*VEXT/FLEX) < VIN < (0.9*VEXT/FLEX)
else
VIHmin; AL VIHmin; TTL VILmax; AL and TTL VIHmin; AL and TTL VILmax; AL VILmax; TTL
PMOS/NMOS ;
IOH=0.5mA; IOL=0.5mA
PMOS/NMOS ;
IOH=2mA; IOL=2mA
PMOS/NMOS ;
IOH=8mA; IOL=8mA

Data Sheet

3-329

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical Specification5 V / 3.3 V switchable Pads

Table 3-9 Class MP 5V (cont'd)

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ.

Max.

Rise / fall time for MP pad 3) tMP CC

-

-

95+2.1*C ns

CL50pF; pin out

L

driver=weak

-

-

200+2.9*( ns

CL50pF; CL200pF;

CL-50)

pin out driver=weak

-

-

25+0.5*C ns

CL50pF; pin out

L

driver=medium

-

-

50 + 0.75 ns

CL50pF; CL200pF;

* ( CL - 50

pin out driver=medium

)

-

-

17.5+0.25 ns

CL50pF;

*CL

edge=medium ; pin out

driver=strong

-

-

30+0.3*( ns

CL50pF; CL200pF;

CL-50)

edge=medium ; pin out

driver=strong

-

-

7+0.2*CL ns

CL50pF; edge=sharp

; pin out driver=strong

-

-

17+0.3*( ns

CL50pF; CL200pF;

CL-50)

edge=sharp ; pin out

driver=strong

Input high voltage for MP pad VIHMP SR (0.73*VEX -

-

V

Hysteresis active, AL

T/FLEX)-

0.25

2.03 4)

-

-

V

Hysteresis active, TTL

Input low voltage for MP pad VILMP SR -

-

(0.52*VEX V

Hysteresis active, AL

T/FLEX)-

0.25

-

-

0.8 5)

V

Hysteresis active, TTL

Input low / high voltage for MP VILHMP CC 1.85

-

pad

3.0

V

Hysteresis inactive

Pad set-up time for MP pad tSET_MP CC -

-

Short Circuit current for MP pad ISC SR

-10

-

6)

100

ns

10

mA absolute max value

(PSI5)

Deviation of symmetry for rising SYM CC -

-

20

%

and falling edges

1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise.
2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged. 3) Rise / fall times are defined 10% - 90% of VEXT/FLEX. 4) VIHx = 0.27 * VEXT/FLEX + 0.545V 5) VILx = 0.17 * VEXT/FLEX 6) The values are only valid if the pad is not used during operation, otherwise ISC defines the limits for operation.

Data Sheet

3-330

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical Specification5 V / 3.3 V switchable Pads

Table 3-10 Class MP 3.3V Parameter Input frequency Input Hysteresis for MP pad 1) Input Leakage current for MP pad Pull-up current for MP pad
Pull-down current for MP pad
On-Resistance for MP pad, weak driver 2)

Symbol

Min.

fIN SR

-

-

HYSMP CC 0.05 * VEXT/FLEX
IOZMP CC -500

IPUHMP CC
IPDLMP CC
RDSONMPW
CC

-1000 |17| |19| |22| |11| 250

Values Typ. -
-
875

Max. 50 100 -
500
1000 |75| |75| 1500

Unit
MHz MHz V
nA
nA µA µA µA µA µA µA Ohm

On-Resistance for MP pad, medium driver 2)
On-Resistance for MP pad, strong driver 2)
Rise / fall time for MP pad 3)

RDSONMPM 70
CC

RDSONMPS 20
CC

tMP CC

-

-

-

-

-

-

-

235

400

Ohm

110

200

Ohm

-

150+3.4* ns

CL

-

320+4.5*( ns

CL-50)

-

30+0.8*C ns

L

-

70+1.1*( ns

CL-50)

-

32.5+0.35 ns

*CL

-

50+0.45*( ns

CL-50)

-

14.5+0.35 ns

*CL

-

32+0.5*( ns

CL-50)

Note / Test Condition
Hysteresis active
Hysteresis inactive
AL and TTL
(0.1*VEXT/FLEX) < VIN < (0.9*VEXT/FLEX)
else
VIHmin; AL VIHmin; TTL VILmax; AL and TTL VIHmin; AL and TTL VILmax; AL VILmax; TTL
; NMOS/PMOS ;
IOH=0.25mA; IOL=0.25mA
; NMOS/PMOS ;
IOH=1mA; IOL=1mA
PMOS/NMOS ;
IOH=4mA; IOL=4mA CL50pF; pin out
driver=weak
CL50pF; CL200pF;
pin out driver=weak
CL50pF; pin out
driver=medium
CL50pF; CL200pF;
pin out driver=medium
CL50pF;
edge=medium ; pin out driver=strong
CL50pF; CL200pF;
edge=medium ; pin out driver=strong
CL50pF; edge=sharp
; pin out driver=strong
CL50pF; CL200pF;
edge=sharp ; pin out driver=strong

Data Sheet

3-331

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical Specification5 V / 3.3 V switchable Pads

Table 3-10 Class MP 3.3V (cont'd)

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ.

Max.

Input high voltage for MP pad VIHMP SR (0.73*VEX -

-

V

Hysteresis active, AL

T/FLEX)-

0.25

1.6 4)

-

-

V

Hysteresis active, TTL

Input low voltage for MP pad VILMP SR -

-

(0.52*VEX V

Hysteresis active, AL

T/FLEX)-

0.25

-

-

0.5 5)

V

Hysteresis active, TTL

Input low / high voltage for MP VILHMP CC 1.1

-

pad

1.9

V

Hysteresis inactive

Pad set-up time for MP pad tSET_MP CC -

-

Short Circuit current for MP pad ISC SR

-10

-

6)

100

ns

10

mA absolute max value

(PSI5)

Deviation of symmetry for rising SYM CC -

-

20

%

and falling edges

1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise.

2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged. 3) Rise / fall times are defined 10% - 90% of VEXT/FLEX. 4) VIHx = 0.27 * VEXT/FLEX + 0.545V 5) VILx = 0.17 * VEXT/FLEX 6) The values are only valid if the pad is not used during operation, otherwise ISC defines the limits for operation.

Table 3-11 Class MP+ 5V

Parameter

Symbol

Min.

Input frequency

fIN SR

Input hysteresis for MP+ pad 1) HYSMPP
CC

Input leakage current for MP+ IOZMPP CC
pad

-
-
0.09 *
VEXT/FLEX
0.075 *
VEXT/FLEX
-750

-1500

Pull-up current for MP+ pad

IPUHMPP CC |30|
|43|

-

Pull-down current for MP+ pad IPDLMPP CC -
|46|

|21|

Values Typ. -
-
-
-

Max. 75 150 -
-
750
1500 |107| |100| -

Data Sheet

3-332

Unit Note / Test Condition

MHz MHz V

Hysteresis active Hysteresis inactive AL

V

TTL

nA

(0.1*VEXT/FLEX) < VIN <

(0.9*VEXT/FLEX)

nA else

µA

VIHmin; AL

µA

VIHmin; TTL

µA

VILmax; AL and TTL

µA

VIHmin; AL and TTL

µA

VILmax; AL

µA

VILmax; TTL

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical Specification5 V / 3.3 V switchable Pads

Table 3-11 Class MP+ 5V (cont'd)

Parameter

Symbol

On-resistance for MP+ pad, weak driver 2)
On-resistance for MP+ pad, medium driver 2)
On-resistance for MP+ pad, strong driver 2)
Rise/fall time for MP+ pad 3)

RDSONMPPW
CC
RDSONMPPM
CC
RDSONMPPS
CC
tMPP CC

Min. 200 50 20 -

-

-

-

-

-

-

-

Values Typ. 620

Max. 1040

Unit Ohm

155

260

Ohm

55

90

Ohm

-

95+2.1*C ns

L

-

200+2.9*( ns

CL-50)

-

25+0.5*C ns

L

-

50+0.75*( ns

CL-50)

-

9+0.16*C ns

L

-

17+0.2*( ns

CL-50)

-

4+0.16*C ns

L

-

12+0.21*( ns

CL-50)

-

5

ns

-

-

Input high voltage for MP+ pad VIHMPP SR Input low voltage for MP+ pad VILMPP SR

(0.73*VEX -
T/FLEX)0.25

2.03 4)

-

-

-

-

-

Input low / high voltage for MP+ VILHMPP CC 1.85

-

pad

Pad set-up time for MP+ pad tSET_MPP CC -

-

4.5

ns

-

V

-

V

(0.52*VEX V
T/FLEX)0.25

0.8 5)

V

3.0

V

100

ns

Note / Test Condition
PMOS/NMOS ;
IOH=0.5mA; IOL=0.5mA
PMOS/NMOS ;
IOH=2mA; IOL=2mA
PMOS/NMOS ;
IOH=8mA; IOL=8mA CL50pF; pin out
driver=weak
CL50pF; CL200pF;
pin out driver=weak
CL50pF; pin out
driver=medium
CL50pF; CL200pF;
pin out driver=medium
CL50pF;
edge=medium ; pin out driver=strong
CL50pF; CL200pF;
edge=medium ; pin out driver=strong
CL50pF; edge=sharp
; pin out driver=strong
CL50pF; CL200pF;
edge=sharp ; pin out driver=strong from 0.8V to 2.0V
(RMII) ; CL=25pF;
edge=sharp ; pin out driver=strong
CL=15pF; edge=sharp
; pin out driver=strong Hysteresis active, AL
Hysteresis active, TTL Hysteresis active, AL
Hysteresis active, TTL Hysteresis inactive

Data Sheet

3-333

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical Specification5 V / 3.3 V switchable Pads

Table 3-11 Class MP+ 5V (cont'd)

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ.

Max.

Short circuit current for MP+ ISCMPP SR -10

-

pad 6)

10

mA absolute max value

(PSI5)

Deviation of symmetry for rising SYM CC -

-

20

%

and falling edges

1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise.

2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged. 3) Rise / fall times are defined 10% - 90% of VEXT/FLEX. 4) VIHx = 0.27 * VEXT/FLEX + 0.545V 5) VILx = 0.17 * VEXT/FLEX 6) The values are only valid if the pad is not used during operation, otherwise ISC defines the limits for operation.

Table 3-12 Class MP+ 3.3V

Parameter

Symbol

Min.

Input frequency

fIN SR

Input hysteresis for MP+ pad 1) HYSMPP
CC
Input leakage current for MP+ IOZMPP CC
pad

0.05 *
VEXT/FLEX
-750

-1500

Pull-up current for MP+ pad

IPUHMPP CC |17|
|19|

-

Pull-down current for MP+ pad IPDLMPP CC -
|22|

|11|

On-resistance for MP+ pad, weak driver 2)

RDSONMPPW 250
CC

Values Typ. -
-
875

Max. 50 100 -
750
1500 |75| |75| 1500

On-resistance for MP+ pad, medium driver 2)
On-resistance for MP+ pad, strong driver 2)

RDSONMPPM 70
CC
RDSONMPPS 20
CC

235

400

75

130

Unit Note / Test Condition

MHz MHz V

Hysteresis active Hysteresis inactive AL and TTL

nA
nA µA µA µA µA µA µA Ohm
Ohm
Ohm

(0.1*VEXT/FLEX) < VIN < (0.9*VEXT/FLEX)
else
VIHmin; AL VIHmin; TTL VILmax; AL and TTL VIHmin; AL and TTL VILmax; AL VILmax; TTL
; NMOS/PMOS ;
IOH=0.25mA; IOL=0.25mA
; NMOS/PMOS ;
IOH=1mA; IOL=1mA
PMOS/NMOS ;
IOH=4mA; IOL=4mA

Data Sheet

3-334

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical Specification5 V / 3.3 V switchable Pads

Table 3-12 Class MP+ 3.3V (cont'd)

Parameter

Symbol

Rise/fall time for MP+ pad 3) tMPP CC

Data Sheet

Min. -
-
-

Values Typ. -
-
-
-
-

Unit
Max.
150+3.4* ns
CL
320+4.5*( ns
CL-50) 30+0.8*C ns
L
70+1.1*( ns
CL-50) 20+0.2*C ns
L

-

30+0.3*( ns

CL-50)

-

13+0.2*C ns

L

-

7.65

ns

-

-

5.42

ns

-

-

7.36

ns

-

-

5.32

ns

-

-

5.9

ns

-

-

4.8

ns

-

-

-

-

3-335

-

-

23+0.3*( ns
CL-50)

5

ns

4.5

ns

Note / Test Condition
CL50pF; pin out
driver=weak
CL50pF; CL200pF;
pin out driver=weak
CL50pF; pin out
driver=medium
CL50pF; CL200pF;
pin out driver=medium
CL50pF;
edge=medium ; pin out driver=strong
CL50pF; CL200pF;
edge=medium ; pin out driver=strong
CL50pF; edge=sharp
; pin out driver=strong
CL = 15pF; VEXT/FLEX = 3.135V; V = 0V to
2.0V; edge=sharp ; pin out driver=strong
CL = 15pF; VEXT/FLEX = 3.135V; V = 3.135V to
0.8V; edge=sharp ; pin out driver=strong
CL = 15pF; VEXT/FLEX = 3.201V; V = 0V to
2.0V; edge=sharp ; pin out driver=strong
CL = 15pF; VEXT/FLEX = 3.201V; V = 3.201V to
0.8V; edge=sharp ; pin out driver=strong
CL = 15pF; VEXT/FLEX = 3.63V; V = 0V to 2.0V;
edge=sharp ; pin out driver=strong
CL = 15pF; VEXT/FLEX = 3.63V; V = 3.63V to
0.8V; edge=sharp ; pin out driver=strong
CL50pF; CL200pF;
edge=sharp ; pin out driver=strong
from 0.8V to 2.0V
(RMII) ; CL=25pF;
edge=shaVrp1;.0pi2n0o1u7t-03 driver=strong
from 0.2 * VEXT/FLEX to

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical Specification5 V / 3.3 V switchable Pads

Table 3-12 Class MP+ 3.3V (cont'd)

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ.

Max.

Input high voltage for MP+ pad VIHMPP SR (0.73*VEX -

-

V

Hysteresis active, AL

T/FLEX)-

0.25

1.6 4)

-

-

V

Hysteresis active, TTL

Input low voltage for MP+ pad VILMPP SR -

-

(0.52*VEX V

Hysteresis active, AL

T/FLEX)-

0.25

-

-

0.5 5)

V

Hysteresis active, TTL

Input low / high voltage for MP+ VILHMPP CC 1.1

-

pad

1.9

V

Hysteresis inactive

Pad set-up time for MP+ pad tSET_MPP CC -

-

Short circuit current for MP+ ISCMPP SR -10

-

pad 6)

100

ns

10

mA absolute max value

(PSI5)

Deviation of symmetry for rising SYM CC -

-

20

%

and falling edges

1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise.

2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged. 3) Rise / fall times are defined 10% - 90% of VEXT/FLEX. 4) VIHx = 0.27 * VEXT/FLEX + 0.545V 5) VILx = 0.17 * VEXT/FLEX 6) The values are only valid if the pad is not used during operation, otherwise ISC defines the limits for operation.

Table 3-13 Class MPR 5V

Parameter

Symbol

Min.

Input frequency

fIN SR

-

-

Input Hysteresis for MPR pads HYSMPR

1)

CC

Input leakage current class MPR

IOZMPR CC

0.09 *
VEXT/FLEX
0.075*
VEXT/FLEX
-750

-1500

Pull-up current

IPUHMPR CC |30|
|43|

-

Pull-down current

IPDLMPR CC -
|46|

|21|

Values Typ. -
-
-
-

Max. 75 150 -
-
750
1500 |107| |100| -

Data Sheet

3-336

Unit Note / Test Condition

MHz MHz V

Hysteresis active Hysteresis inactive AL

V

TTL

nA

(0.1*VEXT/FLEX) < VIN <

(0.9*VEXT/FLEX)

nA else

µA

VIHmin; AL

µA

VIHmin; TTL

µA

VILmax; AL and TTL

µA

VIHmin; AL and TTL

µA

VILmax; AL

µA

VILmax; TTL

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical Specification5 V / 3.3 V switchable Pads

Table 3-13 Class MPR 5V (cont'd)

Parameter

Symbol

Min.

On-resistance of the MPR pad, RDSONMPRW 200

weak driver 2)

CC

On-resistance of the MPR pad, RDSONMPRM 50

medium driver 2)

CC

On-resistance of the MPR pad, RDSONMPRS 20

strong driver 2)

CC

Rise/fall time 3)

tMPR CC

-

-

-

-

-

-

-

-

Values Typ. 620

Max. 1040

Unit Ohm

155

260

Ohm

55

90

Ohm

-

95+2.1*C ns

L

-

200+2.9*( ns

CL-50)

-

25+0.5*C ns

L

-

50+0.75*( ns

CL-50)

-

9+0.16*C ns

L

-

17+0.2*( ns

CL-50)

-

4+0.16*C ns

L

-

12+0.21*( ns

CL-50)

-

5

ns

-

-

4.5

ns

Input high voltage, class MPR VIHMPR SR
pads
Input low voltage, class MPR VILMPR SR
pads

(0.73*VEX -
T/FLEX)0.25

2.03 4)

-

-

-

-

-

Input low / high voltage, class VILHMPR SR 1.2

-

MPR pads

-

V

-

V

(0.52*VEX V
T/FLEX)0.25

0.8 5)

V

2.3

V

Note / Test Condition
PMOS/NMOS ;
IOH=0.5mA; IOL=0.5mA
PMOS/NMOS ;
IOH=2mA; IOL=2mA
PMOS/NMOS ;
IOH=8mA; IOL=8mA CL50pF; pin out
driver=weak
CL50pF; CL200pF;
pin out driver=weak
CL50pF; pin out
driver=medium
CL50pF; CL200pF;
pin out driver=medium
CL0pF; CL50pF;
edge=medium ; pin out driver=strong
CL50pF; CL200pF;
edge=medium ; pin out driver=strong
CL50pF; edge=sharp
; pin out driver=strong
CL50pF; CL200pF;
edge=sharp ; pin out driver=strong from 0.8V to 2.0V
(RMII) ; CL=25pF;
edge=sharp ; pin out driver=strong
from 0.2 * VEXT/FLEX to 0.8 * VEXT/FLEX; CL=15pF; edge=sharp
; pin out driver=strong Hysteresis active, AL
Hysteresis active, TTL Hysteresis active, AL
Hysteresis active, TTL Hysteresis inactive

Data Sheet

3-337

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical Specification5 V / 3.3 V switchable Pads

Table 3-13 Class MPR 5V (cont'd)

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ.

Max.

Pad set-up time

tSET_MPR CC -

-

Short circuit current Class MPR ISC SR

-10

-

100

ns

10

mA absolute max value

(PSI5)

Deviation of symmetry for rising SYM CC -

-

20

%

and falling edges

1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise.

2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged. 3) Rise / fall times are defined 10% - 90% of VEXT/FLEX. 4) VIHx = 0.27 * VEXT/FLEX + 0.545V 5) VILx = 0.17 * VEXT/FLEX

Table 3-14 Class MPR 3.3V

Parameter

Symbol

Min.

Input frequency

fIN SR

-

-

Input Hysteresis for MPR pads HYSMPR

1)

CC

Input leakage current class MPR

IOZMPR CC

0.05 *
VEXT/FLEX
-750

-1500

Pull-up current

IPUHMPR CC |17|
|19|

-

Pull-down current

IPDLMPR CC -
|22|

|11|

On-resistance of the MPR pad, RDSONMPRW 250

weak driver 2)

CC

Values Typ. -
-
875

Max. 50 100 -
750
1500 |75| |75| 1500

On-resistance of the MPR pad, RDSONMPRM 70

medium driver 2)

CC

On-resistance of the MPR pad, RDSONMPRS 20

strong driver 2)

CC

235

400

75

130

Unit Note / Test Condition

MHz MHz V

Hysteresis active Hysteresis inactive AL and TTL

nA
nA µA µA µA µA µA µA Ohm
Ohm
Ohm

(0.1*VEXT/FLEX) < VIN < (0.9*VEXT/FLEX)
else
VIHmin; AL VIHmin; TTL VILmax; AL and TTL VIHmin; AL and TTL VILmax; AL VILmax; TTL
; NMOS/PMOS ;
IOH=0.25mA; IOL=0.25mA
; NMOS/PMOS ;
IOH=1mA; IOL=1mA
PMOS/NMOS ;
IOH=4mA; IOL=4mA

Data Sheet

3-338

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical Specification5 V / 3.3 V switchable Pads

Table 3-14 Class MPR 3.3V (cont'd)

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ.

Max.

Rise/fall time 3)

tMPR CC

-

-

150+3.4* ns

CL50pF; pin out

CL

driver=weak

-

-

320+4.5*( ns

CL50pF; CL200pF;

CL-50)

pin out driver=weak

-

-

30+0.8*C ns

CL50pF; pin out

L

driver=medium

-

-

70+1.1*( ns

CL50pF; CL200pF;

CL-50)

pin out driver=medium

-

-

20+0.2*C ns

CL0pF; CL50pF;

L

edge=medium ; pin out

driver=strong

-

-

30+0.3*( ns

CL50pF; CL200pF;

CL-50)

edge=medium ; pin out

driver=strong

-

-

13+0.2*C ns

CL50pF; edge=sharp

L

; pin out driver=strong

-

-

23+0.3*( ns

CL50pF; CL200pF;

CL-50)

edge=sharp ; pin out

driver=strong

-

-

5

ns

from 0.8V to 2.0V

(RMII) ; CL=25pF;
edge=sharp ; pin out

driver=strong

-

-

4.5

ns

from 0.2 * VEXT/FLEX to

0.8 * VEXT/FLEX;

CL=15pF; edge=sharp

; pin out driver=strong

Input high voltage, class MPR VIHMPR SR (0.73*VEX -

-

V

Hysteresis active, AL

pads

T/FLEX)-

0.25

1.6 4)

-

-

V

Hysteresis active, TTL

Input low voltage, class MPR VILMPR SR -

-

(0.52*VEX V

Hysteresis active, AL

pads

T/FLEX)-

0.25

-

-

0.5 5)

V

Hysteresis active, TTL

Input low / high voltage, class VILHMPR SR 0.8

-

MPR pads

1.7

V

Hysteresis inactive

Pad set-up time

tSET_MPR CC -

-

Short circuit current Class MPR ISC SR

-10

-

100

ns

10

mA absolute max value

(PSI5)

1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise.
2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged.

Data Sheet

3-339

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical Specification5 V / 3.3 V switchable Pads

3) Rise / fall times are defined 10% - 90% of VEXT/FLEX. 4) VIHx = 0.27 * VEXT/FLEX + 0.545V 5) VILx = 0.17 * VEXT/FLEX

Table 3-15 Class S

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ.

Max.

Input frequency

fIN SR

-

-

-

-

Input Hysteresis for S pad 1) HYSS CC 0.3

-

75

MHz Hysteresis active

150

MHz Hysteresis inactive

-

V

Pull-up current for S pad

IPUHS CC |30|

-

-

-

Pull-down current for S pad IPDLS CC -

-

|46|

-

Input Leakage current Class S IOZS CC -350

-

|107| |100| 350

µA

VIHmin

µA

VILmax

µA

VIHmin

µA

VILmax

nA Analog Inputs with pull

down diagnostics

-150

-

150

nA else

Input voltage high for S pad VIHS SR

-

-

(0.73*VDD V

Hysteresis active

M)-0.25

Input voltage low for S pad

VILS SR

(0.52*VDD -

-

V

Hysteresis active

M)-0.25

Input low threshold variation for VILSD SR -50

-

S pad 2)

50

mV max. variation of 1ms;

VDDM=constant

Input capacitance for S pad CINS CC -

-

10

pF

Pad set-up time for S pad

tSETS CC

-

-

100

ns

1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed

that it suppresses switching due to external system noise.

2) VILSD is implemented to ensure J2716 specification. For details of dedicated pins please see AP32286 for details.

Table 3-16 Class I 5V Parameter Input frequency Input Hysteresis for I pad 1)
Pull-up current for I pad
Data Sheet

Symbol
fIN SR HYSI CC
IPUHI CC

Min.
-
-
0.07 *
VEXT/FLEX
0.09 *
VEXT/FLEX
0.075 *
VEXT/FLEX
|30|
|43|
-

Values Typ. -
-
-
-

Max. 75 150 -
-
-
|107|

3-340

Unit Note / Test Condition

MHz MHz V

Hysteresis active Hysteresis inactive PORST pad only

V

AL

V

TTL

µA

VIHmin; AL

µA

VIHmin; TTL

µA

VILmax; AL and TTL

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical Specification5 V / 3.3 V switchable Pads

Table 3-16 Class I 5V (cont'd)

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ.

Max.

Pull-down current for I pad

IPDLI CC

-

-

|46|

-

|21|

-

Input Leakage Current for I pad IOZI CC

-150

-

-350

-

|100| 150
350

µA

VIHmin; AL and TTL

µA

VILmax; AL

µA

VILmax; TTL

nA

(0.1*VEXT/FLEX) < VIN <

(0.9*VEXT/FLEX)

nA else

Input high voltage for I pad Input low voltage for I pad

VIHI SR VILI SR

2.03 2)

-

(0.73*VEX -
T/FLEX)0.25

-

-

-

-

-

V

-

V

0.8 3)

V

(0.52*VEX V
T/FLEX)0.25

Hysteresis active, TTL
Hysteresis active; AL; not available for the PORST pad
Hysteresis active, TTL
Hysteresis active; AL; not available for the PORST pad

Input low / high voltage for I pad VILHI CC 1.85

-

3.0

V

Hysteresis inactive

Pad set-up time for I pad

tSETI CC

-

-

100

ns

1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise.

2) VIHx = 0.27 * VEXT/FLEX + 0.545V 3) VILx = 0.17 * VEXT/FLEX

Table 3-17 Class I 3.3V Parameter

Symbol

Input frequency Input Hysteresis for I pad 1)

fIN SR HYSI CC

Pull-up current for I pad

IPUHI CC

Pull-down current for I pad

IPDLI CC

Input Leakage Current for I pad IOZI CC

Min. 0.045 *
VEXT/FLEX
0.05 *
VEXT/FLEX
|17| |19| |22| |11| -150

Values Typ. -
-
-

Max. 50 100 -
-
|75| |75| 150

-350

-

350

Unit Note / Test Condition

MHz MHz V

Hysteresis active Hysteresis inactive PORST pad only

V

AL and TTL

µA

VIHmin; AL

µA

VIHmin; TTL

µA

VILmax; AL and TTL

µA

VIHmin; AL and TTL

µA

VILmax; AL

µA

VILmax; TTL

nA

(0.1*VEXT/FLEX) < VIN <

(0.9*VEXT/FLEX)

nA else

Data Sheet

3-341

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical Specification5 V / 3.3 V switchable Pads

Table 3-17 Class I 3.3V (cont'd)

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ.

Max.

Input high voltage for I pad Input low voltage for I pad

VIHI SR VILI SR

1.6 2)

-

(0.73*VEX -
T/FLEX)0.25

-

-

-

-

-

V

-

V

0.5 3)

V

(0.52*VEX V
T/FLEX)0.25

Hysteresis active, TTL
Hysteresis active; AL; not available for the PORST pad
Hysteresis active, TTL
Hysteresis active; AL; not available for the PORST pad

Input low / high voltage for I pad VILHI CC 1.1

-

1.9

V

Hysteresis inactive

Pad set-up time for I pad

tSETI CC

-

-

100

ns

1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise.

2) VIHx = 0.27 * VEXT/FLEX + 0.545V 3) VILx = 0.17 * VEXT/FLEX

Table 3-18 Class A2 Parameter
Input frequency Input Hysteresis for A2 pad 1)
Input Leakage current for A2 pad
Pull-up current for A2 pad
Pull-down current for A2 pad
On-Resistance for A2 pad, weak driver 2) On-Resistance for A2 pad, medium driver 2) On-Resistance for A2 pad, strong driver 2)

Symbol

Min.

fIN SR HYSA2 CC
IOZA2 CC

-
0.1 *
VDDP3
0.06 *
VDDP3
-300

IPUHA2 CC
IPDLA2 CC
RDSONA2W
CC
RDSONA2M
CC
RDSONA2S
CC

-800 |25| |23| 100
40
20

Values Typ. -

Max. 160 -

-

-

-

300

-

500

-

|100|

-

-

-

-

-

|100|

200

325

70

100

35

50

Unit Note / Test Condition

MHz

V

TTL;else

V
nA
nA µA µA µA µA Ohm
Ohm
Ohm

valid for P21.6 and P21.7
(0.1*VEXT/FLEX) < VIN < (0.9*VEXT/FLEX)
else
VIHmin VILmax VIHmin VILmax
PMOS/NMOS ;
IOH=0.5mA; IOL=0.5mA
PMOS/NMOS ;
IOH=2mA; IOL=2mA
PMOS/NMOS ;
IOH=8mA; IOL=8mA

Data Sheet

3-342

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical Specification5 V / 3.3 V switchable Pads

Table 3-18 Class A2 (cont'd)

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ.

Max.

Rise/fall time for A2 pad 3)

tA2 CC

-

-

20+0.8*C ns

CL50pF; pin out

L

driver=weak

-

-

17.5+0.85 ns

CL50pF; CL200pF;

*CL

pin out driver=weak

-

-

12+0.16* ns

CL50pF; pin out

CL

driver=medium

-

-

11.5+0.17 ns

CL50pF; CL200pF;

*CL

pin out driver=medium

-

-

6+0.06*C ns

CL50pF;

L

edge=medium ; pin out

driver=strong

-

-

5.5+0.07* ns

CL50pF; CL200pF;

CL

edge=medium ; pin out

driver=strong

-

-

-

-

Input high voltage for A2 pad VIHA2 SR 2.04 4)

-

0.0+0.12* ns
CL
0.0+0.12* ns
CL

-

V

CL50pF; edge=sharp
; pin out driver=strong
CL50pF; CL200pF;
edge=sharp ; pin out driver=strong
TTL;valid for all A2 pads except TMS/DAP1, TRST, and TCK/DAP0

0.7 *

-

VDDP3

Input low voltage for A2 pad VILA2 SR -

-

-

V

0.8 5)

V

valid for TMS/DAP1, TRST, and TCK/DAP0
TTL;valid for all A2 pads except TMS/DAP1, TRST, and TCK/DAP0

-

-

0.3 *

V

valid for TMS/DAP1,

VDDP3

TRST, and TCK/DAP0

Pad set-up time for A2 pad

tSETA2 CC -

-

100

ns

Deviation of symmetry for rising SYM CC -

-

20

%

and falling edges

1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise.

2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged. 3) Rise / fall times are defined 10% - 90% of VDDP3. 4) VIHx = 0.57 * VDDP3 - 0.03V 5) VILx = 0.25 * VDDP3 + 0.058V

Data Sheet

3-343

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical Specification5 V / 3.3 V switchable Pads

Table 3-19 Driver Mode Selection for LP Pads

PDx.2

PDx.1

PDx.0

Port Functionality

X

X

0

Speed grade 1

X

X

1

Speed grade 2

Table 3-20 Driver Mode Selection for MP / MP+ Pads

PDx.2

PDx.1

PDx.0

Port Functionality

X

0

0

Speed grade 1

X

0

1

Speed grade 2

X

1

0

Speed grade 3

X

1

1

Speed grade 4

Table 3-21 Driver Mode Selection for A2 Pads

PDx.2

PDx.1

PDx.0

Port Functionality

X

0

0

Speed grade 1

X

0

1

Speed grade 2

X

1

0

Speed grade 3

X

1

1

Speed grade 4

Table 3-22 Driver Mode Selection for F Pads

PDx.2

PDx.1

PDx.0

Port Functionality

X

0

0

Speed grade 1

X

0

1

Speed grade 2

X

1

0

Speed grade 3

X

1

1

Speed grade 4

Driver Setting medium (LPm) weak (LPw)
Driver Setting Strong sharp edge (MPss / MP+ss) Strong medium edge (MPsm / MP+sm) medium (MPm / MP+m) weak (MPw / MP+w)
Driver Setting Strong sharp edge Strong medium edge medium weak
Driver Setting Reduced Strong sharp edge Reduced Strong medium edge medium weak

Data Sheet

3-344

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationHigh performance LVDS Pads (LVDSH)

3.6

High performance LVDS Pads (LVDSH)

This LVDS pad type is used for the high speed chip to chip communication inferface of the new TC290 / TC297 / TC298 / TC299. It compose out of a LVDSH pad and a Class F pad.

This pad combination is always supplied by the 3.3V supply rail.

Table 3-23 Class F Parameter
Input frequency Input Hysteresis for F pad 1)
Input Leakage Current for F pad

Symbol
fIN SR HYSF CC IOZF CC

Min. 0.1 *
VDDP3
-1000

Values Typ. -

Max. 75 -

-

-

-

-

1000

-1500 -

1500

-300

-

300

-

-

2000

-2000 -

-

-3000 -

3000

-600

-

Pull-up current for F pad

IPUHF CC |25|

-

-

-

Pull-down current for class F IPDLF CC -

-

pads

|25|

-

On resistance for F pad, weak RDSONFW 100

200

driver 2)

CC

600
|100| |100| 325

Unit Note / Test Condition

MHz

V

TTL

nA
nA
nA
nA nA nA nA nA µA µA µA µA Ohm

(0.1*VDDP3) < VIN < (0.9*VDDP3); valid for
P21.0, P21.1, P21.2
and P21.3; TJ = 150°C
(0.1*VDDP3) < VIN < (0.9*VDDP3); valid for
P21.0, P21.1, P21.2
and P21.3; TJ =
150°C
(0.1*VDDP3) < VIN < (0.9*VDDP3); valid for
P21.0, P21.1, P21.2
and P21.3; TJ =
170°C
(0.1*VDDP3) < VIN < (0.9*VDDP3); valid for
P21.4 and P21.5
else; valid for P21.0, P21.1, P21.2 and
P21.3; TJ = 150°C
else; valid for P21.0, P21.1, P21.2 and
P21.3; TJ = 150°C
else; valid for P21.0, P21.1, P21.2 and
P21.3; TJ = 170°C
else; valid for P21.4 and P21.5
VIHmin
VILmax
VIHmin
VILmax
PMOS/NMOS ;
IOH=0.5mA; IOL=0.5mA

Data Sheet

3-345

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationHigh performance LVDS Pads (LVDSH)

Table 3-23 Class F (cont'd)

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ.

Max.

On resistance for F pad,

RDSONFM

40

70

100

Ohm PMOS/NMOS ;

medium driver 2)

CC

IOH=2mA; IOL=2mA

On resistance for F pad, strong RDSONFS CC 20

50

80

Ohm PMOS/NMOS ;

driver 2)

IOH=4mA; IOL=4mA

Rise/fall time for F pad 3)

trfF CC

-

-

20+0.8*C ns

CL50pF; pin out

L

driver=weak

-

-

17.5+0.85 ns

CL50pF; CL200pF;

*CL

pin out driver=weak

-

-

12+0.16* ns

CL50pF; pin out

CL

driver=medium

-

-

11.5+0.17 ns

CL50pF; CL200pF;

*CL

pin out driver=medium

-

-

7+0.16*C ns

CL50pF;

L

edge=medium ; pin out

driver=reduced strong

-

-

6.5+0.17* ns

CL50pF; CL200pF;

CL

edge=meduim ; pin out

driver>reduced strong

-

-

4+0.16*C ns

CL50pF; edge=sharp

L

; pin out

driver=reduced strong

-

-

3.5+0.17* ns

CL50pF; CL200pF;

CL

edge=sharp ; pin out

driver=reduced strong

Input high voltage for F pad VIHF SR

2.04 4)

-

Input low voltage for F pad

VILF SR

-

-

Pad set-up time for F pad

tSETF CC

-

-

Deviation of symmetry for rising SYM CC -

-

and falling edges

-

V

TTL

0.8 5)

V

TTL

100

ns

20

%

1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can't be guaranteed that it suppresses switching due to external system noise.
2) For currents smaller than the IOL/OH from the test condition the defined Max. value stays unchanged. 3) Rise / fall times are defined 10% - 90% of VDDP3. 4) VIHx = 0.57 * VDDP3 - 0.03V 5) VILx = 0.25 * VDDP3 + 0.058V

CL = 2.5 pF for all LVDSH parameters.

Data Sheet

3-346

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationHigh performance LVDS Pads (LVDSH)

Table 3-24 LVDSH - IEEE standard LVDS general purpose link (GPL)

Parameter

Symbol

Values

Min.

Typ.

Max.

Output impedance Rise time 1)

R0 CC

40

-

140

trise20 CC

-

-

0.5

Fall time 1)

tfall20 CC

-

-

0.5

Output differential voltage

VOD CC

250

-

Output voltage high

VOH CC

-

-

400 1475

Output voltage low

VOL CC

925

-

Output offset (Common mode) VOS CC

1125

-

voltage

Input voltage range

VI SR

0

-

1275
1600

0

-

2000

Input differential threshold

Vidth SR

-100

-

100

Delta output impedance

dR0 SR -

-

10

Change in VOS between 0 and dVOS CC -

-

25

1

Change in Vod between 0 and dVod CC -

-

25

1

Duty cycle

tduty CC

45

-

55

1) Rise / fall times are defined for 20% - 80% of VOD

Table 3-25 LVDSH - IEEE standard LVDS reduced link (REDL)

Parameter

Symbol

Values

Min.

Typ.

Max.

Output impedance

R0 CC

40

-

Output differential voltage

VOD CC

150

-

Output voltage high

VOH CC

-

-

Output voltage low

VOL CC

1025

-

Output offset (Common mode) VOS CC

1125

-

voltage

140 250 1375 1275

Input voltage range

VI SR

825

-

1575

Unit Note / Test Condition

Ohm ns
ns
mV mV
mV mV

Vcm = 1.0 V and 1.4 V ZL = 100 Ohm ±5% @2 pF ZL = 100 Ohm ±5% @ 2 pF RT = 100 Ohm ±5% RT = 100 Ohm ±5% (400 mV/2) + 1275 mV RT = 100 Ohm ±5% RT = 100 Ohm ±5%

mV Driver ground potential difference < 925 mV; RT = 100 Ohm ±10%

mV Driver ground potential difference < 925 mV; RT = 100 Ohm ±20%

mV Driver ground potential difference < 925 mV

%

Vcm = 1.0 V and 1.4 V

(mismatch Pd and Pn)

mV RT = 100 Ohm ±5%

mV RT = 100 Ohm ±5%

%

Unit Note / Test Condition

Ohm mV mV mV mV

Vcm = 1.0 V and 1.4 V RT = 100 Ohm ±5% RT = 100 Ohm ±5% RT = 100 Ohm ±5% RT = 100 Ohm ±5%

mV Driver ground potential difference < 50 mV

Data Sheet

3-347

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationHigh performance LVDS Pads (LVDSH)

Table 3-25 LVDSH - IEEE standard LVDS reduced link (REDL) (cont'd)

Parameter

Symbol

Values

Min.

Typ.

Max.

Input differential threshold

Vidth SR

-100

-

100

Change in VOS between 0 and dVOS CC -

-

25

1

Change in Vod between 0 and dVod CC -

-

25

1

Duty cycle
VOD Fall time 1)

tduty CC

45

-

55

tfall10 CC

-

-

0.5

VOD Rise time 1)

trise10 CC

-

-

0.5

1) Rise / fall times are defined for 10% - 90% of VOD default after start-up = CMOS function

Unit Note / Test Condition

mV Driver ground potential difference < 50 mV
mV RT = 100 Ohm ±5%

mV RT = 100 Ohm ±5%

%

ns

ZL = 100 Ohm ±5% @

2pF

ns

ZL = 100 Ohm ±5% @

2pF

Cext=2pF RT=100Ohm
Cext=2pF

Htotal=5nH

Ctotal=3.5pF

P

LVDSH

Rin

IN

Htotal=5nH

N Ctotal=3.5pF

Figure 3-1 LVDSH pad Input model

LVDSH _Input _Pad _Model .vsd

Data Sheet

3-348

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationMedium performance LVDS Pads (LVDSM)

3.7

Medium performance LVDS Pads (LVDSM)

This LVDS pad type is used for the medium speed chip to chip communication inferface of the new TC290 / TC297 / TC298 / TC299. It compose out of a LVDSM pad and a MP pad.

This pad combination is always supplied by the 5V or 3.3V.

For the parameters of the MP pad please see Chapter 3.5.

Table 3-26 LVDSM Parameter
Output impedance Fall time

Symbol
RO CC tF CC

Min. 40 -

Rise time

tR CC

-

Pad set-up time Output Differential Voltage Output voltage high Output voltage low Output Offset Voltage

tSET_LVDS
CC
VOD CC
VOH CC
VOL CC
VOS CC

250 925 1125

default after start-up = CMOS function

Values Typ. 100 -

Max. 140 2.5

-

2.5

10

13

-

400

-

1475

-

-

-

1275

Unit Note / Test Condition

Ohm ns
ns
µs

Zload = 100 Ohm;
termination 100 Ohm ±1%
Zload = 100 Ohm;
termination 100 Ohm ±1%

mV termination 100 Ohm ±1%
mV termination 100 Ohm ±1%
mV termination 100 Ohm ±1%
mV termination 100 Ohm ±1%

Data Sheet

3-349

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationVADC Parameters

3.8

VADC Parameters

VADC parameter are valid for VDDM = 4.5 V to 5.5 V.
This table also covers the parameters for Class D pads.

Table 3-27 VADC Parameter
Analog reference voltage 1)
Analog reference ground
Analog input voltage range Converter reference clock Charge consumption per conversion 2) 3)

Symbol
VAREF SR
VAGND SR
VAIN SR fADCI SR QCONV CC

Min.
VAGND +
1.0
VSSM -
0.05
VAGND
2
-

Values Typ. -
-
50

Max.
VDDM +
0.05
VSSM +
0.05
VAREF
20
75

-

10

22

Conversion time for 12-bit result

tC12 CC

-

Conversion time for 10-bit result

tC10 CC

-

Conversion time for 8-bit result tC8 CC

-

Conversion time for fast compare mode

tCF CC

-

Broken wire detection delay
against VAGND 4)
Broken wire detection delay
against VAREF 5)
Input leakage at analog inputs

tBWG CC tBWR CC IOZ1 CC

-350

(16 +

-

STC) x

tADCI + 2 x tVADC

(14 +

-

STC) x

tADCI + 2 x tVADC

(12 +

-

STC) x

tADCI + 2 x tVADC

(4 + STC) -

x tADCI + 2 x tVADC

-

120

-

60

-

350

-150

-

150

Total Unadjusted Error 1)

TUE CC -4 6)

-

4 6)

Unit Note / Test Condition

V

V

V MHz pC
pC

VAIN = 5 V, charge
consumed from reference pin, precharging disabled
VAIN = 5 V, charge
consumed from reference pin, precharging enabled
Includes sample time and post calibration

Includes sample time

Includes sample time

Includes sample time
cycles Result below 10%
cycles Result above 80%
nA Analog Inputs overlaid with class LP pads or pull down diagnostics
nA else LSB 12-bit resolution

Data Sheet

3-350

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Table 3-27 VADC (cont'd) Parameter

Symbol

INL Error Gain Error 1) DNL error 1) Offset Error 1)
Total capacitance of an analog input

EAINL CC EAGAIN CC EADNL CC EAOFF CC CAINT CC

Switched capacitance of an analog input

CAINS CC

Resistance of the analog input RAIN CC
path

Min. -3 -3.5 -3 -4 -
2
-

Switched capacitance of a reference input RMS Noise 7)
Positive reference VAREFx pin
leakage

CAREFS CC -

ENRMS CC -

IOZ2 CC

-7

-4

-2

-1

Negative reference VAGNDx pin IOZ3 CC

-13

leakage

-7

-4.5

-2.5

Resistance of the reference input path CSD resistance 9)

RAREF CC RCSD CC -

Electrical SpecificationVADC Parameters

Values Typ. -

Max. 3 3.5 3 4 30

Unit Note / Test Condition
LSB 12-bit resolution LSB 12-bit resolution LSB 12-bit resolution LSB 12-bit resolution pF

4

7

pF

-

1.5

kOhm else

-

1.8

kOhm valid for analog inputs

mapped to GPIOs

-

30

pF

0.5

0.8 6)8)

LSB

-

7

µA

VAREFx = VAREF2;

VAREF>VDDMV;

TJ>150°C

-

4

µA

VAREFx = VAREF2;

VAREF>VDDMV;

TJ150°C

-

3

µA

VAREFx = VAREF2;

VAREFVDDMV;

TJ>150°C

-

1

µA

VAREFx = VAREF2;

VAREFVDDMV;

TJ150°C

-

13

µA

VAGNDx = VAGND2;

VAGND<VSSMV;

TJ>150°C

-

7

µA

VAGNDx = VAGND2;

VAGND<VSSMV;

TJ150°C

-

2.5

µA

VAGNDx = VAGND2;

VAREFVDDMV;

TJ>150°C

-

1

µA

VAGNDx = VAGND2;

VAREFVDDMV;

TJ150°C

-

1

kOhm

-

28

kOhm

Data Sheet

3-351

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationVADC Parameters

Table 3-27 VADC (cont'd)

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ.

Max.

Resistance of the multiplexer diagnostics pull-down device
Resistance of the multiplexer diagnostics pull-up device
Resistance of the pull-down test device 10) CSD voltage accuracy 11) 12)

RMDD CC RMDU CC

25 + 1*VIN -

-5 +

-

13*VIN

45 - 6*VIN -

RPDD CC

40 - 4*VIN -

-

-

dVCSD CC -

-

35 - 8*VIN
15 +
16*VIN
90 -
16*VIN 65 - 6*VIN
0.3

kOhm kOhm
kOhm
kOhm kOhm

0 V  VIN  2.5 V 2.5 V  VIN  VDDM
0 V  VIN  2.5 V
2.5 V  VIN  VDDM

10

%

Wakeup time

tWU CC

-

-

12

µs

1) If the reference voltage is reduced by the factor k (k < 1), TUE,DNL,INL,Gain, and Offset errors increase also by the factor 1/k. VAREF must be decoupled with an external capacitor.
2) For QCONV = X pC and a conversion time of 1 µs a rms value of X µA results for IAREFx. 3) For the details of the mapping for a VADC group to pin VAREFx please see the User's Manual. 4) The broken wire detection delay against VAGND is measured in numbers of consecutive precharge cycles at a conversion
rate higher than 1 conversion per 500 ms.

5) The broken wire detection delay against VAREF is measured in numbers of consecutive precharge cycles at a conversion rate higher than 1 conversion per 10 ms. This function is influenced by leakage current, in particular at high temperature.

6) Resulting worst case combined error is arithmetic combination of TUE and ENRMS. 7) This parameter is valid for soldered devices and requires careful analog board design.

8) Value is defined for one sigma Gauss distribution.

9) In order to avoid an additional error due to incomplete sampling, the sampling time shall be set greater than 5 * RCSD * CAINS.
10) The pull-down resistor RPDD is connected between the input pad and the analog multiplexer. The input pad itself adds another 200-Ohm series resistance, when measuring through the pin.

11) CSD: Converter Self Diagnostics, for details please consult the User's Manual.

12) Note, that in case CSD voltage is chosen to nom. 1/3 or 2/3 of VAREF voltage, the reference voltage is loaded with a current of max. VAREF / 45 kOhm.

The following VADC parameter are valid for VDDM = 2.97 V to 4.5 V.
This table also covers the parameters for Class D pads.

Table 3-28 VADC_33V Parameter
Analog reference voltage 1)
Analog reference ground
Analog input voltage range Converter reference clock

Symbol
VAREF SR VAGND SR VAIN SR fADCI SR

Min.
VAGND +
1.0
VSSM -
0.05
VAGND
2

Values Typ. -
-
-

Max.
VDDM +
0.05
VSSM +
0.05
VAREF
20

Unit Note / Test Condition
V V V MHz

Data Sheet

3-352

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Table 3-28 VADC_33V (cont'd)

Parameter

Symbol

Charge consumption per conversion 2) 3)

QCONV CC

Min. -

-

Conversion time for 12-bit result

tC12 CC

-

Conversion time for 10-bit result

tC10 CC

-

Conversion time for 8-bit result tC8 CC

-

Conversion time for fast compare mode

tCF CC

-

Broken wire detection delay
against VAGND 4)
Broken wire detection delay
against VAREF 5)
Input leakage at analog inputs

tBWG CC tBWR CC IOZ1 CC

-350

Total Unadjusted Error 1) INL Error Gain Error 1)

TUE CC

-150 -12 6)

-6 6)

EAINL CC -12
-5

EAGAIN CC -6
-5.5

Electrical SpecificationVADC Parameters

Values Typ. 35

Max. 50

8

17

(16 +

-

STC) x

tADCI + 2 x tVADC

(14 +

-

STC) x

tADCI + 2 x tVADC

(12 +

-

STC) x

tADCI + 2 x tVADC

(4 + STC) -

x tADCI + 2 x tVADC

-

120

-

60

-

350

-

150

-

12 6)

-

6 6)

-

12

-

5

-

6

-

5.5

Unit Note / Test Condition

pC

VAIN = 3.3 V, charge

consumed from

reference pin,

precharging disabled

pC

VAIN = 3.3 V, charge

consumed from

reference pin,

precharging enabled

Includes sample time and post calibration

Includes sample time

Includes sample time

Includes sample time
cycles Result below 10%
cycles Result above 80%
nA Analog Inputs overlaid with class LP pads or pull down diagnostics
nA else
LSB 12-bit Resolution; TJ >
150 °C
LSB 12-bit Resolution; TJ 
150 °C
LSB 12-bit Resolution; TJ >
150 °C
LSB 12-bit Resolution; TJ 
150 °C
LSB 12-bit Resolution; TJ >
150 °C
LSB 12-bit Resolution; TJ 
150 °C

Data Sheet

3-353

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Table 3-28 VADC_33V (cont'd)

Parameter

Symbol

DNL error 1) Offset Error 1)

EADNL CC EAOFF CC

Min. -4 -6

-5

Total capacitance of an analog CAINT CC -
input

Switched capacitance of an analog input

CAINS CC 2

Resistance of the analog input RAIN CC -
path

Switched capacitance of a reference input

CAREFS CC -

RMS Noise 7)
Positive reference VAREFx pin
leakage

ENRMS CC -

IOZ2 CC

-6

-3.5

-2

-1

Negative reference VAGNDx pin IOZ3 CC

-12

leakage

-6.5

-2.2

-1

Resistance of the reference input path CSD resistance 9)

RAREF CC RCSD CC -

Electrical SpecificationVADC Parameters

Values Typ. -

Max. 4 6

-

5

-

30

Unit Note / Test Condition
LSB 12-bit resolution
LSB 12-bit Resolution; TJ >
150 °C
LSB 12-bit Resolution; TJ 
150 °C pF

4

7

pF

-

4.5

kOhm

-

30

pF

-

1.7 6)8) LSB target

-

6

µA

VAREFx = VAREF2;

VAREF>VDDMV;

TJ>150°C

-

3.5

µA

VAREFx = VAREF2;

VAREF>VDDMV;

TJ150°C

-

2.5

µA

VAREFx = VAREF2;

VAREFVDDMV;

TJ>150°C

-

1

µA

VAREFx = VAREF2;

VAREFVDDMV;

TJ150°C

-

12

µA

VAGNDx = VAGND2;

VAGND<VSSMV;

TJ>150°C

-

6.5

µA

VAGNDx = VAGND2;

VAGND<VSSMV;

TJ150°C

-

2

µA

VAGNDx = VAGND2;

VAREFVDDMV;

TJ>150°C

-

1

µA

VAGNDx = VAGND2;

VAREFVDDMV;

TJ150°C

-

3

kOhm

-

28

kOhm

Data Sheet

3-354

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationVADC Parameters

Table 3-28 VADC_33V (cont'd)

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ.

Max.

Resistance of the multiplexer RMDD CC
diagnostics pull-down device
Resistance of the multiplexer RMDU CC
diagnostics pull-up device

25 + 3*VIN -

0 + 18*VIN -

60 -

-

12*VIN

55 - 9*VIN -

Resistance of the pull-down RPDD CC -

-

test device 10)

CSD voltage accuracy 11) 12) dVCSD CC -

-

40 +

kOhm

12*VIN

0 + 18*VIN kOhm

120 -

kOhm

30*VIN

95 -

kOhm

15*VIN

0.9

kOhm

0 V  VIN  1.667 V
1.667 V  VIN  VDDM 0 V  VIN  1.667 V
1.667 V  VIN  VDDM

10

%

Wakeup time

tWU CC

-

-

12

µs

1) If the reference voltage is reduced by the factor k (k < 1), TUE,DNL,INL,Gain, and Offset errors increase also by the factor

1/k. VAREF must be decoupled with an external capacitor.

2) For QCONV = X pC and a conversion time of 1 µs a rms value of X µA results for IAREFx.

3) For the details of the mapping for a VADC group to pin VAREFx please see the User's Manual.

4) The broken wire detection delay against VAGND is measured in numbers of consecutive precharge cycles at a conversion rate higher than 1 conversion per 500 ms.

5) The broken wire detection delay against VAREF is measured in numbers of consecutive precharge cycles at a conversion rate higher than 1 conversion per 10 ms. This function is influenced by leakage current, in particular at high temperature.

6) Resulting worst case combined error is arithmetic combination of TUE and ENRMS. 7) This parameter is valid for soldered devices and requires careful analog board design.

8) Value is defined for one sigma Gauss distribution.

9) In order to avoid an additional error due to incomplete sampling, the sampling time shall be set greater than 5 * RCSD * CAINS.
10) The pull-down resistor RPDD is connected between the input pad and the analog multiplexer. The input pad itself adds another 200-Ohm series resistance, when measuring through the pin.

11) CSD: Converter Self Diagnostics, for details please consult the User's Manual.

12) Note, that in case CSD voltage is chosen to nom. 1/3 or 2/3 of VAREF voltage, the reference voltage is loaded with a current of max. VAREF / 45 kOhm.

V AIN

RSource

C Ext

RAIN, On

A/D Converter

C AINT - C AINS

CAINS

Figure 3-2 Equivalent Circuitry for Analog Inputs

MCS05570

Data Sheet

3-355

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationDSADC Parameters

3.9

DSADC Parameters

The following DSADC parameter are valid for VDDM = 4.5 V to 5.5 V.

Table 3-29 DSADC Parameter

Symbol

Analog input voltage range 1) VDSIN SR

Min. 0 0

Values Typ. -

Max. 5 10

Reference load current

IREF SR

-

4.5

Modulator clock frequency 2) fMOD SR

10

-

Gain error

EDGAIN CC -1

-

-3.5 4)

-

-0.2

-

5.5
20 1 3) 3.5 4) 0.2 5)

DC offset error

EDOFF CC -5

-

-50

-

-100 4)

04)

Common Mode Rejection Ratio EDCM CC 200

500

Input impedance 6)

RDAIN CC 100

130

Signal-Noise Ratio 7) 8) 9) 10) SNR CC 80

-

5 5) 50 100 4) 170
-

78

-

-

70

-

-

74

-

-

76

-

-

74

-

-

Pass band
Pass band ripple 8) Output sampling rate

fPB CC

10 11)

-

100

dfPB CC

-1

-

1

fD CC

30

-

330

Unit Note / Test Condition

V V
µA
MHz % % %
mV mV mV

single ended
differential;VDSxP VDSxN
per twin-modulator (1 or 2 channels)
Calibrated once Uncalibrated calibrated; GAIN = 1; MODCFG.INCFGx=01 calibrated calibrated once gain = 1; uncalibrated

kOhm dB dB dB dB dB dB kHz % kHz

Exact value (±1%) available in UCB
fPB = 30 kHz; VDDM = ±5%; fMOD = 20 MHz;
GAIN = 1
fPB = 50 kHz; VDDM = ±5%; fMOD = 20 MHz;
GAIN = 1
fPB = 100 kHz; VDDM = ±10%; fMOD = 20 MHz;
GAIN = 1
fPB = 100 kHz; VDDM = ±5%; fMOD = 20 MHz;
GAIN = 1
fPB = 30 kHz; VDDM = ±10%; fMOD = 20 MHz;
GAIN = 1
fPB = 50 kHz; VDDM = ±10%; fMOD = 20 MHz;
GAIN = 1
Output data rate fD = fPB * 3

Data Sheet

3-356

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationDSADC Parameters

Table 3-29 DSADC (cont'd)

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ.

Max.

DC compensation factor

DCF CC -3

-

Positive reference VAREF1 pin IOZ5 CC

-2

-

leakage

-

dB

10-5 fD

2

µA

Negative reference VAGND1 pin IOZ6 CC

-3

-

leakage

Stop band attenuation 8)

SBA CC 40

-

45

-

50

-

55

-

60

-

Reference ground voltage

VAGND SR VSSM -

-

0.05

2

µA

-

dB

-

dB

-

dB

-

dB

-

dB

VSSM +

V

0.05

0.5 ... 1 fD 1 ... 1.5 fD 1.5 ... 2 fD 2 ... 2.5 fD 2.5 ... OSR/2 fD

Positive reference voltage

VAREF SR

VDDMnom * -
0.9

VDDM + V
0.05

Common mode voltage accuracy

dVCM CC -100

-

100

mV from selected voltage

Common mode hold voltage dVCMH CC -200

-

deviation 12)

200

mV From common mode

voltage

Analog filter settling time Modulator recovery time

tAFSET CC tMREC CC -

2

4

µs

If enabled

3.5

5.5

µs

After leaving overdrive

state

Modulator settling time 13)

tMSET CC -

1

-

µs

After switching on,

voltage regulator

already running

Spurious Free Dynamic Range SFDR CC 60

-

-

dB

VCM = 2.2 V, DC

7)14)

coupled; VDDM = ±10%

1) The maximum input range for symmetrical signals (e.g. AC-coupled inputs) depends on the selected internal/external

common mode voltage. In this case the Amplitude is limited to VCM * 2.

2) All modulators must run on the same frequency.

3) The calibration sequence must be executed once after an Application Reset

4) The total DC error for the uncalibrated case can be calculated by the geometric addition of EDGAIN and EDOFF 5) Recalibration needed in case of a temperature change > 20ºC

6) The variation of the impedance between different channels is < 1.5%.

7) Derating factors: -2 dB in standard-performance mode. -3 dB for CMV = 10B, i.e. VCM = (VAREF±2%) / 2.0.
8) CIC3, FIR0, FIR1 filters enabled.

9) Single-ended mode reduces the SNR by 6 dB if the unused input is grounded, by 3 dB if the unused input connects to VCM (GAIN = 2).

10) The defined limits are only valid if the following condition is not applicable: TJ > 150°C and VVAREF > VDDM. 11) 10 kHz only reachable with 10 MHz modulator clock frequency.

12) Voltage VCM is proportional to VAREF, voltage VCMH is proportional to VDDM. 13) The modulator needs to settle after being switched on and after leaving the overdrive state. 14) SFDR = 20 * log(INL / 2N); N = amount of bits

Data Sheet

3-357

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationDSADC Parameters

The following DSADC parameter are valid for VDDM = 2.97 V to 4.5 V.

Table 3-30 DSADC_33V Parameter

Symbol

Analog input voltage range 1) VDSIN SR

Min. 0 0

Values Typ. -

Max. 3.3 6.6

Reference load current

IREF SR

-

4.5

Modulator clock frequency 2) fMOD SR

10

-

Gain error

EDGAIN CC -1.5

-

-10 4)

-

-0.3

-

5.5
20 1.5 3) 10 4) 0.3 5)

DC offset error

EDOFF CC -5

-

-50

-

-100 4)

04)

Common Mode Rejection Ratio EDCM CC 200

500

Input impedance 6)

RDAIN CC 100

130

Signal-Noise Ratio 7) 8) 9) 10) SNR CC 45

63

5 5) 50 100 4) 170
-

60

69

-

60

68

-

69

74

-

55

66

-

65

72

-

Pass band

fPB CC

10 11)

-

100

Pass band ripple 8)

dfPB CC

-1

-

1

Output sampling rate

fD CC

30

-

330

DC compensation factor

DCF CC -3

-

-

Unit Note / Test Condition

V V
µA
MHz % % %
mV mV mV

single ended
differential;VDSxP VDSxN
per twin-modulator (1 or 2 channels)
Calibrated once Uncalibrated calibrated; GAIN = 1; MODCFG.INCFGx=01 calibrated calibrated once gain = 1; uncalibrated

kOhm dB
dB
dB
dB
dB
dB
kHz % kHz dB

Exact value (±1%) available in UCB
fPB = 100kHz; VDDM = ±10%; fMOD = 20 MHz;
GAIN = 1
fPB = 100kHz; VDDM = ±5%; fMOD = 20 MHz;
GAIN = 1
fPB = 30kHz; VDDM = ±10%; fMOD = 20 MHz;
GAIN = 1
fPB = 30kHz; VDDM = ±5%; fMOD = 20 MHz;
GAIN = 1
fPB = 50kHz; VDDM = ±10%; fMOD = 20 MHz;
GAIN = 1
fPB = 50kHz; VDDM = ±5%; fMOD = 20 MHz;
GAIN = 1
Output data rate fD = fPB * 3
10-5 fD

Data Sheet

3-358

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationDSADC Parameters

Table 3-30 DSADC_33V (cont'd)

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ.

Max.

Positive reference VAREF1 pin IOZ5 CC

-2

-

leakage

2

µA

Negative reference VAGND1 pin IOZ6 CC

-3

-

leakage

Stop band attenuation 8)

SBA CC 40

-

45

-

50

-

55

-

60

-

Reference ground voltage

VAGND SR VSSM -

-

0.05

2

µA

-

dB

-

dB

-

dB

-

dB

-

dB

VSSM +

V

0.05

0.5 ... 1 fD 1 ... 1.5 fD 1.5 ... 2 fD 2 ... 2.5 fD 2.5 ... OSR/2 fD

Positive reference voltage

VAREF SR

VDDMnom * -
0.9

VDDM + V
0.05

Common mode voltage accuracy

dVCM CC -100

-

100

mV from selected voltage

Common mode hold voltage dVCMH CC -200

-

deviation 12)

200

mV From common mode

voltage

Analog filter settling time Modulator recovery time

tAFSET CC tMREC CC -

2

4

3.5

-

µs

If enabled

µs

After leaving overdrive

state

Modulator settling time 13)

tMSET CC -

1

-

µs

After switching on,

voltage regulator

already running

Spurious Free Dynamic Range SFDR CC 52

-

-

dB

VCM = 2.2 V, DC

7)14)

coupled; VDDM = ±10%

60

-

-

dB

VCM = 2.2 V, DC

coupled; VDDM = ±5%

1) The maximum input range for symmetrical signals (e.g. AC-coupled inputs) depends on the selected internal/external common mode voltage. In this case the Amplitude is limited to VCM * 2.
2) All modulators must run on the same frequency.

3) The calibration sequence must be executed once after an Application Reset

4) The total DC error for the uncalibrated case can be calculated by the geometric addition of EDGAIN and EDOFF 5) Recalibration needed in case of a temperature change > 20ºC.

6) The variation of the impedance between different channels is < 1.5%.

7) Derating factors: -2 dB in standard-performance mode. -3 dB for CMV = 10B, i.e. VCM = (VAREF±2%) / 2.0.
8) CIC3, FIR0, FIR1 filters enabled.

9) Single-ended mode reduces the SNR by 6 dB if the unused input is grounded, by 3 dB if the unused input connects to VCM (GAIN = 2).

10) The defined limits are only valid if the following condition is not applicable: TJ > 150°C and VVAREF > VDDM. 11) 10 kHz bandwidth only with 10Mhz modulator clock frequency reachable

12) Voltage VCM is proportional to VAREF, voltage VCMH is proportional to VDDM. 13) The modulator needs to settle after being switched on and after leaving the overdrive state.

Data Sheet

3-359

V 1.0 2017-03

Input
37 k 37 k

14) SFDR = 20 * log(INL / 2N); N = amount of bits
130 k 130 k
Figure 3-3 DSADC Analog Inputs

TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationDSADC Parameters

VCM
Gain

V OFFSET
=

Modu lator

Gain
MC_DSADC_MODULATORBLOCK

Data Sheet

3-360

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationMHz Oscillator

3.10

MHz Oscillator

OSC_XTAL is used as accurate and exact clock source. OSC_XTAL supports 8 MHz to 40 MHz crystals external outside of the device. Support of ceramic resonators is also provided.

Table 3-31 OSC_XTAL

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ.

Max.

Input current at XTAL1 Oscillator frequency

IIX1 CC

-25

-

fOSC SR

4

-

25

µA

VIN>0V; VIN<VDDP3V

40

MHz Direct Input Mode

selected

8

-

Oscillator start-up time 1)

tOSCS CC -

-

Input high voltage at XTAL1 VIHBX SR 0.8

-

40
5 2)
VDDP3 +
0.5

MHz
ms V

External Crystal Mode selected
If shaper is bypassed

Input low voltage at XTAL1

VILBX SR -0.5

-

Input voltage at XTAL1

VIX SR

-0.5

-

0.4

V

VDDP3 + V
0.5

If shaper is bypassed
If shaper is not bypassed

Input amplitude (peak to peak) VPPX SR 0.3 *

-

at XTAL1

VDDP3

VDDP3 + V
1.0

If shaper is not
bypassed; fOSC >
25MHz

0.4 *

-

VDDP3

VDDP3 + V
1.0

If shaper is not
bypassed; fOSC 
25MHz

Internal load capacitor

CL0 CC

2

2.35

2.7

pF

Internal load capacitor

CL1 CC

2

2.35

2.7

pF

Internal load capacitor

CL2 CC

3

3.5

4

pF

Internal load capacitor

CL3 CC

5.1

5.9

6.6

pF

1) tOSCS is defined from the moment when VDDP3 = 3.13V until the oscillations reach an amplitude at XTAL1 of 0.3 * VDDP3. The external oscillator circuitry must be optimized by the customer and checked for negative resistance as recommended

and specified by crystal suppliers.

2) This value depends on the frequency of the used external crystal. For faster crystal frequencies this value decrease.

Note: It is strongly recommended to measure the oscillation allowance (negative resistance) in the final target system (layout) to determine the optimal parameters for the oscillator operation. Please refer to the limits specified by the crystal or ceramic resonator supplier.

Data Sheet

3-361

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationBack-up Clock

3.11

Back-up Clock

The back-up clock provides an alternative clock source.

Table 3-32 Back-up Clock

Parameter

Symbol

Min.

Back-up clock before trimming Slow speed Back-up clock Back-up clock after trimming

fBACKUT CC fBACKSS CC fBACKT CC

75 75 97.5

Values Typ. 100 100 100

Max. 125 125 102.5

Unit Note / Test Condition

MHz kHz MHz

VEXT2.97V VEXT2.97V VEXT2.97V

Data Sheet

3-362

V 1.0 2017-03

3.12

Temperature Sensor

TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationTemperature Sensor

Table 3-33 DTS

Parameter

Symbol

Min.

Measurement time

tM CC

-

Calibration reference accuracy TCALACC CC -1

Non-linearity accuracy over TNL CC

-2

temperature range

Temperature sensor range
Start-up time after resets inactive

TSR SR

-40

tTSST SR

-

Values Typ. -

Max. 100 1

-

2

-

170

-

20

Unit Note / Test Condition

µs

°C

calibration points @

TJ=-40°C and TJ=127°C

°C

°C µs

The following formula calculates the temperature measured by the DTS in [oC] from the RESULT bit field of the DTSSTAT register.
(3.1)
Tj = -D----T----S-----S----T----A----T----R-----E----S-----U----L----T-----­-----(--6----0---7----) 2, 13

Data Sheet

3-363

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationPower Supply Current

3.13

Power Supply Current

The total power supply current defined below consists of leakage and switching component.

Application relevant values are typically lower than those given in the following table and depend on the customer's system operating conditions (e.g. thermal connection or used application configurations).

The operating conditions for the parameters in the following table are:

The real (realisic) power pattern defines the following conditions:

· TJ = 150 °C · fCPU0 = 200 MHz · fSRI = fMAX = fCPU1 = fCPU2 300 MHz · fSPB = fSTM = fGTM = fBAUD1 = fBAUD2 = fASCLIN = 50 MHz · VDD = 1.326 V · VDDP3 = 3.366 V · VEXT / FLEX = VDDM = 5.1 V
· all cores are active including one lockstep core

· the following peripherals are inactive: EBU, HSM, HSCT, Ethernet, PSI5, I2C, FCE, MTU, and 50% of the DSADC channels

The max power pattern defines the following conditions:

· TJ = 150 °C · fCPU0 = 200 MHz · fSRI = fMAX = fCPU1 = fCPU2 300 MHz · fSPB = fSTM = fGTM = fBAUD1 = fBAUD2 = fASCLIN = 100 MHz · VDD = 1.43 V · VDDP3 = 3.63 V · VEXT / FLEX = VDDM = 5.5 V
· all cores and lockstep cores are active

· all peripherals are active

Data Sheet

3-364

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationPower Supply Current

Table 3-34 Power Supply Parameter

Symbol

 Sum of IDD 1.3 V core and IDD CC
peripheral supply currents

Min. -

-

-

Values Typ. -

Max. 750

-

800

-

950

-

930

-

567

-

637

Unit Note / Test Condition
mA max power pattern
with fSRI/CPUx = 270 MHz with VDD = 1.3V +
10%; valid for Feature Package T, TP, and TC products
mA max power pattern with fSRI/CPUx = 300 MHz with VDD = 1.33V + 7.5%. valid for Feature Package T, TP, and TC products
mA max power pattern. valid for Feature Package TA and TB products
mA max power pattern. valid for Feature Package TX and TY products
mA real power pattern. valid for Feature Package T, TP, and TC products
mA real power pattern. valid for Feature Package TA, TB, TX and TY products

Data Sheet

3-365

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Table 3-34 Power Supply (cont'd)

Parameter

Symbol

IDD core current during active
power-on reset (PORST held
low)

IDDPORST
CC

Min. -

-

-

-

-

-

IDD core current of CPU1 main IDDC10 CC -
core with CPU1 lockstep core inactive
IDD core current of CPU1 main IDDC11 CC -
core with lockstep core active
IDD core current of CPU2 main IDDC20 CC -
core
IDD core current added by HSM IDDHSM CC -

IDD core current added by AMU IDDAMU CC IDD core current added by FFT IDDFFT CC -

 Sum of 3.3 V supply currents IDDx3RAIL CC -
without pad activity

IDDFL3 Flash memory current

IDDFL3 CC -
-

Electrical SpecificationPower Supply Current

Values Typ. -

Max. 140

-

220

-

176

-

310

-

290

-

405

-

62

Unit Note / Test Condition
mA valid for Feature Package T, TP, and TC products;
TJ=125°C
mA valid for Feature Package T, TP, and TC products;
TJ=150°C
mA valid for Feature Package TA, TB, TX, and TY products;
TJ=125°C
mA valid for Feature Package T, TP, and TC products;
TJ=165°C
mA valid for Feature Package TA, TB, TX, and TY products;
TJ=150°C
mA valid for Feature Package TA, TB, TX, and TY products;
TJ=165°C
mA real power pattern

-

IDDC10 + mA real power pattern

48

-

60

mA real power pattern

-

20

mA HSM running at

100MHz.

-

48

mA real power pattern

-

40

mA FFT running at

200MHz

-

104 1)

mA real power pattern

-

84 2)

mA flash read current

-

84 3)

mA flash read current

while programming Dflash

Data Sheet

3-366

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationPower Supply Current

Table 3-34 Power Supply (cont'd)

Parameter

Symbol

IDDP3 supply current without
pad activity

IDDP3 CC

Min. -

-

-

Values Typ. -

Max. 29 2)

-

46 3)

-

46 4)

IDDP3 supply current for LVDSH IDDP3LVDSH -

-

16

pads in LVDS mode

CC

 Sum of external and ADC IEXTRAIL CC -

-

98

supply currents (incl.

IEXTFLEX+IDDM+IEXTLVDSM)

Sum of IEXT and IFLEX supply IEXT/FLEX CC -

-

16

current without pad activity

IEXT supply current for LVDSM IEXTLVDSM -

-

20 5)

pads in LVDS mode

CC

IDDM supply current

IDDM CC

-

-

62

-

-

52

-

-

100 6)

-

-

10

-

-

20 7)

 Sum of all currents (incl.

IDDTOT CC -

-

770

IEXTRAIL+IDDx3RAIL+IDD)

-

-

840

Data Sheet

3-367

Unit Note / Test Condition
mA real power pattern; incl. OSC & flash read current
mA incl. OSC and flash programming current
mA incl. OSC current and flash 3.3V programming current when using external 5V supply
mA
mA real power pattern
mA real power pattern; PORST output inactive.
mA real power pattern
mA real power pattern; sum of currents of DSADC and VADC modules
mA current for DSADC module only; 50% DSADC channels active.
mA max power pattern; All DSADC channels active 100% time.
mA real pattern; current for VADC only
mA max power pattern; All VADC converters are active 100% time
mA real power pattern; valid for Feature Package T, TP, and TC products
mA real power pattern; valid for Feature Package TA, TB, TX, and TY products
V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationPower Supply Current

Table 3-34 Power Supply (cont'd)

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ.

Max.

 Sum of all currents with DC- IDDTOTDC3 -

-

460

mA real power pattern;

DC EVR13 regulator active 8) CC

VEXT = 3.3V

 Sum of all currents with DC- IDDTOTDC5 -

-

370

mA real power pattern;

DC EVR13 regulator active 8) CC

VEXT = 5V

 Sum of all currents (STANDBY mode)

IEVRSB CC -

-

150 9)

µA

Standby RAM is

active. Power to

remaining domains

switched off. TJ = 25°C; VEVRSB = 5V

 Sum of all currents (SLEEP ISLEEP CC -

-

24

mA All CPUs in idle, All

mode)

peripherals in sleep,

fSRI/SPB = 1 MHz via LPDIV divider; TJ = 25°C; valid for Feature

Package T, TP, and

TC products

-

-

26

mA All CPUs in idle, All

peripherals in sleep,

fSRI/SPB = 1 MHz via LPDIV divider; TJ = 25°C; valid for Feature

Package TA, TB, TX,

and TY products

Maximum power dissipation PD CC

-

-

2382

mW max power pattern ;

valid for Feature

Package TA and TB

products

-

-

2140

mW max power pattern.

valid for Feature

Package T, TP, and

TC products

-

-

2350

mW max power pattern.

valid for Feature

Package TX and TY

products

-

-

1600

mW real power pattern.

valid for Feature

Package T, TP, and

TC products

-

-

1700

mW real power pattern.

valid for Feature

Package TA, TB, TX,

and TY products

1) In case EVR33 is not used, Injection current into 3.3V VDDP3 supply rail with active sink on 5V VEXT rail should be limited to 500 mA if during power sequencing 3.3V is supplied before 5V by external regulator.

Data Sheet

3-368

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationPower Supply Current

2) Realistic Pflash read pattern with 70% Pflash bandwidth utlilization and a code mix of 50% 0s and 50% 1s. A common decoupling capacitor of atleast 100nF for (VDDFL3+VDDP3) is used. Dflash read current is also included. Flash read current is predominantly drawn from VDDFL3 pin and a minor part drawn from the neighbouring VDDP3 pin.
3) Continuous Dflash programming in burst mode with 3.3 V supply and realistic Pflash read access in parallel. Erase currents of the corresponding flash modules are less than the respective programming currents at VDDP3 pin. Programming and erasing flash may generate transient current spikes of up to x mA for maximum x us which is handled by the decoupling and buffer capacitors. This parameter is relevant for external power supply dimensioning and not for thermal considerations.
4) In addition to the current specified, upto 4 mA is additionally drawn at VEXT supply in burst programming mode with 5V external supply. Erase currents of the corresponding flash modules are less than the respective programming currents at VDDP3 supply. This parameter is relevant for external power supply dimensioning and not for thermal considerations.
5) The current consumption is for 2 pairs of LVDSM differential pads (8 pins). A single pair of LVDSM differential pads (4 pins) consumes 7 mA.
6) The current consumption is for 6 DS channels with standard performance (MCFG=11b). A single DS channel instance consumes 6-8 mA.
7) A single converter instance of VADC unit consumes 2 mA.
8) The total current drawn from external regulator is estimated with 72% EVR13 SMPS regulator Efficiency. IDDTOTDCx is calculated from IDDTOT using the scaled core current [(IDD x VDD)/(VinxEfficiency)] and constitutes all other rail currents and IDDM.
9)  Sum of all currents during RUN mode at VEVRSB supply pin is less than (8 mA + ISCRSB) . It is recommended to have atleast 100 nF decoupling capacitor at this pin.

3.13.1 Calculating the 1.3 V Current Consumption
The current consumption of the 1.3 V rail compose out of two parts: · Static current consumption · Dynamic current consumption The static current consumption is related to the device temperature TJ and the dynamic current consumption depends of the configured clocking frequencies and the software application executed. These two parts needs to be added in order to get the rail current consumption. Valid for Feature Package T, TP, and TC products:

(3.2)

I0

=

0, 894

m------A-C

× e0, 0289 × TJ[C]

I0

=

4, 319

m------A-C

× e0, 0259 × TJ[C]

(3.3)

Valid for Feature Package TA, TB, TX, and TY products:

I0

=

2, 731

m------A-C

× e0, 0244 × TJ[C]

(3.4)

I0

=

5, 832

m------A-C

× e0, 0257 × TJ[C]

(3.5)

Data Sheet

3-369

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationPower Supply Current Function 2 / 4 defines the typical static current consumption and Function 3 / 5 defines the maximum static current consumption. Both functions are valid for VDD = 1.326 V.

Data Sheet

3-370

V 1.0 2017-03

3.14

Power-up and Power-down

TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationPower-up and Power-down

3.14.1 External Supply Mode
5 V & 1.3 V supplies are externally supplied. 3.3V is generated internally by EVR33.
· External supplies VEXT and VDD may ramp-up or ramp-down independent of each other with regards to start, rise and fall time(s). Voltage Ramp-up from a residual threshold (Eg : up to 1 V) should also lead to a normal startup of the device.
· The rate at which current is drawn from the external regulator (dIEXT /dt or dIDD /dt) is limited in the Start-up phase to a maximum of 50 mA/100 us.
· PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted.
· PORST (input) active means that the reset is held active by external agents by pulling the PORST pin low. It is recommended to keep the PORST (input) asserted until all the external supplies are above their primary reset thresholds.
· PORST (output) active means that µC asserts the reset internally and drives the PORST pin low thus propagating the reset to external devices. The PORST (output) is asserted by the µC when atleast one among the three supply domains (1.3 V, 3.3 V or 5 V) violate their primary under-voltage reset thresholds.The PORST (output) is deasserted by the µC when all supplies are above their primary reset thresholds and the basic supply and clock infrastructure is available.
· The power sequence as shown in Figure 3-4 is enumerated below
­ T1 refers to the point in time when basic supply and clock infrastructure is available as the external supplies ramp up. The supply mode is evaluated based on the HWCFG [0:2] pins and consequently a soft start of EVR33 regulator is initiated.
­ T2 refers to the point in time when all supplies are above their primary reset thresholds. EVR33 regulator has ramped up. PORST (output) is deasserted and HWCFG [0:7] pins are latched on PORST rising edge. Firmware execution is initiated.
­ T3 refers to the point in time when Firmware execution is completed. User code execution starts with a default frequency of 100 MHz.
­ T4 refers to the point in time during the Ramp-down phase when atleast one of the externally provided or generated supplies (1.3 V, 3.3 V or 5 V) drop below their respective primary under-voltage reset thresholds.
Please note that there is no special requirements for PORST slew rates.

Data Sheet

3-371

V 1.0 2017-03

VEXT (externally supplied ) 0
5.5 V 5.0 V 4.5 V
2.97 V Primary Reset Threshold
0 V
VDD (externally supplied )
1.33 V 1.30 V 1.17 V Primary Reset Threshold
0 V
PORST (output ) PORST (input)
VDDP3 (internally generated
by EVR33) 3.63 V 3.30 V 2.97 V
Primary Reset Threshold

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationPower-up and Power-down

1

2

3

4

0 V

T0
Basic Supply & Clock Infrastructure

T1

T2

EVR33 Ramp-up Phase

Firmware Execution

T3
User Code Execution fCPU=100MHz default on firmware exit

T4 Power Ramp-down phase
Startup_Diag_1 v 0.1

Figure 3-4 External Supply Mode - 5 V and 1.3 V externally supplied

Data Sheet

3-372

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationPower-up and Power-down
3.14.2 Single Supply Mode
5 V single supply mode. 1.3 V & 3.3 V are generated internally by EVR13 & EVR33. · The rate at which current is drawn from the external regulator (dIEXT /dt) is limited in the Start-up phase to a
maximum of 50 mA/100 us. · PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted. · PORST (input) active means that the reset is held active by external agents by pulling the PORST pin low. It
is recommended to keep the PORST (input) asserted until the external supply is above the respective primary reset threshold. · PORST (output) active means that µC asserts the reset internally and drives the PORST pin low thus propagating the reset to external devices. The PORST (output) is asserted by the µC when atleast one among the three supply domains (1.3 V, 3.3 V or 5 V) violate their primary under-voltage reset thresholds.The PORST (output) is deasserted by the µC when all supplies are above their primary reset thresholds and the basic supply and clock infrastructure is available. · The power sequence as shown in Figure 3-5 is enumerated below ­ T1 refers to the point in time when basic supply and clock infrastructure is available as the external supply
ramps up. The supply mode is evaluated based on the HWCFG [0:2] pins and consequently a soft start of EVR13 and EVR33 regulators are initiated. ­ T2 refers to the point in time when all supplies are above their primary reset thresholds. EVR13 and EVR33 regulators have ramped up. PORST (output) is deasserted and HWCFG [0:7] pins are latched on PORST rising edge. Firmware execution is initiated. ­ T3 refers to the point in time when Firmware execution is completed. User code execution starts with a default frequency of 100 MHz. ­ T4 refers to the point in time during the Ramp-down phase when atleast one of the externally provided or generated supplies (1.3 V, 3.3 V or 5 V) drop below their respective primary under-voltage reset thresholds. Please note that there is no special requirements for PORST slew rates.

Data Sheet

3-373

V 1.0 2017-03

VEXT (externally supplied ) 0
5.5 V 5.0 V 4.5 V
2.97 V Primary Reset Threshold

0 V

PORST (output ) PORST (input)

VDD (internally generated

1.33 V

by EVR13)

1.30 V

1.17 V Primary Reset Threshold

0 V
VDDP3 (internally generated
by EVR33) 3.63 V 3.30 V 2.97 V
Primary Reset Threshold

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationPower-up and Power-down

1

2

3

4

0 V

T0
Basic Supply & Clock Infrastructure

T1

T2

EVR13 & EVR 33 Ramp-up Phase

Firmware Execution

T3
User Code Execution fCPU=100MHz default on firmware exit

T4 Power Ramp-down phase

Startup_Diag_2 v 0.1

Figure 3-5 Single Supply Mode - 5 V single supply

Data Sheet

3-374

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationPower-up and Power-down
3.14.3 External Supply Mode
All supplies, namely 5 V, 3.3 V & 1.3 V, are externally supplied. · External supplies VEXT ,, VDDP3 & VDD may ramp-up or ramp-down independent of each other with regards
to start, rise and fall time(s). · The rate at which current is drawn from the external regulator (dIEXT /dt, dIDD /dt or dIDDP3 /dt) is limited in
the Start-up phase to a maximum of 50 mA/100 us. · PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted. · PORST (input) active means that the reset is held active by external agents by pulling the PORST pin low. It
is recommended to keep the PORST (input) asserted until all the external supplies are above their primary reset thresholds. · PORST (output) active means that µC asserts the reset internally and drives the PORST pin low thus propagating the reset to external devices. The PORST (output) is asserted by the µC when atleast one among the three supply domains (1.3 V, 3.3 V or 5 V) violate their primary under-voltage reset thresholds.The PORST (output) is deasserted by the µC when all supplies are above their primary reset thresholds and the basic supply and clock infrastructure is available. · The power sequence as shown in Figure 3-6 is enumerated below ­ T1 refers to the point in time when all supplies are above their primary reset thresholds and basic clock
infrastructure is available. The supply mode is evaluated based on the HWCFG [0:2] pins. PORST (output) is deasserted and HWCFG [0:7] pins are latched on PORST rising edge. Firmware execution is initiated. ­ T2 refers to the point in time when Firmware execution is completed. User code execution starts with a default frequency of 100 MHz. ­ T3 refers to the point in time during the Ramp-down phase when atleast one of the externally provided supplies (1.3 V, 3.3 V or 5 V) drop below their respective primary under-voltage reset thresholds. Please note that there is no special requirements for PORST slew rates.

Data Sheet

3-375

V 1.0 2017-03

VEXT (externally supplied ) 0

1

5.5 V 5.0 V 4.5 V

2.97 V Primary Reset Threshold

0 V
VDD (externally supplied )
1.33 V 1.30 V 1.17 V Primary Reset Threshold
0 V
VDDP3 (externally supplied)
3.63 V 3.30 V 2.97 V
Primary Reset Threshold

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationPower-up and Power-down

2

3

0 V

PORST (output ) PORST (input)

T0
Basic Supply & Clock Infrastructure

T1 Firmware Execution

T2
User Code Execution fCPU=100 MHz default on firmware exit

T3 Power Ramp-down phase

Startup_Diag_3 v 0.1

Figure 3-6 External Supply Mode - 5 V, 3.3 V & 1.3 V externally supplied

Data Sheet

3-376

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationPower-up and Power-down
3.14.4 Single Supply Mode
3.3 V single supply mode. 1.3 V is generated internally by EVR13. · The rate at which current is drawn from the external regulator (dIEXT /dt) is limited in the Start-up phase to a
maximum of 50 mA/100 us. · PORST is active/asserted when either PORST (input) or PORST (output) is active/asserted. · PORST (input) active means that the reset is held active by external agents by pulling the PORST pin low. It
is recommended to keep the PORST (input) asserted until the external supply is above the respective primary reset threshold. · PORST (output) active means that µC asserts the reset internally and drives the PORST pin low thus propagating the reset to external devices. The PORST (output) is asserted by the µC when atleast one among the three supply domains (1.3 V or 3.3 V) violate their primary under-voltage reset thresholds.The PORST (output) is deasserted by the µC when all supplies are above their primary reset thresholds and the basic supply and clock infrastructure is available. · The power sequence as shown in Figure 3-7 is enumerated below ­ T1 refers to the point in time when basic supply and clock infrastructure is available as the external supply
ramps up. The supply mode is evaluated based on the HWCFG [0:2] pins and consequently a soft start of EVR13 regulator is initiated. ­ T2 refers to the point in time when all supplies are above their primary reset thresholds. EVR13 regulator has ramped up. PORST (output) is deasserted and HWCFG [0:7] pins are latched on PORST rising edge. Firmware execution is initiated. ­ T3 refers to the point in time when Firmware execution is completed. User code execution starts with a default frequency of 100 MHz. ­ T4 refers to the point in time during the Ramp-down phase when atleast one of the externally provided or generated supplies (1.3 V or 3.3 V) drop below their respective primary under-voltage reset thresholds. Please note that there is no special requirements for PORST slew rates.

Data Sheet

3-377

V 1.0 2017-03

VEXT (externally supplied ) 0 &
VDDP3 (externally supplied )
3.63 V 3.30 V 2.97 V
Primary Reset Threshold

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationPower-up and Power-down

1

2

3

4

0 V
PORST (output ) PORST (input)
VDD (internally generated
by EVR 13) 1.33 V 1.30 V 1.17 V Primary Reset Threshold

0 V

T0
Basic Supply & Clock Infrastructure

T1

T2

EVR13 Ramp-up Phase

Firmware Execution

T3
User Code Execution fCPU=100MHz default on firmware exit

T4 Power Ramp-down phase

Figure 3-7 Single Supply Mode - 3.3 V single supply

Startup_Diag_4 v 0.1

Data Sheet

3-378

V 1.0 2017-03

3.15

Reset Timing

TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationReset Timing

Table 3-35 Reset Timings

Parameter

Symbol

Values

Unit Note / Test Condition

Application Reset Boot Time 1) tB CC

Min. -

Typ. -

Max.

350 2)

µs

operating with max.

frequencies.

System Reset Boot Time

tBS CC

-

-

1

ms

Power on Reset Boot Time 3) tBP CC

-

-

2.5 2)

ms dV/dT=1V/ms.

including EVR ramp-

up and Firmware

execution time

-

-

1.11 2)

ms

Firmware execution

time; without EVR operation (external

supply only)

Minimum PORST hold time tEVRPOR CC 10

-

-

µs

incase of power fail event

issued by EVR primary monitor

EVR start-up or ramp-up time tEVRstartup -

-

1

ms dV/dT=1V/ms. EVR13

CC

and EVR33 active

Minimum PORST active hold tPOA CC

1

-

-

ms

time after power supplies are

stable at operating levels 4)

Configurable PORST digital tPORSTDF CC 600

-

filter delay in addition to analog

pad filter delay

1200

ns

HWCFG pins hold time from tHDH CC

16 / fSPB -

-

ns

ESR0 rising edge

HWCFG pins setup time to

tHDS CC

0

-

-

ns

ESR0 rising edge

Ports inactive after ESR0 reset tPI CC

-

-

8/fSPB

ns

active

Ports inactive after PORST tPIP CC

-

-

150

ns

reset active 5)

Hold time from PORST rising tPOH SR

150

-

-

ns

edge

Setup time to PORST rising tPOS SR

0

-

-

ns

edge

1) The duration of the boot time is defined between the rising edge of the internal application reset and the clock cycle when the first user instruction has entered the CPU pipeline and its processing starts.

2) The timing values assumes programmed BMI with ESR0CNT inactive.

3) The duration of the boot time is defined by all external supply voltages are inside there operation condictions and the clock cycle when the first user instruction has entered the CPU pipeline and its processing starts.

Data Sheet

3-379

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationReset Timing
4) The regulator that supplies VEXT should ensure that VEXT is in the operational region before PORST is externally released by the regulator. Incase of 5V nominal supply, it should be ensured that VEXT > 4V before PORST is released. Incase of 3.3V nominal supply , it should be ensured that VEXT > 3V before PORST is released. The additional minimum PORST hold time is required as an additional mechanism to avoid consecutive PORST toggling owing to slow supply slopes or residual supply ramp-ups. It is also required to activate external PORST atleast 100us before power-fail is recognised to avoid consecutive PORST toggling on a power fail event.
5) This parameter includes the delay of the analog spike filter in the PORST pad.

VDDP

VD DPPA

VDD PPA

VDD PORST

tPOA tPOA
Cold

Warm

V D D PR

ESR0 Pads

Padstate undefined

Tristate Z / pullup H

tPI tP IP
Programmed

Z/ H

t PI Programmed Z / H

TRST TESTMODE

t P OS

t POH

t POS

tP OH

Programmed

Pad-
state undefined

HWCFG

t HDH power -on config

Figure 3-8 Power, Pad and Reset Timing

t HDA

t HDH

config

t HDA

t HDH

config

res et_beh_auri x

Data Sheet

3-380

V 1.0 2017-03

3.16

EVR

TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationEVR

Table 3-36 3.3V

Parameter

Symbol

Values

Unit Note / Test Condition

Input voltage range 1)

VIN SR

Min. 4

Typ. -

Max.

5.50

V

5.50

V

pass device=off chip pass device=on chip

Output voltage operational

VOUT CC 2.97

3.3

range including load/line

2.97

3.3

regulation and aging incase of

LDO regulator

3.63

V

pass device=off chip

3.63

V

pass device=on chip

Output VDDx3 static voltage

VOUTT CC 3.225

3.3

accuracy after trimming and

3.225

3.3

aging without dynamic load/line

Regulation incase of LDO

regulator.

3.375

V

3.375

V

pass device=off chip pass device=on chip

Output buffer capacitance on COUT CC -

VOUT 2)

-

2.2

-

2.2

-

µF pass device=off chip µF pass device=on chip

Primary Undervoltage Reset VRST33 CC -

-

3.0

V

by reset release before

threshold for VDDx3 3)

EVR trimming on

supply ramp-up.

Startup time

tSTR CC

-

-

External VIN supply ramp 4)

dVin/dT

-

SR

-

-

1000

µs

pass device=off chip

-

1000

µs

pass device=on chip

1

50

V/ms pass device=off chip

1

50

V/ms pass device=on chip

Load step response

dVout/dIout -

-

240

mV dI=-100mA;

CC

Tsettle=20µs; pass

device=off chip

-

-

240

mV dI=-70mA/20ns;

Tsettle=20us; pass

device=on chip

-240

-

-

mV dI=100mA;

Tsettle=20µs; pass

device=off chip

-240

-

-

mV dI=50mA/20ns;

Tsettle=20us; pass

device=on chip

Line step response

dVout/dVin -20

-

CC

20

mV dV/dT=1V/ms; pass

device=off chip

-20

-

20

mV dV/dT=1V/ms; pass

device=on chip

1) A maximum pass device dropout voltage of 700mV is included in the minimum input voltage to ensure optimal pass device operation.

Data Sheet

3-381

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationEVR
2) It is recommended to select a capacitor with ESR less than 50 mOhm (0.5MHz - 10 MHz). It is also recommended that the resistance of the supply trace from the pin to the EVR output capacitor is less than 100 mOhm.
3) The reset release on supply ramp-up is delayed by a time duration 20-40 us after reaching undervoltage reset threshold. This serves as a time hysteresis to avoid multiple consecutive cold PORST events during slow supply ramp-ups owing to voltage drop/current jumps when reset is released. The reset limit of 2,97V at pin is for the case with 3.3V generated internally from EVR33. In case the 3.3V supply is provided externally, the bondwire drop will cause a reset at a higher voltage of 3.0V at the VDDP3 pin.
4) EVR robust against residual voltage ramp-up starting between 0-1 V.

Table 3-37 1.3V

Parameter

Symbol

Values

Unit Note / Test Condition

Input voltage range 1)
Output voltage operational range including load/line regulation and aging incase of LDO regulator

VIN SR VOUT CC

Min. 2.97 1.17

Typ. 1.3

Max.

5.5

V

1.43

V

pass device=off chip pass device=off chip

Output VDD static voltage

VOUTT CC 1.275

1.3

accuracy after trimming without

dynamic load/line regulation

with aging incase of LDO

regulator.

1.325

V

pass device=off chip

Output buffer capacitance on COUT CC 3 VOUT 2)

Primary undervoltage reset
threshold for VDD 3)

VRST13 CC -

4.7

6.3

µF pass device=off chip

-

1.17

V

by reset release before

EVR trimming on

supply ramp-up. pass

device=off chip

Startup time

tSTR CC

-

External VIN supply ramp 4)

dVin/dT

-

SR

-

1000

µs

pass device=off chip

1

50

V/ms pass device=off chip

Load step response

dVout/dIout -

-

100

mV dI=-150mA;

CC

Tsettle=20µs; pass

device=off chip

-100

-

-

mV dI=100mA;

Tsettle=20µs; pass

device=off chip

Line step response

dVout/dVin -10

-

10

mV dV/dT=1V/ms; pass

CC

device=off chip

1) A maximum pass device dropout voltage of 700mV is included in the minimum input voltage to ensure optimal pass device operation.

2) It is recommended to select a capacitor with ESR less than 50 mOhm (0.5MHz - 10 MHz). It is also recommended that the resistance of the supply trace from the pin to the EVR output capacitor is less than 100 mOhm.

3) The reset release on supply ramp-up is delayed by a time duration 30-60 µs after reaching undervoltage reset threshold. This serves as a time hysteresis to avoid multiple consecutive cold PORST events during slow supply ramp-ups owing to voltage drop/current jumps when reset is released.The reset limit of 1,17V at pin is for the case with 1.3V generated internally from EVR13. In case the 1.3V supply is provided externally, the bondwire drop will cause a reset at a higher voltage of 1.18V at the VDD pin.

4) EVR robust against residual voltage ramp-up starting between 0-1 V.

Data Sheet

3-382

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationEVR

Table 3-38 Supply Monitoring

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ.

Max.

VEXT primary undervoltage

VEXTPRIUV 2.86

2.92

2.97

V

VEXT = Undervoltage

monitor accuracy after

SR

Reset Threshold

trimming 1)

VDDP3 primary undervoltage

VDDP3PRIUV 2.86

2.90

2.97

V

VDDP3 = Undervoltage

monitor accuracy after

SR

Reset Threshold

trimming 1)

VDD primary undervoltage

VDDPRIUV

1.13

1.15

1.17

V

VDD = Undervoltage

monitor accuracy after

SR

Reset Threshold

trimming 1)

VEXT secondary supply monitor VEXTMON CC 4.9

5.0

5.1

V

SWDxxVAL VEXT

accuracy

monitoring

threshold=5V=DAh

VDDP3 secondary supply
monitor accuracy

VDDP3MON 3.23

3.30

3.37

V

EVR33xxVAL VDDP3

CC

monitoring

threshold=3.3V=90h

VDD secondary supply monitor VDDMON CC 1.27

1.30

1.33

V

EVR13xxVAL VDD

accuracy

monitoring

threshold=1.3V=DFh

EVR primary and secondary tEVRMON CC -

-

1.8

µs

monitor measurement latency

for a new supply value

1) The monitor tolerances constitute the inherent variation of the bandgap and ADC over process, voltage and temperature operational ranges. The xxxPRIUV parameters are device individually tested in production with ±1% tolerance about the min and max xxxPRIUV limits. In TQFP100 and QFP80 pin packages, VDDPRIUV is not tested as HWCFG2 pin is absent.

Table 3-39 EVR13 SMPS External components

Parameter

Symbol

Min.

External output capacitor value COUTDC SR 15.4
1)
6.5

External output capacitor ESR CDC_ESR SR -

-

External input capacitor value 1) CIN SR

6.5

4.42

External input capacitor ESR External inductor value 2)

CIN_ESR SR -
-

LDC SR

2.31 3.29

External inductor ESR
P + N-channel MOSFET logic level

LDC_ESR SR -

VLL SR

-

Values Typ. 22 10 10 6.8 3.3 4.7 -

Max. 29.7 13.5 50 100 13.5 9.18 50 100 4.29 6.11 0.2 2.5

Data Sheet

3-383

Unit Note / Test Condition

µF

IDDDC=1A

µF

IDDDC=400mA

mOhm f0.5MHz; f10MHz

Ohm f=10Hz

µF

IDDDC=1A

µF

IDDDC=400mA

mOhm f0.5MHz; f10MHz

Ohm f=100Hz

µH µH Ohm

fDCDC=1.5MHz fDCDC=1MHz

V

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationEVR

Table 3-39 EVR13 SMPS External components (cont'd)

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ.

Max.

P + N-channel MOSFET drain |VBR_DS| SR -

-

7

V

source breakdown voltage

P + N-channel MOSFET drain RON SR

-

-

150

mOhm IDDDC=1A;VGS=2.5V ;

source ON-state resistance

TA=25°C

-

-

200

mOhm IDDDC=400mA;VGS=2.5

V ; TA=25°C

P + N-channel MOSFET Gate Qac SR

-

Charge

4

-

nC

IDDDC=1A; MOS-

VGS=5V

-

8

-

nC

IDDDC=400mA; MOS-

VGS=5V

External MOSFET commutation time

tc SR

10

30

40

ns

configurable

N-channel MOSFET reverse VRDN SR -

0.8

-

V

diode forward voltage

1) Capacitor min-max range represent typical ±35% tolerance including DC bias effect. The trace resistance from the capacitor to the supply or ground rail should be limited to 25 mOhm.

2) External inductor min-max range represent typical ±30% tolerance at a DC bias current of 100mA.

Table 3-40 EVR13 SMPS

Parameter

Symbol

Min.

Input VDDP3 voltage range Input VEXT Voltage range
SMPS regulator output voltage range including load/line regulation and aging 1)

VIN CC VIN SR VDDDC CC

2.97 2.97 1.17

SMPS regulator static voltage output accuracy after trimming without dynamic load/line Regulation with aging. 2)

VDDDCT CC

1.275

Programmable switching frequency

fDCDC CC 0.4

Switching frequency modulation spread

fDCSPR CC -

Maximum ripple at IMAX (peak- VDDDC CC -
to-peak) 3)

No load current consumption of IDCNL CC -
SMPS regulator

Values Typ. -

Max. 3.63 5.5 1.43

1.3

1.325

-

2.0

-

2%

-

15

5

10

Unit Note / Test Condition

V

V

V

VDD2.97V; VDD5.5V;

IDDDC1mA; IDDDC1A

V

VDD2.97V; VDD5.5V;

IDDDC1mA; IDDDC1A

MHz

MHz

mV VDD2.97V; VDD5.5V; IDDDC300mA; IDDDC1A

mA

fDCDC=1MHz

Data Sheet

3-384

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationEVR

Table 3-40 EVR13 SMPS (cont'd)

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ.

Max.

SMPS regulator load transient dVout/dIout -25

-

response

CC

-65

-

-130

-

Maximum output current of the IMAX SR

-

-

regulator

25

mV dI < 200mA ;

fDCDC=1MHz; tr=0.1µs; tf=0.1µs; VDDDC=1.3V

65

mV dI < 400mA ;

fDCDC=1MHz; tr=0.1µs; tf=0.1µs; VDDDC=1.3V

130

mV dI < 700mA ;

fDCDC=1MHz; tr=0.1µs; tf=0.1µs; VDDDC=1.3V

1

A

limited by thermal

constraints and

component choice

SMPS regulator efficiency

nDC CC

-

85

-

%

VIN=3.3V;

IDDDC=300mA;

fDCDC=1MHz

-

75

-

%

VIN=5V; IDDDC=400mA;

fDCDC=1.5MHz

-

80

-

%

VIN=5V; IDDDC=400mA;

fDCDC=1MHz

1) Incase of SMPS mode, It shall be ensured that the VDD output pin shall be connected on PCB level to all other VDD Input pins.

2) Incase of fSRI running with max frequency, it shall be ensured that the VDD operating range is limited to 1.235V upto 1.430V. The DCDC may be configured in this case with a nominal voltage of 1.33V±7.5%. The static accuracy and regulation
parameter ranges remain also valid for this case.

3) If frequency spreading (SDFREQSPRD = 1) is activated, an additional ripple of 1% need to be considered.

Data Sheet

3-385

V 1.0 2017-03

3.17

Phase Locked Loop (PLL)

TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationPhase Locked Loop (PLL)

Table 3-41 PLL Parameter
PLL base frequency VCO frequency range VCO Input frequency range Modulation Amplitude Peak Period jitter Peak Accumulated Jitter Total long term jitter

Symbol

Min.

fPLLBASE CC 80

fVCO SR

400

fREF CC

8

MA CC 0

DP CC

-200

DPP CC

-5

JTOT CC

-

System frequency deviation Modulation variation frequency PLL lock-in time

fSYSD CC fMV CC tL CC

2 11.5

Values Typ. 150 -

Max. 360 800 24 2 200 5 11.5

-

0.01

3.6

5.4

-

200

Unit Note / Test Condition

MHz MHz MHz % ps ns ns
% MHz µs

without modulation including modulation; MA  1% with active modulation

Note: The specified PLL jitter values are valid if the capacitive load per pin does not exceed CL = 20 pF with the
maximum driver and sharp edge.
Note: The maximum peak-to-peak noise on the power supply voltage, is limited to a peak-to-peak voltage of
VPP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise frequencies above 300 KHz.
These conditions can be achieved by appropriate blocking of the supply voltage as near as possible to the supply pins and using PCB supply and ground planes.

Data Sheet

3-386

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

3.18

Electrical SpecificationERAY Phase Locked Loop (ERAY_PLL)
ERAY Phase Locked Loop (ERAY_PLL)

Table 3-42 PLL_ERAY

Parameter

Symbol

Min.

PLL Base Frequency of the ERAY PLL
VCO frequency range of the ERAY PLL

fPLLBASE_ERA
Y CC
fVCO_ERAY
SR

50 400

VCO input frequency of the fREF SR

16

ERAY PLL

Accumulated_Jitter

DP CC

-0.5

Accumulated jitter at SYSCLK DPP CC

-0.8

pin

PLL lock-in time

tL CC

5.6

Values Typ. 200

Max. 320

-

480

-

24

-

0.5

-

0.8

-

200

Unit Note / Test Condition
MHz MHz MHz ns ns µs

Note: The specified PLL jitter values are valid if the capacitive load per pin does not exceed CL = 20 pF with the
maximum driver and sharp edge.
Note: The maximum peak-to-peak noise on the power supply voltage, is limited to a peak-to-peak voltage of
VPP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise frequencies above 300 KHz.
These conditions can be achieved by appropriate blocking of the supply voltage as near as possible to the supply pins and using PCB supply and ground planes.

Data Sheet

3-387

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationAC Specifications

3.19

AC Specifications

All AC parameters are specified for the complette operating range defined in Chapter 3.4 unless otherwise noted in colum Note / test Condition.

Unless otherwise noted in the figures the timings are defined with the following guidelines:

VEXT/FLEX / VDDP3

90%

90%

VSS

10% tr

Figure 3-9 Definition of rise / fall times

10% tf
ri s e_fal l

VEXT/FLEX / VDDP3 VSS

VEXT/FLEX / VDDP3 2

Figure 3-10 Time Reference Point Definition

Timing Reference
Points

VEXT /FLEX / VDDP3 2
timing_reference

Data Sheet

3-388

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationJTAG Parameters

3.20

JTAG Parameters

The following parameters are applicable for communication through the JTAG debug interface. The JTAG module is fully compliant with IEEE1149.1-2000.

Table 3-43 JTAG

Parameter

Symbol

Values

Min.

Typ.

TCK clock period

t1 SR

25

-

TCK high time

t2 SR

10

-

TCK low time

t3 SR

10

-

TCK clock rise time

t4 SR

-

-

TCK clock fall time

t5 SR

-

-

TDI/TMS setup to TCK rising t6 SR

6.0

-

edge

TDI/TMS hold after TCK rising t7 SR

6.0

-

edge

TDO valid after TCK falling

t8 CC

3.0

-

edge (propagation delay) 1)

-

-

TDO hold after TCK falling

t18 CC

2

-

edge 1)

TDO high impedance to valid t9 CC

-

-

from TCK falling edge 1)2)

TDO valid output to high

t10 CC

-

-

impedance from TCK falling

edge 1)

1) The falling edge on TCK is used to generate the TDO timing.

2) The setup time for TDO is given implicitly by the TCK cycle time.

Max. 4 4 -
-
16.5 -
17.5
17.5

Unit Note / Test Condition

ns ns ns ns ns ns

ns

ns

CL20pF

ns

CL50pF

ns

ns

CL50pF

ns

CL50pF

t1

0.5 VDDP

t5

t2

t3

Figure 3-11 Test Clock Timing (TCK)

0.9 VDDP

t4

0.1 VDDP

MC_ JTAG_ TCK

Data Sheet

3-389

V 1.0 2017-03

TCK
TMS
TDI
t9
TDO Figure 3-12 JTAG Timing

TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationJTAG Parameters

t6

t7

t6

t7

t8

t1 0

t18
MC_JTAG

Data Sheet

3-390

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationDAP Parameters

3.21

DAP Parameters

The following parameters are applicable for communication through the DAP debug interface.

Table 3-44 DAP

Parameter

Symbol

Values

Unit

Min.

Typ.

Max.

DAP0 clock period DAP0 high time DAP0 low time DAP0 clock rise time

t11 SR

6.25

-

t12 SR

2

-

t13 SR

2

-

t14 SR

-

-

-

-

-

ns

-

ns

-

ns

1

ns

2

ns

DAP0 clock fall time

t15 SR

-

-

1

ns

-

-

2

ns

DAP1 setup to DAP0 rising t16 SR

4

-

-

ns

edge

DAP1 hold after DAP0 rising t17 SR

2

-

-

ns

edge

DAP1 valid per DAP0 clock t19 CC

3

-

-

ns

period 1)

8

-

-

ns

10

-

-

ns

1) The Host has to find a suitable sampling point by analyzing the sync telegram response.

Note / Test Condition
f=160MHz f=80MHz f=160MHz f=80MHz
CL=20pF; f=160MHz CL=20pF; f=80MHz CL=50pF; f=40MHz

t11

0.5 VDDP

t1 5

t1 2

t1 3

Figure 3-13 Test Clock Timing (DAP0)

0.9 VDDP

t14

0.1 VDDP

MC_DAP0

DAP0 DAP1
Figure 3-14 DAP Timing Host to Device

t1 6

t1 7

MC_ DAP1_RX

Data Sheet

3-391

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationDAP Parameters
t1 1
DAP1
t1 9
MC_ DAP1_TX
Figure 3-15 DAP Timing Device to Host (DAP1 and DAP2 pins) Note: The DAP1 and DAP2 device to host timing is individual for both pins. There is no guaranteed max. signal
skew.

Data Sheet

3-392

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationASCLIN SPI Master Timing

3.22

ASCLIN SPI Master Timing

This section defines the timings for the ASCLIN in the TC290 / TC297 / TC298 / TC299, for 5V power supply.

Note: Pad asymmetry is already included in the following timings.

Table 3-45 Master Mode MP+ss/MPRss output pads

Parameter

Symbol

Values

ASCLKO clock period 1)

t50 CC

Deviation from ideal duty cycle t500 CC
2)

Min. 20 -3

Typ. -

Max. 3

Unit Note / Test Condition

ns

CL=25pF

ns

0 < CL < 50pF

MTSR delay from ASCLKO t51 CC

-7

-

shifting edge

6

ns

CL=25pF

ASLSOn delay from the first t510 CC

5

-

ASCLKO edge

35

ns

CL=25pF; pad used =

LPm

MRST setup to ASCLKO

t52 SR

30

-

-

ns

CL=25pF

latching edge

MRST hold from ASCLKO

t53 SR

-4.5

-

-

ns

CL=25pF

latching edge

1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite.

Table 3-46 Master Mode MP+sm/MPRsm output pads

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ.

Max.

ASCLKO clock period 1)

t50 CC

50

-

Deviation from ideal duty cycle t500 CC

-2

-

2)

MTSR delay from ASCLKO t51 CC

-10

-

shifting edge

-

ns

3+0.01 * ns

CL

10

ns

CL=50pF 0 < CL < 200pF
CL=50pF

ASLSOn delay from the first t510 CC

5

-

ASCLKO edge

35

ns

CL=50pF; pad used =

LPm

MRST setup to ASCLKO

t52 SR

50

-

-

ns

CL=50pF

latching edge

MRST hold from ASCLKO

t53 SR

-9

-

-

ns

CL=50pF

latching edge

1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite.

Data Sheet

3-393

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationASCLIN SPI Master Timing

Table 3-47 Master Mode MPss output pads

Parameter

Symbol

Values

Unit Note / Test Condition

ASCLKO clock period 1)

t50 CC

Deviation from ideal duty cycle t500 CC
2)

MTSR delay from ASCLKO shifting edge

t51 CC

Min. 20 -2
-7

Typ. -
-

Max.

-

ns

3.5+0.035 ns

* CL

6

ns

CL=25pF 0 < CL < 200pF
CL=25pF

ASLSOn delay from the first t510 CC

-7

-

ASCLKO edge

6

ns

CL=25pF

MRST setup to ASCLKO

t52 SR

31

-

-

ns

CL=25pF, else

latching edge

33 3)

-

-

ns

CL=25pF, for P14.2,

P14.4, and P15.1

MRST hold from ASCLKO

t53 SR

-5

-

-

ns

CL=25pF

latching edge

1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite.

3) Please note that these pins didn't support the hystereses inactive feature.

Table 3-48 Master Mode MPsm output pads

Parameter

Symbol

Values

Unit Note / Test Condition

ASCLKO clock period 1)

t50 CC

Deviation from ideal duty cycle t500 CC
2)

MTSR delay from ASCLKO shifting edge

t51 CC

Min. 100 -3
-11

Typ. -
-

Max.

-

ns

4+0.04 * ns

CL

10

ns

CL=50pF 0 < CL < 200pF
CL=50pF

ASLSOn delay from the first t510 CC

-11

-

ASCLKO edge

10

ns

CL=50pF

MRST setup to ASCLKO

t52 SR

60

-

-

ns

CL=50pF

latching edge

MRST hold from ASCLKO

t53 SR

-10

-

-

ns

CL=50pF

latching edge

1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite.

Data Sheet

3-394

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationASCLIN SPI Master Timing

Table 3-49 Master Mode medium output pads

Parameter

Symbol

Values

Unit Note / Test Condition

ASCLKO clock period 1)

t50 CC

Deviation from ideal duty cycle t500 CC
2)

MTSR delay from ASCLKO shifting edge

t51 CC

Min. 200 -8
-20

Typ. -
-

Max.

-

ns

4+0.06 * ns

CL

18.5

ns

CL=50pF 0 < CL < 200pF
CL=50pF

ASLSOn delay from the first t510 CC

-20

-

ASCLKO edge

20

ns

CL=50pF

MRST setup to ASCLKO

t52 SR

70

-

-

ns

CL=50pF

latching edge

MRST hold from ASCLKO

t53 SR

-10

-

-

ns

CL=50pF

latching edge

1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite.

Table 3-50 Master Mode weak output pads

Parameter

Symbol

Values

Unit Note / Test Condition

ASCLKO clock period 1)

t50 CC

Deviation from ideal duty cycle t500 CC
2)

MTSR delay from ASCLKO shifting edge

t51 CC

Min. 1000 -30
-75

Typ. -
-

Max.

-

ns

30+0.15 * ns

CL

75

ns

CL=50pF 0 < CL < 200pF
CL=50pF

ASLSOn delay from the first t510 CC

-65

-

ASCLKO edge

65

ns

CL=50pF

MRST setup to ASCLKO

t52 SR

510

-

-

ns

CL=50pF

latching edge

MRST hold from ASCLKO

t53 SR

-50

-

-

ns

CL=50pF

latching edge

1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite.

Data Sheet

3-395

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationASCLIN SPI Master Timing

ASCLKO MTSR MRST ASLSO

t50

t51

t500

t52 t53
Data valid
t510

Figure 3-16 ASCLIN SPI Master Timing

t51
Data valid
ASCLIN_TmgMM.vsd

Data Sheet

3-396

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationASCLIN SPI Master Timing

3.23

ASCLIN SPI Master Timing

This section defines the timings for the ASCLIN in the TC290 / TC297 / TC298 / TC299, for 3.3V power supply,
Medium Performance pads, strong sharp edge (MPss), CL=25pF.
Note: Pad asymmetry is already included in the following timings.

Table 3-51 Master Mode MP+ss/MPRss output pads

Parameter

Symbol

Values

ASCLKO clock period 1)

t50 CC

Deviation from ideal duty cycle t500 CC
2)

Min. 40 -5

Typ. -

Max. 5

Unit Note / Test Condition

ns

CL=25pF

ns

0 < CL < 50pF

MTSR delay from ASCLKO t51 CC

-12

-

shifting edge

12

ns

CL=25pF

ASLSOn delay from the first t510 CC

0

-

ASCLKO edge

60

ns

CL=25pF; pad used =

LPm

MRST setup to ASCLKO

t52 SR

50

-

-

ns

CL=25pF

latching edge

MRST hold from ASCLKO

t53 SR

-5

-

-

ns

CL=25pF

latching edge

1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite.

Table 3-52 Master Mode MP+sm/MPRsm output pads

Parameter

Symbol

Values

ASCLKO clock period 1)

t50 CC

Deviation from ideal duty cycle t500 CC
2)

Min. 100 -3

Typ. -

Max. 7

Unit Note / Test Condition

ns

CL=50pF

ns

0 < CL < 200pF

MTSR delay from ASCLKO t51 CC

-17

-

shifting edge

17

ns

CL=50pF

ASLSOn delay from the first t510 CC

0

-

ASCLKO edge

60

ns

CL=50pF; pad used =

LPm

MRST setup to ASCLKO

t52 SR

85

-

-

ns

CL=50pF

latching edge

MRST hold from ASCLKO

t53 SR

-5

-

-

ns

CL=50pF

latching edge

1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite.

Data Sheet

3-397

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationASCLIN SPI Master Timing

Table 3-53 Master Mode MPss output pads

Parameter

Symbol

Values

Unit Note / Test Condition

ASCLKO clock period 1)

t50 CC

Deviation from ideal duty cycle t500 CC
2)

MTSR delay from ASCLKO shifting edge

t51 CC

Min. 40 -5
-12

Typ. -
-

Max.

-

ns

7+0.07 * ns

CL

12

ns

CL=25pF 0 < CL < 200pF
CL=25pF

ASLSOn delay from the first t510 CC

-12

-

ASCLKO edge

12

ns

CL=25pF

MRST setup to ASCLKO

t52 SR

50

-

-

ns

CL=25pF

latching edge

MRST hold from ASCLKO

t53 SR

-5

-

-

ns

CL=25pF

latching edge

1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite.

Table 3-54 Master Mode MPsm output pads

Parameter

Symbol

Values

Unit Note / Test Condition

ASCLKO clock period 1)

t50 CC

Deviation from ideal duty cycle t500 CC
2)

MTSR delay from ASCLKO shifting edge

t51 CC

Min. 200 -5
-19

Typ. -
-

Max.

-

ns

9+0.06 * ns

CL

17

ns

CL=50pF 0 < CL < 200pF
CL=50pF

ASLSOn delay from the first t510 CC

-19

-

ASCLKO edge

17

ns

CL=50pF

MRST setup to ASCLKO

t52 SR

100

-

-

ns

CL=50pF

latching edge

MRST hold from ASCLKO

t53 SR

-13

-

-

ns

CL=50pF

latching edge

1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite.

Table 3-55 Master Mode medium output pads

Parameter

Symbol

ASCLKO clock period 1)

t50 CC

Deviation from ideal duty cycle t500 CC
2)

Min. 400 -6-0.07 *
CL

Values Typ. -

Max. 6+0.07 *
CL

Unit
ns ns

Note / Test Condition
CL=50pF 0 < CL < 200pF

Data Sheet

3-398

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationASCLIN SPI Master Timing

Table 3-55 Master Mode medium output pads (cont'd)

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ.

Max.

MTSR delay from ASCLKO t51 CC

-33

-

shifting edge

25

ns

CL=50pF

ASLSOn delay from the first t510 CC

-35

-

ASCLKO edge

35

ns

CL=50pF

MRST setup to ASCLKO

t52 SR

120

-

-

ns

CL=50pF

latching edge

MRST hold from ASCLKO

t53 SR

-13

-

-

ns

CL=50pF

latching edge

1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite.

Table 3-56 Master Mode weak output pads

Parameter

Symbol

Min.

ASCLKO clock period 1)

t50 CC

Deviation from ideal duty cycle t500 CC
2)

2000 -110

Values Typ. -

Max. 150

Unit Note / Test Condition

ns

CL=50pF

ns

0 < CL < 200pF

MTSR delay from ASCLKO t51 CC

-170

-

shifting edge

170

ns

CL=50pF

ASLSOn delay from the first t510 CC

-170

-

ASCLKO edge

170

ns

CL=50pF

MRST setup to ASCLKO

t52 SR

510

-

-

ns

CL=50pF

latching edge

MRST hold from ASCLKO

t53 SR

-40

-

-

ns

CL=50pF

latching edge

1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite.

Table 3-57 Master Mode A2ss output pads

Parameter

Symbol

ASCLKO clock period 1)

t50 CC

Deviation from ideal duty cycle t500 CC
2)

Min. 20 -3

MTSR delay from ASCLKO t51 CC

-4

shifting edge

ASLSOn delay from the first t510 CC

-5

ASCLKO edge

Values Typ. -

Max. 3

-

4

-

4

Data Sheet

3-399

Unit Note / Test Condition

ns

CL=50pF

ns

CL=50pF

ns

CL=50pF

ns

CL=50pF

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationASCLIN SPI Master Timing

Table 3-57 Master Mode A2ss output pads (cont'd)

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ.

Max.

MRST setup to ASCLKO

t52 SR

17

-

-

ns

CL=50pF

latching edge

MRST hold from ASCLKO

t53 SR

0

-

-

ns

CL=50pF

latching edge

1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite.

Table 3-58 Master Mode A2sm output pads

Parameter

Symbol

ASCLKO clock period 1)

t50 CC

Deviation from ideal duty cycle t500 CC
2)

Min. 40 -4

Values Typ. -

Max. 4

Unit Note / Test Condition

ns

CL=50pF

ns

CL=50pF

MTSR delay from ASCLKO t51 CC

-8

-

shifting edge

6

ns

CL=50pF

ASLSOn delay from the first t510 CC

-8

-

ASCLKO edge

9

ns

CL=50pF

MRST setup to ASCLKO

t52 SR

26

-

-

ns

CL=50pF

latching edge

MRST hold from ASCLKO

t53 SR

0

-

-

ns

CL=50pF

latching edge

1) PLL Jitter not included. Should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the BITCON.SAMPLEPOINT bitfield with the finest granularity of TMAX = 1 / fMAX.
2) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite.

ASCLKO MTSR MRST ASLSO

t50

t51

t500

t52 t53
Data valid
t510

Figure 3-17 ASCLIN SPI Master Timing

t51
Data valid
ASCLIN_TmgMM.vsd

Data Sheet

3-400

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationQSPI Timings, Master and Slave Mode

3.24

QSPI Timings, Master and Slave Mode

This section defines the timings for the QSPI in the TC290 / TC297 / TC298 / TC299, for 5V pad power supply. It is assumed that SCLKO, MTSR, and SLSO pads have the same pad settings:

· LVDSM output pads,LVDSH input pad, master mode, CL=25pF
· Medium Performance Plus Pads (MP+):

­ strong sharp edge (MP+ss), CL=25pF ­ strong medium edge (MP+sm), CL=50pF ­ medium edge (MP+m), CL=50pF ­ weak edge (MP+w), CL=50pF
· Medium Performance Pads (MP):

­ strong sharp edge (MPss), CL=25pF ­ strong medium edge (MPsm), CL=50pF
· Medium and Low Performance Pads (MP/LP), the identical output strength settings:

­ medium edge (LP/MPm), CL=50pF ­ weak edge (MPw), CL=50pF

Table 3-59 Master Mode Timing, LVDSM output pads for data and clock

Parameter

Symbol

Values

Unit Note / Test Condition

SCLKO clock period 1)
Deviation from the ideal duty cycle 3) 4)

t50 CC t500 CC

Min. 20 2) -1

Typ. -

Max.

-

ns

CL=25pF

1

ns

CL=25pF

MTSR delay from SCLKO

t51 CC

-3

-

shifting edge

3

ns

CL=25pF

SLSOn deviation from the ideal t510 CC

0

-

programmed position

-5

-

30

ns

CL=25pF; MPsm

7

ns

CL=25pF; MPss

-4

-

7

ns

MP+ss; CL=25pF

-1

-

MRST setup to SCLK latching t52 SR

19 5)

-

edge 5)

15

ns

MP+sm; CL=25pF

-

ns

CL=25pF; LVDSM 5V

output and LVDSH

3.3V input

MRST hold from SCLK latching t53 SR

-6 5)

-

-

ns

CL=25pF; LVDSM 5V

edge

output and LVDSH

3.3V input

1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has to be taken into account.

2) The capacitive load on the LVDS pins is differential, the capacitive load on the CMOS pins is single ended.

3) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX.
4) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite.

5) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.

Data Sheet

3-401

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationQSPI Timings, Master and Slave Mode

Table 3-60 Master Mode MP+ss/MPRss output pads

Parameter

Symbol

Values

Unit Note / Test Condition

SCLKO clock period 1)
Deviation from the ideal duty cycle 2) 3)

t50 CC t500 CC

Min. 20 -3

Typ. -

Max. 3

ns

CL=25pF

ns

0 < CL < 50pF

MTSR delay from SCLKO

t51 CC

-7

-

shifting edge

6

ns

CL=25pF

SLSOn deviation from the ideal t510 CC

-7

-

programmed position

6

ns

CL=25pF

MRST setup to SCLK latching t52 SR

27 4)5)

-

-

ns

CL=25pF

edge 4)

MRST hold from SCLK latching t53 SR

-4.5 4)5) -

-

ns

CL=25pF

edge

1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has to be taken into account.

2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite.

4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.

5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.

Table 3-61 Master Mode MP+sm/MPRsm output pads for data and clock

Parameter

Symbol

Values

Unit Note / Test Condition

SCLKO clock period 1)
Deviation from the ideal duty cycle 2) 3)
MTSR delay from SCLKO shifting edge

t50 CC t500 CC
t51 CC

Min. 50 -2
-10

Typ. -
-

Max.

-

ns

3+0.01 * ns

CL

10

ns

CL=50pF 0 < CL < 200pF
CL=50pF

SLSOn deviation from the ideal t510 CC

-10

-

programmed position

-13

-

10

ns

MP+sm; CL=50pF

1

ns

MPss; CL=50pF

MRST setup to SCLK latching t52 SR
edge 4)

0

-

50 4)5)

-

40

ns

MP+m, MPm, LPm;

CL=50pF

-

ns

CL=50pF

MRST hold from SCLK latching t53 SR

-9 4)5)

-

-

ns

CL=50pF

edge

1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has to be taken into account.

2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite.

Data Sheet

3-402

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationQSPI Timings, Master and Slave Mode
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C. 5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.

Table 3-62 Master Mode timing MPss output pads for data and clock, CL=50pF

Parameter

Symbol

Values

Unit Note / Test Condition

SCLKO clock period 1)
Deviation from the ideal duty cycle 2) 3)
MTSR delay from SCLKO shifting edge

t50 CC t500 CC
t51 CC

Min. 40 -2
-8

Typ. -
-

Max.

-

ns

3.5+0.035 ns

* CL

8

ns

CL=50pF 0 < CL < 200pF
CL=50pF

SLSOn deviation from the ideal t510 CC

-8

-

programmed position

-1

-

8

ns

MPss; CL=50pF

15

ns

MP+sm; CL=50pF

MRST setup to SCLK latching t52 SR
edge 4)

0

-

40 4)5)

-

50

ns

MP+m, MPm, LPm;

CL=50pF

-

ns

CL=50pF

MRST hold from SCLK latching t53 SR

-5 4)5)

-

-

ns

CL=50pF

edge

1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has to be taken into account.

2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite.

4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.

5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.

Table 3-63 Master Mode timing MPsm output pads

Parameter

Symbol

Values

Unit Note / Test Condition

SCLKO clock period 1)
Deviation from the ideal duty cycle 2) 3)
MTSR delay from SCLKO shifting edge

t50 CC t500 CC
t51 CC

Min. 100 -3
-11

Typ. -
-

Max.

-

ns

4+0.04 * ns

CL

10

ns

CL=50pF 0 < CL < 200pF
CL=50pF

SLSOn deviation from the ideal t510 CC

-11

-

programmed position

10

ns

CL=50pF

MRST setup to SCLK latching t52 SR

60 4)5)

-

-

ns

CL=50pF

edge 4)

MRST hold from SCLK latching t53 SR

-10 4)5)

-

-

ns

CL=50pF

edge

1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has to be taken into account.

Data Sheet

3-403

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationQSPI Timings, Master and Slave Mode
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C. 5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.

Table 3-64 Master Mode timing MPRm/MP+m/MPm/LPm output pads

Parameter

Symbol

Values

Unit Note / Test Condition

SCLKO clock period 1)
Deviation from the ideal duty cycle 2) 3)
MTSR delay from SCLKO shifting edge

t50 CC t500 CC
t51 CC

Min. 200 -10
-15

Typ. -
-

Max.

-

ns

16+0.04 * ns

CL

20

ns

CL=50pF 0 < CL < 200pF
CL=50pF

SLSOn deviation from the ideal t510 CC

-20

-

programmed position

20

ns

CL=50pF

MRST setup to SCLK latching t52 SR

70 4)5)

-

-

ns

CL=50pF

edge 4)

MRST hold from SCLK latching t53 SR

-10 4)5)

-

-

ns

CL=50pF

edge

1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has to be taken into account.

2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite.

4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.

5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.

Table 3-65 Master Mode Weak output pads

Parameter

Symbol

Values

Unit Note / Test Condition

SCLKO clock period 1)
Deviation from the ideal duty cycle 2) 3)
MTSR delay from SCLKO shifting edge

t50 CC t500 CC
t51 CC

Min. 1000 -30
-65

Typ. -
-

Max.

-

ns

30+0.15 * ns

CL

65

ns

CL=50pF 0 < CL < 200pF
CL=50pF

SLSOn deviation from the ideal t510 CC

-65

-

programmed position

65

ns

CL=50pF

MRST setup to SCLK latching t52 SR

300 4)5) -

-

ns

CL=50pF

edge 4)

MRST hold from SCLK latching t53 SR

-40 4)5)

-

-

ns

CL=50pF

edge

1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has to be taken into account.

Data Sheet

3-404

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationQSPI Timings, Master and Slave Mode
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C. 5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.

Table 3-66 Slave mode timing

Parameter

Symbol

SCLK clock period SCLK duty cycle MTSR setup to SCLK latching edge

t54 SR t55/t54 SR t56 SR

MTSR hold from SCLK latching t57 SR
edge

SLSI setup to first SCLK shift t58 SR
edge

SLSI hold from last SCLK latching edge

t59 SR

MRST delay from SCLK shift t60 CC
edge

Min.
4 x TMAX
40 4 1) 5 1) 5 1) 3.5 1) 6 1) 9 1) 5 1) 4 1) 8 1) 6 3 1) 4 1) 8 1) 10

Values Typ. -

Max. 60 70

9

-

50

5

-

30

40

-

300

10

-

70

10

-

55

5

-

30

40

-

300

SLSI to valid data on MRST t61 SR

-

-

5

1) Except pin P15.1.

Unit Note / Test Condition

ns

%

ns

Hystheresis Inactive

ns

Input Level AL

ns

Input Level TTL

ns

Hystheresis Inactive

ns

Input Level AL

ns

Input Level TTL

ns

Hystheresis Inactive

ns

Input Level AL

ns

Input Level TTL

ns

Only for pin 15.1, AL

ns

Hystheresis Inactive

ns

Input Level AL

ns

Input Level TTL

ns

MP+m/MPRm;

CL=50pF

ns

MP+sm/MPRsm;

CL=50pF

ns

MP+ss/MPRss;

CL=25pF

ns

MP+w/MPRw;

CL=50pF

ns

MPm/LPm; CL=50pF

ns

MPsm; CL=50pF

ns

MPss; CL=25pF

ns

MPw/LPw; CL=50pF

ns

Data Sheet

3-405

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationQSPI Timings, Master and Slave Mode

SCLK1)2)

t50 t500
t51

0.5 VEXT/FLEX SAMPLING POINT

MTSR1) MRST1) SLSOn2)

t52 t53
Data valid
t510

0.5 VEXT/FLEX
Data valid
0.5 VEXT/FLEX

1) This timing is based on the following setup: ECON.CPH = 1, ECON.CPOL = 0, ECON.B=0 (no sampling point delay). 2) t510 is the deviation from the ideal position configured with the leading delay, BACON.LPRE and BACON.LEAD > 0.
QSPI_TmgMM.vsd
Figure 3-18 Master Mode Timing

SCLKI1) MTSR1) MRST1) SLSI

t54

First shift SCLK edge

First latching SCLK edge

t55

t55

t56

t57

Data valid

t60

t60

t58 t61

Last latching SCLK edge
0.5 VEXT/FLEX
t56 t57
Data valid
0.5 VEXT/FLEX
t59

1) This timing is based on the following setup: ECON.CPH = 1, ECON.CPOL = 0. QSPI_TmgSM.vsd

Figure 3-19 Slave Mode Timing

3.25

QSPI Timings, Master and Slave Mode

This section defines the timings for the QSPI in the TC290 / TC297 / TC298 / TC299, for 3.3V pad power supply. It is assumed that SCLKO, MTSR, and SLSO pads have the same pad settings:

· LVDSM output pads,LVDSH input pad, master mode, CL=25pF
· Medium Performance Plus Pads (MP+):

­ strong sharp edge (MP+ss), CL=25pF ­ strong medium edge (MP+sm), CL=50pF ­ medium edge (MP+m), CL=50pF ­ weak edge (MP+w), CL=50pF
· Medium Performance Pads (MP):

­ strong sharp edge (MPss), CL=25pF ­ strong medium edge (MPsm), CL=50pF
· Medium and Low Performance Pads (MP/LP), the identical output strength settings:

Data Sheet

3-406

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationQSPI Timings, Master and Slave Mode

­ medium edge (LP/MPm), CL=50pF ­ weak edge (MPw), CL=50pF

Table 3-67 Master Mode Timing, LVDSM output pads for data and clock

Parameter

Symbol

Values

Unit Note / Test Condition

SCLKO clock period 1)
Deviation from the ideal duty cycle 2) 3)

t50 CC t500 CC

Min. 20 -2

Typ. -

Max. 2

ns

CL=25pF

ns

CL=25pF

MTSR delay from SCLKO

t51 CC

-5

-

shifting edge

5

ns

CL=25pF

SLSOn deviation from the ideal t510 CC

-2

-

programmed position

-9

-

-7

-

-2

-

MRST setup to SCLK latching t52 SR

20

-

edge 4)

55

ns

CL=25pF; MPsm

12

ns

CL=25pF; MPss

12

ns

MP+ss; CL=25pF

26

ns

MP+sm; CL=25pF

-

ns

CL=25pF; LVDSM 5V

output and LVDSH

3.3V input

MRST hold from SCLK latching t53 SR

-6

-

-

ns

CL=25pF; LVDSM 5V

edge

output and LVDSH

3.3V input

1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has to be taken into account.

2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite.

4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.

Table 3-68 Master Mode MP+ss/MPRss output pads

Parameter

Symbol

Values

Unit Note / Test Condition

SCLKO clock period 1)
Deviation from the ideal duty cycle 2) 3)

t50 CC t500 CC

Min. 40 -5

Typ. -

Max. 5

ns

CL=25pF

ns

0 < CL < 50pF

MTSR delay from SCLKO

t51 CC

-12

-

shifting edge

12

ns

CL=25pF

SLSOn deviation from the ideal t510 CC

-12

-

programmed position

12

ns

CL=25pF

MRST setup to SCLK latching t52 SR

50 4)5)

-

-

ns

CL=25pF

edge 4)

MRST hold from SCLK latching t53 SR

-5 4)5)

-

-

ns

CL=25pF

edge

1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has to be taken into account.

Data Sheet

3-407

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationQSPI Timings, Master and Slave Mode
2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite.
4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C. 5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.

Table 3-69 Master Mode MP+sm/MPRsm output pads for data and clock

Parameter

Symbol

Values

Unit Note / Test Condition

SCLKO clock period 1)
Deviation from the ideal duty cycle 2) 3)

t50 CC t500 CC

Min. 100 -3

Typ. -

Max. 7

ns

CL=50pF

ns

0 < CL < 200pF

MTSR delay from SCLKO

t51 CC

-17

-

shifting edge

17

ns

CL=50pF

SLSOn deviation from the ideal t510 CC

-17

-

programmed position

-22

-

17

ns

MP+sm; CL=50pF

2

ns

MPss; CL=50pF

MRST setup to SCLK latching t52 SR
edge 4)

0

-

85 4)5)

-

70

ns

MP+m; MPm; LPm;

CL=50pF

-

ns

CL=50pF

MRST hold from SCLK latching t53 SR

-10 4)5)

-

-

ns

CL=50pF

edge

1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has to be taken into account.

2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite.

4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.

5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.

Table 3-70 Master Mode timing MPss output pads

Parameter

Symbol

SCLKO clock period 1)
Deviation from the ideal duty cycle 2) 3)

t50 CC t500 CC

Min. 40 -5

MTSR delay from SCLKO

t51 CC

-7

shifting edge

SLSOn deviation from the ideal t510 CC

-10

programmed position

Values Typ. -
-
-

Max. 5+0.04 *
CL
7
10

Unit
ns ns ns ns

Note / Test Condition
CL=25pF CL=25pF CL=25pF CL=25pF

Data Sheet

3-408

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationQSPI Timings, Master and Slave Mode

Table 3-70 Master Mode timing MPss output pads (cont'd)

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ.

Max.

MRST setup to SCLK latching t52 SR

50 4)5)

-

-

ns

CL=25pF

edge 4)

MRST hold from SCLK latching t53 SR

-6 4)5)

-

-

ns

CL=25pF

edge

1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has to be taken into account.

2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite.

4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.

5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.

Table 3-71 Master Mode timing MPsm output pads

Parameter

Symbol

Values

Unit Note / Test Condition

SCLKO clock period 1)
Deviation from the ideal duty cycle 2) 3)
MTSR delay from SCLKO shifting edge

t50 CC t500 CC
t51 CC

Min. 200 -5
-19

Typ. -
-

Max.

-

ns

9+0.06 * ns

CL

19

ns

CL=50pF 0 < CL < 200pF
CL=50pF

SLSOn deviation from the ideal t510 CC

-19

-

programmed position

17

ns

CL=50pF

MRST setup to SCLK latching t52 SR

100 4)5) -

-

ns

CL=50pF

edge 4)

MRST hold from SCLK latching t53 SR

-13 4)5)

-

-

ns

CL=50pF

edge

1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has to be taken into account.

2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite.

4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.

5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.

Table 3-72 Master Mode timing MPRm/MP+m/MPm/LPm output pads

Parameter

Symbol

Values

Unit

SCLKO clock period 1)
Deviation from the ideal duty cycle 2) 3)

t50 CC t500 CC

Min. 400 -6-0.07 *
CL

Typ. -

Max.

-

ns

6+0.095 * ns
CL

Note / Test Condition
CL=50pF 0 < CL < 200pF

Data Sheet

3-409

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationQSPI Timings, Master and Slave Mode

Table 3-72 Master Mode timing MPRm/MP+m/MPm/LPm output pads (cont'd)

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ.

Max.

MTSR delay from SCLKO

t51 CC

-25

-

shifting edge

33

ns

CL=50pF

SLSOn deviation from the ideal t510 CC
programmed position
MRST setup to SCLK latching t52 SR
edge 4)

-35

-

120 4)5) -

35

ns

CL=50pF

-

ns

CL=50pF

MRST hold from SCLK latching t53 SR

-13 4)5)

-

-

ns

CL=50pF

edge

1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has to be taken into account.

2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite.

4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.

5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.

Table 3-73 Master Mode Weak output pads

Parameter

Symbol

Values

Unit Note / Test Condition

SCLKO clock period 1)
Deviation from the ideal duty cycle 2) 3)

t50 CC t500 CC

Min. 2000 -110

Typ. -

Max. 125

ns

CL=50pF

ns

0 < CL < 200pF

MTSR delay from SCLKO

t51 CC

-170

-

shifting edge

170

ns

CL=50pF

SLSOn deviation from the ideal t510 CC

-170

-

programmed position

170

ns

CL=50pF

MRST setup to SCLK latching t52 SR

510 4)5) -

-

ns

CL=50pF

edge 4)

MRST hold from SCLK latching t53 SR

-40 4)5)

-

-

ns

CL=50pF

edge

1) Documented value is valid for master transmit or slave receive only. For full duplex the external SPI counterpart timing has to be taken into account.

2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted using the bit fields ECONz.A, B and C with the finest granularity of TMAX = 1 / fMAX.
3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite.

4) For compensation of the average on-chip delay the QSPI module provides the bit fields ECONz.A, B and C.

5) The setup and hold times are valid for both settings of the input pads thresholds: TTL and AL.

Data Sheet

3-410

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationQSPI Timings, Master and Slave Mode

Table 3-74 Slave mode timing

Parameter

Symbol

SCLK clock period SCLK duty cycle MTSR setup to SCLK latching edge

t54 SR t55/t54 SR t56 SR

MTSR hold from SCLK latching t57 SR
edge

SLSI setup to first SCLK shift t58 SR
edge

SLSI hold from last SCLK latching edge

t59 SR

MRST delay from SCLK shift t60 CC
edge

Min.
4 x TMAX
40 7 1) 9 1) 7 1) 5 1) 11 1) 16 1) 7 1) 7 1) 14 1) 11 5 1) 7 1) 14 1) 13

Values Typ. -

Max. 60 120

12.5

-

85

5.5

-

50

70

-

500

13

-

120

13

-

100

6

-

52

70

-

500

SLSI to valid data on MRST t61 SR

-

-

9

1) Except pin P15.1

Unit Note / Test Condition

ns

%

ns

Hystheresis inactive

ns

Input Level AL

ns

Input Level TTL

ns

Hystheresis inactive

ns

Input Level AL

ns

Input Level TTL

ns

Hystheresis inactive

ns

Input Level AL

ns

Input Level TTL

ns

Only for pin P15.1, AL

ns

Hystheresis inactive

ns

Input Level AL

ns

Input Level TTL

ns

MP+m/MPRm;

CL=50pF

ns

MP+sm/MPRsm;

CL=50pF

ns

MP+ss/MPRss;

CL=25pF

ns

MP+w/MPRw;

CL=50pF

ns

MPm/LPm; CL=50pF

ns

MPsm; CL=50pF

ns

MPss; CL=25pF

ns

MPw/LPw; CL=50pF

ns

Data Sheet

3-411

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationQSPI Timings, Master and Slave Mode

SCLK1)2)

t50 t500
t51

0.5 VEXT/FLEX SAMPLING POINT

MTSR1) MRST1) SLSOn2)

t52 t53
Data valid
t510

0.5 VEXT/FLEX
Data valid
0.5 VEXT/FLEX

1) This timing is based on the following setup: ECON.CPH = 1, ECON.CPOL = 0, ECON.B=0 (no sampling point delay). 2) t510 is the deviation from the ideal position configured with the leading delay, BACON.LPRE and BACON.LEAD > 0.
QSPI_TmgMM.vsd

Figure 3-20 Master Mode Timing

SCLKI1) MTSR1) MRST1) SLSI

t54

First shift SCLK edge

First latching SCLK edge

t55

t55

t56

t57

Data valid

t60

t60

t58 t61

Last latching SCLK edge
0.5 VEXT/FLEX
t56 t57
Data valid
0.5 VEXT/FLEX
t59

1) This timing is based on the following setup: ECON.CPH = 1, ECON.CPOL = 0. QSPI_TmgSM.vsd

Figure 3-21 Slave Mode Timing

Data Sheet

3-412

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

3.26

MSC Timing 5 V Operation

Electrical SpecificationMSC Timing 5 V Operation

The following section defines the timings for 5V pad power supply. Note: Pad asymmetry is already included in the following timings. Note: Load for LVDS pads are defined as differential loads in the following timings.

Table 3-75 LVDS clock/data (LVDS pads in LVDS mode)

Parameter

Symbol

FCLPx clock period 1)

t40 CC

Deviation from ideal duty cycle t400 CC
4) 5)

Values

Min.

Typ.

2 * TA 2) 3) -

-1

-

Max. 1

Unit Note / Test Condition

ns

LVDSM; CL=50pF

ns

LVDSM; 0 < CL < 50pF

SOPx output delay 6)

t44 CC

-3

-

4

ns

LVDSM; CL=50pF;

option EN01

-4

-

4.5

ns

LVDSM; CL=50pF;

option EN01D

ENx output delay 6)

t45 CC

-4

-

5

ns

MP+ss/MPRss; option

EN01; CL=25pF

-3.5

-

7

ns

MP+ss/MPRss; option

EN01; CL=50pF

-3

-

11

ns

MP+sm/MPRsm;

option EN01D;

CL=50pF

-2.5

-

9

ns

MP+ss/MPRss; option

EN23; CL=25pF

-2.5

-

10

ns

MP+ss/MPRss; option

EN23; CL=50pF

-3

-

11

ns

MPss; option EN01;

CL=50pF

-7

-

3

ns

MP+ss/MPRss; option

EN01; CL=0pF

-5

-

3

ns

MP+sm/MPRsm;

option EN01D; CL=0pF

-4

-

6

ns

MP+ss/MPRss; option

EN23; CL=0pF

-7

-

4

ns

MPss; option EN01;

CL=0pF

SDI bit time

t46 CC

8 * tMSC -

-

ns

Upstream Timing

SDI rise time 7)

t48 SR

-

-

200

ns

Upstream Timing

SDI fall time 7)

t49 SR

-

-

200

ns

Upstream Timing

1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA.

2) TA depends on the clock source selected for baud rate generation in the ABRA block of the MSC.

3) The capacitive load on the LVDS pins is differential, the capacitive load on the CMOS pins is single ended.

Data Sheet

3-413

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationMSC Timing 5 V Operation
4) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted if the ABRA block is used.
5) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite.
6) From FCLP rising edge. 7) When using slow and asymmetrical edges, like in case of open drain upstream connection, the application must take care
that the bit is long enough (the baud rate is low enough) so that under worst case conditions the three sampling points in the middle of the bit are not violated.

Data Sheet

3-414

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationMSC Timing 5 V Operation

Timing Options for t45
The wiring shown in the Figure 3-22 provides three useful timing options for t45. depending on the signals selected
with the alternate output lines (ALT1 to ALT7) in the ports:

· EN01 - FCLN, SON, EN0, EN1

- t45 reference timing

· EN01D - FCLND, SOND, EN0, EN1 - t45 window shifted to the left

· EN23 - FCLN, SON, EN2, EN3

- t45 window shifted to the right

The timings corresponding to EN01, EN01D, and EN23 are defined in the LVDS mode. In order to use the EN23

timings, the application should use the EN2 and EN3 outputs of the MSC module.

FCLP FCLN
SOP SON
EN0 EN1 EN2 EN3

ALT1 FCLN ALTx
ALTy FCLND
ALT7
ALT1 SON ALTx
ALTy SOND
ALT7
ALT1 ALTx ALTy

LVDSM
PAD LVDSM
PAD CMOS

ALT7
ALT1 ALTx ALTy

PAD CMOS

MSC
Figure 3-22 Timing Options for t45

ALT7

PAD _DoublePath_4a.vsd

Mapping B, CMOS MP Pads This timing applies for the dedicated CMOS pads, pin Mapping B: · MP strong sharp (MPss) output pads for the clock and the data signals · MP strong sharp or strong medium (MP+ss or MP+sm) output pads for enable signals

Table 3-76 MPss clock/data (LVDS pads in CMOS mode, option EN01)

Parameter

Symbol

Values

Unit

FCLPx clock period 1)

t40 CC

Deviation from ideal duty cycle t400 CC
4) 5)

Min.

Typ.

2 * TA 2) 3) -

-2

-

Max.

-

ns

3+0.035 * ns
CL

Note / Test Condition
MPss; CL=50pF MPss; 0 < CL < 100pF

Data Sheet

3-415

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationMSC Timing 5 V Operation

Table 3-76 MPss clock/data (LVDS pads in CMOS mode, option EN01) (cont'd)

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ.

Max.

SOPx output delay 6) ENx output delay 6)

t44 CC

-4

-

t45 CC

-6

-

-2

-

-4

-

0

-

7 7
16.5
10 32

ns

MPss; CL=50pF

ns

MP+ss/MPRss;

CL=50pF

ns

MP+sm/MPRsm;

CL=50pF

ns

MPss; CL=50pF

ns

MPsm; CL=50pF;

except pin P13.0

0

-

32

ns

MPsm; CL=50pF; pin

P13.0

5

-

45

ns

MPm/MP+m/MPRm;

CL=50pF

-11

-

7.5

ns

MP+ss/MPRss;

CL=0pF

-4

-

13

ns

MP+sm/MPRsm;

CL=0pF

-10

-

7

ns

MPss; CL=0pF

-1

-

22

ns

MPsm; CL=0pF

-2

-

25

ns

MP+m/MPm/MPRm;

CL=0pF

SDI bit time

t46 CC

8 * tMSC -

-

ns

Upstream Timing

SDI rise time 7)

t48 SR

-

-

200

ns

Upstream Timing

SDI fall time 7)

t49 SR

-

-

200

ns

Upstream Timing

1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA.

2) TA depends on the clock source selected for baud rate generation in the ABRA block of the MSC.

3) FCLP signal high and low can be minimum 1 * TMSC.

4) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can

be adjusted if the ABRA block is used.

5) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite.

6) From FCLP rising edge.

7) When using slow and asymmetrical edges, like in case of open drain upstream connection, the application must take care that the bit is long enough (the baud rate is low enough) so that under worst case conditions the three sampling points in the middle of the bit are not violated.

Table 3-77 MP+sm/MPRsm clock/data

Parameter

Symbol

FCLPx clock period 1)

t40 CC

Min.
2 * TA

Deviation from ideal duty cycle t400 CC

-3

2) 3)

Values

Unit

Typ.

Max.

-

-

ns

-

3+0.01 * ns

CL

Note / Test Condition
MP+sm/MPRsm;
CL=50pF
MP+sm/MPRsm; 0 <
CL < 200pF

Data Sheet

3-416

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationMSC Timing 5 V Operation

Table 3-77 MP+sm/MPRsm clock/data (cont'd)

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ.

Max.

SOPx output delay 4)

t44 CC

-5

-

7

ns

MP+sm; CL=50pF

ENx output delay 4)

t45 CC

-13

-

2 5)

ns

MPss; CL=50pF

-5

-

11

ns

MP+sm/MPRsm;

CL=50pF

1

-

25

ns

MPsm; CL=50pF

3

-

37

ns

MP+m/MPm/MPRm;

CL=50pF

-19

-

2

ns

MPss; CL=0pF

-13

-

8

ns

MP+sm; CL=0pF

-5

-

17

ns

MPsm; CL=0pF

-5

-

20

ns

MPm/MP+m/MPRm;

CL=0pF
1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA. 2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can
be adjusted if the ABRA block is used.

3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite.

4) From FCLP rising edge.

5) If EN1 is configured to P13.0 the max limt is increased by 0.5ns to 2.5ns.

Table 3-78 MPm/MP+m/MPRm clock/data

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ.

Max.

FCLPx clock period 1)

t40 CC

2 * TA

-

-

ns

MPm/MP+m/MPRm;

CL=50pF

Deviation from ideal duty cycle t400 CC

-16

-

2) 3)

SOPx output delay 4) ENx output delay 4)

t44 CC

-11

-

t45 CC

-13

-

4+0.04 * ns

CL

20

ns

24

ns

MPm/MP+m; 0 < CL <
200pF
MPm/MP+m; CL=50pF
MPm/MP+m/MPRm;
CL=50pF

-33

-

17

ns

MPm/MP+m/MPRm;

CL=0pF

1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA.

2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can

be adjusted if the ABRA block is used.

3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite.

4) From FCLP rising edge.

Data Sheet

3-417

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationMSC Timing 3.3 V Operation

t40 t400

FCLP

t44

t44

SOP

t45
EN

t45 t48

0.5 VEXT/FLEX
t49

SDI
t46 Figure 3-23 MSC Interface Timing

0.9 VEXT/FLEX 0.1 VEXT/FLEX

t46

MSC_Timing_A.vsd

Note: The SOP data signal is sampled with the falling edge of FCLP in the target device.

3.27

MSC Timing 3.3 V Operation

The following section defines the timings for 3.3V pad power supply.
Mapping A, Combo Pads in LVDS Mode or CMOS Mode The timing applies for the LVDS pads in LVDS operating mode: · The LVDSM output pads for clock and data signals set in LVDS mode · The CMOS MP pads for enable signals, with strong driver sharp edge (MPss) or strong driver medium edge
(MPsm).

Table 3-79 LVDS clock/data (LVDS pads in LVDS mode)

Parameter

Symbol

Values

FCLPx clock period 1)

t40 CC

Deviation from ideal duty cycle t400 CC
4) 5)

Min.

Typ.

2 * TA 2) 3) -

-2

-

Max. 2

SOPx output delay 6)

t44 CC

-5

-

5

-7

-

7

Unit Note / Test Condition

ns

LVDSM; CL=50pF

ns

LVDSM; 0 < CL < 50pF

ns

LVDSM; CL=50pF;

option EN01

ns

LVDSM; CL=50pF;

option EN01D

Data Sheet

3-418

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationMSC Timing 3.3 V Operation

Table 3-79 LVDS clock/data (LVDS pads in LVDS mode) (cont'd)

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ.

Max.

ENx output delay 6)

t45 CC

-7

-

9.5

ns

MP+ss/MPRss; option

EN01; CL=25pF

-5

-

13

ns

MP+ss/MPRss; option

EN01; CL=50pF

-5

-

26

ns

MP+sm/MPRsm;

option EN01D;

CL=50pF

-4

-

16

ns

MP+ss/MPRss; option

EN23; CL=25pF

-4

-

17

ns

MP+ss/MPRss; option

EN23; CL=50pF

-5

-

19

ns

MPss; option EN01;

CL=50pF

-12

-

5.5

ns

MP+ss/MPRss; option

EN01; CL=0pF

-9

-

11

ns

MP+sm/MPRsm;

option EN01D; CL=0pF

-7

-

9

ns

MP+ss/MPRss; option

EN23; CL=0pF

-12

-

7

ns

MPss; option EN01;

CL=0pF

SDI bit time

t46 CC

8 * tMSC -

-

ns

Upstream Timing

SDI rise time 7)

t48 SR

-

-

200

ns

Upstream Timing

SDI fall time 7)

t49 SR

-

-

200

ns

Upstream Timing

1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA.

2) TAmin = TMAX. When TMAX = 100 MHz,t40 = 20 ns

3) The capacitive load on the LVDS pins is differential, the capacitive load on the CMOS pins is single ended.

4) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can be adjusted if the ABRA block is used.

5) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite.

6) From FCLP rising edge.

7) When using slow and asymmetrical edges, like in case of open drain upstream connection, the application must take care

that the bit is long enough (the baud rate is low enough) so that under worst case conditions the three sampling points in the middle of the bit are not violated.

Mapping B, CMOS MP Pads This timing applies for the dedicated CMOS pads, pin Mapping B: · MP strong sharp (MPss) output pads for the clock and the data signals · MP strong sharp or strong medium (MPss or MPsm) output pads for enable signals

Data Sheet

3-419

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationMSC Timing 3.3 V Operation

Table 3-80 MPss clock/data (LVDS pads in CMOS mode, option EN01)

Parameter

Symbol

Values

Unit Note / Test Condition

FCLPx clock period 1)

t40 CC

Deviation from ideal duty cycle t400 CC
4) 5)

SOPx output delay 6) ENx output delay 6)

t44 CC t45 CC

Min.

Typ.

2 * TA 2) 3) -

-5

-

-7

-

-9

-

-4

-

-7

-

0

-

Max.

-

ns

7+0.07 * ns

CL

12

ns

12

ns

26

ns

17

ns

56

ns

MPss; CL=50pF MPss; 0 < CL < 100pF
MPss; CL=50pF
MP+ss/MPRss;
CL=50pF
MP+sm/MPRsm;
CL=50pF MPss; CL=50pF MPsm; CL=50pF;
except pin P13.0

0

-

58

ns

MPsm; CL=50pF; pin

P13.0

4

-

77

ns

MPm/MP+m/MPRm;

CL=50pF

-19

-

8

ns

MP+ss/MPRss;

CL=0pF

-7

-

19

ns

MP+sm/MPRsm;

CL=0pF

-17

-

8

ns

MPss; CL=0pF

-2

-

38

ns

MPsm; CL=0pF

-4

-

41

ns

MP+m/MPm/MPRm;

CL=0pF

SDI bit time

t46 CC

8 * tMSC -

-

ns

Upstream Timing

SDI rise time 7)

t48 SR

-

-

200

ns

Upstream Timing

SDI fall time 7)

t49 SR

-

-

200

ns

Upstream Timing

1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA.

2) TAmin = TMAX. When TMAX = 100 MHz,t40 = 20 ns

3) FCLP signal high and low can be minimum 1 * TMSC.

4) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can

be adjusted if the ABRA block is used.

5) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite.

6) From FCLP rising edge.

7) When using slow and asymmetrical edges, like in case of open drain upstream connection, the application must take care that the bit is long enough (the baud rate is low enough) so that under worst case conditions the three sampling points in the middle of the bit are not violated.

Data Sheet

3-420

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationMSC Timing 3.3 V Operation

Table 3-81 MP+sm/MPRsm clock/data

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ.

Max.

FCLPx clock period 1)

t40 CC

2 * TA

-

-

ns

MP+sm/MPRsm;

CL=50pF

Deviation from ideal duty cycle t400 CC

-6

-

2) 3)

SOPx output delay 4) ENx output delay 4)

t44 CC

-9

-

t45 CC

-20

-

7

ns

MP+sm/MPRsm; 0 <

CL < 200pF

12

ns

MP+sm; CL=50pF

4

ns

MPss; CL=50pF

-9

-

19

ns

MP+sm/MPRsm;

CL=50pF

0

-

44

ns

MPsm; CL=50pF

0

-

63

ns

MP+m/MPm/MPRm;

CL=50pF

-33

-

0

ns

MPss; CL=0pF

-23

-

9

ns

MP+sm/MPRsm;

CL=0pF

-9

-

28

ns

MPsm; CL=0pF

-9

-

31

ns

MPm/MP+m/MPRm;

CL=0pF

1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA.

2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can

be adjusted if the ABRA block is used.

3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite.

4) From FCLP rising edge.

Table 3-82 MPm/MP+m/MPRm clock/data

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ.

Max.

FCLPx clock period 1)

t40 CC

2 * TA

-

-

ns

MPm/MP+m/MPRm;

CL=50pF

Deviation from ideal duty cycle t400 CC
2) 3)

SOPx output delay 4) ENx output delay 4)

t44 CC t45 CC

-6-0.95 * -

CL

-19

-

-19

-

6+0.07 * ns

CL

34

ns

38

ns

MPm/MP+m/MPRm; 0
< CL < 200pF MPm/MP+m; CL=50pF
MPm/MP+m/MPRm;
CL=50pF

-57

-

27

ns

MPm/MP+m/MPRm;

CL=0pF

1) FCLP signal rise/fall times are the rise/fall times of the LVDSM pads, and the high/low times are min 1 * TA.

2) The PLL jitter is not included. It should be considered additionally, corresponding to the used baudrate. The duty cycle can

be adjusted if the ABRA block is used.

3) Positive deviation lenghtens the high time and shortens the low time of a clock period. Negative deviation does the opposite.

Data Sheet

3-421

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

4) From FCLP rising edge.

Electrical SpecificationMSC Timing 3.3 V Operation

t40 t400

FCLP

t44

t44

SOP

t45
EN

t45 t48

0.5 VEXT/FLEX
t49

SDI
t46 Figure 3-24 MSC Interface Timing

0.9 VEXT/FLEX 0.1 VEXT/FLEX

t46

MSC_Timing_A.vsd

Note: The SOP data signal is sampled with the falling edge of FCLP in the target device.

Data Sheet

3-422

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

3.28

Electrical SpecificationEthernet Interface (ETH) Characteristics
Ethernet Interface (ETH) Characteristics

3.28.1 ETH Measurement Reference Points

ETH Clock 1.4 V

1.4 V

2.0 V ETH I/O 0.8 V
tR
Figure 3-25 ETH Measurement Reference Points

2.0 V 0.8 V
tF
E TH_Tes tpoi nts.v s d

Data Sheet

3-423

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationEthernet Interface (ETH) Characteristics
3.28.2 ETH Management Signal Parameters (ETH_MDC, ETH_MDIO)

Table 3-83 ETH Management Signal Parameters

Parameter

Symbol

Min.

ETH_MDC period

t1 CC

400

ETH_MDC high time

t2 CC

160

ETH_MDC low time

t3 CC

160

ETH_MDIO setup time (output) t4 CC

10

ETH_MDIO hold time (output) t5 CC

10

ETH_MDIO data valid (input) t6 SR

0

Values Typ. -

Max. 300

Unit Note / Test Condition

ns

CL=25pF

ns

CL=25pF

ns

CL=25pF

ns

CL=25pF

ns

CL=25pF

ns

CL=25pF

ETH_MDC ETH_MDIO sourced by controller : ETH_MDC
ETH_MDIO (output )
ETH_MDIO sourced by PHY: ETH_MDC
ETH_MDIO (input )
Figure 3-26 ETH Management Signal Timing

t1

t3

t2

t4

t5

Valid Data

t6 Valid Data
E TH_Ti mi ng-Mgmt.v s d

Data Sheet

3-424

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationEthernet Interface (ETH) Characteristics

3.28.3 ETH MII Parameters
In the following, the parameters of the MII (Media Independent Interface) are described.

Table 3-84 ETH MII Signal Timing Parameters

Parameter

Symbol

Min.

Clock period

t7 SR

40

400

Clock high time

t8 SR

14 140 1)

Clock low time

t9 SR

14 140 1)

Input setup time

t10 SR

10

Input hold time

t11 SR

10

Output valid time

t12 CC

0

1) Defined by 35% of clock period.

2) Defined by 65% of clock period.

Values Typ. -

Max. -

-

-

-

26

-

260 2)

-

26

-

260 2)

-

-

-

-

-

25

Unit Note / Test Condition

ns

CL=25pF;

baudrate=100Mbps

ns

CL=25pF;

baudrate=10Mbps

ns

CL=25pF;

baudrate=100Mbps

ns

CL=25pF;

baudrate=10Mbps

ns

CL=25pF;

baudrate=100Mbps

ns

CL=25pF;

baudrate=10Mbps

ns

CL=25pF

ns

CL=25pF

ns

CL=25pF

ETH_MII_RX_CLK ETH_MII_TX_CLK
ETH_MII_RX_CLK
ETH_MII_RXD[3:0] ETH_MII_RX_DV ETH_MII_RX_ER (sourced by PHY )
ETH_MII_TX_CLK
ETH_MII_TXD[3:0] ETH_MII_TXEN
(sourced by controller )
Figure 3-27 ETH MII Signal Timing

t7

t9

t8

t1 0

t1 1

Valid Data

t1 2 Valid Data
ETH_Timing-MII.vsd

Data Sheet

3-425

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationEthernet Interface (ETH) Characteristics

3.28.4 ETH RMII Parameters
In the following, the parameters of the RMII (Reduced Media Independent Interface) are described.

Table 3-85 ETH RMII Signal Timing Parameters

Parameter

Symbol

Min.

ETH_RMII_REF_CL clock

t13 CC

20

period

ETH_RMII_REF_CL clock high t14 CC

7 1)

time

ETH_RMII_REF_CL clock low t15 CC

7 1)

time

ETHTXEN, ETHTXD[1:0],

t16 CC

4

ETHRXD[1:0], ETHCRSDV,

ETHRXER; setup time

ETHTXEN, ETHTXD[1:0],

t17 CC

2

ETHRXD[1:0], ETHCRSDV,

ETHRXER; hold time

1) Defined by 35% of clock period.

2) Defined by 65% of clock period.

Values Typ. -

Max. -

-

13 2)

-

13 2)

-

-

-

-

Unit Note / Test Condition

ns

CL=25pF; 50ppm

ns

CL=25pF

ns

CL=25pF

ns

CL=25pF

ns

CL=25pF

ETH_RMII_REF_CL

t1 3

t1 5

t14

ETH_RMII_REF_CL
ETHTXEN, ETHTXD[1:0], ETHRXD[1:0], ETHCRSDV,
ETHRXER
Figure 3-28 ETH RMII Signal Timing

t1 6

t17

Valid Data

ETH_Timing-RMII .vsd

Data Sheet

3-426

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationE-Ray Parameters

3.29

E-Ray Parameters

The timings of this section are valid for the strong driver and either sharp edge settings of the output drivers with
CL = 25 pF. For the inputs the hysteresis has to be configured to inactive.

Table 3-86 Transmit Parameters

Parameter

Symbol

Min.

Rise time of TxEN Fall time of TxEN

tdCCTxENRise2 -
5 CC
tdCCTxENFall25 -
CC

Sum of rise and fall time

tdCCTxRise25+ -
dCCTxFall25
CC

Sum of delay between TP1_FF tdCCTxEN01 -

and TP1_CC and delays

CC

derived from TP1_FFi, rising

edge of TxEN

Sum of delay between TP1_FF tdCCTxEN10 -

and TP1_CC and delays

CC

derived from TP1_FFi, falling

edge of TxEN

Asymmetry of sending
Sum of delay between TP1_FF and TP1_CC and delays derived from TP1_FFi, rising edge of TxD

ttx_asym CC
tdCCTxD01
CC

-2.45 -

Sum of delay between TP1_FF tdCCTxD10 -

and TP1_CC and delays

CC

derived from TP1_FFi, falling

edge of TxD

TxD signal sum of rise and fall ttxd_sum CC -
time at TP1_BD

Values Typ. -

Max. 9

-

9

-

9

-

25

-

25

-

2.45

-

25

-

25

-

9

Unit Note / Test Condition

ns

CL=25pF

ns

CL=25pF

ns

20% - 80%; CL=25pF

ns

ns

ns

CL=25pF

ns

ns

ns

Table 3-87 Receive Parameters

Parameter

Symbol

Min.

Acceptance of asymmetry at receiving part
Acceptance of asymmetry at receiving part
Threshold for detecting logical high

tdCCTxAsymAcc -30.5
ept25 SR

tdCCTxAsymAcc -31.5
ept15 SR

TuCCLogic1

35

SR

Threshold for detecting logical TuCCLogic0 30

low

SR

Values Typ. -

Max. 43.0

-

44.0

-

70

-

65

Unit Note / Test Condition

ns

CL=25pF

ns

CL=15pF

%

%

Data Sheet

3-427

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Table 3-87 Receive Parameters (cont'd)

Parameter

Symbol

Sum of delay between TP4_CC tdCCRxD01

and TP4_FF and delays

CC

derived from TP4_FFi, rising

edge of RxD

Sum of delay between TP1_CC tdCCRxD10

and TP1_CC and delays

CC

derived from TP4_FFi, falling

edge of RxD

Min. -
-

Electrical SpecificationE-Ray Parameters

Values Typ. -

Max. 10

Unit Note / Test Condition ns

-

10

ns

Data Sheet

3-428

V 1.0 2017-03

3.30

HSCT Parameters

TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationHSCT Parameters

Table 3-88 HSCT - Rx/Tx setup timing

Parameter

Symbol

RX o/p duty cycle Bias startup time

DCrx CC tbias CC

Min. 40 -

RX startup time TX startup time

trxi CC

-

ttx CC

-

Table 3-89 HSCT - Rx parasitics and loads

Parameter

Symbol

Min.

Capacitance total budget

Ctotal CC

-

Parasitic inductance budget Htotal CC -

Table 3-90 LVDSH - Reduced TX and RX (RED)

Parameter

Symbol

Min.

Output differential voltage

VOD CC

150

Output voltage high Output voltage low Output offset (Common mode) voltage

VOH CC VOL CC VOS CC

Input voltage range

VI SR

937 1.08
-

0.15

Input differential threshold

Vidth SR

-100

Data frequency

DR CC

5

Values Typ. 5

Max. 60 10

5

-

5

-

Values Typ. 3.5

Max. 5

5

-

Values Typ. 200

Max. 285

-

1463

-

-

1.2

1.32

-

1.6

-

-

-

100

-

320

Unit Note / Test Condition

%

µs

Bias distributor waking

up from power down

and provide stable

Bias.

µs

Wake-up RX from

power down.

µs

Wake-up TX from

power down.

Unit Note / Test Condition
pF Total Budget for complete receiver including silicon, package, pins and bond wire
nH

Unit Note / Test Condition

mV mV mV V V V mV
Mbps

Rt = 100 Ohm ±20% @2pF
Rt = 100 Ohm ±20%
Rt = 100 Ohm ±20%
Rt = 100 Ohm ±20% @2pF
Absolute max = 1.6 V + (285mV/2) = 1.743
Absolute min = 0.15 V (285 mV /2) = 0 V
100 mV for 55% of bit period; Note Absolute Value (Vidth - Vidthl)

Data Sheet

3-429

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationHSCT Parameters

Table 3-90 LVDSH - Reduced TX and RX (RED) (cont'd)

Parameter

Symbol

Values

Min.

Typ.

Receiver differential input

Rin CC

90

100

impedance

80

100

Slew rate

SRtx CC -

-

Change in VOS between 0 and dVOS CC -

-

1

Max. 110 120 2 50

Change in Vod between 0 and dVod CC -

-

50

1

Fall time 1)

tfall CC

0.26

-

1.2

Rise time 1)

trise CC

0.26

-

1.2

1) Rise / fall times are defined for 10% - 90% of VOD

Unit Note / Test Condition

Ohm Ohm V/ns mV
mV
ns ns

0 V < VI < 1.6V 1.6 V < VI < 2.0V
Peak to peak (including DC transients). Peak to peak (including DC transients) Rt = 100 Ohm ±20% @2pF Rt = 100 Ohm ±20% @2pF

Table 3-91 HSCT PLL Parameter

Symbol

PLL frequency range

fPLL CC

PLL input frequency

fREF CC

PLL lock-in time

tLOCK CC

Bit Error Rate based on 10 MHz BER10 CC
reference clock at Slave PLL

side

Min. 12.5 10 -

Bit Error Rate based on 20 MHz BER20 CC -
reference clock at Slave PLL
side

Absolute RMS Jitter (TX out) JABS10 CC -125

Absolute RMS Jitter (TX out) JABS20 CC -85

Values Typ. 320 -

Max. 320 20 50 10EXP-9

Unit
MHz MHz µs -

-

10EXP- -

12

-

125

ps

-

85

ps

Note / Test Condition
Bit Error Rate based on Slave interface reference clock at 10 MHz Bit Error Rate based on Slave interface reference clock at 20 MHz Measured at link TX out; valid for Reference frequency at 10 MHz Measured at link TX out; valid for Reference frequency at 20 MHz

Data Sheet

3-430

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Table 3-91 HSCT PLL (cont'd)

Parameter

Symbol

Accumulated RMS Jitter (RX JACC10 CC
side)

Min. -

Accumulated RMS Jitter (link JACC20 CC -
RX side)

Total Jitter peak to peak

TJpp CC

-

Table 3-92 HSCT Sysclk Parameter
Frequency Frequency error Duty Cycle Load impedance Load capacitance Integrated phase noise

Symbol
fSYSCLK CC dfERR CC DCsys CC RLOAD CC CLOAD CC IPN CC

Min. 10 -1 45 10 -

Electrical SpecificationHSCT Parameters

Values Typ. -

Max. 145

-

115

-

2083

Unit Note / Test Condition

ps

Measured at link RX

input, based on 5000

measures, each 300

clock cycles; valid for

Reference frequency

at 10 MHz

ps

Measured at link RX

input, based on 5000

measures, each 300

clock cycles; valid for

Reference frequency

at 20 MHz

ps

Total Jitter as sum of

deterministic jitter and

random jitter

Values Typ. -

Max. 20 1 55 10 -58

Unit Note / Test Condition
MHz % % kOhm pF dB single sideband phase
noise in 10 kHz to 10 Mhz at 20 MHz SysClk

Data Sheet

3-431

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationInter-IC (I2C) Interface Timing

3.31

Inter-IC (I2C) Interface Timing

This section defines the timings for I2C in the TC290 / TC297 / TC298 / TC299.

All I2C timing parameter are SR for Master Mode and CC for Slave Mode.

Table 3-93 I2C Standard Mode Timing

Parameter

Symbol

Fall time of both SDA and SCL t1

Min. -

Capacitive load for each bus Cb SR

-

line

Bus free time between a STOP t10

4.7

and ATART condition

Rise time of both SDA and SCL t2

-

Data hold time

t3

0

Data set-up time

t4

250

Low period of SCL clock

t5

4.7

High period of SCL clock

t6

4

Hold time for the (repeated) t7

4

START condition

Values Typ. -

Max. 300

-

400

-

-

-

1000

-

-

-

-

-

-

-

-

-

-

Unit Note / Test Condition

ns

Measured with a pull-

up resistor of 4.7

kohms at each of the

SCL and SDA line

pF

µs

Measured with a pull-

up resistor of 4.7

kohms at each of the

SCL and SDA line

ns

Measured with a pull-

up resistor of 4.7

kohms at each of the

SCL and SDA line

µs

Measured with a pull-

up resistor of 4.7

kohms at each of the

SCL and SDA line

ns

Measured with a pull-

up resistor of 4.7

kohms at each of the

SCL and SDA line

µs

Measured with a pull-

up resistor of 4.7

kohms at each of the

SCL and SDA line

µs

Measured with a pull-

up resistor of 4.7

kohms at each of the

SCL and SDA line

µs

Measured with a pull-

up resistor of 4.7

kohms at each of the

SCL and SDA line

Data Sheet

3-432

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationInter-IC (I2C) Interface Timing

Table 3-93 I2C Standard Mode Timing (cont'd)

Parameter

Symbol

Min.

Set-up time for (repeated)

t8

4.7

START condition

Set-up time for STOP condition t9

4

Values Typ. -

Max. -

-

-

Unit Note / Test Condition

µs

Measured with a pull-

up resistor of 4.7

kohms at each of the

SCL and SDA line

µs

Measured with a pull-

up resistor of 4.7

kohms at each of the

SCL and SDA line

Table 3-94 I2C Fast Mode Timing

Parameter

Symbol

Fall time of both SDA and SCL t1

Values

Min.

Typ.

20+0.1*C -

b

Max. 300

Capacitive load for each bus Cb SR

-

-

400

line

Bus free time between a STOP t10

1.3

-

-

and ATART condition

Rise time of both SDA and SCL t2

Data hold time

t3

20+0.1*C -

300

b

0

-

-

Data set-up time

t4

100

-

-

Low period of SCL clock

t5

1.3

-

-

High period of SCL clock

t6

0.6

-

-

Unit Note / Test Condition

ns

Measured with a pull-

up resistor of 4.7

kohms at each of the

SCL and SDA line

pF

µs

Measured with a pull-

up resistor of 4.7

kohms at each of the

SCL and SDA line

ns

Measured with a pull-

up resistor of 4.7

kohms at each of the

SCL and SDA line

µs

Measured with a pull-

up resistor of 4.7

kohms at each of the

SCL and SDA line

ns

Measured with a pull-

up resistor of 4.7

kohms at each of the

SCL and SDA line

µs

Measured with a pull-

up resistor of 4.7

kohms at each of the

SCL and SDA line

µs

Measured with a pull-

up resistor of 4.7

kohms at each of the

SCL and SDA line

Data Sheet

3-433

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationInter-IC (I2C) Interface Timing

Table 3-94 I2C Fast Mode Timing (cont'd)

Parameter

Symbol

Min.

Hold time for the (repeated) t7

0.6

START condition

Set-up time for (repeated)

t8

0.6

START condition

Set-up time for STOP condition t9

0.6

Values Typ. -

Max. -

-

-

-

-

Unit Note / Test Condition

µs

Measured with a pull-

up resistor of 4.7

kohms at each of the

SCL and SDA line

µs

Measured with a pull-

up resistor of 4.7

kohms at each of the

SCL and SDA line

µs

Measured with a pull-

up resistor of 4.7

kohms at each of the

SCL and SDA line

SDA SCL

t1

t2

70%

30 %

t1

t3

t7 S

t4 t2

SDA SCL

t8

t7

Sr

Figure 3-29 I2C Standard and Fast Mode Timing

t6 t5

9th clock t10

t9

9th clock

P

S

Data Sheet

3-434

V 1.0 2017-03

3.32

EBU Timings

TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationEBU Timings

3.32.1 BFCLKO Output Clock Timing
VSS = 0 V;VDD = 1.3 V ± 5%; VDDEBU = 2.5 V ± 5% and 3.3 V ± 5%,; CL = 35 pF

Table 3-95 BFCLK0 Output Clock Timing Parameters1)

Parameter

Symbol

Values

Unit Note /

Min.

Typ. Max.

Test Conditi on

BFCLKO clock period

tBFCLKO CC

13.332) ­

­

ns ­

BFCLKO high time

t5

CC

3

­

­

ns ­

BFCLKO low time

t6

CC

3

­

­

ns ­

BFCLKO rise time

t7

CC

­

­

3

ns ­

BFCLKO fall time

t8 CC

­

­

3

BFCLKO duty cycle t5/(t5 + t6)3)

DC

35

50

55

1) Not subject to production test, verified by design/characterization.

ns ­

%

­

2) The PLL jitter characteristics add to this value according to the application settings. See the PLL jitter parameters.

3) The PLL jitter is not included in this parameter. If the BFCLKO frequency is equal to fCPU, the K divider has to be regarded.

tBFCLKO

BFCLKO 0.5 VDDP05

t5

t6

t8

Figure 3-30 BFCLKO Output Clock Timing

0.9 VDD

t7

0.1 VDD

MCT04883_mod

3.32.2 EBU Asynchronous Timings
VSS = 0 V;VDD = 1.3 V ± 5%; VDDEBU = 2.5 V ± 5% and 3.3 V ± 5%, Class B pins; CL = 35 pF for address/data; CL = 40pF for the control lines.
For each timing, the accumulated PLL jitter of the programed duration in number of clock periods must be added
separately. Operating conditions apply and CL = 35 pF.

Table 3-96 Common Asynchronous Timings

Parameter

Symbol

Min.

AD(31:0) output delay to ADV# t13 CC

-5.5

rising edge, multiplexed read /

write

AD(31:0) output delay to ADV# t14 CC

-5.5

rising edge, multiplexed read /

write

Values Typ. -

Max. 2

Unit Note / Test Condition ns

-

2

ns

Data Sheet

3-435

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationEBU Timings

Table 3-96 Common Asynchronous Timings (cont'd)

Parameter

Symbol

Values

Min.

Typ.

Address valid to CS falling

t15 CC

-2

-

edge (deviation from

programmed value)

Address valid -> ADV falling t16 CC

-2

-

edge (deviation from

programmed value)

ADV falling edge -> CS falling t17 CC

-2

-

edge (deviation from

programmed value)

Pulse wdih deviation from the ta CC

-0.8

-

ideal programmed width due to

-0.8

-

pad asymmetry, rise delay - fall

delay

Max. 2
2
2
0.8 0.8

Unit Note / Test Condition ns

ns

ns

ns

edge=medium

ns

edge=sharp

Table 3-97 Asynchronous Read Timings

Parameter

Symbol

Min.

A(23:0) output delay to RD

t0 CC

-2.5

rising edge, deviation from the

ideal programmed value

AD(31:0) output delay to ADV# t13 CC

-2.5

rising edge, multiplexed read /

write

AD(31:0) output delay to ADV# t14 CC

-2.5

rising edge, multiplexed read /

write

Data input Hold from CS rising t18 CC

-4

edge

Data input Setup to CS rising t19 CC

12

edge

A(23:0) output delay to RD

t1 CC

-2.5

rising edge, deviation from the

ideal programmed value

CS rising edge to RD rising t2 CC

-2

edge, deviation from the ideal

programmed value

ADV rising edge to RD rising t3 CC

-1.5

edge, deviation from the ideal

programmed value

BC rising edge to RD rising t4 CC

-2.5

edge, deviation from the ideal

programmed value

Values Typ. -

Max. 2.5

Unit Note / Test Condition ns

-

10

ns

-

10

ns

-

-

ns

-

-

ns

-

2.5

ns

-

2.5

ns

-

4.5

ns

-

2.5

ns

Data Sheet

3-436

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationEBU Timings

Table 3-97 Asynchronous Read Timings (cont'd)

Parameter

Symbol

Min.

WAIT input setup to RD rising t5 SR

12

edge

WAIT input hold to RD rising t6 SR

0

edge

Data input setup to RD rising t7 SR

12

edge

Data input hold to RD rising t8 SR

0

edge

MR / W output delay to RD# t9 CC

-2.5

rising edge, deviation from the

ideal programmed value

Values Typ. -

Max. -

-

-

-

-

-

-

-

1.5

Unit Note / Test Condition ns ns ns ns ns

EBU STATE
Control Bitfield: Duration Limits in EBU_CLK Cycles
A[23:0]
CS[3:0] CSCOMB
ADV
RD/WR
BC[3:0]

Address Phase
ADDRC 1...15

Address Hold Command

Phase (opt.)

Phase

AHOLDC 0...15

RDWAIT 1...31

Data

Recovery New Addr.

Hold Phase Phase (opt.) Phase

DATAC 0...15

RDRECOVC 0...15

ADDRC 1...15

Valid Address

pv + t30

pv + ta

pv + ta

pv + t33

pv + t32

pv + t31

Next Addr.

pv + ta

pv + ta
pv + ta t34

WAIT AD[31:0]

t14 pv + t13
Address Out

t35

t36

t37

pv + t38

Data Out

MR/W

pv + t39

pv = programmed value, TEBU_CLK * sum (correponding bitfield values)

new_MuxWR_Async_10.vsd

Figure 3-31 Multiplexed Read Access Data Sheet

3-437

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationEBU Timings

EBU STATE
Control Bitfield: Duration Limits in EBU_CLK Cycles
A[23:0]
CS[3:0] CSCOMB
ADV
RD/WR
BC[3:0]

Address Phase
ADDRC 1...15

Address Hold Command

Phase (opt.)

Phase

AHOLDC 0...15

RDWAIT 1...31

Data

Recovery New Addr.

Hold Phase Phase (opt.)

Phase

DATAC 0...15

RDRECOVC 0...15

ADDRC 1...15

Valid Address

pv + t30

pv + ta

pv + ta

pv + t33

pv + t32

pv +t31

Next Addr.

pv + ta

pv + ta
pv + ta t34

WAIT AD[31:0]

t35

t36

t37

pv + t38

Data Out

MR/W

pv + t39

pv = programmed value, TEBU_CLK * sum (correponding bitfield values)

new_DemuxWR_Async_10.vsd

Figure 3-32 Demultiplexed Read Access

Table 3-98 Asynchronous Write Timings

Parameter

Symbol

Min.

A(23:0) output delay to WR t30 CC

-2.5

rising edge, deviation from the

ideal programmed value

A(23:0) output delay to WR t31 CC

-2.5

rising edge, deviation from the

ideal programmed value

CS rising edge to WR rising t32 CC

-2

edge, deviation from the ideal

programmed value

Values Typ. -

Max. 2.5

Unit Note / Test Condition ns

-

2.5

ns

-

2

ns

Data Sheet

3-438

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationEBU Timings

Table 3-98 Asynchronous Write Timings (cont'd)

Parameter

Symbol

Min.

ADV rising edge to WR rising t33 CC

-2.5

edge, deviation from the ideal

programmed value

BC rising edge to WR rising t34 CC

-2.5

edge, deviation from the ideal

programmed value

WAIT input setup to WR rising t35 SR

12

edge, deviation from the ideal

programmed value

WAIT input hold to WR rising t36 CC

0

edge, deviation from the ideal

programmed value

Data output delay to WR rising t37 CC

-5.5

edge, deviation from the ideal

programmed value

Data output delay to WR rising t38 CC

-5.5

edge, deviation from the ideal

programmed value

MR / W output delay to WR t39 CC

-2.5

rising edge, deviation from the

ideal programmed value

Values Typ. -

Max. 2

-

2

-

-

-

-

-

10

-

2

-

1.5

3.32.3 EBU Burst Mode Access Timing
VSS = 0 V;VDD = 1.3 V ± 5%; VDDEBU = 2.5 V ± 5% and 3.3 V ± 5%; CL = 35 pF;

Table 3-99 Burst Read Timings

Parameter

Symbol

Output delay from BFCLKO rising edge

t10 CC

D(31:0) Output delay from BFCLKO rising edge

t10a CC

RD and RD/WR active/inactive t12 CC
after BFCLKO active edge

CSx output delay from BFCLKO active edge

t21 CC

ADV active/inactive after BFCLKO active edge

t22 CC

BAA active/inactive after BFCLKO active edge

t22a CC

Data setup to BFCLKI rising edge

t23 SR

Min. -2 -2 -2 -2.5 -2 -2.5 3

Values Typ. -

Max. 2

-

10

-

2

-

1.5

-

2

-

4.5

-

-

Data Sheet

3-439

Unit Note / Test Condition ns ns ns ns ns ns ns
Unit Note / Test Condition ns ns ns ns ns ns ns
V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Table 3-99 Burst Read Timings (cont'd)

Parameter

Symbol

Data hold from BFCLKI rising edge
WAIT setup (low or high) to BFCLKI rising edge
WAIT hold (low or high) from BFCLKI rising edge

t24 SR t25 SR t26 SR

Min. 0
3
0

Electrical SpecificationEBU Timings

Values Typ. -

Max. -

-

-

-

-

Unit Note / Test Condition ns ns ns

BFCLKI 1) BFCLKO A[23:0]

Address Phase(s)
t10

Command Phase(s)

Burst Phase(s)

Burst Phase(s)

Burst Start Address

t22

t22

ADV

Recovery Next Addr. Phase(s) Phase(s)
t10
Next Addr.
t22

t21
CS[3:0] CSCOMB
t12
RD RD/WR
t22a
BAA

t21

t21

t12

t22a

D[31:0] (32-Bit)

t24 t23
Data (Addr+0)

t24 t23
Data (Addr+4)

D[15:0] (16-Bit)
WAIT

t26 t25

Data (Addr+0) Data (Addr+2)

1) Output delays are always referenced to BCLKO. The reference clock for input characteristics depends on bit EBU_BFCON.FDBKEN. EBU_BFCON.FDBKEN = 0: BFCLKO is the input reference clock. EBU_BFCON.FDBKEN = 1: BFCLKI is the input reference clock (EBU clock feedback enabled).
Figure 3-33 EBU Burst Mode Read / Write Access Timing

BurstRDWR_4.vsd

Data Sheet

3-440

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationEBU Timings

3.32.4 EBU Arbitration Signal Timing
VSS = 0 V;VDD = 1.5 V ± 5%; VDDEBU = 2.5 V ± 5% and 3.3 V ± 5% ; TA = -40°C to +125°C; CL = 35 pF;

Table 3-100 EBU Arbitration Timings

Parameter

Symbol

Output delay from BFCLKO rising edge

t27 CC

Data setup to BFCLKO falling t28 SR
edge

Data hold from BFCLKO falling t29 SR
edge

Min. -
15
2

Values Typ. -

Max. 4.5

-

-

-

-

Unit Note / Test Condition ns ns ns

B FCL K O

t27

t27

HLDA Output

t27

t27

BREQ Output

B FCL K O

t28

t28

t29

t29

HOLD Input

HLDA Input

Figure 3-34 EBU Arbitration Signal Timing

EBUArb_1

Data Sheet

3-441

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationCIF Parameters

3.33

CIF Parameters

CIF timings are valid only for temperatures up the TJ = 150°C.

Table 3-101 Timings for 5V Parameter

Symbol

Pixel clock period HSYNC, VSYNC set up time

t70 SR t71 SR

Min. 10.42 2.5

Values Typ. -

Max. -

2

-

-

6.5

-

-

4

-

-

HSYNC, VSYNC hold time

t72 SR

2.5

-

-

2.5

-

-

7

-

-

4

-

-

Pixel data set up time

t73 SR

2.5

-

-

2

-

-

6.5

-

-

4

-

-

Pixel data hold time

t74 SR

2.5

-

-

2.5

-

-

7

-

-

4

-

-

Unit Note / Test Condition

ns

96 MHz

ns

AL input level,

hysteresis bypass

ns

TTL input level,

hysteresis bypass

ns

TTL input level,

hysteresis on

ns

AL input level,

hysteresis on

ns

AL input level,

hysteresis bypass

ns

TTL input level,

hysteresis bypass

ns

TTL input level,

hysteresis on

ns

AL input level,

hysteresis on

ns

AL input level,

hysteresis bypass

ns

TTL input level,

hysteresis bypass

ns

TTL input level,

hysteresis on

ns

AL input level,

hysteresis on

ns

AL input level,

hysteresis bypass

ns

TTL input level,

hysteresis bypass

ns

TTL input level,

hysteresis on

ns

AL input level,

hysteresis on

Data Sheet

3-442

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationCIF Parameters

Table 3-102 Timings for 3.3V

Parameter

Symbol

Pixel clock period HSYNC, VSYNC set up time

t70 SR t71 SR

Min. 10.42 3.5
4.5

9

3

HSYNC, VSYNC hold time

t72 SR

4

5

10

3.5

Pixel data set up time

t73 SR

3.5

4.5

9

3

Pixel data hold time

t74 SR

4

5

10

3.5

Values Typ. -

Max. -

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Table 3-103 Timings for 0.4V to 2.4V input signals (2.8V imager)

Parameter

Symbol

Values

Min.

Typ.

Max.

Pixel clock period

t70 SR

10.42

-

-

Unit Note / Test Condition

ns

ns

AL input level,

hysteresis bypass

ns

AL input level,

hysteresis on

ns

TTL input level,

hysteresis on

ns

TTL input level,

hysteresis bypass

ns

AL input level,

hysteresis bypass

ns

AL input level,

hysteresis on

ns

TTL input level,

hysteresis on

ns

TTL input level,

hysteresis bypass

ns

AL input level,

hysteresis bypass

ns

AL input level,

hysteresis on

ns

TTL input level,

hysteresis on

ns

TTL input level,

hysteresis bypass

ns

AL input level,

hysteresis bypass

ns

AL input level,

hysteresis on

ns

TTL input level,

hysteresis on

ns

TTL input level,

hysteresis bypass

Unit Note / Test Condition ns

Data Sheet

3-443

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationCIF Parameters

Table 3-103 Timings for 0.4V to 2.4V input signals (2.8V imager) (cont'd)

Parameter

Symbol

Values

Min.

Typ.

Max.

HSYNC, VSYNC set up time t71 SR

3

-

-

9

-

-

4.5

-

-

HSYNC, VSYNC hold time

t72 SR

3.5

-

-

10

-

-

5

-

-

Pixel data set up time

t73 SR

3

-

-

9

-

-

4.5

-

-

Pixel data hold time

t74 SR

3.5

-

-

10

-

-

5

-

-

Unit ns ns ns ns ns ns ns ns ns ns ns ns

Note / Test Condition
Hysteresis Bypass, 3.3V±10% TTL Input Levels, 3.3V±10% TTL Input Levels, 5V±10% Hysteresis Bypass, 3.3V±10% TTL Input Levels, 3.3V±10% TTL Input Levels, 5V±10% Hysteresis Bypass, 3.3V±10% TTL Input Levels, 3.3V±10% TTL Input Levels, 5V±10% Hysteresis Bypass, 3.3V±10% TTL Input Levels, 3.3V±10% TTL Input Levels, 5V±10%

Table 3-104 Timings for 0.4V to 2.4V input signals (2.8V imager), ±5% pad power supply

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ.

Max.

Pixel clock period

t70 SR

10.42

-

-

ns

HSYNC, VSYNC set up time t71 SR

3

-

-

ns

Hysteresis Bypass,

3.3V±5%

9

-

-

ns

TTL Input Levels,

3.3V±5%

4.5

-

-

ns

TTL Input Levels,

5V±5%

HSYNC, VSYNC hold time

t72 SR

3.5

-

-

ns

Hysteresis Bypass,

3.3V±5%

10

-

-

ns

TTL Input Levels,

3.3V±5%

5

-

-

ns

TTL Input Levels,

5V±5%

Data Sheet

3-444

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationCIF Parameters

Table 3-104 Timings for 0.4V to 2.4V input signals (2.8V imager), ±5% pad power supply (cont'd)

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ.

Max.

Pixel data set up time

t73 SR

3

-

-

ns

Hysteresis Bypass,

3.3V±5%

9

-

-

ns

TTL Input Levels,

3.3V±5%

4.5

-

-

ns

TTL Input Levels,

5V±5%

Pixel data hold time

t74 SR

3.5

-

-

ns

Hysteresis Bypass,

3.3V±5%

10

-

-

ns

TTL Input Levels,

3.3V±5%

5

-

-

ns

TTL Input Levels,

5V±5%

Table 3-105 Timings for 1.8V imager, TTL input level

Parameter

Symbol

Values

Min.

Typ.

Pixel clock period HSYNC, VSYNC set up time

t70 SR t71 SR

10.42

-

3

-

Max. -

9

-

-

4.5

-

-

3.5

-

-

HSYNC, VSYNC hold time

t72 SR

3.5

-

-

10

-

-

5

-

-

4

-

-

Pixel data set up time

t73 SR

3

-

-

9

-

-

4.5

-

-

3.5

-

-

Unit Note / Test Condition

ns

ns

Input signal 0.1V to

1.7V

ns

Input signal 0.2V to

1.6V

ns

Input signal 0.3V to

1.5V

ns

Input signal 0.4V to

1.4V

ns

Input signal 0.1V to

1.7V

ns

Input signal 0.2V to

1.6V

ns

Input signal 0.3V to

1.5V

ns

Input signal 0.4V to

1.4V

ns

Input signal 0.1V to

1.7V

ns

Input signal 0.2V to

1.6V

ns

Input signal 0.3V to

1.5V

ns

Input signal 0.4V to

1.4V

Data Sheet

3-445

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationCIF Parameters

Table 3-105 Timings for 1.8V imager, TTL input level (cont'd)

Parameter

Symbol

Values

Min.

Typ.

Pixel data hold time

t74 SR

3.5

-

Max. -

10

-

-

5

-

-

4

-

-

Unit Note / Test Condition

ns

Input signal 0.1V to

1.7V

ns

Input signal 0.2V to

1.6V

ns

Input signal 0.3V to

1.5V

ns

Input signal 0.4V to

1.4V

Table 3-106 Timings for 1.8V imager, 3.3V±5% pad power supply, TTL input level

Parameter

Symbol

Values

Unit

Min.

Typ.

Max.

Pixel clock period

t70 SR

10.42

-

-

ns

HSYNC, VSYNC set up time t71 SR

3

-

-

ns

9

-

-

ns

4.5

-

-

ns

3.5

-

-

ns

HSYNC, VSYNC hold time

t72 SR

3.5

-

-

ns

10

-

-

ns

5

-

-

ns

4

-

-

ns

Pixel data set up time

t73 SR

3

-

-

ns

9

-

-

ns

4.5

-

-

ns

3.5

-

-

ns

Note / Test Condition
Input signal 0.1V to 1.7V Input signal 0.2V to 1.6V Input signal 0.3V to 1.5V Input signal 0.4V to 1.4V Input signal 0.1V to 1.7V Input signal 0.2V to 1.6V Input signal 0.3V to 1.5V Input signal 0.4V to 1.4V Input signal 0.1V to 1.7V Input signal 0.2V to 1.6V Input signal 0.3V to 1.5V Input signal 0.4V to 1.4V

Data Sheet

3-446

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationCIF Parameters

Table 3-106 Timings for 1.8V imager, 3.3V±5% pad power supply, TTL input level (cont'd)

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ.

Max.

Pixel data hold time

t74 SR

3.5

-

-

ns

Input signal 0.1V to

1.7V

10

-

-

ns

Input signal 0.2V to

1.6V

5

-

-

ns

Input signal 0.3V to

1.5V

4

-

-

ns

Input signal 0.4V to

1.4V

Data Sheet

3-447

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationFlash Target Parameters

3.34

Flash Target Parameters

Program Flash program and erase operation is only allowed up the TJ = 150°C. Flash timing parameter are valid for fFSI = 100 MHz.

Table 3-107 FLASH Parameter

Symbol

Program Flash Erase Time per tERP CC
logical sector

Min. -

Program Flash Erase Time per tMERP CC -
Multi-Sector Command
-

Program Flash program time tPRP5 CC -
per page in 5 V mode

Program Flash program time tPRP3 CC -
per page in 3.3 V mode

Program Flash program time tPRPB5 CC -
per burst in 5 V mode

Program Flash program time tPRPB3 CC -
per burst in 3.3 V mode

Program Flash program time tPRPB5_1MB -

for 1 MByte with burst

CC

programming in 5 V mode

excluding communication

Program Flash program time tPRPB5_PF -
for complete PFlash with burst CC programming in 5 V mode excluding communication

Write Page Once adder

tADD CC

-

Values

Typ.

Max.

-

1

0.207 + -
0.003 * (S
[KByte]) /
(fFSI
[MHz])1)

-

1

Unit s s
s

0.207 + -

s

0.003 * (S

[KByte]) /

(fFSI
[MHz])1)

-

50 +

µs

3000/(fFSI
[MHz])

-

81 +

µs

3400/(fFSI
[MHz])

-

125 + µs

9500/(fFSI
[MHz])

-

410 + µs

12000/(fF
SI [MHz])

-

0.9

s

-

7.2

s

-

15 +

µs

500/(fFSI
[MHz])

Note / Test Condition
cycle count < 1000 cycle count < 1000, for sector of size S
For consecutive logical sectors in a physical sector, cycle count < 1000 For consecutive logical sector range of size S in a physical sector, cycle count < 1000
32 Byte
32 Byte
256 Byte
256 Byte
Derived value for documentation
purpose, valid for fFSI =
100MHz Derived value for documentation
purpose, valid for fFSI =
100MHz Adder to Program Time when using Write Page Once

Data Sheet

3-448

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationFlash Target Parameters

Table 3-107 FLASH (cont'd) Parameter

Symbol

Program Flash suspend to read tSPNDP CC
latency

Min. -

Data Flash Erase Time per

tERD CC

-

Sector 2)

-

Data Flash Erase Time per Multi-Sector Command 2)

tMERD CC -

-

Data Flash erase disturb limit NDFD CC -

Program time data flash per tPRD CC

-

page 3)

Complete Device Flash Erase tER_Dev CC -
Time PFlash and DFlash 4)

Data Flash program time per tPRDB CC -
burst 3)

Data Flash suspend to read latency

tSPNDD CC -

Wait time after margin change tFL_MarginDel -
CC

Program Flash Retention Time, tRET CC

20

Sector

Data Flash Endurance per EEPROMx sector 5)

NE_EEP10
CC

125000

Data Flash Endurance per HSMx sector 5)

NE_HSM CC 125000

Values

Unit Note / Test Condition

Typ.

Max.

-

12000/(fF µs

For Write Burst, Verify

SI [MHz])

Erased and for multi-

(logical) sector erase

commands

0.12 + -
0.08/(fFSI
[MHz])1)

s

cycle count < 1000

0.57 + 0.928 + s
0.15/(fFSI 0.15/(fFSI
[MHz])1) [MHz])

cycle count < 125000

0.12 + -
0.01 * (S
[KByte]) /
(fFSI
[MHz])1)

s

For consecutive logical

sector range of size S,

cycle count < 1000

0.57 + 0.928 + s

0.019 * (S 0.019 * (S

[KByte]) / [KByte]) /

(fFSI

(fFSI

[MHz])1) [MHz])

For consecutive logical sector range of size S, cycle count < 125000

-

50

cycles

-

50 +

µs

8 Byte

2500/(fFSI
[MHz]) 3)

-

17

s

Derived value for

documentation

purpose (excl. UCBs

and HSMs), valid for

fFSI = 100MHz

-

96 +

µs

32 Bytes

4400/(fFSI
[MHz]) 3)

-

12000/(fF µs

SI [MHz])

-

10

µs

-

-

years Max. 1000

erase/program cycles

-

-

cycles Max. data retention

time 10 years

-

-

cycles Max. data retention

time 10 years

Data Sheet

3-449

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationFlash Target Parameters

Table 3-107 FLASH (cont'd)

Parameter

Symbol

Values

Unit Note / Test Condition

Min.

Typ.

Max.

UCB Retention Time

tRTU CC

20

-

-

years Max. 100

erase/program cycles

per UCB, max 400

erase/program cycles

in total

Data Flash access delay

tDF CC

-

-

100

ns

see

PMU_FCON.WSDFLA

SH

Data Flash ECC Delay

tDFECC CC -

-

20

ns

see

PMU_FCON.WSECD

F

Program Flash access delay tPF CC

-

-

30

ns

see

PMU_FCON.WSPFLA

SH

Program Flash ECC delay

tPFECC CC -

-

10

ns

see

PMU_FCON.WSECP

F

Number of erase operations on NERD0 CC -

-

750000 cycles

DF0 over lifetime

Number of erase operations on NERD1 CC -

-

500000 cycles

DF1 over lifetime

Junction temperature limit for TJPFlash SR -

-

150

°C

PFlash program/erase

operations

1) All typical values were characterised, but are not tested. Typical values are safe median values at room temperature

2) Under out-of-spec conditions (e.g. over-cycling) or in case of activation of WL oriented defects, the duration of erase processes may be increased by up to 50%.

3) Time is not dependent on program mode (5V or 3.3V).

4) Using 512 KByte erase commands.

5) Only valid when a robust EEPROM emulation algorithm is used. For more details see the Users Manual.

Data Sheet

3-450

V 1.0 2017-03

3.35

Package Outline

TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationPackage Outline

1 7 ±0.1 SEATIN G PLAN E

B

17 ±0. 1

A

CODE

292 x 0.15
COPLANARITY

INDEX MARKING (LASERED )
C
Figure 3-35 Package Outlines LF-BGA-292-6

1 .7 MAX

0 .5 ±0.05

292 x
0.15 M C A B 0.08 M C

0.1 C
0.8 0.33 MIN STANDOFF

0.8 19 x 0 .8 = 1 5.2

Y W V U T R P N ML K J HG F E D C B A

20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
INDEX

19 x 0.8 = 15 .2

MARKING

27
CODE
INDEX MARKING (LASERED )

27
C SEATIN G PL ANE

d 0.1 2 x

25 x 1 .0 = 25

A

B

2x d 0 .1

2 .15 MAX

(0.56)

1.0

(0.95 )

416 x 0.15 C COPLANARITY

0.1 C

0.63+-00..1073

416 x
0 .25 M C A B 0.1 M C

26
25 24 23
22 21 20
19 18
17 16 15 14 13
12 11 10 9
8 7 6
5 4 3 2
1

0 ,41 MIN STAND OFF

AF AD AB Y W V U T R P N M L K J H G F E D C B A AE AC AA
1.0

Figure 3-36 Package Outlines PG-BGA-416-26

Data Sheet

3-451

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step

Electrical SpecificationPackage Outline

25 ±0.1
CODE
INDEX MARKING (LASERED )

25 ±0.1

d 0.1 2 x

A

B

2x d 0.1

5 16x 0.15 COPLANARITY

C SEATIN G PL ANE

1.7 MAX

29 x 0.8 = 23.2

0.1 C

0.5 ±0.05

516 x

0 .8

0 .1 5 M C A B

0.08 M C

30

29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3

2 1

AJ AG AE AC AA Y W V U T R P N M L K J H G F E D C B A AK AH AF AD AB
0.8

0.8
INDEX MARKING

2 9 x 0 .8 = 23 .2

0 ,3 MIN

STAND OFF

Figure 3-37 Package Outlines PG-LFBGA-516-5

You can find all of our packages, sorts of packing and others in our Infineon Internet Page "Products": http://www.infineon.com/products.

3.35.1 Package Parameters

Table 3-108 Thermal Characteristics of the Package

Device

Package

RQJCT1) RQJCB1) RQJA

Unit

Note

TC297

LF-BGA-292-6

3,0

4,3

15,1

K/W

TC298

PG-BGA-416-26

2,9

5,4

12,8

K/W

TC299

PG-LFBGA-516-5

2,8

4,3

15,1

K/W

1) The top and bottom thermal resistances between the case and the ambient (RTCAT, RTCAB) are to be combined with the thermal resistances between the junction and the case given above (RTJCT, RTJCB), in order to calculate the total thermal resistance between the junction and the ambient (RTJA). The thermal resistances between the case and the ambient (RTCAT, RTCAB) depend on the external system (PCB, case) characteristics, and are under user responsibility. The junction temperature can be calculated using the following equation: TJ = TA + RTJA * PD, where the RTJA is the total thermal resistance between the junction and the ambient. This total junction ambient resistance RTJA can be obtained from the upper four partial thermal resistances.
Thermal resistances as measured by the 'cold plate method' (MIL SPEC-883 Method 1012.1).

3.35.2 TC290 Carrier Tape

Data Sheet

3-452

V 1.0 2017-03

TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationPackage Outline

Figure 3-38 Carrier Tape Dimenions

Table 3-109 TC290 Chip Dimenions

Device

A

TC290

8,770 mm

B 9,357 mm

T 0,3 mm

Data Sheet

3-453

V 1.0 2017-03

3.36

Quality Declarations

TC290 / TC297 / TC298 / TC299 BC-Step
Electrical SpecificationQuality Declarations

Table 3-110 Quality Parameters

Parameter

Symbol

Operation Lifetime

tOP

ESD susceptibility according to VHBM
Human Body Model (HBM)

ESD susceptibility of the LVDS VHBM1
pins

ESD susceptibility according to VCDM
Charged Device Model (CDM)

Min. -
-
-

-

Moisture Sensitivity Level

MSL

-

Values Typ. -

Max. 24500 2000

-

500

Unit Note / Test Condition

hour V
V

Conforming to JESD22-A114-B

-

500

V

for all other balls/pins;

conforming to

JESD22-C101-C

-

750

V

for corner balls/pins;

conforming to

JESD22-C101-C

-

3

Conforming to Jedec J-STD--020C for 240C

Data Sheet

3-454

V 1.0 2017-03

4

History

TC290 / TC297 / TC298 / TC299 BC-Step
HistoryChanges from TC29xBB_v1.1 to TC29xBC_v1.0

4.1

Changes from TC29xBB_v1.1 to TC29xBC_v1.0

· VADC
­ Add parameter tWU ­ Add parameter RMDU ­ Add parameter RMDD
· Changes in table 'Class LP 3.3V' of Standard_Pads
­ Change note of VILHLP from 'Hysteresis inactive; not available for P14.2, P14.4, and P15.1' to 'Hysteresis
inactive; not available for P14.2, P14.4, P15.1, P15.10 and P15.11'
· Changes in table 'Class LP 5V' of Standard_Pads
­ Change note of VILHLP from 'Hysteresis inactive; not available for P14.2, P14.4, and P15.1' to 'Hysteresis
inactive; not available for P14.2, P14.4, P15.1, P15.10 and P15.11'
· ERAY
­ Add statement `The timings of this section are valid for the strong driver and either sharp edge settings of
the output drivers with CL = 25 pF. For the inputs the hysteresis has to be configured to inactive.'
· Package Outline
­ change values in table `TC290 Chip Dimenions'

Data Sheet

455

V 1.0 2017-03

www.infineon.com Published by Infineon Technologies AG