Home › PCIe Reference Clock Jitter Measurements for Gen5 and Beyond

PCIe Reference Clock Jitter Measurements for Gen5 and Beyond

File info: application/pdf · 22 pages · 1.42MB

16-bit, low power consumption, 45.5 μA/MHz, general purpose

Full PDF Document

If the inline viewer fails, it will open the original document in compatibility mode automatically. You can also open the file directly.

Extracted Text

White Paper
PCI Express� Clocks
PCIe Reference Clock Jitter Measurements for Gen5 and Beyond
Ron Wade, System Architect, Data Center Business Division John Hsu, Senior Manager, Electrical Design Engineering Joe Tajnai, Manager, Product Engineering
Introduction
Peripheral Component Interconnect (PCI) was a parallel address/data bus specified with time-domain electrical parameters such as set-up/hold times and cycle-to-cycle jitter. The ideal measurement instrument for these time-domain parameters was (and is) a digital sampling oscilloscope (DSO), sometimes referred to as a real-time oscilloscope. PCI used 3.3V LVCMOS signaling, and used spread-spectrum clocking (SSC) techniques to minimize EMI.
PCI Express (PCIe) superseded PCI by introducing serial communication links in place of the parallel address/data buses. Frequency-domain parameters such as phase jitter became very important, although PCIe Gen1 did not initially recognize this. PCIe also introduced �0.7V differential HCSL signaling levels. HCSL helped reduce EMI from the clock, and SSC remained the default for most PCIe systems. The PCIe ecosystem developed procedures for gathering time-domain information (clock period files) with DSOs and calculating clock phase jitter.
This methodology is unique to PCIe, as is the use of SSC with serial communication links. Other serial communication interfaces use Phase Noise Analyzers (PNAs) to measure phase noise; that is, other protocols use a frequency domain instrument to measure frequency domain parameters. Other serial protocols do not use SSC. Until recently, PNAs could not measure spreadspectrum clocks � that is no longer the case. PNAs are now available that can measure spread-spectrum clocks and provide dBc/Hz CSV files for post processing.
Unfortunately, as PCIe data rates increase and reference clock (Refclk) jitter budgets shrink, we can no longer ignore the intrinsic jitter of our measurement setup. We define "intrinsic jitter" as jitter originating or due to causes or factors wholly within a system. In theory, we may obtain the intrinsic jitter of a measurement setup by measuring a "noiseless" device. The results are the intrinsic jitter of the measurement setup. Ideally, we can then remove the intrinsic jitter from our measurements.
Note: We use the term "noiseless" to mean "noiseless" with respect to PCIe Gen5 (and Gen6).
This white paper:
1. Identifies two "noiseless" PCIe Refclk sources and calculates their theoretical PCIe Gen5 jitter limits
2. Measures a noiseless PCIe Refclk source with a PNA and a DSO, and compares the results
3. Measures a noiseless PCIe Refclk source at various slew rates with a PNA and a DSO, and compares the results
4. Measures a fan-out buffer and attempts to remove DSO intrinsic jitter from the results
5. Measures a clock generator and attempts to remove DSO intrinsic jitter from the results
Note: In the interest of brevity, this document focuses exclusively on the 32GT/s Gen5 Common Clocked (CC) specifications. The document applies to all current and future PCIe data rates.

Aug.5.20

Page 1

PCIe Reference Clock Jitter Measurements for Gen5 and Beyond

White Paper

Contents
1. "Noiseless" Sources ................................................................................................................................................... 3
1.1 Noiseless Ultra-Low Noise Crystal Oscillators (ULNXO) ........................................................................................................... 3 1.2 Noiseless Programmable RF and Microwave Signal Generators (RFSG)................................................................................. 4
2. Measuring the Noiseless Refclk Source.....................................................................................................................5
2.1 Measurement Setup ................................................................................................................................................................... 5 2.2 PNA Measurement Results ........................................................................................................................................................ 6 2.3 DSO Measurement Results ....................................................................................................................................................... 7
3. Measuring the Noiseless Refclk for Various Slew Rates............................................................................................9
3.1 Measurement Setup for Various Slew Rates ............................................................................................................................. 9 3.2 PNA Measurement Results for Various Slew Rates ................................................................................................................ 10 3.3 DSO Measurement Results for Various Slew Rates ................................................................................................................ 11
4. Removing DSO Intrinsic Noise Using an RFSG as a Noiseless Source ..................................................................12
4.1 Measuring Additive Jitter of a Fan-out Buffer Using a PNA ..................................................................................................... 12 4.2 Measuring Additive Jitter of a Fan-out Buffer using a DSO ..................................................................................................... 13 4.3 A Formula to Remove DSO Intrinsic Noise Due to Slew Rate ................................................................................................. 14 4.3.1 Applying the Noise Removal Formula to the Additive Jitter of a Fan-out Buffer.................................................................... 14
5. Removing DSO Intrinsic Jitter with a UNLXO as a Noiseless Source......................................................................15 6. Conclusions..............................................................................................................................................................16
Appendix A. Mathematical Discussion of Phase Noise Measurements on the PNA and DSO .........................................17
Appendix B. Removing DSO Intrinsic Noise Due to Slew Rate.........................................................................................19 References ........................................................................................................................................................................ 21
Revision History ................................................................................................................................................................ 21

Aug.5.20

Page 2

PCIe Reference Clock Jitter Measurements for Gen5 and Beyond

White Paper

1. Noiseless" Sources
No source is truly "noiseless." However, we can consider several clock sources to be noiseless with respect to PCIe. These sources have theoretical phase jitter limits of less than 5fs RMS against the PCIe Gen5 CC limit of 150fs RMS. One such source is an ultra-low noise crystal oscillator, such as the Wenzel� VHF ULN series. A second noiseless source is a programmable RF and Microwave Signal Generator, such as the Rhode and Schwarz� SMA100B. Each has advantages and disadvantages, and both are suitable for our purposes. First, we convert the phase jitter specifications into piece-wise-linear plots. From the plots, we generate dBc/Hz CSV files, and calculate the theoretical best-case PCIe Gen5 CC jitter for each.
1.1 Noiseless Ultra-Low Noise Crystal Oscillators (ULNXO)
ULNXOs are very low noise, relatively inexpensive and easy to use. The highest performance versions provide a single-ended LVCMOS sine wave output. This makes these devices easiest to measure with a PNA since the single output connects directly to the PNA input via a coaxial cable.
Measuring a UNLXO with an oscilloscope presents a few challenges. The major challenge is the very slow slew rate of the UNLXO sine wave output. We need an external device to "sharpen the edges". (We will dive into this issue in more detail later in this document.) The other major challenge is the single-ended nature of the output. We need another device to convert the UNLXO output to the differential type used by PCIe. Luckily, we can use a single device, referred to as a balun, to resolve both issues.

10.E+0 -80 -100 -120 -140 -160 -180 -200

100MHz Ultra Low Noise Crystal Oscillator

100.E+0

1.E+3

10.E+3 100.E+3

1.E+6

Offset Frequency (Hz)

10.E+6

dBc

Figure 1. Phase Noise of UNLXO (Piece-wise Linear Model from Datasheet) The theoretical limit in Figure 1 is 10.07fs RMS (12kHz to 20MHz) and 1.84fs RMS (PCIe Gen5 CC).

Aug.5.20

Page 3

PCIe Reference Clock Jitter Measurements for Gen5 and Beyond

White Paper

1.2 Noiseless Programmable RF and Microwave Signal Generators (RFSG)
RFSGs are also very low noise, and easy to use. An RFSG can generate a wide range of frequencies (8kHz to 67GHz for an SMA100B) making it much more flexible than ULNXOs. (A single ULNXO is required for each desired output frequency.) An RFSG, such as the SMA100B, offers both single-ended and differential square wave and single-ended sine wave outputs, making it ideal for use with both PNAs and DSOs.

10.E+0 -80 -100 -120 -140 -160 -180 -200

100MHz RF and Microwave Signal Generator

100.E+0

1.E+3

10.E+3 100.E+3

1.E+6

Offset Frequency (Hz)

10.E+6

dBc

Figure 2. Phase Noise of SMA100B (Piece-wise Linear Model from Datasheet) The theoretical limit in Figure 2 is 23.96 RMS (12 kHz to 20 MHz) and 2.48fs RMS (PCIe Gen5 CC).

We note that the SMA100B is slightly higher jitter than a UNLXO. However, with respect to the 150fs RMS limit for PCIe Gen5 we still have SQRT(1502 - 2.482) = 149.98fs RMS of jitter budget. The SMA100B and the UNLXO are essentially noiseless with respect to PCIe Gen5.
Table 1 summarizes the theoretical limits of our noiseless PCIe sources. If our measurement setup added no noise to the results, these values are the best that we could expect. Note that we round the values.
Table 1. Theoretical Phase Jitter Limits of Noiseless PCIe Sources

Source ULNXO RFSG

Phase Jitter (12kHz � 20MHz) 10 fs RMS 24 fs RMS

PCIe Gen5 CC Phase Jitter 1.8 fs RMS 2.5 fs RMS

Aug.5.20

Page 4

PCIe Reference Clock Jitter Measurements for Gen5 and Beyond

White Paper

2. Measuring the Noiseless Refclk Source

Table 2 lists the equipment used for our intrinsic jitter measurements.

Table 2. Equipment Used for Intrinsic Jitter Measurements

Noiseless Source R&S� SMA100B

PNA R&S� FSWP

DSO Keysight� S404

Balun Mini-Circuits� ZFSCJ Series

2.1 Measurement Setup
We will use the SMA100B as our noiseless source and measure it two ways. We will obtain phase noise files with the PNA and clock period files with the DSO. We will then post-process the files to obtain the PCIe Gen5 CC results. Figure 3 shows the measurement setups. While the SMA100B offers a single-ended output, we use the differential outputs for three reasons:
1. We want to use the same SMA100B internal signal source for both PNA and DSO measurements.
2. The SMA100B differential outputs allow a direct connection to the DSO.
3. The SMA100B specifies its differential outputs to drive 50-ohm terminations, which is the input impedance of the PNA and the DSO.
We use a balun to combine the differential outputs of the noiseless source into a single output to drive the PNA. This balun has a minimum bandwidth of 2GHz to minimize any impact on the results.

CK+ "Noiseless"
Source CK-
SMA Connectors

Balun

PNA

Coax Cables

CK+

"Noiseless" Source

DSO

CKFigure 3. Setup for Baseline Intrinsic Jitter Measurements

Aug.5.20

Page 5

PCIe Reference Clock Jitter Measurements for Gen5 and Beyond

White Paper

2.2 PNA Measurement Results
Figure 4 is the phase noise plot of the SMA100B obtained by the PNA. The 12kHz to 20MHz phase jitter measures 23.793fs RMS. These results are 0.2fs RMS lower than the theoretical best case. This is possible because we derived the theoretical limit from a piece-wise-linear approximation of the phase noise plot in the SMA100B datasheet. The approximation was intentionally conservative; therefore, we round to 24fs RMS and can state that this measurement setup is essentially noiseless.

Figure 4. Phase Noise of SMA100B (Measured)
Next, we take the CSV file saved from Figure 4 and post-process it with the Renesas PNA2PCIe tool.
In Figure 5 we see that the FSWP PNA measured the SMA100B at 3.28fs RMS against the PCIe Gen5 CC filter. We round this to 3.3fs RMS. As a cross check, the tool can also calculate the 12kHz � 20MHz single-side band phase noise, which is 23.75fs RMS. This agrees very closely with the 23.793 fs RMS value given by the PNA itself, and we round to 24fs RMS.

Figure 5. PCIe Gen5 CC Results from PNA Aug.5.20

Page 6

PCIe Reference Clock Jitter Measurements for Gen5 and Beyond

White Paper

Table 3 summarizes the PCIe Gen5 results measured with a PNA. The PNA measurement setup adds 2.2fs RMS to the theoretical PCIe Gen5 CC results, leaving us with a margin of:

(150)2 - (2.22) = 149.98 Table 3. Summary SMA100B PCIe Gen5 Results Measured by PNA

Specification PCIe Gen5 CC

PCIe Gen5 Result (fs RMS)
3.3

Theoretical Limit (fs RMS)
2.5

PNA Gen5 Additive Jitter (fs RMS)

(3.3)2 - (2.52)

= 2.2

These results show that SMA100B is a noiseless source with respect to the PCIe Gen5 CC 150fs RMS jitter limit.

2.3 DSO Measurement Results
Figure 6 shows the SMA100B differential output from which the DSO generates the clock period files for analysis. The Renesas DSO2PCIe tool post-processes these files to calculate the PCIe Gen5 jitter.

3
2
Figure 6. SMA100B Clock Sampled by DSO There are several things to note about the SMA100B waveform before we proceed. First, the mean value of the clock slew rate is >12V/ns! The PCIe specification indicates a maximum slew rate of 4V/ns. We will return to this item in the next section. Second, the frequency range (Max � Min) is ~30kHz, with a corresponding period jitter of 3ps. The SMA100B frequency accuracy is <<<30 kHz, and therefore, its period jitter is <<< 3ps. Third, the single-ended amplitude is ~860mV, because the SMA100B outputs are specified into a 50ohm load, which matches the input impedance of the DSO.

Aug.5.20

Page 7

PCIe Reference Clock Jitter Measurements for Gen5 and Beyond

White Paper

Now, let us look at the PCIe results from the clock period file. Figure 7 illustrates the results obtained by post processing the clock period file from the waveform in Figure 6. According to the post-processed clock period file, the SMA100B is 28fs RMS when filtered for PCIe Gen5 CC.
This is a significantly higher than the 3.3fs RMS calculated from the PNA CSV file.

Figure 7. PCIe Gen5 CC Results from DSO
Due to the wonders of RMS math, we still have a significant margin to the PCIe Gen5 CC specification. Table 4 summarizes the PCIe Gen5 results for the noiseless source measured with a DSO. The DSO measurement setup adds 27.9fs RMS to the PCIe Gen5 CC results, leaving us with a margin of:

(150)2 - (27.92) = 147.4
Therefore, we may still consider the SMA100B to be a noiseless source, even when calculated from time domain measurements obtained with a DSO. Note that Figure 7 presents results in picoseconds, which we convert to femtoseconds for use in this document.
Table 4. Summary SMA100B Results Measured by DSO

Specification PCIe Gen5 CC

PCIe Gen5 Result (fs RMS) 28

Theoretical Limit (fs RMS) 2.5

PNA Gen5 Additive Jitter

(fs RMS)

(28)2 - (2.52)

= 27.9

Another way of looking at Table 4 is that we can never measure a PCIe Gen5 CC result < 28fs RMS for a clock with similar electrical characteristics (amplitude, slew rate and phase noise). This means that for this DSO and this clock source, 27.9fs RMS is the lowest value that we can measure for PCIe Gen5 CC. We round this value to 28fs RMS.
So far, we can consider the SMA100B as noiseless source whether using a PNA or a DSO for PCIe Gen5 CC.

Aug.5.20

Page 8

PCIe Reference Clock Jitter Measurements for Gen5 and Beyond

White Paper

3. Measuring the Noiseless Refclk for Various Slew Rates
Recall from Figure 6 that the SMA100B output slew rate is > 12V/ns; also recall that the maximum PCIe Refclk slew rate is specified as 4V/ns. Our next task it to measure the noiseless source at various slew rates with both the PNA and the DSO, to ensure that the intrinsic jitter of our measurement setup remains negligible.

3.1 Measurement Setup for Various Slew Rates
The SMA100B does not have a programmable output slew rate. Therefore, we must find a way to slow down the output slew rate. We must also find a way to do so while maintaining the 860mV output amplitude of the signal generator. The solution chosen for this white paper is a simple circuit board with SMA inputs and outputs and a position to mount load capacitors of different values. A purely capacitive load does not attenuate signal amplitude and we may adjust the clock slew rate by changing the capacitor values.
Table 5 shows the capacitor values used to adjust the slew rate of the SMA100B outputs, while Figure 8 illustrates the revised test setup. It is very similar to the baseline setup in Figure 4 with the addition of the load board. In fact, the baseline measurements (0pf) use the setup in Figure 4 without the load board.
Table 5. Load Capacitance vs. Slew Rate

CL (pF)

22 20 16.9 12.7 10.7 8.7 6.7 4.7 2 0

Slew Rate (V/ns)

0.7

0.9

1.5 2.2

3.1

3.8

3.9

4.2

7 12.7

Key Takeaway

The key takeaway of Table 5 is the slew rate and not the capacitor values.

CK+
"Noiseless" Source
CK-

CL Load Board
CL

SMA Connectors

Balun

PNA

Coax Cables

CK+
"Noiseless" Source CK-

CL Load Board
CL

DSO

Figure 8. Setups for Variable Slew Rate Intrinsic Jitter Measurements
We can see that the measurement setup for variable slew rate is identical to the baseline setup, except for the insertion of the load board between the noiseless source and the balun for PNA measurements, and between the noiseless source and the DSO for the DSO measurements.

Aug.5.20

Page 9

PCIe Reference Clock Jitter Measurements for Gen5 and Beyond

White Paper

3.2 PNA Measurement Results for Various Slew Rates
Figure 9 and Figure 10 show the PCIe Gen5 CC results from the PNA measurements taken at various slew rates. The first figure shows the results against the 150fs RMS limit for Gen5 CC. The second figure shows the same results with the vertical axis zoomed from 150fs RMS full scale to 8fs RMS full scale.
We see that the PNA results are virtually independent of slew rate and are virtually noiseless with respect to PCIe Gen5 CC. Recall that the amplitude for these measurements is relatively constant at ~860mV. Zooming in on the vertical axis, Figure 10 shows that the measured PCIe Gen5 CC results range from 3.0 to 3.5 fs RMS across all slew rates. The dashed line is a best-fit trend line, which is linear, and is virtually flat.

fs (RMS)

PCIe G5 CC from PNA Measurements - Full Scale

150

140

130

120

110

100

Slew Rate (V/ns)

Figure 9. PCIe Gen5 CC Results vs. Slew Rate for PNA � Noiseless Source

Aug.5.20

Page 10

PCIe Reference Clock Jitter Measurements for Gen5 and Beyond

White Paper

fs (RMS)

PCIe G5 CC from PNA Measurements - Zoomed
8

Slew Rate (V/ns)

Figure 10. PCIe Gen5 CC Results vs. Slew Rate for PNA � Noiseless Source - Zoomed Vertical Axis

3.3 DSO Measurement Results for Various Slew Rates
We use the same test set up shown in Figure 8 to adjust the output slew rate of the SMA100B for DSO measurements. The slew rates are as indicated in Table 5.

fs (RMS)

PCIe G5 CC Phase Jitter from DSO Measurements
400

350

300

250

200

150

100

Slew Rate (V/nSec)

Figure 11. PCIe Gen5 CC Results vs. Slew Rate for DSO

Aug.5.20

Page 11

PCIe Reference Clock Jitter Measurements for Gen5 and Beyond

White Paper

Figure 11 shows the PCIe Gen5 CC results obtained by post processing DSO clock period files obtained at different slew rates. The red dots are the measured data and the dashed line is the best-fit trend line. Clearly, this is different from the PNA results. The DSO results show dramatically increasing jitter as slew rates decrease. These results seem to indicate that the SMA100B violates the PCIe Gen5 CC jitter limit as slew rates decline to < ~1.5V/ns!

fs (RMS)

PCIe G5 CC Phase Jitter from DSO and PNA

400

350

300

250

200

150

100

Slew Rate (V/nSec)

PCIeG5 CC DSO

PCIeG5 CC PNA

Power (PCIeG5 CC DSO)

Figure 12. Comparison of DSO and PNA Results
Figure 12 plots the DSO and PNA on the same scale to illustrate this difference. The PNA results are consistent and noiseless. The DSO results are varying and range from ~noiseless at 12.7V/ns to violating the 150fs RMS spec limit at 1.5V/ns. Remember, we mean noiseless with respect to PCIe Gen5.
The SMA100B is a virtually noiseless noise source for all these measurements. The only thing changed is the use of a DSO instead of a PNA. What is going on? Why the dramatic difference in results between the PNA and the DSO? We will return to these questions later.

4. Removing DSO Intrinsic Noise Using an RFSG as a Noiseless Source
This section uses the RFSG noiseless source to drive a Fan-out Buffer. We will measure additive jitter and attempt to remove the DSO intrinsic noise from the results.
4.1 Measuring Additive Jitter of a Fan-out Buffer Using a PNA
Now, we calculate additive jitter of a fan-out buffer. Figure 13 illustrates the setups for measuring additive jitter. The setup is identical to the variable slew rate setup of Figure 8 with the load boards replaced with the DUT board containing the buffer. The buffer's additive RMS jitter is:
c = a2 - b2, where c = additive jitter, a = output jitter, and b = input jitter
The fan-out buffer has two selectable output slew rates, fast and slow. We will calculate the additive jitter for both settings using the PNA and DSO setups. We discuss actual slew rates in the DSO section, since, as we have seen, they have minimal impact on PNA results.

Aug.5.20

Page 12

PCIe Reference Clock Jitter Measurements for Gen5 and Beyond

White Paper

CK+

"Noiseless" Source

DUT Board

CK-
SMA Connectors

Balun

PNA

Coax Cables

CK+
"Noiseless" Source CK-

DUT Board

DSO

Figure 13. Setups for Measuring Additive Jitter of a Fan-out Buffer
Additive jitter results from the PNA measurements are show in Table 6. We can see very little slew rate impact on the results. For PCIe Gen5 CC, the buffer under test has additive phase jitter of 14 to 16 fs RMS. 12kHz to 20MHz data is provided as a cross check.

Table 6. Calculating the Additive Jitter of a Fan-out Buffer - PNA Results

Units are fs RMS

Input Jitter

Output Jitter

Additive Jitter

Output Jitter

Input is SMA100B (Noiseless Source) (Fast Slew Rate) (Fast Slew Rate) (Slow Slew Rate)

Additive Jitter (Slow Slew Rate)

PCIe Gen5 CC

12 kHz ~ 20MHz

109

105

112

108

We see the results are very consistent, as expected. Next, we will repeat the same procedures with the DSO and look for the same consistency.

4.2 Measuring Additive Jitter of a Fan-out Buffer using a DSO
Using the DSO setup from Figure 13, we obtain additive jitter results in Table 7. There are two things to note. First, the additive jitter values are much higher than those obtained using the PNA. Second, the results are, again, extremely sensitive to the DUT slew rate. At the slow slew rate setting, the DSO measurement setup provides an additive jitter result that is higher than the 150fs RMS PCIe Gen5 CC specification limit. Clearly, we must consider DUT slew rate for any attempt at removing intrinsic jitter. We will attempt this in the next section. Remember that the PNA results do not require this extra step.

Table 7. Calculating the Additive Jitter of a Fan-out Buffer - DSO Results

All jitter units are

Input Jitter

Output Jitter

Additive Jitter

Output Jitter

Additive Jitter

fs RMS

(Noiseless Source) (Fast Slew Rate) (Fast Slew Rate) (Slow Slew Rate) (Slow Slew Rate)

PCIe Gen5 CC

159

156

Slew rate (V/ns)

12.6

1.3

Aug.5.20

Page 13

PCIe Reference Clock Jitter Measurements for Gen5 and Beyond

White Paper

4.3 A Formula to Remove DSO Intrinsic Noise Due to Slew Rate
If signal slew rate is the only variable affecting DSO results, then we should now be able to remove DSO intrinsic noise from our results. In an earlier version of this white paper, we developed a formula to correct for intrinsic DSO jitter due to slew rate. We list the summary equations below.

1. = ()2 - ()2

2. = . Substituting equation 2 into equation 1 give us:

( )2

The parameters in the above equations are:

= . = = . = "noiseless source". = The " source". = .

4.3.1 Applying the Noise Removal Formula to the Additive Jitter of a Fan-out Buffer Studying equation 3 carefully, we can see that Tjm must be 0 or the equation will attempt the square root of a negative number. We can determine the conditions where equation 3 is valid, and find from Appendix B. Removing DSO Intrinsic Noise Due to Slew Rate, that it is valid when:

Using this equation, we now test the results in Table 7 to see if we can use the slew-rate correction formula. Let us test the fast slew rate results first. We ask ourselves, "Is the following true?"
12.6 81 2 28
No, 6.3 is not < 2.9. Therefore, the formula does not hold and we cannot use it to remove intrinsic noise due to slew rate.
For completeness, let us try the DUT slow slew rate. We ask ourselves, "Is the following true?"
12.6 159 1.3 28
No, 9.7 is not < 5.7. Therefore, the formula does not hold and we cannot use it to remove intrinsic noise due to slew rate. Substituting other slew rate/jitter combinations from the equation in Figure 11 does not change the results. The equation does not hold.
Perhaps there is an additional factor beyond slew rate. DSOs have an Analog-to-Digital-Converter (ADC) on the input channels, so signal amplitude is also a variable that we need to consider. Both the DSO and the PNA terminate inputs with 50 ohms to ground. The SMA100B outputs specify a 50ohm load. They drive ~850mV into this load. On the other hand, driving a 50ohm load results in double terminating the DUT HCSL outputs. Therefore, their output amplitude is only ~425mV. Does input amplitude (ADC resolution) also have an impact on DSO results?
Before we address this question, let us look at a different set of measurements.

Aug.5.20

Page 14

PCIe Reference Clock Jitter Measurements for Gen5 and Beyond

White Paper

5. Removing DSO Intrinsic Jitter with a UNLXO as a Noiseless Source

Recall that we identified two noiseless clock sources. The examples discussed to this point have used the RFSG as the source. We have not used the UNLXO in any of the discussions � the original white paper used a UNLXO as the noiseless reference source. Let us look at another example using the same UNLXO. For this example, the amplitude of the UNLXO and DUT into the DSO are identical.
If we take Figure 3, replace the noiseless source with a clock generator DUT and then obtain DSO results for the DUT and the ULNXO, we can attempt to correct for DSO intrinsic noise. The UNLXO drives a balun into the two DSO inputs. For DSO measurements, we also note the slew rates of the measured waveforms. Table 8 contains these measurement results.

Table 8. Clock Generator and UNLXO DSO Results

All jitter units are fs RMS

UNLXO Jitter (Noiseless Source)

Measured DUT Jitter
(Fast Slew Rate)

Formula 3 Corrected Jitter
(Fast Slew Rate)

Measured DUT Jitter
(Slow Slew Rate)

Formula 3 Corrected Jitter
(Slow Slew Rate)

PCIe Gen5 CC

237

150

Slew rate (V/ns)

2.8

2.7

0.9

Recalling the conditions for which the correction formula is valid: For the fast slew rate, we have: 2.8 89 2.7 58 We can see that 1.037 is < 1.53 and Formula 3 is valid.
For the slow slew rate, we have: 2.8 237 2.7 58 We can see that 1.037 is < 4.09 and Formula 3 is valid.
How do the corrected DSO results compare to the PNA results?
Using the PNA, we measure 64fs RMS PCIe Gen5 CC phase jitter of the clock generator DUT at the fast slew rate setting. This compares very favorably with 65fs RMS result obtained after removing the intrinsic noise of the DSO. Unfortunately, PNA results for the slow slew rate are not available.

Aug.5.20

Page 15

PCIe Reference Clock Jitter Measurements for Gen5 and Beyond

White Paper

6. Conclusions
PCIe Gen5 CC results from a DSO are highly dependent on the DUT slew rate. PCIe Gen5 CC measurements from a DSO require removal of its intrinsic noise. This implies a requirement for a two-pass
measurement, access to a noiseless clock source, and additional calculations. Correcting for slew rate is not sufficient to remove the intrinsic noise of the DSO measurement setup. PCIe Gen5 CC measurements from a PNA are highly consistent across DUT slew rates, and do not require two-pass
measurements. Intrinsic noise is not an issue when using a PNA for PCIe Gen5 Refclk jitter measurements. We note a 2:1 amplitude difference in our measurements when using the RFSG as the noiseless reference. The SMA100B
drives ~850mV into 50ohm loads. The DUT drives ~425mV into 50ohm loads. We must also take into account signal amplitude in our attempts to remove intrinsic noise. We note very good results for intrinsic DSO noise removal when using the ULNXO noiseless source. The ULNXO and DUT amplitudes were matched for the measurements made for this white paper.
Several efforts are underway to develop a consistent method for intrinsic jitter removal from DSO measurements. All require taking multiple measurements to obtain one result.
A PNA provides the simplest way to measure PCI Gen5 (and Gen6) Refclk jitter. Newer PNAs support spread-spectrum clocking, removing one of the biggest objections to use of a PNA.

Aug.5.20

Page 16

PCIe Reference Clock Jitter Measurements for Gen5 and Beyond

White Paper

Appendix A. Mathematical Discussion of Phase Noise Measurements on the PNA and DSO
Appendix A, of National Bureau of Standards Technical Note 632, and updated in the IEEE Std. 1139-1999 defines the notation used in the following discussion. It is augmented with text book conventions (e.g., the Fourier transform of h(t) is denoted as H(f)). A square wave with average frequency of 0, and phase jitter of (t) has overall phase of
(t) = 20t+ (t)
in radians. Its average period is = 1/0.
Phase jitter is normally measured in units of time. It is defined as x(t) = (t)/20.
Therefore (t) = 20t+ (t) = 20(t + x(t)).
Its phase is approximately expressed as (n) = 20n + (n) = 20(n + x(n)).
That is, the phase of the square wave is measured at the zero cross over of each period. The rest of the discussion will use t for notation, where
t = n.
(t) and its Fourier transform, (f) form a transform pair. Where f denotes Fourier frequency. (f) cannot be readily measured. A signal's power spectral density (PSD) is measureable. PSD of a band limited signal is defined as
S(f) = (f) *(f)/BW
where *(f) is the complex conjugate of (f) and BW is the measurement bandwidth. In the Fourier spectrum of the signal under test, S(f) is the two-sided noise spectrum about the carrier. Phase Noise Analyzers demodulate and measure the single-sided phase noise spectrum, L(f), of the signals under test. Where
L(f) S(f)/2
and they display PN = 10log10(L(f))

in dBc/Hz. For a phase noise spectrum multiplied by a transfer function H(f), such as PCIe phase noise, PN can be calculated from the display with
PN = 10log10(L(f))+20log(|H(f)|)

The above equation allows the calculation of RMS jitter.

1 20

1010

Aug.5.20

Page 17

PCIe Reference Clock Jitter Measurements for Gen5 and Beyond

White Paper

Alternatively, DSOs can be used to either measure phase jitter, (n), of the signal under test (DUT) by recording the time of zero cross over
(n) = (0() - 0( - 1))/20 , [rad] tox(n) = time of nth zero crossing
or p(n) of the DUT, the period jitter of the signal under test. Period jitter, which is basically phase jitter in seconds, p(n) can be calculated with
p(n) = (0() - 0( - 1)) - , n 0 x(j) = =0 () is the accumulated phase jitter
The Fourier transform of the accumulated phase jitter is calculated by () = DFT(x(j)). (1)

The maximum measureable modulation frequency of a DUT with frequency 0 is its Nyquist rate = 0/2
This represents bimodal jitter in the time domain. For an FFT result with N bins, the bandwidth of each bin is = /
This is the measurement bandwidth of the phase noise spectrum. At this point, the phase noise spectrum of DUT is calculated by the equation
PN = 1010(L(f)) = 1010(S(f)/2)=2010(20()())

Aug.5.20

Page 18

PCIe Reference Clock Jitter Measurements for Gen5 and Beyond

White Paper

Appendix B. Removing DSO Intrinsic Noise Due to Slew Rate
DSOs have intrinsic voltage and other noises introduced by their component parts and architecture. DSO intrinsic noise adds to clock period measurements resulting in additional phase noise. We must measure the noise, and subtract the noise from the overall measurement for a valid result. We can measure and record voltage noise with a null input, but other intrinsic noise sources such as time base noise and quantization noise are hard to measure. Therefore, we must measure the overall jitter of the test setup with a noiseless source (NS) at the input. Only then can we remove the intrinsic jitter of the test setup from our results.
To calibrate with a noiseless source, obtain () (Fourier transform of the phase jitter of a noiseless source) as in (1) and measure the signal slew rate seen by the test setup of both the noiseless source, , and the signal under test, . The phase noise power spectrum measured by the noiseless source is
|()| = ()()

The additive phase noise from the measurement setup is (see section 3.2 for variable definitions):

| ()|

() ()

|()|.

The above equation corrects for the DSO intrinsic noise sensitivity to input slew rate. Phase noise filtered with a transfer function H(f), is given by PNf(f) where

PNf(f)

=1010

(20

|()||()|)2.

Filtering the phase noise of the DUT and the noiseless source (NS) as shown above yields:

PNDUT(f) =1010 (20 |()||()|)2

PNadd(f)

=1010

(20

|()||()|)2

We can calculate the RMS jitter as

1 20

10()10

1 20

12(20

|()||()|)2

1 20

10()10

1 20

|()||()|2

1 20

2 12(20

|()||()|)2

The calibrated phase noise measurement (after removal of intrinsic noise), PNm is then:

PNm(f)

1010

(20

| ()|| ( )|)2

(20

| ()|| ( )|)2

Aug.5.20

Page 19

PCIe Reference Clock Jitter Measurements for Gen5 and Beyond

White Paper

RMS jitter from the measurement is then

1 20

10()10

1 20

|()||()|2

12 20

()||()| 2

12 20

()||

()| 2

=()2 - ()2

=( )2

This equation must be 0. Therefore, we can determine the conditions where this equation is valid by solving the following equation

( )2

Aug.5.20

Page 20

PCIe Reference Clock Jitter Measurements for Gen5 and Beyond

White Paper

References
1. Schwartz; Information Transmission, Modulation and Noise, 3rd ed.; McGraw Hill; 1980
2. Papoulis; Probability, Random Variables, and Stochastic Processes; McGraw Hill; 1965
3. Papoulis; Signal Analysis; McGraw Hill; 1977
4. Clementi; Reference Clock Measurement Limits for PCIe Gen2; IDT; 2006
5. IEEE; IEEE Standard Definitions of Physical Quantities for Fundamental Frequency and Time Metrology-- Random Instabilities; IEEE; 1999
6. Lance, Seal, Labaar, Phase Noise and AM Noise Measurements in the Frequency Domain, Infrared and Millimeter Waves, Vol. II, 1984
7. Weigandt, Kim, Gray. Analysis of Timing Jitter in Ring Oscillators. IEEE ISCAS 1994
8. PCIe SIG Measurement Specification
9. Ron Wade, John Hsu, Jagdeep Bal; PCIe Reference Clock Measurement Methods for PCIe and Their Limits; PCIe SIG presentation, September, 2017
10. Ron Wade, John Hsu, Jagdeep Bal, Joe Tajnai; Appendix - PCIe Reference Clock Measurement Methods for PCIe & Their Limits; September, 2017

Revision History

Revision Date August 5, 2020

Initial release.

Description

Aug.5.20

Page 21

IMPORTANT NOTICE AND DISCLAIMER
RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES ("RENESAS") PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES "AS IS" AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products.

(Rev.1.0 Mar 2020)

Corporate Headquarters
TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com
Trademarks
Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners.

Contact Information
For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/