EFM32GG11 Data Sheet
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EFM32GG11 Data Sheet
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EFM32GG11 Data Sheet - Silicon Labs
EFM32 Giant Gecko Series 1 Family EFM32GG11 Family Data Sheet The EFM32 Giant Gecko Series 1 MCUs are the world’s most energy-friendly microcontrollers, featuring new connectivity interfa
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EFM32 Giant Gecko Series 1 Family EFM32GG11 Family Data Sheet
The EFM32 Giant Gecko Series 1 MCUs are the world's most energy-friendly microcontrollers, featuring new connectivity interfaces and user interface features.
EFM32GG11 includes a powerful 32-bit ARM� Cortex�-M4 and provides robust security via a unique cryptographic hardware engine supporting AES, ECC, SHA, and True Random Number Generator (TRNG). New features include an SD/MMC/SDIO controller, Octal/Quad-SPI memory controller, 10/100 Ethernet MAC, CAN bus controller, highly robust capacitive sensing, enhanced alpha blending graphics engine, and LESENSE/PCNT enhancements for smart energy meters. These features, combined with ultra-low current active mode and short wake-up time from energy-saving modes, make EFM32GG11 microcontrollers well suited for any battery-powered application, as well as other systems requiring high performance and low-energy consumption.
Example applications:
� Smart energy meters � Industrial and factory automation � Home automation and security
� Mid- and high-tier wearables � IoT devices
� ARM Cortex-M4 at 72 MHz
� Ultra low energy operation � 80 �A/MHz in Energy Mode 0 (EM0)
� 2.1 A EM2 Deep Sleep current (RTCC running with state and RAM retention)
� Octal/Quad-SPI memory interface w/ XIP
� SD/MMC/SDIO Host Controller
� 10/100 Ethernet MAC with 802.3az EEE, IEEE1588
� Dual CAN 2.0 Bus Controller
� Crystal-free low-energy USB
� Hardware cryptographic engine supports AES, ECC, SHA, and TRNG
� Robust capacitive touch sense
� Footprint compatible with select EFM32 packages
� 5 V tolerant I/O
Core / Memory
ARM CortexTM M4 processor with FPU and
MPU
ETM
Flash Program Memory
RAM Memory
Debug Interface
LDMA Controller
Clock Management
High Frequency Crystal Oscillator
High Frequency RC Oscillator
PLL
Universal HF RC Oscillator
Auxiliary High Freq. RC Osc.
Ultra Low Freq. RC Oscillator
Low Frequency Crystal Oscillator
Low Frequency RC Oscillator
Energy Management
Voltage Regulator
Voltage/Temp Monitor
DC-DC Converter
Power-On Reset
Brown-Out Detector
Backup Domain
Other
CRYPTO
CRC True Random Number Generator
SMU
Serial Interfaces
USART
UART
10/100 Ethernet
SD / MMC / SDIO
CAN
LEUSB (crystal free)
I2C
Quad-SPI
Low Energy UARTTM
32-bit bus Peripheral Reflex System
I/O Ports
EBI + pixel-alpha
TFT Driver
Timers and Triggers
Timer/Counter
Low Energy Sensor IF
External Interrupts
General Purpose I/O
Low Energy Timer Real Time Counter
Pulse Counter
Watchdog Timer
Pin Reset
Pin Wakeup
Real Time Counter and Calendar
CRYOTIMER
Analog Interfaces
Low Energy LCD Controller
VDAC
Analog Comparator
Capacitive Sensing
ADC
Operational Amplifier
IDAC
Lowest power mode with peripheral operational:
EM0 - Active
EM1 - Sleep
EM2 � Deep Sleep
EM3 - Stop
EM4H - Hibernate
EM4S - Shutoff
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Rev. 1.0
EFM32GG11 Family Data Sheet
Feature List
1. Feature List
The EFM32GG11 highlighted features are listed below.
� ARM Cortex-M4 CPU platform � High performance 32-bit processor @ up to 72 MHz � DSP instruction support and Floating Point Unit � Memory Protection Unit � Wake-up Interrupt Controller
� Flexible Energy Management System � 80 A/MHz in Active Mode (EM0) � 2.1 A EM2 Deep Sleep current (16 kB RAM retention and RTCC running from LFRCO)
� Integrated DC-DC buck converter � Up to 2048 kB flash program memory
� Dual-bank with read-while-write support � Up to 512 kB RAM data memory
� 256 kB with ECC (SEC-DED) � Octal/Quad-SPI Flash Memory Interface
� Supports 3 V and 1.8 V memories � 1/2/4/8-bit data bus � Quad-SPI Execute In Place (XIP) � Communication Interfaces � Low-energy Universal Serial Bus (USB) with Device and
Host support � Fully USB 2.0 compliant � On-chip PHY and embedded 5V to 3.3V regulator � Crystal-free Device mode operation � Patent-pending Low-Energy Mode (LEM) � SD/MMC/SDIO Host Controller � SD v3.01, SDIO v3.0 and MMC v4.51 � 1/4/8-bit bus width � 10/100 Ethernet MAC with MII/RMII interface � IEEE1588-2008 precision time stamping � Energy Efficient Ethernet (802.3az) � Up to 2� CAN Bus Controller � Version 2.0A and 2.0B up to 1 Mbps � 6� Universal Synchronous/Asynchronous Receiver/ Transmitter � UART/SPI/SmartCard (ISO 7816)/IrDA/I2S/LIN � Triple buffered full/half-duplex operation with flow control � Ultra high speed (36 MHz) operation on one instance � 2� Universal Asynchronous Receiver/ Transmitter � 2� Low Energy UART � Autonomous operation with DMA in Deep Sleep Mode � 3� I2C Interface with SMBus support � Address recognition in EM3 Stop Mode
� Up to 144 General Purpose I/O Pins � Configurable push-pull, open-drain, pull-up/down, input filter, drive strength � Configurable peripheral I/O locations � 5 V tolerance on select pins � Asynchronous external interrupts � Output state retention and wake-up from Shutoff Mode
� Up to 24 Channel DMA Controller � Up to 24 Channel Peripheral Reflex System (PRS) for au-
tonomous inter-peripheral signaling � External Bus Interface for up to 4x256 MB of external
memory mapped space � TFT Controller with Direct Drive � Per-pixel alpha-blending engine � Hardware Cryptography � AES 128/256-bit keys � ECC B/K163, B/K233, P192, P224, P256 � SHA-1 and SHA-2 (SHA-224 and SHA-256) � True Random Number Generator (TRNG) � Hardware CRC engine � Single-cycle computation with 8/16/32-bit data and 16-bit
(programmable)/32-bit (fixed) polynomial � Security Management Unit (SMU)
� Fine-grained access control for on-chip peripherals � Integrated Low-energy LCD Controller with up to 8�36 seg-
ments � Voltage boost, contrast and autonomous animation � Patented low-energy LCD driver � Backup Power Domain � RTCC and retention registers in a separate power domain,
available down to energy mode EM4H � Operation from backup battery when main power absent/
insufficient � Ultra Low-Power Precision Analog Peripherals
� 2� 12-bit 1 Msamples/s Analog to Digital Converter (ADC) � On-chip temperature sensor
� 2� 12-bit 500 ksamples/s Digital to Analog Converter (VDAC)
� Digital to Analog Current Converter (IDAC) � Up to 4� Analog Comparator (ACMP) � Up to 4� Operational Amplifier (OPAMP) � Robust current-based capacitive sensing with up to 64 in-
puts and wake-on-touch (CSEN) � Up to 108 GPIO pins are analog-capable. Flexible analog
peripheral-to-pin routing via Analog Port (APORT) � Supply Voltage Monitor
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Rev. 1.0 | 2
EFM32GG11 Family Data Sheet
Feature List
� Timers/Counters � 7� 16-bit Timer/Counter � 3 + 4 Compare/Capture/PWM channels (4 + 4 on one timer instance) � Dead-Time Insertion on several timer instances � 4� 32-bit Timer/Counter � 32-bit Real Time Counter and Calendar (RTCC) � 24-bit Real Time Counter (RTC) � 32-bit Ultra Low Energy CRYOTIMER for periodic wakeup from any Energy Mode � 2� 16-bit Low Energy Timer for waveform generation � 3� 16-bit Pulse Counter with asynchronous operation � 2� Watchdog Timer with dedicated RC oscillator
� Low Energy Sensor Interface (LESENSE) � Autonomous sensor monitoring in Deep Sleep Mode � Wide range of sensors supported, including LC sensors and capacitive buttons � Up to 16 inputs
� Ultra efficient Power-on Reset and Brown-Out Detector � Debug Interface
� 2-pin Serial Wire Debug interface � 1-pin Serial Wire Viewer � 4-pin JTAG interface � Embedded Trace Macrocell (ETM)
� Pre-Programmed Bootloader � Wide Operating Range
� 1.8 V to 3.8 V single power supply � Integrated DC-DC, down to 1.8 V output with up to 200 mA
load current for system � Standard (-40 �C to 85 �C TAMB) and Extended (-40 �C to
125 �C TJ) temperature grades available � Packages
� QFN64 (9x9 mm) � TQFP64 (10x10 mm) � TQFP100 (14x14 mm) � BGA112 (10x10 mm) � BGA120 (7x7 mm) � BGA152 (8x8 mm) � BGA192 (7x7mm)
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Rev. 1.0 | 3
2. Ordering Information
Table 2.1. Ordering Information
EFM32GG11 Family Data Sheet
Ordering Information
DC-DC Converter USB Ethernet QSPI SDIO LCD
Ordering Code
Flash RAM (kB) (kB)
GPIO Package Temp Range
EFM32GG11B820F2048GL192-B 2048 512 Yes Yes Yes Yes Yes Yes 144 BGA192 -40 to +85�C
EFM32GG11B840F1024GL192-B 1024 512 Yes Yes Yes Yes Yes Yes 144 BGA192 -40 to +85�C
EFM32GG11B820F2048GL152-B 2048 512 Yes Yes Yes Yes Yes Yes 121 BGA152 -40 to +85�C
EFM32GG11B820F2048IL152-B 2048 512 Yes Yes Yes Yes Yes Yes 121 BGA152 -40 to +125�C
EFM32GG11B840F1024GL152-B 1024 512 Yes Yes Yes Yes Yes Yes 121 BGA152 -40 to +85�C
EFM32GG11B840F1024IL152-B 1024 512 Yes Yes Yes Yes Yes Yes 121 BGA152 -40 to +125�C
EFM32GG11B820F2048GL120-B 2048 512 Yes Yes Yes Yes Yes Yes 95 BGA120 -40 to +85�C
EFM32GG11B820F2048IL120-B 2048 512 Yes Yes Yes Yes Yes Yes 95 BGA120 -40 to +125�C
EFM32GG11B840F1024GL120-B 1024 512 Yes Yes Yes Yes Yes Yes 95 BGA120 -40 to +85�C
EFM32GG11B840F1024IL120-B 1024 512 Yes Yes Yes Yes Yes Yes 95 BGA120 -40 to +125�C
EFM32GG11B820F2048GQ100-B 2048 512 Yes Yes Yes Yes Yes Yes 80 QFP100 -40 to +85�C
EFM32GG11B820F2048IQ100-B 2048 512 Yes Yes Yes Yes Yes Yes 80 QFP100 -40 to +125�C
EFM32GG11B840F1024GQ100-B 1024 512 Yes Yes Yes Yes Yes Yes 80 QFP100 -40 to +85�C
EFM32GG11B840F1024IQ100-B 1024 512 Yes Yes Yes Yes Yes Yes 80 QFP100 -40 to +125�C
EFM32GG11B820F2048GQ64-B 2048 512 Yes Yes Yes Yes Yes Yes 47
QFP64 -40 to +85�C
EFM32GG11B820F2048GM64-B 2048 512 Yes Yes Yes Yes Yes Yes 50
QFN64 -40 to +85�C
EFM32GG11B820F2048IQ64-B
2048 512 Yes Yes Yes Yes Yes Yes 47
QFP64 -40 to +125�C
EFM32GG11B820F2048IM64-B
2048 512 Yes Yes Yes Yes Yes Yes 50
QFN64 -40 to +125�C
EFM32GG11B840F1024GQ64-B 1024 512 Yes Yes Yes Yes Yes Yes 47
QFP64 -40 to +85�C
EFM32GG11B840F1024GM64-B 1024 512 Yes Yes Yes Yes Yes Yes 50
QFN64 -40 to +85�C
EFM32GG11B840F1024IQ64-B
1024 512 Yes Yes Yes Yes Yes Yes 47
QFP64 -40 to +125�C
EFM32GG11B840F1024IM64-B
1024 512 Yes Yes Yes Yes Yes Yes 50
QFN64 -40 to +125�C
EFM32GG11B520F2048GL120-B 2048 512 Yes No No No No Yes 95 BGA120 -40 to +85�C
EFM32GG11B510F2048GL120-B 2048 384 Yes No No No No Yes 95 BGA120 -40 to +85�C
EFM32GG11B520F2048IL120-B 2048 512 Yes No No No No Yes 95 BGA120 -40 to +125�C
EFM32GG11B510F2048IL120-B 2048 384 Yes No No No No Yes 95 BGA120 -40 to +125�C
EFM32GG11B520F2048GQ100-B 2048 512 Yes No No No No Yes 83 QFP100 -40 to +85�C
EFM32GG11B510F2048GQ100-B 2048 384 Yes No No No No Yes 83 QFP100 -40 to +85�C
EFM32GG11B520F2048IQ100-B 2048 512 Yes No No No No Yes 83 QFP100 -40 to +125�C
EFM32GG11B510F2048IQ100-B 2048 384 Yes No No No No Yes 83 QFP100 -40 to +125�C
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EFM32GG11 Family Data Sheet
Ordering Information
DC-DC Converter USB Ethernet QSPI SDIO LCD
Ordering Code
Flash RAM (kB) (kB)
GPIO Package Temp Range
EFM32GG11B520F2048GQ64-B 2048 512 Yes No No No No Yes 50
QFP64 -40 to +85�C
EFM32GG11B510F2048GQ64-B 2048 384 Yes No No No No Yes 50
QFP64 -40 to +85�C
EFM32GG11B520F2048GM64-B 2048 512 Yes No No No No Yes 53
QFN64 -40 to +85�C
EFM32GG11B510F2048GM64-B 2048 384 Yes No No No No Yes 53
QFN64 -40 to +85�C
EFM32GG11B520F2048IQ64-B
2048 512 Yes No No No No Yes 50
QFP64 -40 to +125�C
EFM32GG11B510F2048IQ64-B
2048 384 Yes No No No No Yes 50
QFP64 -40 to +125�C
EFM32GG11B520F2048IM64-B
2048 512 Yes No No No No Yes 53
QFN64 -40 to +125�C
EFM32GG11B510F2048IM64-B
2048 384 Yes No No No No Yes 53
QFN64 -40 to +125�C
EFM32GG11B420F2048GL120-B 2048 512 No Yes Yes Yes Yes Yes 93 BGA120 -40 to +85�C
EFM32GG11B420F2048IL120-B 2048 512 No Yes Yes Yes Yes Yes 93 BGA120 -40 to +125�C
EFM32GG11B420F2048GL112-B 2048 512 No Yes Yes Yes Yes Yes 87 BGA112 -40 to +85�C
EFM32GG11B420F2048IL112-B 2048 512 No Yes Yes Yes Yes Yes 87 BGA112 -40 to +125�C
EFM32GG11B420F2048GQ100-B 2048 512 No Yes Yes Yes Yes Yes 83 QFP100 -40 to +85�C
EFM32GG11B420F2048IQ100-B 2048 512 No Yes Yes Yes Yes Yes 83 QFP100 -40 to +125�C
EFM32GG11B420F2048GQ64-B 2048 512 No Yes Yes Yes Yes Yes 50
QFP64 -40 to +85�C
EFM32GG11B420F2048GM64-B 2048 512 No Yes Yes Yes Yes Yes 53
QFN64 -40 to +85�C
EFM32GG11B420F2048IQ64-B
2048 512 No Yes Yes Yes Yes Yes 50
QFP64 -40 to +125�C
EFM32GG11B420F2048IM64-B
2048 512 No Yes Yes Yes Yes Yes 53
QFN64 -40 to +125�C
EFM32GG11B320F2048GL112-B 2048 512 No No No No No Yes 90 BGA112 -40 to +85�C
EFM32GG11B310F2048GL112-B 2048 384 No No No No No Yes 90 BGA112 -40 to +85�C
EFM32GG11B320F2048GQ100-B 2048 512 No No No No No Yes 86 QFP100 -40 to +85�C
EFM32GG11B310F2048GQ100-B 2048 384 No No No No No Yes 86 QFP100 -40 to +85�C
EFM32GG11B120F2048GQ64-B 2048 512 No No No No No No 53
QFP64 -40 to +85�C
EFM32GG11B110F2048GQ64-B 2048 384 No No No No No No 53
QFP64 -40 to +85�C
EFM32GG11B120F2048GM64-B 2048 512 No No No No No No 56
QFN64 -40 to +85�C
EFM32GG11B110F2048GM64-B 2048 384 No No No No No No 56
QFN64 -40 to +85�C
EFM32GG11B120F2048IQ64-B
2048 512 No No No No No No 53
QFP64 -40 to +125�C
EFM32GG11B110F2048IQ64-B
2048 384 No No No No No No 53
QFP64 -40 to +125�C
EFM32GG11B120F2048IM64-B
2048 512 No No No No No No 56
QFN64 -40 to +125�C
EFM32GG11B110F2048IM64-B
2048 384 No No No No No No 56
QFN64 -40 to +125�C
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Rev. 1.0 | 5
EFM32GG11 Family Data Sheet
Ordering Information
EFM32 G G 1 1 B 820 F 2048 G L 192 � A R
Tape and Reel (Optional) Revision Pin Count Package � M (QFN), L (BGA), Q (QFP) Temperature Grade � G (-40 to +85 �C), I (-40 to +125 �C) Flash Memory Size in kB Memory Type (Flash) Feature Set Code Performance Grade � B (Basic) Device Configuration Series Gecko Family � G (Giant) Energy Friendly Microcontroller 32-bit
Figure 2.1. Ordering Code Key
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Rev. 1.0 | 6
Table of Contents
1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.2 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.2.1 Energy Management Unit (EMU) . . . . . . . . . . . . . . . . . . . . . .13 3.2.2 DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.2.3 5 V Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.2.4 EM2 and EM3 Power Domains . . . . . . . . . . . . . . . . . . . . . . .14
3.3 General Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . .14
3.4 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 3.4.1 Clock Management Unit (CMU) . . . . . . . . . . . . . . . . . . . . . . .14 3.4.2 Internal and External Oscillators. . . . . . . . . . . . . . . . . . . . . . .15
3.5 Counters/Timers and PWM . . . . . . . . . . . . . . . . . . . . . . . . . .15 3.5.1 Timer/Counter (TIMER) . . . . . . . . . . . . . . . . . . . . . . . . .15 3.5.2 Wide Timer/Counter (WTIMER) . . . . . . . . . . . . . . . . . . . . . . .15 3.5.3 Real Time Counter and Calendar (RTCC) . . . . . . . . . . . . . . . . . . .15 3.5.4 Low Energy Timer (LETIMER) . . . . . . . . . . . . . . . . . . . . . . .15 3.5.5 Ultra Low Power Wake-up Timer (CRYOTIMER) . . . . . . . . . . . . . . . . .15 3.5.6 Pulse Counter (PCNT) . . . . . . . . . . . . . . . . . . . . . . . . . .16 3.5.7 Watchdog Timer (WDOG) . . . . . . . . . . . . . . . . . . . . . . . . .16
3.6 Communications and Other Digital Peripherals . . . . . . . . . . . . . . . . . . .16 3.6.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) . . . . . . . . . .16 3.6.2 Universal Asynchronous Receiver/Transmitter (UART) . . . . . . . . . . . . . . .16 3.6.3 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) . . . . . . . . . .16 3.6.4 Inter-Integrated Circuit Interface (I2C) . . . . . . . . . . . . . . . . . . . . .16 3.6.5 External Bus Interface (EBI) . . . . . . . . . . . . . . . . . . . . . . . .16 3.6.6 Quad-SPI Flash Controller (QSPI) . . . . . . . . . . . . . . . . . . . . . .17 3.6.7 SDIO Host Controller (SDIO) . . . . . . . . . . . . . . . . . . . . . . . .17 3.6.8 Universal Serial Bus (USB) . . . . . . . . . . . . . . . . . . . . . . . .17 3.6.9 Ethernet (ETH) . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 3.6.10 Controller Area Network (CAN) . . . . . . . . . . . . . . . . . . . . . .17 3.6.11 Peripheral Reflex System (PRS) . . . . . . . . . . . . . . . . . . . . . .17 3.6.12 Low Energy Sensor Interface (LESENSE) . . . . . . . . . . . . . . . . . . .17
3.7 Security Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 3.7.1 GPCRC (General Purpose Cyclic Redundancy Check) . . . . . . . . . . . . . . .18 3.7.2 Crypto Accelerator (CRYPTO) . . . . . . . . . . . . . . . . . . . . . . .18 3.7.3 True Random Number Generator (TRNG) . . . . . . . . . . . . . . . . . . .18 3.7.4 Security Management Unit (SMU) . . . . . . . . . . . . . . . . . . . . . .18
3.8 Analog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.8.1 Analog Port (APORT) . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.8.2 Analog Comparator (ACMP) . . . . . . . . . . . . . . . . . . . . . . . .18 3.8.3 Analog to Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . .18
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3.8.4 Capacitive Sense (CSEN) . . . . . . . . . . . . . . . . . . . . . . . . .18 3.8.5 Digital to Analog Current Converter (IDAC) . . . . . . . . . . . . . . . . . . .19 3.8.6 Digital to Analog Converter (VDAC) . . . . . . . . . . . . . . . . . . . . .19 3.8.7 Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . .19 3.8.8 Liquid Crystal Display Driver (LCD). . . . . . . . . . . . . . . . . . . . . .19
3.9 Reset Management Unit (RMU) . . . . . . . . . . . . . . . . . . . . . . . .19
3.10 Core and Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 3.10.1 Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 3.10.2 Memory System Controller (MSC) . . . . . . . . . . . . . . . . . . . . .19 3.10.3 Linked Direct Memory Access Controller (LDMA) . . . . . . . . . . . . . . . .20 3.10.4 Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.11 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.12 Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . .23
4. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .24 4.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . .25 4.1.2 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . .26 4.1.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .29 4.1.4 DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . .30 4.1.5 5V Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 4.1.6 Backup Supply Domain . . . . . . . . . . . . . . . . . . . . . . . . .33 4.1.7 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . .34 4.1.8 Wake Up Times . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 4.1.9 Brown Out Detector (BOD) . . . . . . . . . . . . . . . . . . . . . . . .43 4.1.10 Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
4.1.11 Flash Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . .51 4.1.12 General-Purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . .52 4.1.13 Voltage Monitor (VMON) . . . . . . . . . . . . . . . . . . . . . . . . .54 4.1.14 Analog to Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . .55 4.1.15 Analog Comparator (ACMP) . . . . . . . . . . . . . . . . . . . . . . .57 4.1.16 Digital to Analog Converter (VDAC) . . . . . . . . . . . . . . . . . . . . .60 4.1.17 Current Digital to Analog Converter (IDAC) . . . . . . . . . . . . . . . . . .63 4.1.18 Capacitive Sense (CSEN) . . . . . . . . . . . . . . . . . . . . . . . .65 4.1.19 Operational Amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . .67 4.1.20 LCD Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 4.1.21 Pulse Counter (PCNT) . . . . . . . . . . . . . . . . . . . . . . . . .71 4.1.22 Analog Port (APORT) . . . . . . . . . . . . . . . . . . . . . . . . . .71 4.1.23 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 4.1.24 USART SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 4.1.25 External Bus Interface (EBI) . . . . . . . . . . . . . . . . . . . . . . .78 4.1.26 Ethernet (ETH) . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 4.1.27 Serial Data I/O Host Controller (SDIO) . . . . . . . . . . . . . . . . . . . .90 4.1.28 Quad SPI (QSPI) . . . . . . . . . . . . . . . . . . . . . . . . . .108
4.2 Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . .112 4.2.1 Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 13 4.2.2 DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . 1. 19
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5. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 5.1 EFM32GG11B8xx in BGA192 Device Pinout . . . . . . . . . . . . . . . . . . . 121 5.2 EFM32GG11B8xx in BGA152 Device Pinout . . . . . . . . . . . . . . . . . . . 125 5.3 EFM32GG11B8xx in BGA120 Device Pinout . . . . . . . . . . . . . . . . . . . 129 5.4 EFM32GG11B5xx in BGA120 Device Pinout . . . . . . . . . . . . . . . . . . . 132 5.5 EFM32GG11B4xx in BGA120 Device Pinout . . . . . . . . . . . . . . . . . . . 135 5.6 EFM32GG11B4xx in BGA112 Device Pinout . . . . . . . . . . . . . . . . . . . 138 5.7 EFM32GG11B3xx in BGA112 Device Pinout . . . . . . . . . . . . . . . . . . . 141 5.8 EFM32GG11B8xx in QFP100 Device Pinout . . . . . . . . . . . . . . . . . . . 144 5.9 EFM32GG11B5xx in QFP100 Device Pinout . . . . . . . . . . . . . . . . . . . 147 5.10 EFM32GG11B4xx in QFP100 Device Pinout . . . . . . . . . . . . . . . . . 1. 50 5.11 EFM32GG11B3xx in QFP100 Device Pinout . . . . . . . . . . . . . . . . . 1. 53 5.12 EFM32GG11B8xx in QFP64 Device Pinout . . . . . . . . . . . . . . . . . . . 156 5.13 EFM32GG11B5xx in QFP64 Device Pinout . . . . . . . . . . . . . . . . . . . 158 5.14 EFM32GG11B4xx in QFP64 Device Pinout . . . . . . . . . . . . . . . . . . . 160 5.15 EFM32GG11B1xx in QFP64 Device Pinout . . . . . . . . . . . . . . . . . . . 162 5.16 EFM32GG11B8xx in QFN64 Device Pinout . . . . . . . . . . . . . . . . . . . 164 5.17 EFM32GG11B5xx in QFN64 Device Pinout . . . . . . . . . . . . . . . . . . . 166 5.18 EFM32GG11B4xx in QFN64 Device Pinout . . . . . . . . . . . . . . . . . . . 168 5.19 EFM32GG11B1xx in QFN64 Device Pinout . . . . . . . . . . . . . . . . . . . 170 5.20 GPIO Functionality Table . . . . . . . . . . . . . . . . . . . . . . . . . 172 5.21 Alternate Functionality Overview . . . . . . . . . . . . . . . . . . . . . 1. 84 5.22 Analog Port (APORT) Client Maps . . . . . . . . . . . . . . . . . . . . . . 217
6. BGA192 Package Specifications . . . . . . . . . . . . . . . . . . . . . . .230 6.1 BGA192 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 230 6.2 BGA192 PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . 232 6.3 BGA192 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . 234
7. BGA152 Package Specifications . . . . . . . . . . . . . . . . . . . . . . .235 7.1 BGA152 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 235 7.2 BGA152 PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . 237 7.3 BGA152 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . 239
8. BGA120 Package Specifications . . . . . . . . . . . . . . . . . . . . . . .240 8.1 BGA120 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 240 8.2 BGA120 PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . 242 8.3 BGA120 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . 244
9. BGA112 Package Specifications . . . . . . . . . . . . . . . . . . . . . . .245 9.1 BGA112 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 245
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9.2 BGA112 PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . 247 9.3 BGA112 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . 249
10. TQFP100 Package Specifications . . . . . . . . . . . . . . . . . . . . . .250 10.1 TQFP100 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . 250 10.2 TQFP100 PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . 252 10.3 TQFP100 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . 253
11. TQFP64 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . 254 11.1 TQFP64 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . .254 11.2 TQFP64 PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . .256 11.3 TQFP64 Package Marking . . . . . . . . . . . . . . . . . . . . . . . 2. 57
12. QFN64 Package Specifications . . . . . . . . . . . . . . . . . . . . . . .258 12.1 QFN64 Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . . 258 12.2 QFN64 PCB Land Pattern. . . . . . . . . . . . . . . . . . . . . . . . . 260 12.3 QFN64 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . 262
13. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
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3. System Overview
EFM32GG11 Family Data Sheet
System Overview
3.1 Introduction
The Giant Gecko Series 1 product family is well suited for any battery operated application as well as other systems requiring high performance and low energy consumption. This section gives a short introduction to the MCU system. The detailed functional description can be found in the Giant Gecko Series 1 Reference Manual.
A block diagram of the Giant Gecko Series 1 family is shown in Figure 3.1 Detailed EFM32GG11 Block Diagram on page 11. The diagram shows a superset of features available on the family, which vary by OPN. For more information about specific device features, consult Ordering Information.
VREGI VBUS VREGO IOVDDn AVDD DVDD VREGVDD VREGSW DECOUPLE
RESETn
Debug Signals (shared w/GPIO)
LFXTAL_P LFXTAL_N HFXTAL_P HFXTAL_N
Energy Management
5V Regulator
Backup Domain
BU_VIN BU_STAT To BU_VOUT GPIO
Voltage Monitor
bypass
DC-DC
Voltage
Converter Regulator
Brown Out / Power-On
Reset
Reset Management
Unit
Serial Wire and ETM Debug /
Programming
ARM Cortex-M4 Core
Up to 2048 KB ISP Flash Program Memory Up to 512 KB RAM
Memory Protection Unit
Security Management
Floating Point Unit
LDMA Controller
Watchdog Timers
Clock Management
ULFRCO AUXHFRCO
LFRCO USHFRCO
LFXO HFRCO + DPLL
HFXO
AA HP BB
Port I/O Configuration
Digital Peripherals
LETIMER
USB
TIMER / WTIMER
CAN
CRYOTIMER
Ethernet
PCNT
EBI
RTC / RTCC
TFT
USART / UART
SDIO
LEUART
QSPI
I2C
CRC
CRYPTO
LESENSE
TRNG
Analog Peripherals
IDAC
Mux & FB
+ -
VDAC
Internal Reference
Op-Amp
Input Mux
VDD
12-bit ADC
Temp Sense
Capacitive Touch
+ Analog Comparator
Low-Energy LCD, up to 8x36 configuration
Figure 3.1. Detailed EFM32GG11 Block Diagram
Analog Port (APORT) Digital Port Mapper
Port A Drivers
Port B Drivers
Port C Drivers
Port D Drivers
Port E Drivers
Port F Drivers
Port G Drivers
Port H Drivers
Port I Drivers
IOVDDn
n=2: PA0-6, PA15, PE14-15
n=1: PD9-12, PE8-13, PF6-9
n=0: All other GPIO
PA0-15
PB0-15
PC0-15
PD0-15
PE0-15
PF0-15
PG0-15
PH0-15
PI0-15
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3.2 Power
EFM32GG11 Family Data Sheet
System Overview
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EFM32GG11 Family Data Sheet
System Overview
The EFM32GG11 has an Energy Management Unit (EMU) and efficient integrated regulators to generate internal supply voltages. Only a single external supply voltage is required, from which all internal voltages are created. A 5 V regulator is available on some OPNs, allowing the device to be powered directly from 5 V power sources, such as USB. An optional integrated DC-DC buck regulator can be utilized to further reduce the current consumption. The DC-DC regulator requires one external inductor and one external capacitor.
The EFM32GG11 device family includes support for internal supply voltage scaling, as well as two different power domain groups for peripherals. These enhancements allow for further supply current reductions and lower overall power consumption.
AVDD and VREGVDD need to be 1.8 V or higher for the MCU to operate across all conditions; however the rest of the system will operate down to 1.62 V, including the digital supply and I/O. This means that the device is fully compatible with 1.8 V components. Running from a sufficiently high supply, the device can use the DC-DC to regulate voltage not only for itself, but also for other PCB components, supplying up to a total of 200 mA.
3.2.1 Energy Management Unit (EMU)
The Energy Management Unit manages transitions of energy modes in the device. Each energy mode defines which peripherals and features are available and the amount of current the device consumes. The EMU can also be used to turn off the power to unused RAM blocks, and it contains control registers for the DC-DC regulator and the Voltage Monitor (VMON). The VMON is used to monitor multiple supply voltages. It has multiple channels which can be programmed individually by the user to determine if a sensed supply has fallen below a chosen threshold.
3.2.2 DC-DC Converter
The DC-DC buck converter covers a wide range of load currents and provides up to 90% efficiency in energy modes EM0, EM1, EM2 and EM3, and can supply up to 200 mA to the device and surrounding PCB components. Protection features include programmable current limiting, short-circuit protection, and dead-time protection. The DC-DC converter may also enter bypass mode when the input voltage is too low for efficient operation. In bypass mode, the DC-DC input supply is internally connected directly to its output through a low resistance switch. Bypass mode also supports in-rush current limiting to prevent input supply voltage droops due to excessive output current transients.
3.2.3 5 V Regulator
A 5 V input regulator is available, allowing the device to be powered directly from 5 V power sources such as the USB VBUS line. The regulator is available in all energy modes, and outputs 3.3 V to be used to power the USB PHY and other 3.3 V systems. Two inputs to the regulator allow for seamless switching between local and external power sources.
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EFM32GG11 Family Data Sheet
System Overview
3.2.4 EM2 and EM3 Power Domains
The EFM32GG11 has three independent peripheral power domains for use in EM2 and EM3. Two of these domains are dynamic and can be shut down to save energy. Peripherals associated with the two dynamic power domains are listed in Table 3.1 EM2 and EM3 Peripheral Power Subdomains on page 14. If all of the peripherals in a peripheral power domain are unused, the power domain for that group will be powered off in EM2 and EM3, reducing the overall current consumption of the device. Other EM2, EM3, and EM4capable peripherals and functions not listed in the table below reside on the primary power domain, which is always on in EM2 and EM3.
Table 3.1. EM2 and EM3 Peripheral Power Subdomains
Peripheral Power Domain 1 ACMP0 PCNT0 ADC0 LETIMER0 LESENSE APORT -
Peripheral Power Domain 2 ACMP1 PCNT1 PCNT2 CSEN VDAC0 LEUART0 LEUART1 LETIMER1 I2C0 I2C1 I2C2 IDAC ADC1 ACMP2 ACMP3 LCD RTC
3.3 General Purpose Input/Output (GPIO)
EFM32GG11 has up to 144 General Purpose Input/Output pins. GPIO are organized on three independent supply rails, allowing for interface to multiple logic levels in the system simultaneously. Each GPIO pin can be individually configured as either an output or input. More advanced configurations including open-drain, open-source, and glitch-filtering can be configured for each individual GPIO pin. The GPIO pins can be overridden by peripheral connections, like SPI communication. Each peripheral connection can be routed to several GPIO pins on the device. The input value of a GPIO pin can be routed through the Peripheral Reflex System to other peripherals. The GPIO subsystem supports asynchronous external pin interrupts.
3.4 Clocking
3.4.1 Clock Management Unit (CMU)
The Clock Management Unit controls oscillators and clocks in the EFM32GG11. Individual enabling and disabling of clocks to all peripheral modules is performed by the CMU. The CMU also controls enabling and configuration of the oscillators. A high degree of flexibility allows software to optimize energy consumption in any specific application by minimizing power dissipation in unused peripherals and oscillators.
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EFM32GG11 Family Data Sheet
System Overview
3.4.2 Internal and External Oscillators
The EFM32GG11 supports two crystal oscillators and fully integrates five RC oscillators, listed below.
� A high frequency crystal oscillator (HFXO) with integrated load capacitors, tunable in small steps, provides a precise timing reference for the MCU. Crystal frequencies in the range from 4 to 50 MHz are supported. An external clock source such as a TCXO can also be applied to the HFXO input for improved accuracy over temperature.
� A 32.768 kHz crystal oscillator (LFXO) provides an accurate timing reference for low energy modes.
� An integrated high frequency RC oscillator (HFRCO) is available for the MCU system. The HFRCO employs fast startup at minimal energy consumption combined with a wide frequency range. When crystal accuracy is not required, it can be operated in free-running mode at a number of factory-calibrated frequencies. A digital phase-locked loop (DPLL) feature allows the HFRCO to achieve higher accuracy and stability by referencing other available clock sources such as LFXO and HFXO.
� An integrated auxilliary high frequency RC oscillator (AUXHFRCO) is available for timing the general-purpose ADC and the Serial Wire Viewer port with a wide frequency range.
� An integrated universal high frequency RC oscillator (USHFRCO) is available for timing the USB, SDIO and QSPI peripherals. The USHFRCO can be syncronized to the host's USB clock to allow the USB to operate in device mode without the additional cost of an external crystal.
� An integrated low frequency 32.768 kHz RC oscillator (LFRCO) can be used as a timing reference in low energy modes, when crystal accuracy is not required.
� An integrated ultra-low frequency 1 kHz RC oscillator (ULFRCO) is available to provide a timing reference at the lowest energy consumption in low energy modes.
3.5 Counters/Timers and PWM
3.5.1 Timer/Counter (TIMER)
TIMER peripherals keep track of timing, count events, generate PWM outputs and trigger timed actions in other peripherals through the PRS system. The core of each TIMER is a 16-bit counter with up to 4 compare/capture channels. Each channel is configurable in one of three modes. In capture mode, the counter state is stored in a buffer at a selected input event. In compare mode, the channel output reflects the comparison of the counter to a programmed threshold value. In PWM mode, the TIMER supports generation of pulse-width modulation (PWM) outputs of arbitrary waveforms defined by the sequence of values written to the compare registers, with optional dead-time insertion available in timer unit TIMER_0 only.
3.5.2 Wide Timer/Counter (WTIMER)
WTIMER peripherals function just as TIMER peripherals, but are 32 bits wide. They keep track of timing, count events, generate PWM outputs and trigger timed actions in other peripherals through the PRS system. The core of each WTIMER is a 32-bit counter with up to 4 compare/capture channels. Each channel is configurable in one of three modes. In capture mode, the counter state is stored in a buffer at a selected input event. In compare mode, the channel output reflects the comparison of the counter to a programmed threshold value. In PWM mode, the WTIMER supports generation of pulse-width modulation (PWM) outputs of arbitrary waveforms defined by the sequence of values written to the compare registers, with optional dead-time insertion available in timer unit WTIMER_0 only.
3.5.3 Real Time Counter and Calendar (RTCC)
The Real Time Counter and Calendar (RTCC) is a 32-bit counter providing timekeeping in all energy modes. The RTCC includes a Binary Coded Decimal (BCD) calendar mode for easy time and date keeping. The RTCC can be clocked by any of the on-board oscillators with the exception of the AUXHFRCO, and it is capable of providing system wake-up at user defined instances. The RTCC includes 128 bytes of general purpose data retention, allowing easy and convenient data storage in all energy modes down to EM4H.
3.5.4 Low Energy Timer (LETIMER)
The unique LETIMER is a 16-bit timer that is available in energy mode EM2 Deep Sleep in addition to EM1 Sleep and EM0 Active. This allows it to be used for timing and output generation when most of the device is powered down, allowing simple tasks to be performed while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of waveforms with minimal software intervention. The LETIMER is connected to the Real Time Counter and Calendar (RTCC), and can be configured to start counting on compare matches from the RTCC.
3.5.5 Ultra Low Power Wake-up Timer (CRYOTIMER)
The CRYOTIMER is a 32-bit counter that is capable of running in all energy modes. It can be clocked by either the 32.768 kHz crystal oscillator (LFXO), the 32.768 kHz RC oscillator (LFRCO), or the 1 kHz RC oscillator (ULFRCO). It can provide periodic Wakeup events and PRS signals which can be used to wake up peripherals from any energy mode. The CRYOTIMER provides a wide range of interrupt periods, facilitating flexible ultra-low energy operation.
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EFM32GG11 Family Data Sheet
System Overview
3.5.6 Pulse Counter (PCNT)
The Pulse Counter (PCNT) peripheral can be used for counting pulses on a single input or to decode quadrature encoded inputs. The clock for PCNT is selectable from either an external source on pin PCTNn_S0IN or from an internal timing reference, selectable from among any of the internal oscillators, except the AUXHFRCO. The module may operate in energy mode EM0 Active, EM1 Sleep, EM2 Deep Sleep, and EM3 Stop.
3.5.7 Watchdog Timer (WDOG)
The watchdog timer can act both as an independent watchdog or as a watchdog synchronous with the CPU clock. It has windowed monitoring capabilities, and can generate a reset or different interrupts depending on the failure mode of the system. The watchdog can also monitor autonomous systems driven by PRS.
3.6 Communications and Other Digital Peripherals
3.6.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
The Universal Synchronous/Asynchronous Receiver/Transmitter is a flexible serial I/O module. It supports full duplex asynchronous UART communication with hardware flow control as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with devices supporting: � ISO7816 SmartCards � IrDA � I2S
3.6.2 Universal Asynchronous Receiver/Transmitter (UART)
The Universal Asynchronous Receiver/Transmitter is a subset of the USART module, supporting full duplex asynchronous UART communication with hardware flow control and RS-485.
3.6.3 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART)
The unique LEUARTTM provides two-way UART communication on a strict power budget. Only a 32.768 kHz clock is needed to allow UART communication up to 9600 baud. The LEUART includes all necessary hardware to make asynchronous serial communication possible with a minimum of software intervention and energy consumption.
3.6.4 Inter-Integrated Circuit Interface (I2C)
The I2C module provides an interface between the MCU and a serial I2C bus. It is capable of acting as both a master and a slave and supports multi-master buses. Standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates from 10 kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also available, allowing implementation of an SMBus-compliant system. The interface provided to software by the I2C module allows precise timing control of the transmission process and highly automated transfers. Automatic recognition of slave addresses is provided in active and low energy modes.
3.6.5 External Bus Interface (EBI)
The External Bus Interface provides access to external parallel interface devices. The interface is memory mapped into the address bus of the Cortex-M4. This enables seamless access from software without manually manipulating the I/O settings each time a read or write is performed. The data and address lines are multiplexed in order to reduce the number of pins required to interface to external devices. Timing is adjustable to meet specifications of the external devices. The interface is limited to asynchronous devices.
The EBI contains a TFT controller which can drive a TFT via an RGB interface. The TFT controller supports programmable display and port sizes and offers accurate control of frequency and setup and hold timing. Direct Drive is supported for TFT displays which do not have their own frame buffer. In that case TFT Direct Drive can transfer data from either on-chip memory or from an external memory device to the TFT at low CPU load. Automatic alpha-blending and masking is also supported for transfers through the EBI interface.
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EFM32GG11 Family Data Sheet
System Overview
3.6.6 Quad-SPI Flash Controller (QSPI)
The QSPI provides access to to a wide range of flash devices with wide I/O busses. The I/O and clocking configuration is flexible and supports many types of devices. Up to 8-bit wide interfaces are supported. The QSPI handles opcodes, status flag polling, and timing configuration automatically.
The external flash memory is mapped directly to internal memory to allow random access to any word in the flash and direct code execution. An integrated instruction cache minimizes latency and allows efficient code execution. Execute in Place (XIP) is supported for devices with this feature.
Large data chunks can be transferred with DMA as efficiently as possible with high throughput and minimimal bus load, utilizing an integrated 1 kB SRAM FIFO.
3.6.7 SDIO Host Controller (SDIO)
The SDIO is an SD3.01 / SDIO3.0 / eMMC4.51-compliant Host Controller interface for transferring data to and from SD/MMC/SDIO devices. The module conforms to the SD Host Controller Standard Specification Version 3.00. The Host Controller handles SDIO/SD/MMC Protocol at the transmission level, packing data, adding cyclic redundancy check (CRC), Start/End bits, and checking for transaction format correctness.
3.6.8 Universal Serial Bus (USB)
The USB is a full-speed/low-speed USB 2.0 compliant host/device controller. The USB can be used in device and host-only configurations, while a clock recovery mechanism allows crystal-less operation in device mode. The USB block supports both full speed (12 MBit/s) and low speed (1.5 MBit/s) operation. When operating as a device, a special Low Energy Mode ensures the current consumption is optimized, enabling USB communications on a strict power budget. The USB device includes an internal dedicated DescriptorBased Scatter/Gather DMA and supports up to 6 OUT endpoints and 6 IN endpoints, in addition to endpoint 0. The on-chip PHY includes internal pull-up and pull-down resistors, as well as voltage comparators for monitoring the VBUS voltage and A/B device identification using the ID line.
3.6.9 Ethernet (ETH)
The Ethernet peripheral is compliant with IEEE 802.3-2002 for Ethernet MAC. It supports 802.1AS and IEEE 1588 precision clock synchronization protocol, as well as 802.3az Energy Efficient Ethernet. The ETH supports a wide variety of frame formats and standard operating modes such as MII/RMII. Direct Memory Access (DMA) support makes it possible to transmit and receive large frames at high data rates with minimal CPU overhead. The Ethernet peripheral supports 10 Mbps and 100 Mbps operation, and includes a total of 8 kB of dedicated dual-port RAM FIFO (4 kB for TX and 4 kB for RX).
3.6.10 Controller Area Network (CAN)
The CAN peripheral provides support for communication at up to 1 Mbps over CAN protocol version 2.0 part A and B. It includes 32 message objects with independent identifier masks and retains message RAM in EM2. Automatic retransmittion may be disabled in order to support Time Triggered CAN applications.
3.6.11 Peripheral Reflex System (PRS)
The Peripheral Reflex System provides a communication network between different peripheral modules without software involvement. Peripheral modules producing Reflex signals are called producers. The PRS routes Reflex signals from producers to consumer peripherals which in turn perform actions in response. Edge triggers and other functionality such as simple logic operations (AND, OR, NOT) can be applied by the PRS to the signals. The PRS allows peripheral to act autonomously without waking the MCU core, saving power.
3.6.12 Low Energy Sensor Interface (LESENSE)
The Low Energy Sensor Interface LESENSETM is a highly configurable sensor interface with support for up to 16 individually configurable sensors. By controlling the analog comparators, ADC, and DAC, LESENSE is capable of supporting a wide range of sensors and measurement schemes, and can for instance measure LC sensors, resistive sensors and capacitive sensors. LESENSE also includes a programmable finite state machine which enables simple processing of measurement results without CPU intervention. LESENSE is available in energy mode EM2, in addition to EM0 and EM1, making it ideal for sensor monitoring in applications with a strict energy budget.
3.7 Security Features
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EFM32GG11 Family Data Sheet
System Overview
3.7.1 GPCRC (General Purpose Cyclic Redundancy Check)
The GPCRC module implements a Cyclic Redundancy Check (CRC) function. It supports both 32-bit and 16-bit polynomials. The supported 32-bit polynomial is 0x04C11DB7 (IEEE 802.3), while the 16-bit polynomial can be programmed to any value, depending on the needs of the application.
3.7.2 Crypto Accelerator (CRYPTO)
The Crypto Accelerator is a fast and energy-efficient autonomous hardware encryption and decryption accelerator. Giant Gecko Series 1 devices support AES encryption and decryption with 128- or 256-bit keys, ECC over both GF(P) and GF(2m), and SHA-1 and SHA-2 (SHA-224 and SHA-256).
Supported block cipher modes of operation for AES include: ECB, CTR, CBC, PCBC, CFB, OFB, GCM, CBC-MAC, GMAC and CCM.
Supported ECC NIST recommended curves include P-192, P-224, P-256, K-163, K-233, B-163 and B-233.
The CRYPTO module allows fast processing of GCM (AES), ECC and SHA with little CPU intervention. CRYPTO also provides trigger signals for DMA read and write operations.
3.7.3 True Random Number Generator (TRNG)
The TRNG module is a non-deterministic random number generator based on a full hardware solution. The TRNG is validated with NIST800-22 and AIS-31 test suites as well as being suitable for FIPS 140-2 certification (for the purposes of cryptographic key generation).
3.7.4 Security Management Unit (SMU)
The Security Management Unit (SMU) allows software to set up fine-grained security for peripheral access, which is not possible in the Memory Protection Unit (MPU). Peripherals may be secured by hardware on an individual basis, such that only priveleged accesses to the peripheral's register interface will be allowed. When an access fault occurs, the SMU reports the specific peripheral involved and can optionally generate an interrupt.
3.8 Analog
3.8.1 Analog Port (APORT)
The Analog Port (APORT) is an analog interconnect matrix allowing access to many analog modules on a flexible selection of pins. Each APORT bus consists of analog switches connected to a common wire. Since many clients can operate differentially, buses are grouped by X/Y pairs.
3.8.2 Analog Comparator (ACMP)
The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is higher. Inputs are selected from among internal references and external pins. The tradeoff between response time and current consumption is configurable by software. Two 6-bit reference dividers allow for a wide range of internally-programmable reference sources. The ACMP can also be used to monitor the supply voltage. An interrupt can be generated when the supply falls below or rises above the programmable threshold.
3.8.3 Analog to Digital Converter (ADC)
The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to 1 Msps. The output sample resolution is configurable and additional resolution is possible using integrated hardware for averaging over multiple samples. The ADC includes integrated voltage references and an integrated temperature sensor. Inputs are selectable from a wide range of sources, including pins configurable as either single-ended or differential.
3.8.4 Capacitive Sense (CSEN)
The CSEN module is a dedicated Capacitive Sensing block for implementing touch-sensitive user interface elements such a switches and sliders. The CSEN module uses a charge ramping measurement technique, which provides robust sensing even in adverse conditions including radiated noise and moisture. The module can be configured to take measurements on a single port pin or scan through multiple pins and store results to memory through DMA. Several channels can also be shorted together to measure the combined capacitance or implement wake-on-touch from very low energy modes. Hardware includes a digital accumulator and an averaging filter, as well as digital threshold comparators to reduce software overhead.
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EFM32GG11 Family Data Sheet
System Overview
3.8.5 Digital to Analog Current Converter (IDAC)
The Digital to Analog Current Converter can source or sink a configurable constant current. This current can be driven on an output pin or routed to the selected ADC input pin for capacitive sensing. The full-scale current is programmable between 0.05 �A and 64 �A with several ranges consisting of various step sizes.
3.8.6 Digital to Analog Converter (VDAC)
The Digital to Analog Converter (VDAC) can convert a digital value to an analog output voltage. The VDAC is a fully differential, 500 ksps, 12-bit converter. The opamps are used in conjunction with the VDAC, to provide output buffering. One opamp is used per singleended channel, or two opamps are used to provide differential outputs. The VDAC may be used for a number of different applications such as sensor interfaces or sound output. The VDAC can generate high-resolution analog signals while the MCU is operating at low frequencies and with low total power consumption. Using DMA and a timer, the VDAC can be used to generate waveforms without any CPU intervention. The VDAC is available in all energy modes down to and including EM3.
3.8.7 Operational Amplifiers
The opamps are low power amplifiers with a high degree of flexibility targeting a wide variety of standard opamp application areas, and are available down to EM3. With flexible built-in programming for gain and interconnection they can be configured to support multiple common opamp functions. All pins are also available externally for filter configurations. Each opamp has a rail to rail input and a rail to rail output. They can be used in conjunction with the VDAC module or in stand-alone configurations. The opamps save energy, PCB space, and cost as compared with standalone opamps because they are integrated on-chip.
3.8.8 Liquid Crystal Display Driver (LCD)
The LCD driver is capable of driving a segmented LCD display with up to 8x36 segments. A voltage boost function enables it to provide the LCD display with higher voltage than the supply voltage for the device. A patented charge redistribution driver can reduce the LCD module supply current by up to 40%. In addition, an animation feature can run custom animations on the LCD display without any CPU intervention. The LCD driver can also remain active even in Energy Mode 2 and provides a Frame Counter interrupt that can wake-up the device on a regular basis for updating data.
3.9 Reset Management Unit (RMU)
The RMU is responsible for handling reset of the EFM32GG11. A wide range of reset sources are available, including several power supply monitors, pin reset, software controlled reset, core lockup reset, and watchdog reset.
3.10 Core and Memory
3.10.1 Processor Core
The ARM Cortex-M processor includes a 32-bit RISC processor integrating the following features and tasks in the system: � ARM Cortex-M4 RISC processor with FPU achieving 1.25 Dhrystone MIPS/MHz � Memory Protection Unit (MPU) supporting up to 8 memory segments � Embedded Trace Macrocell (ETM) for real-time trace and debug � Up to 2048 kB flash program memory
� Dual-bank memory with read-while-write support � Up to 512 kB RAM data memory � Configuration and event handling of all modules � 2-pin Serial-Wire or 4-pin JTAG debug interface
3.10.2 Memory System Controller (MSC)
The Memory System Controller (MSC) is the program memory unit of the microcontroller. The flash memory is readable and writable from both the Cortex-M and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code is normally written to the main block, whereas the information block is available for special user data and flash lock bits. There is also a read-only page in the information block containing system and device calibration data. Read and write operations are supported in energy modes EM0 Active and EM1 Sleep.
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EFM32GG11 Family Data Sheet
System Overview
3.10.3 Linked Direct Memory Access Controller (LDMA)
The Linked Direct Memory Access (LDMA) controller allows the system to perform memory operations independently of software. This reduces both energy consumption and software workload. The LDMA allows operations to be linked together and staged, enabling sophisticated operations to be implemented.
3.10.4 Bootloader
All devices come pre-programmed with a UART bootloader. This bootloader resides in flash and can be erased if it is not needed. More information about the bootloader protocol and usage can be found in AN0003: UART Bootloader. Application notes can be found on the Silicon Labs website (www.silabs.com/32bit-appnotes) or within Simplicity Studio in the [Documentation] area.
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EFM32GG11 Family Data Sheet
System Overview
3.11 Memory Map The EFM32GG11 memory map is shown in the figures below. RAM and flash sizes are for the largest memory configuration.
Figure 3.2. EFM32GG11 Memory Map -- Core Peripherals and Code Space
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EFM32GG11 Family Data Sheet
System Overview
Figure 3.3. EFM32GG11 Memory Map -- Peripherals
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EFM32GG11 Family Data Sheet
System Overview
3.12 Configuration Summary The features of the EFM32GG11 are a subset of the feature set described in the device reference manual. The table below describes device specific implementation of the features. Remaining modules support full configuration.
Table 3.2. Configuration Summary
Module USART0 USART1 USART2 USART3 USART4 USART5 TIMER0 TIMER1 TIMER2 TIMER3 TIMER4 TIMER5 TIMER6 WTIMER0 WTIMER1 WTIMER2 WTIMER3
Configuration IrDA, SmartCard I2S, SmartCard IrDA, SmartCard, High-Speed I2S, SmartCard I2S, SmartCard SmartCard with DTI with DTI with DTI with DTI with DTI -
Pin Connections US0_TX, US0_RX, US0_CLK, US0_CS US1_TX, US1_RX, US1_CLK, US1_CS US2_TX, US2_RX, US2_CLK, US2_CS US3_TX, US3_RX, US3_CLK, US3_CS US4_TX, US4_RX, US4_CLK, US4_CS US5_TX, US5_RX, US5_CLK, US5_CS TIM0_CC[2:0], TIM0_CDTI[2:0] TIM1_CC[3:0] TIM2_CC[2:0], TIM2_CDTI[2:0] TIM3_CC[2:0] TIM4_CC[2:0], TIM4_CDTI[2:0] TIM5_CC[2:0] TIM6_CC[2:0], TIM6_CDTI[2:0] WTIM0_CC[2:0], WTIM0_CDTI[2:0] WTIM1_CC[3:0] WTIM2_CC[2:0] WTIM3_CC[2:0]
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4. Electrical Specifications
EFM32GG11 Family Data Sheet
Electrical Specifications
4.1 Electrical Characteristics
All electrical parameters in all tables are specified under the following conditions, unless stated otherwise: � Typical values are based on TAMB=25 �C and VDD= 3.3 V, by production test and/or technology characterization. � Minimum and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature,
unless stated otherwise.
Refer to 4.1.2.1 General Operating Conditions for more details about operational supply and temperature limits.
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EFM32GG11 Family Data Sheet
Electrical Specifications
4.1.1 Absolute Maximum Ratings
Stresses above those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and reliability data, see the Quality and Reliability Monitor Report at http://www.silabs.com/support/quality/pages/default.aspx.
Table 4.1. Absolute Maximum Ratings
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Storage temperature range TSTG
-50
--
150
�C
Voltage on supply pins other VDDMAX than VREGI and VBUS
-0.3
--
3.8
V
Voltage ramp rate on any supply pin
VDDRAMPMAX
--
--
1
V / �s
DC voltage on any GPIO pin VDIGPIN
5V tolerant GPIO pins1 2 3
-0.3
--
Min of 5.25 V
and IOVDD
+2
LCD pins3
-0.3
--
Min of 3.8
V
and IOVDD
+2
Standard GPIO pins
-0.3
--
IOVDD+0.3 V
Total current into VDD power IVDDMAX lines
Source
--
--
200
mA
Total current into VSS ground lines
IVSSMAX
Sink
--
--
200
mA
Current per I/O pin
IIOMAX
Sink Source
--
--
50
mA
--
--
50
mA
Current for all I/O pins
IIOALLMAX
Sink Source
--
--
200
mA
--
--
200
mA
Junction temperature
TJ
-G grade devices -I grade devices
-40
--
105
�C
-40
--
125
�C
Voltage on regulator supply VVREGI pins VREGI and VBUS
-0.3
--
5.5
V
Note:
1. When a GPIO pin is routed to the analog module through the APORT, the maximum voltage = IOVDD.
2. Valid for IOVDD in valid operating range or when IOVDD is undriven (high-Z). If IOVDD is connected to a low-impedance source below the valid operating range (e.g. IOVDD shorted to VSS), the pin voltage maximum is IOVDD + 0.3 V, to avoid exceeding the maximum IO current specifications.
3. To operate above the IOVDD supply rail, over-voltage tolerance must be enabled according to the GPIO_Px_OVTDIS register. Pins with over-voltage tolerance disabled have the same limits as Standard GPIO.
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4.1.2 Operating Conditions
EFM32GG11 Family Data Sheet
Electrical Specifications
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Rev. 1.0 | 26
When assigning supply sources, the following requirements must be observed: � VREGVDD must be greater than or equal to AVDD, DVDD and all IOVDD supplies. � VREGVDD = AVDD � DVDD AVDD � IOVDD AVDD
EFM32GG11 Family Data Sheet
Electrical Specifications
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4.1.2.1 General Operating Conditions
Table 4.2. General Operating Conditions
Parameter
Symbol
Operating ambient tempera- TA ture range6
AVDD supply voltage2
VAVDD
VREGVDD operating supply VVREGVDD voltage2 1
VREGVDD current
IVREGVDD
DVDD operating supply volt- VDVDD age
IOVDD operating supply volt- VIOVDD age
DECOUPLE output capaci- CDECOUPLE tor3 4
HFCORECLK frequency
fCORE
HFCLK frequency
fHFCLK
HFSRCCLK frequency
fHFSRCCLK
HFBUSCLK frequency
fHFBUSCLK
HFPERCLK frequency
fHFPERCLK
HFPERBCLK frequency
fHFPERBCLK
HFPERCCLK frequency
fHFPERCCLK
Test Condition
Min
-G temperature grade
-40
-I temperature grade
-40
1.8
DCDC in regulation
2.4
DCDC in bypass, 50mA load
1.8
DCDC not in use. DVDD external-
1.8
ly shorted to VREGVDD
DCDC in bypass, T 85 �C
--
DCDC in bypass, T > 85 �C
--
1.62
All IOVDD pins5
1.62
0.75
VSCALE2, MODE = WS3
--
VSCALE2, MODE = WS2
--
VSCALE2, MODE = WS1
--
VSCALE2, MODE = WS0
--
VSCALE0, MODE = WS2
--
VSCALE0, MODE = WS1
--
VSCALE0, MODE = WS0
--
VSCALE2
--
VSCALE0
--
VSCALE2
--
VSCALE0
--
VSCALE2
--
VSCALE0
--
VSCALE2
--
VSCALE0
--
VSCALE2
--
VSCALE0
--
VSCALE2
--
VSCALE0
--
EFM32GG11 Family Data Sheet
Electrical Specifications
Typ
Max
Unit
25
85
�C
25
125
�C
3.3
3.8
V
3.3
3.8
V
3.3
3.8
V
3.3
3.8
V
--
200
mA
--
100
mA
--
VVREGVDD
V
--
VVREGVDD
V
1.0
2.75
�F
--
72
MHz
--
54
MHz
--
36
MHz
--
18
MHz
--
20
MHz
--
14
MHz
--
7
MHz
--
72
MHz
--
20
MHz
--
72
MHz
--
20
MHz
--
50
MHz
--
20
MHz
--
50
MHz
--
20
MHz
--
72
MHz
--
20
MHz
--
50
MHz
--
20
MHz
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EFM32GG11 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Note:
1. The minimum voltage required in bypass mode is calculated using RBYP from the DCDC specification table. Requirements for other loads can be calculated as VDVDD_min+ILOAD * RBYP_max.
2. VREGVDD must be tied to AVDD. Both VREGVDD and AVDD minimum voltages must be satisfied for the part to operate.
3. The system designer should consult the characteristic specs of the capacitor used on DECOUPLE to ensure its capacitance value stays within the specified bounds across temperature and DC bias.
4. VSCALE0 to VSCALE2 voltage change transitions occur at a rate of 10 mV / usec for approximately 20 usec. During this transition, peak currents will be dependent on the value of the DECOUPLE output capacitor, from 35 mA (with a 1 �F capacitor) to 70 mA (with a 2.7 �F capacitor).
5. When the CSEN peripheral is used with chopping enabled (CSEN_CTRL_CHOPEN = ENABLE), IOVDD must be equal to AVDD.
6. The maximum limit on TA may be lower due to device self-heating, which depends on the power dissipation of the specific application. TA (max) = TJ (max) - (THETAJA x PowerDissipation). Refer to the Absolute Maximum Ratings table and the Thermal Characteristics table for TJ and THETAJA.
4.1.3 Thermal Characteristics
Table 4.3. Thermal Characteristics
Parameter
Symbol
Test Condition
Min
Thermal resistance, QFN64 THETAJA_QFN64 4-Layer PCB, Air velocity = 0 m/s
--
Package
4-Layer PCB, Air velocity = 1 m/s
--
4-Layer PCB, Air velocity = 2 m/s
--
Thermal resistance, TQFP64 THE-
4-Layer PCB, Air velocity = 0 m/s
--
Package
TAJA_TQFP64
4-Layer PCB, Air velocity = 1 m/s
--
4-Layer PCB, Air velocity = 2 m/s
--
Thermal resistance, TQFP100 Package
THE-
4-Layer PCB, Air velocity = 0 m/s
--
TAJA_TQFP100
4-Layer PCB, Air velocity = 1 m/s
--
4-Layer PCB, Air velocity = 2 m/s
--
Thermal resistance, BGA112 THE-
4-Layer PCB, Air velocity = 0 m/s
--
Package
TAJA_BGA112
4-Layer PCB, Air velocity = 1 m/s
--
4-Layer PCB, Air velocity = 2 m/s
--
Thermal resistance, BGA120 THE-
4-Layer PCB, Air velocity = 0 m/s
--
Package
TAJA_BGA120
4-Layer PCB, Air velocity = 1 m/s
--
4-Layer PCB, Air velocity = 2 m/s
--
Thermal resistance, BGA152 THE-
4-Layer PCB, Air velocity = 0 m/s
--
Package
TAJA_BGA152
4-Layer PCB, Air velocity = 1 m/s
--
4-Layer PCB, Air velocity = 2 m/s
--
Thermal resistance, BGA192 THE-
4-Layer PCB, Air velocity = 0 m/s
--
Package
TAJA_BGA192
4-Layer PCB, Air velocity = 1 m/s
--
4-Layer PCB, Air velocity = 2 m/s
--
Typ 17.8 15.4 13.8 33.9 32.1 30.1 44.1 37.7 35.5 42.0 37.0 35.3 47.9 41.8 39.6 35.7 31.0 29.5 47.9 41.8 39.6
Max
Unit
--
�C/W
--
�C/W
--
�C/W
--
�C/W
--
�C/W
--
�C/W
--
�C/W
--
�C/W
--
�C/W
--
�C/W
--
�C/W
--
�C/W
--
�C/W
--
�C/W
--
�C/W
--
�C/W
--
�C/W
--
�C/W
--
�C/W
--
�C/W
--
�C/W
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EFM32GG11 Family Data Sheet
Electrical Specifications
4.1.4 DC-DC Converter Test conditions: L_DCDC=4.7 �H (Murata LQH3NPN4R7MM0L), C_DCDC=4.7 �F (Samsung CL10B475KQ8NQNC), V_DCDC_I=3.3 V, V_DCDC_O=1.8 V, I_DCDC_LOAD=50 mA, Heavy Drive configuration, F_DCDC_LN=7 MHz, unless otherwise indicated.
Table 4.4. DC-DC Converter
Parameter Input voltage range
Symbol VDCDC_I
Output voltage programmable range1
Regulation DC accuracy
VDCDC_O ACCDC
Regulation window4
WINREG
Steady-state output ripple VR Output voltage under/over- VOV shoot
DC line regulation DC load regulation
VREG IREG
Test Condition
Min
Bypass mode, IDCDC_LOAD = 50
1.8
mA
Low noise (LN) mode, 1.8 V out-
2.4
put, IDCDC_LOAD = 100 mA, or
Low power (LP) mode, 1.8 V out-
put, IDCDC_LOAD = 10 mA
Low noise (LN) mode, 1.8 V out-
2.6
put, IDCDC_LOAD = 200 mA
1.8
Low Noise (LN) mode, 1.8 V tar-
1.7
get output
Low Power (LP) mode, LPCMPBIASEMxx3 = 0, 1.8 V target output, IDCDC_LOAD 75 �A
Low Power (LP) mode, LPCMPBIASEMxx3 = 3, 1.8 V target output, IDCDC_LOAD 10 mA
1.63 1.63 --
CCM Mode (LNFORCECCM3 =
--
1), Load changes between 0 mA
and 100 mA
DCM Mode (LNFORCECCM3 =
--
0), Load changes between 0 mA
and 10 mA
Overshoot during LP to LN
--
CCM/DCM mode transitions com-
pared to DC level in LN mode
Undershoot during BYP/LP to LN
--
CCM (LNFORCECCM3 = 1) mode
transitions compared to DC level
in LN mode
Undershoot during BYP/LP to LN
--
DCM (LNFORCECCM3 = 0) mode
transitions compared to DC level
in LN mode
Input changes between
--
VVREGVDD_MAX and 2.4 V
Load changes between 0 mA and
--
100 mA in CCM mode
Typ --
--
Max
VVREGVDD_
MAX
VVREGVDD_
MAX
Unit V
V
--
VVREGVDD_
V
MAX
--
VVREGVDD
V
--
1.9
V
--
2.2
V
--
2.1
V
3
--
mVpp
25
60
mV
45
90
mV
200
--
mV
40
--
mV
100
--
mV
0.1
--
%
0.1
--
%
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EFM32GG11 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Max load current
ILOAD_MAX
Low noise (LN) mode, Heavy Drive2, T 85 �C
--
--
200
mA
Low noise (LN) mode, Heavy Drive2, T > 85 �C
--
--
100
mA
Low noise (LN) mode, Medium
--
Drive2
--
100
mA
Low noise (LN) mode, Light Drive2
--
--
50
mA
Low power (LP) mode, LPCMPBIASEMxx3 = 0
--
--
75
�A
Low power (LP) mode, LPCMPBIASEMxx3 = 3
--
--
10
mA
DCDC nominal output capacitor5
CDCDC
25% tolerance
1
4.7
4.7
�F
DCDC nominal output induc- LDCDC tor
20% tolerance
4.7
4.7
4.7
�H
Resistance in Bypass mode RBYP
--
1.2
2.5
Note:
1. Due to internal dropout, the DC-DC output will never be able to reach its input voltage, VVREGVDD.
2. Drive levels are defined by configuration of the PFETCNT and NFETCNT registers. Light Drive: PFETCNT=NFETCNT=3; Medium Drive: PFETCNT=NFETCNT=7; Heavy Drive: PFETCNT=NFETCNT=15.
3. LPCMPBIASEMxx refers to either LPCMPBIASEM234H in the EMU_DCDCMISCCTRL register or LPCMPBIASEM01 in the EMU_DCDCLOEM01CFG register, depending on the energy mode.
4. LP mode controller is a hysteretic controller that maintains the output voltage within the specified limits.
5. Output voltage under/over-shoot and regulation are specified with CDCDC 4.7 �F. Different settings for DCDCLNCOMPCTRL must be used if CDCDC is lower than 4.7 �F. See Application Note AN0948 for details.
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4.1.5 5V Regulator VVREGI = 5 V, VVREGO = 3.3 V, CVREGI = 10 �F, CVREGO = 4.7 �F, unless otherwise specified.
Table 4.5. 5V Regulator
Parameter
VREGI or VBUS input voltage range
Symbol VVREGI
VREGO output voltage
VVREGO
Voltage output step size Resistance in Bypass Mode Output current
VVREGO_SS RBYP IOUT
Load regulation
LRVREGO
DC power supply rejection PSRDC VREGI or VBUS bypass ca- CVREGI pacitance VREGO bypass capacitance CVREGO Supply current consumption IVREGI
VREGI and VBUS detection VDET_H high threshold VREGI and VBUS detection VDET_L low threshold Current monitor transfer ratio IMONXF
Test Condition
Min
Regulating output
2.7
Bypass mode enabled
2.7
Regulating output, 3.3 V setting
3.1
EM4S open-loop output, IOUT <
1.8
100 �A
--
Bypass mode enabled
--
EM0 or EM1, VVREGI > VVREGO +
--
0.6 V
EM0 or EM1, VVREGI > VVREGO +
--
0.3 V
EM2, EM3, or EM4H, VVREGI >
--
VVREGO + 0.6 V
EM2, EM3, or EM4H, VVREGI >
--
VVREGO + 0.3 V
EM4S
--
EM0 or EM1
--
EM2, EM3, or EM4H
--
--
--
1
EM0 or EM1, No load
--
EM2, EM3, or EM4H, No load
--
EM4S, No load
--
0.9
--
Translation of current through
--
VREGO path to voltage at ADC
input
EFM32GG11 Family Data Sheet
Electrical Specifications
Typ
Max
Unit
--
5.5
V
--
3.8
V
3.3
3.5
V
--
3.8
V
0.1
--
V
1.2
2.5
--
200
mA
--
100
mA
--
2
mA
--
0.5
mA
--
20
�A
0.10
--
mV/mA
2.5
--
mV/mA
40
--
dB
10
--
�F
4.7
10
�F
29
--
�A
270
--
nA
70
--
nA
1.15
--
V
1.07
1.45
V
0.35
--
mA/mV
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4.1.6 Backup Supply Domain
EFM32GG11 Family Data Sheet
Electrical Specifications
Table 4.6. Backup Supply Domain
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Backup supply voltage range VBU_VIN
1.8
--
3.8
V
PWRRES resistor
RPWRRES
EMU_BUCTRL_PWRRES = RES0
3400
3900
4400
EMU_BUCTRL_PWRRES = RES1
1450
1800
2150
EMU_BUCTRL_PWRRES = RES2
1000
1350
1700
EMU_BUCTRL_PWRRES = RES3
525
815
1100
Output impedance between RBU_VOUT BU_VIN and BU_VOUT 2
EMU_BUCTRL_VOUTRES = STRONG
35
110
185
EMU_BUCTRL_VOUTRES = MED
475
775
1075
EMU_BUCTRL_VOUTRES = WEAK
5600
6500
7400
Supply current
IBU_VIN
BU_VIN not powering backup do-
--
main, 25 �C
11
100
nA
BU_VIN powering backup domain, 25 �C 1
--
550
2500
nA
Note:
1. Additional current required by backup circuitry when backup is active. Includes supply current of backup switches and backup regulator. Does not include supply current required for backed-up circuitry.
2. BU_VOUT and BU_STAT signals are not available in all package configurations. Check the device pinout for availability.
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4.1.7 Current Consumption
EFM32GG11 Family Data Sheet
Electrical Specifications
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Rev. 1.0 | 34
EFM32GG11 Family Data Sheet
Electrical Specifications
4.1.7.1 Current Consumption 3.3 V without DC-DC Converter Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = DVDD = 3.3 V. T = 25 �C. DCDC is off. Minimum and maximum values in this table represent the worst conditions across process variation at T = 25 �C.
Table 4.7. Current Consumption 3.3 V without DC-DC Converter
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Current consumption in EM0 IACTIVE mode with all peripherals disabled
72 MHz HFRCO, CPU running
--
120
--
�A/MHz
Prime from flash
72 MHz HFRCO, CPU running
--
120
130
�A/MHz
while loop from flash
72 MHz HFRCO, CPU running
--
140
--
�A/MHz
CoreMark loop from flash
50 MHz crystal, CPU running while loop from flash
--
123
--
�A/MHz
48 MHz HFRCO, CPU running
--
122
135
�A/MHz
while loop from flash
32 MHz HFRCO, CPU running
--
124
--
�A/MHz
while loop from flash
26 MHz HFRCO, CPU running
--
126
140
�A/MHz
while loop from flash
16 MHz HFRCO, CPU running
--
131
--
�A/MHz
while loop from flash
1 MHz HFRCO, CPU running while loop from flash
--
319
470
�A/MHz
Current consumption in EM0 IACTIVE_VS
19 MHz HFRCO, CPU running
--
107
--
�A/MHz
mode with all peripherals dis-
while loop from flash
abled and voltage scaling enabled
1 MHz HFRCO, CPU running while loop from flash
--
262
--
�A/MHz
Current consumption in EM1 IEM1 mode with all peripherals disabled
72 MHz HFRCO 50 MHz crystal 48 MHz HFRCO
--
57
67
�A/MHz
--
60
--
�A/MHz
--
59
70
�A/MHz
32 MHz HFRCO
--
61
--
�A/MHz
26 MHz HFRCO
--
63
75
�A/MHz
16 MHz HFRCO
--
68
--
�A/MHz
1 MHz HFRCO
--
255
420
�A/MHz
Current consumption in EM1 IEM1_VS mode with all peripherals disabled and voltage scaling enabled
19 MHz HFRCO 1 MHz HFRCO
--
55
--
�A/MHz
--
210
--
�A/MHz
Current consumption in EM2 IEM2_VS
Full 512 kB RAM retention and
--
3.9
--
�A
mode, with voltage scaling
RTCC running from LFXO
enabled
Full 512 kB RAM retention and
--
4.3
--
�A
RTCC running from LFRCO
16 kB (1 bank) RAM retention and
--
RTCC running from LFRCO2
2.8
5.5
�A
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Rev. 1.0 | 35
EFM32GG11 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Current consumption in EM3 IEM3_VS
Full 512 kB RAM retention and
--
3.6
mode, with voltage scaling
CRYOTIMER running from ULFR-
enabled
CO
7
�A
Current consumption in EM4H mode, with voltage scaling enabled
IEM4H_VS
128 byte RAM retention, RTCC
--
running from LFXO
128 byte RAM retention, CRYO-
--
TIMER running from ULFRCO
1.08 0.69
--
�A
--
�A
128 byte RAM retention, no RTCC
--
0.6
1
�A
Current consumption in EM4S mode
IEM4S
No RAM retention, no RTCC
--
0.06
0.2
�A
Current consumption of pe- IPD1_VS ripheral power domain 1, with voltage scaling enabled
Additional current consumption in
--
EM2/3 when any peripherals on
power domain 1 are enabled1
0.68
--
�A
Current consumption of pe- IPD2_VS ripheral power domain 2, with voltage scaling enabled
Additional current consumption in
--
EM2/3 when any peripherals on
power domain 2 are enabled1
0.28
--
�A
Note:
1. Extra current consumed by power domain. Does not include current associated with the enabled peripherals. See 3.2.4 EM2 and EM3 Power Domains for a list of the peripherals in each power domain.
2. CMU_LFRCOCTRL_ENVREF = 1, CMU_LFRCOCTRL_VREFUPDATE = 1
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Rev. 1.0 | 36
EFM32GG11 Family Data Sheet
Electrical Specifications
4.1.7.2 Current Consumption 3.3 V using DC-DC Converter Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = 1.8 V DC-DC output. T = 25 �C. Minimum and maximum values in this table represent the worst conditions across process variation at T = 25 �C.
Table 4.8. Current Consumption 3.3 V using DC-DC Converter
Parameter
Symbol
Current consumption in EM0 IACTIVE_DCM mode with all peripherals disabled, DCDC in Low Noise DCM mode2
Current consumption in EM0 IACTIVE_CCM mode with all peripherals disabled, DCDC in Low Noise CCM mode1
Test Condition
72 MHz HFRCO, CPU running Prime from flash
72 MHz HFRCO, CPU running while loop from flash
72 MHz HFRCO, CPU running CoreMark loop from flash
50 MHz crystal, CPU running while loop from flash
48 MHz HFRCO, CPU running while loop from flash
32 MHz HFRCO, CPU running while loop from flash
26 MHz HFRCO, CPU running while loop from flash
16 MHz HFRCO, CPU running while loop from flash
1 MHz HFRCO, CPU running while loop from flash
72 MHz HFRCO, CPU running Prime from flash
72 MHz HFRCO, CPU running while loop from flash
72 MHz HFRCO, CPU running CoreMark loop from flash
50 MHz crystal, CPU running while loop from flash
48 MHz HFRCO, CPU running while loop from flash
32 MHz HFRCO, CPU running while loop from flash
26 MHz HFRCO, CPU running while loop from flash
16 MHz HFRCO, CPU running while loop from flash
1 MHz HFRCO, CPU running while loop from flash
Min
Typ
Max
Unit
--
80
--
�A/MHz
--
80
--
�A/MHz
--
92
--
�A/MHz
--
84
--
�A/MHz
--
84
--
�A/MHz
--
90
--
�A/MHz
--
94
--
�A/MHz
--
109
--
�A/MHz
--
698
--
�A/MHz
--
84
--
�A/MHz
--
84
--
�A/MHz
--
95
--
�A/MHz
--
91
--
�A/MHz
--
92
--
�A/MHz
--
104
--
�A/MHz
--
113
--
�A/MHz
--
142
--
�A/MHz
--
1264
--
�A/MHz
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Parameter
Symbol
Test Condition
Min
Current consumption in EM0 IACTIVE_LPM
32 MHz HFRCO, CPU running
--
mode with all peripherals dis-
while loop from flash
abled, DCDC in LP mode3
26 MHz HFRCO, CPU running
--
while loop from flash
16 MHz HFRCO, CPU running
--
while loop from flash
1 MHz HFRCO, CPU running
--
while loop from flash
Current consumption in EM0 IACTIVE_CCM_VS 19 MHz HFRCO, CPU running
--
mode with all peripherals dis-
while loop from flash
abled and voltage scaling enabled, DCDC in Low Noise CCM mode1
1 MHz HFRCO, CPU running
--
while loop from flash
Current consumption in EM0 IACTIVE_LPM_VS 19 MHz HFRCO, CPU running
--
mode with all peripherals dis-
while loop from flash
abled and voltage scaling enabled, DCDC in LP mode3
1 MHz HFRCO, CPU running
--
while loop from flash
Current consumption in EM1 IEM1_DCM
72 MHz HFRCO
--
mode with all peripherals dis-
abled, DCDC in Low Noise
50 MHz crystal
--
DCM mode2
48 MHz HFRCO
--
32 MHz HFRCO
--
26 MHz HFRCO
--
16 MHz HFRCO
--
1 MHz HFRCO
--
Current consumption in EM1 IEM1_LPM
32 MHz HFRCO
--
mode with all peripherals dis-
abled, DCDC in Low Power
26 MHz HFRCO
--
mode3
16 MHz HFRCO
--
1 MHz HFRCO
--
Current consumption in EM1 IEM1_DCM_VS
19 MHz HFRCO
--
mode with all peripherals dis-
abled and voltage scaling
1 MHz HFRCO
--
enabled, DCDC in Low
Noise DCM mode2
Current consumption in EM1 IEM1_LPM_VS
19 MHz HFRCO
--
mode with all peripherals dis-
abled and voltage scaling
1 MHz HFRCO
--
enabled. DCDC in LP mode3
Current consumption in EM2 IEM2_VS mode, with voltage scaling enabled, DCDC in LP mode3
Full 512 kB RAM retention and
--
RTCC running from LFXO
Full 512 kB RAM retention and
--
RTCC running from LFRCO
16 kB (1 bank) RAM retention and
--
RTCC running from LFRCO5
Current consumption in EM3 IEM3_VS mode, with voltage scaling enabled
Full 512 kB RAM retention and
--
CRYOTIMER running from ULFR-
CO
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EFM32GG11 Family Data Sheet
Electrical Specifications
Typ
Max
Unit
82
--
�A/MHz
83
--
�A/MHz
88
--
�A/MHz
257
--
�A/MHz
117
--
�A/MHz
1231
--
�A/MHz
72
--
�A/MHz
219
--
�A/MHz
42
--
�A/MHz
46
--
�A/MHz
46
--
�A/MHz
53
--
�A/MHz
57
--
�A/MHz
72
--
�A/MHz
663
--
�A/MHz
42
--
�A/MHz
43
--
�A/MHz
48
--
�A/MHz
219
--
�A/MHz
60
--
�A/MHz
637
--
�A/MHz
39
--
�A/MHz
190
--
�A/MHz
2.8
--
�A
3.1
--
�A
2.1
--
�A
2.4
--
�A
Rev. 1.0 | 38
EFM32GG11 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Current consumption in EM4H mode, with voltage scaling enabled
IEM4H_VS
128 byte RAM retention, RTCC
--
running from LFXO
128 byte RAM retention, CRYO-
--
TIMER running from ULFRCO
0.94 0.62
--
�A
--
�A
128 byte RAM retention, no RTCC
--
0.62
--
�A
Current consumption in EM4S mode
IEM4S
No RAM retention, no RTCC
--
0.13
--
�A
Current consumption of peripheral power domain 1, with voltage scaling enabled, DCDC in LP mode3
IPD1_VS
Additional current consumption in
--
EM2/3 when any peripherals on
power domain 1 are enabled4
0.68
--
�A
Current consumption of peripheral power domain 2, with voltage scaling enabled, DCDC in LP mode3
IPD2_VS
Additional current consumption in
--
EM2/3 when any peripherals on
power domain 2 are enabled4
0.28
--
�A
Note:
1. DCDC Low Noise CCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=6.4 MHz (RCOBAND=4), ANASW=DVDD.
2. DCDC Low Noise DCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=3.0 MHz (RCOBAND=0), ANASW=DVDD.
3. DCDC Low Power Mode = Medium Drive (PFETCNT=NFETCNT=7), LPOSCDIV=1, LPCMPBIASEM234H=0, LPCLIMILIMSEL=1, ANASW=DVDD.
4. Extra current consumed by power domain. Does not include current associated with the enabled peripherals. See 3.2.4 EM2 and EM3 Power Domains for a list of the peripherals in each power domain.
5. CMU_LFRCOCTRL_ENVREF = 1, CMU_LFRCOCTRL_VREFUPDATE = 1
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Rev. 1.0 | 39
EFM32GG11 Family Data Sheet
Electrical Specifications
4.1.7.3 Current Consumption 1.8 V without DC-DC Converter Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = DVDD = 1.8 V. T = 25 �C. DCDC is off. Minimum and maximum values in this table represent the worst conditions across process variation at T = 25 �C.
Table 4.9. Current Consumption 1.8 V without DC-DC Converter
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Current consumption in EM0 IACTIVE mode with all peripherals disabled
72 MHz HFRCO, CPU running
--
120
--
�A/MHz
Prime from flash
72 MHz HFRCO, CPU running
--
120
--
�A/MHz
while loop from flash
72 MHz HFRCO, CPU running
--
140
--
�A/MHz
CoreMark loop from flash
50 MHz crystal, CPU running while loop from flash
--
122
--
�A/MHz
48 MHz HFRCO, CPU running
--
122
--
�A/MHz
while loop from flash
32 MHz HFRCO, CPU running
--
124
--
�A/MHz
while loop from flash
26 MHz HFRCO, CPU running
--
126
--
�A/MHz
while loop from flash
16 MHz HFRCO, CPU running
--
131
--
�A/MHz
while loop from flash
1 MHz HFRCO, CPU running while loop from flash
--
315
--
�A/MHz
Current consumption in EM0 IACTIVE_VS
19 MHz HFRCO, CPU running
--
107
--
�A/MHz
mode with all peripherals dis-
while loop from flash
abled and voltage scaling enabled
1 MHz HFRCO, CPU running while loop from flash
--
259
--
�A/MHz
Current consumption in EM1 IEM1 mode with all peripherals disabled
72 MHz HFRCO 50 MHz crystal 48 MHz HFRCO
--
57
--
�A/MHz
--
59
--
�A/MHz
--
59
--
�A/MHz
32 MHz HFRCO
--
61
--
�A/MHz
26 MHz HFRCO
--
63
--
�A/MHz
16 MHz HFRCO
--
68
--
�A/MHz
1 MHz HFRCO
--
252
--
�A/MHz
Current consumption in EM1 IEM1_VS mode with all peripherals disabled and voltage scaling enabled
19 MHz HFRCO 1 MHz HFRCO
--
55
--
�A/MHz
--
207
--
�A/MHz
Current consumption in EM2 IEM2_VS
Full 512 kB RAM retention and
--
3.7
--
�A
mode, with voltage scaling
RTCC running from LFXO
enabled
Full 512 kB RAM retention and
--
4.0
--
�A
RTCC running from LFRCO
16 kB (1 bank) RAM retention and
--
2.5
--
�A
RTCC running from LFRCO2
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EFM32GG11 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Current consumption in EM3 IEM3_VS
Full 512 kB RAM retention and
--
3.4
--
�A
mode, with voltage scaling
CRYOTIMER running from ULFR-
enabled
CO
Current consumption in EM4H mode, with voltage scaling enabled
IEM4H_VS
128 byte RAM retention, RTCC
--
running from LFXO
128 byte RAM retention, CRYO-
--
TIMER running from ULFRCO
0.94 0.56
--
�A
--
�A
128 byte RAM retention, no RTCC
--
0.56
--
�A
Current consumption in EM4S mode
IEM4S
No RAM retention, no RTCC
--
0.1
--
�A
Current consumption of pe- IPD1_VS ripheral power domain 1, with voltage scaling enabled
Additional current consumption in
--
EM2/3 when any peripherals on
power domain 1 are enabled1
0.68
--
�A
Current consumption of pe- IPD2_VS ripheral power domain 2, with voltage scaling enabled
Additional current consumption in
--
EM2/3 when any peripherals on
power domain 2 are enabled1
0.28
--
�A
Note:
1. Extra current consumed by power domain. Does not include current associated with the enabled peripherals. See 3.2.4 EM2 and EM3 Power Domains for a list of the peripherals in each power domain.
2. CMU_LFRCOCTRL_ENVREF = 1, CMU_LFRCOCTRL_VREFUPDATE = 1
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4.1.8 Wake Up Times
EFM32GG11 Family Data Sheet
Electrical Specifications
Table 4.10. Wake Up Times
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Wake up time from EM1
tEM1_WU
--
3
--
AHB
Clocks
Wake up from EM2
tEM2_WU
Code execution from flash Code execution from RAM
--
11.8
--
�s
--
4.1
--
�s
Wake up from EM3
tEM3_WU
Code execution from flash Code execution from RAM
--
11.8
--
�s
--
4.1
--
�s
Wake up from EM4H1
tEM4H_WU
Executing from flash
--
94
--
�s
Wake up from EM4S1
tEM4S_WU
Executing from flash
--
294
--
�s
Time from release of reset tRESET source to first instruction execution
Soft Pin Reset released Any other reset released
--
55
--
�s
--
359
--
�s
Power mode scaling time
tSCALE
VSCALE0 to VSCALE2, HFCLK =
--
19 MHz4 2
31.8
--
�s
VSCALE2 to VSCALE0, HFCLK =
--
4.3
--
�s
19 MHz3
Note:
1. Time from wake up request until first instruction is executed. Wakeup results in device reset.
2. VSCALE0 to VSCALE2 voltage change transitions occur at a rate of 10 mV/�s for approximately 20 �s. During this transition, peak currents will be dependent on the value of the DECOUPLE output capacitor, from 35 mA (with a 1 �F capacitor) to 70 mA (with a 2.7 �F capacitor).
3. Scaling down from VSCALE2 to VSCALE0 requires approximately 2.8 �s + 29 HFCLKs.
4. Scaling up from VSCALE0 to VSCALE2 requires approximately 30.3 �s + 28 HFCLKs.
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Rev. 1.0 | 42
4.1.9 Brown Out Detector (BOD)
Table 4.11. Brown Out Detector (BOD)
Parameter DVDD BOD threshold
DVDD BOD hysteresis DVDD BOD response time AVDD BOD threshold
AVDD BOD hysteresis AVDD BOD response time EM4 BOD threshold
EM4 BOD hysteresis EM4 BOD response time
Symbol
Test Condition
VDVDDBOD
DVDD rising DVDD falling (EM0/EM1)
DVDD falling (EM2/EM3)
VDVDDBOD_HYST
tDVDDBOD_DELAY Supply drops at 0.1V/�s rate
VAVDDBOD
AVDD rising AVDD falling (EM0/EM1)
AVDD falling (EM2/EM3)
VAVDDBOD_HYST
tAVDDBOD_DELAY Supply drops at 0.1V/�s rate
VEM4DBOD
AVDD rising AVDD falling
VEM4BOD_HYST
tEM4BOD_DELAY Supply drops at 0.1V/�s rate
Min -- 1.35 1.3 -- -- -- 1.62 1.53 -- -- -- 1.45 -- --
EFM32GG11 Family Data Sheet
Electrical Specifications
Typ
Max
Unit
--
1.62
V
--
--
V
--
--
V
18
--
mV
2.4
--
�s
--
1.8
V
--
--
V
--
--
V
20
--
mV
2.4
--
�s
--
1.7
V
--
--
V
25
--
mV
300
--
�s
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Rev. 1.0 | 43
4.1.10 Oscillators 4.1.10.1 Low-Frequency Crystal Oscillator (LFXO)
EFM32GG11 Family Data Sheet
Electrical Specifications
Table 4.12. Low-Frequency Crystal Oscillator (LFXO)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Crystal frequency
fLFXO
--
32.768
--
kHz
Supported crystal equivalent ESRLFXO series resistance (ESR)
--
--
70
k
Supported range of crystal load capacitance 1
CLFXO_CL
6
--
18
pF
On-chip tuning cap range 2 CLFXO_T
On each of LFXTAL_N and LFXTAL_P pins
8
--
40
pF
On-chip tuning cap step size SSLFXO
--
0.25
--
pF
Current consumption after startup 3
ILFXO
ESR = 70 kOhm, CL = 7 pF, GAIN4 = 2, AGC4 = 1
--
273
--
nA
Start- up time
tLFXO
ESR = 70 kOhm, CL = 7 pF, GAIN4 = 2
--
308
--
ms
Note: 1. Total load capacitance as seen by the crystal. 2. The effective load capacitance seen by the crystal will be CLFXO_T /2. This is because each XTAL pin has a tuning cap and the two caps will be seen in series by the crystal. 3. Block is supplied by AVDD if ANASW = 0, or DVDD if ANASW=1 in EMU_PWRCTRL register. 4. In CMU_LFXOCTRL register.
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Rev. 1.0 | 44
4.1.10.2 High-Frequency Crystal Oscillator (HFXO)
EFM32GG11 Family Data Sheet
Electrical Specifications
Table 4.13. High-Frequency Crystal Oscillator (HFXO)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Crystal frequency
fHFXO
No clock doubling Clock doubler enabled
4
--
50
MHz
4
--
25
MHz
Supported crystal equivalent ESRHFXO series resistance (ESR)
50 MHz crystal 24 MHz crystal
--
--
50
--
--
150
4 MHz crystal
--
--
180
Nominal on-chip tuning cap CHFXO_T range1
On each of HFXTAL_N and HFXTAL_P pins
8.7
--
51.7
pF
On-chip tuning capacitance SSHFXO step
--
0.084
--
pF
Startup time
tHFXO
50 MHz crystal, ESR = 50 Ohm,
--
350
--
�s
CL = 8 pF
24 MHz crystal, ESR = 150 Ohm,
--
700
--
�s
CL = 6 pF
4 MHz crystal, ESR = 180 Ohm,
--
3
--
ms
CL = 18 pF
Current consumption after startup
IHFXO
50 MHz crystal 24 MHz crystal
--
880
--
�A
--
420
--
�A
4 MHz crystal
--
80
--
�A
Note:
1. The effective load capacitance seen by the crystal will be CHFXO_T /2. This is because each XTAL pin has a tuning cap and the two caps will be seen in series by the crystal.
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Rev. 1.0 | 45
4.1.10.3 Low-Frequency RC Oscillator (LFRCO)
EFM32GG11 Family Data Sheet
Electrical Specifications
Table 4.14. Low-Frequency RC Oscillator (LFRCO)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Oscillation frequency
fLFRCO
ENVREF2 = 1, T 85 �C
31.3
32.768
33.6
kHz
ENVREF2 = 1, T > 85 �C
31
32.768
36.8
kHz
ENVREF2 = 0, T 85 �C
31.3
32.768
33.4
kHz
ENVREF2 = 0, T > 85 �C
30
32.768
33.6
kHz
Startup time
tLFRCO
--
500
--
�s
Current consumption 1
ILFRCO
ENVREF = 1 in CMU_LFRCOCTRL
--
370
--
nA
ENVREF = 0 in CMU_LFRCOCTRL
--
520
--
nA
Note: 1. Block is supplied by AVDD if ANASW = 0, or DVDD if ANASW=1 in EMU_PWRCTRL register. 2. In CMU_LFRCOCTRL register.
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4.1.10.4 High-Frequency RC Oscillator (HFRCO)
EFM32GG11 Family Data Sheet
Electrical Specifications
Table 4.15. High-Frequency RC Oscillator (HFRCO)
Parameter
Symbol
Test Condition
Min
Typ
Frequency accuracy
fHFRCO_ACC
At production calibrated frequen-
-2.5
--
cies, across supply voltage and
temperature
Start-up time
tHFRCO
fHFRCO 19 MHz
--
300
4 < fHFRCO < 19 MHz
--
1
fHFRCO 4 MHz
--
2.5
Maximum DPLL lock time1 tDPLL_LOCK
fREF = 32.768 kHz, fHFRCO = 39.98 MHz, N = 1219, M = 0
--
183
Current consumption on all IHFRCO supplies
fHFRCO = 72 MHz fHFRCO = 64 MHz
--
610
--
550
fHFRCO = 56 MHz
--
482
fHFRCO = 48 MHz
--
413
fHFRCO = 38 MHz
--
341
fHFRCO = 32 MHz
--
286
fHFRCO = 26 MHz
--
240
fHFRCO = 19 MHz
--
191
fHFRCO = 16 MHz
--
164
fHFRCO = 13 MHz
--
144
fHFRCO = 7 MHz
--
103
fHFRCO = 4 MHz
--
42
fHFRCO = 2 MHz
--
33
fHFRCO = 1 MHz
--
28
fHFRCO = 72 MHz, DPLL enabled
--
930
fHFRCO = 40 MHz, DPLL enabled
--
526
fHFRCO = 32 MHz, DPLL enabled
--
419
fHFRCO = 16 MHz, DPLL enabled
--
233
fHFRCO = 4 MHz, DPLL enabled
--
60
fHFRCO = 1 MHz, DPLL enabled
--
36
Coarse trim step size (% of period)
SSHFRCO_COARS
E
--
0.8
Fine trim step size (% of pe- SSHFRCO_FINE riod)
--
0.1
Period jitter
PJHFRCO
--
0.2
Max
Unit
2.5
%
--
ns
--
�s
--
�s
--
�s
690
�A
615
�A
535
�A
470
�A
390
�A
330
�A
275
�A
220
�A
200
�A
180
�A
130
�A
60
�A
43
�A
38
�A
1200
�A
700
�A
520
�A
280
�A
100
�A
60
�A
--
%
--
%
--
% RMS
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Parameter
Symbol
Test Condition
Min
Frequency limits
fHFRCO_BAND
FREQRANGE = 0, FINETUNIN-
1
GEN = 0
FREQRANGE = 3, FINETUNIN-
2
GEN = 0
FREQRANGE = 6, FINETUNIN-
4
GEN = 0
FREQRANGE = 7, FINETUNIN-
5
GEN = 0
FREQRANGE = 8, FINETUNIN-
7
GEN = 0
FREQRANGE = 10, FINETUNIN-
12
GEN = 0
FREQRANGE = 11, FINETUNIN-
15
GEN = 0
FREQRANGE = 12, FINETUNIN-
18
GEN = 0
FREQRANGE = 13, FINETUNIN-
24
GEN = 0
FREQRANGE = 14, FINETUNIN-
28
GEN = 0
FREQRANGE = 15, FINETUNIN-
33
GEN = 0
FREQRANGE = 16, FINETUNIN-
43
GEN = 0
Note: 1. Maximum DPLL lock time ~= 6 x (M+1) x tREF, where tREF is the reference clock period.
EFM32GG11 Family Data Sheet
Electrical Specifications
Typ
Max
Unit
--
10
MHz
--
17
MHz
--
30
MHz
--
34
MHz
--
42
MHz
--
58
MHz
--
68
MHz
--
83
MHz
--
100
MHz
--
119
MHz
--
138
MHz
--
163
MHz
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4.1.10.5 Auxiliary High-Frequency RC Oscillator (AUXHFRCO)
EFM32GG11 Family Data Sheet
Electrical Specifications
Table 4.16. Auxiliary High-Frequency RC Oscillator (AUXHFRCO)
Parameter
Symbol
Test Condition
Min
Typ
Frequency accuracy
fAUXHFRCO_ACC At production calibrated frequen-
-3
--
cies, across supply voltage and
temperature
Start-up time
tAUXHFRCO
fAUXHFRCO 19 MHz
--
400
4 < fAUXHFRCO < 19 MHz
--
1.4
fAUXHFRCO 4 MHz
--
2.5
Current consumption on all IAUXHFRCO supplies
fAUXHFRCO = 50 MHz fAUXHFRCO = 48 MHz
--
289
--
276
fAUXHFRCO = 38 MHz
--
227
fAUXHFRCO = 32 MHz
--
186
fAUXHFRCO = 26 MHz
--
158
fAUXHFRCO = 19 MHz
--
126
fAUXHFRCO = 16 MHz
--
114
fAUXHFRCO = 13 MHz
--
88
fAUXHFRCO = 7 MHz
--
59
fAUXHFRCO = 4 MHz
--
33
fAUXHFRCO = 2 MHz
--
28
fAUXHFRCO = 1 MHz
--
26
Coarse trim step size (% of period)
SSAUXHFR-
CO_COARSE
--
0.8
Fine trim step size (% of pe- SSAUXHFR-
riod)
CO_FINE
--
0.1
Period jitter
PJAUXHFRCO
--
0.2
Max
Unit
3
%
--
ns
--
�s
--
�s
335
�A
320
�A
265
�A
220
�A
190
�A
160
�A
140
�A
112
�A
72
�A
42
�A
37
�A
33
�A
--
%
--
%
--
% RMS
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4.1.10.6 Universal High-Frequency RC Oscillator (USHFRCO)
EFM32GG11 Family Data Sheet
Electrical Specifications
Table 4.17. Universal High-Frequency RC Oscillator (USHFRCO)
Parameter
Symbol
Test Condition
Min
Typ
Frequency accuracy
fUSHFRCO_ACC At production calibrated frequen-
-2.5
--
cies, across supply voltage and
temperature
USB clock recovery enabled, Ac-
-0.25
--
tive connection as device, FINE-
TUNINGEN1 = 1
Start-up time
tUSHFRCO
--
300
Current consumption on all IUSHFRCO
fUSHFRCO = 48 MHz, FINETUNIN-
--
340
supplies
GEN1 = 1
fUSHFRCO = 50 MHz, FINETUNIN-
--
320
GEN1 = 0
fUSHFRCO = 48 MHz, FINETUNIN-
--
300
GEN1 = 0
fUSHFRCO = 32 MHz, FINETUNIN-
--
200
GEN1 = 0
fUSHFRCO = 16 MHz, FINETUNIN-
--
120
GEN1 = 0
Period jitter
PJUSHFRCO
--
0.2
Note: 1. In the CMU_USHFRCOCTRL register.
Max
Unit
2.5
%
0.25
%
--
ns
400
�A
380
�A
370
�A
240
�A
160
�A
--
% RMS
4.1.10.7 Ultra-low Frequency RC Oscillator (ULFRCO)
Parameter Oscillation frequency
Table 4.18. Ultra-low Frequency RC Oscillator (ULFRCO)
Symbol fULFRCO
Test Condition
Min
Typ
0.88
1
Max
Unit
1.12
kHz
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4.1.11 Flash Memory Characteristics5
EFM32GG11 Family Data Sheet
Electrical Specifications
Table 4.19. Flash Memory Characteristics5
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Flash erase cycles before failure
ECFLASH
10000
--
--
cycles
Flash data retention
RETFLASH
T 85 �C T 125 �C
10
--
--
years
10
--
--
years
Word (32-bit) programming tW_PROG time
Burst write, 128 words, average
20
time per word
26.2
32
�s
Single word
59
68.7
83
�s
Page erase time4
tPERASE
20
26.8
35
ms
Mass erase time1
tMERASE
20
26.9
35
ms
Device erase time2 3
tDERASE
T 85 �C T 125 �C
--
80.7
95
ms
--
80.7
100
ms
Erase current6
IERASE
Page Erase Mass or Device Erase
--
--
1.7
mA
--
--
2.1
mA
Write current6
IWRITE
--
--
3.9
mA
Supply voltage during flash VFLASH erase and write
1.62
--
3.6
V
Note:
1. Mass erase is issued by the CPU and erases all flash.
2. Device erase is issued over the AAP interface and erases all flash, SRAM, the Lock Bit (LB) page, and the User data page Lock Word (ULW).
3. From setting the DEVICEERASE bit in AAP_CMD to 1 until the ERASEBUSY bit in AAP_STATUS is cleared to 0. Internal setup and hold times for flash control signals are included.
4. From setting the ERASEPAGE bit in MSC_WRITECMD to 1 until the BUSY bit in MSC_STATUS is cleared to 0. Internal setup and hold times for flash control signals are included.
5. Flash data retention information is published in the Quarterly Quality and Reliability Report.
6. Measured at 25 �C.
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4.1.12 General-Purpose I/O (GPIO)
EFM32GG11 Family Data Sheet
Electrical Specifications
Table 4.20. General-Purpose I/O (GPIO)
Parameter Input low voltage
Input high voltage
Output high voltage relative to IOVDD
Symbol VIL VIH VOH
Output low voltage relative to VOL IOVDD
Input leakage current
IIOLEAK
Input leakage current on
I5VTOLLEAK
5VTOL pads above IOVDD
I/O pin pull-up/pull-down re- RPUD sistor
Pulse width of pulses re-
tIOGLITCH
moved by the glitch suppres-
sion filter
Test Condition
Min
Typ
Max
Unit
GPIO pins
--
--
IOVDD*0.3 V
GPIO pins
IOVDD*0.7
--
--
V
Sourcing 3 mA, IOVDD 3 V,
IOVDD*0.8
--
--
V
DRIVESTRENGTH1 = WEAK
Sourcing 1.2 mA, IOVDD 1.62 IOVDD*0.6
--
V,
--
V
DRIVESTRENGTH1 = WEAK
Sourcing 20 mA, IOVDD 3 V, IOVDD*0.8
--
--
V
DRIVESTRENGTH1 = STRONG
Sourcing 8 mA, IOVDD 1.62 V, IOVDD*0.6
--
--
V
DRIVESTRENGTH1 = STRONG
Sinking 3 mA, IOVDD 3 V,
--
--
IOVDD*0.2 V
DRIVESTRENGTH1 = WEAK
Sinking 1.2 mA, IOVDD 1.62 V,
--
--
IOVDD*0.4 V
DRIVESTRENGTH1 = WEAK
Sinking 20 mA, IOVDD 3 V,
--
--
IOVDD*0.2 V
DRIVESTRENGTH1 = STRONG
Sinking 8 mA, IOVDD 1.62 V,
--
--
IOVDD*0.4 V
DRIVESTRENGTH1 = STRONG
All GPIO except BUVIN, LFXO,
--
0.1
40
nA
and USB pins, GPIO IOVDD, T
85 �C
BUVIN, LFXO, and USB pins,
--
0.1
60
nA
GPIO IOVDD, T 85 �C
All GPIO except BUVIN, LFXO,
--
and USB pins, GPIO IOVDD, T
> 85 �C
--
150
nA
BUVIN, LFXO, and USB pins,
--
--
300
nA
GPIO IOVDD, T > 85 �C
IOVDD < GPIO IOVDD + 2 V
--
3.3
15
�A
30
40
65
k
15
25
35
ns
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Parameter
Output fall time, From 70% to 30% of VIO
Symbol tIOOF
Output rise time, From 30% tIOOR to 70% of VIO
Required external series re- RUSB sistor on USB D+ and D-
Note: 1. In GPIO_Pn_CTRL register.
Test Condition CL = 50 pF, DRIVESTRENGTH1 = STRONG, SLEWRATE1 = 0x6 CL = 50 pF, DRIVESTRENGTH1 = WEAK, SLEWRATE1 = 0x6 CL = 50 pF, DRIVESTRENGTH1 = STRONG, SLEWRATE = 0x61 CL = 50 pF, DRIVESTRENGTH1 = WEAK, SLEWRATE1 = 0x6
EFM32GG11 Family Data Sheet
Electrical Specifications
Min
Typ
Max
Unit
--
1.8
--
ns
--
4.5
--
ns
--
2.2
--
ns
--
7.4
--
ns
--
33 +/-10%
--
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Rev. 1.0 | 53
4.1.13 Voltage Monitor (VMON)
Table 4.21. Voltage Monitor (VMON)
Parameter
Supply current (including I_SENSE)
Symbol IVMON
Loading of monitored supply ISENSE
Threshold range Threshold step size
VVMON_RANGE NVMON_STESP
Response time Hysteresis
tVMON_RES VVMON_HYST
Test Condition
In EM0 or EM1, 1 supply monitored, T 85 �C
In EM0 or EM1, 1 supply monitored, T > 85 �C
In EM0 or EM1, 4 supplies monitored, T 85 �C
In EM0 or EM1, 4 supplies monitored, T > 85 �C
In EM2, EM3 or EM4, 1 supply monitored and above threshold
In EM2, EM3 or EM4, 1 supply monitored and below threshold
In EM2, EM3 or EM4, 4 supplies monitored and all above threshold
In EM2, EM3 or EM4, 4 supplies monitored and all below threshold
In EM0 or EM1
In EM2, EM3 or EM4
Coarse
Fine
Supply drops at 1V/�s rate
Min --
--
--
--
--
--
--
--
-- -- 1.62 -- -- -- --
EFM32GG11 Family Data Sheet
Electrical Specifications
Typ
Max
Unit
6
11
�A
--
21
�A
15
20
�A
--
32
�A
62
--
nA
62
--
nA
99
--
nA
99
--
nA
2
--
�A
2
--
nA
--
3.4
V
200
--
mV
20
--
mV
460
--
ns
26
--
mV
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EFM32GG11 Family Data Sheet
Electrical Specifications
4.1.14 Analog to Digital Converter (ADC) Specified at 1 Msps, ADCCLK = 16 MHz, BIASPROG = 0, GPBIASACC = 0, unless otherwise indicated.
Table 4.22. Analog to Digital Converter (ADC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Resolution
VRESOLUTION
6
--
12
Bits
Input voltage range5
VADCIN
Single ended
--
--
VFS
V
Differential
-VFS/2
--
VFS/2
V
Input range of external refer- VADCREFIN_P ence voltage, single ended and differential
1
--
VAVDD
V
Power supply rejection2
PSRRADC
At DC
--
80
--
dB
Analog input common mode CMRRADC rejection ratio
At DC
--
80
--
dB
Current from all supplies, us- IADC_CONTINU- 1 Msps / 16 MHz ADCCLK, BIA-
--
ing internal reference buffer. OUS_LP
SPROG = 0, GPBIASACC = 1 3
Continuous operation. WAR-
MUPMODE4 = KEEPADC-
250 ksps / 4 MHz ADCCLK, BIA-
--
WARM
SPROG = 6, GPBIASACC = 1 3
62.5 ksps / 1 MHz ADCCLK, BIA-
--
SPROG = 15, GPBIASACC = 1 3
270
350
�A
125
--
�A
80
--
�A
Current from all supplies, us- IADC_NORMAL_LP 35 ksps / 16 MHz ADCCLK, BIA-
--
45
--
�A
ing internal reference buffer.
SPROG = 0, GPBIASACC = 1 3
Duty-cycled operation. WAR-
MUPMODE4 = NORMAL
5 ksps / 16 MHz ADCCLK BIA-
--
8
--
�A
SPROG = 0, GPBIASACC = 1 3
Current from all supplies, us- IADC_STAND-
125 ksps / 16 MHz ADCCLK, BIA-
--
105
--
�A
ing internal reference buffer. BY_LP
SPROG = 0, GPBIASACC = 1 3
Duty-cycled operation.
AWARMUPMODE4 = KEEPINSTANDBY or KEEPIN-
35 ksps / 16 MHz ADCCLK, BIA-
--
70
--
�A
SPROG = 0, GPBIASACC = 1 3
SLOWACC
Current from all supplies, us- IADC_CONTINU- 1 Msps / 16 MHz ADCCLK, BIA-
--
325
--
�A
ing internal reference buffer. OUS_HP
SPROG = 0, GPBIASACC = 0 3
Continuous operation. WAR-
MUPMODE4 = KEEPADC-
250 ksps / 4 MHz ADCCLK, BIA-
--
175
--
�A
WARM
SPROG = 6, GPBIASACC = 0 3
62.5 ksps / 1 MHz ADCCLK, BIA-
--
125
--
�A
SPROG = 15, GPBIASACC = 0 3
Current from all supplies, us- IADC_NORMAL_HP 35 ksps / 16 MHz ADCCLK, BIA-
--
85
--
�A
ing internal reference buffer.
SPROG = 0, GPBIASACC = 0 3
Duty-cycled operation. WAR-
MUPMODE4 = NORMAL
5 ksps / 16 MHz ADCCLK BIA-
--
16
--
�A
SPROG = 0, GPBIASACC = 0 3
Current from all supplies, us- IADC_STAND-
125 ksps / 16 MHz ADCCLK, BIA-
--
160
--
�A
ing internal reference buffer. BY_HP
SPROG = 0, GPBIASACC = 0 3
Duty-cycled operation.
AWARMUPMODE4 = KEEPINSTANDBY or KEEPIN-
35 ksps / 16 MHz ADCCLK, BIA-
--
125
--
�A
SPROG = 0, GPBIASACC = 0 3
SLOWACC
Current from HFPERCLK
IADC_CLK
HFPERCLK = 16 MHz
--
180
--
�A
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EFM32GG11 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
ADC clock frequency
fADCCLK
--
--
16
MHz
Throughput rate
fADCRATE
--
--
1
Msps
Conversion time1
tADCCONV
6 bit 8 bit
--
7
--
cycles
--
9
--
cycles
12 bit
--
13
--
cycles
Startup time of reference
tADCSTART
WARMUPMODE4 = NORMAL
--
--
generator and ADC core
WARMUPMODE4 = KEEPIN-
--
--
STANDBY
5
�s
2
�s
WARMUPMODE4 = KEEPINSLO-
--
--
WACC
1
�s
SNDR at 1Msps and fIN =
SNDRADC
Internal reference7, differential
58
67
--
dB
10kHz
measurement
External reference6, differential
--
68
--
dB
measurement
Spurious-free dynamic range SFDRADC
1 MSamples/s, 10 kHz full-scale
--
75
--
dB
(SFDR)
sine wave
Differential non-linearity
DNLADC
12 bit resolution, No missing co-
-1
--
2
LSB
(DNL)
des
Integral non-linearity (INL), INLADC End point method
12 bit resolution
-6
--
6
LSB
Offset error
VADCOFFSETERR
-3
0
3
LSB
Gain error in ADC
VADCGAIN
Using internal reference Using external reference
--
-0.2
3.5
%
--
-1
--
%
Temperature sensor slope VTS_SLOPE
--
-1.84
--
mV/�C
Note:
1. Derived from ADCCLK.
2. PSRR is referenced to AVDD when ANASW=0 and to DVDD when ANASW=1 in EMU_PWRCTRL.
3. In ADCn_BIASPROG register.
4. In ADCn_CNTL register.
5. The absolute voltage allowed at any ADC input is dictated by the power rail supplied to on-chip circuitry, and may be lower than the effective full scale voltage. All ADC inputs are limited to the ADC supply (AVDD or DVDD depending on EMU_PWRCTRL_ANASW). Any ADC input routed through the APORT will further be limited by the IOVDD supply to the pin.
6. External reference is 1.25 V applied externally to ADCnEXTREFP, with the selection CONF in the SINGLECTRL_REF or SCANCTRL_REF register field and VREFP in the SINGLECTRLX_VREFSEL or SCANCTRLX_VREFSEL field. The differential input range with this configuration is � 1.25 V.
7. Internal reference option used corresponds to selection 2V5 in the SINGLECTRL_REF or SCANCTRL_REF register field. The differential input range with this configuration is � 1.25 V. Typical value is characterized using full-scale sine wave input. Minimum value is production-tested using sine wave input at 1.5 dB lower than full scale.
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4.1.15 Analog Comparator (ACMP)
Table 4.23. Analog Comparator (ACMP)
Parameter Input voltage range
Supply voltage
Symbol VACMPIN
VACMPVDD
Active current not including IACMP voltage reference2
Current consumption of inter- IACMPREF nal voltage reference2
Test Condition
Min
ACMPVDD =
--
ACMPn_CTRL_PWRSEL 1
BIASPROG4 0x10 or FULL-
1.8
BIAS4 = 0
0x10 < BIASPROG4 0x20 and
2.1
FULLBIAS4 = 1
BIASPROG4 = 1, FULLBIAS4 = 0
--
BIASPROG4 = 0x10, FULLBIAS4
--
= 0
BIASPROG4 = 0x02, FULLBIAS4
--
= 1
BIASPROG4 = 0x20, FULLBIAS4
--
= 1
VLP selected as input using 2.5 V
--
Reference / 4 (0.625 V)
VLP selected as input using VDD
--
VBDIV selected as input using
--
1.25 V reference / 1
VADIV selected as input using
--
VDD/1
EFM32GG11 Family Data Sheet
Electrical Specifications
Typ -- --
--
50 306
Max VACMPVDD
Unit V
VVREGVDD_
V
MAX
VVREGVDD_
V
MAX
--
nA
--
nA
6.5
--
�A
74
100
�A
50
--
nA
20
--
nA
4.1
--
�A
2.4
--
�A
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Rev. 1.0 | 57
Parameter
Hysteresis (VCM = 1.25 V, BIASPROG4 = 0x10, FULLBIAS4 = 1)
Symbol VACMPHYST
Comparator delay3
tACMPDELAY
Offset voltage Reference voltage
VACMPOFFSET VACMPREF
Capacitive sense internal re- RCSRES sistance
Test Condition HYSTSEL5 = HYST0 HYSTSEL5 = HYST1 HYSTSEL5 = HYST2 HYSTSEL5 = HYST3 HYSTSEL5 = HYST4 HYSTSEL5 = HYST5 HYSTSEL5 = HYST6 HYSTSEL5 = HYST7 HYSTSEL5 = HYST8 HYSTSEL5 = HYST9 HYSTSEL5 = HYST10 HYSTSEL5 = HYST11 HYSTSEL5 = HYST12 HYSTSEL5 = HYST13 HYSTSEL5 = HYST14 HYSTSEL5 = HYST15 BIASPROG4 = 1, FULLBIAS4 = 0 BIASPROG4 = 0x10, FULLBIAS4 = 0 BIASPROG4 = 0x02, FULLBIAS4 = 1 BIASPROG4 = 0x20, FULLBIAS4 = 1 BIASPROG4 =0x10, FULLBIAS4 = 1 Internal 1.25 V reference Internal 2.5 V reference CSRESSEL6 = 0 CSRESSEL6 = 1 CSRESSEL6 = 2 CSRESSEL6 = 3 CSRESSEL6 = 4 CSRESSEL6 = 5 CSRESSEL6 = 6 CSRESSEL6 = 7
Min -3 5 12 17 23 26 30 34 -3 -27 -50 -67 -92 -108 -140 -160 -- --
--
--
-35
1 1.98 -- -- -- -- -- -- -- --
EFM32GG11 Family Data Sheet
Electrical Specifications
Typ
Max
Unit
0
3
mV
18
27
mV
33
50
mV
46
67
mV
57
92
mV
68
108
mV
79
140
mV
90
160
mV
0
3
mV
-18
-5
mV
-33
-12
mV
-45
-17
mV
-57
-23
mV
-67
-26
mV
-78
-30
mV
-88
-34
mV
30
--
�s
3.7
--
�s
360
--
ns
35
--
ns
--
35
mV
1.25
1.47
V
2.5
2.8
V
infinite
--
k
15
--
k
27
--
k
39
--
k
51
--
k
100
--
k
162
--
k
235
--
k
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Rev. 1.0 | 58
EFM32GG11 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Note: 1. ACMPVDD is a supply chosen by the setting in ACMPn_CTRL_PWRSEL and may be IOVDD, AVDD or DVDD. 2. The total ACMP current is the sum of the contributions from the ACMP and its internal voltage reference. IACMPTOTAL = IACMP + IACMPREF. 3. � 100 mV differential drive. 4. In ACMPn_CTRL register. 5. In ACMPn_HYSTERESIS registers. 6. In ACMPn_INPUTSEL register.
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4.1.16 Digital to Analog Converter (VDAC) DRIVESTRENGTH = 2 unless otherwise specified. Primary VDAC output.
Table 4.24. Digital to Analog Converter (VDAC)
Parameter Output voltage
Symbol VDACOUT
Current consumption includ- IDAC ing references (2 channels)1
Current from HFPERCLK4 Sample rate DAC clock frequency Conversion time Settling time Startup time
IDAC_CLK SRDAC fDAC tDACCONV tDACSETTLE tDACSTARTUP
Output impedance
ROUT
Power supply rejection ratio6 PSRR
Test Condition
Single-Ended
Differential2
500 ksps, 12-bit, DRIVESTRENGTH = 2, REFSEL = 4
44.1 ksps, 12-bit, DRIVESTRENGTH = 1, REFSEL = 4
200 Hz refresh rate, 12-bit Sample-Off mode in EM2, DRIVESTRENGTH = 2, BGRREQTIME = 1, EM2REFENTIME = 9, REFSEL = 4, SETTLETIME = 0x0A, WARMUPTIME = 0x02
fDAC = 1MHz
50% fs step settling to 5 LSB
Enable to 90% fs output, settling to 10 LSB
DRIVESTRENGTH = 2, 0.4 V VOUT VOPA - 0.4 V, -8 mA < IOUT < 8 mA, Full supply range
DRIVESTRENGTH = 0 or 1, 0.4 V VOUT VOPA - 0.4 V, -400 �A < IOUT < 400 �A, Full supply range
DRIVESTRENGTH = 2, 0.1 V VOUT VOPA - 0.1 V, -2 mA < IOUT < 2 mA, Full supply range
DRIVESTRENGTH = 0 or 1, 0.1 V VOUT VOPA - 0.1 V, -100 �A < IOUT < 100 �A, Full supply range
Vout = 50% fs. DC
Min 0
-VVREF -- -- --
-- -- -- 2 -- -- --
--
--
--
--
EFM32GG11 Family Data Sheet
Electrical Specifications
Typ
Max
Unit
--
VVREF
V
--
VVREF
V
402
--
�A
88
--
�A
2
--
�A
5.25
--
�A/MHz
--
500
ksps
--
1
MHz
--
--
�s
2.5
--
�s
--
12
�s
2
--
2
--
2
--
2
--
65.5
--
dB
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Parameter
Symbol
Test Condition
Signal to noise and distortion SNDRDAC ratio (1 kHz sine wave), Noise band limited to 250 kHz
500 ksps, single-ended, internal 1.25V reference
500 ksps, single-ended, internal 2.5V reference
500 ksps, single-ended, 3.3V VDD reference
500 ksps, differential, internal 1.25V reference
500 ksps, differential, internal 2.5V reference
500 ksps, differential, 3.3V VDD reference
Signal to noise and distortion SNDRDAC_BAND ratio (1 kHz sine wave), Noise band limited to 22 kHz
500 ksps, single-ended, internal 1.25V reference
500 ksps, single-ended, internal 2.5V reference
500 ksps, differential, 3.3V VDD reference
500 ksps, differential, internal 1.25V reference
500 ksps, differential, internal 2.5V reference
500 ksps, single-ended, 3.3V VDD reference
Total harmonic distortion
THD
Differential non-linearity3
DNLDAC
Intergral non-linearity
INLDAC
Offset error5
VOFFSET
T = 25 �C
Across operating temperature range
Gain error5
VGAIN
T = 25 �C, Low-noise internal reference (REFSEL = 1V25LN or 2V5LN)
Across operating temperature range, Low-noise internal reference (REFSEL = 1V25LN or 2V5LN)
External load capactiance, OUTSCALE=0
CLOAD
Min -- -- -- -- -- -- -- -- -- -- -- -- -- -1.25 -4 -8 -25 -2.5
-3.5
--
EFM32GG11 Family Data Sheet
Electrical Specifications
Typ
Max
Unit
60.4
--
dB
61.6
--
dB
64.0
--
dB
63.3
--
dB
64.4
--
dB
65.8
--
dB
65.3
--
dB
66.7
--
dB
68.5
--
dB
67.8
--
dB
69.0
--
dB
70.0
--
dB
70.2
--
dB
--
1.25
LSB
--
4
LSB
--
8
mV
--
25
mV
--
2.5
%
--
3.5
%
--
75
pF
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EFM32GG11 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Note:
1. Supply current specifications are for VDAC circuitry operating with static output only and do not include current required to drive the load.
2. In differential mode, the output is defined as the difference between two single-ended outputs. Absolute voltage on each output is limited to the single-ended range.
3. Entire range is monotonic and has no missing codes.
4. Current from HFPERCLK is dependent on HFPERCLK frequency. This current contributes to the total supply current used when the clock to the DAC module is enabled in the CMU.
5. Gain is calculated by measuring the slope from 10% to 90% of full scale. Offset is calculated by comparing actual VDAC output at 10% of full scale to ideal VDAC output at 10% of full scale with the measured gain.
6. PSRR calculated as 20 * log10(VDD / VOUT), VDAC output at 90% of full scale
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4.1.17 Current Digital to Analog Converter (IDAC)
EFM32GG11 Family Data Sheet
Electrical Specifications
Table 4.25. Current Digital to Analog Converter (IDAC)
Parameter
Symbol
Test Condition
Min
Typ
Number of ranges
NIDAC_RANGES
--
4
Output current
IIDAC_OUT
RANGSEL1 = RANGE0
0.05
--
RANGSEL1 = RANGE1
1.6
--
RANGSEL1 = RANGE2
0.5
--
RANGSEL1 = RANGE3
2
--
Linear steps within each range
NIDAC_STEPS
--
32
Step size
SSIDAC
RANGSEL1 = RANGE0
--
50
RANGSEL1 = RANGE1
--
100
RANGSEL1 = RANGE2
--
500
RANGSEL1 = RANGE3
--
2
Total accuracy, STEPSEL1 = ACCIDAC
EM0 or EM1, AVDD=3.3 V, T = 25
-3
--
0x10
�C
EM0 or EM1, Across operating
-18
--
temperature range
EM2 or EM3, Source mode, RANGSEL1 = RANGE0, AVDD=3.3 V, T = 25 �C
--
-2.7
EM2 or EM3, Source mode, RANGSEL1 = RANGE1, AVDD=3.3 V, T = 25 �C
--
-2.5
EM2 or EM3, Source mode, RANGSEL1 = RANGE2, AVDD=3.3 V, T = 25 �C
--
-1.5
EM2 or EM3, Source mode, RANGSEL1 = RANGE3, AVDD=3.3 V, T = 25 �C
--
-1.0
EM2 or EM3, Sink mode, RANG-
--
-1.1
SEL1 = RANGE0, AVDD=3.3 V, T
= 25 �C
EM2 or EM3, Sink mode, RANG-
--
-1.1
SEL1 = RANGE1, AVDD=3.3 V, T
= 25 �C
EM2 or EM3, Sink mode, RANG-
--
-0.9
SEL1 = RANGE2, AVDD=3.3 V, T
= 25 �C
EM2 or EM3, Sink mode, RANG-
--
-0.9
SEL1 = RANGE3, AVDD=3.3 V, T
= 25 �C
Max
Unit
--
ranges
1.6
�A
4.7
�A
16
�A
64
�A
--
steps
--
nA
--
nA
--
nA
--
�A
3
%
22
%
--
%
--
%
--
%
--
%
--
%
--
%
--
%
--
%
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EFM32GG11 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Start up time
tIDAC_SU
Output within 1% of steady state
--
5
--
�s
value
Settling time, (output settled tIDAC_SETTLE within 1% of steady state value),
Range setting is changed Step value is changed
--
5
--
�s
--
1
--
�s
Current consumption2
IIDAC
EM0 or EM1 Source mode, ex-
--
11
28
�A
cluding output current, Across op-
erating temperature range
EM0 or EM1 Sink mode, exclud-
--
13
30
�A
ing output current, Across operat-
ing temperature range
EM2 or EM3 Source mode, ex-
--
0.05
--
�A
cluding output current, T = 25 �C
EM2 or EM3 Sink mode, exclud-
--
0.07
--
�A
ing output current, T = 25 �C
EM2 or EM3 Source mode, ex-
--
11
--
�A
cluding output current, T 85 �C
EM2 or EM3 Sink mode, exclud-
--
13
--
�A
ing output current, T 85 �C
Output voltage compliance in ICOMP_SRC
RANGESEL1=0, output voltage =
--
0.11
--
%
source mode, source current
min(VIOVDD, VAVDD2-100 mV)
change relative to current
sourced at 0 V
RANGESEL1=1, output voltage =
--
0.06
--
%
min(VIOVDD, VAVDD2-100 mV)
RANGESEL1=2, output voltage =
--
0.04
--
%
min(VIOVDD, VAVDD2-150 mV)
RANGESEL1=3, output voltage =
--
0.03
--
%
min(VIOVDD, VAVDD2-250 mV)
Output voltage compliance in ICOMP_SINK
RANGESEL1=0, output voltage =
--
0.29
--
%
sink mode, sink current
100 mV
change relative to current sunk at IOVDD
RANGESEL1=1, output voltage =
--
0.27
--
%
100 mV
RANGESEL1=2, output voltage =
--
0.12
--
%
150 mV
RANGESEL1=3, output voltage =
--
0.03
--
%
250 mV
Note:
1. In IDAC_CURPROG register.
2. The IDAC is supplied by either AVDD, DVDD, or IOVDD based on the setting of ANASW in the EMU_PWRCTRL register and PWRSEL in the IDAC_CTRL register. Setting PWRSEL to 1 selects IOVDD. With PWRSEL cleared to 0, ANASW selects between AVDD (0) and DVDD (1).
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4.1.18 Capacitive Sense (CSEN)
Table 4.26. Capacitive Sense (CSEN)
Parameter
Single conversion time (1x accumulation)
Symbol tCNV
Maximum external capacitive CEXTMAX load
Maximum external series im- REXTMAX pedance
Supply current, EM2 bonded conversions, WARMUPMODE=NORMAL, WARMUPCNT=0
ICSEN_BOND
Supply current, EM2 scan conversions, WARMUPMODE=NORMAL, WARMUPCNT=0
ICSEN_EM2
Test Condition
Min
12-bit SAR Conversions
--
16-bit SAR Conversions
--
Delta Modulation Conversion (sin-
--
gle comparison)
CS0CG=7 (Gain = 1x), including
--
routing parasitics
CS0CG=0 (Gain = 10x), including
--
routing parasitics
--
12-bit SAR conversions, 20 ms
--
conversion rate, CS0CG=7 (Gain
= 1x), 10 channels bonded (total
capacitance of 330 pF)1
Delta Modulation conversions, 20
--
ms conversion rate, CS0CG=7
(Gain = 1x), 10 channels bonded
(total capacitance of 330 pF)1
12-bit SAR conversions, 200 ms
--
conversion rate, CS0CG=7 (Gain
= 1x), 10 channels bonded (total
capacitance of 330 pF)1
Delta Modulation conversions,
--
200 ms conversion rate,
CS0CG=7 (Gain = 1x), 10 chan-
nels bonded (total capacitance of
330 pF)1
12-bit SAR conversions, 20 ms
--
scan rate, CS0CG=0 (Gain =
10x), 8 samples per scan1
Delta Modulation conversions, 20
--
ms scan rate, 8 comparisons per
sample (DMCR = 1, DMR = 2),
CS0CG=0 (Gain = 10x), 8 sam-
ples per scan1
12-bit SAR conversions, 200 ms
--
scan rate, CS0CG=0 (Gain =
10x), 8 samples per scan1
Delta Modulation conversions,
--
200 ms scan rate, 8 comparisons
per sample (DMCR = 1, DMR =
2), CS0CG=0 (Gain = 10x), 8
samples per scan1
EFM32GG11 Family Data Sheet
Electrical Specifications
Typ
Max
Unit
20.2
--
�s
26.4
--
�s
1.55
--
�s
68
--
pF
680
--
pF
1
--
k
326
--
nA
226
--
nA
33
--
nA
25
--
nA
690
--
nA
515
--
nA
79
--
nA
57
--
nA
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EFM32GG11 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Supply current, continuous ICSEN_ACTIVE
SAR or Delta Modulation conver-
--
conversions, WARMUP-
sions of 33 pF capacitor,
MODE=KEEPCSENWARM
CS0CG=0 (Gain = 10x), always
on
90.5
--
�A
HFPERCLK supply current ICSEN_HFPERCLK Current contribution from
--
HFPERCLK when clock to CSEN
block is enabled.
2.25
--
�A/MHz
Note:
1. Current is specified with a total external capacitance of 33 pF per channel. Average current is dependent on how long the module is actively sampling channels within the scan period, and scales with the number of samples acquired. Supply current for a specific application can be estimated by multiplying the current per sample by the total number of samples per period (total_current = single_sample_current * (number_of_channels * accumulation)).
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EFM32GG11 Family Data Sheet
Electrical Specifications
4.1.19 Operational Amplifier (OPAMP)
Unless otherwise indicated, specified conditions are: Non-inverting input configuration, VDD = 3.3 V, DRIVESTRENGTH = 2, MAINOUTEN = 1, CLOAD = 75 pF with OUTSCALE = 0, or CLOAD = 37.5 pF with OUTSCALE = 1. Unit gain buffer and 3X-gain connection as specified in table footnotes8 1.
Table 4.27. Operational Amplifier (OPAMP)
Parameter
Symbol
Supply voltage (from AVDD) VOPA
Input voltage
VIN
Input impedance Output voltage Load capacitance2
Output impedance
RIN VOUT CLOAD
ROUT
Internal closed-loop gain
GCL
Active current4
IOPA
Test Condition
HCMDIS = 0, Rail-to-rail input range
HCMDIS = 1
HCMDIS = 0, Rail-to-rail input range
HCMDIS = 1
OUTSCALE = 0
OUTSCALE = 1
DRIVESTRENGTH = 2 or 3, 0.4 V VOUT VOPA - 0.4 V, -8 mA < IOUT < 8 mA, Buffer connection, Full supply range
DRIVESTRENGTH = 0 or 1, 0.4 V VOUT VOPA - 0.4 V, -400 �A < IOUT < 400 �A, Buffer connection, Full supply range
DRIVESTRENGTH = 2 or 3, 0.1 V VOUT VOPA - 0.1 V, -2 mA < IOUT < 2 mA, Buffer connection, Full supply range
DRIVESTRENGTH = 0 or 1, 0.1 V VOUT VOPA - 0.1 V, -100 �A < IOUT < 100 �A, Buffer connection, Full supply range
Buffer connection
3x Gain connection
16x Gain connection
DRIVESTRENGTH = 3, OUTSCALE = 0
DRIVESTRENGTH = 2, OUTSCALE = 0
DRIVESTRENGTH = 1, OUTSCALE = 0
DRIVESTRENGTH = 0, OUTSCALE = 0
Min 2
1.62 VVSS VVSS 100 VVSS
-- -- --
--
--
--
0.99 2.93 15.07 -- -- -- --
Typ --
-- --
-- -- -- -- -- 0.25
Max
Unit
3.8
V
3.8
V
VOPA
V
VOPA-1.2
V
--
M
VOPA
V
75
pF
37.5
pF
--
0.6
--
0.4
--
1
--
1
1.01
-
2.99
3.05
-
15.7
16.33
-
580
--
�A
176
--
�A
13
--
�A
4.7
--
�A
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Parameter Open-loop gain
Symbol GOL
Loop unit-gain frequency7 UGF
Phase margin
PM
Output voltage noise
NOUT
Test Condition
Min
DRIVESTRENGTH = 3
--
DRIVESTRENGTH = 2
--
DRIVESTRENGTH = 1
--
DRIVESTRENGTH = 0
--
DRIVESTRENGTH = 3, Buffer
--
connection
DRIVESTRENGTH = 2, Buffer
--
connection
DRIVESTRENGTH = 1, Buffer
--
connection
DRIVESTRENGTH = 0, Buffer
--
connection
DRIVESTRENGTH = 3, 3x Gain
--
connection
DRIVESTRENGTH = 2, 3x Gain
--
connection
DRIVESTRENGTH = 1, 3x Gain
--
connection
DRIVESTRENGTH = 0, 3x Gain
--
connection
DRIVESTRENGTH = 3, Buffer
--
connection
DRIVESTRENGTH = 2, Buffer
--
connection
DRIVESTRENGTH = 1, Buffer
--
connection
DRIVESTRENGTH = 0, Buffer
--
connection
DRIVESTRENGTH = 3, Buffer
--
connection, 10 Hz - 10 MHz
DRIVESTRENGTH = 2, Buffer
--
connection, 10 Hz - 10 MHz
DRIVESTRENGTH = 1, Buffer
--
connection, 10 Hz - 1 MHz
DRIVESTRENGTH = 0, Buffer
--
connection, 10 Hz - 1 MHz
DRIVESTRENGTH = 3, 3x Gain
--
connection, 10 Hz - 10 MHz
DRIVESTRENGTH = 2, 3x Gain
--
connection, 10 Hz - 10 MHz
DRIVESTRENGTH = 1, 3x Gain
--
connection, 10 Hz - 1 MHz
DRIVESTRENGTH = 0, 3x Gain
--
connection, 10 Hz - 1 MHz
EFM32GG11 Family Data Sheet
Electrical Specifications
Typ
Max
Unit
135
--
dB
137
--
dB
121
--
dB
109
--
dB
3.38
--
MHz
0.9
--
MHz
132
--
kHz
34
--
kHz
2.57
--
MHz
0.71
--
MHz
113
--
kHz
28
--
kHz
67
--
�
69
--
�
63
--
�
68
--
�
146
--
�Vrms
163
--
�Vrms
170
--
�Vrms
176
--
�Vrms
313
--
�Vrms
271
--
�Vrms
247
--
�Vrms
245
--
�Vrms
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Parameter Slew rate5
Symbol SR
Startup time6 Input offset voltage
TSTART VOSI
DC power supply rejection ratio9
PSRRDC
DC common-mode rejection CMRRDC ratio9
Total harmonic distortion
THDOPA
Test Condition
Min
DRIVESTRENGTH = 3,
--
INCBW=13
DRIVESTRENGTH = 3,
--
INCBW=0
DRIVESTRENGTH = 2,
--
INCBW=13
DRIVESTRENGTH = 2,
--
INCBW=0
DRIVESTRENGTH = 1,
--
INCBW=13
DRIVESTRENGTH = 1,
--
INCBW=0
DRIVESTRENGTH = 0,
--
INCBW=13
DRIVESTRENGTH = 0,
--
INCBW=0
DRIVESTRENGTH = 2
--
DRIVESTRENGTH = 2 or 3, T =
-3
25 �C
DRIVESTRENGTH = 1 or 0, T =
-3
25 �C
DRIVESTRENGTH = 2 or 3,
-12
across operating temperature
range
DRIVESTRENGTH = 1 or 0,
-30
across operating temperature
range
Input referred
--
Input referred
--
DRIVESTRENGTH = 2, 3x Gain
--
connection, 1 kHz, VOUT = 0.1 V
to VOPA - 0.1 V
DRIVESTRENGTH = 0, 3x Gain
--
connection, 0.1 kHz, VOUT = 0.1 V
to VOPA - 0.1 V
EFM32GG11 Family Data Sheet
Electrical Specifications
Typ
Max
Unit
4.7
--
V/�s
1.5
--
V/�s
1.27
--
V/�s
0.42
--
V/�s
0.17
--
V/�s
0.058
--
V/�s
0.044
--
V/�s
0.015
--
V/�s
--
12
�s
--
3
mV
--
3
mV
--
12
mV
--
30
mV
70
--
dB
70
--
dB
90
--
dB
90
--
dB
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EFM32GG11 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Note:
1. Specified configuration for 3X-Gain configuration is: INCBW = 1, HCMDIS = 1, RESINSEL = VSS, VINPUT = 0.5 V, VOUTPUT = 1.5 V. Nominal voltage gain is 3.
2. If the maximum CLOAD is exceeded, an isolation resistor is required for stability. See AN0038 for more information.
3. When INCBW is set to 1 the OPAMP bandwidth is increased. This is allowed only when the non-inverting close-loop gain is 3, or the OPAMP may not be stable.
4. Current into the load resistor is excluded. When the OPAMP is connected with closed-loop gain > 1, there will be extra current to drive the resistor feedback network. The internal resistor feedback network has total resistance of 143.5 kOhm, which will cause another ~10 �A current when the OPAMP drives 1.5 V between output and ground.
5. Step between 0.2V and VOPA-0.2V, 10%-90% rising/falling range.
6. From enable to output settled. In sample-and-off mode, RC network after OPAMP will contribute extra delay. Settling error < 1mV.
7. In unit gain connection, UGF is the gain-bandwidth product of the OPAMP. In 3x Gain connection, UGF is the gain-bandwidth product of the OPAMP and 1/3 attenuation of the feedback network.
8. Specified configuration for Unit gain buffer configuration is: INCBW = 0, HCMDIS = 0, RESINSEL = DISABLE. VINPUT = 0.5 V, VOUTPUT = 0.5 V.
9. When HCMDIS=1 and input common mode transitions the region from VOPA-1.4V to VOPA-1V, input offset will change. PSRR and CMRR specifications do not apply to this transition region.
4.1.20 LCD Driver
Table 4.28. LCD Driver
Parameter
Symbol
Test Condition
Min
Typ
Max
Frame rate
fLCDFR
30
--
100
LCD supply range2
VLCDIN
1.8
--
3.8
LCD output voltage range VLCD
Current source mode, No external
2.0
LCD capacitor
--
VLCDIN-0.4
Step-down mode with external
2.0
LCD capacitor
--
VLCDIN
Charge pump mode with external
2.0
LCD capacitor
--
1.9 *
VLCDIN
Contrast control step size
STEPCONTRAST Current source mode
--
64
--
Charge pump or Step-down mode
--
43
--
Contrast control step accura- ACCCONTRAST cy1
--
+/-4
--
Note: 1. Step size accuracy is measured relative to the typical step size, and typ value represents one standard deviation. 2. VLCDIN is selectable between the AVDD or DVDD supply pins, depending on EMU_PWRCTRL_ANASW.
Unit Hz V V
V
V
mV mV %
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4.1.21 Pulse Counter (PCNT)
EFM32GG11 Family Data Sheet
Electrical Specifications
Parameter Input frequency
Symbol FIN
4.1.22 Analog Port (APORT)
Table 4.29. Pulse Counter (PCNT)
Test Condition
Min
Typ
Max
Unit
Asynchronous Single and Quad-
--
--
20
MHz
rature Modes
Sampled Modes with Debounce
--
--
filter set to 0.
8
kHz
Table 4.30. Analog Port (APORT)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Supply current2 1
IAPORT
Operation in EM0/EM1 Operation in EM2/EM3
--
7
--
�A
--
63
--
nA
Note:
1. Specified current is for continuous APORT operation. In applications where the APORT is not requested continuously (e.g. periodic ACMP requests from LESENSE in EM2), the average current requirements can be estimated by mutiplying the duty cycle of the requests by the specified continuous current number.
2. Supply current increase that occurs when an analog peripheral requests access to APORT. This current is not included in reported module currents. Additional peripherals requesting access to APORT do not incur further current.
4.1.23 I2C
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4.1.23.1 I2C Standard-mode (Sm)1
EFM32GG11 Family Data Sheet
Electrical Specifications
Table 4.31. I2C Standard-mode (Sm)1
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCL clock frequency2
fSCL
0
--
100
kHz
SCL clock low time
tLOW
4.7
--
--
�s
SCL clock high time
tHIGH
4
--
--
�s
SDA set-up time
tSU_DAT
250
--
--
ns
SDA hold time3
tHD_DAT
100
--
3450
ns
Repeated START condition tSU_STA set-up time
4.7
--
--
�s
(Repeated) START condition tHD_STA hold time
4
--
--
�s
STOP condition set-up time tSU_STO
4
--
--
�s
Bus free time between a
tBUF
STOP and START condition
4.7
--
--
�s
Note: 1. For CLHR set to 0 in the I2Cn_CTRL register. 2. For the minimum HFPERCLK frequency required in Standard-mode, refer to the I2C chapter in the reference manual. 3. The maximum SDA hold time (tHD_DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).
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4.1.23.2 I2C Fast-mode (Fm)1
EFM32GG11 Family Data Sheet
Electrical Specifications
Table 4.32. I2C Fast-mode (Fm)1
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCL clock frequency2
fSCL
0
--
400
kHz
SCL clock low time
tLOW
1.3
--
--
�s
SCL clock high time
tHIGH
0.6
--
--
�s
SDA set-up time
tSU_DAT
100
--
--
ns
SDA hold time3
tHD_DAT
100
--
900
ns
Repeated START condition tSU_STA set-up time
0.6
--
--
�s
(Repeated) START condition tHD_STA hold time
0.6
--
--
�s
STOP condition set-up time tSU_STO
0.6
--
--
�s
Bus free time between a
tBUF
STOP and START condition
1.3
--
--
�s
Note: 1. For CLHR set to 1 in the I2Cn_CTRL register. 2. For the minimum HFPERCLK frequency required in Fast-mode, refer to the I2C chapter in the reference manual. 3. The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).
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4.1.23.3 I2C Fast-mode Plus (Fm+)1
EFM32GG11 Family Data Sheet
Electrical Specifications
Table 4.33. I2C Fast-mode Plus (Fm+)1
Parameter
Symbol
Test Condition
Min
Typ
Max
SCL clock frequency2
fSCL
0
--
1000
SCL clock low time
tLOW
0.5
--
--
SCL clock high time
tHIGH
0.26
--
--
SDA set-up time
tSU_DAT
50
--
--
SDA hold time
tHD_DAT
100
--
--
Repeated START condition tSU_STA set-up time
0.26
--
--
(Repeated) START condition tHD_STA hold time
0.26
--
--
STOP condition set-up time tSU_STO
0.26
--
--
Bus free time between a
tBUF
STOP and START condition
0.5
--
--
Note: 1. For CLHR set to 0 or 1 in the I2Cn_CTRL register. 2. For the minimum HFPERCLK frequency required in Fast-mode Plus, refer to the I2C chapter in the reference manual.
Unit kHz �s �s ns ns �s
�s
�s �s
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4.1.24 USART SPI SPI Master Timing
EFM32GG11 Family Data Sheet
Electrical Specifications
Parameter SCLK period 1 3 2
Symbol tSCLK
CS to MOSI 1 3
tCS_MO
SCLK to MOSI 1 3
tSCLK_MO
MISO setup time 1 3
tSU_MI
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Table 4.34. SPI Master Timing
Test Condition
Min
Typ
All USARTs except USART2
2 *
--
tHFPERCLK
USART2
2 *
--
tHFPERBCLK
USART2, location 4, IOVDD = 1.8
-3.2
--
V
USART2, location 4, IOVDD = 3.0
-2.3
--
V
USART2, location 5, IOVDD = 1.8
-8.1
--
V
USART2, location 5, IOVDD = 3.0
-7.3
--
V
All other USARTs and locations,
-15
--
IOVDD = 1.8 V
All other USARTs and locations,
-13
--
IOVDD = 3.0 V
USART2, location 4, IOVDD = 1.8
-0.3
--
V
USART2, location 4, IOVDD = 3.0
-0.3
--
V
USART2, location 5, IOVDD = 1.8
-3.6
--
V
USART2, location 5, IOVDD = 3.0
-3.4
--
V
All other USARTs and locations,
-10
--
IOVDD = 1.8 V
All other USARTs and locations,
-9
--
IOVDD = 3.0 V
USART2, location 4, IOVDD = 1.8
39.7
--
V
USART2, location 4, IOVDD = 3.0
22.4
--
V
USART2, location 5, IOVDD = 1.8
49.2
--
V
USART2, location 5, IOVDD = 3.0
30.0
--
V
All other USARTs and locations,
55
--
IOVDD = 1.8 V
All other USARTs and locations,
36
--
IOVDD = 3.0 V
Max
Unit
--
ns
--
ns
6.8
ns
6.0
ns
6.3
ns
4.4
ns
13
ns
11
ns
9.2
ns
8.6
ns
5.0
ns
3.2
ns
11
ns
11
ns
--
ns
--
ns
--
ns
--
ns
--
ns
--
ns
Rev. 1.0 | 75
EFM32GG11 Family Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
MISO hold time 1 3
tH_MI
USART2, location 4, IOVDD = 1.8 -11.6
--
V
USART2, location 4, IOVDD = 3.0 -11.6
--
V
USART2, location 5, IOVDD = 1.8
-9.1
--
V
USART2, location 5, IOVDD = 3.0
-9.1
--
V
All other USARTs and locations,
-8
--
IOVDD = 1.8 V
All other USARTs and locations,
-8
--
IOVDD = 3.0 V
Note: 1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0). 2. tHFPERCLK is one period of the selected HFPERCLK. 3. Measurement done with 8 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD).
Max
Unit
--
ns
--
ns
--
ns
--
ns
--
ns
--
ns
CS
SCLK
CLKPOL = 0
SCLK
CLKPOL = 1
MOSI
MISO
tCS_MO
tSCKL_MO tSCLK
tSU_MI
tH_MI
Figure 4.1. SPI Master Timing Diagram
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SPI Slave Timing
EFM32GG11 Family Data Sheet
Electrical Specifications
Table 4.35. SPI Slave Timing
Parameter
Symbol
Test Condition
Min
Typ
SCLK period 1 3 2
tSCLK
6 *
--
tHFPERCLK
SCLK high time1 3 2
tSCLK_HI
2.5 *
--
tHFPERCLK
SCLK low time1 3 2
tSCLK_LO
2.5 *
--
tHFPERCLK
CS active to MISO 1 3
tCS_ACT_MI
24
--
CS disable to MISO 1 3
tCS_DIS_MI
19
--
MOSI setup time 1 3
tSU_MO
7
--
MOSI hold time 1 3 2
tH_MO
6
--
SCLK to MISO 1 3 2
tSCLK_MI
16 + 1.5 *
--
tHFPERCLK
Note: 1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0). 2. tHFPERCLK is one period of the selected HFPERCLK. 3. Measurement done with 8 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD).
Max
Unit
--
ns
--
ns
--
ns
69
ns
175
ns
--
ns
--
ns
43 + 2.5 *
ns
tHFPERCLK
CS
SCLK
CLKPOL = 0
SCLK
CLKPOL = 1
MOSI
MISO
tCS_ACT_MI
tSU_MO
tH_MO
tSCLK_HI
tSCLK_LO
tSCLK
tSCLK_MI
Figure 4.2. SPI Slave Timing Diagram
tCS_DIS_MI
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4.1.25 External Bus Interface (EBI)
EFM32GG11 Family Data Sheet
Electrical Specifications
EBI Write Enable Output Timing
Timing applies to both EBI_WEn and EBI_NANDWEn for all addressing modes and both polarities. All numbers are based on route locations 0,1,2 only (with all EBI alternate functions using the same location at the same time). Timing is specified at 10% and 90% of IOVDD, 25 pF external loading, and slew rate for all GPIO set to 6.
Table 4.36. EBI Write Enable Timing
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output hold time, from trailing EBI_WEn / EBI_NANDWEn edge to EBI_AD, EBI_A, EBI_CSn, EBI_BLn invalid
tOH_WEn
IOVDD 1.62 V IOVDD 3.0 V
-22 +
--
(WRHOLD
* t{}HFCOR-
ECLK{})
-13 +
--
(WRHOLD
* tHFCOR-
ECLK)
--
ns
--
ns
Output setup time, from EBI_AD, EBI_A, EBI_CSn, EBI_BLn valid to leading EBI_WEn / EBI_NANDWEn edge1
tOSU_WEn
IOVDD 1.62 V
-12 +
--
(WRSET-
UP *
tHFCOR-
ECLK)
--
ns
IOVDD 3.0 V
-10 +
--
(WRSET-
UP *
tHFCOR-
ECLK)
--
ns
EBI_WEn / EBI_NANDWEn tWIDTH_WEn pulse width1
IOVDD 1.62 V
-6 +
--
(MAX(1,
WRSTRB)
* tHFCOR-
ECLK)
--
ns
IOVDD 3.0 V
-5 +
--
(MAX(1,
WRSTRB)
* tHFCOR-
ECLK)
--
ns
Note:
1. The figure shows the timing for the case that the half strobe length functionality is not used, i.e. HALFWE=0. The leading edge of EBI_WEn can be moved to the right by setting HALFWE=1. This decreases the length of tWIDTH_WEn and increases the length of tOSU_WEn by 1/2 * tHFCLKNODIV.
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EFM32GG11 Family Data Sheet
Electrical Specifications
EBI_BL[N-1:0] EBI_A[N-1:0] EBI_AD[15:0] EBI_CSn EBI_WEn
WRSETUP (0, 1, 2, ...)
WRSTRB (1, 2, 3, ...)
WRHOLD (0, 1, 2, ...)
EBI_BL tOSU_WEn
EBI_A tOSU_WEn
Z tOH_WEn
Z tOH_WEn
DATA[15:0] tOSU_WEn
Z tOH_WEn
tOSU_WEn
tWIDTH_WEn
tOH_WEn
Figure 4.3. EBI Write Enable Output Timing Diagram
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EFM32GG11 Family Data Sheet
Electrical Specifications
EBI Address Latch Enable Output Timing
Timing applies to multiplexed addressing modes D8A24ALE and D16A16ALE for both polarities. All numbers are based on route locations 0,1,2 only (with all EBI alternate functions using the same location at the same time). Timing is specified at 10% and 90% of IOVDD, 25 pF external loading, and slew rate for all GPIO set to 6.
Table 4.37. EBI Address Latch Enable Output Timing
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output hold time, from trailing EBI_ALE edge to EBI_AD invalid1 2
tOH_ALEn
IOVDD 1.62 V
-22 +
--
(ADDR-
HOLD *
tHFCOR-
ECLK)
--
ns
IOVDD 3.0 V
-11 +
--
(ADDR-
HOLD *
tHFCOR-
ECLK)
--
ns
Output setup time, from EBI_AD valid to leading EBI_ALE edge
tOSU_ALEn
IOVDD 1.62 V IOVDD 3.0 V
-12
--
-9
--
--
ns
--
ns
EBI_ALEn pulse width1
tWIDTH_ALEn
IOVDD 1.62 V
-4 +
--
((ADDR-
SETUP +
1) *
t{}HFCOR-
ECLK{})
--
ns
IOVDD 3.0 V
-3 +
--
((ADDR-
SETUP +
1) *
t{}HFCOR-
ECLK{})
--
ns
Note:
1. The figure shows the timing for the case that the half strobe length functionality is not used, i.e. HALFALE=0. The trailing edge of EBI_ALEn can be moved to the left by setting HALFALE=1. This decreases the length of tWIDTH_ALEn and increases the length of tOSU_ALEn by tHFCORECLK - 1/2 * tHFCLKNODIV.
2. The figure shows a write operation. For a multiplexed read operation the address hold time is controlled via the RDSETUP state instead of via the ADDRHOLD state.
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EFM32GG11 Family Data Sheet
Electrical Specifications
EBI_AD[15:0] EBI_ALE EBI_CSn EBI_WEn
ADDRSETUP (1, 2, 3, ...)
ADDR[16:1]
tWIDTH_ALEn tOSU_ALEn
ADDRHOLD (0, 1, 2, ...)
tWIDTH_ALEn
WRSETUP (0, 1, 2, ...)
WRSTRB (1, 2, 3, ...)
DATA[15:0]
WRHOLD (0, 1, 2, ...)
Z
Figure 4.4. EBI Address Latch Enable Output Timing Diagram
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EFM32GG11 Family Data Sheet
Electrical Specifications
EBI Read Enable Output Timing
Timing applies to both EBI_REn and EBI_NANDREn for all addressing modes and both polarities. Output timing for EBI_AD applies only to multiplexed addressing modes D8A24ALE and D16A16ALE. All numbers are based on route locations 0,1,2 only (with all EBI alternate functions using the same location at the same time). Timing is specified at 10% and 90% of IOVDD, 25 pF external loading, and slew rate for all GPIO set to 6.
Table 4.38. EBI Read Enable Output Timing
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output hold time, from trailing EBI_REn / EBI_NANDREn edge to EBI_AD, EBI_A, EBI_CSn, EBI_BLn invalid
tOH_REn
IOVDD 1.62 V IOVDD 3.0 V
-23 +
--
(RDHOLD *
tHFCOR-
ECLK)
-13 +
--
(RDHOLD *
tHFCOR-
ECLK)
--
ns
--
ns
Output setup time, from EBI_AD, EBI_A, EBI_CSn, EBI_BLn valid to leading EBI_REn / EBI_NANDREn edge 1
tOSU_REn
IOVDD 1.62 V IOVDD 3.0 V
-12 +
--
(RDSETUP
* tHFCOR-
ECLK)
-11 +
--
(RDSETUP
* tHFCOR-
ECLK)
--
ns
--
ns
EBI_REn pulse width1 2
tWIDTH_REn
IOVDD 1.62 V
-6 +
--
(MAX(1,
RDSTRB) *
tHFCOR-
ECLK)
--
ns
IOVDD 3.0 V
-4 +
--
(MAX(1,
RDSTRB) *
tHFCOR-
ECLK)
--
ns
Note:
1. The figure shows the timing for the case that the half strobe length functionality is not used, i.e. HALFRE=0. The leading edge of EBI_REn can be moved to the right by setting HALFRE=1. This decreases the length of tWIDTH_REn and increases the length of tOSU_REn by 1/2 * tHFCLKNODIV.
2. When page mode is used, RDSTRB is replaced by RDPA for page hits.
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EFM32GG11 Family Data Sheet
Electrical Specifications
EBI_BL[1:0] EBI_A[27:0] EBI_AD[15:8]
EBI_CSn EBI_AD[7:0]
EBI_REn
RDSETUP (0, 1, 2, ...)
RDSTRB (1, 2, 3, ...)
RDHOLD (0, 1, 2, ...)
EBI_BL tSU_REn
Z tH_REn
EBI_A tSU_REn
Z tH_REn
ADDR[7:0] tSU_REn
Z tH_REn
tSU_REn Z
DATA[7:0]
tH_REn Z
tWIDTH_REn
Figure 4.5. EBI Read Enable Output Timing Diagram
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EFM32GG11 Family Data Sheet
Electrical Specifications
EBI TFT Output Timing All numbers are based on route locations 0,1,2 only (with all EBI alternate functions using the same location at the same time). Timing is specified at 10% and 90% of IOVDD, 25 pF external loading, and slew rate for all GPIO set to 6.
Table 4.39. EBI TFT Output Timing
Parameter
Symbol
Output hold time, EBI_DCLK tOH_DCLK to EBI_AD invalid
Test Condition IOVDD 1.62 V
IOVDD 3.0 V
Output setup time, EBI_AD tOSU_DCLK valid to EBI_DCLK
IOVDD 1.62 V
IOVDD 3.0 V
Min
Typ
-23 +
--
(TFTHOLD
* tHFCOR-
ECLK)
-12 +
--
(TFTHOLD
* tHFCOR-
ECLK)
-11 +
--
(TFTSET-
UP *
tHFCOR-
ECLK)
-9 +
--
(TFTSET-
UP *
tHFCOR-
ECLK)
Max
Unit
--
ns
--
ns
--
ns
--
ns
EBI_DCLK EBI_AD
tOSU_DCLK DATA[15:0]
tOH_DCLK DATA[15:0]
DATA[15:0]
Figure 4.6. EBI TFT Output Timing
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EFM32GG11 Family Data Sheet
Electrical Specifications
EBI Read Enable Timing Requirements
Timing applies to both EBI_REn and EBI_NANDREn for all addressing modes and both polarities. All numbers are based on route locations 0,1,2 only (with all EBI alternate functions using the same location at the same time). Timing is specified at 10% and 90% of IOVDD, 25 pF external loading, and slew rate for all GPIO set to 6.
Table 4.40. EBI Read Enable Timing Requirements
Parameter
Symbol
Setup time, from EBI_AD valid to trailing EBI_REn edge
tSU_REn
Hold time, from trailing
tH_REn
EBI_REn edge to EBI_AD in-
valid
Test Condition IOVDD 1.62 V IOVDD 3.0 V IOVDD 1.62 V
Min
Typ
Max
Unit
55
--
--
ns
36
--
--
ns
-9
--
--
ns
EBI_A[N-1:0] EBI_AD[15:0]
EBI_CSn EBI_REn
RDSETUP (0, 1, 2, ...)
RDSTRB (1, 2, 3, ...)
RDHOLD (0, 1, 2, ...)
ADDR[N:1]
Z
Z
DATA[15:0]
Z
tSU_REn
tH_REn
Figure 4.7. EBI Read Enable Timing Requirements
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EFM32GG11 Family Data Sheet
Electrical Specifications
EBI Ready/Wait Timing Requirements
Timing applies to both EBI_REn and EBI_WEn for all addressing modes and both polarities. All numbers are based on route locations 0,1,2 only (with all EBI alternate functions using the same location at the same time). Timing is specified at 10% and 90% of IOVDD, 25 pF external loading, and slew rate for all GPIO set to 6.
Table 4.41. EBI Ready/Wait Timing Requirements
Parameter
Symbol
Setup time, from EBI_ARDY tSU_ARDY valid to trailing EBI_REn, EBI_WEn edge
Hold time, from trailing
tH_ARDY
EBI_REn, EBI_WEn edge to
EBI_ARDY invalid
Test Condition IOVDD 1.62 V
IOVDD 3.0 V
IOVDD 1.62 V
Min
Typ
55 + (3 *
--
tHFCOR-
ECLK)
36 + (3 *
--
tHFCOR-
ECLK)
-9
--
Max
Unit
--
ns
--
ns
--
ns
EBI_RDY EBI_AD[15:0]
EBI_CSn EBI_REn
RDSETUP (0, 1, 2, ...)
RDSTRB (1, 2, 3, ...)
Z
SYNC (3)
RDHOLD (0, 1, 2, ...)
DATA[15:0]
tSU_ARDY
tH_ARDY
Figure 4.8. EBI Ready/Wait Timing Requirements
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4.1.26 Ethernet (ETH)
EFM32GG11 Family Data Sheet
Electrical Specifications
MII Transmit Timing Timing is specified with 3.0 V IOVDD 3.8 V, 25 pF external loading, and slew rate for all GPIO set to 6 unless otherwise indicated.
Table 4.42. Ethernet MII Transmit Timing
Parameter TX_CLK frequency
TX_CLK duty cycle
Output delay, TX_CLK to TXD[3:0], TX_EN, TX_ER
Symbol FTX_CLK DCTX_CLK tOUT
Test Condition Output slew rate set to 7
Min
Typ
Max
Unit
--
25
--
MHz
35
--
65
%
0
--
25
ns
TX_CLK
TXD[3:0], TX_EN, TX_ER
tOUT
Figure 4.9. Ethernet MII Transmit Timing
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EFM32GG11 Family Data Sheet
Electrical Specifications
MII Receive Timing Timing is specified with 3.0 V IOVDD 3.8 V, 25 pF external loading, and slew rate for all GPIO set to 6 unless otherwise indicated.
Table 4.43. Ethernet MII Receive Timing
Parameter
RX_CLK frequency
RX_CLK duty cycle
Setup time, RXD[3:0], RX_DV, RX_ER valid to RX_CLK
Hold time, RX_CLK to RXD[3:0], RX_DV, RX_ER change
Symbol FRX_CLK DCRX_CLK tSU
tHD
Test Condition
Min
Typ
Max
Unit
--
25
--
MHz
35
--
65
%
6
--
--
ns
5
--
--
ns
RX_CLK
RXD[3:0], RX_DV, RX_ER
tSU
tHD
Figure 4.10. Ethernet MII Receive Timing
RMII Transmit Timing Timing is specified with 3.0 V IOVDD 3.8 V, 25 pF external loading, and slew rate for all GPIO set to 6 unless otherwise indicated.
Table 4.44. Ethernet RMII Transmit Timing
Parameter REF_CLK frequency
REF_CLK duty cycle
Output delay, REF_CLK to TXD[1:0], TX_EN
Symbol FREF_CLK DCREF_CLK tOUT
Test Condition Output slew rate set to 7
Min
Typ
Max
Unit
--
50
--
MHz
35
--
65
%
2.3
--
14.1
ns
REF_CLK TXD[1:0], TX_EN
tOUT
Figure 4.11. Ethernet RMII Transmit Timing silabs.com | Building a more connected world.
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EFM32GG11 Family Data Sheet
Electrical Specifications
RMII Receive Timing Timing is specified with 3.0 V IOVDD 3.8 V, 25 pF external loading, and slew rate for all GPIO set to 6 unless otherwise indicated.
Table 4.45. Ethernet RMII Receive Timing
Parameter
Symbol
REF_CLK frequency
FREF_CLK
REF_CLK duty cycle
DCREF_CLK
Setup time, RXD[1:0],
tSU
CRS_DV, RX_ER valid to
REF_CLK
Hold time, REF_CLK to
tHD
RXD[1:0], CRS_DV, RX_ER
change
Test Condition Output slew rate set to 7
Min
Typ
Max
Unit
--
50
--
MHz
35
--
65
%
4
--
--
ns
2
--
--
ns
REF_CLK
RXD[1:0], CRS_DV, RX_ER
tSU
tHD
Figure 4.12. Ethernet RMII Receive Timing
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4.1.27 Serial Data I/O Host Controller (SDIO)
EFM32GG11 Family Data Sheet
Electrical Specifications
SDIO DS Mode Timing
Timing is specified at 3.0 V IOVDD with voltage scaling disabled. Slew rate for SD_CLK set to 6, all other GPIO set to 6, DRIVESTRENGTH = STRONG for all pins. SDIO_CTRL_TXDLYMUXSEL = 1. Loading between 5 and 10 pF on all pins or between 10 and 40 pF on all pins.
Table 4.46. SDIO DS Mode Timing (Location 0)
Parameter
Symbol
Clock frequency during data FSD_CLK transfer
Clock low time
tWL
Clock high time
tWH
Clock rise time
tR
Clock fall time
tF
Input setup time, CMD,
tISU
DAT[0:3] valid to SD_CLK
Input hold time, SD_CLK to tIH CMD, DAT[0:3] change
Output delay time, SD_CLK tODLY to CMD, DAT[0:3] valid
Output hold time, SD_CLK to tOH CMD, DAT[0:3] change
Test Condition
Min
Typ
Max
Unit
Using HFRCO, AUXHFRCO, or
--
--
23
MHz
USHFRCO
Using HFXO
--
--
20.5
MHz
Using HFRCO, AUXHFRCO, or
19.6
--
USHFRCO
Using HFXO
19.1
--
Using HFRCO, AUXHFRCO, or
19.6
--
USHFRCO
--
ns
--
ns
--
ns
Using HFXO
19.1
--
--
ns
1.4
--
4.9
ns
1.2
--
4.0
ns
7
--
--
ns
0
--
--
ns
--
--
18.6
ns
5
--
--
ns
Table 4.47. SDIO DS Mode Timing (Location 1)
Parameter
Symbol
Clock frequency during data FSD_CLK transfer
Clock low time
tWL
Clock high time
tWH
Clock rise time
tR
Clock fall time
tF
Test Condition
Min
Typ
Max
Unit
Using HFRCO, AUXHFRCO, or
--
--
14
MHz
USHFRCO
Using HFXO
--
--
13.5
MHz
Using HFRCO, AUXHFRCO, or
32.3
--
USHFRCO
--
ns
Using HFXO
29.2
--
--
ns
Using HFRCO, AUXHFRCO, or
32.3
--
USHFRCO
--
ns
Using HFXO
29.2
--
--
ns
1.4
--
4.9
ns
1.2
--
4.0
ns
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Parameter
Symbol
Input setup time, CMD,
tISU
DAT[0:3] valid to SD_CLK
Input hold time, SD_CLK to tIH CMD, DAT[0:3] change
Output delay time, SD_CLK tODLY to CMD, DAT[0:3] valid
Output hold time, SD_CLK to tOH CMD, DAT[0:3] change
SD_CLK
CMD, DAT[0:3]
Test Condition
tWL
EFM32GG11 Family Data Sheet
Electrical Specifications
Min
Typ
Max
Unit
11.6
--
--
ns
0
--
--
ns
--
--
29.5
ns
5
--
--
ns
tWH
Not Valid
tISU
tIH
Valid
Input Timing
Not Valid
SD_CLK
CMD, DAT[0:3]
tODLY (max)
Not Valid
Valid
tOH (min) Not Valid
Output Timing
Figure 4.13. SDIO DS Mode Timing
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EFM32GG11 Family Data Sheet
Electrical Specifications
SDIO HS Mode Timing
Timing is specified at 3.0 V IOVDD with voltage scaling disabled. Slew rate for SD_CLK set to 7, all other GPIO set to 6, DRIVESTRENGTH = STRONG for all pins. SDIO_CTRL_TXDLYMUXSEL = 1. Loading between 5 and 10 pF on all pins or between 10 and 30 pF on all pins.
Table 4.48. SDIO HS Mode Timing (Location 0)
Parameter
Symbol
Clock frequency during data FSD_CLK transfer
Clock low time
tWL
Clock high time
tWH
Clock rise time
tR
Input setup time, CMD,
tISU
DAT[0:3] valid to SD_CLK
Input hold time, SD_CLK to tIH CMD, DAT[0:3] change
Output delay time, SD_CLK tODLY to CMD, DAT[0:3] valid
Output hold time, SD_CLK to tOH CMD, DAT[0:3] change
Test Condition
Min
Typ
Max
Unit
Using HFRCO, AUXHFRCO, or
--
--
46
MHz
USHFRCO
Using HFXO
--
--
46
MHz
Using HFRCO, AUXHFRCO, or
9.8
--
USHFRCO
--
ns
Using HFXO
8.2
--
--
ns
Using HFRCO, AUXHFRCO, or
9.8
--
USHFRCO
--
ns
Using HFXO
8.2
--
--
ns
0.8
--
3.0
ns
3.4
--
--
ns
2.5
--
--
ns
--
--
14.4
ns
2
--
--
ns
Table 4.49. SDIO HS Mode Timing (Location 1)
Parameter
Symbol
Clock frequency during data FSD_CLK transfer
Clock low time
tWL
Clock high time
tWH
Clock rise time
tR
Input setup time, CMD,
tISU
DAT[0:3] valid to SD_CLK
Input hold time, SD_CLK to tIH CMD, DAT[0:3] change
Test Condition
Min
Typ
Max
Unit
Using HFRCO, AUXHFRCO, or
--
--
30
MHz
USHFRCO
Using HFXO
--
--
30
MHz
Using HFRCO, AUXHFRCO, or
15
--
USHFRCO
Using HFXO
12.9
--
Using HFRCO, AUXHFRCO, or
15
--
USHFRCO
Using HFXO
12.9
--
--
ns
--
ns
--
ns
--
ns
0.8
--
3.0
ns
3.3
--
--
ns
2.5
--
--
ns
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Parameter
Symbol
Output delay time, SD_CLK tODLY to CMD, DAT[0:3] valid
Output hold time, SD_CLK to tOH CMD, DAT[0:3] change
SD_CLK
CMD, DAT[0:7]
SD_CLK
CMD, DAT[0:7]
Test Condition
tWL
EFM32GG11 Family Data Sheet
Electrical Specifications
Min
Typ
Max
Unit
--
--
22.9
ns
2
--
--
ns
tWH
Not Valid
tISU
tIH
Valid
Input Timing
Not Valid
tODLY (max) Not Valid
tOH (min)
Valid
Not Valid
Output Timing
Figure 4.14. SDIO HS Mode Timing
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EFM32GG11 Family Data Sheet
Electrical Specifications
SDIO SDR Mode Timing
Timing is specified at 1.62 V IOVDD with voltage scaling disabled. Slew rate for SD_CLK set to 7, all other GPIO set to 6, DRIVESTRENGTH = STRONG for all pins. SDIO_CTRL_TXDLYMUXSEL = 0. Loading between 5 and 10 pF on all pins or between 10 and 40 pF on all pins.
Table 4.50. SDIO SDR Mode Timing (Location 0)
Parameter
Symbol
Clock frequency during data FSD_CLK transfer
Clock low time
tWL
Clock high time
tWH
Clock rise time
tR
Input setup time, CMD,
tISU
DAT[0:3] valid to SD_CLK
Input hold time, SD_CLK to tIH CMD, DAT[0:3] change
Output delay time, SD_CLK tODLY to CMD, DAT[0:3] valid
Output hold time, SD_CLK to tOH CMD, DAT[0:3] change
Test Condition
Min
Typ
Max
Unit
Using HFRCO, AUXHFRCO, or
--
--
USHFRCO
Using HFXO
--
--
Using HFRCO, AUXHFRCO, or
17.3
--
USHFRCO
Using HFXO
14.9
--
26
MHz
26
MHz
--
ns
--
ns
Using HFRCO, AUXHFRCO, or
17.3
--
USHFRCO
--
ns
Using HFXO
14.9
--
--
ns
0.8
--
7.6
ns
5.1
--
--
ns
1.5
--
--
ns
--
--
19.5
ns
0.8
--
--
ns
Table 4.51. SDIO SDR Mode Timing (Location 1)
Parameter
Symbol
Clock frequency during data FSD_CLK transfer
Clock low time
tWL
Clock high time
tWH
Clock rise time
tR
Input setup time, CMD,
tISU
DAT[0:3] valid to SD_CLK
Input hold time, SD_CLK to tIH CMD, DAT[0:3] change
Test Condition
Min
Typ
Max
Unit
Using HFRCO, AUXHFRCO, or
--
--
23
MHz
USHFRCO
Using HFXO
--
--
23
MHz
Using HFRCO, AUXHFRCO, or
19.6
--
USHFRCO
Using HFXO
16.9
--
Using HFRCO, AUXHFRCO, or
19.6
--
USHFRCO
Using HFXO
16.9
--
--
ns
--
ns
--
ns
--
ns
0.8
--
7.6
ns
5.0
--
--
ns
1.5
--
--
ns
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Rev. 1.0 | 94
Parameter
Symbol
Output delay time, SD_CLK tODLY to CMD, DAT[0:3] valid
Output hold time, SD_CLK to tOH CMD, DAT[0:3] change
SD_CLK
CMD, DAT[0:7]
Test Condition
tWL
EFM32GG11 Family Data Sheet
Electrical Specifications
Min
Typ
Max
Unit
--
--
27.0
ns
0.8
--
--
ns
tWH
Not Valid
tISU
tIH
Valid
Input Timing
Not Valid
SD_CLK
CMD, DAT[0:7]
tODLY (max) Not Valid
tOH (min)
Valid
Not Valid
Output Timing
Figure 4.15. SDIO SDR Mode Timing
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EFM32GG11 Family Data Sheet
Electrical Specifications
SDIO DDR Mode Timing
Timing is specified at 1.62 V IOVDD with voltage scaling disabled. Slew rate for SD_CLK set to 6, all other GPIO set to 6, DRIVESTRENGTH = STRONG for all pins. SDIO_CTRL_TXDLYMUXSEL = 1. Loading between 5 and 10 pF on all pins or between 10 and 30 pF on all pins.
Table 4.52. SDIO DDR Mode Timing (Location 0)
Parameter
Symbol
Clock frequency during data FSD_CLK transfer
Clock low time
tWL
Clock high time
tWH
Clock rise time
tR
Clock fall time
tF
Input setup time, CMD valid tISU to SD_CLK
Input hold time, SD_CLK to tIH CMD change
Output delay time, SD_CLK tODLY to CMD valid
Output hold time, SD_CLK to tOH CMD change
Input setup time, DAT[0:3] valid to SD_CLK
tISU2X
Input hold time, SD_CLK to tIH2X DAT[0:3] change
Output delay time, SD_CLK tODLY2X to DAT[0:3] valid
Output hold time, SD_CLK to tOH2X DAT[0:3] change
Test Condition
Min
Typ
Max
Unit
Using HFRCO, AUXHFRCO, or
--
--
20
MHz
USHFRCO
Using HFXO
--
--
17.5
MHz
Using HFRCO, AUXHFRCO, or
22.6
--
USHFRCO
--
ns
Using HFXO
22.4
--
--
ns
Using HFRCO, AUXHFRCO, or
22.6
--
USHFRCO
--
ns
Using HFXO
22.4
--
--
ns
1.4
--
8.7
ns
1.2
--
6.4
ns
7.4
--
--
ns
1.5
--
--
ns
--
--
22.0
ns
2.0
--
--
ns
9.5
--
--
ns
1.5
--
--
ns
--
--
24.4
ns
2.0
--
--
ns
Table 4.53. SDIO DDR Mode Timing (Location 1)
Parameter
Symbol
Clock frequency during data FSD_CLK transfer
Clock low time
tWL
Test Condition
Min
Typ
Max
Unit
Using HFRCO, AUXHFRCO, or
--
USHFRCO
--
12.5
MHz
Using HFXO
--
--
12.5
MHz
Using HFRCO, AUXHFRCO, or
36.1
--
USHFRCO
--
ns
Using HFXO
31.6
--
--
ns
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Parameter Clock high time
Symbol tWH
Clock rise time
tR
Clock fall time
tF
Input setup time, CMD valid tISU to SD_CLK
Input hold time, SD_CLK to tIH CMD change
Output delay time, SD_CLK tODLY to CMD valid
Output hold time, SD_CLK to tOH CMD change
Input setup time, DAT[0:3] valid to SD_CLK
tISU2X
Input hold time, SD_CLK to tIH2X DAT[0:3] change
Output delay time, SD_CLK tODLY2X to DAT[0:3] valid
Output hold time, SD_CLK to tOH2X DAT[0:3] change
Test Condition
Min
Using HFRCO, AUXHFRCO, or
36.1
USHFRCO
Using HFXO
31.6
1.4
1.2
11.9
1.5
--
2.0
14.1
1.5
--
2.0
EFM32GG11 Family Data Sheet
Electrical Specifications
Typ
Max
Unit
--
--
ns
--
--
ns
--
8.7
ns
--
6.4
ns
--
--
ns
--
--
ns
--
29.6
ns
--
--
ns
--
--
ns
--
--
ns
--
36.2
ns
--
--
ns
SD_CLK
tWH
tWL
tISU2X tIH2X
tISU2X tIH2X
DAT[0:3]
xxxx Valid xxxx Valid xxxx Valid xxxx Valid
tISU
tIH
xxxx
CMD
Not Valid
Valid
Not Valid
Input Timing
SD_CLK
tWH
tWL
tODLY2X (max) tODLY2X (min)
tODLY2X (max) tODLY2X (min)
DAT[0:3]
xxxx
Valid xxxx Valid tODLY (max)
xxxx
Valid xxxx Valid tOH (min)
xxxx
CMD
Not Valid
Valid
Not Valid
Output Timing
Figure 4.16. SDIO DDR Mode Timing
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EFM32GG11 Family Data Sheet
Electrical Specifications
SDIO MMC Legacy Mode Timing Timing is specified with voltage scaling disabled. Slew rate for SD_CLK set to 7, all other GPIO set to 6, DRIVESTRENGTH = STRONG for all pins. SDIO_CTRL_TXDLYMUXSEL = 1. Loading between 5 and 10 pF on all pins or between 10 and 20 pF on all pins.
Table 4.54. SDIO MMC Legacy Mode Timing (Location 0)
Parameter
Symbol
Clock frequency during data FSD_CLK transfer
Clock low time
tWL
Clock high time
tWH
Clock rise time
tR
Input setup time, CMD,
tISU
DAT[0:7] valid to SD_CLK
Input hold time, SD_CLK to tIH CMD, DAT[0:7] change
Output delay time, SD_CLK tODLY to CMD, DAT[0:7] valid
Output hold time, SD_CLK to tOH CMD, DAT[0:7] change
Test Condition
Min
Typ
Max
Unit
Using HFRCO, AUXHFRCO, or
--
--
USHFRCO
Using HFXO
--
--
Using HFRCO, AUXHFRCO, or
17.3
--
USHFRCO
Using HFXO
14.9
--
26
MHz
26
MHz
--
ns
--
ns
Using HFRCO, AUXHFRCO, or
17.3
--
USHFRCO
--
ns
Using HFXO
14.9
--
--
ns
0.8
--
6.6
ns
5.1
--
--
ns
2.5
--
--
ns
--
--
17.7
ns
3
--
--
ns
Table 4.55. SDIO MMC Legacy Mode Timing (Location 1)
Parameter
Symbol
Clock frequency during data FSD_CLK transfer
Clock low time
tWL
Clock high time
tWH
Clock rise time
tR
Input setup time, CMD,
tISU
DAT[0:7] valid to SD_CLK
Input hold time, SD_CLK to tIH CMD, DAT[0:7] change
Output delay time, SD_CLK tODLY to CMD, DAT[0:7] valid
Test Condition
Min
Typ
Using HFRCO, AUXHFRCO, or
--
--
USHFRCO
Using HFXO
--
--
Using HFRCO, AUXHFRCO, or
19.6
--
USHFRCO
Using HFXO
16.9
--
Using HFRCO, AUXHFRCO, or
19.6
--
USHFRCO
Using HFXO
16.9
--
0.8
--
6.1
--
2.5
--
--
--
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Max
Unit
23
MHz
23
MHz
--
ns
--
ns
--
ns
--
ns
6.6
ns
--
ns
--
ns
29.7
ns
Rev. 1.0 | 98
Parameter
Symbol
Output hold time, SD_CLK to tOH CMD, DAT[0:7] change
SD_CLK
CMD, DAT[0:7]
Test Condition
tWL
EFM32GG11 Family Data Sheet
Electrical Specifications
Min
Typ
Max
Unit
3
--
--
ns
tWH
Not Valid
tISU
tIH
Valid
Input Timing
Not Valid
SD_CLK
CMD, DAT[0:7]
tODLY (max) Not Valid
tOH (min)
Valid
Not Valid
Output Timing
Figure 4.17. SDIO MMC Legacy Mode Timing
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EFM32GG11 Family Data Sheet
Electrical Specifications
SDIO MMC SDR Mode Timing at 1.8 V
Timing is specified at 1.62 V IOVDD with voltage scaling disabled. Slew rate for SD_CLK set to 7, all other GPIO set to 6, DRIVESTRENGTH = STRONG for all pins. SDIO_CTRL_TXDLYMUXSEL = 1. Loading between 5 and 10 pF, between 10 and 20 pF, or between 20 and 30 pF on all pins.
Table 4.56. SDIO MMC SDR Mode Timing (Location 0, 1.62 V I/O)
Parameter
Symbol
Clock frequency during data FSD_CLK transfer
Clock low time
tWL
Clock high time
tWH
Clock rise time
tR
Input setup time, CMD,
tISU
DAT[0:7] valid to SD_CLK
Input hold time, SD_CLK to tIH CMD, DAT[0:7] change
Output delay time, SD_CLK tODLY to CMD, DAT[0:7] valid
Output hold time, SD_CLK to tOH CMD, DAT[0:7] change
Test Condition
Min
Typ
Max
Unit
Using HFRCO, AUXHFRCO, or
--
--
USHFRCO
Using HFXO
--
--
Using HFRCO, AUXHFRCO, or
17.3
--
USHFRCO
Using HFXO
14.9
--
26
MHz
26
MHz
--
ns
--
ns
Using HFRCO, AUXHFRCO, or
17.3
--
USHFRCO
--
ns
Using HFXO
14.9
--
--
ns
1.1
--
6.6
ns
5.1
--
--
ns
2.5
--
--
ns
--
--
17.7
ns
3
--
--
ns
Table 4.57. SDIO MMC SDR Mode Timing (Location 1, 1.62 V I/O)
Parameter
Symbol
Clock frequency during data FSD_CLK transfer
Clock low time
tWL
Clock high time
tWH
Clock rise time
tR
Input setup time, CMD,
tISU
DAT[0:7] valid to SD_CLK
Input hold time, SD_CLK to tIH CMD, DAT[0:7] change
Test Condition
Min
Typ
Using HFRCO, AUXHFRCO, or
--
--
USHFRCO
Using HFXO
--
--
Using HFRCO, AUXHFRCO, or
19.6
--
USHFRCO
Using HFXO
16.9
--
Using HFRCO, AUXHFRCO, or
19.6
--
USHFRCO
Using HFXO
16.9
--
1.1
--
6.1
--
2.5
--
Max
Unit
23
MHz
23
MHz
--
ns
--
ns
--
ns
--
ns
6.6
ns
--
ns
--
ns
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Parameter
Symbol
Output delay time, SD_CLK tODLY to CMD, DAT[0:7] valid
Output hold time, SD_CLK to tOH CMD, DAT[0:7] change
SD_CLK
CMD, DAT[0:7]
Test Condition
tWL
EFM32GG11 Family Data Sheet
Electrical Specifications
Min
Typ
Max
Unit
--
--
29.7
ns
3
--
--
ns
tWH
Not Valid
tISU
tIH
Valid
Input Timing
Not Valid
SD_CLK
CMD, DAT[0:7]
tODLY (max) Not Valid
tOH (min)
Valid
Not Valid
Output Timing
Figure 4.18. SDIO MMC SDR Mode Timing
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EFM32GG11 Family Data Sheet
Electrical Specifications
SDIO MMC SDR Mode Timing at 3.0 V
Timing is specified at 3.0 V IOVDD with voltage scaling disabled. Slew rate for SD_CLK set to 7, all other GPIO set to 6, DRIVESTRENGTH = STRONG for all pins. SDIO_CTRL_TXDLYMUXSEL = 1. Loading between 5 and 10 pF on all pins or between 10 and 20 pF on all pins.
Table 4.58. SDIO MMC SDR Mode Timing (Location 0, 3 V I/O)
Parameter
Symbol
Clock frequency during data FSD_CLK transfer
Clock low time
tWL
Clock high time
tWH
Clock rise time
tR
Input setup time, CMD,
tISU
DAT[0:7] valid to SD_CLK
Input hold time, SD_CLK to tIH CMD, DAT[0:7] change
Output delay time, SD_CLK tODLY to CMD, DAT[0:7] valid
Output hold time, SD_CLK to tOH CMD, DAT[0:7] change
Test Condition
Min
Typ
Max
Unit
Using HFRCO, AUXHFRCO, or
--
--
50
MHz
USHFRCO
Using HFXO
--
--
50
MHz
Using HFRCO, AUXHFRCO, or
9
USHFRCO
--
--
ns
Using HFXO
7.6
--
--
ns
Using HFRCO, AUXHFRCO, or
9
USHFRCO
--
--
ns
Using HFXO
7.6
--
--
ns
0.8
--
2.5
ns
3.4
--
--
ns
2.5
--
--
ns
--
--
14
ns
3
--
--
ns
Table 4.59. SDIO MMC SDR Mode Timing (Location 1, 3 V I/O)
Parameter
Symbol
Clock frequency during data FSD_CLK transfer
Clock low time
tWL
Clock high time
tWH
Clock rise time
tR
Input setup time, CMD,
tISU
DAT[0:7] valid to SD_CLK
Input hold time, SD_CLK to tIH CMD, DAT[0:7] change
Test Condition
Min
Typ
Using HFRCO, AUXHFRCO, or
--
--
USHFRCO
Using HFXO
--
--
Using HFRCO, AUXHFRCO, or
14.1
--
USHFRCO
Using HFXO
12.1
--
Using HFRCO, AUXHFRCO, or
14.1
--
USHFRCO
Using HFXO
12.1
--
0.8
--
5.2
--
2.5
--
Max
Unit
32
MHz
32
MHz
--
ns
--
ns
--
ns
--
ns
2.5
ns
--
ns
--
ns
silabs.com | Building a more connected world.
Rev. 1.0 | 102
Parameter
Symbol
Output delay time, SD_CLK tODLY to CMD, DAT[0:7] valid
Output hold time, SD_CLK to tOH CMD, DAT[0:7] change
SD_CLK
CMD, DAT[0:7]
Test Condition
tWL
EFM32GG11 Family Data Sheet
Electrical Specifications
Min
Typ
Max
Unit
--
--
24.9
ns
3
--
--
ns
tWH
Not Valid
tISU
tIH
Valid
Input Timing
Not Valid
SD_CLK
CMD, DAT[0:7]
tODLY (max) Not Valid
tOH (min)
Valid
Not Valid
Output Timing
Figure 4.19. SDIO MMC SDR Mode Timing
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EFM32GG11 Family Data Sheet
Electrical Specifications
SDIO MMC DDR Mode Timing at 1.8 V
Timing is specified at 1.62 V IOVDD with voltage scaling disabled. Slew rate for SD_CLK set to 7, all other GPIO set to 6, DRIVESTRENGTH = STRONG for all pins. SDIO_CTRL_TXDLYMUXSEL = 1. Loading between 5 and 10 pF on all pins or between 10 and 25 pF on all pins.
Table 4.60. SDIO MMC DDR Mode Timing (Location 0, 1.62 V I/O)
Parameter
Symbol
Clock frequency during data FSD_CLK transfer
Clock low time
tWL
Clock high time
tWH
Clock rise time
tR
Clock fall time
tF
Input setup time, CMD valid tISU to SD_CLK
Input hold time, SD_CLK to tIH CMD change
Output delay time, SD_CLK tODLY to CMD valid
Output hold time, SD_CLK to tOH CMD change
Input setup time, DAT[0:7] valid to SD_CLK
tISU2X
Input hold time, SD_CLK to tIH2X DAT[0:7] change
Output delay time, SD_CLK tODLY2X to DAT[0:7] valid
Output hold time, SD_CLK to tOH2X DAT[0:7] change
Test Condition
Min
Typ
Max
Unit
Using HFRCO, AUXHFRCO, or
--
--
18
MHz
USHFRCO
Using HFXO
--
--
15.5
MHz
Using HFRCO, AUXHFRCO, or
25.1
--
USHFRCO
--
ns
Using HFXO
25.4
--
--
ns
Using HFRCO, AUXHFRCO, or
25.1
--
USHFRCO
--
ns
Using HFXO
25.4
--
--
ns
0.8
--
6.1
ns
0.7
--
4.7
ns
3.8
--
--
ns
2.5
--
--
ns
--
--
20.1
ns
3
--
--
ns
7.4
--
--
ns
2.5
--
--
ns
--
--
22.7
ns
3
--
--
ns
Table 4.61. SDIO MMC DDR Mode Timing (Location 1, 1.62 V I/O)
Parameter
Symbol
Clock frequency during data FSD_CLK transfer
Clock low time
tWL
Test Condition
Min
Typ
Using HFRCO, AUXHFRCO, or
--
--
USHFRCO
Using HFXO
--
--
Using HFRCO, AUXHFRCO, or
36.1
--
USHFRCO
Using HFXO
35.9
--
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Max
Unit
12.5
MHz
11
MHz
--
ns
--
ns
Rev. 1.0 | 104
Parameter Clock high time
Symbol tWH
Clock rise time
tR
Clock fall time
tF
Input setup time, CMD valid tISU to SD_CLK
Input hold time, SD_CLK to tIH CMD change
Output delay time, SD_CLK tODLY to CMD valid
Output hold time, SD_CLK to tOH CMD change
Input setup time, DAT[0:7] valid to SD_CLK
tISU2X
Input hold time, SD_CLK to tIH2X DAT[0:7] change
Output delay time, SD_CLK tODLY2X to DAT[0:7] valid
Output hold time, SD_CLK to tOH2X DAT[0:7] change
Test Condition
Min
Using HFRCO, AUXHFRCO, or
36.1
USHFRCO
Using HFXO
35.9
0.8
0.7
13.7
2.5
--
3
16.4
2.5
--
3
EFM32GG11 Family Data Sheet
Electrical Specifications
Typ
Max
Unit
--
--
ns
--
--
ns
--
6.1
ns
--
4.7
ns
--
--
ns
--
--
ns
--
33.1
ns
--
--
ns
--
--
ns
--
--
ns
--
40.4
ns
--
--
ns
SD_CLK
tWH
tWL
tISU2X tIH2X
tISU2X tIH2X
DAT[0:7]
xxxx Valid xxxx Valid xxxx Valid xxxx Valid
tISU
tIH
xxxx
CMD
Not Valid
Valid
Not Valid
Input Timing
SD_CLK
tWH
tWL
tODLY2X (max) tODLY2X (min)
tODLY2X (max) tODLY2X (min)
DAT[0:7]
xxxx
Valid xxxx Valid tODLY (max)
xxxx
Valid xxxx Valid tOH (min)
xxxx
CMD
Not Valid
Valid
Not Valid
Output Timing
Figure 4.20. SDIO MMC DDR Mode Timing
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EFM32GG11 Family Data Sheet
Electrical Specifications
SDIO MMC DDR Mode Timing at 3.0 V
Timing is specified at 3.0 V IOVDD with voltage scaling disabled. Slew rate for SD_CLK set to 7, all other GPIO set to 6, DRIVESTRENGTH = STRONG for all pins. SDIO_CTRL_TXDLYMUXSEL = 1. Loading between 5 and 10 pF on all pins or between 10 and 25 pF on all pins.
Table 4.62. SDIO MMC DDR Mode Timing (Location 0, 3 V I/O)
Parameter
Symbol
Clock frequency during data FSD_CLK transfer
Clock low time
tWL
Clock high time
tWH
Clock rise time
tR
Clock fall time
tF
Input setup time, CMD valid tISU to SD_CLK
Input hold time, SD_CLK to tIH CMD change
Output delay time, SD_CLK tODLY to CMD valid
Output hold time, SD_CLK to tOH CMD change
Input setup time, DAT[0:7] valid to SD_CLK
tISU2X
Input hold time, SD_CLK to tIH2X DAT[0:7] change
Output delay time, SD_CLK tODLY2X to DAT[0:7] valid
Output hold time, SD_CLK to tOH2X DAT[0:7] change
Test Condition
Min
Typ
Max
Unit
Using HFRCO, AUXHFRCO, or
--
--
20
MHz
USHFRCO
Using HFXO
--
--
17.5
MHz
Using HFRCO, AUXHFRCO, or
22.6
--
USHFRCO
--
ns
Using HFXO
22.4
--
--
ns
Using HFRCO, AUXHFRCO, or
22.6
--
USHFRCO
--
ns
Using HFXO
22.4
--
--
ns
0.8
--
2.8
ns
0.7
--
2.4
ns
7.1
--
--
ns
2.5
--
--
ns
--
--
20.7
ns
3
--
--
ns
10.1
--
--
ns
2.5
--
--
ns
--
--
23.7
ns
3
--
--
ns
Table 4.63. SDIO MMC DDR Mode Timing (Location 1, 3 V I/O)
Parameter
Symbol
Clock frequency during data FSD_CLK transfer
Clock low time
tWL
Test Condition
Min
Typ
Using HFRCO, AUXHFRCO, or
--
--
USHFRCO
Using HFXO
--
--
Using HFRCO, AUXHFRCO, or
36.1
--
USHFRCO
Using HFXO
34.3
--
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Max
Unit
12.5
MHz
11.5
MHz
--
ns
--
ns
Rev. 1.0 | 106
Parameter Clock high time
Symbol tWH
Clock rise time
tR
Clock fall time
tF
Input setup time, CMD valid tISU to SD_CLK
Input hold time, SD_CLK to tIH CMD change
Output delay time, SD_CLK tODLY to CMD valid
Output hold time, SD_CLK to tOH CMD change
Input setup time, DAT[0:7] valid to SD_CLK
tISU2X
Input hold time, SD_CLK to tIH2X DAT[0:7] change
Output delay time, SD_CLK tODLY2X to DAT[0:7] valid
Output hold time, SD_CLK to tOH2X DAT[0:7] change
Test Condition
Min
Using HFRCO, AUXHFRCO, or
36.1
USHFRCO
Using HFXO
34.3
0.8
0.7
11.6
2.5
--
3
14.7
2.5
--
3
EFM32GG11 Family Data Sheet
Electrical Specifications
Typ
Max
Unit
--
--
ns
--
--
ns
--
2.8
ns
--
2.4
ns
--
--
ns
--
--
ns
--
29.3
ns
--
--
ns
--
--
ns
--
--
ns
--
38.6
ns
--
--
ns
SD_CLK
tWH
tWL
tISU2X tIH2X
tISU2X tIH2X
DAT[0:7]
xxxx Valid xxxx Valid xxxx Valid xxxx Valid
tISU
tIH
xxxx
CMD
Not Valid
Valid
Not Valid
Input Timing
SD_CLK
tWH
tWL
tODLY2X (max) tODLY2X (min)
tODLY2X (max) tODLY2X (min)
DAT[0:7]
xxxx
Valid xxxx Valid tODLY (max)
xxxx
Valid xxxx Valid tOH (min)
xxxx
CMD
Not Valid
Valid
Not Valid
Output Timing
Figure 4.21. SDIO MMC DDR Mode Timing
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4.1.28 Quad SPI (QSPI)
EFM32GG11 Family Data Sheet
Electrical Specifications
4.1.28.1 QSPI SDR Mode
QSPI SDR Mode Timing (Location 0) Timing is specified with voltage scaling disabled, PHY-mode, route location 0 only, TX DLL = 25, RX DLL = 61, 5-25 pF loading per GPIO, and slew rate for all GPIO set to 6, DRIVESTRENGTH = STRONG.
Table 4.64. QSPI SDR Mode Timing (Location 0)
Parameter Full SCLK period
Output valid Output hold Input setup Input hold
Symbol T
tOV tOH tSU tH
Test Condition
Min
Typ
(1/FSCLK) *
--
0.95
--
--
T/2 - 34.1
--
29.8 - T/2
--
T/2 - 0.5
--
Max
Unit
--
ns
T/2 - 2.3
ns
--
ns
--
ns
--
ns
QSPI SDR Mode Timing (Optimal Conditions) Timing is specified at IOVDD 3.0V, using internal HFRCO oscillator and with voltage scaling disabled, PHY-mode, route location 0 only, TX DLL = 25, RX DLL = 43, 5-25 pF loading per GPIO, and slew rate for all GPIO set to 6, DRIVESTRENGTH = STRONG.
Table 4.65. QSPI SDR Mode Timing (Optimized at 3.0V, Location 0)
Parameter Full SCLK period
Output valid Output hold Input setup Input hold
Symbol T
tOV tOH tSU tH
Test Condition
Min
Typ
(1/FSCLK) *
--
0.95
--
--
T/2 - 24.7
--
21.9 - T/2
--
T/2 - 4.6
--
Max
Unit
--
ns
T/2 - 2.4
ns
--
ns
--
ns
--
ns
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Rev. 1.0 | 108
EFM32GG11 Family Data Sheet
Electrical Specifications
QSPI SDR Mode Timing (Locations 1, 2) Timing is specified with voltage scaling disabled, PHY-mode, route locations other than 0, TX DLL = 37, RX DLL = 79, 5-25 pF loading per GPIO, and slew rate for all GPIO set to 6, DRIVESTRENGTH = STRONG.
Table 4.66. QSPI SDR Mode Timing (Locations 1, 2)
Parameter Full SCLK period
Output valid Output hold Input setup Input hold
Symbol T
tOV tOH tSU tH
Test Condition
Min
Typ
(1/FSCLK) *
--
0.95
--
--
T/2 - 44.1
--
38.2 - T/2
--
T/2 - 0.8
--
Max
Unit
--
ns
T/2 - 2.0
ns
--
ns
--
ns
--
ns
SCLK DQx
DQx Output Timing
tOV
tOH
SCLK DQx
DQx Input Timing
tSU
tH
Figure 4.22. QSPI SDR Timing Diagrams
QSPI SDR Flash Timing Example
This example uses timing values from SDR Mode Timing (Optimal Conditions) to demonstrate the calculation of allowable flash timing using the QSPI in SDR mode. � Using a configured SCLK frequency (FSCLK) of 33 MHz: � The resulting minimum period, T(min) = (1/FSCLK) * 0.95 = 28.8 ns. � Flash will see a minimum setup time of T/2 � tOV = T/2 � (T/2 � 2.4) = 2.4 ns. � Flash will see a minimum hold time of T/2 + tOH = T/2 + (T/2 � 24.7) = T � 24.7 = 28.8 � 24.7 = 4.1 ns. � Flash can have a maximum output valid time of T/2 � tSU = T/2 � (21.9 � T/2) = T � 21.9 = 28.8 � 21.9 = 6.9 ns. � Flash can have a minimum output hold time of tH � T/2 = (T/2 � 4.6) � T/2 = - 4.6 ns.
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4.1.28.2 QSPI DDR Mode
EFM32GG11 Family Data Sheet
Electrical Specifications
QSPI DDR Mode Timing (Location 0) Timing is specified with voltage scaling disabled, PHY-mode, route location 0 only, TX DLL = 35, RX DLL = 69, 5-25 pF loading per GPIO, and slew rate for all GPIO set to 6, DRIVESTRENGTH = STRONG.
Table 4.67. QSPI DDR Mode Timing (Location 0)
Parameter Half SCLK period
Output valid Output hold Input setup Input hold
Symbol T/2
tOV tOH tSU tH
Test Condition
Min
Typ
HFXO
(1/FSCLK) *
--
0.4 - 0.4
HFRCO, AUXHFRCO, USHFRCO (1/FSCLK) *
--
0.44
--
--
T/2 - 39.4
--
33.7
--
-0.8
--
Max
Unit
--
ns
--
ns
T/2 - 4.5
ns
--
ns
--
ns
--
ns
QSPI DDR Mode Timing (Optimal Conditions) Timing is specified at IOVDD 3.0V, using internal HFRCO oscillator and with voltage scaling disabled, PHY-mode, route location 0 only, TX DLL = 26, RX DLL = 60, 5-25 pF loading per GPIO, and slew rate for all GPIO set to 6, DRIVESTRENGTH = STRONG.
Table 4.68. QSPI DDR Mode Timing (Optimized at 3.0V, Location 0)
Parameter Half SCLK period
Output valid Output hold Input setup Input hold
Symbol T/2
tOV tOH tSU tH
Test Condition
Min
Typ
HFRCO, AUXHFRCO, USHFRCO (1/FSCLK) *
--
0.44
--
--
T/2 - 24.3
--
14.4
--
-0.9
--
Max
Unit
--
ns
T/2 - 2.5
ns
--
ns
--
ns
--
ns
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EFM32GG11 Family Data Sheet
Electrical Specifications
QSPI DDR Mode Timing (Locations 1, 2) Timing is specified with voltage scaling disabled, PHY-mode, route locations other than 0, TX DLL = 39, RX DLL = 84, 5-25 pF loading per GPIO, and slew rate for all GPIO set to 6, DRIVESTRENGTH = STRONG.
Table 4.69. QSPI DDR Mode Timing (Locations 1, 2)
Parameter Half SCLK period
Output valid Output hold Input setup Input hold
Symbol T/2
tOV tOH tSU tH
Test Condition
Min
Typ
HFXO
(1/FSCLK) *
--
0.4 - 0.4
HFRCO, AUXHFRCO, USHFRCO (1/FSCLK) *
--
0.44
--
--
T/2 - 43.5
--
38.4
--
0.0
--
Max
Unit
--
ns
--
ns
T/2 - 3.0
ns
--
ns
--
ns
--
ns
SCLK DQx
DQx Output Timing
tOV
tOV
tOH
tOH
SCLK DQx
DQx Input Timing
tSU
tH
tSU
tH
Figure 4.23. QSPI DDR Timing Diagrams
QSPI DDR Flash Timing Example
This example uses timing values for DDR Mode Timing (Optimal Conditions) to demonstrate the calculation of allowable flash timing using the QSPI in DDR mode. � Using a configured SCLK frequency (FSCLK) of 17 MHz from the HFXO clock source: � The resulting minimum half-period, T/2(min) = (1/FSCLK) * 0.44 = 25.9 ns. � Flash will see a minimum setup time of T/2 � tOV = T/2 � (T/2 � 2.5) = 2.5 ns. � Flash will see a minimum hold time of tOH = T/2 � 24.3 = 25.9 � 24.3 = 1.6 ns. � Flash can have a maximum output valid time of T/2 � tSU = T/2 � 14.4 = 25.9 � 14.4 = 11.5 ns. � Flash can have a minimum output hold time of tH = - 0.9 ns.
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4.2 Typical Performance Curves Typical performance curves indicate typical characterized performance under the stated conditions.
EFM32GG11 Family Data Sheet
Electrical Specifications
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4.2.1 Supply Current
EFM32GG11 Family Data Sheet
Electrical Specifications
Figure 4.24. EM0 Full Speed Active Mode Typical Supply Current vs. Temperature
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EFM32GG11 Family Data Sheet
Electrical Specifications
Figure 4.25. EM0 Active Mode Typical Supply Current vs. Temperature
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EFM32GG11 Family Data Sheet
Electrical Specifications
Figure 4.26. EM1 Sleep Mode Typical Supply Current vs. Temperature Typical supply current for EM2, EM3 and EM4H using standard software libraries from Silicon Laboratories.
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EFM32GG11 Family Data Sheet
Electrical Specifications
Figure 4.27. EM2, EM3, EM4H and EM4S Typical Supply Current vs. Temperature
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EFM32GG11 Family Data Sheet
Electrical Specifications
Figure 4.28. EM0 and EM1 Mode Typical Supply Current vs. Supply Typical supply current for EM2, EM3 and EM4H using standard software libraries from Silicon Laboratories.
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EFM32GG11 Family Data Sheet
Electrical Specifications
Figure 4.29. EM2, EM3, EM4H and EM4S Typical Supply Current vs. Supply
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EFM32GG11 Family Data Sheet
Electrical Specifications
4.2.2 DC-DC Converter Default test conditions: CCM mode, LDCDC = 4.7 H, CDCDC = 4.7 F, VDCDC_I = 3.3 V, VDCDC_O = 1.8 V, FDCDC_LN = 7 MHz
Figure 4.30. DC-DC Converter Typical Performance Characteristics
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EFM32GG11 Family Data Sheet
Electrical Specifications
LN (CCM) and LP mode transition (load: 5mA)
Load Step Response in LN (CCM) mode (Heavy Drive)
DVDD
60mV/div offset:1.8V
VSW
2V/div offset:1.8V
100s/div
DVDD
20mV/div offset:1.8V
100mA
ILOAD
1mA
10s/div
Figure 4.31. DC-DC Converter Transition Waveforms
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5. Pin Definitions
5.1 EFM32GG11B8xx in BGA192 Device Pinout
EFM32GG11 Family Data Sheet
Pin Definitions
Figure 5.1. EFM32GG11B8xx in BGA192 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 5.20 GPIO Functionality Table or 5.21 Alternate Functionality Overview.
Table 5.1. EFM32GG11B8xx in BGA192 Device Pinout
Pin Name PA15 PE14 PE12 PE10 PE8 PI6
Pin(s) Description A1 GPIO A3 GPIO A5 GPIO A7 GPIO A9 GPIO A11 GPIO (5V)
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Pin Name PE15 PE13 PE11 PE9 PI9 PF14
Pin(s) Description A2 GPIO A4 GPIO A6 GPIO A8 GPIO A10 GPIO (5V) A12 GPIO (5V)
Rev. 1.0 | 121
Pin Name
VBUS
PF10 PA0 PD10 PF9 PF7 PI11 PF5 PF3
PF1
PA1 PD14 PI15 PI13 PI10 PF15 PF4 PC14 PA2 PD15 PC12 PA3 PG1 PC9 PA4
PG3
Pin(s) Description
A13
USB VBUS signal and auxiliary input to 5 V regulator.
A15 GPIO (5V)
B1 GPIO
B3 GPIO
B5 GPIO
B7 GPIO
B9 GPIO (5V)
B11 GPIO
B13 GPIO
Pin Name
PF11
PF0 PD11 PD9 PF8 PF6
PI8 PF13 PF2
B15 GPIO (5V)
VREGO
C1 GPIO C3 GPIO (5V) C5 GPIO (5V) C7 GPIO (5V) C9 GPIO (5V) C11 GPIO (5V) C13 GPIO C15 GPIO (5V) D1 GPIO D3 GPIO (5V) D15 GPIO (5V) E1 GPIO E3 GPIO (5V) E15 GPIO (5V) F1 GPIO
F3 GPIO (5V)
PD12 PD13 PI14 PI12
PI7 PF12 PC15 VREGI PG0 PC13 PC11 PG2 PC10 PC8 PG4
IOVDD2
EFM32GG11 Family Data Sheet
Pin Definitions
Pin(s) Description
A14 GPIO (5V)
A16 GPIO (5V)
B2 GPIO
B4 GPIO
B6 GPIO
B8 GPIO
B10 GPIO (5V)
B12 GPIO (5V)
B14 GPIO
Decoupling for 5 V regulator and reguB16 lator output. Power for USB PHY in
USB-enabled OPNs
C2 GPIO
C4 GPIO (5V)
C6 GPIO (5V)
C8 GPIO (5V)
C10 GPIO (5V)
C12 GPIO
C14 GPIO (5V)
C16 Input to 5 V regulator.
D2 GPIO (5V)
D14 GPIO (5V)
D16 GPIO (5V)
E2 GPIO (5V)
E14 GPIO (5V)
E16 GPIO (5V)
F2 GPIO (5V)
F6 G6
Digital IO power supply 2.
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Pin Name
Pin(s) Description
IOVDD1
F7 G7
Digital IO power supply 1.
NC
F9 No Connect.
PI5 PI3 PG6 PI2 PI0 PG8 PE5 PE7 PG10 PE3
DECOUPLE
PG13 PE1 DVDD PB15 PE0 VREGVDD
F14 GPIO (5V) F16 GPIO (5V) G2 GPIO (5V) G14 GPIO (5V) G16 GPIO (5V) H2 GPIO (5V) H14 GPIO H16 GPIO J2 GPIO (5V) J14 GPIO
Decouple output for on-chip voltage J16 regulator. An external decoupling ca-
pacitor is required at this pin. K2 GPIO K14 GPIO (5V) K16 Digital power supply. L2 GPIO (5V) L14 GPIO (5V) L16 Voltage regulator VDD input
Pin Name
VSS
IOVDD0
PI4 PA5 PG5 PI1 PA6 PG7 PE6 PG11 PG9 PE4 PG14 PG12 PE2 PG15 PB0 PC7 PB1
EFM32GG11 Family Data Sheet
Pin Definitions
Pin(s) Description
F8 G8 G9 H6 H7 H8 H9 H10 H11 J6 Ground J7 J8 J9 J10 J11 K8 K9 L8 L9
F10
F11
G10
G11
K6
K7 K10
Digital IO power supply 0.
K11
L6
L7
L10
L11
F15 GPIO (5V)
G1 GPIO
G3 GPIO (5V)
G15 GPIO (5V)
H1 GPIO
H3 GPIO (5V)
H15 GPIO
J1 GPIO (5V)
J3 GPIO (5V)
J15 GPIO
K1 GPIO
K3 GPIO K15 GPIO L1 GPIO (5V) L3 GPIO L15 GPIO M1 GPIO
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EFM32GG11 Family Data Sheet
Pin Definitions
Pin Name
Pin(s) Description
Pin Name
Pin(s) Description
PB2
M2 GPIO
PB3
M3 GPIO
PC6
M14 GPIO
VREGVSS
M15 N16
Voltage regulator VSS
VREGSW
M16 DCDC regulator switching node
PB4
N1 GPIO
PB5
N2 GPIO
PB6
N3 GPIO
PD5
N14 GPIO
PD4
N15 GPIO
PC0
P1 GPIO (5V)
PC1
P2 GPIO (5V)
PC2
P3 GPIO (5V)
PA8
P4 GPIO
PA11
P5 GPIO
PA13
P6 GPIO (5V)
PB9
P7 GPIO (5V)
PB12
P8 GPIO
PH2
P9 GPIO (5V)
PH5
P10 GPIO
PH8
P11 GPIO (5V)
PH11
P12 GPIO (5V)
PH13
P13 GPIO (5V)
PD0
P14 GPIO (5V)
PD3
P15 GPIO
PD8
P16 GPIO
PB7
R1 GPIO
PC3
R2 GPIO (5V)
PC5
R3 GPIO
PA9
R4 GPIO
BODEN
Brown-Out Detector Enable. This pin R5 may be left disconnected or tied to
AVDD.
RESETn
Reset input, active low. To apply an external reset source to this pin, it is reR6 quired to only drive this pin low during reset, and let the internal pull-up ensure that reset is released.
PB10
R7 GPIO (5V)
PH0
R8 GPIO (5V)
PH3
R9 GPIO (5V)
PH6
R10 GPIO
PH9
R11 GPIO (5V)
PH12
R12 GPIO (5V)
PH14
R13 GPIO (5V)
PH15
R14 GPIO (5V)
PD2
R15 GPIO (5V)
PD7
R16 GPIO
PB8
T1 GPIO
PC4
T2 GPIO
PA7
T3 GPIO
PA10
T4 GPIO
PA12
T5 GPIO (5V)
PA14
T6 GPIO
PB11
T7 GPIO
PH1
T8 GPIO (5V)
PH4
T9 GPIO
PH7
T10 GPIO (5V)
PH10
T11 GPIO (5V)
PB13
T12 GPIO
PB14
T13 GPIO
AVDD
T14 Analog power supply.
PD1
T15 GPIO
PD6
T16 GPIO
Note:
1. GPIO with 5V tolerance are indicated by (5V).
2. The pins PD13, PD14, and PD15 will not be 5V tolerant on all future devices. In order to preserve upgrade options with full hardware compatibility, do not use these pins with 5V domains.
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5.2 EFM32GG11B8xx in BGA152 Device Pinout
EFM32GG11 Family Data Sheet
Pin Definitions
Figure 5.2. EFM32GG11B8xx in BGA152 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 5.20 GPIO Functionality Table or 5.21 Alternate Functionality Overview.
Table 5.2. EFM32GG11B8xx in BGA152 Device Pinout
Pin Name PE15 PE11 PD12 PF9
PF13
PF1 PF11
Pin(s) Description A1 GPIO A3 GPIO A5 GPIO A7 GPIO
A9 GPIO (5V)
A11 GPIO (5V) A13 GPIO (5V)
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Pin Name PE13 PE9 PD10 PF7
VBUS
PC15 PF10
Pin(s) Description
A2 GPIO
A4 GPIO
A6 GPIO
A8 GPIO
A10
USB VBUS signal and auxiliary input to 5 V regulator.
A12 GPIO (5V)
A14 GPIO (5V)
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Pin Name PA15 PE12 PD11 PF8 PF14 PF2
Pin(s) Description B1 GPIO B3 GPIO B5 GPIO B7 GPIO B9 GPIO (5V) B11 GPIO
PC14
B13 GPIO (5V)
PA1 PD13
PI8 PI6 PF15 PF3 PC12 PA3 PD14 PC10 PA5 PD15
VSS
PC8 PI4 PA6 IOVDD2 PI2 PG3 PG2
C1 GPIO
C3 GPIO (5V)
C5 GPIO (5V)
C7 GPIO (5V)
C9 GPIO (5V)
C11 GPIO
C13 GPIO (5V)
D1 GPIO
D3 GPIO (5V)
D13 GPIO (5V)
E1 GPIO
E3 GPIO (5V)
E7
E8
G5
G7
G8
G10 H5
Ground
H7
H8
H10
K7
K8
E12 GPIO (5V)
E14 GPIO (5V)
F2 GPIO
F5 Digital IO power supply 2.
F13 GPIO (5V)
G1 GPIO (5V)
G3 GPIO (5V)
PI0
G13 GPIO (5V)
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Pin Name PE14 PE8 PD9 PF6 PF12 PF0
VREGO
PA0 PE10 PI7 PF5 PF4 PC13 VREGI PA2 PC11 PC9 PA4 IOVDD1
EFM32GG11 Family Data Sheet
Pin Definitions
Pin(s) Description B2 GPIO B4 GPIO B6 GPIO B8 GPIO B10 GPIO B12 GPIO (5V) Decoupling for 5 V regulator and reguB14 lator output. Power for USB PHY in USB-enabled OPNs C2 GPIO C4 GPIO C6 GPIO (5V) C8 GPIO C10 GPIO C12 GPIO (5V) C14 Input to 5 V regulator. D2 GPIO D12 GPIO (5V) D14 GPIO (5V) E2 GPIO E6 Digital IO power supply 1.
IOVDD0
E9
F10
J5 J10
Digital IO power supply 0.
K6
K9
PI5 PG0 PG1 PI3 PI1 PG4 PE7
DECOUPLE
E13 GPIO (5V)
F1 GPIO (5V)
F3 GPIO (5V)
F12 GPIO (5V)
F14 GPIO (5V)
G2 GPIO (5V)
G12 GPIO
Decouple output for on-chip voltage G14 regulator. An external decoupling ca-
pacitor is required at this pin.
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Pin Name PG6 PG5 PE5 PG9 PG8 PE4 PG12 PG11 PE1 PG15 PG14 PE0 PB0 PB4 PC3
BODEN
RESETn
PD1 PD5 PB7 PB5 PC5 PA11 PB11 PD0 PD4 PB8 PB6 PC4 PA10 PB9 PB14 PD3
EFM32GG11 Family Data Sheet
Pin Definitions
Pin(s) Description
Pin Name
H1 GPIO (5V)
PG7
H3 GPIO (5V)
PE6
H13 GPIO
DVDD
J1 GPIO (5V)
PG10
J3 GPIO (5V)
PE3
J13 GPIO
VREGVDD
K1 GPIO
PG13
K3 GPIO (5V)
PE2
K13 GPIO (5V)
VREGSW
L1 GPIO (5V)
PB15
L3 GPIO
PC7
L13 GPIO (5V)
VREGVSS
M1 GPIO
PB1
M3 GPIO
PC0
M5 GPIO (5V)
PA9
Brown-Out Detector Enable. This pin M7 may be left disconnected or tied to
AVDD.
PA12
Reset input, active low. To apply an external reset source to this pin, it is reM9 quired to only drive this pin low during reset, and let the internal pull-up ensure that reset is released.
PB10
M11 GPIO
PC6
M13 GPIO
PD8
N1 GPIO
PB2
N3 GPIO
PC2
N5 GPIO
PA8
N7 GPIO
PA14
N9 GPIO
PB12
N11 GPIO (5V)
PD2
N13 GPIO
PD7
P1 GPIO
PB3
P3 GPIO
PC1
P5 GPIO
PA7
P7 GPIO
PA13
P9 GPIO (5V)
PB13
P11 GPIO
AVDD
P13 GPIO
PD6
Pin(s) Description H2 GPIO (5V) H12 GPIO H14 Digital power supply. J2 GPIO (5V) J12 GPIO J14 Voltage regulator VDD input K2 GPIO K12 GPIO K14 DCDC regulator switching node L2 GPIO (5V) L12 GPIO L14 Voltage regulator VSS M2 GPIO M4 GPIO (5V) M6 GPIO
M8 GPIO (5V)
M10 GPIO (5V)
M12 GPIO M14 GPIO N2 GPIO N4 GPIO (5V) N6 GPIO N8 GPIO N10 GPIO N12 GPIO (5V) N14 GPIO P2 GPIO P4 GPIO (5V) P6 GPIO P8 GPIO (5V) P10 GPIO P12 Analog power supply. P14 GPIO
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EFM32GG11 Family Data Sheet
Pin Definitions
Pin Name
Pin(s) Description
Pin Name
Pin(s) Description
Note:
1. GPIO with 5V tolerance are indicated by (5V).
2. The pins PD13, PD14, and PD15 will not be 5V tolerant on all future devices. In order to preserve upgrade options with full hardware compatibility, do not use these pins with 5V domains.
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5.3 EFM32GG11B8xx in BGA120 Device Pinout
EFM32GG11 Family Data Sheet
Pin Definitions
Figure 5.3. EFM32GG11B8xx in BGA120 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 5.20 GPIO Functionality Table or 5.21 Alternate Functionality Overview.
Table 5.3. EFM32GG11B8xx in BGA120 Device Pinout
Pin Name PE15 PE12 PD11 PF7 PF14
VREGI
Pin(s) Description A1 GPIO A3 GPIO A5 GPIO A7 GPIO A9 GPIO (5V)
A11 Input to 5 V regulator.
Pin Name PE14 PE9 PD9 PF5 PF12
VREGO
Pin(s) Description
A2 GPIO
A4 GPIO
A6 GPIO
A8 GPIO
A10 GPIO
Decoupling for 5 V regulator and reguA12 lator output. Power for USB PHY in
USB-enabled OPNs
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Pin Name PF11 PE13 PE8 PD10 PF6 PF4 VBUS PA1 PE10
VSS
Pin(s) Description
A13 GPIO (5V)
B2 GPIO
B4 GPIO
B6 GPIO
B8 GPIO
B10 GPIO
B12
USB VBUS signal and auxiliary input to 5 V regulator.
C1 GPIO
C3 GPIO
C5 C8 H3 J3 Ground K11 L5 L8
Pin Name PA15 PE11 PD12 PF8 PF13 PF3 PF10 PA0 PD13
IOVDD1
PF9
C7 GPIO
IOVDD0
PF2 PC14 PA3 PB15 PC12 PA6 PA4 PC10 PB0 PB2 PE7 PB3 IOVDD2 PE4 PB5 DVDD
DECOUPLE
PD15
C10 GPIO C12 GPIO (5V) D1 GPIO D3 GPIO (5V) D12 GPIO (5V) E1 GPIO E3 GPIO E12 GPIO (5V) F1 GPIO F3 GPIO F12 GPIO G1 GPIO G3 Digital IO power supply 2. G12 GPIO H1 GPIO H11 Digital power supply.
Decouple output for on-chip voltage H13 regulator. An external decoupling ca-
pacitor is required at this pin. J2 GPIO (5V)
PF1 PC15 PA2 PF0 PC13 PA5 PC9 PC11 PB1 PE6 PC8 PB4 PE3 PE5 PB6 PE2
PD14
PE1
EFM32GG11 Family Data Sheet
Pin Definitions
Pin(s) Description B1 GPIO B3 GPIO B5 GPIO B7 GPIO B9 GPIO (5V) B11 GPIO
B13 GPIO (5V)
C2 GPIO C4 GPIO (5V)
C6 Digital IO power supply 1.
C9 J11 K3 Digital IO power supply 0. L4 L9 C11 GPIO (5V) C13 GPIO (5V) D2 GPIO D11 GPIO (5V) D13 GPIO (5V) E2 GPIO E11 GPIO (5V) E13 GPIO (5V) F2 GPIO F11 GPIO F13 GPIO (5V) G2 GPIO G11 GPIO G13 GPIO H2 GPIO H12 GPIO
J1 GPIO (5V)
J12 GPIO (5V)
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EFM32GG11 Family Data Sheet
Pin Definitions
Pin Name
Pin(s) Description
Pin Name
Pin(s) Description
VREGVDD J13 Voltage regulator VDD input
PC0
K1 GPIO (5V)
PC1
K2 GPIO (5V)
PE0
K12 GPIO (5V)
VREGSW
K13 DCDC regulator switching node
PC2
L1 GPIO (5V)
PC3
L2 GPIO (5V)
PA7
L3 GPIO
PB9
L6 GPIO (5V)
PB10
L7 GPIO (5V)
PD1
L10 GPIO
PC6
L11 GPIO
PC7
L12 GPIO
VREGVSS L13 Voltage regulator VSS
PB7
M1 GPIO
PC4
M2 GPIO
PA8
M3 GPIO
PA10
M4 GPIO
PA13
M5 GPIO (5V)
PA14
M6 GPIO
RESETn
Reset input, active low. To apply an external reset source to this pin, it is reM7 quired to only drive this pin low during reset, and let the internal pull-up ensure that reset is released.
PB12
M8 GPIO
PD0
M9 GPIO (5V)
PD2
M10 GPIO (5V)
PD3
M11 GPIO
PD4
M12 GPIO
PD8
M13 GPIO
PB8
N1 GPIO
PC5
N2 GPIO
PA9
N3 GPIO
PA11
N4 GPIO
PA12
N5 GPIO (5V)
PB11
N6 GPIO
BODEN
Brown-Out Detector Enable. This pin N7 may be left disconnected or tied to
AVDD.
PB13
N8 GPIO
PB14
N9 GPIO
AVDD
N10 Analog power supply.
PD5
N11 GPIO
PD6
N12 GPIO
PD7
N13 GPIO
Note:
1. GPIO with 5V tolerance are indicated by (5V).
2. The pins PD13, PD14, and PD15 will not be 5V tolerant on all future devices. In order to preserve upgrade options with full hardware compatibility, do not use these pins with 5V domains.
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5.4 EFM32GG11B5xx in BGA120 Device Pinout
EFM32GG11 Family Data Sheet
Pin Definitions
Figure 5.4. EFM32GG11B5xx in BGA120 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 5.20 GPIO Functionality Table or 5.21 Alternate Functionality Overview.
Table 5.4. EFM32GG11B5xx in BGA120 Device Pinout
Pin Name PE15 PE12 PD11 PF7 PF14
VREGI
Pin(s) Description A1 GPIO A3 GPIO A5 GPIO A7 GPIO A9 GPIO (5V)
A11 Input to 5 V regulator.
Pin Name PE14 PE9 PD9 PF5 PF12
VREGO
Pin(s) Description
A2 GPIO
A4 GPIO
A6 GPIO
A8 GPIO
A10 GPIO
Decoupling for 5 V regulator and reguA12 lator output. Power for USB PHY in
USB-enabled OPNs
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Pin Name PF11 PE13 PE8 PD10 PF6 PF4 NC PA1 PE10
VSS
Pin(s) Description
A13 GPIO (5V)
B2 GPIO
B4 GPIO
B6 GPIO
B8 GPIO
B10 GPIO
B12 No Connect.
C1 GPIO
C3 GPIO
C5 C8 H3 J3 Ground K11 L5 L8
PF9
C7 GPIO
PF2 PC14 PA3 PB15 PC12 PA6 PA4 PC10 PB0 PB2 PE7 PB3 IOVDD2 PE4 PB5 DVDD
DECOUPLE
PD15 VREGVDD
C10 GPIO C12 GPIO (5V) D1 GPIO D3 GPIO (5V) D12 GPIO (5V) E1 GPIO E3 GPIO E12 GPIO (5V) F1 GPIO F3 GPIO F12 GPIO G1 GPIO G3 Digital IO power supply 2. G12 GPIO H1 GPIO H11 Digital power supply.
Decouple output for on-chip voltage H13 regulator. An external decoupling ca-
pacitor is required at this pin. J2 GPIO (5V) J13 Voltage regulator VDD input
Pin Name PA15 PE11 PD12 PF8 PF13 PF3 PF10 PA0 PD13
IOVDD1
IOVDD0
PF1 PC15 PA2 PF0 PC13 PA5 PC9 PC11 PB1 PE6 PC8 PB4 PE3 PE5 PB6 PE2
PD14
PE1 PC0
EFM32GG11 Family Data Sheet
Pin Definitions
Pin(s) Description B1 GPIO B3 GPIO B5 GPIO B7 GPIO B9 GPIO (5V) B11 GPIO B13 GPIO (5V) C2 GPIO C4 GPIO (5V)
C6 Digital IO power supply 1.
C9 J11 K3 Digital IO power supply 0. L4 L9 C11 GPIO (5V) C13 GPIO (5V) D2 GPIO D11 GPIO (5V) D13 GPIO (5V) E2 GPIO E11 GPIO (5V) E13 GPIO (5V) F2 GPIO F11 GPIO F13 GPIO (5V) G2 GPIO G11 GPIO G13 GPIO H2 GPIO H12 GPIO
J1 GPIO (5V)
J12 GPIO (5V) K1 GPIO (5V)
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EFM32GG11 Family Data Sheet
Pin Definitions
Pin Name
Pin(s) Description
Pin Name
Pin(s) Description
PC1
K2 GPIO (5V)
PE0
K12 GPIO (5V)
VREGSW
K13 DCDC regulator switching node
PC2
L1 GPIO (5V)
PC3
L2 GPIO (5V)
PA7
L3 GPIO
PB9
L6 GPIO (5V)
PB10
L7 GPIO (5V)
PD1
L10 GPIO
PC6
L11 GPIO
PC7
L12 GPIO
VREGVSS L13 Voltage regulator VSS
PB7
M1 GPIO
PC4
M2 GPIO
PA8
M3 GPIO
PA10
M4 GPIO
PA13
M5 GPIO (5V)
PA14
M6 GPIO
RESETn
Reset input, active low. To apply an external reset source to this pin, it is reM7 quired to only drive this pin low during reset, and let the internal pull-up ensure that reset is released.
PB12
M8 GPIO
PD0
M9 GPIO (5V)
PD2
M10 GPIO (5V)
PD3
M11 GPIO
PD4
M12 GPIO
PD8
M13 GPIO
PB8
N1 GPIO
PC5
N2 GPIO
PA9
N3 GPIO
PA11
N4 GPIO
PA12
N5 GPIO (5V)
PB11
N6 GPIO
BODEN
Brown-Out Detector Enable. This pin N7 may be left disconnected or tied to
AVDD.
PB13
N8 GPIO
PB14
N9 GPIO
AVDD
N10 Analog power supply.
PD5
N11 GPIO
PD6
N12 GPIO
PD7
N13 GPIO
Note:
1. GPIO with 5V tolerance are indicated by (5V).
2. The pins PD13, PD14, and PD15 will not be 5V tolerant on all future devices. In order to preserve upgrade options with full hardware compatibility, do not use these pins with 5V domains.
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5.5 EFM32GG11B4xx in BGA120 Device Pinout
EFM32GG11 Family Data Sheet
Pin Definitions
Figure 5.5. EFM32GG11B4xx in BGA120 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 5.20 GPIO Functionality Table or 5.21 Alternate Functionality Overview.
Table 5.5. EFM32GG11B4xx in BGA120 Device Pinout
Pin Name PE15 PE12 PD11 PF7 PF4
VREGI
Pin(s) Description A1 GPIO A3 GPIO A5 GPIO A7 GPIO A9 GPIO
A11 Input to 5 V regulator.
Pin Name PE14 PE9 PD9 PF5 PF2
VREGO
Pin(s) Description
A2 GPIO
A4 GPIO
A6 GPIO
A8 GPIO
A10 GPIO
Decoupling for 5 V regulator and reguA12 lator output. Power for USB PHY in
USB-enabled OPNs
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Pin Name PF11 PE13 PE8 PD10 PF6 PF1 VBUS PA1 PE10
VSS
PF9
PF0 PC14 PA3 PB15 PC12 PA6 PA4 PC10 PB0 PB2 PC8 PB3 IOVDD2 PE1 PB5 DVDD PC7
Pin(s) Description
A13 GPIO (5V)
B2 GPIO
B4 GPIO
B6 GPIO
B8 GPIO
B10 GPIO (5V)
B12
USB VBUS signal and auxiliary input to 5 V regulator.
C1 GPIO
C3 GPIO
C5 C8 H3 J3 K11 K12 Ground L5 L6 M8 M11 N8
Pin Name PA15 PE11 PD12 PF8 PF3 PF12 PF10 PA0 PD13
IOVDD1
C7 GPIO
IOVDD0
C10 GPIO (5V) C12 GPIO (5V) D1 GPIO D3 GPIO (5V) D12 GPIO (5V) E1 GPIO E3 GPIO E12 GPIO (5V) F1 GPIO F3 GPIO F12 GPIO (5V) G1 GPIO G3 Digital IO power supply 2. G12 GPIO (5V) H1 GPIO H11 Digital power supply. H13 GPIO
PE4 PC15 PA2 PE5 PC13 PA5 PE6 PC11 PB1 PE7 PC9 PB4 PE0 PE3 PB6 PE2 PD14
EFM32GG11 Family Data Sheet
Pin Definitions
Pin(s) Description B1 GPIO B3 GPIO B5 GPIO B7 GPIO B9 GPIO B11 GPIO
B13 GPIO (5V)
C2 GPIO C4 GPIO (5V)
C6 Digital IO power supply 1.
C9 J11 K3 Digital IO power supply 0. L4 L7 C11 GPIO C13 GPIO (5V) D2 GPIO D11 GPIO D13 GPIO (5V) E2 GPIO E11 GPIO E13 GPIO (5V) F2 GPIO F11 GPIO F13 GPIO (5V) G2 GPIO G11 GPIO (5V) G13 GPIO H2 GPIO H12 GPIO J1 GPIO (5V)
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EFM32GG11 Family Data Sheet
Pin Definitions
Pin Name
Pin(s) Description
Pin Name
Pin(s) Description
PD15
J2 GPIO (5V)
PC6
J12 GPIO
DECOUPLE
Decouple output for on-chip voltage J13 regulator. An external decoupling ca-
pacitor is required at this pin.
PC0
K1 GPIO (5V)
PC1
K2 GPIO (5V)
PD8
K13 GPIO
PC2
L1 GPIO (5V)
PC3
L2 GPIO (5V)
PA7
L3 GPIO
PB9
L8 GPIO (5V)
PB10
L9 GPIO (5V)
PD0
L10 GPIO (5V)
PD1
L11 GPIO
PD4
L12 GPIO
PD7
L13 GPIO
PB7
M1 GPIO
PC4
M2 GPIO
PA8
M3 GPIO
PA10
M4 GPIO
PA13
M5 GPIO (5V)
PA14
M6 GPIO
RESETn
Reset input, active low. To apply an external reset source to this pin, it is reM7 quired to only drive this pin low during reset, and let the internal pull-up ensure that reset is released.
AVDD
M9 M10 Analog power supply. N11
PD3
M12 GPIO
PD6
M13 GPIO
PB8
N1 GPIO
PC5
N2 GPIO
PA9
N3 GPIO
PA11
N4 GPIO
PA12
N5 GPIO (5V)
PB11
N6 GPIO
PB12
N7 GPIO
PB13
N9 GPIO
PB14
N10 GPIO
PD2
N12 GPIO (5V)
PD5
N13 GPIO
Note:
1. GPIO with 5V tolerance are indicated by (5V).
2. The pins PD13, PD14, and PD15 will not be 5V tolerant on all future devices. In order to preserve upgrade options with full hardware compatibility, do not use these pins with 5V domains.
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5.6 EFM32GG11B4xx in BGA112 Device Pinout
EFM32GG11 Family Data Sheet
Pin Definitions
Figure 5.6. EFM32GG11B4xx in BGA112 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 5.20 GPIO Functionality Table or 5.21 Alternate Functionality Overview.
Table 5.6. EFM32GG11B4xx in BGA112 Device Pinout
Pin Name PE15 PE12 PD10 PF5 PE4 PF11 PE13
Pin(s) Description A1 GPIO A3 GPIO A5 GPIO A7 GPIO A9 GPIO A11 GPIO (5V) B2 GPIO
Pin Name PE14 PE9 PF7 PF12 PF10 PA15 PE11
Pin(s) Description A2 GPIO A4 GPIO A6 GPIO A8 GPIO A10 GPIO (5V) B1 GPIO B3 GPIO
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Pin Name PE8 PF8 VBUS
VREGI
PA1 PE10 PD12
VSS
PE6 PC11 PA2 IOVDD1
IOVDD0
PE7 PC9 PA5 PB0 PE0 PE3 PB2 PB4
PE2
PB5 IOVDD2
PC7 PC2 PA7
EFM32GG11 Family Data Sheet
Pin Definitions
Pin(s) Description
B4 GPIO
B6 GPIO
B8
USB VBUS signal and auxiliary input to 5 V regulator.
B10 Input to 5 V regulator.
C1 GPIO
C3 GPIO
C5 GPIO
C7
D4
F9
G3
G9 H6
Ground
K4
K7
K10
L7
C9 GPIO
C11 GPIO (5V)
D2 GPIO
D5 Digital IO power supply 1.
D7
G8 H7
Digital IO power supply 0.
L4
D9 GPIO
D11 GPIO (5V)
E2 GPIO
E4 GPIO
E9 GPIO (5V)
E11 GPIO
F2 GPIO
F4 GPIO
F10 GPIO
G1 GPIO G4 Digital IO power supply 2. G11 GPIO H2 GPIO (5V) H4 GPIO
Pin Name PD11 PF6 PE5
VREGO
PA0 PD13 PF9
PF2
PC10 PA3 PB15 PD9
PF1
PC8 PA6 PA4 PF0 PE1 PB1 PB3 DVDD
DECOUPLE
PB6 PC6 PC0 PD14 PA8
Pin(s) Description B5 GPIO B7 GPIO B9 GPIO Decoupling for 5 V regulator and reguB11 lator output. Power for USB PHY in USB-enabled OPNs C2 GPIO C4 GPIO (5V) C6 GPIO
C8 GPIO
C10 GPIO (5V) D1 GPIO D3 GPIO (5V) D6 GPIO
D8 GPIO (5V)
D10 GPIO (5V) E1 GPIO E3 GPIO E8 GPIO (5V) E10 GPIO (5V) F1 GPIO F3 GPIO F8 Digital power supply.
Decouple output for on-chip voltage F11 regulator. An external decoupling ca-
pacitor is required at this pin. G2 GPIO G10 GPIO H1 GPIO (5V) H3 GPIO (5V) H5 GPIO
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EFM32GG11 Family Data Sheet
Pin Definitions
Pin Name
Pin(s) Description
Pin Name
Pin(s) Description
PD8
H8 GPIO
PD5
H9 GPIO
PD6
H10 GPIO
PD7
H11 GPIO
PC1
J1 GPIO (5V)
PC3
J2 GPIO (5V)
PD15
J3 GPIO (5V)
PA12
J4 GPIO (5V)
PA9
J5 GPIO
PA10
J6 GPIO
PB9
J7 GPIO (5V)
PB10
J8 GPIO (5V)
PD2
J9 GPIO (5V)
PD3
J10 GPIO
PD4
J11 GPIO
PB7
K1 GPIO
PC4
K2 GPIO
PA13
K3 GPIO (5V)
PA11
K5 GPIO
RESETn
Reset input, active low. To apply an external reset source to this pin, it is reK6 quired to only drive this pin low during reset, and let the internal pull-up ensure that reset is released.
AVDD
K8 K9 Analog power supply. L10
PD1
K11 GPIO
PB8
L1 GPIO
PC5
L2 GPIO
PA14
L3 GPIO
PB11
L5 GPIO
PB12
L6 GPIO
PB13
L8 GPIO
PB14
L9 GPIO
PD0
L11 GPIO (5V)
Note:
1. GPIO with 5V tolerance are indicated by (5V).
2. The pins PD13, PD14, and PD15 will not be 5V tolerant on all future devices. In order to preserve upgrade options with full hardware compatibility, do not use these pins with 5V domains.
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5.7 EFM32GG11B3xx in BGA112 Device Pinout
EFM32GG11 Family Data Sheet
Pin Definitions
Figure 5.7. EFM32GG11B3xx in BGA112 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 5.20 GPIO Functionality Table or 5.21 Alternate Functionality Overview.
Table 5.7. EFM32GG11B3xx in BGA112 Device Pinout
Pin Name PE15 PE12 PD10 PF5 PE4 PC15 PE13
Pin(s) Description A1 GPIO A3 GPIO A5 GPIO A7 GPIO A9 GPIO A11 GPIO (5V) B2 GPIO
Pin Name PE14 PE9 PF7 PF4 PC14 PA15 PE11
Pin(s) Description A2 GPIO A4 GPIO A6 GPIO A8 GPIO A10 GPIO (5V) B1 GPIO B3 GPIO
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Pin Name PE8 PF8 PF3 PC12 PA1 PE10 PD12
VSS
PE6 PC11 PA2 IOVDD1
IOVDD0
PE7 PC9 PA5 PB0 PE0 PE3 PB2 PB4
Pin(s) Description
B4 GPIO
B6 GPIO
B8 GPIO
B10 GPIO (5V)
C1 GPIO
C3 GPIO
C5 GPIO
C7
D4
F9
G3
G9 H6
Ground
K4
K7
K10
L7
C9 GPIO
C11 GPIO (5V)
D2 GPIO
D5 Digital IO power supply 1.
D7
G8 H7
Digital IO power supply 0.
L4
D9 GPIO
D11 GPIO (5V)
E2 GPIO
E4 GPIO
E9 GPIO (5V)
E11 GPIO
F2 GPIO
F4 GPIO
PE2
F10 GPIO
PB5 IOVDD2
PC7 PC2 PA7 PD8 PD6
G1 GPIO G4 Digital IO power supply 2. G11 GPIO H2 GPIO (5V) H4 GPIO H8 GPIO H10 GPIO
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Pin Name PD11 PF6 PE5 PC13 PA0 PD13 PF9
EFM32GG11 Family Data Sheet
Pin Definitions
Pin(s) Description B5 GPIO B7 GPIO B9 GPIO B11 GPIO (5V) C2 GPIO C4 GPIO (5V) C6 GPIO
PF2
C8 GPIO
PC10 PA3 PB15 PD9
C10 GPIO (5V) D1 GPIO D3 GPIO (5V) D6 GPIO
PF1
D8 GPIO (5V)
PC8 PA6 PA4 PF0 PE1 PB1 PB3 DVDD
DECOUPLE
PB6 PC6 PC0 PD14 PA8 PD5 PD7
D10 GPIO (5V) E1 GPIO E3 GPIO E8 GPIO (5V) E10 GPIO (5V) F1 GPIO F3 GPIO F8 Digital power supply.
Decouple output for on-chip voltage F11 regulator. An external decoupling ca-
pacitor is required at this pin. G2 GPIO G10 GPIO H1 GPIO (5V) H3 GPIO (5V) H5 GPIO H9 GPIO H11 GPIO
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EFM32GG11 Family Data Sheet
Pin Definitions
Pin Name
Pin(s) Description
Pin Name
Pin(s) Description
PC1
J1 GPIO (5V)
PC3
J2 GPIO (5V)
PD15
J3 GPIO (5V)
PA12
J4 GPIO (5V)
PA9
J5 GPIO
PA10
J6 GPIO
PB9
J7 GPIO (5V)
PB10
J8 GPIO (5V)
PD2
J9 GPIO (5V)
PD3
J10 GPIO
PD4
J11 GPIO
PB7
K1 GPIO
PC4
K2 GPIO
PA13
K3 GPIO (5V)
PA11
K5 GPIO
RESETn
Reset input, active low. To apply an external reset source to this pin, it is reK6 quired to only drive this pin low during reset, and let the internal pull-up ensure that reset is released.
AVDD
K8 K9 Analog power supply. L10
PD1
K11 GPIO
PB8
L1 GPIO
PC5
L2 GPIO
PA14
L3 GPIO
PB11
L5 GPIO
PB12
L6 GPIO
PB13
L8 GPIO
PB14
L9 GPIO
PD0
L11 GPIO (5V)
Note:
1. GPIO with 5V tolerance are indicated by (5V).
2. The pins PD13, PD14, and PD15 will not be 5V tolerant on all future devices. In order to preserve upgrade options with full hardware compatibility, do not use these pins with 5V domains.
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5.8 EFM32GG11B8xx in QFP100 Device Pinout
EFM32GG11 Family Data Sheet
Pin Definitions
Figure 5.8. EFM32GG11B8xx in QFP100 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 5.20 GPIO Functionality Table or 5.21 Alternate Functionality Overview.
Table 5.8. EFM32GG11B8xx in QFP100 Device Pinout
Pin Name PA0 PA2 PA4
Pin(s) Description 1 GPIO 3 GPIO 5 GPIO
PA6
7 GPIO
PB0
9 GPIO
Pin Name PA1 PA3 PA5
IOVDD0
PB1
Pin(s) Description
2 GPIO
4 GPIO
6 GPIO
8 17 31 Digital IO power supply 0. 44 82
10 GPIO
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EFM32GG11 Family Data Sheet
Pin Definitions
Pin Name PB2 PB4
Pin(s) Description 11 GPIO 13 GPIO
Pin Name PB3 PB5
PB6
15 GPIO
VSS
PC0 PC2 PC4 PB7 PA7 PA9 PA11 PA13
RESETn
PB10 PB12 PB13 PD0 PD2 PD4 PD6 PD8 VREGVSS VREGVDD
DECOUPLE
PE2 PE4 PE6 PC8 PC10
18 GPIO (5V) 20 GPIO (5V) 22 GPIO 24 GPIO 26 GPIO 28 GPIO 30 GPIO 34 GPIO (5V)
Reset input, active low. To apply an external reset source to this pin, it is re36 quired to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. 38 GPIO (5V) 40 GPIO 42 GPIO 45 GPIO (5V) 47 GPIO (5V) 49 GPIO 51 GPIO 53 GPIO 55 Voltage regulator VSS 57 Voltage regulator VDD input Decouple output for on-chip voltage 60 regulator. An external decoupling capacitor is required at this pin. 62 GPIO 64 GPIO 66 GPIO 68 GPIO (5V) 70 GPIO (5V)
PC1 PC3 PC5 PB8 PA8 PA10 PA12 PA14
PB9
PB11 AVDD PB14 PD1 PD3 PD5 PD7 PC7 VREGSW DVDD
PE1
PE3 PE5 PE7 PC9 PC11
VREGI
72 Input to 5 V regulator.
VREGO
PF10 PF0
74 GPIO (5V) 76 GPIO (5V)
PF11 PF1
Pin(s) Description
12 GPIO
14 GPIO
16
32 59
Ground
83
19 GPIO (5V)
21 GPIO (5V)
23 GPIO
25 GPIO
27 GPIO
29 GPIO
33 GPIO (5V)
35 GPIO
37 GPIO (5V)
39 GPIO 41 Analog power supply. 43 GPIO 46 GPIO 48 GPIO 50 GPIO 52 GPIO 54 GPIO 56 DCDC regulator switching node 58 Digital power supply.
61 GPIO (5V)
63 GPIO 65 GPIO 67 GPIO 69 GPIO (5V) 71 GPIO (5V)
Decoupling for 5 V regulator and regu73 lator output. Power for USB PHY in
USB-enabled OPNs 75 GPIO (5V) 77 GPIO (5V)
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Pin Name
Pin(s) Description
PF2
78 GPIO
PF12
80 GPIO
PF6
84 GPIO
PF8
86 GPIO
PD9
88 GPIO
PD11
90 GPIO
PE8
92 GPIO
PE10
94 GPIO
PE12
96 GPIO
PE14
98 GPIO
PA15
100 GPIO
Note: 1. GPIO with 5V tolerance are indicated by (5V).
Pin Name
VBUS
PF5 PF7 PF9 PD10 PD12 PE9 PE11 PE13 PE15
EFM32GG11 Family Data Sheet
Pin Definitions
Pin(s) Description
79
USB VBUS signal and auxiliary input to 5 V regulator.
81 GPIO
85 GPIO
87 GPIO
89 GPIO
91 GPIO
93 GPIO
95 GPIO
97 GPIO
99 GPIO
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5.9 EFM32GG11B5xx in QFP100 Device Pinout
EFM32GG11 Family Data Sheet
Pin Definitions
Figure 5.9. EFM32GG11B5xx in QFP100 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 5.20 GPIO Functionality Table or 5.21 Alternate Functionality Overview.
Table 5.9. EFM32GG11B5xx in QFP100 Device Pinout
Pin Name PA0 PA2 PA4
Pin(s) Description 1 GPIO 3 GPIO 5 GPIO
PA6
7 GPIO
PB0
9 GPIO
Pin Name PA1 PA3 PA5
IOVDD0
PB1
Pin(s) Description
2 GPIO
4 GPIO
6 GPIO
8 17 31 Digital IO power supply 0. 44 82
10 GPIO
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EFM32GG11 Family Data Sheet
Pin Definitions
Pin Name PB2 PB4
Pin(s) Description 11 GPIO 13 GPIO
Pin Name PB3 PB5
PB6
15 GPIO
VSS
PC0 PC2 PC4 PB7 PA7 PA9 PA11 PA13
RESETn
PB10 PB12 PB13 PD0 PD2 PD4 PD6 PD8 VREGVSS VREGVDD
DECOUPLE
PE2 PE4 PE6 PC8 PC10
18 GPIO (5V) 20 GPIO (5V) 22 GPIO 24 GPIO 26 GPIO 28 GPIO 30 GPIO 34 GPIO (5V)
Reset input, active low. To apply an external reset source to this pin, it is re36 quired to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. 38 GPIO (5V) 40 GPIO 42 GPIO 45 GPIO (5V) 47 GPIO (5V) 49 GPIO 51 GPIO 53 GPIO 55 Voltage regulator VSS 57 Voltage regulator VDD input Decouple output for on-chip voltage 60 regulator. An external decoupling capacitor is required at this pin. 62 GPIO 64 GPIO 66 GPIO 68 GPIO (5V) 70 GPIO (5V)
PC1 PC3 PC5 PB8 PA8 PA10 PA12 PA14
PB9
PB11 AVDD PB14 PD1 PD3 PD5 PD7 PC7 VREGSW DVDD
PE1
PE3 PE5 PE7 PC9 PC11
VREGI
72 Input to 5 V regulator.
VREGO
PF10 PF0
74 GPIO (5V) 76 GPIO (5V)
PF11 PF1
Pin(s) Description
12 GPIO
14 GPIO
16
32 59
Ground
83
19 GPIO (5V)
21 GPIO (5V)
23 GPIO
25 GPIO
27 GPIO
29 GPIO
33 GPIO (5V)
35 GPIO
37 GPIO (5V)
39 GPIO 41 Analog power supply. 43 GPIO 46 GPIO 48 GPIO 50 GPIO 52 GPIO 54 GPIO 56 DCDC regulator switching node 58 Digital power supply.
61 GPIO (5V)
63 GPIO 65 GPIO 67 GPIO 69 GPIO (5V) 71 GPIO (5V)
Decoupling for 5 V regulator and regu73 lator output. Power for USB PHY in
USB-enabled OPNs 75 GPIO (5V) 77 GPIO (5V)
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Pin Name
Pin(s) Description
PF2
78 GPIO
PF12
80 GPIO
PF6
84 GPIO
PF8
86 GPIO
PD9
88 GPIO
PD11
90 GPIO
PE8
92 GPIO
PE10
94 GPIO
PE12
96 GPIO
PE14
98 GPIO
PA15
100 GPIO
Note: 1. GPIO with 5V tolerance are indicated by (5V).
Pin Name NC PF5 PF7 PF9
PD10 PD12 PE9 PE11 PE13 PE15
EFM32GG11 Family Data Sheet
Pin Definitions
Pin(s) Description 79 No Connect. 81 GPIO 85 GPIO 87 GPIO 89 GPIO 91 GPIO 93 GPIO 95 GPIO 97 GPIO 99 GPIO
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5.10 EFM32GG11B4xx in QFP100 Device Pinout
EFM32GG11 Family Data Sheet
Pin Definitions
Figure 5.10. EFM32GG11B4xx in QFP100 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 5.20 GPIO Functionality Table or 5.21 Alternate Functionality Overview.
Table 5.10. EFM32GG11B4xx in QFP100 Device Pinout
Pin Name PA0 PA2 PA4
Pin(s) Description 1 GPIO 3 GPIO 5 GPIO
PA6
7 GPIO
PB0
9 GPIO
Pin Name PA1 PA3 PA5
IOVDD0
PB1
Pin(s) Description
2 GPIO
4 GPIO
6 GPIO
8 17 31 Digital IO power supply 0. 44 82
10 GPIO
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Pin Name PB2 PB4
Pin(s) Description 11 GPIO 13 GPIO
Pin Name PB3 PB5
PB6
15 GPIO
VSS
PC0 PC2 PC4 PB7 PA7 PA9 PA11 PA13
RESETn
PB10 PB12 PB13 PD0 PD2 PD4 PD6 PD8 PC7
DECOUPLE
PE1 PE3 PE5 PE7 PC9 PC11
VREGO
PF11
18 GPIO (5V) 20 GPIO (5V) 22 GPIO 24 GPIO 26 GPIO 28 GPIO 30 GPIO 34 GPIO (5V)
Reset input, active low. To apply an external reset source to this pin, it is re36 quired to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. 38 GPIO (5V)
40 GPIO
42 GPIO 46 GPIO (5V) 48 GPIO (5V) 50 GPIO 52 GPIO 54 GPIO 56 GPIO
Decouple output for on-chip voltage 59 regulator. An external decoupling ca-
pacitor is required at this pin. 61 GPIO (5V) 63 GPIO 65 GPIO 67 GPIO 69 GPIO (5V) 71 GPIO (5V)
Decoupling for 5 V regulator and regu73 lator output. Power for USB PHY in
USB-enabled OPNs 75 GPIO (5V)
PC1 PC3 PC5 PB8 PA8 PA10 PA12 PA14
PB9
PB11 AVDD PB14 PD1 PD3 PD5 PD7 PC6 DVDD
PE0
PE2 PE4 PE6 PC8 PC10 VREGI
PF10
PF0
EFM32GG11 Family Data Sheet
Pin Definitions
Pin(s) Description
12 GPIO
14 GPIO
16
32 58
Ground
83
19 GPIO (5V)
21 GPIO (5V)
23 GPIO
25 GPIO
27 GPIO
29 GPIO
33 GPIO (5V)
35 GPIO
37 GPIO (5V)
39 GPIO
41 45
Analog power supply.
43 GPIO
47 GPIO
49 GPIO
51 GPIO
53 GPIO
55 GPIO
57 Digital power supply.
60 GPIO (5V)
62 GPIO 64 GPIO 66 GPIO 68 GPIO (5V) 70 GPIO (5V) 72 Input to 5 V regulator.
74 GPIO (5V)
76 GPIO (5V)
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Pin Name
Pin(s) Description
PF1
77 GPIO (5V)
VBUS
79
USB VBUS signal and auxiliary input to 5 V regulator.
PF5
81 GPIO
PF7
85 GPIO
PF9
87 GPIO
PD10
89 GPIO
PD12
91 GPIO
PE9
93 GPIO
PE11
95 GPIO
PE13
97 GPIO
PE15
99 GPIO
Note: 1. GPIO with 5V tolerance are indicated by (5V).
Pin Name PF2
PF12
PF6 PF8 PD9 PD11 PE8 PE10 PE12 PE14 PA15
EFM32GG11 Family Data Sheet
Pin Definitions
Pin(s) Description 78 GPIO
80 GPIO
84 GPIO 86 GPIO 88 GPIO 90 GPIO 92 GPIO 94 GPIO 96 GPIO 98 GPIO 100 GPIO
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5.11 EFM32GG11B3xx in QFP100 Device Pinout
EFM32GG11 Family Data Sheet
Pin Definitions
Figure 5.11. EFM32GG11B3xx in QFP100 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 5.20 GPIO Functionality Table or 5.21 Alternate Functionality Overview.
Table 5.11. EFM32GG11B3xx in QFP100 Device Pinout
Pin Name PA0 PA2 PA4
Pin(s) Description 1 GPIO 3 GPIO 5 GPIO
PA6
7 GPIO
PB0
9 GPIO
Pin Name PA1 PA3 PA5
IOVDD0
PB1
Pin(s) Description
2 GPIO
4 GPIO
6 GPIO
8 17 31 Digital IO power supply 0. 44 82
10 GPIO
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Pin Name PB2 PB4
Pin(s) Description 11 GPIO 13 GPIO
Pin Name PB3 PB5
PB6
15 GPIO
VSS
PC0 PC2 PC4 PB7 PA7 PA9 PA11 PA13
RESETn
PB10 PB12 PB13 PD0 PD2 PD4 PD6 PD8 PC7
DECOUPLE
PE1 PE3 PE5 PE7 PC9 PC11 PC13 PC15 PF1
18 GPIO (5V) 20 GPIO (5V) 22 GPIO 24 GPIO 26 GPIO 28 GPIO 30 GPIO 34 GPIO (5V)
Reset input, active low. To apply an external reset source to this pin, it is re36 quired to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. 38 GPIO (5V)
40 GPIO
42 GPIO 46 GPIO (5V) 48 GPIO (5V) 50 GPIO 52 GPIO 54 GPIO 56 GPIO
Decouple output for on-chip voltage 59 regulator. An external decoupling ca-
pacitor is required at this pin. 61 GPIO (5V) 63 GPIO 65 GPIO 67 GPIO 69 GPIO (5V) 71 GPIO (5V) 73 GPIO (5V) 75 GPIO (5V) 77 GPIO (5V)
PC1 PC3 PC5 PB8 PA8 PA10 PA12 PA14
PB9
PB11 AVDD PB14 PD1 PD3 PD5 PD7 PC6 DVDD
PE0
PE2 PE4 PE6 PC8 PC10 PC12 PC14 PF0 PF2
EFM32GG11 Family Data Sheet
Pin Definitions
Pin(s) Description
12 GPIO
14 GPIO
16
32 58
Ground
83
19 GPIO (5V)
21 GPIO (5V)
23 GPIO
25 GPIO
27 GPIO
29 GPIO
33 GPIO (5V)
35 GPIO
37 GPIO (5V)
39 GPIO
41 45
Analog power supply.
43 GPIO
47 GPIO
49 GPIO
51 GPIO
53 GPIO
55 GPIO
57 Digital power supply.
60 GPIO (5V)
62 GPIO 64 GPIO 66 GPIO 68 GPIO (5V) 70 GPIO (5V) 72 GPIO (5V) 74 GPIO (5V) 76 GPIO (5V) 78 GPIO
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Pin Name
Pin(s) Description
PF3
79 GPIO
PF5
81 GPIO
PF7
85 GPIO
PF9
87 GPIO
PD10
89 GPIO
PD12
91 GPIO
PE9
93 GPIO
PE11
95 GPIO
PE13
97 GPIO
PE15
99 GPIO
Note: 1. GPIO with 5V tolerance are indicated by (5V).
Pin Name PF4 PF6 PF8 PD9 PD11 PE8 PE10 PE12 PE14 PA15
EFM32GG11 Family Data Sheet
Pin Definitions
Pin(s) Description 80 GPIO 84 GPIO 86 GPIO 88 GPIO 90 GPIO 92 GPIO 94 GPIO 96 GPIO 98 GPIO 100 GPIO
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5.12 EFM32GG11B8xx in QFP64 Device Pinout
EFM32GG11 Family Data Sheet
Pin Definitions
Figure 5.12. EFM32GG11B8xx in QFP64 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 5.20 GPIO Functionality Table or 5.21 Alternate Functionality Overview.
Table 5.12. EFM32GG11B8xx in QFP64 Device Pinout
Pin Name PA0 PA2 PA4
IOVDD0
PB3 PB5
Pin(s) Description
1 GPIO
3 GPIO
5 GPIO
7 27 Digital IO power supply 0. 55
9 GPIO
11 GPIO
Pin Name PA1 PA3 PA5
VSS
PB4 PB6
Pin(s) Description
2 GPIO
4 GPIO
6 GPIO
8 23 Ground 56
10 GPIO
12 GPIO
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Pin Name PC4 PB7 PA8
Pin(s) Description 13 GPIO 15 GPIO 17 GPIO
PA14
19 GPIO
PB11 AVDD PB14 PD1 PD3 PD5 PD8 VREGSW
21 GPIO 24 Analog power supply. 26 GPIO 29 GPIO 31 GPIO 33 GPIO 35 GPIO 37 DCDC regulator switching node
DVDD
39 Digital power supply.
PE4
41 GPIO
PE6
43 GPIO
VREGI
45 Input to 5 V regulator.
PF10 PF0
47 GPIO (5V) 49 GPIO (5V)
PF2
51 GPIO
PF12
53 GPIO
PE8
57 GPIO
PE10
59 GPIO
PE12
61 GPIO
PE14
63 GPIO
Note: 1. GPIO with 5V tolerance are indicated by (5V).
EFM32GG11 Family Data Sheet
Pin Definitions
Pin Name PC5 PB8 PA12
RESETn
PB12 PB13 PD0 PD2 PD4 PD6 VREGVSS VREGVDD
DECOUPLE
PE5 PE7
VREGO
PF11 PF1 VBUS PF5 PE9 PE11 PE13 PE15
Pin(s) Description
14 GPIO
16 GPIO
18 GPIO (5V)
Reset input, active low. To apply an external reset source to this pin, it is re20 quired to only drive this pin low during reset, and let the internal pull-up ensure that reset is released.
22 GPIO
25 GPIO
28 GPIO (5V)
30 GPIO (5V)
32 GPIO
34 GPIO
36 Voltage regulator VSS
38 Voltage regulator VDD input
Decouple output for on-chip voltage 40 regulator. An external decoupling ca-
pacitor is required at this pin.
42 GPIO
44 GPIO
Decoupling for 5 V regulator and regu46 lator output. Power for USB PHY in
USB-enabled OPNs
48 GPIO (5V)
50 GPIO (5V)
52
USB VBUS signal and auxiliary input to 5 V regulator.
54 GPIO
58 GPIO
60 GPIO
62 GPIO
64 GPIO
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5.13 EFM32GG11B5xx in QFP64 Device Pinout
EFM32GG11 Family Data Sheet
Pin Definitions
Figure 5.13. EFM32GG11B5xx in QFP64 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 5.20 GPIO Functionality Table or 5.21 Alternate Functionality Overview.
Table 5.13. EFM32GG11B5xx in QFP64 Device Pinout
Pin Name PA0 PA2 PA4
IOVDD0
PB3 PB5
Pin(s) Description
1 GPIO
3 GPIO
5 GPIO
7 27 Digital IO power supply 0. 55
9 GPIO
11 GPIO
Pin Name PA1 PA3 PA5
VSS
PB4 PB6
Pin(s) Description
2 GPIO
4 GPIO
6 GPIO
8 23 Ground 56
10 GPIO
12 GPIO
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Pin Name PC4 PB7 PA8
Pin(s) Description 13 GPIO 15 GPIO 17 GPIO
PA14
19 GPIO
PB11 AVDD PB14 PD1 PD3 PD5 PD7 PC7 VREGSW
21 GPIO 24 Analog power supply. 26 GPIO 29 GPIO 31 GPIO 33 GPIO 35 GPIO 37 GPIO 39 DCDC regulator switching node
DVDD
41 Digital power supply.
PE4
43 GPIO
PE6
45 GPIO
PC12
47 GPIO (5V)
PF0
49 GPIO (5V)
PF2
51 GPIO
PF4
53 GPIO
PE8
57 GPIO
PE10
59 GPIO
PE12
61 GPIO
PE14
63 GPIO
Note: 1. GPIO with 5V tolerance are indicated by (5V).
EFM32GG11 Family Data Sheet
Pin Definitions
Pin Name PC5 PB8 PA12
RESETn
PB12 PB13 PD0 PD2 PD4 PD6 PD8 VREGVSS VREGVDD
DECOUPLE
PE5 PE7 PC13 PF1 PF3 PF5 PE9 PE11 PE13 PE15
Pin(s) Description 14 GPIO 16 GPIO 18 GPIO (5V) Reset input, active low. To apply an external reset source to this pin, it is re20 quired to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. 22 GPIO 25 GPIO 28 GPIO (5V) 30 GPIO (5V) 32 GPIO 34 GPIO 36 GPIO 38 Voltage regulator VSS 40 Voltage regulator VDD input Decouple output for on-chip voltage 42 regulator. An external decoupling capacitor is required at this pin. 44 GPIO 46 GPIO 48 GPIO (5V) 50 GPIO (5V) 52 GPIO 54 GPIO 58 GPIO 60 GPIO 62 GPIO 64 GPIO
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5.14 EFM32GG11B4xx in QFP64 Device Pinout
EFM32GG11 Family Data Sheet
Pin Definitions
Figure 5.14. EFM32GG11B4xx in QFP64 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 5.20 GPIO Functionality Table or 5.21 Alternate Functionality Overview.
Table 5.14. EFM32GG11B4xx in QFP64 Device Pinout
Pin Name PA0 PA2 PA4
IOVDD0
PB3 PB5
Pin(s) Description
1 GPIO
3 GPIO
5 GPIO
7 26 Digital IO power supply 0. 55
9 GPIO
11 GPIO
Pin Name PA1 PA3 PA5
VSS
PB4 PB6
Pin(s) Description
2 GPIO
4 GPIO
6 GPIO
8 22 Ground 56
10 GPIO
12 GPIO
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Pin Name PC4 PB7 PA12
Pin(s) Description 13 GPIO 15 GPIO 17 GPIO (5V)
PA14
19 GPIO
Pin Name PC5 PB8 PA13
RESETn
PB11
21 GPIO
PB13
24 GPIO
PD0
28 GPIO (5V)
PD2
30 GPIO (5V)
PD4
32 GPIO
PD6
34 GPIO
PD8
36 GPIO
PC7
38 GPIO
DECOUPLE
Decouple output for on-chip voltage 40 regulator. An external decoupling ca-
pacitor is required at this pin.
PE5
42 GPIO
PE7
44 GPIO
VREGO
Decoupling for 5 V regulator and regu46 lator output. Power for USB PHY in
USB-enabled OPNs
PF11
48 GPIO (5V)
PF1
50 GPIO (5V)
VBUS
52
USB VBUS signal and auxiliary input to 5 V regulator.
PF5
54 GPIO
PE9
58 GPIO
PE11
60 GPIO
PE13
62 GPIO
PE15
64 GPIO
Note: 1. GPIO with 5V tolerance are indicated by (5V).
AVDD PB14 PD1 PD3 PD5 PD7 PC6 DVDD
PE4
PE6 VREGI
PF10
PF0 PF2 PF12 PE8 PE10 PE12 PE14
EFM32GG11 Family Data Sheet
Pin Definitions
Pin(s) Description
14 GPIO
16 GPIO
18 GPIO (5V)
Reset input, active low. To apply an external reset source to this pin, it is re20 quired to only drive this pin low during reset, and let the internal pull-up ensure that reset is released.
23 27
Analog power supply.
25 GPIO
29 GPIO
31 GPIO
33 GPIO
35 GPIO
37 GPIO
39 Digital power supply.
41 GPIO
43 GPIO 45 Input to 5 V regulator.
47 GPIO (5V)
49 GPIO (5V) 51 GPIO
53 GPIO
57 GPIO 59 GPIO 61 GPIO 63 GPIO
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5.15 EFM32GG11B1xx in QFP64 Device Pinout
EFM32GG11 Family Data Sheet
Pin Definitions
Figure 5.15. EFM32GG11B1xx in QFP64 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 5.20 GPIO Functionality Table or 5.21 Alternate Functionality Overview.
Table 5.15. EFM32GG11B1xx in QFP64 Device Pinout
Pin Name PA0 PA2 PA4
IOVDD0
PC0 PC2
Pin(s) Description
1 GPIO
3 GPIO
5 GPIO
7 26 Digital IO power supply 0. 55
9 GPIO (5V)
11 GPIO (5V)
Pin Name PA1 PA3 PA5
VSS
PC1 PC3
Pin(s) Description
2 GPIO
4 GPIO
6 GPIO
8 22 Ground 56
10 GPIO (5V)
12 GPIO (5V)
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Pin Name PC4 PB7 PA8
Pin(s) Description 13 GPIO 15 GPIO 17 GPIO
PA10
19 GPIO
PB11
21 GPIO
PB13
24 GPIO
PD0
28 GPIO (5V)
PD2
30 GPIO (5V)
PD4
32 GPIO
PD6
34 GPIO
PD8
36 GPIO
PC7
38 GPIO
DECOUPLE
Decouple output for on-chip voltage 40 regulator. An external decoupling ca-
pacitor is required at this pin.
PC9
42 GPIO (5V)
PC11
44 GPIO (5V)
PC13
46 GPIO (5V)
PC15
48 GPIO (5V)
PF1
50 GPIO (5V)
PF3
52 GPIO
PF5
54 GPIO
PE9
58 GPIO
PE11
60 GPIO
PE13
62 GPIO
PE15
64 GPIO
Note: 1. GPIO with 5V tolerance are indicated by (5V).
Pin Name PC5 PB8 PA9
RESETn
AVDD PB14 PD1 PD3 PD5 PD7 PC6 DVDD
PC8
PC10 PC12 PC14 PF0 PF2 PF4 PE8 PE10 PE12 PE14
EFM32GG11 Family Data Sheet
Pin Definitions
Pin(s) Description
14 GPIO
16 GPIO
18 GPIO
Reset input, active low. To apply an external reset source to this pin, it is re20 quired to only drive this pin low during reset, and let the internal pull-up ensure that reset is released.
23 27
Analog power supply.
25 GPIO
29 GPIO
31 GPIO
33 GPIO
35 GPIO
37 GPIO
39 Digital power supply.
41 GPIO (5V)
43 GPIO (5V) 45 GPIO (5V) 47 GPIO (5V) 49 GPIO (5V) 51 GPIO 53 GPIO 57 GPIO 59 GPIO 61 GPIO 63 GPIO
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5.16 EFM32GG11B8xx in QFN64 Device Pinout
EFM32GG11 Family Data Sheet
Pin Definitions
Figure 5.16. EFM32GG11B8xx in QFN64 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 5.20 GPIO Functionality Table or 5.21 Alternate Functionality Overview.
Table 5.16. EFM32GG11B8xx in QFN64 Device Pinout
Pin Name VSS PA1 PA3 PA5
IOVDD0
PB4
Pin(s) Description
0 Ground
2 GPIO
4 GPIO
6 GPIO
8 27 Digital IO power supply 0. 55
10 GPIO
Pin Name PA0 PA2 PA4 PA6
PB3
PB5
Pin(s) Description 1 GPIO 3 GPIO 5 GPIO 7 GPIO
9 GPIO
11 GPIO
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Pin Name PB6 PC5 PB8 PA12
Pin(s) Description 12 GPIO 14 GPIO 16 GPIO 18 GPIO (5V)
PA14
20 GPIO
PB11 AVDD PB14 PD1 PD3 PD5 PD8 VREGSW
22 GPIO 24 Analog power supply. 26 GPIO 29 GPIO 31 GPIO 33 GPIO 35 GPIO 37 DCDC regulator switching node
DVDD
39 Digital power supply.
PE4
41 GPIO
PE6
43 GPIO
VREGI
45 Input to 5 V regulator.
PF10 PF0
47 GPIO (5V) 49 GPIO (5V)
PF2
51 GPIO
PF12
53 GPIO
PE8
56 GPIO
PE10
58 GPIO
PE12
60 GPIO
PE14
62 GPIO
PA15
64 GPIO
Note: 1. GPIO with 5V tolerance are indicated by (5V).
EFM32GG11 Family Data Sheet
Pin Definitions
Pin Name PC4 PB7 PA8 PA13
RESETn
PB12 PB13 PD0 PD2 PD4 PD6 VREGVSS VREGVDD
DECOUPLE
PE5 PE7
VREGO
PF11 PF1 VBUS PF5 PE9 PE11 PE13 PE15
Pin(s) Description
13 GPIO
15 GPIO
17 GPIO
19 GPIO (5V)
Reset input, active low. To apply an external reset source to this pin, it is re21 quired to only drive this pin low during reset, and let the internal pull-up ensure that reset is released.
23 GPIO
25 GPIO
28 GPIO (5V)
30 GPIO (5V)
32 GPIO
34 GPIO
36 Voltage regulator VSS
38 Voltage regulator VDD input
Decouple output for on-chip voltage 40 regulator. An external decoupling ca-
pacitor is required at this pin.
42 GPIO
44 GPIO
Decoupling for 5 V regulator and regu46 lator output. Power for USB PHY in
USB-enabled OPNs
48 GPIO (5V)
50 GPIO (5V)
52
USB VBUS signal and auxiliary input to 5 V regulator.
54 GPIO
57 GPIO
59 GPIO
61 GPIO
63 GPIO
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5.17 EFM32GG11B5xx in QFN64 Device Pinout
EFM32GG11 Family Data Sheet
Pin Definitions
Figure 5.17. EFM32GG11B5xx in QFN64 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 5.20 GPIO Functionality Table or 5.21 Alternate Functionality Overview.
Table 5.17. EFM32GG11B5xx in QFN64 Device Pinout
Pin Name VSS PA1 PA3 PA5
IOVDD0
PB4
Pin(s) Description
0 Ground
2 GPIO
4 GPIO
6 GPIO
8 27 Digital IO power supply 0. 55
10 GPIO
Pin Name PA0 PA2 PA4 PA6
PB3
PB5
Pin(s) Description 1 GPIO 3 GPIO 5 GPIO 7 GPIO
9 GPIO
11 GPIO
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Pin Name PB6 PC5 PB8 PA12
Pin(s) Description 12 GPIO 14 GPIO 16 GPIO 18 GPIO (5V)
PA14
20 GPIO
PB11 AVDD PB14 PD1 PD3 PD5 PD7 PC7 VREGSW
22 GPIO 24 Analog power supply. 26 GPIO 29 GPIO 31 GPIO 33 GPIO 35 GPIO 37 GPIO 39 DCDC regulator switching node
DVDD
41 Digital power supply.
PE4
43 GPIO
PE6
45 GPIO
PC12
47 GPIO (5V)
PF0
49 GPIO (5V)
PF2
51 GPIO
PF4
53 GPIO
PE8
56 GPIO
PE10
58 GPIO
PE12
60 GPIO
PE14
62 GPIO
PA15
64 GPIO
Note: 1. GPIO with 5V tolerance are indicated by (5V).
EFM32GG11 Family Data Sheet
Pin Definitions
Pin Name PC4 PB7 PA8 PA13
RESETn
PB12 PB13 PD0 PD2 PD4 PD6 PD8 VREGVSS VREGVDD
DECOUPLE
PE5 PE7 PC13 PF1 PF3 PF5 PE9 PE11 PE13 PE15
Pin(s) Description 13 GPIO 15 GPIO 17 GPIO 19 GPIO (5V) Reset input, active low. To apply an external reset source to this pin, it is re21 quired to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. 23 GPIO 25 GPIO 28 GPIO (5V) 30 GPIO (5V) 32 GPIO 34 GPIO 36 GPIO 38 Voltage regulator VSS 40 Voltage regulator VDD input Decouple output for on-chip voltage 42 regulator. An external decoupling capacitor is required at this pin. 44 GPIO 46 GPIO 48 GPIO (5V) 50 GPIO (5V) 52 GPIO 54 GPIO 57 GPIO 59 GPIO 61 GPIO 63 GPIO
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5.18 EFM32GG11B4xx in QFN64 Device Pinout
EFM32GG11 Family Data Sheet
Pin Definitions
Figure 5.18. EFM32GG11B4xx in QFN64 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 5.20 GPIO Functionality Table or 5.21 Alternate Functionality Overview.
Table 5.18. EFM32GG11B4xx in QFN64 Device Pinout
Pin Name VSS PA1 PA3 PA5
IOVDD0
PB4
Pin(s) Description
0 Ground
2 GPIO
4 GPIO
6 GPIO
8 26 Digital IO power supply 0. 55
10 GPIO
Pin Name PA0 PA2 PA4 PA6
PB3
PB5
Pin(s) Description 1 GPIO 3 GPIO 5 GPIO 7 GPIO
9 GPIO
11 GPIO
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Pin Name PB6 PC5 PB8 PA13
RESETn
Pin(s) Description
Pin Name
12 GPIO
PC4
14 GPIO
PB7
16 GPIO
PA12
18 GPIO (5V)
PA14
Reset input, active low. To apply an external reset source to this pin, it is re20 quired to only drive this pin low during reset, and let the internal pull-up ensure that reset is released.
PB11
PB12
22 GPIO
AVDD
PB13
24 GPIO
PD0
28 GPIO (5V)
PD2
30 GPIO (5V)
PD4
32 GPIO
PD6
34 GPIO
PD8
36 GPIO
PC7
38 GPIO
DECOUPLE
Decouple output for on-chip voltage 40 regulator. An external decoupling ca-
pacitor is required at this pin.
PE5
42 GPIO
PE7
44 GPIO
VREGO
Decoupling for 5 V regulator and regu46 lator output. Power for USB PHY in
USB-enabled OPNs
PF11
48 GPIO (5V)
PF1
50 GPIO (5V)
VBUS
52
USB VBUS signal and auxiliary input to 5 V regulator.
PF5
54 GPIO
PE9
57 GPIO
PE11
59 GPIO
PE13
61 GPIO
PE15
63 GPIO
Note: 1. GPIO with 5V tolerance are indicated by (5V).
PB14 PD1 PD3 PD5 PD7 PC6 DVDD
PE4
PE6 VREGI
PF10
PF0 PF2 PF12 PE8 PE10 PE12 PE14 PA15
EFM32GG11 Family Data Sheet
Pin Definitions
Pin(s) Description 13 GPIO 15 GPIO 17 GPIO (5V) 19 GPIO
21 GPIO
23 27
Analog power supply.
25 GPIO
29 GPIO
31 GPIO
33 GPIO
35 GPIO
37 GPIO
39 Digital power supply.
41 GPIO
43 GPIO 45 Input to 5 V regulator.
47 GPIO (5V)
49 GPIO (5V) 51 GPIO
53 GPIO
56 GPIO 58 GPIO 60 GPIO 62 GPIO 64 GPIO
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5.19 EFM32GG11B1xx in QFN64 Device Pinout
EFM32GG11 Family Data Sheet
Pin Definitions
Figure 5.19. EFM32GG11B1xx in QFN64 Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 5.20 GPIO Functionality Table or 5.21 Alternate Functionality Overview.
Table 5.19. EFM32GG11B1xx in QFN64 Device Pinout
Pin Name VSS PA1 PA3 PA5
IOVDD0
PC1
Pin(s) Description
0 Ground
2 GPIO
4 GPIO
6 GPIO
8 26 Digital IO power supply 0. 55
10 GPIO (5V)
Pin Name PA0 PA2 PA4 PA6
PC0
PC2
Pin(s) Description 1 GPIO 3 GPIO 5 GPIO 7 GPIO
9 GPIO (5V)
11 GPIO (5V)
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Pin Name PC3 PC5 PB8 PA9
RESETn
Pin(s) Description
Pin Name
12 GPIO (5V)
PC4
14 GPIO
PB7
16 GPIO
PA8
18 GPIO
PA10
Reset input, active low. To apply an external reset source to this pin, it is re20 quired to only drive this pin low during reset, and let the internal pull-up ensure that reset is released.
PB11
PB12
22 GPIO
AVDD
PB13
24 GPIO
PD0
28 GPIO (5V)
PD2
30 GPIO (5V)
PD4
32 GPIO
PD6
34 GPIO
PD8
36 GPIO
PC7
38 GPIO
DECOUPLE
Decouple output for on-chip voltage 40 regulator. An external decoupling ca-
pacitor is required at this pin.
PC9
42 GPIO (5V)
PC11
44 GPIO (5V)
PC13
46 GPIO (5V)
PC15
48 GPIO (5V)
PF1
50 GPIO (5V)
PF3
52 GPIO
PF5
54 GPIO
PE9
57 GPIO
PE11
59 GPIO
PE13
61 GPIO
PE15
63 GPIO
Note: 1. GPIO with 5V tolerance are indicated by (5V).
PB14 PD1 PD3 PD5 PD7 PC6 DVDD
PC8
PC10 PC12 PC14 PF0 PF2 PF4 PE8 PE10 PE12 PE14 PA15
EFM32GG11 Family Data Sheet
Pin Definitions
Pin(s) Description 13 GPIO 15 GPIO 17 GPIO 19 GPIO
21 GPIO
23 27
Analog power supply.
25 GPIO
29 GPIO
31 GPIO
33 GPIO
35 GPIO
37 GPIO
39 Digital power supply.
41 GPIO (5V)
43 GPIO (5V) 45 GPIO (5V) 47 GPIO (5V) 49 GPIO (5V) 51 GPIO 53 GPIO 56 GPIO 58 GPIO 60 GPIO 62 GPIO 64 GPIO
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EFM32GG11 Family Data Sheet
Pin Definitions
5.20 GPIO Functionality Table
A wide selection of alternate functionality is available for multiplexing to various pins. The following table shows the name of each GPIO pin, followed by the functionality available on that pin. Refer to 5.21 Alternate Functionality Overview for a list of GPIO locations available for each function.
Table 5.20. GPIO Functionality Table
GPIO Name
Analog
PA0
BUSBY BUSAX LCD_SEG13
PA1
BUSAY BUSBX LCD_SEG14
PA2
BUSBY BUSAX LCD_SEG15
PA3
BUSAY BUSBX LCD_SEG16
PA4
BUSBY BUSAX LCD_SEG17
PA5
BUSAY BUSBX LCD_SEG18
PA6
BUSBY BUSAX LCD_SEG19
PA7
BUSAY BUSBX LCD_SEG35
Pin Alternate Functionality / Description
EBI
Timers
Communication
EBI_AD09 #0 EBI_CSTFT #3
TIM0_CC0 #0 TIM0_CC1 #7 TIM3_CC0 #4 PCNT0_S0IN #4
ETH_RMIITXEN #0 ETH_MIITXCLK #0
SDIO_DAT0 #1 US1_RX #5 US3_TX
#0 QSPI0_CS0 #1 LEU0_RX #4 I2C0_SDA #0
EBI_AD10 #0 EBI_DCLK #3
TIM0_CC0 #7 TIM0_CC1 #0 TIM3_CC1 #4 PCNT0_S1IN #4
ETH_RMIIRXD1 #0 ETH_MIITXD3 #0 SDIO_DAT1 #1
US3_RX #0 QSPI0_CS1 #1 I2C0_SCL #0
EBI_AD11 #0 EBI_DTEN #3
TIM0_CC2 #0 TIM3_CC2 #4
ETH_RMIIRXD0 #0 ETH_MIITXD2 #0 SDIO_DAT2 #1
US1_RX #6 US3_CLK #0 QSPI0_DQ0 #1
EBI_AD12 #0 EBI_VSNC #3
TIM0_CDTI0 #0 TIM3_CC0 #5
ETH_RMIIREFCLK #0 ETH_MIITXD1 #0
SDIO_DAT3 #1 US3_CS #0 U0_TX #2 QSPI0_DQ1 #1
EBI_AD13 #0 EBI_HSNC #3
EBI_AD14 #0
EBI_AD15 #0 EBI_AD13 #1 EBI_A01 #3 EBI_CSTFT #0
TIM0_CDTI1 #0 TIM3_CC1 #5
ETH_RMIICRSDV #0 ETH_MIITXD0 #0 SDIO_DAT4 #1
US3_CTS #0 U0_RX #2 QSPI0_DQ2 #1
TIM0_CDTI2 #0 TIM3_CC2 #5 PCNT1_S0IN #0
ETH_RMIIRXER #0 ETH_MIITXEN #0
SDIO_DAT5 #1 US3_RTS #0 U0_CTS #2
QSPI0_DQ3 #1 LEU1_TX #1
TIM3_CC0 #6 WTIM0_CC0 #1 LE-
TIM1_OUT1 #0 PCNT1_S1IN #0
ETH_MIITXER #0 ETH_MDC #3 SDIO_CD #2
US5_TX #1 U0_RTS #2 LEU1_RX #1
TIM0_CC2 #5 LETIM1_OUT0 #0 PCNT1_S0IN #4
US2_TX #2 US4_CTS #0 US5_RX #1
Other
CMU_CLK2 #0 PRS_CH0 #0 PRS_CH3 #3 GPIO_EM4WU0
CMU_CLK1 #0 PRS_CH1 #0
CMU_CLK0 #0 PRS_CH8 #1 ETM_TD0 #3
CMU_CLK2 #1 CMU_CLKI0 #1 CMU_CLK2 #4 LES_ALTEX2 PRS_CH9 #1
ETM_TD1 #3
LES_ALTEX3 PRS_CH16 #0 ETM_TD2 #3
LES_ALTEX4 PRS_CH17 #0 ACMP1_O #7 ETM_TD3 #3
PRS_CH6 #0 ACMP0_O #4 ETM_TCLK #3 GPIO_EM4WU1
PRS_CH7 #1
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GPIO Name PA8 PA9 PA10 PA11 PA12
PA13 PA14 PA15 PB0
PB1 PB2 PB3
EFM32GG11 Family Data Sheet
Pin Definitions
Analog BUSBY BUSAX
LCD_SEG36
BUSAY BUSBX LCD_SEG37
BUSBY BUSAX LCD_SEG38
BUSAY BUSBX LCD_SEG39
BUSBY BUSAX
BUSAY BUSBX
BUSBY BUSAX LCD_BEXT
BUSAY BUSBX LCD_SEG12
BUSBY BUSAX LCD_SEG32
BUSAY BUSBX LCD_SEG33
BUSBY BUSAX LCD_SEG34
BUSAY BUSBX LCD_SEG20 / LCD_COM4
Pin Alternate Functionality / Description
EBI
Timers
Communication
EBI_AD14 #1 EBI_A02 #3 EBI_DCLK #0
TIM2_CC0 #0 TIM0_CC0 #6 LE-
TIM0_OUT0 #6 PCNT1_S1IN #4
US2_RX #2 US4_RTS #0
EBI_AD15 #1 EBI_A03 #3 EBI_DTEN #0
TIM2_CC1 #0 TIM0_CC1 #6 WTIM2_CC0 #0 LETIM0_OUT1 #6
US2_CLK #2
EBI_CS0 #1 EBI_A04 #3 EBI_VSNC #0
TIM2_CC2 #0 TIM0_CC2 #6 WTIM2_CC1 #0
US2_CS #2
EBI_CS1 #1 EBI_A05 #3 EBI_HSNC #0
WTIM2_CC2 #0 LETIM1_OUT0 #1
US2_CTS #2
EBI_CS2 #1 EBI_REn #2 EBI_A00 #0 EBI_A06
#3
TIM2_CC0 #1 WTIM0_CDTI0 #2 WTIM2_CC0 #1 LE-
TIM1_OUT0 #2 PCNT1_S0IN #5
CAN1_RX #5 US0_CLK #5 US2_RTS #2
EBI_WEn #1 EBI_NANDWEn #2 EBI_A01 #0 EBI_A07
#3
TIM0_CC2 #7 TIM2_CC1 #1 WTIM0_CDTI1 #2 WTIM2_CC1 #1 LETIM1_OUT1 #1 PCNT1_S1IN #5
CAN1_TX #5 US0_CS #5 US2_TX
#3
EBI_REn #1 EBI_A02 #0 EBI_A08
#3
TIM2_CC2 #1 WTIM0_CDTI2 #2 WTIM2_CC2 #1 LE-
TIM1_OUT1 #2
US1_TX #6 US2_RX #3 US3_RTS #2
EBI_AD08 #0
TIM3_CC2 #0
ETH_MIIRXCLK #0 ETH_MDIO #3 US2_CLK #3
EBI_AD00 #1 EBI_CS0 #3 EBI_A16 #0
TIM2_CDTI0 #0 TIM1_CC0 #2 TIM3_CC2 #7 WTIM0_CC0 #5 PCNT0_S0IN #5 PCNT1_S1IN #2
LEU1_TX #3
EBI_AD01 #1 EBI_CS1 #3 EBI_A17 #0
TIM2_CDTI1 #0 TIM1_CC1 #2 WTIM0_CC1 #5 LETIM1_OUT1 #5 PCNT0_S1IN #5
ETH_MIICRS #0 US5_RX #2 LEU1_RX #3
EBI_AD02 #1 EBI_CS2 #3 EBI_A18 #0
TIM2_CDTI2 #0 TIM1_CC2 #2 WTIM0_CC2 #5 LETIM1_OUT0 #5
ETH_MIICOL #0 US1_CS #6
EBI_AD03 #1 EBI_CS3 #3 EBI_A19 #0
TIM1_CC3 #2 WTIM0_CC0 #6 PCNT1_S0IN #1
ETH_MIICRS #2 ETH_MDIO #0 SDIO_DAT6 #1 US2_TX #1 US3_TX #2 QSPI0_DQ4 #1
Other PRS_CH8 #0
PRS_CH9 #0
PRS_CH10 #0 PRS_CH11 #0 CMU_CLK0 #5 PRS_CH12 #0 ACMP1_O #3
PRS_CH13 #0
PRS_CH14 #0 ACMP1_O #4 PRS_CH15 #0
PRS_CH4 #1 ACMP0_O #5
PRS_CH5 #1
PRS_CH18 #0 ACMP0_O #6
PRS_CH19 #0 ACMP0_O #7
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GPIO Name PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14
EFM32GG11 Family Data Sheet
Pin Definitions
Analog
BUSBY BUSAX LCD_SEG21 / LCD_COM5
BUSAY BUSBX LCD_SEG22 / LCD_COM6
BUSBY BUSAX LCD_SEG23 / LCD_COM7
LFXTAL_P
LFXTAL_N
BUSAY BUSBX
BUSBY BUSAX
BUSAY BUSBX VDAC0_OUT0 /
OPA0_OUT IDAC0_OUT
BUSBY BUSAX VDAC0_OUT1 /
OPA1_OUT
BUSAY BUSBX HFXTAL_P
BUSBY BUSAX HFXTAL_N
Pin Alternate Functionality / Description
EBI
Timers
Communication
EBI_AD04 #1 EBI_ARDY #3 EBI_A20 #0
WTIM0_CC1 #6 PCNT1_S1IN #1
ETH_MIICOL #2 ETH_MDC #0 SDIO_DAT7 #1 US2_RX #1 QSPI0_DQ5 #1 LEU1_TX #4
EBI_AD05 #1
WTIM0_CC2 #6 LE-
EBI_ALE #3 EBI_A21 TIM1_OUT0 #4
#0
PCNT0_S0IN #6
ETH_TSUEXTCLK #0 US0_RTS #4 US2_CLK #1 QSPI0_DQ6 #1 LEU1_RX #4
EBI_AD06 #1 EBI_WEn #3 EBI_A22 #0
TIM0_CC0 #3 TIM2_CC0 #4 WTIM3_CC0 #6 LETIM1_OUT1 #4 PCNT0_S1IN #6
ETH_TSUTMRTOG #0 US0_CTS #4 US2_CS #1 QSPI0_DQ7 #1
TIM0_CDTI0 #4 TIM1_CC0 #3
US0_TX #4 US1_CLK #0 US3_RX #2 US4_TX #0 U0_CTS #4
TIM0_CDTI1 #4 TIM1_CC1 #3
US0_RX #4 US1_CS #0 US4_RX #0 U0_RTS #4
EBI_ALE #1 EBI_NANDREn #2 EBI_A00 #1 EBI_A03
#0 EBI_A09 #3
WTIM2_CC0 #2 LETIM0_OUT0 #7
SDIO_WP #3 CAN0_RX #3 US1_CTS #0 U1_TX
#2
EBI_BL0 #2 EBI_A01 #1 EBI_A04 #0 EBI_A10 #3
WTIM2_CC1 #2 LETIM0_OUT1 #7
SDIO_CD #3 CAN0_TX #3 US1_RTS #0 US2_CTS #3 U1_RX
#2
EBI_BL1 #2 EBI_A02 #1 EBI_A11 #3
TIM0_CDTI2 #4 TIM1_CC2 #3 WTIM2_CC2 #2 LETIM0_OUT0 #1 PCNT0_S1IN #7 PCNT1_S0IN #6
US0_CTS #5 US1_CLK #5 US2_CS #3 US5_CLK #0 U1_CTS #2 I2C1_SDA #1
EBI_A03 #1 EBI_A12 #3 EBI_CSTFT #2
TIM1_CC3 #3 WTIM2_CC0 #3 LE-
TIM0_OUT1 #1 PCNT0_S0IN #7 PCNT1_S1IN #6
US2_CTS #1 US5_RTS #0 U1_RTS #2 I2C1_SCL #1
TIM6_CC0 #5 WTIM1_CC0 #0 PCNT2_S0IN #2
US0_CLK #4 US1_CTS #5 US5_CS #0 LEU0_TX #1
TIM6_CC1 #5 WTIM1_CC1 #0 PCNT2_S1IN #2
US0_CS #4 US1_RTS #5 US5_CTS #0 LEU0_RX #1
Other
PRS_CH20 #0
PRS_CH21 #0
PRS_CH12 #1
PRS_CH22 #0
CMU_CLKI0 #2 PRS_CH23 #0 PRS_CH13 #1 ACMP1_O #5
PRS_CH9 #2 ACMP1_O #6
CMU_CLK1 #5 CMU_CLKI0 #7 PRS_CH21 #2 ACMP0_O #3 GPIO_EM4WU7
PRS_CH16 #1
CMU_CLKI0 #3 PRS_CH7 #0
PRS_CH6 #1
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EFM32GG11 Family Data Sheet
Pin Definitions
GPIO Name PB15 PC0
PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10
Pin Alternate Functionality / Description
Analog
EBI
Timers
Communication
Other
BUSAY BUSBX
EBI_CS3 #1 EBI_ARDY #2
TIM3_CC1 #7
ETH_TSUTMRTOG #1 SDIO_WP #2 US2_RTS #1 US5_RTS #1
PRS_CH17 #1 ETM_TD2 #1
VDAC0_OUT0ALT / OPA0_OUTALT #0 BUSACMP0Y BU-
SACMP0X
EBI_AD07 #1 EBI_CS0 #2 EBI_REn #3 EBI_A23 #0
TIM0_CC1 #3 TIM2_CC1 #4 PCNT0_S0IN #2
ETH_MDIO #2 CAN0_RX #0 US0_TX #5 US1_TX #0 US1_CS #4 US2_RTS #0 US3_CS #3 I2C0_SDA #4
LES_CH0 PRS_CH2 #0
VDAC0_OUT0ALT / OPA0_OUTALT #1 BUSACMP0Y BU-
SACMP0X
EBI_AD08 #1 EBI_CS1 #2 EBI_BL0 #3 EBI_A24
#0
TIM0_CC2 #3 TIM2_CC2 #4 WTIM0_CC0 #7 PCNT0_S1IN #2
ETH_MDC #2 CAN0_TX #0 US0_RX #5 US1_TX #4 US1_RX #0 US2_CTS #0 US3_RTS #1 I2C0_SCL #4
LES_CH1 PRS_CH3 #0
VDAC0_OUT0ALT / OPA0_OUTALT #2 BUSACMP0Y BU-
SACMP0X
EBI_AD09 #1 EBI_CS2 #2 EBI_NANDWEn #3 EBI_A25 #0
TIM0_CDTI0 #3 TIM2_CC0 #5 WTIM0_CC1 #7 LETIM1_OUT0 #3
ETH_TSUEXTCLK #2 CAN1_RX #0
US1_RX #4 US2_TX #0
LES_CH2 PRS_CH10 #1
VDAC0_OUT0ALT / OPA0_OUTALT #3 BUSACMP0Y BU-
SACMP0X
EBI_AD10 #1 EBI_CS3 #2 EBI_BL1 #3 EBI_NANDREn #0
TIM0_CDTI1 #3 TIM2_CC1 #5 WTIM0_CC2 #7 LETIM1_OUT1 #3
ETH_TSUTMRTOG #2 CAN1_TX #0 US1_CLK #4 US2_RX #0
LES_CH3 PRS_CH11 #1
BUSACMP0Y BUSACMP0X OPA0_P
EBI_AD11 #1 EBI_ALE #2 EBI_NANDREn #3 EBI_A26 #0
TIM0_CC0 #5 TIM0_CDTI2 #3 TIM2_CC2 #5 LETIM0_OUT0 #3 PCNT1_S0IN #3
SDIO_CD #1 US2_CLK #0 US4_CLK #0 U0_TX #4 U1_CTS #4 I2C1_SDA #0
LES_CH4 PRS_CH18 #2 GPIO_EM4WU6
BUSACMP0Y BUSACMP0X OPA0_N
EBI_AD12 #1 EBI_WEn #2 EBI_NANDWEn #0 EBI_A00 #3
TIM0_CC1 #5 LETIM0_OUT1 #3 PCNT1_S1IN #3
SDIO_WP #1 US2_CS #0 US4_CS
#0 U0_RX #4 U1_RTS #4 I2C1_SCL #0
LES_CH5 PRS_CH19 #2
BUSACMP0Y BUSACMP0X OPA3_P
EBI_A05 #0
WTIM1_CC3 #2
US0_RTS #2 US1_CTS #3 LEU1_TX #0 I2C0_SDA #2
LES_CH6 PRS_CH14 #1 ETM_TCLK #2
BUSACMP0Y BU- EBI_A06 #0 EBI_A13
SACMP0X OPA3_N
#1 EBI_A21 #3
WTIM1_CC0 #3
US0_CTS #2 US1_RTS #3 LEU1_RX #0 I2C0_SCL #2
LES_CH7 PRS_CH15 #1 ETM_TD0 #2
BUSACMP1Y BUSACMP1X
EBI_A08 #2 EBI_A15 #0 EBI_A20 #1 EBI_A26 #3
TIM2_CC0 #2 TIM5_CC0 #4 WTIM3_CC0 #1
US0_CS #2
LES_CH8 PRS_CH4 #0
BUSACMP1Y BU- EBI_A09 #2 EBI_A21
SACMP1X
#1 EBI_A27 #3
TIM2_CC1 #2 TIM5_CC1 #4 WTIM3_CC1 #1
CAN1_RX #3 US0_CLK #2
LES_CH9 PRS_CH5 #0 GPIO_EM4WU2
BUSACMP1Y BU- EBI_A10 #2 EBI_A22
SACMP1X
#1
TIM2_CC2 #2 TIM5_CC2 #4 WTIM3_CC2 #1
CAN1_TX #3 US0_RX #2
LES_CH10 PRS_CH18 #1
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EFM32GG11 Family Data Sheet
Pin Definitions
GPIO Name PC11 PC12
PC13
PC14
PC15 PD0 PD1 PD2 PD3 PD4
Pin Alternate Functionality / Description
Analog
EBI
Timers
Communication
BUSACMP1Y BUSACMP1X
EBI_ALE #4 EBI_ALE #5 EBI_A23
#1
TIM5_CC0 #5 WTIM3_CC0 #2
CAN1_TX #4 US0_TX #2 I2C1_SDA #4
VDAC0_OUT1ALT / OPA1_OUTALT #0 BUSACMP1Y BU-
SACMP1X
TIM1_CC3 #0 TIM5_CC1 #5 WTIM3_CC1 #2 PCNT2_S0IN #4
CAN1_RX #4 US0_RTS #3 US1_CTS #4 US2_CTS #4 U0_RTS #3 U1_TX #0 I2C2_SDA #6
VDAC0_OUT1ALT / OPA1_OUTALT #1 BUSACMP1Y BU-
SACMP1X
EBI_ARDY #4
TIM0_CDTI0 #1 TIM1_CC0 #0 TIM1_CC2 #4 TIM5_CC2 #5 WTIM3_CC2 #2 PCNT0_S0IN #0 PCNT2_S1IN #4
US0_CTS #3 US1_RTS #4 US2_RTS #4 U0_CTS #3 U1_RX #0 I2C2_SCL #6
VDAC0_OUT1ALT / OPA1_OUTALT #2 BUSACMP1Y BU-
SACMP1X
EBI_NANDWEn #4
TIM0_CDTI1 #1 TIM1_CC1 #0 TIM1_CC3 #4 TIM5_CC0 #6 WTIM3_CC0 #3 LETIM0_OUT0 #5 PCNT0_S1IN #0
US0_CS #3 US1_CS #3 US2_RTS #3
US3_CS #2 U0_TX #3 U1_CTS #0 LEU0_TX #5 I2C2_SDA #1
VDAC0_OUT1ALT / OPA1_OUTALT #3 BUSACMP1Y BU-
SACMP1X
EBI_NANDREn #4
TIM0_CDTI2 #1 TIM1_CC2 #0 WTIM0_CC0 #4 LETIM0_OUT1 #5
US0_CLK #3 US1_CLK #3 US3_RTS #3 U0_RX #3 U1_RTS #0 LEU0_RX #5 I2C2_SCL #1
VDAC0_OUT0ALT /
OPA0_OUTALT #4 EBI_A04 #1 EBI_A13
OPA2_OUTALT BU-
#3
SADC0Y BUSADC0X
TIM4_CDTI0 TIM6_CC2 #5 WTIM1_CC2 #0 PCNT2_S0IN #0
CAN0_RX #2 US1_TX #1
VDAC0_OUT1ALT /
OPA1_OUTALT #4 EBI_A05 #1 EBI_A14
BUSADC0Y BU-
#3
SADC0X OPA3_OUT
TIM4_CDTI1 TIM0_CC0 #2 TIM6_CC0 #6 WTIM1_CC3 #0 PCNT2_S1IN #0
CAN0_TX #2 US1_RX #1
BUSADC0Y BUSADC0X
EBI_A06 #1 EBI_A15 #3 EBI_A27 #0
TIM0_CC1 #2 TIM6_CC1 #6 WTIM1_CC0 #1
US1_CLK #1 LEU1_TX #2
BUSADC0Y BU- EBI_A07 #1 EBI_A16
SADC0X OPA2_N
#3
TIM4_CDTI2 TIM0_CC2 #2 TIM6_CC2 #6 WTIM1_CC1 #1 WTIM2_CC0 #5
CAN1_RX #2 US1_CS #1 LEU1_RX #2
BUSADC0Y BUSADC0X OPA2_P
EBI_A08 #1 EBI_A17 #3
TIM6_CC0 #7 WTIM0_CDTI0 #4 WTIM1_CC2 #1 WTIM2_CC1 #5
CAN1_TX #2 US1_CTS #1 US3_CLK #2 LEU0_TX #0 I2C1_SDA #3
Other LES_CH11 PRS_CH19 #1
CMU_CLK0 #1 LES_CH12
PRS_CH20 #1
LES_CH13 PRS_CH21 #1 ACMP3_O #3
LES_CH14 PRS_CH0 #2 ACMP3_O #2
LES_CH15 PRS_CH1 #2 ACMP3_O #1 DBG_SWO #1
DBG_SWO #2
DBG_SWO #3
ETM_TD1 #0 ETM_TD1 #2
CMU_CLKI0 #0 PRS_CH10 #2 ETM_TD2 #0 ETM_TD2 #2
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Rev. 1.0 | 176
EFM32GG11 Family Data Sheet
Pin Definitions
GPIO Name PD5 PD6 PD7
Pin Alternate Functionality / Description
Analog
EBI
Timers
Communication
BUSADC0Y BU- EBI_A09 #1 EBI_A18
SADC0X OPA2_OUT
#3
TIM6_CC1 #7 WTIM0_CDTI1 #4 WTIM1_CC3 #1 WTIM2_CC2 #5
US1_RTS #1 U0_CTS #5 LEU0_RX #0 I2C1_SCL #3
BUSADC0Y BUSADC0X
ADC0_EXTP VDAC0_EXT ADC1_EXTP
OPA1_P
EBI_A10 #1 EBI_A19 #3
TIM1_CC0 #4 TIM6_CC2 #7 WTIM0_CDTI2 #4 WTIM1_CC0 #2 LETIM0_OUT0 #0 PCNT0_S0IN #3
US0_RTS #5 US1_RX #2 US2_CTS #5 US3_CTS #2 U0_RTS #5 I2C0_SDA #1
BUSADC0Y BUSADC0X
ADC0_EXTN ADC1_EXTN
OPA1_N
EBI_A11 #1 EBI_A20 #3
TIM1_CC1 #4 WTIM1_CC1 #2 LE-
TIM0_OUT1 #0 PCNT0_S1IN #3
US1_TX #2 US3_CLK #1 U0_TX
#6 I2C0_SCL #1
PD8
BU_VIN
EBI_A12 #1
WTIM1_CC2 #2
US2_RTS #5
PD9 PD10 PD11 PD12 PD13 PD14 PD15 PE0
LCD_SEG28 LCD_SEG29 LCD_SEG30 LCD_SEG31
BUSDY BUSCX
EBI_CS0 #0 EBI_DTEN #1
EBI_CS1 #0 EBI_VSNC #1
EBI_CS2 #0 EBI_HSNC #1
EBI_CS3 #0
EBI_ARDY #1
EBI_NANDWEn #1
EBI_NANDREn #1 EBI_A00 #2 EBI_A07
#0
TIM4_CC1 #5 WTIM3_CC0 #0
TIM4_CC2 #5 WTIM3_CC1 #0
TIM4_CC0 #6 WTIM3_CC2 #0
TIM4_CC1 #6
TIM2_CDTI0 #1 TIM3_CC1 #6 WTIM0_CC1 #1
TIM2_CDTI1 #1 TIM3_CC2 #6 WTIM0_CC2 #1
TIM2_CDTI2 #1 TIM3_CC0 #7 WTIM0_CDTI0 #1 PCNT1_S0IN #2 TIM3_CC0 #1 WTIM1_CC1 #3 PCNT0_S0IN #1
ETH_RMIIRXD0 #1 SDIO_DAT7 #0 QSPI0_DQ0 #0
ETH_MIIRXD1 #2 US4_TX #1
ETH_RMIIREFCLK #1 SDIO_DAT6 #0
QSPI0_DQ1 #0 ETH_MIIRXD2 #2
US4_RX #1
ETH_RMIICRSDV #1 SDIO_DAT5 #0 QSPI0_DQ2 #0
ETH_MIIRXD3 #2 US4_CLK #1
ETH_RMIIRXER #1 SDIO_DAT4 #0 QSPI0_DQ3 #0
ETH_MIIRXCLK #2 US4_CS #1
ETH_MDIO #1 US4_CTS #1 US5_CLK #1
ETH_MDC #1 CAN0_RX #5 US4_RTS #1 US5_CS #1 I2C0_SDA #3
ETH_TSUEXTCLK #1 CAN0_TX #5 US5_CTS #1 I2C0_SCL #3
CAN0_RX #6 U0_TX #1 I2C1_SDA #2
Other PRS_CH11 #2 ETM_TD3 #0 ETM_TD3 #2 CMU_CLK2 #2 LES_ALTEX0 PRS_CH5 #2 ACMP0_O #2 ETM_TD0 #0 CMU_CLK0 #2 LES_ALTEX1 ACMP1_O #2 ETM_TCLK #0 CMU_CLK1 #1 PRS_CH12 #2 ACMP2_O #0
CMU_CLK2 #5 CMU_CLKI0 #5
ETM_TD1 #1
PRS_CH22 #1 ACMP2_O #1
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Rev. 1.0 | 177
EFM32GG11 Family Data Sheet
Pin Definitions
GPIO Name PE1 PE2 PE3 PE4
PE5
PE6 PE7 PE8 PE9 PE10 PE11 PE12 PE13
Analog BUSCY BUSDX
BU_VOUT
BU_STAT
BUSDY BUSCX LCD_COM0
BUSCY BUSDX LCD_COM1
BUSDY BUSCX LCD_COM2
BUSCY BUSDX LCD_COM3
BUSDY BUSCX LCD_SEG4
BUSCY BUSDX LCD_SEG5
BUSDY BUSCX LCD_SEG6
BUSCY BUSDX LCD_SEG7
BUSDY BUSCX LCD_SEG8
BUSCY BUSDX LCD_SEG9
Pin Alternate Functionality / Description
EBI
Timers
Communication
EBI_A01 #2 EBI_A08 #0
TIM3_CC1 #1 WTIM1_CC2 #3 PCNT0_S1IN #1
CAN0_TX #6 U0_RX #1 I2C1_SCL #2
EBI_A09 #0 EBI_A14 #1
TIM3_CC2 #1 WTIM1_CC3 #3
US0_RTS #1 U0_CTS #1 U1_TX
#3
EBI_A10 #0 EBI_A15 #1
TIM3_CC0 #2 WTIM1_CC0 #4
US0_CTS #1 U0_RTS #1 U1_RX
#3
EBI_A11 #0 EBI_A16 #1 EBI_A22 #3
TIM3_CC1 #2 TIM5_CC0 #0 TIM6_CDTI0 #2 WTIM0_CC0 #0 WTIM1_CC1 #4
US0_CS #1 US1_CS #5 US3_CS #1
U0_RX #6 U1_CTS #3 I2C0_SDA #7
EBI_A12 #0 EBI_A17 #1 EBI_A23 #3
TIM3_CC0 #3 TIM3_CC2 #2 TIM5_CC1 #0 TIM6_CDTI1 #2 WTIM0_CC1 #0 WTIM1_CC2 #4
US0_CLK #1 US1_CLK #6 US3_CTS #1 U1_RTS #3 I2C0_SCL #7
EBI_A13 #0 EBI_A18 #1 EBI_A24 #3
TIM3_CC1 #3 TIM5_CC2 #0 TIM6_CDTI2 #2 WTIM0_CC2 #0 WTIM1_CC3 #4
US0_RX #1 US3_TX #1
EBI_A14 #0 EBI_A19 #1 EBI_A25 #3
TIM3_CC2 #3 TIM5_CC0 #1 WTIM1_CC0 #5
US0_TX #1 US3_RX #1
EBI_AD00 #0 EBI_CS0 #4
TIM2_CDTI0 #2 TIM4_CC2 #6 PCNT2_S0IN #1
SDIO_DAT3 #0 QSPI0_DQ4 #0
US5_TX #0 I2C2_SDA #0
EBI_AD01 #0 EBI_CS1 #4
TIM4_CC0 #7 PCNT2_S1IN #1
SDIO_DAT2 #0 QSPI0_DQ5 #0
US5_RX #0
EBI_AD02 #0 EBI_CS2 #4
TIM1_CC0 #1 TIM4_CC1 #7 WTIM0_CDTI0 #0
SDIO_DAT1 #0 QSPI0_DQ6 #0 ETH_MIIRXER #0
US0_TX #0
EBI_AD03 #0 EBI_CS3 #4
TIM1_CC1 #1 TIM4_CC2 #7 WTIM0_CDTI1 #0
SDIO_DAT0 #0 QSPI0_DQ7 #0 ETH_MIIRXDV #0
US0_RX #0
EBI_AD04 #0
TIM1_CC2 #1 TIM2_CC1 #3 WTIM0_CDTI2 #0 LETIM0_OUT0 #4
SDIO_CMD #0 ETH_MIIRXD0 #0
US0_RX #3 US0_CLK #0 U1_TX
#4 I2C0_SDA #6
EBI_AD05 #0
TIM1_CC3 #1 TIM2_CC2 #3 LE-
TIM0_OUT1 #4
SDIO_CLK #0 ETH_MIIRXD1 #0 US0_TX #3 US0_CS
#0 U1_RX #4 I2C0_SCL #6
Other CMU_CLKI0 #4 PRS_CH23 #1 ACMP2_O #2 PRS_CH20 #2 ACMP0_O #1
ACMP1_O #1
PRS_CH16 #2
PRS_CH17 #2
PRS_CH6 #2
PRS_CH7 #2
PRS_CH3 #1
PRS_CH8 #2
PRS_CH2 #2 GPIO_EM4WU9
LES_ALTEX5 PRS_CH3 #2 ETM_TCLK #4 CMU_CLK1 #2 CMU_CLKI0 #6 LES_ALTEX6 PRS_CH1 #3 ETM_TD0 #4 LES_ALTEX7 PRS_CH2 #3 ACMP0_O #0 ETM_TD1 #4 GPIO_EM4WU5
silabs.com | Building a more connected world.
Rev. 1.0 | 178
GPIO Name PE14
PE15 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7
EFM32GG11 Family Data Sheet
Pin Definitions
Analog
BUSDY BUSCX LCD_SEG10
BUSCY BUSDX LCD_SEG11
BUSDY BUSCX
BUSCY BUSDX
BUSDY BUSCX LCD_SEG0
BUSCY BUSDX LCD_SEG1
BUSDY BUSCX LCD_SEG2
BUSCY BUSDX LCD_SEG3
BUSDY BUSCX LCD_SEG24
BUSCY BUSDX LCD_SEG25
Pin Alternate Functionality / Description
EBI
Timers
Communication
EBI_AD06 #0
TIM2_CDTI1 #2 TIM3_CC0 #0
ETH_RMIITXD1 #0 ETH_MIIRXD2 #0
SDIO_CLK #1 US0_CTS #0 QSPI0_SCLK #1 LEU0_TX #2
EBI_AD07 #0
TIM2_CDTI2 #2 TIM3_CC1 #0
ETH_RMIITXD0 #0 ETH_MIIRXD3 #0
SDIO_CMD #1 US0_RTS #0 QSPI0_DQS #1 LEU0_RX #2
EBI_A24 #1
TIM0_CC0 #4 WTIM0_CC1 #4 LE-
TIM0_OUT0 #2
US2_TX #5 CAN0_RX #1 US1_CLK #2 LEU0_TX #3 I2C0_SDA #5
EBI_A25 #1
TIM0_CC1 #4 WTIM0_CC2 #4 LE-
TIM0_OUT1 #2
US2_RX #5 CAN1_RX #1 US1_CS #2 U0_TX #5 LEU0_RX #3 I2C0_SCL #5
EBI_ARDY #0 EBI_A26 #1
TIM0_CC2 #4 TIM1_CC0 #5 TIM2_CC0 #3
US2_CLK #5 CAN0_TX #1 US1_TX #5 U0_RX #5 LEU0_TX #4 I2C1_SCL #4
EBI_ALE #0
EBI_WEn #0 EBI_WEn #5
EBI_REn #0 EBI_REn #5 EBI_A27 #1
TIM4_CC0 #0 TIM0_CDTI0 #2 TIM1_CC1 #5
TIM4_CC1 #0 TIM0_CDTI1 #2 TIM1_CC2 #5 WTIM3_CC1 #6
TIM0_CDTI2 #2 TIM1_CC3 #6 TIM4_CC0 #2
EBI_BL0 #0 EBI_BL0 #4 EBI_BL0 #5 EBI_CSTFT #1
TIM0_CC0 #1 TIM4_CC0 #4 WTIM3_CC2 #5
EBI_BL1 #0 EBI_BL1 #4 EBI_BL1 #5 EBI_DCLK #1
TIM0_CC1 #1 TIM4_CC1 #4
CAN1_TX #1 US1_CTS #2 I2C2_SCL #5
US1_RTS #2 I2C2_SDA #3
US2_CS #5 I2C2_SCL #0 USB_VBUSEN
ETH_RMIITXD1 #1 US2_TX #4
QSPI0_SCLK #0 US1_TX #3 U0_TX
#0
ETH_RMIITXD0 #1 US2_RX #4
QSPI0_CS0 #0 ETH_MIIRXER #2 US1_RX #3 U0_RX
#0
Other
PRS_CH13 #2 ETM_TD2 #4
PRS_CH14 #2 ETM_TD3 #4
PRS_CH15 #2 ACMP3_O #0 DBG_SWCLKTCK
BOOT_TX
PRS_CH4 #2 DBG_SWDIOTMS GPIO_EM4WU3
BOOT_RX CMU_CLK0 #4 PRS_CH0 #3 ACMP1_O #0
DBG_TDO DBG_SWO #0 GPIO_EM4WU4 CMU_CLK1 #4 PRS_CH0 #1 ETM_TD3 #1
PRS_CH1 #1
PRS_CH2 #1 DBG_TDI
PRS_CH22 #2
PRS_CH23 #2
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Rev. 1.0 | 179
GPIO Name
PF8
PF9
PF10 PF11 PF12 PF13 PF14 PF15 PG0 PG1 PG2 PG3
EFM32GG11 Family Data Sheet
Pin Definitions
Analog
BUSDY BUSCX LCD_SEG26
BUSCY BUSDX LCD_SEG27
BUSDY BUSCX BUSCY BUSDX
BUSDY BUSCX
BUSCY BUSDX
BUSDY BUSCX
BUSCY BUSDX BUSACMP2Y BU-
SACMP2X BUSACMP2Y BU-
SACMP2X BUSACMP2Y BU-
SACMP2X BUSACMP2Y BU-
SACMP2X
Pin Alternate Functionality / Description
EBI
Timers
Communication
EBI_WEn #4 EBI_BL0 #1
TIM0_CC2 #1 TIM4_CC2 #4
ETH_RMIITXEN #1 US2_CLK #4 QSPI0_CS1 #0
ETH_MIIRXDV #2 ETH_TSUEXTCLK
#3 SDIO_CD #0 U0_CTS #0 U1_RTS
#1
EBI_REn #4 EBI_BL1 #1
TIM4_CC0 #5
ETH_RMIIRXD1 #1 US2_CS #4
QSPI0_DQS #0 ETH_MIIRXD0 #2 ETH_TSUTMRTOG #3 SDIO_WP #0 U0_RTS #0 U1_CTS
#1
EBI_ARDY #5
TIM5_CC1 #6 WTIM3_CC1 #3 PCNT2_S0IN #3
US5_RTS #2 U1_TX #1 I2C2_SDA #2 USB_DM
EBI_NANDWEn #5
TIM5_CC2 #6 WTIM3_CC2 #3 PCNT2_S1IN #3
US5_CTS #2 U1_RX #1 I2C2_SCL #2 USB_DP
EBI_NANDREn #5
TIM4_CC2 #0 TIM1_CC3 #5 TIM5_CC0 #7 WTIM3_CC2 #6
US5_CS #2 I2C2_SCL #3
USB_ID
TIM1_CC0 #6 TIM4_CC0 #1 TIM5_CC1 #7 WTIM3_CC0 #7
US5_CLK #2 I2C2_SDA #4
TIM1_CC1 #6 TIM4_CC1 #1 TIM5_CC2 #7 WTIM3_CC1 #7
I2C2_SCL #4
TIM1_CC2 #6 TIM4_CC2 #1 WTIM3_CC2 #7
US5_TX #2 I2C2_SDA #5
EBI_AD00 #2
TIM6_CC0 #0 TIM2_CDTI0 #3 WTIM0_CDTI1 #1 LETIM1_OUT0 #6
ETH_MIITXCLK #1 US3_TX #4
QSPI0_SCLK #2
EBI_AD01 #2
TIM6_CC1 #0 TIM2_CDTI1 #3 WTIM0_CDTI2 #1 LETIM1_OUT1 #6
ETH_MIITXD3 #1 US3_RX #4
QSPI0_DQ0 #2
EBI_AD02 #2
TIM6_CC2 #0 TIM2_CDTI2 #3 WTIM0_CC0 #2 LETIM1_OUT0 #7
ETH_MIITXD2 #1 US3_CLK #4
QSPI0_DQ1 #2
EBI_AD03 #2
TIM6_CDTI0 #0 WTIM0_CC1 #2 LE-
TIM1_OUT1 #7
ETH_MIITXD1 #1 US3_CS #4
QSPI0_DQ2 #2
Other ETM_TCLK #1 GPIO_EM4WU8 ETM_TD0 #1
CMU_CLK2 #3 CMU_CLK1 #3 CMU_CLK0 #3
silabs.com | Building a more connected world.
Rev. 1.0 | 180
GPIO Name PG4
Analog
BUSACMP2Y BUSACMP2X
PG5
BUSACMP2Y BUSACMP2X
PG6
BUSACMP2Y BUSACMP2X
PG7
BUSACMP2Y BUSACMP2X
PG8
PG9
PG10
PG11
PG12 PG13 PG14 PG15 PH0 PH1 PH2 PH3 PH4
BUSADC1Y BUSADC1X
BUSADC1Y BUSADC1X
BUSADC1Y BUSADC1X
BUSADC1Y BUSADC1X
BUSADC1Y BUSADC1X
EFM32GG11 Family Data Sheet
Pin Definitions
Pin Alternate Functionality / Description
EBI
Timers
Communication
EBI_AD04 #2
TIM6_CDTI1 #0 WTIM0_CC2 #2
ETH_MIITXD0 #1 US3_CTS #4
QSPI0_DQ3 #2
EBI_AD05 #2
TIM6_CDTI2 #0 TIM2_CC0 #7
ETH_MIITXEN #1 US3_RTS #4
QSPI0_DQ4 #2
EBI_AD06 #2
TIM2_CC1 #7 TIM6_CC0 #1
ETH_MIITXER #1 US3_TX #3
QSPI0_DQ5 #2
EBI_AD07 #2
TIM2_CC2 #7 TIM6_CC1 #1
ETH_MIIRXCLK #1 US3_RX #3
QSPI0_DQ6 #2
EBI_AD08 #2
TIM2_CC0 #6 TIM6_CC2 #1 WTIM0_CC0 #3
ETH_MIIRXD3 #1 CAN0_RX #4 US3_CLK #3 QSPI0_DQ7 #2
EBI_AD09 #2
TIM2_CC1 #6 TIM6_CDTI0 #1 WTIM0_CC1 #3
ETH_MIIRXD2 #1 CAN0_TX #4 US3_CTS #5 QSPI0_CS0 #2
EBI_AD10 #2
TIM2_CC2 #6 TIM6_CDTI1 #1 WTIM0_CC2 #3
ETH_MIIRXD1 #1 CAN1_RX #6 US3_CTS #3 QSPI0_CS1 #2
EBI_AD11 #2
TIM6_CDTI2 #1 WTIM0_CDTI0 #3
ETH_MIIRXD0 #1 CAN1_TX #6 US3_RTS #5
QSPI0_DQS #2
EBI_AD12 #2
TIM6_CC0 #2 WTIM0_CDTI1 #3 WTIM2_CC1 #3
ETH_MIIRXDV #1 US0_TX #6
EBI_AD13 #2
TIM6_CC1 #2 WTIM0_CDTI2 #3 WTIM2_CC2 #3
ETH_MIIRXER #1 US0_RX #6
EBI_AD14 #2
TIM6_CC2 #2 WTIM2_CC0 #4 PCNT1_S0IN #7
ETH_MIICRS #1 US0_CLK #6
EBI_AD15 #2
WTIM2_CC1 #4 PCNT1_S1IN #7
ETH_MIICOL #1 US0_CS #6
EBI_DCLK #2
WTIM2_CC2 #4
US0_CTS #6 LEU1_TX #5
EBI_DTEN #2
US0_RTS #6 LEU1_RX #5
EBI_VSNC #2
TIM6_CC0 #3
US1_CTS #6
Other
ETM_TD3 #5 ETM_TD2 #5 ETM_TD1 #5 ETM_TD0 #5 ETM_TCLK #5
EBI_HSNC #2 EBI_A16 #2
TIM6_CC1 #3
TIM6_CC2 #3 WTIM2_CC0 #6
US1_RTS #6 US4_TX #4
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Rev. 1.0 | 181
GPIO Name
PH5 PH6 PH7 PH8
Analog
BUSADC1Y BUSADC1X
BUSADC1Y BUSADC1X
BUSADC1Y BUSADC1X
BUSACMP3Y BUSACMP3X
PH9 PH10 PH11 PH12 PH13
BUSACMP3Y BUSACMP3X
BUSACMP3Y BUSACMP3X
BUSACMP3Y BUSACMP3X
BUSACMP3Y BUSACMP3X
BUSACMP3Y BUSACMP3X
PH14
BUSACMP3Y BUSACMP3X
PH15
BUSACMP3Y BUSACMP3X
PI0
PI1
PI2 PI3 PI4 PI5 PI6
PI7
EFM32GG11 Family Data Sheet
Pin Definitions
Pin Alternate Functionality / Description
EBI
Timers
Communication
EBI_A17 #2
TIM6_CDTI0 #3 WTIM2_CC1 #6
US4_RX #4
EBI_A18 #2
TIM6_CDTI1 #3 WTIM2_CC2 #6
US4_CLK #4
EBI_A19 #2
TIM6_CDTI2 #3 WTIM2_CC0 #7
US4_CS #4
EBI_A20 #2
TIM6_CC0 #4 WTIM1_CC0 #6 WTIM2_CC1 #7
US4_CTS #4
EBI_A21 #2
TIM6_CC1 #4 WTIM1_CC1 #6 WTIM2_CC2 #7
US4_RTS #4
EBI_A22 #2
TIM6_CC2 #4 WTIM1_CC2 #6
US5_TX #3
EBI_A23 #2
TIM5_CC1 #1 WTIM1_CC3 #6
US5_RX #3 U1_TX #5 I2C1_SDA #5
EBI_A24 #2
TIM5_CC2 #1 WTIM1_CC0 #7
US5_CLK #3 U1_RX #5 I2C1_SCL #5
EBI_A25 #2
TIM5_CC0 #2 WTIM1_CC1 #7 PCNT2_S1IN #7
US5_CS #3 U1_CTS #5 I2C1_SDA #6
EBI_A26 #2
TIM5_CC1 #2 WTIM1_CC2 #7 PCNT2_S0IN #7
US5_CTS #3 U1_RTS #5 I2C1_SCL #6
EBI_A27 #2
TIM5_CC2 #2 WTIM1_CC3 #7 PCNT2_S1IN #6
US5_RTS #3
EBI_A02 #2
TIM5_CC0 #3 WTIM1_CC1 #5 PCNT2_S0IN #6
US4_TX #2
EBI_A03 #2
TIM5_CC1 #3 WTIM1_CC2 #5 PCNT2_S1IN #5
US4_RX #2
EBI_A04 #2
TIM5_CC2 #3 WTIM1_CC3 #5 PCNT2_S0IN #5
US4_CLK #2 I2C1_SDA #7
EBI_A05 #2
WTIM3_CC0 #4
US4_CS #2 I2C1_SCL #7
EBI_A06 #2
WTIM3_CC1 #4
US4_CTS #2 I2C2_SDA #7
EBI_A07 #2
WTIM3_CC2 #4
US4_RTS #2 I2C2_SCL #7
EBI_A11 #2
TIM1_CC0 #7 TIM4_CC1 #2 WTIM3_CC0 #5
US4_TX #3
EBI_A12 #2
TIM1_CC1 #7 TIM4_CC2 #2 WTIM3_CC1 #5
US4_RX #3
Other
ACMP2_O #3 ACMP2_O #4 ACMP2_O #5 ACMP3_O #4 ACMP3_O #5
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GPIO Name
PI8 PI9 PI10 PI11 PI12 PI13 PI14 PI15
Analog
EFM32GG11 Family Data Sheet
Pin Definitions
Pin Alternate Functionality / Description
EBI
Timers
Communication
EBI_A13 #2
TIM1_CC2 #7 TIM4_CC0 #3
US4_CLK #3
EBI_A14 #2
TIM1_CC3 #7 TIM4_CC1 #3
US4_CS #3
EBI_A15 #2
TIM4_CC2 #3
US4_CTS #3
US4_RTS #3
CAN0_RX #7 US3_TX #5
CAN0_TX #7 US3_RX #5
CAN1_RX #7 US3_CLK #5
CAN1_TX #7 US3_CS #5
Other
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Rev. 1.0 | 183
EFM32GG11 Family Data Sheet
Pin Definitions
5.21 Alternate Functionality Overview
A wide selection of alternate functionality is available for multiplexing to various pins. The following table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings and the associated GPIO pin. Refer to 5.20 GPIO Functionality Table for a list of functions available on each GPIO pin.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0.
Alternate Functionality ACMP0_O ACMP1_O ACMP2_O ACMP3_O ADC0_EXTN ADC0_EXTP ADC1_EXTN ADC1_EXTP BOOT_RX BOOT_TX
Table 5.21. Alternate Functionality Overview
LOCATION
0 - 3
4 - 7
0: PE13 1: PE2 2: PD6 3: PB11
4: PA6 5: PB0 6: PB2 7: PB3
0: PF2 1: PE3 2: PD7 3: PA12
4: PA14 5: PB9 6: PB10 7: PA5
0: PD8 1: PE0 2: PE1 3: PI0
4: PI1 5: PI2
0: PF0 1: PC15 2: PC14 3: PC13
4: PI4 5: PI5
0: PD7
Description Analog comparator ACMP0, digital output. Analog comparator ACMP1, digital output. Analog comparator ACMP2, digital output. Analog comparator ACMP3, digital output. Analog to digital converter ADC0 external reference input negative pin.
0: PD6
Analog to digital converter ADC0 external reference input positive pin.
0: PD7
Analog to digital converter ADC1 external reference input negative pin.
0: PD6
Analog to digital converter ADC1 external reference input positive pin.
0: PF1
Bootloader RX.
0: PF0
Bootloader TX.
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Alternate Functionality
BU_STAT
EFM32GG11 Family Data Sheet
Pin Definitions
LOCATION
0 - 3
4 - 7
0: PE3
Description Backup Power Domain status, whether or not the system is in backup mode.
BU_VIN
0: PD8
Battery input for Backup Power Domain.
BU_VOUT
0: PE2
Power output for Backup Power Domain.
CAN0_RX
0: PC0 1: PF0 2: PD0 3: PB9
CAN0_TX
0: PC1 1: PF2 2: PD1 3: PB10
CAN1_RX
0: PC2 1: PF1 2: PD3 3: PC9
CAN1_TX
0: PC3 1: PF3 2: PD4 3: PC10
CMU_CLK0
0: PA2 1: PC12 2: PD7 3: PG2
CMU_CLK1
0: PA1 1: PD8 2: PE12 3: PG1
CMU_CLK2
0: PA0 1: PA3 2: PD6 3: PG0
CMU_CLKI0
0: PD4 1: PA3 2: PB8 3: PB13
0: PF0 DBG_SWCLKTCK
4: PG8 5: PD14 6: PE0 7: PI12
4: PG9 5: PD15 6: PE1 7: PI13
4: PC12 5: PA12 6: PG10 7: PI14
4: PC11 5: PA13 6: PG11 7: PI15
4: PF2 5: PA12
4: PF3 5: PB11
4: PA3 5: PD10
4: PE1 5: PD10 6: PE12 7: PB11
CAN0 RX. CAN0 TX. CAN1 RX. CAN1 TX. Clock Management Unit, clock output number 0. Clock Management Unit, clock output number 1. Clock Management Unit, clock output number 2. Clock Management Unit, clock input number 0. Debug-interface Serial Wire clock input and JTAG Test Clock. Note that this function is enabled to the pin out of reset, and has a built-in pull down.
0: PF1 DBG_SWDIOTMS
Debug-interface Serial Wire data input / output and JTAG Test Mode Select. Note that this function is enabled to the pin out of reset, and has a built-in pull up.
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Alternate Functionality DBG_SWO DBG_TDI DBG_TDO EBI_A00 EBI_A01 EBI_A02 EBI_A03 EBI_A04 EBI_A05 EBI_A06 EBI_A07 EBI_A08 EBI_A09
EFM32GG11 Family Data Sheet
Pin Definitions
LOCATION
0 - 3
4 - 7
0: PF2 1: PC15 2: PD1 3: PD2
0: PF5
0: PF2
0: PA12 1: PB9 2: PE0 3: PC5
0: PA13 1: PB10 2: PE1 3: PA7
0: PA14 1: PB11 2: PI0 3: PA8
0: PB9 1: PB12 2: PI1 3: PA9
0: PB10 1: PD0 2: PI2 3: PA10
0: PC6 1: PD1 2: PI3 3: PA11
0: PC7 1: PD2 2: PI4 3: PA12
0: PE0 1: PD3 2: PI5 3: PA13
0: PE1 1: PD4 2: PC8 3: PA14
0: PE2 1: PD5 2: PC9 3: PB9
Description Debug-interface Serial Wire viewer Output. Note that this function is not enabled after reset, and must be enabled by software to be used. Debug-interface JTAG Test Data In. Note that this function becomes available after the first valid JTAG command is received, and has a built-in pull up when JTAG is active. Debug-interface JTAG Test Data Out. Note that this function becomes available after the first valid JTAG command is received. External Bus Interface (EBI) address output pin 00.
External Bus Interface (EBI) address output pin 01.
External Bus Interface (EBI) address output pin 02.
External Bus Interface (EBI) address output pin 03.
External Bus Interface (EBI) address output pin 04.
External Bus Interface (EBI) address output pin 05.
External Bus Interface (EBI) address output pin 06.
External Bus Interface (EBI) address output pin 07.
External Bus Interface (EBI) address output pin 08.
External Bus Interface (EBI) address output pin 09.
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Alternate Functionality EBI_A10 EBI_A11 EBI_A12 EBI_A13 EBI_A14 EBI_A15 EBI_A16 EBI_A17 EBI_A18 EBI_A19 EBI_A20 EBI_A21 EBI_A22
LOCATION
0 - 3
4 - 7
0: PE3 1: PD6 2: PC10 3: PB10
0: PE4 1: PD7 2: PI6 3: PB11
0: PE5 1: PD8 2: PI7 3: PB12
0: PE6 1: PC7 2: PI8 3: PD0
0: PE7 1: PE2 2: PI9 3: PD1
0: PC8 1: PE3 2: PI10 3: PD2
0: PB0 1: PE4 2: PH4 3: PD3
0: PB1 1: PE5 2: PH5 3: PD4
0: PB2 1: PE6 2: PH6 3: PD5
0: PB3 1: PE7 2: PH7 3: PD6
0: PB4 1: PC8 2: PH8 3: PD7
0: PB5 1: PC9 2: PH9 3: PC7
0: PB6 1: PC10 2: PH10 3: PE4
Description External Bus Interface (EBI) address output pin 10. External Bus Interface (EBI) address output pin 11. External Bus Interface (EBI) address output pin 12. External Bus Interface (EBI) address output pin 13. External Bus Interface (EBI) address output pin 14. External Bus Interface (EBI) address output pin 15. External Bus Interface (EBI) address output pin 16. External Bus Interface (EBI) address output pin 17. External Bus Interface (EBI) address output pin 18. External Bus Interface (EBI) address output pin 19. External Bus Interface (EBI) address output pin 20. External Bus Interface (EBI) address output pin 21. External Bus Interface (EBI) address output pin 22.
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EFM32GG11 Family Data Sheet
Pin Definitions
Rev. 1.0 | 187
Alternate Functionality EBI_A23 EBI_A24 EBI_A25 EBI_A26 EBI_A27 EBI_AD00 EBI_AD01 EBI_AD02 EBI_AD03 EBI_AD04 EBI_AD05 EBI_AD06 EBI_AD07
EFM32GG11 Family Data Sheet
Pin Definitions
LOCATION
0 - 3
4 - 7
0: PC0 1: PC11 2: PH11 3: PE5
0: PC1 1: PF0 2: PH12 3: PE6
0: PC2 1: PF1 2: PH13 3: PE7
0: PC4 1: PF2 2: PH14 3: PC8
0: PD2 1: PF5 2: PH15 3: PC9
0: PE8 1: PB0 2: PG0
Description External Bus Interface (EBI) address output pin 23. External Bus Interface (EBI) address output pin 24. External Bus Interface (EBI) address output pin 25. External Bus Interface (EBI) address output pin 26. External Bus Interface (EBI) address output pin 27. External Bus Interface (EBI) address and data input / output pin 00.
0: PE9 1: PB1 2: PG1
External Bus Interface (EBI) address and data input / output pin 01.
0: PE10 1: PB2 2: PG2
External Bus Interface (EBI) address and data input / output pin 02.
0: PE11 1: PB3 2: PG3
External Bus Interface (EBI) address and data input / output pin 03.
0: PE12 1: PB4 2: PG4
External Bus Interface (EBI) address and data input / output pin 04.
0: PE13 1: PB5 2: PG5
External Bus Interface (EBI) address and data input / output pin 05.
0: PE14 1: PB6 2: PG6
External Bus Interface (EBI) address and data input / output pin 06.
0: PE15 1: PC0 2: PG7
External Bus Interface (EBI) address and data input / output pin 07.
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Alternate Functionality EBI_AD08 EBI_AD09 EBI_AD10 EBI_AD11 EBI_AD12 EBI_AD13 EBI_AD14 EBI_AD15 EBI_ALE EBI_ARDY EBI_BL0 EBI_BL1 EBI_CS0
EFM32GG11 Family Data Sheet
Pin Definitions
LOCATION
0 - 3
4 - 7
0: PA15 1: PC1 2: PG8
Description External Bus Interface (EBI) address and data input / output pin 08.
0: PA0 1: PC2 2: PG9
External Bus Interface (EBI) address and data input / output pin 09.
0: PA1 1: PC3 2: PG10
External Bus Interface (EBI) address and data input / output pin 10.
0: PA2 1: PC4 2: PG11
External Bus Interface (EBI) address and data input / output pin 11.
0: PA3 1: PC5 2: PG12
External Bus Interface (EBI) address and data input / output pin 12.
0: PA4 1: PA7 2: PG13
External Bus Interface (EBI) address and data input / output pin 13.
0: PA5 1: PA8 2: PG14
External Bus Interface (EBI) address and data input / output pin 14.
0: PA6 1: PA9 2: PG15
External Bus Interface (EBI) address and data input / output pin 15.
0: PF3 1: PB9 2: PC4 3: PB5
0: PF2 1: PD13 2: PB15 3: PB4
0: PF6 1: PF8 2: PB10 3: PC1
0: PF7 1: PF9 2: PB11 3: PC3
0: PD9 1: PA10 2: PC0 3: PB0
4: PC11 5: PC11
4: PC13 5: PF10
4: PF6 5: PF6
4: PF7 5: PF7
4: PE8
External Bus Interface (EBI) Address Latch Enable output. External Bus Interface (EBI) Hardware Ready Control input. External Bus Interface (EBI) Byte Lane/Enable pin 0. External Bus Interface (EBI) Byte Lane/Enable pin 1. External Bus Interface (EBI) Chip Select output 0.
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EFM32GG11 Family Data Sheet
Pin Definitions
Alternate Functionality EBI_CS1 EBI_CS2 EBI_CS3 EBI_CSTFT EBI_DCLK EBI_DTEN EBI_HSNC EBI_NANDREn EBI_NANDWEn EBI_REn EBI_VSNC EBI_WEn ETH_MDC
LOCATION
0 - 3
4 - 7
0: PD10 1: PA11 2: PC1 3: PB1
4: PE9
0: PD11 1: PA12 2: PC2 3: PB2
4: PE10
0: PD12 1: PB15 2: PC3 3: PB3
4: PE11
0: PA7 1: PF6 2: PB12 3: PA0
0: PA8 1: PF7 2: PH0 3: PA1
0: PA9 1: PD9 2: PH1 3: PA2
0: PA11 1: PD11 2: PH3 3: PA4
0: PC3 1: PD15 2: PB9 3: PC4
4: PC15 5: PF12
0: PC5 1: PD14 2: PA13 3: PC2
4: PC14 5: PF11
0: PF5 1: PA14 2: PA12 3: PC0
4: PF9 5: PF5
0: PA10 1: PD10 2: PH2 3: PA3
0: PF4 1: PA13 2: PC5 3: PB6
4: PF8 5: PF4
0: PB4 1: PD14 2: PC1 3: PA6
Description External Bus Interface (EBI) Chip Select output 1. External Bus Interface (EBI) Chip Select output 2. External Bus Interface (EBI) Chip Select output 3. External Bus Interface (EBI) Chip Select output TFT. External Bus Interface (EBI) TFT Dot Clock pin. External Bus Interface (EBI) TFT Data Enable pin. External Bus Interface (EBI) TFT Horizontal Synchronization pin. External Bus Interface (EBI) NAND Read Enable output. External Bus Interface (EBI) NAND Write Enable output. External Bus Interface (EBI) Read Enable output. External Bus Interface (EBI) TFT Vertical Synchronization pin. External Bus Interface (EBI) Write Enable output. Ethernet Management Data Clock.
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Alternate Functionality ETH_MDIO
ETH_MIICOL
LOCATION
0 - 3
4 - 7
0: PB3 1: PD13 2: PC0 3: PA15
0: PB2 1: PG15 2: PB4
Ethernet Management Data I/O. Ethernet MII Collision Detect.
Description
ETH_MIICRS
0: PB1 1: PG14 2: PB3
Ethernet MII Carrier Sense.
ETH_MIIRXCLK
0: PA15 1: PG7 2: PD12
Ethernet MII Receive Clock.
ETH_MIIRXD0
0: PE12 1: PG11 2: PF9
Ethernet MII Receive Data Bit 0.
ETH_MIIRXD1
0: PE13 1: PG10 2: PD9
Ethernet MII Receive Data Bit 1.
ETH_MIIRXD2
0: PE14 1: PG9 2: PD10
Ethernet MII Receive Data Bit 2.
ETH_MIIRXD3
0: PE15 1: PG8 2: PD11
Ethernet MII Receive Data Bit 3.
ETH_MIIRXDV
0: PE11 1: PG12 2: PF8
Ethernet MII Receive Data Valid.
ETH_MIIRXER
0: PE10 1: PG13 2: PF7
Ethernet MII Receive Error.
ETH_MIITXCLK
0: PA0 1: PG0
Ethernet MII Transmit Clock.
ETH_MIITXD0
0: PA4 1: PG4
Ethernet MII Transmit Data Bit 0.
ETH_MIITXD1
0: PA3 1: PG3
Ethernet MII Transmit Data Bit 1.
EFM32GG11 Family Data Sheet
Pin Definitions
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Alternate Functionality
ETH_MIITXD2
LOCATION
0 - 3
4 - 7
0: PA2 1: PG2
Ethernet MII Transmit Data Bit 2.
Description
ETH_MIITXD3
0: PA1 1: PG1
Ethernet MII Transmit Data Bit 3.
ETH_MIITXEN
0: PA5 1: PG5
Ethernet MII Transmit Enable.
ETH_MIITXER
0: PA6 1: PG6
Ethernet MII Transmit Error.
0: PA4 ETH_RMIICRSDV 1: PD11
Ethernet RMII Carrier Sense / Data Valid.
0: PA3 ETH_RMIIREFCLK 1: PD10
Ethernet RMII Reference Clock.
ETH_RMIIRXD0
0: PA2 1: PD9
Ethernet RMII Receive Data Bit 0.
ETH_RMIIRXD1
0: PA1 1: PF9
Ethernet RMII Receive Data Bit 1.
ETH_RMIIRXER
0: PA5 1: PD12
Ethernet RMII Receive Error.
ETH_RMIITXD0
0: PE15 1: PF7
Ethernet RMII Transmit Data Bit 0.
ETH_RMIITXD1
0: PE14 1: PF6
Ethernet RMII Transmit Data Bit 1.
ETH_RMIITXEN
0: PA0 1: PF8
Ethernet RMII Transmit Enable.
ETH_TSUEXTCLK
0: PB5 1: PD15 2: PC2 3: PF8
Ethernet IEEE1588 External Reference Clock.
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EFM32GG11 Family Data Sheet
Pin Definitions
Rev. 1.0 | 192
Alternate Functionality ETH_TSUTMRTOG ETM_TCLK
ETM_TD0
ETM_TD1
ETM_TD2
ETM_TD3
GPIO_EM4WU0
LOCATION
0 - 3
4 - 7
0: PB6 1: PB15 2: PC3 3: PF9
0: PD7 1: PF8 2: PC6 3: PA6
4: PE11 5: PG15
0: PD6 1: PF9 2: PC7 3: PA2
4: PE12 5: PG14
0: PD3 1: PD13 2: PD3 3: PA3
4: PE13 5: PG13
0: PD4 1: PB15 2: PD4 3: PA4
4: PE14 5: PG12
0: PD5 1: PF3 2: PD5 3: PA5
4: PE15 5: PG11
0: PA0
Description Ethernet IEEE1588 Timer Toggle. Embedded Trace Module ETM clock . Embedded Trace Module ETM data 0. Embedded Trace Module ETM data 1. Embedded Trace Module ETM data 2. Embedded Trace Module ETM data 3. Pin can be used to wake the system up from EM4
GPIO_EM4WU1
0: PA6
Pin can be used to wake the system up from EM4
GPIO_EM4WU2
0: PC9
Pin can be used to wake the system up from EM4
GPIO_EM4WU3
0: PF1
Pin can be used to wake the system up from EM4
GPIO_EM4WU4
0: PF2
Pin can be used to wake the system up from EM4
GPIO_EM4WU5
0: PE13
Pin can be used to wake the system up from EM4
GPIO_EM4WU6
0: PC4
Pin can be used to wake the system up from EM4
EFM32GG11 Family Data Sheet
Pin Definitions
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Alternate Functionality
GPIO_EM4WU7
LOCATION
0 - 3
4 - 7
0: PB11
Description Pin can be used to wake the system up from EM4
EFM32GG11 Family Data Sheet
Pin Definitions
GPIO_EM4WU8
0: PF8
Pin can be used to wake the system up from EM4
GPIO_EM4WU9
0: PE10
Pin can be used to wake the system up from EM4
HFXTAL_N
0: PB14
High Frequency Crystal negative pin. Also used as external optional clock input pin.
HFXTAL_P
0: PB13
High Frequency Crystal positive pin.
I2C0_SCL I2C0_SDA I2C1_SCL I2C1_SDA I2C2_SCL I2C2_SDA IDAC0_OUT
0: PA1 1: PD7 2: PC7 3: PD15
0: PA0 1: PD6 2: PC6 3: PD14
0: PC5 1: PB12 2: PE1 3: PD5
0: PC4 1: PB11 2: PE0 3: PD4
0: PF5 1: PC15 2: PF11 3: PF12
0: PE8 1: PC14 2: PF10 3: PF4
0: PB11
4: PC1 5: PF1 6: PE13 7: PE5
4: PC0 5: PF0 6: PE12 7: PE4
4: PF2 5: PH12 6: PH14 7: PI3
4: PC11 5: PH11 6: PH13 7: PI2
4: PF14 5: PF3 6: PC13 7: PI5
4: PF13 5: PF15 6: PC12 7: PI4
I2C0 Serial Clock Line input / output. I2C0 Serial Data input / output. I2C1 Serial Clock Line input / output. I2C1 Serial Data input / output. I2C2 Serial Clock Line input / output. I2C2 Serial Data input / output. IDAC0 output.
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Alternate Functionality LCD_BEXT
LCD_COM0 LCD_COM1 LCD_COM2 LCD_COM3 LCD_SEG0 LCD_SEG1 LCD_SEG2 LCD_SEG3 LCD_SEG4 LCD_SEG5 LCD_SEG6
EFM32GG11 Family Data Sheet
Pin Definitions
LOCATION
0 - 3
4 - 7
0: PA14
0: PE4
Description
LCD external supply bypass in step down or charge pump mode. If using the LCD in step-down or charge pump mode, a 1 uF (minimum) capacitor between this pin and VSS is required.
To reduce supply ripple, a larger capcitor of approximately 1000 times the total LCD segment capacitance may be used.
If using the LCD with the internal supply source, this pin may be left unconnected or used as a GPIO.
LCD driver common line number 0.
0: PE5
LCD driver common line number 1.
0: PE6
LCD driver common line number 2.
0: PE7
LCD driver common line number 3.
0: PF2
LCD segment line 0.
0: PF3
LCD segment line 1.
0: PF4
LCD segment line 2.
0: PF5
LCD segment line 3.
0: PE8
LCD segment line 4.
0: PE9
LCD segment line 5.
0: PE10
LCD segment line 6.
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Alternate Functionality LCD_SEG7 LCD_SEG8 LCD_SEG9 LCD_SEG10 LCD_SEG11 LCD_SEG12 LCD_SEG13 LCD_SEG14 LCD_SEG15 LCD_SEG16 LCD_SEG17 LCD_SEG18 LCD_SEG19
LOCATION
0 - 3
4 - 7
0: PE11
LCD segment line 7.
0: PE12
LCD segment line 8.
0: PE13
LCD segment line 9.
0: PE14
LCD segment line 10.
0: PE15
LCD segment line 11.
0: PA15
LCD segment line 12.
0: PA0
LCD segment line 13.
0: PA1
LCD segment line 14.
0: PA2
LCD segment line 15.
0: PA3
LCD segment line 16.
0: PA4
LCD segment line 17.
0: PA5
LCD segment line 18.
0: PA6
LCD segment line 19.
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EFM32GG11 Family Data Sheet
Pin Definitions Description
Rev. 1.0 | 196
Alternate Functionality LCD_SEG20 / LCD_COM4
LCD_SEG21 / LCD_COM5
LCD_SEG22 / LCD_COM6
LCD_SEG23 / LCD_COM7
LCD_SEG24
EFM32GG11 Family Data Sheet
Pin Definitions
LOCATION
0 - 3
4 - 7
0: PB3
Description LCD segment line 20. This pin may also be used as LCD COM line 4
0: PB4
LCD segment line 21. This pin may also be used as LCD COM line 5
0: PB5
LCD segment line 22. This pin may also be used as LCD COM line 6
0: PB6
LCD segment line 23. This pin may also be used as LCD COM line 7
0: PF6
LCD segment line 24.
LCD_SEG25
0: PF7
LCD segment line 25.
LCD_SEG26
0: PF8
LCD segment line 26.
LCD_SEG27
0: PF9
LCD segment line 27.
LCD_SEG28
0: PD9
LCD segment line 28.
LCD_SEG29
0: PD10
LCD segment line 29.
LCD_SEG30
0: PD11
LCD segment line 30.
LCD_SEG31
0: PD12
LCD segment line 31.
LCD_SEG32
0: PB0
LCD segment line 32.
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Alternate Functionality LCD_SEG33 LCD_SEG34 LCD_SEG35 LCD_SEG36 LCD_SEG37 LCD_SEG38 LCD_SEG39 LES_ALTEX0 LES_ALTEX1 LES_ALTEX2 LES_ALTEX3 LES_ALTEX4 LES_ALTEX5
LOCATION
0 - 3
4 - 7
0: PB1
LCD segment line 33.
Description
0: PB2
LCD segment line 34.
0: PA7
LCD segment line 35.
0: PA8
LCD segment line 36.
0: PA9
LCD segment line 37.
0: PA10
LCD segment line 38.
0: PA11
LCD segment line 39.
0: PD6
LESENSE alternate excite output 0.
0: PD7
LESENSE alternate excite output 1.
0: PA3
LESENSE alternate excite output 2.
0: PA4
LESENSE alternate excite output 3.
0: PA5
LESENSE alternate excite output 4.
0: PE11
LESENSE alternate excite output 5.
EFM32GG11 Family Data Sheet
Pin Definitions
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Alternate Functionality LES_ALTEX6 LES_ALTEX7 LES_CH0 LES_CH1 LES_CH2 LES_CH3 LES_CH4 LES_CH5 LES_CH6 LES_CH7 LES_CH8 LES_CH9 LES_CH10
LOCATION
0 - 3
4 - 7
0: PE12
Description LESENSE alternate excite output 6.
0: PE13
LESENSE alternate excite output 7.
0: PC0
LESENSE channel 0.
0: PC1
LESENSE channel 1.
0: PC2
LESENSE channel 2.
0: PC3
LESENSE channel 3.
0: PC4
LESENSE channel 4.
0: PC5
LESENSE channel 5.
0: PC6
LESENSE channel 6.
0: PC7
LESENSE channel 7.
0: PC8
LESENSE channel 8.
0: PC9
LESENSE channel 9.
0: PC10
LESENSE channel 10.
EFM32GG11 Family Data Sheet
Pin Definitions
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Alternate Functionality
LES_CH11
LOCATION
0 - 3
4 - 7
0: PC11
LESENSE channel 11.
EFM32GG11 Family Data Sheet
Pin Definitions
Description
LES_CH12
0: PC12
LESENSE channel 12.
LES_CH13
0: PC13
LESENSE channel 13.
LES_CH14
0: PC14
LESENSE channel 14.
LES_CH15
0: PC15
LESENSE channel 15.
LETIM0_OUT0 LETIM0_OUT1 LETIM1_OUT0 LETIM1_OUT1 LEU0_RX LEU0_TX LEU1_RX LEU1_TX
0: PD6 1: PB11 2: PF0 3: PC4
0: PD7 1: PB12 2: PF1 3: PC5
0: PA7 1: PA11 2: PA12 3: PC2
0: PA6 1: PA13 2: PA14 3: PC3
0: PD5 1: PB14 2: PE15 3: PF1
0: PD4 1: PB13 2: PE14 3: PF0
0: PC7 1: PA6 2: PD3 3: PB1
0: PC6 1: PA5 2: PD2 3: PB0
4: PE12 5: PC14 6: PA8 7: PB9
4: PE13 5: PC15 6: PA9 7: PB10
4: PB5 5: PB2 6: PG0 7: PG2
4: PB6 5: PB1 6: PG1 7: PG3
4: PA0 5: PC15
4: PF2 5: PC14
4: PB5 5: PH1
4: PB4 5: PH0
Low Energy Timer LETIM0, output channel 0. Low Energy Timer LETIM0, output channel 1. Low Energy Timer LETIM1, output channel 0. Low Energy Timer LETIM1, output channel 1. LEUART0 Receive input. LEUART0 Transmit output. Also used as receive input in half duplex communication. LEUART1 Receive input. LEUART1 Transmit output. Also used as receive input in half duplex communication.
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Rev. 1.0 | 200
Alternate Functionality LFXTAL_N
LFXTAL_P
EFM32GG11 Family Data Sheet
Pin Definitions
LOCATION
0 - 3
4 - 7
0: PB8
Description
Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin.
0: PB7
Low Frequency Crystal (typically 32.768 kHz) positive pin.
OPA0_N
0: PC5
Operational Amplifier 0 external negative input.
OPA0_P
0: PC4
Operational Amplifier 0 external positive input.
OPA1_N
0: PD7
Operational Amplifier 1 external negative input.
OPA1_P
0: PD6
Operational Amplifier 1 external positive input.
OPA2_N
0: PD3
Operational Amplifier 2 external negative input.
OPA2_OUT
0: PD5
Operational Amplifier 2 output.
OPA2_OUTALT
0: PD0
Operational Amplifier 2 alternative output.
OPA2_P
0: PD4
Operational Amplifier 2 external positive input.
OPA3_N
0: PC7
Operational Amplifier 3 external negative input.
OPA3_OUT
0: PD1
Operational Amplifier 3 output.
OPA3_P
0: PC6
Operational Amplifier 3 external positive input.
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Rev. 1.0 | 201
Alternate Functionality PCNT0_S0IN PCNT0_S1IN PCNT1_S0IN PCNT1_S1IN PCNT2_S0IN PCNT2_S1IN PRS_CH0 PRS_CH1 PRS_CH2 PRS_CH3 PRS_CH4 PRS_CH5 PRS_CH6
LOCATION
0 - 3
4 - 7
0: PC13 1: PE0 2: PC0 3: PD6
4: PA0 5: PB0 6: PB5 7: PB12
0: PC14 1: PE1 2: PC1 3: PD7
4: PA1 5: PB1 6: PB6 7: PB11
0: PA5 1: PB3 2: PD15 3: PC4
4: PA7 5: PA12 6: PB11 7: PG14
0: PA6 1: PB4 2: PB0 3: PC5
4: PA8 5: PA13 6: PB12 7: PG15
0: PD0 1: PE8 2: PB13 3: PF10
4: PC12 5: PI2 6: PI0 7: PH14
0: PD1 1: PE9 2: PB14 3: PF11
4: PC13 5: PI1 6: PH15 7: PH13
0: PA0 1: PF3 2: PC14 3: PF2
0: PA1 1: PF4 2: PC15 3: PE12
0: PC0 1: PF5 2: PE10 3: PE13
0: PC1 1: PE8 2: PE11 3: PA0
0: PC8 1: PB0 2: PF1
Description Pulse Counter PCNT0 input number 0. Pulse Counter PCNT0 input number 1. Pulse Counter PCNT1 input number 0. Pulse Counter PCNT1 input number 1. Pulse Counter PCNT2 input number 0. Pulse Counter PCNT2 input number 1. Peripheral Reflex System PRS, channel 0. Peripheral Reflex System PRS, channel 1. Peripheral Reflex System PRS, channel 2. Peripheral Reflex System PRS, channel 3. Peripheral Reflex System PRS, channel 4.
0: PC9 1: PB1 2: PD6
Peripheral Reflex System PRS, channel 5.
0: PA6 1: PB14 2: PE6
Peripheral Reflex System PRS, channel 6.
EFM32GG11 Family Data Sheet
Pin Definitions
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Alternate Functionality PRS_CH7 PRS_CH8 PRS_CH9 PRS_CH10 PRS_CH11 PRS_CH12 PRS_CH13 PRS_CH14 PRS_CH15 PRS_CH16 PRS_CH17 PRS_CH18 PRS_CH19
LOCATION
0 - 3
4 - 7
0: PB13 1: PA7 2: PE7
Description Peripheral Reflex System PRS, channel 7.
0: PA8 1: PA2 2: PE9
Peripheral Reflex System PRS, channel 8.
0: PA9 1: PA3 2: PB10
Peripheral Reflex System PRS, channel 9.
0: PA10 1: PC2 2: PD4
Peripheral Reflex System PRS, channel 10.
0: PA11 1: PC3 2: PD5
Peripheral Reflex System PRS, channel 11.
0: PA12 1: PB6 2: PD8
Peripheral Reflex System PRS, channel 12.
0: PA13 1: PB9 2: PE14
Peripheral Reflex System PRS, channel 13.
0: PA14 1: PC6 2: PE15
Peripheral Reflex System PRS, channel 14.
0: PA15 1: PC7 2: PF0
Peripheral Reflex System PRS, channel 15.
0: PA4 1: PB12 2: PE4
Peripheral Reflex System PRS, channel 16.
0: PA5 1: PB15 2: PE5
Peripheral Reflex System PRS, channel 17.
0: PB2 1: PC10 2: PC4
Peripheral Reflex System PRS, channel 18.
0: PB3 1: PC11 2: PC5
Peripheral Reflex System PRS, channel 19.
EFM32GG11 Family Data Sheet
Pin Definitions
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Rev. 1.0 | 203
Alternate Functionality PRS_CH20 PRS_CH21 PRS_CH22 PRS_CH23 QSPI0_CS0 QSPI0_CS1 QSPI0_DQ0 QSPI0_DQ1 QSPI0_DQ2 QSPI0_DQ3 QSPI0_DQ4 QSPI0_DQ5 QSPI0_DQ6
LOCATION
0 - 3
4 - 7
0: PB4 1: PC12 2: PE2
Description Peripheral Reflex System PRS, channel 20.
0: PB5 1: PC13 2: PB11
Peripheral Reflex System PRS, channel 21.
0: PB7 1: PE0 2: PF6
Peripheral Reflex System PRS, channel 22.
0: PB8 1: PE1 2: PF7
Peripheral Reflex System PRS, channel 23.
0: PF7 1: PA0 2: PG9
Quad SPI 0 Chip Select 0.
0: PF8 1: PA1 2: PG10
Quad SPI 0 Chip Select 1.
0: PD9 1: PA2 2: PG1
Quad SPI 0 Data 0.
0: PD10 1: PA3 2: PG2
Quad SPI 0 Data 1.
0: PD11 1: PA4 2: PG3
Quad SPI 0 Data 2.
0: PD12 1: PA5 2: PG4
Quad SPI 0 Data 3.
0: PE8 1: PB3 2: PG5
Quad SPI 0 Data 4.
0: PE9 1: PB4 2: PG6
Quad SPI 0 Data 5.
0: PE10 1: PB5 2: PG7
Quad SPI 0 Data 6.
EFM32GG11 Family Data Sheet
Pin Definitions
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Rev. 1.0 | 204
Alternate Functionality QSPI0_DQ7 QSPI0_DQS QSPI0_SCLK SDIO_CD SDIO_CLK SDIO_CMD SDIO_DAT0 SDIO_DAT1 SDIO_DAT2 SDIO_DAT3 SDIO_DAT4 SDIO_DAT5 SDIO_DAT6
LOCATION
0 - 3
4 - 7
0: PE11 1: PB6 2: PG8
Quad SPI 0 Data 7.
0: PF9 1: PE15 2: PG11
Quad SPI 0 Data S.
0: PF6 1: PE14 2: PG0
Quad SPI 0 Serial Clock.
0: PF8 1: PC4 2: PA6 3: PB10
0: PE13 1: PE14
SDIO Card Detect. SDIO Serial Clock.
0: PE12 1: PE15
SDIO Command.
0: PE11 1: PA0
SDIO Data 0.
0: PE10 1: PA1
SDIO Data 1.
0: PE9 1: PA2
SDIO Data 2.
0: PE8 1: PA3
SDIO Data 3.
0: PD12 1: PA4
SDIO Data 4.
0: PD11 1: PA5
SDIO Data 5.
0: PD10 1: PB3
SDIO Data 6.
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EFM32GG11 Family Data Sheet
Pin Definitions Description
Rev. 1.0 | 205
Alternate Functionality SDIO_DAT7 SDIO_WP TIM0_CC0 TIM0_CC1 TIM0_CC2 TIM0_CDTI0 TIM0_CDTI1 TIM0_CDTI2 TIM1_CC0 TIM1_CC1 TIM1_CC2 TIM1_CC3 TIM2_CC0
LOCATION
0 - 3
4 - 7
0: PD9 1: PB4
SDIO Data 7.
EFM32GG11 Family Data Sheet
Pin Definitions
Description
0: PF9 1: PC5 2: PB15 3: PB9
0: PA0 1: PF6 2: PD1 3: PB6
0: PA1 1: PF7 2: PD2 3: PC0
0: PA2 1: PF8 2: PD3 3: PC1
0: PA3 1: PC13 2: PF3 3: PC2
0: PA4 1: PC14 2: PF4 3: PC3
0: PA5 1: PC15 2: PF5 3: PC4
0: PC13 1: PE10 2: PB0 3: PB7
0: PC14 1: PE11 2: PB1 3: PB8
0: PC15 1: PE12 2: PB2 3: PB11
0: PC12 1: PE13 2: PB3 3: PB12
0: PA8 1: PA12 2: PC8 3: PF2
4: PF0 5: PC4 6: PA8 7: PA1
4: PF1 5: PC5 6: PA9 7: PA0
4: PF2 5: PA7 6: PA10 7: PA13
4: PB7
4: PB8
4: PB11
4: PD6 5: PF2 6: PF13 7: PI6
4: PD7 5: PF3 6: PF14 7: PI7
4: PC13 5: PF4 6: PF15 7: PI8
4: PC14 5: PF12 6: PF5 7: PI9
4: PB6 5: PC2 6: PG8 7: PG5
SDIO Write Protect. Timer 0 Capture Compare input / output channel 0. Timer 0 Capture Compare input / output channel 1. Timer 0 Capture Compare input / output channel 2. Timer 0 Complimentary Dead Time Insertion channel 0. Timer 0 Complimentary Dead Time Insertion channel 1. Timer 0 Complimentary Dead Time Insertion channel 2. Timer 1 Capture Compare input / output channel 0. Timer 1 Capture Compare input / output channel 1. Timer 1 Capture Compare input / output channel 2. Timer 1 Capture Compare input / output channel 3. Timer 2 Capture Compare input / output channel 0.
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Alternate Functionality TIM2_CC1 TIM2_CC2 TIM2_CDTI0 TIM2_CDTI1 TIM2_CDTI2 TIM3_CC0 TIM3_CC1 TIM3_CC2 TIM4_CC0 TIM4_CC1 TIM4_CC2 TIM4_CDTI0 TIM4_CDTI1
EFM32GG11 Family Data Sheet
Pin Definitions
LOCATION
0 - 3
4 - 7
0: PA9 1: PA13 2: PC9 3: PE12
4: PC0 5: PC3 6: PG9 7: PG6
0: PA10 1: PA14 2: PC10 3: PE13
4: PC1 5: PC4 6: PG10 7: PG7
0: PB0 1: PD13 2: PE8 3: PG0
0: PB1 1: PD14 2: PE14 3: PG1
0: PB2 1: PD15 2: PE15 3: PG2
0: PE14 1: PE0 2: PE3 3: PE5
4: PA0 5: PA3 6: PA6 7: PD15
0: PE15 1: PE1 2: PE4 3: PE6
4: PA1 5: PA4 6: PD13 7: PB15
0: PA15 1: PE2 2: PE5 3: PE7
4: PA2 5: PA5 6: PD14 7: PB0
0: PF3 1: PF13 2: PF5 3: PI8
4: PF6 5: PF9 6: PD11 7: PE9
0: PF4 1: PF14 2: PI6 3: PI9
4: PF7 5: PD9 6: PD12 7: PE10
0: PF12 1: PF15 2: PI7 3: PI10
4: PF8 5: PD10 6: PE8 7: PE11
0: PD0
Description Timer 2 Capture Compare input / output channel 1. Timer 2 Capture Compare input / output channel 2. Timer 2 Complimentary Dead Time Insertion channel 0. Timer 2 Complimentary Dead Time Insertion channel 1. Timer 2 Complimentary Dead Time Insertion channel 2. Timer 3 Capture Compare input / output channel 0. Timer 3 Capture Compare input / output channel 1. Timer 3 Capture Compare input / output channel 2. Timer 4 Capture Compare input / output channel 0. Timer 4 Capture Compare input / output channel 1. Timer 4 Capture Compare input / output channel 2. Timer 4 Complimentary Dead Time Insertion channel 0.
0: PD1
Timer 4 Complimentary Dead Time Insertion channel 1.
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Alternate Functionality TIM4_CDTI2 TIM5_CC0 TIM5_CC1 TIM5_CC2 TIM6_CC0 TIM6_CC1 TIM6_CC2 TIM6_CDTI0 TIM6_CDTI1 TIM6_CDTI2 U0_CTS U0_RTS U0_RX
EFM32GG11 Family Data Sheet
Pin Definitions
LOCATION
0 - 3
4 - 7
0: PD3
Description Timer 4 Complimentary Dead Time Insertion channel 2.
0: PE4 1: PE7 2: PH13 3: PI0
0: PE5 1: PH11 2: PH14 3: PI1
0: PE6 1: PH12 2: PH15 3: PI2
0: PG0 1: PG6 2: PG12 3: PH2
0: PG1 1: PG7 2: PG13 3: PH3
0: PG2 1: PG8 2: PG14 3: PH4
0: PG3 1: PG9 2: PE4 3: PH5
0: PG4 1: PG10 2: PE5 3: PH6
0: PG5 1: PG11 2: PE6 3: PH7
0: PF8 1: PE2 2: PA5 3: PC13
0: PF9 1: PE3 2: PA6 3: PC12
0: PF7 1: PE1 2: PA4 3: PC15
4: PC8 5: PC11 6: PC14 7: PF12 4: PC9 5: PC12 6: PF10 7: PF13 4: PC10 5: PC13 6: PF11 7: PF14 4: PH8 5: PB13 6: PD1 7: PD4 4: PH9 5: PB14 6: PD2 7: PD5 4: PH10 5: PD0 6: PD3 7: PD6
4: PB7 5: PD5
4: PB8 5: PD6
4: PC5 5: PF2 6: PE4
Timer 5 Capture Compare input / output channel 0. Timer 5 Capture Compare input / output channel 1. Timer 5 Capture Compare input / output channel 2. Timer 6 Capture Compare input / output channel 0. Timer 6 Capture Compare input / output channel 1. Timer 6 Capture Compare input / output channel 2. Timer 6 Complimentary Dead Time Insertion channel 0. Timer 6 Complimentary Dead Time Insertion channel 1. Timer 6 Complimentary Dead Time Insertion channel 2. UART0 Clear To Send hardware flow control input. UART0 Request To Send hardware flow control output. UART0 Receive input.
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Alternate Functionality U0_TX U1_CTS U1_RTS U1_RX U1_TX US0_CLK US0_CS US0_CTS US0_RTS US0_RX US0_TX US1_CLK US1_CS
EFM32GG11 Family Data Sheet
Pin Definitions
LOCATION
0 - 3
4 - 7
0: PF6 1: PE0 2: PA3 3: PC14
4: PC4 5: PF1 6: PD7
0: PC14 1: PF9 2: PB11 3: PE4
4: PC4 5: PH13
0: PC15 1: PF8 2: PB12 3: PE5
4: PC5 5: PH14
0: PC13 1: PF11 2: PB10 3: PE3
4: PE13 5: PH12
0: PC12 1: PF10 2: PB9 3: PE2
4: PE12 5: PH11
0: PE12 1: PE5 2: PC9 3: PC15
4: PB13 5: PA12 6: PG14
0: PE13 1: PE4 2: PC8 3: PC14
4: PB14 5: PA13 6: PG15
0: PE14 1: PE3 2: PC7 3: PC13
4: PB6 5: PB11 6: PH0
0: PE15 1: PE2 2: PC6 3: PC12
4: PB5 5: PD6 6: PH1
0: PE11 1: PE6 2: PC10 3: PE12
4: PB8 5: PC1 6: PG13
0: PE10 1: PE7 2: PC11 3: PE13
4: PB7 5: PC0 6: PG12
0: PB7 1: PD2 2: PF0 3: PC15
4: PC3 5: PB11 6: PE5
0: PB8 1: PD3 2: PF1 3: PC14
4: PC0 5: PE4 6: PB2
Description UART0 Transmit output. Also used as receive input in half duplex communication.
UART1 Clear To Send hardware flow control input.
UART1 Request To Send hardware flow control output.
UART1 Receive input.
UART1 Transmit output. Also used as receive input in half duplex communication.
USART0 clock input / output.
USART0 chip select input / output.
USART0 Clear To Send hardware flow control input.
USART0 Request To Send hardware flow control output. USART0 Asynchronous Receive. USART0 Synchronous mode Master Input / Slave Output (MISO). USART0 Asynchronous Transmit. Also used as receive input in half duplex communication. USART0 Synchronous mode Master Output / Slave Input (MOSI). USART1 clock input / output.
USART1 chip select input / output.
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Rev. 1.0 | 209
Alternate Functionality US1_CTS US1_RTS US1_RX US1_TX US2_CLK US2_CS US2_CTS US2_RTS US2_RX US2_TX US3_CLK US3_CS US3_CTS
EFM32GG11 Family Data Sheet
Pin Definitions
LOCATION
0 - 3
4 - 7
0: PB9 1: PD4 2: PF3 3: PC6
4: PC12 5: PB13 6: PH2
0: PB10 1: PD5 2: PF4 3: PC7
4: PC13 5: PB14 6: PH3
0: PC1 1: PD1 2: PD6 3: PF7
4: PC2 5: PA0 6: PA2
0: PC0 1: PD0 2: PD7 3: PF6
4: PC1 5: PF2 6: PA14
0: PC4 1: PB5 2: PA9 3: PA15
4: PF8 5: PF2
0: PC5 1: PB6 2: PA10 3: PB11
4: PF9 5: PF5
0: PC1 1: PB12 2: PA11 3: PB10
4: PC12 5: PD6
0: PC0 1: PB15 2: PA12 3: PC14
4: PC13 5: PD8
0: PC3 1: PB4 2: PA8 3: PA14
4: PF7 5: PF1
0: PC2 1: PB3 2: PA7 3: PA13
4: PF6 5: PF0
0: PA2 1: PD7 2: PD4 3: PG8
4: PG2 5: PI14
0: PA3 1: PE4 2: PC14 3: PC0
4: PG3 5: PI15
0: PA4 1: PE5 2: PD6 3: PG10
4: PG4 5: PG9
Description USART1 Clear To Send hardware flow control input.
USART1 Request To Send hardware flow control output.
USART1 Asynchronous Receive. USART1 Synchronous mode Master Input / Slave Output (MISO). USART1 Asynchronous Transmit. Also used as receive input in half duplex communication. USART1 Synchronous mode Master Output / Slave Input (MOSI). USART2 clock input / output.
USART2 chip select input / output.
USART2 Clear To Send hardware flow control input.
USART2 Request To Send hardware flow control output.
USART2 Asynchronous Receive. USART2 Synchronous mode Master Input / Slave Output (MISO). USART2 Asynchronous Transmit. Also used as receive input in half duplex communication. USART2 Synchronous mode Master Output / Slave Input (MOSI). USART3 clock input / output.
USART3 chip select input / output.
USART3 Clear To Send hardware flow control input.
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Rev. 1.0 | 210
Alternate Functionality US3_RTS US3_RX US3_TX US4_CLK US4_CS US4_CTS US4_RTS US4_RX US4_TX US5_CLK US5_CS US5_CTS US5_RTS
EFM32GG11 Family Data Sheet
Pin Definitions
LOCATION
0 - 3
4 - 7
0: PA5 1: PC1 2: PA14 3: PC15
4: PG5 5: PG11
0: PA1 1: PE7 2: PB7 3: PG7
4: PG1 5: PI13
0: PA0 1: PE6 2: PB3 3: PG6
4: PG0 5: PI12
0: PC4 1: PD11 2: PI2 3: PI8
4: PH6
0: PC5 1: PD12 2: PI3 3: PI9
4: PH7
0: PA7 1: PD13 2: PI4 3: PI10
4: PH8
0: PA8 1: PD14 2: PI5 3: PI11
4: PH9
0: PB8 1: PD10 2: PI1 3: PI7
4: PH5
0: PB7 1: PD9 2: PI0 3: PI6
4: PH4
0: PB11 1: PD13 2: PF13 3: PH12
0: PB13 1: PD14 2: PF12 3: PH13
0: PB14 1: PD15 2: PF11 3: PH14
0: PB12 1: PB15 2: PF10 3: PH15
Description USART3 Request To Send hardware flow control output.
USART3 Asynchronous Receive. USART3 Synchronous mode Master Input / Slave Output (MISO). USART3 Asynchronous Transmit. Also used as receive input in half duplex communication. USART3 Synchronous mode Master Output / Slave Input (MOSI). USART4 clock input / output.
USART4 chip select input / output.
USART4 Clear To Send hardware flow control input.
USART4 Request To Send hardware flow control output.
USART4 Asynchronous Receive. USART4 Synchronous mode Master Input / Slave Output (MISO). USART4 Asynchronous Transmit. Also used as receive input in half duplex communication. USART4 Synchronous mode Master Output / Slave Input (MOSI). USART5 clock input / output.
USART5 chip select input / output.
USART5 Clear To Send hardware flow control input.
USART5 Request To Send hardware flow control output.
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Alternate Functionality US5_RX
US5_TX
USB_DM
EFM32GG11 Family Data Sheet
Pin Definitions
LOCATION
0 - 3
4 - 7
0: PE9 1: PA7 2: PB1 3: PH11
0: PE8 1: PA6 2: PF15 3: PH10
0: PF10
Description USART5 Asynchronous Receive. USART5 Synchronous mode Master Input / Slave Output (MISO).
USART5 Asynchronous Transmit. Also used as receive input in half duplex communication. USART5 Synchronous mode Master Output / Slave Input (MOSI).
USB D- pin.
USB_DP
0: PF11
USB D+ pin.
USB_ID
0: PF12
USB ID pin.
USB_VBUSEN
0: PF5
USB 5 V VBUS enable.
VDAC0_EXT
0: PD6
Digital to analog converter VDAC0 external reference input pin.
VDAC0_OUT0 / OPA0_OUT
0: PB11
Digital to Analog Converter DAC0 output channel number 0.
VDAC0_OUT0ALT / OPA0_OUTALT
0: PC0 1: PC1 2: PC2 3: PC3
VDAC0_OUT1 / OPA1_OUT
0: PB12
4: PD0
Digital to Analog Converter DAC0 alternative output for channel 0. Digital to Analog Converter DAC0 output channel number 1.
VDAC0_OUT1ALT / OPA1_OUTALT
0: PC12 1: PC13 2: PC14 3: PC15
WTIM0_CC0
0: PE4 1: PA6 2: PG2 3: PG8
WTIM0_CC1
0: PE5 1: PD13 2: PG3 3: PG9
4: PD1
4: PC15 5: PB0 6: PB3 7: PC1
4: PF0 5: PB1 6: PB4 7: PC2
Digital to Analog Converter DAC0 alternative output for channel 1. Wide timer 0 Capture Compare input / output channel 0. Wide timer 0 Capture Compare input / output channel 1.
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Alternate Functionality WTIM0_CC2 WTIM0_CDTI0 WTIM0_CDTI1 WTIM0_CDTI2 WTIM1_CC0 WTIM1_CC1 WTIM1_CC2 WTIM1_CC3 WTIM2_CC0 WTIM2_CC1 WTIM2_CC2 WTIM3_CC0 WTIM3_CC1
EFM32GG11 Family Data Sheet
Pin Definitions
LOCATION
0 - 3
4 - 7
0: PE6 1: PD14 2: PG4 3: PG10
4: PF1 5: PB2 6: PB5 7: PC3
0: PE10 1: PD15 2: PA12 3: PG11
4: PD4
0: PE11 1: PG0 2: PA13 3: PG12
4: PD5
0: PE12 1: PG1 2: PA14 3: PG13
4: PD6
0: PB13 1: PD2 2: PD6 3: PC7
4: PE3 5: PE7 6: PH8 7: PH12
0: PB14 1: PD3 2: PD7 3: PE0
4: PE4 5: PI0 6: PH9 7: PH13
0: PD0 1: PD4 2: PD8 3: PE1
4: PE5 5: PI1 6: PH10 7: PH14
0: PD1 1: PD5 2: PC6 3: PE2
4: PE6 5: PI2 6: PH11 7: PH15
0: PA9 1: PA12 2: PB9 3: PB12
4: PG14 5: PD3 6: PH4 7: PH7
0: PA10 1: PA13 2: PB10 3: PG12
4: PG15 5: PD4 6: PH5 7: PH8
0: PA11 1: PA14 2: PB11 3: PG13
4: PH0 5: PD5 6: PH6 7: PH9
0: PD9 1: PC8 2: PC11 3: PC14
4: PI3 5: PI6 6: PB6 7: PF13
0: PD10 1: PC9 2: PC12 3: PF10
4: PI4 5: PI7 6: PF4 7: PF14
Description Wide timer 0 Capture Compare input / output channel 2. Wide timer 0 Complimentary Dead Time Insertion channel 0. Wide timer 0 Complimentary Dead Time Insertion channel 1. Wide timer 0 Complimentary Dead Time Insertion channel 2. Wide timer 1 Capture Compare input / output channel 0. Wide timer 1 Capture Compare input / output channel 1. Wide timer 1 Capture Compare input / output channel 2. Wide timer 1 Capture Compare input / output channel 3. Wide timer 2 Capture Compare input / output channel 0. Wide timer 2 Capture Compare input / output channel 1. Wide timer 2 Capture Compare input / output channel 2. Wide timer 3 Capture Compare input / output channel 0. Wide timer 3 Capture Compare input / output channel 1.
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EFM32GG11 Family Data Sheet
Pin Definitions
Alternate Functionality
WTIM3_CC2
LOCATION
0 - 3
4 - 7
0: PD11 1: PC10 2: PC13 3: PF11
4: PI5 5: PF6 6: PF12 7: PF15
Description Wide timer 3 Capture Compare input / output channel 2.
Certain alternate function locations may have non-interference priority. These locations will take precedence over any other functions selected on that pin (i.e. another alternate function enabled to the same pin inadvertently).
Some alternate functions may also have high speed priority on certain locations. These locations ensure the fastest possible paths to the pins for timing-critical signals.
The following table lists the alternate functions and locations with special priority.
Table 5.22. Alternate Functionality Priority
Alternate Functionality CMU_CLK2
CMU_CLKI0
ETH_RMIICRSDV
ETH_RMIIREFCLK
ETH_RMIIRXD0
ETH_RMIIRXD1
ETH_RMIIRXER
ETH_RMIITXD0
ETH_RMIITXD1
ETH_RMIITXEN QSPI0_CS0 QSPI0_CS1 QSPI0_DQ0 QSPI0_DQ1 QSPI0_DQ2 QSPI0_DQ3 QSPI0_DQ4 QSPI0_DQ5 QSPI0_DQ6 QSPI0_DQ7
Location
1: PA3 5: PD10
1: PA3 5: PD10
0: PA4 1: PD11
0: PA3 1: PD10
0: PA2 1: PD9
0: PA1 1: PF9
0: PA5 1: PD12
0: PE15 1: PF7
0: PE14 1: PF6
0: PA0 1: PF8
0: PF7
0: PF8
0: PD9
0: PD10
0: PD11
0: PD12
0: PE8
0: PE9
0: PE10
0: PE11
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Priority
High Speed High Speed
High Speed High Speed
High Speed High Speed
High Speed High Speed
High Speed High Speed
High Speed High Speed
High Speed High Speed
High Speed High Speed
High Speed High Speed
High Speed High Speed
High Speed
High Speed
High Speed
High Speed
High Speed
High Speed
High Speed
High Speed
High Speed
High Speed
Rev. 1.0 | 214
Alternate Functionality QSPI0_DQS QSPI0_SCLK SDIO_CLK SDIO_CMD SDIO_DAT0 SDIO_DAT1 SDIO_DAT2 SDIO_DAT3 SDIO_DAT4 SDIO_DAT5 SDIO_DAT6 SDIO_DAT7 TIM0_CC0 TIM0_CC1 TIM0_CC2 TIM0_CDTI0 TIM0_CDTI1 TIM0_CDTI2 TIM2_CC0 TIM2_CC1 TIM2_CC2 TIM2_CDTI0 TIM2_CDTI1 TIM2_CDTI2 TIM4_CC0 TIM4_CC1 TIM4_CC2 TIM4_CDTI0 TIM4_CDTI1 TIM4_CDTI2 TIM6_CC0 TIM6_CC1 TIM6_CC2 TIM6_CDTI0 TIM6_CDTI1 TIM6_CDTI2
Location 0: PF9 0: PF6 0: PE13 0: PE12 0: PE11 0: PE10 0: PE9 0: PE8 0: PD12 0: PD11 0: PD10 0: PD9 3: PB6 3: PC0 3: PC1 1: PC13 1: PC14 1: PC15 0: PA8 0: PA9 0: PA10 0: PB0 0: PB1 0: PB2 0: PF3 0: PF4 0: PF12 0: PD0 0: PD1 0: PD3 0: PG0 0: PG1 0: PG2 0: PG3 0: PG4 0: PG5
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Priority High Speed High Speed High Speed High Speed High Speed High Speed High Speed High Speed High Speed High Speed High Speed High Speed Non-interference Non-interference Non-interference Non-interference Non-interference Non-interference Non-interference Non-interference Non-interference Non-interference Non-interference Non-interference Non-interference Non-interference Non-interference Non-interference Non-interference Non-interference Non-interference Non-interference Non-interference Non-interference Non-interference Non-interference
EFM32GG11 Family Data Sheet
Pin Definitions
Rev. 1.0 | 215
Alternate Functionality US2_CLK US2_CS US2_RX US2_TX
Location
4: PF8 5: PF2
4: PF9 5: PF5
4: PF7 5: PF1
4: PF6 5: PF0
Priority
High Speed High Speed
High Speed High Speed
High Speed High Speed
High Speed High Speed
EFM32GG11 Family Data Sheet
Pin Definitions
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Rev. 1.0 | 216
EFM32GG11 Family Data Sheet
Pin Definitions
5.22 Analog Port (APORT) Client Maps
The Analog Port (APORT) is an infrastructure used to connect chip pins with on-chip analog clients such as analog comparators, ADCs, DACs, etc. The APORT consists of a set of shared buses, switches, and control logic needed to configurably implement the signal routing. Figure 5.20 APORT Connection Diagram on page 217 shows the APORT routing for this device family (note that available features may vary by part number). A complete description of APORT functionality can be found in the Reference Manual.
IOVDD_1
IOVDD_0
PF0 PF1 PF2 PF3 PF4 PF12 PF13 PF14 PF15 PF5
PF6 PF7 PF8 PF9
PE8 PE9 PE10 PE11 PE12 PE13
PE14 PE15
IOVDD_2
IOVDD_0
CX CY
DX DY
PA15 PA0 PA1 PA2 PA3 PA4 PA5 PA6
PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PC0
PC1
VDAC0_OUT0ALT VDAC0_OUT0ALT
PC2
VDAC0_OUT0ALT
VDAC0_OU0ALTT PC3
PC4
PC5
AX AY BX BY ACMP2X ACMP2Y
ACMP0X ACMP0Y
IDAC0_OUTPAD 1X 1Y
IDAC0
POS ACMP2
NEG
0X 1X 2X 3X 4X NEXT1 NEXT0
0Y 1Y 2Y 3Y 4Y
NEXT1 NEXT0
1X
1Y
CEXT
3X
3Y
2X
CSEN
2Y CEXT_SENSE 4X
4Y
POS ACMP0
NEG
0X 1X 2X 3X 4X NEXT1 NEXT0
0Y 1Y 2Y 3Y 4Y NEXT1 NEXT0
ADC0
POS
NEG EXTP EXTN
0X 1X 2X 3X 4X NEXT2 NEXT0
0Y 1Y 2Y 3Y 4Y NEXT3 NEXT1
OUT0ALT OUT0ALT
OUT0ALT OUT0ALT
OPA0_P
OPA0_N
ADC1X ADC1Y ACMP3X ACMP3Y
CCBDBDAAAAAAYYXXYYXXDDDDCCCC1100YXYX
0X 1X 2X 3X 4X NEXT2 NEXT0
0Y 1Y 2Y 3Y 4Y NEXT3 NEXT1
POS NEG ADC1
EXTP EXTN
POS
OPA0_P 1X 2X 3X 4X
NEG OPA0
OPA0_N 1Y 2Y 3Y 4Y
OUT
OUT0 OUT0ALT OUT1 OUT2 OUT3 OUT4
NEXT0
POS
NEG OPA1
OUT
OPA1_P 1X 2X 3X 4X
OPA1_N 1Y 2Y 3Y 4Y
OUT1 OUT1ALT OUT1 OUT2 OUT3 OUT4 NEXT1
nX, nY
APORTnX, APORTnY
AX, BY, ... BUSAX, BUSBY, ...
ADC0X, ADC1Y, ...
ACMP0X, ACMP3Y, ...
BUSADC0X, BUSADC1Y, ...
BUSACMP0X, BUSACMP3Y, ...
OUT0 IDAC0_OUTPAD OUT1
ADC0X ADC0Y
DBBAACCDYYYXXYXX
OUT2ALT OUT0ALT OUT1ALT OUT3 OPA2_N OPA2_P
ACMP1X ACMP1Y
0X 1X 2X 3X 4X NEXT1 NEXT0 0Y 1Y 2Y 3Y 4Y
NEXT1 NEXT0
POS
ACMP1 NEG
OUT1ALT OUT1ALT
0X 1X 2X 3X 4X
NEXT1 NEXT0
0Y 1Y 2Y 3Y 4Y NEXT1 NEXT0
OUT1ALT
POS
OUT1ALT
ACMP3 NEG
OPA2_P 1X 2X 3X 4X
POS
OPA2_N 1Y 2Y 3Y 4Y
OUT2 OUT2ALT
OUT1 OUT2 OUT3 OUT4 NEXT2
NEG OPA2
OUT
OPA3_P 1X 2X 3X 4X
POS
OPA3_N 1Y 2Y 3Y 4Y
NEG OPA3
OUT3 OUT3ALT
OUT1 OUT2 OUT3 OUT4 NEXT3
OUT
VDAC0_OUT1ALT VDAC0_OUT1ALT
PC15 PF11 PF10
PC14
VDAC0_OUT1ALT VDAC0_OUT1ALT
PC13 PC12
PC11 PC10 PC9 PC8
PE7 PE6 PE5 PE4
PE1 PE0
OPA3_P PC7
OPA3_N PC6
ADC_EXTN
OPA1_N
PD7
ADC_EXTP
OPA1_P
PD6
PD5 OUT2
VDAC0_OUT2ALT VDAC0_OUT0ALT VDAC0_OUT1ALT
PD4
PD2 PD3
PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 PH8 PH9 PH10 PH11 PH12 PH13 PH14 PH15 PB13 PB14 PD0 PD1
PB12
PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PB9 PB10 PB11
Figure 5.20. APORT Connection Diagram
Client maps for each analog circuit using the APORT are shown in the following tables. The maps are organized by bus, and show the peripheral's port connection, the shared bus, and the connection from specific bus channel numbers to GPIO pins.
In general, enumerations for the pin selection field in an analog peripheral's register can be determined by finding the desired pin connection in the table and then combining the value in the Port column (APORT__), and the channel identifier (CH__). For example, if pin
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Rev. 1.0 | 217
EFM32GG11 Family Data Sheet
Pin Definitions
PF7 is available on port APORT2X as CH23, the register field enumeration to connect to PF7 would be APORT2XCH23. The shared bus used by this connection is indicated in the Bus column.
Table 5.23. ACMP0 Bus and Pin Mapping
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APORT4Y APORT4X APORT3Y APORT3X APORT2Y APORT2X APORT1Y APORT1X APORT0Y APORT0X Port
BUSDY BUSDX BUSCY BUSCX BUSBY BUSBX BUSAY BUSAX BUSACMP0Y BUSACMP0X Bus
PF15
PF15
PB15
PB15
CH31
PF14
PF14
PB14
PB14
CH30
PF13
PF13
PB13
PB13
CH29
PF12
PF12
PB12
PB12
CH28
PF11
PF11
PB11
PB11
CH27
PF10
PF10
PB10
PB10
CH26
PF9
PF9
PB9
PB9
CH25
PF8
PF8
CH24
PF7
PF7
CH23
PF6
PF6
PB6
PB6
CH22
PF5
PF5
PB5
PB5
CH21
PF4
PF4
PB4
PB4
CH20
PF3
PF3
PB3
PB3
CH19
PF2
PF2
PB2
PB2
CH18
PF1
PF1
PB1
PB1
CH17
PF0
PF0
PB0
PB0
CH16
PE15
PE15
PA15
PA15
CH15
PE14
PE14
PA14
PA14
CH14
PE13
PE13
PA13
PA13
CH13
PE12
PE12
PA12
PA12
CH12
PE11
PE11
PA11
PA11
CH11
PE10
PE10
PA10
PA10
CH10
PE9
PE9
PA9
PA9
CH9
PE8
PE8
PA8
PA8
CH8
PE7
PE7
PA7
PA7
PC7
PC7
CH7
PE6
PE6
PA6
PA6
PC6
PC6
CH6
PE5
PE5
PA5
PA5
PC5
PC5
CH5
PE4
PE4
PA4
PA4
PC4
PC4
CH4
PA3
PA3
PC3
PC3
CH3
Rev. 1.0 | 218
PA2
PA2
PC2
PC2
CH2
PE1
PE1
PA1
PA1
PC1
PC1
CH1
PE0
PE0
PA0
PA0
PC0
PC0
CH0
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APORT4Y APORT4X APORT3Y APORT3X APORT2Y APORT2X APORT1Y APORT1X APORT0Y APORT0X Port
BUSDY BUSDX BUSCY BUSCX BUSBY BUSBX BUSAY BUSAX BUSACMP1Y BUSACMP1X Bus
PF15
PF15
PB15
PB15
CH31
PF14
PF14
PB14
PB14
CH30
PF13
PF13
PB13
PB13
CH29
PF12
PF12
PB12
PB12
CH28
PF11
PF11
PB11
PB11
CH27
PF10
PF10
PB10
PB10
CH26
PF9
PF9
PB9
PB9
CH25
PF8
PF8
CH24
PF7
PF7
CH23
Table 5.24. ACMP1 Bus and Pin Mapping
PF6
PF6
PB6
PB6
CH22
PF5
PF5
PB5
PB5
CH21
PF4
PF4
PB4
PB4
CH20
PF3
PF3
PB3
PB3
CH19
PF2
PF2
PB2
PB2
CH18
PF1
PF1
PB1
PB1
CH17
PF0
PF0
PB0
PB0
CH16
PE15
PE15
PA15
PA15
CH15
PE14
PE14
PA14
PA14
CH14
PE13
PE13
PA13
PA13
CH13
PE12
PE12
PA12
PA12
CH12
PE11
PE11
PA11
PA11
CH11
PE10
PE10
PA10
PA10
CH10
PE9
PE9
PA9
PA9
CH9
PE8
PE8
PA8
PA8
CH8
PE7
PE7
PA7
PA7
PC15
PC15
CH7
EFM32GG11 Family Data Sheet
Pin Definitions
PE6
PE6
PA6
PA6
PC14
PC14
CH6
PE5
PE5
PA5
PA5
PC13
PC13
CH5
PE4
PE4
PA4
PA4
PC12
PC12
CH4
PA3
PA3
PC11
PC11
CH3
Rev. 1.0 | 219
PA2
PA2
PC10
PC10
CH2
PE1
PE1
PA1
PA1
PC9
PC9
CH1
PE0
PE0
PA0
PA0
PC8
PC8
CH0
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APORT4Y APORT4X APORT3Y APORT3X APORT2Y APORT2X APORT1Y APORT1X APORT0Y APORT0X Port
BUSDY BUSDX BUSCY BUSCX BUSBY BUSBX BUSAY BUSAX BUSACMP2Y BUSACMP2X Bus
PF15
PF15
PB15
PB15
CH31
PF14
PF14
PB14
PB14
CH30
PF13
PF13
PB13
PB13
CH29
PF12
PF12
PB12
PB12
CH28
PF11
PF11
PB11
PB11
CH27
PF10
PF10
PB10
PB10
CH26
PF9
PF9
PB9
PB9
CH25
PF8
PF8
CH24
PF7
PF7
CH23
Table 5.25. ACMP2 Bus and Pin Mapping
PF6
PF6
PB6
PB6
CH22
PF5
PF5
PB5
PB5
CH21
PF4
PF4
PB4
PB4
CH20
PF3
PF3
PB3
PB3
CH19
PF2
PF2
PB2
PB2
CH18
PF1
PF1
PB1
PB1
CH17
PF0
PF0
PB0
PB0
CH16
PE15
PE15
PA15
PA15
CH15
PE14
PE14
PA14
PA14
CH14
PE13
PE13
PA13
PA13
CH13
PE12
PE12
PA12
PA12
CH12
PE11
PE11
PA11
PA11
CH11
PE10
PE10
PA10
PA10
CH10
PE9
PE9
PA9
PA9
CH9
PE8
PE8
PA8
PA8
CH8
PE7
PE7
PA7
PA7
PG7
PG7
CH7
EFM32GG11 Family Data Sheet
Pin Definitions
PE6
PE6
PA6
PA6
PG6
PG6
CH6
PE5
PE5
PA5
PA5
PG5
PG5
CH5
PE4
PE4
PA4
PA4
PG4
PG4
CH4
PA3
PA3
PG3
PG3
CH3
Rev. 1.0 | 220
PA2
PA2
PG2
PG2
CH2
PE1
PE1
PA1
PA1
PG1
PG1
CH1
PE0
PE0
PA0
PA0
PG0
PG0
CH0
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APORT4Y APORT4X APORT3Y APORT3X APORT2Y APORT2X APORT1Y APORT1X APORT0Y APORT0X Port
BUSDY BUSDX BUSCY BUSCX BUSBY BUSBX BUSAY BUSAX BUSACMP3Y BUSACMP3X Bus
PF15
PF15
PB15
PB15
CH31
PF14
PF14
PB14
PB14
CH30
PF13
PF13
PB13
PB13
CH29
PF12
PF12
PB12
PB12
CH28
PF11
PF11
PB11
PB11
CH27
PF10
PF10
PB10
PB10
CH26
PF9
PF9
PB9
PB9
CH25
PF8
PF8
CH24
PF7
PF7
CH23
Table 5.26. ACMP3 Bus and Pin Mapping
PF6
PF6
PB6
PB6
CH22
PF5
PF5
PB5
PB5
CH21
PF4
PF4
PB4
PB4
CH20
PF3
PF3
PB3
PB3
CH19
PF2
PF2
PB2
PB2
CH18
PF1
PF1
PB1
PB1
CH17
PF0
PF0
PB0
PB0
CH16
PE15
PE15
PA15
PA15
CH15
PE14
PE14
PA14
PA14
CH14
PE13
PE13
PA13
PA13
CH13
PE12
PE12
PA12
PA12
CH12
PE11
PE11
PA11
PA11
CH11
PE10
PE10
PA10
PA10
CH10
PE9
PE9
PA9
PA9
CH9
PE8
PE8
PA8
PA8
CH8
PE7
PE7
PA7
PA7
PH15
PH15
CH7
EFM32GG11 Family Data Sheet
Pin Definitions
PE6
PE6
PA6
PA6
PH14
PH14
CH6
PE5
PE5
PA5
PA5
PH13
PH13
CH5
PE4
PE4
PA4
PA4
PH12
PH12
CH4
PA3
PA3
PH11
PH11
CH3
Rev. 1.0 | 221
PA2
PA2
PH10
PH10
CH2
PE1
PE1
PA1
PA1
PH9
PH9
CH1
PE0
PE0
PA0
PA0
PH8
PH8
CH0
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APORT4Y APORT4X APORT3Y APORT3X APORT2Y APORT2X APORT1Y APORT1X APORT0Y APORT0X Port
BUSDY BUSDX BUSCY BUSCX BUSBY BUSBX BUSAY BUSAX BUSADC0Y BUSADC0X Bus
PF15
PF15
PB15
PB15
CH31
PF14
PF14
PB14
PB14
CH30
PF13
PF13
PB13
PB13
CH29
PF12
PF12
PB12
PB12
CH28
PF11
PF11
PB11
PB11
CH27
PF10
PF10
PB10
PB10
CH26
PF9
PF9
PB9
PB9
CH25
PF8
PF8
CH24
PF7
PF7
CH23
PF6
PF6
PB6
PB6
CH22
Table 5.27. ADC0 Bus and Pin Mapping
PF5
PF5
PB5
PB5
CH21
PF4
PF4
PB4
PB4
CH20
PF3
PF3
PB3
PB3
CH19
PF2
PF2
PB2
PB2
CH18
PF1
PF1
PB1
PB1
CH17
PF0
PF0
PB0
PB0
CH16
PE15
PE15
PA15
PA15
CH15
PE14
PE14
PA14
PA14
CH14
PE13
PE13
PA13
PA13
CH13
PE12
PE12
PA12
PA12
CH12
PE11
PE11
PA11
PA11
CH11
PE10
PE10
PA10
PA10
CH10
PE9
PE9
PA9
PA9
CH9
PE8
PE8
PA8
PA8
CH8
PE7
PE7
PA7
PA7
PD7
PD7
CH7
EFM32GG11 Family Data Sheet
Pin Definitions
PE6
PE6
PA6
PA6
PD6
PD6
CH6
PE5
PE5
PA5
PA5
PD5
PD5
CH5
PE4
PE4
PA4
PA4
PD4
PD4
CH4
PA3
PA3
PD3
PD3
CH3
Rev. 1.0 | 222
PA2
PA2
PD2
PD2
CH2
PE1
PE1
PA1
PA1
PD1
PD1
CH1
PE0
PE0
PA0
PA0
PD0
PD0
CH0
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APORT4Y APORT4X APORT3Y APORT3X APORT2Y APORT2X APORT1Y APORT1X APORT0Y APORT0X Port
BUSDY BUSDX BUSCY BUSCX BUSBY BUSBX BUSAY BUSAX BUSADC1Y BUSADC1X Bus
PF15
PF15
PB15
PB15
CH31
PF14
PF14
PB14
PB14
CH30
PF13
PF13
PB13
PB13
CH29
PF12
PF12
PB12
PB12
CH28
PF11
PF11
PB11
PB11
CH27
PF10
PF10
PB10
PB10
CH26
PF9
PF9
PB9
PB9
CH25
PF8
PF8
CH24
PF7
PF7
CH23
PF6
PF6
PB6
PB6
CH22
Table 5.28. ADC1 Bus and Pin Mapping
PF5
PF5
PB5
PB5
CH21
PF4
PF4
PB4
PB4
CH20
PF3
PF3
PB3
PB3
CH19
PF2
PF2
PB2
PB2
CH18
PF1
PF1
PB1
PB1
CH17
PF0
PF0
PB0
PB0
CH16
PE15
PE15
PA15
PA15
CH15
PE14
PE14
PA14
PA14
CH14
PE13
PE13
PA13
PA13
CH13
PE12
PE12
PA12
PA12
CH12
PE11
PE11
PA11
PA11
CH11
PE10
PE10
PA10
PA10
CH10
PE9
PE9
PA9
PA9
CH9
PE8
PE8
PA8
PA8
CH8
PE7
PE7
PA7
PA7
PH7
PH7
CH7
EFM32GG11 Family Data Sheet
Pin Definitions
PE6
PE6
PA6
PA6
PH6
PH6
CH6
PE5
PE5
PA5
PA5
PH5
PH5
CH5
PE4
PE4
PA4
PA4
PH4
PH4
CH4
PA3
PA3
PH3
PH3
CH3
Rev. 1.0 | 223
PA2
PA2
PH2
PH2
CH2
PE1
PE1
PA1
PA1
PH1
PH1
CH1
PE0
PE0
PA0
PA0
PH0
PH0
CH0
Rev. 1.0 | 224
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APORT1Y APORT1X Port
BUSCY BUSCX Bus
PF15
CH31
PF14 CH30
PF13
CH29
PF12 CH28
PF11
CH27
PF10 CH26
PF9
CH25
PF8 CH24
PF7
CH23
PF6 CH22
PF5
CH21
PF4 CH20
PF3
CH19
PF2 CH18
PF1
CH17
PF0 CH16
PE15
CH15
PE14 CH14
PE13
CH13
PE12 CH12
PE11
CH11
PE10 CH10
PE9
CH9
PE8 CH8
PE7
CH7
PE6 CH6
PE5
CH5
PE4 CH4
CH3
CH2
PE1
CH1
PE0 CH0
Table 5.30. IDAC0 Bus and Pin Mapping
APORT4Y APORT4X APORT2Y APORT2X
BUSDY BUSDX BUSBY BUSBX
PF15
PB15
PF14
PB14
PF13
PB13
PF12
PB12
PF11
PB11
PF10
PB10
PF9
PB9
PF8
PF7
PF6
PB6
PF5
PB5
PF4
PB4
PF3
PB3
PF2
PB2
PF1
PB1
PF0
PB0
PE15
PA15
PE14
PA14
PE13
PA13
PE12
PA12
PE11
PA11
PE10
PA10
PE9
PA9
PE8
PA8
PE7
PA7
PE6
PA6
PE5
PA5
PE4
PA4
PA3
PA2
PE1
PA1
PE0
PA0
CEXT_SENSE
APORT3Y APORT3X APORT1Y APORT1X
BUSCY BUSCX BUSAY BUSAX
PF15
PB15
PF14
PB14
PF13
PB13
PF12
PB12
PF11
PB11
PF10
PB10
PF9
PB9
PF8
PF7
PF6
PB6
PF5
PB5
PF4
PB4
PF3
PB3
PF2
PB2
PF1
PB1
PF0
PB0
PE15
PA15
PE14
PA14
PE13
PA13
PE12
PA12
PE11
PA11
PE10
PA10
PE9
PA9
PE8
PA8
PE7
PA7
PE6
PA6
PE5
PA5
PE4
PA4
PA3
PA2
PE1
PA1
PE0
PA0
CEXT
Port Bus CH31 CH30 CH29 CH28 CH27 CH26 CH25 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
Table 5.29. CSEN Bus and Pin Mapping
EFM32GG11 Family Data Sheet
Pin Definitions
Rev. 1.0 | 225
silabs.com | Building a more connected world.
APORT4X APORT3X APORT2X APORT1X
BUSDX BUSCX BUSBX BUSAX
PF15
PB15
PF14
PB14
PF13
PB13
PF12
PB12
PF11
PB11
PF10
PB10
PF9
PB9
PF8
PF7
PF6
PB6
PF5
PB5
PF4
PB4
PF3
PB3
PF2
PB2
PF1
PB1
PF0
PB0
PE15
PA15
PE14
PA14
PE13
PA13
PE12
PA12
PE11
PA11
PE10
PA10
PE9
PA9
PE8
PA8
PE7
PA7
PE6
PA6
PE5
PA5
PE4
PA4
PA3
PA2
PE1
PA1
PE0
PA0
OPA0_P
APORT4Y APORT3Y APORT2Y APORT1Y
BUSDY BUSCY BUSBY BUSAY
PF15
PB15
PF14
PB14
PF13
PB13
PF12
PB12
PF11
PB11
PF10
PB10
PF9
PB9
PF8
PF7
PF6
PB6
PF5
PB5
PF4
PB4
PF3
PB3
PF2
PB2
PF1
PB1
PF0
PB0
PE15
PA15
PE14
PA14
PE13
PA13
PE12
PA12
PE11
PA11
PE10
PA10
PE9
PA9
PE8
PA8
PE7
PA7
PE6
PA6
PE5
PA5
PE4
PA4
PA3
PA2
PE1
PA1
PE0
PA0
OPA0_N
Port Bus CH31 CH30 CH29 CH28 CH27 CH26 CH25 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
Table 5.31. VDAC0 / OPA Bus and Pin Mapping
EFM32GG11 Family Data Sheet
Pin Definitions
EFM32GG11 Family Data Sheet
Pin Definitions
Rev. 1.0 | 226
OPA1_N OPA1_P OPA2_N silabs.com | Building a more connected world.
APORT4Y APORT3Y APORT2Y APORT1Y
BUSDY BUSCY BUSBY BUSAY
PF15
PB15
PF14
PB14
PF13
PB13
PF12
PB12
PF11
PB11
PF10
PB10
PF9
PB9
PF8
PF7
PF6
PB6
PF5
PB5
PF4
PB4
PF3
PB3
PF2
PB2
PF1
PB1
PF0
PB0
PE15
PA15
PE14
PA14
PE13
PA13
PE12
PA12
PE11
PA11
PE10
PA10
PE9
PA9
PE8
PA8
PE7
PA7
PE6
PA6
PE5
PA5
PE4
PA4
PA3
PA2
PE1
PA1
PE0
PA0
APORT4X APORT3X APORT2X APORT1X
BUSDX BUSCX BUSBX BUSAX
PF15
PB15
PF14
PB14
PF13
PB13
PF12
PB12
PF11
PB11
PF10
PB10
PF9
PB9
PF8
PF7
PF6
PB6
PF5
PB5
PF4
PB4
PF3
PB3
PF2
PB2
PF1
PB1
PF0
PB0
PE15
PA15
PE14
PA14
PE13
PA13
PE12
PA12
PE11
PA11
PE10
PA10
PE9
PA9
PE8
PA8
PE7
PA7
PE6
PA6
PE5
PA5
PE4
PA4
PA3
PA2
PE1
PA1
PE0
PA0
APORT4Y APORT3Y APORT2Y APORT1Y
BUSDY BUSCY BUSBY BUSAY
PF15
PB15
PF14
PB14
PF13
PB13
PF12
PB12
PF11
PB11
PF10
PB10
PF9
PB9
PF8
PF7
PF6
PB6
PF5
PB5
PF4
PB4
PF3
PB3
PF2
PB2
PF1
PB1
PF0
PB0
PE15
PA15
PE14
PA14
PE13
PA13
PE12
PA12
PE11
PA11
PE10
PA10
PE9
PA9
PE8
PA8
PE7
PA7
PE6
PA6
PE5
PA5
PE4
PA4
PA3
PA2
PE1
PA1
PE0
PA0
Port Bus CH31 CH30 CH29 CH28 CH27 CH26 CH25 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
EFM32GG11 Family Data Sheet
Pin Definitions
Rev. 1.0 | 227
OPA2_OUT OPA2_P OPA3_N silabs.com | Building a more connected world.
APORT4Y APORT3Y APORT2Y APORT1Y
BUSDY BUSCY BUSBY BUSAY
PF15
PB15
PF14
PB14
PF13
PB13
PF12
PB12
PF11
PB11
PF10
PB10
PF9
PB9
PF8
PF7
PF6
PB6
PF5
PB5
PF4
PB4
PF3
PB3
PF2
PB2
PF1
PB1
PF0
PB0
PE15
PA15
PE14
PA14
PE13
PA13
PE12
PA12
PE11
PA11
PE10
PA10
PE9
PA9
PE8
PA8
PE7
PA7
PE6
PA6
PE5
PA5
PE4
PA4
PA3
PA2
PE1
PA1
PE0
PA0
APORT4X APORT3X APORT2X APORT1X
BUSDX BUSCX BUSBX BUSAX
PF15
PB15
PF14
PB14
PF13
PB13
PF12
PB12
PF11
PB11
PF10
PB10
PF9
PB9
PF8
PF7
PF6
PB6
PF5
PB5
PF4
PB4
PF3
PB3
PF2
PB2
PF1
PB1
PF0
PB0
PE15
PA15
PE14
PA14
PE13
PA13
PE12
PA12
PE11
PA11
PE10
PA10
PE9
PA9
PE8
PA8
PE7
PA7
PE6
PA6
PE5
PA5
PE4
PA4
PA3
PA2
PE1
PA1
PE0
PA0
APORT4Y APORT3Y APORT2Y APORT1Y
BUSDY BUSCY BUSBY BUSAY
PF15
PB15
PF14
PB14
PF13
PB13
PF12
PB12
PF11
PB11
PF10
PB10
PF9
PB9
PF8
PF7
PF6
PB6
PF5
PB5
PF4
PB4
PF3
PB3
PF2
PB2
PF1
PB1
PF0
PB0
PE15
PA15
PE14
PA14
PE13
PA13
PE12
PA12
PE11
PA11
PE10
PA10
PE9
PA9
PE8
PA8
PE7
PA7
PE6
PA6
PE5
PA5
PE4
PA4
PA3
PA2
PE1
PA1
PE0
PA0
Port Bus CH31 CH30 CH29 CH28 CH27 CH26 CH25 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
EFM32GG11 Family Data Sheet
Pin Definitions
Rev. 1.0 | 228
OPA3_OUT OPA3_P VDAC0_OUT0 / OPA0_OUT silabs.com | Building a more connected world.
APORT4Y APORT3Y APORT2Y APORT1Y
BUSDY BUSCY BUSBY BUSAY
PF15
PB15
PF14
PB14
PF13
PB13
PF12
PB12
PF11
PB11
PF10
PB10
PF9
PB9
PF8
PF7
PF6
PB6
PF5
PB5
PF4
PB4
PF3
PB3
PF2
PB2
PF1
PB1
PF0
PB0
PE15
PA15
PE14
PA14
PE13
PA13
PE12
PA12
PE11
PA11
PE10
PA10
PE9
PA9
PE8
PA8
PE7
PA7
PE6
PA6
PE5
PA5
PE4
PA4
PA3
PA2
PE1
PA1
PE0
PA0
APORT4X APORT3X APORT2X APORT1X
BUSDX BUSCX BUSBX BUSAX
PF15
PB15
PF14
PB14
PF13
PB13
PF12
PB12
PF11
PB11
PF10
PB10
PF9
PB9
PF8
PF7
PF6
PB6
PF5
PB5
PF4
PB4
PF3
PB3
PF2
PB2
PF1
PB1
PF0
PB0
PE15
PA15
PE14
PA14
PE13
PA13
PE12
PA12
PE11
PA11
PE10
PA10
PE9
PA9
PE8
PA8
PE7
PA7
PE6
PA6
PE5
PA5
PE4
PA4
PA3
PA2
PE1
PA1
PE0
PA0
APORT4Y APORT3Y APORT2Y APORT1Y
BUSDY BUSCY BUSBY BUSAY
PF15
PB15
PF14
PB14
PF13
PB13
PF12
PB12
PF11
PB11
PF10
PB10
PF9
PB9
PF8
PF7
PF6
PB6
PF5
PB5
PF4
PB4
PF3
PB3
PF2
PB2
PF1
PB1
PF0
PB0
PE15
PA15
PE14
PA14
PE13
PA13
PE12
PA12
PE11
PA11
PE10
PA10
PE9
PA9
PE8
PA8
PE7
PA7
PE6
PA6
PE5
PA5
PE4
PA4
PA3
PA2
PE1
PA1
PE0
PA0
Port Bus CH31 CH30 CH29 CH28 CH27 CH26 CH25 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
Rev. 1.0 | 229
silabs.com | Building a more connected world.
APORT4Y APORT3Y APORT2Y APORT1Y
BUSDY BUSCY BUSBY BUSAY
PF15
PB15
PF14
PB14
PF13
PB13
PF12
PB12
PF11
PB11
PF10
PB10
PF9
PB9
PF8
PF7
PF6
PB6
PF5
PB5
PF4
PB4
PF3
PB3
PF2
PB2
PF1
PB1
PF0
PB0
PE15
PA15
PE14
PA14
PE13
PA13
PE12
PA12
PE11
PA11
PE10
PA10
PE9
PA9
PE8
PA8
PE7
PA7
PE6
PA6
PE5
PA5
PE4
PA4
PA3
PA2
PE1
PA1
PE0
PA0
VDAC0_OUT1 / OPA1_OUT
Port Bus CH31 CH30 CH29 CH28 CH27 CH26 CH25 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
EFM32GG11 Family Data Sheet
Pin Definitions
6. BGA192 Package Specifications
6.1 BGA192 Package Dimensions
EFM32GG11 Family Data Sheet
BGA192 Package Specifications
Figure 6.1. BGA192 Package Drawing silabs.com | Building a more connected world.
Rev. 1.0 | 230
EFM32GG11 Family Data Sheet
BGA192 Package Specifications
Table 6.1. BGA192 Package Dimensions
Dimension
Min
Typ
Max
A
0.77
0.83
0.89
A1
0.13
0.18
0.23
A3
0.16
0.20
0.24
A2
0.45 REF
D
7.00 BSC
e
0.40 BSC
E
7.00 BSC
D1
6.00 BSC
E1
6.00 BSC
b
0.20
0.25
0.30
aaa
0.10
bbb
0.10
ddd
0.08
eee
0.15
fff
0.05
Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Rev. 1.0 | 231
6.2 BGA192 PCB Land Pattern
EFM32GG11 Family Data Sheet
BGA192 Package Specifications
Figure 6.2. BGA192 PCB Land Pattern Drawing
silabs.com | Building a more connected world.
Rev. 1.0 | 232
EFM32GG11 Family Data Sheet
BGA192 Package Specifications
Table 6.2. BGA192 PCB Land Pattern Dimensions
Dimension
Min
Nom
Max
X
0.20
C1
6.00
C2
6.00
E1
0.4
E2
0.4
Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on the IPC-7351 guidelines. 4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 �m minimum, all the way around the pad. 5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 6. The stencil thickness should be 0.125 mm (5 mils). 7. The ratio of stencil aperture to land pad size should be 1:1. 8. A No-Clean, Type-3 solder paste is recommended. 9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
silabs.com | Building a more connected world.
Rev. 1.0 | 233
6.3 BGA192 Package Marking
EFM32GG11 Family Data Sheet
BGA192 Package Specifications
EFM32
PPPPPPPPPP TTTTTT YYWW
Figure 6.3. BGA192 Package Marking
The package marking consists of: � PPPPPPPPPP � The part number designation. � TTTTTT � A trace or manufacturing code. The first letter is the device revision. � YY � The last 2 digits of the assembly year. � WW � The 2-digit workweek when the device was assembled.
silabs.com | Building a more connected world.
Rev. 1.0 | 234
7. BGA152 Package Specifications
7.1 BGA152 Package Dimensions A1 BALL CORNER
E
EFM32GG11 Family Data Sheet
BGA152 Package Specifications
aaa C B (2X) A
A A3
(0.75) aaa C A (2X)
D DETAIL K
TOP VIEW
B
SIDE VIEW
14 13 12 11 10 9 8 7 6 5 4 3 2 1
A1 BALL CORNER
A B
152X b 2
C
eee C A B
D
fff C
E
F
e/2
D1
G H
J
K
L
M
e
N
P
(0.75)
e/2
e
E1
BOTTOM VIEW
4
bbb C
A1
ddd C?
C SEATING PLANE 3
DETAIL K
ROTATED 90�� CW
Figure 7.1. BGA152 Package Drawing
silabs.com | Building a more connected world.
Rev. 1.0 | 235
EFM32GG11 Family Data Sheet
BGA152 Package Specifications
Table 7.1. BGA152 Package Dimensions
Dimension
Min
Typ
Max
A
0.78
0.84
0.90
A1
0.13
0.18
0.23
A3
0.16
0.20
0.24
A2
0.45 REF
D
8.00 BSC
e
0.50 BSC
E
8.00 BSC
D1
6.50 BSC
E1
6.50 BSC
b
0.20
0.25
0.30
aaa
0.10
bbb
0.10
ddd
0.08
eee
0.15
fff
0.05
Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
silabs.com | Building a more connected world.
Rev. 1.0 | 236
7.2 BGA152 PCB Land Pattern
EFM32GG11 Family Data Sheet
BGA152 Package Specifications
Figure 7.2. BGA152 PCB Land Pattern Drawing
silabs.com | Building a more connected world.
Rev. 1.0 | 237
EFM32GG11 Family Data Sheet
BGA152 Package Specifications
Table 7.2. BGA152 PCB Land Pattern Dimensions
Dimension
Min
Nom
Max
X
0.20
C1
6.50
C2
6.50
E1
0.5
E2
0.5
Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on the IPC-7351 guidelines. 4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 �m minimum, all the way around the pad. 5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 6. The stencil thickness should be 0.125 mm (5 mils). 7. The ratio of stencil aperture to land pad size should be 1:1. 8. A No-Clean, Type-3 solder paste is recommended. 9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
silabs.com | Building a more connected world.
Rev. 1.0 | 238
7.3 BGA152 Package Marking
EFM32GG11 Family Data Sheet
BGA152 Package Specifications
EFM32
PPPPPPPPPP TTTTTT YYWW
Figure 7.3. BGA152 Package Marking
The package marking consists of: � PPPPPPPPPP � The part number designation. � TTTTTT � A trace or manufacturing code. The first letter is the device revision. � YY � The last 2 digits of the assembly year. � WW � The 2-digit workweek when the device was assembled.
silabs.com | Building a more connected world.
Rev. 1.0 | 239
8. BGA120 Package Specifications
8.1 BGA120 Package Dimensions
EFM32GG11 Family Data Sheet
BGA120 Package Specifications
Figure 8.1. BGA120 Package Drawing silabs.com | Building a more connected world.
Rev. 1.0 | 240
EFM32GG11 Family Data Sheet
BGA120 Package Specifications
Table 8.1. BGA120 Package Dimensions
Dimension
Min
Typ
Max
A
0.78
0.84
0.90
A1
0.13
0.18
0.23
A3
0.17
0.21
0.25
A2
0.45 REF
D
7.00 BSC
e
0.50 BSC
E
7.00 BSC
D1
6.00 BSC
E1
6.00 BSC
b
0.20
0.25
0.30
aaa
0.10
bbb
0.10
ddd
0.08
eee
0.15
fff
0.05
Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
silabs.com | Building a more connected world.
Rev. 1.0 | 241
8.2 BGA120 PCB Land Pattern
EFM32GG11 Family Data Sheet
BGA120 Package Specifications
Figure 8.2. BGA120 PCB Land Pattern Drawing
silabs.com | Building a more connected world.
Rev. 1.0 | 242
EFM32GG11 Family Data Sheet
BGA120 Package Specifications
Table 8.2. BGA120 PCB Land Pattern Dimensions
Dimension
Min
Nom
Max
X
0.20
C1
6.00
C2
6.00
E1
0.5
E2
0.5
Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on the IPC-7351 guidelines. 4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 �m minimum, all the way around the pad. 5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 6. The stencil thickness should be 0.125 mm (5 mils). 7. The ratio of stencil aperture to land pad size should be 1:1. 8. A No-Clean, Type-3 solder paste is recommended. 9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
silabs.com | Building a more connected world.
Rev. 1.0 | 243
8.3 BGA120 Package Marking
EFM32GG11 Family Data Sheet
BGA120 Package Specifications
EFM32
PPPPPPPPPP TTTTTT YYWW
Figure 8.3. BGA120 Package Marking
The package marking consists of: � PPPPPPPPPP � The part number designation. � TTTTTT � A trace or manufacturing code. The first letter is the device revision. � YY � The last 2 digits of the assembly year. � WW � The 2-digit workweek when the device was assembled.
silabs.com | Building a more connected world.
Rev. 1.0 | 244
9. BGA112 Package Specifications
9.1 BGA112 Package Dimensions
EFM32GG11 Family Data Sheet
BGA112 Package Specifications
Figure 9.1. BGA112 Package Drawing
silabs.com | Building a more connected world.
Rev. 1.0 | 245
EFM32GG11 Family Data Sheet
BGA112 Package Specifications
Table 9.1. BGA112 Package Dimensions
Dimension
Min
Typ
Max
A
-
-
1.30
A1
0.55
0.60
0.65
A2
0.21 BSC
A3
0.30
0.35
0.40
d
0.43
0.48
0.53
D
10.00 BSC
D1
8.00 BSC
E
10.00 BSC
E1
8.00 BSC
e1
0.80 BSC
e2
0.80 BSC
L1
1.00 REF
L2
1.00 REF
Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
silabs.com | Building a more connected world.
Rev. 1.0 | 246
9.2 BGA112 PCB Land Pattern
EFM32GG11 Family Data Sheet
BGA112 Package Specifications
Figure 9.2. BGA112 PCB Land Pattern Drawing
silabs.com | Building a more connected world.
Rev. 1.0 | 247
EFM32GG11 Family Data Sheet
BGA112 Package Specifications
Table 9.2. BGA112 PCB Land Pattern Dimensions
Dimension
Min
Nom
Max
X
0.45
C1
8.00
C2
8.00
E1
0.8
E2
0.8
Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on the IPC-7351 guidelines. 4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 �m minimum, all the way around the pad. 5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 6. The stencil thickness should be 0.125 mm (5 mils). 7. The ratio of stencil aperture to land pad size should be 1:1. 8. A No-Clean, Type-3 solder paste is recommended. 9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
silabs.com | Building a more connected world.
Rev. 1.0 | 248
9.3 BGA112 Package Marking
EFM32GG11 Family Data Sheet
BGA112 Package Specifications
EFM32
PPPPPPPPPP TTTTTT YYWW
Figure 9.3. BGA112 Package Marking
The package marking consists of: � PPPPPPPPPP � The part number designation. � TTTTTT � A trace or manufacturing code. The first letter is the device revision. � YY � The last 2 digits of the assembly year. � WW � The 2-digit workweek when the device was assembled.
silabs.com | Building a more connected world.
Rev. 1.0 | 249
10. TQFP100 Package Specifications
10.1 TQFP100 Package Dimensions
EFM32GG11 Family Data Sheet
TQFP100 Package Specifications
Figure 10.1. TQFP100 Package Drawing
silabs.com | Building a more connected world.
Rev. 1.0 | 250
EFM32GG11 Family Data Sheet
TQFP100 Package Specifications
Table 10.1. TQFP100 Package Dimensions
Dimension
Min
Typ
Max
A
-
-
1.20
A1
0.05
-
0.15
A2
0.95
1.00
1.05
b
0.17
0.22
0.27
b1
0.17
0.20
0.23
c
0.09
-
0.20
c1
0.09
-
0.16
D
16.0 BSC
E
16.0 BSC
D1
14.0 BSC
E1
14.0 BSC
e
0.50 BSC
L1
1 REF
L
0.45
0.60
0.75
0
3.5
7
1
0
-
-
2
11
12
13
3
11
12
13
R1
0.08
-
-
R2
0.08
-
0.2
S
0.2
-
-
aaa
0.2
bbb
0.2
ccc
0.08
ddd
0.08
eee
0.05
Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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10.2 TQFP100 PCB Land Pattern
EFM32GG11 Family Data Sheet
TQFP100 Package Specifications
Figure 10.2. TQFP100 PCB Land Pattern Drawing
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EFM32GG11 Family Data Sheet
TQFP100 Package Specifications
Table 10.2. TQFP100 PCB Land Pattern Dimensions
Dimension
Min
Nom
Max
C1
15.4
C2
15.4
E
0.50 BSC
X
0.30
Y
1.50
Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. 3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 �m minimum, all the way around the pad. 4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. The stencil thickness should be 0.125 mm (5 mils). 6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 7. A No-Clean, Type-3 solder paste is recommended. 8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
10.3 TQFP100 Package Marking
EFM32
PPPPPPPPPP TTTTTT YYWW
Figure 10.3. TQFP100 Package Marking
The package marking consists of: � PPPPPPPPPP � The part number designation. � TTTTTT � A trace or manufacturing code. The first letter is the device revision. � YY � The last 2 digits of the assembly year. � WW � The 2-digit workweek when the device was assembled.
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11. TQFP64 Package Specifications
11.1 TQFP64 Package Dimensions
EFM32GG11 Family Data Sheet
TQFP64 Package Specifications
Figure 11.1. TQFP64 Package Drawing silabs.com | Building a more connected world.
Rev. 1.0 | 254
EFM32GG11 Family Data Sheet
TQFP64 Package Specifications
Table 11.1. TQFP64 Package Dimensions
Dimension
Min
Typ
Max
A
--
1.15
1.20
A1
0.05
--
0.15
A2
0.95
1.00
1.05
b
0.17
0.22
0.27
b1
0.17
0.20
0.23
c
0.09
--
0.20
c1
0.09
--
0.16
D
12.00 BSC
D1
10.00 BSC
e
0.50 BSC
E
12.00 BSC
E1
10.00 BSC
L
0.45
0.60
0.75
L1
1.00 REF
R1
0.08
--
--
R2
0.08
--
0.20
S
0.20
--
--
0
3.5
7
1
0
--
0.10
2
11
12
13
3
11
12
13
Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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11.2 TQFP64 PCB Land Pattern
EFM32GG11 Family Data Sheet
TQFP64 Package Specifications
Figure 11.2. TQFP64 PCB Land Pattern Drawing
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EFM32GG11 Family Data Sheet
TQFP64 Package Specifications
Table 11.2. TQFP64 PCB Land Pattern Dimensions
Dimension
Min
Max
C1
11.30
11.40
C2
11.30
11.40
E
0.50 BSC
X
0.20
0.30
Y
1.40
1.50
Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. 3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 �m minimum, all the way around the pad. 4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. The stencil thickness should be 0.125 mm (5 mils). 6. The ratio of stencil aperture to land pad size can be 1:1 for all pads. 7. A No-Clean, Type-3 solder paste is recommended. 8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
11.3 TQFP64 Package Marking
EFM32
PPPPPPPPPP TTTTTT YYWW
Figure 11.3. TQFP64 Package Marking
The package marking consists of: � PPPPPPPPPP � The part number designation. � TTTTTT � A trace or manufacturing code. The first letter is the device revision. � YY � The last 2 digits of the assembly year. � WW � The 2-digit workweek when the device was assembled.
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12. QFN64 Package Specifications
12.1 QFN64 Package Dimensions
EFM32GG11 Family Data Sheet
QFN64 Package Specifications
Figure 12.1. QFN64 Package Drawing silabs.com | Building a more connected world.
Rev. 1.0 | 258
EFM32GG11 Family Data Sheet
QFN64 Package Specifications
Table 12.1. QFN64 Package Dimensions
Dimension
Min
Typ
Max
A
0.70
0.75
0.80
A1
0.00
--
0.05
b
0.20
0.25
0.30
A3
0.203 REF
D
9.00 BSC
e
0.50 BSC
E
9.00 BSC
D2
7.10
7.20
7.30
E2
7.10
7.20
7.30
L
0.40
0.45
0.50
L1
0.00
--
0.10
aaa
0.10
bbb
0.10
ccc
0.10
ddd
0.05
eee
0.08
Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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12.2 QFN64 PCB Land Pattern
EFM32GG11 Family Data Sheet
QFN64 Package Specifications
Figure 12.2. QFN64 PCB Land Pattern Drawing
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EFM32GG11 Family Data Sheet
QFN64 Package Specifications
Table 12.2. QFN64 PCB Land Pattern Dimensions
Dimension
Typ
C1
8.90
C2
8.90
E
0.50
X1
0.30
Y1
0.85
X2
7.30
Y2
7.30
Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. 3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05mm. 4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 �m minimum, all the way around the pad. 5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 6. The stencil thickness should be 0.125 mm (5 mils). 7. The ratio of stencil aperture to land pad size can be 1:1 for all pads. 8. A 3x3 array of 1.45 mm square openings on a 2.00 mm pitch can be used for the center ground pad. 9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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12.3 QFN64 Package Marking
EFM32GG11 Family Data Sheet
QFN64 Package Specifications
EFM32
PPPPPPPPPP TTTTTT YYWW
Figure 12.3. QFN64 Package Marking
The package marking consists of: � PPPPPPPPPP � The part number designation. � TTTTTT � A trace or manufacturing code. The first letter is the device revision. � YY � The last 2 digits of the assembly year. � WW � The 2-digit workweek when the device was assembled.
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13. Revision History
EFM32GG11 Family Data Sheet
Revision History
Revision 1.0
August, 2018
� Updated Table 2.1 Ordering Information on page 4 with revision B part numbers. � Updated 4.1 Electrical Characteristics with latest characterization data and production test limits. � Added RUSB specification to Table 4.20 General-Purpose I/O (GPIO) on page 52. � Updated 4.1.28 Quad SPI (QSPI) with final TXDLL, RXDLL and timing conditions for revision B, and added optimal timing tables. � Updated 4.1.27 Serial Data I/O Host Controller (SDIO) with final timing for revision B, added timing tables for location 1 and MMC
legacy mode, and removed tF specification from non-DDR mode tables. � Corrected ball numbering for row L in BGA120 pinout tables: Table 5.3 EFM32GG11B8xx in BGA120 Device Pinout on page 129,
Table 5.4 EFM32GG11B5xx in BGA120 Device Pinout on page 132, and Table 5.5 EFM32GG11B4xx in BGA120 Device Pinout on page 135. � Table 5.20 GPIO Functionality Table on page 172: re-ordered to show pins in alphabetical order by GPIO name. � 7.2 BGA152 PCB Land Pattern: corrected dimension "X" in figure.
Revision 0.6
March, 2018
� Removed "Confidential" watermark. � Updated 4.1 Electrical Characteristics and 4.2 Typical Performance Curves with latest characterization data.
Revision 0.2
October, 2017
� Updated memory maps to latest formatting and to include all peripherals. � Updated all electrical specifications tables with latest characterization results. � Absolute Maximum Ratings Table:
� Removed redundant IVSSMAX line. � Added footnote to clarify VDIGPIN specification for 5V tolerant GPIO. � General Operating Conditions Table: � Removed dVDD specification and redundant footnote about shorting VREGVDD and AVDD together. � Added footnote about IOVDD voltage restriction when CSEN peripheral is used with chopping enabled. � Flash Memory Characteristics Table: Added timing measurement clarification for Device Erase and Mass Erase. � Analog to Digital Converter (ADC) Table: � Added header text for general specification conditions. � Added footnote for clarification of input voltage limits. � Minor typographical corrections, including capitalization, mis-spellings and punctuation marks, throughout document. � Minor formatting and styling updates, including table formats, TOC location, and boilerplate information throughout document.
Revision 0.1 April 27th, 2017 Initial release.
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Rev. 1.0 | 263
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