PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers. Technical Reference Manual ( TRM). PSoC 62 MCU. Number: 002-20777 Rev. *F.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers. Technical Reference Manual (TRM). PSoC 62 MCU. Number: 002-20777 Rev. *F.
2 янв. 2022 г. — Copyrights. © Cypress Semiconductor Corporation - An Infineon Technologies Company, 2017-2020. This document is the property of.
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P 6 TRM
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers Technical Reference Manual (TRM)
PSoC 62 MCU
Document Number: 002-20777 Rev. *F July 24, 2020
Cypress Semiconductor An Infineon Technologies Company
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Copyrights
© Cypress Semiconductor Corporation - An Infineon Technologies Company, 2017-2020. This document is the property of Cypress Semiconductor Corporation and its subsidiaries ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, nonexclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited.
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, FRAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
2
Contents
Register Mapping
5
Section A: Supervisory Flash Registers
9
1.
Supervisory Flash Registers .......................................................................................... 10
Section B: Peripheral Group 0
16
2.
Peripheral Registers ...................................................................................................... 17
Section C: Peripheral Group 1
265
3.
Cryptography Registers ............................................................................................... 266
Section D: Peripheral Group 2
318
4.
CPU Sub System (CPUSS) Registers .......................................................................... 319
5.
Fault Registers ............................................................................................................ 358
6.
Inter-Processor Communication Registers ................................................................... 377
7.
Protection Unit Registers ............................................................................................. 391
8.
Flash Controller Registers ........................................................................................... 432
9.
System Resources Subsystem Registers ..................................................................... 519
10.
Multi-Counter WDT (MCWDT) Registers ...................................................................... 599
11.
Backup System Registers ............................................................................................ 614
12.
Direct Memory Access (DMA) Registers ....................................................................... 640
13.
eFuse Registers .......................................................................................................... 673
14.
Profiler Registers ........................................................................................................ 681
Section E: Peripheral Group 3
692
15.
High Speed IO Matrix (HSIOM) Registers .................................................................... 693
16.
General Purpose I/O (GPIO) Registers ........................................................................ 705
17.
Smart I/O Registers ..................................................................................................... 793
18.
Universal Digital Block (UDB) Registers ....................................................................... 806
19.
Low-Power Comparator Registers .............................................................................. 1047
20.
Timer, Counter, PWM (TCPWM) Registers ................................................................. 1062
21.
Segment LCD Drive Registers ................................................................................... 1121
22.
USB Registers ........................................................................................................... 1129
Section F: Peripheral Group 4
1279
23.
Serial Memory Interface (SMIF) Registers .................................................................. 1280
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Contents
Section G: Peripheral Group 6
1337
24.
Serial Communication Block (SCB) Registers ............................................................ 1338
Section H: Peripheral Group 9
1445
25.
Analog Reference Block (AREF) Registers................................................................. 1446
26.
Continuous-Time Block Mini Registers ....................................................................... 1450
27.
Continuous-Time DAC Registers ................................................................................ 1481
28.
SAR ADC Registers ................................................................................................... 1492
Section I:
29. 30.
Peripheral Group 10
1549
Pulse Density Modulation (PDM) Registers ................................................................ 1550
Inter IC Sound (I2S) Registers ................................................................................... 1569
Section J: System Registers
1599
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
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Register Mapping
The Register Mapping section discusses the registers and lists all the registers in mapping tables, in address order for PSoC® 6 MCUs. For Architecture details, see the PSoC 6 MCU: CY8C62x6, CY8C62x7 Architecture Technical Reference Manual (TRM).
Note that memory mapped I/O (MMIO) registers support only 32-bit access, unless otherwise specified in the register description.
Register General Conventions
The register conventions specific to this section and the Register Reference chapter are listed in this table.
RW R W RW1C
RW0C
RW1S
Convention
A
None / Reserved `x' in a register /bit field name
Description Read/Write Read only Write only Read/Write `1' to clear
Read/Write `0' to clear
Read/Write `1' to set
Alias
Reserved bits Multiple instances
Explanation
These bits can be both read and written.
These bits can only be read. Writing has no effect on the bit value.
These bits can only be written. Reading the bit returns the reset value.
These bits can be read as well as cleared by writing `1'. Writing `0' has no effect on the bit value.
These bits can be read as well as cleared by writing `0'. Writing `1' has no effect on the bit value.
These bits can be read as well as set by writing `1'. Writing `0' has no effect on the bit value.
This register is an additional alias for another register. This convention is used when a physical register is mapped to multiple addresses, typically for firmware debug purposes. See the corresponding register descriptions for more details.
Keep these bits at the default value
Multiple instances/address ranges of the same register/bit field
Acronyms This table lists the acronyms used in this document
Table 3-1. Acronyms
ABUS AC ADC AHB API APOR BC BOM BR BRA BRQ
Symbol
Unit of Measure analog output bus alternating current analog-to-digital converter AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus application programming interface analog power-on reset broadcast clock bill of materials bit rate bus request acknowledge bus request
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
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Table 3-1. Acronyms
CAN CI CMP CO CPU CRC
Symbol
CSD
CT CTBm DAC DC DI DMA DNL DO DSI DSM ECO EEPROM EMIF FB FIFO FSR GPIO HCI HFCLK I2C IDE ILO IMO INL I/O IOR IOW IRES IRA IRQ ISR IVR L2CAP LPCOMP LRb LRB LSb
Unit of Measure controller area network carry in compare carry out central processing unit cyclic redundancy check CapSense® sigma delta continuous time continuous time block-mini digital-to-analog converter direct current digital or data input direct memory access differential nonlinearity digital or data output digital signal interface deep-sleep mode external crystal oscillator electrically erasable programmable read only memory external memory interface feedback first in first out full scale range general purpose I/O host-controller interface high-frequency clock inter-integrated circuit integrated development environment internal low-speed oscillator internal main oscillator integral nonlinearity input/output I/O read I/O write initial power on reset interrupt request acknowledge interrupt request interrupt service routine interrupt vector read logical link control and adaptation protocol low-power comparator last received bit last received byte least significant bit
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
Register Mapping 6
Table 3-1. Acronyms
LSB LUT MISO MMIO MOSI MSb MSB PC PCH PCL PD PGA PM PMA POR PPOR PRS
Symbol
PSoC PSRR PSSDC PWM RAM RETI RF ROM RW SAR SC SCB SIE SIO SE0 SNR SOF SOI SP SPD SPI SPIM SPIS SRAM SRSS SROM SSADC
least significant byte lookup table master-in-slave-out memory mapped input/output master-out-slave-in most significant bit most significant byte program counter program counter high program counter low power down programmable gain amplifier power management PSoC memory arbiter power-on reset precision power-on reset pseudo random sequence Programmable System-on-Chip power supply rejection ratio power system sleep duty cycle pulse width modulator random-access memory return from interrupt radio frequency read only memory read/write successive approximation register switched capacitor serial communication block serial interface engine special I/O single-ended zero signal-to-noise ratio start of frame start of instruction stack pointer sequential phase detector serial peripheral interconnect serial peripheral interconnect master serial peripheral interconnect slave static random-access memory system resources sub-system supervisory read only memory single slope ADC
Unit of Measure
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
Register Mapping 7
Table 3-1. Acronyms
Symbol SSC SYSCLK SWD TC TD UART UDB USB USBIO WCO WDT WDR XRES XRES_N
supervisory system call system clock single wire debug terminal count transaction descriptors universal asynchronous receiver/transmitter universal digital block universal serial bus USB I/O watch crystal oscillator watchdog timer watchdog reset external reset external reset, active low
Unit of Measure
Register Mapping
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
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Section A: Supervisory Flash Registers
This section encompasses the following chapter: Supervisory Flash Registers chapter on page 10
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
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1 Supervisory Flash Registers
This section discusses the Supervisory Flash registers. It lists all the registers in mapping tables, in address order.
1.1 Register Details
Register SFLASH_SI_REVISION_ID SFLASH_SILICON_ID SFLASH_FAMILY_ID SFLASH_SAR_TEMP_MULTIPLIER SFLASH_SAR_TEMP_OFFSET
Address 0x16000001 0x16000002 0x1600000C 0x16000648 0x1600064A
Description Indicates Silicon Revision ID of the device Indicates Silicon ID of the device Indicates Family ID of the device SAR Temperature Sensor Multiplication Factor SAR Temperature Sensor Offset
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
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SFLASH_SI_REVISION_ID
1.1.1 SFLASH_SI_REVISION_ID
Address = 0x16000001 Indicates Silicon Revision ID of the device Address: 0x16000001 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
Name
SI_REVISION_ID [7:0]
Bits 7 : 0
Name SI_REVISION_ID
Description
Silicon Revision ID Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
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SFLASH_SILICON_ID
1.1.2 SFLASH_SILICON_ID
Address = 0x16000002 Indicates Silicon ID of the device Address: 0x16000002 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
Name
ID [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
Name
ID [15:8]
Bits 15 : 0
Name ID
Description
Silicon ID Default Value: X
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SFLASH_FAMILY_ID
1.1.3 SFLASH_FAMILY_ID
Address = 0x1600000C Indicates Family ID of the device Address: 0x1600000C Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
Name
FAMILY_ID [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
Name
FAMILY_ID [15:8]
Bits 15 : 0
Name FAMILY_ID
Description
Family ID Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
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SFLASH_SAR_TEMP_MULTIPLIER
1.1.4 SFLASH_SAR_TEMP_MULTIPLIER
Address = 0x16000648 SAR Temperature Sensor Multiplication Factor Address: 0x16000648 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
Name
TEMP_MULTIPLIER [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
Name
TEMP_MULTIPLIER [15:8]
Bits 15 : 0
Name TEMP_MULTIPLIER
Description
Multiplier value for SAR temperature sensor Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
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SFLASH_SAR_TEMP_OFFSET
1.1.5 SFLASH_SAR_TEMP_OFFSET
Address = 0x1600064A SAR Temperature Sensor Offset Address: 0x1600064A Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
Name
TEMP_OFFSET [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
Name
TEMP_OFFSET [15:8]
Bits 15 : 0
Name TEMP_OFFSET
Description
Offset value for SAR temperature sensor Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
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Section B: Peripheral Group 0
This section encompasses the following chapters: Peripheral Registers chapter on page 17
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
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2 Peripheral Registers
This section discusses the Peripheral registers. It lists all the registers in mapping tables, in address order.
2.1 Register Details
Register PERI_GR0_SL_CTL PERI_GR1_SL_CTL PERI_GR1_TIMEOUT_CTL PERI_GR2_SL_CTL PERI_GR2_TIMEOUT_CTL PERI_GR3_CLOCK_CTL PERI_GR3_SL_CTL PERI_GR3_TIMEOUT_CTL PERI_GR4_CLOCK_CTL PERI_GR4_SL_CTL PERI_GR4_TIMEOUT_CTL PERI_GR6_CLOCK_CTL PERI_GR6_SL_CTL PERI_GR6_TIMEOUT_CTL PERI_GR9_CLOCK_CTL PERI_GR9_SL_CTL PERI_GR9_TIMEOUT_CTL PERI_GR10_CLOCK_CTL PERI_GR10_SL_CTL PERI_GR10_TIMEOUT_CTL PERI_DIV_CMD PERI_DIV_8_CTL0
PERI_DIV_8_CTL1
PERI_DIV_8_CTL2
PERI_DIV_8_CTL3
Address 0x40010020 0x40010060 0x40010064 0x400100A0 0x400100A4 0x400100C0 0x400100E0 0x400100E4 0x40010100 0x40010120 0x40010124 0x40010180 0x400101A0 0x400101A4 0x40010240 0x40010260 0x40010264 0x40010280 0x400102A0 0x400102A4 0x40010400 0x40010800
0x40010804
0x40010808
0x4001080C
Description Slave control Slave control Timeout control Slave control Timeout control. See PERI_GR1_TIMEOUT_CTL for the details of bit fields. Clock control Slave control Timeout control. See PERI_GR1_TIMEOUT_CTL for the details of bit fields. Clock control. See PERI_GR3_CLOCK_CTL for the details of bit fields. Slave control Timeout control. See PERI_GR1_TIMEOUT_CTL for the details of bit fields. Clock control. See PERI_GR3_CLOCK_CTL for the details of bit fields. Slave control Timeout control. See PERI_GR1_TIMEOUT_CTL for the details of bit fields. Clock control. See PERI_GR3_CLOCK_CTL for the details of bit fields. Slave control. See PERI_GR1_SL_CTL for the details of bit fields. Timeout control. See PERI_GR1_TIMEOUT_CTL for the details of bit fields. Clock control. See PERI_GR3_CLOCK_CTL for the details of bit fields. Slave control Timeout control. See PERI_GR1_TIMEOUT_CTL for the details of bit fields. Divider command register Divider control register (for 8.0 divider) Divider control register (for 8.0 divider). See PERI_DIV_8_CTL0 for the details of bit fields. Divider control register (for 8.0 divider). See PERI_DIV_8_CTL0 for the details of bit fields. Divider control register (for 8.0 divider). See PERI_DIV_8_CTL0 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
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Peripheral Registers
Register PERI_DIV_8_CTL4 PERI_DIV_8_CTL5 PERI_DIV_8_CTL6 PERI_DIV_8_CTL7 PERI_DIV_16_CTL0 PERI_DIV_16_CTL1 PERI_DIV_16_CTL2 PERI_DIV_16_CTL3 PERI_DIV_16_CTL4 PERI_DIV_16_CTL5 PERI_DIV_16_CTL6 PERI_DIV_16_CTL7 PERI_DIV_16_CTL8 PERI_DIV_16_CTL9 PERI_DIV_16_CTL10 PERI_DIV_16_CTL11 PERI_DIV_16_CTL12 PERI_DIV_16_CTL13 PERI_DIV_16_CTL14 PERI_DIV_16_CTL15 PERI_DIV_16_5_CTL0 PERI_DIV_16_5_CTL1 PERI_DIV_16_5_CTL2 PERI_DIV_16_5_CTL3 PERI_DIV_24_5_CTL0 PERI_CLOCK_CTL0 PERI_CLOCK_CTL1 PERI_CLOCK_CTL2 PERI_CLOCK_CTL3 PERI_CLOCK_CTL4 PERI_CLOCK_CTL5 PERI_CLOCK_CTL6
Address 0x40010810 0x40010814 0x40010818 0x4001081C 0x40010900 0x40010904 0x40010908 0x4001090C 0x40010910 0x40010914 0x40010918 0x4001091C 0x40010920 0x40010924 0x40010928 0x4001092C 0x40010930 0x40010934 0x40010938 0x4001093C 0x40010A00 0x40010A04 0x40010A08 0x40010A0C 0x40010B00 0x40010C00 0x40010C04 0x40010C08 0x40010C0C 0x40010C10 0x40010C14 0x40010C18
Description
Divider control register (for 8.0 divider). See PERI_DIV_8_CTL0 for the details of bit fields.
Divider control register (for 8.0 divider). See PERI_DIV_8_CTL0 for the details of bit fields.
Divider control register (for 8.0 divider). See PERI_DIV_8_CTL0 for the details of bit fields.
Divider control register (for 8.0 divider). See PERI_DIV_8_CTL0 for the details of bit fields.
Divider control register (for 16.0 divider)
Divider control register (for 16.0 divider). See PERI_DIV_16_CTL0 for the details of bit fields.
Divider control register (for 16.0 divider). See PERI_DIV_16_CTL0 for the details of bit fields.
Divider control register (for 16.0 divider). See PERI_DIV_16_CTL0 for the details of bit fields.
Divider control register (for 16.0 divider). See PERI_DIV_16_CTL0 for the details of bit fields.
Divider control register (for 16.0 divider). See PERI_DIV_16_CTL0 for the details of bit fields.
Divider control register (for 16.0 divider). See PERI_DIV_16_CTL0 for the details of bit fields.
Divider control register (for 16.0 divider). See PERI_DIV_16_CTL0 for the details of bit fields.
Divider control register (for 16.0 divider). See PERI_DIV_16_CTL0 for the details of bit fields.
Divider control register (for 16.0 divider). See PERI_DIV_16_CTL0 for the details of bit fields.
Divider control register (for 16.0 divider). See PERI_DIV_16_CTL0 for the details of bit fields.
Divider control register (for 16.0 divider). See PERI_DIV_16_CTL0 for the details of bit fields.
Divider control register (for 16.0 divider). See PERI_DIV_16_CTL0 for the details of bit fields.
Divider control register (for 16.0 divider). See PERI_DIV_16_CTL0 for the details of bit fields.
Divider control register (for 16.0 divider). See PERI_DIV_16_CTL0 for the details of bit fields.
Divider control register (for 16.0 divider). See PERI_DIV_16_CTL0 for the details of bit fields.
Divider control register (for 16.5 divider)
Divider control register (for 16.5 divider). See PERI_DIV_16_5_CTL0 for the details of bit fields.
Divider control register (for 16.5 divider). See PERI_DIV_16_5_CTL0 for the details of bit fields.
Divider control register (for 16.5 divider). See PERI_DIV_16_5_CTL0 for the details of bit fields.
Divider control register (for 24.5 divider)
Clock control register
Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields.
Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields.
Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields.
Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields.
Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields.
Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
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Peripheral Registers
Register PERI_CLOCK_CTL7 PERI_CLOCK_CTL8 PERI_CLOCK_CTL9 PERI_CLOCK_CTL10 PERI_CLOCK_CTL11 PERI_CLOCK_CTL12 PERI_CLOCK_CTL13 PERI_CLOCK_CTL14 PERI_CLOCK_CTL15 PERI_CLOCK_CTL16 PERI_CLOCK_CTL17 PERI_CLOCK_CTL18 PERI_CLOCK_CTL19 PERI_CLOCK_CTL20 PERI_CLOCK_CTL21 PERI_CLOCK_CTL22 PERI_CLOCK_CTL23 PERI_CLOCK_CTL24 PERI_CLOCK_CTL25 PERI_CLOCK_CTL26 PERI_CLOCK_CTL27 PERI_CLOCK_CTL28 PERI_CLOCK_CTL29 PERI_CLOCK_CTL30 PERI_CLOCK_CTL31 PERI_CLOCK_CTL32 PERI_CLOCK_CTL33 PERI_CLOCK_CTL34 PERI_CLOCK_CTL35 PERI_CLOCK_CTL36 PERI_CLOCK_CTL37 PERI_CLOCK_CTL38 PERI_CLOCK_CTL39 PERI_CLOCK_CTL40 PERI_CLOCK_CTL41 PERI_CLOCK_CTL42 PERI_CLOCK_CTL43 PERI_CLOCK_CTL44 PERI_CLOCK_CTL45 PERI_CLOCK_CTL46 PERI_CLOCK_CTL47 PERI_CLOCK_CTL48
Address 0x40010C1C 0x40010C20 0x40010C24 0x40010C28 0x40010C2C 0x40010C30 0x40010C34 0x40010C38 0x40010C3C 0x40010C40 0x40010C44 0x40010C48 0x40010C4C 0x40010C50 0x40010C54 0x40010C58 0x40010C5C 0x40010C60 0x40010C64 0x40010C68 0x40010C6C 0x40010C70 0x40010C74 0x40010C78 0x40010C7C 0x40010C80 0x40010C84 0x40010C88 0x40010C8C 0x40010C90 0x40010C94 0x40010C98 0x40010C9C 0x40010CA0 0x40010CA4 0x40010CA8 0x40010CAC 0x40010CB0 0x40010CB4 0x40010CB8 0x40010CBC 0x40010CC0
Description Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields. Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields. Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields. Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields. Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields. Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields. Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields. Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields. Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields. Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields. Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields. Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields. Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields. Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields. Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields. Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields. Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields. Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields. Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields. Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields. Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields. Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields. Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields. Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields. Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields. Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields. Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields. Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields. Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields. Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields. Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields. Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields. Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields. Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields. Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields. Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields. Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields. Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields. Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields. Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields. Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields. Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
19
Peripheral Registers
Register PERI_CLOCK_CTL49 PERI_CLOCK_CTL50 PERI_CLOCK_CTL51 PERI_CLOCK_CTL52 PERI_CLOCK_CTL53 PERI_CLOCK_CTL54 PERI_CLOCK_CTL55 PERI_CLOCK_CTL56 PERI_CLOCK_CTL57 PERI_CLOCK_CTL58 PERI_TR_CMD PERI_TR_GR0_TR_OUT_CTL0 PERI_TR_GR0_TR_OUT_CTL1 PERI_TR_GR0_TR_OUT_CTL2 PERI_TR_GR0_TR_OUT_CTL3 PERI_TR_GR0_TR_OUT_CTL4 PERI_TR_GR0_TR_OUT_CTL5 PERI_TR_GR0_TR_OUT_CTL6 PERI_TR_GR0_TR_OUT_CTL7 PERI_TR_GR0_TR_OUT_CTL8 PERI_TR_GR0_TR_OUT_CTL9 PERI_TR_GR0_TR_OUT_CTL10 PERI_TR_GR0_TR_OUT_CTL11 PERI_TR_GR0_TR_OUT_CTL12 PERI_TR_GR0_TR_OUT_CTL13 PERI_TR_GR0_TR_OUT_CTL14 PERI_TR_GR0_TR_OUT_CTL15 PERI_TR_GR1_TR_OUT_CTL0 PERI_TR_GR1_TR_OUT_CTL1 PERI_TR_GR1_TR_OUT_CTL2 PERI_TR_GR1_TR_OUT_CTL3 PERI_TR_GR1_TR_OUT_CTL4 PERI_TR_GR1_TR_OUT_CTL5
Address 0x40010CC4 0x40010CC8 0x40010CCC 0x40010CD0 0x40010CD4 0x40010CD8 0x40010CDC 0x40010CE0 0x40010CE4 0x40010CE8 0x40011000 0x40012000 0x40012004 0x40012008 0x4001200C 0x40012010 0x40012014 0x40012018 0x4001201C 0x40012020 0x40012024 0x40012028 0x4001202C 0x40012030 0x40012034 0x40012038 0x4001203C 0x40012200 0x40012204 0x40012208 0x4001220C 0x40012210 0x40012214
Description
Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields.
Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields.
Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields.
Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields.
Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields.
Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields.
Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields.
Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields.
Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields.
Clock control register. See PERI_CLOCK_CTL0 for the details of bit fields.
Trigger command register
Trigger control register
Trigger control register. See PERI_TR_GR0_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR0_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR0_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR0_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR0_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR0_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR0_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR0_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR0_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR0_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR0_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR0_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR0_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR0_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR0_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR0_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR0_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR0_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR0_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR0_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR0_TR_OUT_CTL0 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
20
Register PERI_TR_GR1_TR_OUT_CTL6 PERI_TR_GR1_TR_OUT_CTL7 PERI_TR_GR1_TR_OUT_CTL8 PERI_TR_GR1_TR_OUT_CTL9 PERI_TR_GR1_TR_OUT_CTL10 PERI_TR_GR1_TR_OUT_CTL11 PERI_TR_GR1_TR_OUT_CTL12 PERI_TR_GR1_TR_OUT_CTL13 PERI_TR_GR1_TR_OUT_CTL14 PERI_TR_GR1_TR_OUT_CTL15 PERI_TR_GR2_TR_OUT_CTL0 PERI_TR_GR2_TR_OUT_CTL1 PERI_TR_GR2_TR_OUT_CTL2 PERI_TR_GR2_TR_OUT_CTL3 PERI_TR_GR2_TR_OUT_CTL4 PERI_TR_GR2_TR_OUT_CTL5 PERI_TR_GR2_TR_OUT_CTL6 PERI_TR_GR2_TR_OUT_CTL7 PERI_TR_GR2_TR_OUT_CTL8 PERI_TR_GR2_TR_OUT_CTL9 PERI_TR_GR2_TR_OUT_CTL10 PERI_TR_GR2_TR_OUT_CTL11 PERI_TR_GR2_TR_OUT_CTL12 PERI_TR_GR2_TR_OUT_CTL13 PERI_TR_GR3_TR_OUT_CTL0 PERI_TR_GR3_TR_OUT_CTL1 PERI_TR_GR3_TR_OUT_CTL2 PERI_TR_GR3_TR_OUT_CTL3 PERI_TR_GR3_TR_OUT_CTL4
Peripheral Registers
Address 0x40012218 0x4001221C 0x40012220 0x40012224 0x40012228 0x4001222C 0x40012230 0x40012234 0x40012238 0x4001223C 0x40012400 0x40012404 0x40012408 0x4001240C 0x40012410 0x40012414 0x40012418 0x4001241C 0x40012420 0x40012424 0x40012428 0x4001242C 0x40012430 0x40012434 0x40012600 0x40012604 0x40012608 0x4001260C 0x40012610
Description
Trigger control register. See PERI_TR_GR0_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR0_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR0_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR0_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR0_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR0_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR0_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR0_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR0_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR0_TR_OUT_CTL0 for the details of bit fields.
Trigger control register
Trigger control register. See PERI_TR_GR2_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR2_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR2_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR2_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR2_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR2_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR2_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR2_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR2_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR2_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR2_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR2_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR2_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR2_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR2_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR2_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR2_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR2_TR_OUT_CTL0 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
21
Peripheral Registers
Register PERI_TR_GR3_TR_OUT_CTL5 PERI_TR_GR3_TR_OUT_CTL6 PERI_TR_GR3_TR_OUT_CTL7 PERI_TR_GR3_TR_OUT_CTL8 PERI_TR_GR3_TR_OUT_CTL9 PERI_TR_GR3_TR_OUT_CTL10 PERI_TR_GR3_TR_OUT_CTL11 PERI_TR_GR3_TR_OUT_CTL12 PERI_TR_GR3_TR_OUT_CTL13 PERI_TR_GR4_TR_OUT_CTL0 PERI_TR_GR4_TR_OUT_CTL1 PERI_TR_GR5_TR_OUT_CTL0 PERI_TR_GR5_TR_OUT_CTL1 PERI_TR_GR6_TR_OUT_CTL0 PERI_TR_GR7_TR_OUT_CTL0 PERI_TR_GR7_TR_OUT_CTL1 PERI_TR_GR8_TR_OUT_CTL0 PERI_TR_GR8_TR_OUT_CTL1 PERI_TR_GR9_TR_OUT_CTL0 PERI_TR_GR9_TR_OUT_CTL1 PERI_TR_GR9_TR_OUT_CTL2 PERI_TR_GR9_TR_OUT_CTL3 PERI_TR_GR9_TR_OUT_CTL4 PERI_TR_GR9_TR_OUT_CTL5 PERI_TR_GR9_TR_OUT_CTL6 PERI_TR_GR9_TR_OUT_CTL7 PERI_TR_GR10_TR_OUT_CTL0 PERI_TR_GR10_TR_OUT_CTL1 PERI_TR_GR10_TR_OUT_CTL2 PERI_TR_GR10_TR_OUT_CTL3
Address 0x40012614 0x40012618 0x4001261C 0x40012620 0x40012624 0x40012628 0x4001262C 0x40012630 0x40012634 0x40012800 0x40012804 0x40012A00 0x40012A04 0x40012C00 0x40012E00 0x40012E04 0x40013000 0x40013004 0x40013200 0x40013204 0x40013208 0x4001320C 0x40013210 0x40013214 0x40013218 0x4001321C 0x40013400 0x40013404 0x40013408 0x4001340C
Description
Trigger control register. See PERI_TR_GR2_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR2_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR2_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR2_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR2_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR2_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR2_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR2_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR2_TR_OUT_CTL0 for the details of bit fields.
Trigger control register
Trigger control register. See PERI_TR_GR4_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR4_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR4_TR_OUT_CTL0 for the details of bit fields.
Trigger control register
Trigger control register. See PERI_TR_GR4_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR4_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR4_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR4_TR_OUT_CTL0 for the details of bit fields.
Trigger control register
Trigger control register. See PERI_TR_GR9_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR9_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR9_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR9_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR9_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR9_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR9_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR9_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR9_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR9_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR9_TR_OUT_CTL0 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
22
Peripheral Registers
Register PERI_TR_GR10_TR_OUT_CTL4 PERI_TR_GR10_TR_OUT_CTL5 PERI_TR_GR10_TR_OUT_CTL6 PERI_TR_GR10_TR_OUT_CTL7 PERI_TR_GR11_TR_OUT_CTL0 PERI_TR_GR11_TR_OUT_CTL1 PERI_TR_GR11_TR_OUT_CTL2 PERI_TR_GR11_TR_OUT_CTL3 PERI_TR_GR11_TR_OUT_CTL4 PERI_TR_GR11_TR_OUT_CTL5 PERI_TR_GR11_TR_OUT_CTL6 PERI_TR_GR11_TR_OUT_CTL7 PERI_TR_GR11_TR_OUT_CTL8 PERI_TR_GR11_TR_OUT_CTL9 PERI_TR_GR11_TR_OUT_CTL10 PERI_TR_GR11_TR_OUT_CTL11 PERI_TR_GR11_TR_OUT_CTL12 PERI_TR_GR11_TR_OUT_CTL13 PERI_TR_GR11_TR_OUT_CTL14 PERI_TR_GR11_TR_OUT_CTL15 PERI_TR_GR12_TR_OUT_CTL0 PERI_TR_GR12_TR_OUT_CTL1 PERI_TR_GR12_TR_OUT_CTL2 PERI_TR_GR12_TR_OUT_CTL3 PERI_TR_GR12_TR_OUT_CTL4 PERI_TR_GR12_TR_OUT_CTL5 PERI_TR_GR12_TR_OUT_CTL6 PERI_TR_GR12_TR_OUT_CTL7 PERI_TR_GR12_TR_OUT_CTL8 PERI_TR_GR12_TR_OUT_CTL9
Address 0x40013410 0x40013414 0x40013418 0x4001341C 0x40013600 0x40013604 0x40013608 0x4001360C 0x40013610 0x40013614 0x40013618 0x4001361C 0x40013620 0x40013624 0x40013628 0x4001362C 0x40013630 0x40013634 0x40013638 0x4001363C 0x40013800 0x40013804 0x40013808 0x4001380C 0x40013810 0x40013814 0x40013818 0x4001381C 0x40013820 0x40013824
Description
Trigger control register. See PERI_TR_GR9_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR9_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR9_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR9_TR_OUT_CTL0 for the details of bit fields.
Trigger control register
Trigger control register. See PERI_TR_GR11_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR11_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR11_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR11_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR11_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR11_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR11_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR11_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR11_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR11_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR11_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR11_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR11_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR11_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR11_TR_OUT_CTL0 for the details of bit fields.
Trigger control register
Trigger control register. See PERI_TR_GR12_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR12_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR12_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR12_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR12_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR12_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR12_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR12_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR12_TR_OUT_CTL0 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
23
Peripheral Registers
Register PERI_TR_GR13_TR_OUT_CTL0 PERI_TR_GR13_TR_OUT_CTL1 PERI_TR_GR13_TR_OUT_CTL2 PERI_TR_GR13_TR_OUT_CTL3 PERI_TR_GR13_TR_OUT_CTL4 PERI_TR_GR13_TR_OUT_CTL5 PERI_TR_GR13_TR_OUT_CTL6 PERI_TR_GR13_TR_OUT_CTL7 PERI_TR_GR13_TR_OUT_CTL8 PERI_TR_GR13_TR_OUT_CTL9 PERI_TR_GR13_TR_OUT_CTL10 PERI_TR_GR13_TR_OUT_CTL11 PERI_TR_GR13_TR_OUT_CTL12 PERI_TR_GR13_TR_OUT_CTL13 PERI_TR_GR13_TR_OUT_CTL14 PERI_TR_GR13_TR_OUT_CTL15 PERI_TR_GR13_TR_OUT_CTL16 PERI_TR_GR13_TR_OUT_CTL17 PERI_TR_GR14_TR_OUT_CTL0 PERI_TR_GR14_TR_OUT_CTL1 PERI_TR_GR14_TR_OUT_CTL2 PERI_TR_GR14_TR_OUT_CTL3 PERI_TR_GR14_TR_OUT_CTL4 PERI_TR_GR14_TR_OUT_CTL5 PERI_TR_GR14_TR_OUT_CTL6 PERI_TR_GR14_TR_OUT_CTL7 PERI_TR_GR14_TR_OUT_CTL8 PERI_TR_GR14_TR_OUT_CTL9 PERI_TR_GR14_TR_OUT_CTL10 PERI_TR_GR14_TR_OUT_CTL11
Address 0x40013A00 0x40013A04 0x40013A08 0x40013A0C 0x40013A10 0x40013A14 0x40013A18 0x40013A1C 0x40013A20 0x40013A24 0x40013A28 0x40013A2C 0x40013A30 0x40013A34 0x40013A38 0x40013A3C 0x40013A40 0x40013A44 0x40013C00 0x40013C04 0x40013C08 0x40013C0C 0x40013C10 0x40013C14 0x40013C18 0x40013C1C 0x40013C20 0x40013C24 0x40013C28 0x40013C2C
Description
Trigger control register
Trigger control register. See PERI_TR_GR13_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR13_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR13_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR13_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR13_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR13_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR13_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR13_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR13_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR13_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR13_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR13_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR13_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR13_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR13_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR13_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR13_TR_OUT_CTL0 for the details of bit fields.
Trigger control register
Trigger control register. See PERI_TR_GR14_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR14_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR14_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR14_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR14_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR14_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR14_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR14_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR14_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR14_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR14_TR_OUT_CTL0 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
24
Peripheral Registers
Register PERI_TR_GR14_TR_OUT_CTL12 PERI_TR_GR14_TR_OUT_CTL13 PERI_TR_GR14_TR_OUT_CTL14 PERI_TR_GR14_TR_OUT_CTL15 PERI_PPU_PR0_ADDR0 PERI_PPU_PR0_ATT0 PERI_PPU_PR0_ADDR1 PERI_PPU_PR0_ATT1 PERI_PPU_PR1_ADDR0 PERI_PPU_PR1_ATT0 PERI_PPU_PR1_ADDR1 PERI_PPU_PR1_ATT1 PERI_PPU_PR2_ADDR0 PERI_PPU_PR2_ATT0 PERI_PPU_PR2_ADDR1 PERI_PPU_PR2_ATT1 PERI_PPU_PR3_ADDR0 PERI_PPU_PR3_ATT0 PERI_PPU_PR3_ADDR1 PERI_PPU_PR3_ATT1 PERI_PPU_PR4_ADDR0 PERI_PPU_PR4_ATT0 PERI_PPU_PR4_ADDR1 PERI_PPU_PR4_ATT1 PERI_PPU_PR5_ADDR0 PERI_PPU_PR5_ATT0 PERI_PPU_PR5_ADDR1 PERI_PPU_PR5_ATT1 PERI_PPU_PR6_ADDR0 PERI_PPU_PR6_ATT0 PERI_PPU_PR6_ADDR1 PERI_PPU_PR6_ATT1
Address 0x40013C30 0x40013C34 0x40013C38 0x40013C3C 0x40014000 0x40014004 0x40014020 0x40014024 0x40014040 0x40014044 0x40014060 0x40014064 0x40014080 0x40014084 0x400140A0 0x400140A4 0x400140C0 0x400140C4 0x400140E0 0x400140E4 0x40014100 0x40014104 0x40014120 0x40014124 0x40014140 0x40014144 0x40014160 0x40014164 0x40014180 0x40014184 0x400141A0 0x400141A4
Description
Trigger control register. See PERI_TR_GR14_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR14_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR14_TR_OUT_CTL0 for the details of bit fields.
Trigger control register. See PERI_TR_GR14_TR_OUT_CTL0 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure)
PPU region address 1 (master structure)
PPU region attributes 1 (master structure)
PPU region address 0 (slave structure). See PERI_PPU_PR0_ADDR0 for the details of bit fields.
PPU region attributes 0 (slave structure). See PERI_PPU_PR0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_PPU_PR0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure). See PERI_PPU_PR0_ADDR0 for the details of bit fields.
PPU region attributes 0 (slave structure). See PERI_PPU_PR0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_PPU_PR0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure). See PERI_PPU_PR0_ADDR0 for the details of bit fields.
PPU region attributes 0 (slave structure). See PERI_PPU_PR0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_PPU_PR0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure). See PERI_PPU_PR0_ADDR0 for the details of bit fields.
PPU region attributes 0 (slave structure). See PERI_PPU_PR0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_PPU_PR0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure). See PERI_PPU_PR0_ADDR0 for the details of bit fields.
PPU region attributes 0 (slave structure). See PERI_PPU_PR0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_PPU_PR0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure). See PERI_PPU_PR0_ADDR0 for the details of bit fields.
PPU region attributes 0 (slave structure). See PERI_PPU_PR0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_PPU_PR0_ATT1 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
25
Register PERI_PPU_PR7_ADDR0 PERI_PPU_PR7_ATT0 PERI_PPU_PR7_ADDR1 PERI_PPU_PR7_ATT1 PERI_PPU_PR8_ADDR0 PERI_PPU_PR8_ATT0 PERI_PPU_PR8_ADDR1 PERI_PPU_PR8_ATT1 PERI_PPU_PR9_ADDR0 PERI_PPU_PR9_ATT0 PERI_PPU_PR9_ADDR1 PERI_PPU_PR9_ATT1 PERI_PPU_PR10_ADDR0 PERI_PPU_PR10_ATT0 PERI_PPU_PR10_ADDR1 PERI_PPU_PR10_ATT1 PERI_PPU_PR11_ADDR0 PERI_PPU_PR11_ATT0 PERI_PPU_PR11_ADDR1 PERI_PPU_PR11_ATT1 PERI_PPU_PR12_ADDR0 PERI_PPU_PR12_ATT0 PERI_PPU_PR12_ADDR1 PERI_PPU_PR12_ATT1 PERI_PPU_PR13_ADDR0 PERI_PPU_PR13_ATT0 PERI_PPU_PR13_ADDR1 PERI_PPU_PR13_ATT1 PERI_PPU_PR14_ADDR0 PERI_PPU_PR14_ATT0 PERI_PPU_PR14_ADDR1
Peripheral Registers
Address 0x400141C0 0x400141C4 0x400141E0 0x400141E4 0x40014200 0x40014204 0x40014220 0x40014224 0x40014240 0x40014244 0x40014260 0x40014264 0x40014280 0x40014284 0x400142A0 0x400142A4 0x400142C0 0x400142C4 0x400142E0 0x400142E4 0x40014300 0x40014304 0x40014320 0x40014324 0x40014340 0x40014344 0x40014360 0x40014364 0x40014380 0x40014384 0x400143A0
Description
PPU region address 0 (slave structure). See PERI_PPU_PR0_ADDR0 for the details of bit fields.
PPU region attributes 0 (slave structure). See PERI_PPU_PR0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_PPU_PR0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure). See PERI_PPU_PR0_ADDR0 for the details of bit fields.
PPU region attributes 0 (slave structure). See PERI_PPU_PR0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_PPU_PR0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure). See PERI_PPU_PR0_ADDR0 for the details of bit fields.
PPU region attributes 0 (slave structure). See PERI_PPU_PR0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_PPU_PR0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure). See PERI_PPU_PR0_ADDR0 for the details of bit fields.
PPU region attributes 0 (slave structure). See PERI_PPU_PR0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_PPU_PR0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure). See PERI_PPU_PR0_ADDR0 for the details of bit fields.
PPU region attributes 0 (slave structure). See PERI_PPU_PR0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_PPU_PR0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure). See PERI_PPU_PR0_ADDR0 for the details of bit fields.
PPU region attributes 0 (slave structure). See PERI_PPU_PR0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_PPU_PR0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure). See PERI_PPU_PR0_ADDR0 for the details of bit fields.
PPU region attributes 0 (slave structure). See PERI_PPU_PR0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_PPU_PR0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure). See PERI_PPU_PR0_ADDR0 for the details of bit fields.
PPU region attributes 0 (slave structure). See PERI_PPU_PR0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
26
Peripheral Registers
Register PERI_PPU_PR14_ATT1
PERI_PPU_PR15_ADDR0
PERI_PPU_PR15_ATT0 PERI_PPU_PR15_ADDR1 PERI_PPU_PR15_ATT1 PERI_PPU_GR0_ADDR0 PERI_PPU_GR0_ATT0 PERI_PPU_GR0_ADDR1 PERI_PPU_GR0_ATT1 PERI_PPU_GR1_ADDR0 PERI_PPU_GR1_ATT0 PERI_PPU_GR1_ADDR1 PERI_PPU_GR1_ATT1 PERI_PPU_GR2_ADDR0 PERI_PPU_GR2_ATT0 PERI_PPU_GR2_ADDR1 PERI_PPU_GR2_ATT1 PERI_PPU_GR3_ADDR0 PERI_PPU_GR3_ATT0 PERI_PPU_GR3_ADDR1 PERI_PPU_GR3_ATT1 PERI_PPU_GR4_ADDR0 PERI_PPU_GR4_ATT0 PERI_PPU_GR4_ADDR1 PERI_PPU_GR4_ATT1 PERI_PPU_GR6_ADDR0 PERI_PPU_GR6_ATT0 PERI_PPU_GR6_ADDR1 PERI_PPU_GR6_ATT1 PERI_PPU_GR9_ADDR0 PERI_PPU_GR9_ATT0 PERI_PPU_GR9_ADDR1 PERI_PPU_GR9_ATT1 PERI_PPU_GR10_ADDR0 PERI_PPU_GR10_ATT0
Address 0x400143A4
0x400143C0
0x400143C4 0x400143E0 0x400143E4 0x40015000 0x40015004 0x40015020 0x40015024 0x40015040 0x40015044 0x40015060 0x40015064 0x40015080 0x40015084 0x400150A0 0x400150A4 0x400150C0 0x400150C4 0x400150E0 0x400150E4 0x40015100 0x40015104 0x40015120 0x40015124 0x40015180 0x40015184 0x400151A0 0x400151A4 0x40015240 0x40015244 0x40015260 0x40015264 0x40015280 0x40015284
Description
PPU region attributes 1 (master structure). See PERI_PPU_PR0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure). See PERI_PPU_PR0_ADDR0 for the details of bit fields.
PPU region attributes 0 (slave structure). See PERI_PPU_PR0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_PPU_PR0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure)
PPU region address 1 (master structure)
PPU region attributes 1 (master structure)
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_PPU_GR0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_PPU_GR0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_PPU_GR0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_PPU_GR0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_PPU_GR0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_PPU_GR0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_PPU_GR0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_PPU_GR0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_PPU_GR0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_PPU_GR0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure)
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_PPU_GR0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_PPU_GR0_ATT0 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
27
Register PERI_PPU_GR10_ADDR1 PERI_PPU_GR10_ATT1 PERI_GR1_PPU_SL0_ADDR0 PERI_GR1_PPU_SL0_ATT0 PERI_GR1_PPU_SL0_ADDR1 PERI_GR1_PPU_SL0_ATT1 PERI_GR1_PPU_SL1_ADDR0 PERI_GR1_PPU_SL1_ATT0 PERI_GR1_PPU_SL1_ADDR1 PERI_GR1_PPU_SL1_ATT1 PERI_GR2_PPU_SL0_ADDR0 PERI_GR2_PPU_SL0_ATT0 PERI_GR2_PPU_SL0_ADDR1 PERI_GR2_PPU_SL0_ATT1 PERI_GR2_PPU_SL1_ADDR0 PERI_GR2_PPU_SL1_ATT0 PERI_GR2_PPU_SL1_ADDR1 PERI_GR2_PPU_SL1_ATT1 PERI_GR2_PPU_SL2_ADDR0 PERI_GR2_PPU_SL2_ATT0 PERI_GR2_PPU_SL2_ADDR1 PERI_GR2_PPU_SL2_ATT1 PERI_GR2_PPU_SL3_ADDR0 PERI_GR2_PPU_SL3_ATT0 PERI_GR2_PPU_SL3_ADDR1 PERI_GR2_PPU_SL3_ATT1 PERI_GR2_PPU_SL4_ADDR0 PERI_GR2_PPU_SL4_ATT0 PERI_GR2_PPU_SL4_ADDR1 PERI_GR2_PPU_SL4_ATT1 PERI_GR2_PPU_SL5_ADDR0 PERI_GR2_PPU_SL5_ATT0 PERI_GR2_PPU_SL5_ADDR1 PERI_GR2_PPU_SL5_ATT1 PERI_GR2_PPU_SL6_ADDR0
Peripheral Registers
Address 0x400152A0 0x400152A4 0x40100000 0x40100004 0x40100020 0x40100024 0x40100040 0x40100044 0x40100060 0x40100064 0x40200000 0x40200004 0x40200020 0x40200024 0x40200040 0x40200044 0x40200060 0x40200064 0x40200080 0x40200084 0x402000A0 0x402000A4 0x402000C0 0x402000C4 0x402000E0 0x402000E4 0x40200100 0x40200104 0x40200120 0x40200124 0x40200140 0x40200144 0x40200160 0x40200164 0x40200180
Description
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_PPU_GR0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure)
PPU region address 1 (master structure)
PPU region attributes 1 (master structure)
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR1_PPU_SL0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR1_PPU_SL0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR1_PPU_SL0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR1_PPU_SL0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR1_PPU_SL0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR1_PPU_SL0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR1_PPU_SL0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
28
Peripheral Registers
Register PERI_GR2_PPU_SL6_ATT0 PERI_GR2_PPU_SL6_ADDR1 PERI_GR2_PPU_SL6_ATT1 PERI_GR2_PPU_SL7_ADDR0 PERI_GR2_PPU_SL7_ATT0 PERI_GR2_PPU_SL7_ADDR1 PERI_GR2_PPU_SL7_ATT1 PERI_GR2_PPU_SL8_ADDR0 PERI_GR2_PPU_SL8_ATT0 PERI_GR2_PPU_SL8_ADDR1 PERI_GR2_PPU_SL8_ATT1
PERI_GR2_PPU_SL9_ADDR0
PERI_GR2_PPU_SL9_ATT0 PERI_GR2_PPU_SL9_ADDR1 PERI_GR2_PPU_SL9_ATT1 PERI_GR2_PPU_SL12_ADDR0 PERI_GR2_PPU_SL12_ATT0 PERI_GR2_PPU_SL12_ADDR1 PERI_GR2_PPU_SL12_ATT1 PERI_GR2_PPU_SL13_ADDR0 PERI_GR2_PPU_SL13_ATT0 PERI_GR2_PPU_SL13_ADDR1 PERI_GR2_PPU_SL13_ATT1 PERI_GR2_PPU_RG0_ADDR0 PERI_GR2_PPU_RG0_ATT0 PERI_GR2_PPU_RG0_ADDR1 PERI_GR2_PPU_RG0_ATT1 PERI_GR2_PPU_RG1_ADDR0 PERI_GR2_PPU_RG1_ATT0 PERI_GR2_PPU_RG1_ADDR1 PERI_GR2_PPU_RG1_ATT1 PERI_GR2_PPU_RG2_ADDR0 PERI_GR2_PPU_RG2_ATT0 PERI_GR2_PPU_RG2_ADDR1 PERI_GR2_PPU_RG2_ATT1
Address 0x40200184 0x402001A0 0x402001A4 0x402001C0 0x402001C4 0x402001E0 0x402001E4 0x40200200 0x40200204 0x40200220 0x40200224
0x40200240
0x40200244 0x40200260 0x40200264 0x40200300 0x40200304 0x40200320 0x40200324 0x40200340 0x40200344 0x40200360 0x40200364 0x40201000 0x40201004 0x40201020 0x40201024 0x40201040 0x40201044 0x40201060 0x40201064 0x40201080 0x40201084 0x402010A0 0x402010A4
Description
PPU region attributes 0 (slave structure). See PERI_GR1_PPU_SL0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR1_PPU_SL0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure)
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure). See PERI_GR2_PPU_SL8_ADDR0 for the details of bit fields.
PPU region attributes 0 (slave structure). See PERI_GR2_PPU_SL8_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR2_PPU_SL8_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR1_PPU_SL0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure)
PPU region address 1 (master structure)
PPU region attributes 1 (master structure)
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR2_PPU_RG0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR2_PPU_RG0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR2_PPU_RG0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR2_PPU_RG0_ATT1 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
29
Peripheral Registers
Register PERI_GR2_PPU_RG3_ADDR0 PERI_GR2_PPU_RG3_ATT0 PERI_GR2_PPU_RG3_ADDR1 PERI_GR2_PPU_RG3_ATT1 PERI_GR2_PPU_RG4_ADDR0 PERI_GR2_PPU_RG4_ATT0 PERI_GR2_PPU_RG4_ADDR1 PERI_GR2_PPU_RG4_ATT1 PERI_GR2_PPU_RG5_ADDR0 PERI_GR2_PPU_RG5_ATT0 PERI_GR2_PPU_RG5_ADDR1 PERI_GR2_PPU_RG5_ATT1 PERI_GR2_PPU_RG6_ADDR0 PERI_GR2_PPU_RG6_ATT0 PERI_GR2_PPU_RG6_ADDR1 PERI_GR2_PPU_RG6_ATT1 PERI_GR2_PPU_RG7_ADDR0 PERI_GR2_PPU_RG7_ATT0 PERI_GR2_PPU_RG7_ADDR1 PERI_GR2_PPU_RG7_ATT1 PERI_GR2_PPU_RG8_ADDR0 PERI_GR2_PPU_RG8_ATT0 PERI_GR2_PPU_RG8_ADDR1 PERI_GR2_PPU_RG8_ATT1 PERI_GR2_PPU_RG9_ADDR0 PERI_GR2_PPU_RG9_ATT0 PERI_GR2_PPU_RG9_ADDR1 PERI_GR2_PPU_RG9_ATT1 PERI_GR2_PPU_RG10_ADDR0 PERI_GR2_PPU_RG10_ATT0 PERI_GR2_PPU_RG10_ADDR1 PERI_GR2_PPU_RG10_ATT1 PERI_GR2_PPU_RG11_ADDR0 PERI_GR2_PPU_RG11_ATT0 PERI_GR2_PPU_RG11_ADDR1
Address 0x402010C0 0x402010C4 0x402010E0 0x402010E4 0x40201100 0x40201104 0x40201120 0x40201124 0x40201140 0x40201144 0x40201160 0x40201164 0x40201180 0x40201184 0x402011A0 0x402011A4 0x402011C0 0x402011C4 0x402011E0 0x402011E4 0x40201200 0x40201204 0x40201220 0x40201224 0x40201240 0x40201244 0x40201260 0x40201264 0x40201280 0x40201284 0x402012A0 0x402012A4 0x402012C0 0x402012C4 0x402012E0
Description
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR2_PPU_RG0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR2_PPU_RG0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR2_PPU_RG0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR2_PPU_RG0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR2_PPU_RG0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR2_PPU_RG0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR2_PPU_RG0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR2_PPU_RG0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR2_PPU_RG0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR2_PPU_RG0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR2_PPU_RG0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR2_PPU_RG0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR2_PPU_RG0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR2_PPU_RG0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR2_PPU_RG0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR2_PPU_RG0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR2_PPU_RG0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
30
Register PERI_GR2_PPU_RG11_ATT1 PERI_GR2_PPU_RG12_ADDR0 PERI_GR2_PPU_RG12_ATT0 PERI_GR2_PPU_RG12_ADDR1 PERI_GR2_PPU_RG12_ATT1 PERI_GR2_PPU_RG13_ADDR0 PERI_GR2_PPU_RG13_ATT0 PERI_GR2_PPU_RG13_ADDR1 PERI_GR2_PPU_RG13_ATT1 PERI_GR2_PPU_RG14_ADDR0 PERI_GR2_PPU_RG14_ATT0 PERI_GR2_PPU_RG14_ADDR1 PERI_GR2_PPU_RG14_ATT1 PERI_GR2_PPU_RG15_ADDR0 PERI_GR2_PPU_RG15_ATT0 PERI_GR2_PPU_RG15_ADDR1 PERI_GR2_PPU_RG15_ATT1 PERI_GR2_PPU_RG16_ADDR0 PERI_GR2_PPU_RG16_ATT0 PERI_GR2_PPU_RG16_ADDR1 PERI_GR2_PPU_RG16_ATT1 PERI_GR2_PPU_RG17_ADDR0 PERI_GR2_PPU_RG17_ATT0 PERI_GR2_PPU_RG17_ADDR1 PERI_GR2_PPU_RG17_ATT1 PERI_GR2_PPU_RG18_ADDR0 PERI_GR2_PPU_RG18_ATT0 PERI_GR2_PPU_RG18_ADDR1 PERI_GR2_PPU_RG18_ATT1 PERI_GR2_PPU_RG19_ADDR0 PERI_GR2_PPU_RG19_ATT0 PERI_GR2_PPU_RG19_ADDR1 PERI_GR2_PPU_RG19_ATT1 PERI_GR2_PPU_RG20_ADDR0
Peripheral Registers
Address 0x402012E4 0x40201300 0x40201304 0x40201320 0x40201324 0x40201340 0x40201344 0x40201360 0x40201364 0x40201380 0x40201384 0x402013A0 0x402013A4 0x402013C0 0x402013C4 0x402013E0 0x402013E4 0x40201400 0x40201404 0x40201420 0x40201424 0x40201440 0x40201444 0x40201460 0x40201464 0x40201480 0x40201484 0x402014A0 0x402014A4 0x402014C0 0x402014C4 0x402014E0 0x402014E4 0x40201500
Description
PPU region attributes 1 (master structure). See PERI_GR2_PPU_RG0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR2_PPU_RG0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR2_PPU_RG0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR2_PPU_RG0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR2_PPU_RG0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR2_PPU_RG0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR2_PPU_RG0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR2_PPU_RG0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR2_PPU_RG0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR2_PPU_RG0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR2_PPU_RG0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR2_PPU_RG0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR2_PPU_RG0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR2_PPU_RG0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR2_PPU_RG0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR2_PPU_RG0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR2_PPU_RG0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
31
Peripheral Registers
Register PERI_GR2_PPU_RG20_ATT0 PERI_GR2_PPU_RG20_ADDR1 PERI_GR2_PPU_RG20_ATT1 PERI_GR2_PPU_RG21_ADDR0 PERI_GR2_PPU_RG21_ATT0 PERI_GR2_PPU_RG21_ADDR1 PERI_GR2_PPU_RG21_ATT1 PERI_GR2_PPU_RG22_ADDR0 PERI_GR2_PPU_RG22_ATT0 PERI_GR2_PPU_RG22_ADDR1 PERI_GR2_PPU_RG22_ATT1 PERI_GR2_PPU_RG23_ADDR0 PERI_GR2_PPU_RG23_ATT0 PERI_GR2_PPU_RG23_ADDR1 PERI_GR2_PPU_RG23_ATT1 PERI_GR2_PPU_RG24_ADDR0 PERI_GR2_PPU_RG24_ATT0 PERI_GR2_PPU_RG24_ADDR1 PERI_GR2_PPU_RG24_ATT1 PERI_GR2_PPU_RG25_ADDR0 PERI_GR2_PPU_RG25_ATT0 PERI_GR2_PPU_RG25_ADDR1 PERI_GR2_PPU_RG25_ATT1 PERI_GR2_PPU_RG26_ADDR0 PERI_GR2_PPU_RG26_ATT0 PERI_GR2_PPU_RG26_ADDR1 PERI_GR2_PPU_RG26_ATT1 PERI_GR2_PPU_RG27_ADDR0 PERI_GR2_PPU_RG27_ATT0 PERI_GR2_PPU_RG27_ADDR1 PERI_GR2_PPU_RG27_ATT1 PERI_GR2_PPU_RG28_ADDR0 PERI_GR2_PPU_RG28_ATT0 PERI_GR2_PPU_RG28_ADDR1 PERI_GR2_PPU_RG28_ATT1
Address 0x40201504 0x40201520 0x40201524 0x40201540 0x40201544 0x40201560 0x40201564 0x40201580 0x40201584 0x402015A0 0x402015A4 0x402015C0 0x402015C4 0x402015E0 0x402015E4 0x40201600 0x40201604 0x40201620 0x40201624 0x40201640 0x40201644 0x40201660 0x40201664 0x40201680 0x40201684 0x402016A0 0x402016A4 0x402016C0 0x402016C4 0x402016E0 0x402016E4 0x40201700 0x40201704 0x40201720 0x40201724
Description
PPU region attributes 0 (slave structure). See PERI_GR2_PPU_RG0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR2_PPU_RG0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR2_PPU_RG0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR2_PPU_RG0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR2_PPU_RG0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR2_PPU_RG0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR2_PPU_RG0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR2_PPU_RG0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR2_PPU_RG0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR2_PPU_RG0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure)
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR2_PPU_RG0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR2_PPU_RG25_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR2_PPU_RG0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR2_PPU_RG25_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR2_PPU_RG0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR2_PPU_RG25_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR2_PPU_RG0_ATT1 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
32
Peripheral Registers
Register PERI_GR3_PPU_SL0_ADDR0 PERI_GR3_PPU_SL0_ATT0 PERI_GR3_PPU_SL0_ADDR1 PERI_GR3_PPU_SL0_ATT1 PERI_GR3_PPU_SL1_ADDR0 PERI_GR3_PPU_SL1_ATT0 PERI_GR3_PPU_SL1_ADDR1 PERI_GR3_PPU_SL1_ATT1 PERI_GR3_PPU_SL2_ADDR0 PERI_GR3_PPU_SL2_ATT0 PERI_GR3_PPU_SL2_ADDR1 PERI_GR3_PPU_SL2_ATT1 PERI_GR3_PPU_SL3_ADDR0 PERI_GR3_PPU_SL3_ATT0 PERI_GR3_PPU_SL3_ADDR1 PERI_GR3_PPU_SL3_ATT1 PERI_GR3_PPU_SL4_ADDR0 PERI_GR3_PPU_SL4_ATT0 PERI_GR3_PPU_SL4_ADDR1 PERI_GR3_PPU_SL4_ATT1 PERI_GR3_PPU_SL5_ADDR0 PERI_GR3_PPU_SL5_ATT0 PERI_GR3_PPU_SL5_ADDR1 PERI_GR3_PPU_SL5_ATT1 PERI_GR3_PPU_SL6_ADDR0 PERI_GR3_PPU_SL6_ATT0 PERI_GR3_PPU_SL6_ADDR1 PERI_GR3_PPU_SL6_ATT1 PERI_GR3_PPU_SL8_ADDR0 PERI_GR3_PPU_SL8_ATT0 PERI_GR3_PPU_SL8_ADDR1 PERI_GR3_PPU_SL8_ATT1
PERI_GR3_PPU_SL9_ADDR0
PERI_GR3_PPU_SL9_ATT0 PERI_GR3_PPU_SL9_ADDR1
Address 0x40300000 0x40300004 0x40300020 0x40300024 0x40300040 0x40300044 0x40300060 0x40300064 0x40300080 0x40300084 0x403000A0 0x403000A4 0x403000C0 0x403000C4 0x403000E0 0x403000E4 0x40300100 0x40300104 0x40300120 0x40300124 0x40300140 0x40300144 0x40300160 0x40300164 0x40300180 0x40300184 0x403001A0 0x403001A4 0x40300200 0x40300204 0x40300220 0x40300224
0x40300240
0x40300244 0x40300260
Description
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR1_PPU_SL0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure)
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR1_PPU_SL0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR1_PPU_SL0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR1_PPU_SL0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR1_PPU_SL0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR2_PPU_SL8_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR1_PPU_SL0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure). See PERI_GR3_PPU_SL8_ADDR0 for the details of bit fields.
PPU region attributes 0 (slave structure). See PERI_GR1_PPU_SL0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
33
Peripheral Registers
Register PERI_GR3_PPU_SL9_ATT1 PERI_GR3_PPU_SL10_ADDR0 PERI_GR3_PPU_SL10_ATT0 PERI_GR3_PPU_SL10_ADDR1 PERI_GR3_PPU_SL10_ATT1 PERI_GR3_PPU_SL11_ADDR0 PERI_GR3_PPU_SL11_ATT0 PERI_GR3_PPU_SL11_ADDR1 PERI_GR3_PPU_SL11_ATT1 PERI_GR3_PPU_SL12_ADDR0 PERI_GR3_PPU_SL12_ATT0 PERI_GR3_PPU_SL12_ADDR1 PERI_GR3_PPU_SL12_ATT1 PERI_GR4_PPU_SL0_ADDR0 PERI_GR4_PPU_SL0_ATT0 PERI_GR4_PPU_SL0_ADDR1 PERI_GR4_PPU_SL0_ATT1 PERI_GR4_PPU_SL2_ADDR0 PERI_GR4_PPU_SL2_ATT0 PERI_GR4_PPU_SL2_ADDR1 PERI_GR4_PPU_SL2_ATT1 PERI_GR6_PPU_SL0_ADDR0 PERI_GR6_PPU_SL0_ATT0 PERI_GR6_PPU_SL0_ADDR1 PERI_GR6_PPU_SL0_ATT1 PERI_GR6_PPU_SL1_ADDR0 PERI_GR6_PPU_SL1_ATT0 PERI_GR6_PPU_SL1_ADDR1 PERI_GR6_PPU_SL1_ATT1
PERI_GR6_PPU_SL2_ADDR0
PERI_GR6_PPU_SL2_ATT0 PERI_GR6_PPU_SL2_ADDR1 PERI_GR6_PPU_SL2_ATT1
PERI_GR6_PPU_SL3_ADDR0
Address 0x40300264 0x40300280 0x40300284 0x403002A0 0x403002A4 0x403002C0 0x403002C4 0x403002E0 0x403002E4 0x40300300 0x40300304 0x40300320 0x40300324 0x40400000 0x40400004 0x40400020 0x40400024 0x40400080 0x40400084 0x404000A0 0x404000A4 0x40600000 0x40600004 0x40600020 0x40600024 0x40600040 0x40600044 0x40600060 0x40600064
0x40600080
0x40600084 0x406000A0 0x406000A4
0x406000C0
Description
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR1_PPU_SL0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure)
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR1_PPU_SL0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR1_PPU_SL0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR1_PPU_SL0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR1_PPU_SL0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR1_PPU_SL0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure). See PERI_GR6_PPU_SL1_ADDR0 for the details of bit fields.
PPU region attributes 0 (slave structure). See PERI_GR1_PPU_SL0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure). See PERI_GR6_PPU_SL1_ADDR0 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
34
Peripheral Registers
Register PERI_GR6_PPU_SL3_ATT0 PERI_GR6_PPU_SL3_ADDR1 PERI_GR6_PPU_SL3_ATT1 PERI_GR6_PPU_SL4_ADDR0 PERI_GR6_PPU_SL4_ATT0 PERI_GR6_PPU_SL4_ADDR1 PERI_GR6_PPU_SL4_ATT1 PERI_GR6_PPU_SL5_ADDR0 PERI_GR6_PPU_SL5_ATT0 PERI_GR6_PPU_SL5_ADDR1 PERI_GR6_PPU_SL5_ATT1 PERI_GR6_PPU_SL6_ADDR0 PERI_GR6_PPU_SL6_ATT0 PERI_GR6_PPU_SL6_ADDR1 PERI_GR6_PPU_SL6_ATT1 PERI_GR6_PPU_SL7_ADDR0 PERI_GR6_PPU_SL7_ATT0 PERI_GR6_PPU_SL7_ADDR1 PERI_GR6_PPU_SL7_ATT1 PERI_GR6_PPU_SL8_ADDR0 PERI_GR6_PPU_SL8_ATT0 PERI_GR6_PPU_SL8_ADDR1 PERI_GR6_PPU_SL8_ATT1 PERI_GR6_PPU_SL9_ADDR0 PERI_GR6_PPU_SL9_ATT0 PERI_GR6_PPU_SL9_ADDR1 PERI_GR6_PPU_SL9_ATT1 PERI_GR9_PPU_SL0_ADDR0 PERI_GR9_PPU_SL0_ATT0 PERI_GR9_PPU_SL0_ADDR1 PERI_GR9_PPU_SL0_ATT1 PERI_GR9_PPU_SL1_ADDR0
Address 0x406000C4 0x406000E0 0x406000E4 0x40600100 0x40600104 0x40600120 0x40600124 0x40600140 0x40600144 0x40600160 0x40600164 0x40600180 0x40600184 0x406001A0 0x406001A4 0x406001C0 0x406001C4 0x406001E0 0x406001E4 0x40600200 0x40600204 0x40600220 0x40600224 0x40600240 0x40600244 0x40600260 0x40600264 0x41000000 0x41000004 0x41000020 0x41000024 0x41000040
Description
PPU region attributes 0 (slave structure). See PERI_GR1_PPU_SL0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure). See PERI_GR6_PPU_SL1_ADDR0 for the details of bit fields.
PPU region attributes 0 (slave structure). See PERI_GR1_PPU_SL0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure). See PERI_GR6_PPU_SL1_ADDR0 for the details of bit fields.
PPU region attributes 0 (slave structure). See PERI_GR1_PPU_SL0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure). See PERI_GR6_PPU_SL1_ADDR0 for the details of bit fields.
PPU region attributes 0 (slave structure). See PERI_GR1_PPU_SL0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure). See PERI_GR6_PPU_SL1_ADDR0 for the details of bit fields.
PPU region attributes 0 (slave structure). See PERI_GR1_PPU_SL0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure). See PERI_GR6_PPU_SL1_ADDR0 for the details of bit fields.
PPU region attributes 0 (slave structure). See PERI_GR1_PPU_SL0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure). See PERI_GR6_PPU_SL1_ADDR0 for the details of bit fields.
PPU region attributes 0 (slave structure). See PERI_GR1_PPU_SL0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR1_PPU_SL0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
35
Register PERI_GR9_PPU_SL1_ATT0 PERI_GR9_PPU_SL1_ADDR1 PERI_GR9_PPU_SL1_ATT1 PERI_GR10_PPU_SL0_ADDR0 PERI_GR10_PPU_SL0_ATT0 PERI_GR10_PPU_SL0_ADDR1 PERI_GR10_PPU_SL0_ATT1 PERI_GR10_PPU_SL1_ADDR0 PERI_GR10_PPU_SL1_ATT0 PERI_GR10_PPU_SL1_ADDR1 PERI_GR10_PPU_SL1_ATT1 PERI_GR10_PPU_SL2_ADDR0 PERI_GR10_PPU_SL2_ATT0 PERI_GR10_PPU_SL2_ADDR1 PERI_GR10_PPU_SL2_ATT1
Peripheral Registers
Address 0x41000044 0x41000060 0x41000064 0x42A00000 0x42A00004 0x42A00020 0x42A00024 0x42A00040 0x42A00044 0x42A00060 0x42A00064 0x42A00080 0x42A00084 0x42A000A0 0x42A000A4
Description
PPU region attributes 0 (slave structure)
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR1_PPU_SL0_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR2_PPU_SL8_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PPU region address 0 (slave structure)
PPU region attributes 0 (slave structure). See PERI_GR2_PPU_SL8_ATT0 for the details of bit fields.
PPU region address 1 (master structure)
PPU region attributes 1 (master structure). See PERI_GR1_PPU_SL0_ATT1 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
36
PERI_GR0_SL_CTL
2.1.1 PERI_GR0_SL_CTL
Address = 0x40010020 Slave control Address: 0x40010020 Retention: Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:2]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
0
RW
None
R
None
ENABLED_1
None
10
9
8
18
17
16
26
25
24
Bits
Name
1
ENABLED_1
Description
Peripheral group, slave 1 enable. If the slave is disabled, its clock is gated off (constant "0") and its resets are activated.
Note: For peripheral group 0 (the peripheral interconnect MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled. Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
37
PERI_GR1_SL_CTL
2.1.1 PERI_GR1_SL_CTL
Address = 0x40010060 Slave control Address: 0x40010060 Retention: Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:2]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
0
RW
R
R
R
ENABLED_1
ENABLED_0
10
9
8
18
17
16
26
25
24
Bits
Name
1
ENABLED_1
0
ENABLED_0
Description
Peripheral group, slave 1 enable. If the slave is disabled, its clock is gated off (constant "0") and its resets are activated.
Note: For peripheral group 0 (the peripheral interconnect MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled. Default Value: 1
Peripheral group, slave 0 enable. This field is for the peripheral group internal MMIO register slave (PPU structures) and is a constant '1'. This slave can NOT be disabled. Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
38
PERI_GR1_TIMEOUT_CTL
2.1.2 PERI_GR1_TIMEOUT_CTL
Address = 0x40010064 Timeout control Address: 0x40010064 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
TIMEOUT [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
TIMEOUT [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 0
Name TIMEOUT
Description
This field specifies a number of peripheral group (clk_group) clock cycles. If an AHB-Lite bus transfer takes more than the specified number of cycles (timeout detection), the bus transfer is terminated with an AHB-Lite bus error and a fault is generated (and possibly recorded in the fault report structure(s)). "0x0000"-"0xfffe": Number of peripheral group clock cycles. "0xffff": This value is the default/reset value and specifies that no timeout detection is performed: a bus transfer will never be terminated and a fault will never be generated. Default Value: 65535
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
39
PERI_GR2_SL_CTL
2.1.3 PERI_GR2_SL_CTL
Address = 0x400100A0 Slave control Address: 0x400100A0 Retention: Retained
Bits SW Access HW Access
Name
7
RW
R
ENABLED_7
6
RW
R
ENABLED_6
5
RW
R
ENABLED_5
4
RW
R
ENABLED_4
3
RW
R
ENABLED_3
2
RW
R
ENABLED_2
Bits SW Access HW Access
Name
15
14
None
None
None [15:14]
13
RW
R
ENABLED_13
12
RW
R
ENABLED_12
11
10
None
None
None [11:10]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
1 RW R ENABLED_1
9 RW R ENABLED_9 17
25
0 R R ENABLED_0 8 RW R ENABLED_8 16
24
Bits
Name
13
ENABLED_13
12
ENABLED_12
9
ENABLED_9
8
ENABLED_8
7
ENABLED_7
6
ENABLED_6
5
ENABLED_5
4
ENABLED_4
3
ENABLED_3
Description Default Value: 1 Default Value: 1 Default Value: 1 Default Value: 1 Default Value: 1 Default Value: 1 Default Value: 1 Default Value: 1 Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
40
PERI_GR2_SL_CTL
2.1.3
2
1
0
PERI_GR2_SL_CTL (continued)
ENABLED_2 ENABLED_1 ENABLED_0
Peripheral group, slave 2 enable. If the slave is disabled, its clock is gated off (constant "0") and its resets are activated.
Note: For peripheral group 0 (the peripheral interconnect, master interface MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled. Default Value: 1
Peripheral group, slave 1 enable. If the slave is disabled, its clock is gated off (constant "0") and its resets are activated.
Note: For peripheral group 0 (the peripheral interconnect MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled. Default Value: 1
Peripheral group, slave 0 enable. This field is for the peripheral group internal MMIO register slave (PPU structures) and is a constant '1'. This slave can NOT be disabled. Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
41
PERI_GR3_CLOCK_CTL
2.1.4 PERI_GR3_CLOCK_CTL
Address = 0x400100C0 Clock control Address: 0x400100C0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
INT8_DIV [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 8
Name INT8_DIV
Description
Specifies a group clock divider (from the peripheral clock "clk_peri" to the group clock "clk_group[3/4/5/...15]"). Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256].
Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to "0" when transitioning from DeepSleep to Active power mode. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
42
PERI_GR3_SL_CTL
2.1.5 PERI_GR3_SL_CTL
Address = 0x400100E0 Slave control Address: 0x400100E0 Retention: Retained
Bits SW Access HW Access
Name
7 None None
None
6
RW
R
ENABLED_6
5
RW
R
ENABLED_5
4
RW
R
ENABLED_4
3
RW
R
ENABLED_3
2
RW
R
ENABLED_2
1
RW
R
ENABLED_1
Bits SW Access HW Access
Name
15
14
13
None
None
None [15:13]
12
RW
R
ENABLED_12
11
RW
R
ENABLED_11
10
RW
R
ENABLED_10
9
RW
R
ENABLED_9
Bits
23
22
21
20
19
18
17
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
SW Access
None
HW Access
None
Name
None [31:24]
0 R R ENABLED_0 8 RW R ENABLED_8 16
24
Bits
Name
12
ENABLED_12
11
ENABLED_11
10
ENABLED_10
9
ENABLED_9
8
ENABLED_8
6
ENABLED_6
5
ENABLED_5
4
ENABLED_4
3
ENABLED_3
Description Default Value: 1 Default Value: 1 Default Value: 1 Default Value: 1 Default Value: 1 Default Value: 1 Default Value: 1 Default Value: 1 Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
43
PERI_GR3_SL_CTL
2.1.5
2
1
0
PERI_GR3_SL_CTL (continued)
ENABLED_2 ENABLED_1 ENABLED_0
Peripheral group, slave 2 enable. If the slave is disabled, its clock is gated off (constant "0") and its resets are activated.
Note: For peripheral group 0 (the peripheral interconnect, master interface MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled. Default Value: 1
Peripheral group, slave 1 enable. If the slave is disabled, its clock is gated off (constant "0") and its resets are activated.
Note: For peripheral group 0 (the peripheral interconnect MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled. Default Value: 1
Peripheral group, slave 0 enable. This field is for the peripheral group internal MMIO register slave (PPU structures) and is a constant '1'. This slave can NOT be disabled. Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
44
PERI_GR4_SL_CTL
2.1.6 PERI_GR4_SL_CTL
Address = 0x40010120 Slave control Address: 0x40010120 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:3]
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4
3
12
11
None
None
None [15:8]
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
2 RW R ENABLED_2
10
1 None None None
9
0 R R ENABLED_0
8
18
17
16
26
25
24
Bits
Name
2
ENABLED_2
0
ENABLED_0
Description
Peripheral group, slave 2 enable. If the slave is disabled, its clock is gated off (constant "0") and its resets are activated.
Note: For peripheral group 0 (the peripheral interconnect, master interface MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled. Default Value: 1
Peripheral group, slave 0 enable. This field is for the peripheral group internal MMIO register slave (PPU structures) and is a constant '1'. This slave can NOT be disabled. Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
45
PERI_GR6_SL_CTL
2.1.7 PERI_GR6_SL_CTL
Address = 0x400101A0 Slave control Address: 0x400101A0 Retention: Retained
Bits SW Access HW Access
Name
7
RW
R
ENABLED_7
6
RW
R
ENABLED_6
5
RW
R
ENABLED_5
4
RW
R
ENABLED_4
Bits
15
14
13
12
SW Access
None
HW Access
None
Name
None [15:10]
3 RW R ENABLED_3
11
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2 RW R ENABLED_2 10
18
26
1 RW R ENABLED_1
9 RW R ENABLED_9 17
25
0 R R ENABLED_0 8 RW R ENABLED_8 16
24
Bits
Name
9
ENABLED_9
8
ENABLED_8
7
ENABLED_7
6
ENABLED_6
5
ENABLED_5
4
ENABLED_4
3
ENABLED_3
2
ENABLED_2
Description Default Value: 1 Default Value: 1 Default Value: 1 Default Value: 1 Default Value: 1 Default Value: 1 Default Value: 1 Peripheral group, slave 2 enable. If the slave is disabled, its clock is gated off (constant "0") and its resets are activated.
Note: For peripheral group 0 (the peripheral interconnect, master interface MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled. Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
46
PERI_GR6_SL_CTL
2.1.7
1
0
PERI_GR6_SL_CTL (continued)
ENABLED_1 ENABLED_0
Peripheral group, slave 1 enable. If the slave is disabled, its clock is gated off (constant "0") and its resets are activated.
Note: For peripheral group 0 (the peripheral interconnect MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled. Default Value: 1
Peripheral group, slave 0 enable. This field is for the peripheral group internal MMIO register slave (PPU structures) and is a constant '1'. This slave can NOT be disabled. Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
47
PERI_GR10_SL_CTL
2.1.8 PERI_GR10_SL_CTL
Address = 0x400102A0 Slave control Address: 0x400102A0 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:3]
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4
3
12
11
None
None
None [15:8]
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
2 RW R ENABLED_2
10
1 RW R ENABLED_1
9
0 R R ENABLED_0
8
18
17
16
26
25
24
Bits
Name
2
ENABLED_2
1
ENABLED_1
0
ENABLED_0
Description
Peripheral group, slave 2 enable. If the slave is disabled, its clock is gated off (constant "0") and its resets are activated.
Note: For peripheral group 0 (the peripheral interconnect, master interface MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled. Default Value: 1
Peripheral group, slave 1 enable. If the slave is disabled, its clock is gated off (constant "0") and its resets are activated.
Note: For peripheral group 0 (the peripheral interconnect MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled. Default Value: 1
Peripheral group, slave 0 enable. This field is for the peripheral group internal MMIO register slave (PPU structures) and is a constant '1'. This slave can NOT be disabled. Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
48
PERI_DIV_CMD
2.1.9 PERI_DIV_CMD
Address = 0x40010400 Divider command register Address: 0x40010400 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
RW
HW Access
R
R
Name
TYPE_SEL [7:6]
DIV_SEL [5:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
RW
HW Access
R
R
Name
PA_TYPE_SEL [15:14]
PA_DIV_SEL [13:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
RW
None
HW Access
RW1C
RW1C
None
Name
ENABLE DISABLE
None [29:24]
Bits
Name
31
ENABLE
Description
Clock divider enable command (mutually exclusive with DISABLE). Typically, SW sets this field to '1' to enable a divider and HW sets this field to '0' to indicate that divider enabling has completed. When a divider is enabled, its integer and fractional (if present) counters are initialized to "0". If a divider is to be re-enabled using different integer and fractional divider values, the SW should follow these steps: 0: Disable the divider using the DIV_CMD.DISABLE field. 1: Configure the divider's DIV_XXX_CTL register. 2: Enable the divider using the DIV_CMD_ENABLE field.
The DIV_SEL and TYPE_SEL fields specify which divider is to be enabled. The enabled divider may be phase aligned to either "clk_peri" (typical usage) or to ANY enabled divider.
The PA_DIV_SEL and PA_TYPE_SEL fields specify the reference divider.
The HW sets the ENABLE field to '0' when the enabling is performed and the HW set the DIV_XXX_CTL.EN field of the divider to '1' when the enabling is performed. Note that enabling with phase alignment to a low frequency divider takes time. E.g. To align to a divider that generates a clock of "clk_peri"/n (with n being the integer divider value INT_DIV+1), up to n cycles may be required to perform alignment. Phase alignment to "clk_peri" takes affect immediately. SW can set this field to '0' during phase alignment to abort the enabling process. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
49
PERI_DIV_CMD
2.1.9
30
15 : 14 13 : 8 7 : 6 5 : 0
PERI_DIV_CMD (continued)
DISABLE PA_TYPE_SEL PA_DIV_SEL TYPE_SEL DIV_SEL
Clock divider disable command (mutually exclusive with ENABLE). SW sets this field to '1' and HW sets this field to '0'.
The DIV_SEL and TYPE_SEL fields specify which divider is to be disabled.
The HW sets the DISABLE field to '0' immediately and the HW sets the DIV_XXX_CTL.EN field of the divider to '0' immediately. Default Value: 0
Specifies the divider type of the divider to which phase alignment is performed for the clock enable command: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. Default Value: 3
(PA_TYPE_SEL, PA_DIV_SEL) specifies the divider to which phase alignment is performed for the clock enable command. Any enabled divider can be used as reference. This allows all dividers to be aligned with each other, even when they are enabled at different times.
If PA_DIV_SEL is "63" and PA_TYPE_SEL is "3", "clk_peri" is used as reference. Default Value: 63
Specifies the divider type of the divider on which the command is performed: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. Default Value: 3
(TYPE_SEL, DIV_SEL) specifies the divider on which the command (DISABLE/ENABLE) is performed.
If DIV_SEL is "63" and TYPE_SEL is "3" (default/reset value), no divider is specified and no clock signal(s) are generated. Default Value: 63
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
50
PERI_DIV_8_CTL0
2.1.10 PERI_DIV_8_CTL0
Address = 0x40010800 Divider control register (for 8.0 divider) Address: 0x40010800 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
R
HW Access
None
RW
Name
None [7:1]
EN
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
INT8_DIV [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 8
Name INT8_DIV
0
EN
Description
Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division.
For the generation of a divided clock, the integer division range is restricted to [2, 256].
For the generation of a 50/50% duty cycle digital divided clock, the integer division range is resticited to even numbers in the range [2, 256]. The generation of a 50/50 % duty cycle analog divided clock has no restrictions.
Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to "0" when transitioning from DeepSleep to Active power mode. Default Value: 0
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command.
Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
51
PERI_DIV_16_CTL0
2.1.11 PERI_DIV_16_CTL0
Address = 0x40010900 Divider control register (for 16.0 divider) Address: 0x40010900 Retention: Retained
Bits
7
6
5
4
3
2
SW Access
None
HW Access
None
Name
None [7:1]
Bits
15
14
13
12
11
10
SW Access
RW
HW Access
R
Name
INT16_DIV [15:8]
Bits
23
22
21
20
19
18
SW Access
RW
HW Access
R
Name
INT16_DIV [23:16]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
1
0
R
RW
EN
9
8
17
16
25
24
Bits 23 : 8
Name INT16_DIV
0
EN
Description
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division.
For the generation of a divided clock, the integer division range is restricted to [2, 65,536].
For the generation of a 50/50% duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50 % duty cycle analog divided clock has no restrictions.
Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to "0" when transitioning from DeepSleep to Active power mode. Default Value: 0
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command.
Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
52
PERI_DIV_16_5_CTL0
2.1.12 PERI_DIV_16_5_CTL0
Address = 0x40010A00 Divider control register (for 16.5 divider) Address: 0x40010A00 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
None
R
HW Access
R
None
RW
Name
FRAC5_DIV [7:3]
None [2:1]
EN
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
INT16_DIV [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
INT16_DIV [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 23 : 8
Name INT16_DIV
7 : 3
FRAC5_DIV
Description
Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/ 32] in 1/32 increments.
For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32].
For the generation of a 50/50% duty cycle divided clock, the division range is restricted to [2, 65,536].
Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to "0" when transitioning from DeepSleep to Active power mode. Default Value: 0
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 "clk_peri" cycle longer than other clock periods.
Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to "0" when transitioning from DeepSleep to Active power mode. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
53
PERI_DIV_16_5_CTL0
2.1.12
0
PERI_DIV_16_5_CTL0 (continued)
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field
to '0' as a result on a DISABLE command.
Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
54
PERI_DIV_24_5_CTL0
2.1.13 PERI_DIV_24_5_CTL0
Address = 0x40010B00 Divider control register (for 24.5 divider) Address: 0x40010B00 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
None
R
HW Access
R
None
RW
Name
FRAC5_DIV [7:3]
None [2:1]
EN
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
INT24_DIV [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
INT24_DIV [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
INT24_DIV [31:24]
Bits 31 : 8
Name INT24_DIV
7 : 3
FRAC5_DIV
Description
Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments.
For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/ 32].
For the generation of a 50/50% duty cycle divided clock, the division range is restricted to [2, 16,777,216].
Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to "0" when transitioning from DeepSleep to Active power mode. Default Value: 0
Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 "clk_peri" cycle longer than other clock periods.
Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to "0" when transitioning from DeepSleep to Active power mode. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
55
PERI_DIV_24_5_CTL0
2.1.13
0
PERI_DIV_24_5_CTL0 (continued)
EN
Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field
to '0' as a result on a DISABLE command.
Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
56
PERI_CLOCK_CTL0
2.1.14 PERI_CLOCK_CTL0
Address = 0x40010C00 Clock control register Address: 0x40010C00 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
None
RW
HW Access
R
None
R
Name
TYPE_SEL [7:6]
None [5:4]
DIV_SEL [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 6
Name TYPE_SEL
3 : 0
DIV_SEL
Description
Specifies divider type: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers. Default Value: 3
Specifies one of the dividers of the divider type specified by TYPE_SEL.
If DIV_SEL is "63" and TYPE_SEL is "3" (default/reset value), no divider is specified and no clock control signal(s) are generated.
When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one "clk_peri" cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is "63" and TYPE_SEL is "3") for a transition time that is larger than the smaller of the two divider periods. Default Value: 15
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
57
PERI_TR_CMD
2.1.15 PERI_TR_CMD
Address = 0x40011000 Trigger command register Address: 0x40011000 Retention: Not Retained
Bits
7
6
5
SW Access
HW Access
Name
Bits
15
SW Access
HW Access
Name
14
13
None
None
None [15:12]
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
RW
RW
HW Access
RW1C
R
Name
ACTIVATE OUT_SEL
4
3
2
1
0
RW
R
TR_SEL [7:0]
12
11
10
9
8
RW
R
GROUP_SEL [11:8]
20
19
18
17
16
RW
RW
COUNT [23:16]
28
27
26
25
24
None
None
None [29:24]
Bits
Name
31
ACTIVATE
30
OUT_SEL
23 : 16
COUNT
Description
SW sets this field to '1' by to activate (set to '1') a trigger as identified by TR_SEL and OUT_SEL for COUNT cycles. HW sets this field to '0' when the cycle counter is decremented to "0". Note: a COUNT value of 255 is a special case and trigger activation is under direct control of the ACTIVATE field (the counter is not decremented). Default Value: 0
Specifies whether trigger activation is for a specific input or ouput trigger of the trigger multiplexer. Activation of a specific input trigger, will result in activation of all output triggers that have the specific input trigger selected through their TR_OUT_CTL.TR_SEL field. Activation of a specific output trigger, will result in activation of the specified TR_SEL output trigger only. '0': TR_SEL selection and trigger activation is for an input trigger to the trigger multiplexer. '1': TR_SEL selection and trigger activation is for an output trigger from the trigger multiplexer. Default Value: 0
Amount of "clk_peri" cycles a specific trigger is activated. During activation (ACTIVATE is '1'), HW decrements this field to "0" using a cycle counter. During activation, SW should not modify this register field. A value of 255 is a special case: HW does NOT decrement this field to "0" and trigger activation is under direct control of ACTIVATE when ACTIVATE is '1' the trigger is activated and when ACTIVATE is '0' the trigger is deactivated. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
58
PERI_TR_CMD
2.1.15
11 : 8 7 : 0
PERI_TR_CMD (continued)
GROUP_SEL TR_SEL
Specifies the trigger group. Default Value: 0
Specifies the activated trigger when ACTIVATE is '1'. OUT_SEL specifies whether the activated trigger is an input trigger or output trigger to the trigger multiplexer. During activation (ACTIVATE is '1'), SW should not modify this register field. If the specified trigger is not present, the trigger activation has no effect. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
59
PERI_TR_GR0_TR_OUT_CTL0
2.1.16 PERI_TR_GR0_TR_OUT_CTL0
Address = 0x40012000 Trigger control register Address: 0x40012000 Retention: Retained
Bits
7
6
5
4
3
2
SW Access
None
RW
HW Access
None
R
Name
None [7:6]
TR_SEL [5:0]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:10]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
1
0
9 RW R TR_EDGE
17
8 RW R TR_INV
16
25
24
Bits
Name
9
TR_EDGE
8
TR_INV
5 : 0
TR_SEL
Description
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. Default Value: 0
Specifies if the output trigger is inverted. Default Value: 0
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
60
PERI_TR_GR2_TR_OUT_CTL0
2.1.17 PERI_TR_GR2_TR_OUT_CTL0
Address = 0x40012400 Trigger control register Address: 0x40012400 Retention: Retained
Bits
7
6
5
4
3
2
SW Access
None
RW
HW Access
None
R
Name
None [7:6]
TR_SEL [5:0]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:10]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
1
0
9 RW R TR_EDGE
17
8 RW R TR_INV
16
25
24
Bits
Name
9
TR_EDGE
8
TR_INV
5 : 0
TR_SEL
Description
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. Default Value: 0
Specifies if the output trigger is inverted. Default Value: 0
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
61
PERI_TR_GR4_TR_OUT_CTL0
2.1.18 PERI_TR_GR4_TR_OUT_CTL0
Address = 0x40012800 Trigger control register Address: 0x40012800 Retention: Retained
Bits
7
6
5
4
3
2
SW Access
None
RW
HW Access
None
R
Name
None [7:6]
TR_SEL [5:0]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:10]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
1
0
9 RW R TR_EDGE
17
8 RW R TR_INV
16
25
24
Bits
Name
9
TR_EDGE
8
TR_INV
5 : 0
TR_SEL
Description
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. Default Value: 0
Specifies if the output trigger is inverted. Default Value: 0
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
62
PERI_TR_GR6_TR_OUT_CTL0
2.1.19 PERI_TR_GR6_TR_OUT_CTL0
Address = 0x40012C00 Trigger control register Address: 0x40012C00 Retention: Retained
Bits
7
6
5
4
3
2
SW Access
None
RW
HW Access
None
R
Name
None [7:6]
TR_SEL [5:0]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:10]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
1
0
9 RW R TR_EDGE
17
8 RW R TR_INV
16
25
24
Bits
Name
9
TR_EDGE
8
TR_INV
5 : 0
TR_SEL
Description
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. Default Value: 0
Specifies if the output trigger is inverted. Default Value: 0
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
63
PERI_TR_GR9_TR_OUT_CTL0
2.1.20 PERI_TR_GR9_TR_OUT_CTL0
Address = 0x40013200 Trigger control register Address: 0x40013200 Retention: Retained
Bits
7
6
5
4
3
2
SW Access
None
RW
HW Access
None
R
Name
None [7:6]
TR_SEL [5:0]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:10]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
1
0
9 RW R TR_EDGE
17
8 RW R TR_INV
16
25
24
Bits
Name
9
TR_EDGE
8
TR_INV
5 : 0
TR_SEL
Description
Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive trigger. '0': level sensitive. '1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock. Default Value: 0
Specifies if the output trigger is inverted. Default Value: 0
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
64
PERI_TR_GR11_TR_OUT_CTL0
2.1.21 PERI_TR_GR11_TR_OUT_CTL0
Address = 0x40013600 Trigger control register Address: 0x40013600 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None
TR_SEL [6:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 6 : 0
Name TR_SEL
Description
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
65
PERI_TR_GR12_TR_OUT_CTL0
2.1.22 PERI_TR_GR12_TR_OUT_CTL0
Address = 0x40013800 Trigger control register Address: 0x40013800 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:5]
TR_SEL [4:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 4 : 0
Name TR_SEL
Description
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
66
PERI_TR_GR13_TR_OUT_CTL0
2.1.23 PERI_TR_GR13_TR_OUT_CTL0
Address = 0x40013A00 Trigger control register Address: 0x40013A00 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:6]
TR_SEL [5:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 5 : 0
Name TR_SEL
Description
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
67
PERI_TR_GR14_TR_OUT_CTL0
2.1.24 PERI_TR_GR14_TR_OUT_CTL0
Address = 0x40013C00 Trigger control register Address: 0x40013C00 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:6]
TR_SEL [5:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 5 : 0
Name TR_SEL
Description
Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
68
PERI_PPU_PR0_ADDR0
2.1.25 PERI_PPU_PR0_ADDR0
Address = 0x40014000 PPU region address 0 (slave structure) Address: 0x40014000 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
Name ADDR24
Description
This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by PPU_REGION_ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is "15") is 64 KByte aligned, and ADDR24[7:0] are ignored. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
69
PERI_PPU_PR0_ADDR0
2.1.25
7 : 0
PERI_PPU_PR0_ADDR0 (continued)
SUBREGION_DISABLE
This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. E.g., a 64 KByte address region (REGION_SIZE is "15") has eight 8 KByte subregions. The access control as defined by PPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
70
PERI_PPU_PR0_ATT0
2.1.26 PERI_PPU_PR0_ATT0
Address = 0x40014004 PPU region attributes 0 (slave structure) Address: 0x40014004 Retention: Retained
Bits
7
6
5
4
3
2
1
SW Access
None
RW
R
RW
RW
R
RW
HW Access
None
R
R
R
R
R
R
Name
None
NS
PX
PW
PR
UX
UW
Bits
15
14
13
12
11
10
9
SW Access
RW
HW Access
R
Name
PC_MASK_15_TO_1 [15:9]
Bits SW Access HW Access
Name
Bits SW Access HW Access
Name
23
22
21
31 RW R ENABLED
30 RW R PC_MATCH
29 None None None
20
19
18
17
None
None
None [23:16]
28
27
26
25
RW
R
REGION_SIZE [28:24]
0 RW R UR
8 R R PC_MASK_ 0 16
24
Bits
Name
31
ENABLED
30
PC_MATCH
Description
Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled.
Note: a disabled address region performs logic gating to reduce dynamic power consumption. Default Value: 0
This field specifies if the PC field participates in the "matching" process or the "access evaluation" process: '0': PC field participates in "access evaluation". '1': PC field participates in "matching".
Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
71
PERI_PPU_PR0_ATT0
2.1.26
28 : 24
15 : 9 8 6 5 4 3 2
PERI_PPU_PR0_ATT0 (continued)
REGION_SIZE
PC_MASK_15_TO_1 PC_MASK_0 NS PX PW PR UX
This field specifies the region size: "0"-"6": Undefined. "7": 256 B region "8": 512 B region "9": 1 KB region "10": 2 KB region "11": 4 KB region "12": 8 KB region "13": 16 KB region "14": 32 KB region "15": 64 KB region "16": 128 KB region "17": 256 KB region "18": 512 KB region "19": 1 MB region "20": 2 MB region "21": 4 MB region "22": 8 MB region "23": 16 MB region "24": 32 MB region "25": 64 MB region "26": 128 MB region "27": 256 MB region "28": 512 MB region "29": 1 GB region "30": 2 GB region "31": 4 GB region Default Value: Undefined
This field specifies protection context identifier based access control. Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed. Default Value: Undefined
This field specifies protection context identifier based access control for protection context "0". Default Value: 1
Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). Default Value: Undefined
Privileged execute enable: '0': Disabled (privileged, execute accesses are NOT allowed). '1': Enabled (privileged, execute accesses are allowed). Default Value: 1
Privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed). Default Value: Undefined
Privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed). Default Value: Undefined
User execute enable: '0': Disabled (user, execute accesses are NOT allowed). '1': Enabled (user, execute accesses are allowed). Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
72
PERI_PPU_PR0_ATT0
2.1.26
1
0
PERI_PPU_PR0_ATT0 (continued)
UW
User write enable:
'0': Disabled (user, write accesses are NOT allowed).
'1': Enabled (user, write accesses are allowed).
Default Value: Undefined
UR
User read enable:
'0': Disabled (user, read accesses are NOT allowed).
'1': Enabled (user, read accesses are allowed).
Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
73
PERI_PPU_PR0_ADDR1
2.1.27 PERI_PPU_PR0_ADDR1
Address = 0x40014020 PPU region address 1 (master structure) Address: 0x40014020 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4194624 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 252
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
74
PERI_PPU_PR0_ATT1
2.1.28 PERI_PPU_PR0_ATT1
Address = 0x40014024 PPU region attributes 1 (master structure) Address: 0x40014024 Retention: Retained
Bits
7
6
5
4
3
2
1
SW Access
None
RW
R
RW
R
R
RW
HW Access
None
R
R
R
R
R
R
Name
None
NS
PX
PW
PR
UX
UW
Bits
15
14
13
12
11
10
9
SW Access
RW
HW Access
R
Name
PC_MASK_15_TO_1 [15:9]
Bits SW Access HW Access
Name
Bits SW Access HW Access
Name
23
22
21
31 RW R ENABLED
30 RW R PC_MATCH
29 None None None
20
19
18
17
None
None
None [23:16]
28
27
26
25
R
R
REGION_SIZE [28:24]
0 R R UR 8 R R PC_MASK_ 0 16
24
Bits 31 30 28 : 24
Name ENABLED PC_MATCH REGION_SIZE
15 : 9 8 6
PC_MASK_15_TO_1 PC_MASK_0 NS
Description
See corresponding field for PPU structure with programmable address. Default Value: 0
See corresponding field for PPU structure with programmable address. Default Value: Undefined
See corresponding field for PPU structure with programmable address.
"7": 256 B region Default Value: 7
See corresponding field for PPU structure with programmable address. Default Value: Undefined
See corresponding field for PPU structure with programmable address. Default Value: 1
See corresponding field for PPU structure with programmable address. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
75
PERI_PPU_PR0_ATT1
2.1.28
5
4 3
2
1 0
PERI_PPU_PR0_ATT1 (continued)
PX
See corresponding field for PPU structure with programmable address.
Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed. Default Value: 0
PW
See corresponding field for PPU structure with programmable address.
Default Value: Undefined
PR
See corresponding field for PPU structure with programmable address.
Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed. Default Value: 1
UX
See corresponding field for PPU structure with programmable address.
Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed. Default Value: 0
UW
See corresponding field for PPU structure with programmable address.
Default Value: Undefined
UR
See corresponding field for PPU structure with programmable address.
Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed. Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
76
PERI_PPU_PR1_ADDR1
2.1.29 PERI_PPU_PR1_ADDR1
Address = 0x40014060 PPU region address 1 (master structure) Address: 0x40014060 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4194624 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 243
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
77
PERI_PPU_PR2_ADDR1
2.1.30 PERI_PPU_PR2_ADDR1
Address = 0x400140A0 PPU region address 1 (master structure) Address: 0x400140A0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4194624 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 207
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
78
PERI_PPU_PR3_ADDR1
2.1.31 PERI_PPU_PR3_ADDR1
Address = 0x400140E0 PPU region address 1 (master structure) Address: 0x400140E0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4194624 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 63
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
79
PERI_PPU_PR4_ADDR1
2.1.32 PERI_PPU_PR4_ADDR1
Address = 0x40014120 PPU region address 1 (master structure) Address: 0x40014120 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4194625 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 252
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
80
PERI_PPU_PR5_ADDR1
2.1.33 PERI_PPU_PR5_ADDR1
Address = 0x40014160 PPU region address 1 (master structure) Address: 0x40014160 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4194625 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 243
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
81
PERI_PPU_PR6_ADDR1
2.1.34 PERI_PPU_PR6_ADDR1
Address = 0x400141A0 PPU region address 1 (master structure) Address: 0x400141A0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4194625 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 207
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
82
PERI_PPU_PR7_ADDR1
2.1.35 PERI_PPU_PR7_ADDR1
Address = 0x400141E0 PPU region address 1 (master structure) Address: 0x400141E0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4194625 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 63
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
83
PERI_PPU_PR8_ADDR1
2.1.36 PERI_PPU_PR8_ADDR1
Address = 0x40014220 PPU region address 1 (master structure) Address: 0x40014220 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4194626 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 252
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
84
PERI_PPU_PR9_ADDR1
2.1.37 PERI_PPU_PR9_ADDR1
Address = 0x40014260 PPU region address 1 (master structure) Address: 0x40014260 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4194626 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 243
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
85
PERI_PPU_PR10_ADDR1
2.1.38 PERI_PPU_PR10_ADDR1
Address = 0x400142A0 PPU region address 1 (master structure) Address: 0x400142A0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4194626 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 207
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
86
PERI_PPU_PR11_ADDR1
2.1.39 PERI_PPU_PR11_ADDR1
Address = 0x400142E0 PPU region address 1 (master structure) Address: 0x400142E0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4194626 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 63
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
87
PERI_PPU_PR12_ADDR1
2.1.40 PERI_PPU_PR12_ADDR1
Address = 0x40014320 PPU region address 1 (master structure) Address: 0x40014320 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4194627 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 252
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
88
PERI_PPU_PR13_ADDR1
2.1.41 PERI_PPU_PR13_ADDR1
Address = 0x40014360 PPU region address 1 (master structure) Address: 0x40014360 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4194627 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 243
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
89
PERI_PPU_PR14_ADDR1
2.1.42 PERI_PPU_PR14_ADDR1
Address = 0x400143A0 PPU region address 1 (master structure) Address: 0x400143A0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4194627 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 207
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
90
PERI_PPU_PR15_ADDR1
2.1.43 PERI_PPU_PR15_ADDR1
Address = 0x400143E0 PPU region address 1 (master structure) Address: 0x400143E0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4194627 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 63
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
91
PERI_PPU_GR0_ADDR0
2.1.44 PERI_PPU_GR0_ADDR0
Address = 0x40015000 PPU region address 0 (slave structure) Address: 0x40015000 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4194304 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
92
PERI_PPU_GR0_ATT0
2.1.45 PERI_PPU_GR0_ATT0
Address = 0x40015004 PPU region attributes 0 (slave structure) Address: 0x40015004 Retention: Retained
Bits
7
6
5
4
3
2
1
SW Access
None
RW
R
RW
RW
R
RW
HW Access
None
R
R
R
R
R
R
Name
None
NS
PX
PW
PR
UX
UW
Bits
15
14
13
12
11
10
9
SW Access
RW
HW Access
R
Name
PC_MASK_15_TO_1 [15:9]
Bits SW Access HW Access
Name
Bits SW Access HW Access
Name
23
22
21
31 RW R ENABLED
30 RW R PC_MATCH
29 None None None
20
19
18
17
None
None
None [23:16]
28
27
26
25
R
R
REGION_SIZE [28:24]
0 RW R UR
8 R R PC_MASK_ 0 16
24
Bits 31 30 28 : 24
Name ENABLED PC_MATCH REGION_SIZE
15 : 9 8 6
PC_MASK_15_TO_1 PC_MASK_0 NS
Description
See corresponding field for PPU structure with programmable address. Default Value: 0
See corresponding field for PPU structure with programmable address. Default Value: Undefined
See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 19
See corresponding field for PPU structure with programmable address. Default Value: Undefined
See corresponding field for PPU structure with programmable address. Default Value: 1
See corresponding field for PPU structure with programmable address. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
93
PERI_PPU_GR0_ATT0
2.1.45
5
4 3 2
1 0
PERI_PPU_GR0_ATT0 (continued)
PX
See corresponding field for PPU structure with programmable address.
Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed. Default Value: 1
PW
See corresponding field for PPU structure with programmable address.
Default Value: Undefined
PR
See corresponding field for PPU structure with programmable address.
Default Value: Undefined
UX
See corresponding field for PPU structure with programmable address.
Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed. Default Value: 1
UW
See corresponding field for PPU structure with programmable address.
Default Value: Undefined
UR
See corresponding field for PPU structure with programmable address.
Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
94
PERI_PPU_GR0_ADDR1
2.1.46 PERI_PPU_GR0_ADDR1
Address = 0x40015020 PPU region address 1 (master structure) Address: 0x40015020 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4194640 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 252
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
95
PERI_PPU_GR0_ATT1
2.1.47 PERI_PPU_GR0_ATT1
Address = 0x40015024 PPU region attributes 1 (master structure) Address: 0x40015024 Retention: Retained
Bits
7
6
5
4
3
2
1
SW Access
None
RW
R
RW
R
R
RW
HW Access
None
R
R
R
R
R
R
Name
None
NS
PX
PW
PR
UX
UW
Bits
15
14
13
12
11
10
9
SW Access
RW
HW Access
R
Name
PC_MASK_15_TO_1 [15:9]
Bits SW Access HW Access
Name
Bits SW Access HW Access
Name
23
22
21
31 RW R ENABLED
30 RW R PC_MATCH
29 None None None
20
19
18
17
None
None
None [23:16]
28
27
26
25
R
R
REGION_SIZE [28:24]
0 R R UR 8 R R PC_MASK_ 0 16
24
Bits 31 30 28 : 24
Name ENABLED PC_MATCH REGION_SIZE
15 : 9 8 6
PC_MASK_15_TO_1 PC_MASK_0 NS
Description
See corresponding field for PPU structure with programmable address. Default Value: 0
See corresponding field for PPU structure with programmable address. Default Value: Undefined
See corresponding field for PPU structure with programmable address.
"7": 256 B region Default Value: 7
See corresponding field for PPU structure with programmable address. Default Value: Undefined
See corresponding field for PPU structure with programmable address. Default Value: 1
See corresponding field for PPU structure with programmable address. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
96
PERI_PPU_GR0_ATT1
2.1.47
5
4 3
2
1 0
PERI_PPU_GR0_ATT1 (continued)
PX
See corresponding field for PPU structure with programmable address.
Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed. Default Value: 0
PW
See corresponding field for PPU structure with programmable address.
Default Value: Undefined
PR
See corresponding field for PPU structure with programmable address.
Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed. Default Value: 1
UX
See corresponding field for PPU structure with programmable address.
Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed. Default Value: 0
UW
See corresponding field for PPU structure with programmable address.
Default Value: Undefined
UR
See corresponding field for PPU structure with programmable address.
Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed. Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
97
PERI_PPU_GR1_ADDR0
2.1.48 PERI_PPU_GR1_ADDR0
Address = 0x40015040 PPU region address 0 (slave structure) Address: 0x40015040 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4198400 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
98
PERI_PPU_GR1_ADDR1
2.1.49 PERI_PPU_GR1_ADDR1
Address = 0x40015060 PPU region address 1 (master structure) Address: 0x40015060 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4194640 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 243
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
99
PERI_PPU_GR2_ADDR0
2.1.50 PERI_PPU_GR2_ADDR0
Address = 0x40015080 PPU region address 0 (slave structure) Address: 0x40015080 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4202496 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
100
PERI_PPU_GR2_ADDR1
2.1.51 PERI_PPU_GR2_ADDR1
Address = 0x400150A0 PPU region address 1 (master structure) Address: 0x400150A0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4194640 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 207
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
101
PERI_PPU_GR3_ADDR0
2.1.52 PERI_PPU_GR3_ADDR0
Address = 0x400150C0 PPU region address 0 (slave structure) Address: 0x400150C0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4206592 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
102
PERI_PPU_GR3_ADDR1
2.1.53 PERI_PPU_GR3_ADDR1
Address = 0x400150E0 PPU region address 1 (master structure) Address: 0x400150E0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4194640 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 63
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
103
PERI_PPU_GR4_ADDR0
2.1.54 PERI_PPU_GR4_ADDR0
Address = 0x40015100 PPU region address 0 (slave structure) Address: 0x40015100 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4210688 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
104
PERI_PPU_GR4_ADDR1
2.1.55 PERI_PPU_GR4_ADDR1
Address = 0x40015120 PPU region address 1 (master structure) Address: 0x40015120 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4194641 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 252
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
105
PERI_PPU_GR6_ADDR0
2.1.56 PERI_PPU_GR6_ADDR0
Address = 0x40015180 PPU region address 0 (slave structure) Address: 0x40015180 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4218880 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
106
PERI_PPU_GR6_ADDR1
2.1.57 PERI_PPU_GR6_ADDR1
Address = 0x400151A0 PPU region address 1 (master structure) Address: 0x400151A0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4194641 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 207
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
107
PERI_PPU_GR9_ADDR0
2.1.58 PERI_PPU_GR9_ADDR0
Address = 0x40015240 PPU region address 0 (slave structure) Address: 0x40015240 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4259840 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
108
PERI_PPU_GR9_ATT0
2.1.59 PERI_PPU_GR9_ATT0
Address = 0x40015244 PPU region attributes 0 (slave structure) Address: 0x40015244 Retention: Retained
Bits
7
6
5
4
3
2
1
SW Access
None
RW
R
RW
RW
R
RW
HW Access
None
R
R
R
R
R
R
Name
None
NS
PX
PW
PR
UX
UW
Bits
15
14
13
12
11
10
9
SW Access
RW
HW Access
R
Name
PC_MASK_15_TO_1 [15:9]
Bits SW Access HW Access
Name
Bits SW Access HW Access
Name
23
22
21
31 RW R ENABLED
30 RW R PC_MATCH
29 None None None
20
19
18
17
None
None
None [23:16]
28
27
26
25
R
R
REGION_SIZE [28:24]
0 RW R UR
8 R R PC_MASK_ 0 16
24
Bits 31 30 28 : 24
Name ENABLED PC_MATCH REGION_SIZE
15 : 9 8 6
PC_MASK_15_TO_1 PC_MASK_0 NS
Description
See corresponding field for PPU structure with programmable address. Default Value: 0
See corresponding field for PPU structure with programmable address. Default Value: Undefined
See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 23
See corresponding field for PPU structure with programmable address. Default Value: Undefined
See corresponding field for PPU structure with programmable address. Default Value: 1
See corresponding field for PPU structure with programmable address. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
109
PERI_PPU_GR9_ATT0
2.1.59
5
4 3 2
1 0
PERI_PPU_GR9_ATT0 (continued)
PX
See corresponding field for PPU structure with programmable address.
Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed. Default Value: 1
PW
See corresponding field for PPU structure with programmable address.
Default Value: Undefined
PR
See corresponding field for PPU structure with programmable address.
Default Value: Undefined
UX
See corresponding field for PPU structure with programmable address.
Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed. Default Value: 1
UW
See corresponding field for PPU structure with programmable address.
Default Value: Undefined
UR
See corresponding field for PPU structure with programmable address.
Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
110
PERI_PPU_GR9_ADDR1
2.1.60 PERI_PPU_GR9_ADDR1
Address = 0x40015260 PPU region address 1 (master structure) Address: 0x40015260 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4194642 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 243
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
111
PERI_PPU_GR10_ADDR0
2.1.61 PERI_PPU_GR10_ADDR0
Address = 0x40015280 PPU region address 0 (slave structure) Address: 0x40015280 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4366336 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
112
PERI_PPU_GR10_ADDR1
2.1.62 PERI_PPU_GR10_ADDR1
Address = 0x400152A0 PPU region address 1 (master structure) Address: 0x400152A0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4194642 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 207
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
113
PERI_GR1_PPU_SL0_ADDR0
2.1.63 PERI_GR1_PPU_SL0_ADDR0
Address = 0x40100000 PPU region address 0 (slave structure) Address: 0x40100000 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4198400 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
114
PERI_GR1_PPU_SL0_ATT0
2.1.64 PERI_GR1_PPU_SL0_ATT0
Address = 0x40100004 PPU region attributes 0 (slave structure) Address: 0x40100004 Retention: Retained
Bits
7
6
5
4
3
2
1
SW Access
None
RW
R
RW
RW
R
RW
HW Access
None
R
R
R
R
R
R
Name
None
NS
PX
PW
PR
UX
UW
Bits
15
14
13
12
11
10
9
SW Access
RW
HW Access
R
Name
PC_MASK_15_TO_1 [15:9]
Bits SW Access HW Access
Name
Bits SW Access HW Access
Name
23
22
21
31 RW R ENABLED
30 RW R PC_MATCH
29 None None None
20
19
18
17
None
None
None [23:16]
28
27
26
25
R
R
REGION_SIZE [28:24]
0 RW R UR
8 R R PC_MASK_ 0 16
24
Bits 31 30 28 : 24
Name ENABLED PC_MATCH REGION_SIZE
15 : 9 8 6
PC_MASK_15_TO_1 PC_MASK_0 NS
Description
See corresponding field for PPU structure with programmable address. Default Value: 0
See corresponding field for PPU structure with programmable address. Default Value: Undefined
See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 15
See corresponding field for PPU structure with programmable address. Default Value: Undefined
See corresponding field for PPU structure with programmable address. Default Value: 1
See corresponding field for PPU structure with programmable address. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
115
PERI_GR1_PPU_SL0_ATT0
2.1.64
5
4 3 2
1 0
PERI_GR1_PPU_SL0_ATT0 (continued)
PX
See corresponding field for PPU structure with programmable address.
Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed. Default Value: 1
PW
See corresponding field for PPU structure with programmable address.
Default Value: Undefined
PR
See corresponding field for PPU structure with programmable address.
Default Value: Undefined
UX
See corresponding field for PPU structure with programmable address.
Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed. Default Value: 1
UW
See corresponding field for PPU structure with programmable address.
Default Value: Undefined
UR
See corresponding field for PPU structure with programmable address.
Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
116
PERI_GR1_PPU_SL0_ADDR1
2.1.65 PERI_GR1_PPU_SL0_ADDR1
Address = 0x40100020 PPU region address 1 (master structure) Address: 0x40100020 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4198400 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 252
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
117
PERI_GR1_PPU_SL0_ATT1
2.1.66 PERI_GR1_PPU_SL0_ATT1
Address = 0x40100024 PPU region attributes 1 (master structure) Address: 0x40100024 Retention: Retained
Bits
7
6
5
4
3
2
1
SW Access
None
RW
R
RW
R
R
RW
HW Access
None
R
R
R
R
R
R
Name
None
NS
PX
PW
PR
UX
UW
Bits
15
14
13
12
11
10
9
SW Access
RW
HW Access
R
Name
PC_MASK_15_TO_1 [15:9]
Bits SW Access HW Access
Name
Bits SW Access HW Access
Name
23
22
21
31 RW R ENABLED
30 RW R PC_MATCH
29 None None None
20
19
18
17
None
None
None [23:16]
28
27
26
25
R
R
REGION_SIZE [28:24]
0 R R UR 8 R R PC_MASK_ 0 16
24
Bits 31 30 28 : 24
Name ENABLED PC_MATCH REGION_SIZE
15 : 9 8 6
PC_MASK_15_TO_1 PC_MASK_0 NS
Description
See corresponding field for PPU structure with programmable address. Default Value: 0
See corresponding field for PPU structure with programmable address. Default Value: Undefined
See corresponding field for PPU structure with programmable address.
"7": 256 B region Default Value: 7
See corresponding field for PPU structure with programmable address. Default Value: Undefined
See corresponding field for PPU structure with programmable address. Default Value: 1
See corresponding field for PPU structure with programmable address. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
118
PERI_GR1_PPU_SL0_ATT1
2.1.66
5
4 3
2
1 0
PERI_GR1_PPU_SL0_ATT1 (continued)
PX
See corresponding field for PPU structure with programmable address.
Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed. Default Value: 0
PW
See corresponding field for PPU structure with programmable address.
Default Value: Undefined
PR
See corresponding field for PPU structure with programmable address.
Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed. Default Value: 1
UX
See corresponding field for PPU structure with programmable address.
Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed. Default Value: 0
UW
See corresponding field for PPU structure with programmable address.
Default Value: Undefined
UR
See corresponding field for PPU structure with programmable address.
Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed. Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
119
PERI_GR1_PPU_SL1_ADDR0
2.1.67 PERI_GR1_PPU_SL1_ADDR0
Address = 0x40100040 PPU region address 0 (slave structure) Address: 0x40100040 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4198656 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
120
PERI_GR1_PPU_SL1_ADDR1
2.1.68 PERI_GR1_PPU_SL1_ADDR1
Address = 0x40100060 PPU region address 1 (master structure) Address: 0x40100060 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4198400 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 243
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
121
PERI_GR2_PPU_SL0_ADDR0
2.1.69 PERI_GR2_PPU_SL0_ADDR0
Address = 0x40200000 PPU region address 0 (slave structure) Address: 0x40200000 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4202496 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
122
PERI_GR2_PPU_SL1_ADDR0
2.1.70 PERI_GR2_PPU_SL1_ADDR0
Address = 0x40200040 PPU region address 0 (slave structure) Address: 0x40200040 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4202752 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
123
PERI_GR2_PPU_SL1_ADDR1
2.1.71 PERI_GR2_PPU_SL1_ADDR1
Address = 0x40200060 PPU region address 1 (master structure) Address: 0x40200060 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4202496 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 243
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
124
PERI_GR2_PPU_SL2_ADDR0
2.1.72 PERI_GR2_PPU_SL2_ADDR0
Address = 0x40200080 PPU region address 0 (slave structure) Address: 0x40200080 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4203008 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
125
PERI_GR2_PPU_SL2_ADDR1
2.1.73 PERI_GR2_PPU_SL2_ADDR1
Address = 0x402000A0 PPU region address 1 (master structure) Address: 0x402000A0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4202496 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 207
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
126
PERI_GR2_PPU_SL3_ADDR0
2.1.74 PERI_GR2_PPU_SL3_ADDR0
Address = 0x402000C0 PPU region address 0 (slave structure) Address: 0x402000C0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4203264 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
127
PERI_GR2_PPU_SL3_ADDR1
2.1.75 PERI_GR2_PPU_SL3_ADDR1
Address = 0x402000E0 PPU region address 1 (master structure) Address: 0x402000E0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4202496 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 63
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
128
PERI_GR2_PPU_SL4_ADDR0
2.1.76 PERI_GR2_PPU_SL4_ADDR0
Address = 0x40200100 PPU region address 0 (slave structure) Address: 0x40200100 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4203520 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
129
PERI_GR2_PPU_SL4_ADDR1
2.1.77 PERI_GR2_PPU_SL4_ADDR1
Address = 0x40200120 PPU region address 1 (master structure) Address: 0x40200120 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4202497 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 252
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
130
PERI_GR2_PPU_SL5_ADDR0
2.1.78 PERI_GR2_PPU_SL5_ADDR0
Address = 0x40200140 PPU region address 0 (slave structure) Address: 0x40200140 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4203776 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
131
PERI_GR2_PPU_SL5_ADDR1
2.1.79 PERI_GR2_PPU_SL5_ADDR1
Address = 0x40200160 PPU region address 1 (master structure) Address: 0x40200160 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4202497 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 243
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
132
PERI_GR2_PPU_SL6_ADDR0
2.1.80 PERI_GR2_PPU_SL6_ADDR0
Address = 0x40200180 PPU region address 0 (slave structure) Address: 0x40200180 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4204032 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
133
PERI_GR2_PPU_SL6_ADDR1
2.1.81 PERI_GR2_PPU_SL6_ADDR1
Address = 0x402001A0 PPU region address 1 (master structure) Address: 0x402001A0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4202497 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 207
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
134
PERI_GR2_PPU_SL7_ADDR0
2.1.82 PERI_GR2_PPU_SL7_ADDR0
Address = 0x402001C0 PPU region address 0 (slave structure) Address: 0x402001C0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4204288 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
135
PERI_GR2_PPU_SL7_ADDR1
2.1.83 PERI_GR2_PPU_SL7_ADDR1
Address = 0x402001E0 PPU region address 1 (master structure) Address: 0x402001E0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4202497 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 63
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
136
PERI_GR2_PPU_SL8_ADDR0
2.1.84 PERI_GR2_PPU_SL8_ADDR0
Address = 0x40200200 PPU region address 0 (slave structure) Address: 0x40200200 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4204544 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
137
PERI_GR2_PPU_SL8_ATT0
2.1.85 PERI_GR2_PPU_SL8_ATT0
Address = 0x40200204 PPU region attributes 0 (slave structure) Address: 0x40200204 Retention: Retained
Bits
7
6
5
4
3
2
1
SW Access
None
RW
R
RW
RW
R
RW
HW Access
None
R
R
R
R
R
R
Name
None
NS
PX
PW
PR
UX
UW
Bits
15
14
13
12
11
10
9
SW Access
RW
HW Access
R
Name
PC_MASK_15_TO_1 [15:9]
Bits SW Access HW Access
Name
Bits SW Access HW Access
Name
23
22
21
31 RW R ENABLED
30 RW R PC_MATCH
29 None None None
20
19
18
17
None
None
None [23:16]
28
27
26
25
R
R
REGION_SIZE [28:24]
0 RW R UR
8 R R PC_MASK_ 0 16
24
Bits 31 30 28 : 24
Name ENABLED PC_MATCH REGION_SIZE
15 : 9 8 6
PC_MASK_15_TO_1 PC_MASK_0 NS
Description
See corresponding field for PPU structure with programmable address. Default Value: 0
See corresponding field for PPU structure with programmable address. Default Value: Undefined
See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 11
See corresponding field for PPU structure with programmable address. Default Value: Undefined
See corresponding field for PPU structure with programmable address. Default Value: 1
See corresponding field for PPU structure with programmable address. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
138
PERI_GR2_PPU_SL8_ATT0
2.1.85
5
4 3 2
1 0
PERI_GR2_PPU_SL8_ATT0 (continued)
PX
See corresponding field for PPU structure with programmable address.
Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed. Default Value: 1
PW
See corresponding field for PPU structure with programmable address.
Default Value: Undefined
PR
See corresponding field for PPU structure with programmable address.
Default Value: Undefined
UX
See corresponding field for PPU structure with programmable address.
Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed. Default Value: 1
UW
See corresponding field for PPU structure with programmable address.
Default Value: Undefined
UR
See corresponding field for PPU structure with programmable address.
Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
139
PERI_GR2_PPU_SL8_ADDR1
2.1.86 PERI_GR2_PPU_SL8_ADDR1
Address = 0x40200220 PPU region address 1 (master structure) Address: 0x40200220 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4202498 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 252
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
140
PERI_GR2_PPU_SL9_ADDR1
2.1.87 PERI_GR2_PPU_SL9_ADDR1
Address = 0x40200260 PPU region address 1 (master structure) Address: 0x40200260 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4202498 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 243
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
141
PERI_GR2_PPU_SL12_ADDR0
2.1.88 PERI_GR2_PPU_SL12_ADDR0
Address = 0x40200300 PPU region address 0 (slave structure) Address: 0x40200300 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4205568 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
142
PERI_GR2_PPU_SL12_ADDR1
2.1.89 PERI_GR2_PPU_SL12_ADDR1
Address = 0x40200320 PPU region address 1 (master structure) Address: 0x40200320 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4202499 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 252
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
143
PERI_GR2_PPU_SL13_ADDR0
2.1.90 PERI_GR2_PPU_SL13_ADDR0
Address = 0x40200340 PPU region address 0 (slave structure) Address: 0x40200340 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4205824 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
144
PERI_GR2_PPU_SL13_ADDR1
2.1.91 PERI_GR2_PPU_SL13_ADDR1
Address = 0x40200360 PPU region address 1 (master structure) Address: 0x40200360 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4202499 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 243
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
145
PERI_GR2_PPU_RG0_ADDR0
2.1.92 PERI_GR2_PPU_RG0_ADDR0
Address = 0x40201000 PPU region address 0 (slave structure) Address: 0x40201000 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4203264 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 254
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
146
PERI_GR2_PPU_RG0_ATT0
2.1.93 PERI_GR2_PPU_RG0_ATT0
Address = 0x40201004 PPU region attributes 0 (slave structure) Address: 0x40201004 Retention: Retained
Bits
7
6
5
4
3
2
1
SW Access
None
RW
R
RW
RW
R
RW
HW Access
None
R
R
R
R
R
R
Name
None
NS
PX
PW
PR
UX
UW
Bits
15
14
13
12
11
10
9
SW Access
RW
HW Access
R
Name
PC_MASK_15_TO_1 [15:9]
Bits SW Access HW Access
Name
Bits SW Access HW Access
Name
23
22
21
31 RW R ENABLED
30 RW R PC_MATCH
29 None None None
20
19
18
17
None
None
None [23:16]
28
27
26
25
R
R
REGION_SIZE [28:24]
0 RW R UR
8 R R PC_MASK_ 0 16
24
Bits 31 30 28 : 24
Name ENABLED PC_MATCH REGION_SIZE
15 : 9 8 6
PC_MASK_15_TO_1 PC_MASK_0 NS
Description
See corresponding field for PPU structure with programmable address. Default Value: 0
See corresponding field for PPU structure with programmable address. Default Value: Undefined
See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 7
See corresponding field for PPU structure with programmable address. Default Value: Undefined
See corresponding field for PPU structure with programmable address. Default Value: 1
See corresponding field for PPU structure with programmable address. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
147
PERI_GR2_PPU_RG0_ATT0
2.1.93
5
4 3 2
1 0
PERI_GR2_PPU_RG0_ATT0 (continued)
PX
See corresponding field for PPU structure with programmable address.
Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed. Default Value: 1
PW
See corresponding field for PPU structure with programmable address.
Default Value: Undefined
PR
See corresponding field for PPU structure with programmable address.
Default Value: Undefined
UX
See corresponding field for PPU structure with programmable address.
Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed. Default Value: 1
UW
See corresponding field for PPU structure with programmable address.
Default Value: Undefined
UR
See corresponding field for PPU structure with programmable address.
Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
148
PERI_GR2_PPU_RG0_ADDR1
2.1.94 PERI_GR2_PPU_RG0_ADDR1
Address = 0x40201020 PPU region address 1 (master structure) Address: 0x40201020 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4202512 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 252
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
149
PERI_GR2_PPU_RG0_ATT1
2.1.95 PERI_GR2_PPU_RG0_ATT1
Address = 0x40201024 PPU region attributes 1 (master structure) Address: 0x40201024 Retention: Retained
Bits
7
6
5
4
3
2
1
SW Access
None
RW
R
RW
R
R
RW
HW Access
None
R
R
R
R
R
R
Name
None
NS
PX
PW
PR
UX
UW
Bits
15
14
13
12
11
10
9
SW Access
RW
HW Access
R
Name
PC_MASK_15_TO_1 [15:9]
Bits SW Access HW Access
Name
Bits SW Access HW Access
Name
23
22
21
31 RW R ENABLED
30 RW R PC_MATCH
29 None None None
20
19
18
17
None
None
None [23:16]
28
27
26
25
R
R
REGION_SIZE [28:24]
0 R R UR 8 R R PC_MASK_ 0 16
24
Bits 31 30 28 : 24
Name ENABLED PC_MATCH REGION_SIZE
15 : 9 8 6
PC_MASK_15_TO_1 PC_MASK_0 NS
Description
See corresponding field for PPU structure with programmable address. Default Value: 0
See corresponding field for PPU structure with programmable address. Default Value: Undefined
See corresponding field for PPU structure with programmable address.
"7": 256 B region Default Value: 7
See corresponding field for PPU structure with programmable address. Default Value: Undefined
See corresponding field for PPU structure with programmable address. Default Value: 1
See corresponding field for PPU structure with programmable address. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
150
PERI_GR2_PPU_RG0_ATT1
2.1.95
5
4 3
2
1 0
PERI_GR2_PPU_RG0_ATT1 (continued)
PX
See corresponding field for PPU structure with programmable address.
Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed. Default Value: 0
PW
See corresponding field for PPU structure with programmable address.
Default Value: Undefined
PR
See corresponding field for PPU structure with programmable address.
Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed. Default Value: 1
UX
See corresponding field for PPU structure with programmable address.
Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed. Default Value: 0
UW
See corresponding field for PPU structure with programmable address.
Default Value: Undefined
UR
See corresponding field for PPU structure with programmable address.
Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed. Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
151
PERI_GR2_PPU_RG1_ADDR0
2.1.96 PERI_GR2_PPU_RG1_ADDR0
Address = 0x40201040 PPU region address 0 (slave structure) Address: 0x40201040 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4203264 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 253
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
152
PERI_GR2_PPU_RG1_ADDR1
2.1.97 PERI_GR2_PPU_RG1_ADDR1
Address = 0x40201060 PPU region address 1 (master structure) Address: 0x40201060 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4202512 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 243
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
153
PERI_GR2_PPU_RG2_ADDR0
2.1.98 PERI_GR2_PPU_RG2_ADDR0
Address = 0x40201080 PPU region address 0 (slave structure) Address: 0x40201080 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4203264 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 251
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
154
PERI_GR2_PPU_RG2_ADDR1
2.1.99 PERI_GR2_PPU_RG2_ADDR1
Address = 0x402010A0 PPU region address 1 (master structure) Address: 0x402010A0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4202512 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 207
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
155
PERI_GR2_PPU_RG3_ADDR0
2.1.100 PERI_GR2_PPU_RG3_ADDR0
Address = 0x402010C0 PPU region address 0 (slave structure) Address: 0x402010C0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4203264 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 247
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
156
PERI_GR2_PPU_RG3_ADDR1
2.1.101 PERI_GR2_PPU_RG3_ADDR1
Address = 0x402010E0 PPU region address 1 (master structure) Address: 0x402010E0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4202512 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 63
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
157
PERI_GR2_PPU_RG4_ADDR0
2.1.102 PERI_GR2_PPU_RG4_ADDR0
Address = 0x40201100 PPU region address 0 (slave structure) Address: 0x40201100 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4203264 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 239
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
158
PERI_GR2_PPU_RG4_ADDR1
2.1.103 PERI_GR2_PPU_RG4_ADDR1
Address = 0x40201120 PPU region address 1 (master structure) Address: 0x40201120 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4202513 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 252
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
159
PERI_GR2_PPU_RG5_ADDR0
2.1.104 PERI_GR2_PPU_RG5_ADDR0
Address = 0x40201140 PPU region address 0 (slave structure) Address: 0x40201140 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4203264 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 223
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
160
PERI_GR2_PPU_RG5_ADDR1
2.1.105 PERI_GR2_PPU_RG5_ADDR1
Address = 0x40201160 PPU region address 1 (master structure) Address: 0x40201160 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4202513 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 243
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
161
PERI_GR2_PPU_RG6_ADDR0
2.1.106 PERI_GR2_PPU_RG6_ADDR0
Address = 0x40201180 PPU region address 0 (slave structure) Address: 0x40201180 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4203264 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 191
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
162
PERI_GR2_PPU_RG6_ADDR1
2.1.107 PERI_GR2_PPU_RG6_ADDR1
Address = 0x402011A0 PPU region address 1 (master structure) Address: 0x402011A0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4202513 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 207
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
163
PERI_GR2_PPU_RG7_ADDR0
2.1.108 PERI_GR2_PPU_RG7_ADDR0
Address = 0x402011C0 PPU region address 0 (slave structure) Address: 0x402011C0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4203264 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 127
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
164
PERI_GR2_PPU_RG7_ADDR1
2.1.109 PERI_GR2_PPU_RG7_ADDR1
Address = 0x402011E0 PPU region address 1 (master structure) Address: 0x402011E0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4202513 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 63
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
165
PERI_GR2_PPU_RG8_ADDR0
2.1.110 PERI_GR2_PPU_RG8_ADDR0
Address = 0x40201200 PPU region address 0 (slave structure) Address: 0x40201200 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4203281 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 254
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
166
PERI_GR2_PPU_RG8_ADDR1
2.1.111 PERI_GR2_PPU_RG8_ADDR1
Address = 0x40201220 PPU region address 1 (master structure) Address: 0x40201220 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4202514 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 252
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
167
PERI_GR2_PPU_RG9_ADDR0
2.1.112 PERI_GR2_PPU_RG9_ADDR0
Address = 0x40201240 PPU region address 0 (slave structure) Address: 0x40201240 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4203281 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 253
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
168
PERI_GR2_PPU_RG9_ADDR1
2.1.113 PERI_GR2_PPU_RG9_ADDR1
Address = 0x40201260 PPU region address 1 (master structure) Address: 0x40201260 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4202514 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 243
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
169
PERI_GR2_PPU_RG10_ADDR0
2.1.114 PERI_GR2_PPU_RG10_ADDR0
Address = 0x40201280 PPU region address 0 (slave structure) Address: 0x40201280 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4203281 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 251
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
170
PERI_GR2_PPU_RG10_ADDR1
2.1.115 PERI_GR2_PPU_RG10_ADDR1
Address = 0x402012A0 PPU region address 1 (master structure) Address: 0x402012A0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4202514 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 207
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
171
PERI_GR2_PPU_RG11_ADDR0
2.1.116 PERI_GR2_PPU_RG11_ADDR0
Address = 0x402012C0 PPU region address 0 (slave structure) Address: 0x402012C0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4203281 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 247
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
172
PERI_GR2_PPU_RG11_ADDR1
2.1.117 PERI_GR2_PPU_RG11_ADDR1
Address = 0x402012E0 PPU region address 1 (master structure) Address: 0x402012E0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4202514 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 63
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
173
PERI_GR2_PPU_RG12_ADDR0
2.1.118 PERI_GR2_PPU_RG12_ADDR0
Address = 0x40201300 PPU region address 0 (slave structure) Address: 0x40201300 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4203281 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 239
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
174
PERI_GR2_PPU_RG12_ADDR1
2.1.119 PERI_GR2_PPU_RG12_ADDR1
Address = 0x40201320 PPU region address 1 (master structure) Address: 0x40201320 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4202515 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 252
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
175
PERI_GR2_PPU_RG13_ADDR0
2.1.120 PERI_GR2_PPU_RG13_ADDR0
Address = 0x40201340 PPU region address 0 (slave structure) Address: 0x40201340 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4203281 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 223
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
176
PERI_GR2_PPU_RG13_ADDR1
2.1.121 PERI_GR2_PPU_RG13_ADDR1
Address = 0x40201360 PPU region address 1 (master structure) Address: 0x40201360 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4202515 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 243
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
177
PERI_GR2_PPU_RG14_ADDR0
2.1.122 PERI_GR2_PPU_RG14_ADDR0
Address = 0x40201380 PPU region address 0 (slave structure) Address: 0x40201380 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4203281 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 191
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
178
PERI_GR2_PPU_RG14_ADDR1
2.1.123 PERI_GR2_PPU_RG14_ADDR1
Address = 0x402013A0 PPU region address 1 (master structure) Address: 0x402013A0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4202515 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 207
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
179
PERI_GR2_PPU_RG15_ADDR0
2.1.124 PERI_GR2_PPU_RG15_ADDR0
Address = 0x402013C0 PPU region address 0 (slave structure) Address: 0x402013C0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4203281 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 127
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
180
PERI_GR2_PPU_RG15_ADDR1
2.1.125 PERI_GR2_PPU_RG15_ADDR1
Address = 0x402013E0 PPU region address 1 (master structure) Address: 0x402013E0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4202515 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 63
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
181
PERI_GR2_PPU_RG16_ADDR0
2.1.126 PERI_GR2_PPU_RG16_ADDR0
Address = 0x40201400 PPU region address 0 (slave structure) Address: 0x40201400 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4204554 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 254
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
182
PERI_GR2_PPU_RG16_ADDR1
2.1.127 PERI_GR2_PPU_RG16_ADDR1
Address = 0x40201420 PPU region address 1 (master structure) Address: 0x40201420 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4202516 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 252
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
183
PERI_GR2_PPU_RG17_ADDR0
2.1.128 PERI_GR2_PPU_RG17_ADDR0
Address = 0x40201440 PPU region address 0 (slave structure) Address: 0x40201440 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4204554 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 253
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
184
PERI_GR2_PPU_RG17_ADDR1
2.1.129 PERI_GR2_PPU_RG17_ADDR1
Address = 0x40201460 PPU region address 1 (master structure) Address: 0x40201460 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4202516 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 243
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
185
PERI_GR2_PPU_RG18_ADDR0
2.1.130 PERI_GR2_PPU_RG18_ADDR0
Address = 0x40201480 PPU region address 0 (slave structure) Address: 0x40201480 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4204554 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 251
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
186
PERI_GR2_PPU_RG18_ADDR1
2.1.131 PERI_GR2_PPU_RG18_ADDR1
Address = 0x402014A0 PPU region address 1 (master structure) Address: 0x402014A0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4202516 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 207
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
187
PERI_GR2_PPU_RG19_ADDR0
2.1.132 PERI_GR2_PPU_RG19_ADDR0
Address = 0x402014C0 PPU region address 0 (slave structure) Address: 0x402014C0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4204554 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 247
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
188
PERI_GR2_PPU_RG19_ADDR1
2.1.133 PERI_GR2_PPU_RG19_ADDR1
Address = 0x402014E0 PPU region address 1 (master structure) Address: 0x402014E0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4202516 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 63
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
189
PERI_GR2_PPU_RG20_ADDR0
2.1.134 PERI_GR2_PPU_RG20_ADDR0
Address = 0x40201500 PPU region address 0 (slave structure) Address: 0x40201500 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4204570 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 239
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
190
PERI_GR2_PPU_RG20_ADDR1
2.1.135 PERI_GR2_PPU_RG20_ADDR1
Address = 0x40201520 PPU region address 1 (master structure) Address: 0x40201520 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4202517 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 252
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
191
PERI_GR2_PPU_RG21_ADDR0
2.1.136 PERI_GR2_PPU_RG21_ADDR0
Address = 0x40201540 PPU region address 0 (slave structure) Address: 0x40201540 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4204570 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 223
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
192
PERI_GR2_PPU_RG21_ADDR1
2.1.137 PERI_GR2_PPU_RG21_ADDR1
Address = 0x40201560 PPU region address 1 (master structure) Address: 0x40201560 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4202517 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 243
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
193
PERI_GR2_PPU_RG22_ADDR0
2.1.138 PERI_GR2_PPU_RG22_ADDR0
Address = 0x40201580 PPU region address 0 (slave structure) Address: 0x40201580 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4204570 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 191
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
194
PERI_GR2_PPU_RG22_ADDR1
2.1.139 PERI_GR2_PPU_RG22_ADDR1
Address = 0x402015A0 PPU region address 1 (master structure) Address: 0x402015A0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4202517 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 207
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
195
PERI_GR2_PPU_RG23_ADDR0
2.1.140 PERI_GR2_PPU_RG23_ADDR0
Address = 0x402015C0 PPU region address 0 (slave structure) Address: 0x402015C0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4204570 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 127
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
196
PERI_GR2_PPU_RG23_ADDR1
2.1.141 PERI_GR2_PPU_RG23_ADDR1
Address = 0x402015E0 PPU region address 1 (master structure) Address: 0x402015E0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4202517 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 63
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
197
PERI_GR2_PPU_RG24_ADDR0
2.1.142 PERI_GR2_PPU_RG24_ADDR0
Address = 0x40201600 PPU region address 0 (slave structure) Address: 0x40201600 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4203520 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 252
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
198
PERI_GR2_PPU_RG24_ADDR1
2.1.143 PERI_GR2_PPU_RG24_ADDR1
Address = 0x40201620 PPU region address 1 (master structure) Address: 0x40201620 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4202518 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 252
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
199
PERI_GR2_PPU_RG25_ADDR0
2.1.144 PERI_GR2_PPU_RG25_ADDR0
Address = 0x40201640 PPU region address 0 (slave structure) Address: 0x40201640 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4203584 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
200
PERI_GR2_PPU_RG25_ATT0
2.1.145 PERI_GR2_PPU_RG25_ATT0
Address = 0x40201644 PPU region attributes 0 (slave structure) Address: 0x40201644 Retention: Retained
Bits
7
6
5
4
3
2
1
SW Access
None
RW
R
RW
RW
R
RW
HW Access
None
R
R
R
R
R
R
Name
None
NS
PX
PW
PR
UX
UW
Bits
15
14
13
12
11
10
9
SW Access
RW
HW Access
R
Name
PC_MASK_15_TO_1 [15:9]
Bits SW Access HW Access
Name
Bits SW Access HW Access
Name
23
22
21
31 RW R ENABLED
30 RW R PC_MATCH
29 None None None
20
19
18
17
None
None
None [23:16]
28
27
26
25
R
R
REGION_SIZE [28:24]
0 RW R UR
8 R R PC_MASK_ 0 16
24
Bits 31 30 28 : 24
Name ENABLED PC_MATCH REGION_SIZE
15 : 9 8 6
PC_MASK_15_TO_1 PC_MASK_0 NS
Description
See corresponding field for PPU structure with programmable address. Default Value: 0
See corresponding field for PPU structure with programmable address. Default Value: Undefined
See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 9
See corresponding field for PPU structure with programmable address. Default Value: Undefined
See corresponding field for PPU structure with programmable address. Default Value: 1
See corresponding field for PPU structure with programmable address. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
201
PERI_GR2_PPU_RG25_ATT0
2.1.145 PERI_GR2_PPU_RG25_ATT0 (continued)
5
PX
4
PW
3
PR
2
UX
1
UW
0
UR
See corresponding field for PPU structure with programmable address.
Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed. Default Value: 1
See corresponding field for PPU structure with programmable address. Default Value: Undefined
See corresponding field for PPU structure with programmable address. Default Value: Undefined
See corresponding field for PPU structure with programmable address.
Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed. Default Value: 1
See corresponding field for PPU structure with programmable address. Default Value: Undefined
See corresponding field for PPU structure with programmable address. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
202
PERI_GR2_PPU_RG25_ADDR1
2.1.146 PERI_GR2_PPU_RG25_ADDR1
Address = 0x40201660 PPU region address 1 (master structure) Address: 0x40201660 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4202518 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 243
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
203
PERI_GR2_PPU_RG26_ADDR0
2.1.147 PERI_GR2_PPU_RG26_ADDR0
Address = 0x40201680 PPU region address 0 (slave structure) Address: 0x40201680 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4203588 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
204
PERI_GR2_PPU_RG26_ADDR1
2.1.148 PERI_GR2_PPU_RG26_ADDR1
Address = 0x402016A0 PPU region address 1 (master structure) Address: 0x402016A0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4202518 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 207
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
205
PERI_GR2_PPU_RG27_ADDR0
2.1.149 PERI_GR2_PPU_RG27_ADDR0
Address = 0x402016C0 PPU region address 0 (slave structure) Address: 0x402016C0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4203640 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
206
PERI_GR2_PPU_RG27_ADDR1
2.1.150 PERI_GR2_PPU_RG27_ADDR1
Address = 0x402016E0 PPU region address 1 (master structure) Address: 0x402016E0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4202518 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 63
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
207
PERI_GR2_PPU_RG28_ADDR0
2.1.151 PERI_GR2_PPU_RG28_ADDR0
Address = 0x40201700 PPU region address 0 (slave structure) Address: 0x40201700 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4203644 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
208
PERI_GR2_PPU_RG28_ADDR1
2.1.152 PERI_GR2_PPU_RG28_ADDR1
Address = 0x40201720 PPU region address 1 (master structure) Address: 0x40201720 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4202519 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 252
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
209
PERI_GR3_PPU_SL0_ADDR0
2.1.153 PERI_GR3_PPU_SL0_ADDR0
Address = 0x40300000 PPU region address 0 (slave structure) Address: 0x40300000 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4206592 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
210
PERI_GR3_PPU_SL0_ADDR1
2.1.154 PERI_GR3_PPU_SL0_ADDR1
Address = 0x40300020 PPU region address 1 (master structure) Address: 0x40300020 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4206592 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 252
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
211
PERI_GR3_PPU_SL1_ADDR0
2.1.155 PERI_GR3_PPU_SL1_ADDR0
Address = 0x40300040 PPU region address 0 (slave structure) Address: 0x40300040 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4206848 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
212
PERI_GR3_PPU_SL1_ATT0
2.1.156 PERI_GR3_PPU_SL1_ATT0
Address = 0x40300044 PPU region attributes 0 (slave structure) Address: 0x40300044 Retention: Retained
Bits
7
6
5
4
3
2
1
SW Access
None
RW
R
RW
RW
R
RW
HW Access
None
R
R
R
R
R
R
Name
None
NS
PX
PW
PR
UX
UW
Bits
15
14
13
12
11
10
9
SW Access
RW
HW Access
R
Name
PC_MASK_15_TO_1 [15:9]
Bits SW Access HW Access
Name
Bits SW Access HW Access
Name
23
22
21
31 RW R ENABLED
30 RW R PC_MATCH
29 None None None
20
19
18
17
None
None
None [23:16]
28
27
26
25
R
R
REGION_SIZE [28:24]
0 RW R UR
8 R R PC_MASK_ 0 16
24
Bits 31 30 28 : 24
Name ENABLED PC_MATCH REGION_SIZE
15 : 9 8 6
PC_MASK_15_TO_1 PC_MASK_0 NS
Description
See corresponding field for PPU structure with programmable address. Default Value: 0
See corresponding field for PPU structure with programmable address. Default Value: Undefined
See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 13
See corresponding field for PPU structure with programmable address. Default Value: Undefined
See corresponding field for PPU structure with programmable address. Default Value: 1
See corresponding field for PPU structure with programmable address. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
213
PERI_GR3_PPU_SL1_ATT0
2.1.156 PERI_GR3_PPU_SL1_ATT0 (continued)
5
PX
4
PW
3
PR
2
UX
1
UW
0
UR
See corresponding field for PPU structure with programmable address.
Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed. Default Value: 1
See corresponding field for PPU structure with programmable address. Default Value: Undefined
See corresponding field for PPU structure with programmable address. Default Value: Undefined
See corresponding field for PPU structure with programmable address.
Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed. Default Value: 1
See corresponding field for PPU structure with programmable address. Default Value: Undefined
See corresponding field for PPU structure with programmable address. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
214
PERI_GR3_PPU_SL1_ADDR1
2.1.157 PERI_GR3_PPU_SL1_ADDR1
Address = 0x40300060 PPU region address 1 (master structure) Address: 0x40300060 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4206592 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 243
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
215
PERI_GR3_PPU_SL2_ADDR0
2.1.158 PERI_GR3_PPU_SL2_ADDR0
Address = 0x40300080 PPU region address 0 (slave structure) Address: 0x40300080 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4207104 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
216
PERI_GR3_PPU_SL2_ADDR1
2.1.159 PERI_GR3_PPU_SL2_ADDR1
Address = 0x403000A0 PPU region address 1 (master structure) Address: 0x403000A0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4206592 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 207
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
217
PERI_GR3_PPU_SL3_ADDR0
2.1.160 PERI_GR3_PPU_SL3_ADDR0
Address = 0x403000C0 PPU region address 0 (slave structure) Address: 0x403000C0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4207360 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
218
PERI_GR3_PPU_SL3_ADDR1
2.1.161 PERI_GR3_PPU_SL3_ADDR1
Address = 0x403000E0 PPU region address 1 (master structure) Address: 0x403000E0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4206592 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 63
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
219
PERI_GR3_PPU_SL4_ADDR0
2.1.162 PERI_GR3_PPU_SL4_ADDR0
Address = 0x40300100 PPU region address 0 (slave structure) Address: 0x40300100 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4207616 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
220
PERI_GR3_PPU_SL4_ADDR1
2.1.163 PERI_GR3_PPU_SL4_ADDR1
Address = 0x40300120 PPU region address 1 (master structure) Address: 0x40300120 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4206593 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 252
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
221
PERI_GR3_PPU_SL5_ADDR0
2.1.164 PERI_GR3_PPU_SL5_ADDR0
Address = 0x40300140 PPU region address 0 (slave structure) Address: 0x40300140 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4207872 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
222
PERI_GR3_PPU_SL5_ADDR1
2.1.165 PERI_GR3_PPU_SL5_ADDR1
Address = 0x40300160 PPU region address 1 (master structure) Address: 0x40300160 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4206593 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 243
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
223
PERI_GR3_PPU_SL6_ADDR0
2.1.166 PERI_GR3_PPU_SL6_ADDR0
Address = 0x40300180 PPU region address 0 (slave structure) Address: 0x40300180 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4208128 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
224
PERI_GR3_PPU_SL6_ADDR1
2.1.167 PERI_GR3_PPU_SL6_ADDR1
Address = 0x403001A0 PPU region address 1 (master structure) Address: 0x403001A0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4206593 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 207
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
225
PERI_GR3_PPU_SL8_ADDR0
2.1.168 PERI_GR3_PPU_SL8_ADDR0
Address = 0x40300200 PPU region address 0 (slave structure) Address: 0x40300200 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4208640 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
226
PERI_GR3_PPU_SL8_ADDR1
2.1.169 PERI_GR3_PPU_SL8_ADDR1
Address = 0x40300220 PPU region address 1 (master structure) Address: 0x40300220 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4206594 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 252
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
227
PERI_GR3_PPU_SL9_ADDR1
2.1.170 PERI_GR3_PPU_SL9_ADDR1
Address = 0x40300260 PPU region address 1 (master structure) Address: 0x40300260 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4206594 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 243
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
228
PERI_GR3_PPU_SL10_ADDR0
2.1.171 PERI_GR3_PPU_SL10_ADDR0
Address = 0x40300280 PPU region address 0 (slave structure) Address: 0x40300280 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4209408 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
229
PERI_GR3_PPU_SL10_ADDR1
2.1.172 PERI_GR3_PPU_SL10_ADDR1
Address = 0x403002A0 PPU region address 1 (master structure) Address: 0x403002A0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4206594 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 207
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
230
PERI_GR3_PPU_SL11_ADDR0
2.1.173 PERI_GR3_PPU_SL11_ADDR0
Address = 0x403002C0 PPU region address 0 (slave structure) Address: 0x403002C0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4209664 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
231
PERI_GR3_PPU_SL11_ATT0
2.1.174 PERI_GR3_PPU_SL11_ATT0
Address = 0x403002C4 PPU region attributes 0 (slave structure) Address: 0x403002C4 Retention: Retained
Bits
7
6
5
4
3
2
1
SW Access
None
RW
R
RW
RW
R
RW
HW Access
None
R
R
R
R
R
R
Name
None
NS
PX
PW
PR
UX
UW
Bits
15
14
13
12
11
10
9
SW Access
RW
HW Access
R
Name
PC_MASK_15_TO_1 [15:9]
Bits SW Access HW Access
Name
Bits SW Access HW Access
Name
23
22
21
31 RW R ENABLED
30 RW R PC_MATCH
29 None None None
20
19
18
17
None
None
None [23:16]
28
27
26
25
R
R
REGION_SIZE [28:24]
0 RW R UR
8 R R PC_MASK_ 0 16
24
Bits 31 30 28 : 24
Name ENABLED PC_MATCH REGION_SIZE
15 : 9 8 6
PC_MASK_15_TO_1 PC_MASK_0 NS
Description
See corresponding field for PPU structure with programmable address. Default Value: 0
See corresponding field for PPU structure with programmable address. Default Value: Undefined
See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 16
See corresponding field for PPU structure with programmable address. Default Value: Undefined
See corresponding field for PPU structure with programmable address. Default Value: 1
See corresponding field for PPU structure with programmable address. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
232
PERI_GR3_PPU_SL11_ATT0
2.1.174 PERI_GR3_PPU_SL11_ATT0 (continued)
5
PX
4
PW
3
PR
2
UX
1
UW
0
UR
See corresponding field for PPU structure with programmable address.
Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed. Default Value: 1
See corresponding field for PPU structure with programmable address. Default Value: Undefined
See corresponding field for PPU structure with programmable address. Default Value: Undefined
See corresponding field for PPU structure with programmable address.
Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed. Default Value: 1
See corresponding field for PPU structure with programmable address. Default Value: Undefined
See corresponding field for PPU structure with programmable address. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
233
PERI_GR3_PPU_SL11_ADDR1
2.1.175 PERI_GR3_PPU_SL11_ADDR1
Address = 0x403002E0 PPU region address 1 (master structure) Address: 0x403002E0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4206594 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 63
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
234
PERI_GR3_PPU_SL12_ADDR0
2.1.176 PERI_GR3_PPU_SL12_ADDR0
Address = 0x40300300 PPU region address 0 (slave structure) Address: 0x40300300 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4210432 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
235
PERI_GR3_PPU_SL12_ADDR1
2.1.177 PERI_GR3_PPU_SL12_ADDR1
Address = 0x40300320 PPU region address 1 (master structure) Address: 0x40300320 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4206595 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 252
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
236
PERI_GR4_PPU_SL0_ADDR0
2.1.178 PERI_GR4_PPU_SL0_ADDR0
Address = 0x40400000 PPU region address 0 (slave structure) Address: 0x40400000 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4210688 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
237
PERI_GR4_PPU_SL0_ADDR1
2.1.179 PERI_GR4_PPU_SL0_ADDR1
Address = 0x40400020 PPU region address 1 (master structure) Address: 0x40400020 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4210688 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 252
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
238
PERI_GR4_PPU_SL2_ADDR0
2.1.180 PERI_GR4_PPU_SL2_ADDR0
Address = 0x40400080 PPU region address 0 (slave structure) Address: 0x40400080 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4211200 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
239
PERI_GR4_PPU_SL2_ADDR1
2.1.181 PERI_GR4_PPU_SL2_ADDR1
Address = 0x404000A0 PPU region address 1 (master structure) Address: 0x404000A0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4210688 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 207
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
240
PERI_GR6_PPU_SL0_ADDR0
2.1.182 PERI_GR6_PPU_SL0_ADDR0
Address = 0x40600000 PPU region address 0 (slave structure) Address: 0x40600000 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4218880 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
241
PERI_GR6_PPU_SL0_ADDR1
2.1.183 PERI_GR6_PPU_SL0_ADDR1
Address = 0x40600020 PPU region address 1 (master structure) Address: 0x40600020 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4218880 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 252
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
242
PERI_GR6_PPU_SL1_ADDR0
2.1.184 PERI_GR6_PPU_SL1_ADDR0
Address = 0x40600040 PPU region address 0 (slave structure) Address: 0x40600040 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4219136 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
243
PERI_GR6_PPU_SL1_ADDR1
2.1.185 PERI_GR6_PPU_SL1_ADDR1
Address = 0x40600060 PPU region address 1 (master structure) Address: 0x40600060 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4218880 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 243
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
244
PERI_GR6_PPU_SL2_ADDR1
2.1.186 PERI_GR6_PPU_SL2_ADDR1
Address = 0x406000A0 PPU region address 1 (master structure) Address: 0x406000A0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4218880 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 207
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
245
PERI_GR6_PPU_SL3_ADDR1
2.1.187 PERI_GR6_PPU_SL3_ADDR1
Address = 0x406000E0 PPU region address 1 (master structure) Address: 0x406000E0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4218880 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 63
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
246
PERI_GR6_PPU_SL4_ADDR1
2.1.188 PERI_GR6_PPU_SL4_ADDR1
Address = 0x40600120 PPU region address 1 (master structure) Address: 0x40600120 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4218881 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 252
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
247
PERI_GR6_PPU_SL5_ADDR1
2.1.189 PERI_GR6_PPU_SL5_ADDR1
Address = 0x40600160 PPU region address 1 (master structure) Address: 0x40600160 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4218881 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 243
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
248
PERI_GR6_PPU_SL6_ADDR1
2.1.190 PERI_GR6_PPU_SL6_ADDR1
Address = 0x406001A0 PPU region address 1 (master structure) Address: 0x406001A0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4218881 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 207
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
249
PERI_GR6_PPU_SL7_ADDR1
2.1.191 PERI_GR6_PPU_SL7_ADDR1
Address = 0x406001E0 PPU region address 1 (master structure) Address: 0x406001E0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4218881 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 63
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
250
PERI_GR6_PPU_SL8_ADDR1
2.1.192 PERI_GR6_PPU_SL8_ADDR1
Address = 0x40600220 PPU region address 1 (master structure) Address: 0x40600220 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4218882 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 252
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
251
PERI_GR6_PPU_SL9_ADDR1
2.1.193 PERI_GR6_PPU_SL9_ADDR1
Address = 0x40600260 PPU region address 1 (master structure) Address: 0x40600260 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4218882 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 243
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
252
PERI_GR9_PPU_SL0_ADDR0
2.1.194 PERI_GR9_PPU_SL0_ADDR0
Address = 0x41000000 PPU region address 0 (slave structure) Address: 0x41000000 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4259840 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
253
PERI_GR9_PPU_SL0_ADDR1
2.1.195 PERI_GR9_PPU_SL0_ADDR1
Address = 0x41000020 PPU region address 1 (master structure) Address: 0x41000020 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4259840 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 252
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
254
PERI_GR9_PPU_SL1_ADDR0
2.1.196 PERI_GR9_PPU_SL1_ADDR0
Address = 0x41000040 PPU region address 0 (slave structure) Address: 0x41000040 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4263936 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
255
PERI_GR9_PPU_SL1_ATT0
2.1.197 PERI_GR9_PPU_SL1_ATT0
Address = 0x41000044 PPU region attributes 0 (slave structure) Address: 0x41000044 Retention: Retained
Bits
7
6
5
4
3
2
1
SW Access
None
RW
R
RW
RW
R
RW
HW Access
None
R
R
R
R
R
R
Name
None
NS
PX
PW
PR
UX
UW
Bits
15
14
13
12
11
10
9
SW Access
RW
HW Access
R
Name
PC_MASK_15_TO_1 [15:9]
Bits SW Access HW Access
Name
Bits SW Access HW Access
Name
23
22
21
31 RW R ENABLED
30 RW R PC_MATCH
29 None None None
20
19
18
17
None
None
None [23:16]
28
27
26
25
R
R
REGION_SIZE [28:24]
0 RW R UR
8 R R PC_MASK_ 0 16
24
Bits 31 30 28 : 24
Name ENABLED PC_MATCH REGION_SIZE
15 : 9 8 6
PC_MASK_15_TO_1 PC_MASK_0 NS
Description
See corresponding field for PPU structure with programmable address. Default Value: 0
See corresponding field for PPU structure with programmable address. Default Value: Undefined
See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 19
See corresponding field for PPU structure with programmable address. Default Value: Undefined
See corresponding field for PPU structure with programmable address. Default Value: 1
See corresponding field for PPU structure with programmable address. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
256
PERI_GR9_PPU_SL1_ATT0
2.1.197 PERI_GR9_PPU_SL1_ATT0 (continued)
5
PX
4
PW
3
PR
2
UX
1
UW
0
UR
See corresponding field for PPU structure with programmable address.
Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed. Default Value: 1
See corresponding field for PPU structure with programmable address. Default Value: Undefined
See corresponding field for PPU structure with programmable address. Default Value: Undefined
See corresponding field for PPU structure with programmable address.
Note that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed. Default Value: 1
See corresponding field for PPU structure with programmable address. Default Value: Undefined
See corresponding field for PPU structure with programmable address. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
257
PERI_GR9_PPU_SL1_ADDR1
2.1.198 PERI_GR9_PPU_SL1_ADDR1
Address = 0x41000060 PPU region address 1 (master structure) Address: 0x41000060 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4259840 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 243
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
258
PERI_GR10_PPU_SL0_ADDR0
2.1.199 PERI_GR10_PPU_SL0_ADDR0
Address = 0x42A00000 PPU region address 0 (slave structure) Address: 0x42A00000 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4366336 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
259
PERI_GR10_PPU_SL0_ADDR1
2.1.200 PERI_GR10_PPU_SL0_ADDR1
Address = 0x42A00020 PPU region address 1 (master structure) Address: 0x42A00020 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4366336 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 252
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
260
PERI_GR10_PPU_SL1_ADDR0
2.1.201 PERI_GR10_PPU_SL1_ADDR0
Address = 0x42A00040 PPU region address 0 (slave structure) Address: 0x42A00040 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4366592 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
261
PERI_GR10_PPU_SL1_ADDR1
2.1.202 PERI_GR10_PPU_SL1_ADDR1
Address = 0x42A00060 PPU region address 1 (master structure) Address: 0x42A00060 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4366336 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 243
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
262
PERI_GR10_PPU_SL2_ADDR0
2.1.203 PERI_GR10_PPU_SL2_ADDR0
Address = 0x42A00080 PPU region address 0 (slave structure) Address: 0x42A00080 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": address of protected region.
Note: this field is read-only. Its value is chip specific. Default Value: 4366848 See corresponding field for PPU structure with programmable address.
Note: this field is read-only. Its value is chip specific. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
263
PERI_GR10_PPU_SL2_ADDR1
2.1.204 PERI_GR10_PPU_SL2_ADDR1
Address = 0x42A000A0 PPU region address 1 (master structure) Address: 0x42A000A0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description See corresponding field for PPU structure with programmable address.
"ADDR_DEF1": base address of structure.
Note: this field is read-only. Default Value: 4366336 See corresponding field for PPU structure with programmable address.
Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
Note: this field is read-only. Default Value: 207
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
264
Section C:Peripheral Group 1
This section encompasses the following chapters: Cryptography Registers chapter on page 266
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265
3 Cryptography Registers
This section discusses the Cryptography Registers (CRYPTO) registers. It lists all the registers in mapping tables, in address order.
3.1 Register Details
Register CRYPTO_CTL CRYPTO_STATUS CRYPTO_RAM_PWRUP_DELAY CRYPTO_ERROR_STATUS0 CRYPTO_ERROR_STATUS1 CRYPTO_INSTR_FF_CTL CRYPTO_INSTR_FF_STATUS CRYPTO_INSTR_FF_WR CRYPTO_RF_DATA0 CRYPTO_RF_DATA1 CRYPTO_RF_DATA2 CRYPTO_RF_DATA3 CRYPTO_RF_DATA4 CRYPTO_RF_DATA5 CRYPTO_RF_DATA6 CRYPTO_RF_DATA7 CRYPTO_RF_DATA8 CRYPTO_RF_DATA9 CRYPTO_RF_DATA10 CRYPTO_RF_DATA11 CRYPTO_RF_DATA12 CRYPTO_RF_DATA13 CRYPTO_RF_DATA14 CRYPTO_RF_DATA15 CRYPTO_AES_CTL CRYPTO_STR_RESULT
Address 0x40110000 0x40110004 0x40110008 0x40110020 0x40110024 0x40110040 0x40110044 0x40110048 0x40110080 0x40110084 0x40110088 0x4011008C 0x40110090 0x40110094 0x40110098 0x4011009C 0x401100A0 0x401100A4 0x401100A8 0x401100AC 0x401100B0 0x401100B4 0x401100B8 0x401100BC 0x40110100 0x40110180
Description Control Status Power up delay used for SRAM power domain Error status 0 Error status 1 Instruction FIFO control Instruction FIFO status Instruction FIFO write Register-file Register-file. See CRYPTO_RF_DATA0 for the details of bit fields. Register-file. See CRYPTO_RF_DATA0 for the details of bit fields. Register-file. See CRYPTO_RF_DATA0 for the details of bit fields. Register-file. See CRYPTO_RF_DATA0 for the details of bit fields. Register-file. See CRYPTO_RF_DATA0 for the details of bit fields. Register-file. See CRYPTO_RF_DATA0 for the details of bit fields. Register-file. See CRYPTO_RF_DATA0 for the details of bit fields. Register-file. See CRYPTO_RF_DATA0 for the details of bit fields. Register-file. See CRYPTO_RF_DATA0 for the details of bit fields. Register-file. See CRYPTO_RF_DATA0 for the details of bit fields. Register-file. See CRYPTO_RF_DATA0 for the details of bit fields. Register-file. See CRYPTO_RF_DATA0 for the details of bit fields. Register-file. See CRYPTO_RF_DATA0 for the details of bit fields. Register-file. See CRYPTO_RF_DATA0 for the details of bit fields. Register-file. See CRYPTO_RF_DATA0 for the details of bit fields. AES control String result
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
266
Cryptography Registers
Register
Address
CRYPTO_PR_LFSR_CTL0
0x40110200
CRYPTO_PR_LFSR_CTL1
0x40110204
CRYPTO_PR_LFSR_CTL2
0x40110208
CRYPTO_PR_RESULT
0x40110210
CRYPTO_TR_CTL0
0x40110280
CRYPTO_TR_CTL1
0x40110284
CRYPTO_TR_RESULT
0x40110288
CRYPTO_TR_GARO_CTL
0x401102A0
CRYPTO_TR_FIRO_CTL
0x401102A4
CRYPTO_TR_MON_CTL
0x401102C0
CRYPTO_TR_MON_CMD
0x401102C8
CRYPTO_TR_MON_RC_CTL
0x401102D0
CRYPTO_TR_MON_RC_STATUS0 0x401102D8
CRYPTO_TR_MON_RC_STATUS1 0x401102DC
CRYPTO_TR_MON_AP_CTL
0x401102E0
CRYPTO_TR_MON_AP_STATUS0 0x401102E8
CRYPTO_TR_MON_AP_STATUS1 0x401102EC
CRYPTO_SHA_CTL
0x40110300
CRYPTO_CRC_CTL
0x40110400
CRYPTO_CRC_DATA_CTL
0x40110410
CRYPTO_CRC_POL_CTL
0x40110420
CRYPTO_CRC_LFSR_CTL
0x40110430
CRYPTO_CRC_REM_CTL
0x40110440
CRYPTO_CRC_REM_RESULT
0x40110448
CRYPTO_VU_CTL0
0x40110480
CRYPTO_VU_CTL1
0x40110484
CRYPTO_VU_STATUS
0x40110490
CRYPTO_INTR
0x401107C0
CRYPTO_INTR_SET
0x401107C4
CRYPTO_INTR_MASK
0x401107C8
CRYPTO_INTR_MASKED
0x401107CC
CRYPTO_MEM_BUFF0
0x40114000
Description Pseudo random LFSR control 0 Pseudo random LFSR control 1 Pseudo random LFSR control 2 Pseudo random result True random control 0 True random control 1 True random result True random GARO control True random FIRO control True random monitor control True random monitor command True random monitor RC control True random monitor RC status 0 True random monitor RC status 1 True random monitor AP control True random monitor AP status 0 True random monitor AP status 1 SHA control CRC control CRC data control CRC polynomial control CRC LFSR control CRC remainder control CRC remainder result Vector unit control 0 Vector unit control 1 Vector unit status Interrupt register Interrupt set register Interrupt mask register Interrupt masked register Memory buffer. This is the starting address of a register bank containing 1024 registers (CRYPTO_MEM_BUFF0 to CRYPTO_MEM_BUFF1023)
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CRYPTO_CTL
3.1.1 CRYPTO_CTL
Address = 0x40110000 Control Address: 0x40110000 Retention: Retained
Bits
7
6
SW Access
HW Access
Name
Bits
15
14
SW Access
HW Access
Name
Bits
23
22
SW Access
HW Access
Name
Bits
31
30
SW Access
RW
HW Access
R
Name
ENABLED
5
4
3
2
None
None
None [7:2]
13
12
11
10
None
None
None [15:8]
21
20
19
18
None
None
None [23:16]
29
28
27
26
None
None
None [30:24]
1
0
RW
R
PWR_MODE [1:0]
9
8
17
16
25
24
Bits
Name
31
ENABLED
1 : 0
PWR_MODE
Description
IP enable: '0': Disabled. All non-retention registers (command and status registers) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled. '1': Enabled. Default Value: 0
0x0: DISABLED
0x1: ENABLED
Set power mode for memory buffer SRAM. Default Value: 3
0x0: OFF : See CM4_PWR_CTL
0x1: RESERVED : undefined
0x2: RETAINED : See CM4_PWR_CTL
0x3: ENABLED : See CM4_PWR_CTL
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
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CRYPTO_STATUS
3.1.2 CRYPTO_STATUS
Address = 0x40110004 Status Address: 0x40110004 Retention: Not Retained
Bits SW Access HW Access
Name
7 R W VU_BUSY
6 R W TR_BUSY
5 R W PR_BUSY
4
3
2
1
0
R
R
R
R
R
W
W
W
W
W
STR_BUSY CRC_BUSY SHA_BUSY DES_BUSY AES_BUSY
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
None
HW Access
W
None
Name
CMD_FF_BUS
Y
None [30:24]
Bits
Name
31
CMD_FF_BUSY
7
VU_BUSY
6
TR_BUSY
5
PR_BUSY
4
STR_BUSY
3
CRC_BUSY
Description
Reflects the state of the command FIFO (copy of CMD_FF_STATUS.BUSY): '0': No instruction pending. '1': Instruction pending. Default Value: 0
Reflects the state of the vector unit component. Default Value: 0
Reflects the state of the TR component. Default Value: 0
Reflects the state of the PR component. Default Value: 0
Reflects the state of the CRC component. Default Value: 0
Reflects the state of the CRC component. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
269
2
SHA_BUSY
1
DES_BUSY
0
AES_BUSY
CRYPTO_STATUS
Reflects the state of the SHA component. Default Value: 0 Reflects the state of the DES component. Default Value: 0 Reflects the state of the AES component: '0': Component is not busy. '1': Component is busy performing an instruction. When the component is busy, it is NOT possible to start another operation. However, it is possible to access the instruction FIFO or memory buffer (to prepare for another operation). Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
270
0x40110008 CRYPTO_RAM_PWRUP_DELAY
3.1.3 CRYPTO_RAM_PWRUP_DELAY
Address = 0x40110008 Power up delay used for SRAM power domain Address: 0x40110008 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
PWRUP_DELAY [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
RW
HW Access
None
R
Name
None [15:10]
PWRUP_DELAY [9:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 9 : 0
Name PWRUP_DELAY
Description
Number clock cycles delay needed after power domain power up Default Value: 150
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
271
CRYPTO_ERROR_STATUS0
3.1.4 CRYPTO_ERROR_STATUS0
Address = 0x40110020 Error status 0 Address: 0x40110020 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
DATA32 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
DATA32 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
W
Name
DATA32 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
W
Name
DATA32 [31:24]
Bits 31 : 0
Name DATA32
Description
Captures error description information. For INSTR_OPC_ERROR: - Violating instruction. For INSTR_CC_ERROR: - Violating instruction. For BUS_ERROR: - Violating transfer address. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
272
0x40110024 CRYPTO_ERROR_STATUS1
3.1.5 CRYPTO_ERROR_STATUS1
Address = 0x40110024 Error status 1 Address: 0x40110024 Retention: Not Retained
Bits
7
6
5
4
3
SW Access
R
HW Access
W
Name
DATA23 [7:0]
Bits
15
14
13
12
11
SW Access
R
HW Access
W
Name
DATA23 [15:8]
Bits
23
22
21
20
19
SW Access
R
HW Access
W
Name
DATA23 [23:16]
Bits
31
30
29
28
27
SW Access
RW
None
HW Access
RW1S
None
Name
VALID
None [30:27]
2
1
0
10
9
8
18
17
16
26
25
24
RW
RW
IDX [26:24]
Bits 31
26 : 24
Name VALID
IDX
23 : 0
DATA23
Description
Specifies if ERROR_STATUS0 and ERROR_STATUS1 capture valid error information. Default Value: 0
Error source: "0": INSTR_OPC_ERROR, instruction decoder error. "1": INSTR_CC_ERROR, instruction condition code error. "2": BUS_ERROR, Bus master interface AHB-Lite bus error. "3": TR_AP_DETECT_ERROR. "4": TR_RC_DETECT_ERROR. "5"-"7": Undefined. Default Value: 0
Captures error description information. For BUS_ERROR: - Violating transfer, read attribute (DATA23[0]). - Violating transfer, size attribute (DATA23[5:4]). "0": 8-bit transfer, "1": 16 bits transfer, "2": 32bit transfer. For INSTR_CC_ERROR: Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
273
CRYPTO_INSTR_FF_CTL
3.1.6 CRYPTO_INSTR_FF_CTL
Address = 0x40110040 Instruction FIFO control Address: 0x40110040 Retention: Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:3]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:18]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
0
RW
R
EVENT_LEVEL [2:0]
10
9
8
18
17
16
RW
RW
R
RW1S
BLOCK
CLEAR
26
25
24
Bits
Name
17
BLOCK
16
CLEAR
2 : 0
EVENT_LEVEL
Description
This field specifies the behavior when an instruction is written to a full FIFO (INSTR_FIFO_WR MMIO register): '0': The write is ignored/dropped and the INTR.INSTR_FF_OVERFLOW interrupt cause is set to '1'. '1': The write is blocked, resulting in AHB-Lite wait states and the INTR.INSTR_FF_OVERFLOW interrupt cause is set to '1' (this cause may be masked out). The instruction is written to the FIFO as soon as a FIFO entry becomes available. The maximum time is roughly the time of the execution of the slowest/longest instruction. Note that this setting may "lock up" the CPU. When the CPU is "locked up" it can not respond to interrupts. As a result, the interrupt latency is increased. Default Value: 1
When '1', the instruction FIFO is cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. HW sets this field to '1' on when an error INTR cause is activated. Default Value: 0
Event level. When the number of entries in the instruction FIFO is less than the amount of this field, an event is generated: - "event" = INSTR_FF_STATUS.USED < EVENT_LEVEL. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
274
0x40110044 CRYPTO_INSTR_FF_STATUS
3.1.7 CRYPTO_INSTR_FF_STATUS
Address = 0x40110044 Instruction FIFO status Address: 0x40110044 Retention: Not Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:4]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:17]
Bits
31
30
29
28
27
SW Access
R
None
HW Access
W
None
Name
BUSY
None [30:24]
2
1
R
W
USED [3:0]
10
9
18
17
26
25
0
8
16 R W EVENT 24
Bits
Name
31
BUSY
16
EVENT
3 : 0
USED
Description
Reflects the state of the instruction FIFO: '0': No instruction pending (USED is "0"). '1': Instruction pending. Default Value: 0
Instruction FIFO event. Default Value: 0
Number of instructions in the instruction FIFO. The value of this field ranges from 0 to 8. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
275
0x40110048 CRYPTO_INSTR_FF_WR
3.1.8 CRYPTO_INSTR_FF_WR
Address = 0x40110048 Instruction FIFO write Address: 0x40110048 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
W
HW Access
R
Name
DATA32 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
W
HW Access
R
Name
DATA32 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
W
HW Access
R
Name
DATA32 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
W
HW Access
R
Name
DATA32 [31:24]
Bits 31 : 0
Name DATA32
Description
Instruction or instruction operand data that is written to the instruction FIFO. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
276
0x40110080 CRYPTO_RF_DATA0
3.1.9 CRYPTO_RF_DATA0
Address = 0x40110080 Register-file Address: 0x40110080 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
DATA32 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
DATA32 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
W
Name
DATA32 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
W
Name
DATA32 [31:24]
Bits 31 : 0
Name DATA32
Description
Register-file data. For the vector unit component, a register-file register has the following layout: DATA[29:16]: data DATA[11:0]: bit size (minus 1) Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
277
CRYPTO_AES_CTL
3.1.10 CRYPTO_AES_CTL
Address = 0x40110100 AES control Address: 0x40110100 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:2]
KEY_SIZE [1:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 1 : 0
Name KEY_SIZE
Description
AES key size: "0": 128-bit key, 10 rounds AES (inverse) cipher operation. SRC_CTL0 specifies the location of a 16 Byte key. "1": 192-bit key, 12 rounds AES (inverse) cipher operation. SRC_CTL0 specifies the location of a 24 Byte key. "2": 256-bit key, 14 rounds AES (inverse) cipher operation. SRC_CTL0 specifies the location of a 32 Byte key. "3": Undefined Default Value: 0
0x0: AES128 :
0x1: AES192 :
0x2: AES256 :
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
278
0x40110180 CRYPTO_STR_RESULT
3.1.11 CRYPTO_STR_RESULT
Address = 0x40110180 String result Address: 0x40110180 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
R
HW Access
None
W
Name
None [7:1]
MEMCMP
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
MEMCMP
Description
Result of a STR_MEMCMP operation: '0': source 0 equals source 1. '1': source 0 does NOT equal source 1. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
279
CRYPTO_PR_LFSR_CTL0
3.1.12 CRYPTO_PR_LFSR_CTL0
Address = 0x40110200 Pseudo random LFSR control 0 Address: 0x40110200 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
LFSR32 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
RW
Name
LFSR32 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
RW
Name
LFSR32 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
RW
Name
LFSR32 [31:24]
Bits 31 : 0
Name LFSR32
Description
State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to generate a pseudo random bit sequence. This register needs to be initialized by SW. The initialization value should be different from "0". The three PR_LFSR_CTL registers represents the state of a 32-bit, 31-bit and 29-bit LFSR. Individually, these LFSRs generate a pseudo random bit sequence that repeats itself after (2^32)1, (2^31)-1 and (2^29)-1 bits. The numbers (2^32)-1, (2^31)-1 and (2^29)-1 are relatively prime (their greatest common denominator is "1"). The three bit sequence are combined (XOR'd) into a single bitstream to create a pseudo random bit sequence that repeats itself after ((2^32)-1) * ((2^31)-1) * ((2*29)-1) bits. The following polynomials are used: - 32-bit irreducible polynomial: x^32+x^30+x^26+x^25+1. - 31-bit irreducible polynomial: x^31+x^28+1. - 29-bit irreducible polynomial: x^29+x^27+1. Default Value: 3633683401
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
280
0x40110204 CRYPTO_PR_LFSR_CTL1
3.1.13 CRYPTO_PR_LFSR_CTL1
Address = 0x40110204 Pseudo random LFSR control 1 Address: 0x40110204 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
LFSR31 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
RW
Name
LFSR31 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
RW
Name
LFSR31 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
RW
HW Access
None
RW
Name
None
LFSR31 [30:24]
Bits 30 : 0
Name LFSR31
Description
State of a 31-bit Linear Feedback Shift Registers (LFSR) that is used to generate a pseudo random bit sequence. See PR_LFSR_CTL0. Default Value: 733549048
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
281
CRYPTO_PR_LFSR_CTL2
3.1.14 CRYPTO_PR_LFSR_CTL2
Address = 0x40110208 Pseudo random LFSR control 2 Address: 0x40110208 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
LFSR29 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
RW
Name
LFSR29 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
RW
Name
LFSR29 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
RW
HW Access
None
RW
Name
None [31:29]
LFSR29 [28:24]
Bits 28 : 0
Name LFSR29
Description
State of a 29-bit Linear Feedback Shift Registers (LFSR) that is used to generate a pseudo random bit sequence. See PR_LFSR_CTL0. Default Value: 101462455
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
282
0x40110210 CRYPTO_PR_RESULT
3.1.15 CRYPTO_PR_RESULT
Address = 0x40110210 Pseudo random result Address: 0x40110210 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
A
Name
DATA32 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
A
Name
DATA32 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
A
Name
DATA32 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
A
Name
DATA32 [31:24]
Bits 31 : 0
Name DATA32
Description
Result of a pseudo random number generation operation. The resulting value DATA is in the range [0, MAX], with MAX specified by rsrc0. HW generates the number in this field. Note that SW can write this field. This functionality can be used prevent information leakage. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
283
CRYPTO_TR_CTL0
3.1.16 CRYPTO_TR_CTL0
Address = 0x40110280 True random control 0 Address: 0x40110280 Retention: Retained
Bits
7
6
5
4
3
2
1
SW Access
RW
HW Access
R
Name
SAMPLE_CLOCK_DIV [7:0]
Bits
15
14
13
12
11
10
9
SW Access
RW
HW Access
R
Name
RED_CLOCK_DIV [15:8]
Bits
23
22
21
20
19
18
17
SW Access
RW
HW Access
R
Name
INIT_DELAY [23:16]
Bits SW Access HW Access
Name
31
30
None
None
None [31:30]
29
28
RW
RW
R
R
STOP_ON_ RC_DETECT
STOP_ON_ AP_DETECT
27
26
25
None
None
None [27:25]
0
8
16
24 RW R VON_NEUMANN_CORR
Bits
Name
Description
29
STOP_ON_RC_DETECT Specifies if TRNG functionality is stopped on a repetition count test detection (when HW sets IN-
TR.TR_RC_DETECT to '1'):
'0': Functionality is NOT stopped.
'1': Functionality is stopped (TR_CTL1 fields are set to '0' by HW).
Default Value: 0
28
STOP_ON_AP_DETECT Specifies if TRNG functionality is stopped on an adaptive proportion test detection (when HW
sets INTR.TR_AP_DETECT to '1'):
'0': Functionality is NOT stopped.
'1': Functionality is stopped (TR_CTL1 fields are set to '0' by HW).
Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
284
0x40110280 CRYPTO_TR_CTL0
3.1.16
24
23 : 16
15 : 8 7 : 0
CRYPTO_TR_CTL0 (continued)
VON_NEUMANN_CORR INIT_DELAY RED_CLOCK_DIV SAMPLE_CLOCK_DIV
Specifies if the "von Neumann corrector" is disabled or enabled: '0': disabled. '1': enabled. The "von Neumann corrector" post-processes the reduced bits to remove a '0' or '1' bias. The corrector operates on reduced bit pairs ("oldest bit, newest bit"): "00": no bit is produced. "01": '0' bit is produced (oldest bit). "10": '1' bit is produced (oldest bit). "11": no bit is produced. Note that the corrector produces bits at a random pace and at a frequency that is 1/4 of the reduced bit frequency (reduced bits are processed in pairs, and half of the pairs do NOT produce a bit). Default Value: 0
Specifies an initialization delay: number of removed/dropped samples before reduced bits are generated. This field should be programmed in the range [1, 255]. After starting the oscillators, at least the first 2 samples should be removed/dropped to clear the state of internal synchronizers. In addition, it is advised to drop at least the second 2 samples from the oscillators (to circumvent the semi-predictable oscillator startup behavior). This result in the default field value of "3". Field encoding is as follows: "0": 1 sample is dropped. "1": 2 samples are dropped. ... "255": 256 samples are dropped. The TR_INITIALIZED interrupt cause is set to '1', when the initialization delay is passed. Default Value: 3
Specifies the clock divider that is used to produce reduced bits. "0": 1 reduced bit is produced for each sample. "1": 1 reduced bit is produced for each 2 samples. ... "255": 1 reduced bit is produced for each 256 samples. The reduced bits are considered random bits and shifted into TR_RESULT0.DATA32. Default Value: 0
Specifies the clock divider that is used to sample oscillator data. This clock divider is wrt. "clk_sys". "0": sample clock is "clk_sys". "1": sample clock is "clk_sys"/2. ... "255": sample clock is "clk_sys"/256. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
285
CRYPTO_TR_CTL1
3.1.17 CRYPTO_TR_CTL1
Address = 0x40110284 True random control 1 Address: 0x40110284 Retention: Retained
Bits SW Access HW Access
Name
7
6
None
None
None [7:6]
5 RW RW1C
4 RW RW1C
FIRO31_EN FIRO15_EN
3
RW
RW1C
GARO31_EN
2
RW
RW1C
GARO15_EN
1 RW RW1C
RO15_EN
0 RW RW1C
RO11_EN
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
5
FIRO31_EN
4
FIRO15_EN
3
GARO31_EN
2
GARO15_EN
1
RO15_EN
0
RO11_EN
Description
FW sets this field to '1' to enable the programmable Fibonacci ring oscillator with up to 31 inverters. The TR_FIRO_CTL register specifies the programmable polynomial. Default Value: 0
FW sets this field to '1' to enable the fixed Fibonacci ring oscillator with 15 inverters. Default Value: 0
FW sets this field to '1' to enable the programmable Galois ring oscillator with up to 31 inverters. The TR_GARO_CTL register specifies the programmable polynomial. Default Value: 0
FW sets this field to '1' to enable the fixed Galois ring oscillator with 15 inverters. Default Value: 0
FW sets this field to '1' to enable the ring oscillator with 15 inverters. Default Value: 0
FW sets this field to '1' to enable the ring oscillator with 11 inverters. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
286
0x40110288 CRYPTO_TR_RESULT
3.1.18 CRYPTO_TR_RESULT
Address = 0x40110288 True random result Address: 0x40110288 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
A
Name
DATA32 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
A
Name
DATA32 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
A
Name
DATA32 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
A
Name
DATA32 [31:24]
Bits 31 : 0
Name DATA32
Description
Generated true random number. HW generates the number in the least significant bit positions of this field. The TR_DATA_AVAILABLE interrupt cause is activated when the number is generated. Note that SW can write this field. This functionality can be used prevent information leakage. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
287
CRYPTO_TR_GARO_CTL
3.1.19 CRYPTO_TR_GARO_CTL
Address = 0x401102A0 True random GARO control Address: 0x401102A0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
POLYNOMIAL31 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
POLYNOMIAL31 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
POLYNOMIAL31 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
RW
HW Access
None
R
Name
None
POLYNOMIAL31 [30:24]
Bits 30 : 0
Name POLYNOMIAL31
Description
Polynomial for programmable Galois ring oscillator. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned such that the more significant bits (bit 30 and down) contain the polynomial and the less significant bits (bit 0 and up) contain padding '0's. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
288
0x401102A4 CRYPTO_TR_FIRO_CTL
3.1.20 CRYPTO_TR_FIRO_CTL
Address = 0x401102A4 True random FIRO control Address: 0x401102A4 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
POLYNOMIAL31 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
POLYNOMIAL31 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
POLYNOMIAL31 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
RW
HW Access
None
R
Name
None
POLYNOMIAL31 [30:24]
Bits 30 : 0
Name POLYNOMIAL31
Description
Polynomial for programmable Fibonacci ring oscillator. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned such that the more significant bits (bit 30 and down) contain the polynomial and the less significant bits (bit 0 and up) contain padding '0's. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
289
CRYPTO_TR_MON_CTL
3.1.21 CRYPTO_TR_MON_CTL
Address = 0x401102C0 True random monitor control Address: 0x401102C0 Retention: Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:2]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
Bits 1 : 0
Name BITSTREAM_SEL
Description
Selection of the bitstream: "0": DAS bitstream. "1": RED bitstream. "2": TR bitstream. "3": Undefined. Default Value: 2
2
1
0
RW
R
BITSTREAM_SEL [1:0]
10
9
8
18
17
16
26
25
24
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
290
0x401102C8 CRYPTO_TR_MON_CMD
3.1.22 CRYPTO_TR_MON_CMD
Address = 0x401102C8 True random monitor command Address: 0x401102C8 Retention: Not Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:2]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
0
RW
RW
RW1C
RW1C
START_RC START_AP
10
9
8
18
17
16
26
25
24
Bits
Name
1
START_RC
0
START_AP
Description
Repetition count (RC) test enable: '0': Disabled. '1': Enabled. On a RC detection, HW sets this field to '0' and sets INTR.TR_RC_DETECT to '1. Default Value: 0
Adaptive proportion (AP) test enable: '0': Stopped. '1': Started. On a AP detection, HW sets this field to '0' and sets INTR.TR_AP_DETECT to '1. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
291
CRYPTO_TR_MON_RC_CTL
3.1.23 CRYPTO_TR_MON_RC_CTL
Address = 0x401102D0 True random monitor RC control Address: 0x401102D0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
CUTOFF_COUNT8 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 0
Name CUTOFF_COUNT8
Description
Cutoff count (legal range is [1, 255]): "0": Illegal. "1": 1 repetition. ... "255": 255 repetitions. Default Value: 255
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
292
0x401102D8 CRYPTO_TR_MON_RC_STATUS0
3.1.24 CRYPTO_TR_MON_RC_STATUS0
Address = 0x401102D8 True random monitor RC status 0 Address: 0x401102D8 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
R
HW Access
None
RW
Name
None [7:1]
BIT
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
BIT
Description
Current active bit value: '0': '0'. '1': '1'. This field is only valid when TR_MON_RC_STATUS1.REP_COUNT is NOT equal to "0". Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
293
CRYPTO_TR_MON_RC_STATUS1
3.1.25 CRYPTO_TR_MON_RC_STATUS1
Address = 0x401102DC True random monitor RC status 1 Address: 0x401102DC Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
RW
Name
REP_COUNT [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 0
Name REP_COUNT
Description
Number of repetitions of the current active bit counter: "0": 0 repetitions. ... "255": 255 repetitions. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
294
0x401102E0 CRYPTO_TR_MON_AP_CTL
3.1.26 CRYPTO_TR_MON_AP_CTL
Address = 0x401102E0 True random monitor AP control Address: 0x401102E0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
CUTOFF_COUNT16 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
CUTOFF_COUNT16 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
WINDOW_SIZE [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
WINDOW_SIZE [31:24]
Bits 31 : 16
Name WINDOW_SIZE
15 : 0
CUTOFF_COUNT16
Description
Window size (minus 1) : "0": 1 bit. ... "65535": 65536 bits. Default Value: 65535
Cutoff count (legal range is [1, 65535]). "0": Illegal. "1": 1 occurrence. ... "65535": 65535 occurrences. Default Value: 65535
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
295
CRYPTO_TR_MON_AP_STATUS0
3.1.27 CRYPTO_TR_MON_AP_STATUS0
Address = 0x401102E8 True random monitor AP status 0 Address: 0x401102E8 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
R
HW Access
None
RW
Name
None [7:1]
BIT
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
BIT
Description
Current active bit value: '0': '0'. '1': '1'. This field is only valid when TR_MON_AP_STATUS1.OCC_COUNT is NOT equal to "0". Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
296
0x401102EC CRYPTO_TR_MON_AP_STATUS1
3.1.28 CRYPTO_TR_MON_AP_STATUS1
Address = 0x401102EC True random monitor AP status 1 Address: 0x401102EC Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
RW
Name
OCC_COUNT [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
RW
Name
OCC_COUNT [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
RW
Name
WINDOW_INDEX [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
RW
Name
WINDOW_INDEX [31:24]
Bits 31 : 16
Name WINDOW_INDEX
15 : 0
OCC_COUNT
Description
Counter to keep track of the current index in the window (counts from "0" to TR_MON_AP_CTL.WINDOW_SIZE). Default Value: 0
Number of occurrences of the current active bit counter: "0": 0 occurrences ... "65535": 65535 occurrences Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
297
CRYPTO_SHA_CTL
3.1.29 CRYPTO_SHA_CTL
Address = 0x40110300 SHA control Address: 0x40110300 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:3]
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4
3
12
11
None
None
None [15:8]
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
2
1
0
RW
R
MODE [2:0]
10
9
8
18
17
16
26
25
24
Bits 2 : 0
Name MODE
Description
SHA mode: "0": SHA1. The message is 16 32 bits words: 64 Bytes. The hash is 5 32-bit words: 20 Bytes. There are 80 32-bit message schedule round constants: 320 Bytes. "1": SHA224, SHA256. The message is 16 32-bit words: 64 Bytes. The hash is 8 32-bit words: 32 Bytes. There are 64 32-bit message schedule round constants: 256 Bytes. The difference between SHA224 and SHA256 is entirely in software (differences in initialization hash and message digest size). "2": SHA512/224, SHA512/256, SHA384, SHA512. The message is 8 64-bit words: 64 Bytes. The hash is 8 64-bit words: 64 Bytes. There are 80 64-bit message schedule round constants: 640 Bytes. The difference between SHA512/224, SHA512/256, SHA384 and SHA512 is entirely in software (differences in initialization hash and message digest size). "3"-"7": Undefined. Default Value: 0
0x0: SHA1 :
0x1: SHA256 :
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
298
3.1.29
CRYPTO_SHA_CTL (continued)
0x2: SHA512 :
0x40110300 CRYPTO_SHA_CTL
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
299
CRYPTO_CRC_CTL
3.1.30 CRYPTO_CRC_CTL
Address = 0x40110400 CRC control Address: 0x40110400 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:1]
DATA_REVERSE
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:9]
9
8
RW
R
REM_REVERSE
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
8
REM_REVERSE
0
DATA_REVERSE
Description
Specifies whether the remainder is bit reversed (reversal is performed after XORing): '0': No. '1': Yes. Default Value: 0
Specifies the bit order in which a data Byte is processed (reversal is performed after XORing): '0': Most significant bit (bit 1) first. '1': Least significant bit (bit 0) first. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
300
0x40110410 CRYPTO_CRC_DATA_CTL
3.1.31 CRYPTO_CRC_DATA_CTL
Address = 0x40110410 CRC data control Address: 0x40110410 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
DATA_XOR [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 0
Name DATA_XOR
Description
Specifies a byte mask with which each data byte is XOR'd. The XOR is performed before data reversal. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
301
CRYPTO_CRC_POL_CTL
3.1.32 CRYPTO_CRC_POL_CTL
Address = 0x40110420 CRC polynomial control Address: 0x40110420 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
POLYNOMIAL [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
POLYNOMIAL [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
POLYNOMIAL [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
POLYNOMIAL [31:24]
Bits 31 : 0
Name POLYNOMIAL
Description
CRC polynomial. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned/shifted such that the more significant bits (bit 31 and down) contain the polynomial and the less significant bits (bit 0 and up) contain padding '0's. Some frequently used polynomials: - CRC32: POLYNOMIAL is 0x04c11db7 (x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1). - CRC16: POLYNOMIAL is 0x80050000 (x^16 + x^15 + x^2 + 1, shifted by 16 bit positions). - CRC16 CCITT: POLYNOMIAL is 0x10210000 (x^16 + x^12 + x^5 + 1, shifted by 16 bit positions). Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
302
0x40110430 CRYPTO_CRC_LFSR_CTL
3.1.33 CRYPTO_CRC_LFSR_CTL
Address = 0x40110430 CRC LFSR control Address: 0x40110430 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
LFSR32 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
RW
Name
LFSR32 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
RW
Name
LFSR32 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
RW
Name
LFSR32 [31:24]
Bits 31 : 0
Name LFSR32
Description
State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to implement CRC. This register needs to be initialized by SW to provide the CRC seed value. The seed value should be aligned such that the more significant bits (bit 31 and down) contain the seed value and the less significant bits (bit 0 and up) contain padding '0's. Note that SW can write this field. This functionality can be used prevent information leakage (through either CRC_LFSR_CTL or CRC_REM_RESULT) from the privileged domain to the user domain. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
303
CRYPTO_CRC_REM_CTL
3.1.34 CRYPTO_CRC_REM_CTL
Address = 0x40110440 CRC remainder control Address: 0x40110440 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
REM_XOR [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
REM_XOR [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
REM_XOR [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
REM_XOR [31:24]
Bits 31 : 0
Name REM_XOR
Description
Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XOR'd to produce a remainder. The XOR is performed before remainder reversal. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
304
0x40110448 CRYPTO_CRC_REM_RESULT
3.1.35 CRYPTO_CRC_REM_RESULT
Address = 0x40110448 CRC remainder result Address: 0x40110448 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
REM [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
REM [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
W
Name
REM [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
W
Name
REM [31:24]
Bits 31 : 0
Name REM
Description
Remainder value. The alignment of the remainder depends on CRC_REM_CTL0.REM_REVERSE: '0': the more significant bits (bit 31 and down) contain the remainder. '1': the less significant bits (bit 0 and up) contain the remainder. Note: This field is combinatorially derived from CRC_LFSR_CTL.LFSR32, CRC_REM_CTL0.REM_REVERSE and CRC_REM_CTL1.REM_XOR. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
305
CRYPTO_VU_CTL0
3.1.36 CRYPTO_VU_CTL0
Address = 0x40110480 Vector unit control 0 Address: 0x40110480 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:1]
ALWAYS_EX-
ECUTE
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
Description
0
ALWAYS_EXECUTE
Specifies if a conditional instruction is executed or not, when its condition code evaluates to false/
'0'.
'0': The instruction is NOT executed. As a result, the instruction may be handled faster than when
it is executed.
'1': The instruction is executed, but the execution result (including status field information) is not
reflected in the IP. The instruction is handled just as fast as when it is executed.
Note: a conditional instruction with a condition code that evaluates to false/'0' does not affect the
architectural state: VU_STATUS fields, memory or register-file data.
Note: Always execution is useful to prevent/complicate differential timing and differential power
attacks.
Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
306
0x40110484 CRYPTO_VU_CTL1
3.1.37 CRYPTO_VU_CTL1
Address = 0x40110484 Vector unit control 1 Address: 0x40110484 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
None
HW Access
R
None
Name
ADDR [15:14]
None [13:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
ADDR [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
ADDR [31:24]
Bits 31 : 14
Name ADDR
Description
Specifies base address of vector unit operands in memory. The register-file registers provide offsets wrt. this base address. The base address is a multiple of 16 KB. The register-file registers provide 12-bit word address offsets in this 16 KB. Together, they provide access to a 16 KB memory region for vector unit instructions: ADDR[31:14] = VU_CTL1.ADDR[31:14] ADDR[13:2] = register-file register offset The base address is either the IP's internal memory buffer (memory capacity is the internal memory buffer capacity) or a location in system memory (memory capacity is 16 KB). For best performance, the IP's memory buffer should be used and VU_CTL1.ADDR should be programmed to MEM_BUFF. If VU_CTL1.ADDR is set to MEM_BUFF and the memory buffer capacity is less than 16 KB, memory accesses beyond the memory buffer capacity access a memory hole (reads return "0" and writes are ignored). E.g., if the memory buffer is 8 KB, accesses with ADDR[13] set to '1', access a memory hole. If the IP's memory buffer capacity is not large enough to support the vector unit operands, VU_CTL1.ADDR can be set to a 16 KB aligned location in system memory. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
307
CRYPTO_VU_STATUS
3.1.38 CRYPTO_VU_STATUS
Address = 0x40110490 Vector unit status Address: 0x40110490 Retention: Not Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:4]
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4
3
R
W
ONE
12
11
None
None
None [15:8]
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
2 R W ZERO
10
1 R W EVEN
9
0 R W CARRY
8
18
17
16
26
25
24
Bits
Name
3
ONE
2
ZERO
1
EVEN
0
CARRY
Description
STATUS ONE field. Default Value: 0
STATUS ZERO field. Default Value: 0
STATUS EVEN field. Default Value: 0
STATUS CARRY field. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
308
0x401107C0 CRYPTO_INTR
3.1.39 CRYPTO_INTR
Address = 0x401107C0 Interrupt register Address: 0x401107C0 Retention: Not Retained
Bits SW Access HW Access
Name
7
6
5
4
3
2
1
0
None
RW1C
RW1C
RW1C
RW1C
RW1C
None
RW1S
RW1S
RW1S
RW1S
RW1S
None [7:5]
PR_DATA_AVAI
LABLE
TR_DATA_AVAI
LABLE
TR_INITIALIZED
INSTR_FF_O VERFLOW
INSTR_FF_L
EVEL
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits SW Access HW Access
Name
23
22
21
None
None
None [23:21]
20
19
RW1C
RW1C
RW1S
RW1S
TR_RC_DE-
TECT_ERR OR
TR_AP_DETECT_ER-
ROR
18 RW1C RW1S
BUS_ERROR
17 RW1C RW1S
16 RW1C RW1S
INSTR_C- INSTR_OPC_ERROR C_ERROR
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
Description
20
TR_RC_DETECT_ER-
This interrupt cause is activated (HW sets the field to '1') when the true random number gener-
ROR
ator monitor adaptive proportion test detects a disproportionate occurrence of a specific bit val-
ue.
Default Value: 0
19
TR_AP_DETECT_ER-
This interrupt cause is activated (HW sets the field to '1') when the true random number gener-
ROR
ator monitor adaptive proportion test detects a repetition of a specific bit value.
Default Value: 0
18
BUS_ERROR
This interrupt cause is activated (HW sets the field to '1') when a AHB-Lite bus error is observed on the AHB-Lite master interface. Default Value: 0
17
INSTR_CC_ERROR
This interrupt cause is activated (HW sets the field to '1') when the instruction decoder encoun-
ters an instruction with a non-defined condition code. This error is only generated for VU instruc-
tions.
Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
309
0x401107C0 CRYPTO_INTR
3.1.39
16 4 3 2 1 0
CRYPTO_INTR (continued)
INSTR_OPC_ERROR PR_DATA_AVAILABLE TR_DATA_AVAILABLE TR_INITIALIZED INSTR_FF_OVERFLOW INSTR_FF_LEVEL
This interrupt cause is activated (HW sets the field to '1') when the instruction decoder encounters an instruction with a non-defined operation code (opcode). Default Value: 0
This interrupt cause is activated (HW sets the field to '1') when the pseudo random number generator has generated a data value. Default Value: 0
This interrupt cause is activated (HW sets the field to '1') when the true random number generator has generated a data value of the specified bit size. Default Value: 0
This interrupt cause is activated (HW sets the field to '1') when the true random number generator is initialized. Default Value: 0
This interrupt cause is activated (HW sets the field to '1') when the instruction FIFO overflows (an attempt is made to write to a full FIFO). Default Value: 0
This interrupt cause is activated (HW sets the field to '1') when the instruction FIFO event is activated. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
310
0x401107C4 CRYPTO_INTR_SET
3.1.40 CRYPTO_INTR_SET
Address = 0x401107C4 Interrupt set register Address: 0x401107C4 Retention: Not Retained
Bits SW Access HW Access
Name
7
6
5
None
None
None [7:5]
Bits SW Access HW Access
Name
Bits SW Access HW Access
Name
15
14
13
23
22
21
None
None
None [23:21]
Bits
31
30
29
SW Access
HW Access
Name
4
RW1S
A
PR_DATA_AVAI
LABLE
3
RW1S
A
TR_DATA_AVAI
LABLE
2 RW1S
A
TR_INITIALIZED
1
RW1S
A
INSTR_FF_O VERFLOW
0
RW1S
A
INSTR_FF_L
EVEL
12
11
10
9
8
None
None
None [15:8]
20
19
RW1S
RW1S
A
A
TR_RC_DE-
TECT_ERR OR
TR_AP_DETECT_ER-
ROR
18 RW1S
A
BUS_ERROR
17 RW1S
A
16 RW1S
A
INSTR_C- INSTR_OPC_ERROR C_ERROR
28
27
26
25
24
None
None
None [31:24]
Bits
Name
Description
20
TR_RC_DETECT_ER-
SW writes a '1' to this field to set the corresponding field in interrupt request register.
ROR
Default Value: 0
19
TR_AP_DETECT_ER-
SW writes a '1' to this field to set the corresponding field in interrupt request register.
ROR
Default Value: 0
18
BUS_ERROR
SW writes a '1' to this field to set the corresponding field in interrupt request register. Default Value: 0
17
INSTR_CC_ERROR
SW writes a '1' to this field to set the corresponding field in interrupt request register.
Default Value: 0
16
INSTR_OPC_ERROR
SW writes a '1' to this field to set the corresponding field in interrupt request register.
Default Value: 0
4
PR_DATA_AVAILABLE SW writes a '1' to this field to set the corresponding field in interrupt request register.
Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
311
0x401107C4 CRYPTO_INTR_SET
3.1.40
3 2 1 0
CRYPTO_INTR_SET (continued)
TR_DATA_AVAILABLE TR_INITIALIZED INSTR_FF_OVERFLOW INSTR_FF_LEVEL
SW writes a '1' to this field to set the corresponding field in interrupt request register. Default Value: 0
SW writes a '1' to this field to set the corresponding field in interrupt request register. Default Value: 0
SW writes a '1' to this field to set the corresponding field in interrupt request register. Default Value: 0
SW writes a '1' to this field to set the corresponding field in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
312
0x401107C8 CRYPTO_INTR_MASK
3.1.41 CRYPTO_INTR_MASK
Address = 0x401107C8 Interrupt mask register Address: 0x401107C8 Retention: Retained
Bits SW Access HW Access
Name
7
6
5
None
None
None [7:5]
Bits SW Access HW Access
Name
Bits SW Access HW Access
Name
15
14
13
23
22
21
None
None
None [23:21]
Bits
31
30
29
SW Access
HW Access
Name
4
RW
R
PR_DATA_AVAI
LABLE
3
RW
R
TR_DATA_AVAI
LABLE
2 RW R
TR_INITIALIZED
1
RW
R
INSTR_FF_O VERFLOW
0
RW
R
INSTR_FF_L
EVEL
12
11
10
9
8
None
None
None [15:8]
20
19
RW
RW
R
R
TR_RC_DE-
TECT_ERR OR
TR_AP_DETECT_ER-
ROR
18 RW R
BUS_ERROR
17
16
RW
RW
R
R
INSTR_C- INSTR_OPC_ERROR C_ERROR
28
27
26
25
24
None
None
None [31:24]
Bits
Name
Description
20
TR_RC_DETECT_ER-
Mask bit for corresponding field in interrupt request register.
ROR
Default Value: 0
19
TR_AP_DETECT_ER-
Mask bit for corresponding field in interrupt request register.
ROR
Default Value: 0
18
BUS_ERROR
Mask bit for corresponding field in interrupt request register. Default Value: 0
17
INSTR_CC_ERROR
Mask bit for corresponding field in interrupt request register.
Default Value: 0
16
INSTR_OPC_ERROR
Mask bit for corresponding field in interrupt request register.
Default Value: 0
4
PR_DATA_AVAILABLE Mask bit for corresponding field in interrupt request register.
Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
313
0x401107C8 CRYPTO_INTR_MASK
3.1.41
3 2 1 0
CRYPTO_INTR_MASK (continued)
TR_DATA_AVAILABLE TR_INITIALIZED INSTR_FF_OVERFLOW INSTR_FF_LEVEL
Mask bit for corresponding field in interrupt request register. Default Value: 0
Mask bit for corresponding field in interrupt request register. Default Value: 0
Mask bit for corresponding field in interrupt request register. Default Value: 0
Mask bit for corresponding field in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
314
0x401107CC CRYPTO_INTR_MASKED
3.1.42 CRYPTO_INTR_MASKED
Address = 0x401107CC Interrupt masked register Address: 0x401107CC Retention: Not Retained
Bits SW Access HW Access
Name
7
6
5
4
3
2
1
0
None
R
R
R
R
R
None
W
W
W
W
W
None [7:5]
PR_DATA_AVAI
LABLE
TR_DATA_AVAI
LABLE
TR_INITIALIZED
INSTR_FF_O VERFLOW
INSTR_FF_L
EVEL
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits SW Access HW Access
Name
23
22
21
None
None
None [23:21]
20
19
R
R
W
W
TR_RC_DE-
TECT_ERR OR
TR_AP_DETECT_ER-
ROR
18 R W
BUS_ERROR
17
16
R
R
W
W
INSTR_C- INSTR_OPC_ERROR C_ERROR
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
Description
20
TR_RC_DETECT_ER-
Logical and of corresponding request and mask bits.
ROR
Default Value: 0
19
TR_AP_DETECT_ER-
Logical and of corresponding request and mask bits.
ROR
Default Value: 0
18
BUS_ERROR
Logical and of corresponding request and mask bits. Default Value: 0
17
INSTR_CC_ERROR
Logical and of corresponding request and mask bits.
Default Value: 0
16
INSTR_OPC_ERROR
Logical and of corresponding request and mask bits.
Default Value: 0
4
PR_DATA_AVAILABLE Logical and of corresponding request and mask bits.
Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
315
0x401107CC CRYPTO_INTR_MASKED
3.1.42
3 2 1 0
CRYPTO_INTR_MASKED (continued)
TR_DATA_AVAILABLE TR_INITIALIZED INSTR_FF_OVERFLOW INSTR_FF_LEVEL
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
316
0x40114000 CRYPTO_MEM_BUFF0
3.1.43 CRYPTO_MEM_BUFF0
Address = 0x40114000 Memory buffer Address: 0x40114000 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
DATA32 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
RW
Name
DATA32 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
RW
Name
DATA32 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
RW
Name
DATA32 [31:24]
Bits 31 : 0
Name DATA32
Description Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
317
Section D:Peripheral Group 2
This section encompasses the following chapters: CPU Sub System (CPUSS) Registers chapter on page 319 Fault Registers chapter on page 358 Inter-Processor Communication Registers chapter on page 377 Protection Unit Registers chapter on page 391 Flash Controller Registers chapter on page 432 System Resources Subsystem Registers chapter on page 519 Multi-Counter WDT (MCWDT) Registers chapter on page 599 Backup System Registers chapter on page 614 Direct Memory Access (DMA) Registers chapter on page 640 eFuse Registers chapter on page 673 Profiler Registers chapter on page 681
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
318
4 CPU Sub System (CPUSS) Registers
This section discusses the CPU Sub System (CPUSS) registers. It lists all the registers in mapping tables, in address order.
4.1 Register Details
Register CPUSS_CM0_CTL CPUSS_CM0_STATUS CPUSS_CM0_CLOCK_CTL CPUSS_CM0_INT_CTL0 CPUSS_CM0_INT_CTL1 CPUSS_CM0_INT_CTL2 CPUSS_CM0_INT_CTL3 CPUSS_CM0_INT_CTL4 CPUSS_CM0_INT_CTL5 CPUSS_CM0_INT_CTL6 CPUSS_CM0_INT_CTL7 CPUSS_CM4_PWR_CTL CPUSS_CM4_PWR_DELAY_CTL CPUSS_CM4_STATUS CPUSS_CM4_CLOCK_CTL CPUSS_CM4_NMI_CTL CPUSS_RAM0_CTL0 CPUSS_RAM0_PWR_MACRO_CTL0 CPUSS_RAM0_PWR_MACRO_CTL1 CPUSS_RAM0_PWR_MACRO_CTL2 CPUSS_RAM0_PWR_MACRO_CTL3 CPUSS_RAM0_PWR_MACRO_CTL4 CPUSS_RAM0_PWR_MACRO_CTL5 CPUSS_RAM0_PWR_MACRO_CTL6 CPUSS_RAM0_PWR_MACRO_CTL7 CPUSS_RAM0_PWR_MACRO_CTL8 CPUSS_RAM_PWR_DELAY_CTL
Address 0x40210000 0x40210008 0x40210010 0x40210020 0x40210024 0x40210028 0x4021002C 0x40210030 0x40210034 0x40210038 0x4021003C 0x40210080 0x40210084 0x40210088 0x40210090 0x402100A0 0x40210100 0x40210140 0x40210144 0x40210148 0x4021014C 0x40210150 0x40210154 0x40210158 0x4021015C 0x40210160 0x402101C0
Description CM0+ control CM0+ status CM0+ clock control CM0+ interrupt control 0 CM0+ interrupt control 1 CM0+ interrupt control 2 CM0+ interrupt control 3 CM0+ interrupt control 4 CM0+ interrupt control 5 CM0+ interrupt control 6 CM0+ interrupt control 7 CM4 power control CM4 power control CM4 status CM4 clock control CM4 NMI control RAM 0 control 0 RAM 0 power control RAM 0 power control. See CPUSS_RAM0_PWR_MACRO_CTL0 for the details of bit fields. RAM 0 power control. See CPUSS_RAM0_PWR_MACRO_CTL0 for the details of bit fields. RAM 0 power control. See CPUSS_RAM0_PWR_MACRO_CTL0 for the details of bit fields. RAM 0 power control. See CPUSS_RAM0_PWR_MACRO_CTL0 for the details of bit fields. RAM 0 power control. See CPUSS_RAM0_PWR_MACRO_CTL0 for the details of bit fields. RAM 0 power control. See CPUSS_RAM0_PWR_MACRO_CTL0 for the details of bit fields. RAM 0 power control. See CPUSS_RAM0_PWR_MACRO_CTL0 for the details of bit fields. RAM 0 power control. See CPUSS_RAM0_PWR_MACRO_CTL0 for the details of bit fields. Power up delay used for all SRAM power domains
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
319
CPU Sub System (CPUSS) Registers
Register CPUSS_ROM_CTL CPUSS_UDB_PWR_CTL CPUSS_UDB_PWR_DELAY_CTL CPUSS_DP_STATUS CPUSS_BUFF_CTL CPUSS_SYSTICK_CTL CPUSS_CM0_VECTOR_TABLE_BASE CPUSS_CM4_VECTOR_TABLE_BASE CPUSS_CM0_PC0_HANDLER CPUSS_IDENTITY CPUSS_PROTECTION CPUSS_CM0_NMI_CTL CPUSS_MBIST_STAT CPUSS_TRIM_ROM_CTL CPUSS_TRIM_RAM_CTL
Address 0x402101D0 0x402101F0 0x402101F4 0x40210208 0x40210220 0x40210240 0x402102B0 0x402102C0 0x40210320 0x40210400 0x40210500 0x40210520 0x402105A0 0x4021F000 0x4021F004
ROM control UDB power control UDB power control Debug port status Buffer control SysTick timer control CM0+ vector table base CM4 vector table base CM0+ protection context 0 handler Identity Protection status CM0+ NMI control Memory BIST status ROM trim control RAM trim control
Description
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
320
CPUSS_CM0_CTL
4.1.1 CPUSS_CM0_CTL
Address = 0x40210000 CM0+ control Address: 0x40210000 Retention: Retained
Bits
7
6
SW Access
HW Access
Name
Bits
15
14
SW Access
HW Access
Name
Bits
23
22
SW Access
HW Access
Name
Bits
31
30
SW Access
HW Access
Name
5
4
3
None
None
None [7:2]
13
12
11
None
None
None [15:8]
21
20
19
R
VECTKEYSTAT [23:16]
29
28
27
R
VECTKEYSTAT [31:24]
2
1
0
RW
RW
RW1S
R
ENABLED SLV_STALL
10
9
8
18
17
16
26
25
24
Bits 31 : 16
Name VECTKEYSTAT
1
ENABLED
Description
Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Default Value: 64005
Processor enable: '0': Disabled. Processor clock is turned off and reset is activated. After SW clears this field to '0', HW automatically sets this field to '1'. This effectively results in a CM0+ reset, followed by a CM0+ warm boot. '1': Enabled. Note: The intent is that this bit is modified only through an external probe or by the CM4 while the CM0+ is in Sleep or DeepSleep power mode. If this field is cleared to '0' by the CM0+ itself, it should be done under controlled conditions (such that undesirable side effects can be prevented). Note: The CM0+ CPU has a AIRCR.SYSRESETREQ register field that allows the CM0+ to reset the complete device (ENABLED only disables/enables the CM0+), resulting in a warm boot. This CPU register field has similar "built-in protection" as this CM0_CTL register to prevent accidental system writes (the upper 16-bits of the register need to be written with a 0x05fa key value; see CPU user manual for more details). Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
321
CPUSS_CM0_CTL
4.1.1
0
CPUSS_CM0_CTL (continued)
SLV_STALL
Processor debug access control: '0': Access. '1': Stall access. This field is used to stall/delay debug accesses. This is useful to protect execution of code that needs to be protected from debug accesses. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
322
CPUSS_CM0_STATUS
4.1.2 CPUSS_CM0_STATUS
Address = 0x40210008 CM0+ status Address: 0x40210008 Retention: Not Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:2]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
0
R
R
W
W
SLEEPDEEP
SLEEPING
10
9
8
18
17
16
26
25
24
Bits
Name
1
SLEEPDEEP
0
SLEEPING
Description
Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field. Default Value: 0
Specifies if the CPU is in Active, Sleep or DeepSleep power mode: - Active power mode: SLEEPING is '0'. - Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'. - DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
323
CPUSS_CM0_CLOCK_CTL
4.1.3 CPUSS_CM0_CLOCK_CTL
Address = 0x40210010 CM0+ clock control Address: 0x40210010 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
SLOW_INT_DIV [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
PERI_INT_DIV [31:24]
Bits 31 : 24
Name PERI_INT_DIV
15 : 8
SLOW_INT_DIV
Description
Specifies the peripheral clock divider (from the high frequency clock "clk_hf" to the peripheral clock "clk_peri"). Integer division by (1+PERI_INT_DIV). Allows for integer divisions in the range [1, 256] (PERI_INT_DIV is in the range [0, 255]).
Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to "0" when transitioning from DeepSleep to Active power mode. Note that Fperi <= Fperi_max. Fperi_max is likely to be smaller than Fhf_max. In other words, if Fhf = Fhf_max, PERI_INT_DIV should not be set to "0". Default Value: 1
Specifies the slow clock divider (from the peripheral clock "clk_peri" to the slow clock "clk_slow"). Integer division by (1+SLOW_INT_DIV). Allows for integer divisions in the range [1, 256] (SLOW_INT_DIV is in the range [0, 255]).
Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to "0" when transitioning from DeepSleep to Active power mode. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
324
CPUSS_CM0_INT_CTL0
4.1.4 CPUSS_CM0_INT_CTL0
Address = 0x40210020 CM0+ interrupt control 0 Address: 0x40210020 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
MUX0_SEL [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
MUX1_SEL [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
MUX2_SEL [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
MUX3_SEL [31:24]
Bits 31 : 24 23 : 16 15 : 8 7 : 0
Name MUX3_SEL MUX2_SEL MUX1_SEL MUX0_SEL
Description
System interrupt select for CPU interrupt source 3. Default Value: 240
System interrupt select for CPU interrupt source 2. Default Value: 240
System interrupt select for CPU interrupt source 1. Default Value: 240
System interrupt select for CPU interrupt source 0. If the field value is 240, no system interrupt is connected and the CPU interrupt source is always '0'/de-activated. Default Value: 240
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
325
CPUSS_CM0_INT_CTL1
4.1.5 CPUSS_CM0_INT_CTL1
Address = 0x40210024 CM0+ interrupt control 1 Address: 0x40210024 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
MUX0_SEL [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
MUX1_SEL [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
MUX2_SEL [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
MUX3_SEL [31:24]
Bits 31 : 24 23 : 16 15 : 8 7 : 0
Name MUX3_SEL MUX2_SEL MUX1_SEL MUX0_SEL
Description
System interrupt select for CPU interrupt source 7. Default Value: 240
System interrupt select for CPU interrupt source 6. Default Value: 240
System interrupt select for CPU interrupt source 5. Default Value: 240
System interrupt select for CPU interrupt source 4. Default Value: 240
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
326
CPUSS_CM0_INT_CTL2
4.1.6 CPUSS_CM0_INT_CTL2
Address = 0x40210028 CM0+ interrupt control 2 Address: 0x40210028 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
MUX0_SEL [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
MUX1_SEL [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
MUX2_SEL [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
MUX3_SEL [31:24]
Bits 31 : 24 23 : 16 15 : 8 7 : 0
Name MUX3_SEL MUX2_SEL MUX1_SEL MUX0_SEL
Description
System interrupt select for CPU interrupt source 11. Default Value: 240
System interrupt select for CPU interrupt source 10. Default Value: 240
System interrupt select for CPU interrupt source 9. Default Value: 240
System interrupt select for CPU interrupt source 8. Default Value: 240
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
327
CPUSS_CM0_INT_CTL3
4.1.7 CPUSS_CM0_INT_CTL3
Address = 0x4021002C CM0+ interrupt control 3 Address: 0x4021002C Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
MUX0_SEL [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
MUX1_SEL [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
MUX2_SEL [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
MUX3_SEL [31:24]
Bits 31 : 24 23 : 16 15 : 8 7 : 0
Name MUX3_SEL MUX2_SEL MUX1_SEL MUX0_SEL
Description
System interrupt select for CPU interrupt source 15. Default Value: 240
System interrupt select for CPU interrupt source 14. Default Value: 240
System interrupt select for CPU interrupt source 13. Default Value: 240
System interrupt select for CPU interrupt source 12. Default Value: 240
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
328
CPUSS_CM0_INT_CTL4
4.1.8 CPUSS_CM0_INT_CTL4
Address = 0x40210030 CM0+ interrupt control 4 Address: 0x40210030 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
MUX0_SEL [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
MUX1_SEL [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
MUX2_SEL [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
MUX3_SEL [31:24]
Bits 31 : 24 23 : 16 15 : 8 7 : 0
Name MUX3_SEL MUX2_SEL MUX1_SEL MUX0_SEL
Description
System interrupt select for CPU interrupt source 19. Default Value: 240
System interrupt select for CPU interrupt source 18. Default Value: 240
System interrupt select for CPU interrupt source 17. Default Value: 240
System interrupt select for CPU interrupt source 16. Default Value: 240
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
329
CPUSS_CM0_INT_CTL5
4.1.9 CPUSS_CM0_INT_CTL5
Address = 0x40210034 CM0+ interrupt control 5 Address: 0x40210034 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
MUX0_SEL [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
MUX1_SEL [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
MUX2_SEL [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
MUX3_SEL [31:24]
Bits 31 : 24 23 : 16 15 : 8 7 : 0
Name MUX3_SEL MUX2_SEL MUX1_SEL MUX0_SEL
Description
System interrupt select for CPU interrupt source 23. Default Value: 240
System interrupt select for CPU interrupt source 22. Default Value: 240
System interrupt select for CPU interrupt source 21. Default Value: 240
System interrupt select for CPU interrupt source 20. Default Value: 240
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
330
CPUSS_CM0_INT_CTL6
4.1.10 CPUSS_CM0_INT_CTL6
Address = 0x40210038 CM0+ interrupt control 6 Address: 0x40210038 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
MUX0_SEL [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
MUX1_SEL [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
MUX2_SEL [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
MUX3_SEL [31:24]
Bits 31 : 24 23 : 16 15 : 8 7 : 0
Name MUX3_SEL MUX2_SEL MUX1_SEL MUX0_SEL
Description
System interrupt select for CPU interrupt source 27. Default Value: 240
System interrupt select for CPU interrupt source 26. Default Value: 240
System interrupt select for CPU interrupt source 25. Default Value: 240
System interrupt select for CPU interrupt source 24. Default Value: 240
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
331
CPUSS_CM0_INT_CTL7
4.1.11 CPUSS_CM0_INT_CTL7
Address = 0x4021003C CM0+ interrupt control 7 Address: 0x4021003C Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
MUX0_SEL [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
MUX1_SEL [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
MUX2_SEL [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
MUX3_SEL [31:24]
Bits 31 : 24 23 : 16 15 : 8 7 : 0
Name MUX3_SEL MUX2_SEL MUX1_SEL MUX0_SEL
Description
System interrupt select for CPU interrupt source 31. Default Value: 240
System interrupt select for CPU interrupt source 30. Default Value: 240
System interrupt select for CPU interrupt source 29. Default Value: 240
System interrupt select for CPU interrupt source 28. Default Value: 240
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
332
CPUSS_CM4_PWR_CTL
4.1.12 CPUSS_CM4_PWR_CTL
Address = 0x40210080 CM4 power control Address: 0x40210080 Retention: Retained
Bits
7
6
5
4
3
2
SW Access
None
HW Access
None
Name
None [7:2]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
SW Access
R
HW Access
Name
VECTKEYSTAT [23:16]
Bits
31
30
29
28
27
26
SW Access
R
HW Access
Name
VECTKEYSTAT [31:24]
1
0
RW
R
PWR_MODE [1:0]
9
8
17
16
25
24
Bits 31 : 16
Name VECTKEYSTAT
1 : 0
PWR_MODE
Description
Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Default Value: 64005
Set Power mode for CM4 Default Value: 1
0x0: OFF : Switch CM4 offPower off, clock off, isolate, reset and no retain.
0x1: RESET : Reset CM4 Clock off, no isolated, no retain and reset. Note: The CM4 CPU has a AIRCR.SYSRESETREQ register field that allows the CM4 to reset the complete device (RESET only resets the CM4), resulting in a warm boot.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
333
CPUSS_CM4_PWR_CTL
4.1.12
CPUSS_CM4_PWR_CTL (continued)
0x2: RETAINED : Put CM4 in Retained mode This can only become effective if CM4 is in SleepDeep mode. Check PWR_DONE flag to see if CM4 RETAINED state has been reached. Power off, clock off, isolate, no reset and retain.
0x3: ENABLED : Switch CM4 on. Power on, clock on, no isolate, no reset and no retain.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
334
CPUSS_CM4_PWR_DELAY_CTL
4.1.13 CPUSS_CM4_PWR_DELAY_CTL
Address = 0x40210084 CM4 power control Address: 0x40210084 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
UP [7:0]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:10]
9
8
RW
R
UP [9:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 9 : 0
Name UP
Description
Number clock cycles delay needed after power domain power up Default Value: 300
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
335
CPUSS_CM4_STATUS
4.1.14 CPUSS_CM4_STATUS
Address = 0x40210088 CM4 status Address: 0x40210088 Retention: Not Retained
Bits SW Access HW Access
Name
7
6
5
None
None
None [7:5]
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4
R
W
PWR_DONE
3
2
None
None
None [3:2]
12
11
10
None
None
None [15:8]
20
19
18
None
None
None [23:16]
28
27
26
None
None
None [31:24]
1 R W SLEEPDEEP
9
0 R W SLEEPING
8
17
16
25
24
Bits
Name
4
PWR_DONE
1
SLEEPDEEP
0
SLEEPING
Description
After a PWR_MODE change this flag indicates if the new power mode has taken effect or not. Note: this flag can also change as a result of a change in debug power up req Default Value: 1
Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field. Default Value: 1
Specifies if the CPU is in Active, Sleep or DeepSleep power mode: - Active power mode: SLEEPING is '0'. - Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'. - DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'. Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
336
CPUSS_CM4_CLOCK_CTL
4.1.15 CPUSS_CM4_CLOCK_CTL
Address = 0x40210090 CM4 clock control Address: 0x40210090 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
FAST_INT_DIV [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 8
Name FAST_INT_DIV
Description
Specifies the fast clock divider (from the high frequency clock "clk_hf" to the peripheral clock "clk_fast"). Integer division by (1+FAST_INT_DIV). Allows for integer divisions in the range [1, 256] (FAST_INT_DIV is in the range [0, 255]).
Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to "0" when transitioning from DeepSleep to Active power mode. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
337
CPUSS_CM4_NMI_CTL
4.1.16 CPUSS_CM4_NMI_CTL
Address = 0x402100A0 CM4 NMI control Address: 0x402100A0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
MUX0_SEL [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 0
Name MUX0_SEL
Description
System interrupt select for CPU NMI. The reset value ensure that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset. Default Value: 240
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
338
CPUSS_RAM0_CTL0
4.1.17 CPUSS_RAM0_CTL0
Address = 0x40210100 RAM 0 control 0 Address: 0x40210100 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:2]
SLOW_WS [1:0]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:10]
9
8
RW
R
FAST_WS [9:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 9 : 8
1 : 0
Name FAST_WS
SLOW_WS
Description
Memory wait states for the fast clock domain ("clk_fast"). The number of wait states is expressed in "clk_hf" clock domain cycles. Default Value: 0
Memory wait states for the slow clock domain ("clk_slow"). The number of wait states is expressed in "clk_hf" clock domain cycles. Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
339
CPUSS_RAM0_PWR_MACRO_CTL0
4.1.18 CPUSS_RAM0_PWR_MACRO_CTL0
Address = 0x40210140 RAM 0 power control Address: 0x40210140 Retention: Retained
Bits
7
6
5
4
3
2
SW Access
None
HW Access
None
Name
None [7:2]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
SW Access
R
HW Access
Name
VECTKEYSTAT [23:16]
Bits
31
30
29
28
27
26
SW Access
R
HW Access
Name
VECTKEYSTAT [31:24]
1
0
RW
R
PWR_MODE [1:0]
9
8
17
16
25
24
Bits 31 : 16
Name VECTKEYSTAT
1 : 0
PWR_MODE
Description
Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Default Value: 64005
Set Power mode for 1 SRAM0 Macro Default Value: 3
0x0: OFF : See CM4_PWR_CTL
0x1: RESERVED : undefined
0x2: RETAINED : See CM4_PWR_CTL
0x3: ENABLED : See CM4_PWR_CTL
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
340
CPUSS_RAM_PWR_DELAY_CTL
4.1.19 CPUSS_RAM_PWR_DELAY_CTL
Address = 0x402101C0 Power up delay used for all SRAM power domains Address: 0x402101C0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
UP [7:0]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:10]
9
8
RW
R
UP [9:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 9 : 0
Name UP
Description
Number clock cycles delay needed after power domain power up Default Value: 150
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
341
CPUSS_ROM_CTL
4.1.20 CPUSS_ROM_CTL
Address = 0x402101D0 ROM control Address: 0x402101D0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:2]
SLOW_WS [1:0]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:10]
9
8
RW
R
FAST_WS [9:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 9 : 8
1 : 0
Name FAST_WS
SLOW_WS
Description
Memory wait states for the fast clock domain ("clk_fast"). The number of wait states is expressed in "clk_hf" clock domain cycles. Default Value: 0
Memory wait states for the slow clock domain ("clk_slow"). The number of wait states is expressed in "clk_hf" clock domain cycles. Timing paths to and from the memory have a (fixed) minimum duration that always needs to be considered/met. The "clk_hf" clock domain frequency determines this field's value such that the timing paths minimum duration is met. A table/formula will be provided for this field's values for different "clk_hf" frequencies. Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
342
CPUSS_UDB_PWR_CTL
4.1.21 CPUSS_UDB_PWR_CTL
Address = 0x402101F0 UDB power control Address: 0x402101F0 Retention: Retained
Bits
7
6
5
4
3
2
SW Access
None
HW Access
None
Name
None [7:2]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
SW Access
R
HW Access
Name
VECTKEYSTAT [23:16]
Bits
31
30
29
28
27
26
SW Access
R
HW Access
Name
VECTKEYSTAT [31:24]
1
0
RW
R
PWR_MODE [1:0]
9
8
17
16
25
24
Bits 31 : 16
Name VECTKEYSTAT
1 : 0
PWR_MODE
Description
Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Default Value: 64005
Set Power mode for UDBs Default Value: 1
0x0: OFF : See CM4_PWR_CTL
0x1: RESET : See CM4_PWR_CTL
0x2: RETAINED : See CM4_PWR_CTL
0x3: ENABLED : See CM4_PWR_CTL
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
343
CPUSS_UDB_PWR_DELAY_CTL
4.1.22 CPUSS_UDB_PWR_DELAY_CTL
Address = 0x402101F4 UDB power control Address: 0x402101F4 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
UP [7:0]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:10]
9
8
RW
R
UP [9:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 9 : 0
Name UP
Description
Number clock cycles delay needed after power domain power up Default Value: 300
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
344
CPUSS_DP_STATUS
4.1.23 CPUSS_DP_STATUS
Address = 0x40210208 Debug port status Address: 0x40210208 Retention: Not Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:3]
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4
3
12
11
None
None
None [15:8]
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
2
R
W
SWJ_JTAG_SEL
1
R
W
SWJ_DEBUG_EN
0
R
W
SWJ_CONNECTED
10
9
8
18
17
16
26
25
24
Bits
Name
Description
2
SWJ_JTAG_SEL
Specifies if the JTAG or SWD interface is selected. This signal is valid when DP_CTL.PTM_SEL
is '0' (SWJ mode selected) and SWJ_CONNECTED is '1' (SWJ is connected).
'0': SWD selected.
'1': JTAG selected.
Default Value: 1
1
SWJ_DEBUG_EN
Specifies if SWJ debug is enabled, i.e. CDBGPWRUPACK is '1' and thus debug clocks are on:
'0': Disabled.
'1': Enabled.
Default Value: 0
0
SWJ_CONNECTED
Specifies if the SWJ debug port is connected; i.e. debug host interface is active:
'0': Not connected/not active.
'1': Connected/active.
Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
345
CPUSS_BUFF_CTL
4.1.24 CPUSS_BUFF_CTL
Address = 0x40210220 Buffer control Address: 0x40210220 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:1]
WRITE_BU FF
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
WRITE_BUFF
Description
Specifies if write transfer can be buffered in the bus infrastructure bridges: '0': Write transfers are not buffered, independent of the transfer's bufferable attribute. '1': Write transfers can be buffered, if the transfer's bufferable attribute indicates that the transfer is a bufferable/posted write. Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
346
CPUSS_SYSTICK_CTL
4.1.25 CPUSS_SYSTICK_CTL
Address = 0x40210240 SysTick timer control Address: 0x40210240 Retention: Retained
Bits
7
6
5
SW Access
HW Access
Name
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
RW
RW
HW Access
R
R
Name
NOREF
SKEW
4
3
RW
R
TENMS [7:0]
12
11
RW
R
TENMS [15:8]
20
19
RW
R
TENMS [23:16]
28
27
None
None
None [29:26]
2
1
0
10
9
8
18
17
16
26
25
24
RW
R
CLOCK_SOURCE [25:24]
Bits
Name
31
NOREF
30
SKEW
Description
Specifies if an external clock source is provided: '0': An external clock source is provided. '1': An external clock source is NOT provided and only the CPU internal clock can be used as SysTick timer clock source. Default Value: 0
Specifies the precision of the clock source and if the TENMS field represents exactly 10 ms (clock source frequency is a multiple of 100 Hz). This affects the suitability of the SysTick timer as a SW real-time clock: 0: Precise. 1: Imprecise. Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
347
CPUSS_SYSTICK_CTL
25 : 24
CLOCK_SOURCE
23 : 0
TENMS
Specifies an external clock source: 0: The low frequency clock clk_lf is selected. The precision of this clock depends on whether the low frequency clock source is a SRSS internal RC oscillator (imprecise) or a device external crystal oscillator (precise). 1: The internal main oscillator (IMO) clock clk_imo is selected. o 2: The external crystal oscillator (ECO) clock clk_eco is selected. 3: The SRSS "clk_timer" is selected ("clk_timer" is a divided/gated version of "clk_hf" or "clk_imo"). Note: If NOREF is 1, the CLOCK_SOURCE value is NOT used. Note: It is SWs responsibility to provide the correct NOREF, SKEW and TENMS field values for the selected clock source. Default Value: 0
Specifies the number of clock source cycles (minus 1) that make up 10 ms. E.g., for a 32,768 Hz reference clock, TENMS is 328 1 = 327. Default Value: 327
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
348
CPUSS_CM0_VECTOR_TABLE_BASE
4.1.26 CPUSS_CM0_VECTOR_TABLE_BASE
Address = 0x402102B0 CM0+ vector table base Address: 0x402102B0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
Name
ADDR24 [31:24]
Bits 31 : 8
Name ADDR24
Description
Address of CM0+ vector table. Note: the CM0+ vector table is at an address that is a 256 B multiple. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
349
CPUSS_CM4_VECTOR_TABLE_BASE
4.1.27 CPUSS_CM4_VECTOR_TABLE_BASE
Address = 0x402102C0 CM4 vector table base Address: 0x402102C0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
14
13
12
11
10
SW Access
RW
HW Access
Name
ADDR22 [15:10]
9
8
None
None
None [9:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
Name
ADDR22 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
Name
ADDR22 [31:24]
Bits 31 : 10
Name ADDR22
Description
Address of CM4 vector table. Note: the CM4 vector table is at an address that is a 1024 B multiple. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
350
CPUSS_CM0_PC0_HANDLER
4.1.28 CPUSS_CM0_PC0_HANDLER
Address = 0x40210320 CM0+ protection context 0 handler Address: 0x40210320 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
ADDR [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
ADDR [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
ADDR [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
ADDR [31:24]
Bits 31 : 0
Name ADDR
Description
Address of the protection context 0 handler. This field is used to detect entry to Cypress "trusted" code through an exception/interrupt. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
351
CPUSS_IDENTITY
4.1.29 CPUSS_IDENTITY
Address = 0x40210400 Identity Address: 0x40210400 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
None
R
R
HW Access
W
None
W
W
Name
PC [7:4]
None [3:2]
NS
P
Bits
15
14
13
12
11
10
9
8
SW Access
None
R
HW Access
None
W
Name
None [15:12]
MS [11:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 11 : 8 7 : 4 1
Name MS PC NS
0
P
Description
This field specifies the bus master identifier of the transfer that reads the register. Default Value: Undefined
This field specifies the protection context of the transfer that reads the register. Default Value: Undefined
This field specifies the security setting ('0': secure mode; '1': non-secure mode) of the transfer that reads the register. Default Value: Undefined
This field specifies the privileged setting ('0': user mode; '1': privileged mode) of the transfer that reads the register. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
352
CPUSS_PROTECTION
4.1.30 CPUSS_PROTECTION
Address = 0x40210500 Protection status Address: 0x40210500 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:3]
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4
3
12
11
None
None
None [15:8]
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
2
1
0
RW
R
STATE [2:0]
10
9
8
18
17
16
26
25
24
Bits 2 : 0
Name STATE
Description
Protection state: "0": UNKNOWN. "1": VIRGIN. "2": NORMAL. "3": SECURE. "4": DEAD. The following state transitions are allowed (and enforced by HW): - UNKNOWN => VIRGIN/NORMAL/SECURE/DEAD - NORMAL => DEAD - SECURE => DEAD An attempt to make a NOT allowed state transition will NOT affect this register field. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
353
CPUSS_CM0_NMI_CTL
4.1.31 CPUSS_CM0_NMI_CTL
Address = 0x40210520 CM0+ NMI control Address: 0x40210520 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
MUX0_SEL [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 0
Name MUX0_SEL
Description
System interrupt select for CPU NMI. The reset value ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset. Default Value: 240
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
354
CPUSS_MBIST_STAT
4.1.32 CPUSS_MBIST_STAT
Address = 0x402105A0 Memory BIST status Address: 0x402105A0 Retention: Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:2]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
0
R
R
RW
RW
SFP_FAIL
SFP_READY
10
9
8
18
17
16
26
25
24
Bits
Name
1
SFP_FAIL
0
SFP_READY
Description
Report status of the BIST run, only valid if SFP_READY=1 Default Value: 0
Flag indicating the BIST run is done. Note that after starting a BIST run this flag must be set before a new run can be started. For the first BIST run this will be 0. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
355
CPUSS_TRIM_ROM_CTL
4.1.33 CPUSS_TRIM_ROM_CTL
Address = 0x4021F000 ROM trim control Address: 0x4021F000 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
RW
HW Access
None
R
R
Name
None [7:5]
RME
RM [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 4
3 : 0
Name RME
RM
Description
Read-Write margin enable control. This selects between the default Read-Write margin setting, and the external pin Read-Write margin setting. Default Value: 0
Read-Write margin control. This is used for setting the Read-Write margin. It programs the sense amplifier differential setting and allows the trade off between speed and robustness. - RM[1:0] values control access time and cycle time of the memory. RM[1:0] = "0" is the slowest possible mode of operation for the memory. This setting is required for VDDMIN operation. - RM[3:2] are factory pins reserved for debug mode and should be set to "0". Default Value: 2
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
356
CPUSS_TRIM_RAM_CTL
4.1.34 CPUSS_TRIM_RAM_CTL
Address = 0x4021F004 RAM trim control Address: 0x4021F004 Retention: Retained
Bits SW Access HW Access
Name
7
6
5
RW
R
WPULSE [7:5]
Bits SW Access HW Access
Name
15 None None None
14
13
RW
R
WA [14:12]
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4
3
2
1
0
RW
RW
R
R
RME
RM [3:0]
12
11
10
None
None
None [11:10]
9
8
RW
R
RA [9:8]
20
19
18
17
16
None
None
None [23:16]
28
27
26
25
24
None
None
None [31:24]
Bits 14 : 12
Name WA
9 : 8
RA
7 : 5
WPULSE
4
RME
3 : 0
RM
Description
Write assist enable control (Active High). - WA[1:0] Write Assist pins to control negative voltage on SRAM bitline. Default Value: 6
Read Assist control for WL under-drive. Default Value: 0
Write Assist Pulse to control pulse width of negative voltage on SRAM bitline. Default Value: 0
Read-Write margin enable control. This selects between the default Read-Write margin setting, and the external RM[3:0] Read-Write margin setting. Default Value: 0
Read-Write margin control. This is used for setting the Read-Write margin. It programs the sense amplifier differential setting and allows the trade off between speed and robustness. - RM[1:0] values control access time and cycle time of the memory. RM[1:0] = "0" is the slowest possible mode of operation for the memory. This setting is required for VDDMIN operation. - RM[3:2] are factory pins reserved for debug mode and should be set to "0". Default Value: 2
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
357
5 Fault Registers
This section discusses the Fault registers. It lists all the registers in mapping tables, in address order.
5.1 Register Details
Register FAULT_STRUCT0_CTL FAULT_STRUCT0_STATUS FAULT_STRUCT0_DATA0 FAULT_STRUCT0_DATA1 FAULT_STRUCT0_DATA2 FAULT_STRUCT0_DATA3 FAULT_STRUCT0_PENDING0 FAULT_STRUCT0_PENDING1 FAULT_STRUCT0_PENDING2 FAULT_STRUCT0_MASK0 FAULT_STRUCT0_MASK1 FAULT_STRUCT0_MASK2 FAULT_STRUCT0_INTR FAULT_STRUCT0_INTR_SET FAULT_STRUCT0_INTR_MASK FAULT_STRUCT0_INTR_MASKED FAULT_STRUCT1_CTL FAULT_STRUCT1_STATUS FAULT_STRUCT1_DATA0 FAULT_STRUCT1_DATA1 FAULT_STRUCT1_DATA2 FAULT_STRUCT1_DATA3 FAULT_STRUCT1_PENDING0 FAULT_STRUCT1_PENDING1 FAULT_STRUCT1_PENDING2 FAULT_STRUCT1_MASK0 FAULT_STRUCT1_MASK1
Address 0x40220000 0x4022000C 0x40220010 0x40220014 0x40220018 0x4022001C 0x40220040 0x40220044 0x40220048 0x40220050 0x40220054 0x40220058 0x402200C0 0x402200C4 0x402200C8 0x402200CC 0x40220100 0x4022010C 0x40220110 0x40220114 0x40220118 0x4022011C 0x40220140 0x40220144 0x40220148 0x40220150 0x40220154
Description Fault control Fault status Fault data Fault data. See FAULT_STRUCT0_DATA0 for the details of bit fields. Fault data. See FAULT_STRUCT0_DATA0 for the details of bit fields. Fault data. See FAULT_STRUCT0_DATA0 for the details of bit fields. Fault pending 0 Fault pending 1 Fault pending 2 Fault mask 0 Fault mask 1 Fault mask 2 Interrupt Interrupt set Interrupt mask Interrupt masked Fault control. See FAULT_STRUCT0_CTL for the details of bit fields. Fault status. See FAULT_STRUCT0_STATUS for the details of bit fields. Fault data. See FAULT_STRUCT0_DATA0 for the details of bit fields. Fault data. See FAULT_STRUCT0_DATA0 for the details of bit fields. Fault data. See FAULT_STRUCT0_DATA0 for the details of bit fields. Fault data. See FAULT_STRUCT0_DATA0 for the details of bit fields. Fault pending 0. See FAULT_STRUCT0_PENDING0 for the details of bit fields. Fault pending 1. See FAULT_STRUCT0_PENDING1 for the details of bit fields. Fault pending 2. See FAULT_STRUCT0_PENDING2 for the details of bit fields. Fault mask 0. See FAULT_STRUCT0_MASK0 for the details of bit fields. Fault mask 1. See FAULT_STRUCT0_MASK1 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
358
Fault Registers
Register FAULT_STRUCT1_MASK2 FAULT_STRUCT1_INTR FAULT_STRUCT1_INTR_SET FAULT_STRUCT1_INTR_MASK FAULT_STRUCT1_INTR_MASKED
Address 0x40220158 0x402201C0 0x402201C4 0x402201C8 0x402201CC
Description Fault mask 2. See FAULT_STRUCT0_MASK2 for the details of bit fields. Interrupt. See FAULT_STRUCT0_INTR for the details of bit fields. Interrupt set. See FAULT_STRUCT0_INTR_SET for the details of bit fields. Interrupt mask. See FAULT_STRUCT0_INTR_MASK for the details of bit fields. Interrupt masked. See FAULT_STRUCT0_INTR_MASKED for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
359
FAULT_STRUCT0_CTL
5.1.1 FAULT_STRUCT0_CTL
Address = 0x40220000 Fault control Address: 0x40220000 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:3]
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4
3
12
11
None
None
None [15:8]
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
2
RW
R
RESET_REQ_
EN
1 RW R
OUT_EN
10
9
0 RW R
TR_EN
8
18
17
16
26
25
24
Bits
Name
2
RESET_REQ_EN
1
OUT_EN
Description
Reset request enable: '0': Disabled. '1': Enabled. The output reset request signal "fault_reset_req" reflects STATUS.VALID. This reset causes a warm/soft/core reset. This warm/soft/core reset does not affect the fault logic STATUS, DATA0, ..., DATA3 registers (allowing for post soft reset failure analysis). The "fault_reset_req" signals of the individual fault report structures are combined (logically OR'd) into a single SRSS "fault_reset_req" signal. Default Value: 0
IO output signal enable: '0': Disabled. The IO output signal "fault_out" is '0'. The IO output enable signal "fault_out_en" is '0'. '1': Enabled. The IO output signal "fault_out" reflects STATUS.VALID. The IO output enable signal "fault_out_en" is '1'. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
360
FAULT_STRUCT0_CTL
5.1.1
0
FAULT_STRUCT0_CTL (continued)
TR_EN
Trigger output enable: '0': Disabled. The trigger output "tr_fault" is '0'. '1': Enabled. The trigger output "tr_fault" reflects STATUS.VALID. The trigger can be used to initiate a Datawire transfer of the FAULT data (FAULT_DATA0 through FAULT_DATA3). Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
361
FAULT_STRUCT0_STATUS
5.1.2 FAULT_STRUCT0_STATUS
Address = 0x4022000C Fault status Address: 0x4022000C Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
R
HW Access
None
W
Name
None
IDX [6:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW0C
None
HW Access
RW1S
None
Name
VALID
None [30:24]
Bits
Name
31
VALID
6 : 0
IDX
Description
Valid indication: '0': Invalid. '1': Valid. HW sets this field to '1' when new fault source data is captured. New fault source data is ONLY captured when VALID is '0'. SW can clear this field to '0' when the fault is handled (by SW). Default Value: 0
The fault source index for which fault information is captured in DATA0 through DATA3. The fault information is fault source specific and described below. Note: this register field (and associated fault source data in DATA0 through DATA3) should only be considered valid, when VALID is '1'. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
362
FAULT_STRUCT0_STATUS
5.1.2
FAULT_STRUCT0_STATUS (continued)
0x0: MPU_0 : Bus master 0 MPU/SMPU. DATA0[31:0]: Violating address. DATA1[0]: User read. DATA1[1]: User write. DATA1[2]: User execute. DATA1[3]: Privileged read. DATA1[4]: Privileged write. DATA1[5]: Privileged execute. DATA1[6]: Non-secure. DATA1[11:8]: Master identifier. DATA1[15:12]: Protection context identifier. DATA1[31]: '0' MPU violation; '1': SMPU violation.
0x1: MPU_1 : Bus master 1 MPU. See MPU_0 description.
0x2: MPU_2 : Bus master 2 MPU. See MPU_0 description.
0x3: MPU_3 : Bus master 3 MPU. See MPU_0 description.
0x4: MPU_4 : Bus master 4 MPU. See MPU_0 description.
0x5: MPU_5 : Bus master 5 MPU. See MPU_0 description.
0x6: MPU_6 : Bus master 6 MPU. See MPU_0 description.
0x7: MPU_7 : Bus master 7 MPU. See MPU_0 description.
0x8: MPU_8 : Bus master 8 MPU. See MPU_0 description.
0x9: MPU_9 : Bus master 9 MPU. See MPU_0 description.
0xa: MPU_10 : Bus master 10 MPU. See MPU_0 description.
0xb: MPU_11 : Bus master 11 MPU. See MPU_0 description.
0xc: MPU_12 : Bus master 12 MPU. See MPU_0 description.
0xd: MPU_13 : Bus master 13 MPU. See MPU_0 description.
0xe: MPU_14 : Bus master 14 MPU. See MPU_0 description.
0xf: MPU_15 : Bus master 15 MPU. See MPU_0 description.
0x10: CM4_SYS_MPU : CM4 system bus AHB-Lite interface MPU. See MPU_0 description.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
363
FAULT_STRUCT0_STATUS
5.1.2
FAULT_STRUCT0_STATUS (continued)
0x1c: MS_PPU_0 : Peripheral master interface 0 PPU. DATA0[31:0]: Violating address. DATA1[0]: User read. DATA1[1]: User write. DATA1[2]: User execute. DATA1[3]: Privileged read. DATA1[4]: Privileged write. DATA1[5]: Privileged execute. DATA1[6]: Non-secure. DATA1[11:8]: Master identifier. DATA1[15:12]: Protection context identifier. DATA1[31]: '0': PPU violation, '1': peripheral bus error.
0x1d: MS_PPU_1 : Peripheral master interface 0 PPU. See MS_PPU_0 description.
0x1e: MS_PPU_2 : Peripheral master interface 1 PPU. See MS_PPU_0 description.
0x1f: MS_PPU_3 : Peripheral master interface 2 PPU. See MS_PPU_0 description.
0x20: GROUP_PPU_0 : Peripheral group 0 PPU. DATA0[31:0]: Violating address. DATA1[0]: User read. DATA1[1]: User write. DATA1[2]: User execute. DATA1[3]: Privileged read. DATA1[4]: Privileged write. DATA1[5]: Privileged execute. DATA1[6]: Non-secure. DATA1[11:8]: Master identifier. DATA1[15:12]: Protection context identifier. DATA1[31:30]: "0": PPU violation, "1": timeout detected, "2": peripheral bus error.
0x21: GROUP_PPU_1 : Peripheral group 1 PPU. See GROUP_PPU_0 description.
0x22: GROUP_PPU_2 : Peripheral group 2 PPU. See GROUP_PPU_0 description.
0x23: GROUP_PPU_3 : Peripheral group 3 PPU. See GROUP_PPU_0 description.
0x24: GROUP_PPU_4 : Peripheral group 4 PPU. See GROUP_PPU_0 description.
0x25: GROUP_PPU_5 : Peripheral group 5 PPU. See GROUP_PPU_0 description.
0x26: GROUP_PPU_6 : Peripheral group 6 PPU. See GROUP_PPU_0 description.
0x27: GROUP_PPU_7 : Peripheral group 7 PPU. See GROUP_PPU_0 description.
0x28: GROUP_PPU_8 : Peripheral group 8 PPU. See GROUP_PPU_0 description.
0x29: GROUP_PPU_9 : Peripheral group 9 PPU. See GROUP_PPU_0 description.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
364
FAULT_STRUCT0_STATUS
5.1.2
FAULT_STRUCT0_STATUS (continued)
0x2a: GROUP_PPU_10 : Peripheral group 10 PPU. See GROUP_PPU_0 description.
0x2b: GROUP_PPU_11 : Peripheral group 11 PPU. See GROUP_PPU_0 description.
0x2c: GROUP_PPU_12 : Peripheral group 12 PPU. See GROUP_PPU_0 description.
0x2d: GROUP_PPU_13 : Peripheral group 13 PPU. See GROUP_PPU_0 description.
0x2e: GROUP_PPU_14 : Peripheral group 14 PPU. See GROUP_PPU_0 description.
0x2f: GROUP_PPU_15 : Peripheral group 15 PPU. See GROUP_PPU_0 description.
0x32: FLASHC_MAIN_BUS_ERROR : Flash controller, main interface, bus error: FAULT_DATA0[31:0]: Violating address. FAULT_DATA1[31]: '0': FLASH macro interface bus error; '1': memory hole. FAULT_DATA1[15:12]: Protection context identifier. FAULT_DATA1[11:8]: Master identifier.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
365
FAULT_STRUCT0_DATA0
5.1.3 FAULT_STRUCT0_DATA0
Address = 0x40220010 Fault data Address: 0x40220010 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
DATA [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
DATA [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
W
Name
DATA [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
W
Name
DATA [31:24]
Bits 31 : 0
Name DATA
Description
Captured fault source data. Note: the fault source index STATUS.IDX specifies the format of the DATA registers. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
366
FAULT_STRUCT0_PENDING0
5.1.4 FAULT_STRUCT0_PENDING0
Address = 0x40220040 Fault pending 0 Address: 0x40220040 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
SOURCE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
SOURCE [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
W
Name
SOURCE [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
W
Name
SOURCE [31:24]
Bits 31 : 0
Name SOURCE
Description
This field specifies the following sources: Bit 0: CM0 MPU. Bit 1: CRYPTO MPU. Bit 2: DW 0 MPU. Bit 3: DW 1 MPU. ... Bit 14: CM4 code bus MPU. Bit 15: DAP MPU. Bit 16: CM4 s+G92ystem bus MPU.
Bit 28: Peripheral master interface 0 PPU. Bit 29: Peripheral master interface 1 PPU. Bit 30: Peripheral master interface 2 PPU. Bit 31: Peripheral master interface 3 PPU. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
367
FAULT_STRUCT0_PENDING1
5.1.5 FAULT_STRUCT0_PENDING1
Address = 0x40220044 Fault pending 1 Address: 0x40220044 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
SOURCE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
SOURCE [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
W
Name
SOURCE [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
W
Name
SOURCE [31:24]
Bits 31 : 0
Name SOURCE
Description
This field specifies the following sources: Bit 0: Peripheral group 0 PPU. Bit 1: Peripheral group 1 PPU. Bit 2: Peripheral group 2 PPU. Bit 3: Peripheral group 3 PPU. Bit 4: Peripheral group 4 PPU. Bit 5: Peripheral group 5 PPU. Bit 6: Peripheral group 6 PPU. Bit 7: Peripheral group 7 PPU. ... Bit 15: Peripheral group 15 PPU. Bit 18: Flash controller, main interface, bus error. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
368
FAULT_STRUCT0_PENDING2
5.1.6 FAULT_STRUCT0_PENDING2
Address = 0x40220048 Fault pending 2 Address: 0x40220048 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
SOURCE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
SOURCE [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
W
Name
SOURCE [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
W
Name
SOURCE [31:24]
Bits 31 : 0
Name SOURCE
Description
Reserved. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
369
FAULT_STRUCT0_MASK0
5.1.7 FAULT_STRUCT0_MASK0
Address = 0x40220050 Fault mask 0 Address: 0x40220050 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
SOURCE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
SOURCE [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
SOURCE [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
SOURCE [31:24]
Bits 31 : 0
Name SOURCE
Description
Fault source enables: Bits 31-0: Fault sources 31 to 0. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
370
FAULT_STRUCT0_MASK1
5.1.8 FAULT_STRUCT0_MASK1
Address = 0x40220054 Fault mask 1 Address: 0x40220054 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
SOURCE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
SOURCE [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
SOURCE [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
SOURCE [31:24]
Bits 31 : 0
Name SOURCE
Description
Fault source enables: Bits 31-0: Fault sources 63 to 32. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
371
FAULT_STRUCT0_MASK2
5.1.9 FAULT_STRUCT0_MASK2
Address = 0x40220058 Fault mask 2 Address: 0x40220058 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
SOURCE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
SOURCE [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
SOURCE [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
SOURCE [31:24]
Bits 31 : 0
Name SOURCE
Description
Fault source enables: Bits 31-0: Fault sources 95 to 64. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
372
FAULT_STRUCT0_INTR
5.1.10 FAULT_STRUCT0_INTR
Address = 0x402200C0 Interrupt Address: 0x402200C0 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW1C
HW Access
None
RW1S
Name
None [7:1]
FAULT
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
FAULT
Description
This interrupt cause field is activated (HW sets the field to '1') when an enabled (MASK0/MASK1/ MASK2) pending fault source is captured: - STATUS.VALID is set to '1'. - STATUS.IDX specifies the fault source index. - DATA0 through DATA3 captures the fault source data. SW writes a '1' to these field to clear the interrupt cause to '0'. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
373
FAULT_STRUCT0_INTR_SET
5.1.11 FAULT_STRUCT0_INTR_SET
Address = 0x402200C4 Interrupt set Address: 0x402200C4 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW1S
HW Access
None
A
Name
None [7:1]
FAULT
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
FAULT
Description
SW writes a '1' to this field to set the corresponding field in the INTR register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
374
FAULT_STRUCT0_INTR_MASK
5.1.12 FAULT_STRUCT0_INTR_MASK
Address = 0x402200C8 Interrupt mask Address: 0x402200C8 Retention: Retained
Bits
7
6
5
4
3
2
SW Access
None
HW Access
None
Name
None [7:1]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
FAULT
Description
Mask bit for corresponding field in the INTR register. Default Value: 0
1
0
RW
R
FAULT
9
8
17
16
25
24
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
375
FAULT_STRUCT0_INTR_MASKED
5.1.13 FAULT_STRUCT0_INTR_MASKED
Address = 0x402200CC Interrupt masked Address: 0x402200CC Retention: Not Retained
Bits
7
6
5
4
3
2
SW Access
None
HW Access
None
Name
None [7:1]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
FAULT
Description
Logical and of corresponding INTR and INTR_MASK fields. Default Value: 0
1
0
R
W
FAULT
9
8
17
16
25
24
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
376
6 Inter-Processor Communication Registers
This section discusses the Inter-Processor Communication (IPC) registers. It lists all the registers in mapping tables, in address order.
6.1 Register Details
Register IPC_STRUCT0_ACQUIRE IPC_STRUCT0_RELEASE IPC_STRUCT0_NOTIFY IPC_STRUCT0_DATA IPC_STRUCT0_LOCK_STATUS IPC_STRUCT1_ACQUIRE IPC_STRUCT1_RELEASE IPC_STRUCT1_NOTIFY IPC_STRUCT1_DATA IPC_STRUCT1_LOCK_STATUS IPC_STRUCT2_ACQUIRE IPC_STRUCT2_RELEASE IPC_STRUCT2_NOTIFY IPC_STRUCT2_DATA IPC_STRUCT2_LOCK_STATUS IPC_STRUCT3_ACQUIRE IPC_STRUCT3_RELEASE IPC_STRUCT3_NOTIFY IPC_STRUCT3_DATA IPC_STRUCT3_LOCK_STATUS IPC_STRUCT4_ACQUIRE IPC_STRUCT4_RELEASE IPC_STRUCT4_NOTIFY IPC_STRUCT4_DATA IPC_STRUCT4_LOCK_STATUS IPC_STRUCT5_ACQUIRE
Address 0x40230000 0x40230004 0x40230008 0x4023000C 0x40230010 0x40230020 0x40230024 0x40230028 0x4023002C 0x40230030 0x40230040 0x40230044 0x40230048 0x4023004C 0x40230050 0x40230060 0x40230064 0x40230068 0x4023006C 0x40230070 0x40230080 0x40230084 0x40230088 0x4023008C 0x40230090 0x402300A0
Description IPC acquire IPC release IPC notification IPC data IPC lock status IPC acquire. See IPC_STRUCT0_ACQUIRE for the details of bit fields. IPC release. See IPC_STRUCT0_RELEASE for the details of bit fields. IPC notification. See IPC_STRUCT0_NOTIFY for the details of bit fields. IPC data. See IPC_STRUCT0_DATA for the details of bit fields. IPC lock status. See IPC_STRUCT0_LOCK_STATUS for the details of bit fields. IPC acquire. See IPC_STRUCT0_ACQUIRE for the details of bit fields. IPC release. See IPC_STRUCT0_RELEASE for the details of bit fields. IPC notification. See IPC_STRUCT0_NOTIFY for the details of bit fields. IPC data. See IPC_STRUCT0_DATA for the details of bit fields. IPC lock status. See IPC_STRUCT0_LOCK_STATUS for the details of bit fields. IPC acquire. See IPC_STRUCT0_ACQUIRE for the details of bit fields. IPC release. See IPC_STRUCT0_RELEASE for the details of bit fields. IPC notification. See IPC_STRUCT0_NOTIFY for the details of bit fields. IPC data. See IPC_STRUCT0_DATA for the details of bit fields. IPC lock status. See IPC_STRUCT0_LOCK_STATUS for the details of bit fields. IPC acquire. See IPC_STRUCT0_ACQUIRE for the details of bit fields. IPC release. See IPC_STRUCT0_RELEASE for the details of bit fields. IPC notification. See IPC_STRUCT0_NOTIFY for the details of bit fields. IPC data. See IPC_STRUCT0_DATA for the details of bit fields. IPC lock status. See IPC_STRUCT0_LOCK_STATUS for the details of bit fields. IPC acquire. See IPC_STRUCT0_ACQUIRE for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
377
Inter-Processor Communication Registers
Register IPC_STRUCT5_RELEASE IPC_STRUCT5_NOTIFY IPC_STRUCT5_DATA IPC_STRUCT5_LOCK_STATUS IPC_STRUCT6_ACQUIRE IPC_STRUCT6_RELEASE IPC_STRUCT6_NOTIFY IPC_STRUCT6_DATA IPC_STRUCT6_LOCK_STATUS IPC_STRUCT7_ACQUIRE IPC_STRUCT7_RELEASE IPC_STRUCT7_NOTIFY IPC_STRUCT7_DATA IPC_STRUCT7_LOCK_STATUS IPC_STRUCT8_ACQUIRE IPC_STRUCT8_RELEASE IPC_STRUCT8_NOTIFY IPC_STRUCT8_DATA IPC_STRUCT8_LOCK_STATUS IPC_STRUCT9_ACQUIRE IPC_STRUCT9_RELEASE IPC_STRUCT9_NOTIFY IPC_STRUCT9_DATA IPC_STRUCT9_LOCK_STATUS IPC_STRUCT10_ACQUIRE IPC_STRUCT10_RELEASE IPC_STRUCT10_NOTIFY IPC_STRUCT10_DATA IPC_STRUCT10_LOCK_STATUS IPC_STRUCT11_ACQUIRE IPC_STRUCT11_RELEASE IPC_STRUCT11_NOTIFY IPC_STRUCT11_DATA IPC_STRUCT11_LOCK_STATUS IPC_STRUCT12_ACQUIRE IPC_STRUCT12_RELEASE IPC_STRUCT12_NOTIFY IPC_STRUCT12_DATA IPC_STRUCT12_LOCK_STATUS IPC_STRUCT13_ACQUIRE IPC_STRUCT13_RELEASE IPC_STRUCT13_NOTIFY
Address 0x402300A4 0x402300A8 0x402300AC 0x402300B0 0x402300C0 0x402300C4 0x402300C8 0x402300CC 0x402300D0 0x402300E0 0x402300E4 0x402300E8 0x402300EC 0x402300F0 0x40230100 0x40230104 0x40230108 0x4023010C 0x40230110 0x40230120 0x40230124 0x40230128 0x4023012C 0x40230130 0x40230140 0x40230144 0x40230148 0x4023014C 0x40230150 0x40230160 0x40230164 0x40230168 0x4023016C 0x40230170 0x40230180 0x40230184 0x40230188 0x4023018C 0x40230190 0x402301A0 0x402301A4 0x402301A8
Description IPC release. See IPC_STRUCT0_RELEASE for the details of bit fields. IPC notification. See IPC_STRUCT0_NOTIFY for the details of bit fields. IPC data. See IPC_STRUCT0_DATA for the details of bit fields. IPC lock status. See IPC_STRUCT0_LOCK_STATUS for the details of bit fields. IPC acquire. See IPC_STRUCT0_ACQUIRE for the details of bit fields. IPC release. See IPC_STRUCT0_RELEASE for the details of bit fields. IPC notification. See IPC_STRUCT0_NOTIFY for the details of bit fields. IPC data. See IPC_STRUCT0_DATA for the details of bit fields. IPC lock status. See IPC_STRUCT0_LOCK_STATUS for the details of bit fields. IPC acquire. See IPC_STRUCT0_ACQUIRE for the details of bit fields. IPC release. See IPC_STRUCT0_RELEASE for the details of bit fields. IPC notification. See IPC_STRUCT0_NOTIFY for the details of bit fields. IPC data. See IPC_STRUCT0_DATA for the details of bit fields. IPC lock status. See IPC_STRUCT0_LOCK_STATUS for the details of bit fields. IPC acquire. See IPC_STRUCT0_ACQUIRE for the details of bit fields. IPC release. See IPC_STRUCT0_RELEASE for the details of bit fields. IPC notification. See IPC_STRUCT0_NOTIFY for the details of bit fields. IPC data. See IPC_STRUCT0_DATA for the details of bit fields. IPC lock status. See IPC_STRUCT0_LOCK_STATUS for the details of bit fields. IPC acquire. See IPC_STRUCT0_ACQUIRE for the details of bit fields. IPC release. See IPC_STRUCT0_RELEASE for the details of bit fields. IPC notification. See IPC_STRUCT0_NOTIFY for the details of bit fields. IPC data. See IPC_STRUCT0_DATA for the details of bit fields. IPC lock status. See IPC_STRUCT0_LOCK_STATUS for the details of bit fields. IPC acquire. See IPC_STRUCT0_ACQUIRE for the details of bit fields. IPC release. See IPC_STRUCT0_RELEASE for the details of bit fields. IPC notification. See IPC_STRUCT0_NOTIFY for the details of bit fields. IPC data. See IPC_STRUCT0_DATA for the details of bit fields. IPC lock status. See IPC_STRUCT0_LOCK_STATUS for the details of bit fields. IPC acquire. See IPC_STRUCT0_ACQUIRE for the details of bit fields. IPC release. See IPC_STRUCT0_RELEASE for the details of bit fields. IPC notification. See IPC_STRUCT0_NOTIFY for the details of bit fields. IPC data. See IPC_STRUCT0_DATA for the details of bit fields. IPC lock status. See IPC_STRUCT0_LOCK_STATUS for the details of bit fields. IPC acquire. See IPC_STRUCT0_ACQUIRE for the details of bit fields. IPC release. See IPC_STRUCT0_RELEASE for the details of bit fields. IPC notification. See IPC_STRUCT0_NOTIFY for the details of bit fields. IPC data. See IPC_STRUCT0_DATA for the details of bit fields. IPC lock status. See IPC_STRUCT0_LOCK_STATUS for the details of bit fields. IPC acquire. See IPC_STRUCT0_ACQUIRE for the details of bit fields. IPC release. See IPC_STRUCT0_RELEASE for the details of bit fields. IPC notification. See IPC_STRUCT0_NOTIFY for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
378
Inter-Processor Communication Registers
Register IPC_STRUCT13_DATA IPC_STRUCT13_LOCK_STATUS IPC_STRUCT14_ACQUIRE IPC_STRUCT14_RELEASE IPC_STRUCT14_NOTIFY IPC_STRUCT14_DATA IPC_STRUCT14_LOCK_STATUS IPC_STRUCT15_ACQUIRE IPC_STRUCT15_RELEASE IPC_STRUCT15_NOTIFY IPC_STRUCT15_DATA IPC_STRUCT15_LOCK_STATUS IPC_INTR_STRUCT0_INTR IPC_INTR_STRUCT0_INTR_SET IPC_INTR_STRUCT0_INTR_MASK IPC_INTR_STRUCT0_INTR_MASKED IPC_INTR_STRUCT1_INTR IPC_INTR_STRUCT1_INTR_SET IPC_INTR_STRUCT1_INTR_MASK IPC_INTR_STRUCT1_INTR_MASKED IPC_INTR_STRUCT2_INTR IPC_INTR_STRUCT2_INTR_SET IPC_INTR_STRUCT2_INTR_MASK IPC_INTR_STRUCT2_INTR_MASKED IPC_INTR_STRUCT3_INTR IPC_INTR_STRUCT3_INTR_SET IPC_INTR_STRUCT3_INTR_MASK IPC_INTR_STRUCT3_INTR_MASKED IPC_INTR_STRUCT4_INTR IPC_INTR_STRUCT4_INTR_SET IPC_INTR_STRUCT4_INTR_MASK IPC_INTR_STRUCT4_INTR_MASKED IPC_INTR_STRUCT5_INTR IPC_INTR_STRUCT5_INTR_SET IPC_INTR_STRUCT5_INTR_MASK IPC_INTR_STRUCT5_INTR_MASKED IPC_INTR_STRUCT6_INTR IPC_INTR_STRUCT6_INTR_SET IPC_INTR_STRUCT6_INTR_MASK IPC_INTR_STRUCT6_INTR_MASKED IPC_INTR_STRUCT7_INTR IPC_INTR_STRUCT7_INTR_SET
Address 0x402301AC 0x402301B0 0x402301C0 0x402301C4 0x402301C8 0x402301CC 0x402301D0 0x402301E0 0x402301E4 0x402301E8 0x402301EC 0x402301F0 0x40231000 0x40231004 0x40231008 0x4023100C 0x40231020 0x40231024 0x40231028 0x4023102C 0x40231040 0x40231044 0x40231048 0x4023104C 0x40231060 0x40231064 0x40231068 0x4023106C 0x40231080 0x40231084 0x40231088 0x4023108C 0x402310A0 0x402310A4 0x402310A8 0x402310AC 0x402310C0 0x402310C4 0x402310C8 0x402310CC 0x402310E0 0x402310E4
Description IPC data. See IPC_STRUCT0_DATA for the details of bit fields. IPC lock status. See IPC_STRUCT0_LOCK_STATUS for the details of bit fields. IPC acquire. See IPC_STRUCT0_ACQUIRE for the details of bit fields. IPC release. See IPC_STRUCT0_RELEASE for the details of bit fields. IPC notification. See IPC_STRUCT0_NOTIFY for the details of bit fields. IPC data. See IPC_STRUCT0_DATA for the details of bit fields. IPC lock status. See IPC_STRUCT0_LOCK_STATUS for the details of bit fields. IPC acquire. See IPC_STRUCT0_ACQUIRE for the details of bit fields. IPC release. See IPC_STRUCT0_RELEASE for the details of bit fields. IPC notification. See IPC_STRUCT0_NOTIFY for the details of bit fields. IPC data. See IPC_STRUCT0_DATA for the details of bit fields. IPC lock status. See IPC_STRUCT0_LOCK_STATUS for the details of bit fields. Interrupt Interrupt set Interrupt mask Interrupt masked Interrupt. See IPC_INTR_STRUCT0_INTR for the details of bit fields. Interrupt set. See IPC_INTR_STRUCT0_INTR_SET for the details of bit fields. Interrupt mask. See IPC_INTR_STRUCT0_INTR_MASK for the details of bit fields. Interrupt masked. See IPC_INTR_STRUCT0_INTR_MASKED for the details of bit fields. Interrupt. See IPC_INTR_STRUCT0_INTR for the details of bit fields. Interrupt set. See IPC_INTR_STRUCT0_INTR_SET for the details of bit fields. Interrupt mask. See IPC_INTR_STRUCT0_INTR_MASK for the details of bit fields. Interrupt masked. See IPC_INTR_STRUCT0_INTR_MASKED for the details of bit fields. Interrupt. See IPC_INTR_STRUCT0_INTR for the details of bit fields. Interrupt set. See IPC_INTR_STRUCT0_INTR_SET for the details of bit fields. Interrupt mask. See IPC_INTR_STRUCT0_INTR_MASK for the details of bit fields. Interrupt masked. See IPC_INTR_STRUCT0_INTR_MASKED for the details of bit fields. Interrupt. See IPC_INTR_STRUCT0_INTR for the details of bit fields. Interrupt set. See IPC_INTR_STRUCT0_INTR_SET for the details of bit fields. Interrupt mask. See IPC_INTR_STRUCT0_INTR_MASK for the details of bit fields. Interrupt masked. See IPC_INTR_STRUCT0_INTR_MASKED for the details of bit fields. Interrupt. See IPC_INTR_STRUCT0_INTR for the details of bit fields. Interrupt set. See IPC_INTR_STRUCT0_INTR_SET for the details of bit fields. Interrupt mask. See IPC_INTR_STRUCT0_INTR_MASK for the details of bit fields. Interrupt masked. See IPC_INTR_STRUCT0_INTR_MASKED for the details of bit fields. Interrupt. See IPC_INTR_STRUCT0_INTR for the details of bit fields. Interrupt set. See IPC_INTR_STRUCT0_INTR_SET for the details of bit fields. Interrupt mask. See IPC_INTR_STRUCT0_INTR_MASK for the details of bit fields. Interrupt masked. See IPC_INTR_STRUCT0_INTR_MASKED for the details of bit fields. Interrupt. See IPC_INTR_STRUCT0_INTR for the details of bit fields. Interrupt set. See IPC_INTR_STRUCT0_INTR_SET for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
379
Inter-Processor Communication Registers
Register
Address
IPC_INTR_STRUCT7_INTR_MASK
0x402310E8
IPC_INTR_STRUCT7_INTR_MASKED 0x402310EC
IPC_INTR_STRUCT8_INTR
0x40231100
IPC_INTR_STRUCT8_INTR_SET
0x40231104
IPC_INTR_STRUCT8_INTR_MASK
0x40231108
IPC_INTR_STRUCT8_INTR_MASKED 0x4023110C
IPC_INTR_STRUCT9_INTR
0x40231120
IPC_INTR_STRUCT9_INTR_SET
0x40231124
IPC_INTR_STRUCT9_INTR_MASK
0x40231128
IPC_INTR_STRUCT9_INTR_MASKED 0x4023112C
IPC_INTR_STRUCT10_INTR
0x40231140
IPC_INTR_STRUCT10_INTR_SET
0x40231144
IPC_INTR_STRUCT10_INTR_MASK
0x40231148
IPC_INTR_STRUCT10_INTR_MASKED 0x4023114C
IPC_INTR_STRUCT11_INTR
0x40231160
IPC_INTR_STRUCT11_INTR_SET
0x40231164
IPC_INTR_STRUCT11_INTR_MASK
0x40231168
IPC_INTR_STRUCT11_INTR_MASKED 0x4023116C
IPC_INTR_STRUCT12_INTR
0x40231180
IPC_INTR_STRUCT12_INTR_SET
0x40231184
IPC_INTR_STRUCT12_INTR_MASK
0x40231188
IPC_INTR_STRUCT12_INTR_MASKED 0x4023118C
IPC_INTR_STRUCT13_INTR
0x402311A0
IPC_INTR_STRUCT13_INTR_SET
0x402311A4
IPC_INTR_STRUCT13_INTR_MASK
0x402311A8
IPC_INTR_STRUCT13_INTR_MASKED 0x402311AC
IPC_INTR_STRUCT14_INTR
0x402311C0
IPC_INTR_STRUCT14_INTR_SET
0x402311C4
IPC_INTR_STRUCT14_INTR_MASK
0x402311C8
IPC_INTR_STRUCT14_INTR_MASKED 0x402311CC
IPC_INTR_STRUCT15_INTR
0x402311E0
IPC_INTR_STRUCT15_INTR_SET
0x402311E4
IPC_INTR_STRUCT15_INTR_MASK
0x402311E8
IPC_INTR_STRUCT15_INTR_MASKED 0x402311EC
Description Interrupt mask. See IPC_INTR_STRUCT0_INTR_MASK for the details of bit fields. Interrupt masked. See IPC_INTR_STRUCT0_INTR_MASKED for the details of bit fields. Interrupt. See IPC_INTR_STRUCT0_INTR for the details of bit fields. Interrupt set. See IPC_INTR_STRUCT0_INTR_SET for the details of bit fields. Interrupt mask. See IPC_INTR_STRUCT0_INTR_MASK for the details of bit fields. Interrupt masked. See IPC_INTR_STRUCT0_INTR_MASKED for the details of bit fields. Interrupt. See IPC_INTR_STRUCT0_INTR for the details of bit fields. Interrupt set. See IPC_INTR_STRUCT0_INTR_SET for the details of bit fields. Interrupt mask. See IPC_INTR_STRUCT0_INTR_MASK for the details of bit fields. Interrupt masked. See IPC_INTR_STRUCT0_INTR_MASKED for the details of bit fields. Interrupt. See IPC_INTR_STRUCT0_INTR for the details of bit fields. Interrupt set. See IPC_INTR_STRUCT0_INTR_SET for the details of bit fields. Interrupt mask. See IPC_INTR_STRUCT0_INTR_MASK for the details of bit fields. Interrupt masked. See IPC_INTR_STRUCT0_INTR_MASKED for the details of bit fields. Interrupt. See IPC_INTR_STRUCT0_INTR for the details of bit fields. Interrupt set. See IPC_INTR_STRUCT0_INTR_SET for the details of bit fields. Interrupt mask. See IPC_INTR_STRUCT0_INTR_MASK for the details of bit fields. Interrupt masked. See IPC_INTR_STRUCT0_INTR_MASKED for the details of bit fields. Interrupt. See IPC_INTR_STRUCT0_INTR for the details of bit fields. Interrupt set. See IPC_INTR_STRUCT0_INTR_SET for the details of bit fields. Interrupt mask. See IPC_INTR_STRUCT0_INTR_MASK for the details of bit fields. Interrupt masked. See IPC_INTR_STRUCT0_INTR_MASKED for the details of bit fields. Interrupt. See IPC_INTR_STRUCT0_INTR for the details of bit fields. Interrupt set. See IPC_INTR_STRUCT0_INTR_SET for the details of bit fields. Interrupt mask. See IPC_INTR_STRUCT0_INTR_MASK for the details of bit fields. Interrupt masked. See IPC_INTR_STRUCT0_INTR_MASKED for the details of bit fields. Interrupt. See IPC_INTR_STRUCT0_INTR for the details of bit fields. Interrupt set. See IPC_INTR_STRUCT0_INTR_SET for the details of bit fields. Interrupt mask. See IPC_INTR_STRUCT0_INTR_MASK for the details of bit fields. Interrupt masked. See IPC_INTR_STRUCT0_INTR_MASKED for the details of bit fields. Interrupt. See IPC_INTR_STRUCT0_INTR for the details of bit fields. Interrupt set. See IPC_INTR_STRUCT0_INTR_SET for the details of bit fields. Interrupt mask. See IPC_INTR_STRUCT0_INTR_MASK for the details of bit fields. Interrupt masked. See IPC_INTR_STRUCT0_INTR_MASKED for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
380
IPC_STRUCT0_ACQUIRE
6.1.1 IPC_STRUCT0_ACQUIRE
Address = 0x40230000 IPC acquire Address: 0x40230000 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
None
R
R
HW Access
W
None
W
W
Name
PC [7:4]
None [3:2]
NS
P
Bits
15
14
13
12
11
10
9
8
SW Access
None
R
HW Access
None
W
Name
None [15:12]
MS [11:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
None
HW Access
RW
None
Name
SUCCESS
None [30:24]
Bits
Name
31
SUCCESS
11 : 8
MS
7 : 4
PC
Description
Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED): '0': Not successfully acquired; i.e. the lock was already acquired by another read transaction and not released. The P, NS, PC and MS fields reflect the access attributes of the transaction that previously successfully acuired the lock; the fields are NOT affected by the current access. '1': Successfully acquired. The P, NS, PC and MS fields reflect the access attributes of the current access. Note that this field is NOT SW writable. A lock is released by writing to the associated RELEASE register (irrespective of the write value). Default Value: 0
This field specifies the bus master identifier that successfully acquired the lock. Default Value: Undefined
This field specifies the protection context that successfully acquired the lock. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
381
IPC_STRUCT0_ACQUIRE
6.1.1
1
0
IPC_STRUCT0_ACQUIRE (continued)
NS
Secure/on-secure access control:
'0': secure.
'1': non-secure.
This field is set with the secure/non-secure access control of the access that successfully ac-
quired the lock.
Default Value: Undefined
P
User/privileged access control:
'0': user mode.
'1': privileged mode.
This field is set with the user/privileged access control of the access that successfully acquired
the lock.
Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
382
IPC_STRUCT0_RELEASE
6.1.2 IPC_STRUCT0_RELEASE
Address = 0x40230004 IPC release Address: 0x40230004 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
W
HW Access
Name
INTR_RELEASE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
W
HW Access
Name
INTR_RELEASE [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 0
Name INTR_RELEASE
Description
This field allows for the generation of release events to the IPC interrupt structures, but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_RELEASE[] is set to '1'. SW writes a '1' to the bit fields to generate a release event. Due to the transient nature of this event, SW always reads a '0' from this field. As a side effect, a write to this register will always set LOCK_STATUS.ACQUIRED to '0' (even when no release event is generated; i.e. the written data is "0"). Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
383
IPC_STRUCT0_NOTIFY
6.1.3 IPC_STRUCT0_NOTIFY
Address = 0x40230008 IPC notification Address: 0x40230008 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
W
HW Access
Name
INTR_NOTIFY [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
W
HW Access
Name
INTR_NOTIFY [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 0
Name INTR_NOTIFY
Description
This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_NOTIFY[] is set to '1'. SW writes a '1' to the bit fields to generate a notify event. Due to the transient nature of this event, SW always reads a '0' from this field. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
384
IPC_STRUCT0_DATA
6.1.4 IPC_STRUCT0_DATA
Address = 0x4023000C IPC data Address: 0x4023000C Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
Name
DATA [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
Name
DATA [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
Name
DATA [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
Name
DATA [31:24]
Bits 31 : 0
Name DATA
Description
This field holds a 32-bit data element that is associated with the IPC structure. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
385
IPC_STRUCT0_LOCK_STATUS
6.1.5 IPC_STRUCT0_LOCK_STATUS
Address = 0x40230010 IPC lock status Address: 0x40230010 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
None
R
R
HW Access
W
None
W
W
Name
PC [7:4]
None [3:2]
NS
P
Bits
15
14
13
12
11
10
9
8
SW Access
None
R
HW Access
None
W
Name
None [15:12]
MS [11:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
None
HW Access
R
None
Name
ACQUIRED
None [30:24]
Bits
Name
31
ACQUIRED
11 : 8
MS
7 : 4
PC
1
NS
0
P
Description
Specifies if the lock is acquired. This field is set to '1', if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1'). Default Value: 0
This field specifies the bus master identifier that successfully acquired the lock. Default Value: Undefined
This field specifies the protection context that successfully acquired the lock. Default Value: Undefined
This field specifies the cecure/on-secure access control: '0': secure. '1': non-secure. Default Value: Undefined
This field specifies the user/privileged access control: '0': user mode. '1': privileged mode. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
386
IPC_INTR_STRUCT0_INTR
6.1.6 IPC_INTR_STRUCT0_INTR
Address = 0x40231000 Interrupt Address: 0x40231000 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW1C
HW Access
RW1S
Name
RELEASE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW1C
HW Access
RW1S
Name
RELEASE [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW1C
HW Access
RW1S
Name
NOTIFY [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW1C
HW Access
RW1S
Name
NOTIFY [31:24]
Bits 31 : 16
Name NOTIFY
15 : 0
RELEASE
Description
These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause. Default Value: 0
These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
387
IPC_INTR_STRUCT0_INTR_SET
6.1.7 IPC_INTR_STRUCT0_INTR_SET
Address = 0x40231004 Interrupt set Address: 0x40231004 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW1S
HW Access
A
Name
RELEASE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW1S
HW Access
A
Name
RELEASE [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW1S
HW Access
A
Name
NOTIFY [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW1S
HW Access
A
Name
NOTIFY [31:24]
Bits 31 : 16
15 : 0
Name NOTIFY
RELEASE
Description
SW writes a '1' to this field to set the corresponding field in the INTR register. Default Value: 0
SW writes a '1' to this field to set the corresponding field in the INTR register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
388
IPC_INTR_STRUCT0_INTR_MASK
6.1.8 IPC_INTR_STRUCT0_INTR_MASK
Address = 0x40231008 Interrupt mask Address: 0x40231008 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
RELEASE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
RELEASE [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
NOTIFY [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
NOTIFY [31:24]
Bits 31 : 16
15 : 0
Name NOTIFY
RELEASE
Description
Mask bit for corresponding field in the INTR register. Default Value: 0
Mask bit for corresponding field in the INTR register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
389
IPC_INTR_STRUCT0_INTR_MASKED
6.1.9 IPC_INTR_STRUCT0_INTR_MASKED
Address = 0x4023100C Interrupt masked Address: 0x4023100C Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
RELEASE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
RELEASE [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
W
Name
NOTIFY [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
W
Name
NOTIFY [31:24]
Bits 31 : 16
15 : 0
Name NOTIFY
RELEASE
Description
Logical and of corresponding INTR and INTR_MASK fields. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
390
7 Protection Unit Registers
This section discusses the Protection Unit registers. It lists all the registers in mapping tables, in address order.
7.1 Register Details
Register PROT_SMPU_MS0_CTL PROT_SMPU_MS1_CTL PROT_SMPU_MS2_CTL PROT_SMPU_MS3_CTL PROT_SMPU_MS14_CTL PROT_SMPU_MS15_CTL PROT_SMPU_SMPU_STRUCT0_ADDR0 PROT_SMPU_SMPU_STRUCT0_ATT0 PROT_SMPU_SMPU_STRUCT0_ADDR1 PROT_SMPU_SMPU_STRUCT0_ATT1
PROT_SMPU_SMPU_STRUCT1_ADDR0
PROT_SMPU_SMPU_STRUCT1_ATT0
Address
Description
0x40240000 Master 0 protection context control
0x40240004 Master 1 protection context control
0x40240008 Master 2 protection context control
0x4024000C Master 3 protection context control
0x40240038 Master 14 protection context control
0x4024003C Master 15 protection context control
0x40242000 SMPU region address 0 (slave structure)
0x40242004 SMPU region attributes 0 (slave structure)
0x40242020 SMPU region address 1 (master structure)
0x40242024 SMPU region attributes 1 (master structure)
0x40242040
SMPU region address 0 (slave structure). See PROT_SMPU_SMPU_STRUCT0_ADDR0 for the details of bit fields.
0x40242044
SMPU region attributes 0 (slave structure). See PROT_SMPU_SMPU_STRUCT0_ATT0 for the details of bit fields.
PROT_SMPU_SMPU_STRUCT1_ADDR1 0x40242060 SMPU region address 1 (master structure)
PROT_SMPU_SMPU_STRUCT1_ATT1 PROT_SMPU_SMPU_STRUCT2_ADDR0 PROT_SMPU_SMPU_STRUCT2_ATT0
0x40242064 0x40242080 0x40242084
SMPU region attributes 1 (master structure). See PROT_SMPU_SMPU_STRUCT0_ATT1 for the details of bit fields.
SMPU region address 0 (slave structure). See PROT_SMPU_SMPU_STRUCT0_ADDR0 for the details of bit fields.
SMPU region attributes 0 (slave structure). See PROT_SMPU_SMPU_STRUCT0_ATT0 for the details of bit fields.
PROT_SMPU_SMPU_STRUCT2_ADDR1 0x402420A0 SMPU region address 1 (master structure)
PROT_SMPU_SMPU_STRUCT2_ATT1 PROT_SMPU_SMPU_STRUCT3_ADDR0 PROT_SMPU_SMPU_STRUCT3_ATT0
0x402420A4 0x402420C0 0x402420C4
SMPU region attributes 1 (master structure). See PROT_SMPU_SMPU_STRUCT0_ATT1 for the details of bit fields.
SMPU region address 0 (slave structure). See PROT_SMPU_SMPU_STRUCT0_ADDR0 for the details of bit fields.
SMPU region attributes 0 (slave structure). See PROT_SMPU_SMPU_STRUCT0_ATT0 for the details of bit fields.
PROT_SMPU_SMPU_STRUCT3_ADDR1 0x402420E0 SMPU region address 1 (master structure)
PROT_SMPU_SMPU_STRUCT3_ATT1
0x402420E4
SMPU region attributes 1 (master structure). See PROT_SMPU_SMPU_STRUCT0_ATT1 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
391
Protection Unit Registers
Register PROT_SMPU_SMPU_STRUCT4_ADDR0 PROT_SMPU_SMPU_STRUCT4_ATT0
Address 0x40242100 0x40242104
Description
SMPU region address 0 (slave structure). See PROT_SMPU_SMPU_STRUCT0_ADDR0 for the details of bit fields.
SMPU region attributes 0 (slave structure). See PROT_SMPU_SMPU_STRUCT0_ATT0 for the details of bit fields.
PROT_SMPU_SMPU_STRUCT4_ADDR1 0x40242120 SMPU region address 1 (master structure)
PROT_SMPU_SMPU_STRUCT4_ATT1 PROT_SMPU_SMPU_STRUCT5_ADDR0 PROT_SMPU_SMPU_STRUCT5_ATT0
0x40242124 0x40242140 0x40242144
SMPU region attributes 1 (master structure). See PROT_SMPU_SMPU_STRUCT0_ATT1 for the details of bit fields.
SMPU region address 0 (slave structure). See PROT_SMPU_SMPU_STRUCT0_ADDR0 for the details of bit fields.
SMPU region attributes 0 (slave structure). See PROT_SMPU_SMPU_STRUCT0_ATT0 for the details of bit fields.
PROT_SMPU_SMPU_STRUCT5_ADDR1 0x40242160 SMPU region address 1 (master structure)
PROT_SMPU_SMPU_STRUCT5_ATT1 PROT_SMPU_SMPU_STRUCT6_ADDR0 PROT_SMPU_SMPU_STRUCT6_ATT0
0x40242164 0x40242180 0x40242184
SMPU region attributes 1 (master structure). See PROT_SMPU_SMPU_STRUCT0_ATT1 for the details of bit fields.
SMPU region address 0 (slave structure). See PROT_SMPU_SMPU_STRUCT0_ADDR0 for the details of bit fields.
SMPU region attributes 0 (slave structure). See PROT_SMPU_SMPU_STRUCT0_ATT0 for the details of bit fields.
PROT_SMPU_SMPU_STRUCT6_ADDR1 0x402421A0 SMPU region address 1 (master structure)
PROT_SMPU_SMPU_STRUCT6_ATT1 PROT_SMPU_SMPU_STRUCT7_ADDR0 PROT_SMPU_SMPU_STRUCT7_ATT0
0x402421A4 0x402421C0 0x402421C4
SMPU region attributes 1 (master structure). See PROT_SMPU_SMPU_STRUCT0_ATT1 for the details of bit fields.
SMPU region address 0 (slave structure). See PROT_SMPU_SMPU_STRUCT0_ADDR0 for the details of bit fields.
SMPU region attributes 0 (slave structure). See PROT_SMPU_SMPU_STRUCT0_ATT0 for the details of bit fields.
PROT_SMPU_SMPU_STRUCT7_ADDR1 0x402421E0 SMPU region address 1 (master structure)
PROT_SMPU_SMPU_STRUCT7_ATT1 PROT_SMPU_SMPU_STRUCT8_ADDR0 PROT_SMPU_SMPU_STRUCT8_ATT0
0x402421E4 0x40242200 0x40242204
SMPU region attributes 1 (master structure). See PROT_SMPU_SMPU_STRUCT0_ATT1 for the details of bit fields.
SMPU region address 0 (slave structure). See PROT_SMPU_SMPU_STRUCT0_ADDR0 for the details of bit fields.
SMPU region attributes 0 (slave structure). See PROT_SMPU_SMPU_STRUCT0_ATT0 for the details of bit fields.
PROT_SMPU_SMPU_STRUCT8_ADDR1 0x40242220 SMPU region address 1 (master structure)
PROT_SMPU_SMPU_STRUCT8_ATT1 PROT_SMPU_SMPU_STRUCT9_ADDR0 PROT_SMPU_SMPU_STRUCT9_ATT0
0x40242224 0x40242240 0x40242244
SMPU region attributes 1 (master structure). See PROT_SMPU_SMPU_STRUCT0_ATT1 for the details of bit fields.
SMPU region address 0 (slave structure). See PROT_SMPU_SMPU_STRUCT0_ADDR0 for the details of bit fields.
SMPU region attributes 0 (slave structure). See PROT_SMPU_SMPU_STRUCT0_ATT0 for the details of bit fields.
PROT_SMPU_SMPU_STRUCT9_ADDR1 0x40242260 SMPU region address 1 (master structure)
PROT_SMPU_SMPU_STRUCT9_ATT1
0x40242264
PROT_SMPU_SMPU_STRUCT10_ADDR0 0x40242280
PROT_SMPU_SMPU_STRUCT10_ATT0 0x40242284
SMPU region attributes 1 (master structure). See PROT_SMPU_SMPU_STRUCT0_ATT1 for the details of bit fields.
SMPU region address 0 (slave structure). See PROT_SMPU_SMPU_STRUCT0_ADDR0 for the details of bit fields.
SMPU region attributes 0 (slave structure). See PROT_SMPU_SMPU_STRUCT0_ATT0 for the details of bit fields.
PROT_SMPU_SMPU_STRUCT10_ADDR1 0x402422A0 SMPU region address 1 (master structure)
PROT_SMPU_SMPU_STRUCT10_ATT1 PROT_SMPU_SMPU_STRUCT11_ADDR0
0x402422A4 0x402422C0
SMPU region attributes 1 (master structure). See PROT_SMPU_SMPU_STRUCT0_ATT1 for the details of bit fields.
SMPU region address 0 (slave structure). See PROT_SMPU_SMPU_STRUCT0_ADDR0 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
392
Protection Unit Registers
Register PROT_SMPU_SMPU_STRUCT11_ATT0
Address
Description
0x402422C4
SMPU region attributes 0 (slave structure). See PROT_SMPU_SMPU_STRUCT0_ATT0 for the details of bit fields.
PROT_SMPU_SMPU_STRUCT11_ADDR1 0x402422E0 SMPU region address 1 (master structure)
PROT_SMPU_SMPU_STRUCT11_ATT1 0x402422E4 PROT_SMPU_SMPU_STRUCT12_ADDR0 0x40242300 PROT_SMPU_SMPU_STRUCT12_ATT0 0x40242304
SMPU region attributes 1 (master structure). See PROT_SMPU_SMPU_STRUCT0_ATT1 for the details of bit fields.
SMPU region address 0 (slave structure). See PROT_SMPU_SMPU_STRUCT0_ADDR0 for the details of bit fields.
SMPU region attributes 0 (slave structure). See PROT_SMPU_SMPU_STRUCT0_ATT0 for the details of bit fields.
PROT_SMPU_SMPU_STRUCT12_ADDR1 0x40242320 SMPU region address 1 (master structure)
PROT_SMPU_SMPU_STRUCT12_ATT1 0x40242324 PROT_SMPU_SMPU_STRUCT13_ADDR0 0x40242340 PROT_SMPU_SMPU_STRUCT13_ATT0 0x40242344
SMPU region attributes 1 (master structure). See PROT_SMPU_SMPU_STRUCT0_ATT1 for the details of bit fields.
SMPU region address 0 (slave structure). See PROT_SMPU_SMPU_STRUCT0_ADDR0 for the details of bit fields.
SMPU region attributes 0 (slave structure). See PROT_SMPU_SMPU_STRUCT0_ATT0 for the details of bit fields.
PROT_SMPU_SMPU_STRUCT13_ADDR1 0x40242360 SMPU region address 1 (master structure)
PROT_SMPU_SMPU_STRUCT13_ATT1 0x40242364 PROT_SMPU_SMPU_STRUCT14_ADDR0 0x40242380 PROT_SMPU_SMPU_STRUCT14_ATT0 0x40242384
SMPU region attributes 1 (master structure). See PROT_SMPU_SMPU_STRUCT0_ATT1 for the details of bit fields.
SMPU region address 0 (slave structure). See PROT_SMPU_SMPU_STRUCT0_ADDR0 for the details of bit fields.
SMPU region attributes 0 (slave structure). See PROT_SMPU_SMPU_STRUCT0_ATT0 for the details of bit fields.
PROT_SMPU_SMPU_STRUCT14_ADDR1 0x402423A0 SMPU region address 1 (master structure)
PROT_SMPU_SMPU_STRUCT14_ATT1 0x402423A4 PROT_SMPU_SMPU_STRUCT15_ADDR0 0x402423C0 PROT_SMPU_SMPU_STRUCT15_ATT0 0x402423C4
SMPU region attributes 1 (master structure). See PROT_SMPU_SMPU_STRUCT0_ATT1 for the details of bit fields.
SMPU region address 0 (slave structure). See PROT_SMPU_SMPU_STRUCT0_ADDR0 for the details of bit fields.
SMPU region attributes 0 (slave structure). See PROT_SMPU_SMPU_STRUCT0_ATT0 for the details of bit fields.
PROT_SMPU_SMPU_STRUCT15_ADDR1 0x402423E0 SMPU region address 1 (master structure)
PROT_SMPU_SMPU_STRUCT15_ATT1
PROT_MPU0_MS_CTL PROT_MPU1_MS_CTL PROT_MPU1_MPU_STRUCT0_ADDR PROT_MPU1_MPU_STRUCT0_ATT PROT_MPU1_MPU_STRUCT1_ADDR PROT_MPU1_MPU_STRUCT1_ATT PROT_MPU1_MPU_STRUCT2_ADDR PROT_MPU1_MPU_STRUCT2_ATT PROT_MPU1_MPU_STRUCT3_ADDR PROT_MPU1_MPU_STRUCT3_ATT PROT_MPU1_MPU_STRUCT4_ADDR PROT_MPU1_MPU_STRUCT4_ATT PROT_MPU1_MPU_STRUCT5_ADDR PROT_MPU1_MPU_STRUCT5_ATT PROT_MPU1_MPU_STRUCT6_ADDR
0x402423E4
SMPU region attributes 1 (master structure). See PROT_SMPU_SMPU_STRUCT0_ATT1 for the details of bit fields.
0x40244000 Master control
0x40244400 Master control
0x40244600 MPU region address
0x40244604 MPU region attributes
0x40244620 MPU region address. See PROT_MPU1_MPU_STRUCT0_ADDR for the details of bit fields.
0x40244624 MPU region attributes. See PROT_MPU1_MPU_STRUCT0_ATT for the details of bit fields.
0x40244640 MPU region address. See PROT_MPU1_MPU_STRUCT0_ADDR for the details of bit fields.
0x40244644 MPU region attributes. See PROT_MPU1_MPU_STRUCT0_ATT for the details of bit fields.
0x40244660 MPU region address. See PROT_MPU1_MPU_STRUCT0_ADDR for the details of bit fields.
0x40244664 MPU region attributes. See PROT_MPU1_MPU_STRUCT0_ATT for the details of bit fields.
0x40244680 MPU region address. See PROT_MPU1_MPU_STRUCT0_ADDR for the details of bit fields.
0x40244684 MPU region attributes. See PROT_MPU1_MPU_STRUCT0_ATT for the details of bit fields.
0x402446A0 MPU region address. See PROT_MPU1_MPU_STRUCT0_ADDR for the details of bit fields.
0x402446A4 MPU region attributes. See PROT_MPU1_MPU_STRUCT0_ATT for the details of bit fields.
0x402446C0 MPU region address. See PROT_MPU1_MPU_STRUCT0_ADDR for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
393
Protection Unit Registers
Register PROT_MPU1_MPU_STRUCT6_ATT PROT_MPU1_MPU_STRUCT7_ADDR PROT_MPU1_MPU_STRUCT7_ATT PROT_MPU14_MS_CTL PROT_MPU15_MS_CTL PROT_MPU15_MPU_STRUCT0_ADDR PROT_MPU15_MPU_STRUCT0_ATT PROT_MPU15_MPU_STRUCT1_ADDR PROT_MPU15_MPU_STRUCT1_ATT PROT_MPU15_MPU_STRUCT2_ADDR PROT_MPU15_MPU_STRUCT2_ATT PROT_MPU15_MPU_STRUCT3_ADDR PROT_MPU15_MPU_STRUCT3_ATT PROT_MPU15_MPU_STRUCT4_ADDR PROT_MPU15_MPU_STRUCT4_ATT PROT_MPU15_MPU_STRUCT5_ADDR PROT_MPU15_MPU_STRUCT5_ATT PROT_MPU15_MPU_STRUCT6_ADDR PROT_MPU15_MPU_STRUCT6_ATT PROT_MPU15_MPU_STRUCT7_ADDR PROT_MPU15_MPU_STRUCT7_ATT
Address
Description
0x402446C4 MPU region attributes. See PROT_MPU1_MPU_STRUCT0_ATT for the details of bit fields.
0x402446E0 MPU region address. See PROT_MPU1_MPU_STRUCT0_ADDR for the details of bit fields.
0x402446E4 MPU region attributes. See PROT_MPU1_MPU_STRUCT0_ATT for the details of bit fields.
0x40247800 Master control. See PROT_MPU1_MS_CTL for the details of bit fields.
0x40247C00 Master control. See PROT_MPU1_MS_CTL for the details of bit fields.
0x40247E00 MPU region address. See PROT_MPU1_MPU_STRUCT0_ADDR for the details of bit fields.
0x40247E04 MPU region attributes. See PROT_MPU1_MPU_STRUCT0_ATT for the details of bit fields.
0x40247E20 MPU region address. See PROT_MPU1_MPU_STRUCT0_ADDR for the details of bit fields.
0x40247E24 MPU region attributes. See PROT_MPU1_MPU_STRUCT0_ATT for the details of bit fields.
0x40247E40 MPU region address. See PROT_MPU1_MPU_STRUCT0_ADDR for the details of bit fields.
0x40247E44 MPU region attributes. See PROT_MPU1_MPU_STRUCT0_ATT for the details of bit fields.
0x40247E60 MPU region address. See PROT_MPU1_MPU_STRUCT0_ADDR for the details of bit fields.
0x40247E64 MPU region attributes. See PROT_MPU1_MPU_STRUCT0_ATT for the details of bit fields.
0x40247E80 MPU region address. See PROT_MPU1_MPU_STRUCT0_ADDR for the details of bit fields.
0x40247E84 MPU region attributes. See PROT_MPU1_MPU_STRUCT0_ATT for the details of bit fields.
0x40247EA0 MPU region address. See PROT_MPU1_MPU_STRUCT0_ADDR for the details of bit fields.
0x40247EA4 MPU region attributes. See PROT_MPU1_MPU_STRUCT0_ATT for the details of bit fields.
0x40247EC0 MPU region address. See PROT_MPU1_MPU_STRUCT0_ADDR for the details of bit fields.
0x40247EC4 MPU region attributes. See PROT_MPU1_MPU_STRUCT0_ATT for the details of bit fields.
0x40247EE0 MPU region address. See PROT_MPU1_MPU_STRUCT0_ADDR for the details of bit fields.
0x40247EE4 MPU region attributes. See PROT_MPU1_MPU_STRUCT0_ATT for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
394
PROT_SMPU_MS0_CTL
7.1.1 PROT_SMPU_MS0_CTL
Address = 0x40240000 Master 0 protection context control Address: 0x40240000 Retention: Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:2]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:10]
Bits
23
22
21
20
19
SW Access
RW
HW Access
R
Name
PC_MASK_15_TO_1 [23:17]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
0
RW
RW
R
R
NS
P
10
9
8
RW
R
PRIO [9:8]
18
17
16
R
R
PC_MASK_ 0
26
25
24
Bits 23 : 17
Name PC_MASK_15_TO_1
16
PC_MASK_0
Description
Protection context mask for protection contexts "15" down to "1". Bit PC_MASK_15_TO_1[i] indicates if the MPU MS_CTL.PC[3:0] protection context field can be set to the value "i+1": - PC_MASK_15_TO_1[i] is '0': MPU MS_CTL.PC[3:0] can NOT be set to "i+1"; and PC[3:0] is not changed. If the protection context of the write transfer is "0", protection is not applied and PC[3:0] can be changed. - PC_MASK_15_TO_1[i] is '1': MPU MS_CTL.PC[3:0] can be set to "i+1". Note: When CPUSS_CM0_PC_CTL.VALID[i] is '1' (the associated protection context handler is valid), write transfers to PC_MASK_15_TO_1[i-1] always write '0', regardless of data written. This ensures that when valid protection context handlers are used to enter protection contexts 1, 2 or 3 through (HW modifies MPU MS_CTL.PC[3:0] on entry of the handler), it is NOT possible for SW to enter those protection contexts (SW modifies MPU MS_CTL.PC[3:0]). Default Value: 0
Protection context mask for protection context "0". This field is a constant '0': - PC_MASK_0 is '0': MPU MS_CTL.PC[3:0] can NOT be set to "0" and PC[3:0] is not changed. If the protection context of the write transfer is "0", protection is not applied and PC[3:0] can be changed. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
395
PROT_SMPU_MS0_CTL
7.1.1
9 : 8
1 0
PROT_SMPU_MS0_CTL (continued)
PRIO NS P
Device wide bus arbitration priority setting ("0": highest priority, "3": lowest priority). Notes: The AHB-Lite interconnect performs arbitration on the individual beats/transfers of a burst (this optimizes latency over locality/bandwidth). The AXI-Lite interconnects performs a single arbitration for the complete burst (this optimizes locality/bandwidth over latency). Masters with the same priority setting form a "priority group". Within a "priority group", round robin arbitration is performed. Default Value: 3
Security setting ('0': secure mode; '1': non-secure mode). Notes: This field is ONLY used for masters that do NOT provide their own secure/non-secure access control attribute. Note that the default/reset field value provides non-secure mode access capabilities to all masters. Default Value: 1
Privileged setting ('0': user mode; '1': privileged mode). Notes: This field is ONLY used for masters that do NOT provide their own user/privileged access control attribute. The default/reset field value provides privileged mode access capabilities. Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
396
PROT_SMPU_MS1_CTL
7.1.2 PROT_SMPU_MS1_CTL
Address = 0x40240004 Master 1 protection context control Address: 0x40240004 Retention: Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:2]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:10]
Bits
23
22
21
20
19
SW Access
RW
HW Access
R
Name
PC_MASK_15_TO_1 [23:17]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
Bits 23 : 17 16 9 : 8 1 0
Name PC_MASK_15_TO_1 PC_MASK_0 PRIO NS P
Description
See MS0_CTL.PC_MASK_15_TO_1. Default Value: 0
See MS0_CTL.PC_MASK_0. Default Value: 0
See MS0_CTL.PRIO Default Value: 3
See MS0_CTL.NS. Default Value: 1
See MS0_CTL.P. Default Value: 1
2
1
0
RW
RW
R
R
NS
P
10
9
8
RW
R
PRIO [9:8]
18
17
16
R
R
PC_MASK_ 0
26
25
24
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
397
PROT_SMPU_MS2_CTL
7.1.3 PROT_SMPU_MS2_CTL
Address = 0x40240008 Master 2 protection context control Address: 0x40240008 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:10]
9
8
RW
R
PRIO [9:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
R
HW Access
None
R
Name
None [23:17]
PC_MASK_ 0
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 16
9 : 8
Name PC_MASK_0
PRIO
Description
See MS0_CTL.PC_MASK_0. Default Value: 0
See MS0_CTL.PRIO Default Value: 3
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
398
PROT_SMPU_MS3_CTL
7.1.4 PROT_SMPU_MS3_CTL
Address = 0x4024000C Master 3 protection context control Address: 0x4024000C Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:10]
9
8
RW
R
PRIO [9:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
R
HW Access
None
R
Name
None [23:17]
PC_MASK_ 0
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 16
9 : 8
Name PC_MASK_0
PRIO
Description
See MS0_CTL.PC_MASK_0. Default Value: 0
See MS0_CTL.PRIO Default Value: 3
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
399
PROT_SMPU_MS14_CTL
7.1.5 PROT_SMPU_MS14_CTL
Address = 0x40240038 Master 14 protection context control Address: 0x40240038 Retention: Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:2]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:10]
Bits
23
22
21
20
19
SW Access
RW
HW Access
R
Name
PC_MASK_15_TO_1 [23:17]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
Bits 23 : 17 16 9 : 8 1 0
Name PC_MASK_15_TO_1 PC_MASK_0 PRIO NS P
Description
See MS0_CTL.PC_MASK_15_TO_1. Default Value: 0
See MS0_CTL.PC_MASK_0. Default Value: 0
See MS0_CTL.PRIO Default Value: 3
See MS0_CTL.NS. Default Value: 1
See MS0_CTL.P. Default Value: 1
2
1
0
RW
RW
R
R
NS
P
10
9
8
RW
R
PRIO [9:8]
18
17
16
R
R
PC_MASK_ 0
26
25
24
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
400
PROT_SMPU_MS15_CTL
7.1.6 PROT_SMPU_MS15_CTL
Address = 0x4024003C Master 15 protection context control Address: 0x4024003C Retention: Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:2]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:10]
Bits
23
22
21
20
19
SW Access
RW
HW Access
R
Name
PC_MASK_15_TO_1 [23:17]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
Bits 23 : 17 16 9 : 8 1 0
Name PC_MASK_15_TO_1 PC_MASK_0 PRIO NS P
Description
See MS0_CTL.PC_MASK_15_TO_1. Default Value: 0
See MS0_CTL.PC_MASK_0. Default Value: 0
See MS0_CTL.PRIO Default Value: 3
See MS0_CTL.NS. Default Value: 1
See MS0_CTL.P. Default Value: 1
2
1
0
RW
RW
R
R
NS
P
10
9
8
RW
R
PRIO [9:8]
18
17
16
R
R
PC_MASK_ 0
26
25
24
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
401
PROT_SMPU_SMPU_STRUCT0_ADDR0
7.1.7 PROT_SMPU_SMPU_STRUCT0_ADDR0
Address = 0x40242000 SMPU region address 0 (slave structure) Address: 0x40242000 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
Name ADDR24
Description
This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT0.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is "15") is 64 KByte aligned, and ADDR24[7:0] are ignored. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
402
PROT_SMPU_SMPU_STRUCT0_ADDR0
7.1.7
7 : 0
PROT_SMPU_SMPU_STRUCT0_ADDR0 (continued)
SUBREGION_DISABLE
This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. E.g., a 64 KByte address region (ATT0.REGION_SIZE is "15") has eight 8 KByte subregions. The access control as defined by ATT0 applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
403
PROT_SMPU_SMPU_STRUCT0_ATT0
7.1.8 PROT_SMPU_SMPU_STRUCT0_ATT0
Address = 0x40242004 SMPU region attributes 0 (slave structure) Address: 0x40242004 Retention: Retained
Bits
7
6
5
4
3
2
1
SW Access
None
RW
RW
RW
RW
RW
RW
HW Access
None
R
R
R
R
R
R
Name
None
NS
PX
PW
PR
UX
UW
Bits
15
14
13
12
11
10
9
SW Access
RW
HW Access
R
Name
PC_MASK_15_TO_1 [15:9]
Bits SW Access HW Access
Name
Bits SW Access HW Access
Name
23
22
21
31 RW R ENABLED
30 RW R PC_MATCH
29 None None None
20
19
18
17
None
None
None [23:16]
28
27
26
25
RW
R
REGION_SIZE [28:24]
0 RW R UR
8 R R PC_MASK_ 0 16
24
Bits
Name
31
ENABLED
30
PC_MATCH
Description
Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. Note: a disabled address region performs logic gating to reduce dynamic power consumption. Default Value: 0
This field specifies if the PC field participates in the "matching" process or the "access evaluation" process: '0': PC field participates in "access evaluation". '1': PC field participates in "matching". Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
404
PROT_SMPU_SMPU_STRUCT0_ATT0
7.1.8
28 : 24
15 : 9 8 6 5 4 3 2
PROT_SMPU_SMPU_STRUCT0_ATT0 (continued)
REGION_SIZE
PC_MASK_15_TO_1 PC_MASK_0 NS PX PW PR UX
This field specifies the region size: "0"-"6": Undefined. "7": 256 B region "8": 512 B region "9": 1 KB region "10": 2 KB region "11": 4 KB region "12": 8 KB region "13": 16 KB region "14": 32 KB region "15": 64 KB region "16": 128 KB region "17": 256 KB region "18": 512 KB region "19": 1 MB region "20": 2 MB region "21": 4 MB region "22": 8 MB region "23": 16 MB region "24": 32 MB region "25": 64 MB region "26": 128 MB region "27": 256 MB region "28": 512 MB region "39": 1 GB region "30": 2 GB region "31": 4 GB region Default Value: Undefined
This field specifies protection context identifier based access control. Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed. Default Value: Undefined
This field specifies protection context identifier based access control for protection context "0". Default Value: 1
Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). Default Value: Undefined
Privileged execute enable: '0': Disabled (privileged, execute accesses are NOT allowed). '1': Enabled (privileged, execute accesses are allowed). Default Value: Undefined
Privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed). Default Value: Undefined
Privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed). Default Value: Undefined
User execute enable: '0': Disabled (user, execute accesses are NOT allowed). '1': Enabled (user, execute accesses are allowed). Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
405
PROT_SMPU_SMPU_STRUCT0_ATT0
7.1.8
1
0
PROT_SMPU_SMPU_STRUCT0_ATT0 (continued)
UW
User write enable:
'0': Disabled (user, write accesses are NOT allowed).
'1': Enabled (user, write accesses are allowed).
Default Value: Undefined
UR
User read enable:
'0': Disabled (user, read accesses are NOT allowed).
'1': Enabled (user, read accesses are allowed).
Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
406
PROT_SMPU_SMPU_STRUCT0_ADDR1
7.1.9 PROT_SMPU_SMPU_STRUCT0_ADDR1
Address = 0x40242020 SMPU region address 1 (master structure) Address: 0x40242020 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description
This field specifies the most significant bits of the 32-bit address of an address region. "ADDR_DEF1": base address of structure. Note: this field is read-only. Default Value: 4203552
This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only. Default Value: 252
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
407
PROT_SMPU_SMPU_STRUCT0_ATT1
7.1.10 PROT_SMPU_SMPU_STRUCT0_ATT1
Address = 0x40242024 SMPU region attributes 1 (master structure) Address: 0x40242024 Retention: Retained
Bits
7
6
5
4
3
2
1
SW Access
None
RW
R
RW
R
R
RW
HW Access
None
R
R
R
R
R
R
Name
None
NS
PX
PW
PR
UX
UW
Bits
15
14
13
12
11
10
9
SW Access
RW
HW Access
R
Name
PC_MASK_15_TO_1 [15:9]
Bits SW Access HW Access
Name
Bits SW Access HW Access
Name
23
22
21
31 RW R ENABLED
30 RW R PC_MATCH
29 None None None
20
19
18
17
None
None
None [23:16]
28
27
26
25
R
R
REGION_SIZE [28:24]
0 R R UR 8 R R PC_MASK_ 0 16
24
Bits
Name
31
ENABLED
30
PC_MATCH
28 : 24
REGION_SIZE
Description
Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. Default Value: 0
This field specifies if the PC field participates in the "matching" process or the "access evaluation" process: '0': PC field participates in "access evaluation". '1': PC field participates in "matching". Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'. Default Value: Undefined
This field specifies the region size: "7": 256 B region (8 32 B subregions) Note: this field is read-only. Default Value: 7
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
408
PROT_SMPU_SMPU_STRUCT0_ATT1
7.1.10
15 : 9 8 6 5
4 3
2
1 0
PROT_SMPU_SMPU_STRUCT0_ATT1 (continued)
PC_MASK_15_TO_1 PC_MASK_0 NS PX PW PR UX UW UR
This field specifies protection context identifier based access control. Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed. Default Value: Undefined
This field specifies protection context identifier based access control for protection context "0". Default Value: 1
Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). Default Value: Undefined
Privileged execute enable: '0': Disabled (privileged, execute accesses are NOT allowed). '1': Enabled (privileged, execute accesses are allowed). Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed. Default Value: 0
Privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed). Default Value: Undefined
Privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed). Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed. Default Value: 1
User execute enable: '0': Disabled (user, execute accesses are NOT allowed). '1': Enabled (user, execute accesses are allowed). Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed. Default Value: 0
User write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed). Default Value: Undefined
User read enable: '0': Disabled (user, read accesses are NOT allowed). '1': Enabled (user, read accesses are allowed). Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed. Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
409
PROT_SMPU_SMPU_STRUCT1_ADDR1
7.1.11 PROT_SMPU_SMPU_STRUCT1_ADDR1
Address = 0x40242060 SMPU region address 1 (master structure) Address: 0x40242060 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description
This field specifies the most significant bits of the 32-bit address of an address region. "ADDR_DEF1": base address of structure. Note: this field is read-only. Default Value: 4203552
This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only. Default Value: 243
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
410
PROT_SMPU_SMPU_STRUCT2_ADDR1
7.1.12 PROT_SMPU_SMPU_STRUCT2_ADDR1
Address = 0x402420A0 SMPU region address 1 (master structure) Address: 0x402420A0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description
This field specifies the most significant bits of the 32-bit address of an address region. "ADDR_DEF1": base address of structure. Note: this field is read-only. Default Value: 4203552
This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only. Default Value: 207
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
411
PROT_SMPU_SMPU_STRUCT3_ADDR1
7.1.13 PROT_SMPU_SMPU_STRUCT3_ADDR1
Address = 0x402420E0 SMPU region address 1 (master structure) Address: 0x402420E0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description
This field specifies the most significant bits of the 32-bit address of an address region. "ADDR_DEF1": base address of structure. Note: this field is read-only. Default Value: 4203552
This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only. Default Value: 63
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
412
PROT_SMPU_SMPU_STRUCT4_ADDR1
7.1.14 PROT_SMPU_SMPU_STRUCT4_ADDR1
Address = 0x40242120 SMPU region address 1 (master structure) Address: 0x40242120 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description
This field specifies the most significant bits of the 32-bit address of an address region. "ADDR_DEF1": base address of structure. Note: this field is read-only. Default Value: 4203553
This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only. Default Value: 252
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
413
PROT_SMPU_SMPU_STRUCT5_ADDR1
7.1.15 PROT_SMPU_SMPU_STRUCT5_ADDR1
Address = 0x40242160 SMPU region address 1 (master structure) Address: 0x40242160 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description
This field specifies the most significant bits of the 32-bit address of an address region. "ADDR_DEF1": base address of structure. Note: this field is read-only. Default Value: 4203553
This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only. Default Value: 243
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
414
PROT_SMPU_SMPU_STRUCT6_ADDR1
7.1.16 PROT_SMPU_SMPU_STRUCT6_ADDR1
Address = 0x402421A0 SMPU region address 1 (master structure) Address: 0x402421A0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description
This field specifies the most significant bits of the 32-bit address of an address region. "ADDR_DEF1": base address of structure. Note: this field is read-only. Default Value: 4203553
This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only. Default Value: 207
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
415
PROT_SMPU_SMPU_STRUCT7_ADDR1
7.1.17 PROT_SMPU_SMPU_STRUCT7_ADDR1
Address = 0x402421E0 SMPU region address 1 (master structure) Address: 0x402421E0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description
This field specifies the most significant bits of the 32-bit address of an address region. "ADDR_DEF1": base address of structure. Note: this field is read-only. Default Value: 4203553
This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only. Default Value: 63
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
416
PROT_SMPU_SMPU_STRUCT8_ADDR1
7.1.18 PROT_SMPU_SMPU_STRUCT8_ADDR1
Address = 0x40242220 SMPU region address 1 (master structure) Address: 0x40242220 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description
This field specifies the most significant bits of the 32-bit address of an address region. "ADDR_DEF1": base address of structure. Note: this field is read-only. Default Value: 4203554
This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only. Default Value: 252
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
417
PROT_SMPU_SMPU_STRUCT9_ADDR1
7.1.19 PROT_SMPU_SMPU_STRUCT9_ADDR1
Address = 0x40242260 SMPU region address 1 (master structure) Address: 0x40242260 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description
This field specifies the most significant bits of the 32-bit address of an address region. "ADDR_DEF1": base address of structure. Note: this field is read-only. Default Value: 4203554
This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only. Default Value: 243
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
418
PROT_SMPU_SMPU_STRUCT10_ADDR1
7.1.20 PROT_SMPU_SMPU_STRUCT10_ADDR1
Address = 0x402422A0 SMPU region address 1 (master structure) Address: 0x402422A0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description
This field specifies the most significant bits of the 32-bit address of an address region. "ADDR_DEF1": base address of structure. Note: this field is read-only. Default Value: 4203554
This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only. Default Value: 207
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
419
PROT_SMPU_SMPU_STRUCT11_ADDR1
7.1.21 PROT_SMPU_SMPU_STRUCT11_ADDR1
Address = 0x402422E0 SMPU region address 1 (master structure) Address: 0x402422E0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description
This field specifies the most significant bits of the 32-bit address of an address region. "ADDR_DEF1": base address of structure. Note: this field is read-only. Default Value: 4203554
This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only. Default Value: 63
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
420
PROT_SMPU_SMPU_STRUCT12_ADDR1
7.1.22 PROT_SMPU_SMPU_STRUCT12_ADDR1
Address = 0x40242320 SMPU region address 1 (master structure) Address: 0x40242320 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description
This field specifies the most significant bits of the 32-bit address of an address region. "ADDR_DEF1": base address of structure. Note: this field is read-only. Default Value: 4203555
This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only. Default Value: 252
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
421
PROT_SMPU_SMPU_STRUCT13_ADDR1
7.1.23 PROT_SMPU_SMPU_STRUCT13_ADDR1
Address = 0x40242360 SMPU region address 1 (master structure) Address: 0x40242360 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description
This field specifies the most significant bits of the 32-bit address of an address region. "ADDR_DEF1": base address of structure. Note: this field is read-only. Default Value: 4203555
This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only. Default Value: 243
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
422
PROT_SMPU_SMPU_STRUCT14_ADDR1
7.1.24 PROT_SMPU_SMPU_STRUCT14_ADDR1
Address = 0x402423A0 SMPU region address 1 (master structure) Address: 0x402423A0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description
This field specifies the most significant bits of the 32-bit address of an address region. "ADDR_DEF1": base address of structure. Note: this field is read-only. Default Value: 4203555
This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only. Default Value: 207
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
423
PROT_SMPU_SMPU_STRUCT15_ADDR1
7.1.25 PROT_SMPU_SMPU_STRUCT15_ADDR1
Address = 0x402423E0 SMPU region address 1 (master structure) Address: 0x402423E0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
7 : 0
Name ADDR24
SUBREGION_DISABLE
Description
This field specifies the most significant bits of the 32-bit address of an address region. "ADDR_DEF1": base address of structure. Note: this field is read-only. Default Value: 4203555
This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1. Note: this field is read-only. Default Value: 63
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
424
PROT_MPU0_MS_CTL
7.1.26 PROT_MPU0_MS_CTL
Address = 0x40244000 Master control Address: 0x40244000 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:4]
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
SW Access
HW Access
Name
22
21
None
None
None [23:20]
Bits
31
30
29
SW Access
HW Access
Name
4
3
2
1
0
RW
RW
PC [3:0]
12
11
10
9
8
None
None
None [15:8]
20
19
18
17
16
RW
RW
PC_SAVED [19:16]
28
27
26
25
24
None
None
None [31:24]
Bits 19 : 16
Name PC_SAVED
3 : 0
PC
Description
Saved protection context. Modifications to this field are constrained by the associated MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields. Default Value: 0
Active protection context. Modifications to this field are constrained by the associated MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields. In addition, a write transfer with protection context "0" can change this field. The CM0+ CPU PC field is writable by HW and SW (all other PC fields are only writable by SW). On entry of a Cypress "trusted" exception/interrupt handler (the handler start address equals CPUSS CM0_PC0_HANDLER.ADDR): - PC_SAVED is not changed if PC is "0". PC_SAVED is set to PC if PC is not "0". - PC is set to "0". On entry of any other exception/interrupt handler (the handler start address does not equal CPUSS CM0_PC0_HANDLER.ADDR): - PC_SAVED is not changed. - PC is set to PC_SAVED. Protection context "0" is considered a special protection context in trusted systems and should be reserved for Cypress "trusted" code execution. In addition, a write transfer with protection context "0" can change this field. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
425
PROT_MPU1_MS_CTL
7.1.27 PROT_MPU1_MS_CTL
Address = 0x40244400 Master control Address: 0x40244400 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
RW
Name
None [7:4]
PC [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 3 : 0
Name PC
Description
Active protection context. Modifications to this field are constrained by the associated MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields. In addition, a write transfer with protection context "0" can change this field. The CM0+ CPU PC field is writable by HW and SW (all other PC fields are only writable by SW). On entry of a Cypress "trusted" exception/interrupt handler (the handler start address equals CPUSS CM0_PC0_HANDLER.ADDR): - PC_SAVED is not changed if PC is "0". PC_SAVED is set to PC if PC is not "0". - PC is set to "0". On entry of any other exception/interrupt handler (the handler start address does not equal CPUSS CM0_PC0_HANDLER.ADDR): - PC_SAVED is not changed. - PC is set to PC_SAVED. Protection context "0" is considered a special protection context in trusted systems and should be reserved for Cypress "trusted" code execution. In addition, a write transfer with protection context "0" can change this field. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
426
PROT_MPU1_MPU_STRUCT0_ADDR
7.1.28 PROT_MPU1_MPU_STRUCT0_ADDR
Address = 0x40244600 MPU region address Address: 0x40244600 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
SUBREGION_DISABLE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
ADDR24 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
ADDR24 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
ADDR24 [31:24]
Bits 31 : 8
Name ADDR24
Description
This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is "15") is 64 KByte aligned, and ADDR24[7:0] are ignored. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
427
PROT_MPU1_MPU_STRUCT0_ADDR
7.1.28
7 : 0
PROT_MPU1_MPU_STRUCT0_ADDR (continued)
SUBREGION_DISABLE
This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable: Bit 0: subregion 0 disable. Bit 1: subregion 1 disable. Bit 2: subregion 2 disable. Bit 3: subregion 3 disable. Bit 4: subregion 4 disable. Bit 5: subregion 5 disable. Bit 6: subregion 6 disable. Bit 7: subregion 7 disable. E.g., a 64 KByte address region (REGION_SIZE is "15") has eight 8 KByte subregions. The access control as defined by MPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
428
PROT_MPU1_MPU_STRUCT0_ATT
7.1.29 PROT_MPU1_MPU_STRUCT0_ATT
Address = 0x40244604 MPU region attrributes Address: 0x40244604 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
RW
RW
RW
RW
RW
RW
HW Access
None
R
R
R
R
R
R
R
Name
None
NS
PX
PW
PR
UX
UW
UR
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
None
RW
HW Access
R
None
R
Name
ENABLED
None [30:29]
REGION_SIZE [28:24]
Bits
Name
31
ENABLED
Description
Region enable: '0': Disabled. A disabled region will never result in a match on the bus transfer address. '1': Enabled. Note: a disabled address region performs logic gating to reduce dynamic power consumption. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
429
PROT_MPU1_MPU_STRUCT0_ATT
7.1.29
28 : 24
6 5 4 3 2 1
PROT_MPU1_MPU_STRUCT0_ATT (continued)
REGION_SIZE
NS PX PW PR UX UW
This field specifies the region size: "0"-"6": Undefined. "7": 256 B region "8": 512 B region "9": 1 KB region "10": 2 KB region "11": 4 KB region "12": 8 KB region "13": 16 KB region "14": 32 KB region "15": 64 KB region "16": 128 KB region "17": 256 KB region "18": 512 KB region "19": 1 MB region "20": 2 MB region "21": 4 MB region "22": 8 MB region "23": 16 MB region "24": 32 MB region "25": 64 MB region "26": 128 MB region "27": 256 MB region "28": 512 MB region "39": 1 GB region "30": 2 GB region "31": 4 GB region Default Value: Undefined
Non-secure: '0': Secure (secure accesses allowed, non-secure access NOT allowed). '1': Non-secure (both secure and non-secure accesses allowed). Default Value: Undefined
Privileged execute enable: '0': Disabled (privileged, execute accesses are NOT allowed). '1': Enabled (privileged, execute accesses are allowed). Default Value: Undefined
Privileged write enable: '0': Disabled (privileged, write accesses are NOT allowed). '1': Enabled (privileged, write accesses are allowed). Default Value: Undefined
Privileged read enable: '0': Disabled (privileged, read accesses are NOT allowed). '1': Enabled (privileged, read accesses are allowed). Default Value: Undefined
User execute enable: '0': Disabled (user, execute accesses are NOT allowed). '1': Enabled (user, execute accesses are allowed). Default Value: Undefined
User write enable: '0': Disabled (user, write accesses are NOT allowed). '1': Enabled (user, write accesses are allowed). Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
430
PROT_MPU1_MPU_STRUCT0_ATT
7.1.29
0
PROT_MPU1_MPU_STRUCT0_ATT (continued)
UR
User read enable:
'0': Disabled (user, read accesses are NOT allowed).
'1': Enabled (user, read accesses are allowed).
Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
431
8 Flash Controller Registers
This section discusses the Flash Controller registers. It lists all the registers in mapping tables, in address order.
8.1 Register Details
Register FLASHC_FLASH_CTL FLASHC_FLASH_PWR_CTL FLASHC_FLASH_CMD FLASHC_BIST_CTL FLASHC_BIST_CMD FLASHC_BIST_ADDR_START FLASHC_BIST_DATA0 FLASHC_BIST_DATA1 FLASHC_BIST_DATA2 FLASHC_BIST_DATA3 FLASHC_BIST_DATA_ACT0 FLASHC_BIST_DATA_ACT1 FLASHC_BIST_DATA_ACT2 FLASHC_BIST_DATA_ACT3 FLASHC_BIST_DATA_EXP0 FLASHC_BIST_DATA_EXP1 FLASHC_BIST_DATA_EXP2 FLASHC_BIST_DATA_EXP3 FLASHC_BIST_ADDR FLASHC_BIST_STATUS FLASHC_CM0_CA_CTL0 FLASHC_CM0_CA_CTL1 FLASHC_CM0_CA_CTL2 FLASHC_CM0_CA_CMD FLASHC_CM0_CA_STATUS0 FLASHC_CM0_CA_STATUS1 FLASHC_CM0_CA_STATUS2
Address 0x40250000 0x40250004 0x40250008 0x40250100 0x40250104 0x40250108 0x4025010C 0x40250110 0x40250114 0x40250118 0x4025012C 0x40250130 0x40250134 0x40250138 0x4025014C 0x40250150 0x40250154 0x40250158 0x4025016C 0x40250170 0x40250400 0x40250404 0x40250408 0x4025040C 0x40250440 0x40250444 0x40250448
Description Control Flash power control Command BIST control BIST command BIST address start register BIST data register(s) BIST data register(s). See FLASHC_BIST_DATA0 for the details of bit fields. BIST data register(s). See FLASHC_BIST_DATA0 for the details of bit fields. BIST data register(s). See FLASHC_BIST_DATA0 for the details of bit fields. BIST data actual register(s) BIST data actual register(s). See FLASHC_BIST_DATA_ACT0 for the details of bit fields. BIST data actual register(s). See FLASHC_BIST_DATA_ACT0 for the details of bit fields. BIST data actual register(s). See FLASHC_BIST_DATA_ACT0 for the details of bit fields. BIST data expected register(s) BIST data expected register(s). See FLASHC_BIST_DATA_EXP0 for the details of bit fields. BIST data expected register(s). See FLASHC_BIST_DATA_EXP0 for the details of bit fields. BIST data expected register(s). See FLASHC_BIST_DATA_EXP0 for the details of bit fields. BIST address register BIST status register CM0+ cache control CM0+ cache control CM0+ cache control CM0+ cache command CM0+ cache status 0 CM0+ cache status 1 CM0+ cache status 2
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
432
Flash Controller Registers
Register
Address
Description
FLASHC_CM4_CA_CTL0
0x40250480 CM4 cache control
FLASHC_CM4_CA_CTL1
0x40250484 CM4 cache control
FLASHC_CM4_CA_CTL2
0x40250488 CM4 cache control
FLASHC_CM4_CA_CMD
0x4025048C CM4 cache command
FLASHC_CM4_CA_STATUS0
0x402504C0 CM4 cache status 0
FLASHC_CM4_CA_STATUS1
0x402504C4 CM4 cache status 1
FLASHC_CM4_CA_STATUS2
0x402504C8 CM4 cache status 2
FLASHC_CRYPTO_BUFF_CTL
0x40250500 Cryptography buffer control
FLASHC_CRYPTO_BUFF_CMD
0x40250508 Cryptography buffer command
FLASHC_DW0_BUFF_CTL
0x40250580 Datawire 0 buffer control
FLASHC_DW0_BUFF_CMD
0x40250588 Datawire 0 buffer command
FLASHC_DW1_BUFF_CTL
0x40250600 Datawire 1 buffer control
FLASHC_DW1_BUFF_CMD
0x40250608 Datawire 1 buffer command
FLASHC_DAP_BUFF_CTL
0x40250680 Debug access port buffer control
FLASHC_DAP_BUFF_CMD
0x40250688 Debug access port buffer command
FLASHC_EXT_MS0_BUFF_CTL
0x40250700 External master 0 buffer control
FLASHC_EXT_MS0_BUFF_CMD
0x40250708 External master 0 buffer command
FLASHC_EXT_MS1_BUFF_CTL
0x40250780 External master 1 buffer control
FLASHC_EXT_MS1_BUFF_CMD
0x40250788 External master 1 buffer command
FLASHC_FM_CTL
0x4025F000 Flash macro control
FLASHC_STATUS
0x4025F004 Status
FLASHC_FM_ADDR
0x4025F008 Flash macro address
FLASHC_GEOMETRY
0x4025F00C Regular flash geometry
FLASHC_GEOMETRY_SUPERVISORY 0x4025F010 Supervisory flash geometry
FLASHC_TIMER_CTL
0x4025F014 Timer control
FLASHC_ANA_CTL0
0x4025F018 Analog control 0
FLASHC_ANA_CTL1
0x4025F01C Analog control 1
FLASHC_GEOMETRY_GEN
0x4025F020 N/A, DNU
FLASHC_TEST_CTL
0x4025F024 Test mode control
FLASHC_WAIT_CTL
0x4025F028 Wiat State control
FLASHC_MONITOR_STATUS
0x4025F02C Monitor Status
FLASHC_SCRATCH_CTL
0x4025F030 Scratch Control
FLASHC_HV_CTL
0x4025F034 High voltage control
FLASHC_ACLK_CTL
0x4025F038 Aclk control
FLASHC_INTR
0x4025F03C Interrupt
FLASHC_INTR_SET
0x4025F040 Interrupt set
FLASHC_INTR_MASK
0x4025F044 Interrupt mask
FLASHC_INTR_MASKED
0x4025F048 Interrupt masked
FLASHC_FM_HV_DATA_ALL
0x4025F04C Flash macro high Voltage page latches data (for all page latches)
FLASHC_CAL_CTL0
0x4025F050 Cal control BG LO trim bits
FLASHC_CAL_CTL1
0x4025F054 Cal control BG HI trim bits
FLASHC_CAL_CTL2
0x4025F058 Cal control BG LO&HI ipref trim, ref sel, fm_active, turbo_ext
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
433
Register FLASHC_CAL_CTL3 FLASHC_BOOKMARK FLASHC_RED_CTL01 FLASHC_RED_CTL23 FLASHC_RED_CTL45 FLASHC_RED_CTL67 FLASHC_RED_CTL_SM01 FLASHC_TM_CMPR0
FLASHC_FM_HV_DATA0
FLASHC_FM_MEM_DATA0
Flash Controller Registers
Address
Description
0x4025F05C Cal control osc trim bits, idac, sdac, itim, bdac.
0x4025F060 Bookmark register - keeps the current FW HV seq
0x4025F080 Redundancy Control normal sectors 0,1
0x4025F084 Redundancy Controll normal sectors 2,3
0x4025F088 Redundancy Controll normal sectors 4,5
0x4025F08C Redundancy Controll normal sectors 6,7
0x4025F090 Redundancy Controll special sectors 0,1
0x4025F100
Do Not Use. This is the starting address of a register bank containing 32 registers (FLASHC_TM_CMPR0 to FLASHC_TM_CMPR31).
0x4025F800
Flash macro high Voltage page latches data. This is the starting address of a register bank containing 128 registers (FLASHC_FM_HV_DATA0 to FLASHC_FM_HV_DATA127).
0x4025FC00
Flash macro memory sense amplifier and column decoder data. This is the starting address of a register bank containing 128 registers (FLASHC_FM_MEM_DATA0 to FLASHC_FM_MEM_DATA127).
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
434
FLASHC_FLASH_CTL
8.1.1 FLASHC_FLASH_CTL
Address = 0x40250000 Control Address: 0x40250000 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:4]
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4
3
12
11
None
None
None [15:9]
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
Bits
Name
Description
2
1
RW
R
MAIN_WS [3:0]
10
9
18
17
0
8 RW R REMAP 16
26
25
24
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
435
0x40250000 FLASHC_FLASH_CTL
8.1.1
8
3 : 0
FLASHC_FLASH_CTL (continued)
REMAP MAIN_WS
Specifies remapping of FLASH macro main region. 0: No remapping. 1: Remapping. The highest address bit of the FLASH main region is inverted. This effectively remaps the location of FLASH main region physical sectors in the logical address space. In other words, the higher half physical sectors are swapped with the lower half physical sectors. Note: remapping only affects reading of the FLASH main region (over the R interface). It does NOT affect programming/erasing of the FLASH memory region (over the C interface). E.g., for a 512 KB / 4 Mb main region, the logical address space ranges from [0x1000:0000, 0x1007:ffff] (the highest bit if the FLASH main region is bit 18). The memory has four physical sectors: sectors 0, 1, 2 and 3. If REMAP is '0', the physical regions logical addresses are as follows: - The physical region 0: [0x1000:0000, 0x1001:ffff]. - The physical region 1: [0x1002:0000, 0x1003:ffff]. - The physical region 2: [0x1004:0000, 0x1005:ffff]. - The physical region 3: [0x1006:0000, 0x1007:ffff]. If REMAP is '1', the physical regions logical addresses are as follows: - The physical region 0: [0x1004:0000, 0x1005:ffff]. - The physical region 1: [0x1006:0000, 0x1007:ffff]. - The physical region 2: [0x1000:0000, 0x1001:ffff]. - The physical region 3: [0x1002:0000, 0x1003:ffff]. Note: when the REMAP is changed, SW should invalidate the caches and buffers. Default Value: 0
FLASH macro main interface wait states: 0: 0 wait states. ... 15: 15 wait states Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
436
FLASHC_FLASH_PWR_CTL
8.1.2 FLASHC_FLASH_PWR_CTL
Address = 0x40250004 Flash power control Address: 0x40250004 Retention: Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:2]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
1
ENABLE_HV
0
ENABLE
Description
Controls "enable_hv" pin of the Flash memory. Default Value: 1
Controls "enable" pin of the Flash memory. Default Value: 1
2
1
0
RW
RW
R
R
ENABLE_HV
ENABLE
10
9
8
18
17
16
26
25
24
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
437
0x40250008 FLASHC_FLASH_CMD
8.1.3 FLASHC_FLASH_CMD
Address = 0x40250008 Command Address: 0x40250008 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW1S
HW Access
None
RW1C
Name
None [7:1]
INV
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
INV
Description
FLASH cache and buffer invalidation for ALL cache and buffers. SW writes a '1' to clear the cache and buffers. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. The caches' LRU structures are also reset to their default state. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
438
FLASHC_BIST_CTL
8.1.4 FLASHC_BIST_CTL
Address = 0x40250100 BIST control Address: 0x40250100 Retention: Not Retained
Bits
7
6
5
4
3
2
SW Access
RW
RW
RW
RW
RW
RW
HW Access
R
R
R
R
R
R
Name
STOP_ON_ ERROR
INCR_DECR_BOTH
ADDR_COMPLIMENT_ENA
BLED
ADDR_START _ENABLED
ROW_FIRST
UP
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
1
0
RW
R
OPCODE [1:0]
9
8
17
16
25
24
Bits
Name
Description
7
STOP_ON_ERROR
Specifies the BIST to continue indefinitely, regardless of occurrence of errors or not.
0: BIST controller doesn't stop on the data failures, it continues regardless of the errors.
1: BIST controller stops on when the first data failure is encountered.
Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
439
0x40250100 FLASHC_BIST_CTL
8.1.4
6
5
4 3 2
FLASHC_BIST_CTL (continued)
INCR_DECR_BOTH
Specifies to generate patterns where both column address and row address are incremented/ decremented simultaneously. 0: Generate normal increment/decrement patterns. 1: Generate address patterns with both row and column address changing. Example: With UP = 1 and ROW_FIRST = 0 00_00 01_01 10_10 11_11 00_01 01_10 10_11 11_00 00_10 ... Default Value: 0
ADDR_COMPLIMENT_ENABLED
Specifies to generate address compliment patterns. 0: Generate normal increment/decrement patterns. 1: Generate address patterns which interleaves compliment of previous address in between. Example: The following is an example pattern, With UP=1 and ROW_FIRST =0 00_00 11_11 00_01 11_10 00_10 11_01 ... Default Value: 0
ADDR_START_ENABLED
Specifies Flash BIST start addresses: '0': Row and column addresses start with their maximum/minimum values. '1': Row and column addresses start with their values as specified by BIST_ADDR_START. This feature is supported only for simple increment/decrement patterns. It is not supported with address compliment pattern (BIST_CTL.ADDR_COMPLIMENT_ENABLED) or address pattern which increments/decrements both row address and column address (BIST_CTL.INCR_DECR_BOTH) for every read. Default Value: 0
ROW_FIRST
Specifies how the Flash BIST addresses are generated: '0': Column address is incremented/decremented till it reaches its maximum/minimum value. Once it reach its maximum/minimum value, it is set to its minimum/maximum value and only then is the row address incremented/decremented. '1': Row address is incremented/decremented till it reaches its maximum/minimum value. Once it reach its maximum/minimum value, it is set to its minimum/maximum value and only then is the column address incremented/decremented. Default Value: 0
UP
Specifies direction in which Flash BIST steps through addresses:
0: BIST steps through the Flash from the maximum row and column addresses (as specified by
a design time configuration parameter when ADDR_START_ENABLED is "0" and as specified
by BIST_ADDR_START when ADDR_START_ENABLED is "1") to the minimum row and col-
umn addresses.
1: BIST steps through the Flash from the minimum row and column addresses ("0" when AD-
DR_START_ENABLED is "0" and as specified by BIST_ADDR_START when AD-
DR_START_ENABLED is "1'" to the maximum row and column addresses.
Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
440
0x40250100 FLASHC_BIST_CTL
8.1.4
1 : 0
FLASHC_BIST_CTL (continued)
OPCODE
This field specifies how the data check should be performed after reading the data from Flash memory. 0: Read the Flash and compare the output to BIST_DATA (R0). 1: Read the Flash and compare the output to the binary complement of BIST_DATA (R1). 3: Read the Flash and compare with BIST_DATA[] and compliment of BIST_DATA alternately (R01). The expected data of the first read is BIST_DATA, expected data of the second read is binary compliment of BIST_DATA, third read expected data is BIST_DATA, fourth read expected data is binary compliment of BIST_DATA and so on. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
441
0x40250104 FLASHC_BIST_CMD
8.1.5 FLASHC_BIST_CMD
Address = 0x40250104 BIST command Address: 0x40250104 Retention: Not Retained
Bits
7
6
5
4
3
2
1
SW Access
None
HW Access
None
Name
None [7:1]
Bits
15
14
13
12
11
10
9
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
START
Description
1: Start FLASH BIST. Hardware set this field to '0' when BIST is completed. Default Value: 0
0 RW RW1C START
8
16
24
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
442
FLASHC_BIST_ADDR_START
8.1.6 FLASHC_BIST_ADDR_START
Address = 0x40250108 BIST address start register Address: 0x40250108 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
COL_ADDR_START [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
COL_ADDR_START [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
ROW_ADDR_START [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
ROW_ADDR_START [31:24]
Bits 31 : 16
Name ROW_ADDR_START
15 : 0
COL_ADDR_START
Description
Row start address. Useful to apply BIST to a part of an Flash. The value of this field should be in a legal range (a value outside of the legal range has an undefined result, and may lock up the BIST state machine). This legal range is dependent on the number of rows of the SRAM the BIST is applied to (as specified by BIST_CTL.SRAMS_ENABLED). E.g. for a Flash with m columns, the legal range is [0, m-1]. Default Value: 0
Column start address. Useful to apply BIST to a part of an Flash. The value of this field should be in a legal range (a value outside of the legal range has an undefined result, and may lock up the BIST state machine). This legal range is dependent on the number of columns of the SRAM the BIST is applied to (as specified by BIST_CTL.SRAMS_ENABLED). E.g. for a Flash with n columns, the legal range is [0, n-1]. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
443
0x4025010C FLASHC_BIST_DATA0
8.1.7 FLASHC_BIST_DATA0
Address = 0x4025010C BIST data register(s) Address: 0x4025010C Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
DATA [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
DATA [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
DATA [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
DATA [31:24]
Bits 31 : 0
Name DATA
Description
BIST data register to store the expected value for data comparison. For a 128-bit Flash memory, there will be 4 BIST_DATA registers to store 128-bit value. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
444
FLASHC_BIST_DATA_ACT0
8.1.8 FLASHC_BIST_DATA_ACT0
Address = 0x4025012C BIST data actual register(s) Address: 0x4025012C Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
DATA [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
DATA [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
W
Name
DATA [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
W
Name
DATA [31:24]
Bits 31 : 0
Name DATA
Description
This field specified the actual Flash data output that caused the BIST failure. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
445
0x4025014C FLASHC_BIST_DATA_EXP0
8.1.9 FLASHC_BIST_DATA_EXP0
Address = 0x4025014C BIST data expected register(s) Address: 0x4025014C Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
DATA [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
DATA [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
W
Name
DATA [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
W
Name
DATA [31:24]
Bits 31 : 0
Name DATA
Description
This field specified the expected Flash data output. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
446
FLASHC_BIST_ADDR
8.1.10 FLASHC_BIST_ADDR
Address = 0x4025016C BIST address register Address: 0x4025016C Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
COL_ADDR [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
COL_ADDR [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
W
Name
ROW_ADDR [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
W
Name
ROW_ADDR [31:24]
Bits 31 : 16
15 : 0
Name ROW_ADDR
COL_ADDR
Description
Current row address. Default Value: Undefined
Current column address. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
447
0x40250170 FLASHC_BIST_STATUS
8.1.11 FLASHC_BIST_STATUS
Address = 0x40250170 BIST status register Address: 0x40250170 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
W1S
Name
None [7:1]
FAIL
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
FAIL
Description
0: BIST passed. 1: BIST failed. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
448
FLASHC_CM0_CA_CTL0
8.1.12 FLASHC_CM0_CA_CTL0
Address = 0x40250400 CM0+ cache control Address: 0x40250400 Retention: Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:18]
Bits SW Access HW Access
Name
31 RW R ENABLED
30 RW R PREF_EN
29
28
27
None
None
None [29:27]
2
1
0
10
9
8
18
17
16
RW
R
WAY [17:16]
26
25
24
RW
R
SET_ADDR [26:24]
Bits
Name
31
ENABLED
30
PREF_EN
26 : 24 17 : 16
SET_ADDR WAY
Description
Cache enable: 0: Disabled. The cache tag valid bits are reset to '0's and the cache LRU information is set to '1's (making way 0 the LRU way and way 3 the MRU way). 1: Enabled. Default Value: 1
Prefetch enable: 0: Disabled. 1: Enabled. Prefetching requires the cache to be enabled; i.e. ENABLED is '1'. Default Value: 1
Specifies the cache set for which cache information is provided in CM0_CA_STATUS0/1/2. Default Value: 0
Specifies the cache way for which cache information is provided in CM0_CA_STATUS0/1/2. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
449
0x40250404 FLASHC_CM0_CA_CTL1
8.1.13 FLASHC_CM0_CA_CTL1
Address = 0x40250404 CM0+ cache control Address: 0x40250404 Retention: Retained
Bits
7
6
5
4
3
2
SW Access
None
HW Access
None
Name
None [7:2]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
SW Access
R
HW Access
Name
VECTKEYSTAT [23:16]
Bits
31
30
29
28
27
26
SW Access
R
HW Access
Name
VECTKEYSTAT [31:24]
1
0
RW
R
PWR_MODE [1:0]
9
8
17
16
25
24
Bits 31 : 16
Name VECTKEYSTAT
1 : 0
PWR_MODE
Description Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Default Value: 64005 Set Power mode for CM0 cache Default Value: 3 0x0: OFF :
See CM4_PWR_CTL
0x1: RESERVED :
undefined
0x2: RETAINED :
See CM4_PWR_CTL
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
450
8.1.13
FLASHC_CM0_CA_CTL1 (continued)
0x3: ENABLED : See CM4_PWR_CTL
0x40250404 FLASHC_CM0_CA_CTL1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
451
0x40250408 FLASHC_CM0_CA_CTL2
8.1.14 FLASHC_CM0_CA_CTL2
Address = 0x40250408 CM0+ cache control Address: 0x40250408 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
PWRUP_DELAY [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
RW
HW Access
None
R
Name
None [15:10]
PWRUP_DELAY [9:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 9 : 0
Name PWRUP_DELAY
Description
Number clock cycles delay needed after power domain power up Default Value: 300
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
452
FLASHC_CM0_CA_CMD
8.1.15 FLASHC_CM0_CA_CMD
Address = 0x4025040C CM0+ cache command Address: 0x4025040C Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW1S
HW Access
None
RW1C
Name
None [7:1]
INV
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
INV
Description
FLASH cache invalidation. SW writes a "1" to clear the cache. W sets this field to "0" when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. The cache's LRU structure is also reset to its default state. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
453
0x40250440 FLASHC_CM0_CA_STATUS0
8.1.16 FLASHC_CM0_CA_STATUS0
Address = 0x40250440 CM0+ cache status 0 Address: 0x40250440 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
VALID16 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
VALID16 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 0
Name VALID16
Description
Sixteen valid bits of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
454
FLASHC_CM0_CA_STATUS1
8.1.17 FLASHC_CM0_CA_STATUS1
Address = 0x40250444 CM0+ cache status 1 Address: 0x40250444 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
TAG [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
TAG [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
W
Name
TAG [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
W
Name
TAG [31:24]
Bits 31 : 0
Name TAG
Description
Cache line address of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
455
0x40250448 FLASHC_CM0_CA_STATUS2
8.1.18 FLASHC_CM0_CA_STATUS2
Address = 0x40250448 CM0+ cache status 2 Address: 0x40250448 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
R
HW Access
None
W
Name
None [7:6]
LRU [5:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 5 : 0
Name LRU
Description
Six bit LRU representation of the cache set specified by CM0_CA_CTL.SET_ADDR. The encoding of the field is as follows ("X_LRU_Y" indicates that way X is Less Recently Used than way Y): Bit 5: 0_LRU_1: way 0 less recently used than way 1. Bit 4: 0_LRU_2. Bit 3: 0_LRU_3. Bit 2: 1_LRU_2. Bit 1: 1_LRU_3. Bit 0: 2_LRU_3. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
456
FLASHC_CM4_CA_CTL0
8.1.19 FLASHC_CM4_CA_CTL0
Address = 0x40250480 CM4 cache control Address: 0x40250480 Retention: Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:18]
Bits SW Access HW Access
Name
31 RW R ENABLED
30 RW R PREF_EN
29
28
27
None
None
None [29:27]
Bits 31 30 26 : 24 17 : 16
Name ENABLED PREF_EN SET_ADDR WAY
Description
See CM0_CA_CTL. Default Value: 1
See CM0_CA_CTL. Default Value: 1
See CM0_CA_CTL. Default Value: 0
See CM0_CA_CTL. Default Value: 0
2
1
0
10
9
8
18
17
16
RW
R
WAY [17:16]
26
25
24
RW
R
SET_ADDR [26:24]
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
457
0x40250484 FLASHC_CM4_CA_CTL1
8.1.20 FLASHC_CM4_CA_CTL1
Address = 0x40250484 CM4 cache control Address: 0x40250484 Retention: Retained
Bits
7
6
5
4
3
2
SW Access
None
HW Access
None
Name
None [7:2]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
SW Access
R
HW Access
Name
VECTKEYSTAT [23:16]
Bits
31
30
29
28
27
26
SW Access
R
HW Access
Name
VECTKEYSTAT [31:24]
1
0
RW
R
PWR_MODE [1:0]
9
8
17
16
25
24
Bits 31 : 16
Name VECTKEYSTAT
1 : 0
PWR_MODE
Description Register key (to prevent accidental writes). - Should be written with a 0x05fa key value for the write to take effect. - Always reads as 0xfa05. Default Value: 64005 Set Power mode for CM4 cache Default Value: 3 0x0: OFF :
See CM4_PWR_CTL
0x1: RESERVED :
undefined
0x2: RETAINED :
See CM4_PWR_CTL
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
458
8.1.20
FLASHC_CM4_CA_CTL1 (continued)
0x3: ENABLED : See CM4_PWR_CTL
0x40250484 FLASHC_CM4_CA_CTL1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
459
0x40250488 FLASHC_CM4_CA_CTL2
8.1.21 FLASHC_CM4_CA_CTL2
Address = 0x40250488 CM4 cache control Address: 0x40250488 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
PWRUP_DELAY [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
RW
HW Access
None
R
Name
None [15:10]
PWRUP_DELAY [9:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 9 : 0
Name PWRUP_DELAY
Description
Number clock cycles delay needed after power domain power up Default Value: 300
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
460
FLASHC_CM4_CA_CMD
8.1.22 FLASHC_CM4_CA_CMD
Address = 0x4025048C CM4 cache command Address: 0x4025048C Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW1S
HW Access
None
RW1C
Name
None [7:1]
INV
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
INV
Description
See CM0_CA_CMD. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
461
0x402504C0 FLASHC_CM4_CA_STATUS0
8.1.23 FLASHC_CM4_CA_STATUS0
Address = 0x402504C0 CM4 cache status 0 Address: 0x402504C0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
VALID16 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
VALID16 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 0
Name VALID16
Description
See CM0_CA_STATUS0. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
462
FLASHC_CM4_CA_STATUS1
8.1.24 FLASHC_CM4_CA_STATUS1
Address = 0x402504C4 CM4 cache status 1 Address: 0x402504C4 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
TAG [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
TAG [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
W
Name
TAG [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
W
Name
TAG [31:24]
Bits 31 : 0
Name TAG
Description
See CM0_CA_STATUS1. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
463
0x402504C8 FLASHC_CM4_CA_STATUS2
8.1.25 FLASHC_CM4_CA_STATUS2
Address = 0x402504C8 CM4 cache status 2 Address: 0x402504C8 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
R
HW Access
None
W
Name
None [7:6]
LRU [5:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 5 : 0
Name LRU
Description
See CM0_CA_STATUS2. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
464
FLASHC_CRYPTO_BUFF_CTL
8.1.26 FLASHC_CRYPTO_BUFF_CTL
Address = 0x40250500 Cryptography buffer control Address: 0x40250500 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
RW
None
HW Access
R
R
None
Name
ENABLED PREF_EN
None
Bits
Name
31
ENABLED
30
PREF_EN
Description
Cache enable: 0: Disabled. 1: Enabled. Default Value: 1
Prefetch enable: 0: Disabled. 1: Enabled. Prefetching requires the buffer to be enabled; i.e. ENABLED is '1'. Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
465
0x40250508 FLASHC_CRYPTO_BUFF_CMD
8.1.27 FLASHC_CRYPTO_BUFF_CMD
Address = 0x40250508 Cryptography buffer command Address: 0x40250508 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW1S
HW Access
None
RW1C
Name
None [7:1]
INV
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
INV
Description
FLASH buffer invalidation. SW writes a "1" to clear the buffer. HW sets this field to '0' when the operation is completed. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
466
FLASHC_DW0_BUFF_CTL
8.1.28 FLASHC_DW0_BUFF_CTL
Address = 0x40250580 Datawire 0 buffer control Address: 0x40250580 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
RW
None
HW Access
R
R
None
Name
ENABLED PREF_EN
None
Bits
Name
31
ENABLED
30
PREF_EN
Description
See CRYPTO_BUFF_CTL. Default Value: 1
See CRYPTO_BUFF_CTL. Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
467
0x40250588 FLASHC_DW0_BUFF_CMD
8.1.29 FLASHC_DW0_BUFF_CMD
Address = 0x40250588 Datawire 0 buffer command Address: 0x40250588 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW1S
HW Access
None
RW1C
Name
None [7:1]
INV
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
INV
Description
See CRYPTO_BUFF_CMD. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
468
FLASHC_DW1_BUFF_CTL
8.1.30 FLASHC_DW1_BUFF_CTL
Address = 0x40250600 Datawire 1 buffer control Address: 0x40250600 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
RW
None
HW Access
R
R
None
Name
ENABLED PREF_EN
None
Bits
Name
31
ENABLED
30
PREF_EN
Description
See CRYPTO_BUFF_CTL. Default Value: 1
See CRYPTO_BUFF_CTL. Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
469
0x40250608 FLASHC_DW1_BUFF_CMD
8.1.31 FLASHC_DW1_BUFF_CMD
Address = 0x40250608 Datawire 1 buffer command Address: 0x40250608 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW1S
HW Access
None
RW1C
Name
None [7:1]
INV
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
INV
Description
See CRYPTO_BUFF_CMD. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
470
FLASHC_DAP_BUFF_CTL
8.1.32 FLASHC_DAP_BUFF_CTL
Address = 0x40250680 Debug access port buffer control Address: 0x40250680 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
RW
None
HW Access
R
R
None
Name
ENABLED PREF_EN
None
Bits
Name
31
ENABLED
30
PREF_EN
Description
See CRYPTO_BUFF_CTL. Default Value: 1
See CRYPTO_BUFF_CTL. Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
471
0x40250688 FLASHC_DAP_BUFF_CMD
8.1.33 FLASHC_DAP_BUFF_CMD
Address = 0x40250688 Debug access port buffer command Address: 0x40250688 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW1S
HW Access
None
RW1C
Name
None [7:1]
INV
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
INV
Description
See CRYPTO_BUFF_CMD. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
472
FLASHC_EXT_MS0_BUFF_CTL
8.1.34 FLASHC_EXT_MS0_BUFF_CTL
Address = 0x40250700 External master 0 buffer control Address: 0x40250700 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
RW
None
HW Access
R
R
None
Name
ENABLED PREF_EN
None
Bits
Name
31
ENABLED
30
PREF_EN
Description
See CRYPTO_BUFF_CTL. Default Value: 1
See CRYPTO_BUFF_CTL. Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
473
0x40250708 FLASHC_EXT_MS0_BUFF_CMD
8.1.35 FLASHC_EXT_MS0_BUFF_CMD
Address = 0x40250708 External master 0 buffer command Address: 0x40250708 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW1S
HW Access
None
RW1C
Name
None [7:1]
INV
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
INV
Description
See CRYPTO_BUFF_CMD. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
474
FLASHC_EXT_MS1_BUFF_CTL
8.1.36 FLASHC_EXT_MS1_BUFF_CTL
Address = 0x40250780 External master 1 buffer control Address: 0x40250780 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
RW
None
HW Access
R
R
None
Name
ENABLED PREF_EN
None
Bits
Name
31
ENABLED
30
PREF_EN
Description
See CRYPTO_BUFF_CTL. Default Value: 1
See CRYPTO_BUFF_CTL. Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
475
0x40250788 FLASHC_EXT_MS1_BUFF_CMD
8.1.37 FLASHC_EXT_MS1_BUFF_CMD
Address = 0x40250788 External master 1 buffer command Address: 0x40250788 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW1S
HW Access
None
RW1C
Name
None [7:1]
INV
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
INV
Description
See CRYPTO_BUFF_CMD. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
476
FLASHC_FM_CTL
8.1.38 FLASHC_FM_CTL
Address = 0x4025F000 Flash macro control Address: 0x4025F000 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:4]
FM_MODE [3:0]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:10]
9
8
RW
R
FM_SEQ [9:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
HW Access
None
R
Name
None
DAA_MUX_SEL [22:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
RW
RW
HW Access
None
R
R
Name
None [31:26]
WR_EN
IF_SEL
Bits
Name
25
WR_EN
24
IF_SEL
22 : 16 9 : 8
DAA_MUX_SEL FM_SEQ
Description
"0": normal mode "1": Fm Write Enable Default Value: 0
Interface selection. Specifies the interface that is used for flash memory read operations: '0': R interface is used (default value). In this case, the flash memory address is provided as part of the R signal interface. '1': C interface is used. In this case, the flash memory address is provided by FM_MEM_ADDR (the page address) and by the C interface access offset in the FM_MEM_DATA structure. Default Value: 0
Direct memory cell access address. Default Value: 0
Flash macro sequence select: "0": TBD "1": TBD "2": TBD "3": TBD Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
477
0x4025F000 FLASHC_FM_CTL
8.1.38
3 : 0
FLASHC_FM_CTL (continued)
FM_MODE
Flash macro mode selection: "0": Normal functional mode. "1": Sets "pre-program control bit" for soft pre-program operation of all selected SONOS cells. the control bit is cleared by the HW after any program operation. "2": Sets ... "15": TBD Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
478
FLASHC_STATUS
8.1.39 FLASHC_STATUS
Address = 0x4025F004 Status Address: 0x4025F004 Retention: Not Retained
Bits SW Access HW Access
Name
7
6
None
None
None [7:6]
5
4
R
R
W
W
IF-
WR_EN_M
_SEL_MON
ON
3 R W
TURBO_N
2
1
R
R
W
W
ILLE-
HV_REGS_
GAL_HVOP ISOLATED
0
R
W
HV_TIMER_RUN-
NING
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
5
IF_SEL_MON
4
WR_EN_MON
3
TURBO_N
2
ILLEGAL_HVOP
Description
FM_CTL.IF_SEL bit after being synchronized in clk_r domain Default Value: 0
FM_CTL.WR_EN bit after being synchronized in clk_r domain Default Value: 0
After FM power up indicates the analog blocks currents are boosted to faster reach their functional state.. Used in the testchip boot only as an "FM READY" flag. '0' - turbo mode '1' - normal mode Default Value: 0
Indicates a bulk, sector erase, program has been requested when axa=1 '0' - no error '1' - illegal HV operation error Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
479
0x4025F004 FLASHC_STATUS
8.1.39
1
0
FLASHC_STATUS (continued)
HV_REGS_ISOLATED HV_TIMER_RUNNING
Indicates the isolation status at HV trim and redundancy registers inputs '0' - Not isolated, writing permitted '1' - isolated writing disabled Default Value: 0
Indicates if the high voltage timer is running: '0': not running '1': running Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
480
FLASHC_FM_ADDR
8.1.40 FLASHC_FM_ADDR
Address = 0x4025F008 Flash macro address Address: 0x4025F008 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
RA [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
RA [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
BA [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
RW
HW Access
None
R
Name
None [31:25]
AXA
Bits
Name
24
AXA
23 : 16
BA
15 : 0
RA
Description
Auxiliary address field: '0': regular flash memory. '1': supervisory flash memory. Default Value: 0
Bank address. Default Value: 0
Row address. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
481
0x4025F00C FLASHC_GEOMETRY
8.1.41 FLASHC_GEOMETRY
Address = 0x4025F00C Regular flash geometry Address: 0x4025F00C Retention: Retained
Bits SW Access HW Access
Name
7
6
5
4
R
W
PAGE_SIZE_LOG2 [7:4]
3
2
1
0
R
W
WORD_SIZE_LOG2 [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
ROW_COUNT [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
W
Name
ROW_COUNT [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
W
Name
BANK_COUNT [31:24]
Bits 31 : 24
Name BANK_COUNT
23 : 8
ROW_COUNT
Description
Number of banks (minus 1): "0": 1 bank "1": 2 banks ... "255": 256 banks Default Value: 0
Number of rows (minus 1): "0": 1 row "1": 2 rows "2": 3 rows ... "65535": 65536 rows Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
482
0x4025F00C FLASHC_GEOMETRY
8.1.41
7 : 4
3 : 0
FLASHC_GEOMETRY (continued)
PAGE_SIZE_LOG2 WORD_SIZE_LOG2
Number of Bytes per page (log 2): "0": 1 Byte "1": 2 Bytes "2": 4 Bytes ... "15": 32768 Bytes The currently planned flash macros have a page size of either 256 Byte or 512 Byte, resulting in PAGE_SIZE_LOG2 settings of 8 and 9 respectively. Default Value: 0
Number of Bytes per word (log 2). A word is defined as the data that is read from the flash macro over the R interface with a single read access: "0": 1 Byte "1": 2 Bytes "2": 4 Bytes ... "7": 128 Bytes The currently planned flash macros have a word size of either 32-bit, 64-bit or 128-bit, resulting in WORD_SIZE_LOG2 settings of 2, 3 and 4 respectively. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
483
0x4025F010 FLASHC_GEOMETRY_SUPERVISORY
8.1.42 FLASHC_GEOMETRY_SUPERVISORY
Address = 0x4025F010 Supervisory flash geometry Address: 0x4025F010 Retention: Retained
Bits SW Access HW Access
Name
7
6
5
4
R
W
PAGE_SIZE_LOG2 [7:4]
3
2
1
0
R
W
WORD_SIZE_LOG2 [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
ROW_COUNT [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
W
Name
ROW_COUNT [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
W
Name
BANK_COUNT [31:24]
Bits 31 : 24 23 : 8 7 : 4
Name BANK_COUNT ROW_COUNT PAGE_SIZE_LOG2
3 : 0
WORD_SIZE_LOG2
Description
Number of banks (minus 1). BANK_COUNT is less or equal to GEOMETRY.BANK_COUNT. Default Value: 0
Number of rows (minus 1). ROW_COUNT is typically less than GEOMETRY.ROW_COUNT Default Value: 0
Number of Bytes per page (log 2). See GEOMETRY.PAGE_SIZE_LOG2. Typically, PAGE_SIZE_LOG2 equals GEOMETRY.PAGE_SIZE_LOG2. Default Value: 0
Number of Bytes per word (log 2). See GEOMETRY.WORD_SIZE_LOG2. Typically, WORD_SIZE_LOG2 equals GEOMETRY.WORD_SIZE_LOG2. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
484
FLASHC_TIMER_CTL
8.1.43 FLASHC_TIMER_CTL
Address = 0x4025F014 Timer control Address: 0x4025F014 Retention: Not Retained
Bits
7
6
5
4
3
SW Access
RW
HW Access
R
Name
PERIOD [7:0]
Bits
15
14
13
12
11
SW Access
RW
HW Access
R
Name
PERIOD [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:17]
Bits SW Access HW Access
Name
31 RW RW0C
30 RW RW0C
29 RW RW0C
TIMER_EN ACLK_EN PUMP_EN
28
27
None
None
None [28:27]
2
1
0
10
9
8
18
17
16
RW
R
SCALE
26
25
RW
RW
R
R
PRE_PRO PRE_PRO
G_CSL
G
24
RW
R
PUMP_CLOCK_-
SEL
Bits
Name
31
TIMER_EN
30
ACLK_EN
29
PUMP_EN
Description
Timer enable: '0': disabled '1': enabled. SW sets this field to '1' to start the timer. HW sets this field to '0' when the timer is expired. Default Value: 0
ACLK enable (generates a single cycle pulse for the FM): '0': disabled '1': enabled. SW set this field to '1' to generate a single cycle pulse. HW sets this field to '0' when the pulse is generated. Default Value: 0
Pump enable: '0': disabled '1': enabled (also requires FM_CTL.IF_SEL to be '1', this additional restriction is required to prevent non intentional clearing of the FM). SW sets this field to '1' to generate a single PE pulse. HW clears this field when timer is expired. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
485
0x4025F014 FLASHC_TIMER_CTL
8.1.43
26 25 24
16
15 : 0
FLASHC_TIMER_CTL (continued)
PRE_PROG_CSL PRE_PROG PUMP_CLOCK_SEL
SCALE
PERIOD
'0' CSL lines driven by CSL_DAC '1' CSL lines driven by VNEG_G Default Value: 1
'1' during pre-program operation Default Value: 0
Pump clock select: '0': internal clock. '1': external clock. Default Value: 0
Timer tick scale: '0': 1 microsecond. '1': 100 microseconds. Default Value: 0
Timer period in either microseconds (SCALE is '0') or 100's of microseconds (SCALE is '1') multiples. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
486
FLASHC_ANA_CTL0
8.1.44 FLASHC_ANA_CTL0
Address = 0x4025F018 Analog control 0 Address: 0x4025F018 Retention: Not Retained
Bits
7
6
5
SW Access
HW Access
Name
Bits
15
SW Access
HW Access
Name
14
13
None
None
None [15:11]
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
SW Access
HW Access
Name
30
29
None
None
None [31:28]
4
3
None
None
None [7:0]
12
11
20
19
None
None
None [23:16]
28
27
RW
R
FLIP_AMU XBUS_AB
2
1
0
10
9
8
RW
R
CSLDAC [10:8]
18
17
16
26
25
None
None
None [26:25]
24 RW R
VCC_SEL
Bits 27 24
10 : 8
Name FLIP_AMUXBUS_AB VCC_SEL
CSLDAC
Description
Flips amuxbusa and amuxbusb '0': amuxbusa, amuxbusb '1': amuxbusb, amuxbusb Default Value: 0
Vcc select: '0': 1.2 V : LP reset value '1': 0.95 V: ULP reset value Note: the flash macro compiler has a configuration option that specifies the default/reset value of this field. Default Value: 0
Trimming of common source line DAC. Default Value: 4
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
487
0x4025F01C FLASHC_ANA_CTL1
8.1.45 FLASHC_ANA_CTL1
Address = 0x4025F01C Analog control 1 Address: 0x4025F01C Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
MDAC [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
HW Access
None
R
Name
None [23:20]
PDAC [19:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
RW
RW
RW
RW
HW Access
None
R
R
R
R
Name
None
RST_S- R_GRANT_ VPROT_OV
FT_HVPL
CTL
ERRIDE
NDAC [27:24]
Bits
Name
30
RST_SFT_HVPL
29
R_GRANT_CTL
28
VPROT_OVERRIDE
27 : 24 19 : 16 7 : 0
NDAC PDAC MDAC
Description
'1': Page Latches Soft Reset Default Value: 0
r_grant control: "0": r_grant normal functionality "1": forces r_grant LO synchronized on clk_r Default Value: 0
'0': vprot = BG.vprot. '1': vprot = vcc Default Value: 0
Trimming of negative pump output Voltage: Default Value: 6
Trimming of positive pump output Voltage: Default Value: 6
Trimming of the output margin Voltage as a function of Vpos and Vneg. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
488
FLASHC_GEOMETRY_GEN
8.1.46 FLASHC_GEOMETRY_GEN
Address = 0x4025F020 N/A, DNU Address: 0x4025F020 Retention: Not Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:4]
4
3
2
1
R
R
R
W
W
W
DNU_0x20_ DNU_0x20_ DNU_0x20_
3
2
1
Bits
15
14
13
12
11
10
9
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
SW Access
None
HW Access
None
Name
None [31:24]
0 None None None
8
16
24
Bits
Name
3
DNU_0x20_3
2
DNU_0x20_2
1
DNU_0x20_1
Description
N/A Default Value: 0
N/A Default Value: 0
N/A Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
489
0x4025F024 FLASHC_TEST_CTL
8.1.47 FLASHC_TEST_CTL
Address = 0x4025F024 Test mode control Address: 0x4025F024 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:5]
TEST_MODE [4:0]
Bits
15
SW Access
HW Access
Name
14
13
None
None
None [15:12]
12
11
10
9
8
RW
RW
RW
RW
R
R
R
R
TM_DISNEG
TM_DISPOS
TM_PE
PN_CTL
Bits
23
SW Access
HW Access
Name
22
21
20
None
None
None [23:19]
19
18
17
16
RW
RW
RW
R
R
R
EN-
CSL_DE-
ABLE_OSC
BUG
EN_CLK_MON
Bits
31
30
29
28
27
26
25
24
SW Access
RW
None
HW Access
R
None
Name
UNSCRAMBLE_WA
None [30:24]
Bits
Name
Description
31
UNSCRAMBLE_WA
See BSN-242 memo
'0': normal
'1': disables the Word Address scrambling
Default Value: 0
18
ENABLE_OSC
0': the oscillator enable logic has control over the internal oscillator '1': forces oscillator enable HI Default Value: 0
17
CSL_DEBUG
Engineering Debug Register Default Value: 0
16
EN_CLK_MON
1: enables the oscillator output monitor Default Value: 0
11
TM_DISNEG
Test mode negative pump disable Default Value: 0
10
TM_DISPOS
Test mode positive pump disable Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
490
0x4025F024 FLASHC_TEST_CTL
8.1.47
9 8
4 : 0
FLASHC_TEST_CTL (continued)
TM_PE PN_CTL
TEST_MODE
PUMP_EN override: Pump Enable =PUMP_EN | PE_TM Default Value: 0
Positive/negative margin mode control: '0': negative margin control '1': positive margin control Default Value: 0
Test mode control: "0"-"31": TBD Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
491
FLASHC_WAIT_CTL
8.1.48 FLASHC_WAIT_CTL
Address = 0x4025F028 Wiat State control Address: 0x4025F028 Retention: Not Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:4]
Bits
15
SW Access
HW Access
Name
14
13
None
None
None [15:12]
Bits
23
SW Access
HW Access
Name
22
21
None
None
None [23:19]
Bits
31
30
29
SW Access
HW Access
Name
4
3
12
11
20
19
28
27
None
None
None [31:24]
2
1
0
RW
R
WAIT_FM_MEM_RD [3:0]
10
9
8
RW
R
WAIT_FM_HV_RD [11:8]
18
17
16
RW
R
WAIT_FM_HV_WR [18:16]
26
25
24
Bits 18 : 16
11 : 8
Name WAIT_FM_HV_WR
WAIT_FM_HV_RD
3 : 0
WAIT_FM_MEM_RD
Description
Number of C interface wait cycles (on "clk_c") for a write to the high Voltage page latches. Default Value: 3
Number of C interface wait cycles (on "clk_c") for a read from the high Voltage page latches. Common for reading HV Page Latches and the DATA_COMP_RESULT bit Default Value: 11
Number of C interface wait cycles (on "clk_c") for a read from the memory Default Value: 9
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
492
FLASHC_MONITOR_STATUS
8.1.49 FLASHC_MONITOR_STATUS
Address = 0x4025F02C Monitor Status Address: 0x4025F02C Retention: Not Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:3]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
R
W
NEG_PUM P_VHI
1
R
W
POS_PUM P_VLO
10
9
0 None None None
8
18
17
16
26
25
24
Bits
Name
2
NEG_PUMP_VHI
1
POS_PUMP_VLO
Description
NEG pump VHI Default Value: 1
POS pump VLO Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
493
0x4025F030 FLASHC_SCRATCH_CTL
8.1.50 FLASHC_SCRATCH_CTL
Address = 0x4025F030 Scratch Control Address: 0x4025F030 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
DUMMY32 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
DUMMY32 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
DUMMY32 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
DUMMY32 [31:24]
Bits 31 : 0
Name DUMMY32
Description
Scratchpad register fields. Provided for test purposes. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
494
FLASHC_HV_CTL
8.1.51 FLASHC_HV_CTL
Address = 0x4025F034 High voltage control Address: 0x4025F034 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
TIMER_CLOCK_FREQ [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 0
Name TIMER_CLOCK_FREQ
Description
Specifies the frequency in MHz of the timer clock "clk_t" as provide to the flash macro. E.g., if "4", the timer clock "clk_t" has a frequency of 4 MHz. Default Value: 50
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
495
0x4025F038 FLASHC_ACLK_CTL
8.1.52 FLASHC_ACLK_CTL
Address = 0x4025F038 Aclk control Address: 0x4025F038 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
W
HW Access
None
R
Name
None [7:1]
ACLK_GEN
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
ACLK_GEN
Description
A write to this register generates a ACLK pulse for the flash macro (also requires FM_CTL.IF_SEL to be '1'). Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
496
FLASHC_INTR
8.1.53 FLASHC_INTR
Address = 0x4025F03C Interrupt Address: 0x4025F03C Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW1C
HW Access
None
RW1S
Name
None [7:1]
TIMER_EXPIRED
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
TIMER_EXPIRED
Description
Set to '1', when event is detected. Write INTR field with '1', to clear bit. Write INTR_SET field with '1', to set bit. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
497
0x4025F040 FLASHC_INTR_SET
8.1.54 FLASHC_INTR_SET
Address = 0x4025F040 Interrupt set Address: 0x4025F040 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW1S
HW Access
None
A
Name
None [7:1]
TIMER_EXPIRED
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
TIMER_EXPIRED
Description
Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect). Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
498
FLASHC_INTR_MASK
8.1.55 FLASHC_INTR_MASK
Address = 0x4025F044 Interrupt mask Address: 0x4025F044 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:1]
TIMER_EXPIRED
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
TIMER_EXPIRED
Description
Mask for corresponding field in INTR register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
499
0x4025F048 FLASHC_INTR_MASKED
8.1.56 FLASHC_INTR_MASKED
Address = 0x4025F048 Interrupt masked Address: 0x4025F048 Retention: Not Retained
Bits
7
6
5
4
3
2
SW Access
None
HW Access
None
Name
None [7:1]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
TIMER_EXPIRED
Description
Logical and of corresponding request and mask fields. Default Value: 0
1
0
R
W
TIMER_EXPIRED
9
8
17
16
25
24
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
500
FLASHC_FM_HV_DATA_ALL
8.1.57 FLASHC_FM_HV_DATA_ALL
Address = 0x4025F04C Flash macro high Voltage page latches data (for all page latches) Address: 0x4025F04C Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
W
HW Access
R
Name
DATA32 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
W
HW Access
R
Name
DATA32 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
W
HW Access
R
Name
DATA32 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
W
HW Access
R
Name
DATA32 [31:24]
Bits 31 : 0
Name DATA32
Description
Write all high Voltage page latches with the same 32-bit data in a single write cycle Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
501
0x4025F050 FLASHC_CAL_CTL0
8.1.58 FLASHC_CAL_CTL0
Address = 0x4025F050 Cal control BG LO trim bits Address: 0x4025F050 Retention: Retained
Bits SW Access HW Access
Name
7
6
5
RW
R
CDAC_LO_HV [7:5]
Bits SW Access HW Access
Name
15
14
13
RW
R
VBG_TC_TRIM_LO_HV [15:13]
Bits
23
SW Access
HW Access
Name
22
21
None
None
None [23:20]
Bits
31
30
29
SW Access
HW Access
Name
4
3
2
1
0
RW
R
VCT_TRIM_LO_HV [4:0]
12
11
10
9
8
RW
R
VBG_TRIM_LO_HV [12:8]
20
19
18
17
16
RW
R
IPREF_TRIM_LO_HV [19:16]
28
27
26
25
24
None
None
None [31:24]
Bits 19 : 16 15 : 13 12 : 8 7 : 5 4 : 0
Name IPREF_TRIM_LO_HV VBG_TC_TRIM_LO_HV VBG_TRIM_LO_HV CDAC_LO_HV VCT_TRIM_LO_HV
Description
LO Bandgap IPTAT trim control. Default Value: 8
LO Bandgap Voltage Temperature Compensation trim control Default Value: 4
LO Bandgap Voltage trim control. Default Value: 15
LO Temperature compensated trim DAC. To control Vcstat slope for Vpos. Default Value: 4
LO Bandgap Voltage Temperature Compensation trim control. Default Value: 15
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
502
FLASHC_CAL_CTL1
8.1.59 FLASHC_CAL_CTL1
Address = 0x4025F054 Cal control BG HI trim bits Address: 0x4025F054 Retention: Retained
Bits SW Access HW Access
Name
7
6
5
RW
R
CDAC_HI_HV [7:5]
Bits SW Access HW Access
Name
15
14
13
RW
R
VBG_TC_TRIM_HI_HV [15:13]
Bits
23
SW Access
HW Access
Name
22
21
None
None
None [23:20]
Bits
31
30
29
SW Access
HW Access
Name
4
3
2
1
0
RW
R
VCT_TRIM_HI_HV [4:0]
12
11
10
9
8
RW
R
VBG_TRIM_HI_HV [12:8]
20
19
18
17
16
RW
R
IPREF_TRIM_HI_HV [19:16]
28
27
26
25
24
None
None
None [31:24]
Bits 19 : 16 15 : 13 12 : 8 7 : 5 4 : 0
Name IPREF_TRIM_HI_HV VBG_TC_TRIM_HI_HV VBG_TRIM_HI_HV CDAC_HI_HV VCT_TRIM_HI_HV
Description
HI Bandgap IPTAT trim control. Default Value: 8
HI Bandgap Voltage Temperature Compensation trim control. Default Value: 4
HI Bandgap Voltage trim control. Default Value: 15
HI Temperature compensated trim DAC. To control Vcstat slope for Vpos. Default Value: 4
HI Bandgap Voltage Temperature Compensation trim control. Default Value: 15
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
503
0x4025F058 FLASHC_CAL_CTL2
8.1.60 FLASHC_CAL_CTL2
Address = 0x4025F058 Cal control BG LO ipref trim, ref sel, fm_active, turbo_ext Address: 0x4025F058 Retention: Retained
Bits SW Access HW Access
Name
7
6
5
RW
R
ICREF_TC_TRIM_LO_HV [7:5]
Bits SW Access HW Access
Name
15
14
13
RW
R
ICREF_TC_TRIM_HI_HV [15:13]
Bits
23
SW Access
HW Access
Name
22
21
None
None
None [23:20]
Bits
31
30
29
SW Access
HW Access
Name
4
3
2
1
0
RW
R
ICREF_TRIM_LO_HV [4:0]
12
11
10
9
8
RW
R
ICREF_TRIM_HI_HV [12:8]
20
19
18
17
16
RW
RW
RW
RW
R
R
R
R
TURBO_EX-
T_HV
FM_AC- IREF_SEL_ VREF_SEL
TIVE_HV
HV
_HV
28
27
26
25
24
None
None
None [31:24]
Bits 19 18 17
16
15 : 13
Name TURBO_EXT_HV FM_ACTIVE_HV IREF_SEL_HV
VREF_SEL_HV
ICREF_TC_TRIM_HI_HV
Description
0: turbo signal generated internally 1: turbo cleared by clk_pump_ext HI Default Value: 0
0: No Action 1: Forces FM SYS in active mode Default Value: 0
Current reference: '0': internal current reference '1': external current reference Default Value: 0
Voltage reference: '0': internal bandgap reference '1': external voltage reference Default Value: 0
HI Bandgap Current Temperature Compensation trim control. Default Value: 3
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
504
0x4025F058 FLASHC_CAL_CTL2
8.1.60
12 : 8 7 : 5 4 : 0
FLASHC_CAL_CTL2 (continued)
ICREF_TRIM_HI_HV
HI Bandgap Current trim control. Default Value: 16
ICREF_TC_TRIM_LO_HV LO Bandgap Current Temperature Compensation trim control Default Value: 3
ICREF_TRIM_LO_HV
LO Bandgap Current trim control. Default Value: 16
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
505
FLASHC_CAL_CTL3
8.1.61 FLASHC_CAL_CTL3
Address = 0x4025F05C Cal control osc trim bits, idac, sdac, itim, bdac. Address: 0x4025F05C Retention: Retained
Bits SW Access HW Access
Name
7
6
5
4
3
RW
RW
R
R
IDAC_HV [7:5]
OSC_RANGE_
TRIM_HV
2
1
0
RW
R
OSC_TRIM_HV [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
RW
RW
RW
HW Access
R
R
R
R
Name
VDDHI_HV
ITIM_HV [14:11]
SDAC_HV [10:9]
IDAC_HV
Bits
23
SW Access
HW Access
Name
22
21
None
None
None [23:20]
20
19
18
17
16
RW
RW
RW
R
R
R
BGHI_EN_ BGLO_EN_
HV
HV
TURBO_PULSEW_HV [17:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 19 18 17 : 16 15
14 : 11 10 : 9 8 : 5
Name BGHI_EN_HV BGLO_EN_HV TURBO_PULSEW_HV VDDHI_HV
ITIM_HV SDAC_HV IDAC_HV
Description
HI Bandgap Enable Default Value: 0
LO Bandgap Enable Default Value: 0
Turbo pulse width trim Default Value: 0
0': vdd<2.3V '1': vdd>=2.3V Default Value: 1
Trimming of timing current Default Value: 4
Default Value: 2
Default Value: 8
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
506
8.1.61
4
3 : 0
FLASHC_CAL_CTL3 (continued)
OSC_RANGE_TRIM_HV OSC_TRIM_HV
0: Oscillator High Frequency Range 1: Oscillator Low Frequency range Default Value: 0
Flash macro pump clock trim control. Default Value: 4
0x4025F05C FLASHC_CAL_CTL3
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
507
FLASHC_BOOKMARK
8.1.62 FLASHC_BOOKMARK
Address = 0x4025F060 Bookmark register - keeps the current FW HV seq Address: 0x4025F060 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
W
HW Access
R
Name
BOOKMARK [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
W
HW Access
R
Name
BOOKMARK [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
W
HW Access
R
Name
BOOKMARK [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
W
HW Access
R
Name
BOOKMARK [31:24]
Bits 31 : 0
Name BOOKMARK
Description
Used by FW. Keeps the Current HV cycle sequence Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
508
FLASHC_RED_CTL01
8.1.63 FLASHC_RED_CTL01
Address = 0x4025F080 Redundancy Control normal sectors 0,1 Address: 0x4025F080 Retention: Retained
Bits
7
6
5
4
3
2
SW Access
RW
HW Access
R
Name
RED_ADDR_0 [7:0]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:9]
Bits
23
22
21
20
19
18
SW Access
RW
HW Access
R
Name
RED_ADDR_1 [23:16]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:25]
Bits 24 23 : 16 8 7 : 0
Name RED_EN_1 RED_ADDR_1 RED_EN_0 RED_ADDR_0
Description
'1': Redundancy Enable for Sector 1 Default Value: 0
Bad Row Pair Address for Sector 1 Default Value: 0
'1': Redundancy Enable for Sector 0 Default Value: 0
Bad Row Pair Address for Sector 0 Default Value: 0
1
0
9
8
RW
R
RED_EN_0
17
16
25
24
RW
R
RED_EN_1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
509
0x4025F084 FLASHC_RED_CTL23
8.1.64 FLASHC_RED_CTL23
Address = 0x4025F084 Redundancy Controll normal sectors 2,3 Address: 0x4025F084 Retention: Retained
Bits
7
6
5
4
3
2
SW Access
RW
HW Access
R
Name
RED_ADDR_2 [7:0]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:9]
Bits
23
22
21
20
19
18
SW Access
RW
HW Access
R
Name
RED_ADDR_3 [23:16]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:25]
Bits 24 23 : 16 8 7 : 0
Name RED_EN_3 RED_ADDR_3 RED_EN_2 RED_ADDR_2
Description
1': Redundancy Enable for Sector 3 Default Value: 0
Bad Row Pair Address for Sector 3 Default Value: 0
1': Redundancy Enable for Sector 2 Default Value: 0
Bad Row Pair Address for Sector 2 Default Value: 0
1
0
9
8
RW
R
RED_EN_2
17
16
25
24
RW
R
RED_EN_3
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
510
FLASHC_RED_CTL45
8.1.65 FLASHC_RED_CTL45
Address = 0x4025F088 Redundancy Controll normal sectors 4,5 Address: 0x4025F088 Retention: Retained
Bits SW Access HW Access
Name
7
RW
R
VLIM_TRIM _HV_0
6 RW R
DNU_45_6
5
RW
R
FDIV_TRIM _HV_1
4 RW R
DNU_45_5
3
RW
R
FDIV_TRIM _HV_0
2 RW R
DNU_45_3
1
RW
R
REG_ACT_ HV
0 RW R
DNU_45_1
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:9]
9
8
RW
R
DNU_45_8
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
DNU_45_23_16 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 23 : 16 8 7
Name DNU_45_23_16 DNU_45_8 VLIM_TRIM_HV_0
6
DNU_45_6
5
FDIV_TRIM_HV_1
Description
Not Used Default Value: 0
Not Used Default Value: 0
'2b00' V2 = 650mV see vlim_trim_hv<1> value as well '2b01' V2 = 600mV '2b10' V2 = 750mV '2b11' V2 = 700mV Default Value: 0
Not Used Default Value: 0
'2b00' F = 1MHz see fdiv_trim_hv<0> value as well '2b01' F = 0.5MHz '2b10' F = 2MHz '2b11' F = 4Mhz Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
511
0x4025F088 FLASHC_RED_CTL45
8.1.65
4 3
2 1 0
FLASHC_RED_CTL45 (continued)
DNU_45_5 FDIV_TRIM_HV_0
DNU_45_3 REG_ACT_HV DNU_45_1
Not Used Default Value: 0
'2b00' F = 1MHz see fdiv_trim_hv<1> value as well '2b01' F = 0.5MHz '2b10' F = 2MHz '2b11' F = 4Mhz Default Value: 0
Not Used Default Value: 0
Forces the VBST regulator in active mode all the time Default Value: 0
Not Used Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
512
FLASHC_RED_CTL67
8.1.66 FLASHC_RED_CTL67
Address = 0x4025F08C Redundancy Controll normal sectors 6,7 Address: 0x4025F08C Retention: Retained
Bits SW Access HW Access
Name
7 RW R
DNU_67_7
6 RW R
IPREF_TRIMA_HI_HV
5 RW R
DNU_67_5
4
RW
R
IPREF_TC_H
V
3 RW R
DNU_67_3
2 RW R
VPROT_AC T_HV
1 RW R
DNU_67_1
0 RW R
VLIM_TRIM _HV_1
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:9]
9
8
RW
R
IPREF_TRIMA_LO_HV
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
DNU_67_23_16 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 23 : 16 8 7 6 5 4 3
Name DNU_67_23_16 IPREF_TRIMA_LO_HV DNU_67_7 IPREF_TRIMA_HI_HV DNU_67_5 IPREF_TC_HV DNU_67_3
Description
Not Used Default Value: 0
Adds 200-300nA boost on IPREF_LO Default Value: 0
Not Used Default Value: 0
Adds 200-300nA boost on IPREF_HI Default Value: 0
Not Used Default Value: 0
Reduces the IPREF Tempco by not subtracting ICREF form IPREF - IPREF will be 1uA Default Value: 0
Not Used Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
513
0x4025F08C FLASHC_RED_CTL67
8.1.66
2 1 0
FLASHC_RED_CTL67 (continued)
VPROT_ACT_HV DNU_67_1 VLIM_TRIM_HV_1
Forces VPROT in active mode all the time Default Value: 0
Not Used Default Value: 0
'2b00' V2 = 650mV see vlim_trim_hv<0> value as well '2b01' V2 = 600mV '2b10' V2 = 750mV '2b11' V2 = 700mV Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
514
FLASHC_RED_CTL_SM01
8.1.67 FLASHC_RED_CTL_SM01
Address = 0x4025F090 Redundancy Controll special sectors 0,1 Address: 0x4025F090 Retention: Retained
Bits
7
6
5
4
3
2
SW Access
RW
HW Access
R
Name
RED_ADDR_SM0 [7:0]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:9]
Bits SW Access HW Access
Name
Bits SW Access HW Access
Name
23
31 RW R R_GRANT_ EN
22
30 RW R TRKD
21
20
19
18
RW
R
RED_ADDR_SM1 [23:16]
29
28
27
26
None
None
None [29:25]
Bits
Name
31
R_GRANT_EN
30 24 23 : 16 8 7 : 0
TRKD RED_EN_SM1 RED_ADDR_SM1 RED_EN_SM0 RED_ADDR_SM0
Description
'0': r_grant handshake disabled, r_grant always 1. '1': r_grand handshake enabled Default Value: 0
Sense Amp Control tracking delay Default Value: 0
Redundancy Enable for Special Sector 1 Default Value: 0
Bad Row Pair Address for Special Sector 1 Default Value: 0
Redundancy Enable for Special Sector 0 Default Value: 0
Bad Row Pair Address for Special Sector 0 Default Value: 0
1
0
9
8
RW
R
RED_EN_S M0
17
16
25
24
RW
R
RED_EN_S M1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
515
0x4025F100 FLASHC_TM_CMPR0
8.1.68 FLASHC_TM_CMPR0
Address = 0x4025F100 Do Not Use Address: 0x4025F100 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
R
HW Access
None
W
Name
None [7:1]
DATA_COMP_RE-
SULT
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
Description
0
DATA_COMP_RESULT The result of a comparison between the flash macro data output and the content of the high volt-
age page latches.
The comparison result for a given column "Column_Number" is updated in this register field on
a read to address: 0x100+4*Column_Number.
The number of wait states is given by WAIT_CTL.WAIT_FM_HV_RD.
'0': FALSE (not equal)
'1': TRUE (equal)
Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
516
FLASHC_FM_HV_DATA0
8.1.69 FLASHC_FM_HV_DATA0
Address = 0x4025F800 Flash macro high Voltage page latches data Address: 0x4025F800 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
DATA32 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
DATA32 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
DATA32 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
DATA32 [31:24]
Bits 31 : 0
Name DATA32
Description
Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_SEL to be '1'). Note: the high Voltage page latches are readable for test mode functionality. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
517
0x4025FC00 FLASHC_FM_MEM_DATA0
8.1.70 FLASHC_FM_MEM_DATA0
Address = 0x4025FC00 Flash macro memory sense amplifier and column decoder data Address: 0x4025FC00 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
DATA32 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
DATA32 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
W
Name
DATA32 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
W
Name
DATA32 [31:24]
Bits 31 : 0
Name DATA32
Description
Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL: - IF_SEL is "0": data as specified by the R interface address - IF_SEL is "1": data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
518
9 System Resources Subsystem Registers
This section discusses the System Resources Subsystem (SRSS) registers. It lists all the registers in mapping tables, in address order.
9.1 Register Details
Register PWR_CTL PWR_HIBERNATE PWR_LVD_CTL PWR_BUCK_CTL PWR_BUCK_CTL2 PWR_LVD_STATUS PWR_HIB_DATA0 WDT_CTL WDT_CNT WDT_MATCH CLK_DSI_SELECT0 CLK_DSI_SELECT1 CLK_DSI_SELECT2 CLK_DSI_SELECT3 CLK_DSI_SELECT4 CLK_PATH_SELECT0 CLK_PATH_SELECT1 CLK_PATH_SELECT2 CLK_PATH_SELECT3 CLK_PATH_SELECT4 CLK_ROOT_SELECT0 CLK_ROOT_SELECT1 CLK_ROOT_SELECT2 CLK_ROOT_SELECT3 CLK_ROOT_SELECT4 CLK_SELECT
Address 0x40260000 0x40260004 0x40260008 0x40260014 0x40260018 0x4026001C 0x40260080 0x40260180 0x40260184 0x40260188 0x40260300 0x40260304 0x40260308 0x4026030C 0x40260310 0x40260340 0x40260344 0x40260348 0x4026034C 0x40260350 0x40260380 0x40260384 0x40260388 0x4026038C 0x40260390 0x40260500
Description Power Mode Control HIBERNATE Mode Register Low Voltage Detector (LVD) Configuration Register Buck Control Register Buck Control Register 2 Low Voltage Detector (LVD) Status Register HIBERNATE Data Register Watchdog Counter Control Register Watchdog Counter Count Register Watchdog Counter Match Register Clock DSI Select Register Clock DSI Select Register. See CLK_DSI_SELECT0 for the details of bit fields. Clock DSI Select Register. See CLK_DSI_SELECT0 for the details of bit fields. Clock DSI Select Register. See CLK_DSI_SELECT0 for the details of bit fields. Clock DSI Select Register. See CLK_DSI_SELECT0 for the details of bit fields. Clock Path Select Register Clock Path Select Register. See CLK_PATH_SELECT0 for the details of bit fields. Clock Path Select Register. See CLK_PATH_SELECT0 for the details of bit fields. Clock Path Select Register. See CLK_PATH_SELECT0 for the details of bit fields. Clock Path Select Register. See CLK_PATH_SELECT0 for the details of bit fields. Clock Root Select Register Clock Root Select Register. See CLK_ROOT_SELECT0 for the details of bit fields. Clock Root Select Register. See CLK_ROOT_SELECT0 for the details of bit fields. Clock Root Select Register. See CLK_ROOT_SELECT0 for the details of bit fields. Clock Root Select Register. See CLK_ROOT_SELECT0 for the details of bit fields. Clock selection register
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
519
System Resources Subsystem Registers
Register CLK_TIMER_CTL CLK_ILO_CONFIG CLK_IMO_CONFIG CLK_OUTPUT_FAST CLK_OUTPUT_SLOW CLK_CAL_CNT1 CLK_CAL_CNT2 CLK_ECO_CONFIG CLK_ECO_STATUS CLK_PILO_CONFIG CLK_FLL_CONFIG CLK_FLL_CONFIG2 CLK_FLL_CONFIG3 CLK_FLL_CONFIG4 CLK_FLL_STATUS CLK_PLL_CONFIG0 CLK_PLL_STATUS0 SRSS_INTR SRSS_INTR_SET SRSS_INTR_MASK SRSS_INTR_MASKED SRSS_INTR_CFG RES_CAUSE RES_CAUSE2 PWR_TRIM_REF_CTL PWR_TRIM_BODOVP_CTL CLK_TRIM_CCO_CTL CLK_TRIM_CCO_CTL2 PWR_TRIM_WAKE_CTL PWR_TRIM_LVD_CTL CLK_TRIM_ILO_CTL PWR_TRIM_PWRSYS_CTL CLK_TRIM_ECO_CTL CLK_TRIM_PILO_CTL CLK_TRIM_PILO_CTL2 CLK_TRIM_PILO_CTL3
Address 0x40260504 0x4026050C 0x40260510 0x40260514 0x40260518 0x4026051C 0x40260520 0x4026052C 0x40260530 0x4026053C 0x40260580 0x40260584 0x40260588 0x4026058C 0x40260590 0x40260600 0x40260640 0x40260700 0x40260704 0x40260708 0x4026070C 0x40260710 0x40260800 0x40260804 0x40267F00 0x40267F04 0x40267F08 0x40267F0C 0x40267F30 0x4026FF10 0x4026FF18 0x4026FF1C 0x4026FF20 0x4026FF24 0x4026FF28 0x4026FF2C
Timer Clock Control Register ILO Configuration IMO Configuration Fast Clock Output Select Register Slow Clock Output Select Register Clock Calibration Counter 1 Clock Calibration Counter 2 ECO Configuration Register ECO Status Register Precision ILO Configuration Register FLL Configuration Register FLL Configuration Register 2 FLL Configuration Register 3 FLL Configuration Register 4 FLL Status Register PLL Configuration Register PLL Status Register SRSS Interrupt Register SRSS Interrupt Set Register SRSS Interrupt Mask Register SRSS Interrupt Masked Register SRSS Interrupt Configuration Register Reset Cause Observation Register Reset Cause Observation Register 2 Reference Trim Register BOD/OVP Trim Register CCO Trim Register CCO Trim Register 2 Wakeup Trim Register LVD Trim Register ILO Trim Register Power System Trim Register ECO Trim Register PILO Trim Register PILO Trim Register 2 PILO Trim Register 3
Description
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
520
PWR_CTL
9.1.1 PWR_CTL
Address = 0x40260000 Power Mode Control Address: 0x40260000 Retention: Retained
Bits SW Access HW Access
Name
7
6
None
None
None [7:6]
5
R
RW
LPM_READY
4
R
RW
DEBUG_SESSION
3
2
None
None
None [3:2]
1
0
R
RW
POWER_MODE [1:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits SW Access HW Access
Name
23 RW A
LINREG_DIS
22
21
20
RW
RW
RW
A
A
A
NWELL_RE G_DIS
RET_REG_ DIS
DPSLP_REG_DI
S
19 R RW
VREFBUF_OK
18 RW A
IREF_LPMODE
17
16
None
None
None [17:16]
Bits SW Access HW Access
Name
31
30
29
R
RW
RW
RW
A
A
ACT_REF_ ACT_REF_
OK
DIS
VREFBUF_DIS
28
RW
A
VREFBUF_LP-
MODE
27
26
RW
RW
R
A
PLL_LS_BY BGREF_LP
PASS
MODE
25
RW
A
PORBOD_LP-
MODE
24
RW
A
LINREG_LP-
MODE
Bits
Name
31
ACT_REF_OK
30
ACT_REF_DIS
29
VREFBUF_DIS
Description
Indicates that the normal mode of the Active Reference is ready. Default Value: 0
Disables the Active Reference. Firmware must ensure that LPM_READY==1 and BGREF_LPMODE==1 for at least 1us before disabling the Active Reference. When enabling the Active Reference, use ACT_REF_OK indicator to know when it is ready. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: Active Reference is enabled 1: Active Reference is disabled Default Value: 0
Disable the 800mV voltage reference buffer. Firmware should only disable the buffer when there is no connected circuit that is using it. SRSS circuits that require it are the PLL and ECO. A particular product may have circuits outside the SRSS that use the buffer. This register is only reset by XRES/POR/BOD/HIBERNATE. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
521
PWR_CTL
9.1.1
28 27 26
25 24 23
PWR_CTL (continued)
VREFBUF_LPMODE PLL_LS_BYPASS BGREF_LPMODE
PORBOD_LPMODE LINREG_LPMODE LINREG_DIS
Control the power mode of the 800mV voltage reference buffer. The value in this register is ignored and normal mode is used until LPM_READY==1. 0: Voltage Reference Buffer operates in normal mode. They work for vddd ramp rates of 100mV/ us or less. This register is only reset by XRES/POR/BOD/HIBERNATE. 1: Voltage Reference Buffer operates in low power mode. Power supply rejection is reduced to save current, and they work for vddd ramp rates of 10mV/us or less. Default Value: 0
Bypass level shifter inside the PLL. 0: Do not bypass the level shifter. This setting is ok for all operational modes and vccd target voltage. 1: Bypass the level shifter. This may reduce jitter on the PLL output clock, but can only be used when vccd is targeted to 1.1V nominal. Otherwise, it can result in clock degradation and static current. Default Value: 0
Control the power mode of the Bandgap Voltage and Current References. This applies to voltage and current generation and is different than the reference voltage buffer. The value in this register is ignored and normal mode is used until LPM_READY==1. When lower power mode is used, the Active Reference circuit can be disabled to reduce current. Firmware is responsible to ensure ACT_REF_OK==1 before changing back to normal mode. This register is only reset by XRES/ POR/BOD/HIBERNATE. 0: Active Bandgap Voltage and Current Reference operates in normal mode. They work for vddd ramp rates of 100mV/us or less. 1: Active Bandgap Voltage and Current Reference operates in low power mode. Power supply rejection is reduced to save current, and they work for vddd ramp rates of 10mV/us or less. The Active Reference may be disabled using ACT_REF_DIS=0. Default Value: 0
Control the power mode of the POR/BOD circuits. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: POR/BOD circuits operate in normal mode. They work for vddd ramp rates of 100mV/us or less. 1: POR/BOD circuits operate in low power mode. Response time is reduced to save current, and they work for vddd ramp rates of 10mV/us or less. Default Value: 0
Control the power mode of the Linear Regulator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: Linear Regulator operates in normal mode. Internal current consumption is 50uA and load current capability is 50mA to 300mA, depending on the number of regulator modules present in the product. 1: Linear Regulator operates in low power mode. Internal current consumption is 5uA and load current capability is 25mA. Firmware must ensure the current is kept within the limit. Default Value: 0
Disable the linear Core Regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/ BOD/HIBERNATE. 0: Linear regulator is on. 1: Linear regulator is off. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
522
PWR_CTL
9.1.1
22 21 20 19 18 5
4
1 : 0
PWR_CTL (continued)
NWELL_REG_DIS RET_REG_DIS DPSLP_REG_DIS VREFBUF_OK IREF_LPMODE LPM_READY
DEBUG_SESSION
Disable the Nwell regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: Nwell Regulator is on. 1: Nwell Regulator is off. Default Value: 0
Disable the Retention regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/ HIBERNATE. 0: Retention Regulator is on. 1: Retention Regulator is off. Default Value: 0
Disable the DeepSleep regulator. This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/ BOD/HIBERNATE. 0: DeepSleep Regulator is on. 1: DeepSleep Regulator is off. Default Value: 0
Indicates that the voltage reference buffer is ready. Due to synchronization delays, it may take two IMO clock cycles for hardware to clear this bit after asserting VREFBUF_DIS=1. Default Value: 0
Control the power mode of the reference current generator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/ HIBERNATE. 0: Current reference generator operates in normal mode. It works for vddd ramp rates of 100mV/ us or less. 1: Current reference generator operates in low power mode. Response time is reduced to save current, and it works for vddd ramp rates of 10mV/us or less. Default Value: 0
Indicates whether certain low power functions are ready. The low current circuits take longer to startup after XRES/POR/BOD/HIBERNATE wakeup than the normal mode circuits. HIBERNATE mode may be entered regardless of this bit. This register is only reset by XRES/POR/ BOD/HIBERNATE. 0: If a low power circuit operation is requested, it will stay in its normal operating mode until it is ready. If DEEPSLEEP is requested by all processors WFI/WFE, the device will instead enter SLEEP. When low power circuits are ready, device will automatically enter the originally requested mode. 1: Normal operation. DEEPSLEEP and low power circuits operate as requested in other registers. Default Value: 0
Indicates whether a debug session is active (CDBGPWRUPREQ signal is 1) Default Value: 0
0x0: NO_SESSION :
No debug session active
0x1: SESSION_ACTIVE : Debug session is active. Power modes behave differently to keep the debug session active.
POWER_MODE
Current power mode of the device. Note that this field cannot be read in all power modes on actual silicon. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
523
PWR_CTL
9.1.1
PWR_CTL (continued)
0x0: RESET : System is resetting.
0x1: ACTIVE : At least one CPU is running.
0x2: SLEEP : No CPUs are running. Peripherals may be running.
0x3: DEEPSLEEP : Main high-frequency clock is off; low speed clocks are available. Communication interface clocks may be present.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
524
PWR_HIBERNATE
9.1.2 PWR_HIBERNATE
Address = 0x40260004 HIBERNATE Mode Register Address: 0x40260004 Retention: Retained
Bits
7
6
5
4
3
2
1
SW Access
RW
HW Access
A
Name
TOKEN [7:0]
Bits
15
14
13
12
11
10
9
SW Access
RW
HW Access
A
Name
UNLOCK [15:8]
Bits SW Access HW Access
Name
23
22
21
20
19
18
17
RW
RW
RW
RW
A
A
A
A
POLARITY_HIBPIN [23:20]
MASK_HIB- MASK_HI-
WDT
BALARM
FREEZE
Bits SW Access HW Access
Name
31 RW A
HIBERNATE
30
RW1S
R
HIBERNATE_DIS-
ABLE
29
28
None
None
None [29:28]
27
26
25
RW
A
MASK_HIBPIN [27:24]
0
8
16 None None None
24
Bits 31
30
27 : 24
Name HIBERNATE
HIBERNATE_DISABLE
MASK_HIBPIN
Description
Firmware sets this bit to enter HIBERNATE mode. The system will enter HIBERNATE mode immediately after writing to this bit and will wakeup only in response to XRES or WAKEUP event. Both UNLOCK and FREEZE must have been set correctly in a previous write operations. Otherwise, it will not enter HIBERNATE. External supplies must have been stable for 250us before entering HIBERNATE mode. Default Value: 0
Hibernate disable bit. 0: Normal operation, HIBERNATE works as described 1: Further writes to this register are ignored Note: This bit is a write-once bit until the next reset. Avoid changing any other bits in this register while disabling HIBERNATE mode. Also, it is recommended to clear the UNLOCK code, if it was previously written.. Default Value: 0
When set, HIBERNATE will wakeup if the corresponding pin input matches the POLARITY_HIBPIN setting. Each bit corresponds to one of the wakeup pins. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
525
PWR_HIBERNATE
9.1.2
23 : 20 19 18 17
15 : 8 7 : 0
PWR_HIBERNATE (continued)
POLARITY_HIBPIN MASK_HIBWDT MASK_HIBALARM FREEZE
UNLOCK TOKEN
Each bit sets the active polarity of the corresponding wakeup pin. 0: Pin input of 0 will wakeup the part from HIBERNATE 1: Pin input of 1 will wakeup the part from HIBERNATE Default Value: 0
When set, HIBERNATE will wakeup if WDT matches Default Value: 0
When set, HIBERNATE will wakeup for a RTC interrupt Default Value: 0
Firmware sets this bit to freeze the configuration, mode and state of all GPIOs and SIOs in the system. When entering HIBERNATE mode, the first write instructs DEEPSLEEP peripherals that they cannot ignore the upcoming freeze command. This occurs even in the illegal condition where UNLOCK is not set. If UNLOCK and HIBERNATE are properly set, the IOs actually freeze on the second write. Default Value: 0
This byte must be set to 0x3A for FREEZE or HIBERNATE fields to operate. Any other value in this register will cause FREEZE/HIBERNATE to have no effect, except as noted in the FREEZE description. Default Value: 0
Contains a 8-bit token that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware to differentiate WAKEUP from a general RESET event. Note that waking up from HIBERNATE using XRES will reset this register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
526
PWR_LVD_CTL
9.1.3 PWR_LVD_CTL
Address = 0x40260008 Low Voltage Detector (LVD) Configuration Register Address: 0x40260008 Retention: Retained
Bits SW Access HW Access
Name
7
RW
A
HVLVD1_EN
6
5
4
RW
R
HVLVD1_SRCSEL [6:4]
3
2
1
0
RW
R
HVLVD1_TRIPSEL [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
7
HVLVD1_EN
6 : 4
HVLVD1_SRCSEL
Description
Enable HVLVD1 voltage monitor. When the LVD is enabled, it takes 20us for it to settle. There is no hardware stabilization counter, and it may falsely trigger during settling. It is recommended that firmware keep the interrupt masked for at least 8us, write a 1'b1 to the corresponding SRSS_INTR field to any falsely pended interrupt, and then optionally unmask the interrupt. After enabling, it is further recommended to read the related PWR_LVD_STATUS field, since the interrupt only triggers on edges. This bit is cleared (LVD is disabled) when entering DEEPSLEEP to prevent false interrupts during wakeup. Default Value: 0
Source selection for HVLVD1 Default Value: 0
0x0: VDDD :
Select VDDD
0x1: AMUXBUSA :
Select AMUXBUSA (VDDD branch)
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
527
PWR_LVD_CTL
9.1.3
3 : 0
PWR_LVD_CTL (continued)
0x2: RESERVED : Reserved. Connected AMUXBUSA (VDDD branch)
0x3: VDDIO : Reserved. Selects VDDD.
0x4: AMUXBUSB : Select AMUXBUSB (VDDD branch)
HVLVD1_TRIPSEL
Threshold selection for HVLVD1. Disable the LVD (HVLVD1_EN=0) before changing the threshold. 0: rise=1.225V (nom), fall=1.2V (nom) 1: rise=1.425V (nom), fall=1.4V (nom) 2: rise=1.625V (nom), fall=1.6V (nom) 3: rise=1.825V (nom), fall=1.8V (nom) 4: rise=2.025V (nom), fall=2V (nom) 5: rise=2.125V (nom), fall=2.1V (nom) 6: rise=2.225V (nom), fall=2.2V (nom) 7: rise=2.325V (nom), fall=2.3V (nom) 8: rise=2.425V (nom), fall=2.4V (nom) 9: rise=2.525V (nom), fall=2.5V (nom) 10: rise=2.625V (nom), fall=2.6V (nom) 11: rise=2.725V (nom), fall=2.7V (nom) 12: rise=2.825V (nom), fall=2.8V (nom) 13: rise=2.925V (nom), fall=2.9V (nom) 14: rise=3.025V (nom), fall=3.0V (nom) 15: rise=3.125V (nom), fall=3.1V (nom) Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
528
PWR_BUCK_CTL
9.1.4 PWR_BUCK_CTL
Address = 0x40260014 Buck Control Register Address: 0x40260014 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:3]
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
RW
RW
HW Access
A
A
Name
BUCK_OUT 1_EN
BUCK_EN
4
3
2
1
0
RW
A
BUCK_OUT1_SEL [2:0]
12
11
10
9
8
None
None
None [15:8]
20
19
18
17
16
None
None
None [23:16]
28
27
26
25
24
None
None
None [29:24]
Bits
Name
31
BUCK_OUT1_EN
30
BUCK_EN
Description
Enable for vccbuck1 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. This register is only reset by XRES/POR/BOD/HIBERNATE. The regulator takes up to 600us to charge the external capacitor. If there is additional load current while charging, this will increase the startup time. The TRM specifies the required sequence when transitioning vccd from the LDO to SIMO Buck output #1. Default Value: 0
Master enable for buck converter. This register is only reset by XRES/POR/BOD/HIBERNATE. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
529
PWR_BUCK_CTL
9.1.4
2 : 0
PWR_BUCK_CTL (continued)
BUCK_OUT1_SEL
Voltage output selection for vccbuck1 output. This register is only reset by XRES/POR/BOD/HIBERNATE. When increasing the voltage, it can take up to 200us for the output voltage to settle. When decreasing the voltage, the settling time depends on the load current. 0: 0.85V 1: 0.875V 2: 0.90V 3: 0.95V 4: 1.05V 5: 1.10V 6: 1.15V 7: 1.20V Default Value: 5
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
530
PWR_BUCK_CTL2
9.1.5 PWR_BUCK_CTL2
Address = 0x40260018 Buck Control Register 2 Address: 0x40260018 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:3]
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
RW
RW
HW Access
R
R
Name
BUCK_OUT BUCK_OUT
2_EN
2_HW_SEL
4
3
2
1
0
RW
R
BUCK_OUT2_SEL [2:0]
12
11
10
9
8
None
None
None [15:8]
20
19
18
17
16
None
None
None [23:16]
28
27
26
25
24
None
None
None [29:24]
Bits
Name
Description
31
BUCK_OUT2_EN
Enable for vccbuck2 output. The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1. The regulator takes up to 600us to charge the external capacitor. If there is additional load current while charging, this will increase the startup time. Default Value: 0
30
BUCK_OUT2_HW_SEL Hardware control for vccbuck2 output. When this bit is set, the value in BUCK_OUT2_EN is ig-
nored and a hardware signal is used instead. If the product has supporting hardware, it can di-
rectly control the enable signal for vccbuck2. The same charging time in BUCK_OUT2_EN
applies.
Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
531
PWR_BUCK_CTL2
9.1.5
2 : 0
PWR_BUCK_CTL2 (continued)
BUCK_OUT2_SEL
Voltage output selection for vccbuck2 output. When increasing the voltage, it can take up to 200us for the output voltage to settle. When decreasing the voltage, the settling time depends on the load current. 0: 1.15V 1: 1.20V 2: 1.25V 3: 1.30V 4: 1.35V 5: 1.40V 6: 1.45V 7: 1.50V Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
532
PWR_LVD_STATUS
9.1.6 PWR_LVD_STATUS
Address = 0x4026001C Low Voltage Detector (LVD) Status Register Address: 0x4026001C Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
R
HW Access
None
RW
Name
None [7:1]
HVLVD1_OK
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
HVLVD1_OK
Description
HVLVD1 output. 0: below voltage threshold 1: above voltage threshold Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
533
PWR_HIB_DATA0
9.1.7 PWR_HIB_DATA0
Address = 0x40260080 HIBERNATE Data Register Address: 0x40260080 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
A
Name
HIB_DATA [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
A
Name
HIB_DATA [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
A
Name
HIB_DATA [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
A
Name
HIB_DATA [31:24]
Bits 31 : 0
Name HIB_DATA
Description
Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose. Note that waking up from HIBERNATE using XRES will reset this register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
534
WDT_CTL
9.1.8 WDT_CTL
Address = 0x40260180 Watchdog Counter Control Register Address: 0x40260180 Retention: Retained
Bits
7
6
SW Access
HW Access
Name
Bits
15
14
SW Access
HW Access
Name
Bits
23
22
SW Access
HW Access
Name
Bits SW Access HW Access
Name
31
30
RW
A
WDT_LOCK [31:30]
5
4
3
2
None
None
None [7:1]
13
12
11
10
None
None
None [15:8]
21
20
19
18
None
None
None [23:16]
29
28
27
26
None
None
None [29:24]
1
0
RW
A
WDT_EN
9
8
17
16
25
24
Bits 31 : 30
Name WDT_LOCK
Description
Prohibits writing to WDT_*, CLK_ILO_CONFIG, CLK_SELECT.LFCLK_SEL, and CLK_TRIM_ILO_CTL registers when not equal 0. Requires at least two different writes to unlock. A change in WDT_LOCK takes effect beginning with the next write cycle. Note that this field is 2 bits to force multiple writes only. It represents only a single write protect signal protecting all those registers at the same time. WDT will lock on any reset. This field is not retained during Deep Sleep or Hibernate mode, so the WDT will be locked after wakeup from these modes. Default Value: 3
0x0: NO_CHG :
No effect
0x1: CLR0 :
Clears bit 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
535
WDT_CTL
9.1.8
0
WDT_CTL (continued)
0x2: CLR1 : Clears bit 1
0x3: SET01 : Sets both bits 0 and 1
WDT_EN
Enable this watchdog timer. This field is retained during Deep Sleep and Hibernate modes. Even though the default value is 1, in most cases the Cortex-M0+ executing the SROM code will change the value of this bit to 0. So effectively the user code starts with the WDT disabled. Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
536
WDT_CNT
9.1.9 WDT_CNT
Address = 0x40260184 Watchdog Counter Count Register Address: 0x40260184 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
A
Name
COUNTER [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
A
Name
COUNTER [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 0
Name COUNTER
Description
Current value of WDT Counter. The write feature of this register is for verification purposes, has no synchronization, and can only be applied when the WDT is off. When writing, the value is updated immediately in the WDT counter, but it will read back as the old value until this register resynchronizes just after the negative edge of ILO. Writes will be ignored if they occur when the WDT is enabled. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
537
WDT_MATCH
9.1.10 WDT_MATCH
Address = 0x40260188 Watchdog Counter Match Register Address: 0x40260188 Retention: Retained
Bits
7
6
5
SW Access
HW Access
Name
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
SW Access
HW Access
Name
22
21
None
None
None [23:20]
Bits
31
30
29
SW Access
HW Access
Name
4
3
2
1
0
RW
A
MATCH [7:0]
12
11
10
9
8
RW
A
MATCH [15:8]
20
19
18
17
16
RW
A
IGNORE_BITS [19:16]
28
27
26
25
24
None
None
None [31:24]
Bits 19 : 16
Name IGNORE_BITS
15 : 0
MATCH
Description
The number of MSB bits of the watchdog timer that are NOT checked against MATCH. This value provides control over the time-to-reset of the watchdog (which happens after 3 successive matches). Up to 12 MSB can be ignored. Settings >12 behave like a setting of 12. Default Value: 0
Match value for Watchdog counter. Every time WDT_COUNTER reaches MATCH an interrupt is generated. Two unserviced interrupts will lead to a system reset (i.e. at the third match). Default Value: 4096
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
538
CLK_DSI_SELECT0
9.1.11 CLK_DSI_SELECT0
Address = 0x40260300 Clock DSI Select Register Address: 0x40260300 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:5]
DSI_MUX [4:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 4 : 0
Name DSI_MUX
Description Selects a DSI source or low frequency clock for use in a clock path. The output of this mux can be selected for clock PATH using CLK_SELECT_PATH register. Using the output of this mux as HFCLK source will result in undefined behavior. It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits. This mux is not glitch free, so do not change the selection while it is an actively selected clock. Default Value: 0 0x0: DSI_OUT0 :
DSI0 - dsi_out[0]
0x1: DSI_OUT1 :
DSI1 - dsi_out[1]
0x2: DSI_OUT2 :
DSI2 - dsi_out[2]
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
539
9.1.11
CLK_DSI_SELECT0 (continued)
0x3: DSI_OUT3 : DSI3 - dsi_out[3] 0x4: DSI_OUT4 : DSI4 - dsi_out[4] 0x5: DSI_OUT5 : DSI5 - dsi_out[5] 0x6: DSI_OUT6 : DSI6 - dsi_out[6] 0x7: DSI_OUT7 : DSI7 - dsi_out[7] 0x8: DSI_OUT8 : DSI8 - dsi_out[8] 0x9: DSI_OUT9 : DSI9 - dsi_out[9] 0xa: DSI_OUT10 : DSI10 - dsi_out[10] 0xb: DSI_OUT11 : DSI11 - dsi_out[11] 0xc: DSI_OUT12 : DSI12 - dsi_out[12] 0xd: DSI_OUT13 : DSI13 - dsi_out[13] 0xe: DSI_OUT14 : DSI14 - dsi_out[14]
CLK_DSI_SELECT0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
540
9.1.11
CLK_DSI_SELECT0 (continued)
0xf: DSI_OUT15 : DSI15 - dsi_out[15] 0x10: ILO : ILO - Internal Low-speed Oscillator 0x11: WCO : WCO - Watch-Crystal Oscillator
0x12: ALTLF : ALTLF - Alternate Low-Frequency Clock 0x13: PILO : PILO - Precision Internal Low-speed Oscillator
CLK_DSI_SELECT0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
541
CLK_PATH_SELECT0
9.1.12 CLK_PATH_SELECT0
Address = 0x40260340 Clock Path Select Register Address: 0x40260340 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:3]
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4
3
12
11
None
None
None [15:8]
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
2
1
0
RW
R
PATH_MUX [2:0]
10
9
8
18
17
16
26
25
24
Bits 2 : 0
Name PATH_MUX
Description Selects a source for clock PATH. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. Default Value: 0 0x0: IMO : IMO - Internal R/C Oscillator
0x1: EXTCLK : EXTCLK - External Clock Pin
0x2: ECO : ECO - External-Crystal Oscillator
0x3: ALTHF : ALTHF - Alternate High-Frequency clock input (product-specific clock)
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
542
CLK_PATH_SELECT0
9.1.12
CLK_PATH_SELECT0 (continued)
0x4: DSI_MUX :
DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HFCLK will result in undefined behavior.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
543
CLK_ROOT_SELECT0
9.1.13 CLK_ROOT_SELECT0
Address = 0x40260380 Clock Root Select Register Address: 0x40260380 Retention: Retained
Bits SW Access HW Access
Name
7
6
None
None
None [7:6]
5
4
RW
R
ROOT_DIV [5:4]
3
2
1
0
RW
R
ROOT_MUX [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
None
HW Access
A
None
Name
ENABLE
None [30:24]
Bits 31
5 : 4
Name ENABLE
ROOT_DIV
Description Enable for this clock root. All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled. Default Value: 0 Selects predivider value for this clock root and DSI input. Default Value: 0 0x0: NO_DIV :
Transparent mode, feed through selected clock source w/o dividing.
0x1: DIV_BY_2 :
Divide selected clock source by 2
0x2: DIV_BY_4 :
Divide selected clock source by 4
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
544
CLK_ROOT_SELECT0
9.1.13
CLK_ROOT_SELECT0 (continued)
0x3: DIV_BY_8 : Divide selected clock source by 8
3 : 0
ROOT_MUX
Selects a clock path as the root of HFCLK and for SRSS DSI input . Use CLK_SELECT_PATH[i] to configure the desired path. Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers. Configure the FLL using CLK_FLL_CONFIG register. Configure a PLL using the related CLK_PLL_CONFIG[k] register. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. Default Value: 0
0x0: PATH0 :
Select PATH0 (can be configured for FLL)
0x1: PATH1 : Select PATH1 (can be configured for PLL0, if available in the product)
0x2: PATH2 : Select PATH2 (can be configured for PLL1, if available in the product)
0x3: PATH3 : Select PATH3 (can be configured for PLL2, if available in the product)
0x4: PATH4 : Select PATH4 (can be configured for PLL3, if available in the product)
0x5: PATH5 : Select PATH5 (can be configured for PLL4, if available in the product)
0x6: PATH6 : Select PATH6 (can be configured for PLL5, if available in the product)
0x7: PATH7 : Select PATH7 (can be configured for PLL6, if available in the product)
0x8: PATH8 : Select PATH8 (can be configured for PLL7, if available in the product)
0x9: PATH9 : Select PATH9 (can be configured for PLL8, if available in the product)
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
545
CLK_ROOT_SELECT0
9.1.13
CLK_ROOT_SELECT0 (continued)
0xa: PATH10 : Select PATH10 (can be configured for PLL9, if available in the product) 0xb: PATH11 : Select PATH11 (can be configured for PLL10, if available in the product) 0xc: PATH12 : Select PATH12 (can be configured for PLL11, if available in the product) 0xd: PATH13 : Select PATH13 (can be configured for PLL12, if available in the product) 0xe: PATH14 : Select PATH14 (can be configured for PLL13, if available in the product) 0xf: PATH15 : Select PATH15 (can be configured for PLL14, if available in the product)
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
546
CLK_SELECT
9.1.14 CLK_SELECT
Address = 0x40260500 Clock selection register Address: 0x40260500 Retention: Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:2]
Bits
15
14
13
12
11
SW Access
RW
RW
HW Access
R
R
Name
PUMP_ENABLE
PUMP_DIV [14:12]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
0
RW
A
LFCLK_SEL [1:0]
10
9
8
RW
R
PUMP_SEL [11:8]
18
17
16
26
25
24
Bits
Name
15
PUMP_ENABLE
14 : 12
PUMP_DIV
Description
Enable the pump clock. PUMP_ENABLE and the PUMP_SEL mux are not glitch-free to minimize side-effects, avoid changing the PUMP_SEL and PUMP_DIV while changing PUMP_ENABLE. To change the settings, do the following: 1) If the pump clock is enabled, write PUMP_ENABLE=0 without changing PUMP_SEL and PUMP_DIV. 2) Change PUMP_SEL and PUMP_DIV to desired settings with PUMP_ENABLE=0. 3) Write PUMP_ENABLE=1 without changing PUMP_SEL and PUMP_DIV. Default Value: 0
Division ratio for PUMPCLK. Uses selected PUMP_SEL clock as the source. Default Value: 0
0x0: NO_DIV :
Transparent mode, feed through selected clock source w/o dividing.
0x1: DIV_BY_2 :
Divide selected clock source by 2
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
547
CLK_SELECT
9.1.14
CLK_SELECT (continued)
0x2: DIV_BY_4 : Divide selected clock source by 4
0x3: DIV_BY_8 : Divide selected clock source by 8
0x4: DIV_BY_16 : Divide selected clock source by 16
11 : 8
PUMP_SEL
1 : 0
LFCLK_SEL
Selects clock PATH, where k=PUMP_SEL. The output of this mux goes to the PUMP_DIV to make PUMPCLK Each product has a specific number of available clock paths. Selecting a path that is not implemented on a product will result in undefined behavior. Note that this is not a glitch free mux. Default Value: 0
Select source for LFCLK. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. Default Value: 0
0x0: ILO :
ILO - Internal Low-speed Oscillator
0x1: WCO :
WCO - Watch-Crystal Oscillator. Requires Backup domain to be present and properly configured (including external watch crystal, if used).
0x2: ALTLF : ALTLF - Alternate Low-Frequency Clock. Capability is product-specific
0x3: PILO :
PILO - Precision ILO. If present, it works in DEEPSLEEP and higher modes. Does not work in HIBERNATE mode.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
548
CLK_TIMER_CTL
9.1.15 CLK_TIMER_CTL
Address = 0x40260504 Timer Clock Control Register Address: 0x40260504 Retention: Retained
Bits
7
6
5
4
3
2
SW Access
None
HW Access
None
Name
None [7:1]
Bits
15
14
SW Access
HW Access
Name
Bits
23
22
SW Access
HW Access
Name
Bits
31
30
SW Access
RW
HW Access
R
Name
ENABLE
13
12
11
10
None
None
None [15:10]
21
20
19
18
RW
R
TIMER_DIV [23:16]
29
28
27
26
None
None
None [30:24]
1
0
RW
R
TIMER_SEL
9
8
RW
R
TIMER_HF0_DIV [9:8]
17
16
25
24
Bits
Name
31
ENABLE
23 : 16
TIMER_DIV
9 : 8
TIMER_HF0_DIV
Description
Enable for TIMERCLK. 0: TIMERCLK is off 1: TIMERCLK is enabled Default Value: 0
Divide selected timer clock source by (1+TIMER_DIV). The output of this divider is TIMERCLK Allows for integer divisions in the range [1, 256]. Do not change this setting while the timer is enabled. Default Value: 7
Predivider used when HF0_DIV is selected in TIMER_SEL. If HFCLK0 frequency is less than 100MHz and has approximately 50% duty cycle, then no division is required (NO_DIV). Otherwise, select a divide ratio of 2, 4, or 8 before selected HF0_DIV as the timer clock. Default Value: 0
0x0: NO_DIV :
Transparent mode, feed through selected clock source w/o dividing or correcting duty cycle.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
549
CLK_TIMER_CTL
9.1.15
CLK_TIMER_CTL (continued)
0x1: DIV_BY_2 : Divide HFCLK0 by 2.
0x2: DIV_BY_4 : Divide HFCLK0 by 4.
0x3: DIV_BY_8 : Divide HFCLK0 by 8.
0
TIMER_SEL
Select source for TIMERCLK. The output of this mux can be further divided using TIMER_DIV. Default Value: 0 0x0: IMO :
IMO - Internal Main Oscillator
0x1: HF0_DIV : Select the output of the predivider configured by TIMER_HF0_DIV.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
550
CLK_ILO_CONFIG
9.1.16 CLK_ILO_CONFIG
Address = 0x4026050C ILO Configuration Address: 0x4026050C Retention: Retained
Bits
7
6
5
SW Access
HW Access
Name
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
RW
HW Access
A
Name
ENABLE
4
3
2
None
None
None [7:1]
12
11
10
None
None
None [15:8]
20
19
18
None
None
None [23:16]
28
27
26
None
None
None [30:24]
1
0
RW
A
ILO_BACKUP
9
8
17
16
25
24
Bits
Name
31
ENABLE
0
ILO_BACKUP
Description
Master enable for ILO. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. After enabling, it takes at most two cycles to reach the accuracy spec. Default Value: 1
If backup domain is present on this product, this register indicates that ILO should stay enabled for use by backup domain during XRES, HIBERNATE mode, and through power-related resets like BOD on VDDD/VCCD. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. 0: ILO turns off at XRES/BOD event or HIBERNATE entry. 1: ILO remains on if backup domain is present and powered even for XRES/BOD or HIBERNATE entry. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
551
CLK_IMO_CONFIG
9.1.17 CLK_IMO_CONFIG
Address = 0x40260510 IMO Configuration Address: 0x40260510 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
None
HW Access
R
None
Name
ENABLE
None
Bits
Name
31
ENABLE
Description
Master enable for IMO oscillator. This bit must be high at all times for all functions to work properly. Hardware will automatically disable the IMO during HIBERNATE and XRES. It will automatically disable during DEEPSLEEP if DPSLP_ENABLE==0. Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
552
CLK_OUTPUT_FAST
9.1.18 CLK_OUTPUT_FAST
Address = 0x40260514 Fast Clock Output Select Register Address: 0x40260514 Retention: Retained
Bits
7
6
5
4
SW Access
RW
HW Access
R
Name
PATH_SEL0 [7:4]
Bits
15
14
13
12
SW Access
None
HW Access
None
Name
None [15:12]
Bits
23
22
21
20
SW Access
RW
HW Access
R
Name
PATH_SEL1 [23:20]
Bits
31
30
29
28
SW Access
None
HW Access
None
Name
None [31:28]
3
2
1
0
RW
R
FAST_SEL0 [3:0]
11
10
9
8
RW
R
HFCLK_SEL0 [11:8]
19
18
17
16
RW
R
FAST_SEL1 [19:16]
27
26
25
24
RW
R
HFCLK_SEL1 [27:24]
Bits 27 : 24
23 : 20
Name HFCLK_SEL1
PATH_SEL1
19 : 16
FAST_SEL1
Description Selects a HFCLK tree for use in fast clock output #1 logic Default Value: 0 Selects a clock path to use in fast clock output #1 logic. 0: FLL output 1-15: PLL output on path1-path15 (if available) Default Value: 0 Select signal for fast clock output #1 Default Value: 0 0x0: NC :
Disabled - output is 0. For power savings, clocks are blocked before entering any muxes, including PATH_SEL1 and HFCLK_SEL1.
0x1: ECO :
External Crystal Oscillator (ECO)
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
553
CLK_OUTPUT_FAST
9.1.18
CLK_OUTPUT_FAST (continued)
0x2: EXTCLK : External clock input (EXTCLK)
0x3: ALTHF : Alternate High-Frequency (ALTHF) clock input to SRSS
0x4: TIMERCLK :
Timer clock. It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse.
0x5: PATH_SEL1 : Selects the clock path chosen by PATH_SEL1 field
0x6: HFCLK_SEL1 : Selects the output of the HFCLK_SEL1 mux
0x7: SLOW_SEL1 : Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL1
11 : 8 7 : 4
HFCLK_SEL0 PATH_SEL0
3 : 0
FAST_SEL0
Selects a HFCLK tree for use in fast clock output #0 Default Value: 0
Selects a clock path to use in fast clock output #0 logic. 0: FLL output 1-15: PLL output on path1-path15 (if available) Default Value: 0
Select signal for fast clock output #0 Default Value: 0
0x0: NC :
Disabled - output is 0. For power savings, clocks are blocked before entering any muxes, including PATH_SEL0 and HFCLK_SEL0.
0x1: ECO : External Crystal Oscillator (ECO)
0x2: EXTCLK : External clock input (EXTCLK)
0x3: ALTHF : Alternate High-Frequency (ALTHF) clock input to SRSS
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
554
CLK_OUTPUT_FAST
9.1.18
CLK_OUTPUT_FAST (continued)
0x4: TIMERCLK : Timer clock. It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse.
0x5: PATH_SEL0 : Selects the clock path chosen by PATH_SEL0 field
0x6: HFCLK_SEL0 : Selects the output of the HFCLK_SEL0 mux
0x7: SLOW_SEL0 : Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
555
CLK_OUTPUT_SLOW
9.1.19 CLK_OUTPUT_SLOW
Address = 0x40260518 Slow Clock Output Select Register Address: 0x40260518 Retention: Retained
Bits
7
6
5
4
SW Access
RW
HW Access
R
Name
SLOW_SEL1 [7:4]
3
2
1
0
RW
R
SLOW_SEL0 [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 4
Name SLOW_SEL1
Description Select signal for slow clock output #1 Default Value: 0 0x0: NC : Disabled - output is 0. For power savings, clocks are blocked before entering any muxes.
0x1: ILO : Internal Low Speed Oscillator (ILO)
0x2: WCO : Watch-Crystal Oscillator (WCO)
0x3: BAK : Root of the Backup domain clock tree (BAK)
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
556
CLK_OUTPUT_SLOW
9.1.19
CLK_OUTPUT_SLOW (continued)
0x4: ALTLF : Alternate low-frequency clock input to SRSS (ALTLF)
0x5: LFCLK : Root of the low-speed clock tree (LFCLK)
0x6: IMO :
Internal Main Oscillator (IMO). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit.
0x7: SLPCTRL :
Sleep Controller clock (SLPCTRL). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit.
0x8: PILO : Precision Internal Low Speed Oscillator (PILO)
3 : 0
SLOW_SEL0
Select signal for slow clock output #0 Default Value: 0 0x0: NC :
Disabled - output is 0. For power savings, clocks are blocked before entering any muxes.
0x1: ILO : Internal Low Speed Oscillator (ILO)
0x2: WCO : Watch-Crystal Oscillator (WCO)
0x3: BAK : Root of the Backup domain clock tree (BAK)
0x4: ALTLF : Alternate low-frequency clock input to SRSS (ALTLF)
0x5: LFCLK : Root of the low-speed clock tree (LFCLK)
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
557
CLK_OUTPUT_SLOW
9.1.19
CLK_OUTPUT_SLOW (continued)
0x6: IMO : Internal Main Oscillator (IMO). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit.
0x7: SLPCTRL : Sleep Controller clock (SLPCTRL). This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit.
0x8: PILO : Precision Internal Low Speed Oscillator (PILO)
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
558
CLK_CAL_CNT1
9.1.20 CLK_CAL_CNT1
Address = 0x4026051C Clock Calibration Counter 1 Address: 0x4026051C Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
A
Name
CAL_COUNTER1 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
A
Name
CAL_COUNTER1 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
A
Name
CAL_COUNTER1 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
None
HW Access
W
None
Name
CAL_COUN TER_DONE
None [30:24]
Bits 31
23 : 0
Name CAL_COUNTER_DONE
CAL_COUNTER1
Description
Status bit indicating that the internal counter #1 is finished counting and CLK_CAL_CNT2.COUNTER stopped counting up Default Value: 1
Down-counter clocked on fast clock output #0 (see CLK_OUTPUT_FAST). This register always reads as zero. Counting starts internally when this register is written with a nonzero value. CAL_COUNTER_DONE goes immediately low to indicate that the counter has started and will be asserted when the counters are done. Do not write this field unless CAL_COUNTER_DONE==1. Both clocks must be running or the measurement will not complete. A stalled counter can be recovered by selecting valid clocks, waiting until the measurement completes, and discarding the first result. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
559
CLK_CAL_CNT2
9.1.21 CLK_CAL_CNT2
Address = 0x40260520 Clock Calibration Counter 2 Address: 0x40260520 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
RW
Name
CAL_COUNTER2 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
RW
Name
CAL_COUNTER2 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
RW
Name
CAL_COUNTER2 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 23 : 0
Name CAL_COUNTER2
Description
Up-counter clocked on fast clock output #1 (see CLK_OUTPUT_FAST). When CLK_CAL_CNT1.CAL_COUNTER_DONE==1, the counter is stopped and can be read by SW. Do not read this value unless CAL_COUNTER_DONE==1. The expected final value is related to the ratio of clock frequencies used for the two counters and the value loaded into counter 1: CLK_CAL_CNT2.COUNTER=(F_cnt2/F_cnt1)*(CLK_CAL_CNT1.COUNTER) Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
560
CLK_ECO_CONFIG
9.1.22 CLK_ECO_CONFIG
Address = 0x4026052C ECO Configuration Register Address: 0x4026052C Retention: Retained
Bits
7
6
5
4
3
2
SW Access
None
HW Access
None
Name
None [7:2]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
SW Access
RW
None
HW Access
R
None
Name
ECO_EN
None [30:24]
1 RW R AGC_EN
9
0 None None None
8
17
16
25
24
Bits
Name
31
ECO_EN
1
AGC_EN
Description
Master enable for ECO oscillator. Default Value: 0
Automatic Gain Control (AGC) enable. When set, the oscillation amplitude is controlled to the level selected by ECO_TRIM0.ATRIM. When low, the amplitude is not explicitly controlled and can be as high as the vddd supply. WARNING: use care when disabling AGC because driving a crystal beyond its rated limit can permanently damage the crystal. Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
561
CLK_ECO_STATUS
9.1.23 CLK_ECO_STATUS
Address = 0x40260530 ECO Status Register Address: 0x40260530 Retention: Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:2]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
0
R
R
W
W
ECO_READ Y
ECO_OK
10
9
8
18
17
16
26
25
24
Bits
Name
1
ECO_READY
0
ECO_OK
Description
Indicates the ECO internal oscillator circuit has had enough time to fully stabilize. This is the output of a counter since ECO was enabled, and it does not check the ECO output. It is recommended to also confirm ECO_OK==1. Default Value: 0
Indicates the ECO internal oscillator circuit has sufficient amplitude. It may not meet the PPM accuracy or duty cycle spec. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
562
CLK_PILO_CONFIG
9.1.24 CLK_PILO_CONFIG
Address = 0x4026053C Precision ILO Configuration Register Address: 0x4026053C Retention: Retained
Bits
7
6
5
4
3
SW Access
RW
HW Access
R
Name
PILO_FFREQ [7:0]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:10]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
RW
RW
RW
HW Access
R
R
R
Name
PILO_EN
PILO_RESET_N
PILO_CLK_EN
2
10
18
26 None None None [28:24]
1
0
9
8
RW
R
PILO_FFREQ [9:8]
17
16
25
24
Bits
Name
31
PILO_EN
30
PILO_RESET_N
29
PILO_CLK_EN
9 : 0
PILO_FFREQ
Description
Enable PILO. When enabling PILO, set PILO_EN=1, wait 1ms, then PILO_RESET_N=1 and PILO_CLK_EN=1. When disabling PILO, clear PILO_EN=0, PILO_RESET_N=0, and PLO_CLK_EN=0 in the same write cycle. Default Value: 0
Reset the PILO. See PILO_EN field for required sequencing. Default Value: 0
Enable the PILO clock output. See PILO_EN field for required sequencing. Default Value: 0
Fine frequency trim allowing +/-250ppm accuracy with periodic calibration. The nominal step size of the LSB is 8Hz. Default Value: 128
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
563
CLK_FLL_CONFIG
9.1.25 CLK_FLL_CONFIG
Address = 0x40260580 FLL Configuration Register Address: 0x40260580 Retention: Retained
Bits
7
6
SW Access
HW Access
Name
Bits
15
14
SW Access
HW Access
Name
Bits
23
22
SW Access
HW Access
Name
Bits
31
30
SW Access
RW
HW Access
R
Name
FLL_ENABLE
5
4
3
RW
R
FLL_MULT [7:0]
13
12
11
RW
R
FLL_MULT [15:8]
21
20
19
None
None
None [23:18]
29
28
27
None
None
None [30:25]
2
1
0
10
9
8
18
17
16
RW
R
FLL_MULT [17:16]
26
25
24
RW
R
FLL_OUTPUT_DIV
Bits
Name
31
FLL_ENABLE
Description
Master enable for FLL. The FLL requires firmware sequencing when enabling, disabling, and entering/exiting DEEPSLEEP. To enable the FLL, first enable the CCO by writing CLK_FLL_CONFIG4.CCO_ENABLE=1 and wait until CLK_FLL_STATUS.CCO_READY==1. Next, ensure the reference clock has stabilized and CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF. Next, write FLL_ENABLE=1 and wait until CLK_FLL_STATUS.LOCKED==1. Finally, write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_OUT to switch to the FLL output. It takes seven reference clock cycles plus four FLL output cycles to switch to the FLL output. Do not disable the FLL before this time completes. To disable the FLL, write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF and (optionally) read the same register to ensure the write completes. Then, wait at least seven FLL reference clock cycles before disabling it with FLL_ENABLE=0. Lastly, disable the CCO by writing CLK_FLL_CONFIG4.CCO_ENABLE=0. Before entering DEEPSLEEP, either disable the FLL using above sequence or use the following procedure to deselect/select it before/after DEEPSLEEP. Before entering DEEPSLEEP, write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF to change the FLL to use its reference clock. After DEEPSLEEP wakeup, wait until CLK_FLL_STATUS.LOCKED==1 and then write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_OUT to switch to the FLL output. 0: Block is powered off 1: Block is powered on Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
564
CLK_FLL_CONFIG
9.1.25
24
17 : 0
CLK_FLL_CONFIG (continued)
FLL_OUTPUT_DIV FLL_MULT
Control bits for Output divider. Set the divide value before enabling the FLL, and do not change it while FLL is enabled. 0: no division 1: divide by 2 Default Value: 1
Multiplier to determine CCO frequency in multiples of the frequency of the selected reference clock (Fref). Ffll = (FLL_MULT) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV+1) Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
565
CLK_FLL_CONFIG2
9.1.26 CLK_FLL_CONFIG2
Address = 0x40260584 FLL Configuration Register 2 Address: 0x40260584 Retention: Retained
Bits
7
6
5
SW Access
HW Access
Name
Bits SW Access HW Access
Name
15
14
13
None
None
None [15:13]
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4
3
2
1
RW
R
FLL_REF_DIV [7:0]
12
11
10
9
RW
R
FLL_REF_DIV [12:8]
20
19
18
17
RW
R
LOCK_TOL [23:16]
28
27
26
25
None
None
None [31:25]
0
8
16
24 RW R LOCK_TOL
Bits 24 : 16
Name LOCK_TOL
12 : 0
FLL_REF_DIV
Description
Lock tolerance sets the error threshold for when the FLL output is considered locked to the reference input. A high tolerance can be used to lock more quickly or to track a less accurate source. The tolerance should be set so that the FLL does not unlock under normal conditions. The tolerance is the allowed difference between the count value for the ideal formula and the measured value. 0: tolerate error of 1 count value 1: tolerate error of 2 count values ... 511: tolerate error of 512 count values Default Value: 2
Control bits for reference divider. Set the divide value before enabling the FLL, and do not change it while FLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 8191: divide by 8191 Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
566
CLK_FLL_CONFIG3
9.1.27 CLK_FLL_CONFIG3
Address = 0x40260588 FLL Configuration Register 3 Address: 0x40260588 Retention: Retained
Bits
7
6
5
4
SW Access
RW
HW Access
R
Name
FLL_LF_PGAIN [7:4]
3
2
1
0
RW
R
FLL_LF_IGAIN [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
SETTLING_COUNT [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
HW Access
None
R
Name
None [23:21]
SETTLING_COUNT [20:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
RW
None
HW Access
None
R
None
Name
None [31:30]
BYPASS_SEL [29:28]
None [27:24]
Bits 29 : 28
Name BYPASS_SEL
Description Bypass mux located just after FLL output. See FLL_ENABLE description for instructions on how to use this field when enabling/disabling the FLL. Default Value: 0 0x0: AUTO : Reserved
0x1: AUTO1 : Reserved
0x2: FLL_REF : Select FLL reference input (bypass mode). Ignores lock indicator
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
567
CLK_FLL_CONFIG3
9.1.27
CLK_FLL_CONFIG3 (continued)
0x3: FLL_OUT : Select FLL output. Ignores lock indicator.
20 : 8
SETTLING_COUNT
7 : 4
FLL_LF_PGAIN
3 : 0
FLL_LF_IGAIN
Number of undivided reference clock cycles to wait after changing the CCO trim until the loop measurement restarts. A delay allows the CCO output to settle and gives a more accurate measurement. The default is tuned to an 8MHz reference clock since the IMO is expected to be the most common use case. 0: no settling time 1: wait one reference clock cycle ... 8191: wait 8191 reference clock cycles Default Value: 40
FLL Loop Filter Gain Setting #2. The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN. 0: 1/256 1: 1/128 2: 1/64 3: 1/32 4: 1/16 5: 1/8 6: 1/4 7: 1/2 8: 1.0 9: 2.0 10: 4.0 11: 8.0 >=12: illegal Default Value: 0
FLL Loop Filter Gain Setting #1. The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN. 0: 1/256 1: 1/128 2: 1/64 3: 1/32 4: 1/16 5: 1/8 6: 1/4 7: 1/2 8: 1.0 9: 2.0 10: 4.0 11: 8.0 >=12: illegal Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
568
CLK_FLL_CONFIG4
9.1.28 CLK_FLL_CONFIG4
Address = 0x4026058C FLL Configuration Register 4 Address: 0x4026058C Retention: Retained
Bits
7
6
5
SW Access
HW Access
Name
Bits
15
SW Access
HW Access
Name
14
13
None
None
None [15:11]
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
RW
RW
HW Access
R
R
Name
CCO_ENABLE
CCO_HW_ UP-
DATE_DIS
4
3
RW
R
CCO_LIMIT [7:0]
12
11
20
19
RW
RW
CCO_FREQ [23:16]
28
27
None
None
None [29:25]
2
1
0
10
9
8
RW
R
CCO_RANGE [10:8]
18
17
16
26
25
24
RW
RW
CCO_FREQ
Bits 31
30
24 : 16
10 : 8
Name CCO_ENABLE
CCO_HW_UPDATE_DIS
CCO_FREQ
CCO_RANGE
Description
Enable the CCO. It is required to enable the CCO before using the FLL. 0: Block is powered off 1: Block is powered on Default Value: 0
Disable CCO frequency update by FLL hardware 0: Hardware update of CCO settings is allowed. Use this setting for normal FLL operation. 1: Hardware update of CCO settings is disabled. Use this setting for open-loop FLL operation. Default Value: 0
CCO frequency code. This is updated by HW when the FLL is enabled. It can be manually updated to use the CCO in an open loop configuration. The meaning of each frequency code depends on the range. Default Value: 0
Frequency range of CCO Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
569
CLK_FLL_CONFIG4
9.1.28
CLK_FLL_CONFIG4 (continued)
0x0: RANGE0 : Target frequency is in range [48, 64) MHz
0x1: RANGE1 : Target frequency is in range [64, 85) MHz
0x2: RANGE2 : Target frequency is in range [85, 113) MHz
0x3: RANGE3 : Target frequency is in range [113, 150) MHz
0x4: RANGE4 : Target frequency is in range [150, 200] MHz
7 : 0
CCO_LIMIT
Maximum CCO offset allowed (used to prevent FLL dynamics from selecting an CCO frequency that the logic cannot support) Default Value: 255
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
570
CLK_FLL_STATUS
9.1.29 CLK_FLL_STATUS
Address = 0x40260590 FLL Status Register Address: 0x40260590 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:3]
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4
3
12
11
None
None
None [15:8]
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
2 R RW
CCO_REA DY
1
RW1C
A
UNLOCK_OCCURRED
0 R W
LOCKED
10
9
8
18
17
16
26
25
24
Bits
Name
Description
2
CCO_READY
This indicates that the CCO is internally settled and ready to use. Default Value: 0
1
UNLOCK_OCCURRED Reserved. Do not use.
Default Value: 0
0
LOCKED
FLL Lock Indicator. LOCKED is high when FLL is within CLK_FLL_CONFIG2.LOCK_TOL. If FLL is outside LOCK_TOL, LOCKED goes low. Note that this can happen during normal operation, if FLL needs to recalculate due to a change in the reference clock, change in voltage, or change in temperature. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
571
CLK_PLL_CONFIG0
9.1.30 CLK_PLL_CONFIG0
Address = 0x40260600 PLL Configuration Register Address: 0x40260600 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None
FEEDBACK_DIV [6:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
RW
HW Access
None
R
Name
None [15:13]
REFERENCE_DIV [12:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
HW Access
None
R
Name
None [23:21]
OUTPUT_DIV [20:16]
Bits SW Access HW Access
Name
31 RW R
ENABLE
30 None None
None
29
28
RW
R
BYPASS_SEL [29:28]
27
RW
R
PLL_LF_MODE
26
25
24
None
None
None [26:24]
Bits
Name
31
ENABLE
29 : 28
BYPASS_SEL
Description
Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1. To disable the PLL, first deselect it using .BYPASS_SEL=PLL_REF, wait at least six PLL clock cycles, and then disable it with .ENABLE=0. Fpll = (FEEDBACK_DIV) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV) 0: Block is disabled 1: Block is enabled Default Value: 0
Bypass mux located just after PLL output. This selection is glitch-free and can be changed while the PLL is running. Default Value: 0
0x0: AUTO :
Automatic using lock indicator. When unlocked, automatically selects PLL reference input (bypass mode). When locked, automatically selects PLL output.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
572
CLK_PLL_CONFIG0
9.1.30
CLK_PLL_CONFIG0 (continued)
0x1: AUTO1 : Same as AUTO
0x2: PLL_REF : Select PLL reference input (bypass mode). Ignores lock indicator
0x3: PLL_OUT : Select PLL output. Ignores lock indicator.
27
PLL_LF_MODE
20 : 16
OUTPUT_DIV
12 : 8
REFERENCE_DIV
6 : 0
FEEDBACK_DIV
VCO frequency range selection. Configure this bit according to the targeted VCO frequency. Do not change this setting while the PLL is enabled. 0: VCO frequency is [200MHz, 400MHz] 1: VCO frequency is [170MHz, 200MHz) Default Value: 0
Control bits for Output divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: illegal (undefined behavior) 2: divide by 2. Suitable for direct usage as HFCLK source. ... 16: divide by 16. Suitable for direct usage as HFCLK source. >16: illegal (undefined behavior) Default Value: 2
Control bits for reference divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0: illegal (undefined behavior) 1: divide by 1 ... 20: divide by 20 others: illegal (undefined behavior) Default Value: 1
Control bits for feedback divider. Set the divide value before enabling the PLL, and do not change it while PLL is enabled. 0-21: illegal (undefined behavior) 22: divide by 22 ... 112: divide by 112 >112: illegal (undefined behavior) Default Value: 22
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
573
CLK_PLL_STATUS0
9.1.31 CLK_PLL_STATUS0
Address = 0x40260640 PLL Status Register Address: 0x40260640 Retention: Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:2]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
0
RW1C
R
A
W
UNLOCK_OCCURRED
LOCKED
10
9
8
18
17
16
26
25
24
Bits
Name
Description
1
UNLOCK_OCCURRED This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware.
Default Value: 0
0
LOCKED
PLL Lock Indicator Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
574
SRSS_INTR
9.1.32 SRSS_INTR
Address = 0x40260700 SRSS Interrupt Register Address: 0x40260700 Retention: Retained
Bits SW Access HW Access
Name
7
6
5
4
3
2
None
RW1C
None
None
A
None
None [7:6]
CLK_CAL
None [4:2]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
1 RW1C
A HVLVD1
9
0 RW1C
A WDT_MATCH
8
17
16
25
24
Bits
Name
5
CLK_CAL
1
HVLVD1
0
WDT_MATCH
Description
Clock calibration counter is done. This field is reset during DEEPSLEEP mode. Default Value: 0
Interrupt for low voltage detector HVLVD1 Default Value: 0
WDT Interrupt Request. This bit is set each time WDT_COUNTR==WDT_MATCH. W1C also feeds the watch dog. Missing 2 interrupts in a row will generate a reset. Due to internal synchronization, it takes 2 SYSCLK cycles to update after a W1C. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
575
SRSS_INTR_SET
9.1.33 SRSS_INTR_SET
Address = 0x40260704 SRSS Interrupt Set Register Address: 0x40260704 Retention: Retained
Bits SW Access HW Access
Name
7
6
5
4
3
2
None
RW1S
None
None
A
None
None [7:6]
CLK_CAL
None [4:2]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
1 RW1S
A HVLVD1
9
0 RW1S
A WDT_MATCH
8
17
16
25
24
Bits
Name
5
CLK_CAL
1
HVLVD1
0
WDT_MATCH
Description
Set interrupt for clock calibration counter done. This field is reset during DEEPSLEEP mode. Default Value: 0
Set interrupt for low voltage detector HVLVD1 Default Value: 0
Set interrupt for low voltage detector WDT_MATCH Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
576
SRSS_INTR_MASK
9.1.34 SRSS_INTR_MASK
Address = 0x40260708 SRSS Interrupt Mask Register Address: 0x40260708 Retention: Retained
Bits SW Access HW Access
Name
7
6
5
4
3
2
None
RW
None
None
R
None
None [7:6]
CLK_CAL
None [4:2]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
1 RW R HVLVD1
9
0 RW R WDT_MATCH
8
17
16
25
24
Bits
Name
5
CLK_CAL
1
HVLVD1
0
WDT_MATCH
Description
Mask for clock calibration done Default Value: 0
Mask for low voltage detector HVLVD1 Default Value: 0
Mask for watchdog timer. Clearing this bit will not forward the interrupt to the CPU. It will not, however, disable the WDT reset generation on 2 missed interrupts. When WDT resets the chip, it also internally pends an interrupt that survives the reset. To prevent unintended ISR execution, clear SRSS_INTR.WDT_MATCH before setting this bit. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
577
SRSS_INTR_MASKED
9.1.35 SRSS_INTR_MASKED
Address = 0x4026070C SRSS Interrupt Masked Register Address: 0x4026070C Retention: Retained
Bits SW Access HW Access
Name
7
6
5
4
3
2
None
R
None
None
RW
None
None [7:6]
CLK_CAL
None [4:2]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
1 R RW HVLVD1
9
0 R RW WDT_MATCH
8
17
16
25
24
Bits
Name
5
CLK_CAL
1
HVLVD1
0
WDT_MATCH
Description
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
578
SRSS_INTR_CFG
9.1.36 SRSS_INTR_CFG
Address = 0x40260710 SRSS Interrupt Configuration Register Address: 0x40260710 Retention: Retained
Bits
7
6
SW Access
HW Access
Name
Bits
15
14
SW Access
HW Access
Name
Bits
23
22
SW Access
HW Access
Name
Bits
31
30
SW Access
HW Access
Name
5
4
3
None
None
None [7:2]
13
12
11
None
None
None [15:8]
21
20
19
None
None
None [23:16]
29
28
27
None
None
None [31:24]
2
1
0
RW
R
HVLVD1_EDGE_SEL [1:0]
10
9
8
18
17
16
26
25
24
Bits 1 : 0
Name HVLVD1_EDGE_SEL
Description Sets which edge(s) will trigger an IRQ for HVLVD1 Default Value: 0 0x0: DISABLE : Disabled
0x1: RISING : Rising edge
0x2: FALLING : Falling edge
0x3: BOTH : Both rising and falling edges
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
579
RES_CAUSE
9.1.37 RES_CAUSE
Address = 0x40260800 Reset Cause Observation Register Address: 0x40260800 Retention: Retained
Bits SW Access HW Access
Name
7 RW1C
A
6 RW1C
A
5 RW1C
A
RESET_MCW
DT2
RESET_MCW
DT1
RESET_MCW
DT0
4 RW1C
A
RESET_SOFT
3
RW1C
A
RESET_CSV_ WCO_LOS
S
2 RW1C
A
RESET_DPSLP_FAULT
1 RW1C
A
RESET_ACT_-
FAULT
0 RW1C
A
RESET_WDT
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:9]
9
8
RW1C
A
RESET_MCW
DT3
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
8
RESET_MCWDT3
7
RESET_MCWDT2
6
RESET_MCWDT1
5
RESET_MCWDT0
4
RESET_SOFT
Description
Multi-Counter Watchdog timer reset #3 has occurred since last power cycle. This hardware is not present in PSoC6 devices. Default Value: 0
Multi-Counter Watchdog timer reset #2 has occurred since last power cycle. This hardware is not present in PSoC6 devices. Default Value: 0
Multi-Counter Watchdog timer reset #1 has occurred since last power cycle. Default Value: 0
Multi-Counter Watchdog timer reset #0 has occurred since last power cycle. Default Value: 0
A CPU requested a system reset through it's SYSRESETREQ. This can be done via a debugger probe or in firmware. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
580
RES_CAUSE
9.1.37
3 2 1 0
RES_CAUSE (continued)
RESET_CSV_WCO_LOSS RESET_DPSLP_FAULT
RESET_ACT_FAULT
RESET_WDT
Clock supervision logic requested a reset due to loss of a watch-crystal clock. Default Value: 0
Fault logging system requested a reset from its DeepSleep logic. Default Value: 0
Fault logging system requested a reset from its Active logic. Default Value: 0
A basic WatchDog Timer (WDT) reset has occurred since last power cycle. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
581
RES_CAUSE2
9.1.38 RES_CAUSE2
Address = 0x40260804 Reset Cause Observation Register 2 Address: 0x40260804 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW1C
HW Access
A
Name
RESET_CSV_HF_LOSS [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW1C
HW Access
A
Name
RESET_CSV_HF_LOSS [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW1C
HW Access
A
Name
RESET_CSV_HF_FREQ [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW1C
HW Access
A
Name
RESET_CSV_HF_FREQ [31:24]
Bits 31 : 16
15 : 0
Name RESET_CSV_HF_FREQ
RESET_CSV_HF_LOSS
Description
Clock supervision logic requested a reset due to frequency error of high-frequency clock. Each bit index K corresponds to a HFCLK. Unimplemented clock bits return zero. Default Value: 0
Clock supervision logic requested a reset due to loss of a high-frequency clock. Each bit index K corresponds to a HFCLK. Unimplemented clock bits return zero. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
582
PWR_TRIM_REF_CTL
9.1.39 PWR_TRIM_REF_CTL
Address = 0x40267F00 Reference Trim Register Address: 0x40267F00 Retention: Retained
Bits SW Access HW Access
Name
7
6
5
4
RW
A
ACT_REF_ITRIM [7:4]
Bits
15
14
13
12
SW Access
None
RW
None
HW Access
None
A
None
Name
None
ACT_REF_I BOOST
None
Bits SW Access HW Access
Name
23
22
21
20
RW
A
DPSLP_REF_ABSTRIM [23:20]
Bits SW Access HW Access
Name
31
30
29
28
RW
A
DPSLP_REF_ITRIM [31:28]
3
2
1
0
RW
A
ACT_REF_TCTRIM [3:0]
11
10
9
8
RW
A
ACT_REF_ABSTRIM [12:8]
19
18
17
16
RW
A
DPSLP_REF_TCTRIM [19:16]
27
26
25
None
None
None [27:25]
24
RW
A
DPSLP_REF_A
BSTRIM
Bits 31 : 28 24 : 20 19 : 16
14
Name DPSLP_REF_ITRIM DPSLP_REF_ABSTRIM DPSLP_REF_TCTRIM
ACT_REF_IBOOST
Description
DeepSleep current reference trim. This register is only reset by XRES/POR/BOD/HIBERNATE. Default Value: 7
DeepSleep-Reference absolute voltage trim. This register is only reset by XRES/POR/BOD/HIBERNATE. Default Value: 15
DeepSleep-Reference temperature trim. This register is only reset by XRES/POR/BOD/HIBERNATE. 0 -> default setting at POR; not for trimming use others -> normal trim range Default Value: 0
Active-Reference current boost. This register is only reset by XRES/POR/BOD/HIBERNATE. 0: normal operation others: risk mitigation Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
583
PWR_TRIM_REF_CTL
9.1.39
12 : 8
7 : 4 3 : 0
PWR_TRIM_REF_CTL (continued)
ACT_REF_ABSTRIM ACT_REF_ITRIM ACT_REF_TCTRIM
Active-Reference absolute voltage trim. This register is only reset by XRES/POR/BOD/HIBERNATE. 0 -> default setting at POR; not for trimming use others -> normal trim range Default Value: 0
Active-Reference current trim. This register is only reset by XRES/POR/BOD/HIBERNATE. 0 -> default setting at POR; not for trimming use others -> normal trim range Default Value: 0
Active-Reference temperature trim. This register is only reset by XRES/POR/BOD/HIBERNATE. 0 -> default setting at POR; not for trimming use others -> normal trim range Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
584
PWR_TRIM_BODOVP_CTL
9.1.40 PWR_TRIM_BODOVP_CTL
Address = 0x40267F04 BOD/OVP Trim Register Address: 0x40267F04 Retention: Retained
Bits SW Access HW Access
Name
7
RW
A
HVPORBOD_ITRIM
6
5
4
RW
A
HVPORBOD_OFSTRIM [6:4]
3 None None
None
2
1
0
RW
A
HVPORBOD_TRIPSEL [2:0]
Bits SW Access HW Access
Name
15
14
RW
A
LVPORBOD_OFSTRIM [15:14]
13 None None
None
12
11
10
RW
A
LVPORBOD_TRIPSEL [12:10]
9
8
RW
A
HVPORBOD_ITRIM [9:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
RW
HW Access
None
A
A
Name
None [23:20]
LVPORBOD_ITRIM [19:17]
LVPORBOD_OF-
STRIM
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 19 : 17 16 : 14 12 : 10
9 : 7 6 : 4 2 : 0
Name LVPORBOD_ITRIM LVPORBOD_OFSTRIM LVPORBOD_TRIPSEL
HVPORBOD_ITRIM HVPORBOD_OFSTRIM HVPORBOD_TRIPSEL
Description
LVPORBOD current trim. This register is only reset by XRES/POR/BOD/HIBERNATE. Default Value: 2
LVPORBOD offset trim. This register is only reset by XRES/POR/BOD/HIBERNATE. Default Value: 0
LVPORBOD trip point selection. Monitors vccd. This register is only reset by XRES/POR/BOD/ HIBERNATE. Default Value: 3
HVPORBOD current trim. This register is only reset by XRES/POR/BOD/HIBERNATE. Default Value: 2
HVPORBOD offset trim. This register is only reset by XRES/POR/BOD/HIBERNATE. Default Value: 0
HVPORBOD trip point selection. Monitors vddd. This register is only reset by XRES/POR/BOD/ HIBERNATE. Default Value: 4
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
585
CLK_TRIM_CCO_CTL
9.1.41 CLK_TRIM_CCO_CTL
Address = 0x40267F08 CCO Trim Register Address: 0x40267F08 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:6]
CCO_RCSTRIM [5:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
None
RW
HW Access
R
None
R
Name
ENABLE_CNT
None
CCO_STABLE_CNT [29:24]
Bits 31 29 : 24 5 : 0
Name ENABLE_CNT CCO_STABLE_CNT CCO_RCSTRIM
Description
Enables the automatic stabilization counter. Default Value: 1
Terminal count for the stabilization counter from CCO_ENABLE until stable. Default Value: 39
CCO reference current source trim. Default Value: 32
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
586
CLK_TRIM_CCO_CTL2
9.1.42 CLK_TRIM_CCO_CTL2
Address = 0x40267F0C CCO Trim Register 2 Address: 0x40267F0C Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
RW
HW Access
R
R
Name
CCO_FCTRIM2 [7:5]
CCO_FCTRIM1 [4:0]
Bits
15
14
SW Access
RW
HW Access
R
Name
CCO_FCTRIM4
13
12
11
RW
R
CCO_FCTRIM3 [14:10]
10
9
8
RW
R
CCO_FCTRIM2 [9:8]
Bits SW Access HW Access
Name
23
22
21
20
RW
R
CCO_FCTRIM5 [23:20]
19
18
17
16
RW
R
CCO_FCTRIM4 [19:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
RW
HW Access
None
R
Name
None [31:25]
CCO_FCTRIM5
Bits 24 : 20 19 : 15 14 : 10 9 : 5 4 : 0
Name CCO_FCTRIM5 CCO_FCTRIM4 CCO_FCTRIM3 CCO_FCTRIM2 CCO_FCTRIM1
Description
CCO frequency 5th range calibration Default Value: 8
CCO frequency 4th range calibration Default Value: 16
CCO frequency 3rd range calibration Default Value: 16
CCO frequency 2nd range calibration Default Value: 8
CCO frequency 1st range calibration Default Value: 16
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
587
PWR_TRIM_WAKE_CTL
9.1.43 PWR_TRIM_WAKE_CTL
Address = 0x40267F30 Wakeup Trim Register Address: 0x40267F30 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
WAKE_DELAY [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 0
Name WAKE_DELAY
Description
Wakeup holdoff. Spec (fastest) wake time is achieved with a setting of 0. Additional delay can be added for debugging or workaround. The delay is counted by the IMO. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
588
PWR_TRIM_LVD_CTL
9.1.44 PWR_TRIM_LVD_CTL
Address = 0x4026FF10 LVD Trim Register Address: 0x4026FF10 Retention: Retained
Bits SW Access HW Access
Name
7 None None None
6
5
4
RW
R
HVLVD1_ITRIM [6:4]
3 None None None
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
Bits 6 : 4
2 : 0
Name HVLVD1_ITRIM
HVLVD1_OFSTRIM
Description
HVLVD1 current trim Default Value: 2
HVLVD1 offset trim Default Value: 0
2
1
0
RW
R
HVLVD1_OFSTRIM [2:0]
10
9
8
18
17
16
26
25
24
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
589
CLK_TRIM_ILO_CTL
9.1.45 CLK_TRIM_ILO_CTL
Address = 0x4026FF18 ILO Trim Register Address: 0x4026FF18 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
A
Name
None [7:6]
ILO_FTRIM [5:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 5 : 0
Name ILO_FTRIM
Description
ILO frequency trims. LSB step size is 1.5% (typical) of the frequency. Default Value: 44
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
590
PWR_TRIM_PWRSYS_CTL
9.1.46 PWR_TRIM_PWRSYS_CTL
Address = 0x4026FF1C Power System Trim Register Address: 0x4026FF1C Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
A
Name
None [7:5]
ACT_REG_TRIM [4:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
None
HW Access
A
None
Name
ACT_REG_BOOST [31:30]
None [29:24]
Bits 31 : 30
Name ACT_REG_BOOST
Description
Controls the tradeoff between output current and internal operating current for the Active Regulator. The maximum output current depends on the silicon implementation, but an application may limit its maximum current to less than that. This may allow a reduction in the internal operating current of the regulator. The regulator internal operating current depends on the boost setting: 2'b00: 50uA 2'b01: 100uA 2'b10: 150uA 2'b11: 200uA The allowed setting is a lookup table based on the chip-specific maximum (set in factory) and an application-specific maximum (set by customer). The defaults are set assuming the application consumes the maximum allowed by the chip. 50mA chip: 2'b00 (default); 100mA chip: 2'b00 (default); 150mA chip: 50..100mA app => 2'b00, 150mA app => 2'b01 (default); 200mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200mA app => 2'b10 (default); 250mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200..250mA app => 2'b10 (default); 300mA chip: 50mA app => 2'b00, 100..150mA app => 2'b01, 200..250mA app => 2'b10, 300mA app => 2'b11 (default); This register is only reset by XRES/POR/BOD/HIBERNATE. Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
591
PWR_TRIM_PWRSYS_CTL
9.1.46
4 : 0
PWR_TRIM_PWRSYS_CTL (continued)
ACT_REG_TRIM
Trim for the Active-Regulator. This sets the output voltage level. This register is only reset by XRES/POR/BOD/HIBERNATE. Two voltages are supported: 0.9V and 1.1V. The codes for these are stored in SFLASH_LDO_0P9V_TRIM and SFLASH_LDO_1P1V_TRIM, respectively. Default Value: 23
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
592
CLK_TRIM_ECO_CTL
9.1.47 CLK_TRIM_ECO_CTL
Address = 0x4026FF20 ECO Trim Register Address: 0x4026FF20 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
RW
R
ATRIM [7:4]
4
3
2
None
None
None
Bits SW Access HW Access
Name
15
14
None
None
None [15:14]
13
12
RW
R
GTRIM [13:12]
11
10
RW
R
RTRIM [11:10]
Bits
23
22
21
20
19
18
SW Access
None
RW
HW Access
None
R
Name
None [23:22]
ITRIM [21:16]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
1
0
RW
R
WDTRIM [2:0]
9
8
RW
R
FTRIM [9:8]
17
16
25
24
Bits 21 : 16 13 : 12 11 : 10 9 : 8
Name ITRIM GTRIM RTRIM FTRIM
Description
Current Trim Default Value: 31
Gain Trim - Startup time Default Value: 0
Feedback resistor Trim Default Value: 0
Filter Trim - 3rd harmonic oscillation Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
593
CLK_TRIM_ECO_CTL
9.1.47
7 : 4
2 : 0
CLK_TRIM_ECO_CTL (continued)
ATRIM WDTRIM
Amplitude trim to set the crystal drive level when ECO_CONFIG.AGC_EN=1. WARNING: use care when setting this field because driving a crystal beyond its rated limit can permanently damage the crystal. 0x0 - 150mV 0x1 - 175mV 0x2 - 200mV 0x3 - 225mV 0x4 - 250mV 0x5 - 275mV 0x6 - 300mV 0x7 - 325mV 0x8 - 350mV 0x9 - 375mV 0xA - 400mV 0xB - 425mV 0xC - 450mV 0xD - 475mV 0xE - 500mV 0xF - 525mV Default Value: 0
Watch Dog Trim - Delta voltage below steady state level 0x0 - 50mV 0x1 - 75mV 0x2 - 100mV 0x3 - 125mV 0x4 - 150mV 0x5 - 175mV 0x6 - 200mV 0x7 - 225mV Default Value: 3
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
594
CLK_TRIM_PILO_CTL
9.1.48 CLK_TRIM_PILO_CTL
Address = 0x4026FF24 PILO Trim Register Address: 0x4026FF24 Retention: Retained
Bits
7
6
5
4
SW Access
None
HW Access
None
Name
None [7:6]
Bits SW Access HW Access
Name
15 None None None
14
13
12
RW
R
PILO_OSC_TRIM [14:12]
Bits SW Access HW Access
Name
23
22
21
20
RW
R
PILO_RES_TRIM [23:20]
Bits SW Access HW Access
Name
31 None None
None
30
29
28
RW
R
PILO_VTDIFF_TRIM [30:28]
3
2
1
0
RW
R
PILO_CFREQ [5:0]
11
10
9
8
None
None
None [11:8]
19
18
RW
R
PILO_NBIAS_TRIM [19:18]
17
16
RW
R
PILO_COMP_TRIM [17:16]
27
26
RW
R
PILO_ISLOPE_TRIM [27:26]
25 None None
None
24
RW
R
PILO_RES_T
RIM
Bits 30 : 28 27 : 26 24 : 20 19 : 18 17 : 16 14 : 12
Name PILO_VTDIFF_TRIM PILO_ISLOPE_TRIM PILO_RES_TRIM PILO_NBIAS_TRIM PILO_COMP_TRIM PILO_OSC_TRIM
Description
Trim for VT-DIFF output (internal power supply) Default Value: 0
Trim for beta-multiplier current slope Default Value: 0
Trim for beta-multiplier branch current Default Value: 16
Trim for biasn by trimming sub-Vth NMOS width in beta-multiplier Default Value: 2
Trim for comparator bias current. Default Value: 0
Trim for current in oscillator block. Default Value: 5
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
595
CLK_TRIM_PILO_CTL
9.1.48
5 : 0
CLK_TRIM_PILO_CTL (continued)
PILO_CFREQ
Coarse frequency trim to meet 32.768kHz +/-2% across PVT without calibration. The nominal step size of the LSB is 1kHz. Default Value: 15
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
596
CLK_TRIM_PILO_CTL2
9.1.49 CLK_TRIM_PILO_CTL2
Address = 0x4026FF28 PILO Trim Register 2 Address: 0x4026FF28 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
PILO_VREF_TRIM [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
RW
HW Access
None
R
Name
None [15:13]
PILO_IREFBM_TRIM [12:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
PILO_IREF_TRIM [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 23 : 16 12 : 8 7 : 0
Name PILO_IREF_TRIM PILO_IREFBM_TRIM PILO_VREF_TRIM
Description
Trim for current reference Default Value: 218
Trim for beta-multiplier current reference Default Value: 16
Trim for voltage reference Default Value: 224
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
597
CLK_TRIM_PILO_CTL3
9.1.50 CLK_TRIM_PILO_CTL3
Address = 0x4026FF2C PILO Trim Register 3 Address: 0x4026FF2C Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
PILO_ENGOPT [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
PILO_ENGOPT [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 0
Name PILO_ENGOPT
Description
Engineering options for PILO circuits 0: Short vdda to vpwr 1: Beta:mult current change 2: Iref generation Ptat current addition 3: Disable current path in secondary Beta:mult startup circuit 4: Double oscillator current 5: Switch between deep:sub:threshold and sub:threshold stacks in Vref generation block 6: Spare 7: Ptat component increase in Iref 8: vpwr_rc and vpwr_dig_rc shorting testmode 9: Switch b/w psub connection for cascode nfet for vref generation 10: Switch between sub:threshold and deep:sub:threshold stacks in comparator. 15-11: Frequency fine trim. See AKK-444 for an overview of the trim strategy. Default Value: 18432
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
598
10 Multi-Counter WDT (MCWDT) Registers
This section discusses the Multi-Counter WDT (MCWDT) registers. It lists all the registers in mapping tables, in address order.
10.1 Register Details
Register
Address
Description
MCWDT_CNTLOW0
0x40260204 Multi-Counter Watchdog Sub-counters 0/1
MCWDT_CNTHIGH0
0x40260208 Multi-Counter Watchdog Sub-counter 2
MCWDT_MATCH0
0x4026020C Multi-Counter Watchdog Counter Match Register
MCWDT_CONFIG0
0x40260210 Multi-Counter Watchdog Counter Configuration
MCWDT_CTL0
0x40260214 Multi-Counter Watchdog Counter Control
MCWDT_INTR0
0x40260218 Multi-Counter Watchdog Counter Interrupt Register
MCWDT_INTR_SET0
0x4026021C Multi-Counter Watchdog Counter Interrupt Set Register
MCWDT_INTR_MASK0 0x40260220 Multi-Counter Watchdog Counter Interrupt Mask Register
MCWDT_INTR_MASKED0 0x40260224 Multi-Counter Watchdog Counter Interrupt Masked Register
MCWDT_LOCK0
0x40260228 Multi-Counter Watchdog Counter Lock Register
MCWDT_CNTLOW1
0x40260244 Multi-Counter Watchdog Sub-counters 0/1. See MCWDT_CNTLOW0 for the details of bit fields.
MCWDT_CNTHIGH1
0x40260248 Multi-Counter Watchdog Sub-counter 2. See MCWDT_CNTHIGH0 for the details of bit fields.
MCWDT_MATCH1
0x4026024C Multi-Counter Watchdog Counter Match Register. See MCWDT_MATCH0 for the details of bit fields.
MCWDT_CONFIG1
0x40260250 Multi-Counter Watchdog Counter Configuration. See MCWDT_CONFIG0 for the details of bit fields.
MCWDT_CTL1
0x40260254 Multi-Counter Watchdog Counter Control. See MCWDT_CTL0 for the details of bit fields.
MCWDT_INTR1
0x40260258 Multi-Counter Watchdog Counter Interrupt Register. See MCWDT_INTR0 for the details of bit fields.
MCWDT_INTR_SET1
0x4026025C Multi-Counter Watchdog Counter Interrupt Set Register. See MCWDT_INTR_SET0 for the details of bit fields.
MCWDT_INTR_MASK1 0x40260260 Multi-Counter Watchdog Counter Interrupt Mask Register. See MCWDT_INTR_MASK0 for the details of bit fields.
MCWDT_INTR_MASKED1 0x40260264
Multi-Counter Watchdog Counter Interrupt Masked Register. See MCWDT_INTR_MASKED0 for the details of bit fields.
MCWDT_LOCK1
0x40260268 Multi-Counter Watchdog Counter Lock Register. See MCWDT_LOCK0 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
599
MCWDT_CNTLOW0
10.1.1 MCWDT_CNTLOW0
Address = 0x40260204 Multi-Counter Watchdog Sub-counters 0/1 Address: 0x40260204 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
A
Name
WDT_CTR0 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
A
Name
WDT_CTR0 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
A
Name
WDT_CTR1 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
A
Name
WDT_CTR1 [31:24]
Bits 31 : 16
Name WDT_CTR1
15 : 0
WDT_CTR0
Description
Current value of sub-counter 1 for this MCWDT. Software writes are ignored when the sub-counter is enabled Default Value: 0
Current value of sub-counter 0 for this MCWDT. Software writes are ignored when the sub-counter is enabled. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
600
MCWDT_CNTHIGH0
10.1.2 MCWDT_CNTHIGH0
Address = 0x40260208 Multi-Counter Watchdog Sub-counter 2 Address: 0x40260208 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
A
Name
WDT_CTR2 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
A
Name
WDT_CTR2 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
A
Name
WDT_CTR2 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
A
Name
WDT_CTR2 [31:24]
Bits 31 : 0
Name WDT_CTR2
Description
Current value of sub-counter 2 for this MCWDT. Software writes are ignored when the sub-counter is enabled Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
601
MCWDT_MATCH0
10.1.3 MCWDT_MATCH0
Address = 0x4026020C Multi-Counter Watchdog Counter Match Register Address: 0x4026020C Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
WDT_MATCH0 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
WDT_MATCH0 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
WDT_MATCH1 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
WDT_MATCH1 [31:24]
Bits 31 : 16
15 : 0
Name WDT_MATCH1
WDT_MATCH0
Description
Match value for sub-counter 1 of this MCWDT Default Value: 0
Match value for sub-counter 0 of this MCWDT Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
602
MCWDT_CONFIG0
10.1.4 MCWDT_CONFIG0
Address = 0x40260210 Multi-Counter Watchdog Counter Configuration Address: 0x40260210 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:4]
Bits
15
SW Access
HW Access
Name
14
13
None
None
None [15:12]
Bits
23
22
21
SW Access
HW Access
Name
Bits SW Access HW Access
Name
31
30
29
None
None
None [31:29]
4
3
2
1
0
RW
RW
RW
R
R
R
WDT_CASCADE0_1
WDT_CLEAR0
WDT_MODE0 [1:0]
12
11
10
9
8
RW
RW
RW
R
R
R
WDT_CASCADE1_2
WDT_CLEAR1
WDT_MODE1 [9:8]
20
19
18
17
16
None
RW
None
R
None [23:17]
WDT_MODE2
28
27
26
25
24
RW
R
WDT_BITS2 [28:24]
Bits 28 : 24
Name WDT_BITS2
16
WDT_MODE2
Description
Bit to observe for WDT_INT2: 0: Assert after bit0 of WDT_CTR2 toggles (one int every tick) ... 31: Assert after bit31 of WDT_CTR2 toggles (one int every 2^31 ticks) Default Value: 0
Watchdog Counter 2 Mode. Default Value: 0
0x0: NOTHING :
Free running counter with no interrupt requests
0x1: INT :
Free running counter with interrupt request that occurs one LFCLK cycle after the specified bit in CTR2 toggles (see WDT_BITS2).
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
603
MCWDT_CONFIG0
10.1.4
11
10
9 : 8
MCWDT_CONFIG0 (continued)
WDT_CASCADE1_2 WDT_CLEAR1 WDT_MODE1
Cascade Watchdog Counters 1,2. Counter 2 increments the cycle after WDT_CTR1=WDT_MATCH1. It is allowed to cascade all three WDT counters. 0: Independent counters 1: Cascaded counters. When cascading all three counters, WDT_CLEAR1 must be 1. Default Value: 0
Clear Watchdog Counter when WDT_CTR1==WDT_MATCH1. In other words WDT_CTR1 divides LFCLK by (WDT_MATCH1+1). 0: Free running counter 1: Clear on match. In this mode, the minimum legal setting of WDT_MATCH1 is 1. Default Value: 0
Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR1=WDT_MATCH1). Default Value: 0
0x0: NOTHING :
Do nothing
0x1: INT : Assert WDT_INTx
0x2: RESET : Assert WDT Reset
0x3: INT_THEN_RESET : Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt
3
WDT_CASCADE0_1
Cascade Watchdog Counters 0,1. Counter 1 increments the cycle after WDT_CTR0=WDT_-
MATCH0.
0: Independent counters
1: Cascaded counters
Default Value: 0
2
WDT_CLEAR0
Clear Watchdog Counter when WDT_CTR0=WDT_MATCH0. In other words WDT_CTR0 divides LFCLK by (WDT_MATCH0+1). 0: Free running counter 1: Clear on match. In this mode, the minimum legal setting of WDT_MATCH0 is 1. Default Value: 0
1 : 0
WDT_MODE0
Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR0=WDT_MATCH0). Default Value: 0
0x0: NOTHING :
Do nothing
0x1: INT : Assert WDT_INTx
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
604
MCWDT_CONFIG0
10.1.4
MCWDT_CONFIG0 (continued)
0x2: RESET : Assert WDT Reset
0x3: INT_THEN_RESET : Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
605
MCWDT_CTL0
10.1.5 MCWDT_CTL0
Address = 0x40260214 Multi-Counter Watchdog Counter Control Address: 0x40260214 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:4]
Bits
15
SW Access
HW Access
Name
14
13
None
None
None [15:12]
Bits
23
SW Access
HW Access
Name
22
21
None
None
None [23:20]
Bits
31
30
29
SW Access
HW Access
Name
4
3
RW1S
RW0C
WDT_RESET0
12
11
RW1S
RW0C
WDT_RESET1
20
19
RW1S
RW0C
WDT_RESET2
28
27
None
None
None [31:24]
2 None None None
10 None None None
18 None None None
26
1
R
RW
WDT_ENABLED0
0
RW
R
WDT_ENABLE0
9
R
RW
WDT_ENABLED1
8
RW
R
WDT_ENABLE1
17
R
RW
WDT_ENABLED2
16
RW
R
WDT_ENABLE2
25
24
Bits
Name
19
WDT_RESET2
17
WDT_ENABLED2
16
WDT_ENABLE2
11
WDT_RESET1
9
WDT_ENABLED1
Description
Resets counter 2 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect. Default Value: 0
Indicates actual state of counter. May lag WDT_ENABLE2 by up to two LFCLK cycles. Default Value: 0
Enable subcounter 2. May take up to 2 LFCLK cycles to take effect. 0: Counter is disabled (not clocked) 1: Counter is enabled (counting up) Default Value: 0
Resets counter 1 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect. Default Value: 0
Indicates actual state of counter. May lag WDT_ENABLE1 by up to two LFCLK cycles. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
606
MCWDT_CTL0
10.1.5
8
3 1 0
MCWDT_CTL0 (continued)
WDT_ENABLE1
WDT_RESET0 WDT_ENABLED0 WDT_ENABLE0
Enable subcounter 1. May take up to 2 LFCLK cycles to take effect. 0: Counter is disabled (not clocked) 1: Counter is enabled (counting up) Default Value: 0
Resets counter 0 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect. Default Value: 0
Indicates actual state of counter. May lag WDT_ENABLE0 by up to two LFCLK cycles. Default Value: 0
Enable subcounter 0. May take up to 2 LFCLK cycles to take effect. 0: Counter is disabled (not clocked) 1: Counter is enabled (counting up) Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
607
MCWDT_INTR0
10.1.6 MCWDT_INTR0
Address = 0x40260218 Multi-Counter Watchdog Counter Interrupt Register Address: 0x40260218 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:3]
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4
3
12
11
None
None
None [15:8]
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
2
1
0
RW1C
RW1C
RW1C
A
A
A
MCWDT_IN MCWDT_IN MCWDT_IN
T2
T1
T0
10
9
8
18
17
16
26
25
24
Bits
Name
2
MCWDT_INT2
1
MCWDT_INT1
0
MCWDT_INT0
Description
MCWDT Interrupt Request for sub-counter 2. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE2=3. Default Value: 0
MCWDT Interrupt Request for sub-counter 1. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE1=3. Default Value: 0
MCWDT Interrupt Request for sub-counter 0. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODE0=3. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
608
MCWDT_INTR_SET0
10.1.7 MCWDT_INTR_SET0
Address = 0x4026021C Multi-Counter Watchdog Counter Interrupt Set Register Address: 0x4026021C Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:3]
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4
3
12
11
None
None
None [15:8]
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
2
1
0
RW1S
RW1S
RW1S
A
A
A
MCWDT_IN MCWDT_IN MCWDT_IN
T2
T1
T0
10
9
8
18
17
16
26
25
24
Bits
Name
2
MCWDT_INT2
1
MCWDT_INT1
0
MCWDT_INT0
Description
Set interrupt for MCWDT_INT2 Default Value: 0
Set interrupt for MCWDT_INT1 Default Value: 0
Set interrupt for MCWDT_INT0 Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
609
MCWDT_INTR_MASK0
10.1.8 MCWDT_INTR_MASK0
Address = 0x40260220 Multi-Counter Watchdog Counter Interrupt Mask Register Address: 0x40260220 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:3]
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4
3
12
11
None
None
None [15:8]
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
2
1
0
RW
RW
RW
R
R
R
MCWDT_IN MCWDT_IN MCWDT_IN
T2
T1
T0
10
9
8
18
17
16
26
25
24
Bits
Name
2
MCWDT_INT2
1
MCWDT_INT1
0
MCWDT_INT0
Description
Interrupt Mask for sub-counter 2. The bit controls if the interrupt is forwarded to the CPU. The interrupt is blocked when the value of the bit is 0. The interrupt is forwarded if the value of the bit is 1. Default Value: 0
Interrupt Mask for sub-counter 1. The bit controls if the interrupt is forwarded to the CPU. The interrupt is blocked when the value of the bit is 0. The interrupt is forwarded if the value of the bit is 1. Default Value: 0
Interrupt Mask for sub-counter 0. The bit controls if the interrupt is forwarded to the CPU. The interrupt is blocked when the value of the bit is 0. The interrupt is forwarded if the value of the bit is 1. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
610
MCWDT_INTR_MASKED0
10.1.9 MCWDT_INTR_MASKED0
Address = 0x40260224 Multi-Counter Watchdog Counter Interrupt Masked Register Address: 0x40260224 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:3]
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4
3
12
11
None
None
None [15:8]
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
2
1
0
R
R
R
RW
RW
RW
MCWDT_IN MCWDT_IN MCWDT_IN
T2
T1
T0
10
9
8
18
17
16
26
25
24
Bits
Name
2
MCWDT_INT2
1
MCWDT_INT1
0
MCWDT_INT0
Description
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
611
MCWDT_LOCK0
10.1.10 MCWDT_LOCK0
Address = 0x40260228 Multi-Counter Watchdog Counter Lock Register Address: 0x40260228 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
None
HW Access
A
None
Name
MCWDT_LOCK [31:30]
None [29:24]
Bits 31 : 30
Name MCWDT_LOCK
Description Prohibits writing control and configuration registers related to this MCWDT when not equal 0 (as specified in the other register descriptions). Requires at least two different writes to unlock. Note that this field is 2 bits to force multiple writes only. Each MCWDT has a separate local lock. LFCLK settings are locked by the global WDT_LOCK register, and this register has no effect on that. Default Value: 0 0x0: NO_CHG :
No effect
0x1: CLR0 :
Clears bit 0
0x2: CLR1 :
Clears bit 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
612
10.1.10
MCWDT_LOCK0 (continued)
0x3: SET01 : Sets both bits 0 and 1
MCWDT_LOCK0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
613
11 Backup System Registers
This section discusses the Backup System registers. It lists all the registers in mapping tables, in address order.
11.1 Register Details
Register BACKUP_CTL BACKUP_RTC_RW BACKUP_CAL_CTL BACKUP_STATUS BACKUP_RTC_TIME BACKUP_RTC_DATE BACKUP_ALM1_TIME BACKUP_ALM1_DATE BACKUP_ALM2_TIME BACKUP_ALM2_DATE BACKUP_INTR BACKUP_INTR_SET BACKUP_INTR_MASK BACKUP_INTR_MASKED BACKUP_OSCCNT BACKUP_TICKS BACKUP_PMIC_CTL BACKUP_RESET BACKUP_BREG0 BACKUP_BREG1 BACKUP_BREG2 BACKUP_BREG3 BACKUP_BREG4 BACKUP_BREG5 BACKUP_BREG6 BACKUP_BREG7 BACKUP_BREG8
Address 0x40270000 0x40270008 0x4027000C 0x40270010 0x40270014 0x40270018 0x4027001C 0x40270020 0x40270024 0x40270028 0x4027002C 0x40270030 0x40270034 0x40270038 0x4027003C 0x40270040 0x40270044 0x40270048 0x40271000 0x40271004 0x40271008 0x4027100C 0x40271010 0x40271014 0x40271018 0x4027101C 0x40271020
Description Control RTC Read Write register Oscillator calibration for absolute frequency Status Calendar Seconds, Minutes, Hours, Day of Week Calendar Day of Month, Month, Year Alarm 1 Seconds, Minute, Hours, Day of Week Alarm 1 Day of Month, Month Alarm 2 Seconds, Minute, Hours, Day of Week Alarm 2 Day of Month, Month Interrupt request register Interrupt set request register Interrupt mask register Interrupt masked request register 32kHz oscillator counter 128Hz tick counter PMIC control register Backup reset register Backup register region Backup register region. See BACKUP_BREG0 for the details of bit fields. Backup register region. See BACKUP_BREG0 for the details of bit fields. Backup register region. See BACKUP_BREG0 for the details of bit fields. Backup register region. See BACKUP_BREG0 for the details of bit fields. Backup register region. See BACKUP_BREG0 for the details of bit fields. Backup register region. See BACKUP_BREG0 for the details of bit fields. Backup register region. See BACKUP_BREG0 for the details of bit fields. Backup register region. See BACKUP_BREG0 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
614
Register BACKUP_BREG9 BACKUP_BREG10 BACKUP_BREG11 BACKUP_BREG12 BACKUP_BREG13 BACKUP_BREG14 BACKUP_BREG15 BACKUP_TRIM
Backup System Registers
Address 0x40271024 0x40271028 0x4027102C 0x40271030 0x40271034 0x40271038 0x4027103C 0x4027FF00
Description Backup register region. See BACKUP_BREG0 for the details of bit fields. Backup register region. See BACKUP_BREG0 for the details of bit fields. Backup register region. See BACKUP_BREG0 for the details of bit fields. Backup register region. See BACKUP_BREG0 for the details of bit fields. Backup register region. See BACKUP_BREG0 for the details of bit fields. Backup register region. See BACKUP_BREG0 for the details of bit fields. Backup register region. See BACKUP_BREG0 for the details of bit fields. Trim Register
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
615
BACKUP_CTL
11.1.1 BACKUP_CTL
Address = 0x40270000 Control Address: 0x40270000 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:4]
4
3
2
1
0
RW
None
A
None
WCO_EN
None
Bits SW Access HW Access
Name
15
14
None
None
None [15:14]
13
12
RW
A
PRESCALER [13:12]
11
10
None
None
None [11:10]
9
8
RW
A
CLK_SEL [9:8]
Bits
23
SW Access
HW Access
Name
22
21
None
None
None [23:20]
20
19
18
17
16
RW
RW
RW
A
A
A
VBACKUP_MEAS
VDDBAK_CTL [18:17]
WCO_BYPASS
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
A
Name
EN_CHARGE_KEY [31:24]
Bits 31 : 24
Name EN_CHARGE_KEY
19
VBACKUP_MEAS
18 : 17
VDDBAK_CTL
Description
When set to 3C, the supercap charger circuit is enabled. Any other code disables the supercap charger. THIS CHARGING CIRCUIT IS FOR A SUPERCAP ONLY AND CANNOT SAFELY CHARGE A BATTERY. DO NOT WRITE THIS KEY WHEN VBACKUP IS CONNECTED TO A BATTERY. Default Value: 0
Connect vbackup supply to the vbackup_meas output for measurement by an ADC attached to amuxbusa_adft_vddd. The vbackup_meas signal is scaled by 40% so it is within the supply range of the ADC. Default Value: 0
Controls the behavior of the switch that generates vddbak from vbackup or vddd. 0: automatically select vddd if its brownout detector says it is valid. If the brownout says its not valid, then use vmax which is the highest of vddd or vbackup. 1,2,3: force vddbak and vmax to select vbackup, regardless of its voltage. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
616
BACKUP_CTL
11.1.1
16
13 : 12
9 : 8
BACKUP_CTL (continued)
WCO_BYPASS PRESCALER CLK_SEL
Configures the WCO for different board-level connections to the WCO pins. For example, this can be used to connect an external watch crystal oscillator instead of a watch crystal. In all cases, the two related GPIO pins (WCO input and output pins) must be configured as analog connections using GPIO registers, and they must be hooked at the board level as described below. Configure this field before enabling the WCO, and do not change this setting when WCO_EN=1. 0: Watch crystal. Connect a 32.768 kHz watch crystal between WCO input and output pins. 1: Clock signal, either a square wave or sine wave. See PRESCALER field for connection information. Default Value: 0
Prescaler for real time clock used when WCO_BYPASS=1. Configure this field before enabling the WCO, and do not change this setting when WCO_EN=1. 0: 32768 Hz square wave. Connect a 32768 Hz square wave to WCO output pin. Do not connect WCO input pin. 1: 60 Hz sine wave. Connect an AC-coupled sine wave to WCO input pin. Do not connect the WCO output pin at the board level. 2: 50 Hz sine wave. Connect an AC-couple sine wave to WCO input pin. Do not connect the WCO output pin at the board level. 3: reserved (32768 Hz) Default Value: 0
Clock select for BAK clock Default Value: 0
0x0: WCO :
Watch-crystal oscillator input.
0x1: ALTBAK :
This allows to use the LFCLK selection as an alternate backup domain clock. Note that LFCLK is not available in all power modes, and clock glitches can propagate into the backup logic when the clock is stopped. For this reason, if the WCO is intended as the clock source then choose it directly instead of routing through LFCLK.
3
WCO_EN
Watch-crystal oscillator (WCO) enable. If there is a write in progress when this bit is cleared, the WCO will be internally kept on until the write completes. After enabling the WCO software must wait until STATUS.WCO_OK=1 before configuring any component that depends on clk_lf/clk_bak, like for example RTC or WDTs. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
617
BACKUP_RTC_RW
11.1.2 BACKUP_RTC_RW
Address = 0x40270008 RTC Read Write register Address: 0x40270008 Retention: Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:2]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
0
RW
RW
A
A
WRITE
READ
10
9
8
18
17
16
26
25
24
Bits
Name
1
WRITE
0
READ
Description
Write bit Only when this bit is set can the RTC registers be written to (otherwise writes are ignored). This bit cannot be set if the RTC is still busy with a previous update (see RTC_BUSY bit) or if the Read bit is set or getting set. The user writes to the RTC user registers, when the Write bit is cleared by the user then the user registers content is copied to the actual RTC registers. Only user RTC registers that were written to will get copied, others will not be affected. When the SECONDS field is updated then TICKS will also be reset (WDT is not affected). When the Write bit is cleared by a reset (brown out/DeepSleep) then the RTC update will be ignored/lost. Do not set the Write bit if the RTC if the RTC is still busy with a previous update (see RTC_BUSY). Do not set the Write bit at the same time that the Read bit is cleared. Default Value: 0
Read bit When this bit is set the RTC registers will be copied to user registers and frozen so that a coherent RTC value can safely be read. The RTC will keep on running. Do not set the read bit if the RTC is still busy with a previous update (see RTC_BUSY bit) or if the Write bit is set. Do not set the Read bit at the same time that the Write bit is cleared. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
618
BACKUP_CAL_CTL
11.1.3 BACKUP_CAL_CTL
Address = 0x4027000C Oscillator calibration for absolute frequency Address: 0x4027000C Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
RW
HW Access
None
A
A
Name
None
CALIB_SIGN
CALIB_VAL [5:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
None
HW Access
A
None
Name
CAL_OUT
None [30:24]
Bits
Name
31
CAL_OUT
6
CALIB_SIGN
5 : 0
CALIB_VAL
Description
Output enable for 512Hz signal for calibration and allow CALIB_VAL to be written. Note that calibration does not affect the 512Hz output signal. Default Value: 0
Calibration sign: 0= Negative sign: remove pulses (it takes more clock ticks to count one second) 1= Positive sign: add pulses (it takes less clock ticks to count one second) Default Value: 0
Calibration value for absolute frequency (at a fixed temperature). Each step causes 128 ticks to be added or removed each hour. Effectively that means that each step is 1.085ppm (= 128/ (60*60*32,768)). Positive values 0x01-0x3c (1..60) add pulses, negative values remove pulses, thus giving a range of +/-65.1 ppm (limited by 60 minutes per hour, not the range of this field) Calibration is performed hourly, starting at 59 minutes and 59 seconds, and applied as 64 ticks every 30 seconds until there have been 2*CALIB_VAL adjustments. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
619
BACKUP_STATUS
11.1.4 BACKUP_STATUS
Address = 0x40270010 Status Address: 0x40270010 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:3]
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4
3
12
11
None
None
None [15:8]
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
2 R W WCO_OK
10
1 None None None
9
0 R W RTC_BUSY
8
18
17
16
26
25
24
Bits
Name
2
WCO_OK
0
RTC_BUSY
Description
Indicates that output has transitioned. Default Value: 0
pending RTC write Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
620
BACKUP_RTC_TIME
11.1.5 BACKUP_RTC_TIME
Address = 0x40270014 Calendar Seconds, Minutes, Hours, Day of Week Address: 0x40270014 Retention: Retained
Bits
7
6
5
SW Access
None
HW Access
None
Name
None
Bits
15
14
13
SW Access
None
HW Access
None
Name
None
Bits SW Access HW Access
Name
23
22
21
None
RW
None
A
None
CTRL_12H R
Bits
31
SW Access
HW Access
Name
30
29
None
None
None [31:27]
4
3
2
1
0
RW
A
RTC_SEC [6:0]
12
11
10
9
8
RW
A
RTC_MIN [14:8]
20
19
18
17
16
RW
A
RTC_HOUR [21:16]
28
27
26
25
24
RW
A
RTC_DAY [26:24]
Bits 26 : 24
Name RTC_DAY
22 21 : 16
CTRL_12HR RTC_HOUR
14 : 8 6 : 0
RTC_MIN RTC_SEC
Description
Calendar Day of the week in BCD, 1-7 It is up to the user to define the meaning of the values, but 1=Monday is recommended Default Value: 0
Select 12/24HR mode: 1=12HR, 0=24HR Default Value: 0
Calendar hours in BCD, value depending on 12/24HR mode 0=24HR: [21:16]=0-23 1=12HR: [21]:0=AM, 1=PM, [20:16]=1-12 Default Value: 0
Calendar minutes in BCD, 0-59 Default Value: 0
Calendar seconds in BCD, 0-59 Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
621
BACKUP_RTC_DATE
11.1.6 BACKUP_RTC_DATE
Address = 0x40270018 Calendar Day of Month, Month, Year Address: 0x40270018 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
A
Name
None [7:6]
RTC_DATE [5:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
RW
HW Access
None
A
Name
None [15:13]
RTC_MON [12:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
A
Name
RTC_YEAR [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 23 : 16 12 : 8 5 : 0
Name RTC_YEAR RTC_MON RTC_DATE
Description
Calendar year in BCD, 0-99 Default Value: 0
Calendar Month in BCD, 1-12 Default Value: 0
Calendar Day of the Month in BCD, 1-31 Automatic Leap Year Correction Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
622
BACKUP_ALM1_TIME
11.1.7 BACKUP_ALM1_TIME
Address = 0x4027001C Alarm 1 Seconds, Minute, Hours, Day of Week Address: 0x4027001C Retention: Retained
Bits
7
6
5
4
SW Access
RW
HW Access
A
Name
ALM_SEC_ EN
Bits
15
14
13
12
SW Access
RW
HW Access
A
Name
ALM_MIN_ EN
Bits
23
22
21
20
SW Access
RW
None
HW Access
A
None
Name
ALM_HOU R_EN
None
Bits
31
30
SW Access
RW
HW Access
A
Name
ALM_DAY_EN
29
28
None
None
None [30:27]
3
2
1
0
RW
A
ALM_SEC [6:0]
11
10
9
8
RW
A
ALM_MIN [14:8]
19
18
17
16
RW
A
ALM_HOUR [21:16]
27
26
25
24
RW
A
ALM_DAY [26:24]
Bits 31
26 : 24
Name ALM_DAY_EN
ALM_DAY
23 21 : 16
ALM_HOUR_EN ALM_HOUR
15
ALM_MIN_EN
Description
Alarm Day of the Week enable: 0=ignore, 1=match Default Value: 0
Alarm Day of the week in BCD, 1-7 It is up to the user to define the meaning of the values, but 1=Monday is recommended Default Value: 1
Alarm hour enable: 0=ignore, 1=match Default Value: 0
Alarm hours in BCD, value depending on 12/24HR mode 12HR: [5]:0=AM, 1=PM, [4:0]=1-12 24HR: [5:0]=0-23 Default Value: 0
Alarm minutes enable: 0=ignore, 1=match Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
623
11.1.7
14 : 8 7 6 : 0
BACKUP_ALM1_TIME (continued)
ALM_MIN ALM_SEC_EN ALM_SEC
Alarm minutes in BCD, 0-59 Default Value: 0
Alarm second enable: 0=ignore, 1=match Default Value: 0
Alarm seconds in BCD, 0-59 Default Value: 0
BACKUP_ALM1_TIME
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
624
BACKUP_ALM1_DATE
11.1.8 BACKUP_ALM1_DATE
Address = 0x40270020 Alarm 1 Day of Month, Month Address: 0x40270020 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
None
RW
HW Access
A
None
A
Name
ALM_DATE_EN
None
ALM_DATE [5:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
None
RW
HW Access
A
None
A
Name
ALM_MON_ EN
None [14:13]
ALM_MON [12:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
None
HW Access
A
None
Name
ALM_EN
None [30:24]
Bits
Name
31
ALM_EN
15 12 : 8 7 5 : 0
ALM_MON_EN ALM_MON ALM_DATE_EN ALM_DATE
Description
Master enable for alarm 1. 0: Alarm 1 is disabled. Fields for date and time are ignored. 1: Alarm 1 is enabled. If none of the date and time fields are enabled, then this alarm triggers once every second. Default Value: 0
Alarm Month enable: 0=ignore, 1=match Default Value: 0
Alarm Month in BCD, 1-12 Default Value: 1
Alarm Day of the Month enable: 0=ignore, 1=match Default Value: 0
Alarm Day of the Month in BCD, 1-31 Leap Year corrected Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
625
BACKUP_ALM2_TIME
11.1.9 BACKUP_ALM2_TIME
Address = 0x40270024 Alarm 2 Seconds, Minute, Hours, Day of Week Address: 0x40270024 Retention: Retained
Bits
7
6
5
4
SW Access
RW
HW Access
A
Name
ALM_SEC_ EN
Bits
15
14
13
12
SW Access
RW
HW Access
A
Name
ALM_MIN_ EN
Bits
23
22
21
20
SW Access
RW
None
HW Access
A
None
Name
ALM_HOU R_EN
None
Bits
31
30
SW Access
RW
HW Access
A
Name
ALM_DAY_EN
29
28
None
None
None [30:27]
3
2
1
0
RW
A
ALM_SEC [6:0]
11
10
9
8
RW
A
ALM_MIN [14:8]
19
18
17
16
RW
A
ALM_HOUR [21:16]
27
26
25
24
RW
A
ALM_DAY [26:24]
Bits 31
26 : 24
Name ALM_DAY_EN
ALM_DAY
23 21 : 16
ALM_HOUR_EN ALM_HOUR
15
ALM_MIN_EN
Description
Alarm Day of the Week enable: 0=ignore, 1=match Default Value: 0
Alarm Day of the week in BCD, 1-7 It is up to the user to define the meaning of the values, but 1=Monday is recommended Default Value: 1
Alarm hour enable: 0=ignore, 1=match Default Value: 0
Alarm hours in BCD, value depending on 12/24HR mode 12HR: [5]:0=AM, 1=PM, [4:0]=1-12 24HR: [5:0]=0-23 Default Value: 0
Alarm minutes enable: 0=ignore, 1=match Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
626
11.1.9
14 : 8 7 6 : 0
BACKUP_ALM2_TIME (continued)
ALM_MIN ALM_SEC_EN ALM_SEC
Alarm minutes in BCD, 0-59 Default Value: 0
Alarm second enable: 0=ignore, 1=match Default Value: 0
Alarm seconds in BCD, 0-59 Default Value: 0
BACKUP_ALM2_TIME
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
627
BACKUP_ALM2_DATE
11.1.10 BACKUP_ALM2_DATE
Address = 0x40270028 Alarm 2 Day of Month, Month Address: 0x40270028 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
None
RW
HW Access
A
None
A
Name
ALM_DATE_EN
None
ALM_DATE [5:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
None
RW
HW Access
A
None
A
Name
ALM_MON_ EN
None [14:13]
ALM_MON [12:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
None
HW Access
A
None
Name
ALM_EN
None [30:24]
Bits
Name
31
ALM_EN
15 12 : 8 7 5 : 0
ALM_MON_EN ALM_MON ALM_DATE_EN ALM_DATE
Description
Master enable for alarm 2. 0: Alarm 2 is disabled. Fields for date and time are ignored. 1: Alarm 2 is enabled. If none of the date and time fields are enabled, then this alarm triggers once every second. Default Value: 0
Alarm Month enable: 0=ignore, 1=match Default Value: 0
Alarm Month in BCD, 1-12 Default Value: 1
Alarm Day of the Month enable: 0=ignore, 1=match Default Value: 0
Alarm Day of the Month in BCD, 1-31 Leap Year corrected Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
628
BACKUP_INTR
11.1.11 BACKUP_INTR
Address = 0x4027002C Interrupt request register Address: 0x4027002C Retention: Retained
Bits
7
6
SW Access
HW Access
Name
Bits
15
14
SW Access
HW Access
Name
Bits
23
22
SW Access
HW Access
Name
Bits
31
30
SW Access
HW Access
Name
5 None None None [7:3]
13
21
29
4
3
12
11
None
None
None [15:8]
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
2 RW1C RW1S CENTURY
10
1 RW1C RW1S ALARM2
9
0 RW1C RW1S ALARM1
8
18
17
16
26
25
24
Bits
Name
2
CENTURY
1
ALARM2
0
ALARM1
Description
Century overflow interrupt Default Value: 0
Alarm 2 Interrupt Default Value: 0
Alarm 1 Interrupt Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
629
BACKUP_INTR_SET
11.1.12 BACKUP_INTR_SET
Address = 0x40270030 Interrupt set request register Address: 0x40270030 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:3]
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4
3
12
11
None
None
None [15:8]
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
2 RW1S
A CENTURY
10
1 RW1S
A ALARM2
9
0 RW1S
A ALARM1
8
18
17
16
26
25
24
Bits
Name
2
CENTURY
1
ALARM2
0
ALARM1
Description
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
630
BACKUP_INTR_MASK
11.1.13 BACKUP_INTR_MASK
Address = 0x40270034 Interrupt mask register Address: 0x40270034 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:3]
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4
3
12
11
None
None
None [15:8]
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
2 RW R CENTURY
10
1 RW R ALARM2
9
0 RW R ALARM1
8
18
17
16
26
25
24
Bits
Name
2
CENTURY
1
ALARM2
0
ALARM1
Description
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
631
BACKUP_INTR_MASKED
11.1.14 BACKUP_INTR_MASKED
Address = 0x40270038 Interrupt masked request register Address: 0x40270038 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:3]
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4
3
12
11
None
None
None [15:8]
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
2 R RW CENTURY
10
1 R RW ALARM2
9
0 R RW ALARM1
8
18
17
16
26
25
24
Bits
Name
2
CENTURY
1
ALARM2
0
ALARM1
Description
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
632
BACKUP_OSCCNT
11.1.15 BACKUP_OSCCNT
Address = 0x4027003C 32kHz oscillator counter Address: 0x4027003C Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
A
Name
CNT32KHZ [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 0
Name CNT32KHZ
Description
32kHz oscillator count (msb=128Hz), calibration can cause bit 6 to skip. Reset when RTC_TIME.RTC_SEC fields is written. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
633
BACKUP_TICKS
11.1.16 BACKUP_TICKS
Address = 0x40270040 128Hz tick counter Address: 0x40270040 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
R
HW Access
None
A
Name
None [7:6]
CNT128HZ [5:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 5 : 0
Name CNT128HZ
Description
128Hz counter (msb=2Hz) When SECONDS is written this field will be reset. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
634
BACKUP_PMIC_CTL
11.1.17 BACKUP_PMIC_CTL
Address = 0x40270044 PMIC control register Address: 0x40270044 Retention: Retained
Bits
7
6
5
4
3
2
1
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
14
13
12
11
10
9
SW Access
RW
HW Access
A
Name
UNLOCK [15:8]
Bits
23
22
21
20
19
18
17
SW Access
None
HW Access
None
Name
None [23:17]
Bits
31
30
29
28
SW Access
RW
RW1S
RW
HW Access
A
R
A
Name
PMIC_EN
PMIC_AL- PMIC_EN_
WAYSEN
OUTEN
27
26
25
None
None
None [28:24]
0
8
16 RW A POLARITY 24
Bits
Name
Description
31
PMIC_EN
Enable for external PMIC that supplies vddd (if present). This bit will only clear if UNLOCK was written correctly in a previous write operation and PMIC_ALWAYSEN=0. When PMIC_EN=0, the system functions normally until vddd is no longer present (OFF w/Backup mode). Firmware can set this bit, if it does so before vddd is actually removed. This bit is also set by any RTC alarm or PMIC pin wakeup event regardless of UNLOCK setting. Default Value: 1
30
PMIC_ALWAYSEN
Override normal PMIC controls to prevent accidentally turning off the PMIC by errant firmware.
0: Normal operation, PMIC_EN and PMIC_OUTEN work as described
1: PMIC_EN and PMIC_OUTEN are ignored and the output pad is forced enabled.
Note: This bit is a write-once bit until the next backup reset.
Default Value: 0
29
PMIC_EN_OUTEN
Output enable for the output driver in the PMIC_EN pad.
0: Output pad is tristate for PMIC_EN pin. This can allow this pin to be used for another purpose.
Tristate condition is kept only if the UNLOCK key (0x3A) is present
1: Output pad is enabled for PMIC_EN pin.
Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
635
BACKUP_PMIC_CTL
11.1.17 BACKUP_PMIC_CTL (continued)
16
POLARITY
15 : 8
UNLOCK
Set polarity of wakeup signal used to enable the PMIC. Always write this bit "1". 0: reserved for future use, 1: PMIC enables when wakeup signal is high. Default Value: 0
This byte must be set to 0x3A for PMIC to be disabled. When the UNLOCK code is not present: writes to PMIC_EN field are ignored and the hardware ignores the value in PMIC_EN. Do not change PMIC_EN in the same write cycle as setting/clearing the UNLOCK code; do these in separate write cycles. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
636
BACKUP_RESET
11.1.18 BACKUP_RESET
Address = 0x40270048 Backup reset register Address: 0x40270048 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW1S
None
HW Access
A
None
Name
RESET
None
Bits
Name
31
RESET
Description
Writing 1 to this register resets the backup logic. Hardware clears it when the reset is complete. After setting this register, firmware should confirm it reads as 0 before attempting to write other backup registers. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
637
BACKUP_BREG0
11.1.19 BACKUP_BREG0
Address = 0x40271000 Backup register region Address: 0x40271000 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
A
Name
BREG [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
A
Name
BREG [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
A
Name
BREG [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
A
Name
BREG [31:24]
Bits 31 : 0
Name BREG
Description
Backup memory that contains application-specific data. Memory is retained on vbackup supply. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
638
BACKUP_TRIM
11.1.20 BACKUP_TRIM
Address = 0x4027FF00 Trim Register Address: 0x4027FF00 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:6]
TRIM [5:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 5 : 0
Name TRIM
Description
WCO trim Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
639
12 Direct Memory Access (DMA) Registers
This section discusses the Direct Memory Access (DMA) registers. It lists all the registers in mapping tables, in address order.
12.1 Register Details
Register DW0_CTL0 DW0_STATUS0 DW0_PENDING0 DW0_STATUS_INTR0 DW0_STATUS_INTR_MASKED0 DW0_ACT_DESCR_CTL0 DW0_ACT_DESCR_SRC0 DW0_ACT_DESCR_DST0 DW0_ACT_DESCR_X_CTL0 DW0_ACT_DESCR_Y_CTL0 DW0_ACT_DESCR_NEXT_PTR0 DW0_ACT_SRC0 DW0_ACT_DST0 DW0_CH_STRUCT0_CH_CTL DW0_CH_STRUCT0_CH_STATUS DW0_CH_STRUCT0_CH_IDX DW0_CH_STRUCT0_CH_CURR_PTR DW0_CH_STRUCT0_INTR DW0_CH_STRUCT0_INTR_SET DW0_CH_STRUCT0_INTR_MASK DW0_CH_STRUCT0_INTR_MASKED DW0_CH_STRUCT1_CH_CTL DW0_CH_STRUCT1_CH_STATUS DW0_CH_STRUCT1_CH_IDX
DW0_CH_STRUCT1_CH_CURR_PTR
DW0_CH_STRUCT1_INTR
Address
Description
0x40280000 Control
0x40280004 Status
0x40280008 Pending channels
0x40280010 System interrupt control
0x40280014 Status of interrupts masked
0x40280020 Active descriptor control
0x40280024 Active descriptor source
0x40280028 Active descriptor destination
0x40280030 Active descriptor X loop control
0x40280034 Active descriptor Y loop control
0x40280038 Active descriptor next pointer
0x40280040 Active source
0x40280044 Active destination
0x40280800 Channel control
0x40280804 Channel status
0x40280808 Channel current indices
0x4028080C Channel current descriptor pointer
0x40280810 Interrupt
0x40280814 Interrupt set
0x40280818 Interrupt mask
0x4028081C Interrupt masked
0x40280820 Channel control. See DW0_CH_STRUCT0_CH_CTL for the details of bit fields.
0x40280824 Channel status. See DW0_CH_STRUCT0_CH_STATUS for the details of bit fields.
0x40280828 0x4028082C
Channel current indices. See DW0_CH_STRUCT0_CH_IDX for the details of bit fields.
Channel current descriptor pointer. See DW0_CH_STRUCT0_CH_CURR_PTR for the details of bit fields.
0x40280830 Interrupt. See DW0_CH_STRUCT0_INTRfor the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
640
Direct Memory Access (DMA) Registers
Register DW0_CH_STRUCT1_INTR_SET DW0_CH_STRUCT1_INTR_MASK DW0_CH_STRUCT1_INTR_MASKED DW0_CH_STRUCT2_CH_CTL DW0_CH_STRUCT2_CH_STATUS DW0_CH_STRUCT2_CH_IDX DW0_CH_STRUCT2_CH_CURR_PTR DW0_CH_STRUCT2_INTR DW0_CH_STRUCT2_INTR_SET DW0_CH_STRUCT2_INTR_MASK DW0_CH_STRUCT2_INTR_MASKED DW0_CH_STRUCT3_CH_CTL DW0_CH_STRUCT3_CH_STATUS DW0_CH_STRUCT3_CH_IDX DW0_CH_STRUCT3_CH_CURR_PTR DW0_CH_STRUCT3_INTR DW0_CH_STRUCT3_INTR_SET DW0_CH_STRUCT3_INTR_MASK DW0_CH_STRUCT3_INTR_MASKED DW0_CH_STRUCT4_CH_CTL DW0_CH_STRUCT4_CH_STATUS DW0_CH_STRUCT4_CH_IDX DW0_CH_STRUCT4_CH_CURR_PTR DW0_CH_STRUCT4_INTR DW0_CH_STRUCT4_INTR_SET DW0_CH_STRUCT4_INTR_MASK DW0_CH_STRUCT4_INTR_MASKED DW0_CH_STRUCT5_CH_CTL DW0_CH_STRUCT5_CH_STATUS DW0_CH_STRUCT5_CH_IDX DW0_CH_STRUCT5_CH_CURR_PTR
Address
Description
0x40280834 Interrupt set. See DW0_CH_STRUCT0_INTR_SETfor the details of bit fields.
0x40280838 Interrupt mask. See DW0_CH_STRUCT0_INTR_MASK for the details of bit fields.
0x4028083C Interrupt masked. See DW0_CH_STRUCT0_INTR_MASKED for the details of bit fields.
0x40280840 Channel control. See DW0_CH_STRUCT0_CH_CTL for the details of bit fields.
0x40280844 Channel status. See DW0_CH_STRUCT0_CH_STATUS for the details of bit fields.
0x40280848 Channel current indices. See DW0_CH_STRUCT0_CH_IDX for the details of bit fields.
0x4028084C
Channel current descriptor pointer. See DW0_CH_STRUCT0_CH_CURR_PTR for the details of bit fields.
0x40280850 Interrupt. See DW0_CH_STRUCT0_INTRfor the details of bit fields.
0x40280854 Interrupt set. See DW0_CH_STRUCT0_INTR_SETfor the details of bit fields.
0x40280858 Interrupt mask. See DW0_CH_STRUCT0_INTR_MASK for the details of bit fields.
0x4028085C Interrupt masked. See DW0_CH_STRUCT0_INTR_MASKED for the details of bit fields.
0x40280860 Channel control. See DW0_CH_STRUCT0_CH_CTL for the details of bit fields.
0x40280864 Channel status. See DW0_CH_STRUCT0_CH_STATUS for the details of bit fields.
0x40280868 Channel current indices. See DW0_CH_STRUCT0_CH_IDX for the details of bit fields.
0x4028086C
Channel current descriptor pointer. See DW0_CH_STRUCT0_CH_CURR_PTR for the details of bit fields.
0x40280870 Interrupt. See DW0_CH_STRUCT0_INTRfor the details of bit fields.
0x40280874 Interrupt set. See DW0_CH_STRUCT0_INTR_SETfor the details of bit fields.
0x40280878 Interrupt mask. See DW0_CH_STRUCT0_INTR_MASK for the details of bit fields.
0x4028087C Interrupt masked. See DW0_CH_STRUCT0_INTR_MASKED for the details of bit fields.
0x40280880 Channel control. See DW0_CH_STRUCT0_CH_CTL for the details of bit fields.
0x40280884 Channel status. See DW0_CH_STRUCT0_CH_STATUS for the details of bit fields.
0x40280888 Channel current indices. See DW0_CH_STRUCT0_CH_IDX for the details of bit fields.
0x4028088C
Channel current descriptor pointer. See DW0_CH_STRUCT0_CH_CURR_PTR for the details of bit fields.
0x40280890 Interrupt. See DW0_CH_STRUCT0_INTRfor the details of bit fields.
0x40280894 Interrupt set. See DW0_CH_STRUCT0_INTR_SETfor the details of bit fields.
0x40280898 Interrupt mask. See DW0_CH_STRUCT0_INTR_MASK for the details of bit fields.
0x4028089C Interrupt masked. See DW0_CH_STRUCT0_INTR_MASKED for the details of bit fields.
0x402808A0 Channel control. See DW0_CH_STRUCT0_CH_CTL for the details of bit fields.
0x402808A4 Channel status. See DW0_CH_STRUCT0_CH_STATUS for the details of bit fields.
0x402808A8 Channel current indices. See DW0_CH_STRUCT0_CH_IDX for the details of bit fields.
0x402808AC
Channel current descriptor pointer. See DW0_CH_STRUCT0_CH_CURR_PTR for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
641
Direct Memory Access (DMA) Registers
Register DW0_CH_STRUCT5_INTR DW0_CH_STRUCT5_INTR_SET DW0_CH_STRUCT5_INTR_MASK DW0_CH_STRUCT5_INTR_MASKED DW0_CH_STRUCT6_CH_CTL DW0_CH_STRUCT6_CH_STATUS DW0_CH_STRUCT6_CH_IDX DW0_CH_STRUCT6_CH_CURR_PTR DW0_CH_STRUCT6_INTR DW0_CH_STRUCT6_INTR_SET DW0_CH_STRUCT6_INTR_MASK DW0_CH_STRUCT6_INTR_MASKED DW0_CH_STRUCT7_CH_CTL DW0_CH_STRUCT7_CH_STATUS DW0_CH_STRUCT7_CH_IDX DW0_CH_STRUCT7_CH_CURR_PTR DW0_CH_STRUCT7_INTR DW0_CH_STRUCT7_INTR_SET DW0_CH_STRUCT7_INTR_MASK DW0_CH_STRUCT7_INTR_MASKED DW0_CH_STRUCT8_CH_CTL DW0_CH_STRUCT8_CH_STATUS DW0_CH_STRUCT8_CH_IDX DW0_CH_STRUCT8_CH_CURR_PTR DW0_CH_STRUCT8_INTR DW0_CH_STRUCT8_INTR_SET DW0_CH_STRUCT8_INTR_MASK DW0_CH_STRUCT8_INTR_MASKED DW0_CH_STRUCT9_CH_CTL DW0_CH_STRUCT9_CH_STATUS DW0_CH_STRUCT9_CH_IDX
Address
Description
0x402808B0 Interrupt. See DW0_CH_STRUCT0_INTRfor the details of bit fields.
0x402808B4 Interrupt set. See DW0_CH_STRUCT0_INTR_SETfor the details of bit fields.
0x402808B8 Interrupt mask. See DW0_CH_STRUCT0_INTR_MASK for the details of bit fields.
0x402808BC Interrupt masked. See DW0_CH_STRUCT0_INTR_MASKED for the details of bit fields.
0x402808C0 Channel control. See DW0_CH_STRUCT0_CH_CTL for the details of bit fields.
0x402808C4 Channel status. See DW0_CH_STRUCT0_CH_STATUS for the details of bit fields.
0x402808C8 Channel current indices. See DW0_CH_STRUCT0_CH_IDX for the details of bit fields.
0x402808CC
Channel current descriptor pointer. See DW0_CH_STRUCT0_CH_CURR_PTR for the details of bit fields.
0x402808D0 Interrupt. See DW0_CH_STRUCT0_INTRfor the details of bit fields.
0x402808D4 Interrupt set. See DW0_CH_STRUCT0_INTR_SETfor the details of bit fields.
0x402808D8 Interrupt mask. See DW0_CH_STRUCT0_INTR_MASK for the details of bit fields.
0x402808DC Interrupt masked. See DW0_CH_STRUCT0_INTR_MASKED for the details of bit fields.
0x402808E0 Channel control. See DW0_CH_STRUCT0_CH_CTL for the details of bit fields.
0x402808E4 Channel status. See DW0_CH_STRUCT0_CH_STATUS for the details of bit fields.
0x402808E8 Channel current indices. See DW0_CH_STRUCT0_CH_IDX for the details of bit fields.
0x402808EC
Channel current descriptor pointer. See DW0_CH_STRUCT0_CH_CURR_PTR for the details of bit fields.
0x402808F0 Interrupt. See DW0_CH_STRUCT0_INTRfor the details of bit fields.
0x402808F4 Interrupt set. See DW0_CH_STRUCT0_INTR_SETfor the details of bit fields.
0x402808F8 Interrupt mask. See DW0_CH_STRUCT0_INTR_MASK for the details of bit fields.
0x402808FC Interrupt masked. See DW0_CH_STRUCT0_INTR_MASKED for the details of bit fields.
0x40280900 Channel control. See DW0_CH_STRUCT0_CH_CTL for the details of bit fields.
0x40280904 Channel status. See DW0_CH_STRUCT0_CH_STATUS for the details of bit fields.
0x40280908 Channel current indices. See DW0_CH_STRUCT0_CH_IDX for the details of bit fields.
0x4028090C
Channel current descriptor pointer. See DW0_CH_STRUCT0_CH_CURR_PTR for the details of bit fields.
0x40280910 Interrupt. See DW0_CH_STRUCT0_INTRfor the details of bit fields.
0x40280914 Interrupt set. See DW0_CH_STRUCT0_INTR_SETfor the details of bit fields.
0x40280918 Interrupt mask. See DW0_CH_STRUCT0_INTR_MASK for the details of bit fields.
0x4028091C Interrupt masked. See DW0_CH_STRUCT0_INTR_MASKED for the details of bit fields.
0x40280920 Channel control. See DW0_CH_STRUCT0_CH_CTL for the details of bit fields.
0x40280924 Channel status. See DW0_CH_STRUCT0_CH_STATUS for the details of bit fields.
0x40280928 Channel current indices. See DW0_CH_STRUCT0_CH_IDX for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
642
Direct Memory Access (DMA) Registers
Register DW0_CH_STRUCT9_CH_CURR_PTR DW0_CH_STRUCT9_INTR DW0_CH_STRUCT9_INTR_SET DW0_CH_STRUCT9_INTR_MASK DW0_CH_STRUCT9_INTR_MASKED DW0_CH_STRUCT10_CH_CTL DW0_CH_STRUCT10_CH_STATUS DW0_CH_STRUCT10_CH_IDX DW0_CH_STRUCT10_CH_CURR_PTR DW0_CH_STRUCT10_INTR DW0_CH_STRUCT10_INTR_SET DW0_CH_STRUCT10_INTR_MASK DW0_CH_STRUCT10_INTR_MASKED DW0_CH_STRUCT11_CH_CTL DW0_CH_STRUCT11_CH_STATUS DW0_CH_STRUCT11_CH_IDX DW0_CH_STRUCT11_CH_CURR_PTR DW0_CH_STRUCT11_INTR DW0_CH_STRUCT11_INTR_SET DW0_CH_STRUCT11_INTR_MASK DW0_CH_STRUCT11_INTR_MASKED DW0_CH_STRUCT12_CH_CTL DW0_CH_STRUCT12_CH_STATUS DW0_CH_STRUCT12_CH_IDX DW0_CH_STRUCT12_CH_CURR_PTR DW0_CH_STRUCT12_INTR DW0_CH_STRUCT12_INTR_SET DW0_CH_STRUCT12_INTR_MASK DW0_CH_STRUCT12_INTR_MASKED DW0_CH_STRUCT13_CH_CTL DW0_CH_STRUCT13_CH_STATUS
Address 0x4028092C
Description
Channel current descriptor pointer. See DW0_CH_STRUCT0_CH_CURR_PTR for the details of bit fields.
0x40280930 Interrupt. See DW0_CH_STRUCT0_INTRfor the details of bit fields.
0x40280934 Interrupt set. See DW0_CH_STRUCT0_INTR_SETfor the details of bit fields.
0x40280938 Interrupt mask. See DW0_CH_STRUCT0_INTR_MASK for the details of bit fields.
0x4028093C Interrupt masked. See DW0_CH_STRUCT0_INTR_MASKED for the details of bit fields.
0x40280940 Channel control. See DW0_CH_STRUCT0_CH_CTL for the details of bit fields.
0x40280944 Channel status. See DW0_CH_STRUCT0_CH_STATUS for the details of bit fields.
0x40280948 Channel current indices. See DW0_CH_STRUCT0_CH_IDX for the details of bit fields.
0x4028094C
Channel current descriptor pointer. See DW0_CH_STRUCT0_CH_CURR_PTR for the details of bit fields.
0x40280950 Interrupt. See DW0_CH_STRUCT0_INTRfor the details of bit fields.
0x40280954 Interrupt set. See DW0_CH_STRUCT0_INTR_SETfor the details of bit fields.
0x40280958 Interrupt mask. See DW0_CH_STRUCT0_INTR_MASK for the details of bit fields.
0x4028095C Interrupt masked. See DW0_CH_STRUCT0_INTR_MASKED for the details of bit fields.
0x40280960 Channel control. See DW0_CH_STRUCT0_CH_CTL for the details of bit fields.
0x40280964 Channel status. See DW0_CH_STRUCT0_CH_STATUS for the details of bit fields.
0x40280968 Channel current indices. See DW0_CH_STRUCT0_CH_IDX for the details of bit fields.
0x4028096C
Channel current descriptor pointer. See DW0_CH_STRUCT0_CH_CURR_PTR for the details of bit fields.
0x40280970 Interrupt. See DW0_CH_STRUCT0_INTRfor the details of bit fields.
0x40280974 Interrupt set. See DW0_CH_STRUCT0_INTR_SETfor the details of bit fields.
0x40280978 Interrupt mask. See DW0_CH_STRUCT0_INTR_MASK for the details of bit fields.
0x4028097C Interrupt masked. See DW0_CH_STRUCT0_INTR_MASKED for the details of bit fields.
0x40280980 Channel control. See DW0_CH_STRUCT0_CH_CTL for the details of bit fields.
0x40280984 Channel status. See DW0_CH_STRUCT0_CH_STATUS for the details of bit fields.
0x40280988 Channel current indices. See DW0_CH_STRUCT0_CH_IDX for the details of bit fields.
0x4028098C
Channel current descriptor pointer. See DW0_CH_STRUCT0_CH_CURR_PTR for the details of bit fields.
0x40280990 Interrupt. See DW0_CH_STRUCT0_INTRfor the details of bit fields.
0x40280994 Interrupt set. See DW0_CH_STRUCT0_INTR_SETfor the details of bit fields.
0x40280998 Interrupt mask. See DW0_CH_STRUCT0_INTR_MASK for the details of bit fields.
0x4028099C Interrupt masked. See DW0_CH_STRUCT0_INTR_MASKED for the details of bit fields.
0x402809A0 Channel control. See DW0_CH_STRUCT0_CH_CTL for the details of bit fields.
0x402809A4 Channel status. See DW0_CH_STRUCT0_CH_STATUS for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
643
Direct Memory Access (DMA) Registers
Register DW0_CH_STRUCT13_CH_IDX DW0_CH_STRUCT13_CH_CURR_PTR DW0_CH_STRUCT13_INTR DW0_CH_STRUCT13_INTR_SET DW0_CH_STRUCT13_INTR_MASK DW0_CH_STRUCT13_INTR_MASKED DW0_CH_STRUCT14_CH_CTL DW0_CH_STRUCT14_CH_STATUS DW0_CH_STRUCT14_CH_IDX DW0_CH_STRUCT14_CH_CURR_PTR DW0_CH_STRUCT14_INTR DW0_CH_STRUCT14_INTR_SET DW0_CH_STRUCT14_INTR_MASK DW0_CH_STRUCT14_INTR_MASKED DW0_CH_STRUCT15_CH_CTL DW0_CH_STRUCT15_CH_STATUS DW0_CH_STRUCT15_CH_IDX DW0_CH_STRUCT15_CH_CURR_PTR DW0_CH_STRUCT15_INTR DW0_CH_STRUCT15_INTR_SET DW0_CH_STRUCT15_INTR_MASK DW0_CH_STRUCT15_INTR_MASKED DW1_CTL0 DW1_STATUS0 DW1_PENDING0 DW1_STATUS_INTR0 DW1_STATUS_INTR_MASKED0 DW1_ACT_DESCR_CTL0 DW1_ACT_DESCR_SRC0 DW1_ACT_DESCR_DST0 DW1_ACT_DESCR_X_CTL0
Address
Description
0x402809A8 Channel current indices. See DW0_CH_STRUCT0_CH_IDX for the details of bit fields.
0x402809AC
Channel current descriptor pointer. See DW0_CH_STRUCT0_CH_CURR_PTR for the details of bit fields.
0x402809B0 Interrupt. See DW0_CH_STRUCT0_INTRfor the details of bit fields.
0x402809B4 Interrupt set. See DW0_CH_STRUCT0_INTR_SETfor the details of bit fields.
0x402809B8 Interrupt mask. See DW0_CH_STRUCT0_INTR_MASK for the details of bit fields.
0x402809BC Interrupt masked. See DW0_CH_STRUCT0_INTR_MASKED for the details of bit fields.
0x402809C0 Channel control. See DW0_CH_STRUCT0_CH_CTL for the details of bit fields.
0x402809C4 Channel status. See DW0_CH_STRUCT0_CH_STATUS for the details of bit fields.
0x402809C8 Channel current indices. See DW0_CH_STRUCT0_CH_IDX for the details of bit fields.
0x402809CC
Channel current descriptor pointer. See DW0_CH_STRUCT0_CH_CURR_PTR for the details of bit fields.
0x402809D0 Interrupt. See DW0_CH_STRUCT0_INTRfor the details of bit fields.
0x402809D4 Interrupt set. See DW0_CH_STRUCT0_INTR_SETfor the details of bit fields.
0x402809D8 Interrupt mask. See DW0_CH_STRUCT0_INTR_MASK for the details of bit fields.
0x402809DC Interrupt masked. See DW0_CH_STRUCT0_INTR_MASKED for the details of bit fields.
0x402809E0 Channel control. See DW0_CH_STRUCT0_CH_CTL for the details of bit fields.
0x402809E4 Channel status. See DW0_CH_STRUCT0_CH_STATUS for the details of bit fields.
0x402809E8 Channel current indices. See DW0_CH_STRUCT0_CH_IDX for the details of bit fields.
0x402809EC
Channel current descriptor pointer. See DW0_CH_STRUCT0_CH_CURR_PTR for the details of bit fields.
0x402809F0 Interrupt. See DW0_CH_STRUCT0_INTRfor the details of bit fields.
0x402809F4 Interrupt set. See DW0_CH_STRUCT0_INTR_SETfor the details of bit fields.
0x402809F8 Interrupt mask. See DW0_CH_STRUCT0_INTR_MASK for the details of bit fields.
0x402809FC Interrupt masked. See DW0_CH_STRUCT0_INTR_MASKED for the details of bit fields.
0x40281000 Control. See DW0_CTL0 for the details of bit fields.
0x40281004 Status. See DW0_STATUS0 for the details of bit fields.
0x40281008 Pending channels. See DW0_PENDING0 for the details of bit fields.
0x40281010 System interrupt control. See DW0_STATUS_INTR0 for the details of bit fields.
0x40281014 Status of interrupts masked. See DW0_STATUS_INTR_MASKED0 for the details of bit fields.
0x40281020 Active descriptor control. See DW0_ACT_DESCR_CTL0 for the details of bit fields.
0x40281024 Active descriptor source. See DW0_ACT_DESCR_SRC0 for the details of bit fields.
0x40281028 Active descriptor destination. See DW0_ACT_DESCR_DST0 for the details of bit fields.
0x40281030 Active descriptor X loop control. See DW0_ACT_DESCR_X_CTL0 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
644
Direct Memory Access (DMA) Registers
Register DW1_ACT_DESCR_Y_CTL0 DW1_ACT_DESCR_NEXT_PTR0 DW1_ACT_SRC0 DW1_ACT_DST0 DW1_CH_STRUCT0_CH_CTL DW1_CH_STRUCT0_CH_STATUS DW1_CH_STRUCT0_CH_IDX DW1_CH_STRUCT0_CH_CURR_PTR DW1_CH_STRUCT0_INTR DW1_CH_STRUCT0_INTR_SET DW1_CH_STRUCT0_INTR_MASK DW1_CH_STRUCT0_INTR_MASKED DW1_CH_STRUCT1_CH_CTL DW1_CH_STRUCT1_CH_STATUS DW1_CH_STRUCT1_CH_IDX DW1_CH_STRUCT1_CH_CURR_PTR DW1_CH_STRUCT1_INTR DW1_CH_STRUCT1_INTR_SET DW1_CH_STRUCT1_INTR_MASK DW1_CH_STRUCT1_INTR_MASKED DW1_CH_STRUCT2_CH_CTL DW1_CH_STRUCT2_CH_STATUS DW1_CH_STRUCT2_CH_IDX DW1_CH_STRUCT2_CH_CURR_PTR DW1_CH_STRUCT2_INTR DW1_CH_STRUCT2_INTR_SET DW1_CH_STRUCT2_INTR_MASK DW1_CH_STRUCT2_INTR_MASKED DW1_CH_STRUCT3_CH_CTL DW1_CH_STRUCT3_CH_STATUS DW1_CH_STRUCT3_CH_IDX
Address
Description
0x40281034 Active descriptor Y loop control. See DW0_ACT_DESCR_Y_CTL0 for the details of bit fields.
0x40281038 Active descriptor next pointer. See DW0_ACT_DESCR_NEXT_PTR0 for the details of bit fields.
0x40281040 Active source. See DW0_ACT_SRC0 for the details of bit fields.
0x40281044 Active destination. See DW0_ACT_DST0 for the details of bit fields.
0x40281800 Channel control. See DW0_CH_STRUCT0_CH_CTL for the details of bit fields.
0x40281804 Channel status. See DW0_CH_STRUCT0_CH_STATUS for the details of bit fields.
0x40281808 Channel current indices. See DW0_CH_STRUCT0_CH_IDX for the details of bit fields.
0x4028180C
Channel current descriptor pointer. See DW0_CH_STRUCT0_CH_CURR_PTR for the details of bit fields.
0x40281810 Interrupt. See DW0_CH_STRUCT0_INTRfor the details of bit fields.
0x40281814 Interrupt set. See DW0_CH_STRUCT0_INTR_SETfor the details of bit fields.
0x40281818 Interrupt mask. See DW0_CH_STRUCT0_INTR_MASKfor the details of bit fields.
0x4028181C Interrupt masked. See DW0_CH_STRUCT0_INTR_MASKEDfor the details of bit fields.
0x40281820 Channel control. See DW0_CH_STRUCT0_CH_CTL for the details of bit fields.
0x40281824 Channel status. See DW0_CH_STRUCT0_CH_STATUS for the details of bit fields.
0x40281828 Channel current indices. See DW0_CH_STRUCT0_CH_IDX for the details of bit fields.
0x4028182C
Channel current descriptor pointer. See DW0_CH_STRUCT0_CH_CURR_PTR for the details of bit fields.
0x40281830 Interrupt. See DW0_CH_STRUCT0_INTRfor the details of bit fields.
0x40281834 Interrupt set. See DW0_CH_STRUCT0_INTR_SETfor the details of bit fields.
0x40281838 Interrupt mask. See DW0_CH_STRUCT0_INTR_MASK for the details of bit fields.
0x4028183C Interrupt masked. See DW0_CH_STRUCT0_INTR_MASKED for the details of bit fields.
0x40281840 Channel control. See DW0_CH_STRUCT0_CH_CTL for the details of bit fields.
0x40281844 Channel status. See DW0_CH_STRUCT0_CH_STATUS for the details of bit fields.
0x40281848 Channel current indices. See DW0_CH_STRUCT0_CH_IDX for the details of bit fields.
0x4028184C
Channel current descriptor pointer. See DW0_CH_STRUCT0_CH_CURR_PTR for the details of bit fields.
0x40281850 Interrupt. See DW0_CH_STRUCT0_INTRfor the details of bit fields.
0x40281854 Interrupt set. See DW0_CH_STRUCT0_INTR_SETfor the details of bit fields.
0x40281858 Interrupt mask. See DW0_CH_STRUCT0_INTR_MASK for the details of bit fields.
0x4028185C Interrupt masked. See DW0_CH_STRUCT0_INTR_MASKED for the details of bit fields.
0x40281860 Channel control. See DW0_CH_STRUCT0_CH_CTL for the details of bit fields.
0x40281864 Channel status. See DW0_CH_STRUCT0_CH_STATUS for the details of bit fields.
0x40281868 Channel current indices. See DW0_CH_STRUCT0_CH_IDX for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
645
Direct Memory Access (DMA) Registers
Register DW1_CH_STRUCT3_CH_CURR_PTR DW1_CH_STRUCT3_INTR DW1_CH_STRUCT3_INTR_SET DW1_CH_STRUCT3_INTR_MASK DW1_CH_STRUCT3_INTR_MASKED DW1_CH_STRUCT4_CH_CTL DW1_CH_STRUCT4_CH_STATUS DW1_CH_STRUCT4_CH_IDX DW1_CH_STRUCT4_CH_CURR_PTR DW1_CH_STRUCT4_INTR DW1_CH_STRUCT4_INTR_SET DW1_CH_STRUCT4_INTR_MASK DW1_CH_STRUCT4_INTR_MASKED DW1_CH_STRUCT5_CH_CTL DW1_CH_STRUCT5_CH_STATUS DW1_CH_STRUCT5_CH_IDX DW1_CH_STRUCT5_CH_CURR_PTR DW1_CH_STRUCT5_INTR DW1_CH_STRUCT5_INTR_SET DW1_CH_STRUCT5_INTR_MASK DW1_CH_STRUCT5_INTR_MASKED DW1_CH_STRUCT6_CH_CTL DW1_CH_STRUCT6_CH_STATUS DW1_CH_STRUCT6_CH_IDX DW1_CH_STRUCT6_CH_CURR_PTR DW1_CH_STRUCT6_INTR DW1_CH_STRUCT6_INTR_SET DW1_CH_STRUCT6_INTR_MASK DW1_CH_STRUCT6_INTR_MASKED DW1_CH_STRUCT7_CH_CTL DW1_CH_STRUCT7_CH_STATUS
Address 0x4028186C
Description
Channel current descriptor pointer. See DW0_CH_STRUCT0_CH_CURR_PTR for the details of bit fields.
0x40281870 Interrupt. See DW0_CH_STRUCT0_INTRfor the details of bit fields.
0x40281874 Interrupt set. See DW0_CH_STRUCT0_INTR_SETfor the details of bit fields.
0x40281878 Interrupt mask. See DW0_CH_STRUCT0_INTR_MASK for the details of bit fields.
0x4028187C Interrupt masked. See DW0_CH_STRUCT0_INTR_MASKED for the details of bit fields.
0x40281880 Channel control. See DW0_CH_STRUCT0_CH_CTL for the details of bit fields.
0x40281884 Channel status. See DW0_CH_STRUCT0_CH_STATUS for the details of bit fields.
0x40281888 Channel current indices. See DW0_CH_STRUCT0_CH_IDX for the details of bit fields.
0x4028188C
Channel current descriptor pointer. See DW0_CH_STRUCT0_CH_CURR_PTR for the details of bit fields.
0x40281890 Interrupt. See DW0_CH_STRUCT0_INTRfor the details of bit fields.
0x40281894 Interrupt set. See DW0_CH_STRUCT0_INTR_SETfor the details of bit fields.
0x40281898 Interrupt mask. See DW0_CH_STRUCT0_INTR_MASK for the details of bit fields.
0x4028189C Interrupt masked. See DW0_CH_STRUCT0_INTR_MASKED for the details of bit fields.
0x402818A0 Channel control. See DW0_CH_STRUCT0_CH_CTL for the details of bit fields.
0x402818A4 Channel status. See DW0_CH_STRUCT0_CH_STATUS for the details of bit fields.
0x402818A8 Channel current indices. See DW0_CH_STRUCT0_CH_IDX for the details of bit fields.
0x402818AC
Channel current descriptor pointer. See DW0_CH_STRUCT0_CH_CURR_PTR for the details of bit fields.
0x402818B0 Interrupt. See DW0_CH_STRUCT0_INTRfor the details of bit fields.
0x402818B4 Interrupt set. See DW0_CH_STRUCT0_INTR_SETfor the details of bit fields.
0x402818B8 Interrupt mask. See DW0_CH_STRUCT0_INTR_MASK for the details of bit fields.
0x402818BC Interrupt masked. See DW0_CH_STRUCT0_INTR_MASKED for the details of bit fields.
0x402818C0 Channel control. See DW0_CH_STRUCT0_CH_CTL for the details of bit fields.
0x402818C4 Channel status. See DW0_CH_STRUCT0_CH_STATUS for the details of bit fields.
0x402818C8 Channel current indices. See DW0_CH_STRUCT0_CH_IDX for the details of bit fields.
0x402818CC
Channel current descriptor pointer. See DW0_CH_STRUCT0_CH_CURR_PTR for the details of bit fields.
0x402818D0 Interrupt. See DW0_CH_STRUCT0_INTRfor the details of bit fields.
0x402818D4 Interrupt set. See DW0_CH_STRUCT0_INTR_SETfor the details of bit fields.
0x402818D8 Interrupt mask. See DW0_CH_STRUCT0_INTR_MASK for the details of bit fields.
0x402818DC Interrupt masked. See DW0_CH_STRUCT0_INTR_MASKED for the details of bit fields.
0x402818E0 Channel control. See DW0_CH_STRUCT0_CH_CTL for the details of bit fields.
0x402818E4 Channel status. See DW0_CH_STRUCT0_CH_STATUS for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
646
Direct Memory Access (DMA) Registers
Register DW1_CH_STRUCT7_CH_IDX DW1_CH_STRUCT7_CH_CURR_PTR DW1_CH_STRUCT7_INTR DW1_CH_STRUCT7_INTR_SET DW1_CH_STRUCT7_INTR_MASK DW1_CH_STRUCT7_INTR_MASKED DW1_CH_STRUCT8_CH_CTL DW1_CH_STRUCT8_CH_STATUS DW1_CH_STRUCT8_CH_IDX DW1_CH_STRUCT8_CH_CURR_PTR DW1_CH_STRUCT8_INTR DW1_CH_STRUCT8_INTR_SET DW1_CH_STRUCT8_INTR_MASK DW1_CH_STRUCT8_INTR_MASKED DW1_CH_STRUCT9_CH_CTL DW1_CH_STRUCT9_CH_STATUS DW1_CH_STRUCT9_CH_IDX DW1_CH_STRUCT9_CH_CURR_PTR DW1_CH_STRUCT9_INTR DW1_CH_STRUCT9_INTR_SET DW1_CH_STRUCT9_INTR_MASK DW1_CH_STRUCT9_INTR_MASKED DW1_CH_STRUCT10_CH_CTL DW1_CH_STRUCT10_CH_STATUS DW1_CH_STRUCT10_CH_IDX DW1_CH_STRUCT10_CH_CURR_PTR DW1_CH_STRUCT10_INTR DW1_CH_STRUCT10_INTR_SET DW1_CH_STRUCT10_INTR_MASK DW1_CH_STRUCT10_INTR_MASKED DW1_CH_STRUCT11_CH_CTL
Address
Description
0x402818E8 Channel current indices. See DW0_CH_STRUCT0_CH_IDX for the details of bit fields.
0x402818EC
Channel current descriptor pointer. See DW0_CH_STRUCT0_CH_CURR_PTR for the details of bit fields.
0x402818F0 Interrupt. See DW0_CH_STRUCT0_INTRfor the details of bit fields.
0x402818F4 Interrupt set. See DW0_CH_STRUCT0_INTR_SETfor the details of bit fields.
0x402818F8 Interrupt mask. See DW0_CH_STRUCT0_INTR_MASK for the details of bit fields.
0x402818FC Interrupt masked. See DW0_CH_STRUCT0_INTR_MASKED for the details of bit fields.
0x40281900 Channel control. See DW0_CH_STRUCT0_CH_CTL for the details of bit fields.
0x40281904 Channel status. See DW0_CH_STRUCT0_CH_STATUS for the details of bit fields.
0x40281908 Channel current indices. See DW0_CH_STRUCT0_CH_IDX for the details of bit fields.
0x4028190C
Channel current descriptor pointer. See DW0_CH_STRUCT0_CH_CURR_PTR for the details of bit fields.
0x40281910 Interrupt. See DW0_CH_STRUCT0_INTRfor the details of bit fields.
0x40281914 Interrupt set. See DW0_CH_STRUCT0_INTR_SETfor the details of bit fields.
0x40281918 Interrupt mask. See DW0_CH_STRUCT0_INTR_MASK for the details of bit fields.
0x4028191C Interrupt masked. See DW0_CH_STRUCT0_INTR_MASKED for the details of bit fields.
0x40281920 Channel control. See DW0_CH_STRUCT0_CH_CTL for the details of bit fields.
0x40281924 Channel status. See DW0_CH_STRUCT0_CH_STATUS for the details of bit fields.
0x40281928 Channel current indices. See DW0_CH_STRUCT0_CH_IDX for the details of bit fields.
0x4028192C
Channel current descriptor pointer. See DW0_CH_STRUCT0_CH_CURR_PTR for the details of bit fields.
0x40281930 Interrupt. See DW0_CH_STRUCT0_INTRfor the details of bit fields.
0x40281934 Interrupt set. See DW0_CH_STRUCT0_INTR_SETfor the details of bit fields.
0x40281938 Interrupt mask. See DW0_CH_STRUCT0_INTR_MASK for the details of bit fields.
0x4028193C Interrupt masked. See DW0_CH_STRUCT0_INTR_MASKED for the details of bit fields.
0x40281940 Channel control. See DW0_CH_STRUCT0_CH_CTL for the details of bit fields.
0x40281944 Channel status. See DW0_CH_STRUCT0_CH_STATUS for the details of bit fields.
0x40281948 Channel current indices. See DW0_CH_STRUCT0_CH_IDX for the details of bit fields.
0x4028194C
Channel current descriptor pointer. See DW0_CH_STRUCT0_CH_CURR_PTR for the details of bit fields.
0x40281950 Interrupt. See DW0_CH_STRUCT0_INTRfor the details of bit fields.
0x40281954 Interrupt set. See DW0_CH_STRUCT0_INTR_SETfor the details of bit fields.
0x40281958 Interrupt mask. See DW0_CH_STRUCT0_INTR_MASK for the details of bit fields.
0x4028195C Interrupt masked. See DW0_CH_STRUCT0_INTR_MASKED for the details of bit fields.
0x40281960 Channel control. See DW0_CH_STRUCT0_CH_CTL for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
647
Direct Memory Access (DMA) Registers
Register DW1_CH_STRUCT11_CH_STATUS DW1_CH_STRUCT11_CH_IDX DW1_CH_STRUCT11_CH_CURR_PTR DW1_CH_STRUCT11_INTR DW1_CH_STRUCT11_INTR_SET DW1_CH_STRUCT11_INTR_MASK DW1_CH_STRUCT11_INTR_MASKED DW1_CH_STRUCT12_CH_CTL DW1_CH_STRUCT12_CH_STATUS DW1_CH_STRUCT12_CH_IDX DW1_CH_STRUCT12_CH_CURR_PTR DW1_CH_STRUCT12_INTR DW1_CH_STRUCT12_INTR_SET DW1_CH_STRUCT12_INTR_MASK DW1_CH_STRUCT12_INTR_MASKED DW1_CH_STRUCT13_CH_CTL DW1_CH_STRUCT13_CH_STATUS DW1_CH_STRUCT13_CH_IDX DW1_CH_STRUCT13_CH_CURR_PTR DW1_CH_STRUCT13_INTR DW1_CH_STRUCT13_INTR_SET DW1_CH_STRUCT13_INTR_MASK DW1_CH_STRUCT13_INTR_MASKED DW1_CH_STRUCT14_CH_CTL DW1_CH_STRUCT14_CH_STATUS DW1_CH_STRUCT14_CH_IDX DW1_CH_STRUCT14_CH_CURR_PTR DW1_CH_STRUCT14_INTR DW1_CH_STRUCT14_INTR_SET DW1_CH_STRUCT14_INTR_MASK DW1_CH_STRUCT14_INTR_MASKED
Address
Description
0x40281964 Channel status. See DW0_CH_STRUCT0_CH_STATUS for the details of bit fields.
0x40281968 Channel current indices. See DW0_CH_STRUCT0_CH_IDX for the details of bit fields.
0x4028196C
Channel current descriptor pointer. See DW0_CH_STRUCT0_CH_CURR_PTR for the details of bit fields.
0x40281970 Interrupt. See DW0_CH_STRUCT0_INTRfor the details of bit fields.
0x40281974 Interrupt set. See DW0_CH_STRUCT0_INTR_SETfor the details of bit fields.
0x40281978 Interrupt mask. See DW0_CH_STRUCT0_INTR_MASK for the details of bit fields.
0x4028197C Interrupt masked. See DW0_CH_STRUCT0_INTR_MASKED for the details of bit fields.
0x40281980 Channel control. See DW0_CH_STRUCT0_CH_CTL for the details of bit fields.
0x40281984 Channel status. See DW0_CH_STRUCT0_CH_STATUS for the details of bit fields.
0x40281988 Channel current indices. See DW0_CH_STRUCT0_CH_IDX for the details of bit fields.
0x4028198C
Channel current descriptor pointer. See DW0_CH_STRUCT0_CH_CURR_PTR for the details of bit fields.
0x40281990 Interrupt. See DW0_CH_STRUCT0_INTRfor the details of bit fields.
0x40281994 Interrupt set. See DW0_CH_STRUCT0_INTR_SETfor the details of bit fields.
0x40281998 Interrupt mask. See DW0_CH_STRUCT0_INTR_MASK for the details of bit fields.
0x4028199C Interrupt masked. See DW0_CH_STRUCT0_INTR_MASKED for the details of bit fields.
0x402819A0 Channel control. See DW0_CH_STRUCT0_CH_CTL for the details of bit fields.
0x402819A4 Channel status. See DW0_CH_STRUCT0_CH_STATUS for the details of bit fields.
0x402819A8 Channel current indices. See DW0_CH_STRUCT0_CH_IDX for the details of bit fields.
0x402819AC
Channel current descriptor pointer. See DW0_CH_STRUCT0_CH_CURR_PTR for the details of bit fields.
0x402819B0 Interrupt. See DW0_CH_STRUCT0_INTRfor the details of bit fields.
0x402819B4 Interrupt set. See DW0_CH_STRUCT0_INTR_SETfor the details of bit fields.
0x402819B8 Interrupt mask. See DW0_CH_STRUCT0_INTR_MASK for the details of bit fields.
0x402819BC Interrupt masked. See DW0_CH_STRUCT0_INTR_MASKED for the details of bit fields.
0x402819C0 Channel control. See DW0_CH_STRUCT0_CH_CTL for the details of bit fields.
0x402819C4 Channel status. See DW0_CH_STRUCT0_CH_STATUS for the details of bit fields.
0x402819C8 Channel current indices. See DW0_CH_STRUCT0_CH_IDX for the details of bit fields.
0x402819CC
Channel current descriptor pointer. See DW0_CH_STRUCT0_CH_CURR_PTR for the details of bit fields.
0x402819D0 Interrupt. See DW0_CH_STRUCT0_INTRfor the details of bit fields.
0x402819D4 Interrupt set. See DW0_CH_STRUCT0_INTR_SETfor the details of bit fields.
0x402819D8 Interrupt mask. See DW0_CH_STRUCT0_INTR_MASK for the details of bit fields.
0x402819DC Interrupt masked. See DW0_CH_STRUCT0_INTR_MASKED for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
648
Direct Memory Access (DMA) Registers
Register DW1_CH_STRUCT15_CH_CTL DW1_CH_STRUCT15_CH_STATUS DW1_CH_STRUCT15_CH_IDX DW1_CH_STRUCT15_CH_CURR_PTR DW1_CH_STRUCT15_INTR DW1_CH_STRUCT15_INTR_SET DW1_CH_STRUCT15_INTR_MASK DW1_CH_STRUCT15_INTR_MASKED
Address
Description
0x402819E0 Channel control. See DW0_CH_STRUCT0_CH_CTL for the details of bit fields.
0x402819E4 Channel status. See DW0_CH_STRUCT0_CH_STATUS for the details of bit fields.
0x402819E8 Channel current indices. See DW0_CH_STRUCT0_CH_IDX for the details of bit fields.
0x402819EC
Channel current descriptor pointer. See DW0_CH_STRUCT0_CH_CURR_PTR for the details of bit fields.
0x402819F0 Interrupt. See DW0_CH_STRUCT0_INTRfor the details of bit fields.
0x402819F4 Interrupt set. See DW0_CH_STRUCT0_INTR_SETfor the details of bit fields.
0x402819F8 Interrupt mask. See DW0_CH_STRUCT0_INTR_MASK for the details of bit fields.
0x402819FC Interrupt masked. See DW0_CH_STRUCT0_INTR_MASKED for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
649
DW0_CTL0
12.1.1 DW0_CTL0
Address = 0x40280000 Control Address: 0x40280000 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
None
HW Access
R
None
Name
ENABLED
None
Bits
Name
31
ENABLED
Description
IP enable: '0': Disabled. Disabling the IP activates the IP's Active logic reset: Active logic and non-retention MMIO registers are reset (retention MMIO registers are not affected). '1': Enabled. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
650
DW0_STATUS0
12.1.2 DW0_STATUS0
Address = 0x40280004 Status Address: 0x40280004 Retention: Not Retained
Bits
7
6
5
4
SW Access
R
HW Access
RW
Name
PC [7:4]
Bits
15
14
13
12
SW Access
None
HW Access
None
Name
None [15:13]
Bits SW Access HW Access
Name
23 None None
None
22
21
20
R
W
STATE [22:20]
Bits
31
30
29
28
SW Access
R
HW Access
W
Name
ACTIVE
3
2
None
R
None
RW
None
B
11
10
R
W
CH_IDX [12:8]
19 None None
None
18
R
W
PREEMPTABLE
27
26
None
None
None [30:24]
1
0
R
R
RW
RW
NS
P
9
8
17
16
R
W
PRIO [17:16]
25
24
Bits
Name
31
ACTIVE
22 : 20
STATE
18 17 : 16
PREEMPTABLE PRIO
Description
Active channel present: 0: No. 1: Yes. Default Value: 0
State of the DW controller. 0: Default/inactive state. 1: Loading descriptor. 2: Loading data element from source location. 3: Storing data element to destination location. 4: Update of active control information (e.g. source and destination addresses). 5: Wait for trigger de-activation. Default Value: 0
Active channel preemptable. Default Value: Undefined
Active channel priority. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
651
12.1.2
12 : 8 7 : 4 2
1
0
DW0_STATUS0 (continued)
CH_IDX PC B
NS
P
Active channel index. Default Value: Undefined
Active channel protection context. Default Value: Undefined
Active channel, non-bufferable/bufferable access control: '0': non-bufferable '1': bufferable. Default Value: Undefined
Active channel, secure/non-secure access control: '0': secure. '1': non-secure. Default Value: Undefined
Active channel, user/privileged access control: '0': user mode. '1': privileged mode. Default Value: Undefined
DW0_STATUS0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
652
DW0_PENDING0
12.1.3 DW0_PENDING0
Address = 0x40280008 Pending channels Address: 0x40280008 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
CH_PENDING [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
CH_PENDING [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 0
Name CH_PENDING
Description
Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s)). Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
653
DW0_STATUS_INTR0
12.1.4 DW0_STATUS_INTR0
Address = 0x40280010 System interrupt control Address: 0x40280010 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
CH [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
CH [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 0
Name CH
Description
Reflects the INTR.CH bit fields of all channels. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
654
DW0_STATUS_INTR_MASKED0
12.1.5 DW0_STATUS_INTR_MASKED0
Address = 0x40280014 Status of interrupts masked Address: 0x40280014 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
CH [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
CH [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 0
Name CH
Description
Reflects the INTR_MASKED.CH bit fields of all channels. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
655
DW0_ACT_DESCR_CTL0
12.1.6 DW0_ACT_DESCR_CTL0
Address = 0x40280020 Active descriptor control Address: 0x40280020 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
DATA [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
DATA [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
W
Name
DATA [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
W
Name
DATA [31:24]
Bits 31 : 0
Name DATA
Description
Copy of DESCR_CTL of the currently active descriptor. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
656
DW0_ACT_DESCR_SRC0
12.1.7 DW0_ACT_DESCR_SRC0
Address = 0x40280024 Active descriptor source Address: 0x40280024 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
DATA [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
DATA [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
W
Name
DATA [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
W
Name
DATA [31:24]
Bits 31 : 0
Name DATA
Description
Copy of DESCR_SRC of the currently active descriptor. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
657
DW0_ACT_DESCR_DST0
12.1.8 DW0_ACT_DESCR_DST0
Address = 0x40280028 Active descriptor destination Address: 0x40280028 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
DATA [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
DATA [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
W
Name
DATA [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
W
Name
DATA [31:24]
Bits 31 : 0
Name DATA
Description
Copy of DESCR_DST of the currently active descriptor. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
658
DW0_ACT_DESCR_X_CTL0
12.1.9 DW0_ACT_DESCR_X_CTL0
Address = 0x40280030 Active descriptor X loop control Address: 0x40280030 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
DATA [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
DATA [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
W
Name
DATA [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
W
Name
DATA [31:24]
Bits 31 : 0
Name DATA
Description
Copy of DESCR_X_CTL of the currently active descriptor. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
659
DW0_ACT_DESCR_Y_CTL0
12.1.10 DW0_ACT_DESCR_Y_CTL0
Address = 0x40280034 Active descriptor Y loop control Address: 0x40280034 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
DATA [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
DATA [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
W
Name
DATA [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
W
Name
DATA [31:24]
Bits 31 : 0
Name DATA
Description
Copy of DESCR_Y_CTL of the currently active descriptor. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
660
DW0_ACT_DESCR_NEXT_PTR0
12.1.11 DW0_ACT_DESCR_NEXT_PTR0
Address = 0x40280038 Active descriptor next pointer Address: 0x40280038 Retention: Not Retained
Bits
7
6
5
4
3
2
SW Access
R
HW Access
W
Name
ADDR [7:2]
Bits
15
14
13
12
11
10
SW Access
R
HW Access
W
Name
ADDR [15:8]
Bits
23
22
21
20
19
18
SW Access
R
HW Access
W
Name
ADDR [23:16]
Bits
31
30
29
28
27
26
SW Access
R
HW Access
W
Name
ADDR [31:24]
Bits 31 : 2
Name ADDR
Description
Copy of DESCR_NEXT_PTR of the currently active descriptor. Default Value: Undefined
1
0
None
None
None [1:0]
9
8
17
16
25
24
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
661
DW0_ACT_SRC0
12.1.12 DW0_ACT_SRC0
Address = 0x40280040 Active source Address: 0x40280040 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
SRC_ADDR [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
SRC_ADDR [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
W
Name
SRC_ADDR [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
W
Name
SRC_ADDR [31:24]
Bits 31 : 0
Name SRC_ADDR
Description
Current address of source location. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
662
DW0_ACT_DST0
12.1.13 DW0_ACT_DST0
Address = 0x40280044 Active destination Address: 0x40280044 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
DST_ADDR [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
DST_ADDR [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
W
Name
DST_ADDR [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
W
Name
DST_ADDR [31:24]
Bits 31 : 0
Name DST_ADDR
Description
Current address of destination location. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
663
DW0_CH_STRUCT0_CH_CTL
12.1.14 DW0_CH_STRUCT0_CH_CTL
Address = 0x40280800 Channel control Address: 0x40280800 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
RW
R
PC [7:4]
4
3
2
None
RW
None
R
None
B
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
SW Access
HW Access
Name
22
21
20
None
None
None [23:19]
19
18
RW
R
PREEMPTABLE
Bits
31
30
29
28
27
26
SW Access
RW
None
HW Access
RW1C
None
Name
ENABLED
None [30:24]
1
0
RW
RW
R
R
NS
P
9
8
17
16
RW
R
PRIO [17:16]
25
24
Bits
Name
31
ENABLED
18
PREEMPTABLE
Description
Channel enable: 0: Disabled. The channels trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pending channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed). 1: Enabled. SW sets this field to 1 to enable a specific channel. HW sets this field to 0 on an error interrupt cause (the specific error is specified by CH_STATUS.INTR_CAUSE). Default Value: 0
Specifies if the channel is preemptable. '0': Not preemptable. 1: Preemptable. This field allows higher priority pending channels (from a higher priority group; i.e. an active channel can NOT be preempted by a pending channel in the same priority group) to preempt the active channel in between "single transfers" (a 1D transfer consists out of X_COUNT single transfers; a 2D transfer consists out of X_COUNT*Y_COUNT single transfers). Preemption will NOT affect the pending status of channel. As a result, after completion of a higher priority activated channel, the current channel may be reactivated. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
664
DW0_CH_STRUCT0_CH_CTL
12.1.14 DW0_CH_STRUCT0_CH_CTL (continued)
17 : 16
PRIO
7 : 4
PC
2
B
1
NS
0
P
Channel priority: 0: highest priority. "1" "2" 3: lowest priority. Channels with the same priority constitute a priority group. Priority decoding determines the highest priority pending channel. This channel is determined as follows. First, the highest priority group with pending channels is identified. Second, within this priority group, round robin arbitration is applied. Round robin arbitration (within a priority group) gives the highest priority to the lower channel indices (within the priority group). Default Value: 0
Protection context. This field is set with the protection context of the transaction that writes this register; i.e. the 'write data' is ignored and instead the context is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel uses the PC field for the protection context. Default Value: 0
Non-bufferable/bufferable access control: '0': non-bufferable. '1': bufferable. This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data. All transactions for this channel uses the B field for the non-bufferable/bufferable access control ("hprot[2]"). Default Value: 0
Secure/on-secure access control: '0': secure. '1': non-secure. This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the NS field for the secure/non-secure access control ("hprot[4]"). Default Value: 1
User/privileged access control: '0': user mode. '1': privileged mode. This field is set with the user/privileged access control of the transaction that writes this register; i.e. the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R). All transactions for this channel use the P field for the user/privileged access control ("hprot[1]"). Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
665
DW0_CH_STRUCT0_CH_STATUS
12.1.15 DW0_CH_STRUCT0_CH_STATUS
Address = 0x40280804 Channel status Address: 0x40280804 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
R
HW Access
None
W
Name
None [7:4]
INTR_CAUSE [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 3 : 0
Name INTR_CAUSE
Description
Specifies the source of the interrupt cause: "0": NO_INTR "1": COMPLETION "2": SRC_BUS_ERROR "3": DST_BUS_ERROR "4": SRC_MISAL "5": DST_MISAL "6": CURR_PTR_NULL "7": ACTIVE_CH_DISABLED "8": DESCR_BUS_ERROR "9"-"15": Not used. For error related interrupt causes (INTR_CAUSE is "2", "3", ..., "8"), the channel is disabled (HW sets CH_CTL.ENABLED to '0'). Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
666
DW0_CH_STRUCT0_CH_IDX
12.1.16 DW0_CH_STRUCT0_CH_IDX
Address = 0x40280808 Channel current indices Address: 0x40280808 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
X_IDX [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
RW
Name
Y_IDX [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 8
Name Y_IDX
7 : 0
X_IDX
Description
Specifies the Y loop index, with X_COUNT taken from the current descriptor. Note: HW sets this field to "0" when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to "0" when it updates CH_CURR_PTR. Default Value: Undefined
Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor. Note: HW sets this field to "0" when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: SW should set this field to "0" when it updates CH_CURR_PTR. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
667
DW0_CH_STRUCT0_CH_CURR_PTR
12.1.17 DW0_CH_STRUCT0_CH_CURR_PTR
Address = 0x4028080C Channel current descriptor pointer Address: 0x4028080C Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
None
HW Access
RW
None
Name
ADDR [7:2]
None [1:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
RW
Name
ADDR [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
RW
Name
ADDR [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
RW
Name
ADDR [31:24]
Bits 31 : 2
Name ADDR
Description
Address of current descriptor. When this field is "0", there is no valid descriptor. Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor. Note: Typically, when SW updates the current descriptor pointer CH_CURR_PTR, it also sets CH_IDX.X_IDX and CH_IDX.Y_IDX to "0". Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
668
DW0_CH_STRUCT0_INTR
12.1.18 DW0_CH_STRUCT0_INTR
Address = 0x40280810 Interrupt Address: 0x40280810 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW1C
HW Access
None
RW1S
Name
None [7:1]
CH
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
CH
Description
Set to '1', when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1', to clear bit. Write INTR_SET.CH field with '1', to set bit. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
669
DW0_CH_STRUCT0_INTR_SET
12.1.19 DW0_CH_STRUCT0_INTR_SET
Address = 0x40280814 Interrupt set Address: 0x40280814 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW1S
HW Access
None
A
Name
None [7:1]
CH
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
CH
Description
Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect). Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
670
DW0_CH_STRUCT0_INTR_MASK
12.1.20 DW0_CH_STRUCT0_INTR_MASK
Address = 0x40280818 Interrupt mask Address: 0x40280818 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:1]
CH
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
CH
Description
Mask for corresponding field in INTR register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
671
DW0_CH_STRUCT0_INTR_MASKED
12.1.21 DW0_CH_STRUCT0_INTR_MASKED
Address = 0x4028081C Interrupt masked Address: 0x4028081C Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
R
HW Access
None
W
Name
None [7:1]
CH
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
CH
Description
Logical and of corresponding INTR and INTR_MASK fields. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
672
13 eFuse Registers
This section discusses the eFuse registers. It lists all the registers in mapping tables, in address order.
13.1 Register Details
Register
Address
EFUSE_DATA_DEAD_ACCESS_RESTRICT0 0x402C0827
EFUSE_DATA_DEAD_ACCESS_RESTRICT1 0x402C0828
EFUSE_DATA_SECURE_ACCESS_RESTRICT0 0x402C0829
EFUSE_DATA_SECURE_ACCESS_RESTRICT1 0x402C082A
EFUSE_DATA_LIFECYCLE_STAGE
0x402C082B
EFUSE_DATA_CUSTOMER_DATA0
0x402C0840
EFUSE_DATA_CUSTOMER_DATA1
0x402C0841
EFUSE_DATA_CUSTOMER_DATA2
0x402C0842
EFUSE_DATA_CUSTOMER_DATA3
0x402C0843
EFUSE_DATA_CUSTOMER_DATA4
0x402C0844
EFUSE_DATA_CUSTOMER_DATA5
0x402C0845
EFUSE_DATA_CUSTOMER_DATA6
0x402C0846
EFUSE_DATA_CUSTOMER_DATA7
0x402C0847
EFUSE_DATA_CUSTOMER_DATA8
0x402C0848
EFUSE_DATA_CUSTOMER_DATA9
0x402C0849
EFUSE_DATA_CUSTOMER_DATA10
0x402C084A
EFUSE_DATA_CUSTOMER_DATA11
0x402C084B
EFUSE_DATA_CUSTOMER_DATA12
0x402C084C
EFUSE_DATA_CUSTOMER_DATA13
0x402C084D
EFUSE_DATA_CUSTOMER_DATA14
0x402C084E
EFUSE_DATA_CUSTOMER_DATA15
0x402C084F
EFUSE_DATA_CUSTOMER_DATA16
0x402C0850
EFUSE_DATA_CUSTOMER_DATA17
0x402C0851
EFUSE_DATA_CUSTOMER_DATA18
0x402C0852
EFUSE_DATA_CUSTOMER_DATA19
0x402C0853
EFUSE_DATA_CUSTOMER_DATA20
0x402C0854
EFUSE_DATA_CUSTOMER_DATA21
0x402C0855
Description DEAD access restrictions DEAD access restrictions SECURE access restrictions SECURE access restrictions NORMAL, SECURE_WITH_DEBUG, and SECURE fuse bits Customer data Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
673
eFuse Registers
Register EFUSE_DATA_CUSTOMER_DATA22 EFUSE_DATA_CUSTOMER_DATA23 EFUSE_DATA_CUSTOMER_DATA24 EFUSE_DATA_CUSTOMER_DATA25 EFUSE_DATA_CUSTOMER_DATA26 EFUSE_DATA_CUSTOMER_DATA27 EFUSE_DATA_CUSTOMER_DATA28 EFUSE_DATA_CUSTOMER_DATA29 EFUSE_DATA_CUSTOMER_DATA30 EFUSE_DATA_CUSTOMER_DATA31 EFUSE_DATA_CUSTOMER_DATA32 EFUSE_DATA_CUSTOMER_DATA33 EFUSE_DATA_CUSTOMER_DATA34 EFUSE_DATA_CUSTOMER_DATA35 EFUSE_DATA_CUSTOMER_DATA36 EFUSE_DATA_CUSTOMER_DATA37 EFUSE_DATA_CUSTOMER_DATA38 EFUSE_DATA_CUSTOMER_DATA39 EFUSE_DATA_CUSTOMER_DATA40 EFUSE_DATA_CUSTOMER_DATA41 EFUSE_DATA_CUSTOMER_DATA42 EFUSE_DATA_CUSTOMER_DATA43 EFUSE_DATA_CUSTOMER_DATA44 EFUSE_DATA_CUSTOMER_DATA45 EFUSE_DATA_CUSTOMER_DATA46 EFUSE_DATA_CUSTOMER_DATA47 EFUSE_DATA_CUSTOMER_DATA48 EFUSE_DATA_CUSTOMER_DATA49 EFUSE_DATA_CUSTOMER_DATA50 EFUSE_DATA_CUSTOMER_DATA51 EFUSE_DATA_CUSTOMER_DATA52 EFUSE_DATA_CUSTOMER_DATA53 EFUSE_DATA_CUSTOMER_DATA54 EFUSE_DATA_CUSTOMER_DATA55 EFUSE_DATA_CUSTOMER_DATA56 EFUSE_DATA_CUSTOMER_DATA57 EFUSE_DATA_CUSTOMER_DATA58 EFUSE_DATA_CUSTOMER_DATA59 EFUSE_DATA_CUSTOMER_DATA60 EFUSE_DATA_CUSTOMER_DATA61 EFUSE_DATA_CUSTOMER_DATA62 EFUSE_DATA_CUSTOMER_DATA63
Address 0x402C0856 0x402C0857 0x402C0858 0x402C0859 0x402C085A 0x402C085B 0x402C085C 0x402C085D 0x402C085E 0x402C085F 0x402C0860 0x402C0861 0x402C0862 0x402C0863 0x402C0864 0x402C0865 0x402C0866 0x402C0867 0x402C0868 0x402C0869 0x402C086A 0x402C086B 0x402C086C 0x402C086D 0x402C086E 0x402C086F 0x402C0870 0x402C0871 0x402C0872 0x402C0873 0x402C0874 0x402C0875 0x402C0876 0x402C0877 0x402C0878 0x402C0879 0x402C087A 0x402C087B 0x402C087C 0x402C087D 0x402C087E 0x402C087F
Description Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields. Customer data. See EFUSE_DATA_CUSTOMER_DATA0 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
674
EFUSE_DATA_DEAD_ACCESS_RESTRICT0
13.1.1 EFUSE_DATA_DEAD_ACCESS_RESTRICT0
Address = 0x402C0827 DEAD access restrictions Address: 0x402C0827 Retention: Retained
Bits SW Access HW Access
Name
7
6
RW
R
MMIO_ALLOWED [7:6]
5
4
RW
R
SFLASH_ALLOWED [5:4]
3
RW
R
SYS_AP_MPU_ENABL
E
2 RW R
SYS_DISABLE
1 RW R
CM4_DISABLE
0 RW R
CM0_DISABLE
Bits 7 : 6
5 : 4
3 2 1 0
Name MMIO_ALLOWED
SFLASH_ALLOWED
SYS_AP_MPU_ENABLE SYS_DISABLE CM4_DISABLE CM0_DISABLE
Description
This field indicates what portion of the MMIO region is accessible through the system debug access port. Encoding is as follows: 0: All MMIO registers 1: Only IPC MMIO registers accessible (system calls) 2, 3: No MMIO access Default Value: 0
This field indicates what portion of Supervisory Flash is accessible through the system debug access port. Only a portion of Supervisory Flash starting at the bottom of the area is exposed. Encoding is as follows: 0: entire region 1: 1/2 2: 1/4th 3: nothing Default Value: 0
Indicates that the MPU on the system debug access port must be programmed and locked according to the settings in the next 5 fields. Default Value: 0
Indicates that this device does not allow access to the system debug access port (DAP). Default Value: 0
Indicates that this device does not allow access to the M4 debug access port (DAP). Default Value: 0
Indicates that this device does not allow access to the M0+ debug access port (DAP). Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
675
EFUSE_DATA_DEAD_ACCESS_RESTRICT1
13.1.2 EFUSE_DATA_DEAD_ACCESS_RESTRICT1
Address = 0x402C0828 DEAD access restrictions Address: 0x402C0828 Retention: Retained
Bits SW Access HW Access
Name
7
RW
R
DIRECT_EXECUTE_DI
SABLE
6 RW R
UNUSED
5
4
3
RW
R
SRAM_ALLOWED [5:3]
2
1
0
RW
R
FLASH_ALLOWED [2:0]
Bits 7 6 5 : 3
2 : 0
Name DIRECT_EXECUTE_DISABLE UNUSED SRAM_ALLOWED
FLASH_ALLOWED
Description
Disables DirectExecute system call functionality (implemented in software). Default Value: 0
UNUSED Default Value: 0
This field indicates what portion of SRAM 0 is accessible through the system debug access port. Only a portion of SRAM starting at the bottom of the area is exposed. Encoding is the same as FLASH_ALLOWED. Default Value: 0
This field indicates what portion of Main Flash is accessible through the system debug access port. Only a portion of Main Flash starting at the bottom of the area is exposed. Encoding is as follows: 0: entire region 1: 7/8th 2: 3/4th 3: 1/2 4: 1/4th 5: 1/8th 6: 1/16th 7: nothing Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
676
EFUSE_DATA_SECURE_ACCESS_RESTRICT0
13.1.3 EFUSE_DATA_SECURE_ACCESS_RESTRICT0
Address = 0x402C0829 SECURE access restrictions Address: 0x402C0829 Retention: Retained
Bits SW Access HW Access
Name
7
6
RW
R
MMIO_ALLOWED [7:6]
5
4
RW
R
SFLASH_ALLOWED [5:4]
3
RW
R
SYS_AP_MPU_ENABL
E
2 RW R
SYS_DISABLE
1 RW R
CM4_DISABLE
0 RW R
CM0_DISABLE
Bits 7 : 6
5 : 4
3 2 1 0
Name MMIO_ALLOWED
SFLASH_ALLOWED
SYS_AP_MPU_ENABLE SYS_DISABLE CM4_DISABLE CM0_DISABLE
Description
This field indicates what portion of the MMIO region is accessible through the system debug access port. Encoding is as follows: 0: All MMIO registers 1: Only IPC MMIO registers accessible (system calls) 2, 3: No MMIO access Default Value: 0
This field indicates what portion of Supervisory Flash is accessible through the system debug access port. Only a portion of Supervisory Flash starting at the bottom of the area is exposed. Encoding is as follows: 0: entire region 1: 1/2 2: 1/4th 3: nothing Default Value: 0
Indicates that the MPU on the system debug access port must be programmed and locked according to the settings in the next 5 fields. Default Value: 0
Indicates that this device does not allow access to the system debug access port. Default Value: 0
Indicates that this device does not allow access to the M4 debug access port. Default Value: 0
Indicates that this device does not allow access to the M0+ debug access port. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
677
EFUSE_DATA_SECURE_ACCESS_RESTRICT1
13.1.4 EFUSE_DATA_SECURE_ACCESS_RESTRICT1
Address = 0x402C082A SECURE access restrictions Address: 0x402C082A Retention: Retained
Bits SW Access HW Access
Name
7
RW
R
DIRECT_EXECUTE_DI
SABLE
6 RW
R
SMIF_XIP_ALLOWED
5
4
3
RW
R
SRAM_ALLOWED [5:3]
2
1
0
RW
R
FLASH_ALLOWED [2:0]
Bits 7 6
5 : 3
2 : 0
Name DIRECT_EXECUTE_DISABLE SMIF_XIP_ALLOWED
SRAM_ALLOWED
FLASH_ALLOWED
Description
Disables DirectExecute system call functionality (implemented in software). Default Value: 0
This field indicates what portion of SMIF_XIP is accessible through the system debug access port. Encoding is as follows: 0: entire region 1: nothing Default Value: 0
This field indicates what portion of SRAM 0 is accessible through the system debug access port. Only a portion of SRAM starting at the bottom of the area is exposed. Encoding is the same as FLASH_ALLOWED. Default Value: 0
This field indicates what portion of Main Flash is accessible through the system debug access port. Only a portion of Main Flash starting at the bottom of the area is exposed. Encoding is as follows: 0: entire region 1: 7/8th 2: 3/4th 3: 1/2 4: 1/4th 5: 1/8th 6: 1/16th 7: nothing Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
678
EFUSE_DATA_LIFECYCLE_STAGE
13.1.5 EFUSE_DATA_LIFECYCLE_STAGE
Address = 0x402C082B NORMAL, SECURE_WITH_DEBUG, and SECURE fuse bits Address: 0x402C082B Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:4]
4
3
RW
R
RMA
2 RW R
SECURE
1
RW
R
SECURE_WIT H_DEBUG
0 RW R
NORMAL
Bits
Name
Description
3
RMA
This life cycle stage allows one to perform Failure Analysis (FA). The customer transitions the part to RMA life cycle stage when the customer wants Cypress to perform failure analysis on the part. The customer erases all the sensitive data prior to invoking the system call that transitions the part to RMA. Default Value: 0
2
SECURE
This is the life cycle stage of a secure device. Prior to transitioning to this stage, the SECURE_HASH must have been programmed in eFuse and valid application code must have been programmed in the Main Flash Default Value: 0
1
SECURE_WITH_DEBUG This is same as SECURE life cycle stage, except the device allows for debugging. Prior to tran-
sitioning to this stage, the SECURE_HASH must have been programmed in eFuse and valid ap-
plication code must have been programmed in the Main Flash.
Default Value: 0
0
NORMAL
This is the life cycle stage of a device after trimming and testing is complete in the factory. All configuration and trimming information is complete. Valid FLASH boot code has been programmed in the Supervisory Flash. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
679
EFUSE_DATA_CUSTOMER_DATA0
13.1.6 EFUSE_DATA_CUSTOMER_DATA0
Address = 0x402C0840 Customer data Address: 0x402C0840 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
CUSTOMER_USE [7:0]
Bits 7 : 0
Name CUSTOMER_USE
Description
Fuses left over are available for customer use. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
680
14 Profiler Registers
This section discusses the Profiler registers. It lists all the registers in mapping tables, in address order
14.1 Register Details
Register PROFILE_CTL PROFILE_STATUS PROFILE_CMD PROFILE_INTR PROFILE_INTR_SET PROFILE_INTR_MASK PROFILE_INTR_MASKED PROFILE_CNT_STRUCT0_CTL PROFILE_CNT_STRUCT0_CNT PROFILE_CNT_STRUCT1_CTL PROFILE_CNT_STRUCT1_CNT PROFILE_CNT_STRUCT2_CTL PROFILE_CNT_STRUCT2_CNT PROFILE_CNT_STRUCT3_CTL PROFILE_CNT_STRUCT3_CNT PROFILE_CNT_STRUCT4_CTL PROFILE_CNT_STRUCT4_CNT PROFILE_CNT_STRUCT5_CTL PROFILE_CNT_STRUCT5_CNT PROFILE_CNT_STRUCT6_CTL PROFILE_CNT_STRUCT6_CNT PROFILE_CNT_STRUCT7_CTL PROFILE_CNT_STRUCT7_CNT
Address 0x402D0000 0x402D0004 0x402D0010 0x402D07C0 0x402D07C4 0x402D07C8 0x402D07CC 0x402D0800 0x402D0808 0x402D0810 0x402D0818 0x402D0820 0x402D0828 0x402D0830 0x402D0838 0x402D0840 0x402D0848 0x402D0850 0x402D0858 0x402D0860 0x402D0868 0x402D0870 0x402D0878
Description Profile control Profile status Profile command Profile interrupt Profile interrupt set Profile interrupt mask Profile interrupt masked Profile counter configuration Profile counter value Profile counter configuration. See PROFILE_CNT_STRUCT0_CTL for the details of bit fields. Profile counter value. See PROFILE_CNT_STRUCT0_CNT for the details of bit fields. Profile counter configuration. See PROFILE_CNT_STRUCT0_CTL for the details of bit fields. Profile counter value. See PROFILE_CNT_STRUCT0_CNT for the details of bit fields. Profile counter configuration. See PROFILE_CNT_STRUCT0_CTL for the details of bit fields. Profile counter value. See PROFILE_CNT_STRUCT0_CNT for the details of bit fields. Profile counter configuration. See PROFILE_CNT_STRUCT0_CTL for the details of bit fields. Profile counter value. See PROFILE_CNT_STRUCT0_CNT for the details of bit fields. Profile counter configuration. See PROFILE_CNT_STRUCT0_CTL for the details of bit fields. Profile counter value. See PROFILE_CNT_STRUCT0_CNT for the details of bit fields. Profile counter configuration. See PROFILE_CNT_STRUCT0_CTL for the details of bit fields. Profile counter value. See PROFILE_CNT_STRUCT0_CNT for the details of bit fields. Profile counter configuration. See PROFILE_CNT_STRUCT0_CTL for the details of bit fields. Profile counter value. See PROFILE_CNT_STRUCT0_CNT for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
681
PROFILE_CTL
14.1.1 PROFILE_CTL
Address = 0x402D0000 Profile control Address: 0x402D0000 Retention: Retained
Bits
7
6
SW Access
HW Access
Name
Bits
15
14
SW Access
HW Access
Name
Bits
23
22
SW Access
HW Access
Name
Bits
31
30
SW Access
RW
HW Access
R
Name
ENABLED
5
4
3
2
None
None
None [7:1]
13
12
11
10
None
None
None [15:8]
21
20
19
18
None
None
None [23:16]
29
28
27
26
None
None
None [30:24]
1
0
RW
R
WIN_MODE
9
8
17
16
25
24
Bits
Name
31
ENABLED
0
WIN_MODE
Description
Enables the profiling block: '0': Disabled. '1': Enabled. Default Value: 0
Specifies the profiling time window mode: '0': Start / stop mode. The profiling time window is started when a rising edge of the start trigger signal occurs and stopped when a rising edge of the stop trigger signal occurs. In case both rising edges (of start and stop trigger signals) occur in the same cycle, the profiling time window is stopped. '1': Enable mode. The profiling time window is active as long as the start 'trigger' signal is active. The stop trigger signal has no effect. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
682
PROFILE_STATUS
14.1.2 PROFILE_STATUS
Address = 0x402D0004 Profile status Address: 0x402D0004 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
R
HW Access
None
W
Name
None [7:1]
WIN_ACTIVE
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
WIN_ACTIVE
Description
Indicates if the profiling time window is active. '0': Not active. '1': Active. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
683
PROFILE_CMD
14.1.3 PROFILE_CMD
Address = 0x402D0010 Profile command Address: 0x402D0010 Retention: Retained
Bits
7
6
SW Access
HW Access
Name
Bits
15
14
SW Access
HW Access
Name
Bits
23
22
SW Access
HW Access
Name
Bits
31
30
SW Access
HW Access
Name
5
4
3
None
None
None [7:2]
13
12
11
None
None
None [15:9]
21
20
19
None
None
None [23:16]
29
28
27
None
None
None [31:24]
2
1
0
RW1S
RW1S
RW1C
RW1C
STOP_TR START_TR
10
9
8
RW1S
RW1C
CLR_ALL_CN
T
18
17
16
26
25
24
Bits
Name
8
CLR_ALL_CNT
1
STOP_TR
0
START_TR
Description
Counter clear. When written with '1', all profiling counter registers are cleared to 0x00. Default Value: 0
Software stop trigger for the profiling time window. When written with '1', the profiling time window is stopped. Can only be used in start / stop mode (PROFILE_WIN_MODE=0). Has no effect in enable mode (PROFILE_WIN_MODE=1). Default Value: 0
Software start trigger for the profiling time window. When written with '1', the profiling time window is started. Can only be used in start / stop mode (PROFILE_WIN_MODE=0). Has no effect in enable mode (PROFILE_WIN_MODE=1). Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
684
PROFILE_INTR
14.1.4 PROFILE_INTR
Address = 0x402D07C0 Profile interrupt Address: 0x402D07C0 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW1C
HW Access
RW1S
Name
CNT_OVFLW [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 0
Name CNT_OVFLW
Description
This interrupt cause field is activated (HW sets the field to '1') when an profiling counter overflow (from 0xFFFFFFFF to 0x00000000) is captured. There is one bit per profling counter. SW writes a '1' to a bit of this field to clear this bit to '0' (writing 0xFFFFFFFF clears all interrupt causes to '0'). Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
685
PROFILE_INTR_SET
14.1.5 PROFILE_INTR_SET
Address = 0x402D07C4 Profile interrupt set Address: 0x402D07C4 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW1S
HW Access
A
Name
CNT_OVFLW [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 0
Name CNT_OVFLW
Description
SW writes a '1' to a bit of this field to set the corresponding bit in the INTR register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
686
PROFILE_INTR_MASK
14.1.6 PROFILE_INTR_MASK
Address = 0x402D07C8 Profile interrupt mask Address: 0x402D07C8 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
CNT_OVFLW [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 0
Name CNT_OVFLW
Description
Mask bit for corresponding field in the INTR register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
687
PROFILE_INTR_MASKED
14.1.7 PROFILE_INTR_MASKED
Address = 0x402D07CC Profile interrupt masked Address: 0x402D07CC Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
CNT_OVFLW [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 0
Name CNT_OVFLW
Description
Logical and of corresponding INTR and INTR_MASK fields. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
688
PROFILE_CNT_STRUCT0_CTL
14.1.8 PROFILE_CNT_STRUCT0_CTL
Address = 0x402D0800 Profile counter configuration Address: 0x402D0800 Retention: Retained
Bits SW Access HW Access
Name
7 None None
None
6
5
4
RW
R
REF_CLK_SEL [6:4]
3
2
1
0
None
RW
None
R
None [3:1]
CNT_DURATION
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
HW Access
None
R
Name
None
MON_SEL [22:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
None
HW Access
R
None
Name
ENABLED
None [30:24]
Bits
Name
31
ENABLED
22 : 16
MON_SEL
6 : 4
REF_CLK_SEL
Description
Enables the profiling counter: '0': Disabled. '1': Enabled. Default Value: 0
This field specifies the montior input signal to be observed by the profiling counter. The monitor signals are product specific, see product definition spreadsheet tab "Monitor" for details. Default Value: 0
This field specifies the reference clock used for a counting time base when counting durations. Has no effect when CTL.CNT_DURATION=0. Default Value: 0
0x0: CLK_TIMER : Timer clock (divided or undivided high frequency clock, e.g. from IMO). Selection is done in SRSS register CLK_TIMER_CTL.TIMER_SEL.
0x1: CLK_IMO : IMO - Internal Main Oscillator
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
689
PROFILE_CNT_STRUCT0_CTL
14.1.8
0
PROFILE_CNT_STRUCT0_CTL (continued)
CNT_DURATION
0x2: CLK_ECO :
ECO - External-Crystal Oscillator
0x3: CLK_LF : Low frequency clock (ILO, WCO or ALTLF). Selection is done in SRSS register CLK_SELECT.LFCLK_SEL.
0x4: CLK_HF : High frequuency clock ("clk_hfx").
0x5: CLK_PERI : Peripheral clock ("clk_peri").
0x6: RESERVED_6 : Reserved. Do not use. When using, the behavior of this profiling counter is undefined.
0x7: RESERVED_7 : Reserved. Do not use. When using, the behavior of this profiling counter is undefined.
This field specifies if events (edges) or a duration of the monitor signal is counted. '0': Events are monitored. An edge detection is done. All edges of the selected monitor signal are counted. '1': A duration is monitored. No edge detection is done. The monitored signal is taken as a (high active) level signal for enabling the profiling counter. Note: All monitor signals which only can represent events are edge encoded in hardware, therefore a selection of CTL.CNT_DURATION=1 will not produce meaningful results. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
690
PROFILE_CNT_STRUCT0_CNT
14.1.9 PROFILE_CNT_STRUCT0_CNT
Address = 0x402D0808 Profile counter value Address: 0x402D0808 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
A
Name
CNT [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
A
Name
CNT [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
A
Name
CNT [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
A
Name
CNT [31:24]
Bits 31 : 0
Name CNT
Description
This field shows / specifies the actual value of the profiling counter. It allows reading as well as writing the profiling counter. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
691
Section E: Peripheral Group 3
This section encompasses the following chapters: High Speed IO Matrix (HSIOM) Registers chapter on page 693 General Purpose I/O (GPIO) Registers chapter on page 705 Smart I/O Registers chapter on page 793 Universal Digital Block (UDB) Registers chapter on page 806 Low-Power Comparator Registers chapter on page 1047 Timer, Counter, PWM (TCPWM) Registers chapter on page 1062 Segment LCD Drive Registers chapter on page 1121 USB Registers chapter on page 1129
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
692
15 High Speed IO Matrix (HSIOM) Registers
This section discusses the High-Speed I/O Matrix (HSIOM) registers. It lists all the registers in mapping tables, in address order.
15.1 Register Details
Register HSIOM_PRT0_PORT_SEL0 HSIOM_PRT0_PORT_SEL1 HSIOM_PRT1_PORT_SEL0 HSIOM_PRT1_PORT_SEL1 HSIOM_PRT2_PORT_SEL0 HSIOM_PRT2_PORT_SEL1 HSIOM_PRT3_PORT_SEL0 HSIOM_PRT3_PORT_SEL1 HSIOM_PRT4_PORT_SEL0 HSIOM_PRT5_PORT_SEL0 HSIOM_PRT5_PORT_SEL1 HSIOM_PRT6_PORT_SEL0 HSIOM_PRT6_PORT_SEL1 HSIOM_PRT7_PORT_SEL0 HSIOM_PRT7_PORT_SEL1 HSIOM_PRT8_PORT_SEL0 HSIOM_PRT8_PORT_SEL1 HSIOM_PRT9_PORT_SEL0 HSIOM_PRT9_PORT_SEL1 HSIOM_PRT10_PORT_SEL0 HSIOM_PRT10_PORT_SEL1 HSIOM_PRT11_PORT_SEL0 HSIOM_PRT11_PORT_SEL1 HSIOM_PRT12_PORT_SEL0 HSIOM_PRT12_PORT_SEL1 HSIOM_PRT13_PORT_SEL0
Address 0x40310000 0x40310004 0x40310010 0x40310014 0x40310020 0x40310024 0x40310030 0x40310034 0x40310040 0x40310050 0x40310054 0x40310060 0x40310064 0x40310070 0x40310074 0x40310080 0x40310084 0x40310090 0x40310094 0x403100A0 0x403100A4 0x403100B0 0x403100B4 0x403100C0 0x403100C4 0x403100D0
Description Port selection 0 Port selection 1 Port selection 0. See HSIOM_PRT0_PORT_SEL0 for the details of bit fields. Port selection 1. See HSIOM_PRT0_PORT_SEL1 for the details of bit fields. Port selection 0. See HSIOM_PRT0_PORT_SEL0 for the details of bit fields. Port selection 1 Port selection 0. See HSIOM_PRT0_PORT_SEL0 for the details of bit fields. Port selection 1. See HSIOM_PRT0_PORT_SEL1 for the details of bit fields. Port selection 0. See HSIOM_PRT0_PORT_SEL0 for the details of bit fields. Port selection 0. See HSIOM_PRT0_PORT_SEL0 for the details of bit fields. Port selection 1. See HSIOM_PRT2_PORT_SEL1 for the details of bit fields. Port selection 0. See HSIOM_PRT0_PORT_SEL0 for the details of bit fields. Port selection 1. See HSIOM_PRT2_PORT_SEL1 for the details of bit fields. Port selection 0. See HSIOM_PRT0_PORT_SEL0 for the details of bit fields. Port selection 1. See HSIOM_PRT2_PORT_SEL1 for the details of bit fields. Port selection 0. See HSIOM_PRT0_PORT_SEL0 for the details of bit fields. Port selection 1. See HSIOM_PRT2_PORT_SEL1 for the details of bit fields. Port selection 0. See HSIOM_PRT0_PORT_SEL0 for the details of bit fields. Port selection 1. See HSIOM_PRT2_PORT_SEL1 for the details of bit fields. Port selection 0. See HSIOM_PRT0_PORT_SEL0 for the details of bit fields. Port selection 1. See HSIOM_PRT2_PORT_SEL1 for the details of bit fields. Port selection 0. See HSIOM_PRT0_PORT_SEL0 for the details of bit fields. Port selection 1. See HSIOM_PRT2_PORT_SEL1 for the details of bit fields. Port selection 0. See HSIOM_PRT0_PORT_SEL0 for the details of bit fields. Port selection 1. See HSIOM_PRT2_PORT_SEL1 for the details of bit fields. Port selection 0. See HSIOM_PRT0_PORT_SEL0 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
693
High Speed IO Matrix (HSIOM) Registers
Register HSIOM_PRT13_PORT_SEL1 HSIOM_PRT14_PORT_SEL0 HSIOM_AMUX_SPLIT_CTL0 HSIOM_AMUX_SPLIT_CTL1 HSIOM_AMUX_SPLIT_CTL2 HSIOM_AMUX_SPLIT_CTL3 HSIOM_AMUX_SPLIT_CTL4 HSIOM_AMUX_SPLIT_CTL5 HSIOM_AMUX_SPLIT_CTL6 HSIOM_AMUX_SPLIT_CTL7 HSIOM_AMUX_SPLIT_CTL8
Address 0x403100D4 0x403100E0 0x40312000 0x40312004 0x40312008 0x4031200C 0x40312010 0x40312014 0x40312018 0x4031201C 0x40312020
Description Port selection 1. See HSIOM_PRT2_PORT_SEL1 for the details of bit fields. Port selection 0 AMUX splitter cell control AMUX splitter cell control. See HSIOM_AMUX_SPLIT_CTL0 for the details of bit fields. AMUX splitter cell control. See HSIOM_AMUX_SPLIT_CTL0 for the details of bit fields. AMUX splitter cell control. See HSIOM_AMUX_SPLIT_CTL0 for the details of bit fields. AMUX splitter cell control. See HSIOM_AMUX_SPLIT_CTL0 for the details of bit fields. AMUX splitter cell control. See HSIOM_AMUX_SPLIT_CTL0 for the details of bit fields. AMUX splitter cell control. See HSIOM_AMUX_SPLIT_CTL0 for the details of bit fields. AMUX splitter cell control. See HSIOM_AMUX_SPLIT_CTL0 for the details of bit fields. AMUX splitter cell control. See HSIOM_AMUX_SPLIT_CTL0 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
694
HSIOM_PRT0_PORT_SEL0
15.1.1 HSIOM_PRT0_PORT_SEL0
Address = 0x40310000 Port selection 0 Address: 0x40310000 Retention: Retained
Bits
7
6
5
4
SW Access
None
HW Access
None
Name
None [7:5]
Bits
15
14
13
12
SW Access
None
HW Access
None
Name
None [15:13]
Bits
23
22
21
20
SW Access
None
HW Access
None
Name
None [23:21]
Bits
31
30
29
28
SW Access
None
HW Access
None
Name
None [31:29]
3
2
1
RW
RW
IO0_SEL [4:0]
11
10
9
RW
RW
IO1_SEL [12:8]
19
18
17
RW
RW
IO2_SEL [20:16]
27
26
25
RW
RW
IO3_SEL [28:24]
Bits 28 : 24 20 : 16 12 : 8 4 : 0
Name IO3_SEL IO2_SEL IO1_SEL IO0_SEL
Description
Selects connection for IO pin 3 route. Default Value: 0
Selects connection for IO pin 2 route. Default Value: 0
Selects connection for IO pin 1 route. Default Value: 0
Selects connection for IO pin 0 route. Default Value: 0
0x0: GPIO : GPIO controls "out"
0x1: GPIO_DSI : GPIO controls "out", DSI controls "output enable"
0x2: DSI_DSI : DSI controls "out" and "output enable"
0x3: DSI_GPIO : DSI controls "out", GPIO controls "output enable"
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
0 8 16 24
695
15.1.1
HSIOM_PRT0_PORT_SEL0 (continued)
0x4: AMUXA : Analog mux bus A
0x5: AMUXB : Analog mux bus B
0x6: AMUXA_DSI : Analog mux bus A, DSI control
0x7: AMUXB_DSI : Analog mux bus B, DSI control
0x8: ACT_0 : Active functionality 0
0x9: ACT_1 : Active functionality 1
0xa: ACT_2 : Active functionality 2
0xb: ACT_3 : Active functionality 3
0xc: DS_0 : DeepSleep functionality 0
0xd: DS_1 : DeepSleep functionality 1
0xe: DS_2 : DeepSleep functionality 2
0xf: DS_3 : DeepSleep functionality 3
0x10: ACT_4 : Active functionality 4
0x11: ACT_5 : Active functionality 5
0x12: ACT_6 : Active functionality 6
0x13: ACT_7 : Active functionality 7
0x14: ACT_8 : Active functionality 8
0x15: ACT_9 : Active functionality 9
0x16: ACT_10 : Active functionality 10
0x17: ACT_11 : Active functionality 11
0x18: ACT_12 : Active functionality 12
0x19: ACT_13 : Active functionality 13
HSIOM_PRT0_PORT_SEL0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
696
15.1.1
HSIOM_PRT0_PORT_SEL0 (continued)
0x1a: ACT_14 : Active functionality 14
0x1b: ACT_15 : Active functionality 15
0x1c: DS_4 : DeepSleep functionality 4
0x1d: DS_5 : DeepSleep functionality 5
0x1e: DS_6 : DeepSleep functionality 6
0x1f: DS_7 : DeepSleep functionality 7
HSIOM_PRT0_PORT_SEL0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
697
HSIOM_PRT0_PORT_SEL1
15.1.2 HSIOM_PRT0_PORT_SEL1
Address = 0x40310004 Port selection 1 Address: 0x40310004 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
RW
Name
None [7:5]
IO4_SEL [4:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
RW
HW Access
None
RW
Name
None [15:13]
IO5_SEL [12:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 12 : 8
4 : 0
Name IO5_SEL
IO4_SEL
Description
Selects connection for IO pin 5 route. Default Value: 0
Selects connection for IO pin 4 route. See PORT_SEL0 for connection details. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
698
HSIOM_PRT2_PORT_SEL1
15.1.3 HSIOM_PRT2_PORT_SEL1
Address = 0x40310024 Port selection 1 Address: 0x40310024 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
RW
Name
None [7:5]
IO4_SEL [4:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
RW
HW Access
None
RW
Name
None [15:13]
IO5_SEL [12:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
HW Access
None
RW
Name
None [23:21]
IO6_SEL [20:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
RW
HW Access
None
RW
Name
None [31:29]
IO7_SEL [28:24]
Bits 28 : 24 20 : 16 12 : 8 4 : 0
Name IO7_SEL IO6_SEL IO5_SEL IO4_SEL
Description
Selects connection for IO pin 7 route. Default Value: 0
Selects connection for IO pin 6 route. Default Value: 0
Selects connection for IO pin 5 route. Default Value: 0
Selects connection for IO pin 4 route. See PORT_SEL0 for connection details. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
699
HSIOM_PRT14_PORT_SEL0
15.1.4 HSIOM_PRT14_PORT_SEL0
Address = 0x403100E0 Port selection 0 Address: 0x403100E0 Retention: Retained
Bits
7
6
5
4
3
2
1
SW Access
None
RW
HW Access
None
RW
Name
None [7:5]
IO0_SEL [4:0]
Bits
15
14
13
12
11
10
9
SW Access
None
RW
HW Access
None
RW
Name
None [15:13]
IO1_SEL [12:8]
Bits
23
22
21
20
19
18
17
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
SW Access
None
HW Access
None
Name
None [31:24]
Bits 12 : 8
4 : 0
Name IO1_SEL
IO0_SEL
Description
Selects connection for IO pin 1 route. Default Value: 0
Selects connection for IO pin 0 route. Default Value: 0
0x0: GPIO : GPIO controls "out"
0x1: GPIO_DSI : GPIO controls "out", DSI controls "output enable"
0x2: DSI_DSI : DSI controls "out" and "output enable"
0x3: DSI_GPIO : DSI controls "out", GPIO controls "output enable"
0x4: AMUXA : Analog mux bus A
0x5: AMUXB : Analog mux bus B
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
0 8 16 24
700
HSIOM_PRT14_PORT_SEL0
0x6: AMUXA_DSI : Analog mux bus A, DSI control
0x7: AMUXB_DSI : Analog mux bus B, DSI control
0x8: ACT_0 : Active functionality 0
0x9: ACT_1 : Active functionality 1
0xa: ACT_2 : Active functionality 2
0xb: ACT_3 : Active functionality 3
0xc: DS_0 : DeepSleep functionality 0
0xd: DS_1 : DeepSleep functionality 1
0xe: DS_2 : DeepSleep functionality 2
0xf: DS_3 : DeepSleep functionality 3
0x10: ACT_4 : Active functionality 4
0x11: ACT_5 : Active functionality 5
0x12: ACT_6 : Active functionality 6
0x13: ACT_7 : Active functionality 7
0x14: ACT_8 : Active functionality 8
0x15: ACT_9 : Active functionality 9
0x16: ACT_10 : Active functionality 10
0x17: ACT_11 : Active functionality 11
0x18: ACT_12 : Active functionality 12
0x19: ACT_13 : Active functionality 13
0x1a: ACT_14 : Active functionality 14
0x1b: ACT_15 : Active functionality 15
0x1c: DS_4 : DeepSleep functionality 4
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
701
15.1.4
HSIOM_PRT14_PORT_SEL0 (continued)
0x1d: DS_5 : DeepSleep functionality 5
0x1e: DS_6 : DeepSleep functionality 6
0x1f: DS_7 : DeepSleep functionality 7
HSIOM_PRT14_PORT_SEL0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
702
HSIOM_AMUX_SPLIT_CTL0
15.1.5 HSIOM_AMUX_SPLIT_CTL0
Address = 0x40312000 AMUX splitter cell control Address: 0x40312000 Retention: Retained
Bits SW Access HW Access
Name
7 None None
None
6
5
4
RW
RW
RW
R
R
R
SWITCH_B- SWITCH_B- SWITCH_B-
B_S0
B_SR
B_SL
3 None None
None
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
RW
R
SWITCH_A A_S0
1
RW
R
SWITCH_A A_SR
0
RW
R
SWITCH_A A_SL
10
9
8
18
17
16
26
25
24
Bits
Name
6
SWITCH_BB_S0
5
SWITCH_BB_SR
4
SWITCH_BB_SL
2
SWITCH_AA_S0
1
SWITCH_AA_SR
Description
T-switch control for AMUXBUSB vssa/ground switch. Default Value: 0
T-switch control for Right AMUXBUSB switch. Default Value: 0
T-switch control for Left AMUXBUSB switch. Default Value: 0
T-switch control for AMUXBUSA vssa/ground switch: '0': switch open. '1': switch closed. Default Value: 0
T-switch control for Right AMUXBUSA switch: '0': switch open. '1': switch closed. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
703
HSIOM_AMUX_SPLIT_CTL0
15.1.5
0
HSIOM_AMUX_SPLIT_CTL0 (continued)
SWITCH_AA_SL
T-switch control for Left AMUXBUSA switch: '0': switch open. '1': switch closed. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
704
16 General Purpose I/O (GPIO) Registers
This section discusses the General Purpose I/O (GPIO) registers. It lists all the registers in mapping tables, in address order.
16.1 Register Details
Register GPIO_PRT0_OUT GPIO_PRT0_OUT_CLR GPIO_PRT0_OUT_SET GPIO_PRT0_OUT_INV GPIO_PRT0_IN GPIO_PRT0_INTR GPIO_PRT0_INTR_MASK GPIO_PRT0_INTR_MASKED GPIO_PRT0_INTR_SET GPIO_PRT0_INTR_CFG GPIO_PRT0_CFG GPIO_PRT0_CFG_IN GPIO_PRT0_CFG_OUT GPIO_PRT1_OUT GPIO_PRT1_OUT_CLR GPIO_PRT1_OUT_SET GPIO_PRT1_OUT_INV GPIO_PRT1_IN GPIO_PRT1_INTR GPIO_PRT1_INTR_MASK GPIO_PRT1_INTR_MASKED GPIO_PRT1_INTR_SET GPIO_PRT1_INTR_CFG GPIO_PRT1_CFG GPIO_PRT1_CFG_IN GPIO_PRT1_CFG_OUT GPIO_PRT2_OUT
Address 0x40320000 0x40320004 0x40320008 0x4032000C 0x40320010 0x40320014 0x40320018 0x4032001C 0x40320020 0x40320024 0x40320028 0x4032002C 0x40320030 0x40320080 0x40320084 0x40320088 0x4032008C 0x40320090 0x40320094 0x40320098 0x4032009C 0x403200A0 0x403200A4 0x403200A8 0x403200AC 0x403200B0 0x40320100
Description Port output data register Port output data clear register Port output data set register Port output data invert register Port input state register Port interrupt status register Port interrupt mask register Port interrupt masked status register Port interrupt set register Port interrupt configuration register Port configuration register Port input buffer configuration register Port output buffer configuration register Port output data register. See GPIO_PRT0_OUT for the details of bit fields. Port output data clear register. See GPIO_PRT0_OUT_CLR for the details of bit fields. Port output data set register. See GPIO_PRT0_OUT_SET for the details of bit fields. Port output data invert register. See GPIO_PRT0_OUT_INV for the details of bit fields. Port input state register. See GPIO_PRT0_IN for the details of bit fields. Port interrupt status register. See GPIO_PRT0_INTR for the details of bit fields. Port interrupt mask register. See GPIO_PRT0_INTR_MASK for the details of bit fields. Port interrupt masked status register. See GPIO_PRT0_INTR_MASKED for the details of bit fields. Port interrupt set register. See GPIO_PRT0_INTR_SET for the details of bit fields. Port interrupt configuration register. See GPIO_PRT0_INTR_CFG for the details of bit fields. Port configuration register. See GPIO_PRT0_CFG for the details of bit fields. Port input buffer configuration register. See GPIO_PRT0_CFG_IN for the details of bit fields. Port output buffer configuration register. See GPIO_PRT0_CFG_OUT for the details of bit fields. Port output data register
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
705
General Purpose I/O (GPIO) Registers
Register GPIO_PRT2_OUT_CLR GPIO_PRT2_OUT_SET GPIO_PRT2_OUT_INV GPIO_PRT2_IN GPIO_PRT2_INTR GPIO_PRT2_INTR_MASK GPIO_PRT2_INTR_MASKEDT GPIO_PRT2_INTR_SET GPIO_PRT2_INTR_CFG GPIO_PRT2_CFG GPIO_PRT2_CFG_IN GPIO_PRT2_CFG_OUT GPIO_PRT3_OUT GPIO_PRT3_OUT_CLR GPIO_PRT3_OUT_SET GPIO_PRT3_OUT_INV GPIO_PRT3_IN GPIO_PRT3_INTR GPIO_PRT3_INTR_MASK GPIO_PRT3_INTR_MASKED GPIO_PRT3_INTR_SET GPIO_PRT3_INTR_CFG GPIO_PRT3_CFG GPIO_PRT3_CFG_IN GPIO_PRT3_CFG_OUT GPIO_PRT4_OUT GPIO_PRT4_OUT_CLR GPIO_PRT4_OUT_SET GPIO_PRT4_OUT_INV GPIO_PRT4_IN GPIO_PRT4_INTR GPIO_PRT4_INTR_MASK GPIO_PRT4_INTR_MASKED GPIO_PRT4_INTR_SET GPIO_PRT4_INTR_CFG GPIO_PRT4_CFG GPIO_PRT4_CFG_IN GPIO_PRT4_CFG_OUT GPIO_PRT5_OUT GPIO_PRT5_OUT_CLR GPIO_PRT5_OUT_SET GPIO_PRT5_OUT_INV
Address 0x40320104 0x40320108 0x4032010C 0x40320110 0x40320114 0x40320118 0x4032011C 0x40320120 0x40320124 0x40320128 0x4032012C 0x40320130 0x40320180 0x40320184 0x40320188 0x4032018C 0x40320190 0x40320194 0x40320198 0x4032019C 0x403201A0 0x403201A4 0x403201A8 0x403201AC 0x403201B0 0x40320200 0x40320204 0x40320208 0x4032020C 0x40320210 0x40320214 0x40320218 0x4032021C 0x40320220 0x40320224 0x40320228 0x4032022C 0x40320230 0x40320280 0x40320284 0x40320288 0x4032028C
Description Port output data clear register. See GPIO_PRT0_OUT_CLR for the details of bit fields. Port output data set register. See GPIO_PRT0_OUT_SET for the details of bit fields. Port output data invert register. See GPIO_PRT0_OUT_INV for the details of bit fields. Port input state register Port interrupt status register Port interrupt mask register Port interrupt masked status register Port interrupt set register Port interrupt configuration register Port configuration register Port input buffer configuration register Port output buffer configuration register Port output data register. See GPIO_PRT0_OUT for the details of bit fields. Port output data clear register. See GPIO_PRT0_OUT_CLR for the details of bit fields. Port output data set register. See GPIO_PRT0_OUT_SET for the details of bit fields. Port output data invert register. See GPIO_PRT0_OUT_INV for the details of bit fields. Port input state register. See GPIO_PRT0_IN for the details of bit fields. Port interrupt status register. See GPIO_PRT0_INTR for the details of bit fields. Port interrupt mask register. See GPIO_PRT0_INTR_MASK for the details of bit fields. Port interrupt masked status register. See GPIO_PRT0_INTR_MASKED for the details of bit fields. Port interrupt set register. See GPIO_PRT0_INTR_SET for the details of bit fields. Port interrupt configuration register. See GPIO_PRT0_INTR_CFG for the details of bit fields. Port configuration register. See GPIO_PRT0_CFG for the details of bit fields. Port input buffer configuration register. See GPIO_PRT0_CFG_IN for the details of bit fields. Port output buffer configuration register. See GPIO_PRT0_CFG_OUT for the details of bit fields. Port output data register Port output data clear register. See GPIO_PRT0_OUT_CLR for the details of bit fields. Port output data set register. See GPIO_PRT0_OUT_SET for the details of bit fields. Port output data invert register. See GPIO_PRT0_OUT_INV for the details of bit fields. Port input state register Port interrupt status register Port interrupt mask register Port interrupt masked status register Port interrupt set register Port interrupt configuration register Port configuration register Port input buffer configuration register Port output buffer configuration register Port output data register. See GPIO_PRT2_OUT for the details of bit fields. Port output data clear register. See GPIO_PRT0_OUT_CLR for the details of bit fields. Port output data set register. See GPIO_PRT0_OUT_SET for the details of bit fields. Port output data invert register. See GPIO_PRT0_OUT_INV for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
706
General Purpose I/O (GPIO) Registers
Register GPIO_PRT5_IN GPIO_PRT5_INTR GPIO_PRT5_INTR_MASK GPIO_PRT5_INTR_MASKED GPIO_PRT5_INTR_SET GPIO_PRT5_INTR_CFG GPIO_PRT5_CFG GPIO_PRT5_CFG_IN GPIO_PRT5_CFG_OUT GPIO_PRT6_OUT GPIO_PRT6_OUT_CLR GPIO_PRT6_OUT_SET GPIO_PRT6_OUT_INV GPIO_PRT6_IN GPIO_PRT6_INTR GPIO_PRT6_INTR_MASK GPIO_PRT6_INTR_MASKED GPIO_PRT6_INTR_SET GPIO_PRT6_INTR_CFG GPIO_PRT6_CFG GPIO_PRT6_CFG_IN GPIO_PRT6_CFG_OUT GPIO_PRT7_OUT GPIO_PRT7_OUT_CLR GPIO_PRT7_OUT_SET GPIO_PRT7_OUT_INV GPIO_PRT7_IN GPIO_PRT7_INTR GPIO_PRT7_INTR_MASK GPIO_PRT7_INTR_MASKED GPIO_PRT7_INTR_SET GPIO_PRT7_INTR_CFG GPIO_PRT7_CFG GPIO_PRT7_CFG_IN GPIO_PRT7_CFG_OUT GPIO_PRT8_OUT GPIO_PRT8_OUT_CLR GPIO_PRT8_OUT_SET GPIO_PRT8_OUT_INV GPIO_PRT8_IN GPIO_PRT8_INTR GPIO_PRT8_INTR_MASK
Address 0x40320290 0x40320294 0x40320298 0x4032029C 0x403202A0 0x403202A4 0x403202A8 0x403202AC 0x403202B0 0x40320300 0x40320304 0x40320308 0x4032030C 0x40320310 0x40320314 0x40320318 0x4032031C 0x40320320 0x40320324 0x40320328 0x4032032C 0x40320330 0x40320380 0x40320384 0x40320388 0x4032038C 0x40320390 0x40320394 0x40320398 0x4032039C 0x403203A0 0x403203A4 0x403203A8 0x403203AC 0x403203B0 0x40320400 0x40320404 0x40320408 0x4032040C 0x40320410 0x40320414 0x40320418
Description Port input state register. See GPIO_PRT2_IN for the details of bit fields. Port interrupt status register. See GPIO_PRT2_INTR for the details of bit fields. Port interrupt mask register. See GPIO_PRT2_INTR_MASK for the details of bit fields. Port interrupt masked status register. See GPIO_PRT2_INTR_MASKED for the details of bit fields. Port interrupt set register. See GPIO_PRT2_INTR_SET for the details of bit fields. Port interrupt configuration register. See GPIO_PRT2_INTR_CFG for the details of bit fields. Port configuration register. See GPIO_PRT2_CFG for the details of bit fields. Port input buffer configuration register. See GPIO_PRT2_CFG_IN for the details of bit fields. Port output buffer configuration register. See GPIO_PRT2_CFG_OUT for the details of bit fields. Port output data register. See GPIO_PRT2_OUT for the details of bit fields. Port output data clear register. See GPIO_PRT0_OUT_CLR for the details of bit fields. Port output data set register. See GPIO_PRT0_OUT_SET for the details of bit fields. Port output data invert register. See GPIO_PRT0_OUT_INV for the details of bit fields. Port input state register. See GPIO_PRT2_IN for the details of bit fields. Port interrupt status register. See GPIO_PRT2_INTR for the details of bit fields. Port interrupt mask register. See GPIO_PRT2_INTR_MASK for the details of bit fields. Port interrupt masked status register. See GPIO_PRT2_INTR_MASKED for the details of bit fields. Port interrupt set register. See GPIO_PRT2_INTR_SET for the details of bit fields. Port interrupt configuration register. See GPIO_PRT2_INTR_CFG for the details of bit fields. Port configuration register. See GPIO_PRT2_CFG for the details of bit fields. Port input buffer configuration register. See GPIO_PRT2_CFG_IN for the details of bit fields. Port output buffer configuration register. See GPIO_PRT2_CFG_OUT for the details of bit fields. Port output data register. See GPIO_PRT2_OUT for the details of bit fields. Port output data clear register. See GPIO_PRT0_OUT_CLR for the details of bit fields. Port output data set register. See GPIO_PRT0_OUT_SET for the details of bit fields. Port output data invert register. See GPIO_PRT0_OUT_INV for the details of bit fields. Port input state register. See GPIO_PRT2_IN for the details of bit fields. Port interrupt status register. See GPIO_PRT2_INTR for the details of bit fields. Port interrupt mask register. See GPIO_PRT2_INTR_MASK for the details of bit fields. Port interrupt masked status register. See GPIO_PRT2_INTR_MASKED for the details of bit fields. Port interrupt set register. See GPIO_PRT2_INTR_SET for the details of bit fields. Port interrupt configuration register. See GPIO_PRT2_INTR_CFG for the details of bit fields. Port configuration register. See GPIO_PRT2_CFG for the details of bit fields. Port input buffer configuration register. See GPIO_PRT2_CFG_IN for the details of bit fields. Port output buffer configuration register. See GPIO_PRT2_CFG_OUT for the details of bit fields. Port output data register. See GPIO_PRT2_OUT for the details of bit fields. Port output data clear register. See GPIO_PRT0_OUT_CLR for the details of bit fields. Port output data set register. See GPIO_PRT0_OUT_SET for the details of bit fields. Port output data invert register. See GPIO_PRT0_OUT_INV for the details of bit fields. Port input state register. See GPIO_PRT2_IN for the details of bit fields. Port interrupt status register. See GPIO_PRT2_INTR for the details of bit fields. Port interrupt mask register. See GPIO_PRT2_INTR_MASK for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
707
General Purpose I/O (GPIO) Registers
Register GPIO_PRT8_INTR_MASKED GPIO_PRT8_INTR_SET GPIO_PRT8_INTR_CFG GPIO_PRT8_CFG GPIO_PRT8_CFG_IN GPIO_PRT8_CFG_OUT GPIO_PRT9_OUT GPIO_PRT9_OUT_CLR GPIO_PRT9_OUT_SET GPIO_PRT9_OUT_INV GPIO_PRT9_IN GPIO_PRT9_INTR GPIO_PRT9_INTR_MASK GPIO_PRT9_INTR_MASKED GPIO_PRT9_INTR_SET GPIO_PRT9_INTR_CFG GPIO_PRT9_CFG GPIO_PRT9_CFG_IN GPIO_PRT9_CFG_OUT GPIO_PRT10_OUT GPIO_PRT10_OUT_CLR GPIO_PRT10_OUT_SET GPIO_PRT10_OUT_INV GPIO_PRT10_IN GPIO_PRT10_INTR GPIO_PRT10_INTR_MASK GPIO_PRT10_INTR_MASKED GPIO_PRT10_INTR_SET GPIO_PRT10_INTR_CFG GPIO_PRT10_CFG GPIO_PRT10_CFG_IN GPIO_PRT10_CFG_OUT GPIO_PRT11_OUT GPIO_PRT11_OUT_CLR GPIO_PRT11_OUT_SET GPIO_PRT11_OUT_INV GPIO_PRT11_IN GPIO_PRT11_INTR GPIO_PRT11_INTR_MASK GPIO_PRT11_INTR_MASKED GPIO_PRT11_INTR_SET GPIO_PRT11_INTR_CFG
Address 0x4032041C 0x40320420 0x40320424 0x40320428 0x4032042C 0x40320430 0x40320480 0x40320484 0x40320488 0x4032048C 0x40320490 0x40320494 0x40320498 0x4032049C 0x403204A0 0x403204A4 0x403204A8 0x403204AC 0x403204B0 0x40320500 0x40320504 0x40320508 0x4032050C 0x40320510 0x40320514 0x40320518 0x4032051C 0x40320520 0x40320524 0x40320528 0x4032052C 0x40320530 0x40320580 0x40320584 0x40320588 0x4032058C 0x40320590 0x40320594 0x40320598 0x4032059C 0x403205A0 0x403205A4
Description Port interrupt masked status register. See GPIO_PRT2_INTR_MASKED for the details of bit fields. Port interrupt set register. See GPIO_PRT2_INTR_SET for the details of bit fields. Port interrupt configuration register. See GPIO_PRT2_INTR_CFG for the details of bit fields. Port configuration register. See GPIO_PRT2_CFG for the details of bit fields. Port input buffer configuration register. See GPIO_PRT2_CFG_IN for the details of bit fields. Port output buffer configuration register. See GPIO_PRT2_CFG_OUT for the details of bit fields. Port output data register. See GPIO_PRT2_OUT for the details of bit fields. Port output data clear register. See GPIO_PRT0_OUT_CLR for the details of bit fields. Port output data set register. See GPIO_PRT0_OUT_SET for the details of bit fields. Port output data invert register. See GPIO_PRT0_OUT_INV for the details of bit fields. Port input state register. See GPIO_PRT2_IN for the details of bit fields. Port interrupt status register. See GPIO_PRT2_INTR for the details of bit fields. Port interrupt mask register. See GPIO_PRT2_INTR_MASK for the details of bit fields. Port interrupt masked status register. See GPIO_PRT2_INTR_MASKED for the details of bit fields. Port interrupt set register. See GPIO_PRT2_INTR_SET for the details of bit fields. Port interrupt configuration register. See GPIO_PRT2_INTR_CFG for the details of bit fields. Port configuration register. See GPIO_PRT2_CFG for the details of bit fields. Port input buffer configuration register. See GPIO_PRT2_CFG_IN for the details of bit fields. Port output buffer configuration register. See GPIO_PRT2_CFG_OUT for the details of bit fields. Port output data register. See GPIO_PRT2_OUT for the details of bit fields. Port output data clear register. See GPIO_PRT0_OUT_CLR for the details of bit fields. Port output data set register. See GPIO_PRT0_OUT_SET for the details of bit fields. Port output data invert register. See GPIO_PRT0_OUT_INV for the details of bit fields. Port input state register. See GPIO_PRT2_IN for the details of bit fields. Port interrupt status register. See GPIO_PRT2_INTR for the details of bit fields. Port interrupt mask register. See GPIO_PRT2_INTR_MASK for the details of bit fields. Port interrupt masked status register. See GPIO_PRT2_INTR_MASKED for the details of bit fields. Port interrupt set register. See GPIO_PRT2_INTR_SET for the details of bit fields. Port interrupt configuration register. See GPIO_PRT2_INTR_CFG for the details of bit fields. Port configuration register. See GPIO_PRT2_CFG for the details of bit fields. Port input buffer configuration register. See GPIO_PRT2_CFG_IN for the details of bit fields. Port output buffer configuration register. See GPIO_PRT2_CFG_OUT for the details of bit fields. Port output data register. See GPIO_PRT2_OUT for the details of bit fields. Port output data clear register. See GPIO_PRT0_OUT_CLR for the details of bit fields. Port output data set register. See GPIO_PRT0_OUT_SET for the details of bit fields. Port output data invert register. See GPIO_PRT0_OUT_INV for the details of bit fields. Port input state register. See GPIO_PRT2_IN for the details of bit fields. Port interrupt status register. See GPIO_PRT2_INTR for the details of bit fields. Port interrupt mask register. See GPIO_PRT2_INTR_MASK for the details of bit fields. Port interrupt masked status register. See GPIO_PRT2_INTR_MASKED for the details of bit fields. Port interrupt set register. See GPIO_PRT2_INTR_SET for the details of bit fields. Port interrupt configuration register. See GPIO_PRT2_INTR_CFG for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
708
General Purpose I/O (GPIO) Registers
Register GPIO_PRT11_CFG GPIO_PRT11_CFG_IN GPIO_PRT11_CFG_OUT GPIO_PRT12_OUT GPIO_PRT12_OUT_CLR GPIO_PRT12_OUT_SET GPIO_PRT12_OUT_INV GPIO_PRT12_IN GPIO_PRT12_INTR GPIO_PRT12_INTR_MASK GPIO_PRT12_INTR_MASKED GPIO_PRT12_INTR_SET GPIO_PRT12_INTR_CFG GPIO_PRT12_CFG GPIO_PRT12_CFG_IN GPIO_PRT12_CFG_OUT GPIO_PRT13_OUT GPIO_PRT13_OUT_CLR GPIO_PRT13_OUT_SET GPIO_PRT13_OUT_INV GPIO_PRT13_IN GPIO_PRT13_INTR GPIO_PRT13_INTR_MASK GPIO_PRT13_INTR_MASKED GPIO_PRT13_INTR_SET GPIO_PRT13_INTR_CFG GPIO_PRT13_CFG GPIO_PRT13_CFG_IN GPIO_PRT13_CFG_OUT GPIO_PRT14_OUT GPIO_PRT14_OUT_CLR GPIO_PRT14_OUT_SET GPIO_PRT14_OUT_INV GPIO_PRT14_IN GPIO_PRT14_INTR GPIO_PRT14_INTR_MASK GPIO_PRT14_INTR_MASKED GPIO_PRT14_INTR_SET GPIO_PRT14_INTR_CFG GPIO_PRT14_CFG GPIO_INTR_CAUSE0 GPIO_VDD_ACTIVE
Address 0x403205A8 0x403205AC 0x403205B0 0x40320600 0x40320604 0x40320608 0x4032060C 0x40320610 0x40320614 0x40320618 0x4032061C 0x40320620 0x40320624 0x40320628 0x4032062C 0x40320630 0x40320680 0x40320684 0x40320688 0x4032068C 0x40320690 0x40320694 0x40320698 0x4032069C 0x403206A0 0x403206A4 0x403206A8 0x403206AC 0x403206B0 0x40320700 0x40320704 0x40320708 0x4032070C 0x40320710 0x40320714 0x40320718 0x4032071C 0x40320720 0x40320724 0x40320728 0x40324000 0x40324010
Description Port configuration register. See GPIO_PRT2_CFG for the details of bit fields. Port input buffer configuration register. See GPIO_PRT2_CFG_IN for the details of bit fields. Port output buffer configuration register. See GPIO_PRT2_CFG_OUT for the details of bit fields. Port output data register. See GPIO_PRT2_OUT for the details of bit fields. Port output data clear register. See GPIO_PRT0_OUT_CLR for the details of bit fields. Port output data set register. See GPIO_PRT0_OUT_SET for the details of bit fields. Port output data invert register. See GPIO_PRT0_OUT_INV for the details of bit fields. Port input state register. See GPIO_PRT2_IN for the details of bit fields. Port interrupt status register. See GPIO_PRT2_INTR for the details of bit fields. Port interrupt mask register. See GPIO_PRT2_INTR_MASK for the details of bit fields. Port interrupt masked status register. See GPIO_PRT2_INTR_MASKED for the details of bit fields. Port interrupt set register. See GPIO_PRT2_INTR_SET for the details of bit fields. Port interrupt configuration register. See GPIO_PRT2_INTR_CFG for the details of bit fields. Port configuration register. See GPIO_PRT2_CFG for the details of bit fields. Port input buffer configuration register. See GPIO_PRT2_CFG_IN for the details of bit fields. Port output buffer configuration register. See GPIO_PRT2_CFG_OUT for the details of bit fields. Port output data register. See GPIO_PRT2_OUT for the details of bit fields. Port output data clear register. See GPIO_PRT0_OUT_CLR for the details of bit fields. Port output data set register. See GPIO_PRT0_OUT_SET for the details of bit fields. Port output data invert register. See GPIO_PRT0_OUT_INV for the details of bit fields. Port input state register. See GPIO_PRT2_IN for the details of bit fields. Port interrupt status register. See GPIO_PRT2_INTR for the details of bit fields. Port interrupt mask register. See GPIO_PRT2_INTR_MASK for the details of bit fields. Port interrupt masked status register. See GPIO_PRT2_INTR_MASKED for the details of bit fields. Port interrupt set register. See GPIO_PRT2_INTR_SET for the details of bit fields. Port interrupt configuration register. See GPIO_PRT2_INTR_CFG for the details of bit fields. Port configuration register. See GPIO_PRT2_CFG for the details of bit fields. Port input buffer configuration register. See GPIO_PRT2_CFG_IN for the details of bit fields. Port output buffer configuration register. See GPIO_PRT2_CFG_OUT for the details of bit fields. Port output data register Port output data clear register. See GPIO_PRT0_OUT_CLR for the details of bit fields. Port output data set register. See GPIO_PRT0_OUT_SET for the details of bit fields. Port output data invert register. See GPIO_PRT0_OUT_INV for the details of bit fields. Port input state register Port interrupt status register Port interrupt mask register Port interrupt masked status register Port interrupt set register Port interrupt configuration register Port configuration register Interrupt port cause register 0 Extern power supply detection register
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
709
General Purpose I/O (GPIO) Registers
Register GPIO_VDD_INTR GPIO_VDD_INTR_MASK GPIO_VDD_INTR_MASKED .GPIO_VDD_INTR_SET
Address 0x40324014 0x40324018 0x4032401C 0x40324020
Supply detection interrupt register Supply detection interrupt mask register Supply detection interrupt masked register Supply detection interrupt set register
Description
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
710
GPIO_PRT0_OUT
16.1.1 GPIO_PRT0_OUT
Address = 0x40320000 Port output data register Address: 0x40320000 Retention: Retained
Bits SW Access HW Access
Name
7
6
None
None
None [7:6]
Bits
15
14
SW Access
HW Access
Name
Bits
23
22
SW Access
HW Access
Name
Bits
31
30
SW Access
HW Access
Name
5 RW RW OUT5 13
21
29
4 RW RW OUT4
3 RW RW OUT3
12
11
None
None
None [15:8]
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
2 RW RW OUT2 10
18
26
1 RW RW OUT1
9
17
25
0 RW RW OUT0
8
16
24
Bits
Name
5
OUT5
4
OUT4
3
OUT3
2
OUT2
1
OUT1
0
OUT0
Description
IO output data for pin 5 Default Value: 0
IO output data for pin 4 Default Value: 0
IO output data for pin 3 Default Value: 0
IO output data for pin 2 Default Value: 0
IO output data for pin 1 Default Value: 0
IO output data for pin 0 '0': Output state set to '0' '1': Output state set to '1' Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
711
GPIO_PRT0_OUT_CLR
16.1.2 GPIO_PRT0_OUT_CLR
Address = 0x40320004 Port output data clear register Address: 0x40320004 Retention: Retained
Bits SW Access HW Access
Name
7 RW A OUT7
6 RW A OUT6
5 RW A OUT5
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4 RW A OUT4
3 RW A OUT3
12
11
None
None
None [15:8]
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
2 RW A OUT2 10
18
26
1 RW A OUT1
9
17
25
0 RW A OUT0
8
16
24
Bits
Name
7
OUT7
6
OUT6
5
OUT5
4
OUT4
3
OUT3
2
OUT2
1
OUT1
Description
IO clear output for pin 7 Default Value: 0
IO clear output for pin 6 Default Value: 0
IO clear output for pin 5 Default Value: 0
IO clear output for pin 4 Default Value: 0
IO clear output for pin 3 Default Value: 0
IO clear output for pin 2 Default Value: 0
IO clear output for pin 1 Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
712
16.1.2
0
GPIO_PRT0_OUT_CLR (continued)
OUT0
IO clear output for pin 0: '0': Output state not affected. '1': Output state set to '0'. Default Value: 0
GPIO_PRT0_OUT_CLR
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
713
GPIO_PRT0_OUT_SET
16.1.3 GPIO_PRT0_OUT_SET
Address = 0x40320008 Port output data set register Address: 0x40320008 Retention: Retained
Bits SW Access HW Access
Name
7 RW A OUT7
6 RW A OUT6
5 RW A OUT5
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4 RW A OUT4
3 RW A OUT3
12
11
None
None
None [15:8]
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
2 RW A OUT2 10
18
26
1 RW A OUT1
9
17
25
0 RW A OUT0
8
16
24
Bits
Name
7
OUT7
6
OUT6
5
OUT5
4
OUT4
3
OUT3
2
OUT2
1
OUT1
Description
IO set output for pin 7 Default Value: 0
IO set output for pin 6 Default Value: 0
IO set output for pin 5 Default Value: 0
IO set output for pin 4 Default Value: 0
IO set output for pin 3 Default Value: 0
IO set output for pin 2 Default Value: 0
IO set output for pin 1 Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
714
16.1.3
0
GPIO_PRT0_OUT_SET (continued)
OUT0
IO set output for pin 0: '0': Output state not affected. '1': Output state set to '1'. Default Value: 0
GPIO_PRT0_OUT_SET
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
715
GPIO_PRT0_OUT_INV
16.1.4 GPIO_PRT0_OUT_INV
Address = 0x4032000C Port output data invert register Address: 0x4032000C Retention: Retained
Bits SW Access HW Access
Name
7 RW A OUT7
6 RW A OUT6
5 RW A OUT5
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4 RW A OUT4
3 RW A OUT3
12
11
None
None
None [15:8]
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
2 RW A OUT2 10
18
26
1 RW A OUT1
9
17
25
0 RW A OUT0
8
16
24
Bits
Name
7
OUT7
6
OUT6
5
OUT5
4
OUT4
3
OUT3
2
OUT2
1
OUT1
Description
IO invert output for pin 7 Default Value: 0
IO invert output for pin 6 Default Value: 0
IO invert output for pin 5 Default Value: 0
IO invert output for pin 4 Default Value: 0
IO invert output for pin 3 Default Value: 0
IO invert output for pin 2 Default Value: 0
IO invert output for pin 1 Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
716
16.1.4
0
GPIO_PRT0_OUT_INV (continued)
OUT0
IO invert output for pin 0: '0': Output state not affected. '1': Output state inverted ('0' => '1', '1' => '0'). Default Value: 0
GPIO_PRT0_OUT_INV
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
717
GPIO_PRT0_IN
16.1.5 GPIO_PRT0_IN
Address = 0x40320010 Port input state register Address: 0x40320010 Retention: Not Retained
Bits SW Access HW Access
Name
7
6
None
None
None [7:6]
5
4
3
2
1
0
R
R
R
R
R
R
W
W
W
W
W
W
IN5
IN4
IN3
IN2
IN1
IN0
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:9]
9
8
R
W
FLT_IN
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
8
FLT_IN
5
IN5
4
IN4
3
IN3
2
IN2
1
IN1
0
IN0
Description
Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register. Default Value: 0
IO pin state for pin 5 Default Value: 0
IO pin state for pin 4 Default Value: 0
IO pin state for pin 3 Default Value: 0
IO pin state for pin 2 Default Value: 0
IO pin state for pin 1 Default Value: 0
IO pin state for pin 0 '0': Low logic level present on pin. '1': High logic level present on pin. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
718
GPIO_PRT0_INTR
16.1.6 GPIO_PRT0_INTR
Address = 0x40320014 Port interrupt status register Address: 0x40320014 Retention: Retained
Bits SW Access HW Access
Name
7
6
None
None
None [7:6]
5 RW1C
A EDGE5
4 RW1C
A EDGE4
3 RW1C
A EDGE3
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:9]
Bits SW Access HW Access
Name
23
22
None
None
None [23:22]
21 R W IN_IN5
20 R W IN_IN4
19 R W IN_IN3
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:25]
2 RW1C
A EDGE2
10
18 R W IN_IN2 26
1 RW1C
A EDGE1
9
17 R W IN_IN1 25
0 RW1C
A EDGE0
8 RW1C
A FLT_EDGE
16 R W IN_IN0
24 R W FLT_IN_IN
Bits
Name
24
FLT_IN_IN
21
IN_IN5
20
IN_IN4
19
IN_IN3
18
IN_IN2
17
IN_IN1
16
IN_IN0
8
FLT_EDGE
Description
Filtered pin state for pin selected by INTR_CFG.FLT_SEL Default Value: 0
IO pin state for pin 5 Default Value: 0
IO pin state for pin 4 Default Value: 0
IO pin state for pin 3 Default Value: 0
IO pin state for pin 2 Default Value: 0
IO pin state for pin 1 Default Value: 0
IO pin state for pin 0 Default Value: 0
Edge detected on filtered pin selected by INTR_CFG.FLT_SEL Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
719
16.1.6
5 4 3 2 1 0
GPIO_PRT0_INTR (continued)
EDGE5 EDGE4 EDGE3 EDGE2 EDGE1 EDGE0
Edge detect for IO pin 5 Default Value: 0
Edge detect for IO pin 4 Default Value: 0
Edge detect for IO pin 3 Default Value: 0
Edge detect for IO pin 2 Default Value: 0
Edge detect for IO pin 1 Default Value: 0
Edge detect for IO pin 0 '0': No edge was detected on pin. '1': An edge was detected on pin. Default Value: 0
GPIO_PRT0_INTR
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
720
GPIO_PRT0_INTR_MASK
16.1.7 GPIO_PRT0_INTR_MASK
Address = 0x40320018 Port interrupt mask register Address: 0x40320018 Retention: Retained
Bits SW Access HW Access
Name
7
6
None
None
None [7:6]
5 RW R EDGE5
4 RW R EDGE4
3 RW R EDGE3
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:9]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2 RW R EDGE2 10
18
26
1 RW R EDGE1
9
17
0 RW R EDGE0
8 RW R FLT_EDGE
16
25
24
Bits
Name
8
FLT_EDGE
5
EDGE5
4
EDGE4
3
EDGE3
2
EDGE2
1
EDGE1
0
EDGE0
Description
Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL Default Value: 0
Masks edge interrupt on IO pin 5 Default Value: 0
Masks edge interrupt on IO pin 4 Default Value: 0
Masks edge interrupt on IO pin 3 Default Value: 0
Masks edge interrupt on IO pin 2 Default Value: 0
Masks edge interrupt on IO pin 1 Default Value: 0
Masks edge interrupt on IO pin 0 '0': Pin interrupt forwarding disabled '1': Pin interrupt forwarding enabled Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
721
GPIO_PRT0_INTR_MASKED
16.1.8 GPIO_PRT0_INTR_MASKED
Address = 0x4032001C Port interrupt masked status register Address: 0x4032001C Retention: Retained
Bits SW Access HW Access
Name
7
6
None
None
None [7:6]
5 R W EDGE5
4 R W EDGE4
3 R W EDGE3
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:9]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2 R W EDGE2 10
18
26
1 R W EDGE1 9
17
0 R W EDGE0
8 R W FLT_EDGE
16
25
24
Bits
Name
8
FLT_EDGE
5
EDGE5
4
EDGE4
3
EDGE3
2
EDGE2
1
EDGE1
0
EDGE0
Description
Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL Default Value: 0
Edge detected and masked on IO pin 5 Default Value: 0
Edge detected and masked on IO pin 4 Default Value: 0
Edge detected and masked on IO pin 3 Default Value: 0
Edge detected and masked on IO pin 2 Default Value: 0
Edge detected and masked on IO pin 1 Default Value: 0
Edge detected AND masked on IO pin 0 '0': Interrupt was not forwarded to CPU '1': Interrupt occurred and was forwarded to CPU Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
722
GPIO_PRT0_INTR_SET
16.1.9
GPIO_PRT0_INTR_SET (continued)
16.1.9 GPIO_PRT0_INTR_SET
Address = 0x40320020 Port interrupt set register Address: 0x40320020 Retention: Retained
Bits SW Access HW Access
Name
7
6
None
None
None [7:6]
5 RW1S
A EDGE5
4 RW1S
A EDGE4
3 RW1S
A EDGE3
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:9]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2 RW1S
A EDGE2
10
18
26
1 RW1S
A EDGE1
9
17
0 RW1S
A EDGE0
8 RW1S
A FLT_EDGE
16
25
24
Bits
Name
8
FLT_EDGE
5
EDGE5
4
EDGE4
3
EDGE3
2
EDGE2
1
EDGE1
Description
Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL Default Value: 0
Sets edge detect interrupt for IO pin 5 Default Value: 0
Sets edge detect interrupt for IO pin 4 Default Value: 0
Sets edge detect interrupt for IO pin 3 Default Value: 0
Sets edge detect interrupt for IO pin 2 Default Value: 0
Sets edge detect interrupt for IO pin 1 Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
723
16.1.9
0
GPIO_PRT0_INTR_SET (continued)
EDGE0
Sets edge detect interrupt for IO pin 0 '0': Interrupt state not affected '1': Interrupt set Default Value: 0
GPIO_PRT0_INTR_SET
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
724
GPIO_PRT0_INTR_CFG
16.1.10 GPIO_PRT0_INTR_CFG
Address = 0x40320024 Port interrupt configuration register Address: 0x40320024 Retention: Retained
Bits SW Access HW Access
Name
7
6
RW
R
EDGE3_SEL [7:6]
5
4
RW
R
EDGE2_SEL [5:4]
3
2
RW
R
EDGE1_SEL [3:2]
Bits
15
SW Access
HW Access
Name
14
13
None
None
None [15:12]
12
11
10
RW
R
EDGE5_SEL [11:10]
Bits SW Access HW Access
Name
23
22
21
None
None
None [23:21]
20
19
18
RW
R
FLT_SEL [20:18]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
1
0
RW
R
EDGE0_SEL [1:0]
9
8
RW
R
EDGE4_SEL [9:8]
17
16
RW
R
FLT_EDGE_SEL [17:16]
25
24
Bits 20 : 18
17 : 16
Name FLT_SEL
FLT_EDGE_SEL
Description Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt. Default Value: 0 Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL Default Value: 0 0x0: DISABLE : Disabled
0x1: RISING : Rising edge
0x2: FALLING : Falling edge
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
725
16.1.10
GPIO_PRT0_INTR_CFG (continued)
0x3: BOTH : Both rising and falling edges
11 : 10 9 : 8 7 : 6 5 : 4 3 : 2 1 : 0
EDGE5_SEL EDGE4_SEL EDGE3_SEL EDGE2_SEL EDGE1_SEL EDGE0_SEL
Sets which edge will trigger an IRQ for IO pin 5 Default Value: 0
Sets which edge will trigger an IRQ for IO pin 4 Default Value: 0
Sets which edge will trigger an IRQ for IO pin 3 Default Value: 0
Sets which edge will trigger an IRQ for IO pin 2 Default Value: 0
Sets which edge will trigger an IRQ for IO pin 1 Default Value: 0
Sets which edge will trigger an IRQ for IO pin 0 Default Value: 0
0x0: DISABLE :
Disabled
0x1: RISING : Rising edge
0x2: FALLING : Falling edge
0x3: BOTH : Both rising and falling edges
GPIO_PRT0_INTR_CFG
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
726
GPIO_PRT0_CFG
16.1.11 GPIO_PRT0_CFG
Address = 0x40320028 Port configuration register Address: 0x40320028 Retention: Retained
Bits SW Access HW Access
Name
7 RW R IN_EN1
6
5
4
RW
R
DRIVE_MODE1 [6:4]
3 RW R IN_EN0
Bits SW Access HW Access
Name
15 RW R IN_EN3
14
13
12
RW
R
DRIVE_MODE3 [14:12]
11 RW R IN_EN2
Bits SW Access HW Access
Name
23 RW R IN_EN5
22
21
20
RW
R
DRIVE_MODE5 [22:20]
19 RW R IN_EN4
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
Bits 23 22 : 20 19 18 : 16 15 14 : 12 11 10 : 8
Name IN_EN5 DRIVE_MODE5 IN_EN4 DRIVE_MODE4 IN_EN3 DRIVE_MODE3 IN_EN2 DRIVE_MODE2
Description
Enables the input buffer for IO pin 5 Default Value: 0
The GPIO drive mode for IO pin 5 Default Value: 0
Enables the input buffer for IO pin 4 Default Value: 0
The GPIO drive mode for IO pin4 Default Value: 0
Enables the input buffer for IO pin 3 Default Value: 0
The GPIO drive mode for IO pin 3 Default Value: 0
Enables the input buffer for IO pin 2 Default Value: 0
The GPIO drive mode for IO pin 2 Default Value: 0
2
1
0
RW
R
DRIVE_MODE0 [2:0]
10
9
8
RW
R
DRIVE_MODE2 [10:8]
18
17
16
RW
R
DRIVE_MODE4 [18:16]
26
25
24
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
727
GPIO_PRT0_CFG
16.1.11 GPIO_PRT0_CFG (continued)
7
IN_EN1
6 : 4
DRIVE_MODE1
3
IN_EN0
2 : 0
DRIVE_MODE0
Enables the input buffer for IO pin 1 Default Value: 0
The GPIO drive mode for IO pin 1 Default Value: 0
Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue. '0': Input buffer disabled '1': Input buffer enabled Default Value: 0
The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode. Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured before turning the IO on here to avoid producing glitches on the bus. Note: that peripherals other than GPIO & UDB/DSI directly control both the output and outputenable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0'). Note: D_OUT, D_OUT_EN are pins of GPIO cell. Default Value: 0
0x0: HIGHZ :
Output buffer is off creating a high impedance input D_OUT = '0': High Impedance D_OUT = '1': High Impedance
0x1: RESERVED :
This mode is reserved and should not be used. No damage will occur if this mode is selected. The pin will generally perform the same as the STRONG drive mode although this is not guaranteed for all use cases. For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
728
16.1.11
GPIO_PRT0_CFG (continued)
0x2: PULLUP :
Resistive pull up For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Weak/resistive pull up When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': Weak/resistive pull up D_OUT = '1': Weak/resistive pull up
0x3: PULLDOWN :
Resistive pull down For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': Weak/resistive pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': Weak/resistive pull down D_OUT = '1': Weak/resistive pull down
0x4: OD_DRIVESLOW :
Open drain, drives low For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': High Impedance When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High Impedance D_OUT = '1': High Impedance
GPIO_PRT0_CFG
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
729
GPIO_PRT0_CFG
16.1.11
GPIO_PRT0_CFG (continued)
0x5: OD_DRIVESHIGH :
Open drain, drives high For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': High Impedance D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High Impedance D_OUT = '1': High Impedance
0x6: STRONG :
Strong D_OUTput buffer For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High Impedance D_OUT = '1': High Impedance
0x7: PULLUP_DOWN :
Pull up or pull down For GPIO & UDB/DSI peripherals: When D_OUT_EN = '0': GPIO_DSI_OUT = '0': Weak/resistive pull down GPIO_DSI_OUT = '1': Weak/resistive pull up where "GPIO_DSI_OUT" is a function of PORT_SEL, OUT & DSI_DATA_OUT. For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': Weak/resistive pull down D_OUT = '1': Weak/resistive pull up
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
730
GPIO_PRT0_CFG_IN
16.1.12 GPIO_PRT0_CFG_IN
Address = 0x4032002C Port input buffer configuration register Address: 0x4032002C Retention: Retained
Bits SW Access HW Access
Name
7
6
None
None
None [7:6]
5
RW
R
VTRIP_SEL5_0
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4
RW
R
VTRIP_SEL4_0
3
RW
R
VTRIP_SEL3_0
12
11
None
None
None [15:8]
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
2 RW R VTRIP_SEL2_0 10
18
26
1 RW R VTRIP_SEL1_0
9
17
25
0 RW R VTRIP_SEL0_0
8
16
24
Bits
Name
5
VTRIP_SEL5_0
4
VTRIP_SEL4_0
3
VTRIP_SEL3_0
2
VTRIP_SEL2_0
1
VTRIP_SEL1_0
0
VTRIP_SEL0_0
Description
Configures the pin 5 input buffer mode (trip points and hysteresis) Default Value: 0
Configures the pin 4 input buffer mode (trip points and hysteresis) Default Value: 0
Configures the pin 3 input buffer mode (trip points and hysteresis) Default Value: 0
Configures the pin 2 input buffer mode (trip points and hysteresis) Default Value: 0
Configures the pin 1 input buffer mode (trip points and hysteresis) Default Value: 0
Configures the pin 0 input buffer mode (trip points and hysteresis) Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
731
GPIO_PRT0_CFG_IN
16.1.12
GPIO_PRT0_CFG_IN (continued)
0x0: CMOS :
S40E: {CFG_IN_GPIO5V.VTRIP_SEL0_1, CFG_IN.VTRIP_SEL0_0} 0,0: CMOS 0,1: TTL 1,0: input buffer is compatible with automotive. 1,1: input buffer is compatible with automotvie
0x1: TTL :
S40S: Input buffer compatible with TTL and MediaLB interfaces
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
732
GPIO_PRT0_CFG_OUT
16.1.13 GPIO_PRT0_CFG_OUT
Address = 0x40320030 Port output buffer configuration register Address: 0x40320030 Retention: Retained
Bits SW Access HW Access
Name
7
6
None
None
None [7:6]
5 RW R SLOW5
4 RW R SLOW4
3 RW R SLOW3
2 RW R SLOW2
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits SW Access HW Access
Name
23
22
RW
R
DRIVE_SEL3 [23:22]
21
20
RW
R
DRIVE_SEL2 [21:20]
19
18
RW
R
DRIVE_SEL1 [19:18]
Bits
31
SW Access
HW Access
Name
30
29
None
None
None [31:28]
28
27
26
RW
R
DRIVE_SEL5 [27:26]
1 RW R SLOW1
9
0 RW R SLOW0
8
17
16
RW
R
DRIVE_SEL0 [17:16]
25
24
RW
R
DRIVE_SEL4 [25:24]
Bits 27 : 26 25 : 24 23 : 22 21 : 20 19 : 18 17 : 16
Name DRIVE_SEL5 DRIVE_SEL4 DRIVE_SEL3 DRIVE_SEL2 DRIVE_SEL1 DRIVE_SEL0
Description
Sets the GPIO drive strength for IO pin 5 Default Value: 0
Sets the GPIO drive strength for IO pin 4 Default Value: 0
Sets the GPIO drive strength for IO pin 3 Default Value: 0
Sets the GPIO drive strength for IO pin 2 Default Value: 0
Sets the GPIO drive strength for IO pin 1 Default Value: 0
Sets the GPIO drive strength for IO pin 0 Default Value: 0
0x0: FULL_DRIVE :
Full drive strength: GPIO drives current at its max rated spec.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
733
GPIO_PRT0_CFG_OUT
16.1.13
GPIO_PRT0_CFG_OUT (continued)
0x1: ONE_HALF_DRIVE : 1/2 drive strength: GPIO drives current at 1/2 of its max rated spec
0x2: ONE_QUARTER_DRIVE : 1/4 drive strength: GPIO drives current at 1/4 of its max rated spec.
0x3: ONE_EIGHTH_DRIVE : 1/8 drive strength: GPIO drives current at 1/8 of its max rated spec.
5
SLOW5
4
SLOW4
3
SLOW3
2
SLOW2
1
SLOW1
0
SLOW0
Enables slow slew rate for IO pin 5 Default Value: 0
Enables slow slew rate for IO pin 4 Default Value: 0
Enables slow slew rate for IO pin 3 Default Value: 0
Enables slow slew rate for IO pin 2 Default Value: 0
Enables slow slew rate for IO pin 1 Default Value: 0
Enables slow slew rate for IO pin 0 '0': Fast slew rate '1': Slow slew rate Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
734
GPIO_PRT2_OUT
16.1.14 GPIO_PRT2_OUT
Address = 0x40320100 Port output data register Address: 0x40320100 Retention: Retained
Bits SW Access HW Access
Name
7 RW RW OUT7
6 RW RW OUT6
Bits
15
14
SW Access
HW Access
Name
Bits
23
22
SW Access
HW Access
Name
Bits
31
30
SW Access
HW Access
Name
5 RW RW OUT5 13
21
29
4 RW RW OUT4
3 RW RW OUT3
12
11
None
None
None [15:8]
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
2 RW RW OUT2 10
18
26
1 RW RW OUT1
9
17
25
0 RW RW OUT0
8
16
24
Bits
Name
7
OUT7
6
OUT6
5
OUT5
4
OUT4
3
OUT3
2
OUT2
1
OUT1
Description
IO output data for pin 7 Default Value: 0
IO output data for pin 6 Default Value: 0
IO output data for pin 5 Default Value: 0
IO output data for pin 4 Default Value: 0
IO output data for pin 3 Default Value: 0
IO output data for pin 2 Default Value: 0
IO output data for pin 1 Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
735
16.1.14 GPIO_PRT2_OUT (continued)
0
OUT0
IO output data for pin 0 '0': Output state set to '0' '1': Output state set to '1' Default Value: 0
GPIO_PRT2_OUT
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
736
GPIO_PRT2_IN
16.1.15 GPIO_PRT2_IN
Address = 0x40320110 Port input state register Address: 0x40320110 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
R
R
R
R
R
R
R
HW Access
W
W
W
W
W
W
W
W
Name
IN7
IN6
IN5
IN4
IN3
IN2
IN1
IN0
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:9]
9
8
R
W
FLT_IN
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
8
FLT_IN
7
IN7
6
IN6
5
IN5
4
IN4
3
IN3
2
IN2
Description
Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register. Default Value: 0
IO pin state for pin 7 Default Value: 0
IO pin state for pin 6 Default Value: 0
IO pin state for pin 5 Default Value: 0
IO pin state for pin 4 Default Value: 0
IO pin state for pin 3 Default Value: 0
IO pin state for pin 2 Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
737
16.1.15 GPIO_PRT2_IN (continued)
1
IN1
0
IN0
IO pin state for pin 1 Default Value: 0
IO pin state for pin 0 '0': Low logic level present on pin. '1': High logic level present on pin. Default Value: 0
GPIO_PRT2_IN
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
738
GPIO_PRT2_INTR
16.1.16 GPIO_PRT2_INTR
Address = 0x40320114 Port interrupt status register Address: 0x40320114 Retention: Retained
Bits SW Access HW Access
Name
7 RW1C
A EDGE7
6 RW1C
A EDGE6
5 RW1C
A EDGE5
4 RW1C
A EDGE4
3 RW1C
A EDGE3
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:9]
Bits SW Access HW Access
Name
23 R W IN_IN7
22 R W IN_IN6
21 R W IN_IN5
20 R W IN_IN4
19 R W IN_IN3
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:25]
2 RW1C
A EDGE2
10
18 R W IN_IN2 26
1 RW1C
A EDGE1
9
17 R W IN_IN1 25
0 RW1C
A EDGE0
8 RW1C
A FLT_EDGE
16 R W IN_IN0
24 R W FLT_IN_IN
Bits
Name
24
FLT_IN_IN
23
IN_IN7
22
IN_IN6
21
IN_IN5
20
IN_IN4
19
IN_IN3
18
IN_IN2
17
IN_IN1
Description
Filtered pin state for pin selected by INTR_CFG.FLT_SEL Default Value: 0
IO pin state for pin 7 Default Value: 0
IO pin state for pin 6 Default Value: 0
IO pin state for pin 5 Default Value: 0
IO pin state for pin 4 Default Value: 0
IO pin state for pin 3 Default Value: 0
IO pin state for pin 2 Default Value: 0
IO pin state for pin 1 Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
739
GPIO_PRT2_INTR
16.1.16 GPIO_PRT2_INTR (continued)
16
IN_IN0
8
FLT_EDGE
7
EDGE7
6
EDGE6
5
EDGE5
4
EDGE4
3
EDGE3
2
EDGE2
1
EDGE1
0
EDGE0
IO pin state for pin 0 Default Value: 0
Edge detected on filtered pin selected by INTR_CFG.FLT_SEL Default Value: 0
Edge detect for IO pin 7 Default Value: 0
Edge detect for IO pin 6 Default Value: 0
Edge detect for IO pin 5 Default Value: 0
Edge detect for IO pin 4 Default Value: 0
Edge detect for IO pin 3 Default Value: 0
Edge detect for IO pin 2 Default Value: 0
Edge detect for IO pin 1 Default Value: 0
Edge detect for IO pin 0 '0': No edge was detected on pin. '1': An edge was detected on pin. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
740
GPIO_PRT2_INTR_MASK
16.1.17 GPIO_PRT2_INTR_MASK
Address = 0x40320118 Port interrupt mask register Address: 0x40320118 Retention: Retained
Bits SW Access HW Access
Name
7 RW R EDGE7
6 RW R EDGE6
5 RW R EDGE5
4 RW R EDGE4
3 RW R EDGE3
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:9]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2 RW R EDGE2 10
18
26
1 RW R EDGE1
9
17
0 RW R EDGE0
8 RW R FLT_EDGE
16
25
24
Bits
Name
8
FLT_EDGE
7
EDGE7
6
EDGE6
5
EDGE5
4
EDGE4
3
EDGE3
2
EDGE2
1
EDGE1
Description
Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL Default Value: 0
Masks edge interrupt on IO pin 7 Default Value: 0
Masks edge interrupt on IO pin 6 Default Value: 0
Masks edge interrupt on IO pin 5 Default Value: 0
Masks edge interrupt on IO pin 4 Default Value: 0
Masks edge interrupt on IO pin 3 Default Value: 0
Masks edge interrupt on IO pin 2 Default Value: 0
Masks edge interrupt on IO pin 1 Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
741
16.1.17 GPIO_PRT2_INTR_MASK (continued)
0
EDGE0
Masks edge interrupt on IO pin 0 '0': Pin interrupt forwarding disabled '1': Pin interrupt forwarding enabled Default Value: 0
GPIO_PRT2_INTR_MASK
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
742
GPIO_PRT2_INTR_MASKED
16.1.18 GPIO_PRT2_INTR_MASKED
Address = 0x4032011C Port interrupt masked status register Address: 0x4032011C Retention: Retained
Bits SW Access HW Access
Name
7 R W EDGE7
6 R W EDGE6
5 R W EDGE5
4 R W EDGE4
3 R W EDGE3
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:9]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2 R W EDGE2 10
18
26
1 R W EDGE1 9
17
0 R W EDGE0
8 R W FLT_EDGE
16
25
24
Bits
Name
8
FLT_EDGE
7
EDGE7
6
EDGE6
5
EDGE5
4
EDGE4
3
EDGE3
2
EDGE2
1
EDGE1
Description
Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL Default Value: 0
Edge detected and masked on IO pin 7 Default Value: 0
Edge detected and masked on IO pin 6 Default Value: 0
Edge detected and masked on IO pin 5 Default Value: 0
Edge detected and masked on IO pin 4 Default Value: 0
Edge detected and masked on IO pin 3 Default Value: 0
Edge detected and masked on IO pin 2 Default Value: 0
Edge detected and masked on IO pin 1 Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
743
GPIO_PRT2_INTR_MASKED
16.1.18 GPIO_PRT2_INTR_MASKED (continued)
0
EDGE0
Edge detected AND masked on IO pin 0 '0': Interrupt was not forwarded to CPU '1': Interrupt occurred and was forwarded to CPU Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
744
GPIO_PRT2_INTR_SET
16.1.19 GPIO_PRT2_INTR_SET
Address = 0x40320120 Port interrupt set register Address: 0x40320120 Retention: Retained
Bits SW Access HW Access
Name
7 RW1S
A EDGE7
6 RW1S
A EDGE6
5 RW1S
A EDGE5
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4 RW1S
A EDGE4
3 RW1S
A EDGE3
12
11
None
None
None [15:9]
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
2 RW1S
A EDGE2
10
18
26
1 RW1S
A EDGE1
9
17
0 RW1S
A EDGE0
8 RW1S
A FLT_EDGE
16
25
24
Bits
Name
8
FLT_EDGE
7
EDGE7
6
EDGE6
5
EDGE5
4
EDGE4
3
EDGE3
2
EDGE2
1
EDGE1
Description
Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL Default Value: 0
Sets edge detect interrupt for IO pin 7 Default Value: 0
Sets edge detect interrupt for IO pin 6 Default Value: 0
Sets edge detect interrupt for IO pin 5 Default Value: 0
Sets edge detect interrupt for IO pin 4 Default Value: 0
Sets edge detect interrupt for IO pin 3 Default Value: 0
Sets edge detect interrupt for IO pin 2 Default Value: 0
Sets edge detect interrupt for IO pin 1 Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
745
16.1.19 GPIO_PRT2_INTR_SET (continued)
0
EDGE0
Sets edge detect interrupt for IO pin 0 '0': Interrupt state not affected '1': Interrupt set Default Value: 0
GPIO_PRT2_INTR_SET
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
746
GPIO_PRT2_INTR_CFG
16.1.20 GPIO_PRT2_INTR_CFG
Address = 0x40320124 Port interrupt configuration register Address: 0x40320124 Retention: Retained
Bits SW Access HW Access
Name
7
6
RW
R
EDGE3_SEL [7:6]
5
4
RW
R
EDGE2_SEL [5:4]
3
2
RW
R
EDGE1_SEL [3:2]
Bits SW Access HW Access
Name
15
14
RW
R
EDGE7_SEL [15:14]
13
12
RW
R
EDGE6_SEL [13:12]
11
10
RW
R
EDGE5_SEL [11:10]
Bits SW Access HW Access
Name
23
22
21
None
None
None [23:21]
20
19
18
RW
R
FLT_SEL [20:18]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
1
0
RW
R
EDGE0_SEL [1:0]
9
8
RW
R
EDGE4_SEL [9:8]
17
16
RW
R
FLT_EDGE_SEL [17:16]
25
24
Bits 20 : 18
17 : 16
Name FLT_SEL
FLT_EDGE_SEL
Description Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt. Default Value: 0 Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL Default Value: 0 0x0: DISABLE : Disabled
0x1: RISING : Rising edge
0x2: FALLING : Falling edge
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
747
16.1.20
GPIO_PRT2_INTR_CFG (continued)
0x3: BOTH : Both rising and falling edges
15 : 14 13 : 12 11 : 10 9 : 8 7 : 6 5 : 4 3 : 2 1 : 0
EDGE7_SEL EDGE6_SEL EDGE5_SEL EDGE4_SEL EDGE3_SEL EDGE2_SEL EDGE1_SEL EDGE0_SEL
Sets which edge will trigger an IRQ for IO pin 7 Default Value: 0
Sets which edge will trigger an IRQ for IO pin 6 Default Value: 0
Sets which edge will trigger an IRQ for IO pin 5 Default Value: 0
Sets which edge will trigger an IRQ for IO pin 4 Default Value: 0
Sets which edge will trigger an IRQ for IO pin 3 Default Value: 0
Sets which edge will trigger an IRQ for IO pin 2 Default Value: 0
Sets which edge will trigger an IRQ for IO pin 1 Default Value: 0
Sets which edge will trigger an IRQ for IO pin 0 Default Value: 0
0x0: DISABLE :
Disabled
0x1: RISING : Rising edge
0x2: FALLING : Falling edge
0x3: BOTH : Both rising and falling edges
GPIO_PRT2_INTR_CFG
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
748
GPIO_PRT2_CFG
16.1.21 GPIO_PRT2_CFG
Address = 0x40320128 Port configuration register Address: 0x40320128 Retention: Retained
Bits SW Access HW Access
Name
7 RW R IN_EN1
6
5
4
RW
R
DRIVE_MODE1 [6:4]
Bits SW Access HW Access
Name
15 RW R IN_EN3
14
13
12
RW
R
DRIVE_MODE3 [14:12]
Bits SW Access HW Access
Name
23 RW R IN_EN5
22
21
20
RW
R
DRIVE_MODE5 [22:20]
Bits SW Access HW Access
Name
31 RW R IN_EN7
30
29
28
RW
R
DRIVE_MODE7 [30:28]
3 RW R IN_EN0
11 RW R IN_EN2
19 RW R IN_EN4
27 RW R IN_EN6
Bits 31 30 : 28 27 26 : 24 23 22 : 20 19 18 : 16
Name IN_EN7 DRIVE_MODE7 IN_EN6 DRIVE_MODE6 IN_EN5 DRIVE_MODE5 IN_EN4 DRIVE_MODE4
Description
Enables the input buffer for IO pin 7 Default Value: 0
The GPIO drive mode for IO pin 7 Default Value: 0
Enables the input buffer for IO pin 6 Default Value: 0
The GPIO drive mode for IO pin 6 Default Value: 0
Enables the input buffer for IO pin 5 Default Value: 0
The GPIO drive mode for IO pin 5 Default Value: 0
Enables the input buffer for IO pin 4 Default Value: 0
The GPIO drive mode for IO pin4 Default Value: 0
2
1
0
RW
R
DRIVE_MODE0 [2:0]
10
9
8
RW
R
DRIVE_MODE2 [10:8]
18
17
16
RW
R
DRIVE_MODE4 [18:16]
26
25
24
RW
R
DRIVE_MODE6 [26:24]
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
749
GPIO_PRT2_CFG
16.1.21 GPIO_PRT2_CFG (continued)
15 14 : 12 11 10 : 8 7 6 : 4 3
IN_EN3 DRIVE_MODE3 IN_EN2 DRIVE_MODE2 IN_EN1 DRIVE_MODE1 IN_EN0
2 : 0
DRIVE_MODE0
Enables the input buffer for IO pin 3 Default Value: 0
The GPIO drive mode for IO pin 3 Default Value: 0
Enables the input buffer for IO pin 2 Default Value: 0
The GPIO drive mode for IO pin 2 Default Value: 0
Enables the input buffer for IO pin 1 Default Value: 0
The GPIO drive mode for IO pin 1 Default Value: 0
Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue. '0': Input buffer disabled '1': Input buffer enabled Default Value: 0
The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode. Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured before turning the IO on here to avoid producing glitches on the bus. Note: that peripherals other than GPIO & UDB/DSI directly control both the output and outputenable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0'). Note: D_OUT, D_OUT_EN are pins of GPIO cell. Default Value: 0
0x0: HIGHZ :
Output buffer is off creating a high impedance input D_OUT = '0': High Impedance D_OUT = '1': High Impedance
0x1: RESERVED :
This mode is reserved and should not be used. No damage will occur if this mode is selected. The pin will generally perform the same as the STRONG drive mode although this is not guaranteed for all use cases. For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
750
16.1.21
GPIO_PRT2_CFG (continued)
0x2: PULLUP :
Resistive pull up For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Weak/resistive pull up When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': Weak/resistive pull up D_OUT = '1': Weak/resistive pull up
0x3: PULLDOWN :
Resistive pull down For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': Weak/resistive pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': Weak/resistive pull down D_OUT = '1': Weak/resistive pull down
0x4: OD_DRIVESLOW :
Open drain, drives low For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': High Impedance When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High Impedance D_OUT = '1': High Impedance
GPIO_PRT2_CFG
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
751
GPIO_PRT2_CFG
16.1.21
GPIO_PRT2_CFG (continued)
0x5: OD_DRIVESHIGH :
Open drain, drives high For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': High Impedance D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High Impedance D_OUT = '1': High Impedance
0x6: STRONG :
Strong D_OUTput buffer For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High Impedance D_OUT = '1': High Impedance
0x7: PULLUP_DOWN :
Pull up or pull down For GPIO & UDB/DSI peripherals: When D_OUT_EN = '0': GPIO_DSI_OUT = '0': Weak/resistive pull down GPIO_DSI_OUT = '1': Weak/resistive pull up where "GPIO_DSI_OUT" is a function of PORT_SEL, OUT & DSI_DATA_OUT. For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': Weak/resistive pull down D_OUT = '1': Weak/resistive pull up
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
752
GPIO_PRT2_CFG_IN
16.1.22 GPIO_PRT2_CFG_IN
Address = 0x4032012C Port input buffer configuration register Address: 0x4032012C Retention: Retained
Bits SW Access HW Access
Name
7
RW
R
VTRIP_SEL7_0
6
RW
R
VTRIP_SEL6_0
5
RW
R
VTRIP_SEL5_0
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4
RW
R
VTRIP_SEL4_0
3
RW
R
VTRIP_SEL3_0
12
11
None
None
None [15:8]
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
2 RW R VTRIP_SEL2_0 10
18
26
1 RW R VTRIP_SEL1_0
9
17
25
0 RW R VTRIP_SEL0_0
8
16
24
Bits
Name
7
VTRIP_SEL7_0
6
VTRIP_SEL6_0
5
VTRIP_SEL5_0
4
VTRIP_SEL4_0
3
VTRIP_SEL3_0
2
VTRIP_SEL2_0
1
VTRIP_SEL1_0
Description
Configures the pin 7 input buffer mode (trip points and hysteresis) Default Value: 0
Configures the pin 6 input buffer mode (trip points and hysteresis) Default Value: 0
Configures the pin 5 input buffer mode (trip points and hysteresis) Default Value: 0
Configures the pin 4 input buffer mode (trip points and hysteresis) Default Value: 0
Configures the pin 3 input buffer mode (trip points and hysteresis) Default Value: 0
Configures the pin 2 input buffer mode (trip points and hysteresis) Default Value: 0
Configures the pin 1 input buffer mode (trip points and hysteresis) Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
753
GPIO_PRT2_CFG_IN
16.1.22 GPIO_PRT2_CFG_IN (continued)
0
VTRIP_SEL0_0
Configures the pin 0 input buffer mode (trip points and hysteresis) Default Value: 0
0x0: CMOS :
S40E: {CFG_IN_GPIO5V.VTRIP_SEL0_1, CFG_IN.VTRIP_SEL0_0} 0,0: CMOS 0,1: TTL 1,0: input buffer is compatible with automotive. 1,1: input buffer is compatible with automotvie
0x1: TTL : S40S: Input buffer compatible with TTL and MediaLB interfaces
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
754
GPIO_PRT2_CFG_OUT
16.1.23 GPIO_PRT2_CFG_OUT
Address = 0x40320130 Port output buffer configuration register Address: 0x40320130 Retention: Retained
Bits SW Access HW Access
Name
7 RW R SLOW7
6 RW R SLOW6
5 RW R SLOW5
4 RW R SLOW4
3 RW R SLOW3
2 RW R SLOW2
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits SW Access HW Access
Name
23
22
RW
R
DRIVE_SEL3 [23:22]
21
20
RW
R
DRIVE_SEL2 [21:20]
19
18
RW
R
DRIVE_SEL1 [19:18]
Bits SW Access HW Access
Name
31
30
RW
R
DRIVE_SEL7 [31:30]
29
28
RW
R
DRIVE_SEL6 [29:28]
27
26
RW
R
DRIVE_SEL5 [27:26]
1 RW R SLOW1
9
0 RW R SLOW0
8
17
16
RW
R
DRIVE_SEL0 [17:16]
25
24
RW
R
DRIVE_SEL4 [25:24]
Bits 31 : 30 29 : 28 27 : 26 25 : 24 23 : 22 21 : 20 19 : 18 17 : 16
Name DRIVE_SEL7 DRIVE_SEL6 DRIVE_SEL5 DRIVE_SEL4 DRIVE_SEL3 DRIVE_SEL2 DRIVE_SEL1 DRIVE_SEL0
Description
Sets the GPIO drive strength for IO pin 7 Default Value: 0
Sets the GPIO drive strength for IO pin 6 Default Value: 0
Sets the GPIO drive strength for IO pin 5 Default Value: 0
Sets the GPIO drive strength for IO pin 4 Default Value: 0
Sets the GPIO drive strength for IO pin 3 Default Value: 0
Sets the GPIO drive strength for IO pin 2 Default Value: 0
Sets the GPIO drive strength for IO pin 1 Default Value: 0
Sets the GPIO drive strength for IO pin 0 Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
755
GPIO_PRT2_CFG_OUT
16.1.23
GPIO_PRT2_CFG_OUT (continued)
0x0: FULL_DRIVE : Full drive strength: GPIO drives current at its max rated spec.
0x1: ONE_HALF_DRIVE : 1/2 drive strength: GPIO drives current at 1/2 of its max rated spec
0x2: ONE_QUARTER_DRIVE : 1/4 drive strength: GPIO drives current at 1/4 of its max rated spec.
0x3: ONE_EIGHTH_DRIVE : 1/8 drive strength: GPIO drives current at 1/8 of its max rated spec.
7
SLOW7
6
SLOW6
5
SLOW5
4
SLOW4
3
SLOW3
2
SLOW2
1
SLOW1
0
SLOW0
Enables slow slew rate for IO pin 7 Default Value: 0
Enables slow slew rate for IO pin 6 Default Value: 0
Enables slow slew rate for IO pin 5 Default Value: 0
Enables slow slew rate for IO pin 4 Default Value: 0
Enables slow slew rate for IO pin 3 Default Value: 0
Enables slow slew rate for IO pin 2 Default Value: 0
Enables slow slew rate for IO pin 1 Default Value: 0
Enables slow slew rate for IO pin 0 '0': Fast slew rate '1': Slow slew rate Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
756
GPIO_PRT4_OUT
16.1.24 GPIO_PRT4_OUT
Address = 0x40320200 Port output data register Address: 0x40320200 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:4]
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4
3
RW
RW
OUT3
12
11
None
None
None [15:8]
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
2 RW RW OUT2 10
18
26
1 RW RW OUT1
9
17
25
0 RW RW OUT0
8
16
24
Bits
Name
3
OUT3
2
OUT2
1
OUT1
0
OUT0
Description
IO output data for pin 3 Default Value: 0
IO output data for pin 2 Default Value: 0
IO output data for pin 1 Default Value: 0
IO output data for pin 0 '0': Output state set to '0' '1': Output state set to '1' Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
757
GPIO_PRT4_IN
16.1.25 GPIO_PRT4_IN
Address = 0x40320210 Port input state register Address: 0x40320210 Retention: Not Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:4]
4
3
2
1
0
R
R
R
R
W
W
W
W
IN3
IN2
IN1
IN0
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:9]
9
8
R
W
FLT_IN
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
8
FLT_IN
3
IN3
2
IN2
1
IN1
0
IN0
Description
Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register. Default Value: 0
IO pin state for pin 3 Default Value: 0
IO pin state for pin 2 Default Value: 0
IO pin state for pin 1 Default Value: 0
IO pin state for pin 0 '0': Low logic level present on pin. '1': High logic level present on pin. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
758
GPIO_PRT4_INTR
16.1.26 GPIO_PRT4_INTR
Address = 0x40320214 Port interrupt status register Address: 0x40320214 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:4]
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
SW Access
HW Access
Name
22
21
None
None
None [23:20]
Bits
31
30
29
SW Access
HW Access
Name
4
3
RW1C
A
EDGE3
12
11
None
None
None [15:9]
20
19
R
W
IN_IN3
28
27
None
None
None [31:25]
2 RW1C
A EDGE2
10
18 R W IN_IN2 26
1 RW1C
A EDGE1
9
17 R W IN_IN1 25
0 RW1C
A EDGE0
8 RW1C
A FLT_EDGE
16 R W IN_IN0
24 R W FLT_IN_IN
Bits
Name
24
FLT_IN_IN
19
IN_IN3
18
IN_IN2
17
IN_IN1
16
IN_IN0
8
FLT_EDGE
3
EDGE3
2
EDGE2
Description
Filtered pin state for pin selected by INTR_CFG.FLT_SEL Default Value: 0
IO pin state for pin 3 Default Value: 0
IO pin state for pin 2 Default Value: 0
IO pin state for pin 1 Default Value: 0
IO pin state for pin 0 Default Value: 0
Edge detected on filtered pin selected by INTR_CFG.FLT_SEL Default Value: 0
Edge detect for IO pin 3 Default Value: 0
Edge detect for IO pin 2 Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
759
16.1.26 GPIO_PRT4_INTR (continued)
1
EDGE1
0
EDGE0
Edge detect for IO pin 1 Default Value: 0
Edge detect for IO pin 0 '0': No edge was detected on pin. '1': An edge was detected on pin. Default Value: 0
GPIO_PRT4_INTR
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
760
GPIO_PRT4_INTR_MASK
16.1.27 GPIO_PRT4_INTR_MASK
Address = 0x40320218 Port interrupt mask register Address: 0x40320218 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:4]
4
3
RW
R
EDGE3
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:9]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2 RW R EDGE2 10
18
26
1 RW R EDGE1
9
17
0 RW R EDGE0
8 RW R FLT_EDGE
16
25
24
Bits
Name
8
FLT_EDGE
3
EDGE3
2
EDGE2
1
EDGE1
0
EDGE0
Description
Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL Default Value: 0
Masks edge interrupt on IO pin 3 Default Value: 0
Masks edge interrupt on IO pin 2 Default Value: 0
Masks edge interrupt on IO pin 1 Default Value: 0
Masks edge interrupt on IO pin 0 '0': Pin interrupt forwarding disabled '1': Pin interrupt forwarding enabled Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
761
GPIO_PRT4_INTR_MASKED
16.1.28 GPIO_PRT4_INTR_MASKED
Address = 0x4032021C Port interrupt masked status register Address: 0x4032021C Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:4]
4
3
R
W
EDGE3
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:9]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2 R W EDGE2 10
18
26
1 R W EDGE1 9
17
0 R W EDGE0
8 R W FLT_EDGE
16
25
24
Bits
Name
8
FLT_EDGE
3
EDGE3
2
EDGE2
1
EDGE1
0
EDGE0
Description
Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL Default Value: 0
Edge detected and masked on IO pin 3 Default Value: 0
Edge detected and masked on IO pin 2 Default Value: 0
Edge detected and masked on IO pin 1 Default Value: 0
Edge detected AND masked on IO pin 0 '0': Interrupt was not forwarded to CPU '1': Interrupt occurred and was forwarded to CPU Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
762
GPIO_PRT4_INTR_SET
16.1.29 GPIO_PRT4_INTR_SET
Address = 0x40320220 Port interrupt set register Address: 0x40320220 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:4]
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4
3
RW1S
A
EDGE3
12
11
None
None
None [15:9]
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
2 RW1S
A EDGE2
10
18
26
1 RW1S
A EDGE1
9
17
0 RW1S
A EDGE0
8 RW1S
A FLT_EDGE
16
25
24
Bits
Name
8
FLT_EDGE
3
EDGE3
2
EDGE2
1
EDGE1
0
EDGE0
Description
Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL Default Value: 0
Sets edge detect interrupt for IO pin 3 Default Value: 0
Sets edge detect interrupt for IO pin 2 Default Value: 0
Sets edge detect interrupt for IO pin 1 Default Value: 0
Sets edge detect interrupt for IO pin 0 '0': Interrupt state not affected '1': Interrupt set Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
763
GPIO_PRT4_INTR_CFG
16.1.30 GPIO_PRT4_INTR_CFG (continued)
16.1.30 GPIO_PRT4_INTR_CFG
Address = 0x40320224 Port interrupt configuration register Address: 0x40320224 Retention: Retained
Bits SW Access HW Access
Name
7
6
RW
R
EDGE3_SEL [7:6]
5
4
RW
R
EDGE2_SEL [5:4]
3
2
RW
R
EDGE1_SEL [3:2]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits SW Access HW Access
Name
23
22
21
None
None
None [23:21]
20
19
18
RW
R
FLT_SEL [20:18]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
1
0
RW
R
EDGE0_SEL [1:0]
9
8
17
16
RW
R
FLT_EDGE_SEL [17:16]
25
24
Bits 20 : 18
17 : 16
Name FLT_SEL
FLT_EDGE_SEL
Description Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt. Default Value: 0 Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL Default Value: 0 0x0: DISABLE : Disabled
0x1: RISING : Rising edge
0x2: FALLING : Falling edge
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
764
16.1.30
GPIO_PRT4_INTR_CFG (continued)
0x3: BOTH : Both rising and falling edges
7 : 6
EDGE3_SEL
5 : 4
EDGE2_SEL
3 : 2
EDGE1_SEL
1 : 0
EDGE0_SEL
Sets which edge will trigger an IRQ for IO pin 3 Default Value: 0
Sets which edge will trigger an IRQ for IO pin 2 Default Value: 0
Sets which edge will trigger an IRQ for IO pin 1 Default Value: 0
Sets which edge will trigger an IRQ for IO pin 0 Default Value: 0
0x0: DISABLE :
Disabled
0x1: RISING : Rising edge
0x2: FALLING : Falling edge
0x3: BOTH : Both rising and falling edges
GPIO_PRT4_INTR_CFG
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
765
GPIO_PRT4_CFG
16.1.31 GPIO_PRT4_CFG
Address = 0x40320228 Port configuration register Address: 0x40320228 Retention: Retained
Bits SW Access HW Access
Name
7 RW R IN_EN1
6
5
4
RW
R
DRIVE_MODE1 [6:4]
3 RW R IN_EN0
Bits SW Access HW Access
Name
15 RW R IN_EN3
14
13
12
RW
R
DRIVE_MODE3 [14:12]
11 RW R IN_EN2
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 14 : 12 11 10 : 8 7 6 : 4
Name IN_EN3 DRIVE_MODE3 IN_EN2 DRIVE_MODE2 IN_EN1 DRIVE_MODE1
Description
Enables the input buffer for IO pin 3 Default Value: 0
The GPIO drive mode for IO pin 3 Default Value: 0
Enables the input buffer for IO pin 2 Default Value: 0
The GPIO drive mode for IO pin 2 Default Value: 0
Enables the input buffer for IO pin 1 Default Value: 0
The GPIO drive mode for IO pin 1 Default Value: 0
2
1
0
RW
R
DRIVE_MODE0 [2:0]
10
9
8
RW
R
DRIVE_MODE2 [10:8]
18
17
16
26
25
24
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
766
GPIO_PRT4_CFG
16.1.31 GPIO_PRT4_CFG (continued)
3
IN_EN0
2 : 0
DRIVE_MODE0
Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue. '0': Input buffer disabled '1': Input buffer enabled Default Value: 0
The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode. Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured before turning the IO on here to avoid producing glitches on the bus. Note: that peripherals other than GPIO & UDB/DSI directly control both the output and outputenable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0'). Note: D_OUT, D_OUT_EN are pins of GPIO cell. Default Value: 0
0x0: HIGHZ :
Output buffer is off creating a high impedance input D_OUT = '0': High Impedance D_OUT = '1': High Impedance
0x1: RESERVED :
This mode is reserved and should not be used. No damage will occur if this mode is selected. The pin will generally perform the same as the STRONG drive mode although this is not guaranteed for all use cases. For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
767
16.1.31
GPIO_PRT4_CFG (continued)
0x2: PULLUP :
Resistive pull up For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Weak/resistive pull up When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': Weak/resistive pull up D_OUT = '1': Weak/resistive pull up
0x3: PULLDOWN :
Resistive pull down For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': Weak/resistive pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': Weak/resistive pull down D_OUT = '1': Weak/resistive pull down
0x4: OD_DRIVESLOW :
Open drain, drives low For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': High Impedance When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High Impedance D_OUT = '1': High Impedance
GPIO_PRT4_CFG
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
768
GPIO_PRT4_CFG
16.1.31
GPIO_PRT4_CFG (continued)
0x5: OD_DRIVESHIGH :
Open drain, drives high For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': High Impedance D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High Impedance D_OUT = '1': High Impedance
0x6: STRONG :
Strong D_OUTput buffer For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High Impedance D_OUT = '1': High Impedance
0x7: PULLUP_DOWN :
Pull up or pull down For GPIO & UDB/DSI peripherals: When D_OUT_EN = '0': GPIO_DSI_OUT = '0': Weak/resistive pull down GPIO_DSI_OUT = '1': Weak/resistive pull up where "GPIO_DSI_OUT" is a function of PORT_SEL, OUT & DSI_DATA_OUT. For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': Weak/resistive pull down D_OUT = '1': Weak/resistive pull up
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
769
GPIO_PRT4_CFG_IN
16.1.32 GPIO_PRT4_CFG_IN
Address = 0x4032022C Port input buffer configuration register Address: 0x4032022C Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:4]
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4
3
RW
R
VTRIP_SEL3_0
12
11
None
None
None [15:8]
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
2 RW R VTRIP_SEL2_0 10
18
26
1 RW R VTRIP_SEL1_0
9
17
25
0 RW R VTRIP_SEL0_0
8
16
24
Bits
Name
3
VTRIP_SEL3_0
2
VTRIP_SEL2_0
1
VTRIP_SEL1_0
0
VTRIP_SEL0_0
Description
Configures the pin 3 input buffer mode (trip points and hysteresis) Default Value: 0
Configures the pin 2 input buffer mode (trip points and hysteresis) Default Value: 0
Configures the pin 1 input buffer mode (trip points and hysteresis) Default Value: 0
Configures the pin 0 input buffer mode (trip points and hysteresis) Default Value: 0
0x0: CMOS :
S40E: {CFG_IN_GPIO5V.VTRIP_SEL0_1, CFG_IN.VTRIP_SEL0_0} 0,0: CMOS 0,1: TTL 1,0: input buffer is compatible with automotive. 1,1: input buffer is compatible with automotvie
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
770
GPIO_PRT4_CFG_IN
16.1.32
GPIO_PRT4_CFG_IN (continued)
0x1: TTL : S40S: Input buffer compatible with TTL and MediaLB interfaces
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
771
GPIO_PRT4_CFG_OUT
16.1.33 GPIO_PRT4_CFG_OUT
Address = 0x40320230 Port output buffer configuration register Address: 0x40320230 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:4]
4
3
2
RW
RW
R
R
SLOW3
SLOW2
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits SW Access HW Access
Name
23
22
RW
R
DRIVE_SEL3 [23:22]
21
20
RW
R
DRIVE_SEL2 [21:20]
19
18
RW
R
DRIVE_SEL1 [19:18]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
1 RW R SLOW1
9
0 RW R SLOW0
8
17
16
RW
R
DRIVE_SEL0 [17:16]
25
24
Bits 23 : 22 21 : 20 19 : 18 17 : 16
Name DRIVE_SEL3 DRIVE_SEL2 DRIVE_SEL1 DRIVE_SEL0
Description Sets the GPIO drive strength for IO pin 3 Default Value: 0 Sets the GPIO drive strength for IO pin 2 Default Value: 0 Sets the GPIO drive strength for IO pin 1 Default Value: 0 Sets the GPIO drive strength for IO pin 0 Default Value: 0 0x0: FULL_DRIVE :
Full drive strength: GPIO drives current at its max rated spec.
0x1: ONE_HALF_DRIVE :
1/2 drive strength: GPIO drives current at 1/2 of its max rated spec
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
772
GPIO_PRT4_CFG_OUT
16.1.33
GPIO_PRT4_CFG_OUT (continued)
0x2: ONE_QUARTER_DRIVE : 1/4 drive strength: GPIO drives current at 1/4 of its max rated spec.
0x3: ONE_EIGHTH_DRIVE : 1/8 drive strength: GPIO drives current at 1/8 of its max rated spec.
3
SLOW3
2
SLOW2
1
SLOW1
0
SLOW0
Enables slow slew rate for IO pin 3 Default Value: 0
Enables slow slew rate for IO pin 2 Default Value: 0
Enables slow slew rate for IO pin 1 Default Value: 0
Enables slow slew rate for IO pin 0 '0': Fast slew rate '1': Slow slew rate Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
773
GPIO_PRT14_OUT
16.1.34 GPIO_PRT14_OUT
Address = 0x40320700 Port output data register Address: 0x40320700 Retention: Retained
Bits
7
6
SW Access
HW Access
Name
Bits
15
14
SW Access
HW Access
Name
Bits
23
22
SW Access
HW Access
Name
Bits
31
30
SW Access
HW Access
Name
5
4
3
None
None
None [7:2]
13
12
11
None
None
None [15:8]
21
20
19
None
None
None [23:16]
29
28
27
None
None
None [31:24]
Bits
Name
1
OUT1
0
OUT0
Description
IO output data for pin 1 Default Value: 0
IO output data for pin 0 '0': Output state set to '0' '1': Output state set to '1' Default Value: 0
2
1
0
RW
RW
RW
RW
OUT1
OUT0
10
9
8
18
17
16
26
25
24
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
774
GPIO_PRT14_IN
16.1.35 GPIO_PRT14_IN
Address = 0x40320710 Port input state register Address: 0x40320710 Retention: Not Retained
Bits
7
6
SW Access
HW Access
Name
Bits
15
14
SW Access
HW Access
Name
Bits
23
22
SW Access
HW Access
Name
Bits
31
30
SW Access
HW Access
Name
5
4
3
None
None
None [7:2]
13
12
11
None
None
None [15:9]
21
20
19
None
None
None [23:16]
29
28
27
None
None
None [31:24]
2
1
0
R
R
W
W
IN1
IN0
10
9
8
R
W
FLT_IN
18
17
16
26
25
24
Bits
Name
8
FLT_IN
1
IN1
0
IN0
Description
Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register. Default Value: 0
IO pin state for pin 1 Default Value: 0
IO pin state for pin 0 '0': Low logic level present on pin. '1': High logic level present on pin. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
775
GPIO_PRT14_INTR
16.1.36 GPIO_PRT14_INTR
Address = 0x40320714 Port interrupt status register Address: 0x40320714 Retention: Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:2]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:9]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:18]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:25]
2
1
0
RW1C
RW1C
A
A
EDGE1
EDGE0
10
9
8
RW1C
A
FLT_EDGE
18
17
16
R
R
W
W
IN_IN1
IN_IN0
26
25
24
R
W
FLT_IN_IN
Bits
Name
24
FLT_IN_IN
17
IN_IN1
16
IN_IN0
8
FLT_EDGE
1
EDGE1
0
EDGE0
Description
Filtered pin state for pin selected by INTR_CFG.FLT_SEL Default Value: 0
IO pin state for pin 1 Default Value: 0
IO pin state for pin 0 Default Value: 0
Edge detected on filtered pin selected by INTR_CFG.FLT_SEL Default Value: 0
Edge detect for IO pin 1 Default Value: 0
Edge detect for IO pin 0 '0': No edge was detected on pin. '1': An edge was detected on pin. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
776
GPIO_PRT14_INTR_MASK
16.1.37 GPIO_PRT14_INTR_MASK
Address = 0x40320718 Port interrupt mask register Address: 0x40320718 Retention: Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:2]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:9]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
0
RW
RW
R
R
EDGE1
EDGE0
10
9
8
RW
R
FLT_EDGE
18
17
16
26
25
24
Bits
Name
8
FLT_EDGE
1
EDGE1
0
EDGE0
Description
Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL Default Value: 0
Masks edge interrupt on IO pin 1 Default Value: 0
Masks edge interrupt on IO pin 0 '0': Pin interrupt forwarding disabled '1': Pin interrupt forwarding enabled Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
777
GPIO_PRT14_INTR_MASKED
16.1.38 GPIO_PRT14_INTR_MASKED
Address = 0x4032071C Port interrupt masked status register Address: 0x4032071C Retention: Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:2]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:9]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
0
R
R
W
W
EDGE1
EDGE0
10
9
8
R
W
FLT_EDGE
18
17
16
26
25
24
Bits
Name
8
FLT_EDGE
1
EDGE1
0
EDGE0
Description
Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL Default Value: 0
Edge detected and masked on IO pin 1 Default Value: 0
Edge detected AND masked on IO pin 0 '0': Interrupt was not forwarded to CPU '1': Interrupt occurred and was forwarded to CPU Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
778
GPIO_PRT14_INTR_SET
16.1.39 GPIO_PRT14_INTR_SET
Address = 0x40320720 Port interrupt set register Address: 0x40320720 Retention: Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:2]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:9]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
0
RW1S
RW1S
A
A
EDGE1
EDGE0
10
9
8
RW1S
A
FLT_EDGE
18
17
16
26
25
24
Bits
Name
8
FLT_EDGE
1
EDGE1
0
EDGE0
Description
Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL Default Value: 0
Sets edge detect interrupt for IO pin 1 Default Value: 0
Sets edge detect interrupt for IO pin 0 '0': Interrupt state not affected '1': Interrupt set Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
779
GPIO_PRT14_INTR_CFG
16.1.40 GPIO_PRT14_INTR_CFG
Address = 0x40320724 Port interrupt configuration register Address: 0x40320724 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:4]
Bits
15
14
13
SW Access
HW Access
Name
Bits SW Access HW Access
Name
23
22
21
None
None
None [23:21]
Bits
31
30
29
SW Access
HW Access
Name
4
3
2
RW
R
EDGE1_SEL [3:2]
12
11
10
None
None
None [15:8]
20
19
18
RW
R
FLT_SEL [20:18]
28
27
26
None
None
None [31:24]
1
0
RW
R
EDGE0_SEL [1:0]
9
8
17
16
RW
R
FLT_EDGE_SEL [17:16]
25
24
Bits 20 : 18
17 : 16
Name FLT_SEL
FLT_EDGE_SEL
Description Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt. Default Value: 0 Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL Default Value: 0 0x0: DISABLE : Disabled
0x1: RISING : Rising edge
0x2: FALLING : Falling edge
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
780
16.1.40
GPIO_PRT14_INTR_CFG (continued)
0x3: BOTH : Both rising and falling edges
3 : 2
EDGE1_SEL
1 : 0
EDGE0_SEL
Sets which edge will trigger an IRQ for IO pin 1 Default Value: 0
Sets which edge will trigger an IRQ for IO pin 0 Default Value: 0
0x0: DISABLE :
Disabled
0x1: RISING : Rising edge
0x2: FALLING : Falling edge
0x3: BOTH : Both rising and falling edges
GPIO_PRT14_INTR_CFG
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
781
GPIO_PRT14_CFG
16.1.41 GPIO_PRT14_CFG
Address = 0x40320728 Port configuration register Address: 0x40320728 Retention: Retained
Bits SW Access HW Access
Name
7 RW R IN_EN1
6
5
4
RW
R
DRIVE_MODE1 [6:4]
3 RW R IN_EN0
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
0
RW
R
DRIVE_MODE0 [2:0]
10
9
8
18
17
16
26
25
24
Bits 7 6 : 4 3
Name IN_EN1 DRIVE_MODE1 IN_EN0
2 : 0
DRIVE_MODE0
Description
Enables the input buffer for IO pin 1 Default Value: 0
The GPIO drive mode for IO pin 1 Default Value: 0
Enables the input buffer for IO pin 0. This bit should be cleared when analog signals are present on the pin to avoid crowbar currents. The output buffer can be used to drive analog signals high or low without issue. '0': Input buffer disabled '1': Input buffer enabled Default Value: 0
The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode. Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured before turning the IO on here to avoid producing glitches on the bus. Note: that peripherals other than GPIO & UDB/DSI directly control both the output and outputenable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0'). Note: D_OUT, D_OUT_EN are pins of GPIO cell. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
782
GPIO_PRT14_CFG
16.1.41
GPIO_PRT14_CFG (continued)
0x0: HIGHZ :
Output buffer is off creating a high impedance input D_OUT = '0': High Impedance D_OUT = '1': High Impedance
0x1: RESERVED :
This mode is reserved and should not be used. No damage will occur if this mode is selected. The pin will generally perform the same as the STRONG drive mode although this is not guaranteed for all use cases. For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance
0x2: PULLUP :
Resistive pull up For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Weak/resistive pull up When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': Weak/resistive pull up D_OUT = '1': Weak/resistive pull up
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
783
16.1.41
GPIO_PRT14_CFG (continued)
0x3: PULLDOWN :
Resistive pull down For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': Weak/resistive pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': Weak/resistive pull down D_OUT = '1': Weak/resistive pull down
0x4: OD_DRIVESLOW :
Open drain, drives low For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': High Impedance When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High Impedance D_OUT = '1': High Impedance
0x5: OD_DRIVESHIGH :
Open drain, drives high For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': High Impedance D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High Impedance D_OUT = '1': High Impedance
GPIO_PRT14_CFG
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
784
GPIO_PRT14_CFG
16.1.41
GPIO_PRT14_CFG (continued)
0x6: STRONG :
Strong D_OUTput buffer For GPIO & UDB/DSI peripherals: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High impedance D_OUT = '1': High impedance For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': High Impedance D_OUT = '1': High Impedance
0x7: PULLUP_DOWN :
Pull up or pull down For GPIO & UDB/DSI peripherals: When D_OUT_EN = '0': GPIO_DSI_OUT = '0': Weak/resistive pull down GPIO_DSI_OUT = '1': Weak/resistive pull up where "GPIO_DSI_OUT" is a function of PORT_SEL, OUT & DSI_DATA_OUT. For peripherals other than GPIO & UDB/DSI: When D_OUT_EN = 1: D_OUT = '0': Strong pull down D_OUT = '1': Strong pull up When D_OUT_EN = 0: D_OUT = '0': Weak/resistive pull down D_OUT = '1': Weak/resistive pull up
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
785
GPIO_INTR_CAUSE0
16.1.42 GPIO_INTR_CAUSE0
Address = 0x40324000 Interrupt port cause register 0 Address: 0x40324000 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
PORT_INT [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
R
HW Access
None
W
Name
None
PORT_INT [14:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 14 : 0
Name PORT_INT
Description
Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects "gpio_interrupts[i]" for IO port i). The register is used when the system uses a combined interrupt line "gpio_interrupt". The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PRT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt. '0': Port has no pending interrupt '1': Port has pending interrupt Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
786
GPIO_VDD_ACTIVE
16.1.43 GPIO_VDD_ACTIVE
Address = 0x40324010 Extern power supply detection register Address: 0x40324010 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
R
HW Access
None
W
Name
None [7:6]
VDDIO_ACTIVE [5:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
R
None
HW Access
W
W
None
Name
VDDD_AC- VDDA_AC-
TIVE
TIVE
None [29:24]
Bits
Name
31
VDDD_ACTIVE
30
VDDA_ACTIVE
Description
This bit indicates presence of the VDDD supply. This bit will always read-back 1. The VDDD supply has robust brown-out protection monitoring and it is not possible to read back this register without a valid supply. (This bit is used in certain test-modes to observe the brown-out detector status.) Default Value: 0
Same as VDDIO_ACTIVE for the analog supply VDDA. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
787
GPIO_VDD_ACTIVE
16.1.43 GPIO_VDD_ACTIVE (continued)
5 : 0
VDDIO_ACTIVE
Indicates presence or absence of VDDIO supplies (i.e. other than VDDD, VDDA) on the device (supplies are numbered 0..n-1). Note that VDDIO supplies have basic (crude) supply detectors only. If separate, robust, brown-out detection is desired on IO supplies, on-chip or off-chip analog resources need to provide it. For these bits to work reliable, the supply must be within valid spec range (per datasheet) or held at ground. Any in-between voltage has an undefined result. '0': Supply is not present '1': Supply is present When multiple VDDIO supplies are present, they will be assigned in alphanumeric ascending order to these bits during implementation. For example "vddusb, vddio_0, vddio_a, vbackup, vddio_r, vddio_1" are present then they will be assigned to these bits as below: 0: vbackup, 1: vddio_0, 2: vddio_1, 3: vddio_a, 4: vddio_r, 5: vddusb" Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
788
GPIO_VDD_INTR
16.1.44 GPIO_VDD_INTR
Address = 0x40324014 Supply detection interrupt register Address: 0x40324014 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW1C
HW Access
None
A
Name
None [7:6]
VDDIO_ACTIVE [5:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW1C
RW1C
None
HW Access
A
A
None
Name
VDDD_AC- VDDA_AC-
TIVE
TIVE
None [29:24]
Bits
Name
31
VDDD_ACTIVE
30
VDDA_ACTIVE
5 : 0
VDDIO_ACTIVE
Description
The VDDD supply is always present during operation so a supply transition can not occur. This bit will always read back '1'. Default Value: 0
Same as VDDIO_ACTIVE for the analog supply VDDA. Default Value: 0
Supply state change detected. '0': No change to supply detected '1': Change to supply detected Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
789
GPIO_VDD_INTR_MASK
16.1.45 GPIO_VDD_INTR_MASK
Address = 0x40324018 Supply detection interrupt mask register Address: 0x40324018 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:6]
VDDIO_ACTIVE [5:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
RW
None
HW Access
R
R
None
Name
VDDD_AC- VDDA_AC-
TIVE
TIVE
None [29:24]
Bits 31 30 5 : 0
Name VDDD_ACTIVE VDDA_ACTIVE VDDIO_ACTIVE
Description
Same as VDDIO_ACTIVE for the digital supply VDDD. Default Value: 0
Same as VDDIO_ACTIVE for the analog supply VDDA. Default Value: 0
Masks supply interrupt on VDDIO. '0': VDDIO interrupt forwarding disabled '1': VDDIO interrupt forwarding enabled Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
790
GPIO_VDD_INTR_MASKED
16.1.46 GPIO_VDD_INTR_MASKED
Address = 0x4032401C Supply detection interrupt masked register Address: 0x4032401C Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
R
HW Access
None
W
Name
None [7:6]
VDDIO_ACTIVE [5:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
R
None
HW Access
W
W
None
Name
VDDD_AC- VDDA_AC-
TIVE
TIVE
None [29:24]
Bits 31 30 5 : 0
Name VDDD_ACTIVE VDDA_ACTIVE VDDIO_ACTIVE
Description
Same as VDDIO_ACTIVE for the digital supply VDDD. Default Value: 0
Same as VDDIO_ACTIVE for the analog supply VDDA. Default Value: 0
Supply transition detected AND masked '0': Interrupt was not forwarded to CPU '1': Interrupt occurred and was forwarded to CPU Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
791
GPIO_VDD_INTR_SET
16.1.47 GPIO_VDD_INTR_SET
Address = 0x40324020 Supply detection interrupt set register Address: 0x40324020 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW1S
HW Access
None
A
Name
None [7:6]
VDDIO_ACTIVE [5:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW1S
RW1S
None
HW Access
A
A
None
Name
VDDD_AC- VDDA_AC-
TIVE
TIVE
None [29:24]
Bits 31 30 5 : 0
Name VDDD_ACTIVE VDDA_ACTIVE VDDIO_ACTIVE
Description
Same as VDDIO_ACTIVE for the digital supply VDDD. Default Value: 0
Same as VDDIO_ACTIVE for the analog supply VDDA. Default Value: 0
Sets supply interrupt. '0': Interrupt state not affected '1': Interrupt set Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
792
17 Smart I/O Registers
This section discusses the Smart I/O registers. It lists all the registers in mapping tables, in address order.
17.1 Register Details
Register SMARTIO_PRT8_CTL SMARTIO_PRT8_SYNC_CTL SMARTIO_PRT8_LUT_SEL0 SMARTIO_PRT8_LUT_SEL1 SMARTIO_PRT8_LUT_SEL2 SMARTIO_PRT8_LUT_SEL3 SMARTIO_PRT8_LUT_SEL4 SMARTIO_PRT8_LUT_SEL5 SMARTIO_PRT8_LUT_SEL6 SMARTIO_PRT8_LUT_SEL7 SMARTIO_PRT8_LUT_CTL0 SMARTIO_PRT8_LUT_CTL1 SMARTIO_PRT8_LUT_CTL2 SMARTIO_PRT8_LUT_CTL3 SMARTIO_PRT8_LUT_CTL4 SMARTIO_PRT8_LUT_CTL5 SMARTIO_PRT8_LUT_CTL6 SMARTIO_PRT8_LUT_CTL7 SMARTIO_PRT8_DU_SEL SMARTIO_PRT8_DU_CTL SMARTIO_PRT8_DATA SMARTIO_PRT9_CTL SMARTIO_PRT9_SYNC_CTL SMARTIO_PRT9_LUT_SEL0 SMARTIO_PRT9_LUT_SEL1 SMARTIO_PRT9_LUT_SEL2 SMARTIO_PRT9_LUT_SEL3
Address 0x40330800 0x40330810 0x40330820 0x40330824 0x40330828 0x4033082C 0x40330830 0x40330834 0x40330838 0x4033083C 0x40330840 0x40330844 0x40330848 0x4033084C 0x40330850 0x40330854 0x40330858 0x4033085C 0x403308C0 0x403308C4 0x403308F0 0x40330900 0x40330910 0x40330920 0x40330924 0x40330928 0x4033092C
Description Control register Synchronization control register LUT component input selection LUT component input selection. See SMARTIO_PRT8_LUT_SEL0 for the details of bit fields. LUT component input selection. See SMARTIO_PRT8_LUT_SEL0 for the details of bit fields. LUT component input selection. See SMARTIO_PRT8_LUT_SEL0 for the details of bit fields. LUT component input selection. See SMARTIO_PRT8_LUT_SEL0 for the details of bit fields. LUT component input selection. See SMARTIO_PRT8_LUT_SEL0 for the details of bit fields. LUT component input selection. See SMARTIO_PRT8_LUT_SEL0 for the details of bit fields. LUT component input selection. See SMARTIO_PRT8_LUT_SEL0 for the details of bit fields. LUT component control register LUT component control register. See SMARTIO_PRT8_LUT_CTL0 for the details of bit fields. LUT component control register. See SMARTIO_PRT8_LUT_CTL0 for the details of bit fields. LUT component control register. See SMARTIO_PRT8_LUT_CTL0 for the details of bit fields. LUT component control register. See SMARTIO_PRT8_LUT_CTL0 for the details of bit fields. LUT component control register. See SMARTIO_PRT8_LUT_CTL0 for the details of bit fields. LUT component control register. See SMARTIO_PRT8_LUT_CTL0 for the details of bit fields. LUT component control register. See SMARTIO_PRT8_LUT_CTL0 for the details of bit fields. Data unit component input selection Data unit component control register Data register Control register. See SMARTIO_PRT8_CTL for the details of bit fields. Synchronization control register. See SMARTIO_PRT8_SYNC_CTL for the details of bit fields. LUT component input selection. See SMARTIO_PRT8_LUT_SEL0 for the details of bit fields. LUT component input selection. See SMARTIO_PRT8_LUT_SEL0 for the details of bit fields. LUT component input selection. See SMARTIO_PRT8_LUT_SEL0 for the details of bit fields. LUT component input selection. See SMARTIO_PRT8_LUT_SEL0 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
793
Smart I/O Registers
Register SMARTIO_PRT9_LUT_SEL4 SMARTIO_PRT9_LUT_SEL5 SMARTIO_PRT9_LUT_SEL6 SMARTIO_PRT9_LUT_SEL7 SMARTIO_PRT9_LUT_CTL0 SMARTIO_PRT9_LUT_CTL1 SMARTIO_PRT9_LUT_CTL2 SMARTIO_PRT9_LUT_CTL3 SMARTIO_PRT9_LUT_CTL4 SMARTIO_PRT9_LUT_CTL5 SMARTIO_PRT9_LUT_CTL6 SMARTIO_PRT9_LUT_CTL7 SMARTIO_PRT9_DU_SEL SMARTIO_PRT9_DU_CTL SMARTIO_PRT9_DATA
Address 0x40330930 0x40330934 0x40330938 0x4033093C 0x40330940 0x40330944 0x40330948 0x4033094C 0x40330950 0x40330954 0x40330958 0x4033095C 0x403309C0 0x403309C4 0x403309F0
Description LUT component input selection. See SMARTIO_PRT8_LUT_SEL0 for the details of bit fields. LUT component input selection. See SMARTIO_PRT8_LUT_SEL0 for the details of bit fields. LUT component input selection. See SMARTIO_PRT8_LUT_SEL0 for the details of bit fields. LUT component input selection. See SMARTIO_PRT8_LUT_SEL0 for the details of bit fields. LUT component control register. See SMARTIO_PRT8_LUT_CTL0 for the details of bit fields. LUT component control register. See SMARTIO_PRT8_LUT_CTL0 for the details of bit fields. LUT component control register. See SMARTIO_PRT8_LUT_CTL0 for the details of bit fields. LUT component control register. See SMARTIO_PRT8_LUT_CTL0 for the details of bit fields. LUT component control register. See SMARTIO_PRT8_LUT_CTL0 for the details of bit fields. LUT component control register. See SMARTIO_PRT8_LUT_CTL0 for the details of bit fields. LUT component control register. See SMARTIO_PRT8_LUT_CTL0 for the details of bit fields. LUT component control register. See SMARTIO_PRT8_LUT_CTL0 for the details of bit fields. Data unit component input selection. See SMARTIO_PRT8_DU_SEL for the details of bit fields. Data unit component control register. See SMARTIO_PRT8_DU_CTL for the details of bit fields. Data register. See SMARTIO_PRT8_DATA for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
794
SMARTIO_PRT8_CTL
17.1.1 SMARTIO_PRT8_CTL
Address = 0x40330800 Control register Address: 0x40330800 Retention: Retained
Bits
7
6
5
SW Access
HW Access
Name
Bits SW Access HW Access
Name
15
14
13
None
None
None [15:13]
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
RW
HW Access
R
Name
ENABLED
4
3
2
1
RW
R
BYPASS [7:0]
12
11
10
9
RW
R
CLOCK_SRC [12:8]
20
19
18
17
None
None
None [23:16]
28
27
None
None
None [30:26]
26
25
RW
R
PIPELINE_EN
0
8
16
24 RW R HLD_OVR
Bits
Name
31
ENABLED
25
PIPELINE_EN
Description
Enable for programmable IO. Should only be set to '1' when the programmable IO is completely configured: '0': Disabled (signals are bypassed; behavior as if BYPASS is 0xFF). When disabled, the fabric (data unit and LUTs) reset is activated. If the IP is disabled: - The PIPELINE_EN register field should be set to '1', to ensure low power consumption by preventing combinatorial loops. - The CLOCK_SRC register field should be set to "20"-"30" (clock is constant '0'), to ensure low power consumption. '1': Enabled. Once enabled, it takes 3 "clk_fabric" clock cycles till the fabric reset is de-activated and the fabric becomes fully functional. This ensures that the IO pins' input synchronizer states are flushed when the fabric is fully functional. Default Value: 0
Enable for pipeline register: '0': Disabled (register is bypassed). '1': Enabled. Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
795
SMARTIO_PRT8_CTL
17.1.1
24 12 : 8
7 : 0
SMARTIO_PRT8_CTL (continued)
HLD_OVR CLOCK_SRC
BYPASS
IO cell hold override functionality. In DeepSleep power mode, the HSIOM holds the IO cell output and output enable signals if Active functionality is connected to the IO pads. This is undesirable if the SMARTIO is supposed to deliver DeepSleep output functionality on these IO pads. This field is used to control the hold override functionality from the SMARTIO: '0': The HSIOM controls the IO cell hold override functionality ("hsiom_hld_ovr"). '1': The SMARTIO controls the IO cel hold override functionality: - In bypass mode (ENABLED is '0' or BYPASS[i] is '1'), the HSIOM control is used. - In NON bypass mode (ENABLED is '1' and BYPASS[i] is '0'), the SMARTIO sets hold override to "pwr_hld_ovr_hib" to enable SMARTIO functionality in DeepSleep power mode (but disables it in Hibernate or Stop power mode). Default Value: Undefined
Clock ("clk_fabric") and reset ("rst_fabric_n") source selection: "0": io_data_in[0]/'1'. ... "7": io_data_in[7]/'1'. "8": chip_data[0]/'1'. ... "15": chip_data[7]/'1'. "16": clk_smartio/rst_sys_act_n. Used for both Active functionality synchronous logic on "clk_smartio". This selection is intended for synchronous operation on a PCLK specified clock frequency ("clock_smartio_pos_en"). Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to "clk_sys". "17": clk_smartio/rst_sys_dpslp_n. Used for both DeepSleep functionality synchronous logic on "clk_smartio" (note that "clk_smartio" is NOT available in DeepSleep and Hibernate power modes). This selection is intended for synchronous operation on a PCLK specified clock frequency ("clock_smartio_pos_en"). Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to "clk_sys". "18": Same as "17". "19": clk_lf/rst_lf_dpslp_n (note that "clk_lf" is available in DeepSleep power mode). This selection is intended for synchronous operation on"clk_lf". Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to other "clk_lf" clocked elements. "20"-"30": Clock source is constant '0'. Any of these clock sources should be selected when the IP is disabled to ensure low power consumption. "31": asynchronous mode/'1'. Select this when clockless operation is configured. NOTE: Two positive edges of the selected clock are required for the block to be enabled (to deactivate reset). In asynchronous (clockless) mode clk_sys is used to enable the block, but is not available for clocking. Default Value: 20
Bypass of the programmable IO, one bit for each IO pin: BYPASS[i] is for IO pin i. When ENABLED is '1', this field is used. When ENABLED is '0', this field is NOT used and SMARTIO fabric is always bypassed. '0': No bypass (programmable SMARTIO fabric is exposed). '1': Bypass (programmable SMARTIOIO fabric is hidden). Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
796
SMARTIO_PRT8_SYNC_CTL
17.1.2 SMARTIO_PRT8_SYNC_CTL
Address = 0x40330810 Synchronization control register Address: 0x40330810 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
IO_SYNC_EN [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
CHIP_SYNC_EN [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 8
Name CHIP_SYNC_EN
7 : 0
IO_SYNC_EN
Description
Synchronization of the chip input signals to "clk_fabric", one bit for each input: CHIP_SYNC_EN[i] is for input i. '0': No synchronization. '1': Synchronization. Default Value: Undefined
Synchronization of the IO pin input signals to "clk_fabric", one bit for each IO pin: IO_SYNC_EN[i] is for IO pin i. '0': No synchronization. '1': Synchronization. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
797
SMARTIO_PRT8_LUT_SEL0
17.1.3 SMARTIO_PRT8_LUT_SEL0
Address = 0x40330820 LUT component input selection Address: 0x40330820 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:4]
LUT_TR0_SEL [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
RW
HW Access
None
R
Name
None [15:12]
LUT_TR1_SEL [11:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
HW Access
None
R
Name
None [23:20]
LUT_TR2_SEL [19:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 19 : 16
11 : 8
Name LUT_TR2_SEL
LUT_TR1_SEL
Description
LUT input signal "tr2_in" source selection. Encoding is the same as for LUT_TR1_SEL. Default Value: Undefined
LUT input signal "tr1_in" source selection: "0": LUT 0 output. "1": LUT 1 output. "2": LUT 2 output. "3": LUT 3 output. "4": LUT 4 output. "5": LUT 5 output. "6": LUT 6 output. "7": LUT 7 output. "8": chip_data[0] (for LUTs 0, 1, 2, 3); chip_data[4] (for LUTs 4, 5, 6, 7). "9": chip_data[1] (for LUTs 0, 1, 2, 3); chip_data[5] (for LUTs 4, 5, 6, 7). "10": chip_data[2] (for LUTs 0, 1, 2, 3); chip_data[6] (for LUTs 4, 5, 6, 7). "11": chip_data[3] (for LUTs 0, 1, 2, 3); chip_data[7] (for LUTs 4, 5, 6, 7). "12": io_data_in[0] (for LUTs 0, 1, 2, 3); io_data_in[4] (for LUTs 4, 5, 6, 7). "13": io_data_in[1] (for LUTs 0, 1, 2, 3); io_data_in[5] (for LUTs 4, 5, 6, 7). "14": io_data_in[2] (for LUTs 0, 1, 2, 3); io_data_in[6] (for LUTs 4, 5, 6, 7). "15": io_data_in[3] (for LUTs 0, 1, 2, 3); io_data_in[7] (for LUTs 4, 5, 6, 7). Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
798
SMARTIO_PRT8_LUT_SEL0
17.1.3
3 : 0
SMARTIO_PRT8_LUT_SEL0 (continued)
LUT_TR0_SEL
LUT input signal "tr0_in" source selection: "0": Data unit output. "1": LUT 1 output. "2": LUT 2 output. "3": LUT 3 output. "4": LUT 4 output. "5": LUT 5 output. "6": LUT 6 output. "7": LUT 7 output. "8": chip_data[0] (for LUTs 0, 1, 2, 3); chip_data[4] (for LUTs 4, 5, 6, 7). "9": chip_data[1] (for LUTs 0, 1, 2, 3); chip_data[5] (for LUTs 4, 5, 6, 7). "10": chip_data[2] (for LUTs 0, 1, 2, 3); chip_data[6] (for LUTs 4, 5, 6, 7). "11": chip_data[3] (for LUTs 0, 1, 2, 3); chip_data[7] (for LUTs 4, 5, 6, 7). "12": io_data_in[0] (for LUTs 0, 1, 2, 3); io_data_in[4] (for LUTs 4, 5, 6, 7). "13": io_data_in[1] (for LUTs 0, 1, 2, 3); io_data_in[5] (for LUTs 4, 5, 6, 7). "14": io_data_in[2] (for LUTs 0, 1, 2, 3); io_data_in[6] (for LUTs 4, 5, 6, 7). "15": io_data_in[3] (for LUTs 0, 1, 2, 3); io_data_in[7] (for LUTs 4, 5, 6, 7). Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
799
SMARTIO_PRT8_LUT_CTL0
17.1.4 SMARTIO_PRT8_LUT_CTL0
Address = 0x40330840 LUT component control register Address: 0x40330840 Retention: Retained
Bits
7
6
5
4
3
2
SW Access
RW
HW Access
R
Name
LUT [7:0]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:10]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
Bits 9 : 8
Name LUT_OPC
Description
LUT opcode specifies the LUT operation: "0": Combinatoral output, no feedback. tr_out = LUT[{tr2_in, tr1_in, tr0_in}]. "1": Combinatorial output, feedback. tr_out = LUT[{lut_reg, tr1_in, tr0_in}]. On clock: lut_reg <= tr_in2. "2": Sequential output, no feedback. temp = LUT[{tr2_in, tr1_in, tr0_in}]. tr_out = lut_reg. On clock: lut_reg <= temp. "3": Register with asynchronous set and reset. tr_out = lut_reg. enable = (tr2_in ^ LUT[4]) | LUT[5]. set = enable & (tr1_in ^ LUT[2]) & LUT[3]. clr = enable & (tr0_in ^ LUT[0]) & LUT[1]. Asynchronously (no clock required): lut_reg <= if (clr) '0' else if (set) '1' Default Value: Undefined
1
0
9
8
RW
R
LUT_OPC [9:8]
17
16
25
24
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
800
SMARTIO_PRT8_LUT_CTL0
17.1.4
7 : 0
SMARTIO_PRT8_LUT_CTL0 (continued)
LUT
LUT configuration. Depending on the LUT opcode LUT_OPC, the internal state lut_reg (captured
in a flip-flop) and the LUT input signals tr0_in, tr1_in, tr2_in, the LUT configuration is used to de-
termine the LUT output signal and the next sequential state (lut_reg).
Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
801
SMARTIO_PRT8_DU_SEL
17.1.5 SMARTIO_PRT8_DU_SEL
Address = 0x403308C0 Data unit component input selection Address: 0x403308C0 Retention: Retained
Bits
7
6
5
4
SW Access
None
HW Access
None
Name
None [7:4]
Bits
15
14
13
12
SW Access
None
HW Access
None
Name
None [15:12]
Bits
23
22
21
20
SW Access
None
HW Access
None
Name
None [23:20]
Bits SW Access HW Access
Name
31
30
None
None
None [31:30]
29
28
RW
R
DU_DATA1_SEL [29:28]
3
2
1
0
RW
R
DU_TR0_SEL [3:0]
11
10
9
8
RW
R
DU_TR1_SEL [11:8]
19
18
17
16
RW
R
DU_TR2_SEL [19:16]
27
26
None
None
None [27:26]
25
24
RW
R
DU_DATA0_SEL [25:24]
Bits 29 : 28
25 : 24
Name DU_DATA1_SEL
DU_DATA0_SEL
19 : 16 11 : 8
DU_TR2_SEL DU_TR1_SEL
Description
Data unit input data "data1_in" source selection. Encoding is the same as for DU_DATA0_SEL. Default Value: Undefined
Data unit input data "data0_in" source selection: "0": Constant "0". "1": chip_data[7:0]. "2": io_data_in[7:0]. "3": DATA.DATA MMIO register field. Default Value: Undefined
Data unit input signal "tr2_in" source selection. Encoding is the same as for DU_TR0_SEL. Default Value: Undefined
Data unit input signal "tr1_in" source selection. Encoding is the same as for DU_TR0_SEL. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
802
SMARTIO_PRT8_DU_SEL
17.1.5
3 : 0
SMARTIO_PRT8_DU_SEL (continued)
DU_TR0_SEL
Data unit input signal "tr0_in" source selection: "0": Constant '0'. "1": Constant '1'. "2": Data unit output. "10-3": LUT 7 - 0 outputs. Otherwise: Undefined. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
803
SMARTIO_PRT8_DU_CTL
17.1.6 SMARTIO_PRT8_DU_CTL
Address = 0x403308C4 Data unit component control register Address: 0x403308C4 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:3]
Bits
15
SW Access
HW Access
Name
14
13
None
None
None [15:12]
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4
3
12
11
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
2
1
0
RW
R
DU_SIZE [2:0]
10
9
8
RW
R
DU_OPC [11:8]
18
17
16
26
25
24
Bits 11 : 8
Name DU_OPC
2 : 0
DU_SIZE
Description
Data unit opcode specifies the data unit operation: "1": INCR "2": DECR "3": INCR_WRAP "4": DECR_WRAP "5": INCR_DECR "6": INCR_DECR_WRAP "7": ROR "8": SHR "9": AND_OR "10": SHR_MAJ3 "11": SHR_EQL. Otherwise: Undefined. Default Value: Undefined
Size/width of the data unit data operands (in bits) is DU_SIZE+1. E.g., if DU_SIZE is 7, the width is 8 bits. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
804
SMARTIO_PRT8_DATA
17.1.7 SMARTIO_PRT8_DATA
Address = 0x403308F0 Data register Address: 0x403308F0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
DATA [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 0
Name DATA
Description
Data unit input data source. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
805
18 Universal Digital Block (UDB) Registers
This section discusses the Universal Digital Block (UDB) registers. It lists all the registers in mapping tables, in address order.
18.1 Register Details
Register UDB_WRKONE_A0 UDB_WRKONE_A1 UDB_WRKONE_A2 UDB_WRKONE_A3 UDB_WRKONE_A4 UDB_WRKONE_A5 UDB_WRKONE_A6 UDB_WRKONE_A7 UDB_WRKONE_A8 UDB_WRKONE_A9 UDB_WRKONE_A10 UDB_WRKONE_A11 UDB_WRKONE_D0 UDB_WRKONE_D1 UDB_WRKONE_D2 UDB_WRKONE_D3 UDB_WRKONE_D4 UDB_WRKONE_D5 UDB_WRKONE_D6
Address 0x40340000 Accumulator Registers {A1,A0}
Description
0x40340004 Accumulator Registers {A1,A0}. See UDB_WRKONE_A0 for the details of bit fields.
0x40340008 Accumulator Registers {A1,A0}. See UDB_WRKONE_A0 for the details of bit fields.
0x4034000C Accumulator Registers {A1,A0}. See UDB_WRKONE_A0 for the details of bit fields.
0x40340010 Accumulator Registers {A1,A0}. See UDB_WRKONE_A0 for the details of bit fields.
0x40340014 Accumulator Registers {A1,A0}. See UDB_WRKONE_A0 for the details of bit fields.
0x40340018 Accumulator Registers {A1,A0}. See UDB_WRKONE_A0 for the details of bit fields.
0x4034001C Accumulator Registers {A1,A0}. See UDB_WRKONE_A0 for the details of bit fields.
0x40340020 Accumulator Registers {A1,A0}. See UDB_WRKONE_A0 for the details of bit fields.
0x40340024 Accumulator Registers {A1,A0}. See UDB_WRKONE_A0 for the details of bit fields.
0x40340028 Accumulator Registers {A1,A0}. See UDB_WRKONE_A0 for the details of bit fields.
0x4034002C Accumulator Registers {A1,A0}. See UDB_WRKONE_A0 for the details of bit fields.
0x40340100 Data Registers {D1,D0}
0x40340104 Data Registers {D1,D0}. See UDB_WRKONE_D0 for the details of bit fields.
0x40340108 Data Registers {D1,D0}. See UDB_WRKONE_D0 for the details of bit fields.
0x4034010C Data Registers {D1,D0}. See UDB_WRKONE_D0 for the details of bit fields.
0x40340110 Data Registers {D1,D0}. See UDB_WRKONE_D0 for the details of bit fields.
0x40340114 Data Registers {D1,D0}. See UDB_WRKONE_D0 for the details of bit fields.
0x40340118 Data Registers {D1,D0}. See UDB_WRKONE_D0 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
806
Universal Digital Block (UDB) Registers
Register UDB_WRKONE_D7 UDB_WRKONE_D8 UDB_WRKONE_D9 UDB_WRKONE_D10 UDB_WRKONE_D11 UDB_WRKONE_F0 UDB_WRKONE_F1 UDB_WRKONE_F2 UDB_WRKONE_F3 UDB_WRKONE_F4 UDB_WRKONE_F5 UDB_WRKONE_F6 UDB_WRKONE_F7 UDB_WRKONE_F8 UDB_WRKONE_F9 UDB_WRKONE_F10 UDB_WRKONE_F11 UDB_WRKONE_CTL_ST0 UDB_WRKONE_CTL_ST1 UDB_WRKONE_CTL_ST2 UDB_WRKONE_CTL_ST3 UDB_WRKONE_CTL_ST4 UDB_WRKONE_CTL_ST5 UDB_WRKONE_CTL_ST6 UDB_WRKONE_CTL_ST7 UDB_WRKONE_CTL_ST8 UDB_WRKONE_CTL_ST9 UDB_WRKONE_CTL_ST10 UDB_WRKONE_CTL_ST11
Address
Description
0x4034011C Data Registers {D1,D0}. See UDB_WRKONE_D0 for the details of bit fields.
0x40340120 Data Registers {D1,D0}. See UDB_WRKONE_D0 for the details of bit fields.
0x40340124 Data Registers {D1,D0}. See UDB_WRKONE_D0 for the details of bit fields.
0x40340128 Data Registers {D1,D0}. See UDB_WRKONE_D0 for the details of bit fields.
0x4034012C Data Registers {D1,D0}. See UDB_WRKONE_D0 for the details of bit fields.
0x40340200 FIFOs {F1,F0}
0x40340204 FIFOs {F1,F0}. See UDB_WRKONE_F0 for the details of bit fields.
0x40340208 FIFOs {F1,F0}. See UDB_WRKONE_F0 for the details of bit fields.
0x4034020C FIFOs {F1,F0}. See UDB_WRKONE_F0 for the details of bit fields.
0x40340210 FIFOs {F1,F0}. See UDB_WRKONE_F0 for the details of bit fields.
0x40340214 FIFOs {F1,F0}. See UDB_WRKONE_F0 for the details of bit fields.
0x40340218 FIFOs {F1,F0}. See UDB_WRKONE_F0 for the details of bit fields.
0x4034021C FIFOs {F1,F0}. See UDB_WRKONE_F0 for the details of bit fields.
0x40340220 FIFOs {F1,F0}. See UDB_WRKONE_F0 for the details of bit fields.
0x40340224 FIFOs {F1,F0}. See UDB_WRKONE_F0 for the details of bit fields.
0x40340228 FIFOs {F1,F0}. See UDB_WRKONE_F0 for the details of bit fields.
0x4034022C FIFOs {F1,F0}. See UDB_WRKONE_F0 for the details of bit fields.
0x40340300 Status and Control Registers {CTL,ST}
0x40340304 0x40340308 0x4034030C 0x40340310 0x40340314 0x40340318 0x4034031C 0x40340320 0x40340324 0x40340328 0x4034032C
Status and Control Registers {CTL,ST}. See UDB_WRKONE_CTL_ST0 for the details of bit fields.
Status and Control Registers {CTL,ST}. See UDB_WRKONE_CTL_ST0 for the details of bit fields.
Status and Control Registers {CTL,ST}. See UDB_WRKONE_CTL_ST0 for the details of bit fields.
Status and Control Registers {CTL,ST}. See UDB_WRKONE_CTL_ST0 for the details of bit fields.
Status and Control Registers {CTL,ST}. See UDB_WRKONE_CTL_ST0 for the details of bit fields.
Status and Control Registers {CTL,ST}. See UDB_WRKONE_CTL_ST0 for the details of bit fields.
Status and Control Registers {CTL,ST}. See UDB_WRKONE_CTL_ST0 for the details of bit fields.
Status and Control Registers {CTL,ST}. See UDB_WRKONE_CTL_ST0 for the details of bit fields.
Status and Control Registers {CTL,ST}. See UDB_WRKONE_CTL_ST0 for the details of bit fields.
Status and Control Registers {CTL,ST}. See UDB_WRKONE_CTL_ST0 for the details of bit fields.
Status and Control Registers {CTL,ST}. See UDB_WRKONE_CTL_ST0 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
807
Register UDB_WRKONE_ACTL_MSK0 UDB_WRKONE_ACTL_MSK1 UDB_WRKONE_ACTL_MSK2 UDB_WRKONE_ACTL_MSK3 UDB_WRKONE_ACTL_MSK4 UDB_WRKONE_ACTL_MSK5 UDB_WRKONE_ACTL_MSK6 UDB_WRKONE_ACTL_MSK7 UDB_WRKONE_ACTL_MSK8 UDB_WRKONE_ACTL_MSK9 UDB_WRKONE_ACTL_MSK10 UDB_WRKONE_ACTL_MSK11 UDB_WRKONE_MC0 UDB_WRKONE_MC1 UDB_WRKONE_MC2 UDB_WRKONE_MC3 UDB_WRKONE_MC4 UDB_WRKONE_MC5 UDB_WRKONE_MC6 UDB_WRKONE_MC7 UDB_WRKONE_MC8 UDB_WRKONE_MC9 UDB_WRKONE_MC10 UDB_WRKONE_MC11 UDB_WRKMULT_A00 UDB_WRKMULT_A01 UDB_WRKMULT_A02 UDB_WRKMULT_A03 UDB_WRKMULT_A04
Universal Digital Block (UDB) Registers
Address
Description
0x40340400 Mask and Auxiliary Control Registers {ACTL,MSK}
0x40340404 0x40340408 0x4034040C 0x40340410 0x40340414 0x40340418 0x4034041C 0x40340420 0x40340424 0x40340428 0x4034042C
Mask and Auxiliary Control Registers {ACTL,MSK}. See UDB_WRKONE_ACTL_MSK0 for the details of bit fields.
Mask and Auxiliary Control Registers {ACTL,MSK}. See UDB_WRKONE_ACTL_MSK0 for the details of bit fields.
Mask and Auxiliary Control Registers {ACTL,MSK}. See UDB_WRKONE_ACTL_MSK0 for the details of bit fields.
Mask and Auxiliary Control Registers {ACTL,MSK}. See UDB_WRKONE_ACTL_MSK0 for the details of bit fields.
Mask and Auxiliary Control Registers {ACTL,MSK}. See UDB_WRKONE_ACTL_MSK0 for the details of bit fields.
Mask and Auxiliary Control Registers {ACTL,MSK}. See UDB_WRKONE_ACTL_MSK0 for the details of bit fields.
Mask and Auxiliary Control Registers {ACTL,MSK}. See UDB_WRKONE_ACTL_MSK0 for the details of bit fields.
Mask and Auxiliary Control Registers {ACTL,MSK}. See UDB_WRKONE_ACTL_MSK0 for the details of bit fields.
Mask and Auxiliary Control Registers {ACTL,MSK}. See UDB_WRKONE_ACTL_MSK0 for the details of bit fields.
Mask and Auxiliary Control Registers {ACTL,MSK}. See UDB_WRKONE_ACTL_MSK0 for the details of bit fields.
Mask and Auxiliary Control Registers {ACTL,MSK}. See UDB_WRKONE_ACTL_MSK0 for the details of bit fields.
0x40340500 PLD Macrocell Read Registers {00,MC}
0x40340504 0x40340508 0x4034050C 0x40340510 0x40340514 0x40340518 0x4034051C 0x40340520 0x40340524 0x40340528 0x4034052C
PLD Macrocell Read Registers {00,MC}. See UDB_WRKONE_MC0 for the details of bit fields.
PLD Macrocell Read Registers {00,MC}. See UDB_WRKONE_MC0 for the details of bit fields.
PLD Macrocell Read Registers {00,MC}. See UDB_WRKONE_MC0 for the details of bit fields.
PLD Macrocell Read Registers {00,MC}. See UDB_WRKONE_MC0 for the details of bit fields.
PLD Macrocell Read Registers {00,MC}. See UDB_WRKONE_MC0 for the details of bit fields.
PLD Macrocell Read Registers {00,MC}. See UDB_WRKONE_MC0 for the details of bit fields.
PLD Macrocell Read Registers {00,MC}. See UDB_WRKONE_MC0 for the details of bit fields.
PLD Macrocell Read Registers {00,MC}. See UDB_WRKONE_MC0 for the details of bit fields.
PLD Macrocell Read Registers {00,MC}. See UDB_WRKONE_MC0 for the details of bit fields.
PLD Macrocell Read Registers {00,MC}. See UDB_WRKONE_MC0 for the details of bit fields.
PLD Macrocell Read Registers {00,MC}. See UDB_WRKONE_MC0 for the details of bit fields.
0x40341000 Accumulator 0
0x40341004 Accumulator 0. See UDB_WRKMULT_A00 for the details of bit fields.
0x40341008 Accumulator 0. See UDB_WRKMULT_A00 for the details of bit fields.
0x4034100C Accumulator 0. See UDB_WRKMULT_A00 for the details of bit fields.
0x40341010 Accumulator 0. See UDB_WRKMULT_A00 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
808
Register UDB_WRKMULT_A05 UDB_WRKMULT_A06 UDB_WRKMULT_A07 UDB_WRKMULT_A08 UDB_WRKMULT_A09 UDB_WRKMULT_A010 UDB_WRKMULT_A011 UDB_WRKMULT_A10 UDB_WRKMULT_A11 UDB_WRKMULT_A12 UDB_WRKMULT_A13 UDB_WRKMULT_A14 UDB_WRKMULT_A15 UDB_WRKMULT_A16 UDB_WRKMULT_A17 UDB_WRKMULT_A18 UDB_WRKMULT_A19 UDB_WRKMULT_A110 UDB_WRKMULT_A111 UDB_WRKMULT_D00 UDB_WRKMULT_D01 UDB_WRKMULT_D02 UDB_WRKMULT_D03 UDB_WRKMULT_D04 UDB_WRKMULT_D05 UDB_WRKMULT_D06 UDB_WRKMULT_D07 UDB_WRKMULT_D08 UDB_WRKMULT_D09
Universal Digital Block (UDB) Registers
Address
Description
0x40341014 Accumulator 0. See UDB_WRKMULT_A00 for the details of bit fields.
0x40341018 Accumulator 0. See UDB_WRKMULT_A00 for the details of bit fields.
0x4034101C Accumulator 0. See UDB_WRKMULT_A00 for the details of bit fields.
0x40341020 Accumulator 0. See UDB_WRKMULT_A00 for the details of bit fields.
0x40341024 Accumulator 0. See UDB_WRKMULT_A00 for the details of bit fields.
0x40341028 Accumulator 0. See UDB_WRKMULT_A00 for the details of bit fields.
0x4034102C Accumulator 0. See UDB_WRKMULT_A00 for the details of bit fields.
0x40341100 Accumulator 1
0x40341104 Accumulator 1. See UDB_WRKMULT_A10 for the details of bit fields.
0x40341108 Accumulator 1. See UDB_WRKMULT_A10 for the details of bit fields.
0x4034110C Accumulator 1. See UDB_WRKMULT_A10 for the details of bit fields.
0x40341110 Accumulator 1. See UDB_WRKMULT_A10 for the details of bit fields.
0x40341114 Accumulator 1. See UDB_WRKMULT_A10 for the details of bit fields.
0x40341118 Accumulator 1. See UDB_WRKMULT_A10 for the details of bit fields.
0x4034111C Accumulator 1. See UDB_WRKMULT_A10 for the details of bit fields.
0x40341120 Accumulator 1. See UDB_WRKMULT_A10 for the details of bit fields.
0x40341124 Accumulator 1. See UDB_WRKMULT_A10 for the details of bit fields.
0x40341128 Accumulator 1. See UDB_WRKMULT_A10 for the details of bit fields.
0x4034112C Accumulator 1. See UDB_WRKMULT_A10 for the details of bit fields.
0x40341200 Data 0
0x40341204 Data 0. See UDB_WRKMULT_D00 for the details of bit fields.
0x40341208 Data 0. See UDB_WRKMULT_D00 for the details of bit fields.
0x4034120C Data 0. See UDB_WRKMULT_D00 for the details of bit fields.
0x40341210 Data 0. See UDB_WRKMULT_D00 for the details of bit fields.
0x40341214 Data 0. See UDB_WRKMULT_D00 for the details of bit fields.
0x40341218 Data 0. See UDB_WRKMULT_D00 for the details of bit fields.
0x4034121C Data 0. See UDB_WRKMULT_D00 for the details of bit fields.
0x40341220 Data 0. See UDB_WRKMULT_D00 for the details of bit fields.
0x40341224 Data 0. See UDB_WRKMULT_D00 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
809
Register UDB_WRKMULT_D010 UDB_WRKMULT_D011 UDB_WRKMULT_D10 UDB_WRKMULT_D11 UDB_WRKMULT_D12 UDB_WRKMULT_D13 UDB_WRKMULT_D14 UDB_WRKMULT_D15 UDB_WRKMULT_D16 UDB_WRKMULT_D17 UDB_WRKMULT_D18 UDB_WRKMULT_D19 UDB_WRKMULT_D110 UDB_WRKMULT_D111 UDB_WRKMULT_F00 UDB_WRKMULT_F01 UDB_WRKMULT_F02 UDB_WRKMULT_F03 UDB_WRKMULT_F04 UDB_WRKMULT_F05 UDB_WRKMULT_F06 UDB_WRKMULT_F07 UDB_WRKMULT_F08 UDB_WRKMULT_F09 UDB_WRKMULT_F010 UDB_WRKMULT_F011 UDB_WRKMULT_F10 UDB_WRKMULT_F11 UDB_WRKMULT_F12
Universal Digital Block (UDB) Registers
Address
Description
0x40341228 Data 0. See UDB_WRKMULT_D00 for the details of bit fields.
0x4034122C Data 0. See UDB_WRKMULT_D00 for the details of bit fields.
0x40341300 Data 1
0x40341304 Data 1. See UDB_WRKMULT_D10 for the details of bit fields.
0x40341308 Data 1. See UDB_WRKMULT_D10 for the details of bit fields.
0x4034130C Data 1. See UDB_WRKMULT_D10 for the details of bit fields.
0x40341310 Data 1. See UDB_WRKMULT_D10 for the details of bit fields.
0x40341314 Data 1. See UDB_WRKMULT_D10 for the details of bit fields.
0x40341318 Data 1. See UDB_WRKMULT_D10 for the details of bit fields.
0x4034131C Data 1. See UDB_WRKMULT_D10 for the details of bit fields.
0x40341320 Data 1. See UDB_WRKMULT_D10 for the details of bit fields.
0x40341324 Data 1. See UDB_WRKMULT_D10 for the details of bit fields.
0x40341328 Data 1. See UDB_WRKMULT_D10 for the details of bit fields.
0x4034132C Data 1. See UDB_WRKMULT_D10 for the details of bit fields.
0x40341400 FIFO 0
0x40341404 FIFO 0. See UDB_WRKMULT_F00 for the details of bit fields.
0x40341408 FIFO 0. See UDB_WRKMULT_F00 for the details of bit fields.
0x4034140C FIFO 0. See UDB_WRKMULT_F00 for the details of bit fields.
0x40341410 FIFO 0. See UDB_WRKMULT_F00 for the details of bit fields.
0x40341414 FIFO 0. See UDB_WRKMULT_F00 for the details of bit fields.
0x40341418 FIFO 0. See UDB_WRKMULT_F00 for the details of bit fields.
0x4034141C FIFO 0. See UDB_WRKMULT_F00 for the details of bit fields.
0x40341420 FIFO 0. See UDB_WRKMULT_F00 for the details of bit fields.
0x40341424 FIFO 0. See UDB_WRKMULT_F00 for the details of bit fields.
0x40341428 FIFO 0. See UDB_WRKMULT_F00 for the details of bit fields.
0x4034142C FIFO 0. See UDB_WRKMULT_F00 for the details of bit fields.
0x40341500 FIFO 1
0x40341504 FIFO 1. See UDB_WRKMULT_F10 for the details of bit fields.
0x40341508 FIFO 1. See UDB_WRKMULT_F10 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
810
Register UDB_WRKMULT_F13 UDB_WRKMULT_F14 UDB_WRKMULT_F15 UDB_WRKMULT_F16 UDB_WRKMULT_F17 UDB_WRKMULT_F18 UDB_WRKMULT_F19 UDB_WRKMULT_F110 UDB_WRKMULT_F111 UDB_WRKMULT_ST0 UDB_WRKMULT_ST1 UDB_WRKMULT_ST2 UDB_WRKMULT_ST3 UDB_WRKMULT_ST4 UDB_WRKMULT_ST5 UDB_WRKMULT_ST6 UDB_WRKMULT_ST7 UDB_WRKMULT_ST8 UDB_WRKMULT_ST9 UDB_WRKMULT_ST10 UDB_WRKMULT_ST11 UDB_WRKMULT_CTL0 UDB_WRKMULT_CTL1 UDB_WRKMULT_CTL2 UDB_WRKMULT_CTL3 UDB_WRKMULT_CTL4 UDB_WRKMULT_CTL5 UDB_WRKMULT_CTL6 UDB_WRKMULT_CTL7
Universal Digital Block (UDB) Registers
Address
Description
0x4034150C FIFO 1. See UDB_WRKMULT_F10 for the details of bit fields.
0x40341510 FIFO 1. See UDB_WRKMULT_F10 for the details of bit fields.
0x40341514 FIFO 1. See UDB_WRKMULT_F10 for the details of bit fields.
0x40341518 FIFO 1. See UDB_WRKMULT_F10 for the details of bit fields.
0x4034151C FIFO 1. See UDB_WRKMULT_F10 for the details of bit fields.
0x40341520 FIFO 1. See UDB_WRKMULT_F10 for the details of bit fields.
0x40341524 FIFO 1. See UDB_WRKMULT_F10 for the details of bit fields.
0x40341528 FIFO 1. See UDB_WRKMULT_F10 for the details of bit fields.
0x4034152C FIFO 1. See UDB_WRKMULT_F10 for the details of bit fields.
0x40341600 Status Register
0x40341604 Status Register. See UDB_WRKMULT_ST0 for the details of bit fields.
0x40341608 Status Register. See UDB_WRKMULT_ST0 for the details of bit fields.
0x4034160C Status Register. See UDB_WRKMULT_ST0 for the details of bit fields.
0x40341610 Status Register. See UDB_WRKMULT_ST0 for the details of bit fields.
0x40341614 Status Register. See UDB_WRKMULT_ST0 for the details of bit fields.
0x40341618 Status Register. See UDB_WRKMULT_ST0 for the details of bit fields.
0x4034161C Status Register. See UDB_WRKMULT_ST0 for the details of bit fields.
0x40341620 Status Register. See UDB_WRKMULT_ST0 for the details of bit fields.
0x40341624 Status Register. See UDB_WRKMULT_ST0 for the details of bit fields.
0x40341628 Status Register. See UDB_WRKMULT_ST0 for the details of bit fields.
0x4034162C Status Register. See UDB_WRKMULT_ST0 for the details of bit fields.
0x40341700 Control Register
0x40341704 Control Register. See UDB_WRKMULT_CTL0 for the details of bit fields.
0x40341708 Control Register. See UDB_WRKMULT_CTL0 for the details of bit fields.
0x4034170C Control Register. See UDB_WRKMULT_CTL0 for the details of bit fields.
0x40341710 Control Register. See UDB_WRKMULT_CTL0 for the details of bit fields.
0x40341714 Control Register. See UDB_WRKMULT_CTL0 for the details of bit fields.
0x40341718 Control Register. See UDB_WRKMULT_CTL0 for the details of bit fields.
0x4034171C Control Register. See UDB_WRKMULT_CTL0 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
811
Register UDB_WRKMULT_CTL8 UDB_WRKMULT_CTL9 UDB_WRKMULT_CTL10 UDB_WRKMULT_CTL11 UDB_WRKMULT_MSK0 UDB_WRKMULT_MSK1 UDB_WRKMULT_MSK2 UDB_WRKMULT_MSK3 UDB_WRKMULT_MSK4 UDB_WRKMULT_MSK5 UDB_WRKMULT_MSK6 UDB_WRKMULT_MSK7 UDB_WRKMULT_MSK8 UDB_WRKMULT_MSK9 UDB_WRKMULT_MSK10 UDB_WRKMULT_MSK11 UDB_WRKMULT_ACTL0 UDB_WRKMULT_ACTL1 UDB_WRKMULT_ACTL2 UDB_WRKMULT_ACTL3 UDB_WRKMULT_ACTL4 UDB_WRKMULT_ACTL5 UDB_WRKMULT_ACTL6 UDB_WRKMULT_ACTL7 UDB_WRKMULT_ACTL8 UDB_WRKMULT_ACTL9 UDB_WRKMULT_ACTL10 UDB_WRKMULT_ACTL11 UDB_WRKMULT_MC0
Universal Digital Block (UDB) Registers
Address
Description
0x40341720 Control Register. See UDB_WRKMULT_CTL0 for the details of bit fields.
0x40341724 Control Register. See UDB_WRKMULT_CTL0 for the details of bit fields.
0x40341728 Control Register. See UDB_WRKMULT_CTL0 for the details of bit fields.
0x4034172C Control Register. See UDB_WRKMULT_CTL0 for the details of bit fields.
0x40341800 Interrupt Mask
0x40341804 Interrupt Mask. See UDB_WRKMULT_MSK0 for the details of bit fields.
0x40341808 Interrupt Mask. See UDB_WRKMULT_MSK0 for the details of bit fields.
0x4034180C Interrupt Mask. See UDB_WRKMULT_MSK0 for the details of bit fields.
0x40341810 Interrupt Mask. See UDB_WRKMULT_MSK0 for the details of bit fields.
0x40341814 Interrupt Mask. See UDB_WRKMULT_MSK0 for the details of bit fields.
0x40341818 Interrupt Mask. See UDB_WRKMULT_MSK0 for the details of bit fields.
0x4034181C Interrupt Mask. See UDB_WRKMULT_MSK0 for the details of bit fields.
0x40341820 Interrupt Mask. See UDB_WRKMULT_MSK0 for the details of bit fields.
0x40341824 Interrupt Mask. See UDB_WRKMULT_MSK0 for the details of bit fields.
0x40341828 Interrupt Mask. See UDB_WRKMULT_MSK0 for the details of bit fields.
0x4034182C Interrupt Mask. See UDB_WRKMULT_MSK0 for the details of bit fields.
0x40341900 Auxiliary Control
0x40341904 Auxiliary Control. See UDB_WRKMULT_ACTL0 for the details of bit fields.
0x40341908 Auxiliary Control. See UDB_WRKMULT_ACTL0 for the details of bit fields.
0x4034190C Auxiliary Control. See UDB_WRKMULT_ACTL0 for the details of bit fields.
0x40341910 Auxiliary Control. See UDB_WRKMULT_ACTL0 for the details of bit fields.
0x40341914 Auxiliary Control. See UDB_WRKMULT_ACTL0 for the details of bit fields.
0x40341918 Auxiliary Control. See UDB_WRKMULT_ACTL0 for the details of bit fields.
0x4034191C Auxiliary Control. See UDB_WRKMULT_ACTL0 for the details of bit fields.
0x40341920 Auxiliary Control. See UDB_WRKMULT_ACTL0 for the details of bit fields.
0x40341924 Auxiliary Control. See UDB_WRKMULT_ACTL0 for the details of bit fields.
0x40341928 Auxiliary Control. See UDB_WRKMULT_ACTL0 for the details of bit fields.
0x4034192C Auxiliary Control. See UDB_WRKMULT_ACTL0 for the details of bit fields.
0x40341A00 PLD Macrocell reading
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
812
Universal Digital Block (UDB) Registers
Register UDB_WRKMULT_MC1
Address
Description
0x40341A04 PLD Macrocell reading. See UDB_WRKMULT_MC0 for the details of bit fields.
UDB_WRKMULT_MC2
0x40341A08 PLD Macrocell reading. See UDB_WRKMULT_MC0 for the details of bit fields.
UDB_WRKMULT_MC3
0x40341A0C PLD Macrocell reading. See UDB_WRKMULT_MC0 for the details of bit fields.
UDB_WRKMULT_MC4
0x40341A10 PLD Macrocell reading. See UDB_WRKMULT_MC0 for the details of bit fields.
UDB_WRKMULT_MC5
0x40341A14 PLD Macrocell reading. See UDB_WRKMULT_MC0 for the details of bit fields.
UDB_WRKMULT_MC6
0x40341A18 PLD Macrocell reading. See UDB_WRKMULT_MC0 for the details of bit fields.
UDB_WRKMULT_MC7
0x40341A1C PLD Macrocell reading. See UDB_WRKMULT_MC0 for the details of bit fields.
UDB_WRKMULT_MC8
0x40341A20 PLD Macrocell reading. See UDB_WRKMULT_MC0 for the details of bit fields.
UDB_WRKMULT_MC9
0x40341A24 PLD Macrocell reading. See UDB_WRKMULT_MC0 for the details of bit fields.
UDB_WRKMULT_MC10
0x40341A28 PLD Macrocell reading. See UDB_WRKMULT_MC0 for the details of bit fields.
UDB_WRKMULT_MC11
0x40341A2C PLD Macrocell reading. See UDB_WRKMULT_MC0 for the details of bit fields.
UDB_UDBPAIR0_UDBSNG0_PLD_IT0
0x40342000 PLD Input Terms
UDB_UDBPAIR0_UDBSNG0_PLD_IT1
0x40342004 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR0_UDBSNG0_PLD_IT2
0x40342008 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR0_UDBSNG0_PLD_IT3
0x4034200C PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR0_UDBSNG0_PLD_IT4
0x40342010 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR0_UDBSNG0_PLD_IT5
0x40342014 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR0_UDBSNG0_PLD_IT6
0x40342018 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR0_UDBSNG0_PLD_IT7
0x4034201C PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR0_UDBSNG0_PLD_IT8
0x40342020 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR0_UDBSNG0_PLD_IT9
0x40342024 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR0_UDBSNG0_PLD_IT10
0x40342028 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR0_UDBSNG0_PLD_IT11
0x4034202C PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR0_UDBSNG0_PLD_ORT0
0x40342030 PLD OR Terms
UDB_UDBPAIR0_UDBSNG0_PLD_ORT1
0x40342034 PLD OR Terms
UDB_UDBPAIR0_UDBSNG0_PLD_CFG0
0x40342038 PLD configuration for Carry Enable, Constant, and XOR feedback
UDB_UDBPAIR0_UDBSNG0_PLD_CFG1
0x4034203C PLD configuration for Set / Reset selection, and Bypass control
UDB_UDBPAIR0_UDBSNG0_DPATH_CFG0 0x40342040 Datapath input selections (RAD0, RAD1, RAD2, F0_LD, F1_LD, D0_LD, D1_LD)
UDB_UDBPAIR0_UDBSNG0_DPATH_CFG1 0x40342044 Datapath input and output selections (SCI_MUX, SI_MUX, OUT0 thru OUT5)
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
813
Universal Digital Block (UDB) Registers
Register
Address
Description
UDB_UDBPAIR0_UDBSNG0_DPATH_CFG2 0x40342048 Datapath output synchronization, ALU mask, compare 0 and 1 masks
UDB_UDBPAIR0_UDBSNG0_DPATH_CFG3
0x4034204C
Datapath mask enables, shift in, carry in, compare, chaining, MSB configs; FIFO, shift and parallel input control
UDB_UDBPAIR0_UDBSNG0_DPATH_CFG4 0x40342050 Datapath FIFO and register access configuration control
UDB_UDBPAIR0_UDBSNG0_SC_CFG0
0x40342054 SC Mode 0 and 1 control registers; status register input mode; general SC configuration
UDB_UDBPAIR0_UDBSNG0_SC_CFG1
0x40342058 SC counter control
UDB_UDBPAIR0_UDBSNG0_RC_CFG0
0x4034205C PLD0, PLD1, Datatpath, and SC clock and reset control
UDB_UDBPAIR0_UDBSNG0_RC_CFG1
0x40342060 PLD0, PLD1, Datatpath, and SC clock selection, general reset control
UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 0x40342064 Datapath opcode configuration
UDB_UDBPAIR0_UDBSNG0_DPATH_OPC1 UDB_UDBPAIR0_UDBSNG0_DPATH_OPC2 UDB_UDBPAIR0_UDBSNG0_DPATH_OPC3
0x40342068 0x4034206C 0x40342070
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
UDB_UDBPAIR0_UDBSNG1_PLD_IT0
0x40342080 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR0_UDBSNG1_PLD_IT1
0x40342084 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR0_UDBSNG1_PLD_IT2
0x40342088 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR0_UDBSNG1_PLD_IT3
0x4034208C PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR0_UDBSNG1_PLD_IT4
0x40342090 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR0_UDBSNG1_PLD_IT5
0x40342094 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR0_UDBSNG1_PLD_IT6
0x40342098 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR0_UDBSNG1_PLD_IT7
0x4034209C PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR0_UDBSNG1_PLD_IT8
0x403420A0 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR0_UDBSNG1_PLD_IT9
0x403420A4 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR0_UDBSNG1_PLD_IT10
0x403420A8 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR0_UDBSNG1_PLD_IT11
0x403420AC PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR0_UDBSNG1_PLD_ORT0
0x403420B0 PLD OR Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_ORT0 for the details of bit fields.
UDB_UDBPAIR0_UDBSNG1_PLD_ORT1
0x403420B4 PLD OR Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_ORT1 for the details of bit fields.
UDB_UDBPAIR0_UDBSNG1_PLD_CFG0 UDB_UDBPAIR0_UDBSNG1_PLD_CFG1 UDB_UDBPAIR0_UDBSNG1_DPATH_CFG0 UDB_UDBPAIR0_UDBSNG1_DPATH_CFG1
0x403420B8
PLD configuration for Carry Enable, Constant, and XOR feedback. See UDB_UDBPAIR0_UDBSNG0_PLD_CFG0 for the details of bit fields.
0x403420BC
PLD configuration for Set / Reset selection, and Bypass control. See UDB_UDBPAIR0_UDBSNG0_PLD_CFG1 for the details of bit fields.
0x403420C0
Datapath input selections (RAD0, RAD1, RAD2, F0_LD, F1_LD, D0_LD, D1_LD). See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG0 for the details of bit fields.
0x403420C4
Datapath input and output selections (SCI_MUX, SI_MUX, OUT0 thru OUT5). See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG1 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
814
Universal Digital Block (UDB) Registers
Register UDB_UDBPAIR0_UDBSNG1_DPATH_CFG2 UDB_UDBPAIR0_UDBSNG1_DPATH_CFG3 UDB_UDBPAIR0_UDBSNG1_DPATH_CFG4 UDB_UDBPAIR0_UDBSNG1_SC_CFG0
Address
Description
0x403420C8 0x403420CC 0x403420D0
Datapath output synchronization, ALU mask, compare 0 and 1 masks. See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG2 for the details of bit fields.
Datapath mask enables, shift in, carry in, compare, chaining, MSB configs; FIFO, shift and parallel input control. See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG3 for the details of bit fields.
Datapath FIFO and register access configuration control. See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG4 for the details of bit fields.
0x403420D4
SC Mode 0 and 1 control registers; status register input mode; general SC configuration. See UDB_UDBPAIR0_UDBSNG0_SC_CFG0 for the details of bit fields.
UDB_UDBPAIR0_UDBSNG1_SC_CFG1
0x403420D8 SC counter control. See UDB_UDBPAIR0_UDBSNG0_SC_CFG1 for the details of bit fields.
UDB_UDBPAIR0_UDBSNG1_RC_CFG0 UDB_UDBPAIR0_UDBSNG1_RC_CFG1 UDB_UDBPAIR0_UDBSNG1_DPATH_OPC0 UDB_UDBPAIR0_UDBSNG1_DPATH_OPC1 UDB_UDBPAIR0_UDBSNG1_DPATH_OPC2 UDB_UDBPAIR0_UDBSNG1_DPATH_OPC3
0x403420DC
PLD0, PLD1, Datatpath, and SC clock and reset control. See UDB_UDBPAIR0_UDBSNG0_RC_CFG0 for the details of bit fields.
0x403420E0
PLD0, PLD1, Datatpath, and SC clock selection, general reset control. See UDB_UDBPAIR0_UDBSNG0_RC_CFG1 for the details of bit fields.
0x403420E4
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
0x403420E8
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
0x403420EC
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
0x403420F0
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
UDB_UDBPAIR0_ROUTE_TOP_V_BOT
0x40342100 Top Vertical Input (TVI) vs Bottom Vertical Input (BVI) muxing
UDB_UDBPAIR0_ROUTE_LVO1_V_2
0x40342104 Left Vertical Ouput (LVO) 1 vs 2 muxing for certain horizontals
UDB_UDBPAIR0_ROUTE_RVO1_V_2
0x40342108 Right Vertical Ouput (RVO) 1 vs 2 muxing for certain horizontals
UDB_UDBPAIR0_ROUTE_TUI_CFG0
0x4034210C Top UDB Input (TUI) selection
UDB_UDBPAIR0_ROUTE_TUI_CFG1
0x40342110 Top UDB Input (TUI) selection
UDB_UDBPAIR0_ROUTE_TUI_CFG2
0x40342114 Top UDB Input (TUI) selection
UDB_UDBPAIR0_ROUTE_TUI_CFG3
0x40342118 Top UDB Input (TUI) selection
UDB_UDBPAIR0_ROUTE_TUI_CFG4
0x4034211C Top UDB Input (TUI) selection
UDB_UDBPAIR0_ROUTE_TUI_CFG5
0x40342120 Top UDB Input (TUI) selection
UDB_UDBPAIR0_ROUTE_BUI_CFG0
0x40342124 Bottom UDB Input (BUI) selection
UDB_UDBPAIR0_ROUTE_BUI_CFG1
0x40342128 Bottom UDB Input (BUI) selection
UDB_UDBPAIR0_ROUTE_BUI_CFG2
0x4034212C Bottom UDB Input (BUI) selection
UDB_UDBPAIR0_ROUTE_BUI_CFG3
0x40342130 Bottom UDB Input (BUI) selection
UDB_UDBPAIR0_ROUTE_BUI_CFG4
0x40342134 Bottom UDB Input (BUI) selection
UDB_UDBPAIR0_ROUTE_BUI_CFG5
0x40342138 Bottom UDB Input (BUI) selection
UDB_UDBPAIR0_ROUTE_RVO_CFG0
0x4034213C Right Vertical Ouput (RVO) selection
UDB_UDBPAIR0_ROUTE_RVO_CFG1
0x40342140 Right Vertical Ouput (RVO) selection
UDB_UDBPAIR0_ROUTE_RVO_CFG2
0x40342144 Right Vertical Ouput (RVO) selection
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
815
Universal Digital Block (UDB) Registers
Register UDB_UDBPAIR0_ROUTE_RVO_CFG3 UDB_UDBPAIR0_ROUTE_LVO_CFG0 UDB_UDBPAIR0_ROUTE_LVO_CFG1 UDB_UDBPAIR0_ROUTE_RHO_CFG0 UDB_UDBPAIR0_ROUTE_RHO_CFG1 UDB_UDBPAIR0_ROUTE_RHO_CFG2 UDB_UDBPAIR0_ROUTE_LHO_CFG0 UDB_UDBPAIR0_ROUTE_LHO_CFG1 UDB_UDBPAIR0_ROUTE_LHO_CFG2 UDB_UDBPAIR0_ROUTE_LHO_CFG3 UDB_UDBPAIR0_ROUTE_LHO_CFG4 UDB_UDBPAIR0_ROUTE_LHO_CFG5 UDB_UDBPAIR0_ROUTE_LHO_CFG6 UDB_UDBPAIR0_ROUTE_LHO_CFG7 UDB_UDBPAIR0_ROUTE_LHO_CFG8 UDB_UDBPAIR0_ROUTE_LHO_CFG9 UDB_UDBPAIR0_ROUTE_LHO_CFG10 UDB_UDBPAIR0_ROUTE_LHO_CFG11 UDB_UDBPAIR1_UDBSNG0_PLD_IT0 UDB_UDBPAIR1_UDBSNG0_PLD_IT1 UDB_UDBPAIR1_UDBSNG0_PLD_IT2 UDB_UDBPAIR1_UDBSNG0_PLD_IT3 UDB_UDBPAIR1_UDBSNG0_PLD_IT4 UDB_UDBPAIR1_UDBSNG0_PLD_IT5 UDB_UDBPAIR1_UDBSNG0_PLD_IT6 UDB_UDBPAIR1_UDBSNG0_PLD_IT7 UDB_UDBPAIR1_UDBSNG0_PLD_IT8 UDB_UDBPAIR1_UDBSNG0_PLD_IT9 UDB_UDBPAIR1_UDBSNG0_PLD_IT10
Address
Description
0x40342148 Right Vertical Ouput (RVO) selection
0x4034214C Left Vertical Ouput (LVO) selection
0x40342150 Left Vertical Ouput (LVO) selection
0x40342154 Right Horizontal Out (RHO) selection
0x40342158 Right Horizontal Out (RHO) selection
0x4034215C Right Horizontal Out (RHO) selection
0x40342160 Left Horizontal Out (LHO) selection
0x40342164 Left Horizontal Out (LHO) selection
0x40342168 Left Horizontal Out (LHO) selection
0x4034216C Left Horizontal Out (LHO) selection
0x40342170 Left Horizontal Out (LHO) selection
0x40342174 Left Horizontal Out (LHO) selection
0x40342178 Left Horizontal Out (LHO) selection
0x4034217C Left Horizontal Out (LHO) selection
0x40342180 Left Horizontal Out (LHO) selection
0x40342184 Left Horizontal Out (LHO) selection
0x40342188 Left Horizontal Out (LHO) selection
0x4034218C Left Horizontal Out (LHO) selection
0x40342200 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
0x40342204 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
0x40342208 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
0x4034220C PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
0x40342210 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
0x40342214 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
0x40342218 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
0x4034221C PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
0x40342220 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
0x40342224 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
0x40342228 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
816
Universal Digital Block (UDB) Registers
Register UDB_UDBPAIR1_UDBSNG0_PLD_IT11
Address
Description
0x4034222C PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR1_UDBSNG0_PLD_ORT0
0x40342230 PLD OR Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_ORT0 for the details of bit fields.
UDB_UDBPAIR1_UDBSNG0_PLD_ORT1
0x40342234 PLD OR Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_ORT1 for the details of bit fields.
UDB_UDBPAIR1_UDBSNG0_PLD_CFG0 UDB_UDBPAIR1_UDBSNG0_PLD_CFG1 UDB_UDBPAIR1_UDBSNG0_DPATH_CFG0 UDB_UDBPAIR1_UDBSNG0_DPATH_CFG1 UDB_UDBPAIR1_UDBSNG0_DPATH_CFG2 UDB_UDBPAIR1_UDBSNG0_DPATH_CFG3 UDB_UDBPAIR1_UDBSNG0_DPATH_CFG4 UDB_UDBPAIR1_UDBSNG0_SC_CFG0
0x40342238 0x4034223C 0x40342240 0x40342244 0x40342248 0x4034224C 0x40342250 0x40342254
PLD configuration for Carry Enable, Constant, and XOR feedback. See UDB_UDBPAIR0_UDBSNG0_PLD_CFG0 for the details of bit fields.
PLD configuration for Set / Reset selection, and Bypass control. See UDB_UDBPAIR0_UDBSNG0_PLD_CFG1 for the details of bit fields.
Datapath input selections (RAD0, RAD1, RAD2, F0_LD, F1_LD, D0_LD, D1_LD). See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG0 for the details of bit fields.
Datapath input and output selections (SCI_MUX, SI_MUX, OUT0 thru OUT5). See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG1 for the details of bit fields.
Datapath output synchronization, ALU mask, compare 0 and 1 masks. See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG2 for the details of bit fields. Datapath mask enables, shift in, carry in, compare, chaining, MSB configs; FIFO, shift and parallel input control. See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG3 for the details of bit fields. Datapath FIFO and register access configuration control. See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG4 for the details of bit fields.
SC Mode 0 and 1 control registers; status register input mode; general SC configuration. See UDB_UDBPAIR0_UDBSNG0_SC_CFG0 for the details of bit fields.
UDB_UDBPAIR1_UDBSNG0_SC_CFG1
0x40342258 SC counter control. See UDB_UDBPAIR0_UDBSNG0_SC_CFG1 for the details of bit fields.
UDB_UDBPAIR1_UDBSNG0_RC_CFG0 UDB_UDBPAIR1_UDBSNG0_RC_CFG1 UDB_UDBPAIR1_UDBSNG0_DPATH_OPC0 UDB_UDBPAIR1_UDBSNG0_DPATH_OPC1 UDB_UDBPAIR1_UDBSNG0_DPATH_OPC2 UDB_UDBPAIR1_UDBSNG0_DPATH_OPC3
0x4034225C 0x40342260 0x40342264 0x40342268 0x4034226C 0x40342270
PLD0, PLD1, Datatpath, and SC clock and reset control. See UDB_UDBPAIR0_UDBSNG0_RC_CFG0 for the details of bit fields.
PLD0, PLD1, Datatpath, and SC clock selection, general reset control. See UDB_UDBPAIR0_UDBSNG0_RC_CFG1 for the details of bit fields.
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
UDB_UDBPAIR1_UDBSNG1_PLD_IT0
0x40342280 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR1_UDBSNG1_PLD_IT1
0x40342284 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR1_UDBSNG1_PLD_IT2
0x40342288 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR1_UDBSNG1_PLD_IT3
0x4034228C PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR1_UDBSNG1_PLD_IT4
0x40342290 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR1_UDBSNG1_PLD_IT5
0x40342294 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR1_UDBSNG1_PLD_IT6
0x40342298 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR1_UDBSNG1_PLD_IT7
0x4034229C PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR1_UDBSNG1_PLD_IT8
0x403422A0 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR1_UDBSNG1_PLD_IT9
0x403422A4 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR1_UDBSNG1_PLD_IT10
0x403422A8 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
817
Universal Digital Block (UDB) Registers
Register UDB_UDBPAIR1_UDBSNG1_PLD_IT11
Address
Description
0x403422AC PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR1_UDBSNG1_PLD_ORT0
0x403422B0 PLD OR Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_ORT0 for the details of bit fields.
UDB_UDBPAIR1_UDBSNG1_PLD_ORT1
0x403422B4 PLD OR Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_ORT1 for the details of bit fields.
UDB_UDBPAIR1_UDBSNG1_PLD_CFG0 UDB_UDBPAIR1_UDBSNG1_PLD_CFG1 UDB_UDBPAIR1_UDBSNG1_DPATH_CFG0 UDB_UDBPAIR1_UDBSNG1_DPATH_CFG1 UDB_UDBPAIR1_UDBSNG1_DPATH_CFG2 UDB_UDBPAIR1_UDBSNG1_DPATH_CFG3 UDB_UDBPAIR1_UDBSNG1_DPATH_CFG4 UDB_UDBPAIR1_UDBSNG1_SC_CFG0
0x403422B8
PLD configuration for Carry Enable, Constant, and XOR feedback. See UDB_UDBPAIR0_UDBSNG0_PLD_CFG0 for the details of bit fields.
0x403422BC
PLD configuration for Set / Reset selection, and Bypass control. See UDB_UDBPAIR0_UDBSNG0_PLD_CFG1 for the details of bit fields.
0x403422C0
Datapath input selections (RAD0, RAD1, RAD2, F0_LD, F1_LD, D0_LD, D1_LD). See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG0 for the details of bit fields.
0x403422C4
Datapath input and output selections (SCI_MUX, SI_MUX, OUT0 thru OUT5). See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG1 for the details of bit fields.
0x403422C8 0x403422CC 0x403422D0
Datapath output synchronization, ALU mask, compare 0 and 1 masks. See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG2 for the details of bit fields.
Datapath mask enables, shift in, carry in, compare, chaining, MSB configs; FIFO, shift and parallel input control. See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG3 for the details of bit fields.
Datapath FIFO and register access configuration control. See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG4 for the details of bit fields.
0x403422D4
SC Mode 0 and 1 control registers; status register input mode; general SC configuration. See UDB_UDBPAIR0_UDBSNG0_SC_CFG0 for the details of bit fields.
UDB_UDBPAIR1_UDBSNG1_SC_CFG1
0x403422D8 SC counter control. See UDB_UDBPAIR0_UDBSNG0_SC_CFG1 for the details of bit fields.
UDB_UDBPAIR1_UDBSNG1_RC_CFG0 UDB_UDBPAIR1_UDBSNG1_RC_CFG1 UDB_UDBPAIR1_UDBSNG1_DPATH_OPC0 UDB_UDBPAIR1_UDBSNG1_DPATH_OPC1 UDB_UDBPAIR1_UDBSNG1_DPATH_OPC2 UDB_UDBPAIR1_UDBSNG1_DPATH_OPC3 UDB_UDBPAIR1_ROUTE_TOP_V_BOT UDB_UDBPAIR1_ROUTE_LVO1_V_2 UDB_UDBPAIR1_ROUTE_RVO1_V_2 UDB_UDBPAIR1_ROUTE_TUI_CFG0 UDB_UDBPAIR1_ROUTE_TUI_CFG1 UDB_UDBPAIR1_ROUTE_TUI_CFG2 UDB_UDBPAIR1_ROUTE_TUI_CFG3 UDB_UDBPAIR1_ROUTE_TUI_CFG4 UDB_UDBPAIR1_ROUTE_TUI_CFG5 UDB_UDBPAIR1_ROUTE_BUI_CFG0 UDB_UDBPAIR1_ROUTE_BUI_CFG1
0x403422DC
PLD0, PLD1, Datatpath, and SC clock and reset control. See UDB_UDBPAIR0_UDBSNG0_RC_CFG0 for the details of bit fields.
0x403422E0
PLD0, PLD1, Datatpath, and SC clock selection, general reset control. See UDB_UDBPAIR0_UDBSNG0_RC_CFG1 for the details of bit fields.
0x403422E4
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
0x403422E8
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
0x403422EC
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
0x403422F0
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
0x40342300
Top Vertical Input (TVI) vs Bottom Vertical Input (BVI) muxing. See UDB_UDBPAIR0_ROUTE_TOP_V_BOT for the details of bit fields.
0x40342304
Left Vertical Ouput (LVO) 1 vs 2 muxing for certain horizontals. See UDB_UDBPAIR0_ROUTE_LVO1_V_2 for the details of bit fields.
0x40342308
Right Vertical Ouput (RVO) 1 vs 2 muxing for certain horizontals. See UDB_UDBPAIR0_ROUTE_RVO1_V_2 for the details of bit fields.
0x4034230C
Top UDB Input (TUI) selection. See UDB_UDBPAIR0_ROUTE_TUI_CFG0 for the details of bit fields.
0x40342310
Top UDB Input (TUI) selection. See UDB_UDBPAIR0_ROUTE_TUI_CFG1 for the details of bit fields.
0x40342314
Top UDB Input (TUI) selection. See UDB_UDBPAIR0_ROUTE_TUI_CFG2 for the details of bit fields.
0x40342318
Top UDB Input (TUI) selection. See UDB_UDBPAIR0_ROUTE_TUI_CFG3 for the details of bit fields.
0x4034231C
Top UDB Input (TUI) selection. See UDB_UDBPAIR0_ROUTE_TUI_CFG4 for the details of bit fields.
0x40342320
Top UDB Input (TUI) selection. See UDB_UDBPAIR0_ROUTE_TUI_CFG5 for the details of bit fields.
0x40342324
Bottom UDB Input (BUI) selection. See UDB_UDBPAIR0_ROUTE_BUI_CFG0 for the details of bit fields.
0x40342328
Bottom UDB Input (BUI) selection. See UDB_UDBPAIR0_ROUTE_BUI_CFG1 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
818
Universal Digital Block (UDB) Registers
Register UDB_UDBPAIR1_ROUTE_BUI_CFG2 UDB_UDBPAIR1_ROUTE_BUI_CFG3 UDB_UDBPAIR1_ROUTE_BUI_CFG4 UDB_UDBPAIR1_ROUTE_BUI_CFG5 UDB_UDBPAIR1_ROUTE_RVO_CFG0 UDB_UDBPAIR1_ROUTE_RVO_CFG1 UDB_UDBPAIR1_ROUTE_RVO_CFG2 UDB_UDBPAIR1_ROUTE_RVO_CFG3 UDB_UDBPAIR1_ROUTE_LVO_CFG0 UDB_UDBPAIR1_ROUTE_LVO_CFG1 UDB_UDBPAIR1_ROUTE_RHO_CFG0 UDB_UDBPAIR1_ROUTE_RHO_CFG1 UDB_UDBPAIR1_ROUTE_RHO_CFG2 UDB_UDBPAIR1_ROUTE_LHO_CFG0 UDB_UDBPAIR1_ROUTE_LHO_CFG1 UDB_UDBPAIR1_ROUTE_LHO_CFG2 UDB_UDBPAIR1_ROUTE_LHO_CFG3 UDB_UDBPAIR1_ROUTE_LHO_CFG4 UDB_UDBPAIR1_ROUTE_LHO_CFG5 UDB_UDBPAIR1_ROUTE_LHO_CFG6 UDB_UDBPAIR1_ROUTE_LHO_CFG7 UDB_UDBPAIR1_ROUTE_LHO_CFG8 UDB_UDBPAIR1_ROUTE_LHO_CFG9 UDB_UDBPAIR1_ROUTE_LHO_CFG10 UDB_UDBPAIR1_ROUTE_LHO_CFG11 UDB_UDBPAIR2_UDBSNG0_PLD_IT0 UDB_UDBPAIR2_UDBSNG0_PLD_IT1 UDB_UDBPAIR2_UDBSNG0_PLD_IT2 UDB_UDBPAIR2_UDBSNG0_PLD_IT3
Address
Description
0x4034232C
Bottom UDB Input (BUI) selection. See UDB_UDBPAIR0_ROUTE_BUI_CFG2 for the details of bit fields.
0x40342330
Bottom UDB Input (BUI) selection. See UDB_UDBPAIR0_ROUTE_BUI_CFG3 for the details of bit fields.
0x40342334
Bottom UDB Input (BUI) selection. See UDB_UDBPAIR0_ROUTE_BUI_CFG4 for the details of bit fields.
0x40342338
Bottom UDB Input (BUI) selection. See UDB_UDBPAIR0_ROUTE_BUI_CFG5 for the details of bit fields.
0x4034233C
Right Vertical Ouput (RVO) selection. See UDB_UDBPAIR0_ROUTE_RVO_CFG0 for the details of bit fields.
0x40342340
Right Vertical Ouput (RVO) selection. See UDB_UDBPAIR0_ROUTE_RVO_CFG1 for the details of bit fields.
0x40342344
Right Vertical Ouput (RVO) selection. See UDB_UDBPAIR0_ROUTE_RVO_CFG2 for the details of bit fields.
0x40342348
Right Vertical Ouput (RVO) selection. See UDB_UDBPAIR0_ROUTE_RVO_CFG3 for the details of bit fields.
0x4034234C
Left Vertical Ouput (LVO) selection. See UDB_UDBPAIR0_ROUTE_LVO_CFG0 for the details of bit fields.
0x40342350
Left Vertical Ouput (LVO) selection. See UDB_UDBPAIR0_ROUTE_LVO_CFG1 for the details of bit fields.
0x40342354
Right Horizontal Out (RHO) selection. See UDB_UDBPAIR0_ROUTE_RHO_CFG0 for the details of bit fields.
0x40342358
Right Horizontal Out (RHO) selection. See UDB_UDBPAIR0_ROUTE_RHO_CFG1 for the details of bit fields.
0x4034235C
Right Horizontal Out (RHO) selection. See UDB_UDBPAIR0_ROUTE_RHO_CFG2 for the details of bit fields.
0x40342360
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG0 for the details of bit fields.
0x40342364
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG1 for the details of bit fields.
0x40342368
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG2 for the details of bit fields.
0x4034236C
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG3 for the details of bit fields.
0x40342370
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG4 for the details of bit fields.
0x40342374
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG5 for the details of bit fields.
0x40342378
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG6 for the details of bit fields.
0x4034237C
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG7 for the details of bit fields.
0x40342380
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG8 for the details of bit fields.
0x40342384
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG9 for the details of bit fields.
0x40342388
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG10 for the details of bit fields.
0x4034238C
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG11 for the details of bit fields.
0x40342400 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
0x40342404 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
0x40342408 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
0x4034240C PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
819
Universal Digital Block (UDB) Registers
Register UDB_UDBPAIR2_UDBSNG0_PLD_IT4
Address
Description
0x40342410 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR2_UDBSNG0_PLD_IT5
0x40342414 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR2_UDBSNG0_PLD_IT6
0x40342418 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR2_UDBSNG0_PLD_IT7
0x4034241C PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR2_UDBSNG0_PLD_IT8
0x40342420 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR2_UDBSNG0_PLD_IT9
0x40342424 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR2_UDBSNG0_PLD_IT10
0x40342428 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR2_UDBSNG0_PLD_IT11
0x4034242C PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR2_UDBSNG0_PLD_ORT0
0x40342430 PLD OR Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_ORT0 for the details of bit fields.
UDB_UDBPAIR2_UDBSNG0_PLD_ORT1
0x40342434 PLD OR Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_ORT1 for the details of bit fields.
UDB_UDBPAIR2_UDBSNG0_PLD_CFG0 UDB_UDBPAIR2_UDBSNG0_PLD_CFG1 UDB_UDBPAIR2_UDBSNG0_DPATH_CFG0 UDB_UDBPAIR2_UDBSNG0_DPATH_CFG1 UDB_UDBPAIR2_UDBSNG0_DPATH_CFG2 UDB_UDBPAIR2_UDBSNG0_DPATH_CFG3 UDB_UDBPAIR2_UDBSNG0_DPATH_CFG4 UDB_UDBPAIR2_UDBSNG0_SC_CFG0
0x40342438 0x4034243C 0x40342440 0x40342444 0x40342448 0x4034244C 0x40342450 0x40342454
PLD configuration for Carry Enable, Constant, and XOR feedback. See UDB_UDBPAIR0_UDBSNG0_PLD_CFG0 for the details of bit fields.
PLD configuration for Set / Reset selection, and Bypass control. See UDB_UDBPAIR0_UDBSNG0_PLD_CFG1 for the details of bit fields.
Datapath input selections (RAD0, RAD1, RAD2, F0_LD, F1_LD, D0_LD, D1_LD). See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG0 for the details of bit fields.
Datapath input and output selections (SCI_MUX, SI_MUX, OUT0 thru OUT5). See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG1 for the details of bit fields.
Datapath output synchronization, ALU mask, compare 0 and 1 masks. See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG2 for the details of bit fields. Datapath mask enables, shift in, carry in, compare, chaining, MSB configs; FIFO, shift and parallel input control. See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG3 for the details of bit fields. Datapath FIFO and register access configuration control. See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG4 for the details of bit fields.
SC Mode 0 and 1 control registers; status register input mode; general SC configuration. See UDB_UDBPAIR0_UDBSNG0_SC_CFG0 for the details of bit fields.
UDB_UDBPAIR2_UDBSNG0_SC_CFG1
0x40342458 SC counter control. See UDB_UDBPAIR0_UDBSNG0_SC_CFG1 for the details of bit fields.
UDB_UDBPAIR2_UDBSNG0_RC_CFG0 UDB_UDBPAIR2_UDBSNG0_RC_CFG1 UDB_UDBPAIR2_UDBSNG0_DPATH_OPC0 UDB_UDBPAIR2_UDBSNG0_DPATH_OPC1 UDB_UDBPAIR2_UDBSNG0_DPATH_OPC2 UDB_UDBPAIR2_UDBSNG0_DPATH_OPC3
0x4034245C 0x40342460 0x40342464 0x40342468 0x4034246C 0x40342470
PLD0, PLD1, Datatpath, and SC clock and reset control. See UDB_UDBPAIR0_UDBSNG0_RC_CFG0 for the details of bit fields.
PLD0, PLD1, Datatpath, and SC clock selection, general reset control. See UDB_UDBPAIR0_UDBSNG0_RC_CFG1 for the details of bit fields.
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
UDB_UDBPAIR2_UDBSNG1_PLD_IT0
0x40342480 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR2_UDBSNG1_PLD_IT1
0x40342484 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR2_UDBSNG1_PLD_IT2
0x40342488 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR2_UDBSNG1_PLD_IT3
0x4034248C PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
820
Universal Digital Block (UDB) Registers
Register UDB_UDBPAIR2_UDBSNG1_PLD_IT4
Address
Description
0x40342490 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR2_UDBSNG1_PLD_IT5
0x40342494 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR2_UDBSNG1_PLD_IT6
0x40342498 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR2_UDBSNG1_PLD_IT7
0x4034249C PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR2_UDBSNG1_PLD_IT8
0x403424A0 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR2_UDBSNG1_PLD_IT9
0x403424A4 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR2_UDBSNG1_PLD_IT10
0x403424A8 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR2_UDBSNG1_PLD_IT11
0x403424AC PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR2_UDBSNG1_PLD_ORT0
0x403424B0 PLD OR Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_ORT0 for the details of bit fields.
UDB_UDBPAIR2_UDBSNG1_PLD_ORT1
0x403424B4 PLD OR Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_ORT1 for the details of bit fields.
UDB_UDBPAIR2_UDBSNG1_PLD_CFG0 UDB_UDBPAIR2_UDBSNG1_PLD_CFG1 UDB_UDBPAIR2_UDBSNG1_DPATH_CFG0 UDB_UDBPAIR2_UDBSNG1_DPATH_CFG1 UDB_UDBPAIR2_UDBSNG1_DPATH_CFG2 UDB_UDBPAIR2_UDBSNG1_DPATH_CFG3 UDB_UDBPAIR2_UDBSNG1_DPATH_CFG4 UDB_UDBPAIR2_UDBSNG1_SC_CFG0
0x403424B8
PLD configuration for Carry Enable, Constant, and XOR feedback. See UDB_UDBPAIR0_UDBSNG0_PLD_CFG0 for the details of bit fields.
0x403424BC
PLD configuration for Set / Reset selection, and Bypass control. See UDB_UDBPAIR0_UDBSNG0_PLD_CFG1 for the details of bit fields.
0x403424C0
Datapath input selections (RAD0, RAD1, RAD2, F0_LD, F1_LD, D0_LD, D1_LD). See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG0 for the details of bit fields.
0x403424C4
Datapath input and output selections (SCI_MUX, SI_MUX, OUT0 thru OUT5). See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG1 for the details of bit fields.
0x403424C8 0x403424CC 0x403424D0
Datapath output synchronization, ALU mask, compare 0 and 1 masks. See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG2 for the details of bit fields.
Datapath mask enables, shift in, carry in, compare, chaining, MSB configs; FIFO, shift and parallel input control. See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG3 for the details of bit fields.
Datapath FIFO and register access configuration control. See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG4 for the details of bit fields.
0x403424D4
SC Mode 0 and 1 control registers; status register input mode; general SC configuration. See UDB_UDBPAIR0_UDBSNG0_SC_CFG0 for the details of bit fields.
UDB_UDBPAIR2_UDBSNG1_SC_CFG1
0x403424D8 SC counter control. See UDB_UDBPAIR0_UDBSNG0_SC_CFG1 for the details of bit fields.
UDB_UDBPAIR2_UDBSNG1_RC_CFG0 UDB_UDBPAIR2_UDBSNG1_RC_CFG1 UDB_UDBPAIR2_UDBSNG1_DPATH_OPC0 UDB_UDBPAIR2_UDBSNG1_DPATH_OPC1 UDB_UDBPAIR2_UDBSNG1_DPATH_OPC2 UDB_UDBPAIR2_UDBSNG1_DPATH_OPC3 UDB_UDBPAIR2_ROUTE_TOP_V_BOT UDB_UDBPAIR2_ROUTE_LVO1_V_2 UDB_UDBPAIR2_ROUTE_RVO1_V_2 UDB_UDBPAIR2_ROUTE_TUI_CFG0
0x403424DC
PLD0, PLD1, Datatpath, and SC clock and reset control. See UDB_UDBPAIR0_UDBSNG0_RC_CFG0 for the details of bit fields.
0x403424E0
PLD0, PLD1, Datatpath, and SC clock selection, general reset control. See UDB_UDBPAIR0_UDBSNG0_RC_CFG1 for the details of bit fields.
0x403424E4
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
0x403424E8
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
0x403424EC
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
0x403424F0
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
0x40342500
Top Vertical Input (TVI) vs Bottom Vertical Input (BVI) muxing. See UDB_UDBPAIR0_ROUTE_TOP_V_BOT for the details of bit fields.
0x40342504
Left Vertical Ouput (LVO) 1 vs 2 muxing for certain horizontals. See UDB_UDBPAIR0_ROUTE_LVO1_V_2 for the details of bit fields.
0x40342508
Right Vertical Ouput (RVO) 1 vs 2 muxing for certain horizontals. See UDB_UDBPAIR0_ROUTE_RVO1_V_2 for the details of bit fields.
0x4034250C
Top UDB Input (TUI) selection. See UDB_UDBPAIR0_ROUTE_TUI_CFG0 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
821
Universal Digital Block (UDB) Registers
Register UDB_UDBPAIR2_ROUTE_TUI_CFG1 UDB_UDBPAIR2_ROUTE_TUI_CFG2 UDB_UDBPAIR2_ROUTE_TUI_CFG3 UDB_UDBPAIR2_ROUTE_TUI_CFG4 UDB_UDBPAIR2_ROUTE_TUI_CFG5 UDB_UDBPAIR2_ROUTE_BUI_CFG0 UDB_UDBPAIR2_ROUTE_BUI_CFG1 UDB_UDBPAIR2_ROUTE_BUI_CFG2 UDB_UDBPAIR2_ROUTE_BUI_CFG3 UDB_UDBPAIR2_ROUTE_BUI_CFG4 UDB_UDBPAIR2_ROUTE_BUI_CFG5 UDB_UDBPAIR2_ROUTE_RVO_CFG0 UDB_UDBPAIR2_ROUTE_RVO_CFG1 UDB_UDBPAIR2_ROUTE_RVO_CFG2 UDB_UDBPAIR2_ROUTE_RVO_CFG3 UDB_UDBPAIR2_ROUTE_LVO_CFG0 UDB_UDBPAIR2_ROUTE_LVO_CFG1 UDB_UDBPAIR2_ROUTE_RHO_CFG0 UDB_UDBPAIR2_ROUTE_RHO_CFG1 UDB_UDBPAIR2_ROUTE_RHO_CFG2 UDB_UDBPAIR2_ROUTE_LHO_CFG0 UDB_UDBPAIR2_ROUTE_LHO_CFG1 UDB_UDBPAIR2_ROUTE_LHO_CFG2 UDB_UDBPAIR2_ROUTE_LHO_CFG3 UDB_UDBPAIR2_ROUTE_LHO_CFG4 UDB_UDBPAIR2_ROUTE_LHO_CFG5 UDB_UDBPAIR2_ROUTE_LHO_CFG6 UDB_UDBPAIR2_ROUTE_LHO_CFG7 UDB_UDBPAIR2_ROUTE_LHO_CFG8
Address
Description
0x40342510
Top UDB Input (TUI) selection. See UDB_UDBPAIR0_ROUTE_TUI_CFG1 for the details of bit fields.
0x40342514
Top UDB Input (TUI) selection. See UDB_UDBPAIR0_ROUTE_TUI_CFG2 for the details of bit fields.
0x40342518
Top UDB Input (TUI) selection. See UDB_UDBPAIR0_ROUTE_TUI_CFG3 for the details of bit fields.
0x4034251C
Top UDB Input (TUI) selection. See UDB_UDBPAIR0_ROUTE_TUI_CFG4 for the details of bit fields.
0x40342520
Top UDB Input (TUI) selection. See UDB_UDBPAIR0_ROUTE_TUI_CFG5 for the details of bit fields.
0x40342524
Bottom UDB Input (BUI) selection. See UDB_UDBPAIR0_ROUTE_BUI_CFG0 for the details of bit fields.
0x40342528
Bottom UDB Input (BUI) selection. See UDB_UDBPAIR0_ROUTE_BUI_CFG1 for the details of bit fields.
0x4034252C
Bottom UDB Input (BUI) selection. See UDB_UDBPAIR0_ROUTE_BUI_CFG2 for the details of bit fields.
0x40342530
Bottom UDB Input (BUI) selection. See UDB_UDBPAIR0_ROUTE_BUI_CFG3 for the details of bit fields.
0x40342534
Bottom UDB Input (BUI) selection. See UDB_UDBPAIR0_ROUTE_BUI_CFG4 for the details of bit fields.
0x40342538
Bottom UDB Input (BUI) selection. See UDB_UDBPAIR0_ROUTE_BUI_CFG5 for the details of bit fields.
0x4034253C
Right Vertical Ouput (RVO) selection. See UDB_UDBPAIR0_ROUTE_RVO_CFG0 for the details of bit fields.
0x40342540
Right Vertical Ouput (RVO) selection. See UDB_UDBPAIR0_ROUTE_RVO_CFG1 for the details of bit fields.
0x40342544
Right Vertical Ouput (RVO) selection. See UDB_UDBPAIR0_ROUTE_RVO_CFG2 for the details of bit fields.
0x40342548
Right Vertical Ouput (RVO) selection. See UDB_UDBPAIR0_ROUTE_RVO_CFG3 for the details of bit fields.
0x4034254C
Left Vertical Ouput (LVO) selection. See UDB_UDBPAIR0_ROUTE_LVO_CFG0 for the details of bit fields.
0x40342550
Left Vertical Ouput (LVO) selection. See UDB_UDBPAIR0_ROUTE_LVO_CFG1 for the details of bit fields.
0x40342554
Right Horizontal Out (RHO) selection. See UDB_UDBPAIR0_ROUTE_RHO_CFG0 for the details of bit fields.
0x40342558
Right Horizontal Out (RHO) selection. See UDB_UDBPAIR0_ROUTE_RHO_CFG1 for the details of bit fields.
0x4034255C
Right Horizontal Out (RHO) selection. See UDB_UDBPAIR0_ROUTE_RHO_CFG2 for the details of bit fields.
0x40342560
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG0 for the details of bit fields.
0x40342564
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG1 for the details of bit fields.
0x40342568
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG2 for the details of bit fields.
0x4034256C
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG3 for the details of bit fields.
0x40342570
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG4 for the details of bit fields.
0x40342574
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG5 for the details of bit fields.
0x40342578
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG6 for the details of bit fields.
0x4034257C
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG7 for the details of bit fields.
0x40342580
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG8 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
822
Universal Digital Block (UDB) Registers
Register UDB_UDBPAIR2_ROUTE_LHO_CFG9 UDB_UDBPAIR2_ROUTE_LHO_CFG10 UDB_UDBPAIR2_ROUTE_LHO_CFG11 UDB_UDBPAIR3_UDBSNG0_PLD_IT0
Address
Description
0x40342584
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG9 for the details of bit fields.
0x40342588
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG10 for the details of bit fields.
0x4034258C
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG11 for the details of bit fields.
0x40342600 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR3_UDBSNG0_PLD_IT1
0x40342604 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR3_UDBSNG0_PLD_IT2
0x40342608 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR3_UDBSNG0_PLD_IT3
0x4034260C PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR3_UDBSNG0_PLD_IT4
0x40342610 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR3_UDBSNG0_PLD_IT5
0x40342614 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR3_UDBSNG0_PLD_IT6
0x40342618 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR3_UDBSNG0_PLD_IT7
0x4034261C PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR3_UDBSNG0_PLD_IT8
0x40342620 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR3_UDBSNG0_PLD_IT9
0x40342624 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR3_UDBSNG0_PLD_IT10
0x40342628 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR3_UDBSNG0_PLD_IT11
0x4034262C PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR3_UDBSNG0_PLD_ORT0
0x40342630 PLD OR Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_ORT0 for the details of bit fields.
UDB_UDBPAIR3_UDBSNG0_PLD_ORT1
0x40342634 PLD OR Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_ORT1 for the details of bit fields.
UDB_UDBPAIR3_UDBSNG0_PLD_CFG0 UDB_UDBPAIR3_UDBSNG0_PLD_CFG1 UDB_UDBPAIR3_UDBSNG0_DPATH_CFG0 UDB_UDBPAIR3_UDBSNG0_DPATH_CFG1 UDB_UDBPAIR3_UDBSNG0_DPATH_CFG2 UDB_UDBPAIR3_UDBSNG0_DPATH_CFG3 UDB_UDBPAIR3_UDBSNG0_DPATH_CFG4 UDB_UDBPAIR3_UDBSNG0_SC_CFG0
0x40342638 0x4034263C 0x40342640 0x40342644 0x40342648 0x4034264C 0x40342650 0x40342654
PLD configuration for Carry Enable, Constant, and XOR feedback. See UDB_UDBPAIR0_UDBSNG0_PLD_CFG0 for the details of bit fields.
PLD configuration for Set / Reset selection, and Bypass control. See UDB_UDBPAIR0_UDBSNG0_PLD_CFG1 for the details of bit fields.
Datapath input selections (RAD0, RAD1, RAD2, F0_LD, F1_LD, D0_LD, D1_LD). See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG0 for the details of bit fields.
Datapath input and output selections (SCI_MUX, SI_MUX, OUT0 thru OUT5). See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG1 for the details of bit fields.
Datapath output synchronization, ALU mask, compare 0 and 1 masks. See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG2 for the details of bit fields. Datapath mask enables, shift in, carry in, compare, chaining, MSB configs; FIFO, shift and parallel input control. See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG3 for the details of bit fields. Datapath FIFO and register access configuration control. See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG4 for the details of bit fields.
SC Mode 0 and 1 control registers; status register input mode; general SC configuration. See UDB_UDBPAIR0_UDBSNG0_SC_CFG0 for the details of bit fields.
UDB_UDBPAIR3_UDBSNG0_SC_CFG1
0x40342658 SC counter control. See UDB_UDBPAIR0_UDBSNG0_SC_CFG1 for the details of bit fields.
UDB_UDBPAIR3_UDBSNG0_RC_CFG0 UDB_UDBPAIR3_UDBSNG0_RC_CFG1 UDB_UDBPAIR3_UDBSNG0_DPATH_OPC0
0x4034265C 0x40342660 0x40342664
PLD0, PLD1, Datatpath, and SC clock and reset control. See UDB_UDBPAIR0_UDBSNG0_RC_CFG0 for the details of bit fields.
PLD0, PLD1, Datatpath, and SC clock selection, general reset control. See UDB_UDBPAIR0_UDBSNG0_RC_CFG1 for the details of bit fields.
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
823
Universal Digital Block (UDB) Registers
Register UDB_UDBPAIR3_UDBSNG0_DPATH_OPC1 UDB_UDBPAIR3_UDBSNG0_DPATH_OPC2 UDB_UDBPAIR3_UDBSNG0_DPATH_OPC3
Address
Description
0x40342668
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
0x4034266C
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
0x40342670
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
UDB_UDBPAIR3_UDBSNG1_PLD_IT0
0x40342680 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR3_UDBSNG1_PLD_IT1
0x40342684 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR3_UDBSNG1_PLD_IT2
0x40342688 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR3_UDBSNG1_PLD_IT3
0x4034268C PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR3_UDBSNG1_PLD_IT4
0x40342690 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR3_UDBSNG1_PLD_IT5
0x40342694 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR3_UDBSNG1_PLD_IT6
0x40342698 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR3_UDBSNG1_PLD_IT7
0x4034269C PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR3_UDBSNG1_PLD_IT8
0x403426A0 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR3_UDBSNG1_PLD_IT9
0x403426A4 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR3_UDBSNG1_PLD_IT10
0x403426A8 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR3_UDBSNG1_PLD_IT11
0x403426AC PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR3_UDBSNG1_PLD_ORT0
0x403426B0 PLD OR Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_ORT0 for the details of bit fields.
UDB_UDBPAIR3_UDBSNG1_PLD_ORT1
0x403426B4 PLD OR Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_ORT1 for the details of bit fields.
UDB_UDBPAIR3_UDBSNG1_PLD_CFG0 UDB_UDBPAIR3_UDBSNG1_PLD_CFG1 UDB_UDBPAIR3_UDBSNG1_DPATH_CFG0 UDB_UDBPAIR3_UDBSNG1_DPATH_CFG1 UDB_UDBPAIR3_UDBSNG1_DPATH_CFG2 UDB_UDBPAIR3_UDBSNG1_DPATH_CFG3 UDB_UDBPAIR3_UDBSNG1_DPATH_CFG4 UDB_UDBPAIR3_UDBSNG1_SC_CFG0
0x403426B8
PLD configuration for Carry Enable, Constant, and XOR feedback. See UDB_UDBPAIR0_UDBSNG0_PLD_CFG0 for the details of bit fields.
0x403426BC
PLD configuration for Set / Reset selection, and Bypass control. See UDB_UDBPAIR0_UDBSNG0_PLD_CFG1 for the details of bit fields.
0x403426C0
Datapath input selections (RAD0, RAD1, RAD2, F0_LD, F1_LD, D0_LD, D1_LD). See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG0 for the details of bit fields.
0x403426C4
Datapath input and output selections (SCI_MUX, SI_MUX, OUT0 thru OUT5). See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG1 for the details of bit fields.
0x403426C8 0x403426CC 0x403426D0
Datapath output synchronization, ALU mask, compare 0 and 1 masks. See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG2 for the details of bit fields.
Datapath mask enables, shift in, carry in, compare, chaining, MSB configs; FIFO, shift and parallel input control. See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG3 for the details of bit fields.
Datapath FIFO and register access configuration control. See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG4 for the details of bit fields.
0x403426D4
SC Mode 0 and 1 control registers; status register input mode; general SC configuration. See UDB_UDBPAIR0_UDBSNG0_SC_CFG0 for the details of bit fields.
UDB_UDBPAIR3_UDBSNG1_SC_CFG1
0x403426D8 SC counter control. See UDB_UDBPAIR0_UDBSNG0_SC_CFG1 for the details of bit fields.
UDB_UDBPAIR3_UDBSNG1_RC_CFG0 UDB_UDBPAIR3_UDBSNG1_RC_CFG1 UDB_UDBPAIR3_UDBSNG1_DPATH_OPC0
0x403426DC
PLD0, PLD1, Datatpath, and SC clock and reset control. See UDB_UDBPAIR0_UDBSNG0_RC_CFG0 for the details of bit fields.
0x403426E0
PLD0, PLD1, Datatpath, and SC clock selection, general reset control. See UDB_UDBPAIR0_UDBSNG0_RC_CFG1 for the details of bit fields.
0x403426E4
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
824
Universal Digital Block (UDB) Registers
Register UDB_UDBPAIR3_UDBSNG1_DPATH_OPC1 UDB_UDBPAIR3_UDBSNG1_DPATH_OPC2 UDB_UDBPAIR3_UDBSNG1_DPATH_OPC3 UDB_UDBPAIR3_ROUTE_TOP_V_BOT UDB_UDBPAIR3_ROUTE_LVO1_V_2 UDB_UDBPAIR3_ROUTE_RVO1_V_2 UDB_UDBPAIR3_ROUTE_TUI_CFG0 UDB_UDBPAIR3_ROUTE_TUI_CFG1 UDB_UDBPAIR3_ROUTE_TUI_CFG2 UDB_UDBPAIR3_ROUTE_TUI_CFG3 UDB_UDBPAIR3_ROUTE_TUI_CFG4 UDB_UDBPAIR3_ROUTE_TUI_CFG5 UDB_UDBPAIR3_ROUTE_BUI_CFG0 UDB_UDBPAIR3_ROUTE_BUI_CFG1 UDB_UDBPAIR3_ROUTE_BUI_CFG2 UDB_UDBPAIR3_ROUTE_BUI_CFG3 UDB_UDBPAIR3_ROUTE_BUI_CFG4 UDB_UDBPAIR3_ROUTE_BUI_CFG5 UDB_UDBPAIR3_ROUTE_RVO_CFG0 UDB_UDBPAIR3_ROUTE_RVO_CFG1 UDB_UDBPAIR3_ROUTE_RVO_CFG2 UDB_UDBPAIR3_ROUTE_RVO_CFG3 UDB_UDBPAIR3_ROUTE_LVO_CFG0 UDB_UDBPAIR3_ROUTE_LVO_CFG1 UDB_UDBPAIR3_ROUTE_RHO_CFG0 UDB_UDBPAIR3_ROUTE_RHO_CFG1 UDB_UDBPAIR3_ROUTE_RHO_CFG2 UDB_UDBPAIR3_ROUTE_LHO_CFG0 UDB_UDBPAIR3_ROUTE_LHO_CFG1
Address
Description
0x403426E8
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
0x403426EC
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
0x403426F0
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
0x40342700
Top Vertical Input (TVI) vs Bottom Vertical Input (BVI) muxing. See UDB_UDBPAIR0_ROUTE_TOP_V_BOT for the details of bit fields.
0x40342704
Left Vertical Ouput (LVO) 1 vs 2 muxing for certain horizontals. See UDB_UDBPAIR0_ROUTE_LVO1_V_2 for the details of bit fields.
0x40342708
Right Vertical Ouput (RVO) 1 vs 2 muxing for certain horizontals. See UDB_UDBPAIR0_ROUTE_RVO1_V_2 for the details of bit fields.
0x4034270C
Top UDB Input (TUI) selection. See UDB_UDBPAIR0_ROUTE_TUI_CFG0 for the details of bit fields.
0x40342710
Top UDB Input (TUI) selection. See UDB_UDBPAIR0_ROUTE_TUI_CFG1 for the details of bit fields.
0x40342714
Top UDB Input (TUI) selection. See UDB_UDBPAIR0_ROUTE_TUI_CFG2 for the details of bit fields.
0x40342718
Top UDB Input (TUI) selection. See UDB_UDBPAIR0_ROUTE_TUI_CFG3 for the details of bit fields.
0x4034271C
Top UDB Input (TUI) selection. See UDB_UDBPAIR0_ROUTE_TUI_CFG4 for the details of bit fields.
0x40342720
Top UDB Input (TUI) selection. See UDB_UDBPAIR0_ROUTE_TUI_CFG5 for the details of bit fields.
0x40342724
Bottom UDB Input (BUI) selection. See UDB_UDBPAIR0_ROUTE_BUI_CFG0 for the details of bit fields.
0x40342728
Bottom UDB Input (BUI) selection. See UDB_UDBPAIR0_ROUTE_BUI_CFG1 for the details of bit fields.
0x4034272C
Bottom UDB Input (BUI) selection. See UDB_UDBPAIR0_ROUTE_BUI_CFG2 for the details of bit fields.
0x40342730
Bottom UDB Input (BUI) selection. See UDB_UDBPAIR0_ROUTE_BUI_CFG3 for the details of bit fields.
0x40342734
Bottom UDB Input (BUI) selection. See UDB_UDBPAIR0_ROUTE_BUI_CFG4 for the details of bit fields.
0x40342738
Bottom UDB Input (BUI) selection. See UDB_UDBPAIR0_ROUTE_BUI_CFG5 for the details of bit fields.
0x4034273C
Right Vertical Ouput (RVO) selection. See UDB_UDBPAIR0_ROUTE_RVO_CFG0 for the details of bit fields.
0x40342740
Right Vertical Ouput (RVO) selection. See UDB_UDBPAIR0_ROUTE_RVO_CFG1 for the details of bit fields.
0x40342744
Right Vertical Ouput (RVO) selection. See UDB_UDBPAIR0_ROUTE_RVO_CFG2 for the details of bit fields.
0x40342748
Right Vertical Ouput (RVO) selection. See UDB_UDBPAIR0_ROUTE_RVO_CFG3 for the details of bit fields.
0x4034274C
Left Vertical Ouput (LVO) selection. See UDB_UDBPAIR0_ROUTE_LVO_CFG0 for the details of bit fields.
0x40342750
Left Vertical Ouput (LVO) selection. See UDB_UDBPAIR0_ROUTE_LVO_CFG1 for the details of bit fields.
0x40342754
Right Horizontal Out (RHO) selection. See UDB_UDBPAIR0_ROUTE_RHO_CFG0 for the details of bit fields.
0x40342758
Right Horizontal Out (RHO) selection. See UDB_UDBPAIR0_ROUTE_RHO_CFG1 for the details of bit fields.
0x4034275C
Right Horizontal Out (RHO) selection. See UDB_UDBPAIR0_ROUTE_RHO_CFG2 for the details of bit fields.
0x40342760
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG0 for the details of bit fields.
0x40342764
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG1 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
825
Universal Digital Block (UDB) Registers
Register UDB_UDBPAIR3_ROUTE_LHO_CFG2 UDB_UDBPAIR3_ROUTE_LHO_CFG3 UDB_UDBPAIR3_ROUTE_LHO_CFG4 UDB_UDBPAIR3_ROUTE_LHO_CFG5 UDB_UDBPAIR3_ROUTE_LHO_CFG6 UDB_UDBPAIR3_ROUTE_LHO_CFG7 UDB_UDBPAIR3_ROUTE_LHO_CFG8 UDB_UDBPAIR3_ROUTE_LHO_CFG9 UDB_UDBPAIR3_ROUTE_LHO_CFG10 UDB_UDBPAIR3_ROUTE_LHO_CFG11 UDB_UDBPAIR4_UDBSNG0_PLD_IT0
Address
Description
0x40342768
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG2 for the details of bit fields.
0x4034276C
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG3 for the details of bit fields.
0x40342770
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG4 for the details of bit fields.
0x40342774
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG5 for the details of bit fields.
0x40342778
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG6 for the details of bit fields.
0x4034277C
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG7 for the details of bit fields.
0x40342780
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG8 for the details of bit fields.
0x40342784
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG9 for the details of bit fields.
0x40342788
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG10 for the details of bit fields.
0x4034278C
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG11 for the details of bit fields.
0x40342800 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR4_UDBSNG0_PLD_IT1
0x40342804 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR4_UDBSNG0_PLD_IT2
0x40342808 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR4_UDBSNG0_PLD_IT3
0x4034280C PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR4_UDBSNG0_PLD_IT4
0x40342810 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR4_UDBSNG0_PLD_IT5
0x40342814 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR4_UDBSNG0_PLD_IT6
0x40342818 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR4_UDBSNG0_PLD_IT7
0x4034281C PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR4_UDBSNG0_PLD_IT8
0x40342820 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR4_UDBSNG0_PLD_IT9
0x40342824 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR4_UDBSNG0_PLD_IT10
0x40342828 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR4_UDBSNG0_PLD_IT11
0x4034282C PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR4_UDBSNG0_PLD_ORT0
0x40342830 PLD OR Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_ORT0 for the details of bit fields.
UDB_UDBPAIR4_UDBSNG0_PLD_ORT1
0x40342834 PLD OR Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_ORT1 for the details of bit fields.
UDB_UDBPAIR4_UDBSNG0_PLD_CFG0 UDB_UDBPAIR4_UDBSNG0_PLD_CFG1 UDB_UDBPAIR4_UDBSNG0_DPATH_CFG0 UDB_UDBPAIR4_UDBSNG0_DPATH_CFG1 UDB_UDBPAIR4_UDBSNG0_DPATH_CFG2
0x40342838 0x4034283C 0x40342840 0x40342844 0x40342848
PLD configuration for Carry Enable, Constant, and XOR feedback. See UDB_UDBPAIR0_UDBSNG0_PLD_CFG0 for the details of bit fields.
PLD configuration for Set / Reset selection, and Bypass control. See UDB_UDBPAIR0_UDBSNG0_PLD_CFG1 for the details of bit fields.
Datapath input selections (RAD0, RAD1, RAD2, F0_LD, F1_LD, D0_LD, D1_LD). See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG0 for the details of bit fields.
Datapath input and output selections (SCI_MUX, SI_MUX, OUT0 thru OUT5). See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG1 for the details of bit fields.
Datapath output synchronization, ALU mask, compare 0 and 1 masks. See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG2 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
826
Universal Digital Block (UDB) Registers
Register UDB_UDBPAIR4_UDBSNG0_DPATH_CFG3 UDB_UDBPAIR4_UDBSNG0_DPATH_CFG4 UDB_UDBPAIR4_UDBSNG0_SC_CFG0
Address 0x4034284C 0x40342850 0x40342854
Description
Datapath mask enables, shift in, carry in, compare, chaining, MSB configs; FIFO, shift and parallel input control. See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG3 for the details of bit fields.
Datapath FIFO and register access configuration control. See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG4 for the details of bit fields.
SC Mode 0 and 1 control registers; status register input mode; general SC configuration. See UDB_UDBPAIR0_UDBSNG0_SC_CFG0 for the details of bit fields.
UDB_UDBPAIR4_UDBSNG0_SC_CFG1
0x40342858 SC counter control. See UDB_UDBPAIR0_UDBSNG0_SC_CFG1 for the details of bit fields.
UDB_UDBPAIR4_UDBSNG0_RC_CFG0 UDB_UDBPAIR4_UDBSNG0_RC_CFG1 UDB_UDBPAIR4_UDBSNG0_DPATH_OPC0 UDB_UDBPAIR4_UDBSNG0_DPATH_OPC1 UDB_UDBPAIR4_UDBSNG0_DPATH_OPC2 UDB_UDBPAIR4_UDBSNG0_DPATH_OPC3
0x4034285C 0x40342860 0x40342864 0x40342868 0x4034286C 0x40342870
PLD0, PLD1, Datatpath, and SC clock and reset control. See UDB_UDBPAIR0_UDBSNG0_RC_CFG0 for the details of bit fields.
PLD0, PLD1, Datatpath, and SC clock selection, general reset control. See UDB_UDBPAIR0_UDBSNG0_RC_CFG1 for the details of bit fields.
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
UDB_UDBPAIR4_UDBSNG1_PLD_IT0
0x40342880 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR4_UDBSNG1_PLD_IT1
0x40342884 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR4_UDBSNG1_PLD_IT2
0x40342888 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR4_UDBSNG1_PLD_IT3
0x4034288C PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR4_UDBSNG1_PLD_IT4
0x40342890 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR4_UDBSNG1_PLD_IT5
0x40342894 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR4_UDBSNG1_PLD_IT6
0x40342898 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR4_UDBSNG1_PLD_IT7
0x4034289C PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR4_UDBSNG1_PLD_IT8
0x403428A0 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR4_UDBSNG1_PLD_IT9
0x403428A4 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR4_UDBSNG1_PLD_IT10
0x403428A8 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR4_UDBSNG1_PLD_IT11
0x403428AC PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR4_UDBSNG1_PLD_ORT0
0x403428B0 PLD OR Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_ORT0 for the details of bit fields.
UDB_UDBPAIR4_UDBSNG1_PLD_ORT1
0x403428B4 PLD OR Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_ORT1 for the details of bit fields.
UDB_UDBPAIR4_UDBSNG1_PLD_CFG0 UDB_UDBPAIR4_UDBSNG1_PLD_CFG1 UDB_UDBPAIR4_UDBSNG1_DPATH_CFG0 UDB_UDBPAIR4_UDBSNG1_DPATH_CFG1 UDB_UDBPAIR4_UDBSNG1_DPATH_CFG2
0x403428B8
PLD configuration for Carry Enable, Constant, and XOR feedback. See UDB_UDBPAIR0_UDBSNG0_PLD_CFG0 for the details of bit fields.
0x403428BC
PLD configuration for Set / Reset selection, and Bypass control. See UDB_UDBPAIR0_UDBSNG0_PLD_CFG1 for the details of bit fields.
0x403428C0
Datapath input selections (RAD0, RAD1, RAD2, F0_LD, F1_LD, D0_LD, D1_LD). See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG0 for the details of bit fields.
0x403428C4
Datapath input and output selections (SCI_MUX, SI_MUX, OUT0 thru OUT5). See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG1 for the details of bit fields.
0x403428C8
Datapath output synchronization, ALU mask, compare 0 and 1 masks. See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG2 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
827
Universal Digital Block (UDB) Registers
Register UDB_UDBPAIR4_UDBSNG1_DPATH_CFG3 UDB_UDBPAIR4_UDBSNG1_DPATH_CFG4 UDB_UDBPAIR4_UDBSNG1_SC_CFG0
Address 0x403428CC 0x403428D0
Description
Datapath mask enables, shift in, carry in, compare, chaining, MSB configs; FIFO, shift and parallel input control. See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG3 for the details of bit fields.
Datapath FIFO and register access configuration control. See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG4 for the details of bit fields.
0x403428D4
SC Mode 0 and 1 control registers; status register input mode; general SC configuration. See UDB_UDBPAIR0_UDBSNG0_SC_CFG0 for the details of bit fields.
UDB_UDBPAIR4_UDBSNG1_SC_CFG1
0x403428D8 SC counter control. See UDB_UDBPAIR0_UDBSNG0_SC_CFG1 for the details of bit fields.
UDB_UDBPAIR4_UDBSNG1_RC_CFG0 UDB_UDBPAIR4_UDBSNG1_RC_CFG1 UDB_UDBPAIR4_UDBSNG1_DPATH_OPC0 UDB_UDBPAIR4_UDBSNG1_DPATH_OPC1 UDB_UDBPAIR4_UDBSNG1_DPATH_OPC2 UDB_UDBPAIR4_UDBSNG1_DPATH_OPC3 UDB_UDBPAIR4_ROUTE_TOP_V_BOT UDB_UDBPAIR4_ROUTE_LVO1_V_2 UDB_UDBPAIR4_ROUTE_RVO1_V_2 UDB_UDBPAIR4_ROUTE_TUI_CFG0 UDB_UDBPAIR4_ROUTE_TUI_CFG1 UDB_UDBPAIR4_ROUTE_TUI_CFG2 UDB_UDBPAIR4_ROUTE_TUI_CFG3 UDB_UDBPAIR4_ROUTE_TUI_CFG4 UDB_UDBPAIR4_ROUTE_TUI_CFG5 UDB_UDBPAIR4_ROUTE_BUI_CFG0 UDB_UDBPAIR4_ROUTE_BUI_CFG1 UDB_UDBPAIR4_ROUTE_BUI_CFG2 UDB_UDBPAIR4_ROUTE_BUI_CFG3 UDB_UDBPAIR4_ROUTE_BUI_CFG4 UDB_UDBPAIR4_ROUTE_BUI_CFG5 UDB_UDBPAIR4_ROUTE_RVO_CFG0 UDB_UDBPAIR4_ROUTE_RVO_CFG1 UDB_UDBPAIR4_ROUTE_RVO_CFG2 UDB_UDBPAIR4_ROUTE_RVO_CFG3
0x403428DC
PLD0, PLD1, Datatpath, and SC clock and reset control. See UDB_UDBPAIR0_UDBSNG0_RC_CFG0 for the details of bit fields.
0x403428E0
PLD0, PLD1, Datatpath, and SC clock selection, general reset control. See UDB_UDBPAIR0_UDBSNG0_RC_CFG1 for the details of bit fields.
0x403428E4
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
0x403428E8
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
0x403428EC
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
0x403428F0
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
0x40342900
Top Vertical Input (TVI) vs Bottom Vertical Input (BVI) muxing. See UDB_UDBPAIR0_ROUTE_TOP_V_BOT for the details of bit fields.
0x40342904
Left Vertical Ouput (LVO) 1 vs 2 muxing for certain horizontals. See UDB_UDBPAIR0_ROUTE_LVO1_V_2 for the details of bit fields.
0x40342908
Right Vertical Ouput (RVO) 1 vs 2 muxing for certain horizontals. See UDB_UDBPAIR0_ROUTE_RVO1_V_2 for the details of bit fields.
0x4034290C
Top UDB Input (TUI) selection. See UDB_UDBPAIR0_ROUTE_TUI_CFG0 for the details of bit fields.
0x40342910
Top UDB Input (TUI) selection. See UDB_UDBPAIR0_ROUTE_TUI_CFG1 for the details of bit fields.
0x40342914
Top UDB Input (TUI) selection. See UDB_UDBPAIR0_ROUTE_TUI_CFG2 for the details of bit fields.
0x40342918
Top UDB Input (TUI) selection. See UDB_UDBPAIR0_ROUTE_TUI_CFG3 for the details of bit fields.
0x4034291C
Top UDB Input (TUI) selection. See UDB_UDBPAIR0_ROUTE_TUI_CFG4 for the details of bit fields.
0x40342920
Top UDB Input (TUI) selection. See UDB_UDBPAIR0_ROUTE_TUI_CFG5 for the details of bit fields.
0x40342924
Bottom UDB Input (BUI) selection. See UDB_UDBPAIR0_ROUTE_BUI_CFG0 for the details of bit fields.
0x40342928
Bottom UDB Input (BUI) selection. See UDB_UDBPAIR0_ROUTE_BUI_CFG1 for the details of bit fields.
0x4034292C
Bottom UDB Input (BUI) selection. See UDB_UDBPAIR0_ROUTE_BUI_CFG2 for the details of bit fields.
0x40342930
Bottom UDB Input (BUI) selection. See UDB_UDBPAIR0_ROUTE_BUI_CFG3 for the details of bit fields.
0x40342934
Bottom UDB Input (BUI) selection. See UDB_UDBPAIR0_ROUTE_BUI_CFG4 for the details of bit fields.
0x40342938
Bottom UDB Input (BUI) selection. See UDB_UDBPAIR0_ROUTE_BUI_CFG5 for the details of bit fields.
0x4034293C
Right Vertical Ouput (RVO) selection. See UDB_UDBPAIR0_ROUTE_RVO_CFG0 for the details of bit fields.
0x40342940
Right Vertical Ouput (RVO) selection. See UDB_UDBPAIR0_ROUTE_RVO_CFG1 for the details of bit fields.
0x40342944
Right Vertical Ouput (RVO) selection. See UDB_UDBPAIR0_ROUTE_RVO_CFG2 for the details of bit fields.
0x40342948
Right Vertical Ouput (RVO) selection. See UDB_UDBPAIR0_ROUTE_RVO_CFG3 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
828
Universal Digital Block (UDB) Registers
Register UDB_UDBPAIR4_ROUTE_LVO_CFG0 UDB_UDBPAIR4_ROUTE_LVO_CFG1 UDB_UDBPAIR4_ROUTE_RHO_CFG0 UDB_UDBPAIR4_ROUTE_RHO_CFG1 UDB_UDBPAIR4_ROUTE_RHO_CFG2 UDB_UDBPAIR4_ROUTE_LHO_CFG0 UDB_UDBPAIR4_ROUTE_LHO_CFG1 UDB_UDBPAIR4_ROUTE_LHO_CFG2 UDB_UDBPAIR4_ROUTE_LHO_CFG3 UDB_UDBPAIR4_ROUTE_LHO_CFG4 UDB_UDBPAIR4_ROUTE_LHO_CFG5 UDB_UDBPAIR4_ROUTE_LHO_CFG6 UDB_UDBPAIR4_ROUTE_LHO_CFG7 UDB_UDBPAIR4_ROUTE_LHO_CFG8 UDB_UDBPAIR4_ROUTE_LHO_CFG9 UDB_UDBPAIR4_ROUTE_LHO_CFG10 UDB_UDBPAIR4_ROUTE_LHO_CFG11 UDB_UDBPAIR5_UDBSNG0_PLD_IT0 UDB_UDBPAIR5_UDBSNG0_PLD_IT1 UDB_UDBPAIR5_UDBSNG0_PLD_IT2 UDB_UDBPAIR5_UDBSNG0_PLD_IT3 UDB_UDBPAIR5_UDBSNG0_PLD_IT4 UDB_UDBPAIR5_UDBSNG0_PLD_IT5 UDB_UDBPAIR5_UDBSNG0_PLD_IT6 UDB_UDBPAIR5_UDBSNG0_PLD_IT7 UDB_UDBPAIR5_UDBSNG0_PLD_IT8 UDB_UDBPAIR5_UDBSNG0_PLD_IT9 UDB_UDBPAIR5_UDBSNG0_PLD_IT10 UDB_UDBPAIR5_UDBSNG0_PLD_IT11
Address
Description
0x4034294C
Left Vertical Ouput (LVO) selection. See UDB_UDBPAIR0_ROUTE_LVO_CFG0 for the details of bit fields.
0x40342950
Left Vertical Ouput (LVO) selection. See UDB_UDBPAIR0_ROUTE_LVO_CFG1 for the details of bit fields.
0x40342954
Right Horizontal Out (RHO) selection. See UDB_UDBPAIR0_ROUTE_RHO_CFG0 for the details of bit fields.
0x40342958
Right Horizontal Out (RHO) selection. See UDB_UDBPAIR0_ROUTE_RHO_CFG1 for the details of bit fields.
0x4034295C
Right Horizontal Out (RHO) selection. See UDB_UDBPAIR0_ROUTE_RHO_CFG2 for the details of bit fields.
0x40342960
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG0 for the details of bit fields.
0x40342964
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG1 for the details of bit fields.
0x40342968
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG2 for the details of bit fields.
0x4034296C
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG3 for the details of bit fields.
0x40342970
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG4 for the details of bit fields.
0x40342974
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG5 for the details of bit fields.
0x40342978
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG6 for the details of bit fields.
0x4034297C
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG7 for the details of bit fields.
0x40342980
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG8 for the details of bit fields.
0x40342984
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG9 for the details of bit fields.
0x40342988
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG10 for the details of bit fields.
0x4034298C
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG11 for the details of bit fields.
0x40342A00 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
0x40342A04 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
0x40342A08 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
0x40342A0C PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
0x40342A10 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
0x40342A14 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
0x40342A18 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
0x40342A1C PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
0x40342A20 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
0x40342A24 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
0x40342A28 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
0x40342A2C PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
829
Universal Digital Block (UDB) Registers
Register UDB_UDBPAIR5_UDBSNG0_PLD_ORT0
Address
Description
0x40342A30 PLD OR Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_ORT0 for the details of bit fields.
UDB_UDBPAIR5_UDBSNG0_PLD_ORT1
0x40342A34 PLD OR Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_ORT1 for the details of bit fields.
UDB_UDBPAIR5_UDBSNG0_PLD_CFG0 UDB_UDBPAIR5_UDBSNG0_PLD_CFG1 UDB_UDBPAIR5_UDBSNG0_DPATH_CFG0 UDB_UDBPAIR5_UDBSNG0_DPATH_CFG1 UDB_UDBPAIR5_UDBSNG0_DPATH_CFG2 UDB_UDBPAIR5_UDBSNG0_DPATH_CFG3 UDB_UDBPAIR5_UDBSNG0_DPATH_CFG4 UDB_UDBPAIR5_UDBSNG0_SC_CFG0
0x40342A38
PLD configuration for Carry Enable, Constant, and XOR feedback. See UDB_UDBPAIR0_UDBSNG0_PLD_CFG0 for the details of bit fields.
0x40342A3C
PLD configuration for Set / Reset selection, and Bypass control. See UDB_UDBPAIR0_UDBSNG0_PLD_CFG1 for the details of bit fields.
0x40342A40
Datapath input selections (RAD0, RAD1, RAD2, F0_LD, F1_LD, D0_LD, D1_LD). See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG0 for the details of bit fields.
0x40342A44
Datapath input and output selections (SCI_MUX, SI_MUX, OUT0 thru OUT5). See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG1 for the details of bit fields.
0x40342A48 0x40342A4C 0x40342A50
Datapath output synchronization, ALU mask, compare 0 and 1 masks. See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG2 for the details of bit fields.
Datapath mask enables, shift in, carry in, compare, chaining, MSB configs; FIFO, shift and parallel input control. See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG3 for the details of bit fields.
Datapath FIFO and register access configuration control. See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG4 for the details of bit fields.
0x40342A54
SC Mode 0 and 1 control registers; status register input mode; general SC configuration. See UDB_UDBPAIR0_UDBSNG0_SC_CFG0 for the details of bit fields.
UDB_UDBPAIR5_UDBSNG0_SC_CFG1
0x40342A58 SC counter control. See UDB_UDBPAIR0_UDBSNG0_SC_CFG1 for the details of bit fields.
UDB_UDBPAIR5_UDBSNG0_RC_CFG0 UDB_UDBPAIR5_UDBSNG0_RC_CFG1 UDB_UDBPAIR5_UDBSNG0_DPATH_OPC0 UDB_UDBPAIR5_UDBSNG0_DPATH_OPC1 UDB_UDBPAIR5_UDBSNG0_DPATH_OPC2 UDB_UDBPAIR5_UDBSNG0_DPATH_OPC3
0x40342A5C
PLD0, PLD1, Datatpath, and SC clock and reset control. See UDB_UDBPAIR0_UDBSNG0_RC_CFG0 for the details of bit fields.
0x40342A60
PLD0, PLD1, Datatpath, and SC clock selection, general reset control. See UDB_UDBPAIR0_UDBSNG0_RC_CFG1 for the details of bit fields.
0x40342A64
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
0x40342A68
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
0x40342A6C
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
0x40342A70
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
UDB_UDBPAIR5_UDBSNG1_PLD_IT0
0x40342A80 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR5_UDBSNG1_PLD_IT1
0x40342A84 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR5_UDBSNG1_PLD_IT2
0x40342A88 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR5_UDBSNG1_PLD_IT3
0x40342A8C PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR5_UDBSNG1_PLD_IT4
0x40342A90 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR5_UDBSNG1_PLD_IT5
0x40342A94 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR5_UDBSNG1_PLD_IT6
0x40342A98 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR5_UDBSNG1_PLD_IT7
0x40342A9C PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR5_UDBSNG1_PLD_IT8
0x40342AA0 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR5_UDBSNG1_PLD_IT9
0x40342AA4 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR5_UDBSNG1_PLD_IT10
0x40342AA8 PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
UDB_UDBPAIR5_UDBSNG1_PLD_IT11
0x40342AAC PLD Input Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_IT0 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
830
Universal Digital Block (UDB) Registers
Register UDB_UDBPAIR5_UDBSNG1_PLD_ORT0
Address
Description
0x40342AB0 PLD OR Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_ORT0 for the details of bit fields.
UDB_UDBPAIR5_UDBSNG1_PLD_ORT1
0x40342AB4 PLD OR Terms. See UDB_UDBPAIR0_UDBSNG0_PLD_ORT1 for the details of bit fields.
UDB_UDBPAIR5_UDBSNG1_PLD_CFG0 UDB_UDBPAIR5_UDBSNG1_PLD_CFG1 UDB_UDBPAIR5_UDBSNG1_DPATH_CFG0 UDB_UDBPAIR5_UDBSNG1_DPATH_CFG1 UDB_UDBPAIR5_UDBSNG1_DPATH_CFG2 UDB_UDBPAIR5_UDBSNG1_DPATH_CFG3 UDB_UDBPAIR5_UDBSNG1_DPATH_CFG4 UDB_UDBPAIR5_UDBSNG1_SC_CFG0
0x40342AB8
PLD configuration for Carry Enable, Constant, and XOR feedback. See UDB_UDBPAIR0_UDBSNG0_PLD_CFG0 for the details of bit fields.
0x40342ABC
PLD configuration for Set / Reset selection, and Bypass control. See UDB_UDBPAIR0_UDBSNG0_PLD_CFG1 for the details of bit fields.
0x40342AC0
Datapath input selections (RAD0, RAD1, RAD2, F0_LD, F1_LD, D0_LD, D1_LD). See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG0 for the details of bit fields.
0x40342AC4
Datapath input and output selections (SCI_MUX, SI_MUX, OUT0 thru OUT5). See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG1 for the details of bit fields.
0x40342AC8 0x40342ACC 0x40342AD0
Datapath output synchronization, ALU mask, compare 0 and 1 masks. See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG2 for the details of bit fields.
Datapath mask enables, shift in, carry in, compare, chaining, MSB configs; FIFO, shift and parallel input control. See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG3 for the details of bit fields.
Datapath FIFO and register access configuration control. See UDB_UDBPAIR0_UDBSNG0_DPATH_CFG4 for the details of bit fields.
0x40342AD4
SC Mode 0 and 1 control registers; status register input mode; general SC configuration. See UDB_UDBPAIR0_UDBSNG0_SC_CFG0 for the details of bit fields.
UDB_UDBPAIR5_UDBSNG1_SC_CFG1
0x40342AD8 SC counter control. See UDB_UDBPAIR0_UDBSNG0_SC_CFG1 for the details of bit fields.
UDB_UDBPAIR5_UDBSNG1_RC_CFG0 UDB_UDBPAIR5_UDBSNG1_RC_CFG1 UDB_UDBPAIR5_UDBSNG1_DPATH_OPC0 UDB_UDBPAIR5_UDBSNG1_DPATH_OPC1 UDB_UDBPAIR5_UDBSNG1_DPATH_OPC2 UDB_UDBPAIR5_UDBSNG1_DPATH_OPC3 UDB_UDBPAIR5_ROUTE_TOP_V_BOT UDB_UDBPAIR5_ROUTE_LVO1_V_2 UDB_UDBPAIR5_ROUTE_RVO1_V_2 UDB_UDBPAIR5_ROUTE_TUI_CFG0 UDB_UDBPAIR5_ROUTE_TUI_CFG1 UDB_UDBPAIR5_ROUTE_TUI_CFG2 UDB_UDBPAIR5_ROUTE_TUI_CFG3 UDB_UDBPAIR5_ROUTE_TUI_CFG4 UDB_UDBPAIR5_ROUTE_TUI_CFG5 UDB_UDBPAIR5_ROUTE_BUI_CFG0 UDB_UDBPAIR5_ROUTE_BUI_CFG1 UDB_UDBPAIR5_ROUTE_BUI_CFG2
0x40342ADC
PLD0, PLD1, Datatpath, and SC clock and reset control. See UDB_UDBPAIR0_UDBSNG0_RC_CFG0 for the details of bit fields.
0x40342AE0
PLD0, PLD1, Datatpath, and SC clock selection, general reset control. See UDB_UDBPAIR0_UDBSNG0_RC_CFG1 for the details of bit fields.
0x40342AE4
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
0x40342AE8
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
0x40342AEC
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
0x40342AF0
Datapath opcode configuration. See UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 for the details of bit fields.
0x40342B00
Top Vertical Input (TVI) vs Bottom Vertical Input (BVI) muxing. See UDB_UDBPAIR0_ROUTE_TOP_V_BOT for the details of bit fields.
0x40342B04
Left Vertical Ouput (LVO) 1 vs 2 muxing for certain horizontals. See UDB_UDBPAIR0_ROUTE_LVO1_V_2 for the details of bit fields.
0x40342B08
Right Vertical Ouput (RVO) 1 vs 2 muxing for certain horizontals. See UDB_UDBPAIR0_ROUTE_RVO1_V_2 for the details of bit fields.
0x40342B0C
Top UDB Input (TUI) selection. See UDB_UDBPAIR0_ROUTE_TUI_CFG0 for the details of bit fields.
0x40342B10
Top UDB Input (TUI) selection. See UDB_UDBPAIR0_ROUTE_TUI_CFG1 for the details of bit fields.
0x40342B14
Top UDB Input (TUI) selection. See UDB_UDBPAIR0_ROUTE_TUI_CFG2 for the details of bit fields.
0x40342B18
Top UDB Input (TUI) selection. See UDB_UDBPAIR0_ROUTE_TUI_CFG3 for the details of bit fields.
0x40342B1C
Top UDB Input (TUI) selection. See UDB_UDBPAIR0_ROUTE_TUI_CFG4 for the details of bit fields.
0x40342B20
Top UDB Input (TUI) selection. See UDB_UDBPAIR0_ROUTE_TUI_CFG5 for the details of bit fields.
0x40342B24
Bottom UDB Input (BUI) selection. See UDB_UDBPAIR0_ROUTE_BUI_CFG0 for the details of bit fields.
0x40342B28
Bottom UDB Input (BUI) selection. See UDB_UDBPAIR0_ROUTE_BUI_CFG1 for the details of bit fields.
0x40342B2C
Bottom UDB Input (BUI) selection. See UDB_UDBPAIR0_ROUTE_BUI_CFG2 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
831
Universal Digital Block (UDB) Registers
Register UDB_UDBPAIR5_ROUTE_BUI_CFG3 UDB_UDBPAIR5_ROUTE_BUI_CFG4 UDB_UDBPAIR5_ROUTE_BUI_CFG5 UDB_UDBPAIR5_ROUTE_RVO_CFG0 UDB_UDBPAIR5_ROUTE_RVO_CFG1 UDB_UDBPAIR5_ROUTE_RVO_CFG2 UDB_UDBPAIR5_ROUTE_RVO_CFG3 UDB_UDBPAIR5_ROUTE_LVO_CFG0 UDB_UDBPAIR5_ROUTE_LVO_CFG1 UDB_UDBPAIR5_ROUTE_RHO_CFG0 UDB_UDBPAIR5_ROUTE_RHO_CFG1 UDB_UDBPAIR5_ROUTE_RHO_CFG2 UDB_UDBPAIR5_ROUTE_LHO_CFG0 UDB_UDBPAIR5_ROUTE_LHO_CFG1 UDB_UDBPAIR5_ROUTE_LHO_CFG2 UDB_UDBPAIR5_ROUTE_LHO_CFG3 UDB_UDBPAIR5_ROUTE_LHO_CFG4 UDB_UDBPAIR5_ROUTE_LHO_CFG5 UDB_UDBPAIR5_ROUTE_LHO_CFG6 UDB_UDBPAIR5_ROUTE_LHO_CFG7 UDB_UDBPAIR5_ROUTE_LHO_CFG8 UDB_UDBPAIR5_ROUTE_LHO_CFG9 UDB_UDBPAIR5_ROUTE_LHO_CFG10 UDB_UDBPAIR5_ROUTE_LHO_CFG11 UDB_DSI0_LVO1_V_2 UDB_DSI0_RVO1_V_2 UDB_DSI0_DOP_CFG0 UDB_DSI0_DOP_CFG1 UDB_DSI0_DOP_CFG2
Address
Description
0x40342B30
Bottom UDB Input (BUI) selection. See UDB_UDBPAIR0_ROUTE_BUI_CFG3 for the details of bit fields.
0x40342B34
Bottom UDB Input (BUI) selection. See UDB_UDBPAIR0_ROUTE_BUI_CFG4 for the details of bit fields.
0x40342B38
Bottom UDB Input (BUI) selection. See UDB_UDBPAIR0_ROUTE_BUI_CFG5 for the details of bit fields.
0x40342B3C
Right Vertical Ouput (RVO) selection. See UDB_UDBPAIR0_ROUTE_RVO_CFG0 for the details of bit fields.
0x40342B40
Right Vertical Ouput (RVO) selection. See UDB_UDBPAIR0_ROUTE_RVO_CFG1 for the details of bit fields.
0x40342B44
Right Vertical Ouput (RVO) selection. See UDB_UDBPAIR0_ROUTE_RVO_CFG2 for the details of bit fields.
0x40342B48
Right Vertical Ouput (RVO) selection. See UDB_UDBPAIR0_ROUTE_RVO_CFG3 for the details of bit fields.
0x40342B4C
Left Vertical Ouput (LVO) selection. See UDB_UDBPAIR0_ROUTE_LVO_CFG0 for the details of bit fields.
0x40342B50
Left Vertical Ouput (LVO) selection. See UDB_UDBPAIR0_ROUTE_LVO_CFG1 for the details of bit fields.
0x40342B54
Right Horizontal Out (RHO) selection. See UDB_UDBPAIR0_ROUTE_RHO_CFG0 for the details of bit fields.
0x40342B58
Right Horizontal Out (RHO) selection. See UDB_UDBPAIR0_ROUTE_RHO_CFG1 for the details of bit fields.
0x40342B5C
Right Horizontal Out (RHO) selection. See UDB_UDBPAIR0_ROUTE_RHO_CFG2 for the details of bit fields.
0x40342B60
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG0 for the details of bit fields.
0x40342B64
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG1 for the details of bit fields.
0x40342B68
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG2 for the details of bit fields.
0x40342B6C
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG3 for the details of bit fields.
0x40342B70
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG4 for the details of bit fields.
0x40342B74
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG5 for the details of bit fields.
0x40342B78
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG6 for the details of bit fields.
0x40342B7C
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG7 for the details of bit fields.
0x40342B80
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG8 for the details of bit fields.
0x40342B84
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG9 for the details of bit fields.
0x40342B88
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG10 for the details of bit fields.
0x40342B8C
Left Horizontal Out (LHO) selection. See UDB_UDBPAIR0_ROUTE_LHO_CFG11 for the details of bit fields.
0x40346000 Left Vertical Ouput (LVO) 1 vs 2 muxing for certain horizontals
0x40346004 Right Vertical Ouput (RVO) 1 vs 2 muxing for certain horizontals
0x40346008 DSI Out Pair (DOP) selection
0x4034600C DSI Out Pair (DOP) selection
0x40346010 DSI Out Pair (DOP) selection
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
832
Register UDB_DSI0_DOP_CFG3 UDB_DSI0_DOT_CFG0 UDB_DSI0_DOT_CFG1 UDB_DSI0_DOT_CFG2 UDB_DSI0_DOT_CFG3 UDB_DSI0_RVO_CFG0 UDB_DSI0_RVO_CFG1 UDB_DSI0_RVO_CFG2 UDB_DSI0_RVO_CFG3 UDB_DSI0_LVO_CFG0 UDB_DSI0_LVO_CFG1 UDB_DSI0_RHO_CFG0 UDB_DSI0_RHO_CFG1 UDB_DSI0_RHO_CFG2 UDB_DSI0_LHO_CFG0 UDB_DSI0_LHO_CFG1 UDB_DSI0_LHO_CFG2 UDB_DSI0_LHO_CFG3 UDB_DSI0_LHO_CFG4 UDB_DSI0_LHO_CFG5 UDB_DSI0_LHO_CFG6 UDB_DSI0_LHO_CFG7 UDB_DSI0_LHO_CFG8 UDB_DSI0_LHO_CFG9 UDB_DSI0_LHO_CFG10 UDB_DSI0_LHO_CFG11 UDB_DSI1_LVO1_V_2 UDB_DSI1_RVO1_V_2 UDB_DSI1_DOP_CFG0
Universal Digital Block (UDB) Registers
Address 0x40346014 DSI Out Pair (DOP) selection
Description
0x40346018 DSI Out Triplet (DOT) selection
0x4034601C DSI Out Triplet (DOT) selection
0x40346020 DSI Out Triplet (DOT) selection
0x40346024 DSI Out Triplet (DOT) selection
0x40346028 Right Vertical Ouput (RVO) selection
0x4034602C Right Vertical Ouput (RVO) selection
0x40346030 Right Vertical Ouput (RVO) selection
0x40346034 Right Vertical Ouput (RVO) selection
0x40346038 Left Vertical Ouput (LVO) selection
0x4034603C Left Vertical Ouput (LVO) selection
0x40346040 Right Horizontal Out (RHO) selection
0x40346044 Right Horizontal Out (RHO) selection
0x40346048 Right Horizontal Out (RHO) selection
0x4034604C Left Horizontal Out (LHO) selection
0x40346050 Left Horizontal Out (LHO) selection
0x40346054 Left Horizontal Out (LHO) selection
0x40346058 Left Horizontal Out (LHO) selection
0x4034605C Left Horizontal Out (LHO) selection
0x40346060 Left Horizontal Out (LHO) selection
0x40346064 Left Horizontal Out (LHO) selection
0x40346068 Left Horizontal Out (LHO) selection
0x4034606C Left Horizontal Out (LHO) selection
0x40346070 Left Horizontal Out (LHO) selection
0x40346074 Left Horizontal Out (LHO) selection
0x40346078 Left Horizontal Out (LHO) selection
0x40346080 0x40346084
Left Vertical Ouput (LVO) 1 vs 2 muxing for certain horizontals. See UDB_DSI0_LVO1_V_2 for the details of bit fields.
Right Vertical Ouput (RVO) 1 vs 2 muxing for certain horizontals. See UDB_DSI0_RVO1_V_2 for the details of bit fields.
0x40346088 DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG0 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
833
Universal Digital Block (UDB) Registers
Register UDB_DSI1_DOP_CFG1 UDB_DSI1_DOP_CFG2 UDB_DSI1_DOP_CFG3 UDB_DSI1_DOT_CFG0 UDB_DSI1_DOT_CFG1 UDB_DSI1_DOT_CFG2 UDB_DSI1_DOT_CFG3 UDB_DSI1_RVO_CFG0 UDB_DSI1_RVO_CFG1 UDB_DSI1_RVO_CFG2 UDB_DSI1_RVO_CFG3 UDB_DSI1_LVO_CFG0 UDB_DSI1_LVO_CFG1 UDB_DSI1_RHO_CFG0 UDB_DSI1_RHO_CFG1 UDB_DSI1_RHO_CFG2 UDB_DSI1_LHO_CFG0 UDB_DSI1_LHO_CFG1 UDB_DSI1_LHO_CFG2 UDB_DSI1_LHO_CFG3 UDB_DSI1_LHO_CFG4 UDB_DSI1_LHO_CFG5 UDB_DSI1_LHO_CFG6 UDB_DSI1_LHO_CFG7 UDB_DSI1_LHO_CFG8 UDB_DSI1_LHO_CFG9 UDB_DSI1_LHO_CFG10 UDB_DSI1_LHO_CFG11 UDB_DSI2_LVO1_V_2
Address
Description
0x4034608C DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG1 for the details of bit fields.
0x40346090 DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG2 for the details of bit fields.
0x40346094 DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG3 for the details of bit fields.
0x40346098 DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG0 for the details of bit fields.
0x4034609C DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG1 for the details of bit fields.
0x403460A0 DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG2 for the details of bit fields.
0x403460A4 DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG3 for the details of bit fields.
0x403460A8 Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG0 for the details of bit fields.
0x403460AC Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG1 for the details of bit fields.
0x403460B0 Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG2 for the details of bit fields.
0x403460B4 Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG3 for the details of bit fields.
0x403460B8 Left Vertical Ouput (LVO) selection. See UDB_DSI0_LVO_CFG0 for the details of bit fields.
0x403460BC Left Vertical Ouput (LVO) selection. See UDB_DSI0_LVO_CFG1 for the details of bit fields.
0x403460C0 Right Horizontal Out (RHO) selection. See UDB_DSI0_RHO_CFG0 for the details of bit fields.
0x403460C4 Right Horizontal Out (RHO) selection. See UDB_DSI0_RHO_CFG1 for the details of bit fields.
0x403460C8 Right Horizontal Out (RHO) selection. See UDB_DSI0_RHO_CFG2 for the details of bit fields.
0x403460CC Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG0 for the details of bit fields.
0x403460D0 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG1 for the details of bit fields.
0x403460D4 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG2 for the details of bit fields.
0x403460D8 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG3 for the details of bit fields.
0x403460DC Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG4 for the details of bit fields.
0x403460E0 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG5 for the details of bit fields.
0x403460E4 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG6 for the details of bit fields.
0x403460E8 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG7 for the details of bit fields.
0x403460EC Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG8 for the details of bit fields.
0x403460F0 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG9 for the details of bit fields.
0x403460F4 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG10 for the details of bit fields.
0x403460F8 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG11 for the details of bit fields.
0x40346100
Left Vertical Ouput (LVO) 1 vs 2 muxing for certain horizontals. See UDB_DSI0_LVO1_V_2 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
834
Register UDB_DSI2_RVO1_V_2 UDB_DSI2_DOP_CFG0 UDB_DSI2_DOP_CFG1 UDB_DSI2_DOP_CFG2 UDB_DSI2_DOP_CFG3 UDB_DSI2_DOT_CFG0 UDB_DSI2_DOT_CFG1 UDB_DSI2_DOT_CFG2 UDB_DSI2_DOT_CFG3 UDB_DSI2_RVO_CFG0 UDB_DSI2_RVO_CFG1 UDB_DSI2_RVO_CFG2 UDB_DSI2_RVO_CFG3 UDB_DSI2_LVO_CFG0 UDB_DSI2_LVO_CFG1 UDB_DSI2_RHO_CFG0 UDB_DSI2_RHO_CFG1 UDB_DSI2_RHO_CFG2 UDB_DSI2_LHO_CFG0 UDB_DSI2_LHO_CFG1 UDB_DSI2_LHO_CFG2 UDB_DSI2_LHO_CFG3 UDB_DSI2_LHO_CFG4 UDB_DSI2_LHO_CFG5 UDB_DSI2_LHO_CFG6 UDB_DSI2_LHO_CFG7 UDB_DSI2_LHO_CFG8 UDB_DSI2_LHO_CFG9 UDB_DSI2_LHO_CFG10
Universal Digital Block (UDB) Registers
Address 0x40346104
Description
Right Vertical Ouput (RVO) 1 vs 2 muxing for certain horizontals. See UDB_DSI0_RVO1_V_2 for the details of bit fields.
0x40346108 DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG0 for the details of bit fields.
0x4034610C DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG1 for the details of bit fields.
0x40346110 DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG2 for the details of bit fields.
0x40346114 DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG3 for the details of bit fields.
0x40346118 DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG0 for the details of bit fields.
0x4034611C DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG1 for the details of bit fields.
0x40346120 DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG2 for the details of bit fields.
0x40346124 DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG3 for the details of bit fields.
0x40346128 Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG0 for the details of bit fields.
0x4034612C Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG1 for the details of bit fields.
0x40346130 Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG2 for the details of bit fields.
0x40346134 Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG3 for the details of bit fields.
0x40346138 Left Vertical Ouput (LVO) selection. See UDB_DSI0_LVO_CFG0 for the details of bit fields.
0x4034613C Left Vertical Ouput (LVO) selection. See UDB_DSI0_LVO_CFG1 for the details of bit fields.
0x40346140 Right Horizontal Out (RHO) selection. See UDB_DSI0_RHO_CFG0 for the details of bit fields.
0x40346144 Right Horizontal Out (RHO) selection. See UDB_DSI0_RHO_CFG1 for the details of bit fields.
0x40346148 Right Horizontal Out (RHO) selection. See UDB_DSI0_RHO_CFG2 for the details of bit fields.
0x4034614C Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG0 for the details of bit fields.
0x40346150 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG1 for the details of bit fields.
0x40346154 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG2 for the details of bit fields.
0x40346158 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG3 for the details of bit fields.
0x4034615C Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG4 for the details of bit fields.
0x40346160 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG5 for the details of bit fields.
0x40346164 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG6 for the details of bit fields.
0x40346168 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG7 for the details of bit fields.
0x4034616C Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG8 for the details of bit fields.
0x40346170 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG9 for the details of bit fields.
0x40346174 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG10 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
835
Register UDB_DSI2_LHO_CFG11 UDB_DSI3_LVO1_V_2 UDB_DSI3_RVO1_V_2 UDB_DSI3_DOP_CFG0 UDB_DSI3_DOP_CFG1 UDB_DSI3_DOP_CFG2 UDB_DSI3_DOP_CFG3 UDB_DSI3_DOT_CFG0 UDB_DSI3_DOT_CFG1 UDB_DSI3_DOT_CFG2 UDB_DSI3_DOT_CFG3 UDB_DSI3_RVO_CFG0 UDB_DSI3_RVO_CFG1 UDB_DSI3_RVO_CFG2 UDB_DSI3_RVO_CFG3 UDB_DSI3_LVO_CFG0 UDB_DSI3_LVO_CFG1 UDB_DSI3_RHO_CFG0 UDB_DSI3_RHO_CFG1 UDB_DSI3_RHO_CFG2 UDB_DSI3_LHO_CFG0 UDB_DSI3_LHO_CFG1 UDB_DSI3_LHO_CFG2 UDB_DSI3_LHO_CFG3 UDB_DSI3_LHO_CFG4 UDB_DSI3_LHO_CFG5 UDB_DSI3_LHO_CFG6 UDB_DSI3_LHO_CFG7 UDB_DSI3_LHO_CFG8
Universal Digital Block (UDB) Registers
Address
Description
0x40346178 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG11 for the details of bit fields.
0x40346180 0x40346184
Left Vertical Ouput (LVO) 1 vs 2 muxing for certain horizontals. See UDB_DSI0_LVO1_V_2 for the details of bit fields.
Right Vertical Ouput (RVO) 1 vs 2 muxing for certain horizontals. See UDB_DSI0_RVO1_V_2 for the details of bit fields.
0x40346188 DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG0 for the details of bit fields.
0x4034618C DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG1 for the details of bit fields.
0x40346190 DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG2 for the details of bit fields.
0x40346194 DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG3 for the details of bit fields.
0x40346198 DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG0 for the details of bit fields.
0x4034619C DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG1 for the details of bit fields.
0x403461A0 DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG2 for the details of bit fields.
0x403461A4 DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG3 for the details of bit fields.
0x403461A8 Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG0 for the details of bit fields.
0x403461AC Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG1 for the details of bit fields.
0x403461B0 Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG2 for the details of bit fields.
0x403461B4 Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG3 for the details of bit fields.
0x403461B8 Left Vertical Ouput (LVO) selection. See UDB_DSI0_LVO_CFG0 for the details of bit fields.
0x403461BC Left Vertical Ouput (LVO) selection. See UDB_DSI0_LVO_CFG1 for the details of bit fields.
0x403461C0 Right Horizontal Out (RHO) selection. See UDB_DSI0_RHO_CFG0 for the details of bit fields.
0x403461C4 Right Horizontal Out (RHO) selection. See UDB_DSI0_RHO_CFG1 for the details of bit fields.
0x403461C8 Right Horizontal Out (RHO) selection. See UDB_DSI0_RHO_CFG2 for the details of bit fields.
0x403461CC Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG0 for the details of bit fields.
0x403461D0 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG1 for the details of bit fields.
0x403461D4 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG2 for the details of bit fields.
0x403461D8 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG3 for the details of bit fields.
0x403461DC Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG4 for the details of bit fields.
0x403461E0 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG5 for the details of bit fields.
0x403461E4 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG6 for the details of bit fields.
0x403461E8 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG7 for the details of bit fields.
0x403461EC Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG8 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
836
Register UDB_DSI3_LHO_CFG9 UDB_DSI3_LHO_CFG10 UDB_DSI3_LHO_CFG11 UDB_DSI4_LVO1_V_2 UDB_DSI4_RVO1_V_2 UDB_DSI4_DOP_CFG0 UDB_DSI4_DOP_CFG1 UDB_DSI4_DOP_CFG2 UDB_DSI4_DOP_CFG3 UDB_DSI4_DOT_CFG0 UDB_DSI4_DOT_CFG1 UDB_DSI4_DOT_CFG2 UDB_DSI4_DOT_CFG3 UDB_DSI4_RVO_CFG0 UDB_DSI4_RVO_CFG1 UDB_DSI4_RVO_CFG2 UDB_DSI4_RVO_CFG3 UDB_DSI4_LVO_CFG0 UDB_DSI4_LVO_CFG1 UDB_DSI4_RHO_CFG0 UDB_DSI4_RHO_CFG1 UDB_DSI4_RHO_CFG2 UDB_DSI4_LHO_CFG0 UDB_DSI4_LHO_CFG1 UDB_DSI4_LHO_CFG2 UDB_DSI4_LHO_CFG3 UDB_DSI4_LHO_CFG4 UDB_DSI4_LHO_CFG5 UDB_DSI4_LHO_CFG6
Universal Digital Block (UDB) Registers
Address
Description
0x403461F0 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG9 for the details of bit fields.
0x403461F4 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG10 for the details of bit fields.
0x403461F8 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG11 for the details of bit fields.
0x40346200 0x40346204
Left Vertical Ouput (LVO) 1 vs 2 muxing for certain horizontals. See UDB_DSI0_LVO1_V_2 for the details of bit fields.
Right Vertical Ouput (RVO) 1 vs 2 muxing for certain horizontals. See UDB_DSI0_RVO1_V_2 for the details of bit fields.
0x40346208 DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG0 for the details of bit fields.
0x4034620C DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG1 for the details of bit fields.
0x40346210 DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG2 for the details of bit fields.
0x40346214 DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG3 for the details of bit fields.
0x40346218 DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG0 for the details of bit fields.
0x4034621C DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG1 for the details of bit fields.
0x40346220 DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG2 for the details of bit fields.
0x40346224 DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG3 for the details of bit fields.
0x40346228 Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG0 for the details of bit fields.
0x4034622C Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG1 for the details of bit fields.
0x40346230 Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG2 for the details of bit fields.
0x40346234 Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG3 for the details of bit fields.
0x40346238 Left Vertical Ouput (LVO) selection. See UDB_DSI0_LVO_CFG0 for the details of bit fields.
0x4034623C Left Vertical Ouput (LVO) selection. See UDB_DSI0_LVO_CFG1 for the details of bit fields.
0x40346240 Right Horizontal Out (RHO) selection. See UDB_DSI0_RHO_CFG0 for the details of bit fields.
0x40346244 Right Horizontal Out (RHO) selection. See UDB_DSI0_RHO_CFG1 for the details of bit fields.
0x40346248 Right Horizontal Out (RHO) selection. See UDB_DSI0_RHO_CFG2 for the details of bit fields.
0x4034624C Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG0 for the details of bit fields.
0x40346250 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG1 for the details of bit fields.
0x40346254 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG2 for the details of bit fields.
0x40346258 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG3 for the details of bit fields.
0x4034625C Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG4 for the details of bit fields.
0x40346260 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG5 for the details of bit fields.
0x40346264 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG6 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
837
Register UDB_DSI4_LHO_CFG7 UDB_DSI4_LHO_CFG8 UDB_DSI4_LHO_CFG9 UDB_DSI4_LHO_CFG10 UDB_DSI4_LHO_CFG11 UDB_DSI5_LVO1_V_2 UDB_DSI5_RVO1_V_2 UDB_DSI5_DOP_CFG0 UDB_DSI5_DOP_CFG1 UDB_DSI5_DOP_CFG2 UDB_DSI5_DOP_CFG3 UDB_DSI5_DOT_CFG0 UDB_DSI5_DOT_CFG1 UDB_DSI5_DOT_CFG2 UDB_DSI5_DOT_CFG3 UDB_DSI5_RVO_CFG0 UDB_DSI5_RVO_CFG1 UDB_DSI5_RVO_CFG2 UDB_DSI5_RVO_CFG3 UDB_DSI5_LVO_CFG0 UDB_DSI5_LVO_CFG1 UDB_DSI5_RHO_CFG0 UDB_DSI5_RHO_CFG1 UDB_DSI5_RHO_CFG2 UDB_DSI5_LHO_CFG0 UDB_DSI5_LHO_CFG1 UDB_DSI5_LHO_CFG2 UDB_DSI5_LHO_CFG3 UDB_DSI5_LHO_CFG4
Universal Digital Block (UDB) Registers
Address
Description
0x40346268 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG7 for the details of bit fields.
0x4034626C Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG8 for the details of bit fields.
0x40346270 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG9 for the details of bit fields.
0x40346274 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG10 for the details of bit fields.
0x40346278 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG11 for the details of bit fields.
0x40346280 0x40346284
Left Vertical Ouput (LVO) 1 vs 2 muxing for certain horizontals. See UDB_DSI0_LVO1_V_2 for the details of bit fields.
Right Vertical Ouput (RVO) 1 vs 2 muxing for certain horizontals. See UDB_DSI0_RVO1_V_2 for the details of bit fields.
0x40346288 DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG0 for the details of bit fields.
0x4034628C DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG1 for the details of bit fields.
0x40346290 DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG2 for the details of bit fields.
0x40346294 DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG3 for the details of bit fields.
0x40346298 DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG0 for the details of bit fields.
0x4034629C DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG1 for the details of bit fields.
0x403462A0 DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG2 for the details of bit fields.
0x403462A4 DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG3 for the details of bit fields.
0x403462A8 Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG0 for the details of bit fields.
0x403462AC Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG1 for the details of bit fields.
0x403462B0 Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG2 for the details of bit fields.
0x403462B4 Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG3 for the details of bit fields.
0x403462B8 Left Vertical Ouput (LVO) selection. See UDB_DSI0_LVO_CFG0 for the details of bit fields.
0x403462BC Left Vertical Ouput (LVO) selection. See UDB_DSI0_LVO_CFG1 for the details of bit fields.
0x403462C0 Right Horizontal Out (RHO) selection. See UDB_DSI0_RHO_CFG0 for the details of bit fields.
0x403462C4 Right Horizontal Out (RHO) selection. See UDB_DSI0_RHO_CFG1 for the details of bit fields.
0x403462C8 Right Horizontal Out (RHO) selection. See UDB_DSI0_RHO_CFG2 for the details of bit fields.
0x403462CC Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG0 for the details of bit fields.
0x403462D0 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG1 for the details of bit fields.
0x403462D4 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG2 for the details of bit fields.
0x403462D8 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG3 for the details of bit fields.
0x403462DC Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG4 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
838
Register UDB_DSI5_LHO_CFG5 UDB_DSI5_LHO_CFG6 UDB_DSI5_LHO_CFG7 UDB_DSI5_LHO_CFG8 UDB_DSI5_LHO_CFG9 UDB_DSI5_LHO_CFG10 UDB_DSI5_LHO_CFG11 UDB_DSI6_LVO1_V_2 UDB_DSI6_RVO1_V_2 UDB_DSI6_DOP_CFG0 UDB_DSI6_DOP_CFG1 UDB_DSI6_DOP_CFG2 UDB_DSI6_DOP_CFG3 UDB_DSI6_DOT_CFG0 UDB_DSI6_DOT_CFG1 UDB_DSI6_DOT_CFG2 UDB_DSI6_DOT_CFG3 UDB_DSI6_RVO_CFG0 UDB_DSI6_RVO_CFG1 UDB_DSI6_RVO_CFG2 UDB_DSI6_RVO_CFG3 UDB_DSI6_LVO_CFG0 UDB_DSI6_LVO_CFG1 UDB_DSI6_RHO_CFG0 UDB_DSI6_RHO_CFG1 UDB_DSI6_RHO_CFG2 UDB_DSI6_LHO_CFG0 UDB_DSI6_LHO_CFG1 UDB_DSI6_LHO_CFG2
Universal Digital Block (UDB) Registers
Address
Description
0x403462E0 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG5 for the details of bit fields.
0x403462E4 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG6 for the details of bit fields.
0x403462E8 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG7 for the details of bit fields.
0x403462EC Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG8 for the details of bit fields.
0x403462F0 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG9 for the details of bit fields.
0x403462F4 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG10 for the details of bit fields.
0x403462F8 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG11 for the details of bit fields.
0x40346300 0x40346304
Left Vertical Ouput (LVO) 1 vs 2 muxing for certain horizontals. See UDB_DSI0_LVO1_V_2 for the details of bit fields.
Right Vertical Ouput (RVO) 1 vs 2 muxing for certain horizontals. See UDB_DSI0_RVO1_V_2 for the details of bit fields.
0x40346308 DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG0 for the details of bit fields.
0x4034630C DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG1 for the details of bit fields.
0x40346310 DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG2 for the details of bit fields.
0x40346314 DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG3 for the details of bit fields.
0x40346318 DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG0 for the details of bit fields.
0x4034631C DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG1 for the details of bit fields.
0x40346320 DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG2 for the details of bit fields.
0x40346324 DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG3 for the details of bit fields.
0x40346328 Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG0 for the details of bit fields.
0x4034632C Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG1 for the details of bit fields.
0x40346330 Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG2 for the details of bit fields.
0x40346334 Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG3 for the details of bit fields.
0x40346338 Left Vertical Ouput (LVO) selection. See UDB_DSI0_LVO_CFG0 for the details of bit fields.
0x4034633C Left Vertical Ouput (LVO) selection. See UDB_DSI0_LVO_CFG1 for the details of bit fields.
0x40346340 Right Horizontal Out (RHO) selection. See UDB_DSI0_RHO_CFG0 for the details of bit fields.
0x40346344 Right Horizontal Out (RHO) selection. See UDB_DSI0_RHO_CFG1 for the details of bit fields.
0x40346348 Right Horizontal Out (RHO) selection. See UDB_DSI0_RHO_CFG2 for the details of bit fields.
0x4034634C Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG0 for the details of bit fields.
0x40346350 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG1 for the details of bit fields.
0x40346354 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG2 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
839
Register UDB_DSI6_LHO_CFG3 UDB_DSI6_LHO_CFG4 UDB_DSI6_LHO_CFG5 UDB_DSI6_LHO_CFG6 UDB_DSI6_LHO_CFG7 UDB_DSI6_LHO_CFG8 UDB_DSI6_LHO_CFG9 UDB_DSI6_LHO_CFG10 UDB_DSI6_LHO_CFG11 UDB_DSI7_LVO1_V_2 UDB_DSI7_RVO1_V_2 UDB_DSI7_DOP_CFG0 UDB_DSI7_DOP_CFG1 UDB_DSI7_DOP_CFG2 UDB_DSI7_DOP_CFG3 UDB_DSI7_DOT_CFG0 UDB_DSI7_DOT_CFG1 UDB_DSI7_DOT_CFG2 UDB_DSI7_DOT_CFG3 UDB_DSI7_RVO_CFG0 UDB_DSI7_RVO_CFG1 UDB_DSI7_RVO_CFG2 UDB_DSI7_RVO_CFG3 UDB_DSI7_LVO_CFG0 UDB_DSI7_LVO_CFG1 UDB_DSI7_RHO_CFG0 UDB_DSI7_RHO_CFG1 UDB_DSI7_RHO_CFG2 UDB_DSI7_LHO_CFG0
Universal Digital Block (UDB) Registers
Address
Description
0x40346358 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG3 for the details of bit fields.
0x4034635C Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG4 for the details of bit fields.
0x40346360 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG5 for the details of bit fields.
0x40346364 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG6 for the details of bit fields.
0x40346368 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG7 for the details of bit fields.
0x4034636C Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG8 for the details of bit fields.
0x40346370 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG9 for the details of bit fields.
0x40346374 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG10 for the details of bit fields.
0x40346378 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG11 for the details of bit fields.
0x40346380 0x40346384
Left Vertical Ouput (LVO) 1 vs 2 muxing for certain horizontals. See UDB_DSI0_LVO1_V_2 for the details of bit fields.
Right Vertical Ouput (RVO) 1 vs 2 muxing for certain horizontals. See UDB_DSI0_RVO1_V_2 for the details of bit fields.
0x40346388 DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG0 for the details of bit fields.
0x4034638C DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG1 for the details of bit fields.
0x40346390 DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG2 for the details of bit fields.
0x40346394 DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG3 for the details of bit fields.
0x40346398 DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG0 for the details of bit fields.
0x4034639C DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG1 for the details of bit fields.
0x403463A0 DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG2 for the details of bit fields.
0x403463A4 DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG3 for the details of bit fields.
0x403463A8 Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG0 for the details of bit fields.
0x403463AC Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG1 for the details of bit fields.
0x403463B0 Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG2 for the details of bit fields.
0x403463B4 Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG3 for the details of bit fields.
0x403463B8 Left Vertical Ouput (LVO) selection. See UDB_DSI0_LVO_CFG0 for the details of bit fields.
0x403463BC Left Vertical Ouput (LVO) selection. See UDB_DSI0_LVO_CFG1 for the details of bit fields.
0x403463C0 Right Horizontal Out (RHO) selection. See UDB_DSI0_RHO_CFG0 for the details of bit fields.
0x403463C4 Right Horizontal Out (RHO) selection. See UDB_DSI0_RHO_CFG1 for the details of bit fields.
0x403463C8 Right Horizontal Out (RHO) selection. See UDB_DSI0_RHO_CFG2 for the details of bit fields.
0x403463CC Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG0 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
840
Register UDB_DSI7_LHO_CFG1 UDB_DSI7_LHO_CFG2 UDB_DSI7_LHO_CFG3 UDB_DSI7_LHO_CFG4 UDB_DSI7_LHO_CFG5 UDB_DSI7_LHO_CFG6 UDB_DSI7_LHO_CFG7 UDB_DSI7_LHO_CFG8 UDB_DSI7_LHO_CFG9 UDB_DSI7_LHO_CFG10 UDB_DSI7_LHO_CFG11 UDB_DSI8_LVO1_V_2 UDB_DSI8_RVO1_V_2 UDB_DSI8_DOP_CFG0 UDB_DSI8_DOP_CFG1 UDB_DSI8_DOP_CFG2 UDB_DSI8_DOP_CFG3 UDB_DSI8_DOT_CFG0 UDB_DSI8_DOT_CFG1 UDB_DSI8_DOT_CFG2 UDB_DSI8_DOT_CFG3 UDB_DSI8_RVO_CFG0 UDB_DSI8_RVO_CFG1 UDB_DSI8_RVO_CFG2 UDB_DSI8_RVO_CFG3 UDB_DSI8_LVO_CFG0 UDB_DSI8_LVO_CFG1 UDB_DSI8_RHO_CFG0 UDB_DSI8_RHO_CFG1
Universal Digital Block (UDB) Registers
Address
Description
0x403463D0 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG1 for the details of bit fields.
0x403463D4 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG2 for the details of bit fields.
0x403463D8 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG3 for the details of bit fields.
0x403463DC Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG4 for the details of bit fields.
0x403463E0 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG5 for the details of bit fields.
0x403463E4 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG6 for the details of bit fields.
0x403463E8 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG7 for the details of bit fields.
0x403463EC Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG8 for the details of bit fields.
0x403463F0 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG9 for the details of bit fields.
0x403463F4 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG10 for the details of bit fields.
0x403463F8 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG11 for the details of bit fields.
0x40346400 0x40346404
Left Vertical Ouput (LVO) 1 vs 2 muxing for certain horizontals. See UDB_DSI0_LVO1_V_2 for the details of bit fields.
Right Vertical Ouput (RVO) 1 vs 2 muxing for certain horizontals. See UDB_DSI0_RVO1_V_2 for the details of bit fields.
0x40346408 DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG0 for the details of bit fields.
0x4034640C DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG1 for the details of bit fields.
0x40346410 DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG2 for the details of bit fields.
0x40346414 DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG3 for the details of bit fields.
0x40346418 DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG0 for the details of bit fields.
0x4034641C DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG1 for the details of bit fields.
0x40346420 DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG2 for the details of bit fields.
0x40346424 DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG3 for the details of bit fields.
0x40346428 Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG0 for the details of bit fields.
0x4034642C Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG1 for the details of bit fields.
0x40346430 Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG2 for the details of bit fields.
0x40346434 Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG3 for the details of bit fields.
0x40346438 Left Vertical Ouput (LVO) selection. See UDB_DSI0_LVO_CFG0 for the details of bit fields.
0x4034643C Left Vertical Ouput (LVO) selection. See UDB_DSI0_LVO_CFG1 for the details of bit fields.
0x40346440 Right Horizontal Out (RHO) selection. See UDB_DSI0_RHO_CFG0 for the details of bit fields.
0x40346444 Right Horizontal Out (RHO) selection. See UDB_DSI0_RHO_CFG1 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
841
Register UDB_DSI8_RHO_CFG2 UDB_DSI8_LHO_CFG0 UDB_DSI8_LHO_CFG1 UDB_DSI8_LHO_CFG2 UDB_DSI8_LHO_CFG3 UDB_DSI8_LHO_CFG4 UDB_DSI8_LHO_CFG5 UDB_DSI8_LHO_CFG6 UDB_DSI8_LHO_CFG7 UDB_DSI8_LHO_CFG8 UDB_DSI8_LHO_CFG9 UDB_DSI8_LHO_CFG10 UDB_DSI8_LHO_CFG11 UDB_DSI9_LVO1_V_2 UDB_DSI9_RVO1_V_2 UDB_DSI9_DOP_CFG0 UDB_DSI9_DOP_CFG1 UDB_DSI9_DOP_CFG2 UDB_DSI9_DOP_CFG3 UDB_DSI9_DOT_CFG0 UDB_DSI9_DOT_CFG1 UDB_DSI9_DOT_CFG2 UDB_DSI9_DOT_CFG3 UDB_DSI9_RVO_CFG0 UDB_DSI9_RVO_CFG1 UDB_DSI9_RVO_CFG2 UDB_DSI9_RVO_CFG3 UDB_DSI9_LVO_CFG0 UDB_DSI9_LVO_CFG1
Universal Digital Block (UDB) Registers
Address
Description
0x40346448 Right Horizontal Out (RHO) selection. See UDB_DSI0_RHO_CFG2 for the details of bit fields.
0x4034644C Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG0 for the details of bit fields.
0x40346450 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG1 for the details of bit fields.
0x40346454 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG2 for the details of bit fields.
0x40346458 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG3 for the details of bit fields.
0x4034645C Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG4 for the details of bit fields.
0x40346460 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG5 for the details of bit fields.
0x40346464 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG6 for the details of bit fields.
0x40346468 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG7 for the details of bit fields.
0x4034646C Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG8 for the details of bit fields.
0x40346470 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG9 for the details of bit fields.
0x40346474 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG10 for the details of bit fields.
0x40346478 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG11 for the details of bit fields.
0x40346480 0x40346484
Left Vertical Ouput (LVO) 1 vs 2 muxing for certain horizontals. See UDB_DSI0_LVO1_V_2 for the details of bit fields.
Right Vertical Ouput (RVO) 1 vs 2 muxing for certain horizontals. See UDB_DSI0_RVO1_V_2 for the details of bit fields.
0x40346488 DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG0 for the details of bit fields.
0x4034648C DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG1 for the details of bit fields.
0x40346490 DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG2 for the details of bit fields.
0x40346494 DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG3 for the details of bit fields.
0x40346498 DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG0 for the details of bit fields.
0x4034649C DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG1 for the details of bit fields.
0x403464A0 DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG2 for the details of bit fields.
0x403464A4 DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG3 for the details of bit fields.
0x403464A8 Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG0 for the details of bit fields.
0x403464AC Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG1 for the details of bit fields.
0x403464B0 Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG2 for the details of bit fields.
0x403464B4 Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG3 for the details of bit fields.
0x403464B8 Left Vertical Ouput (LVO) selection. See UDB_DSI0_LVO_CFG0 for the details of bit fields.
0x403464BC Left Vertical Ouput (LVO) selection. See UDB_DSI0_LVO_CFG1 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
842
Register UDB_DSI9_RHO_CFG0 UDB_DSI9_RHO_CFG1 UDB_DSI9_RHO_CFG2 UDB_DSI9_LHO_CFG0 UDB_DSI9_LHO_CFG1 UDB_DSI9_LHO_CFG2 UDB_DSI9_LHO_CFG3 UDB_DSI9_LHO_CFG4 UDB_DSI9_LHO_CFG5 UDB_DSI9_LHO_CFG6 UDB_DSI9_LHO_CFG7 UDB_DSI9_LHO_CFG8 UDB_DSI9_LHO_CFG9 UDB_DSI9_LHO_CFG10 UDB_DSI9_LHO_CFG11 UDB_DSI10_LVO1_V_2 UDB_DSI10_RVO1_V_2 UDB_DSI10_DOP_CFG0 UDB_DSI10_DOP_CFG1 UDB_DSI10_DOP_CFG2 UDB_DSI10_DOP_CFG3 UDB_DSI10_DOT_CFG0 UDB_DSI10_DOT_CFG1 UDB_DSI10_DOT_CFG2 UDB_DSI10_DOT_CFG3 UDB_DSI10_RVO_CFG0 UDB_DSI10_RVO_CFG1 UDB_DSI10_RVO_CFG2 UDB_DSI10_RVO_CFG3
Universal Digital Block (UDB) Registers
Address
Description
0x403464C0 Right Horizontal Out (RHO) selection. See UDB_DSI0_RHO_CFG0 for the details of bit fields.
0x403464C4 Right Horizontal Out (RHO) selection. See UDB_DSI0_RHO_CFG1 for the details of bit fields.
0x403464C8 Right Horizontal Out (RHO) selection. See UDB_DSI0_RHO_CFG2 for the details of bit fields.
0x403464CC Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG0 for the details of bit fields.
0x403464D0 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG1 for the details of bit fields.
0x403464D4 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG2 for the details of bit fields.
0x403464D8 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG3 for the details of bit fields.
0x403464DC Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG4 for the details of bit fields.
0x403464E0 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG5 for the details of bit fields.
0x403464E4 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG6 for the details of bit fields.
0x403464E8 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG7 for the details of bit fields.
0x403464EC Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG8 for the details of bit fields.
0x403464F0 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG9 for the details of bit fields.
0x403464F4 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG10 for the details of bit fields.
0x403464F8 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG11 for the details of bit fields.
0x40346500 0x40346504
Left Vertical Ouput (LVO) 1 vs 2 muxing for certain horizontals. See UDB_DSI0_LVO1_V_2 for the details of bit fields.
Right Vertical Ouput (RVO) 1 vs 2 muxing for certain horizontals. See UDB_DSI0_RVO1_V_2 for the details of bit fields.
0x40346508 DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG0 for the details of bit fields.
0x4034650C DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG1 for the details of bit fields.
0x40346510 DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG2 for the details of bit fields.
0x40346514 DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG3 for the details of bit fields.
0x40346518 DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG0 for the details of bit fields.
0x4034651C DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG1 for the details of bit fields.
0x40346520 DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG2 for the details of bit fields.
0x40346524 DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG3 for the details of bit fields.
0x40346528 Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG0 for the details of bit fields.
0x4034652C Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG1 for the details of bit fields.
0x40346530 Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG2 for the details of bit fields.
0x40346534 Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG3 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
843
Register UDB_DSI10_LVO_CFG0 UDB_DSI10_LVO_CFG1 UDB_DSI10_RHO_CFG0 UDB_DSI10_RHO_CFG1 UDB_DSI10_RHO_CFG2 UDB_DSI10_LHO_CFG0 UDB_DSI10_LHO_CFG1 UDB_DSI10_LHO_CFG2 UDB_DSI10_LHO_CFG3 UDB_DSI10_LHO_CFG4 UDB_DSI10_LHO_CFG5 UDB_DSI10_LHO_CFG6 UDB_DSI10_LHO_CFG7 UDB_DSI10_LHO_CFG8 UDB_DSI10_LHO_CFG9 UDB_DSI10_LHO_CFG10 UDB_DSI10_LHO_CFG11 UDB_DSI11_LVO1_V_2 UDB_DSI11_RVO1_V_2 UDB_DSI11_DOP_CFG0 UDB_DSI11_DOP_CFG1 UDB_DSI11_DOP_CFG2 UDB_DSI11_DOP_CFG3 UDB_DSI11_DOT_CFG0 UDB_DSI11_DOT_CFG1 UDB_DSI11_DOT_CFG2 UDB_DSI11_DOT_CFG3 UDB_DSI11_RVO_CFG0 UDB_DSI11_RVO_CFG1
Universal Digital Block (UDB) Registers
Address
Description
0x40346538 Left Vertical Ouput (LVO) selection. See UDB_DSI0_LVO_CFG0 for the details of bit fields.
0x4034653C Left Vertical Ouput (LVO) selection. See UDB_DSI0_LVO_CFG1 for the details of bit fields.
0x40346540 Right Horizontal Out (RHO) selection. See UDB_DSI0_RHO_CFG0 for the details of bit fields.
0x40346544 Right Horizontal Out (RHO) selection. See UDB_DSI0_RHO_CFG1 for the details of bit fields.
0x40346548 Right Horizontal Out (RHO) selection. See UDB_DSI0_RHO_CFG2 for the details of bit fields.
0x4034654C Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG0 for the details of bit fields.
0x40346550 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG1 for the details of bit fields.
0x40346554 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG2 for the details of bit fields.
0x40346558 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG3 for the details of bit fields.
0x4034655C Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG4 for the details of bit fields.
0x40346560 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG5 for the details of bit fields.
0x40346564 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG6 for the details of bit fields.
0x40346568 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG7 for the details of bit fields.
0x4034656C Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG8 for the details of bit fields.
0x40346570 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG9 for the details of bit fields.
0x40346574 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG10 for the details of bit fields.
0x40346578 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG11 for the details of bit fields.
0x40346580 0x40346584
Left Vertical Ouput (LVO) 1 vs 2 muxing for certain horizontals. See UDB_DSI0_LVO1_V_2 for the details of bit fields.
Right Vertical Ouput (RVO) 1 vs 2 muxing for certain horizontals. See UDB_DSI0_RVO1_V_2 for the details of bit fields.
0x40346588 DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG0 for the details of bit fields.
0x4034658C DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG1 for the details of bit fields.
0x40346590 DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG2 for the details of bit fields.
0x40346594 DSI Out Pair (DOP) selection. See UDB_DSI0_DOP_CFG3 for the details of bit fields.
0x40346598 DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG0 for the details of bit fields.
0x4034659C DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG1 for the details of bit fields.
0x403465A0 DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG2 for the details of bit fields.
0x403465A4 DSI Out Triplet (DOT) selection. See UDB_DSI0_DOT_CFG3 for the details of bit fields.
0x403465A8 Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG0 for the details of bit fields.
0x403465AC Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG1 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
844
Register UDB_DSI11_RVO_CFG2 UDB_DSI11_RVO_CFG3 UDB_DSI11_LVO_CFG0 UDB_DSI11_LVO_CFG1 UDB_DSI11_RHO_CFG0 UDB_DSI11_RHO_CFG1 UDB_DSI11_RHO_CFG2 UDB_DSI11_LHO_CFG0 UDB_DSI11_LHO_CFG1 UDB_DSI11_LHO_CFG2 UDB_DSI11_LHO_CFG3 UDB_DSI11_LHO_CFG4 UDB_DSI11_LHO_CFG5 UDB_DSI11_LHO_CFG6 UDB_DSI11_LHO_CFG7 UDB_DSI11_LHO_CFG8 UDB_DSI11_LHO_CFG9 UDB_DSI11_LHO_CFG10 UDB_DSI11_LHO_CFG11 UDB_PA0_CFG0 UDB_PA0_CFG1 UDB_PA0_CFG2 UDB_PA0_CFG3 UDB_PA0_CFG4 UDB_PA0_CFG5 UDB_PA0_CFG6 UDB_PA0_CFG7 UDB_PA0_CFG8 UDB_PA0_CFG9
Universal Digital Block (UDB) Registers
Address
Description
0x403465B0 Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG2 for the details of bit fields.
0x403465B4 Right Vertical Ouput (RVO) selection. See UDB_DSI0_RVO_CFG3 for the details of bit fields.
0x403465B8 Left Vertical Ouput (LVO) selection. See UDB_DSI0_LVO_CFG0 for the details of bit fields.
0x403465BC Left Vertical Ouput (LVO) selection. See UDB_DSI0_LVO_CFG1 for the details of bit fields.
0x403465C0 Right Horizontal Out (RHO) selection. See UDB_DSI0_RHO_CFG0 for the details of bit fields.
0x403465C4 Right Horizontal Out (RHO) selection. See UDB_DSI0_RHO_CFG1 for the details of bit fields.
0x403465C8 Right Horizontal Out (RHO) selection. See UDB_DSI0_RHO_CFG2 for the details of bit fields.
0x403465CC Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG0 for the details of bit fields.
0x403465D0 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG1 for the details of bit fields.
0x403465D4 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG2 for the details of bit fields.
0x403465D8 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG3 for the details of bit fields.
0x403465DC Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG4 for the details of bit fields.
0x403465E0 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG5 for the details of bit fields.
0x403465E4 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG6 for the details of bit fields.
0x403465E8 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG7 for the details of bit fields.
0x403465EC Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG8 for the details of bit fields.
0x403465F0 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG9 for the details of bit fields.
0x403465F4 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG10 for the details of bit fields.
0x403465F8 Left Horizontal Out (LHO) selection. See UDB_DSI0_LHO_CFG11 for the details of bit fields.
0x40347000 PA Data In Clock Control Register
0x40347004 PA Data Out Clock Control Register
0x40347008 PA Clock Select Register
0x4034700C PA Reset Select Register
0x40347010 PA Reset Enable Register
0x40347014 PA Reset Pin Select Register
0x40347018 PA Input Data Sync Control Register - Low
0x4034701C PA Input Data Sync Control Register - High
0x40347020 PA Output Data Sync Control Register - Low
0x40347024 PA Output Data Sync Control Register - High
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
845
Register UDB_PA0_CFG10 UDB_PA0_CFG11 UDB_PA0_CFG12 UDB_PA0_CFG13 UDB_PA0_CFG14 UDB_PA1_CFG0 UDB_PA1_CFG1 UDB_PA1_CFG2 UDB_PA1_CFG3 UDB_PA1_CFG4 UDB_PA1_CFG5 UDB_PA1_CFG6 UDB_PA1_CFG7 UDB_PA1_CFG8 UDB_PA1_CFG9 UDB_PA1_CFG10 UDB_PA1_CFG11 UDB_PA1_CFG12 UDB_PA1_CFG13 UDB_PA1_CFG14 UDB_PA2_CFG0 UDB_PA2_CFG1 UDB_PA2_CFG2 UDB_PA2_CFG3 UDB_PA2_CFG4 UDB_PA2_CFG5 UDB_PA2_CFG6 UDB_PA2_CFG7 UDB_PA2_CFG8
Universal Digital Block (UDB) Registers
Address
Description
0x40347028 PA Output Data Select Register - Low
0x4034702C PA Output Data Select Register - High
0x40347030 PA OE Select Register - Low
0x40347034 PA OE Select Register - High
0x40347038 PA OE Sync Register
0x40347040 PA Data In Clock Control Register. See UDB_PA0_CFG0 for the details of bit fields.
0x40347044 PA Data Out Clock Control Register. See UDB_PA0_CFG1 for the details of bit fields.
0x40347048 PA Clock Select Register. See UDB_PA0_CFG2 for the details of bit fields.
0x4034704C PA Reset Select Register. See UDB_PA0_CFG3 for the details of bit fields.
0x40347050 PA Reset Enable Register. See UDB_PA0_CFG4 for the details of bit fields.
0x40347054 PA Reset Pin Select Register. See UDB_PA0_CFG5 for the details of bit fields.
0x40347058 PA Input Data Sync Control Register - Low. See UDB_PA0_CFG6 for the details of bit fields.
0x4034705C PA Input Data Sync Control Register - High. See UDB_PA0_CFG7 for the details of bit fields.
0x40347060 PA Output Data Sync Control Register - Low. See UDB_PA0_CFG8 for the details of bit fields.
0x40347064
PA Output Data Sync Control Register - High. See UDB_PA0_CFG9 for the details of bit fields.
0x40347068 PA Output Data Select Register - Low. See UDB_PA0_CFG10 for the details of bit fields.
0x4034706C PA Output Data Select Register - High. See UDB_PA0_CFG11 for the details of bit fields.
0x40347070 PA OE Select Register - Low. See UDB_PA0_CFG12 for the details of bit fields.
0x40347074 PA OE Select Register - High. See UDB_PA0_CFG13 for the details of bit fields.
0x40347078 PA OE Sync Register. See UDB_PA0_CFG14 for the details of bit fields.
0x40347080 PA Data In Clock Control Register. See UDB_PA0_CFG0 for the details of bit fields.
0x40347084 PA Data Out Clock Control Register. See UDB_PA0_CFG1 for the details of bit fields.
0x40347088 PA Clock Select Register. See UDB_PA0_CFG2 for the details of bit fields.
0x4034708C PA Reset Select Register. See UDB_PA0_CFG3 for the details of bit fields.
0x40347090 PA Reset Enable Register. See UDB_PA0_CFG4 for the details of bit fields.
0x40347094 PA Reset Pin Select Register. See UDB_PA0_CFG5 for the details of bit fields.
0x40347098 PA Input Data Sync Control Register - Low. See UDB_PA0_CFG6 for the details of bit fields.
0x4034709C PA Input Data Sync Control Register - High. See UDB_PA0_CFG7 for the details of bit fields.
0x403470A0 PA Output Data Sync Control Register - Low. See UDB_PA0_CFG8 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
846
Register UDB_PA2_CFG9 UDB_PA2_CFG10 UDB_PA2_CFG11 UDB_PA2_CFG12 UDB_PA2_CFG13 UDB_PA2_CFG14 UDB_PA3_CFG0 UDB_PA3_CFG1 UDB_PA3_CFG2 UDB_PA3_CFG3 UDB_PA3_CFG4 UDB_PA3_CFG5 UDB_PA3_CFG6 UDB_PA3_CFG7 UDB_PA3_CFG8 UDB_PA3_CFG9 UDB_PA3_CFG10 UDB_PA3_CFG11 UDB_PA3_CFG12 UDB_PA3_CFG13 UDB_PA3_CFG14 UDB_PA4_CFG0 UDB_PA4_CFG1 UDB_PA4_CFG2 UDB_PA4_CFG3 UDB_PA4_CFG4 UDB_PA4_CFG5 UDB_PA4_CFG6 UDB_PA4_CFG7
Universal Digital Block (UDB) Registers
Address 0x403470A4
Description
PA Output Data Sync Control Register - High. See UDB_PA0_CFG9 for the details of bit fields.
0x403470A8 PA Output Data Select Register - Low. See UDB_PA0_CFG10 for the details of bit fields.
0x403470AC PA Output Data Select Register - High. See UDB_PA0_CFG11 for the details of bit fields.
0x403470B0 PA OE Select Register - Low. See UDB_PA0_CFG12 for the details of bit fields.
0x403470B4 PA OE Select Register - High. See UDB_PA0_CFG13 for the details of bit fields.
0x403470B8 PA OE Sync Register. See UDB_PA0_CFG14 for the details of bit fields.
0x403470C0 PA Data In Clock Control Register. See UDB_PA0_CFG0 for the details of bit fields.
0x403470C4 PA Data Out Clock Control Register. See UDB_PA0_CFG1 for the details of bit fields.
0x403470C8 PA Clock Select Register. See UDB_PA0_CFG2 for the details of bit fields.
0x403470CC PA Reset Select Register. See UDB_PA0_CFG3 for the details of bit fields.
0x403470D0 PA Reset Enable Register. See UDB_PA0_CFG4 for the details of bit fields.
0x403470D4 PA Reset Pin Select Register. See UDB_PA0_CFG5 for the details of bit fields.
0x403470D8 PA Input Data Sync Control Register - Low. See UDB_PA0_CFG6 for the details of bit fields.
0x403470DC PA Input Data Sync Control Register - High. See UDB_PA0_CFG7 for the details of bit fields.
0x403470E0 PA Output Data Sync Control Register - Low. See UDB_PA0_CFG8 for the details of bit fields.
0x403470E4
PA Output Data Sync Control Register - High. See UDB_PA0_CFG9 for the details of bit fields.
0x403470E8 PA Output Data Select Register - Low. See UDB_PA0_CFG10 for the details of bit fields.
0x403470EC PA Output Data Select Register - High. See UDB_PA0_CFG11 for the details of bit fields.
0x403470F0 PA OE Select Register - Low. See UDB_PA0_CFG12 for the details of bit fields.
0x403470F4 PA OE Select Register - High. See UDB_PA0_CFG13 for the details of bit fields.
0x403470F8 PA OE Sync Register. See UDB_PA0_CFG14 for the details of bit fields.
0x40347100 PA Data In Clock Control Register. See UDB_PA0_CFG0 for the details of bit fields.
0x40347104 PA Data Out Clock Control Register. See UDB_PA0_CFG1 for the details of bit fields.
0x40347108 PA Clock Select Register. See UDB_PA0_CFG2 for the details of bit fields.
0x4034710C PA Reset Select Register. See UDB_PA0_CFG3 for the details of bit fields.
0x40347110 PA Reset Enable Register. See UDB_PA0_CFG4 for the details of bit fields.
0x40347114 PA Reset Pin Select Register. See UDB_PA0_CFG5 for the details of bit fields.
0x40347118 PA Input Data Sync Control Register - Low. See UDB_PA0_CFG6 for the details of bit fields.
0x4034711C PA Input Data Sync Control Register - High. See UDB_PA0_CFG7 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
847
Register UDB_PA4_CFG8 UDB_PA4_CFG9 UDB_PA4_CFG10 UDB_PA4_CFG11 UDB_PA4_CFG12 UDB_PA4_CFG13 UDB_PA4_CFG14 UDB_PA5_CFG0 UDB_PA5_CFG1 UDB_PA5_CFG2 UDB_PA5_CFG3 UDB_PA5_CFG4 UDB_PA5_CFG5 UDB_PA5_CFG6 UDB_PA5_CFG7 UDB_PA5_CFG8 UDB_PA5_CFG9 UDB_PA5_CFG10 UDB_PA5_CFG11 UDB_PA5_CFG12 UDB_PA5_CFG13 UDB_PA5_CFG14 UDB_PA6_CFG0 UDB_PA6_CFG1 UDB_PA6_CFG2 UDB_PA6_CFG3 UDB_PA6_CFG4 UDB_PA6_CFG5 UDB_PA6_CFG6
Universal Digital Block (UDB) Registers
Address
Description
0x40347120 PA Output Data Sync Control Register - Low. See UDB_PA0_CFG8 for the details of bit fields.
0x40347124
PA Output Data Sync Control Register - High. See UDB_PA0_CFG9 for the details of bit fields.
0x40347128 PA Output Data Select Register - Low. See UDB_PA0_CFG10 for the details of bit fields.
0x4034712C PA Output Data Select Register - High. See UDB_PA0_CFG11 for the details of bit fields.
0x40347130 PA OE Select Register - Low. See UDB_PA0_CFG12 for the details of bit fields.
0x40347134 PA OE Select Register - High. See UDB_PA0_CFG13 for the details of bit fields.
0x40347138 PA OE Sync Register. See UDB_PA0_CFG14 for the details of bit fields.
0x40347140 PA Data In Clock Control Register. See UDB_PA0_CFG0 for the details of bit fields.
0x40347144 PA Data Out Clock Control Register. See UDB_PA0_CFG1 for the details of bit fields.
0x40347148 PA Clock Select Register. See UDB_PA0_CFG2 for the details of bit fields.
0x4034714C PA Reset Select Register. See UDB_PA0_CFG3 for the details of bit fields.
0x40347150 PA Reset Enable Register. See UDB_PA0_CFG4 for the details of bit fields.
0x40347154 PA Reset Pin Select Register. See UDB_PA0_CFG5 for the details of bit fields.
0x40347158 PA Input Data Sync Control Register - Low. See UDB_PA0_CFG6 for the details of bit fields.
0x4034715C PA Input Data Sync Control Register - High. See UDB_PA0_CFG7 for the details of bit fields.
0x40347160 PA Output Data Sync Control Register - Low. See UDB_PA0_CFG8 for the details of bit fields.
0x40347164
PA Output Data Sync Control Register - High. See UDB_PA0_CFG9 for the details of bit fields.
0x40347168 PA Output Data Select Register - Low. See UDB_PA0_CFG10 for the details of bit fields.
0x4034716C PA Output Data Select Register - High. See UDB_PA0_CFG11 for the details of bit fields.
0x40347170 PA OE Select Register - Low. See UDB_PA0_CFG12 for the details of bit fields.
0x40347174 PA OE Select Register - High. See UDB_PA0_CFG13 for the details of bit fields.
0x40347178 PA OE Sync Register. See UDB_PA0_CFG14 for the details of bit fields.
0x40347180 PA Data In Clock Control Register. See UDB_PA0_CFG0 for the details of bit fields.
0x40347184 PA Data Out Clock Control Register. See UDB_PA0_CFG1 for the details of bit fields.
0x40347188 PA Clock Select Register. See UDB_PA0_CFG2 for the details of bit fields.
0x4034718C PA Reset Select Register. See UDB_PA0_CFG3 for the details of bit fields.
0x40347190 PA Reset Enable Register. See UDB_PA0_CFG4 for the details of bit fields.
0x40347194 PA Reset Pin Select Register. See UDB_PA0_CFG5 for the details of bit fields.
0x40347198 PA Input Data Sync Control Register - Low. See UDB_PA0_CFG6 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
848
Register UDB_PA6_CFG7 UDB_PA6_CFG8 UDB_PA6_CFG9 UDB_PA6_CFG10 UDB_PA6_CFG11 UDB_PA6_CFG12 UDB_PA6_CFG13 UDB_PA6_CFG14 UDB_PA7_CFG0 UDB_PA7_CFG1 UDB_PA7_CFG2 UDB_PA7_CFG3 UDB_PA7_CFG4 UDB_PA7_CFG5 UDB_PA7_CFG6 UDB_PA7_CFG7 UDB_PA7_CFG8 UDB_PA7_CFG9 UDB_PA7_CFG10 UDB_PA7_CFG11 UDB_PA7_CFG12 UDB_PA7_CFG13 UDB_PA7_CFG14 UDB_PA8_CFG0 UDB_PA8_CFG1 UDB_PA8_CFG2 UDB_PA8_CFG3 UDB_PA8_CFG4 UDB_PA8_CFG5
Universal Digital Block (UDB) Registers
Address
Description
0x4034719C PA Input Data Sync Control Register - High. See UDB_PA0_CFG7 for the details of bit fields.
0x403471A0 PA Output Data Sync Control Register - Low. See UDB_PA0_CFG8 for the details of bit fields.
0x403471A4
PA Output Data Sync Control Register - High. See UDB_PA0_CFG9 for the details of bit fields.
0x403471A8 PA Output Data Select Register - Low. See UDB_PA0_CFG10 for the details of bit fields.
0x403471AC PA Output Data Select Register - High. See UDB_PA0_CFG11 for the details of bit fields.
0x403471B0 PA OE Select Register - Low. See UDB_PA0_CFG12 for the details of bit fields.
0x403471B4 PA OE Select Register - High. See UDB_PA0_CFG13 for the details of bit fields.
0x403471B8 PA OE Sync Register. See UDB_PA0_CFG14 for the details of bit fields.
0x403471C0 PA Data In Clock Control Register. See UDB_PA0_CFG0 for the details of bit fields.
0x403471C4 PA Data Out Clock Control Register. See UDB_PA0_CFG1 for the details of bit fields.
0x403471C8 PA Clock Select Register. See UDB_PA0_CFG2 for the details of bit fields.
0x403471CC PA Reset Select Register. See UDB_PA0_CFG3 for the details of bit fields.
0x403471D0 PA Reset Enable Register. See UDB_PA0_CFG4 for the details of bit fields.
0x403471D4 PA Reset Pin Select Register. See UDB_PA0_CFG5 for the details of bit fields.
0x403471D8 PA Input Data Sync Control Register - Low. See UDB_PA0_CFG6 for the details of bit fields.
0x403471DC PA Input Data Sync Control Register - High. See UDB_PA0_CFG7 for the details of bit fields.
0x403471E0 PA Output Data Sync Control Register - Low. See UDB_PA0_CFG8 for the details of bit fields.
0x403471E4
PA Output Data Sync Control Register - High. See UDB_PA0_CFG9 for the details of bit fields.
0x403471E8 PA Output Data Select Register - Low. See UDB_PA0_CFG10 for the details of bit fields.
0x403471EC PA Output Data Select Register - High. See UDB_PA0_CFG11 for the details of bit fields.
0x403471F0 PA OE Select Register - Low. See UDB_PA0_CFG12 for the details of bit fields.
0x403471F4 PA OE Select Register - High. See UDB_PA0_CFG13 for the details of bit fields.
0x403471F8 PA OE Sync Register. See UDB_PA0_CFG14 for the details of bit fields.
0x40347200 PA Data In Clock Control Register. See UDB_PA0_CFG0 for the details of bit fields.
0x40347204 PA Data Out Clock Control Register. See UDB_PA0_CFG1 for the details of bit fields.
0x40347208 PA Clock Select Register. See UDB_PA0_CFG2 for the details of bit fields.
0x4034720C PA Reset Select Register. See UDB_PA0_CFG3 for the details of bit fields.
0x40347210 PA Reset Enable Register. See UDB_PA0_CFG4 for the details of bit fields.
0x40347214 PA Reset Pin Select Register. See UDB_PA0_CFG5 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
849
Register UDB_PA8_CFG6 UDB_PA8_CFG7 UDB_PA8_CFG8 UDB_PA8_CFG9 UDB_PA8_CFG10 UDB_PA8_CFG11 UDB_PA8_CFG12 UDB_PA8_CFG13 UDB_PA8_CFG14 UDB_PA9_CFG0 UDB_PA9_CFG1 UDB_PA9_CFG2 UDB_PA9_CFG3 UDB_PA9_CFG4 UDB_PA9_CFG5 UDB_PA9_CFG6 UDB_PA9_CFG7 UDB_PA9_CFG8 UDB_PA9_CFG9 UDB_PA9_CFG10 UDB_PA9_CFG11 UDB_PA9_CFG12 UDB_PA9_CFG13 UDB_PA9_CFG14 UDB_PA10_CFG0 UDB_PA10_CFG1 UDB_PA10_CFG2 UDB_PA10_CFG3 UDB_PA10_CFG4
Universal Digital Block (UDB) Registers
Address
Description
0x40347218 PA Input Data Sync Control Register - Low. See UDB_PA0_CFG6 for the details of bit fields.
0x4034721C PA Input Data Sync Control Register - High. See UDB_PA0_CFG7 for the details of bit fields.
0x40347220 PA Output Data Sync Control Register - Low. See UDB_PA0_CFG8 for the details of bit fields.
0x40347224
PA Output Data Sync Control Register - High. See UDB_PA0_CFG9 for the details of bit fields.
0x40347228 PA Output Data Select Register - Low. See UDB_PA0_CFG10 for the details of bit fields.
0x4034722C PA Output Data Select Register - High. See UDB_PA0_CFG11 for the details of bit fields.
0x40347230 PA OE Select Register - Low. See UDB_PA0_CFG12 for the details of bit fields.
0x40347234 PA OE Select Register - High. See UDB_PA0_CFG13 for the details of bit fields.
0x40347238 PA OE Sync Register. See UDB_PA0_CFG14 for the details of bit fields.
0x40347240 PA Data In Clock Control Register. See UDB_PA0_CFG0 for the details of bit fields.
0x40347244 PA Data Out Clock Control Register. See UDB_PA0_CFG1 for the details of bit fields.
0x40347248 PA Clock Select Register. See UDB_PA0_CFG2 for the details of bit fields.
0x4034724C PA Reset Select Register. See UDB_PA0_CFG3 for the details of bit fields.
0x40347250 PA Reset Enable Register. See UDB_PA0_CFG4 for the details of bit fields.
0x40347254 PA Reset Pin Select Register. See UDB_PA0_CFG5 for the details of bit fields.
0x40347258 PA Input Data Sync Control Register - Low. See UDB_PA0_CFG6 for the details of bit fields.
0x4034725C PA Input Data Sync Control Register - High. See UDB_PA0_CFG7 for the details of bit fields.
0x40347260 PA Output Data Sync Control Register - Low. See UDB_PA0_CFG8 for the details of bit fields.
0x40347264
PA Output Data Sync Control Register - High. See UDB_PA0_CFG9 for the details of bit fields.
0x40347268 PA Output Data Select Register - Low. See UDB_PA0_CFG10 for the details of bit fields.
0x4034726C PA Output Data Select Register - High. See UDB_PA0_CFG11 for the details of bit fields.
0x40347270 PA OE Select Register - Low. See UDB_PA0_CFG12 for the details of bit fields.
0x40347274 PA OE Select Register - High. See UDB_PA0_CFG13 for the details of bit fields.
0x40347278 PA OE Sync Register. See UDB_PA0_CFG14 for the details of bit fields.
0x40347280 PA Data In Clock Control Register. See UDB_PA0_CFG0 for the details of bit fields.
0x40347284 PA Data Out Clock Control Register. See UDB_PA0_CFG1 for the details of bit fields.
0x40347288 PA Clock Select Register. See UDB_PA0_CFG2 for the details of bit fields.
0x4034728C PA Reset Select Register. See UDB_PA0_CFG3 for the details of bit fields.
0x40347290 PA Reset Enable Register. See UDB_PA0_CFG4 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
850
Register UDB_PA10_CFG5 UDB_PA10_CFG6 UDB_PA10_CFG7 UDB_PA10_CFG8 UDB_PA10_CFG9 UDB_PA10_CFG10 UDB_PA10_CFG11 UDB_PA10_CFG12 UDB_PA10_CFG13 UDB_PA10_CFG14 UDB_PA11_CFG0 UDB_PA11_CFG1 UDB_PA11_CFG2 UDB_PA11_CFG3 UDB_PA11_CFG4 UDB_PA11_CFG5 UDB_PA11_CFG6 UDB_PA11_CFG7 UDB_PA11_CFG8 UDB_PA11_CFG9 UDB_PA11_CFG10 UDB_PA11_CFG11 UDB_PA11_CFG12 UDB_PA11_CFG13 UDB_PA11_CFG14 UDB_BCTL_MDCLK_EN UDB_BCTL_MBCLK_EN UDB_BCTL_BOTSEL_L UDB_BCTL_BOTSEL_U
Universal Digital Block (UDB) Registers
Address
Description
0x40347294 PA Reset Pin Select Register. See UDB_PA0_CFG5 for the details of bit fields.
0x40347298 PA Input Data Sync Control Register - Low. See UDB_PA0_CFG6 for the details of bit fields.
0x4034729C PA Input Data Sync Control Register - High. See UDB_PA0_CFG7 for the details of bit fields.
0x403472A0 PA Output Data Sync Control Register - Low. See UDB_PA0_CFG8 for the details of bit fields.
0x403472A4
PA Output Data Sync Control Register - High. See UDB_PA0_CFG9 for the details of bit fields.
0x403472A8 PA Output Data Select Register - Low. See UDB_PA0_CFG10 for the details of bit fields.
0x403472AC PA Output Data Select Register - High. See UDB_PA0_CFG11 for the details of bit fields.
0x403472B0 PA OE Select Register - Low. See UDB_PA0_CFG12 for the details of bit fields.
0x403472B4 PA OE Select Register - High. See UDB_PA0_CFG13 for the details of bit fields.
0x403472B8 PA OE Sync Register. See UDB_PA0_CFG14 for the details of bit fields.
0x403472C0 PA Data In Clock Control Register. See UDB_PA0_CFG0 for the details of bit fields.
0x403472C4 PA Data Out Clock Control Register. See UDB_PA0_CFG1 for the details of bit fields.
0x403472C8 PA Clock Select Register. See UDB_PA0_CFG2 for the details of bit fields.
0x403472CC PA Reset Select Register. See UDB_PA0_CFG3 for the details of bit fields.
0x403472D0 PA Reset Enable Register. See UDB_PA0_CFG4 for the details of bit fields.
0x403472D4 PA Reset Pin Select Register. See UDB_PA0_CFG5 for the details of bit fields.
0x403472D8 PA Input Data Sync Control Register - Low. See UDB_PA0_CFG6 for the details of bit fields.
0x403472DC PA Input Data Sync Control Register - High. See UDB_PA0_CFG7 for the details of bit fields.
0x403472E0 PA Output Data Sync Control Register - Low. See UDB_PA0_CFG8 for the details of bit fields.
0x403472E4
PA Output Data Sync Control Register - High. See UDB_PA0_CFG9 for the details of bit fields.
0x403472E8 PA Output Data Select Register - Low. See UDB_PA0_CFG10 for the details of bit fields.
0x403472EC PA Output Data Select Register - High. See UDB_PA0_CFG11 for the details of bit fields.
0x403472F0 PA OE Select Register - Low. See UDB_PA0_CFG12 for the details of bit fields.
0x403472F4 PA OE Select Register - High. See UDB_PA0_CFG13 for the details of bit fields.
0x403472F8 PA OE Sync Register. See UDB_PA0_CFG14 for the details of bit fields.
0x40347800 Master Digital Clock Enable Register
0x40347804 Master clk_peri_app Enable Register
0x40347808 Lower Nibble Bottom Digital Clock Select Register
0x4034780C Upper Nibble Bottom Digital Clock Select Register
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
851
Register UDB_BCTL_QCLK_EN0 UDB_BCTL_QCLK_EN1 UDB_BCTL_QCLK_EN2 UDB_UDBIF_BANK_CTL UDB_UDBIF_INT_CLK_CTL UDB_UDBIF_INT_CFG UDB_UDBIF_TR_CLK_CTL UDB_UDBIF_TR_CFG UDB_UDBIF_PRIVATE
Universal Digital Block (UDB) Registers
Address
Description
0x40347810 Quadrant Digital Clock Enable Registers
0x40347814 0x40347818
Quadrant Digital Clock Enable Registers. See UDB_BCTL_QCLK_EN0 for the details of bit fields.
Quadrant Digital Clock Enable Registers. See UDB_BCTL_QCLK_EN0 for the details of bit fields.
0x40347900 Bank Control
0x40347904 Interrupt Clock Control
0x40347908 Interrupt Configuration
0x4034790C Trigger Clock Control
0x40347910 Trigger Configuration
0x40347914 Internal use only
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
852
UDB_WRKONE_A0
18.1.1 UDB_WRKONE_A0
Address = 0x40340000 Accumulator Registers {A1,A0} Address: 0x40340000 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
A0 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
RW
Name
A1 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 8
7 : 0
Name A1
A0
Description
Accumulator 1 Register Default Value: 0
Accumulator 0 Register Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
853
UDB_WRKONE_D0
18.1.2 UDB_WRKONE_D0
Address = 0x40340100 Data Registers {D1,D0} Address: 0x40340100 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
D0 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
RW
Name
D1 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 8
7 : 0
Name D1
D0
Description
Data 1 Register Default Value: 0
Data 0 Register Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
854
UDB_WRKONE_F0
18.1.3 UDB_WRKONE_F0
Address = 0x40340200 FIFOs {F1,F0} Address: 0x40340200 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
F0 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
RW
Name
F1 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 8
7 : 0
Name F1
F0
Description
FIFO 1 Default Value: X
FIFO 0 Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
855
UDB_WRKONE_CTL_ST0
18.1.4 UDB_WRKONE_CTL_ST0
Address = 0x40340300 Status and Control Registers {CTL,ST} Address: 0x40340300 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
ST [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
CTL [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 8
7 : 0
Name CTL
ST
Description
Control Register Default Value: 0
Status Register Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
856
UDB_WRKONE_ACTL_MSK0
18.1.5 UDB_WRKONE_ACTL_MSK0
Address = 0x40340400 Mask and Auxiliary Control Registers {ACTL,MSK} Address: 0x40340400 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None
MSK [6:0]
Bits SW Access HW Access
Name
15
14
None
None
None [15:14]
13
RW
R
CNT_STAR T
12 RW R
INT_EN
11
10
9
8
RW
RW
RW
RW
R
R
R
R
FIFO1_LVL FIFO0_LVL FIFO1_CLR FIFO0_CLR
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
13
CNT_START
12
INT_EN
11
FIFO1_LVL
Description
Control Register Counter Enable Default Value: 0
0x0: DISABLE : Counter disabled
0x1: ENABLE : Counter enabled
enable interrupt Default Value: 0
0x0: DISABLE : Interrupt disabled
0x1: ENABLE : Interrupt enabled
FIFO fill status level control Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
857
UDB_WRKONE_ACTL_MSK0
18.1.5
10 9 8 6 : 0
UDB_WRKONE_ACTL_MSK0 (continued)
FIFO0_LVL FIFO1_CLR FIFO0_CLR MSK
0x0: NORMAL : input mode: FIFO not full; output mode: FIFO not empty
0x1: MID : input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full
FIFO fill status level control Default Value: 0
0x0: NORMAL : input mode: FIFO not full; output mode: FIFO not empty
0x1: MID : input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full
FIFO clear Default Value: 0
0x0: NORMAL : Normal FIFO operation
0x1: CLEAR : Clear FIFO state
FIFO clear Default Value: 0
0x0: NORMAL : Normal FIFO operation
0x1: CLEAR : Clear FIFO state
Interrupt Mask Register Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
858
UDB_WRKONE_MC0
18.1.6 UDB_WRKONE_MC0
Address = 0x40340500 PLD Macrocell Read Registers {00,MC} Address: 0x40340500 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
R
HW Access
W
W
Name
PLD1_MC [7:4]
PLD0_MC [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 4
3 : 0
Name PLD1_MC
PLD0_MC
Description
PLD1 Macrocell Read Register Default Value: 0
PLD0 Macrocell Read Register Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
859
UDB_WRKMULT_A00
18.1.7 UDB_WRKMULT_A00
Address = 0x40341000 Accumulator 0 Address: 0x40341000 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
A0_0 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
RW
Name
A0_1 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
RW
Name
A0_2 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
RW
Name
A0_3 [31:24]
Bits 31 : 24 23 : 16 15 : 8 7 : 0
Name A0_3 A0_2 A0_1 A0_0
Description
Accumulator 0 for UDB[n+3] Default Value: 0
Accumulator 0 for UDB[n+2] Default Value: 0
Accumulator 0 for UDB[n+1] Default Value: 0
Accumulator 0 for UDB[n] Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
860
UDB_WRKMULT_A10
18.1.8 UDB_WRKMULT_A10
Address = 0x40341100 Accumulator 1 Address: 0x40341100 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
A1_0 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
RW
Name
A1_1 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
RW
Name
A1_2 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
RW
Name
A1_3 [31:24]
Bits 31 : 24 23 : 16 15 : 8 7 : 0
Name A1_3 A1_2 A1_1 A1_0
Description
Accumulator 1 for UDB[n+3] Default Value: 0
Accumulator 1 for UDB[n+2] Default Value: 0
Accumulator 1 for UDB[n+1] Default Value: 0
Accumulator 1 for UDB[n] Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
861
UDB_WRKMULT_D00
18.1.9 UDB_WRKMULT_D00
Address = 0x40341200 Data 0 Address: 0x40341200 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
D0_0 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
RW
Name
D0_1 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
RW
Name
D0_2 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
RW
Name
D0_3 [31:24]
Bits 31 : 24 23 : 16 15 : 8 7 : 0
Name D0_3 D0_2 D0_1 D0_0
Description
Data 0 for UDB[n+3] Default Value: 0
Data 0 for UDB[n+2] Default Value: 0
Data 0 for UDB[n+1] Default Value: 0
Data 0 for UDB[n] Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
862
UDB_WRKMULT_D10
18.1.10 UDB_WRKMULT_D10
Address = 0x40341300 Data 1 Address: 0x40341300 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
D1_0 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
RW
Name
D1_1 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
RW
Name
D1_2 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
RW
Name
D1_3 [31:24]
Bits 31 : 24 23 : 16 15 : 8 7 : 0
Name D1_3 D1_2 D1_1 D1_0
Description
Data 1 for UDB[n+3] Default Value: 0
Data 1 for UDB[n+2] Default Value: 0
Data 1 for UDB[n+1] Default Value: 0
Data 1 for UDB[n] Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
863
UDB_WRKMULT_F00
18.1.11 UDB_WRKMULT_F00
Address = 0x40341400 FIFO 0 Address: 0x40341400 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
F0_0 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
RW
Name
F0_1 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
RW
Name
F0_2 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
RW
Name
F0_3 [31:24]
Bits 31 : 24 23 : 16 15 : 8 7 : 0
Name F0_3 F0_2 F0_1 F0_0
Description
Fifo 0 for UDB[n+3] Default Value: X
Fifo 0 for UDB[n+2] Default Value: X
Fifo 0 for UDB[n+1] Default Value: X
Fifo 0 for UDB[n] Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
864
UDB_WRKMULT_F10
18.1.12 UDB_WRKMULT_F10
Address = 0x40341500 FIFO 1 Address: 0x40341500 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
F1_0 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
RW
Name
F1_1 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
RW
Name
F1_2 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
RW
Name
F1_3 [31:24]
Bits 31 : 24 23 : 16 15 : 8 7 : 0
Name F1_3 F1_2 F1_1 F1_0
Description
Fifo 1 for UDB[n+3] Default Value: X
Fifo 1 for UDB[n+2] Default Value: X
Fifo 1 for UDB[n+1] Default Value: X
Fifo 1 for UDB[n] Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
865
UDB_WRKMULT_ST0
18.1.13 UDB_WRKMULT_ST0
Address = 0x40341600 Status Register Address: 0x40341600 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
ST_0 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
ST_1 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
W
Name
ST_2 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
W
Name
ST_3 [31:24]
Bits 31 : 24 23 : 16 15 : 8 7 : 0
Name ST_3 ST_2 ST_1 ST_0
Description
Status register for UDB[n+3] Default Value: 0
Status register for UDB[n+2] Default Value: 0
Status register for UDB[n+1] Default Value: 0
Status register for UDB[n] Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
866
UDB_WRKMULT_CTL0
18.1.14 UDB_WRKMULT_CTL0
Address = 0x40341700 Control Register Address: 0x40341700 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
CTL_0 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
CTL_1 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
CTL_2 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
CTL_3 [31:24]
Bits 31 : 24 23 : 16 15 : 8 7 : 0
Name CTL_3 CTL_2 CTL_1 CTL_0
Description
Control register for UDB[n+3] Default Value: 0
Control register for UDB[n+2] Default Value: 0
Control register for UDB[n+1] Default Value: 0
Control register for UDB[n] Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
867
UDB_WRKMULT_MSK0
18.1.15 UDB_WRKMULT_MSK0
Address = 0x40341800 Interrupt Mask Address: 0x40341800 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None
MSK_0 [6:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
RW
HW Access
None
R
Name
None
MSK_1 [14:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
HW Access
None
R
Name
None
MSK_2 [22:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
RW
HW Access
None
R
Name
None
MSK_3 [30:24]
Bits 30 : 24 22 : 16 14 : 8 6 : 0
Name MSK_3 MSK_2 MSK_1 MSK_0
Description
Interrupt Mask Register Default Value: 0
Interrupt Mask Register Default Value: 0
Interrupt Mask Register Default Value: 0
Interrupt Mask Register Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
868
UDB_WRKMULT_ACTL0
18.1.16 UDB_WRKMULT_ACTL0
Address = 0x40341900 Auxiliary Control Address: 0x40341900 Retention: Retained
Bits SW Access HW Access
Name
7
6
None
None
None [7:6]
5
RW
R
CNT_STAR T_0
4 RW R
INT_EN_0
3
RW
R
FIFO1_LVL _0
2
RW
R
FIFO0_LVL _0
1
RW
R
FIFO1_CLR_0
0
RW
R
FIFO0_CLR_0
Bits SW Access HW Access
Name
15
14
None
None
None [15:14]
13
RW
R
CNT_STAR T_1
12 RW R
INT_EN_1
11
RW
R
FIFO1_LVL _1
10
RW
R
FIFO0_LVL _1
9
RW
R
FIFO1_CLR_1
8
RW
R
FIFO0_CLR_1
Bits SW Access HW Access
Name
23
22
None
None
None [23:22]
21
RW
R
CNT_STAR T_2
20 RW R
INT_EN_2
19
RW
R
FIFO1_LVL _2
18
RW
R
FIFO0_LVL _2
17
RW
R
FIFO1_CLR_2
16
RW
R
FIFO0_CLR_2
Bits SW Access HW Access
Name
31
30
None
None
None [31:30]
29
RW
R
CNT_STAR T_3
28 RW R
INT_EN_3
27
RW
R
FIFO1_LVL _3
26
RW
R
FIFO0_LVL _3
25
RW
R
FIFO1_CLR_3
24
RW
R
FIFO0_CLR_3
Bits
Name
29
CNT_START_3
28
INT_EN_3
Description
Control Register Counter Enable Default Value: 0
0x0: DISABLE : Counter disabled
0x1: ENABLE : Counter enabled
enable interrupt Default Value: 0
0x0: DISABLE : Interrupt disabled
0x1: ENABLE : Interrupt enabled
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
869
UDB_WRKMULT_ACTL0
18.1.16 UDB_WRKMULT_ACTL0 (continued)
27
FIFO1_LVL_3
26
FIFO0_LVL_3
25
FIFO1_CLR_3
24
FIFO0_CLR_3
21
CNT_START_2
20
INT_EN_2
19
FIFO1_LVL_2
18
FIFO0_LVL_2
FIFO fill status level control Default Value: 0
0x0: NORMAL : input mode: FIFO not full; output mode: FIFO not empty
0x1: MID : input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full
FIFO fill status level control Default Value: 0
0x0: NORMAL : input mode: FIFO not full; output mode: FIFO not empty
0x1: MID : input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full
FIFO clear Default Value: 0
0x0: NORMAL : Normal FIFO operation
0x1: CLEAR : Clear FIFO state
FIFO clear Default Value: 0
0x0: NORMAL : Normal FIFO operation
0x1: CLEAR : Clear FIFO state
Control Register Counter Enable Default Value: 0
0x0: DISABLE : Counter disabled
0x1: ENABLE : Counter enabled
enable interrupt Default Value: 0
0x0: DISABLE : Interrupt disabled
0x1: ENABLE : Interrupt enabled
FIFO fill status level control Default Value: 0
0x0: NORMAL : input mode: FIFO not full; output mode: FIFO not empty
0x1: MID : input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full
FIFO fill status level control Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
870
UDB_WRKMULT_ACTL0
18.1.16 UDB_WRKMULT_ACTL0 (continued)
17
FIFO1_CLR_2
16
FIFO0_CLR_2
13
CNT_START_1
12
INT_EN_1
11
FIFO1_LVL_1
10
FIFO0_LVL_1
9
FIFO1_CLR_1
0x0: NORMAL : input mode: FIFO not full; output mode: FIFO not empty
0x1: MID : input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full
FIFO clear Default Value: 0
0x0: NORMAL : Normal FIFO operation
0x1: CLEAR : Clear FIFO state
FIFO clear Default Value: 0
0x0: NORMAL : Normal FIFO operation
0x1: CLEAR : Clear FIFO state
Control Register Counter Enable Default Value: 0
0x0: DISABLE : Counter disabled
0x1: ENABLE : Counter enabled
enable interrupt Default Value: 0
0x0: DISABLE : Interrupt disabled
0x1: ENABLE : Interrupt enabled
FIFO fill status level control Default Value: 0
0x0: NORMAL : input mode: FIFO not full; output mode: FIFO not empty
0x1: MID : input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full
FIFO fill status level control Default Value: 0
0x0: NORMAL : input mode: FIFO not full; output mode: FIFO not empty
0x1: MID : input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full
FIFO clear Default Value: 0
0x0: NORMAL : Normal FIFO operation
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
871
UDB_WRKMULT_ACTL0
18.1.16 UDB_WRKMULT_ACTL0 (continued)
8
FIFO0_CLR_1
5
CNT_START_0
4
INT_EN_0
3
FIFO1_LVL_0
2
FIFO0_LVL_0
1
FIFO1_CLR_0
0
FIFO0_CLR_0
0x1: CLEAR : Clear FIFO state
FIFO clear Default Value: 0
0x0: NORMAL : Normal FIFO operation
0x1: CLEAR : Clear FIFO state
Control Register Counter Enable Default Value: 0
0x0: DISABLE : Counter disabled
0x1: ENABLE : Counter enabled
enable interrupt Default Value: 0
0x0: DISABLE : Interrupt disabled
0x1: ENABLE : Interrupt enabled
FIFO fill status level control Default Value: 0
0x0: NORMAL : input mode: FIFO not full; output mode: FIFO not empty
0x1: MID : input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full
FIFO fill status level control Default Value: 0
0x0: NORMAL : input mode: FIFO not full; output mode: FIFO not empty
0x1: MID : input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full
FIFO clear Default Value: 0
0x0: NORMAL : Normal FIFO operation
0x1: CLEAR : Clear FIFO state
FIFO clear Default Value: 0
0x0: NORMAL : Normal FIFO operation
0x1: CLEAR : Clear FIFO state
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
872
UDB_WRKMULT_MC0
18.1.17 UDB_WRKMULT_MC0
Address = 0x40341A00 PLD Macrocell reading Address: 0x40341A00 Retention: Not Retained
Bits
7
6
5
4
SW Access
R
HW Access
RW
Name
PLD1_MC_0 [7:4]
Bits
15
14
13
12
SW Access
R
HW Access
RW
Name
PLD1_MC_1 [15:12]
Bits
23
22
21
20
SW Access
R
HW Access
RW
Name
PLD1_MC_2 [23:20]
Bits
31
30
29
28
SW Access
R
HW Access
RW
Name
PLD1_MC_3 [31:28]
Bits 31 : 28 27 : 24 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
Name PLD1_MC_3 PLD0_MC_3 PLD1_MC_2 PLD0_MC_2 PLD1_MC_1 PLD0_MC_1 PLD1_MC_0 PLD0_MC_0
Description
Read Macrocell 1 for UDB[n+3] Default Value: 0
Read Macrocell 0 for UDB[n+3] Default Value: 0
Read Macrocell 1 for UDB[n+2] Default Value: 0
Read Macrocell 0 for UDB[n+2] Default Value: 0
Read Macrocell 1 for UDB[n+1] Default Value: 0
Read Macrocell 0 for UDB[n+1] Default Value: 0
Read Macrocell 1 for UDB[n] Default Value: 0
Read Macrocell 0 for UDB[n] Default Value: 0
3
2
1
0
R
RW
PLD0_MC_0 [3:0]
11
10
9
8
R
RW
PLD0_MC_1 [11:8]
19
18
17
16
R
RW
PLD0_MC_2 [19:16]
27
26
25
24
R
RW
PLD0_MC_3 [27:24]
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
873
UDB_UDBPAIR0_UDBSNG0_PLD_IT0
18.1.18 UDB_UDBPAIR0_UDBSNG0_PLD_IT0
Address = 0x40342000 PLD Input Terms Address: 0x40342000 Retention: Retained
Bits SW Access HW Access
Name
7
RW
R
PLD0_INx_C_-
FOR_PT7
6
RW
R
PLD0_INx_C_-
FOR_PT6
5
RW
R
PLD0_INx_C_-
FOR_PT5
4
RW
R
PLD0_INx_C_-
FOR_PT4
3
RW
R
PLD0_INx_C_-
FOR_PT3
2
RW
R
PLD0_INx_C_-
FOR_PT2
1
RW
R
PLD0_INx_C_-
FOR_PT1
0
RW
R
PLD0_INx_C_-
FOR_PT0
Bits SW Access HW Access
Name
15
RW
R
PLD1_INx_C_-
FOR_PT7
14
RW
R
PLD1_INx_C_-
FOR_PT6
13
RW
R
PLD1_INx_C_-
FOR_PT5
12
RW
R
PLD1_INx_C_-
FOR_PT4
11
RW
R
PLD1_INx_C_-
FOR_PT3
10
RW
R
PLD1_INx_C_-
FOR_PT2
9
RW
R
PLD1_INx_C_-
FOR_PT1
8
RW
R
PLD1_INx_C_-
FOR_PT0
Bits SW Access HW Access
Name
23
RW
R
PLD0_INx_T_-
FOR_PT7
22
RW
R
PLD0_INx_T_-
FOR_PT6
21
RW
R
PLD0_INx_T_-
FOR_PT5
20
RW
R
PLD0_INx_T_-
FOR_PT4
19
RW
R
PLD0_INx_T_-
FOR_PT3
18
RW
R
PLD0_INx_T_-
FOR_PT2
17
RW
R
PLD0_INx_T_-
FOR_PT1
16
RW
R
PLD0_INx_T_-
FOR_PT0
Bits SW Access HW Access
Name
31
RW
R
PLD1_INx_T_-
FOR_PT7
30
RW
R
PLD1_INx_T_-
FOR_PT6
29
RW
R
PLD1_INx_T_-
FOR_PT5
28
RW
R
PLD1_INx_T_-
FOR_PT4
27
RW
R
PLD1_INx_T_-
FOR_PT3
26
RW
R
PLD1_INx_T_-
FOR_PT2
25
RW
R
PLD1_INx_T_-
FOR_PT1
24
RW
R
PLD1_INx_T_-
FOR_PT0
Bits
Name
Description
31
PLD1_INx_T_FOR_PT7 True input term
Default Value: X
30
PLD1_INx_T_FOR_PT6 True input term
Default Value: X
29
PLD1_INx_T_FOR_PT5 True input term
Default Value: X
28
PLD1_INx_T_FOR_PT4 True input term
Default Value: X
27
PLD1_INx_T_FOR_PT3 True input term
Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
874
UDB_UDBPAIR0_UDBSNG0_PLD_IT0
18.1.18 UDB_UDBPAIR0_UDBSNG0_PLD_IT0 (continued)
26
PLD1_INx_T_FOR_PT2 True input term
Default Value: X
25
PLD1_INx_T_FOR_PT1 True input term
Default Value: X
24
PLD1_INx_T_FOR_PT0 True input term
Default Value: X
23
PLD0_INx_T_FOR_PT7 True input term
Default Value: X
22
PLD0_INx_T_FOR_PT6 True input term
Default Value: X
21
PLD0_INx_T_FOR_PT5 True input term
Default Value: X
20
PLD0_INx_T_FOR_PT4 True input term
Default Value: X
19
PLD0_INx_T_FOR_PT3 True input term
Default Value: X
18
PLD0_INx_T_FOR_PT2 True input term
Default Value: X
17
PLD0_INx_T_FOR_PT1 True input term
Default Value: X
16
PLD0_INx_T_FOR_PT0 True input term
Default Value: X
15
PLD1_INx_C_FOR_PT7 Complement input term
Default Value: X
14
PLD1_INx_C_FOR_PT6 Complement input term
Default Value: X
13
PLD1_INx_C_FOR_PT5 Complement input term
Default Value: X
12
PLD1_INx_C_FOR_PT4 Complement input term
Default Value: X
11
PLD1_INx_C_FOR_PT3 Complement input term
Default Value: X
10
PLD1_INx_C_FOR_PT2 Complement input term
Default Value: X
9
PLD1_INx_C_FOR_PT1 Complement input term
Default Value: X
8
PLD1_INx_C_FOR_PT0 Complement input term
Default Value: X
7
PLD0_INx_C_FOR_PT7 Complement input term
Default Value: X
6
PLD0_INx_C_FOR_PT6 Complement input term
Default Value: X
5
PLD0_INx_C_FOR_PT5 Complement input term
Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
875
UDB_UDBPAIR0_UDBSNG0_PLD_IT0
18.1.18 UDB_UDBPAIR0_UDBSNG0_PLD_IT0 (continued)
4
PLD0_INx_C_FOR_PT4 Complement input term
Default Value: X
3
PLD0_INx_C_FOR_PT3 Complement input term
Default Value: X
2
PLD0_INx_C_FOR_PT2 Complement input term
Default Value: X
1
PLD0_INx_C_FOR_PT1 Complement input term
Default Value: X
0
PLD0_INx_C_FOR_PT0 Complement input term
Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
876
UDB_UDBPAIR0_UDBSNG0_PLD_ORT0
18.1.19 UDB_UDBPAIR0_UDBSNG0_PLD_ORT0
Address = 0x40342030 PLD OR Terms Address: 0x40342030 Retention: Retained
Bits SW Access HW Access
Name
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
R
R
R
R
R
R
R
R
PLD0_PT7_ PLD0_PT6_ PLD0_PT5_ PLD0_PT4_ PLD0_PT3_ PLD0_PT2_ PLD0_PT1_ PLD0_PT0_
T_-
T_-
T_-
T_-
T_-
T_-
T_-
T_-
FOR_OUT0 FOR_OUT0 FOR_OUT0 FOR_OUT0 FOR_OUT0 FOR_OUT0 FOR_OUT0 FOR_OUT0
Bits SW Access HW Access
Name
15
14
13
12
11
10
9
8
RW
RW
RW
RW
RW
RW
RW
RW
R
R
R
R
R
R
R
R
PLD1_PT7_ PLD1_PT6_ PLD1_PT5_ PLD1_PT4_ PLD1_PT3_ PLD1_PT2_ PLD1_PT1_ PLD1_PT0_
T_-
T_-
T_-
T_-
T_-
T_-
T_-
T_-
FOR_OUT0 FOR_OUT0 FOR_OUT0 FOR_OUT0 FOR_OUT0 FOR_OUT0 FOR_OUT0 FOR_OUT0
Bits SW Access HW Access
Name
23
22
21
20
19
18
17
16
RW
RW
RW
RW
RW
RW
RW
RW
R
R
R
R
R
R
R
R
PLD0_PT7_ PLD0_PT6_ PLD0_PT5_ PLD0_PT4_ PLD0_PT3_ PLD0_PT2_ PLD0_PT1_ PLD0_PT0_
T_-
T_-
T_-
T_-
T_-
T_-
T_-
T_-
FOR_OUT1 FOR_OUT1 FOR_OUT1 FOR_OUT1 FOR_OUT1 FOR_OUT1 FOR_OUT1 FOR_OUT1
Bits SW Access HW Access
Name
31
30
29
28
27
26
25
24
RW
RW
RW
RW
RW
RW
RW
RW
R
R
R
R
R
R
R
R
PLD1_PT7_ PLD1_PT6_ PLD1_PT5_ PLD1_PT4_ PLD1_PT3_ PLD1_PT2_ PLD1_PT1_ PLD1_PT0_
T_-
T_-
T_-
T_-
T_-
T_-
T_-
T_-
FOR_OUT1 FOR_OUT1 FOR_OUT1 FOR_OUT1 FOR_OUT1 FOR_OUT1 FOR_OUT1 FOR_OUT1
Bits
Name
31
PLD1_PT7_T_-
FOR_OUT1
30
PLD1_PT6_T_-
FOR_OUT1
29
PLD1_PT5_T_-
FOR_OUT1
28
PLD1_PT4_T_-
FOR_OUT1
27
PLD1_PT3_T_-
FOR_OUT1
Description
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
877
UDB_UDBPAIR0_UDBSNG0_PLD_ORT0
18.1.19 UDB_UDBPAIR0_UDBSNG0_PLD_ORT0 (continued)
26
PLD1_PT2_T_-
FOR_OUT1
25
PLD1_PT1_T_-
FOR_OUT1
24
PLD1_PT0_T_-
FOR_OUT1
23
PLD0_PT7_T_-
FOR_OUT1
22
PLD0_PT6_T_-
FOR_OUT1
21
PLD0_PT5_T_-
FOR_OUT1
20
PLD0_PT4_T_-
FOR_OUT1
19
PLD0_PT3_T_-
FOR_OUT1
18
PLD0_PT2_T_-
FOR_OUT1
17
PLD0_PT1_T_-
FOR_OUT1
16
PLD0_PT0_T_-
FOR_OUT1
15
PLD1_PT7_T_-
FOR_OUT0
14
PLD1_PT6_T_-
FOR_OUT0
13
PLD1_PT5_T_-
FOR_OUT0
12
PLD1_PT4_T_-
FOR_OUT0
11
PLD1_PT3_T_-
FOR_OUT0
10
PLD1_PT2_T_-
FOR_OUT0
9
PLD1_PT1_T_-
FOR_OUT0
8
PLD1_PT0_T_-
FOR_OUT0
7
PLD0_PT7_T_-
FOR_OUT0
6
PLD0_PT6_T_-
FOR_OUT0
5
PLD0_PT5_T_-
FOR_OUT0
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
878
UDB_UDBPAIR0_UDBSNG0_PLD_ORT0
18.1.19 UDB_UDBPAIR0_UDBSNG0_PLD_ORT0 (continued)
4
PLD0_PT4_T_-
FOR_OUT0
3
PLD0_PT3_T_-
FOR_OUT0
2
PLD0_PT2_T_-
FOR_OUT0
1
PLD0_PT1_T_-
FOR_OUT0
0
PLD0_PT0_T_-
FOR_OUT0
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
879
UDB_UDBPAIR0_UDBSNG0_PLD_ORT1
18.1.20 UDB_UDBPAIR0_UDBSNG0_PLD_ORT1
Address = 0x40342034 PLD OR Terms Address: 0x40342034 Retention: Retained
Bits SW Access HW Access
Name
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RW
RW
R
R
R
R
R
R
R
R
PLD0_PT7_ PLD0_PT6_ PLD0_PT5_ PLD0_PT4_ PLD0_PT3_ PLD0_PT2_ PLD0_PT1_ PLD0_PT0_
T_-
T_-
T_-
T_-
T_-
T_-
T_-
T_-
FOR_OUT2 FOR_OUT2 FOR_OUT2 FOR_OUT2 FOR_OUT2 FOR_OUT2 FOR_OUT2 FOR_OUT2
Bits SW Access HW Access
Name
15
14
13
12
11
10
9
8
RW
RW
RW
RW
RW
RW
RW
RW
R
R
R
R
R
R
R
R
PLD1_PT7_ PLD1_PT6_ PLD1_PT5_ PLD1_PT4_ PLD1_PT3_ PLD1_PT2_ PLD1_PT1_ PLD1_PT0_
T_-
T_-
T_-
T_-
T_-
T_-
T_-
T_-
FOR_OUT2 FOR_OUT2 FOR_OUT2 FOR_OUT2 FOR_OUT2 FOR_OUT2 FOR_OUT2 FOR_OUT2
Bits SW Access HW Access
Name
23
22
21
20
19
18
17
16
RW
RW
RW
RW
RW
RW
RW
RW
R
R
R
R
R
R
R
R
PLD0_PT7_ PLD0_PT6_ PLD0_PT5_ PLD0_PT4_ PLD0_PT3_ PLD0_PT2_ PLD0_PT1_ PLD0_PT0_
T_-
T_-
T_-
T_-
T_-
T_-
T_-
T_-
FOR_OUT3 FOR_OUT3 FOR_OUT3 FOR_OUT3 FOR_OUT3 FOR_OUT3 FOR_OUT3 FOR_OUT3
Bits SW Access HW Access
Name
31
30
29
28
27
26
25
24
RW
RW
RW
RW
RW
RW
RW
RW
R
R
R
R
R
R
R
R
PLD1_PT7_ PLD1_PT6_ PLD1_PT5_ PLD1_PT4_ PLD1_PT3_ PLD1_PT2_ PLD1_PT1_ PLD1_PT0_
T_-
T_-
T_-
T_-
T_-
T_-
T_-
T_-
FOR_OUT3 FOR_OUT3 FOR_OUT3 FOR_OUT3 FOR_OUT3 FOR_OUT3 FOR_OUT3 FOR_OUT3
Bits
Name
31
PLD1_PT7_T_-
FOR_OUT3
30
PLD1_PT6_T_-
FOR_OUT3
29
PLD1_PT5_T_-
FOR_OUT3
28
PLD1_PT4_T_-
FOR_OUT3
27
PLD1_PT3_T_-
FOR_OUT3
Description
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
880
UDB_UDBPAIR0_UDBSNG0_PLD_ORT1
18.1.20 UDB_UDBPAIR0_UDBSNG0_PLD_ORT1 (continued)
26
PLD1_PT2_T_-
FOR_OUT3
25
PLD1_PT1_T_-
FOR_OUT3
24
PLD1_PT0_T_-
FOR_OUT3
23
PLD0_PT7_T_-
FOR_OUT3
22
PLD0_PT6_T_-
FOR_OUT3
21
PLD0_PT5_T_-
FOR_OUT3
20
PLD0_PT4_T_-
FOR_OUT3
19
PLD0_PT3_T_-
FOR_OUT3
18
PLD0_PT2_T_-
FOR_OUT3
17
PLD0_PT1_T_-
FOR_OUT3
16
PLD0_PT0_T_-
FOR_OUT3
15
PLD1_PT7_T_-
FOR_OUT2
14
PLD1_PT6_T_-
FOR_OUT2
13
PLD1_PT5_T_-
FOR_OUT2
12
PLD1_PT4_T_-
FOR_OUT2
11
PLD1_PT3_T_-
FOR_OUT2
10
PLD1_PT2_T_-
FOR_OUT2
9
PLD1_PT1_T_-
FOR_OUT2
8
PLD1_PT0_T_-
FOR_OUT2
7
PLD0_PT7_T_-
FOR_OUT2
6
PLD0_PT6_T_-
FOR_OUT2
5
PLD0_PT5_T_-
FOR_OUT2
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
881
UDB_UDBPAIR0_UDBSNG0_PLD_ORT1
18.1.20 UDB_UDBPAIR0_UDBSNG0_PLD_ORT1 (continued)
4
PLD0_PT4_T_-
FOR_OUT2
3
PLD0_PT3_T_-
FOR_OUT2
2
PLD0_PT2_T_-
FOR_OUT2
1
PLD0_PT1_T_-
FOR_OUT2
0
PLD0_PT0_T_-
FOR_OUT2
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
OR term Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
882
UDB_UDBPAIR0_UDBSNG0_PLD_CFG0
18.1.21 UDB_UDBPAIR0_UDBSNG0_PLD_CFG0
Address = 0x40342038 PLD configuration for Carry Enable, Constant, and XOR feedback Address: 0x40342038 Retention: Retained
Bits SW Access HW Access
Name
7
RW
R
PLD0_MC3 _DFF_C
6
RW
R
PLD0_MC3 _CEN
5
RW
R
PLD0_MC2 _DFF_C
4
RW
R
PLD0_MC2 _CEN
3
RW
R
PLD0_MC1 _DFF_C
2
RW
R
PLD0_MC1 _CEN
1
RW
R
PLD0_MC0 _DFF_C
0
RW
R
PLD0_MC0 _CEN
Bits SW Access HW Access
Name
15
RW
R
PLD1_MC3 _DFF_C
14
RW
R
PLD1_MC3 _CEN
13
RW
R
PLD1_MC2 _DFF_C
12
RW
R
PLD1_MC2 _CEN
11
RW
R
PLD1_MC1 _DFF_C
10
RW
R
PLD1_MC1 _CEN
9
RW
R
PLD1_MC0 _DFF_C
8
RW
R
PLD1_MC0 _CEN
Bits SW Access HW Access
Name
23
22
RW
R
PLD0_MC3_XORFB [23:22]
21
20
RW
R
PLD0_MC2_XORFB [21:20]
19
18
RW
R
PLD0_MC1_XORFB [19:18]
17
16
RW
R
PLD0_MC0_XORFB [17:16]
Bits SW Access HW Access
Name
31
30
RW
R
PLD1_MC3_XORFB [31:30]
29
28
RW
R
PLD1_MC2_XORFB [29:28]
27
26
RW
R
PLD1_MC1_XORFB [27:26]
25
24
RW
R
PLD1_MC0_XORFB [25:24]
Bits 31 : 30
Name PLD1_MC3_XORFB
29 : 28
PLD1_MC2_XORFB
Description
XOR feedback Default Value: X
0x0: DFF : DFF
0x1: CARRY : Carry
0x2: TFF_H : TFF on high
0x3: TFF_L : TFF on low
XOR feedback Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
883
UDB_UDBPAIR0_UDBSNG0_PLD_CFG0
18.1.21 UDB_UDBPAIR0_UDBSNG0_PLD_CFG0 (continued)
27 : 26
PLD1_MC1_XORFB
25 : 24
PLD1_MC0_XORFB
23 : 22
PLD0_MC3_XORFB
21 : 20
PLD0_MC2_XORFB
0x0: DFF : DFF
0x1: CARRY : Carry
0x2: TFF_H : TFF on high
0x3: TFF_L : TFF on low
XOR feedback Default Value: X
0x0: DFF : DFF
0x1: CARRY : Carry
0x2: TFF_H : TFF on high
0x3: TFF_L : TFF on low
XOR feedback Default Value: X
0x0: DFF : DFF
0x1: CARRY : Carry
0x2: TFF_H : TFF on high
0x3: TFF_L : TFF on low
XOR feedback Default Value: X
0x0: DFF : DFF
0x1: CARRY : Carry
0x2: TFF_H : TFF on high
0x3: TFF_L : TFF on low
XOR feedback Default Value: X
0x0: DFF : DFF
0x1: CARRY : Carry
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
884
UDB_UDBPAIR0_UDBSNG0_PLD_CFG0
18.1.21 UDB_UDBPAIR0_UDBSNG0_PLD_CFG0 (continued)
19 : 18
PLD0_MC1_XORFB
17 : 16
PLD0_MC0_XORFB
15
PLD1_MC3_DFF_C
14
PLD1_MC3_CEN
13
PLD1_MC2_DFF_C
12
PLD1_MC2_CEN
0x2: TFF_H : TFF on high
0x3: TFF_L : TFF on low
XOR feedback Default Value: X
0x0: DFF : DFF
0x1: CARRY : Carry
0x2: TFF_H : TFF on high
0x3: TFF_L : TFF on low
XOR feedback Default Value: X
0x0: DFF : DFF
0x1: CARRY : Carry
0x2: TFF_H : TFF on high
0x3: TFF_L : TFF on low
DFF Constant Default Value: X
0x0: NOINV : DFF non-inverted
0x1: INVERTED : DFF inverted
Carry enable Default Value: X
0x0: DISABLE : Disabled
0x1: ENABLE : Enabled
DFF Constant Default Value: X
0x0: NOINV : DFF non-inverted
0x1: INVERTED : DFF inverted
Carry enable Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
885
UDB_UDBPAIR0_UDBSNG0_PLD_CFG0
18.1.21 UDB_UDBPAIR0_UDBSNG0_PLD_CFG0 (continued)
0x0: DISABLE : Disabled
0x1: ENABLE : Enabled
11
PLD1_MC1_DFF_C
DFF Constant
Default Value: X
0x0: NOINV : DFF non-inverted
0x1: INVERTED : DFF inverted
10
PLD1_MC1_CEN
Carry enable Default Value: X
0x0: DISABLE : Disabled
0x1: ENABLE : Enabled
9
PLD1_MC0_DFF_C
DFF Constant
Default Value: X
0x0: NOINV : DFF non-inverted
0x1: INVERTED : DFF inverted
8
PLD1_MC0_CEN
Carry enable
Default Value: X
0x0: DISABLE : Disabled
0x1: ENABLE : Enabled
7
PLD0_MC3_DFF_C
DFF Constant
Default Value: X
0x0: NOINV : DFF non-inverted
0x1: INVERTED : DFF inverted
6
PLD0_MC3_CEN
Carry enable
Default Value: X
0x0: DISABLE : Disabled
0x1: ENABLE : Enabled
5
PLD0_MC2_DFF_C
DFF Constant
Default Value: X
0x0: NOINV : DFF non-inverted
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
886
UDB_UDBPAIR0_UDBSNG0_PLD_CFG0
18.1.21 UDB_UDBPAIR0_UDBSNG0_PLD_CFG0 (continued)
0x1: INVERTED : DFF inverted
4
PLD0_MC2_CEN
Carry enable
Default Value: X
0x0: DISABLE : Disabled
0x1: ENABLE : Enabled
3
PLD0_MC1_DFF_C
DFF Constant
Default Value: X
0x0: NOINV : DFF non-inverted
0x1: INVERTED : DFF inverted
2
PLD0_MC1_CEN
Carry enable
Default Value: X
0x0: DISABLE : Disabled
0x1: ENABLE : Enabled
1
PLD0_MC0_DFF_C
DFF Constant
Default Value: X
0x0: NOINV : DFF non-inverted
0x1: INVERTED : DFF inverted
0
PLD0_MC0_CEN
Carry enable
Default Value: X
0x0: DISABLE : Disabled
0x1: ENABLE : Enabled
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
887
UDB_UDBPAIR0_UDBSNG0_PLD_CFG1
18.1.22 UDB_UDBPAIR0_UDBSNG0_PLD_CFG1
Address = 0x4034203C PLD configuration for Set / Reset selection, and Bypass control Address: 0x4034203C Retention: Retained
Bits SW Access HW Access
Name
7
RW
R
PLD0_MC3 _RESET_-
SEL
6 RW R
PLD0_MC3 _SET_SEL
5
RW
R
PLD0_MC2 _RESET_-
SEL
4 RW R
PLD0_MC2 _SET_SEL
3
RW
R
PLD0_MC1 _RESET_-
SEL
2 RW R
PLD0_MC1 _SET_SEL
1
RW
R
PLD0_MC0 _RESET_-
SEL
0 RW R
PLD0_MC0 _SET_SEL
Bits SW Access HW Access
Name
15
RW
R
PLD1_MC3 _RESET_-
SEL
14 RW R
PLD1_MC3 _SET_SEL
13
RW
R
PLD1_MC2 _RESET_-
SEL
12 RW R
PLD1_MC2 _SET_SEL
11
RW
R
PLD1_MC1 _RESET_-
SEL
10 RW R
PLD1_MC1 _SET_SEL
9
RW
R
PLD1_MC0 _RESET_-
SEL
8 RW R
PLD1_MC0 _SET_SEL
Bits SW Access HW Access
Name
23 None None
None
22
RW
R
PLD0_MC3 _BYPASS
21 None None
None
20
RW
R
PLD0_MC2 _BYPASS
19 None None
None
18
RW
R
PLD0_MC1 _BYPASS
17 None None
None
16
RW
R
PLD0_MC0 _BYPASS
Bits SW Access HW Access
Name
31 None None
None
30
RW
R
PLD1_MC3 _BYPASS
29 None None
None
28
RW
R
PLD1_MC2 _BYPASS
27 None None
None
26
RW
R
PLD1_MC1 _BYPASS
25 None None
None
24
RW
R
PLD1_MC0 _BYPASS
Bits
Name
Description
30
PLD1_MC3_BYPASS
Bypass selection
Default Value: X
0x0: REGISTER : Registered output
0x1: COMBINATIONAL : Combinational output
28
PLD1_MC2_BYPASS
Bypass selection
Default Value: X
0x0: REGISTER : Registered output
0x1: COMBINATIONAL : Combinational output
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
888
UDB_UDBPAIR0_UDBSNG0_PLD_CFG1
18.1.22 UDB_UDBPAIR0_UDBSNG0_PLD_CFG1 (continued)
26
PLD1_MC1_BYPASS
Bypass selection
Default Value: X
0x0: REGISTER : Registered output
0x1: COMBINATIONAL : Combinational output
24
PLD1_MC0_BYPASS
Bypass selection
Default Value: X
0x0: REGISTER : Registered output
0x1: COMBINATIONAL : Combinational output
22
PLD0_MC3_BYPASS
Bypass selection
Default Value: X
0x0: REGISTER : Registered output
0x1: COMBINATIONAL : Combinational output
20
PLD0_MC2_BYPASS
Bypass selection
Default Value: X
0x0: REGISTER : Registered output
0x1: COMBINATIONAL : Combinational output
18
PLD0_MC1_BYPASS
Bypass selection
Default Value: X
0x0: REGISTER : Registered output
0x1: COMBINATIONAL : Combinational output
16
PLD0_MC0_BYPASS
Bypass selection
Default Value: X
0x0: REGISTER : Registered output
0x1: COMBINATIONAL : Combinational output
15
PLD1_MC3_RESET_SEL Reset select enable
Default Value: X
0x0: DISABLE : Reset not used
0x1: ENABLE : Reset enabled
14
PLD1_MC3_SET_SEL
Set select enable
Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
889
UDB_UDBPAIR0_UDBSNG0_PLD_CFG1
18.1.22 UDB_UDBPAIR0_UDBSNG0_PLD_CFG1 (continued)
0x0: DISABLE: Set not used
0x1: ENABLE : Set enabled
13
PLD1_MC2_RESET_SEL Reset select enable
Default Value: X
0x0: DISABLE : Reset not used
0x1: ENABLE : Reset enabled
12
PLD1_MC2_SET_SEL
Set select enable
Default Value: X
0x0: DISABLE : Set not used
0x1: ENABLE : Set enabled
11
PLD1_MC1_RESET_SEL Reset select enable
Default Value: X
0x0: DISABLE : Reset not used
0x1: ENABLE : Reset enabled
10
PLD1_MC1_SET_SEL
Set select enable
Default Value: X
0x0: DISABLE : Set not used
0x1: ENABLE : Set enabled
9
PLD1_MC0_RESET_SEL Reset select enable
Default Value: X
0x0: DISABLE : Reset not used
0x1: ENABLE : Reset enabled
8
PLD1_MC0_SET_SEL
Set select enable
Default Value: X
0x0: DISABLE : Set not used
0x1: ENABLE : Set enabled
7
PLD0_MC3_RESET_SEL Reset select enable
Default Value: X
0x0: DISABLE : Reset not used
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
890
UDB_UDBPAIR0_UDBSNG0_PLD_CFG1
18.1.22 UDB_UDBPAIR0_UDBSNG0_PLD_CFG1 (continued)
0x1: ENABLE : Reset enabled
6
PLD0_MC3_SET_SEL
Set select enable
Default Value: X
0x0: DISABLE : Set not used
0x1: ENABLE : Set enabled
5
PLD0_MC2_RESET_SEL Reset select enable
Default Value: X
0x0: DISABLE : Reset not used
0x1: ENABLE : Reset enabled
4
PLD0_MC2_SET_SEL
Set select enable
Default Value: X
0x0: DISABLE : Set not used
0x1: ENABLE : Set enabled
3
PLD0_MC1_RESET_SEL Reset select enable
Default Value: X
0x0: DISABLE : Reset not used
0x1: ENABLE : Reset enabled
2
PLD0_MC1_SET_SEL
Set select enable
Default Value: X
0x0: DISABLE : Set not used
0x1: ENABLE : Set enabled
1
PLD0_MC0_RESET_SEL Reset select enable
Default Value: X
0x0: DISABLE : Reset not used
0x1: ENABLE : Reset enabled
0
PLD0_MC0_SET_SEL
Set select enable
Default Value: X
0x0: DISABLE : Set not used
0x1: ENABLE : Set enabled
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
891
UDB_UDBPAIR0_UDBSNG0_DPATH_CFG0
18.1.23 UDB_UDBPAIR0_UDBSNG0_DPATH_CFG0
Address = 0x40342040 Datapath input selections (RAD0, RAD1, RAD2, F0_LD, F1_LD, D0_LD, D1_LD) Address: 0x40342040 Retention: Retained
Bits SW Access HW Access
Name
7 None None None
6
5
4
RW
R
RAD1 [6:4]
3 None None None
2
1
0
RW
R
RAD0 [2:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
RW
RW
RW
RW
RW
HW Access
R
R
R
R
R
R
Name
DP_RTE_B DP_RTE_B DP_RTE_B DP_RTE_B DP_RTE_B
YPASS4
YPASS3
YPASS2
YPASS1
YPASS0
RAD2 [10:8]
Bits SW Access HW Access
Name
23 None None
None
22
21
20
RW
R
F1_LD [22:20]
19
RW
R
DP_RTE_B YPASS5
18
17
16
RW
R
F0_LD [18:16]
Bits SW Access HW Access
Name
31 None None None
30
29
28
RW
R
D1_LD [30:28]
27 None None None
26
25
24
RW
R
D0_LD [26:24]
Bits 30 : 28
Name D1_LD
Description
Datapath Permutable Input Mux Default Value: 0
0x0: OFF : Input off
0x1: DP_IN0 : Set to dp_in[0]
0x2: DP_IN1 : Set to dp_in[1]
0x3: DP_IN2 : Set to dp_in[2]
0x4: DP_IN3 : Set to dp_in[3]
0x5: DP_IN4 : Set to dp_in[4]
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
892
UDB_UDBPAIR0_UDBSNG0_DPATH_CFG0
18.1.23 UDB_UDBPAIR0_UDBSNG0_DPATH_CFG0 (continued)
26 : 24
D0_LD
22 : 20
F1_LD
19
DP_RTE_BYPASS5
0x6: DP_IN5 : Set to dp_in[5]
0x7: RESERVED : Reserved
Datapath Permutable Input Mux Default Value: 0
0x0: OFF : Input off
0x1: DP_IN0 : Set to dp_in[0]
0x2: DP_IN1 : Set to dp_in[1]
0x3: DP_IN2 : Set to dp_in[2]
0x4: DP_IN3 : Set to dp_in[3]
0x5: DP_IN4 : Set to dp_in[4]
0x6: DP_IN5 : Set to dp_in[5]
0x7: RESERVED : Reserved
Datapath Permutable Input Mux Default Value: 0
0x0: OFF : Input off
0x1: DP_IN0 : Set to dp_in[0]
0x2: DP_IN1 : Set to dp_in[1]
0x3: DP_IN2 : Set to dp_in[2]
0x4: DP_IN3 : Set to dp_in[3]
0x5: DP_IN4 : Set to dp_in[4]
0x6: DP_IN5 : Set to dp_in[5]
0x7: RESERVED : Reserved
DP_In bypass control Default Value: 0
0x0: DP_IN5_ROUTE : Use dp_in[5]
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
893
UDB_UDBPAIR0_UDBSNG0_DPATH_CFG0
18.1.23 UDB_UDBPAIR0_UDBSNG0_DPATH_CFG0 (continued)
18 : 16
F0_LD
15
DP_RTE_BYPASS4
14
DP_RTE_BYPASS3
13
DP_RTE_BYPASS2
12
DP_RTE_BYPASS1
0x1: DP_IN5_BYPASS : Use dp_out[5] via bypass
Datapath Permutable Input Mux Default Value: 0
0x0: OFF : Input off
0x1: DP_IN0 : Set to dp_in[0]
0x2: DP_IN1 : Set to dp_in[1]
0x3: DP_IN2 : Set to dp_in[2]
0x4: DP_IN3 : Set to dp_in[3]
0x5: DP_IN4 : Set to dp_in[4]
0x6: DP_IN5 : Set to dp_in[5]
0x7: RESERVED : Reserved
DP_In bypass control Default Value: 0
0x0: DP_IN4_ROUTE : Use dp_in[4]
0x1: DP_IN4_BYPASS : Use dp_out[4] as input via bypass
DP_In bypass control Default Value: 0
0x0: DP_IN3_ROUTE : Use dp_in[3]
0x1: DP_IN3_BYPASS : Use dp_out[3] as input via bypass
DP_In bypass control Default Value: 0
0x0: DP_IN2_ROUTE : Use dp_in[2]
0x1: DP_IN2_BYPASS : Use dp_out[2] as input via bypass
DP_In bypass control Default Value: 0
0x0: DP_IN1_ROUTE : Use dp_in[1]
0x1: DP_IN1_BYPASS : Use dp_out[1] as input via bypass
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
894
UDB_UDBPAIR0_UDBSNG0_DPATH_CFG0
18.1.23 UDB_UDBPAIR0_UDBSNG0_DPATH_CFG0 (continued)
11
DP_RTE_BYPASS0
10 : 8
RAD2
6 : 4
RAD1
2 : 0
RAD0
DP_In bypass control Default Value: 0
0x0: DP_IN0_ROUTE : Use dp_in[0]
0x1: DP_IN0_BYPASS : Use dp_out[0] as input via bypass
Datapath Permutable Input Mux Default Value: 0
0x0: OFF : Input off
0x1: DP_IN0 : Set to dp_in[0]
0x2: DP_IN1 : Set to dp_in[1]
0x3: DP_IN2 : Set to dp_in[2]
0x4: DP_IN3 : Set to dp_in[3]
0x5: DP_IN4 : Set to dp_in[4]
0x6: DP_IN5 : Set to dp_in[5]
0x7: RESERVED : Reserved
Datapath Permutable Input Mux Default Value: 0
0x0: OFF : Input off
0x1: DP_IN0 : Set to dp_in[0]
0x2: DP_IN1 : Set to dp_in[1]
0x3: DP_IN2 : Set to dp_in[2]
0x4: DP_IN3 : Set to dp_in[3]
0x5: DP_IN4 : Set to dp_in[4]
0x6: DP_IN5 : Set to dp_in[5]
0x7: RESERVED : Reserved
Datapath Permutable Input Mux Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
895
UDB_UDBPAIR0_UDBSNG0_DPATH_CFG0
18.1.23
UDB_UDBPAIR0_UDBSNG0_DPATH_CFG0 (continued)
0x0: OFF : Input off
0x1: DP_IN0 : Set to dp_in[0]
0x2: DP_IN1 : Set to dp_in[1]
0x3: DP_IN2 : Set to dp_in[2]
0x4: DP_IN3 : Set to dp_in[3]
0x5: DP_IN4 : Set to dp_in[4]
0x6: DP_IN5 : Set to dp_in[5]
0x7: RESERVED : Reserved
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
896
UDB_UDBPAIR0_UDBSNG0_DPATH_CFG1
18.1.24 UDB_UDBPAIR0_UDBSNG0_DPATH_CFG1
Address = 0x40342044 Datapath input and output selections (SCI_MUX, SI_MUX, OUT0 thru OUT5) Address: 0x40342044 Retention: Retained
Bits SW Access HW Access
Name
7 None None None
6
5
4
RW
R
CI_MUX [6:4]
3 None None None
2
1
0
RW
R
SI_MUX [2:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
RW
HW Access
R
R
Name
OUT1 [15:12]
OUT0 [11:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
RW
HW Access
R
R
Name
OUT3 [23:20]
OUT2 [19:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
RW
HW Access
R
R
Name
OUT5 [31:28]
OUT4 [27:24]
Bits 31 : 28
Name OUT5
Description
Datapath Permutable Output Mux Default Value: 0
0x0: CE0 : Comparator 0 equal
0x1: CL0 : Comparator 0 less than
0x2: Z0 : Accumulator 0 zero detect
0x3: FF0 : Accumulator 0 ones detect
0x4: CE1 : Comparator 1 equal
0x5: CL1 : Comparator 1 less than
0x6: Z1 : Accumulator 1 zero detect
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
897
UDB_UDBPAIR0_UDBSNG0_DPATH_CFG1
27 : 24
OUT4
0x7: FF1 : Accumulator 1 ones detect
0x8: OV_MSB : Overflow of MSB
0x9: CO_MSB : Carry out of MSB
0xa: CMSBO : CRC MSB
0xb: SO : Shift out
0xc: F0_BLK_STAT : FIFO 0 block status defined by direction
0xd: F1_BLK_STAT : FIFO 1 block status defined by direction
0xe: F0_BUS_STAT : FIFO 0 bus status defined by direction and level
0xf: F1_BUS_STAT : FIFO 1 bus status defined by direction and level
Datapath Permutable Output Mux Default Value: 0
0x0: CE0 : Comparator 0 equal
0x1: CL0 : Comparator 0 less than
0x2: Z0 : Accumulator 0 zero detect
0x3: FF0 : Accumulator 0 ones detect
0x4: CE1 : Comparator 1 equal
0x5: CL1 : Comparator 1 less than
0x6: Z1 : Accumulator 1 zero detect
0x7: FF1 : Accumulator 1 ones detect
0x8: OV_MSB : Overflow of MSB
0x9: CO_MSB : Carry out of MSB
0xa: CMSBO : CRC MSB
0xb: SO : Shift out
0xc: F0_BLK_STAT : FIFO 0 block status defined by direction
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
898
UDB_UDBPAIR0_UDBSNG0_DPATH_CFG1
18.1.24 UDB_UDBPAIR0_UDBSNG0_DPATH_CFG1 (continued)
23 : 20
OUT3
19 : 16
OUT2
0xd: F1_BLK_STAT : FIFO 1 block status defined by direction
0xe: F0_BUS_STAT : FIFO 0 bus status defined by direction and level
0xf: F1_BUS_STAT : FIFO 1 bus status defined by direction and level
Datapath Permutable Output Mux Default Value: 0
0x0: CE0 : Comparator 0 equal
0x1: CL0 : Comparator 0 less than
0x2: Z0 : Accumulator 0 zero detect
0x3: FF0 : Accumulator 0 ones detect
0x4: CE1 : Comparator 1 equal
0x5: CL1 : Comparator 1 less than
0x6: Z1 : Accumulator 1 zero detect
0x7: FF1 : Accumulator 1 ones detect
0x8: OV_MSB : Overflow of MSB
0x9: CO_MSB : Carry out of MSB
0xa: CMSBO : CRC MSB
0xb: SO : Shift out
0xc: F0_BLK_STAT : FIFO 0 block status defined by direction
0xd: F1_BLK_STAT : FIFO 1 block status defined by direction
0xe: F0_BUS_STAT : FIFO 0 bus status defined by direction and level
0xf: F1_BUS_STAT : FIFO 1 bus status defined by direction and level
Datapath Permutable Output Mux Default Value: 0
0x0: CE0 : Comparator 0 equal
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
899
UDB_UDBPAIR0_UDBSNG0_DPATH_CFG1
18.1.24 UDB_UDBPAIR0_UDBSNG0_DPATH_CFG1 (continued)
15 : 12
OUT1
0x1: CL0 : Comparator 0 less than
0x2: Z0 : Accumulator 0 zero detect
0x3: FF0 : Accumulator 0 ones detect
0x4: CE1 : Comparator 1 equal
0x5: CL1 : Comparator 1 less than
0x6: Z1 : Accumulator 1 zero detect
0x7: FF1 : Accumulator 1 ones detect
0x8: OV_MSB : Overflow of MSB
0x9: CO_MSB : Carry out of MSB
0xa: CMSBO : CRC MSB
0xb: SO : Shift out
0xc: F0_BLK_STAT : FIFO 0 block status defined by direction
0xd: F1_BLK_STAT : FIFO 1 block status defined by direction
0xe: F0_BUS_STAT : FIFO 0 bus status defined by direction and level
0xf: F1_BUS_STAT : FIFO 1 bus status defined by direction and level
Datapath Permutable Output Mux Default Value: 0
0x0: CE0 : Comparator 0 equal
0x1: CL0 : Comparator 0 less than
0x2: Z0 : Accumulator 0 zero detect
0x3: FF0 : Accumulator 0 ones detect
0x4: CE1 : Comparator 1 equal
0x5: CL1 : Comparator 1 less than
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
900
UDB_UDBPAIR0_UDBSNG0_DPATH_CFG1
18.1.24 UDB_UDBPAIR0_UDBSNG0_DPATH_CFG1 (continued)
11 : 8
OUT0
0x6: Z1 : Accumulator 1 zero detect
0x7: FF1 : Accumulator 1 ones detect
0x8: OV_MSB : Overflow of MSB
0x9: CO_MSB : Carry out of MSB
0xa: CMSBO : CRC MSB
0xb: SO : Shift out
0xc: F0_BLK_STAT : FIFO 0 block status defined by direction
0xd: F1_BLK_STAT : FIFO 1 block status defined by direction
0xe: F0_BUS_STAT : FIFO 0 bus status defined by direction and level
0xf: F1_BUS_STAT : FIFO 1 bus status defined by direction and level
Datapath Permutable Output Mux Default Value: 0
0x0: CE0 : Comparator 0 equal
0x1: CL0 : Comparator 0 less than
0x2: Z0 : Accumulator 0 zero detect
0x3: FF0 : Accumulator 0 ones detect
0x4: CE1 : Comparator 1 equal
0x5: CL1 : Comparator 1 less than
0x6: Z1 : Accumulator 1 zero detect
0x7: FF1 : Accumulator 1 ones detect
0x8: OV_MSB : Overflow of MSB
0x9: CO_MSB : Carry out of MSB
0xa: CMSBO : CRC MSB
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
901
UDB_UDBPAIR0_UDBSNG0_DPATH_CFG1
18.1.24 UDB_UDBPAIR0_UDBSNG0_DPATH_CFG1 (continued)
6 : 4
CI_MUX
2 : 0
SI_MUX
0xb: SO : Shift out
0xc: F0_BLK_STAT : FIFO 0 block status defined by direction
0xd: F1_BLK_STAT : FIFO 1 block status defined by direction
0xe: F0_BUS_STAT : FIFO 0 bus status defined by direction and level
0xf: F1_BUS_STAT : FIFO 1 bus status defined by direction and level
Datapath Permutable Input Mux Default Value: 0
0x0: OFF : Input off
0x1: DP_IN0 : Set to dp_in[0]
0x2: DP_IN1 : Set to dp_in[1]
0x3: DP_IN2 : Set to dp_in[2]
0x4: DP_IN3 : Set to dp_in[3]
0x5: DP_IN4 : Set to dp_in[4]
0x6: DP_IN5 : Set to dp_in[5]
0x7: RESERVED : Reserved
Datapath Permutable Input Mux Default Value: 0
0x0: OFF : Input off
0x1: DP_IN0 : Set to dp_in[0]
0x2: DP_IN1 : Set to dp_in[1]
0x3: DP_IN2 : Set to dp_in[2]
0x4: DP_IN3 : Set to dp_in[3]
0x5: DP_IN4 : Set to dp_in[4]
0x6: DP_IN5 : Set to dp_in[5]
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
902
UDB_UDBPAIR0_UDBSNG0_DPATH_CFG1
18.1.24
UDB_UDBPAIR0_UDBSNG0_DPATH_CFG1 (continued)
0x7: RESERVED : Reserved
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
903
UDB_UDBPAIR0_UDBSNG0_DPATH_CFG2
18.1.25 UDB_UDBPAIR0_UDBSNG0_DPATH_CFG2
Address = 0x40342048 Datapath output synchronization, ALU mask, compare 0 and 1 masks Address: 0x40342048 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:6]
OUT_SYNC [5:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
AMASK [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
CMASK0 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
CMASK1 [31:24]
Bits 31 : 24
Name CMASK1
23 : 16
CMASK0
15 : 8
AMASK
5 : 0
OUT_SYNC
Description
Datapath Compare 1 Mask. The mask value in this register is applied to the Accumulator 0 vs Accumulator 1 mux output before it is used for Compare 1 (it does not apply to the Accumulator 0 vs. Data 1 mux output). The CMASK1_EN bit (DPATH_CFG3) must be set for the mask to be operational. Default Value: 0
Datapath Compare 0 Mask. The mask value in this register is applied to the output of the Accumulator 0 before it is used for comparison in Compare block 0. The CMASK0_EN bit (DPATH_CFG3) must be set for the mask to be operational. Default Value: 0
Datapath ALU Mask. The mask value in this register is applied to the output of the Datapath ALU result before the result is stored. The AMASK_EN bit (DPATH_CFG3) must be set for the mask to be operational. Default Value: 0
Datapath Output Synchronization. Each datapath output can be registered (default,0), or combinational (1) Default Value: 0
0x0: REGISTERED : registered
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
904
UDB_UDBPAIR0_UDBSNG0_DPATH_CFG2
18.1.25
UDB_UDBPAIR0_UDBSNG0_DPATH_CFG2 (continued)
0x1: COMBINATIONAL : combinational
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
905
UDB_UDBPAIR0_UDBSNG0_DPATH_CFG3
18.1.26 UDB_UDBPAIR0_UDBSNG0_DPATH_CFG3
Address = 0x4034204C Datapath mask enables, shift in, carry in, compare, chaining, MSB configs; FIFO, shift and parallel input control Address: 0x4034204C Retention: Retained
Bits SW Access HW Access
Name
7
6
5
RW
RW
RW
R
R
R
CMASK1_E N
CMASK0_E N
AMASK_EN
4 RW R
DEF_SI
3
2
RW
R
SI_SELB [3:2]
1
0
RW
R
SI_SELA [1:0]
Bits SW Access HW Access
Name
15
14
RW
R
CMP_SELB [15:14]
13
12
RW
R
CMP_SELA [13:12]
11
10
RW
R
CI_SELB [11:10]
9
8
RW
R
CI_SELA [9:8]
Bits SW Access HW Access
Name
23 RW R
MSB_EN
22
21
20
RW
R
MSB_SEL [22:20]
19
RW
R
CHAIN_CM SB
18 RW R
CHAIN_FB
17 RW R
CHAIN1
16 RW R
CHAIN0
Bits SW Access HW Access
Name
31 RW R PI_SEL
30 RW R SHIFT_SEL
29 RW R PI_DYN
28 RW R MSB_SI
27
26
RW
R
F1_INSEL [27:26]
25
24
RW
R
F0_INSEL [25:24]
Bits
Name
31
PI_SEL
30
SHIFT_SEL
29
PI_DYN
Description
Datapath parallel input selection Default Value: 0
0x0: NORMAL : Normal operation, ALU source is from accumulator selection
0x1: PARALLEL : ALU source A input is from the parallel data input
Datapath shift out selection Default Value: 0
0x0: SOL_MSB : Routed shift out is shift out left (sol_msb)
0x1: SOR : Routed shift out is shift out right (sor)
Enable for dynamic control of parallel data input (PI) mux. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
906
UDB_UDBPAIR0_UDBSNG0_DPATH_CFG3
18.1.26 UDB_UDBPAIR0_UDBSNG0_DPATH_CFG3 (continued)
28
MSB_SI
27 : 26
F1_INSEL
0x0: DISABLE : Parallel input mux select is only controlled by static configuration (PI_SEL).
0x1: ENABLE : Parallel input mux to the Datapath is controlled by CFB_EN field in Datapath Dynamic RAM. When this mode is enabled, the CFB_EN usage for CRC/PRS functionality is disabled.
Arithmetic shift right operation shift in selection Default Value: 0
0x0: DEFAULT : Shift in default value (when SI_SELA and/or SI_SELB == 0)
0x1: MSB : Override default and shift in MSB value
Datapath FIFO Configuration Default Value: 0
0x0: INPUT : Input Mode: Write source is the system bus; read destination is corresponding data register or accumulator
0x1: OUTPUT_A0 : Output Mode: Write source is A0, read destination is the system bus
25 : 24
F0_INSEL
23
MSB_EN
22 : 20
MSB_SEL
0x2: OUTPUT_A1 :
Output Mode: Write source is A1, read destination is the system bus
0x3: OUTPUT_ALU : Output Mode: Write source is the ALU output, read destination is the system bus
Datapath FIFO Configuration Default Value: 0
0x0: INPUT : Input Mode: Write source is the system bus; read destination is corresponding data register or accumulator
0x1: OUTPUT_A0 : Output Mode: Write source is A0, read destination is the system bus
0x2: OUTPUT_A1 : Output Mode: Write source is A1, read destination is the system bus
0x3: OUTPUT_ALU : Output Mode: Write source is the ALU output, read destination is the system bus
Datapath MSB selection enable Default Value: 0
0x0: DISABLE : MSB selection is disabled, MSB is bit 7
0x1: ENABLE : MSB selection is controlled by MSB_SEL
Datapath MSB Selection Default Value: 0
0x0: BIT0 : MSB is bit 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
907
UDB_UDBPAIR0_UDBSNG0_DPATH_CFG3
18.1.26 UDB_UDBPAIR0_UDBSNG0_DPATH_CFG3 (continued)
19
CHAIN_CMSB
18
CHAIN_FB
17
CHAIN1
16
CHAIN0
15 : 14
CMP_SELB
0x1: BIT1 : MSB is bit 1
0x2: BIT2 : MSB is bit 2
0x3: BIT3 : MSB is bit 3
0x4: BIT4 : MSB is bit 4
0x5: BIT5 : MSB is bit 5
0x6: BIT6 : MSB is bit 6
0x7: BIT7 : MSB is bit 7 - equivalent to MSB_EN=0
Datapath CRC MSB chaining enable Default Value: 0
0x0: DISABLE : CRC MSB is not chained
0x1: ENABLE : CRC MSB is chained from the next (MSB) datapath
Datapath CRC feedback chaining enable Default Value: 0
0x0: DISABLE : CRC feedback is not chained
0x1: ENABLE : CRC feedback is chained from the previous (LSB) datapath
Datapath condition chaining enable Default Value: 0
0x0: DISABLE : Conditions are not chained
0x1: ENABLE : Conditions are chained from the previous (LSB) datapath
Datapath condition chaining enable Default Value: 0
0x0: DISABLE : Conditions are not chained
0x1: ENABLE : Conditions are chained from the previous (LSB) datapath
Datapath compare select Default Value: 0
0x0: A1_D1 : Compare A1 to D1
0x1: A1_A0 : Compare A1 to A0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
908
UDB_UDBPAIR0_UDBSNG0_DPATH_CFG3
18.1.26 UDB_UDBPAIR0_UDBSNG0_DPATH_CFG3 (continued)
13 : 12
CMP_SELA
11 : 10
CI_SELB
9 : 8
CI_SELA
7
CMASK1_EN
6
CMASK0_EN
0x2: A0_D1 : Compare A0 to D1
0x3: A0_A0 : Compare A0 to A0
Datapath compare select Default Value: 0
0x0: A1_D1 : Compare A1 to D1
0x1: A1_A0 : Compare A1 to A0
0x2: A0_D1 : Compare A0 to D1
0x3: A0_A0 : Compare A0 to A0
Datapath carry in source select Default Value: 0
0x0: DEFAULT : Default arithmetic mode
0x1: REGISTERED : Carry in is the carry out registered from previous cycle
0x2: ROUTE : Carry in is selected from datapath routing input
0x3: CHAIN : Carry in is chained from the previous datapath
Datapath carry in source select Default Value: 0
0x0: DEFAULT : Default arithmetic mode
0x1: REGISTERED : Carry in is the carry out registered from previous cycle
0x2: ROUTE : Carry in is selected from datapath routing input
0x3: CHAIN : Carry in is chained from the previous datapath
Datapath mask enable Default Value: 0
0x0: DISABLE : Masking disabled
0x1: ENABLE : Masking enabled
Datapath mask enable Default Value: 0
0x0: DISABLE : Masking disabled
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
909
UDB_UDBPAIR0_UDBSNG0_DPATH_CFG3
18.1.26 UDB_UDBPAIR0_UDBSNG0_DPATH_CFG3 (continued)
5
AMASK_EN
4
DEF_SI
3 : 2
SI_SELB
1 : 0
SI_SELA
0x1: ENABLE : Masking enabled
Datapath mask enable Default Value: 0
0x0: DISABLE : Masking disabled
0x1: ENABLE : Masking enabled
Datapath default shift value Default Value: 0
0x0: DEFAULT_0 : Default shift is 0
0x1: DEFAULT_1 : Default shift is 1
Datapath shift in source select Default Value: 0
0x0: DEFAULT : Default value specified in default shift field
0x1: REGISTERED : Shift in is the shift out registered from previous cycle
0x2: ROUTE : Shift in is selected from datapath routing input
0x3: CHAIN : Shift in is chained from the previous datapath
Datapath shift in source select Default Value: 0
0x0: DEFAULT : Default value specified in default shift field
0x1: REGISTERED : Shift in is the shift out registered from previous cycle
0x2: ROUTE : Shift in is selected from datapath routing input
0x3: CHAIN : Shift in is chained from the previous datapath
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
910
UDB_UDBPAIR0_UDBSNG0_DPATH_CFG4
18.1.27 UDB_UDBPAIR0_UDBSNG0_DPATH_CFG4
Address = 0x40342050 Datapath FIFO and register access configuration control Address: 0x40342050 Retention: Retained
Bits SW Access HW Access
Name
7
6
5
4
RW
RW
RW
RW
R
R
R
R
F1_CK_INV F0_CK_INV FIFO_FAST FIFO_CAP
3
RW
R
FIFO_EDGE
2
1
RW
RW
R
R
FI-
EX-
FO_ASYNC T_CRCPRS
0 None None
None
Bits SW Access HW Access
Name
15
14
13
None
None
None [15:13]
12
RW
R
FIFO_ADD_SYNC
11
10
None
None
None [11:10]
9 RW R
F1_DYN
8 RW R
F0_DYN
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
12
FIFO_ADD_SYNC
9
F1_DYN
Description
Adds a flop stage to FIFO block status if additional timing margin is needed Default Value: 0
0x0: DISABLE : No flop stage is added to the block status calculation
0x1: ENABLE : 1 flop stage is added to the block status calculation
Default Value: 0
0x0: STATIC : Default. FIFO direction is static and controlled by the associated Fx_INSEL bits (DPATH_CFG3).
0x1: DYNAMIC : The associated FIFO direction is dynamically controlled by the associated 'dx_load' Datapath input signal. When the 'dx_load' signal is '0', the access is internal, where the FIFO is both a source and destination for the Datapath. When the 'dx_load' signal is '1', the access is extenal, where the FIFO is both a source and destination for AHB.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
911
UDB_UDBPAIR0_UDBSNG0_DPATH_CFG4
18.1.27 UDB_UDBPAIR0_UDBSNG0_DPATH_CFG4 (continued)
8
F0_DYN
7
F1_CK_INV
6
F0_CK_INV
5
FIFO_FAST
4
FIFO_CAP
3
FIFO_EDGE
When this bit is set, the associated FIFO configuration may be dynamically controlled. Default Value: 0
0x0: STATIC : Default. FIFO direction is static and controlled by the associated Fx_INSEL bits (DPATH_CFG3).
0x1: DYNAMIC : The associated FIFO direction is dynamically controlled by the associated 'dx_load' Datapath input signal. When the 'dx_load' signal is '0', the access is internal, where the FIFO is both a source and destination for the Datapath. When the 'dx_load' signal is '1', the access is extenal, where the FIFO is both a source and destination for AHB.
FIFO Clock Invert. When this bit is set, the polarity of the clock for the given FIFO will be inverted, with respect to the polarity of the selected Datapath clock. Default Value: 0
0x0: NORMAL : FIFO clock is the same polarity as the Datapath clock.
0x1: INVERT : FIFO clock is inverted with respect to the Datapath clock.
FIFO Clock Invert. When this bit is set, the polarity of the clock for the given FIFO will be inverted, with respect to the polarity of the selected Datapath clock. Default Value: 0
0x0: NORMAL : FIFO clock is the same polarity as the Datapath clock.
0x1: INVERT : FIFO clock is inverted with respect to the Datapath clock.
FIFO Fast Mode. When this bit is set, the FIFO write logic is clocked by the application bus clock. Lowers the latency of capture timing, at the expense of additional power. Default Value: 0
0x0: DISABLE : FIFO is clocked with selected Datapath clock.
0x1: ENABLE : FIFO is clocked with application bus clock. Master and quadrant bus clock gating must be enabled.
FIFO Software Capture Mode. When this bit is set, a read of A0 or A1 triggers a capture into F0 or F1 respectively. This function follows the chaining configuration. All accumulators in the chain from a given block to the MS block in the chain are capture Default Value: 0
0x0: DISABLE : FIFO capture is disabled.
0x1: ENABLE : FIFO capture is enabled (FIFO must be in output mode). A read of A0 or A1 will write into F0 or F1.
Edge/level sensitive FIFO write control (Fx_LD). Only applies to FIFO configured in output mode Default Value: 0
0x0: LEVEL : FIFO write from accumulators/ALU is level sensitive. FIFO write occurs on a clock edge whenever the write control is sampled high on that edge.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
912
UDB_UDBPAIR0_UDBSNG0_DPATH_CFG4
18.1.27 UDB_UDBPAIR0_UDBSNG0_DPATH_CFG4 (continued)
2
FIFO_ASYNC
1
EXT_CRCPRS
0x1: EDGE : FIFO write from accumulators/ALU is edge sensitive. FIFO write occurs on a clock edge following a 0 to 1 transition on the write control. The write control must be negated for at least one full cycle of the FIFO clock for a subsequent transition to be deleted.
Asynchronous FIFO clocking support Default Value: 0
0x0: DISABLE : FIFO clocks are synchronous
0x1: ENABLE : FIFO clocks are asynchronous
External CRC/PRS mode Default Value: 0
0x0: INTERNAL : Internal CRC/PRS routing
0x1: EXTERNAL : External CRC/PRS routing
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
913
UDB_UDBPAIR0_UDBSNG0_SC_CFG0
18.1.28 UDB_UDBPAIR0_UDBSNG0_SC_CFG0
Address = 0x40342054 SC Mode 0 and 1 control registers; status register input mode; general SC configuration Address: 0x40342054 Retention: Retained
Bits
7
6
5
4
3
2
SW Access
RW
HW Access
R
Name
CTL_MD0 [7:0]
Bits
15
14
13
12
11
10
SW Access
RW
HW Access
R
Name
CTL_MD1 [15:8]
Bits
23
22
21
20
19
18
SW Access
RW
HW Access
R
Name
STAT_MD [23:16]
Bits SW Access HW Access
Name
31
30
29
None
None
None [31:29]
28
RW
R
SC_EXT_RES
27
RW
R
SC_SYNC_MD
26
RW
R
SC_INT_M D
1
0
9
8
17
16
25
24
RW
R
SC_OUT_CTL [25:24]
Bits
Name
28
SC_EXT_RES
27
SC_SYNC_MD
Description
Control register external reset operation. This bit supports autonomous usage of the control register, where a routed reset should clear the writable input registers. By default this is off because the CPU writable register can be cleared in firmware. Default Value: 0
0x0: DISABLED : When a routed reset is applied to the control register, only embedded state (sampling registers) are cleared
0x1: ENABLED : When a routed reset is applied to the control register, all state is cleared, including the CPU writable control bits.
SC Sync Mode - controls when the status register operates as a 4-bit double synchronizer module Default Value: 0
0x0: NORMAL : Normal Mode - Status register operation
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
914
UDB_UDBPAIR0_UDBSNG0_SC_CFG0
18.1.28 UDB_UDBPAIR0_UDBSNG0_SC_CFG0 (continued)
26
SC_INT_MD
25 : 24
SC_OUT_CTL
23 : 16
STAT_MD
15 : 8
CTL_MD1
7 : 0
CTL_MD0
0x1: SYNC_MODE : Sync Mode - Routing inputs sc_in[3:0] are the 4 sync inputs, and connections sc_io[3:0] operate as the sync outputs
SC Interrupt Mode - controls when the UDB driving an interrupt generated from the masked OR reduction of status bits 6 to 0 Default Value: 0
0x0: NORMAL : Normal Mode - Routing connection sc_io[3] is a normal input to the status register
0x1: INT_MODE : Interrupt Mode - Routing connection sc_io[3] operates as the UDB interrupt output
Selects the output source for the Status and Control routing connections Default Value: 0
0x0: CONTROL : Control out, 8-bits of control are driven to the routing connections
0x1: PARALLEL : Datapath parallel output, 8-bits of datapath parallel output data are driven to the routing connections
0x2: COUNTER : Counter out, 7-bits of count and 1 bit (MSB) of terminal count are driven to the routing connections
0x3: RESERVED : Reserved
Mode selection for each bit of the status register. A '0' is transparent mode, where internal routing is read indrectly by CPU firmware. A '1' is sticky-clear-on-read mode, where once the given bit is set, it will stay set until the CPU reads the bit. Default Value: 0
CTL_MD1 and CTL_MD0 are concatenated to form an encoding for the mode of each control bit in the control register. Default Value: 0
0x0: DIRECT : The value written to that bit drives directly into the routing.
0x1: SYNC : The value written is resampled by the selected SC clock. The resampled value is driven into the routing.
0x2: DOUBLE_SYNC : The value written is doubly synced by the selected SC clock. The synched value is driven into the routing.
0x3: PULSE : The value written is resampled and a synchronous pulse is generated and driven into the routing based on the selected SC clock. At the end of the generated pulse, the control register bit is automatically reset.
CTL_MD1 and CTL_MD0 are concatenated to form an encoding for the mode of each control bit in the control register. Default Value: 0
0x0: DIRECT : The value written to that bit drives directly into the routing.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
915
UDB_UDBPAIR0_UDBSNG0_SC_CFG0
18.1.28
UDB_UDBPAIR0_UDBSNG0_SC_CFG0 (continued)
0x1: SYNC : The value written is resampled by the selected SC clock. The resampled value is driven into the routing.
0x2: DOUBLE_SYNC : The value written is doubly synced by the selected SC clock. The synched value is driven into the routing.
0x3: PULSE : The value written is resampled and a synchronous pulse is generated and driven into the routing based on the selected SC clock. At the end of the generated pulse, the control register bit is automatically reset.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
916
UDB_UDBPAIR0_UDBSNG0_SC_CFG1
18.1.29 UDB_UDBPAIR0_UDBSNG0_SC_CFG1
Address = 0x40342058 SC counter control Address: 0x40342058 Retention: Retained
Bits SW Access HW Access
Name
7 None None None
6 RW R ALT_CNT
5
4
RW
RW
R
R
ROUTE_EN ROUTE_LD
3
2
RW
R
CNT_EN_SEL [3:2]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
1
0
RW
R
CNT_LD_SEL [1:0]
9
8
17
16
25
24
Bits
Name
6
ALT_CNT
5
ROUTE_EN
4
ROUTE_LD
Description
Configure the alternate operating mode of the counter Default Value: 0
0x0: DEFAULT_MODE : Default counter operating mode
0x1: ALT_MODE : Alternate counter operating mode
Configure the counter enable signal for routing input Default Value: 0
0x0: DISABLE : Routed EN signal is not used. EN signal is only controlled by firmware CNT START (ACTL register)
0x1: ROUTED : Routed EN signal is used, CNT START must be set
Configure the counter load signal for routing input Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
917
UDB_UDBPAIR0_UDBSNG0_SC_CFG1
18.1.29 UDB_UDBPAIR0_UDBSNG0_SC_CFG1 (continued)
3 : 2
CNT_EN_SEL
1 : 0
CNT_LD_SEL
0x0: DISABLE : Routed LD signal is not used
0x1: ROUTED : Routed LD signal is used
Selects the routing inputs for the counter enable signal Default Value: 0
0x0: SC_IN4 : sc_io_in[0]
0x1: SC_IN5 : sc_io_in[1]
0x2: SC_IN6 : sc_io_in[2]
0x3: SC_IO : sc_io_in[3]
Selects the routing inputs for the counter load signal Default Value: 0
0x0: SC_IN0 : sc_in[0]
0x1: SC_IN1 : sc_in[1]
0x2: SC_IN2 : sc_in[2]
0x3: SC_IN3 : sc_in[3]
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
918
UDB_UDBPAIR0_UDBSNG0_RC_CFG0
18.1.30 UDB_UDBPAIR0_UDBSNG0_RC_CFG0
Address = 0x4034205C PLD0, PLD1, Datatpath, and SC clock and reset control Address: 0x4034205C Retention: Retained
Bits SW Access HW Access
Name
7 RW R
PLD0_RC_ RES_SEL1
6
RW
R
PLD0_RC_ RES_-
SEL0_OR_FRES
5 RW R
PLD0_RC_INV
4 RW R
PLD0_RC_ EN_INV
3
2
RW
R
PLD0_RC_EN_MODE [3:2]
Bits SW Access HW Access
Name
15 None None
None
14
RW
R
PLD1_RC_ RES_-
SEL0_OR_FRES
13 RW R
PLD1_RC_INV
12 RW R
PLD1_RC_ EN_INV
11
10
RW
R
PLD1_RC_EN_MODE [11:10]
Bits SW Access HW Access
Name
23
22
RW
RW
R
R
DP_RC_RE S_SEL1
DP_RC_RE S_-
SEL0_OR_FRES
21 RW R
DP_RC_INV
20 RW R
DP_RC_EN _INV
19
18
RW
R
DP_RC_EN_MODE [19:18]
Bits SW Access HW Access
Name
31
30
RW
RW
R
R
SC_RC_RE S_SEL1
SC_RC_RE S_-
SEL0_OR_FRES
29 RW R
SC_RC_INV
28 RW R
SC_RC_EN _INV
27
26
RW
R
SC_RC_EN_MODE [27:26]
1
0
RW
R
PLD0_RC_EN_SEL [1:0]
9
8
RW
R
PLD1_RC_EN_SEL [9:8]
17
16
RW
R
DP_RC_EN_SEL [17:16]
25
24
RW
R
SC_RC_EN_SEL [25:24]
Bits
Name
Description
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
919
UDB_UDBPAIR0_UDBSNG0_RC_CFG0
18.1.30 UDB_UDBPAIR0_UDBSNG0_RC_CFG0 (continued)
31
SC_RC_RES_SEL1
30
SC_RC_RES_-
SEL0_OR_FRES
29
SC_RC_INV
28
SC_RC_EN_INV
27 : 26
SC_RC_EN_MODE
25 : 24
SC_RC_EN_SEL
Configures the routed reset for the associated UDB component block. The meaning of this bit depends on the value of ALT RES (RC_CFG1). When ALT RES = '0' - This bit is not used. When ALT RES = '1' - The bits {RC_SEL1,RC_SEL0_OR_FRES} select the RC routing for routed reset control according to the following: 00 : rc_in [0] 01 : rc_in [1] 10 : rc_in [2] 11 : rc_in [3] Default Value: 0
Configures the routed or firmware reset for the associated UDB component block. The meaning of this bit depends on the value of ALT RES (RC_CFG1). When ALT RES = '0' - This bit is a firmware reset. When ALT RES = '1' - The bits {RC_SEL1,RC_SEL0_OR_FRES} select the RC routing for routed reset control according to the following: 00 : rc_in [0] 01 : rc_in [1] 10 : rc_in [2] 11 : rc_in [3] Default Value: 0
Optionally inverts the clock selection for the associated UDB component block. Default Value: 0
0x0: NOINV : Non-inverted
0x1: INVERT : Inverted
Optionally inverts the clock enable selection for the associated UDB component blocks. Default Value: 0
0x0: NOINV : Non-inverted
0x1: INVERT : Inverted
Selects the operating mode for the clock to the associated UDB component block. Default Value: 0
0x0: OFF : Always off
0x1: ON : Always on
0x2: POSEDGE : Positive edge
0x3: LEVEL : Level sensitive
Selects channel route for enable control to the associated UDB component block Default Value: 0
0x0: RC_IN0 : rc_in[0]
0x1: RC_IN1 : rc_in[1]
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
920
UDB_UDBPAIR0_UDBSNG0_RC_CFG0
18.1.30 UDB_UDBPAIR0_UDBSNG0_RC_CFG0 (continued)
23
DP_RC_RES_SEL1
22
DP_RC_RES_-
SEL0_OR_FRES
21
DP_RC_INV
20
DP_RC_EN_INV
19 : 18
DP_RC_EN_MODE
17 : 16
DP_RC_EN_SEL
0x2: RC_IN2 : rc_in[2]
0x3: RC_IN3 : rc_in[3]
Configures the routed reset for the associated UDB component block. The meaning of this bit depends on the value of ALT RES (RC_CFG1). When ALT RES = '0' - This bit is not used. When ALT RES = '1' - The bits {RC_SEL1,RC_SEL0_OR_FRES} select the RC routing for routed reset control according to the following: 00 : rc_in [0] 01 : rc_in [1] 10 : rc_in [2] 11 : rc_in [3] Default Value: 0
Configures the routed or firmware reset for the associated UDB component block. The meaning of this bit depends on the value of ALT RES (RC_CFG1). When ALT RES = '0' - This bit is a firmware reset. When ALT RES = '1' - The bits {RC_SEL1,RC_SEL0_OR_FRES} select the RC routing for routed reset control according to the following: 00 : rc_in [0] 01 : rc_in [1] 10 : rc_in [2] 11 : rc_in [3] Default Value: 0
Optionally inverts the clock selection for the associated UDB component block. Default Value: 0
0x0: NOINV : Non-inverted
0x1: INVERT : Inverted
Optionally inverts the clock enable selection for the associated UDB component blocks. Default Value: 0
0x0: NOINV : Non-inverted
0x1: INVERT : Inverted
Selects the operating mode for the clock to the associated UDB component block. Default Value: 0
0x0: OFF : Always off
0x1: ON : Always on
0x2: POSEDGE : Positive edge
0x3: LEVEL : Level sensitive
Selects channel route for enable control to the associated UDB component block Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
921
UDB_UDBPAIR0_UDBSNG0_RC_CFG0
18.1.30 UDB_UDBPAIR0_UDBSNG0_RC_CFG0 (continued)
14
PLD1_RC_RES_-
SEL0_OR_FRES
13
PLD1_RC_INV
12
PLD1_RC_EN_INV
11 : 10
PLD1_RC_EN_MODE
9 : 8
PLD1_RC_EN_SEL
0x0: RC_IN0 : rc_in[0]
0x1: RC_IN1 : rc_in[1]
0x2: RC_IN2 : rc_in[2]
0x3: RC_IN3 : rc_in[3]
Configures the routed or firmware reset for the associated UDB component block. The meaning of this bit depends on the value of ALT RES (RC_CFG1). When ALT RES = '0' - This bit is a firmware reset. When ALT RES = '1' - The bits {RC_SEL1,RC_SEL0_OR_FRES} select the RC routing for routed reset control according to the following: 00 : rc_in [0] 01 : rc_in [1] 10 : rc_in [2] 11 : rc_in [3] Default Value: 0
Optionally inverts the clock selection for the associated UDB component block. Default Value: 0
0x0: NOINV : Non-inverted
0x1: INVERT : Inverted
Optionally inverts the clock enable selection for the associated UDB component blocks. Default Value: 0
0x0: NOINV : Non-inverted
0x1: INVERT : Inverted
Selects the operating mode for the clock to the associated UDB component block. Default Value: 0
0x0: OFF : Always off
0x1: ON : Always on
0x2: POSEDGE : Positive edge
0x3: LEVEL : Level sensitive
Selects channel route for enable control to the associated UDB component block Default Value: 0
0x0: RC_IN0 : rc_in[0]
0x1: RC_IN1 : rc_in[1]
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
922
UDB_UDBPAIR0_UDBSNG0_RC_CFG0
18.1.30 UDB_UDBPAIR0_UDBSNG0_RC_CFG0 (continued)
0x2: RC_IN2 : rc_in[2]
0x3: RC_IN3 : rc_in[3]
7
PLD0_RC_RES_SEL1
Configures the routed reset for the associated UDB component block. The meaning of this bit
depends on the value of ALT RES (RC_CFG1).
When ALT RES = '0' - This bit is not used.
When ALT RES = '1' - The bits {RC_SEL1,RC_SEL0_OR_FRES} select the RC routing for rout-
ed reset control according to the following:
00 : rc_in [0]
01 : rc_in [1]
10 : rc_in [2]
11 : rc_in [3]
Default Value: 0
6
PLD0_RC_RES_-
Configures the routed or firmware reset for the associated UDB component block. The meaning
SEL0_OR_FRES
of this bit depends on the value of ALT RES (RC_CFG1).
When ALT RES = '0' - This bit is a firmware reset.
When ALT RES = '1' - The bits {RC_SEL1,RC_SEL0_OR_FRES} select the RC routing for rout-
ed reset control according to the following:
00 : rc_in [0]
01 : rc_in [1]
10 : rc_in [2]
11 : rc_in [3]
Default Value: 0
5
PLD0_RC_INV
Optionally inverts the clock selection for the associated UDB component block. Default Value: 0
0x0: NOINV : Non-inverted
0x1: INVERT : Inverted
4
PLD0_RC_EN_INV
Optionally inverts the clock enable selection for the associated UDB component blocks.
Default Value: 0
0x0: NOINV : Non-inverted
0x1: INVERT : Inverted
3 : 2
PLD0_RC_EN_MODE
Selects the operating mode for the clock to the associated UDB component block.
Default Value: 0
0x0: OFF : Always off
0x1: ON : Always on
0x2: POSEDGE : Positive edge
0x3: LEVEL : Level sensitive
1 : 0
PLD0_RC_EN_SEL
Selects channel route for enable control to the associated UDB component block
Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
923
UDB_UDBPAIR0_UDBSNG0_RC_CFG0
18.1.30
UDB_UDBPAIR0_UDBSNG0_RC_CFG0 (continued)
0x0: RC_IN0 : rc_in[0]
0x1: RC_IN1 : rc_in[1]
0x2: RC_IN2 : rc_in[2]
0x3: RC_IN3 : rc_in[3]
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
924
UDB_UDBPAIR0_UDBSNG0_RC_CFG1
18.1.31 UDB_UDBPAIR0_UDBSNG0_RC_CFG1
Address = 0x40342060 PLD0, PLD1, Datatpath, and SC clock selection, general reset control Address: 0x40342060 Retention: Retained
Bits
7
6
5
4
SW Access
RW
HW Access
R
Name
PLD1_CK_SEL [7:4]
3
2
1
0
RW
R
PLD0_CK_SEL [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
RW
HW Access
R
R
Name
SC_CK_SEL [15:12]
DP_CK_SEL [11:8]
Bits SW Access HW Access
Name
23
22
RW
RW
R
R
SC_RES_P DP_RES_P
OL
OL
21
20
None
None
None [21:20]
19
RW
R
EN_RES_C NTCTL
18 RW R
RES_POL
17
16
RW
R
RES_SEL [17:16]
Bits SW Access HW Access
Name
31 None None
None
30
RW
R
PLD0_RES _POL
29
28
RW
R
EXT_CK_SEL [29:28]
27
26
25
RW
RW
RW
R
R
R
EN_RES_D P
EN_RES_S TAT
EXT_SYNC
24 RW R
ALT_RES
Bits
Name
30
PLD0_RES_POL
29 : 28
EXT_CK_SEL
Description
The meaning of this bit depends on the value of ALT RES. When ALT RES is '1', this bit controls the polarity of the selected PLD0 routed reset. NOTE: There is only one routed reset available to both PLDs in the UDB. When ALT RES is '1', PLD0 RES SEL controls the polarity of the routed reset for both PLDs. Therefore a "PLD1_RES_POL" bit does not exist. Default Value: 0
0x0: NOINV : Routed reset to the PLD0/PLD1 block is true polarity.
0x1: INVERT : Routed reset to the PLD0/PLD1 block is inverted polarity.
External clock selection Default Value: 0
0x0: RC_IN0 : rc_in[0]
0x1: RC_IN1 : rc_in[1]
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
925
UDB_UDBPAIR0_UDBSNG0_RC_CFG1
18.1.31 UDB_UDBPAIR0_UDBSNG0_RC_CFG1 (continued)
27
EN_RES_DP
26
EN_RES_STAT
25
EXT_SYNC
24
ALT_RES
23
SC_RES_POL
22
DP_RES_POL
0x2: RC_IN2 : rc_in[2]
0x3: RC_IN3 : rc_in[3]
Only valid when ALT RES is '1'. This bit gates the routed reset to the Datapath block. Default Value: 0
0x0: DISABLE : Routed reset to the Datapath block is gated off.
0x1: ENABLE : Routed reset to the Datapath block is on. ALT RES must be '1' and routed reset must be selected in RC_CFG0 (DP_RC_RES_SEL1, DP_RC_RES_SEL0_OR_FRES)
Only valid when ALT RES is '1'. This bit gates the routed reset to the status register. Default Value: 0
0x0: NEGATED : Status register routed reset is gated off
0x1: ASSERTED : Status register routed reset is on
Enable synchronization of selected external clock Default Value: 0
0x0: DISABLE : Selected external clock input is not synchronized
0x1: ENABLE : Selected external clock input is synchronized
This bit toggles between two reset configurations. When this bit is '0', one routed reset is shared by all components in this UDB (compatible mode). When this bit is a 1, each block can select a unique routed reset from the available RC inputs. Default Value: 0
0x0: COMPATIBLE : All UDB blocks share a common routed reset.
0x1: ALTERNATE : Each UDB component block can select and control its individual routed reset.
Only valid when ALT RES is '1'. This bit controls the polarity of the selected SC routed reset. Default Value: 0
0x0: NOINV : Routed reset to the Status and Control block is true polarity.
0x1: INVERT : Routed reset to the Status and Control block is inverted polarity.
Only valid when ALT RES is '1'. This bit controls the polarity of the selected Datapath routed reset. Default Value: 0
0x0: NOINV : Routed reset to the Datapath block is true polarity.
0x1: INVERT : Routed reset to the Datapath block is inverted polarity.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
926
UDB_UDBPAIR0_UDBSNG0_RC_CFG1
18.1.31 UDB_UDBPAIR0_UDBSNG0_RC_CFG1 (continued)
19
EN_RES_CNTCTL
18
RES_POL
17 : 16
RES_SEL
15 : 12
SC_CK_SEL
This bit gates the routed reset to the counter/control register. By default, the operation is compatible, i.e., it only applies to the counter. However, if the updated control regisiter modes are used (sync mode, pulse mode, or the ext res bit) then the routed reset applies to the control register also. Default Value: 0
0x0: DISABLE : Routed reset is not applied to counter/control register
0x1: ENABLE : Routed reset is applied to the counter/control register
The meaning of this bit depends on the value of the ALT RES bit. When ALT RES is '0' (compatible mode), this bit sets the polarity of the routed reset. When ALT RES is '1', this bit is unused. Default Value: 0
0x0: NEGATED : Polarity of the routed reset is true.
0x1: ASSERTED : Polarity of the routed reset is inverted.
The meaning of this bit depends on the value of ALT RES. When ALT RES is '0' (compatible mode), this 2 bit field selects the RC routing input for the compatible reset scheme. When the ALT RES bit is '1', these bits are not used. Default Value: 0
0x0: RC_IN0 : rc_in[0]
0x1: RC_IN1 : rc_in[1]
0x2: RC_IN2 : rc_in[2]
0x3: RC_IN3 : rc_in[3]
Clock selection registers Default Value: 0
0x0: GCLK0 : gclk[0]
0x1: GCLK1 : gclk[1]
0x2: GCLK2 : gclk[2]
0x3: GCLK3 : gclk[3]
0x4: GCLK4 : gclk[4]
0x5: GCLK5 : gclk[5]
0x6: GCLK6 : gclk[6]
0x7: GCLK7 : gclk[7]
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
927
UDB_UDBPAIR0_UDBSNG0_RC_CFG1
18.1.31 UDB_UDBPAIR0_UDBSNG0_RC_CFG1 (continued)
11 : 8
DP_CK_SEL
7 : 4
PLD1_CK_SEL
0x8: CLK_EXT : clk_ext
0x9: CLK_PERI_APP : clk_peri_app
Clock selection registers Default Value: 0
0x0: GCLK0 : gclk[0]
0x1: GCLK1 : gclk[1]
0x2: GCLK2 : gclk[2]
0x3: GCLK3 : gclk[3]
0x4: GCLK4 : gclk[4]
0x5: GCLK5 : gclk[5]
0x6: GCLK6 : gclk[6]
0x7: GCLK7 : gclk[7]
0x8: CLK_EXT : clk_ext
0x9: CLK_PERI_APP : clk_peri_app
Clock selection registers Default Value: 0
0x0: GCLK0 : gclk[0]
0x1: GCLK1 : gclk[1]
0x2: GCLK2 : gclk[2]
0x3: GCLK3 : gclk[3]
0x4: GCLK4 : gclk[4]
0x5: GCLK5 : gclk[5]
0x6: GCLK6 : gclk[6]
0x7: GCLK7 : gclk[7]
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
928
UDB_UDBPAIR0_UDBSNG0_RC_CFG1
18.1.31 UDB_UDBPAIR0_UDBSNG0_RC_CFG1 (continued)
3 : 0
PLD0_CK_SEL
0x8: CLK_EXT : clk_ext
0x9: CLK_PERI_APP : clk_peri_app
Clock selection registers Default Value: 0
0x0: GCLK0 : gclk[0]
0x1: GCLK1 : gclk[1]
0x2: GCLK2 : gclk[2]
0x3: GCLK3 : gclk[3]
0x4: GCLK4 : gclk[4]
0x5: GCLK5 : gclk[5]
0x6: GCLK6 : gclk[6]
0x7: GCLK7 : gclk[7]
0x8: CLK_EXT : clk_ext
0x9: CLK_PERI_APP : clk_peri_app
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
929
UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0
18.1.32 UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0
Address = 0x40342064 Datapath opcode configuration Address: 0x40342064 Retention: Retained
Bits SW Access HW Access
Name
7
6
RW
R
OPC0_A0_WR_SRC [7:6]
5
4
RW
R
OPC0_A1_WR_SRC [5:4]
3
RW
R
OPC0_CFB_EN
2
RW
R
OPC0_CI_SEL
1
RW
R
OPC0_SI_SEL
0
RW
R
OPC0_CMP_SEL
Bits SW Access HW Access
Name
15
14
13
RW
R
OPC0_FUNC [15:13]
12
RW
R
OPC0_SRC_A
11
10
RW
R
OPC0_SRC_B [11:10]
9
8
RW
R
OPC0_SHIFT [9:8]
Bits SW Access HW Access
Name
23
22
RW
R
OPC1_A0_WR_SRC [23:22]
21
20
RW
R
OPC1_A1_WR_SRC [21:20]
19
RW
R
OPC1_CFB_EN
18
RW
R
OPC1_CI_SEL
17
RW
R
OPC1_SI_SEL
16
RW
R
OPC1_CMP_SEL
Bits SW Access HW Access
Name
31
30
29
RW
R
OPC1_FUNC [31:29]
28
RW
R
OPC1_SRC_A
27
26
RW
R
OPC1_SRC_B [27:26]
25
24
RW
R
OPC1_SHIFT [25:24]
Bits 31 : 29
Name OPC1_FUNC
Description
Dynamic ALU function selection Default Value: X
0x0: PASS : Pass
0x1: INC_A : Increment source A
0x2: DEC_A : Decrement source A
0x3: ADD : Add
0x4: SUB : Subtract
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
930
UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0
18.1.32 UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 (continued)
28
OPC1_SRC_A
27 : 26
OPC1_SRC_B
25 : 24
OPC1_SHIFT
23 : 22
OPC1_A0_WR_SRC
21 : 20
OPC1_A1_WR_SRC
0x5: XOR : Bitwise XOR
0x6: AND : Bitwise AND
0x7: OR : Bitwise OR
Dynamic ALU source A selection Default Value: X
0x0: A0 : ALU source A is A0
0x1: A1 : ALU source A is A1
Dynamic ALU source B selection Default Value: X
0x0: D0 : ALU source B is D0
0x1: D1 : ALU source B is D1
0x2: A0 : ALU source B is A0
0x3: A1 : ALU source B is A1
Dynamic shift selection Default Value: X
0x0: NOSHIFT : No shift
0x1: LEFT : Left Shift
0x2: RIGHT : Right Shift
0x3: SWAP : Nibble swap
Dynamic A0 write source selection Default Value: X
0x0: NOWRITE : no value written to A0
0x1: ALU : ALU output written to A0
0x2: D0 : D0 value written to A0
0x3: F0 : F0 value written to A0
Dynamic A1 write source selection Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
931
UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0
18.1.32 UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 (continued)
19
OPC1_CFB_EN
18
OPC1_CI_SEL
17
OPC1_SI_SEL
16
OPC1_CMP_SEL
15 : 13
OPC0_FUNC
0x0: NOWRITE : no value written to A1
0x1: ALU : ALU output written to A1
0x2: D1 : D1 value written to A1
0x3: F1 : F1 value written to A1
Dynamic CRC feedback selection Default Value: X
0x0: DISABLE : CRC feedback disabled
0x1: ENABLE : CRC feedback enabled
Dynamic carry in selection Default Value: X
0x0: CFG_A : Configuration A
0x1: CFG_B : Configuration B
Dynamic shift in selection Default Value: X
0x0: CFG_A : Configuration A
0x1: CFG_B : Configuration B
Dynamic compare selection Default Value: X
0x0: CFG_A : Configuration A
0x1: CFG_B : Configuration B
Dynamic ALU function selection Default Value: X
0x0: PASS : Pass
0x1: INC_A : Increment source A
0x2: DEC_A : Decrement source A
0x3: ADD : Add
0x4: SUB : Subtract
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
932
UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0
18.1.32 UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 (continued)
12
OPC0_SRC_A
11 : 10
OPC0_SRC_B
9 : 8
OPC0_SHIFT
7 : 6
OPC0_A0_WR_SRC
5 : 4
OPC0_A1_WR_SRC
0x5: XOR : Bitwise XOR
0x6: AND : Bitwise AND
0x7: OR : Bitwise OR
Dynamic ALU source A selection Default Value: X
0x0: A0 : ALU source A is A0
0x1: A1 : ALU source A is A1
Dynamic ALU source B selection Default Value: X
0x0: D0 : ALU source B is D0
0x1: D1 : ALU source B is D1
0x2: A0 : ALU source B is A0
0x3: A1 : ALU source B is A1
Dynamic shift selection Default Value: X
0x0: NOSHIFT : No shift
0x1: LEFT : Left Shift
0x2: RIGHT : Right Shift
0x3: SWAP : Nibble swap
Dynamic A0 write source selection Default Value: X
0x0: NOWRITE : no value written to A0
0x1: ALU : ALU output written to A0
0x2: D0 : D0 value written to A0
0x3: F0 : F0 value written to A0
Dynamic A1 write source selection Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
933
UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0
18.1.32 UDB_UDBPAIR0_UDBSNG0_DPATH_OPC0 (continued)
0x0: NOWRITE : no value written to A1
0x1: ALU : ALU output written to A1
0x2: D1 : D1 value written to A1
0x3: F1 : F1 value written to A1
3
OPC0_CFB_EN
Dynamic CRC feedback selection Default Value: X
0x0: DISABLE : CRC feedback disabled
0x1: ENABLE : CRC feedback enabled
2
OPC0_CI_SEL
Dynamic carry in selection Default Value: X
0x0: CFG_A : Configuration A
0x1: CFG_B : Configuration B
1
OPC0_SI_SEL
Dynamic shift in selection Default Value: X
0x0: CFG_A : Configuration A
0x1: CFG_B : Configuration B
0
OPC0_CMP_SEL
Dynamic compare selection
Default Value: X
0x0: CFG_A : Configuration A
0x1: CFG_B : Configuration B
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
934
UDB_UDBPAIR0_ROUTE_TOP_V_BOT
18.1.33 UDB_UDBPAIR0_ROUTE_TOP_V_BOT
Address = 0x40342100 Top Vertical Input (TVI) vs Bottom Vertical Input (BVI) muxing Address: 0x40342100 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
TOP_V_BOT [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
TOP_V_BOT [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
TOP_V_BOT [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
TOP_V_BOT [31:24]
Bits 31 : 0
Name TOP_V_BOT
Description Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
935
UDB_UDBPAIR0_ROUTE_LVO1_V_2
18.1.34 UDB_UDBPAIR0_ROUTE_LVO1_V_2
Address = 0x40342104 Left Vertical Ouput (LVO) 1 vs 2 muxing for certain horizontals Address: 0x40342104 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
LVO1_V_2 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
LVO1_V_2 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
LVO1_V_2 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
LVO1_V_2 [31:24]
Bits 31 : 0
Name LVO1_V_2
Description Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
936
UDB_UDBPAIR0_ROUTE_RVO1_V_2
18.1.35 UDB_UDBPAIR0_ROUTE_RVO1_V_2
Address = 0x40342108 Right Vertical Ouput (RVO) 1 vs 2 muxing for certain horizontals Address: 0x40342108 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
RVO1_V_2 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
RVO1_V_2 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
RVO1_V_2 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
RVO1_V_2 [31:24]
Bits 31 : 0
Name RVO1_V_2
Description Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
937
UDB_UDBPAIR0_ROUTE_TUI_CFG0
18.1.36 UDB_UDBPAIR0_ROUTE_TUI_CFG0
Address = 0x4034210C Top UDB Input (TUI) selection Address: 0x4034210C Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
RW
HW Access
R
R
Name
TUI1SEL [7:4]
TUI0SEL [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
RW
HW Access
R
R
Name
TUI3SEL [15:12]
TUI2SEL [11:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
RW
HW Access
R
R
Name
TUI5SEL [23:20]
TUI4SEL [19:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
RW
HW Access
R
R
Name
TUI7SEL [31:28]
TUI6SEL [27:24]
Bits 31 : 28 27 : 24 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
Name TUI7SEL TUI6SEL TUI5SEL TUI4SEL TUI3SEL TUI2SEL TUI1SEL TUI0SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
938
UDB_UDBPAIR0_ROUTE_TUI_CFG1
18.1.37 UDB_UDBPAIR0_ROUTE_TUI_CFG1
Address = 0x40342110 Top UDB Input (TUI) selection Address: 0x40342110 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
RW
HW Access
R
R
Name
TUI9SEL [7:4]
TUI8SEL [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
RW
HW Access
R
R
Name
TUI11SEL [15:12]
TUI10SEL [11:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
RW
HW Access
R
R
Name
TUI13SEL [23:20]
TUI12SEL [19:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
RW
HW Access
R
R
Name
TUI15SEL [31:28]
TUI14SEL [27:24]
Bits 31 : 28 27 : 24 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
Name TUI15SEL TUI14SEL TUI13SEL TUI12SEL TUI11SEL TUI10SEL TUI9SEL TUI8SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
939
UDB_UDBPAIR0_ROUTE_TUI_CFG2
18.1.38 UDB_UDBPAIR0_ROUTE_TUI_CFG2
Address = 0x40342114 Top UDB Input (TUI) selection Address: 0x40342114 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
RW
HW Access
R
R
Name
TUI17SEL [7:4]
TUI16SEL [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
RW
HW Access
R
R
Name
TUI19SEL [15:12]
TUI18SEL [11:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
RW
HW Access
R
R
Name
TUI21SEL [23:20]
TUI20SEL [19:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
RW
HW Access
R
R
Name
TUI23SEL [31:28]
TUI22SEL [27:24]
Bits 31 : 28 27 : 24 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
Name TUI23SEL TUI22SEL TUI21SEL TUI20SEL TUI19SEL TUI18SEL TUI17SEL TUI16SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
940
UDB_UDBPAIR0_ROUTE_TUI_CFG3
18.1.39 UDB_UDBPAIR0_ROUTE_TUI_CFG3
Address = 0x40342118 Top UDB Input (TUI) selection Address: 0x40342118 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
RW
HW Access
R
R
Name
TUI25SEL [7:4]
TUI24SEL [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
RW
HW Access
R
R
Name
TUI27SEL [15:12]
TUI26SEL [11:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
RW
HW Access
R
R
Name
TUI29SEL [23:20]
TUI28SEL [19:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
RW
HW Access
R
R
Name
TUI31SEL [31:28]
TUI30SEL [27:24]
Bits 31 : 28 27 : 24 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
Name TUI31SEL TUI30SEL TUI29SEL TUI28SEL TUI27SEL TUI26SEL TUI25SEL TUI24SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
941
UDB_UDBPAIR0_ROUTE_TUI_CFG4
18.1.40 UDB_UDBPAIR0_ROUTE_TUI_CFG4
Address = 0x4034211C Top UDB Input (TUI) selection Address: 0x4034211C Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
RW
HW Access
R
R
Name
TUI33SEL [7:4]
TUI32SEL [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
RW
HW Access
R
R
Name
TUI35SEL [15:12]
TUI34SEL [11:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
RW
HW Access
R
R
Name
TUI37SEL [23:20]
TUI36SEL [19:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
RW
HW Access
R
R
Name
TUI39SEL [31:28]
TUI38SEL [27:24]
Bits 31 : 28 27 : 24 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
Name TUI39SEL TUI38SEL TUI37SEL TUI36SEL TUI35SEL TUI34SEL TUI33SEL TUI32SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
942
UDB_UDBPAIR0_ROUTE_TUI_CFG5
18.1.41 UDB_UDBPAIR0_ROUTE_TUI_CFG5
Address = 0x40342120 Top UDB Input (TUI) selection Address: 0x40342120 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
RW
HW Access
R
R
Name
TUI41SEL [7:4]
TUI40SEL [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 4 3 : 0
Name TUI41SEL TUI40SEL
Description Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
943
UDB_UDBPAIR0_ROUTE_BUI_CFG0
18.1.42 UDB_UDBPAIR0_ROUTE_BUI_CFG0
Address = 0x40342124 Bottom UDB Input (BUI) selection Address: 0x40342124 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
RW
HW Access
R
R
Name
BUI1SEL [7:4]
BUI0SEL [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
RW
HW Access
R
R
Name
BUI3SEL [15:12]
BUI2SEL [11:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
RW
HW Access
R
R
Name
BUI5SEL [23:20]
BUI4SEL [19:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
RW
HW Access
R
R
Name
BUI7SEL [31:28]
BUI6SEL [27:24]
Bits 31 : 28 27 : 24 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
Name BUI7SEL BUI6SEL BUI5SEL BUI4SEL BUI3SEL BUI2SEL BUI1SEL BUI0SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
944
UDB_UDBPAIR0_ROUTE_BUI_CFG1
18.1.43 UDB_UDBPAIR0_ROUTE_BUI_CFG1
Address = 0x40342128 Bottom UDB Input (BUI) selection Address: 0x40342128 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
RW
HW Access
R
R
Name
BUI9SEL [7:4]
BUI8SEL [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
RW
HW Access
R
R
Name
BUI11SEL [15:12]
BUI10SEL [11:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
RW
HW Access
R
R
Name
BUI13SEL [23:20]
BUI12SEL [19:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
RW
HW Access
R
R
Name
BUI15SEL [31:28]
BUI14SEL [27:24]
Bits 31 : 28 27 : 24 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
Name BUI15SEL BUI14SEL BUI13SEL BUI12SEL BUI11SEL BUI10SEL BUI9SEL BUI8SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
945
UDB_UDBPAIR0_ROUTE_BUI_CFG2
18.1.44 UDB_UDBPAIR0_ROUTE_BUI_CFG2
Address = 0x4034212C Bottom UDB Input (BUI) selection Address: 0x4034212C Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
RW
HW Access
R
R
Name
BUI17SEL [7:4]
BUI16SEL [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
RW
HW Access
R
R
Name
BUI19SEL [15:12]
BUI18SEL [11:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
RW
HW Access
R
R
Name
BUI21SEL [23:20]
BUI20SEL [19:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
RW
HW Access
R
R
Name
BUI23SEL [31:28]
BUI22SEL [27:24]
Bits 31 : 28 27 : 24 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
Name BUI23SEL BUI22SEL BUI21SEL BUI20SEL BUI19SEL BUI18SEL BUI17SEL BUI16SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
946
UDB_UDBPAIR0_ROUTE_BUI_CFG3
18.1.45 UDB_UDBPAIR0_ROUTE_BUI_CFG3
Address = 0x40342130 Bottom UDB Input (BUI) selection Address: 0x40342130 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
RW
HW Access
R
R
Name
BUI25SEL [7:4]
BUI24SEL [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
RW
HW Access
R
R
Name
BUI27SEL [15:12]
BUI26SEL [11:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
RW
HW Access
R
R
Name
BUI29SEL [23:20]
BUI28SEL [19:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
RW
HW Access
R
R
Name
BUI31SEL [31:28]
BUI30SEL [27:24]
Bits 31 : 28 27 : 24 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
Name BUI31SEL BUI30SEL BUI29SEL BUI28SEL BUI27SEL BUI26SEL BUI25SEL BUI24SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
947
UDB_UDBPAIR0_ROUTE_BUI_CFG4
18.1.46 UDB_UDBPAIR0_ROUTE_BUI_CFG4
Address = 0x40342134 Bottom UDB Input (BUI) selection Address: 0x40342134 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
RW
HW Access
R
R
Name
BUI33SEL [7:4]
BUI32SEL [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
RW
HW Access
R
R
Name
BUI35SEL [15:12]
BUI34SEL [11:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
RW
HW Access
R
R
Name
BUI37SEL [23:20]
BUI36SEL [19:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
RW
HW Access
R
R
Name
BUI39SEL [31:28]
BUI38SEL [27:24]
Bits 31 : 28 27 : 24 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
Name BUI39SEL BUI38SEL BUI37SEL BUI36SEL BUI35SEL BUI34SEL BUI33SEL BUI32SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
948
UDB_UDBPAIR0_ROUTE_BUI_CFG5
18.1.47 UDB_UDBPAIR0_ROUTE_BUI_CFG5
Address = 0x40342138 Bottom UDB Input (BUI) selection Address: 0x40342138 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
RW
HW Access
R
R
Name
BUI41SEL [7:4]
BUI40SEL [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 4 3 : 0
Name BUI41SEL BUI40SEL
Description Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
949
UDB_UDBPAIR0_ROUTE_RVO_CFG0
18.1.48 UDB_UDBPAIR0_ROUTE_RVO_CFG0
Address = 0x4034213C Right Vertical Ouput (RVO) selection Address: 0x4034213C Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:5]
RVO0SEL [4:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
RW
HW Access
None
R
Name
None [15:13]
RVO1SEL [12:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
HW Access
None
R
Name
None [23:21]
RVO2SEL [20:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
RW
HW Access
None
R
Name
None [31:29]
RVO3SEL [28:24]
Bits 28 : 24 20 : 16 12 : 8 4 : 0
Name RVO3SEL RVO2SEL RVO1SEL RVO0SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
950
UDB_UDBPAIR0_ROUTE_RVO_CFG1
18.1.49 UDB_UDBPAIR0_ROUTE_RVO_CFG1
Address = 0x40342140 Right Vertical Ouput (RVO) selection Address: 0x40342140 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:5]
RVO4SEL [4:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
RW
HW Access
None
R
Name
None [15:13]
RVO5SEL [12:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
HW Access
None
R
Name
None [23:21]
RVO6SEL [20:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
RW
HW Access
None
R
Name
None [31:29]
RVO7SEL [28:24]
Bits 28 : 24 20 : 16 12 : 8 4 : 0
Name RVO7SEL RVO6SEL RVO5SEL RVO4SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
951
UDB_UDBPAIR0_ROUTE_RVO_CFG2
18.1.50 UDB_UDBPAIR0_ROUTE_RVO_CFG2
Address = 0x40342144 Right Vertical Ouput (RVO) selection Address: 0x40342144 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:5]
RVO8SEL [4:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
RW
HW Access
None
R
Name
None [15:13]
RVO9SEL [12:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
HW Access
None
R
Name
None [23:21]
RVO10SEL [20:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
RW
HW Access
None
R
Name
None [31:29]
RVO11SEL [28:24]
Bits 28 : 24 20 : 16 12 : 8 4 : 0
Name RVO11SEL RVO10SEL RVO9SEL RVO8SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
952
UDB_UDBPAIR0_ROUTE_RVO_CFG3
18.1.51 UDB_UDBPAIR0_ROUTE_RVO_CFG3
Address = 0x40342148 Right Vertical Ouput (RVO) selection Address: 0x40342148 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:5]
RVO12SEL [4:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
RW
HW Access
None
R
Name
None [15:13]
RVO13SEL [12:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
HW Access
None
R
Name
None [23:21]
RVO14SEL [20:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
RW
HW Access
None
R
Name
None [31:29]
RVO15SEL [28:24]
Bits 28 : 24 20 : 16 12 : 8 4 : 0
Name RVO15SEL RVO14SEL RVO13SEL RVO12SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
953
UDB_UDBPAIR0_ROUTE_LVO_CFG0
18.1.52 UDB_UDBPAIR0_ROUTE_LVO_CFG0
Address = 0x4034214C Left Vertical Ouput (LVO) selection Address: 0x4034214C Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
RW
HW Access
R
R
Name
LVO1SEL [7:4]
LVO0SEL [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
RW
HW Access
R
R
Name
LVO3SEL [15:12]
LVO2SEL [11:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
RW
HW Access
R
R
Name
LVO5SEL [23:20]
LVO4SEL [19:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
RW
HW Access
R
R
Name
LVO7SEL [31:28]
LVO6SEL [27:24]
Bits 31 : 28 27 : 24 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
Name LVO7SEL LVO6SEL LVO5SEL LVO4SEL LVO3SEL LVO2SEL LVO1SEL LVO0SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
954
UDB_UDBPAIR0_ROUTE_LVO_CFG1
18.1.53 UDB_UDBPAIR0_ROUTE_LVO_CFG1
Address = 0x40342150 Left Vertical Ouput (LVO) selection Address: 0x40342150 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
RW
HW Access
R
R
Name
LVO9SEL [7:4]
LVO8SEL [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
RW
HW Access
R
R
Name
LVO11SEL [15:12]
LVO10SEL [11:8]
Bits
23
22
21
20
SW Access
RW
HW Access
R
Name
LVO13SEL [23:20]
19
18
17
16
RW
R
LVO12SEL [19:16]
Bits
31
30
29
28
SW Access
RW
HW Access
R
Name
LVO15SEL [31:28]
27
26
25
24
RW
R
LVO14SEL [27:24]
Bits 31 : 28 27 : 24 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
Name LVO15SEL LVO14SEL LVO13SEL LVO12SEL LVO11SEL LVO10SEL LVO9SEL LVO8SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
955
UDB_UDBPAIR0_ROUTE_RHO_CFG0
18.1.54 UDB_UDBPAIR0_ROUTE_RHO_CFG0
Address = 0x40342154 Right Horizontal Out (RHO) selection Address: 0x40342154 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
RHOSEL [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
RHOSEL [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
RHOSEL [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
RHOSEL [31:24]
Bits 31 : 0
Name RHOSEL
Description
Right Horizontal Output select for bits 31:0 Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
956
UDB_UDBPAIR0_ROUTE_RHO_CFG1
18.1.55 UDB_UDBPAIR0_ROUTE_RHO_CFG1
Address = 0x40342158 Right Horizontal Out (RHO) selection Address: 0x40342158 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
RHOSEL [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
RHOSEL [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
RHOSEL [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
RHOSEL [31:24]
Bits 31 : 0
Name RHOSEL
Description
Right Horizontal Output select for bits 63:32 Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
957
UDB_UDBPAIR0_ROUTE_RHO_CFG2
18.1.56 UDB_UDBPAIR0_ROUTE_RHO_CFG2
Address = 0x4034215C Right Horizontal Out (RHO) selection Address: 0x4034215C Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
RHOSEL [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
RHOSEL [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
RHOSEL [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
RHOSEL [31:24]
Bits 31 : 0
Name RHOSEL
Description
Right Horizontal Output select for bits 95:64 Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
958
UDB_UDBPAIR0_ROUTE_LHO_CFG0
18.1.57 UDB_UDBPAIR0_ROUTE_LHO_CFG0
Address = 0x40342160 Left Horizontal Out (LHO) selection Address: 0x40342160 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
RW
HW Access
R
R
Name
LHO1SEL [7:4]
LHO0SEL [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
RW
HW Access
R
R
Name
LHO3SEL [15:12]
LHO2SEL [11:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
RW
HW Access
R
R
Name
LHO5SEL [23:20]
LHO4SEL [19:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
RW
HW Access
R
R
Name
LHO7SEL [31:28]
LHO6SEL [27:24]
Bits 31 : 28 27 : 24 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
Name LHO7SEL LHO6SEL LHO5SEL LHO4SEL LHO3SEL LHO2SEL LHO1SEL LHO0SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
959
UDB_UDBPAIR0_ROUTE_LHO_CFG1
18.1.58 UDB_UDBPAIR0_ROUTE_LHO_CFG1
Address = 0x40342164 Left Horizontal Out (LHO) selection Address: 0x40342164 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
RW
HW Access
R
R
Name
LHO9SEL [7:4]
LHO8SEL [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
RW
HW Access
R
R
Name
LHO11SEL [15:12]
LHO10SEL [11:8]
Bits
23
22
21
20
SW Access
RW
HW Access
R
Name
LHO13SEL [23:20]
19
18
17
16
RW
R
LHO12SEL [19:16]
Bits
31
30
29
28
SW Access
RW
HW Access
R
Name
LHO15SEL [31:28]
27
26
25
24
RW
R
LHO14SEL [27:24]
Bits 31 : 28 27 : 24 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
Name LHO15SEL LHO14SEL LHO13SEL LHO12SEL LHO11SEL LHO10SEL LHO9SEL LHO8SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
960
UDB_UDBPAIR0_ROUTE_LHO_CFG2
18.1.59 UDB_UDBPAIR0_ROUTE_LHO_CFG2
Address = 0x40342168 Left Horizontal Out (LHO) selection Address: 0x40342168 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
RW
HW Access
R
R
Name
LHO17SEL [7:4]
LHO16SEL [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
RW
HW Access
R
R
Name
LHO19SEL [15:12]
LHO18SEL [11:8]
Bits
23
22
21
20
SW Access
RW
HW Access
R
Name
LHO21SEL [23:20]
19
18
17
16
RW
R
LHO20SEL [19:16]
Bits
31
30
29
28
SW Access
RW
HW Access
R
Name
LHO23SEL [31:28]
27
26
25
24
RW
R
LHO22SEL [27:24]
Bits 31 : 28 27 : 24 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
Name LHO23SEL LHO22SEL LHO21SEL LHO20SEL LHO19SEL LHO18SEL LHO17SEL LHO16SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
961
UDB_UDBPAIR0_ROUTE_LHO_CFG3
18.1.60 UDB_UDBPAIR0_ROUTE_LHO_CFG3
Address = 0x4034216C Left Horizontal Out (LHO) selection Address: 0x4034216C Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
RW
HW Access
R
R
Name
LHO25SEL [7:4]
LHO24SEL [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
RW
HW Access
R
R
Name
LHO27SEL [15:12]
LHO26SEL [11:8]
Bits
23
22
21
20
SW Access
RW
HW Access
R
Name
LHO29SEL [23:20]
19
18
17
16
RW
R
LHO28SEL [19:16]
Bits
31
30
29
28
SW Access
RW
HW Access
R
Name
LHO31SEL [31:28]
27
26
25
24
RW
R
LHO30SEL [27:24]
Bits 31 : 28 27 : 24 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
Name LHO31SEL LHO30SEL LHO29SEL LHO28SEL LHO27SEL LHO26SEL LHO25SEL LHO24SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
962
UDB_UDBPAIR0_ROUTE_LHO_CFG4
18.1.61 UDB_UDBPAIR0_ROUTE_LHO_CFG4
Address = 0x40342170 Left Horizontal Out (LHO) selection Address: 0x40342170 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
RW
HW Access
R
R
Name
LHO33SEL [7:4]
LHO32SEL [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
RW
HW Access
R
R
Name
LHO35SEL [15:12]
LHO34SEL [11:8]
Bits
23
22
21
20
SW Access
RW
HW Access
R
Name
LHO37SEL [23:20]
19
18
17
16
RW
R
LHO36SEL [19:16]
Bits
31
30
29
28
SW Access
RW
HW Access
R
Name
LHO39SEL [31:28]
27
26
25
24
RW
R
LHO38SEL [27:24]
Bits 31 : 28 27 : 24 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
Name LHO39SEL LHO38SEL LHO37SEL LHO36SEL LHO35SEL LHO34SEL LHO33SEL LHO32SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
963
UDB_UDBPAIR0_ROUTE_LHO_CFG5
18.1.62 UDB_UDBPAIR0_ROUTE_LHO_CFG5
Address = 0x40342174 Left Horizontal Out (LHO) selection Address: 0x40342174 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
RW
HW Access
R
R
Name
LHO41SEL [7:4]
LHO40SEL [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
RW
HW Access
R
R
Name
LHO43SEL [15:12]
LHO42SEL [11:8]
Bits
23
22
21
20
SW Access
RW
HW Access
R
Name
LHO45SEL [23:20]
19
18
17
16
RW
R
LHO44SEL [19:16]
Bits
31
30
29
28
SW Access
RW
HW Access
R
Name
LHO47SEL [31:28]
27
26
25
24
RW
R
LHO46SEL [27:24]
Bits 31 : 28 27 : 24 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
Name LHO47SEL LHO46SEL LHO45SEL LHO44SEL LHO43SEL LHO42SEL LHO41SEL LHO40SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
964
UDB_UDBPAIR0_ROUTE_LHO_CFG6
18.1.63 UDB_UDBPAIR0_ROUTE_LHO_CFG6
Address = 0x40342178 Left Horizontal Out (LHO) selection Address: 0x40342178 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
RW
HW Access
R
R
Name
LHO49SEL [7:4]
LHO48SEL [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
RW
HW Access
R
R
Name
LHO51SEL [15:12]
LHO50SEL [11:8]
Bits
23
22
21
20
SW Access
RW
HW Access
R
Name
LHO53SEL [23:20]
19
18
17
16
RW
R
LHO52SEL [19:16]
Bits
31
30
29
28
SW Access
RW
HW Access
R
Name
LHO55SEL [31:28]
27
26
25
24
RW
R
LHO54SEL [27:24]
Bits 31 : 28 27 : 24 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
Name LHO55SEL LHO54SEL LHO53SEL LHO52SEL LHO51SEL LHO50SEL LHO49SEL LHO48SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
965
UDB_UDBPAIR0_ROUTE_LHO_CFG7
18.1.64 UDB_UDBPAIR0_ROUTE_LHO_CFG7
Address = 0x4034217C Left Horizontal Out (LHO) selection Address: 0x4034217C Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
RW
HW Access
R
R
Name
LHO57SEL [7:4]
LHO56SEL [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
RW
HW Access
R
R
Name
LHO59SEL [15:12]
LHO58SEL [11:8]
Bits
23
22
21
20
SW Access
RW
HW Access
R
Name
LHO61SEL [23:20]
19
18
17
16
RW
R
LHO60SEL [19:16]
Bits
31
30
29
28
SW Access
RW
HW Access
R
Name
LHO63SEL [31:28]
27
26
25
24
RW
R
LHO62SEL [27:24]
Bits 31 : 28 27 : 24 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
Name LHO63SEL LHO62SEL LHO61SEL LHO60SEL LHO59SEL LHO58SEL LHO57SEL LHO56SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
966
UDB_UDBPAIR0_ROUTE_LHO_CFG8
18.1.65 UDB_UDBPAIR0_ROUTE_LHO_CFG8
Address = 0x40342180 Left Horizontal Out (LHO) selection Address: 0x40342180 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
RW
HW Access
R
R
Name
LHO65SEL [7:4]
LHO64SEL [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
RW
HW Access
R
R
Name
LHO67SEL [15:12]
LHO66SEL [11:8]
Bits
23
22
21
20
SW Access
RW
HW Access
R
Name
LHO69SEL [23:20]
19
18
17
16
RW
R
LHO68SEL [19:16]
Bits
31
30
29
28
SW Access
RW
HW Access
R
Name
LHO71SEL [31:28]
27
26
25
24
RW
R
LHO70SEL [27:24]
Bits 31 : 28 27 : 24 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
Name LHO71SEL LHO70SEL LHO69SEL LHO68SEL LHO67SEL LHO66SEL LHO65SEL LHO64SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
967
UDB_UDBPAIR0_ROUTE_LHO_CFG9
18.1.66 UDB_UDBPAIR0_ROUTE_LHO_CFG9
Address = 0x40342184 Left Horizontal Out (LHO) selection Address: 0x40342184 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
RW
HW Access
R
R
Name
LHO73SEL [7:4]
LHO72SEL [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
RW
HW Access
R
R
Name
LHO75SEL [15:12]
LHO74SEL [11:8]
Bits
23
22
21
20
SW Access
RW
HW Access
R
Name
LHO77SEL [23:20]
19
18
17
16
RW
R
LHO76SEL [19:16]
Bits
31
30
29
28
SW Access
RW
HW Access
R
Name
LHO79SEL [31:28]
27
26
25
24
RW
R
LHO78SEL [27:24]
Bits 31 : 28 27 : 24 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
Name LHO79SEL LHO78SEL LHO77SEL LHO76SEL LHO75SEL LHO74SEL LHO73SEL LHO72SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
968
UDB_UDBPAIR0_ROUTE_LHO_CFG10
18.1.67 UDB_UDBPAIR0_ROUTE_LHO_CFG10
Address = 0x40342188 Left Horizontal Out (LHO) selection Address: 0x40342188 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
RW
HW Access
R
R
Name
LHO81SEL [7:4]
LHO80SEL [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
RW
HW Access
R
R
Name
LHO83SEL [15:12]
LHO82SEL [11:8]
Bits
23
22
21
20
SW Access
RW
HW Access
R
Name
LHO85SEL [23:20]
19
18
17
16
RW
R
LHO84SEL [19:16]
Bits
31
30
29
28
SW Access
RW
HW Access
R
Name
LHO87SEL [31:28]
27
26
25
24
RW
R
LHO86SEL [27:24]
Bits 31 : 28 27 : 24 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
Name LHO87SEL LHO86SEL LHO85SEL LHO84SEL LHO83SEL LHO82SEL LHO81SEL LHO80SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
969
UDB_UDBPAIR0_ROUTE_LHO_CFG11
18.1.68 UDB_UDBPAIR0_ROUTE_LHO_CFG11
Address = 0x4034218C Left Horizontal Out (LHO) selection Address: 0x4034218C Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
RW
HW Access
R
R
Name
LHO89SEL [7:4]
LHO88SEL [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
RW
HW Access
R
R
Name
LHO91SEL [15:12]
LHO90SEL [11:8]
Bits
23
22
21
20
SW Access
RW
HW Access
R
Name
LHO93SEL [23:20]
19
18
17
16
RW
R
LHO92SEL [19:16]
Bits
31
30
29
28
SW Access
RW
HW Access
R
Name
LHO95SEL [31:28]
27
26
25
24
RW
R
LHO94SEL [27:24]
Bits 31 : 28 27 : 24 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
Name LHO95SEL LHO94SEL LHO93SEL LHO92SEL LHO91SEL LHO90SEL LHO89SEL LHO88SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
970
UDB_DSI0_LVO1_V_2
18.1.69 UDB_DSI0_LVO1_V_2
Address = 0x40346000 Left Vertical Ouput (LVO) 1 vs 2 muxing for certain horizontals Address: 0x40346000 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
LVO1_V_2 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
LVO1_V_2 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
LVO1_V_2 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
LVO1_V_2 [31:24]
Bits 31 : 0
Name LVO1_V_2
Description Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
971
UDB_DSI0_RVO1_V_2
18.1.70 UDB_DSI0_RVO1_V_2
Address = 0x40346004 Right Vertical Ouput (RVO) 1 vs 2 muxing for certain horizontals Address: 0x40346004 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
RVO1_V_2 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
RVO1_V_2 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
RVO1_V_2 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
RVO1_V_2 [31:24]
Bits 31 : 0
Name RVO1_V_2
Description Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
972
UDB_DSI0_DOP_CFG0
18.1.71 UDB_DSI0_DOP_CFG0
Address = 0x40346008 DSI Out Pair (DOP) selection Address: 0x40346008 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:5]
DOP0SEL [4:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
RW
HW Access
None
R
Name
None [15:13]
DOP1SEL [12:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
HW Access
None
R
Name
None [23:21]
DOP2SEL [20:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
RW
HW Access
None
R
Name
None [31:29]
DOP3SEL [28:24]
Bits 28 : 24 20 : 16 12 : 8 4 : 0
Name DOP3SEL DOP2SEL DOP1SEL DOP0SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
973
UDB_DSI0_DOP_CFG1
18.1.72 UDB_DSI0_DOP_CFG1
Address = 0x4034600C DSI Out Pair (DOP) selection Address: 0x4034600C Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:5]
DOP4SEL [4:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
RW
HW Access
None
R
Name
None [15:13]
DOP5SEL [12:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
HW Access
None
R
Name
None [23:21]
DOP6SEL [20:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
RW
HW Access
None
R
Name
None [31:29]
DOP7SEL [28:24]
Bits 28 : 24 20 : 16 12 : 8 4 : 0
Name DOP7SEL DOP6SEL DOP5SEL DOP4SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
974
UDB_DSI0_DOP_CFG2
18.1.73 UDB_DSI0_DOP_CFG2
Address = 0x40346010 DSI Out Pair (DOP) selection Address: 0x40346010 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:5]
DOP8SEL [4:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
RW
HW Access
None
R
Name
None [15:13]
DOP9SEL [12:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
HW Access
None
R
Name
None [23:21]
DOP10SEL [20:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
RW
HW Access
None
R
Name
None [31:29]
DOP11SEL [28:24]
Bits 28 : 24 20 : 16 12 : 8 4 : 0
Name DOP11SEL DOP10SEL DOP9SEL DOP8SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
975
UDB_DSI0_DOP_CFG3
18.1.74 UDB_DSI0_DOP_CFG3
Address = 0x40346014 DSI Out Pair (DOP) selection Address: 0x40346014 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:5]
DOP12SEL [4:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
RW
HW Access
None
R
Name
None [15:13]
DOP13SEL [12:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
HW Access
None
R
Name
None [23:21]
DOP14SEL [20:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
RW
HW Access
None
R
Name
None [31:29]
DOP15SEL [28:24]
Bits 28 : 24 20 : 16 12 : 8 4 : 0
Name DOP15SEL DOP14SEL DOP13SEL DOP12SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
976
UDB_DSI0_DOT_CFG0
18.1.75 UDB_DSI0_DOT_CFG0
Address = 0x40346018 DSI Out Triplet (DOT) selection Address: 0x40346018 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:5]
DOT0SEL [4:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
RW
HW Access
None
R
Name
None [15:13]
DOT1SEL [12:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
HW Access
None
R
Name
None [23:21]
DOT2SEL [20:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
RW
HW Access
None
R
Name
None [31:29]
DOT3SEL [28:24]
Bits 28 : 24 20 : 16 12 : 8 4 : 0
Name DOT3SEL DOT2SEL DOT1SEL DOT0SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
977
UDB_DSI0_DOT_CFG1
18.1.76 UDB_DSI0_DOT_CFG1
Address = 0x4034601C DSI Out Triplet (DOT) selection Address: 0x4034601C Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:5]
DOT4SEL [4:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
RW
HW Access
None
R
Name
None [15:13]
DOT5SEL [12:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
HW Access
None
R
Name
None [23:21]
DOT6SEL [20:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
RW
HW Access
None
R
Name
None [31:29]
DOT7SEL [28:24]
Bits 28 : 24 20 : 16 12 : 8 4 : 0
Name DOT7SEL DOT6SEL DOT5SEL DOT4SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
978
UDB_DSI0_DOT_CFG2
18.1.77 UDB_DSI0_DOT_CFG2
Address = 0x40346020 DSI Out Triplet (DOT) selection Address: 0x40346020 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:5]
DOT8SEL [4:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
RW
HW Access
None
R
Name
None [15:13]
DOT9SEL [12:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
HW Access
None
R
Name
None [23:21]
DOT10SEL [20:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
RW
HW Access
None
R
Name
None [31:29]
DOT11SEL [28:24]
Bits 28 : 24 20 : 16 12 : 8 4 : 0
Name DOT11SEL DOT10SEL DOT9SEL DOT8SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
979
UDB_DSI0_DOT_CFG3
18.1.78 UDB_DSI0_DOT_CFG3
Address = 0x40346024 DSI Out Triplet (DOT) selection Address: 0x40346024 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:5]
DOT12SEL [4:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
RW
HW Access
None
R
Name
None [15:13]
DOT13SEL [12:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
HW Access
None
R
Name
None [23:21]
DOT14SEL [20:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
RW
HW Access
None
R
Name
None [31:29]
DOT15SEL [28:24]
Bits 28 : 24 20 : 16 12 : 8 4 : 0
Name DOT15SEL DOT14SEL DOT13SEL DOT12SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
980
UDB_DSI0_RVO_CFG0
18.1.79 UDB_DSI0_RVO_CFG0
Address = 0x40346028 Right Vertical Ouput (RVO) selection Address: 0x40346028 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:5]
RVO0SEL [4:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
RW
HW Access
None
R
Name
None [15:13]
RVO1SEL [12:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
HW Access
None
R
Name
None [23:21]
RVO2SEL [20:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
RW
HW Access
None
R
Name
None [31:29]
RVO3SEL [28:24]
Bits 28 : 24 20 : 16 12 : 8 4 : 0
Name RVO3SEL RVO2SEL RVO1SEL RVO0SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
981
UDB_DSI0_RVO_CFG1
18.1.80 UDB_DSI0_RVO_CFG1
Address = 0x4034602C Right Vertical Ouput (RVO) selection Address: 0x4034602C Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:5]
RVO4SEL [4:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
RW
HW Access
None
R
Name
None [15:13]
RVO5SEL [12:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
HW Access
None
R
Name
None [23:21]
RVO6SEL [20:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
RW
HW Access
None
R
Name
None [31:29]
RVO7SEL [28:24]
Bits 28 : 24 20 : 16 12 : 8 4 : 0
Name RVO7SEL RVO6SEL RVO5SEL RVO4SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
982
UDB_DSI0_RVO_CFG2
18.1.81 UDB_DSI0_RVO_CFG2
Address = 0x40346030 Right Vertical Ouput (RVO) selection Address: 0x40346030 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:5]
RVO8SEL [4:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
RW
HW Access
None
R
Name
None [15:13]
RVO9SEL [12:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
HW Access
None
R
Name
None [23:21]
RVO10SEL [20:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
RW
HW Access
None
R
Name
None [31:29]
RVO11SEL [28:24]
Bits 28 : 24 20 : 16 12 : 8 4 : 0
Name RVO11SEL RVO10SEL RVO9SEL RVO8SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
983
UDB_DSI0_RVO_CFG3
18.1.82 UDB_DSI0_RVO_CFG3
Address = 0x40346034 Right Vertical Ouput (RVO) selection Address: 0x40346034 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:5]
RVO12SEL [4:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
RW
HW Access
None
R
Name
None [15:13]
RVO13SEL [12:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
HW Access
None
R
Name
None [23:21]
RVO14SEL [20:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
RW
HW Access
None
R
Name
None [31:29]
RVO15SEL [28:24]
Bits 28 : 24 20 : 16 12 : 8 4 : 0
Name RVO15SEL RVO14SEL RVO13SEL RVO12SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
984
UDB_DSI0_LVO_CFG0
18.1.83 UDB_DSI0_LVO_CFG0
Address = 0x40346038 Left Vertical Ouput (LVO) selection Address: 0x40346038 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
RW
HW Access
R
R
Name
LVO1SEL [7:4]
LVO0SEL [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
RW
HW Access
R
R
Name
LVO3SEL [15:12]
LVO2SEL [11:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
RW
HW Access
R
R
Name
LVO5SEL [23:20]
LVO4SEL [19:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
RW
HW Access
R
R
Name
LVO7SEL [31:28]
LVO6SEL [27:24]
Bits 31 : 28 27 : 24 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
Name LVO7SEL LVO6SEL LVO5SEL LVO4SEL LVO3SEL LVO2SEL LVO1SEL LVO0SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
985
UDB_DSI0_LVO_CFG1
18.1.84 UDB_DSI0_LVO_CFG1
Address = 0x4034603C Left Vertical Ouput (LVO) selection Address: 0x4034603C Retention: Retained
Bits
7
6
5
4
SW Access
RW
HW Access
R
Name
LVO9SEL [7:4]
Bits
15
14
13
12
SW Access
RW
HW Access
R
Name
LVO11SEL [15:12]
Bits
23
22
21
20
SW Access
RW
HW Access
R
Name
LVO13SEL [23:20]
Bits
31
30
29
28
SW Access
RW
HW Access
R
Name
LVO15SEL [31:28]
Bits 31 : 28 27 : 24 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
Name LVO15SEL LVO14SEL LVO13SEL LVO12SEL LVO11SEL LVO10SEL LVO9SEL LVO8SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X
3
2
1
0
RW
R
LVO8SEL [3:0]
11
10
9
8
RW
R
LVO10SEL [11:8]
19
18
17
16
RW
R
LVO12SEL [19:16]
27
26
25
24
RW
R
LVO14SEL [27:24]
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
986
UDB_DSI0_RHO_CFG0
18.1.85 UDB_DSI0_RHO_CFG0
Address = 0x40346040 Right Horizontal Out (RHO) selection Address: 0x40346040 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
RHOSEL [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
RHOSEL [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
RHOSEL [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
RHOSEL [31:24]
Bits 31 : 0
Name RHOSEL
Description
Right Horizontal Output select for bits 31:0 Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
987
UDB_DSI0_RHO_CFG1
18.1.86 UDB_DSI0_RHO_CFG1
Address = 0x40346044 Right Horizontal Out (RHO) selection Address: 0x40346044 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
RHOSEL [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
RHOSEL [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
RHOSEL [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
RHOSEL [31:24]
Bits 31 : 0
Name RHOSEL
Description
Right Horizontal Output select for bits 63:32 Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
988
UDB_DSI0_RHO_CFG2
18.1.87 UDB_DSI0_RHO_CFG2
Address = 0x40346048 Right Horizontal Out (RHO) selection Address: 0x40346048 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
RHOSEL [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
RHOSEL [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
RHOSEL [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
RHOSEL [31:24]
Bits 31 : 0
Name RHOSEL
Description
Right Horizontal Output select for bits 95:64 Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
989
UDB_DSI0_LHO_CFG0
18.1.88 UDB_DSI0_LHO_CFG0
Address = 0x4034604C Left Horizontal Out (LHO) selection Address: 0x4034604C Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
RW
HW Access
R
R
Name
LHO1SEL [7:4]
LHO0SEL [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
RW
HW Access
R
R
Name
LHO3SEL [15:12]
LHO2SEL [11:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
RW
HW Access
R
R
Name
LHO5SEL [23:20]
LHO4SEL [19:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
RW
HW Access
R
R
Name
LHO7SEL [31:28]
LHO6SEL [27:24]
Bits 31 : 28 27 : 24 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
Name LHO7SEL LHO6SEL LHO5SEL LHO4SEL LHO3SEL LHO2SEL LHO1SEL LHO0SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
990
UDB_DSI0_LHO_CFG1
18.1.89 UDB_DSI0_LHO_CFG1
Address = 0x40346050 Left Horizontal Out (LHO) selection Address: 0x40346050 Retention: Retained
Bits
7
6
5
4
SW Access
RW
HW Access
R
Name
LHO9SEL [7:4]
Bits
15
14
13
12
SW Access
RW
HW Access
R
Name
LHO11SEL [15:12]
Bits
23
22
21
20
SW Access
RW
HW Access
R
Name
LHO13SEL [23:20]
Bits
31
30
29
28
SW Access
RW
HW Access
R
Name
LHO15SEL [31:28]
Bits 31 : 28 27 : 24 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
Name LHO15SEL LHO14SEL LHO13SEL LHO12SEL LHO11SEL LHO10SEL LHO9SEL LHO8SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X
3
2
1
0
RW
R
LHO8SEL [3:0]
11
10
9
8
RW
R
LHO10SEL [11:8]
19
18
17
16
RW
R
LHO12SEL [19:16]
27
26
25
24
RW
R
LHO14SEL [27:24]
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
991
UDB_DSI0_LHO_CFG2
18.1.90 UDB_DSI0_LHO_CFG2
Address = 0x40346054 Left Horizontal Out (LHO) selection Address: 0x40346054 Retention: Retained
Bits
7
6
5
4
SW Access
RW
HW Access
R
Name
LHO17SEL [7:4]
Bits
15
14
13
12
SW Access
RW
HW Access
R
Name
LHO19SEL [15:12]
Bits
23
22
21
20
SW Access
RW
HW Access
R
Name
LHO21SEL [23:20]
Bits
31
30
29
28
SW Access
RW
HW Access
R
Name
LHO23SEL [31:28]
Bits 31 : 28 27 : 24 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
Name LHO23SEL LHO22SEL LHO21SEL LHO20SEL LHO19SEL LHO18SEL LHO17SEL LHO16SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X
3
2
1
0
RW
R
LHO16SEL [3:0]
11
10
9
8
RW
R
LHO18SEL [11:8]
19
18
17
16
RW
R
LHO20SEL [19:16]
27
26
25
24
RW
R
LHO22SEL [27:24]
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
992
UDB_DSI0_LHO_CFG3
18.1.91 UDB_DSI0_LHO_CFG3
Address = 0x40346058 Left Horizontal Out (LHO) selection Address: 0x40346058 Retention: Retained
Bits
7
6
5
4
SW Access
RW
HW Access
R
Name
LHO25SEL [7:4]
Bits
15
14
13
12
SW Access
RW
HW Access
R
Name
LHO27SEL [15:12]
Bits
23
22
21
20
SW Access
RW
HW Access
R
Name
LHO29SEL [23:20]
Bits
31
30
29
28
SW Access
RW
HW Access
R
Name
LHO31SEL [31:28]
Bits 31 : 28 27 : 24 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
Name LHO31SEL LHO30SEL LHO29SEL LHO28SEL LHO27SEL LHO26SEL LHO25SEL LHO24SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X
3
2
1
0
RW
R
LHO24SEL [3:0]
11
10
9
8
RW
R
LHO26SEL [11:8]
19
18
17
16
RW
R
LHO28SEL [19:16]
27
26
25
24
RW
R
LHO30SEL [27:24]
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
993
UDB_DSI0_LHO_CFG4
18.1.92 UDB_DSI0_LHO_CFG4
Address = 0x4034605C Left Horizontal Out (LHO) selection Address: 0x4034605C Retention: Retained
Bits
7
6
5
4
SW Access
RW
HW Access
R
Name
LHO33SEL [7:4]
Bits
15
14
13
12
SW Access
RW
HW Access
R
Name
LHO35SEL [15:12]
Bits
23
22
21
20
SW Access
RW
HW Access
R
Name
LHO37SEL [23:20]
Bits
31
30
29
28
SW Access
RW
HW Access
R
Name
LHO39SEL [31:28]
Bits 31 : 28 27 : 24 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
Name LHO39SEL LHO38SEL LHO37SEL LHO36SEL LHO35SEL LHO34SEL LHO33SEL LHO32SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X
3
2
1
0
RW
R
LHO32SEL [3:0]
11
10
9
8
RW
R
LHO34SEL [11:8]
19
18
17
16
RW
R
LHO36SEL [19:16]
27
26
25
24
RW
R
LHO38SEL [27:24]
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
994
UDB_DSI0_LHO_CFG5
18.1.93 UDB_DSI0_LHO_CFG5
Address = 0x40346060 Left Horizontal Out (LHO) selection Address: 0x40346060 Retention: Retained
Bits
7
6
5
4
SW Access
RW
HW Access
R
Name
LHO41SEL [7:4]
Bits
15
14
13
12
SW Access
RW
HW Access
R
Name
LHO43SEL [15:12]
Bits
23
22
21
20
SW Access
RW
HW Access
R
Name
LHO45SEL [23:20]
Bits
31
30
29
28
SW Access
RW
HW Access
R
Name
LHO47SEL [31:28]
Bits 31 : 28 27 : 24 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
Name LHO47SEL LHO46SEL LHO45SEL LHO44SEL LHO43SEL LHO42SEL LHO41SEL LHO40SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X
3
2
1
0
RW
R
LHO40SEL [3:0]
11
10
9
8
RW
R
LHO42SEL [11:8]
19
18
17
16
RW
R
LHO44SEL [19:16]
27
26
25
24
RW
R
LHO46SEL [27:24]
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
995
UDB_DSI0_LHO_CFG6
18.1.94 UDB_DSI0_LHO_CFG6
Address = 0x40346064 Left Horizontal Out (LHO) selection Address: 0x40346064 Retention: Retained
Bits
7
6
5
4
SW Access
RW
HW Access
R
Name
LHO49SEL [7:4]
Bits
15
14
13
12
SW Access
RW
HW Access
R
Name
LHO51SEL [15:12]
Bits
23
22
21
20
SW Access
RW
HW Access
R
Name
LHO53SEL [23:20]
Bits
31
30
29
28
SW Access
RW
HW Access
R
Name
LHO55SEL [31:28]
Bits 31 : 28 27 : 24 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
Name LHO55SEL LHO54SEL LHO53SEL LHO52SEL LHO51SEL LHO50SEL LHO49SEL LHO48SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X
3
2
1
0
RW
R
LHO48SEL [3:0]
11
10
9
8
RW
R
LHO50SEL [11:8]
19
18
17
16
RW
R
LHO52SEL [19:16]
27
26
25
24
RW
R
LHO54SEL [27:24]
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
996
UDB_DSI0_LHO_CFG7
18.1.95 UDB_DSI0_LHO_CFG7
Address = 0x40346068 Left Horizontal Out (LHO) selection Address: 0x40346068 Retention: Retained
Bits
7
6
5
4
SW Access
RW
HW Access
R
Name
LHO57SEL [7:4]
Bits
15
14
13
12
SW Access
RW
HW Access
R
Name
LHO59SEL [15:12]
Bits
23
22
21
20
SW Access
RW
HW Access
R
Name
LHO61SEL [23:20]
Bits
31
30
29
28
SW Access
RW
HW Access
R
Name
LHO63SEL [31:28]
Bits 31 : 28 27 : 24 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
Name LHO63SEL LHO62SEL LHO61SEL LHO60SEL LHO59SEL LHO58SEL LHO57SEL LHO56SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X
3
2
1
0
RW
R
LHO56SEL [3:0]
11
10
9
8
RW
R
LHO58SEL [11:8]
19
18
17
16
RW
R
LHO60SEL [19:16]
27
26
25
24
RW
R
LHO62SEL [27:24]
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
997
UDB_DSI0_LHO_CFG8
18.1.96 UDB_DSI0_LHO_CFG8
Address = 0x4034606C Left Horizontal Out (LHO) selection Address: 0x4034606C Retention: Retained
Bits
7
6
5
4
SW Access
RW
HW Access
R
Name
LHO65SEL [7:4]
Bits
15
14
13
12
SW Access
RW
HW Access
R
Name
LHO67SEL [15:12]
Bits
23
22
21
20
SW Access
RW
HW Access
R
Name
LHO69SEL [23:20]
Bits
31
30
29
28
SW Access
RW
HW Access
R
Name
LHO71SEL [31:28]
Bits 31 : 28 27 : 24 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
Name LHO71SEL LHO70SEL LHO69SEL LHO68SEL LHO67SEL LHO66SEL LHO65SEL LHO64SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X
3
2
1
0
RW
R
LHO64SEL [3:0]
11
10
9
8
RW
R
LHO66SEL [11:8]
19
18
17
16
RW
R
LHO68SEL [19:16]
27
26
25
24
RW
R
LHO70SEL [27:24]
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
998
UDB_DSI0_LHO_CFG9
18.1.97 UDB_DSI0_LHO_CFG9
Address = 0x40346070 Left Horizontal Out (LHO) selection Address: 0x40346070 Retention: Retained
Bits
7
6
5
4
SW Access
RW
HW Access
R
Name
LHO73SEL [7:4]
Bits
15
14
13
12
SW Access
RW
HW Access
R
Name
LHO75SEL [15:12]
Bits
23
22
21
20
SW Access
RW
HW Access
R
Name
LHO77SEL [23:20]
Bits
31
30
29
28
SW Access
RW
HW Access
R
Name
LHO79SEL [31:28]
Bits 31 : 28 27 : 24 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
Name LHO79SEL LHO78SEL LHO77SEL LHO76SEL LHO75SEL LHO74SEL LHO73SEL LHO72SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X
3
2
1
0
RW
R
LHO72SEL [3:0]
11
10
9
8
RW
R
LHO74SEL [11:8]
19
18
17
16
RW
R
LHO76SEL [19:16]
27
26
25
24
RW
R
LHO78SEL [27:24]
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
999
UDB_DSI0_LHO_CFG10
18.1.98 UDB_DSI0_LHO_CFG10
Address = 0x40346074 Left Horizontal Out (LHO) selection Address: 0x40346074 Retention: Retained
Bits
7
6
5
4
SW Access
RW
HW Access
R
Name
LHO81SEL [7:4]
Bits
15
14
13
12
SW Access
RW
HW Access
R
Name
LHO83SEL [15:12]
Bits
23
22
21
20
SW Access
RW
HW Access
R
Name
LHO85SEL [23:20]
Bits
31
30
29
28
SW Access
RW
HW Access
R
Name
LHO87SEL [31:28]
Bits 31 : 28 27 : 24 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
Name LHO87SEL LHO86SEL LHO85SEL LHO84SEL LHO83SEL LHO82SEL LHO81SEL LHO80SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X
3
2
1
0
RW
R
LHO80SEL [3:0]
11
10
9
8
RW
R
LHO82SEL [11:8]
19
18
17
16
RW
R
LHO84SEL [19:16]
27
26
25
24
RW
R
LHO86SEL [27:24]
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1000
UDB_DSI0_LHO_CFG11
18.1.99 UDB_DSI0_LHO_CFG11
Address = 0x40346078 Left Horizontal Out (LHO) selection Address: 0x40346078 Retention: Retained
Bits
7
6
5
4
SW Access
RW
HW Access
R
Name
LHO89SEL [7:4]
Bits
15
14
13
12
SW Access
RW
HW Access
R
Name
LHO91SEL [15:12]
Bits
23
22
21
20
SW Access
RW
HW Access
R
Name
LHO93SEL [23:20]
Bits
31
30
29
28
SW Access
RW
HW Access
R
Name
LHO95SEL [31:28]
Bits 31 : 28 27 : 24 23 : 20 19 : 16 15 : 12 11 : 8 7 : 4 3 : 0
Name LHO95SEL LHO94SEL LHO93SEL LHO92SEL LHO91SEL LHO90SEL LHO89SEL LHO88SEL
Description Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X Default Value: X
3
2
1
0
RW
R
LHO88SEL [3:0]
11
10
9
8
RW
R
LHO90SEL [11:8]
19
18
17
16
RW
R
LHO92SEL [19:16]
27
26
25
24
RW
R
LHO94SEL [27:24]
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1001
UDB_PA0_CFG0
18.1.100 UDB_PA0_CFG0
Address = 0x40347000 PA Data In Clock Control Register Address: 0x40347000 Retention: Retained
Bits SW Access HW Access
Name
7
6
None
None
None [7:6]
5
4
RW
RW
R
R
CLKIN_INV
CLKIN_EN_ INV
3
2
RW
R
CLKIN_EN_MODE [3:2]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
1
0
RW
R
CLKIN_EN_SEL [1:0]
9
8
17
16
25
24
Bits
Name
5
CLKIN_INV
4
CLKIN_EN_INV
3 : 2
CLKIN_EN_MODE
Description
Determines whether the selected clock is inverted or not. Default Value: 0
0x0: NOINV : Not Inverted
0x1: INV : Inverted
Determines whether the selected enable is inverted or not. Default Value: 0
0x0: NOINV : Not Inverted
0x1: INV : Inverted
Select one of four operating modes Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1002
UDB_PA0_CFG0
18.1.100 UDB_PA0_CFG0 (continued)
1 : 0
CLKIN_EN_SEL
0x0: OFF : Always off
0x1: ON : Always on
0x2: POSEDGE : Positive edge - A clock is output on a 0 to 1 transition on the enable input
0x3: LEVEL : Level sensitive - A clock is output when the enable is high.
Select one of four choices for clock enable Default Value: 0
0x0: PIN_RC : pin_rc - port pin multiplexer output
0x1: DSI_RC_0 : dsi_rc[0] - dsi_xx_out_p[4]
0x2: DSI_RC_1 : dsi_rc[1] - dsi_xx_out_p[5]
0x3: DSI_RC_2 : dsi_rc{1} - dsi_xx_out_p[6]
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1003
UDB_PA0_CFG1
18.1.101 UDB_PA0_CFG1
Address = 0x40347004 PA Data Out Clock Control Register Address: 0x40347004 Retention: Retained
Bits SW Access HW Access
Name
7
6
None
None
None [7:6]
Bits
15
14
SW Access
HW Access
Name
Bits
23
22
SW Access
HW Access
Name
Bits
31
30
SW Access
HW Access
Name
5 RW R
CLKOUT_INV
4
RW
R
CLKOUT_EN_-
INV
3
2
RW
R
CLKOUT_EN_MODE [3:2]
13
12
11
10
None
None
None [15:8]
21
20
19
18
None
None
None [23:16]
29
28
27
26
None
None
None [31:24]
1
0
RW
R
CLKOUT_EN_SEL [1:0]
9
8
17
16
25
24
Bits 5
4
3 : 2
Name CLKOUT_INV
CLKOUT_EN_INV
CLKOUT_EN_MODE
Description
Determines whether the selected clock is inverted or not. Default Value: 0
0x0: NOINV : Not Inverted
0x1: INV : Inverted
Determines whether the selected enable is inverted or not. Default Value: 0
0x0: NOINV : Not Inverted
0x1: INV : Inverted
Select one of four operating modes Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1004
UDB_PA0_CFG1
18.1.101 UDB_PA0_CFG1 (continued)
1 : 0
CLKOUT_EN_SEL
0x0: OFF : Always off
0x1: ON : Always on
0x2: POSEDGE : Positive edge - A clock is output on a 0 to 1 transition on the enable input
0x3: LEVEL : Level sensitive - A clock is output when the enable is high.
Select one of four choices for clock enable Default Value: 0
0x0: PIN_RC : pin_rc - port pin multiplexer output
0x1: DSI_RC_0 : dsi_rc[0] - dsi_xx_out_p[4]
0x2: DSI_RC_1 : dsi_rc[1] - dsi_xx_out_p[5]
0x3: DSI_RC_2 : dsi_rc{1} - dsi_xx_out_p[6]
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1005
UDB_PA0_CFG2
18.1.102 UDB_PA0_CFG2
Address = 0x40347008 PA Clock Select Register Address: 0x40347008 Retention: Retained
Bits
7
6
5
SW Access
RW
HW Access
R
Name
CLKOUT_SEL [7:4]
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4
3
12
11
None
None
None [15:8]
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
Bits 7 : 4
Name CLKOUT_SEL
Description
Select one of four choices for clock enable Default Value: 0
0x0: GCLK0 : gclk[0]
0x1: GCLK1 : gclk[1]
0x2: GCLK2 : gclk[2]
0x3: GCLK3 : gclk[3]
0x4: GCLK4 : gclk[4]
0x5: GCLK5 : gclk[5]
0x6: GCLK6 : gclk[6]
2
1
RW
R
CLKIN_SEL [3:0]
10
9
18
17
26
25
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
0 8 16 24
1006
18.1.102 UDB_PA0_CFG2 (continued)
3 : 0
CLKIN_SEL
0x7: GCLK7 : gclk[7]
0x9: BUS_CLK_APP : bus_clk_app
0xc: PIN_RC : pin_rc - port pin multiplexer output
0xd: DSI_RC_0 : dsi_rc[0] - dsi_xx_out_p[4]
0xe: DSI_RC_1 : dsi_rc[1] - dsi_xx_out_p[5]
0xf: DSI_RC_2 : dsi_rc{1} - dsi_xx_out_p[6]
Select one of four choices for clock enable Default Value: 0
0x0: GCLK0 : gclk[0]
0x1: GCLK1 : gclk[1]
0x2: GCLK2 : gclk[2]
0x3: GCLK3 : gclk[3]
0x4: GCLK4 : gclk[4]
0x5: GCLK5 : gclk[5]
0x6: GCLK6 : gclk[6]
0x7: GCLK7 : gclk[7]
0x9: BUS_CLK_APP : bus_clk_app
0xc: PIN_RC : pin_rc - port pin multiplexer output
0xd: DSI_RC_0 : dsi_rc[0] - dsi_xx_out_p[4]
0xe: DSI_RC_1 : dsi_rc[1] - dsi_xx_out_p[5]
0xf: DSI_RC_2 : dsi_rc{1} - dsi_xx_out_p[6]
UDB_PA0_CFG2
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1007
UDB_PA0_CFG3
18.1.103 UDB_PA0_CFG3
Address = 0x4034700C PA Reset Select Register Address: 0x4034700C Retention: Retained
Bits SW Access HW Access
Name
7 None None
None
6
RW
R
RES_OUT_ INV
Bits
15
14
SW Access
HW Access
Name
Bits
23
22
SW Access
HW Access
Name
Bits
31
30
SW Access
HW Access
Name
5
4
RW
R
RES_OUT_SEL [5:4]
3 None None
None
13
12
11
None
None
None [15:8]
21
20
19
None
None
None [23:16]
29
28
27
None
None
None [31:24]
2 RW R RES_IN_INV 10
18
26
1
0
RW
R
RES_IN_SEL [1:0]
9
8
17
16
25
24
Bits
Name
6
RES_OUT_INV
5 : 4
RES_OUT_SEL
Description
Select the polarity of the reset control. Default Value: 0
0x0: NOINV : Not Inverted
0x1: INV : Inverted
Select one of four inputs to serve as the reset control to the block. Default Value: 0
0x0: PIN_RC : pin_rc - port pin multiplexer output
0x1: DSI_RC_0 : dsi_rc[0] - dsi_xx_out_p[4]
0x2: DSI_RC_1 : dsi_rc[1] - dsi_xx_out_p[5]
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1008
UDB_PA0_CFG3
18.1.103 UDB_PA0_CFG3 (continued)
2
RES_IN_INV
1 : 0
RES_IN_SEL
0x3: DSI_RC_2 : dsi_rc{1} - dsi_xx_out_p[6]
Select the polarity of the reset control. Default Value: 0
0x0: NOINV : Not Inverted
0x1: INV : Inverted
Select one of four inputs to serve as the reset control to the block. Default Value: 0
0x0: PIN_RC : pin_rc - port pin multiplexer output
0x1: DSI_RC_0 : dsi_rc[0] - dsi_xx_out_p[4]
0x2: DSI_RC_1 : dsi_rc[1] - dsi_xx_out_p[5]
0x3: DSI_RC_2 : dsi_rc{1} - dsi_xx_out_p[6]
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1009
UDB_PA0_CFG4
18.1.104 UDB_PA0_CFG4
Address = 0x40347010 PA Reset Enable Register Address: 0x40347010 Retention: Retained
Bits
7
6
SW Access
HW Access
Name
5 None None
None [7:3]
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4
3
12
11
None
None
None [15:8]
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
2
1
RW
RW
R
R
RES_OE_E RES_OUT_
N
EN
0
RW
R
RES_IN_E N
10
9
8
18
17
16
26
25
24
Bits
Name
2
RES_OE_EN
1
RES_OUT_EN
0
RES_IN_EN
Description
Enable the selected reset Default Value: 0
0x0: DISABLE : Reset Disabled
0x1: ENABLE : Reset Enabled
Enable the selected reset Default Value: 0
0x0: DISABLE : Reset Disabled
0x1: ENABLE : Reset Enabled
Enable the selected reset Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1010
18.1.104
UDB_PA0_CFG4 (continued)
0x0: DISABLE : Reset Disabled
0x1: ENABLE : Reset Enabled
UDB_PA0_CFG4
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1011
UDB_PA0_CFG5
18.1.105 UDB_PA0_CFG5
Address = 0x40347014 PA Reset Pin Select Register Address: 0x40347014 Retention: Retained
Bits
7
6
SW Access
HW Access
Name
Bits
15
14
SW Access
HW Access
Name
Bits
23
22
SW Access
HW Access
Name
Bits
31
30
SW Access
HW Access
Name
5 None None None [7:3]
13
21
29
4
3
12
11
None
None
None [15:8]
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
2
1
0
RW
R
PIN_SEL [2:0]
10
9
8
18
17
16
26
25
24
Bits 2 : 0
Name PIN_SEL
Description
Select port input to route to reset multiplexer (dsi_xx_input_p[7:0]) Default Value: 0
0x0: PIN0 : dsi_from_port_pin[0]
0x1: PIN1 : dsi_from_port_pin[1]
0x2: PIN2 : dsi_from_port_pin[2]
0x3: PIN3 : dsi_from_port_pin[3]
0x4: PIN4 : dsi_from_port_pin[4]
0x5: PIN5 : dsi_from_port_pin[5]
0x6: PIN6 : dsi_from_port_pin[6]
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1012
18.1.105
UDB_PA0_CFG5 (continued)
0x7: PIN7 : dsi_from_port_pin[7]
UDB_PA0_CFG5
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1013
UDB_PA0_CFG6
18.1.106 UDB_PA0_CFG6
Address = 0x40347018 PA Input Data Sync Control Register - Low Address: 0x40347018 Retention: Retained
Bits SW Access HW Access
Name
7
6
RW
R
IN_SYNC3 [7:6]
Bits
15
14
SW Access
HW Access
Name
Bits
23
22
SW Access
HW Access
Name
Bits
31
30
SW Access
HW Access
Name
5
4
RW
R
IN_SYNC2 [5:4]
3
2
RW
R
IN_SYNC1 [3:2]
13
12
11
10
None
None
None [15:8]
21
20
19
18
None
None
None [23:16]
29
28
27
26
None
None
None [31:24]
Bits 7 : 6
Name IN_SYNC3
5 : 4
IN_SYNC2
Description
Synchronization selection for PA input 3 Default Value: 0
0x0: TRANSPARENT : transparent
0x1: SINGLESYNC : single sync
0x2: DOUBLESYNC : double sync
0x3: RESERVED : reserved
Synchronization selection for PA input 2 Default Value: 0
0x0: TRANSPARENT : transparent
0x1: SINGLESYNC : single sync
1
0
RW
R
IN_SYNC0 [1:0]
9
8
17
16
25
24
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1014
18.1.106 UDB_PA0_CFG6 (continued)
3 : 2
IN_SYNC1
1 : 0
IN_SYNC0
0x2: DOUBLESYNC : double sync
0x3: RESERVED : reserved
Synchronization selection for PA input 1 Default Value: 0
0x0: TRANSPARENT : transparent
0x1: SINGLESYNC : single sync
0x2: DOUBLESYNC : double sync
0x3: RESERVED : reserved
Synchronization selection for PA input 0 Default Value: 0
0x0: TRANSPARENT : transparent
0x1: SINGLESYNC : single sync
0x2: DOUBLESYNC : double sync
0x3: RESERVED : reserved
UDB_PA0_CFG6
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1015
UDB_PA0_CFG7
18.1.107 UDB_PA0_CFG7
Address = 0x4034701C PA Input Data Sync Control Register - High Address: 0x4034701C Retention: Retained
Bits SW Access HW Access
Name
7
6
RW
R
IN_SYNC7 [7:6]
Bits
15
14
SW Access
HW Access
Name
Bits
23
22
SW Access
HW Access
Name
Bits
31
30
SW Access
HW Access
Name
5
4
RW
R
IN_SYNC6 [5:4]
3
2
RW
R
IN_SYNC5 [3:2]
13
12
11
10
None
None
None [15:8]
21
20
19
18
None
None
None [23:16]
29
28
27
26
None
None
None [31:24]
Bits 7 : 6
Name IN_SYNC7
5 : 4
IN_SYNC6
Description
Synchronization selection for PA input 7 Default Value: 0
0x0: TRANSPARENT : transparent
0x1: SINGLESYNC : single sync
0x2: DOUBLESYNC : double sync
0x3: RESERVED : reserved
Synchronization selection for PA input 6 Default Value: 0
0x0: TRANSPARENT : transparent
0x1: SINGLESYNC : single sync
1
0
RW
R
IN_SYNC4 [1:0]
9
8
17
16
25
24
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1016
18.1.107 UDB_PA0_CFG7 (continued)
3 : 2
IN_SYNC5
1 : 0
IN_SYNC4
0x2: DOUBLESYNC : double sync
0x3: RESERVED : reserved
Synchronization selection for PA input 5 Default Value: 0
0x0: TRANSPARENT : transparent
0x1: SINGLESYNC : single sync
0x2: DOUBLESYNC : double sync
0x3: RESERVED : reserved
Synchronization selection for PA input 4 Default Value: 0
0x0: TRANSPARENT : transparent
0x1: SINGLESYNC : single sync
0x2: DOUBLESYNC : double sync
0x3: RESERVED : reserved
UDB_PA0_CFG7
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1017
UDB_PA0_CFG8
18.1.108 UDB_PA0_CFG8
Address = 0x40347020 PA Output Data Sync Control Register - Low Address: 0x40347020 Retention: Retained
Bits SW Access HW Access
Name
7
6
RW
R
OUT_SYNC3 [7:6]
Bits
15
14
SW Access
HW Access
Name
Bits
23
22
SW Access
HW Access
Name
Bits
31
30
SW Access
HW Access
Name
5
4
RW
R
OUT_SYNC2 [5:4]
3
2
RW
R
OUT_SYNC1 [3:2]
13
12
11
10
None
None
None [15:8]
21
20
19
18
None
None
None [23:16]
29
28
27
26
None
None
None [31:24]
Bits 7 : 6
Name OUT_SYNC3
5 : 4
OUT_SYNC2
Description
Synchronization selection for PA output 3 Default Value: 0
0x0: TRANSPARENT : transparent
0x1: SINGLESYNC : single sync
0x2: CLOCK : clock
0x3: CLOCKINV : clock inverted
Synchronization selection for PA output 2 Default Value: 0
0x0: TRANSPARENT : transparent
0x1: SINGLESYNC : single sync
1
0
RW
R
OUT_SYNC0 [1:0]
9
8
17
16
25
24
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1018
18.1.108 UDB_PA0_CFG8 (continued)
3 : 2
OUT_SYNC1
1 : 0
OUT_SYNC0
0x2: CLOCK : clock
0x3: CLOCKINV : clock inverted
Synchronization selection for PA output 1 Default Value: 0
0x0: TRANSPARENT : transparent
0x1: SINGLESYNC : single sync
0x2: CLOCK : clock
0x3: CLOCKINV : clock inverted
Synchronization selection for PA output 0 Default Value: 0
0x0: TRANSPARENT : transparent
0x1: SINGLESYNC : single sync
0x2: CLOCK : clock
0x3: CLOCKINV : clock inverted
UDB_PA0_CFG8
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1019
UDB_PA0_CFG9
18.1.109 UDB_PA0_CFG9
Address = 0x40347024 PA Output Data Sync Control Register - High Address: 0x40347024 Retention: Retained
Bits SW Access HW Access
Name
7
6
RW
R
OUT_SYNC7 [7:6]
Bits
15
14
SW Access
HW Access
Name
Bits
23
22
SW Access
HW Access
Name
Bits
31
30
SW Access
HW Access
Name
5
4
RW
R
OUT_SYNC6 [5:4]
3
2
RW
R
OUT_SYNC5 [3:2]
13
12
11
10
None
None
None [15:8]
21
20
19
18
None
None
None [23:16]
29
28
27
26
None
None
None [31:24]
Bits 7 : 6
Name OUT_SYNC7
5 : 4
OUT_SYNC6
Description
Synchronization selection for PA output 7 Default Value: 0
0x0: TRANSPARENT : transparent
0x1: SINGLESYNC : single sync
0x2: CLOCK : clock
0x3: CLOCKINV : clock inverted
Synchronization selection for PA output 6 Default Value: 0
0x0: TRANSPARENT : transparent
0x1: SINGLESYNC : single sync
1
0
RW
R
OUT_SYNC4 [1:0]
9
8
17
16
25
24
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1020
18.1.109 UDB_PA0_CFG9 (continued)
3 : 2
OUT_SYNC5
1 : 0
OUT_SYNC4
0x2: CLOCK : clock
0x3: CLOCKINV : clock inverted
Synchronization selection for PA output 5 Default Value: 0
0x0: TRANSPARENT : transparent
0x1: SINGLESYNC : single sync
0x2: CLOCK : clock
0x3: CLOCKINV : clock inverted
Synchronization selection for PA output 4 Default Value: 0
0x0: TRANSPARENT : transparent
0x1: SINGLESYNC : single sync
0x2: CLOCK : clock
0x3: CLOCKINV : clock inverted
UDB_PA0_CFG9
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1021
UDB_PA0_CFG10
18.1.110 UDB_PA0_CFG10
Address = 0x40347028 PA Output Data Select Register - Low Address: 0x40347028 Retention: Retained
Bits SW Access HW Access
Name
7
6
RW
R
DATA_SEL3 [7:6]
Bits
15
14
SW Access
HW Access
Name
Bits
23
22
SW Access
HW Access
Name
Bits
31
30
SW Access
HW Access
Name
5
4
RW
R
DATA_SEL2 [5:4]
3
2
RW
R
DATA_SEL1 [3:2]
13
12
11
10
None
None
None [15:8]
21
20
19
18
None
None
None [23:16]
29
28
27
26
None
None
None [31:24]
Bits 7 : 6
Name DATA_SEL3
5 : 4
DATA_SEL2
Description
Data selection for PA output 3 Default Value: 0
0x0: DSI_OUTPUT0 : dsi output 0
0x1: DSI_OUTPUT1 : dsi output 1
0x2: DSI_OUTPUT2 : dsi output 2
0x3: DSI_OUTPUT3 : dsi output 3
Data selection for PA output 2 Default Value: 0
0x0: DSI_OUTPUT0 : dsi output 0
0x1: DSI_OUTPUT1 : dsi output 1
1
0
RW
R
DATA_SEL0 [1:0]
9
8
17
16
25
24
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1022
18.1.110 UDB_PA0_CFG10 (continued)
3 : 2
DATA_SEL1
1 : 0
DATA_SEL0
0x2: DSI_OUTPUT2 : dsi output 2
0x3: DSI_OUTPUT3 : dsi output 3
Data selection for PA output 1 Default Value: 0
0x0: DSI_OUTPUT0 : dsi output 0
0x1: DSI_OUTPUT1 : dsi output 1
0x2: DSI_OUTPUT2 : dsi output 2
0x3: DSI_OUTPUT3 : dsi output 3
Data selection for PA output 0 Default Value: 0
0x0: DSI_OUTPUT0 : dsi output 0
0x1: DSI_OUTPUT1 : dsi output 1
0x2: DSI_OUTPUT2 : dsi output 2
0x3: DSI_OUTPUT3 : dsi output 3
UDB_PA0_CFG10
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1023
UDB_PA0_CFG11
18.1.111 UDB_PA0_CFG11
Address = 0x4034702C PA Output Data Select Register - High Address: 0x4034702C Retention: Retained
Bits SW Access HW Access
Name
7
6
RW
R
DATA_SEL7 [7:6]
Bits
15
14
SW Access
HW Access
Name
Bits
23
22
SW Access
HW Access
Name
Bits
31
30
SW Access
HW Access
Name
5
4
RW
R
DATA_SEL6 [5:4]
3
2
RW
R
DATA_SEL5 [3:2]
13
12
11
10
None
None
None [15:8]
21
20
19
18
None
None
None [23:16]
29
28
27
26
None
None
None [31:24]
Bits 7 : 6
Name DATA_SEL7
5 : 4
DATA_SEL6
Description
Data selection for PA output 7 Default Value: 0
0x0: DSI_OUTPUT4 : dsi output 4
0x1: DSI_OUTPUT5 : dsi output 5
0x2: DSI_OUTPUT6 : dsi output 6
0x3: DSI_OUTPUT7 : dsi output 7
Data selection for PA output 6 Default Value: 0
0x0: DSI_OUTPUT4 : dsi output 4
0x1: DSI_OUTPUT5 : dsi output 5
1
0
RW
R
DATA_SEL4 [1:0]
9
8
17
16
25
24
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1024
18.1.111 UDB_PA0_CFG11 (continued)
3 : 2
DATA_SEL5
1 : 0
DATA_SEL4
0x2: DSI_OUTPUT6 : dsi output 6
0x3: DSI_OUTPUT7 : dsi output 7
Data selection for PA output 5 Default Value: 0
0x0: DSI_OUTPUT4 : dsi output 4
0x1: DSI_OUTPUT5 : dsi output 5
0x2: DSI_OUTPUT6 : dsi output 6
0x3: DSI_OUTPUT7 : dsi output 7
Data selection for PA output 4 Default Value: 0
0x0: DSI_OUTPUT4 : dsi output 4
0x1: DSI_OUTPUT5 : dsi output 5
0x2: DSI_OUTPUT6 : dsi output 6
0x3: DSI_OUTPUT7 : dsi output 7
UDB_PA0_CFG11
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1025
UDB_PA0_CFG12
18.1.112 UDB_PA0_CFG12
Address = 0x40347030 PA OE Select Register - Low Address: 0x40347030 Retention: Retained
Bits SW Access HW Access
Name
7
6
RW
R
OE_SEL3 [7:6]
Bits
15
14
SW Access
HW Access
Name
Bits
23
22
SW Access
HW Access
Name
Bits
31
30
SW Access
HW Access
Name
5
4
RW
R
OE_SEL2 [5:4]
3
2
RW
R
OE_SEL1 [3:2]
13
12
11
10
None
None
None [15:8]
21
20
19
18
None
None
None [23:16]
29
28
27
26
None
None
None [31:24]
Bits 7 : 6
Name OE_SEL3
5 : 4
OE_SEL2
Description
Data selection for PA oe 3 Default Value: 0
0x0: DSI_OE_OUT0 : synchronized dsi oe output 0
0x1: DSI_OE_OUT1 : synchronized dsi oe output 1
0x2: DSI_OE_OUT2 : synchronized dsi oe output 2
0x3: DSI_OE_OUT3 : synchronized dsi oe output 3
Data selection for PA oe 2 Default Value: 0
0x0: DSI_OE_OUT0 : synchronized dsi oe output 0
0x1: DSI_OE_OUT1 : synchronized dsi oe output 1
1
0
RW
R
OE_SEL0 [1:0]
9
8
17
16
25
24
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1026
18.1.112 UDB_PA0_CFG12 (continued)
3 : 2
OE_SEL1
1 : 0
OE_SEL0
0x2: DSI_OE_OUT2 : synchronized dsi oe output 2
0x3: DSI_OE_OUT3 : synchronized dsi oe output 3
Data selection for PA oe 1 Default Value: 0
0x0: DSI_OE_OUT0 : synchronized dsi oe output 0
0x1: DSI_OE_OUT1 : synchronized dsi oe output 1
0x2: DSI_OE_OUT2 : synchronized dsi oe output 2
0x3: DSI_OE_OUT3 : synchronized dsi oe output 3
Data selection for PA oe 0 Default Value: 0
0x0: DSI_OE_OUT0 : synchronized dsi oe output 0
0x1: DSI_OE_OUT1 : synchronized dsi oe output 1
0x2: DSI_OE_OUT2 : synchronized dsi oe output 2
0x3: DSI_OE_OUT3 : synchronized dsi oe output 3
UDB_PA0_CFG12
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1027
UDB_PA0_CFG13
18.1.113 UDB_PA0_CFG13
Address = 0x40347034 PA OE Select Register - High Address: 0x40347034 Retention: Retained
Bits SW Access HW Access
Name
7
6
RW
R
OE_SEL7 [7:6]
Bits
15
14
SW Access
HW Access
Name
Bits
23
22
SW Access
HW Access
Name
Bits
31
30
SW Access
HW Access
Name
5
4
RW
R
OE_SEL6 [5:4]
3
2
RW
R
OE_SEL5 [3:2]
13
12
11
10
None
None
None [15:8]
21
20
19
18
None
None
None [23:16]
29
28
27
26
None
None
None [31:24]
Bits 7 : 6
Name OE_SEL7
5 : 4
OE_SEL6
Description
Data selection for PA oe 7 Default Value: 0
0x0: DSI_OE_OUT0 : synchronized dsi oe output 0
0x1: DSI_OE_OUT1 : synchronized dsi oe output 1
0x2: DSI_OE_OUT2 : synchronized dsi oe output 2
0x3: DSI_OE_OUT3 : synchronized dsi oe output 3
Data selection for PA oe 6 Default Value: 0
0x0: DSI_OE_OUT0 : synchronized dsi oe output 0
0x1: DSI_OE_OUT1 : synchronized dsi oe output 1
1
0
RW
R
OE_SEL4 [1:0]
9
8
17
16
25
24
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1028
18.1.113 UDB_PA0_CFG13 (continued)
3 : 2
OE_SEL5
1 : 0
OE_SEL4
0x2: DSI_OE_OUT2 : synchronized dsi oe output 2
0x3: DSI_OE_OUT3 : synchronized dsi oe output 3
Data selection for PA oe 5 Default Value: 0
0x0: DSI_OE_OUT0 : synchronized dsi oe output 0
0x1: DSI_OE_OUT1 : synchronized dsi oe output 1
0x2: DSI_OE_OUT2 : synchronized dsi oe output 2
0x3: DSI_OE_OUT3 : synchronized dsi oe output 3
Data selection for PA oe 4 Default Value: 0
0x0: DSI_OE_OUT0 : synchronized dsi oe output 0
0x1: DSI_OE_OUT1 : synchronized dsi oe output 1
0x2: DSI_OE_OUT2 : synchronized dsi oe output 2
0x3: DSI_OE_OUT3 : synchronized dsi oe output 3
UDB_PA0_CFG13
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1029
UDB_PA0_CFG14
18.1.114 UDB_PA0_CFG14
Address = 0x40347038 PA OE Sync Register Address: 0x40347038 Retention: Retained
Bits SW Access HW Access
Name
7
6
RW
R
OE_SYNC3 [7:6]
Bits
15
14
SW Access
HW Access
Name
Bits
23
22
SW Access
HW Access
Name
Bits
31
30
SW Access
HW Access
Name
5
4
RW
R
OE_SYNC2 [5:4]
3
2
RW
R
OE_SYNC1 [3:2]
13
12
11
10
None
None
None [15:8]
21
20
19
18
None
None
None [23:16]
29
28
27
26
None
None
None [31:24]
Bits 7 : 6
Name OE_SYNC3
5 : 4
OE_SYNC2
Description
Synchronization options for dsi_to_oe[3] Default Value: 0
0x0: TRANSPARENT : transparent
0x1: SINGLESYNC : single sync
0x2: CONSTANT1 : 1: (Active high OE Enabled)
0x3: CONSTANT0 : 0: (Active high OE Disabled)
Synchronization options for dsi_to_oe[2] Default Value: 0
0x0: TRANSPARENT : transparent
0x1: SINGLESYNC : single sync
1
0
RW
R
OE_SYNC0 [1:0]
9
8
17
16
25
24
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1030
18.1.114 UDB_PA0_CFG14 (continued)
3 : 2
OE_SYNC1
1 : 0
OE_SYNC0
0x2: CONSTANT1 : 1: (Active high OE Enabled)
0x3: CONSTANT0 : 0: (Active high OE Disabled)
Synchronization options for dsi_to_oe[1] Default Value: 0
0x0: TRANSPARENT : transparent
0x1: SINGLESYNC : single sync
0x2: CONSTANT1 : 1: (Active high OE Enabled)
0x3: CONSTANT0 : 0: (Active high OE Disabled)
Synchronization options for dsi_to_oe[0] Default Value: 0
0x0: TRANSPARENT : transparent
0x1: SINGLESYNC : single sync
0x2: CONSTANT1 : 1: (Active high OE Enabled)
0x3: CONSTANT0 : 0: (Active high OE Disabled)
UDB_PA0_CFG14
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1031
UDB_BCTL_MDCLK_EN
18.1.115 UDB_BCTL_MDCLK_EN
Address = 0x40347800 Master Digital Clock Enable Register Address: 0x40347800 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
DCEN [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 0
Name DCEN
Description
Master digital clock enable for the digital clock that matches the index. Default Value: 0
0x0: DISABLE : Disabled
0x1: ENABLE : Enabled
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1032
UDB_BCTL_MBCLK_EN
18.1.116 UDB_BCTL_MBCLK_EN
Address = 0x40347804 Master clk_peri_app Enable Register Address: 0x40347804 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:1]
BCEN
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
BCEN
Description
clk_peri_app master enable Default Value: 0
0x0: DISABLE : Disabled
0x1: ENABLE : Enabled
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1033
UDB_BCTL_BOTSEL_L
18.1.117 UDB_BCTL_BOTSEL_L
Address = 0x40347808 Lower Nibble Bottom Digital Clock Select Register Address: 0x40347808 Retention: Retained
Bits SW Access HW Access
Name
7
6
RW
R
CLK_SEL3 [7:6]
5
4
RW
R
CLK_SEL2 [5:4]
3
2
RW
R
CLK_SEL1 [3:2]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
1
0
RW
R
CLK_SEL0 [1:0]
9
8
17
16
25
24
Bits 7 : 6
Name CLK_SEL3
5 : 4
CLK_SEL2
Description
Clock selection control for digital clock Default Value: 0
0x0: EDGE_ENABLES : clock generated from edge enables from clock distribution block
0x1: PORT_INPUT : Port input
0x2: DSI_OUTPUT : DSI output
0x3: SYNC_DSI_OUTPUT : synchronized DSI output
Clock selection control for digital clock Default Value: 0
0x0: EDGE_ENABLES : clock generated from edge enables from clock distribution block
0x1: PORT_INPUT : Port input
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1034
UDB_BCTL_BOTSEL_L
18.1.117 UDB_BCTL_BOTSEL_L (continued)
3 : 2
CLK_SEL1
1 : 0
CLK_SEL0
0x2: DSI_OUTPUT : DSI output
0x3: SYNC_DSI_OUTPUT : synchronized DSI output
Clock selection control for digital clock Default Value: 0
0x0: EDGE_ENABLES : clock generated from edge enables from clock distribution block
0x1: PORT_INPUT : Port input
0x2: DSI_OUTPUT : DSI output
0x3: SYNC_DSI_OUTPUT : synchronized DSI output
Clock selection control for digital clock Default Value: 0
0x0: EDGE_ENABLES : clock generated from edge enables from clock distribution block
0x1: PORT_INPUT : Port input
0x2: DSI_OUTPUT : DSI output
0x3: SYNC_DSI_OUTPUT : synchronized DSI output
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1035
UDB_BCTL_BOTSEL_U
18.1.118 UDB_BCTL_BOTSEL_U
Address = 0x4034780C Upper Nibble Bottom Digital Clock Select Register Address: 0x4034780C Retention: Retained
Bits SW Access HW Access
Name
7
6
RW
R
CLK_SEL7 [7:6]
5
4
RW
R
CLK_SEL6 [5:4]
3
2
RW
R
CLK_SEL5 [3:2]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
1
0
RW
R
CLK_SEL4 [1:0]
9
8
17
16
25
24
Bits 7 : 6
Name CLK_SEL7
5 : 4
CLK_SEL6
Description
Clock selection control for digital clock Default Value: 0
0x0: EDGE_ENABLES : clock generated from edge enables from clock distribution block
0x1: PORT_INPUT : Port input
0x2: DSI_OUTPUT : DSI output
0x3: SYNC_DSI_OUTPUT : synchronized DSI output
Clock selection control for digital clock Default Value: 0
0x0: EDGE_ENABLES : clock generated from edge enables from clock distribution block
0x1: PORT_INPUT : Port input
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1036
UDB_BCTL_BOTSEL_U
18.1.118 UDB_BCTL_BOTSEL_U (continued)
3 : 2
CLK_SEL5
1 : 0
CLK_SEL4
0x2: DSI_OUTPUT : DSI output
0x3: SYNC_DSI_OUTPUT : synchronized DSI output
Clock selection control for digital clock Default Value: 0
0x0: EDGE_ENABLES : clock generated from edge enables from clock distribution block
0x1: PORT_INPUT : Port input
0x2: DSI_OUTPUT : DSI output
0x3: SYNC_DSI_OUTPUT : synchronized DSI output
Clock selection control for digital clock Default Value: 0
0x0: EDGE_ENABLES : clock generated from edge enables from clock distribution block
0x1: PORT_INPUT : Port input
0x2: DSI_OUTPUT : DSI output
0x3: SYNC_DSI_OUTPUT : synchronized DSI output
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1037
UDB_BCTL_QCLK_EN0
18.1.119 UDB_BCTL_QCLK_EN0
Address = 0x40347810 Quadrant Digital Clock Enable Registers Address: 0x40347810 Retention: Retained
Bits
7
6
5
SW Access
HW Access
Name
Bits
15
SW Access
HW Access
Name
14
13
None
None
None [15:12]
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4
3
RW
R
DCEN_Q [7:0]
12
11
RW
R
DISABLE_ROU
TE
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
2
1
10
9
None
None
None [10:9]
18
17
26
25
0
8 RW R BCEN_Q 16
24
Bits
Name
11
DISABLE_ROUTE
8
BCEN_Q
Description
By default, when this bit is set to '0', the quadrant routing (for 2 channels in the quadrant) are enabled when the global route enable for the bank is set. However, when this bit is set to '1', the routing in the associated quadrant is disabled and is not enabled by the global route enable bit. The routing will remain in a benign state until it is subsequently configured and then enabled by clearing this bit. Default Value: 0
0x0: DISABLE : The routing in this quadrant can be enabled with the bank route enable bit. (default)
0x1: ENABLE : The routing in this quadrant is disabled and held in a benign state.
clk_peri_app quadrant enable Default Value: 0
0x0: DISABLE : clk_peri_app to the quadrant is disabled
0x1: ENABLE : clk_peri_app to the quadrant is enabled
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1038
UDB_BCTL_QCLK_EN0
18.1.119 UDB_BCTL_QCLK_EN0 (continued)
7 : 0
DCEN_Q
Digital clock enable for indexed digital clock for the associated quadrant. Default Value: 0
0x0: DISABLE : Disabled
0x1: ENABLE : Enabled
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1039
UDB_UDBIF_BANK_CTL
18.1.120 UDB_UDBIF_BANK_CTL
Address = 0x40347900 Bank Control Address: 0x40347900 Retention: Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:3]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:9]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2 RW R BANK_EN
1 RW R ROUTE_EN
0 RW R DIS_COR
10
9
8
RW
R
READ_WAI T
18
17
16
26
25
24
Bits
Name
8
READ_WAIT
2
BANK_EN
Description
AHB wait states for read operations. This is required to be set if any of the following conditions are true (substitute 20 MHz for 50 MHz if in ULP mode voltage): 1. clk_sys > 50 MHz 2. Reads from WRKONE/WRKMULT.A0/A1/D0/D1 if those are being clocked on clk_dpath and clk_dpath > 50 MHz. 3. Reads from WRKONE/WRKMULT.CTL when the control register is configured in pulse mode and clk_peri > 50 MHz. 4. Reads from WRKONE/WRKMULT.MC if clk_pld > 50 MHz. Default Value: 1
0x0: ZERO_WAIT_STATES : Zero wait states
0x1: ONE_WAIT_STATE : One wait state
Enable Bank Default Value: 0
0x0: DISABLE : Bank disabled
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1040
UDB_UDBIF_BANK_CTL
18.1.120 UDB_UDBIF_BANK_CTL (continued)
1
ROUTE_EN
0
DIS_COR
0x1: ENABLE : Bank enabled
Enable Routing Default Value: 0
0x0: DISABLE : Routing disabled
0x1: ENABLE : Routing enabled
If Clear-On-Read is enabled it will prevent any changes to the Status registers or FIFOs anywhere in the array as a result of reads. This aids in SW debug. Default Value: 0
0x0: NORMAL : Clear-On-Read enabled
0x1: DISABLE : Clear-On-Read disabled
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1041
UDB_UDBIF_INT_CLK_CTL
18.1.121 UDB_UDBIF_INT_CLK_CTL
Address = 0x40347904 Interrupt Clock Control Address: 0x40347904 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:1]
INT_CLK_EN-
ABLE
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
Description
0
INT_CLK_ENABLE
This bit enables the interrupt synchronizer in the UDB interface. It needs to be set whenever
UDB/DSI interrupts are used. Disabling the interrupt synchronizer saves power in Active/Sleep
mode.
Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1042
UDB_UDBIF_INT_CFG
18.1.122 UDB_UDBIF_INT_CFG
Address = 0x40347908 Interrupt Configuration Address: 0x40347908 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
INT_MODE_CFG [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
INT_MODE_CFG [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 0
Name INT_MODE_CFG
Description
Interrupt Mode; bit position corresponds to interrupt Default Value: 0
0x0: LEVEL : Level
0x1: PULSE : Pulse
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1043
UDB_UDBIF_TR_CLK_CTL
18.1.123 UDB_UDBIF_TR_CLK_CTL
Address = 0x4034790C Trigger Clock Control Address: 0x4034790C Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:1]
TR_CLOCK_EN
ABLE
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
Description
0
TR_CLOCK_ENABLE
This bit enables/disables the clock and reset of the DMA request logic.
Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1044
UDB_UDBIF_TR_CFG
18.1.124 UDB_UDBIF_TR_CFG
Address = 0x40347910 Trigger Configuration Address: 0x40347910 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
TR_MODE_CFG [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
TR_MODE_CFG [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 0
Name TR_MODE_CFG
Description
Trigger Mode Configuration '0' : dsi_tr[i] is tied to udb_tr_out[i] '1' : dsi_tr[i] is synchronized to clk_tr before being sourced to dsi_tr[i] Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1045
UDB_UDBIF_PRIVATE
18.1.125 UDB_UDBIF_PRIVATE
Address = 0x40347914 Internal use only Address: 0x40347914 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:1]
PIPELINE_MD
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
PIPELINE_MD
Description
Implements pipeline stages to breakup timing loops to aid internal design analysis. '0' : Normal functional mode. '1' : Pipeline stages muxed in (not for customer use) Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1046
19 Low-Power Comparator Registers
This section discusses the Low-Power Comparator (LPCOMP) registers. It lists all the registers in mapping tables, in address order.
19.1 Register Details
Register LPCOMP_CONFIG LPCOMP_STATUS LPCOMP_INTR LPCOMP_INTR_SET LPCOMP_INTR_MASK LPCOMP_INTR_MASKED LPCOMP_CMP0_CTRL LPCOMP_CMP0_SW LPCOMP_CMP0_SW_CLEAR LPCOMP_CMP1_CTRL LPCOMP_CMP1_SW LPCOMP_CMP1_SW_CLEAR
Address 0x40350000 0x40350004 0x40350010 0x40350014 0x40350018 0x4035001C 0x40350040 0x40350050 0x40350054 0x40350080 0x40350090 0x40350094
Description LPCOMP Configuration Register LPCOMP Status Register LPCOMP Interrupt request register LPCOMP Interrupt set register LPCOMP Interrupt request mask LPCOMP Interrupt request masked Comparator 0 control Register Comparator 0 switch control Comparator 0 switch control clear Comparator 1 control Register Comparator 1 switch control Comparator 1 switch control clear
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1047
LPCOMP_CONFIG
19.1.1 LPCOMP_CONFIG
Address = 0x40350000 LPCOMP Configuration Register Address: 0x40350000 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
RW
None
HW Access
R
R
None
Name
ENABLED LPREF_EN
None
Bits
Name
31
ENABLED
30
LPREF_EN
Description
- 0: LPCOMP disabled (puts analog in power down, opens all switches, all clocks turned off) - 1: LPCOMP enabled Default Value: 0
Enable the local reference generator circuit to generate the local Vref and Ibias. Ibias current is an alternative to the reference current IREF generated by SRSS. This bit must be set for System Deep Sleep and System Hibernate operation. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1048
LPCOMP_STATUS
19.1.2 LPCOMP_STATUS
Address = 0x40350004 LPCOMP Status Register Address: 0x40350004 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
R
HW Access
None
RW
Name
None [7:1]
OUT0
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
R
HW Access
None
RW
Name
None [23:17]
OUT1
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
16
OUT1
0
OUT0
Description
Current output value of the comparator 1. Default Value: 0
Current output value of the comparator 0. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1049
LPCOMP_INTR
19.1.3 LPCOMP_INTR
Address = 0x40350010 LPCOMP Interrupt request register Address: 0x40350010 Retention: Retained
Bits
7
6
SW Access
HW Access
Name
Bits
15
14
SW Access
HW Access
Name
Bits
23
22
SW Access
HW Access
Name
Bits
31
30
SW Access
HW Access
Name
5
4
3
None
None
None [7:2]
13
12
11
None
None
None [15:8]
21
20
19
None
None
None [23:16]
29
28
27
None
None
None [31:24]
2
1
0
RW1C
RW1C
RW1S
RW1S
COMP1
COMP0
10
9
8
18
17
16
26
25
24
Bits
Name
1
COMP1
0
COMP0
Description
Comparator 1 Interrupt: hardware sets this interrupt when comparator 1 triggers. Write with '1' to clear bit. Default Value: 0
Comparator 0 Interrupt: hardware sets this interrupt when comparator 0 triggers. Write with '1' to clear bit. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1050
LPCOMP_INTR_SET
19.1.4 LPCOMP_INTR_SET
Address = 0x40350014 LPCOMP Interrupt set register Address: 0x40350014 Retention: Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:2]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
0
RW1S
RW1S
A
A
COMP1
COMP0
10
9
8
18
17
16
26
25
24
Bits
Name
1
COMP1
0
COMP0
Description
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1051
LPCOMP_INTR_MASK
19.1.5 LPCOMP_INTR_MASK
Address = 0x40350018 LPCOMP Interrupt request mask Address: 0x40350018 Retention: Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:2]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
0
RW
RW
R
R
COMP1_M COMP0_M
ASK
ASK
10
9
8
18
17
16
26
25
24
Bits
Name
1
COMP1_MASK
0
COMP0_MASK
Description
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1052
LPCOMP_INTR_MASKED
19.1.6 LPCOMP_INTR_MASKED
Address = 0x4035001C LPCOMP Interrupt request masked Address: 0x4035001C Retention: Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:2]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
0
R
R
W
W
COMP1_M COMP0_M
ASKED
ASKED
10
9
8
18
17
16
26
25
24
Bits
Name
1
COMP1_MASKED
0
COMP0_MASKED
Description
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1053
LPCOMP_CMP0_CTRL
19.1.7 LPCOMP_CMP0_CTRL
Address = 0x40350040 Comparator 0 control Register Address: 0x40350040 Retention: Retained
Bits SW Access HW Access
Name
7
6
RW
R
INTTYPE0 [7:6]
5 RW R HYST0
Bits
15
SW Access
HW Access
Name
14
13
None
None
None [15:12]
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4
3
None
None
None [4:2]
12
11
RW
R
DSI_LEVEL0
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
2
10 RW R DSI_BYPASS0 18
26
1
0
RW
R
MODE0 [1:0]
9
8
None
None
None [9:8]
17
16
25
24
Bits
Name
11
DSI_LEVEL0
10
DSI_BYPASS0
7 : 6
INTTYPE0
Description
Synchronous comparator output (trigger): 0=pulse 1=level Default Value: 0
Asynchronous: bypass comparator output synchronization: 0=synchronize (level or pulse) 1=bypass (output async) Note that in System Deep Sleep mode, this bit needs to be set to observe the output on the dedicated pin. Default Value: 0
Sets which edge will trigger an IRQ Default Value: 0
0x0: DISABLE :
Disabled, no interrupts will be detected
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1054
LPCOMP_CMP0_CTRL
19.1.7
LPCOMP_CMP0_CTRL (continued)
0x1: RISING : Rising edge
0x2: FALLING : Falling edge
0x3: BOTH : Both rising and falling edges
5
HYST0
1 : 0
MODE0
Add hysteresis to the comparator 0= Disable Hysteresis 1= Enable Hysteresis Default Value: 0
Operating mode for the comparator Default Value: 0
0x0: OFF :
Off
0x1: ULP :
Ultra low power operating mode. This mode must be used for System Deep Sleep and System Hibernate operation. In this mode, local Ibias is used.
0x2: LP : Low Power operating mode. In this mode, IREF from SRSS is used.
0x3: NORMAL : Normal power, full speed operating mode. In this mode, IREF from SRSS is used.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1055
LPCOMP_CMP0_SW
19.1.8 LPCOMP_CMP0_SW
Address = 0x40350050 Comparator 0 switch control Address: 0x40350050 Retention: Retained
Bits SW Access HW Access
Name
7 RW1S RW1C CMP0_VN0
6 RW1S RW1C CMP0_BN0
5 RW1S RW1C CMP0_AN0
4 RW1S RW1C CMP0_IN0
3 None None None
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
RW1S
RW1S
RW1C
RW1C
CMP0_BP0 CMP0_AP0
0 RW1S RW1C CMP0_IP0
10
9
8
18
17
16
26
25
24
Bits
Name
7
CMP0_VN0
6
CMP0_BN0
5
CMP0_AN0
4
CMP0_IN0
2
CMP0_BP0
1
CMP0_AP0
0
CMP0_IP0
Description
Comparator 0 negative terminal switch to local Vref (LPREF_EN must be set) Default Value: 0
Comparator 0 negative terminal switch to amuxbusB Default Value: 0
Comparator 0 negative terminal switch to amuxbusA Default Value: 0
Comparator 0 negative terminal isolation switch to GPIO Default Value: 0
Comparator 0 positive terminal switch to amuxbusB Default Value: 0
Comparator 0 positive terminal switch to amuxbusA Default Value: 0
Comparator 0 positive terminal isolation switch to GPIO Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1056
LPCOMP_CMP0_SW_CLEAR
19.1.9 LPCOMP_CMP0_SW_CLEAR
Address = 0x40350054 Comparator 0 switch control clear Address: 0x40350054 Retention: Retained
Bits SW Access HW Access
Name
7 RW1C
A CMP0_VN0
6 RW1C
A CMP0_BN0
5 RW1C
A CMP0_AN0
4 RW1C
A CMP0_IN0
3 None None None
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
RW1C
RW1C
A
A
CMP0_BP0 CMP0_AP0
0 RW1C
A CMP0_IP0
10
9
8
18
17
16
26
25
24
Bits
Name
7
CMP0_VN0
6
CMP0_BN0
5
CMP0_AN0
4
CMP0_IN0
2
CMP0_BP0
1
CMP0_AP0
0
CMP0_IP0
Description
see corresponding bit in CMP0_SW Default Value: 0
see corresponding bit in CMP0_SW Default Value: 0
see corresponding bit in CMP0_SW Default Value: 0
see corresponding bit in CMP0_SW Default Value: 0
see corresponding bit in CMP0_SW Default Value: 0
see corresponding bit in CMP0_SW Default Value: 0
see corresponding bit in CMP0_SW Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1057
LPCOMP_CMP1_CTRL
19.1.10 LPCOMP_CMP1_CTRL
Address = 0x40350080 Comparator 1 control Register Address: 0x40350080 Retention: Retained
Bits SW Access HW Access
Name
7
6
RW
R
INTTYPE1 [7:6]
5 RW R HYST1
Bits
15
SW Access
HW Access
Name
14
13
None
None
None [15:12]
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4
3
None
None
None [4:2]
12
11
RW
R
DSI_LEVEL1
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
2
10 RW R DSI_BYPASS1 18
26
1
0
RW
R
MODE1 [1:0]
9
8
None
None
None [9:8]
17
16
25
24
Bits
Name
11
DSI_LEVEL1
10
DSI_BYPASS1
7 : 6
INTTYPE1
Description
Synchronous comparator output (trigger): 0=pulse 1=level Default Value: 0
Asynchronous: bypass comparator output synchronization: 0=synchronize (level or pulse) 1=bypass (output async) Note that in System Deep Sleep mode, this bit needs to be set to observe the output on the dedicated pin. Default Value: 0
Sets which edge will trigger an IRQ Default Value: 0
0x0: DISABLE :
Disabled, no interrupts will be detected
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1058
LPCOMP_CMP1_CTRL
19.1.10
LPCOMP_CMP1_CTRL (continued)
0x1: RISING : Rising edge
0x2: FALLING : Falling edge
0x3: BOTH : Both rising and falling edges
5
HYST1
1 : 0
MODE1
Add hysteresis to the comparator 0= Disable Hysteresis 1= Enable Hysteresis Default Value: 0
Operating mode for the comparator Default Value: 0
0x0: OFF :
Off
0x1: ULP :
Ultra low power operating mode. This mode must be used for System Deep Sleep and System Hibernate operation. In this mode, local Ibias is used.
0x2: LP : Low Power operating mode. In this mode, IREF from SRSS is used.
0x3: NORMAL : Normal power, full speed operating mode. In this mode, IREF from SRSS is used.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1059
LPCOMP_CMP1_SW
19.1.11 LPCOMP_CMP1_SW
Address = 0x40350090 Comparator 1 switch control Address: 0x40350090 Retention: Retained
Bits SW Access HW Access
Name
7 RW1S RW1C CMP1_VN1
6 RW1S RW1C CMP1_BN1
5 RW1S RW1C CMP1_AN1
4 RW1S RW1C CMP1_IN1
3 None None None
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
RW1S
RW1S
RW1C
RW1C
CMP1_BP1 CMP1_AP1
0 RW1S RW1C CMP1_IP1
10
9
8
18
17
16
26
25
24
Bits
Name
7
CMP1_VN1
6
CMP1_BN1
5
CMP1_AN1
4
CMP1_IN1
2
CMP1_BP1
1
CMP1_AP1
0
CMP1_IP1
Description
Comparator 1 negative terminal switch to local Vref (LPREF_EN must be set) Default Value: 0
Comparator 1 negative terminal switch to amuxbusB Default Value: 0
Comparator 1 negative terminal switch to amuxbusA Default Value: 0
Comparator 1 negative terminal isolation switch to GPIO Default Value: 0
Comparator 1 positive terminal switch to amuxbusB Default Value: 0
Comparator 1 positive terminal switch to amuxbusA Default Value: 0
Comparator 1 positive terminal isolation switch to GPIO Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1060
LPCOMP_CMP1_SW_CLEAR
19.1.12 LPCOMP_CMP1_SW_CLEAR
Address = 0x40350094 Comparator 1 switch control clear Address: 0x40350094 Retention: Retained
Bits SW Access HW Access
Name
7 RW1C
A CMP1_VN1
6 RW1C
A CMP1_BN1
5 RW1C
A CMP1_AN1
4 RW1C
A CMP1_IN1
3 None None None
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
RW1C
RW1C
A
A
CMP1_BP1 CMP1_AP1
0 RW1C
A CMP1_IP1
10
9
8
18
17
16
26
25
24
Bits
Name
7
CMP1_VN1
6
CMP1_BN1
5
CMP1_AN1
4
CMP1_IN1
2
CMP1_BP1
1
CMP1_AP1
0
CMP1_IP1
Description
see corresponding bit in CMP1_SW Default Value: 0
see corresponding bit in CMP1_SW Default Value: 0
see corresponding bit in CMP1_SW Default Value: 0
see corresponding bit in CMP1_SW Default Value: 0
see corresponding bit in CMP1_SW Default Value: 0
see corresponding bit in CMP1_SW Default Value: 0
see corresponding bit in CMP1_SW Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1061
20 Timer, Counter, PWM (TCPWM) Registers
This section discusses the Timer, Counter, PWM (TCPWM) registers. It lists all the registers in mapping tables, in address order.
20.1 Register Details
Register TCPWM0_CTRL TCPWM0_CTRL_CLR TCPWM0_CTRL_SET TCPWM0_CMD_CAPTURE TCPWM0_CMD_RELOAD TCPWM0_CMD_STOP TCPWM0_CMD_START TCPWM0_INTR_CAUSE TCPWM0_CNT0_CTRL TCPWM0_CNT0_STATUS TCPWM0_CNT0_COUNTER TCPWM0_CNT0_CC TCPWM0_CNT0_CC_BUFF TCPWM0_CNT0_PERIOD TCPWM0_CNT0_PERIOD_BUFF TCPWM0_CNT0_TR_CTRL0 TCPWM0_CNT0_TR_CTRL1 TCPWM0_CNT0_TR_CTRL2 TCPWM0_CNT0_INTR TCPWM0_CNT0_INTR_SET TCPWM0_CNT0_INTR_MASK TCPWM0_CNT0_INTR_MASKED TCPWM0_CNT1_CTRL TCPWM0_CNT1_STATUS TCPWM0_CNT1_COUNTER TCPWM0_CNT1_CC
TCPWM0_CNT1_CC_BUFF
Address 0x40380000 0x40380004 0x40380008 0x4038000C 0x40380010 0x40380014 0x40380018 0x4038001C 0x40380100 0x40380104 0x40380108 0x4038010C 0x40380110 0x40380114 0x40380118 0x40380120 0x40380124 0x40380128 0x40380130 0x40380134 0x40380138 0x4038013C 0x40380140 0x40380144 0x40380148 0x4038014C
0x40380150
Description TCPWM control register TCPWM control clear register TCPWM control set register TCPWM capture command register TCPWM reload command register TCPWM stop command register TCPWM start command register TCPWM Counter interrupt cause register Counter control register Counter status register Counter count register Counter compare/capture register Counter buffered compare/capture register Counter period register Counter buffered period register Counter trigger control register 0 Counter trigger control register 1 Counter trigger control register 2 Interrupt request register Interrupt set request register Interrupt mask register Interrupt masked request register Counter control register. See TCPWM0_CNT0_CTRL for the details of bit fields. Counter status register. See TCPWM0_CNT0_STATUS for the details of bit fields. Counter count register. See TCPWM0_CNT0_COUNTER for the details of bit fields. Counter compare/capture register. See TCPWM0_CNT0_CCfor the details of bit fields. Counter buffered compare/capture register. See TCPWM0_CNT0_CC_BUFFfor the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1062
Timer, Counter, PWM (TCPWM) Registers
Register TCPWM0_CNT1_PERIOD TCPWM0_CNT1_PERIOD_BUFF TCPWM0_CNT1_TR_CTRL0 TCPWM0_CNT1_TR_CTRL1 TCPWM0_CNT1_TR_CTRL2 TCPWM0_CNT1_INTR TCPWM0_CNT1_INTR_SET TCPWM0_CNT1_INTR_MASK TCPWM0_CNT1_INTR_MASKED TCPWM0_CNT2_CTRL TCPWM0_CNT2_STATUS TCPWM0_CNT2_COUNTER TCPWM0_CNT2_CC TCPWM0_CNT2_CC_BUFF TCPWM0_CNT2_PERIOD TCPWM0_CNT2_PERIOD_BUF F TCPWM0_CNT2_TR_CTRL0 TCPWM0_CNT2_TR_CTRL1 TCPWM0_CNT2_TR_CTRL2 TCPWM0_CNT2_INTR TCPWM0_CNT2_INTR_SET TCPWM0_CNT2_INTR_MASK TCPWM0_CNT2_INTR_MASKED TCPWM0_CNT3_CTRL TCPWM0_CNT3_STATUS TCPWM0_CNT3_COUNTER TCPWM0_CNT3_CC TCPWM0_CNT3_CC_BUFF TCPWM0_CNT3_PERIOD
Address 0x40380154 0x40380158 0x40380160 0x40380164 0x40380168 0x40380170 0x40380174 0x40380178 0x4038017C 0x40380180 0x40380184 0x40380188 0x4038018C 0x40380190 0x40380194 0x40380198 0x403801A0 0x403801A4 0x403801A8 0x403801B0 0x403801B4 0x403801B8 0x403801BC 0x403801C0 0x403801C4 0x403801C8 0x403801CC 0x403801D0 0x403801D4
Description Counter period register. See TCPWM0_CNT0_PERIODfor the details of bit fields. Counter buffered period register. See TCPWM0_CNT0_PERIOD_BUFFfor the details of bit fields. Counter trigger control register 0. See TCPWM0_CNT0_TR_CTRL0 for the details of bit fields.
Counter trigger control register 1. See TCPWM0_CNT0_TR_CTRL1 for the details of bit fields.
Counter trigger control register 2. See TCPWM0_CNT0_TR_CTRL2 for the details of bit fields.
Interrupt request register. See TCPWM0_CNT0_INTRfor the details of bit fields.
Interrupt set request register. See TCPWM0_CNT0_INTR_SETfor the details of bit fields.
Interrupt mask register. See TCPWM0_CNT0_INTR_MASKfor the details of bit fields. Interrupt masked request register. See TCPWM0_CNT0_INTR_MASKED for the details of bit fields. Counter control register. See TCPWM0_CNT0_CTRL for the details of bit fields.
Counter status register. See TCPWM0_CNT0_STATUS for the details of bit fields.
Counter count register. See TCPWM0_CNT0_COUNTER for the details of bit fields.
Counter compare/capture register. See TCPWM0_CNT0_CC for the details of bit fields. Counter buffered compare/capture register. See TCPWM0_CNT0_CC_BUFFfor the details of bit fields. Counter period register. See TCPWM0_CNT0_PERIOD for the details of bit fields. Counter buffered period register. See TCPWM0_CNT0_PERIOD_BUFF for the details of bit fields. Counter trigger control register 0. See TCPWM0_CNT0_TR_CTRL0 for the details of bit fields.
Counter trigger control register 1. See TCPWM0_CNT0_TR_CTRL1 for the details of bit fields.
Counter trigger control register 2. See TCPWM0_CNT0_TR_CTRL2 for the details of bit fields.
Interrupt request register. See TCPWM0_CNT0_INTR for the details of bit fields.
Interrupt set request register. See TCPWM0_CNT0_INTR_SETfor the details of bit fields.
Interrupt mask register. See TCPWM0_CNT0_INTR_MASK for the details of bit fields. Interrupt masked request register. See TCPWM0_CNT0_INTR_MASKEDfor the details of bit fields. Counter control register. See TCPWM0_CNT0_CTRL for the details of bit fields.
Counter status register. See TCPWM0_CNT0_STATUS for the details of bit fields.
Counter count register. See TCPWM0_CNT0_COUNTER for the details of bit fields.
Counter compare/capture register. See TCPWM0_CNT0_CCfor the details of bit fields. Counter buffered compare/capture register. See TCPWM0_CNT0_CC_BUFFfor the details of bit fields. Counter period register. See TCPWM0_CNT0_PERIODfor the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1063
Timer, Counter, PWM (TCPWM) Registers
Register TCPWM0_CNT3_PERIOD_BUFF TCPWM0_CNT3_TR_CTRL0 TCPWM0_CNT3_TR_CTRL1 TCPWM0_CNT3_TR_CTRL2 TCPWM0_CNT3_INTR TCPWM0_CNT3_INTR_SET TCPWM0_CNT3_INTR_MASK TCPWM0_CNT3_INTR_MASKED TCPWM0_CNT4_CTRL TCPWM0_CNT4_STATUS TCPWM0_CNT4_COUNTER TCPWM0_CNT4_CC TCPWM0_CNT4_CC_BUFF TCPWM0_CNT4_PERIOD TCPWM0_CNT4_PERIOD_BUFF TCPWM0_CNT4_TR_CTRL0 TCPWM0_CNT4_TR_CTRL1 TCPWM0_CNT4_TR_CTRL2 TCPWM0_CNT4_INTR TCPWM0_CNT4_INTR_SET TCPWM0_CNT4_INTR_MASK TCPWM0_CNT4_INTR_MASKED TCPWM0_CNT5_CTRL TCPWM0_CNT5_STATUS TCPWM0_CNT5_COUNTER TCPWM0_CNT5_CC TCPWM0_CNT5_CC_BUFF TCPWM0_CNT5_PERIOD TCPWM0_CNT5_PERIOD_BUFF
Address 0x403801D8 0x403801E0 0x403801E4 0x403801E8 0x403801F0 0x403801F4 0x403801F8 0x403801FC 0x40380200 0x40380204 0x40380208 0x4038020C 0x40380210 0x40380214 0x40380218 0x40380220 0x40380224 0x40380228 0x40380230 0x40380234 0x40380238 0x4038023C 0x40380240 0x40380244 0x40380248 0x4038024C 0x40380250 0x40380254 0x40380258
Description Counter buffered period register. See TCPWM0_CNT0_PERIOD_BUFFfor the details of bit fields. Counter trigger control register 0. See TCPWM0_CNT0_TR_CTRL0 for the details of bit fields.
Counter trigger control register 1. See TCPWM0_CNT0_TR_CTRL1 for the details of bit fields.
Counter trigger control register 2. See TCPWM0_CNT0_TR_CTRL2 for the details of bit fields.
Interrupt request register. See TCPWM0_CNT0_INTRfor the details of bit fields.
Interrupt set request register. See TCPWM0_CNT0_INTR_SETfor the details of bit fields.
Interrupt mask register. See TCPWM0_CNT0_INTR_MASKfor the details of bit fields. Interrupt masked request register. See TCPWM0_CNT0_INTR_MASKEDfor the details of bit fields. Counter control register. See TCPWM0_CNT0_CTRL for the details of bit fields.
Counter status register. See TCPWM0_CNT0_STATUS for the details of bit fields.
Counter count register. See TCPWM0_CNT0_COUNTER for the details of bit fields.
Counter compare/capture register. See TCPWM0_CNT0_CCfor the details of bit fields. Counter buffered compare/capture register. See TCPWM0_CNT0_CC_BUFFfor the details of bit fields. Counter period register. See TCPWM0_CNT0_PERIODfor the details of bit fields. Counter buffered period register. See TCPWM0_CNT0_PERIOD_BUFFfor the details of bit fields. Counter trigger control register 0. See TCPWM0_CNT0_TR_CTRL0 for the details of bit fields.
Counter trigger control register 1. See TCPWM0_CNT0_TR_CTRL1 for the details of bit fields.
Counter trigger control register 2. See TCPWM0_CNT0_TR_CTRL2 for the details of bit fields.
Interrupt request register. See TCPWM0_CNT0_INTRfor the details of bit fields.
Interrupt set request register. See TCPWM0_CNT0_INTR_SETfor the details of bit fields.
Interrupt mask register. See TCPWM0_CNT0_INTR_MASKfor the details of bit fields. Interrupt masked request register. See TCPWM0_CNT0_INTR_MASKEDfor the details of bit fields. Counter control register. See TCPWM0_CNT0_CTRL for the details of bit fields.
Counter status register. See TCPWM0_CNT0_STATUS for the details of bit fields.
Counter count register. See TCPWM0_CNT0_COUNTER for the details of bit fields.
Counter compare/capture register. See TCPWM0_CNT0_CCfor the details of bit fields. Counter buffered compare/capture register. See TCPWM0_CNT0_CC_BUFFfor the details of bit fields. Counter period register. See TCPWM0_CNT0_PERIODfor the details of bit fields. Counter buffered period register. See TCPWM0_CNT0_PERIOD_BUFFfor the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1064
Timer, Counter, PWM (TCPWM) Registers
Register TCPWM0_CNT5_TR_CTRL0 TCPWM0_CNT5_TR_CTRL1 TCPWM0_CNT5_TR_CTRL2 TCPWM0_CNT5_INTR TCPWM0_CNT5_INTR_SET TCPWM0_CNT5_INTR_MASK TCPWM0_CNT5_INTR_MASKED TCPWM0_CNT6_CTRL TCPWM0_CNT6_STATUS TCPWM0_CNT6_COUNTER TCPWM0_CNT6_CC TCPWM0_CNT6_CC_BUFF TCPWM0_CNT6_PERIOD TCPWM0_CNT6_PERIOD_BUFF TCPWM0_CNT6_TR_CTRL0 TCPWM0_CNT6_TR_CTRL1 TCPWM0_CNT6_TR_CTRL2 TCPWM0_CNT6_INTR TCPWM0_CNT6_INTR_SET TCPWM0_CNT6_INTR_MASK TCPWM0_CNT6_INTR_MASKED TCPWM0_CNT7_CTRL TCPWM0_CNT7_STATUS TCPWM0_CNT7_COUNTER TCPWM0_CNT7_CC TCPWM0_CNT7_CC_BUFF TCPWM0_CNT7_PERIOD TCPWM0_CNT7_PERIOD_BUFF TCPWM0_CNT7_TR_CTRL0
Address 0x40380260 0x40380264 0x40380268 0x40380270 0x40380274 0x40380278 0x4038027C 0x40380280 0x40380284 0x40380288 0x4038028C 0x40380290 0x40380294 0x40380298 0x403802A0 0x403802A4 0x403802A8 0x403802B0 0x403802B4 0x403802B8 0x403802BC 0x403802C0 0x403802C4 0x403802C8 0x403802CC 0x403802D0 0x403802D4 0x403802D8 0x403802E0
Description Counter trigger control register 0. See TCPWM0_CNT0_TR_CTRL0 for the details of bit fields.
Counter trigger control register 1. See TCPWM0_CNT0_TR_CTRL1 for the details of bit fields.
Counter trigger control register 2. See TCPWM0_CNT0_TR_CTRL2 for the details of bit fields.
Interrupt request register. See TCPWM0_CNT0_INTRfor the details of bit fields.
Interrupt set request register. See TCPWM0_CNT0_INTR_SETfor the details of bit fields.
Interrupt mask register. See TCPWM0_CNT0_INTR_MASKfor the details of bit fields. Interrupt masked request register. See TCPWM0_CNT0_INTR_MASKEDfor the details of bit fields. Counter control register. See TCPWM0_CNT0_CTRL for the details of bit fields.
Counter status register. See TCPWM0_CNT0_STATUS for the details of bit fields.
Counter count register. See TCPWM0_CNT0_COUNTER for the details of bit fields.
Counter compare/capture register. See TCPWM0_CNT0_CCfor the details of bit fields. Counter buffered compare/capture register. See TCPWM0_CNT0_CC_BUFFfor the details of bit fields. Counter period register. See TCPWM0_CNT0_PERIODfor the details of bit fields. Counter buffered period register. See TCPWM0_CNT0_PERIOD_BUFFfor the details of bit fields. Counter trigger control register 0. See TCPWM0_CNT0_TR_CTRL0 for the details of bit fields.
Counter trigger control register 1. See TCPWM0_CNT0_TR_CTRL1 for the details of bit fields.
Counter trigger control register 2. See TCPWM0_CNT0_TR_CTRL2 for the details of bit fields.
Interrupt request register. See TCPWM0_CNT0_INTRfor the details of bit fields.
Interrupt set request register. See TCPWM0_CNT0_INTR_SETfor the details of bit fields.
Interrupt mask register. See TCPWM0_CNT0_INTR_MASKfor the details of bit fields. Interrupt masked request register. See TCPWM0_CNT0_INTR_MASKEDfor the details of bit fields. Counter control register. See TCPWM0_CNT0_CTRL for the details of bit fields.
Counter status register. See TCPWM0_CNT0_STATUS for the details of bit fields.
Counter count register. See TCPWM0_CNT0_COUNTER for the details of bit fields.
Counter compare/capture register. See TCPWM0_CNT0_CCfor the details of bit fields. Counter buffered compare/capture register. See TCPWM0_CNT0_CC_BUFFfor the details of bit fields. Counter period register. See TCPWM0_CNT0_PERIODfor the details of bit fields. Counter buffered period register. See TCPWM0_CNT0_PERIOD_BUFFfor the details of bit fields. Counter trigger control register 0. See TCPWM0_CNT0_TR_CTRL0 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1065
Timer, Counter, PWM (TCPWM) Registers
Register TCPWM0_CNT7_TR_CTRL1 TCPWM0_CNT7_TR_CTRL2 TCPWM0_CNT7_INTR TCPWM0_CNT7_INTR_SET TCPWM0_CNT7_INTR_MASK TCPWM0_CNT7_INTR_MASKED TCPWM1_CTRL TCPWM1_CTRL_CLR TCPWM1_CTRL_SET TCPWM1_CMD_CAPTURE TCPWM1_CMD_RELOAD TCPWM1_CMD_STOP TCPWM1_CMD_START TCPWM1_INTR_CAUSE TCPWM1_CNT0_CTRL TCPWM1_CNT0_STATUS TCPWM1_CNT0_COUNTER TCPWM1_CNT0_CC TCPWM1_CNT0_CC_BUFF TCPWM1_CNT0_PERIOD TCPWM1_CNT0_PERIOD_BUFF TCPWM1_CNT0_TR_CTRL0 TCPWM1_CNT0_TR_CTRL1 TCPWM1_CNT0_TR_CTRL2 TCPWM1_CNT0_INTR TCPWM1_CNT0_INTR_SET TCPWM1_CNT0_INTR_MASK TCPWM1_CNT0_INTR_MASKED TCPWM1_CNT1_CTRL
Address 0x403802E4 0x403802E8 0x403802F0 0x403802F4 0x403802F8 0x403802FC 0x40390000 0x40390004 0x40390008 0x4039000C 0x40390010 0x40390014 0x40390018 0x4039001C 0x40390100 0x40390104 0x40390108 0x4039010C 0x40390110 0x40390114 0x40390118 0x40390120 0x40390124 0x40390128 0x40390130 0x40390134 0x40390138 0x4039013C 0x40390140
Description Counter trigger control register 1. See TCPWM0_CNT0_TR_CTRL1 for the details of bit fields. Counter trigger control register 2. See TCPWM0_CNT0_TR_CTRL2 for the details of bit fields. Interrupt request register. See TCPWM0_CNT0_INTRfor the details of bit fields. Interrupt set request register. See TCPWM0_CNT0_INTR_SETfor the details of bit fields. Interrupt mask register. See TCPWM0_CNT0_INTR_MASKfor the details of bit fields. Interrupt masked request register. See TCPWM0_CNT0_INTR_MASKED for the details of bit fields. TCPWM control register TCPWM control clear register TCPWM control set register TCPWM capture command register TCPWM reload command register TCPWM stop command register TCPWM start command register TCPWM Counter interrupt cause register Counter control register. See TCPWM0_CNT0_CTRL for the details of bit fields. Counter status register. See TCPWM0_CNT0_STATUS for the details of bit fields. Counter count register Counter compare/capture register Counter buffered compare/capture register Counter period register Counter buffered period register Counter trigger control register 0. See TCPWM0_CNT0_TR_CTRL0 for the details of bit fields. Counter trigger control register 1. See TCPWM0_CNT0_TR_CTRL1 for the details of bit fields. Counter trigger control register 2. See TCPWM0_CNT0_TR_CTRL2 for the details of bit fields. Interrupt request register. See TCPWM0_CNT0_INTRfor the details of bit fields. Interrupt set request register. See TCPWM0_CNT0_INTR_SETfor the details of bit fields. Interrupt mask register. See TCPWM0_CNT0_INTR_MASKfor the details of bit fields. Interrupt masked request register. See TCPWM0_CNT0_INTR_MASKEDfor the details of bit fields. Counter control register. See TCPWM0_CNT0_CTRL for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1066
Timer, Counter, PWM (TCPWM) Registers
Register TCPWM1_CNT1_STATUS TCPWM1_CNT1_COUNTER TCPWM1_CNT1_CC TCPWM1_CNT1_CC_BUFF TCPWM1_CNT1_PERIOD TCPWM1_CNT1_PERIOD_BUFF TCPWM1_CNT1_TR_CTRL0 TCPWM1_CNT1_TR_CTRL1 TCPWM1_CNT1_TR_CTRL2 TCPWM1_CNT1_INTR TCPWM1_CNT1_INTR_SET TCPWM1_CNT1_INTR_MASK TCPWM1_CNT1_INTR_MASKED TCPWM1_CNT2_CTRL TCPWM1_CNT2_STATUS TCPWM1_CNT2_COUNTER TCPWM1_CNT2_CC TCPWM1_CNT2_CC_BUFF TCPWM1_CNT2_PERIOD TCPWM1_CNT2_PERIOD_BUFF TCPWM1_CNT2_TR_CTRL0 TCPWM1_CNT2_TR_CTRL1 TCPWM1_CNT2_TR_CTRL2 TCPWM1_CNT2_INTR TCPWM1_CNT2_INTR_SET TCPWM1_CNT2_INTR_MASK TCPWM1_CNT2_INTR_MASKED TCPWM1_CNT3_CTRL TCPWM1_CNT3_STATUS
Address 0x40390144 0x40390148 0x4039014C 0x40390150 0x40390154 0x40390158 0x40390160 0x40390164 0x40390168 0x40390170 0x40390174 0x40390178 0x4039017C 0x40390180 0x40390184 0x40390188 0x4039018C 0x40390190 0x40390194 0x40390198 0x403901A0 0x403901A4 0x403901A8 0x403901B0 0x403901B4 0x403901B8 0x403901BC 0x403901C0 0x403901C4
Description Counter status register. See TCPWM0_CNT0_STATUS for the details of bit fields.
Counter count register. See TCPWM1_CNT0_COUNTER for the details of bit fields.
Counter compare/capture register. See TCPWM1_CNT0_CCfor the details of bit fields. Counter buffered compare/capture register. See TCPWM1_CNT0_CC_BUFFfor the details of bit fields. Counter period register. See TCPWM1_CNT0_PERIODfor the details of bit fields. Counter buffered period register. See TCPWM1_CNT0_PERIOD_BUFFfor the details of bit fields. Counter trigger control register 0. See TCPWM0_CNT0_TR_CTRL0 for the details of bit fields.
Counter trigger control register 1. See TCPWM0_CNT0_TR_CTRL1 for the details of bit fields.
Counter trigger control register 2. See TCPWM0_CNT0_TR_CTRL2 for the details of bit fields.
Interrupt request register. See TCPWM0_CNT0_INTRfor the details of bit fields.
Interrupt set request register. See TCPWM0_CNT0_INTR_SETfor the details of bit fields.
Interrupt mask register. See TCPWM0_CNT0_INTR_MASKfor the details of bit fields. Interrupt masked request register. See TCPWM0_CNT0_INTR_MASKED for the details of bit fields. Counter control register. See TCPWM0_CNT0_CTRL for the details of bit fields.
Counter status register. See TCPWM0_CNT0_STATUS for the details of bit fields.
Counter count register. See TCPWM1_CNT0_COUNTER for the details of bit fields.
Counter compare/capture register. See TCPWM1_CNT0_CCfor the details of bit fields. Counter buffered compare/capture register. See TCPWM1_CNT0_CC_BUFFfor the details of bit fields. Counter period register. See TCPWM1_CNT0_PERIODfor the details of bit fields. Counter buffered period register. See TCPWM1_CNT0_PERIOD_BUFFfor the details of bit fields. Counter trigger control register 0. See TCPWM0_CNT0_TR_CTRL0 for the details of bit fields.
Counter trigger control register 1. See TCPWM0_CNT0_TR_CTRL1 for the details of bit fields.
Counter trigger control register 2. See TCPWM0_CNT0_TR_CTRL2 for the details of bit fields.
Interrupt request register. See TCPWM0_CNT0_INTR for the details of bit fields.
Interrupt set request register. See TCPWM0_CNT0_INTR_SET for the details of bit fields.
Interrupt mask register. See TCPWM0_CNT0_INTR_MASK for the details of bit fields. Interrupt masked request register. See TCPWM0_CNT0_INTR_MASKEDfor the details of bit fields. Counter control register. See TCPWM0_CNT0_CTRL for the details of bit fields.
Counter status register. See TCPWM0_CNT0_STATUS for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1067
Timer, Counter, PWM (TCPWM) Registers
Register TCPWM1_CNT3_COUNTER TCPWM1_CNT3_CC TCPWM1_CNT3_CC_BUFF TCPWM1_CNT3_PERIOD TCPWM1_CNT3_PERIOD_BUFF TCPWM1_CNT3_TR_CTRL0 TCPWM1_CNT3_TR_CTRL1 TCPWM1_CNT3_TR_CTRL2 TCPWM1_CNT3_INTR TCPWM1_CNT3_INTR_SET TCPWM1_CNT3_INTR_MASK TCPWM1_CNT3_INTR_MASKED TCPWM1_CNT4_CTRL TCPWM1_CNT4_STATUS TCPWM1_CNT4_COUNTER TCPWM1_CNT4_CC TCPWM1_CNT4_CC_BUFF TCPWM1_CNT4_PERIOD TCPWM1_CNT4_PERIOD_BUFF TCPWM1_CNT4_TR_CTRL0 TCPWM1_CNT4_TR_CTRL1 TCPWM1_CNT4_TR_CTRL2 TCPWM1_CNT4_INTR TCPWM1_CNT4_INTR_SET TCPWM1_CNT4_INTR_MASK TCPWM1_CNT4_INTR_MASKED TCPWM1_CNT5_CTRL TCPWM1_CNT5_STATUS TCPWM1_CNT5_COUNTER
Address 0x403901C8 0x403901CC 0x403901D0 0x403901D4 0x403901D8 0x403901E0 0x403901E4 0x403901E8 0x403901F0 0x403901F4 0x403901F8 0x403901FC 0x40390200 0x40390204 0x40390208 0x4039020C 0x40390210 0x40390214 0x40390218 0x40390220 0x40390224 0x40390228 0x40390230 0x40390234 0x40390238 0x4039023C 0x40390240 0x40390244 0x40390248
Description Counter count register. See TCPWM1_CNT0_COUNTER for the details of bit fields.
Counter compare/capture register. See TCPWM1_CNT0_CCfor the details of bit fields. Counter buffered compare/capture register. See TCPWM1_CNT0_CC_BUFFfor the details of bit fields. Counter period register. See TCPWM1_CNT0_PERIODfor the details of bit fields. Counter buffered period register. See TCPWM1_CNT0_PERIOD_BUFFfor the details of bit fields. Counter trigger control register 0. See TCPWM0_CNT0_TR_CTRL0 for the details of bit fields.
Counter trigger control register 1. See TCPWM0_CNT0_TR_CTRL1 for the details of bit fields.
Counter trigger control register 2. See TCPWM0_CNT0_TR_CTRL2 for the details of bit fields.
Interrupt request register. See TCPWM0_CNT0_INTRfor the details of bit fields.
Interrupt set request register. See TCPWM0_CNT0_INTR_SETfor the details of bit fields.
Interrupt mask register. See TCPWM0_CNT0_INTR_MASKfor the details of bit fields. Interrupt masked request register. See TCPWM0_CNT0_INTR_MASKED for the details of bit fields. Counter control register. See TCPWM0_CNT0_CTRL for the details of bit fields.
Counter status register. See TCPWM0_CNT0_STATUS for the details of bit fields.
Counter count register. See TCPWM1_CNT0_COUNTER for the details of bit fields.
Counter compare/capture register. See TCPWM1_CNT0_CCfor the details of bit fields. Counter buffered compare/capture register. See TCPWM1_CNT0_CC_BUFFfor the details of bit fields. Counter period register. See TCPWM1_CNT0_PERIODfor the details of bit fields. Counter buffered period register. See TCPWM1_CNT0_PERIOD_BUFFfor the details of bit fields. Counter trigger control register 0. See TCPWM0_CNT0_TR_CTRL0 for the details of bit fields.
Counter trigger control register 1. See TCPWM0_CNT0_TR_CTRL1 for the details of bit fields.
Counter trigger control register 2. See TCPWM0_CNT0_TR_CTRL2 for the details of bit fields.
Interrupt request register. See TCPWM0_CNT0_INTRfor the details of bit fields.
Interrupt set request register. See TCPWM0_CNT0_INTR_SETfor the details of bit fields.
Interrupt mask register. See TCPWM0_CNT0_INTR_MASKfor the details of bit fields. Interrupt masked request register. See TCPWM0_CNT0_INTR_MASKEDfor the details of bit fields. Counter control register. See TCPWM0_CNT0_CTRL for the details of bit fields.
Counter status register. See TCPWM0_CNT0_STATUS for the details of bit fields.
Counter count register. See TCPWM1_CNT0_COUNTER for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1068
Timer, Counter, PWM (TCPWM) Registers
Register TCPWM1_CNT5_CC TCPWM1_CNT5_CC_BUFF TCPWM1_CNT5_PERIOD TCPWM1_CNT5_PERIOD_BUFF TCPWM1_CNT5_TR_CTRL0 TCPWM1_CNT5_TR_CTRL1 TCPWM1_CNT5_TR_CTRL2 TCPWM1_CNT5_INTR TCPWM1_CNT5_INTR_SET TCPWM1_CNT5_INTR_MASK TCPWM1_CNT5_INTR_MASKED TCPWM1_CNT6_CTRL TCPWM1_CNT6_STATUS TCPWM1_CNT6_COUNTER TCPWM1_CNT6_CC TCPWM1_CNT6_CC_BUFF TCPWM1_CNT6_PERIOD TCPWM1_CNT6_PERIOD_BUFF TCPWM1_CNT6_TR_CTRL0 TCPWM1_CNT6_TR_CTRL1 TCPWM1_CNT6_TR_CTRL2 TCPWM1_CNT6_INTR TCPWM1_CNT6_INTR_SET TCPWM1_CNT6_INTR_MASK TCPWM1_CNT6_INTR_MASKED TCPWM1_CNT7_CTRL TCPWM1_CNT7_STATUS TCPWM1_CNT7_COUNTER TCPWM1_CNT7_CC
Address 0x4039024C 0x40390250 0x40390254 0x40390258 0x40390260 0x40390264 0x40390268 0x40390270 0x40390274 0x40390278 0x4039027C 0x40390280 0x40390284 0x40390288 0x4039028C 0x40390290 0x40390294 0x40390298 0x403902A0 0x403902A4 0x403902A8 0x403902B0 0x403902B4 0x403902B8 0x403902BC 0x403902C0 0x403902C4 0x403902C8 0x403902CC
Description Counter compare/capture register. See TCPWM1_CNT0_CCfor the details of bit fields. Counter buffered compare/capture register. See TCPWM1_CNT0_CC_BUFFfor the details of bit fields. Counter period register. See TCPWM1_CNT0_PERIODfor the details of bit fields. Counter buffered period register. See TCPWM1_CNT0_PERIOD_BUFFfor the details of bit fields. Counter trigger control register 0. See TCPWM0_CNT0_TR_CTRL0 for the details of bit fields.
Counter trigger control register 1. See TCPWM0_CNT0_TR_CTRL1 for the details of bit fields.
Counter trigger control register 2. See TCPWM0_CNT0_TR_CTRL2 for the details of bit fields.
Interrupt request register. See TCPWM0_CNT0_INTRfor the details of bit fields.
Interrupt set request register. See TCPWM0_CNT0_INTR_SETfor the details of bit fields.
Interrupt mask register. See TCPWM0_CNT0_INTR_MASKfor the details of bit fields. Interrupt masked request register. See TCPWM0_CNT0_INTR_MASKEDfor the details of bit fields. Counter control register. See TCPWM0_CNT0_CTRL for the details of bit fields.
Counter status register. See TCPWM0_CNT0_STATUS for the details of bit fields.
Counter count register. See TCPWM1_CNT0_COUNTER for the details of bit fields.
Counter compare/capture register. See TCPWM1_CNT0_CCfor the details of bit fields. Counter buffered compare/capture register. See TCPWM1_CNT0_CC_BUFFfor the details of bit fields. Counter period register. See TCPWM1_CNT0_PERIODfor the details of bit fields. Counter buffered period register. See TCPWM1_CNT0_PERIOD_BUFFfor the details of bit fields. Counter trigger control register 0. See TCPWM0_CNT0_TR_CTRL0 for the details of bit fields.
Counter trigger control register 1. See TCPWM0_CNT0_TR_CTRL1 for the details of bit fields.
Counter trigger control register 2. See TCPWM0_CNT0_TR_CTRL2 for the details of bit fields.
Interrupt request register. See TCPWM0_CNT0_INTRfor the details of bit fields.
Interrupt set request register. See TCPWM0_CNT0_INTR_SETfor the details of bit fields.
Interrupt mask register. See TCPWM0_CNT0_INTR_MASKfor the details of bit fields. Interrupt masked request register. See TCPWM0_CNT0_INTR_MASKEDfor the details of bit fields. Counter control register. See TCPWM0_CNT0_CTRL for the details of bit fields.
Counter status register. See TCPWM0_CNT0_STATUS for the details of bit fields.
Counter count register. See TCPWM1_CNT0_COUNTER for the details of bit fields.
Counter compare/capture register. See TCPWM1_CNT0_CCfor the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1069
Timer, Counter, PWM (TCPWM) Registers
Register TCPWM1_CNT7_CC_BUFF TCPWM1_CNT7_PERIOD TCPWM1_CNT7_PERIOD_BUFF TCPWM1_CNT7_TR_CTRL0 TCPWM1_CNT7_TR_CTRL1 TCPWM1_CNT7_TR_CTRL2 TCPWM1_CNT7_INTR TCPWM1_CNT7_INTR_SET TCPWM1_CNT7_INTR_MASK TCPWM1_CNT7_INTR_MASKED TCPWM1_CNT8_CTRL TCPWM1_CNT8_STATUS TCPWM1_CNT8_COUNTER TCPWM1_CNT8_CC TCPWM1_CNT8_CC_BUFF TCPWM1_CNT8_PERIOD TCPWM1_CNT8_PERIOD_BUFF TCPWM1_CNT8_TR_CTRL0 TCPWM1_CNT8_TR_CTRL1 TCPWM1_CNT8_TR_CTRL2 TCPWM1_CNT8_INTR TCPWM1_CNT8_INTR_SET TCPWM1_CNT8_INTR_MASK TCPWM1_CNT8_INTR_MASKED TCPWM1_CNT9_CTRL TCPWM1_CNT9_STATUS TCPWM1_CNT9_COUNTER TCPWM1_CNT9_CC TCPWM1_CNT9_CC_BUFF
Address 0x403902D0 0x403902D4 0x403902D8 0x403902E0 0x403902E4 0x403902E8 0x403902F0 0x403902F4 0x403902F8 0x403902FC 0x40390300 0x40390304 0x40390308 0x4039030C 0x40390310 0x40390314 0x40390318 0x40390320 0x40390324 0x40390328 0x40390330 0x40390334 0x40390338 0x4039033C 0x40390340 0x40390344 0x40390348 0x4039034C 0x40390350
Description Counter buffered compare/capture register. See TCPWM1_CNT0_CC_BUFFfor the details of bit fields. Counter period register. See TCPWM1_CNT0_PERIODfor the details of bit fields. Counter buffered period register. See TCPWM1_CNT0_PERIOD_BUFFfor the details of bit fields. Counter trigger control register 0. See TCPWM0_CNT0_TR_CTRL0 for the details of bit fields.
Counter trigger control register 1. See TCPWM0_CNT0_TR_CTRL1 for the details of bit fields.
Counter trigger control register 2. See TCPWM0_CNT0_TR_CTRL2 for the details of bit fields.
Interrupt request register. See TCPWM0_CNT0_INTRfor the details of bit fields.
Interrupt set request register. See TCPWM0_CNT0_INTR_SETfor the details of bit fields.
Interrupt mask register. See TCPWM0_CNT0_INTR_MASKfor the details of bit fields. Interrupt masked request register. See TCPWM0_CNT0_INTR_MASKEDfor the details of bit fields. Counter control register. See TCPWM0_CNT0_CTRL for the details of bit fields.
Counter status register. See TCPWM0_CNT0_STATUS for the details of bit fields.
Counter count register. See TCPWM1_CNT0_COUNTER for the details of bit fields.
Counter compare/capture register. See TCPWM1_CNT0_CCfor the details of bit fields. Counter buffered compare/capture register. See TCPWM1_CNT0_CC_BUFFfor the details of bit fields. Counter period register. See TCPWM1_CNT0_PERIODfor the details of bit fields. Counter buffered period register. See TCPWM1_CNT0_PERIOD_BUFFfor the details of bit fields. Counter trigger control register 0. See TCPWM0_CNT0_TR_CTRL0 for the details of bit fields.
Counter trigger control register 1. See TCPWM0_CNT0_TR_CTRL1 for the details of bit fields.
Counter trigger control register 2. See TCPWM0_CNT0_TR_CTRL2 for the details of bit fields.
Interrupt request register. See TCPWM0_CNT0_INTRfor the details of bit fields.
Interrupt set request register. See TCPWM0_CNT0_INTR_SETfor the details of bit fields.
Interrupt mask register. See TCPWM0_CNT0_INTR_MASKfor the details of bit fields. Interrupt masked request register. See TCPWM0_CNT0_INTR_MASKEDfor the details of bit fields. Counter control register. See TCPWM0_CNT0_CTRL for the details of bit fields.
Counter status register. See TCPWM0_CNT0_STATUS for the details of bit fields.
Counter count register. See TCPWM1_CNT0_COUNTER for the details of bit fields.
Counter compare/capture register. See TCPWM1_CNT0_CCfor the details of bit fields. Counter buffered compare/capture register. See TCPWM1_CNT0_CC_BUFFfor the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1070
Timer, Counter, PWM (TCPWM) Registers
Register TCPWM1_CNT9_PERIOD TCPWM1_CNT9_PERIOD_BUFF TCPWM1_CNT9_TR_CTRL0 TCPWM1_CNT9_TR_CTRL1 TCPWM1_CNT9_TR_CTRL2 TCPWM1_CNT9_INTR TCPWM1_CNT9_INTR_SET TCPWM1_CNT9_INTR_MASK TCPWM1_CNT9_INTR_MASKED TCPWM1_CNT10_CTRL TCPWM1_CNT10_STATUS TCPWM1_CNT10_COUNTER TCPWM1_CNT10_CC TCPWM1_CNT10_CC_BUFF TCPWM1_CNT10_PERIOD TCPWM1_CNT10_PERIOD_BUFF TCPWM1_CNT10_TR_CTRL0 TCPWM1_CNT10_TR_CTRL1 TCPWM1_CNT10_TR_CTRL2 TCPWM1_CNT10_INTR TCPWM1_CNT10_INTR_SET TCPWM1_CNT10_INTR_MASK TCPWM1_CNT10_INTR_MASKED TCPWM1_CNT11_CTRL TCPWM1_CNT11_STATUS TCPWM1_CNT11_COUNTER TCPWM1_CNT11_CC TCPWM1_CNT11_CC_BUFF TCPWM1_CNT11_PERIOD
Address 0x40390354 0x40390358 0x40390360 0x40390364 0x40390368 0x40390370 0x40390374 0x40390378 0x4039037C 0x40390380 0x40390384 0x40390388 0x4039038C 0x40390390 0x40390394 0x40390398 0x403903A0 0x403903A4 0x403903A8 0x403903B0 0x403903B4 0x403903B8 0x403903BC 0x403903C0 0x403903C4 0x403903C8 0x403903CC 0x403903D0 0x403903D4
Description Counter period register. See TCPWM1_CNT0_PERIODfor the details of bit fields. Counter buffered period register. See TCPWM1_CNT0_PERIOD_BUFFfor the details of bit fields. Counter trigger control register 0. See TCPWM0_CNT0_TR_CTRL0 for the details of bit fields.
Counter trigger control register 1. See TCPWM0_CNT0_TR_CTRL1 for the details of bit fields.
Counter trigger control register 2. See TCPWM0_CNT0_TR_CTRL2 for the details of bit fields.
Interrupt request register. See TCPWM0_CNT0_INTRfor the details of bit fields.
Interrupt set request register. See TCPWM0_CNT0_INTR_SETfor the details of bit fields.
Interrupt mask register. See TCPWM0_CNT0_INTR_MASKfor the details of bit fields. Interrupt masked request register. See TCPWM0_CNT0_INTR_MASKEDfor the details of bit fields. Counter control register. See TCPWM0_CNT0_CTRL for the details of bit fields.
Counter status register. See TCPWM0_CNT0_STATUS for the details of bit fields.
Counter count register. See TCPWM1_CNT0_COUNTER for the details of bit fields.
Counter compare/capture register. See TCPWM1_CNT0_CCfor the details of bit fields. Counter buffered compare/capture register. See TCPWM1_CNT0_CC_BUFFfor the details of bit fields. Counter period register. See TCPWM1_CNT0_PERIODfor the details of bit fields. Counter buffered period register. See TCPWM1_CNT0_PERIOD_BUFFfor the details of bit fields. Counter trigger control register 0. See TCPWM0_CNT0_TR_CTRL0 for the details of bit fields.
Counter trigger control register 1. See TCPWM0_CNT0_TR_CTRL1 for the details of bit fields.
Counter trigger control register 2. See TCPWM0_CNT0_TR_CTRL2 for the details of bit fields.
Interrupt request register. See TCPWM0_CNT0_INTRfor the details of bit fields.
Interrupt set request register. See TCPWM0_CNT0_INTR_SETfor the details of bit fields.
Interrupt mask register. See TCPWM0_CNT0_INTR_MASKfor the details of bit fields. Interrupt masked request register. See TCPWM0_CNT0_INTR_MASKEDfor the details of bit fields. Counter control register. See TCPWM0_CNT0_CTRL for the details of bit fields.
Counter status register. See TCPWM0_CNT0_STATUS for the details of bit fields.
Counter count register. See TCPWM1_CNT0_COUNTER for the details of bit fields.
Counter compare/capture register. See TCPWM1_CNT0_CCfor the details of bit fields. Counter buffered compare/capture register. See TCPWM1_CNT0_CC_BUFFfor the details of bit fields. Counter period register. See TCPWM1_CNT0_PERIODfor the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1071
Timer, Counter, PWM (TCPWM) Registers
Register TCPWM1_CNT11_PERIOD_BUFF TCPWM1_CNT11_TR_CTRL0 TCPWM1_CNT11_TR_CTRL1 TCPWM1_CNT11_TR_CTRL2 TCPWM1_CNT11_INTR TCPWM1_CNT11_INTR_SET TCPWM1_CNT11_INTR_MASK TCPWM1_CNT11_INTR_MASKED TCPWM1_CNT12_CTRL TCPWM1_CNT12_STATUS TCPWM1_CNT12_COUNTER TCPWM1_CNT12_CC TCPWM1_CNT12_CC_BUFF TCPWM1_CNT12_PERIOD TCPWM1_CNT12_PERIOD_BUFF TCPWM1_CNT12_TR_CTRL0 TCPWM1_CNT12_TR_CTRL1 TCPWM1_CNT12_TR_CTRL2 TCPWM1_CNT12_INTR TCPWM1_CNT12_INTR_SET TCPWM1_CNT12_INTR_MASK TCPWM1_CNT12_INTR_MASKED TCPWM1_CNT13_CTRL TCPWM1_CNT13_STATUS TCPWM1_CNT13_COUNTER TCPWM1_CNT13_CC TCPWM1_CNT13_CC_BUFF TCPWM1_CNT13_PERIOD TCPWM1_CNT13_PERIOD_BUFF
Address 0x403903D8 0x403903E0 0x403903E4 0x403903E8 0x403903F0 0x403903F4 0x403903F8 0x403903FC 0x40390400 0x40390404 0x40390408 0x4039040C 0x40390410 0x40390414 0x40390418 0x40390420 0x40390424 0x40390428 0x40390430 0x40390434 0x40390438 0x4039043C 0x40390440 0x40390444 0x40390448 0x4039044C 0x40390450 0x40390454 0x40390458
Description Counter buffered period register. See TCPWM1_CNT0_PERIOD_BUFFfor the details of bit fields. Counter trigger control register 0. See TCPWM0_CNT0_TR_CTRL0 for the details of bit fields.
Counter trigger control register 1. See TCPWM0_CNT0_TR_CTRL1 for the details of bit fields.
Counter trigger control register 2. See TCPWM0_CNT0_TR_CTRL2 for the details of bit fields.
Interrupt request register. See TCPWM0_CNT0_INTRfor the details of bit fields.
Interrupt set request register. See TCPWM0_CNT0_INTR_SETfor the details of bit fields.
Interrupt mask register. See TCPWM0_CNT0_INTR_MASKfor the details of bit fields. Interrupt masked request register. See TCPWM0_CNT0_INTR_MASKEDfor the details of bit fields. Counter control register. See TCPWM0_CNT0_CTRL for the details of bit fields.
Counter status register. See TCPWM0_CNT0_STATUS for the details of bit fields.
Counter count register. See TCPWM1_CNT0_COUNTER for the details of bit fields.
Counter compare/capture register. See TCPWM1_CNT0_CCfor the details of bit fields. Counter buffered compare/capture register. See TCPWM1_CNT0_CC_BUFFfor the details of bit fields. Counter period register. See TCPWM1_CNT0_PERIODfor the details of bit fields. Counter buffered period register. See TCPWM1_CNT0_PERIOD_BUFFfor the details of bit fields. Counter trigger control register 0. See TCPWM0_CNT0_TR_CTRL0for the details of bit fields.
Counter trigger control register 1. See TCPWM0_CNT0_TR_CTRL1for the details of bit fields.
Counter trigger control register 2. See TCPWM0_CNT0_TR_CTRL2for the details of bit fields.
Interrupt request register. See TCPWM0_CNT0_INTRfor the details of bit fields.
Interrupt set request register. See TCPWM0_CNT0_INTR_SETfor the details of bit fields.
Interrupt mask register. See TCPWM0_CNT0_INTR_MASKfor the details of bit fields. Interrupt masked request register. See TCPWM0_CNT0_INTR_MASKEDfor the details of bit fields. Counter control register. See TCPWM0_CNT0_CTRL for the details of bit fields.
Counter status register. See TCPWM0_CNT0_STATUS for the details of bit fields.
Counter count register. See TCPWM1_CNT0_COUNTER for the details of bit fields.
Counter compare/capture register. See TCPWM1_CNT0_CCfor the details of bit fields. Counter buffered compare/capture register. See TCPWM1_CNT0_CC_BUFFfor the details of bit fields. Counter period register. See TCPWM1_CNT0_PERIODfor the details of bit fields. Counter buffered period register. See TCPWM1_CNT0_PERIOD_BUFFfor the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1072
Timer, Counter, PWM (TCPWM) Registers
Register TCPWM1_CNT13_TR_CTRL0 TCPWM1_CNT13_TR_CTRL1 TCPWM1_CNT13_TR_CTRL2 TCPWM1_CNT13_INTR TCPWM1_CNT13_INTR_SET TCPWM1_CNT13_INTR_MASK TCPWM1_CNT13_INTR_MASKED TCPWM1_CNT14_CTRL TCPWM1_CNT14_STATUS TCPWM1_CNT14_COUNTER TCPWM1_CNT14_CC TCPWM1_CNT14_CC_BUFF TCPWM1_CNT14_PERIOD TCPWM1_CNT14_PERIOD_BUFF TCPWM1_CNT14_TR_CTRL0 TCPWM1_CNT14_TR_CTRL1 TCPWM1_CNT14_TR_CTRL2 TCPWM1_CNT14_INTR TCPWM1_CNT14_INTR_SET TCPWM1_CNT14_INTR_MASK TCPWM1_CNT14_INTR_MASKED TCPWM1_CNT15_CTRL TCPWM1_CNT15_STATUS TCPWM1_CNT15_COUNTER TCPWM1_CNT15_CC TCPWM1_CNT15_CC_BUFF TCPWM1_CNT15_PERIOD TCPWM1_CNT15_PERIOD_BUFF TCPWM1_CNT15_TR_CTRL0
Address 0x40390460 0x40390464 0x40390468 0x40390470 0x40390474 0x40390478 0x4039047C 0x40390480 0x40390484 0x40390488 0x4039048C 0x40390490 0x40390494 0x40390498 0x403904A0 0x403904A4 0x403904A8 0x403904B0 0x403904B4 0x403904B8 0x403904BC 0x403904C0 0x403904C4 0x403904C8 0x403904CC 0x403904D0 0x403904D4 0x403904D8 0x403904E0
Description Counter trigger control register 0. See TCPWM0_CNT0_TR_CTRL0 for the details of bit fields.
Counter trigger control register 1. See TCPWM0_CNT0_TR_CTRL1 for the details of bit fields.
Counter trigger control register 2. See TCPWM0_CNT0_TR_CTRL2 for the details of bit fields.
Interrupt request register. See TCPWM0_CNT0_INTRfor the details of bit fields.
Interrupt set request register. See TCPWM0_CNT0_INTR_SETfor the details of bit fields.
Interrupt mask register. See TCPWM0_CNT0_INTR_MASKfor the details of bit fields. Interrupt masked request register. See TCPWM0_CNT0_INTR_MASKEDfor the details of bit fields. Counter control register. See TCPWM0_CNT0_CTRL for the details of bit fields.
Counter status register. See TCPWM0_CNT0_STATUS for the details of bit fields.
Counter count register. See TCPWM1_CNT0_COUNTER for the details of bit fields.
Counter compare/capture register. See TCPWM1_CNT0_CCfor the details of bit fields. Counter buffered compare/capture register. See TCPWM1_CNT0_CC_BUFFfor the details of bit fields. Counter period register. See TCPWM1_CNT0_PERIODfor the details of bit fields. Counter buffered period register. See TCPWM1_CNT0_PERIOD_BUFFfor the details of bit fields. Counter trigger control register 0. See TCPWM0_CNT0_TR_CTRL0 for the details of bit fields.
Counter trigger control register 1. See TCPWM0_CNT0_TR_CTRL1 for the details of bit fields.
Counter trigger control register 2. See TCPWM0_CNT0_TR_CTRL2 for the details of bit fields.
Interrupt request register. See TCPWM0_CNT0_INTRfor the details of bit fields.
Interrupt set request register. See TCPWM0_CNT0_INTR_SETfor the details of bit fields.
Interrupt mask register. See TCPWM0_CNT0_INTR_MASKfor the details of bit fields. Interrupt masked request register. See TCPWM0_CNT0_INTR_MASKEDfor the details of bit fields. Counter control register. See TCPWM0_CNT0_CTRL for the details of bit fields.
Counter status register. See TCPWM0_CNT0_STATUS for the details of bit fields.
Counter count register. See TCPWM1_CNT0_COUNTER for the details of bit fields.
Counter compare/capture register. See TCPWM1_CNT0_CCfor the details of bit fields. Counter buffered compare/capture register. See TCPWM1_CNT0_CC_BUFFfor the details of bit fields. Counter period register. See TCPWM1_CNT0_PERIODfor the details of bit fields. Counter buffered period register. See TCPWM1_CNT0_PERIOD_BUFFfor the details of bit fields. Counter trigger control register 0. See TCPWM0_CNT0_TR_CTRL0 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1073
Timer, Counter, PWM (TCPWM) Registers
Register TCPWM1_CNT15_TR_CTRL1 TCPWM1_CNT15_TR_CTRL2 TCPWM1_CNT15_INTR TCPWM1_CNT15_INTR_SET TCPWM1_CNT15_INTR_MASK TCPWM1_CNT15_INTR_MASKED TCPWM1_CNT16_CTRL TCPWM1_CNT16_STATUS TCPWM1_CNT16_COUNTER TCPWM1_CNT16_CC TCPWM1_CNT16_CC_BUFF TCPWM1_CNT16_PERIOD TCPWM1_CNT16_PERIOD_BUFF TCPWM1_CNT16_TR_CTRL0 TCPWM1_CNT16_TR_CTRL1 TCPWM1_CNT16_TR_CTRL2 TCPWM1_CNT16_INTR TCPWM1_CNT16_INTR_SET TCPWM1_CNT16_INTR_MASK TCPWM1_CNT16_INTR_MASKED TCPWM1_CNT17_CTRL TCPWM1_CNT17_STATUS TCPWM1_CNT17_COUNTER TCPWM1_CNT17_CC TCPWM1_CNT17_CC_BUFF TCPWM1_CNT17_PERIOD TCPWM1_CNT17_PERIOD_BUFF TCPWM1_CNT17_TR_CTRL0 TCPWM1_CNT17_TR_CTRL1
Address 0x403904E4 0x403904E8 0x403904F0 0x403904F4 0x403904F8 0x403904FC 0x40390500 0x40390504 0x40390508 0x4039050C 0x40390510 0x40390514 0x40390518 0x40390520 0x40390524 0x40390528 0x40390530 0x40390534 0x40390538 0x4039053C 0x40390540 0x40390544 0x40390548 0x4039054C 0x40390550 0x40390554 0x40390558 0x40390560 0x40390564
Description Counter trigger control register 1. See TCPWM0_CNT0_TR_CTRL1 for the details of bit fields.
Counter trigger control register 2. See TCPWM0_CNT0_TR_CTRL2 for the details of bit fields.
Interrupt request register. See TCPWM0_CNT0_INTRfor the details of bit fields.
Interrupt set request register. See TCPWM0_CNT0_INTR_SETfor the details of bit fields.
Interrupt mask register. See TCPWM0_CNT0_INTR_MASKfor the details of bit fields. Interrupt masked request register. See TCPWM0_CNT0_INTR_MASKEDfor the details of bit fields. Counter control register. See TCPWM0_CNT0_CTRL for the details of bit fields.
Counter status register. See TCPWM0_CNT0_STATUS for the details of bit fields.
Counter count register. See TCPWM1_CNT0_COUNTER for the details of bit fields.
Counter compare/capture register. See TCPWM1_CNT0_CCfor the details of bit fields. Counter buffered compare/capture register. See TCPWM1_CNT0_CC_BUFFfor the details of bit fields. Counter period register. See TCPWM1_CNT0_PERIODfor the details of bit fields. Counter buffered period register. See TCPWM1_CNT0_PERIOD_BUFFfor the details of bit fields. Counter trigger control register 0. See TCPWM0_CNT0_TR_CTRL0 for the details of bit fields.
Counter trigger control register 1. See TCPWM0_CNT0_TR_CTRL1 for the details of bit fields.
Counter trigger control register 2. See TCPWM0_CNT0_TR_CTRL2 for the details of bit fields.
Interrupt request register. See TCPWM0_CNT0_INTRfor the details of bit fields.
Interrupt set request register. See TCPWM0_CNT0_INTR_SETfor the details of bit fields.
Interrupt mask register. See TCPWM0_CNT0_INTR_MASKfor the details of bit fields. Interrupt masked request register. See TCPWM0_CNT0_INTR_MASKEDfor the details of bit fields. Counter control register. See TCPWM0_CNT0_CTRL for the details of bit fields.
Counter status register. See TCPWM0_CNT0_STATUS for the details of bit fields.
Counter count register. See TCPWM1_CNT0_COUNTER for the details of bit fields.
Counter compare/capture register. See TCPWM1_CNT0_CCfor the details of bit fields. Counter buffered compare/capture register. See TCPWM1_CNT0_CC_BUFFfor the details of bit fields. Counter period register. See TCPWM1_CNT0_PERIODfor the details of bit fields. Counter buffered period register. See TCPWM1_CNT0_PERIOD_BUFFfor the details of bit fields. Counter trigger control register 0. See TCPWM0_CNT0_TR_CTRL0 for the details of bit fields.
Counter trigger control register 1. See TCPWM0_CNT0_TR_CTRL1 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1074
Timer, Counter, PWM (TCPWM) Registers
Register TCPWM1_CNT17_TR_CTRL2 TCPWM1_CNT17_INTR TCPWM1_CNT17_INTR_SET TCPWM1_CNT17_INTR_MASK TCPWM1_CNT17_INTR_MASKED TCPWM1_CNT18_CTRL TCPWM1_CNT18_STATUS TCPWM1_CNT18_COUNTER TCPWM1_CNT18_CC TCPWM1_CNT18_CC_BUFF TCPWM1_CNT18_PERIOD TCPWM1_CNT18_PERIOD_BUFF TCPWM1_CNT18_TR_CTRL0 TCPWM1_CNT18_TR_CTRL1 TCPWM1_CNT18_TR_CTRL2 TCPWM1_CNT18_INTR TCPWM1_CNT18_INTR_SET TCPWM1_CNT18_INTR_MASK TCPWM1_CNT18_INTR_MASKED TCPWM1_CNT19_CTRL TCPWM1_CNT19_STATUS TCPWM1_CNT19_COUNTER TCPWM1_CNT19_CC TCPWM1_CNT19_CC_BUFF TCPWM1_CNT19_PERIOD TCPWM1_CNT19_PERIOD_BUFF TCPWM1_CNT19_TR_CTRL0 TCPWM1_CNT19_TR_CTRL1 TCPWM1_CNT19_TR_CTRL2
Address 0x40390568 0x40390570 0x40390574 0x40390578 0x4039057C 0x40390580 0x40390584 0x40390588 0x4039058C 0x40390590 0x40390594 0x40390598 0x403905A0 0x403905A4 0x403905A8 0x403905B0 0x403905B4 0x403905B8 0x403905BC 0x403905C0 0x403905C4 0x403905C8 0x403905CC 0x403905D0 0x403905D4 0x403905D8 0x403905E0 0x403905E4 0x403905E8
Description Counter trigger control register 2. See TCPWM0_CNT0_TR_CTRL2 for the details of bit fields.
Interrupt request register. See TCPWM0_CNT0_INTRfor the details of bit fields.
Interrupt set request register. See TCPWM0_CNT0_INTR_SETfor the details of bit fields.
Interrupt mask register. See TCPWM0_CNT0_INTR_MASKfor the details of bit fields. Interrupt masked request register. See TCPWM0_CNT0_INTR_MASKEDfor the details of bit fields. Counter control register. See TCPWM0_CNT0_CTRL for the details of bit fields.
Counter status register. See TCPWM0_CNT0_STATUS for the details of bit fields.
Counter count register. See TCPWM1_CNT0_COUNTER for the details of bit fields.
Counter compare/capture register. See TCPWM1_CNT0_CCfor the details of bit fields. Counter buffered compare/capture register. See TCPWM1_CNT0_CC_BUFFfor the details of bit fields. Counter period register. See TCPWM1_CNT0_PERIODfor the details of bit fields. Counter buffered period register. See TCPWM1_CNT0_PERIOD_BUFFfor the details of bit fields. Counter trigger control register 0. See TCPWM0_CNT0_TR_CTRL0 for the details of bit fields.
Counter trigger control register 1. See TCPWM0_CNT0_TR_CTRL1 for the details of bit fields.
Counter trigger control register 2. See TCPWM0_CNT0_TR_CTRL2 for the details of bit fields.
Interrupt request register. See TCPWM0_CNT0_INTRfor the details of bit fields.
Interrupt set request register. See TCPWM0_CNT0_INTR_SETfor the details of bit fields.
Interrupt mask register. See TCPWM0_CNT0_INTR_MASKfor the details of bit fields. Interrupt masked request register. See TCPWM0_CNT0_INTR_MASKEDfor the details of bit fields. Counter control register. See TCPWM0_CNT0_CTRL for the details of bit fields.
Counter status register. See TCPWM0_CNT0_STATUS for the details of bit fields.
Counter count register. See TCPWM1_CNT0_COUNTER for the details of bit fields.
Counter compare/capture register. See TCPWM1_CNT0_CCfor the details of bit fields. Counter buffered compare/capture register. See TCPWM1_CNT0_CC_BUFFfor the details of bit fields. Counter period register. See TCPWM1_CNT0_PERIODfor the details of bit fields. Counter buffered period register. See TCPWM1_CNT0_PERIOD_BUFFfor the details of bit fields. Counter trigger control register 0. See TCPWM0_CNT0_TR_CTRL0 for the details of bit fields.
Counter trigger control register 1. See TCPWM0_CNT0_TR_CTRL1 for the details of bit fields.
Counter trigger control register 2. See TCPWM0_CNT0_TR_CTRL2 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1075
Timer, Counter, PWM (TCPWM) Registers
Register TCPWM1_CNT19_INTR TCPWM1_CNT19_INTR_SET TCPWM1_CNT19_INTR_MASK TCPWM1_CNT19_INTR_MASKED TCPWM1_CNT20_CTRL TCPWM1_CNT20_STATUS TCPWM1_CNT20_COUNTER TCPWM1_CNT20_CC TCPWM1_CNT20_CC_BUFF TCPWM1_CNT20_PERIOD TCPWM1_CNT20_PERIOD_BUFF TCPWM1_CNT20_TR_CTRL0 TCPWM1_CNT20_TR_CTRL1 TCPWM1_CNT20_TR_CTRL2 TCPWM1_CNT20_INTR TCPWM1_CNT20_INTR_SET TCPWM1_CNT20_INTR_MASK TCPWM1_CNT20_INTR_MASKED TCPWM1_CNT21_CTRL TCPWM1_CNT21_STATUS TCPWM1_CNT21_COUNTER TCPWM1_CNT21_CC TCPWM1_CNT21_CC_BUFF TCPWM1_CNT21_PERIOD TCPWM1_CNT21_PERIOD_BUFF TCPWM1_CNT21_TR_CTRL0 TCPWM1_CNT21_TR_CTRL1 TCPWM1_CNT21_TR_CTRL2 TCPWM1_CNT21_INTR
Address 0x403905F0 0x403905F4 0x403905F8 0x403905FC 0x40390600 0x40390604 0x40390608 0x4039060C 0x40390610 0x40390614 0x40390618 0x40390620 0x40390624 0x40390628 0x40390630 0x40390634 0x40390638 0x4039063C 0x40390640 0x40390644 0x40390648 0x4039064C 0x40390650 0x40390654 0x40390658 0x40390660 0x40390664 0x40390668 0x40390670
Description Interrupt request register. See TCPWM0_CNT0_INTRfor the details of bit fields.
Interrupt set request register. See TCPWM0_CNT0_INTR_SETfor the details of bit fields.
Interrupt mask register. See TCPWM0_CNT0_INTR_MASKfor the details of bit fields. Interrupt masked request register. See TCPWM0_CNT0_INTR_MASKEDfor the details of bit fields. Counter control register. See TCPWM0_CNT0_CTRL for the details of bit fields.
Counter status register. See TCPWM0_CNT0_STATUS for the details of bit fields.
Counter count register. See TCPWM1_CNT0_COUNTER for the details of bit fields.
Counter compare/capture register. See TCPWM1_CNT0_CCfor the details of bit fields. Counter buffered compare/capture register. See TCPWM1_CNT0_CC_BUFFfor the details of bit fields. Counter period register. See TCPWM1_CNT0_PERIODfor the details of bit fields. Counter buffered period register. See TCPWM1_CNT0_PERIOD_BUFFfor the details of bit fields. Counter trigger control register 0. See TCPWM0_CNT0_TR_CTRL0 for the details of bit fields.
Counter trigger control register 1. See TCPWM0_CNT0_TR_CTRL1 for the details of bit fields.
Counter trigger control register 2. See TCPWM0_CNT0_TR_CTRL2 for the details of bit fields.
Interrupt request register. See TCPWM0_CNT0_INTRfor the details of bit fields.
Interrupt set request register. See TCPWM0_CNT0_INTR_SETfor the details of bit fields.
Interrupt mask register. See TCPWM0_CNT0_INTR_MASKfor the details of bit fields. Interrupt masked request register. See TCPWM0_CNT0_INTR_MASKEDfor the details of bit fields. Counter control register. See TCPWM0_CNT0_CTRL for the details of bit fields.
Counter status register. See TCPWM0_CNT0_STATUS for the details of bit fields.
Counter count register. See TCPWM1_CNT0_COUNTER for the details of bit fields.
Counter compare/capture register. See TCPWM1_CNT0_CCfor the details of bit fields. Counter buffered compare/capture register. See TCPWM1_CNT0_CC_BUFFfor the details of bit fields. Counter period register. See TCPWM1_CNT0_PERIODfor the details of bit fields. Counter buffered period register. See TCPWM1_CNT0_PERIOD_BUFFfor the details of bit fields. Counter trigger control register 0. See TCPWM0_CNT0_TR_CTRL0 for the details of bit fields.
Counter trigger control register 1. See TCPWM0_CNT0_TR_CTRL1 for the details of bit fields.
Counter trigger control register 2. See TCPWM0_CNT0_TR_CTRL2 for the details of bit fields.
Interrupt request register. See TCPWM0_CNT0_INTRfor the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1076
Timer, Counter, PWM (TCPWM) Registers
Register TCPWM1_CNT21_INTR_SET TCPWM1_CNT21_INTR_MASK TCPWM1_CNT21_INTR_MASKED TCPWM1_CNT22_CTRL TCPWM1_CNT22_STATUS TCPWM1_CNT22_COUNTER TCPWM1_CNT22_CC TCPWM1_CNT22_CC_BUFF TCPWM1_CNT22_PERIOD TCPWM1_CNT22_PERIOD_BUFF TCPWM1_CNT22_TR_CTRL0 TCPWM1_CNT22_TR_CTRL1 TCPWM1_CNT22_TR_CTRL2 TCPWM1_CNT22_INTR TCPWM1_CNT22_INTR_SET TCPWM1_CNT22_INTR_MASK TCPWM1_CNT22_INTR_MASKED TCPWM1_CNT23_CTRL TCPWM1_CNT23_STATUS TCPWM1_CNT23_COUNTER TCPWM1_CNT23_CC TCPWM1_CNT23_CC_BUFF TCPWM1_CNT23_PERIOD TCPWM1_CNT23_PERIOD_BUFF TCPWM1_CNT23_TR_CTRL0 TCPWM1_CNT23_TR_CTRL1 TCPWM1_CNT23_TR_CTRL2 TCPWM1_CNT23_INTR TCPWM1_CNT23_INTR_SET
Address 0x40390674 0x40390678 0x4039067C 0x40390680 0x40390684 0x40390688 0x4039068C 0x40390690 0x40390694 0x40390698 0x403906A0 0x403906A4 0x403906A8 0x403906B0 0x403906B4 0x403906B8 0x403906BC 0x403906C0 0x403906C4 0x403906C8 0x403906CC 0x403906D0 0x403906D4 0x403906D8 0x403906E0 0x403906E4 0x403906E8 0x403906F0 0x403906F4
Description Interrupt set request register. See TCPWM0_CNT0_INTR_SETfor the details of bit fields.
Interrupt mask register. See TCPWM0_CNT0_INTR_MASKfor the details of bit fields. Interrupt masked request register. See TCPWM0_CNT0_INTR_MASKEDfor the details of bit fields. Counter control register. See TCPWM0_CNT0_CTRL for the details of bit fields.
Counter status register. See TCPWM0_CNT0_STATUS for the details of bit fields.
Counter count register. See TCPWM1_CNT0_COUNTER for the details of bit fields.
Counter compare/capture register. See TCPWM1_CNT0_CCfor the details of bit fields. Counter buffered compare/capture register. See TCPWM1_CNT0_CC_BUFFfor the details of bit fields. Counter period register. See TCPWM1_CNT0_PERIODfor the details of bit fields. Counter buffered period register. See TCPWM1_CNT0_PERIOD_BUFFfor the details of bit fields. Counter trigger control register 0. See TCPWM0_CNT0_TR_CTRL0 for the details of bit fields.
Counter trigger control register 1. See TCPWM0_CNT0_TR_CTRL1 for the details of bit fields.
Counter trigger control register 2. See TCPWM0_CNT0_TR_CTRL2 for the details of bit fields.
Interrupt request register. See TCPWM0_CNT0_INTRfor the details of bit fields.
Interrupt set request register. See TCPWM0_CNT0_INTR_SETfor the details of bit fields.
Interrupt mask register. See TCPWM0_CNT0_INTR_MASKfor the details of bit fields. Interrupt masked request register. See TCPWM0_CNT0_INTR_MASKEDfor the details of bit fields. Counter control register. See TCPWM0_CNT0_CTRL for the details of bit fields.
Counter status register. See TCPWM0_CNT0_STATUS for the details of bit fields.
Counter count register. See TCPWM1_CNT0_COUNTER for the details of bit fields.
Counter compare/capture register. See TCPWM1_CNT0_CC for the details of bit fields. Counter buffered compare/capture register. See TCPWM1_CNT0_CC_BUFFfor the details of bit fields. Counter period register. See TCPWM1_CNT0_PERIOD for the details of bit fields. Counter buffered period register. See TCPWM1_CNT0_PERIOD_BUFFfor the details of bit fields. Counter trigger control register 0. See TCPWM0_CNT0_TR_CTRL0 for the details of bit fields.
Counter trigger control register 1. See TCPWM0_CNT0_TR_CTRL1 for the details of bit fields.
Counter trigger control register 2. See TCPWM0_CNT0_TR_CTRL2 for the details of bit fields.
Interrupt request register. See TCPWM0_CNT0_INTR for the details of bit fields.
Interrupt set request register. See TCPWM0_CNT0_INTR_SET for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1077
Timer, Counter, PWM (TCPWM) Registers
Register TCPWM1_CNT23_INTR_MASK TCPWM1_CNT23_INTR_MASKED
Address 0x403906F8 0x403906FC
Description
Interrupt mask register. See TCPWM0_CNT0_INTR_MASK for the details of bit fields.
Interrupt masked request register. See TCPWM0_CNT0_INTR_MASKED for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1078
TCPWM0_CTRL
20.1.1 TCPWM0_CTRL
Address = 0x40380000 TCPWM control register Address: 0x40380000 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
COUNTER_ENABLED [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 0
Name COUNTER_ENABLED
Description
Counter enables for counters 0 up to CNT_NR-1. '0': counter disabled. '1': counter enabled. Counter static configuration information (e.g. CTRL.MODE, all TR_CTRL0, TR_CTRL1, and TR_CTRL2 register fields) should only be modified when the counter is disabled. When a counter is disabled, command and status information associated to the counter is cleared by HW, this includes: - the associated counter triggers in the CMD register are set to '0'. - the counter's interrupt cause fields in counter's INTR register. - the counter's status fields in counter's STATUS register.. - the counter's trigger outputs ("tr_overflow", "tr_underflow" and "tr_compare_match"). - the counter's line outputs ("line_out" and "line_compl_out"). In multi-core environments, use the CTRL_SET/CTRL_CLR registers to avoid race-conditions on read-modify-write attempts to this register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1079
TCPWM0_CTRL_CLR
20.1.2 TCPWM0_CTRL_CLR
Address = 0x40380004 TCPWM control clear register Address: 0x40380004 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW1C
HW Access
A
Name
COUNTER_ENABLED [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 0
Name COUNTER_ENABLED
Description
Alias of CTRL that only allows disabling of counters. A write access: '0': Does nothing. '1': Clears respective COUNTER_ENABLED field. A read access returns CTRL.COUNTER_ENABLED. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1080
TCPWM0_CTRL_SET
20.1.3 TCPWM0_CTRL_SET
Address = 0x40380008 TCPWM control set register Address: 0x40380008 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW1S
HW Access
A
Name
COUNTER_ENABLED [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 0
Name COUNTER_ENABLED
Description
Alias of CTRL that only allows enabling of counters. A write access: '0': Does nothing. '1': Sets respective COUNTER_ENABLED field. A read access returns CTRL.COUNTER_ENABLED. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1081
TCPWM0_CMD_CAPTURE
20.1.4 TCPWM0_CMD_CAPTURE
Address = 0x4038000C TCPWM capture command register Address: 0x4038000C Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW1S
HW Access
RW1C
Name
COUNTER_CAPTURE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 0
Name COUNTER_CAPTURE
Description
Counters SW capture trigger. When written with '1', a capture trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is disabled through CTRL.COUNTER_ENABLED, the field is immediately set to '0'. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1082
TCPWM0_CMD_RELOAD
20.1.5 TCPWM0_CMD_RELOAD
Address = 0x40380010 TCPWM reload command register Address: 0x40380010 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW1S
HW Access
RW1C
Name
COUNTER_RELOAD [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 0
Name COUNTER_RELOAD
Description
Counters SW reload trigger. For HW behavior, see COUNTER_CAPTURE field. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1083
TCPWM0_CMD_STOP
20.1.6 TCPWM0_CMD_STOP
Address = 0x40380014 TCPWM stop command register Address: 0x40380014 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW1S
HW Access
RW1C
Name
COUNTER_STOP [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 0
Name COUNTER_STOP
Description
Counters SW stop trigger. For HW behavior, see COUNTER_CAPTURE field. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1084
TCPWM0_CMD_START
20.1.7 TCPWM0_CMD_START
Address = 0x40380018 TCPWM start command register Address: 0x40380018 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW1S
HW Access
RW1C
Name
COUNTER_START [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 0
Name COUNTER_START
Description
Counters SW start trigger. For HW behavior, see COUNTER_CAPTURE field. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1085
TCPWM0_INTR_CAUSE
20.1.8 TCPWM0_INTR_CAUSE
Address = 0x4038001C TCPWM Counter interrupt cause register Address: 0x4038001C Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
COUNTER_INT [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 0
Name COUNTER_INT
Description
Counters interrupt signal active. If the counter is disabled through CTRL.COUNTER_ENABLED, the associated interrupt field is immediately set to '0'. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1086
TCPWM0_CNT0_CTRL
20.1.9 TCPWM0_CNT0_CTRL
Address = 0x40380100 Counter control register Address: 0x40380100 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:4]
4
3
2
1
0
RW
RW
RW
RW
R
R
R
R
PWM_STOP_O
N_KILL
PWM_SYNC_KILL
AUTO_RELOAD_PE-
RIOD
AUTO_RELOAD_CC
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
GENERIC [15:8]
Bits SW Access HW Access
Name
23
22
None
None
None [23:22]
21
20
RW
R
QUADRATURE_MODE [21:20]
19 None None
None
18
17
16
RW
RW
R
R
ONE_SHOT UP_DOWN_MODE [17:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
RW
HW Access
None
R
Name
None [31:27]
MODE [26:24]
Bits 26 : 24
Name MODE
Description Counter mode. Default Value: 0 0x0: TIMER : Timer mode
0x2: CAPTURE : Capture mode
0x3: QUAD : Quadrature encoding mode
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1087
TCPWM0_CNT0_CTRL
20.1.9
TCPWM0_CNT0_CTRL (continued)
0x4: PWM : Pulse width modulation (PWM) mode
0x5: PWM_DT : PWM with deadtime insertion mode
0x6: PWM_PR : Pseudo random pulse width modulation
21 : 20
QUADRATURE_MODE
In QUAD mode selects quadrature encoding mode (X1/X2/X4). In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert "dt_line_out" and "dt_line_compl_out". Inversion is the last step in generation of "dt_line_out" and "dt_line_compl_out"; i.e. a disabled output line "dt_line_out" has the value QUADRATURE_MODE[0] and a disabled output line "dt_line_compl_out" has the value QUADRATURE_MODE[1]. Default Value: 0
0x0: X1 :
X1 encoding (QUAD mode)
0x1: X2 : X2 encoding (QUAD mode)
0x2: X4 : X4 encoding (QUAD mode)
0x1: INV_OUT : When bit 0 is '1', QUADRATURE_MODE[0] inverts "dt_line_out" (PWM/PWM_DT modes)
0x2: INV_COMPL_OUT :
When bit 1 is '1', QUADRATURE_MODE[1] inverts "dt_line_compl_out" (PWM/PWM_DT modes)
18
ONE_SHOT
17 : 16
UP_DOWN_MODE
When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated. Default Value: 0
Determines counter direction. Default Value: 0
0x0: COUNT_UP :
Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1088
TCPWM0_CNT0_CTRL
20.1.9
TCPWM0_CNT0_CTRL (continued)
0x1: COUNT_DOWN :
Count down (to "0"). An underflow event is generated when the counter changes from a state in which COUNTER equals "0". A terminal count event is generated when the counter changes from a state in which COUNTER equals "0".
0x2: COUNT_UPDN1 :
Count up (to PERIOD), then count down (to "0"). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals "0". A terminal count event is generated when the counter changes from a state in which COUNTER equals "0".
0x3: COUNT_UPDN2 :
Count up (to PERIOD), then count down (to "0"). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals "0". A terminal count event is generated when the counter changes from a state in which COUNTER equals "0" AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates).
15 : 8
GENERIC
Generic 8-bit control field. In PWM_DT mode, this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock. Default Value: 0
0x0: DIVBY1 :
Divide by 1 (other-than-PWM_DT mode)
0x1: DIVBY2 : Divide by 2 (other-than-PWM_DT mode)
0x2: DIVBY4 : Divide by 4 (other-than-PWM_DT mode)
0x3: DIVBY8 : Divide by 8 (other-than-PWM_DT mode)
0x4: DIVBY16 : Divide by 16 (other-than-PWM_DT mode)
0x5: DIVBY32 : Divide by 32 (other-than-PWM_DT mode)
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1089
TCPWM0_CNT0_CTRL
20.1.9
TCPWM0_CNT0_CTRL (continued)
0x6: DIVBY64 : Divide by 64 (other-than-PWM_DT mode)
0x7: DIVBY128 : Divide by 128 (other-than-PWM_DT mode)
3
PWM_STOP_ON_KILL
Specifies whether the counter stops on a kill events:
'0': kill event does NOT stop counter.
'1': kill event stops counter.
This field has a function in PWM, PWM_DT and PWM_PR modes only.
Default Value: 0
2
PWM_SYNC_KILL
Specifies asynchronous/synchronous kill behavior:
'1': synchronous kill mode: the kill event disables the "dt_line_out" and "dt_line_compl_out" sig-
nals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE
should be RISING_EDGE.
'0': asynchronous kill mode: the kill event only disables the "dt_line_out" and "dt_line_compl_out"
signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET.
This field has a function in PWM and PWM_DT modes only. This field is only used when PW-
M_STOP_ON_KILL is '0'.
Default Value: 0
1
AUTO_RELOAD_PERIOD Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in
PWM, PWM_DT and PWM_PR modes.
'0': never switch.
'1': switch on a terminal count event with and actively pending switch event.
Default Value: 0
0
AUTO_RELOAD_CC
Specifies switching of the CC and buffered CC values. This field has a function in TIMER, PWM,
PWM_DT and PWM_PR modes.
Timer mode:
'0': never switch.
'1': switch on a compare match event.
PWM, PWM_DT, PWM_PR modes:
'0: never switch.
'1': switch on a terminal count event with an actively pending switch event.
Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1090
TCPWM0_CNT0_STATUS
20.1.10 TCPWM0_CNT0_STATUS
Address = 0x40380104 Counter status register Address: 0x40380104 Retention: Not Retained
Bits
7
6
5
4
3
2
SW Access
None
HW Access
None
Name
None [7:1]
Bits
15
14
13
12
11
10
SW Access
R
HW Access
RW
Name
GENERIC [15:8]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
SW Access
R
None
HW Access
RW
None
Name
RUNNING
None [30:24]
1
0
R
RW
DOWN
9
8
17
16
25
24
Bits 31
15 : 8
Name RUNNING
GENERIC
0
DOWN
Description
When '0', the counter is NOT running. When '1', the counter is running. Default Value: 0
Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion. In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality. Default Value: 0
When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1091
TCPWM0_CNT0_COUNTER
20.1.11 TCPWM0_CNT0_COUNTER
Address = 0x40380108 Counter count register Address: 0x40380108 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
COUNTER [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
RW
Name
COUNTER [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
RW
Name
COUNTER [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
RW
Name
COUNTER [31:24]
Bits 31 : 0
Name COUNTER
Description
32-bit counter value. It is advised to not write to this field when the counter is running. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1092
TCPWM0_CNT0_CC
20.1.12 TCPWM0_CNT0_CC
Address = 0x4038010C Counter compare/capture register Address: 0x4038010C Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
CC [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
RW
Name
CC [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
RW
Name
CC [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
RW
Name
CC [31:24]
Bits 31 : 0
Name CC
Description
In CAPTURE mode, captures the counter value. In other modes, compared to counter value. Default Value: 4294967295
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1093
TCPWM0_CNT0_CC_BUFF
20.1.13 TCPWM0_CNT0_CC_BUFF
Address = 0x40380110 Counter buffered compare/capture register Address: 0x40380110 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
CC [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
RW
Name
CC [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
RW
Name
CC [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
RW
Name
CC [31:24]
Bits 31 : 0
Name CC
Description
Additional buffer for counter CC register. Default Value: 4294967295
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1094
TCPWM0_CNT0_PERIOD
20.1.14 TCPWM0_CNT0_PERIOD
Address = 0x40380114 Counter period register Address: 0x40380114 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
PERIOD [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
RW
Name
PERIOD [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
RW
Name
PERIOD [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
RW
Name
PERIOD [31:24]
Bits 31 : 0
Name PERIOD
Description
Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1. Default Value: 4294967295
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1095
TCPWM0_CNT0_PERIOD_BUFF
20.1.15 TCPWM0_CNT0_PERIOD_BUFF
Address = 0x40380118 Counter buffered period register Address: 0x40380118 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
PERIOD [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
RW
Name
PERIOD [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
RW
Name
PERIOD [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
RW
Name
PERIOD [31:24]
Bits 31 : 0
Name PERIOD
Description
Additional buffer for counter PERIOD register. Default Value: 4294967295
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1096
TCPWM0_CNT0_TR_CTRL0
20.1.16 TCPWM0_CNT0_TR_CTRL0
Address = 0x40380120 Counter trigger control register 0 Address: 0x40380120 Retention: Retained
Bits
7
6
5
4
SW Access
RW
HW Access
R
Name
COUNT_SEL [7:4]
3
2
1
0
RW
R
CAPTURE_SEL [3:0]
Bits
15
14
13
12
SW Access
RW
HW Access
R
Name
STOP_SEL [15:12]
11
10
9
8
RW
R
RELOAD_SEL [11:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
HW Access
None
R
Name
None [23:20]
START_SEL [19:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 19 : 16
Name START_SEL
15 : 12
STOP_SEL
11 : 8
RELOAD_SEL
7 : 4
COUNT_SEL
Description
Selects one of the 16 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B). Default Value: 0
Selects one of the 16 input triggers as a stop trigger. In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event. Default Value: 0
Selects one of the 16 input triggers as a reload trigger. In QUAD mode, this is the index or revolution pulse. In this mode, it will update the counter with 0x8000 (counter midpoint). Default Value: 0
Selects one of the 16 input triggers as a count trigger. In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'. Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1097
TCPWM0_CNT0_TR_CTRL0
20.1.16 TCPWM0_CNT0_TR_CTRL0 (continued)
3 : 0
CAPTURE_SEL
Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger is always '1'. In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1098
TCPWM0_CNT0_TR_CTRL1
20.1.17 TCPWM0_CNT0_TR_CTRL1
Address = 0x40380124 Counter trigger control register 1 Address: 0x40380124 Retention: Retained
Bits SW Access HW Access
Name
7
6
RW
R
STOP_EDGE [7:6]
5
4
RW
R
RELOAD_EDGE [5:4]
3
2
RW
R
COUNT_EDGE [3:2]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:10]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
1
0
RW
R
CAPTURE_EDGE [1:0]
9
8
RW
R
START_EDGE [9:8]
17
16
25
24
Bits 9 : 8
Name START_EDGE
Description A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does. Default Value: 3 0x0: RISING_EDGE : Rising edge. Any rising edge generates an event.
0x1: FALLING_EDGE : Falling edge. Any falling edge generates an event.
0x2: BOTH_EDGES : Rising AND falling edge. Any odd amount of edges generates an event.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1099
TCPWM0_CNT0_TR_CTRL1
20.1.17
TCPWM0_CNT0_TR_CTRL1 (continued)
0x3: NO_EDGE_DET : No edge detection, use trigger as is.
7 : 6
STOP_EDGE
A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter. Default Value: 3
0x0: RISING_EDGE :
Rising edge. Any rising edge generates an event.
0x1: FALLING_EDGE : Falling edge. Any falling edge generates an event.
0x2: BOTH_EDGES : Rising AND falling edge. Any odd amount of edges generates an event.
0x3: NO_EDGE_DET : No edge detection, use trigger as is.
5 : 4
RELOAD_EDGE
A reload event will initialize the counter. When counting up, the counter is initialized to "0". When counting down, the counter is initialized with PERIOD. Default Value: 3
0x0: RISING_EDGE :
Rising edge. Any rising edge generates an event.
0x1: FALLING_EDGE : Falling edge. Any falling edge generates an event.
0x2: BOTH_EDGES : Rising AND falling edge. Any odd amount of edges generates an event.
0x3: NO_EDGE_DET : No edge detection, use trigger as is.
3 : 2
COUNT_EDGE
A counter event will increase or decrease the counter by '1'. Default Value: 3 0x0: RISING_EDGE :
Rising edge. Any rising edge generates an event.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1100
TCPWM0_CNT0_TR_CTRL1
20.1.17
TCPWM0_CNT0_TR_CTRL1 (continued)
0x1: FALLING_EDGE : Falling edge. Any falling edge generates an event.
0x2: BOTH_EDGES : Rising AND falling edge. Any odd amount of edges generates an event.
0x3: NO_EDGE_DET : No edge detection, use trigger as is.
1 : 0
CAPTURE_EDGE
A capture event will copy the counter value into the CC register. Default Value: 3 0x0: RISING_EDGE :
Rising edge. Any rising edge generates an event.
0x1: FALLING_EDGE : Falling edge. Any falling edge generates an event.
0x2: BOTH_EDGES : Rising AND falling edge. Any odd amount of edges generates an event.
0x3: NO_EDGE_DET : No edge detection, use trigger as is.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1101
TCPWM0_CNT0_TR_CTRL2
20.1.18 TCPWM0_CNT0_TR_CTRL2
Address = 0x40380128 Counter trigger control register 2 Address: 0x40380128 Retention: Retained
Bits SW Access HW Access
Name
7
6
None
None
None [7:6]
5
4
RW
R
UNDERFLOW_MODE [5:4]
3
2
RW
R
1
0
RW
R
OVERFLOW_MODE [3:2] CC_MATCH_MODE [1:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 5 : 4
Name UNDERFLOW_MODE
Description Determines the effect of a counter underflow event (COUNTER reaches "0") on the "line_out" output signals. Default Value: 3 0x0: SET : Set to '1'
0x1: CLEAR : Set to '0'
0x2: INVERT : Invert
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1102
TCPWM0_CNT0_TR_CTRL2
20.1.18
TCPWM0_CNT0_TR_CTRL2 (continued)
0x3: NO_CHANGE : No Change
3 : 2
OVERFLOW_MODE
Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the
"line_out" output signals.
Default Value: 3
0x0: SET :
Set to '1'
0x1: CLEAR : Set to '0'
0x2: INVERT : Invert
0x3: NO_CHANGE : No Change
1 : 0
CC_MATCH_MODE
Determines the effect of a compare match event (COUNTER equals CC register) on the
"line_out" output signals. Note that INVERT is especially useful for center aligned pulse width
modulation.
To generate a duty cycle of 0%, the counter CC register should be set to "0". For a 100% duty
cycle, the counter CC register should be set to larger than the counter PERIOD register.
Default Value: 3
0x0: SET :
Set to '1'
0x1: CLEAR : Set to '0'
0x2: INVERT : Invert
0x3: NO_CHANGE : No Change
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1103
TCPWM0_CNT0_INTR
20.1.19 TCPWM0_CNT0_INTR
Address = 0x40380130 Interrupt request register Address: 0x40380130 Retention: Not Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:2]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
0
RW1C
RW1C
RW1S
RW1S
CC_MATCH
TC
10
9
8
18
17
16
26
25
24
Bits
Name
1
CC_MATCH
0
TC
Description
Counter matches CC register event. Set to '1', when event is detected. Write with '1' to clear bit. Default Value: 0
Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1104
TCPWM0_CNT0_INTR_SET
20.1.20 TCPWM0_CNT0_INTR_SET
Address = 0x40380134 Interrupt set request register Address: 0x40380134 Retention: Not Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:2]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
0
RW1S
RW1S
A
A
CC_MATCH
TC
10
9
8
18
17
16
26
25
24
Bits
Name
1
CC_MATCH
0
TC
Description
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1105
TCPWM0_CNT0_INTR_MASK
20.1.21 TCPWM0_CNT0_INTR_MASK
Address = 0x40380138 Interrupt mask register Address: 0x40380138 Retention: Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:2]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
0
RW
RW
R
R
CC_MATCH
TC
10
9
8
18
17
16
26
25
24
Bits
Name
1
CC_MATCH
0
TC
Description
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1106
TCPWM0_CNT0_INTR_MASKED
20.1.22 TCPWM0_CNT0_INTR_MASKED
Address = 0x4038013C Interrupt masked request register Address: 0x4038013C Retention: Not Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:2]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
0
R
R
W
W
CC_MATCH
TC
10
9
8
18
17
16
26
25
24
Bits
Name
1
CC_MATCH
0
TC
Description
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1107
TCPWM1_CTRL
20.1.23 TCPWM1_CTRL
Address = 0x40390000 TCPWM control register Address: 0x40390000 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
COUNTER_ENABLED [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
RW
Name
COUNTER_ENABLED [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
RW
Name
COUNTER_ENABLED [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 23 : 0
Name COUNTER_ENABLED
Description
Counter enables for counters 0 up to CNT_NR-1. '0': counter disabled. '1': counter enabled. Counter static configuration information (e.g. CTRL.MODE, all TR_CTRL0, TR_CTRL1, and TR_CTRL2 register fields) should only be modified when the counter is disabled. When a counter is disabled, command and status information associated to the counter is cleared by HW, this includes: - the associated counter triggers in the CMD register are set to '0'. - the counter's interrupt cause fields in counter's INTR register. - the counter's status fields in counter's STATUS register.. - the counter's trigger outputs ("tr_overflow", "tr_underflow" and "tr_compare_match"). - the counter's line outputs ("line_out" and "line_compl_out"). In multi-core environments, use the CTRL_SET/CTRL_CLR registers to avoid race-conditions on read-modify-write attempts to this register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1108
TCPWM1_CTRL_CLR
20.1.24 TCPWM1_CTRL_CLR
Address = 0x40390004 TCPWM control clear register Address: 0x40390004 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW1C
HW Access
A
Name
COUNTER_ENABLED [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW1C
HW Access
A
Name
COUNTER_ENABLED [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW1C
HW Access
A
Name
COUNTER_ENABLED [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 23 : 0
Name COUNTER_ENABLED
Description
Alias of CTRL that only allows disabling of counters. A write access: '0': Does nothing. '1': Clears respective COUNTER_ENABLED field. A read access returns CTRL.COUNTER_ENABLED. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1109
TCPWM1_CTRL_SET
20.1.25 TCPWM1_CTRL_SET
Address = 0x40390008 TCPWM control set register Address: 0x40390008 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW1S
HW Access
A
Name
COUNTER_ENABLED [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW1S
HW Access
A
Name
COUNTER_ENABLED [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW1S
HW Access
A
Name
COUNTER_ENABLED [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 23 : 0
Name COUNTER_ENABLED
Description
Alias of CTRL that only allows enabling of counters. A write access: '0': Does nothing. '1': Sets respective COUNTER_ENABLED field. A read access returns CTRL.COUNTER_ENABLED. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1110
TCPWM1_CMD_CAPTURE
20.1.26 TCPWM1_CMD_CAPTURE
Address = 0x4039000C TCPWM capture command register Address: 0x4039000C Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW1S
HW Access
RW1C
Name
COUNTER_CAPTURE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW1S
HW Access
RW1C
Name
COUNTER_CAPTURE [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW1S
HW Access
RW1C
Name
COUNTER_CAPTURE [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 23 : 0
Name COUNTER_CAPTURE
Description
Counters SW capture trigger. When written with '1', a capture trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is disabled through CTRL.COUNTER_ENABLED, the field is immediately set to '0'. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1111
TCPWM1_CMD_RELOAD
20.1.27 TCPWM1_CMD_RELOAD
Address = 0x40390010 TCPWM reload command register Address: 0x40390010 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW1S
HW Access
RW1C
Name
COUNTER_RELOAD [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW1S
HW Access
RW1C
Name
COUNTER_RELOAD [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW1S
HW Access
RW1C
Name
COUNTER_RELOAD [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 23 : 0
Name COUNTER_RELOAD
Description
Counters SW reload trigger. For HW behavior, see COUNTER_CAPTURE field. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1112
TCPWM1_CMD_STOP
20.1.28 TCPWM1_CMD_STOP
Address = 0x40390014 TCPWM stop command register Address: 0x40390014 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW1S
HW Access
RW1C
Name
COUNTER_STOP [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW1S
HW Access
RW1C
Name
COUNTER_STOP [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW1S
HW Access
RW1C
Name
COUNTER_STOP [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 23 : 0
Name COUNTER_STOP
Description
Counters SW stop trigger. For HW behavior, see COUNTER_CAPTURE field. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1113
TCPWM1_CMD_START
20.1.29 TCPWM1_CMD_START
Address = 0x40390018 TCPWM start command register Address: 0x40390018 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW1S
HW Access
RW1C
Name
COUNTER_START [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW1S
HW Access
RW1C
Name
COUNTER_START [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW1S
HW Access
RW1C
Name
COUNTER_START [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 23 : 0
Name COUNTER_START
Description
Counters SW start trigger. For HW behavior, see COUNTER_CAPTURE field. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1114
TCPWM1_INTR_CAUSE
20.1.30 TCPWM1_INTR_CAUSE
Address = 0x4039001C TCPWM Counter interrupt cause register Address: 0x4039001C Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
COUNTER_INT [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
COUNTER_INT [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
W
Name
COUNTER_INT [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 23 : 0
Name COUNTER_INT
Description
Counters interrupt signal active. If the counter is disabled through CTRL.COUNTER_ENABLED, the associated interrupt field is immediately set to '0'. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1115
TCPWM1_CNT0_COUNTER
20.1.31 TCPWM1_CNT0_COUNTER
Address = 0x40390108 Counter count register Address: 0x40390108 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
COUNTER [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
RW
Name
COUNTER [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 0
Name COUNTER
Description
16-bit counter value. It is advised to not write to this field when the counter is running. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1116
TCPWM1_CNT0_CC
20.1.32 TCPWM1_CNT0_CC
Address = 0x4039010C Counter compare/capture register Address: 0x4039010C Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
CC [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
RW
Name
CC [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 0
Name CC
Description
In CAPTURE mode, captures the counter value. In other modes, compared to counter value. Default Value: 65535
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1117
TCPWM1_CNT0_CC_BUFF
20.1.33 TCPWM1_CNT0_CC_BUFF
Address = 0x40390110 Counter buffered compare/capture register Address: 0x40390110 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
CC [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
RW
Name
CC [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 0
Name CC
Description
Additional buffer for counter CC register. Default Value: 65535
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1118
TCPWM1_CNT0_PERIOD
20.1.34 TCPWM1_CNT0_PERIOD
Address = 0x40390114 Counter period register Address: 0x40390114 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
PERIOD [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
RW
Name
PERIOD [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 0
Name PERIOD
Description
Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1. Default Value: 65535
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1119
TCPWM1_CNT0_PERIOD_BUFF
20.1.35 TCPWM1_CNT0_PERIOD_BUFF
Address = 0x40390118 Counter buffered period register Address: 0x40390118 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
PERIOD [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
RW
Name
PERIOD [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 0
Name PERIOD
Description
Additional buffer for counter PERIOD register. Default Value: 65535
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1120
21 Segment LCD Drive Registers
This section discusses the Segment LCD Drive registers. It lists all the registers in mapping tables, in address order.
21.1 Register Details
Register LCD0_ID LCD0_DIVIDER LCD0_CONTROL LCD0_DATA00 LCD0_DATA01 LCD0_DATA02 LCD0_DATA03 LCD0_DATA04 LCD0_DATA05 LCD0_DATA06 LCD0_DATA07 LCD0_DATA10 LCD0_DATA11 LCD0_DATA12 LCD0_DATA13 LCD0_DATA14 LCD0_DATA15 LCD0_DATA16 LCD0_DATA17
Address 0x403B0000 0x403B0004 0x403B0008 0x403B0100 0x403B0104 0x403B0108 0x403B010C 0x403B0110 0x403B0114 0x403B0118 0x403B011C 0x403B0200 0x403B0204 0x403B0208 0x403B020C 0x403B0210 0x403B0214 0x403B0218 0x403B021C
Description ID & Revision LCD Divider Register LCD Configuration Register LCD Pin Data Registers LCD Pin Data Registers. See LCD0_DATA00 for the details of bit fields. LCD Pin Data Registers. See LCD0_DATA00 for the details of bit fields. LCD Pin Data Registers. See LCD0_DATA00 for the details of bit fields. LCD Pin Data Registers. See LCD0_DATA00 for the details of bit fields. LCD Pin Data Registers. See LCD0_DATA00 for the details of bit fields. LCD Pin Data Registers. See LCD0_DATA00 for the details of bit fields. LCD Pin Data Registers. See LCD0_DATA00 for the details of bit fields. LCD Pin Data Registers LCD Pin Data Registers. See LCD0_DATA10 for the details of bit fields. LCD Pin Data Registers. See LCD0_DATA10 for the details of bit fields. LCD Pin Data Registers. See LCD0_DATA10 for the details of bit fields. LCD Pin Data Registers. See LCD0_DATA10 for the details of bit fields. LCD Pin Data Registers. See LCD0_DATA10 for the details of bit fields. LCD Pin Data Registers. See LCD0_DATA10 for the details of bit fields. LCD Pin Data Registers. See LCD0_DATA10 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1121
LCD0_ID
21.1.1 LCD0_ID
Address = 0x403B0000 ID & Revision Address: 0x403B0000 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
Name
ID [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
Name
ID [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
Name
REVISION [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
Name
REVISION [31:24]
Bits 31 : 16
15 : 0
Name REVISION
ID
Description
the version number is 0x0001 Default Value: 1
the ID of LCD controller peripheral is 0xF0F0 Default Value: 61680
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1122
LCD0_DIVIDER
21.1.2 LCD0_DIVIDER
Address = 0x403B0004 LCD Divider Register Address: 0x403B0004 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
SUBFR_DIV [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
SUBFR_DIV [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
DEAD_DIV [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
DEAD_DIV [31:24]
Bits 31 : 16
15 : 0
Name DEAD_DIV
SUBFR_DIV
Description
Length of the dead time period in cycles. When set to zero, no dead time period exists. Default Value: 0
Input clock frequency divide value, to generate the 1/4 sub-frame period. The sub-frame period is 4*(SUBFR_DIV+1) cycles long. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1123
LCD0_CONTROL
21.1.3 LCD0_CONTROL
Address = 0x403B0008 LCD Configuration Register Address: 0x403B0008 Retention: Retained
Bits SW Access HW Access
Name
7 None None
None
6
5
RW
R
BIAS [6:5]
Bits SW Access HW Access
Name
Bits SW Access HW Access
Name
Bits SW Access HW Access
Name
15
23
31 R W LS_EN_ST AT
14
13
None
None
None [15:12]
22
21
30
29
4 RW R OP_MODE
12
3 RW R TYPE
11
20
19
None
None
None [23:16]
28
27
None
None
None [30:24]
2
RW
R
LCD_MODE
1 RW R
HS_EN
10
9
RW
R
COM_NUM [11:8]
18
17
26
25
0 RW R LS_EN
8
16
24
Bits
Name
31
LS_EN_STAT
11 : 8
COM_NUM
Description
LS enable status bit. This bit is a copy of LS_EN that is synchronized to the low speed clock domain and back to the system clock domain. Firmware can use this bit to observe whether LS_EN has taken effect in the low speed clock domain. Firmware should never change the configuration for the LS generator without ensuring this bit is 0. The following procedure should be followed to disable the LS generator: 1. If LS_EN=0 we are done. Exit the procedure. 2. Check that LS_EN_STAT=1. If not, wait until it is. This will catch the case of a recent enable (LS_EN=1) that has not taken effect yet. 3. Set LS_EN=0. 4. Wait until LS_EN_STAT=0. Default Value: 0
The number of COM connections minus 2. So: 0: 2 COM's 1: 3 COM's ... 6: 8 COM's Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1124
LCD0_CONTROL
21.1.3
6 : 5
LCD0_CONTROL (continued)
BIAS
PWM bias selection Default Value: 0 0x0: HALF :
1/2 Bias
0x1: THIRD : 1/3 Bias
0x2: FOURTH : 1/4 Bias (not supported by LS generator)
0x3: FIFTH : 1/5 Bias (not supported by LS generator)
4
OP_MODE
Driving mode configuration Default Value: 0 0x0: PWM :
PWM Mode
0x1: CORRELATION : Digital Correlation Mode
3
TYPE
LCD driving waveform type configuration. Default Value: 0 0x0: TYPE_A :
Type A - Each frame addresses each COM pin only once with a balanced (DC=0) waveform.
0x1: TYPE_B :
Type B - Each frame addresses each COM pin twice in sequence with a positive and negative waveform that together are balanced (DC=0).
2
LCD_MODE
HS/LS Mode selection Default Value: 0 0x0: LS :
Select Low Speed (32kHz) Generator (Works in Active, Sleep and DeepSleep power modes).
0x1: HS : Select High Speed (system clock) Generator (Works in Active and Sleep power modes only).
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1125
21.1.3
1
0
LCD0_CONTROL (continued)
HS_EN LS_EN
High speed (HS) generator enable 1: enable 0: disable Default Value: 0
Low speed (LS) generator enable 1: enable 0: disable Default Value: 0
LCD0_CONTROL
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1126
LCD0_DATA00
21.1.4 LCD0_DATA00
Address = 0x403B0100 LCD Pin Data Registers Address: 0x403B0100 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
DATA [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
DATA [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
DATA [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
DATA [31:24]
Bits 31 : 0
Name DATA
Description
Bits [4i+3:4i] represent the pin data for pin [i] for COMS 0-3 (COM0 is lsb). Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1127
LCD0_DATA10
21.1.5 LCD0_DATA10
Address = 0x403B0200 LCD Pin Data Registers Address: 0x403B0200 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
DATA [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
DATA [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
DATA [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
DATA [31:24]
Bits 31 : 0
Name DATA
Description
Bits [4i+3:4i] represent the pin data for pin [i] for COMS 4-7 (COM4 is lsb). Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1128
22 USB Registers
This section discusses the USB registers. It lists all the registers in mapping tables, in address order.
22.1 Register Details
Register USBFS0_USBDEV_EP0_DR0
USBFS0_USBDEV_EP0_DR1
USBFS0_USBDEV_EP0_DR2
USBFS0_USBDEV_EP0_DR3
USBFS0_USBDEV_EP0_DR4
USBFS0_USBDEV_EP0_DR5
USBFS0_USBDEV_EP0_DR6
USBFS0_USBDEV_EP0_DR7 USBFS0_USBDEV_CR0 USBFS0_USBDEV_CR1 USBFS0_USBDEV_SIE_EP_INT_EN USBFS0_USBDEV_SIE_EP_INT_SR USBFS0_USBDEV_SIE_EP1_CNT0 USBFS0_USBDEV_SIE_EP1_CNT1 USBFS0_USBDEV_SIE_EP1_CR0 USBFS0_USBDEV_USBIO_CR0 USBFS0_USBDEV_USBIO_CR2 USBFS0_USBDEV_USBIO_CR1 USBFS0_USBDEV_DYN_RECONFIG USBFS0_USBDEV_SOF0 USBFS0_USBDEV_SOF1 USBFS0_USBDEV_SIE_EP2_CNT0
USBFS0_USBDEV_SIE_EP2_CNT1
Address
Description
0x403F0000 Control End point EP0 Data Register
0x403F0004
Control End point EP0 Data Register. See USBFS0_USBDEV_EP0_DR0 for the details of bit fields.
0x403F0008
Control End point EP0 Data Register. See USBFS0_USBDEV_EP0_DR0 for the details of bit fields.
0x403F000C
Control End point EP0 Data Register. See USBFS0_USBDEV_EP0_DR0 for the details of bit fields.
0x403F0010
Control End point EP0 Data Register. See USBFS0_USBDEV_EP0_DR0 for the details of bit fields.
0x403F0014
Control End point EP0 Data Register. See USBFS0_USBDEV_EP0_DR0 for the details of bit fields.
0x403F0018
Control End point EP0 Data Register. See USBFS0_USBDEV_EP0_DR0 for the details of bit fields.
0x403F001C
Control End point EP0 Data Register. See USBFS0_USBDEV_EP0_DR0 for the details of bit fields.
0x403F0020 USB control 0 Register
0x403F0024 USB control 1 Register
0x403F0028 USB SIE Data Endpoints Interrupt Enable Register
0x403F002C USB SIE Data Endpoint Interrupt Status
0x403F0030 Non-control endpoint count register
0x403F0034 Non-control endpoint count register
0x403F0038 Non-control endpoint's control Register
0x403F0040 USBIO Control 0 Register
0x403F0044 USBIO control 2 Register
0x403F0048 USBIO control 1 Register
0x403F0050 USB Dynamic reconfiguration register
0x403F0060 Start Of Frame Register
0x403F0064 Start Of Frame Register
0x403F0070
Non-control endpoint count register. See USBFS0_USBDEV_SIE_EP1_CNT0 for the details of bit fields.
0x403F0074
Non-control endpoint count register. See USBFS0_USBDEV_SIE_EP1_CNT1 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1129
USB Registers
Register USBFS0_USBDEV_SIE_EP2_CR0 USBFS0_USBDEV_OSCLK_DR0 USBFS0_USBDEV_OSCLK_DR1 USBFS0_USBDEV_EP0_CR USBFS0_USBDEV_EP0_CNT USBFS0_USBDEV_SIE_EP3_CNT0 USBFS0_USBDEV_SIE_EP3_CNT1 USBFS0_USBDEV_SIE_EP3_CR0 USBFS0_USBDEV_SIE_EP4_CNT0 USBFS0_USBDEV_SIE_EP4_CNT1 USBFS0_USBDEV_SIE_EP4_CR0 USBFS0_USBDEV_SIE_EP5_CNT0 USBFS0_USBDEV_SIE_EP5_CNT1 USBFS0_USBDEV_SIE_EP5_CR0 USBFS0_USBDEV_SIE_EP6_CNT0 USBFS0_USBDEV_SIE_EP6_CNT1 USBFS0_USBDEV_SIE_EP6_CR0 USBFS0_USBDEV_SIE_EP7_CNT0 USBFS0_USBDEV_SIE_EP7_CNT1 USBFS0_USBDEV_SIE_EP7_CR0 USBFS0_USBDEV_SIE_EP8_CNT0 USBFS0_USBDEV_SIE_EP8_CNT1 USBFS0_USBDEV_SIE_EP8_CR0 USBFS0_USBDEV_ARB_EP1_CFG USBFS0_USBDEV_ARB_EP1_INT_EN USBFS0_USBDEV_ARB_EP1_SR USBFS0_USBDEV_ARB_RW1_WA USBFS0_USBDEV_ARB_RW1_WA_MSB USBFS0_USBDEV_ARB_RW1_RA USBFS0_USBDEV_ARB_RW1_RA_MSB
Address
Description
0x403F0078
Non-control endpoint's control Register. See USBFS0_USBDEV_SIE_EP1_CR0 for the details of bit fields.
0x403F0080 Oscillator lock data register 0
0x403F0084 Oscillator lock data register 1
0x403F00A0 Endpoint0 control Register
0x403F00A4 Endpoint0 count Register
0x403F00B0
Non-control endpoint count register. See USBFS0_USBDEV_SIE_EP1_CNT0 for the details of bit fields.
0x403F00B4
Non-control endpoint count register. See USBFS0_USBDEV_SIE_EP1_CNT1 for the details of bit fields.
0x403F00B8
Non-control endpoint's control Register. See USBFS0_USBDEV_SIE_EP1_CR0 for the details of bit fields.
0x403F00F0
Non-control endpoint count register. See USBFS0_USBDEV_SIE_EP1_CNT0 for the details of bit fields.
0x403F00F4
Non-control endpoint count register. See USBFS0_USBDEV_SIE_EP1_CNT1 for the details of bit fields.
0x403F00F8
Non-control endpoint's control Register. See USBFS0_USBDEV_SIE_EP1_CR0 for the details of bit fields.
0x403F0130
Non-control endpoint count register. See USBFS0_USBDEV_SIE_EP1_CNT0 for the details of bit fields.
0x403F0134
Non-control endpoint count register. See USBFS0_USBDEV_SIE_EP1_CNT1 for the details of bit fields.
0x403F0138
Non-control endpoint's control Register. See USBFS0_USBDEV_SIE_EP1_CR0 for the details of bit fields.
0x403F0170
Non-control endpoint count register. See USBFS0_USBDEV_SIE_EP1_CNT0 for the details of bit fields.
0x403F0174
Non-control endpoint count register. See USBFS0_USBDEV_SIE_EP1_CNT1 for the details of bit fields.
0x403F0178
Non-control endpoint's control Register. See USBFS0_USBDEV_SIE_EP1_CR0 for the details of bit fields.
0x403F01B0
Non-control endpoint count register. See USBFS0_USBDEV_SIE_EP1_CNT0 for the details of bit fields.
0x403F01B4
Non-control endpoint count register. See USBFS0_USBDEV_SIE_EP1_CNT1 for the details of bit fields.
0x403F01B8
Non-control endpoint's control Register. See USBFS0_USBDEV_SIE_EP1_CR0 for the details of bit fields.
0x403F01F0
Non-control endpoint count register. See USBFS0_USBDEV_SIE_EP1_CNT0 for the details of bit fields.
0x403F01F4
Non-control endpoint count register. See USBFS0_USBDEV_SIE_EP1_CNT1 for the details of bit fields.
0x403F01F8
Non-control endpoint's control Register. See USBFS0_USBDEV_SIE_EP1_CR0 for the details of bit fields.
0x403F0200 Endpoint Configuration Register *1
0x403F0204 Endpoint Interrupt Enable Register *1
0x403F0208 Endpoint Interrupt Enable Register *1
0x403F0210 Endpoint Write Address value *1, *2
0x403F0214 Endpoint Write Address value *1, *2
0x403F0218 Endpoint Read Address value *1, *2
0x403F021C Endpoint Read Address value *1, *2
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1130
USB Registers
Register USBFS0_USBDEV_ARB_RW1_DR USBFS0_USBDEV_BUF_SIZE USBFS0_USBDEV_EP_ACTIVE USBFS0_USBDEV_EP_TYPE USBFS0_USBDEV_ARB_EP2_CFG USBFS0_USBDEV_ARB_EP2_INT_EN USBFS0_USBDEV_ARB_EP2_SR USBFS0_USBDEV_ARB_RW2_WA USBFS0_USBDEV_ARB_RW2_WA_MSB USBFS0_USBDEV_ARB_RW2_RA USBFS0_USBDEV_ARB_RW2_RA_MSB USBFS0_USBDEV_ARB_RW2_DR USBFS0_USBDEV_ARB_CFG USBFS0_USBDEV_USB_CLK_EN USBFS0_USBDEV_ARB_INT_EN USBFS0_USBDEV_ARB_INT_SR USBFS0_USBDEV_ARB_EP3_CFG USBFS0_USBDEV_ARB_EP3_INT_EN USBFS0_USBDEV_ARB_EP3_SR USBFS0_USBDEV_ARB_RW3_WA USBFS0_USBDEV_ARB_RW3_WA_MSB USBFS0_USBDEV_ARB_RW3_RA USBFS0_USBDEV_ARB_RW3_RA_MSB USBFS0_USBDEV_ARB_RW3_DR USBFS0_USBDEV_CWA USBFS0_USBDEV_CWA_MSB USBFS0_USBDEV_ARB_EP4_CFG USBFS0_USBDEV_ARB_EP4_INT_EN USBFS0_USBDEV_ARB_EP4_SR
Address 0x403F0220 Endpoint Data Register
Description
0x403F0230 Dedicated Endpoint Buffer Size Register *1
0x403F0238 Endpoint Active Indication Register *1
0x403F023C Endpoint Type (IN/OUT) Indication *1
0x403F0240
Endpoint Configuration Register *1. See USBFS0_USBDEV_ARB_EP1_CFG for the details of bit fields.
0x403F0244
Endpoint Interrupt Enable Register *1. See USBFS0_USBDEV_ARB_EP1_INT_EN for the details of bit fields.
0x403F0248
Endpoint Interrupt Enable Register *1. See USBFS0_USBDEV_ARB_EP1_SR for the details of bit fields.
0x403F0250
Endpoint Write Address value *1, *2. See USBFS0_USBDEV_ARB_RW1_WA for the details of bit fields.
0x403F0254
Endpoint Write Address value *1, *2. See USBFS0_USBDEV_ARB_RW1_WA_MSB for the details of bit fields.
0x403F0258
Endpoint Read Address value *1, *2. See USBFS0_USBDEV_ARB_RW1_RA for the details of bit fields.
0x403F025C
Endpoint Read Address value *1, *2. See USBFS0_USBDEV_ARB_RW1_RA_MSB for the details of bit fields.
0x403F0260 Endpoint Data Register. See USBFS0_USBDEV_ARB_RW1_DR for the details of bit fields.
0x403F0270 Arbiter Configuration Register *1
0x403F0274 USB Block Clock Enable Register
0x403F0278 Arbiter Interrupt Enable *1
0x403F027C Arbiter Interrupt Status *1
0x403F0280
Endpoint Configuration Register *1. See USBFS0_USBDEV_ARB_EP1_CFG for the details of bit fields.
0x403F0284
Endpoint Interrupt Enable Register *1. See USBFS0_USBDEV_ARB_EP1_INT_EN for the details of bit fields.
0x403F0288
Endpoint Interrupt Enable Register *1. See USBFS0_USBDEV_ARB_EP1_SR for the details of bit fields.
0x403F0290
Endpoint Write Address value *1, *2. See USBFS0_USBDEV_ARB_RW1_WA for the details of bit fields.
0x403F0294
Endpoint Write Address value *1, *2. See USBFS0_USBDEV_ARB_RW1_WA_MSB for the details of bit fields.
0x403F0298
Endpoint Read Address value *1, *2. See USBFS0_USBDEV_ARB_RW1_RA for the details of bit fields.
0x403F029C
Endpoint Read Address value *1, *2. See USBFS0_USBDEV_ARB_RW1_RA_MSB for the details of bit fields.
0x403F02A0 Endpoint Data Register. See USBFS0_USBDEV_ARB_RW1_DR for the details of bit fields.
0x403F02B0 Common Area Write Address *1
0x403F02B4 Endpoint Read Address value *1
0x403F02C0
Endpoint Configuration Register *1. See USBFS0_USBDEV_ARB_EP1_CFG for the details of bit fields.
0x403F02C4
Endpoint Interrupt Enable Register *1. See USBFS0_USBDEV_ARB_EP1_INT_EN for the details of bit fields.
0x403F02C8
Endpoint Interrupt Enable Register *1. See USBFS0_USBDEV_ARB_EP1_SR for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1131
USB Registers
Register USBFS0_USBDEV_ARB_RW4_WA USBFS0_USBDEV_ARB_RW4_WA_MSB USBFS0_USBDEV_ARB_RW4_RA USBFS0_USBDEV_ARB_RW4_RA_MSB USBFS0_USBDEV_ARB_RW4_DR USBFS0_USBDEV_DMA_THRES USBFS0_USBDEV_DMA_THRES_MSB USBFS0_USBDEV_ARB_EP5_CFG USBFS0_USBDEV_ARB_EP5_INT_EN USBFS0_USBDEV_ARB_EP5_SR USBFS0_USBDEV_ARB_RW5_WA USBFS0_USBDEV_ARB_RW5_WA_MSB USBFS0_USBDEV_ARB_RW5_RA USBFS0_USBDEV_ARB_RW5_RA_MSB USBFS0_USBDEV_ARB_RW5_DR USBFS0_USBDEV_BUS_RST_CNT USBFS0_USBDEV_ARB_EP6_CFG USBFS0_USBDEV_ARB_EP6_INT_EN USBFS0_USBDEV_ARB_EP6_SR USBFS0_USBDEV_ARB_RW6_WA USBFS0_USBDEV_ARB_RW6_WA_MSB USBFS0_USBDEV_ARB_RW6_RA USBFS0_USBDEV_ARB_RW6_RA_MSB USBFS0_USBDEV_ARB_RW6_DR USBFS0_USBDEV_ARB_EP7_CFG USBFS0_USBDEV_ARB_EP7_INT_EN USBFS0_USBDEV_ARB_EP7_SR USBFS0_USBDEV_ARB_RW7_WA USBFS0_USBDEV_ARB_RW7_WA_MSB
Address
Description
0x403F02D0
Endpoint Write Address value *1, *2. See USBFS0_USBDEV_ARB_RW1_WA for the details of bit fields.
0x403F02D4
Endpoint Write Address value *1, *2. See USBFS0_USBDEV_ARB_RW1_WA_MSB for the details of bit fields.
0x403F02D8
Endpoint Read Address value *1, *2. See USBFS0_USBDEV_ARB_RW1_RA for the details of bit fields.
0x403F02DC
Endpoint Read Address value *1, *2. See USBFS0_USBDEV_ARB_RW1_RA_MSB for the details of bit fields.
0x403F02E0 Endpoint Data Register. See USBFS0_USBDEV_ARB_RW1_DR for the details of bit fields.
0x403F02F0 DMA Burst / Threshold Configuration
0x403F02F4 DMA Burst / Threshold Configuration
0x403F0300
Endpoint Configuration Register *1. See USBFS0_USBDEV_ARB_EP1_CFG for the details of bit fields.
0x403F0304
Endpoint Interrupt Enable Register *1. See USBFS0_USBDEV_ARB_EP1_INT_EN for the details of bit fields.
0x403F0308
Endpoint Interrupt Enable Register *1. See USBFS0_USBDEV_ARB_EP1_SR for the details of bit fields.
0x403F0310
Endpoint Write Address value *1, *2. See USBFS0_USBDEV_ARB_RW1_WA for the details of bit fields.
0x403F0314
Endpoint Write Address value *1, *2. See USBFS0_USBDEV_ARB_RW1_WA_MSB for the details of bit fields.
0x403F0318
Endpoint Read Address value *1, *2. See USBFS0_USBDEV_ARB_RW1_RA for the details of bit fields.
0x403F031C
Endpoint Read Address value *1, *2. See USBFS0_USBDEV_ARB_RW1_RA_MSB for the details of bit fields.
0x403F0320 Endpoint Data Register. See USBFS0_USBDEV_ARB_RW1_DR for the details of bit fields.
0x403F0330 Bus Reset Count Register
0x403F0340
Endpoint Configuration Register *1. See USBFS0_USBDEV_ARB_EP1_CFG for the details of bit fields.
0x403F0344
Endpoint Interrupt Enable Register *1. See USBFS0_USBDEV_ARB_EP1_INT_EN for the details of bit fields.
0x403F0348
Endpoint Interrupt Enable Register *1. See USBFS0_USBDEV_ARB_EP1_SR for the details of bit fields.
0x403F0350
Endpoint Write Address value *1, *2. See USBFS0_USBDEV_ARB_RW1_WA for the details of bit fields.
0x403F0354
Endpoint Write Address value *1, *2. See USBFS0_USBDEV_ARB_RW1_WA_MSBfor the details of bit fields.
0x403F0358
Endpoint Read Address value *1, *2. See USBFS0_USBDEV_ARB_RW1_RA for the details of bit fields.
0x403F035C
Endpoint Read Address value *1, *2. See USBFS0_USBDEV_ARB_RW1_RA_MSB for the details of bit fields.
0x403F0360 Endpoint Data Register. See USBFS0_USBDEV_ARB_RW1_DR for the details of bit fields.
0x403F0380
Endpoint Configuration Register *1. See USBFS0_USBDEV_ARB_EP1_CFG for the details of bit fields.
0x403F0384
Endpoint Interrupt Enable Register *1. See USBFS0_USBDEV_ARB_EP1_INT_EN for the details of bit fields.
0x403F0388
Endpoint Interrupt Enable Register *1. See USBFS0_USBDEV_ARB_EP1_SR for the details of bit fields.
0x403F0390
Endpoint Write Address value *1, *2. See USBFS0_USBDEV_ARB_RW1_WA for the details of bit fields.
0x403F0394
Endpoint Write Address value *1, *2. See USBFS0_USBDEV_ARB_RW1_WA_MSB for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1132
USB Registers
Register USBFS0_USBDEV_ARB_RW7_RA USBFS0_USBDEV_ARB_RW7_RA_MSB USBFS0_USBDEV_ARB_RW7_DR USBFS0_USBDEV_ARB_EP8_CFG USBFS0_USBDEV_ARB_EP8_INT_EN USBFS0_USBDEV_ARB_EP8_SR USBFS0_USBDEV_ARB_RW8_WA USBFS0_USBDEV_ARB_RW8_WA_MSB USBFS0_USBDEV_ARB_RW8_RA USBFS0_USBDEV_ARB_RW8_RA_MSB USBFS0_USBDEV_ARB_RW8_DR USBFS0_USBDEV_MEM_DATA0 USBFS0_USBDEV_SOF16 USBFS0_USBDEV_OSCLK_DR16 USBFS0_USBDEV_ARB_RW1_WA16 USBFS0_USBDEV_ARB_RW1_RA16 USBFS0_USBDEV_ARB_RW1_DR16 USBFS0_USBDEV_ARB_RW2_WA16 USBFS0_USBDEV_ARB_RW2_RA16 USBFS0_USBDEV_ARB_RW2_DR16 USBFS0_USBDEV_ARB_RW3_WA16 USBFS0_USBDEV_ARB_RW3_RA16 USBFS0_USBDEV_ARB_RW3_DR16 USBFS0_USBDEV_CWA16 USBFS0_USBDEV_ARB_RW4_WA16 USBFS0_USBDEV_ARB_RW4_RA16 USBFS0_USBDEV_ARB_RW4_DR16 USBFS0_USBDEV_DMA_THRES16 USBFS0_USBDEV_ARB_RW5_WA16
Address
Description
0x403F0398
Endpoint Read Address value *1, *2. See USBFS0_USBDEV_ARB_RW1_RA for the details of bit fields.
0x403F039C
Endpoint Read Address value *1, *2. See USBFS0_USBDEV_ARB_RW1_RA_MSB for the details of bit fields.
0x403F03A0 Endpoint Data Register. See USBFS0_USBDEV_ARB_RW1_DR for the details of bit fields.
0x403F03C0
Endpoint Configuration Register *1. See USBFS0_USBDEV_ARB_EP1_CFG for the details of bit fields.
0x403F03C4
Endpoint Interrupt Enable Register *1. See USBFS0_USBDEV_ARB_EP1_INT_EN for the details of bit fields.
0x403F03C8
Endpoint Interrupt Enable Register *1. See USBFS0_USBDEV_ARB_EP1_SR for the details of bit fields.
0x403F03D0
Endpoint Write Address value *1, *2. See USBFS0_USBDEV_ARB_RW1_WA for the details of bit fields.
0x403F03D4
Endpoint Write Address value *1, *2. See USBFS0_USBDEV_ARB_RW1_WA_MSB for the details of bit fields.
0x403F03D8
Endpoint Read Address value *1, *2. See USBFS0_USBDEV_ARB_RW1_RA for the details of bit fields.
0x403F03DC
Endpoint Read Address value *1, *2. See USBFS0_USBDEV_ARB_RW1_RA_MSB for the details of bit fields.
0x403F03E0 Endpoint Data Register. See USBFS0_USBDEV_ARB_RW1_DR for the details of bit fields.
0x403F0400
DATA. This is the starting address of a register bank containing 512 registers (USBFS0_USBDEV_MEM_DATA0 to USBFS0_USBDEV_MEM_DATA511)
0x403F1060 Start Of Frame Register
0x403F1080 Oscillator lock data register
0x403F1210 Endpoint Write Address value *3
0x403F1218 Endpoint Read Address value *3
0x403F1220 Endpoint Data Register
0x403F1250
Endpoint Write Address value *3. See USBFS0_USBDEV_ARB_RW1_WA16 for the details of bit fields.
0x403F1258
Endpoint Read Address value *3. See USBFS0_USBDEV_ARB_RW1_RA16 for the details of bit fields.
0x403F1260
Endpoint Data Register. See USBFS0_USBDEV_ARB_RW1_DR16 for the details of bit fields.
0x403F1290
Endpoint Write Address value *3. See USBFS0_USBDEV_ARB_RW1_WA16 for the details of bit fields.
0x403F1298
Endpoint Read Address value *3. See USBFS0_USBDEV_ARB_RW1_RA16 for the details of bit fields.
0x403F12A0
Endpoint Data Register. See USBFS0_USBDEV_ARB_RW1_DR16 for the details of bit fields.
0x403F12B0 Common Area Write Address
0x403F12D0
Endpoint Write Address value *3. See USBFS0_USBDEV_ARB_RW1_WA16 for the details of bit fields.
0x403F12D8
Endpoint Read Address value *3. See USBFS0_USBDEV_ARB_RW1_RA16 for the details of bit fields.
0x403F12E0
Endpoint Data Register. See USBFS0_USBDEV_ARB_RW1_DR16 for the details of bit fields.
0x403F12F0 DMA Burst / Threshold Configuration
0x403F1310
Endpoint Write Address value *3. See USBFS0_USBDEV_ARB_RW1_WA16 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1133
USB Registers
Register USBFS0_USBDEV_ARB_RW5_RA16 USBFS0_USBDEV_ARB_RW5_DR16 USBFS0_USBDEV_ARB_RW6_WA16 USBFS0_USBDEV_ARB_RW6_RA16 USBFS0_USBDEV_ARB_RW6_DR16 USBFS0_USBDEV_ARB_RW7_WA16 USBFS0_USBDEV_ARB_RW7_RA16 USBFS0_USBDEV_ARB_RW7_DR16 USBFS0_USBDEV_ARB_RW8_WA16 USBFS0_USBDEV_ARB_RW8_RA16 USBFS0_USBDEV_ARB_RW8_DR16 USBFS0_USBLPM_POWER_CTL USBFS0_USBLPM_USBIO_CTL USBFS0_USBLPM_FLOW_CTL USBFS0_USBLPM_LPM_CTL USBFS0_USBLPM_LPM_STAT USBFS0_USBLPM_INTR_SIE USBFS0_USBLPM_INTR_SIE_SET USBFS0_USBLPM_INTR_SIE_MASK USBFS0_USBLPM_INTR_SIE_MASKED USBFS0_USBLPM_INTR_LVL_SEL USBFS0_USBLPM_INTR_CAUSE_HI USBFS0_USBLPM_INTR_CAUSE_MED USBFS0_USBLPM_INTR_CAUSE_LO USBFS0_USBLPM_DFT_CTL USBFS0_USBHOST_HOST_CTL0 USBFS0_USBHOST_HOST_CTL1 USBFS0_USBHOST_HOST_CTL2 USBFS0_USBHOST_HOST_ERR
Address
Description
0x403F1318
Endpoint Read Address value *3. See USBFS0_USBDEV_ARB_RW1_RA16 for the details of bit fields.
0x403F1320
Endpoint Data Register. See USBFS0_USBDEV_ARB_RW1_DR16 for the details of bit fields.
0x403F1350
Endpoint Write Address value *3. See USBFS0_USBDEV_ARB_RW1_WA16 for the details of bit fields.
0x403F1358
Endpoint Read Address value *3. See USBFS0_USBDEV_ARB_RW1_RA16 for the details of bit fields.
0x403F1360
Endpoint Data Register. See USBFS0_USBDEV_ARB_RW1_DR16 for the details of bit fields.
0x403F1390
Endpoint Write Address value *3. See USBFS0_USBDEV_ARB_RW1_WA16 for the details of bit fields.
0x403F1398
Endpoint Read Address value *3. See USBFS0_USBDEV_ARB_RW1_RA16 for the details of bit fields.
0x403F13A0
Endpoint Data Register. See USBFS0_USBDEV_ARB_RW1_DR16 for the details of bit fields.
0x403F13D0
Endpoint Write Address value *3. See USBFS0_USBDEV_ARB_RW1_WA16 for the details of bit fields.
0x403F13D8
Endpoint Read Address value *3. See USBFS0_USBDEV_ARB_RW1_RA16 for the details of bit fields.
0x403F13E0
Endpoint Data Register. See USBFS0_USBDEV_ARB_RW1_DR16 for the details of bit fields.
0x403F2000 Power Control Register
0x403F2008 USB IO Control Register
0x403F200C Flow Control Register
0x403F2010 LPM Control Register
0x403F2014 LPM Status register
0x403F2020 USB SOF, BUS RESET and EP0 Interrupt Status
0x403F2024 USB SOF, BUS RESET and EP0 Interrupt Set
0x403F2028 USB SOF, BUS RESET and EP0 Interrupt Mask
0x403F202C USB SOF, BUS RESET and EP0 Interrupt Masked
0x403F2030 Select interrupt level for each interrupt source
0x403F2034 High priority interrupt Cause register
0x403F2038 Medium priority interrupt Cause register
0x403F203C Low priority interrupt Cause register
0x403F2070 DFT control
0x403F4000 Host Control 0 Register.
0x403F4010 Host Control 1 Register.
0x403F4100 Host Control 2 Register.
0x403F4104 Host Error Status Register.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1134
Register USBFS0_USBHOST_HOST_STATUS
Address 0x403F4108 Host Status Register.
Description
USBFS0_USBHOST_HOST_FCOMP
0x403F410C Host SOF Interrupt Frame Compare Register
USBFS0_USBHOST_HOST_RTIMER
0x403F4110 Host Retry Timer Setup Register
USBFS0_USBHOST_HOST_ADDR
0x403F4114 Host Address Register
USBFS0_USBHOST_HOST_EOF
0x403F4118 Host EOF Setup Register
USBFS0_USBHOST_HOST_FRAME
0x403F411C Host Frame Setup Register
USBFS0_USBHOST_HOST_TOKEN
0x403F4120 Host Token Endpoint Register
USBFS0_USBHOST_HOST_EP1_CTL
0x403F4400 Host Endpoint 1 Control Register
USBFS0_USBHOST_HOST_EP1_STATUS
0x403F4404 Host Endpoint 1 Status Register
USBFS0_USBHOST_HOST_EP1_RW1_DR
0x403F4408 Host Endpoint 1 Data 1-Byte Register
USBFS0_USBHOST_HOST_EP1_RW2_DR
0x403F440C Host Endpoint 1 Data 2-Byte Register
USBFS0_USBHOST_HOST_EP2_CTL
0x403F4500 Host Endpoint 2 Control Register
USBFS0_USBHOST_HOST_EP2_STATUS
0x403F4504 Host Endpoint 2 Status Register
USBFS0_USBHOST_HOST_EP2_RW1_DR
0x403F4508 Host Endpoint 2 Data 1-Byte Register
USBFS0_USBHOST_HOST_EP2_RW2_DR
0x403F450C Host Endpoint 2 Data 2-Byte Register
USBFS0_USBHOST_HOST_LVL1_SEL
0x403F4800 Host Interrupt Level 1 Selection Register
USBFS0_USBHOST_HOST_LVL2_SEL
USBFS0_USBHOST_INTR_USBHOST_CAUSE_HI
USBFS0_USBHOST_INTR_USBHOST_CAUSE_MED
USBFS0_USBHOST_INTR_USBHOST_CAUSE_LO
USBFS0_USBHOST_INTR_HOST_EP_CAUSE_HI
USBFS0_USBHOST_INTR_HOST_EP_CAUSE_MED
USBFS0_USBHOST_INTR_HOST_EP_CAUSE_LO
USBFS0_USBHOST_INTR_USBHOST
0x403F4804 Host Interrupt Level 2 Selection Register 0x403F4900 Interrupt USB Host Cause High Register 0x403F4904 Interrupt USB Host Cause Medium Register 0x403F4908 Interrupt USB Host Cause Low Register 0x403F4920 Interrupt USB Host Endpoint Cause High Register 0x403F4924 Interrupt USB Host Endpoint Cause Medium Register 0x403F4928 Interrupt USB Host Endpoint Cause Low Register 0x403F4940 Interrupt USB Host Register
USBFS0_USBHOST_INTR_USBHOST_SET 0x403F4944 Interrupt USB Host Set Register
USBFS0_USBHOST_INTR_USBHOST_MASK 0x403F4948 Interrupt USB Host Mask Register
USBFS0_USBHOST_INTR_USBHOST_MASKED
0x403F494C Interrupt USB Host Masked Register
USBFS0_USBHOST_INTR_HOST_EP
0x403F4A00 Interrupt USB Host Endpoint Register
USBFS0_USBHOST_INTR_HOST_EP_SET 0x403F4A04 Interrupt USB Host Endpoint Set Register
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
USB Registers 1135
Register
Address
Description
USBFS0_USBHOST_INTR_HOST_EP_MASK 0x403F4A08 Interrupt USB Host Endpoint Mask Register
USBFS0_USBHOST_INTR_HOST_EP_MASKED
0x403F4A0C Interrupt USB Host Endpoint Masked Register
USBFS0_USBHOST_HOST_DMA_ENBL
0x403F4B00 Host DMA Enable Register
USBFS0_USBHOST_HOST_EP1_BLK
0x403F4B20 Host Endpoint 1 Block Register
USBFS0_USBHOST_HOST_EP2_BLK
0x403F4B30 Host Endpoint 2 Block Register
USB Registers
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1136
0x403F0000 USBFS0_USBDEV_EP0_DR0
22.1.1 USBFS0_USBDEV_EP0_DR0
Address = 0x403F0000 Control End point EP0 Data Register Address: 0x403F0000 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
DATA_BYTE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 0
Name DATA_BYTE
Description
This register is shared for both transmit and receive. The count in the EP0_CNT register determines the number of bytes received or to be transferred. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1137
0x403F0020 USBFS0_USBDEV_CR0
22.1.2 USBFS0_USBDEV_CR0
Address = 0x403F0020 USB control 0 Register Address: 0x403F0020 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
RW
HW Access
RW
RW
Name
USB_ENABLE
DEVICE_ADDRESS [6:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7
6 : 0
Name USB_ENABLE
DEVICE_ADDRESS
Description
This bit enables the device to respond to USB traffic. If USB bus reset is detected, this bit is cleared. Note: When USB PHY is GPIO mode(USBIO_CR1.IOMODE=0), USB bus reset is detected. Therefore, when USB PHY is GPIO mode, this bit is cleared even if this bit is set to 1. If this bit is set to 1, write this bit upon USB bus reset interrupt, and do not write to this bit during initialization steps. Default Value: 0
These bits specify the USB device address to which the SIE will respond. This address must be set by firmware and is specified by the USB Host with a SET ADDRESS command during USB enumeration. This value must be programmed by firmware when assigned during enumeration. It is not set automatically by the hardware. If USB bus reset is detected, these bits are initialized. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1138
0x403F0024 USBFS0_USBDEV_CR1
22.1.3 USBFS0_USBDEV_CR1
Address = 0x403F0024 USB control 1 Register Address: 0x403F0024 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:4]
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4
3
2
1
0
RW
RW0C
RW
RW
R
RW1S
R
R
RESERVED_3
BUS_ACTIVITY
ENABLE_LOC
K
REG_ENABLE
12
11
10
9
8
None
None
None [15:8]
20
19
18
17
16
None
None
None [23:16]
28
27
26
25
24
None
None
None [31:24]
Bits
Name
3
RESERVED_3
2
BUS_ACTIVITY
1
ENABLE_LOCK
0
REG_ENABLE
Description
Reserved Default Value: 0
The Bus Activity bit is a stickybit that detects any non-idle USB event that has occurred on the USB bus. Once set to High by the SIE to indicate the bus activity this bit retains its logical High value until firmware clears it. Default Value: 0
This bit is set to turn on the automatic frequency locking of the internal oscillator to USB traffic. Unless an external clock is being provided this bit should remain set for proper USB operation. Default Value: 0
This bit controls the operation of the internal USB regulator. For applications with supply voltages in the 5V range this bit is set high to enable the internal regulator. For device supply voltage in the 3.3V range this bit is cleared to connect the transceiver directly to the supply. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1139
0x403F0028 USBFS0_USBDEV_SIE_EP_INT_EN
22.1.4 USBFS0_USBDEV_SIE_EP_INT_EN
Address = 0x403F0028 USB SIE Data Endpoints Interrupt Enable Register Address: 0x403F0028 Retention: Not Retained
Bits SW Access HW Access
Name
7
RW
R
EP8_INTR_EN
6
RW
R
EP7_INTR_EN
5
RW
R
EP6_INTR_EN
4
RW
R
EP5_INTR_EN
3
RW
R
EP4_INTR_EN
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2 RW R EP3_INTR_EN 10
18
26
1 RW R EP2_INTR_EN
9
17
25
0 RW R EP1_INTR_EN
8
16
24
Bits
Name
7
EP8_INTR_EN
6
EP7_INTR_EN
5
EP6_INTR_EN
4
EP5_INTR_EN
3
EP4_INTR_EN
2
EP3_INTR_EN
1
EP2_INTR_EN
Description
Enables interrupt for EP8 Default Value: 0
Enables interrupt for EP7 Default Value: 0
Enables interrupt for EP6 Default Value: 0
Enables interrupt for EP5 Default Value: 0
Enables interrupt for EP4 Default Value: 0
Enables interrupt for EP3 Default Value: 0
Enables interrupt for EP2 Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1140
0x403F0028 USBFS0_USBDEV_SIE_EP_INT_EN
22.1.4
0
USBFS0_USBDEV_SIE_EP_INT_EN (continued)
EP1_INTR_EN
Enables interrupt for EP1 Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1141
0x403F002C USBFS0_USBDEV_SIE_EP_INT_SR
22.1.5 USBFS0_USBDEV_SIE_EP_INT_SR
Address = 0x403F002C USB SIE Data Endpoint Interrupt Status Address: 0x403F002C Retention: Not Retained
Bits SW Access HW Access
Name
7 RW1C RW1S EP8_INTR
6 RW1C RW1S EP7_INTR
5 RW1C RW1S EP6_INTR
4 RW1C RW1S EP5_INTR
3 RW1C RW1S EP4_INTR
2 RW1C RW1S EP3_INTR
1 RW1C RW1S EP2_INTR
0 RW1C RW1S EP1_INTR
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
7
EP8_INTR
6
EP7_INTR
5
EP6_INTR
4
EP5_INTR
3
EP4_INTR
2
EP3_INTR
1
EP2_INTR
0
EP1_INTR
Description
Interrupt status for EP8 Default Value: 0
Interrupt status for EP7 Default Value: 0
Interrupt status for EP6 Default Value: 0
Interrupt status for EP5 Default Value: 0
Interrupt status for EP4 Default Value: 0
Interrupt status for EP3 Default Value: 0
Interrupt status for EP2 Default Value: 0
Interrupt status for EP1 Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1142
0x403F0030 USBFS0_USBDEV_SIE_EP1_CNT0
22.1.6 USBFS0_USBDEV_SIE_EP1_CNT0
Address = 0x403F0030 Non-control endpoint count register Address: 0x403F0030 Retention: Not Retained
Bits
7
6
5
4
3
SW Access
RW
RW0C
None
HW Access
RW
RW1S
None
Name
DATA_- DATA_VAL-
TOGGLE
ID
None [5:3]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
0
RW
RW
DATA_COUNT_MSB [2:0]
10
9
8
18
17
16
26
25
24
Bits 7 6
2 : 0
Name DATA_TOGGLE DATA_VALID
DATA_COUNT_MSB
Description
This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. Default Value: 0
This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. Default Value: 0
0x0: DATA_ERROR : No ACK'd transactions since bit was last cleared.
0x1: DATA_VALID : Indicates a transaction ended with an ACK.
These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1143
0x403F0034 USBFS0_USBDEV_SIE_EP1_CNT1
22.1.7 USBFS0_USBDEV_SIE_EP1_CNT1
Address = 0x403F0034 Non-control endpoint count register Address: 0x403F0034 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
DATA_COUNT [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 0
Name DATA_COUNT
Description
These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11bit count indicates the number of data bytes in a transaction. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1144
0x403F0038 USBFS0_USBDEV_SIE_EP1_CR0
22.1.8 USBFS0_USBDEV_SIE_EP1_CR0
Address = 0x403F0038 Non-control endpoint's control Register Address: 0x403F0038 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
RWC
RW
RWC
RW
HW Access
R
RW1S
R
RW1S
RW
Name
STALL
ER-
NA-
ACKED_TX
R_IN_TXN K_INT_EN
N
MODE [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
7
STALL
6
ERR_IN_TXN
5
NAK_INT_EN
4
ACKED_TXN
Description
When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. Default Value: 0
The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register. Default Value: 0
When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. Default Value: 0
The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. Default Value: 0
0x0: ACKED_NO :
No ACK'd transactions since bit was last cleared.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1145
0x403F0038 USBFS0_USBDEV_SIE_EP1_CR0
22.1.8
USBFS0_USBDEV_SIE_EP1_CR0 (continued)
0x1: ACKED_YES : Indicates a transaction ended with an ACK.
3 : 0
MODE
The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. Default Value: 0
0x0: DISABLE :
Ignore all USB traffic to this endpoint
0x1: NAK_INOUT :
SETUP: Accept IN: NAK OUT: NAK
0x2: STATUS_OUT_ONLY :
SETUP: Accept IN: STALL OUT: ACK 0B tokens, NAK others
0x3: STALL_INOUT :
SETUP: Accept IN: STALL OUT: STALL
0x5: ISO_OUT :
SETUP: Ignore IN: Ignore OUT: Accept Isochronous OUT token
0x6: STATUS_IN_ONLY :
SETUP: Accept IN: Respond with 0B data OUT: Stall
0x7: ISO_IN :
SETUP: Ignore IN: Accept Isochronous IN token OUT: Ignore
0x8: NAK_OUT :
SETUP: Ignore IN: Ignore OUT: NAK
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1146
0x403F0038 USBFS0_USBDEV_SIE_EP1_CR0
22.1.8
USBFS0_USBDEV_SIE_EP1_CR0 (continued)
0x9: ACK_OUT :
SETUP: Ignore IN: Ignore OUT: Accept data and ACK if STALL=0, STALL otherwise. Change to MODE=8 after one succesfull OUT token.
0xb: ACK_OUT_STATUS_IN :
SETUP: Accept IN: Respond with 0B data OUT: Accept data
0xc: NAK_IN :
SETUP: Ignore IN: NAK OUT: Ignore
0xd: ACK_IN :
SETUP: Ignore IN: Respond to IN with data if STALL=0, STALL otherwise OUT: Ignore
0xf: ACK_IN_STATUS_OUT :
SETUP: Accept IN: Respond to IN with data OUT: ACK 0B tokens, NAK others
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1147
0x403F0040 USBFS0_USBDEV_USBIO_CR0
22.1.9 USBFS0_USBDEV_USBIO_CR0
Address = 0x403F0040 USBIO Control 0 Register Address: 0x403F0040 Retention: Retained
Bits
7
6
5
4
SW Access
RW
RW
RW
HW Access
R
R
R
Name
TEN
TSE0
TD
3
2
None
None
None [4:1]
1
0
R
W
RD
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
7
TEN
6
TSE0
5
TD
Description USB Transmit Enable. This is used to manually transmit on the D+ and D- pins. Normally this bit should be cleared to allow the internal SIE to drive the pins. The most common reason for manually transmitting is to force a resume state on the bus. Default Value: 0 Transmit Single-Ended Zero. SE0: both D+ and D- low. No effect if TEN=0. Default Value: 0 Transmit Data. Transmit a USB J or K state on the USB bus. No effect if TEN=0 or TSE0=1. Default Value: 0 0x0: DIFF_K :
Force USB K state (D+ is low D- is high).
0x1: DIFF_J :
Force USB J state (D+ is high D- is low).
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1148
0x403F0040 USBFS0_USBDEV_USBIO_CR0
22.1.9
0
USBFS0_USBDEV_USBIO_CR0 (continued)
RD
Received Data. This read only bit gives the state of the USB differential receiver when IOMODE
bit is '0' and USB doesn't transmit. This bit is valid if USB Device.
If D+=D- (SE0), this value is undefined.
Default Value: X
0x0: DIFF_LOW :
D+ < D- (K state)
0x1: DIFF_HIGH : D+ > D- (J state)
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1149
0x403F0044 USBFS0_USBDEV_USBIO_CR2
22.1.10 USBFS0_USBDEV_USBIO_CR2
Address = 0x403F0044 USBIO control 2 Register Address: 0x403F0044 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
RW
R
HW Access
R
R
R
Name
RESERVED_7
TEST_PKT
RESERVED_5_0 [5:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 6
5 : 0
Name RESERVED_7 TEST_PKT
RESERVED_5_0
Description
Reserved Default Value: 0
This bit enables the device to transmit a packet in response to an internally generated IN packet. When set, one packet will be generated. Default Value: 0
Reserved Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1150
0x403F0048 USBFS0_USBDEV_USBIO_CR1
22.1.11 USBFS0_USBDEV_USBIO_CR1
Address = 0x403F0048 USBIO control 1 Register Address: 0x403F0048 Retention: Retained
Bits SW Access HW Access
Name
7
6
None
None
None [7:6]
5 RW R
IOMODE
4
3
None
None
None [4:3]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2 RW W RESERVED_2
10
1 R W DPO
9
18
17
26
25
0 R W DMO 8
16
24
Bits
Name
5
IOMODE
2
RESERVED_2
1
DPO
0
DMO
Description
This bit allows the D+ and D- pins to be configured for either USB mode or bit-banged modes. If this bit is set the DMI and DPI bits are used to drive the D- and D+ pins. Default Value: 1
Reserved Default Value: X
This read only bit gives the state of the D+ pin when IOMODE bit is '0' and USB doesn't transmit. This bit displays the output value of D+ pin when USB transmits SE0 or data. This bit is valid if USB Device. Default Value: X
This read only bit gives the state of the D- pin when IOMODE bit is '0' and USB doesn't transmit. This bit is '0' when USB transmits SE0, and this bit is '1' when USB transmits other than SE0. This bit is valid if USB Device. Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1151
0x403F0050 USBFS0_USBDEV_DYN_RECONFIG
22.1.12 USBFS0_USBDEV_DYN_RECONFIG
Address = 0x403F0050 USB Dynamic reconfiguration register Address: 0x403F0050 Retention: Not Retained
Bits SW Access HW Access
Name
7
6
5
4
3
2
1
None
R
RW
None
W
R
None [7:5]
DYN_RECON-
FIG_RDY_ STS
DYN_RECONFIG_EPNO [3:1]
Bits
15
14
13
12
11
10
9
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
SW Access
None
HW Access
None
Name
None [31:24]
0 RW R DYN_CONFIG_EN
8
16
24
Bits 4
3 : 1
0
Name DYN_RECONFIG_RDY_STS
DYN_RECONFIG_EPNO
DYN_CONFIG_EN
Description
This bit indicates the ready status for the dynamic reconfiguration, when set to 1, indicates the block is ready for reconfiguration. Default Value: 0
These bits indicates the EP number for which reconfiguration is required when dyn_config_en bit is set to 1. Default Value: 0
This bit is used to enable the dynamic re-configuration for the selected EP. If set to 1, indicates the reconfiguration required for selected EP. Use 0 for EP1, 1 for EP2, etc. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1152
0x403F0060 USBFS0_USBDEV_SOF0
22.1.13 USBFS0_USBDEV_SOF0
Address = 0x403F0060 Start Of Frame Register Address: 0x403F0060 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
RW
Name
FRAME_NUMBER [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 0
Name FRAME_NUMBER
Description
It has the lower 8 bits [7:0] of the SOF frame number. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1153
0x403F0064 USBFS0_USBDEV_SOF1
22.1.14 USBFS0_USBDEV_SOF1
Address = 0x403F0064 Start Of Frame Register Address: 0x403F0064 Retention: Not Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:3]
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4
3
12
11
None
None
None [15:8]
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
2
1
0
R
RW
FRAME_NUMBER_MSB [2:0]
10
9
8
18
17
16
26
25
24
Bits 2 : 0
Name FRAME_NUMBER_MSB
Description
It has the upper 3 bits [10:8] of the SOF frame number. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1154
0x403F0080 USBFS0_USBDEV_OSCLK_DR0
22.1.15 USBFS0_USBDEV_OSCLK_DR0
Address = 0x403F0080 Oscillator lock data register 0 Address: 0x403F0080 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
ADDER [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 0
Name ADDER
Description
These bits return the lower 8 bits of the oscillator locking circuits adder output. Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1155
0x403F0084 USBFS0_USBDEV_OSCLK_DR1
22.1.16 USBFS0_USBDEV_OSCLK_DR1
Address = 0x403F0084 Oscillator lock data register 1 Address: 0x403F0084 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
R
HW Access
None
W
Name
None
ADDER_MSB [6:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 6 : 0
Name ADDER_MSB
Description
These bits return the upper 7 bits of the oscillator locking circuits adder output. Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1156
0x403F00A0 USBFS0_USBDEV_EP0_CR
22.1.17 USBFS0_USBDEV_EP0_CR
Address = 0x403F00A0 Endpoint0 control Register Address: 0x403F00A0 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RWC
RWC
RWC
RWC
RW
HW Access
RW1S
RW1S
RW1S
RW1S
RW
Name
SETUP_RCVD
IN_RCVD
OUT_RCVD
ACKED_TX N
MODE [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
7
SETUP_RCVD
6
IN_RCVD
5
OUT_RCVD
Description
When set this bit indicates a valid SETUP packet was received and ACKed. This bit is forced HIGH from the start of the data packet phase of the SETUP transaction until the start of the ACK packet returned by the SIE. The CPU is prevented from clearing this bit during this interval. After this interval the bit will remain set until cleared by firmware. While this bit is set to '1' the CPU cannot write to the EP0_DRx registers. This prevents firmware from overwriting an incoming SETUP transaction before firmware has a chance to read the SETUP data. This bit is cleared by any non-locked writes to the register. Default Value: 0
When set this bit indicates a valid IN packet has been received. This bit is updated to '1' after the host acknowledges an IN data packet. When clear this bit indicates either no IN has been received or that the host did not acknowledge the IN data by sending ACK handshake. It is cleared by any writes to the register. Default Value: 0
When set this bit indicates a valid OUT packet has been received and ACKed. This bit is updated to '1' after the last received packet in an OUT transaction. When clear this bit indicates no OUT received. It is cleared by any writes to the register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1157
0x403F00A0 USBFS0_USBDEV_EP0_CR
22.1.17 USBFS0_USBDEV_EP0_CR (continued)
4
ACKED_TXN
The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register. Default Value: 0
0x0: ACKED_NO :
No ACK'd transactions since bit was last cleared.
0x1: ACKED_YES : Indicates a transaction ended with an ACK.
3 : 0
MODE
The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. Default Value: 0
0x0: DISABLE :
Ignore all USB traffic to this endpoint
0x1: NAK_INOUT :
SETUP: Accept IN: NAK OUT: NAK
0x2: STATUS_OUT_ONLY :
SETUP: Accept IN: STALL OUT: ACK 0B tokens, NAK others
0x3: STALL_INOUT :
SETUP: Accept IN: STALL OUT: STALL
0x5: ISO_OUT :
SETUP: Ignore IN: Ignore OUT: Accept Isochronous OUT token
0x6: STATUS_IN_ONLY :
SETUP: Accept IN: Respond with 0B data OUT: Stall
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1158
0x403F00A0 USBFS0_USBDEV_EP0_CR
22.1.17
USBFS0_USBDEV_EP0_CR (continued)
0x7: ISO_IN :
SETUP: Ignore IN: Accept Isochronous IN token OUT: Ignore
0x8: NAK_OUT :
SETUP: Ignore IN: Ignore OUT: NAK
0x9: ACK_OUT :
SETUP: Ignore IN: Ignore OUT: Accept data and ACK if STALL=0, STALL otherwise. Change to MODE=8 after one succesfull OUT token.
0xb: ACK_OUT_STATUS_IN :
SETUP: Accept IN: Respond with 0B data OUT: Accept data
0xc: NAK_IN :
SETUP: Ignore IN: NAK OUT: Ignore
0xd: ACK_IN :
SETUP: Ignore IN: Respond to IN with data if STALL=0, STALL otherwise OUT: Ignore
0xf: ACK_IN_STATUS_OUT :
SETUP: Accept IN: Respond to IN with data OUT: ACK 0B tokens, NAK others
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1159
0x403F00A4 USBFS0_USBDEV_EP0_CNT
22.1.18 USBFS0_USBDEV_EP0_CNT
Address = 0x403F00A4 Endpoint0 count Register Address: 0x403F00A4 Retention: Not Retained
Bits SW Access HW Access
Name
7
RW
RW
DATA_TOGGLE
6
RW0C
RW1S
DATA_VALID
5
4
None
None
None [5:4]
3
2
1
0
RW
RW
BYTE_COUNT [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
7
DATA_TOGGLE
6
DATA_VALID
Description This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. Default Value: 0 This bit is used for OUT/SETUP transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. Default Value: 0 0x0: DATA_ERROR :
No ACK'd transactions since bit was last cleared.
0x1: DATA_VALID :
Indicates a transaction ended with an ACK.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1160
0x403F00A4 USBFS0_USBDEV_EP0_CNT
22.1.18 USBFS0_USBDEV_EP0_CNT (continued)
3 : 0
BYTE_COUNT
These bits indicate the number of data bytes in a transaction. For IN transactions firmware loads the count with the number of bytes to be transmitted to the host from the endpoint FIFO. Valid values are 0 to 8. For OUT or SETUP transactions the count is updated by hardware to the number of data bytes received plus two for the CRC bytes. Valid values are 2 to 10. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1161
0x403F0200 USBFS0_USBDEV_ARB_EP1_CFG
22.1.19 USBFS0_USBDEV_ARB_EP1_CFG
Address = 0x403F0200 Endpoint Configuration Register *1 Address: 0x403F0200 Retention: Not Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:4]
4
3
RW
R
RESET_PTR
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
RW
R
CRC_BYPASS
1 RW R
DMA_REQ
0
RW
R
IN_DATA_RDY
10
9
8
18
17
16
26
25
24
Bits
Name
3
RESET_PTR
2
CRC_BYPASS
Description Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction. Default Value: 0 0x0: RESET_KRYPTON :
Do not Reset Pointer; Krypton Backward compatibility mode
0x1: RESET_NORMAL :
Reset Pointer; recommended value for reduction of CPU Configuration Writes.
Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1162
0x403F0200 USBFS0_USBDEV_ARB_EP1_CFG
22.1.19
USBFS0_USBDEV_ARB_EP1_CFG (continued)
0x0: CRC_NORMAL :
No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s
0x1: CRC_BYPASS :
CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s
1
DMA_REQ
0
IN_DATA_RDY
Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. Default Value: 0
Indication that Endpoint Packet Data is Ready in Main memory Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1163
0x403F0204 USBFS0_USBDEV_ARB_EP1_INT_EN
22.1.20 USBFS0_USBDEV_ARB_EP1_INT_EN
Address = 0x403F0204 Endpoint Interrupt Enable Register *1 Address: 0x403F0204 Retention: Not Retained
Bits SW Access HW Access
Name
7
6
None
None
None [7:6]
5
RW
R
DMA_TERMIN_EN
4
RW
R
ERR_INT_EN
3
2
RW
RW
R
R
BUF_UNDE BUF_OVER
R_EN
_EN
1
RW
R
DMA_GNT_EN
0
RW
R
IN_BUF_FULL_EN
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
Description
5
DMA_TERMIN_EN
Endpoint DMA Terminated Enable
Default Value: 0
4
ERR_INT_EN
Endpoint Error in Transaction Interrupt Enable Default Value: 0
3
BUF_UNDER_EN
Endpoint Buffer Underflow Enable
Default Value: 0
2
BUF_OVER_EN
Endpoint Buffer Overflow Enable Default Value: 0
1
DMA_GNT_EN
Endpoint DMA Grant Enable Default Value: 0
0
IN_BUF_FULL_EN
IN Endpoint Local Buffer Full Enable
Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1164
0x403F0208 USBFS0_USBDEV_ARB_EP1_SR
22.1.21 USBFS0_USBDEV_ARB_EP1_SR
Address = 0x403F0208 Endpoint Interrupt Enable Register *1 Address: 0x403F0208 Retention: Not Retained
Bits SW Access HW Access
Name
7
6
None
None
None [7:6]
5
RW1C
RW1S
DMA_TERMIN
4 None None
None
3
2
RW1C
RW1C
RW1S
RW1S
BUF_UNDE R
BUF_OVER
1 RW1C RW1S
DMA_GNT
0
RW1C
RW1S
IN_BUF_FULL
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
5
DMA_TERMIN
3
BUF_UNDER
2
BUF_OVER
1
DMA_GNT
0
IN_BUF_FULL
Description
Endpoint DMA Terminated Interrupt Default Value: 0
Endpoint Buffer Underflow Interrupt Default Value: 0
Endpoint Buffer Overflow Interrupt Default Value: 0
Endpoint DMA Grant Interrupt Default Value: 0
IN Endpoint Local Buffer Full Interrupt Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1165
0x403F0210 USBFS0_USBDEV_ARB_RW1_WA
22.1.22 USBFS0_USBDEV_ARB_RW1_WA
Address = 0x403F0210 Endpoint Write Address value *1, *2 Address: 0x403F0210 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
WA [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 0
Name WA
Description
Write Address for EP Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1166
0x403F0214 USBFS0_USBDEV_ARB_RW1_WA_MSB
22.1.23 USBFS0_USBDEV_ARB_RW1_WA_MSB
Address = 0x403F0214 Endpoint Write Address value *1, *2 Address: 0x403F0214 Retention: Not Retained
Bits
7
6
5
4
3
2
SW Access
None
HW Access
None
Name
None [7:1]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
WA_MSB
Description
Write Address for EP Default Value: 0
1
0
RW
RW
WA_MSB
9
8
17
16
25
24
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1167
0x403F0218 USBFS0_USBDEV_ARB_RW1_RA
22.1.24 USBFS0_USBDEV_ARB_RW1_RA
Address = 0x403F0218 Endpoint Read Address value *1, *2 Address: 0x403F0218 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
RA [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 0
Name RA
Description
Read Address for EP Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1168
0x403F021C USBFS0_USBDEV_ARB_RW1_RA_MSB
22.1.25 USBFS0_USBDEV_ARB_RW1_RA_MSB
Address = 0x403F021C Endpoint Read Address value *1, *2 Address: 0x403F021C Retention: Not Retained
Bits
7
6
5
4
3
2
SW Access
None
HW Access
None
Name
None [7:1]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
RA_MSB
Description
Read Address for EP Default Value: 0
1
0
RW
RW
RA_MSB
9
8
17
16
25
24
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1169
0x403F0220 USBFS0_USBDEV_ARB_RW1_DR
22.1.26 USBFS0_USBDEV_ARB_RW1_DR
Address = 0x403F0220 Endpoint Data Register Address: 0x403F0220 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
DR [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 0
Name DR
Description
Data Register for EP ; This register is linked to the memory, hence reset value is undefined Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1170
0x403F0230 USBFS0_USBDEV_BUF_SIZE
22.1.27 USBFS0_USBDEV_BUF_SIZE
Address = 0x403F0230 Dedicated Endpoint Buffer Size Register *1 Address: 0x403F0230 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
RW
HW Access
R
R
Name
OUT_BUF [7:4]
IN_BUF [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 4
3 : 0
Name OUT_BUF
IN_BUF
Description
Buffer size for OUT Endpoints. Default Value: 0
Buffer size for IN Endpoints. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1171
0x403F0238 USBFS0_USBDEV_EP_ACTIVE
22.1.28 USBFS0_USBDEV_EP_ACTIVE
Address = 0x403F0238 Endpoint Active Indication Register *1 Address: 0x403F0238 Retention: Not Retained
Bits SW Access HW Access
Name
7 RW R EP8_ACT
6 RW R EP7_ACT
5 RW R EP6_ACT
4 RW R EP5_ACT
3 RW R EP4_ACT
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2 RW R EP3_ACT 10
18
26
1 RW R EP2_ACT
9
17
25
0 RW R EP1_ACT
8
16
24
Bits
Name
7
EP8_ACT
6
EP7_ACT
5
EP6_ACT
4
EP5_ACT
3
EP4_ACT
2
EP3_ACT
1
EP2_ACT
0
EP1_ACT
Description
Indicates that Endpoint is currently active. Default Value: 0
Indicates that Endpoint is currently active. Default Value: 0
Indicates that Endpoint is currently active. Default Value: 0
Indicates that Endpoint is currently active. Default Value: 0
Indicates that Endpoint is currently active. Default Value: 0
Indicates that Endpoint is currently active. Default Value: 0
Indicates that Endpoint is currently active. Default Value: 0
Indicates that Endpoint is currently active. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1172
0x403F023C USBFS0_USBDEV_EP_TYPE
22.1.29 USBFS0_USBDEV_EP_TYPE
Address = 0x403F023C Endpoint Type (IN/OUT) Indication *1 Address: 0x403F023C Retention: Not Retained
Bits SW Access HW Access
Name
7 RW R EP8_TYP
6 RW R EP7_TYP
5 RW R EP6_TYP
4 RW R EP5_TYP
3 RW R EP4_TYP
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2 RW R EP3_TYP 10
18
26
1 RW R EP2_TYP
9
17
25
0 RW R EP1_TYP
8
16
24
Bits
Name
7
EP8_TYP
6
EP7_TYP
Description Endpoint Type Indication. Default Value: 0 0x0: EP_IN : IN outpoint
0x1: EP_OUT : OUT outpoint
Endpoint Type Indication. Default Value: 0 0x0: EP_IN : IN outpoint
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1173
22.1.29
USBFS0_USBDEV_EP_TYPE (continued)
0x1: EP_OUT : OUT outpoint
5
EP6_TYP
Endpoint Type Indication. Default Value: 0 0x0: EP_IN :
IN outpoint
0x1: EP_OUT : OUT outpoint
4
EP5_TYP
Endpoint Type Indication. Default Value: 0 0x0: EP_IN :
IN outpoint
0x1: EP_OUT : OUT outpoint
3
EP4_TYP
Endpoint Type Indication. Default Value: 0 0x0: EP_IN :
IN outpoint
0x1: EP_OUT : OUT outpoint
2
EP3_TYP
Endpoint Type Indication. Default Value: 0 0x0: EP_IN :
IN outpoint
0x1: EP_OUT : OUT outpoint
1
EP2_TYP
Endpoint Type Indication. Default Value: 0 0x0: EP_IN :
IN outpoint
0x403F023C USBFS0_USBDEV_EP_TYPE
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1174
22.1.29
USBFS0_USBDEV_EP_TYPE (continued)
0x1: EP_OUT : OUT outpoint
0
EP1_TYP
Endpoint Type Indication. Default Value: 0 0x0: EP_IN :
IN outpoint
0x1: EP_OUT : OUT outpoint
0x403F023C USBFS0_USBDEV_EP_TYPE
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1175
0x403F0270 USBFS0_USBDEV_ARB_CFG
22.1.30 USBFS0_USBDEV_ARB_CFG
Address = 0x403F0270 Arbiter Configuration Register *1 Address: 0x403F0270 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
RW
RW
None
HW Access
R
R
R
None
Name
CFG_CMP
DMA_CFG [6:5]
AUTO_MEM
None
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
7
CFG_CMP
6 : 5
DMA_CFG
Description Register Configuration Complete Indication. Posedge is detected on this bit. Hence a 0 to 1 transition is required. Default Value: 0 DMA Access Configuration. Default Value: 0 0x0: DMA_NONE :
No DMA
0x1: DMA_MANUAL :
Manual DMA
0x2: DMA_AUTO :
Auto DMA
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1176
0x403F0270 USBFS0_USBDEV_ARB_CFG
22.1.30 USBFS0_USBDEV_ARB_CFG (continued)
4
AUTO_MEM
Enables Auto Memory Configuration. Manual memory configuration by default. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1177
0x403F0274 USBFS0_USBDEV_USB_CLK_EN
22.1.31 USBFS0_USBDEV_USB_CLK_EN
Address = 0x403F0274 USB Block Clock Enable Register Address: 0x403F0274 Retention: Not Retained
Bits
7
6
5
4
3
2
SW Access
None
HW Access
None
Name
None [7:1]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
CSR_CLK_EN
Description
Clock Enable for Core Logic clocked by AHB bus clock Default Value: 0
1
0
RW
R
CSR_CLK_EN
9
8
17
16
25
24
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1178
0x403F0278 USBFS0_USBDEV_ARB_INT_EN
22.1.32 USBFS0_USBDEV_ARB_INT_EN
Address = 0x403F0278 Arbiter Interrupt Enable *1 Address: 0x403F0278 Retention: Not Retained
Bits SW Access HW Access
Name
7
RW
R
EP8_INTR_EN
6
RW
R
EP7_INTR_EN
5
RW
R
EP6_INTR_EN
4
RW
R
EP5_INTR_EN
3
RW
R
EP4_INTR_EN
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2 RW R EP3_INTR_EN 10
18
26
1 RW R EP2_INTR_EN
9
17
25
0 RW R EP1_INTR_EN
8
16
24
Bits
Name
7
EP8_INTR_EN
6
EP7_INTR_EN
5
EP6_INTR_EN
4
EP5_INTR_EN
3
EP4_INTR_EN
2
EP3_INTR_EN
1
EP2_INTR_EN
Description
Enables interrupt for EP8 Default Value: 0
Enables interrupt for EP7 Default Value: 0
Enables interrupt for EP6 Default Value: 0
Enables interrupt for EP5 Default Value: 0
Enables interrupt for EP4 Default Value: 0
Enables interrupt for EP3 Default Value: 0
Enables interrupt for EP2 Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1179
0x403F0278 USBFS0_USBDEV_ARB_INT_EN
22.1.32 USBFS0_USBDEV_ARB_INT_EN (continued)
0
EP1_INTR_EN
Enables interrupt for EP1 Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1180
0x403F027C USBFS0_USBDEV_ARB_INT_SR
22.1.33 USBFS0_USBDEV_ARB_INT_SR
Address = 0x403F027C Arbiter Interrupt Status *1 Address: 0x403F027C Retention: Not Retained
Bits SW Access HW Access
Name
7 R RW1S EP8_INTR
6 R RW1S EP7_INTR
5 R RW1S EP6_INTR
4 R RW1S EP5_INTR
3 R RW1S EP4_INTR
2 R RW1S EP3_INTR
1 R RW1S EP2_INTR
0 R RW1S EP1_INTR
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
7
EP8_INTR
6
EP7_INTR
5
EP6_INTR
4
EP5_INTR
3
EP4_INTR
2
EP3_INTR
1
EP2_INTR
0
EP1_INTR
Description
Interrupt status for EP8 Default Value: 0
Interrupt status for EP7 Default Value: 0
Interrupt status for EP6 Default Value: 0
Interrupt status for EP5 Default Value: 0
Interrupt status for EP4 Default Value: 0
Interrupt status for EP3 Default Value: 0
Interrupt status for EP2 Default Value: 0
Interrupt status for EP1 Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1181
0x403F02B0 USBFS0_USBDEV_CWA
22.1.34 USBFS0_USBDEV_CWA
Address = 0x403F02B0 Common Area Write Address *1 Address: 0x403F02B0 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
CWA [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 0
Name CWA
Description
Write Address for Common Area Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1182
0x403F02B4 USBFS0_USBDEV_CWA_MSB
22.1.35 USBFS0_USBDEV_CWA_MSB
Address = 0x403F02B4 Endpoint Read Address value *1 Address: 0x403F02B4 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
RW
Name
None [7:1]
CWA_MSB
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
CWA_MSB
Description
Write Address for Common Area Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1183
0x403F02F0 USBFS0_USBDEV_DMA_THRES
22.1.36 USBFS0_USBDEV_DMA_THRES
Address = 0x403F02F0 DMA Burst / Threshold Configuration Address: 0x403F02F0 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
DMA_THS [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 0
Name DMA_THS
Description
DMA Threshold count Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1184
0x403F02F4 USBFS0_USBDEV_DMA_THRES_MSB
22.1.37 USBFS0_USBDEV_DMA_THRES_MSB
Address = 0x403F02F4 DMA Burst / Threshold Configuration Address: 0x403F02F4 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
RW
Name
None [7:1]
DMA_THS_ MSB
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
DMA_THS_MSB
Description
DMA Threshold count Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1185
0x403F0330 USBFS0_USBDEV_BUS_RST_CNT
22.1.38 USBFS0_USBDEV_BUS_RST_CNT
Address = 0x403F0330 Bus Reset Count Register Address: 0x403F0330 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:4]
bus_rst_cnt [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 3 : 0
Name bus_rst_cnt
Description
Bus Reset Count Length Default Value: 10
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1186
0x403F0400 USBFS0_USBDEV_MEM_DATA0
22.1.39 USBFS0_USBDEV_MEM_DATA0
Address = 0x403F0400 DATA Address: 0x403F0400 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
DR [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 0
Name DR
Description
Data Register for EP ; This register is linked to the memory, hence reset value is undefined Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1187
0x403F1060 USBFS0_USBDEV_SOF16
22.1.40 USBFS0_USBDEV_SOF16
Address = 0x403F1060 Start Of Frame Register Address: 0x403F1060 Retention: Not Retained
Bits
7
6
5
4
3
SW Access
R
HW Access
RW
Name
FRAME_NUMBER16 [7:0]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:11]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
0
10
9
8
R
RW
FRAME_NUMBER16 [10:8]
18
17
16
26
25
24
Bits 10 : 0
Name FRAME_NUMBER16
Description
The frame number (11b) Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1188
0x403F1080 USBFS0_USBDEV_OSCLK_DR16
22.1.41 USBFS0_USBDEV_OSCLK_DR16
Address = 0x403F1080 Oscillator lock data register Address: 0x403F1080 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
ADDER16 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
R
HW Access
None
W
Name
None
ADDER16 [14:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 14 : 0
Name ADDER16
Description
These bits return the oscillator locking circuits adder output. Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1189
0x403F1210 USBFS0_USBDEV_ARB_RW1_WA16
22.1.42 USBFS0_USBDEV_ARB_RW1_WA16
Address = 0x403F1210 Endpoint Write Address value *3 Address: 0x403F1210 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
WA16 [7:0]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:9]
9
8
RW
RW
WA16
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 8 : 0
Name WA16
Description
Write Address for EP Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1190
0x403F1218 USBFS0_USBDEV_ARB_RW1_RA16
22.1.43 USBFS0_USBDEV_ARB_RW1_RA16
Address = 0x403F1218 Endpoint Read Address value *3 Address: 0x403F1218 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
RA16 [7:0]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:9]
9
8
RW
RW
RA16
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 8 : 0
Name RA16
Description
Read Address for EP Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1191
0x403F1220 USBFS0_USBDEV_ARB_RW1_DR16
22.1.44 USBFS0_USBDEV_ARB_RW1_DR16
Address = 0x403F1220 Endpoint Data Register Address: 0x403F1220 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
DR16 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
RW
Name
DR16 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 0
Name DR16
Description
Data Register for EP ; This register is linked to the memory, hence reset value is undefined Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1192
0x403F12B0 USBFS0_USBDEV_CWA16
22.1.45 USBFS0_USBDEV_CWA16
Address = 0x403F12B0 Common Area Write Address Address: 0x403F12B0 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
CWA16 [7:0]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:9]
9
8
RW
RW
CWA16
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 8 : 0
Name CWA16
Description
Write Address for Common Area Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1193
0x403F12F0 USBFS0_USBDEV_DMA_THRES16
22.1.46 USBFS0_USBDEV_DMA_THRES16
Address = 0x403F12F0 DMA Burst / Threshold Configuration Address: 0x403F12F0 Retention: Not Retained
Bits
7
6
5
4
3
2
SW Access
RW
HW Access
RW
Name
DMA_THS16 [7:0]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:9]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
Bits 8 : 0
Name DMA_THS16
Description
DMA Threshold count Default Value: 0
1
0
9
8
RW
RW
DMA_THS1 6
17
16
25
24
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1194
0x403F2000 USBFS0_USBLPM_POWER_CTL
22.1.47 USBFS0_USBLPM_POWER_CTL
Address = 0x403F2000 Power Control Register Address: 0x403F2000 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
4
None
None
None [7:3]
3
2
1
0
RW
None
R
None
SUSPEND
None
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits SW Access HW Access
Name
23
22
None
None
None [23:22]
21
RW
R
DM_DOWN _EN
20 RW R
DM_BIG
19
18
RW
RW
R
R
DM_UP_EN
DP_DOWN _EN
17 RW R
DP_BIG
16 RW R
DP_UP_EN
Bits
31
30
29
28
27
26
25
24
SW Access
None
RW
RW
None
HW Access
None
R
R
None
Name
None [31:30]
EN-
EN-
ABLE_DMO ABLE_DPO
None [27:24]
Bits
Name
29
ENABLE_DMO
28
ENABLE_DPO
21
DM_DOWN_EN
20
DM_BIG
19
DM_UP_EN
Description
Enables the signle ended receiver on D-. Default Value: 0
Enables the single ended receiver on D+. Default Value: 0
Enables the ~15k pull down on the DP. Default Value: 0
Select the resister value if POWER_CTL.DM_EN='1'. This bit is valid in GPIO. '0' : The resister value is from 900 to1575Ohmpull up on the DM. '1' : The resister value is from 1425 to 3090Ohmpull up on the DM Default Value: 0
Enables the pull up on the DM. The bit is valid in GPIO. The pull up resistor is disabled in not GPIO. '0' : Disable. '1' : Enable. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1195
0x403F2000 USBFS0_USBLPM_POWER_CTL
18
DP_DOWN_EN
17
DP_BIG
16
DP_UP_EN
2
SUSPEND
Enables the ~15k pull down on the DP. Default Value: 0
Select the resister value if POWER_CTL.DP_EN='1'. This bit is valid in GPIO. '0' : The resister value is from 900 to1575Ohmpull up on the DP. '1' : The resister value is from 1425 to 3090Ohmpull up on the DP Default Value: 0
Enables the pull up on the DP. '0' : Disable. '1' : Enable. Default Value: 0
Put PHY into Suspend mode. If the PHY is enabled, this bit MUST be set before entering a low power mode (DeepSleep). Note: - This bit is invalid if the HOST bit of the Host Control 0 Register (HOST_CTL0) is '1'. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1196
0x403F2008 USBFS0_USBLPM_USBIO_CTL
22.1.48 USBFS0_USBLPM_USBIO_CTL
Address = 0x403F2008 USB IO Control Register Address: 0x403F2008 Retention: Retained
Bits SW Access HW Access
Name
7
6
None
None
None [7:6]
5
4
3
RW
R
DM_M [5:3]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
0
RW
R
DM_P [2:0]
10
9
8
18
17
16
26
25
24
Bits 5 : 3
2 : 0
Name DM_M
DM_P
Description The GPIO Drive Mode for DM IO pad. Default Value: 0 The GPIO Drive Mode for DP IO pad. This field only applies if USBIO_CR1.IOMODE =1. Data comes from the corresponding GPIO.DR register. Default Value: 0 0x0: OFF :
Mode 0: Output buffer off (high Z). Input buffer off.
0x1: INPUT :
Mode 1: Output buffer off (high Z). Input buffer on. Other values, not supported.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1197
0x403F200C USBFS0_USBLPM_FLOW_CTL
22.1.49 USBFS0_USBLPM_FLOW_CTL
Address = 0x403F200C Flow Control Register Address: 0x403F200C Retention: Retained
Bits SW Access HW Access
Name
7
RW
R
EP8_ERR_RESP
6
RW
R
EP7_ERR_RESP
5
RW
R
EP6_ERR_RESP
4
RW
R
EP5_ERR_RESP
3
RW
R
EP4_ERR_RESP
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2 RW R EP3_ERR_RESP 10
18
26
1 RW R EP2_ERR_RESP
9
17
25
0 RW R EP1_ERR_RESP
8
16
24
Bits
Name
7
EP8_ERR_RESP
6
EP7_ERR_RESP
5
EP6_ERR_RESP
4
EP5_ERR_RESP
3
EP4_ERR_RESP
2
EP3_ERR_RESP
1
EP2_ERR_RESP
Description
End Point 8 error response Default Value: 0
End Point 7 error response Default Value: 0
End Point 6 error response Default Value: 0
End Point 5 error response Default Value: 0
End Point 4 error response Default Value: 0
End Point 3 error response Default Value: 0
End Point 2 error response Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1198
0x403F200C USBFS0_USBLPM_FLOW_CTL
22.1.49 USBFS0_USBLPM_FLOW_CTL (continued)
0
EP1_ERR_RESP
End Point 1 error response
0: do nothing (backward compatibility mode)
1: if this is an IN EP and an underflow occurs then cause a CRC error, if this is an OUT EP and
an overflow occurs then send a NAK
Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1199
0x403F2010 USBFS0_USBLPM_LPM_CTL
22.1.50 USBFS0_USBLPM_LPM_CTL (continued)
22.1.50 USBFS0_USBLPM_LPM_CTL
Address = 0x403F2010 LPM Control Register Address: 0x403F2010 Retention: Retained
Bits SW Access HW Access
Name
7
6
5
4
None
RW
None
R
None [7:5]
SUB_RESP
3 None None
None
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2 RW R
NYET_EN
1
RW
R
LPM_ACK_RE
SP
0 RW R
LPM_EN
10
9
8
18
17
16
26
25
24
Bits
Name
4
SUB_RESP
2
NYET_EN
1
LPM_ACK_RESP
Description
Enable a STALL response for all undefined SubPIDs, i.e. other than LPM (0011b). If not enabled then there will be no response (Error) for the undefined SubPIDs. Default Value: 0
Allow firmware to choose which response to use for an LPM token (LPM_EN=1) when the device is NOT ready to go to the requested low power mode (LPM_ACK_RESP=0). 0: a LPM token will get an NAK response (indicating a CRC error), the host is expected to repeat the LPM token. 1: a LPM token will get a NYET response Default Value: 0
LPM ACK response enable (if LPM_EN=1), to allow firmware to refuse a low power request 0: a LPM token will get a NYET or NAK (depending on NYET_EN bit below) response and the device will NOT go to a low power mode 1: a LPM token will get an ACK response and the device will go to the requested low power mode Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1200
0
LPM_EN
0x403F2010 USBFS0_USBLPM_LPM_CTL
LPM enable 0: Disabled, LPM token will not get a response (backward compatibility mode) 1: Enable, LPM token will get a handshake response (ACK, STALL, NYET or NAK) A STALL will be sent if the bLinkState is not 0001b A NYET, NAK or ACK response will be sent depending on the NYET_EN and LPM_ACK_RESP bits below Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1201
0x403F2014 USBFS0_USBLPM_LPM_STAT
22.1.51 USBFS0_USBLPM_LPM_STAT
Address = 0x403F2014 LPM Status register Address: 0x403F2014 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
R
R
HW Access
None
RW
RW
Name
None [7:5]
LPM_REMOTEWAK
E
LPM_BESL [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 4
3 : 0
Name LPM_REMOTEWAKE
LPM_BESL
Description
0: Device is prohibited from initiating a remote wake 1: Device is allow to wake the host Default Value: 0
Best Effort Service Latency This value should match either the Baseline (DeepSleep) or Deep (Hibernate) BESL in the BOS descriptor. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1202
0x403F2020 USBFS0_USBLPM_INTR_SIE
22.1.52 USBFS0_USBLPM_INTR_SIE
Address = 0x403F2020 USB SOF, BUS RESET and EP0 Interrupt Status Address: 0x403F2020 Retention: Not Retained
Bits SW Access HW Access
Name
7
6
5
4
3
2
1
0
None
RW1C
RW1C
RW1C
RW1C
RW1C
None
RW1S
RW1S
RW1S
RW1S
RW1S
None [7:5]
RESUME_IN-
TR
LPM_INTR
EP0_INTR
BUS_RESET_INTR
SOF_INTR
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
Description
4
RESUME_INTR
Interrupt status for Resume Default Value: 0
3
LPM_INTR
Interrupt status for LPM (Link Power Management, L1 entry) Default Value: 0
2
EP0_INTR
Interrupt status for EP0 Default Value: 0
1
BUS_RESET_INTR
Interrupt status for BUS RESET
Default Value: 0
0
SOF_INTR
Interrupt status for USB SOF Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1203
0x403F2024 USBFS0_USBLPM_INTR_SIE_SET
22.1.53 USBFS0_USBLPM_INTR_SIE_SET
Address = 0x403F2024 USB SOF, BUS RESET and EP0 Interrupt Set Address: 0x403F2024 Retention: Not Retained
Bits SW Access HW Access
Name
7
6
5
4
3
None
RW1S
RW1S
None
A
A
None [7:5]
RESUME_INTR_SET
LPM_INTR_SET
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2 RW1S
A EP0_INTR_SET
10
18
26
1 RW1S
A BUS_RESET_INTR_SET
9
0 RW1S
A
SOF_INTR_SET
8
17
16
25
24
Bits
Name
Description
4
RESUME_INTR_SET
Write with '1' to set corresponding bit in interrupt request register.
Default Value: 0
3
LPM_INTR_SET
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
2
EP0_INTR_SET
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
1
BUS_RESET_INTR_SET Write with '1' to set corresponding bit in interrupt request register.
Default Value: 0
0
SOF_INTR_SET
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1204
0x403F2028 USBFS0_USBLPM_INTR_SIE_MASK
22.1.54 USBFS0_USBLPM_INTR_SIE_MASK
Address = 0x403F2028 USB SOF, BUS RESET and EP0 Interrupt Mask Address: 0x403F2028 Retention: Retained
Bits SW Access HW Access
Name
7
6
5
4
3
2
1
0
None
RW
RW
RW
RW
RW
None
R
R
R
R
R
None [7:5]
RESUME_INTR_MASK
LPM_INTR_MASK
EP0_INTR_MASK
BUS_RESET_INTR_MASK
SOF_INTR_MASK
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
Description
4
RESUME_INTR_MASK Set to 1 to enable interrupt corresponding to interrupt request register
Default Value: 0
3
LPM_INTR_MASK
Set to 1 to enable interrupt corresponding to interrupt request register
Default Value: 0
2
EP0_INTR_MASK
Set to 1 to enable interrupt corresponding to interrupt request register
Default Value: 0
1
BUS_RESET_IN-
Set to 1 to enable interrupt corresponding to interrupt request register
TR_MASK
Default Value: 0
0
SOF_INTR_MASK
Set to 1 to enable interrupt corresponding to interrupt request register
Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1205
0x403F202C USBFS0_USBLPM_INTR_SIE_MASKED
22.1.55 USBFS0_USBLPM_INTR_SIE_MASKED
Address = 0x403F202C USB SOF, BUS RESET and EP0 Interrupt Masked Address: 0x403F202C Retention: Retained
Bits SW Access HW Access
Name
7
6
5
4
3
2
1
0
None
R
R
R
R
R
None
W
W
W
W
W
None [7:5]
RESUME_INTR_MASKE
D
LPM_INTR_MASKE
D
EP0_INTR_MASKE
D
BUS_RESET_INTR_MASKE
D
SOF_INTR_MASKE
D
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
Description
4
RESUME_IN-
TR_MASKED
Logical and of corresponding request and mask bits. Default Value: 0
3
LPM_INTR_MASKED
Logical and of corresponding request and mask bits.
Default Value: 0
2
EP0_INTR_MASKED
Logical and of corresponding request and mask bits.
Default Value: 0
1
BUS_RESET_IN-
Logical and of corresponding request and mask bits.
TR_MASKED
Default Value: 0
0
SOF_INTR_MASKED
Logical and of corresponding request and mask bits.
Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1206
0x403F2030 USBFS0_USBLPM_INTR_LVL_SEL
22.1.56 USBFS0_USBLPM_INTR_LVL_SEL
Address = 0x403F2030 Select interrupt level for each interrupt source Address: 0x403F2030 Retention: Retained
Bits SW Access HW Access
Name
7
6
RW
R
LPM_LVL_SEL [7:6]
5
4
RW
R
EP0_LVL_SEL [5:4]
3
2
RW
R
BUS_RESET_LVL_SEL [3:2]
Bits
15
14
13
12
11
10
SW Access
RW
None
HW Access
R
None
Name
ARB_EP_LVL_SEL [15:14]
None [13:10]
Bits SW Access HW Access
Name
23
22
RW
R
EP4_LVL_SEL [23:22]
21
20
RW
R
EP3_LVL_SEL [21:20]
19
18
RW
R
EP2_LVL_SEL [19:18]
Bits SW Access HW Access
Name
31
30
RW
R
EP8_LVL_SEL [31:30]
29
28
RW
R
EP7_LVL_SEL [29:28]
27
26
RW
R
EP6_LVL_SEL [27:26]
1
0
RW
R
SOF_LVL_SEL [1:0]
9
8
RW
R
RESUME_LVL_SEL [9:8]
17
16
RW
R
EP1_LVL_SEL [17:16]
25
24
RW
R
EP5_LVL_SEL [25:24]
Bits 31 : 30 29 : 28 27 : 26 25 : 24 23 : 22 21 : 20 19 : 18
Name EP8_LVL_SEL EP7_LVL_SEL EP6_LVL_SEL EP5_LVL_SEL EP4_LVL_SEL EP3_LVL_SEL EP2_LVL_SEL
Description
EP8 Interrupt level select Default Value: 0
EP7 Interrupt level select Default Value: 0
EP6 Interrupt level select Default Value: 0
EP5 Interrupt level select Default Value: 0
EP4 Interrupt level select Default Value: 0
EP3 Interrupt level select Default Value: 0
EP2 Interrupt level select Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1207
0x403F2030 USBFS0_USBLPM_INTR_LVL_SEL
17 : 16 15 : 14 9 : 8 7 : 6 5 : 4 3 : 2 1 : 0
EP1_LVL_SEL ARB_EP_LVL_SEL RESUME_LVL_SEL LPM_LVL_SEL EP0_LVL_SEL BUS_RESET_LVL_SEL SOF_LVL_SEL
EP1 Interrupt level select Default Value: 0
Arbiter Endpoint Interrupt level select Default Value: 0
Resume Interrupt level select Default Value: 0
LPM Interrupt level select Default Value: 0
EP0 Interrupt level select Default Value: 0
BUS RESET Interrupt level select Default Value: 0
USB SOF Interrupt level select Default Value: 0
0x0: HI :
High priority interrupt
0x1: MED : Medium priority interrupt
0x2: LO : Low priority interrupt
0x3: RESERVED : illegal
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1208
0x403F2034 USBFS0_USBLPM_INTR_CAUSE_HI
22.1.57 USBFS0_USBLPM_INTR_CAUSE_HI
Address = 0x403F2034 High priority interrupt Cause register Address: 0x403F2034 Retention: Not Retained
Bits SW Access HW Access
Name
7 R RW
ARB_EP_INTR
6
5
None
None
None [6:5]
4
R
RW
RESUME_IN-
TR
3 R RW
LPM_INTR
2 R RW
EP0_INTR
1 R RW
BUS_RESET_INTR
0 R RW
SOF_INTR
Bits SW Access HW Access
Name
15 R RW EP8_INTR
14 R RW EP7_INTR
13 R RW EP6_INTR
12 R RW EP5_INTR
11 R RW EP4_INTR
10 R RW EP3_INTR
9 R RW EP2_INTR
8 R RW EP1_INTR
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
15
EP8_INTR
14
EP7_INTR
13
EP6_INTR
12
EP5_INTR
11
EP4_INTR
10
EP3_INTR
9
EP2_INTR
Description
EP8 Interrupt Default Value: 0
EP7 Interrupt Default Value: 0
EP6 Interrupt Default Value: 0
EP5 Interrupt Default Value: 0
EP4 Interrupt Default Value: 0
EP3 Interrupt Default Value: 0
EP2 Interrupt Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1209
0x403F2034 USBFS0_USBLPM_INTR_CAUSE_HI
22.1.57 USBFS0_USBLPM_INTR_CAUSE_HI (continued)
8
EP1_INTR
EP1 Interrupt Default Value: 0
7
ARB_EP_INTR
Arbiter Endpoint Interrupt Default Value: 0
4
RESUME_INTR
Resume Interrupt Default Value: 0
3
LPM_INTR
LPM Interrupt Default Value: 0
2
EP0_INTR
EP0 Interrupt Default Value: 0
1
BUS_RESET_INTR
BUS RESET Interrupt
Default Value: 0
0
SOF_INTR
USB SOF Interrupt Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1210
0x403F2038 USBFS0_USBLPM_INTR_CAUSE_MED
22.1.58 USBFS0_USBLPM_INTR_CAUSE_MED
Address = 0x403F2038 Medium priority interrupt Cause register Address: 0x403F2038 Retention: Not Retained
Bits SW Access HW Access
Name
7 R RW
ARB_EP_INTR
6
5
None
None
None [6:5]
4
R
RW
RESUME_IN-
TR
3 R RW
LPM_INTR
2 R RW
EP0_INTR
1 R RW
BUS_RESET_INTR
0 R RW
SOF_INTR
Bits SW Access HW Access
Name
15 R RW EP8_INTR
14 R RW EP7_INTR
13 R RW EP6_INTR
12 R RW EP5_INTR
11 R RW EP4_INTR
10 R RW EP3_INTR
9 R RW EP2_INTR
8 R RW EP1_INTR
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
15
EP8_INTR
14
EP7_INTR
13
EP6_INTR
12
EP5_INTR
11
EP4_INTR
10
EP3_INTR
9
EP2_INTR
Description
EP8 Interrupt Default Value: 0
EP7 Interrupt Default Value: 0
EP6 Interrupt Default Value: 0
EP5 Interrupt Default Value: 0
EP4 Interrupt Default Value: 0
EP3 Interrupt Default Value: 0
EP2 Interrupt Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1211
0x403F2038 USBFS0_USBLPM_INTR_CAUSE_MED
22.1.58 USBFS0_USBLPM_INTR_CAUSE_MED (continued)
8
EP1_INTR
EP1 Interrupt Default Value: 0
7
ARB_EP_INTR
Arbiter Endpoint Interrupt Default Value: 0
4
RESUME_INTR
Resume Interrupt Default Value: 0
3
LPM_INTR
LPM Interrupt Default Value: 0
2
EP0_INTR
EP0 Interrupt Default Value: 0
1
BUS_RESET_INTR
BUS RESET Interrupt
Default Value: 0
0
SOF_INTR
USB SOF Interrupt Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1212
0x403F203C USBFS0_USBLPM_INTR_CAUSE_LO
22.1.59 USBFS0_USBLPM_INTR_CAUSE_LO
Address = 0x403F203C Low priority interrupt Cause register Address: 0x403F203C Retention: Not Retained
Bits SW Access HW Access
Name
7 R RW
ARB_EP_INTR
6
5
None
None
None [6:5]
4
R
RW
RESUME_IN-
TR
3 R RW
LPM_INTR
2 R RW
EP0_INTR
1 R RW
BUS_RESET_INTR
0 R RW
SOF_INTR
Bits SW Access HW Access
Name
15 R RW EP8_INTR
14 R RW EP7_INTR
13 R RW EP6_INTR
12 R RW EP5_INTR
11 R RW EP4_INTR
10 R RW EP3_INTR
9 R RW EP2_INTR
8 R RW EP1_INTR
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
15
EP8_INTR
14
EP7_INTR
13
EP6_INTR
12
EP5_INTR
11
EP4_INTR
10
EP3_INTR
9
EP2_INTR
Description
EP8 Interrupt Default Value: 0
EP7 Interrupt Default Value: 0
EP6 Interrupt Default Value: 0
EP5 Interrupt Default Value: 0
EP4 Interrupt Default Value: 0
EP3 Interrupt Default Value: 0
EP2 Interrupt Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1213
0x403F203C USBFS0_USBLPM_INTR_CAUSE_LO
22.1.59 USBFS0_USBLPM_INTR_CAUSE_LO (continued)
8
EP1_INTR
EP1 Interrupt Default Value: 0
7
ARB_EP_INTR
Arbiter Endpoint Interrupt Default Value: 0
4
RESUME_INTR
Resume Interrupt Default Value: 0
3
LPM_INTR
LPM Interrupt Default Value: 0
2
EP0_INTR
EP0 Interrupt Default Value: 0
1
BUS_RESET_INTR
BUS RESET Interrupt
Default Value: 0
0
SOF_INTR
USB SOF Interrupt Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1214
0x403F2070 USBFS0_USBLPM_DFT_CTL
22.1.60 USBFS0_USBLPM_DFT_CTL
Address = 0x403F2070 DFT control Address: 0x403F2070 Retention: Retained
Bits SW Access HW Access
Name
7
6
5
None
None
None [7:5]
4
3
RW
R
DDFT_IN_SEL [4:3]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
Bits 4 : 3
Name DDFT_IN_SEL
2 : 0
DDFT_OUT_SEL
Description DDFT input select signal Default Value: 0 0x0: OFF : Nothing connected, output 0
0x1: GPIO_DP_IN : GPIO input of DP
0x2: GPIO_DM_IN : GPIO input of DM
DDFT output select signal Default Value: 0
2
1
0
RW
R
DDFT_OUT_SEL [2:0]
10
9
8
18
17
16
26
25
24
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1215
22.1.60
USBFS0_USBLPM_DFT_CTL (continued)
0x0: OFF : Nothing connected, output 0 0x1: DP_SE : Single Ended output of DP 0x2: DM_SE : Single Ended output of DM 0x3: TXOE : Output Enable 0x4: RCV_DF : Differential Receiver output 0x5: GPIO_DP_OUT : GPIO output of DP 0x6: GPIO_DM_OUT : GPIO output of DM
0x403F2070 USBFS0_USBLPM_DFT_CTL
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1216
0x403F4000 USBFS0_USBHOST_HOST_CTL0
22.1.61 USBFS0_USBHOST_HOST_CTL0
Address = 0x403F4000 Host Control 0 Register. Address: 0x403F4000 Retention: Retained
Bits
7
6
5
4
3
2
SW Access
None
HW Access
None
Name
None [7:1]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
SW Access
RW
None
HW Access
R
None
Name
ENABLE
None [30:24]
1
0
RW
RW
HOST
9
8
17
16
25
24
Bits
Name
31
ENABLE
0
HOST
Description
This bit enables the operation of this IP. '0' : Disable USB Host '1' : Enable USB Host Note: - This bit doesn't affect the USB Device. Default Value: 0
This bit selects an operating mode of this IP. '0' : USB Device '1' : USB Host Notes: - The mode of operation mode does not transition immediately after setting this bit. Read this bit to confirm that the operation mode has changed. - This bit is reset to '0' if the ENABLE bit in this register changes from '1' to '0'. - Before changing from the USB Host to the USB Device, check that the following conditions are satisfied and also set the RST bit of the Host Control 1 Register (HOST_CTL1). to '1'. * The SOFBUSY bit of the Host Status Register (HOST_STATUS) is set to '0'. * The TKNEN bits of the Host Token Endpoint Register (HOST_TOKEN) is set to '000'. * The SUSP bit of the Host Status Register (HOST_STATUS) is set to '0'. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1217
0x403F4010 USBFS0_USBHOST_HOST_CTL1
22.1.62 USBFS0_USBHOST_HOST_CTL1
Address = 0x403F4010 Host Control 1 Register. Address: 0x403F4010 Retention: Retained
Bits
7
6
SW Access
RW
HW Access
R
Name
RST
5
4
3
None
None
None [6:2]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
0
RW
RW
R
R
USTP
CLKSEL
10
9
8
18
17
16
26
25
24
Bits
Name
7
RST
1
USTP
Description
This bit resets the USB Host. '0' : Normal operating mode. '1' : USB Host is reset. Notes: - This bit is to it's default value '1' if the ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from '1' to '0'. - If this bit is set to '1', both the BFINI bits of the Host Endpoint 1 Control Register (HOST_EP1_CTL) and Host Endpoint 2 Control Register (HOST_EP2_CTL) are set to '1'. Default Value: 1
This bit stops the clock for the USB Host operating unit. When this bit is '1', power consumption can be reduced by configuring this bit. '0' : Normal operating mode. '1' : Stops the clock for the USB Host operating unit. Notes: - If this bit is set to '1', the function of USB Host can't be used because internal clock is stopped. - This bit is initialized if ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from '1' to '0'. Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1218
0x403F4010 USBFS0_USBHOST_HOST_CTL1
22.1.62 USBFS0_USBHOST_HOST_CTL1 (continued)
0
CLKSEL
This bit selects the operating clock of USB Host. '0' : Low-speed clock '1' : Full-speed clock Notes: - This bit is set to it's default vaulue '1' if the ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from '1' to '0'. - This bit must always be set to '1' in the USB Device mode. Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1219
0x403F4100 USBFS0_USBHOST_HOST_CTL2
22.1.63 USBFS0_USBHOST_HOST_CTL2
Address = 0x403F4100 Host Control 2 Register. Address: 0x403F4100 Retention: Retained
Bits SW Access HW Access
Name
7
6
RW
R
TTEST [7:6]
5
RW
R
RESERVED_5
4
RW
R
RESERVED_4
3 RW R
ALIVE
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2 RW R
SOFSTEP
1 RW R
CANCEL
10
9
18
17
26
25
0 RW R RETRY
8
16
24
Bits 7 : 6 5 4 3
Name TTEST RESERVED_5 RESERVED_4 ALIVE
Description
Reserved. Keep this bitfield at the default value. Default Value: 0
Reserved. Keep this bitfield at the default value. Default Value: 0
Reserved. Keep this bitfield at the default value. Default Value: 0
This bit is used to specify the keep-alive function in the low-speed mode. If this bit it set to '1' while the CLKSEL bit of the Host Control 1 Register (HOST_CTL1) is '0', SE0 is output instead of SOF. This bit is only effective when the CLKSEL bit is '0'. If the CLKSEL bit is '1' (Full-Speed mode), SOF is output regardless of the setting of the ALIVE bit. '0' : SOF output. '1' : SE0 output (Keep alive) Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1220
0x403F4100 USBFS0_USBHOST_HOST_CTL2
22.1.63 USBFS0_USBHOST_HOST_CTL2 (continued)
2
SOFSTEP
1
CANCEL
0
RETRY
If this bit is set to '1', the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is set to '1' each time SOF is sent. If this bit is set to '0', the set value of the Host SOF Interrupt Frame Compare Register (HOST_FCOMP) is compared with the low-order eight bits of the SOF frame number. If they match, the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is set to '1'. '0' : An interrupt occurred due to the HOST_HFCOMP setting. '1' : An interrupt occurred. Notes: - If a SOF token (TKNEN='001') is sent by the setting of the Host Token Endpoint Register (HOST_TOKEN), the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is not set to '1' regardless of the setting of this bit. Default Value: 0
When this bit is set to '1', if the target token is written to the Host Token Endpoint Register (HOST_TOKEN) in the EOF area (specified in the Host EOF Setup Register), its sending is canceled. When this bit is set to '0', token sending is not canceled even if the target token is written to the register. The cancellation of token sending is detected by reading the TCAN bit of the Interrupt USB Host Register (INTR_USBHOST). '0' : Continues a token. '1' : Cancels a token. Default Value: 0
If this bit is set to '1', the target token is retried if a NAK or error* occurs. Retry processing is performed after the time that is specified in the Host Retry Timer Setup Register (HOST_RTIMER). * : HOST_ERR.RERR='1', HOST_ERR.TOUT='1', HOST_ERR.CRC='1', HOST_ERR.TGERR='1', HOST_ERR.STUFF='1' '0' : Doesn't retry token sending. '1' : Retries token sending Note: - This bit isn't initialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1221
0x403F4104 USBFS0_USBHOST_HOST_ERR
22.1.64 USBFS0_USBHOST_HOST_ERR
Address = 0x403F4104 Host Error Status Register. Address: 0x403F4104 Retention: Not Retained
Bits SW Access HW Access
Name
7 RW1C W1S LSTSOF
6 RW1C W1S RERR
5 RW1C W1S TOUT
4 RW1C W1S CRC
3 RW1C W1S TGERR
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2 RW1C W1S STUFF
10
18
26
1
0
RW1S
W
HS [1:0]
9
8
17
16
25
24
Bits
Name
7
LSTSOF
6
RERR
Description
If this bit is set to '1', it means that the SOF token can't be sent in the USB Host because other token is in process. When this bit is '0', it means that SOF token was sent with no error. Write '1' to clear, a write of '0' is ignored. '0' : SOF sent without error. '1' : SOF error detected. Note: - This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. Default Value: 0
When this bit is set to '1', it means that the received data exceeds the specified maximum number of packets in the USB Host. If a receive error is detected, bit5 (TOUT) of this register is also set to '1'. When this bit is '0', it means that no error is detected. Write '1' to clear, a write of '0' is ignored. '0' : No receive error. '1' : Maximum packet receive error detected. - This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1222
0x403F4104 USBFS0_USBHOST_HOST_ERR
22.1.64 USBFS0_USBHOST_HOST_ERR (continued)
5
TOUT
4
CRC
3
TGERR
2
STUFF
1 : 0
HS
If this bit is set to '1', it means that no response is returned from the device within the specified time after a token has been sent in the USB Host. When this bit is '0', it means that no timeout is detected. Write '1' to clear, a write of '0' is ignored. '0' : No timeout. '1' : Timeout has detected. Note: - This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. Default Value: 0
If this bit is set to '1', it means that a CRC error is detected in the USB Host. When this bit is '0', it means that no error is detected. If a CRC error is detected, bit5 (TOUT) of this register is also set to '1'. Write '1' to clear, a write of '0' is ignored. '0' : No CRC error. '1' : CRC error detected. Note: - This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. Default Value: 0
If this bit is set to '1', it means that the data does not match the TGGL data. When this bit is '0', it means that no error is detected. Write '1' to clear, a write of '0' is ignored. '0' : No toggle error. '1' : Toggle error detected. Note: - This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. Default Value: 0
If this bit is set to '1', it means that a bit stuffing error has been detected. When this bit is '0', it means that no error is detected. If a stuffing error is detected, bit5 (TOUT) of this register is also set to '1'. Write '1' to clear, a write of '0' is ignored. '0' : No stuffing error. '1' : Stuffing error detected. Note: - This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. Default Value: 0
These flags indicate the status of a handshake packet to be sent or received. These flags are set to 'NULL' when no handshake occurs due to an error or when a SOF token has been ended with the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN). These bits are updated when sending or receiving has been ended. Write '11' to set the status back to 'NULL", all other write values are ignored. Note: This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. Default Value: 3
0x0: ACK :
Acknowledge Packet
0x1: NAK : Non-Acknowledge Packet
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1223
0x403F4104 USBFS0_USBHOST_HOST_ERR
22.1.64
USBFS0_USBHOST_HOST_ERR (continued)
0x2: STALL : Stall Packet
0x3: NULL : Null Packet
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1224
0x403F4108 USBFS0_USBHOST_HOST_STATUS
22.1.65 USBFS0_USBHOST_HOST_STATUS
Address = 0x403F4108 Host Status Register. Address: 0x403F4108 Retention: Not Retained
Bits SW Access HW Access
Name
7
R
RW
CLKSEL_ST
6 R RW
RSTBUSY
5
R
RW
RESERVED_5
4 RW1S RW0C
URST
3 RW0C
RW
SOFBUSY
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:9]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2 RW RW SUSP 10
18
26
1 R RW
TMODE
0 R RW
CSTAT
9
8
R
RW
HOST_ST
17
16
25
24
Bits
Name
8
HOST_ST
7
CLKSEL_ST
Description
This bit shows whether the device is in USB Host mode. If the HOST bit of the Host Control Register (HOST_CTL0) is set to '1', this bit is set to '1'. '0' : USB Device '1' : USB Host Notes: - If this bit is different from the HOST bit, The execution of a token must wait these bits match. - This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1). Read this bit to confirm the operation is complete. Default Value: 0
This bit shows whether it is full-speed or not. If the CLKSEL bit of the Host Control 1 Register (HOST_CTL1) is set to '1', this bit is set to '1'. '0' : Low speed '1' : Full speed Note: - If this bit is different from the CLKSEL bit, The execution of the token and bus reset must wait these bits match. - This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1). Read this bit to confirm the operation is complete. Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1225
0x403F4108 USBFS0_USBHOST_HOST_STATUS
22.1.65 USBFS0_USBHOST_HOST_STATUS (continued)
6
RSTBUSY
5
RESERVED_5
4
URST
3
SOFBUSY
2
SUSP
This bit shows that USB Host is being reset internally. If the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1', this bit is set to '1'. If the RST bit of Host Control 1 Register (HOST_CTL1) is set to '0', this bit is set to '0'. '0' : USB Host isn't being reset. '1' : USB Host is being reset. Notes: - If this bit is '1', the a token must not be executed. - This bit isn't set to '0' or '1' immediately even if the RST bit of Host Control 1 Register (HOST_CTL1) is set to '0' or '1'. Read this bit to confirm the operation is complete. Default Value: 1
Reserved. Keep this bitfield at the default value. Default Value: 0
When this bit is set to '1', the USB bus is reset. This bit remains a '1' during USB bus resetting, and changes to '0' when USB bus resetting is ended. If this bit is set to '0', the USB bus reset is complete Default Value: 0
When a SOF token is sent using the Host Token Endpoint Register (HOST_TOKEN), this bit is set to '1', which means that the SOF timer is active. When this bit is '0', it means that the SOF timer is under suspension. To stop the active SOF timer, write '0' to this bit. However, if this bit is written with '1', its value is ignored. '0' : The SOF timer is stopped. '1' : The SOF timer is active. Notes: - This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. - This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1). - The SOF timer does not stop immediately after this bit has been set to '0' to stop the SOF timer. To check whether or not the SOF timer is stopped, read this bit. Default Value: 0
If this bit is set to '1', the USB Host is placed into the suspend state. If this bit is set to '0' while it is '1' or the USB bus is placed into the k-state mode, then suspend state is released, and the RWIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'. Set to '1' : Suspend. Set '0' when this bit is '1' : Resume. Other conditions : Holds the status. Notes: - This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. - The transition to disconnected on RST isn't immediate. Read this bit to confirm the transition is complete. - If this bit is set to '1', this bit must not be set to '1' until the RWIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'. - Do not set this bit to '1' while the USB is active (during USB bus resetting, data transfer, or SOF timer running). - If the value of this bit is changed, it is not immediately reflected on the state of the USB bus. To check whether or not the state is updated, read this bit. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1226
0x403F4108 USBFS0_USBHOST_HOST_STATUS
22.1.65 USBFS0_USBHOST_HOST_STATUS (continued)
1
TMODE
0
CSTAT
If this bit is '1', it means that the device is connected in the full-speed mode. When this bit is '0', it means that the device is connected in the low-speed mode. This bit is valid when the CSTAT bit of the Host Status Register (HOST_STATUS) is '1'. '0' : Low-speed. '1' : Full-speed. Notes: - This bit is set to the default value if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. - The transition to disconnected on RST isn't immediate. Read this bit to confirm the transition is complete. Default Value: 1
When this bit is '1', it means that the device is connected. When this bit is '0', it means that the device is disconnected. '0' : Device is disconnected. '1' : Device is connected. Notes: - This bit is set to the default value if the RST bit of the Host Control 1 Register (Host_CTL1) is set to '1'. - The transition to disconnected on RST isn't immediate. Read this bit to confirm the transition is complete. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1227
0x403F410C USBFS0_USBHOST_HOST_FCOMP
22.1.66 USBFS0_USBHOST_HOST_FCOMP
Address = 0x403F410C Host SOF Interrupt Frame Compare Register Address: 0x403F410C Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
FRAMECOMP [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 0
Name FRAMECOMP
Description
These bits are used to specify the data to be compared with the low-order eight bits of a frame number when sending a SOF token. If the SOFSTEP bit of Host Control 2 Register (HOST_CTL2) is '0', the frame number of SOF is compared with the value of this register when sending a SOF token. If they match, the SOFIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'. The setting of this register is invalid when the SOFSTEP bit of Host Control 2 Register (HOST_CTL2) is '1'. Note: - This bit is not reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1228
0x403F4110 USBFS0_USBHOST_HOST_RTIMER
22.1.67 USBFS0_USBHOST_HOST_RTIMER
Address = 0x403F4110 Host Retry Timer Setup Register Address: 0x403F4110 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
RTIMER [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
RTIMER [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
HW Access
None
R
Name
None [23:18]
RTIMER [17:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 17 : 0
Name RTIMER
Description
These bits are used to specify the retry time in this register. The retry timer is activated when token sending starts while the RETRY bit of Host Control 2 Register (HOST_CTL2) is '1'. The retry time is then decremented by one when a 1-bit transfer clock (12 MHz in the full-speed mode) is output. When the retry timer reaches 0, the target token is sent, and processing ends. If a token retry occurs in the EOF area, the retry timer is stopped until SOF sending is ended. After SOF sending has been completed, the retry timer restarts with the value that is set when the timer stopped. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1229
0x403F4114 USBFS0_USBHOST_HOST_ADDR
22.1.68 USBFS0_USBHOST_HOST_ADDR
Address = 0x403F4114 Host Address Register Address: 0x403F4114 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None
ADDRESS [6:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 6 : 0
Name ADDRESS
Description
These bits are used to specify a token address. Note: - This bit is reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1230
0x403F4118 USBFS0_USBHOST_HOST_EOF
22.1.69 USBFS0_USBHOST_HOST_EOF
Address = 0x403F4118 Host EOF Setup Register Address: 0x403F4118 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
EOF [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
RW
HW Access
None
R
Name
None [15:14]
EOF [13:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 13 : 0
Name EOF
Description
These bits are used to specify the time to disable token sending before transferring SOF. Specify the time with a margin, which is longer than the one-packet length. The time unit is the 1-bit transfer time. Setting example: MAXPKT = 64 bytes, full-speed mode (Token_length + packet_length + header + CRC)*7/6 + Turn_around_time =(34 bit + 546 bit)*7/6 + 36 bit = 712.7 bit Therefore, set 0x2C9. Note: - This bit is not reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1231
0x403F411C USBFS0_USBHOST_HOST_FRAME
22.1.70 USBFS0_USBHOST_HOST_FRAME
Address = 0x403F411C Host Frame Setup Register Address: 0x403F411C Retention: Retained
Bits
7
6
5
4
3
SW Access
RW
HW Access
RW
Name
FRAME [7:0]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:11]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
0
10
9
8
RW
RW
FRAME [10:8]
18
17
16
26
25
24
Bits 10 : 0
Name FRAME
Description
These bits are used to specify a frame number of SOF. Notes: - This bit isn't reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. - Specify a frame number in this register before setting SOF in the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN). - This register cannot be written while the SOFBUSY bit of the Host Status Register (HOST_STATUS) is '1' and a SOF token is in process. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1232
0x403F4120 USBFS0_USBHOST_HOST_TOKEN
22.1.71 USBFS0_USBHOST_HOST_TOKEN
Address = 0x403F4120 Host Token Endpoint Register Address: 0x403F4120 Retention: Not Retained
Bits
7
6
5
4
3
SW Access
None
RW
HW Access
None
RW0C
Name
None
TKNEN [6:4]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:9]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
RW
R
ENDPT [3:0]
10
9
18
17
0
8 RW R TGGL 16
26
25
24
Bits
Name
8
TGGL
Description
This bit is used to set toggle data. Toggle data is sent depending on the setting of this bit. When receiving toggle data, received toggle data is compared with the toggle data of this bit to verify whether or not an error occurs. '0' : DATA0 '1' : DATA1 Notes: - This bit isn't reset to the default value even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. - Set this bit when the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN) is '000'. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1233
0x403F4120 USBFS0_USBHOST_HOST_TOKEN
22.1.71 USBFS0_USBHOST_HOST_TOKEN (continued)
6 : 4
TKNEN
These bits send a token according to the current settings. After operation is complete, the TKNEN bit is set to '000', and the CMPIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'. The settings of the TGGL and ENDPT bits are ignored when sending a SOF token. Notes: - This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. - The PRE packet isn't supported. - Do not set '100' to the TKNEN bit when the SOFBUSY bit of the Host Status Register (HOST_STATUS) is '1' - Mode should be USB Host before writing data to this bit. - When issuing a token again after the token interrupt flag (CMPIRQ) has been set to '1', wait for 3 cycles or more after a USB transfer clock (12 MHz in the full-speed mode, 1.5 MHz in the lowspeed mode) was output, then write data to this bit. - Read the value of TKNEN bit if a new value is written in it .Continue writing in this bit until a retrieved value equals a new value written in. During this checking process, it is needed to prevent any interrupt. - Take the following steps when CMPIRQ bit of Interrupt USB Host Register (INTR_USBHOST) is set to '1' by finishing IN token or Isochronous IN token. 1. Read HS bit of Host Error Status Register (HOST_ERR), then set CMPIRQ bit to '0'. 2. Set EPn bit of Host DMA Enable Register (HOST_DMA_ENBL) (n=1 or 2) to '1' if HS bit of Host Error Status Register (HOST_ERR) is equal to '00' and wait until EPn bit of Host DMA Data Request Register (HOST_DMA_DREQ) changes to '1'. Finish the IN token processing if HS bit is not equal to '00'. 3. Read the received data if EPn bit of Host DMA Data Requet (HOST_DMA_DREQ) (n=1 or 2) changes to '1'. Default Value: 0
0x0: NONE :
Sends no data.
0x1: SETUP : Sends SETUP token.
0x2: IN : Sends IN token.
0x3: OUT : Sends OUT token.
0x4: SOF : Sends SOF token.
0x5: ISO_IN : Sends Isochronous IN.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1234
0x403F4120 USBFS0_USBHOST_HOST_TOKEN
22.1.71
USBFS0_USBHOST_HOST_TOKEN (continued)
0x6: ISO_OUT : Sends Isochronous OUT.
0x7: RSV : Reserved.
3 : 0
ENDPT
These bits are used to specify an endpoint to send or receive data to or from the device. Note: - This bit isn't reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1235
0x403F4400 USBFS0_USBHOST_HOST_EP1_CTL
22.1.72 USBFS0_USBHOST_HOST_EP1_CTL
Address = 0x403F4400 Host Endpoint 1 Control Register Address: 0x403F4400 Retention: Retained
Bits
7
6
5
4
3
SW Access
RW
HW Access
R
Name
PKS1 [7:0]
Bits SW Access HW Access
Name
15 RW RW1S BFINI
14
13
None
None
None [14:13]
12
11
RW
RW
R
R
DIR
DMAE
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
10 RW R NULLE 18
26
1
9 None None None
17
25
0
8 RW R PKS1 16
24
Bits
Name
15
BFINI
12
DIR
Description
This bit initializes the send/receive buffer of transfer data. The BFINI bit is also automatically set by setting the RST bit of the HOST Control 1 Register (HOST_CTL1). If the RST bit was used for resetting, therefore, set the RST bit to "0" before clearing the BFINI bit. '0' : Clears the initialization. '1' : Initializes the send/receive buffer Note : - The EP1 buffer has a double-buffer configuration. The BFINI bit initialization initializes the double buffers concurrently and also initializes the EP1DRQ and EP1SPK bits. Default Value: 1
This bit specifies the transfer direction the Endpoint support. '0' : IN Endpoint. '1' : OUT Endpoint Note: - This bit must be changed when INI_ST bit of the Host Endpoint 1 Status Register (HOST_EP1_STATUS) is '1'. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1236
0x403F4400 USBFS0_USBHOST_HOST_EP1_CTL
22.1.72 USBFS0_USBHOST_HOST_EP1_CTL (continued)
11
DMAE
10
NULLE
8 : 0
PKS1
This bit sets a mode that uses DMA for writing or reading transfer data to/from send/receive buffer, and automatically transfers the send/receive data synchronized with an data request in the IN or OUT direction. Until the data size set in the DMA is reached, the data is transferred. '0' : Releases the packet transfer mode. '1' : Sets the packet transfer mode. Note : - The CPU must not access the send/receive buffer while the DMAE bit is set to '1'. For data transfer in the IN direction, set the DMA transfer size to the multiples of that set in PKS1 bits of the Host EP1 Control Register (HOST_EP1_CTL) and Host EP2 Control Register (HOST_EP2_CTR). Default Value: 0
When a data transfer request in OUT the direction is transmitted while automatic buffer transfer mode is set (DMAE = 1), this bit sets a mode that transfers 0-byte data automatically upon the detection of the last packet transfer. '0' : Releases the NULL automatic transfer mode. '1' : Sets the NULL automatic transfer mode. Note : - For data transfer in the IN direction or when automatic buffer transfer mode is not set, the NULL bit configuration does not affect communication. Default Value: 0
This bit specifies the maximum size transferred by one packet. The configurable range is from 0x001 to 0x100. - If automatic buffer transfer mode (DMAE='1') is used, Endpoint 0,1, or 2 cannot be used, Default Value: 256
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1237
0x403F4404 USBFS0_USBHOST_HOST_EP1_STATUS
22.1.73 USBFS0_USBHOST_HOST_EP1_STATUS
Address = 0x403F4404 Host Endpoint 1 Status Register Address: 0x403F4404 Retention: Not Retained
Bits
7
6
5
4
3
2
SW Access
R
HW Access
RW
Name
SIZE1 [7:0]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:9]
Bits
23
SW Access
HW Access
Name
22
21
20
None
None
None [23:19]
19
18
R
RW
RESERVED_1
8
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
1
9
17 R RW INI_ST 25
0
8 R RW SIZE1 16 R RW VAL_DATA
24
Bits
Name
18
RESERVED_18
17
INI_ST
16
VAL_DATA
Description
Reserved. Keep this bitfield at the default value. Default Value: 1
This bit shows that EP1 is initialized. If the init bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is set to '1' and EP1 is initialized, this bit is to '1'. '0' : Not initiatialized '1' : Initialized Note: - This bit isn't set to '0' or '1' immediately even if BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is set to '0' or '1'. Read this bit to confirm the transition. Default Value: 1
This bit shows that there is valid data in the EP1 buffer. '0' : Invalid data in the buffer '1' : Valid data in the buffer Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1238
0x403F4404 USBFS0_USBHOST_HOST_EP1_STATUS
22.1.73 USBFS0_USBHOST_HOST_EP1_STATUS (continued)
8 : 0
SIZE1
These bits indicate the number of data bytes written to the receive buffer when IN packet transfer of EP1 has finished. The indication range is from 0x000 to 0x100. Note : - These bits are set to the data size transferred in the IN direction and written to the buffer. Therefore, a value read during transfer in the OUT direction has no effect. Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1239
0x403F4408 USBFS0_USBHOST_HOST_EP1_RW1_DR
22.1.74 USBFS0_USBHOST_HOST_EP1_RW1_DR
Address = 0x403F4408 Host Endpoint 1 Data 1-Byte Register Address: 0x403F4408 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
BFDT8 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 0
Name BFDT8
Description
Data Register for EP1 for 1-byte data Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1240
0x403F440C USBFS0_USBHOST_HOST_EP1_RW2_DR
22.1.75 USBFS0_USBHOST_HOST_EP1_RW2_DR
Address = 0x403F440C Host Endpoint 1 Data 2-Byte Register Address: 0x403F440C Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
BFDT16 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
RW
Name
BFDT16 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 0
Name BFDT16
Description
Data Register for EP1 for 2-byte data Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1241
0x403F4500 USBFS0_USBHOST_HOST_EP2_CTL
22.1.76 USBFS0_USBHOST_HOST_EP2_CTL
Address = 0x403F4500 Host Endpoint 2 Control Register Address: 0x403F4500 Retention: Retained
Bits
7
6
5
4
3
SW Access
None
RW
HW Access
None
R
Name
None
PKS2 [6:0]
Bits SW Access HW Access
Name
15 RW RW1S BFINI
14
13
None
None
None [14:13]
12
11
RW
RW
R
R
DIR
DMAE
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
10 RW R NULLE 18
26
1
0
9
8
None
None
None [9:8]
17
16
25
24
Bits
Name
15
BFINI
12
DIR
Description
This bit initializes the send/receive buffer of transfer data. The BFINI bit is also automatically set by setting the RST bit of the HOST Control 1 Register (HOST_CTL1). If the RST bit was used for resetting, therefore, set the RST bit to '0' before clearing the BFINI bit. '0' : Clears the initialization. '1' : Initializes the send/receive buffer Note : - The EP2 buffer has a double-buffer configuration. The BFINI bit initialization initializes the double buffers concurrently and also initializes the EP2DRQ and EP2SPK bits. Default Value: 1
This bit specifies the transfer direction the Endpoint support. '0' : IN Endpoint. '1' : OUT Endpoint Note: - This bit must be changed when INI_ST bit of the Host Endpoint 2 Status Register (HOST_EP2_STATUS) is '1'. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1242
0x403F4500 USBFS0_USBHOST_HOST_EP2_CTL
22.1.76 USBFS0_USBHOST_HOST_EP2_CTL (continued)
11
DMAE
10
NULLE
6 : 0
PKS2
This bit sets a mode that uses DMA for writing or reading transfer data to/from send/receive buffer, and automatically transfers the send/receive data synchronized with an data request in the IN or OUT direction. Until the data size set in the DMA is reached, the data is transferred. '0' : Releases the automatic buffer transfer mode. '1' : Sets the automatic buffer transfer mode. Note : - The CPU must not access the send/receive buffer while the DMAE bit is set to '1'. For data transfer in the IN direction, set the DMA transfer size to the multiples of that set in PKS bits of the Host EP1 Control Register (HOST_EP1_CTL) and Host EP2 Control Register (HOST_EP2_CTR). Default Value: 0
When a data transfer request in the OUT direction transmitted while packet transfer mode is set (DMAE = 1), this bit sets a mode that transfers 0-byte data automatically upon the detection of the last packet transfer. '0' : Releases the NULL automatic transfer mode. '1' : Sets the NULL automatic transfer mode. Note : - For data transfer in the IN direction or when automatic buffer transfer mode is not set, the NULL bit configuration does not affect communication. Default Value: 0
This bit specifies the maximum size transferred by one packet. The configurable range is from 0x001 to 0x40. - If automatic buffer transfer mode (DMAE='1') is used, this Endpoint must not set from 0 to 2. Default Value: 64
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1243
0x403F4504 USBFS0_USBHOST_HOST_EP2_STATUS
22.1.77 USBFS0_USBHOST_HOST_EP2_STATUS
Address = 0x403F4504 Host Endpoint 2 Status Register Address: 0x403F4504 Retention: Not Retained
Bits
7
6
5
4
3
2
SW Access
None
R
HW Access
None
RW
Name
None
SIZE2 [6:0]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
SW Access
HW Access
Name
22
21
20
None
None
None [23:19]
19
18
R
RW
RESERVED_1
8
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
1
9
17 R RW INI_ST 25
0
8
16 R RW VAL_DATA 24
Bits
Name
18
RESERVED_18
17
INI_ST
16
VAL_DATA
Description
Reserved. Keep this bitfield at the default value. Default Value: 1
This bit shows that EP2 is initialized. If the BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to '1' and EP2 is initialized, this bit is to '1'. '0' : Not Initialized '1' : Initialized Note: - This bit isn't set to '0' or '1' immediately evne if BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to '0' or '1'. Default Value: 1
This bit shows that there is valid data in the EP2 buffer. '0' : Invalid data in the buffer '1' : Valid data in the buffer Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1244
0x403F4504 USBFS0_USBHOST_HOST_EP2_STATUS
22.1.77 USBFS0_USBHOST_HOST_EP2_STATUS (continued)
6 : 0
SIZE2
These bits indicate the number of data bytes written to the receive buffer when IN packet transfer of EP2 has finished. The indication range is from 0x000 to 0x40. Note : - These bits are set to the data size transferred in the IN direction and written to the buffer. Therefore, a value read during transfer in the OUT direction has no effect. Default Value: X
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1245
0x403F4508 USBFS0_USBHOST_HOST_EP2_RW1_DR
22.1.78 USBFS0_USBHOST_HOST_EP2_RW1_DR
Address = 0x403F4508 Host Endpoint 2 Data 1-Byte Register Address: 0x403F4508 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
BFDT8 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 0
Name BFDT8
Description
Data Register for EP2 for 1-byte data. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1246
0x403F450C USBFS0_USBHOST_HOST_EP2_RW2_DR
22.1.79 USBFS0_USBHOST_HOST_EP2_RW2_DR
Address = 0x403F450C Host Endpoint 2 Data 2-Byte Register Address: 0x403F450C Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
BFDT16 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
RW
Name
BFDT16 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 0
Name BFDT16
Description
Data Register for EP2 for 2 byte data. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1247
0x403F4800 USBFS0_USBHOST_HOST_LVL1_SEL
22.1.80 USBFS0_USBHOST_HOST_LVL1_SEL
Address = 0x403F4800 Host Interrupt Level 1 Selection Register Address: 0x403F4800 Retention: Retained
Bits SW Access HW Access
Name
7
6
RW
R
CMPIRQ_SEL [7:6]
5
4
RW
R
CNNIRQ_SEL [5:4]
3
2
RW
R
DIRQ_SEL [3:2]
Bits SW Access HW Access
Name
15
14
RW
R
TCAN_SEL [15:14]
13
12
RW
R
RESERVED_13_12 [13:12]
11
10
RW
R
RWKIRQ_SEL [11:10]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
1
0
RW
R
SOFIRQ_SEL [1:0]
9
8
RW
R
URIRQ_SEL [9:8]
17
16
25
24
Bits 15 : 14 13 : 12 11 : 10 9 : 8 7 : 6 5 : 4 3 : 2 1 : 0
Name TCAN_SEL RESERVED_13_12 RWKIRQ_SEL URIRQ_SEL CMPIRQ_SEL CNNIRQ_SEL DIRQ_SEL SOFIRQ_SEL
Description
These bits assign TCAN interrupt flag to selected interrupt signals. Default Value: 0
Reserved. Keep this bitfield at the default value. Default Value: 0
These bits assign RWKIRQ interrupt flag to selected interrupt signals. Default Value: 0
These bits assign URIRQ interrupt flag to selected interrupt signals. Default Value: 0
These bits assign URIRQ interrupt flag to selected interrupt signals. Default Value: 0
These bits assign CNNIRQ interrupt flag to selected interrupt signals. Default Value: 0
These bits assign DIRQ interrupt flag to selected interrupt signals. Default Value: 0
These bits assign SOFIRQ interrupt flag to selected interrupt signals. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1248
0x403F4800 USBFS0_USBHOST_HOST_LVL1_SEL
22.1.80
USBFS0_USBHOST_HOST_LVL1_SEL (continued)
0x0: HI : High priority interrupt
0x1: MED : Medium priority interrupt
0x2: LO : Low priority interrupt
0x3: RESERVED : Reserved.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1249
0x403F4804 USBFS0_USBHOST_HOST_LVL2_SEL
22.1.81 USBFS0_USBHOST_HOST_LVL2_SEL
Address = 0x403F4804 Host Interrupt Level 2 Selection Register Address: 0x403F4804 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
RW
None
HW Access
R
R
None
Name
EP1_SPK_SEL [7:6]
EP1_DRQ_SEL [5:4]
None [3:0]
Bits
15
SW Access
HW Access
Name
14
13
None
None
None [15:12]
12
11
10
9
8
RW
RW
R
R
EP2_SPK_SEL [11:10]
EP2_DRQ_SEL [9:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 11 : 10 9 : 8 7 : 6 5 : 4
Name EP2_SPK_SEL EP2_DRQ_SEL EP1_SPK_SEL EP1_DRQ_SEL
Description These bits assign EP2_SPK interrupt flag to selected interrupt signals. Default Value: 0 These bits assign EP2_DRQ interrupt flag to selected interrupt signals. Default Value: 0 These bits assign EP1_SPK interrupt flag to selected interrupt signals. Default Value: 0 These bits assign EP1_DRQ interrupt flag to selected interrupt signals. Default Value: 0 0x0: HI :
High priority interrupt
0x1: MED :
Medium priority interrupt
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1250
0x2: LO : Low priority interrupt
0x3: RESERVED : Reserved.
0x403F4804 USBFS0_USBHOST_HOST_LVL2_SEL
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1251
0x403F4900 USBFS0_USBHOST_INTR_USBHOST_CAUSE_HI
22.1.82 USBFS0_USBHOST_INTR_USBHOST_CAUSE_HI
Address = 0x403F4900 Interrupt USB Host Cause High Register Address: 0x403F4900 Retention: Not Retained
Bits SW Access HW Access
Name
7 R W
TCAN_INT
6
R
W
RESERVED_6
5
R
W
RWKIRQ_I NT
4 R W
URIRQ_INT
3
R
W
CMPIRQ_INT
2
R
W
CNNIRQ_INT
1 R W
DIRQ_INT
0
R
W
SOFIRQ_INT
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
7
TCAN_INT
6
RESERVED_6
5
RWKIRQ_INT
4
URIRQ_INT
3
CMPIRQ_INT
2
CNNIRQ_INT
1
DIRQ_INT
Description
TCAN interrupt Default Value: 0
Reserved. Default Value: 0
RWKIRQ interrupt Default Value: 0
URIRQ interrupt Default Value: 0
CMPIRQ interrupt Default Value: 0
CNNIRQ interrupt Default Value: 0
DIRQ interrupt Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1252
0x403F4900 USBFS0_USBHOST_INTR_USBHOST_CAUSE_HI
22.1.82 USBFS0_USBHOST_INTR_USBHOST_CAUSE_HI (continued)
0
SOFIRQ_INT
SOFIRQ interrupt Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1253
0x403F4904 USBFS0_USBHOST_INTR_USBHOST_CAUSE_MED
22.1.83 USBFS0_USBHOST_INTR_USBHOST_CAUSE_MED
Address = 0x403F4904 Interrupt USB Host Cause Medium Register Address: 0x403F4904 Retention: Not Retained
Bits SW Access HW Access
Name
7 R W
TCAN_INT
6
R
W
RESERVED_6
5
R
W
RWKIRQ_I NT
4 R W
URIRQ_INT
3
R
W
CMPIRQ_INT
2
R
W
CNNIRQ_INT
1 R W
DIRQ_INT
0
R
W
SOFIRQ_INT
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
7
TCAN_INT
6
RESERVED_6
5
RWKIRQ_INT
4
URIRQ_INT
3
CMPIRQ_INT
2
CNNIRQ_INT
1
DIRQ_INT
Description
TCAN interrupt Default Value: 0
Reserved. Default Value: 0
RWKIRQ interrupt Default Value: 0
URIRQ interrupt Default Value: 0
CMPIRQ interrupt Default Value: 0
CNNIRQ interrupt Default Value: 0
DIRQ interrupt Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1254
0x403F4904 USBFS0_USBHOST_INTR_USBHOST_CAUSE_MED
22.1.83 USBFS0_USBHOST_INTR_USBHOST_CAUSE_MED (continued)
0
SOFIRQ_INT
SOFIRQ interrupt Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1255
0x403F4908 USBFS0_USBHOST_INTR_USBHOST_CAUSE_LO
22.1.84 USBFS0_USBHOST_INTR_USBHOST_CAUSE_LO
Address = 0x403F4908 Interrupt USB Host Cause Low Register Address: 0x403F4908 Retention: Not Retained
Bits SW Access HW Access
Name
7 R W
TCAN_INT
6
R
W
RESERVED_6
5
R
W
RWKIRQ_I NT
4 R W
URIRQ_INT
3
R
W
CMPIRQ_INT
2
R
W
CNNIRQ_INT
1 R W
DIRQ_INT
0
R
W
SOFIRQ_INT
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
7
TCAN_INT
6
RESERVED_6
5
RWKIRQ_INT
4
URIRQ_INT
3
CMPIRQ_INT
2
CNNIRQ_INT
1
DIRQ_INT
Description
TCAN interrupt Default Value: 0
Reserved. Default Value: 0
RWKIRQ interrupt Default Value: 0
URIRQ interrupt Default Value: 0
CMPIRQ interrupt Default Value: 0
CNNIRQ interrupt Default Value: 0
DIRQ interrupt Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1256
0x403F4908 USBFS0_USBHOST_INTR_USBHOST_CAUSE_LO
22.1.84 USBFS0_USBHOST_INTR_USBHOST_CAUSE_LO (continued)
0
SOFIRQ_INT
SOFIRQ interrupt Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1257
0x403F4920 USBFS0_USBHOST_INTR_HOST_EP_CAUSE_HI
22.1.85 USBFS0_USBHOST_INTR_HOST_EP_CAUSE_HI
Address = 0x403F4920 Interrupt USB Host Endpoint Cause High Register Address: 0x403F4920 Retention: Not Retained
Bits SW Access HW Access
Name
7
6
None
None
None [7:6]
5
R
W
EP2SPK_INT
4
R
W
EP2DRQ_I NT
3
R
W
EP1SPK_INT
2
R
W
EP1DRQ_I NT
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
1
0
None
None
None
9
8
17
16
25
24
Bits
Name
5
EP2SPK_INT
4
EP2DRQ_INT
3
EP1SPK_INT
2
EP1DRQ_INT
Description
EP2SPK interrupt Default Value: 0
EP2DRQ interrupt Default Value: 0
EP1SPK interrupt Default Value: 0
EP1DRQ interrupt Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1258
0x403F4924 USBFS0_USBHOST_INTR_HOST_EP_CAUSE_MED
22.1.86 USBFS0_USBHOST_INTR_HOST_EP_CAUSE_MED
Address = 0x403F4924 Interrupt USB Host Endpoint Cause Medium Register Address: 0x403F4924 Retention: Not Retained
Bits SW Access HW Access
Name
7
6
None
None
None [7:6]
5
R
W
EP2SPK_INT
4
R
W
EP2DRQ_I NT
3
R
W
EP1SPK_INT
2
R
W
EP1DRQ_I NT
1
0
None
None
None
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
5
EP2SPK_INT
4
EP2DRQ_INT
3
EP1SPK_INT
2
EP1DRQ_INT
Description
EP2SPK interrupt Default Value: 0
EP2DRQ interrupt Default Value: 0
EP1SPK interrupt Default Value: 0
EP1DRQ interrupt Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1259
0x403F4928 USBFS0_USBHOST_INTR_HOST_EP_CAUSE_LO
22.1.87 USBFS0_USBHOST_INTR_HOST_EP_CAUSE_LO
Address = 0x403F4928 Interrupt USB Host Endpoint Cause Low Register Address: 0x403F4928 Retention: Not Retained
Bits SW Access HW Access
Name
7
6
None
None
None [7:6]
5
R
W
EP2SPK_INT
4
R
W
EP2DRQ_I NT
3
R
W
EP1SPK_INT
2
R
W
EP1DRQ_I NT
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
1
0
None
None
None
9
8
17
16
25
24
Bits
Name
5
EP2SPK_INT
4
EP2DRQ_INT
3
EP1SPK_INT
2
EP1DRQ_INT
Description
EP2SPK interrupt Default Value: 0
EP2DRQ interrupt Default Value: 0
EP1SPK interrupt Default Value: 0
EP1DRQ interrupt Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1260
0x403F4940 USBFS0_USBHOST_INTR_USBHOST
22.1.88 USBFS0_USBHOST_INTR_USBHOST
Address = 0x403F4940 Interrupt USB Host Register Address: 0x403F4940 Retention: Not Retained
Bits SW Access HW Access
Name
7 RW1C W1S
TCAN
6
RW1C
W1S
RESERVED_6
5 RW1C W1S
RWKIRQ
4 RW1C W1S
URIRQ
3 RW1C W1S
CMPIRQ
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2 RW1C W1S CNNIRQ
10
18
26
1 RW1C W1S DIRQ
9
17
25
0 RW1C W1S SOFIRQ
8
16
24
Bits
Name
7
TCAN
6
RESERVED_6
Description
If this bit is set to '1', it means that token sending is canceled based on the setting of the CANCEL bit of Host Control 2 Register (HOST_CTL2). When this bit is '0', it means that token sending is not canceled. Write '1' to clear, a write of '0' is ignored. '0' : Does not cancel token sending. '1' : Cancels token sending. Note : - This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. Default Value: 0
Reserved. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1261
0x403F4940 USBFS0_USBHOST_INTR_USBHOST
22.1.88 USBFS0_USBHOST_INTR_USBHOST (continued)
5
RWKIRQ
4
URIRQ
3
CMPIRQ
2
CNNIRQ
1
DIRQ
If this bit is set to '1', it means that remote Wake-up is ended. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored. '0' : Issues no interrupt request by restart. '1' : Issues an interrupt request by restart. Note : - This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. Default Value: 0
If this bit is set to '1', it means that USB bus resetting is ended. When this bit is '0', it has no meaning. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored. '0' : Issues no interrupt request by USB bus resetting. '1' : Issues an interrupt request by USB bus resetting. Note : - This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. Default Value: 0
If this bit is set to '1', it means that a token is completed. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored. '0' : Issues no interrupt request by token completion. '1' : Issues an interrupt request by token completion. Note : - This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. - This bit is not set to '1' even if the TCAN bit of the Interrupt USBHost Register (INTR_USBHOST) changes to '1'. - Take the following steps when this bit is set to '1' by finishing IN token or Isochronous IN token. 1. Read HS bit of Host Error Status Register (HOST_ERR), then set CMPIRQ bit to '0'. 2. Set EPn bit of Host DMA Enable Register (HOST_DMA_ENBL) (n=1 or 2) to '1' if HS bit of Host Error Status Register (HOST_ERR) is equal to '00' and wait until EPn bit of Host DMA Data Request Register (HOST_DMA_DREQ) changes to '1'. Finish the IN token processing if HS bit is not equal to '00'. 3. Read the received data if EPn bit of Host DMA Data Requet (HOST_DMA_DREQ) (n=1 or 2) changes to '1'. Default Value: 0
If this bit is set to '1', it means that a device connection is detected. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored. '0' : Issues no interrupt request by detecting a device connection. '1' : Issues an interrupt request by detecting a device connection. Note : - This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. Default Value: 0
If this bit is set to '1', it means that a device disconnection is detected. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored. '0' : Issues no interrupt request by detecting a device disconnection. '1' : Issues an interrupt request by detecting a device disconnection. Note : - This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1262
0x403F4940 USBFS0_USBHOST_INTR_USBHOST
22.1.88 USBFS0_USBHOST_INTR_USBHOST (continued)
0
SOFIRQ
If this bit is set to '1', it means that SOF token sending is started. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored. '0' : Does not issue an interrupt request by starting a SOF token. '1' : Issues an interrupt request by starting a SOF token. Note : - This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1263
0x403F4944 USBFS0_USBHOST_INTR_USBHOST_SET
22.1.89 USBFS0_USBHOST_INTR_USBHOST_SET
Address = 0x403F4944 Interrupt USB Host Set Register Address: 0x403F4944 Retention: Not Retained
Bits SW Access HW Access
Name
7 RW1S
A
TCANS
6
RW1S
A
RESERVED_6
5 RW1S
A
RWKIRQS
4 RW1S
A
URIRQS
3 RW1S
A
2 RW1S
A
CMPIRQS CNNIRQS
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
1 RW1S
A DIRQS
9
17
25
0 RW1S
A SOFIRQS
8
16
24
Bits
Name
7
TCANS
6
RESERVED_6
5
RWKIRQS
4
URIRQS
3
CMPIRQS
2
CNNIRQS
Description
This bit sets TCAN bit. If this bit is written to '1', TCAN is set to '1'. However, if this bit is written with '0', its value is ignored. Default Value: 0
Reserved. Keep this bitfield at the default value. Default Value: 0
This bit sets RWKIRQ bit. If this bit is written to '1', RWKIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. Default Value: 0
This bit sets URIRQ bit. If this bit is written to '1', URIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. Default Value: 0
This bit sets CMPIRQ bit. If this bit is written to '1', CMPIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. Default Value: 0
This bit sets CNNIRQ bit. If this bit is written to '1', CNNIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1264
0x403F4944 USBFS0_USBHOST_INTR_USBHOST_SET
22.1.89 USBFS0_USBHOST_INTR_USBHOST_SET (continued)
1
DIRQS
0
SOFIRQS
This bit sets DIRQ bit. If this bit is written to '1', DIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. Default Value: 0
This bit sets SOFIRQ bit. If this bit is written to '1', SOFIRQ is set to '1'. However, if this bit is written with '0', its value is ignored. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1265
0x403F4948 USBFS0_USBHOST_INTR_USBHOST_MASK
22.1.90 USBFS0_USBHOST_INTR_USBHOST_MASK
Address = 0x403F4948 Interrupt USB Host Mask Register Address: 0x403F4948 Retention: Retained
Bits SW Access HW Access
Name
7 RW R
TCANM
6
RW
R
RESERVED_6
5 RW R
RWKIRQM
4 RW R
URIRQM
3
2
RW
RW
R
R
CMPIRQM CNNIRQM
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
1 RW R DIRQM
9
17
25
0 RW R SOFIRQM
8
16
24
Bits
Name
7
TCANM
6
RESERVED_6
5
RWKIRQM
4
URIRQM
Description
This bit masks the interrupt by TCAN flag. '0' : Disables '1' : Enables Default Value: 0
Reserved. Keep this bitfield at the default value. Default Value: 0
This bit masks the interrupt by RWKIRQ flag. '0' : Disables '1' : Enables Default Value: 0
This bit masks the interrupt by URIRQ flag. '0' : Disables '1' : Enables Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1266
0x403F4948 USBFS0_USBHOST_INTR_USBHOST_MASK
22.1.90 USBFS0_USBHOST_INTR_USBHOST_MASK (continued)
3
CMPIRQM
2
CNNIRQM
1
DIRQM
0
SOFIRQM
This bit masks the interrupt by CMPIRQ flag. '0' : Disables '1' : Enables Default Value: 0
This bit masks the interrupt by CNNIRQ flag. '0' : Disables '1' : Enables Default Value: 0
This bit masks the interrupt by DIRQ flag. '0' : Disables '1' : Enables Default Value: 0
This bit masks the interrupt by SOF flag. '0' : Disables '1' : Enables Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1267
0x403F494C USBFS0_USBHOST_INTR_USBHOST_MASKED
22.1.91 USBFS0_USBHOST_INTR_USBHOST_MASKED
Address = 0x403F494C Interrupt USB Host Masked Register Address: 0x403F494C Retention: Not Retained
Bits SW Access HW Access
Name
7 R RW
TCANED
6
5
R
R
RW
RW
RESERVED_6
RWKIRQED
4 R RW
URIRQED
3
2
R
R
RW
RW
CMPIRQED CNNIRQED
1 R RW
DIRQED
0 R RW
SOFIRQED
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
7
TCANED
6
RESERVED_6
5
RWKIRQED
4
URIRQED
Description
This bit indicates the interrupt by TCAN flag. '0' : Doesn't request the interrupt by TCAN '1' : Request the interrupt by TCAN Default Value: 0
Reserved. Default Value: 0
This bit indicates the interrupt by RWKIRQ flag. '0' : Doesn't request the interrupt by RWKIRQ '1' : Request the interrupt by RWKIRQ Default Value: 0
This bit indicates the interrupt by URIRQ flag. '0' : Doesn't request the interrupt by URIRQ '1' : Request the interrupt by URIRQ Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1268
0x403F494C USBFS0_USBHOST_INTR_USBHOST_MASKED
22.1.91 USBFS0_USBHOST_INTR_USBHOST_MASKED (continued)
3
CMPIRQED
2
CNNIRQED
1
DIRQED
0
SOFIRQED
This bit indicates the interrupt by CMPIRQ flag. '0' : Doesn't request the interrupt by CMPIRQ '1' : Request the interrupt by CMPIRQ Default Value: 0
This bit indicates the interrupt by CNNIRQ flag. '0' : Doesn't request the interrupt by CNNIRQ '1' : Request the interrupt by CNNIRQ Default Value: 0
This bit indicates the interrupt by DIRQ flag. '0' : Doesn't request the interrupt by DIRQ '1' : Request the interrupt by DIRQ Default Value: 0
This bit indicates the interrupt by SOF flag. '0' : Doesn't request the interrupt by SOF '1' : Request the interrupt by SOF Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1269
0x403F4A00 USBFS0_USBHOST_INTR_HOST_EP
22.1.92 USBFS0_USBHOST_INTR_HOST_EP
Address = 0x403F4A00 Interrupt USB Host Endpoint Register Address: 0x403F4A00 Retention: Not Retained
Bits SW Access HW Access
Name
7
6
None
None
None [7:6]
5 RW1C W1S EP2SPK
4 RW1C W1S EP2DRQ
3 RW1C W1S EP1SPK
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2 RW1C W1S EP1DRQ
10
18
26
1
0
None
None
None
9
8
17
16
25
24
Bits
Name
5
EP2SPK
Description
This bit indicates that the data size transferred from the host does not satisfy the maximum packet size (including 0-byte) set by PKS1 in the Host Endpoint 2 Control Register (HOST_EP2_CTL) when the data has been received successfully. This bit is an interrupt cause, and writing '0' is ignored. Clear it by writing '1'. '0' : Received data size satisfies the maximum packet size '1' : Received data size does not satisfy the maximum packet size Note : - The SPK bit is not set during data transfer in the OUT direction. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1270
0x403F4A00 USBFS0_USBHOST_INTR_HOST_EP
22.1.92 USBFS0_USBHOST_INTR_HOST_EP (continued)
4
EP2DRQ
3
EP1SPK
2
EP1DRQ
This bit indicates that the EP2 packet transfer has normally ended, and processing of the data is required. The DRQ bit is an interrupt cause, and writing '0' is ignored. Clear the DRQ bit by writing '1'. '0' : Clears the interrupt cause '1' : Packet transfer normally ended Note : - If packet transfer mode (DMAE = '1') is not used, '1' must be written to the DRQ bit after data has been written or read to/from the send/receive buffer. Switch the access buffers once the DRQ bit is cleared. That DRQ = '0' may not be read after the DRQ bit is cleared. If the transfer direction is set to OUT, and the DRQ bit is cleared without writing buffer data while the DRQ bit is '1', it implies that 0-byte data is set. If DIR of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to '1' at initial settings, the DRQ bit of corresponding Endpoint is set at the same time. Also while the DRQ bit is not set, '1' must not be written. Default Value: 0
This bit indicates that the data size transferred from the host does not satisfy the maximum packet size (including 0-byte) set by PKS in the Host Endpoint 1 Control Register (HOST_EP1_CTL) when the data has been received successfully. This bit is an interrupt cause, and writing '0' is ignored. Clear it by writing '1'. '0' : Received data size satisfies the maximum packet size '1' : Received data size does not satisfy the maximum packet size Note : - The EP1SPK bit is not set during data transfer in the OUT direction. Default Value: 0
This bit indicates that the EP1 packet transfer has normally ended, and processing of the data is required. The DRQ bit is an interrupt cause, and writing '0' is ignored. Clear the DRQ bit by writing '1'. '0' : Clears the interrupt cause '1' : Packet transfer normally ended Note : - If automatic buffer transfer mode (DMAE = '1') is not used, '1' must be written to the DRQ bit after data has been written or read to/from the send/receive buffer. Switch the access buffers once the DRQ bit is cleared. That DRQ = '0' may not be read after the DRQ bit is cleared. If the transfer direction is set to OUT, and the DRQ bit is cleared without writing buffer data while the DRQ bit is '1', it implies that 0-byte data is set. If DIR of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is set to '1' at initial settings, the DRQ bit of corresponding Endpoint is set at the same time. Also while the DRQ bit is not set, '1' must not be written. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1271
0x403F4A04 USBFS0_USBHOST_INTR_HOST_EP_SET
22.1.93 USBFS0_USBHOST_INTR_HOST_EP_SET
Address = 0x403F4A04 Interrupt USB Host Endpoint Set Register Address: 0x403F4A04 Retention: Not Retained
Bits SW Access HW Access
Name
7
6
None
None
None [7:6]
5 RW1S
A EP2SPKS
4 RW1S
A EP2DRQS
3 RW1S
A EP1SPKS
2 RW1S
A EP1DRQS
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
1
0
None
None
None
9
8
17
16
25
24
Bits
Name
5
EP2SPKS
4
EP2DRQS
3
EP1SPKS
Description
This bit sets EP2SPK bit. If this bit is written to '1', EP2SPK is set to '1'. However, if this bit is written with '0', its value is ignored. Note: If BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is '1', EP2SPK can't be set to '1'. Default Value: 0
This bit sets EP2DRQ bit. If this bit is written to '1', EP2DRQ is set to '1'. However, if this bit is written with '0', its value is ignored. Note: If BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is '1', EP2DRQ can't be set to '1'. Default Value: 0
This bit sets EP1SPK bit. If this bit is written to '1', EP1SPK is set to '1'. However, if this bit is written with '0', its value is ignored. Note: If BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is '1', EP1SPK can't be set to '1'. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1272
0x403F4A04 USBFS0_USBHOST_INTR_HOST_EP_SET
22.1.93 USBFS0_USBHOST_INTR_HOST_EP_SET (continued)
2
EP1DRQS
This bit sets EP1DRQ bit. If this bit is written to '1', EP1DRQ is set to '1'. However, if this bit is written with '0', its value is ignored. Note: If BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is '1', EP1DRQ can't be set to '1'. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1273
0x403F4A08 USBFS0_USBHOST_INTR_HOST_EP_MASK
22.1.94 USBFS0_USBHOST_INTR_HOST_EP_MASK
Address = 0x403F4A08 Interrupt USB Host Endpoint Mask Register Address: 0x403F4A08 Retention: Retained
Bits SW Access HW Access
Name
7
6
None
None
None [7:6]
5 RW R EP2SPKM
4 RW R EP2DRQM
3 RW R EP1SPKM
2 RW R EP1DRQM
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
1
0
None
None
None
9
8
17
16
25
24
Bits
Name
5
EP2SPKM
4
EP2DRQM
3
EP1SPKM
2
EP1DRQM
Description
This bit masks the interrupt by EP2SPK flag. '0' : Disables '1' : Enables Default Value: 0
This bit masks the interrupt by EP2DRQ flag. '0' : Disables '1' : Enables Default Value: 0
This bit masks the interrupt by EP1SPK flag. '0' : Disables '1' : Enables Default Value: 0
This bit masks the interrupt by EP1DRQ flag. '0' : Disables '1' : Enables Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1274
0x403F4A0C USBFS0_USBHOST_INTR_HOST_EP_MASKED
22.1.95 USBFS0_USBHOST_INTR_HOST_EP_MASKED
Address = 0x403F4A0C Interrupt USB Host Endpoint Masked Register Address: 0x403F4A0C Retention: Not Retained
Bits SW Access HW Access
Name
7
6
None
None
None [7:6]
5
4
3
2
R
R
R
R
RW
RW
RW
RW
EP2SPKED EP2DRQED EP1SPKED EP1DRQED
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
1
0
None
None
None
9
8
17
16
25
24
Bits
Name
5
EP2SPKED
4
EP2DRQED
3
EP1SPKED
2
EP1DRQED
Description
This bit indicates the interrupt by EP2SPK flag. '0' : Doesn't request the interrupt by EP2SPK '1' : Request the interrupt by EP2SPK Default Value: 0
This bit indicates the interrupt by EP2DRQ flag. '0' : Doesn't request the interrupt by EP2DRQ '1' : Request the interrupt by EP2DRQ Default Value: 0
This bit indicates the interrupt by EP1SPK flag. '0' : Doesn't request the interrupt by EP1SPK '1' : Request the interrupt by EP1SPK Default Value: 0
This bit indicates the interrupt by EP1DRQ flag. '0' : Doesn't request the interrupt by EP1DRQ '1' : Request the interrupt by EP1DRQ Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1275
0x403F4B00 USBFS0_USBHOST_HOST_DMA_ENBL
22.1.96 USBFS0_USBHOST_HOST_DMA_ENBL
Address = 0x403F4B00 Host DMA Enable Register Address: 0x403F4B00 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:4]
4
3
2
RW
RW
R
R
DM_EP2DR DM_EP1DR
QE
QE
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
1
0
None
None
None
9
8
17
16
25
24
Bits
Name
3
DM_EP2DRQE
2
DM_EP1DRQE
Description
This bit enables DMA Request by EP2DRQ. '0' : Disable '1' : Enable Default Value: 0
This bit enables DMA Request by EP1DRQ. '0' : Disable '1' : Enable Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1276
0x403F4B20 USBFS0_USBHOST_HOST_EP1_BLK
22.1.97 USBFS0_USBHOST_HOST_EP1_BLK
Address = 0x403F4B20 Host Endpoint 1 Block Register Address: 0x403F4B20 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
BLK_NUM [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
BLK_NUM [31:24]
Bits 31 : 16
Name BLK_NUM
Description
Set the total byte number for DMA transfer. If HOST_EP1_RW1_DR or HOST_EP1_RW2_DR is written, the block number counter is decremented when DMAE='1'. - Set this bits before DMA transfer is enabled (HOST_DMA_ENBL.DM_DP1DRQE='1') Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1277
0x403F4B30 USBFS0_USBHOST_HOST_EP2_BLK
22.1.98 USBFS0_USBHOST_HOST_EP2_BLK
Address = 0x403F4B30 Host Endpoint 2 Block Register Address: 0x403F4B30 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
BLK_NUM [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
BLK_NUM [31:24]
Bits 31 : 16
Name BLK_NUM
Description
Set the total byte number for DMA transfer. If HOST_EP2_RW1_DR or HOST_EP2_RW2_DR is written, the block number counter is decremented when DMAE='1'. - Set this bits before DMA transfer is enabled (HOST_DMA_ENBL.DM_DP2DRQE='1') Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1278
Section F: Peripheral Group 4
This section encompasses the following chapter: Serial Memory Interface (SMIF) Registers chapter on page 1280
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1279
23 Serial Memory Interface (SMIF) Registers
This section discusses the Serial Memory Interface (SMIF) registers. It lists all the registers in mapping tables, in address order.
23.1 Register Details
Register SMIF0_CTL SMIF0_STATUS SMIF0_TX_CMD_FIFO_STATUS SMIF0_TX_CMD_FIFO_WR SMIF0_TX_DATA_FIFO_CTL SMIF0_TX_DATA_FIFO_STATUS SMIF0_TX_DATA_FIFO_WR1 SMIF0_TX_DATA_FIFO_WR2 SMIF0_TX_DATA_FIFO_WR4 SMIF0_RX_DATA_FIFO_CTL SMIF0_RX_DATA_FIFO_STATUS SMIF0_RX_DATA_FIFO_RD1 SMIF0_RX_DATA_FIFO_RD2 SMIF0_RX_DATA_FIFO_RD4 SMIF0_RX_DATA_FIFO_RD1_SILENT SMIF0_SLOW_CA_CTL SMIF0_SLOW_CA_CMD SMIF0_FAST_CA_CTL SMIF0_FAST_CA_CMD SMIF0_CRYPTO_CMD SMIF0_CRYPTO_INPUT0 SMIF0_CRYPTO_INPUT1 SMIF0_CRYPTO_INPUT2 SMIF0_CRYPTO_INPUT3 SMIF0_CRYPTO_KEY0 SMIF0_CRYPTO_KEY1
Address 0x40420000 0x40420004 0x40420044 0x40420050 0x40420080 0x40420084 0x40420090 0x40420094 0x40420098 0x404200C0 0x404200C4 0x404200D0 0x404200D4 0x404200D8 0x404200E0 0x40420100 0x40420108 0x40420180 0x40420188 0x40420200 0x40420220 0x40420224 0x40420228 0x4042022C 0x40420240 0x40420244
Description Control Status Transmitter command FIFO status Transmitter command FIFO write Transmitter data FIFO control Transmitter data FIFO status Transmitter data FIFO write Transmitter data FIFO write Transmitter data FIFO write Receiver data FIFO control Receiver data FIFO status Receiver data FIFO read Receiver data FIFO read Receiver data FIFO read Receiver data FIFO silent read Slow cache control Slow cache command Fast cache control Fast cache command Cryptography Command Cryptography input 0 Cryptography input 1 Cryptography input 2 Cryptography input 3 Cryptography key 0 Cryptography key 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1280
Serial Memory Interface (SMIF) Registers
Register SMIF0_CRYPTO_KEY2 SMIF0_CRYPTO_KEY3 SMIF0_CRYPTO_OUTPUT0 SMIF0_CRYPTO_OUTPUT1 SMIF0_CRYPTO_OUTPUT2 SMIF0_CRYPTO_OUTPUT3 SMIF0_INTR SMIF0_INTR_SET SMIF0_INTR_MASK SMIF0_INTR_MASKED SMIF0_DEVICE0_CTL SMIF0_DEVICE0_ADDR SMIF0_DEVICE0_MASK SMIF0_DEVICE0_ADDR_CTL SMIF0_DEVICE0_RD_CMD_CTL SMIF0_DEVICE0_RD_ADDR_CTL SMIF0_DEVICE0_RD_MODE_CTL SMIF0_DEVICE0_RD_DUMMY_CTL SMIF0_DEVICE0_RD_DATA_CTL SMIF0_DEVICE0_WR_CMD_CTL SMIF0_DEVICE0_WR_ADDR_CTL SMIF0_DEVICE0_WR_MODE_CTL SMIF0_DEVICE0_WR_DUMMY_CTL SMIF0_DEVICE0_WR_DATA_CTL SMIF0_DEVICE1_CTL SMIF0_DEVICE1_ADDR
SMIF0_DEVICE1_MASK
SMIF0_DEVICE1_ADDR_CTL
SMIF0_DEVICE1_RD_CMD_CTL
SMIF0_DEVICE1_RD_ADDR_CTL
SMIF0_DEVICE1_RD_MODE_CTL
SMIF0_DEVICE1_RD_DUMMY_CTL
SMIF0_DEVICE1_RD_DATA_CTL
SMIF0_DEVICE1_WR_CMD_CTL
SMIF0_DEVICE1_WR_ADDR_CTL
SMIF0_DEVICE1_WR_MODE_CTL
SMIF0_DEVICE1_WR_DUMMY_CTL
Address 0x40420248 0x4042024C 0x40420260 0x40420264 0x40420268 0x4042026C 0x404207C0 0x404207C4 0x404207C8 0x404207CC 0x40420800 0x40420808 0x4042080C 0x40420820 0x40420840 0x40420844 0x40420848 0x4042084C 0x40420850 0x40420860 0x40420864 0x40420868 0x4042086C 0x40420870 0x40420880 0x40420888
0x4042088C
0x404208A0
0x404208C0
0x404208C4
0x404208C8
0x404208CC
0x404208D0
0x404208E0
0x404208E4
0x404208E8
0x404208EC
Description
Cryptography key 2
Cryptography key 3
Cryptography output 0
Cryptography output 1
Cryptography output 2
Cryptography output 3
Interrupt register
Interrupt set register
Interrupt mask register
Interrupt masked register
Control
Device region base address
Device region mask
Address control
Read command control
Read address control
Read mode control
Read dummy control
Read data control
Write command control
Write address control
Write mode control
Write dummy control
Write data control
Control. See SMIF0_DEVICE0_CTL for the details of bit fields. Device region base address. See SMIF0_DEVICE0_ADDR for the details of bit fields.
Device region mask. See SMIF0_DEVICE0_MASK for the details of bit fields.
Address control. See SMIF0_DEVICE0_ADDR_CTL for the details of bit fields.
Read command control. See SMIF0_DEVICE0_RD_CMD_CTL for the details of bit fields. Read address control. See SMIF0_DEVICE0_RD_ADDR_CTL for the details of bit fields. Read mode control. See SMIF0_DEVICE0_RD_MODE_CTL for the details of bit fields. Read dummy control. See SMIF0_DEVICE0_RD_DUMMY_CTL for the details of bit fields. Read data control. See SMIF0_DEVICE0_RD_DATA_CTL for the details of bit fields. Write command control. See SMIF0_DEVICE0_WR_CMD_CTL for the details of bit fields. Write address control. See SMIF0_DEVICE0_WR_ADDR_CTL for the details of bit fields. Write mode control. See SMIF0_DEVICE0_WR_MODE_CTL for the details of bit fields. Write dummy control. See SMIF0_DEVICE0_WR_DUMMY_CTL for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1281
Register SMIF0_DEVICE1_WR_DATA_CTL SMIF0_DEVICE2_CTL SMIF0_DEVICE2_ADDR SMIF0_DEVICE2_MASK SMIF0_DEVICE2_ADDR_CTL SMIF0_DEVICE2_RD_CMD_CTL SMIF0_DEVICE2_RD_ADDR_CTL SMIF0_DEVICE2_RD_MODE_CTL SMIF0_DEVICE2_RD_DUMMY_CTL SMIF0_DEVICE2_RD_DATA_CTL SMIF0_DEVICE2_WR_CMD_CTL SMIF0_DEVICE2_WR_ADDR_CTL SMIF0_DEVICE2_WR_MODE_CTL SMIF0_DEVICE2_WR_DUMMY_CTL SMIF0_DEVICE2_WR_DATA_CTL SMIF0_DEVICE3_CTL SMIF0_DEVICE3_ADDR SMIF0_DEVICE3_MASK SMIF0_DEVICE3_ADDR_CTL SMIF0_DEVICE3_RD_CMD_CTL SMIF0_DEVICE3_RD_ADDR_CTL SMIF0_DEVICE3_RD_MODE_CTL SMIF0_DEVICE3_RD_DUMMY_CTL SMIF0_DEVICE3_RD_DATA_CTL SMIF0_DEVICE3_WR_CMD_CTL SMIF0_DEVICE3_WR_ADDR_CTL SMIF0_DEVICE3_WR_MODE_CTL SMIF0_DEVICE3_WR_DUMMY_CTL SMIF0_DEVICE3_WR_DATA_CTL
Serial Memory Interface (SMIF) Registers
Address 0x404208F0 0x40420900 0x40420908 0x4042090C 0x40420920 0x40420940 0x40420944 0x40420948 0x4042094C 0x40420950 0x40420960 0x40420964 0x40420968 0x4042096C 0x40420970 0x40420980 0x40420988 0x4042098C 0x404209A0 0x404209C0 0x404209C4 0x404209C8 0x404209CC 0x404209D0 0x404209E0 0x404209E4 0x404209E8 0x404209EC 0x404209F0
Description
Write data control. See SMIF0_DEVICE0_WR_DATA_CTL for the details of bit fields.
Control. See SMIF0_DEVICE0_CTLfor the details of bit fields.
Device region base address. See SMIF0_DEVICE0_ADDR for the details of bit fields.
Device region mask. See SMIF0_DEVICE0_MASK for the details of bit fields.
Address control. See SMIF0_DEVICE0_ADDR_CTL for the details of bit fields.
Read command control. See SMIF0_DEVICE0_RD_CMD_CTL for the details of bit fields.
Read address control. See SMIF0_DEVICE0_RD_ADDR_CTL for the details of bit fields.
Read mode control. See SMIF0_DEVICE0_RD_MODE_CTL for the details of bit fields.
Read dummy control. See SMIF0_DEVICE0_RD_DUMMY_CTL for the details of bit fields.
Read data control. See SMIF0_DEVICE0_RD_DATA_CTL for the details of bit fields.
Write command control. See SMIF0_DEVICE0_WR_CMD_CTL for the details of bit fields.
Write address control. See SMIF0_DEVICE0_WR_ADDR_CTL for the details of bit fields.
Write mode control. See SMIF0_DEVICE0_WR_MODE_CTL for the details of bit fields.
Write dummy control. See SMIF0_DEVICE0_WR_DUMMY_CTL for the details of bit fields.
Write data control. See SMIF0_DEVICE0_WR_DATA_CTL for the details of bit fields.
Control. See SMIF0_DEVICE0_CTL for the details of bit fields.
Device region base address. See SMIF0_DEVICE0_ADDR for the details of bit fields.
Device region mask. See SMIF0_DEVICE0_MASK for the details of bit fields.
Address control. See SMIF0_DEVICE0_ADDR_CTL for the details of bit fields.
Read command control. See SMIF0_DEVICE0_RD_CMD_CTL for the details of bit fields.
Read address control. See SMIF0_DEVICE0_RD_ADDR_CTL for the details of bit fields.
Read mode control. See SMIF0_DEVICE0_RD_MODE_CTL for the details of bit fields.
Read dummy control. See SMIF0_DEVICE0_RD_DUMMY_CTL for the details of bit fields.
Read data control. See SMIF0_DEVICE0_RD_DATA_CTL for the details of bit fields.
Write command control. See SMIF0_DEVICE0_WR_CMD_CTL for the details of bit fields.
Write address control. See SMIF0_DEVICE0_WR_ADDR_CTL for the details of bit fields.
Write mode control. See SMIF0_DEVICE0_WR_MODE_CTL for the details of bit fields.
Write dummy control. See SMIF0_DEVICE0_WR_DUMMY_CTL for the details of bit fields.
Write data control. See SMIF0_DEVICE0_WR_DATA_CTL for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1282
SMIF0_CTL
23.1.1 SMIF0_CTL
Address = 0x40420000 Control Address: 0x40420000 Retention: Retained
Bits
7
6
SW Access
HW Access
Name
Bits SW Access HW Access
Name
15
14
None
None
None [15:14]
Bits
23
22
SW Access
HW Access
Name
Bits
31
30
SW Access
RW
HW Access
R
Name
ENABLED
5
4
3
None
None
None [7:1]
13
12
11
RW
R
CLOCK_IF_RX_SEL [13:12]
21
20
19
None
None
None [23:19]
29
28
27
None
None
None [30:25]
2
1
10
9
None
None
None [11:8]
0 RW R XIP_MODE
8
18
17
16
RW
R
DESELECT_DELAY [18:16]
26
25
24
RW
R
BLOCK
Bits
Name
31
ENABLED
24
BLOCK
Description
IP enable: '0': Disabled. All non-retention registers are reset to their default value when the IP is disabled. When the IP is disabled, the XIP accesses produce AHB-Lite bus errors. '1': Enabled. Note: Before disabling the IP, SW should ensure that the IP is NOT busy (STATUS.BUSY is '0'), otherwise illegal interface transfers may occur. Default Value: 0
0x0: DISABLED :
0x1: ENABLED :
Specifies what happens for MMIO interface read accesses to an empty RX data FIFO or to a full TX format/data FIFO. Note: the FIFOs can only be accessed in MMIO_MODE. This field is not used for test controller accesses. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1283
SMIF0_CTL
23.1.1
SMIF0_CTL (continued)
0x0: BUS_ERROR :
0': Generate an AHB-Lite bus error. This option is useful when SW decides to use polling on STATUS.TR_BUSY to determine if a interface transfer is no longer busy (transfer is completed). This option adds SW complexity, but limits the number of AHB-Lite wait states (and limits ISR latency).
0x1: WAIT_STATES :
1': Introduce wait states. This setting potentially locks up the AHB-Lite infrastructure and may increase the CPU interrupt latency.This option is useful when SW performs TX/RX data FIFO accesses immediately after a command is setup using the TX format FIFO. This option has low SW complexity, but may result in a significant number of AHB-Lite wait states (and may increase ISR latency).
18 : 16
DESELECT_DELAY
13 : 12
CLOCK_IF_RX_SEL
0
XIP_MODE
Specifies the minimum duration of SPI deselection ("spi_select_out[]" is high/'1') in between SPI transfers: "0": 1 interface clock cycle. "1": 2 interface clock cycles. "2": 3 interface clock cycles. "3": 4 interface clock cycles. "4": 5 interface clock cycles. "5": 6 interface clock cycles. "6": 7 interface clock cycles. "7": 8 interface clock cycles. During SPI deselection, "spi_select_out[]" are '1'/inactive, "spi_data_out[]" are '1' and "spi_clk_out" is '0'/inactive. Default Value: 0
Specifies device interface receiver clock "clk_if_rx" source. MISO data is captured on the rising edge of "clk_if_rx". "0": "spi_clk_out" (internal clock) "1": !"spi_clk_out" (internal clock) "2": "spi_clk_in" (feedback clock) "3": !"spi_clk_in" (feedback clock) Note: the device interface transmitter clock "clk_if_tx" is fixed and is "spi_clk_out" MOSI data is driven on the falling edge of "clk_if_tx". Default Value: 3
Mode of operation. Note: this field should only be changed when the IP is disabled or when STATUS.BUSY is '0' and SW should not be executing from the XIP interface or MMIO interface. Default Value: 0
0x0: MMIO_MODE :
'0': MMIO mode. Individual MMIO accesses to TX and RX FIFOs are used to generate a sequence of SPI transfers. This mode of operation allows for large flexibility in terms of the SPI transfers that can be generated.
0x1: XIP_MODE :
1': XIP mode. eXecute-In-Place mode: incoming read and write transfers over the AHB-Lite bus infrastructure are automatically translated in SPI transfers to read data from and write data to a device. This mode of operation allow for efficient device read and write operations. This mode is only supported in SPI_MODE.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1284
SMIF0_STATUS
23.1.2 SMIF0_STATUS
Address = 0x40420004 Status Address: 0x40420004 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
None
HW Access
W
None
Name
BUSY
None
Bits
Name
31
BUSY
Description
Cache, cryptography, XIP, device interface or any other logic busy in the IP: '0': not busy '1': busy When BUSY is '0', the IP can be safely disabled without: - the potential loss of transient write data. - the potential risk of aborting an inflight SPI device interface transfer. When BUSY is '0', the mode of operation (XIP_MODE or MMIO_MODE) can be safely changed. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1285
SMIF0_TX_CMD_FIFO_STATUS
23.1.3 SMIF0_TX_CMD_FIFO_STATUS
Address = 0x40420044 Transmitter command FIFO status Address: 0x40420044 Retention: Not Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:3]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
0
R
W
USED3 [2:0]
10
9
8
18
17
16
26
25
24
Bits 2 : 0
Name USED3
Description
Number of entries that are used in the TX command FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 4]. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1286
SMIF0_TX_CMD_FIFO_WR
23.1.4 SMIF0_TX_CMD_FIFO_WR
Address = 0x40420050 Transmitter command FIFO write Address: 0x40420050 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
W
HW Access
R
Name
DATA20 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
W
HW Access
R
Name
DATA20 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
W
HW Access
None
R
Name
None [23:20]
DATA20 [19:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
Description
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1287
SMIF0_TX_CMD_FIFO_WR
23.1.4
19 : 0
SMIF0_TX_CMD_FIFO_WR (continued)
DATA20
Command data. The higher two bits DATA[19:18] specify the specific command "0"/TX: A SPI transfer always start with a TX command FIFO entry of the TX format. - DATA[17:16] specifies the width of the data transfer: - "0": 1 bit/cycle (single data transfer). - "1": 2 bits/cycle (dual data transfer). - "2": 4 bits/cycle (quad data transfer). - "3": 8 bits/cycle (octal data transfer). - DATA[15]: specifies whether this is the last TX Byte; i.e. whether the spi_select_out[3:0] IO output signals are de-activated after the transfer. - DATA[11:8] specifies which of the four devices are selected. DATA[11:8] are directly mapped to "spi_select_out[3:0]". Two devices can be selected at the same time in dual-quad mode. - '0': device deselected - '1': device selected - DATA[7:0] specifies the transmitted Byte. "1"/TX_COUNT: The TX_COUNT command relies on the TX data FIFO to provide the transmitted bytes. The "TX_COUNT" command is ALWAYS considered to be the last command of a SPI data transfers. - DATA[17:16] specifies the width of the transfer. - DATA[15:0] specifies the number of to be transmitted Bytes (minus 1) from the TX data FIFO. "2"/RX_COUNT: The RX_COUNT command relies on the RX data FIFO to accept the received bytes. The "RX_COUNT" command is ALWAYS considered to be the last command of a SPI data transfers. - DATA[17:16] specifies the width of the transfer. - DATA[15:0] specifies the number of to be transmitted Bytes (minus 1) to the RX data FIFO. "3"/DUMMY_COUNT: The "DUMMY_COUNT" command conveys dummy cycles. Dummy cycles are used to implement a Turn-Around time in which the SPI master changes from a transmitter driving the data lines to a receiver receiving on the same data lines. The "DUMMY_COUNT" command is ALWAYS considered to be NOT the last command of a SPI data transfers; i.e. it needs to be followed by another command. - DATA[15:0] specifies the number of dummy cycles (minus 1). In dummy cycles, the data lines are not driven. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1288
SMIF0_TX_DATA_FIFO_CTL
23.1.5 SMIF0_TX_DATA_FIFO_CTL
Address = 0x40420080 Transmitter data FIFO control Address: 0x40420080 Retention: Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:3]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
0
RW
R
TRIGGER_LEVEL [2:0]
10
9
8
18
17
16
26
25
24
Bits 2 : 0
Name TRIGGER_LEVEL
Description
Determines when the TX data FIFO "tr_tx_req" trigger is activated (trigger activation requires MMIO_MODE, the trigger is NOT activated in XIP_MODE): - Trigger is active when TX_DATA_FIFO_STATUS.USED <= TRIGGER_LEVEL. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1289
SMIF0_TX_DATA_FIFO_STATUS
23.1.6 SMIF0_TX_DATA_FIFO_STATUS
Address = 0x40420084 Transmitter data FIFO status Address: 0x40420084 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
R
HW Access
None
W
Name
None [7:4]
USED4 [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 3 : 0
Name USED4
Description
Number of entries that are used in the TX data FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 8]. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1290
SMIF0_TX_DATA_FIFO_WR1
23.1.7 SMIF0_TX_DATA_FIFO_WR1
Address = 0x40420090 Transmitter data FIFO write Address: 0x40420090 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
W
HW Access
R
Name
DATA0 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 0
Name DATA0
Description
TX data (written to TX data FIFO). Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1291
SMIF0_TX_DATA_FIFO_WR2
23.1.8 SMIF0_TX_DATA_FIFO_WR2
Address = 0x40420094 Transmitter data FIFO write Address: 0x40420094 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
W
HW Access
R
Name
DATA0 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
W
HW Access
R
Name
DATA1 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 8
7 : 0
Name DATA1
DATA0
Description
TX data (written to TX data FIFO, second byte). Default Value: 0
TX data (written to TX data FIFO, first byte). Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1292
SMIF0_TX_DATA_FIFO_WR4
23.1.9 SMIF0_TX_DATA_FIFO_WR4
Address = 0x40420098 Transmitter data FIFO write Address: 0x40420098 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
W
HW Access
R
Name
DATA0 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
W
HW Access
R
Name
DATA1 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
W
HW Access
R
Name
DATA2 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
W
HW Access
R
Name
DATA3 [31:24]
Bits 31 : 24 23 : 16 15 : 8 7 : 0
Name DATA3 DATA2 DATA1 DATA0
Description
TX data (written to TX data FIFO, fourth byte). Default Value: 0
TX data (written to TX data FIFO, third byte). Default Value: 0
TX data (written to TX data FIFO, second byte). Default Value: 0
TX data (written to TX data FIFO, first byte). Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1293
SMIF0_RX_DATA_FIFO_CTL
23.1.10 SMIF0_RX_DATA_FIFO_CTL
Address = 0x404200C0 Receiver data FIFO control Address: 0x404200C0 Retention: Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:3]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
0
RW
R
TRIGGER_LEVEL [2:0]
10
9
8
18
17
16
26
25
24
Bits 2 : 0
Name TRIGGER_LEVEL
Description
Determines when RX data FIFO "tr_rx_req" trigger is activated (trigger activation requires MMIO_MODE, the trigger is NOT activated in XIP_MODE): - Trigger is active when RX_DATA_FIFO_STATUS.USED > TRIGGER_LEVEL. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1294
SMIF0_RX_DATA_FIFO_STATUS
23.1.11 SMIF0_RX_DATA_FIFO_STATUS
Address = 0x404200C4 Receiver data FIFO status Address: 0x404200C4 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
R
HW Access
None
W
Name
None [7:4]
USED4 [3:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 3 : 0
Name USED4
Description
Number of entries that are used in the RX data FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 8]. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1295
SMIF0_RX_DATA_FIFO_RD1
23.1.12 SMIF0_RX_DATA_FIFO_RD1
Address = 0x404200D0 Receiver data FIFO read Address: 0x404200D0 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
DATA0 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 0
Name DATA0
Description
RX data (read from RX data FIFO). Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1296
SMIF0_RX_DATA_FIFO_RD2
23.1.13 SMIF0_RX_DATA_FIFO_RD2
Address = 0x404200D4 Receiver data FIFO read Address: 0x404200D4 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
DATA0 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
DATA1 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 8
7 : 0
Name DATA1
DATA0
Description
RX data (read from RX data FIFO, second byte). Default Value: 0
RX data (read from RX data FIFO, first byte). Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1297
SMIF0_RX_DATA_FIFO_RD4
23.1.14 SMIF0_RX_DATA_FIFO_RD4
Address = 0x404200D8 Receiver data FIFO read Address: 0x404200D8 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
DATA0 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
DATA1 [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
W
Name
DATA2 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
W
Name
DATA3 [31:24]
Bits 31 : 24 23 : 16 15 : 8 7 : 0
Name DATA3 DATA2 DATA1 DATA0
Description
RX data (read from RX data FIFO, fourth byte). Default Value: 0
RX data (read from RX data FIFO, third byte). Default Value: 0
RX data (read from RX data FIFO, second byte). Default Value: 0
RX data (read from RX data FIFO, first byte). Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1298
SMIF0_RX_DATA_FIFO_RD1_SILENT
23.1.15 SMIF0_RX_DATA_FIFO_RD1_SILENT
Address = 0x404200E0 Receiver data FIFO silent read Address: 0x404200E0 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
DATA0 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 0
Name DATA0
Description
RX data (read from RX data FIFO). Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1299
SMIF0_SLOW_CA_CTL
23.1.16 SMIF0_SLOW_CA_CTL
Address = 0x40420100 Slow cache control Address: 0x40420100 Retention: Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:18]
Bits
31
30
29
SW Access
RW
RW
HW Access
R
R
Name
ENABLED PREF_EN
28
27
None
None
None [29:26]
2
1
0
10
9
8
18
17
16
RW
R
WAY [17:16]
26
25
24
RW
R
SET_ADDR [25:24]
Bits
Name
31
ENABLED
30
PREF_EN
25 : 24 17 : 16
SET_ADDR WAY
Description
Cache enable: '0': Disabled. '1': Enabled. Default Value: 1
Prefetch enable: '0': Disabled. '1': Enabled. Prefetching requires the cache to be enabled; i.e. ENABLED is '1'. Default Value: 1
Specifies the cache set for which cache information is provided in SLOW_CA_STATUS0/1/2. Default Value: 0
Specifies the cache way for which cache information is provided in SLOW_CA_STATUS0/1/2. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1300
SMIF0_SLOW_CA_CMD
23.1.17 SMIF0_SLOW_CA_CMD
Address = 0x40420108 Slow cache command Address: 0x40420108 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW1S
HW Access
None
RW1C
Name
None [7:1]
INV
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
INV
Description
Cache and prefetch buffer invalidation. SW writes a '1' to clear the cache and prefetch buffer. The cache's LRU structure is also reset to its default state. Note, A write access will invalidate the prefetch buffer automatically in hardware. A write access should invalidate both fast and slow caches, by firmware. Note, firmware should invalidate the cache and prefetch buffer only when STATUS.BUSY is '0'. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1301
SMIF0_FAST_CA_CTL
23.1.18 SMIF0_FAST_CA_CTL
Address = 0x40420180 Fast cache control Address: 0x40420180 Retention: Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:18]
Bits
31
30
29
SW Access
RW
RW
HW Access
R
R
Name
ENABLED PREF_EN
28
27
None
None
None [29:26]
Bits 31 30 25 : 24 17 : 16
Name ENABLED PREF_EN SET_ADDR WAY
Description
See SLOW_CA_CTL.ENABLED. Default Value: 1
See SLOW_CA_CTL.PREF_EN. Default Value: 1
See SLOW_CA_CTL.SET_ADDR. Default Value: 0
See SLOW_CA_CTL.WAY. Default Value: 0
2
1
0
10
9
8
18
17
16
RW
R
WAY [17:16]
26
25
24
RW
R
SET_ADDR [25:24]
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1302
SMIF0_FAST_CA_CMD
23.1.19 SMIF0_FAST_CA_CMD
Address = 0x40420188 Fast cache command Address: 0x40420188 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW1S
HW Access
None
RW1C
Name
None [7:1]
INV
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
INV
Description
See SLOW_CA_CMD.INV. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1303
SMIF0_CRYPTO_CMD
23.1.20 SMIF0_CRYPTO_CMD
Address = 0x40420200 Cryptography Command Address: 0x40420200 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW1S
HW Access
None
RW1C
Name
None [7:1]
START
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
START
Description
SW sets this field to '1' to start a AES-128 forward block cipher operation (on the address in CRYPTO_ADDR). HW sets this field to '0' to indicate that the operation has completed. Once completed, the result of the operation can be read from CRYPTO_RESULT0, ..., CRYPTO_RESULT3. The operation takes roughly 13 clk_hf clock cycles. Note: An operation can only be started in MMIO_MODE. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1304
SMIF0_CRYPTO_INPUT0
23.1.21 SMIF0_CRYPTO_INPUT0
Address = 0x40420220 Cryptography input 0 Address: 0x40420220 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
INPUT [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
INPUT [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
INPUT [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
INPUT [31:24]
Bits 31 : 0
Name INPUT
Description
Four Bytes of the plaintext PT[31:0] = CRYPTO_INPUT0.INPUT[31:0]. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1305
SMIF0_CRYPTO_INPUT1
23.1.22 SMIF0_CRYPTO_INPUT1
Address = 0x40420224 Cryptography input 1 Address: 0x40420224 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
INPUT [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
INPUT [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
INPUT [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
INPUT [31:24]
Bits 31 : 0
Name INPUT
Description
Four Bytes of the plaintext PT[63:32] = CRYPTO_INPUT1.INPUT[31:0]. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1306
SMIF0_CRYPTO_INPUT2
23.1.23 SMIF0_CRYPTO_INPUT2
Address = 0x40420228 Cryptography input 2 Address: 0x40420228 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
INPUT [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
INPUT [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
INPUT [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
INPUT [31:24]
Bits 31 : 0
Name INPUT
Description
Four Bytes of the plaintext PT[95:64] = CRYPTO_INPUT2.INPUT[31:0]. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1307
SMIF0_CRYPTO_INPUT3
23.1.24 SMIF0_CRYPTO_INPUT3
Address = 0x4042022C Cryptography input 3 Address: 0x4042022C Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
INPUT [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
INPUT [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
INPUT [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
INPUT [31:24]
Bits 31 : 0
Name INPUT
Description
Four Bytes of the plaintext PT[127:96] = CRYPTO_INPUT3.INPUT[31:0]. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1308
SMIF0_CRYPTO_KEY0
23.1.25 SMIF0_CRYPTO_KEY0
Address = 0x40420240 Cryptography key 0 Address: 0x40420240 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
W
HW Access
R
Name
KEY [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
W
HW Access
R
Name
KEY [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
W
HW Access
R
Name
KEY [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
W
HW Access
R
Name
KEY [31:24]
Bits 31 : 0
Name KEY
Description
Four Bytes of the key KEY[31:0] = CRYPTO_KEY0.KEY[31:0]. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1309
SMIF0_CRYPTO_KEY1
23.1.26 SMIF0_CRYPTO_KEY1
Address = 0x40420244 Cryptography key 1 Address: 0x40420244 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
W
HW Access
R
Name
KEY [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
W
HW Access
R
Name
KEY [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
W
HW Access
R
Name
KEY [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
W
HW Access
R
Name
KEY [31:24]
Bits 31 : 0
Name KEY
Description
Four Bytes of the key KEY[63:32] = CRYPTO_KEY1.KEY[31:0]. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1310
SMIF0_CRYPTO_KEY2
23.1.27 SMIF0_CRYPTO_KEY2
Address = 0x40420248 Cryptography key 2 Address: 0x40420248 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
W
HW Access
R
Name
KEY [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
W
HW Access
R
Name
KEY [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
W
HW Access
R
Name
KEY [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
W
HW Access
R
Name
KEY [31:24]
Bits 31 : 0
Name KEY
Description
Four Bytes of the key KEY[95:64] = CRYPTO_KEY2.KEY[31:0]. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1311
SMIF0_CRYPTO_KEY3
23.1.28 SMIF0_CRYPTO_KEY3
Address = 0x4042024C Cryptography key 3 Address: 0x4042024C Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
W
HW Access
R
Name
KEY [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
W
HW Access
R
Name
KEY [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
W
HW Access
R
Name
KEY [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
W
HW Access
R
Name
KEY [31:24]
Bits 31 : 0
Name KEY
Description
Four Bytes of the key KEY[127:96] = CRYPTO_KEY3.KEY[31:0]. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1312
SMIF0_CRYPTO_OUTPUT0
23.1.29 SMIF0_CRYPTO_OUTPUT0
Address = 0x40420260 Cryptography output 0 Address: 0x40420260 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
A
Name
OUTPUT [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
A
Name
OUTPUT [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
A
Name
OUTPUT [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
A
Name
OUTPUT [31:24]
Bits 31 : 0
Name OUTPUT
Description
Four Bytes of the ciphertext CT[31:0] = CRYPTO_OUTPUT0.OUTPUT[31:0]. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1313
SMIF0_CRYPTO_OUTPUT1
23.1.30 SMIF0_CRYPTO_OUTPUT1
Address = 0x40420264 Cryptography output 1 Address: 0x40420264 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
A
Name
OUTPUT [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
A
Name
OUTPUT [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
A
Name
OUTPUT [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
A
Name
OUTPUT [31:24]
Bits 31 : 0
Name OUTPUT
Description
Four Bytes of the ciphertext CT[63:32] = CRYPTO_OUTPUT1.OUTPUT[31:0]. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1314
SMIF0_CRYPTO_OUTPUT2
23.1.31 SMIF0_CRYPTO_OUTPUT2
Address = 0x40420268 Cryptography output 2 Address: 0x40420268 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
A
Name
OUTPUT [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
A
Name
OUTPUT [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
A
Name
OUTPUT [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
A
Name
OUTPUT [31:24]
Bits 31 : 0
Name OUTPUT
Description
Four Bytes of the ciphertext CT[95:64] = CRYPTO_OUTPUT2.OUTPUT[31:0]. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1315
SMIF0_CRYPTO_OUTPUT3
23.1.32 SMIF0_CRYPTO_OUTPUT3
Address = 0x4042026C Cryptography output 3 Address: 0x4042026C Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
A
Name
OUTPUT [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
A
Name
OUTPUT [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
A
Name
OUTPUT [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
A
Name
OUTPUT [31:24]
Bits 31 : 0
Name OUTPUT
Description
Four Bytes of the ciphertext CT[127:96] = CRYPTO_OUTPUT3.OUTPUT[31:0]. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1316
SMIF0_INTR
23.1.33 SMIF0_INTR
Address = 0x404207C0 Interrupt register Address: 0x404207C0 Retention: Not Retained
Bits SW Access HW Access
Name
7
6
None
None
None [7:6]
Bits
15
14
SW Access
HW Access
Name
Bits
23
22
SW Access
HW Access
Name
Bits
31
30
SW Access
HW Access
Name
5
4
3
2
RW1C
RW1C
RW1C
RW1C
RW1S
RW1S
RW1S
RW1S
RX_DATA_FIFO_UNDER
FLOW
TX_DATA_FIFO_OVERF
LOW
TX_CMD_FI-
FO_OVERF LOW
XIP_ALIGNMENT_ER-
ROR
1 RW1C RW1S
TR_RX_REQ
13
12
11
10
9
None
None
None [15:8]
21
20
19
18
17
None
None
None [23:16]
29
28
27
26
25
None
None
None [31:24]
0 RW1C RW1S TR_TX_REQ
8
16
24
Bits
Name
Description
5
RX_DATA_FIFO_UNDER- Activated in MMIO mode, on an AHB-Lite read transfer from the RX data FIFO (RX_DATA_FI-
FLOW
FO_RD1, RX_DATA_FIFO_RD2, RX_DATA_FIFO_RD4) with not enough entries available.
Only activated for NON test bus controller transfers.
Default Value: 0
4
TX_DATA_FIFO_OVER- Activated in MMIO mode, on an AHB-Lite write transfer to the TX data FIFO (TX_DATA_FI-
FLOW
FO_WR1, TX_DATA_FIFO_WR2, TX_DATA_FIFO_WR4) with not enough free entries avail-
able.
Default Value: 0
3
TX_CMD_FIFO_OVER- Activated in MMIO mode, on an AHB-Lite write transfer to the TX command FIFO (TX_CMD_FI-
FLOW
FO_WR) with not enough free entries available.
Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1317
SMIF0_INTR
23.1.33 SMIF0_INTR (continued)
2
XIP_ALIGNMENT_ER-
Activated in XIP mode, if:
ROR
- The selected device's ADDR_CTL.DIV2 is '1' and the AHB-Lite bus transfer address is not a
multiple of 2.
- The selected device's ADDR_CTL.DIV2 is '1' and the XIP transfer request is NOT for a multiple
of 2 Bytes.
Note: In dual-quad SPI mode (ADDR_CTL.DIV is '1'), each memory device contributes a 4-bit
nibble for read data or write data. This is only possible if the request address is a multiple of 2
and the number of requested Bytes is a multiple of 2.
Default Value: 0
1
TR_RX_REQ
Activated in MMIO mode, when a RX data FIFO trigger "tr_rx_req" is activated. Default Value: 0
0
TR_TX_REQ
Activated in MMIO mode, when a TX data FIFO trigger "tr_tx_req" is activated. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1318
SMIF0_INTR_SET
23.1.34 SMIF0_INTR_SET
Address = 0x404207C4 Interrupt set register Address: 0x404207C4 Retention: Not Retained
Bits SW Access HW Access
Name
7
6
None
None
None [7:6]
5
4
3
2
RW1S
RW1S
RW1S
RW1S
A
A
A
A
RX_DATA_FIFO_UNDER
FLOW
TX_DATA_FIFO_OVERF
LOW
TX_CMD_FI-
FO_OVERF LOW
XIP_ALIGNMENT_ER-
ROR
1 RW1S
A
TR_RX_REQ
Bits
15
14
13
12
11
10
9
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
SW Access
None
HW Access
None
Name
None [31:24]
0 RW1S
A TR_TX_REQ
8
16
24
Bits
Name
Description
5
RX_DATA_FIFO_UNDER- Write with '1' to set corresponding bit in interrupt request register.
FLOW
Default Value: 0
4
TX_DATA_FIFO_OVER- Write with '1' to set corresponding bit in interrupt request register.
FLOW
Default Value: 0
3
TX_CMD_FIFO_OVER- Write with '1' to set corresponding bit in interrupt request register.
FLOW
Default Value: 0
2
XIP_ALIGNMENT_ER-
Write with '1' to set corresponding bit in interrupt request register.
ROR
Default Value: 0
1
TR_RX_REQ
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
0
TR_TX_REQ
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1319
SMIF0_INTR_MASK
23.1.35 SMIF0_INTR_MASK
Address = 0x404207C8 Interrupt mask register Address: 0x404207C8 Retention: Retained
Bits SW Access HW Access
Name
7
6
None
None
None [7:6]
5
4
3
2
RW
RW
RW
RW
R
R
R
R
RX_DATA_FIFO_UNDER
FLOW
TX_DATA_FIFO_OVERF
LOW
TX_CMD_FI-
FO_OVERF LOW
XIP_ALIGNMENT_ER-
ROR
1 RW R
TR_RX_REQ
Bits
15
14
13
12
11
10
9
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
SW Access
None
HW Access
None
Name
None [31:24]
0 RW R TR_TX_REQ
8
16
24
Bits
Name
Description
5
RX_DATA_FIFO_UNDER- Mask bit for corresponding bit in interrupt request register.
FLOW
Default Value: 0
4
TX_DATA_FIFO_OVER- Mask bit for corresponding bit in interrupt request register.
FLOW
Default Value: 0
3
TX_CMD_FIFO_OVER- Mask bit for corresponding bit in interrupt request register.
FLOW
Default Value: 0
2
XIP_ALIGNMENT_ER-
Mask bit for corresponding bit in interrupt request register.
ROR
Default Value: 0
1
TR_RX_REQ
Mask bit for corresponding bit in interrupt request register. Default Value: 0
0
TR_TX_REQ
Mask bit for corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1320
SMIF0_INTR_MASKED
23.1.36 SMIF0_INTR_MASKED
Address = 0x404207CC Interrupt masked register Address: 0x404207CC Retention: Not Retained
Bits SW Access HW Access
Name
7
6
None
None
None [7:6]
5
4
3
2
R
R
R
R
W
W
W
W
RX_DATA_FIFO_UNDER
FLOW
TX_DATA_FIFO_OVERF
LOW
TX_CMD_FI-
FO_OVERF LOW
XIP_ALIGNMENT_ER-
ROR
1 R W
TR_RX_REQ
Bits
15
14
13
12
11
10
9
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
SW Access
None
HW Access
None
Name
None [31:24]
0 R W TR_TX_REQ 8
16
24
Bits
Name
Description
5
RX_DATA_FIFO_UNDER- Logical and of corresponding request and mask bits.
FLOW
Default Value: 0
4
TX_DATA_FIFO_OVER- Logical and of corresponding request and mask bits.
FLOW
Default Value: 0
3
TX_CMD_FIFO_OVER- Logical and of corresponding request and mask bits.
FLOW
Default Value: 0
2
XIP_ALIGNMENT_ER-
Logical and of corresponding request and mask bits.
ROR
Default Value: 0
1
TR_RX_REQ
Logical and of corresponding request and mask bits. Default Value: 0
0
TR_TX_REQ
Logical and of corresponding request and mask bits. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1321
SMIF0_DEVICE0_CTL
23.1.37 SMIF0_DEVICE0_CTL
Address = 0x40420800 Control Address: 0x40420800 Retention: Retained
Bits
7
6
5
4
3
2
SW Access
None
HW Access
None
Name
None [7:1]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:9]
Bits
23
22
SW Access
HW Access
Name
Bits
31
30
SW Access
RW
HW Access
R
Name
ENABLED
21
20
19
18
None
None
None [23:18]
29
28
27
26
None
None
None [30:24]
1
0
RW
R
WR_EN
9
8
RW
R
CRYPTO_EN
17
16
RW
R
DATA_SEL [17:16]
25
24
Bits
Name
31
ENABLED
17 : 16
DATA_SEL
Description
Device enable: '0': Disabled. '1': Enabled. Default Value: 0
Specifies the connection of the IP's data lines (spi_data[0], , spi_data[7]) to the device's data lines (SI/IO0, SO/IO1, IO2, IO3, IO4, IO5, IO6, IO7): "0": spi_data[0] = IO0, spi_data[1] = IO1, , spi_data[7] = IO7. This value is allowed for single, dual, quad, dual quad and octal SPI modes. This value must be used for the first device in dual quad SPI mode. This value must be used for octal SPI mode. "1": spi_data[2] = IO0, spi_data[3] = IO1. This value is only allowed for single and dual SPI modes. "2": spi_data[4] = IO0, spi_data[5] = IO1, , spi_data[7] = IO3. This value is only allowed for single, dual, quad and dual quad SPI modes. In dual quad SPI mode, this value must be used for the second device. "3": spi_data[6] = IO0, spi_data[7] = IO1. This value is only allowed for single and dual SPI modes. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1322
SMIF0_DEVICE0_CTL
23.1.37 SMIF0_DEVICE0_CTL (continued)
8
CRYPTO_EN
0
WR_EN
Cryptography on read/write accesses: '0': disabled. '1': enabled. Default Value: 0
Write enable: '0': write transfers are not allowed to this device. An attempt to write to this device results in an AHB-Lite bus error. '1': write transfers are allowed to this device. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1323
SMIF0_DEVICE0_ADDR
23.1.38 SMIF0_DEVICE0_ADDR
Address = 0x40420808 Device region base address Address: 0x40420808 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
A
Name
ADDR [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
A
Name
ADDR [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
A
Name
ADDR [31:24]
Bits 31 : 8
Name ADDR
Description
Specifies the base address of the device region. If the device region is 2^m Bytes, ADDR MUST be a multiple of 2^m. In dual quad SPI data transfer, the two devices should have the same ADDR and MASK register settings. The device control information (ADDR_CTL, RD_CMD_CTL, etc.) are provided by the MMIO control registers of the device with the lowest index. The most significant bit fields are constants and set based on the SMIF_XIP_ADDR parameter. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK is 0xff00:0000 (16 MB XIP memory region), ADDR[31:24] = SMIF_XIP_ADDR[31:24]. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1324
SMIF0_DEVICE0_MASK
23.1.39 SMIF0_DEVICE0_MASK
Address = 0x4042080C Device region mask Address: 0x4042080C Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
A
Name
MASK [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
A
Name
MASK [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
A
Name
MASK [31:24]
Bits 31 : 8
Name MASK
Description
Specifies the size of the device region. All '1' bits are used to compare the incoming transfer request address A[31:0] with the address as specified in ADDR.ADDR: Address A is in the device when (A[31:8] & MASK[31:8]) == ADDR.ADDR[31:8]. The most significant bit fields are constants and set to'1'. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK is 0xff00:0000 (16 MB XIP memory region), MASK[31:24] = 0xff. Note: a transfer request that is not in any device region results in an AHB-Lite bus error. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1325
SMIF0_DEVICE0_ADDR_CTL
23.1.40 SMIF0_DEVICE0_ADDR_CTL
Address = 0x40420820 Address control Address: 0x40420820 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:2]
SIZE2 [1:0]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:9]
9
8
RW
R
DIV2
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
8
DIV2
1 : 0
SIZE2
Description
Specifies if the AHB-Lite bus transfer address is divided by 2 or not: '0': No divide by 2. '1': Divide by 2. This functionality is used for read and write operation in XIP, dual quad SPI mode; i.e. this DIV2 must be set to '1' in dual quad SPI mode. If the transfer request address is NOT a multiple of 2 or the requested number of Bytes is not a multiple of 2, the XIP_ALIGNMENT_ERROR interrupt cause is activated. Default Value: 0
Specifies the size of the XIP device address in Bytes: "0": 1 Byte address. "1": 2 Byte address. "2": 3 Byte address. "3": 4 Byte address. The lower significant address Bytes of the transfer request are used as XIP address to the external device. Note that for dual quad SPI data transfer, the transfer request address is divided by 2. Therefore, the transfer request address needs to be a multiple of 2. If the trasnfer requestaddress is NOT a multiple of 2, the XIP_ALIGNMENT_ERROR interrupt cause is activated. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1326
SMIF0_DEVICE0_RD_CMD_CTL
23.1.41 SMIF0_DEVICE0_RD_CMD_CTL
Address = 0x40420840 Read command control Address: 0x40420840 Retention: Retained
Bits
7
6
5
4
3
2
SW Access
RW
HW Access
R
Name
CODE [7:0]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:18]
Bits
31
30
29
28
27
26
SW Access
RW
None
HW Access
R
None
Name
PRESENT
None [30:24]
Bits
Name
31
PRESENT
17 : 16
WIDTH
7 : 0
CODE
Description
Presence of command field: '0': not present '1': present Default Value: 0
Width of data transfer: "0": 1 bit/cycle (single data transfer). "1": 2 bits/cycle (dual data transfer). "2": 4 bits/cycle (quad data transfer). "3": 8 bits/cycle (octal data transfer). Default Value: 0
Command byte code. Default Value: 0
1
0
9
8
17
16
RW
R
WIDTH [17:16]
25
24
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1327
SMIF0_DEVICE0_RD_ADDR_CTL
23.1.42 SMIF0_DEVICE0_RD_ADDR_CTL
Address = 0x40420844 Read address control Address: 0x40420844 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
HW Access
None
R
Name
None [23:18]
WIDTH [17:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 17 : 16
Name WIDTH
Description
Width of transfer. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1328
SMIF0_DEVICE0_RD_MODE_CTL
23.1.43 SMIF0_DEVICE0_RD_MODE_CTL
Address = 0x40420848 Read mode control Address: 0x40420848 Retention: Retained
Bits
7
6
5
4
3
2
SW Access
RW
HW Access
R
Name
CODE [7:0]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:18]
Bits
31
30
29
28
27
26
SW Access
RW
None
HW Access
R
None
Name
PRESENT
None [30:24]
Bits
Name
31
PRESENT
17 : 16 7 : 0
WIDTH CODE
Description
Presence of mode field: '0': not present '1': present Default Value: 0
Width of transfer. Default Value: 0
Mode byte code. Default Value: 0
1
0
9
8
17
16
RW
R
WIDTH [17:16]
25
24
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1329
SMIF0_DEVICE0_RD_DUMMY_CTL
23.1.44 SMIF0_DEVICE0_RD_DUMMY_CTL
Address = 0x4042084C Read dummy control Address: 0x4042084C Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:5]
SIZE5 [4:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
None
HW Access
R
None
Name
PRESENT
None [30:24]
Bits
Name
31
PRESENT
4 : 0
SIZE5
Description
Presence of dummy cycles: '0': not present '1': present Default Value: 0
Number of dummy cycles (minus 1): "0": 1 cycles ... "31": 32 cycles. Note: this field specifies dummy cycles, not dummy Bytes! Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1330
SMIF0_DEVICE0_RD_DATA_CTL
23.1.45 SMIF0_DEVICE0_RD_DATA_CTL
Address = 0x40420850 Read data control Address: 0x40420850 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
HW Access
None
R
Name
None [23:18]
WIDTH [17:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 17 : 16
Name WIDTH
Description
Width of transfer. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1331
SMIF0_DEVICE0_WR_CMD_CTL
23.1.46 SMIF0_DEVICE0_WR_CMD_CTL
Address = 0x40420860 Write command control Address: 0x40420860 Retention: Retained
Bits
7
6
5
4
3
2
SW Access
RW
HW Access
R
Name
CODE [7:0]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:18]
Bits
31
30
29
28
27
26
SW Access
RW
None
HW Access
R
None
Name
PRESENT
None [30:24]
Bits
Name
31
PRESENT
17 : 16 7 : 0
WIDTH CODE
Description
Presence of command field: '0': not present '1': present Default Value: 0
Width of transfer. Default Value: 0
Command byte code. Default Value: 0
1
0
9
8
17
16
RW
R
WIDTH [17:16]
25
24
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1332
SMIF0_DEVICE0_WR_ADDR_CTL
23.1.47 SMIF0_DEVICE0_WR_ADDR_CTL
Address = 0x40420864 Write address control Address: 0x40420864 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
HW Access
None
R
Name
None [23:18]
WIDTH [17:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 17 : 16
Name WIDTH
Description
Width of transfer. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1333
SMIF0_DEVICE0_WR_MODE_CTL
23.1.48 SMIF0_DEVICE0_WR_MODE_CTL
Address = 0x40420868 Write mode control Address: 0x40420868 Retention: Retained
Bits
7
6
5
4
3
2
SW Access
RW
HW Access
R
Name
CODE [7:0]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:18]
Bits
31
30
29
28
27
26
SW Access
RW
None
HW Access
R
None
Name
PRESENT
None [30:24]
Bits
Name
31
PRESENT
17 : 16 7 : 0
WIDTH CODE
Description
Presence of mode field: '0': not present '1': present Default Value: 0
Width of transfer. Default Value: 0
Mode byte code. Default Value: 0
1
0
9
8
17
16
RW
R
WIDTH [17:16]
25
24
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1334
SMIF0_DEVICE0_WR_DUMMY_CTL
23.1.49 SMIF0_DEVICE0_WR_DUMMY_CTL
Address = 0x4042086C Write dummy control Address: 0x4042086C Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:5]
SIZE5 [4:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
None
HW Access
R
None
Name
PRESENT
None [30:24]
Bits
Name
31
PRESENT
4 : 0
SIZE5
Description
Presence of dummy cycles: '0': not present '1': present Default Value: 0
Number of dummy cycles (minus 1): "0": 1 cycles ... "31": 32 cycles. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1335
SMIF0_DEVICE0_WR_DATA_CTL
23.1.50 SMIF0_DEVICE0_WR_DATA_CTL
Address = 0x40420870 Write data control Address: 0x40420870 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
HW Access
None
R
Name
None [23:18]
WIDTH [17:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 17 : 16
Name WIDTH
Description
Width of transfer. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1336
Section G: Peripheral Group 6
This section encompasses the following chapters: Serial Communication Block (SCB) Registers chapter on page 1338
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1337
24 Serial Communication Block (SCB) Registers
This section discusses the Serial Communications Block (SCB) registers. It lists all the registers in mapping tables, in address order
24.1 Register Details
Register SCB0_CTRL SCB0_SPI_CTRL SCB0_SPI_STATUS SCB0_UART_CTRL SCB0_UART_TX_CTRL SCB0_UART_RX_CTRL SCB0_UART_RX_STATUS SCB0_UART_FLOW_CTRL SCB0_I2C_CTRL SCB0_I2C_STATUS SCB0_I2C_M_CMD SCB0_I2C_S_CMD SCB0_I2C_CFG SCB0_TX_CTRL SCB0_TX_FIFO_CTRL SCB0_TX_FIFO_STATUS SCB0_TX_FIFO_WR SCB0_RX_CTRL SCB0_RX_FIFO_CTRL SCB0_RX_FIFO_STATUS SCB0_RX_MATCH SCB0_RX_FIFO_RD SCB0_RX_FIFO_RD_SILENT
SCB0_EZ_DATA0
SCB0_INTR_CAUSE SCB0_INTR_M
Address 0x40610000 0x40610020 0x40610024 0x40610040 0x40610044 0x40610048 0x4061004C 0x40610050 0x40610060 0x40610064 0x40610068 0x4061006C 0x40610070 0x40610200 0x40610204 0x40610208 0x40610240 0x40610300 0x40610304 0x40610308 0x40610310 0x40610340 0x40610344
0x40610400
0x40610E00 0x40610F00
Description Generic control SPI control SPI status UART control UART transmitter control UART receiver control UART receiver status UART flow control I2C control I2C status I2C master command I2C slave command I2C configuration Transmitter control Transmitter FIFO control Transmitter FIFO status Transmitter FIFO write Receiver control Receiver FIFO control Receiver FIFO status Slave address and mask Receiver FIFO read Receiver FIFO read silent Memory buffer. This is the starting address of a register bank containing 256 registers (SCB0_EZ_DATA0 to SCB0_EZ_DATA255) Active clocked interrupt signal Master interrupt request
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1338
Serial Communication Block (SCB) Registers
Register SCB0_INTR_M_SET SCB0_INTR_M_MASK SCB0_INTR_M_MASKED SCB0_INTR_S SCB0_INTR_S_SET SCB0_INTR_S_MASK SCB0_INTR_S_MASKED SCB0_INTR_TX SCB0_INTR_TX_SET SCB0_INTR_TX_MASK SCB0_INTR_TX_MASKED SCB0_INTR_RX SCB0_INTR_RX_SET SCB0_INTR_RX_MASK SCB0_INTR_RX_MASKED SCB1_CTRL SCB1_SPI_CTRL SCB1_SPI_STATUS SCB1_UART_CTRL SCB1_UART_TX_CTRL SCB1_UART_RX_CTRL SCB1_UART_RX_STATUS SCB1_UART_FLOW_CTRL SCB1_I2C_CTRL SCB1_I2C_STATUS SCB1_I2C_M_CMD SCB1_I2C_S_CMD SCB1_I2C_CFG SCB1_TX_CTRL SCB1_TX_FIFO_CTRL SCB1_TX_FIFO_STATUS SCB1_TX_FIFO_WR SCB1_RX_CTRL SCB1_RX_FIFO_CTRL SCB1_RX_FIFO_STATUS SCB1_RX_MATCH SCB1_RX_FIFO_RD SCB1_RX_FIFO_RD_SILENT
SCB1_EZ_DATA0
SCB1_INTR_CAUSE SCB1_INTR_M SCB1_INTR_M_SET
Address 0x40610F04 0x40610F08 0x40610F0C 0x40610F40 0x40610F44 0x40610F48 0x40610F4C 0x40610F80 0x40610F84 0x40610F88 0x40610F8C 0x40610FC0 0x40610FC4 0x40610FC8 0x40610FCC 0x40620000 0x40620020 0x40620024 0x40620040 0x40620044 0x40620048 0x4062004C 0x40620050 0x40620060 0x40620064 0x40620068 0x4062006C 0x40620070 0x40620200 0x40620204 0x40620208 0x40620240 0x40620300 0x40620304 0x40620308 0x40620310 0x40620340 0x40620344
0x40620400
0x40620E00 0x40620F00 0x40620F04
Description Master interrupt set request Master interrupt mask Master interrupt masked request Slave interrupt request Slave interrupt set request Slave interrupt mask Slave interrupt masked request Transmitter interrupt request Transmitter interrupt set request Transmitter interrupt mask Transmitter interrupt masked request Receiver interrupt request Receiver interrupt set request Receiver interrupt mask Receiver interrupt masked request Generic control. See SCB0_CTRL for the details of bit fields. SPI control. See SCB0_SPI_CTRL for the details of bit fields. SPI status. See SCB0_SPI_STATUS for the details of bit fields. UART control. See SCB0_UART_CTRL for the details of bit fields. UART transmitter control. See SCB0_UART_TX_CTRL for the details of bit fields. UART receiver control. See SCB0_UART_RX_CTRL for the details of bit fields. UART receiver status. See SCB0_UART_RX_STATUS for the details of bit fields. UART flow control. See SCB0_UART_FLOW_CTRL for the details of bit fields. I2C control. See SCB0_I2C_CTRL for the details of bit fields. I2C status. See SCB0_I2C_STATUS for the details of bit fields. I2C master command. See SCB0_I2C_M_CMD for the details of bit fields. I2C slave command. See SCB0_I2C_S_CMD for the details of bit fields. I2C configuration. See SCB0_I2C_CFG for the details of bit fields. Transmitter control. See SCB0_TX_CTRL for the details of bit fields. Transmitter FIFO control. See SCB0_TX_FIFO_CTRL for the details of bit fields. Transmitter FIFO status. See SCB0_TX_FIFO_STATUS for the details of bit fields. Transmitter FIFO write. See SCB0_TX_FIFO_WR for the details of bit fields. Receiver control. See SCB0_RX_CTRL for the details of bit fields. Receiver FIFO control. See SCB0_RX_FIFO_CTRL for the details of bit fields. Receiver FIFO status. See SCB0_RX_FIFO_STATUS for the details of bit fields. Slave address and mask. See SCB0_RX_MATCH for the details of bit fields. Receiver FIFO read. See SCB0_RX_FIFO_RDfor the details of bit fields. Receiver FIFO read silent. See SCB0_RX_FIFO_RD_SILENT for the details of bit fields. Memory buffer. This is the starting address of a register bank containing 256 registers (SCB1_EZ_DATA0 to SCB1_EZ_DATA255). See SCB0_EZ_DATA0 for the details of bit fields. Active clocked interrupt signal. See SCB0_INTR_CAUSEfor the details of bit fields. Master interrupt request. See SCB0_INTR_Mfor the details of bit fields. Master interrupt set request. See SCB0_INTR_M_SETfor the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1339
Serial Communication Block (SCB) Registers
Register SCB1_INTR_M_MASK SCB1_INTR_M_MASKED SCB1_INTR_S SCB1_INTR_S_SET SCB1_INTR_S_MASK SCB1_INTR_S_MASKED SCB1_INTR_TX SCB1_INTR_TX_SET SCB1_INTR_TX_MASK SCB1_INTR_TX_MASKED SCB1_INTR_RX SCB1_INTR_RX_SET SCB1_INTR_RX_MASK SCB1_INTR_RX_MASKED SCB2_CTRL SCB2_SPI_CTRL SCB2_SPI_STATUS SCB2_UART_CTRL SCB2_UART_TX_CTRL SCB2_UART_RX_CTRL SCB2_UART_RX_STATUS SCB2_UART_FLOW_CTRL SCB2_I2C_CTRL SCB2_I2C_STATUS SCB2_I2C_M_CMD SCB2_I2C_S_CMD SCB2_I2C_CFG SCB2_TX_CTRL SCB2_TX_FIFO_CTRL SCB2_TX_FIFO_STATUS SCB2_TX_FIFO_WR SCB2_RX_CTRL SCB2_RX_FIFO_CTRL SCB2_RX_FIFO_STATUS SCB2_RX_MATCH SCB2_RX_FIFO_RD SCB2_RX_FIFO_RD_SILENT
SCB2_EZ_DATA0
SCB2_INTR_CAUSE SCB2_INTR_M SCB2_INTR_M_SET
Address 0x40620F08 0x40620F0C 0x40620F40 0x40620F44 0x40620F48 0x40620F4C 0x40620F80 0x40620F84 0x40620F88 0x40620F8C 0x40620FC0 0x40620FC4 0x40620FC8 0x40620FCC 0x40630000 0x40630020 0x40630024 0x40630040 0x40630044 0x40630048 0x4063004C 0x40630050 0x40630060 0x40630064 0x40630068 0x4063006C 0x40630070 0x40630200 0x40630204 0x40630208 0x40630240 0x40630300 0x40630304 0x40630308 0x40630310 0x40630340 0x40630344
0x40630400
0x40630E00 0x40630F00 0x40630F04
Description Master interrupt mask. See SCB0_INTR_M_MASKfor the details of bit fields. Master interrupt masked request. See SCB0_INTR_M_MASKEDfor the details of bit fields. Slave interrupt request. See SCB0_INTR_Sfor the details of bit fields. Slave interrupt set request. See SCB0_INTR_S_SETfor the details of bit fields. Slave interrupt mask. See SCB0_INTR_S_MASKfor the details of bit fields. Slave interrupt masked request. See SCB0_INTR_S_MASKEDfor the details of bit fields. Transmitter interrupt request. See SCB0_INTR_TXfor the details of bit fields. Transmitter interrupt set request. See SCB0_INTR_TX_SETfor the details of bit fields. Transmitter interrupt mask. See SCB0_INTR_TX_MASKfor the details of bit fields. Transmitter interrupt masked request. See SCB0_INTR_TX_MASKEDfor the details of bit fields. Receiver interrupt request. See SCB0_INTR_RXfor the details of bit fields. Receiver interrupt set request. See SCB0_INTR_RX_SETfor the details of bit fields. Receiver interrupt mask. See SCB0_INTR_RX_MASKfor the details of bit fields. Receiver interrupt masked request. See SCB0_INTR_RX_MASKEDfor the details of bit fields. Generic control. See SCB0_CTRL for the details of bit fields. SPI control. See SCB0_SPI_CTRL for the details of bit fields. SPI status. See SCB0_SPI_STATUS for the details of bit fields. UART control. See SCB0_UART_CTRL for the details of bit fields. UART transmitter control. See SCB0_UART_TX_CTRL for the details of bit fields. UART receiver control. See SCB0_UART_RX_CTRL for the details of bit fields. UART receiver status. See SCB0_UART_RX_STATUS for the details of bit fields. UART flow control. See SCB0_UART_FLOW_CTRL for the details of bit fields. I2C control. See SCB0_I2C_CTRL for the details of bit fields. I2C status. See SCB0_I2C_STATUS for the details of bit fields. I2C master command. See SCB0_I2C_M_CMD for the details of bit fields. I2C slave command. See SCB0_I2C_S_CMD for the details of bit fields. I2C configuration. See SCB0_I2C_CFG for the details of bit fields. Transmitter control. See SCB0_TX_CTRL for the details of bit fields. Transmitter FIFO control. See SCB0_TX_FIFO_CTRL for the details of bit fields. Transmitter FIFO status. See SCB0_TX_FIFO_STATUS for the details of bit fields. Transmitter FIFO write. See SCB0_TX_FIFO_WR for the details of bit fields. Receiver control. See SCB0_RX_CTRL for the details of bit fields. Receiver FIFO control. See SCB0_RX_FIFO_CTRL for the details of bit fields. Receiver FIFO status. See SCB0_RX_FIFO_STATUS for the details of bit fields. Slave address and mask. See SCB0_RX_MATCH for the details of bit fields. Receiver FIFO read. See SCB0_RX_FIFO_RDfor the details of bit fields. Receiver FIFO read silent. See SCB0_RX_FIFO_RD_SILENT for the details of bit fields. Memory buffer. This is the starting address of a register bank containing 256 registers(SCB2_EZ_DATA0 to SCB2_EZ_DATA255) . See SCB0_EZ_DATA0 for the details of bit fields. Active clocked interrupt signal. See SCB0_INTR_CAUSEfor the details of bit fields. Master interrupt request. See SCB0_INTR_Mfor the details of bit fields. Master interrupt set request. See SCB0_INTR_M_SETfor the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1340
Serial Communication Block (SCB) Registers
Register SCB2_INTR_M_MASK SCB2_INTR_M_MASKED SCB2_INTR_S SCB2_INTR_S_SET SCB2_INTR_S_MASK SCB2_INTR_S_MASKED SCB2_INTR_TX SCB2_INTR_TX_SET SCB2_INTR_TX_MASK SCB2_INTR_TX_MASKED SCB2_INTR_RX SCB2_INTR_RX_SET SCB2_INTR_RX_MASK SCB2_INTR_RX_MASKED SCB3_CTRL SCB3_SPI_CTRL SCB3_SPI_STATUS SCB3_UART_CTRL SCB3_UART_TX_CTRL SCB3_UART_RX_CTRL SCB3_UART_RX_STATUS SCB3_UART_FLOW_CTRL SCB3_I2C_CTRL SCB3_I2C_STATUS SCB3_I2C_M_CMD SCB3_I2C_S_CMD SCB3_I2C_CFG SCB3_TX_CTRL SCB3_TX_FIFO_CTRL SCB3_TX_FIFO_STATUS SCB3_TX_FIFO_WR SCB3_RX_CTRL SCB3_RX_FIFO_CTRL SCB3_RX_FIFO_STATUS SCB3_RX_MATCH SCB3_RX_FIFO_RD SCB3_RX_FIFO_RD_SILENT
SCB3_EZ_DATA0
SCB3_INTR_CAUSE SCB3_INTR_M SCB3_INTR_M_SET
Address 0x40630F08 0x40630F0C 0x40630F40 0x40630F44 0x40630F48 0x40630F4C 0x40630F80 0x40630F84 0x40630F88 0x40630F8C 0x40630FC0 0x40630FC4 0x40630FC8 0x40630FCC 0x40640000 0x40640020 0x40640024 0x40640040 0x40640044 0x40640048 0x4064004C 0x40640050 0x40640060 0x40640064 0x40640068 0x4064006C 0x40640070 0x40640200 0x40640204 0x40640208 0x40640240 0x40640300 0x40640304 0x40640308 0x40640310 0x40640340 0x40640344
0x40640400
0x40640E00 0x40640F00 0x40640F04
Description Master interrupt mask. See SCB0_INTR_M_MASKfor the details of bit fields. Master interrupt masked request. See SCB0_INTR_M_MASKEDfor the details of bit fields. Slave interrupt request. See SCB0_INTR_Sfor the details of bit fields. Slave interrupt set request. See SCB0_INTR_S_SETfor the details of bit fields. Slave interrupt mask. See SCB0_INTR_S_MASKfor the details of bit fields. Slave interrupt masked request. See SCB0_INTR_S_MASKEDfor the details of bit fields. Transmitter interrupt request. See SCB0_INTR_TXfor the details of bit fields. Transmitter interrupt set request. See SCB0_INTR_TX_SETfor the details of bit fields. Transmitter interrupt mask. See SCB0_INTR_TX_MASKfor the details of bit fields. Transmitter interrupt masked request. See SCB0_INTR_TX_MASKEDfor the details of bit fields. Receiver interrupt request. See SCB0_INTR_RXfor the details of bit fields. Receiver interrupt set request. See SCB0_INTR_RX_SETfor the details of bit fields. Receiver interrupt mask. See SCB0_INTR_RX_MASKfor the details of bit fields. Receiver interrupt masked request. See SCB0_INTR_RX_MASKEDfor the details of bit fields. Generic control. See SCB0_CTRL for the details of bit fields. SPI control. See SCB0_SPI_CTRL for the details of bit fields. SPI status. See SCB0_SPI_STATUS for the details of bit fields. UART control. See SCB0_UART_CTRL for the details of bit fields. UART transmitter control. See SCB0_UART_TX_CTRL for the details of bit fields. UART receiver control. See SCB0_UART_RX_CTRL for the details of bit fields. UART receiver status. See SCB0_UART_RX_STATUS for the details of bit fields. UART flow control. See SCB0_UART_FLOW_CTRL for the details of bit fields. I2C control. See SCB0_I2C_CTRL for the details of bit fields. I2C status. See SCB0_I2C_STATUS for the details of bit fields. I2C master command. See SCB0_I2C_M_CMD for the details of bit fields. I2C slave command. See SCB0_I2C_S_CMD for the details of bit fields. I2C configuration. See SCB0_I2C_CFG for the details of bit fields. Transmitter control. See SCB0_TX_CTRL for the details of bit fields. Transmitter FIFO control. See SCB0_TX_FIFO_CTRL for the details of bit fields. Transmitter FIFO status. See SCB0_TX_FIFO_STATUS for the details of bit fields. Transmitter FIFO write. See SCB0_TX_FIFO_WR for the details of bit fields. Receiver control. See SCB0_RX_CTRL for the details of bit fields. Receiver FIFO control. See SCB0_RX_FIFO_CTRL for the details of bit fields. Receiver FIFO status. See SCB0_RX_FIFO_STATUS for the details of bit fields. Slave address and mask. See SCB0_RX_MATCH for the details of bit fields. Receiver FIFO read. See SCB0_RX_FIFO_RDfor the details of bit fields. Receiver FIFO read silent. See SCB0_RX_FIFO_RD_SILENT for the details of bit fields. Memory buffer. This is the starting address of a register bank containing 256 registers(SCB3_EZ_DATA0 to SCB3_EZ_DATA255) . See SCB0_EZ_DATA0 for the details of bit fields. Active clocked interrupt signal. See SCB0_INTR_CAUSEfor the details of bit fields. Master interrupt request. See SCB0_INTR_Mfor the details of bit fields. Master interrupt set request. See SCB0_INTR_M_SETfor the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1341
Serial Communication Block (SCB) Registers
Register SCB3_INTR_M_MASK SCB3_INTR_M_MASKED SCB3_INTR_S SCB3_INTR_S_SET SCB3_INTR_S_MASK SCB3_INTR_S_MASKED SCB3_INTR_TX SCB3_INTR_TX_SET SCB3_INTR_TX_MASK SCB3_INTR_TX_MASKED SCB3_INTR_RX SCB3_INTR_RX_SET SCB3_INTR_RX_MASK SCB3_INTR_RX_MASKED SCB4_CTRL SCB4_SPI_CTRL SCB4_SPI_STATUS SCB4_UART_CTRL SCB4_UART_TX_CTRL SCB4_UART_RX_CTRL SCB4_UART_RX_STATUS SCB4_UART_FLOW_CTRL SCB4_I2C_CTRL SCB4_I2C_STATUS SCB4_I2C_M_CMD SCB4_I2C_S_CMD SCB4_I2C_CFG SCB4_TX_CTRL SCB4_TX_FIFO_CTRL SCB4_TX_FIFO_STATUS SCB4_TX_FIFO_WR SCB4_RX_CTRL SCB4_RX_FIFO_CTRL SCB4_RX_FIFO_STATUS SCB4_RX_MATCH SCB4_RX_FIFO_RD SCB4_RX_FIFO_RD_SILENT
SCB4_EZ_DATA0
SCB4_INTR_CAUSE SCB4_INTR_M SCB4_INTR_M_SET SCB4_INTR_M_MASK
Address 0x40640F08 0x40640F0C 0x40640F40 0x40640F44 0x40640F48 0x40640F4C 0x40640F80 0x40640F84 0x40640F88 0x40640F8C 0x40640FC0 0x40640FC4 0x40640FC8 0x40640FCC 0x40650000 0x40650020 0x40650024 0x40650040 0x40650044 0x40650048 0x4065004C 0x40650050 0x40650060 0x40650064 0x40650068 0x4065006C 0x40650070 0x40650200 0x40650204 0x40650208 0x40650240 0x40650300 0x40650304 0x40650308 0x40650310 0x40650340 0x40650344
0x40650400
0x40650E00 0x40650F00 0x40650F04 0x40650F08
Description Master interrupt mask. See SCB0_INTR_M_MASKfor the details of bit fields. Master interrupt masked request. See SCB0_INTR_M_MASKEDfor the details of bit fields. Slave interrupt request. See SCB0_INTR_Sfor the details of bit fields. Slave interrupt set request. See SCB0_INTR_S_SETfor the details of bit fields. Slave interrupt mask. See SCB0_INTR_S_MASKfor the details of bit fields. Slave interrupt masked request. See SCB0_INTR_S_MASKEDfor the details of bit fields. Transmitter interrupt request. See SCB0_INTR_TXfor the details of bit fields. Transmitter interrupt set request. See SCB0_INTR_TX_SETfor the details of bit fields. Transmitter interrupt mask. See SCB0_INTR_TX_MASKfor the details of bit fields. Transmitter interrupt masked request. See SCB0_INTR_TX_MASKEDfor the details of bit fields. Receiver interrupt request. See SCB0_INTR_RXfor the details of bit fields. Receiver interrupt set request. See SCB0_INTR_RX_SETfor the details of bit fields. Receiver interrupt mask. See SCB0_INTR_RX_MASKfor the details of bit fields. Receiver interrupt masked request. See SCB0_INTR_RX_MASKEDfor the details of bit fields. Generic control. See SCB0_CTRL for the details of bit fields. SPI control. See SCB0_SPI_CTRL for the details of bit fields. SPI status. See SCB0_SPI_STATUS for the details of bit fields. UART control. See SCB0_UART_CTRL for the details of bit fields. UART transmitter control. See SCB0_UART_TX_CTRL for the details of bit fields. UART receiver control. See SCB0_UART_RX_CTRL for the details of bit fields. UART receiver status. See SCB0_UART_RX_STATUS for the details of bit fields. UART flow control. See SCB0_UART_FLOW_CTRL for the details of bit fields. I2C control. See SCB0_I2C_CTRL for the details of bit fields. I2C status. See SCB0_I2C_STATUS for the details of bit fields. I2C master command. See SCB0_I2C_M_CMD for the details of bit fields. I2C slave command. See SCB0_I2C_S_CMD for the details of bit fields. I2C configuration. See SCB0_I2C_CFG for the details of bit fields. Transmitter control. See SCB0_TX_CTRL for the details of bit fields. Transmitter FIFO control. See SCB0_TX_FIFO_CTRL for the details of bit fields. Transmitter FIFO status. See SCB0_TX_FIFO_STATUS for the details of bit fields. Transmitter FIFO write. See SCB0_TX_FIFO_WR for the details of bit fields. Receiver control. See SCB0_RX_CTRL for the details of bit fields. Receiver FIFO control. See SCB0_RX_FIFO_CTRL for the details of bit fields. Receiver FIFO status. See SCB0_RX_FIFO_STATUS for the details of bit fields. Slave address and mask. See SCB0_RX_MATCH for the details of bit fields. Receiver FIFO read. See SCB0_RX_FIFO_RDfor the details of bit fields. Receiver FIFO read silent. See SCB0_RX_FIFO_RD_SILENT for the details of bit fields. Memory buffer. This is the starting address of a register bank containing 256 registers (SCB4_EZ_DATA1 to SCB4_EZ_DATA255) . See SCB0_EZ_DATA0 for the details of bit fields. Active clocked interrupt signal. See SCB0_INTR_CAUSEfor the details of bit fields. Master interrupt request. See SCB0_INTR_M for the details of bit fields. Master interrupt set request. See SCB0_INTR_M_SET for the details of bit fields. Master interrupt mask. See SCB0_INTR_M_MASK for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1342
Serial Communication Block (SCB) Registers
Register SCB4_INTR_M_MASKED SCB4_INTR_S SCB4_INTR_S_SET SCB4_INTR_S_MASK SCB4_INTR_S_MASKED SCB4_INTR_TX SCB4_INTR_TX_SET SCB4_INTR_TX_MASK SCB4_INTR_TX_MASKED SCB4_INTR_RX SCB4_INTR_RX_SET SCB4_INTR_RX_MASK SCB4_INTR_RX_MASKED SCB5_CTRL SCB5_SPI_CTRL SCB5_SPI_STATUS SCB5_UART_CTRL SCB5_UART_TX_CTRL SCB5_UART_RX_CTRL SCB5_UART_RX_STATUS SCB5_UART_FLOW_CTRL SCB5_I2C_CTRL SCB5_I2C_STATUS SCB5_I2C_M_CMD SCB5_I2C_S_CMD SCB5_I2C_CFG SCB5_TX_CTRL SCB5_TX_FIFO_CTRL SCB5_TX_FIFO_STATUS SCB5_TX_FIFO_WR SCB5_RX_CTRL SCB5_RX_FIFO_CTRL SCB5_RX_FIFO_STATUS SCB5_RX_MATCH SCB5_RX_FIFO_RD SCB5_RX_FIFO_RD_SILENT
SCB5_EZ_DATA0
SCB5_INTR_CAUSE SCB5_INTR_M SCB5_INTR_M_SET SCB5_INTR_M_MASK SCB5_INTR_M_MASKED
Address 0x40650F0C 0x40650F40 0x40650F44 0x40650F48 0x40650F4C 0x40650F80 0x40650F84 0x40650F88 0x40650F8C 0x40650FC0 0x40650FC4 0x40650FC8 0x40650FCC 0x40660000 0x40660020 0x40660024 0x40660040 0x40660044 0x40660048 0x4066004C 0x40660050 0x40660060 0x40660064 0x40660068 0x4066006C 0x40660070 0x40660200 0x40660204 0x40660208 0x40660240 0x40660300 0x40660304 0x40660308 0x40660310 0x40660340 0x40660344
0x40660400
0x40660E00 0x40660F00 0x40660F04 0x40660F08 0x40660F0C
Description Master interrupt masked request. See SCB0_INTR_M_MASKED for the details of bit fields. Slave interrupt request. See SCB0_INTR_S for the details of bit fields. Slave interrupt set request. See SCB0_INTR_S_SET for the details of bit fields. Slave interrupt mask. See SCB0_INTR_S_MASK for the details of bit fields. Slave interrupt masked request. See SCB0_INTR_S_MASKED for the details of bit fields. Transmitter interrupt request. See SCB0_INTR_TX for the details of bit fields. Transmitter interrupt set request. See SCB0_INTR_TX_SETfor the details of bit fields. Transmitter interrupt mask. See SCB0_INTR_TX_MASK for the details of bit fields. Transmitter interrupt masked request. See SCB0_INTR_TX_MASKED for the details of bit fields. Receiver interrupt request. See SCB0_INTR_RX for the details of bit fields. Receiver interrupt set request. See SCB0_INTR_RX_SETfor the details of bit fields. Receiver interrupt mask. See SCB0_INTR_RX_MASK for the details of bit fields. Receiver interrupt masked request. See SCB0_INTR_RX_MASKEDfor the details of bit fields. Generic control. See SCB0_CTRL for the details of bit fields. SPI control. See SCB0_SPI_CTRL for the details of bit fields. SPI status. See SCB0_SPI_STATUS for the details of bit fields. UART control. See SCB0_UART_CTRL for the details of bit fields. UART transmitter control. See SCB0_UART_TX_CTRL for the details of bit fields. UART receiver control. See SCB0_UART_RX_CTRL for the details of bit fields. UART receiver status. See SCB0_UART_RX_STATUS for the details of bit fields. UART flow control. See SCB0_UART_FLOW_CTRL for the details of bit fields. I2C control. See SCB0_I2C_CTRL for the details of bit fields. I2C status. See SCB0_I2C_STATUS for the details of bit fields. I2C master command. See SCB0_I2C_M_CMD for the details of bit fields. I2C slave command. See SCB0_I2C_S_CMD for the details of bit fields. I2C configuration. See SCB0_I2C_CFG for the details of bit fields. Transmitter control. See SCB0_TX_CTRL for the details of bit fields. Transmitter FIFO control. See SCB0_TX_FIFO_CTRL for the details of bit fields. Transmitter FIFO status. See SCB0_TX_FIFO_STATUS for the details of bit fields. Transmitter FIFO write. See SCB0_TX_FIFO_WR for the details of bit fields. Receiver control. See SCB0_RX_CTRL for the details of bit fields. Receiver FIFO control. See SCB0_RX_FIFO_CTRL for the details of bit fields. Receiver FIFO status. See SCB0_RX_FIFO_STATUS for the details of bit fields. Slave address and mask. See SCB0_RX_MATCH for the details of bit fields. Receiver FIFO read. See SCB0_RX_FIFO_RDfor the details of bit fields. Receiver FIFO read silent. See SCB0_RX_FIFO_RD_SILENT for the details of bit fields. Memory buffer. This is the starting address of a register bank containing 256 registers (SCB5_EZ_DATA0 to SCB5_EZ_DATA255) . See SCB0_EZ_DATA0 for the details of bit fields. Active clocked interrupt signal. See SCB0_INTR_CAUSEfor the details of bit fields. Master interrupt request. See SCB0_INTR_M for the details of bit fields. Master interrupt set request. See SCB0_INTR_M_SET for the details of bit fields. Master interrupt mask. See SCB0_INTR_M_MASK for the details of bit fields. Master interrupt masked request. See SCB0_INTR_M_MASKEDfor the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1343
Serial Communication Block (SCB) Registers
Register SCB5_INTR_S SCB5_INTR_S_SET SCB5_INTR_S_MASK SCB5_INTR_S_MASKED SCB5_INTR_TX SCB5_INTR_TX_SET SCB5_INTR_TX_MASK SCB5_INTR_TX_MASKED SCB5_INTR_RX SCB5_INTR_RX_SET SCB5_INTR_RX_MASK SCB5_INTR_RX_MASKED SCB6_CTRL SCB6_SPI_CTRL SCB6_SPI_STATUS SCB6_UART_CTRL SCB6_UART_TX_CTRL SCB6_UART_RX_CTRL SCB6_UART_RX_STATUS SCB6_UART_FLOW_CTRL SCB6_I2C_CTRL SCB6_I2C_STATUS SCB6_I2C_M_CMD SCB6_I2C_S_CMD SCB6_I2C_CFG SCB6_TX_CTRL SCB6_TX_FIFO_CTRL SCB6_TX_FIFO_STATUS SCB6_TX_FIFO_WR SCB6_RX_CTRL SCB6_RX_FIFO_CTRL SCB6_RX_FIFO_STATUS SCB6_RX_MATCH SCB6_RX_FIFO_RD SCB6_RX_FIFO_RD_SILENT
SCB6_EZ_DATA0
SCB6_INTR_CAUSE SCB6_INTR_M SCB6_INTR_M_SET SCB6_INTR_M_MASK SCB6_INTR_M_MASKED SCB6_INTR_S
Address 0x40660F40 0x40660F44 0x40660F48 0x40660F4C 0x40660F80 0x40660F84 0x40660F88 0x40660F8C 0x40660FC0 0x40660FC4 0x40660FC8 0x40660FCC 0x40670000 0x40670020 0x40670024 0x40670040 0x40670044 0x40670048 0x4067004C 0x40670050 0x40670060 0x40670064 0x40670068 0x4067006C 0x40670070 0x40670200 0x40670204 0x40670208 0x40670240 0x40670300 0x40670304 0x40670308 0x40670310 0x40670340 0x40670344
0x40670400
0x40670E00 0x40670F00 0x40670F04 0x40670F08 0x40670F0C 0x40670F40
Description Slave interrupt request. See SCB0_INTR_Sfor the details of bit fields. Slave interrupt set request. See SCB0_INTR_S_SET for the details of bit fields. Slave interrupt mask. See SCB0_INTR_S_MASK for the details of bit fields. Slave interrupt masked request. See SCB0_INTR_S_MASKED for the details of bit fields. Transmitter interrupt request. See SCB0_INTR_TX for the details of bit fields. Transmitter interrupt set request. See SCB0_INTR_TX_SET for the details of bit fields. Transmitter interrupt mask. See SCB0_INTR_TX_MASK for the details of bit fields. Transmitter interrupt masked request. See SCB0_INTR_TX_MASKED for the details of bit fields. Receiver interrupt request. See SCB0_INTR_RX for the details of bit fields. Receiver interrupt set request. See SCB0_INTR_RX_SET for the details of bit fields. Receiver interrupt mask. See SCB0_INTR_RX_MASK for the details of bit fields. Receiver interrupt masked request. See SCB0_INTR_RX_MASKED for the details of bit fields. Generic control. See SCB0_CTRL for the details of bit fields. SPI control. See SCB0_SPI_CTRL for the details of bit fields. SPI status. See SCB0_SPI_STATUS for the details of bit fields. UART control. See SCB0_UART_CTRL for the details of bit fields. UART transmitter control. See SCB0_UART_TX_CTRL for the details of bit fields. UART receiver control. See SCB0_UART_RX_CTRL for the details of bit fields. UART receiver status. See SCB0_UART_RX_STATUS for the details of bit fields. UART flow control. See SCB0_UART_FLOW_CTRL for the details of bit fields. I2C control. See SCB0_I2C_CTRL for the details of bit fields. I2C status. See SCB0_I2C_STATUS for the details of bit fields. I2C master command. See SCB0_I2C_M_CMD for the details of bit fields. I2C slave command. See SCB0_I2C_S_CMD for the details of bit fields. I2C configuration. See SCB0_I2C_CFG for the details of bit fields. Transmitter control. See SCB0_TX_CTRL for the details of bit fields. Transmitter FIFO control. See SCB0_TX_FIFO_CTRL for the details of bit fields. Transmitter FIFO status. See SCB0_TX_FIFO_STATUS for the details of bit fields. Transmitter FIFO write. See SCB0_TX_FIFO_WR for the details of bit fields. Receiver control. See SCB0_RX_CTRL for the details of bit fields. Receiver FIFO control. See SCB0_RX_FIFO_CTRL for the details of bit fields. Receiver FIFO status. See SCB0_RX_FIFO_STATUS for the details of bit fields. Slave address and mask. See SCB0_RX_MATCH for the details of bit fields. Receiver FIFO read. See SCB0_RX_FIFO_RDfor the details of bit fields. Receiver FIFO read silent. See SCB0_RX_FIFO_RD_SILENT for the details of bit fields. Memory buffer. This is the starting address of a register bank containing 256 registers (SCB6_EZ_DATA0 to SCB6_EZ_DATA255). See SCB0_EZ_DATA0 for the details of bit fields. Active clocked interrupt signal. See SCB0_INTR_CAUSE for the details of bit fields. Master interrupt request. See SCB0_INTR_M for the details of bit fields. Master interrupt set request. See SCB0_INTR_M_SET for the details of bit fields. Master interrupt mask. See SCB0_INTR_M_MASK for the details of bit fields. Master interrupt masked request. See SCB0_INTR_M_MASKED for the details of bit fields. Slave interrupt request. See SCB0_INTR_S for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1344
Serial Communication Block (SCB) Registers
Register SCB6_INTR_S_SET SCB6_INTR_S_MASK SCB6_INTR_S_MASKED SCB6_INTR_TX SCB6_INTR_TX_SET SCB6_INTR_TX_MASK SCB6_INTR_TX_MASKED SCB6_INTR_RX SCB6_INTR_RX_SET SCB6_INTR_RX_MASK SCB6_INTR_RX_MASKED SCB7_CTRL SCB7_SPI_CTRL SCB7_SPI_STATUS SCB7_UART_CTRL SCB7_UART_TX_CTRL SCB7_UART_RX_CTRL SCB7_UART_RX_STATUS SCB7_UART_FLOW_CTRL SCB7_I2C_CTRL SCB7_I2C_STATUS SCB7_I2C_M_CMD SCB7_I2C_S_CMD SCB7_I2C_CFG SCB7_TX_CTRL SCB7_TX_FIFO_CTRL SCB7_TX_FIFO_STATUS SCB7_TX_FIFO_WR SCB7_RX_CTRL SCB7_RX_FIFO_CTRL SCB7_RX_FIFO_STATUS SCB7_RX_MATCH SCB7_RX_FIFO_RD SCB7_RX_FIFO_RD_SILENT
SCB7_EZ_DATA0
SCB7_INTR_CAUSE SCB7_INTR_M SCB7_INTR_M_SET SCB7_INTR_M_MASK SCB7_INTR_M_MASKED SCB7_INTR_S SCB7_INTR_S_SET
Address 0x40670F44 0x40670F48 0x40670F4C 0x40670F80 0x40670F84 0x40670F88 0x40670F8C 0x40670FC0 0x40670FC4 0x40670FC8 0x40670FCC 0x40680000 0x40680020 0x40680024 0x40680040 0x40680044 0x40680048 0x4068004C 0x40680050 0x40680060 0x40680064 0x40680068 0x4068006C 0x40680070 0x40680200 0x40680204 0x40680208 0x40680240 0x40680300 0x40680304 0x40680308 0x40680310 0x40680340 0x40680344
0x40680400
0x40680E00 0x40680F00 0x40680F04 0x40680F08 0x40680F0C 0x40680F40 0x40680F44
Description Slave interrupt set request. See SCB0_INTR_S_SETfor the details of bit fields. Slave interrupt mask. See SCB0_INTR_S_MASK for the details of bit fields. Slave interrupt masked request. See SCB0_INTR_S_MASKED for the details of bit fields. Transmitter interrupt request. See SCB0_INTR_TX for the details of bit fields. Transmitter interrupt set request. See SCB0_INTR_TX_SET for the details of bit fields. Transmitter interrupt mask. See SCB0_INTR_TX_MASK for the details of bit fields. Transmitter interrupt masked request. See SCB0_INTR_TX_MASKED for the details of bit fields. Receiver interrupt request. See SCB0_INTR_RX for the details of bit fields. Receiver interrupt set request. See SCB0_INTR_RX_SET for the details of bit fields. Receiver interrupt mask. See SCB0_INTR_RX_MASK for the details of bit fields. Receiver interrupt masked request. See SCB0_INTR_RX_MASKED for the details of bit fields. Generic control. See SCB0_CTRL for the details of bit fields. SPI control. See SCB0_SPI_CTRL for the details of bit fields. SPI status. See SCB0_SPI_STATUS for the details of bit fields. UART control. See SCB0_UART_CTRL for the details of bit fields. UART transmitter control. See SCB0_UART_TX_CTRL for the details of bit fields. UART receiver control. See SCB0_UART_RX_CTRL for the details of bit fields. UART receiver status. See SCB0_UART_RX_STATUS for the details of bit fields. UART flow control. See SCB0_UART_FLOW_CTRL for the details of bit fields. I2C control. See SCB0_I2C_CTRL for the details of bit fields. I2C status. See SCB0_I2C_STATUS for the details of bit fields. I2C master command. See SCB0_I2C_M_CMD for the details of bit fields. I2C slave command. See SCB0_I2C_S_CMD for the details of bit fields. I2C configuration. See SCB0_I2C_CFG for the details of bit fields. Transmitter control. See SCB0_TX_CTRL for the details of bit fields. Transmitter FIFO control. See SCB0_TX_FIFO_CTRL for the details of bit fields. Transmitter FIFO status. See SCB0_TX_FIFO_STATUS for the details of bit fields. Transmitter FIFO write. See SCB0_TX_FIFO_WR for the details of bit fields. Receiver control. See SCB0_RX_CTRL for the details of bit fields. Receiver FIFO control. See SCB0_RX_FIFO_CTRL for the details of bit fields. Receiver FIFO status. See SCB0_RX_FIFO_STATUS for the details of bit fields. Slave address and mask. See SCB0_RX_MATCH for the details of bit fields. Receiver FIFO read. See SCB0_RX_FIFO_RDfor the details of bit fields. Receiver FIFO read silent. See SCB0_RX_FIFO_RD_SILENT for the details of bit fields. Memory buffer. This is the starting address of a register bank containing 256 registers (SCB7_EZ_DATA0 to SCB7_EZ_DATA255) .See SCB0_EZ_DATA0 for the details of bit fields. Active clocked interrupt signal. See SCB0_INTR_CAUSEfor the details of bit fields. Master interrupt request. See SCB0_INTR_M for the details of bit fields. Master interrupt set request. See SCB0_INTR_M_SET for the details of bit fields. Master interrupt mask. See SCB0_INTR_M_MASK for the details of bit fields. Master interrupt masked request. See SCB0_INTR_M_MASKED for the details of bit fields. Slave interrupt request. See SCB0_INTR_S for the details of bit fields. Slave interrupt set request. See SCB0_INTR_S_SET for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1345
Serial Communication Block (SCB) Registers
Register SCB7_INTR_S_MASK SCB7_INTR_S_MASKED SCB7_INTR_TX SCB7_INTR_TX_SET SCB7_INTR_TX_MASK SCB7_INTR_TX_MASKED SCB7_INTR_RX SCB7_INTR_RX_SET SCB7_INTR_RX_MASK SCB7_INTR_RX_MASKED SCB8_CTRL SCB8_STATUS SCB8_CMD_RESP_CTRL SCB8_CMD_RESP_STATUS SCB8_SPI_CTRL SCB8_SPI_STATUS SCB8_I2C_CTRL SCB8_I2C_STATUS SCB8_I2C_S_CMD SCB8_I2C_CFG SCB8_TX_CTRL SCB8_TX_FIFO_CTRL SCB8_TX_FIFO_STATUS SCB8_TX_FIFO_WR SCB8_RX_CTRL SCB8_RX_FIFO_CTRL SCB8_RX_FIFO_STATUS SCB8_RX_MATCH SCB8_RX_FIFO_RD SCB8_RX_FIFO_RD_SILENT
SCB8_EZ_DATA0
SCB8_INTR_CAUSE SCB8_INTR_I2C_EC SCB8_INTR_I2C_EC_MASK SCB8_INTR_I2C_EC_MASKED SCB8_INTR_SPI_EC SCB8_INTR_SPI_EC_MASK SCB8_INTR_SPI_EC_MASKED SCB8_INTR_S SCB8_INTR_S_SET SCB8_INTR_S_MASK SCB8_INTR_S_MASKED
Address 0x40680F48 0x40680F4C 0x40680F80 0x40680F84 0x40680F88 0x40680F8C 0x40680FC0 0x40680FC4 0x40680FC8 0x40680FCC 0x40690000 0x40690004 0x40690008 0x4069000C 0x40690020 0x40690024 0x40690060 0x40690064 0x4069006C 0x40690070 0x40690200 0x40690204 0x40690208 0x40690240 0x40690300 0x40690304 0x40690308 0x40690310 0x40690340 0x40690344
0x40690400
0x40690E00 0x40690E80 0x40690E88 0x40690E8C 0x40690EC0 0x40690EC8 0x40690ECC 0x40690F40 0x40690F44 0x40690F48 0x40690F4C
Description Slave interrupt mask. See SCB0_INTR_S_MASKfor the details of bit fields. Slave interrupt masked request. See SCB0_INTR_S_MASKEDfor the details of bit fields. Transmitter interrupt request. See SCB0_INTR_TX for the details of bit fields. Transmitter interrupt set request. See SCB0_INTR_TX_SETfor the details of bit fields. Transmitter interrupt mask. See SCB0_INTR_TX_MASK for the details of bit fields. Transmitter interrupt masked request. See SCB0_INTR_TX_MASKED for the details of bit fields. Receiver interrupt request. See SCB0_INTR_RX for the details of bit fields. Receiver interrupt set request. See SCB0_INTR_RX_SET for the details of bit fields. Receiver interrupt mask. See SCB0_INTR_RX_MASK for the details of bit fields. Receiver interrupt masked request. See SCB0_INTR_RX_MASKED for the details of bit fields. Generic control Generic status Command/response control Command/response status SPI control SPI status I2C control I2C status I2C slave command. See SCB0_I2C_S_CMD for the details of bit fields. I2C configuration. See SCB0_I2C_CFG for the details of bit fields. Transmitter control. See SCB0_TX_CTRL for the details of bit fields. Transmitter FIFO control. See SCB0_TX_FIFO_CTRL for the details of bit fields. Transmitter FIFO status. See SCB0_TX_FIFO_STATUS for the details of bit fields. Transmitter FIFO write. See SCB0_TX_FIFO_WR for the details of bit fields. Receiver control. See SCB0_RX_CTRL for the details of bit fields. Receiver FIFO control. See SCB0_RX_FIFO_CTRL for the details of bit fields. Receiver FIFO status. See SCB0_RX_FIFO_STATUS for the details of bit fields. Slave address and mask. See SCB0_RX_MATCH for the details of bit fields. Receiver FIFO read. See SCB0_RX_FIFO_RDfor the details of bit fields. Receiver FIFO read silent. See SCB0_RX_FIFO_RD_SILENT for the details of bit fields. Memory buffer. This is the starting address of a register bank containing 256 registers (SCB_EZ_DATA0 to SCB8_EZ_DATA255).See SCB0_EZ_DATA0 for the details of bit fields. Active clocked interrupt signal Externally clocked I2C interrupt request Externally clocked I2C interrupt mask Externally clocked I2C interrupt masked Externally clocked SPI interrupt request Externally clocked SPI interrupt mask Externally clocked SPI interrupt masked Slave interrupt request. See SCB0_INTR_Sfor the details of bit fields. Slave interrupt set request. See SCB0_INTR_S_SET for the details of bit fields. Slave interrupt mask. See SCB0_INTR_S_MASK for the details of bit fields. Slave interrupt masked request. See SCB0_INTR_S_MASKED for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1346
Serial Communication Block (SCB) Registers
Register SCB8_INTR_TX SCB8_INTR_TX_SET SCB8_INTR_TX_MASK SCB8_INTR_TX_MASKED SCB8_INTR_RX SCB8_INTR_RX_SET SCB8_INTR_RX_MASK SCB8_INTR_RX_MASKED
Address 0x40690F80 0x40690F84 0x40690F88 0x40690F8C 0x40690FC0 0x40690FC4 0x40690FC8 0x40690FCC
Transmitter interrupt request Transmitter interrupt set request Transmitter interrupt mask Transmitter interrupt masked request Receiver interrupt request Receiver interrupt set request Receiver interrupt mask Receiver interrupt masked request
Description
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1347
SCB0_CTRL
24.1.1 SCB0_CTRL
Address = 0x40610000 Generic control Address: 0x40610000 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:4]
Bits
15
SW Access
HW Access
Name
14
13
None
None
None [15:12]
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
RW
HW Access
R
Name
ENABLED
4
3
12
11
RW
R
BYTE_MODE
20
19
None
None
None [23:17]
28
27
None
None
None [30:26]
2
1
0
RW
R
OVS [3:0]
10
9
8
None
None
None [10:8]
18
17
16
RW
R
ADDR_ACCEPT
26
25
24
RW
R
MODE [25:24]
Bits
Name
31
ENABLED
25 : 24
MODE
Description
0': Block Disabled '1': Block Enabled The proper order in which to initialize the SCB is as follows: - Program protocol specific information using SPI_CTRL, UART_CTRL (and UART_TX_CTRL and UART_RX_CTRL) or I2C_CTRL. This includes selection of a submode, master/slave functionality and transmitter/receiver functionality when applicable. - Program generic transmitter (TX_CTRL) and receiver (RX_CTRL) information. This includes enabling of the transmitter and receiver functionality. - Program transmitter FIFO (TX_FIFO_CTRL) and receiver FIFO (RX_FIFO_CTRL) information. - Program CTRL to enable SCB, select the specific operation mode and oversampling factor. When the SCB is enabled, no control information should be changed. Changes must be made AFTER disabling the SCB, e.g. to modify the operation mode (from I2C to SPI) or to go from externally to internally clocked. The change takes effect after the SCB is re-enabled. Note that disabling the SCB will cause re-initialization of the design and associated state is lost (e.g. FIFO content). Default Value: 0
Mode of operation (3: Reserved) Default Value: 3
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1348
SCB0_CTRL
24.1.1
16 11
SCB0_CTRL (continued)
ADDR_ACCEPT BYTE_MODE
0x0: I2C : Inter-Integrated Circuits (I2C) mode.
0x1: SPI : Serial Peripheral Interface (SPI) mode.
0x2: UART : Universal Asynchronous Receiver/Transmitter (UART) mode.
Determines whether a received matching address is accepted in the RX FIFO:. '0': Matching address does not go in RX FIFO '1': Match address does go in RX FIFO In I2C mode, this field is used to allow the slave to put the received slave address or general call address in the RX FIFO. Note that a received matching address is put in the RX FIFO when this bit is '1' for both I2C read and write transfers. In multi-processor UART receiver mode, this field is used to allow the receiver to put the received address in the RX FIFO. Note: non-matching addresses are never put in the RX FIFO. In SPI mode this field must be '0' Default Value: 0
Determines the number of bits per FIFO data element: '0': 16-bit FIFO data elements. '1': 8-bit FIFO data elements. This mode doubles the amount of FIFO entries, but TX_CTRL.DATA_WIDTH and RX_CTRL.DATA_WIDTH are restricted to [0, 7]. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1349
SCB0_CTRL
24.1.1
3 : 0
SCB0_CTRL (continued)
OVS
Serial interface bit period oversampling factor expressed in clk_scb cycles. clk_scb is the peripheral clock divider connected to the SCB. Used for SPI Master and UART functionality. This field is NOT used in externally clocked mode. This filed is NOT used for SPI slave or I2C mode. OVS + 1 clk_scb cycles constitute a single serial interface clock/bit cycle. If OVS is odd, the oversampling factor is even and the low and high phase of the interface clock period are the same. If OVS is even, the oversampling factor is odd and the low and high phase can differ by 1 SCB clock period. In SPI master mode, the valid range is [3, 15]. The frequency of the SPI Clock is (frequency of clk_scb) / (OVS + 1). For example, is clk_scb is 50 MHz and OVS is 9, then the frequency of SPI Clock is 50 MHz / (9+1) = 5 MHz. If the MISO signal is not used for SPI master the valid range changes to [1,15] In SPI slave mode, the OVS field is NOT used. Refer to the architecture TRM for information on how to configure clk_scb for SPI Slave. Generally, it is recommended that clk_scb be as fast as possible for the slave. In UART standard sub mode (including LIN and Smartcard), the valid range is [7, 15]. In UART IrDA sub mode this field indirectly specifies the oversampling. The oversampling determines the interface clock/bit cycle and the width of the pulse. For normal transmission mode, the pulse is roughly 3/16 of the bit period (for all bit rates). There is only one valid OVS value: - 0: 16 times oversampling. clk_scb frequency = 16*115.2 KHz for 115.2 Kbps. clk_scb frequency = 16*57.6 KHz for 57.6 Kbps. clk_scb frequency = 16*38.4 KHz for 38.4 Kbps. clk_scb frequency = 16*19.2 KHz for 19.2 Kbps. clk_scb frequency = 16*9.6 KHz for 9.6 Kbps. clk_scb frequency = 16*2.4 KHz for 2.4 Kbps. clk_scb frequency = 16*1.2 KHz for 1.2 Kbps. - all other values are not used in normal mode. RX_CTRL.MEDIAN must be set to '1' for IrDA receiver functionality. UART IrDA RX Low power mode, OVS field values (with the required clk_scb frequency): - 0: 16 times oversampling. clk_scb frequency = 16*115.2 KHz for 115.2 Kbps. - 1: 32 times oversampling. clk_scb frequency = 32*57.6 KHz for 57.6 Kbps. - 2: 48 times oversampling. clk_scb frequency = 48*38.4 KHz for 38.4 Kbps. - 3: 96 times oversampling. clk_scb frequency = 96*19.2 KHz for 19.2 Kbps. - 4: 192 times oversampling. clk_scb frequency = 192*9.6 KHz for 9.6 Kbps. - 5: 768 times oversampling. clk_scb frequency = 768*2.4 KHz for 2.4 Kbps. - 6: 1536 times oversampling. clk_scb frequency = 1536*1.2 KHz for 1.2 Kbps. - all other values are not used in low power mode. In low power transmission mode, this pulse is potentially smaller (down to 1.62 us typical and 1.41 us minimal) than 3/16 of the bit period (for < 115.2 Kbps bitrates). Pulse widths greater or equal than two SCB clock cycles are guaranteed to be detected by the receiver. Pulse widths less than two SCB clock cycles and greater or equal than one SCB clock cycle may be detected by the receiver. Pulse widths less than one SCB clock cycle will not be detected by the receiver. Default Value: 15
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1350
SCB0_SPI_CTRL
24.1.2 SCB0_SPI_CTRL
Address = 0x40610020 SPI control Address: 0x40610020 Retention: Retained
Bits SW Access HW Access
Name
7
6
None
None
None [7:6]
5
RW
R
SCLK_CONTINU-
OUS
4 RW R
LATE_MISO _SAMPLE
3 RW R
CPOL
2 RW R
CPHA
1
RW
R
SELECT_PRE-
CEDE
0
RW
R
SSEL_CONTINU-
OUS
Bits
15
SW Access
HW Access
Name
14
13
None
None
None [15:12]
12
11
10
9
8
RW
RW
RW
RW
R
R
R
R
SSEL_PO- SSEL_PO- SSEL_PO- SSEL_PO-
LARITY3
LARITY2
LARITY1
LARITY0
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
HW Access
None
R
Name
None [23:17]
LOOPBACK
Bits SW Access HW Access
Name
31
RW
R
MASTER_MODE
30
29
28
None
None
None [30:28]
27
26
RW
R
SSEL [27:26]
25
24
RW
R
MODE [25:24]
Bits
Name
31
MASTER_MODE
27 : 26
SSEL
25 : 24
MODE
Description
Master ('1') or slave ('0') mode. In master mode, transmission will commence on availability of data frames in the TX FIFO. In slave mode, when selected and there is no data frame in the TX FIFO, the slave will transmit all '1's. In both master and slave modes, received data frames will be lost if the RX FIFO is full. Default Value: 0
Selects one of the four incoming/outgoing SPI slave select signals: - 0: Slave 0, SSEL[0]. - 1: Slave 1, SSEL[1]. - 2: Slave 2, SSEL[2]. - 3: Slave 3, SSEL[3]. The SCB should be disabled when changes are made to this field. Default Value: 0
Submode of SPI operation (3: Reserved). Default Value: 3
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-18270 Rev. *F
1351
SCB0_SPI_CTRL
24.1.2
SCB0_SPI_CTRL (continued)
0x0: SPI_MOTOROLA : SPI Motorola submode.
0x1: SPI_TI : SPI Texas Instruments submode.
0x2: SPI_NS : SPI National Semiconducturs submode.
16
LOOPBACK
Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode. '0': No local loopback '1': the SPI master MISO line is connected to the SPI master MOSI line. In other words, in loopback mode the SPI master receives on MISO what it transmits on MOSI. Default Value: 0
11
SSEL_POLARITY3
Slave select polarity.
Default Value: 0
10
SSEL_POLARITY2
Slave select polarity.
Default Value: 0
9
SSEL_POLARITY1
Slave select polarity.
Default Value: 0
8
SSEL_POLARITY0
Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal 0 (mas-
ter mode) and to the incoming SPI slave select signal (slave mode). For Motorola and National
Semiconductors submodes:
'0': slave select is low/'0' active.
'1': slave select is high/'1' active.
For Texas Instruments submode:
'0': high/'1' active precede/coincide pulse.
'1': low/'0' active precede/coincide pulse.
Default Value: 0
5
SCLK_CONTINUOUS
Only applicable in master mode.
'0': SCLK is generated, when the SPI master is enabled and data is transmitted.
'1': SCLK is generated, when the SPI master is enabled. This mode is useful for slave devices
that use SCLK for functional operation other than just SPI functionality.
Default Value: 0
4
LATE_MISO_SAMPLE
Changes the SCLK edge on which MISO is captured. Only used in master mode.
When '0', the default applies (
for Motorola as determined by CPOL and CPHA,
for Texas Instruments on the falling edge of SCLK and
for National Semiconductors on the rising edge of SCLK).
When '1', the alternate clock edge is used (which comes half a SPI SCLK period later). Late sam-
pling addresses the round trip delay associated with transmitting SCLK from the master to the
slave and transmitting MISO from the slave to the master.
Default Value: 0
3
CPOL
Indicates the clock polarity. This field, together with the CPHA field, indicates when MOSI data is driven and MISO data is captured: - CPOL is 0: SCLK is 0 when not transmitting data. - CPOL is 1: SCLK is 1 when not transmitting data. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1352
SCB0_SPI_CTRL
24.1.2
2
1 0
SCB0_SPI_CTRL (continued)
CPHA
SELECT_PRECEDE SSEL_CONTINUOUS
Indicates the clock phase. This field, together with the CPOL field, indicates when MOSI data is driven and MISO data is captured: - Motorola mode 0. CPOL is 0, CPHA is 0: MOSI is driven on a falling edge of SCLK. MISO is captured on a rising edge of SCLK. - Motorola mode 1. CPOL is 0, CPHA is 1: MOSI is driven on a rising edge of SCLK. MISO is captured on a falling edge of SCLK. - Motorola mode 2. CPOL is 1, CPHA is 0: MOSI is driven on a rising edge of SCLK. MISO is captured on a falling edge of SCLK. - Motorola mode 3. CPOL is 1, CPHA is 1: MOSI is driven on a falling edge of SCLK. MISO is captured on a rising edge of SCLK. In SPI Motorola submode, all four CPOL/CPHA modes are valid. in SPI NS submode, only CPOL=0 CPHA=0 mode is valid. in SPI TI submode, only CPOL=0 CPHA=1 mode is valid. Default Value: 0
Only used in SPI Texas Instruments' submode. When '1', the data frame start indication is a pulse on the Slave SELECT line that precedes the transfer of the first data frame bit. When '0', the data frame start indication is a pulse on the Slave SELECT line that coincides with the transfer of the first data frame bit. Default Value: 0
Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode, both continuous and non-continuous SPI data transfers are supported independent of this field. When continuous transfers are enabled indiviual data transfers are NOT seperated by slave select deselection as long as there is data in the TX FIFO. If the TX FIFO becomes empty then the slave select will be deselected. When continuous transfers are not enabled individual data frame transfers are always seperated by slave select deselection: independent of the availability of TX FIFO data frames. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1353
SCB0_SPI_STATUS
24.1.3 SCB0_SPI_STATUS
Address = 0x40610024 SPI status Address: 0x40610024 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
R
HW Access
None
W
Name
None [7:1]
BUS_BUSY
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
BUS_BUSY
Description
SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes, the busy bit is '1', when the slave selection is activated. For TI submode, the busy bit is '1' from the time the preceding/coinciding slave select is activated for the first transmitted data frame, till the last MOSI/MISO bit of the last data frame is transmitted. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1354
SCB0_UART_CTRL
24.1.4 SCB0_UART_CTRL
Address = 0x40610040 UART control Address: 0x40610040 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
HW Access
None
R
Name
None [23:17]
LOOPBACK
Bits
31
30
29
28
27
26
25
24
SW Access
None
RW
HW Access
None
R
Name
None [31:26]
MODE [25:24]
Bits 25 : 24
Name MODE
16
LOOPBACK
Description
Submode of UART operation (3: Reserved) Default Value: 3
0x0: UART_STD : Standard UART submode.
0x1: UART_SMARTCARD : SmartCard (ISO7816) submode. Support for negative acknowledgement (NACK) on the receiver side and retransmission on the transmitter side.
0x2: UART_IRDA : Infrared Data Association (IrDA) submode. Return to Zero modulation scheme.
Local loopback control (does NOT affect the information on the pins). 0: Loopback is not enabled 1: UART_TX is connected to UART_RX. UART_RTS is connected to UART_CTS. This allows a SCB UART transmitter to communicate with its receiver counterpart. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1355
SCB0_UART_TX_CTRL
24.1.5 SCB0_UART_TX_CTRL
Address = 0x40610044 UART transmitter control Address: 0x40610044 Retention: Retained
Bits SW Access HW Access
Name
7
6
None
None
None [7:6]
5
RW
R
PARITY_ENABLED
Bits
15
14
13
SW Access
HW Access
Name
4 RW R
PARITY
12 None None
None [15:9]
3 None None
None
11
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
0
RW
R
STOP_BITS [2:0]
10
9
8
RW
R
RETRY_ON_N
ACK
18
17
16
26
25
24
Bits
Name
8
RETRY_ON_NACK
5
PARITY_ENABLED
4
PARITY
2 : 0
STOP_BITS
Description
When '1', a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode. Default Value: 0
Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode, parity generation is always enabled through hardware. In IrDA submode, parity generation is always disabled through hardware Default Value: 0
Parity bit. When '0', the transmitter generates an even parity. When '1', the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes. Default Value: 0
Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of haf bit periods. Valid range is [1, 7]; i.e. a stop period should last at least one bit period. Default Value: 2
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1356
SCB0_UART_RX_CTRL
24.1.6 SCB0_UART_RX_CTRL
Address = 0x40610048 UART receiver control Address: 0x40610048 Retention: Retained
Bits SW Access HW Access
Name
7 None None
None
6 RW R
POLARITY
5
RW
R
PARITY_ENABLED
4 RW R
PARITY
Bits SW Access HW Access
Name
15
14
None
None
None [15:14]
13
12
RW
RW
R
R
SKIP_STAR T
LIN_MODE
3 None None
None
11 None None
None
Bits
23
SW Access
HW Access
Name
Bits
31
SW Access
HW Access
Name
22
21
None
None
None [23:20]
30
29
20
19
28
27
None
None
None [31:24]
2
1
0
RW
R
STOP_BITS [2:0]
10 RW R
MP_MODE
9
8
RW
RW
R
R
DROP_ON_ DROP_ON_
FRAME_ER
PARI-
ROR
TY_ERROR
18
17
16
RW
R
BREAK_WIDTH [19:16]
26
25
24
Bits 19 : 16
Name BREAK_WIDTH
Description
Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ("break field" detection). Once, the break is detected, the INTR_RX.BREAK_DETECT bit is set to '1'. Note for LIN the break detection precedes baud rate detection, which is used to synchronize/refine the receiver clock to the transmitter clock. As a result, break detection operates with an unsynchronized/unrefined receiver clock. Therefore, the receiver's definition of a bit period is imprecise and the setting of this field should take this imprecision into account. The LIN standard also accounts for this imprecision: a LIN start bit followed by 8 data bits allows for up to 9 consecutive '0' bit periods during regular transmission, whereas the LIN break detection should be at least 13 consecutive '0' bit periods. This provides for a margin of 4 bit periods. Therefore, the default value of this field is set to 10, representing a minimal break field with of 10+1 = 11 bit periods; a value in between the 9 consecutive bit periods of a regular transmission and the 13 consecutive bit periods of a break field. This provides for slight imprecisions of the receiver clock wrt. the transmitter clock. There should not be a need to program this field to any value other than its default value. Default Value: 10
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1357
SCB0_UART_RX_CTRL
24.1.6
13
12
10 9 8 6 5 4
SCB0_UART_RX_CTRL (continued)
SKIP_START
LIN_MODE
MP_MODE DROP_ON_FRAME_ERROR DROP_ON_PARITY_ERROR POLARITY PARITY_ENABLED PARITY
Only applicable in standard UART submode. When '1', the receiver skips start bit detection for the first received data frame. Instead, it synchronizes on the first received data frame bit, which should be a '1'. This functionality is intended for wake up from DeepSleep when receiving a data frame. The transition from idle ('1') to START ('0') on the RX line is used to wake up the CPU. The transition detection (and the associated wake up functionality) is performed by the GPIO. The woken up CPU will enable the SCB's UART receiver functionality. Once enabled, it is assumed that the START bit is ongoing (the CPU wakeup and SCB enable time should be less than the START bit period). The SCB will then synchronize to a '0' to '1' transition, which indicates the first data frame bit is received (first data frame bit should be '1'). After synchronization to the first data frame bit, the SCB will resume normal UART functionality: subsequent data frames will be synchronized on the receipt of a START bit. Default Value: 0
Only applicable in standard UART submode. When '1', the receiver performs break detection and baud rate detection on the incoming data. First, break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies the minum required amount of bit periods. Successful break detection sets the INTR_RX.BREAK_DETECT interrupt cause to '1'. Second, baud rate detection counts the amount of peripheral clock periods that are use to receive the synchronization byte (0x55; least significant bit first). The count is available through UART_RX_STATUS.BR_COUNTER. Successful baud rate detection sets the INTR_RX.BAUD_DETECT interrupt cause to '1' (BR_COUNTER is reliable). This functionality is used to synchronize/refine the receiver clock to the transmitter clock. The receiver software can use the BR_COUNTER value to set the right clk_scb to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte. Default Value: 0
Multi-processor mode. When '1', multi-processor mode is enabled. In this mode, RX_CTRL.DATA_WIDTH must be 9 bits. In multi-processor mode, the 9th received bit of a data frame seperates addresses (bit is '1') from data (bit is '0'). A received address is matched with RX_MATCH.DATA and RX_MATCH.MASK. In the case of a match, subsequent received data is sent to the RX FIFO. In the case of NO match, subsequent received data is dropped. Default Value: 0
Behaviour when an error is detected in a start or stop period. When '0', received data is sent to the RX FIFO. When '1', received data is dropped and lost. Default Value: 0
Behavior when a parity check fails. When '0', received data is send to the RX FIFO. When '1', received data is dropped and lost. Only applicable in standard UART and SmartCard submodes (negatively acknowledged SmartCard data frames may be dropped with this field). Default Value: 0
Inverts incoming RX line signal "uart_rx_in". Inversion is after local loopback. This functionality only works for IrDA receiver functionality. Default Value: 0
Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode, parity checking is always enabled through hardware. In IrDA submode, parity checking is always disabled through hardware. Default Value: 0
Parity bit. When '0', the receiver expects an even parity. When '1', the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1358
SCB0_UART_RX_CTRL
24.1.6
2 : 0
SCB0_UART_RX_CTRL (continued)
STOP_BITS
Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of haf bit periods. Valid range is [1, 7]; i.e. a stop period should last at least one bit period. If STOP_BITS is '1', stop bits error detection is NOT performed. If STOP_BITS is in [2, 7], stop bits error detection is performed and the associated interrupt cause INTR_RX.FRAME_ERROR is set to '1' if an error is detected. In other words, the receiver supports data frames with a 1 bit period stop bit sequence, but requires at least 1.5 bit period stop bit sequences to detect errors. Note that in case of a stop bits error, the successive data frames may get lost as the receiver needs to resynchronize its start bit detection. The amount of lost data frames depends on both the amount of stop bits, the idle time between data frames and the data frame value. Default Value: 2
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1359
SCB0_UART_RX_STATUS
24.1.7 SCB0_UART_RX_STATUS
Address = 0x4061004C UART receiver status Address: 0x4061004C Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
BR_COUNTER [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
R
HW Access
None
W
Name
None [15:12]
BR_COUNTER [11:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 11 : 0
Name BR_COUNTER
Description
For LIN: Amount of clk_scb periods that constitute the transmission of a 0x55 data frame (sent least signficant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of clk_scb periods that constitute a bit period. This field has valid data when INTR_RX.BAUD_DETECT is set to '1'. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1360
SCB0_UART_FLOW_CTRL
24.1.8 SCB0_UART_FLOW_CTRL
Address = 0x40610050 UART flow control Address: 0x40610050 Retention: Retained
Bits
7
6
5
4
3
2
SW Access
None
RW
HW Access
None
R
Name
None
TRIGGER_LEVEL [6:0]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:17]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:26]
1
0
9
8
17
25 RW R CTS_ENABLED
16 RW R RTS_POLARITY
24 RW R CTS_POLARITY
Bits
Name
25
CTS_ENABLED
24
CTS_POLARITY
Description
Enable use of CTS input signal by the UART transmitter: '0': Disabled. The UART transmitter ignores the CTS input signal and transmits when a data frame is available for transmission in the TX FIFO or the TX shift register. '1': Enabled. The UART transmitter uses CTS input signal to qualify the transmission of data. It transmits when CTS input signal is active and a data frame is available for transmission in the TX FIFO or the TX shift register. If UART_CTRL.LOOPBACK is '1', the CTS input signal is driven by the RTS output signal locally in SCB (both signals are subjected to signal polarity changes are indicated by RTS_POLARITY and CTS_POLARITY). Default Value: 0
Polarity of the CTS input signal '0': CTS is active low ; '1': CTS is active high; Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1361
SCB0_UART_FLOW_CTRL
24.1.8
16
6 : 0
SCB0_UART_FLOW_CTRL (continued)
RTS_POLARITY TRIGGER_LEVEL
Polarity of the RTS output signal: '0': RTS is active low; '1': RTS is active high; During SCB reset (Hibernate system power mode), RTS output signal is '1'. This represents an inactive state assuming an active low polarity. Default Value: 0
Trigger level. When the receiver FIFO has less entries than the amount of this field, a Ready To Send (RTS) output signal is activated. By setting this field to "0", flow control is disabled Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1362
SCB0_I2C_CTRL
24.1.9 SCB0_I2C_CTRL
Address = 0x40610060 I2C control Address: 0x40610060 Retention: Retained
Bits SW Access HW Access
Name
7
6
5
4
RW
R
LOW_PHASE_OVS [7:4]
3
2
1
0
RW
R
HIGH_PHASE_OVS [3:0]
Bits SW Access HW Access
Name
15
14
13
12
11
RW
RW
RW
RW
RW
R
R
R
R
R
S_NOT_RE ADY_-
DATA_NAC K
S_NOT_RE ADY_ADDR_NACK
S_READY_ DATA_ACK
S_READY_ ADDR_ACK
S_GENERAL_IGNOR
E
10 None None
None
9
8
RW
RW
R
R
M_NOT_RE ADY_-
DATA_NAC K
M_READY_ DATA_ACK
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
HW Access
None
R
Name
None [23:17]
LOOPBACK
Bits
31
30
29
28
27
26
25
24
SW Access
RW
RW
None
HW Access
R
R
None
Name
MASTER_MODE
SLAVE_MODE
None [29:24]
Bits
Name
31
MASTER_MODE
30
SLAVE_MODE
16
LOOPBACK
Description
Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the SCB to address itself. Default Value: 0
Slave mode enabled ('1') or not ('0'). Default Value: 0
Local loopback control (does NOT affect the information on the pins). Only applicable in master/ slave mode. When '0', no loopback When '1', loopback is enabled internally in the peripheral, and as a result unaffected by other I2C devices. This allows a SCB I2C peripheral to address itself. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1363
SCB0_I2C_CTRL
24.1.9
15 14
13 12 11 9 8 7 : 4 3 : 0
SCB0_I2C_CTRL (continued)
S_NOT_READY_DATA_NACK S_NOT_READY_ADDR_NACK
S_READY_DATA_ACK S_READY_ADDR_ACK S_GENERAL_IGNORE
M_NOT_READY_DATA_NACK M_READY_DATA_ACK LOW_PHASE_OVS
HIGH_PHASE_OVS
Only used for FIFO mode, NOT EZ or CMD_RESP mode. Functionality is as follows: - 1: a received data element byte the slave is immediately NACK'd when the receiver FIFO is full. - 0: clock stretching is performed (till the receiver FIFO is no longer full). Default Value: 1
Only used for FIFO mode, NOT EZ or CMD_RESP mode. Functionality is as follows: - 1: In Active/Sleep mode a received (matching) slave address is immediately NACK'd when the RX FIFO is full In DeepSleep power mode when EC_AM = '1' and EC_OP = '0' clk_scb is not avaliable, so the incoming address will be NACK'd until the clock is avaliable. Once clk_scb is avaliable the address ACK will follow S_READY_ADDR_ACK - 0: in Active/Sleep mode clock stretching is performed when the RX FIFO is full, the strech is released when the RX FIFO is no longer full. In DeepSleep power mode when EC_AM = '1' and EC_OP = '0' clk_scb is not avaliable, so the clocked will be streched on an incoming address until clk_scb is avaliable. After clk_scb is avalaible the address ACK will follow S_READY_ADDR_ACK Default Value: 1
When '1', a received data element by the slave is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode, this field should be set to '1'. When '0' the data must be ACK/NACK'd by the CPU using I2C_S_CMD.S_ACK or I2C_S_CMD.S_NACK Default Value: 1
When '1', a received (matching) slave address is immediately ACK'd when the RX FIFO is not full. In EZ and CMD_RESP mode, this field should be set to '1'. When '0' the address must be ACK/NACK'd by the CPU using I2C_S_CMD.S_ACK or I2C_S_CMD.S_NACK Default Value: 1
When '1', a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure. When '0' the general call address is accepted and follows S_READY_ADDR_ACK and S_NOT_READY_ADDR_NACK Default Value: 1
When '1', a received data element by the master is immediately NACK'd when the RX FIFO is full. When '0', clock stretching is used instead (till the RX FIFO is no longer full). Default Value: 1
When '1', a received data element by the master is immediately ACK'd when the RX FIFO is not full. When '0' the CPU is responsible for ACK/NACKing the received data frame using I2C_M_CMD.M_ACK or I2C_M_CMD.M_NACK Default Value: 1
Serial I2C interface low phase oversampling factor. (LOW_PHASE_OVS + 1) * clk_scb constitutes the low phase of a bit period. The valid range is [7, 15] with input signal median filtering and [6, 15] without input signal median filtering. The field is only used in master mode. In slave mode, the field is NOT used. See architecture TRM for information on slave data rate requirments. Default Value: 8
Serial I2C interface high phase oversampling factor. (HIGH_PHASE_OVS + 1) * clk_scb constitutes the high phase of a bit period. The valid range is [5, 15] with input signal median filtering and [4, 15] without input signal median filtering. The field is only used in master mode. In slave mode, the field is NOT used. See architecture TRM for information on slave data rate requirments. Default Value: 8
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1364
SCB0_I2C_STATUS
24.1.10 SCB0_I2C_STATUS
Address = 0x40610064 I2C status Address: 0x40610064 Retention: Not Retained
Bits SW Access HW Access
Name
7
6
None
None
None [7:6]
5 R W M_READ
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4
3
R
W
S_READ
12
11
None
None
None [15:8]
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
2 None None None [3:1]
10
18
26
1
0
R
W
BUS_BUSY
9
8
17
16
25
24
Bits
Name
5
M_READ
4
S_READ
0
BUS_BUSY
Description
I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/ idle or transmitting START, REPEATED START, STOP or an address, this field is '0''. Default Value: 0
I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START, REPEATED START, STOP or an address, this field is '0''. Default Value: 0
I2C bus is busy. The bus is considered busy ('1'), from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0'), from the time a STOP is detected. If the SCB is disabled, BUS_BUSY is '0'. After enabling the SCB, it takes time for the BUS_BUSY to detect a busy bus. This time is the maximum high time of the SCL line. For a 100 kHz interface frequency, this maximum high time may last roughly 5 us (half a bit period). For single master systems, BUS_BUSY does not have to be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START (no bus collisions). For multi-master systems, BUS_BUSY can be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START_ON_IDLE (to prevent bus collisions). Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1365
SCB0_I2C_M_CMD
24.1.11 SCB0_I2C_M_CMD
Address = 0x40610068 I2C master command Address: 0x40610068 Retention: Not Retained
Bits SW Access HW Access
Name
7
6
5
None
None
None [7:5]
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4 RW RW1C
M_STOP
3 RW RW1C
M_NACK
12
11
None
None
None [15:8]
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
2 RW RW1C M_ACK
10
1
RW
RW1C
M_START_ ON_IDLE
0 RW RW1C
M_START
9
8
18
17
16
26
25
24
Bits
Name
4
M_STOP
3
M_NACK
2
M_ACK
Description
When '1', attempt to transmit a STOP. When this action is performed, the hardware sets this field to '0'. I2C_M_CMD.M_START has a higher priority than this command: in situations where both a STOP and a REPEATED START could be transmitted, M_START takes precedence over M_STOP. Default Value: 0
When '1', attempt to transmit a negative acknowledgement (NACK). When this action is performed, the hardware sets this field to '0'. Default Value: 0
When '1', attempt to transmit an acknowledgement (ACK). When this action is performed, the hardware sets this field to '0'. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1366
SCB0_I2C_M_CMD
24.1.11 SCB0_I2C_M_CMD (continued)
1
M_START_ON_IDLE
When '1', transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0', note that
BUSY has a default value of '0').
For bus idle detection the hardware relies on STOP detection. As a result, bus idle detection is
only functional after at least one I2C bus transfer has been detected on the bus (default/reset
value of BUSY is '0') . A START is only transmitted when the master state machine is in the de-
fault state. When this action is performed, the hardware sets this field to '0'.
Default Value: 0
0
M_START
When '1', transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START is transmitted when the master state machine is not in the default state, but is working on an ongoing transaction. The REPEATED START can only be transmitted after a NACK or ACK has been received for a transmitted data element or after a NACK has been transmitted for a received data element. When this action is performed, the hardware sets this field to '0'. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1367
SCB0_I2C_S_CMD
24.1.12 SCB0_I2C_S_CMD
Address = 0x4061006C I2C slave command Address: 0x4061006C Retention: Not Retained
Bits
7
6
SW Access
HW Access
Name
Bits
15
14
SW Access
HW Access
Name
Bits
23
22
SW Access
HW Access
Name
Bits
31
30
SW Access
HW Access
Name
5
4
3
None
None
None [7:2]
13
12
11
None
None
None [15:8]
21
20
19
None
None
None [23:16]
29
28
27
None
None
None [31:24]
2
1
0
RW
RW
RW1C
RW1C
S_NACK
S_ACK
10
9
8
18
17
16
26
25
24
Bits
Name
1
S_NACK
0
S_ACK
Description
When '1', attempt to transmit a negative acknowledgement (NACK). When this action is performed, the hardware sets this field to '0'. In EZ and CMD_RESP mode, this field should be set to '0' (it is only to be used in FIFO mode). This command has a higher priority than I2C_S_CMD.S_ACK, I2C_CTRL.S_READY_ADDR_ACK or I2C_CTRL.S_READY_DATA_ACK. Default Value: 0
When '1', attempt to transmit an acknowledgement (ACK). When this action is performed, the hardware sets this field to '0'. In EZ and CMD_RESP mode, this field should be set to '0' (it is only to be used in FIFO mode). Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1368
SCB0_I2C_CFG
24.1.13 SCB0_I2C_CFG
Address = 0x40610070 I2C configuration Address: 0x40610070 Retention: Retained
Bits SW Access HW Access
Name
7
6
5
4
None
RW
None
R
None [7:5]
SDA_IN_FILT_SEL
Bits SW Access HW Access
Name
15
14
13
None
None
None [15:13]
12
RW
R
SCL_IN_FILT_SEL
Bits SW Access HW Access
Name
23
22
None
None
None [23:22]
21
20
RW
R
SDA_OUT_FILT2_TRIM [21:20]
Bits SW Access HW Access
Name
31
30
None
None
None [31:30]
29
28
RW
R
SDA_OUT_FILT_SEL [29:28]
3
2
None
None
None [3:2]
1
0
RW
R
SDA_IN_FILT_TRIM [1:0]
11
10
None
None
None [11:10]
9
8
RW
R
SCL_IN_FILT_TRIM [9:8]
19
18
RW
R
SDA_OUT_FILT1_TRIM [19:18]
17
16
RW
R
SDA_OUT_FILT0_TRIM [17:16]
27
26
25
24
None
None
None [27:24]
Bits 29 : 28
21 : 20 19 : 18 17 : 16
Name SDA_OUT_FILT_SEL
SDA_OUT_FILT2_TRIM SDA_OUT_FILT1_TRIM SDA_OUT_FILT0_TRIM
Description
Selection of cumulative "i2c_sda_out" filter delay: "0": 0 ns. "1": 50 ns (filter 0 enabled). "2": 100 ns (filters 0 and 1 enabled). "3": 150 ns (filters 0, 1 and 2 enabled). Default Value: 0
Trim bits for "i2c_sda_out" 50 ns filter 2. Not to be modified by the user Default Value: 2
Trim bits for "i2c_sda_out" 50 ns filter 1. Not to be modified by the user Default Value: 2
Trim bits for "i2c_sda_out" 50 ns filter 0. Not to be modified by the user Default Value: 2
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1369
SCB0_I2C_CFG
24.1.13 SCB0_I2C_CFG (continued)
12
SCL_IN_FILT_SEL
Selection of "i2c_scl_in" filter delay:
'0': 0 ns.
'1: 50 ns (filter enabled).
Default Value: 1
9 : 8
SCL_IN_FILT_TRIM
Trim bits for "i2c_scl_in" 50 ns filter. Not to be modified by the user
Default Value: 0
4
SDA_IN_FILT_SEL
Selection of "i2c_sda_in" filter delay:
'0': 0 ns.
'1: 50 ns (filter enabled).
Default Value: 1
1 : 0
SDA_IN_FILT_TRIM
Trim bits for "i2c_sda_in" 50 ns filter.
SDA_IN_FILT_TRIM[1] is used to enable I2CS_EC or SPIS_EC access to internal EZ memory.
1: enable clk_scb
0: disable clk_scb
Before going to deepsleep this field should be set to 0. It should be re-enabled once the device
is awoken and clk_hf[0] is at the desired frequency.
Default Value: 3
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1370
SCB0_TX_CTRL
24.1.14 SCB0_TX_CTRL
Address = 0x40610200 Transmitter control Address: 0x40610200 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:4]
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4
3
12
11
None
None
None [15:9]
20
19
None
None
None [23:17]
28
27
None
None
None [31:24]
2
1
RW
R
DATA_WIDTH [3:0]
10
9
18
17
26
25
0
8 RW R MSB_FIRST 16 RW R OPEN_DRA IN 24
Bits
Name
16
OPEN_DRAIN
Description
Each IO cell "xxx" has two associated SCB output signals "xxx_out_en" and "xxx_out". This field determines how the SCB controls those two signals. Consult the GPIO chapter in the architecture TRM to understand how the pin drive modes behave when connected to SCBs. '0': Normal operation mode. In this operation mode "xxx_out_en" output enable signal is typically constant '1' the "xxx_out" output is the outputted value. In other words, in normal operation mode, the "xxx_out" output is used to control the IO cell output value: "xxx_out" is '0' to drive an IO cell output value of '0' and "xxx_out" is '1' to drive an IO cell output value of '1'. '1': Open drain operation mode. In this operation mode "xxx_out_en" output controls the outputted value. Typically the "xxx_out" signal is a constant "0". Thus when "xxx_out_en" is "1" the line is driven low, but when "xxx_out_en" is "0" the output is not driven. This requires that the line is driven high by an external device or pull-up resistor The open drain mode is supported for: - I2C mode this field must be set. - UART mode use this mode when a pull-up resistor is used on the TX line. - SPI mode this field must be set if there are multiple slaves driving MISO. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1371
SCB0_TX_CTRL
24.1.14 SCB0_TX_CTRL (continued)
8
MSB_FIRST
3 : 0
DATA_WIDTH
Least significant bit first ('0') or most significant bit first ('1'). For I2C, this field should be '1'. For EZ and CMD_RESP this field must be set to "1" Default Value: 1
Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start, parity and stop bits. For UART mode, the valid range is [3, 8]. For SPI, the valid range is [3, 15]. For I2C the only valid value is 7. In EZ and CMD_RESP mode (for both SPI and I2C), the only valid value is 7. Default Value: 7
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1372
SCB0_TX_FIFO_CTRL
24.1.15 SCB0_TX_FIFO_CTRL
Address = 0x40610204 Transmitter FIFO control Address: 0x40610204 Retention: Retained
Bits
7
6
5
4
3
2
SW Access
None
RW
HW Access
None
R
Name
None
TRIGGER_LEVEL [6:0]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:18]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
1
0
9
8
17 RW R FREEZE
25
16 RW R CLEAR
24
Bits
Name
17
FREEZE
16
CLEAR
6 : 0
TRIGGER_LEVEL
Description
When '1', hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer. Default Value: 0
When '1', the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. Default Value: 0
Trigger level. When the transmitter FIFO has less entries than the number of this field, a transmitter trigger event is generated. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1373
SCB0_TX_FIFO_STATUS
24.1.16 SCB0_TX_FIFO_STATUS
Address = 0x40610208 Transmitter FIFO status Address: 0x40610208 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
USED [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
None
HW Access
W
None
Name
SR_VALID
None [14:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
R
HW Access
None
W
Name
None
RD_PTR [22:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
R
HW Access
None
W
Name
None
WR_PTR [30:24]
Bits 30 : 24 22 : 16 15
Name WR_PTR RD_PTR SR_VALID
7 : 0
USED
Description
FIFO write pointer: FIFO location at which a new data frame is written. Default Value: 0
FIFO read pointer: FIFO location from which a data frame is read by the hardware. Default Value: 0
Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working register and holds the data frame that is currently transmitted (when the protocol state machine is transmitting a data frame) or the data frame that is transmitted next (when the protocol state machine is not transmitting a data frame). Default Value: 0
Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1374
SCB0_TX_FIFO_WR
24.1.17 SCB0_TX_FIFO_WR
Address = 0x40610240 Transmitter FIFO write Address: 0x40610240 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
W
HW Access
R
Name
DATA [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
W
HW Access
R
Name
DATA [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 0
Name DATA
Description
Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.BYTE_MODE is '1', only DATA[7:0] are used. A write to a full TX FIFO sets INTR_TX.OVERFLOW to '1'. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1375
SCB0_RX_CTRL
24.1.18 SCB0_RX_CTRL
Address = 0x40610300 Receiver control Address: 0x40610300 Retention: Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:4]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:10]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
RW
R
DATA_WIDTH [3:0]
10
9
RW
R
MEDIAN
18
17
0
8 RW R MSB_FIRST 16
26
25
24
Bits
Name
9
MEDIAN
8
MSB_FIRST
3 : 0
DATA_WIDTH
Description
Median filter. When '1', a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However, its requires higher oversampling values. For UART IrDA submode, this field should always be '1'. Default Value: 0
Least significant bit first ('0') or most significant bit first ('1'). For I2C, this field should be '1'. For EZ and CMD_RESP this field must be set to "1" Default Value: 1
Dataframe width. DATA_WIDTH + 1 is the expected amount of bits in received data frame. This number does not include start, parity and stop bits. For UART mode, the valid range is [3, 8]. For SPI, the valid range is [3, 15]. For I2C the only valid value is 7. In EZ mode (for both SPI and I2C), the only valid value is 7. Default Value: 7
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1376
SCB0_RX_FIFO_CTRL
24.1.19 SCB0_RX_FIFO_CTRL
Address = 0x40610304 Receiver FIFO control Address: 0x40610304 Retention: Retained
Bits
7
6
5
4
3
2
SW Access
None
RW
HW Access
None
R
Name
None
TRIGGER_LEVEL [6:0]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:18]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
1
0
9
8
17 RW R FREEZE
25
16 RW R CLEAR
24
Bits
Name
17
FREEZE
16
CLEAR
6 : 0
TRIGGER_LEVEL
Description
When '1', hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer. Default Value: 0
When '1', the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. Default Value: 0
Trigger level. When the receiver FIFO has more entries than the number of this field, a receiver trigger event is generated. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1377
SCB0_RX_FIFO_STATUS
24.1.20 SCB0_RX_FIFO_STATUS
Address = 0x40610308 Receiver FIFO status Address: 0x40610308 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
USED [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
None
HW Access
W
None
Name
SR_VALID
None [14:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
R
HW Access
None
W
Name
None
RD_PTR [22:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
R
HW Access
None
W
Name
None
WR_PTR [30:24]
Bits 30 : 24 22 : 16 15
Name WR_PTR RD_PTR SR_VALID
7 : 0
USED
Description
FIFO write pointer: FIFO location at which a new data frame is written by the hardware. Default Value: 0
FIFO read pointer: FIFO location from which a data frame is read. Default Value: 0
Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register is a working register and holds the data frame that is currently being received (when the protocol state machine is receiving a data frame). Default Value: 0
Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1378
SCB0_RX_MATCH
24.1.21 SCB0_RX_MATCH
Address = 0x40610310 Slave address and mask Address: 0x40610310 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
ADDR [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
MASK [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 23 : 16
Name MASK
7 : 0
ADDR
Description
Slave device address mask. This field is a mask that specifies which of the ADDR field bits in the ADDR field take part in the matching of the slave address: MATCH = ((ADDR & MASK) == ("slave address" & MASK)). Default Value: 0
Slave device address. In UART multi-processor mode, all 8 bits are used. In I2C slave mode, only bits 7 down to 1 are used. This reflects the organization of the first transmitted byte in a I2C transfer: the first 7 bits represent the address of the addressed slave, and the last 1 bit is a read/write indicator ('0': write, '1': read). Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1379
SCB0_RX_FIFO_RD
24.1.22 SCB0_RX_FIFO_RD
Address = 0x40610340 Receiver FIFO read Address: 0x40610340 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
DATA [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
DATA [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 0
Name DATA
Description
Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.BYTE_MODE is '1', only DATA[7:0] are used. When in debug mode a read from this register behaves as a read from the SCB_RX_FIFO_RD_SILENT register. That is data will not be removed from the FIFO A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1380
SCB0_RX_FIFO_RD_SILENT
24.1.23 SCB0_RX_FIFO_RD_SILENT
Address = 0x40610344 Receiver FIFO read silent Address: 0x40610344 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
DATA [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
DATA [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 0
Name DATA
Description
Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.BYTE_MODE is '1', only DATA[7:0] are used. A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1381
SCB0_EZ_DATA0
24.1.24 SCB0_EZ_DATA0
Address = 0x40610400 Memory buffer Address: 0x40610400 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
EZ_DATA [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 7 : 0
Name EZ_DATA
Description
Data in buffer memory location. In case of a blocked discarded access, a read access returns 0xffff:ffff and a write access is dropped. Note that the 0xffff:ffff value is unique (not a legal EZ_DATA byte value) and can be detected by SW. Note that a discarded write access can be detected by reading back the written value, or checking the field BLOCKED of the INTR_TX and INTR_RX registers Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1382
SCB0_INTR_CAUSE
24.1.25 SCB0_INTR_CAUSE
Address = 0x40610E00 Active clocked interrupt signal Address: 0x40610E00 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:4]
4
3
2
1
0
R
R
R
R
W
W
W
W
RX
TX
S
M
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
3
RX
2
TX
1
S
0
M
Description
Receiver interrupt active ("interrupt_rx"): INTR_RX_MASKED != 0. Default Value: 0
Transmitter interrupt active ("interrupt_tx"): INTR_TX_MASKED != 0. Default Value: 0
Slave interrupt active ("interrupt_slave"): INTR_S_MASKED != 0. Default Value: 0
Master interrupt active ("interrupt_master"): INTR_M_MASKED != 0. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1383
SCB0_INTR_M
24.1.26 SCB0_INTR_M
Address = 0x40610F00 Master interrupt request Address: 0x40610F00 Retention: Not Retained
Bits SW Access HW Access
Name
7
6
None
None
None [7:5]
Bits
15
14
SW Access
HW Access
Name
Bits
23
22
SW Access
HW Access
Name
Bits
31
30
SW Access
HW Access
Name
5
4
3
RW1C
None
RW1S
None
I2C_STOP
None
13
12
11
None
None
None [15:10]
21
20
19
None
None
None [23:16]
29
28
27
None
None
None [31:24]
2 RW1C RW1S
I2C_ACK
1 RW1C RW1S
I2C_NACK
0
RW1C
RW1S
I2C_ARB_LOST
10
9
8
RW1C
RW1C
RW1S
RW1S
SPI_DONE
I2C_BUS_E RROR
18
17
16
26
25
24
Bits
Name
9
SPI_DONE
8
I2C_BUS_ERROR
4
I2C_STOP
2
I2C_ACK
1
I2C_NACK
Description
SPI master transfer done event: all data frames in the transmit FIFO are sent, the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty), and SPI select output pin is deselected. Default Value: 0
I2C master bus error (unexpected detection of START or STOP condition). Default Value: 0
I2C master STOP. Set to '1', when the master has transmitted a STOP. Default Value: 0
I2C master acknowledgement. Set to '1', when the master receives a ACK (typically after the master transmitted the slave address or TX data). Default Value: 0
I2C master negative acknowledgement. Set to '1', when the master receives a NACK (typically after the master transmitted the slave address or TX data). Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1384
SCB0_INTR_M
24.1.26 SCB0_INTR_M (continued)
0
I2C_ARB_LOST
I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1385
SCB0_INTR_M_SET
24.1.27 SCB0_INTR_M_SET
Address = 0x40610F04 Master interrupt set request Address: 0x40610F04 Retention: Not Retained
Bits SW Access HW Access
Name
7
6
5
None
None
None [7:5]
4 RW1S
A
I2C_STOP
3 None None
None
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:10]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2 RW1S
A
I2C_ACK
1 RW1S
A
I2C_NACK
0
RW1S
A
I2C_ARB_LOST
10
9
8
RW1S
RW1S
A
A
SPI_DONE
I2C_BUS_E RROR
18
17
16
26
25
24
Bits
Name
9
SPI_DONE
8
I2C_BUS_ERROR
4
I2C_STOP
2
I2C_ACK
1
I2C_NACK
0
I2C_ARB_LOST
Description
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1386
SCB0_INTR_M_MASK
24.1.28 SCB0_INTR_M_MASK
Address = 0x40610F08 Master interrupt mask Address: 0x40610F08 Retention: Retained
Bits SW Access HW Access
Name
7
6
5
None
None
None [7:5]
4 RW R
I2C_STOP
3 None None
None
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:10]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2 RW R
I2C_ACK
1 RW R
I2C_NACK
0
RW
R
I2C_ARB_LOST
10
9
8
RW
RW
R
R
SPI_DONE
I2C_BUS_E RROR
18
17
16
26
25
24
Bits
Name
9
SPI_DONE
8
I2C_BUS_ERROR
4
I2C_STOP
2
I2C_ACK
1
I2C_NACK
0
I2C_ARB_LOST
Description
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1387
SCB0_INTR_M_MASKED
24.1.29 SCB0_INTR_M_MASKED
Address = 0x40610F0C Master interrupt masked request Address: 0x40610F0C Retention: Not Retained
Bits SW Access HW Access
Name
7
6
5
4
None
R
None
W
None [7:5]
I2C_STOP
3 None None
None
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:10]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2 R W
I2C_ACK
1 R W
I2C_NACK
0
R
W
I2C_ARB_LOST
10
9
8
R
R
W
W
SPI_DONE
I2C_BUS_E RROR
18
17
16
26
25
24
Bits
Name
9
SPI_DONE
8
I2C_BUS_ERROR
4
I2C_STOP
2
I2C_ACK
1
I2C_NACK
0
I2C_ARB_LOST
Description
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1388
SCB0_INTR_S
24.1.30 SCB0_INTR_S
Address = 0x40610F40 Slave interrupt request Address: 0x40610F40 Retention: Not Retained
Bits SW Access HW Access
Name
7
RW1C
RW1S
I2C_GENERAL
6
5
RW1C
RW1C
RW1S
RW1S
I2C_ADDR_MATCH
I2C_START
4 RW1C RW1S
I2C_STOP
3
RW1C
RW1S
I2C_WRITE _STOP
2 RW1C RW1S
I2C_ACK
1 RW1C RW1S
I2C_NACK
0
RW1C
RW1S
I2C_ARB_LOST
Bits
15
SW Access
HW Access
Name
14
13
None
None
None [15:12]
12
11
10
9
8
RW1C
RW1C
RW1C
RW1C
RW1S
RW1S
RW1S
RW1S
SPI_BUS_E SPI_EZ_ST SPI_EZ_W I2C_BUS_E
RROR
OP
RITE_STOP RROR
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
Description
11
SPI_BUS_ERROR
SPI slave deselected at an unexpected time in the SPI transfer. Firmware may decide to clear
the TX and RX FIFOs in case of this error.
Default Value: 0
10
SPI_EZ_STOP
SPI slave deselected after any EZ SPI transfer occurred. Default Value: 0
9
SPI_EZ_WRITE_STOP SPI slave deselected after a write EZ SPI transfer occurred.
Default Value: 0
8
I2C_BUS_ERROR
I2C slave bus error (unexpected detection of START or STOP condition). This should not occur,
it represents erroneous I2C bus behavior. In case of a bus error, the I2C slave state machine
abort the ongoing transfer. Firmware may decide to clear the TX and RX FIFOs in case of this
error.
Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1389
SCB0_INTR_S
24.1.30 SCB0_INTR_S (continued)
7
I2C_GENERAL
I2C slave general call address received. If CTRL.ADDR_ACCEPT is set the received address 0x00 (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked operation (CTRL.EC_OP_MODE is '0'), this field is set when the event is detected. Default Value: 0
6
I2C_ADDR_MATCH
I2C slave matching address received. If CTRL.ADDR_ACCEPT, the received address (including
the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching
(CTRL.EC_AM_MODE is '1') and internally clocked operation (CTRL.EC_OP_MODE is '0'), this
field is set when the event is detected.
Default Value: 0
5
I2C_START
I2C slave START received. Set to '1', when START or REPEATED START event is detected. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') AND clock stretching is performed (till the internally clocked logic takes over) (I2C_CTRL.S_NOT_READY_ADDR_NACK is '0'), this field is NOT set. Firmware should use INTR_S_EC.WAKE_UP, INTR_S.I2C_ADDR_MATCH and INTR_S.I2C_GENERAL. Default Value: 0
4
I2C_STOP
I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1', when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C transfers separated by a REPEATED START can be distinguished and potentially treated separately by the Firmware. Note that the second I2C transfer (after a REPEATED START) may be to a different slave address. The event is detected on any I2C transfer intended for this slave. Note that a I2C address intended for the slave (address is matching) will result in a I2C_STOP event independent of whether the I2C address is ACK'd or NACK'd. Default Value: 0
3
I2C_WRITE_STOP
I2C STOP event for I2C write transfer intended for this slave (address matching is performed).
Set to '1', when STOP or REPEATED START event is detected. The REPEATED START event
is included in this interrupt cause such that the I2C transfers separated by a REPEATED START
can be distinguished and potentially treated separately by the firmware. Note that the second I2C
transfer (after a REPEATED START) may be to a different slave address.
Note that a I2C write address intended for the slave (address is matching and a it is a write trans-
fer) will result in a I2C_WRITE_STOP event independent of whether the I2C address is ACK'd
or NACK'd.
In EZ mode, the event is detected only on I2C write transfers that have EZ data written to the
memory structure (an I2C write transfer that only communicates an I2C address and EZ base
address, will not result in this event being detected).
Default Value: 0
2
I2C_ACK
I2C slave acknowledgement received. Set to '1', when the slave receives a ACK (typically after the slave transmitted TX data). Default Value: 0
1
I2C_NACK
I2C slave negative acknowledgement received. Set to '1', when the slave receives a NACK (typically after the slave transmitted TX data). Default Value: 0
0
I2C_ARB_LOST
I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur, it represents erroneous I2C bus behavior. In case of lost arbitration, the I2C slave state machine aborts the ongoing transfer. SW may decide to clear the TX and RX FIFOs in case of this error. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1390
SCB0_INTR_S_SET
24.1.31 SCB0_INTR_S_SET
Address = 0x40610F44 Slave interrupt set request Address: 0x40610F44 Retention: Not Retained
Bits SW Access HW Access
Name
7
RW1S
A
I2C_GENERAL
6
5
RW1S
RW1S
A
A
I2C_ADDR_MATCH
I2C_START
4 RW1S
A
I2C_STOP
3
RW1S
A
I2C_WRITE _STOP
2 RW1S
A
I2C_ACK
1 RW1S
A
I2C_NACK
0
RW1S
A
I2C_ARB_LOST
Bits
15
SW Access
HW Access
Name
14
13
None
None
None [15:12]
12
11
10
9
8
RW1S
RW1S
RW1S
RW1S
A
A
A
A
SPI_BUS_E SPI_EZ_ST SPI_EZ_W I2C_BUS_E
RROR
OP
RITE_STOP RROR
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
Description
11
SPI_BUS_ERROR
Write with '1' to set corresponding bit in interrupt request register.
Default Value: 0
10
SPI_EZ_STOP
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
9
SPI_EZ_WRITE_STOP Write with '1' to set corresponding bit in interrupt request register.
Default Value: 0
8
I2C_BUS_ERROR
Write with '1' to set corresponding bit in interrupt request register.
Default Value: 0
7
I2C_GENERAL
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
6
I2C_ADDR_MATCH
Write with '1' to set corresponding bit in interrupt request register.
Default Value: 0
5
I2C_START
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1391
SCB0_INTR_S_SET
24.1.31 SCB0_INTR_S_SET (continued)
4
I2C_STOP
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
3
I2C_WRITE_STOP
Write with '1' to set corresponding bit in interrupt request register.
Default Value: 0
2
I2C_ACK
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
1
I2C_NACK
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
0
I2C_ARB_LOST
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1392
SCB0_INTR_S_MASK
24.1.32 SCB0_INTR_S_MASK
Address = 0x40610F48 Slave interrupt mask Address: 0x40610F48 Retention: Retained
Bits SW Access HW Access
Name
7
RW
R
I2C_GENERAL
6
5
RW
RW
R
R
I2C_ADDR_MATCH
I2C_START
4 RW R
I2C_STOP
3
RW
R
I2C_WRITE _STOP
2 RW R
I2C_ACK
1 RW R
I2C_NACK
0
RW
R
I2C_ARB_LOST
Bits
15
SW Access
HW Access
Name
14
13
None
None
None [15:12]
12
11
10
9
8
RW
RW
RW
RW
R
R
R
R
SPI_BUS_E SPI_EZ_ST SPI_EZ_W I2C_BUS_E
RROR
OP
RITE_STOP RROR
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
Description
11
SPI_BUS_ERROR
Mask bit for corresponding bit in interrupt request register.
Default Value: 0
10
SPI_EZ_STOP
Mask bit for corresponding bit in interrupt request register. Default Value: 0
9
SPI_EZ_WRITE_STOP Mask bit for corresponding bit in interrupt request register.
Default Value: 0
8
I2C_BUS_ERROR
Mask bit for corresponding bit in interrupt request register.
Default Value: 0
7
I2C_GENERAL
Mask bit for corresponding bit in interrupt request register. Default Value: 0
6
I2C_ADDR_MATCH
Mask bit for corresponding bit in interrupt request register.
Default Value: 0
5
I2C_START
Mask bit for corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1393
SCB0_INTR_S_MASK
24.1.32 SCB0_INTR_S_MASK (continued)
4
I2C_STOP
Mask bit for corresponding bit in interrupt request register. Default Value: 0
3
I2C_WRITE_STOP
Mask bit for corresponding bit in interrupt request register.
Default Value: 0
2
I2C_ACK
Mask bit for corresponding bit in interrupt request register. Default Value: 0
1
I2C_NACK
Mask bit for corresponding bit in interrupt request register. Default Value: 0
0
I2C_ARB_LOST
Mask bit for corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1394
SCB0_INTR_S_MASKED
24.1.33 SCB0_INTR_S_MASKED
Address = 0x40610F4C Slave interrupt masked request Address: 0x40610F4C Retention: Not Retained
Bits SW Access HW Access
Name
7
R
W
I2C_GENERAL
6
5
R
R
W
W
I2C_ADDR_MATCH
I2C_START
4 R W
I2C_STOP
3
R
W
I2C_WRITE _STOP
2 R W
I2C_ACK
1 R W
I2C_NACK
0
R
W
I2C_ARB_LOST
Bits
15
SW Access
HW Access
Name
14
13
None
None
None [15:12]
12
11
10
9
8
R
R
R
R
W
W
W
W
SPI_BUS_E SPI_EZ_ST SPI_EZ_W I2C_BUS_E
RROR
OP
RITE_STOP RROR
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
Description
11
SPI_BUS_ERROR
Logical and of corresponding request and mask bits.
Default Value: 0
10
SPI_EZ_STOP
Logical and of corresponding request and mask bits. Default Value: 0
9
SPI_EZ_WRITE_STOP Logical and of corresponding request and mask bits.
Default Value: 0
8
I2C_BUS_ERROR
Logical and of corresponding request and mask bits.
Default Value: 0
7
I2C_GENERAL
Logical and of corresponding request and mask bits. Default Value: 0
6
I2C_ADDR_MATCH
Logical and of corresponding request and mask bits.
Default Value: 0
5
I2C_START
Logical and of corresponding request and mask bits. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1395
SCB0_INTR_S_MASKED
24.1.33 SCB0_INTR_S_MASKED (continued)
4
I2C_STOP
Logical and of corresponding request and mask bits. Default Value: 0
3
I2C_WRITE_STOP
Logical and of corresponding request and mask bits.
Default Value: 0
2
I2C_ACK
Logical and of corresponding request and mask bits. Default Value: 0
1
I2C_NACK
Logical and of corresponding request and mask bits. Default Value: 0
0
I2C_ARB_LOST
Logical and of corresponding request and mask bits. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1396
SCB0_INTR_TX
24.1.34 SCB0_INTR_TX
Address = 0x40610F80 Transmitter interrupt request Address: 0x40610F80 Retention: Not Retained
Bits SW Access HW Access
Name
7 None None
None
6
RW1C
RW1S
UNDERFLOW
5
RW1C
RW1S
OVERFLOW
4 RW1C RW1S
EMPTY
3
2
None
None
None [3:2]
1 RW1C RW1S
0 RW1C RW1S
NOT_FULL TRIGGER
Bits
15
SW Access
HW Access
Name
14
13
12
None
None
None [15:11]
11
10
9
8
RW1C
RW1C
RW1C
RW1S
RW1S
RW1S
UART_ARB_LOST
UART_DONE
UART_NAC K
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
10
UART_ARB_LOST
9
UART_DONE
8
UART_NACK
6
UNDERFLOW
Description
UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is usefull when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes. Default Value: 0
UART transmitter done event. This happens when the SCB is done transferring all data in the TX FIFO, and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty). Default Value: 0
UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1', when event is detected. Write with '1' to clear bit. Default Value: 0
Attempt to read from an empty TX FIFO. This happens when the SCB is ready to transfer data and EMPTY is '1'. Only used in FIFO mode. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1397
SCB0_INTR_TX
24.1.34 SCB0_INTR_TX (continued)
5
OVERFLOW
4
EMPTY
1
NOT_FULL
0
TRIGGER
Attempt to write to a full TX FIFO. Only used in FIFO mode. Default Value: 0
TX FIFO is empty; i.e. it has 0 entries. Only used in FIFO mode. Default Value: 0
TX FIFO is not full. Dependent on CTRL.BYTE_MODE: BYTE_MODE is '0': # entries != FF_DATA_NR/2. BYTE_MODE is '1': # entries != FF_DATA_NR. Only used in FIFO mode. Default Value: 0
Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL. Only used in FIFO mode. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1398
SCB0_INTR_TX_SET
24.1.35 SCB0_INTR_TX_SET
Address = 0x40610F84 Transmitter interrupt set request Address: 0x40610F84 Retention: Not Retained
Bits SW Access HW Access
Name
7 None None
None
6
RW1S
A
UNDERFLOW
5
RW1S
A
OVERFLOW
4 RW1S
A
EMPTY
3
2
None
None
None [3:2]
1 RW1S
A
0 RW1S
A
NOT_FULL TRIGGER
Bits
15
SW Access
HW Access
Name
14
13
12
None
None
None [15:11]
11
10
9
8
RW1S
RW1S
RW1S
A
A
A
UART_ARB_LOST
UART_DONE
UART_NAC K
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
10
UART_ARB_LOST
9
UART_DONE
8
UART_NACK
6
UNDERFLOW
5
OVERFLOW
4
EMPTY
1
NOT_FULL
Description
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1399
SCB0_INTR_TX_SET
24.1.35 SCB0_INTR_TX_SET (continued)
0
TRIGGER
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1400
SCB0_INTR_TX_MASK
24.1.36 SCB0_INTR_TX_MASK
Address = 0x40610F88 Transmitter interrupt mask Address: 0x40610F88 Retention: Retained
Bits SW Access HW Access
Name
7 None None
None
6
RW
R
UNDERFLOW
5
RW
R
OVERFLOW
4 RW R
EMPTY
3
2
None
None
None [3:2]
1
0
RW
RW
R
R
NOT_FULL TRIGGER
Bits
15
SW Access
HW Access
Name
14
13
12
None
None
None [15:11]
11
10
9
8
RW
RW
RW
R
R
R
UART_ARB_LOST
UART_DONE
UART_NAC K
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
10
UART_ARB_LOST
9
UART_DONE
8
UART_NACK
6
UNDERFLOW
5
OVERFLOW
4
EMPTY
1
NOT_FULL
Description
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1401
SCB0_INTR_TX_MASK
24.1.36 SCB0_INTR_TX_MASK (continued)
0
TRIGGER
Mask bit for corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1402
SCB0_INTR_TX_MASKED
24.1.37 SCB0_INTR_TX_MASKED
Address = 0x40610F8C Transmitter interrupt masked request Address: 0x40610F8C Retention: Not Retained
Bits SW Access HW Access
Name
7 None None
None
6
R
W
UNDERFLOW
5
R
W
OVERFLOW
4 R W
EMPTY
3
2
None
None
None [3:2]
1
0
R
R
W
W
NOT_FULL TRIGGER
Bits
15
SW Access
HW Access
Name
14
13
12
None
None
None [15:11]
11
10
9
8
R
R
R
W
W
W
UART_ARB_LOST
UART_DONE
UART_NAC K
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
10
UART_ARB_LOST
9
UART_DONE
8
UART_NACK
6
UNDERFLOW
5
OVERFLOW
4
EMPTY
1
NOT_FULL
Description
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1403
SCB0_INTR_TX_MASKED
24.1.37 SCB0_INTR_TX_MASKED (continued)
0
TRIGGER
Logical and of corresponding request and mask bits. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1404
SCB0_INTR_RX
24.1.38 SCB0_INTR_RX
Address = 0x40610FC0 Receiver interrupt request Address: 0x40610FC0 Retention: Not Retained
Bits SW Access HW Access
Name
7 None None
None
6
RW1C
RW1S
UNDERFLOW
5
RW1C
RW1S
OVERFLOW
Bits
15
SW Access
HW Access
Name
14
13
None
None
None [15:12]
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4 None None
None
3 RW1C RW1S
FULL
2
RW1C
RW1S
NOT_EMPTY
1 None None
None
0 RW1C RW1S
TRIGGER
12
11
10
9
8
RW1C
RW1C
RW1C
RW1C
RW1S
RW1S
RW1S
RW1S
BREAK_DETECT
BAUD_DE-
PARI-
FRAME_ER
TECT
TY_ERROR
ROR
20
19
18
17
16
None
None
None [23:16]
28
27
26
25
24
None
None
None [31:24]
Bits
Name
11
BREAK_DETECT
10
BAUD_DETECT
Description
Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. "break-in-data" is supported. This feature is supported for the UART standard and LIN submodes. For the UART standard submodes, ongoing receipt of data frames is NOT affected; i.e. Firmware is expected to take the proper action. For the LIN submode, possible ongoing receipt of a data frame is stopped and the (partially) received data frame is dropped and baud rate detection is started. Set to '1', when event is detected. Write with '1' to clear bit. Default Value: 0
LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the clk_scb to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1405
SCB0_INTR_RX
24.1.38 SCB0_INTR_RX (continued)
9
PARITY_ERROR
UART Parity error in received data frame. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1',
the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0', the re-
ceived frame is send to the RX FIFO. In SmartCard submode, negatively acknowledged data
frames generate a parity error. Note that Firmware can only identify the erroneous data frame in
the RX FIFO if it is fast enough to read the data frame before the hardware writes a next data
frame into the RX FIFO.
Default Value: 0
8
FRAME_ERROR
UART Frame error in received data frame.
This can be either a start or stop bit(s) error:
Start bit error: after the detection of the beginning of a start bit period (RX line changes from '1'
to '0'), the middle of the start bit period is sampled erroneously (RX line is '1'). Note: a start bit
error is detected BEFORE a data frame is received.
Stop bit error: the RX line is sampled as '0', but a '1' was expected. Note: a stop bit error may
result in failure to receive successive data frame(s). Note: a stop bit error is detected AFTER a
data frame is received.
A stop bit error is detected after a data frame is received, and the UART_RX_CTL.DROP_ON_-
FRAME_ERROR field specifies whether the received frame is dropped or send to the RX FIFO.
If UART_RX_CTL.DROP_ON_FRAME_ERROR is '1', the received data frame is dropped. If
UART_RX_CTL.DROP_ON_FRAME_ERROR is '0', the received data frame is send to the RX
FIFO. Note that Firmware can only identify the erroneous data frame in the RX FIFO if it is fast
enough to read the data frame before the hardware writes a next data frame into the RX FIFO;
i.e. the RX FIFO does not have error flags to tag erroneous data frames.
Default Value: 0
6
UNDERFLOW
Attempt to read from an empty RX FIFO. Only used in FIFO mode. Default Value: 0
5
OVERFLOW
Attempt to write to a full RX FIFO. Note: in I2C mode, the OVERFLOW is set when a data frame is received and the RX FIFO is full, independent of whether it is ACK'd or NACK'd. Only used in FIFO mode. Default Value: 0
3
FULL
RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.BYTE_MODET: BYTE_MODE is '0': # entries == FF_DATA_NR/2. BYTE_MODE is '1': # entries == FF_DATA_NR. Only used in FIFO mode. Default Value: 0
2
NOT_EMPTY
RX FIFO is not empty. Only used in FIFO mode. Default Value: 0
0
TRIGGER
More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in SCB_RX_FIFO_CTL. Only used in FIFO mode. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1406
SCB0_INTR_RX_SET
24.1.39 SCB0_INTR_RX_SET
Address = 0x40610FC4 Receiver interrupt set request Address: 0x40610FC4 Retention: Not Retained
Bits SW Access HW Access
Name
7 None None
None
6
RW1S
A
UNDERFLOW
5
RW1S
A
OVERFLOW
Bits
15
SW Access
HW Access
Name
14
13
None
None
None [15:12]
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4 None None
None
3 RW1S
A
FULL
2
RW1S
A
NOT_EMPTY
1 None None
None
0 RW1S
A
TRIGGER
12
11
10
9
8
RW1S
RW1S
RW1S
RW1S
A
A
A
A
BREAK_DETECT
BAUD_DE-
PARI-
FRAME_ER
TECT
TY_ERROR
ROR
20
19
18
17
16
None
None
None [23:16]
28
27
26
25
24
None
None
None [31:24]
Bits
Name
11
BREAK_DETECT
10
BAUD_DETECT
9
PARITY_ERROR
8
FRAME_ERROR
6
UNDERFLOW
5
OVERFLOW
3
FULL
Description
Write with '1' to set corresponding bit in interrupt status register. Default Value: 0
Write with '1' to set corresponding bit in interrupt status register. Default Value: 0
Write with '1' to set corresponding bit in interrupt status register. Default Value: 0
Write with '1' to set corresponding bit in interrupt status register. Default Value: 0
Write with '1' to set corresponding bit in interrupt status register. Default Value: 0
Write with '1' to set corresponding bit in interrupt status register. Default Value: 0
Write with '1' to set corresponding bit in interrupt status register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1407
SCB0_INTR_RX_SET
24.1.39 SCB0_INTR_RX_SET (continued)
2
NOT_EMPTY
0
TRIGGER
Write with '1' to set corresponding bit in interrupt status register. Default Value: 0
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1408
SCB0_INTR_RX_MASK
24.1.40 SCB0_INTR_RX_MASK
Address = 0x40610FC8 Receiver interrupt mask Address: 0x40610FC8 Retention: Retained
Bits SW Access HW Access
Name
7 None None
None
6
RW
R
UNDERFLOW
5
RW
R
OVERFLOW
Bits
15
SW Access
HW Access
Name
14
13
None
None
None [15:12]
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4 None None
None
3 RW R
FULL
2
RW
R
NOT_EMPTY
1 None None
None
0 RW R
TRIGGER
12
11
10
9
8
RW
RW
RW
RW
R
R
R
R
BREAK_DETECT
BAUD_DE-
PARI-
FRAME_ER
TECT
TY_ERROR
ROR
20
19
18
17
16
None
None
None [23:16]
28
27
26
25
24
None
None
None [31:24]
Bits
Name
11
BREAK_DETECT
10
BAUD_DETECT
9
PARITY_ERROR
8
FRAME_ERROR
6
UNDERFLOW
5
OVERFLOW
3
FULL
Description
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1409
SCB0_INTR_RX_MASK
24.1.40 SCB0_INTR_RX_MASK (continued)
2
NOT_EMPTY
0
TRIGGER
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1410
SCB0_INTR_RX_MASKED
24.1.41 SCB0_INTR_RX_MASKED
Address = 0x40610FCC Receiver interrupt masked request Address: 0x40610FCC Retention: Not Retained
Bits SW Access HW Access
Name
7 None None
None
6
R
W
UNDERFLOW
5
R
W
OVERFLOW
4 None None
None
3 R W
FULL
2
R
W
NOT_EMPTY
1 None None
None
0 R W
TRIGGER
Bits
15
SW Access
HW Access
Name
14
13
None
None
None [15:12]
12
11
10
9
8
R
R
R
R
W
W
W
W
BREAK_DETECT
BAUD_DE-
PARI-
FRAME_ER
TECT
TY_ERROR
ROR
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
11
BREAK_DETECT
10
BAUD_DETECT
9
PARITY_ERROR
8
FRAME_ERROR
6
UNDERFLOW
5
OVERFLOW
3
FULL
Description
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1411
SCB0_INTR_RX_MASKED
24.1.41 SCB0_INTR_RX_MASKED (continued)
2
NOT_EMPTY
0
TRIGGER
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1412
SCB8_CTRL
24.1.42 SCB8_CTRL
Address = 0x40690000 Generic control Address: 0x40690000 Retention: Retained
Bits
7
6
5
4
SW Access
None
HW Access
None
Name
None [7:4]
Bits SW Access HW Access
Name
15
14
13
None
None
None [15:13]
12
RW
R
CMD_RESP_MODE
Bits
23
22
21
20
SW Access
None
HW Access
None
Name
None [23:18]
3
11 RW R BYTE_MODE 19
Bits
31
30
SW Access
RW
HW Access
R
Name
ENABLED
29
28
27
None
None
None [30:26]
2
1
0
RW
R
OVS [3:0]
10 RW R
EZ_MODE
9
RW
R
EC_OP_MODE
8
RW
R
EC_AM_MODE
18
17
16
RW
RW
R
R
BLOCK
ADDR_ACCEPT
26
25
24
RW
R
MODE [25:24]
Bits
Name
31
ENABLED
25 : 24
MODE
Description
0': Block Disabled '1': Block Enabled The proper order in which to initialize the SCB is as follows: - Program protocol specific information using SPI_CTRL, UART_CTRL (and UART_TX_CTRL and UART_RX_CTRL) or I2C_CTRL. This includes selection of a submode, master/slave functionality and transmitter/receiver functionality when applicable. - Program generic transmitter (TX_CTRL) and receiver (RX_CTRL) information. This includes enabling of the transmitter and receiver functionality. - Program transmitter FIFO (TX_FIFO_CTRL) and receiver FIFO (RX_FIFO_CTRL) information. - Program CTRL to enable SCB, select the specific operation mode and oversampling factor. When the SCB is enabled, no control information should be changed. Changes must be made AFTER disabling the SCB, e.g. to modify the operation mode (from I2C to SPI) or to go from externally to internally clocked. The change takes effect after the SCB is re-enabled. Note that disabling the SCB will cause re-initialization of the design and associated state is lost (e.g. FIFO content). Default Value: 0
Mode of operation (3: Reserved) Default Value: 3
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1413
SCB8_CTRL
24.1.42 SCB8_CTRL (continued)
0x0: I2C : Inter-Integrated Circuits (I2C) mode.
0x1: SPI : Serial Peripheral Interface (SPI) mode.
0x2: UART : Universal Asynchronous Receiver/Transmitter (UART) mode.
17
BLOCK
Only used in externally clocked mode. If the externally clocked logic and the CPU access the EZ memory at the same time this bit determines whether a CPU access should block and result in bus wait states '0': Do not block, but ingore a write and return 0xffff:ffff for a read '1': Block, resulting in CPU wait states. If BLOCK is 0 and the accesses collide, CPU read operations return 0xffff:ffff and CPU write operations are ignored. Colliding accesses are registered as interrupt causes: field BLOCKED of the INTR_TX and INTR_RX registers. Default Value: 0
16
ADDR_ACCEPT
Determines whether a received matching address is accepted in the RX FIFO:. '0': Matching address does not go in RX FIFO '1': Match address does go in RX FIFO In I2C mode, this field is used to allow the slave to put the received slave address or general call address in the RX FIFO. Note that a received matching address is put in the RX FIFO when this bit is '1' for both I2C read and write transfers. In multi-processor UART receiver mode, this field is used to allow the receiver to put the received address in the RX FIFO. Note: non-matching addresses are never put in the RX FIFO. In SPI mode this field must be '0' Default Value: 0
12
CMD_RESP_MODE
Determines CMD_RESP mode of operation:
'0': CMD_RESP mode disabled.
'1': CMD_RESP mode enabled (also requires EC_AM_MODE and EC_OP_MODE to be set to
'1').
In CMD_RESP mode, a meta protocol is applied to the serial interface protocol. This meta pro-
tocol adds meaning to the data frames transferred by the serial interface protocol: a data frame
can represent a write memory data element or a read memory data element. The difference from
EZ mode is that the address is written by the CPU, not the interface master.
CMD_RESP mode can only be used for synchronous serial interface protocols (SPI and I2C) in
slave mode.
In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported. The external
master should use continuous data frames; i.e. data frames not seperated by slave deselection.
In CMD_RESP mode, data frames should 8-bit in size and should be transmitted and received
with the Most Significant Bit (MSB) first.
In UART mode this field must be '0'.
Default Value: 0
11
BYTE_MODE
Determines the number of bits per FIFO data element: '0': 16-bit FIFO data elements. '1': 8-bit FIFO data elements. This mode doubles the amount of FIFO entries, but TX_CTRL.DATA_WIDTH and RX_CTRL.DATA_WIDTH are restricted to [0, 7]. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1414
SCB8_CTRL
24.1.42 SCB8_CTRL (continued)
10
EZ_MODE
9
EC_OP_MODE
8
EC_AM_MODE
This field determines if EZ mode is enabled or disabled for the SCB block '0': EZ Mode Disabled '1': EZ Mode Enabled In EZ mode, a meta protocol is applied to the serial interface protocol. This meta protocol adds meaning to the data frames transferred by the serial interface protocol: a data frame can represent a memory address, a write memory data element or a read memory data element. EZ mode can only be used for synchronous serial interface protocols (SPI and I2C) in slave mode. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported. The external master should use continuous data frames; i.e. data frames not seperated by slave deselection. In EZ mode, data frames should 8-bit in size and should be transmitted and received with the Most Significant Bit (MSB) first. In UART mode this field must be '0'. Default Value: 0
This field specifies the clocking for the SCB block after the address phase '0': Internally clocked mode '1': externally clocked mode In internally clocked mode, the serial interface protocols run off the clk_scb. In externally clocked mode, the serial interface protocols run off the clock as provided by the serial interface. Externally clocked operation mode is only used for synchronous serial interface protocols (SPI and I2C) in slave mode. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported. In UART mode this field must be '0'. Default Value: 0
This field specifies the clocking for the address matching (I2C slave) or slave selection detection logic (SPI slave) '0': Internally clocked mode '1': Externally clocked mode In internally clocked mode the address detection(and slave selection detection) is done by clk_scb, and thus won't be done in deep sleep power mode as clk_scb isn't active. In externally clocked mode the address detection is done by the I2C/SPI interface clock. This allows for the device to be awoken on I2C salve address match and SPI slave select assertion. The clocking for the rest of the logic is determined by CTRL.EC_OP_MODE. Externally clocked mode is only used for synchronous serial interface protocols (SPI and I2C) in slave mode. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported. In UART mode this field must be '0'. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1415
SCB8_CTRL
24.1.42 SCB8_CTRL (continued)
3 : 0
OVS
Serial interface bit period oversampling factor expressed in clk_scb cycles. clk_scb is the peripheral clock divider connected to the SCB. Used for SPI Master and UART functionality. This field is NOT used in externally clocked mode. This filed is NOT used for SPI slave or I2C mode. OVS + 1 clk_scb cycles constitute a single serial interface clock/bit cycle. If OVS is odd, the oversampling factor is even and the low and high phase of the interface clock period are the same. If OVS is even, the oversampling factor is odd and the low and high phase can differ by 1 SCB clock period. In SPI master mode, the valid range is [3, 15]. The frequency of the SPI Clock is (frequency of clk_scb) / (OVS + 1). For example, is clk_scb is 50 MHz and OVS is 9, then the frequency of SPI Clock is 50 MHz / (9+1) = 5 MHz. If the MISO signal is not used for SPI master the valid range changes to [1,15] In SPI slave mode, the OVS field is NOT used. Refer to the architecture TRM for information on how to configure clk_scb for SPI Slave. Generally, it is recommended that clk_scb be as fast as possible for the slave. In UART standard sub mode (including LIN and Smartcard), the valid range is [7, 15]. In UART IrDA sub mode this field indirectly specifies the oversampling. The oversampling determines the interface clock/bit cycle and the width of the pulse. For normal transmission mode, the pulse is roughly 3/16 of the bit period (for all bit rates). There is only one valid OVS value: - 0: 16 times oversampling. clk_scb frequency = 16*115.2 KHz for 115.2 Kbps. clk_scb frequency = 16*57.6 KHz for 57.6 Kbps. clk_scb frequency = 16*38.4 KHz for 38.4 Kbps. clk_scb frequency = 16*19.2 KHz for 19.2 Kbps. clk_scb frequency = 16*9.6 KHz for 9.6 Kbps. clk_scb frequency = 16*2.4 KHz for 2.4 Kbps. clk_scb frequency = 16*1.2 KHz for 1.2 Kbps. - all other values are not used in normal mode. RX_CTRL.MEDIAN must be set to '1' for IrDA receiver functionality. UART IrDA RX Low power mode, OVS field values (with the required clk_scb frequency): - 0: 16 times oversampling. clk_scb frequency = 16*115.2 KHz for 115.2 Kbps. - 1: 32 times oversampling. clk_scb frequency = 32*57.6 KHz for 57.6 Kbps. - 2: 48 times oversampling. clk_scb frequency = 48*38.4 KHz for 38.4 Kbps. - 3: 96 times oversampling. clk_scb frequency = 96*19.2 KHz for 19.2 Kbps. - 4: 192 times oversampling. clk_scb frequency = 192*9.6 KHz for 9.6 Kbps. - 5: 768 times oversampling. clk_scb frequency = 768*2.4 KHz for 2.4 Kbps. - 6: 1536 times oversampling. clk_scb frequency = 1536*1.2 KHz for 1.2 Kbps. - all other values are not used in low power mode. In low power transmission mode, this pulse is potentially smaller (down to 1.62 us typical and 1.41 us minimal) than 3/16 of the bit period (for < 115.2 Kbps bitrates). Pulse widths greater or equal than two SCB clock cycles are guaranteed to be detected by the receiver. Pulse widths less than two SCB clock cycles and greater or equal than one SCB clock cycle may be detected by the receiver. Pulse widths less than one SCB clock cycle will not be detected by the receiver. Default Value: 15
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1416
SCB8_STATUS
24.1.43 SCB8_STATUS
Address = 0x40690004 Generic status Address: 0x40690004 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
R
HW Access
None
W
Name
None [7:1]
EC_BUSY
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
EC_BUSY
Description
Inidicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ and CMD_RESP mode). This bit can be used by SW to determine whether it is safe for the CPU to access the EZ memory (without bus wait states (a blocked CPU access) or bus errors being generated). Note that the INTR_TX.BLOCKED and INTR_RX.BLOCKED interrupt causes are used to indicate whether CPU access was actually blocked by externally clocked logic. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1417
SCB8_CMD_RESP_CTRL
24.1.44 SCB8_CMD_RESP_CTRL
Address = 0x40690008 Command/response control Address: 0x40690008 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
BASE_RD_ADDR [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
BASE_WR_ADDR [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 23 : 16
Name BASE_WR_ADDR
7 : 0
BASE_RD_ADDR
Description
I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers. Default Value: 0
I2C/SPI write base address for CMD_RESP mode. At the start of a write transfer this BASE_WR_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1418
SCB8_CMD_RESP_STATUS
24.1.45 SCB8_CMD_RESP_STATUS
Address = 0x4069000C Command/response status Address: 0x4069000C Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
CURR_RD_ADDR [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
W
Name
CURR_WR_ADDR [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
R
None
HW Access
W
W
None
Name
CMD_RESP_EC_BU
SY
CMD_RESP_EC_BU
S_BUSY
None [29:24]
Bits
Name
Description
31
CMD_RESP_EC_BUSY Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reli-
able (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1').
Note:
- When there is no ongoing bus transfer, CMD_RESP_EC_BUSY is '0' (reliable).
- When there is a ongoing bus transfer, CMD_RESP_EC_BUSY is '0' (reliable), when the CUR-
R_RD_ADDR and CURR_WR_ADDR are not being updated by the HW.
- When there is a ongoing bus transfer, CMD_RESP_EC_BUSY is '1' (not reliable), when the
CURR_RD_ADDR or CURR_WR_ADDR are being updated by the HW.
Note that this update lasts one I2C clock cycle, or two SPI clock cycles.
Default Value: Undefined
30
CMD_RE-
Indicates whether there is an ongoing bus transfer to the SCB.
SP_EC_BUS_BUSY
'0': no ongoing bus transfer.
'1': ongoing bus transfer.
For SPI, the field is '1' when slave mode is selected.
For I2C, the field is set to '1' at a I2C START/RESTART. In case of an address match, the field
is set to '0' on a I2C STOP. In case of NO address match, the field is set to '0' after the failing
address match.
Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1419
SCB8_CMD_RESP_STATUS
24.1.45 SCB8_CMD_RESP_STATUS (continued)
23 : 16
CURR_WR_ADDR
7 : 0
CURR_RD_ADDR
I2C/SPI write current address for CMD_RESP mode. HW increments the field after a write access to the memory buffer. However, when the last memory buffer address is reached, the address is NOT incremented (but remains at the maximim memory buffer address). The field is used to determine how many bytes have been written (# bytes = CURR_WR_ADDR - CMD_RESP_CTRL.BASE_WR_ADDR). This field is reliable when there is no bus transfer. This field is potentially unreliable when there is a ongoing bus transfer, i.e when CMD_RESP_EC_BUSY is '0', the field is reliable. Default Value: Undefined
I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However, when the last memory buffer address is reached, the address is NOT incremented (but remains at the maximim memory buffer address). The field is used to determine how many bytes have been read (# bytes = CURR_RD_ADDR CMD_RESP_CTRL.BASE_RD_ADDR). This field is reliable when there is no bus transfer. This field is potentially unreliable when there is a ongoing bus transfer, i.e. when CMD_RESP_EC_BUSY is '0', the field is reliable. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1420
SCB8_SPI_CTRL
24.1.46 SCB8_SPI_CTRL
Address = 0x40690020 SPI control Address: 0x40690020 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:4]
Bits
15
SW Access
HW Access
Name
Bits
23
SW Access
HW Access
Name
Bits
31
SW Access
HW Access
Name
14
13
None
None
None [15:12]
22
21
30
29
None
None
None [31:28]
4
3
2
1
0
RW
RW
RW
None
R
R
R
None
CPOL
CPHA
SELECT_PRE-
CEDE
None
12
11
10
9
8
RW
RW
RW
RW
R
R
R
R
SSEL_PO- SSEL_PO- SSEL_PO- SSEL_PO-
LARITY3
LARITY2
LARITY1
LARITY0
20
19
18
17
16
None
None
None [23:16]
28
27
26
25
24
RW
RW
R
R
SSEL [27:26]
MODE [25:24]
Bits 27 : 26
Name SSEL
25 : 24
MODE
Description
Selects one of the four incoming/outgoing SPI slave select signals: - 0: Slave 0, SSEL[0]. - 1: Slave 1, SSEL[1]. - 2: Slave 2, SSEL[2]. - 3: Slave 3, SSEL[3]. The SCB should be disabled when changes are made to this field. Default Value: 0
Submode of SPI operation (3: Reserved). Default Value: 3
0x0: SPI_MOTOROLA :
SPI Motorola submode.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1421
SCB8_SPI_CTRL
24.1.46
SCB8_SPI_CTRL (continued)
0x1: SPI_TI : SPI Texas Instruments submode.
0x2: SPI_NS : SPI National Semiconducturs submode.
11
SSEL_POLARITY3
Slave select polarity.
Default Value: 0
10
SSEL_POLARITY2
Slave select polarity.
Default Value: 0
9
SSEL_POLARITY1
Slave select polarity.
Default Value: 0
8
SSEL_POLARITY0
Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal 0 (mas-
ter mode) and to the incoming SPI slave select signal (slave mode). For Motorola and National
Semiconductors submodes:
'0': slave select is low/'0' active.
'1': slave select is high/'1' active.
For Texas Instruments submode:
'0': high/'1' active precede/coincide pulse.
'1': low/'0' active precede/coincide pulse.
Default Value: 0
3
CPOL
Indicates the clock polarity. This field, together with the CPHA field, indicates when MOSI data is driven and MISO data is captured: - CPOL is 0: SCLK is 0 when not transmitting data. - CPOL is 1: SCLK is 1 when not transmitting data. Default Value: 0
2
CPHA
Indicates the clock phase. This field, together with the CPOL field, indicates when MOSI data is driven and MISO data is captured: - Motorola mode 0. CPOL is 0, CPHA is 0: MOSI is driven on a falling edge of SCLK. MISO is captured on a rising edge of SCLK. - Motorola mode 1. CPOL is 0, CPHA is 1: MOSI is driven on a rising edge of SCLK. MISO is captured on a falling edge of SCLK. - Motorola mode 2. CPOL is 1, CPHA is 0: MOSI is driven on a rising edge of SCLK. MISO is captured on a falling edge of SCLK. - Motorola mode 3. CPOL is 1, CPHA is 1: MOSI is driven on a falling edge of SCLK. MISO is captured on a rising edge of SCLK. In SPI Motorola submode, all four CPOL/CPHA modes are valid. in SPI NS submode, only CPOL=0 CPHA=0 mode is valid. in SPI TI submode, only CPOL=0 CPHA=1 mode is valid. Default Value: 0
1
SELECT_PRECEDE
Only used in SPI Texas Instruments' submode.
When '1', the data frame start indication is a pulse on the Slave SELECT line that precedes the
transfer of the first data frame bit.
When '0', the data frame start indication is a pulse on the Slave SELECT line that coincides with
the transfer of the first data frame bit.
Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1422
SCB8_SPI_STATUS
24.1.47 SCB8_SPI_STATUS
Address = 0x40690024 SPI status Address: 0x40690024 Retention: Not Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:2]
Bits
15
14
13
12
11
SW Access
R
HW Access
W
Name
CURR_EZ_ADDR [15:8]
Bits
23
22
21
20
19
SW Access
R
HW Access
W
Name
BASE_EZ_ADDR [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
0
R
R
W
W
SPI_EC_BU SY
BUS_BUSY
10
9
8
18
17
16
26
25
24
Bits 23 : 16
Name BASE_EZ_ADDR
15 : 8
CURR_EZ_ADDR
1
SPI_EC_BUSY
0
BUS_BUSY
Description
SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable. Default Value: Undefined
SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1'). Default Value: Undefined
Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether BASE_ADDR and CURR_ADDR are reliable. Default Value: Undefined
SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes, the busy bit is '1', when the slave selection is activated. For TI submode, the busy bit is '1' from the time the preceding/coinciding slave select is activated for the first transmitted data frame, till the last MOSI/MISO bit of the last data frame is transmitted. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1423
SCB8_I2C_CTRL
24.1.48 SCB8_I2C_CTRL
Address = 0x40690060 I2C control Address: 0x40690060 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
RW
RW
RW
RW
None
HW Access
R
R
R
R
R
None
Name
S_NOT_RE ADY_-
DATA_NAC K
S_NOT_RE ADY_ADDR_NACK
S_READY_ DATA_ACK
S_READY_ ADDR_ACK
S_GENERAL_IGNOR
E
None
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
RW
None
HW Access
None
R
None
Name
None
SLAVE_MODE
None [29:24]
Bits
Name
30
SLAVE_MODE
15
S_NOT_READY_-
DATA_NACK
Description
Slave mode enabled ('1') or not ('0'). Default Value: 0
Only used for FIFO mode, NOT EZ or CMD_RESP mode. Functionality is as follows: - 1: a received data element byte the slave is immediately NACK'd when the receiver FIFO is full. - 0: clock stretching is performed (till the receiver FIFO is no longer full). Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1424
SCB8_I2C_CTRL
24.1.48 SCB8_I2C_CTRL (continued)
14
S_NOT_READY_AD-
Only used for FIFO mode, NOT EZ or CMD_RESP mode.
DR_NACK
Functionality is as follows:
- 1: In Active/Sleep mode a received (matching) slave address is immediately NACK'd when the
RX FIFO is full
In DeepSleep power mode when EC_AM = '1' and EC_OP = '0' clk_scb is not avaliable, so the
incoming address will be NACK'd until the clock is avaliable. Once clk_scb is avaliable the ad-
dress ACK will follow S_READY_ADDR_ACK
- 0: in Active/Sleep mode clock stretching is performed when the RX FIFO is full, the strech is
released when the RX FIFO is no longer full.
In DeepSleep power mode when EC_AM = '1' and EC_OP = '0' clk_scb is not avaliable, so the
clocked will be streched on an incoming address until clk_scb is avaliable. After clk_scb is ava-
laible the address ACK will follow S_READY_ADDR_ACK
Default Value: 1
13
S_READY_DATA_ACK When '1', a received data element by the slave is immediately ACK'd when the RX FIFO is not
full. In EZ and CMD_RESP mode, this field should be set to '1'.
When '0' the data must be ACK/NACK'd by the CPU using I2C_S_CMD.S_ACK or I2C_S_C-
MD.S_NACK
Default Value: 1
12
S_READY_ADDR_ACK When '1', a received (matching) slave address is immediately ACK'd when the RX FIFO is not
full. In EZ and CMD_RESP mode, this field should be set to '1'.
When '0' the address must be ACK/NACK'd by the CPU using I2C_S_CMD.S_ACK or I2C_S_C-
MD.S_NACK
Default Value: 1
11
S_GENERAL_IGNORE When '1', a received general call slave address is immediately NACK'd (no ACK or clock stretch-
ing) and treated as a non matching slave address. This is useful for slaves that do not need any
data supplied within the general call structure.
When '0' the general call address is accepted and follows S_READY_ADDR_ACK and
S_NOT_READY_ADDR_NACK
Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1425
SCB8_I2C_STATUS
24.1.49 SCB8_I2C_STATUS
Address = 0x40690064 I2C status Address: 0x40690064 Retention: Not Retained
Bits SW Access HW Access
Name
7
6
5
None
None
None [7:5]
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4 R W
S_READ
3
2
None
None
None [3:2]
12
11
10
R
W
CURR_EZ_ADDR [15:8]
20
19
18
R
W
BASE_EZ_ADDR [23:16]
28
27
26
None
None
None [31:24]
1
0
R
R
W
W
I2C_EC_BU SY
BUS_BUSY
9
8
17
16
25
24
Bits 23 : 16
Name BASE_EZ_ADDR
15 : 8
CURR_EZ_ADDR
4
S_READ
1
I2C_EC_BUSY
Description
I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable. Default Value: Undefined
I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1'). Default Value: Undefined
I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START, REPEATED START, STOP or an address, this field is '0''. Default Value: 0
Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ and CMD_RESP mode). This bit can be used by the CPU to determine whether BASE_ADDR and CURR_ADDR are reliable. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1426
SCB8_I2C_STATUS
24.1.49 SCB8_I2C_STATUS (continued)
0
BUS_BUSY
I2C bus is busy. The bus is considered busy ('1'), from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0'), from the time a STOP is detected. If the SCB is disabled, BUS_BUSY is '0'. After enabling the SCB, it takes time for the BUS_BUSY to detect a busy bus. This time is the maximum high time of the SCL line. For a 100 kHz interface frequency, this maximum high time may last roughly 5 us (half a bit period). For single master systems, BUS_BUSY does not have to be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START (no bus collisions). For multi-master systems, BUS_BUSY can be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START_ON_IDLE (to prevent bus collisions). Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1427
SCB8_INTR_CAUSE
24.1.50 SCB8_INTR_CAUSE
Address = 0x40690E00 Active clocked interrupt signal Address: 0x40690E00 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
R
R
R
R
R
R
HW Access
None
W
W
W
W
W
W
Name
None [7:6]
SPI_EC
I2C_EC
RX
TX
S
M
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
5
SPI_EC
4
I2C_EC
3
RX
2
TX
1
S
0
M
Description
Externally clocked SPI interrupt active ("interrupt_spi_ec"): INTR_SPI_EC_MASKED != 0. Default Value: 0
Externally clock I2C interrupt active ("interrupt_i2c_ec"): INTR_I2C_EC_MASKED != 0. Default Value: 0
Receiver interrupt active ("interrupt_rx"): INTR_RX_MASKED != 0. Default Value: 0
Transmitter interrupt active ("interrupt_tx"): INTR_TX_MASKED != 0. Default Value: 0
Slave interrupt active ("interrupt_slave"): INTR_S_MASKED != 0. Default Value: 0
Master interrupt active ("interrupt_master"): INTR_M_MASKED != 0. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1428
SCB8_INTR_I2C_EC
24.1.51 SCB8_INTR_I2C_EC
Address = 0x40690E80 Externally clocked I2C interrupt request Address: 0x40690E80 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:4]
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4
3
2
1
0
RW1C
RW1C
RW1C
RW1C
A
A
A
A
EZ_READ_ EZ_WRITE
STOP
_STOP
EZ_STOP
WAKE_UP
12
11
10
9
8
None
None
None [15:8]
20
19
18
17
16
None
None
None [23:16]
28
27
26
25
24
None
None
None [31:24]
Bits
Name
3
EZ_READ_STOP
2
EZ_WRITE_STOP
1
EZ_STOP
0
WAKE_UP
Description
STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from. Only set for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'. Default Value: 0
STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address does NOT activate this event. Only set for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'. Default Value: 0
STOP detection. Activated on the end of a every transfer (I2C STOP). Only set for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'. Default Value: 0
Wake up request. Active on incoming slave request (with address match). Only set when EC_AM is '1'. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1429
SCB8_INTR_I2C_EC_MASK
24.1.52 SCB8_INTR_I2C_EC_MASK
Address = 0x40690E88 Externally clocked I2C interrupt mask Address: 0x40690E88 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:4]
4
3
2
1
0
RW
RW
RW
RW
R
R
R
R
EZ_READ_ EZ_WRITE
STOP
_STOP
EZ_STOP
WAKE_UP
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
3
EZ_READ_STOP
2
EZ_WRITE_STOP
1
EZ_STOP
0
WAKE_UP
Description
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1430
SCB8_INTR_I2C_EC_MASKED
24.1.53 SCB8_INTR_I2C_EC_MASKED
Address = 0x40690E8C Externally clocked I2C interrupt masked Address: 0x40690E8C Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:4]
4
3
2
1
0
R
R
R
R
W
W
W
W
EZ_READ_ EZ_WRITE
STOP
_STOP
EZ_STOP
WAKE_UP
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
3
EZ_READ_STOP
2
EZ_WRITE_STOP
1
EZ_STOP
0
WAKE_UP
Description
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1431
SCB8_INTR_SPI_EC
24.1.54 SCB8_INTR_SPI_EC
Address = 0x40690EC0 Externally clocked SPI interrupt request Address: 0x40690EC0 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:4]
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4
3
2
1
0
RW1C
RW1C
RW1C
RW1C
A
A
A
A
EZ_READ_ EZ_WRITE
STOP
_STOP
EZ_STOP
WAKE_UP
12
11
10
9
8
None
None
None [15:8]
20
19
18
17
16
None
None
None [23:16]
28
27
26
25
24
None
None
None [31:24]
Bits
Name
3
EZ_READ_STOP
2
EZ_WRITE_STOP
1
EZ_STOP
0
WAKE_UP
Description
STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from. Only set in EZ and CMD_RESP modes and when EC_OP is '1'. Default Value: 0
STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address does NOT activate this event. Only set in EZ and CMD_RESP modes and when EC_OP is '1'. Default Value: 0
STOP detection. Activated on the end of a every transfer (SPI deselection). Only set in EZ and CMD_RESP mode and when EC_OP is '1'. Default Value: 0
Wake up request. Active on incoming slave request. Only set when EC_AM is '1'. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1432
SCB8_INTR_SPI_EC_MASK
24.1.55 SCB8_INTR_SPI_EC_MASK
Address = 0x40690EC8 Externally clocked SPI interrupt mask Address: 0x40690EC8 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:4]
4
3
2
1
0
RW
RW
RW
RW
R
R
R
R
EZ_READ_ EZ_WRITE
STOP
_STOP
EZ_STOP
WAKE_UP
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
3
EZ_READ_STOP
2
EZ_WRITE_STOP
1
EZ_STOP
0
WAKE_UP
Description
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1433
SCB8_INTR_SPI_EC_MASKED
24.1.56 SCB8_INTR_SPI_EC_MASKED
Address = 0x40690ECC Externally clocked SPI interrupt masked Address: 0x40690ECC Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:4]
4
3
2
1
0
R
R
R
R
W
W
W
W
EZ_READ_ EZ_WRITE
STOP
_STOP
EZ_STOP
WAKE_UP
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
3
EZ_READ_STOP
2
EZ_WRITE_STOP
1
EZ_STOP
0
WAKE_UP
Description
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1434
SCB8_INTR_TX
24.1.57 SCB8_INTR_TX
Address = 0x40690F80 Transmitter interrupt request Address: 0x40690F80 Retention: Not Retained
Bits SW Access HW Access
Name
7 RW1C RW1S
BLOCKED
6
RW1C
RW1S
UNDERFLOW
Bits
15
14
SW Access
HW Access
Name
Bits
23
22
SW Access
HW Access
Name
Bits
31
30
SW Access
HW Access
Name
5 RW1C RW1S OVERFLOW
13
21
29
4 RW1C RW1S
EMPTY
3
2
None
None
None [3:2]
12
11
10
None
None
None [15:8]
20
19
18
None
None
None [23:16]
28
27
26
None
None
None [31:24]
1 RW1C RW1S
0 RW1C RW1S
NOT_FULL TRIGGER
9
8
17
16
25
24
Bits
Name
7
BLOCKED
6
UNDERFLOW
5
OVERFLOW
4
EMPTY
Description
CPU write can not get access to the EZ memory (EZ data access), due to an externally clocked EZ access. Default Value: 0
Attempt to read from an empty TX FIFO. This happens when the SCB is ready to transfer data and EMPTY is '1'. Only used in FIFO mode. Default Value: 0
Attempt to write to a full TX FIFO. Only used in FIFO mode. Default Value: 0
TX FIFO is empty; i.e. it has 0 entries. Only used in FIFO mode. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1435
SCB8_INTR_TX
24.1.57 SCB8_INTR_TX (continued)
1
NOT_FULL
0
TRIGGER
TX FIFO is not full. Dependent on CTRL.BYTE_MODE: BYTE_MODE is '0': # entries != FF_DATA_NR/2. BYTE_MODE is '1': # entries != FF_DATA_NR. Only used in FIFO mode. Default Value: 0
Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL. Only used in FIFO mode. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1436
SCB8_INTR_TX_SET
24.1.58 SCB8_INTR_TX_SET
Address = 0x40690F84 Transmitter interrupt set request Address: 0x40690F84 Retention: Not Retained
Bits SW Access HW Access
Name
7 RW1S
A
BLOCKED
6
RW1S
A
UNDERFLOW
5
RW1S
A
OVERFLOW
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4 RW1S
A
EMPTY
3
2
None
None
None [3:2]
12
11
10
None
None
None [15:8]
20
19
18
None
None
None [23:16]
28
27
26
None
None
None [31:24]
1 RW1S
A
0 RW1S
A
NOT_FULL TRIGGER
9
8
17
16
25
24
Bits
Name
7
BLOCKED
6
UNDERFLOW
5
OVERFLOW
4
EMPTY
1
NOT_FULL
0
TRIGGER
Description
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1437
SCB8_INTR_TX_MASK
24.1.59 SCB8_INTR_TX_MASK
Address = 0x40690F88 Transmitter interrupt mask Address: 0x40690F88 Retention: Retained
Bits SW Access HW Access
Name
7 RW R
BLOCKED
6
RW
R
UNDERFLOW
5
RW
R
OVERFLOW
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4 RW R
EMPTY
3
2
None
None
None [3:2]
12
11
10
None
None
None [15:8]
20
19
18
None
None
None [23:16]
28
27
26
None
None
None [31:24]
1
0
RW
RW
R
R
NOT_FULL TRIGGER
9
8
17
16
25
24
Bits
Name
7
BLOCKED
6
UNDERFLOW
5
OVERFLOW
4
EMPTY
1
NOT_FULL
0
TRIGGER
Description
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1438
SCB8_INTR_TX_MASKED
24.1.60 SCB8_INTR_TX_MASKED
Address = 0x40690F8C Transmitter interrupt masked request Address: 0x40690F8C Retention: Not Retained
Bits SW Access HW Access
Name
7 R W
BLOCKED
6
R
W
UNDERFLOW
5
R
W
OVERFLOW
4 R W
EMPTY
3
2
None
None
None [3:2]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
1
0
R
R
W
W
NOT_FULL TRIGGER
9
8
17
16
25
24
Bits
Name
7
BLOCKED
6
UNDERFLOW
5
OVERFLOW
4
EMPTY
1
NOT_FULL
0
TRIGGER
Description
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1439
SCB8_INTR_RX
24.1.61 SCB8_INTR_RX
Address = 0x40690FC0 Receiver interrupt request Address: 0x40690FC0 Retention: Not Retained
Bits SW Access HW Access
Name
7 RW1C RW1S
BLOCKED
6
RW1C
RW1S
UNDERFLOW
Bits
15
14
SW Access
HW Access
Name
Bits
23
22
SW Access
HW Access
Name
Bits
31
30
SW Access
HW Access
Name
5 RW1C RW1S OVERFLOW
13
21
29
4 None None
None
3 RW1C RW1S
FULL
12
11
None
None
None [15:8]
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
2 RW1C RW1S NOT_EMP-
TY 10
18
26
1 None None None
9
17
25
0 RW1C RW1S TRIGGER
8
16
24
Bits
Name
7
BLOCKED
6
UNDERFLOW
5
OVERFLOW
3
FULL
Description
CPU read transfer can not get access to the EZ memory (EZ_DATA accesses), due to an externally clocked EZ access. Default Value: 0
Attempt to read from an empty RX FIFO. Only used in FIFO mode. Default Value: 0
Attempt to write to a full RX FIFO. Note: in I2C mode, the OVERFLOW is set when a data frame is received and the RX FIFO is full, independent of whether it is ACK'd or NACK'd. Only used in FIFO mode. Default Value: 0
RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.BYTE_MODET: BYTE_MODE is '0': # entries == FF_DATA_NR/2. BYTE_MODE is '1': # entries == FF_DATA_NR. Only used in FIFO mode. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1440
SCB8_INTR_RX
24.1.61 SCB8_INTR_RX (continued)
2
NOT_EMPTY
0
TRIGGER
RX FIFO is not empty. Only used in FIFO mode. Default Value: 0
More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in SCB_RX_FIFO_CTL. Only used in FIFO mode. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1441
SCB8_INTR_RX_SET
24.1.62 SCB8_INTR_RX_SET
Address = 0x40690FC4 Receiver interrupt set request Address: 0x40690FC4 Retention: Not Retained
Bits SW Access HW Access
Name
7 RW1S
A
BLOCKED
6
RW1S
A
UNDERFLOW
5
RW1S
A
OVERFLOW
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4 None None
None
3 RW1S
A
FULL
12
11
None
None
None [15:8]
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
2 RW1S
A NOT_EMP-
TY 10
18
26
1 None None None
9
17
25
0 RW1S
A TRIGGER
8
16
24
Bits
Name
7
BLOCKED
6
UNDERFLOW
5
OVERFLOW
3
FULL
2
NOT_EMPTY
0
TRIGGER
Description
Write with '1' to set corresponding bit in interrupt status register. Default Value: 0
Write with '1' to set corresponding bit in interrupt status register. Default Value: 0
Write with '1' to set corresponding bit in interrupt status register. Default Value: 0
Write with '1' to set corresponding bit in interrupt status register. Default Value: 0
Write with '1' to set corresponding bit in interrupt status register. Default Value: 0
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1442
SCB8_INTR_RX_MASK
24.1.63 SCB8_INTR_RX_MASK
Address = 0x40690FC8 Receiver interrupt mask Address: 0x40690FC8 Retention: Retained
Bits SW Access HW Access
Name
7 RW R
BLOCKED
6
RW
R
UNDERFLOW
5
RW
R
OVERFLOW
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4 None None
None
3 RW R
FULL
12
11
None
None
None [15:8]
20
19
None
None
None [23:16]
28
27
None
None
None [31:24]
2 RW R NOT_EMPTY 10
18
26
1 None None None
9
17
25
0 RW R TRIGGER
8
16
24
Bits
Name
7
BLOCKED
6
UNDERFLOW
5
OVERFLOW
3
FULL
2
NOT_EMPTY
0
TRIGGER
Description
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1443
SCB8_INTR_RX_MASKED
24.1.64 SCB8_INTR_RX_MASKED
Address = 0x40690FCC Receiver interrupt masked request Address: 0x40690FCC Retention: Not Retained
Bits SW Access HW Access
Name
7 R W
BLOCKED
6
R
W
UNDERFLOW
5
R
W
OVERFLOW
4 None None
None
3 R W
FULL
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2 R W NOT_EMPTY 10
18
26
1 None None None
9
17
25
0 R W TRIGGER 8
16
24
Bits
Name
7
BLOCKED
6
UNDERFLOW
5
OVERFLOW
3
FULL
2
NOT_EMPTY
0
TRIGGER
Description
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1444
Section H:Peripheral Group 9
This section encompasses the following chapters: Analog Reference Block (AREF) Registers chapter on page 1446 Continuous-Time Block Mini Registers chapter on page 1450 Continuous-Time DAC Registers chapter on page 1481 SAR ADC Registers chapter on page 1492
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1445
25 Analog Reference Block (AREF) Registers
This section discusses the Analog Reference Block (AREF) registers. It lists all the registers in mapping tables, in address order.
25.1 Register Details
Register PASS_AREF_AREF_CTRL
0x411F0E00
Address
Description Global AREF control
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1446
PASS_AREF_AREF_CTRL
25.1.1 PASS_AREF_AREF_CTRL
Address = 0x411F0E00 Global AREF control Address: 0x411F0E00 Retention: Retained
Bits SW Access HW Access
Name
7
RW
R
CTB_IPTAT_SCALE
6
5
4
RW
R
AREF_RMB [6:4]
3
2
RW
R
AREF_BIAS_SCALE [3:2]
1 None None
None
Bits
15
14
13
12
11
10
9
SW Access
RW
HW Access
R
Name
CTB_IPTAT_REDIRECT [15:8]
Bits SW Access HW Access
Name
23
22
None
None
None [23:22]
21
20
RW
R
VREF_SEL [21:20]
19
RW
R
CLOCK_PU MP_PERI_-
SEL
18
17
None
None
None [18:17]
Bits
31
30
29
28
27
SW Access
RW
RW
RW
HW Access
R
R
R
Name
ENABLED
DEEPSLEEP_ON
DEEPSLEEP_MODE [29:28]
26
25
None
None
None [27:24]
0 RW R AREF_MODE
8
16 RW R IZTAT_SEL
24
Bits
Name
31
ENABLED
30
DEEPSLEEP_ON
29 : 28
DEEPSLEEP_MODE
Description
Disable AREF Default Value: 0
- 0: AREF IP disabled/off during DeepSleep power mode - 1: AREF IP remains enabled during DeepSleep power mode (if ENABLED=1) Default Value: 0
AREF DeepSleep Operation Modes (only applies if DEEPSLEEP_ON = 1) Default Value: 0
0x0: OFF : All blocks "OFF" in DeepSleep
0x1: IPTAT : IPTAT bias generator "ON" in DeepSleep (used for fast AREF wakeup only: IPTAT outputs not available)
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1447
PASS_AREF_AREF_CTRL
25.1.1
21 : 20
19 16 15 : 8 7 6 : 4
PASS_AREF_AREF_CTRL (continued)
VREF_SEL
CLOCK_PUMP_PERI_SEL IZTAT_SEL
CTB_IPTAT_REDIRECT
CTB_IPTAT_SCALE AREF_RMB
0x2: IPTAT_IZTAT : IPTAT bias generator and outputs "ON" in DeepSleep (used for biasing the CTBm with a PTAT current only in deep sleep) *Note that this mode also requires that the CTB_IPTAT_REDIRECT be set if the CTBm opamp is to operate in DeepSleep
0x3: IPTAT_IZTAT_VREF : IPTAT, VREF, and IZTAT generators "ON" in DeepSleep. This mode provides identical AREF functionality in DeepSleep as in the Active mode.
bandgap voltage select control Default Value: 0
0x0: SRSS : Use 0.8V Vref from SRSS
0x1: LOCAL : Use locally generated Vref
0x2: EXTERNAL : Use externally supplied Vref (aref_ext_vref)
CTBm charge pump clock source select. This field has nothing to do with the AREF. 0: Use the dedicated pump clock from SRSS (default) 1: Use one of the CLK_PERI dividers Default Value: 0
iztat current select control Default Value: 0
0x0: SRSS : Use 250nA IZTAT from SRSS
0x1: LOCAL : Use locally generated 250nA
Re-direct the CTB IPTAT output current. This can be used to reduce amplifier bias glitches during power mode transitions (for PSoC4A/B DSAB backwards compatibility). 0: Opamp.IPTAT = AREF.IPTAT and Opamp.IZTAT= AREF.IZTAT 1: Opamp.IPTAT = HiZ and Opamp.IZTAT= AREF.IPTAT *Note that in Deep Sleep, the AREF IZTAT and/or IPTAT currents can be disabled and therefore the corresponding Opamp.IZTAT/IPTAT will be HiZ. Default Value: 0
CTB IPTAT current scaler. This bit must be set in order to operate the CTB amplifiers in the lowest power mode. This bit is chip-wide (controls all CTB amplifiers). 0: 1uA 1: 100nA Default Value: 0
AREF control signals (RMB). Bit 0: Manual VBG startup circuit enable 0: normal VBG startup circuit operation 1: VBG startup circuit is forced "always on" Bit 1: Manual disable of IPTAT2 DAC 0: normal IPTAT2 DAC operation 1: PTAT2 DAC is disabled while VBG startup is active Bit 2: Manual enable of VBG offset correction DAC 0: normal VBG offset correction DAC operation 1: VBG offset correction DAC is enabled while VBG startup is active Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1448
PASS_AREF_AREF_CTRL
25.1.1
3 : 2
0
PASS_AREF_AREF_CTRL (continued)
AREF_BIAS_SCALE AREF_MODE
BIAS Current Control for all AREF Amplifiers. (These are risk mitigation bits that should not be touched by the customer: the impact on IDDA/noise/startup still needs to be characterized) 0: 125nA (reduced bias: reduction in total AREF IDDA, higher noise and longer startup times) 1: 250nA ("default" setting to meet bandgap performance (noise/startup) and IDDA specifications) 2: 375nA (increased bias: increase in total AREF IDDA, lower noise and shorter startup times) 3: 500nA (further increased bias: increase in total AREF IDDA, lower noise and shorter startup times) Default Value: 0
Control bit to trade off AREF settling and noise performance Default Value: 0
0x0: NORMAL : Nominal noise normal startup mode (meets normal mode settling and noise specifications)
0x1: FAST_START : High noise fast startup mode (meets fast mode settling and noise specifications)
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1449
26 Continuous-Time Block Mini Registers
This section discusses the Continuous-Time Block Mini (CTBm) registers. It lists all the registers in mapping tables, in address order.
26.1 Register Details
Register CTBM0_CTB_CTRL CTBM0_OA_RES0_CTRL CTBM0_OA_RES1_CTRL CTBM0_COMP_STAT CTBM0_INTR CTBM0_INTR_SET CTBM0_INTR_MASK CTBM0_INTR_MASKED CTBM0_OA0_SW CTBM0_OA0_SW_CLEAR CTBM0_OA1_SW CTBM0_OA1_SW_CLEAR CTBM0_CTD_SW CTBM0_CTD_SW_CLEAR CTBM0_CTB_SW_DS_CTRL CTBM0_CTB_SW_SQ_CTRL CTBM0_CTB_SW_STATUS CTBM0_OA0_OFFSET_TRIM CTBM0_OA0_SLOPE_OFFSET_TRIM CTBM0_OA0_COMP_TRIM CTBM0_OA1_OFFSET_TRIM CTBM0_OA1_SLOPE_OFFSET_TRIM CTBM0_OA1_COMP_TRIM PASS_INTR_CAUSE
Address 0x41100000 0x41100004 0x41100008 0x4110000C 0x41100020 0x41100024 0x41100028 0x4110002C 0x41100080 0x41100084 0x41100088 0x4110008C 0x411000A0 0x411000A4 0x411000C0 0x411000C4 0x411000C8 0x41100F00 0x41100F04 0x41100F08 0x41100F0C 0x41100F10 0x41100F14 0x411F0000
Description global CTB and power control Opamp0 and resistor0 control Opamp1 and resistor1 control Comparator status Interrupt request register Interrupt request set register Interrupt request mask Interrupt request masked Opamp0 switch control Opamp0 switch control clear Opamp1 switch control Opamp1 switch control clear CTDAC connection switch control CTDAC connection switch control clear CTB bus switch control CTB bus switch Sar Sequencer control CTB bus switch control status Opamp0 trim control Opamp0 trim control Opamp0 trim control Opamp1 trim control Opamp1 trim control Opamp1 trim control Interrupt cause register
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1450
CTBM0_CTB_CTRL
26.1.1 CTBM0_CTB_CTRL
Address = 0x41100000 global CTB and power control Address: 0x41100000 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
RW
None
HW Access
R
R
None
Name
ENABLED
DEEPSLEEP_ON
None
Bits
Name
31
ENABLED
30
DEEPSLEEP_ON
Description
- 0: CTB IP disabled (put analog in power down, open all switches) - 1: CTB IP enabled Default Value: 0
- 0: CTB IP disabled off during DeepSleep power mode - 1: CTB IP remains enabled during DeepSleep power mode (if ENABLED=1) Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1451
CTBM0_OA_RES0_CTRL
26.1.2
CTBM0_OA_RES0_CTRL (continued)
26.1.2 CTBM0_OA_RES0_CTRL
Address = 0x41100004 Opamp0 and resistor0 control Address: 0x41100004 Retention: Retained
Bits SW Access HW Access
Name
7
6
RW
RW
R
R
OA0_DSI_L EVEL
OA0_BYPASS_DSI_
SYNC
5 RW R
OA0_HYST _EN
4 RW R
OA0_COMP_EN
3
RW
R
OA0_DRIV E_STR_-
SEL
Bits SW Access HW Access
Name
15
14
13
12
11
None
RW
RW
None
R
R
None [15:13]
OA0_- OA0_PUMP
BOOST_EN
_EN
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
0
RW
R
OA0_PWR_MODE [2:0]
10 None None None
18
9
8
RW
R
OA0_COMPINT [9:8]
17
16
26
25
24
Bits 12 11 9 : 8
Name OA0_BOOST_EN OA0_PUMP_EN OA0_COMPINT
Description
Reserved. Keep this bit at the default value. Default Value: 0
Opamp0 pump enable Default Value: 0
Opamp0 comparator edge detect for interrupt and pulse mode of DSI (trigger) Default Value: 0
0x0: DISABLE : Disabled, no interrupts will be detected
0x1: RISING : Rising edge
0x2: FALLING : Falling edge
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1452
CTBM0_OA_RES0_CTRL
26.1.2
7
6 5 4 3 2 : 0
CTBM0_OA_RES0_CTRL (continued)
OA0_DSI_LEVEL
OA0_BYPASS_DSI_SYNC OA0_HYST_EN OA0_COMP_EN OA0_DRIVE_STR_SEL
OA0_PWR_MODE
0x3: BOTH : Both rising and falling edges
Opamp0 comparator DSI (trigger) out level : 0=pulse, each time an edge is detected (see OA0_COMPINT) a pulse is sent out on DSI 1=level, DSI output is a synchronized version of the comparator output Default Value: 0
Opamp0 bypass comparator output synchronization for DSI (trigger) output: 0=synchronize (level or pulse), 1=bypass (output async) Default Value: 0
Opamp0 hysteresis enable (10mV) Default Value: 0
Opamp0 comparator enable Default Value: 0
Opamp0 output strength select 0=1x, 1=10x This setting sets specific requirements for OA0_BOOST_EN and OA0_COMP_TRIM Default Value: 0
Opamp0 power level, assumes Cload=15pF for the (internal only) 1x driver or 50pF for the (external) 10x driver Default Value: 0
0x0: OFF : Off
0x1: LOW : Low power mode (IDD: 350uA, GBW: 1MHz for both 1x/10x)
0x2: MEDIUM : Medium power mode (IDD: 600uA, GBW: 3MHz for 1x & 2.5MHz for 10x)
0x3: HIGH : High power mode for highest GBW (IDD: 1500uA, GBW: 8MHz for 1x & 6MHz for 10x)
0x4: RESERVED : Reserved
0x5: PS_LOW : Power Saver Low power mode (IDD: ~20uA with 1uA bias from AREF, GBW: ~100kHz for 1x/ 10x, offset correcting IDAC is disabled)
0x6: PS_MEDIUM : Power Saver Medium power mode (IDD: ~40uA with 1uA bias from AREF, GBW: ~100kHz for 1x/10x, offset correcting IDAC is enabled)
0x7: PS_HIGH : Power Saver Medium power mode (IDD: ~60uA with 1uA bias from AREF, GBW: ~200kHz for 1x/10x, offset correcting IDAC is enabled)
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1453
CTBM0_OA_RES1_CTRL
26.1.3
CTBM0_OA_RES1_CTRL (continued)
26.1.3 CTBM0_OA_RES1_CTRL
Address = 0x41100008 Opamp1 and resistor1 control Address: 0x41100008 Retention: Retained
Bits SW Access HW Access
Name
7
6
RW
RW
R
R
OA1_DSI_L EVEL
OA1_BYPASS_DSI_
SYNC
5 RW R
OA1_HYST _EN
4 RW R
OA1_COMP_EN
3
RW
R
OA1_DRIV E_STR_-
SEL
Bits SW Access HW Access
Name
15
14
13
12
11
None
RW
RW
None
R
R
None [15:13]
OA1_- OA1_PUMP
BOOST_EN
_EN
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
0
RW
R
OA1_PWR_MODE [2:0]
10 None None None
18
9
8
RW
R
OA1_COMPINT [9:8]
17
16
26
25
24
Bits 12 11 9 : 8
Name OA1_BOOST_EN OA1_PUMP_EN OA1_COMPINT
Description
Reserved. Keep this bit at the default value. Default Value: 0
Opamp1 pump enable Default Value: 0
Opamp1 comparator edge detect for interrupt and pulse mode of DSI (trigger) Default Value: 0
0x0: DISABLE : Disabled, no interrupts will be detected
0x1: RISING : Rising edge
0x2: FALLING : Falling edge
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1454
CTBM0_OA_RES1_CTRL
26.1.3
7
6 5 4 3 2 : 0
CTBM0_OA_RES1_CTRL (continued)
OA1_DSI_LEVEL
OA1_BYPASS_DSI_SYNC OA1_HYST_EN OA1_COMP_EN OA1_DRIVE_STR_SEL
OA1_PWR_MODE
0x3: BOTH : Both rising and falling edges
Opamp1 comparator DSI (trigger) out level : 0=pulse, each time an edge is detected (see OA1_COMPINT) a pulse is sent out on DSI 1=level, DSI output is a synchronized version of the comparator output Default Value: 0
Opamp1 bypass comparator output synchronization for DSI output: 0=synchronize, 1=bypass Default Value: 0
Opamp1 hysteresis enable (10mV) Default Value: 0
Opamp1 comparator enable Default Value: 0
Opamp1 output strength select 0=1x, 1=10x This setting sets specific requirements for OA1_BOOST_EN and OA1_COMP_TRIM Default Value: 0
Opamp1 power level: see description of OA0_PWR_MODE Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1455
CTBM0_COMP_STAT
26.1.4
CTBM0_COMP_STAT (continued)
26.1.4 CTBM0_COMP_STAT
Address = 0x4110000C Comparator status Address: 0x4110000C Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
R
HW Access
None
W
Name
None [7:1]
OA0_COMP
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
R
HW Access
None
W
Name
None [23:17]
OA1_COMP
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
16
OA1_COMP
0
OA0_COMP
Description
Opamp1 current comparator status Default Value: 0
Opamp0 current comparator status Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1456
CTBM0_INTR
26.1.5 CTBM0_INTR
Address = 0x41100020 Interrupt request register Address: 0x41100020 Retention: Retained
Bits
7
6
SW Access
HW Access
Name
Bits
15
14
SW Access
HW Access
Name
Bits
23
22
SW Access
HW Access
Name
Bits
31
30
SW Access
HW Access
Name
5
4
3
None
None
None [7:2]
13
12
11
None
None
None [15:8]
21
20
19
None
None
None [23:16]
29
28
27
None
None
None [31:24]
2
1
0
RW1C
RW1C
RW1S
RW1S
COMP1
COMP0
10
9
8
18
17
16
26
25
24
Bits
Name
1
COMP1
0
COMP0
Description
Comparator 1 Interrupt: hardware sets this interrupt when comparator 1 triggers. Write with '1' to clear bit. Default Value: 0
Comparator 0 Interrupt: hardware sets this interrupt when comparator 0 triggers. Write with '1' to clear bit. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1457
CTBM0_INTR_SET
26.1.6
CTBM0_INTR_SET (continued)
26.1.6 CTBM0_INTR_SET
Address = 0x41100024 Interrupt request set register Address: 0x41100024 Retention: Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:2]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
0
RW1S
RW1S
A
A
COMP1_SE COMP0_SE
T
T
10
9
8
18
17
16
26
25
24
Bits
Name
1
COMP1_SET
0
COMP0_SET
Description
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1458
CTBM0_INTR_MASK
26.1.7 CTBM0_INTR_MASK
Address = 0x41100028 Interrupt request mask Address: 0x41100028 Retention: Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:2]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
0
RW
RW
R
R
COMP1_M COMP0_M
ASK
ASK
10
9
8
18
17
16
26
25
24
Bits
Name
1
COMP1_MASK
0
COMP0_MASK
Description
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1459
CTBM0_INTR_MASKED
26.1.8
CTBM0_INTR_MASKED (continued)
26.1.8 CTBM0_INTR_MASKED
Address = 0x4110002C Interrupt request masked Address: 0x4110002C Retention: Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:2]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
0
R
R
W
W
COMP1_M COMP0_M
ASKED
ASKED
10
9
8
18
17
16
26
25
24
Bits
Name
1
COMP1_MASKED
0
COMP0_MASKED
Description
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1460
CTBM0_OA0_SW
26.1.9 CTBM0_OA0_SW
Address = 0x41100080 Opamp0 switch control Address: 0x41100080 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:4]
Bits SW Access HW Access
Name
15
14
13
None
RW1S
None
RW1C
None
OA0M_A81
Bits SW Access HW Access
Name
23
22
None
None
None [23:22]
21 RW1S RW1C OA0O_D81
Bits
31
30
29
SW Access
HW Access
Name
4
3
2
RW1S
RW1S
RW1C
RW1C
OA0P_A30 OA0P_A20
12
11
10
None
None
None [13:9]
20
19
None
None
None [20:19]
18 RW1S RW1C OA0O_D51
28
27
26
None
None
None [31:24]
1 None None None
0 RW1S RW1C OA0P_A00
9
8
RW1S
RW1C
OA0M_A11
17
16
None
None
None [17:16]
25
24
Bits
Name
21
OA0O_D81
18
OA0O_D51
14
OA0M_A81
8
OA0M_A11
3
OA0P_A30
2
OA0P_A20
0
OA0P_A00
Description
Opamp0 output switch to short 1x with 10x drive Default Value: 0
Opamp0 output sarbus0 (ctbbus2 in CTB) Default Value: 0
Opamp0 negative terminal Opamp0 output Default Value: 0
Opamp0 negative terminal P1 Default Value: 0
Opamp0 positive terminal ctbbus0 Default Value: 0
Opamp0 positive terminal P0 Default Value: 0
Opamp0 positive terminal amuxbusa Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1461
CTBM0_OA0_SW_CLEAR
26.1.10 CTBM0_OA0_SW_CLEAR (continued)
26.1.10 CTBM0_OA0_SW_CLEAR
Address = 0x41100084 Opamp0 switch control clear Address: 0x41100084 Retention: Retained
Bits
7
SW Access
HW Access
Name
6
5
None
None
None [7:4]
4
3
2
RW1C
RW1C
A
A
OA0P_A30 OA0P_A20
Bits SW Access HW Access
Name
15
14
13
None
RW1C
None
A
None
OA0M_A81
12
11
10
None
None
None [13:9]
Bits SW Access HW Access
Name
23
22
None
None
None [23:22]
21 RW1C
A OA0O_D81
20
19
None
None
None [20:19]
18 RW1C
A OA0O_D51
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
1 None None None
0 RW1C
A OA0P_A00
9
8
RW1C
A
OA0M_A11
17
16
None
None
None [17:16]
25
24
Bits
Name
21
OA0O_D81
18
OA0O_D51
14
OA0M_A81
8
OA0M_A11
3
OA0P_A30
2
OA0P_A20
0
OA0P_A00
Description
see corresponding bit in OA0_SW Default Value: 0
see corresponding bit in OA0_SW Default Value: 0
see corresponding bit in OA0_SW Default Value: 0
see corresponding bit in OA0_SW Default Value: 0
see corresponding bit in OA0_SW Default Value: 0
see corresponding bit in OA0_SW Default Value: 0
see corresponding bit in OA0_SW Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1462
CTBM0_OA1_SW
26.1.11 CTBM0_OA1_SW (continued)
26.1.11 CTBM0_OA1_SW
Address = 0x41100088 Opamp1 switch control Address: 0x41100088 Retention: Retained
Bits SW Access HW Access
Name
7 RW1S RW1C OA1P_A73
6
5
None
None
None [6:5]
4 RW1S RW1C OA1P_A43
3
2
None
None
None [3:2]
1 RW1S RW1C OA1P_A13
0 RW1S RW1C OA1P_A03
Bits SW Access HW Access
Name
15
14
13
None
RW1S
None
RW1C
None
OA1M_A82
12
11
10
None
None
None [13:9]
9
8
RW1S
RW1C
OA1M_A22
Bits SW Access HW Access
Name
23
22
None
None
None [23:22]
21 RW1S RW1C OA1O_D82
20 None None None
19 RW1S RW1C OA1O_D62
18 RW1S RW1C OA1O_D52
17
16
None
None
None [17:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
21
OA1O_D82
19
OA1O_D62
18
OA1O_D52
14
OA1M_A82
8
OA1M_A22
7
OA1P_A73
4
OA1P_A43
Description
Opamp1 output switch to short 1x with 10x drive Default Value: 0
Opamp1 output sarbus1 (ctbbus3 in CTB) Default Value: 0
Opamp1 output sarbus0 (ctbbus2 in CTB) Default Value: 0
Opamp1 negative terminal Opamp1 output Default Value: 0
Opamp1 negative terminal P4 Default Value: 0
Opamp1 positive terminal to vref1 Default Value: 0
Opamp1 positive terminal ctbbus1 Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1463
26.1.11 CTBM0_OA1_SW (continued)
1
OA1P_A13
0
OA1P_A03
Opamp1 positive terminal P5 Default Value: 0
Opamp1 positive terminal amuxbusb Default Value: 0
CTBM0_OA1_SW
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1464
CTBM0_OA1_SW_CLEAR
26.1.12 CTBM0_OA1_SW_CLEAR
Address = 0x4110008C Opamp1 switch control clear Address: 0x4110008C Retention: Retained
Bits SW Access HW Access
Name
7 RW1C
A OA1P_A73
6
5
None
None
None [6:5]
4 RW1C
A OA1P_A43
3
2
None
None
None [3:2]
1 RW1C
A OA1P_A13
0 RW1C
A OA1P_A03
Bits SW Access HW Access
Name
15
14
13
None
RW1C
None
A
None
OA1M_A82
12
11
10
None
None
None [13:9]
9
8
RW1C
A
OA1M_A22
Bits SW Access HW Access
Name
23
22
None
None
None [23:22]
21 RW1C
A OA1O_D82
20 None None None
19 RW1C
A OA1O_D62
18 RW1C
A OA1O_D52
17
16
None
None
None [17:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
21
OA1O_D82
19
OA1O_D62
18
OA1O_D52
14
OA1M_A82
8
OA1M_A22
7
OA1P_A73
4
OA1P_A43
1
OA1P_A13
Description
see corresponding bit in OA1_SW Default Value: 0
see corresponding bit in OA1_SW Default Value: 0
see corresponding bit in OA1_SW Default Value: 0
see corresponding bit in OA1_SW Default Value: 0
see corresponding bit in OA1_SW Default Value: 0
see corresponding bit in OA1_SW Default Value: 0
see corresponding bit in OA1_SW Default Value: 0
see corresponding bit in OA1_SW Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1465
26.1.12 CTBM0_OA1_SW_CLEAR (continued)
0
OA1P_A03
see corresponding bit in OA1_SW Default Value: 0
CTBM0_OA1_SW_CLEAR
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1466
CTBM0_CTD_SW
26.1.13 CTBM0_CTD_SW
Address = 0x411000A0 CTDAC connection switch control Address: 0x411000A0 Retention: Retained
Bits SW Access HW Access
Name
7
6
None
None
None [7:6]
5
4
RW1S
RW1S
RW1C
RW1C
CTDS_COR CTDS_CRS
3
2
None
None
None [3:2]
1 RW1S RW1C CTDD_CRD
0 None None None
Bits SW Access HW Access
Name
15 RW1S RW1C
14 RW1S RW1C
13 RW1S RW1C
12 RW1S RW1C
CTDH_ILR CTDH_CIS CTDH_CA0 CTDH_CHD
11 None None
None
10 RW1S RW1C
CTDH_COB
9
RW1S
RW1C
CTDO_COS
8 RW1S RW1C
CTDO_C6H
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
15
CTDH_ILR
14
CTDH_CIS
13
CTDH_CA0
12
CTDH_CHD
10
CTDH_COB
9
CTDO_COS
8
CTDO_C6H
Description
Hold capacitor leakage reduction (drive other side of CIS to capacitor voltage) Default Value: 0
Hold capacitor isolation (from all the other switches) Default Value: 0
Hold capacitor to opamp input Default Value: 0
Hold capacitor connect Default Value: 0
Drive the CTDAC output with CTBM 1x output during hold mode in Sample and Hold operation Default Value: 0
ctdvout to Hold capacitor (Sample switch). Note this switch will temporarily be opened for deglitching if CTDAC.DEGLITCH_COS is set Default Value: 0
P6 pin to Hold capacitor Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1467
26.1.13 CTBM0_CTD_SW (continued)
5
CTDS_COR
4
CTDS_CRS
1
CTDD_CRD
ctdvout to opamp input Default Value: 0
ctdrefsense to opamp input Default Value: 0
CTDAC Reference opamp output to ctdrefdrive Default Value: 0
CTBM0_CTD_SW
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1468
CTBM0_CTD_SW_CLEAR
26.1.14 CTBM0_CTD_SW_CLEAR
Address = 0x411000A4 CTDAC connection switch control clear Address: 0x411000A4 Retention: Retained
Bits SW Access HW Access
Name
7
6
None
None
None [7:6]
5
4
RW1C
RW1C
A
A
CTDS_COR CTDS_CRS
3
2
None
None
None [3:2]
1 RW1C
A CTDD_CRD
0 None None None
Bits SW Access HW Access
Name
15 RW1C
A
14 RW1C
A
13 RW1C
A
12 RW1C
A
CTDH_ILR CTDH_CIS CTDH_CA0 CTDH_CHD
11 None None
None
10 RW1C
A
CTDH_COB
9
RW1C
A
CTDO_COS
8 RW1C
A
CTDO_C6H
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
15
CTDH_ILR
14
CTDH_CIS
13
CTDH_CA0
12
CTDH_CHD
10
CTDH_COB
9
CTDO_COS
8
CTDO_C6H
Description
see corresponding bit in CTD_SW Default Value: 0
see corresponding bit in CTD_SW Default Value: 0
see corresponding bit in CTD_SW Default Value: 0
see corresponding bit in CTD_SW Default Value: 0
see corresponding bit in CTD_SW Default Value: 0
see corresponding bit in CTD_SW Default Value: 0
see corresponding bit in CTD_SW Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1469
26.1.14 CTBM0_CTD_SW_CLEAR (continued)
5
CTDS_COR
4
CTDS_CRS
1
CTDD_CRD
see corresponding bit in CTD_SW Default Value: 0
see corresponding bit in CTD_SW Default Value: 0
see corresponding bit in CTD_SW Default Value: 0
CTBM0_CTD_SW_CLEAR
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1470
CTBM0_CTB_SW_DS_CTRL
26.1.15 CTBM0_CTB_SW_DS_CTRL
Address = 0x411000C0 CTB bus switch control Address: 0x411000C0 Retention: Retained
Bits
7
6
5
4
3
2
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
SW Access
HW Access
Name
14
13
None
None
None [15:12]
12
11
10
RW
RW
R
R
P3_DS_C- P2_DS_C-
TRL23
TRL23
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
SW Access
RW
None
HW Access
R
None
Name
CTD_COS_DS
_CTRL
None [30:24]
1
0
9
8
None
None
None
17
16
25
24
Bits
Name
Description
31
CTD_COS_DS_CTRL
Hold capacitor Sample switch (COS)
Default Value: 0
11
P3_DS_CTRL23
for P33, D52, D62 (dsi_out[3]) Default Value: 0
10
P2_DS_CTRL23
for P22, D51 (dsi_out[2]) Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1471
CTBM0_CTB_SW_SQ_CTRL
26.1.16 CTBM0_CTB_SW_SQ_CTRL
Address = 0x411000C4 CTB bus switch Sar Sequencer control Address: 0x411000C4 Retention: Retained
Bits
7
6
5
4
3
2
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
SW Access
HW Access
Name
14
13
None
None
None [15:12]
12
11
10
RW
RW
R
R
P3_SQ_C- P2_SQ_C-
TRL23
TRL23
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
1
0
9
8
None
None
None
17
16
25
24
Bits
Name
11
P3_SQ_CTRL23
10
P2_SQ_CTRL23
Description
for D52, D62 Default Value: 0
for D51 Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1472
CTBM0_CTB_SW_STATUS
26.1.17 CTBM0_CTB_SW_STATUS
Address = 0x411000C8 CTB bus switch control status Address: 0x411000C8 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
R
R
R
None
HW Access
W
W
W
W
None
Name
CTD_COS_ST
AT
OA1O_D62 _STAT
OA1O_D52 _STAT
OA0O_D51 _STAT
None
Bits
Name
31
CTD_COS_STAT
30
OA1O_D62_STAT
29
OA1O_D52_STAT
28
OA0O_D51_STAT
Description
see COS bit in CTD_SW Default Value: 0
see OA1O_D62 bit in OA1_SW Default Value: 0
see OA1O_D52 bit in OA1_SW Default Value: 0
see OA0O_D51 bit in OA0_SW Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1473
CTBM0_OA0_OFFSET_TRIM
26.1.18 CTBM0_OA0_OFFSET_TRIM
Address = 0x41100F00 Opamp0 trim control Address: 0x41100F00 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:6]
OA0_OFFSET_TRIM [5:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 5 : 0
Name OA0_OFFSET_TRIM
Description
Opamp0 offset trim Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1474
CTBM0_OA0_SLOPE_OFFSET_TRIM
26.1.19 CTBM0_OA0_SLOPE_OFFSET_TRIM
Address = 0x41100F04 Opamp0 trim control Address: 0x41100F04 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:6]
OA0_SLOPE_OFFSET_TRIM [5:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 5 : 0
Name
OA0_SLOPE_OFFSET_TRIM
Description
Opamp0 slope offset drift trim Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1475
CTBM0_OA0_COMP_TRIM
26.1.20 CTBM0_OA0_COMP_TRIM
Address = 0x41100F08 Opamp0 trim control Address: 0x41100F08 Retention: Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:2]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
0
RW
R
OA0_COMP_TRIM [1:0]
10
9
8
18
17
16
26
25
24
Bits 1 : 0
Name OA0_COMP_TRIM
Description
Opamp0 Compensation Capacitor Trim. Value depends on the drive strength setting - 1x mode: set to 01; 10x mode: set to 11 Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1476
CTBM0_OA1_OFFSET_TRIM
26.1.21 CTBM0_OA1_OFFSET_TRIM
Address = 0x41100F0C Opamp1 trim control Address: 0x41100F0C Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:6]
OA1_OFFSET_TRIM [5:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 5 : 0
Name OA1_OFFSET_TRIM
Description
Opamp1 offset trim Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1477
CTBM0_OA1_SLOPE_OFFSET_TRIM
26.1.22 CTBM0_OA1_SLOPE_OFFSET_TRIM
Address = 0x41100F10 Opamp1 trim control Address: 0x41100F10 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:6]
OA1_SLOPE_OFFSET_TRIM [5:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 5 : 0
Name
OA1_SLOPE_OFFSET_TRIM
Description
Opamp1 slope offset drift trim Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1478
CTBM0_OA1_COMP_TRIM
26.1.23 CTBM0_OA1_COMP_TRIM
Address = 0x41100F14 Opamp1 trim control Address: 0x41100F14 Retention: Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:2]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
SW Access
None
HW Access
None
Name
None [31:24]
2
1
0
RW
R
OA1_COMP_TRIM [1:0]
10
9
8
18
17
16
26
25
24
Bits 1 : 0
Name OA1_COMP_TRIM
Description
Opamp1 Compensation Capacitor Trim. Value depends on the drive strength setting - 1x mode: set to 01; 10x mode: set to 11 Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1479
PASS_INTR_CAUSE
26.1.24 PASS_INTR_CAUSE
Address = 0x411F0000 Interrupt cause register Address: 0x411F0000 Retention: Not Retained
Bits SW Access HW Access
Name
7
6
5
4
3
2
1
0
None
R
None
R
None
W
None
W
None [7:5]
CTDAC0_INT
None [3:1]
CTB0_INT
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
4
CTDAC0_INT
0
CTB0_INT
Description
CTDAC0 interrupt pending Default Value: 0
CTB0 interrupt pending Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1480
27 Continuous-Time DAC Registers
This section discusses the Continuous-Time DAC registers. It lists all the registers in mapping tables, in address order.
27.1 Register Details
Register CTDAC0_CTDAC_CTRL CTDAC0_INTR CTDAC0_INTR_SET CTDAC0_INTR_MASK CTDAC0_INTR_MASKED CTDAC0_CTDAC_SW CTDAC0_CTDAC_SW_CLEAR CTDAC0_CTDAC_VAL CTDAC0_CTDAC_VAL_NXT
Address 0x41140000 0x41140020 0x41140024 0x41140028 0x4114002C 0x411400B0 0x411400B4 0x41140100 0x41140104
Description Global CTDAC control Interrupt request register Interrupt request set register Interrupt request mask Interrupt request masked CTDAC switch control CTDAC switch control clear DAC Value Next DAC value (double buffering)
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1481
CTDAC0_CTDAC_CTRL
27.1.1 CTDAC0_CTDAC_CTRL
Address = 0x41140000 Global CTDAC control Address: 0x41140000 Retention: Retained
Bits
7
6
5
4
SW Access
None
HW Access
None
Name
None [7:6]
Bits
15
14
13
12
SW Access
None
HW Access
None
Name
None [15:10]
3
2
RW
R
DEGLITCH_CNT [5:0]
11
10
Bits SW Access HW Access
Name
Bits SW Access HW Access
Name
23
22
21
20
19
18
RW
RW
None
R
R
None
CTDAC_RAN
GE
OUT_EN
None [21:16]
31 RW R
ENABLED
30
29
28
RW
RW
RW
R
R
R
DEEPS- DSI_STRO DSI_STRO LEEP_ON BE_LEVEL BE_EN
27
RW
R
DISABLED_-
MODE
26 None None
None
1
0
9
RW
R
DEGLITCH_-
COS
8 RW R
DEGLITCH_CO6
17
16
25
24
RW
R
CTDAC_MODE [25:24]
Bits
Name
Description
31
ENABLED
0: CTDAC IP disabled (put analog in power down, open all switches) 1: CTDAC IP enabled Default Value: 0
30
DEEPSLEEP_ON
- 0: CTDAC IP disabled off during DeepSleep power mode - 1: CTDAC IP remains enabled during DeepSleep power mode (if ENABLED=1) Default Value: 0
29
DSI_STROBE_LEVEL
Select level or edge detect for DSI strobe
- 0: DSI strobe signal is a pulse input, after a positive edge is detected on the DSI strobe signal
the next DAC value update is done on the next CTDAC clock
- 1: DSI strobe signal is a level input, as long as the DSI strobe signal remains high the CTDAC
will do a next DAC value update on each CTDAC clock.
Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1482
CTDAC0_CTDAC_CTRL
27.1.1
28
27
25 : 24
CTDAC0_CTDAC_CTRL (continued)
DSI_STROBE_EN DISABLED_MODE CTDAC_MODE
DSI strobe input Enable. This enables CTDAC updates to be further throttled by DSI. 0: Ignore DSI strobe input 1: Only do a CTDAC update if allowed by the DSI strobe (throttle), see below for level or edge Default Value: 0
Select the output value when the output is disabled (OUT_EN=0) (for risk mitigation) 0: Tri-state CTDAC output when disabled 1: output Vssa or Vref when disabled (see OUT_EN description) Default Value: 0
DAC mode, this determines the Value decoding Default Value: 0
0x0: UNSIGNED12 :
Unsigned 12-bit VDAC, i.e. no value decoding.
0x1: VIRT_SIGNED12 :
Virtual signed 12-bits' VDAC. Value decoding: add 0x800 to the 12-bit Value (=invert MSB), to convert the lowest signed number 0x800 to the lowest unsigned number 0x000. This is the same as the SAR handles 12-bit 'virtual' signed numbers.
0x2: RESERVED2 : Reserved
0x3: RESERVED3 : Reserved
23
CTDAC_RANGE
22
OUT_EN
9
DEGLITCH_COS
8
DEGLITCH_CO6
5 : 0
DEGLITCH_CNT
By closing the bottom switch in the R2R network the output is lifted by one LSB, effectively adding 1 0: Range is [0, 4095] * Vref / 4096 1: Range is [1, 4096] * Vref / 4096 Default Value: 0
Output enable, intended to be used during the Hold phase of the Sample and Hold when power cycling : 0: output disabled, the output is either: - Tri-state (DISABLED_MODE=0) - or Vssa (DISABLED_MODE=1 && CTDAC_RANGE=0) - or Vref (DISABLED_MODE=1 && CTDAC_RANGE=1) 1: output enabled, CTDAC output drives the programmed VALUE Default Value: 0
Force CTB.COS switch open after each VALUE change for the set number of clock cycles. Default Value: 0
Force CTDAC.CO6 switch open after each VALUE change for the set number of clock cycles. Default Value: 0
To prevent glitches after VALUE changes from propagating the output switch can be opened for DEGLITCH_CNT+1 clk_peri clock cycles. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1483
CTDAC0_INTR
27.1.2 CTDAC0_INTR
Address = 0x41140020 Interrupt request register Address: 0x41140020 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW1C
HW Access
None
RW1S
Name
None [7:1]
VDAC_EMP TY
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
VDAC_EMPTY
Description
VDAC Interrupt: hardware sets this interrupt when VDAC next value field is empty, i.e. was copied to the current VALUE. Write with '1' to clear bit. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1484
CTDAC0_INTR_SET
27.1.3 CTDAC0_INTR_SET
Address = 0x41140024 Interrupt request set register Address: 0x41140024 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW1S
HW Access
None
A
Name
None [7:1]
VDAC_EMP TY_SET
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
Description
0
VDAC_EMPTY_SET
Write with '1' to set corresponding bit in interrupt request register.
Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1485
CTDAC0_INTR_MASK
27.1.4 CTDAC0_INTR_MASK
Address = 0x41140028 Interrupt request mask Address: 0x41140028 Retention: Retained
Bits
7
6
5
4
3
2
SW Access
None
HW Access
None
Name
None [7:1]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
Description
0
VDAC_EMPTY_MASK
Mask bit for corresponding bit in interrupt request register.
Default Value: 0
1
0
RW
R
VDAC_EMP TY_MASK
9
8
17
16
25
24
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1486
CTDAC0_INTR_MASKED
27.1.5 CTDAC0_INTR_MASKED
Address = 0x4114002C Interrupt request masked Address: 0x4114002C Retention: Retained
Bits
7
6
5
4
3
2
SW Access
None
HW Access
None
Name
None [7:1]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
Description
0
VDAC_EMPTY_MASKED Logical and of corresponding request and mask bits.
Default Value: 0
1
0
R
W
VDAC_EMP TY_MASKE
D
9
8
17
16
25
24
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1487
CTDAC0_CTDAC_SW
27.1.6 CTDAC0_CTDAC_SW
Address = 0x411400B0 CTDAC switch control Address: 0x411400B0 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW1S
HW Access
None
RW1C
Name
None [7:1]
CTDD_CVD
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:9]
9
8
RW1S
RW1C
CTDO_CO6
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
8
CTDO_CO6
0
CTDD_CVD
Description
ctdvout to P6 pin. Note this switch will temporarily be opened for deglitching if DEGLITCH_CO6 is set Default Value: 0
VDDA supply to ctdrefdrive Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1488
CTDAC0_CTDAC_SW_CLEAR
27.1.7 CTDAC0_CTDAC_SW_CLEAR
Address = 0x411400B4 CTDAC switch control clear Address: 0x411400B4 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW1C
HW Access
None
A
Name
None [7:1]
CTDD_CVD
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:9]
9
8
RW1C
A
CTDO_CO6
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
8
CTDO_CO6
0
CTDD_CVD
Description
see corresponding bit in CTD_SW Default Value: 0
see corresponding bit in CTD_SW Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1489
CTDAC0_CTDAC_VAL
27.1.8 CTDAC0_CTDAC_VAL
Address = 0x41140100 DAC Value Address: 0x41140100 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
RW
Name
VALUE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
RW
HW Access
None
RW
Name
None [15:12]
VALUE [11:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 11 : 0
Name VALUE
Description
Value, in CTDAC_MODE 1 this value is decoded Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1490
CTDAC0_CTDAC_VAL_NXT
27.1.9 CTDAC0_CTDAC_VAL_NXT
Address = 0x41140104 Next DAC value (double buffering) Address: 0x41140104 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
VALUE [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
RW
HW Access
None
R
Name
None [15:12]
VALUE [11:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 11 : 0
Name VALUE
Description
Next value for CTDAC_VAL.VALUE Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1491
28 SAR ADC Registers
This section discusses the SAR ADC registers. It lists all the registers in mapping tables, in address order.
28.1 Register Details
Register SAR_CTRL SAR_SAMPLE_CTRL SAR_SAMPLE_TIME01 SAR_SAMPLE_TIME23 SAR_RANGE_THRES SAR_RANGE_COND SAR_CHAN_EN SAR_START_CTRL SAR_CHAN_CONFIG0 SAR_CHAN_CONFIG1 SAR_CHAN_CONFIG2 SAR_CHAN_CONFIG3 SAR_CHAN_CONFIG4 SAR_CHAN_CONFIG5 SAR_CHAN_CONFIG6 SAR_CHAN_CONFIG7 SAR_CHAN_CONFIG8 SAR_CHAN_CONFIG9 SAR_CHAN_CONFIG10 SAR_CHAN_CONFIG11 SAR_CHAN_CONFIG12 SAR_CHAN_CONFIG13 SAR_CHAN_CONFIG14 SAR_CHAN_CONFIG15 SAR_CHAN_WORK0 SAR_CHAN_WORK1 SAR_CHAN_WORK2
Address 0x411D0000 0x411D0004 0x411D0010 0x411D0014 0x411D0018 0x411D001C 0x411D0020 0x411D0024 0x411D0080 0x411D0084 0x411D0088 0x411D008C 0x411D0090 0x411D0094 0x411D0098 0x411D009C 0x411D00A0 0x411D00A4 0x411D00A8 0x411D00AC 0x411D00B0 0x411D00B4 0x411D00B8 0x411D00BC 0x411D0100 0x411D0104 0x411D0108
Description Analog control register. Sample control register. Sample time specification ST0 and ST1 Sample time specification ST2 and ST3 Global range detect threshold register. Global range detect mode register. Enable bits for the channels Start control register (firmware trigger). Channel configuration register. Channel configuration register. See SAR_CHAN_CONFIG0 for the details of bit fields. Channel configuration register. See SAR_CHAN_CONFIG0 for the details of bit fields. Channel configuration register. See SAR_CHAN_CONFIG0 for the details of bit fields. Channel configuration register. See SAR_CHAN_CONFIG0 for the details of bit fields. Channel configuration register. See SAR_CHAN_CONFIG0 for the details of bit fields. Channel configuration register. See SAR_CHAN_CONFIG0 for the details of bit fields. Channel configuration register. See SAR_CHAN_CONFIG0 for the details of bit fields. Channel configuration register. See SAR_CHAN_CONFIG0 for the details of bit fields. Channel configuration register. See SAR_CHAN_CONFIG0 for the details of bit fields. Channel configuration register. See SAR_CHAN_CONFIG0 for the details of bit fields. Channel configuration register. See SAR_CHAN_CONFIG0 for the details of bit fields. Channel configuration register. See SAR_CHAN_CONFIG0 for the details of bit fields. Channel configuration register. See SAR_CHAN_CONFIG0 for the details of bit fields. Channel configuration register. See SAR_CHAN_CONFIG0 for the details of bit fields. Channel configuration register. See SAR_CHAN_CONFIG0 for the details of bit fields. Channel working data register Channel working data register. See SAR_CHAN_WORK0 for the details of bit fields. Channel working data register. See SAR_CHAN_WORK0 for the details of bit fields.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1492
SAR ADC Registers
Register SAR_CHAN_WORK3 SAR_CHAN_WORK4 SAR_CHAN_WORK5 SAR_CHAN_WORK6 SAR_CHAN_WORK7 SAR_CHAN_WORK8 SAR_CHAN_WORK9 SAR_CHAN_WORK10 SAR_CHAN_WORK11 SAR_CHAN_WORK12 SAR_CHAN_WORK13 SAR_CHAN_WORK14 SAR_CHAN_WORK15 SAR_CHAN_RESULT0 SAR_CHAN_RESULT1 SAR_CHAN_RESULT2 SAR_CHAN_RESULT3 SAR_CHAN_RESULT4 SAR_CHAN_RESULT5 SAR_CHAN_RESULT6 SAR_CHAN_RESULT7 SAR_CHAN_RESULT8 SAR_CHAN_RESULT9 SAR_CHAN_RESULT10 SAR_CHAN_RESULT11 SAR_CHAN_RESULT12 SAR_CHAN_RESULT13 SAR_CHAN_RESULT14 SAR_CHAN_RESULT15 SAR_CHAN_WORK_UPDATED SAR_CHAN_RESULT_UPDATED SAR_INTR SAR_INTR_SET SAR_INTR_MASK SAR_INTR_MASKED SAR_SATURATE_INTR SAR_SATURATE_INTR_SET SAR_SATURATE_INTR_MASK SAR_SATURATE_INTR_MASKED SAR_RANGE_INTR SAR_RANGE_INTR_SET SAR_RANGE_INTR_MASK
Address 0x411D010C 0x411D0110 0x411D0114 0x411D0118 0x411D011C 0x411D0120 0x411D0124 0x411D0128 0x411D012C 0x411D0130 0x411D0134 0x411D0138 0x411D013C 0x411D0180 0x411D0184 0x411D0188 0x411D018C 0x411D0190 0x411D0194 0x411D0198 0x411D019C 0x411D01A0 0x411D01A4 0x411D01A8 0x411D01AC 0x411D01B0 0x411D01B4 0x411D01B8 0x411D01BC 0x411D0200 0x411D0204 0x411D0210 0x411D0214 0x411D0218 0x411D021C 0x411D0220 0x411D0224 0x411D0228 0x411D022C 0x411D0230 0x411D0234 0x411D0238
Description Channel working data register. See SAR_CHAN_WORK0 for the details of bit fields. Channel working data register. See SAR_CHAN_WORK0 for the details of bit fields. Channel working data register. See SAR_CHAN_WORK0 for the details of bit fields. Channel working data register. See SAR_CHAN_WORK0 for the details of bit fields. Channel working data register. See SAR_CHAN_WORK0 for the details of bit fields. Channel working data register. See SAR_CHAN_WORK0 for the details of bit fields. Channel working data register. See SAR_CHAN_WORK0 for the details of bit fields. Channel working data register. See SAR_CHAN_WORK0 for the details of bit fields. Channel working data register. See SAR_CHAN_WORK0 for the details of bit fields. Channel working data register. See SAR_CHAN_WORK0 for the details of bit fields. Channel working data register. See SAR_CHAN_WORK0 for the details of bit fields. Channel working data register. See SAR_CHAN_WORK0 for the details of bit fields. Channel working data register. See SAR_CHAN_WORK0 for the details of bit fields. Channel result data register Channel result data register. See SAR_CHAN_RESULT0 for the details of bit fields. Channel result data register. See SAR_CHAN_RESULT0 for the details of bit fields. Channel result data register. See SAR_CHAN_RESULT0 for the details of bit fields. Channel result data register. See SAR_CHAN_RESULT0 for the details of bit fields. Channel result data register. See SAR_CHAN_RESULT0 for the details of bit fields. Channel result data register. See SAR_CHAN_RESULT0 for the details of bit fields. Channel result data register. See SAR_CHAN_RESULT0 for the details of bit fields. Channel result data register. See SAR_CHAN_RESULT0 for the details of bit fields. Channel result data register. See SAR_CHAN_RESULT0 for the details of bit fields. Channel result data register. See SAR_CHAN_RESULT0 for the details of bit fields. Channel result data register. See SAR_CHAN_RESULT0 for the details of bit fields. Channel result data register. See SAR_CHAN_RESULT0 for the details of bit fields. Channel result data register. See SAR_CHAN_RESULT0 for the details of bit fields. Channel result data register. See SAR_CHAN_RESULT0 for the details of bit fields. Channel result data register. See SAR_CHAN_RESULT0 for the details of bit fields. Channel working data register 'updated' bits Channel result data register 'updated' bits Interrupt request register. Interrupt set request register Interrupt mask register. Interrupt masked request register Saturate interrupt request register. Saturate interrupt set request register Saturate interrupt mask register. Saturate interrupt masked request register Range detect interrupt request register. Range detect interrupt set request register Range detect interrupt mask register.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1493
SAR ADC Registers
Register SAR_RANGE_INTR_MASKED SAR_INTR_CAUSE SAR_INJ_CHAN_CONFIG SAR_INJ_RESULT SAR_STATUS SAR_AVG_STAT SAR_MUX_SWITCH0 SAR_MUX_SWITCH_CLEAR0 SAR_MUX_SWITCH_DS_CTRL SAR_MUX_SWITCH_SQ_CTRL SAR_MUX_SWITCH_STATUS
Address 0x411D023C 0x411D0240 0x411D0280 0x411D0290 0x411D02A0 0x411D02A4 0x411D0300 0x411D0304 0x411D0340 0x411D0344 0x411D0348
Description Range interrupt masked request register Interrupt cause register Injection channel configuration register. Injection channel result register Current status of internal SAR registers (mostly for debug) Current averaging status (for debug) SARMUX Firmware switch controls SARMUX Firmware switch control clear SARMUX switch DSI control SARMUX switch SAR Sequencer control SARMUX switch status
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1494
SAR_CTRL
28.1.1 SAR_CTRL
Address = 0x411D0000 Analog control register. Address: 0x411D0000 Retention: Retained
Bits SW Access HW Access
Name
7
RW
R
VREF_BYP_CAP_EN
6
5
4
RW
R
VREF_SEL [6:4]
3 None None
None
2
1
0
RW
R
PWR_CTRL_VREF [2:0]
Bits SW Access HW Access
Name
15
14
RW
R
COMP_DLY [15:14]
13
RW
R
SAR_HW_ CTRL_NEG
VREF
12 None None
None
11
10
9
RW
R
NEG_SEL [11:9]
8 None None
None
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
RW
RW
HW Access
None
R
R
R
Name
None [23:22]
REFBUF_EN
BOOSTPUMP_EN
SPARE [19:16]
Bits SW Access HW Access
Name
31 RW R
ENABLED
30
RW
R
SWITCH_DISABLE
29 RW R
DSI_MODE
28
RW
R
DSI_SYNC_CONFIG
27
RW
R
DEEPSLEEP_ON
26
25
24
RW
R
COMP_PWR [26:24]
Bits
Name
Description
31
ENABLED
- 0: SAR disabled (put analog in power down and stop clocks), also can clear FW_TRIGGER and INJ_START_EN (if not tailgaiting) on write. - 1: SAR enabled. Default Value: 0 Default Value: 0
30
SWITCH_DISABLE
Disable SAR sequencer from enabling routing switches (note DSI and firmware can always close
switches independent of this control)
- 0: Normal mode, SAR sequencer changes switches according to pin address in channel con-
figurations
- 1: Switches disabled, SAR sequencer does not enable any switches, it is the responsibility of
the firmware or UDBs (through DSI) to set the switches to route the signal to be converted
through the SARMUX
Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1495
SAR_CTRL
28.1.1
29 28 27 26 : 24
21 20 19 : 16 15 : 14
SAR_CTRL (continued)
DSI_MODE DSI_SYNC_CONFIG DEEPSLEEP_ON COMP_PWR
REFBUF_EN BOOSTPUMP_EN SPARE COMP_DLY
SAR sequencer takes configuration from DSI signals (note this also has the same effect as SWITCH_DISABLE==1) - 0: Normal mode, SAR sequencer operates according to CHAN_EN enables and CHAN_CONFIG channel configurations - 1: CHAN_EN, INJ_START_EN and channel configurations in CHAN_CONFIG and INJ_CHAN_CONFIG are ignored Default Value: 0
- 0: bypass clock domain synchronization of the DSI config signals. - 1: synchronize the DSI config signals to peripheral clock domain. Default Value: 1
- 0: SARMUX IP disabled off during DeepSleep power mode - 1: SARMUX IP remains enabled during DeepSleep power mode (if ENABLED=1) Default Value: 0
Comparator power mode. Default Value: 0
0x0: P100 : Reserved
0x1: P80 : Reserved
0x2: P60 : Reserved
0x3: P50 : Power = 50%, use this for 500-1000Ksps
0x4: P40 : Power = 40%, use this for 250-500Ksps
0x5: P30 : Power = 30%, use this for 100-250Ksps
0x6: P20 : Power = 20%, use this for 100-250Ksps
0x7: P10 : Power = 10%, use this for <100Ksps
For normal ADC operation this bit must be set, for all reference choices - internal, external or vdda based reference. Setting this bit is critical to proper function of switches inside SARREF block. Default Value: 0
Reserved, keep this bit at default value Default Value: 0
Reserved, keep this bit at default value Default Value: 0
Set the comparator latch delay in accordance with SAR conversion rate Default Value: 0
0x0: D2P5 : Reserved
0x1: D4 : Reserved
0x2: D10 : Reserved
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1496
SAR_CTRL
28.1.1
13 11 : 9
7 6 : 4
SAR_CTRL (continued)
SAR_HW_CTRL_NEGVREF NEG_SEL
VREF_BYP_CAP_EN VREF_SEL
0x3: D12 : Select this option for all operating modes
Hardware control: 0=only firmware control, 1=hardware control masked by firmware setting for VREF to NEG switch. Default Value: 0
SARADC internal NEG selection for Single ended conversion Default Value: 0
0x0: VSSA_KELVIN : NEG input of SARADC is connected to "vssa_kelvin", gives more precision around zero. Note this opens both SARADC internal switches, therefore use this value to insert a break-beforemake cycle on those switches when SWITCH_DISABLE is high.
0x1: ART_VSSA : Reserved
0x2: P1 : NEG input of SARADC is connected to P1 pin of SARMUX
0x3: P3 : NEG input of SARADC is connected to P3 pin of SARMUX
0x4: P5 : NEG input of SARADC is connected to P5 pin of SARMUX
0x5: P7 : NEG input of SARADC is connected to P7 pin of SARMUX
0x6: ACORE : Reserved
0x7: VREF : NEG input of SARADC is shorted with VREF input of SARADC.
VREF bypass cap enable for when VREF buffer is on Default Value: 0
SARADC internal VREF selection. Default Value: 0
0x0: VREF0 : Reserved
0x1: VREF1 : Reserved
0x2: VREF2 : Reserved
0x3: VREF_AROUTE : Reserved
0x4: VBGR : 1.2V from BandGap (VREF buffer on)
0x5: VREF_EXT : External precision Vref direct from a pin (low impedance path).
0x6: VDDA_DIV_2 : Vdda/2 (VREF buffer on)
0x7: VDDA : Vdda.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1497
28.1.1
2 : 0
SAR_CTRL (continued)
PWR_CTRL_VREF
VREF buffer low power mode. Default Value: 0
0x0: PWR_100 : full power (100%) (default), bypass cap, max clk_sar is 18MHz.
0x1: PWR_80 : 80% power
0x2: PWR_60 : 60% power
0x3: PWR_50 : 50% power
0x4: PWR_40 : 40% power
0x5: PWR_30 : 30% power
0x6: PWR_20 : 20% power
0x7: PWR_10 : 10% power
SAR_CTRL
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1498
SAR_SAMPLE_CTRL
28.1.2 SAR_SAMPLE_CTRL
Address = 0x411D0004 Sample control register. Address: 0x411D0004 Retention: Retained
Bits SW Access HW Access
Name
7 RW R
AVG_SHIFT
6
5
4
RW
R
AVG_CNT [6:4]
3 RW
R
DIFFERENTIAL_SIGNED
2
RW
R
SINGLE_ENDED_SIGNE
D
1 RW R
LEFT_ALIG N
0 None None
None
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:9]
9
8
RW
R
AVG_MODE
Bits
23
SW Access
HW Access
Name
22
21
None
None
None [23:20]
20
19
18
17
16
RW
RW
RW
RW
R
R
R
R
DSI_SYNC_TRIG-
GER
DSI_TRIGGER_LEV-
EL
DSI_TRIGGER_EN
CONTINUOUS
Bits
31
30
29
28
27
26
25
24
SW Access
RW
None
HW Access
R
None
Name
EOS_DSI_OU
T_EN
None [30:24]
Bits
Name
Description
31
EOS_DSI_OUT_EN
Enable to output EOS_INTR to DSI. When enabled each time EOS_INTR is set by the hardware
also a trigger pulse is send on the tr_sar_out signal.
Default Value: 0
19
DSI_SYNC_TRIGGER
- 0: bypass clock domain synchronization of the trigger signal.
- 1: synchronize the trigger signal to the SAR clock domain, if needed an edge detect is done in
the peripheral clock domain.
Default Value: 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1499
SAR_SAMPLE_CTRL
28.1.2
18 17 16 8
7 6 : 4
3
2
SAR_SAMPLE_CTRL (continued)
DSI_TRIGGER_LEVEL DSI_TRIGGER_EN CONTINUOUS AVG_MODE
AVG_SHIFT AVG_CNT
DIFFERENTIAL_SIGNED
SINGLE_ENDED_SIGNED
- 0: trigger signal is a pulse input, a positive edge detected on the trigger signal triggers a new scan. - 1: trigger signal is a level input, as long as the trigger signal remains high the SAR will do continuous scans. Default Value: 0
- 0: firmware trigger only: disable hardware trigger tr_sar_in. - 1: enable hardware trigger tr_sar_in (e.g. from TCPWM, GPIO or UDB). Default Value: 0
- 0: Wait for next FW_TRIGGER (one shot) or hardware trigger (e.g. from TPWM for periodic triggering) before scanning enabled channels. - 1: Continuously scan enabled channels, ignore triggers. Default Value: 0
Averaging mode, in DSI mode this bit is ignored and only AccuNDump mode is available. Default Value: 0
0x0: ACCUNDUMP : Accumulate and Dump (1st order accumulate and dump filter): a channel will be sampled back to back and averaged
0x1: INTERLEAVED : Interleaved: Each scan (trigger) one sample is taken per channel and averaged over several scans.
Averaging shifting: after averaging the result is shifted right to fit in 12 bits. Default Value: 0
Averaging Count for channels that have averaging enabled (AVG_EN). A channel will be sampled (1<<(AVG_CNT+1)) = [2..256] times. - In ACCUNDUMP mode (1st order accumulate and dump filter) a channel will be sampled back to back, the average result is calculated and stored and then the next enabled channel is sampled. If shifting is not enabled (AVG_SHIFT=0) then the result is forced to shift right so that is fits in 16 bits, so right shift is done by max(0,AVG_CNT-3). - In INTERLEAVED mode one sample is taken per triggered scan, only in the scan where the final averaging count is reached a valid average is calculated and stored in the RESULT register (by definition the same scan for all the channels that have averaging enabled). In all other scans the RESULT register for averaged channels will have an invalid result and the intermediate accumulated value is stored in the 16-bit WORK register. In this mode make sure that the averaging count is low enough to ensure that the intermediate value does not exceed 16-bits otherwise the MSBs will be lost. So for a 12-bit resolution the averaging count should be set to 16 or less (AVG_CNT=<3). Default Value: 0
Output data from a differential conversion as a signed value when DIFFERENTIAL_EN or NEG_ADDR_EN is set to 1 Default Value: 1
0x0: UNSIGNED : result data is unsigned (zero extended if needed)
0x1: SIGNED : Default: result data is signed (sign extended if needed)
Output data from a single ended conversion as a signed value Default Value: 0
0x0: UNSIGNED : Default: result data is unsigned (zero extended if needed)
0x1: SIGNED : result data is signed (sign extended if needed)
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1500
SAR_SAMPLE_CTRL
28.1.2
1
SAR_SAMPLE_CTRL (continued)
LEFT_ALIGN
Left align data in data[15:0], default data is right aligned in data[11:0], with sign extension to 16 bits if the channel is differential. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1501
SAR_SAMPLE_TIME01
28.1.3 SAR_SAMPLE_TIME01
Address = 0x411D0010 Sample time specification ST0 and ST1 Address: 0x411D0010 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
SAMPLE_TIME0 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
RW
HW Access
None
R
Name
None [15:10]
SAMPLE_TIME0 [9:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
SAMPLE_TIME1 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
RW
HW Access
None
R
Name
None [31:26]
SAMPLE_TIME1 [25:24]
Bits 25 : 16
9 : 0
Name SAMPLE_TIME1
SAMPLE_TIME0
Description
Sample time1 Default Value: 3
Sample time0 (aperture) in ADC clock cycles. Note that actual sample time is one clock less than specified here. The minimum sample time is 167ns, which is 3.0 cycles (4 in this field) with an 18MHz clock. Minimum legal value in this register is 2. Default Value: 3
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1502
SAR_SAMPLE_TIME23
28.1.4 SAR_SAMPLE_TIME23
Address = 0x411D0014 Sample time specification ST2 and ST3 Address: 0x411D0014 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
SAMPLE_TIME2 [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
RW
HW Access
None
R
Name
None [15:10]
SAMPLE_TIME2 [9:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
SAMPLE_TIME3 [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
RW
HW Access
None
R
Name
None [31:26]
SAMPLE_TIME3 [25:24]
Bits 25 : 16
9 : 0
Name SAMPLE_TIME3
SAMPLE_TIME2
Description
Sample time3 Default Value: 3
Sample time2 Default Value: 3
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1503
SAR_RANGE_THRES
28.1.5 SAR_RANGE_THRES
Address = 0x411D0018 Global range detect threshold register. Address: 0x411D0018 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
RANGE_LOW [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
RANGE_LOW [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
RANGE_HIGH [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
RANGE_HIGH [31:24]
Bits 31 : 16
15 : 0
Name RANGE_HIGH
RANGE_LOW
Description
High threshold for range detect. Default Value: 0
Low threshold for range detect. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1504
SAR_RANGE_COND
28.1.6 SAR_RANGE_COND
Address = 0x411D001C Global range detect mode register. Address: 0x411D001C Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
None
HW Access
R
None
Name
RANGE_COND [31:30]
None [29:24]
Bits 31 : 30
Name RANGE_COND
Description
Range condition select. Default Value: 0
0x0: BELOW : result < RANGE_LOW
0x1: INSIDE : RANGE_LOW <= result < RANGE_HIGH
0x2: ABOVE : RANGE_HIGH <= result
0x3: OUTSIDE : result < RANGE_LOW || RANGE_HIGH <= result
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1505
SAR_CHAN_EN
28.1.7 SAR_CHAN_EN
Address = 0x411D0020 Enable bits for the channels Address: 0x411D0020 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
CHAN_EN [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
CHAN_EN [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 0
Name CHAN_EN
Description
Channel enable. - 0: the corresponding channel is disabled. - 1: the corresponding channel is enabled, it will be included in the next scan. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1506
SAR_START_CTRL
28.1.8 SAR_START_CTRL
Address = 0x411D0024 Start control register (firmware trigger). Address: 0x411D0024 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW1S
HW Access
None
RW1C
Name
None [7:1]
FW_TRIGGER
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
FW_TRIGGER
Description
When firmware writes a 1 here it will trigger the next scan of enabled channels, hardware clears this bit when the scan started with this trigger is completed. If scanning continuously the trigger is ignored and hardware clears this bit after the next scan is done. This bit is also cleared when the SAR is disabled. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1507
SAR_CHAN_CONFIG0
28.1.9 SAR_CHAN_CONFIG0
Address = 0x411D0080 Channel configuration register. Address: 0x411D0080 Retention: Retained
Bits SW Access HW Access
Name
7 None None None
6
5
4
RW
R
POS_PORT_ADDR [6:4]
3 None None None
Bits SW Access HW Access
Name
15
14
None
None
None [15:14]
13
12
RW
R
SAMPLE_TIME_SEL [13:12]
11 None None
None
Bits SW Access HW Access
Name
23 None None None
22
21
20
RW
R
NEG_PORT_ADDR [22:20]
19 None None None
Bits
31
30
29
28
27
SW Access
RW
None
HW Access
R
None
Name
DSI_OUT_ EN
None [30:25]
2
1
0
RW
R
POS_PIN_ADDR [2:0]
10 RW R
AVG_EN
9 None None
None
8
RW
R
DIFFERENTIAL_EN
18
17
16
RW
R
NEG_PIN_ADDR [18:16]
26
25
24
RW
R
NEG_ADDR_EN
Bits
Name
31
DSI_OUT_EN
24
NEG_ADDR_EN
22 : 20
NEG_PORT_ADDR
Description
DSI data output enable for this channel. - 0: the conversion result for this channel is only stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. - 1: the conversion result for this channel is stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. The same data (same formatting), together with the channel number, is sent out on the DSI communication channel for processing in UDBs. Default Value: 0
1 - The NEG_PIN_ADDR and NEG_PORT_ADDR determines what drives the Vminus pin. This is a variation of differential mode with no even-odd pair limitation 0 - The NEG_SEL determines what drives the Vminus pin. Default Value: 0
Address of the neg port that contains the pin to be sampled by this channel. Default Value: 0
0x0: SARMUX : SARMUX pins.
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1508
SAR_CHAN_CONFIG0
28.1.9
18 : 16 13 : 12 10 8
6 : 4
2 : 0
SAR_CHAN_CONFIG0 (continued)
NEG_PIN_ADDR SAMPLE_TIME_SEL AVG_EN DIFFERENTIAL_EN
POS_PORT_ADDR
POS_PIN_ADDR
0x5: AROUTE_VIRT2 : Reserved
0x6: AROUTE_VIRT1 : Reserved
0x7: SARMUX_VIRT : SARMUX virtual port (VPORT0)
Address of the neg pin to be sampled by this channel. Default Value: 0
Sample time select: select which of the 4 global sample times to use for this channel Default Value: 0
Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s) Default Value: 0
Differential enable for this channel. If NEG_ADDR_EN=0 and this bit is 1 then POS_PIN_ADDR[0] is ignored and considered to be 0, i.e. POS_PIN_ADDR points to the even pin of a pin pair. In that case the even pin of the pair is connected to Vplus and the odd pin of the pair is connected to Vminus. POS_PORT_ADDR is used to identify the port that contains the pins. - 0: The voltage on the addressed pin is measured (Single-ended) and the resulting value is stored in the corresponding data register. - 1: The differential voltage on the addressed pin pair is measured and the resulting value is stored in the corresponding data register. (if NEG_ADDR_EN=0 then POS_PIN_ADDR[0] is ignored). Default Value: 0
Address of the port that contains the pin to be sampled by this channel (connected to Vplus) Default Value: 0
0x0: SARMUX : SARMUX pins.
0x1: CTB0 : CTB0
0x2: CTB1 : CTB1
0x3: CTB2 : Reserved
0x4: CTB3 : Reserved
0x5: AROUTE_VIRT2 : Reserved
0x6: AROUTE_VIRT1 : Reserved
0x7: SARMUX_VIRT : SARMUX virtual port (VPORT0)
Address of the pin to be sampled by this channel (connected to Vplus) Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1509
SAR_CHAN_WORK0
28.1.10 SAR_CHAN_WORK0
Address = 0x411D0100 Channel working data register Address: 0x411D0100 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
RW
Name
WORK [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
RW
Name
WORK [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
None
HW Access
W
None
Name
CHAN_WO RK_UPDATED_MIR
None [30:24]
Bits 31
15 : 0
Name
CHAN_WORK_UPDATED_MIR
WORK
Description
mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register Default Value: 0
SAR conversion working data of the channel. The data is written here right after sampling this channel. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1510
SAR_CHAN_RESULT0
28.1.11 SAR_CHAN_RESULT0
Address = 0x411D0180 Channel result data register Address: 0x411D0180 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
RESULT [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
RESULT [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
R
R
None
HW Access
W
W
W
None
Name
CHAN_RESULT_UPDATED_MI
R
RANGE_INTR_MIR
SATURATE_INTR_MIR
None [28:24]
Bits 31 30 29 15 : 0
Name
Description
CHAN_RESULT_UPDAT- mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register
ED_MIR
Default Value: 0
RANGE_INTR_MIR
mirror bit of corresponding bit in SAR_RANGE_INTR register Default Value: 0
SATURATE_INTR_MIR
mirror bit of corresponding bit in SAR_SATURATE_INTR register Default Value: 0
RESULT
SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1511
SAR_CHAN_WORK_UPDATED
28.1.12 SAR_CHAN_WORK_UPDATED
Address = 0x411D0200 Channel working data register 'updated' bits Address: 0x411D0200 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
RW
Name
CHAN_WORK_UPDATED [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
RW
Name
CHAN_WORK_UPDATED [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 0
Name
Description
CHAN_WORK_UPDATED
If set the corresponding WORK register was updated, i.e. was already sampled during the current scan and, in case of Interleaved averaging, reached the averaging count. If this bit is low then either the channel is not enabled or the averaging count is not yet reached for Interleaved averaging. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1512
SAR_CHAN_RESULT_UPDATED
28.1.13 SAR_CHAN_RESULT_UPDATED
Address = 0x411D0204 Channel result data register 'updated' bits Address: 0x411D0204 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
RW
Name
CHAN_RESULT_UPDATED [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
RW
Name
CHAN_RESULT_UPDATED [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 0
Name
Description
CHAN_RESULT_UPDATED
If set the corresponding RESULT register was updated, i.e. was sampled during the previous scan and, in case of Interleaved averaging, reached the averaging count. If this bit is low then either the channel is not enabled or the averaging count is not yet reached for Interleaved averaging. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1513
SAR_INTR
28.1.14 SAR_INTR
Address = 0x411D0210 Interrupt request register. Address: 0x411D0210 Retention: Not Retained
Bits SW Access HW Access
Name
7
6
5
4
3
2
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
RW1S
RW1S
RW1S
RW1S
RW1S
RW1S
INJ_COLLISION_INTR
INJ_RANGE_I
NTR
INJ_SATURATE_INTR
INJ_EOC_IN-
TR
DSI_COLLISION_INTR
FW_COLLISION_INTR
1
RW1C
RW1S
OVERFLOW_IN-
TR
0 RW1C RW1S
EOS_INTR
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
Description
7
INJ_COLLISION_INTR
Injection Collision Interrupt: hardware sets this interrupt when the injection trigger signal is as-
serted (INJ_START_EN==1 && INJ_TAILGATING==0) while the SAR is BUSY. Raising this in-
terrupt is delayed to when the sampling of the injection channel has been completed, i.e. not
when the preceding scan with which this trigger collided is completed. When this interrupt is set
it implies that the injection channel was sampled later than was intended. Write with '1' to clear
bit.
Default Value: 0
6
INJ_RANGE_INTR
Injection Range detect Interrupt: hardware sets this interrupt if the injection conversion result (af-
ter averaging) met the condition specified by the SAR_RANGE registers. Write with '1' to clear
bit.
Default Value: 0
5
INJ_SATURATE_INTR
Injection Saturation Interrupt: hardware sets this interrupt if an injection conversion result (before
averaging) is either 0x000 or 0xFFF, this is an indication that the ADC likely saturated. Write with
'1' to clear bit.
Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1514
SAR_INTR
28.1.14 SAR_INTR (continued)
4
INJ_EOC_INTR
Injection End of Conversion Interrupt: hardware sets this interrupt after completing the conversion for the injection channel (irrespective of if tailgating was used). Write with '1' to clear bit. Default Value: 0
3
DSI_COLLISION_INTR DSI Collision Interrupt: hardware sets this interrupt when the DSI trigger signal is asserted while
the SAR is BUSY. Raising this interrupt is delayed to when the scan caused by the DSI trigger
has been completed, i.e. not when the preceding scan with which this trigger collided is complet-
ed. When this interrupt is set it implies that the channels were sampled later than was intended
(jitter). Write with '1' to clear bit.
Default Value: 0
2
FW_COLLISION_INTR
Firmware Collision Interrupt: hardware sets this interrupt when FW_TRIGGER is asserted while
the SAR is BUSY. Raising this interrupt is delayed to when the scan caused by the FW_TRIG-
GER has been completed, i.e. not when the preceding scan with which this trigger collided is
completed. When this interrupt is set it implies that the channels were sampled later than was
intended (jitter). Write with '1' to clear bit.
Default Value: 0
1
OVERFLOW_INTR
Overflow Interrupt: hardware sets this interrupt when it sets a new EOS_INTR while that bit was
not yet cleared by the firmware. Write with '1' to clear bit.
Default Value: 0
0
EOS_INTR
End Of Scan Interrupt: hardware sets this interrupt after completing a scan of all the enabled channels. Write with '1' to clear bit. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1515
SAR_INTR_SET
28.1.15 SAR_INTR_SET
Address = 0x411D0214 Interrupt set request register Address: 0x411D0214 Retention: Not Retained
Bits SW Access HW Access
Name
7 RW1S
A
INJ_COLLISION_SET
6
RW1S
A
INJ_RANGE_
SET
5 RW1S
A
INJ_SATURATE_SET
4
3
2
1
RW1S
RW1S
RW1S
RW1S
A
A
A
A
INJ_EOC_SE
T
DSI_COLLISION_SET
FW_COLLISION_SET
OVERFLOW_SET
0 RW1S
A
EOS_SET
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
Description
7
INJ_COLLISION_SET
Write with '1' to set corresponding bit in interrupt request register.
Default Value: 0
6
INJ_RANGE_SET
Write with '1' to set corresponding bit in interrupt request register.
Default Value: 0
5
INJ_SATURATE_SET
Write with '1' to set corresponding bit in interrupt request register.
Default Value: 0
4
INJ_EOC_SET
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
3
DSI_COLLISION_SET
Write with '1' to set corresponding bit in interrupt request register.
Default Value: 0
2
FW_COLLISION_SET
Write with '1' to set corresponding bit in interrupt request register.
Default Value: 0
1
OVERFLOW_SET
Write with '1' to set corresponding bit in interrupt request register.
Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1516
SAR_INTR_SET
28.1.15 SAR_INTR_SET (continued)
0
EOS_SET
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1517
SAR_INTR_MASK
28.1.16 SAR_INTR_MASK
Address = 0x411D0218 Interrupt mask register. Address: 0x411D0218 Retention: Retained
Bits SW Access HW Access
Name
7
RW
R
INJ_COLLISION_MAS
K
6
RW
R
INJ_RANGE_
MASK
5
RW
R
INJ_SATURATE_MAS
K
4
RW
R
INJ_EOC_MA
SK
3
2
RW
RW
R
R
DSI_COLLI- FW_COLLI-
SION_MAS SION_MAS
K
K
1
RW
R
OVERFLOW_MA
SK
0 RW R
EOS_MASK
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
Description
7
INJ_COLLISION_MASK Mask bit for corresponding bit in interrupt request register.
Default Value: 0
6
INJ_RANGE_MASK
Mask bit for corresponding bit in interrupt request register.
Default Value: 0
5
INJ_SATURATE_MASK Mask bit for corresponding bit in interrupt request register.
Default Value: 0
4
INJ_EOC_MASK
Mask bit for corresponding bit in interrupt request register.
Default Value: 0
3
DSI_COLLISION_MASK Mask bit for corresponding bit in interrupt request register.
Default Value: 0
2
FW_COLLISION_MASK Mask bit for corresponding bit in interrupt request register.
Default Value: 0
1
OVERFLOW_MASK
Mask bit for corresponding bit in interrupt request register.
Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1518
SAR_INTR_MASK
28.1.16 SAR_INTR_MASK (continued)
0
EOS_MASK
Mask bit for corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1519
SAR_INTR_MASKED
28.1.17 SAR_INTR_MASKED
Address = 0x411D021C Interrupt masked request register Address: 0x411D021C Retention: Not Retained
Bits SW Access HW Access
Name
7
R
W
INJ_COLLISION_MAS
KED
6
R
W
INJ_RANGE_ MASKED
5
R
W
INJ_SATURATE_MAS
KED
4
R
W
INJ_EOC_MA
SKED
3
2
R
R
W
W
DSI_COLLI- FW_COLLI-
SION_MAS SION_MAS
KED
KED
1
R
W
OVERFLOW_MA
SKED
0 R W
EOS_MASKED
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
Description
7
INJ_COLLI-
SION_MASKED
Logical and of corresponding request and mask bits. Default Value: 0
6
INJ_RANGE_MASKED
Logical and of corresponding request and mask bits.
Default Value: 0
5
INJ_SATU-
RATE_MASKED
Logical and of corresponding request and mask bits. Default Value: 0
4
INJ_EOC_MASKED
Logical and of corresponding request and mask bits.
Default Value: 0
3
DSI_COLLI-
SION_MASKED
Logical and of corresponding request and mask bits. Default Value: 0
2
FW_COLLI-
SION_MASKED
Logical and of corresponding request and mask bits. Default Value: 0
1
OVERFLOW_MASKED Logical and of corresponding request and mask bits.
Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1520
28.1.17 SAR_INTR_MASKED (continued)
0
EOS_MASKED
Logical and of corresponding request and mask bits. Default Value: 0
SAR_INTR_MASKED
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1521
SAR_SATURATE_INTR
28.1.18 SAR_SATURATE_INTR
Address = 0x411D0220 Saturate interrupt request register. Address: 0x411D0220 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW1C
HW Access
RW1S
Name
SATURATE_INTR [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW1C
HW Access
RW1S
Name
SATURATE_INTR [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 0
Name SATURATE_INTR
Description
Saturate Interrupt: hardware sets this interrupt for each channel if a conversion result (before averaging) of that channel is either 0x000 or 0xFFF, this is an indication that the ADC likely saturated. Write with '1' to clear bit. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1522
SAR_SATURATE_INTR_SET
28.1.19 SAR_SATURATE_INTR_SET (continued)
28.1.19 SAR_SATURATE_INTR_SET
Address = 0x411D0224 Saturate interrupt set request register Address: 0x411D0224 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW1S
HW Access
A
Name
SATURATE_SET [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW1S
HW Access
A
Name
SATURATE_SET [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 0
Name SATURATE_SET
Description
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1523
SAR_SATURATE_INTR_MASK
28.1.20 SAR_SATURATE_INTR_MASK
Address = 0x411D0228 Saturate interrupt mask register. Address: 0x411D0228 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
SATURATE_MASK [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
SATURATE_MASK [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 0
Name SATURATE_MASK
Description
Mask bit for corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1524
SAR_SATURATE_INTR_MASKED
28.1.21 SAR_SATURATE_INTR_MASKED
Address = 0x411D022C Saturate interrupt masked request register Address: 0x411D022C Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
SATURATE_MASKED [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
SATURATE_MASKED [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 0
Name SATURATE_MASKED
Description
Logical and of corresponding request and mask bits. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1525
SAR_RANGE_INTR
28.1.22 SAR_RANGE_INTR
Address = 0x411D0230 Range detect interrupt request register. Address: 0x411D0230 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW1C
HW Access
RW1S
Name
RANGE_INTR [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW1C
HW Access
RW1S
Name
RANGE_INTR [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 0
Name RANGE_INTR
Description
Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers. Write with '1' to clear bit. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1526
SAR_RANGE_INTR_SET
28.1.23 SAR_RANGE_INTR_SET
Address = 0x411D0234 Range detect interrupt set request register Address: 0x411D0234 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW1S
HW Access
A
Name
RANGE_SET [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW1S
HW Access
A
Name
RANGE_SET [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 0
Name RANGE_SET
Description
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1527
SAR_RANGE_INTR_MASK
28.1.24 SAR_RANGE_INTR_MASK
Address = 0x411D0238 Range detect interrupt mask register. Address: 0x411D0238 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
RANGE_MASK [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
RANGE_MASK [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 0
Name RANGE_MASK
Description
Mask bit for corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1528
SAR_RANGE_INTR_MASKED
28.1.25 SAR_RANGE_INTR_MASKED
Address = 0x411D023C Range interrupt masked request register Address: 0x411D023C Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
RANGE_MASKED [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
RANGE_MASKED [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 15 : 0
Name RANGE_MASKED
Description
Logical and of corresponding request and mask bits. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1529
SAR_INTR_CAUSE
28.1.26 SAR_INTR_CAUSE
Address = 0x411D0240 Interrupt cause register Address: 0x411D0240 Retention: Not Retained
Bits SW Access HW Access
Name
7 R
W
INJ_COLLISION_MAS KED_MIR
6
R
W
INJ_RANGE_ MASKED_
MIR
5 R
W
INJ_SATURATE_MAS KED_MIR
4 R
W
INJ_EOC_MA SKED_MIR
3 R
W
DSI_COLLISION_MAS KED_MIR
2 R
W
FW_COLLISION_MAS KED_MIR
1 R
W
OVERFLOW_MA SKED_MIR
0 R
W
EOS_MASKED
_MIR
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
R
None
HW Access
W
W
None
Name
RANGE_M ASKED_RE
D
SATURATE_MAS KED_RED
None [29:24]
Bits
Name
Description
31
RANGE_MASKED_RED Reduction OR of all SAR_RANGE_INTR_MASKED bits
Default Value: 0
30
SATU-
Reduction OR of all SAR_SATURATION_INTR_MASKED bits
RATE_MASKED_RED
Default Value: 0
7
INJ_COLLI-
Mirror copy of corresponding bit in SAR_INTR_MASKED
SION_MASKED_MIR
Default Value: 0
6
IN-
Mirror copy of corresponding bit in SAR_INTR_MASKED
J_RANGE_MASKED_MIR Default Value: 0
5
INJ_SATU-
Mirror copy of corresponding bit in SAR_INTR_MASKED
RATE_MASKED_MIR
Default Value: 0
4
INJ_EOC_MASKED_MIR Mirror copy of corresponding bit in SAR_INTR_MASKED
Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1530
SAR_INTR_CAUSE
28.1.26 SAR_INTR_CAUSE (continued)
3
DSI_COLLI-
Mirror copy of corresponding bit in SAR_INTR_MASKED
SION_MASKED_MIR
Default Value: 0
2
FW_COLLI-
Mirror copy of corresponding bit in SAR_INTR_MASKED
SION_MASKED_MIR
Default Value: 0
1
OVER-
Mirror copy of corresponding bit in SAR_INTR_MASKED
FLOW_MASKED_MIR
Default Value: 0
0
EOS_MASKED_MIR
Mirror copy of corresponding bit in SAR_INTR_MASKED
Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1531
SAR_INJ_CHAN_CONFIG
28.1.27 SAR_INJ_CHAN_CONFIG
Address = 0x411D0280 Injection channel configuration register. Address: 0x411D0280 Retention: Retained
Bits SW Access HW Access
Name
7 None None None
6
5
4
RW
R
INJ_PORT_ADDR [6:4]
3 None None None
2
1
0
RW
R
INJ_PIN_ADDR [2:0]
Bits SW Access HW Access
Name
15
14
None
None
None [15:14]
13
12
RW
R
INJ_SAMPLE_TIME_SEL [13:12]
11 None None
None
10 RW R
INJ_AVG_EN
9 None None
None
8
RW
R
INJ_DIFFERENTIAL_EN
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW1S
RW
None
HW Access
RW1C
R
None
Name
INJ_START_E
N
INJ_TAILGATING
None [29:24]
Bits 31
30
13 : 12 10
Name INJ_START_EN
INJ_TAILGATING
INJ_SAMPLE_TIME_SEL INJ_AVG_EN
Description
Set by firmware to enable the injection channel. If INJ_TAILGATING is not set this bit also functions as trigger for this channel. Cleared by hardware after this channel has been sampled (i.e. this channel is always one shot even if CONTINUOUS is set). Also cleared if the SAR is disabled. Default Value: 0
Injection channel tailgating. - 0: no tailgating for this channel, SAR is immediately triggered when the INJ_START_EN bit is set. - 1: injection channel tailgating. The addressed pin is sampled after the next trigger and after all enabled channels have been scanned. Default Value: 0
Injection sample time select: select which of the 4 global sample times to use for this channel Default Value: 0
Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s) Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1532
SAR_INJ_CHAN_CONFIG
28.1.27 SAR_INJ_CHAN_CONFIG (continued)
8
INJ_DIFFERENTIAL_EN Differential enable for this channel.
- 0: The voltage on the addressed pin is measured (Single-ended) and the resulting value is
stored in the corresponding data register.
- 1: The differential voltage on the addressed pin pair is measured and the resulting value is
stored in the corresponding data register. (INJ_PIN_ADDR[0] is ignored).
Default Value: 0
6 : 4
INJ_PORT_ADDR
Address of the port that contains the pin to be sampled by this channel. Default Value: 0
0x0: SARMUX : SARMUX pins.
0x1: CTB0 : CTB0
0x2: CTB1 : CTB1
0x3: CTB2 : Reserved
0x4: CTB3 : Reserved
0x6: AROUTE_VIRT : Reserved
0x7: SARMUX_VIRT : SARMUX virtual port
2 : 0
INJ_PIN_ADDR
Address of the pin to be sampled by this injection channel. If differential is enabled then INJ_PIN_ADDR[0] is ignored and considered to be 0, i.e. INJ_PIN_ADDR points to the even pin of a pin pair. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1533
SAR_INJ_RESULT
28.1.28 SAR_INJ_RESULT
Address = 0x411D0290 Injection channel result register Address: 0x411D0290 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
INJ_RESULT [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
INJ_RESULT [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
R
R
R
None
HW Access
W
W
W
W
None
Name
INJ_EOC_IN-
TR_MIR
INJ_RANGE_I
NTR_MIR
INJ_SATURATE_INTR_MIR
INJ_COLLISION_INTR_MIR
None [27:24]
Bits 31 30 29 28 15 : 0
Name INJ_EOC_INTR_MIR
INJ_RANGE_INTR_MIR
INJ_SATURATE_INTR_MIR INJ_COLLISION_INTR_MIR INJ_RESULT
Description
mirror bit of corresponding bit in SAR_INTR register Default Value: 0
mirror bit of corresponding bit in SAR_INTR register Default Value: 0
mirror bit of corresponding bit in SAR_INTR register Default Value: 0
mirror bit of corresponding bit in SAR_INTR register Default Value: 0
SAR conversion result of the channel. Default Value: Undefined
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1534
SAR_STATUS
28.1.29 SAR_STATUS
Address = 0x411D02A0 Current status of internal SAR registers (mostly for debug) Address: 0x411D02A0 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
R
HW Access
None
W
Name
None [7:5]
CUR_CHAN [4:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
R
None
HW Access
W
W
None
Name
BUSY
SW_VREF_ NEG
None [29:24]
Bits
Name
31
BUSY
30
SW_VREF_NEG
4 : 0
CUR_CHAN
Description
If high then the SAR is busy with a conversion. This bit is always high when CONTINUOUS is set. Firmware should wait for this bit to be low before putting the SAR in power down. Default Value: 0
the current switch status, including DSI and sequencer controls, of the switch in the SARADC that shorts NEG with VREF input (see NEG_SEL). Default Value: 0
current channel being sampled (channel 16 indicates the injection channel), only valid if BUSY. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1535
SAR_AVG_STAT
28.1.30 SAR_AVG_STAT
Address = 0x411D02A4 Current averaging status (for debug) Address: 0x411D02A4 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
CUR_AVG_ACCU [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
CUR_AVG_ACCU [15:8]
Bits SW Access HW Access
Name
23
R
W
INTRLV_BUS
Y
22
21
20
None
None
None [22:20]
19
18
17
16
R
W
CUR_AVG_ACCU [19:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
W
Name
CUR_AVG_CNT [31:24]
Bits 31 : 24
Name CUR_AVG_CNT
23
INTRLV_BUSY
19 : 0
CUR_AVG_ACCU
Description
the current value of the averaging counter. Note that the value shown is updated after the sampling time and therefore runs ahead of the accumulator update. Default Value: 0
If high then the SAR is in the middle of Interleaved averaging spanning several scans. While this bit is high the Firmware should not make any changes to the configuration registers otherwise some results may be incorrect. Note that the CUR_AVG_CNT status register below gives an indication how many more scans need to be done to complete the Interleaved averaging. This bit can be cleared by changing the averaging mode to ACCUNDUMP or by disabling the SAR. Default Value: 0
the current value of the averaging accumulator Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1536
SAR_MUX_SWITCH0
28.1.31 SAR_MUX_SWITCH0
Address = 0x411D0300 SARMUX Firmware switch controls Address: 0x411D0300 Retention: Retained
Bits SW Access HW Access
Name
7
RW1S
RW1C
MUX_FW_P7_VPL
US
6
RW1S
RW1C
MUX_FW_P6_VPL
US
5
RW1S
RW1C
MUX_FW_P5_VPL
US
4
RW1S
RW1C
MUX_FW_P4_VPL
US
3
RW1S
RW1C
MUX_FW_P3_VPL
US
2
RW1S
RW1C
MUX_FW_P2_VPL
US
1
RW1S
RW1C
MUX_FW_P1_VPL
US
0
RW1S
RW1C
MUX_FW_P0_VPL
US
Bits SW Access HW Access
Name
15
14
13
12
11
10
9
8
RW1S
RW1S
RW1S
RW1S
RW1S
RW1S
RW1S
RW1S
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
MUX_F-
MUX_F-
MUX_F-
MUX_F-
MUX_F-
MUX_F-
MUX_F-
MUX_F-
W_P7_VMI- W_P6_VMI- W_P5_VMI- W_P4_VMI- W_P3_VMI- W_P2_VMI- W_P1_VMI- W_P0_VMI-
NUS
NUS
NUS
NUS
NUS
NUS
NUS
NUS
Bits SW Access HW Access
Name
23
RW1S
RW1C
MUX_FW_SARBUS1_VPL
US
22
RW1S
RW1C
MUX_FW_SARBUS0_VPL
US
21
RW1S
RW1C
MUX_FW_AMUXBUSB_VMI
NUS
20
RW1S
RW1C
MUX_FW_AMUXBUSA_VMI
NUS
19
RW1S
RW1C
MUX_FW_AMUXBUSB_VPL
US
18
RW1S
RW1C
MUX_FW_AMUXBUSA_VPL
US
17 RW1S RW1C
MUX_FW_TEMP_VPL
US
16
RW1S
RW1C
MUX_FW_VSSA_VMINU
S
Bits SW Access HW Access
Name
31
30
None
None
None [31:30]
29
28
27
26
25
RW1S
RW1S
RW1S
RW1S
RW1S
RW1C
RW1C
RW1C
RW1C
RW1C
MUX_F-
MUX_F-
MUX_F-
MUX_F-
W_P7_COR W_P6_COR W_P5_COR W_P4_COR
EIO3
EIO2
EIO1
EIO0
MUX_FW_SARBUS1_VMI
NUS
24
RW1S
RW1C
MUX_FW_SARBUS0_VMI
NUS
Bits
Name
Description
29
MUX_FW_P7_COREIO3 Firmware control: 0=open, 1=close switch between P7 and coreio3 signal. Write with '1' to set bit.
Default Value: 0
28
MUX_FW_P6_COREIO2 Firmware control: 0=open, 1=close switch between P6 and coreio2 signal. Write with '1' to set bit.
Default Value: 0
27
MUX_FW_P5_COREIO1 Firmware control: 0=open, 1=close switch between P5 and coreio1 signal. Write with '1' to set bit.
Default Value: 0
26
MUX_FW_P4_COREIO0 Firmware control: 0=open, 1=close switch between P4 and coreio0 signal. Write with '1' to set bit.
Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1537
SAR_MUX_SWITCH0
28.1.31 SAR_MUX_SWITCH0 (continued)
25
MUX_FW_SAR-
BUS1_VMINUS
Firmware control: 0=open, 1=close switch between sarbus1 and vminus signal. Write with '1' to set bit. Default Value: 0
24
MUX_FW_SAR-
BUS0_VMINUS
Firmware control: 0=open, 1=close switch between sarbus0 and vminus signal. Write with '1' to set bit. Default Value: 0
23
MUX_FW_SAR-
BUS1_VPLUS
Firmware control: 0=open, 1=close switch between sarbus1 and vplus signal. Write with '1' to set bit. Default Value: 0
22
MUX_FW_SAR-
BUS0_VPLUS
Firmware control: 0=open, 1=close switch between sarbus0 and vplus signal. Write with '1' to set bit. Default Value: 0
21
MUX_FW_AMUXBUS-
Firmware control: 0=open, 1=close switch between amuxbusb and vminus signal. Write with '1'
B_VMINUS
to set bit.
Default Value: 0
20
MUX_FW_AMUX-
Firmware control: 0=open, 1=close switch between amuxbusa and vminus signal. Write with '1'
BUSA_VMINUS
to set bit.
Default Value: 0
19
MUX_FW_AMUXBUS-
Firmware control: 0=open, 1=close switch between amuxbusb and vplus signal. Write with '1' to
B_VPLUS
set bit.
Default Value: 0
18
MUX_FW_AMUX-
Firmware control: 0=open, 1=close switch between amuxbusa and vplus signal. Write with '1' to
BUSA_VPLUS
set bit.
Default Value: 0
17
MUX_FW_TEMP_VPLUS Firmware control: 0=open, 1=close switch between temperature sensor and vplus signal, also
powers on the temperature sensor. Write with '1' to set bit.
Default Value: 0
16
MUX_FW_VSSA_VMI-
Firmware control: 0=open, 1=close switch between vssa_kelvin and vminus signal. Write with '1'
NUS
to set bit.
Default Value: 0
15
MUX_FW_P7_VMINUS Firmware control: 0=open, 1=close switch between pin P7 and vminus signal. Write with '1' to set
bit.
Default Value: 0
14
MUX_FW_P6_VMINUS Firmware control: 0=open, 1=close switch between pin P6 and vminus signal. Write with '1' to set
bit.
Default Value: 0
13
MUX_FW_P5_VMINUS Firmware control: 0=open, 1=close switch between pin P5 and vminus signal. Write with '1' to set
bit.
Default Value: 0
12
MUX_FW_P4_VMINUS Firmware control: 0=open, 1=close switch between pin P4 and vminus signal. Write with '1' to set
bit.
Default Value: 0
11
MUX_FW_P3_VMINUS Firmware control: 0=open, 1=close switch between pin P3 and vminus signal. Write with '1' to set
bit.
Default Value: 0
10
MUX_FW_P2_VMINUS Firmware control: 0=open, 1=close switch between pin P2 and vminus signal. Write with '1' to set
bit.
Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1538
SAR_MUX_SWITCH0
28.1.31 SAR_MUX_SWITCH0 (continued)
9
MUX_FW_P1_VMINUS Firmware control: 0=open, 1=close switch between pin P1 and vminus signal. Write with '1' to set
bit.
Default Value: 0
8
MUX_FW_P0_VMINUS Firmware control: 0=open, 1=close switch between pin P0 and vminus signal. Write with '1' to set
bit.
Default Value: 0
7
MUX_FW_P7_VPLUS
Firmware control: 0=open, 1=close switch between pin P7 and vplus signal. Write with '1' to set
bit.
Default Value: 0
6
MUX_FW_P6_VPLUS
Firmware control: 0=open, 1=close switch between pin P6 and vplus signal. Write with '1' to set
bit.
Default Value: 0
5
MUX_FW_P5_VPLUS
Firmware control: 0=open, 1=close switch between pin P5 and vplus signal. Write with '1' to set
bit.
Default Value: 0
4
MUX_FW_P4_VPLUS
Firmware control: 0=open, 1=close switch between pin P4 and vplus signal. Write with '1' to set
bit.
Default Value: 0
3
MUX_FW_P3_VPLUS
Firmware control: 0=open, 1=close switch between pin P3 and vplus signal. Write with '1' to set
bit.
Default Value: 0
2
MUX_FW_P2_VPLUS
Firmware control: 0=open, 1=close switch between pin P2 and vplus signal. Write with '1' to set
bit.
Default Value: 0
1
MUX_FW_P1_VPLUS
Firmware control: 0=open, 1=close switch between pin P1 and vplus signal. Write with '1' to set
bit.
Default Value: 0
0
MUX_FW_P0_VPLUS
Firmware control: 0=open, 1=close switch between pin P0 and vplus signal. Write with '1' to set
bit.
Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1539
SAR_MUX_SWITCH_CLEAR0
28.1.32 SAR_MUX_SWITCH_CLEAR0
Address = 0x411D0304 SARMUX Firmware switch control clear Address: 0x411D0304 Retention: Retained
Bits SW Access HW Access
Name
7
RW1C
A
MUX_FW_P7_VPL
US
6
RW1C
A
MUX_FW_P6_VPL
US
5
RW1C
A
MUX_FW_P5_VPL
US
4
RW1C
A
MUX_FW_P4_VPL
US
3
RW1C
A
MUX_FW_P3_VPL
US
2
RW1C
A
MUX_FW_P2_VPL
US
1
RW1C
A
MUX_FW_P1_VPL
US
0
RW1C
A
MUX_FW_P0_VPL
US
Bits SW Access HW Access
Name
15
14
13
12
11
10
9
8
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
A
A
A
A
A
A
A
A
MUX_F-
MUX_F-
MUX_F-
MUX_F-
MUX_F-
MUX_F-
MUX_F-
MUX_F-
W_P7_VMI- W_P6_VMI- W_P5_VMI- W_P4_VMI- W_P3_VMI- W_P2_VMI- W_P1_VMI- W_P0_VMI-
NUS
NUS
NUS
NUS
NUS
NUS
NUS
NUS
Bits SW Access HW Access
Name
23
RW1C
A
MUX_FW_SARBUS1_VPL
US
22
RW1C
A
MUX_FW_SARBUS0_VPL
US
21
RW1C
A
MUX_FW_AMUXBUSB_VMI
NUS
20
RW1C
A
MUX_FW_AMUXBUSA_VMI
NUS
19
RW1C
A
MUX_FW_AMUXBUSB_VPL
US
18
RW1C
A
MUX_FW_AMUXBUSA_VPL
US
17 RW1C
A
MUX_FW_TEMP_VPL
US
16
RW1C
A
MUX_FW_VSSA_VMINU
S
Bits SW Access HW Access
Name
31
30
None
None
None [31:30]
29
28
27
26
25
RW1C
RW1C
RW1C
RW1C
RW1C
A
A
A
A
A
MUX_F-
MUX_F-
MUX_F-
MUX_F-
W_P7_COR W_P6_COR W_P5_COR W_P4_COR
EIO3
EIO2
EIO1
EIO0
MUX_FW_SARBUS1_VMI
NUS
24
RW1C
A
MUX_FW_SARBUS0_VMI
NUS
Bits
Name
Description
29
MUX_FW_P7_COREIO3 Write '1' to clear corresponding bit in MUX_SWITCH0
Default Value: 0
28
MUX_FW_P6_COREIO2 Write '1' to clear corresponding bit in MUX_SWITCH0
Default Value: 0
27
MUX_FW_P5_COREIO1 Write '1' to clear corresponding bit in MUX_SWITCH0
Default Value: 0
26
MUX_FW_P4_COREIO0 Write '1' to clear corresponding bit in MUX_SWITCH0
Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1540
SAR_MUX_SWITCH_CLEAR0
28.1.32 SAR_MUX_SWITCH_CLEAR0 (continued)
25
MUX_FW_SAR-
BUS1_VMINUS
Write '1' to clear corresponding bit in MUX_SWITCH0 Default Value: 0
24
MUX_FW_SAR-
BUS0_VMINUS
Write '1' to clear corresponding bit in MUX_SWITCH0 Default Value: 0
23
MUX_FW_SAR-
BUS1_VPLUS
Write '1' to clear corresponding bit in MUX_SWITCH0 Default Value: 0
22
MUX_FW_SAR-
BUS0_VPLUS
Write '1' to clear corresponding bit in MUX_SWITCH0 Default Value: 0
21
MUX_FW_AMUXBUS-
Write '1' to clear corresponding bit in MUX_SWITCH0
B_VMINUS
Default Value: 0
20
MUX_FW_AMUX-
Write '1' to clear corresponding bit in MUX_SWITCH0
BUSA_VMINUS
Default Value: 0
19
MUX_FW_AMUXBUS-
Write '1' to clear corresponding bit in MUX_SWITCH0
B_VPLUS
Default Value: 0
18
MUX_FW_AMUX-
Write '1' to clear corresponding bit in MUX_SWITCH0
BUSA_VPLUS
Default Value: 0
17
MUX_FW_TEMP_VPLUS Write '1' to clear corresponding bit in MUX_SWITCH0
Default Value: 0
16
MUX_FW_VSSA_VMI-
Write '1' to clear corresponding bit in MUX_SWITCH0
NUS
Default Value: 0
15
MUX_FW_P7_VMINUS Write '1' to clear corresponding bit in MUX_SWITCH0
Default Value: 0
14
MUX_FW_P6_VMINUS Write '1' to clear corresponding bit in MUX_SWITCH0
Default Value: 0
13
MUX_FW_P5_VMINUS Write '1' to clear corresponding bit in MUX_SWITCH0
Default Value: 0
12
MUX_FW_P4_VMINUS Write '1' to clear corresponding bit in MUX_SWITCH0
Default Value: 0
11
MUX_FW_P3_VMINUS Write '1' to clear corresponding bit in MUX_SWITCH0
Default Value: 0
10
MUX_FW_P2_VMINUS Write '1' to clear corresponding bit in MUX_SWITCH0
Default Value: 0
9
MUX_FW_P1_VMINUS Write '1' to clear corresponding bit in MUX_SWITCH0
Default Value: 0
8
MUX_FW_P0_VMINUS Write '1' to clear corresponding bit in MUX_SWITCH0
Default Value: 0
7
MUX_FW_P7_VPLUS
Write '1' to clear corresponding bit in MUX_SWITCH0
Default Value: 0
6
MUX_FW_P6_VPLUS
Write '1' to clear corresponding bit in MUX_SWITCH0
Default Value: 0
5
MUX_FW_P5_VPLUS
Write '1' to clear corresponding bit in MUX_SWITCH0
Default Value: 0
4
MUX_FW_P4_VPLUS
Write '1' to clear corresponding bit in MUX_SWITCH0
Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1541
SAR_MUX_SWITCH_CLEAR0
28.1.32 SAR_MUX_SWITCH_CLEAR0 (continued)
3
MUX_FW_P3_VPLUS
Write '1' to clear corresponding bit in MUX_SWITCH0
Default Value: 0
2
MUX_FW_P2_VPLUS
Write '1' to clear corresponding bit in MUX_SWITCH0
Default Value: 0
1
MUX_FW_P1_VPLUS
Write '1' to clear corresponding bit in MUX_SWITCH0
Default Value: 0
0
MUX_FW_P0_VPLUS
Write '1' to clear corresponding bit in MUX_SWITCH0
Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1542
SAR_MUX_SWITCH_DS_CTRL
28.1.33 SAR_MUX_SWITCH_DS_CTRL
Address = 0x411D0340 SARMUX switch DSI control Address: 0x411D0340 Retention: Retained
Bits SW Access HW Access
Name
7
RW
R
MUX_DS_CTRL_P7
6
RW
R
MUX_DS_CTRL_P6
5
RW
R
MUX_DS_CTRL_P5
4
RW
R
MUX_DS_CTRL_P4
3
RW
R
MUX_DS_CTRL_P3
2
RW
R
MUX_DS_CTRL_P2
1
RW
R
MUX_DS_CTRL_P1
0
RW
R
MUX_DS_CTRL_P0
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits SW Access HW Access
Name
23
RW
R
MUX_DS_CTRL_SARB
US1
22
RW
R
MUX_DS_CTRL_SARB
US0
21
20
None
None
None [21:20]
19
RW
R
MUX_DS_CTRL_AMUX BUSB
18
RW
R
MUX_DS_CTRL_AMUX BUSA
17 RW
R
MUX_DS_CTRL_TEMP
16 RW
R
MUX_DS_CTRL_VSSA
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
Description
23
MUX_DS_CTRL_SAR-
for sarbus1 switch
BUS1
Default Value: 0
22
MUX_DS_CTRL_SAR-
for sarbus0 switch
BUS0
Default Value: 0
19
MUX_DS_CTRL_AMUX- for amuxbusb switches
BUSB
Default Value: 0
18
MUX_DS_CTRL_AMUX- for amuxbusa switch
BUSA
Default Value: 0
17
MUX_DS_CTRL_TEMP for temp switch
Default Value: 0
16
MUX_DS_CTRL_VSSA for vssa switch
Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1543
28.1.33 SAR_MUX_SWITCH_DS_CTRL (continued)
7
MUX_DS_CTRL_P7
for P7 switches
Default Value: 0
6
MUX_DS_CTRL_P6
for P6 switches
Default Value: 0
5
MUX_DS_CTRL_P5
for P5 switches
Default Value: 0
4
MUX_DS_CTRL_P4
for P4 switches
Default Value: 0
3
MUX_DS_CTRL_P3
for P3 switches
Default Value: 0
2
MUX_DS_CTRL_P2
for P2 switches
Default Value: 0
1
MUX_DS_CTRL_P1
for P1 switches
Default Value: 0
0
MUX_DS_CTRL_P0
for P0 switches
Default Value: 0
SAR_MUX_SWITCH_DS_CTRL
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1544
SAR_MUX_SWITCH_SQ_CTRL
28.1.34 SAR_MUX_SWITCH_SQ_CTRL
Address = 0x411D0344 SARMUX switch Sar Sequencer control Address: 0x411D0344 Retention: Retained
Bits SW Access HW Access
Name
7
RW
R
MUX_SQ_CTRL_P7
6
RW
R
MUX_SQ_CTRL_P6
5
RW
R
MUX_SQ_CTRL_P5
4
RW
R
MUX_SQ_CTRL_P4
3
RW
R
MUX_SQ_CTRL_P3
2
RW
R
MUX_SQ_CTRL_P2
1
RW
R
MUX_SQ_CTRL_P1
0
RW
R
MUX_SQ_CTRL_P0
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits SW Access HW Access
Name
23
RW
R
MUX_SQ_CTRL_SARB
US1
22
RW
R
MUX_SQ_CTRL_SARB
US0
21
20
None
None
None [21:20]
19
RW
R
MUX_SQ_CTRL_AMUX BUSB
18
RW
R
MUX_SQ_CTRL_AMUX BUSA
17 RW
R
MUX_SQ_CTRL_TEMP
16 RW
R
MUX_SQ_CTRL_VSSA
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
Description
23
MUX_SQ_CTRL_SAR-
for sarbus1 switch
BUS1
Default Value: 0
22
MUX_SQ_CTRL_SAR-
for sarbus0 switch
BUS0
Default Value: 0
19
MUX_SQ_CTRL_AMUX- for amuxbusb switches
BUSB
Default Value: 0
18
MUX_SQ_CTRL_AMUX- for amuxbusa switch
BUSA
Default Value: 0
17
MUX_SQ_CTRL_TEMP for temp switch
Default Value: 0
16
MUX_SQ_CTRL_VSSA for vssa switch
Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1545
28.1.34 SAR_MUX_SWITCH_SQ_CTRL (continued)
7
MUX_SQ_CTRL_P7
for P7 switches
Default Value: 0
6
MUX_SQ_CTRL_P6
for P6 switches
Default Value: 0
5
MUX_SQ_CTRL_P5
for P5 switches
Default Value: 0
4
MUX_SQ_CTRL_P4
for P4 switches
Default Value: 0
3
MUX_SQ_CTRL_P3
for P3 switches
Default Value: 0
2
MUX_SQ_CTRL_P2
for P2 switches
Default Value: 0
1
MUX_SQ_CTRL_P1
for P1 switches
Default Value: 0
0
MUX_SQ_CTRL_P0
for P0 switches
Default Value: 0
SAR_MUX_SWITCH_SQ_CTRL
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1546
SAR_MUX_SWITCH_STATUS
28.1.35 SAR_MUX_SWITCH_STATUS
Address = 0x411D0348 SARMUX switch status Address: 0x411D0348 Retention: Retained
Bits SW Access HW Access
Name
7
R
W
MUX_FW_P7_VPL
US
6
R
W
MUX_FW_P6_VPL
US
5
R
W
MUX_FW_P5_VPL
US
4
R
W
MUX_FW_P4_VPL
US
3
R
W
MUX_FW_P3_VPL
US
2
R
W
MUX_FW_P2_VPL
US
1
R
W
MUX_FW_P1_VPL
US
0
R
W
MUX_FW_P0_VPL
US
Bits SW Access HW Access
Name
15
14
13
12
11
10
9
8
R
R
R
R
R
R
R
R
W
W
W
W
W
W
W
W
MUX_F-
MUX_F-
MUX_F-
MUX_F-
MUX_F-
MUX_F-
MUX_F-
MUX_F-
W_P7_VMI- W_P6_VMI- W_P5_VMI- W_P4_VMI- W_P3_VMI- W_P2_VMI- W_P1_VMI- W_P0_VMI-
NUS
NUS
NUS
NUS
NUS
NUS
NUS
NUS
Bits SW Access HW Access
Name
23
R
W
MUX_FW_SARBUS1_VPL
US
22
R
W
MUX_FW_SARBUS0_VPL
US
21
R
W
MUX_FW_AMUXBUSB_VMI
NUS
20
R
W
MUX_FW_AMUXBUSA_VMI
NUS
19
R
W
MUX_FW_AMUXBUSB_VPL
US
18
R
W
MUX_FW_AMUXBUSA_VPL
US
17 R W
MUX_FW_TEMP_VPL
US
16
R
W
MUX_FW_VSSA_VMINU
S
Bits
31
30
29
28
27
26
25
24
SW Access
None
R
R
HW Access
None
W
W
Name
None [31:26]
MUX_FW_SARBUS1_VMI
NUS
MUX_FW_SARBUS0_VMI
NUS
Bits
Name
25
MUX_FW_SAR-
BUS1_VMINUS
24
MUX_FW_SAR-
BUS0_VMINUS
23
MUX_FW_SAR-
BUS1_VPLUS
22
MUX_FW_SAR-
BUS0_VPLUS
Description
switch status of corresponding bit in MUX_SWITCH0 Default Value: 0
switch status of corresponding bit in MUX_SWITCH0 Default Value: 0
switch status of corresponding bit in MUX_SWITCH0 Default Value: 0
switch status of corresponding bit in MUX_SWITCH0 Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1547
SAR_MUX_SWITCH_STATUS
28.1.35 SAR_MUX_SWITCH_STATUS (continued)
21
MUX_FW_AMUXBUS-
switch status of corresponding bit in MUX_SWITCH0
B_VMINUS
Default Value: 0
20
MUX_FW_AMUX-
switch status of corresponding bit in MUX_SWITCH0
BUSA_VMINUS
Default Value: 0
19
MUX_FW_AMUXBUS-
switch status of corresponding bit in MUX_SWITCH0
B_VPLUS
Default Value: 0
18
MUX_FW_AMUX-
switch status of corresponding bit in MUX_SWITCH0
BUSA_VPLUS
Default Value: 0
17
MUX_FW_TEMP_VPLUS switch status of corresponding bit in MUX_SWITCH0
Default Value: 0
16
MUX_FW_VSSA_VMI-
switch status of corresponding bit in MUX_SWITCH0
NUS
Default Value: 0
15
MUX_FW_P7_VMINUS switch status of corresponding bit in MUX_SWITCH0
Default Value: 0
14
MUX_FW_P6_VMINUS switch status of corresponding bit in MUX_SWITCH0
Default Value: 0
13
MUX_FW_P5_VMINUS switch status of corresponding bit in MUX_SWITCH0
Default Value: 0
12
MUX_FW_P4_VMINUS switch status of corresponding bit in MUX_SWITCH0
Default Value: 0
11
MUX_FW_P3_VMINUS switch status of corresponding bit in MUX_SWITCH0
Default Value: 0
10
MUX_FW_P2_VMINUS switch status of corresponding bit in MUX_SWITCH0
Default Value: 0
9
MUX_FW_P1_VMINUS switch status of corresponding bit in MUX_SWITCH0
Default Value: 0
8
MUX_FW_P0_VMINUS switch status of corresponding bit in MUX_SWITCH0
Default Value: 0
7
MUX_FW_P7_VPLUS
switch status of corresponding bit in MUX_SWITCH0
Default Value: 0
6
MUX_FW_P6_VPLUS
switch status of corresponding bit in MUX_SWITCH0
Default Value: 0
5
MUX_FW_P5_VPLUS
switch status of corresponding bit in MUX_SWITCH0
Default Value: 0
4
MUX_FW_P4_VPLUS
switch status of corresponding bit in MUX_SWITCH0
Default Value: 0
3
MUX_FW_P3_VPLUS
switch status of corresponding bit in MUX_SWITCH0
Default Value: 0
2
MUX_FW_P2_VPLUS
switch status of corresponding bit in MUX_SWITCH0
Default Value: 0
1
MUX_FW_P1_VPLUS
switch status of corresponding bit in MUX_SWITCH0
Default Value: 0
0
MUX_FW_P0_VPLUS
switch status of corresponding bit in MUX_SWITCH0
Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1548
Section I: Peripheral Group 10
This section encompasses the following chapters: Pulse Density Modulation (PDM) Registers chapter on page 1550 Inter IC Sound (I2S) Registers chapter on page 1569
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1549
29 Pulse Density Modulation (PDM) Registers
This section discusses the Pulse Density Modulation (PDM) block registers. It lists all the registers in mapping tables, in address order.
29.1 Register Details
Register PDM0_CTL PDM0_CLOCK_CTL PDM0_MODE_CTL PDM0_DATA_CTL PDM0_CMD PDM0_TR_CTL PDM0_RX_FIFO_CTL PDM0_RX_FIFO_STATUS PDM0_RX_FIFO_RD PDM0_RX_FIFO_RD_SILENT PDM0_INTR PDM0_INTR_SET PDM0_INTR_MASK PDM0_INTR_MASKED
Address 0x42A20000 0x42A20010 0x42A20014 0x42A20018 0x42A20020 0x42A20040 0x42A20300 0x42A20304 0x42A20308 0x42A2030C 0x42A20F00 0x42A20F04 0x42A20F08 0x42A20F0C
Control Clock control Mode control Data control Command Trigger control RX FIFO control RX FIFO status RX FIFO read RX FIFO silent read Interrupt register Interrupt set register Interrupt mask register Interrupt masked register
Description
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1550
PDM0_CTL
29.1.1 PDM0_CTL
Address = 0x42A20000 Control Address: 0x42A20000 Retention: Retained
Bits
7
6
5
4
SW Access
None
HW Access
None
Name
None [7:4]
Bits
15
14
13
12
SW Access
None
HW Access
None
Name
None [15:12]
Bits
23
22
21
20
SW Access
None
HW Access
None
Name
None [23:18]
Bits
31
30
29
28
SW Access
RW
HW Access
R
Name
ENABLED
3
11
19
27 None None None [30:24]
2
1
RW
R
PGA_R [3:0]
10
9
RW
R
PGA_L [11:8]
18
17
RW
R
STEP_SEL
26
25
0
8
16 RW R SOFT_MUTE 24
Bits
Name
31
ENABLED
17
STEP_SEL
16
SOFT_MUTE
Description
Enables the PDM component: '0': Disabled. '1': Enabled. Default Value: 0
Set fine gain step for smooth PGA or Soft-Mute attenuation transition. '0': 0.13dB '1': 0.26dB (Note: This bit is connected to AR36U12.PDM_CORE2_CFG.SEL_STEP) Default Value: 1
Soft mute function to mute the volume smoothly '0': Disabled. '1': Enabled. (Note: This bit is connected to AR36U12.PDM_CORE_CFG.SOFT_MUTE) Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1551
PDM0_CTL
29.1.1
11 : 8
3 : 0
PDM0_CTL (continued)
PGA_L PGA_R
Left channel PGA gain: +1.5dB/step, -12dB ~ +10.5dB "0": -12 dB "1": -10.5 dB
"15": +10.5 dB (Note: These bits are connected to AR36U12.PDM_CORE_CFG.PGA_L) Default Value: 8
Right channel PGA gain: +1.5dB/step, -12dB ~ +10.5dB "0": -12 dB "1": -10.5 dB
"15" +10.5 dB (Note: These bits are connected to AR36U12.PDM_CORE_CFG.PGA_R) Default Value: 8
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1552
PDM0_CLOCK_CTL
29.1.2 PDM0_CLOCK_CTL
Address = 0x42A20010 Clock control Address: 0x42A20010 Retention: Retained
Bits SW Access HW Access
Name
7
6
None
None
None [7:6]
5
4
RW
R
MCLKQ_CLOCK_DIV [5:4]
3
2
None
None
None [3:2]
1
0
RW
R
CLK_CLOCK_DIV [1:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
RW
HW Access
None
R
Name
None [15:12]
CKO_CLOCK_DIV [11:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
HW Access
None
R
Name
None
SINC_RATE [22:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits 22 : 16
Name SINC_RATE
11 : 8
CKO_CLOCK_DIV
5 : 4
MCLKQ_CLOCK_DIV
Description
SINC Decimation Rate. For details, see the data sheet provided by Archband. Oversampling Ratio = Decimation Rate = 2 X SINC_RATE (Note: These bits are connected to AR36U12.PDM_CORE_CFG.SINC_RATE) Default Value: 32
PDM CKO (FPDM_CKO) clock divider (3rd divider): FPDM_CKO = MCLKQ / (CKO_CLOCK_DIV + 1) Note: To configure "0" to this field is prohibited. (Note: PDM_CKO is configured by MCLKQ_CLOCK_DIV, CLK_CLOCK_DIV and CKO_CLOCK_DIV. ) (Note: These bits are connected to AR36U12.PDM_CORE_CFG.MCLKDIV) Default Value: 3
MCLKQ divider (2nd divider) (Note: These bits are connected to AR36U12.PDM_CORE2_CFG.DIV_MCLKQ) Default Value: 1
0x0: DIVBY1 : Divide by 1
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1553
PDM0_CLOCK_CTL
29.1.2
1 : 0
PDM0_CLOCK_CTL (continued)
CLK_CLOCK_DIV
0x1: DIVBY2 : Divide by 2 (no 50% duty cycle)
0x2: DIVBY3 : Divide by 3 (no 50% duty cycle)
0x3: DIVBY4 : Divide by 4 (no 50% duty cycle)
PDM CLK (FPDM_CLK) (1st divider): This configures a frequency of PDM CLK. The configured frequency is used to operate PDM core. I.e. the frequency is input to MCLKQ_CLOCK_DIV register. Note: configure a frequency of PDM CLK as lower than or equal 50MHz with this divider. Default Value: 0
0x0: DIVBY1 : Divide by 1
0x1: DIVBY2 : Divide by 2 (no 50% duty cycle)
0x2: DIVBY3 : Divide by 3 (no 50% duty cycle)
0x3: DIVBY4 : Divide by 4 (no 50% duty cycle)
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1554
PDM0_MODE_CTL
29.1.3 PDM0_MODE_CTL
Address = 0x42A20014 Mode control Address: 0x42A20014 Retention: Retained
Bits
7
6
5
4
3
SW Access
None
HW Access
None
Name
None [7:3]
Bits
15
14
13
12
11
SW Access
None
HW Access
None
Name
None [15:11]
Bits
23
22
21
20
19
SW Access
None
HW Access
None
Name
None [23:19]
Bits SW Access HW Access
Name
31
30
29
28
27
None
RW
None
R
None [31:29]
HPF_EN_N
2 RW R SWAP_LR
1
0
RW
R
PCM_CH_SET [1:0]
10
9
8
RW
R
S_CYCLES [10:8]
18
17
16
RW
R
CKO_DELAY [18:16]
26
25
24
RW
R
HPF_GAIN [27:24]
Bits
Name
28
HPF_EN_N
27 : 24
HPF_GAIN
18 : 16
CKO_DELAY
Description
Enable high pass filter (active low) '1': Disabled. '0': Enabled. (Note: This bit is connected to AR36U12.PDM_CORE_CFG.ADCHPD) Default Value: 1
Adjust high pass filter coefficients. H(Z) = (1 Z-1 ) / [1 (1- 2 HPF_GAIN) Z-1 ] (Note: These bits are connected to AR36U12.PDM_CORE_CFG.HPGAIN) Default Value: 11
Phase difference from the rising edge of internal sampler clock (CLK_IS) to that of PDM_CKO clock: (Note: These bits are connected to AR36U12.PDM_CORE2_CFG.PDMCKO_DLY) Default Value: 0
0x0: ADV3 : CLK_IS is 3*PDM_CLK period early
0x1: ADV2 : CLK_IS is 2*PDM_CLK period early
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1555
PDM0_MODE_CTL
29.1.3
10 : 8
2 1 : 0
PDM0_MODE_CTL (continued)
S_CYCLES
SWAP_LR PCM_CH_SET
0x2: ADV1 : CLK_IS is 1*PDM_CLK period early
0x3: NO_DELAY : CLK_IS is the same as PDM_CKO
0x4: DLY1 : CLK_IS is 1*PDM_CLK period late
0x5: DLY2 : CLK_IS is 2*PDM_CLK period late
0x6: DLY3 : CLK_IS is 3*PDM_CLK period late
0x7: DLY4 : CLK_IS is 4*PDM_CLK period late
Set time step for gain change during PGA or soft mute operation in number of 1/a sampling rate. (Note: These bits are connected to AR36U12.PDM_CORE_CFG.S_CYCLES) Default Value: 1
0x0: STEP_NUM64 : 64steps
0x1: STEP_NUM96 : 96steps
0x2: STEP_NUM128 : 128steps
0x3: STEP_NUM160 : 160steps
0x4: STEP_NUM192 : 192steps
0x5: STEP_NUM256 : 256steps
0x6: STEP_NUM384 : 384steps
0x7: STEP_NUM512 : 512steps
Input data L/R channel swap: '1': Right/Left channel recording swap '0': No Swap (Note: This bit is connected to AR36U12.PDM_CORE_CFG.LRSWAP) Default Value: 0
Specifies PCM output channels as mono or stereo: (Note: These bits are connected to AR36U12.PDM_CORE2_CFG.PCM_CHSET) Default Value: 3
0x0: DISABLED : Channel disabled
0x1: MONO_L : Mono left channel enable
0x2: MONO_R : Mono right channel enable
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1556
29.1.3
PDM0_MODE_CTL (continued)
0x3: STEREO : Stereo channel enable
PDM0_MODE_CTL
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1557
PDM0_DATA_CTL
29.1.4 PDM0_DATA_CTL
Address = 0x42A20018 Data control Address: 0x42A20018 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:2]
WORD_LEN [1:0]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:9]
9
8
RW
R
BIT_EXTENSION
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
8
BIT_EXTENSION
1 : 0
WORD_LEN
Description
When reception word length is shorter than the word length of RX_FIFO_RD, extension mode of upper bit should be set. '0': Extended by '0' '1': Extended by sign bit (if MSB word is "1", then it is extended by "1", if MSB is "0" then it is extended by "0") Default Value: 0
PCM Word Length in number of bits: (Note: These bits are connected to AR36U12.PDM_CORE2_CFG.PCM_IWL) Default Value: 0
0x0: BIT_LEN16 : 16-bit
0x1: BIT_LEN18 : 18-bit
0x2: BIT_LEN20 : 20-bit
0x3: BIT_LEN24 : 24-bit
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1558
PDM0_CMD
29.1.5 PDM0_CMD
Address = 0x42A20020 Command Address: 0x42A20020 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:1]
STREAM_E N
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
0
STREAM_EN
Description
Enable data streaming flow: '0': Disabled. '1': Enabled. (Note: This bit is connected to AR36U12.PDM_CORE_CFG.PDMA_EN) Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1559
PDM0_TR_CTL
29.1.6 PDM0_TR_CTL
Address = 0x42A20040 Trigger control Address: 0x42A20040 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
HW Access
None
R
Name
None [23:17]
RX_REQ_EN
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
16
RX_REQ_EN
Description
Trigger output ("tr_pdm_rx_req") enable for requests of DMA transfer '0': Disabled. '1': Enabled. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1560
PDM0_RX_FIFO_CTL
29.1.7 PDM0_RX_FIFO_CTL
Address = 0x42A20300 RX FIFO control Address: 0x42A20300 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
TRIGGER_LEVEL [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
RW
HW Access
None
R
R
Name
None [23:18]
FREEZE
CLEAR
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
17
FREEZE
16
CLEAR
7 : 0
TRIGGER_LEVEL
Description
When '1', hardware writes to the RX FIFO have no effect. Freeze will not advance the RX FIFO write pointer.This field is used only for debugging purposes. Default Value: 0
When '1', the RX FIFO and RX_BUF are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. Default Value: 0
Trigger level. When the RX FIFO has more entries than the number of this field, a receiver trigger event is generated. Note: software can configure up to 254 in Mono channel enabled (MODE_CTL.PCM_CH_SET = "1" or "2"), up to 253 in Stereo channel enabled (MODE_CTL.PCM_CH_SET = "3"). Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1561
PDM0_RX_FIFO_STATUS
29.1.8 PDM0_RX_FIFO_STATUS
Address = 0x42A20304 RX FIFO status Address: 0x42A20304 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
USED [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
W
Name
RD_PTR [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
W
Name
WR_PTR [31:24]
Bits 31 : 24
Name WR_PTR
23 : 16
RD_PTR
7 : 0
USED
Description
RX FIFO write pointer: RX FIFO location at which a new data frame is written by the hardware.This field is used only for debugging purposes. Default Value: 0
RX FIFO read pointer: RX FIFO location from which a data frame is read by the host.This field is used only for debugging purposes. Default Value: 0
Number of entries in the RX FIFO. The field value is in the range [0, 255]. When this is zero, the RX FIFO is empty. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1562
PDM0_RX_FIFO_RD
29.1.9 PDM0_RX_FIFO_RD
Address = 0x42A20308 RX FIFO read Address: 0x42A20308 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
DATA [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
DATA [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
W
Name
DATA [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
W
Name
DATA [31:24]
Bits 31 : 0
Name DATA
Description
Data read from the RX FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note: Don't access to this bit while RX_FIFO_CTL.CLEAR is '1'. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1563
PDM0_RX_FIFO_RD_SILENT
29.1.10 PDM0_RX_FIFO_RD_SILENT
Address = 0x42A2030C RX FIFO silent read Address: 0x42A2030C Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
DATA [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
DATA [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
W
Name
DATA [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
W
Name
DATA [31:24]
Bits 31 : 0
Name DATA
Description
Data read from the RX FIFO. Reading a data frame will NOT remove the data frame from the RX FIFO; i.e. behavior is similar to that of a PEEK operation. This field is used only for debugging purposes. Note: Don't access to this bit while RX_FIFO_CTL.CLEAR is '1'. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1564
PDM0_INTR
29.1.11 PDM0_INTR
Address = 0x42A20F00 Interrupt register Address: 0x42A20F00 Retention: Not Retained
Bits
7
6
5
SW Access
HW Access
Name
Bits
15
14
13
SW Access
HW Access
Name
Bits SW Access HW Access
Name
23 None None
None
22 RW1C RW1S
21 RW1C RW1S
RX_UN- RX_OVER-
DERFLOW
FLOW
Bits
31
30
29
SW Access
HW Access
Name
4
3
None
None
None [7:0]
12
11
None
None
None [15:8]
20
19
None
None
None [20:19]
28
27
None
None
None [31:24]
2
1
0
10
9
8
18 RW1C RW1S
RX_NOT_EMP
TY
26
17 None None
None
25
16 RW1C RW1S
RX_TRIGGER
24
Bits
Name
22
RX_UNDERFLOW
21
RX_OVERFLOW
18
RX_NOT_EMPTY
16
RX_TRIGGER
Description
Attempt to read from an empty RX FIFO Default Value: 0
Attempt to write to a full RX FIFO Default Value: 0
RX FIFO is not empty. Default Value: 0
More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in RX_FIFO_CTL. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1565
PDM0_INTR_SET
29.1.12 PDM0_INTR_SET
Address = 0x42A20F04 Interrupt set register Address: 0x42A20F04 Retention: Not Retained
Bits
7
6
5
SW Access
HW Access
Name
Bits
15
14
13
SW Access
HW Access
Name
Bits SW Access HW Access
Name
23 None None
None
22 RW1S
A
21 RW1S
A
RX_UN- RX_OVER-
DERFLOW
FLOW
Bits
31
30
29
SW Access
HW Access
Name
4
3
None
None
None [7:0]
12
11
None
None
None [15:8]
20
19
None
None
None [20:19]
28
27
None
None
None [31:24]
2
1
0
10
9
8
18 RW1S
A RX_NOT_EMP TY
26
17 None None
None
25
16 RW1S
A
RX_TRIGGER
24
Bits
Name
22
RX_UNDERFLOW
21
RX_OVERFLOW
18
RX_NOT_EMPTY
16
RX_TRIGGER
Description
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1566
PDM0_INTR_MASK
29.1.13 PDM0_INTR_MASK
Address = 0x42A20F08 Interrupt mask register Address: 0x42A20F08 Retention: Retained
Bits
7
6
5
SW Access
HW Access
Name
Bits
15
14
13
SW Access
HW Access
Name
Bits SW Access HW Access
Name
23 None None
None
22
21
RW
RW
R
R
RX_UN- RX_OVER-
DERFLOW
FLOW
Bits
31
30
29
SW Access
HW Access
Name
4
3
None
None
None [7:0]
12
11
None
None
None [15:8]
20
19
None
None
None [20:19]
28
27
None
None
None [31:24]
2
1
0
10
9
8
18 RW R RX_NOT_EMP TY
26
17 None None
None
25
16 RW R
RX_TRIGGER
24
Bits
Name
22
RX_UNDERFLOW
21
RX_OVERFLOW
18
RX_NOT_EMPTY
16
RX_TRIGGER
Description
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1567
PDM0_INTR_MASKED
29.1.14 PDM0_INTR_MASKED
Address = 0x42A20F0C Interrupt masked register Address: 0x42A20F0C Retention: Not Retained
Bits
7
6
5
SW Access
HW Access
Name
Bits
15
14
13
SW Access
HW Access
Name
Bits SW Access HW Access
Name
23 None None
None
22
21
R
R
W
W
RX_UN- RX_OVER-
DERFLOW
FLOW
Bits
31
30
29
SW Access
HW Access
Name
4
3
None
None
None [7:0]
12
11
None
None
None [15:8]
20
19
None
None
None [20:19]
28
27
None
None
None [31:24]
2
1
0
10
9
8
18 R W RX_NOT_EMP TY
26
17 None None
None
25
16 R W
RX_TRIGGER
24
Bits
Name
22
RX_UNDERFLOW
21
RX_OVERFLOW
18
RX_NOT_EMPTY
16
RX_TRIGGER
Description
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1568
30 Inter IC Sound (I2S) Registers
This section discusses the Inter IC Sound (I2S) registers. It lists all the registers in mapping tables, in address order.
30.1 Register Details
Register I2S0_CTL I2S0_CLOCK_CTL I2S0_CMD I2S0_TR_CTL I2S0_TX_CTL I2S0_TX_WATCHDOG I2S0_RX_CTL I2S0_RX_WATCHDOG I2S0_TX_FIFO_CTL I2S0_TX_FIFO_STATUS I2S0_TX_FIFO_WR I2S0_RX_FIFO_CTL I2S0_RX_FIFO_STATUS I2S0_RX_FIFO_RD I2S0_RX_FIFO_RD_SILENT I2S0_INTR I2S0_INTR_SET I2S0_INTR_MASK I2S0_INTR_MASKED
Address 0x42A10000 0x42A10010 0x42A10020 0x42A10040 0x42A10080 0x42A10084 0x42A100A0 0x42A100A4 0x42A10200 0x42A10204 0x42A10208 0x42A10300 0x42A10304 0x42A10308 0x42A1030C 0x42A10F00 0x42A10F04 0x42A10F08 0x42A10F0C
Control Clock control Command Trigger control Transmitter control Transmitter watchdog Receiver control Receiver watchdog TX FIFO control TX FIFO status TX FIFO write RX FIFO control RX FIFO status RX FIFO read RX FIFO silent read Interrupt register Interrupt set register Interrupt mask register Interrupt masked register
Description
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1569
I2S0_CTL
30.1.1 I2S0_CTL
Address = 0x42A10000 Control Address: 0x42A10000 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
HW Access
None
Name
None [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
HW Access
None
Name
None [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
RW
None
HW Access
R
R
None
Name
RX_ENABLED
TX_ENABLED
None
Bits
Name
31
RX_ENABLED
30
TX_ENABLED
Description
Enables the I2S RX component: '0': Disabled. '1': Enabled. Default Value: 0
Enables the I2S TX component: '0': Disabled. '1': Enabled. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1570
I2S0_CLOCK_CTL
30.1.2 I2S0_CLOCK_CTL
Address = 0x42A10010 Clock control Address: 0x42A10010 Retention: Retained
Bits
7
6
5
SW Access
None
HW Access
None
Name
None [7:6]
Bits
15
14
13
SW Access
HW Access
Name
Bits
23
22
21
SW Access
HW Access
Name
Bits
31
30
29
SW Access
HW Access
Name
4
12 None None None [15:9]
3
2
RW
R
CLOCK_DIV [5:0]
11
10
20
19
18
None
None
None [23:16]
28
27
26
None
None
None [31:24]
Bits
Name
8
CLOCK_SEL
5 : 0
CLOCK_DIV
Description
Selects clock to be used by I2S: '0': Internal clock ("clk_audio_i2s") '1': External clock ("clk_i2s_if") Default Value: 0
Frequency divisor for generating I2S clock frequency. The selected clock with CLOCK_SEL is divided by this. "0": Bypass "1": 2 x "2": 3 x "3": 4 x ... "62": 63 x "63": 64 x Default Value: 0
1
0
9
8
RW
R
CLOCK_SEL
17
16
25
24
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1571
I2S0_CMD
30.1.3 I2S0_CMD
Address = 0x42A10020 Command Address: 0x42A10020 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:1]
TX_START
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:9]
9
8
RW
R
TX_PAUSE
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
HW Access
None
R
Name
None [23:17]
RX_START
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
16
RX_START
8
TX_PAUSE
0
TX_START
Description
Receiver enable: '0': Disabled. '1': Enabled. Default Value: 0
Pause enable: '0': Disabled (TX FIFO data is sent over I2S). '1': Enabled ("0" data is sent over I2S, instead of TX FIFO data). Default Value: 0
Transmitter enable: '0': Disabled. '1': Enabled. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1572
I2S0_TR_CTL
30.1.4 I2S0_TR_CTL
Address = 0x42A10040 Trigger control Address: 0x42A10040 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
None
RW
HW Access
None
R
Name
None [7:1]
TX_REQ_EN
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
HW Access
None
R
Name
None [23:17]
RX_REQ_EN
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
16
RX_REQ_EN
0
TX_REQ_EN
Description
Trigger output ("tr_i2s_rx_req") enable for requests of DMA transfer in reception '0': Disabled. '1': Enabled. Default Value: 0
Trigger output ("tr_i2s_tx_req") enable for requests of DMA transfer in transmission '0': Disabled. '1': Enabled. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1573
I2S0_TX_CTL
30.1.5 I2S0_TX_CTL
Address = 0x42A10080 Transmitter control Address: 0x42A10080 Retention: Retained
Bits
7
SW Access
RW
HW Access
R
Name MS
6
5
4
3
2
1
0
RW
RW
None
R
R
None
CH_NR [6:4]
B_CLOCK_-
INV
None
Bits SW Access HW Access
Name
15
14
None
None
None [15:14]
13 RW R WD_EN
12 RW R OVHDATA
11 None None None
10 RW R WS_PULSE
9
8
RW
R
I2S_MODE [9:8]
Bits SW Access HW Access
Name
23 None None None
22
21
20
RW
R
WORD_LEN [22:20]
19 None None None
18
17
16
RW
R
CH_LEN [18:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
RW
RW
HW Access
None
R
R
Name
None [31:26]
SCKI_POL SCKO_POL
Bits
Name
25
SCKI_POL
24
SCKO_POL
Description
TX slave bit clock polarity. When this bit is 1, the incoming tx_sck signal is inverted before it is received by the I2S transceiver core. This bit does not affect the internal serial data transmission timing. The word sync (TX_WS) signal is not affected by this bit setting. See TX_CTL.B_CLOCK_INV for more details. Default Value: 0
TX master bit clock polarity. When this bit is 1, the outgoing tx_sck signal is inverted after it has been transmitted from the I2S transceiver core. This bit does not affect the internal serial data transmission timing. The word sync (TX_WS) signal is not affected by this bit setting. '0': When transmitter is in master mode, serial data is transmitted from the falling bit clock edge '1': When transmitter is in master mode, serial data is transmitted from the rising bit clock edge Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1574
I2S0_TX_CTL
30.1.5
22 : 20
18 : 16
13 12
I2S0_TX_CTL (continued)
WORD_LEN
CH_LEN
WD_EN OVHDATA
Word length in number of bits: Note: - When this field is configured to "6" or "7", the length is set to 32-bit (same as "5"). - Don't configure this field as beyond Channel length. (Note: These bits are connected to AR38U12.TX_CFG.TX_IWL) Default Value: 4
0x0: BIT_LEN8 : 8-bit
0x1: BIT_LEN16 : 16-bit
0x2: BIT_LEN18 : 18-bit
0x3: BIT_LEN20 : 20-bit
0x4: BIT_LEN24 : 24-bit
0x5: BIT_LEN32 : 32-bit
Channel length in number of bits: Note: - When this field is configured to "6" or "7", the length is set to 32-bit (same as "5"). - When TDM mode, must be 32-bit length to this field. (Note: These bits are connected to AR38U12.TX_CFG.TX_CHLEN) Default Value: 4
0x0: BIT_LEN8 : 8-bit
0x1: BIT_LEN16 : 16-bit
0x2: BIT_LEN18 : 18-bit
0x3: BIT_LEN20 : 20-bit
0x4: BIT_LEN24 : 24-bit
0x5: BIT_LEN32 : 32-bit
Set watchdog for "tx_ws_in": '0': Disabled. '1': Enabled. Default Value: 0
Set overhead value: '0': Set to '0' '1': Set to '1' (Note: This bit is connected to AR38U12.TX_CFG.TX_OVHDATA) Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1575
I2S0_TX_CTL
30.1.5
10 9 : 8
7 6 : 4
I2S0_TX_CTL (continued)
WS_PULSE I2S_MODE
MS CH_NR
Set WS pulse width in TDM mode: (Note: This bit is connected to AR38U12.TX_CFG.TX_WS_PULSE) Note: When not TDM mode, must be "1". Default Value: 1
0x0: SCK_PERIOD : Pulse width is 1 SCK period
0x1: CH_LENGTH : Pulse width is 1 channel length
Select I2S, left-justified or TDM: (Note: These bits are connected to AR38U12.TX_CFG.TX_I2S_MODE) Default Value: 1
0x0: LEFT_JUSTIFIED : Left Justified
0x1: I2S : I2S mode
0x2: TDM_A : TDM mode A, the 1st Channel align to WSO Rising Edge
0x3: TDM_B : TDM mode B, the 1st Channel align to WSO Rising edge with1 SCK Delay
Set interface in master or slave mode: (Note: This bit is connected to AR38U12.TX_CFG.TX_MS) Default Value: 0
0x0: SLAVE : Slave
0x1: MASTER : Master
Specifies number of channels per frame: Note: only "2channels" is supported during Left Justfied or I2S mode. Hence software must set "1" to this field in the modes. (Note: These bits are connected to AR38U12.TX_CFG.TX_CHSET) Default Value: 1
0x0: CH_NUM1 : 1 channel
0x1: CH_NUM2 : 2 channels
0x2: CH_NUM3 : 3 channels
0x3: CH_NUM4 : 4 channels
0x4: CH_NUM5 : 5 channels
0x5: CH_NUM6 : 6 channels
0x6: CH_NUM7 : 7 channels
0x7: CH_NUM8 : 8 channels
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1576
I2S0_TX_CTL
30.1.5
3
I2S0_TX_CTL (continued)
B_CLOCK_INV
Serial data transmission is advanced by 0.5 SCK cycles. This bit is valid only in TX slave mode. When set to "1", the serial data will be transmitted 0.5 SCK cycles earlier than when set to "0". 1) TX_CTL.SCKI_POL=0 and TX_CTL.B_CLOCK_INV=0: Serial data will be transmitted off the SCK falling edge 2) TX_CTL.SCKI_POL=0 and TX_CTL.B_CLOCK_INV=1: Serial data will be transmitted off the SCK rising edge that is 0.5 SCK cycles before the SCK falling edge in 1) 3) TX_CTL.SCKI_POL=1 and TX_CTL.B_CLOCK_INV=0: Serial data will be transmitted off the SCK rising edge 4) TX_CTL.SCKI_POL=1 and TX_CTL.B_CLOCK_INV=1: Serial data will be transmitted off the SCK falling edge that is 0.5 SCK cycles before the SCK rising edge in 3) (Note that this is only the appearance w.r.t. SCK edge, the actual timing is generated by an internal clock that runs 8x the SCK frequency). The word sync (TX_WS) signal is not affected by this bit setting. Note: When Master mode, must be "0". (Note: This bit is connected to AR38U12.TX_CFG.TX_BCLKINV) Default Value: 0
0x0: FALLING_EDGE_TX : SDO transmitted at SCK falling edge when TX_CTL.SCKI_POL=0
0x1: RISING_EDGE_TX : SDO transmitted at SCK rising edge when TX_CTL.SCKI_POL=0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1577
I2S0_TX_WATCHDOG
30.1.6 I2S0_TX_WATCHDOG
Address = 0x42A10084 Transmitter watchdog Address: 0x42A10084 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
WD_COUNTER [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
WD_COUNTER [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
WD_COUNTER [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
WD_COUNTER [31:24]
Bits 31 : 0
Name WD_COUNTER
Description
Start value of the TX watchdog. With the reset value of 0x0000:0000 the counter is disabled. This is clocked by the AHB-Lite system clock "clk_sys". Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1578
I2S0_RX_CTL
30.1.7 I2S0_RX_CTL
Address = 0x42A100A0 Receiver control Address: 0x42A100A0 Retention: Retained
Bits
7
SW Access
RW
HW Access
R
Name MS
6
5
4
3
2
1
0
RW
RW
None
R
R
None
CH_NR [6:4]
B_CLOCK_-
INV
None
Bits SW Access HW Access
Name
15
14
None
None
None [15:14]
13 RW R WD_EN
12
11
None
None
None [12:11]
10 RW R WS_PULSE
9
8
RW
R
I2S_MODE [9:8]
Bits SW Access HW Access
Name
23
RW
R
BIT_EXTENSION
22
21
20
RW
R
WORD_LEN [22:20]
19 None None
None
18
17
16
RW
R
CH_LEN [18:16]
Bits
31
30
29
28
27
26
25
24
SW Access
None
RW
RW
HW Access
None
R
R
Name
None [31:26]
SCKI_POL SCKO_POL
Bits
Name
25
SCKI_POL
24
SCKO_POL
Description
RX slave bit clock polarity. When this bit is 1, the incoming rx_sck signal is inverted before it is received by the I2S receiver core. This bit does not affect the internal serial data capture timing. The word sync (RX_WS) signal is not affected by this bit setting. '0': When receiver is in slave mode, serial data is sampled on the rising bit clock edge '1': When receiver is in slave mode, serial data is sampled on the falling bit clock edge Default Value: 0
RX master bit clock polarity. When this bit is 1, the outgoing rx_sck signal is inverted after it has been transmitted from the I2S receiver core. This bit does not affect the internal serial data capture timing. The word sync (RX_WS) signal is not affected by this bit setting.See RX_CTL.B_CLOCK_INV for more details. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1579
I2S0_RX_CTL
30.1.7
23 22 : 20
18 : 16
13
I2S0_RX_CTL (continued)
BIT_EXTENSION WORD_LEN
CH_LEN
WD_EN
When reception word length is shorter than the word length of RX_FIFO_RD, extension mode of upper bit should be set. '0': Extended by "0" '1': Extended by sign bit (if MSB word is '1', then it is extended by '1', if MSB is '0' then it is extended by '0') Default Value: 0
Word length in number of bits: Note: - When this field is configured to "6" or "7", the length is set to 32-bit (same as "5"). - Don't configure this field as beyond Channel length. (Note: These bits are connected to AR38U12.RX_CFG.RX_IWL) Default Value: 4
0x0: BIT_LEN8 : 8-bit
0x1: BIT_LEN16 : 16-bit
0x2: BIT_LEN18 : 18-bit
0x3: BIT_LEN20 : 20-bit
0x4: BIT_LEN24 : 24-bit
0x5: BIT_LEN32 : 32-bit
Channel length in number of bits: Note: - When this field is configured to "6" or "7", the length is set to 32-bit (same as "5"). - When TDM mode, must be 32-bit length to this field. (Note: These bits are connected to AR38U12.RX_CFG.RX_CHLEN) Default Value: 4
0x0: BIT_LEN8 : 8-bit
0x1: BIT_LEN16 : 16-bit
0x2: BIT_LEN18 : 18-bit
0x3: BIT_LEN20 : 20-bit
0x4: BIT_LEN24 : 24-bit
0x5: BIT_LEN32 : 32-bit
Set watchdog for "rx_ws_in" '0': Disabled. '1': Enabled. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1580
I2S0_RX_CTL
30.1.7
10 9 : 8
7 6 : 4
I2S0_RX_CTL (continued)
WS_PULSE I2S_MODE
MS CH_NR
Set WS pulse width in TDM mode: (Note: This bit is connected to AR38U12.RX_CFG.RX_WS_PULSE) Note: When not TDM mode, must be "1". Default Value: 1
0x0: SCK_PERIOD : Pulse width is 1 SCK period
0x1: CH_LENGTH : Pulse width is 1 channel length
Select I2S, left-justified or TDM: (Note: These bits are connected to AR38U12.RX_CFG.RX_I2S_MODE) Default Value: 1
0x0: LEFT_JUSTIFIED : Left Justified
0x1: I2S : I2S mode
0x2: TDM_A : TDM mode A, the 1st Channel align to WSO Rising Edge
0x3: TDM_B : TDM mode B, the 1st Channel align to WSO Rising edge with1 SCK Delay
Set interface in master or slave mode: (Note: This bit is connected to AR38U12.TX_CFG.RX_MS) Default Value: 0
0x0: SLAVE : Slave
0x1: MASTER : Master
Specifies number of channels per frame: Note: only "2channels" is supported during Left Justfied or I2S mode. Hence software must set "1" to this field in the modes. (Note: These bits are connected to AR38U12.RX_CFG.RX_CHSET) Default Value: 1
0x0: CH_NUM1 : 1 channel
0x1: CH_NUM2 : 2 channels
0x2: CH_NUM3 : 3 channels
0x3: CH_NUM4 : 4 channels
0x4: CH_NUM5 : 5 channels
0x5: CH_NUM6 : 6 channels
0x6: CH_NUM7 : 7 channels
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1581
I2S0_RX_CTL
30.1.7
3
I2S0_RX_CTL (continued)
B_CLOCK_INV
0x7: CH_NUM8 : 8 channels
Serial data capture is delayed by 0.5 SCK cycles. This bit is valid only in RX master mode. When set to "1", the serial data will be captured 0.5 SCK cycles later than when set to "0". 1) RX_CTL.SCKO_POL=0 and RX_CTL.B_CLOCK_INV=0: Serial data will be captured by the SCK rising edge 2) RX_CTL.SCKO_POL=0 and RX_CTL.B_CLOCK_INV=1: Serial data will be captured by the SCK falling edge that is 0.5 SCK cycles after the SCK rising edge in 1) 3) RX_CTL.SCKO_POL=1 and RX_CTL.B_CLOCK_INV=0: Serial data will be captured by the SCK falling edge 4) RX_CTL.SCKO_POL=1 and RX_CTL.B_CLOCK_INV=1: Serial data will be captured by the SCK rising edge that is 0.5 SCK cycles after the SCK falling edge in 3) (Note that this is only the appearance w.r.t. SCK edge, the actual capture timing is derived from an internal clock that runs 8x the SCK frequency). The word sync (RX_WS) signal is not affected by this bit setting. Note: When Slave mode, must be "0". (Note: This bit is connected to AR38U12.TX_CFG.RX_BCLKINV) Default Value: 0
0x0: RISING_EDGE_RX : SDI received at SCK rising edge when RX_CTL.SCKO_POL=0
0x1: FALLING_EDGE_RX : SDI received at SCK falling edge when RX_CTL.SCKO_POL=0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1582
I2S0_RX_WATCHDOG
30.1.8 I2S0_RX_WATCHDOG
Address = 0x42A100A4 Receiver watchdog Address: 0x42A100A4 Retention: Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
WD_COUNTER [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
RW
HW Access
R
Name
WD_COUNTER [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
RW
HW Access
R
Name
WD_COUNTER [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
RW
HW Access
R
Name
WD_COUNTER [31:24]
Bits 31 : 0
Name WD_COUNTER
Description
Start value of the RX watchdog. With the reset value of 0x0000:0000 the counter is disabled. This is clocked by the AHB-Lite system clock "clk_sys". Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1583
I2S0_TX_FIFO_CTL
30.1.9 I2S0_TX_FIFO_CTL
Address = 0x42A10200 TX FIFO control Address: 0x42A10200 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
TRIGGER_LEVEL [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
RW
HW Access
None
R
R
Name
None [23:18]
FREEZE
CLEAR
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
17
FREEZE
16
CLEAR
7 : 0
TRIGGER_LEVEL
Description
When '1', hardware reads from the TX FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer. This field is used only for debugging purposes. Default Value: 0
When '1', the TX FIFO and TX_BUF are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. Default Value: 0
Trigger level. When the TX FIFO has less entries than the number of this field, a transmitter trigger event is generated. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1584
I2S0_TX_FIFO_STATUS
30.1.10 I2S0_TX_FIFO_STATUS
Address = 0x42A10204 TX FIFO status Address: 0x42A10204 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
USED [7:0]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:9]
9
8
R
W
USED
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
W
Name
RD_PTR [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
W
Name
WR_PTR [31:24]
Bits 31 : 24
Name WR_PTR
23 : 16
RD_PTR
8 : 0
USED
Description
TX FIFO write pointer: FIFO location at which a new data frame is written by the host. This field is used only for debugging purposes. Default Value: 0
TX FIFO read pointer: FIFO location from which a data frame is read by the hardware.This field is used only for debugging purposes. Default Value: 0
Number of entries in the TX FIFO. The field value is in the range [0, 256]. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1585
I2S0_TX_FIFO_WR
30.1.11 I2S0_TX_FIFO_WR
Address = 0x42A10208 TX FIFO write Address: 0x42A10208 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
W
HW Access
R
Name
DATA [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
W
HW Access
R
Name
DATA [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
W
HW Access
R
Name
DATA [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
W
HW Access
R
Name
DATA [31:24]
Bits 31 : 0
Name DATA
Description
Data written into the TX FIFO. Behavior is similar to that of a PUSH operation. Note: Don't access to this register while TX_FIFO_CTL.CLEAR is '1'. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1586
I2S0_RX_FIFO_CTL
30.1.12 I2S0_RX_FIFO_CTL
Address = 0x42A10300 RX FIFO control Address: 0x42A10300 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
RW
HW Access
R
Name
TRIGGER_LEVEL [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
None
HW Access
None
Name
None [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
None
RW
RW
HW Access
None
R
R
Name
None [23:18]
FREEZE
CLEAR
Bits
31
30
29
28
27
26
25
24
SW Access
None
HW Access
None
Name
None [31:24]
Bits
Name
17
FREEZE
16
CLEAR
7 : 0
TRIGGER_LEVEL
Description
When '1', hardware writes to the RX FIFO have no effect. Freeze will not advance the RX FIFO write pointer. This field is used only for debugging purposee. Default Value: 0
When '1', the RX FIFO and RX_BUF are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period. Default Value: 0
Trigger level. When the RX FIFO has more entries than the number of this field, a receiver trigger event is generated. Note: software can configure up to 253 in I2S mode or Left Justified (RX_CTL.I2S_MODE = "0" or "1"). In TDM mode (RX_CTL.I2S_MODE = "2" or "3"), it can configure up to [256 - (RX_CTL.CH_NR+2)]. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1587
I2S0_RX_FIFO_STATUS
30.1.13 I2S0_RX_FIFO_STATUS
Address = 0x42A10304 RX FIFO status Address: 0x42A10304 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
USED [7:0]
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:9]
9
8
R
W
USED
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
W
Name
RD_PTR [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
W
Name
WR_PTR [31:24]
Bits 31 : 24
Name WR_PTR
23 : 16
RD_PTR
8 : 0
USED
Description
RX FIFO write pointer: FIFO location at which a new data frame is written by the hardware. This field is used only for debugging purposes. Default Value: 0
RX FIFO read pointer: FIFO location from which a data frame is read by the host. This field is used only for debugging purposes. Default Value: 0
Number of entries in the RX FIFO. The field value is in the range [0, 256]. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1588
I2S0_RX_FIFO_RD
30.1.14 I2S0_RX_FIFO_RD
Address = 0x42A10308 RX FIFO read Address: 0x42A10308 Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
DATA [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
DATA [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
W
Name
DATA [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
W
Name
DATA [31:24]
Bits 31 : 0
Name DATA
Description
Data read from the RX FIFO. Reading a data frame will remove the data frame from the RX FIFO; i.e. behavior is similar to that of a POP operation. Notes: - Don't access to this register while RX_FIFO_CTL.CLEAR is '1'. - Two stored data may be not valid after CMD.RX_START is set '1'. Therefore we recommend software discard those data. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1589
I2S0_RX_FIFO_RD_SILENT
30.1.15 I2S0_RX_FIFO_RD_SILENT
Address = 0x42A1030C RX FIFO silent read Address: 0x42A1030C Retention: Not Retained
Bits
7
6
5
4
3
2
1
0
SW Access
R
HW Access
W
Name
DATA [7:0]
Bits
15
14
13
12
11
10
9
8
SW Access
R
HW Access
W
Name
DATA [15:8]
Bits
23
22
21
20
19
18
17
16
SW Access
R
HW Access
W
Name
DATA [23:16]
Bits
31
30
29
28
27
26
25
24
SW Access
R
HW Access
W
Name
DATA [31:24]
Bits 31 : 0
Name DATA
Description
Data read from the RX FIFO. Reading a data frame will NOT remove the data frame from the RX FIFO; i.e. behavior is similar to that of a PEEK operation. This field is used only for debugging purposes. Notes: - Don't access to this register while RX_FIFO_CTL.CLEAR is '1'. - Two stored data may be not valid after CMD.RX_START is set '1'. Therefore we recommend software discard those data. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1590
I2S0_INTR
30.1.16 I2S0_INTR
Address = 0x42A10F00 Interrupt register Address: 0x42A10F00 Retention: Not Retained
Bits SW Access HW Access
Name
7 None None
None
6
RW1C
RW1S
TX_UNDERFLOW
5
RW1C
RW1S
TX_OVERFLOW
4 RW1C RW1S
TX_EMPTY
3
2
None
None
None [3:2]
1
RW1C
RW1S
TX_NOT_FULL
0
RW1C
RW1S
TX_TRIGGER
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:9]
9
8
RW1C
RW1S
TX_WD
Bits SW Access HW Access
Name
23 None None
None
22 RW1C RW1S
21 RW1C RW1S
RX_UN- RX_OVER-
DERFLOW
FLOW
20 None None
None
19 RW1C RW1S
RX_FULL
18
RW1C
RW1S
RX_NOT_EMP
TY
17 None None
None
16 RW1C RW1S
RX_TRIGGER
Bits
31
30
29
28
27
26
25
24
SW Access
None
RW1C
HW Access
None
RW1S
Name
None [31:25]
RX_WD
Bits
Name
24
RX_WD
22
RX_UNDERFLOW
21
RX_OVERFLOW
19
RX_FULL
18
RX_NOT_EMPTY
16
RX_TRIGGER
8
TX_WD
Description
Triggers (sets to '1') when the Rx watchdog event occurs. Default Value: 0
Attempt to read from an empty RX FIFO. Default Value: 0
Attempt to write to a full RX FIFO. Default Value: 0
RX FIFO is full. Default Value: 0
RX FIFO is not empty. Default Value: 0
More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in RX_FIFO_CTRL. Default Value: 0
Triggers (sets to '1') when the Tx watchdog event occurs. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1591
I2S0_INTR
30.1.16 I2S0_INTR (continued)
6
TX_UNDERFLOW
Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and
TX_EMPTY is '1'.
Default Value: 0
5
TX_OVERFLOW
Attempt to write to a full TX FIFO.
Default Value: 0
4
TX_EMPTY
TX FIFO is empty; i.e. it has 0 entries. Default Value: 0
1
TX_NOT_FULL
TX FIFO is not full. Default Value: 0
0
TX_TRIGGER
Less entries in the TX FIFO than the value specified by TRIGGER_LEVEL in TX_FIFO_CTRL. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1592
I2S0_INTR_SET
30.1.17 I2S0_INTR_SET
Address = 0x42A10F04 Interrupt set register Address: 0x42A10F04 Retention: Not Retained
Bits SW Access HW Access
Name
7 None None
None
6
RW1S
A
TX_UNDERFLOW
5
RW1S
A
TX_OVERFLOW
4 RW1S
A
TX_EMPTY
3
2
None
None
None [3:2]
1
RW1S
A
TX_NOT_FULL
0
RW1S
A
TX_TRIGGER
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:9]
9
8
RW1S
A
TX_WD
Bits SW Access HW Access
Name
23 None None
None
22 RW1S
A
21 RW1S
A
RX_UN- RX_OVER-
DERFLOW
FLOW
20 None None
None
19 RW1S
A
RX_FULL
18
RW1S
A
RX_NOT_EMP
TY
17 None None
None
16 RW1S
A
RX_TRIGGER
Bits
31
30
29
28
27
26
25
24
SW Access
None
RW1S
HW Access
None
A
Name
None [31:25]
RX_WD
Bits
Name
24
RX_WD
22
RX_UNDERFLOW
21
RX_OVERFLOW
19
RX_FULL
18
RX_NOT_EMPTY
16
RX_TRIGGER
8
TX_WD
Description
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1593
I2S0_INTR_SET
30.1.17 I2S0_INTR_SET (continued)
6
TX_UNDERFLOW
Write with '1' to set corresponding bit in interrupt request register.
Default Value: 0
5
TX_OVERFLOW
Write with '1' to set corresponding bit in interrupt request register.
Default Value: 0
4
TX_EMPTY
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
1
TX_NOT_FULL
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
0
TX_TRIGGER
Write with '1' to set corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1594
I2S0_INTR_MASK
30.1.18 I2S0_INTR_MASK
Address = 0x42A10F08 Interrupt mask register Address: 0x42A10F08 Retention: Retained
Bits SW Access HW Access
Name
7 None None
None
6
RW
R
TX_UNDERFLOW
5
RW
R
TX_OVERFLOW
4 RW R
TX_EMPTY
3
2
None
None
None [3:2]
1
RW
R
TX_NOT_FULL
0
RW
R
TX_TRIGGER
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:9]
9
8
RW
R
TX_WD
Bits SW Access HW Access
Name
23 None None
None
22
21
RW
RW
R
R
RX_UN- RX_OVER-
DERFLOW
FLOW
20 None None
None
19 RW R
RX_FULL
18
RW
R
RX_NOT_EMP
TY
17 None None
None
16 RW R
RX_TRIGGER
Bits
31
30
29
28
27
26
25
24
SW Access
None
RW
HW Access
None
R
Name
None [31:25]
RX_WD
Bits
Name
24
RX_WD
22
RX_UNDERFLOW
21
RX_OVERFLOW
19
RX_FULL
18
RX_NOT_EMPTY
16
RX_TRIGGER
8
TX_WD
Description
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
Mask bit for corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1595
I2S0_INTR_MASK
30.1.18 I2S0_INTR_MASK (continued)
6
TX_UNDERFLOW
Mask bit for corresponding bit in interrupt request register.
Default Value: 0
5
TX_OVERFLOW
Mask bit for corresponding bit in interrupt request register.
Default Value: 0
4
TX_EMPTY
Mask bit for corresponding bit in interrupt request register. Default Value: 0
1
TX_NOT_FULL
Mask bit for corresponding bit in interrupt request register. Default Value: 0
0
TX_TRIGGER
Mask bit for corresponding bit in interrupt request register. Default Value: 0
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
1596
I2S0_INTR_MASKED
30.1.19 I2S0_INTR_MASKED
Address = 0x42A10F0C Interrupt masked register Address: 0x42A10F0C Retention: Not Retained
Bits SW Access HW Access
Name
7 None None
None
6
R
W
TX_UNDERFLOW
5
R
W
TX_OVERFLOW
4 R W
TX_EMPTY
3
2
None
None
None [3:2]
1
R
W
TX_NOT_FULL
0
R
W
TX_TRIGGER
Bits
15
14
13
12
11
10
SW Access
None
HW Access
None
Name
None [15:9]
9
8
R
W
TX_WD
Bits SW Access HW Access
Name
23 None None
None
22
21
R
R
W
W
RX_UN- RX_OVER-
DERFLOW
FLOW
20 None None
None
19 R W
RX_FULL
18
R
W
RX_NOT_EMP
TY
17 None None
None
16 R W
RX_TRIGGER
Bits
31
30
29
28
27
26
25
24
SW Access
None
R
HW Access
None
W
Name
None [31:25]
RX_WD
Bits
Name
24
RX_WD
22
RX_UNDERFLOW
21
RX_OVERFLOW
19
RX_FULL
18
RX_NOT_EMPTY
16
RX_TRIGGER
8
TX_WD
Description
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
Logical and of corresponding request and mask bits. Default Value: 0
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30.1.19 I2S0_INTR_MASKED (continued)
6
TX_UNDERFLOW
Logical and of corresponding request and mask bits.
Default Value: 0
5
TX_OVERFLOW
Logical and of corresponding request and mask bits.
Default Value: 0
4
TX_EMPTY
Logical and of corresponding request and mask bits. Default Value: 0
1
TX_NOT_FULL
Logical and of corresponding request and mask bits. Default Value: 0
0
TX_TRIGGER
Logical and of corresponding request and mask bits. Default Value: 0
I2S0_INTR_MASKED
PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers TRM, Document Number: 002-20777 Rev. *F
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Section J: System Registers
See the following documentation available at Arm® website for the details of Cortex®- M4 and Cortex®-M0+ system registers. Cortex®-M4 Technical Reference Manual Cortex®-M0+ Technical Reference Manual
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Revision History
Revision History
Document Title: PSoC 6 MCU: CY8C62x6, CY8C62x7 Registers Technical Reference Manual (TRM)
Document Number: 002-20777
Revision ECN# Issue Date
Description of Change
**
5855453 08/17/2017 Specification for new silicon
*A
6032757 01/31/2018 Updated all registers
*B
6155258
05/03/2018
Approximately 50% size reduced. The registers TRM is consolidated into a single document instead of three separate documents.
*C
6406758 12/21/2018 Document size reduction.
Changed title
*D
6657179 08/22/2019
Updated Peripheral Registers
Renamed Energy Profiler Registers to Profiler Registers
*E
6683263 09/27/2019
Updated title
*F
6923903
07/24/2020 Added CRYPTO chapter.
Updated SRSS, MCWDT, GPIO, LPCOMP, FLASH and USB chapters.
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