See the security reference manual for this chip for a full list of security features. 10× tamper pins (up to 5 active or 10 passive) Voltage and Temperature tamper detection 64 kB Secure RAM (can be erased via tamper detection) System Control • 2× I2C tightly coupled with Cortex-M4 cores (1× per Cortex M4F core)
NXP Semiconductors Data Sheet: Technical Data Document Number: IMX8QXPIEC Rev. 0, 05/2020 MIMX8QXnAVLFZAC MIMX8DXnAVLFZAC i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors Package Information 21 x 21 mm package case outline Ordering Information See Section 1.1Table 2 on page 5 1 Introduction This data sheet contains specifications for the i.MX 8QuadXPlus and 8DualXPlus processors, which, along with the i.MX 8DualX processor , comprise the i.MX 8X Family (for i.MX 8DualX specifications, see i.MX 8DualX Industrial Processors [IMX8DXIEC]). The i.MX 8X processors consist of three to five Arm cores (two to four Arm Cortex®-A35 and one Cortex®-M4F). All devices include separate GPU and VPU subsystems as well as a failover-ready display controller. Advanced multicore audio processing is supported by the Arm cores and a high performance Tensilica® HiFi 4 DSP for pre- and post-audio processing as well as voice recognition. The i.MX 8X Family supports up to three displays with multiple display output options, including parallel, MIPI-DSI, and LVDS. Memory interfaces for this device include: · LPDDR4 (no error correcting code [ECC]) · DDR3L (optional ECC) 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 System Controller Firmware (SCFW) Requirements5 1.3 Related resources . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 Special Signal Considerations. . . . . . . . . . . . . . . . 14 3.2 Recommended Connections for Unused Interfaces14 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 Chip-level conditions . . . . . . . . . . . . . . . . . . . . . . . 15 4.2 Power supplies requirements and restrictions. . . . 25 4.3 PLL electrical characteristics . . . . . . . . . . . . . . . . . 28 4.4 On-chip oscillators. . . . . . . . . . . . . . . . . . . . . . . . . 31 4.5 I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 34 4.6 I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 41 4.7 Output Buffer Impedance Parameters. . . . . . . . . . 43 4.8 System Modules Timing . . . . . . . . . . . . . . . . . . . . 48 4.9 General-Purpose Media Interface (GPMI) Timing . 52 4.10 External Peripheral Interface Parameters . . . . . . . 61 4.11 Analog-to-digital converter (ADC) . . . . . . . . . . . . 109 5 Boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . 112 5.1 Boot mode configuration pins . . . . . . . . . . . . . . . 112 5.2 Boot devices interfaces allocation . . . . . . . . . . . . 112 6 Package information and contact assignments . . . . . . 114 6.1 FCPBGA, 21 x 21 mm, 0.8 mm pitch . . . . . . . . . 114 7 Release Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 · 2× Quad SPI or 1× Octal SPI (FlexSPI) · eMMC 5.1, RAW NAND, and SD 3.0 NXP reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2018-2020 NXP B.V. Introduction A wide range of peripheral I/Os such as CAN, parallel or MIPI CSI camera input, Gigabit Ethernet, USB 2.0 OTG, USB 3.0 (8QuadXPlus/8DualXPlus only), ADC, and PCIe 3.0 provide impressive flexibility. The i.MX 8QuadXPlus/8DualXPlus processors offer numerous advanced features as shown in this table. Table 1. i.MX 8QuadXPlus/8DualXPlus advanced features Function Multicore architecture provides 2× 4× Cortex-A35 and 1× Cortex-M4F cores Graphics Processing Unit (GPU) Video Processing Unit (VPU) Tensilica HiFi 4 DSP for pre- and post-processing Feature AArch64 for 64-bit support and new architectural features AArch32 for full backward compatibility with ARMv7 Cortex-A35 cores support ARM virtualization extensions. Cortex-M4F cores for real-time applications 4× Vec4 shaders with 16 execution units optimized for higher performance Supports OpenGL 3.0, 2.1,; OpenGL ES 3.1, 3.0, 2.0, and 1.1; OpenCL 1.2 Full Profile and 1.1; OpenVG 1.1; and Vulkan High-performance 2D Blit Engine H.265 decode (4Kp30) H.264 decode (4Kp30) WMV9/VC-1 imple decode MPEG 1 and 2 decode AVS decode MPEG4.2 ASP, H.263, Sorenson Spark decode Divx 3.11 including GMC decode ON2/Google VP6/VP8 decode RealVideo 8/9/10 decode JPEG and MJPEG decode H.264 encode (1080p30) 640 MHz Fixed-point and vector-floating-point support 32 KB instruction cache, 48 KB data cache, 512 KB SRAM (448 KB of OCRAM and 64 KB of TCM) i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 2 NXP Semiconductors Introduction Table 1. i.MX 8QuadXPlus/8DualXPlus advanced features (continued) Memory Function Display Controller Display I/O Camera I/O and video Security System Control Feature 32-bit LPDDR4 @1200 MHz 40-bit DDR3L @933 MHz (ECC option) 1× Quad SPI which can be used to connect to an FPGA 2× Quad SPI or 1× Octal SPI (FlexSPI) for fast boot from SPI NOR flash 2× SD 3.0 card interfaces (note: if eMMC is used, then 1× SD 3.0 available in IOMUX) 1× eMMC5.1/SD3.0 (note: use of eMMC will restrict SD card availability to 1× SD 3.0 due to IOMUX restrictions) RAW NAND (62-bit ECC support via BCH-62 module) Supports up to 3 independent displays (2× MIPI or LVDS + 1× Parallel) Up to 18-layer composition Complementary 2D blitting engines and online warping functionality Integrated Failover Path (SafeAssure) to ensure display content stays valid even in event of a software failure Two MIPI-DSI/LVDS Combo PHYs (each up to 1080p60): Each single PHY can either be a 4-lane MIPI-DSI or a 4-lane channel LVDS interface for a total of 2 display interfaces. In combination, the two PHYs can be configured to be a single dual-channel LVDS interface. 1× 24-bit parallel LCD up to 720p60 (DDR bandwidth might limit the available resolution). 1× MIPI-CSI with 4-lanes 1× 8-bit/10-bit parallel CSI Advanced High Assurance Boot (AHAB) secure & encrypted boot Random Number Generator with a high-quality entropy source generator and Hash_DRBG (based on hash functions) RSA up to 4096, Elliptic Curve up to 1023 AES-128/192/256, DES, 3DES, MD5, SHA-1, SHA-224/256/384/512 Dedicated Security Controller for Flashless SHE and HSM support, Trustzone, RTIC Built-in ECDSA/DSA protocol support See the security reference manual for this chip for a full list of security features. 10× tamper pins (up to 5 active or 10 passive) Voltage and Temperature tamper detection 64 kB Secure RAM (can be erased via tamper detection) · 2× I2C tightly coupled with Cortex-M4 cores (1× per Cortex M4F core) · The tightly coupled M4 I2C ports cannot be used for general-purpose use · System Control Unit (SCU): · Power control, clocks, reset · Boot ROMs · PMIC interface · Resource Domain Controller i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 3 Introduction Table 1. i.MX 8QuadXPlus/8DualXPlus advanced features (continued) Function I/O Packaging Feature 1× PCIe 3.0 (1-lane) with L1 substate support 1× USBOTG 3.0 with PHY--USB 3.0 can be used as USB 2.0 1× USBOTG 2.0 (with PHY) 2× 1Gb Ethernet with AVB (can be used as 10/100 Mbps ENET with AVB) 3× CAN/CAN-FD Note: Legacy CAN mode supports both Mailbox (MB) and RX FIFO (with DMA support) operation. Flexible Data (FD) mode supports MB operation only. There is no enhanced RX FIFO or DMA support in FD mode. 6× UARTs: · 4× UARTs (3× with hardware flow control) · 1× UART tightly coupled with Cortex-M4F cores · 1× SCU UART (Note: SCU UART is dedicated to the SCU and not available for general use) 10× I2C (note that there are two types of I2C: High-speed I2C ports with DMA support, and low-speed I2C ports with no DMA support, which are used in conjunction with a specific PHY interface--for example, for touchscreen): · 4× I2C: High Speed, DMA support · 4× I2C: Low Speed, no DMA support · 1× I2C: PMIC control (dedicated) · 1× I2C: Cortex M4F (dedicated) Note: I2C ports associated with a PHY (e.g. MIPI DSI) can be used generally but require the PHY to be powered on even if the PHY interface itself is not used. 4× SAI (SAI0 and SAI1 are transmit/receive; SAI2 and SAI3 are receive only) 1× Enhanced Serial Audio Interface (ESAI) 2× ASRC (Asynchronous Sample Rate Converter) (note: no I/O signals are directly connected to this module) 1× SPDIF (Tx and Rx) 1× 6-channel ADC converter 3.3 V/1.8 V GPIO 4× PWM channels 1× 6×8 KPP (Key Pad Port) 1× MQS (Medium Quality Sound) 4× SPI Case FCPBGA 21 x 21 mm, 0.8 mm pitch i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 4 NXP Semiconductors 1.1 Ordering Information For ordering information, contact an NXP representative at nxp.com. Introduction Part Number Table 2. i.MX 8QuadXPlus Orderable part numbers Options Cortex-A35 Speed Grade Cortex-M4F Speed Grade Package MIMX8QX6CVLFZAC With GPU, VPU, 24-bit Parallel 1.2 GHz LCD, DSP 264 MHz 21 mm X 21 mm, 0.8 mm pitch, FCPBGA (lidded) MIMX8QX5CVLFZAC With GPU, VPU, 24-bit Parallel 1.2 GHz LCD 264 MHz 21 mm X 21 mm, 0.8 mm pitch, FCPBGA (lidded) Table 3. i.MX 8DualXPlus Orderable part numbers Part Number MIMX8DX6CVLFZAC Options With GPU, VPU, 24-bit Parallel LCD, DSP Cortex-A35 Cortex-M4F Speed Speed Grade Grade Package 1.2 GHz 264 MHz 21 mm X 21 mm, 0.8 mm pitch, FCPBGA (lidded) MIMX8DX5CVLFZAC With GPU, VPU, 24-bit Parallel LCD 1.2 GHz 264 MHz 21 mm X 21 mm, 0.8 mm pitch, FCPBGA (lidded) 1.2 System Controller Firmware (SCFW) Requirements The i.MX 8 and 8X families require a minimum SCFW release version for correct operation and to prevent potential reliability issues. The SCFW is released as part of a Board Support Package (e.g. Linux, Android) which may vary in version number for a specific BSP. For example, NXP Yocto Linux release 4.14.98_2.3.0 contains SCFW version 1.3.0, NXP Yocto Linux release 4.14.98_2.0.0 GA contains SCFW version 1.2.10, whereas NXP Yocto Linux release 4.14.78_1.0.0GA contains SCFW version 1.1.10. i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 5 Architectural Overview The released SCFW version associated within each BSP is the minimum version required to correctly support the wider BSP functionality. Customers should always check that they are using the specific SCFW binary delivered within their chosen BSP release. Customers should not mix newer BSP versions with older revisions of the SCFW. 1.3 Related resources Table 4. Related resources Type Reference manual Data sheet Chip Errata Package drawing Hardware guide Description The i.MX 8DualX/8DualXPlus/8QuadXPlus Applications Processor Reference Manual (IMX8DQXPRM) contains a comprehensive description of the structure and function (operation) of the SoC. This data sheet includes electrical characteristics and signal connections. The chip mask set errata provides additional and/or corrective information for a particular device mask set. Package dimensions are provided in Section 6, "Package information and contact assignments"." Contact an NXP representative for access. 2 Architectural Overview The following subsections provide an architectural overview of the i.MX 8QuadXPlus/8DualXPlus processor system. i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 6 NXP Semiconductors 2.1 Block Diagram The following figure shows the functional modules in the processor system. Architectural Overview 1x UART 1x I2C 1x GPIO 10/100/1000M Ethernet + AVB 1x USB 3.0 PHY 1x USBOTG 2.0 OTG & PHY 1x eMMC 5.1 / SD 3.0 2x SD 3.0 (UHS-I) RAW / ONFI 3.2 NAND Flash 2x Quad SPI / 1x Octal SPI NOR Flash 4x4 Keypad 32-bit GPIO I2C w/ DMA UART (5 Mb/s) CAN / CAN-FD ADC (6 channels) SPDIF TX / RX ESAI TX / RX MQS L/R 2x SAI TX / RX 2x SAI RX 24M and 32k XTALOSC Sources User CM4 Complex M4 Platform M4 CPU nvic fpu mpu MMCAU MCM 16KB code$ 16KB system$ 256KB TCM w/ ECC CPU Platform 4x ARM Cortex-A35 NEON VFP 32KB I$ 32KB D$ 512KB L2 w/ ECC TrustZone LPIT LPUART INTs LPI2C WDOG RGPIO PWM 2x MU Connectivity Subsystem NAND USB3 2x uSDHC 2x USB2 2x ENET Internal Memory OCRAM (256KB) Low Speed I/O (LSIO) Subsystem IEE 4x PWM KPP 2x FlexSPI 14x MU 5x GPT 8x GPIO ESAI ASRC SPDIF SAI GPT ASRC ACM MQS AUDMIX 4x SAI PWM 4x LPSPI 4x LPUART 2x FTM LCDIF 3x FlexCAN 4x LPI2C 1x ADC (4ch) 4x eDMA Audio DMA (ADMA) Subsystem IRQs System Control Unit SCU CM4 Complex M4 Platform M4 CPU nvic fpu mpu MMCAU MCM 16KB code$ 16KB system$ 256KB TCM w/ ECC LPIT LPUART INTs LPI2C WDOG RGPIO PWM 2x MU JTAGC Debug DAP, CTI, etc Boot ROM HAB PMIC I/F IOMUX Clock, Reset Power Mgmt RDC Tempmon Security SNVS SECO OTP ADM CAAM Security Controller (M0+) Memories 2x FlexSPI NAND CTRL (BCH62) External Memory Interface PG PG BN PG DDR Controller SSI Bus High Speed I/O Subsystem PCIe PHY Imaging MJPEG MJPEG ISI DEC ENC Display Controller DPU Graphics Processing Unit GPU Video Processing Unit VPU Parallel I/F (in ADMA SS) LPI2C 2x LVDS / MIPI-DSI LPI2C 1x MIPI CSI2 LPI2C Parallel I/F LPI2C DSP Core (part of ADMA SS) HIFI4 DSP 32KB I$ 48KB D$ 512KB SRAM 64KB TCM 32-bit LPDDR4 (no ECC) @1200 MHz 40-bit DDR3L (w/ ECC) @933 MHz x1 PCIe 3.0 (1 lane) 24-bit LCD Parallel Display 1x I2C MIPI / LVDS Combo 1x I2C MIPI-CSI2 (4-lanes) 1x I2C 8/10-bit Parallel Camera 1x I2C 1x UART 1x I2C 1x GPIO Dedicated RNG Tamper Detection Secure RTC Secure JTAG Ciphers (ECC, RSA) 64k Secure RAM Mult-format Decode H.265 Dec (4k30) H.264 Dec (1080p60) H.264 Enc (1080p30) 4 shaders Vulkan, OGLES 3.1, OCL 1.2, VG 1.1 2D Blit Engine Figure 1. i.MX 8QuadXPlus/8DualXPlus System Block Diagram i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 7 Modules List 3 Modules List The i.MX 8QuadXPlus/8DualXPlus processors contain a variety of digital and analog modules. This table describes the processor modules in alphabetical order. Table 5. i.MX 8QuadXPlus/8DualXPlus modules list Block Mnemonic ADC APBH-DMA A35 ASRC BCH-62 CAAM CTI CTM DAP DC DDR Controller DPR Block Name Brief Description Analog-to-Digital Converter The analog-to-digital converter (ADC) is a successive approximation ADC designed for operation within a SoC. NAND Flash and BCH ECC DMA Controller The AHB-to-APBH bridge provides the chip with a peripheral attachment bus running on the AHB's HCLK, which includes the AHB-to-APB PIO bridge for a memory-mapped I/O to the APB devices, as well as a central DMA facility for devices on this bus and a vectored interrupt controller for the Arm core. Arm (CPU1) 24x Cortex-A35 CPUs with a 32KB L1 instruction cache and a 32 KB data cache. The CPUs share a 512 KB L2 cache. Asynchronous Sample Rate Converter The Asynchronous Sample Rate Converter (ASRC) converts the sampling rate of a signal associated to an input clock into a signal associated to a different output clock. The ASRC supports concurrent sample rate conversion of up to 10 channels of about -120dB THD+N. The sample rate conversion of each channel is associated to a pair of incoming and outgoing sampling rates. The ASRC supports up to three sampling rate pairs. Binary-BCH ECC Processor The BCH62 module provides up to 62-bit ECC for NAND Flash controller (GPMI2) Cryptographic Accelerator and Assurance Module CAAM is a cryptographic accelerator and assurance module. CAAM implements several encryption and hashing functions, a run-time integrity checker, and a Pseudo Random Number Generator (PRNG). CAAM also implements a Secure Memory mechanism. In this device the security memory provided is 64 KB. Cross Trigger Interface CTI sends signals across the chip indicating that debug events have occurred. It is used by features of the Coresight infrastructure. Cross Trigger Matrix Cross Trigger Matrix IP is used to route triggering events between CTIs. Debug Access Port The DAP provides real-time access for the debugger without halting the core to: · System memory and peripheral registers · All debug configuration registers The DAP also provides debugger access to JTAG scan chains. Display Controller Dual display controller DRAM Controller · Memory types: LPDDR4 (no ECC) and DDR3L (ECC option) · One channel of 32-bit memory: · LPDDR4 up to 1.2 GHz · DDR3L up to 933MHz Display/Prefetch/ Resolve The DPR prefetches data from memory and converts the data to raster format for display output. Raster source buffers can also be prefetched unconverted. The resolve process supports graphics and video formatted tile frame buffers and converts them to raster format. Embedded display memory is used as temporary storage for data which is sourced by the display controller to drive the display. i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 8 NXP Semiconductors Block Mnemonic eDMA ENET ESAI FTM FlexCAN Table 5. i.MX 8QuadXPlus/8DualXPlus modules list (continued) Modules List Block Name Brief Description Enhanced Direct Memory Access · 4× eDMA with a total of 96 channels (note: all channels are not assigned; see the product reference manual for more information): · 2× instances with 32 channels each · 2× instances with 16 channels each · Programmable source, destination addresses, transfer size, plus support for enhanced addressing modes · Internal data buffer, used as temporary storage to support 64-byte burst transfers, one outstanding transaction per DMA controller. · Transfer control descriptor organized to support two-deep, nested transfer operations · Channel service request via one of three methods: · Explicit software initiation · Initiation via a channel-to-channel linking mechanism for continuous transfers · Peripheral-paced hardware requests (one per channel) · Support for fixed-priority and round-robin channel arbitration · Channel completion reported via interrupt requests · Support for scatter/gather DMA processing · Support for complex data structures via transfer descriptors · Support to cancel transfers via software or hardware · Each eDMA instance can be uniquely assigned to a different resource domain, security (TZ) state, and virtual machine · In scatter-gather mode, each transfer descriptor's buffers can be assigned to different SMMU translation Ethernet Controller 2× 1 Gbps Ethernet + AVB (Audio Video Bridging, IEEE 802.1Qav) Enhanced Serial Audio Interface The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port for serial communication with a variety of serial devices, including industry-standard codecs, SPDIF transceivers, and other processors. The ESAI consists of independent transmitter and receiver sections, each section with its own clock generator. All serial transfers are synchronized to a clock. Additional synchronization signals are used to delineate the word frames. The normal mode of operation is used to transfer data at a periodic rate, one word per period. The network mode is also intended for periodic transfers; however, it supports up to 32 words (time slots) per period. This mode can be used to build time division multiplexed (TDM) networks. In contrast, the on-demand mode is intended for non-periodic transfers of data and to transfer data serially at high speed when the data becomes available. The ESAI has 12 pins for data and clocking connection to external devices. FlexTimer Provides input signal capture and PWM support Flexible Controller Area Communication controller implementing the CAN with Flexible Data rate (CAN FD) Network protocol and the CAN protocol according to the CAN 2.0B protocol specification. i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 9 Modules List Block Mnemonic FlexSpi (Quad SPI/Octal SPI) GIC GPIO GPMI GPT GPU HiFi 4 DSP I2C IEE Table 5. i.MX 8QuadXPlus/8DualXPlus modules list (continued) Block Name Brief Description Flexible Serial Peripheral Interface · Flexible sequence engine to support various flash vendor devices, including HyperBusTM devices: · Support for FPGA interface · Single, dual, quad, and octal mode of operation. · DDR/DTR mode wherein the data is generated on every edge of the serial flash clock. · Support for flash data strobe signal for data sampling in DDR and SDR mode. · Two identical serial flash devices can be connected and accessed in parallel for data read operations, forming one (virtual) flash memory with doubled readout bandwidth. Generic Interrupt Controller The GIC-500 handles all interrupts from the various subsystems and is ready for virtualization. General Purpose I/O Modules Used for general purpose input/output to external devices. Each GPIO module supports 32 bits of I/O. General Purpose Media The GPMI module supports up to 8× NAND devices. 62-bit ECC (BCH) for NAND Interface Flash controller (GPMI). The GPMI supports separate DMA channels per NAND device. General Purpose Timer Each GPT is a 32-bit "free-running" or "set and forget" mode timer with programmable prescaler and compare and capture register. A timer counter value can be captured using an external event and can be configured to trigger a capture event on either the leading or trailing edges of an input pulse. When the timer is configured to operate in "set and forget" mode, it is capable of providing precise interrupts at regular intervals with minimal processor intervention. The counter has output compare logic to provide the status and interrupt at comparison. This timer can be configured to run either on an external clock or on an internal clock. Graphics Processing 1× GC7000Lite with 4x Vec4 shader cores (16 execution units) Audio Processor I2C Interface A highly optimized audio processor geared for efficient execution of audio and voice codecs and pre- and post-processing modules to offload the Arm core. I2C provides serial interface for external devices. · Supports direct encryption and decryption of FlexSPI memory type · Provides decryption services (lower performance) for DRAM traffic · Supports I/O direct encrypted storage and retrieval · Support for a number of cryptographic standards: · 128/256-bit AES Encryption (AES-CTR, AES-XTS mode options) · Multiple keys supported: · Loaded via secure key channel from security block · Key selection is per access and based on source of transaction IOMUXC JPEG/dec JPEG/enc IOMUX Control MJPEG engine for decode MJPEG engine for encode This module enables flexible I/O multiplexing. Each I/O pad has default and several alternate functions. The alternate functions are software configurable. Provides up to 4-stream decoding in parallel. Provides up to 4-stream encoding in parallel. i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 10 NXP Semiconductors Modules List Table 5. i.MX 8QuadXPlus/8DualXPlus modules list (continued) Block Mnemonic KPP LPIT-1 LPIT-2 LPSPI 03 M4F MIPI CSI-2 MIPI-DSI/LVDS MQS OCOTP_CTRL Block Name Brief Description Key Pad Port The Keypad Port (KPP) is a 16-bit peripheral that can be used as a 4 x 4 keypad matrix interface or as general purpose input/output (I/O). Low-Power Periodic Interrupt Timer Each LPIT is a 32-bit "set and forget" timer that starts counting after the LPIT is enabled by software. It is capable of providing precise interrupts at regular intervals with minimal processor intervention. It has a 12-bit prescaler for division of input clock frequency to get the required time setting for the interrupts to occur, and counter value can be programmed on the fly. Configurable SPI Full-duplex enhanced Synchronous Serial Interface. It is configurable to support Master/Slave modes, four chip selects to support multiple peripherals. Arm (CPU3) · Cortex-M4F core · AHB LMEM (Local Memory Controller) including controllers for TCM and cache memories · 256 KB tightly coupled memory(TCM) (128 KB TCMU, 128 KB TCML) · 16 KB Code Bus Cache · 16 KB System Bus Cache · ECC for TCM memories and parity for code and system caches · Integrated Nested Vector Interrupt Controller (NVIC) · Wakeup Interrupt Controller (WIC) · FPU (Floating Point Unit) · Core MPU (Memory Protection Unit) · Support for exclusive access on the system bus · MMCAU (Crypto Acceleration Unit) · MCM (Miscellaneous Control Module) MIPI CSI-2 Interface The MIPI CSI-2 IP provides MIPI CSI-2 standard camera interface ports. The MIPI CSI-2 interface supports up to 1.5 Gbps for up to 4 data lanes MIPI DSI/LVDS Combo interface The MIPI DSI IP provides DSI standard display serial interface with 4 data lines. The DSI interface supports 80 Mbps to 1.05 Gbps speed per data lane. The LVDS is a high-performance 2-channel serializer that interfaces with LVDS displays. Note: This is a combination PHY interface. It includes the digital logic and physical interface pins for both MIPI DSI (4 data lanes) and LVDS (4 differential pairs plus one for clock). The interface can be pinned out either as MIPI DSI or as LVDS. However, it does not allow for simultaneous use on one interface Medium Quality Sound Medium Quality Sound (MQS) is used to generate 2-channel medium quality PWM-like audio via two standard digital GPIO pins. OTP Controller The On-Chip OTP controller (OCOTP_CTRL) provides an interface for reading, programming, and/or overriding identification and control information stored in on-chip fuse elements. The module supports electrically-programmable poly fuses (eFUSEs). The OCOTP_CTRL also provides a set of volatile software-accessible signals that can be used for software control of hardware elements, not requiring non-volatility. The OCOTP_CTRL provides the primary user-visible mechanism for interfacing with on-chip fuse elements. Among the uses for the fuses are unique chip identifiers, mask revision numbers, cryptographic keys, JTAG secure mode, boot characteristics, and various control signals requiring permanent nonvolatility. i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 11 Modules List Block Mnemonic OCRAM Parallel CSI PCIe PRG PWM RAM 64 KB Secure RAM RAM 256 KB RNG SAI SECO SJC Table 5. i.MX 8QuadXPlus/8DualXPlus modules list (continued) Block Name Brief Description On-Chip Memory Controller The On-Chip Memory controller (OCRAM) module is designed as an interface between the system's AXI bus and the internal (on-chip) SRAM memory module. The OCRAM is used for controlling the 256 KB multimedia RAM through a 64-bit AXI bus. Parallel CSI interface The Parallel Port Capture Subsystem interfaces to Parallel CSI sensors and includes the following features: · Configurable interface logic to support the most commonly used parallel CMOS sensors · Configurable master clock output to drive external sensor (24 MHz nominal) · Up to 150 MHz input clock from sensor · Input data formats supported: · 8-bit/10-bit BT.656 · 8-bit/24-bit data port for RGB, YCbCr, and YUV data input · 8-bit/12-bit/10-bit/16-bit data port for Bayer data input Note: For some formats a single pixel is sent per clock, for others two or three are sent per clock. PCI Express 3.0 The PCIe IP provides PCI Express Gen 3.0 functionality . Prefetch/Resolve Gasket The PRG is a gasket which translates system memory accesses to local display RTRAM accesses for display refresh. It works with the DPR to complete the prefetch and resolving operations needed to drive the display. Pulse Width Modulation The pulse-width modulator (PWM) has a 16-bit counter and is optimized to generate sound from stored sample audio images and it can also generate tones. It uses 16-bit resolution and a 4×16 data FIFO to generate square waveforms. Secure/non-secure RAM Secure/non-secure Internal RAM, interfaced through the CAAM. Internal RAM Internal RAM, which is accessed through OCRAM memory controllers. Random Number Generator The purpose of the RNG is to generate cryptographically strong random data. It uses a true random number generator (TRNG) and a pseudo-random number generator (PRNG) to achieve true randomness and cryptographic strength. The RNG generates random numbers for secret keys, per message secrets, random challenges, and other similar quantities used in cryptographic algorithms. I2S/SSI/AC97 Interface The SAI module provides a synchronous audio interface that supports full duplex serial interfaces with frame synchronization, such as I2S, AC97, TDM, and codec/DSP interfaces. Security Controller Core and associated memory and hardware responsible for key management. Secure JTAG Controller The SJC provides the JTAG interface, which is compatible with JTAG TAP standards, to internal logic. This device uses JTAG port for production, testing, and system debugging. Additionally, the SJC provides BSR (Boundary Scan Register) standard support, which is compatible with IEEE1149.1 and IEEE1149.6 standards. The JTAG port must be accessible during platform initial laboratory bring-up, for manufacturing tests and troubleshooting, as well as for software debugging by authorized entities. The SJC incorporates three security modes for protecting against unauthorized accesses. Modes are selected through eFUSE configuration. i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 12 NXP Semiconductors Block Mnemonic SNVS SPDIF TEMPMON UART USB3/USB2 Table 5. i.MX 8QuadXPlus/8DualXPlus modules list (continued) Modules List Block Name Secure Non-Volatile Storage Sony Philips Digital Interconnect Format Temperature Monitor UART Interface Brief Description Secure Non-Volatile Storage, including Secure Real Time Clock, Security State Machine, Master Key Control, and Violation/Tamper Detection and reporting. The Sony/Philips Digital Interface (SPDIF) audio block is a stereo transceiver that allows the processor to receive and transmit digital audio. The SPDIF transceiver allows the handling of both SPDIF channel status (CS) and User (U) data and includes a frequency measurement block that allows the precise measurement of an incoming sampling frequency. The temperature monitor/sensor IP module for detecting high temperature conditions. The temperature read out does not reflect case or ambient temperature. It reflects the temperature in proximity of the sensor location on the die. Temperature distribution may not be uniformly distributed; therefore, the read-out value may not be the reflection of the temperature value for the entire die. · High-speed TIA/EIA-232-F compatible, up to 5.0 Mbps · Serial IR interface low-speed, IrDA-compatible (up to 115.2 Kbit/s) · 9-bit or Multidrop mode (RS-485) support (automatic slave address detection) · 7, 8, 9, or 10-bit data characters (7-bits only with parity) · 1 or 2 stop bits · Programmable parity (even, odd, and no parity) · Hardware flow control support for request to send (RTS_B) and clear to send (CTS_B) signals The USB3/USB2 OTG module has been specified to perform USB 3.0 dual role and USB 2.0 On-The-Go (OTG) compatible with the USB 3.0, and USB 2.0 specification with OTG supplementary specifications. This controller supports twoindependent USB cores (1× USB3.0 dual-role, 1× USB2.0 OTG) and includes the PHY and I/O interfaces to support this operation. The full pinout of the USB 3.0 controller includes the signaling for both USB 3.0 and USB 2.0. This does not mean there is a separate USB 2.0 controller that can be used independently and simultaneously with USB 3.0. This device has an additional separate, independent USB 2.0 OTG controller which can be used simultaneously with this USB 3.0. Specific features requested for this updated module: · Super Speed (5 Gbps), High Speed (480 Mbps), full speed (12 Mbps) and low speed (1.5 Mbps) · Fully compatible with the USB 3.0 specification (backward compatible with USB 2.0) · Fully compatible with the USB On-The-Go supplement to the USB 2.0 specification · Hardware support for OTG signaling · Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) implemented in hardware, which can also be controlled by software i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 13 Modules List Table 5. i.MX 8QuadXPlus/8DualXPlus modules list (continued) Block Mnemonic USBOH uSDHC VPU WDOG XTAL OSC24M XTAL OSC32K Block Name Brief Description The USBOH module has been specified which performs USB 2.0 On-The-Go (OTG) and USB 2.0 Host functionality compatible with the USB 2.0 with OTG supplement specification. This controller supports one independent USB core (1× USB2.0 OTG) and includes the PHY and I/O interfaces to support this operation. Key features: · One USB2.0 OTG controller · High Speed (480 Mbps), full speed (12 Mbps) and low speed (1.5 Mbps) · Fully compatible with the USB 2.0 specification · Fully compatible with the USB On-The-Go supplement to the USB 2.0 specification · Hardware support for OTG signaling Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) implemented in hardware, which can also be controlled by software SD/eMMC and SDXC Enhanced Multi-Media Card / Secure Digital Host Controller The uSDHC is a host controller used to communicate with external low cost data storage and communication media. It supports the previous versions of the MultiMediaCard (MMC) and Secure Digital Card (SD) standards. Specifically, the uSDHC supports: · SD Host Controller Standard Specification v3.0 with the exception that all the registers do not match the standards address mapping. · SD Physical Layer Specification v3.0 UHS-I (SDR104/DDR50) · SDIO specification v3.0 · eMMC System Specification v5.1 Video Processing Unit See the device reference manual for the complete list of the VPU's decoding/encoding capabilities. Watchdog The Watchdog Timer supports two comparison points during each counting period. Each of the comparison points is configurable to evoke an interrupt to the Arm core, and a second point evokes an external event on the WDOG line. The 24 MHz clock source is an external crystal that acts as one of two main clock sources to the chip. The OSC24M is used as the source clock for subsystem PLLs. OSC24M can be turned off by the System Control Unit (SCU) during sleep mode. The 32 KHz clock source is an external crystal that is one of two main clock sources to the chip. The OSC32K is intended to be always on and is distributed by the SCU to modules in the chip. 3.1 Special Signal Considerations The package contact assignments can be found in Section 6, "Package information and contact assignments"." Signal descriptions are defined in the device reference manual. 3.2 Recommended Connections for Unused Interfaces The recommended connections for unused analog interfaces can be found in the section, "Unused Input/Output Terminations," in the hardware development guide for this device. i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 14 NXP Semiconductors Electrical characteristics 4 Electrical characteristics This section provides the device and module-level electrical characteristics for these processors. 4.1 Chip-level conditions This section provides the device-level electrical characteristics for the SoC. See the following table for a quick reference to the individual tables and sections. Table 6. Chip-level conditions For these characteristics, ... Absolute maximum ratings FCPBGA package thermal resistance data Operating ranges External Input Clock Frequency Maximum supply currents USB 2.0 PHY typical current consumption in Power-Down Mode USB 3.0 PHY typical current consumption in Power-Down Mode Typical current consumption in Power-Down mode for USB 2.0 PHY embedded in USB 3.0 PHY Topic appears ... on page 15 on page 17 on page 18 on page 20 on page 21 on page 24 on page 24 on page 24 4.1.1 Absolute Maximum Ratings CAUTION Stresses beyond those listed under Table 7 may affect reliability or cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated in the "Operating ranges" or other parameter tables is not implied. Exposure to absolute-maximum-rated conditions for extended periods will affect device reliability. Parameter Description Core Supplies Input Voltage DDR PHY supplies Table 7. Absolute maximum ratings Symbol Min VDD_A35 -0.3 VDD_GPU VDD_MAIN VDD_DDR_VDDQ -0.3 Max Units 1.2 V 1.75 V i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 15 Electrical characteristics Table 7. Absolute maximum ratings (continued) Parameter Description 1.0V IO supplies IO Supply for GPIO Type 1.8V IO Single supply IO Supply for GPIO Type 1.8 / 2.5 / 3.3V IO Tri-voltage Supply IO Supply for GPIO Type 1.8 / 3.3V IO Dual Voltage Supply SNVS Coin Cell USB VBUS (OTG2) USB VBUS (OTG1) Symbol Min VDD_MIPI_1P0 -0.3 VDD_USB_OTG_1P0 VDD_ADC_1P8 -0.5 VDD_ADC_DIG_1P8 VDD_ANA0_1P8 (IO, analog,OSC SCU) VDD_ANA1_1P8 (IO, analog,OSC SCU) VDD_DDR_PLL_1P8 (memory PLLs) VDD_MIPI_1P8 (PHY, GPIO) VDD_MIPI_CSI_DIG_1P8 (PHY, GPIO) VDD_PCIE_1P8 (PHY) VDD_USB_1P8 (PHY, GPIO) VDD_ENET0_VSELECT_1P8_2P5_3P3 -0.3 VDD_ENET0_1P8_2P5_3P3 VDD_ESAI_SPDIF_1P8_2P5_3P3 VDD_CAN_UART_1P8_3P3 -0.3 VDD_CSI_1P8_3P3 VDD_EMMC0_1P8_3P3 VDD_EMMC0_VSELECT_1P8_3P3 VDD_ENET_MDIO_1P8_3P3 VDD_MIPI_DSI_DIG_1P8_3P3 VDD_PCIE_DIG_1P8_3P3 VDD_QSPI0A_1P8_3P3 VDD_QSPI0B_1P8_3P3 VDD_SPI_MCLK_UART_1P8_3P3 VDD_SPI_SAI_1P8_3P3 VDD_TMPR_CSI_1P8_3P3 VDD_USB_3P3 (PHY & GPIO) VDD_USDHC1_1P8_3P3 VDD_USDHC1_VSELECT_1P8_3P3 VDD_SNVS_4P2 -0.3 USB_OTG2_VBUS -0.3 USB_OTG1_VBUS -0.3 Max Units 1.2 V 2.1 V 3.8 V 3.8 V 4.3 V 3.63 V 5.5 V i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 16 NXP Semiconductors Electrical characteristics Table 7. Absolute maximum ratings (continued) Parameter Description Symbol Min Max Units I/O Voltage for USB Drivers USB_OTG1_DP/USB_OTG1_DN -0.3 3.63 V USB_OTG2_DP/USB_OTG2_DN I/O Voltage for ADC ADC_INx Vin/Vout input/output voltage range (GPIO Vin/Vout Type Pins) Vin/Vout input/output voltage range (DDR Vin/Vout pins) -0.1 2.1 V -0.3 OVDD+0.31 V -0.3 OVDD+0.41,2 V ESD immunity (HBM). Vesd_HBMX -- 1000 V ESD immunity (CDM). Vesd_CDM -- 250 V Storage temperature range Tstorage -55 150 °C 1 OVDD is the I/O supply voltage. 2 The absolute maximum voltage includes an allowance for 400 mV of overshoot on the I/O pins. Per JEDEC standard the allowed signal overshoot must be derated if NVCC_DRAM exceeds 1.575 V. 4.1.2 Thermal resistance 4.1.2.1 FCPBGA package thermal resistance This table provides the FCPBGA package thermal resistance data. Table 8. FCPBGA package thermal resistance data Rating Board Type1 Symbol Value, 21x21 mm Unit package Junction to Ambient Thermal Resistance2 JESD51-9, 2s2p RJA 15.2 °C/W Junction to Package Top Thermal Resistance2 JESD51-9, 2s2p JT 0.1 °C/W Junction to Case Thermal Resistance3 JESD51-9, 1s RJC 0.7 °C/W 1 Thermal test board meets JEDEC specification for this package (JESD51-9). 2 Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report is solely for a thermal performance comparison of one package to another in a standardized specified environment. It is not meant to predict the performance of a package in an application-specific environment. 3 Junction-to-Case thermal resistance determined using an isothermal cold plate. Case temperature refers to the mold surface temperature at the package top side dead center. i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 17 Electrical characteristics 4.1.3 Operating Ranges The following table provides the operating ranges of these processors. VDD_A35 Symbol VDD_GPU VDD_MAIN2 VDD_DDR_VDDQ VDD_DDR_PLL_1P8 VDD_MIPI_1P0 VDD_ANA0_1P8 VDD_ANA1_1P8 VDD_ADC_1P8 VDD_ADC_DIG_1P8 VDD_MIPI_1P8 VDD_MIPI_CSI_DIG_1P8 VDD_USB_1P8 VDD_PCIE_1P8 Table 9. Operating ranges1 Description Mode Min Typ Max Unit Comments Power supply of Overdrive 1.05 1.10 1.15 V Max frequency: 1.2 GHz Cortex-A35 cluster Nominal 0.95 1.00 1.10 V Max frequency: 900 MHz Power supply of GPU instance Overdrive 1.05 1.10 1.15 V Max frequencies: · Shaders: 850MHz · Core: 700 MHz Nominal 0.95 1.00 1.10 V Max frequencies: shaders: 372 MHz; core: 372 MHz Power supply of remaining core logic N/A 0.95 1.00 1.10 V Max freq.: HiFi4 DSP 640 MHz Max freq.: M4 264 MHz Max freq.: VPU 600 MHz Power supplies of memory IOs DDR3L 1.30 1.35 1.45 V Max frequency: 933 MHz to support DDR3L-1866 LPDDR4 1.06 1.10 1.17 V Max frequency: 1.2GHz to support LPDDR4-2400 Power supplies of memory PLLs N/A 1.65 1.80 1.95 V PLL supply can be merged with other 1.8V supplies with proper on board decoupling. Power supplies of N/A 0.95 1.00 1.10 V -- PHYs (1.0V part) Power supplies of IOs, analog and oscillator of the SCU N/A 1.65 1.80 1.95 V These balls shall be powered by a dedicated supply Power supplies of N/A 1.65 1.80 1.95 V -- PHYs (1.8V part) and GPIO operating at 1.8V only. Power supplies of PCIE PHY (1.8 V part) 1.71 1.80 1.89 V -- i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 18 NXP Semiconductors Electrical characteristics Table 9. Operating ranges1 (continued) Symbol VDD_USB_3P3 VDD_CAN_UART_1P8_3P3 VDD_CSI_1P8_3P3 VDD_EMMC0_1P8_3P3 VDD_EMMC0_VSELECT_1P8_3P3 VDD_ENET_MDIO_1P8_3P3 VDD_MIPI_DSI_DIG_1P8_3P3 VDD_PCIE_DIG_1P8_3P3 VDD_QSPI0A_1P8_3P3 VDD_QSPI0B_1P8_3P3 VDD_SPI_MCLK_UART_1P8_3P3 VDD_SPI_SAI_1P8_3P3 VDD_TMPR_CSI_1P8_3P3 VDD_USDHC1_1P8_3P3 VDD_USDHC1_VSELECT_1P8_3P3 Description Power supplies of PHYs (3.3V part) and GPIO operating at 3.3V only Power supplies of GPIO supporting both 1.8V or 3.3V Mode N/A Min Typ Max Unit 3.00 3.30 3.60 V Comments -- 1.8V 1.65 1.80 1.95 V When VDD_USDHC1_1P8_3P 3 is used to support an SD card, then it shall be on a dedicated 1.8V/3.3V regulator. When VDD_SIM0_1P8_3P3 is used to support a SIM card, it shall be on a dedicated 1.8V/3.3V regulator. When VDD_TMPR_CSI_1P8_ 3P3 is used as a GPIO it can be connected to the 1.8/3.3V supply. VDDs of this list targeting 1.8V can share 1.8V regulator of 1.8V only VDDs VDD_ENET0_1P8_2P5_3P3 Power supplies of VDD_ENET0_VSELECT_1P8_2P5_3P3 ethernet IOs VDD_ESAI_SPDIF_1P8_2P5_3P3 VDD_SNVS_4P2 Power supply of SNVS 3.3V 1.8V 2.5V 3.3V N/A VDDs of this list targeting 3.3V can share 3.3V regulator of 3.3V only VDDs 3.00 3.30 3.60 V -- 1.65 1.80 1.95 V -- 2.40 2.50 2.60 V -- 3.00 3.30 3.60 V -- 2.80 3.30 4.20 V It can be supplied by a backup battery: a coin cell or a super cap. Output of embedded LDOs VDD_PCIE_LDO_1P0_CAP 1.0V output of N/A -- 1.00 -- V -- VDD_USB_SS3_LDO_1P0_CAP embedded LDOs VDD_SNVS_LDO_1P8_CAP 1.8V output of N/A -- 1.80 -- V -- SNVS embedded LDO i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 19 Electrical characteristics Table 9. Operating ranges1 (continued) Symbol Description Mode Min Typ Max Unit Comments Power supplies that shall be connected to output of an embedded LDO VDD_TMPR_CSI_1P8_3P3 VDD_USB_OTG_1P0 -- N/A -- 1.80 -- V Shall be connected to VDD_SNVS_LDO_1P8_ CAP when used as a tamper pin. In CSI mode use an external 1.8 V supply. In this case, follow the 1.8 V I/O specification above. -- N/A -- 1.00 -- V Shall be externally connected to VDD_USB_SS3_LDO_1 P0_CAP Junction temperature Junction temperature -- -- -40 -- 105 °C -- 1 Voltage ranges are defined to group as many supplies as possible. Some supplies may have a wider range than listed here. 2 During low power state (see Section 4.1.6, "Low power mode supply currents"), this voltage can be dropped to 0.8 V +/- 3% for retention. 4.1.4 External clock sources Each processor has two external input system clocks: a low frequency (RTC_XTALI) and a high frequency (XTALI). The RTC_XTALI is used for real time functions. It supplies the clock for real time clock operation and for slow-system and watchdog counters. The clock input can be connected to either an external oscillator or a crystal using the internal oscillator amplifier. The system clock input XTALI is used to generate the main system clock. It supplies the PLLs and other peripherals. The system clock input requires a crystal using the internal oscillator amplifier. The PCIe oscillator can be sourced internally or input to the chip. In both cases, it is a 100 MHz nominal clock using HCSL signaling to provide the PCIe reference clock. The following table shows the interface frequency requirements. Parameter Description RTC_XTALI Oscillator1,2 XTALI Oscillator4,2 PCIe oscillator5 Frequency accuracy Table 10. External Input Clock Frequency Symbol Min fckil -- fxtal -- f100M -- -- -- Typ 32.7683/32.0 24 100 -- Max -- -- -- ±300 Unit kHz MHz MHz ppm i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 20 NXP Semiconductors Electrical characteristics 1 External oscillator or a crystal with internal oscillator amplifier. 2 The required frequency stability of this clock source is application dependent. For recommendations, see the hardware development guide for this device. 3 Recommended nominal frequency 32.768 kHz. 4 Fundamental frequency crystal with internal oscillator amplifier. 5 If using an external clock instead of the internal clock source, an HCSL-compatible clock is required. The typical values shown in Table 10 are required for use with NXP board support packages (BSPs) to ensure precise time keeping and USB operations. 4.1.5 Maximum Supply Currents NOTE Some of the numbers shown in this table are based on the companion regulator limits and not actual use cases. Work is in progress to provide use casebased numbers in future data sheet releases. Table 11. Maximum supply currents Symbol Value Unit Comments VDD_A351 VDD_GPU1 2500 mA 2500 mA VDD_MAIN 5000 mA VDD_DDR_VDDQ 1200 mA Does not comprehend IO of memory VDD_DDR_PLL_1P8 20 mA VDD_ANA0_1P8 200 mA VDD_ANA1_1P8 200 mA VDD_MIPI_1P0 100 mA VDD_MIPI_1P8 115 mA VDD_ADC_DIG_1P8 18 mA VDD_CAN_UART_1P8_3P3 30 mA VDD_CSI_1P8_3P3 12 mA VDD_EMMC0_1P8_3P3 30 mA VDD_EMMC0_VSELECT_1P8_3P3 30 mA VDD_ENET_MDIO_1P8_3P3 15 mA VDD_ENET0_1P8_2P5_3P3 30 mA VDD_ENET0_VSELECT_1P8_2P5_3 30 mA P3 VDD_ESAI_SPDIF_1P8_2P5_3P3 39 mA VDD_MIPI_CSI_DIG_1P8 15 mA i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 21 Electrical characteristics Table 11. Maximum supply currents (continued) Symbol Value Unit Comments VDD_MIPI_DSI_DIG_1P8_3P3 24 mA VDD_PCIE_DIG_1P8_3P3 9 mA VDD_QSPI0A_1P8_3P3 40 mA VDD_QSPI0B_1P8_3P3 40 mA VDD_SPI_MCLK_UART_1P8_3P3 36 mA VDD_SPI_SAI_1P8_3P3 48 mA VDD_TMPR_CSI_1P8_3P3 30 mA VDD_USDHC1_1P8_3P3 30 mA VDD_USDHC1_VSELECT_1P8_3P3 20 mA VDD_ADC_1P8 5 mA VDD_USB_OTG_1P0 36 mA Shall be externally connected to VDD_USB_SS3_LDO_1P0_CAP VDD_USB_1P8 175 mA VDD_USB_3P3 40 mA VDD_PCIE_1P8 255 mA VDD_SNVS_4P22 5 mA Start-up current 1 VDD_A35 and VDD_GPU can be combined with one power supply. 2 Under normal operating conditions, the maximum current on VDD_SNVS_4P2 is shown Table 11. During initial power on, VDD_SNVS_4P2 can draw up to 5 mA if the supply is capable of sourcing that current. If less than 5 mA is available, the VDD_SNVS_LDO_1P8_CAP charge time will increase. i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 22 NXP Semiconductors Electrical characteristics 4.1.6 Low power mode supply currents The following table shows the current core consumption (not including I/O) in selected low power modes. Table 12. i.MX 8QuadXPlus/8DualXPlus Key State (KSx) power consumption Mode Test conditions Supply Max Unit KS0 SNVS only, all other supplies OFF. RTC running, tamper not active, external 32K crystal. VDD_SNVS_4P2 (4.2 V) 50 A KS11 RAM and IO state retained. DRAM in self-refresh, associated I/O's OFF. 32K running, 24M, PLLs and ring oscillators OFF. PHYs are in idle state. A35 and GPU supplies OFF. MAIN2 dropped to 0.8 V. VDD_ANAx_1P8 (1.8 V) 0.9 mA VDD_A35 (OFF) -- mA VDD_GPU (OFF) -- mA VDD_MAIN (0.8 V) 33 mA VDD_DDR_VDDQ (1.1 V) 0.5 mA Total 28.6 mW KS43 Leakage test, not intended as a customer use case. Overdrive conditions set, memories active, all sub-systems powered ON. Active power minimized. VDD_ANAx_1P8 (1.8 V) VDD_A35 (1.1 V) VDD_GPU (1.1 V) VDD_MAIN (1.0 V) Total 3.5 mA 600 mA 250 mA 1100 mA 2541 mW 1 Maximum values are for 25 °C Tambient . 2 0.8 V nominal--voltage specification under this case is ± 3%. 3 Maximum values are for 105 °C Tjunction . i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 23 Electrical characteristics 4.1.7 USB 2.0 PHY typical current consumption in Power-Down mode In power down mode, everything is powered down, including the VBUS valid detectors, typical condition. The following table shows the USB interface typical current consumption in Power-Down mode. Table 13. USB 2.0 PHY typical current consumption in Power-Down Mode Current VDD_USB_3P3 (3.3 V) 1 A VDD_USB_1P8 (1.8 V) 0.06 A VDD_USB_OTG_1P0 (1.0 V) 0.5 A 4.1.8 USB 3.0 PHY typical current consumption in Power-Down mode In power down mode, everything is powered down, including the VBUS valid detectors, typical condition. The following table shows the USB interface typical current consumption in Power-Down mode. Table 14. USB 3.0 PHY typical current consumption in Power-Down Mode Current -- VDD_USB_1P8 (1.8 V) VDD_USB_OTG_1P0 (1.0 V) -- 10 A 70 A The following table shows the current consumption for the USB 2.0 PHY embedded in the USB 3.0 PHY. Table 15. Typical current consumption in Power-Down mode for USB 2.0 PHY embedded in USB 3.0 PHY Current--Host mode Current--Device mode VDD_USB_3P3 (3.3 V) 22.6 A 12.6 VDD_USB_1P8 (1.8 V) 12.7 85.7 VDD_USB_OTG2_1P0VDD_U SB_OTG_1P0 (1.0 V) 81.5 78.5 4.1.8.1 USB 3.0 Type-C connector considerations The device supports USB 3.0 Type-C connection when used in conjunction with the following devices: · PTN36043 · PTN5150A · NX5P3090UK NXP supports many other configurations and implementations for USB 3.0 Type-C connections. See NXP USB Type-C: True Plug'n Play . i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 24 NXP Semiconductors Electrical characteristics 4.2 Power supplies requirements and restrictions The system design must comply with power-up sequence, power-down sequence, and steady state guidelines as described in this section to ensure the reliable operation of the device. Any deviation from these sequences may result in the following situations: · Excessive current during power-up phase · Prevention of the device from booting · Irreversible damage to the processor 4.2.1 Power-up sequence The device has the following power-up sequence requirements: · Supply group 0 (SNVS) must be powered first. It is expected that group 0 will typically remain always on after the first power-on. · Supply group 1 (MAIN and SCU) and group 0 must both be powered to their nominal values prior to boot. They must power up after or simultaneously with group 0. · Supply group 2 (I/O's and DDR interface) consists of those modules required to start the boot process by accessing external storage devices. These must be fully powered prior to POR release if booting from one of these supplies interfaces. They must power up after or simultaneously with group 1. · Supply group 3 consists of the remaining portions of the SoC. This includes nonboot I/O voltages and supplies for the major computational units. These can be sequenced in any order and as required to perform the desired functions for the intended application. They must power up after or simultaneously with group 2. NOTE The definition of "power-up" refers to a stable voltage operating within the range defined in Table 9. This should be taken into consideration, along with the different capacitive loading on each rail, if considering simultaneous switch-on of the different supply groups. 4.2.2 Power-down sequence The device processor has the following power-down sequence requirements: · Supply group 0 must be turned off last, after all other supplies. · Supply group 1 can be turned off just prior to group 0. All remaining supplies can be turned off prior to group 1. i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 25 Electrical characteristics NOTE When switching off supply group 0 (SNVS), VDD_SNVS_4P2 must be discharged below 2.4 V before starting the next power-up sequence to ensure correct operation. This will generate a full SNVS reset, allowing correct operation on the next power-up sequence. This would also be a requirement to clear any security related flag as a result of an SNVS voltage drop, when tamper features are enabled. i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 26 NXP Semiconductors NXP Semiconductors 4.2.3 Power Supplies Usage The following table shows the power supplies usage by group. i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 Table 16. Power supplies usage Supply Groups Voltage Group 0 2.4 - 4.2v VDD_SNVS_4P2 1.8v internal LDO VDD_TMPR_CSI_1P8_3P31 Group 1 1.0v VDD_MAIN VDD_MIPI_1P0 1.8v VDD_ANAx_1P8 1.1 - 1.35v 1.8v 1.8v or 3.3v 1.8v or 3.3v switchable 3.3v VDD_DDR_VDDQ Group 2 VDD_ADC_DIG_1P8 VDD_ADC_1P8 VDD_DDR_PLL_1P8 VDD_MIPI_1P8 VDD_MIPI_CSI_DIG_1P8 VDD_PCIE_1P8 VDD_USB_1P8 VDD_CAN_UART_1P8_3P3 VDD_CSI_1P8_3P3 VDD_EMMC0_VSELECT_1P8_3P3 VDD_ENET_MDIO_1P8_3P3 VDD_MIPI_DSI_DIG_1P8_3P3 VDD_PCIE_DIG_1P8_3P3 VDD_QSPI0x_1P8_3P3 VDD_SPI_MCLK_UART_1P8_3P3 VDD_SPI_SAI_1P8_3P3 VDD_TMPR_CSI_1P8_3P31 VDD_USDHC1_VSELECT_1P8_3P3 VDD_EMMC0_1P8_3P3 VDD_USB_3P3 VDD_USDHC1_1P8_3P3 1.1 - 1.1v 1.0v internal LDO's 1.8v or 2.5v or 3.3v Group 3 VDD_A352 VDD_GPU2 VDD_USB_OTG_1P0 VDD_ENET0_1P8_2P5_3P3 VDD_ENET0_VSELECT_1P8_2P5_3P3 VDD_ESAI_SPDIF_1P8_2P5_3P3 1 Supply connection and Supply Group vary depending on use case. For use as tamper pin, it must be tied to the VDD_SNVS_LDO_1P8_CAP. If used as a CSI/SAI, it is tied to I/O supply. 2 VDD_A35 and VDD_GPU can be combined with one power supply. Electrical characteristics 27 Electrical characteristics 4.3 PLL electrical characteristics 4.3.1 PLLs of subsystems i.MX 8QuadXPlus/8DualXPlus embeds a large number of PLLs to address clocking requirements of the various subsystems. These PLLs are controlled through the SCU and not directly by Cortex-A or Cortex-M4F processors. A software API shall be used by those processors to access the PLL settings. Additional PLLs are specific to high-performance interfaces. These are described in the following sections. This table summarizes the PLLs controlled by the SCU. Subsystem Cortex-A35 GPU DRC (DRAM Controller) Table 17. PLLs controlled by SCU PLL usage Source clock Locking range1 Min freq. Max freq. Lock freq. Subsystem 24 650 1300 · Overdrive: 1200 · Nominal: 9002 PLL #0: subsystem PLL #1: shaders Subsystem 24 648 1344 · Overdrive: 700 · Nominal: 7443 24 648 1344 · Overdrive: : 850 · Nominal: 7444 24 1250 2500 · LPDDR4: 2400 · DDR3L: 18665 Unit MHz MHz MHz DB (DRAM Block) Subsystem 24 Display Controller 0 PLL #0: subsystem 24 PLL #1: display clock #0 24 PLL #2: display clock #1 24 Imaging Subsystem 24 ADMA6 PLL #0: subsystem 24 PLL #1: audio PLL #0 24 PLL #2: audio PLL #1 24 PLL #3: Parallel LCD display 24 Connectivity PLL #0: Subsystem 24 PLL #1: PHY 24 HSIO (High-speed Subsystem 24 I/O) LSIO (Low-speed Subsystem 24 I/O) 650 1300 1200 MHz 650 1300 800 MHz 650 1300 User-configurable MHz 650 1300 User-configurable MHz 650 1300 1200 MHz 650 1300 1280 MHz 650 1300 User-configurable MHz 650 1300 User-configurable MHz 650 1300 Pixel freq. ×N MHz 650 1300 792 MHz 650 1300 1000 MHz 650 1300 800 MHz 650 1300 800 MHz i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 28 NXP Semiconductors Electrical characteristics Table 17. PLLs controlled by SCU (continued) Subsystem PLL usage Locking range1 Source clock Lock freq. Unit Min freq. Max freq. Cortex-M4 Subsystem 24 650 1300 792 MHz VPU PLL #0: subsystem 24 650 1300 1200 MHz MIPI-DSI Subsystem 24 650 1300 864 MHz MIPI-CSI Subsystem 24 650 1300 720 MHz SCU (System Controller Unit) Subsystem 24 650 1300 1056 MHz 1 Operating frequencies are limited to only those supported by the SCFW. 2 1200 MHz is used to generate the overdrive frequency point, and 900 MHz for the nominal frequency point. See Table 9 to get associated voltages. 3 700 MHz is used to generate the overdrive frequency point, and 744 is used to generate the nominal point (372 MHz). 4 850 MHz is used to generate the overdrive frequency point, and 744 is used to generate the nominal point (372 MHz) 5 2400 MHz is used to generate 1200 MHz when in LPDDR4 mode. 1866 MHz is used to generate 933 MHz when in DDR3L mode. See Table 9 to get associated voltages. 6 The audio PLLs support on-the-fly frequency changes for clock synchronization applications, 25 Hz steps, up to a maximum change of +/- 250 KHz is supported. 4.3.2 PLLs dedicated to specific interfaces The following sections cover PLLs used for specific interfaces. Clock output frequency and clock output range refer to the output of the PLL. Additional clock dividers may be on the output path to divide the output frequency down to the targeted frequency. See the related sections in the reference manual for settings of these clock dividers. 4.3.2.1 Ethernet PLL This PLL is controlled by the SCU. Reference clock Clock output frequency Parameter Table 18. Ethernet PLL Value 24 1 Unit MHz GHz 4.3.2.2 USB 3.0 PLLs USB 3.0 has two PLLs. One is embedded in Super-Speed PHY. The other one is embedded in the USB 2.0 OTG PHY that is part of the USB 3.0 interface. i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 29 Electrical characteristics The table below describes the PLL embedded in the Super-Speed PHY. Table 19. USB 2.0 PLL embedded in Super Speed PHY Reference clock Clock output frequency Parameter Value 24 5 Unit MHz GHz The table below describes the PLL embedded in the USBOTG PHY. Table 20. USB 2.0 PLL embedded in USBOTG PHY Reference clock Clock output frequency Parameter Value 24 480 Unit MHz MHz 4.3.2.3 USB 2.0 OTG PLLs This PLL is embedded in the USB 2.0 OTG PHY (the one which is not part of the USB 3.0 feature). Reference clock Clock output frequency Parameter Table 21. USB 2.0 OTG PLLs Value 24 480 Unit MHz MHz 4.3.2.4 PCIe PLLs The PCIe interface has three PLLs: · One is used to generate the single, common 100 MHz reference clock to each lane · One Transmit and one Receive PLL in one lane The table below shows the characteristics for the reference clock PLL. Parameter Reference clock Clock output frequency Table 22. PCIe reference clock PLLs Value 24 100 Unit Comments MHz -- MHz Used to generate internal 100 MHz reference clock to PCIe lanes i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 30 NXP Semiconductors Electrical characteristics The table below shows characteristics of the TX and RX PLLs used in each lane. Parameter Reference clock Clock output range Table 23. PCIe Transmit and Receive PLLs Value 100 6 ~ 10 Unit Comments MHz From differential input clock pads or from internal PLL GHz PCIe gen3: 8GHz to get 8GHz baud clock PCIe gen2: 10GHz to get 5GHz baud clock PCIe gen3: 10GHz to get 2.5GHz baud clock 4.3.2.5 MIPI-DSI/LVDS combo PLL The table below shows characteristics of the PLL embedded in the MIPI-DSI/LVDS combo PHY. Parameter Reference clock Clock output range Table 24. MIPI-DSI/LVDS combo PHY PLL Value 24 0.75 ~ 1.05 Unit Comments MHz -- GHz Dependent on targeted display configuration 4.4 On-chip oscillators 4.4.1 OSC24M This block integrates trimmable internal loading capacitors and driving circuitry. When combined with a suitable 24 MHz external quartz element, it can generate a low-jitter clock. The oscillator is powered from VDD_ANA1_1P8. The internal loading capacitors are trimmable to provide fine adjustment of the 24 MHz oscillation frequency. It is expected that customers burn appropriate trim values for the selected crystal and board parasitics. i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 31 Electrical characteristics Figure 2. Normal Crystal Oscillation mode Table 25. Crystal specifications Parameter description Min Typ Max Unit Frequency1 Cload2 -- 24 -- MHz -- 18 -- pF Maximum drive level 200 -- -- W ESR -- -- 60 1 The required frequency accuracy is set by the serial interfaces utilized for a specific application and is detailed in the respective standard documents. 2 Cload is the specification of the quartz element, not for the capacitors coupled to the quartz element. 4.4.2 OSC32K This block implements an internal amplifier, trimmable load capacitors and a bias network that when combined with a suitable quartz crystal implements a low power oscillator. Additionally, if the clock monitor determines that the 32KHz oscillation is not present, then the source of the 32 KHz clock will automatically switch to the internal relaxation oscillator of lesser frequency accuracy. i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 32 NXP Semiconductors Electrical characteristics CAUTION The internal ring oscillator is not meant to be used in customer applications, due to gross frequency variation over wafer processing, temperature, and supply voltage. These variations will cause timing issues to many different circuits that use the internal ring oscillator for reference; and, if this timing is critical, application issues will occur. To prevent application issues, it is recommended to only use an external crystal or an accurate external clock. If this recommendation is not followed, NXP cannot guarantee full compliance of any circuit using this clock. The OSC32K runs from VDD_SNVS_LDO_1P8_CAP, which is regulated from VDD_SNVS. The target battery/voltage range is 2.8 to 4.2 V for VDD_SNVS, with a regulated output of approximately 1.75 V. Table 26. OSC32K main characteristics Parameter Min Typ Max Comments Fosc -- 32.768 kHz -- This frequency is nominal and determined mainly by the crystal selected. 32.0 KHz is also supported. Current -- · xtal oscillator mode: 5 A -- These values are for typical process and room consumption · 32K internal oscillator mode: 10 A temperature. Values will be updated after silicon characterization. Bias resistor -- 200 M -- This the integrated bias resistor that sets the amplifier into a high gain state. Any leakage through the ESD network, external board leakage, or even a scope probe that is significant relative to this value will debias the amplifier. The debiasing will result in low gain, and will impact the circuit's ability to start up and maintain oscillations. Target Crystal Properties Cload -- 10 pF -- Usually crystals can be purchased tuned for different Cloads. This Cload value is typically 1/2 of the capacitances realized on the PCB on either side of the quartz. A higher Cload will decrease oscillation margin, but increases current oscillating through the crystal. ESR -- 50 k 100 k Equivalent series resistance of the crystal. Choosing a crystal with a higher value will decrease the oscillating margin. Frequency VPP RTC_XTALI Rise/fall time Table 27. External input clock for OSC32K Min Typ -- 32.768 or 32 700 -- -- -- Max -- VDD_SNVS_LDO_1P8_CAP -- Unit kHz mV ns Notes -- 1,2,3 4 i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 33 Electrical characteristics 1 The external clock is fed into the chip from the RTC_XTALI pin; the RTC_XTALO pin should be left floating. 2 The parameter specified here is a peak-to-peak value and VIH/VIL specifications do not apply. 3 The voltage applied on RTC_XTALI must be within the range of VSS to VDD_SNVS_LDO_1P8_CAP. 4 The rise/fall time of the applied clock are not strictly confined. 4.5 I/O DC Parameters This section includes the DC parameters of the following I/O types: · XTALI and RTC_XTALI (clock inputs) DC parameters · General Purpose I/O (GPIO) DC parameters NOTE The term `OVDD' in this section refers to the associated supply rail of an input or output. 1 or pdat 0 Predriver ovdd pmos (Rpu) pad Voh min Vol max nmos (Rpd) ovss Figure 3. Circuit for Parameters Voh and Vol for I/O Cells 4.5.1 XTALI and RTC_XTALI (Clock Inputs) DC Parameters For RTC_XTALI, VIH/VIL specifications do not apply. The high and low levels of the applied clock on this pin are not strictly defined, as long as the input's peak-to-peak amplitude meet the requirements and the input's voltage value does not exceed the limits. 4.5.2 General-purpose I/O (GPIO) DC parameters 4.5.2.1 Tri-voltage GPIO DC parameters The following tables show tri-voltage 1.8V, 2.5 V, and 3.3 V DC parameters, respectively, for GPIO pads. These parameters are guaranteed per the operating ranges in Table 9, unless otherwise noted. i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 34 NXP Semiconductors Electrical characteristics Table 28. Tri-voltage 1.8 V GPIO DC parameters1 Parameter Symbol Test Conditions Min Max Units High-level output voltage2,3 VOH IOH= -0.1mA DSE=1 0.8 × OVDD -- V Low-level output voltage2,3 VOL IOH= -2mA DSE=0 IOL= -0.1mA DSE=1 -- 0.125 × OVDD V High-Level input voltage2,4 VIH Low-Level input voltage VIL Pull-up resistance RPU IOL= -2mA DSE=0 -- -- VIN=0V (Pullup Resistor) PUN = "L", PDN = "H" 0.625 × OVDD OVDD V 0 0.25 × OVDD V 15 50 k Pull-down resistance RDOWN VIN=OVDD( Pulldown Resistor) 15 PUN = "H", PDN = "L" 50 k Input current (no PU/PD) IIN VI = 0, VI = OVDD -1 1 A PUN = "H", PDN = "H" 1 For tri-voltage I/O, the associated IOMUXD compensation control register PSW_OVR and COMP bits must be set correctly. For 1.8 or 3.3 V operation, the SCFW API must be used to set PSW_OVR = 0b0 and COMP=0b000. For 2.5 V operation, PSW_OVR = 0b1 and COMP = 0b010. 2 Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.3 V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods. Noncompliance to this specification may affect device reliability or cause permanent damage to the device. (OVDD is the I/O Supply) 3 DSE is the setting of the PDRV register. High Drive mode is recommended for 3v3 and 2v5 modes. Low Drive mode is recommended for 1v8 mode. 4 To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 ns. Parameter High-level output voltage2,3 Low-level output voltage2,3 High-Level input voltage2,4 Low-Level input voltage Pull-up resistance Table 29. Tri-voltage 2.5 V GPIO DC parameters1 Symbol VOH V OL V IH VIL RPU Test Conditions IOH= -2mA DSE=0 IOL= -2mA DSE=0 -- -- VIN=0V (Pullup Resistor) PUN = "L", PDN = "H" Min 0.8 × OVDD -- 0.625 × OVDD 0 10 Max -- 0.125 × OVDD OVDD 0.25 × OVDD 100 Units V V V V k i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 35 Electrical characteristics Table 29. Tri-voltage 2.5 V GPIO DC parameters1 (continued) Parameter Symbol Test Conditions Min Max Units Pull-down resistance RDOWN VIN=OVDD( Pulldown 10 Resistor) PUN = "H", PDN = "L" 100 k Input current (no PU/PD) IIN VI = 0, VI = OVDD -1 PUN = "H", PDN = "H" 1 A 1 For tri-voltage I/O, the associated IOMUXD compensation control register PSW_OVR and COMP bits must be set correctly. For 1.8 or 3.3 V operation, the SCFW API must be used to set PSW_OVR = 0b0 and COMP=0b000. For 2.5 V operation, PSW_OVR = 0b1 and COMP = 0b010. 2 Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.3 V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods. Noncompliance to this specification may affect device reliability or cause permanent damage to the device. (OVDD is the I/O supply.) 3 DSE is the setting of the PDRV register. High Drive mode is recommended for 3v3 and 2v5 modes. Low Drive mode is recommended for 1v8 mode. 4 To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 ns. Table 30. Tri-voltage 3.3 V GPIO DC parameters1 Parameter Symbol Test Conditions Min Max Units High-level output voltage2,3 V OH IOH= -0.1mA 0.8 × OVDD V 4DSE=1 Low-level output voltage2,3 VOL IOH= -2mA 4DSE=0 IO4LD=S-0E.31=m1A -- 0.125 × OVDD V High-Level input voltage2,4,3 Low-Level input voltage Pull-up resistance VIH VIL RPU IOL= -2mA 4DSE=0 -- -- VIN=0V (Pullup Resistor) PUN = "L", PDN = "H" 0.725 × OVDD OVDD V 0 0.25 × OVDD V 10 100 k Pull-down resistance RDOWN VIN=OVDD( Pulldown Resistor) 10 PUN = "H", PDN = "L" 100 k Input current (no PU/PD) IIN VI = 0, VI = OVDD -2 2 A PUN = "H", PDN = "H" 1 For tri-voltage I/O, the associated IOMUXD compensation control register PSW_OVR and COMP bits must be set correctly. For 1.8 or 3.3 V operation, the SCFW API must be used to set PSW_OVR = 0b0 and COMP=0b000. For 2.5 V operation, PSW_OVR = 0b1 and COMP = 0b010. i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 36 NXP Semiconductors Electrical characteristics 2 Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.3 V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods. Noncompliance to this specification may affect device reliability or cause permanent damage to the device. (OVDD is the I/O Supply.) 3 DSE is the setting of the PDRV register. High Drive mode recommended for 3v3 and 2v5 modes. Low Drive mode is recommended for 1v8 mode. 4 To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 ns. 4.5.2.2 Dual-voltage GPIO DC parameters The following two tables show dual-voltage 1.8 V and 3.3 V DC parameters, respectively, for GPIO pads. These parameters are guaranteed per the operating ranges in Table 9, unless otherwise noted. Table 31. Dual-voltage 1.8 V GPIO DC parameters Parameter Symbol Test Conditions Min Max Units High-level output voltage1,2 VOH Ioh= -0.1mA DSE=1 0.8 × OVDD -- V Low-level output voltage1,2 Ioh= -2mA DSE=0 VOL Iol= -0.1mA DSE=1 -- 0.125 × OVD V D High-Level input voltage1,3 Iol= -2mA DSE=0 VIH -- 0.625 × OVD OVDD V D Low-Level input voltage Pull-up resistance VIL -- RPU Vin=0 V (Pullup Resistor) PUN = "L", PDN = "H" 0 0.25 × OVDD V 15 50 k Pull-down resistance Rdown Vin=OVDD( Pulldown Resistor) 15 PUN = "H", PDN = "L" 50 k Input current (no PU/PD) IIN VI = 0, VI = OVDD PUN = "H", PDN = "H" -1 1 A 1 Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.3 V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods. Noncompliance to this specification may affect device reliability or cause permanent damage to the device. (OVDD is the IO Supply.) 2 DSE is the setting of the PDRV register. High Drive mode is recommended for SD standard (3v3 mode) and MMC standard (1v8/3v3 modes). Low Drive mode is recommended for SD standard (1v8 mode). 3 To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC level through to the target DC level, Vil or Vih. Monotonic input transition time is from 0.1 ns to 1 ns. i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 37 Electrical characteristics Table 32. Dual-voltage 3.3 V GPIO DC parameters Parameter Symbol Test Conditions Min Max Units High-level output voltage1,2 VOH Ioh= -0.1mA DSE=1 0.8 × OVDD -- V Low-level output voltage1,2 VOL Ioh= -2mA DSE=0 Iol= -0.1mA DSE=1 -- 0.125 × OVDD V High-Level input voltage1,3 VIH Low-Level input voltage VIL Pull-upresistance RPU Iol= -2mA DSE=0 -- -- Vin=0V (Pullup Resistor) PUN = "L", PDN = "H" 0.725 × OVDD OVDD V 0 0.25 × OVDD V 10 100 k Pull-down resistance Rdown Vin=OVDD( Pulldown Resistor) 10 PUN = "H", PDN = "L" 100 k Input current (no PU/PD) IIN VI = 0, VI = OVDD -2 2 A PUN = "H", PDN = "H" 1 Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.3 V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods. Noncompliance to this specification may affect device reliability or cause permanent damage to the device. (OVDD is the I/O Supply.) 2 DSE is the setting of the PDRV register. High Drive mode is recommended for SD standard (3v3 mode) and MMC standard (1v8/3v3 modes). Low Drive mode is recommended for SD standard (1v8 mode). 3 To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 ns. 4.5.2.3 Single-voltage GPIO DC parameters Table 33 and Table 34 show single-voltage 1.8 V and 3.3 V DC parameters, respectively, for GPIO pads. These parameters are guaranteed per the operating ranges in Table 9 unless otherwise noted. Parameter High-level output voltage1,2 Table 33. Single-voltage 1.8 V GPIO DC parameters Symbol VOH Test Conditions IOH= -0.1mA DSE = 000 or 001 IOH= -2mA DSE = 010 or 011 IOH= -4mA DSE = 100 to 110 Min OVDD × 0.8 Max Units -- V i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 38 NXP Semiconductors Electrical characteristics Table 33. Single-voltage 1.8 V GPIO DC parameters (continued) Parameter Symbol Test Conditions Min Max Units Low-level output voltage1,2 VOL IOL= 0.1mA DSE = 000 or 001 -- OVDD × 0.2 V IOL= 2mA DSE = 010 or 011 High-Level input voltage2,3 VIH Low-Level input voltage2,3 VIL Pull-up resistance RPU IOL= 4mA DSE = 100 to 110 -- -- Vin=0V (Pullup Resistor) PUN = "L", PDN = "H" 0.65 × OVDD OVDD V 0 0.35 × OVDD V 20 90 k Pull-down resistance Rdown Vin=OVDD( Pulldown Resistor) 20 PUN = "H", PDN = "L" 90 k Input current (no PU/PD) IIN VI = 0, VI = OVDD -5 PUN = "H", PDN = "H" 5 A Keeper Circuit Resistance R_Keeper VI =.3xOVDD, VI = .7x OVDD 20 PUN = "L", PDN = "L" 90 k 1 As programmed in the associated IOMUX (DSE field) register. 2 Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.3 V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods. Noncompliance to this specification may affect device reliability or cause permanent damage to the device. (OVDD is the IO supply.) 3 To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 ns. Parameter High-level output voltage1,2 Low-level output voltage1,2 High-Level input voltage2,3 Low-Level input voltage2,3 Pull-upresistance Table 34. Single-voltage 3.3 V GPIO DC parameters Symbol VOH VOL VIH VIL RPU Test Conditions IOH = -0.1mA DSE = 00 or 01 IOH= -2mA DSE = 10 or 11 IOL=0.1mA DSE = 00 or 01 IOL = 2mA DSE = 10 or 11 -- -- Vin=0 V (Pullup Resistor) PUN = "L", PDN = "H" Min 0.8 × OVDD -- 0.75 × OVDD 0 20 Max Units -- V 0.2 × OVDD V OVDD V 0.25 × OVDD V 90 k i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 39 Electrical characteristics Table 34. Single-voltage 3.3 V GPIO DC parameters (continued) Parameter Symbol Test Conditions Min Max Units Pull-down resistance Rdown Vin=OVDD( Pulldown Resistor) 20 PUN = "H", PDN = "L" 90 k Input current (no PU/PD) IIN VI = 0, VI = OVDD -5 PUN = "H", PDN = "H" 5 A Keeper Circuit Resistance R_Keeper VI =.3xOVDD, VI = .7x OVDD 20 PUN = "L", PDN = "L" 90 k 1 As programmed in the associated IOMUX (DSE field) register. 2 Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.3 V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods. Noncompliance to this specification may affect device reliability or cause permanent damage to the device. (OVDD is the IO supply.) 3 To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 ns. 4.5.3 DDR I/O DC parameters 4.5.3.1 LPDDR4 mode I/O DC parameters These parameters are guaranteed per the operating ranges in Table 9 unless otherwise noted. Table 35. LPDDR4 DC parameters Parameter Symbol Test Conditions Min Max Units High-level output voltage1 Low-level output voltage1 VOH Out Drive = All setting 0.9 × VDDQ -- V (40,48,60,80,120,240) unterminated outputs loaded with 1pF capacitor load VOL Out Drive = All setting -- (40,48,60,80,120,240) unterminated outputs loaded with 1pF capacitor load 0.1 × VDDQ V Input current (no ODT) IIN VI = VSSQ, VI = VDDQ -2 2 A DC High-Level input voltage VIH_DC -- VREF + 0.1 VDDQ V DC Low-Level input voltage VIL_DC -- VSSQ VREF 0.1 V 1 Maximum peak amplitude allowed for overshoot and undershoot area = 0.35 V. Maximum overshoot area above VDD/VDDQ 0.8 V-ns; maximum undershoot area below VSS/VSSQ 0.8 V-ns. i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 40 NXP Semiconductors 4.5.3.2 DDR3L mode I/O DC parameters Electrical characteristics Table 36. SSTL DDR3L DC parameters Parameter Symbol Test Conditions Min Max Units DC High-level output voltage 1 DC Low-level output voltage1 VOH Out Drive = All setting (40,60,120) unterminated outputs loaded with 1pF capacitor load VOL Out Drive = All setting (40,60,120) unterminated outputs loaded with 1pF capacitor load 0.8 × VDDQ -- V -- 0.2 × VDDQ V Input termination resistance (ODT) to VDDQ/2 RTT 40 setting 36 44 60 setting 54 66 120 setting 100 140 Input current (no ODT) IIN VI = VSSQ, VI = VDDQ -2 2 A DC High-Level input voltage VIH_DC VREF + 0.09 VDDQ V DC Low-Level input voltage VIL_DC VSSQ VREF 0.09 V 1 Maximum peak amplitude allowed for overshoot and undershoot area = 0.35 V. Maximum overshoot area above VDD/VDDQ 0.8 V-ns; maximum undershoot area below VSS/VSSQ 0.8 V-ns. 4.6 I/O AC Parameters The GPIO and DDR I/O load circuit and output transition time waveforms are shown in Figure 4 and Figure 5. From Output Under Test Test Point CL CL includes package, probe and fixture capacitance Figure 4. Load Circuit for Output Output (at pad) 80% 20% tr tf Figure 5. Output Transition Time Waveform OVDD 80% 20%0 V i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 41 Electrical characteristics 4.6.1 General Purpose I/O (GPIO) AC Parameters Table 37. General Purpose I/O AC Parameters1 Symbol Parameter Test Condition Min Typ Max Unit 1.8 V application2 fmax Maximum frequency tr Rise time tf Fall time Load = 21 pF (PDRV = H, high -- -- drive, Type A, 33 Load = 15 pF (PDRV = L, low drive, Type B, 50 Measured between VOL and 0.4 -- VOH Measured between VOH and 0.4 -- VOL Driver 3.3 V application3 208 1.32 1.32 MHz ns ns fmax Maximum frequency Load = 30 pF -- -- 52 MHz tr Rise time Measured between -- -- 3 ns VOL and VOH tf Fall time Measured between -- -- 3 ns VOH and VOL 1 All output I/O specifications are guaranteed for Accurate mode of the compensation cell operation. This is applicable for both DC and AC specifications. 2 All timing specifications in 1.8 V application are valid for High Drive mode (PDRV = H). In Low Drive mode (PDRV = L), the driver is functional. 3 All timing specifications in 3.3 V application are valid for Type B driver only. In Type A, the driver is functional. Table 38. Dynamic input characteristics Symbol Parameter Condition1,2 Min Max Unit Dynamic Input Characteristics for 3.3 V Application fop Input frequency of operation INPSL Slope of input signal at I/O IOMAX High level input voltage IOMIN Low level input voltage -- Measured between 10% to 90% of the I/O swing -- -- Dynamic Input Characteristics for 1.8 V Application fop Input frequency of operation INPSL Slope of input signal at I/O IOMAX High level input voltage IOMIN Low level input voltage -- Measured between 10% to 90% of the I/O swing -- -- -- -- -- -0.3 V -- -- -- -0.3 V 52 MHz 3.5 ns 3.3 V + 0.3 V V -- 208 MHz 1.5 ns 1.8 V + 0.3 V V -- i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 42 NXP Semiconductors Electrical characteristics 1 For all supply ranges of operation. 2 The dynamic input characteristic specifications are applicable for the digital bidirectional cells. 4.7 Output Buffer Impedance Parameters This section defines the I/O impedance parameters for the following I/O types: · General Purpose I/O (GPIO) output buffer impedance · Double Data Rate I/O (DDR) output buffer impedance for LPDDR4 and DDR3L modes NOTE GPIO and DDR I/O output driver impedance is measured with "long" transmission line of impedance Ztl attached to I/O pad and incident wave launched into transmission line. Rpu/Rpd and Ztl form a voltage divider that defines specific voltage of incident wave relative to OVDD. Output driver impedance is calculated from this voltage divider (see Figure 6). i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 43 Electrical characteristics ipp_do predriver U,(V) VDD OVDD PMOS (Rpu) pad Ztl , L = 20 inches NMOS (Rpd) OVSS Vin (do) Cload = 1p 0 U,(V) OVDD Vref Vref1 Vref2 t,(ns) Vout (pad) 0 Vovdd Vref1 Rpu = × Ztl Vref1 t,(ns) Rpd = Vref2 × Ztl Vovdd Vref2 Figure 6. Impedance Matching Load for Measurement 4.7.1 GPIO output buffer impedance 4.7.1.1 Tri-voltage GPIO output buffer impedance Parameter Output impedance Output impedance Table 39. Tri-voltage 1.8 V GPIO output impedance DC parameters Symbol ZO ZO Test conditions 1DSE=0 1DSE=1 Typical 33 50 Units i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 44 NXP Semiconductors 1 As programmed in the associated IOMUX (PDRV field) register. Electrical characteristics Table 40. Tri-voltage 2.5 V GPIO output impedance DC parameters Parameter Symbol Test conditions Output impedance ZO 1DSE=0 Output impedance ZO 1DSE=1 1 As programmed in the associated IOMUX (PDRV field) register. Typical 25 33 Units Table 41. Tri-voltage 3.3 V GPIO output impedance DC parameters Parameter Symbol Test conditions Output impedance ZO 1DSE=0 Output impedance ZO 1DSE=1 1 As programmed in the associated IOMUX (PDRV field) register. Typical 25 37 4.7.1.2 Dual-voltage GPIO output buffer impedance Table 42. Dual-voltage 1.8 V GPIO output impedance DC parameters Parameter Symbol Test conditions Output impedance ZO 1DSE=0 Output impedance ZO 1DSE=1 1 `As programmed in the associated IOMUX (PDRV field) register. Typical 33 50 Units Units Table 43. Dual-voltage 3.3 V GPIO output impedance DC parameters Parameter Symbol Test conditions Output impedance ZO 1DSE=0 Output impedance ZO 1DSE=1 1 As programmed in the associated IOMUX (PDRV field) register. Typical 25 37 Units i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 45 Electrical characteristics 4.7.1.3 Single-voltage 1.8 V GPIO output buffer drive strength The following table shows the GPIO output buffer drive strength (OVDD 1.8 V). Table 44. Single-voltage GPIO 1.8 V output impedance DC parameters Parameter Symbol Test conditions 1DSE=000 1DSE=001 1DSE=010 Output impedance ZO 1DSE=011 1DSE=100 1DSE=101 1DSE=110 1DSE=111 1 As programmed in the associated IOMUX (DSE field) register. Typical 200 100 55 40 30 24 20 18 4.7.1.4 Single-voltage 3.3 V GPIO output buffer drive strength The following table shows the GPIO output buffer drive strength (OVDD 3.3 V). Units Table 45. Single-voltage GPIO 3.3 V output impedance DC parameters Parameter Symbol Test conditions Output impedance ZO 1DSE=00 1DSE=01 1DSE=10 1DSE=11 1 As programmed in the associated IOMUX (DSE field) register. Typical 400 200 100 50 Units i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 46 NXP Semiconductors Electrical characteristics 4.7.2 DDR I/O output buffer impedance The following tables show DDR3L and LPDDR4 I/O output buffer impedance of the device. The ZQ Calibration cell uses a single register (ZQnPR0) to determine the target output buffer impedances of the pull-up driver and the pull-down driver, as well as the target on-die termination impedance. The resulting calibration setting is then applied to all DDR pads within the PHY complex. Table 46 and Table 48 show, respectively, the recommended ZQnPR0 field settings for the DDR3L and LPDDR4 I/Os to achieve the desired output buffer impedances. Table 47 and Table 49 show, respectively, the recommended ZQnPR0 field settings for the DDR3L and LPDDR4 I/Os to achieve the desired ODT settings. Parameter Recommended combinations for DQ /CA pins Table 46. LPDDR4 I/O output buffer impedance Typical ZQnPR0 ZPROG_ASYM_PU_DRV 5 7 9 11 Impedance 80 60 48 40 ZQnPR0 ZPROG_ASYM_PD_DRV 3 5 7 9 Impedance 120 80 60 48 Table 47. LPDDR4 I/O on-die termination impedance Parameter Typical Impedance Recommended combinations for DQ/CA pins 120.0 80.0 60.0 48.0 40.0 ZQnPR0. ZPROG_HOST_ODT 3 5 7 9 11 Table 48. DDR3L I/O output buffer impedance Parameter Recommended combinations for DQ/CA pins Typical Impedance ZQnPR0. ZPROG_ASYM_PU_DRV 48.0 9 40.0 11 34.3 13 ZQnPR0. ZPROG_ASYM_PD_DRV 9 11 13 i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 47 Electrical characteristics Table 49. DDR3L I/O on-die termination impedance Parameter Typical Impedance Recommended combinations for DQ/CA pins 120.0 60.0 40.0 ZQnPR0. ZPROG_HOST_ODT 1 3 5 NOTE · Output driver impedance is controlled across PVTs using ZQ calibration procedure. · Calibration is done against 240 external reference resistor. · Output driver impedance deviation (calibration accuracy) is ±5% (max/min impedance) across PVTs. 4.8 System Modules Timing This section contains the timing and electrical parameters for the modules in each processor. 4.8.1 Reset Timing Parameters The following figure shows the reset timing and Table 50 lists the timing parameters. POR_B (Input) CC1 Figure 7. Reset timing diagram Table 50. Reset timing parameters ID CC1 Parameter Duration of SRC_POR_B to be qualified as valid Min Max Unit 1 -- XTALOSC_RTC_ XTALI cycle i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 48 NXP Semiconductors Electrical characteristics 4.8.2 WDOG reset timing parameters The following figure shows the WDOG reset timing and Table 51 lists the timing parameters. Figure 8. SCU_WDOG_OUT timing diagram Table 51. WDOG1_B timing parameters ID Parameter CC3 Duration of SCU_WDOG_OUT assertion Min Max 1 -- Unit XTALOSC_RTC_ XTALI cycle NOTE XTALOSC_RTC_XTALI is approximately 32 kHz. XTALOSC_RTC_XTALI cycle is one period or approximately 30 s. 4.8.3 DDR SDRAMspecific parameters (LPDDR4 and DDR3L) The i.MX 8x Family of processors have been designed and tested to work with JEDEC JESD209-4A compliant LPDDR4 memory and with JEDEC JESD79-3-1 DDR3L compliant with DDR3L memory. Timing diagrams and tolerances required to work with these memories are specified in the respective documents and are not reprinted here. Meeting the necessary timing requirements for a DDR memory system is highly dependent on the components chosen and the design layout of the system as a whole. NXP cannot cover in this document all the requirements needed to achieve a design that meets full system performance over temperature, voltage, and part variation; PCB trace routing, PCB dielectric material, number of routing layers used, placement of bulk/decoupling capacitors on critical power rails, VIA placement, GND and Supply planes layout, and DDR controller/PHY register settings all are factors affecting the performance of the memory system. Consult the hardware user guide for this device and NXP validated design layouts for information on how to properly design a PCB for best DDR performance. NXP strongly recommends duplicating an NXP validated design as much as possible in the design of critical power rails, placement of bulk/decoupling capacitors and DDR trace routing between the processor and the selected DDR memory. All supporting material is readily available on the device web page on i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 49 Electrical characteristics https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applicatio ns-processors/i.mx-8-processors:IMX8-SERIES . Processors that demonstrate full DDR performance on NXP validated designs, but do not function on customer designs, are not considered marginal parts. A report detailing how the returned part behaved on an NXP validated system will be provided to the customer as closure to a customer's reported DDR issue. Customers bear the responsibility of properly designing the Printed Circuit Board, correctly simulating and modeling the designed DDR system, and validating the system under all expected operating conditions (temperatures, voltages) prior to releasing their product to market. Table 52. i.MX 8 Family DRAM controller supported SDRAM configurations Parameter Number of Controllers Number of Channels Number of Chip Selects Bus Width Maximum Clock Frequency 1 Only 16-bit external memory configurations are supported. LPDDR4 2 2 per controller 2 per channel 16 bit per channel1 1600 MHz Table 53. i.MX 8QuadXPlus/8DualXPlus DRAM controller supported SDRAM configurations Parameter Number of Controllers Number of Channels Number of Chip Selects Bus Width Maximum Clock Frequency LPDDR4 2 per controller 2 per channel 16-bit per channel 1200 MHz DDR3L 1 N/A 2 per controller 32-bit (optional 40-bit with ECC) 933 MHz 4.8.3.1 Clock/data/command/address pin allocations These processors uses generic names for clock, data and command address bus (DCF--DRAM controller functions); the following table provides mapping of clock, data and command address signals for LPDDR4 and DDR3L modes. Table 54. Clock, data, and command address signals for LPDDR4 and DDR3L modes DDR_CK0_P DDR_CK0_N Signal name LPDDR4 CK_t_A CK_c_A i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 50 NXP Semiconductors Electrical characteristics Table 54. Clock, data, and command address signals for LPDDR4 and DDR3L modes (continued) DDR_CK1_P DDR_CK1_N DDR_DQ_[15:0] DDR_DQ_[31:16] DDR_DQ_[39:32] DDR_DQS_N_[3:0] DDR_DQS_P_[3:0] DDR_DQS_N_4 DDR_DQS_P_4 DDR_DM_[3:0] DDR_DM_4 DDR_DCF00 DDR_DCF01 DDR_DCF03 DDR_DCF04 DDR_DCF05 DDR_DCF07 DDR_DCF08 DDR_DCF09 DDR_DCF10 DDR_DCF11 DDR_DCF12 DDR_DCF14 DDR_DCF15 DDR_DCF16 DDR_DCF17 DDR_DCF18 DDR_DCF19 DDR_DCF20 DDR_DCF21 DDR_DCF22 DDR_DCF23 DDR_DCF24 Signal name LPDDR4 CK_t_B CK_c_B DQ[15:0]_A DQ[15:0]_B DQS_N_[3:0] DQS_P_[3:0] DM_[3:0] CA2_A CA4_A CA5_A CA3_A ODT_CA_A CS0_A CA0_A CS1_A CKE0_A CKE1_A CA1_A CA4_B RESET_N CA5_B i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 51 Electrical characteristics Table 54. Clock, data, and command address signals for LPDDR4 and DDR3L modes (continued) DDR_DCF25 DDR_DCF26 DDR_DCF27 DDR_DCF28 DDR_DCF29 DDR_DCF30 DDR_DCF31 DDR_DCF32 DDR_DCF33 Signal name LPDDR4 ODT_CA_B CA3_B CA0_B CS0_B CS1_B CKE0_B CKE1_B CA1_B CA2_B 4.8.3.2 ECC for DDR3L i.MX 8QuadXPlus/8DualXPlus supports up to 8-bit ECC when using DDR3L only. This is accomplished through the use of a fifth byte lane (DQS4[P:N],DM4, DQ[32:39]). When using the fifth byte lane, it is not a requirement that all DDR3L devices be identical, but it is required that all devices be able to operate with the same timing parameters. This can be easily accomplished by using memory containing the same die(s), but contained in different packages. Consult the DDR3L device datasheets for timing requirements. The fifth byte lane is for the exclusive use of ECC. If not using ECC, leave the pins as not connected. For LPDDR4 mode, pins DQS4[P:N],DM4, DQ[32:39] are not used and cannot be substituted for one of the other byte lanes. If using LPDDR4 mode, leave these pins as not connected. 4.9 General-Purpose Media Interface (GPMI) Timing The GPMI controller is a flexible interface NAND Flash controller with 8-bit data width, up to 400 MB/s I/O speed, and individual chip select. It supports Asynchronous Timing mode, Source Synchronous Timing mode, and Toggle Timing mode, as described in the following subsections. i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 52 NXP Semiconductors Electrical characteristics 4.9.1 GPMI Asynchronous mode AC timing (ONFI 1.0 compatible) Asynchronous mode AC timings are provided as multiplications of the clock cycle and fixed delay. The Maximum I/O speed of GPMI in Asynchronous mode is about 50 MB/s. Figure 9 through Figure 12 depict the relative timing between GPMI signals at the module level for different operations under Asynchronous mode. Table 55 describes the timing parameters (NF1NF17) that are shown in the figures. .!.$?#,% .!.$?#%?" NF1 NF3 NF2 NF4 .!.$?7%?" NF5 .!.$?!,% .!.$?$!4!XX NF6 NF7 NF8 NF9 Command Figure 9. Command Latch Cycle Timing Diagram .!.$?#,% .!.$?#%?" .!.$?7%?" NF1 NF3 NF10 NF5 NF11 .!.$?!,% NAND_DATAxx NF6 NF8 Address NF7 NF9 Figure 10. Address Latch Cycle Timing Diagram .!.$?#,% .!.$?#%?" .!.$?7%?" NF1 NF3 NF10 NF5 NF11 .!.$?!,% NF6 NF7 .!.$?$!4!XX NF8 NF9 Data to NF Figure 11. Write Data Latch Cycle Timing Diagram i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 53 Electrical characteristics .!.$?#,% .!.$?#%?" .!.$?2%?" NF14 NF13 NF15 .!.$?2%!$9?" NF12 NF16 NF17 .!.$?$!4!XX Data from NF Figure 12. Read Data Latch Cycle Timing Diagram (Non-EDO Mode) .!.$?#,% .!.$?#%?" .!.$?2%?" NF14 NF13 NF15 .!.$?2%!$9?" NF12 NAND_DATAxx NF16 NF17 Data from NF Figure 13. Read Data Latch Cycle Timing Diagram (EDO Mode) Table 55. Asynchronous Mode Timing Parameters1 Timing ID Parameter Symbol T = GPMI Clock Cycle Unit Min Max NF1 NAND_CLE setup time tCLS (AS + DS) × T - 0.12 [see 2,3] ns NF2 NAND_CLE hold time tCLH DH × T - 0.72 [see 2] ns NF3 NAND_CEx_B setup time tCS (AS + DS + 1) × T [see 3,2] ns NF4 NAND_CEx_B hold time tCH (DH+1) × T - 1 [see 2] ns NF5 NAND_WE_B pulse width tWP DS × T [see 2] ns NF6 NAND_ALE setup time tALS (AS + DS) × T - 0.49 [see 3,2] ns NF7 NAND_ALE hold time tALH (DH × T - 0.42 [see 2] ns NF8 Data setup time tDS DS × T - 0.26 [see 2] ns NF9 Data hold time tDH DH × T - 1.37 [see 2] ns NF10 Write cycle time tWC (DS + DH) × T [see 2] ns NF11 NAND_WE_B hold time tWH DH × T [see 2] ns NF12 Ready to NAND_RE_B low tRR4 (AS + 2) × T [see 3,2] -- ns NF13 NAND_RE_B pulse width tRP DS × T [see 2] ns NF14 READ cycle time tRC (DS + DH) × T [see 2] ns NF15 NAND_RE_B high hold time tREH DH × T [see 2] ns i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 54 NXP Semiconductors Electrical characteristics Table 55. Asynchronous Mode Timing Parameters1 (continued) Timing ID Parameter Symbol T = GPMI Clock Cycle Unit Min Max NF16 Data setup on read NF17 Data hold on read tDSR tDHR -- 0.82/11.83 [see 5,6] (DS × T -0.67)/18.38 [see 5,6] ns -- ns 1 The GPMI asynchronous mode output timing can be controlled by the module's internal registers HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD. This AC timing depends on these registers settings. In the table, AS/DS/DH represents each of these settings. 2 AS minimum value can be 0, while DS/DH minimum value is 1. 3 T = GPMI clock period -0.075ns (half of maximum p-p jitter). 4 NF12 is met automatically by the design. 5 Non-EDO mode. 6 EDO mode, GPMI clock 100 MHz (AS=DS=DH=1, GPMI_CTL1 [RDN_DELAY] = 8, GPMI_CTL1 [HALF_PERIOD] = 0). In EDO mode (Figure 13), NF16/NF17 are different from the definition in non-EDO mode (Figure 12). They are called tREA/tRHOH (NAND_RE_B access time/NAND_RE_B HIGH to output hold). The typical value for them are 16 ns (max for tREA)/15 ns (min for tRHOH) at 50 MB/s EDO mode. In EDO mode, GPMI will sample NAND_DATAxx at rising edge of delayed NAND_RE_B provided by an internal DPLL. The delay value can be controlled by GPMI_CTRL1.RDN_DELAY (see the GPMI chapter of the device reference manual. The typical value of this control register is 0x8 at 50 MT/s EDO mode. However, if the board delay is large enough and cannot be ignored, the delay value should be made larger to compensate the board delay. i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 55 Electrical characteristics 4.9.2 GPMI Source Synchronous mode AC timing (ONFI 2.x compatible) The following figure shows the write and read timing of Source Synchronous mode. NF19 NF18 .!.$?#%?" NAND_CLE NAND_ALE NAND_WE/RE_B NAND_CLK NF23 NF25 NF26 NF25 NF26 NF22 NF24 NAND_DQS NAND_DQS Output enable NAND_DATA[7:0] NF20 NF21 CMD NF20 NF21 ADD NAND_DATA[7:0] Output enable Figure 14. Source Synchronous Mode Command and Address Timing Diagram i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 56 NXP Semiconductors .!.$?#%?" NF18 .!.$?#,% .!.$?!,% NAND_WE/RE_B .!.$?#,+ .!.$?$13 .!.$?$13 Output enable NF23 NF23 NF25 NF25 NF27 Electrical characteristics NF19 NF26 NF26 NF24 NF24 NF22 NF27 NF29 NF29 .!.$?$1;= .!.$?$1;= Output enable NF28 NF28 Figure 15. Source Synchronous Mode Data Write Timing Diagram NF18 .!.$?#%?" NF19 .!.$?#,% NF23 NF25 NF26 NF24 NAND_ALE NF23 NF25 NF26 NF24 .!.$?7%2% NF25 NF22 .!.$?#,+ NF26 NF25 .!.$?$13 .!.$?$13 /UTPUTENABLE .!.$?$!4!;= .!.$?$!4!;= /UTPUTENABLE Figure 16. Source Synchronous Mode Data Read Timing Diagram i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 57 Electrical characteristics .!.$?$13 NF30 .!.$?$!4!;= D0 D1 D2 D3 NF30 NF31 NF31 Figure 17. NAND_DQS/NAND_DQ Read Valid Window Table 56. Source Synchronous Mode Timing Parameters1 Timing ID Parameter Symbol T = GPMI Clock Cycle Unit Min Max NF18 NAND_CEx_B access time NF19 NAND_CEx_B hold time tCE CE_DELAY × T - 0.79 [see 2] ns tCH 0.5 × tCK - 0.63 [see 2] ns NF20 Command/address NAND_DATAxx setup time tCAS 0.5 × tCK - 0.05 ns NF21 Command/address NAND_DATAxx hold time tCAH 0.5 × tCK - 1.23 ns NF22 clock period NF23 preamble delay NF24 postamble delay tCK -- ns tPRE PRE_DELAY × T - 0.29 [see 2] ns tPOST POST_DELAY × T - 0.78 [see 2] ns NF25 NAND_CLE and NAND_ALE setup time tCALS 0.5 × tCK - 0.86 ns NF26 NAND_CLE and NAND_ALE hold time tCALH 0.5 × tCK - 0.37 ns NF27 NAND_CLK to first NAND_DQS latching transition tDQSS T - 0.41 [see 2] ns NF28 Data write setup tDS 0.25 × tCK - 0.35 ns NF29 Data write hold tDH 0.25 × tCK - 0.85 ns NF30 NAND_DQS/NAND_DQ read setup skew tDQSQ -- 2.06 -- NF31 NAND_DQS/NAND_DQ read hold skew tQHS -- 1.95 -- 1 The GPMI source synchronous mode output timing can be controlled by the module's internal registers GPMI_TIMING2_CE_DELAY, GPMI_TIMING_PREAMBLE_DELAY, GPMI_TIMING2_POST_DELAY. This AC timing depends on these registers settings. In the table, CE_DELAY/PRE_DELAY/POST_DELAY represents each of these settings. 2 T = tCK (GPMI clock period) -0.075ns (half of maximum p-p jitter). Figure 17 shows the timing diagram of NAND_DQS/NAND_DATAxx read valid window. For Source Synchronous mode, the typical value of tDQSQ is 0.85 ns (max) and 1 ns (max) for tQHS at 200 MB/s. GPMI will sample NAND_DATA[7:0] at both rising and falling edge of a delayed NAND_DQS signal, which can be provided by an internal DPLL. The delay value can be controlled by GPMI register GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the device reference manual. Generally, the typical delay value of this register is equal to 0x7 which means 1/4 clock cycle delay expected. However, if the board delay is large enough and cannot be ignored, the delay value should be made larger to compensate the board delay. i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 58 NXP Semiconductors 4.9.3 ONFI NV-DDR2 mode (ONFI 3.2 compatible) Electrical characteristics 4.9.3.1 Command and address timing ONFI 3.2 mode command and address timing is the same as ONFI 1.0 compatible Async mode AC timing. See Section 4.9.1, "GPMI Asynchronous mode AC timing (ONFI 1.0 compatible)"," for details. 4.9.3.2 Read and write timing ONFI 3.2 mode read and write timing is the same as Toggle mode AC timing. See Section 4.9.4, "Toggle mode AC Timing"," for details. 4.9.4 Toggle mode AC Timing 4.9.4.1 Command and address timing NOTE Toggle mode command and address timing is the same as ONFI 1.0 compatible Asynchronous mode AC timing. See Section 4.9.1, "GPMI Asynchronous mode AC timing (ONFI 1.0 compatible)"," for details. 4.9.4.2 Read and write timing Figure 18. Toggle mode data write timing i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 59 Electrical characteristics DEV?CLK .!.$?#%X?" .!.$?#,% .& .!.$?!,% .!.$?7%?" .!.$?2%?" .!.$?$13 .!.$?$!4!;= T#+ .& T#+ T#+ .& T#+ T#+ Figure 19. Toggle mode data read timing Table 57. Toggle mode timing parameters1 Timing ID Parameter Symbol T = GPMI Clock Cycle Unit Min. Max. NF1 NAND_CLE setup time tCLS (AS + DS) × T - 0.12 [see note2s,3] NF2 NAND_CLE hold time tCLH DH × T - 0.72 [see note2] NF3 NAND_CE0_B setup time tCS (AS + DS) × T - 0.58 [see notes,2] NF4 NAND_CE0_B hold time tCH DH × T - 1 [see note2] NF5 NAND_WE_B pulse width tWP DS × T [see note2] NF6 NAND_ALE setup time tALS (AS + DS) × T - 0.49 [see notes,2] NF7 NAND_ALE hold time tALH DH × T - 0.42 [see note2] NF8 Command/address NAND_DATAxx setup time tCAS DS × T - 0.26 [see note2] NF9 Command/address NAND_DATAxx hold time tCAH DH × T - 1.37 [see note2] NF18 NAND_CEx_B access time tCE CE_DELAY × T [see notes4,2] -- ns NF22 clock period NF23 preamble delay tCK -- -- ns tPRE PRE_DELAY × T [see notes5,2] -- ns NF24 postamble delay tPOST POST_DELAY × T +0.43 [see note2] -- ns i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 60 NXP Semiconductors Electrical characteristics Table 57. Toggle mode timing parameters1 (continued) Timing ID Parameter Symbol T = GPMI Clock Cycle Unit Min. Max. NF28 Data write setup NF29 Data write hold NF30 NAND_DQS/NAND_DQ read setup skew NF31 NAND_DQS/NAND_DQ read hold skew tDS6 tDH6 tDQSQ7 tQHS7 0.25 × tCK - 0.32 0.25 × tCK - 0.79 -- -- -- ns -- ns 3.18 3.27 1 The GPMI toggle mode output timing can be controlled by the module's internal registers HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD. This AC timing depends on these registers settings. In the table, AS/DS/DH represents each of these settings. 2 AS minimum value can be 0, while DS/DH minimum value is 1. 3 T = tCK (GPMI clock period) -0.075 ns (half of maximum p-p jitter). 4 CE_DELAY represents HW_GPMI_TIMING2[CE_DELAY]. NF18 is guaranteed by the design. Read/Write operation is started with enough time of ALE/CLE assertion to low level. 5 PRE_DELAY+1) (AS+DS) 6 Shown in Figure 18. 7 Shown in Figure 19. For DDR Toggle mode, Figure 19 shows the timing diagram of NAND_DQS/NAND_DATAxx read valid window. The typical value of tDQSQ is 1.4 ns (max) and 1.4 ns (max) for tQHS at 133 MB/s. GPMI will sample NAND_DATA[7:0] at both rising and falling edge of an delayed NAND_DQS signal, which is provided by an internal DPLL. The delay value of this register can be controlled by GPMI register GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the device reference manual. Generally, the typical delay value is equal to 0x7 which means 1/4 clock cycle delay expected. But if the board delay is big enough and cannot be ignored, the delay value should be made larger to compensate the board delay. 4.10 External Peripheral Interface Parameters The following subsections provide information on external peripheral interfaces. 4.10.1 LPSPI timing parameters All LPSPI interfaces do not have the same maximum serial clock frequency. There are two groups. LPSPI interfaces which can operate at 60 MHz in Master mode and 40 MHz in Slave mode and the other group where interfaces operate at 40 MHz in Master mode and 20 MHz in Slave mode. The same performance is achieved at 1.8 V and 3.3 V unless otherwise stated. i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 61 Electrical characteristics Below are the LPSPI interfaces and their respective chip selects: Table 58. LPSPI interfaces and chip selects LPSPI interface Chip select 60 MHz in Master mode and 40 MHz in Slave mode 40 MHz in Master mode and 20 MHz in Slave mode SPI0, SPI2, SPI2b, SPI3 SPI1, SPI1b, SPI2c Comment SPI2 - default SPI2 balls SPI2b - muxed behind audio balls SPI1 - muxed behind SAI balls SPI1b - muxed behind CSI balls SP2c - muxed behind uSDHC1 balls 4.10.1.1 LPSPI Master mode Waveform is assuming LPSPI is configured in mode 0, i.e. TCR.CPOL=0b0 and TCR.CPHA=0b0. Timing parameters are valid for all modes using appropriate edge of the clock. Figure 20. LPSPI Master mode Table 59. LPSPI timings--Master mode at 60 MHz ID Parameter -- SPIx_SCLK Cycle frequency t1 SPIx_SCLK High or Low TimeRead SPIx_SCLK High or Low TimeWrite t2 SPIx_CSy pulse width t3 SPIx_CSy Lead Time(1) Min -- 7.5 7.5 FCLK_PERIOD(2) x (PCSSCK + 1) / 2PRESCALE - 3 Max Unit 60 MHz -- ns -- ns -- ns i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 62 NXP Semiconductors Electrical characteristics Table 59. LPSPI timings--Master mode at 60 MHz (continued) ID Parameter Min Max Unit t4 SPIx_CSy Lag Time(3) FCLK_PERIOD(2) x (SCKPCS + 1) / 2PRESCALE + 3 -- ns t5 SPIx_SDO output Delay (CLOAD = 20 pF) -- 3 ns t6 SPIx_SDI Setup Time 2 -- ns t7 SPIx_SDI Hold Time 2 -- ns 1 This timing is controllable through CCR.PCSSCK and TCR.PRESCALE registers. 2 FCLK_PERIOD is the period of the functional clock provided to LPSPI module. Maximum allowed frequency is 240 MHz. 3 This timing is controllable through CCR.SCKPCS and TCR.PRESCALE registers. Table 60. LPSPI timings--Master mode at 40 MHz ID Parameter Min Max Unit -- SPIx_SCLK Cycle frequency -- 40 MHz t1 SPIx_SCLK High or Low TimeRead SPIx_SCLK High or Low TimeWrite 11 -- ns t2 SPIx_CSy pulse width t3 SPIx_CSy Lead Time(1) t4 SPIx_CSy Lag Time(3) 11 FCLK_PERIOD(2) x (PCSSCK + 1) / 2PRESCALE + 3 FCLK_PERIOD(2) x (SCKPCS + 1) / 2PRESCALE + 3 -- ns -- ns -- ns t5 SPIx_SDO output Delay (CLOAD = 20 pF) -- 5 ns t6 SPIx_SDI Setup Time 5 -- ns t7 SPIx_SDI Hold Time 4 -- ns 1 This timing is controllable through CCR.PCSSCK and TCR.PRESCALE registers. 2 FCLK_PERIOD is the period of the functional clock provided to LPSPI module. Maximum allowed frequency is 240 MHz. 3 This timing is controllable through CCR.SCKPCS and TCR.PRESCALE registers. i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 63 Electrical characteristics Figure 21. LPSPI Slave mode Table 61. LPSPI timings--Slave mode at 40 MHz ID Parameter -- SPIx_SCLK Cycle frequency t1 SPIx_SCLK High or Low TimeRead SPIx_SCLK High or Low TimeWrite t2 SPIx_CSy pulse width t3 SPIx_CSy Lead Time (CS setup time) t4 SPIx_CSy Lag Time (CS hold time) t5 SPIx_SDO output Delay (CLOAD = 20 pF) t6 SPIx_SDI Setup Time t7 SPIx_SDI Hold Time Min Max Unit -- 40 MHz 11 -- ns 11 -- ns 4 -- ns 2 -- ns -- 5 ns 2 -- ns 2 -- ns Table 62. LPSPI timings--Slave mode at 20 MHz ID Parameter -- SPIx_SCLK Cycle frequency t1 SPIx_SCLK High or Low TimeRead SPIx_SCLK High or Low TimeWrite t2 SPIx_CSy pulse width t3 SPIx_CSy Lead Time (CS setup time) Min Max Unit -- 20 MHz 22 -- ns 22 -- ns 4 -- ns i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 64 NXP Semiconductors Electrical characteristics Table 62. LPSPI timings--Slave mode at 20 MHz (continued) ID Parameter t4 SPIx_CSy Lag Time (CS hold time) t5 SPIx_SDO output Delay (CLOAD = 20 pF) t6 SPIx_SDI Setup Time t7 SPIx_SDI Hold Time Min Max Unit 2 -- ns -- 18 ns 2 -- ns 2 -- ns 4.10.2 Serial audio interface (SAI) timing parameters The timings and figures in this section are valid for noninverted clock polarity (I2S_TCR2.BCP = 0b0, I2S_RCR2.BCP = 0b0) and non-inverted frame sync polarity (I2S_TCR4.FSP = 0b0, I2S_RCR4.FSP = 0b0). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal (SAI_TXC / SAI_RXC) and/or the frame sync (SAI_TXFS / SAI_RXFS) shown in the figures below. The same performance is achieved at both 1.8 V and 3.3 V unless otherwise stated. NOTE SAI0 and SAI1 are transmit/receive capable. SAI2 and SAI3 are receive only. 4.10.2.1 SAI Master Synchronous mode In this mode, transmitter clock and frame sync are used by both transmitter and receiver (I2S_TCR2.SYNC=0b00, I2S_RCR2.SYNC=0b01). In that case, SAI interface requires only 4 signals to be routed: SAI_TXC, SAI_TXFS, SAI_TXD and SAI_RXD. SAI_RXC and SAI_RXFS can be left unconnected. I2S_RCR2.BCI shall be set to 0b1 to get setup and hold times provided in Table 63. Figure 22. SAI Master Synchronous mode i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 65 Electrical characteristics Table 63. SAI timings--Master Synchronous mode ID Parameters -- SAI TXC clock frequency t1 SAI TXC pulse width low / high t2 SAI TXFS output valid t3 SAI TXD output valid t4 SAI RXD input setup t5 SAI RXD input hold Min -- 45% -- -- 1 4 Max 49.152 55% 2 2 -- -- Unit MHz SAI_TXC period ns ns ns ns 4.10.2.2 SAI Master mode In this mode, transmitter and/or receiver part are set to bring out transmit and/or receive clock. Frame sync can be either input or output. Figure 23. SAI Master mode Table 64. SAI timings--Master mode ID Parameters -- SAI TXC / RXC clock frequency1 t1 SAI TXC / RXC pulse width low / high t2 SAI TXFS / RXFS output valid Min -- 45% -- Max 49.152 55% 2 Unit MHz TXC/RXC period ns i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 66 NXP Semiconductors Electrical characteristics Table 64. SAI timings--Master mode (continued) ID Parameters Min Max Unit t3 SAI TXD output valid -- 2 ns t4 SAI RXD/RXFS/TXFS input setup 6 -- ns t5 SAI RXD/RXFS/TXFS input hold 0 -- ns 1 Given the high setup time requirement on inputs, receiver and transmitter, when using frame sync in input, are likely to run at a lower frequency. This frequency will be driven by characteristics of the external component connected to the interface. 4.10.2.3 SAI Slave mode In this mode, transmitter and/or receiver parts are set to receive transmit and/or receive clock from external world. Frame sync can be either input or output. Figure 24. SAI Slave mode Table 65. SAI timings--Slave mode ID Parameters -- SAI TXC/RXC clock frequency t11 SAI TXC/RXC pulse width low/high t12 SAI TXFS/RXFS output valid t13 SAI TXD output valid t14 SAI RXD/RXFS/TXFS input setup t15 SAI RXD/RXFS/TXFS input hold Min -- 45% -- -- 1 4 Max 24.576 55% 13 13 -- -- Unit MHz TXC/RXC period ns ns ns ns i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 67 Electrical characteristics 4.10.3 Enhanced serial audio interface (ESAI) The same performance is achieved at both 1.8 V and 3.3 V unless otherwise stated. SCKT (Input / Output) FST (bit) out FST (word) out Data Out FST (bit) in FST (word) in Flags Out t1 t1 2t 2t 2t t3 t4 t5 t6 First bit 4t t5 t6 t7 Figure 25. ESAI Transmit timing 2t Last bit t3 i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 68 NXP Semiconductors Electrical characteristics Figure 26. ESAI Receive timing The following table shows the interface timing values. The ID field in the table refers to timing signals found in Figure 25 and Figure 26. Table 66. Enhanced Serial Audio Interface (ESAI) Timing ID Parameters Min Max Condition1 Unit -- Clock frequency -- 24.576 -- t1 SCKT / SCKT pulse width high / low 45% 55% -- t2 FST output delay -- 10 x ck 2 i ck t3 TX data - high impedance / valid data -- 9 x ck 1 i ck t4 TX data output delay -- 10 x ck 2 i ck t5 FST - setup requirement -- 2 x ck 10 i ck t6 FST - hold requirement -- 2 x ck 0 i ck t7 Flag output delay 10 x ck 2 i ck MHz SCKT / SCKR period ns ns ns ns ns ns i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 69 Electrical characteristics Table 66. Enhanced Serial Audio Interface (ESAI) Timing (continued) ID Parameters Min Max Condition1 Unit t8 FSR output delay 7 x ck ns 4 i ck a t9 RX data pins - setup requirement 2 -- x ck ns 10 i ck t10 RX data pins - hold requirement 2 -- x ck ns 0 i ck t11 FSR - setup requirement 2 -- x ck ns 10 i ck a t12 FSR - hold requirement 2 -- x ck ns 0 i ck a t13 Flags - setup requirement 2 -- x ck ns 10 i ck s t14 Flags - hold requirement 2 -- x ck ns 0 i ck s -- RX_HF_CLK / TX_HX_CLK clock cycle 20 -- -- ns -- TX_HF_CLK input to SCKT 10 -- ns -- RX_HF_CLK input to SCKR 10 -- ns 1 i ck = internal clock x ck = external clock i ck a = internal clock, asynchronous mode (SCKT and SCKR are two different clocks) i ck s = internal clock, synchronous mode (SCKT and SCKR are the same clock) 4.10.4 Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC) AC Timing This section describes the electrical information of the uSDHC, including: · SD3.1/eMMC5.1 High-Speed mode AC Timing · eMMC5.1 DDR 52 mode/SD3.1 DDR 50 mode timing · HS400 AC timing--eMMC 5.1 only · HS200 Mode Timing · SDR50/SDR104 AC Timing i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 70 NXP Semiconductors Electrical characteristics 4.10.4.1 SD3.1/eMMC5.1 High-Speed mode AC Timing The following figure depicts the timing of SD3.1/eMMC5.1 High-Speed mode, and Table 67 lists the timing characteristics. SD4 SD2 SD1 SD5 SDx_CLK SD3 SD6 Output from uSDHC to card SDx_DATA[7:0] SD7 SD8 Input from card to uSDHC SDx_DATA[7:0] Figure 27. SD3.1/eMMC5.1 High-Speed mode Timing Table 67. SD3.1/eMMC5.1 High-Speed mode interface timing specification ID Parameter Symbols Min Max Unit Card Input Clock SD1 Clock Frequency (Low Speed) Clock Frequency (SD/SDIO Full Speed/High Speed) Clock Frequency (MMC Full Speed/High Speed) Clock Frequency (Identification Mode) SD2 Clock Low Time SD3 Clock High Time SD4 Clock Rise Time SD5 Clock Fall Time fPP1 0 400 fPP2 0 25/50 fPP3 0 20/52 fOD 100 400 tWL 7 -- tWH 7 -- tTLH -- 3 tTHL -- 3 eSDHC Output/Card Inputs SD_CMD, SD_DATA (Reference to SD_CLK) kHz MHz MHz kHz ns ns ns ns SD6 eSDHC Output Delay tOD 6.6 3.6 ns eSDHC Input/Card Outputs SD_CMD, SD_DATA (Reference to SD_CLK) SD7 eSDHC Input Setup Time tISU 2.5 -- ns SD8 eSDHC Input Hold Time4 tIH 1.5 -- ns 1 In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V. 2 In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 025 MHz. In high-speed mode, clock frequency can be any value between 050 MHz. i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 71 Electrical characteristics 3 In normal (full) speed mode for MMC card, clock frequency can be any value between 020 MHz. In high-speed mode, clock frequency can be any value between 052 MHz. 4 To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns. 4.10.4.2 eMMC5.1 DDR 52 mode/SD3.1 DDR 50 mode timing The following figure depicts the timing of eMMC5.1 DDR 52 mode/SD3.1 DDR 50 mode, and Table 68 lists the timing characteristics. Be aware that only SDx_DATA is sampled on both edges of the clock (not applicable to SD_CMD). SD1 SDx_CLK SD2 SD2 Output from eSDHCv3 to card SDx_DATA[7:0] ...... SD3 SD4 Input from card to eSDHCv3 SDx_DATA[7:0] ...... Figure 28. eMMC 5.1 timing Figure 29. eMMC5.1 DDR 52 mode/SD3.1 DDR 50 mode interface timing Table 68. eMMC5.1 DDR 52 mode/SD3.150 mode interface timing specification ID Parameter Symbols Min Max Card Input Clock1 SD1 Clock Frequency (eMMC5.1 DDR) SD1 Clock Frequency (SD3.1 DDR) fPP 0 52 fPP 0 50 uSDHC Output / Card Inputs SD_CMD, SDx_DATAx (Reference to CLK) SD2 uSDHC Output Delay tOD 2.8 6.8 uSDHC Input / Card Outputs SD_CMD, SDx_DATAx (Reference to CLK) SD3 uSDHC Input Setup Time SD4 uSDHC Input Hold Time 1 Clock duty cycle will be in the range of 47% to 53%. tISU 1.7 -- tIH 1.5 -- Unit MHz MHz ns ns ns 4.10.4.3 HS400 AC timing--eMMC 5.1 only Figure 30 depicts the timing of HS400. Table 69 lists the HS400 timing characteristics. Be aware that only data is sampled on both edges of the clock (not applicable to CMD). The CMD input/output timing for i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 72 NXP Semiconductors Electrical characteristics HS400 mode is the same as CMD input/output timing for SDR104 mode. Check SD5, SD6 and SD7 parameters in Table 71 SDR50/SDR104 Interface Timing Specification for CMD input/output timing for HS400 mode. Figure 30. HS400 timing Table 69. HS400 interface timing specifications ID Parameter Symbols Min Max Unit Card Input clock SD1 Clock Frequency fPP 0 200 Mhz SD2 Clock Low Time SD3 Clock High Time tCL 0.46 × tCLK 0.54 × tCLK ns tCH 0.46 × tCLK 0.54 × tCLK ns uSDHC Output/Card inputs DAT (Reference to SCK) SD4 Output Skew from Data of tOSkew1 0.45 -- ns Edge of SCK SD5 Output Skew from Edge of tOSkew2 0.45 -- ns SCK to Data uSDHC input/Card Outputs DAT (Reference to Strobe) SD6 uSDHC input skew SD7 uSDHC hold skew tRQ -- 0.45 ns tRQH -- 0.45 ns i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 73 Electrical characteristics 4.10.4.4 HS200 Mode Timing The following figure depicts the timing of HS200 mode, and Table 70 lists the HS200 timing characteristics. SCK SD1 SD2 SD3 SD4/SD5 8-bit output from uSDHC to eMMC 8-bit input from eMMC to uSDHC SD6 SD7 SD8 Figure 31. HS200 Mode Timing Table 70. HS200 Interface Timing Specification ID Parameter Symbols Min Max Card Input Clock SD1 Clock Frequency Period SD2 Clock Low Time SD2 Clock High Time tCLK tCL tCH 5.0 0.46 × tCLK 0.46 × tCLK -- 0.54 × tCLK 0.54 × tCLK uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK) SD5 uSDHC Output Delay tOD 1.6 1 uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)1 SD8 Card Output Data Window 1HS200 is for 8 bits while SDR104 is for 4 bits. tODW 0.5*tCLK -- Unit ns ns ns ns ns i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 74 NXP Semiconductors Electrical characteristics 4.10.4.5 SDR50/SDR104 AC Timing The following figure depicts the timing of SDR50/SDR104, and Table 71 lists the SDR50/SDR104 timing characteristics. SCK Output from uSDHC to card SD1 SD2 SD3 SD5 SD4 SD6 SD7 Input from card to uSDHC SD8 Figure 32. SDR50/SDR104 timing Table 71. SDR50/SDR104 Interface Timing Specification ID Parameter Symbols Min Max Unit Card Input Clock SD1 SD2 SD3 Clock Frequency Period Clock Low Time Clock High Time tCLK 4.8 -- ns tCL 0.46 × tCLK 0.54 × tCLK ns tCH 0.46 × tCLK 0.54 × tCLK ns uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR50 (Reference to SDx_CLK) SD4 uSDHC Output Delay tOD 3 1 ns uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR104 (Reference to SDx_CLK) SD5 uSDHC Output Delay tOD 1.6 1 ns uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR50 (Reference to SDx_CLK) SD6 uSDHC Input Setup Time tISU 2.5 -- ns SD7 uSDHC Input Hold Time tIH 1.5 -- ns uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR104 (Reference to SDx_CLK)1 SD8 Card Output Data Window tODW 0.5 × tCLK -- ns 1Data window in SDR100 mode is variable. i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 75 Electrical characteristics 4.10.4.6 Bus Operation Condition for 3.3 V and 1.8 V Signaling The DC parameters for the NVCC_SD1, NVCC_SD2, and NVCC_SD3 supplies are identical to those shown in "," and Table 31, "Dual-voltage 1.8 V GPIO DC parameters," on page 37Table 32, "Dual-voltage 3.3 V GPIO DC parameters," on page 38. 4.10.5 Ethernet Controller (ENET) AC Electrical Specifications ENET interface supporting RGMII protocol in delay and non-delay mode. RGMII is used to support up to 1000 Mbps Ethernet as well as RMII protocol. RMII is used to support up to 100 Mbps Ethernet. NOTE Both ENET0 and ENET1 support RGMII at 1.8 V and 2.5 V, and RMII at 3.3 V. Table 72. RGMII/RMII pin mapping Pin name1 RGMII RMII Comment2 ENETx_RGMII_TXC RGMII_TXC RCLK50M RCLK50M can be an input or an output. It's using different Alternate pin muxing modes. Refer to pin muxing for details. ENETx_RGMII_TX_CTL RGMII_TX_CTL RMII_TXEN -- ENETx_RGMII_TXD0 RGMII_TXD0 RMII_TXD0 -- ENETx_RGMII_TXD1 RGMII_TXD1 RMII_TXD1 -- ENETx_RGMII_TXD2 RGMII_TXD2 N/A -- ENETx_RGMII_TXD3 RGMII_TXD3 N/A -- ENETx_RGMII_RXC RGMII_RXC N/A -- ENETx_RGMII_RX_CTL RGMII_RX_CTL RMII_CRS_DV -- ENETx_RGMII_RXD0 RGMII_RXD0 RMII_RXD0 -- ENETx_RGMII_RXD1 RGMII_RXD1 RMII_RXD1 -- ENETx_RGMII_RXD2 RGMII_RXD2 RMII_RXER RMII_RXER is mapped on ALT1 mode of pin muxing. ENETx_RGMII_RXD3 RGMII_RXD3 N/A -- ENETx_REFCLK_125M_25M RGMII_REF_CLK N/A RGMII_REF_CLK is optional for RGMII operation and dependent on the intended clock configuration. ENETx_MDIO RGMII_MDIO RMII_MDIO -- ENETx_MDC RGMII_MDC RMII_MDC -- 1 x can be 0 or 1. 2 Except for RCLK50M and RMII_RXER, all other RMII functions are using the same pin muxing mode as RGMII. i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 76 NXP Semiconductors 4.10.5.1 RGMII 4.10.5.1.1 No-Internal-Delay mode This mode corresponds to the RGMIIv1.3 specification. Electrical characteristics Figure 33. RGMII timing diagram--No-Internal-Delay mode Table 73. RGMII timings--No-Internal-Delay mode ID Parameter Min Typ Max Unit TXC / RXC frequency -- 125 -- MHz t1 Clock cycle 7.2 8 8.8 ns t2 Data to clock output skew -500 -- 500 ps t3 Data to clock input skew1(1) 1 -- 2.6 ns 1 This implies that PC board design requires clocks to be routed such that an additional trace delay of greater than 1.5 ns and less than 2.0 ns is added to the associated clock signal. 4.10.5.1.2 Internal-delay mode This mode corresponds to RGMIIv2.0 specification. i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 77 Electrical characteristics Figure 34. RGMII timing diagram--Internal-Delay mode Table 74. RGMII timing--Internal-Delay mode ID Parameter TXC / RXC frequency t1 Clock cycle t2 TXD setup time t3 TXD hold time t4 RXD setup time t5 RXD hold time Min Typ Max -- 125 -- 7.2 8 8.8 1.2 -- -- 1.2 -- -- 0 -- -- 2.5 -- -- Unit MHz ns ns ns ns ns 4.10.5.2 RMII RMII interface is matching RMII v1.2 specification. In RMII mode, the reference clock can be generated internally and provided to the PHY through RCLK50M_OUT. Or, it come from and external 50MHz clock generator which is connected to the PHY and to i.MX8 through RCLK50M_IN pin. i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 78 NXP Semiconductors Electrical characteristics Figure 35. RMII timing diagram Timings in table below are covering both cases: reference clock generated internally or externally. Table 75. RMII timing ID Parameter t1 Reference clock Reference clock accuracy Reference clock duty-cycle t2 RMII_TXEN, RMII_TXD output delay t3 RMII_CRS_DV, RMII_RXD setup time t4 RMII_CRS_DV, RMII_RXD hold time Min Typ Max Unit -- 50 -- MHz -- -- 50 ppm 35 -- 65 % 2 -- 12 ns 4 -- -- ns 2 -- -- ns 4.10.5.3 MDIO MDIO is the control link used to configure Ethernet PHY connected to i.MX8 device. i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 79 Electrical characteristics Figure 36. MDIO timing diagram Table 76. MDIO timing ID Parameter MDC frequency t1 MDC high / low pulse width t2 MDIO output delay t3 MDIO setup time t4 MDIO hold time Min Typ Max Unit -- 2.5 -- MHz 180 -- -- % 0 -- 20 ns 10 -- -- ns 10 -- -- ns 4.10.6 CAN network AC Electrical Specifications The Flexible Controller Area Network (FlexCAN) module is a communication controller implementing the CAN protocol according to the CAN with Flexible Data rate (CAN FD) protocol and the CAN 2.0B protocol specification. The processor has three CAN modules available for systems design. Tx and Rx ports for both modules are multiplexed with other I/O pins. See the IOMUXC chapter of the device reference manual to see which pins expose Tx and Rx pins; these ports are named FLEXCAN_TX and FLEXCAN_RX, respectively. i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 80 NXP Semiconductors Electrical characteristics 4.10.7 I2C Module Timing Parameters This section describes the timing parameters of the I2C module. The following figure depicts the timing of the I2C module, and Table 77 lists the I2C module timing characteristics. I2Cx_SDA IC10 IC11 IC9 IC2 I2Cx_SCL START IC8 IC4 IC7 IC10b IC6 IC5 IC1 IC11b START Figure 37. I2C bus timing IC3 STOP START Table 77. I2C Module Timing Parameters Standard Mode Fast Mode ID Parameter Unit Min Max Min Max IC1 I2Cx_SCL cycle time 10 -- 2.5 -- µs IC2 Hold time (repeated) START condition 4.0 -- 0.6 -- µs IC3 Set-up time for STOP condition 4.0 -- 0.6 -- µs IC4 Data hold time 01 3.452 01 0.92 µs IC5 HIGH Period of I2Cx_SCL Clock 4.0 -- 0.6 -- µs IC6 LOW Period of the I2Cx_SCL Clock 4.7 -- 1.3 -- µs IC7 Set-up time for a repeated START condition 4.7 -- 0.6 -- µs IC8 Data set-up time 250 -- 1003 -- ns IC9 Bus free time between a STOP and START condition 4.7 -- 1.3 -- µs IC10/IC10b Rise time of both I2Cx_SDA and I2Cx_SCL signals IC11/IC11b Fall time of both I2Cx_SDA and I2Cx_SCL signals -- 1000 20 + 0.1Cb4 300 ns -- 300 20 + 0.1Cb4 300 ns IC12 Capacitive load for each bus line (Cb) -- 400 -- 400 pF 1 A device must internally provide a hold time of at least 300 ns for I2Cx_SDA signal in order to bridge the undefined region of the falling edge of I2Cx_SCL. 2 The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2Cx_SCL signal. 3 A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement of Set-up time (ID No IC7) of 250 ns must be met. This automatically is the case if the device does not stretch the LOW period of the I2Cx_SCL signal. If such a device does stretch the LOW period of the I2Cx_SCL signal, it must output the next data bit to the I2Cx_SDA line max_rise_time (IC9) + data_setup_time (IC7) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the I2Cx_SCL line is released. 4 Cb = total capacitance of one bus line in pF. i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 81 Electrical characteristics Table 78. I2C timing Fast Mode Plus ID Parameter Min Max IC1 SCL clock frequency -- 1 IC2 Hold time (repeated) START condition 260 -- IC3 Set-up time for STOP condition 260 -- IC4 Data hold time 0 -- IC5 HIGH Period of I2Cx_SCL Clock 260 -- IC6 LOW Period of the I2Cx_SCL Clock 500 -- IC7 Set-up time for a repeated START condition 260 -- IC8 Data set-up time 50 -- IC9 Bus free time between a STOP and START condition 500 -- IC10 Rise time of I2Cx_SDA signals -- 120 IC11 Fall time of I2Cx_SDA signals 12 (@3.3 V) 120 6.5 (@1.8 V) IC10b Rise time of I2Cx_SCL signals -- 120 IC11b Fall time of I2Cx_SCL signals 12 (@3.3 V) 120 6.5 (@1.8 V) IC12 Capacitive load for each bus line (Cb) -- 550 1 High-speed mode is only available for I2C modules in DMA, SCU and Cortex-M4 subsystems. High Speed1 Unit Min Max -- 3.4 MHz 160 -- ns 160 -- ns 0 70 ns 60 -- ns 160 -- ns 160 -- ns 10 -- ns 150 -- ns 10 80 ns 10 80 ns 10 40 ns 10 40 ns -- 100 pF 4.10.8 MIPI-DSI/LVDS combo display output specifications The physical pins of the combo display output controller can be used in LVDS mode or in DSI display mode. 4.10.8.1 MIPI-DSI/LVDS display bridge module parameters Maximum frequency support for combination MIPI-DSI/LVDS modules: Function1,2 DSI Mix Mix Table 79. MIPI-DSI/LVDS combo pins Channel A DSI up to 1.05 Gb/per lane 4 pairs LVDS up to 1.05 Gb per pair DSI up to 1.05 Gb/per lane Channel B DSI up to 1.05 Gb/per lane DSI up to 1.05 Gb/per lane 4 pairs LVDS up to 1.05 Gb per pair i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 82 NXP Semiconductors Electrical characteristics Table 79. MIPI-DSI/LVDS combo pins (continued) Function1,2 Channel A Channel B LVDS (single channel) 4 pairs LVDS up to 1.05 Gb per pair 4 pairs LVDS up to 1.05 Gb per pair LVDS (dual channel) 8 pairs LVDS up to 595 Mb per pair 1 For DSI the maximum clock speed is 1.05 GHz. 2 For LVDS in single-channel operation the maximum clock speed is 150 MHz; in dual-channel operation with a single synchronized clock the maximum clock speed is 85 MHz. 4.10.8.2 LVDS display bridge (LDB) module electrical specifications The MIPI DSI/LVDS interface is compatible with TIA/EIA 644-A standard. For more details, see TIA/EIA STANDARD 644-A, "Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits." Table 80. LVDS Display Bridge (LDB) Electrical Specifications Parameter Differential Voltage Output Voltage Output Voltage High Output Voltage Low Offset Static Voltage VOS Differential Output short-circuited to GND Output short current Symbol VOD Voh Vol VOS VOSDIFF ISA ISB ISAB Test Condition Min 100 Differential load 100 differential load (0 V Diff--Output High Voltage static) 100 differential load (0 V Diff--Output Low Voltage static) Two 49.9 resistors in series between N-P terminal, with output in either Zero or One state, the voltage measured between the 2 resistors. Difference in VOS between a One and a Zero state With the output common shorted to GND 0.25 -- 0.925 1.125 -- -- -- Max 0.4 1.475 Units V V -- V 1.275 V -- mV 40 mA 12 mA 4.10.8.3 MIPI-DSI HS-TX specifications Symbol VCMTX1 |VCMTX|(1,0) |VOD|1 Table 81. MIPI high-speed transmitter DC specifications Parameter High Speed Transmit Static Common Mode Voltage VCMTX mismatch when Output is Differential-1 or Differential-0 High Speed Transmit Differential Voltage Min Typ Max Unit 150 200 250 mV -- -- 5 mV 140 200 270 mV i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 83 Electrical characteristics Table 81. MIPI high-speed transmitter DC specifications (continued) Symbol Parameter |VOD| VOHHS1 VOD mismatch when Output is Differential-1 or Differential-0 High Speed Output High Voltage ZOS Single Ended Output Impedance ZOS Single Ended Output Impedance Mismatch 1 Value when driving into load impedance anywhere in the ZID range. Min Typ Max Unit -- -- 10 mV -- -- 360 mV 40 50 62.5 -- -- 10 % Table 82. MIPI high-speed transmitter AC specifications Symbol Parameter VCMTX(HF) Common-level variations above 450 MHz VCMTX(LF) Common-level variation between 50-450 MHz tR and tF1 Rise Time and Fall Time (20% to 80%) 1 UI is the long-term average unit interval. Min Typ ---- ---- 100 -- Max 15 25 0.35 UI Unit mVRMS mVPEAK ps 4.10.8.4 MIPI-DSI LP-TX specifications Table 83. MIPI low-power transmitter DC specifications Symbol Parameter Min Typ Max Unit VOH1 Thevenin Output High Level 1.1 1.2 1.3 V VOL Thevenin Output Low Level 50 -- 50 mV ZOLP2 Output Impedance of Low Power Transmitter 110 -- -- 1 This specification can only be met when limiting the core supply variation from 1.1 V till 1.3 V. 2 Although there is no specified maximum for ZOLP, the LP transmitter output impedance ensures the TRLP/TFLP specification is met. Table 84. MIPI low-power transmitter AC specifications Symbol Parameter Min Typ Max Unit TRLP/TFLP1 15% to 85% Rise Time and Fall Time -- -- 25 ns TREOT1,2,3 30% to 85% Rise Time and Fall Time -- -- 35 ns TLP-PULSE-TX4 Pulse width of the LP exclusive-OR clock: First LP exclusive-OR clock pulse after Stop 40 -- -- ns state or last pulse before Stop state Pulse width of the LP exclusive-OR clock: All other pulses 20 -- -- ns TLP-PER-TX Period of the LP exclusive-OR clock 90 -- -- ns i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 84 NXP Semiconductors Electrical characteristics Table 84. MIPI low-power transmitter AC specifications (continued) Symbol Parameter Min Typ Max Unit V/tSR1,5,6,7 Slew Rate @ CLOAD= 0 pF Slew Rate @ CLOAD= 5 pF 30 -- 500 mV/ns 30 -- 200 mV/ns Slew Rate @ CLOAD= 20 pF 30 -- 150 mV/ns Slew Rate @ CLOAD= 70 pF 30 -- 100 mV/ns CLOAD Load Capacitance 0 -- 70 pF 1 CLOAD includes the low equivalent transmission line capacitance. The capacitance of TX and RX are assumed to always be < 10 pF. The distributed line capacitance can be up to 50 pF for a transmission line with 2 ns delay. 2 The rise-time of TREOT starts from the HS common-level at the moment of the differential amplitude drops below 70 mV, due to stopping the differential drive. 3 With an additional load capacitance CCM between 0 to 60 pF on the termination center tap at RX side of the lane. 4 This parameter value can be lower then TLPX due to differences in rise vs. fall signal slopes and trip levels and mismatches between Dp and Dn LP transmitters. Any LP exclusive-OR pulse observed during HS EoT (transition from HS level to LP-11) is glitch behavior as described in Low-Power Receiver section. 5 When the output voltage is between 15% and below 85% of the fully settled LP signal levels. 6 Measured as average across any 50 mV segment of the output signal transition. 7 This value represents a corner point in a piecewise linear curve. 4.10.8.5 MIPI-DSI LP-RX specifications Table 85. MIPI low power receiver DC specifications Symbol VIH VIL VIL-ULPS VHYST Parameter Logic 1 input voltage Logic 0 input voltage, not in ULP state Logic 0 input voltage, ULP state Input hysteresis Min Typ Max Unit 880 -- 1.3 mV -- -- 550 mV -- -- 300 mV 25 -- -- mV Table 86. MIPI low power receiver AC specifications Symbol Parameter Min Typ Max Unit eSPIKE1,2 TMIN-RX3 Input pulse rejection Minimum pulse width response -- -- 20 -- VINT Peak Interference amplitude -- -- fINT Interference frequency 450 -- 1 Time-voltage integration of a spike above VIL when in LP-0 state or below VIH when in LP-1 state. 2 An impulse below this value will not change the receiver state. 3 An input pulse greater than this value shall toggle the output. 300 V.ps -- ns 200 mV -- MHz i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 85 Electrical characteristics 4.10.8.6 MIPI-DSI LP-CD specifications Table 87. MIPI contention detector DC specifications Symbol VIHCD VILCD Parameter Logic 1 contention threshold Logic 0 contention threshold Min Typ Max Unit 450 -- -- mV -- -- 200 mV 4.10.8.7 MIPI-DSI DC specifications Table 88. MIPI input characteristics DC specifications Symbol Parameter Min Typ Max Unit VPIN ILEAK1 Pad signal voltage range Pin leakage current 50 -- 1350 mV 10 -- 10 A VGNDSH Ground shift 50 -- 50 mV VPIN(absmax)2 Maximum pin voltage level 0.15 -- 1.45 V TVPIN(absmax)3 Maximum transient time above VPIN(max) or below VPIN(min) -- -- 20 ns 1 When the pad voltage is within the signal voltage range between VGNDSH(min) to VOH + VGNDSH(max) and the Lane Module is in LP receive mode. 2 This value includes ground shift. 3 The voltage overshoot and undershoot beyond the VPIN is only allowed during a single 20 ns window after any LP-0 to LP-1 transition or vice versa. For all other situations it must stay within the VPIN range. 4.10.9 PCIe 3.0 PHY Parameters The TX and RX eye diagrams specifications are per the template shown in the following figure. The summary of specifications is shown in Table 89 and Table 90. Note that the time closure (1A OPENING) in the eye templates needs not match jitter specifications in the Standards Specifications, as there are such discrepancies in some Standards Specifications. The design meets the tightest of specifications in case of discrepancy. i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 86 NXP Semiconductors Electrical characteristics Figure 38. TX and RX eye diagram template Table 89. PCIe transmitter eye specifications for example standards UI AOPENING BOPENING AOPENING BOPENING VDIFFp-pmin VDIFFp-pmax ps UI ps mV PCI Express Gen 1 Transition Bit 400 0.75 0 300 0 800 12001 PCI ExpressGen 1 De-emphasized Bit 400 0.75 0 300 0 PCI Express Gen 2 Transition Bit 200 0.75 0 150 0 PCI Express Gen 2 De-emphasized Bit 200 0.75 0 150 0 1 VDIFFp-p eye opening is limited to VDDIO under matched termination conditions. 505 757 800 12001 379 850 Table 90. PCIe receiver eye specifications for example standards UI AOPENING BOPENING AOPENING BOPENING VDIFFp-pmin VDIFFp-pmax ps UI ps mV PCI Express Gen 1 Transition Bit 400 0.4 0 160 0 175 PCI Express Gen 2 Transition Bit 200 0 0 0 0 100 PCI Express Gen 3 Virtual EYE1 125 0.3 0 38 0 25 1 PCIE 3.0 8 GT/s measured using PCIE reference equalizer + CDR per PCIE specification. 1200 1200 1300 i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 87 Electrical characteristics Table 91. PCIe differential output driver characteristics (including board and load) Parameter Min Typ Max Units Notes Output Rise and fall time TR, TF Output Rise/Fall matching 175 -- 350 ps 1 -- -- 20 % 1, 2 Output skewTOSKEW Initialization time from assertion of TXOE -- -- 50 ps -- 100 -- -- ns -- Initialization time from assertion of TXENA -- 10 -- s -- Transmission line characteristic impedance (ZO) -- Driver output impedance, single ended (small signal @ -- Vout=Vcm) 50 1000 -- -- -- -- Output single ended voltage (RS= 33, RT= 50 ) VOH IOH@ 6 * IR VOL 0.65 -13 -0.20 0.71 -14.2 0.00 0.85 -17 0.05 V 3, 4 mA V 3 Output common mode voltage (RS = 33, RT= 50 ) |VOCM| VOCM (DC) VOCM (AC) Buffer induced deterministic jitter (absolute, pk-pk) 0.25 -0.015 -0.050 -- 0.375 -- 0.55 0.015 0.050 4 V 5 6 ps 7,8 Reference Buffer Dynamic Power (Digital) -- 0.015 0.66 A 9 Reference Buffer Dynamic Power (Analog) -- 2.8 3.14 mA 9 Output Buffer Dynamic Power (Digital) -- 0.035 1.8 A 9 Output Buffer Dynamic Power (Analog) -- 18.9 22.11 mA 9 1 When the output is transitioning between logic 0 and logic 1, or logic 1 and logic 0, and driving a terminated transmission line, the outputs monotonically transition between VOL and VOH, VOH, and VOL respectively. Target rise and fall times observed at the receiver and are primarily set by board trace impedance and Load capacitance. Rise and fall times are defined by 25% and 75% crossing points. 2 Calculated as: 2 × (TRTF) / (TR+ TF) 3 IR is proportional to the reference current. Measured across RT. The primary contributor to output voltage spread is VDD spread, and so a VDD tighter than ±10% may be required to achieve this spread. 4 Higher output voltages may occur depending on load, power supply, and selected output drive. Higher output voltages may transiently occur during initialization period following TXENA assertion. 5 Peak change in output differential voltage when driving a logic 0 and when driving a logic 1 under DC conditions. 6 Peak change in output differential voltage when driving a logic 0 and when driving a logic 1 under AC conditions. 7 Measured under "clean power supply and ground" conditions, and after de-embedding the jitter of the input, measured over a time span of 1000 cycles 8 Power supply induced jitter is included under this category, and the power supply variation is to be less than 8mVpp. Note that customer has to be uncommonly careful with power supply fidelity due to the small jitter numbers. 9 Power consumption is simulated under the following conditions: Typ: TT, VDD=1.0 V, VD18=1.8 V, 25 °C Max: FF, VDD=1.1 V, VD18=1.98 V, 125 °C Dynamic: TXENA=1, TXOE=1 Static: TXENA=0, TXOE=1 i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 88 NXP Semiconductors 4.10.9.1 PCIE_REXT reference resistor connection The following figure shows the PCIE_REXT reference resistor connection. Electrical characteristics Figure 39. PCIE_REXT reference resistor connection 4.10.9.2 PCIE_REF_CLK Contact an NXP representative to obtain the hardware development guide for this device, which contains details on the PCIe reference clock requirements. 4.10.10 Pulse Width Modulator (PWM) Timing Parameters This section describes the electrical information of the PWM. The PWM can be programmed to select one of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before being input to the counter. The output is available at the pulse-width modulator output (PWMO) external pin. The following figure depicts the timing of the PWM, and Table 92 lists the PWM timing parameters. PWMn_OUT Figure 40. PWM Timing Table 92. PWM Output Timing Parameters ID Parameter -- PWM Module Clock Frequency P1 PWM output pulse width high P2 PWM output pulse width low Min Max 0 ipg_clk 15 -- 15 -- Unit MHz ns ns i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 89 Electrical characteristics 4.10.11 LCD controller (LCDIF) parameters Figure 41 shows the LCDIF timing, and the table below lists the timing parameters. LCDn_CLK (falling edge capture) LCDn_CLK (rising edge capture) LCDn_DATA[23:00] LCDn Control Signals L1 L2 L3 L4 L5 L6 L7 Figure 41. LCD Timing Table 93. LCD Timing Parameters ID Parameter Symbol Min L1 LCD pixel clock frequency tCLK(LCD) -- L2 LCD pixel clock high (falling edge capture) tCLKH(LCD) 6 L3 LCD pixel clock low (rising edge capture) tCLKL(LCD) 6 L4 LCD pixel clock high to data valid (falling edge capture) td(CLKH-DV) -1 L5 LCD pixel clock low to data valid (rising edge capture) td(CLKL-DV) -1 L6 LCD pixel clock high to control signal valid (falling edge capture) td(CLKH-CTRLV) -1 L7 LCD pixel clock low to control signal valid (rising edge capture) td(CLKL-CTRLV) -1 Max Unit 80 MHz -- ns -- ns 1 ns 1 ns 1 ns 1 ns 4.10.11.1 LCDIF signal mapping The table below lists the details about the mapping signals. Table 94. LCD Signal Parameters Pin name 8-bit DOTCLK LCD 16-bit DOTCLK LCD 18-bit DOTCLK LCD 24-bit DOTCLK LCD 8-bit DVI LCD IF IF IF IF IF LCD_RS LCD_VSYNC* (Two options) LCD_HSYNC -- LCD_VSYNC LCD_HSYNC -- LCD_VSYNC LCD_HSYNC -- LCD_VSYNC LCD_HSYNC -- LCD_VSYNC LCD_HSYNC CCIR_CLK -- -- i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 90 NXP Semiconductors LCD_DOTCLK LCD_ENABLE LCD_D23 LCD_D22 LCD_D21 LCD_D20 LCD_D19 LCD_D18 LCD_D17 LCD_D16 LCD_D15 / VSYNC* LCD_D14 / HSYNC** LCD_D13 / LCD_DOTCLK ** LCD_D12 / ENABLE** LCD_D11 LCD_D10 LCD_D9 LCD_D8 LCD_D8 LCD_D7 LCD_D6 LCD_D5 LCD_D4 LCD_D3 LCD_D2 LCD_D1 LCD_D0 LCD_RESET LCD_BUSY / LCD_VSYNC Electrical characteristics Table 94. LCD Signal Parameters (continued) LCD_DOTCLK LCD_DOTCLK LCD_DOTCLK LCD_DOTCLK -- LCD_ENABLE LCD_ENABLE LCD_ENABLE LCD_ENABLE -- -- -- -- R[7] -- -- -- -- R[6] -- -- -- -- R[5] -- -- -- -- R[4] -- -- -- -- R[3] -- -- -- -- R[2] -- -- -- R[5] R[1] -- -- -- R[4] R[0] -- -- R[4] R[3] G[7] -- -- R[3] R[2] G[6] -- -- R21] R[1] G[5] -- -- R[1] R[0] -- -- -- -- -- R[2] R[1] R[0] G[2] G[1] G[0] B[1] B[0] LCD_RESET LCD_BUSY (or optional LCD_VSYNC) R[0] G[5] G[4] G[3] G[3] G[2] G[1] G[0] B[4] B[3] B[2] B[1] B[0] LCD_RESET LCD_BUSY (or optional LCD_VSYNC) G[5] G[4] G[3] G[2] G[2] G[1] G[0] B[5] B[4] B[3] B[2] B[1] B[0] LCD_RESET LCD_BUSY (or optional LCD_VSYNC) G[4] G[3] G[2] G[1] G[0] G[0] B[7] B[6] B[5] B[4] B[3] B[2] B[1] B[0] LCD_RESET LCD_BUSY (or optional LCD_VSYNC) -- -- -- -- -- -- Y/C[7] Y/C[6] Y/C[5] Y/C[4] Y/C[3] Y/C[2] Y/C[1] Y/C[0] -- -- i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 91 Electrical characteristics 4.10.12 FlexSPI (Quad SPI/Octal SPI) timing parameters The FlexSPI interface can work in SDR or DDR modes. It can operate up to 60 MHz at 3.3 V, 166 MHz at 1.8 V SDR mode or 200 MHz at 1.8 V DDR mode. It supports single-ended and differential DQS signaling. FlexSPI supports the following clocking scheme for a read data path: · Dummy read strobe generated by FlexSPI controller and looped back internally (FlexSPIn_MCR0[RXCLKSRC] = 0x0) · Dummy read strobe generated by FlexSPI controller and looped back through the DQS pad (FlexSPIn_MCR0[RXCLKSRC] = 0x1). It means the I/O cannot be used for another feature. · Read strobe provided by memory device and input from DQS pad (FlexSPIn_MCR0[RXCLKSRC] = 0x3) 4.10.12.1 SDR mode 4.10.12.1.1 SDR mode timing diagrams The following write timing diagram is valid for any FlexSPIn_MCR0[RXCLKSRC] value. Figure 42. FlexSPI write timing diagram (SDR mode) The following read timing diagram is valid for FlexSPIn_MCR0[RXCLKSRC] = 0x0 or 0x1. Figure 43. FlexSPI read timing diagram (SDR mode) i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 92 NXP Semiconductors Electrical characteristics The following read timing diagram is valid for FlexSPIn_MCR0[RXCLKSRC] = 0x3. Figure 44. FlexSPI read with DQS timing diagram (SDR mode) 4.10.12.1.2 SDR mode timing parameter tables Table 95. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x0 (SDR mode) ID Parameter -- QSPIx[A/B]_SCLK Cycle frequency t1 QSPIx[A/B]_SCLK High or Low Time t2 QSPIx[A/B]_SSy_B pulse width t3 QSPIx[A/B]_SSy_B Lead Time1 t4 QSPIx[A/B]_SSy_B Lag Time1 t5 QSPIx[A/B]_DATAy output Delay t6 QSPIx[A/B]_DATAy Setup Time t7 QSPIx[A/B]_DATAy Hold Time 1 Timing is controlled from FLSHxCR1 register (x=A1, A2, B1, or B2). Min Max -- 60 7.5 -- 1 -- TCSS+0.5 -- TCSH -- -- 1 6 -- 0 -- Unit MHz ns SCLK SCLK SCLK ns ns ns Table 96. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x1 (SDR mode) ID Parameter -- QSPIx[A/B]_SCLK Cycle frequency t1 QSPIx[A/B]_SCLK High or Low Time t2 QSPIx[A/B]_SSy_B pulse width t3 QSPIx[A/B]_SSy_B Lead Time1 t4 QSPIx[A/B]_SSy_B Lag Time1 t5 QSPIx[A/B]_DATAy output Delay t6 QSPIx[A/B]_DATAy Setup Time t7 QSPIx[A/B]_DATAy Hold Time Min Max -- 166 2.7 -- 1 -- TCSS+0.5 -- TCSH -- -- 1 1 -- 2 -- Unit MHz ns SCLK SCLK SCLK ns ns ns i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 93 Electrical characteristics 1 Timing is controlled from FLSHxCR1 register (x=A1, A2, B1, or B2). Table 97. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x3 (SDR mode) ID Parameter -- QSPIx[A/B]_DQS Cycle frequency t1 QSPIx[A/B]_SCLK High or Low Time t2 QSPIx[A/B]_SSy_B pulse width1 t3 QSPIx[A/B]_SSy_B Lead Time2 t4 QSPIx[A/B]_SSy_B Lag Time2 t5 QSPIx[A/B]_DATAy output Delay t8 QSPIx[A/B]_DQS / QSPIx[A/B]_DATAy delta 1 Minimum is 2 SCLK cycles even if CSINTERVAL value is less than 2. 2 Timing is controlled from FLSHxCR1 register (x=A1, A2, B1, or B2). Min Max -- 200 2.25 -- CSINTERVAL -- TCSS+0.5 -- TCSH -- -- 1 -0.65 0.65 4.10.12.2 DDR mode 4.10.12.2.1 DDR mode timing diagrams Unit MHz ns SCLK SCLK SCLK ns ns Figure 45. FlexSPI write timing diagram (DDR mode) Figure 46. FlexSPI read timing diagram (DDR mode) i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 94 NXP Semiconductors Electrical characteristics QSPIx[A/B]_DQS QSPIx[A/B]_DATAy t9 t10 Figure 47. FlexSPI read with DQS timing diagram (DDR mode) Table 98. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x0 (DDR mode) ID Parameter -- QSPIx[A/B]_SCLK Cycle frequency t1 QSPIx[A/B]_SCLK High or Low Time t2 QSPIx[A/B]_SSy_B pulse width t3 QSPIx[A/B]_SSy_B Lead Time1 t4 QSPIx[A/B]_SSy_B Lag Time1 t5 QSPIx[A/B]_DATAy output valid time t6 QSPIx[A/B]_DATAy output hold time t7 QSPIx[A/B]_DATAy Setup Time t8 QSPIx[A/B]_DATAy Hold Time 1 Timing is controlled from FLSHxCR1 register (x=A1, A2, B1, or B2). Min Max -- 30 15 -- 1 -- (TCSS+0.5)/2 -- TCSH/2 -- 6.5 -- 6.5 -- 6 -- 0 -- Unit MHz ns SCLK SCLK SCLK ns ns ns ns Table 99. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x1 (DDR mode) ID Parameter -- QSPIx[A/B]_SCLK Cycle frequency t1 QSPIx[A/B]_SCLK High or Low Time t2 QSPIx[A/B]_SSy_B pulse width t3 QSPIx[A/B]_SSy_B Lead Time1 t4 QSPIx[A/B]_SSy_B Lag Time1 t5 QSPIx[A/B]_DATAy output valid time t6 QSPIx[A/B]_DATAy output hold time t7 QSPIx[A/B]_DATAy Setup Time t8 QSPIx[A/B]_DATAy Hold Time 1 Timing is controlled from FLSHxCR1 register (x=A1, A2, B1, or B2). Min Max -- 83 5.4 -- 1 -- (TCSS+0.5)/2 -- TCSH/2 -- 2 -- 2 -- 1 -- 1 -- i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors Unit MHz ns SCLK SCLK SCLK ns ns ns ns 95 Electrical characteristics Table 100. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x3 (DDR mode) ID Parameter -- QSPIx[A/B]_SCLK Cycle frequency t1 QSPIx[A/B]_SCLK High or Low Time t2 QSPIx[A/B]_SSy_B pulse width t3 QSPIx[A/B]_SSy_B Lead Time1 t4 QSPIx[A/B]_SSy_B Lag Time1 t5 QSPIx[A/B]_DATAy output valid time t6 QSPIx[A/B]_DATAy output hold time t9 QSPIx[A/B]_DATAy Setup Skew t10 QSPIx[A/B]_DATAy Hold Skew 1 Timing is controlled from FLSHxCR1 register (x=A1, A2, B1, or B2). Min -- 2.25 1 (TCSS+0.5)/2 TCSH/2 0.65 0.65 -- -- Max 200 -- -- -- -- -- -- 0.65 0.65 Unit MHz ns SCLK SCLK SCLK ns ns ns ns 4.10.13 Secure JTAG controller (SJC) 4.10.13.1 Internal pull-up/pull-down configuration The following table describes the default configuration of internal pull-ups and pull-downs of the JTAG interface. External pull-ups and pull-downs are needed when this interface is routed to a connector. Table 101. JTAG default configuration for internal pull-up/pull-down Ball name Internal pull setting1 Typical pull value Unit JTAG_TMS JTAG_TCK JTAG_TDI TEST_MODE_SELECT 1 PU = pull-up; PD = pull-down PU 50 K PD PU PD i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 96 NXP Semiconductors Electrical characteristics 4.10.13.2 JTAG timing parameters Figure 48 depicts the SJC test clock input timing. Figure 49 depicts the SJC boundary scan timing. Figure 50 depicts the SJC test access port. Signal parameters are listed in Table 102. JTAG_TCK (Input) VIH SJ3 SJ2 VM VIL SJ1 SJ2 VM SJ3 Figure 48. Test Clock Input Timing Diagram JTAG_TCK (Input) Data Inputs Data Outputs Data Outputs Data Outputs VIL SJ6 SJ7 VIH SJ4 SJ5 Input Data Valid Output Data Valid SJ6 Output Data Valid Figure 49. Boundary system (JTAG) timing diagram i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 97 Electrical characteristics JTAG_TCK (Input) VIL JTAG_TDI JTAG_TMS (Input) JTAG_TDO (Output) JTAG_TDO (Output) JTAG_TDO (Output) SJ10 SJ11 SJ10 VIH SJ8 SJ9 Input Data Valid Output Data Valid Output Data Valid Figure 50. Test Access Port Timing Diagram Table 102. JTAG Timing ID Parameter1,2 SJ0 JTAG_TCK frequency of operation 1/(3xTDC)1 SJ1 JTAG_TCK cycle time in crystal mode SJ2 JTAG_TCK clock pulse width measured at VM2 SJ3 JTAG_TCK rise and fall times SJ4 Boundary scan input data set-up time SJ5 Boundary scan input data hold time SJ6 JTAG_TCK low to output data valid SJ7 JTAG_TCK low to output high impedance SJ8 JTAG_TMS, JTAG_TDI data set-up time SJ9 JTAG_TMS, JTAG_TDI data hold time SJ10 JTAG_TCK low to JTAG_TDO data valid SJ11 JTAG_TCK low to JTAG_TDO high impedance 1 TDC = target frequency of SJC 2 VM = mid-point voltage All Frequencies Min Max 0.001 22 45 -- 22.5 -- -- 3 5 -- 24 -- -- 40 -- 40 5 -- 25 -- -- 44 -- 44 Unit MHz ns ns ns ns ns ns ns ns ns ns ns i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 98 NXP Semiconductors Electrical characteristics 4.10.14 SPDIF Timing Parameters The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal. Table 103, Figure 51, and Figure 52 show SPDIF timing parameters for the Sony/Philips Digital Interconnect Format (SPDIF), including the timing of the modulating Rx clock (SPDIF_SR_CLK) for SPDIF in Rx mode and the timing of the modulating Tx clock (SPDIF_ST_CLK) for SPDIF in Tx mode. Table 103. SPDIF Timing Parameters Parameter SPDIF_IN Skew: asynchronous inputs, no specs apply SPDIF_OUT output (Load = 50pf) · Skew · Transition rising · Transition falling SPDIF_OUT output (Load = 30pf) · Skew · Transition rising · Transition falling Modulating Rx clock (SPDIF_SR_CLK) period SPDIF_SR_CLK high period SPDIF_SR_CLK low period Modulating Tx clock (SPDIF_ST_CLK) period SPDIF_ST_CLK high period SPDIF_ST_CLK low period Timing Parameter Range Symbol Unit Min Max -- -- 0.7 ns -- -- -- -- -- -- 1.5 ns 24.2 31.3 -- -- -- srckp srckph srckpl stclkp stclkph stclkpl -- -- -- 40.0 16.0 16.0 40.0 16.0 16.0 1.5 ns 13.6 18.0 -- ns -- ns -- ns -- ns -- ns -- ns SPDIF_SR_CLK (Output) srckpl VM srckp srckph VM Figure 51. SPDIF_SR_CLK Timing Diagram SPDIF_ST_CLK (Input) stclkpl VM stclkp stclkph VM Figure 52. SPDIF_ST_CLK Timing Diagram i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 99 Electrical characteristics 4.10.15 UART I/O configuration and timing parameters 4.10.15.0.1 UART Transmitter The following figure depicts the transmit timing of UART in the RS-232 serial mode, with 8 data bit/1 stop bit format. Table 104 lists the UART RS-232 serial mode transmit timing characteristics. UARTx_TX_DATA (output) UA1 Start Bit Bit 0 UA1 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 POSSIBLE PARITY BIT Par Bit STOP BIT UA1 UA1 Figure 53. UART RS-232 Serial Mode Transmit Timing Diagram NEXT START BIT Table 104. UART RS-232 Serial Mode Transmit Timing Parameters ID Parameter Symbol Min Max Unit UA1 Transmit Bit Time tTbit 1/Fbaud_rate1 Tref_clk2 1/Fbaud_rate + Tref_clk -- 1 Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (LPUART_clk frequency)/(SBR[12:0] × (OSR+1)). 2 Tref_clk: The period of UART reference clock ref_clk (LPUART_clk after SBR divider). 4.10.15.0.2 UART Receiver The following figure depicts the RS-232 serial mode receive timing with 8 data bit/1 stop bit format. Table 105 lists serial mode receive timing characteristics. UARTx_RX_DATA (input) UA2 UA2 POSSIBLE PARITY BIT Start Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Par Bit STOP BIT UA2 UA2 Figure 54. UART RS-232 Serial Mode Receive Timing Diagram NEXT START BIT Table 105. RS-232 Serial Mode Receive Timing Parameters ID Parameter Symbol Min Max Unit UA2 Receive Bit Time1 tRbit 1/Fbaud_rate2 1/(16 × Fbaud_rate) 1/Fbaud_rate + -- 1/(16 × Fbaud_rate) 1 The UART receiver can tolerate 1/((OSR+1) × Fbaud_rate) tolerance in each bit, but accumulation tolerance in one frame must not exceed 3/((OSR+1) × Fbaud_rate). 2 Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (LPUART_clk frequency)/(SBR[12:0] × (OSR+1)). i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 100 NXP Semiconductors Electrical characteristics 4.10.15.0.3 UART IrDA Mode Timing The following subsections give the UART transmit and receive timings in IrDA mode. UART IrDA Mode Transmitter The following figure depicts the UART IrDA mode transmit timing, with 8 data bit/1 stop bit format. Table 106 lists the transmit timing characteristics. UA3 UA3 UA4 UA3 UA3 UARTx_TX_DATA (output) Start Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Figure 55. UART IrDA Mode Transmit Timing Diagram POSSIBLE PARITY BIT STOP BIT Table 106. IrDA Mode Transmit Timing Parameters ID Parameter Symbol Min Max Unit UA3 Transmit Bit Time in IrDA mode tTIRbit 1/Fbaud_rate1 Tref_clk2 1/Fbaud_rate + Tref_clk -- UA4 Transmit IR Pulse Duration tTIRpulse (TNP+1)/(OSR+1) × (1/Fbaud_rat (TNP+1)/(OSR+1) × (1/Fbaud_rat -- e) Tref_clk e) + Tref_clk 1 Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (LPUART_clk frequency)/(SBR[12:0] × (OSR+1)). 2 Tref_clk: The period of UART reference clock ref_clk (LPUART_clk after SBR divider). UART IrDA Mode Receiver The following figure depicts the UART IrDA mode receive timing, with 8 data bit/1 stop bit format. Table 107 lists the receive timing characteristics. UA5 UA5 UA6 UA5 UA5 UARTx_RX_DATA (input) Start Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Figure 56. UART IrDA Mode Receive Timing Diagram POSSIBLE PARITY BIT STOP BIT Table 107. IrDA Mode Receive Timing Parameters ID Parameter Symbol Min Max Unit UA5 Receive Bit Time1 in IrDA mode tRIRbit 1/Fbaud_rate2 1/(16 × Fbaud_rate) 1/Fbaud_rate + -- 1/(16 × Fbaud_rate) UA6 Receive IR Pulse Duration tRIRpulse 1.41 s (5/16) × (1/Fbaud_rate) -- 1 The UART receiver can tolerate 1/((OSR+1) × Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not exceed 3/((OSR+1) × Fbaud_rate). i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 101 Electrical characteristics 2 Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (LPUART_clk frequency)/(SBR[12:0] × (OSR+1)). 4.10.16 USB 2.0 PHY Parameters 4.10.16.1 USB 2.0 PHY Transmitter specifications This section describes the transmitter specifications for USB2.0 PHY. 4.10.16.1.1 USB 2.0 PHY full-speed/low-speed transmitter specifications The following table lists the full-speed/low-speed (FS/LS) transmitter specifications for USB2.0 PHY. Table 108. USB 2.0 PHY FS/LS transmitter specifications Symbol Description VOL Output Voltage Low VOH Output Voltage High (Driven) VOSE1 Single Ended One (SE1) VCRS Output Signal Cross Over Voltage TFR Driver Rise Time - FS TLR Driver Rise Time - LS TFF Driver Fall Time - FS TLF Driver Fall Time - LS TFRFM Differential Rise and Fall Time Matching - FS TLRFM Differential Rise and Fall Time Matching - LS ZHSDRV Driver Output Resistance (Also serves as HS Termination) TDJ1 Source Jitter (Next Transition) - FS TDJ2 Source Jitter (Paired Transition) - FS TFDEOP Source Jitter (Differential to SE0 transition) - FS TFEOPT Source SE0 interval of EOP - FS TDDJ1 Source Jitter in downstream direction (Next Transition) - LS TDDJ2 Source Jitter in downstream direction (Paired Transition) - LS TUDJ1 Source Jitter in upstream direction (Next Transition) - LS TUDJ2 Source Jitter in upstream direction (Paired Transition) - LS TLDEOP Source Jitter in upstream direction (Differential to SE0 transition) - LS TLEOPT Source SE0 interval of EOP - LS Min Typ Max Units 0 -- 0.3 V 2.8 -- 3.6 V 0.8 -- -- V 1.3 -- 2.0 V 4-- 20 ns 75 -- 300 ns 4-- 20 ns 75 -- 300 ns 90 -- 111.11 % 80 -- 125 % 40.5 -- 49.5 -3.5 -- 3.5 ns -4 -- 4 ns -2 -- 5 ns 160 -- 175 ns -25 -- 25 ns -14 -- 14 ns -95 -- 95 ns -150 -- 150 ns -40 -- 100 ns 1.25 -- 1.5 s i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 102 NXP Semiconductors Electrical characteristics 4.10.16.2 USB 2.0 PHY high-speed transmitter specifications The following table lists the high-speed (HS) transmitter specifications for USB 2.0 PHY. Table 109. USB 2.0 PHY HS transmitter specifications Symbol/Parameter HSOI VHSTERM VHSOL VCHIRPJ VCHIRPK ZHSDRV THSR THSF HS Eye Opening: Template 1 HS Eye Opening: Template 2 HS Jitter: Template 1 HS Jitter: Template 2 Description Min Typ Max Units High Speed Idle Level -10 -- 10 mV Termination Voltage in High Speed -10 -- 10 mV High Speed Data Signaling Low -10 -- 10 mV Chirp J (Differential Voltage) 700 -- 1100 mV Chirp K (Differential Voltage) -900 -- -500 mV Driver Output Resistance 40.5 -- 49.5 Rise Time (10% to 90%) 100 -- -- ps Fall Time (10% to 90%) 100 -- -- ps Differential eye opening at 37.5% US and 62.5% UI for a -300 -- 300 mV hub measured at TP2 and for a device without a captive cable measured at TP3. Differential eye opening at 37.5% US and 62.5% UI for a -175 -- 175 mV device with a captive cable measured at TP2. Peak-Peak Jitter at Zero crossing for a hub measured at TP2 and for a device without captive cable measured at TP3. ---- 15 %UI -- -- 312.5 ps Peak-Peak Jitter at Zero crossing for a device with captive -- cable measured at TP2. -- -- 25 %UI -- 520.83 ps 4.10.16.3 USB 2.0 PHY receiver specifications This section describes the receiver specifications implemented in USB 2.0 PHY. 4.10.16.3.1 USB 2.0 PHY full-speed/low-speed (FS/LS) receiver specifications Table 110. USB 2.0 PHY FS/LS receiver specifications Symbol VIH VIHZ VIL VTH VCM TJR1 Description Input Voltage Level - High (Driven) Input Voltage Level - High (Floating) Input Voltage Level - Low Switching Threshold Common Mode Range Receiver Jitter Budget (Next Transition) - FS Min Typ Max Units 2 ---- V 2.7 -- 3.6 V -- -- 0.8 V 0.8 -- 2.0 V 0.8 -- 2.5 V -18.5 -- 18.5 ns i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 103 Electrical characteristics Table 110. USB 2.0 PHY FS/LS receiver specifications (continued) Symbol TJR2 TFEOPR TUJR1 TUJR2 TDJR1 TDJR2 TLEOPR Description Receiver Jitter Budget (Paired Transition) - FS Receiver EOP Interval of EOP - FS US Port Differential Receiver Jitter (Next Transition) - LS US Port Differential Receiver Jitter (Paired Transition) - LS DS Port Differential Receiver Jitter (Next Transition) - LS DS Port Differential Receiver Jitter (Paired Transition) - LS Receiver EOP Interval of EOP - LS Min -9 82 -152 -200 -75 -45 670 Typ Max -- 9 ---- -- 152 -- 200 -- 75 -- 45 ---- Units ns ns ns ns ns ns ns 4.10.16.3.2 USB 2.0 PHY high-speed receiver specifications The following table lists the high-speed (HS) receiver specifications for USB 2.0 PHY. Table 111. USB 2.0 PHY HS receiver specifications Symbol/Parameter Description Min Typ Max Units VHSCM HS RX input common mode voltage range. -50 -- 500 mV ZHSDRV HS RX input termination (Same as Driver output resistance). 40.5 -- 49.5 HSRX Jitter: Template 3 HS RX Peak-Peak Jitter specification at differential zero crossing for a -- device with captive cable when signal applied at TP2. -- -- 20 %UI -- 416.66 ps HSRX Jitter: Template 4 HS RX Peak-Peak Jitter specification at differential zero crossing for a -- -- 30 %UI device without captive cable at TP3 and for a hub at TP2. -- -- 625 ps HSRX Input Eye Opening: HS RX differential sensitivity specification at 40% and 60% UI for a -275 -- 275 mV Template 3 device with captive cable when signal is applied at TP2. HSRX Input Eye Opening: HS RX differential sensitivity specification at 35% and 65% UI for a -150 -- 150 mV Template 4 device without captive cable when signal is applied at TP3 and for a hub when a signal is applied at TP2. 4.10.16.3.3 USB 2.0 PHY high-speed envelope detector specifications The following table lists the high-speed (HS) Envelope Detector Specifications of USB 2.0 PHY. Table 112. USB 2.0 PHY HS envelope detector specifications Symbol VHSSQ VHSDSC Description HS Squelch Detection threshold (differential signal amplitude) HS Disconnect Detection threshold (differential signal amplitude) Min Typ Max Units 100 -- 150 mV 525 -- 625 mV i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 104 NXP Semiconductors Electrical characteristics 4.10.16.4 USB 2.0 PHY full-speed/high-speed terminations specification The following table lists the full-speed/low-speed (FS/LS) Terminations Specification of USB 2.0 PHY. Table 113. USB 2.0 PHY FS/LS terminations specification Symbol RPU RPD VTERM Description Bus Pull-Up resistor on US Port in IDLE State Bus Pull-Up resistor on US Port in ACTIVE State Bus Pull-Down resistor on DS Port Termination Voltage for US Port Pull-Up (RPU) Min Typ 900 -- 1425 -- 14.25 -- 3.0 -- Max 1575 3090 24.8 3.6 Units K V 4.10.16.5 Voltage threshold specification The following table lists the OTG Comparator Specifications of USB2.0 PHY. Table 114. USB 2.0 PHY OTG comparator specifications Symbol sessvld vbusvalid Description B-Device Session Valid threshold VBUS Valid threshold Min Typ Max 0.8 -- 4.0 4.4 -- 4.75 4.10.17 USB 3.0 PHY parameters The following content is from the USB 3.0 PHY specifications. 4.10.17.1 USB 3.0 PHY external component Units V V Table 115. USB 3.0 PHY external component specifications Name Min Typ Max Units Descriptions rext 497.5 500 502.5 There needs to be an external resistor component connected at rext ball while the internal resistor or current is getting calibrated. Package routing from rext ball to its respective bump should not contribute more than 0.05 . i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 105 Electrical characteristics 4.10.17.2 USB 3.0 PHY transmitter module Table 116. USB 3.0 PHY transmitter module electrical specifications Symbol Description Min Typ Max Unit Voltage/current parameters VTX-DIFFp VTX-DIFFp-p VTX-DIFFp-p-LOW1 ITX-SHORT RLTX-DIFF RLTX-CM ZTX-DIFF-DC UI TTX-MAX-JITTER TTX-RJ-PLL-sigma LTLAT-10 Programmable output voltage 50 -- 500 mV swing (single-ended) Programmable differential 100 -- 1000 mV peak-to-peak output voltage Low power differential p-p TX 400 -- 1200 mV voltage swing Transmit lane short-circuit current ---- 100 mA Transmitter differential return loss ---- 0 < -20dB < 100Mhz Db 100Mhz < -18dB < 300Mhz 300Mhz < -16dB < 600Mhz 600Mhz < -10dB < 2500Mhz 2500Mhz < -9dB < 4875Mhz 4875Mhz < -8dB < 11200Mhz 11200Mhz < -5dB < 16800Mhz and -3dB beyond that Transmitter common mode return ---- 50Hz < -8dB < 15000Mhz dB loss DC differential TX impedance 80 100 120 Unit Interval 199.94 -- 200.06 ps Transmitter total jitter ---- 0.4 UI (peak-to-peak) (Tj) After application of TX jitter transfer -- -- 2.42 ps function Transmitter data latency ---- 210 UI Voltage parameters VTX-CM-DC-ACTIVE-IDLE-DELTA Absolute Delta of DC Common 0-- 100 mV Mode Voltage during L0 and Electrical Idle. VTX-IDLE-DIFF-AC-p Electrical Idle Differential Peak 0-- 20 mV Output Voltage VTX-CM-DC-LINE-DELTA Absolute Delta of DC Common 0-- 25 mV Mode Voltage between D+ and D- VTX-RCV-DETECT The amount of voltage change 0-- 600 mV allowed during Receiver Detection TTX-IDLE-SET-TO-IDLE Maximum time to transition to a ---- 8 ns valid Electrical Idle after sending an EIOS i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 106 NXP Semiconductors Electrical characteristics Table 116. USB 3.0 PHY transmitter module electrical specifications (continued) Symbol TTX-IDLE-TO-DIFF-DATA VTX-CM-AC-PP TEIExit ftol Description Min Typ Maximum time to transition to valid -- -- diff signaling after leaving Electrical Idle Tx AC peak-peak common mode voltage (5.0 GT/s) 20 -- Time to exit Electrical Idle (L0s) state and to enter L0 ---- Tx signal characteristics TX Frequency Long Term Accuracy -300 -- fSSC Spread-Spectrum Modulation Frequency t20-80TX TX Rise/Fall Time tskewTX TX Differential Skew 1 For USB 3.0, no EQ is required 30 -- 0.2 -- ---- Max 8 150 5 300 33 0.41 20 Unit ns mVpp Txsysclk ppm of Fbaud kHz UI ps 4.10.17.3 USB 3.0 PHY receiver module Table 117. USB 3.0 PHY receiver module electrical specifications Symbol Description Min Typ Max Unit Comments Voltage Parameters VRX-DIFF(p-p) Differential input voltage 100 -- 1200 mV -- (peak-to-peak) (that is, receiver eye voltage opening) VRX-IDLE-DET-DIFF(p-p Differential input threshold voltage 100 -- 300 mV USB3 LFPS ) (peak-to-peak) to detect idle (LFPS) Vcm, acRX VRX-CM-AC RX AC Common Mode Voltage Receiver common-mode voltage for AC coupling -- -- 100 mVp-p Simulated at 250 MHz -- 0 150 mV -- ZRX-DIFF-DC RLRX-DIFF Differential input impedance (DC) 80 100 120 Receiver differential return loss Same as -- -- TX RL W 100 ± 10% dB -- Jitter Parameters TRX-MAX-JITTER Receiver total jitter tolerance 0 -- 0.66 UI Incoming Jitter: USB3 = 0.43UI DJ + 0.23UI RJ USB3 numbers are with REFC-TLE i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 107 Electrical characteristics Table 118. PLL module electrical specifications Parameter Symbol Description Min Typ Max Units Input Reference Clock REF CLK Frequency REF CLK Duty Cycle REF CLK Frequency REF CLK RJ Tolerance REF CLK Duty Cycle Divided Reference Frequency REF CLK -- REF CLK -- -- -- -- 19.2 19.2/24/25/26/38.4 38.4 MHz -- 47 -- 53 MHz -- 40 40/48/50/52/100 100 MHz Integrated jitter from 10 kHz to 16 MHz -- after applying appropriate PLL ref clock transfer function and the protocol JTF -- 37 -- 0.5 ps -- 63 % -- 19.2 -- 38.4 MHz Dividers Input division IPDIV<7:0> -- Feedback division pll_fbdiv_high<9:0> -- pll_fbdiv_low<9:0> -- Feedback fractional -- -- division range Number of fractional bits -- This includes one bit for sign 1 -- 255 Counts 2 -- 1025 Counts 2 -- 1025 Counts >-2 -- <2 Counts -- 27 -- Bits VCO Clock frequency -- Output full rate clocks -- 5000 -- MHz VCO frequency -- VCO oscillation frequency -- 5000 -- MHz Output clock -- This includes SSC deviation frequency tolerance -5300 -- 300 ppm SSC modulation rate -- As applicable for USB3.0 30 -- 33 kHz Output clock RJ sigma for TX -- After application of TX jitter transfer -- function -- 2.42 ps Output clock RJ sigma for RX -- After application of RX jitter transfer -- function -- 1.40 ps i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 108 NXP Semiconductors Electrical characteristics 4.11 Analog-to-digital converter (ADC) The following table shows the ADC electrical specifications for VREFH=VDD_ADC_1P8. Table 119. ADC electrical specifications (VREFH=VDD_ADC_1P8) Symbol Description Min Typ1 Max Unit Notes VADIN CADIN RADIN RAS fADCK Csample Ccompare Cconversion DNL INL ENOB Input Voltage Input capacitance Input Resistance Analog Source Resistance ADC Conversion Clock Frequency Sample cycles Fixed compare cycles Conversion cycles Differential Non-Linearity Integral Non-Linearity Effective Number of Bits VREFL -- VREFH V -- -- 4.5 -- pF -- -- 500 -- -- -- -- 5 k 2 -- 24 -- MHz -- 3.5 -- 131.5 -- 3 -- 17.5 -- cycles -- Cconversion = Csample + Ccompare cycles -- -- ± 0.6 -0.5 to +1.1 LSB 4 -- ± 0.9 ±1.1 LSB 4 -- -- -- -- 5,6,7 Avg = 1 10.1 10.4 -- Bits Avg = 2 10.5 10.7 -- Bits Avg = 16 11.1 11.3 -- Bits SINAD Signal to Noise plus Distortion SINAD=6.02 x ENOB + 1.76 dB -- EG EO IVDDA18 Gain error Offset error Supply Current -- -0.29 -- %FSV 8 -- 0.01 -- %FSV 9 -- 480 -- A 10 Iin,ext,leak External Channel Leakage Current -- 30 500 nA -- EIL Input leakage error RAS * Iin mV -- 1 Typical values assume VDD_ADC_1P8 = 1.8 V, Temp = 25 °C, fACLK = Max, unless otherwise stated. Typical values are for reference only. All values, including Min and Max, are derived from lab characterization and are not tested in production. 2 This resistance is external to the input pad. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 15 analog source resistance. The RAS/CAS (analog source capacitance) time constant should be kept to < 1 ns. 3 See Figure 57. 4 ADC conversion clock at max frequency and using linear histogram. 5 Input data used for test was 1 kHz sine wave. 6 Measured at VREFH = 1.8 V and pwrsel = 2. 7 ENOB can be lower than shown, if an ADC channel corrupts other ADC channels through capacitive coupling. This coupling may be dominated by board parasitics. Care must be taken not to corrupt the desired channel being measured. This coupling becomes worse at higher analog frequencies and with switching waveforms due to the harmonic content. 8 Error measured at fullscale at 1.8 V. 9 Error measured at zero scale at 0 V. i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 109 Electrical characteristics 10 Power Configuration Select, PWRSEL, is set to 10 binary. The following table shows the ADC electrical specifications for 1VVREFH<VDD_ADC_1P8. Table 120. ADC electrical specifications (1VVREFH<VDD_ADC_1P8) Symbol Description Min Typ1 Max Unit Notes VADIN CADIN RADIN RAS fADCK Csample Ccompare Cconversion DNL INL ENOB Input Voltage Input capacitance Input Resistance Analog Source Resistance ADC Conversion Clock Frequency Sample cycles Fixed compare cycles Conversion cycles Differential Non-Linearity Integral Non-Linearity Effective Number of Bits VREFL -- VREFH V -- -- 4.5 -- pF -- -- 500 -- -- -- -- 5 k 2 -- 24 -- MHz -- 3.5 -- 131.5 -- 3 -- 17.5 -- cycles -- Cconversion = Csample + Ccompare cycles -- -- ± 0.6 -0.5 to +1.1 LSB 4 -- ± 0.9 ±1.1 LSB 4 -- -- -- -- 5,6,7 Avg = 1 9.5 9.7 -- Bits Avg = 2 9.9 10.1 -- Bits Avg = 16 10.8 11 -- Bits SINAD Signal to Noise plus Distortion SINAD=6.02 x ENOB + 1.76 dB -- EG EO IVDDA18 Gain error Offset error Supply Current -- 0.29 -- 0.01 -- 480 -- %FSV 8 -- %FSV 9 -- A 10 Iin,ext,leak External Channel Leakage Current -- 30 500 nA -- EIL Input leakage error RAS * Iin mV -- 1 Typical values assume VDD_ANA_1P8 = 1.8 V, Temp = 25 °C, fACLK = Max, unless otherwise stated. Typical values are for reference only. All values, including Min and Max, are derived from lab characterization and are not tested in production. 2 This resistance is external to the input pad. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 15 analog source resistance. The RAS/CAS (analog source capacitance) time constant should be kept to < 1 ns. 3 See Figure 57. 4 ADC conversion clock at max frequency and using linear histogram. 5 Input data used for test was 1 kHz sine wave. 6 Measured at VREFH = 1 V and pwrsel = 2. 7 ENOB can be lower than shown, if an ADC channel corrupts other ADC channels through capacitive coupling. This coupling may be dominated by board parasitics. Care must be taken not to corrupt the desired channel being measured. This coupling becomes worse at higher analog frequencies and with switching waveforms due to the harmonic content. 8 Error measured at fullscale at 1.0 V. i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 110 NXP Semiconductors 9 Error measured at zero scale at 0 V. 10 Power Configuration Select, PWRSEL, is set to 10 binary. The following figure shows a plot of the ADC sample time versus RAS. Electrical characteristics Figure 57. Sample time vs. RAS i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 111 Boot mode configuration 5 Boot mode configuration This section provides information on boot mode configuration pins allocation and boot devices interfaces allocation. 5.1 Boot mode configuration pins The following table provides boot options, functionality, fuse values, and associated pins. Several input pins are also sampled at reset and can be used to override fuse values, depending on the value of FORCE_BOOT_FROM_FUSE. After it is blown, the Boot mode pin is ignored by ROM; ROM receives 'boot mode' from the BT_MODE_FUSES fuse. The boot option pins are in effect when BT_FUSE_SEL fuse is `0' (cleared, which is the case for an unblown fuse). For detailed boot mode options configured by the Boot mode pins, see the "System Boot, Fusemap, and eFuse" chapter of the device reference manual for more details. Interface BOOT_MODE[0] BOOT_MODE[1] BOOT_MODE[2] BOOT_MODE[3] Table 121. Fuse and associated pins used for Boot IP Instance Input Input Input Input Allocated Pads During Boot SCU_BOOT_MODE0 SCU_BOOT_MODE1 SCU_BOOT_MODE2 SCU_BOOT_MODE3 Comment Boot mode selection 5.2 Boot devices interfaces allocation The following table lists the interfaces that can be used by the boot process in accordance with the specific Boot mode configuration. The table also describes the interface's specific modes and IOMUXC allocation, which are configured during boot when appropriate. Table 122. Interface allocation during boot Interface IP Instance Allocated Pads During Boot Comment eMMC SD USDHC0 EMMC0_CLK, EMMC0_CMD, EMMC0_DATA0, EMMC0_DATA1, EMMC0_DATA2, EMMC0_DATA3, EMMC0_DATA4, EMMC0_DATA5, EMMC0_DATA6, EMMC0_DATA7, EMMC0_RESET_B USDHC1 USDHC1_CD_B, USDHC1_CLK, USDHC1_CMD, USDHC1_CD_B is used by first (A0) silicon only. USDHC1_DATA0, USDHC1_DATA1, Second (B0) silicon uses USDHC1_DATA3 for USDHC1_DATA2, USDHC1_DATA3, CD (Card Detect). USDHC1_RESET_B, USDHC1_VSELECT i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 112 NXP Semiconductors Boot mode configuration Table 122. Interface allocation during boot (continued) Interface IP Instance Allocated Pads During Boot Comment NAND GPMI EMMC0_CLK, EMMC0_CMD, EMMC0_DATA0, EMMC0_DATA1, EMMC0_DATA2, EMMC0_DATA3, EMMC0_DATA4, EMMC0_DATA5, EMMC0_DATA6, EMMC0_DATA7, EMMC0_STROBE, EMMC0_RESET_B, USDHC1_CD_B, USDHC1_CMD, USDHC1_DATA0, USDHC1_DATA1, USDHC1_DATA2, USDHC1_DATA3, USDHC1_RESET_B, USDHC1_VSELECT, USDHC1_WP 8 bit boot from CS0 only, but will drive CS1 to high when booting if specified in fuse. Single-ended DQS: · USDHC1_CD_B Single-ended RE: · USDHC1_VSELECT Differential DQS: · _N use USDHC1_WP · _P use USDHC1_CD_B Differential RE: · _N use USDHC1_RESET_B · _P use USDHC1_VSELECT Quad SPI QSPI0 QSPI0A_DATA0, QSPI0A_DATA1, 4, dual-4, or 8 bit QSPI0A_DATA2, QSPI0A_DATA3, QSPI0A_DQS, QSPI0A_SCLK, QSPI0A_SS0_B, QSPI0A_SS1_B, QSPI0B_DATA0, QSPI0B_DATA1, QSPI0B_DATA2, QSPI0B_DATA3, QSPI0B_DQS, QSPI0B_SCLK, QSPI0B_SS0_B, QSPI0B_SS1_B USB USB-OTG1 USB_OTG1_DN, USB_OTG2_DN, USB_OTG1_DP, USB_OTG2_DP, USB_OTG1_ID, USB_OTG2_ID, USB_OTG1_VBUS, USB_OTG2_VBUS i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 113 Package information and contact assignments 6 Package information and contact assignments This section contains package information and contact assignments for the following package(s): · FCPBGA, 21 x 21 mm, 0.8 mm pitch 6.1 FCPBGA, 21 x 21 mm, 0.8 mm pitch This section includes the following information for the 21 x 21 mm, 0.8 mm pitch package: · Mechanical package drawing · Ball map · Contact assignments i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 114 NXP Semiconductors Package information and contact assignments 6.1.1 21 x 21 mm package case outline The following figure shows the top, bottom, and side views of the 21 x 21 mm package. Figure 58. 21 x 21 mm Package Top, Bottom, and Side Views i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 115 Package information and contact assignments The following notes pertain to the preceding figure, "21 x 21 mm Package Top, Bottom, and Side Views." Figure 59. Notes on 21 x 21 mm Package Top, Bottom, and Side Views i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 116 NXP Semiconductors Package information and contact assignments 6.1.2 21 x 21 mm, 0.8 mm pitch ball map The following page shows the 21 x 21 mm, 0.8 mm pitch ball map. i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 117 Package information and functional contact assignments for FCPBGA, 21 x 21 mm, 0.8 mm pitch 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 VSS_MAI DDR_DQ DDR_DQ PCIE0_T PCIE_CT PCIE0_R USB_SS3 VSS_MAI USB_SS3 EMMC0_ EMMC0_ USDHC1_ USDHC1_ ENET0_R ENET0_R VSS_MAI A N 31 28 X0_N RL0_WA X0_P _TX_N N _RX_P DATA1 DATA6 VSELECT DATA0 GMII_TX GMII_RX N KE_B _CTL D0 DDR_DQ DDR_DQ DDR_DQ1 VSS_MAI PCIE0_T PCIE0_R VSS_MAI USB_SS3 USB_SS3 VSS_MAI EMMC0_ USDHC1_ USDHC1_ ENET0_R ENET0_R ENET0_ ESAI0_T B 30 29 6 N X0_P X0_N N _TX_P _RX_N N DATA4 RESET_B DATA1 GMII_TX GMII_RX MDIO X1 D1 _CTL VSS_MAI C N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N USB_SS3 _TC3 VSS_MAI N VSS_MAI N EMMC0_ DATA0 VSS_MAI N USDHC1_ CMD VSS_MAI N ENET0_R GMII_RX D1 VSS_MAI N ESAI0_T X3_RX2 VSS_MAI N DDR_DQ DDR_DM DDR_DQ DDR_DQ1 PCIE_CT PCIE_RE USB_OT USB_OT USB_OT EMMC0_ EMMC0_ USDHC1_ USDHC1_ ENET0_R ENET0_ ESAI0_T SPDIF0_T D S3_P 2 S2_P 9 RL0_CLK FCLK100 G2_REXT G2_DN G1_DP CMD DATA7 WP DATA2 GMII_RX MDC X0 X REQ_B M_N C DDR_DM E 3 DDR_DQ S3_N DDR_DQ S2_N DDR_DQ1 8 DDR_DQ1 7 PCIE_RE FCLK100 M_P USB_SS3 _REXT VSS_MAI N USB_OT G2_DP USB_OT G1_DN EMMC0_ DATA2 USDHC1_ CD_B USDHC1_ DATA3 ENET0_R GMII_TX D2 VSS_MAI N ESAI0_S CKT VSS_MAI N SPDIF0_E XT_CLK VSS_MAI VSS_MAI VSS_MAI VSS_MAI VSS_MAI PCIE_RE USB_SS3 USB_OT VSS_MAI VSS_MAI EMMC0_ VSS_MAI ENET0_R ENET0_R ESAI0_FS ESAI0_T SPI3_SD F N N N N N F_QR _TC0 G2_ID N N STROBE N GMII_TX EFCLK_12 R X4_RX1 O D3 5M_25M DDR_DQ G 27 DDR_DQ 26 DDR_DQ 23 DDR_DQ 20 DDR_ZQ PCIE0_PH Y_PLL_R EF_RETU RN VDD_PCI E_1P8 USB_SS3 _TC2 USB_OT G1_ID EMMC0_ CLK EMMC0_ DATA5 USDHC1_ CLK ENET0_R GMII_TX D0 ENET0_R GMII_RX D2 ESAI0_FS T SPDIF0_ RX SPI3_SDI MCLK_IN 0 DDR_DQ DDR_DQ DDR_DQ DDR_DQ PCIE_CT PCIE_RE USB_SS3 USB_OT USB_OT EMMC0_ EMMC0_ ENET0_R ENET0_R ESAI0_S VSS_MAI UART1_T H 24 25 22 21 RL0_PER XT _TC1 G2_VBU G1_VBUS DATA3 RESET_B GMII_TX GMII_RX CKR N SPI3_SCK X ST_B S C D3 VSS_MAI J N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N ESAI0_T X5_RX0 SPI3_CS0 VSS_MAI N SAI0_TX C DDR_DC DDR_DC DDR_DC DDR_DC VSS_MAI VSS_MAI VSS_MAI VSS_MAI VSS_MAI VSS_MAI VSS_MAI VSS_MAI VSS_MAI ESAI0_T UART1_C SAI0_TX K F29 F27 F28 F25 N N N N N N N N N X2_RX3 SPI3_CS1 TS_B D DDR_DC L F18 DDR_DC F32 DDR_DC F31 DDR_DC F26 VSS_MAI N VDD_PCI E_DIG_1P 8_3P3 VDD_PCI E_LDO_1 P0_CAP VDD_US B_3P3 VDD_US B_OTG_1 P0 VDD_EM MC0_1P8 _3P3 VDD_US DHC1_VS ELECT_1P 8_3P3 VDD_EN ET0_VSE LECT_1P8 _2P5_3P 3 VDD_EN ET_MDIO _1P8_3P3 VSS_MAI N MCLK_O UT0 UART1_R X SAI0_TX FS SAI1_RX C VDD_US VDD_EM VSS_MAI VSS_MAI VSS_MAI VSS_MAI VSS_MAI VDD_DD VDD_AN B_SS3_L VDD_US MC0_VS VDD_US VDD_EN VSS_MAI MCLK_IN VSS_MAI SAI1_RX SAI0_RX M N N N N N R_VDDQ A0_1P8 DO_1P0_ B_1P8 ELECT_1P DHC1_1P8 ET0_1P8_ N 1 N D D CAP 8_3P3 _3P3 2P5_3P3 DDR_DC N F19 DDR_DC F17 DDR_CK1 _N DDR_DC F30 VDD_DD R_VDDQ VDD_DD R_VDDQ VSS_MAI N VDD_MA IN VSS_MAI N VDD_MA IN VSS_MAI N VDD_GP U VDD_ES AI_SPDIF _1P8_2P5 _3P3 VSS_MAI N UART1_R TS_B SPI2_SDI VSS_MAI N SAI1_RXF S DDR_DC DDR_DC DDR_CK1 DDR_DC VSS_MAI VDD_MA VSS_MAI VDD_MA VSS_MAI VDD_GP VDD_GP VDD_MA VSS_MAI SPI2_SD P F22 F20 _P F33 N IN N IN N U U IN N SPI2_CS0 SPI0_SCK O SPI0_SDI VSS_MAI R N VSS_MAI N VSS_MAI N VDD_DD R_VDDQ VSS_MAI N VDD_DD R_VDDQ VDD_MA IN VSS_MAI N VDD_MA IN VSS_MAI N VDD_GP U VSS_MAI N VDD_SPI _MCLK_ UART_1P 8_3P3 VSS_MAI N SPI2_SCK SPI0_SD O SPI0_CS0 SPI0_CS1 DDR_DC DDR_DC DDR_DC DDR_DC VSS_MAI VDD_DD VDD_MA VSS_MAI VDD_MA VSS_MAI VDD_GP VSS_MAI VSS_MAI VSS_MAI VSS_MAI VSS_MAI VSS_MAI T F07 F23 F24 F21 N R_VDDQ IN N IN N U N N N N N N DDR_DC U F03 DDR_DC F01 DDR_DC F05 DDR_DC F04 VSS_MAI N VDD_DD R_VDDQ VSS_MAI N VDD_MA IN VSS_MAI N VDD_MA IN VSS_MAI N VDD_GP U VDD_SPI _SAI_1P8 _3P3 VSS_MAI N ADC_VR EFH ADC_VR EFL ADC_IN1 ADC_IN0 VSS_MAI VSS_MAI VSS_MAI VSS_MAI VSS_MAI VDD_MA VSS_MAI VDD_MA VSS_MAI VDD_GP VSS_MAI VDD_MA VSS_MAI VDD_AD V N N N N N IN N IN N U N IN N C_1P8 ADC_IN3 ADC_IN2 ADC_IN5 DDR_DC W F00 DDR_DC F11 DDR_CK 0_P DDR_DC F16 VSS_MAI N VDD_DD R_VDDQ VDD_MA IN VSS_MAI N VDD_MA IN VSS_MAI N VDD_GP U VSS_MAI N VDD_AD C_DIG_1P 8 VSS_MAI N ADC_IN4 VSS_MAI N VSS_MAI N VSS_MAI N DDR_DC DDR_DC DDR_CK DDR_DC VSS_MAI VDD_DD VDD_MA VSS_MAI VDD_MA VSS_MAI VDD_MA VDD_CA VSS_MAI VSS_MAI VSS_MAI FLEXCAN FLEXCAN Y F14 F15 0_N F12 N R_VDDQ IN N IN N IN N_UART N N N 0_TX 0_RX _1P8_3P3 VSS_MAI AA N VSS_MAI N VSS_MAI N VSS_MAI N VDD_DD R_VDDQ VDD_DD R_VDDQ VSS_MAI N VDD_A35 VDD_A35 VDD_A35 VSS_MAI N VDD_MA IN VDD_MIP I_DSI_DI G_1P8_3 P3 VSS_MAI N UART0_T X FLEXCAN 2_TX FLEXCAN 1_RX FLEXCAN 1_TX DDR_DQ1 DDR_DC DDR_DC DDR_AT VSS_MAI VDD_MA VSS_MAI VSS_MAI VDD_AN VSS_MAI MIPI_DSI VSS_MAI UART0_ FLEXCAN AB 4 F08 F09 O N IN N VDD_A35 VDD_A35 VDD_A35 N A1_1P8 N 0_I2C0_S N RX 2_RX DA DDR_DQ1 AC 5 DDR_DQ1 2 DDR_DC F10 DDR_DT O0 VDD_DD R_PLL_1P 8 VDD_DD R_VDDQ VDD_MA IN VSS_MAI N VDD_MA IN VSS_MAI N VDD_MA IN VSS_MAI N VDD_SN VS_4P2 VSS_MAI N MIPI_DSI1 _I2C0_S DA MIPI_DSI 0_I2C0_S CL VSS_MAI N UART2_T X VSS_MAI VSS_MAI VSS_MAI DDR_VR VSS_MAI VDD_DD VDD_MA VDD_MIP VDD_MIP VSS_MAI VDD_MA VDD_TM VSS_MAI SCU_WD MIPI_DSI1 MIPI_DSI UART2_ AD N N N EF N R_VDDQ IN I_1P8 I_1P0 N IN PR_CSI_1 N OG_OUT _GPIO0_ 0_GPIO0 RX P8_3P3 00 _00 DDR_DQ AE S1_N DDR_DQ1 3 DDR_DQ 01 DDR_DT O1 VSS_MAI N VDD_DD R_VDDQ VDD_QS PI0B_1P8 _3P3 VDD_QS PI0A_1P8 _3P3 VDD_MIP I_1P8 VDD_MIP I_1P0 VDD_MIP I_CSI_DI G_1P8 VDD_CSI _1P8_3P3 VDD_SN VS_LDO_ 1P8_CAP VSS_MAI N TEST_M ODE_SEL ECT JTAG_TC K MIPI_DSI1 _I2C0_S CL MIPI_DSI 0_GPIO0 _01 DDR_DQ DDR_DM DDR_DQ DDR_DQ VSS_MAI VSS_MAI VSS_MAI VSS_MAI VSS_MAI VSS_MAI VSS_MAI VSS_MAI VSS_MAI SCU_GPI VSS_MAI JTAG_TD MIPI_DSI1 AF S1_P 1 00 03 N N N N N N N N N O0_00 N O _GPIO0_ 01 VSS_MAI AG N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N SCU_PMI C_STAN DBY POR_B VSS_MAI N JTAG_T MS DDR_DQ1 DDR_DQ1 DDR_DQ DDR_DQ QSPI0B_ QSPI0A_ VSS_MAI VSS_MAI VSS_MAI VSS_MAI VSS_MAI VSS_MAI VSS_MAI ON_OFF_ SCU_GPI PMIC_I2 JTAG_TD AH 0 1 S0_N 02 SS0_B DATA3 N N N N N N N BUTTON O0_01 C_SDA I DDR_DQ AJ 08 DDR_DQ 09 DDR_DQ S0_P DDR_DM 0 QSPI0B_ SS1_B QSPI0B_ DATA2 QSPI0A_ DATA2 MIPI_DSI 0_DATA3 _N MIPI_DSI 0_DATA1 _N MIPI_DSI 0_CLK_N MIPI_DSI 0_DATA0 _N MIPI_DSI 0_DATA2 _N CSI_D06 CSI_D03 SCU_BO OT_MOD E3 SCU_BO OT_MOD E0 PMIC_IN T_B PMIC_I2 C_SCL VSS_MAI VSS_MAI VSS_MAI VSS_MAI QSPI0B_ QSPI0A_ QSPI0A_ MIPI_DSI MIPI_DSI MIPI_DSI MIPI_DSI MIPI_DSI VSS_MAI SCU_BO ANA_TES AK N N N N DQS SS1_B DATA0 0_DATA3 0_DATA1 0_CLK_P 0_DATA0 0_DATA2 CSI_PCLK CSI_D00 N OT_MOD T_OUT_N _P _P _P _P E1 DDR_DQ AL 32 DDR_DQ 34 DDR_DQ 06 DDR_DQ 07 QSPI0B_ DATA1 QSPI0A_ DQS VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N CSI_VSY NC CSI_D01 SCU_BO OT_MOD E2 VSS_MAI N ANA_TES T_OUT_P DDR_DQ DDR_DQ DDR_DQ QSPI0B_ QSPI0B_ QSPI0A_ MIPI_DSI1 MIPI_DSI1 MIPI_DSI1 MIPI_CSI MIPI_CSI MIPI_CSI CSI_MCL RTC_XT AM 33 04 05 DATA3 DATA0 SS0_B _DATA2_ _CLK_N _DATA3_ 0_DATA1 0_DATA0 0_I2C0_S K CSI_D07 CSI_D05 ALO XTALO N N _N _N DA VSS_MAI AN N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N MIPI_DSI1 _DATA0_ N MIPI_DSI1 _DATA1_ N MIPI_CSI 0_DATA3 _N MIPI_CSI 0_CLK_N MIPI_CSI 0_DATA2 _N MIPI_CSI 0_MCLK_ OUT VSS_MAI N CSI_D04 VSS_MAI N VSS_SCU _XTAL VSS_SCU _XTAL DDR_DQ DDR_DQ DDR_DM DDR_DQ DDR_DQ QSPI0A_ MIPI_DSI1 MIPI_DSI1 MIPI_DSI1 MIPI_CSI MIPI_CSI MIPI_CSI MIPI_CSI RTC_XT AP 35 S4_P 4 36 37 SCLK _DATA2_ _CLK_P _DATA3_ 0_DATA1 0_DATA0 0_GPIO0 0_I2C0_S CSI_EN CSI_D02 ALI XTALI P P _P _P _01 CL VSS_MAI DDR_DQ DDR_DQ DDR_DQ QSPI0B_ QSPI0A_ MIPI_DSI1 MIPI_DSI1 MIPI_CSI MIPI_CSI MIPI_CSI MIPI_CSI CSI_RES CSI_HSY PMIC_ON VSS_SCU AR N S4_N 39 38 SCLK DATA1 _DATA0_ _DATA1_ 0_DATA3 0_CLK_P 0_DATA2 0_GPIO0 ET NC _REQ _XTAL P P _P _P _00 i.MX 8QuadXPlus/8DualXPlus Industrial Applications Processors, Rev. 0 05/2020 NXP Semiconductors 118 Package information and contact assignments 6.1.3 21 x 21 mm power supplies and functional contact assignments The following table shows the power supplies contact assignments for the 21 × 21 mm package Table 123. 21 x 21 mm power supplies contact assignments Power rail Ball reference VDD_A351 AA15,AA17,AA19,AB16,AB18,AB20 VDD_ADC_1P8 V28 VDD_ADC_DIG_1P8 W25 VDD_ANA0_1P8 M14 VDD_ANA1_1P8 AB24 VDD_CAN_UART_1P8_3P3 Y24 VDD_CSI_1P8_3P3 AE23 VDD_DDR_PLL_1P8 AC9 VDD_DDR_VDDQ AA11,AA9,M12,N9,N11,R7,R11,T12,U11,W11,Y12,AC11,AD12,AE11 VDD_EMMC0_1P8_3P3 L19 VDD_EMMC0_VSELECT_1P8_3P3 M20 VDD_ENET_MDIO_1P8_3P3 L25 VDD_ENET0_1P8_2P5_3P3 M24 VDD_ENET0_VSELECT_1P8_2P5_3P3 L23 VDD_ESAI_SPDIF_1P8_2P5_3P3 VDD_GPU1 N25 N23,P20,P22,R21,T22,U23,V20,W21 VDD_MAIN AA23,AB12,AC13,AC17,AC21,AD14,AD22,N15,N19,P12,P16,P24,R13,R17,T14,T 18,U15,U19,V12,V16,V24,W13,W17,Y14,Y18,Y22 VDD_MIPI_1P0 AD18,AE19 VDD_MIPI_1P8 AD16,AE17 VDD_MIPI_CSI_DIG_1P8 AE21 VDD_MIPI_DSI_DIG_1P8_3P3 AA25 VDD_PCIE_1P8 G13 VDD_PCIE_DIG_1P8_3P3 L11 VDD_PCIE_LDO_1P0_CAP L13 VDD_QSPI0A_1P8_3P3 AE15 VDD_QSPI0B_1P8_3P3 AE13 VDD_SNVS_4P2 AC25 VDD_SNVS_LDO_1P8_CAP AE25 VDD_SPI_MCLK_UART_1P8_3P3 R25 i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 119 Package information and contact assignments Table 123. 21 x 21 mm power supplies contact assignments (continued) Power rail Ball reference VDD_SPI_SAI_1P8_3P3 U25 VDD_TMPR_CSI_1P8_3P3 AD24 VDD_USB_1P8 M18 VDD_USB_3P3 L15 VDD_USB_OTG_1P0 L17 VDD_USB_SS3_LDO_1P0_CAP M16 VDD_USDHC1_1P8_3P3 M22 VDD_USDHC1_VSELECT_1P8_3P3 L21 VSS_MAIN A17, A3, A33, AA1, AA13, AA21, AA27, AA3, AA5,AA7,AB10,AB14,AB22,AB26,AB30,AC15,AC19,AC23,AC27,AC33,AD10,AD2, AD20,AD26,AD4,AD6,AE27,AE9,AF10,AF12,AF14,AF16,AF18,AF20,AF22,AF24,A F26,AF30,AG1,AG11,AG13,AG15,AG17,AG19,AG21,AG23, AG25,AG27,AG3,AG33,AG5,AG7,AG9,AH14,AH16,AH18,AH20,AH22,AH24,AH26 ,AK2,AK30,AK4,AK6,AK8,AL13,AL15,AL17,AL19,AL21,AL23,AL25,AL33, AN1,AN11,AN13,AN27,AN3,AN31,AN5,AN7,AN9,AR3,B14,B20,B8,C1,C11,C13,C1 7,C19,C23,C27,C3,C31,C35,C5,C7,C9,E15,E29,E33, F10,F18,F2,F20,F24,F4,F6,F8,H30,J1,J11,J13,J15,J17,J19,J21,J23,J25,J27,J3,J3 3,J5,J7,J9,K10,K12,K14,K16,K18,K20,K22,K24,K26,L27,L9,M10,M2,M26, M30,M4,M6,M8,N13,N17,N21,N27,N33,P10,P14,P18,P26,R1,R15,R19,R23,R27,R 3,R5,R9,T10,T16,T20,T24,T26,T28,T30,T32,T34,U13,U17,U21,U27,U9, V10, V14,V18,V2,V22,V26,V4,V6,V8,W15,W19,W23,W27,W31,W33,W35,W9,Y10,Y16, Y20,Y26,Y28,Y30 VSS_SCU_XTAL 1 VDD_A35 and VDD_GPU can be combined with one power supply. AN33,AN35,AR33 i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 120 NXP Semiconductors Package information and contact assignments The following table shows functional contact assignments for the 21 × 21 mm package. Ball U35 U33 V32 V30 W29 V34 U29 U31 AK34 AL35 AK28 AL29 AP30 AJ27 AN29 AM30 AJ25 AM28 AR29 AL27 AP28 AM26 AK26 AR27 G19 D20 C21 A21 E21 H20 B22 G21 A23 Ball Name ADC_IN0 ADC_IN1 ADC_IN2 ADC_IN3 ADC_IN4 ADC_IN5 ADC_VREFH ADC_VREFL ANA_TEST_OUT_N ANA_TEST_OUT_P CSI_D00 CSI_D01 CSI_D02 CSI_D03 CSI_D04 CSI_D05 CSI_D06 CSI_D07 CSI_HSYNC CSI_VSYNC CSI_EN CSI_MCLK CSI_PCLK CSI_RESET EMMC0_CLK EMMC0_CMD EMMC0_DATA0 EMMC0_DATA1 EMMC0_DATA2 EMMC0_DATA3 EMMC0_DATA4 EMMC0_DATA5 EMMC0_DATA6 Table 124. 21 x 21 mm functional contact assignments Power Domain Ball Type 1 Default Mode Reset Condition2 Default Function Default Default Direction Pull VDD_ADC_DIG_1P8 GPIO ALT0 VDD_ADC_DIG_1P8 GPIO ALT0 VDD_ADC_DIG_1P8 GPIO ALT0 VDD_ADC_DIG_1P8 GPIO ALT0 VDD_ADC_DIG_1P8 GPIO ALT0 VDD_ADC_DIG_1P8 GPIO ALT0 VDD_ADC_1P8 ANA VDD_ADC_1P8 ANA VDD_SCU_ANA_1P8 ANA VDD_SCU_ANA_1P8 ANA VDD_TMPR_CSI_1P8_3P3 GPIO ALT0 VDD_TMPR_CSI_1P8_3P3 GPIO ALT0 VDD_TMPR_CSI_1P8_3P3 GPIO ALT0 VDD_TMPR_CSI_1P8_3P3 GPIO ALT0 VDD_TMPR_CSI_1P8_3P3 GPIO ALT0 VDD_TMPR_CSI_1P8_3P3 GPIO ALT0 VDD_TMPR_CSI_1P8_3P3 GPIO ALT0 VDD_TMPR_CSI_1P8_3P3 GPIO ALT0 VDD_TMPR_CSI_1P8_3P3 GPIO ALT0 VDD_TMPR_CSI_1P8_3P3 GPIO ALT0 VDD_CSI_1P8_3P3 GPIO ALT0 VDD_CSI_1P8_3P3 GPIO ALT4 VDD_CSI_1P8_3P3 GPIO ALT0 VDD_CSI_1P8_3P3 GPIO ALT0 VDD_EMMC0_1P8_3P3 FASTD ALT4 VDD_EMMC0_1P8_3P3 FASTD ALT0 VDD_EMMC0_1P8_3P3 FASTD ALT0 VDD_EMMC0_1P8_3P3 FASTD ALT0 VDD_EMMC0_1P8_3P3 FASTD ALT0 VDD_EMMC0_1P8_3P3 FASTD ALT0 VDD_EMMC0_VSELECT_1P8_3P3 FASTD ALT0 VDD_EMMC0_VSELECT_1P8_3P3 FASTD ALT0 VDD_EMMC0_VSELECT_1P8_3P3 FASTD ALT0 ADMA.ADC.IN0 ADMA.ADC.IN1 ADMA.ADC.IN2 ADMA.ADC.IN3 ADMA.ADC.IN4 ADMA.ADC.IN5 ADC_VREFH ADC_VREFL SCU.DSC.TEST_OUT_N SCU.DSC.TEST_OUT_P CI_PI.CSI_D02 CI_PI.CSI_D03 CI_PI.CSI_D04 CI_PI.CSI_D05 CI_PI.CSI_D06 CI_PI.CSI_D07 CI_PI.CSI_D08 CI_PI.CSI_D09 CI_PI.CSI_HSYNC CI_PI.CSI_VSYNC CI_PI.CSI_EN LSIO.GPIO3.IO01 CI_PI.CSI_PCLK CI_PI.CSI_RESET LSIO.GPIO4.IO07 CONN.EMMC0.CMD CONN.EMMC0.DATA0 CONN.EMMC0.DATA1 CONN.EMMC0.DATA2 CONN.EMMC0.DATA3 CONN.EMMC0.DATA4 CONN.EMMC0.DATA5 CONN.EMMC0.DATA6 INPUT INPUT INPUT INPUT INPUT INPUT PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 121 Package information and contact assignments Table 124. 21 x 21 mm functional contact assignments (continued) Ball Ball Name Power Domain Ball Type 1 Default Mode Reset Condition2 Default Function Default Default Direction Pull D22 EMMC0_DATA7 VDD_EMMC0_VSELECT_1P8_3P3 FASTD ALT0 H22 EMMC0_RESET_B VDD_EMMC0_VSELECT_1P8_3P3 GPIO ALT4 F22 EMMC0_STROBE VDD_EMMC0_VSELECT_1P8_3P3 FASTD ALT0 D30 ENET0_MDC VDD_ENET_MDIO_1P8_3P3 GPIO ALT4 B32 ENET0_MDIO VDD_ENET_MDIO_1P8_3P3 GPIO ALT0 F28 ENET0_REFCLK_125M_25M VDD_ENET_MDIO_1P8_3P3 GPIO ALT4 B30 ENET0_RGMII_RX_CTL VDD_ENET0_1P8_2P5_3P3 FASTD ALT0 D28 ENET0_RGMII_RXC VDD_ENET0_1P8_2P5_3P3 FASTD ALT0 A31 ENET0_RGMII_RXD0 VDD_ENET0_1P8_2P5_3P3 FASTD ALT0 C29 ENET0_RGMII_RXD1 VDD_ENET0_1P8_2P5_3P3 FASTD ALT0 G27 ENET0_RGMII_RXD2 VDD_ENET0_1P8_2P5_3P3 FASTD ALT0 H26 ENET0_RGMII_RXD3 VDD_ENET0_1P8_2P5_3P3 FASTD ALT0 A29 ENET0_RGMII_TX_CTL VDD_ENET0_VSELECT_1P8_2P5_3P3 FASTD ALT4 H24 ENET0_RGMII_TXC VDD_ENET0_VSELECT_1P8_2P5_3P3 FASTD ALT4 G25 ENET0_RGMII_TXD0 VDD_ENET0_VSELECT_1P8_2P5_3P3 FASTD ALT4 B28 ENET0_RGMII_TXD1 VDD_ENET0_VSELECT_1P8_2P5_3P3 FASTD ALT4 E27 ENET0_RGMII_TXD2 VDD_ENET0_VSELECT_1P8_2P5_3P3 FASTD ALT4 F26 ENET0_RGMII_TXD3 VDD_ENET0_VSELECT_1P8_2P5_3P3 FASTD ALT4 F30 ESAI0_FSR VDD_ESAI_SPDIF_1P8_2P5_3P3 GPIO ALT0 G29 ESAI0_FST VDD_ESAI_SPDIF_1P8_2P5_3P3 GPIO ALT0 H28 ESAI0_SCKR VDD_ESAI_SPDIF_1P8_2P5_3P3 GPIO ALT0 E31 ESAI0_SCKT VDD_ESAI_SPDIF_1P8_2P5_3P3 GPIO ALT0 D32 ESAI0_TX0 VDD_ESAI_SPDIF_1P8_2P5_3P3 GPIO ALT0 B34 ESAI0_TX1 VDD_ESAI_SPDIF_1P8_2P5_3P3 GPIO ALT0 K28 ESAI0_TX2_RX3 VDD_ESAI_SPDIF_1P8_2P5_3P3 GPIO ALT0 C33 ESAI0_TX3_RX2 VDD_ESAI_SPDIF_1P8_2P5_3P3 GPIO ALT0 F32 ESAI0_TX4_RX1 VDD_ESAI_SPDIF_1P8_2P5_3P3 GPIO ALT0 J29 ESAI0_TX5_RX0 VDD_ESAI_SPDIF_1P8_2P5_3P3 GPIO ALT0 Y34 FLEXCAN0_RX VDD_CAN_UART_1P8_3P3 GPIO ALT0 Y32 FLEXCAN0_TX VDD_CAN_UART_1P8_3P3 GPIO ALT4 AA33 FLEXCAN1_RX VDD_CAN_UART_1P8_3P3 GPIO ALT0 AA35 FLEXCAN1_TX VDD_CAN_UART_1P8_3P3 GPIO ALT4 AB34 FLEXCAN2_RX VDD_CAN_UART_1P8_3P3 GPIO ALT0 AA31 FLEXCAN2_TX VDD_CAN_UART_1P8_3P3 GPIO ALT4 AE31 JTAG_TCK VDD_ANA1_1P8 TEST ALT0 CONN.EMMC0.DATA7 LSIO.GPIO4.IO18 CONN.EMMC0.STROBE LSIO.GPIO5.IO11 CONN.ENET0.MDIO LSIO.GPIO5.IO09 CONN.ENET0.RGMII_RX_CTL CONN.ENET0.RGMII_RXC CONN.ENET0.RGMII_RXD0 CONN.ENET0.RGMII_RXD1 CONN.ENET0.RGMII_RXD2 CONN.ENET0.RGMII_RXD3 LSIO.GPIO4.IO30 LSIO.GPIO4.IO29 LSIO.GPIO4.IO31 LSIO.GPIO5.IO00 LSIO.GPIO5.IO01 LSIO.GPIO5.IO02 ADMA.ESAI0.FSR ADMA.ESAI0.FST ADMA.ESAI0.SCKR ADMA.ESAI0.SCKT ADMA.ESAI0.TX0 ADMA.ESAI0.TX1 ADMA.ESAI0.TX2_RX3 ADMA.ESAI0.TX3_RX2 ADMA.ESAI0.TX4_RX1 ADMA.ESAI0.TX5_RX0 ADMA.FLEXCAN0.RX LSIO.GPIO1.IO16 ADMA.FLEXCAN1.RX LSIO.GPIO1.IO18 ADMA.FLEXCAN2.RX LSIO.GPIO1.IO20 SCU.JTAG.TCK INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT PD(50K) PU(50K) PD(50K) PD(50K) PU(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 122 NXP Semiconductors Ball AH34 AF32 AG35 G35 M28 L29 AN21 AR21 AM22 AP22 AM20 AP20 AN23 AR23 AN19 AR19 AR25 AP24 AP26 AM24 AN25 AJ19 AK20 AJ21 AK22 AJ17 AK18 AJ23 AK24 AJ15 AK16 AD32 AE35 AC31 AB28 Package information and contact assignments Table 124. 21 x 21 mm functional contact assignments (continued) Ball Name Power Domain Ball Type 1 Default Mode Reset Condition2 Default Function Default Default Direction Pull JTAG_TDI JTAG_TDO JTAG_TMS MCLK_IN0 MCLK_IN1 MCLK_OUT0 MIPI_CSI0_CLK_N MIPI_CSI0_CLK_P MIPI_CSI0_DATA0_N MIPI_CSI0_DATA0_P MIPI_CSI0_DATA1_N MIPI_CSI0_DATA1_P MIPI_CSI0_DATA2_N MIPI_CSI0_DATA2_P MIPI_CSI0_DATA3_N MIPI_CSI0_DATA3_P MIPI_CSI0_GPIO0_00 MIPI_CSI0_GPIO0_01 MIPI_CSI0_I2C0_SCL MIPI_CSI0_I2C0_SDA MIPI_CSI0_MCLK_OUT MIPI_DSI0_CLK_N MIPI_DSI0_CLK_P MIPI_DSI0_DATA0_N MIPI_DSI0_DATA0_P MIPI_DSI0_DATA1_N MIPI_DSI0_DATA1_P MIPI_DSI0_DATA2_N MIPI_DSI0_DATA2_P MIPI_DSI0_DATA3_N MIPI_DSI0_DATA3_P MIPI_DSI0_GPIO0_00 MIPI_DSI0_GPIO0_01 MIPI_DSI0_I2C0_SCL MIPI_DSI0_I2C0_SDA VDD_ANA1_1P8 VDD_ANA1_1P8 VDD_ANA1_1P8 VDD_SPI_MCLK_UART_1P8_3P3 VDD_SPI_MCLK_UART_1P8_3P3 VDD_SPI_MCLK_UART_1P8_3P3 VDD_MIPI_1P8 VDD_MIPI_1P8 VDD_MIPI_1P8 VDD_MIPI_1P8 VDD_MIPI_1P8 VDD_MIPI_1P8 VDD_MIPI_1P8 VDD_MIPI_1P8 VDD_MIPI_1P8 VDD_MIPI_1P8 VDD_MIPI_CSI_DIG_1P8 VDD_MIPI_CSI_DIG_1P8 VDD_MIPI_CSI_DIG_1P8 VDD_MIPI_CSI_DIG_1P8 VDD_MIPI_CSI_DIG_1P8 VDD_MIPI_1P8 VDD_MIPI_1P8 VDD_MIPI_1P8 VDD_MIPI_1P8 VDD_MIPI_1P8 VDD_MIPI_1P8 VDD_MIPI_1P8 VDD_MIPI_1P8 VDD_MIPI_1P8 VDD_MIPI_1P8 VDD_MIPI_DSI_DIG_1P8_3P3 VDD_MIPI_DSI_DIG_1P8_3P3 VDD_MIPI_DSI_DIG_1P8_3P3 VDD_MIPI_DSI_DIG_1P8_3P3 TEST TEST TEST GPIO GPIO GPIO CSI CSI CSI CSI CSI CSI CSI CSI CSI CSI GPIO GPIO GPIO GPIO GPIO DSI DSI DSI DSI DSI DSI DSI DSI DSI DSI GPIO GPIO GPIO GPIO ALT0 ALT0 ALT0 ALT0 ALT0 ALT4 ALT0 ALT0 ALT0 ALT0 ALT4 ALT0 ALT0 ALT0 ALT0 SCU.JTAG.TDI SCU.JTAG.TDO SCU.JTAG.TMS ADMA.ACM.MCLK_IN0 ADMA.ACM.MCLK_IN1 LSIO.GPIO0.IO20 MIPI_CSI0.CKN MIPI_CSI0.CKP MIPI_CSI0.DN0 MIPI_CSI0.DP0 MIPI_CSI0.DN1 MIPI_CSI0.DP1 MIPI_CSI0.DN2 MIPI_CSI0.DP2 MIPI_CSI0.DN3 MIPI_CSI0.DP3 MIPI_CSI0.GPIO0.IO00 MIPI_CSI0.GPIO0.IO01 MIPI_CSI0.I2C0.SCL MIPI_CSI0.I2C0.SDA LSIO.GPIO3.IO04 MIPI_DSI0.CKN MIPI_DSI0.CKP MIPI_DSI0.DN0 MIPI_DSI0.DP0 MIPI_DSI0.DN1 MIPI_DSI0.DP1 MIPI_DSI0.DN2 MIPI_DSI0.DP2 MIPI_DSI0.DN3 MIPI_DSI0.DP3 MIPI_DSI0.GPIO0.IO00 MIPI_DSI0.GPIO0.IO01 MIPI_DSI0.I2C0.SCL MIPI_DSI0.I2C0.SDA INPUT PU(50K) OUTPUT HiZ INPUT PU(50K) INPUT PD(50K) INPUT PD(50K) INPUT PD(50K) Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z INPUT PD(50K) INPUT PD(50K) INPUT PU(50K) INPUT PU(50K) INPUT PD(50K) Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z INPUT PD(50K) INPUT PD(50K) INPUT PU(50K) INPUT PU(50K) i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 123 Package information and contact assignments Table 124. 21 x 21 mm functional contact assignments (continued) Ball Ball Name Power Domain Ball Type 1 Default Mode Reset Condition2 Default Function Default Default Direction Pull AM16 MIPI_DSI1_CLK_N AP16 MIPI_DSI1_CLK_P AN15 MIPI_DSI1_DATA0_N AR15 MIPI_DSI1_DATA0_P AN17 MIPI_DSI1_DATA1_N AR17 MIPI_DSI1_DATA1_P AM14 MIPI_DSI1_DATA2_N AP14 MIPI_DSI1_DATA2_P AM18 MIPI_DSI1_DATA3_N AP18 MIPI_DSI1_DATA3_P AD30 MIPI_DSI1_GPIO0_00 AF34 MIPI_DSI1_GPIO0_01 AE33 MIPI_DSI1_I2C0_SCL AC29 MIPI_DSI1_I2C0_SDA AH28 ON_OFF_BUTTON D10 PCIE_CTRL0_CLKREQ_B H10 PCIE_CTRL0_PERST_B A11 PCIE_CTRL0_WAKE_B F12 PCIE_REF_QR D12 PCIE_REFCLK100M_N E11 PCIE_REFCLK100M_P H12 PCIE_REXT G11 PCIE0_PHY_PLL_REF_RETURN B12 PCIE0_RX0_N A13 PCIE0_RX0_P A9 PCIE0_TX0_N B10 PCIE0_TX0_P AJ35 PMIC_I2C_SCL AH32 PMIC_I2C_SDA AJ33 PMIC_INT_B AR31 PMIC_ON_REQ AG31 POR_B AK14 QSPI0A_DATA0 AR13 QSPI0A_DATA1 AJ13 QSPI0A_DATA2 VDD_MIPI_1P8 VDD_MIPI_1P8 VDD_MIPI_1P8 VDD_MIPI_1P8 VDD_MIPI_1P8 VDD_MIPI_1P8 VDD_MIPI_1P8 VDD_MIPI_1P8 VDD_MIPI_1P8 VDD_MIPI_1P8 VDD_MIPI_DSI_DIG_1P8_3P3 VDD_MIPI_DSI_DIG_1P8_3P3 VDD_MIPI_DSI_DIG_1P8_3P3 VDD_MIPI_DSI_DIG_1P8_3P3 VDD_SNVS_LDO_1P8_CAP VDD_PCIE_DIG_1P8_3P3 VDD_PCIE_DIG_1P8_3P3 VDD_PCIE_DIG_1P8_3P3 VDD_PCIE_1P8 VDD_PCIE_1P8 VDD_PCIE_1P8 VDD_PCIE0_1P0 VDD_PCIE_LDO_1P0_CAP VDD_PCIE_LDO_1P0_CAP VDD_PCIE_LDO_1P0_CAP VDD_PCIE_LDO_1P0_CAP VDD_PCIE_LDO_1P0_CAP VDD_ANA1_1P8 VDD_ANA1_1P8 VDD_ANA1_1P8 VDD_SNVS_LDO_1P8_CAP VDD_ANA1_1P8 VDD_QSPI0A_1P8_3P3 VDD_QSPI0A_1P8_3P3 VDD_QSPI0A_1P8_3P3 DSI MIPI_DSI1.CKN DSI MIPI_DSI1.CKP DSI MIPI_DSI1.DN0 DSI MIPI_DSI1.DP0 DSI MIPI_DSI1.DN1 DSI MIPI_DSI1.DP1 DSI MIPI_DSI1.DN2 DSI MIPI_DSI1.DP2 DSI MIPI_DSI1.DN3 DSI MIPI_DSI1.DP3 GPIO ALT0 MIPI_DSI1.GPIO0.IO00 INPUT GPIO ALT0 MIPI_DSI1.GPIO0.IO01 INPUT GPIO ALT0 MIPI_DSI1.I2C0.SCL INPUT GPIO ALT0 MIPI_DSI1.I2C0.SDA INPUT ANA SNVS.ON_OFF_BUTTON GPIO ALT0 HSIO.PCIE0.CLKREQ_B INPUT GPIO ALT0 HSIO.PCIE0.PERST_B INPUT GPIO ALT0 HSIO.PCIE0.WAKE_B INPUT PCIE HSIO.PCIE_IOB.REF_QR PCIE HSIO.PCIE_IOB.EXT_REFCLK100M_N PCIE HSIO.PCIE_IOB.EXT_REFCLK100M_P PCIE HSIO.PCIE.REXT PCIE HSIO.PCIE0.PLL_REF_RETURN PCIE HSIO.PCIE0.RX0_N PCIE HSIO.PCIE0.RX0_P PCIE HSIO.PCIE0.TX0_N PCIE HSIO.PCIE0.TX0_P SCU ALT0 SCU.PMIC_I2C.SCL INPUT SCU ALT0 SCU.PMIC_I2C.SDA INPUT SCU ALT0 SCU.DSC.PMIC_INT_B INPUT ANA SNVS.PMIC_ON_REQ SCU ALT0 SCU.DSC.POR_B INPUT FASTD ALT0 LSIO.QSPI0A.DATA0 INPUT FASTD ALT0 LSIO.QSPI0A.DATA1 INPUT FASTD ALT0 LSIO.QSPI0A.DATA2 INPUT Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z PD(50K) PD(50K) PU(50K) PU(50K) PD(50K) PD(50K) PU(50K) PU(50K) PU(50K) PU(50K) PU(50K) PD(50K) PD(50K) PD(50K) i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 124 NXP Semiconductors Ball AH12 AL11 AP12 AM12 AK12 AM10 AL9 AJ11 AM8 AK10 AR11 AH10 AJ9 AP32 AM32 M34 J35 K34 L33 L35 M32 N35 AJ31 AK32 AL31 AJ29 AF28 AH30 AG29 AD28 E35 G31 D34 R33 R35 Package information and contact assignments Table 124. 21 x 21 mm functional contact assignments (continued) Ball Name Power Domain Ball Type 1 Default Mode Reset Condition2 Default Function Default Default Direction Pull QSPI0A_DATA3 QSPI0A_DQS QSPI0A_SCLK QSPI0A_SS0_B QSPI0A_SS1_B QSPI0B_DATA0 QSPI0B_DATA1 QSPI0B_DATA2 QSPI0B_DATA3 QSPI0B_DQS QSPI0B_SCLK QSPI0B_SS0_B QSPI0B_SS1_B RTC_XTALI RTC_XTALO SAI0_RXD SAI0_TXC SAI0_TXD SAI0_TXFS SAI1_RXC SAI1_RXD SAI1_RXFS SCU_BOOT_MODE0 SCU_BOOT_MODE1 SCU_BOOT_MODE2 SCU_BOOT_MODE3 SCU_GPIO0_00 SCU_GPIO0_01 SCU_PMIC_STANDBY SCU_WDOG_OUT3 SPDIF0_EXT_CLK SPDIF0_RX SPDIF0_TX SPI0_CS0 SPI0_CS1 VDD_QSPI0A_1P8_3P3 FASTD ALT0 VDD_QSPI0A_1P8_3P3 FASTD ALT0 VDD_QSPI0A_1P8_3P3 FASTD ALT4 VDD_QSPI0A_1P8_3P3 FASTD ALT4 VDD_QSPI0A_1P8_3P3 FASTD ALT4 VDD_QSPI0B_1P8_3P3 FASTD ALT0 VDD_QSPI0B_1P8_3P3 FASTD ALT0 VDD_QSPI0B_1P8_3P3 FASTD ALT0 VDD_QSPI0B_1P8_3P3 FASTD ALT0 VDD_QSPI0B_1P8_3P3 FASTD ALT0 VDD_QSPI0B_1P8_3P3 FASTD ALT4 VDD_QSPI0B_1P8_3P3 FASTD ALT4 VDD_QSPI0B_1P8_3P3 FASTD ALT4 VDD_SNVS_LDO_1P8_CAP ANA VDD_SNVS_LDO_1P8_CAP ANA VDD_SPI_SAI_1P8_3P3 GPIO ALT0 VDD_SPI_SAI_1P8_3P3 GPIO ALT0 VDD_SPI_SAI_1P8_3P3 GPIO ALT0 VDD_SPI_SAI_1P8_3P3 GPIO ALT0 VDD_SPI_SAI_1P8_3P3 GPIO ALT0 VDD_SPI_SAI_1P8_3P3 GPIO ALT0 VDD_SPI_SAI_1P8_3P3 GPIO ALT0 VDD_ANA1_1P8 SCU ALT0 VDD_ANA1_1P8 SCU ALT0 VDD_ANA1_1P8 SCU ALT0 VDD_ANA1_1P8 SCU ALT0 VDD_ANA1_1P8 GPIO ALT0 VDD_ANA1_1P8 GPIO ALT0 VDD_ANA1_1P8 SCU ALT0 VDD_ANA1_1P8 SCU ALT1 VDD_ESAI_SPDIF_1P8_2P5_3P3 GPIO ALT0 VDD_ESAI_SPDIF_1P8_2P5_3P3 GPIO ALT0 VDD_ESAI_SPDIF_1P8_2P5_3P3 GPIO ALT4 VDD_SPI_SAI_1P8_3P3 GPIO ALT0 VDD_SPI_SAI_1P8_3P3 GPIO ALT0 LSIO.QSPI0A.DATA3 LSIO.QSPI0A.DQS LSIO.GPIO3.IO16 LSIO.GPIO3.IO14 LSIO.GPIO3.IO15 LSIO.QSPI0B.DATA0 LSIO.QSPI0B.DATA1 LSIO.QSPI0B.DATA2 LSIO.QSPI0B.DATA3 LSIO.QSPI0B.DQS LSIO.GPIO3.IO17 LSIO.GPIO3.IO23 LSIO.GPIO3.IO24 SNVS.RTC_XTALI SNVS.RTC_XTALO ADMA.SAI0.RXD ADMA.SAI0.TXC ADMA.SAI0.TXD ADMA.SAI0.TXFS ADMA.SAI1.RXC ADMA.SAI1.RXD ADMA.SAI1.RXFS SCU.DSC.BOOT_MODE0 SCU.DSC.BOOT_MODE1 SCU.DSC.BOOT_MODE2 SCU.DSC.BOOT_MODE3 SCU.GPIO0.IO00 SCU.GPIO0.IO01 SCU.DSC.PMIC_STANDBY SCU.WDOG0.WDOG_OUT ADMA.SPDIF0.EXT_CLK ADMA.SPDIF0.RX LSIO.GPIO0.IO11 ADMA.SPI0.CS0 ADMA.SPI0.CS1 INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT PD(50K) PD(50K) PD(50K) PU(50K) PU(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PU(50K) PU(50K) INPUT PD(50K) INPUT PD(50K) INPUT PD(50K) INPUT PD(50K) INPUT PD(50K) INPUT PD(50K) INPUT PD(50K) INPUT PD(50K) INPUT PD(50K) INPUT PD(50K) INPUT PD(50K) INPUT PD(50K) INPUT PU(50K) OUTPUT HiZ OUTPUT PD(50K) INPUT PD(50K) INPUT PD(50K) INPUT PD(50K) INPUT PD(50K) INPUT PD(50K) i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 125 Package information and contact assignments Ball P30 P34 R31 P28 R29 N31 P32 J31 K30 H32 G33 F34 AE29 AB32 AA29 K32 N29 L31 H34 AD34 AC35 E19 D18 G17 H18 D16 E17 F16 D14 H16 E13 B18 A19 F14 H14 Table 124. 21 x 21 mm functional contact assignments (continued) Ball Name Power Domain Ball Type 1 Default Mode Reset Condition2 Default Function Default Default Direction Pull SPI0_SCK SPI0_SDI SPI0_SDO SPI2_CS0 SPI2_SCK SPI2_SDI SPI2_SDO SPI3_CS0 SPI3_CS1 SPI3_SCK SPI3_SDI SPI3_SDO TEST_MODE_SELECT UART0_RX UART0_TX UART1_CTS_B UART1_RTS_B UART1_RX UART1_TX UART2_RX UART2_TX USB_OTG1_DN USB_OTG1_DP USB_OTG1_ID USB_OTG1_VBUS USB_OTG2_DN USB_OTG2_DP USB_OTG2_ID USB_OTG2_REXT USB_OTG2_VBUS USB_SS3_REXT USB_SS3_RX_N USB_SS3_RX_P USB_SS3_TC0 USB_SS3_TC1 VDD_SPI_SAI_1P8_3P3 VDD_SPI_SAI_1P8_3P3 VDD_SPI_SAI_1P8_3P3 VDD_SPI_SAI_1P8_3P3 VDD_SPI_SAI_1P8_3P3 VDD_SPI_SAI_1P8_3P3 VDD_SPI_SAI_1P8_3P3 VDD_SPI_MCLK_UART_1P8_3P3 VDD_SPI_MCLK_UART_1P8_3P3 VDD_SPI_MCLK_UART_1P8_3P3 VDD_SPI_MCLK_UART_1P8_3P3 VDD_SPI_MCLK_UART_1P8_3P3 VDD_ANA1_1P8 VDD_CAN_UART_1P8_3P3 VDD_CAN_UART_1P8_3P3 VDD_SPI_MCLK_UART_1P8_3P3 VDD_SPI_MCLK_UART_1P8_3P3 VDD_SPI_MCLK_UART_1P8_3P3 VDD_SPI_MCLK_UART_1P8_3P3 VDD_CAN_UART_1P8_3P3 VDD_CAN_UART_1P8_3P3 VDD_USB_3P3 VDD_USB_3P3 VDD_USB_3P3 VDD_USB_3P3 VDD_USB_3P3 VDD_USB_3P3 VDD_USB_3P3 VDD_USB_1P8 VDD_USB_SS3_LDO_1P0_CAP VDD_USB_SS3_LDO_1P0_CAP VDD_USB_3P3 VDD_USB_3P3 GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO SCU GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO OTG OTG OTG OTG OTG OTG OTG OTG OTG USB3 USB3 USB3 GPIO GPIO ALT0 ALT0 ALT4 ALT0 ALT0 ALT0 ALT4 ALT0 ALT0 ALT0 ALT0 ALT4 ALT0 ALT0 ALT4 ALT0 ALT4 ALT0 ALT4 ALT0 ALT4 ALT0 ALT0 ADMA.SPI0.SCK ADMA.SPI0.SDI LSIO.GPIO1.IO06 ADMA.SPI2.CS0 ADMA.SPI2.SCK ADMA.SPI2.SDI LSIO.GPIO1.IO01 ADMA.SPI3.CS0 ADMA.SPI3.CS1 ADMA.SPI3.SCK ADMA.SPI3.SDI LSIO.GPIO0.IO14 SCU.TCU.TEST_MODE_SELECT ADMA.UART0.RX LSIO.GPIO1.IO22 ADMA.UART1.CTS_B LSIO.GPT0.CLK ADMA.UART1.RX LSIO.GPIO0.IO21 ADMA.UART2.RX LSIO.GPIO1.IO23 CONN.USB_OTG1.DN CONN.USB_OTG1.DP CONN.USB_OTG1.ID CONN.USB_OTG1.VBUS CONN.USB_OTG2.DM CONN.USB_OTG2.DP CONN.USB_OTG2.ID CONN.USB_OTG2.RTRIM CONN.USB_OTG2.VBUS CONN.USB_SS3.REXT CONN.USB_SS3.RX_M_LN_0 CONN.USB_SS3.RX_P_LN_0 ADMA.I2C1.SCL ADMA.I2C1.SCL INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) PD(50K) INPUT INPUT Hi-Z Hi-Z PD(50K) PD(50K) i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 126 NXP Semiconductors Package information and contact assignments Table 124. 21 x 21 mm functional contact assignments (continued) Ball Ball Name Power Domain Ball Type 1 Default Mode Reset Condition2 Default Function Default Default Direction Pull G15 USB_SS3_TC2 VDD_USB_3P3 GPIO ALT0 ADMA.I2C1.SDA INPUT PD(50K) C15 USB_SS3_TC3 VDD_USB_3P3 GPIO ALT0 ADMA.I2C1.SDA INPUT PD(50K) A15 USB_SS3_TX_N VDD_USB_SS3_LDO_1P0_CAP USB3 CONN.USB_SS3.TX_M_LN_0 B16 USB_SS3_TX_P VDD_USB_SS3_LDO_1P0_CAP USB3 CONN.USB_SS3.TX_P_LN_0 E23 USDHC1_CD_B VDD_USDHC1_VSELECT_1P8_3P3 FASTD ALT0 CONN.USDHC1.CD_B INPUT PU(50K) G23 USDHC1_CLK VDD_USDHC1_1P8_3P3 FASTD ALT4 LSIO.GPIO4.IO23 INPUT PD(50K) C25 USDHC1_CMD VDD_USDHC1_1P8_3P3 FASTD ALT0 CONN.USDHC1.CMD INPUT PU(50K) A27 USDHC1_DATA0 VDD_USDHC1_1P8_3P3 FASTD ALT0 CONN.USDHC1.DATA0 INPUT PU(50K) B26 USDHC1_DATA1 VDD_USDHC1_1P8_3P3 FASTD ALT0 CONN.USDHC1.DATA1 INPUT PU(50K) D26 USDHC1_DATA2 VDD_USDHC1_1P8_3P3 FASTD ALT0 CONN.USDHC1.DATA2 INPUT PU(50K) E25 USDHC1_DATA3 VDD_USDHC1_1P8_3P3 FASTD ALT0 CONN.USDHC1.DATA3 INPUT PU(50K) B24 USDHC1_RESET_B VDD_USDHC1_VSELECT_1P8_3P3 FASTD ALT4 LSIO.GPIO4.IO19 INPUT PU(50K) A25 USDHC1_VSELECT VDD_USDHC1_VSELECT_1P8_3P3 FASTD ALT4 LSIO.GPIO4.IO20 INPUT PD(50K) D24 USDHC1_WP VDD_USDHC1_VSELECT_1P8_3P3 FASTD ALT0 CONN.USDHC1.WP INPUT PD(50K) AP34 XTALI VDD_ANA1_1P8 ANA SCU.DSC.XTALI AM34 XTALO VDD_ANA1_1P8 ANA SCU.DSC.XTALO 1 FASTD are GPIO balls configured for high speed operation using the FASTRZ control. 2 Reset condition shown is before boot code execution. For pad changes after boot code execution, see the System Boot chapter of the device reference manual. 3 SCU_WDOG_OUT was previously named JTAG_TRST_B; it has been renamed because its functionality has changed. i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 127 Package information and contact assignments The following table shows DDR pin function. Ball Name Ball DDR_ATO AB8 DDR_CK0_N Y6 DDR_CK0_P W5 DDR_CK1_N N5 DDR_CK1_P P6 DDR_DCF00 W1 DDR_DCF01 U3 DDR_DCF03 U1 DDR_DCF04 U7 DDR_DCF05 U5 DDR_DCF07 T2 DDR_DCF08 AB4 DDR_DCF09 AB6 DDR_DCF10 AC5 DDR_DCF11 W3 DDR_DCF12 Y8 DDR_DCF14 Y2 DDR_DCF15 Y4 DDR_DCF16 W7 DDR_DCF17 N3 DDR_DCF18 L1 DDR_DCF19 N1 DDR_DCF20 P4 DDR_DCF21 T8 DDR_DCF22 P2 DDR_DCF23 T4 DDR_DCF24 T6 DDR_DCF25 K8 DDR_DCF26 L7 DDR_DCF27 K4 DDR_DCF28 K6 Table 125. DRAM pin function LPDDR4 function -- DDR_CK0_N DDR_CK0_P DDR_CK1_N DDR_CK1_P CA2_A CA4_A CA5_A -- -- -- CA3_A ODT_CA_A CS0_A CA0_A CS1_A CKE0_A CKE1_A CA1_A CA4_B RESET_N CA5_B -- -- -- -- -- ODT_CA_B CA3_B CA0_B CS0_B DDR3L function -- DDR_CK0_N DDR_CK0_P DDR_CK1_N DDR_CK1_P A5 A6 A7 A8 A9 RAS# A3 ODT A1 A0 A2 -- -- A4 A12 RESET_N A14 A15 BA0 BA1 BA2 CAS# ODT1 A13 A10 CS_N[0] i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 128 NXP Semiconductors Ball Name DDR_DCF29 DDR_DCF30 DDR_DCF31 DDR_DCF32 DDR_DCF33 DDR_DM0 DDR_DM1 DDR_DM2 DDR_DM3 DDR_DM4 DDR_DQ00 DDR_DQ01 DDR_DQ02 DDR_DQ03 DDR_DQ04 DDR_DQ05 DDR_DQ06 DDR_DQ07 DDR_DQ08 DDR_DQ09 DDR_DQ10 DDR_DQ11 DDR_DQ12 DDR_DQ13 DDR_DQ14 DDR_DQ15 DDR_DQ16 DDR_DQ17 DDR_DQ18 DDR_DQ19 DDR_DQ20 DDR_DQ21 DDR_DQ22 Ball K2 N7 L5 L3 P8 AJ7 AF4 D4 E1 AP6 AF6 AE5 AH8 AF8 AM4 AM6 AL5 AL7 AJ1 AJ3 AH2 AH4 AC3 AE3 AB2 AC1 B6 E9 E7 D8 G7 H8 H6 Package information and contact assignments Table 125. DRAM pin function (continued) LPDDR4 function CS1_B CKE0_B CKE1_B CA1_B CA2_B DDR_DMI0 DDR_DMI1 DDR_DMI2 DDR_DMI3 -- DDR_DQ00 DDR_DQ01 DDR_DQ02 DDR_DQ03 DDR_DQ04 DDR_DQ05 DDR_DQ06 DDR_DQ07 DDR_DQ08 DDR_DQ09 DDR_DQ10 DDR_DQ11 DDR_DQ12 DDR_DQ13 DDR_DQ14 DDR_DQ15 DDR_DQ16 DDR_DQ17 DDR_DQ18 DDR_DQ19 DDR_DQ20 DDR_DQ21 DDR_DQ22 DDR3L function CS_N[1] CKE0 CKE1 A11 WE# DDR_DMI0 DDR_DMI1 DDR_DMI2 DDR_DMI3 DDR_DMI4 DDR_DQ00 DDR_DQ01 DDR_DQ02 DDR_DQ03 DDR_DQ04 DDR_DQ05 DDR_DQ06 DDR_DQ07 DDR_DQ08 DDR_DQ09 DDR_DQ10 DDR_DQ11 DDR_DQ12 DDR_DQ13 DDR_DQ14 DDR_DQ15 DDR_DQ16 DDR_DQ17 DDR_DQ18 DDR_DQ19 DDR_DQ20 DDR_DQ21 DDR_DQ22 i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 129 Package information and contact assignments Table 125. DRAM pin function (continued) Ball Name DDR_DQ23 DDR_DQ24 DDR_DQ25 DDR_DQ26 DDR_DQ27 DDR_DQ28 DDR_DQ29 DDR_DQ30 DDR_DQ31 DDR_DQ32 DDR_DQ33 DDR_DQ34 DDR_DQ35 DDR_DQ36 DDR_DQ37 DDR_DQ38 DDR_DQ39 DDR_DQS0_N DDR_DQS0_P DDR_DQS1_N DDR_DQS1_P DDR_DQS2_N DDR_DQS2_P DDR_DQS3_N DDR_DQS3_P DDR_DQS4_N DDR_DQS4_P DDR_DTO0 DDR_DTO1 DDR_VREF DDR_ZQ Ball G5 H2 H4 G3 G1 A7 B4 B2 A5 AL1 AM2 AL3 AP2 AP8 AP10 AR9 AR7 AH6 AJ5 AE1 AF2 E5 D6 E3 D2 AR5 AP4 AC7 AE7 AD8 G9 LPDDR4 function DDR_DQ23 DDR_DQ24 DDR_DQ25 DDR_DQ26 DDR_DQ27 DDR_DQ28 DDR_DQ29 DDR_DQ30 DDR_DQ31 -- -- -- -- -- -- -- -- DDR_DQS0_N DDR_DQS0_P DDR_DQS1_N DDR_DQS1_P DDR_DQS2_N DDR_DQS2_P DDR_DQS3_N DDR_DQS3_P -- -- -- -- -- -- DDR3L function DDR_DQ23 DDR_DQ24 DDR_DQ25 DDR_DQ26 DDR_DQ27 DDR_DQ28 DDR_DQ29 DDR_DQ30 DDR_DQ31 DDR_DQ32 DDR_DQ33 DDR_DQ34 DDR_DQ35 DDR_DQ36 DDR_DQ37 DDR_DQ38 DDR_DQ39 DDR_DQS0_N DDR_DQS0_P DDR_DQS1_N DDR_DQS1_P DDR_DQS2_N DDR_DQS2_P DDR_DQS3_N DDR_DQS3_P DDR_DQS4_N DDR_DQS4_P -- -- -- -- i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 130 NXP Semiconductors 7 Release Notes This table provides release notes for the data sheet. Rev. Number Date 0 05/2020 · Initial draft Table 126. Data sheet release notes Substantive Change(s) Release Notes i.MX 8QuadXPlus and 8DualXPlus Industrial Applications Processors, Rev. 0, 05/2020 NXP Semiconductors 131 How to Reach Us: Home Page: nxp.com Web Support: nxp.com/support Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein. NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. 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