EFM32 Leopard Gecko Family EFM32LG Data Sheet The EFM32 Leopard Gecko MCUs are the world’s most energy-friendly microcontrollers. The EFM32LG offers unmatched performance and ultra-low power consumption in both
EFM32 Leopard Gecko Family EFM32LG Data Sheet
The EFM32 Leopard Gecko MCUs are the world's most energyfriendly microcontrollers.
The EFM32LG offers unmatched performance and ultra-low power consumption in both active and sleep modes. EFM32LG devices consume as little as 0.65 A in Stop mode and 211 A/MHz in Run mode. It also features autonomous peripherals, high overall chip and analog integration, and the performance of the industry standard 32-bit ARM CortexM3 processor, making it perfect for battery-powered systems and systems with high-performance, low-energy requirements.
EFM32LG applications include the following:
· Energy, gas, water and smart metering · Health and fitness applications · Smart accessories
· Alarm and security systems · Industrial and home automation
KEY FEATURES
· ARM Cortex-M3 at 48 MHz · Ultra-low power operation
· 0.65 A current in Stop (EM3), with brown-out detection and RAM retention
· 63 A/MHz in EM1 · 211 A/MHz in Run mode (EM0) · Fast wake-up time of 2 µs · Hardware cryptography (AES) · Up to 256 kB of flash and 32 kB of RAM
Core / Memory
ARM CortexTM M3 processor
Memory Protection Unit
Flash Program Memory
RAM Memory
Debug w/ ETM DMA Controller
Clock Management
High Frequency Crystal Oscillator
High Frequency RC Oscillator
Auxiliary High Freq. RC Osc.
Low Freq. RC Oscillator
Low Frequency Crystal Oscillator
Ultra Low Freq. RC Oscillator
Energy Management
Voltage Regulator
Voltage Comparator
Brown-out Detector
Power-on Reset
Back-up Power Domain
Security
Hardware AES
Serial Interfaces
USART
UART
Low Energy UARTTM
I2C
USB
32-bit bus
Peripheral Reflex System
I/O Ports
External Bus Interface
TFT Driver
External Interrupts
General Purpose I/O
Pin Reset
Pin Wakeup
Timers and Triggers
Timer/Counter
LESENSE
Low Energy Timer Real Time Counter
Pulse Counter Watchdog Timer
Back-up RTC
Analog Interfaces
ADC
LCD Controller
DAC
Analog Comparator
Operational Amplifier
Lowest power mode with peripheral operational:
EM0 - Active
EM1 - Sleep
EM2 Deep Sleep
EM3 - Stop
EM4 - Shutoff
silabs.com | Building a more connected world.
Rev. 2.30
EFM32LG Data Sheet
Feature List
1. Feature List
· ARM Cortex-M3 CPU platform · High Performance 32-bit processor @ up to 48 MHz · Memory Protection Unit · Wake-up Interrupt Controller · SysTick System Timer
· Flexible Energy Management System · 20 nA @ 3 V Shutoff Mode · 0.4 µA @ 3 V Shutoff Mode with RTC · 0.65 µA @ 3 V Stop Mode, including Power-on Reset, Brown-out Detector, RAM and CPU retention · 0.95 µA @ 3 V Deep Sleep Mode, including RTC with 32.768 kHz oscillator, Power-on Reset, Brown-out Detector, RAM and CPU retention · 63 µA/MHz @ 3 V Sleep Mode · 211 µA/MHz @ 3 V Run Mode, with code executed from flash
· 256/128/64 kB flash · 32 kB RAM · Up to 93 General Purpose I/O pins
· Configurable push-pull, open-drain, pull-up/down, input filter, drive strength · Configurable peripheral I/O locations · 16 asynchronous external interrupts · Output state retention and wake-up from Shutoff Mode · 12 Channel DMA Controller · 12 Channel Peripheral Reflex System (PRS) for autonomous inter-peripheral signaling · Hardware AES with 128/256-bit keys in 54/75 cycles · Timers/Counters · 4× 16-bit Timer/Counter
· 4×3 Compare/Capture/PWM channels · Dead-Time Insertion on TIMER0 · 16-bit Low Energy Timer · 1× 24-bit Real-Time Counter and 1× 32-bit Real-Time Counter · 3× 16/8-bit Pulse Counter · Watchdog Timer with dedicated RC oscillator @ 50 nA · Integrated LCD Controller for up to 8×36 segments · Voltage boost, adjustable contrast, and autonomous animation · Backup Power Domain · RTC and retention registers in a separate power domain, available in all energy modes · Operation from backup battery when main power drains out · External Bus Interface for up to 4x256 MB of external memory mapped space · TFT Controller with Direct Drive · Communication interfaces · Up to 3× Universal Synchronous/Asynchronous Receiver/Transmitter · UART/SPI/SmartCard (ISO 7816)/IrDA/I2S · 2× Universal Asynchronous Receiver/Transmitter · 2× Low Energy UART · Autonomous operation with DMA in Deep Sleep Mode · 2× I2C Interface with SMBus support · Address recognition in Stop Mode · Universal Serial Bus (USB) with Host & OTG support · Fully USB 2.0 compliant · On-chip PHY and embedded 5 to 3.3 V regulator
silabs.com | Building a more connected world.
Rev. 2.30 | 2
· Ultra-low power precision analog peripherals · 12-bit 1 Msamples/s Analog to Digital Converter · 8 single-ended channels/4 differential channels · On-chip temperature sensor · 12-bit 500 ksamples/s Digital to Analog Converter · 2 single-ended channels/1 differential channel · Up to 2× Analog Comparator · Capacitive sensing with up to 16 inputs · 3× Operational Amplifier · 6.1 MHz GBW, Rail-to-rail, Programmable Gain · Supply Voltage Comparator
· Low Energy Sensor Interface (LESENSE) · Autonomous sensor monitoring in Deep Sleep Mode · Wide range of sensors supported, including LC sensors and capacitive buttons
· Ultra efficient Power-on Reset and Brown-Out Detector · Debug Interface
· 2-pin Serial Wire Debug interface · 1-pin Serial Wire Viewer
· Embedded Trace Module v3.5 (ETM) · Pre-programmed USB/UART Bootloader · Temperature range -40 to 85 ºC · Single power supply 1.98 to 3.8 V · Packages:
· BGA112 · BGA120 · CSP81 · LQFP100 · TQFP64 · QFN64 · Full wafer
EFM32LG Data Sheet
Feature List
silabs.com | Building a more connected world.
Rev. 2.30 | 3
2. Ordering Information
The following table shows the available EFM32LG devices. Table 2.1. Ordering Information
EFM32LG Data Sheet
Ordering Information
Ordering Code EFM32LG230F64G-F-QFN64 EFM32LG230F128G-F-QFN64 EFM32LG230F256G-F-QFN64 EFM32LG232F64G-F-QFP64 EFM32LG232F128G-F-QFP64 EFM32LG232F256G-F-QFP64 EFM32LG280F64G-F-QFP100 EFM32LG280F128G-F-QFP100 EFM32LG280F256G-F-QFP100 EFM32LG290F64G-F-BGA112 EFM32LG290F128G-F-BGA112 EFM32LG290F256G-F-BGA112 EFM32LG295F64G-F-BGA120 EFM32LG295F128G-F-BGA120 EFM32LG295F256G-F-BGA120 EFM32LG330F64G-F-QFN64 EFM32LG330F128G-F-QFN64 EFM32LG330F256G-F-QFN64 EFM32LG332F64G-F-QFP64 EFM32LG332F128G-F-QFP64 EFM32LG332F256G-F-QFP64 EFM32LG360F64G-F-CSP81 EFM32LG360F128G-F-CSP81 EFM32LG360F256G-F-CSP81 EFM32LG380F64G-F-QFP100 EFM32LG380F128G-F-QFP100 EFM32LG380F256G-F-QFP100 EFM32LG390F64G-F-BGA112 EFM32LG390F128G-F-BGA112 EFM32LG390F256G-F-BGA112 EFM32LG395F64G-F-BGA120 EFM32LG395F128G-F-BGA120
Flash (kB) 64 128 256 64 128 256 64 128 256 64 128 256 64 128 256 64 128 256 64 128 256 64 128 256 64 128 256 64 128 256 64 128
RAM (kB) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
Max Speed Supply
(MHz)
Voltage (V)
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
Temperature (ºC)
-40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85
Package QFN64 QFN64 QFN64 TQFP64 TQFP64 TQFP64 LQFP100 LQFP100 LQFP100 BGA112 BGA112 BGA112 BGA120 BGA120 BGA120 QFN64 QFN64 QFN64 TQFP64 TQFP64 TQFP64 CSP81 CSP81 CSP81 LQFP100 LQFP100 LQFP100 BGA112 BGA112 BGA112 BGA120 BGA120
silabs.com | Building a more connected world.
Rev. 2.30 | 4
Ordering Code EFM32LG395F256G-F-BGA120 EFM32LG840F64G-F-QFN64 EFM32LG840F128G-F-QFN64 EFM32LG840F256G-F-QFN64 EFM32LG842F64G-F-QFP64 EFM32LG842F128G-F-QFP64 EFM32LG842F256G-F-QFP64 EFM32LG880F64G-F-QFP100 EFM32LG880F128G-F-QFP100 EFM32LG880F256G-F-QFP100 EFM32LG890F64G-F-BGA112 EFM32LG890F128G-F-BGA112 EFM32LG890F256G-F-BGA112 EFM32LG895F64G-F-BGA120 EFM32LG895F128G-F-BGA120 EFM32LG895F256G-F-BGA120 EFM32LG900F256G-F-D1I EFM32LG940F64G-F-QFN64 EFM32LG940F128G-F-QFN64 EFM32LG940F256G-F-QFN64 EFM32LG942F64G-F-QFP64 EFM32LG942F128G-F-QFP64 EFM32LG942F256G-F-QFP64 EFM32LG980F64G-F-QFP100 EFM32LG980F128G-F-QFP100 EFM32LG980F256G-F-QFP100 EFM32LG990F64G-F-BGA112 EFM32LG990F128G-F-BGA112 EFM32LG990F256G-F-BGA112 EFM32LG995F64G-F-BGA120 EFM32LG995F128G-F-BGA120 EFM32LG995F256G-F-BGA120
EFM32LG Data Sheet
Ordering Information
Flash (kB) 256 64 128 256 64 128 256 64 128 256 64 128 256 64 128 256 256 64 128 256 64 128 256 64 128 256 64 128 256 64 128 256
RAM (kB) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
Max Speed Supply
(MHz)
Voltage (V)
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
48
1.98 - 3.8
Temperature (ºC)
-40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85
Package BGA120 QFN64 QFN64 QFN64 TQFP64 TQFP64 TQFP64 LQFP100 LQFP100 LQFP100 BGA112 BGA112 BGA112 BGA120 BGA120 BGA120
Wafer QFN64 QFN64 QFN64 TQFP64 TQFP64 TQFP64 LQFP100 LQFP100 LQFP100 BGA112 BGA112 BGA112 BGA120 BGA120 BGA120
silabs.com | Building a more connected world.
Rev. 2.30 | 5
EFM32LG Data Sheet
Ordering Information
EFM32 LG 995 F 256 G F BGA 120 R
Tape and Reel (Optional) Pin Count Package Revision Temperature Grade G (-40 to +85 °C) Memory Size in kB Memory Type (Flash) Feature Set Code Leopard Gecko Energy Friendly Microcontroller 32-bit
Figure 2.1. Ordering Code Decoder
Adding the suffix 'R' to the part number (e.g. EFM32LGF256G-F-BGA120R) denotes tape and reel. Visit www.silabs.com for information on global distributors and representatives.
silabs.com | Building a more connected world.
Rev. 2.30 | 6
Table of Contents
1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3. System Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 System Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.1.1 ARM Cortex-M3 Core . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.1.2 Debug Interface (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.1.3 Memory System Controller (MSC) . . . . . . . . . . . . . . . . . . . . . .13 3.1.4 Direct Memory Access Controller (DMA) . . . . . . . . . . . . . . . . . . . .13 3.1.5 Reset Management Unit (RMU) . . . . . . . . . . . . . . . . . . . . . . .13 3.1.6 Energy Management Unit (EMU) . . . . . . . . . . . . . . . . . . . . . .14 3.1.7 Clock Management Unit (CMU) . . . . . . . . . . . . . . . . . . . . . . .14 3.1.8 Watchdog (WDOG) . . . . . . . . . . . . . . . . . . . . . . . . . . .14 3.1.9 Peripheral Reflex System (PRS) . . . . . . . . . . . . . . . . . . . . . .14 3.1.10 External Bus Interface (EBI) . . . . . . . . . . . . . . . . . . . . . . .14 3.1.11 TFT Direct Drive . . . . . . . . . . . . . . . . . . . . . . . . . . .14 3.1.12 Universal Serial Bus Controller (USB) . . . . . . . . . . . . . . . . . . . .14 3.1.13 Inter-Integrated Circuit Interface (I2C) . . . . . . . . . . . . . . . . . . . .14 3.1.14 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) . . . . . . . . .14 3.1.15 Pre-Programmed USB/UART Bootloader . . . . . . . . . . . . . . . . . . .15 3.1.16 Universal Asynchronous Receiver/Transmitter (UART) . . . . . . . . . . . . . .15 3.1.17 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) . . . . . . . . .15 3.1.18 Timer/Counter (TIMER) . . . . . . . . . . . . . . . . . . . . . . . . .15 3.1.19 Real Time Counter (RTC) . . . . . . . . . . . . . . . . . . . . . . . .15 3.1.20 Backup Real Time Counter (BURTC) . . . . . . . . . . . . . . . . . . . .15 3.1.21 Low Energy Timer (LETIMER) . . . . . . . . . . . . . . . . . . . . . . .15 3.1.22 Pulse Counter (PCNT) . . . . . . . . . . . . . . . . . . . . . . . . .15 3.1.23 Analog Comparator (ACMP) . . . . . . . . . . . . . . . . . . . . . . .15 3.1.24 Voltage Comparator (VCMP) . . . . . . . . . . . . . . . . . . . . . . .15 3.1.25 Analog to Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . .16 3.1.26 Digital to Analog Converter (DAC) . . . . . . . . . . . . . . . . . . . . .16 3.1.27 Operational Amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . .16 3.1.28 Low Energy Sensor Interface (LESENSE) . . . . . . . . . . . . . . . . . . .16 3.1.29 Backup Power Domain . . . . . . . . . . . . . . . . . . . . . . . . .16 3.1.30 Advanced Encryption Standard Accelerator (AES) . . . . . . . . . . . . . . . .16 3.1.31 General Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . .16 3.1.32 Liquid Crystal Display Driver (LCD) . . . . . . . . . . . . . . . . . . . . .16
3.2 Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .16 3.2.1 EFM32LG230 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 3.2.2 EFM32LG232 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 3.2.3 EFM32LG280 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 3.2.4 EFM32LG290 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 3.2.5 EFM32LG295 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 3.2.6 EFM32LG330 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 3.2.7 EFM32LG332 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
silabs.com | Building a more connected world.
Rev. 2.30 | 7
3.2.8 EFM32LG360 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 3.2.9 EFM32LG380 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 3.2.10 EFM32LG390 . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 3.2.11 EFM32LG395 . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.2.12 EFM32LG840 . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 3.2.13 EFM32LG842 . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 3.2.14 EFM32LG880 . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 3.2.15 EFM32LG890 . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 3.2.16 EFM32LG895 . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 3.2.17 EFM32LG900 . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 3.2.18 EFM32LG940 . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 3.2.19 EFM32LG942 . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 3.2.20 EFM32LG980 . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 3.2.21 EFM32LG990 . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 3.2.22 EFM32LG995 . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
3.3 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.1 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 4.1.1 Typical Values . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 4.1.2 Minimum and Maximum Values . . . . . . . . . . . . . . . . . . . . . . .63
4.2 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . .63
4.3 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . .63
4.4 Backup Supply Domain . . . . . . . . . . . . . . . . . . . . . . . . . . .64
4.5 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 4.5.1 EM1 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . .67 4.5.2 EM2 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . .70 4.5.3 EM3 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . .71 4.5.4 EM4 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . .71
4.6 Transition between Energy Modes . . . . . . . . . . . . . . . . . . . . . . .72
4.7 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
4.8 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
4.9 General Purpose Input Output . . . . . . . . . . . . . . . . . . . . . . . . .74
4.10 Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 4.10.1 LFXO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 4.10.2 HFXO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 4.10.3 LFRCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 4.10.4 HFRCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 4.10.5 AUXHFRCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 4.10.6 ULFRCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
4.11 Analog Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . .91 4.11.1 Typical Performance . . . . . . . . . . . . . . . . . . . . . . . . . .97
4.12 Digital Analog Converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . 102
4.13 Operational Amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . 104
silabs.com | Building a more connected world.
Rev. 2.30 | 8
4.14 Analog Comparator (ACMP) . . . . . . . . . . . . . . . . . . . . . . . . 111 4.15 Voltage Comparator (VCMP) . . . . . . . . . . . . . . . . . . . . . . . . 119 4.16 EBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 20 4.17 LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 4.18 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 26 4.19 USART SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.28 4.20 Digital Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . .130
5. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
5.1 EFM32LG230 (QFN64) . . . . . . . . . . . . . . . . . . . . . . . . . . 131 5.1.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 31 5.1.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . 1.35 5.1.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 140 5.1.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . .140
5.2 EFM32LG232 (TQFP64)
. . . . . . . . . . . . . . . . . . . . . . . . 1.41
5.2.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 41
5.2.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . 1.45
5.2.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 149
5.2.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . .150
5.3 EFM32LG280 (LQFP100) . . . . . . . . . . . . . . . . . . . . . . . . .151 5.3.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 51 5.3.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . 1.57 5.3.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 164 5.3.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . .164
5.4 EFM32LG290 (BGA112)
. . . . . . . . . . . . . . . . . . . . . . . . 1.65
5.4.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 65
5.4.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . 1.71
5.4.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 178
5.4.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . .178
5.5 EFM32LG295 (BGA120)
. . . . . . . . . . . . . . . . . . . . . . . . 1.79
5.5.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 79
5.5.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . 1.85
5.5.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 192
5.5.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . .192
5.6 EFM32LG330 (QFN64) . . . . . . . . . . . . . . . . . . . . . . . . . . 193 5.6.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 93 5.6.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . 1.97 5.6.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 202 5.6.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . .202
5.7 EFM32LG332 (TQFP64)
. . . . . . . . . . . . . . . . . . . . . . . . 2.03
5.7.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2. 03
5.7.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . 2.07
5.7.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 211
5.7.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . .212
5.8 EFM32LG360 (CSP81) . . . . . . . . . . . . . . . . . . . . . . . . . . 213
silabs.com | Building a more connected world.
Rev. 2.30 | 9
5.8.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2. 13 5.8.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . 2.18 5.8.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 223 5.8.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . .223
5.9 EFM32LG380 (LQFP100) . . . . . . . . . . . . . . . . . . . . . . . . .224 5.9.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2. 24 5.9.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . 2.29 5.9.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 236 5.9.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . .236
5.10 EFM32LG390 (BGA112) . . . . . . . . . . . . . . . . . . . . . . . . .237 5.10.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 5.10.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .243 5.10.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . 2. 50 5.10.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 250
5.11 EFM32LG395 (BGA120) . . . . . . . . . . . . . . . . . . . . . . . . .251 5.11.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 5.11.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .257 5.11.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . 2. 64 5.11.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 265
5.12 EFM32LG840 (QFN64)
. . . . . . . . . . . . . . . . . . . . . . . . 2.66
5.12.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
5.12.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .270
5.12.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . 2. 76
5.12.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 276
5.13 EFM32LG842 (TQFP64) . . . . . . . . . . . . . . . . . . . . . . . . .277 5.13.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 5.13.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .281 5.13.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . 2. 87 5.13.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 287
5.14 EFM32LG880 (LQFP100) . . . . . . . . . . . . . . . . . . . . . . . . . 288 5.14.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 5.14.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .294 5.14.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . 3. 03 5.14.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 304
5.15 EFM32LG890 (BGA112) . . . . . . . . . . . . . . . . . . . . . . . . .305 5.15.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 5.15.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .311 5.15.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . 3. 20 5.15.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 321
5.16 EFM32LG895 (BGA120) . . . . . . . . . . . . . . . . . . . . . . . . .322 5.16.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 5.16.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .328 5.16.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . 3. 37 5.16.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 337
5.17 EFM32LG900 (Wafer) . . . . . . . . . . . . . . . . . . . . . . . . . . 338 5.17.1 Padout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
silabs.com | Building a more connected world.
Rev. 2.30 | 10
5.17.2 Alternate Functionality Padout . . . . . . . . . . . . . . . . . . . . . . 344 5.17.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . 3. 53 5.17.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 354
5.18 EFM32LG940 (QFN64)
. . . . . . . . . . . . . . . . . . . . . . . . 3.55
5.18.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
5.18.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .359
5.18.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . 3. 65
5.18.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 365
5.19 EFM32LG942 (TQFP64) . . . . . . . . . . . . . . . . . . . . . . . . .366 5.19.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 5.19.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .370 5.19.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . 3. 75 5.19.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 376
5.20 EFM32LG980 (LQFP100) . . . . . . . . . . . . . . . . . . . . . . . . . 377 5.20.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 5.20.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .383 5.20.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . 3. 92 5.20.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 392
5.21 EFM32LG990 (BGA112) . . . . . . . . . . . . . . . . . . . . . . . . .393 5.21.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 5.21.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .399 5.21.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . 4. 08 5.21.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 408
5.22 EFM32LG995 (BGA120) . . . . . . . . . . . . . . . . . . . . . . . . .409 5.22.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 5.22.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .415 5.22.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . 4. 24 5.22.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 425
6. BGA112 Package Specifications . . . . . . . . . . . . . . . . . . . . . . .426 6.1 BGA112 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 426 6.2 BGA112 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 6.3 BGA112 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . 429
7. BGA120 Package Specifications . . . . . . . . . . . . . . . . . . . . . . .430 7.1 BGA120 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 430 7.2 BGA120 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 7.3 BGA120 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . 433
8. CSP81 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . 434 8.1 CSP81 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . .434 8.2 CSP81 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . .436 8.3 CSP81 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . 4. 39 8.4 CSP81 Environmental . . . . . . . . . . . . . . . . . . . . . . . . . 4. 39
9. LQFP100 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . 440
silabs.com | Building a more connected world.
Rev. 2.30 | 11
9.1 LQFP100 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . .440 9.2 LQFP100 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . 4. 42 9.3 LQFP100 Package Marking . . . . . . . . . . . . . . . . . . . . . . . 4.44
10. QFN64 Package Specifications . . . . . . . . . . . . . . . . . . . . . . .445 10.1 QFN64 Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . . 445 10.2 QFN64 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 10.3 QFN64 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . 449
11. TQFP64 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . 450 11.1 TQFP64 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . .450 11.2 TQFP64 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . .452 11.3 TQFP64 Package Marking . . . . . . . . . . . . . . . . . . . . . . . 4. 54
12. Wafer Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .455
12.1 Bonding Instructions
. . . . . . . . . . . . . . . . . . . . . . . . . 4.55
12.2 Wafer Description . . . . . . . . . . . . . . . . . . . . . . . . . . 4. 55 12.2.1 Environmental . . . . . . . . . . . . . . . . . . . . . . . . . . .455
12.3 Wafer Storage Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . 456
12.4 Failure Analysis (FA) Guidelines . . . . . . . . . . . . . . . . . . . . . 4. 56
13. Chip Revision, Solder Information, Errata . . . . . . . . . . . . . . . . . . .457 13.1 Chip Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 13.2 Soldering Information . . . . . . . . . . . . . . . . . . . . . . . . . .457 13.3 Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4. 57
14. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
silabs.com | Building a more connected world.
Rev. 2.30 | 12
3. System Summary
EFM32LG Data Sheet
System Summary
3.1 System Introduction
The EFM32 MCUs are the world's most energy friendly microcontrollers. With a unique combination of the powerful 32-bit ARM CortexM3, innovative low energy techniques, short wake-up time from energy saving modes, and a wide selection of peripherals, the EFM32LG microcontroller is well suited for any battery operated application as well as other systems requiring high performance and low-energy consumption. This section gives a short introduction to each of the modules in general terms and also shows a summary of the configuration for the EFM32LG devices. For a complete feature set and in-depth information on the modules, refer to the EFM32LG Reference Manual.
A block diagram of the EFM32LG is shown in the following figure.
Core / Memory
ARM CortexTM M3 processor
Memory Protection Unit
Flash Program Memory
RAM Memory
Debug w/ ETM DMA Controller
Clock Management
High Frequency Crystal Oscillator
High Frequency RC Oscillator
Auxiliary High Freq. RC Osc.
Low Freq. RC Oscillator
Low Frequency Crystal Oscillator
Ultra Low Freq. RC Oscillator
Energy Management
Voltage Regulator
Voltage Comparator
Brown-out Detector
Power-on Reset
Back-up Power Domain
Security
Hardware AES
Serial Interfaces
USART
UART
Low Energy UARTTM
I2C
USB
32-bit bus
Peripheral Reflex System
I/O Ports
External Bus Interface
TFT Driver
External Interrupts
General Purpose I/O
Pin Reset
Pin Wakeup
Timers and Triggers
Timer/Counter
LESENSE
Low Energy Timer Real Time Counter
Pulse Counter Watchdog Timer
Back-up RTC
Analog Interfaces
ADC
LCD Controller
DAC
Analog Comparator
Operational Amplifier
Lowest power mode with peripheral operational:
EM0 - Active
EM1 - Sleep
EM2 Deep Sleep
EM3 - Stop
EM4 - Shutoff
Figure 3.1. Block Diagram
3.1.1 ARM Cortex-M3 Core
The ARM Cortex-M3 includes a 32-bit RISC processor which can achieve as much as 1.25 Dhrystone MIPS/MHz. A Memory Protection Unit with support for up to 8 memory segments is included, as well as a Wake-up Interrupt Controller handling interrupts triggered while the CPU is asleep. The EFM32 implementation of the Cortex-M3 is described in detail in EFM32LG Reference Manual.
3.1.2 Debug Interface (DBG)
This device includes hardware debug support through a 2-pin serial-wire debug interface and an Embedded Trace Module (ETM) for data/instruction tracing. In addition there is also a 1-wire Serial Wire Viewer pin which can be used to output profiling information, data trace and software-generated messages.
3.1.3 Memory System Controller (MSC)
The Memory System Controller (MSC) is the program memory unit of the EFM32LG microcontroller. The flash memory is readable and writable from both the Cortex-M3 and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code is normally written to the main block. Additionally, the information block is available for special user data and flash lock bits. There is also a read-only page in the information block containing system and device calibration data. Read and write operations are supported in the energy modes EM0 and EM1.
3.1.4 Direct Memory Access Controller (DMA)
The Direct Memory Access (DMA) controller performs memory operations independently of the CPU. This has the benefit of reducing the energy consumption and the workload of the CPU, and enables the system to stay in low energy modes when moving for instance data from the USART to RAM or from the External Bus Interface to a PWM-generating timer. The DMA controller uses the PL230 µDMA controller licensed from ARM.
3.1.5 Reset Management Unit (RMU)
The RMU is responsible for handling the reset functionality of the EFM32LG.
silabs.com | Building a more connected world.
Rev. 2.30 | 13
EFM32LG Data Sheet
System Summary
3.1.6 Energy Management Unit (EMU)
The Energy Management Unit (EMU) manage all the low energy modes (EM) in EFM32LG microcontrollers. Each energy mode manages if the CPU and the various peripherals are available. The EMU can also be used to turn off the power to unused SRAM blocks.
3.1.7 Clock Management Unit (CMU)
The Clock Management Unit (CMU) is responsible for controlling the oscillators and clocks on-board the EFM32LG. The CMU provides the capability to turn on and off the clock on an individual basis to all peripheral modules in addition to enable/disable and configure the available oscillators. The high degree of flexibility enables software to minimize energy consumption in any specific application by not wasting power on peripherals and oscillators that are inactive.
3.1.8 Watchdog (WDOG)
The purpose of the watchdog timer is to generate a reset in case of a system failure, to increase application reliability. The failure may e.g. be caused by an external event, such as an ESD pulse, or by a software failure.
3.1.9 Peripheral Reflex System (PRS)
The Peripheral Reflex System (PRS) system is a network which lets the different peripheral module communicate directly with each other without involving the CPU. Peripheral modules which send out Reflex signals are called producers. The PRS routes these reflex signals to consumer peripherals which apply actions depending on the data received. The format for the Reflex signals is not given, but edge triggers and other functionality can be applied by the PRS.
3.1.10 External Bus Interface (EBI)
The External Bus Interface provides access to external parallel interface devices such as SRAM, FLASH, ADCs and LCDs. The interface is memory mapped into the address bus of the Cortex-M3. This enables seamless access from software without manually manipulating the IO settings each time a read or write is performed. The data and address lines are multiplexed in order to reduce the number of pins required to interface the external devices. The timing is adjustable to meet specifications of the external devices. The interface is limited to asynchronous devices.
3.1.11 TFT Direct Drive
The EBI contains a TFT controller which can drive a TFT via a 565 RGB interface. The TFT controller supports programmable display and port sizes and offers accurate control of frequency and setup and hold timing. Direct Drive is supported for TFT displays which do not have their own frame buffer. In that case TFT Direct Drive can transfer data from either on-chip memory or from an external memory device to the TFT at low CPU load. Automatic alpha-blending and masking is also supported for transfers through the EBI interface.
3.1.12 Universal Serial Bus Controller (USB)
The USB is a full-speed USB 2.0 compliant OTG host/device controller. The USB can be used in Device, On-the-Go (OTG) Dual Role Device, or Host-only configuration. In OTG mode, the USB supports both Host Negotiation Protocol (HNP) and Session Request Protocol (SRP). The device supports both full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) operation. The USB device includes an internal, dedicated Descriptor-Based Scatter/Gather DMA and supports up to 6 OUT endpoints and 6 IN endpoints, in addition to endpoint 0. The on-chip PHY includes all OTG features, except for the voltage booster for supplying 5V to VBUS when operating as a host.
3.1.13 Inter-Integrated Circuit Interface (I2C)
The I2C module provides an interface between the MCU and a serial I2C-bus. It is capable of acting as both a master and a slave, and supports multi-master buses. Both standard-mode, fast-mode and fastmode plus speeds are supported, allowing transmission rates all the way from 10 kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also provided to allow implementation of an SMBus compliant system. The interface provided to software by the I2C module, allows both fine-grained control of the transmission process and close to automatic transfers. Automatic recognition of slave addresses is provided in all energy modes.
3.1.14 Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
The Universal Synchronous Asynchronous serial Receiver and Transmitter (USART) is a very flexible serial I/O module. It supports full duplex asynchronous UART communication as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with ISO7816 SmartCards, IrDA and I2S devices.
silabs.com | Building a more connected world.
Rev. 2.30 | 14
EFM32LG Data Sheet
System Summary
3.1.15 Pre-Programmed USB/UART Bootloader The bootloader presented in application note, AN0042: USB/UART Bootloader, is pre-programmed in the device at factory. The bootloader enables users to program the EFM32 through a UART or a USB CDC class virtual UART without the need for a debugger. The autobaud feature, interface, and commands are described further in the application note.
3.1.16 Universal Asynchronous Receiver/Transmitter (UART) The Universal Asynchronous serial Receiver and Transmitter (UART) is a very flexible serial I/O module. It supports full- and half-duplex asynchronous UART communication.
3.1.17 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) The unique LEUARTTM, the Low Energy UART, is a UART that allows two-way UART communication on a strict power budget. Only a 32.768 kHz clock is needed to allow UART communication up to 9600 baud/ s. The LEUART includes all necessary hardware support to make asynchronous serial communication possible with minimum of software intervention and energy consumption.
3.1.18 Timer/Counter (TIMER) The 16-bit general purpose timer has three compare/capture channels for input capture and compare/Pulse-Width Modulation (PWM) output. TIMER0 also includes a Dead-Time Insertion module suitable for motor control applications.
3.1.19 Real Time Counter (RTC) The Real Time Counter (RTC) contains a 24-bit counter and is clocked either by a 32.768 kHz crystal oscillator, or a 32.768 kHz RC oscillator. In addition to energy modes EM0 and EM1, the RTC is also available in EM2. This makes it ideal for keeping track of time since the RTC is enabled in EM2 where most of the device is powered down.
3.1.20 Backup Real Time Counter (BURTC) The Backup Real Time Counter (BURTC) contains a 32-bit counter and is clocked either by a 32.768 kHz crystal oscillator, a 32.768 kHz RC oscillator or a 1 kHz ULFRCO. The BURTC is available in all Energy Modes and it can also run in backup mode, making it operational even if the main power should drain out.
3.1.21 Low Energy Timer (LETIMER) The unique LETIMERTM, the Low Energy Timer, is a 16-bit timer that is available in energy mode EM2 in addition to EM1 and EM0. Because of this, it can be used for timing and output generation when most of the device is powered down, allowing simple tasks to be performed while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of waveforms with minimal software intervention. It is also connected to the Real Time Counter (RTC), and can be configured to start counting on compare matches from the RTC.
3.1.22 Pulse Counter (PCNT) The Pulse Counter (PCNT) can be used for counting pulses on a single input or to decode quadrature encoded inputs. It runs off either the internal LFACLK or the PCNTn_S0IN pin as external clock source. The module may operate in energy mode EM0 - EM3.
3.1.23 Analog Comparator (ACMP) The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is higher. Inputs can either be one of the selectable internal references or from external pins. Response time and thereby also the current consumption can be configured by altering the current supply to the comparator.
3.1.24 Voltage Comparator (VCMP) The Voltage Supply Comparator is used to monitor the supply voltage from software. An interrupt can be generated when the supply falls below or rises above a programmable threshold. Response time and thereby also the current consumption can be configured by altering the current supply to the comparator.
silabs.com | Building a more connected world.
Rev. 2.30 | 15
EFM32LG Data Sheet
System Summary
3.1.25 Analog to Digital Converter (ADC)
The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to one million samples per second. The integrated input mux can select inputs from 8 external pins and 6 internal signals.
3.1.26 Digital to Analog Converter (DAC)
The Digital to Analog Converter (DAC) can convert a digital value to an analog output voltage. The DAC is fully differential rail-to-rail, with 12-bit resolution. It has two single-ended output buffers which can be combined into one differential output. The DAC may be used for a number of different applications such as sensor interfaces or sound output.
3.1.27 Operational Amplifier (OPAMP)
The EFM32LG features up to three Operational Amplifiers. The Operational Amplifier is a versatile general purpose amplifier with railto-rail differential input and rail-to-rail single-ended output. The input can be set to pin, DAC or OPAMP, whereas the output can be pin, OPAMP or ADC. The current is programmable and the OPAMP has various internal configurations such as unity gain, programmable gain using internal resistors etc.
3.1.28 Low Energy Sensor Interface (LESENSE)
The Low Energy Sensor Interface (LESENSETM), is a highly configurable sensor interface with support for up to 16 individually configurable sensors. By controlling the analog comparators and DAC, LESENSE is capable of supporting a wide range of sensors and measurement schemes, and can for instance measure LC sensors, resistive sensors and capacitive sensors. LESENSE also includes a programmable FSM which enables simple processing of measurement results without CPU intervention. LESENSE is available in energy mode EM2, in addition to EM0 and EM1, making it ideal for sensor monitoring in applications with a strict energy budget.
3.1.29 Backup Power Domain
The backup power domain is a separate power domain containing a Backup Real Time Counter, BURTC, and a set of retention registers, available in all energy modes. This power domain can be configured to automatically change power source to a backup battery when the main power drains out. The backup power domain enables the EFM32LG to keep track of time and retain data, even if the main power source should drain out.
3.1.30 Advanced Encryption Standard Accelerator (AES)
The AES accelerator performs AES encryption and decryption with 128-bit or 256-bit keys. Encrypting or decrypting one 128-bit data block takes 52 HFCORECLK cycles with 128-bit keys and 75 HFCORECLK cycles with 256-bit keys. The AES module is an AHB slave which enables efficient access to the data and key registers. All write accesses to the AES module must be 32-bit operations, i.e. 8- or 16-bit operations are not supported.
3.1.31 General Purpose Input/Output (GPIO)
In the EFM32LG, there are up to 93 General Purpose Input/Output (GPIO) pins, which are divided into ports with up to 16 pins each. These pins can individually be configured as either an output or input. More advanced configurations like open-drain, filtering and drive strength can also be configured individually for the pins. The GPIO pins can also be overridden by peripheral pin connections, like Timer PWM outputs or USART communication, which can be routed to several locations on the device. The GPIO supports up to 16 asynchronous external pin interrupts, which enables interrupts from any pin on the device. Also, the input value of a pin can be routed through the Peripheral Reflex System to other peripherals.
3.1.32 Liquid Crystal Display Driver (LCD)
The LCD driver is capable of driving a segmented LCD display with up to 8x36 segments. A voltage boost function enables it to provide the LCD display with higher voltage than the supply voltage for the device. In addition, an animation feature can run custom animations on the LCD display without any CPU intervention. The LCD driver can also remain active even in Energy Mode 2 and provides a Frame Counter interrupt that can wake-up the device on a regular basis for updating data.
3.2 Configuration Summary
The following sections provide device-specific features of the EFM32LG family of MCUs. These features are subsets of the full feature set described in the EFM32LG Reference Manual.
silabs.com | Building a more connected world.
Rev. 2.30 | 16
3.2.1 EFM32LG230 The following table describes device-specific implementation of the EFM32LG230 features.
Table 3.1. EFM32LG230 Configuration Summary
EFM32LG Data Sheet
System Summary
Module Cortex-M3 DBG MSC DMA RMU EMU CMU WDOG PRS I2C0 I2C1 USART0 USART1 USART2 LEUART0 LEUART1 TIMER0 TIMER1 TIMER2 TIMER3 RTC BURTC LETIMER0 PCNT0 PCNT1 PCNT2 ACMP0 ACMP1 VCMP ADC0 DAC0 OPAMP
Configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration with IrDA Full configuration with I2S Full configuration with I2S Full configuration Full configuration Full configuration with DTI Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration, 16-bit count register Full configuration, 8-bit count register Full configuration, 8-bit count register Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration
AES
Full configuration
silabs.com | Building a more connected world.
Pin Connections NA DBG_SWCLK, DBG_SWDIO, DBG_SWO NA NA NA NA CMU_OUT0, CMU_OUT1 NA NA I2C0_SDA, I2C0_SCL I2C1_SDA, I2C1_SCL US0_TX, US0_RX. US0_CLK, US0_CS US1_TX, US1_RX, US1_CLK, US1_CS US2_TX, US2_RX, US2_CLK, US2_CS LEU0_TX, LEU0_RX LEU1_TX, LEU1_RX TIM0_CC[2:0], TIM0_CDTI[2:0] TIM1_CC[2:0] TIM2_CC[2:0] TIM3_CC[2:0] NA NA LET0_O[1:0] PCNT0_S[1:0] PCNT1_S[1:0] PCNT2_S[1:0] ACMP0_CH[7:0], ACMP0_O ACMP1_CH[7:0], ACMP1_O NA ADC0_CH[7:0] DAC0_OUT[1:0], DAC0_OUTxALT Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx NA
Rev. 2.30 | 17
Module GPIO
Configuration 56 pins
EFM32LG Data Sheet
System Summary
Pin Connections Available pins are shown in 5.1.3 GPIO Pinout Overview
silabs.com | Building a more connected world.
Rev. 2.30 | 18
3.2.2 EFM32LG232 The following table describes device-specific implementation of the EFM32LG232 features.
Table 3.2. EFM32LG232 Configuration Summary
EFM32LG Data Sheet
System Summary
Module Cortex-M3 DBG MSC DMA RMU EMU CMU WDOG PRS I2C0 I2C1 USART0 USART1 USART2 LEUART0 LEUART1 TIMER0 TIMER1 TIMER2 TIMER3 RTC BURTC LETIMER0 PCNT0 PCNT1 PCNT2 ACMP0 ACMP1 VCMP ADC0 DAC0 OPAMP
Configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration with IrDA Full configuration with I2S Full configuration with I2S Full configuration Full configuration Full configuration with DTI Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration, 16-bit count register Full configuration, 8-bit count register Full configuration, 8-bit count register Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration
AES
Full configuration
silabs.com | Building a more connected world.
Pin Connections NA DBG_SWCLK, DBG_SWDIO, DBG_SWO NA NA NA NA CMU_OUT0, CMU_OUT1 NA NA I2C0_SDA, I2C0_SCL I2C1_SDA, I2C1_SCL US0_TX, US0_RX. US0_CLK, US0_CS US1_TX, US1_RX, US1_CLK, US1_CS US2_TX, US2_RX, US2_CLK, US2_CS LEU0_TX, LEU0_RX LEU1_TX, LEU1_RX TIM0_CC[2:0], TIM0_CDTI[2:0] TIM1_CC[2:0] TIM2_CC[2:0] TIM3_CC[2:0] NA NA LET0_O[1:0] PCNT0_S[1:0] PCNT1_S[1:0] PCNT2_S[1:0] ACMP0_CH[7:0], ACMP0_O ACMP1_CH[7:0], ACMP1_O NA ADC0_CH[7:0] DAC0_OUT[1:0], DAC0_OUTxALT Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx NA
Rev. 2.30 | 19
Module GPIO
Configuration 53 pins
EFM32LG Data Sheet
System Summary
Pin Connections Available pins are shown in 5.2.3 GPIO Pinout Overview
silabs.com | Building a more connected world.
Rev. 2.30 | 20
3.2.3 EFM32LG280 The following table describes device-specific implementation of the EFM32LG280 features.
Table 3.3. EFM32LG280 Configuration Summary
EFM32LG Data Sheet
System Summary
Module Cortex-M3 DBG MSC DMA RMU EMU CMU WDOG PRS EBI
Configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration
I2C0 I2C1 USART0 USART1 USART2 UART0 UART1 LEUART0 LEUART1 TIMER0 TIMER1 TIMER2 TIMER3 RTC BURTC LETIMER0 PCNT0 PCNT1 PCNT2 ACMP0 ACMP1 VCMP
Full configuration Full configuration Full configuration with IrDA Full configuration with I2S Full configuration with I2S Full configuration Full configuration Full configuration Full configuration Full configuration with DTI Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration, 16-bit count register Full configuration, 8-bit count register Full configuration, 8-bit count register Full configuration Full configuration Full configuration
Pin Connections NA DBG_SWCLK, DBG_SWDIO, DBG_SWO NA NA NA NA CMU_OUT0, CMU_OUT1 NA NA EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0], EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC, EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn I2C0_SDA, I2C0_SCL I2C1_SDA, I2C1_SCL US0_TX, US0_RX. US0_CLK, US0_CS US1_TX, US1_RX, US1_CLK, US1_CS US2_TX, US2_RX, US2_CLK, US2_CS U0_TX, U0_RX U1_TX, U1_RX LEU0_TX, LEU0_RX LEU1_TX, LEU1_RX TIM0_CC[2:0], TIM0_CDTI[2:0] TIM1_CC[2:0] TIM2_CC[2:0] TIM3_CC[2:0] NA NA LET0_O[1:0] PCNT0_S[1:0] PCNT1_S[1:0] PCNT2_S[1:0] ACMP0_CH[7:0], ACMP0_O ACMP1_CH[7:0], ACMP1_O NA
silabs.com | Building a more connected world.
Rev. 2.30 | 21
Module ADC0 DAC0 OPAMP
AES GPIO
Configuration Full configuration Full configuration Full configuration
Full configuration 85 pins
EFM32LG Data Sheet
System Summary
Pin Connections ADC0_CH[7:0] DAC0_OUT[1:0], DAC0_OUTxALT Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx NA Available pins are shown in 5.3.3 GPIO Pinout Overview
silabs.com | Building a more connected world.
Rev. 2.30 | 22
3.2.4 EFM32LG290 The following table describes device-specific implementation of the EFM32LG290 features.
Table 3.4. EFM32LG290 Configuration Summary
EFM32LG Data Sheet
System Summary
Module Cortex-M3 DBG MSC DMA RMU EMU CMU WDOG PRS EBI
Configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration
I2C0 I2C1 USART0 USART1 USART2 UART0 UART1 LEUART0 LEUART1 TIMER0 TIMER1 TIMER2 TIMER3 RTC BURTC LETIMER0 PCNT0 PCNT1 PCNT2 ACMP0 ACMP1 VCMP
Full configuration Full configuration Full configuration with IrDA Full configuration with I2S Full configuration with I2S Full configuration Full configuration Full configuration Full configuration Full configuration with DTI Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration, 16-bit count register Full configuration, 8-bit count register Full configuration, 8-bit count register Full configuration Full configuration Full configuration
Pin Connections NA DBG_SWCLK, DBG_SWDIO, DBG_SWO NA NA NA NA CMU_OUT0, CMU_OUT1 NA NA EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0], EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC, EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn I2C0_SDA, I2C0_SCL I2C1_SDA, I2C1_SCL US0_TX, US0_RX. US0_CLK, US0_CS US1_TX, US1_RX, US1_CLK, US1_CS US2_TX, US2_RX, US2_CLK, US2_CS U0_TX, U0_RX U1_TX, U1_RX LEU0_TX, LEU0_RX LEU1_TX, LEU1_RX TIM0_CC[2:0], TIM0_CDTI[2:0] TIM1_CC[2:0] TIM2_CC[2:0] TIM3_CC[2:0] NA NA LET0_O[1:0] PCNT0_S[1:0] PCNT1_S[1:0] PCNT2_S[1:0] ACMP0_CH[7:0], ACMP0_O ACMP1_CH[7:0], ACMP1_O NA
silabs.com | Building a more connected world.
Rev. 2.30 | 23
Module ADC0 DAC0 OPAMP
AES GPIO
Configuration Full configuration Full configuration Full configuration
Full configuration 90 pins
EFM32LG Data Sheet
System Summary
Pin Connections ADC0_CH[7:0] DAC0_OUT[1:0], DAC0_OUTxALT Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx NA Available pins are shown in 5.4.3 GPIO Pinout Overview
silabs.com | Building a more connected world.
Rev. 2.30 | 24
3.2.5 EFM32LG295 The following table describes device-specific implementation of the EFM32LG295 features.
Table 3.5. EFM32LG295 Configuration Summary
EFM32LG Data Sheet
System Summary
Module Cortex-M3 DBG MSC DMA RMU EMU CMU WDOG PRS EBI
Configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration
I2C0 I2C1 USART0 USART1 USART2 UART0 UART1 LEUART0 LEUART1 TIMER0 TIMER1 TIMER2 TIMER3 RTC BURTC LETIMER0 PCNT0 PCNT1 PCNT2 ACMP0 ACMP1 VCMP
Full configuration Full configuration Full configuration with IrDA Full configuration with I2S Full configuration with I2S Full configuration Full configuration Full configuration Full configuration Full configuration with DTI Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration, 16-bit count register Full configuration, 8-bit count register Full configuration, 8-bit count register Full configuration Full configuration Full configuration
Pin Connections NA DBG_SWCLK, DBG_SWDIO, DBG_SWO NA NA NA NA CMU_OUT0, CMU_OUT1 NA NA EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0], EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC, EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn I2C0_SDA, I2C0_SCL I2C1_SDA, I2C1_SCL US0_TX, US0_RX. US0_CLK, US0_CS US1_TX, US1_RX, US1_CLK, US1_CS US2_TX, US2_RX, US2_CLK, US2_CS U0_TX, U0_RX U1_TX, U1_RX LEU0_TX, LEU0_RX LEU1_TX, LEU1_RX TIM0_CC[2:0], TIM0_CDTI[2:0] TIM1_CC[2:0] TIM2_CC[2:0] TIM3_CC[2:0] NA NA LET0_O[1:0] PCNT0_S[1:0] PCNT1_S[1:0] PCNT2_S[1:0] ACMP0_CH[7:0], ACMP0_O ACMP1_CH[7:0], ACMP1_O NA
silabs.com | Building a more connected world.
Rev. 2.30 | 25
Module ADC0 DAC0 OPAMP
AES GPIO
Configuration Full configuration Full configuration Full configuration
Full configuration 93 pins
EFM32LG Data Sheet
System Summary
Pin Connections ADC0_CH[7:0] DAC0_OUT[1:0], DAC0_OUTxALT Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx NA Available pins are shown in 5.5.3 GPIO Pinout Overview
silabs.com | Building a more connected world.
Rev. 2.30 | 26
3.2.6 EFM32LG330 The following table describes device-specific implementation of the EFM32LG330 features.
Table 3.6. EFM32LG330 Configuration Summary
EFM32LG Data Sheet
System Summary
Module Cortex-M3 DBG MSC DMA RMU EMU CMU WDOG PRS USB
Configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration
I2C0 I2C1 USART0 USART1 USART2 LEUART0 LEUART1 TIMER0 TIMER1 TIMER2 TIMER3 RTC BURTC LETIMER0 PCNT0 PCNT1 PCNT2 ACMP0 ACMP1 VCMP ADC0 DAC0
Full configuration Full configuration Full configuration with IrDA Full configuration with I2S Full configuration with I2S Full configuration Full configuration Full configuration with DTI Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration, 16-bit count register Full configuration, 8-bit count register Full configuration, 8-bit count register Full configuration Full configuration Full configuration Full configuration Full configuration
Pin Connections NA DBG_SWCLK, DBG_SWDIO, DBG_SWO NA NA NA NA CMU_OUT0, CMU_OUT1 NA NA USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM, USB_DMPU, USB_DP, USB_ID I2C0_SDA, I2C0_SCL I2C1_SDA, I2C1_SCL US0_TX, US0_RX. US0_CLK, US0_CS US1_TX, US1_RX, US1_CLK, US1_CS US2_TX, US2_RX, US2_CLK, US2_CS LEU0_TX, LEU0_RX LEU1_TX, LEU1_RX TIM0_CC[2:0], TIM0_CDTI[2:0] TIM1_CC[2:0] TIM2_CC[2:0] TIM3_CC[2:0] NA NA LET0_O[1:0] PCNT0_S[1:0] PCNT1_S[1:0] PCNT2_S[1:0] ACMP0_CH[7:0], ACMP0_O ACMP1_CH[3:0], ACMP1_O NA ADC0_CH[7:0] DAC0_OUT[1:0], DAC0_OUTxALT
silabs.com | Building a more connected world.
Rev. 2.30 | 27
Module OPAMP
AES GPIO
Configuration Full configuration
Full configuration 53 pins
EFM32LG Data Sheet
System Summary
Pin Connections Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx NA Available pins are shown in 5.6.3 GPIO Pinout Overview
silabs.com | Building a more connected world.
Rev. 2.30 | 28
3.2.7 EFM32LG332 The following table describes device-specific implementation of the EFM32LG332 features.
Table 3.7. EFM32LG332 Configuration Summary
EFM32LG Data Sheet
System Summary
Module Cortex-M3 DBG MSC DMA RMU EMU CMU WDOG PRS USB
Configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration
I2C0 I2C1 USART0 USART1 USART2 LEUART0 LEUART1 TIMER0 TIMER1 TIMER2 TIMER3 RTC BURTC LETIMER0 PCNT0 PCNT1 PCNT2 ACMP0 ACMP1 VCMP ADC0 DAC0
Full configuration Full configuration Full configuration with IrDA Full configuration with I2S Full configuration with I2S Full configuration Full configuration Full configuration with DTI Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration, 16-bit count register Full configuration, 8-bit count register Full configuration, 8-bit count register Full configuration Full configuration Full configuration Full configuration Full configuration
Pin Connections NA DBG_SWCLK, DBG_SWDIO, DBG_SWO NA NA NA NA CMU_OUT0, CMU_OUT1 NA NA USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM, USB_DMPU, USB_DP, USB_ID I2C0_SDA, I2C0_SCL I2C1_SDA, I2C1_SCL US0_TX, US0_RX. US0_CLK, US0_CS US1_TX, US1_RX, US1_CLK, US1_CS US2_TX, US2_RX, US2_CLK, US2_CS LEU0_TX, LEU0_RX LEU1_TX, LEU1_RX TIM0_CC[2:0], TIM0_CDTI[2:0] TIM1_CC[2:0] TIM2_CC[2:0] TIM3_CC[2:0] NA NA LET0_O[1:0] PCNT0_S[1:0] PCNT1_S[1:0] PCNT2_S[1:0] ACMP0_CH[7:0], ACMP0_O ACMP1_CH[3:0], ACMP1_O NA ADC0_CH[7:0] DAC0_OUT[1:0], DAC0_OUTxALT
silabs.com | Building a more connected world.
Rev. 2.30 | 29
Module OPAMP
AES GPIO
Configuration Full configuration
Full configuration 50 pins
EFM32LG Data Sheet
System Summary
Pin Connections Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx NA Available pins are shown in 5.7.3 GPIO Pinout Overview
silabs.com | Building a more connected world.
Rev. 2.30 | 30
3.2.8 EFM32LG360 The following table describes device-specific implementation of the EFM32LG360 features.
Table 3.8. EFM32LG360 Configuration Summary
EFM32LG Data Sheet
System Summary
Module Cortex-M3 DBG MSC DMA RMU EMU CMU WDOG PRS USB
Configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration
I2C0 I2C1 USART0 USART1 USART2 UART0 UART1 LEUART0 LEUART1 TIMER0 TIMER1 TIMER2 TIMER3 RTC BURTC LETIMER0 PCNT0 PCNT1 PCNT2 ACMP0 ACMP1 VCMP ADC0
Full configuration Full configuration Full configuration with IrDA Full configuration with I2S Full configuration with I2S Full configuration Full configuration Full configuration Full configuration Full configuration with DTI Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration, 16-bit count register Full configuration, 8-bit count register Full configuration, 8-bit count register Full configuration Full configuration Full configuration Full configuration
silabs.com | Building a more connected world.
Pin Connections NA DBG_SWCLK, DBG_SWDIO, DBG_SWO NA NA NA NA CMU_OUT0, CMU_OUT1 NA NA USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM, USB_DMPU, USB_DP, USB_ID I2C0_SDA, I2C0_SCL I2C1_SDA, I2C1_SCL US0_TX, US0_RX. US0_CLK, US0_CS US1_TX, US1_RX, US1_CLK, US1_CS US2_TX, US2_RX, US2_CLK, US2_CS U0_TX, U0_RX U1_TX, U1_RX LEU0_TX, LEU0_RX LEU1_TX, LEU1_RX TIM0_CC[2:0], TIM0_CDTI[2:0] TIM1_CC[2:0] TIM2_CC[2:0] TIM3_CC[2:0] NA NA LET0_O[1:0] PCNT0_S[1:0] PCNT1_S[1:0] PCNT2_S[1:0] ACMP0_CH[7:0], ACMP0_O ACMP1_CH[7:0], ACMP1_O NA ADC0_CH[7:0]
Rev. 2.30 | 31
Module DAC0 OPAMP
AES GPIO
Configuration Full configuration Full configuration
Full configuration 65 pins
EFM32LG Data Sheet
System Summary
Pin Connections DAC0_OUT[1:0], DAC0_OUTxALT Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx NA Available pins are shown in 5.8.3 GPIO Pinout Overview
silabs.com | Building a more connected world.
Rev. 2.30 | 32
3.2.9 EFM32LG380 The following table describes device-specific implementation of the EFM32LG380 features.
Table 3.9. EFM32LG380 Configuration Summary
EFM32LG Data Sheet
System Summary
Module Cortex-M3 DBG MSC DMA RMU EMU CMU WDOG PRS USB
Configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration
EBI
Full configuration
I2C0 I2C1 USART0 USART1 USART2 UART0 UART1 LEUART0 LEUART1 TIMER0 TIMER1 TIMER2 TIMER3 RTC BURTC LETIMER0 PCNT0 PCNT1 PCNT2 ACMP0
Full configuration Full configuration Full configuration with IrDA Full configuration with I2S Full configuration with I2S Full configuration Full configuration Full configuration Full configuration Full configuration with DTI Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration, 16-bit count register Full configuration, 8-bit count register Full configuration, 8-bit count register Full configuration
Pin Connections NA DBG_SWCLK, DBG_SWDIO, DBG_SWO NA NA NA NA CMU_OUT0, CMU_OUT1 NA NA USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM, USB_DMPU, USB_DP, USB_ID EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0], EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC, EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn I2C0_SDA, I2C0_SCL I2C1_SDA, I2C1_SCL US0_TX, US0_RX. US0_CLK, US0_CS US1_TX, US1_RX, US1_CLK, US1_CS US2_TX, US2_RX, US2_CLK, US2_CS U0_TX, U0_RX U1_TX, U1_RX LEU0_TX, LEU0_RX LEU1_TX, LEU1_RX TIM0_CC[2:0], TIM0_CDTI[2:0] TIM1_CC[2:0] TIM2_CC[2:0] TIM3_CC[2:0] NA NA LET0_O[1:0] PCNT0_S[1:0] PCNT1_S[1:0] PCNT2_S[1:0] ACMP0_CH[7:0], ACMP0_O
silabs.com | Building a more connected world.
Rev. 2.30 | 33
Module ACMP1 VCMP ADC0 DAC0 OPAMP
AES GPIO
Configuration Full configuration Full configuration Full configuration Full configuration Full configuration
Full configuration 83 pins
EFM32LG Data Sheet
System Summary
Pin Connections ACMP1_CH[3:0], ACMP1_O NA ADC0_CH[7:0] DAC0_OUT[1:0], DAC0_OUTxALT Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx NA Available pins are shown in 5.9.3 GPIO Pinout Overview
silabs.com | Building a more connected world.
Rev. 2.30 | 34
3.2.10 EFM32LG390 The following table describes device-specific implementation of the EFM32LG390 features.
Table 3.10. EFM32LG390 Configuration Summary
EFM32LG Data Sheet
System Summary
Module Cortex-M3 DBG MSC DMA RMU EMU CMU WDOG PRS USB
Configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration
EBI
Full configuration
I2C0 I2C1 USART0 USART1 USART2 UART0 UART1 LEUART0 LEUART1 TIMER0 TIMER1 TIMER2 TIMER3 RTC BURTC LETIMER0 PCNT0 PCNT1 PCNT2 ACMP0
Full configuration Full configuration Full configuration with IrDA Full configuration with I2S Full configuration with I2S Full configuration Full configuration Full configuration Full configuration Full configuration with DTI Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration, 16-bit count register Full configuration, 8-bit count register Full configuration, 8-bit count register Full configuration
Pin Connections NA DBG_SWCLK, DBG_SWDIO, DBG_SWO NA NA NA NA CMU_OUT0, CMU_OUT1 NA NA USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM, USB_DMPU, USB_DP, USB_ID EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0], EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC, EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn I2C0_SDA, I2C0_SCL I2C1_SDA, I2C1_SCL US0_TX, US0_RX. US0_CLK, US0_CS US1_TX, US1_RX, US1_CLK, US1_CS US2_TX, US2_RX, US2_CLK, US2_CS U0_TX, U0_RX U1_TX, U1_RX LEU0_TX, LEU0_RX LEU1_TX, LEU1_RX TIM0_CC[2:0], TIM0_CDTI[2:0] TIM1_CC[2:0] TIM2_CC[2:0] TIM3_CC[2:0] NA NA LET0_O[1:0] PCNT0_S[1:0] PCNT1_S[1:0] PCNT2_S[1:0] ACMP0_CH[7:0], ACMP0_O
silabs.com | Building a more connected world.
Rev. 2.30 | 35
Module ACMP1 VCMP ADC0 DAC0 OPAMP
AES GPIO
Configuration Full configuration Full configuration Full configuration Full configuration Full configuration
Full configuration 86 pins
EFM32LG Data Sheet
System Summary
Pin Connections ACMP1_CH[3:0], ACMP1_O NA ADC0_CH[7:0] DAC0_OUT[1:0], DAC0_OUTxALT Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx NA Available pins are shown in 5.10.3 GPIO Pinout Overview
silabs.com | Building a more connected world.
Rev. 2.30 | 36
3.2.11 EFM32LG395 The following table describes device-specific implementation of the EFM32LG395 features.
Table 3.11. EFM32LG395 Configuration Summary
EFM32LG Data Sheet
System Summary
Module Cortex-M3 DBG MSC DMA RMU EMU CMU WDOG PRS USB
Configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration
EBI
Full configuration
I2C0 I2C1 USART0 USART1 USART2 UART0 UART1 LEUART0 LEUART1 TIMER0 TIMER1 TIMER2 TIMER3 RTC BURTC LETIMER0 PCNT0 PCNT1 PCNT2 ACMP0
Full configuration Full configuration Full configuration with IrDA Full configuration with I2S Full configuration with I2S Full configuration Full configuration Full configuration Full configuration Full configuration with DTI Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration, 16-bit count register Full configuration, 8-bit count register Full configuration, 8-bit count register Full configuration
Pin Connections NA DBG_SWCLK, DBG_SWDIO, DBG_SWO NA NA NA NA CMU_OUT0, CMU_OUT1 NA NA USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM, USB_DMPU, USB_DP, USB_ID EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0], EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC, EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn I2C0_SDA, I2C0_SCL I2C1_SDA, I2C1_SCL US0_TX, US0_RX. US0_CLK, US0_CS US1_TX, US1_RX, US1_CLK, US1_CS US2_TX, US2_RX, US2_CLK, US2_CS U0_TX, U0_RX U1_TX, U1_RX LEU0_TX, LEU0_RX LEU1_TX, LEU1_RX TIM0_CC[2:0], TIM0_CDTI[2:0] TIM1_CC[2:0] TIM2_CC[2:0] TIM3_CC[2:0] NA NA LET0_O[1:0] PCNT0_S[1:0] PCNT1_S[1:0] PCNT2_S[1:0] ACMP0_CH[7:0], ACMP0_O
silabs.com | Building a more connected world.
Rev. 2.30 | 37
Module ACMP1 VCMP ADC0 DAC0 OPAMP
AES GPIO
Configuration Full configuration Full configuration Full configuration Full configuration Full configuration
Full configuration 93 pins
EFM32LG Data Sheet
System Summary
Pin Connections ACMP1_CH[7:0], ACMP1_O NA ADC0_CH[7:0] DAC0_OUT[1:0], DAC0_OUTxALT Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx NA Available pins are shown in 5.11.3 GPIO Pinout Overview
silabs.com | Building a more connected world.
Rev. 2.30 | 38
3.2.12 EFM32LG840 The following table describes device-specific implementation of the EFM32LG840 features.
Table 3.12. EFM32LG840 Configuration Summary
EFM32LG Data Sheet
System Summary
Module Cortex-M3 DBG MSC DMA RMU EMU CMU WDOG PRS I2C0 I2C1 USART0 USART1 USART2 LEUART0 LEUART1 TIMER0 TIMER1 TIMER2 TIMER3 RTC BURTC LETIMER0 PCNT0 PCNT1 PCNT2 ACMP0 ACMP1 VCMP ADC0 DAC0 OPAMP
Configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration with IrDA Full configuration with I2S Full configuration with I2S Full configuration Full configuration Full configuration with DTI Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration, 16-bit count register Full configuration, 8-bit count register Full configuration, 8-bit count register Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration
AES
Full configuration
silabs.com | Building a more connected world.
Pin Connections NA DBG_SWCLK, DBG_SWDIO, DBG_SWO NA NA NA NA CMU_OUT0, CMU_OUT1 NA NA I2C0_SDA, I2C0_SCL I2C1_SDA, I2C1_SCL US0_TX, US0_RX. US0_CLK, US0_CS US1_TX, US1_RX, US1_CLK, US1_CS US2_TX, US2_RX, US2_CLK, US2_CS LEU0_TX, LEU0_RX LEU1_TX, LEU1_RX TIM0_CC[2:0], TIM0_CDTI[2:0] TIM1_CC[2:0] TIM2_CC[2:0] TIM3_CC[2:0] NA NA LET0_O[1:0] PCNT0_S[1:0] PCNT1_S[1:0] PCNT2_S[1:0] ACMP0_CH[7:4], ACMP0_O ACMP1_CH[7:4], ACMP1_O NA ADC0_CH[7:0] DAC0_OUT[1:0], DAC0_OUTxALT Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx NA
Rev. 2.30 | 39
Module GPIO LCD
Configuration 56 pins Full configuration
EFM32LG Data Sheet
System Summary
Pin Connections Available pins are shown in 5.12.3 GPIO Pinout Overview LCD_SEG[19:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N, LCD_BEXT
silabs.com | Building a more connected world.
Rev. 2.30 | 40
3.2.13 EFM32LG842 The following table describes device-specific implementation of the EFM32LG842 features.
Table 3.13. EFM32LG842 Configuration Summary
EFM32LG Data Sheet
System Summary
Module Cortex-M3 DBG MSC DMA RMU EMU CMU WDOG PRS I2C0 I2C1 USART0 USART1 USART2 LEUART0 LEUART1 TIMER0 TIMER1 TIMER2 TIMER3 RTC BURTC LETIMER0 PCNT0 PCNT1 PCNT2 ACMP0 ACMP1 VCMP ADC0 DAC0 OPAMP
Configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration with IrDA Full configuration with I2S Full configuration with I2S Full configuration Full configuration Full configuration with DTI Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration, 16-bit count register Full configuration, 8-bit count register Full configuration, 8-bit count register Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration
AES
Full configuration
silabs.com | Building a more connected world.
Pin Connections NA DBG_SWCLK, DBG_SWDIO, DBG_SWO NA NA NA NA CMU_OUT0, CMU_OUT1 NA NA I2C0_SDA, I2C0_SCL I2C1_SDA, I2C1_SCL US0_TX, US0_RX. US0_CLK, US0_CS US1_TX, US1_RX, US1_CLK, US1_CS US2_TX, US2_RX, US2_CLK, US2_CS LEU0_TX, LEU0_RX LEU1_TX, LEU1_RX TIM0_CC[2:0], TIM0_CDTI[2:0] TIM1_CC[2:0] TIM2_CC[2:0] TIM3_CC[2:0] NA NA LET0_O[1:0] PCNT0_S[1:0] PCNT1_S[1:0] PCNT2_S[1:0] ACMP0_CH[7:4], ACMP0_O ACMP1_CH[7:4], ACMP1_O NA ADC0_CH[7:0] DAC0_OUT[1:0], DAC0_OUTxALT Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx NA
Rev. 2.30 | 41
Module GPIO LCD
Configuration 53 pins Full configuration
EFM32LG Data Sheet
System Summary
Pin Connections Available pins are shown in 5.13.3 GPIO Pinout Overview LCD_SEG[17:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N, LCD_BEXT
silabs.com | Building a more connected world.
Rev. 2.30 | 42
3.2.14 EFM32LG880 The following table describes device-specific implementation of the EFM32LG880 features.
Table 3.14. EFM32LG880 Configuration Summary
EFM32LG Data Sheet
System Summary
Module Cortex-M3 DBG MSC DMA RMU EMU CMU WDOG PRS EBI
Configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration
I2C0 I2C1 USART0 USART1 USART2 UART0 UART1 LEUART0 LEUART1 TIMER0 TIMER1 TIMER2 TIMER3 RTC BURTC LETIMER0 PCNT0 PCNT1 PCNT2 ACMP0 ACMP1 VCMP
Full configuration Full configuration Full configuration with IrDA Full configuration with I2S Full configuration with I2S Full configuration Full configuration Full configuration Full configuration Full configuration with DTI Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration, 16-bit count register Full configuration, 8-bit count register Full configuration, 8-bit count register Full configuration Full configuration Full configuration
Pin Connections NA DBG_SWCLK, DBG_SWDIO, DBG_SWO NA NA NA NA CMU_OUT0, CMU_OUT1 NA NA EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0], EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC, EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn I2C0_SDA, I2C0_SCL I2C1_SDA, I2C1_SCL US0_TX, US0_RX. US0_CLK, US0_CS US1_TX, US1_RX, US1_CLK, US1_CS US2_TX, US2_RX, US2_CLK, US2_CS U0_TX, U0_RX U1_TX, U1_RX LEU0_TX, LEU0_RX LEU1_TX, LEU1_RX TIM0_CC[2:0], TIM0_CDTI[2:0] TIM1_CC[2:0] TIM2_CC[2:0] TIM3_CC[2:0] NA NA LET0_O[1:0] PCNT0_S[1:0] PCNT1_S[1:0] PCNT2_S[1:0] ACMP0_CH[7:0], ACMP0_O ACMP1_CH[7:0], ACMP1_O NA
silabs.com | Building a more connected world.
Rev. 2.30 | 43
Module ADC0 DAC0 OPAMP
AES GPIO LCD
Configuration Full configuration Full configuration Full configuration
Full configuration 85 pins Full configuration
EFM32LG Data Sheet
System Summary
Pin Connections ADC0_CH[7:0] DAC0_OUT[1:0], DAC0_OUTxALT Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx NA Available pins are shown in 5.14.3 GPIO Pinout Overview LCD_SEG[35:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N, LCD_BEXT
silabs.com | Building a more connected world.
Rev. 2.30 | 44
3.2.15 EFM32LG890 The following table describes device-specific implementation of the EFM32LG890 features.
Table 3.15. EFM32LG890 Configuration Summary
EFM32LG Data Sheet
System Summary
Module Cortex-M3 DBG MSC DMA RMU EMU CMU WDOG PRS EBI
Configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration
I2C0 I2C1 USART0 USART1 USART2 UART0 UART1 LEUART0 LEUART1 TIMER0 TIMER1 TIMER2 TIMER3 RTC BURTC LETIMER0 PCNT0 PCNT1 PCNT2 ACMP0 ACMP1 VCMP
Full configuration Full configuration Full configuration with IrDA Full configuration with I2S Full configuration with I2S Full configuration Full configuration Full configuration Full configuration Full configuration with DTI Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration, 16-bit count register Full configuration, 8-bit count register Full configuration, 8-bit count register Full configuration Full configuration Full configuration
Pin Connections NA DBG_SWCLK, DBG_SWDIO, DBG_SWO NA NA NA NA CMU_OUT0, CMU_OUT1 NA NA EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0], EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC, EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn I2C0_SDA, I2C0_SCL I2C1_SDA, I2C1_SCL US0_TX, US0_RX. US0_CLK, US0_CS US1_TX, US1_RX, US1_CLK, US1_CS US2_TX, US2_RX, US2_CLK, US2_CS U0_TX, U0_RX U1_TX, U1_RX LEU0_TX, LEU0_RX LEU1_TX, LEU1_RX TIM0_CC[2:0], TIM0_CDTI[2:0] TIM1_CC[2:0] TIM2_CC[2:0] TIM3_CC[2:0] NA NA LET0_O[1:0] PCNT0_S[1:0] PCNT1_S[1:0] PCNT2_S[1:0] ACMP0_CH[7:0], ACMP0_O ACMP1_CH[7:0], ACMP1_O NA
silabs.com | Building a more connected world.
Rev. 2.30 | 45
Module ADC0 DAC0 OPAMP
AES GPIO LCD
Configuration Full configuration Full configuration Full configuration
Full configuration 90 pins Full configuration
EFM32LG Data Sheet
System Summary
Pin Connections ADC0_CH[7:0] DAC0_OUT[1:0], DAC0_OUTxALT Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx NA Available pins are shown in 5.15.3 GPIO Pinout Overview LCD_SEG[35:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N, LCD_BEXT
silabs.com | Building a more connected world.
Rev. 2.30 | 46
3.2.16 EFM32LG895 The following table describes device-specific implementation of the EFM32LG895 features.
Table 3.16. EFM32LG895 Configuration Summary
EFM32LG Data Sheet
System Summary
Module Cortex-M3 DBG MSC DMA RMU EMU CMU WDOG PRS EBI
Configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration
I2C0 I2C1 USART0 USART1 USART2 UART0 UART1 LEUART0 LEUART1 TIMER0 TIMER1 TIMER2 TIMER3 RTC BURTC LETIMER0 PCNT0 PCNT1 PCNT2 ACMP0 ACMP1 VCMP
Full configuration Full configuration Full configuration with IrDA Full configuration with I2S Full configuration with I2S Full configuration Full configuration Full configuration Full configuration Full configuration with DTI Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration, 16-bit count register Full configuration, 8-bit count register Full configuration, 8-bit count register Full configuration Full configuration Full configuration
Pin Connections NA DBG_SWCLK, DBG_SWDIO, DBG_SWO NA NA NA NA CMU_OUT0, CMU_OUT1 NA NA EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0], EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC, EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn I2C0_SDA, I2C0_SCL I2C1_SDA, I2C1_SCL US0_TX, US0_RX. US0_CLK, US0_CS US1_TX, US1_RX, US1_CLK, US1_CS US2_TX, US2_RX, US2_CLK, US2_CS U0_TX, U0_RX U1_TX, U1_RX LEU0_TX, LEU0_RX LEU1_TX, LEU1_RX TIM0_CC[2:0], TIM0_CDTI[2:0] TIM1_CC[2:0] TIM2_CC[2:0] TIM3_CC[2:0] NA NA LET0_O[1:0] PCNT0_S[1:0] PCNT1_S[1:0] PCNT2_S[1:0] ACMP0_CH[7:0], ACMP0_O ACMP1_CH[7:0], ACMP1_O NA
silabs.com | Building a more connected world.
Rev. 2.30 | 47
Module ADC0 DAC0 OPAMP
AES GPIO LCD
Configuration Full configuration Full configuration Full configuration
Full configuration 93 pins Full configuration
EFM32LG Data Sheet
System Summary
Pin Connections ADC0_CH[7:0] DAC0_OUT[1:0], DAC0_OUTxALT Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx NA Available pins are shown in Table 4.3 (p. 70) LCD_SEG[35:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N, LCD_BEXT
silabs.com | Building a more connected world.
Rev. 2.30 | 48
3.2.17 EFM32LG900 The following table describes device-specific implementation of the EFM32LG900 features.
Table 3.17. EFM32LG900 Configuration Summary
EFM32LG Data Sheet
System Summary
Module Configuration
Pin Connections
Cortex-M3 Full configuration
NA
DBG
Full configuration
DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC
Full configuration
NA
DMA
Full configuration
NA
RMU
Full configuration
NA
EMU
Full configuration
NA
CMU
Full configuration
CMU_OUT0, CMU_OUT1
WDOG Full configuration
NA
PRS
Full configuration
NA
USB
Full configuration
USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM, USB_DMPU, USB_DP, USB_ID
EBI
Full configuration
EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0], EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC, EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn
I2C0
Full configuration
I2C0_SDA, I2C0_SCL
I2C1
Full configuration
I2C1_SDA, I2C1_SCL
USART0 Full configuration with IrDA
US0_TX, US0_RX. US0_CLK, US0_CS
USART1 Full configuration with I2S
US1_TX, US1_RX, US1_CLK, US1_CS
USART2 Full configuration with I2S
US2_TX, US2_RX, US2_CLK, US2_CS
UART0 Full configuration
U0_TX, U0_RX
UART1 Full configuration
U1_TX, U1_RX
LEUART0 Full configuration
LEU0_TX, LEU0_RX
LEUART1 Full configuration
LEU1_TX, LEU1_RX
TIMER0 Full configuration with DTI
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1 Full configuration
TIM1_CC[2:0]
TIMER2 Full configuration
TIM2_CC[2:0]
TIMER3 Full configuration
TIM3_CC[2:0]
RTC
Full configuration
NA
BURTC Full configuration
NA
LETIMER0 Full configuration
LET0_O[1:0]
PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0]
PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0]
PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0]
ACMP0 Full configuration
ACMP0_CH[7:0], ACMP0_O
silabs.com | Building a more connected world.
Rev. 2.30 | 49
Module ACMP1 VCMP ADC0 DAC0 OPAMP AES GPIO LCD
Configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration 93 pins Full configuration
EFM32LG Data Sheet
System Summary
Pin Connections ACMP1_CH[7:0], ACMP1_O NA ADC0_CH[7:0] DAC0_OUT[1:0], DAC0_OUTxALT Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx NA Available pins are shown in 5.17.3 GPIO Pinout Overview LCD_SEG[35:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N, LCD_BEXT
silabs.com | Building a more connected world.
Rev. 2.30 | 50
3.2.18 EFM32LG940 The following table describes device-specific implementation of the EFM32LG940 features.
Table 3.18. EFM32LG940 Configuration Summary
EFM32LG Data Sheet
System Summary
Module Cortex-M3 DBG MSC DMA RMU EMU CMU WDOG PRS USB
Configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration
I2C0 I2C1 USART0 USART1 USART2 LEUART0 LEUART1 TIMER0 TIMER1 TIMER2 TIMER3 RTC BURTC LETIMER0 PCNT0 PCNT1 PCNT2 ACMP0 ACMP1 VCMP ADC0 DAC0
Full configuration Full configuration Full configuration with IrDA Full configuration with I2S Full configuration with I2S Full configuration Full configuration Full configuration with DTI Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration, 16-bit count register Full configuration, 8-bit count register Full configuration, 8-bit count register Full configuration Full configuration Full configuration Full configuration Full configuration
Pin Connections NA DBG_SWCLK, DBG_SWDIO, DBG_SWO NA NA NA NA CMU_OUT0, CMU_OUT1 NA NA USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM, USB_DMPU, USB_DP, USB_ID I2C0_SDA, I2C0_SCL I2C1_SDA, I2C1_SCL US0_TX, US0_RX. US0_CLK, US0_CS US1_TX, US1_RX, US1_CLK, US1_CS US2_TX, US2_RX, US2_CLK, US2_CS LEU0_TX, LEU0_RX LEU1_TX, LEU1_RX TIM0_CC[2:0], TIM0_CDTI[2:0] TIM1_CC[2:0] TIM2_CC[2:0] TIM3_CC[2:0] NA NA LET0_O[1:0] PCNT0_S[1:0] PCNT1_S[1:0] PCNT2_S[1:0] ACMP0_CH[7:4], ACMP0_O ACMP1_O NA ADC0_CH[7:0] DAC0_OUT[1:0], DAC0_OUTxALT
silabs.com | Building a more connected world.
Rev. 2.30 | 51
Module OPAMP
AES GPIO LCD
Configuration Full configuration
Full configuration 53 pins Full configuration
EFM32LG Data Sheet
System Summary
Pin Connections Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx
NA
Available pins are shown in 5.18.3 GPIO Pinout Overview
LCD_SEG[17:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N, LCD_BEXT
silabs.com | Building a more connected world.
Rev. 2.30 | 52
3.2.19 EFM32LG942 The following table describes device-specific implementation of the EFM32LG942 features.
Table 3.19. EFM32LG942 Configuration Summary
EFM32LG Data Sheet
System Summary
Module Cortex-M3 DBG MSC DMA RMU EMU CMU WDOG PRS USB
Configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration
I2C0 I2C1 USART0 USART1 USART2 LEUART0 LEUART1 TIMER0 TIMER1 TIMER2 TIMER3 RTC BURTC LETIMER0 PCNT0 PCNT1 PCNT2 ACMP0 ACMP1 VCMP ADC0 DAC0
Full configuration Full configuration Full configuration with IrDA Full configuration with I2S Full configuration with I2S Full configuration Full configuration Full configuration with DTI Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration, 16-bit count register Full configuration, 8-bit count register Full configuration, 8-bit count register Full configuration Full configuration Full configuration Full configuration Full configuration
Pin Connections NA DBG_SWCLK, DBG_SWDIO, DBG_SWO NA NA NA NA CMU_OUT0, CMU_OUT1 NA NA USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM, USB_DMPU, USB_DP, USB_ID I2C0_SDA, I2C0_SCL I2C1_SDA, I2C1_SCL US0_TX, US0_RX. US0_CLK, US0_CS US1_TX, US1_RX, US1_CLK, US1_CS US2_TX, US2_RX, US2_CLK, US2_CS LEU0_TX, LEU0_RX LEU1_TX, LEU1_RX TIM0_CC[2:0], TIM0_CDTI[2:0] TIM1_CC[2:0] TIM2_CC[2:0] TIM3_CC[2:0] NA NA LET0_O[1:0] PCNT0_S[1:0] PCNT1_S[1:0] PCNT2_S[1:0] ACMP0_CH[7:4], ACMP0_O ACMP1_O NA ADC0_CH[7:0] DAC0_OUT[1:0], DAC0_OUTxALT
silabs.com | Building a more connected world.
Rev. 2.30 | 53
Module OPAMP
AES GPIO LCD
Configuration Full configuration
Full configuration 50 pins Full configuration
EFM32LG Data Sheet
System Summary
Pin Connections Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx
NA
Available pins are shown in 5.19.3 GPIO Pinout Overview
LCD_SEG[15:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N, LCD_BEXT
silabs.com | Building a more connected world.
Rev. 2.30 | 54
3.2.20 EFM32LG980 The following table describes device-specific implementation of the EFM32LG980 features.
Table 3.20. EFM32LG980 Configuration Summary
EFM32LG Data Sheet
System Summary
Module Cortex-M3 DBG MSC DMA RMU EMU CMU WDOG PRS USB
Configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration
EBI
Full configuration
I2C0 I2C1 USART0 USART1 USART2 UART0 UART1 LEUART0 LEUART1 TIMER0 TIMER1 TIMER2 TIMER3 RTC BURTC LETIMER0 PCNT0 PCNT1 PCNT2 ACMP0
Full configuration Full configuration Full configuration with IrDA Full configuration with I2S Full configuration with I2S Full configuration Full configuration Full configuration Full configuration Full configuration with DTI Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration, 16-bit count register Full configuration, 8-bit count register Full configuration, 8-bit count register Full configuration
Pin Connections NA DBG_SWCLK, DBG_SWDIO, DBG_SWO NA NA NA NA CMU_OUT0, CMU_OUT1 NA NA USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM, USB_DMPU, USB_DP, USB_ID EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0], EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC, EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn I2C0_SDA, I2C0_SCL I2C1_SDA, I2C1_SCL US0_TX, US0_RX. US0_CLK, US0_CS US1_TX, US1_RX, US1_CLK, US1_CS US2_TX, US2_RX, US2_CLK, US2_CS U0_TX, U0_RX U1_TX, U1_RX LEU0_TX, LEU0_RX LEU1_TX, LEU1_RX TIM0_CC[2:0], TIM0_CDTI[2:0] TIM1_CC[2:0] TIM2_CC[2:0] TIM3_CC[2:0] NA NA LET0_O[1:0] PCNT0_S[1:0] PCNT1_S[1:0] PCNT2_S[1:0] ACMP0_CH[7:0], ACMP0_O
silabs.com | Building a more connected world.
Rev. 2.30 | 55
Module ACMP1 VCMP ADC0 DAC0 OPAMP
AES GPIO LCD
Configuration Full configuration Full configuration Full configuration Full configuration Full configuration
Full configuration 81 pins Full configuration
EFM32LG Data Sheet
System Summary
Pin Connections ACMP1_CH[3:0], ACMP1_O NA ADC0_CH[7:0] DAC0_OUT[1:0], DAC0_OUTxALT Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx NA Available pins are shown in 5.20.3 GPIO Pinout Overview LCD_SEG[33:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N, LCD_BEXT
silabs.com | Building a more connected world.
Rev. 2.30 | 56
3.2.21 EFM32LG990 The following table describes device-specific implementation of the EFM32LG990 features.
Table 3.21. EFM32LG990 Configuration Summary
EFM32LG Data Sheet
System Summary
Module Cortex-M3 DBG MSC DMA RMU EMU CMU WDOG PRS USB
Configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration
EBI
Full configuration
I2C0 I2C1 USART0 USART1 USART2 UART0 UART1 LEUART0 LEUART1 TIMER0 TIMER1 TIMER2 TIMER3 RTC BURTC LETIMER0 PCNT0 PCNT1 PCNT2 ACMP0
Full configuration Full configuration Full configuration with IrDA Full configuration with I2S Full configuration with I2S Full configuration Full configuration Full configuration Full configuration Full configuration with DTI Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration, 16-bit count register Full configuration, 8-bit count register Full configuration, 8-bit count register Full configuration
Pin Connections NA DBG_SWCLK, DBG_SWDIO, DBG_SWO NA NA NA NA CMU_OUT0, CMU_OUT1 NA NA USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM, USB_DMPU, USB_DP, USB_ID EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0], EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC, EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn I2C0_SDA, I2C0_SCL I2C1_SDA, I2C1_SCL US0_TX, US0_RX. US0_CLK, US0_CS US1_TX, US1_RX, US1_CLK, US1_CS US2_TX, US2_RX, US2_CLK, US2_CS U0_TX, U0_RX U1_TX, U1_RX LEU0_TX, LEU0_RX LEU1_TX, LEU1_RX TIM0_CC[2:0], TIM0_CDTI[2:0] TIM1_CC[2:0] TIM2_CC[2:0] TIM3_CC[2:0] NA NA LET0_O[1:0] PCNT0_S[1:0] PCNT1_S[1:0] PCNT2_S[1:0] ACMP0_CH[7:0], ACMP0_O
silabs.com | Building a more connected world.
Rev. 2.30 | 57
Module ACMP1 VCMP ADC0 DAC0 OPAMP
AES GPIO LCD
Configuration Full configuration Full configuration Full configuration Full configuration Full configuration
Full configuration 86 pins Full configuration
EFM32LG Data Sheet
System Summary
Pin Connections ACMP1_CH[3:0], ACMP1_O NA ADC0_CH[7:0] DAC0_OUT[1:0], DAC0_OUTxALT Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx NA Available pins are shown in 5.21.3 GPIO Pinout Overview LCD_SEG[33:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N, LCD_BEXT
silabs.com | Building a more connected world.
Rev. 2.30 | 58
3.2.22 EFM32LG995 The following table describes device-specific implementation of the EFM32LG995 features.
Table 3.22. EFM32LG995 Configuration Summary
EFM32LG Data Sheet
System Summary
Module Cortex-M3 DBG MSC DMA RMU EMU CMU WDOG PRS USB
Configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration
EBI
Full configuration
I2C0 I2C1 USART0 USART1 USART2 UART0 UART1 LEUART0 LEUART1 TIMER0 TIMER1 TIMER2 TIMER3 RTC BURTC LETIMER0 PCNT0 PCNT1 PCNT2 ACMP0
Full configuration Full configuration Full configuration with IrDA Full configuration with I2S Full configuration with I2S Full configuration Full configuration Full configuration Full configuration Full configuration with DTI Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration Full configuration, 16-bit count register Full configuration, 8-bit count register Full configuration, 8-bit count register Full configuration
Pin Connections NA DBG_SWCLK, DBG_SWDIO, DBG_SWO NA NA NA NA CMU_OUT0, CMU_OUT1 NA NA USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM, USB_DMPU, USB_DP, USB_ID EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0], EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC, EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn I2C0_SDA, I2C0_SCL I2C1_SDA, I2C1_SCL US0_TX, US0_RX. US0_CLK, US0_CS US1_TX, US1_RX, US1_CLK, US1_CS US2_TX, US2_RX, US2_CLK, US2_CS U0_TX, U0_RX U1_TX, U1_RX LEU0_TX, LEU0_RX LEU1_TX, LEU1_RX TIM0_CC[2:0], TIM0_CDTI[2:0] TIM1_CC[2:0] TIM2_CC[2:0] TIM3_CC[2:0] NA NA LET0_O[1:0] PCNT0_S[1:0] PCNT1_S[1:0] PCNT2_S[1:0] ACMP0_CH[7:0], ACMP0_O
silabs.com | Building a more connected world.
Rev. 2.30 | 59
Module ACMP1 VCMP ADC0 DAC0 OPAMP
AES GPIO LCD
Configuration Full configuration Full configuration Full configuration Full configuration Full configuration
Full configuration 93 pins Full configuration
EFM32LG Data Sheet
System Summary
Pin Connections ACMP1_CH[7:0], ACMP1_O NA ADC0_CH[7:0] DAC0_OUT[1:0], DAC0_OUTxALT Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx NA Available pins are shown in 5.22.3 GPIO Pinout Overview LCD_SEG[35:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N, LCD_BEXT
silabs.com | Building a more connected world.
Rev. 2.30 | 60
EFM32LG Data Sheet
System Summary
3.3 Memory Map The EFM32LG memory map is shown in the following figure, with RAM and flash sizes for the largest memory configuration.
Figure 3.2. System Address Space with Core and Code Space Listing
silabs.com | Building a more connected world.
Rev. 2.30 | 61
EFM32LG Data Sheet
System Summary
Figure 3.3. System Address Space with Peripheral Listing
silabs.com | Building a more connected world.
Rev. 2.30 | 62
4. Electrical Characteristics
EFM32LG Data Sheet
Electrical Characteristics
4.1 Test Conditions
4.1.1 Typical Values The typical data are based on TAMB=25°C and VDD=3.0 V, as defined in 4.3 General Operating Conditions, unless otherwise specified.
4.1.2 Minimum and Maximum Values
The minimum and maximum values represent the worst conditions of ambient temperature, supply voltage and frequencies, as defined in 4.3 General Operating Conditions, unless otherwise specified.
4.2 Absolute Maximum Ratings
The absolute maximum ratings are stress ratings, and functional operation under such conditions are not guaranteed. Stress beyond the limits specified in the following table may affect the device reliability or cause permanent damage to the device. Functional operating conditions are given in 4.3 General Operating Conditions.
Table 4.1. Absolute Maximum Ratings
Parameter Storage temperature range Maximum soldering temperature
External main supply voltage Voltage on any I/O pin Current per I/O pin (sink) Current per I/O pin (source) Junction temperature
Symbol
Test Condition
TSTG
TS
Latest IPC/JEDEC J-
STD-020 Standard
VDDMAX
VIOPIN
IIOMAX_SINK
IIOMAX_SOURCE
TJ
-G grade devices
Min
Typ
Max
Unit
-40
--
150
°C
--
--
260
°C
0
--
3.8
V
-0.3
--
VDD+0.3
V
--
--
100
mA
--
--
-100
mA
-40
--
105
°C
4.3 General Operating Conditions
Table 4.2. General Operating Conditions
Parameter Ambient temperature range Operating supply voltage Internal APB clock frequency Internal AHB clock frequency
Symbol Min
Typ
Max
Unit
TAMB
-40
--
85
°C
VDDOP
1.98
--
3.8
V
fAPB
--
--
48
MHz
fAHB
--
--
48
MHz
silabs.com | Building a more connected world.
Rev. 2.30 | 63
4.4 Backup Supply Domain
EFM32LG Data Sheet
Electrical Characteristics
Table 4.3. Backup Supply Domain
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Backup supply voltage range
VBU_VIN
1.8
--
3.8
V
PWRRES resistor
RPWRRES EMU_PWRCONF_PWRRES =
4234
4485
4786
RES0
EMU_PWRCONF_PWRRES =
2208
2363
2528
RES1
EMU_PWRCONF_PWRRES =
1166
1297
1433
RES2
EMU_PWRCONF_PWRRES =
295
344
399
RES3
Output impedance between BU_VIN and BU_VOUT 1
RBU_VOUT
EMU_PWRCONF_VOUTSTRONG = 1,
49
63
80
EMU_PWRCONF_VOUTMED =
0, EMU_PWRCONF_VOUT-
WEAK = 0
EMU_PWRCONF_VOUT-
522
670
844
STRONG = 0,
EMU_PWRCONF_VOUTMED =
1, EMU_PWRCONF_VOUT-
WEAK = 0
EMU_PWRCONF_VOUT-
5161
6743
7853
STRONG = 0,
EMU_PWRCONF_VOUTMED =
0, EMU_PWRCONF_VOUT-
WEAK = 1
Supply current
IBU_VIN
BU_VIN not powering backup do-
--
main
3.4
6.5
nA
BU_VIN powering backup domain
--
197
1050
nA
Note: 1. BU_VOUT and BU_STAT signals are not available in all package configurations. Check the device pinout for availability.
silabs.com | Building a more connected world.
Rev. 2.30 | 64
4.5 Current Consumption
Table 4.4. Current Consumption
Parameter
Symbol Test Condition
Min
EM0 current. No prescaling.
IEM0 48 MHz HFXO, all peripheral clocks disa-
--
Running prime number calcula-
bled, VDD = 3.0 V, TAMB = 25 °C
tion code from Flash. (Produc-
tion test condition = 14 MHz)
48 MHz HFXO, all peripheral clocks disa-
--
bled, VDD = 3.0 V, TAMB = 85 °C
28 MHz HFRCO, all peripheral clocks disa-
--
bled, VDD = 3.0 V, TAMB = 25°C
28 MHz HFRCO, all peripheral clocks disa-
--
bled, VDD = 3.0 V, TAMB = 85°C
21 MHz HFRCO, all peripheral clocks disa-
--
bled, VDD = 3.0 V, TAMB = 25°C
21 MHz HFRCO, all peripheral clocks disa-
--
bled, VDD = 3.0 V, TAMB = 85 °C
14 MHz HFRCO, all peripheral clocks disa-
--
bled, VDD = 3.0 V, TAMB = 25 °C
14 MHz HFRCO, all peripheral clocks disa-
--
bled, VDD= 3.0 V, TAMB = 85°C
11 MHz HFRCO, all peripheral clocks disa-
--
bled, VDD = 3.0 V, TAMB = 25 °C
11 MHz HFRCO, all peripheral clocks disa-
--
bled, VDD = 3.0 V, TAMB = 85 °C
6.6 MHz HFRCO, all peripheral clocks disa- -- bled, VDD= 3.0 V, TAMB = 25°C
6.6 MHz HFRCO, all peripheral clocks disa- -- bled, VDD = 3.0 V, TAMB = 85°C
1.2 MHz HFRCO, all peripheral clocks disa- -- bled, VDD = 3.0 V, TAMB = 25 °C
1.2 MHz HFRCO, all peripheral clocks disa- -- bled, VDD = 3.0 V, TAMB = 85 °C
EFM32LG Data Sheet
Electrical Characteristics
Typ
Max
Unit
211
225 µA/MHz
211
230 µA/MHz
212
220 µA/MHz
213
223 µA/MHz
214
224 µA/MHz
215
226 µA/MHz
216
231 µA/MHz
217
237 µA/MHz
218
239 µA/MHz
219
239 µA/MHz
224
245 µA/MHz
224
258 µA/MHz
257
285 µA/MHz
261
293 µA/MHz
silabs.com | Building a more connected world.
Rev. 2.30 | 65
Parameter EM1 current (Production test condition = 14 MHz)
EM2 current EM3 current EM4 current Note:
1. Using backup RTC.
Symbol Test Condition
Min
IEM1 48 MHz HFXO, all peripheral clocks disa-
--
bled, VDD = 3.0 V, TAMB = 25 °C
48 MHz HFXO, all peripheral clocks disa-
--
bled, VDD = 3.0 V, TAMB = 85 °C
28 MHz HFRCO, all peripheral clocks disa-
--
bled, VDD = 3.0 V, TAMB = 25 °C
28 MHz HFRCO, all peripheral clocks disa-
--
bled, VDD = 3.0 V, TAMB = 85 °C
21 MHz HFRCO, all peripheral clocks disa-
--
bled, VDD = 3.0 V, TAMB = 25 °C
21 MHz HFRCO, all peripheral clocks disa-
--
bled, VDD = 3.0 V, TAMB = 85 °C
14 MHz HFRCO, all peripheral clocks disa-
--
bled, VDD = 3.0 V, TAMB = 25 °C
14 MHz HFRCO, all peripheral clocks disa-
--
bled, VDD = 3.0 V, TAMB = 85 °C
11 MHz HFRCO, all peripheral clocks disa-
--
bled, VDD = 3.0 V, TAMB = 25 °C
11 MHz HFRCO, all peripheral clocks disa-
--
bled, VDD = 3.0 V, TAMB = 85 °C
6.6 MHz HFRCO, all peripheral clocks disa- -- bled, VDD = 3.0 V, TAMB = 25 °C
6.6 MHz HFRCO, all peripheral clocks disa- -- bled, VDD = 3.0 V, TAMB = 85 °C
1.2 MHz HFRCO. all peripheral clocks disa- -- bled, VDD = 3.0 V, TAMB = 25 °C
1.2 MHz HFRCO. all peripheral clocks disa- -- bled, VDD = 3.0 V, TAMB = 85 °C
IEM2 EM2 current with RTC prescaled to 1 Hz,
--
32.768 kHz LFRCO, VDD = 3.0 V, TAMB =
25 °C
EM2 current with RTC prescaled to 1 Hz,
--
32.768 kHz LFRCO, VDD = 3.0 V, TAMB =
85 °C
IEM3 VDD = 3.0 V, TAMB = 25 °C
--
VDD = 3.0 V, TAMB = 85 °C
--
IEM4 VDD = 3.0 V, TAMB = 25 °C
--
VDD = 3.0 V, TAMB = 85 °C
--
EFM32LG Data Sheet
Electrical Characteristics
Typ
Max
Unit
63
75
µA/MHz
65
76
µA/MHz
64
75
µA/MHz
65
77
µA/MHz
65
76
µA/MHz
66
78
µA/MHz
67
79
µA/MHz
68
82
µA/MHz
68
81
µA/MHz
70
83
µA/MHz
74
87
µA/MHz
76
89
µA/MHz
106
120 µA/MHz
112
129 µA/MHz
0.951
1.71
µA
3.01
4.01
µA
0.65
1.3
µA
2.65
4.0
µA
0.020 0.055
µA
0.44
0.90
µA
silabs.com | Building a more connected world.
Rev. 2.30 | 66
4.5.1 EM1 Current Consumption
EFM32LG Data Sheet
Electrical Characteristics
Idd [mA]
3.15
3.15
3.10
3.10
3.05
3.00
-40°C
-15°C
5°C
2.95
25°C
45°C
65°C
85°C
2.902.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
Vdd [V]
Idd [mA]
3.05 3.00 2.95 2.9040
2.0V 2.2V 2.4V 2.6V 2.8V 3.0V 3.2V 3.4V 3.6V 3.8V
15
5
25
45
65
85
Temperature [°C]
Figure 4.1. EM1 Current Consumption with all Peripheral Clocks Disabled and HFXO Running at 48 MHz
1.85
1.85
1.80
1.80
1.75
1.70
-40°C
-15°C
5°C
1.65
25°C
45°C
65°C
85°C
1.602.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
Vdd [V]
Idd [mA]
1.75 1.70 1.65 1.6040
2.0V 2.2V 2.4V 2.6V 2.8V 3.0V 3.2V 3.4V 3.6V 3.8V
15
5
25
45
65
85
Temperature [°C]
Figure 4.2. EM1 Current Consumption with all Peripheral Clocks Disabled and HFRCO Running at 28 MHz
Idd [mA]
silabs.com | Building a more connected world.
Rev. 2.30 | 67
Idd [mA]
EFM32LG Data Sheet
Electrical Characteristics
1.42
1.40
1.38
1.36
1.34
1.32
1.30
-40°C
-15°C
5°C
1.28
25°C
45°C
1.26
65°C
85°C
1.242.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
Vdd [V]
Idd [mA]
1.42 1.40 1.38 1.36 1.34 1.32 1.30 1.28 1.26 1.2440
2.0V 2.2V 2.4V 2.6V 2.8V 3.0V 3.2V 3.4V 3.6V 3.8V
15
5
25
45
65
85
Temperature [°C]
Figure 4.3. EM1 Current Consumption with all Peripheral Clocks Disabled and HFRCO Running at 21 MHz
0.98
0.98
0.96
0.96
0.94
0.94
Idd [mA]
0.92
0.90
-40°C
-15°C
5°C
25°C
0.88
45°C
65°C
85°C
0.862.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
Vdd [V]
0.92 0.90 0.88 0.8640
2.0V 2.2V 2.4V 2.6V 2.8V 3.0V 3.2V 3.4V 3.6V 3.8V
15
5
25
45
65
85
Temperature [°C]
Figure 4.4. EM1 Current Consumption with all Peripheral Clocks Disabled and HFRCO Running at 14 MHz
Idd [mA]
silabs.com | Building a more connected world.
Rev. 2.30 | 68
Idd [mA]
EFM32LG Data Sheet
Electrical Characteristics
0.78
0.78
0.76
0.76
Idd [mA]
0.74
0.72 0.70
-40°C -15°C 5°C 25°C 45°C 65°C 85°C
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 Vdd [V]
0.74 0.72 0.70
40
2.0V 2.2V 2.4V 2.6V 2.8V 3.0V 3.2V 3.4V 3.6V 3.8V
15
5
25
45
65
85
Temperature [°C]
Figure 4.5. EM1 Current Consumption with all Peripheral Clocks Disabled and HFRCO Running at 11 MHz
0.52
0.52
0.51
0.51
0.50
0.50
0.49
0.48
-40°C
0.47
-15°C
5°C
25°C
0.46
45°C
65°C
85°C
0.452.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
Vdd [V]
Idd [mA]
0.49 0.48 0.47 0.46 0.4540
2.0V 2.2V 2.4V 2.6V 2.8V 3.0V 3.2V 3.4V 3.6V 3.8V
15
5
25
45
65
85
Temperature [°C]
Figure 4.6. EM1 Current Consumption with all Peripheral Clocks Disabled and HFRCO Running at 6.6 MHz
Idd [mA]
silabs.com | Building a more connected world.
Rev. 2.30 | 69
EFM32LG Data Sheet
Electrical Characteristics
Idd [mA] Idd [mA]
0.138 0.136 0.134 0.132
-40°C -15°C 5°C 25°C 45°C 65°C 85°C
0.130
0.128
0.126
0.124
0.1222.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
Vdd [V]
0.160 0.155 0.150 0.145 0.140 0.135
2.0V 2.2V 2.4V 2.6V 2.8V 3.0V 3.2V 3.4V 3.6V 3.8V
0.130
0.125
0.120
0.11540
15
5
25
45
65
85
Temperature [°C]
Figure 4.7. EM1 Current Consumption with all Peripheral Clocks Disabled and HFRCO Running at 1.2 MHz
4.5.2 EM2 Current Consumption
3.5
3.5
-40.0°C
Vdd=2.0V
-15.0°C
Vdd=2.2V
3.0
5.0°C
3.0
Vdd=2.4V
25.0°C
Vdd=2.6V
45.0°C
Vdd=2.8V
65.0°C
Vdd=3.0V
2.5
85.0°C
2.5
Vdd=3.2V
Vdd=3.4V
Vdd=3.6V
2.0
2.0
Vdd=3.8V
Idd [uA] Idd [uA]
1.5
1.5
1.0
1.0
0.52.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
Vdd [V]
0.540
20
0
20
40
60
80
Temperature [°C]
Figure 4.8. EM2 Current Consumption, RTC1 prescaled to 1 kHz, 32.768 kHz LFRCO
Note: 1. Using backup RTC.
silabs.com | Building a more connected world.
Rev. 2.30 | 70
4.5.3 EM3 Current Consumption
EFM32LG Data Sheet
Electrical Characteristics
3.0
3.0
-40.0°C
Vdd=2.0V
-15.0°C
Vdd=2.2V
2.5
5.0°C
2.5
Vdd=2.4V
25.0°C
Vdd=2.6V
45.0°C
Vdd=2.8V
65.0°C
Vdd=3.0V
2.0
85.0°C
2.0
Vdd=3.2V
Vdd=3.4V
Vdd=3.6V
1.5
1.5
Vdd=3.8V
Idd [uA] Idd [uA]
1.0
1.0
0.5
0.5
0.02.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
Vdd [V]
0.040
20
0
20
40
60
80
Temperature [°C]
Figure 4.9. EM3 Current Consumption
4.5.4 EM4 Current Consumption
Idd [uA] Idd [uA]
0.7
-40.0°C
-15.0°C
0.6
5.0°C
25.0°C
45.0°C
0.5
65.0°C
85.0°C
0.4
0.3
0.7
Vdd=2.0V
Vdd=2.2V
0.6
Vdd=2.4V
Vdd=2.6V
Vdd=2.8V
0.5
Vdd=3.0V
Vdd=3.2V
Vdd=3.4V
0.4
Vdd=3.6V
Vdd=3.8V
0.3
0.2
0.2
0.1
0.1
0.02.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
Vdd [V]
0.040
20
0
20
40
60
80
Temperature [°C]
Figure 4.10. EM4 Current Consumption
silabs.com | Building a more connected world.
Rev. 2.30 | 71
4.6 Transition between Energy Modes The transition times are measured from the trigger to the first clock edge in the CPU.
Table 4.5. Energy Modes Transitions
EFM32LG Data Sheet
Electrical Characteristics
Parameter Transition time from EM1 to EM0 Transition time from EM2 to EM0 Transition time from EM3 to EM0 Transition time from EM4 to EM0
Symbol
Min
Typ
Max
Unit
tEM10
--
0
--
HFCORECLK cycles
tEM20
--
2
--
µs
tEM30
--
2
--
µs
tEM40
--
163
--
µs
4.7 Power Management The EFM32LG requires the AVDD_x, VDD_DREG and IOVDD_x pins to be connected together (with optional filter) at the PCB level. For practical schematic recommendations, see the application note, AN0002: EFM32 Hardware Design Considerations.
Table 4.6. Power Management
Parameter
Symbol Test Condition
Min
Typ
Max
Unit
BOD threshold on falling external supply voltage
VBODextthr-
1.74
--
1.96
V
BOD threshold on rising external supply voltage
VBODextthr+
--
1.85
1.98
V
Power-on Reset (POR) threshold on rising external supply voltage
VPORthr+
--
--
1.98
V
Delay from reset is released un-
tRESET
Applies to Power-on Reset, Brown-
--
163
--
µs
til program execution starts
out Reset and pin reset.
Voltage regulator decoupling
CDECOUPLE X5R capacitor recommended. Apply
--
1
--
µF
capacitor.
between DECOUPLE pin and
GROUND
USB voltage regulator out de-
CUSB_VREGO X5R capacitor recommended. Apply
--
1
--
µF
coupling capacitor.
between USB_VREGO pin and
GROUND
USB voltage regulator in decou- CUSB_VREGI X5R capacitor recommended. Apply
--
4.7
--
µF
pling capacitor.
between USB_VREGI pin and
GROUND
silabs.com | Building a more connected world.
Rev. 2.30 | 72
4.8 Flash
EFM32LG Data Sheet
Electrical Characteristics
Table 4.7. Flash
Parameter
Symbol Test Condition
Min
Typ
Max
Unit
Flash erase cycles before failure
ECFLASH
20000
--
--
cycles
Flash word write cycles between erase
WWCFLASH
--
--
21
cycles
Flash data retention
RETFLASH TAMB<150 °C
10000
--
--
h
TAMB<85 °C
10
--
--
years
TAMB<70 °C
20
--
--
years
Word (32-bit) programming time tW_PROG
20
--
--
µs
Page erase time2
tPERASE
20.7
22.0
24.8
ms
Device erase time3
tDERASE
41.8
45.0
49.2
ms
Erase current
IERASE
--
--
74
mA
Write current
IWRITE
--
--
74
mA
Supply voltage during flash erase and write
VFLASH
1.98
--
3.8
V
Note:
1. There is a maximum of two writes to the same word between each erase due to a physical limitation of the flash. No bit should be written to `0' more than once between erases. To write a word twice between erases, any bit written to `0' by the first write should be written to `1' by the second write. This preserves the specified flash write/erase endurance and does not change the `0' written by the first write.
2. From setting ERASEPAGE bit in MSC_WRITECMD to 1 to reading 1 in ERASE bit in MSC_IF. Internal setup and hold times for flash control signals are included.
3. From setting DEVICEERASE bit in AAP_CMD to 1 to reading 0 in ERASEBUSY bit in AAP_STATUS. Internal setup and hold times for flash control signals are included.
4. Measured at 25 °C.
silabs.com | Building a more connected world.
Rev. 2.30 | 73
4.9 General Purpose Input Output
EFM32LG Data Sheet
Electrical Characteristics
Table 4.8. GPIO
Parameter
Symbol Test Condition
Input low voltage
VIOIL
Input high voltage
VIOIH
Output high voltage (Production test condition = 3.0 V, DRIVEMODE = STANDARD)
VIOOH
Sourcing 0.1 mA, VDD = 1.98 V, GPIO_Px_CTRL DRIVEMODE = LOWEST
Sourcing 0.1 mA, VDD = 3.0 V, GPIO_Px_CTRL DRIVEMODE = LOWEST
Sourcing 1 mA, VDD = 1.98 V, GPIO_Px_CTRL DRIVEMODE = LOW
Sourcing 1 mA, VDD = 3.0 V, GPIO_Px_CTRL DRIVEMODE = LOW
Sourcing 6 mA, VDD = 1.98 V, GPIO_Px_CTRL DRIVEMODE = STANDARD
Sourcing 6 mA, VDD = 3.0 V, GPIO_Px_CTRL DRIVEMODE = STANDARD
Sourcing 20 mA, VDD=1.98 V, GPIO_Px_CTRL DRIVEMODE = HIGH
Sourcing 20 mA, VDD = 3.0 V, GPIO_Px_CTRL DRIVEMODE = HIGH
Output low voltage (Production test condition = 3.0V, DRIVEMODE = STANDARD)
VIOOL
Sinking 0.1 mA, VDD = 1.98 V, GPIO_Px_CTRL DRIVEMODE = LOWEST
Sinking 0.1 mA, VDD = 3.0 V, GPIO_Px_CTRL DRIVEMODE = LOWEST
Sinking 1 mA, VDD = 1.98 V, GPIO_Px_CTRL DRIVEMODE = LOW
Sinking 1 mA, VDD = 3.0 V, GPIO_Px_CTRL DRIVEMODE = LOW
Sinking 6 mA, VDD = 1.98 V, GPIO_Px_CTRL DRIVEMODE = STANDARD
Sinking 6 mA, VDD = 3.0 V, GPIO_Px_CTRL DRIVEMODE = STANDARD
Sinking 20 mA, VDD = 1.98 V, GPIO_Px_CTRL DRIVEMODE = HIGH
Sinking 20 mA, VDD = 3.0 V, GPIO_Px_CTRL DRIVEMODE = HIGH
Min -- 0.70×VDD --
Typ -- -- 0.80×VDD
Max 0.30×VDD
-- --
--
0.90×VDD
--
--
0.85×VDD
--
--
0.90×VDD
--
0.75×VDD
--
--
0.85×VDD
--
--
0.60×VDD
--
--
0.80×VDD
--
--
--
0.20×VDD
--
--
0.10×VDD
--
--
0.10×VDD
--
--
0.05×VDD
--
--
--
0.30×VDD
--
--
0.20×VDD
--
--
0.35×VDD
--
--
0.25×VDD
Unit V V V
V
V V V
V
V V V
V
V V V
V
V V
silabs.com | Building a more connected world.
Rev. 2.30 | 74
Parameter
Symbol Test Condition
Min
Input leakage current
IIOLEAK VSS < Vin < VDD; pin configured as in-
-40
put or disabled, pullup and pull-down are
disabled
I/O pin pull-up resistor
RPU
--
I/O pin pull-down resistor
RPD
--
Internal ESD series resistor
RIOESD
--
Pulse width of pulses to be re- tIO-
10
moved by the glitch suppres- GLITCH
sion filter
Output fall time
tIOOF
GPIO_Px_CTRL DRIVEMODE = LOWEST and load capacitance CL = 12.5-2 5pF.
20+0.1×CL
GPIO_Px_CTRL DRIVEMODE = LOW 20+0.1×CL and load capacitance CL = 350 -600 pF
I/O pin hysteresis (VIOTHR+ VIOTHR-)
VIOHYST VDD = 1.98 - 3.8 V
0.10×VDD
EFM32LG Data Sheet
Electrical Characteristics
Typ
Max
Unit
±0.1
40
nA
40
--
k
40
--
k
200
--
--
50
ns
--
250
ns
--
250
ns
--
--
V
silabs.com | Building a more connected world.
Rev. 2.30 | 75
Low-Level Output Current [mA]
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.20
EFM32LG Data Sheet
Electrical Characteristics
GPIO_Px_CTRL DRIVEMODE = LOW
5
4 0.15
Low-Level Output Current [mA]
3 0.10
2
0.05 0.000.0
0.5
1.0
1.5
Low-Level Output Voltage [V]
-40°C 25°C 85°C
2.0
1
-40°C
25°C
85°C
00.0
0.5
1.0
1.5
2.0
Low-Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
20
15
10
5
-40°C
25°C
85°C
00.0
0.5
1.0
1.5
2.0
Low-Level Output Voltage [V]
Low-Level Output Current [mA]
GPIO_Px_CTRL DRIVEMODE = HIGH
45
40
35
30
25
20
15
10
5
-40°C
25°C
85°C
00.0
0.5
1.0
1.5
2.0
Low-Level Output Voltage [V]
Figure 4.11. Typical Low-Level Output Current, 2 V Supply Voltage
Low-Level Output Current [mA]
silabs.com | Building a more connected world.
Rev. 2.30 | 76
High-Level Output Current [mA]
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.00 -40°C 25°C 85°C
0.05
0.10
0.15
High-Level Output Current [mA]
EFM32LG Data Sheet
Electrical Characteristics
GPIO_Px_CTRL DRIVEMODE = LOW
0.0 -40°C 25°C 85°C
0.5
1.0
1.5
2.0
0.200.0
0.5
1.0
1.5
2.0
High-Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
0 -40°C 25°C 85°C
5
2.50.0
0.5
1.0
1.5
2.0
High-Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = HIGH
0 -40°C 25°C 85°C
10
High-Level Output Current [mA]
20 10
30 15
40
20
0.0
0.5
1.0
1.5
2.0
500.0
0.5
1.0
1.5
2.0
High-Level Output Voltage [V]
High-Level Output Voltage [V]
Figure 4.12. Typical High-Level Output Current, 2 V Supply Voltage
High-Level Output Current [mA]
silabs.com | Building a more connected world.
Rev. 2.30 | 77
Low-Level Output Current [mA]
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.5
EFM32LG Data Sheet
Electrical Characteristics
GPIO_Px_CTRL DRIVEMODE = LOW
10
0.4
8
Low-Level Output Current [mA]
0.3
6
0.2
4
0.1 0.00.0
0.5
1.0
1.5
2.0
Low-Level Output Voltage [V]
-40°C 25°C 85°C
2.5
3.0
2
-40°C
25°C
85°C
00.0
0.5
1.0
1.5
2.0
2.5
3.0
Low-Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
40
GPIO_Px_CTRL DRIVEMODE = HIGH
50
35
40 30
Low-Level Output Current [mA]
25 30
20 20
15
10
5
-40°C
25°C
85°C
00.0
0.5
1.0
1.5
2.0
2.5
3.0
Low-Level Output Voltage [V]
10 00.0
0.5
1.0
1.5
2.0
Low-Level Output Voltage [V]
-40°C 25°C 85°C
2.5
3.0
Figure 4.13. Typical Low-Level Output Current, 3 V Supply Voltage
Low-Level Output Current [mA]
silabs.com | Building a more connected world.
Rev. 2.30 | 78
High-Level Output Current [mA]
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.0 -40°C 25°C 85°C
0.1
0.2
0.3
0.4
0.50.0
0.5
1.0
1.5
2.0
2.5
3.0
High-Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
0 -40°C 25°C 85°C
10
High-Level Output Current [mA]
EFM32LG Data Sheet
Electrical Characteristics
GPIO_Px_CTRL DRIVEMODE = LOW
0 -40°C 25°C 85°C
1
2
3
4
5
60.0
0.5
1.0
1.5
2.0
2.5
3.0
High-Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = HIGH
0 -40°C 25°C 85°C
10
High-Level Output Current [mA]
20
20
30
30
40
40
500.0
0.5
1.0
1.5
2.0
2.5
3.0
High-Level Output Voltage [V]
500.0
0.5
1.0
1.5
2.0
2.5
3.0
High-Level Output Voltage [V]
Figure 4.14. Typical High-Level Output Current, 3 V Supply Voltage
High-Level Output Current [mA]
silabs.com | Building a more connected world.
Rev. 2.30 | 79
Low-Level Output Current [mA]
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
-40°C
25°C
85°C
0.00.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Low-Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
50
Low-Level Output Current [mA]
EFM32LG Data Sheet
Electrical Characteristics
GPIO_Px_CTRL DRIVEMODE = LOW
14
12
10
8
6
4
2 -40°C
25°C
85°C
00.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Low-Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = HIGH
50
40
40
Low-Level Output Current [mA]
30
30
20
20
10
-40°C
25°C
85°C
00.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Low-Level Output Voltage [V]
10
-40°C
25°C
85°C
00.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Low-Level Output Voltage [V]
Figure 4.15. Typical Low-Level Output Current, 3.8 V Supply Voltage
Low-Level Output Current [mA]
silabs.com | Building a more connected world.
Rev. 2.30 | 80
High-Level Output Current [mA]
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.0 -40°C
25°C
0.1
85°C
0.2
0.3
0.4
0.5
0.6
0.7
0.80.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
High-Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
0 -40°C 25°C 85°C
10
High-Level Output Current [mA]
EFM32LG Data Sheet
Electrical Characteristics
GPIO_Px_CTRL DRIVEMODE = LOW
0 -40°C
25°C
1
85°C
2
3
4
5
6
7
8
90.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
High-Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = HIGH
0 -40°C 25°C 85°C
10
High-Level Output Current [mA]
20
20
30
30
40
40
500.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
High-Level Output Voltage [V]
500.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
High-Level Output Voltage [V]
Figure 4.16. Typical High-Level Output Current, 3.8 V Supply Voltage
High-Level Output Current [mA]
silabs.com | Building a more connected world.
Rev. 2.30 | 81
4.10 Oscillators 4.10.1 LFXO
EFM32LG Data Sheet
Electrical Characteristics
Table 4.9. LFXO
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Supported nominal crystal frequency
fLFXO
--
32.768
--
kHz
Supported crystal equivalent series resistance (ESR)
ESRLFXO
--
30
120
k
Supported crystal external load range
CLFXOL
X1
--
25
pF
Current consumption for core and buffer after startup.
ILFXO
ESR = 30 k, CL = 10 pF, LFXOBOOST in CMU_CTRL is 1
--
190
--
nA
Start- up time.
tLFXO
ESR = 30 k, CL = 10 pF, 40% - 60%
--
400
--
ms
duty cycle has been reached, LFXO-
BOOST in CMU_CTRL is 1
Note: 1. See Minimum Load Capacitance (CLFXOL) Requirement For Safe Crystal Startup in Configurator in Simplicity Studio.
For safe startup of a given crystal, the Configurator tool in Simplicity Studio contains a tool to help users configure both load capacitance and software settings for using the LFXO. For details regarding the crystal configuration, refer to the application note, AN0016: EFM32 Oscillator Design Consideration.
silabs.com | Building a more connected world.
Rev. 2.30 | 82
4.10.2 HFXO
Parameter Supported nominal crystal Frequency Supported crystal equivalent series resistance (ESR)
The transconductance of the HFXO input transistor at crystal startup Supported crystal external load range Current consumption for HFXO after startup
Startup time
Symbol fHFXO
ESRHFXO
gmHFXO CHFXOL IHFXO
tHFXO
Table 4.10. HFXO
Test Condition
Crystal frequency 48 MHz Crystal frequency 32 MHz Crystal frequency 4 MHz HFXOBOOST in CMU_CTRL equals 0b11
4 MHz: ESR = 400 , CL = 20 pF, HFXOBOOST in CMU_CTRL equals 0b11 32 MHz: ESR = 30 , CL = 10 pF, HFXOBOOST in CMU_CTRL equals 0b11 32 MHz: ESR = 30 , CL = 10 pF, HFXOBOOST in CMU_CTRL equals 0b11
EFM32LG Data Sheet
Electrical Characteristics
Min
Typ
Max
Unit
4
--
48
MHz
--
--
50
--
30
60
--
400
1500
20
--
--
mS
5
--
25
pF
--
85
--
µA
--
165
--
µA
--
400
--
µs
silabs.com | Building a more connected world.
Rev. 2.30 | 83
4.10.3 LFRCO
EFM32LG Data Sheet
Electrical Characteristics
Table 4.11. LFRCO
Parameter Oscillation frequency
Startup time not including software calibration Current consumption Frequency step for LSB change in TUNING value Voltage drift Temperature drift
Symbol fLFRCO
tLFRCO
Test Condition
Min
Typ
Max
Unit
VDD = 3.0 V, TAMB = 25 °C
31.29 32.768 34.28 kHz
Over full supply and temperature range 26.0 32.768 46.2
kHz
--
150
--
µs
ILFRCO TUNESTEPLFRCO
--
300
--
nA
--
1.5
--
%
VDRIFT TDRIFT
-- -123291 --
ppm/V
--
610
-- ppm/°C
Figure 4.17. Calibrated LFRCO Frequency vs Temperature and Supply Voltage
silabs.com | Building a more connected world.
Rev. 2.30 | 84
4.10.4 HFRCO
Table 4.12. HFRCO
Parameter Oscillation frequency, all packages except CSP, VDD= 3.0 V, TAMB=25°C
Oscillation frequency, all packages except CSP, over full supply and temperature range
Oscillation frequency, CSP devices, VDD= 3.0 V, TAMB=25°C
Oscillation frequency, CSP devices, over full supply and temperature range
Settling time after start-up Current consumption
Symbol fHFRCO
fHFRCO
fHFRCO
fHFRCO
tHFRCO_settling IHFRCO
Test Condition fHFRCO = 28 MHz fHFRCO = 21 MHz fHFRCO = 14 MHz fHFRCO = 11 MHz fHFRCO = 6.6 MHz fHFRCO = 1.2 MHz fHFRCO = 28 MHz fHFRCO = 21 MHz fHFRCO = 14 MHz fHFRCO = 11 MHz fHFRCO = 6.6 MHz fHFRCO = 1.2 MHz fHFRCO = 28 MHz fHFRCO = 21 MHz fHFRCO = 14 MHz fHFRCO = 11 MHz fHFRCO = 6.6 MHz fHFRCO = 1.2 MHz fHFRCO = 28 MHz fHFRCO = 21 MHz fHFRCO = 14 MHz fHFRCO = 11 MHz fHFRCO = 6.6 MHz fHFRCO = 1.2 MHz fHFRCO = 14 MHz fHFRCO = 28 MHz fHFRCO = 21 MHz fHFRCO = 14 MHz fHFRCO = 11 MHz fHFRCO = 6.6 MHz fHFRCO = 1.2 MHz
silabs.com | Building a more connected world.
EFM32LG Data Sheet
Electrical Characteristics
Min
Typ
Max
Unit
27.5
28.0
28.5
MHz
20.6
21.0
21.4
MHz
13.7
14.0
14.3
MHz
10.8
11.0
11.2
MHz
6.481
6.61
6.721
MHz
1.152
1.22
1.252
MHz
24.9
28.0
31.1
MHz
18.8
21.0
23.3
MHz
12.4
14.0
15.6
MHz
9.9
11.0
12.2
MHz
5.91
6.61
7.41
MHz
0.82
1.22
1.62
MHz
--
28.0
--
MHz
--
21.0
--
MHz
--
14.0
--
MHz
--
11.0
--
MHz
--
6.61
--
MHz
--
1.22
--
MHz
--
28.0
--
MHz
--
21.0
--
MHz
--
14.0
--
MHz
--
11.0
--
MHz
--
6.61
--
MHz
--
1.22
--
MHz
--
0.6
--
Cycles
--
165
215
µA
--
134
175
µA
--
106
140
µA
--
94
125
µA
--
77
105
µA
--
25
40
µA
Rev. 2.30 | 85
EFM32LG Data Sheet
Electrical Characteristics
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Voltage drift
VHFRCO_DRIFT fHFRCO = 28 MHz
--
10768
--
ppm/V
fHFRCO = 21 MHz
--
8939
--
ppm/V
fHFRCO = 14 MHz
--
8040
--
ppm/V
fHFRCO = 11 MHz
--
7719
--
ppm/V
fHFRCO = 6.6 MHz
--
8491
--
ppm/V
fHFRCO = 1.2 MHz
-- -124035 --
ppm/V
Temperature drift
THFRCO_DRIFT fHFRCO = 28 MHz
--
91
-- ppm/°C
fHFRCO = 21 MHz
--
88
-- ppm/°C
fHFRCO = 14 MHz
--
43
-- ppm/°C
fHFRCO = 11 MHz
--
50
-- ppm/°C
fHFRCO = 6.6 MHz
--
-50
-- ppm/°C
fHFRCO = 1.2 MHz
--
83
-- ppm/°C
Frequency step for LSB change in TUNING value
TUNESTEPHFRCO
--
0.33
--
%
Note:
1. For devices with prod. rev. < 19, Typ = 7MHz and Min/Max values not applicable.
2. For devices with prod. rev. < 19, Typ = 1MHz and Min/Max values not applicable.
3. The TUNING field in the CMU_HFRCOCTRL register may be used to adjust the HFRCO frequency. There is enough adjustment range to ensure that the frequency bands above 7 MHz will always have some overlap across supply voltage and temperature. By using a stable frequency reference such as the LFXO or HFXO, a firmware calibration routine can vary the TUNING bits and the frequency band to maintain the HFRCO frequency at any arbitrary value between 7 MHz and 28 MHz across operating conditions.
Figure 4.18. Calibrated HFRCO 1 MHz Band Frequency vs Supply Voltage and Temperature
silabs.com | Building a more connected world.
Rev. 2.30 | 86
EFM32LG Data Sheet
Electrical Characteristics
Figure 4.19. Calibrated HFRCO 7 MHz Band Frequency vs Supply Voltage and Temperature
Figure 4.20. Calibrated HFRCO 11 MHz Band Frequency vs Supply Voltage and Temperature
silabs.com | Building a more connected world.
Rev. 2.30 | 87
EFM32LG Data Sheet
Electrical Characteristics
Figure 4.21. Calibrated HFRCO 14 MHz Band Frequency vs Supply Voltage and Temperature
Figure 4.22. Calibrated HFRCO 21 MHz Band Frequency vs Supply Voltage and Temperature
silabs.com | Building a more connected world.
Rev. 2.30 | 88
EFM32LG Data Sheet
Electrical Characteristics
Figure 4.23. Calibrated HFRCO 28 MHz Band Frequency vs Supply Voltage and Temperature
silabs.com | Building a more connected world.
Rev. 2.30 | 89
4.10.5 AUXHFRCO
EFM32LG Data Sheet
Electrical Characteristics
Table 4.13. AUXHFRCO
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Oscillation frequency, all packages except CSP, VDD= 3.0 V, TAMB = 25 °C
fAUXHFRCO
fAUXHFRCO = 28 MHz fAUXHFRCO = 21 MHz fAUXHFRCO = 14 MHz
27.5
28.0
28.5
MHz
20.6
21.0
21.4
MHz
13.7
14.0
14.3
MHz
fAUXHFRCO = 11 MHz
10.8
11.0
11.2
MHz
fAUXHFRCO = 6.6 MHz
6.481 6.601
6.721
MHz
fAUXHFRCO = 1.2 MHz
1.152 1.202
1.252
MHz
Oscillation frequency, CSP devices, VDD = 3.0 V, TAMB = 25 °C
fAUXHFRCO
fAUXHFRCO = 28 MHz fAUXHFRCO = 21 MHz fAUXHFRCO = 14 MHz
--
28.0
--
MHz
--
21.0
--
MHz
--
14.0
--
MHz
fAUXHFRCO = 11 MHz
--
11.0
--
MHz
fAUXHFRCO = 6.6 MHz
--
6.601
--
MHz
fAUXHFRCO = 1.2 MHz
--
1.202
--
MHz
Settling time after start-up
tAUXHFRCO_settling fAUXHFRCO = 14 MHz
--
0.6
--
Cycles
Frequency step for LSB change in TUNING value
TUNESTEPAUXHFRCO
--
0.33
--
%
Note:
1. For devices with prod. rev. < 19, Typ = 7MHz and Min/Max values not applicable.
2. For devices with prod. rev. < 19, Typ = 1MHz and Min/Max values not applicable.
3. The TUNING field in the CMU_AUXHFRCOCTRL register may be used to adjust the AUXHFRCO frequency. There is enough adjustment range to ensure that the frequency bands above 7 MHz will always have some overlap across supply voltage and temperature. By using a stable frequency reference such as the LFXO or HFXO, a firmware calibration routine can vary the TUNING bits and the frequency band to maintain the AUXHFRCO frequency at any arbitrary value between 7 MHz and 28 MHz across operating conditions.
4.10.6 ULFRCO
Parameter Oscillation frequency Temperature coefficient Supply voltage coefficient
Table 4.14. ULFRCO
Symbol fULFRCO TCULFRCO VCULFRCO
Test Condition 25 °C, 3 V
Min
Typ
Max
Unit
0.7
--
1.75
kHz
--
0.05
--
%/°C
--
-18.2
--
%/V
silabs.com | Building a more connected world.
Rev. 2.30 | 90
4.11 Analog Digital Converter (ADC)
EFM32LG Data Sheet
Electrical Characteristics
Table 4.15. ADC
Parameter Input voltage range
Input range of external reference voltage, single-ended and differential Input range of external negative reference voltage on channel 7 Input range of external positive reference voltage on channel 6 Common mode input range Input current Analog input common mode rejection ratio Average active current
Input capacitance Input ON resistance Input RC filter resistance Input RC filter/decoupling capacitance Input bias current Input offset current ADC Clock Frequency Conversion time
Symbol VADCIN
VADCREFIN
Test Condition Single-ended Differential
Min 0
-VREF/2 1.25
VADCREFIN_CH7 See VADCREFIN
VADCREFIN_CH6 See VADCREFIN
VADCCMIN IADCIN
CMRRADC
2 pF sampling capacitors
0
0.625
0 -- --
IADC
CADCIN RADCIN RADCFILT CADCFILT
1 MSamples/s, 12-bit, external
--
reference
10 kSamples/s 12-bit, internal
--
1.25 V reference, WARMUP-
MODE in ADCn_CTRL set to
0b00
10 kSamples/s 12-bit, internal
--
1.25 V reference, WARMUP-
MODE in ADCn_CTRL set to
0b01
10 kSamples/s 12-bit, internal
--
1.25 V reference, WARMUP-
MODE in ADCn_CTRL set to
0b10
--
300
--
--
IADCBIASIN
VSS < VIN < VDD
-40
IADCOFFSETIN
VSS < VIN < VDD
-40
fADCCLK
--
tADCCONV
6-bit
7
8-bit
11
12-bit
13
Typ
Max
Unit
--
VREF
V
--
VREF/2
V
--
VDD
V
--
VDD - 1.1
V
--
VDD
V
--
VDD
V
<100
--
nA
65
--
dB
351 1
--
µA
67 1
--
µA
63 1
--
µA
64 1
--
µA
2
--
pF
--
800
10
--
k
250
--
fF
--
40
nA
--
40
nA
--
13
MHz
--
-- ADCCLK
Cycles
--
-- ADCCLK
Cycles
--
-- ADCCLK
Cycles
silabs.com | Building a more connected world.
Rev. 2.30 | 91
Parameter Acquisition time
Required acquisition time for VDD/3 reference Startup time of reference generator and ADC core
Signal-to-Noise Ratio (SNR)
Symbol tADCACQ tADCACQVDD3 tADCSTART
SNRADC
Test Condition
Min
Programmable
1
2
NORMAL mode
--
KEEPADCWARM mode
--
1 MSamples/s, 12-bit, single-
--
ended, internal 1.25 V reference
1 MSamples/s, 12-bit, single-
--
ended, internal 2.5 V reference
1 MSamples/s, 12-bit, single-
--
ended, VDD reference
1 MSamples/s, 12-bit, differen-
--
tial, internal 1.25 V reference
1 MSamples/s, 12-bit, differen-
--
tial, internal 2.5 V reference
1 MSamples/s, 12-bit, differen-
--
tial, 5 V reference
1 MSamples/s, 12-bit, differen-
--
tial, VDD reference
1 MSamples/s, 12-bit, differen-
--
tial, 2xVDD reference
200 kSamples/s, 12-bit, single-
--
ended, internal 1.25 V reference
200 kSamples/s, 12-bit, single-
--
ended, internal 2.5 V reference
200 kSamples/s, 12-bit, single-
--
ended, VDD reference
200 kSamples/s, 12-bit, differ-
--
ential, internal 1.25 V reference
200 kSamples/s, 12-bit, differ-
--
ential, internal 2.5 V reference
200 kSamples/s, 12-bit, differ-
--
ential, 5 V reference
200 kSamples/s, 12-bit, differ-
63
ential, VDD reference
200 kSamples/s, 12-bit, differ-
--
ential, 2xVDD reference
EFM32LG Data Sheet
Electrical Characteristics
Typ
Max
Unit
--
256 ADCCLK
Cycles
--
--
µs
5
--
µs
1
--
µs
59
--
dB
63
--
dB
65
--
dB
60
--
dB
65
--
dB
54
--
dB
67
--
dB
69
--
dB
62
--
dB
63
--
dB
67
--
dB
63
--
dB
66
--
dB
66
--
dB
66
--
dB
70
--
dB
silabs.com | Building a more connected world.
Rev. 2.30 | 92
Parameter
Signal-to-Noise And Distortion Ratio (SINAD)
Symbol SINADADC
Test Condition
Min
1 MSamples/s, 12-bit, single-
--
ended, internal 1.25 V reference
1 MSamples/s, 12-bit, single-
--
ended, internal 2.5 V reference
1 MSamples/s, 12-bit, single-
--
ended, VDD reference
1 MSamples/s, 12-bit, differen-
--
tial, internal 1.25 V reference
1 MSamples/s, 12-bit, differen-
--
tial, internal 2.5 V reference
1 MSamples/s, 12-bit, differen-
--
tial, 5 V reference
1 MSamples/s, 12-bit, differen-
--
tial, VDD reference
1 MSamples/s, 12-bit, differen-
--
tial, 2xVDD reference
200 kSamples/s, 12-bit, single-
--
ended, internal 1.25 V reference
200 kSamples/s, 12-bit, single-
--
ended, internal 2.5 V reference
200 kSamples/s, 12-bit, single-
--
ended, VDD reference
200 kSamples/s, 12-bit, differ-
--
ential, internal 1.25 V reference
200 kSamples/s, 12-bit, differ-
--
ential, internal 2.5 V reference
200 kSamples/s, 12-bit, differ-
--
ential, 5V reference
200 kSamples/s, 12-bit, differ-
62
ential, VDD reference
200 kSamples/s, 12-bit, differ-
--
ential, 2xVDD reference
EFM32LG Data Sheet
Electrical Characteristics
Typ
Max
Unit
58
--
dB
62
--
dB
64
--
dB
60
--
dB
64
--
dB
54
--
dB
66
--
dB
68
--
dB
61
--
dB
65
--
dB
66
--
dB
63
--
dB
66
--
dB
66
--
dB
66
--
dB
69
--
dB
silabs.com | Building a more connected world.
Rev. 2.30 | 93
Parameter Spurious-Free Dynamic Range (SFDR)
Offset voltage Thermometer output gradient Differential non-linearity (DNL) Integral non-linearity (INL), End point method Missing codes Gain error drift
EFM32LG Data Sheet
Electrical Characteristics
Symbol SFDRADC
VADCOFFSET TGRADADCTH
DNLADC INLADC MCADC GAINED
Test Condition
Min
1 MSamples/s, 12-bit, single-
--
ended, internal 1.25 V reference
1 MSamples/s, 12-bit, single-
--
ended, internal 2.5 V reference
1 MSamples/s, 12-bit, single-
--
ended, VDD reference
1 MSamples/s, 12-bit, differen-
--
tial, internal 1.25 V reference
1 MSamples/s, 12-bit, differen-
--
tial, internal 2.5 V reference
1 MSamples/s, 12-bit, differen-
--
tial, VDD reference
1 MSamples/s, 12-bit, differen-
--
tial, 2xVDD reference
1 MSamples/s, 12-bit, differen-
--
tial, 5 V reference
200 kSamples/s, 12-bit, single-
--
ended, internal 1.25 V reference
200 kSamples/s, 12-bit, single-
--
ended, internal 2.5 V reference
200 kSamples/s, 12-bit, single-
--
ended, VDD reference
200 kSamples/s, 12-bit, differ-
--
ential, internal 1.25 V reference
200 kSamples/s, 12-bit, differ-
--
ential, internal 2.5 V reference
200 kSamples/s, 12-bit, differ-
--
ential, 5 V reference
200 kSamples/s, 12-bit, differ-
68
ential, VDD reference
200 kSamples/s, 12-bit, differ-
--
ential, 2xVDD reference
After calibration, single-ended
-3.5
After calibration, differential
--
--
--
Typ 64 76 73 66 77 76 75 69 75 75 76 79 79 78 79 79 0.3 0.3 -1.92 -6.3
VDD= 3.0 V, external 2.5 V reference VDD= 3.0 V, external 2.5 V reference
1.25 V reference 2.5 V reference
-1
--
11.999 2 -- --
±0.7
±1.2
12 0.01 3 0.01 3
Max
Unit
--
dBc
--
dBc
--
dBc
--
dBc
--
dBc
--
dBc
--
dBc
--
dBc
--
dBc
--
dBc
--
dBc
--
dBc
--
dBc
--
dBc
--
dBc
--
dBc
3
mV
--
mV
--
mV/°C
-- ADC Codes/°C
4
LSB
±3
LSB
-- 0.033 4 0.03 4
bits %/°C %/°C
silabs.com | Building a more connected world.
Rev. 2.30 | 94
EFM32LG Data Sheet
Electrical Characteristics
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Offset error drift
OFFSETED
1.25 V reference
--
0.2 3
0.7 4 LSB/°C
2.5 V reference
--
0.2 3
0.62 4 LSB/°C
VREF voltage
VREF
1.25 V reference 2.5 V reference
1.2
1.25
1.3
V
2.4
2.5
2.6
V
VREF voltage drift
VREF_VDRIFT
1.25 V reference
-12.4
2.9
18.2
mV/V
2.5 V reference, VDD > 2.5 V
-24.6
5.7
35.2
mV/V
VREF temperature drift
VREF_TDRIFT
1.25 V reference 2.5 V reference
-132
272
677
µV/°C
-231
545
1271
µV/°C
VREF current consumption
IVREF
1.25 V reference 2.5 V reference
--
67
97
µA
--
55
72
µA
ADC and DAC VREF matching
VREF_MATCH
1.25 V reference 2.5 V reference
--
99.85
--
%
--
100.01
--
%
Note:
1. Includes required contribution from the voltage reference.
2. On the average every ADC will have one missing code, most likely to appear around 2048 +/- n*512 where n can be a value in the set {-3, -2, -1, 1, 2, 3}. There will be no missing code around 2048, and in spite of the missing code the ADC will be monotonic at all times so that a response to a slowly increasing input will always be a slowly increasing output. Around the one code that is missing, the neighbor codes will look wider in the DNL plot. The spectra will show spurs on the level of -78dBc for a full-scale input for chips that have the missing code issue.
3. Typical numbers given by abs(Mean) / (85 - 25).
4. Max number given by (abs(Mean) + 3x stddev) / (85 - 25).
The integral non-linearity (INL) and differential non-linearity parameters are explained in the following two figures.
Digital output code
4095 4094 4093 4092
INL=|[(VD-VSS)/VLSBIDEAL] - D| where 0 < D < 2N- 1
Actual ADC tranfer function before offset and gain correction
Actual ADC tranfer function after offset and gain correction
INL Error (End Point INL)
3
Ideal transfer
curve
2
1
VOFFSET
0
Analog Input
Figure 4.24. Integral Non-Linearity (INL)
silabs.com | Building a more connected world.
Rev. 2.30 | 95
Digital output code
4095 4094 4093 4092
5 4 3 2 1 0
EFM32LG Data Sheet
Electrical Characteristics
DNL=|[(VD+1 - VD)/VLSBIDEAL] - 1| where 0 < D < 2N- 2
Full Scale Range
Example: Adjacent input value VD+1 corrresponds to digital output code D+1
Example: Input value VDcorrresponds to digital output code D
Actual transfer function with one missing code.
Ideal transfer curve
Code width =2 LSB DNL=1 LSB
0.5 LSB
Ideal spacing between two adjacent codes VLSBIDEAL=1 LSB
Ideal 50% Transition Point
Ideal Code Center
Analog Input
Figure 4.25. Differential Non-Linearity (DNL)
silabs.com | Building a more connected world.
Rev. 2.30 | 96
4.11.1 Typical Performance
1.25V Reference
EFM32LG Data Sheet
Electrical Characteristics
2.5V Reference
2XVDDVSS Reference
5VDIFF Reference
VDD Reference
Figure 4.26. ADC Frequency Spectrum, VDD = 3 V, Temp = 25 °C silabs.com | Building a more connected world.
Rev. 2.30 | 97
1.25V Reference
EFM32LG Data Sheet
Electrical Characteristics
2.5V Reference
2XVDDVSS Reference
5VDIFF Reference
VDD Reference
Figure 4.27. ADC Integral Linearity Error vs Code, VDD = 3 V, Temp = 25 °C silabs.com | Building a more connected world.
Rev. 2.30 | 98
1.25V Reference
EFM32LG Data Sheet
Electrical Characteristics
2.5V Reference
2XVDDVSS Reference
5VDIFF Reference
VDD Reference
Figure 4.28. ADC Differential Linearity Error vs Code, VDD = 3 V, Temp = 25 °C
silabs.com | Building a more connected world.
Rev. 2.30 | 99
Actual Offset [LSB]
EFM32LG Data Sheet
Electrical Characteristics
Offset vs Supply Voltage, Temp = 25°C
5
Vref=1V25
4
Vref=2V5
Vref=2XVDDVSS
3
Vref=5VDIFF
Vref=VDD
2
1
0
1
2
3
42.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
Vdd (V)
Actual Offset [LSB]
2.0 1.5 1.0 0.5 0.0 0.5 1.040
Offset vs Temperature, VDD = 3V
VRef=1V25 VRef=2V5 VRef=2XVDDVSS VRef=5VDIFF VRef=VDD
15
5
25
45
65
85
Temp (C)
Figure 4.29. ADC Absolute Offset, Common Mode = VDD/2
Signal to Noise Ratio (SNR)
71
Spurious-Free Dynamic Range (SFDR)
79.4
2XVDDVSS
70
79.2
Vdd 69
79.0
68 78.8
SFDR [dB]
67
5VDIFF
78.6
66
2V5
78.4 65
64
78.2
6340
1V25
15
5
25
45
65
85
Temperature [°C]
78.040
15
5
25
45
65
Temperature [°C]
Figure 4.30. ADC Dynamic Performance vs Temperature for all ADC References, VDD = 3 V
1V25 2VVd5d 2XVDDVSS
5VDIFF 85
SNR [dB]
silabs.com | Building a more connected world.
Rev. 2.30 | 100
Sensor readout
2600 2500
Vdd=2.0 Vdd=3.0 Vdd=3.8
2400
2300
2200
210040
25 15 5 5 15 25 35 45 55 65 75 85 Temperature [°C]
Figure 4.31. ADC Temperature Sensor Readout
EFM32LG Data Sheet
Electrical Characteristics
silabs.com | Building a more connected world.
Rev. 2.30 | 101
4.12 Digital Analog Converter (DAC)
Table 4.16. DAC
Parameter Output voltage range Output common mode voltage range Average active current
Sample rate
Symbol Test Condition VDACOUT VDD voltage reference, single-ended
VDD voltage reference, differential VDACCM
Min 0
-VDD 0
IDAC 500 kSamples/s, 12-bit, internal 1.25 V
--
reference, Continuous Mode
100 kSamples/s, 12-bit, internal 1.25 V
--
reference, Sample/Hold Mode
1 kSamples/s 12-bit, internal 1.25 V ref- -- erence, Sample/Off Mode
SRDAC
--
DAC clock frequency
fDAC Continuous Mode
--
Sample/Hold Mode
--
Sample/Off Mode
--
Clock cycles per conversion
CYCDAC-
--
CONV
Conversion time
tDACCONV
2
Settling time
tDACSET-
--
TLE
Signal-to-Noise Ratio (SNR)
SNRDAC 500 kSamples/s, 12-bit, single-ended,
--
internal 1.25 V reference
500 kSamples/s, 12-bit, single-ended,
--
internal 2.5 V reference
500 kSamples/s, 12-bit, differential, in-
--
ternal 1.25 V reference
500 kSamples/s, 12-bit, differential, in-
--
ternal 2.5V reference
500 kSamples/s, 12-bit, differential,
--
VDD reference
Signal-to-Noise plus Distortion SNDRDAC 500 kSamples/s, 12-bit, single-ended,
--
Ratio (SNDR)
internal 1.25 V reference
500 kSamples/s, 12-bit, single-ended,
--
internal 2.5 V reference
500 kSamples/s, 12-bit, differential, in-
--
ternal 1.25 V reference
500 kSamples/s, 12-bit, differential, in-
--
ternal 2.5 V reference
500 kSamples/s, 12-bit, differential,
--
VDD reference
EFM32LG Data Sheet
Electrical Characteristics
Typ -- -- -- 4001 2001 171 -- -- -- -- 2
-- 5
58 59 58 58 59
57 54 56 53 55
Max VDD VDD VDD
--
Unit V V V
µA
--
µA
--
µA
500
1000 250 250 --
ksamples/ s
kHz kHz kHz cycles
--
µs
--
µs
--
dB
--
dB
--
dB
--
dB
--
dB
--
dB
--
dB
--
dB
--
dB
--
dB
silabs.com | Building a more connected world.
Rev. 2.30 | 102
EFM32LG Data Sheet
Electrical Characteristics
Parameter
Symbol Test Condition
Min
Typ
Max
Unit
Spurious-Free Dynamic Range SFDRDAC 500 kSamples/s, 12-bit, single-ended,
--
62
--
dBc
(SFDR)
internal 1.25 V reference
500 kSamples/s, 12-bit, single-ended,
--
56
--
dBc
internal 2.5 V reference
500 kSamples/s, 12-bit, differential, in-
--
61
--
dBc
ternal 1.25 V reference
500 kSamples/s, 12-bit, differential, in-
--
55
--
dBc
ternal 2.5 V reference
500 kSamples/s, 12-bit, differential, VDD reference
--
60
--
dBc
Offset voltage, all packages except CSP
VDACOFF- After calibration, single-ended SET After calibration, differential
--
2
9
mV
--
2
--
mV
Offset voltage, CSP devices
VDACOFF- After calibration, single-ended SET After calibration, differential
--
2
--
mV
--
2
--
mV
Differential non-linearity
DNLDAC
--
±1
--
LSB
Integral non-linearity
INLDAC
--
±5
--
LSB
No missing codes
MCDAC
--
12
--
bits
Load current
ILOAD_DC
--
--
11
mA
VREF voltage
VREF
1.25 V reference 2.5 V reference
1.2
1.25
1.3
V
2.4
2.5
2.6
V
VREF voltage drift
VREF_VDR 1.25 V reference
IFT
2.5 V reference, VDD > 2.5 V
-12.4
2.3
18.2
mV/V
-24.6
5.3
35.2
mV/V
VREF temperature drift
VREF_TDR 1.25 V reference
IFT
2.5 V reference
-132
242
677
µV/°C
-231
507
1271
µV/°C
VREF current consumption
IVREF
1.25 V reference 2.5 V reference
--
67
97
µA
--
55
72
µA
ADC and DAC VREF matching
VREF_MAT 1.25 V reference
CH
2.5 V reference
--
99.85
--
%
--
100.01
--
%
Note: 1. Measured with a static input code and no loading on the output. Includes required contribution from the voltage reference.
silabs.com | Building a more connected world.
Rev. 2.30 | 103
4.13 Operational Amplifier (OPAMP)
Parameter Active Current
Symbol IOPAMP
Open Loop Gain
GOL
Table 4.17. OPAMP
Test Condition
(OPA2)BIASPROG=0xF,(OPA2)HALFBIAS=0x0, Unity Gain
(OPA2)BIASPROG=0x7,(OPA2)HALFBIAS=0x1, Unity Gain
(OPA2)BIASPROG=0x0,(OPA2)HALFBIAS=0x1, Unity Gain
(OPA2)BIASPROG=0x4,(OPA2)HALFBIAS=0x1, UnityGain
(OPA0)BIASPROG=0x0,(OPA0)HALFBIAS=0x1, UnityGain
(OPA0)BIASPROG=0x4,(OPA0)HALFBIAS=0x1, UnityGain
(OPA1)BIASPROG=0x0,(OPA1)HALFBIAS=0x1, UnityGain
(OPA1)BIASPROG=0x4,(OPA1)HALFBIAS=0x1, UnityGain
(OPA2)BIASPROG=0xF,(OPA2)HALFBIAS=0x0
(OPA2)BIASPROG=0x7,(OPA2)HALFBIAS=0x1
(OPA2)BIASPROG=0x0,(OPA2)HALFBIAS=0x1
EFM32LG Data Sheet
Electrical Characteristics
Min
Typ
Max
Unit
--
370
460
µA
--
95
135
µA
--
13
25
µA
--
63
87
µA
--
18
27
µA
--
68
96
µA
--
18
27
µA
--
67
96
µA
--
101
--
dB
--
98
--
dB
--
91
--
dB
silabs.com | Building a more connected world.
Rev. 2.30 | 104
Parameter
Gain Bandwidth Product
Symbol GBWOPAMP
Test Condition
(OPA0)BIASPROG=0x0,(OPA0)HALFBIAS=0x1, DC bias = 0.3 V
(OPA0)BIASPROG=0x0,(OPA0)HALFBIAS=0x1, DC bias = 1 V
(OPA0)BIASPROG=0x0,(OPA0)HALFBIAS=0x1, DC bias = 2 V
(OPA0)BIASPROG=0x0,(OPA0)HALFBIAS=0x1, DC bias = 2.7 V
(OPA0)BIASPROG=0x4,(OPA0)HALFBIAS=0x1, DC bias = 0.3 V
(OPA0)BIASPROG=0x4,(OPA0)HALFBIAS=0x1, DC bias = 1 V
(OPA0)BIASPROG=0x4,(OPA0)HALFBIAS=0x1, DC bias = 2 V
(OPA0)BIASPROG=0x4,(OPA0)HALFBIAS=0x1, DC bias = 2.7 V
(OPA1)BIASPROG=0x0,(OPA1)HALFBIAS=0x1, DC bias = 0.3 V
(OPA1)BIASPROG=0x0,(OPA1)HALFBIAS=0x1, DC bias = 1 V
(OPA1)BIASPROG=0x0,(OPA1)HALFBIAS=0x1, DC bias = 2 V
(OPA1)BIASPROG=0x0,(OPA1)HALFBIAS=0x1, DC bias = 2.7 V
(OPA1)BIASPROG=0x4,(OPA1)HALFBIAS=0x1, DC bias = 0.3 V
(OPA1)BIASPROG=0x4,(OPA1)HALFBIAS=0x1, DC bias = 1 V
(OPA1)BIASPROG=0x4,(OPA1)HALFBIAS=0x1, DC bias = 2 V
(OPA1)BIASPROG=0x4,(OPA1)HALFBIAS=0x1, DC bias = 2.7 V
(OPA2)BIASPROG=0x0,(OPA2)HALFBIAS=0x1, DC bias = 0.3 V
(OPA2)BIASPROG=0x0,(OPA2)HALFBIAS=0x1, DC bias = 1 V
(OPA2)BIASPROG=0x0,(OPA2)HALFBIAS=0x1, DC bias = 2 V
(OPA2)BIASPROG=0x0,(OPA2)HALFBIAS=0x1, DC bias = 2.7 V
(OPA2)BIASPROG=0x4,(OPA2)HALFBIAS=0x1, DC bias = 0.3 V
(OPA2)BIASPROG=0x4,(OPA2)HALFBIAS=0x1, DC bias = 1 V
(OPA2)BIASPROG=0x4,(OPA2)HALFBIAS=0x1, DC bias = 2 V
EFM32LG Data Sheet
Electrical Characteristics
Min
Typ
Max
--
0.3931
--
Unit MHz
--
0.4871
--
MHz
--
0.3921
--
MHz
--
0.3181
--
MHz
--
1.5951
--
MHz
--
2.6611
--
MHz
--
2.5661
--
MHz
--
1.7871
--
MHz
--
0.4601
--
MHz
--
0.4471
--
MHz
--
0.3721
--
MHz
--
0.2951
--
MHz
--
1.8901
--
MHz
--
2.8491
--
MHz
--
2.5611
--
MHz
--
1.7051
--
MHz
--
0.3391
--
MHz
--
0.4321
--
MHz
--
0.3471
--
MHz
--
0.2861
--
MHz
--
1.2711
--
MHz
--
1.4291
--
MHz
--
1.2831
--
MHz
silabs.com | Building a more connected world.
Rev. 2.30 | 105
Parameter Gain Bandwidth Product
Phase Margin
Input Resistance Load Resistance DC Load Current Input Voltage Output Voltage Input Offset Voltage, all packages except CSP
Input Offset Voltage, CSP devices
Input Offset Voltage Drift Input bias current Input offset current
Symbol GBWOPAMP
PMOPAMP
RINPUT RLOAD ILOAD_DC VINPUT VOUTPUT VOFFSET
VOFFSET
VOFFSET_DRIFT
Test Condition (OPA2)BIASPROG=0x4,(OPA2)HALFBIAS=0x1, DC bias = 2.7 V (OPA2)BIASPROG=0xF,(OPA2)HALFBIAS=0x0, DC bias = 1.5 V (OPA2)BIASPROG=0x7,(OPA2)HALFBIAS=0x1, DC bias = 1.5 V (OPA2)BIASPROG=0xF,(OPA2)HALFBIAS=0x0, CL = 75 pF (OPA2)BIASPROG=0x7,(OPA2)HALFBIAS=0x1, CL = 75 pF (OPA2)BIASPROG=0x0,(OPA2)HALFBIAS=0x1, CL = 75 pF
OPA0/1 OPA/2
OPAxHCMDIS=0
OPAxHCMDIS=1
(OPA0) Unity Gain, VSS<Vin<VDD, OPAxHCMDIS=0 (OPA1) Unity Gain, VSS<Vin<VDD, OPAxHCMDIS=0 (OPA2) Unity Gain, VSS<Vin<VDD, OPAxHCMDIS=0 (OPA2) Unity Gain, VSS<Vin<VDD-1.2,OPAxHCMDIS=1 (OPA0) Unity Gain, VSS<Vin<VDD, OPAxHCMDIS=0 (OPA1) Unity Gain, VSS<Vin<VDD, OPAxHCMDIS=0 (OPA2) Unity Gain, VSS<Vin<VDD, OPAxHCMDIS=0 (OPA2) Unity Gain, VSS<Vin<VDD-1.2,OPAxHCMDIS=1
I OPAMPBIASIN I OPAMPOFFSETI
VSS < VIN < VDD VSS < VIN < VDD
EFM32LG Data Sheet
Electrical Characteristics
Min
Typ
Max
--
1.1361
--
Unit MHz
--
6.12
--
MHz
--
1.82
--
MHz
--
64
--
º
--
58
--
º
--
58
--
º
-- 200 1000 -- VSS VSS VSS -13
100
--
M
--
--
--
--
--
11
mA
--
VDD
V
--
VDD-1.2
V
--
VDD
V
0
11
mV
-13
0.1
11
mV
-13
0
11
mV
--
1
--
mV
--
0
--
mV
--
0.1
--
mV
-13
0
11
mV
--
1
--
mV
--
--
0.02
mV/°C
-40
--
40
nA
-40
--
40
nA
silabs.com | Building a more connected world.
Rev. 2.30 | 106
Parameter Slew Rate
Voltage Noise
Symbol SROPAMP
NOPAMP
Test Condition
Min
(OPA2)BIASPROG=0xF,(OPA2)HALF-
--
BIAS=0x0, 70 pF load Rising (Simulated at
25 C and VDD=3 V)
(OPA2)BIASPROG=0x7,(OPA2)HALF-
--
BIAS=0x1, 70 pF load, Rising (Simulated at
25 °C and VDD = 3 V)
(OPA2)BIASPROG=0x0,(OPA2)HALF-
--
BIAS=0x1, 70 pF load, Rising
(OPA2)BIASPROG=0x0,(OPA2)HALF-
--
BIAS=0x1, 70 pF load, Falling
(OPA2)BIASPROG=0x4,(OPA2)HALF-
--
BIAS=0x1, 70 pF load, Rising
(OPA2)BIASPROG=0x4,(OPA2)HALF-
--
BIAS=0x1, 70 pF load, Falling
(OPA1)BIASPROG=0x0,(OPA1)HALF-
--
BIAS=0x1, 70 pF load, Rising
(OPA1)BIASPROG=0x0,(OPA1)HALF-
--
BIAS=0x1, 70 pF load, Falling
(OPA1)BIASPROG=0x4,(OPA1)HALF-
--
BIAS=0x1, 70 pF load, Rising
(OPA1)BIASPROG=0x4,(OPA1)HALF-
--
BIAS=0x1, 70 pF load, Falling
(OPA0)BIASPROG=0x0,(OPA0)HALF-
--
BIAS=0x1, 70 pF load, Rising
(OPA0)BIASPROG=0x0,(OPA0)HALF-
--
BIAS=0x1, 70 pF load, Falling
(OPA0)BIASPROG=0x4,(OPA0)HALF-
--
BIAS=0x1, 70 pF load, Rising
(OPA0)BIASPROG=0x4,(OPA0)HALF-
--
BIAS=0x1, 70 pF load, Falling
Vout = 1 V, RESSEL=0, 0.1 Hz<f<10 kHz,
--
OPAxHCMDIS=0
Vout = 1 V, RESSEL=0, 0.1 Hz<f<10 kHz,
--
OPAxHCMDIS=1
Vout=1V, RESSEL=0, 0.1 Hz<f<1 MHz,
--
OPAxHCMDIS=0
Vout=1V, RESSEL=0, 0.1 Hz<f<1 MHz,
--
OPAxHCMDIS=1
RESSEL=7, 0.1 Hz<f<10 kHz, OPAxHCM-
--
DIS=0
RESSEL=7, 0.1 Hz<f<10 kHz, OPAxHCM-
--
DIS=1
RESSEL=7, 0.1 Hz<f<1 MHz, OPAxHCM-
--
DIS=0
RESSEL=7, 0.1 Hz<f<1 MHz, OPAxHCM-
--
DIS=1
EFM32LG Data Sheet
Electrical Characteristics
Typ
Max
Unit
3.2
--
V/µs
0.8
--
V/µs
178 198 969 969 166 180 918 937 173 191 935 950 101 141 196 229 1230 2130 1630 2590
--
V/µs
--
V/µs
--
V/µs
--
V/µs
--
V/µs
--
V/µs
--
V/µs
--
V/µs
--
V/µs
--
V/µs
--
V/µs
--
V/µs
--
µVRMS
--
µVRMS
--
µVRMS
--
µVRMS
--
µVRMS
--
µVRMS
--
µVRMS
--
µVRMS
silabs.com | Building a more connected world.
Rev. 2.30 | 107
EFM32LG Data Sheet
Electrical Characteristics
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Note: 1. Measured with 70 pF load capacitance, 25 ºC, and 3 V, using a 100 mV p-p amplitude on the input signal. 2. Simulated with 70 pF load capacitance, 25 ºC, and 3 V, using a 1 mV p-p amplitude on the input signal.
Figure 4.32. OPAMP Common Mode Rejection Ratio
Figure 4.33. OPAMP Positive Power Supply Rejection Ratio
silabs.com | Building a more connected world.
Rev. 2.30 | 108
EFM32LG Data Sheet
Electrical Characteristics
Figure 4.34. OPAMP Negative Power Supply Rejection Ratio
Figure 4.35. OPAMP Voltage Noise Spectral Density(Unity Gain) Vout=1V
silabs.com | Building a more connected world.
Rev. 2.30 | 109
EFM32LG Data Sheet
Electrical Characteristics
Figure 4.36. OPAMP Voltage Noise Spectral Density(Non-Unity Gain)
silabs.com | Building a more connected world.
Rev. 2.30 | 110
4.14 Analog Comparator (ACMP)
Table 4.18. ACMP
Parameter Input voltage range Input bias current Input offset current ACMP Common Mode voltage range Active current
Current consumption of internal voltage reference
Symbol VACMPIN I ACMPBIASIN IACMPOFFSETIN VACMPCM
Test Condition
VSS < VIN < VDD VSS < VIN < VDD
IACMP IACMPREF
BIASPROG=0b0000, FULLBIAS=0 and HALFBIAS=1 in ACMPn_CTRL register
BIASPROG=0b1111, FULLBIAS= 0 and HALFBIAS=0 in ACMPn_CTRL register
BIASPROG=0b1111, FULLBIAS= 1 and HALFBIAS=0 in ACMPn_CTRL register
BIASPROG=0b0100, FULLBIAS=0, HALFBIAS=1 in ACMPn_CTRL register
BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1 inACMPn_CTRL register
Internal voltage reference off. Using external voltage reference
Internal voltage reference
EFM32LG Data Sheet
Electrical Characteristics
Min
Typ
Max
Unit
0
--
VDD
V
-40
--
40
nA
-40
--
40
nA
0
--
VDD
V
--
0.11
0.41
µA
--
2.871
151
µA
--
1951
5201
µA
--
0.81
2.21
µA
--
2.71
8.11
µA
--
0
--
µA
--
5
--
µA
silabs.com | Building a more connected world.
Rev. 2.30 | 111
Parameter Negative response time
EFM32LG Data Sheet
Electrical Characteristics
Symbol
Test Condition
Min
Typ
Max
Unit
t RESPONSE_N
BIASPROG=0b1111, FULL-
--
353
--
ns
BIAS=0, HALFBIAS=1, Over-
drive = 100 mV, LPREF=0,
HYSTSEL=0
BIASPROG=0b1111, FULL-
--
547
--
ns
BIAS=0, HALFBIAS=1, Over-
drive = 100 mV, LPREF=0,
HYSTSEL=1
BIASPROG=0b1111, FULL-
--
578
--
ns
BIAS=0, HALFBIAS=1, Over-
drive = 100 mV, LPREF=0,
HYSTSEL=2
BIASPROG=0b1111, FULL-
--
627
--
ns
BIAS=0, HALFBIAS=1, Over-
drive = 100 mV, LPREF=0,
HYSTSEL=3
BIASPROG=0b1111, FULL-
--
670
--
ns
BIAS=0, HALFBIAS=1, Over-
drive = 100 mV, LPREF=0,
HYSTSEL=4
BIASPROG=0b1111, FULL-
--
741
--
ns
BIAS=0, HALFBIAS=1, Over-
drive = 100 mV, LPREF=0,
HYSTSEL=5
BIASPROG=0b1111, FULL-
--
811
--
ns
BIAS=0, HALFBIAS=1, Over-
drive = 100 mV, LPREF=0,
HYSTSEL=6
BIASPROG=0b1111, FULL-
--
926
--
ns
BIAS=0, HALFBIAS=1, Over-
drive = 100 mV, LPREF=0,
HYSTSEL=7
silabs.com | Building a more connected world.
Rev. 2.30 | 112
Parameter Negative response time
Symbol t RESPONSE_N
Test Condition
BIASPROG=0b0100, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=0
BIASPROG=0b0100, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=1
BIASPROG=0b0100, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=2
BIASPROG=0b0100, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=3
BIASPROG=0b0100, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=4
BIASPROG=0b0100, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=5
BIASPROG=0b0100, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=6
BIASPROG=0b0100, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=7
EFM32LG Data Sheet
Electrical Characteristics
Min
Typ
Max
Unit
--
843
--
ns
--
1499
--
ns
--
1590
--
ns
--
1746
--
ns
--
1876
--
ns
--
2104
--
ns
--
2323
--
ns
--
2691
--
ns
silabs.com | Building a more connected world.
Rev. 2.30 | 113
Parameter Positive response time
Symbol t RESPONSE_P
Test Condition
BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=0
BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=1
BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=2
BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=3
BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=4
BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=5
BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=6
BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=7
EFM32LG Data Sheet
Electrical Characteristics
Min
Typ
Max
Unit
--
451
--
ns
--
643
--
ns
--
679
--
ns
--
725
--
ns
--
761
--
ns
--
826
--
ns
--
909
--
ns
--
1021
--
ns
silabs.com | Building a more connected world.
Rev. 2.30 | 114
Parameter Positive response time
Offset voltage
Symbol t RESPONSE_P
VACMPOFFSET
Test Condition
BIASPROG=0b0100, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=0
BIASPROG=0b0100, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=1
BIASPROG=0b0100, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=2
BIASPROG=0b0100, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=3
BIASPROG=0b0100, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=4
BIASPROG=0b0100, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=5
BIASPROG=0b0100, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=6
BIASPROG=0b0100, FULLBIAS=0, HALFBIAS=1, Overdrive = 100 mV, LPREF=0, HYSTSEL=7
BIASPROG= 0b1010, FULLBIAS=0 and HALFBIAS=0 in ACMPn_CTRL register
BIASPROG= 0b0100, FULLBIAS=0, HALFBIAS=1, and LPREF=0 in ACMPn_CTRL register
BIASPROG= 0b1111, FULLBIAS=0, HALFBIAS=1, and LPREF=0 in ACMPn_CTRL register
EFM32LG Data Sheet
Electrical Characteristics
Min
Typ
Max
Unit
--
1014
--
ns
--
1671
--
ns
--
1786
--
ns
--
1933
--
ns
--
2046
--
ns
--
2262
--
ns
--
2531
--
ns
--
2907
--
ns
-12
0
12
mV
-14.4
0.4
14.8
mV
-13.3
0.3
13.2
mV
silabs.com | Building a more connected world.
Rev. 2.30 | 115
Parameter Negative hysteresis
Positive hysteresis
Symbol VACMPHYST_N
VACMPHYST_P
Test Condition
BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1,LPREF=0, HYSTSEL=0
BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1,LPREF=0, HYSTSEL=1
BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1,LPREF=0, HYSTSEL=2
BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1,LPREF=0, HYSTSEL=3
BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1,LPREF=0, HYSTSEL=4
BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1,LPREF=0, HYSTSEL=5
BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1,LPREF=0, HYSTSEL=6
BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1,LPREF=0, HYSTSEL=7
BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1,LPREF=0, HYSTSEL=0
BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1,LPREF=0, HYSTSEL=1
BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1,LPREF=0, HYSTSEL=2
BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1,LPREF=0, HYSTSEL=3
BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1,LPREF=0, HYSTSEL=4
BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1,LPREF=0, HYSTSEL=5
BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1,LPREF=0, HYSTSEL=6
BIASPROG=0b1111, FULLBIAS=0, HALFBIAS=1,LPREF=0, HYSTSEL=7
Min -0.3 -18.0 -25.0 -33.0 -40.0 -46.0 -56.0 -65.0 -0.3 4.0 9.0 13.0 17.0 20.0 25.0 29.4
EFM32LG Data Sheet
Electrical Characteristics
Typ
Max
Unit
1.2
4.0
mV
-12.2
-4.0
mV
-17.6
-9.0
mV
-22.8
-13.0
mV
-27.8
-16.0
mV
-33.4
-21.0
mV
-39.9
-25.0
mV
-46.4
-29.0
mV
1.2
4.0
mV
12.2
21.0
mV
17.1
25.0
mV
22.3
33.0
mV
28.2
42.0
mV
34.0
49.0
mV
39.8
58.0
mV
46.4
68.0
mV
silabs.com | Building a more connected world.
Rev. 2.30 | 116
Parameter
Capacitive Sense Internal Resistance
Symbol RCSRES
Startup time VDD_SCALED input accuracy
tACMPSTART V VDDSCALED
Note: 1. Reference current not included.
Test Condition
Min
CSRESSEL=0b00 in
--
ACMPn_INPUTSEL
CSRESSEL=0b01 in
--
ACMPn_INPUTSEL
CSRESSEL=0b10 in
--
ACMPn_INPUTSEL
CSRESSEL=0b11 in
--
ACMPn_INPUTSEL
--
VDD_SCALED=9,BIA-
--
SPROG=0b1111, FULLBIAS=0,
HALFBIAS=1, HYSTSEL=0,
LPREF=0
VDD_SCALED=9,BIA-
--
SPROG=0b0000, FULLBIAS=0,
HALFBIAS=1, HYSTSEL=0,
LPREF=1
EFM32LG Data Sheet
Electrical Characteristics
Typ
Max
Unit
39
--
k
71
--
k
104
--
k
136
--
k
--
10
µs
-10.8
--
mV
1.3
--
mV
The total ACMP current is the sum of the contributions from the ACMP and its internal voltage reference as given in in the following equation. IACMPREF is zero if an external voltage reference is used.
IACMPTOTAL = IACMP + IACMPREF
silabs.com | Building a more connected world.
Rev. 2.30 | 117
Current [uA]
EFM32LG Data Sheet
Electrical Characteristics
Current Consumption, HYSTSEL = 4
2.5
2.0
1.5
1.0
0.5
0.0 0
4
8
12
ACMP_CTRL_BIASPROG
Hysteresis
100
BIASPROG=0.0
BIASPROG=4.0
BIASPROG=8.0
80
BIASPROG=12.0
Response Time [us]
Response Time
4.5
HYSTSEL=0.0
4.0
HYSTSEL=2.0
HYSTSEL=4.0
3.5
HYSTSEL=6.0
3.0
2.5
2.0
1.5
1.0
0.5
0.0 0
2
4
6
8
10
12
14
ACMP_CTRL_BIASPROG
60
40
20
00
1
2
3
4
5
6
7
ACMP_CTRL_HYSTSEL
Figure 4.37. ACMP Characteristics, Vdd = 3 V, Temp = 25 °C, FULLBIAS = 0, HALFBIAS = 1
Hysteresis [mV]
silabs.com | Building a more connected world.
Rev. 2.30 | 118
4.15 Voltage Comparator (VCMP)
EFM32LG Data Sheet
Electrical Characteristics
Table 4.19. VCMP
Parameter
Symbol
Test Condition
Input voltage range
VVCMPIN
VCMP Common Mode voltage range
VVCMPCM
Active current
IVCMP
BIASPROG=0b0000 and HALFBIAS=1 in VCMPn_CTRL register
BIASPROG=0b1111 and HALFBIAS=0 in VCMPn_CTRL register. LPREF=0.
Startup time reference generator
tVCMPREF
NORMAL
Offset voltage
VVCMPOFFSET
Single-ended Differential
Negative hysteresis
VVCMPHYST_N
BIASPROG=0b0000, HALFBIAS=1, LPREF=1
Positive hysteresis
VVCMPHYST_P
BIASPROG=0b0000, HALFBIAS=1, LPREF=1
Hysteresis delta
VVCMPHYST_DELTA BIASPROG=0b0000, HALFBIAS=1, LPREF=1
Startup time
tVCMPSTART
Negative response time
tRESPONSE_N
BIASPROG=0b0000, HALFBIAS=1, LPREF=1, HYSTSEL=0
Positive response time
t RESPONSE_P
BIASPROG=0b0000, HALFBIAS=1, LPREF=1, HYSTSEL=0
Note: 1. Includes required contribution from the voltage reference.
Min -- -- --
--
-- -- -- -46.6 -7.5 4.2 -- --
--
Typ VDD VDD 0.31
221
10 10 10 -15.6 23.4 35.2 -- 372.3
865.7
Max -- -- 0.61
351
-- -- -- 11.4 46.6 70.0 10 --
--
Unit V V µA
µA
µs mV mV mV mV mV µs µs
µs
The VDD trigger level can be configured by setting the TRIGLEVEL field of the VCMP_CTRL register in accordance with the following equation:
V DD Trigger Level = 1.667V + 0.034 × TRIGLEVEL
silabs.com | Building a more connected world.
Rev. 2.30 | 119
4.16 EBI
EFM32LG Data Sheet
Electrical Characteristics
EBI_BL[N-1:0] EBI_A[N-1:0] EBI_AD[15:0] EBI_CSn EBI_WEn
WRSETUP (0, 1, 2, ...)
WRSTRB (1, 2, 3, ...)
WRHOLD (0, 1, 2, ...)
EBI_BL tOSU_WEn
Z tOH_WEn
EBI_A tOSU_WEn
Z tOH_WEn
DATA[15:0] tOSU_WEn
Z tOH_WEn
tOSU_WEn
tWIDTH_WEn
tOH_WEn
Figure 4.38. EBI Write Enable Timing Table 4.20. EBI Write Enable Timing
Parameter
Symbol
Min
Typ Max Unit
Output hold time, from trailing EBI_WEn/EBI_NANDWEn edge to EBI_AD, EBI_A, EBI_CSn, EBI_BLn invalid
tOH_WEn 1 2 3 4
-6.00 + (WRHOLD × tHFCORECLK)
-- -- ns
Output setup time, from EBI_AD, EBI_A, EBI_CSn, tOSU_WEn 1 2 3 4 5 -14.00 + (WRSETUP × tHFCORECLK) -- -- ns EBI_BLn valid to leading EBI_WEn/EBI_NANDWEn edge
EBI_WEn/EBI_NANDWEn pulse width
tWIDTH_WEn 1 2 3 4 -7.00 + ((WRSTRB + 1) × tHFCORECLK) -- -- ns
5
Note: 1. Applies for all addressing modes (figure only shows D16 addressing mode) 2. Applies for both EBI_WEn and EBI_NANWEn (figure only shows EBI_WEn) 3. Applies for all polarities (figure only shows active low signals) 4. Measurement done at 10% and 90% of VDD (figure shows 50% of VDD)
5. The figure shows the timing for the case that the half strobe length functionality is not used, i.e. HALFWE=0. The leading edge of EBI_WEn can be moved to the right by setting HALFWE=1. This decreases the length of tWIDTH_WEn and increases the length of tOSU_WEn by 1/2 × tHFCLKNODIV.
silabs.com | Building a more connected world.
Rev. 2.30 | 120
EFM32LG Data Sheet
Electrical Characteristics
EBI_AD[15:0] EBI_ALE EBI_CSn EBI_WEn
ADDRSETUP (1, 2, 3, ...)
ADDR[16:1]
tWIDTH_ALEn tOSU_ALEn
ADDRHOLD (0, 1, 2, ...)
tWIDTH_ALEn
WRSETUP (0, 1, 2, ...)
WRSTRB (1, 2, 3, ...)
DATA[15:0]
WRHOLD (0, 1, 2, ...)
Z
Figure 4.39. EBI Address Latch Enable Related Output Timing Table 4.21. EBI Address Latch Enable Related Output Timing
Parameter
Symbol
Min
Typ Max Unit
Output hold time, from trailing EBI_ALE edge to EBI_AD invalid
tOH_ALEn 1 2 3 4
-6.00 + (ADDRHOLD5 × tHFCORECLK)
--
--
ns
Output setup time, from EBI_AD valid to leading EBI_ALE edge
tOSU_ALEn 1 2 4
-13.00 + (0 × tHFCORECLK)
--
--
ns
EBI_ALEn pulse width
tWIDTH_ALEn 1 2 3 4
-7.00 + ((ADDRSETUP + 1) × tHFCORECLK)
--
--
ns
Note: 1. Applies to addressing modes D8A24ALE and D16A16ALE (figure only shows D16A16ALE)
2. Applies for all polarities (figure only shows active low signals)
3. The figure shows the timing for the case that the half strobe length functionality is not used, i.e. HALFALE=0. The trailing edge of EBI_ALE can be moved to the left by setting HALFALE=1. This decreases the length of tWIDTH_ALEn and increases the length of tOH_ALEn by tHFCORECLK - 1/2 × tHFCLKNODIV.
4. Measurement done at 10% and 90% of VDD (figure shows 50% of VDD)
5. Figure only shows a write operation. For a multiplexed read operation the address hold time is controlled via the RDSETUP state instead of via the ADDRHOLD state.
silabs.com | Building a more connected world.
Rev. 2.30 | 121
EFM32LG Data Sheet
Electrical Characteristics
EBI_BL[1:0] EBI_A[27:0] EBI_AD[15:8]
EBI_CSn EBI_AD[7:0]
EBI_REn
RDSETUP (0, 1, 2, ...)
RDSTRB (1, 2, 3, ...)
RDHOLD (0, 1, 2, ...)
EBI_BL tSU_REn
Z tH_REn
EBI_A tSU_REn
Z tH_REn
ADDR[7:0] tSU_REn
Z tH_REn
tSU_REn Z
DATA[7:0]
tH_REn Z
tWIDTH_REn
Figure 4.40. EBI Read Enable Related Output Timing Table 4.22. EBI Read Enable Related Output Timing
Parameter
Symbol
Min
Typ Max Unit
Output hold time, from trailing EBI_REn/EBI_NANDREn edge to EBI_AD, EBI_A, EBI_CSn, EBI_BLn invalid
tOH_REn 1 2 3 4
-10.00 + (RDHOLD × tHFCORECLK)
----
ns
Output setup time, from EBI_AD, EBI_A, EBI_CSn, EBI_BLn valid to leading EBI_REn/ EBI_NANDREn edge
tOSU_REn 1 2 3 4 5
-10.00 + (RDSETUP × tHFCORECLK)
----
ns
EBI_REn pulse width
tWIDTH_REn 1 2 3 4 5 6
-9.00 + ((RDSTRB + 1) × tHFCORECLK)
----
ns
Note: 1. Applies for all addressing modes (figure only shows D8A8. Output timing for EBI_AD only applies to multiplexed addressing modes D8A24ALE and D16A16ALE)
2. Applies for both EBI_REn and EBI_NANDREn (figure only shows EBI_REn)
3. Applies for all polarities (figure only shows active low signals)
4. Measurement done at 10% and 90% of VDD (figure shows 50% of VDD)
5. The figure shows the timing for the case that the half strobe length functionality is not used, i.e. HALFRE=0. The leading edge of EBI_REn can be moved to the right by setting HALFRE=1. This decreases the length of tWIDTH_REn and increases the length of tOSU_REn by 1/2 × tHFCLKNODIV.
6. When page mode is used, RDSTRB is replaced by RDPA for page hits.
silabs.com | Building a more connected world.
Rev. 2.30 | 122
EFM32LG Data Sheet
Electrical Characteristics
EBI_A[N-1:0] EBI_AD[15:0]
EBI_CSn EBI_REn
RDSETUP (0, 1, 2, ...)
RDSTRB (1, 2, 3, ...)
RDHOLD (0, 1, 2, ...)
ADDR[N:1]
Z
Z
DATA[15:0]
Z
tSU_REn
tH_REn
Figure 4.41. EBI Read Enable Related Timing Requirements Table 4.23. EBI Read Enable Related Timing Requirements
Parameter
Symbol
Min
Setup time, from EBI_AD valid to
tSU_REn 1 2 3 4
37
trailing EBI_REn edge
Hold time, from trailing EBI_REn
tH_REn 1 2 3 4
-1
edge to EBI_AD invalid
Note: 1. Applies for all addressing modes (figure only shows D16A8). 2. Applies for both EBI_REn and EBI_NANDREn (figure only shows EBI_REn) 3. Applies for all polarities (figure only shows active low signals) 4. Measurement done at 10% and 90% of VDD (figure shows 50% of VDD)
Typ Max Unit
--
--
ns
--
--
ns
EBI_RDY EBI_AD[15:0]
EBI_CSn EBI_REn
RDSETUP (0, 1, 2, ...)
RDSTRB (1, 2, 3, ...)
Z
SYNC (3)
RDHOLD (0, 1, 2, ...)
DATA[15:0]
tSU_ARDY
tH_ARDY
Figure 4.42. EBI Ready/Wait Related Timing Requirements
silabs.com | Building a more connected world.
Rev. 2.30 | 123
Table 4.24. EBI Ready/Wait Related Timing Requirements
Parameter
Symbol
Min
Setup time, from EBI_ARDY valid to trailing EBI_REn, EBI_WEn edge
tSU_ARDY 1 2 3 4
37 + (3 × tHFCORECLK)
Hold time, from trailing EBI_REn, EBI_WEn edge to EBI_ARDY invalid
tH_ARDY 1 2 3 4
-1 + (3 × tHFCORECLK)
Note: 1. Applies for all addressing modes (figure only shows D16A8.) 2. Applies for EBI_REn, EBI_WEn (figure only shows EBI_REn) 3. Applies for all polarities (figure only shows active low signals) 4. Measurement done at 10% and 90% of VDD (figure shows 50% of VDD)
EFM32LG Data Sheet
Electrical Characteristics
Typ Max Unit
--
--
ns
--
--
ns
silabs.com | Building a more connected world.
Rev. 2.30 | 124
4.17 LCD
EFM32LG Data Sheet
Electrical Characteristics
Table 4.25. LCD
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Frame rate
fLCDFR
30
--
200
Hz
Number of segments supported
NUMSEG
--
36×8
--
seg
LCD supply voltage range
VLCD
Internal boost circuit enabled
2.0
--
3.8
V
Steady state current consumption.
ILCD
Display disconnected, static
--
250
--
nA
mode, framerate 32 Hz, all
segments on.
Display disconnected, quad-
--
550
--
nA
ruplex mode, framerate 32
Hz, all segments on, bias
mode to ONETHIRD in
LCD_DISPCTRL register.
Steady state Current contribution
ILCDBOOST Internal voltage boost off
--
0
--
µA
of internal boost.
Internal voltage boost on,
--
8.4
--
µA
boosting from 2.2 V to 3.0 V.
Boost Voltage
VBOOST
VBLEV of LCD_DISPCTRL
--
3.02
--
V
register to LEVEL0
VBLEV of LCD_DISPCTRL
--
3.15
--
V
register to LEVEL1
VBLEV of LCD_DISPCTRL
--
3.28
--
V
register to LEVEL2
VBLEV of LCD_DISPCTRL
--
3.41
--
V
register to LEVEL3
VBLEV of LCD_DISPCTRL
--
3.54
--
V
register to LEVEL4
VBLEV of LCD_DISPCTRL
--
3.67
--
V
register to LEVEL5
VBLEV of LCD_DISPCTRL
--
3.73
--
V
register to LEVEL6
VBLEV of LCD_DISPCTRL
--
3.74
--
V
register to LEVEL7
The total LCD current is given by the following equation. ILCDBOOST is zero if internal boost is off. ILCDTOTAL = ILCD + ILCDBOOST
silabs.com | Building a more connected world.
Rev. 2.30 | 125
4.18 I2C
EFM32LG Data Sheet
Electrical Characteristics
Table 4.26. I2C Standard-mode (Sm)
Parameter
Symbol
Min
Typ
Max
Unit
SCL clock frequency
fSCL
0
--
1001
kHz
SCL clock low time
tLOW
4.7
--
--
µs
SCL clock high time
tHIGH
4.0
--
--
µs
SDA set-up time
tSU,DAT
250
--
--
ns
SDA hold time
tHD,DAT
8
--
34502,3
ns
Repeated START condition set-up time
tSU,STA
4.7
--
--
µs
(Repeated) START condition hold time
tHD,STA
4.0
--
--
µs
STOP condition set-up time
tSU,STO
4.0
--
--
µs
Bus free time between a STOP and a START condition
tBUF
4.7
--
--
µs
Note: 1. For the minimum HFPERCLK frequency required in Standard-mode, see the I2C chapter in the EFM32LG Reference Manual. 2. The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW). 3. When transmitting data, this number is guaranteed only when I2Cn_CLKDIV < ((3450*10-9 [s] * fHFPERCLK [Hz]) - 4).
Table 4.27. I2C Fast-mode (Fm)
Parameter
Symbol
Min
Typ
Max
Unit
SCL clock frequency
fSCL
0
4001
kHz
SCL clock low time
tLOW
1.3
µs
SCL clock high time
tHIGH
0.6
µs
SDA set-up time
tSU,DAT
100
ns
SDA hold time
tHD,DAT
8
9002,3
ns
Repeated START condition set-up time
tSU,STA
0.6
µs
(Repeated) START condition hold time
tHD,STA
0.6
µs
STOP condition set-up time
tSU,STO
0.6
µs
Bus free time between a STOP and a START condition
tBUF
1.3
µs
Note: 1. For the minimum HFPERCLK frequency required in Fast-mode, see the I2C chapter in the EFM32LG Reference Manual. 2. The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW). 3. When transmitting data, this number is guaranteed only when I2Cn_CLKDIV < ((900*10-9 [s] * fHFPERCLK [Hz]) - 4).
silabs.com | Building a more connected world.
Rev. 2.30 | 126
EFM32LG Data Sheet
Electrical Characteristics
Table 4.28. I2C Fast-mode Plus (Fm+)
Parameter
Symbol
Min
Typ
Max
Unit
SCL clock frequency
fSCL
0
10001
kHz
SCL clock low time
tLOW
0.5
µs
SCL clock high time
tHIGH
0.26
µs
SDA set-up time
tSU,DAT
50
ns
SDA hold time
tHD,DAT
8
ns
Repeated START condition set-up time
tSU,STA
0.26
µs
(Repeated) START condition hold time
tHD,STA
0.26
µs
STOP condition set-up time
tSU,STO
0.26
µs
Bus free time between a STOP and a START condition
tBUF
0.5
µs
Note: 1. For the minimum HFPERCLK frequency required in Fast-mode Plus, see the I2C chapter in the EFM32LG Reference Manual.
silabs.com | Building a more connected world.
Rev. 2.30 | 127
4.19 USART SPI
EFM32LG Data Sheet
Electrical Characteristics
CS
SCLK
CLKPOL = 0
SCLK
CLKPOL = 1
MOSI
MISO
tCS_MO
tSCKL_MO tSCLK
tSU_MI
tH_MI
Figure 4.43. SPI Master Timing Table 4.29. SPI Master Timing
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCLK period
tSCLK1 2
2 × tHFPERCLK
--
--
ns
CS to MOSI
tCS_MO 1 2
-2.00
--
2.00
ns
SCLK to MOSI
tSCLK_MO 1 2
-1.00
--
3.00
ns
MISO setup time
tSU_MI 1 2
IOVDD = 3.0 V
36.00
--
--
ns
MISO hold time
tH_MI 1 2
-6.00
--
--
ns
Note: 1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0) 2. Measurement done at 10% and 90% of VDD (figure shows 50% of VDD)
Table 4.30. SPI Master Timing with SSSEARLY and SMSDELAY
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCLK period
tSCLK1 2
2 × tHFPERCLK
--
--
ns
CS to MOSI
tCS_MO 1 2
-2.00
--
2.00
ns
SCLK to MOSI
tSCLK_MO 1 2
-1.00
--
3.00
ns
MISO setup time
tSU_MI 1 2
IOVDD = 3.0 V
-32.00
--
--
ns
MISO hold time
tH_MI 1 2
63.00
--
--
ns
Note: 1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0) 2. Measurement done at 10% and 90% of VDD (figure shows 50% of VDD)
silabs.com | Building a more connected world.
Rev. 2.30 | 128
EFM32LG Data Sheet
Electrical Characteristics
CS
SCLK
CLKPOL = 0
SCLK
CLKPOL = 1
MOSI
MISO
tCS_ACT_MI
tSU_MO
tH_MO
tSCLK_HI
tSCLK_LO
tSCLK
tSCLK_MI
tCS_DIS_MI
Figure 4.44. SPI Slave Timing Table 4.31. SPI Slave Timing
Parameter
Symbol
Min
Typ
SCKL period
tSCLK_sl1 2
6 × tHFPERCLK
--
SCLK high period
tSCLK_hi 1 2
3 × tHFPERCLK
--
SCLK low period
tSCLK_lo 1 2
3 × tHFPERCLK
--
CS active to MISO
tCS_ACT_MI 1 2
5.00
--
CS disable to MISO high-im-
tCS_DIS_MI 1 2
5.00
--
pedance
MOSI setup time
tSU_MO 1 2
5.00
--
MOSI hold time
tH_MO 1 2
2 + 2 × tHFPERCLK
--
SCLK to MISO
tSCLK_MI 1 2
7 + tHFPERCLK
--
Note: 1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0) 2. Measurement done at 10% and 90% of VDD (figure shows 50% of VDD)
Max -- -- -- 35.00 35.00
-- -- 42 + 2 × tHFPERCLK
Unit ns ns ns ns ns
ns ns ns
Parameter SCKL period SCLK high period SCLK low period CS active to MISO CS disable to MISO MOSI setup time MOSI hold time
Table 4.32. SPI Slave Timing with SSSEARLY and SMSDELAY
Symbol tSCLK_sl1 2 tSCLK_hi 1 2 tSCLK_lo 1 2 tCS_ACT_MI 1 2 tCS_DIS_MI 1 2 tSU_MO 1 2 tH_MO 1 2
Min 6 × tHFPERCLK 3 × tHFPERCLK 3 × tHFPERCLK
5.00 5.00 5.00 2 + 2 × tHFPERCLK
Typ -- -- -- -- -- -- --
Max -- -- -- 35.00 35.00 -- --
Unit ns ns ns ns ns ns ns
silabs.com | Building a more connected world.
Rev. 2.30 | 129
Parameter
Symbol
Min
Typ
SCLK to MISO
tSCLK_MI 1 2
-264 + tHFPERCLK
--
Note: 1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0) 2. Measurement done at 10% and 90% of VDD (figure shows 50% of VDD)
EFM32LG Data Sheet
Electrical Characteristics
Max -234 + 2 × tHFPERCLK
Unit ns
4.20 Digital Peripherals
Table 4.33. Digital Peripherals
Parameter USART current UART current LEUART current I2C current TIMER current LETIMER current PCNT current RTC current LCD current AES current GPIO current EBI current PRS current DMA current LE Peripheral Interface Clock current
Symbol Test Condition IUSART USART idle current, clock enabled IUART UART idle current, clock enabled ILEUART LEUART idle current, clock enabled
II2C I2C idle current, clock enabled ITIMER TIMER_0 idle current, clock enabled ILETIMER LETIMER idle current, clock enabled IPCNT PCNT idle current, clock enabled IRTC RTC idle current, clock enabled ILCD LCD idle current, clock enabled IAES AES idle current, clock enabled IGPIO GPIO idle current, clock enabled
IEBI EBI idle current, clock enabled IPRS PRS idle current IDMA Clock enable ILFCLK Using LFXO, LFA clock tree
Using LFXO, LFB clock tree
Min
Typ
Max
Unit
--
4.0
--
µA/MHz
--
3.8
--
µA/MHz
--
194.0
--
nA
--
7.6
--
µA/MHz
--
6.5
--
µA/MHz
--
85.8
--
nA
--
91.4
--
nA
--
54.6
--
nA
--
72.7
--
nA
--
1.8
--
µA/MHz
--
3.4
--
µA/MHz
--
6.5
--
µA/MHz
--
3.9
--
µA/MHz
--
10.9
--
µA/MHz
--
12.2
--
µA/MHz
--
4.3
--
µA/MHz
silabs.com | Building a more connected world.
Rev. 2.30 | 130
EFM32LG Data Sheet
Pin Definitions
5. Pin Definitions
Note: Refer to the application note, AN0002: EFM32 Hardware Design Considerations for guidelines on designing Printed Circuit Boards (PCBs) for the EFM32LG.
5.1 EFM32LG230 (QFN64)
5.1.1 Pinout The EFM32LG230 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question.
Figure 5.1. EFM32LG230 Pinout (top view, not to scale)
silabs.com | Building a more connected world.
Rev. 2.30 | 131
EFM32LG Data Sheet
Pin Definitions
Table 5.1. Device Pinout
QFN64 Pin# and Name
Pin #
Pin Name
0
VSS
1
PA0
2
PA1
3
PA2
4
PA3
5
PA4
6
PA5
7
PA6
8
IOVDD_0
9
PC0
10
PC1
11
PC2
12
PC3
13
PC4
14
PC5
15
PB7
16
PB8
17
PA8
18
PA9
19
PA10
20
RESETn
21
PB11
Pin Alternate Functionality / Description
Analog
Timers
Communication
Other
Ground.
TIM0_CC0 #0/1/4
LEU0_RX #4 I2C0_SDA #0
PRS_CH0 #0 GPIO_EM4WU0
TIM0_CC1 #0/1
I2C0_SCL #0
CMU_CLK1 #0 PRS_CH1 #0
TIM0_CC2 #0/1
CMU_CLK0 #0 ETM_TD0 #3
TIM0_CDTI0 #0
LES_ALTEX2 #0 ETM_TD1 #3
TIM0_CDTI1 #0
LES_ALTEX3 #0 ETM_TD2 #3
TIM0_CDTI2 #0
LEU1_TX #1
LES_ALTEX4 #0 ETM_TD3 #3
LEU1_RX #1
ETM_TCLK #3 GPIO_EM4WU1
Digital IO power supply 0.
ACMP0_CH0 DAC0_OUT0ALT #0/ OPAMP_OUT0ALT
TIM0_CC1 #4 PCNT0_S0IN #2
US0_TX #5 US1_TX #0 LES_CH0 #0 PRS_CH2
I2C0_SDA #4
#0
ACMP0_CH1 DAC0_OUT0ALT #1/ OPAMP_OUT0ALT
TIM0_CC2 #4 PCNT0_S1IN #2
US0_RX #5 US1_RX #0 LES_CH1 #0 PRS_CH3
I2C0_SCL #4
#0
ACMP0_CH2 DAC0_OUT0ALT #2/ OPAMP_OUT0ALT
TIM0_CDTI0 #4
US2_TX #0
LES_CH2 #0
ACMP0_CH3 DAC0_OUT0ALT #3/ OPAMP_OUT0ALT
TIM0_CDTI1 #4
US2_RX #0
LES_CH3 #0
ACMP0_CH4 / DAC0_P0 / OPAMP_P0
TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0
US2_CLK #0 I2C1_SDA #0
LES_CH4 #0
ACMP0_CH5 / DAC0_N0 / OPAMP_N0
LETIM0_OUT1 #3 PCNT1_S1IN #0
US2_CS #0 I2C1_SCL #0
LES_CH5 #0
LFXTAL_P
TIM1_CC0 #3
US0_TX #4 US1_CLK #0
LFXTAL_N
TIM1_CC1 #3
US0_RX #4 US1_CS #0
TIM2_CC0 #0
TIM2_CC1 #0
TIM2_CC2 #0
Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released.
DAC0_OUT0 / OPAMP_OUT0
TIM1_CC2 #3 LETIM0_OUT0 #1
I2C1_SDA #1
silabs.com | Building a more connected world.
Rev. 2.30 | 132
EFM32LG Data Sheet
Pin Definitions
QFN64 Pin# and Name
Pin #
Pin Name
22
PB12
23
AVDD_1
24
PB13
25
PB14
26
IOVDD_3
27
AVDD_0
28
PD0
29
PD1
30
PD2
31
PD3
32
PD4
33
PD5
34
PD6
35
PD7
36
PD8
37
PC6
38
PC7
39
VDD_DREG
40
DECOUPLE
41
PC8
42
PC9
43
PC10
44
PC11
45
PC12
Pin Alternate Functionality / Description
Analog
Timers
Communication
Other
DAC0_OUT1 / OPAMP_OUT1
LETIM0_OUT1 #1
I2C1_SCL #1
Analog power supply 1.
HFXTAL_P
US0_CLK #4/5 LEU0_TX #1
HFXTAL_N
US0_CS #4/5 LEU0_RX #1
Digital IO power supply 3.
Analog power supply 0.
ADC0_CH0 DAC0_OUT0ALT #4/ OPAMP_OUT0ALT
OPAMP_OUT2 #1
PCNT2_S0IN #0
US1_TX #1
ADC0_CH1 DAC0_OUT1ALT #4/ OPAMP_OUT1ALT
TIM0_CC0 #3 PCNT2_S1IN #0
US1_RX #1
DBG_SWO #2
ADC0_CH2
TIM0_CC1 #3
US1_CLK #1
DBG_SWO #3
ADC0_CH3 OPAMP_N2
TIM0_CC2 #3
US1_CS #1
ETM_TD1 #0/2
ADC0_CH4 OPAMP_P2
LEU0_TX #0
ETM_TD2 #0/2
ADC0_CH5 OPAMP_OUT2 #0
LEU0_RX #0
ETM_TD3 #0/2
ADC0_CH6 / DAC0_P1 / OPAMP_P1
TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3
US1_RX #2 I2C0_SDA #1
LES_ALTEX0 #0 ACMP0_O #2 ETM_TD0 #0
ADC0_CH7 / DAC0_N1 / OPAMP_N1
TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3
US1_TX #2 I2C0_SCL #1
CMU_CLK0 #2 LES_ALTEX1 #0
ACMP1_O #2 ETM_TCLK #0
BU_VIN
CMU_CLK1 #1
ACMP0_CH6
LEU1_TX #0 I2C0_SDA #2
LES_CH6 #0 ETM_TCLK #2
ACMP0_CH7
LEU1_RX #0 I2C0_SCL LES_CH7 #0 ETM_TD0
#2
#2
Power supply for on-chip voltage regulator.
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin.
ACMP1_CH0
TIM2_CC0 #2
US0_CS #2
LES_CH8 #0
ACMP1_CH1
TIM2_CC1 #2
US0_CLK #2
LES_CH9 #0 GPIO_EM4WU2
ACMP1_CH2
TIM2_CC2 #2
US0_RX #2
LES_CH10 #0
ACMP1_CH3
US0_TX #2
LES_CH11 #0
ACMP1_CH4 DAC0_OUT1ALT #0/ OPAMP_OUT1ALT
CMU_CLK0 #1 LES_CH12 #0
silabs.com | Building a more connected world.
Rev. 2.30 | 133
EFM32LG Data Sheet
Pin Definitions
QFN64 Pin# and Name
Pin #
Pin Name
46
PC13
47
PC14
48
PC15
49
PF0
50
PF1
51
PF2
52
PF3
53
PF4
54
PF5
55
IOVDD_5
56
PE8
57
PE9
58
PE10
59
PE11
60
PE12
61
PE13
62
PE14
63
PE15
64
PA15
Analog ACMP1_CH5 DAC0_OUT1ALT #1/ OPAMP_OUT1ALT ACMP1_CH6 DAC0_OUT1ALT #2/ OPAMP_OUT1ALT ACMP1_CH7 DAC0_OUT1ALT #3/ OPAMP_OUT1ALT
Digital IO power supply 5.
Pin Alternate Functionality / Description
Timers
Communication
TIM0_CDTI0 #1/3 TIM1_CC0 #0 TIM1_CC2 #4
PCNT0_S0IN #0
TIM0_CDTI1 #1/3 TIM1_CC1 #0
PCNT0_S1IN #0
US0_CS #3
Other LES_CH13 #0 LES_CH14 #0
TIM0_CDTI2 #1/3 TIM1_CC2 #0
US0_CLK #3
LES_CH15 #0 DBG_SWO #1
TIM0_CC0 #5 LETIM0_OUT0 #2
TIM0_CC1 #5 LETIM0_OUT1 #2
TIM0_CC2 #5
TIM0_CDTI0 #2/5
TIM0_CDTI1 #2/5 TIM0_CDTI2 #2/5
US1_CLK #2 LEU0_TX #3 I2C0_SDA #5
DBG_SWCLK #0/1/2/3
US1_CS #2 LEU0_RX DBG_SWDIO #0/1/2/3
#3 I2C0_SCL #5
GPIO_EM4WU3
LEU0_TX #4
ACMP1_O #0 DBG_SWO #0 GPIO_EM4WU4
PRS_CH0 #1 ETM_TD3 #1
PRS_CH1 #1
PRS_CH2 #1
PCNT2_S0IN #1 PCNT2_S1IN #1
TIM1_CC0 #1 TIM1_CC1 #1 TIM1_CC2 #1
TIM3_CC0 #0 TIM3_CC1 #0 TIM3_CC2 #0
US0_TX #0
US0_RX #0
US0_RX #3 US0_CLK #0 I2C0_SDA #6
US0_TX #3 US0_CS #0 I2C0_SCL #6
LEU0_TX #2 LEU0_RX #2
PRS_CH3 #1
BOOT_TX LES_ALTEX5 #0
BOOT_RX CMU_CLK1 #2 LES_ALTEX6 #0 LES_ALTEX7 #0 ACMP0_O #0 GPIO_EM4WU5
silabs.com | Building a more connected world.
Rev. 2.30 | 134
EFM32LG Data Sheet
Pin Definitions
5.1.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0.
Alternate Functionality ACMP0_CH0 ACMP0_CH1 ACMP0_CH2 ACMP0_CH3 ACMP0_CH4 ACMP0_CH5 ACMP0_CH6 ACMP0_CH7 ACMP0_O ACMP1_CH0 ACMP1_CH1 ACMP1_CH2 ACMP1_CH3 ACMP1_CH4 ACMP1_CH5 ACMP1_CH6 ACMP1_CH7 ACMP1_O
ADC0_CH0
0 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PE13 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PF2
PD0
ADC0_CH1
PD1
ADC0_CH2
PD2
ADC0_CH3
PD3
ADC0_CH4
PD4
ADC0_CH5
PD5
ADC0_CH6
PD6
Table 5.2. Alternate Functionality Overview
LOCATION
1
2
3
4
5
6
Description
Analog comparator ACMP0, channel 0.
Analog comparator ACMP0, channel 1.
Analog comparator ACMP0, channel 2.
Analog comparator ACMP0, channel 3.
Analog comparator ACMP0, channel 4.
Analog comparator ACMP0, channel 5.
Analog comparator ACMP0, channel 6.
Analog comparator ACMP0, channel 7.
PD6
Analog comparator ACMP0, digital output.
Analog comparator ACMP1, channel 0.
Analog comparator ACMP1, channel 1.
Analog comparator ACMP1, channel 2.
Analog comparator ACMP1, channel 3.
Analog comparator ACMP1, channel 4.
Analog comparator ACMP1, channel 5.
Analog comparator ACMP1, channel 6.
Analog comparator ACMP1, channel 7.
PD7
Analog comparator ACMP1, digital output.
Analog to digital converter ADC0, input channel number 0.
Analog to digital converter ADC0, input channel number 1.
Analog to digital converter ADC0, input channel number 2.
Analog to digital converter ADC0, input channel number 3.
Analog to digital converter ADC0, input channel number 4.
Analog to digital converter ADC0, input channel number 5.
Analog to digital converter ADC0, input channel number 6.
silabs.com | Building a more connected world.
Rev. 2.30 | 135
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
ADC0_CH7
PD7
Analog to digital converter ADC0, input channel number 7.
BOOT_RX
PE11
Bootloader RX.
BOOT_TX
PE10
Bootloader TX.
BU_VIN
PD8
Battery input for Backup Power Domain
CMU_CLK0
PA2 PC12 PD7
Clock Management Unit, clock output number 0.
CMU_CLK1
PA1 PD8 PE12
Clock Management Unit, clock output number 1.
DAC0_OUT0 / OPAMP_OUT0
PB11
Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0.
DAC0_OUT0ALT / OPAMP_OUT0A PC0 PC1 PC2 PC3 PD0 LT
Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0.
DAC0_OUT1 / OPAMP_OUT1
PB12
Digital to Analog Converter DAC0_OUT1 / OPAMP output channel number 1.
DAC0_OUT1ALT / OPAMP_OUT1A PC12 PC13 PC14 PC15 PD1 LT
Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1.
DBG_SWCLK PF0 PF0 PF0 PF0
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, and has a built-in pull down.
DBG_SWDIO PF1 PF1 PF1 PF1
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and has a built-in pull up.
DBG_SWO
PF2 PC15 PD1 PD2
Debug-interface Serial Wire viewer Output.
Note that this function is not enabled after reset, and must be enabled by software to be used.
ETM_TCLK
PD7
PC6 PA6
Embedded Trace Module ETM clock .
ETM_TD0
PD6
PC7 PA2
Embedded Trace Module ETM data 0.
ETM_TD1
PD3
PD3 PA3
Embedded Trace Module ETM data 1.
ETM_TD2
PD4
PD4 PA4
Embedded Trace Module ETM data 2.
ETM_TD3
PD5 PF3 PD5 PA5
Embedded Trace Module ETM data 3.
GPIO_EM4WU0 PA0
Pin can be used to wake the system up from EM4
GPIO_EM4WU1 PA6
Pin can be used to wake the system up from EM4
GPIO_EM4WU2 PC9
Pin can be used to wake the system up from EM4
GPIO_EM4WU3 PF1
Pin can be used to wake the system up from EM4
GPIO_EM4WU4 PF2
Pin can be used to wake the system up from EM4
GPIO_EM4WU5 PE13
Pin can be used to wake the system up from EM4
HFXTAL_N
PB14
High Frequency Crystal negative pin. Also used as external optional clock input pin.
HFXTAL_P
PB13
High Frequency Crystal positive pin.
silabs.com | Building a more connected world.
Rev. 2.30 | 136
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
I2C0_SCL
PA1 PD7 PC7
PC1 PF1 PE13 I2C0 Serial Clock Line input / output.
I2C0_SDA
PA0 PD6 PC6
PC0 PF0 PE12 I2C0 Serial Data input / output.
I2C1_SCL
PC5 PB12
I2C1 Serial Clock Line input / output.
I2C1_SDA
PC4 PB11
I2C1 Serial Data input / output.
LES_ALTEX0 PD6
LESENSE alternate exite output 0.
LES_ALTEX1 PD7
LESENSE alternate exite output 1.
LES_ALTEX2 PA3
LESENSE alternate exite output 2.
LES_ALTEX3 PA4
LESENSE alternate exite output 3.
LES_ALTEX4 PA5
LESENSE alternate exite output 4.
LES_ALTEX5 PE11
LESENSE alternate exite output 5.
LES_ALTEX6 PE12
LESENSE alternate exite output 6.
LES_ALTEX7 PE13
LESENSE alternate exite output 7.
LES_CH0
PC0
LESENSE channel 0.
LES_CH1
PC1
LESENSE channel 1.
LES_CH2
PC2
LESENSE channel 2.
LES_CH3
PC3
LESENSE channel 3.
LES_CH4
PC4
LESENSE channel 4.
LES_CH5
PC5
LESENSE channel 5.
LES_CH6
PC6
LESENSE channel 6.
LES_CH7
PC7
LESENSE channel 7.
LES_CH8
PC8
LESENSE channel 8.
LES_CH9
PC9
LESENSE channel 9.
LES_CH10
PC10
LESENSE channel 10.
LES_CH11
PC11
LESENSE channel 11.
LES_CH12
PC12
LESENSE channel 12.
LES_CH13
PC13
LESENSE channel 13.
LES_CH14
PC14
LESENSE channel 14.
LES_CH15
PC15
LESENSE channel 15.
LETIM0_OUT0 PD6 PB11 PF0 PC4
Low Energy Timer LETIM0, output channel 0.
LETIM0_OUT1 PD7 PB12 PF1 PC5
Low Energy Timer LETIM0, output channel 1.
LEU0_RX
PD5 PB14 PE15 PF1 PA0
LEUART0 Receive input.
LEU0_TX
PD4 PB13 PE14 PF0 PF2
LEUART0 Transmit output. Also used as receive input in half duplex communication.
LEU1_RX
PC7 PA6
LEUART1 Receive input.
LEU1_TX
PC6 PA5
LEUART1 Transmit output. Also used as receive input in half duplex communication.
silabs.com | Building a more connected world.
Rev. 2.30 | 137
Alternate
LOCATION
Functionality
0
1
2
3
4
5
LFXTAL_N
PB8
LFXTAL_P
PB7
OPAMP_N0 / DAC0_N0
PC5
OPAMP_N1 / DAC0_N1
PD7
OPAMP_N2
PD3
OPAMP_OUT2 PD5 PD0
OPAMP_P0 / DAC0_P0
PC4
OPAMP_P1 / DAC0_P1
PD6
OPAMP_P2
PD4
PCNT0_S0IN PC13
PC0 PD6
PCNT0_S1IN PC14
PC1 PD7
PCNT1_S0IN PC4
PCNT1_S1IN PC5
PCNT2_S0IN PD0 PE8
PCNT2_S1IN PD1 PE9
PRS_CH0
PA0 PF3
PRS_CH1
PA1 PF4
PRS_CH2
PC0 PF5
PRS_CH3
PC1 PE8
TIM0_CC0
PA0 PA0
PD1 PA0 PF0
TIM0_CC1
PA1 PA1
PD2 PC0 PF1
TIM0_CC2
PA2 PA2
PD3 PC1 PF2
TIM0_CDTI0
PA3 PC13 PF3 PC13 PC2 PF3
TIM0_CDTI1
PA4 PC14 PF4 PC14 PC3 PF4
TIM0_CDTI2
TIM1_CC0 TIM1_CC1 TIM1_CC2 TIM2_CC0 TIM2_CC1
PA5 PC15 PF5 PC15 PC4 PF5
PC13 PE10
PC14 PE11
PC15 PE12
PA8
PC8
PA9
PC9
PB7 PB8 PB11
PD6 PD7 PC13
silabs.com | Building a more connected world.
EFM32LG Data Sheet
Pin Definitions
6
Description
Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin.
Low Frequency Crystal (typically 32.768 kHz) positive pin.
Operational Amplifier 0 external negative input.
Operational Amplifier 1 external negative input. Operational Amplifier 2 external negative input. Operational Amplifier 2 output. Operational Amplifier 0 external positive input.
Operational Amplifier 1 external positive input.
Operational Amplifier 2 external positive input. Pulse Counter PCNT0 input number 0. Pulse Counter PCNT0 input number 1. Pulse Counter PCNT1 input number 0. Pulse Counter PCNT1 input number 1. Pulse Counter PCNT2 input number 0. Pulse Counter PCNT2 input number 1. Peripheral Reflex System PRS, channel 0. Peripheral Reflex System PRS, channel 1. Peripheral Reflex System PRS, channel 2. Peripheral Reflex System PRS, channel 3. Timer 0 Capture Compare input / output channel 0. Timer 0 Capture Compare input / output channel 1. Timer 0 Capture Compare input / output channel 2. Timer 0 Complimentary Deat Time Insertion channel 0. Timer 0 Complimentary Deat Time Insertion channel 1. Timer 0 Complimentary Deat Time Insertion channel 2. Timer 1 Capture Compare input / output channel 0. Timer 1 Capture Compare input / output channel 1. Timer 1 Capture Compare input / output channel 2. Timer 2 Capture Compare input / output channel 0. Timer 2 Capture Compare input / output channel 1.
Rev. 2.30 | 138
Alternate Functionality TIM2_CC2 TIM3_CC0 TIM3_CC1 TIM3_CC2 US0_CLK US0_CS
0 PA10 PE14 PE15 PA15 PE12 PE13
LOCATION
1
2
3
4
5
PC10
PC9 PC15 PB13 PB13 PC8 PC14 PB14 PB14
US0_RX
PE11
PC10 PE12 PB8 PC1
US0_TX
US1_CLK US1_CS US1_RX
PE10
PC11 PE13 PB7 PC0
PB7 PD2 PF0 PB8 PD3 PF1
PC1 PD1 PD6
US1_TX
US2_CLK US2_CS US2_RX
PC0 PD0 PD7
PC4 PC5 PC3
US2_TX
PC2
EFM32LG Data Sheet
Pin Definitions
6
Description
Timer 2 Capture Compare input / output channel 2.
Timer 3 Capture Compare input / output channel 0.
Timer 3 Capture Compare input / output channel 1.
Timer 3 Capture Compare input / output channel 2.
USART0 clock input / output.
USART0 chip select input / output.
USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output (MISO).
USART0 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input (MOSI).
USART1 clock input / output.
USART1 chip select input / output.
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output (MISO).
USART1 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input (MOSI).
USART2 clock input / output.
USART2 chip select input / output.
USART2 Asynchronous Receive.
USART2 Synchronous mode Master Input / Slave Output (MISO).
USART2 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART2 Synchronous mode Master Output / Slave Input (MOSI).
silabs.com | Building a more connected world.
Rev. 2.30 | 139
EFM32LG Data Sheet
Pin Definitions
5.1.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG230 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.3. GPIO Pinout
Port
Port A Port B Port C Port D Port E Port F
Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 15 14 13 12 11 10 PA15 -- -- -- -- PA10 PA9 PA8 -- PA6 PA5 PA4 PA3 PA2 PA1 PA0 -- PB14 PB13 PA12 PB11 -- -- PB8 PB7 -- -- -- -- -- -- -- PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 -- -- -- -- -- -- -- PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PF5 PF4 PF3 PF2 PF1 PF0
5.1.4 Opamp Pinout Overview
The specific opamp terminals available in EFM32LG230 is shown in the following figure.
PC4
+ OUT0ALT
OPA0 OUT0
PC5
-
PD4
+
PD3
OPA2 -
OUT2
PD6
+ OUT1ALT
PD7
OPA1 -
OUT1
PB11 PB12 PC0 PC1 PC2 PC3 PC12 PC13 PC14 PC15 PD0 PD1 PD5
Figure 5.2. Opamp Pinout
silabs.com | Building a more connected world.
Rev. 2.30 | 140
5.2 EFM32LG232 (TQFP64)
EFM32LG Data Sheet
Pin Definitions
5.2.1 Pinout
The EFM32LG232 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question.
Figure 5.3. EFM32LG232 Pinout (top view, not to scale) Table 5.4. Device Pinout
QFP64 Pin# and Name
Pin #
Pin Name
1
PA0
2
PA1
3
PA2
Analog
Pin Alternate Functionality / Description
Timers
Communication
TIM0_CC0 #0/1/4
LEU0_RX #4 I2C0_SDA #0
TIM0_CC1 #0/1
I2C0_SCL #0
TIM0_CC2 #0/1
Other
PRS_CH0 #0 GPIO_EM4WU0
CMU_CLK1 #0 PRS_CH1 #0
CMU_CLK0 #0 ETM_TD0 #3
silabs.com | Building a more connected world.
Rev. 2.30 | 141
EFM32LG Data Sheet
Pin Definitions
QFP64 Pin# and Name
Pin #
Pin Name
4
PA3
5
PA4
6
PA5
7
IOVDD_0
8
VSS
9
PC0
10
PC1
11
PC2
12
PC3
13
PC4
14
PC5
15
PB7
16
PB8
17
PA8
18
PA9
19
PA10
20
RESETn
21
PB11
22
VSS
23
AVDD_1
24
PB13
25
PB14
26
IOVDD_3
27
AVDD_0
Pin Alternate Functionality / Description
Analog
Timers
Communication
Other
TIM0_CDTI0 #0
LES_ALTEX2 #0 ETM_TD1 #3
TIM0_CDTI1 #0
LES_ALTEX3 #0 ETM_TD2 #3
TIM0_CDTI2 #0
LEU1_TX #1
LES_ALTEX4 #0 ETM_TD3 #3
Digital IO power supply 0.
Ground.
ACMP0_CH0 DAC0_OUT0ALT #0/ OPAMP_OUT0ALT
TIM0_CC1 #4 PCNT0_S0IN #2
US0_TX #5 US1_TX #0 LES_CH0 #0 PRS_CH2
I2C0_SDA #4
#0
ACMP0_CH1 DAC0_OUT0ALT #1/ OPAMP_OUT0ALT
TIM0_CC2 #4 PCNT0_S1IN #2
US0_RX #5 US1_RX #0 LES_CH1 #0 PRS_CH3
I2C0_SCL #4
#0
ACMP0_CH2 DAC0_OUT0ALT #2/ OPAMP_OUT0ALT
TIM0_CDTI0 #4
US2_TX #0
LES_CH2 #0
ACMP0_CH3 DAC0_OUT0ALT #3/ OPAMP_OUT0ALT
TIM0_CDTI1 #4
US2_RX #0
LES_CH3 #0
ACMP0_CH4 / DAC0_P0 / OPAMP_P0
TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0
US2_CLK #0 I2C1_SDA #0
LES_CH4 #0
ACMP0_CH5 / DAC0_N0 / OPAMP_N0
LETIM0_OUT1 #3 PCNT1_S1IN #0
US2_CS #0 I2C1_SCL #0
LES_CH5 #0
LFXTAL_P
TIM1_CC0 #3
US0_TX #4 US1_CLK #0
LFXTAL_N
TIM1_CC1 #3
US0_RX #4 US1_CS #0
TIM2_CC0 #0
TIM2_CC1 #0
TIM2_CC2 #0
Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released.
DAC0_OUT0 / OPAMP_OUT0
TIM1_CC2 #3 LETIM0_OUT0 #1
I2C1_SDA #1
Ground.
Analog power supply 1.
HFXTAL_P
US0_CLK #4/5 LEU0_TX #1
HFXTAL_N
US0_CS #4/5 LEU0_RX #1
Digital IO power supply 3.
Analog power supply 0.
silabs.com | Building a more connected world.
Rev. 2.30 | 142
EFM32LG Data Sheet
Pin Definitions
QFP64 Pin# and Name
Pin #
Pin Name
28
PD0
29
PD1
30
PD2
31
PD3
32
PD4
33
PD5
34
PD6
35
PD7
36
PD8
37
PC6
38
PC7
39
VDD_DREG
40
DECOUPLE
41
PC8
42
PC9
43
PC10
44
PC11
45
PC12
46
PC13
47
PC14
48
PC15
Pin Alternate Functionality / Description
Analog
Timers
Communication
Other
ADC0_CH0 DAC0_OUT0ALT #4/ OPAMP_OUT0ALT
OPAMP_OUT2 #1
PCNT2_S0IN #0
US1_TX #1
ADC0_CH1 DAC0_OUT1ALT #4/ OPAMP_OUT1ALT
TIM0_CC0 #3 PCNT2_S1IN #0
US1_RX #1
DBG_SWO #2
ADC0_CH2
TIM0_CC1 #3
US1_CLK #1
DBG_SWO #3
ADC0_CH3 OPAMP_N2
TIM0_CC2 #3
US1_CS #1
ETM_TD1 #0/2
ADC0_CH4 OPAMP_P2
LEU0_TX #0
ETM_TD2 #0/2
ADC0_CH5 OPAMP_OUT2 #0
LEU0_RX #0
ETM_TD3 #0/2
ADC0_CH6 / DAC0_P1 / OPAMP_P1
TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3
US1_RX #2 I2C0_SDA #1
LES_ALTEX0 #0 ACMP0_O #2 ETM_TD0 #0
ADC0_CH7 / DAC0_N1 / OPAMP_N1
TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3
US1_TX #2 I2C0_SCL #1
CMU_CLK0 #2 LES_ALTEX1 #0
ACMP1_O #2 ETM_TCLK #0
BU_VIN
CMU_CLK1 #1
ACMP0_CH6
LEU1_TX #0 I2C0_SDA #2
LES_CH6 #0 ETM_TCLK #2
ACMP0_CH7
LEU1_RX #0 I2C0_SCL LES_CH7 #0 ETM_TD0
#2
#2
Power supply for on-chip voltage regulator.
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin.
ACMP1_CH0
TIM2_CC0 #2
US0_CS #2
LES_CH8 #0
ACMP1_CH1
TIM2_CC1 #2
US0_CLK #2
LES_CH9 #0 GPIO_EM4WU2
ACMP1_CH2
TIM2_CC2 #2
US0_RX #2
LES_CH10 #0
ACMP1_CH3
US0_TX #2
LES_CH11 #0
ACMP1_CH4 DAC0_OUT1ALT #0/ OPAMP_OUT1ALT
CMU_CLK0 #1 LES_CH12 #0
ACMP1_CH5 DAC0_OUT1ALT #1/ OPAMP_OUT1ALT
TIM0_CDTI0 #1/3 TIM1_CC0 #0 TIM1_CC2 #4
PCNT0_S0IN #0
LES_CH13 #0
ACMP1_CH6 DAC0_OUT1ALT #2/ OPAMP_OUT1ALT
TIM0_CDTI1 #1/3 TIM1_CC1 #0
PCNT0_S1IN #0
US0_CS #3
LES_CH14 #0
ACMP1_CH7 DAC0_OUT1ALT #3/ OPAMP_OUT1ALT
TIM0_CDTI2 #1/3 TIM1_CC2 #0
US0_CLK #3
LES_CH15 #0 DBG_SWO #1
silabs.com | Building a more connected world.
Rev. 2.30 | 143
EFM32LG Data Sheet
Pin Definitions
QFP64 Pin# and Name
Pin #
Pin Name
49
PF0
50
PF1
51
PF2
52
PF3
53
PF4
54
PF5
55
IOVDD_5
56
VSS
57
PE8
58
PE9
59
PE10
60
PE11
61
PE12
62
PE13
63
PE14
64
PE15
Analog
Digital IO power supply 5. Ground.
Pin Alternate Functionality / Description
Timers
Communication
Other
TIM0_CC0 #5 LETIM0_OUT0 #2
US1_CLK #2 LEU0_TX #3 I2C0_SDA #5
DBG_SWCLK #0/1/2/3
TIM0_CC1 #5 LETIM0_OUT1 #2
US1_CS #2 LEU0_RX DBG_SWDIO #0/1/2/3
#3 I2C0_SCL #5
GPIO_EM4WU3
TIM0_CC2 #5
LEU0_TX #4
ACMP1_O #0 DBG_SWO #0 GPIO_EM4WU4
TIM0_CDTI0 #2/5
PRS_CH0 #1 ETM_TD3 #1
TIM0_CDTI1 #2/5
PRS_CH1 #1
TIM0_CDTI2 #2/5
PRS_CH2 #1
PCNT2_S0IN #1 PCNT2_S1IN #1
TIM1_CC0 #1 TIM1_CC1 #1 TIM1_CC2 #1
TIM3_CC0 #0 TIM3_CC1 #0
US0_TX #0
US0_RX #0
US0_RX #3 US0_CLK #0 I2C0_SDA #6
US0_TX #3 US0_CS #0 I2C0_SCL #6
LEU0_TX #2 LEU0_RX #2
PRS_CH3 #1
BOOT_TX LES_ALTEX5 #0
BOOT_RX CMU_CLK1 #2 LES_ALTEX6 #0 LES_ALTEX7 #0 ACMP0_O #0 GPIO_EM4WU5
silabs.com | Building a more connected world.
Rev. 2.30 | 144
EFM32LG Data Sheet
Pin Definitions
5.2.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0.
Alternate Functionality ACMP0_CH0 ACMP0_CH1 ACMP0_CH2 ACMP0_CH3 ACMP0_CH4 ACMP0_CH5 ACMP0_CH6 ACMP0_CH7 ACMP0_O ACMP1_CH0 ACMP1_CH1 ACMP1_CH2 ACMP1_CH3 ACMP1_CH4 ACMP1_CH5 ACMP1_CH6 ACMP1_CH7 ACMP1_O
ADC0_CH0
0 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PE13 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PF2
PD0
ADC0_CH1
PD1
ADC0_CH2
PD2
ADC0_CH3
PD3
ADC0_CH4
PD4
ADC0_CH5
PD5
ADC0_CH6
PD6
Table 5.5. Alternate Functionality Overview
LOCATION
1
2
3
4
5
6
Description
Analog comparator ACMP0, channel 0.
Analog comparator ACMP0, channel 1.
Analog comparator ACMP0, channel 2.
Analog comparator ACMP0, channel 3.
Analog comparator ACMP0, channel 4.
Analog comparator ACMP0, channel 5.
Analog comparator ACMP0, channel 6.
Analog comparator ACMP0, channel 7.
PD6
Analog comparator ACMP0, digital output.
Analog comparator ACMP1, channel 0.
Analog comparator ACMP1, channel 1.
Analog comparator ACMP1, channel 2.
Analog comparator ACMP1, channel 3.
Analog comparator ACMP1, channel 4.
Analog comparator ACMP1, channel 5.
Analog comparator ACMP1, channel 6.
Analog comparator ACMP1, channel 7.
PD7
Analog comparator ACMP1, digital output.
Analog to digital converter ADC0, input channel number 0.
Analog to digital converter ADC0, input channel number 1.
Analog to digital converter ADC0, input channel number 2.
Analog to digital converter ADC0, input channel number 3.
Analog to digital converter ADC0, input channel number 4.
Analog to digital converter ADC0, input channel number 5.
Analog to digital converter ADC0, input channel number 6.
silabs.com | Building a more connected world.
Rev. 2.30 | 145
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
ADC0_CH7
PD7
Analog to digital converter ADC0, input channel number 7.
BOOT_RX
PE11
Bootloader RX.
BOOT_TX
PE10
Bootloader TX.
BU_VIN
PD8
Battery input for Backup Power Domain
CMU_CLK0
PA2 PC12 PD7
Clock Management Unit, clock output number 0.
CMU_CLK1
PA1 PD8 PE12
Clock Management Unit, clock output number 1.
DAC0_OUT0 / OPAMP_OUT0
PB11
Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0.
DAC0_OUT0ALT / OPAMP_OUT0A PC0 PC1 PC2 PC3 PD0 LT
Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0.
DAC0_OUT1ALT / OPAMP_OUT1A PC12 PC13 PC14 PC15 PD1 LT
Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1.
DBG_SWCLK PF0 PF0 PF0 PF0
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, and has a built-in pull down.
DBG_SWDIO PF1 PF1 PF1 PF1
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and has a built-in pull up.
DBG_SWO
PF2 PC15 PD1 PD2
Debug-interface Serial Wire viewer Output.
Note that this function is not enabled after reset, and must be enabled by software to be used.
ETM_TCLK
PD7
PC6
Embedded Trace Module ETM clock .
ETM_TD0
PD6
PC7 PA2
Embedded Trace Module ETM data 0.
ETM_TD1
PD3
PD3 PA3
Embedded Trace Module ETM data 1.
ETM_TD2
PD4
PD4 PA4
Embedded Trace Module ETM data 2.
ETM_TD3
PD5 PF3 PD5 PA5
Embedded Trace Module ETM data 3.
GPIO_EM4WU0 PA0
Pin can be used to wake the system up from EM4
GPIO_EM4WU2 PC9
Pin can be used to wake the system up from EM4
GPIO_EM4WU3 PF1
Pin can be used to wake the system up from EM4
GPIO_EM4WU4 PF2
Pin can be used to wake the system up from EM4
GPIO_EM4WU5 PE13
Pin can be used to wake the system up from EM4
HFXTAL_N
PB14
High Frequency Crystal negative pin. Also used as external optional clock input pin.
HFXTAL_P
PB13
High Frequency Crystal positive pin.
I2C0_SCL
PA1 PD7 PC7
PC1 PF1 PE13 I2C0 Serial Clock Line input / output.
I2C0_SDA
PA0 PD6 PC6
PC0 PF0 PE12 I2C0 Serial Data input / output.
I2C1_SCL
PC5
I2C1 Serial Clock Line input / output.
silabs.com | Building a more connected world.
Rev. 2.30 | 146
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
I2C1_SDA
PC4
I2C1 Serial Data input / output.
LES_ALTEX0 PD6
LESENSE alternate exite output 0.
LES_ALTEX1 PD7
LESENSE alternate exite output 1.
LES_ALTEX2 PA3
LESENSE alternate exite output 2.
LES_ALTEX3 PA4
LESENSE alternate exite output 3.
LES_ALTEX4 PA5
LESENSE alternate exite output 4.
LES_ALTEX5 PE11
LESENSE alternate exite output 5.
LES_ALTEX6 PE12
LESENSE alternate exite output 6.
LES_ALTEX7 PE13
LESENSE alternate exite output 7.
LES_CH0
PC0
LESENSE channel 0.
LES_CH1
PC1
LESENSE channel 1.
LES_CH2
PC2
LESENSE channel 2.
LES_CH3
PC3
LESENSE channel 3.
LES_CH4
PC4
LESENSE channel 4.
LES_CH5
PC5
LESENSE channel 5.
LES_CH6
PC6
LESENSE channel 6.
LES_CH7
PC7
LESENSE channel 7.
LES_CH8
PC8
LESENSE channel 8.
LES_CH9
PC9
LESENSE channel 9.
LES_CH10
PC10
LESENSE channel 10.
LES_CH11
PC11
LESENSE channel 11.
LES_CH12
PC12
LESENSE channel 12.
LES_CH13
PC13
LESENSE channel 13.
LES_CH14
PC14
LESENSE channel 14.
LES_CH15
PC15
LESENSE channel 15.
LETIM0_OUT0 PD6 PB11 PF0 PC4
Low Energy Timer LETIM0, output channel 0.
LETIM0_OUT1 PD7
PF1 PC5
Low Energy Timer LETIM0, output channel 1.
LEU0_RX
PD5 PB14 PE15 PF1 PA0
LEUART0 Receive input.
LEU0_TX
PD4 PB13 PE14 PF0 PF2
LEUART0 Transmit output. Also used as receive input in half duplex communication.
LEU1_RX
PC7
LEUART1 Receive input.
LEU1_TX
PC6 PA5
LEUART1 Transmit output. Also used as receive input in half duplex communication.
LFXTAL_N
PB8
Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin.
LFXTAL_P
PB7
Low Frequency Crystal (typically 32.768 kHz) positive pin.
silabs.com | Building a more connected world.
Rev. 2.30 | 147
Alternate
LOCATION
Functionality
0
1
2
3
4
5
OPAMP_N0 / DAC0_N0
PC5
OPAMP_N1 / DAC0_N1
PD7
OPAMP_N2
PD3
OPAMP_OUT2 PD5 PD0
OPAMP_P0 / DAC0_P0
PC4
OPAMP_P1 / DAC0_P1
PD6
OPAMP_P2
PD4
PCNT0_S0IN PC13
PC0 PD6
PCNT0_S1IN PC14
PC1 PD7
PCNT1_S0IN PC4
PCNT1_S1IN PC5
PCNT2_S0IN PD0 PE8
PCNT2_S1IN PD1 PE9
PRS_CH0
PA0 PF3
PRS_CH1
PA1 PF4
PRS_CH2
PC0 PF5
PRS_CH3
PC1 PE8
TIM0_CC0
PA0 PA0
PD1 PA0 PF0
TIM0_CC1
PA1 PA1
PD2 PC0 PF1
TIM0_CC2
PA2 PA2
PD3 PC1 PF2
TIM0_CDTI0
PA3 PC13 PF3 PC13 PC2 PF3
TIM0_CDTI1
PA4 PC14 PF4 PC14 PC3 PF4
TIM0_CDTI2
TIM1_CC0 TIM1_CC1 TIM1_CC2 TIM2_CC0 TIM2_CC1 TIM2_CC2 TIM3_CC0 TIM3_CC1 US0_CLK
PA5 PC15 PF5 PC15 PC4 PF5
PC13 PC14 PC15 PA8 PA9 PA10 PE14 PE15 PE12
PE10 PE11 PE12
PC8 PC9 PC10
PC9
PB7 PB8 PB11
PC15
PD6 PD7 PC13
PB13
PB13
silabs.com | Building a more connected world.
EFM32LG Data Sheet
Pin Definitions
6
Description
Operational Amplifier 0 external negative input.
Operational Amplifier 1 external negative input. Operational Amplifier 2 external negative input. Operational Amplifier 2 output. Operational Amplifier 0 external positive input.
Operational Amplifier 1 external positive input.
Operational Amplifier 2 external positive input. Pulse Counter PCNT0 input number 0. Pulse Counter PCNT0 input number 1. Pulse Counter PCNT1 input number 0. Pulse Counter PCNT1 input number 1. Pulse Counter PCNT2 input number 0. Pulse Counter PCNT2 input number 1. Peripheral Reflex System PRS, channel 0. Peripheral Reflex System PRS, channel 1. Peripheral Reflex System PRS, channel 2. Peripheral Reflex System PRS, channel 3. Timer 0 Capture Compare input / output channel 0. Timer 0 Capture Compare input / output channel 1. Timer 0 Capture Compare input / output channel 2. Timer 0 Complimentary Deat Time Insertion channel 0. Timer 0 Complimentary Deat Time Insertion channel 1. Timer 0 Complimentary Deat Time Insertion channel 2. Timer 1 Capture Compare input / output channel 0. Timer 1 Capture Compare input / output channel 1. Timer 1 Capture Compare input / output channel 2. Timer 2 Capture Compare input / output channel 0. Timer 2 Capture Compare input / output channel 1. Timer 2 Capture Compare input / output channel 2. Timer 3 Capture Compare input / output channel 0. Timer 3 Capture Compare input / output channel 1. USART0 clock input / output.
Rev. 2.30 | 148
Alternate Functionality US0_CS
0 PE13
LOCATION
1
2
3
4
5
PC8 PC14 PB14 PB14
US0_RX
PE11
PC10 PE12 PB8 PC1
US0_TX
US1_CLK US1_CS US1_RX
PE10
PC11 PE13 PB7 PC0
PB7 PD2 PF0 PB8 PD3 PF1
PC1 PD1 PD6
US1_TX
US2_CLK US2_CS US2_RX
PC0 PD0 PD7
PC4 PC5 PC3
US2_TX
PC2
EFM32LG Data Sheet
Pin Definitions
6
Description
USART0 chip select input / output.
USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output (MISO).
USART0 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input (MOSI).
USART1 clock input / output.
USART1 chip select input / output.
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output (MISO).
USART1 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input (MOSI).
USART2 clock input / output.
USART2 chip select input / output.
USART2 Asynchronous Receive.
USART2 Synchronous mode Master Input / Slave Output (MISO).
USART2 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART2 Synchronous mode Master Output / Slave Input (MOSI).
5.2.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG232 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.6. GPIO Pinout
Port
Port A Port B Port C Port D Port E Port F
Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 15 14 13 12 11 10 -- -- -- -- -- PA10 PA9 PA8 -- -- PA5 PA4 PA3 PA2 PA1 PA0 -- PB14 PB13 -- PB11 -- -- PB8 PB7 -- -- -- -- -- -- -- PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 -- -- -- -- -- -- -- PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PF5 PF4 PF3 PF2 PF1 PF0
silabs.com | Building a more connected world.
Rev. 2.30 | 149
5.2.4 Opamp Pinout Overview
The specific opamp terminals available in EFM32LG232 is shown in the following figure.
PC4
+ OUT0ALT
PC5
OPA0 -
OUT0
PD4
+
PD3
OPA2 -
OUT2
PD6
+ OUT1ALT
PD7
OPA1 -
OUT1
PB11 PB12 PC0 PC1 PC2 PC3 PC12 PC13 PC14 PC15 PD0 PD1 PD5
Figure 5.4. Opamp Pinout
EFM32LG Data Sheet
Pin Definitions
silabs.com | Building a more connected world.
Rev. 2.30 | 150
5.3 EFM32LG280 (LQFP100)
EFM32LG Data Sheet
Pin Definitions
5.3.1 Pinout
The EFM32LG280 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question.
Figure 5.5. EFM32LG280 Pinout (top view, not to scale)
silabs.com | Building a more connected world.
Rev. 2.30 | 151
EFM32LG Data Sheet
Pin Definitions
Table 5.7. Device Pinout
LQFP100 Pin# and Name
Pin # Pin Name
1
PA0
2
PA1
Analog
Pin Alternate Functionality / Description
EBI EBI_AD09 #0/1/2
Timers TIM0_CC0 #0/1/4
Communication
LEU0_RX #4 I2C0_SDA #0
EBI_AD10 #0/1/2 TIM0_CC1 #0/1
I2C0_SCL #0
3
PA2
EBI_AD11 #0/1/2 TIM0_CC2 #0/1
4
PA3
EBI_AD12 #0/1/2 TIM0_CDTI0 #0
U0_TX #2
5
PA4
EBI_AD13 #0/1/2 TIM0_CDTI1 #0
U0_RX #2
6
PA5
EBI_AD14 #0/1/2 TIM0_CDTI2 #0
LEU1_TX #1
7
PA6
EBI_AD15 #0/1/2
LEU1_RX #1
8
IOVDD_0 Digital IO power supply 0.
9
PB0
EBI_A16 #0/1/2
TIM1_CC0 #2
10
PB1
EBI_A17 #0/1/2
TIM1_CC1 #2
11
PB2
EBI_A18 #0/1/2
TIM1_CC2 #2
12
PB3
EBI_A19 #0/1/2
PCNT1_S0IN #1
US2_TX #1
13
PB4
EBI_A20 #0/1/2
PCNT1_S1IN #1
US2_RX #1
14
PB5
EBI_A21 #0/1/2
US2_CLK #1
15
PB6
EBI_A22 #0/1/2
US2_CS #1
16
VSS
Ground.
17
IOVDD_1 Digital IO power supply 1.
18
PC0
ACMP0_CH0 DAC0_OUT0ALT
#0/ OPAMP_OUT0ALT
EBI_A23 #0/1/2
TIM0_CC1 #4 PCNT0_S0IN #2
US0_TX #5 US1_TX #0 I2C0_SDA #4
19
PC1
ACMP0_CH1 DAC0_OUT0ALT
#1/ OPAMP_OUT0ALT
EBI_A24 #0/1/2
TIM0_CC2 #4 PCNT0_S1IN #2
US0_RX #5 US1_RX #0 I2C0_SCL #4
ACMP0_CH2
20
PC2
DAC0_OUT0ALT #2/
EBI_A25 #0/1/2
TIM0_CDTI0 #4
US2_TX #0
OPAMP_OUT0ALT
ACMP0_CH3
21
PC3
DAC0_OUT0ALT #3/
EBI_NANDREn #0/1/2
TIM0_CDTI1 #4
US2_RX #0
OPAMP_OUT0ALT
Other PRS_CH0 #0 GPIO_EM4WU0 CMU_CLK1 #0 PRS_CH1 #0 CMU_CLK0 #0 ETM_TD0 #3 LES_ALTEX2 #0 ETM_TD1 #3 LES_ALTEX3 #0 ETM_TD2 #3 LES_ALTEX4 #0 ETM_TD3 #3 ETM_TCLK #3 GPIO_EM4WU1
LES_CH0 #0 PRS_CH2 #0
LES_CH1 #0 PRS_CH3 #0
LES_CH2 #0
LES_CH3 #0
silabs.com | Building a more connected world.
Rev. 2.30 | 152
EFM32LG Data Sheet
Pin Definitions
LQFP100 Pin# and Name
Pin # Pin Name
22
PC4
23
PC5
24
PB7
25
PB8
26
PA7
27
PA8
28
PA9
29
PA10
30
PA11
31
IOVDD_2
32
VSS
33
PA12
34
PA13
35
PA14
36
RESETn
37
PB9
38
PB10
39
PB11
40
PB12
41
AVDD_1
42
PB13
43
PB14
44
IOVDD_3
45
AVDD_0
46
PD0
Pin Alternate Functionality / Description
Analog
EBI
Timers
Communication
Other
ACMP0_CH4 / DAC0_P0 / OPAMP_P0
EBI_A26 #0/1/2
TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0
US2_CLK #0 I2C1_SDA #0
LES_CH4 #0
ACMP0_CH5 / DAC0_N0 / OPAMP_N0
EBI_NANDWEn #0/1/2
LETIM0_OUT1 #3 PCNT1_S1IN #0
US2_CS #0 I2C1_SCL #0
LES_CH5 #0
LFXTAL_P
TIM1_CC0 #3
US0_TX #4 US1_CLK #0
LFXTAL_N
TIM1_CC1 #3
US0_RX #4 US1_CS #0
EBI_CSTFT #0/1/2
EBI_DCLK #0/1/2
TIM2_CC0 #0
EBI_DTEN #0/1/2
TIM2_CC1 #0
EBI_VSNC #0/1/2
TIM2_CC2 #0
EBI_HSNC #0/1/2
Digital IO power supply 2.
Ground.
EBI_A00 #0/1/2
TIM2_CC0 #1
EBI_A01 #0/1/2
TIM2_CC1 #1
EBI_A02 #0/1/2
TIM2_CC2 #1
Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released.
EBI_A03 #0/1/2
U1_TX #2
EBI_A04 #0/1/2
U1_RX #2
DAC0_OUT0 / OPAMP_OUT0
TIM1_CC2 #3 LETIM0_OUT0 #1
I2C1_SDA #1
DAC0_OUT1 / OPAMP_OUT1
LETIM0_OUT1 #1
I2C1_SCL #1
Analog power supply 1.
HFXTAL_P
US0_CLK #4/5 LEU0_TX #1
HFXTAL_N
US0_CS #4/5 LEU0_RX #1
Digital IO power supply 3.
Analog power supply 0.
ADC0_CH0 DAC0_OUT0ALT
#4/ OPAMP_OUT0ALT OPAMP_OUT2 #1
PCNT2_S0IN #0
US1_TX #1
silabs.com | Building a more connected world.
Rev. 2.30 | 153
EFM32LG Data Sheet
Pin Definitions
LQFP100 Pin# and Name
Pin # Pin Name
47
PD1
48
PD2
49
PD3
50
PD4
51
PD5
52
PD6
53
PD7
54
PD8
55
PC6
56
PC7
57 VDD_DREG
58
VSS
59 DECOUPLE
60
PE0
61
PE1
62
PE2
63
PE3
64
PE4
65
PE5
66
PE6
67
PE7
68
PC8
69
PC9
70
PC10
71
PC11
Pin Alternate Functionality / Description
Analog
EBI
Timers
Communication
Other
ADC0_CH1 DAC0_OUT1ALT
#4/ OPAMP_OUT1ALT
TIM0_CC0 #3 PCNT2_S1IN #0
US1_RX #1
DBG_SWO #2
ADC0_CH2
EBI_A27 #0/1/2
TIM0_CC1 #3
US1_CLK #1
DBG_SWO #3
ADC0_CH3 OPAMP_N2
TIM0_CC2 #3
US1_CS #1
ETM_TD1 #0/2
ADC0_CH4 OPAMP_P2
LEU0_TX #0
ETM_TD2 #0/2
ADC0_CH5 OPAMP_OUT2 #0
LEU0_RX #0
ETM_TD3 #0/2
ADC0_CH6 / DAC0_P1 / OPAMP_P1
TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3
US1_RX #2 I2C0_SDA #1
LES_ALTEX0 #0 ACMP0_O #2 ETM_TD0 #0
ADC0_CH7 / DAC0_N1 / OPAMP_N1
TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3
US1_TX #2 I2C0_SCL #1
CMU_CLK0 #2 LES_ALTEX1 #0
ACMP1_O #2 ETM_TCLK #0
BU_VIN
CMU_CLK1 #1
ACMP0_CH6
EBI_A05 #0/1/2
LEU1_TX #0 I2C0_SDA #2
LES_CH6 #0 ETM_TCLK #2
ACMP0_CH7
EBI_A06 #0/1/2
LEU1_RX #0 I2C0_SCL #2
LES_CH7 #0 ETM_TD0 #2
Power supply for on-chip voltage regulator.
Ground.
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin.
EBI_A07 #0/1/2
TIM3_CC0 #1 PCNT0_S0IN #1
U0_TX #1 I2C1_SDA #2
EBI_A08 #0/1/2
TIM3_CC1 #1 PCNT0_S1IN #1
U0_RX #1 I2C1_SCL #2
BU_VOUT
EBI_A09 #0
TIM3_CC2 #1
U1_TX #3
ACMP0_O #1
BU_STAT
EBI_A10 #0
U1_RX #3
ACMP1_O #1
EBI_A11 #0/1/2
US0_CS #1
EBI_A12 #0/1/2
US0_CLK #1
EBI_A13 #0/1/2
US0_RX #1
EBI_A14 #0/1/2
US0_TX #1
ACMP1_CH0
EBI_A15 #0/1/2
TIM2_CC0 #2
US0_CS #2
LES_CH8 #0
ACMP1_CH1
EBI_A09 #1/2
TIM2_CC1 #2
US0_CLK #2
LES_CH9 #0 GPIO_EM4WU2
ACMP1_CH2
EBI_A10 #1/2
TIM2_CC2 #2
US0_RX #2
LES_CH10 #0
ACMP1_CH3
EBI_ALE #1/2
US0_TX #2
LES_CH11 #0
silabs.com | Building a more connected world.
Rev. 2.30 | 154
EFM32LG Data Sheet
Pin Definitions
LQFP100 Pin# and Name
Pin # Pin Name
72
PC12
73
PC13
74
PC14
75
PC15
76
PF0
77
PF1
78
PF2
79
PF3
80
PF4
81
PF5
82
IOVDD_5
83
VSS
84
PF6
85
PF7
86
PF8
87
PF9
88
PD9
89
PD10
90
PD11
91
PD12
92
PE8
93
PE9
94
PE10
95
PE11
Analog
ACMP1_CH4 DAC0_OUT1ALT
#0/ OPAMP_OUT1ALT
ACMP1_CH5 DAC0_OUT1ALT
#1/ OPAMP_OUT1ALT
ACMP1_CH6 DAC0_OUT1ALT
#2/ OPAMP_OUT1ALT
ACMP1_CH7 DAC0_OUT1ALT
#3/ OPAMP_OUT1ALT
Pin Alternate Functionality / Description
EBI
Timers
Communication
U1_TX #0
TIM0_CDTI0 #1/3 TIM1_CC0 #0 TIM1_CC2 #4
PCNT0_S0IN #0
U1_RX #0
TIM0_CDTI1 #1/3 TIM1_CC1 #0
PCNT0_S1IN #0
US0_CS #3 U0_TX #3
TIM0_CDTI2 #1/3 TIM1_CC2 #0
TIM0_CC0 #5 LETIM0_OUT0 #2
TIM0_CC1 #5 LETIM0_OUT1 #2
US0_CLK #3 U0_RX #3
US1_CLK #2 LEU0_TX #3 I2C0_SDA #5
US1_CS #2 LEU0_RX #3 I2C0_SCL #5
EBI_ARDY #0/1/2
TIM0_CC2 #5
LEU0_TX #4
EBI_ALE #0
TIM0_CDTI0 #2/5
EBI_WEn #0/2 EBI_REn #0/2 Digital IO power supply 5. Ground. EBI_BL0 #0/1/2 EBI_BL1 #0/1/2 EBI_WEn #1 EBI_REn #1 EBI_CS0 #0/1/2 EBI_CS1 #0/1/2 EBI_CS2 #0/1/2 EBI_CS3 #0/1/2 EBI_AD00 #0/1/2 EBI_AD01 #0/1/2 EBI_AD02 #0/1/2
TIM0_CDTI1 #2/5 TIM0_CDTI2 #2/5
TIM0_CC0 #2 TIM0_CC1 #2 TIM0_CC2 #2
PCNT2_S0IN #1 PCNT2_S1IN #1
TIM1_CC0 #1
EBI_AD03 #0/1/2
TIM1_CC1 #1
U0_TX #0 U0_RX #0
US0_TX #0 US0_RX #0
Other CMU_CLK0 #1 LES_CH12 #0
LES_CH13 #0
LES_CH14 #0
LES_CH15 #0 DBG_SWO #1
DBG_SWCLK #0/1/2/3
DBG_SWDIO #0/1/2/3
GPIO_EM4WU3 ACMP1_O #0 DBG_SWO #0
GPIO_EM4WU4 PRS_CH0 #1 ETM_TD3 #1 PRS_CH1 #1 PRS_CH2 #1
ETM_TCLK #1 ETM_TD0 #1
PRS_CH3 #1
BOOT_TX LES_ALTEX5 #0
BOOT_RX
silabs.com | Building a more connected world.
Rev. 2.30 | 155
LQFP100 Pin# and Name
Pin # Pin Name
96
PE12
97
PE13
98
PE14
99
PE15
100
PA15
Analog
EFM32LG Data Sheet
Pin Definitions
Pin Alternate Functionality / Description
EBI EBI_AD04 #0/1/2
EBI_AD05 #0/1/2 EBI_AD06 #0/1/2 EBI_AD07 #0/1/2 EBI_AD08 #0/1/2
Timers TIM1_CC2 #1
TIM3_CC0 #0 TIM3_CC1 #0 TIM3_CC2 #0
Communication
US0_RX #3 US0_CLK #0 I2C0_SDA #6
US0_TX #3 US0_CS #0 I2C0_SCL #6
LEU0_TX #2
LEU0_RX #2
Other
CMU_CLK1 #2 LES_ALTEX6 #0
LES_ALTEX7 #0 ACMP0_O #0
GPIO_EM4WU5
silabs.com | Building a more connected world.
Rev. 2.30 | 156
EFM32LG Data Sheet
Pin Definitions
5.3.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0.
Table 5.8. Alternate Functionality Overview
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
ACMP0_CH0 PC0
Analog comparator ACMP0, channel 0.
ACMP0_CH1 PC1
Analog comparator ACMP0, channel 1.
ACMP0_CH2 PC2
Analog comparator ACMP0, channel 2.
ACMP0_CH3 PC3
Analog comparator ACMP0, channel 3.
ACMP0_CH4 PC4
Analog comparator ACMP0, channel 4.
ACMP0_CH5 PC5
Analog comparator ACMP0, channel 5.
ACMP0_CH6 PC6
Analog comparator ACMP0, channel 6.
ACMP0_CH7 PC7
Analog comparator ACMP0, channel 7.
ACMP0_O
PE13 PE2 PD6
Analog comparator ACMP0, digital output.
ACMP1_CH0 PC8
Analog comparator ACMP1, channel 0.
ACMP1_CH1 PC9
Analog comparator ACMP1, channel 1.
ACMP1_CH2 PC10
Analog comparator ACMP1, channel 2.
ACMP1_CH3 PC11
Analog comparator ACMP1, channel 3.
ACMP1_CH4 PC12
Analog comparator ACMP1, channel 4.
ACMP1_CH5 PC13
Analog comparator ACMP1, channel 5.
ACMP1_CH6 PC14
Analog comparator ACMP1, channel 6.
ACMP1_CH7 PC15
Analog comparator ACMP1, channel 7.
ACMP1_O
PF2 PE3 PD7
Analog comparator ACMP1, digital output.
ADC0_CH0
PD0
Analog to digital converter ADC0, input channel number 0.
ADC0_CH1
PD1
Analog to digital converter ADC0, input channel number 1.
ADC0_CH2
PD2
Analog to digital converter ADC0, input channel number 2.
ADC0_CH3
PD3
Analog to digital converter ADC0, input channel number 3.
ADC0_CH4
PD4
Analog to digital converter ADC0, input channel number 4.
ADC0_CH5
PD5
Analog to digital converter ADC0, input channel number 5.
ADC0_CH6
PD6
Analog to digital converter ADC0, input channel number 6.
silabs.com | Building a more connected world.
Rev. 2.30 | 157
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
ADC0_CH7
PD7
Analog to digital converter ADC0, input channel number 7.
BOOT_RX
PE11
Bootloader RX.
BOOT_TX
PE10
Bootloader TX.
BU_STAT
PE3
Backup Power Domain status, whether or not the system is in backup mode
BU_VIN
PD8
Battery input for Backup Power Domain
BU_VOUT
PE2
Power output for Backup Power Domain
CMU_CLK0
PA2 PC12 PD7
Clock Management Unit, clock output number 0.
CMU_CLK1
PA1 PD8 PE12
Clock Management Unit, clock output number 1.
DAC0_OUT0 / OPAMP_OUT0
PB11
Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0.
DAC0_OUT0ALT / OPAMP_OUT0A PC0 PC1 PC2 PC3 PD0 LT
Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0.
DAC0_OUT1 / OPAMP_OUT1
PB12
Digital to Analog Converter DAC0_OUT1 /OPAMP output channel number 1.
DAC0_OUT1ALT / OPAMP_OUT1A PC12 PC13 PC14 PC15 PD1 LT
Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1.
DBG_SWCLK PF0 PF0 PF0 PF0
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, and has a built-in pull down.
DBG_SWDIO PF1 PF1 PF1 PF1
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and has a built-in pull up.
DBG_SWO
PF2 PC15 PD1 PD2
Debug-interface Serial Wire viewer Output.
Note that this function is not enabled after reset, and must be enabled by software to be used.
EBI_A00
PA12 PA12 PA12
External Bus Interface (EBI) address output pin 00.
EBI_A01
PA13 PA13 PA13
External Bus Interface (EBI) address output pin 01.
EBI_A02
PA14 PA14 PA14
External Bus Interface (EBI) address output pin 02.
EBI_A03
PB9 PB9 PB9
External Bus Interface (EBI) address output pin 03.
EBI_A04
PB10 PB10 PB10
External Bus Interface (EBI) address output pin 04.
EBI_A05
PC6 PC6 PC6
External Bus Interface (EBI) address output pin 05.
EBI_A06
PC7 PC7 PC7
External Bus Interface (EBI) address output pin 06.
EBI_A07
PE0 PE0 PE0
External Bus Interface (EBI) address output pin 07.
EBI_A08
PE1 PE1 PE1
External Bus Interface (EBI) address output pin 08.
EBI_A09
PE2 PC9 PC9
External Bus Interface (EBI) address output pin 09.
EBI_A10
PE3 PC10 PC10
External Bus Interface (EBI) address output pin 10.
silabs.com | Building a more connected world.
Rev. 2.30 | 158
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
EBI_A11
PE4 PE4 PE4
External Bus Interface (EBI) address output pin 11.
EBI_A12
PE5 PE5 PE5
External Bus Interface (EBI) address output pin 12.
EBI_A13
PE6 PE6 PE6
External Bus Interface (EBI) address output pin 13.
EBI_A14
PE7 PE7 PE7
External Bus Interface (EBI) address output pin 14.
EBI_A15
PC8 PC8 PC8
External Bus Interface (EBI) address output pin 15.
EBI_A16
PB0 PB0 PB0
External Bus Interface (EBI) address output pin 16.
EBI_A17
PB1 PB1 PB1
External Bus Interface (EBI) address output pin 17.
EBI_A18
PB2 PB2 PB2
External Bus Interface (EBI) address output pin 18.
EBI_A19
PB3 PB3 PB3
External Bus Interface (EBI) address output pin 19.
EBI_A20
PB4 PB4 PB4
External Bus Interface (EBI) address output pin 20.
EBI_A21
PB5 PB5 PB5
External Bus Interface (EBI) address output pin 21.
EBI_A22
PB6 PB6 PB6
External Bus Interface (EBI) address output pin 22.
EBI_A23
PC0 PC0 PC0
External Bus Interface (EBI) address output pin 23.
EBI_A24
PC1 PC1 PC1
External Bus Interface (EBI) address output pin 24.
EBI_A25
PC2 PC2 PC2
External Bus Interface (EBI) address output pin 25.
EBI_A26
PC4 PC4 PC4
External Bus Interface (EBI) address output pin 26.
EBI_A27
PD2 PD2 PD2
External Bus Interface (EBI) address output pin 27.
EBI_AD00
PE8 PE8 PE8
External Bus Interface (EBI) address and data input / output pin 00.
EBI_AD01
PE9 PE9 PE9
External Bus Interface (EBI) address and data input / output pin 01.
EBI_AD02
PE10 PE10 PE10
External Bus Interface (EBI) address and data input / output pin 02.
EBI_AD03
PE11 PE11 PE11
External Bus Interface (EBI) address and data input / output pin 03.
EBI_AD04
PE12 PE12 PE12
External Bus Interface (EBI) address and data input / output pin 04.
EBI_AD05
PE13 PE13 PE13
External Bus Interface (EBI) address and data input / output pin 05.
EBI_AD06
PE14 PE14 PE14
External Bus Interface (EBI) address and data input / output pin 06.
EBI_AD07
PE15 PE15 PE15
External Bus Interface (EBI) address and data input / output pin 07.
EBI_AD08
PA15 PA15 PA15
External Bus Interface (EBI) address and data input / output pin 08.
EBI_AD09
PA0 PA0 PA0
External Bus Interface (EBI) address and data input / output pin 09.
EBI_AD10
PA1 PA1 PA1
External Bus Interface (EBI) address and data input / output pin 10.
EBI_AD11
PA2 PA2 PA2
External Bus Interface (EBI) address and data input / output pin 11.
silabs.com | Building a more connected world.
Rev. 2.30 | 159
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
EBI_AD12
PA3 PA3 PA3
External Bus Interface (EBI) address and data input / output pin 12.
EBI_AD13
PA4 PA4 PA4
External Bus Interface (EBI) address and data input / output pin 13.
EBI_AD14
PA5 PA5 PA5
External Bus Interface (EBI) address and data input / output pin 14.
EBI_AD15
PA6 PA6 PA6
External Bus Interface (EBI) address and data input / output pin 15.
EBI_ALE
PF3 PC11 PC11
External Bus Interface (EBI) Address Latch Enable output.
EBI_ARDY
PF2 PF2 PF2
External Bus Interface (EBI) Hardware Ready Control input.
EBI_BL0
PF6 PF6 PF6
External Bus Interface (EBI) Byte Lane/Enable pin 0.
EBI_BL1
PF7 PF7 PF7
External Bus Interface (EBI) Byte Lane/Enable pin 1.
EBI_CS0
PD9 PD9 PD9
External Bus Interface (EBI) Chip Select output 0.
EBI_CS1
PD10 PD10 PD10
External Bus Interface (EBI) Chip Select output 1.
EBI_CS2
PD11 PD11 PD11
External Bus Interface (EBI) Chip Select output 2.
EBI_CS3
PD12 PD12 PD12
External Bus Interface (EBI) Chip Select output 3.
EBI_CSTFT
PA7 PA7 PA7
External Bus Interface (EBI) Chip Select output TFT.
EBI_DCLK
PA8 PA8 PA8
External Bus Interface (EBI) TFT Dot Clock pin.
EBI_DTEN
PA9 PA9 PA9
External Bus Interface (EBI) TFT Data Enable pin.
EBI_HSNC
PA11 PA11 PA11
External Bus Interface (EBI) TFT Horizontal Synchronization pin.
EBI_NANDREn PC3 PC3 PC3
External Bus Interface (EBI) NAND Read Enable output.
EBI_NANDWEn PC5 PC5 PC5
External Bus Interface (EBI) NAND Write Enable output.
EBI_REn
PF5 PF9 PF5
External Bus Interface (EBI) Read Enable output.
EBI_VSNC
PA10 PA10 PA10
External Bus Interface (EBI) TFT Vertical Synchronization pin.
EBI_WEn
PF4 PF8 PF4
External Bus Interface (EBI) Write Enable output.
ETM_TCLK
PD7 PF8 PC6 PA6
Embedded Trace Module ETM clock .
ETM_TD0
PD6 PF9 PC7 PA2
Embedded Trace Module ETM data 0.
ETM_TD1
PD3
PD3 PA3
Embedded Trace Module ETM data 1.
ETM_TD2
PD4
PD4 PA4
Embedded Trace Module ETM data 2.
ETM_TD3
PD5 PF3 PD5 PA5
Embedded Trace Module ETM data 3.
GPIO_EM4WU0 PA0
Pin can be used to wake the system up from EM4
GPIO_EM4WU1 PA6
Pin can be used to wake the system up from EM4
silabs.com | Building a more connected world.
Rev. 2.30 | 160
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
GPIO_EM4WU2 PC9
Pin can be used to wake the system up from EM4
GPIO_EM4WU3 PF1
Pin can be used to wake the system up from EM4
GPIO_EM4WU4 PF2
Pin can be used to wake the system up from EM4
GPIO_EM4WU5 PE13
Pin can be used to wake the system up from EM4
HFXTAL_N
PB14
High Frequency Crystal negative pin. Also used as external optional clock input pin.
HFXTAL_P
PB13
High Frequency Crystal positive pin.
I2C0_SCL
PA1 PD7 PC7
PC1 PF1 PE13 I2C0 Serial Clock Line input / output.
I2C0_SDA
PA0 PD6 PC6
PC0 PF0 PE12 I2C0 Serial Data input / output.
I2C1_SCL
PC5 PB12 PE1
I2C1 Serial Clock Line input / output.
I2C1_SDA
PC4 PB11 PE0
I2C1 Serial Data input / output.
LES_ALTEX0 PD6
LESENSE alternate exite output 0.
LES_ALTEX1 PD7
LESENSE alternate exite output 1.
LES_ALTEX2 PA3
LESENSE alternate exite output 2.
LES_ALTEX3 PA4
LESENSE alternate exite output 3.
LES_ALTEX4 PA5
LESENSE alternate exite output 4.
LES_ALTEX5 PE11
LESENSE alternate exite output 5.
LES_ALTEX6 PE12
LESENSE alternate exite output 6.
LES_ALTEX7 PE13
LESENSE alternate exite output 7.
LES_CH0
PC0
LESENSE channel 0.
LES_CH1
PC1
LESENSE channel 1.
LES_CH2
PC2
LESENSE channel 2.
LES_CH3
PC3
LESENSE channel 3.
LES_CH4
PC4
LESENSE channel 4.
LES_CH5
PC5
LESENSE channel 5.
LES_CH6
PC6
LESENSE channel 6.
LES_CH7
PC7
LESENSE channel 7.
LES_CH8
PC8
LESENSE channel 8.
LES_CH9
PC9
LESENSE channel 9.
LES_CH10
PC10
LESENSE channel 10.
LES_CH11
PC11
LESENSE channel 11.
LES_CH12
PC12
LESENSE channel 12.
LES_CH13
PC13
LESENSE channel 13.
LES_CH14
PC14
LESENSE channel 14.
LES_CH15
PC15
LESENSE channel 15.
LETIM0_OUT0 PD6 PB11 PF0 PC4
Low Energy Timer LETIM0, output channel 0.
silabs.com | Building a more connected world.
Rev. 2.30 | 161
Alternate
LOCATION
Functionality
0
1
2
3
4
5
LETIM0_OUT1 PD7 PB12 PF1 PC5
LEU0_RX
PD5 PB14 PE15 PF1 PA0
LEU0_TX
PD4 PB13 PE14 PF0 PF2
LEU1_RX
PC7 PA6
LEU1_TX
PC6 PA5
LFXTAL_N
PB8
LFXTAL_P
PB7
OPAMP_N0 / DAC0_N0
PC5
OPAMP_N1 / DAC0_N1
PD7
OPAMP_N2
PD3
OPAMP_OUT2 PD5 PD0
OPAMP_P0 / DAC0_P0
PC4
OPAMP_P1 / DAC0_P1
PD6
OPAMP_P2
PD4
PCNT0_S0IN PC13 PE0 PC0 PD6
PCNT0_S1IN PC14 PE1 PC1 PD7
PCNT1_S0IN PC4 PB3
PCNT1_S1IN PC5 PB4
PCNT2_S0IN PD0 PE8
PCNT2_S1IN PD1 PE9
PRS_CH0
PA0 PF3
PRS_CH1
PA1 PF4
PRS_CH2
PC0 PF5
PRS_CH3
PC1 PE8
TIM0_CC0
PA0 PA0 PF6 PD1 PA0 PF0
TIM0_CC1
PA1 PA1 PF7 PD2 PC0 PF1
TIM0_CC2
PA2 PA2 PF8 PD3 PC1 PF2
TIM0_CDTI0
PA3 PC13 PF3 PC13 PC2 PF3
TIM0_CDTI1
PA4 PC14 PF4 PC14 PC3 PF4
EFM32LG Data Sheet
Pin Definitions
6
Description
Low Energy Timer LETIM0, output channel 1.
LEUART0 Receive input.
LEUART0 Transmit output. Also used as receive input in half duplex communication.
LEUART1 Receive input.
LEUART1 Transmit output. Also used as receive input in half duplex communication.
Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin.
Low Frequency Crystal (typically 32.768 kHz) positive pin.
Operational Amplifier 0 external negative input.
Operational Amplifier 1 external negative input. Operational Amplifier 2 external negative input. Operational Amplifier 2 output. Operational Amplifier 0 external positive input.
Operational Amplifier 1 external positive input.
Operational Amplifier 2 external positive input. Pulse Counter PCNT0 input number 0. Pulse Counter PCNT0 input number 1. Pulse Counter PCNT1 input number 0. Pulse Counter PCNT1 input number 1. Pulse Counter PCNT2 input number 0. Pulse Counter PCNT2 input number 1. Peripheral Reflex System PRS, channel 0. Peripheral Reflex System PRS, channel 1. Peripheral Reflex System PRS, channel 2. Peripheral Reflex System PRS, channel 3. Timer 0 Capture Compare input / output channel 0. Timer 0 Capture Compare input / output channel 1. Timer 0 Capture Compare input / output channel 2. Timer 0 Complimentary Deat Time Insertion channel 0. Timer 0 Complimentary Deat Time Insertion channel 1.
silabs.com | Building a more connected world.
Rev. 2.30 | 162
Alternate Functionality
TIM0_CDTI2
TIM1_CC0 TIM1_CC1 TIM1_CC2 TIM2_CC0 TIM2_CC1 TIM2_CC2 TIM3_CC0 TIM3_CC1 TIM3_CC2 U0_RX
U0_TX
U1_RX
U1_TX
US0_CLK US0_CS
LOCATION
0
1
2
3
4
5
PA5 PC15 PF5 PC15 PC4 PF5
PC13 PC14 PC15 PA8 PA9 PA10 PE14 PE15 PA15 PF7
PE10 PE11 PE12 PA12 PA13 PA14 PE0 PE1 PE2 PE1
PB0 PB1 PB2 PC8 PC9 PC10
PA4
PB7 PB8 PB11
PC15
PD6 PD7 PC13
PF6 PE0 PA3 PC14
PC13
PB10 PE3
PC12
PB9 PE2
PE12 PE5 PC9 PC15 PB13 PB13 PE13 PE4 PC8 PC14 PB14 PB14
US0_RX
PE11 PE6 PC10 PE12 PB8 PC1
US0_TX
US1_CLK US1_CS US1_RX
PE10 PE7 PC11 PE13 PB7 PC0
PB7 PD2 PF0 PB8 PD3 PF1 PC1 PD1 PD6
US1_TX
US2_CLK US2_CS US2_RX
PC0 PD0 PD7
PC4 PB5 PC5 PB6 PC3 PB4
EFM32LG Data Sheet
Pin Definitions
6
Description
Timer 0 Complimentary Deat Time Insertion channel 2.
Timer 1 Capture Compare input / output channel 0.
Timer 1 Capture Compare input / output channel 1.
Timer 1 Capture Compare input / output channel 2.
Timer 2 Capture Compare input / output channel 0.
Timer 2 Capture Compare input / output channel 1.
Timer 2 Capture Compare input / output channel 2.
Timer 3 Capture Compare input / output channel 0.
Timer 3 Capture Compare input / output channel 1.
Timer 3 Capture Compare input / output channel 2.
UART0 Receive input.
UART0 Transmit output. Also used as receive input in half duplex communication.
UART1 Receive input.
UART1 Transmit output. Also used as receive input in half duplex communication.
USART0 clock input / output.
USART0 chip select input / output.
USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output (MISO).
USART0 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input (MOSI).
USART1 clock input / output.
USART1 chip select input / output.
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output (MISO).
USART1 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input (MOSI).
USART2 clock input / output.
USART2 chip select input / output.
USART2 Asynchronous Receive.
USART2 Synchronous mode Master Input / Slave Output (MISO).
silabs.com | Building a more connected world.
Rev. 2.30 | 163
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
US2_TX
PC2 PB3
USART2 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART2 Synchronous mode Master Output / Slave Input (MOSI).
5.3.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG280 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.9. GPIO Pinout
Port
Port A Port B Port C Port D Port E Port F
Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 15 14 13 12 11 10 PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 -- PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 -- -- -- PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 -- -- -- -- -- -- PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0
5.3.4 Opamp Pinout Overview
The specific opamp terminals available in EFM32LG280 is shown in the following figure.
PC4
+ OUT0ALT
PC5
OPA0 -
OUT0
PD4
+
PD3
OPA2 -
OUT2
PD6
+ OUT1ALT
OPA1 OUT1
PD7
-
PB11 PB12 PC0 PC1 PC2 PC3 PC12 PC13 PC14 PC15 PD0 PD1 PD5
Figure 5.6. Opamp Pinout
silabs.com | Building a more connected world.
Rev. 2.30 | 164
5.4 EFM32LG290 (BGA112)
EFM32LG Data Sheet
Pin Definitions
5.4.1 Pinout
The EFM32LG290 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question.
Figure 5.7. EFM32LG290 Pinout (top view, not to scale) Table 5.10. Device Pinout
BGA112 Pin# and Name
Pin # Pin Name
A1
PE15
A2
PE14
A3
PE12
Analog
Pin Alternate Functionality / Description
EBI EBI_AD07 #0/1/2 EBI_AD06 #0/1/2
EBI_AD04 #0/1/2
Timers TIM3_CC1 #0 TIM3_CC0 #0
TIM1_CC2 #1
Communication
LEU0_RX #2
LEU0_TX #2
US0_RX #3 US0_CLK #0 I2C0_SDA #6
Other
CMU_CLK1 #2 LES_ALTEX6 #0
silabs.com | Building a more connected world.
Rev. 2.30 | 165
EFM32LG Data Sheet
Pin Definitions
BGA112 Pin# and Name
Pin # Pin Name
A4
PE9
A5
PD10
A6
PF7
A7
PF5
A8
PF4
A9
PE4
A10
PC14
A11
PC15
B1
PA15
B2
PE13
B3
PE11
B4
PE8
B5
PD11
B6
PF8
B7
PF6
B8
PF3
B9
PE5
B10
PC12
B11
PC13
C1
PA1
C2
PA0
C3
PE10
C4
PD13
C5
PD12
C6
PF9
Pin Alternate Functionality / Description
Analog
ACMP1_CH6 DAC0_OUT1ALT
#2/ OPAMP_OUT1ALT
ACMP1_CH7 DAC0_OUT1ALT
#3/ OPAMP_OUT1ALT
EBI EBI_AD01 #0/1/2 EBI_CS1 #0/1/2 EBI_BL1 #0/1/2
EBI_REn #0/2 EBI_WEn #0/2 EBI_A11 #0/1/2
EBI_AD08 #0/1/2
EBI_AD05 #0/1/2
EBI_AD03 #0/1/2
EBI_AD00 #0/1/2 EBI_CS2 #0/1/2
EBI_WEn #1 EBI_BL0 #0/1/2
EBI_ALE #0
ACMP1_CH4 DAC0_OUT1ALT
#0/ OPAMP_OUT1ALT
ACMP1_CH5 DAC0_OUT1ALT
#1/ OPAMP_OUT1ALT
EBI_A12 #0/1/2
EBI_AD10 #0/1/2
EBI_AD09 #0/1/2 EBI_AD02 #0/1/2
EBI_CS3 #0/1/2 EBI_REn #1
Timers PCNT2_S1IN #1
TIM0_CC1 #2 TIM0_CDTI2 #2/5 TIM0_CDTI1 #2/5
TIM0_CDTI1 #1/3 TIM1_CC1 #0
PCNT0_S1IN #0
TIM0_CDTI2 #1/3 TIM1_CC2 #0 TIM3_CC2 #0
TIM1_CC1 #1 PCNT2_S0IN #1
TIM0_CC2 #2 TIM0_CC0 #2 TIM0_CDTI0 #2/5
TIM0_CDTI0 #1/3 TIM1_CC0 #0 TIM1_CC2 #4
PCNT0_S0IN #0 TIM0_CC1 #0/1 TIM0_CC0 #0/1/4 TIM1_CC0 #1
Communication
Other
U0_RX #0 US0_CS #1
PRS_CH2 #1 PRS_CH1 #1
US0_CS #3 U0_TX #3
LES_CH14 #0
US0_CLK #3 U0_RX #3
LES_CH15 #0 DBG_SWO #1
US0_TX #3 US0_CS #0 I2C0_SCL #6
US0_RX #0
LES_ALTEX7 #0 ACMP0_O #0
GPIO_EM4WU5
LES_ALTEX5 #0 BOOT_RX
PRS_CH3 #1
U0_TX #0 US0_CLK #1
ETM_TCLK #1
PRS_CH0 #1 ETM_TD3 #1
U1_TX #0
CMU_CLK0 #1 LES_CH12 #0
U1_RX #0
LES_CH13 #0
I2C0_SCL #0
LEU0_RX #4 I2C0_SDA #0 US0_TX #0
CMU_CLK1 #0 PRS_CH1 #0
PRS_CH0 #0 GPIO_EM4WU0
BOOT_TX
ETM_TD1 #1
ETM_TD0 #1
silabs.com | Building a more connected world.
Rev. 2.30 | 166
EFM32LG Data Sheet
Pin Definitions
BGA112 Pin# and Name
Pin # Pin Name
C7
VSS
Analog Ground.
Pin Alternate Functionality / Description
EBI
Timers
Communication
C8
PF2
EBI_ARDY #0/1/2
TIM0_CC2 #5
LEU0_TX #4
C9
PE6
C10
PC10
C11
PC11
D1
PA3
ACMP1_CH2 ACMP1_CH3
EBI_A13 #0/1/2 EBI_A10 #1/2 EBI_ALE #1/2
EBI_AD12 #0/1/2
TIM2_CC2 #2 TIM0_CDTI0 #0
US0_RX #1 US0_RX #2 US0_TX #2
U0_TX #2
D2
PA2
EBI_AD11 #0/1/2 TIM0_CC2 #0/1
D3
PB15
D4
VSS
Ground.
D5
IOVDD_6 Digital IO power supply 6.
D6
PD9
EBI_CS0 #0/1/2
D7
IOVDD_5 Digital IO power supply 5.
D8
PF1
TIM0_CC1 #5 LETIM0_OUT1 #2
US1_CS #2 LEU0_RX #3 I2C0_SCL #5
D9
PE7
EBI_A14 #0/1/2
US0_TX #1
D10
PC8
ACMP1_CH0
EBI_A15 #0/1/2
TIM2_CC0 #2
US0_CS #2
D11
PC9
ACMP1_CH1
EBI_A09 #1/2
TIM2_CC1 #2
US0_CLK #2
E1
PA6
EBI_AD15 #0/1/2
LEU1_RX #1
E2
PA5
EBI_AD14 #0/1/2 TIM0_CDTI2 #0
LEU1_TX #1
E3
PA4
E4
PB0
E8
PF0
E9
PE0
E10
PE1
E11
PE3
F1
PB1
F2
PB2
F3
PB3
BU_STAT
EBI_AD13 #0/1/2 TIM0_CDTI1 #0
EBI_A16 #0/1/2
TIM1_CC0 #2
TIM0_CC0 #5 LETIM0_OUT0 #2
EBI_A07 #0/1/2
EBI_A08 #0/1/2 EBI_A10 #0
EBI_A17 #0/1/2 EBI_A18 #0/1/2 EBI_A19 #0/1/2
TIM3_CC0 #1 PCNT0_S0IN #1
TIM3_CC1 #1 PCNT0_S1IN #1
TIM1_CC1 #2 TIM1_CC2 #2 PCNT1_S0IN #1
U0_RX #2
US1_CLK #2 LEU0_TX #3 I2C0_SDA #5
U0_TX #1 I2C1_SDA #2
U0_RX #1 I2C1_SCL #2
U1_RX #3
US2_TX #1
Other
ACMP1_O #0 DBG_SWO #0 GPIO_EM4WU4
LES_CH10 #0 LES_CH11 #0 LES_ALTEX2 #0 ETM_TD1 #3 CMU_CLK0 #0 ETM_TD0 #3 ETM_TD2 #1
DBG_SWDIO #0/1/2/3
GPIO_EM4WU3
LES_CH8 #0 LES_CH9 #0 GPIO_EM4WU2 ETM_TCLK #3 GPIO_EM4WU1 LES_ALTEX4 #0 ETM_TD3 #3 LES_ALTEX3 #0 ETM_TD2 #3
DBG_SWCLK #0/1/2/3
ACMP1_O #1
silabs.com | Building a more connected world.
Rev. 2.30 | 167
EFM32LG Data Sheet
Pin Definitions
BGA112 Pin# and Name
Pin # Pin Name
F4
PB4
F8 VDD_DREG
F9 VSS_DREG
F10
PE2
F11 DECOUPLE
G1
PB5
G2
PB6
G3
VSS
G4
IOVDD_0
G8
IOVDD_4
G9
VSS
G10
PC6
G11
PC7
H1
PC0
H2
PC2
H3
PD14
H4
PA7
H5
PA8
H6
VSS
H7
IOVDD_3
H8
PD8
H9
PD5
H10
PD6
H11
PD7
J1
PC1
Pin Alternate Functionality / Description
Analog
EBI
Timers
Communication
Other
EBI_A20 #0/1/2
PCNT1_S1IN #1
US2_RX #1
Power supply for on-chip voltage regulator.
Ground for on-chip voltage regulator.
BU_VOUT
EBI_A09 #0
TIM3_CC2 #1
U1_TX #3
ACMP0_O #1
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin.
EBI_A21 #0/1/2
US2_CLK #1
EBI_A22 #0/1/2
US2_CS #1
Ground.
Digital IO power supply 0.
Digital IO power supply 4.
Ground.
ACMP0_CH6
EBI_A05 #0/1/2
LEU1_TX #0 I2C0_SDA #2
LES_CH6 #0 ETM_TCLK #2
ACMP0_CH7
EBI_A06 #0/1/2
LEU1_RX #0 I2C0_SCL #2
LES_CH7 #0 ETM_TD0 #2
ACMP0_CH0 DAC0_OUT0ALT
#0/ OPAMP_OUT0ALT
EBI_A23 #0/1/2
TIM0_CC1 #4 PCNT0_S0IN #2
US0_TX #5 US1_TX #0 I2C0_SDA #4
LES_CH0 #0 PRS_CH2 #0
ACMP0_CH2 DAC0_OUT0ALT
#2/ OPAMP_OUT0ALT
EBI_A25 #0/1/2
TIM0_CDTI0 #4
US2_TX #0
LES_CH2 #0
I2C0_SDA #3
EBI_CSTFT #0/1/2
EBI_DCLK #0/1/2
TIM2_CC0 #0
Ground.
Digital IO power supply 3.
BU_VIN
CMU_CLK1 #1
ADC0_CH5 OPAMP_OUT2 #0
LEU0_RX #0
ETM_TD3 #0/2
ADC0_CH6 / DAC0_P1 / OPAMP_P1
TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3
US1_RX #2 I2C0_SDA #1
LES_ALTEX0 #0 ACMP0_O #2 ETM_TD0 #0
ADC0_CH7 / DAC0_N1 / OPAMP_N1
TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3
US1_TX #2 I2C0_SCL #1
CMU_CLK0 #2 LES_ALTEX1 #0
ACMP1_O #2 ETM_TCLK #0
ACMP0_CH1 DAC0_OUT0ALT
#1/ OPAMP_OUT0ALT
EBI_A24 #0/1/2
TIM0_CC2 #4 PCNT0_S1IN #2
US0_RX #5 US1_RX #0 I2C0_SCL #4
LES_CH1 #0 PRS_CH3 #0
silabs.com | Building a more connected world.
Rev. 2.30 | 168
EFM32LG Data Sheet
Pin Definitions
BGA112 Pin# and Name
Pin # Pin Name
J2
PC3
J3
PD15
J4
PA12
J5
PA9
J6
PA10
J7
PB9
J8
PB10
J9
PD2
J10
PD3
J11
PD4
K1
PB7
K2
PC4
K3
PA13
K4
VSS
K5
PA11
K6
RESETn
K7
AVSS_1
K8
AVDD_2
K9
AVDD_1
K10
AVSS_0
K11
PD1
L1
PB8
L2
PC5
L3
PA14
L4
IOVDD_1
L5
PB11
Pin Alternate Functionality / Description
Analog
EBI
Timers
Communication
Other
ACMP0_CH3 DAC0_OUT0ALT
#3/ OPAMP_OUT0ALT
EBI_NANDREn #0/1/2
TIM0_CDTI1 #4
US2_RX #0
LES_CH3 #0
I2C0_SCL #3
EBI_A00 #0/1/2
TIM2_CC0 #1
EBI_DTEN #0/1/2
TIM2_CC1 #0
EBI_VSNC #0/1/2
TIM2_CC2 #0
EBI_A03 #0/1/2
U1_TX #2
EBI_A04 #0/1/2
U1_RX #2
ADC0_CH2
EBI_A27 #0/1/2
TIM0_CC1 #3
US1_CLK #1
DBG_SWO #3
ADC0_CH3 OPAMP_N2
TIM0_CC2 #3
US1_CS #1
ETM_TD1 #0/2
ADC0_CH4 OPAMP_P2
LEU0_TX #0
ETM_TD2 #0/2
LFXTAL_P
TIM1_CC0 #3
US0_TX #4 US1_CLK #0
ACMP0_CH4 / DAC0_P0 / OPAMP_P0
EBI_A26 #0/1/2
TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0
US2_CLK #0 I2C1_SDA #0
LES_CH4 #0
EBI_A01 #0/1/2
TIM2_CC1 #1
Ground.
EBI_HSNC #0/1/2
Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released.
Analog ground 1.
Analog power supply 2.
Analog power supply 1.
Analog ground 0.
ADC0_CH1 DAC0_OUT1ALT
#4/ OPAMP_OUT1ALT
TIM0_CC0 #3 PCNT2_S1IN #0
US1_RX #1
DBG_SWO #2
LFXTAL_N
TIM1_CC1 #3
US0_RX #4 US1_CS #0
ACMP0_CH5 / DAC0_N0 / OPAMP_N0
EBI_NANDWEn #0/1/2
LETIM0_OUT1 #3 PCNT1_S1IN #0
US2_CS #0 I2C1_SCL #0
LES_CH5 #0
EBI_A02 #0/1/2
TIM2_CC2 #1
Digital IO power supply 1.
DAC0_OUT0 / OPAMP_OUT0
TIM1_CC2 #3 LETIM0_OUT0 #1
I2C1_SDA #1
silabs.com | Building a more connected world.
Rev. 2.30 | 169
BGA112 Pin# and Name
Pin # Pin Name
L6
PB12
L7
AVSS_2
Analog
DAC0_OUT1 / OPAMP_OUT1
Analog ground 2.
L8
PB13
HFXTAL_P
L9
PB14
HFXTAL_N
L10
AVDD_0 Analog power supply 0.
ADC0_CH0
DAC0_OUT0ALT
L11
PD0
#4/
OPAMP_OUT0ALT
OPAMP_OUT2 #1
EFM32LG Data Sheet
Pin Definitions
Pin Alternate Functionality / Description
EBI
Timers
Communication
LETIM0_OUT1 #1
I2C1_SCL #1
Other
US0_CLK #4/5 LEU0_TX #1
US0_CS #4/5 LEU0_RX #1
PCNT2_S0IN #0
US1_TX #1
silabs.com | Building a more connected world.
Rev. 2.30 | 170
EFM32LG Data Sheet
Pin Definitions
5.4.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0.
Table 5.11. Alternate Functionality Overview
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
ACMP0_CH0 PC0
Analog comparator ACMP0, channel 0.
ACMP0_CH1 PC1
Analog comparator ACMP0, channel 1.
ACMP0_CH2 PC2
Analog comparator ACMP0, channel 2.
ACMP0_CH3 PC3
Analog comparator ACMP0, channel 3.
ACMP0_CH4 PC4
Analog comparator ACMP0, channel 4.
ACMP0_CH5 PC5
Analog comparator ACMP0, channel 5.
ACMP0_CH6 PC6
Analog comparator ACMP0, channel 6.
ACMP0_CH7 PC7
Analog comparator ACMP0, channel 7.
ACMP0_O
PE13 PE2 PD6
Analog comparator ACMP0, digital output.
ACMP1_CH0 PC8
Analog comparator ACMP1, channel 0.
ACMP1_CH1 PC9
Analog comparator ACMP1, channel 1.
ACMP1_CH2 PC10
Analog comparator ACMP1, channel 2.
ACMP1_CH3 PC11
Analog comparator ACMP1, channel 3.
ACMP1_CH4 PC12
Analog comparator ACMP1, channel 4.
ACMP1_CH5 PC13
Analog comparator ACMP1, channel 5.
ACMP1_CH6 PC14
Analog comparator ACMP1, channel 6.
ACMP1_CH7 PC15
Analog comparator ACMP1, channel 7.
ACMP1_O
PF2 PE3 PD7
Analog comparator ACMP1, digital output.
ADC0_CH0
PD0
Analog to digital converter ADC0, input channel number 0.
ADC0_CH1
PD1
Analog to digital converter ADC0, input channel number 1.
ADC0_CH2
PD2
Analog to digital converter ADC0, input channel number 2.
ADC0_CH3
PD3
Analog to digital converter ADC0, input channel number 3.
ADC0_CH4
PD4
Analog to digital converter ADC0, input channel number 4.
ADC0_CH5
PD5
Analog to digital converter ADC0, input channel number 5.
ADC0_CH6
PD6
Analog to digital converter ADC0, input channel number 6.
silabs.com | Building a more connected world.
Rev. 2.30 | 171
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
ADC0_CH7
PD7
Analog to digital converter ADC0, input channel number 7.
BOOT_RX
PE11
Bootloader RX.
BOOT_TX
PE10
Bootloader TX.
BU_STAT
PE3
Backup Power Domain status, whether or not the system is in backup mode
BU_VIN
PD8
Battery input for Backup Power Domain
BU_VOUT
PE2
Power output for Backup Power Domain
CMU_CLK0
PA2 PC12 PD7
Clock Management Unit, clock output number 0.
CMU_CLK1
PA1 PD8 PE12
Clock Management Unit, clock output number 1.
DAC0_OUT0 / OPAMP_OUT0
PB11
Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0.
DAC0_OUT0ALT / OPAMP_OUT0A PC0 PC1 PC2 PC3 PD0 LT
Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0.
DAC0_OUT1 / OPAMP_OUT1
PB12
Digital to Analog Converter DAC0_OUT1 /OPAMP output channel number 1.
DAC0_OUT1ALT / OPAMP_OUT1A PC12 PC13 PC14 PC15 PD1 LT
Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1.
DBG_SWCLK PF0 PF0 PF0 PF0
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, and has a built-in pull down.
DBG_SWDIO PF1 PF1 PF1 PF1
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and has a built-in pull up.
DBG_SWO
PF2 PC15 PD1 PD2
Debug-interface Serial Wire viewer Output.
Note that this function is not enabled after reset, and must be enabled by software to be used.
EBI_A00
PA12 PA12 PA12
External Bus Interface (EBI) address output pin 00.
EBI_A01
PA13 PA13 PA13
External Bus Interface (EBI) address output pin 01.
EBI_A02
PA14 PA14 PA14
External Bus Interface (EBI) address output pin 02.
EBI_A03
PB9 PB9 PB9
External Bus Interface (EBI) address output pin 03.
EBI_A04
PB10 PB10 PB10
External Bus Interface (EBI) address output pin 04.
EBI_A05
PC6 PC6 PC6
External Bus Interface (EBI) address output pin 05.
EBI_A06
PC7 PC7 PC7
External Bus Interface (EBI) address output pin 06.
EBI_A07
PE0 PE0 PE0
External Bus Interface (EBI) address output pin 07.
EBI_A08
PE1 PE1 PE1
External Bus Interface (EBI) address output pin 08.
EBI_A09
PE2 PC9 PC9
External Bus Interface (EBI) address output pin 09.
EBI_A10
PE3 PC10 PC10
External Bus Interface (EBI) address output pin 10.
silabs.com | Building a more connected world.
Rev. 2.30 | 172
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
EBI_A11
PE4 PE4 PE4
External Bus Interface (EBI) address output pin 11.
EBI_A12
PE5 PE5 PE5
External Bus Interface (EBI) address output pin 12.
EBI_A13
PE6 PE6 PE6
External Bus Interface (EBI) address output pin 13.
EBI_A14
PE7 PE7 PE7
External Bus Interface (EBI) address output pin 14.
EBI_A15
PC8 PC8 PC8
External Bus Interface (EBI) address output pin 15.
EBI_A16
PB0 PB0 PB0
External Bus Interface (EBI) address output pin 16.
EBI_A17
PB1 PB1 PB1
External Bus Interface (EBI) address output pin 17.
EBI_A18
PB2 PB2 PB2
External Bus Interface (EBI) address output pin 18.
EBI_A19
PB3 PB3 PB3
External Bus Interface (EBI) address output pin 19.
EBI_A20
PB4 PB4 PB4
External Bus Interface (EBI) address output pin 20.
EBI_A21
PB5 PB5 PB5
External Bus Interface (EBI) address output pin 21.
EBI_A22
PB6 PB6 PB6
External Bus Interface (EBI) address output pin 22.
EBI_A23
PC0 PC0 PC0
External Bus Interface (EBI) address output pin 23.
EBI_A24
PC1 PC1 PC1
External Bus Interface (EBI) address output pin 24.
EBI_A25
PC2 PC2 PC2
External Bus Interface (EBI) address output pin 25.
EBI_A26
PC4 PC4 PC4
External Bus Interface (EBI) address output pin 26.
EBI_A27
PD2 PD2 PD2
External Bus Interface (EBI) address output pin 27.
EBI_AD00
PE8 PE8 PE8
External Bus Interface (EBI) address and data input / output pin 00.
EBI_AD01
PE9 PE9 PE9
External Bus Interface (EBI) address and data input / output pin 01.
EBI_AD02
PE10 PE10 PE10
External Bus Interface (EBI) address and data input / output pin 02.
EBI_AD03
PE11 PE11 PE11
External Bus Interface (EBI) address and data input / output pin 03.
EBI_AD04
PE12 PE12 PE12
External Bus Interface (EBI) address and data input / output pin 04.
EBI_AD05
PE13 PE13 PE13
External Bus Interface (EBI) address and data input / output pin 05.
EBI_AD06
PE14 PE14 PE14
External Bus Interface (EBI) address and data input / output pin 06.
EBI_AD07
PE15 PE15 PE15
External Bus Interface (EBI) address and data input / output pin 07.
EBI_AD08
PA15 PA15 PA15
External Bus Interface (EBI) address and data input / output pin 08.
EBI_AD09
PA0 PA0 PA0
External Bus Interface (EBI) address and data input / output pin 09.
EBI_AD10
PA1 PA1 PA1
External Bus Interface (EBI) address and data input / output pin 10.
EBI_AD11
PA2 PA2 PA2
External Bus Interface (EBI) address and data input / output pin 11.
silabs.com | Building a more connected world.
Rev. 2.30 | 173
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
EBI_AD12
PA3 PA3 PA3
External Bus Interface (EBI) address and data input / output pin 12.
EBI_AD13
PA4 PA4 PA4
External Bus Interface (EBI) address and data input / output pin 13.
EBI_AD14
PA5 PA5 PA5
External Bus Interface (EBI) address and data input / output pin 14.
EBI_AD15
PA6 PA6 PA6
External Bus Interface (EBI) address and data input / output pin 15.
EBI_ALE
PF3 PC11 PC11
External Bus Interface (EBI) Address Latch Enable output.
EBI_ARDY
PF2 PF2 PF2
External Bus Interface (EBI) Hardware Ready Control input.
EBI_BL0
PF6 PF6 PF6
External Bus Interface (EBI) Byte Lane/Enable pin 0.
EBI_BL1
PF7 PF7 PF7
External Bus Interface (EBI) Byte Lane/Enable pin 1.
EBI_CS0
PD9 PD9 PD9
External Bus Interface (EBI) Chip Select output 0.
EBI_CS1
PD10 PD10 PD10
External Bus Interface (EBI) Chip Select output 1.
EBI_CS2
PD11 PD11 PD11
External Bus Interface (EBI) Chip Select output 2.
EBI_CS3
PD12 PD12 PD12
External Bus Interface (EBI) Chip Select output 3.
EBI_CSTFT
PA7 PA7 PA7
External Bus Interface (EBI) Chip Select output TFT.
EBI_DCLK
PA8 PA8 PA8
External Bus Interface (EBI) TFT Dot Clock pin.
EBI_DTEN
PA9 PA9 PA9
External Bus Interface (EBI) TFT Data Enable pin.
EBI_HSNC
PA11 PA11 PA11
External Bus Interface (EBI) TFT Horizontal Synchronization pin.
EBI_NANDREn PC3 PC3 PC3
External Bus Interface (EBI) NAND Read Enable output.
EBI_NANDWEn PC5 PC5 PC5
External Bus Interface (EBI) NAND Write Enable output.
EBI_REn
PF5 PF9 PF5
External Bus Interface (EBI) Read Enable output.
EBI_VSNC
PA10 PA10 PA10
External Bus Interface (EBI) TFT Vertical Synchronization pin.
EBI_WEn
PF4 PF8 PF4
External Bus Interface (EBI) Write Enable output.
ETM_TCLK
PD7 PF8 PC6 PA6
Embedded Trace Module ETM clock .
ETM_TD0
PD6 PF9 PC7 PA2
Embedded Trace Module ETM data 0.
ETM_TD1
PD3 PD13 PD3 PA3
Embedded Trace Module ETM data 1.
ETM_TD2
PD4 PB15 PD4 PA4
Embedded Trace Module ETM data 2.
ETM_TD3
PD5 PF3 PD5 PA5
Embedded Trace Module ETM data 3.
GPIO_EM4WU0 PA0
Pin can be used to wake the system up from EM4
GPIO_EM4WU1 PA6
Pin can be used to wake the system up from EM4
silabs.com | Building a more connected world.
Rev. 2.30 | 174
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
GPIO_EM4WU2 PC9
Pin can be used to wake the system up from EM4
GPIO_EM4WU3 PF1
Pin can be used to wake the system up from EM4
GPIO_EM4WU4 PF2
Pin can be used to wake the system up from EM4
GPIO_EM4WU5 PE13
Pin can be used to wake the system up from EM4
HFXTAL_N
PB14
High Frequency Crystal negative pin. Also used as external optional clock input pin.
HFXTAL_P
PB13
High Frequency Crystal positive pin.
I2C0_SCL
PA1 PD7 PC7 PD15 PC1 PF1 PE13 I2C0 Serial Clock Line input / output.
I2C0_SDA
PA0 PD6 PC6 PD14 PC0 PF0 PE12 I2C0 Serial Data input / output.
I2C1_SCL
PC5 PB12 PE1
I2C1 Serial Clock Line input / output.
I2C1_SDA
PC4 PB11 PE0
I2C1 Serial Data input / output.
LES_ALTEX0 PD6
LESENSE alternate exite output 0.
LES_ALTEX1 PD7
LESENSE alternate exite output 1.
LES_ALTEX2 PA3
LESENSE alternate exite output 2.
LES_ALTEX3 PA4
LESENSE alternate exite output 3.
LES_ALTEX4 PA5
LESENSE alternate exite output 4.
LES_ALTEX5 PE11
LESENSE alternate exite output 5.
LES_ALTEX6 PE12
LESENSE alternate exite output 6.
LES_ALTEX7 PE13
LESENSE alternate exite output 7.
LES_CH0
PC0
LESENSE channel 0.
LES_CH1
PC1
LESENSE channel 1.
LES_CH2
PC2
LESENSE channel 2.
LES_CH3
PC3
LESENSE channel 3.
LES_CH4
PC4
LESENSE channel 4.
LES_CH5
PC5
LESENSE channel 5.
LES_CH6
PC6
LESENSE channel 6.
LES_CH7
PC7
LESENSE channel 7.
LES_CH8
PC8
LESENSE channel 8.
LES_CH9
PC9
LESENSE channel 9.
LES_CH10
PC10
LESENSE channel 10.
LES_CH11
PC11
LESENSE channel 11.
LES_CH12
PC12
LESENSE channel 12.
LES_CH13
PC13
LESENSE channel 13.
LES_CH14
PC14
LESENSE channel 14.
LES_CH15
PC15
LESENSE channel 15.
LETIM0_OUT0 PD6 PB11 PF0 PC4
Low Energy Timer LETIM0, output channel 0.
silabs.com | Building a more connected world.
Rev. 2.30 | 175
Alternate
LOCATION
Functionality
0
1
2
3
4
5
LETIM0_OUT1 PD7 PB12 PF1 PC5
LEU0_RX
PD5 PB14 PE15 PF1 PA0
LEU0_TX
PD4 PB13 PE14 PF0 PF2
LEU1_RX
PC7 PA6
LEU1_TX
PC6 PA5
LFXTAL_N
PB8
LFXTAL_P
PB7
OPAMP_N0 / DAC0_N0
PC5
OPAMP_N1 / DAC0_N1
PD7
OPAMP_N2
PD3
OPAMP_OUT2 PD5 PD0
OPAMP_P0 / DAC0_P0
PC4
OPAMP_P1 / DAC0_P1
PD6
OPAMP_P2
PD4
PCNT0_S0IN PC13 PE0 PC0 PD6
PCNT0_S1IN PC14 PE1 PC1 PD7
PCNT1_S0IN PC4 PB3
PCNT1_S1IN PC5 PB4
PCNT2_S0IN PD0 PE8
PCNT2_S1IN PD1 PE9
PRS_CH0
PA0 PF3
PRS_CH1
PA1 PF4
PRS_CH2
PC0 PF5
PRS_CH3
PC1 PE8
TIM0_CC0
PA0 PA0 PF6 PD1 PA0 PF0
TIM0_CC1
PA1 PA1 PF7 PD2 PC0 PF1
TIM0_CC2
PA2 PA2 PF8 PD3 PC1 PF2
TIM0_CDTI0
PA3 PC13 PF3 PC13 PC2 PF3
TIM0_CDTI1
PA4 PC14 PF4 PC14 PC3 PF4
EFM32LG Data Sheet
Pin Definitions
6
Description
Low Energy Timer LETIM0, output channel 1.
LEUART0 Receive input.
LEUART0 Transmit output. Also used as receive input in half duplex communication.
LEUART1 Receive input.
LEUART1 Transmit output. Also used as receive input in half duplex communication.
Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin.
Low Frequency Crystal (typically 32.768 kHz) positive pin.
Operational Amplifier 0 external negative input.
Operational Amplifier 1 external negative input. Operational Amplifier 2 external negative input. Operational Amplifier 2 output. Operational Amplifier 0 external positive input.
Operational Amplifier 1 external positive input.
Operational Amplifier 2 external positive input. Pulse Counter PCNT0 input number 0. Pulse Counter PCNT0 input number 1. Pulse Counter PCNT1 input number 0. Pulse Counter PCNT1 input number 1. Pulse Counter PCNT2 input number 0. Pulse Counter PCNT2 input number 1. Peripheral Reflex System PRS, channel 0. Peripheral Reflex System PRS, channel 1. Peripheral Reflex System PRS, channel 2. Peripheral Reflex System PRS, channel 3. Timer 0 Capture Compare input / output channel 0. Timer 0 Capture Compare input / output channel 1. Timer 0 Capture Compare input / output channel 2. Timer 0 Complimentary Deat Time Insertion channel 0. Timer 0 Complimentary Deat Time Insertion channel 1.
silabs.com | Building a more connected world.
Rev. 2.30 | 176
Alternate Functionality
TIM0_CDTI2
TIM1_CC0 TIM1_CC1 TIM1_CC2 TIM2_CC0 TIM2_CC1 TIM2_CC2 TIM3_CC0 TIM3_CC1 TIM3_CC2 U0_RX
U0_TX
U1_RX
U1_TX
US0_CLK US0_CS
LOCATION
0
1
2
3
4
5
PA5 PC15 PF5 PC15 PC4 PF5
PC13 PC14 PC15 PA8 PA9 PA10 PE14 PE15 PA15 PF7
PE10 PE11 PE12 PA12 PA13 PA14 PE0 PE1 PE2 PE1
PB0 PB1 PB2 PC8 PC9 PC10
PA4
PB7 PB8 PB11
PC15
PD6 PD7 PC13
PF6 PE0 PA3 PC14
PC13
PB10 PE3
PC12
PB9 PE2
PE12 PE5 PC9 PC15 PB13 PB13 PE13 PE4 PC8 PC14 PB14 PB14
US0_RX
PE11 PE6 PC10 PE12 PB8 PC1
US0_TX
US1_CLK US1_CS US1_RX
PE10 PE7 PC11 PE13 PB7 PC0
PB7 PD2 PF0 PB8 PD3 PF1 PC1 PD1 PD6
US1_TX
US2_CLK US2_CS US2_RX
PC0 PD0 PD7
PC4 PB5 PC5 PB6 PC3 PB4
EFM32LG Data Sheet
Pin Definitions
6
Description
Timer 0 Complimentary Deat Time Insertion channel 2.
Timer 1 Capture Compare input / output channel 0.
Timer 1 Capture Compare input / output channel 1.
Timer 1 Capture Compare input / output channel 2.
Timer 2 Capture Compare input / output channel 0.
Timer 2 Capture Compare input / output channel 1.
Timer 2 Capture Compare input / output channel 2.
Timer 3 Capture Compare input / output channel 0.
Timer 3 Capture Compare input / output channel 1.
Timer 3 Capture Compare input / output channel 2.
UART0 Receive input.
UART0 Transmit output. Also used as receive input in half duplex communication.
UART1 Receive input.
UART1 Transmit output. Also used as receive input in half duplex communication.
USART0 clock input / output.
USART0 chip select input / output.
USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output (MISO).
USART0 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input (MOSI).
USART1 clock input / output.
USART1 chip select input / output.
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output (MISO).
USART1 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input (MOSI).
USART2 clock input / output.
USART2 chip select input / output.
USART2 Asynchronous Receive.
USART2 Synchronous mode Master Input / Slave Output (MISO).
silabs.com | Building a more connected world.
Rev. 2.30 | 177
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
US2_TX
PC2 PB3
USART2 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART2 Synchronous mode Master Output / Slave Input (MOSI).
5.4.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG290 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.12. GPIO Pinout
Port
Port A Port B Port C Port D Port E Port F
Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 15 14 13 12 11 10 PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 -- -- -- -- -- -- PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0
5.4.4 Opamp Pinout Overview
The specific opamp terminals available in EFM32LG290 is shown in the following figure.
PC4
+ OUT0ALT
PC5
OPA0 -
OUT0
PD4
+
PD3
OPA2 -
OUT2
PD6
+ OUT1ALT
OPA1 OUT1
PD7
-
PB11 PB12 PC0 PC1 PC2 PC3 PC12 PC13 PC14 PC15 PD0 PD1 PD5
Figure 5.8. Opamp Pinout
silabs.com | Building a more connected world.
Rev. 2.30 | 178
5.5 EFM32LG295 (BGA120)
EFM32LG Data Sheet
Pin Definitions
5.5.1 Pinout
The EFM32LG295 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question.
Figure 5.9. EFM32LG295 Pinout (top view, not to scale) Table 5.13. Device Pinout
BGA120 Pin# and Name
Pin # Pin Name
A1
PE15
A2
PE14
A3
PE12
Analog
Pin Alternate Functionality / Description
EBI EBI_AD07 #0/1/2 EBI_AD06 #0/1/2
EBI_AD04 #0/1/2
Timers TIM3_CC1 #0 TIM3_CC0 #0
TIM1_CC2 #1
Communication
LEU0_RX #2
LEU0_TX #2
US0_RX #3 US0_CLK #0 I2C0_SDA #6
Other
CMU_CLK1 #2 LES_ALTEX6 #0
silabs.com | Building a more connected world.
Rev. 2.30 | 179
EFM32LG Data Sheet
Pin Definitions
BGA120 Pin# and Name
Pin # Pin Name
A4
PE9
A5
PD11
A6
PD9
A7
PF7
A8
PF5
A9
PF4
Analog
Pin Alternate Functionality / Description
EBI EBI_AD01 #0/1/2 EBI_CS2 #0/1/2 EBI_CS0 #0/1/2 EBI_BL1 #0/1/2
EBI_REn #0/2 EBI_WEn #0/2
Timers PCNT2_S1IN #1
TIM0_CC1 #2 TIM0_CDTI2 #2/5 TIM0_CDTI1 #2/5
Communication U0_RX #0
A10
PF2
EBI_ARDY #0/1/2
TIM0_CC2 #5
LEU0_TX #4
A11 USB_VREGI Input to internal 3.3V USB regulator
A12 USB_VREGO Output and decoupling for internal 3.3V USB regulator
A13
PF11
B1
PA15
EBI_AD08 #0/1/2
TIM3_CC2 #0
B2
PE13
EBI_AD05 #0/1/2
B3
PE11
B4
PE8
B5
PD12
B6
PD10
B7
PF8
B8
PF6
B9
PF3
EBI_AD03 #0/1/2
TIM1_CC1 #1
EBI_AD00 #0/1/2 EBI_CS3 #0/1/2 EBI_CS1 #0/1/2
EBI_WEn #1 EBI_BL0 #0/1/2
PCNT2_S0IN #1
TIM0_CC2 #2 TIM0_CC0 #2
EBI_ALE #0
TIM0_CDTI0 #2/5
B10
PF1
TIM0_CC1 #5 LETIM0_OUT1 #2
B11
PF12
B12 USB_VBUS USB 5.0 V VBUS input.
B13
PF10
C1
PA1
EBI_AD10 #0/1/2 TIM0_CC1 #0/1
C2
PA0
EBI_AD09 #0/1/2 TIM0_CC0 #0/1/4
C3
PE10
EBI_AD02 #0/1/2
TIM1_CC0 #1
C4
PD13
C5
VSS
Ground.
C6
IOVDD_0 Digital IO power supply 0.
C7
PF9
EBI_REn #1
U1_RX #1
US0_TX #3 US0_CS #0 I2C0_SCL #6 US0_RX #0
U0_TX #0
US1_CS #2 LEU0_RX #3 I2C0_SCL #5
U1_TX #1 I2C0_SCL #0 LEU0_RX #4 I2C0_SDA #0 US0_TX #0
Other
PRS_CH2 #1 PRS_CH1 #1 ACMP1_O #0 DBG_SWO #0 GPIO_EM4WU4
LES_ALTEX7 #0 ACMP0_O #0
GPIO_EM4WU5 LES_ALTEX5 #0
BOOT_RX PRS_CH3 #1
ETM_TCLK #1
PRS_CH0 #1 ETM_TD3 #1 DBG_SWDIO
#0/1/2/3 GPIO_EM4WU3
CMU_CLK1 #0 PRS_CH1 #0 PRS_CH0 #0 GPIO_EM4WU0
BOOT_TX ETM_TD1 #1
ETM_TD0 #1
silabs.com | Building a more connected world.
Rev. 2.30 | 180
EFM32LG Data Sheet
Pin Definitions
BGA120 Pin# and Name
Pin # Pin Name
C8
VSS
C9
IOVDD_1
C10
PF0
C11
PE4
C12
PC14
C13
PC15
D1
PA3
D2
PA2
D3
PB15
D11
PE5
D12
PC12
D13
PC13
E1
PA6
E2
PA5
E3
PA4
E11
PE6
E12
PC10
E13
PC11
F1
PB0
F2
PB1
F3
PB2
F11
PE7
F12
PC8
F13
PC9
Pin Alternate Functionality / Description
Analog
EBI
Ground.
Digital IO power supply 1.
ACMP1_CH6 DAC0_OUT1ALT
#2/ OPAMP_OUT1ALT
ACMP1_CH7 DAC0_OUT1ALT
#3/ OPAMP_OUT1ALT
EBI_A11 #0/1/2
Timers
Communication
TIM0_CC0 #5 LETIM0_OUT0 #2
US1_CLK #2 LEU0_TX #3 I2C0_SDA #5
US0_CS #1
TIM0_CDTI1 #1/3 TIM1_CC1 #0
PCNT0_S1IN #0
US0_CS #3 U0_TX #3
TIM0_CDTI2 #1/3 TIM1_CC2 #0
US0_CLK #3 U0_RX #3
EBI_AD12 #0/1/2 TIM0_CDTI0 #0
U0_TX #2
EBI_AD11 #0/1/2 TIM0_CC2 #0/1
ACMP1_CH4 DAC0_OUT1ALT
#0/ OPAMP_OUT1ALT
ACMP1_CH5 DAC0_OUT1ALT
#1/ OPAMP_OUT1ALT
EBI_A12 #0/1/2
TIM0_CDTI0 #1/3 TIM1_CC0 #0 TIM1_CC2 #4
PCNT0_S0IN #0
EBI_AD15 #0/1/2
EBI_AD14 #0/1/2 TIM0_CDTI2 #0
ACMP1_CH2 ACMP1_CH3
ACMP1_CH0 ACMP1_CH1
EBI_AD13 #0/1/2
EBI_A13 #0/1/2 EBI_A10 #1/2 EBI_ALE #1/2 EBI_A16 #0/1/2 EBI_A17 #0/1/2 EBI_A18 #0/1/2 EBI_A14 #0/1/2 EBI_A15 #0/1/2
EBI_A09 #1/2
TIM0_CDTI1 #0
TIM2_CC2 #2
TIM1_CC0 #2 TIM1_CC1 #2 TIM1_CC2 #2
TIM2_CC0 #2 TIM2_CC1 #2
US0_CLK #1 U1_TX #0
U1_RX #0
LEU1_RX #1 LEU1_TX #1
U0_RX #2 US0_RX #1 US0_RX #2 US0_TX #2
US0_TX #1 US0_CS #2 US0_CLK #2
Other
DBG_SWCLK #0/1/2/3
LES_CH14 #0
LES_CH15 #0 DBG_SWO #1 LES_ALTEX2 #0 ETM_TD1 #3 CMU_CLK0 #0 ETM_TD0 #3 ETM_TD2 #1
CMU_CLK0 #1 LES_CH12 #0
LES_CH13 #0
ETM_TCLK #3 GPIO_EM4WU1 LES_ALTEX4 #0
ETM_TD3 #3 LES_ALTEX3 #0
ETM_TD2 #3
LES_CH10 #0 LES_CH11 #0
LES_CH8 #0 LES_CH9 #0 GPIO_EM4WU2
silabs.com | Building a more connected world.
Rev. 2.30 | 181
EFM32LG Data Sheet
Pin Definitions
BGA120 Pin# and Name
Pin # Pin Name
G1
PB3
G2
PB4
G3
IOVDD_2
G11
PE0
G12
PE1
G13
PE3
H1
PB5
H2
PB6
H3
VSS
H11 VDD_DREG
H12
PE2
H13
PC7
J1
PD14
J2
PD15
J3
VSS
J11
IOVDD_3
J12
PC6
J13 DECOUPLE
K1
PC0
K2
PC1
K3
IOVDD_4
K11
VSS
K12
VSS
K13
PD8
L1
PC2
Pin Alternate Functionality / Description
Analog
EBI
Timers
Communication
Other
EBI_A19 #0/1/2
PCNT1_S0IN #1
US2_TX #1
EBI_A20 #0/1/2
PCNT1_S1IN #1
US2_RX #1
Digital IO power supply 2.
EBI_A07 #0/1/2
TIM3_CC0 #1 PCNT0_S0IN #1
U0_TX #1 I2C1_SDA #2
EBI_A08 #0/1/2
TIM3_CC1 #1 PCNT0_S1IN #1
U0_RX #1 I2C1_SCL #2
BU_STAT
EBI_A10 #0
U1_RX #3
ACMP1_O #1
EBI_A21 #0/1/2
US2_CLK #1
EBI_A22 #0/1/2
US2_CS #1
Ground.
Power supply for on-chip voltage regulator.
BU_VOUT
EBI_A09 #0
TIM3_CC2 #1
U1_TX #3
ACMP0_O #1
ACMP0_CH7
EBI_A06 #0/1/2
LEU1_RX #0 I2C0_SCL #2
LES_CH7 #0 ETM_TD0 #2
I2C0_SDA #3
I2C0_SCL #3
Ground.
Digital IO power supply 3.
ACMP0_CH6
EBI_A05 #0/1/2
LEU1_TX #0 I2C0_SDA #2
LES_CH6 #0 ETM_TCLK #2
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin.
ACMP0_CH0 DAC0_OUT0ALT
#0/ OPAMP_OUT0ALT
EBI_A23 #0/1/2
TIM0_CC1 #4 PCNT0_S0IN #2
US0_TX #5 US1_TX #0 I2C0_SDA #4
LES_CH0 #0 PRS_CH2 #0
ACMP0_CH1 DAC0_OUT0ALT
#1/ OPAMP_OUT0ALT
EBI_A24 #0/1/2
TIM0_CC2 #4 PCNT0_S1IN #2
US0_RX #5 US1_RX #0 I2C0_SCL #4
LES_CH1 #0 PRS_CH3 #0
Digital IO power supply 4.
Ground.
Ground.
BU_VIN
CMU_CLK1 #1
ACMP0_CH2 DAC0_OUT0ALT
#2/ OPAMP_OUT0ALT
EBI_A25 #0/1/2
TIM0_CDTI0 #4
US2_TX #0
LES_CH2 #0
silabs.com | Building a more connected world.
Rev. 2.30 | 182
EFM32LG Data Sheet
Pin Definitions
BGA120 Pin# and Name
Pin # Pin Name
L2
PC3
L3
PA7
L4
IOVDD_5
L5
VSS
L6
VSS
L7
IOVDD_6
L8
PB9
L9
PB10
L10
PD0
L11
PD1
L12
PD4
L13
PD7
M1
PB7
M2
PC4
M3
PA8
M4
PA10
M5
PA13
M6
PA14
M7
RESETn
M8
AVSS_1
M9
AVDD_2
M10
AVDD_1
M11
AVSS_0
M12
PD3
Pin Alternate Functionality / Description
Analog
EBI
Timers
Communication
Other
ACMP0_CH3 DAC0_OUT0ALT
#3/ OPAMP_OUT0ALT
EBI_NANDREn #0/1/2
TIM0_CDTI1 #4
US2_RX #0
LES_CH3 #0
EBI_CSTFT #0/1/2
Digital IO power supply 5.
Ground.
Ground.
Digital IO power supply 6.
EBI_A03 #0/1/2
U1_TX #2
EBI_A04 #0/1/2
U1_RX #2
ADC0_CH0 DAC0_OUT0ALT
#4/ OPAMP_OUT0ALT OPAMP_OUT2 #1
PCNT2_S0IN #0
US1_TX #1
ADC0_CH1 DAC0_OUT1ALT
#4/ OPAMP_OUT1ALT
TIM0_CC0 #3 PCNT2_S1IN #0
US1_RX #1
DBG_SWO #2
ADC0_CH4 OPAMP_P2
LEU0_TX #0
ETM_TD2 #0/2
ADC0_CH7 / DAC0_N1 / OPAMP_N1
TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3
US1_TX #2 I2C0_SCL #1
CMU_CLK0 #2 LES_ALTEX1 #0
ACMP1_O #2 ETM_TCLK #0
LFXTAL_P
TIM1_CC0 #3
US0_TX #4 US1_CLK #0
ACMP0_CH4 / DAC0_P0 / OPAMP_P0
EBI_A26 #0/1/2
TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0
US2_CLK #0 I2C1_SDA #0
LES_CH4 #0
EBI_DCLK #0/1/2
TIM2_CC0 #0
EBI_VSNC #0/1/2
TIM2_CC2 #0
EBI_A01 #0/1/2
TIM2_CC1 #1
EBI_A02 #0/1/2
TIM2_CC2 #1
Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released.
Analog ground 1.
Analog power supply 2.
Analog power supply 1.
Analog ground 0.
ADC0_CH3 OPAMP_N2
TIM0_CC2 #3
US1_CS #1
ETM_TD1 #0/2
silabs.com | Building a more connected world.
Rev. 2.30 | 183
EFM32LG Data Sheet
Pin Definitions
BGA120 Pin# and Name
Pin # Pin Name
M13
PD6
N1
PB8
N2
PC5
N3
PA9
N4
PA11
N5
PA12
N6
PB11
N7
PB12
N8
AVSS_2
N9
PB13
N10
PB14
N11
AVDD_0
N12
PD2
N13
PD5
Pin Alternate Functionality / Description
Analog ADC0_CH6 / DAC0_P1 / OPAMP_P1
LFXTAL_N
ACMP0_CH5 / DAC0_N0 / OPAMP_N0
DAC0_OUT0 / OPAMP_OUT0 DAC0_OUT1 / OPAMP_OUT1 Analog ground 2.
HFXTAL_P
EBI
Timers
TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3
TIM1_CC1 #3
EBI_NANDWEn #0/1/2
LETIM0_OUT1 #3 PCNT1_S1IN #0
EBI_DTEN #0/1/2 EBI_HSNC #0/1/2
EBI_A00 #0/1/2
TIM2_CC1 #0
TIM2_CC0 #1 TIM1_CC2 #3 LE-
TIM0_OUT0 #1
LETIM0_OUT1 #1
HFXTAL_N
Analog power supply 0.
ADC0_CH2
EBI_A27 #0/1/2
ADC0_CH5 OPAMP_OUT2 #0
TIM0_CC1 #3
Communication US1_RX #2 I2C0_SDA #1 US0_RX #4 US1_CS #0 US2_CS #0 I2C1_SCL #0
I2C1_SDA #1 I2C1_SCL #1
US0_CLK #4/5 LEU0_TX #1 US0_CS #4/5 LEU0_RX #1
US1_CLK #1 LEU0_RX #0
Other LES_ALTEX0 #0
ACMP0_O #2 ETM_TD0 #0 LES_CH5 #0
DBG_SWO #3 ETM_TD3 #0/2
silabs.com | Building a more connected world.
Rev. 2.30 | 184
EFM32LG Data Sheet
Pin Definitions
5.5.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0.
Alternate Functionality ACMP0_CH0 ACMP0_CH1 ACMP0_CH2 ACMP0_CH3 ACMP0_CH4 ACMP0_CH5 ACMP0_CH6 ACMP0_CH7 ACMP0_O ACMP1_CH0 ACMP1_CH1 ACMP1_CH2 ACMP1_CH3 ACMP1_CH4 ACMP1_CH5 ACMP1_CH6 ACMP1_CH7 ACMP1_O ADC0_CH0
ADC0_CH1
ADC0_CH2
ADC0_CH3
ADC0_CH4
ADC0_CH5
ADC0_CH6
Table 5.14. Alternate Functionality Overview
LOCATION
0
1
2
3
4
5
6
Description
PC0
Analog comparator ACMP0, channel 0.
PC1
Analog comparator ACMP0, channel 1.
PC2
Analog comparator ACMP0, channel 2.
PC3
Analog comparator ACMP0, channel 3.
PC4
Analog comparator ACMP0, channel 4.
PC5
Analog comparator ACMP0, channel 5.
PC6
Analog comparator ACMP0, channel 6.
PC7
Analog comparator ACMP0, channel 7.
PE13 PE2 PD6
Analog comparator ACMP0, digital output.
PC8
Analog comparator ACMP1, channel 0.
PC9
Analog comparator ACMP1, channel 1.
PC10
Analog comparator ACMP1, channel 2.
PC11
Analog comparator ACMP1, channel 3.
PC12
Analog comparator ACMP1, channel 4.
PC13
Analog comparator ACMP1, channel 5.
PC14
Analog comparator ACMP1, channel 6.
PC15
Analog comparator ACMP1, channel 7.
PF2 PE3 PD7
Analog comparator ACMP1, digital output.
PD0
Analog to digital converter ADC0, input channel number 0.
PD1
Analog to digital converter ADC0, input channel number 1.
PD2
Analog to digital converter ADC0, input channel number 2.
PD3
Analog to digital converter ADC0, input channel number 3.
PD4
Analog to digital converter ADC0, input channel number 4.
PD5
Analog to digital converter ADC0, input channel number 5.
PD6
Analog to digital converter ADC0, input channel number 6.
silabs.com | Building a more connected world.
Rev. 2.30 | 185
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
ADC0_CH7
PD7
Analog to digital converter ADC0, input channel number 7.
BOOT_RX
PE11
Bootloader RX.
BOOT_TX
PE10
Bootloader TX.
BU_STAT
PE3
Backup Power Domain status, whether or not the system is in backup mode
BU_VIN
PD8
Battery input for Backup Power Domain
BU_VOUT
PE2
Power output for Backup Power Domain
CMU_CLK0
PA2 PC12 PD7
Clock Management Unit, clock output number 0.
CMU_CLK1
PA1 PD8 PE12
Clock Management Unit, clock output number 1.
OPAMP_N0 / DAC0_N0
PC5
Operational Amplifier 0 external negative input.
OPAMP_N1 / DAC0_N1
PD7
Operational Amplifier 1 external negative input.
OPAMP_N2
PD3
Operational Amplifier 2 external negative input.
DAC0_OUT0 / OPAMP_OUT0
PB11
Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0.
DAC0_OUT0ALT / OPAMP_OUT0ALT
PC0
PC1
PC2
PC3
PD0
Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0.
DAC0_OUT1 / OPAMP_OUT1
PB12
Digital to Analog Converter DAC0_OUT1 / OPAMP output channel number 1.
DAC0_OUT1ALT / OPAMP_OUT1ALT
PC12
PC13
PC14
PC15
PD1
Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1.
OPAMP_OUT2
PD5 PD0
Operational Amplifier 2 output.
OPAMP_P0 / DAC0_P0
PC4
Operational Amplifier 0 external positive input.
OPAMP_P1 / DAC0_P1
PD6
Operational Amplifier 1 external positive input.
OPAMP_P2
PD4
Operational Amplifier 2 external positive input.
DBG_SWCLK
PF0 PF0 PF0 PF0
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, and has a built-in pull down.
DBG_SWDIO
PF1 PF1 PF1 PF1
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and has a built-in pull up.
DBG_SWO
PF2 PC15 PD1 PD2
Debug-interface Serial Wire viewer Output.
Note that this function is not enabled after reset, and must be enabled by software to be used.
EBI_A00
PA12 PA12 PA12
External Bus Interface (EBI) address output pin 00.
EBI_A01
PA13 PA13 PA13
External Bus Interface (EBI) address output pin 01.
EBI_A02
PA14 PA14 PA14
External Bus Interface (EBI) address output pin 02.
silabs.com | Building a more connected world.
Rev. 2.30 | 186
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
EBI_A03
PB9 PB9 PB9
External Bus Interface (EBI) address output pin 03.
EBI_A04
PB10 PB10 PB10
External Bus Interface (EBI) address output pin 04.
EBI_A05
PC6 PC6 PC6
External Bus Interface (EBI) address output pin 05.
EBI_A06
PC7 PC7 PC7
External Bus Interface (EBI) address output pin 06.
EBI_A07
PE0 PE0 PE0
External Bus Interface (EBI) address output pin 07.
EBI_A08
PE1 PE1 PE1
External Bus Interface (EBI) address output pin 08.
EBI_A09
PE2 PC9 PC9
External Bus Interface (EBI) address output pin 09.
EBI_A10
PE3 PC10 PC10
External Bus Interface (EBI) address output pin 10.
EBI_A11
PE4 PE4 PE4
External Bus Interface (EBI) address output pin 11.
EBI_A12
PE5 PE5 PE5
External Bus Interface (EBI) address output pin 12.
EBI_A13
PE6 PE6 PE6
External Bus Interface (EBI) address output pin 13.
EBI_A14
PE7 PE7 PE7
External Bus Interface (EBI) address output pin 14.
EBI_A15
PC8 PC8 PC8
External Bus Interface (EBI) address output pin 15.
EBI_A16
PB0 PB0 PB0
External Bus Interface (EBI) address output pin 16.
EBI_A17
PB1 PB1 PB1
External Bus Interface (EBI) address output pin 17.
EBI_A18
PB2 PB2 PB2
External Bus Interface (EBI) address output pin 18.
EBI_A19
PB3 PB3 PB3
External Bus Interface (EBI) address output pin 19.
EBI_A20
PB4 PB4 PB4
External Bus Interface (EBI) address output pin 20.
EBI_A21
PB5 PB5 PB5
External Bus Interface (EBI) address output pin 21.
EBI_A22
PB6 PB6 PB6
External Bus Interface (EBI) address output pin 22.
EBI_A23
PC0 PC0 PC0
External Bus Interface (EBI) address output pin 23.
EBI_A24
PC1 PC1 PC1
External Bus Interface (EBI) address output pin 24.
EBI_A25
PC2 PC2 PC2
External Bus Interface (EBI) address output pin 25.
EBI_A26
PC4 PC4 PC4
External Bus Interface (EBI) address output pin 26.
EBI_A27
PD2 PD2 PD2
External Bus Interface (EBI) address output pin 27.
EBI_AD00
PE8 PE8 PE8
External Bus Interface (EBI) address and data input / output pin 00.
EBI_AD01
PE9 PE9 PE9
External Bus Interface (EBI) address and data input / output pin 01.
EBI_AD02
PE10 PE10 PE10
External Bus Interface (EBI) address and data input / output pin 02.
EBI_AD03
PE11 PE11 PE11
External Bus Interface (EBI) address and data input / output pin 03.
EBI_AD04
PE12 PE12 PE12
External Bus Interface (EBI) address and data input / output pin 04.
EBI_AD05
PE13 PE13 PE13
External Bus Interface (EBI) address and data input / output pin 05.
EBI_AD06
PE14 PE14 PE14
External Bus Interface (EBI) address and data input / output pin 06.
silabs.com | Building a more connected world.
Rev. 2.30 | 187
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
EBI_AD07
PE15 PE15 PE15
External Bus Interface (EBI) address and data input / output pin 07.
EBI_AD08
PA15 PA15 PA15
External Bus Interface (EBI) address and data input / output pin 08.
EBI_AD09
PA0 PA0 PA0
External Bus Interface (EBI) address and data input / output pin 09.
EBI_AD10
PA1 PA1 PA1
External Bus Interface (EBI) address and data input / output pin 10.
EBI_AD11
PA2 PA2 PA2
External Bus Interface (EBI) address and data input / output pin 11.
EBI_AD12
PA3 PA3 PA3
External Bus Interface (EBI) address and data input / output pin 12.
EBI_AD13
PA4 PA4 PA4
External Bus Interface (EBI) address and data input / output pin 13.
EBI_AD14
PA5 PA5 PA5
External Bus Interface (EBI) address and data input / output pin 14.
EBI_AD15
PA6 PA6 PA6
External Bus Interface (EBI) address and data input / output pin 15.
EBI_ALE
PF3 PC11 PC11
External Bus Interface (EBI) Address Latch Enable output.
EBI_ARDY
PF2 PF2 PF2
External Bus Interface (EBI) Hardware Ready Control input.
EBI_BL0
PF6 PF6 PF6
External Bus Interface (EBI) Byte Lane/Enable pin 0.
EBI_BL1
PF7 PF7 PF7
External Bus Interface (EBI) Byte Lane/Enable pin 1.
EBI_CS0
PD9 PD9 PD9
External Bus Interface (EBI) Chip Select output 0.
EBI_CS1
PD10 PD10 PD10
External Bus Interface (EBI) Chip Select output 1.
EBI_CS2
PD11 PD11 PD11
External Bus Interface (EBI) Chip Select output 2.
EBI_CS3
PD12 PD12 PD12
External Bus Interface (EBI) Chip Select output 3.
EBI_CSTFT
PA7 PA7 PA7
External Bus Interface (EBI) Chip Select output TFT.
EBI_DCLK
PA8 PA8 PA8
External Bus Interface (EBI) TFT Dot Clock pin.
EBI_DTEN
PA9 PA9 PA9
External Bus Interface (EBI) TFT Data Enable pin.
EBI_HSNC
PA11 PA11 PA11
External Bus Interface (EBI) TFT Horizontal Synchronization pin.
EBI_NANDREn
PC3 PC3 PC3
External Bus Interface (EBI) NAND Read Enable output.
EBI_NANDWEn
PC5 PC5 PC5
External Bus Interface (EBI) NAND Write Enable output.
EBI_REn
PF5 PF9 PF5
External Bus Interface (EBI) Read Enable output.
EBI_VSNC
PA10 PA10 PA10
External Bus Interface (EBI) TFT Vertical Synchronization pin.
silabs.com | Building a more connected world.
Rev. 2.30 | 188
Alternate Functionality EBI_WEn ETM_TCLK ETM_TD0 ETM_TD1 ETM_TD2 ETM_TD3 GPIO_EM4WU0 GPIO_EM4WU1 GPIO_EM4WU2 GPIO_EM4WU3 GPIO_EM4WU4 GPIO_EM4WU5
HFXTAL_N
HFXTAL_P I2C0_SCL I2C0_SDA I2C1_SCL I2C1_SDA LES_ALTEX0 LES_ALTEX1 LES_ALTEX2 LES_ALTEX3 LES_ALTEX4 LES_ALTEX5 LES_ALTEX6 LES_ALTEX7 LES_CH0 LES_CH1 LES_CH2 LES_CH3 LES_CH4 LES_CH5 LES_CH6 LES_CH7 LES_CH8
EFM32LG Data Sheet
Pin Definitions
LOCATION
0
1
2
3
4
5
6
Description
PF4 PF8 PF4
External Bus Interface (EBI) Write Enable output.
PD7 PF8 PC6 PA6
Embedded Trace Module ETM clock .
PD6 PF9 PC7 PA2
Embedded Trace Module ETM data 0.
PD3 PD13 PD3 PA3
Embedded Trace Module ETM data 1.
PD4 PB15 PD4 PA4
Embedded Trace Module ETM data 2.
PD5 PF3 PD5 PA5
Embedded Trace Module ETM data 3.
PA0
Pin can be used to wake the system up from EM4
PA6
Pin can be used to wake the system up from EM4
PC9
Pin can be used to wake the system up from EM4
PF1
Pin can be used to wake the system up from EM4
PF2
Pin can be used to wake the system up from EM4
PE13
Pin can be used to wake the system up from EM4
PB14
High Frequency Crystal negative pin. Also used as external optional clock input pin.
PB13
High Frequency Crystal positive pin.
PA1 PD7 PC7 PD15 PC1 PF1 PE13 I2C0 Serial Clock Line input / output.
PA0 PD6 PC6 PD14 PC0 PF0 PE12 I2C0 Serial Data input / output.
PC5 PB12 PE1
I2C1 Serial Clock Line input / output.
PC4 PB11 PE0
I2C1 Serial Data input / output.
PD6
LESENSE alternate exite output 0.
PD7
LESENSE alternate exite output 1.
PA3
LESENSE alternate exite output 2.
PA4
LESENSE alternate exite output 3.
PA5
LESENSE alternate exite output 4.
PE11
LESENSE alternate exite output 5.
PE12
LESENSE alternate exite output 6.
PE13
LESENSE alternate exite output 7.
PC0
LESENSE channel 0.
PC1
LESENSE channel 1.
PC2
LESENSE channel 2.
PC3
LESENSE channel 3.
PC4
LESENSE channel 4.
PC5
LESENSE channel 5.
PC6
LESENSE channel 6.
PC7
LESENSE channel 7.
PC8
LESENSE channel 8.
silabs.com | Building a more connected world.
Rev. 2.30 | 189
Alternate
LOCATION
Functionality
0
1
2
3
4
5
LES_CH9
PC9
LES_CH10
PC10
LES_CH11
PC11
LES_CH12
PC12
LES_CH13
PC13
LES_CH14
PC14
LES_CH15
PC15
LETIM0_OUT0
PD6 PB11 PF0 PC4
LETIM0_OUT1
PD7 PB12 PF1 PC5
LEU0_RX
PD5 PB14 PE15 PF1 PA0
LEU0_TX
PD4 PB13 PE14 PF0 PF2
LEU1_RX
PC7 PA6
LEU1_TX
PC6 PA5
LFXTAL_N
PB8
LFXTAL_P
PCNT0_S0IN PCNT0_S1IN PCNT1_S0IN PCNT1_S1IN PCNT2_S0IN PCNT2_S1IN PRS_CH0 PRS_CH1 PRS_CH2 PRS_CH3 TIM0_CC0 TIM0_CC1 TIM0_CC2
TIM0_CDTI0
TIM0_CDTI1
TIM0_CDTI2
PB7
PC13 PE0 PC0 PD6 PC14 PE1 PC1 PD7 PC4 PB3 PC5 PB4 PD0 PE8 PD1 PE9 PA0 PF3 PA1 PF4 PC0 PF5 PC1 PE8 PA0 PA0 PF6 PD1 PA0 PF0 PA1 PA1 PF7 PD2 PC0 PF1 PA2 PA2 PF8 PD3 PC1 PF2
PA3 PC13 PF3 PC13 PC2 PF3
PA4 PC14 PF4 PC14 PC3 PF4
PA5 PC15 PF5 PC15 PC4 PF5
EFM32LG Data Sheet
Pin Definitions
6
Description
LESENSE channel 9.
LESENSE channel 10.
LESENSE channel 11.
LESENSE channel 12.
LESENSE channel 13.
LESENSE channel 14.
LESENSE channel 15.
Low Energy Timer LETIM0, output channel 0.
Low Energy Timer LETIM0, output channel 1.
LEUART0 Receive input.
LEUART0 Transmit output. Also used as receive input in half duplex communication.
LEUART1 Receive input.
LEUART1 Transmit output. Also used as receive input in half duplex communication.
Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin.
Low Frequency Crystal (typically 32.768 kHz) positive pin.
Pulse Counter PCNT0 input number 0.
Pulse Counter PCNT0 input number 1.
Pulse Counter PCNT1 input number 0.
Pulse Counter PCNT1 input number 1.
Pulse Counter PCNT2 input number 0.
Pulse Counter PCNT2 input number 1.
Peripheral Reflex System PRS, channel 0.
Peripheral Reflex System PRS, channel 1.
Peripheral Reflex System PRS, channel 2.
Peripheral Reflex System PRS, channel 3.
Timer 0 Capture Compare input / output channel 0.
Timer 0 Capture Compare input / output channel 1.
Timer 0 Capture Compare input / output channel 2.
Timer 0 Complimentary Deat Time Insertion channel 0.
Timer 0 Complimentary Deat Time Insertion channel 1.
Timer 0 Complimentary Deat Time Insertion channel 2.
silabs.com | Building a more connected world.
Rev. 2.30 | 190
Alternate Functionality TIM1_CC0 TIM1_CC1 TIM1_CC2 TIM2_CC0 TIM2_CC1 TIM2_CC2 TIM3_CC0 TIM3_CC1 TIM3_CC2 U0_RX U0_TX U1_RX U1_TX US0_CLK US0_CS
US0_RX
US0_TX
US1_CLK US1_CS
US1_RX
US1_TX
US2_CLK US2_CS
US2_RX
LOCATION
0
1
2
3
4
5
PC13 PE10 PB0 PB7 PD6
PC14 PE11 PB1 PB8 PD7
PC15 PE12 PB2 PB11 PC13
PA8 PA12 PC8
PA9 PA13 PC9
PA10 PA14 PC10
PE14 PE0
PE15 PE1
PA15 PE2
PF7 PE1 PA4 PC15
PF6 PE0 PA3 PC14
PC13 PF11 PB10 PE3
PC12 PF10 PB9 PE2
PE12 PE5 PC9 PC15 PB13 PB13 PE13 PE4 PC8 PC14 PB14 PB14
PE11 PE6 PC10 PE12 PB8 PC1
PE10 PE7 PC11 PE13 PB7 PC0
PB7 PD2 PF0 PB8 PD3 PF1 PC1 PD1 PD6
PC0 PD0 PD7
PC4 PB5 PC5 PB6 PC3 PB4
EFM32LG Data Sheet
Pin Definitions
6
Description
Timer 1 Capture Compare input / output channel 0.
Timer 1 Capture Compare input / output channel 1.
Timer 1 Capture Compare input / output channel 2.
Timer 2 Capture Compare input / output channel 0.
Timer 2 Capture Compare input / output channel 1.
Timer 2 Capture Compare input / output channel 2.
Timer 3 Capture Compare input / output channel 0.
Timer 3 Capture Compare input / output channel 1.
Timer 3 Capture Compare input / output channel 2.
UART0 Receive input.
UART0 Transmit output. Also used as receive input in half duplex communication.
UART1 Receive input.
UART1 Transmit output. Also used as receive input in half duplex communication.
USART0 clock input / output.
USART0 chip select input / output.
USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output (MISO).
USART0 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input (MOSI).
USART1 clock input / output.
USART1 chip select input / output.
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output (MISO).
USART1 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input (MOSI).
USART2 clock input / output.
USART2 chip select input / output.
USART2 Asynchronous Receive.
USART2 Synchronous mode Master Input / Slave Output (MISO).
silabs.com | Building a more connected world.
Rev. 2.30 | 191
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
US2_TX
PC2 PB3
USART2 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART2 Synchronous mode Master Output / Slave Input (MOSI).
5.5.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG295 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.15. GPIO Pinout
Port
Port A Port B Port C Port D Port E Port F
Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 15 14 13 12 11 10 PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 -- -- -- PF12 PF11 PF10 PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0
5.5.4 Opamp Pinout Overview
The specific opamp terminals available in EFM32LG295 is shown in the following figure.
PC4
+ OUT0ALT
PC5
OPA0 -
OUT0
PD4
+
PD3
OPA2 -
OUT2
PD6
+ OUT1ALT
OPA1 OUT1
PD7
-
PB11 PB12 PC0 PC1 PC2 PC3 PC12 PC13 PC14 PC15 PD0 PD1 PD5
Figure 5.10. Opamp Pinout
silabs.com | Building a more connected world.
Rev. 2.30 | 192
5.6 EFM32LG330 (QFN64)
EFM32LG Data Sheet
Pin Definitions
5.6.1 Pinout
The EFM32LG330 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question.
Figure 5.11. EFM32LG330 Pinout (top view, not to scale) Table 5.16. Device Pinout
QFN64 Pin# and Name
Pin #
Pin Name
0
VSS
Analog Ground.
1
PA0
2
PA1
Pin Alternate Functionality / Description
Timers
Communication
Other
TIM0_CC0 #0/1/4 TIM0_CC1 #0/1
LEU0_RX #4 I2C0_SDA #0
I2C0_SCL #0
PRS_CH0 #0 GPIO_EM4WU0
CMU_CLK1 #0 PRS_CH1 #0
silabs.com | Building a more connected world.
Rev. 2.30 | 193
EFM32LG Data Sheet
Pin Definitions
QFN64 Pin# and Name
Pin #
Pin Name
3
PA2
4
PA3
5
PA4
6
PA5
7
PA6
8
IOVDD_0
9
PC0
10
PC1
11
PC2
12
PC3
13
PC4
14
PC5
15
PB7
16
PB8
17
PA8
18
PA9
19
PA10
20
RESETn
21
PB11
22
PB12
23
AVDD_1
24
PB13
25
PB14
Pin Alternate Functionality / Description
Analog
Timers
Communication
Other
TIM0_CC2 #0/1
CMU_CLK0 #0 ETM_TD0 #3
TIM0_CDTI0 #0
LES_ALTEX2 #0 ETM_TD1 #3
TIM0_CDTI1 #0
LES_ALTEX3 #0 ETM_TD2 #3
TIM0_CDTI2 #0
LEU1_TX #1
LES_ALTEX4 #0 ETM_TD3 #3
LEU1_RX #1
ETM_TCLK #3 GPIO_EM4WU1
Digital IO power supply 0.
ACMP0_CH0 DAC0_OUT0ALT #0/ OPAMP_OUT0ALT
TIM0_CC1 #4 PCNT0_S0IN #2
US0_TX #5 US1_TX #0 LES_CH0 #0 PRS_CH2
I2C0_SDA #4
#0
ACMP0_CH1 DAC0_OUT0ALT #1/ OPAMP_OUT0ALT
TIM0_CC2 #4 PCNT0_S1IN #2
US0_RX #5 US1_RX #0 LES_CH1 #0 PRS_CH3
I2C0_SCL #4
#0
ACMP0_CH2 DAC0_OUT0ALT #2/ OPAMP_OUT0ALT
TIM0_CDTI0 #4
US2_TX #0
LES_CH2 #0
ACMP0_CH3 DAC0_OUT0ALT #3/ OPAMP_OUT0ALT
TIM0_CDTI1 #4
US2_RX #0
LES_CH3 #0
ACMP0_CH4 / DAC0_P0 / OPAMP_P0
TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0
US2_CLK #0 I2C1_SDA #0
LES_CH4 #0
ACMP0_CH5 / DAC0_N0 / OPAMP_N0
LETIM0_OUT1 #3 PCNT1_S1IN #0
US2_CS #0 I2C1_SCL #0
LES_CH5 #0
LFXTAL_P
TIM1_CC0 #3
US0_TX #4 US1_CLK #0
LFXTAL_N
TIM1_CC1 #3
US0_RX #4 US1_CS #0
TIM2_CC0 #0
TIM2_CC1 #0
TIM2_CC2 #0
Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released.
DAC0_OUT0 / OPAMP_OUT0
TIM1_CC2 #3 LETIM0_OUT0 #1
I2C1_SDA #1
DAC0_OUT1 / OPAMP_OUT1
LETIM0_OUT1 #1
I2C1_SCL #1
Analog power supply 1.
HFXTAL_P
US0_CLK #4/5 LEU0_TX #1
HFXTAL_N
US0_CS #4/5 LEU0_RX #1
silabs.com | Building a more connected world.
Rev. 2.30 | 194
EFM32LG Data Sheet
Pin Definitions
QFN64 Pin# and Name
Pin #
Pin Name
26
IOVDD_3
27
AVDD_0
28
PD0
29
PD1
30
PD2
31
PD3
32
PD4
33
PD5
34
PD6
35
PD7
36
PD8
37
PC6
38
PC7
39
VDD_DREG
40
DECOUPLE
41
PC8
42
PC9
43
PC10
44
PC11
45
USB_VREGI
46
USB_VREGO
47
PF10
48
PF11
49
PF0
50
PF1
Pin Alternate Functionality / Description
Analog
Timers
Communication
Other
Digital IO power supply 3.
Analog power supply 0.
ADC0_CH0 DAC0_OUT0ALT #4/ OPAMP_OUT0ALT
OPAMP_OUT2 #1
PCNT2_S0IN #0
US1_TX #1
ADC0_CH1 DAC0_OUT1ALT #4/ OPAMP_OUT1ALT
TIM0_CC0 #3 PCNT2_S1IN #0
US1_RX #1
DBG_SWO #2
ADC0_CH2
TIM0_CC1 #3
USB_DMPU #0 US1_CLK #1
DBG_SWO #3
ADC0_CH3 OPAMP_N2
TIM0_CC2 #3
US1_CS #1
ETM_TD1 #0/2
ADC0_CH4 OPAMP_P2
LEU0_TX #0
ETM_TD2 #0/2
ADC0_CH5 OPAMP_OUT2 #0
LEU0_RX #0
ETM_TD3 #0/2
ADC0_CH6 / DAC0_P1 / OPAMP_P1
TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3
US1_RX #2 I2C0_SDA #1
LES_ALTEX0 #0 ACMP0_O #2 ETM_TD0 #0
ADC0_CH7 / DAC0_N1 / OPAMP_N1
TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3
US1_TX #2 I2C0_SCL #1
CMU_CLK0 #2 LES_ALTEX1 #0
ACMP1_O #2 ETM_TCLK #0
BU_VIN
CMU_CLK1 #1
ACMP0_CH6
LEU1_TX #0 I2C0_SDA #2
LES_CH6 #0 ETM_TCLK #2
ACMP0_CH7
LEU1_RX #0 I2C0_SCL LES_CH7 #0 ETM_TD0
#2
#2
Power supply for on-chip voltage regulator.
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin.
ACMP1_CH0
TIM2_CC0 #2
US0_CS #2
LES_CH8 #0
ACMP1_CH1
TIM2_CC1 #2
US0_CLK #2
LES_CH9 #0 GPIO_EM4WU2
ACMP1_CH2
TIM2_CC2 #2
US0_RX #2
LES_CH10 #0
ACMP1_CH3
US0_TX #2
LES_CH11 #0
Input to internal 3.3V USB regulator
Output and decoupling for internal 3.3V USB regulator
USB_DM
USB_DP
TIM0_CC0 #5 LETIM0_OUT0 #2
US1_CLK #2 LEU0_TX #3 I2C0_SDA #5
DBG_SWCLK #0/1/2/3
TIM0_CC1 #5 LETIM0_OUT1 #2
US1_CS #2 LEU0_RX DBG_SWDIO #0/1/2/3
#3 I2C0_SCL #5
GPIO_EM4WU3
silabs.com | Building a more connected world.
Rev. 2.30 | 195
QFN64 Pin# and Name
Pin #
Pin Name
Analog
Pin Alternate Functionality / Description
Timers
Communication
51
PF2
TIM0_CC2 #5
LEU0_TX #4
52
USB_VBUS USB 5.0 V VBUS input.
53
PF12
USB_ID
54
PF5
TIM0_CDTI2 #2/5
USB_VBUSEN #0
55
IOVDD_5
Digital IO power supply 5.
56
PE8
PCNT2_S0IN #1
57
PE9
PCNT2_S1IN #1
58
PE10
TIM1_CC0 #1
US0_TX #0
59
PE11
TIM1_CC1 #1
US0_RX #0
60
PE12
TIM1_CC2 #1
US0_RX #3 US0_CLK #0 I2C0_SDA #6
61
PE13
US0_TX #3 US0_CS #0 I2C0_SCL #6
62
PE14
63
PE15
64
PA15
TIM3_CC0 #0 TIM3_CC1 #0 TIM3_CC2 #0
LEU0_TX #2 LEU0_RX #2
EFM32LG Data Sheet
Pin Definitions
Other ACMP1_O #0 DBG_SWO #0 GPIO_EM4WU4
PRS_CH2 #1
PRS_CH3 #1
BOOT_TX LES_ALTEX5 #0
BOOT_RX CMU_CLK1 #2 LES_ALTEX6 #0 LES_ALTEX7 #0 ACMP0_O #0 GPIO_EM4WU5
silabs.com | Building a more connected world.
Rev. 2.30 | 196
EFM32LG Data Sheet
Pin Definitions
5.6.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0.
Alternate Functionality ACMP0_CH0 ACMP0_CH1 ACMP0_CH2 ACMP0_CH3 ACMP0_CH4 ACMP0_CH5 ACMP0_CH6 ACMP0_CH7 ACMP0_O ACMP1_CH0 ACMP1_CH1 ACMP1_CH2 ACMP1_CH3 ACMP1_O
ADC0_CH0
0 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PE13 PC8 PC9 PC10 PC11 PF2
PD0
ADC0_CH1
PD1
ADC0_CH2
PD2
ADC0_CH3
PD3
ADC0_CH4
PD4
ADC0_CH5
PD5
ADC0_CH6
PD6
ADC0_CH7
BOOT_RX BOOT_TX BU_VIN
PD7
PE11 PE10 PD8
Table 5.17. Alternate Functionality Overview
LOCATION
1
2
3
4
5
6
Description
Analog comparator ACMP0, channel 0.
Analog comparator ACMP0, channel 1.
Analog comparator ACMP0, channel 2.
Analog comparator ACMP0, channel 3.
Analog comparator ACMP0, channel 4.
Analog comparator ACMP0, channel 5.
Analog comparator ACMP0, channel 6.
Analog comparator ACMP0, channel 7.
PD6
Analog comparator ACMP0, digital output.
Analog comparator ACMP1, channel 0.
Analog comparator ACMP1, channel 1.
Analog comparator ACMP1, channel 2.
Analog comparator ACMP1, channel 3.
PD7
Analog comparator ACMP1, digital output.
Analog to digital converter ADC0, input channel number 0.
Analog to digital converter ADC0, input channel number 1.
Analog to digital converter ADC0, input channel number 2.
Analog to digital converter ADC0, input channel number 3.
Analog to digital converter ADC0, input channel number 4.
Analog to digital converter ADC0, input channel number 5.
Analog to digital converter ADC0, input channel number 6.
Analog to digital converter ADC0, input channel number 7.
Bootloader RX.
Bootloader TX.
Battery input for Backup Power Domain
silabs.com | Building a more connected world.
Rev. 2.30 | 197
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
CMU_CLK0
PA2
PD7
Clock Management Unit, clock output number 0.
CMU_CLK1
PA1 PD8 PE12
Clock Management Unit, clock output number 1.
DAC0_OUT0 / OPAMP_OUT0
PB11
Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0.
DAC0_OUT0ALT / OPAMP_OUT0A PC0 PC1 PC2 PC3 PD0 LT
Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0.
DAC0_OUT1 / OPAMP_OUT1
PB12
Digital to Analog Converter DAC0_OUT1 /OPAMP output channel number 1.
DAC0_OUT1ALT / OPAMP_OUT1A LT
PD1
Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1.
DBG_SWCLK PF0 PF0 PF0 PF0
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, and has a built-in pull down.
DBG_SWDIO PF1 PF1 PF1 PF1
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and has a built-in pull up.
DBG_SWO
PF2
PD1 PD2
Debug-interface Serial Wire viewer Output.
Note that this function is not enabled after reset, and must be enabled by software to be used.
ETM_TCLK
PD7
PC6 PA6
Embedded Trace Module ETM clock .
ETM_TD0
PD6
PC7 PA2
Embedded Trace Module ETM data 0.
ETM_TD1
PD3
PD3 PA3
Embedded Trace Module ETM data 1.
ETM_TD2
PD4
PD4 PA4
Embedded Trace Module ETM data 2.
ETM_TD3
PD5
PD5 PA5
Embedded Trace Module ETM data 3.
GPIO_EM4WU0 PA0
Pin can be used to wake the system up from EM4
GPIO_EM4WU1 PA6
Pin can be used to wake the system up from EM4
GPIO_EM4WU2 PC9
Pin can be used to wake the system up from EM4
GPIO_EM4WU3 PF1
Pin can be used to wake the system up from EM4
GPIO_EM4WU4 PF2
Pin can be used to wake the system up from EM4
GPIO_EM4WU5 PE13
Pin can be used to wake the system up from EM4
HFXTAL_N
PB14
High Frequency Crystal negative pin. Also used as external optional clock input pin.
HFXTAL_P
PB13
High Frequency Crystal positive pin.
I2C0_SCL
PA1 PD7 PC7
PC1 PF1 PE13 I2C0 Serial Clock Line input / output.
I2C0_SDA
PA0 PD6 PC6
PC0 PF0 PE12 I2C0 Serial Data input / output.
I2C1_SCL
PC5 PB12
I2C1 Serial Clock Line input / output.
I2C1_SDA
PC4 PB11
I2C1 Serial Data input / output.
LES_ALTEX0 PD6
LESENSE alternate exite output 0.
silabs.com | Building a more connected world.
Rev. 2.30 | 198
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
LES_ALTEX1 PD7
LESENSE alternate exite output 1.
LES_ALTEX2 PA3
LESENSE alternate exite output 2.
LES_ALTEX3 PA4
LESENSE alternate exite output 3.
LES_ALTEX4 PA5
LESENSE alternate exite output 4.
LES_ALTEX5 PE11
LESENSE alternate exite output 5.
LES_ALTEX6 PE12
LESENSE alternate exite output 6.
LES_ALTEX7 PE13
LESENSE alternate exite output 7.
LES_CH0
PC0
LESENSE channel 0.
LES_CH1
PC1
LESENSE channel 1.
LES_CH2
PC2
LESENSE channel 2.
LES_CH3
PC3
LESENSE channel 3.
LES_CH4
PC4
LESENSE channel 4.
LES_CH5
PC5
LESENSE channel 5.
LES_CH6
PC6
LESENSE channel 6.
LES_CH7
PC7
LESENSE channel 7.
LES_CH8
PC8
LESENSE channel 8.
LES_CH9
PC9
LESENSE channel 9.
LES_CH10
PC10
LESENSE channel 10.
LES_CH11
PC11
LESENSE channel 11.
LETIM0_OUT0 PD6 PB11 PF0 PC4
Low Energy Timer LETIM0, output channel 0.
LETIM0_OUT1 PD7 PB12 PF1 PC5
Low Energy Timer LETIM0, output channel 1.
LEU0_RX
PD5 PB14 PE15 PF1 PA0
LEUART0 Receive input.
LEU0_TX
PD4 PB13 PE14 PF0 PF2
LEUART0 Transmit output. Also used as receive input in half duplex communication.
LEU1_RX
PC7 PA6
LEUART1 Receive input.
LEU1_TX
PC6 PA5
LEUART1 Transmit output. Also used as receive input in half duplex communication.
LFXTAL_N
PB8
Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin.
LFXTAL_P
PB7
Low Frequency Crystal (typically 32.768 kHz) positive pin.
OPAMP_N0 / DAC0_N0
PC5
Operational Amplifier 0 external negative input.
OPAMP_N1 / DAC0_N1
PD7
Operational Amplifier 1 external negative input.
OPAMP_N2
PD3
Operational Amplifier 2 external negative input.
OPAMP_OUT2 PD5 PD0
Operational Amplifier 2 output.
silabs.com | Building a more connected world.
Rev. 2.30 | 199
Alternate
LOCATION
Functionality
0
1
2
3
4
5
OPAMP_P0 / DAC0_P0
PC4
OPAMP_P1 / DAC0_P1
PD6
OPAMP_P2
PD4
PCNT0_S0IN
PC0 PD6
PCNT0_S1IN
PC1 PD7
PCNT1_S0IN PC4
PCNT1_S1IN PC5
PCNT2_S0IN PD0 PE8
PCNT2_S1IN PD1 PE9
PRS_CH0
PA0
PRS_CH1
PA1
PRS_CH2
PC0 PF5
PRS_CH3
PC1 PE8
TIM0_CC0
PA0 PA0
PD1 PA0 PF0
TIM0_CC1
PA1 PA1
PD2 PC0 PF1
TIM0_CC2
PA2 PA2
PD3 PC1 PF2
TIM0_CDTI0
PA3
PC2
TIM0_CDTI1
PA4
PC3
TIM0_CDTI2
TIM1_CC0 TIM1_CC1 TIM1_CC2 TIM2_CC0 TIM2_CC1 TIM2_CC2 TIM3_CC0 TIM3_CC1 TIM3_CC2 US0_CLK US0_CS
PA5
PF5
PC4 PF5
PA8 PA9 PA10 PE14 PE15 PA15 PE12 PE13
PE10 PE11 PE12
PC8 PC9 PC10
PC9 PC8
PB7 PB8 PB11
PD6 PD7
PB13 PB14
PB13 PB14
US0_RX
PE11
PC10 PE12 PB8 PC1
EFM32LG Data Sheet
Pin Definitions
6
Description
Operational Amplifier 0 external positive input.
Operational Amplifier 1 external positive input.
Operational Amplifier 2 external positive input. Pulse Counter PCNT0 input number 0. Pulse Counter PCNT0 input number 1. Pulse Counter PCNT1 input number 0. Pulse Counter PCNT1 input number 1. Pulse Counter PCNT2 input number 0. Pulse Counter PCNT2 input number 1. Peripheral Reflex System PRS, channel 0. Peripheral Reflex System PRS, channel 1. Peripheral Reflex System PRS, channel 2. Peripheral Reflex System PRS, channel 3. Timer 0 Capture Compare input / output channel 0. Timer 0 Capture Compare input / output channel 1. Timer 0 Capture Compare input / output channel 2. Timer 0 Complimentary Deat Time Insertion channel 0. Timer 0 Complimentary Deat Time Insertion channel 1. Timer 0 Complimentary Deat Time Insertion channel 2. Timer 1 Capture Compare input / output channel 0. Timer 1 Capture Compare input / output channel 1. Timer 1 Capture Compare input / output channel 2. Timer 2 Capture Compare input / output channel 0. Timer 2 Capture Compare input / output channel 1. Timer 2 Capture Compare input / output channel 2. Timer 3 Capture Compare input / output channel 0. Timer 3 Capture Compare input / output channel 1. Timer 3 Capture Compare input / output channel 2. USART0 clock input / output. USART0 chip select input / output. USART0 Asynchronous Receive. USART0 Synchronous mode Master Input / Slave Output (MISO).
silabs.com | Building a more connected world.
Rev. 2.30 | 200
Alternate
LOCATION
Functionality
0
1
2
3
4
5
US0_TX
PE10
PC11 PE13 PB7 PC0
US1_CLK US1_CS
US1_RX
PB7 PD2 PF0 PB8 PD3 PF1
PC1 PD1 PD6
US1_TX
US2_CLK US2_CS US2_RX
PC0 PD0 PD7
PC4 PC5 PC3
US2_TX
PC2
USB_DM USB_DMPU USB_DP USB_ID USB_VBUS USB_VBUSEN USB_VREGI
USB_VREGO
PF10
PD2
PF11
PF12
USB_V BUS
PF5
USB_V REGI
USB_V REGO
EFM32LG Data Sheet
Pin Definitions
6
Description
USART0 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input (MOSI).
USART1 clock input / output.
USART1 chip select input / output.
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output (MISO).
USART1 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input (MOSI).
USART2 clock input / output.
USART2 chip select input / output.
USART2 Asynchronous Receive.
USART2 Synchronous mode Master Input / Slave Output (MISO).
USART2 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART2 Synchronous mode Master Output / Slave Input (MOSI).
USB D- pin.
USB D- Pullup control.
USB D+ pin.
USB ID pin. Used in OTG mode.
USB 5 V VBUS input.
USB 5 V VBUS enable.
USB Input to internal 3.3 V regulator
USB Decoupling for internal 3.3 V USB regulator and regulator output
silabs.com | Building a more connected world.
Rev. 2.30 | 201
EFM32LG Data Sheet
Pin Definitions
5.6.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG330 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.18. GPIO Pinout
Port
Port A Port B Port C Port D Port E Port F
Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 15 14 13 12 11 10 PA15 -- -- -- -- PA10 PA9 PA8 -- PA6 PA5 PA4 PA3 PA2 PA1 PA0 -- PB14 PB13 PB12 PB11 -- -- PB8 PB7 -- -- -- -- -- -- -- -- -- -- -- PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 -- -- -- -- -- -- -- PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 -- -- -- -- -- -- -- -- -- -- -- PF12 PF11 PF10 -- -- -- -- PF5 -- -- PF2 PF1 PF0
5.6.4 Opamp Pinout Overview
The specific opamp terminals available in EFM32LG330 is shown in the following figure.
PC4
+ OUT0ALT
OPA0 OUT0
PC5
-
PD4
+
PD3
OPA2 -
OUT2
PD6
+ OUT1ALT
PD7
OPA1 -
OUT1
PB11 PB12 PC0 PC1 PC2 PC3 PC12 PC13 PC14 PC15 PD0 PD1 PD5
Figure 5.12. Opamp Pinout
silabs.com | Building a more connected world.
Rev. 2.30 | 202
5.7 EFM32LG332 (TQFP64)
EFM32LG Data Sheet
Pin Definitions
5.7.1 Pinout
The EFM32LG332 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question.
Figure 5.13. EFM32LG332 Pinout (top view, not to scale) Table 5.19. Device Pinout
QFP64 Pin# and Name
Pin #
Pin Name
1
PA0
2
PA1
3
PA2
Analog
Pin Alternate Functionality / Description
Timers
Communication
TIM0_CC0 #0/1/4
LEU0_RX #4 I2C0_SDA #0
TIM0_CC1 #0/1
I2C0_SCL #0
TIM0_CC2 #0/1
Other
PRS_CH0 #0 GPIO_EM4WU0
CMU_CLK1 #0 PRS_CH1 #0
CMU_CLK0 #0 ETM_TD0 #3
silabs.com | Building a more connected world.
Rev. 2.30 | 203
EFM32LG Data Sheet
Pin Definitions
QFP64 Pin# and Name
Pin #
Pin Name
4
PA3
5
PA4
6
PA5
7
IOVDD_0
8
VSS
9
PC0
10
PC1
11
PC2
12
PC3
13
PC4
14
PC5
15
PB7
16
PB8
17
PA8
18
PA9
19
PA10
20
RESETn
21
PB11
22
VSS
23
AVDD_1
24
PB13
25
PB14
26
IOVDD_3
27
AVDD_0
Pin Alternate Functionality / Description
Analog
Timers
Communication
Other
TIM0_CDTI0 #0
LES_ALTEX2 #0 ETM_TD1 #3
TIM0_CDTI1 #0
LES_ALTEX3 #0 ETM_TD2 #3
TIM0_CDTI2 #0
LEU1_TX #1
LES_ALTEX4 #0 ETM_TD3 #3
Digital IO power supply 0.
Ground.
ACMP0_CH0 DAC0_OUT0ALT #0/ OPAMP_OUT0ALT
TIM0_CC1 #4 PCNT0_S0IN #2
US0_TX #5 US1_TX #0 LES_CH0 #0 PRS_CH2
I2C0_SDA #4
#0
ACMP0_CH1 DAC0_OUT0ALT #1/ OPAMP_OUT0ALT
TIM0_CC2 #4 PCNT0_S1IN #2
US0_RX #5 US1_RX #0 LES_CH1 #0 PRS_CH3
I2C0_SCL #4
#0
ACMP0_CH2 DAC0_OUT0ALT #2/ OPAMP_OUT0ALT
TIM0_CDTI0 #4
US2_TX #0
LES_CH2 #0
ACMP0_CH3 DAC0_OUT0ALT #3/ OPAMP_OUT0ALT
TIM0_CDTI1 #4
US2_RX #0
LES_CH3 #0
ACMP0_CH4 / DAC0_P0 / OPAMP_P0
TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0
US2_CLK #0 I2C1_SDA #0
LES_CH4 #0
ACMP0_CH5 / DAC0_N0 / OPAMP_N0
LETIM0_OUT1 #3 PCNT1_S1IN #0
US2_CS #0 I2C1_SCL #0
LES_CH5 #0
LFXTAL_P
TIM1_CC0 #3
US0_TX #4 US1_CLK #0
LFXTAL_N
TIM1_CC1 #3
US0_RX #4 US1_CS #0
TIM2_CC0 #0
TIM2_CC1 #0
TIM2_CC2 #0
Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released.
DAC0_OUT0 / OPAMP_OUT0
TIM1_CC2 #3 LETIM0_OUT0 #1
I2C1_SDA #1
Ground.
Analog power supply 1.
HFXTAL_P
US0_CLK #4/5 LEU0_TX #1
HFXTAL_N
US0_CS #4/5 LEU0_RX #1
Digital IO power supply 3.
Analog power supply 0.
silabs.com | Building a more connected world.
Rev. 2.30 | 204
EFM32LG Data Sheet
Pin Definitions
QFP64 Pin# and Name
Pin #
Pin Name
28
PD0
29
PD1
30
PD2
31
PD3
32
PD4
33
PD5
34
PD6
35
PD7
36
PD8
37
PC6
38
PC7
39
VDD_DREG
40
DECOUPLE
41
PC8
42
PC9
43
PC10
44
PC11
45
USB_VREGI
46
USB_VREGO
47
PF10
48
PF11
49
PF0
50
PF1
51
PF2
Pin Alternate Functionality / Description
Analog
Timers
Communication
Other
ADC0_CH0 DAC0_OUT0ALT #4/ OPAMP_OUT0ALT
OPAMP_OUT2 #1
PCNT2_S0IN #0
US1_TX #1
ADC0_CH1 DAC0_OUT1ALT #4/ OPAMP_OUT1ALT
TIM0_CC0 #3 PCNT2_S1IN #0
US1_RX #1
DBG_SWO #2
ADC0_CH2
TIM0_CC1 #3
USB_DMPU #0 US1_CLK #1
DBG_SWO #3
ADC0_CH3 OPAMP_N2
TIM0_CC2 #3
US1_CS #1
ETM_TD1 #0/2
ADC0_CH4 OPAMP_P2
LEU0_TX #0
ETM_TD2 #0/2
ADC0_CH5 OPAMP_OUT2 #0
LEU0_RX #0
ETM_TD3 #0/2
ADC0_CH6 / DAC0_P1 / OPAMP_P1
TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3
US1_RX #2 I2C0_SDA #1
LES_ALTEX0 #0 ACMP0_O #2 ETM_TD0 #0
ADC0_CH7 / DAC0_N1 / OPAMP_N1
TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3
US1_TX #2 I2C0_SCL #1
CMU_CLK0 #2 LES_ALTEX1 #0
ACMP1_O #2 ETM_TCLK #0
BU_VIN
CMU_CLK1 #1
ACMP0_CH6
LEU1_TX #0 I2C0_SDA #2
LES_CH6 #0 ETM_TCLK #2
ACMP0_CH7
LEU1_RX #0 I2C0_SCL LES_CH7 #0 ETM_TD0
#2
#2
Power supply for on-chip voltage regulator.
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin.
ACMP1_CH0
TIM2_CC0 #2
US0_CS #2
LES_CH8 #0
ACMP1_CH1
TIM2_CC1 #2
US0_CLK #2
LES_CH9 #0 GPIO_EM4WU2
ACMP1_CH2
TIM2_CC2 #2
US0_RX #2
LES_CH10 #0
ACMP1_CH3
US0_TX #2
LES_CH11 #0
Input to internal 3.3V USB regulator
Output and decoupling for internal 3.3V USB regulator
USB_DM
USB_DP
TIM0_CC0 #5 LETIM0_OUT0 #2
US1_CLK #2 LEU0_TX #3 I2C0_SDA #5
DBG_SWCLK #0/1/2/3
TIM0_CC1 #5 LETIM0_OUT1 #2
US1_CS #2 LEU0_RX DBG_SWDIO #0/1/2/3
#3 I2C0_SCL #5
GPIO_EM4WU3
TIM0_CC2 #5
LEU0_TX #4
ACMP1_O #0 DBG_SWO #0 GPIO_EM4WU4
silabs.com | Building a more connected world.
Rev. 2.30 | 205
QFP64 Pin# and Name
Pin #
Pin Name
52
USB_VBUS
53
PF12
54
PF5
55
IOVDD_5
56
VSS
57
PE8
58
PE9
59
PE10
Analog USB 5.0 V VBUS input.
Digital IO power supply 5. Ground.
Pin Alternate Functionality / Description
Timers
Communication
TIM0_CDTI2 #2/5
USB_ID USB_VBUSEN #0
PCNT2_S0IN #1 PCNT2_S1IN #1
TIM1_CC0 #1
US0_TX #0
60
PE11
TIM1_CC1 #1
US0_RX #0
61
PE12
TIM1_CC2 #1
US0_RX #3 US0_CLK #0 I2C0_SDA #6
62
PE13
US0_TX #3 US0_CS #0 I2C0_SCL #6
63
PE14
64
PE15
TIM3_CC0 #0 TIM3_CC1 #0
LEU0_TX #2 LEU0_RX #2
EFM32LG Data Sheet
Pin Definitions
Other
PRS_CH2 #1
PRS_CH3 #1
BOOT_TX LES_ALTEX5 #0
BOOT_RX CMU_CLK1 #2 LES_ALTEX6 #0 LES_ALTEX7 #0 ACMP0_O #0 GPIO_EM4WU5
silabs.com | Building a more connected world.
Rev. 2.30 | 206
EFM32LG Data Sheet
Pin Definitions
5.7.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0.
Alternate Functionality ACMP0_CH0 ACMP0_CH1 ACMP0_CH2 ACMP0_CH3 ACMP0_CH4 ACMP0_CH5 ACMP0_CH6 ACMP0_CH7 ACMP0_O ACMP1_CH0 ACMP1_CH1 ACMP1_CH2 ACMP1_CH3 ACMP1_O
ADC0_CH0
0 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PE13 PC8 PC9 PC10 PC11 PF2
PD0
ADC0_CH1
PD1
ADC0_CH2
PD2
ADC0_CH3
PD3
ADC0_CH4
PD4
ADC0_CH5
PD5
ADC0_CH6
PD6
ADC0_CH7
BOOT_RX BOOT_TX BU_VIN
PD7
PE11 PE10 PD8
Table 5.20. Alternate Functionality Overview
LOCATION
1
2
3
4
5
6
Description
Analog comparator ACMP0, channel 0.
Analog comparator ACMP0, channel 1.
Analog comparator ACMP0, channel 2.
Analog comparator ACMP0, channel 3.
Analog comparator ACMP0, channel 4.
Analog comparator ACMP0, channel 5.
Analog comparator ACMP0, channel 6.
Analog comparator ACMP0, channel 7.
PD6
Analog comparator ACMP0, digital output.
Analog comparator ACMP1, channel 0.
Analog comparator ACMP1, channel 1.
Analog comparator ACMP1, channel 2.
Analog comparator ACMP1, channel 3.
PD7
Analog comparator ACMP1, digital output.
Analog to digital converter ADC0, input channel number 0.
Analog to digital converter ADC0, input channel number 1.
Analog to digital converter ADC0, input channel number 2.
Analog to digital converter ADC0, input channel number 3.
Analog to digital converter ADC0, input channel number 4.
Analog to digital converter ADC0, input channel number 5.
Analog to digital converter ADC0, input channel number 6.
Analog to digital converter ADC0, input channel number 7.
Bootloader RX.
Bootloader TX.
Battery input for Backup Power Domain
silabs.com | Building a more connected world.
Rev. 2.30 | 207
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
CMU_CLK0
PA2
PD7
Clock Management Unit, clock output number 0.
CMU_CLK1
PA1 PD8 PE12
Clock Management Unit, clock output number 1.
DAC0_OUT0 / OPAMP_OUT0
PB11
Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0.
DAC0_OUT0ALT / OPAMP_OUT0A PC0 PC1 PC2 PC3 PD0 LT
Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0.
DAC0_OUT1ALT / OPAMP_OUT1A LT
PD1
Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1.
DBG_SWCLK PF0 PF0 PF0 PF0
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, and has a built-in pull down.
DBG_SWDIO PF1 PF1 PF1 PF1
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and has a built-in pull up.
DBG_SWO
PF2
PD1 PD2
Debug-interface Serial Wire viewer Output.
Note that this function is not enabled after reset, and must be enabled by software to be used.
ETM_TCLK
PD7
PC6
Embedded Trace Module ETM clock .
ETM_TD0
PD6
PC7 PA2
Embedded Trace Module ETM data 0.
ETM_TD1
PD3
PD3 PA3
Embedded Trace Module ETM data 1.
ETM_TD2
PD4
PD4 PA4
Embedded Trace Module ETM data 2.
ETM_TD3
PD5
PD5 PA5
Embedded Trace Module ETM data 3.
GPIO_EM4WU0 PA0
Pin can be used to wake the system up from EM4
GPIO_EM4WU2 PC9
Pin can be used to wake the system up from EM4
GPIO_EM4WU3 PF1
Pin can be used to wake the system up from EM4
GPIO_EM4WU4 PF2
Pin can be used to wake the system up from EM4
GPIO_EM4WU5 PE13
Pin can be used to wake the system up from EM4
HFXTAL_N
PB14
High Frequency Crystal negative pin. Also used as external optional clock input pin.
HFXTAL_P
PB13
High Frequency Crystal positive pin.
I2C0_SCL
PA1 PD7 PC7
PC1 PF1 PE13 I2C0 Serial Clock Line input / output.
I2C0_SDA
PA0 PD6 PC6
PC0 PF0 PE12 I2C0 Serial Data input / output.
I2C1_SCL
PC5
I2C1 Serial Clock Line input / output.
I2C1_SDA
PC4
I2C1 Serial Data input / output.
LES_ALTEX0 PD6
LESENSE alternate exite output 0.
LES_ALTEX1 PD7
LESENSE alternate exite output 1.
LES_ALTEX2 PA3
LESENSE alternate exite output 2.
LES_ALTEX3 PA4
LESENSE alternate exite output 3.
silabs.com | Building a more connected world.
Rev. 2.30 | 208
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
LES_ALTEX4 PA5
LESENSE alternate exite output 4.
LES_ALTEX5 PE11
LESENSE alternate exite output 5.
LES_ALTEX6 PE12
LESENSE alternate exite output 6.
LES_ALTEX7 PE13
LESENSE alternate exite output 7.
LES_CH0
PC0
LESENSE channel 0.
LES_CH1
PC1
LESENSE channel 1.
LES_CH2
PC2
LESENSE channel 2.
LES_CH3
PC3
LESENSE channel 3.
LES_CH4
PC4
LESENSE channel 4.
LES_CH5
PC5
LESENSE channel 5.
LES_CH6
PC6
LESENSE channel 6.
LES_CH7
PC7
LESENSE channel 7.
LES_CH8
PC8
LESENSE channel 8.
LES_CH9
PC9
LESENSE channel 9.
LES_CH10
PC10
LESENSE channel 10.
LES_CH11
PC11
LESENSE channel 11.
LETIM0_OUT0 PD6 PB11 PF0 PC4
Low Energy Timer LETIM0, output channel 0.
LETIM0_OUT1 PD7
PF1 PC5
Low Energy Timer LETIM0, output channel 1.
LEU0_RX
PD5 PB14 PE15 PF1 PA0
LEUART0 Receive input.
LEU0_TX
PD4 PB13 PE14 PF0 PF2
LEUART0 Transmit output. Also used as receive input in half duplex communication.
LEU1_RX
PC7
LEUART1 Receive input.
LEU1_TX
PC6 PA5
LEUART1 Transmit output. Also used as receive input in half duplex communication.
LFXTAL_N
PB8
Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin.
LFXTAL_P
PB7
Low Frequency Crystal (typically 32.768 kHz) positive pin.
OPAMP_N0 / DAC0_N0
PC5
Operational Amplifier 0 external negative input.
OPAMP_N1 / DAC0_N1
PD7
Operational Amplifier 1 external negative input.
OPAMP_N2
PD3
Operational Amplifier 2 external negative input.
OPAMP_P0 / DAC0_P0
PC4
Operational Amplifier 0 external positive input.
OPAMP_P1 / DAC0_P1
PD6
Operational Amplifier 1 external positive input.
OPAMP_P2
PD4
Operational Amplifier 2 external positive input.
OPAMP_OUT2 PD5 PD0
Operational Amplifier 2 output.
silabs.com | Building a more connected world.
Rev. 2.30 | 209
Alternate
LOCATION
Functionality
0
1
2
3
4
5
PCNT0_S0IN
PC0 PD6
PCNT0_S1IN
PC1 PD7
PCNT1_S0IN PC4
PCNT1_S1IN PC5
PCNT2_S0IN PD0 PE8
PCNT2_S1IN PD1 PE9
PRS_CH0
PA0
PRS_CH1
PA1
PRS_CH2
PC0 PF5
PRS_CH3
PC1 PE8
TIM0_CC0
PA0 PA0
PD1 PA0 PF0
TIM0_CC1
PA1 PA1
PD2 PC0 PF1
TIM0_CC2
PA2 PA2
PD3 PC1 PF2
TIM0_CDTI0
PA3
PC2
TIM0_CDTI1
PA4
PC3
TIM0_CDTI2
TIM1_CC0 TIM1_CC1 TIM1_CC2 TIM2_CC0 TIM2_CC1 TIM2_CC2 TIM3_CC0 TIM3_CC1 US0_CLK US0_CS
PA5
PF5
PC4 PF5
PA8 PA9 PA10 PE14 PE15 PE12 PE13
PE10 PE11 PE12
PC8 PC9 PC10
PC9 PC8
PB7 PB8 PB11
PD6 PD7
PB13 PB14
PB13 PB14
US0_RX
PE11
PC10 PE12 PB8 PC1
US0_TX
US1_CLK US1_CS
PE10
PC11 PE13 PB7 PC0
PB7 PD2 PF0 PB8 PD3 PF1
EFM32LG Data Sheet
Pin Definitions
6
Description
Pulse Counter PCNT0 input number 0.
Pulse Counter PCNT0 input number 1.
Pulse Counter PCNT1 input number 0.
Pulse Counter PCNT1 input number 1.
Pulse Counter PCNT2 input number 0.
Pulse Counter PCNT2 input number 1.
Peripheral Reflex System PRS, channel 0.
Peripheral Reflex System PRS, channel 1.
Peripheral Reflex System PRS, channel 2.
Peripheral Reflex System PRS, channel 3.
Timer 0 Capture Compare input / output channel 0.
Timer 0 Capture Compare input / output channel 1.
Timer 0 Capture Compare input / output channel 2.
Timer 0 Complimentary Deat Time Insertion channel 0.
Timer 0 Complimentary Deat Time Insertion channel 1.
Timer 0 Complimentary Deat Time Insertion channel 2.
Timer 1 Capture Compare input / output channel 0.
Timer 1 Capture Compare input / output channel 1.
Timer 1 Capture Compare input / output channel 2.
Timer 2 Capture Compare input / output channel 0.
Timer 2 Capture Compare input / output channel 1.
Timer 2 Capture Compare input / output channel 2.
Timer 3 Capture Compare input / output channel 0.
Timer 3 Capture Compare input / output channel 1.
USART0 clock input / output.
USART0 chip select input / output.
USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output (MISO).
USART0 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input (MOSI).
USART1 clock input / output.
USART1 chip select input / output.
silabs.com | Building a more connected world.
Rev. 2.30 | 210
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
US1_RX
PC1 PD1 PD6
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output (MISO).
US1_TX
PC0 PD0 PD7
USART1 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input (MOSI).
US2_CLK
PC4
USART2 clock input / output.
US2_CS
PC5
USART2 chip select input / output.
US2_RX
PC3
USART2 Asynchronous Receive.
USART2 Synchronous mode Master Input / Slave Output (MISO).
US2_TX
PC2
USART2 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART2 Synchronous mode Master Output / Slave Input (MOSI).
USB_DM
PF10
USB D- pin.
USB_DMPU
PD2
USB D- Pullup control.
USB_DP
PF11
USB D+ pin.
USB_ID
PF12
USB ID pin. Used in OTG mode.
USB_VBUS
USB_V BUS
USB 5 V VBUS input.
USB_VBUSEN PF5
USB 5 V VBUS enable.
USB_VREGI
USB_V REGI
USB Input to internal 3.3 V regulator
USB_VREGO
USB_V REGO
USB Decoupling for internal 3.3 V USB regulator and regulator output
5.7.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG332 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.21. GPIO Pinout
Port
Port A Port B Port C Port D Port E Port F
Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 15 14 13 12 11 10
-
-
-
-
- PA10 PA9 PA8 -
- PA5 PA4 PA3 PA2 PA1 PA0
- PB14 PB13 - PB11 -
- PB8 PB7 -
-
-
-
-
-
-
-
-
-
- PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
-
-
-
-
-
-
- PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 -
-
-
-
-
-
-
-
-
-
- PF12 PF11 PF10 -
-
-
- PF5 -
- PF2 PF1 PF0
silabs.com | Building a more connected world.
Rev. 2.30 | 211
5.7.4 Opamp Pinout Overview
The specific opamp terminals available in EFM32LG332 is shown in the following figure.
PC4
+ OUT0ALT
PC5
OPA0 -
OUT0
PD4
+
PD3
OPA2 -
OUT2
PD6
+ OUT1ALT
PD7
OPA1 -
OUT1
PB11 PB12 PC0 PC1 PC2 PC3 PC12 PC13 PC14 PC15 PD0 PD1 PD5
Figure 5.14. Opamp Pinout
EFM32LG Data Sheet
Pin Definitions
silabs.com | Building a more connected world.
Rev. 2.30 | 212
5.8 EFM32LG360 (CSP81)
EFM32LG Data Sheet
Pin Definitions
5.8.1 Pinout
The EFM32LG360 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question.
CSP81 Pin# and Name
Pin #
Pin Name
A1
PF10
A2
PF11
A3
PF2
Figure 5.15. EFM32LG360 Pinout (top view, not to scale) Table 5.22. Device Pinout
Analog
Pin Alternate Functionality / Description
Timers
Communication
U1_TX #1 USB_DM
U1_RX #1 USB_DP
TIM0_CC2 #5
LEU0_TX #4
Other
ACMP1_O #0 DBG_SWO #0 GPIO_EM4WU4
silabs.com | Building a more connected world.
Rev. 2.30 | 213
EFM32LG Data Sheet
Pin Definitions
CSP81 Pin# and Name
Pin #
Pin Name
A4
VSS
A5
IOVDD_5
A6
PE9
A7
PE11
A8
PE12
A9
PA15
B1
USB_VREGI
B2
USB_VBUS
B3
PC15
B4
PF1
B5
PF5
B6
PE8
B7
PE13
B8
PA0
B9
PA2
C1
USB_VREGO
C2
PC13
C3
PC14
C4
PF0
C5
PF12
C6
PE10
C7
PE14
C8
PA1
C9
PA3
D1
PC10
D2
PC11
Pin Alternate Functionality / Description
Analog
Timers
Communication
Other
Ground.
Digital IO power supply 5.
PCNT2_S1IN #1
TIM1_CC1 #1
US0_RX #0
LES_ALTEX5 #0 BOOT_RX
TIM1_CC2 #1
US0_RX #3 US0_CLK #0 I2C0_SDA #6
CMU_CLK1 #2 LES_ALTEX6 #0
TIM3_CC2 #0
Input to internal 3.3V USB regulator
USB 5.0 V VBUS input.
ACMP1_CH7 DAC0_OUT1ALT #3/ OPAMP_OUT1ALT
TIM0_CDTI2 #1/3 TIM1_CC2 #0
US0_CLK #3 U0_RX #3
LES_CH15 #0 DBG_SWO #1
TIM0_CC1 #5 LETIM0_OUT1 #2
US1_CS #2 LEU0_RX DBG_SWDIO #0/1/2/3
#3 I2C0_SCL #5
GPIO_EM4WU3
TIM0_CDTI2 #2/5
USB_VBUSEN #0
PRS_CH2 #1
PCNT2_S0IN #1
PRS_CH3 #1
US0_TX #3 US0_CS #0 I2C0_SCL #6
LES_ALTEX7 #0 ACMP0_O #0
GPIO_EM4WU5
TIM0_CC0 #0/1/4
LEU0_RX #4 I2C0_SDA #0
PRS_CH0 #0 GPIO_EM4WU0
TIM0_CC2 #0/1
CMU_CLK0 #0 ETM_TD0 #3
Output and decoupling for internal 3.3V USB regulator
ACMP1_CH5 DAC0_OUT1ALT #1/ OPAMP_OUT1ALT
TIM0_CDTI0 #1/3 TIM1_CC0 #0 TIM1_CC2 #4
PCNT0_S0IN #0
U1_RX #0
LES_CH13 #0
ACMP1_CH6 DAC0_OUT1ALT #2/ OPAMP_OUT1ALT
TIM0_CDTI1 #1/3 TIM1_CC1 #0
PCNT0_S1IN #0
US0_CS #3 U0_TX #3
LES_CH14 #0
TIM0_CC0 #5 LETIM0_OUT0 #2
US1_CLK #2 LEU0_TX #3 I2C0_SDA #5
DBG_SWCLK #0/1/2/3
USB_ID
TIM1_CC0 #1
US0_TX #0
BOOT_TX
TIM3_CC0 #0
LEU0_TX #2
TIM0_CC1 #0/1
I2C0_SCL #0
CMU_CLK1 #0 PRS_CH1 #0
TIM0_CDTI0 #0
U0_TX #2
LES_ALTEX2 #0 ETM_TD1 #3
ACMP1_CH2
TIM2_CC2 #2
US0_RX #2
LES_CH10 #0
ACMP1_CH3
US0_TX #2
LES_CH11 #0
silabs.com | Building a more connected world.
Rev. 2.30 | 214
EFM32LG Data Sheet
Pin Definitions
CSP81 Pin# and Name
Pin #
Pin Name
D3
PC12
D4
PC9
D5
PC8
D6
PA4
D7
PA5
D8
PA6
D9
IOVDD_0
E1
PE4
E2
PE5
E3
PE3
E4
PC7
E5
PE15
E6
PB5
E7
PB3
E8
PB4
E9
VSS
F1
DECOUPLE
F2
PE2
F3
PC6
F4
PD7
F5
PD0
F6
PA8
F7
PC2
F8
PC0
F9
PB6
Pin Alternate Functionality / Description
Analog
Timers
Communication
Other
ACMP1_CH4 DAC0_OUT1ALT #0/ OPAMP_OUT1ALT
U1_TX #0
CMU_CLK0 #1 LES_CH12 #0
ACMP1_CH1
TIM2_CC1 #2
US0_CLK #2
LES_CH9 #0 GPIO_EM4WU2
ACMP1_CH0
TIM2_CC0 #2
US0_CS #2
LES_CH8 #0
TIM0_CDTI1 #0
U0_RX #2
LES_ALTEX3 #0 ETM_TD2 #3
TIM0_CDTI2 #0
LEU1_TX #1
LES_ALTEX4 #0 ETM_TD3 #3
LEU1_RX #1
ETM_TCLK #3 GPIO_EM4WU1
Digital IO power supply 0.
US0_CS #1
US0_CLK #1
BU_STAT
U1_RX #3
ACMP1_O #1
ACMP0_CH7
LEU1_RX #0 I2C0_SCL LES_CH7 #0 ETM_TD0
#2
#2
TIM3_CC1 #0
LEU0_RX #2
US2_CLK #1
PCNT1_S0IN #1
US2_TX #1
PCNT1_S1IN #1
US2_RX #1
Ground.
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin.
BU_VOUT
TIM3_CC2 #1
U1_TX #3
ACMP0_O #1
ACMP0_CH6
LEU1_TX #0 I2C0_SDA #2
LES_CH6 #0 ETM_TCLK #2
ADC0_CH7 / DAC0_N1 / OPAMP_N1
TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3
US1_TX #2 I2C0_SCL #1
CMU_CLK0 #2 LES_ALTEX1 #0
ACMP1_O #2 ETM_TCLK #0
ADC0_CH0 DAC0_OUT0ALT #4/ OPAMP_OUT0ALT
OPAMP_OUT2 #1
PCNT2_S0IN #0
US1_TX #1
TIM2_CC0 #0
ACMP0_CH2 DAC0_OUT0ALT #2/ OPAMP_OUT0ALT
TIM0_CDTI0 #4
US2_TX #0
LES_CH2 #0
ACMP0_CH0 DAC0_OUT0ALT #0/ OPAMP_OUT0ALT
TIM0_CC1 #4 PCNT0_S0IN #2
US0_TX #5 US1_TX #0 LES_CH0 #0 PRS_CH2
I2C0_SDA #4
#0
US2_CS #1
silabs.com | Building a more connected world.
Rev. 2.30 | 215
EFM32LG Data Sheet
Pin Definitions
CSP81 Pin# and Name
Pin #
Pin Name
G1
VDD_DREG
G2
VSS_DREG
G3
PD4
G4
PD3
G5
PB12
G6
PB11
G7
PA9
G8
PC4
G9
PC1
H1
PD8
H2
PD6
H3
PD2
H4
VSS
H5
AVSS_0
H6
AVDD_0
H7
PA10
H8
PC5
H9
PC3
J1
PD5
J2
PD1
J3
IOVDD_3
J4
PB14
J5
PB13
J6
AVDD_1
J7
RESETn
Pin Alternate Functionality / Description
Analog
Timers
Communication
Other
Power supply for on-chip voltage regulator.
Ground for on-chip voltage regulator.
ADC0_CH4 OPAMP_P2
LEU0_TX #0
ETM_TD2 #0/2
ADC0_CH3 OPAMP_N2
TIM0_CC2 #3
US1_CS #1
ETM_TD1 #0/2
DAC0_OUT1 / OPAMP_OUT1
LETIM0_OUT1 #1
I2C1_SCL #1
DAC0_OUT0 / OPAMP_OUT0
TIM1_CC2 #3 LETIM0_OUT0 #1
I2C1_SDA #1
TIM2_CC1 #0
ACMP0_CH4 / DAC0_P0 / OPAMP_P0
TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0
US2_CLK #0 I2C1_SDA #0
LES_CH4 #0
ACMP0_CH1 DAC0_OUT0ALT #1/ OPAMP_OUT0ALT
TIM0_CC2 #4 PCNT0_S1IN #2
US0_RX #5 US1_RX #0 LES_CH1 #0 PRS_CH3
I2C0_SCL #4
#0
BU_VIN
CMU_CLK1 #1
ADC0_CH6 / DAC0_P1 / OPAMP_P1
TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3
US1_RX #2 I2C0_SDA #1
LES_ALTEX0 #0 ACMP0_O #2 ETM_TD0 #0
ADC0_CH2
TIM0_CC1 #3
USB_DMPU #0 US1_CLK #1
DBG_SWO #3
Ground.
Analog ground 0.
Analog power supply 0.
TIM2_CC2 #0
ACMP0_CH5 / DAC0_N0 /
PD6OPAMP_N0
LETIM0_OUT1 #3 PCNT1_S1IN #0
US2_CS #0 I2C1_SCL #0
LES_CH5 #0
ACMP0_CH3 DAC0_OUT0ALT #3/ OPAMP_OUT0ALT
TIM0_CDTI1 #4
US2_RX #0
LES_CH3 #0
ADC0_CH5 OPAMP_OUT2 #0
LEU0_RX #0
ETM_TD3 #0/2
ADC0_CH1 DAC0_OUT1ALT #4/ OPAMP_OUT1ALT
TIM0_CC0 #3 PCNT2_S1IN #0
US1_RX #1
DBG_SWO #2
Digital IO power supply 3.
HFXTAL_N
US0_CS #4/5 LEU0_RX #1
HFXTAL_P
US0_CLK #4/5 LEU0_TX #1
Analog power supply 1.
Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released.
silabs.com | Building a more connected world.
Rev. 2.30 | 216
CSP81 Pin# and Name
Pin #
Pin Name
J8
PB8
J9
PB7
Analog LFXTAL_N
LFXTAL_P
Pin Alternate Functionality / Description
Timers
Communication
TIM1_CC1 #3
US0_RX #4 US1_CS #0
TIM1_CC0 #3
US0_TX #4 US1_CLK #0
EFM32LG Data Sheet
Pin Definitions
Other
silabs.com | Building a more connected world.
Rev. 2.30 | 217
EFM32LG Data Sheet
Pin Definitions
5.8.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0.
Table 5.23. Alternate Functionality Overview
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
ACMP0_CH0 PC0
Analog comparator ACMP0, channel 0.
ACMP0_CH1 PC1
Analog comparator ACMP0, channel 1.
ACMP0_CH2 PC2
Analog comparator ACMP0, channel 2.
ACMP0_CH3 PC3
Analog comparator ACMP0, channel 3.
ACMP0_CH4 PC4
Analog comparator ACMP0, channel 4.
ACMP0_CH5 PC5
Analog comparator ACMP0, channel 5.
ACMP0_CH6 PC6
Analog comparator ACMP0, channel 6.
ACMP0_CH7 PC7
Analog comparator ACMP0, channel 7.
ACMP0_O
PE13 PE2 PD6
Analog comparator ACMP0, digital output.
ACMP1_CH0 PC8
Analog comparator ACMP1, channel 0.
ACMP1_CH1 PC9
Analog comparator ACMP1, channel 1.
ACMP1_CH2 PC10
Analog comparator ACMP1, channel 2.
ACMP1_CH3 PC11
Analog comparator ACMP1, channel 3.
ACMP1_CH4 PC12
Analog comparator ACMP1, channel 4.
ACMP1_CH5 PC13
Analog comparator ACMP1, channel 5.
ACMP1_CH6 PC14
Analog comparator ACMP1, channel 6.
ACMP1_CH7 PC15
Analog comparator ACMP1, channel 7.
ACMP1_O
PF2 PE3 PD7
Analog comparator ACMP1, digital output.
ADC0_CH0
PD0
Analog to digital converter ADC0, input channel number 0.
ADC0_CH1
PD1
Analog to digital converter ADC0, input channel number 1.
ADC0_CH2
PD2
Analog to digital converter ADC0, input channel number 2.
ADC0_CH3
PD3
Analog to digital converter ADC0, input channel number 3.
ADC0_CH4
PD4
Analog to digital converter ADC0, input channel number 4.
ADC0_CH5
PD5
Analog to digital converter ADC0, input channel number 5.
ADC0_CH6
PD6
Analog to digital converter ADC0, input channel number 6.
silabs.com | Building a more connected world.
Rev. 2.30 | 218
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
ADC0_CH7
PD7
Analog to digital converter ADC0, input channel number 7.
BOOT_RX
PE11
Bootloader RX.
BOOT_TX
PE10
Bootloader TX.
BU_STAT
PE3
Backup Power Domain status, whether or not the system is in backup mode
BU_VIN
PD8
Battery input for Backup Power Domain
BU_VOUT
PE2
Power output for Backup Power Domain
CMU_CLK0
PA2 PC12 PD7
Clock Management Unit, clock output number 0.
CMU_CLK1
PA1 PD8 PE12
Clock Management Unit, clock output number 1.
DAC0_OUT0 / OPAMP_OUT0
PB11
Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0.
DAC0_OUT0ALT / OPAMP_OUT0A PC0 PC1 PC2 PC3 PD0 LT
Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0.
DAC0_OUT1 / OPAMP_OUT1
PB12
Digital to Analog Converter DAC0_OUT1 /OPAMP output channel number 1.
DAC0_OUT1ALT / OPAMP_OUT1A PC12 PC13 PC14 PC15 PD1 LT
Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1.
DBG_SWCLK PF0 PF0 PF0 PF0
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, and has a built-in pull down.
DBG_SWDIO PF1 PF1 PF1 PF1
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and has a built-in pull up.
DBG_SWO
PF2 PC15 PD1 PD2
Debug-interface Serial Wire viewer Output.
Note that this function is not enabled after reset, and must be enabled by software to be used.
ETM_TCLK
PD7
PC6 PA6
Embedded Trace Module ETM clock .
ETM_TD0
PD6
PC7 PA2
Embedded Trace Module ETM data 0.
ETM_TD1
PD3
PD3 PA3
Embedded Trace Module ETM data 1.
ETM_TD2
PD4
PD4 PA4
Embedded Trace Module ETM data 2.
ETM_TD3
PD5
PD5 PA5
Embedded Trace Module ETM data 3.
GPIO_EM4WU0 PA0
Pin can be used to wake the system up from EM4
GPIO_EM4WU1 PA6
Pin can be used to wake the system up from EM4
GPIO_EM4WU2 PC9
Pin can be used to wake the system up from EM4
GPIO_EM4WU3 PF1
Pin can be used to wake the system up from EM4
GPIO_EM4WU4 PF2
Pin can be used to wake the system up from EM4
GPIO_EM4WU5 PE13
Pin can be used to wake the system up from EM4
silabs.com | Building a more connected world.
Rev. 2.30 | 219
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
HFXTAL_N
PB14
High Frequency Crystal negative pin. Also used as external optional clock input pin.
HFXTAL_P
PB13
High Frequency Crystal positive pin.
I2C0_SCL
PA1 PD7 PC7
PC1 PF1 PE13 I2C0 Serial Clock Line input / output.
I2C0_SDA
PA0 PD6 PC6
PC0 PF0 PE12 I2C0 Serial Data input / output.
I2C1_SCL
PC5 PB12
I2C1 Serial Clock Line input / output.
I2C1_SDA
PC4 PB11
I2C1 Serial Data input / output.
LES_ALTEX0 PD6
LESENSE alternate exite output 0.
LES_ALTEX1 PD7
LESENSE alternate exite output 1.
LES_ALTEX2 PA3
LESENSE alternate exite output 2.
LES_ALTEX3 PA4
LESENSE alternate exite output 3.
LES_ALTEX4 PA5
LESENSE alternate exite output 4.
LES_ALTEX5 PE11
LESENSE alternate exite output 5.
LES_ALTEX6 PE12
LESENSE alternate exite output 6.
LES_ALTEX7 PE13
LESENSE alternate exite output 7.
LES_CH0
PC0
LESENSE channel 0.
LES_CH1
PC1
LESENSE channel 1.
LES_CH2
PC2
LESENSE channel 2.
LES_CH3
PC3
LESENSE channel 3.
LES_CH4
PC4
LESENSE channel 4.
LES_CH5
PC5
LESENSE channel 5.
LES_CH6
PC6
LESENSE channel 6.
LES_CH7
PC7
LESENSE channel 7.
LES_CH8
PC8
LESENSE channel 8.
LES_CH9
PC9
LESENSE channel 9.
LES_CH10
PC10
LESENSE channel 10.
LES_CH11
PC11
LESENSE channel 11.
LES_CH12
PC12
LESENSE channel 12.
LES_CH13
PC13
LESENSE channel 13.
LES_CH14
PC14
LESENSE channel 14.
LES_CH15
PC15
LESENSE channel 15.
LETIM0_OUT0 PD6 PB11 PF0 PC4
Low Energy Timer LETIM0, output channel 0.
LETIM0_OUT1 PD7 PB12 PF1 PC5
Low Energy Timer LETIM0, output channel 1.
LEU0_RX
PD5 PB14 PE15 PF1 PA0
LEUART0 Receive input.
LEU0_TX
PD4 PB13 PE14 PF0 PF2
LEUART0 Transmit output. Also used as receive input in half duplex communication.
LEU1_RX
PC7 PA6
LEUART1 Receive input.
silabs.com | Building a more connected world.
Rev. 2.30 | 220
Alternate
LOCATION
Functionality
0
1
2
3
4
5
LEU1_TX
PC6 PA5
LFXTAL_N
PB8
LFXTAL_P
PB7
OPAMP_N0 / DAC0_N0
PC5
OPAMP_N1 / DAC0_N1
PD7
OPAMP_N2
PD3
OPAMP_OUT2 PD5 PD0
OPAMP_P0 / DAC0_P0
PC4
OPAMP_P1 / DAC0_P1
PD6
OPAMP_P2
PD4
PCNT0_S0IN PC13
PC0 PD6
PCNT0_S1IN PC14
PC1 PD7
PCNT1_S0IN PC4 PB3
PCNT1_S1IN PC5 PB4
PCNT2_S0IN PD0 PE8
PCNT2_S1IN PD1 PE9
PRS_CH0
PA0
PRS_CH1
PA1
PRS_CH2
PC0 PF5
PRS_CH3
PC1 PE8
TIM0_CC0
PA0 PA0
PD1 PA0 PF0
TIM0_CC1
PA1 PA1
PD2 PC0 PF1
TIM0_CC2
PA2 PA2
PD3 PC1 PF2
TIM0_CDTI0
PA3 PC13
PC13 PC2
TIM0_CDTI1
PA4 PC14
PC14 PC3
TIM0_CDTI2
PA5 PC15 PF5 PC15 PC4 PF5
TIM1_CC0 TIM1_CC1 TIM1_CC2 TIM2_CC0
PC13 PE10
PC14 PE11
PC15 PE12
PA8
PC8
PB7 PB8 PB11
PD6 PD7 PC13
silabs.com | Building a more connected world.
EFM32LG Data Sheet
Pin Definitions
6
Description
LEUART1 Transmit output. Also used as receive input in half duplex communication.
Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin.
Low Frequency Crystal (typically 32.768 kHz) positive pin.
Operational Amplifier 0 external negative input.
Operational Amplifier 1 external negative input. Operational Amplifier 2 external negative input. Operational Amplifier 2 output. Operational Amplifier 0 external positive input.
Operational Amplifier 1 external positive input.
Operational Amplifier 2 external positive input. Pulse Counter PCNT0 input number 0. Pulse Counter PCNT0 input number 1. Pulse Counter PCNT1 input number 0. Pulse Counter PCNT1 input number 1. Pulse Counter PCNT2 input number 0. Pulse Counter PCNT2 input number 1. Peripheral Reflex System PRS, channel 0. Peripheral Reflex System PRS, channel 1. Peripheral Reflex System PRS, channel 2. Peripheral Reflex System PRS, channel 3. Timer 0 Capture Compare input / output channel 0. Timer 0 Capture Compare input / output channel 1. Timer 0 Capture Compare input / output channel 2. Timer 0 Complimentary Deat Time Insertion channel 0. Timer 0 Complimentary Deat Time Insertion channel 1. Timer 0 Complimentary Deat Time Insertion channel 2. Timer 1 Capture Compare input / output channel 0. Timer 1 Capture Compare input / output channel 1. Timer 1 Capture Compare input / output channel 2. Timer 2 Capture Compare input / output channel 0.
Rev. 2.30 | 221
Alternate Functionality TIM2_CC1 TIM2_CC2 TIM3_CC0 TIM3_CC1 TIM3_CC2 U0_RX
U0_TX
U1_RX
U1_TX
US0_CLK US0_CS
LOCATION
0
1
2
3
4
5
PA9
PC9
PA10
PC10
PE14
PE15
PA15 PE2
PA4 PC15
PA3 PC14
PC13 PF11
PE3
PC12 PF10
PE2
PE12 PE5 PC9 PC15 PB13 PB13 PE13 PE4 PC8 PC14 PB14 PB14
US0_RX
PE11
PC10 PE12 PB8 PC1
US0_TX
US1_CLK US1_CS US1_RX
PE10
PC11 PE13 PB7 PC0
PB7 PD2 PF0 PB8 PD3 PF1
PC1 PD1 PD6
US1_TX
US2_CLK US2_CS US2_RX
PC0 PD0 PD7
PC4 PB5 PC5 PB6 PC3 PB4
US2_TX
PC2 PB3
USB_DM USB_DMPU
PF10 PD2
EFM32LG Data Sheet
Pin Definitions
6
Description
Timer 2 Capture Compare input / output channel 1.
Timer 2 Capture Compare input / output channel 2.
Timer 3 Capture Compare input / output channel 0.
Timer 3 Capture Compare input / output channel 1.
Timer 3 Capture Compare input / output channel 2.
UART0 Receive input.
UART0 Transmit output. Also used as receive input in half duplex communication.
UART1 Receive input.
UART1 Transmit output. Also used as receive input in half duplex communication.
USART0 clock input / output.
USART0 chip select input / output.
USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output (MISO).
USART0 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input (MOSI).
USART1 clock input / output.
USART1 chip select input / output.
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output (MISO).
USART1 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input (MOSI).
USART2 clock input / output.
USART2 chip select input / output.
USART2 Asynchronous Receive.
USART2 Synchronous mode Master Input / Slave Output (MISO).
USART2 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART2 Synchronous mode Master Output / Slave Input (MOSI).
USB D- pin.
USB D- Pullup control.
silabs.com | Building a more connected world.
Rev. 2.30 | 222
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
USB_DP
PF11
USB D+ pin.
USB_ID
PF12
USB ID pin. Used in OTG mode.
USB_VBUS
USB_V BUS
USB 5 V VBUS input.
USB_VBUSEN PF5
USB 5 V VBUS enable.
USB_VREGI
USB_V REGI
USB Input to internal 3.3 V regulator
USB_VREGO
USB_V REGO
USB Decoupling for internal 3.3 V USB regulator and regulator output
5.8.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG360 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.24. GPIO Pinout
Port
Port A Port B Port C Port D Port E Port F
Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 15 14 13 12 11 10
PA15 -
-
-
- PA10 PA9 PA8 - PA6 PA5 PA4 PA3 PA2 PA1 PA0
- PB14 PB13 PB12 PB11 -
- PB8 PB7 PB6 PB5 PB4 PB3 -
-
-
PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
-
-
-
-
-
-
- PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 -
- PE5 PE4 PE3 PE2 -
-
-
-
- PF12 PF11 PF10 -
-
-
- PF5 -
- PF2 PF1 PF0
5.8.4 Opamp Pinout Overview
The specific opamp terminals available in EFM32LG360 is shown in the following figure.
PC4
+ OUT0ALT
PC5
OPA0 -
OUT0
PD4
+
PD3
OPA2 -
OUT2
PD6
+ OUT1ALT
OPA1 OUT1
PD7
-
PB11 PB12 PC0 PC1 PC2 PC3 PC12 PC13 PC14 PC15 PD0 PD1 PD5
Figure 5.16. Opamp Pinout
silabs.com | Building a more connected world.
Rev. 2.30 | 223
5.9 EFM32LG380 (LQFP100)
EFM32LG Data Sheet
Pin Definitions
5.9.1 Pinout
The EFM32LG380 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question.
Figure 5.17. EFM32LG380 Pinout (top view, not to scale)
silabs.com | Building a more connected world.
Rev. 2.30 | 224
EFM32LG Data Sheet
Pin Definitions
Table 5.25. Device Pinout
LQFP100 Pin# and Name
Pin # Pin Name
1
PA0
2
PA1
Analog
Pin Alternate Functionality / Description
EBI EBI_AD09 #0/1/2
Timers TIM0_CC0 #0/1/4
Communication
LEU0_RX #4 I2C0_SDA #0
EBI_AD10 #0/1/2 TIM0_CC1 #0/1
I2C0_SCL #0
3
PA2
EBI_AD11 #0/1/2 TIM0_CC2 #0/1
4
PA3
EBI_AD12 #0/1/2 TIM0_CDTI0 #0
U0_TX #2
5
PA4
EBI_AD13 #0/1/2 TIM0_CDTI1 #0
U0_RX #2
6
PA5
EBI_AD14 #0/1/2 TIM0_CDTI2 #0
LEU1_TX #1
7
PA6
EBI_AD15 #0/1/2
LEU1_RX #1
8
IOVDD_0 Digital IO power supply 0.
9
PB0
EBI_A16 #0/1/2
TIM1_CC0 #2
10
PB1
EBI_A17 #0/1/2
TIM1_CC1 #2
11
PB2
EBI_A18 #0/1/2
TIM1_CC2 #2
12
PB3
EBI_A19 #0/1/2
PCNT1_S0IN #1
US2_TX #1
13
PB4
EBI_A20 #0/1/2
PCNT1_S1IN #1
US2_RX #1
14
PB5
EBI_A21 #0/1/2
US2_CLK #1
15
PB6
EBI_A22 #0/1/2
US2_CS #1
16
VSS
Ground.
17
IOVDD_1 Digital IO power supply 1.
18
PC0
ACMP0_CH0 DAC0_OUT0ALT
#0/ OPAMP_OUT0ALT
EBI_A23 #0/1/2
TIM0_CC1 #4 PCNT0_S0IN #2
US0_TX #5 US1_TX #0 I2C0_SDA #4
19
PC1
ACMP0_CH1 DAC0_OUT0ALT
#1/ OPAMP_OUT0ALT
EBI_A24 #0/1/2
TIM0_CC2 #4 PCNT0_S1IN #2
US0_RX #5 US1_RX #0 I2C0_SCL #4
ACMP0_CH2
20
PC2
DAC0_OUT0ALT #2/
EBI_A25 #0/1/2
TIM0_CDTI0 #4
US2_TX #0
OPAMP_OUT0ALT
ACMP0_CH3
21
PC3
DAC0_OUT0ALT #3/
EBI_NANDREn #0/1/2
TIM0_CDTI1 #4
US2_RX #0
OPAMP_OUT0ALT
Other PRS_CH0 #0 GPIO_EM4WU0 CMU_CLK1 #0 PRS_CH1 #0 CMU_CLK0 #0 ETM_TD0 #3 LES_ALTEX2 #0 ETM_TD1 #3 LES_ALTEX3 #0 ETM_TD2 #3 LES_ALTEX4 #0 ETM_TD3 #3 ETM_TCLK #3 GPIO_EM4WU1
LES_CH0 #0 PRS_CH2 #0
LES_CH1 #0 PRS_CH3 #0
LES_CH2 #0
LES_CH3 #0
silabs.com | Building a more connected world.
Rev. 2.30 | 225
EFM32LG Data Sheet
Pin Definitions
LQFP100 Pin# and Name
Pin # Pin Name
22
PC4
23
PC5
24
PB7
25
PB8
26
PA7
27
PA8
28
PA9
29
PA10
30
PA11
31
IOVDD_2
32
VSS
33
PA12
34
PA13
35
PA14
36
RESETn
37
PB9
38
PB10
39
PB11
40
PB12
41
AVDD_1
42
PB13
43
PB14
44
IOVDD_3
45
AVDD_0
46
PD0
Pin Alternate Functionality / Description
Analog
EBI
Timers
Communication
Other
ACMP0_CH4 / DAC0_P0 / OPAMP_P0
EBI_A26 #0/1/2
TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0
US2_CLK #0 I2C1_SDA #0
LES_CH4 #0
ACMP0_CH5 / DAC0_N0 / OPAMP_N0
EBI_NANDWEn #0/1/2
LETIM0_OUT1 #3 PCNT1_S1IN #0
US2_CS #0 I2C1_SCL #0
LES_CH5 #0
LFXTAL_P
TIM1_CC0 #3
US0_TX #4 US1_CLK #0
LFXTAL_N
TIM1_CC1 #3
US0_RX #4 US1_CS #0
EBI_CSTFT #0/1/2
EBI_DCLK #0/1/2
TIM2_CC0 #0
EBI_DTEN #0/1/2
TIM2_CC1 #0
EBI_VSNC #0/1/2
TIM2_CC2 #0
EBI_HSNC #0/1/2
Digital IO power supply 2.
Ground.
EBI_A00 #0/1/2
TIM2_CC0 #1
EBI_A01 #0/1/2
TIM2_CC1 #1
EBI_A02 #0/1/2
TIM2_CC2 #1
Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released.
EBI_A03 #0/1/2
U1_TX #2
EBI_A04 #0/1/2
U1_RX #2
DAC0_OUT0 / OPAMP_OUT0
TIM1_CC2 #3 LETIM0_OUT0 #1
I2C1_SDA #1
DAC0_OUT1 / OPAMP_OUT1
LETIM0_OUT1 #1
I2C1_SCL #1
Analog power supply 1.
HFXTAL_P
US0_CLK #4/5 LEU0_TX #1
HFXTAL_N
US0_CS #4/5 LEU0_RX #1
Digital IO power supply 3.
Analog power supply 0.
ADC0_CH0 DAC0_OUT0ALT
#4/ OPAMP_OUT0ALT OPAMP_OUT2 #1
PCNT2_S0IN #0
US1_TX #1
silabs.com | Building a more connected world.
Rev. 2.30 | 226
EFM32LG Data Sheet
Pin Definitions
LQFP100 Pin# and Name
Pin # Pin Name
47
PD1
48
PD2
49
PD3
50
PD4
51
PD5
52
PD6
53
PD7
54
PD8
55
PC6
56
PC7
57 VDD_DREG
58
VSS
59 DECOUPLE
60
PE0
61
PE1
62
PE2
63
PE3
64
PE4
65
PE5
66
PE6
67
PE7
68
PC8
69
PC9
70
PC10
71
PC11
Pin Alternate Functionality / Description
Analog
EBI
Timers
Communication
Other
ADC0_CH1 DAC0_OUT1ALT
#4/ OPAMP_OUT1ALT
TIM0_CC0 #3 PCNT2_S1IN #0
US1_RX #1
DBG_SWO #2
ADC0_CH2
EBI_A27 #0/1/2
TIM0_CC1 #3
USB_DMPU #0 US1_CLK #1
DBG_SWO #3
ADC0_CH3 OPAMP_N2
TIM0_CC2 #3
US1_CS #1
ETM_TD1 #0/2
ADC0_CH4 OPAMP_P2
LEU0_TX #0
ETM_TD2 #0/2
ADC0_CH5 OPAMP_OUT2 #0
LEU0_RX #0
ETM_TD3 #0/2
ADC0_CH6 / DAC0_P1 / OPAMP_P1
TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3
US1_RX #2 I2C0_SDA #1
LES_ALTEX0 #0 ACMP0_O #2 ETM_TD0 #0
ADC0_CH7 / DAC0_N1 / OPAMP_N1
TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3
US1_TX #2 I2C0_SCL #1
CMU_CLK0 #2 LES_ALTEX1 #0
ACMP1_O #2 ETM_TCLK #0
BU_VIN
CMU_CLK1 #1
ACMP0_CH6
EBI_A05 #0/1/2
LEU1_TX #0 I2C0_SDA #2
LES_CH6 #0 ETM_TCLK #2
ACMP0_CH7
EBI_A06 #0/1/2
LEU1_RX #0 I2C0_SCL #2
LES_CH7 #0 ETM_TD0 #2
Power supply for on-chip voltage regulator.
Ground.
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin.
EBI_A07 #0/1/2
TIM3_CC0 #1 PCNT0_S0IN #1
U0_TX #1 I2C1_SDA #2
EBI_A08 #0/1/2
TIM3_CC1 #1 PCNT0_S1IN #1
U0_RX #1 I2C1_SCL #2
BU_VOUT
EBI_A09 #0
TIM3_CC2 #1
U1_TX #3
ACMP0_O #1
BU_STAT
EBI_A10 #0
U1_RX #3
ACMP1_O #1
EBI_A11 #0/1/2
US0_CS #1
EBI_A12 #0/1/2
US0_CLK #1
EBI_A13 #0/1/2
US0_RX #1
EBI_A14 #0/1/2
US0_TX #1
ACMP1_CH0
EBI_A15 #0/1/2
TIM2_CC0 #2
US0_CS #2
LES_CH8 #0
ACMP1_CH1
EBI_A09 #1/2
TIM2_CC1 #2
US0_CLK #2
LES_CH9 #0 GPIO_EM4WU2
ACMP1_CH2
EBI_A10 #1/2
TIM2_CC2 #2
US0_RX #2
LES_CH10 #0
ACMP1_CH3
EBI_ALE #1/2
US0_TX #2
LES_CH11 #0
silabs.com | Building a more connected world.
Rev. 2.30 | 227
EFM32LG Data Sheet
Pin Definitions
LQFP100 Pin# and Name
Pin Alternate Functionality / Description
Pin # Pin Name
Analog
EBI
Timers
Communication
72 USB_VREGI Input to internal 3.3V USB regulator
73 USB_VREGO Output and decoupling for internal 3.3V USB regulator
74
PF10
U1_TX #1 USB_DM
75
PF11
U1_RX #1 USB_DP
76
PF0
TIM0_CC0 #5 LETIM0_OUT0 #2
US1_CLK #2 LEU0_TX #3 I2C0_SDA #5
77
PF1
TIM0_CC1 #5 LETIM0_OUT1 #2
US1_CS #2 LEU0_RX #3 I2C0_SCL #5
78
PF2
EBI_ARDY #0/1/2
TIM0_CC2 #5
LEU0_TX #4
79 USB_VBUS USB 5.0 V VBUS input.
80
PF12
USB_ID
81
PF5
EBI_REn #0/2
TIM0_CDTI2 #2/5 USB_VBUSEN #0
82
IOVDD_5 Digital IO power supply 5.
83
VSS
Ground.
84
PF6
EBI_BL0 #0/1/2
TIM0_CC0 #2
U0_TX #0
85
PF7
EBI_BL1 #0/1/2
TIM0_CC1 #2
U0_RX #0
86
PF8
EBI_WEn #1
TIM0_CC2 #2
87
PF9
EBI_REn #1
88
PD9
EBI_CS0 #0/1/2
89
PD10
EBI_CS1 #0/1/2
90
PD11
EBI_CS2 #0/1/2
91
PD12
EBI_CS3 #0/1/2
92
PE8
EBI_AD00 #0/1/2 PCNT2_S0IN #1
93
PE9
EBI_AD01 #0/1/2 PCNT2_S1IN #1
94
PE10
EBI_AD02 #0/1/2
TIM1_CC0 #1
US0_TX #0
95
PE11
EBI_AD03 #0/1/2
TIM1_CC1 #1
US0_RX #0
96
PE12
97
PE13
98
PE14
99
PE15
100
PA15
EBI_AD04 #0/1/2
TIM1_CC2 #1
EBI_AD05 #0/1/2
EBI_AD06 #0/1/2 EBI_AD07 #0/1/2 EBI_AD08 #0/1/2
TIM3_CC0 #0 TIM3_CC1 #0 TIM3_CC2 #0
US0_RX #3 US0_CLK #0 I2C0_SDA #6
US0_TX #3 US0_CS #0 I2C0_SCL #6
LEU0_TX #2
LEU0_RX #2
Other
DBG_SWCLK #0/1/2/3
DBG_SWDIO #0/1/2/3
GPIO_EM4WU3 ACMP1_O #0 DBG_SWO #0
GPIO_EM4WU4
PRS_CH2 #1
ETM_TCLK #1 ETM_TD0 #1
PRS_CH3 #1
BOOT_TX LES_ALTEX5 #0
BOOT_RX CMU_CLK1 #2 LES_ALTEX6 #0 LES_ALTEX7 #0 ACMP0_O #0 GPIO_EM4WU5
silabs.com | Building a more connected world.
Rev. 2.30 | 228
EFM32LG Data Sheet
Pin Definitions
5.9.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0.
Table 5.26. Alternate Functionality Overview
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
ACMP0_CH0 PC0
Analog comparator ACMP0, channel 0.
ACMP0_CH1 PC1
Analog comparator ACMP0, channel 1.
ACMP0_CH2 PC2
Analog comparator ACMP0, channel 2.
ACMP0_CH3 PC3
Analog comparator ACMP0, channel 3.
ACMP0_CH4 PC4
Analog comparator ACMP0, channel 4.
ACMP0_CH5 PC5
Analog comparator ACMP0, channel 5.
ACMP0_CH6 PC6
Analog comparator ACMP0, channel 6.
ACMP0_CH7 PC7
Analog comparator ACMP0, channel 7.
ACMP0_O
PE13 PE2 PD6
Analog comparator ACMP0, digital output.
ACMP1_CH0 PC8
Analog comparator ACMP1, channel 0.
ACMP1_CH1 PC9
Analog comparator ACMP1, channel 1.
ACMP1_CH2 PC10
Analog comparator ACMP1, channel 2.
ACMP1_CH3 PC11
Analog comparator ACMP1, channel 3.
ACMP1_O
PF2 PE3 PD7
Analog comparator ACMP1, digital output.
ADC0_CH0
PD0
Analog to digital converter ADC0, input channel number 0.
ADC0_CH1
PD1
Analog to digital converter ADC0, input channel number 1.
ADC0_CH2
PD2
Analog to digital converter ADC0, input channel number 2.
ADC0_CH3
PD3
Analog to digital converter ADC0, input channel number 3.
ADC0_CH4
PD4
Analog to digital converter ADC0, input channel number 4.
ADC0_CH5
PD5
Analog to digital converter ADC0, input channel number 5.
ADC0_CH6
PD6
Analog to digital converter ADC0, input channel number 6.
ADC0_CH7
PD7
Analog to digital converter ADC0, input channel number 7.
BOOT_RX
PE11
Bootloader RX.
BOOT_TX
PE10
Bootloader TX.
silabs.com | Building a more connected world.
Rev. 2.30 | 229
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
BU_STAT
PE3
Backup Power Domain status, whether or not the system is in backup mode
BU_VIN
PD8
Battery input for Backup Power Domain
BU_VOUT
PE2
Power output for Backup Power Domain
CMU_CLK0
PA2
PD7
Clock Management Unit, clock output number 0.
CMU_CLK1
PA1 PD8 PE12
Clock Management Unit, clock output number 1.
DAC0_OUT0 / OPAMP_OUT0
PB11
Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0.
DAC0_OUT0ALT / OPAMP_OUT0A PC0 PC1 PC2 PC3 PD0 LT
Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0.
DAC0_OUT1 / OPAMP_OUT1
PB12
Digital to Analog Converter DAC0_OUT1 /OPAMP output channel number 1.
DAC0_OUT1ALT / OPAMP_OUT1A LT
PD1
Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1.
DBG_SWCLK PF0 PF0 PF0 PF0
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, and has a built-in pull down.
DBG_SWDIO PF1 PF1 PF1 PF1
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and has a built-in pull up.
DBG_SWO
PF2
PD1 PD2
Debug-interface Serial Wire viewer Output.
Note that this function is not enabled after reset, and must be enabled by software to be used.
EBI_A00
PA12 PA12 PA12
External Bus Interface (EBI) address output pin 00.
EBI_A01
PA13 PA13 PA13
External Bus Interface (EBI) address output pin 01.
EBI_A02
PA14 PA14 PA14
External Bus Interface (EBI) address output pin 02.
EBI_A03
PB9 PB9 PB9
External Bus Interface (EBI) address output pin 03.
EBI_A04
PB10 PB10 PB10
External Bus Interface (EBI) address output pin 04.
EBI_A05
PC6 PC6 PC6
External Bus Interface (EBI) address output pin 05.
EBI_A06
PC7 PC7 PC7
External Bus Interface (EBI) address output pin 06.
EBI_A07
PE0 PE0 PE0
External Bus Interface (EBI) address output pin 07.
EBI_A08
PE1 PE1 PE1
External Bus Interface (EBI) address output pin 08.
EBI_A09
PE2 PC9 PC9
External Bus Interface (EBI) address output pin 09.
EBI_A10
PE3 PC10 PC10
External Bus Interface (EBI) address output pin 10.
EBI_A11
PE4 PE4 PE4
External Bus Interface (EBI) address output pin 11.
EBI_A12
PE5 PE5 PE5
External Bus Interface (EBI) address output pin 12.
EBI_A13
PE6 PE6 PE6
External Bus Interface (EBI) address output pin 13.
EBI_A14
PE7 PE7 PE7
External Bus Interface (EBI) address output pin 14.
silabs.com | Building a more connected world.
Rev. 2.30 | 230
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
EBI_A15
PC8 PC8 PC8
External Bus Interface (EBI) address output pin 15.
EBI_A16
PB0 PB0 PB0
External Bus Interface (EBI) address output pin 16.
EBI_A17
PB1 PB1 PB1
External Bus Interface (EBI) address output pin 17.
EBI_A18
PB2 PB2 PB2
External Bus Interface (EBI) address output pin 18.
EBI_A19
PB3 PB3 PB3
External Bus Interface (EBI) address output pin 19.
EBI_A20
PB4 PB4 PB4
External Bus Interface (EBI) address output pin 20.
EBI_A21
PB5 PB5 PB5
External Bus Interface (EBI) address output pin 21.
EBI_A22
PB6 PB6 PB6
External Bus Interface (EBI) address output pin 22.
EBI_A23
PC0 PC0 PC0
External Bus Interface (EBI) address output pin 23.
EBI_A24
PC1 PC1 PC1
External Bus Interface (EBI) address output pin 24.
EBI_A25
PC2 PC2 PC2
External Bus Interface (EBI) address output pin 25.
EBI_A26
PC4 PC4 PC4
External Bus Interface (EBI) address output pin 26.
EBI_A27
PD2 PD2 PD2
External Bus Interface (EBI) address output pin 27.
EBI_AD00
PE8 PE8 PE8
External Bus Interface (EBI) address and data input / output pin 00.
EBI_AD01
PE9 PE9 PE9
External Bus Interface (EBI) address and data input / output pin 01.
EBI_AD02
PE10 PE10 PE10
External Bus Interface (EBI) address and data input / output pin 02.
EBI_AD03
PE11 PE11 PE11
External Bus Interface (EBI) address and data input / output pin 03.
EBI_AD04
PE12 PE12 PE12
External Bus Interface (EBI) address and data input / output pin 04.
EBI_AD05
PE13 PE13 PE13
External Bus Interface (EBI) address and data input / output pin 05.
EBI_AD06
PE14 PE14 PE14
External Bus Interface (EBI) address and data input / output pin 06.
EBI_AD07
PE15 PE15 PE15
External Bus Interface (EBI) address and data input / output pin 07.
EBI_AD08
PA15 PA15 PA15
External Bus Interface (EBI) address and data input / output pin 08.
EBI_AD09
PA0 PA0 PA0
External Bus Interface (EBI) address and data input / output pin 09.
EBI_AD10
PA1 PA1 PA1
External Bus Interface (EBI) address and data input / output pin 10.
EBI_AD11
PA2 PA2 PA2
External Bus Interface (EBI) address and data input / output pin 11.
EBI_AD12
PA3 PA3 PA3
External Bus Interface (EBI) address and data input / output pin 12.
EBI_AD13
PA4 PA4 PA4
External Bus Interface (EBI) address and data input / output pin 13.
silabs.com | Building a more connected world.
Rev. 2.30 | 231
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
EBI_AD14
PA5 PA5 PA5
External Bus Interface (EBI) address and data input / output pin 14.
EBI_AD15
PA6 PA6 PA6
External Bus Interface (EBI) address and data input / output pin 15.
EBI_ALE
PC11 PC11
External Bus Interface (EBI) Address Latch Enable output.
EBI_ARDY
PF2 PF2 PF2
External Bus Interface (EBI) Hardware Ready Control input.
EBI_BL0
PF6 PF6 PF6
External Bus Interface (EBI) Byte Lane/Enable pin 0.
EBI_BL1
PF7 PF7 PF7
External Bus Interface (EBI) Byte Lane/Enable pin 1.
EBI_CS0
PD9 PD9 PD9
External Bus Interface (EBI) Chip Select output 0.
EBI_CS1
PD10 PD10 PD10
External Bus Interface (EBI) Chip Select output 1.
EBI_CS2
PD11 PD11 PD11
External Bus Interface (EBI) Chip Select output 2.
EBI_CS3
PD12 PD12 PD12
External Bus Interface (EBI) Chip Select output 3.
EBI_CSTFT
PA7 PA7 PA7
External Bus Interface (EBI) Chip Select output TFT.
EBI_DCLK
PA8 PA8 PA8
External Bus Interface (EBI) TFT Dot Clock pin.
EBI_DTEN
PA9 PA9 PA9
External Bus Interface (EBI) TFT Data Enable pin.
EBI_HSNC
PA11 PA11 PA11
External Bus Interface (EBI) TFT Horizontal Synchronization pin.
EBI_NANDREn PC3 PC3 PC3
External Bus Interface (EBI) NAND Read Enable output.
EBI_NANDWEn PC5 PC5 PC5
External Bus Interface (EBI) NAND Write Enable output.
EBI_REn
PF5 PF9 PF5
External Bus Interface (EBI) Read Enable output.
EBI_VSNC
PA10 PA10 PA10
External Bus Interface (EBI) TFT Vertical Synchronization pin.
EBI_WEn
PF8
External Bus Interface (EBI) Write Enable output.
ETM_TCLK
PD7 PF8 PC6 PA6
Embedded Trace Module ETM clock .
ETM_TD0
PD6 PF9 PC7 PA2
Embedded Trace Module ETM data 0.
ETM_TD1
PD3
PD3 PA3
Embedded Trace Module ETM data 1.
ETM_TD2
PD4
PD4 PA4
Embedded Trace Module ETM data 2.
ETM_TD3
PD5
PD5 PA5
Embedded Trace Module ETM data 3.
GPIO_EM4WU0 PA0
Pin can be used to wake the system up from EM4
GPIO_EM4WU1 PA6
Pin can be used to wake the system up from EM4
GPIO_EM4WU2 PC9
Pin can be used to wake the system up from EM4
GPIO_EM4WU3 PF1
Pin can be used to wake the system up from EM4
GPIO_EM4WU4 PF2
Pin can be used to wake the system up from EM4
GPIO_EM4WU5 PE13
Pin can be used to wake the system up from EM4
silabs.com | Building a more connected world.
Rev. 2.30 | 232
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
HFXTAL_N
PB14
High Frequency Crystal negative pin. Also used as external optional clock input pin.
HFXTAL_P
PB13
High Frequency Crystal positive pin.
I2C0_SCL
PA1 PD7 PC7
PC1 PF1 PE13 I2C0 Serial Clock Line input / output.
I2C0_SDA
PA0 PD6 PC6
PC0 PF0 PE12 I2C0 Serial Data input / output.
I2C1_SCL
PC5 PB12 PE1
I2C1 Serial Clock Line input / output.
I2C1_SDA
PC4 PB11 PE0
I2C1 Serial Data input / output.
LES_ALTEX0 PD6
LESENSE alternate exite output 0.
LES_ALTEX1 PD7
LESENSE alternate exite output 1.
LES_ALTEX2 PA3
LESENSE alternate exite output 2.
LES_ALTEX3 PA4
LESENSE alternate exite output 3.
LES_ALTEX4 PA5
LESENSE alternate exite output 4.
LES_ALTEX5 PE11
LESENSE alternate exite output 5.
LES_ALTEX6 PE12
LESENSE alternate exite output 6.
LES_ALTEX7 PE13
LESENSE alternate exite output 7.
LES_CH0
PC0
LESENSE channel 0.
LES_CH1
PC1
LESENSE channel 1.
LES_CH2
PC2
LESENSE channel 2.
LES_CH3
PC3
LESENSE channel 3.
LES_CH4
PC4
LESENSE channel 4.
LES_CH5
PC5
LESENSE channel 5.
LES_CH6
PC6
LESENSE channel 6.
LES_CH7
PC7
LESENSE channel 7.
LES_CH8
PC8
LESENSE channel 8.
LES_CH9
PC9
LESENSE channel 9.
LES_CH10
PC10
LESENSE channel 10.
LES_CH11
PC11
LESENSE channel 11.
LETIM0_OUT0 PD6 PB11 PF0 PC4
Low Energy Timer LETIM0, output channel 0.
LETIM0_OUT1 PD7 PB12 PF1 PC5
Low Energy Timer LETIM0, output channel 1.
LEU0_RX
PD5 PB14 PE15 PF1 PA0
LEUART0 Receive input.
LEU0_TX
PD4 PB13 PE14 PF0 PF2
LEUART0 Transmit output. Also used as receive input in half duplex communication.
LEU1_RX
PC7 PA6
LEUART1 Receive input.
LEU1_TX
PC6 PA5
LEUART1 Transmit output. Also used as receive input in half duplex communication.
LFXTAL_N
PB8
Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin.
silabs.com | Building a more connected world.
Rev. 2.30 | 233
Alternate
LOCATION
Functionality
0
1
2
3
4
5
LFXTAL_P
PB7
OPAMP_N0 / DAC0_N0
PC5
OPAMP_N1 / DAC0_N1
PD7
OPAMP_N2
PD3
OPAMP_OUT2 PD5 PD0
OPAMP_P0 / DAC0_P0
PC4
OPAMP_P1 / DAC0_P1
PD6
OPAMP_P2
PD4
PCNT0_S0IN
PE0 PC0 PD6
PCNT0_S1IN
PE1 PC1 PD7
PCNT1_S0IN PC4 PB3
PCNT1_S1IN PC5 PB4
PCNT2_S0IN PD0 PE8
PCNT2_S1IN PD1 PE9
PRS_CH0
PA0
PRS_CH1
PA1
PRS_CH2
PC0 PF5
PRS_CH3
PC1 PE8
TIM0_CC0
PA0 PA0 PF6 PD1 PA0 PF0
TIM0_CC1
PA1 PA1 PF7 PD2 PC0 PF1
TIM0_CC2
PA2 PA2 PF8 PD3 PC1 PF2
TIM0_CDTI0
PA3
PC2
TIM0_CDTI1
PA4
PC3
TIM0_CDTI2
TIM1_CC0 TIM1_CC1 TIM1_CC2 TIM2_CC0 TIM2_CC1 TIM2_CC2 TIM3_CC0
PA5
PF5
PC4 PF5
PE10 PB0 PB7 PD6 PE11 PB1 PB8 PD7 PE12 PB2 PB11 PA8 PA12 PC8 PA9 PA13 PC9 PA10 PA14 PC10 PE14 PE0
EFM32LG Data Sheet
Pin Definitions
6
Description
Low Frequency Crystal (typically 32.768 kHz) positive pin.
Operational Amplifier 0 external negative input.
Operational Amplifier 1 external negative input. Operational Amplifier 2 external negative input. Operational Amplifier 2 output. Operational Amplifier 0 external positive input.
Operational Amplifier 1 external positive input.
Operational Amplifier 2 external positive input. Pulse Counter PCNT0 input number 0. Pulse Counter PCNT0 input number 1. Pulse Counter PCNT1 input number 0. Pulse Counter PCNT1 input number 1. Pulse Counter PCNT2 input number 0. Pulse Counter PCNT2 input number 1. Peripheral Reflex System PRS, channel 0. Peripheral Reflex System PRS, channel 1. Peripheral Reflex System PRS, channel 2. Peripheral Reflex System PRS, channel 3. Timer 0 Capture Compare input / output channel 0. Timer 0 Capture Compare input / output channel 1. Timer 0 Capture Compare input / output channel 2. Timer 0 Complimentary Deat Time Insertion channel 0. Timer 0 Complimentary Deat Time Insertion channel 1. Timer 0 Complimentary Deat Time Insertion channel 2. Timer 1 Capture Compare input / output channel 0. Timer 1 Capture Compare input / output channel 1. Timer 1 Capture Compare input / output channel 2. Timer 2 Capture Compare input / output channel 0. Timer 2 Capture Compare input / output channel 1. Timer 2 Capture Compare input / output channel 2. Timer 3 Capture Compare input / output channel 0.
silabs.com | Building a more connected world.
Rev. 2.30 | 234
Alternate Functionality TIM3_CC1 TIM3_CC2 U0_RX
U0_TX
U1_RX
U1_TX
US0_CLK US0_CS
LOCATION
0
1
2
3
4
5
PE15 PE1
PA15 PE2
PF7 PE1 PA4
PF6 PE0 PA3
PF11 PB10 PE3
PF10 PB9 PE2
PE12 PE5 PC9 PE13 PE4 PC8
PB13 PB13 PB14 PB14
US0_RX
PE11 PE6 PC10 PE12 PB8 PC1
US0_TX
US1_CLK US1_CS US1_RX
PE10 PE7 PC11 PE13 PB7 PC0
PB7 PD2 PF0 PB8 PD3 PF1 PC1 PD1 PD6
US1_TX
US2_CLK US2_CS US2_RX
PC0 PD0 PD7
PC4 PB5 PC5 PB6 PC3 PB4
US2_TX
PC2 PB3
USB_DM USB_DMPU USB_DP USB_ID
USB_VBUS
PF10 PD2 PF11 PF12 USB_V BUS
silabs.com | Building a more connected world.
EFM32LG Data Sheet
Pin Definitions
6
Description
Timer 3 Capture Compare input / output channel 1.
Timer 3 Capture Compare input / output channel 2.
UART0 Receive input.
UART0 Transmit output. Also used as receive input in half duplex communication.
UART1 Receive input.
UART1 Transmit output. Also used as receive input in half duplex communication.
USART0 clock input / output.
USART0 chip select input / output.
USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output (MISO).
USART0 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input (MOSI).
USART1 clock input / output.
USART1 chip select input / output.
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output (MISO).
USART1 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input (MOSI).
USART2 clock input / output.
USART2 chip select input / output.
USART2 Asynchronous Receive.
USART2 Synchronous mode Master Input / Slave Output (MISO).
USART2 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART2 Synchronous mode Master Output / Slave Input (MOSI).
USB D- pin.
USB D- Pullup control.
USB D+ pin.
USB ID pin. Used in OTG mode.
USB 5 V VBUS input.
Rev. 2.30 | 235
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
USB_VBUSEN PF5
USB 5 V VBUS enable.
USB_VREGI
USB_V REGI
USB Input to internal 3.3 V regulator
USB_VREGO
USB_V REGO
USB Decoupling for internal 3.3 V USB regulator and regulator output
5.9.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG380 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.27. GPIO Pinout
Port
Port A Port B Port C Port D Port E Port F
Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 15 14 13 12 11 10 PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 -- PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 -- -- -- -- PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 -- -- -- PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 -- -- -- PF12 PF11 PF10 PF9 PF8 PF7 PF6 PF5 -- -- PF2 PF1 PF0
5.9.4 Opamp Pinout Overview
The specific opamp terminals available in EFM32LG380 is shown in the following figure.
PC4
+ OUT0ALT
PC5
OPA0 -
OUT0
PD4
+
PD3
OPA2 -
OUT2
PD6
+ OUT1ALT
PD7
OPA1 -
OUT1
PB11 PB12 PC0 PC1 PC2 PC3 PC12 PC13 PC14 PC15 PD0 PD1 PD5
Figure 5.18. Opamp Pinout
silabs.com | Building a more connected world.
Rev. 2.30 | 236
5.10 EFM32LG390 (BGA112)
EFM32LG Data Sheet
Pin Definitions
5.10.1 Pinout
The EFM32LG390 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question.
Figure 5.19. EFM32LG390 Pinout (top view, not to scale) Table 5.28. Device Pinout
BGA112 Pin# and Name
Pin # Pin Name
A1
PE15
A2
PE14
A3
PE12
Analog
Pin Alternate Functionality / Description
EBI EBI_AD07 #0/1/2 EBI_AD06 #0/1/2
EBI_AD04 #0/1/2
Timers TIM3_CC1 #0 TIM3_CC0 #0
TIM1_CC2 #1
Communication
LEU0_RX #2
LEU0_TX #2
US0_RX #3 US0_CLK #0 I2C0_SDA #6
Other
CMU_CLK1 #2 LES_ALTEX6 #0
silabs.com | Building a more connected world.
Rev. 2.30 | 237
EFM32LG Data Sheet
Pin Definitions
BGA112 Pin# and Name
Pin # Pin Name
A4
PE9
A5
PD10
A6
PF7
A7
PF5
A8
PF12
A9
PE4
A10
PF10
A11
PF11
B1
PA15
B2
PE13
Analog
Pin Alternate Functionality / Description
EBI EBI_AD01 #0/1/2 EBI_CS1 #0/1/2 EBI_BL1 #0/1/2
EBI_REn #0/2
EBI_A11 #0/1/2
EBI_AD08 #0/1/2 EBI_AD05 #0/1/2
Timers PCNT2_S1IN #1
Communication
TIM0_CC1 #2
U0_RX #0
TIM0_CDTI2 #2/5 USB_VBUSEN #0
USB_ID
US0_CS #1
U1_TX #1 USB_DM
U1_RX #1 USB_DP
TIM3_CC2 #0
US0_TX #3 US0_CS #0 I2C0_SCL #6
B3
PE11
EBI_AD03 #0/1/2
TIM1_CC1 #1
US0_RX #0
B4
PE8
EBI_AD00 #0/1/2 PCNT2_S0IN #1
B5
PD11
EBI_CS2 #0/1/2
B6
PF8
EBI_WEn #1
TIM0_CC2 #2
B7
PF6
EBI_BL0 #0/1/2
TIM0_CC0 #2
B8 USB_VBUS USB 5.0 V VBUS input.
B9
PE5
EBI_A12 #0/1/2
B10 USB_VREGI Input to internal 3.3 V USB regulator
B11 USB_VREGO Output and decoupling for internal 3.3 V USB regulator
U0_TX #0 US0_CLK #1
C1
PA1
EBI_AD10 #0/1/2 TIM0_CC1 #0/1
I2C0_SCL #0
C2
PA0
C3
PE10
C4
PD13
C5
PD12
C6
PF9
C7
VSS
Ground.
EBI_AD09 #0/1/2 TIM0_CC0 #0/1/4
EBI_AD02 #0/1/2
TIM1_CC0 #1
LEU0_RX #4 I2C0_SDA #0
US0_TX #0
EBI_CS3 #0/1/2 EBI_REn #1
C8
PF2
EBI_ARDY #0/1/2
TIM0_CC2 #5
LEU0_TX #4
C9
PE6
C10
PC10
C11
PC11
D1
PA3
ACMP1_CH2 ACMP1_CH3
EBI_A13 #0/1/2 EBI_A10 #1/2 EBI_ALE #1/2
EBI_AD12 #0/1/2
TIM2_CC2 #2 TIM0_CDTI0 #0
US0_RX #1 US0_RX #2 US0_TX #2
U0_TX #2
Other
PRS_CH2 #1
LES_ALTEX7 #0 ACMP0_O #0
GPIO_EM4WU5 LES_ALTEX5 #0
BOOT_RX PRS_CH3 #1
ETM_TCLK #1
CMU_CLK1 #0 PRS_CH1 #0 PRS_CH0 #0 GPIO_EM4WU0
BOOT_TX ETM_TD1 #1
ETM_TD0 #1
ACMP1_O #0 DBG_SWO #0 GPIO_EM4WU4
LES_CH10 #0 LES_CH11 #0 LES_ALTEX2 #0 ETM_TD1 #3
silabs.com | Building a more connected world.
Rev. 2.30 | 238
EFM32LG Data Sheet
Pin Definitions
BGA112 Pin# and Name
Pin # Pin Name
D2
PA2
D3
PB15
D4
VSS
D5
IOVDD_6
D6
PD9
D7
IOVDD_5
D8
PF1
D9
PE7
D10
PC8
D11
PC9
E1
PA6
E2
PA5
E3
PA4
E4
PB0
E8
PF0
E9
PE0
E10
PE1
E11
PE3
F1
PB1
F2
PB2
F3
PB3
F4
PB4
F8 VDD_DREG
F9 VSS_DREG
F10
PE2
F11 DECOUPLE
G1
PB5
G2
PB6
Pin Alternate Functionality / Description
Analog
EBI
Timers
Communication
Other
EBI_AD11 #0/1/2 TIM0_CC2 #0/1
CMU_CLK0 #0 ETM_TD0 #3
ETM_TD2 #1
Ground.
Digital IO power supply 6.
EBI_CS0 #0/1/2
Digital IO power supply 5.
TIM0_CC1 #5 LETIM0_OUT1 #2
US1_CS #2 LEU0_RX #3 I2C0_SCL #5
DBG_SWDIO #0/1/2/3
GPIO_EM4WU3
EBI_A14 #0/1/2
US0_TX #1
ACMP1_CH0
EBI_A15 #0/1/2
TIM2_CC0 #2
US0_CS #2
LES_CH8 #0
ACMP1_CH1
EBI_A09 #1/2
TIM2_CC1 #2
US0_CLK #2
LES_CH9 #0 GPIO_EM4WU2
EBI_AD15 #0/1/2
LEU1_RX #1
ETM_TCLK #3 GPIO_EM4WU1
EBI_AD14 #0/1/2 TIM0_CDTI2 #0
LEU1_TX #1
LES_ALTEX4 #0 ETM_TD3 #3
EBI_AD13 #0/1/2 TIM0_CDTI1 #0
U0_RX #2
LES_ALTEX3 #0 ETM_TD2 #3
EBI_A16 #0/1/2
TIM1_CC0 #2
TIM0_CC0 #5 LETIM0_OUT0 #2
US1_CLK #2 LEU0_TX #3 I2C0_SDA #5
DBG_SWCLK #0/1/2/3
EBI_A07 #0/1/2
TIM3_CC0 #1 PCNT0_S0IN #1
U0_TX #1 I2C1_SDA #2
EBI_A08 #0/1/2
TIM3_CC1 #1 PCNT0_S1IN #1
U0_RX #1 I2C1_SCL #2
BU_STAT
EBI_A10 #0
U1_RX #3
ACMP1_O #1
EBI_A17 #0/1/2
TIM1_CC1 #2
EBI_A18 #0/1/2
TIM1_CC2 #2
EBI_A19 #0/1/2
PCNT1_S0IN #1
US2_TX #1
EBI_A20 #0/1/2
PCNT1_S1IN #1
US2_RX #1
Power supply for on-chip voltage regulator.
Ground for on-chip voltage regulator.
BU_VOUT
EBI_A09 #0
TIM3_CC2 #1
U1_TX #3
ACMP0_O #1
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin.
EBI_A21 #0/1/2
US2_CLK #1
EBI_A22 #0/1/2
US2_CS #1
silabs.com | Building a more connected world.
Rev. 2.30 | 239
EFM32LG Data Sheet
Pin Definitions
BGA112 Pin# and Name
Pin # Pin Name
G3
VSS
G4
IOVDD_0
G8
IOVDD_4
G9
VSS
G10
PC6
G11
PC7
H1
PC0
H2
PC2
H3
PD14
H4
PA7
H5
PA8
H6
VSS
H7
IOVDD_3
H8
PD8
H9
PD5
H10
PD6
Pin Alternate Functionality / Description
Analog
EBI
Ground.
Digital IO power supply 0.
Digital IO power supply 4.
Ground.
ACMP0_CH6
EBI_A05 #0/1/2
Timers
ACMP0_CH7
EBI_A06 #0/1/2
ACMP0_CH0 DAC0_OUT0ALT
#0/ OPAMP_OUT0ALT
ACMP0_CH2 DAC0_OUT0ALT
#2/ OPAMP_OUT0ALT
EBI_A23 #0/1/2 EBI_A25 #0/1/2
TIM0_CC1 #4 PCNT0_S0IN #2
TIM0_CDTI0 #4
EBI_CSTFT #0/1/2
EBI_DCLK #0/1/2
Ground.
Digital IO power supply 3.
BU_VIN
ADC0_CH5 OPAMP_OUT2 #0
ADC0_CH6 / DAC0_P1 / OPAMP_P1
TIM2_CC0 #0
TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3
Communication
LEU1_TX #0 I2C0_SDA #2 LEU1_RX #0 I2C0_SCL #2 US0_TX #5 US1_TX #0 I2C0_SDA #4 US2_TX #0 I2C0_SDA #3
LEU0_RX #0 US1_RX #2 I2C0_SDA #1
H11
PD7
ADC0_CH7 / DAC0_N1 / OPAMP_N1
TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3
US1_TX #2 I2C0_SCL #1
J1
PC1
ACMP0_CH1 DAC0_OUT0ALT
#1/ OPAMP_OUT0ALT
EBI_A24 #0/1/2
TIM0_CC2 #4 PCNT0_S1IN #2
US0_RX #5 US1_RX #0 I2C0_SCL #4
ACMP0_CH3
J2
PC3
DAC0_OUT0ALT #3/
EBI_NANDREn #0/1/2
TIM0_CDTI1 #4
US2_RX #0
OPAMP_OUT0ALT
J3
PD15
I2C0_SCL #3
J4
PA12
EBI_A00 #0/1/2
TIM2_CC0 #1
J5
PA9
EBI_DTEN #0/1/2
TIM2_CC1 #0
J6
PA10
EBI_VSNC #0/1/2
TIM2_CC2 #0
J7
PB9
EBI_A03 #0/1/2
U1_TX #2
Other
LES_CH6 #0 ETM_TCLK #2 LES_CH7 #0 ETM_TD0 #2 LES_CH0 #0 PRS_CH2 #0
LES_CH2 #0
CMU_CLK1 #1 ETM_TD3 #0/2 LES_ALTEX0 #0 ACMP0_O #2 ETM_TD0 #0 CMU_CLK0 #2 LES_ALTEX1 #0 ACMP1_O #2 ETM_TCLK #0 LES_CH1 #0 PRS_CH3 #0
LES_CH3 #0
silabs.com | Building a more connected world.
Rev. 2.30 | 240
EFM32LG Data Sheet
Pin Definitions
BGA112 Pin# and Name
Pin # Pin Name
J8
PB10
J9
PD2
J10
PD3
J11
PD4
K1
PB7
K2
PC4
K3
PA13
K4
VSS
K5
PA11
K6
RESETn
K7
AVSS_1
K8
AVDD_2
K9
AVDD_1
K10
AVSS_0
K11
PD1
L1
PB8
L2
PC5
L3
PA14
L4
IOVDD_1
L5
PB11
L6
PB12
L7
AVSS_2
L8
PB13
L9
PB14
L10
AVDD_0
Pin Alternate Functionality / Description
Analog
EBI
Timers
Communication
Other
EBI_A04 #0/1/2
U1_RX #2
ADC0_CH2
EBI_A27 #0/1/2
TIM0_CC1 #3
USB_DMPU #0 US1_CLK #1
DBG_SWO #3
ADC0_CH3 OPAMP_N2
TIM0_CC2 #3
US1_CS #1
ETM_TD1 #0/2
ADC0_CH4 OPAMP_P2
LEU0_TX #0
ETM_TD2 #0/2
LFXTAL_P
TIM1_CC0 #3
US0_TX #4 US1_CLK #0
ACMP0_CH4 / DAC0_P0 / OPAMP_P0
EBI_A26 #0/1/2
TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0
US2_CLK #0 I2C1_SDA #0
LES_CH4 #0
EBI_A01 #0/1/2
TIM2_CC1 #1
Ground.
EBI_HSNC #0/1/2
Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released.
Analog ground 1.
Analog power supply 2.
Analog power supply 1.
Analog ground 0.
ADC0_CH1 DAC0_OUT1ALT
#4/ OPAMP_OUT1ALT
TIM0_CC0 #3 PCNT2_S1IN #0
US1_RX #1
DBG_SWO #2
LFXTAL_N
TIM1_CC1 #3
US0_RX #4 US1_CS #0
ACMP0_CH5 / DAC0_N0 / OPAMP_N0
EBI_NANDWEn #0/1/2
LETIM0_OUT1 #3 PCNT1_S1IN #0
US2_CS #0 I2C1_SCL #0
LES_CH5 #0
EBI_A02 #0/1/2
TIM2_CC2 #1
Digital IO power supply 1.
DAC0_OUT0 / OPAMP_OUT0
TIM1_CC2 #3 LETIM0_OUT0 #1
I2C1_SDA #1
DAC0_OUT1 / OPAMP_OUT1
LETIM0_OUT1 #1
I2C1_SCL #1
Analog ground 2.
HFXTAL_P
US0_CLK #4/5 LEU0_TX #1
HFXTAL_N
US0_CS #4/5 LEU0_RX #1
Analog power supply 0.
silabs.com | Building a more connected world.
Rev. 2.30 | 241
BGA112 Pin# and Name
Pin # Pin Name
L11
PD0
Analog
ADC0_CH0 DAC0_OUT0ALT
#4/ OPAMP_OUT0ALT OPAMP_OUT2 #1
EFM32LG Data Sheet
Pin Definitions
Pin Alternate Functionality / Description
EBI
Timers
Communication
Other
PCNT2_S0IN #0
US1_TX #1
silabs.com | Building a more connected world.
Rev. 2.30 | 242
EFM32LG Data Sheet
Pin Definitions
5.10.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0.
Table 5.29. Alternate Functionality Overview
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
ACMP0_CH0 PC0
Analog comparator ACMP0, channel 0.
ACMP0_CH1 PC1
Analog comparator ACMP0, channel 1.
ACMP0_CH2 PC2
Analog comparator ACMP0, channel 2.
ACMP0_CH3 PC3
Analog comparator ACMP0, channel 3.
ACMP0_CH4 PC4
Analog comparator ACMP0, channel 4.
ACMP0_CH5 PC5
Analog comparator ACMP0, channel 5.
ACMP0_CH6 PC6
Analog comparator ACMP0, channel 6.
ACMP0_CH7 PC7
Analog comparator ACMP0, channel 7.
ACMP0_O
PE13 PE2 PD6
Analog comparator ACMP0, digital output.
ACMP1_CH0 PC8
Analog comparator ACMP1, channel 0.
ACMP1_CH1 PC9
Analog comparator ACMP1, channel 1.
ACMP1_CH2 PC10
Analog comparator ACMP1, channel 2.
ACMP1_CH3 PC11
Analog comparator ACMP1, channel 3.
ACMP1_O
PF2 PE3 PD7
Analog comparator ACMP1, digital output.
ADC0_CH0
PD0
Analog to digital converter ADC0, input channel number 0.
ADC0_CH1
PD1
Analog to digital converter ADC0, input channel number 1.
ADC0_CH2
PD2
Analog to digital converter ADC0, input channel number 2.
ADC0_CH3
PD3
Analog to digital converter ADC0, input channel number 3.
ADC0_CH4
PD4
Analog to digital converter ADC0, input channel number 4.
ADC0_CH5
PD5
Analog to digital converter ADC0, input channel number 5.
ADC0_CH6
PD6
Analog to digital converter ADC0, input channel number 6.
ADC0_CH7
PD7
Analog to digital converter ADC0, input channel number 7.
BOOT_RX
PE11
Bootloader RX.
BOOT_TX
PE10
Bootloader TX.
silabs.com | Building a more connected world.
Rev. 2.30 | 243
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
BU_STAT
PE3
Backup Power Domain status, whether or not the system is in backup mode
BU_VIN
PD8
Battery input for Backup Power Domain
BU_VOUT
PE2
Power output for Backup Power Domain
CMU_CLK0
PA2
PD7
Clock Management Unit, clock output number 0.
CMU_CLK1
PA1 PD8 PE12
Clock Management Unit, clock output number 1.
DAC0_OUT0 / OPAMP_OUT0
PB11
Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0.
DAC0_OUT0ALT / OPAMP_OUT0A PC0 PC1 PC2 PC3 PD0 LT
Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0.
DAC0_OUT1 / OPAMP_OUT1
PB12
Digital to Analog Converter DAC0_OUT1 /OPAMP output channel number 1.
DAC0_OUT1ALT / OPAMP_OUT1A LT
PD1
Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1.
DBG_SWCLK PF0 PF0 PF0 PF0
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, and has a built-in pull down.
DBG_SWDIO PF1 PF1 PF1 PF1
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and has a built-in pull up.
DBG_SWO
PF2
PD1 PD2
Debug-interface Serial Wire viewer Output.
Note that this function is not enabled after reset, and must be enabled by software to be used.
EBI_A00
PA12 PA12 PA12
External Bus Interface (EBI) address output pin 00.
EBI_A01
PA13 PA13 PA13
External Bus Interface (EBI) address output pin 01.
EBI_A02
PA14 PA14 PA14
External Bus Interface (EBI) address output pin 02.
EBI_A03
PB9 PB9 PB9
External Bus Interface (EBI) address output pin 03.
EBI_A04
PB10 PB10 PB10
External Bus Interface (EBI) address output pin 04.
EBI_A05
PC6 PC6 PC6
External Bus Interface (EBI) address output pin 05.
EBI_A06
PC7 PC7 PC7
External Bus Interface (EBI) address output pin 06.
EBI_A07
PE0 PE0 PE0
External Bus Interface (EBI) address output pin 07.
EBI_A08
PE1 PE1 PE1
External Bus Interface (EBI) address output pin 08.
EBI_A09
PE2 PC9 PC9
External Bus Interface (EBI) address output pin 09.
EBI_A10
PE3 PC10 PC10
External Bus Interface (EBI) address output pin 10.
EBI_A11
PE4 PE4 PE4
External Bus Interface (EBI) address output pin 11.
EBI_A12
PE5 PE5 PE5
External Bus Interface (EBI) address output pin 12.
EBI_A13
PE6 PE6 PE6
External Bus Interface (EBI) address output pin 13.
EBI_A14
PE7 PE7 PE7
External Bus Interface (EBI) address output pin 14.
silabs.com | Building a more connected world.
Rev. 2.30 | 244
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
EBI_A15
PC8 PC8 PC8
External Bus Interface (EBI) address output pin 15.
EBI_A16
PB0 PB0 PB0
External Bus Interface (EBI) address output pin 16.
EBI_A17
PB1 PB1 PB1
External Bus Interface (EBI) address output pin 17.
EBI_A18
PB2 PB2 PB2
External Bus Interface (EBI) address output pin 18.
EBI_A19
PB3 PB3 PB3
External Bus Interface (EBI) address output pin 19.
EBI_A20
PB4 PB4 PB4
External Bus Interface (EBI) address output pin 20.
EBI_A21
PB5 PB5 PB5
External Bus Interface (EBI) address output pin 21.
EBI_A22
PB6 PB6 PB6
External Bus Interface (EBI) address output pin 22.
EBI_A23
PC0 PC0 PC0
External Bus Interface (EBI) address output pin 23.
EBI_A24
PC1 PC1 PC1
External Bus Interface (EBI) address output pin 24.
EBI_A25
PC2 PC2 PC2
External Bus Interface (EBI) address output pin 25.
EBI_A26
PC4 PC4 PC4
External Bus Interface (EBI) address output pin 26.
EBI_A27
PD2 PD2 PD2
External Bus Interface (EBI) address output pin 27.
EBI_AD00
PE8 PE8 PE8
External Bus Interface (EBI) address and data input / output pin 00.
EBI_AD01
PE9 PE9 PE9
External Bus Interface (EBI) address and data input / output pin 01.
EBI_AD02
PE10 PE10 PE10
External Bus Interface (EBI) address and data input / output pin 02.
EBI_AD03
PE11 PE11 PE11
External Bus Interface (EBI) address and data input / output pin 03.
EBI_AD04
PE12 PE12 PE12
External Bus Interface (EBI) address and data input / output pin 04.
EBI_AD05
PE13 PE13 PE13
External Bus Interface (EBI) address and data input / output pin 05.
EBI_AD06
PE14 PE14 PE14
External Bus Interface (EBI) address and data input / output pin 06.
EBI_AD07
PE15 PE15 PE15
External Bus Interface (EBI) address and data input / output pin 07.
EBI_AD08
PA15 PA15 PA15
External Bus Interface (EBI) address and data input / output pin 08.
EBI_AD09
PA0 PA0 PA0
External Bus Interface (EBI) address and data input / output pin 09.
EBI_AD10
PA1 PA1 PA1
External Bus Interface (EBI) address and data input / output pin 10.
EBI_AD11
PA2 PA2 PA2
External Bus Interface (EBI) address and data input / output pin 11.
EBI_AD12
PA3 PA3 PA3
External Bus Interface (EBI) address and data input / output pin 12.
EBI_AD13
PA4 PA4 PA4
External Bus Interface (EBI) address and data input / output pin 13.
silabs.com | Building a more connected world.
Rev. 2.30 | 245
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
EBI_AD14
PA5 PA5 PA5
External Bus Interface (EBI) address and data input / output pin 14.
EBI_AD15
PA6 PA6 PA6
External Bus Interface (EBI) address and data input / output pin 15.
EBI_ALE
PC11 PC11
External Bus Interface (EBI) Address Latch Enable output.
EBI_ARDY
PF2 PF2 PF2
External Bus Interface (EBI) Hardware Ready Control input.
EBI_BL0
PF6 PF6 PF6
External Bus Interface (EBI) Byte Lane/Enable pin 0.
EBI_BL1
PF7 PF7 PF7
External Bus Interface (EBI) Byte Lane/Enable pin 1.
EBI_CS0
PD9 PD9 PD9
External Bus Interface (EBI) Chip Select output 0.
EBI_CS1
PD10 PD10 PD10
External Bus Interface (EBI) Chip Select output 1.
EBI_CS2
PD11 PD11 PD11
External Bus Interface (EBI) Chip Select output 2.
EBI_CS3
PD12 PD12 PD12
External Bus Interface (EBI) Chip Select output 3.
EBI_CSTFT
PA7 PA7 PA7
External Bus Interface (EBI) Chip Select output TFT.
EBI_DCLK
PA8 PA8 PA8
External Bus Interface (EBI) TFT Dot Clock pin.
EBI_DTEN
PA9 PA9 PA9
External Bus Interface (EBI) TFT Data Enable pin.
EBI_HSNC
PA11 PA11 PA11
External Bus Interface (EBI) TFT Horizontal Synchronization pin.
EBI_NANDREn PC3 PC3 PC3
External Bus Interface (EBI) NAND Read Enable output.
EBI_NANDWEn PC5 PC5 PC5
External Bus Interface (EBI) NAND Write Enable output.
EBI_REn
PF5 PF9 PF5
External Bus Interface (EBI) Read Enable output.
EBI_VSNC
PA10 PA10 PA10
External Bus Interface (EBI) TFT Vertical Synchronization pin.
EBI_WEn
PF8
External Bus Interface (EBI) Write Enable output.
ETM_TCLK
PD7 PF8 PC6 PA6
Embedded Trace Module ETM clock .
ETM_TD0
PD6 PF9 PC7 PA2
Embedded Trace Module ETM data 0.
ETM_TD1
PD3 PD13 PD3 PA3
Embedded Trace Module ETM data 1.
ETM_TD2
PD4 PB15 PD4 PA4
Embedded Trace Module ETM data 2.
ETM_TD3
PD5
PD5 PA5
Embedded Trace Module ETM data 3.
GPIO_EM4WU0 PA0
Pin can be used to wake the system up from EM4
GPIO_EM4WU1 PA6
Pin can be used to wake the system up from EM4
GPIO_EM4WU2 PC9
Pin can be used to wake the system up from EM4
GPIO_EM4WU3 PF1
Pin can be used to wake the system up from EM4
GPIO_EM4WU4 PF2
Pin can be used to wake the system up from EM4
GPIO_EM4WU5 PE13
Pin can be used to wake the system up from EM4
silabs.com | Building a more connected world.
Rev. 2.30 | 246
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
HFXTAL_N
PB14
High Frequency Crystal negative pin. Also used as external optional clock input pin.
HFXTAL_P
PB13
High Frequency Crystal positive pin.
I2C0_SCL
PA1 PD7 PC7 PD15 PC1 PF1 PE13 I2C0 Serial Clock Line input / output.
I2C0_SDA
PA0 PD6 PC6 PD14 PC0 PF0 PE12 I2C0 Serial Data input / output.
I2C1_SCL
PC5 PB12 PE1
I2C1 Serial Clock Line input / output.
I2C1_SDA
PC4 PB11 PE0
I2C1 Serial Data input / output.
LES_ALTEX0 PD6
LESENSE alternate exite output 0.
LES_ALTEX1 PD7
LESENSE alternate exite output 1.
LES_ALTEX2 PA3
LESENSE alternate exite output 2.
LES_ALTEX3 PA4
LESENSE alternate exite output 3.
LES_ALTEX4 PA5
LESENSE alternate exite output 4.
LES_ALTEX5 PE11
LESENSE alternate exite output 5.
LES_ALTEX6 PE12
LESENSE alternate exite output 6.
LES_ALTEX7 PE13
LESENSE alternate exite output 7.
LES_CH0
PC0
LESENSE channel 0.
LES_CH1
PC1
LESENSE channel 1.
LES_CH2
PC2
LESENSE channel 2.
LES_CH3
PC3
LESENSE channel 3.
LES_CH4
PC4
LESENSE channel 4.
LES_CH5
PC5
LESENSE channel 5.
LES_CH6
PC6
LESENSE channel 6.
LES_CH7
PC7
LESENSE channel 7.
LES_CH8
PC8
LESENSE channel 8.
LES_CH9
PC9
LESENSE channel 9.
LES_CH10
PC10
LESENSE channel 10.
LES_CH11
PC11
LESENSE channel 11.
LETIM0_OUT0 PD6 PB11 PF0 PC4
Low Energy Timer LETIM0, output channel 0.
LETIM0_OUT1 PD7 PB12 PF1 PC5
Low Energy Timer LETIM0, output channel 1.
LEU0_RX
PD5 PB14 PE15 PF1 PA0
LEUART0 Receive input.
LEU0_TX
PD4 PB13 PE14 PF0 PF2
LEUART0 Transmit output. Also used as receive input in half duplex communication.
LEU1_RX
PC7 PA6
LEUART1 Receive input.
LEU1_TX
PC6 PA5
LEUART1 Transmit output. Also used as receive input in half duplex communication.
LFXTAL_N
PB8
Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin.
silabs.com | Building a more connected world.
Rev. 2.30 | 247
Alternate
LOCATION
Functionality
0
1
2
3
4
5
LFXTAL_P
PB7
OPAMP_N0 / DAC0_N0
PC5
OPAMP_N1 / DAC0_N1
PD7
OPAMP_N2
PD3
OPAMP_OUT2 PD5 PD0
OPAMP_P0 / DAC0_P0
PC4
OPAMP_P1 / DAC0_P1
PD6
OPAMP_P2
PD4
PCNT0_S0IN
PE0 PC0 PD6
PCNT0_S1IN
PE1 PC1 PD7
PCNT1_S0IN PC4 PB3
PCNT1_S1IN PC5 PB4
PCNT2_S0IN PD0 PE8
PCNT2_S1IN PD1 PE9
PRS_CH0
PA0
PRS_CH1
PA1
PRS_CH2
PC0 PF5
PRS_CH3
PC1 PE8
TIM0_CC0
PA0 PA0 PF6 PD1 PA0 PF0
TIM0_CC1
PA1 PA1 PF7 PD2 PC0 PF1
TIM0_CC2
PA2 PA2 PF8 PD3 PC1 PF2
TIM0_CDTI0
PA3
PC2
TIM0_CDTI1
PA4
PC3
TIM0_CDTI2
TIM1_CC0 TIM1_CC1 TIM1_CC2 TIM2_CC0 TIM2_CC1 TIM2_CC2 TIM3_CC0
PA5
PF5
PC4 PF5
PE10 PB0 PB7 PD6 PE11 PB1 PB8 PD7 PE12 PB2 PB11 PA8 PA12 PC8 PA9 PA13 PC9 PA10 PA14 PC10 PE14 PE0
EFM32LG Data Sheet
Pin Definitions
6
Description
Low Frequency Crystal (typically 32.768 kHz) positive pin.
Operational Amplifier 0 external negative input.
Operational Amplifier 1 external negative input. Operational Amplifier 2 external negative input. Operational Amplifier 2 output. Operational Amplifier 0 external positive input.
Operational Amplifier 1 external positive input.
Operational Amplifier 2 external positive input. Pulse Counter PCNT0 input number 0. Pulse Counter PCNT0 input number 1. Pulse Counter PCNT1 input number 0. Pulse Counter PCNT1 input number 1. Pulse Counter PCNT2 input number 0. Pulse Counter PCNT2 input number 1. Peripheral Reflex System PRS, channel 0. Peripheral Reflex System PRS, channel 1. Peripheral Reflex System PRS, channel 2. Peripheral Reflex System PRS, channel 3. Timer 0 Capture Compare input / output channel 0. Timer 0 Capture Compare input / output channel 1. Timer 0 Capture Compare input / output channel 2. Timer 0 Complimentary Deat Time Insertion channel 0. Timer 0 Complimentary Deat Time Insertion channel 1. Timer 0 Complimentary Deat Time Insertion channel 2. Timer 1 Capture Compare input / output channel 0. Timer 1 Capture Compare input / output channel 1. Timer 1 Capture Compare input / output channel 2. Timer 2 Capture Compare input / output channel 0. Timer 2 Capture Compare input / output channel 1. Timer 2 Capture Compare input / output channel 2. Timer 3 Capture Compare input / output channel 0.
silabs.com | Building a more connected world.
Rev. 2.30 | 248
Alternate Functionality TIM3_CC1 TIM3_CC2 U0_RX
U0_TX
U1_RX
U1_TX
US0_CLK US0_CS
LOCATION
0
1
2
3
4
5
PE15 PE1
PA15 PE2
PF7 PE1 PA4
PF6 PE0 PA3
PF11 PB10 PE3
PF10 PB9 PE2
PE12 PE5 PC9 PE13 PE4 PC8
PB13 PB13 PB14 PB14
US0_RX
PE11 PE6 PC10 PE12 PB8 PC1
US0_TX
US1_CLK US1_CS US1_RX
PE10 PE7 PC11 PE13 PB7 PC0
PB7 PD2 PF0 PB8 PD3 PF1 PC1 PD1 PD6
US1_TX
US2_CLK US2_CS US2_RX
PC0 PD0 PD7
PC4 PB5 PC5 PB6 PC3 PB4
US2_TX
PC2 PB3
USB_DM USB_DMPU USB_DP USB_ID
USB_VBUS
PF10 PD2 PF11 PF12 USB_V BUS
silabs.com | Building a more connected world.
EFM32LG Data Sheet
Pin Definitions
6
Description
Timer 3 Capture Compare input / output channel 1.
Timer 3 Capture Compare input / output channel 2.
UART0 Receive input.
UART0 Transmit output. Also used as receive input in half duplex communication.
UART1 Receive input.
UART1 Transmit output. Also used as receive input in half duplex communication.
USART0 clock input / output.
USART0 chip select input / output.
USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output (MISO).
USART0 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input (MOSI).
USART1 clock input / output.
USART1 chip select input / output.
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output (MISO).
USART1 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input (MOSI).
USART2 clock input / output.
USART2 chip select input / output.
USART2 Asynchronous Receive.
USART2 Synchronous mode Master Input / Slave Output (MISO).
USART2 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART2 Synchronous mode Master Output / Slave Input (MOSI).
USB D- pin.
USB D- Pullup control.
USB D+ pin.
USB ID pin. Used in OTG mode.
USB 5 V VBUS input.
Rev. 2.30 | 249
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
USB_VBUSEN PF5
USB 5 V VBUS enable.
USB_VREGI
USB_V REGI
USB Input to internal 3.3 V regulator
USB_VREGO
USB_V REGO
USB Decoupling for internal 3.3 V USB regulator and regulator output
5.10.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG390 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.30. GPIO Pinout
Port
Port A Port B Port C Port D Port E Port F
Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 15 14 13 12 11 10 PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 -- -- -- -- PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 -- -- -- PF12 PF11 PF10 PF9 PF8 PF7 PF6 PF5 -- -- PF2 PF1 PF0
5.10.4 Opamp Pinout Overview
The specific opamp terminals available in EFM32LG390 is shown in the following figure.
PC4
+ OUT0ALT
PC5
OPA0 -
OUT0
PD4
+
PD3
OPA2 -
OUT2
PD6
+ OUT1ALT
PD7
OPA1 -
OUT1
PB11 PB12 PC0 PC1 PC2 PC3
PD0 PD1 PD5
Figure 5.20. Opamp Pinout
silabs.com | Building a more connected world.
Rev. 2.30 | 250
5.11 EFM32LG395 (BGA120)
EFM32LG Data Sheet
Pin Definitions
5.11.1 Pinout
The EFM32LG395 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question.
Figure 5.21. EFM32LG395 Pinout (top view, not to scale) Table 5.31. Device Pinout
BGA120 Pin# and Name
Pin # Pin Name
A1
PE15
A2
PE14
A3
PE12
Analog
Pin Alternate Functionality / Description
EBI EBI_AD07 #0/1/2 EBI_AD06 #0/1/2
EBI_AD04 #0/1/2
Timers TIM3_CC1 #0 TIM3_CC0 #0
TIM1_CC2 #1
Communication
LEU0_RX #2
LEU0_TX #2
US0_RX #3 US0_CLK #0 I2C0_SDA #6
Other
CMU_CLK1 #2 LES_ALTEX6 #0
silabs.com | Building a more connected world.
Rev. 2.30 | 251
EFM32LG Data Sheet
Pin Definitions
BGA120 Pin# and Name
Pin # Pin Name
A4
PE9
A5
PD11
A6
PD9
A7
PF7
A8
PF5
A9
PF4
Analog
Pin Alternate Functionality / Description
EBI EBI_AD01 #0/1/2 EBI_CS2 #0/1/2 EBI_CS0 #0/1/2 EBI_BL1 #0/1/2
EBI_REn #0/2 EBI_WEn #0/2
Timers PCNT2_S1IN #1
Communication
TIM0_CC1 #2 TIM0_CDTI2 #2/5 TIM0_CDTI1 #2/5
U0_RX #0 USB_VBUSEN #0
A10
PF2
EBI_ARDY #0/1/2
TIM0_CC2 #5
LEU0_TX #4
A11 USB_VREGI Input to internal 3.3V USB regulator
A12 USB_VREGO Output and decoupling for internal 3.3V USB regulator
A13
PF11
B1
PA15
EBI_AD08 #0/1/2
TIM3_CC2 #0
B2
PE13
EBI_AD05 #0/1/2
U1_RX #1 USB_DP
US0_TX #3 US0_CS #0 I2C0_SCL #6
B3
PE11
EBI_AD03 #0/1/2
TIM1_CC1 #1
US0_RX #0
B4
PE8
B5
PD12
B6
PD10
B7
PF8
B8
PF6
EBI_AD00 #0/1/2 EBI_CS3 #0/1/2 EBI_CS1 #0/1/2
EBI_WEn #1 EBI_BL0 #0/1/2
PCNT2_S0IN #1
TIM0_CC2 #2 TIM0_CC0 #2
U0_TX #0
B9
PF3
EBI_ALE #0
TIM0_CDTI0 #2/5
B10
PF1
B11
PF12
B12 USB_VBUS USB 5.0 V VBUS input.
B13
PF10
TIM0_CC1 #5 LETIM0_OUT1 #2
US1_CS #2 LEU0_RX #3 I2C0_SCL #5
USB_ID
U1_TX #1 USB_DM
C1
PA1
EBI_AD10 #0/1/2 TIM0_CC1 #0/1
I2C0_SCL #0
C2
PA0
EBI_AD09 #0/1/2 TIM0_CC0 #0/1/4
LEU0_RX #4 I2C0_SDA #0
C3
PE10
EBI_AD02 #0/1/2
TIM1_CC0 #1
US0_TX #0
C4
PD13
C5
VSS
Ground.
C6
IOVDD_0 Digital IO power supply 0.
C7
PF9
EBI_REn #1
Other
PRS_CH2 #1 PRS_CH1 #1 ACMP1_O #0 DBG_SWO #0 GPIO_EM4WU4
LES_ALTEX7 #0 ACMP0_O #0
GPIO_EM4WU5 LES_ALTEX5 #0
BOOT_RX PRS_CH3 #1
ETM_TCLK #1
PRS_CH0 #1 ETM_TD3 #1 DBG_SWDIO
#0/1/2/3 GPIO_EM4WU3
CMU_CLK1 #0 PRS_CH1 #0 PRS_CH0 #0 GPIO_EM4WU0
BOOT_TX ETM_TD1 #1
ETM_TD0 #1
silabs.com | Building a more connected world.
Rev. 2.30 | 252
EFM32LG Data Sheet
Pin Definitions
BGA120 Pin# and Name
Pin # Pin Name
C8
VSS
C9
IOVDD_1
C10
PF0
C11
PE4
C12
PC14
C13
PC15
D1
PA3
D2
PA2
D3
PB15
D11
PE5
D12
PC12
D13
PC13
E1
PA6
E2
PA5
E3
PA4
E11
PE6
E12
PC10
E13
PC11
F1
PB0
F2
PB1
F3
PB2
F11
PE7
F12
PC8
F13
PC9
Pin Alternate Functionality / Description
Analog
EBI
Ground.
Digital IO power supply 1.
ACMP1_CH6 DAC0_OUT1ALT
#2/ OPAMP_OUT1ALT
ACMP1_CH7 DAC0_OUT1ALT
#3/ OPAMP_OUT1ALT
EBI_A11 #0/1/2
Timers
Communication
TIM0_CC0 #5 LETIM0_OUT0 #2
US1_CLK #2 LEU0_TX #3 I2C0_SDA #5
US0_CS #1
TIM0_CDTI1 #1/3 TIM1_CC1 #0
PCNT0_S1IN #0
US0_CS #3 U0_TX #3
TIM0_CDTI2 #1/3 TIM1_CC2 #0
US0_CLK #3 U0_RX #3
EBI_AD12 #0/1/2 TIM0_CDTI0 #0
U0_TX #2
EBI_AD11 #0/1/2 TIM0_CC2 #0/1
ACMP1_CH4 DAC0_OUT1ALT
#0/ OPAMP_OUT1ALT
ACMP1_CH5 DAC0_OUT1ALT
#1/ OPAMP_OUT1ALT
EBI_A12 #0/1/2
TIM0_CDTI0 #1/3 TIM1_CC0 #0 TIM1_CC2 #4
PCNT0_S0IN #0
EBI_AD15 #0/1/2
EBI_AD14 #0/1/2 TIM0_CDTI2 #0
ACMP1_CH2 ACMP1_CH3
ACMP1_CH0 ACMP1_CH1
EBI_AD13 #0/1/2
EBI_A13 #0/1/2 EBI_A10 #1/2 EBI_ALE #1/2 EBI_A16 #0/1/2 EBI_A17 #0/1/2 EBI_A18 #0/1/2 EBI_A14 #0/1/2 EBI_A15 #0/1/2
EBI_A09 #1/2
TIM0_CDTI1 #0
TIM2_CC2 #2
TIM1_CC0 #2 TIM1_CC1 #2 TIM1_CC2 #2
TIM2_CC0 #2 TIM2_CC1 #2
US0_CLK #1 U1_TX #0
U1_RX #0
LEU1_RX #1 LEU1_TX #1
U0_RX #2 US0_RX #1 US0_RX #2 US0_TX #2
US0_TX #1 US0_CS #2 US0_CLK #2
Other
DBG_SWCLK #0/1/2/3
LES_CH14 #0
LES_CH15 #0 DBG_SWO #1 LES_ALTEX2 #0 ETM_TD1 #3 CMU_CLK0 #0 ETM_TD0 #3 ETM_TD2 #1
CMU_CLK0 #1 LES_CH12 #0
LES_CH13 #0
ETM_TCLK #3 GPIO_EM4WU1 LES_ALTEX4 #0
ETM_TD3 #3 LES_ALTEX3 #0
ETM_TD2 #3
LES_CH10 #0 LES_CH11 #0
LES_CH8 #0 LES_CH9 #0 GPIO_EM4WU2
silabs.com | Building a more connected world.
Rev. 2.30 | 253
EFM32LG Data Sheet
Pin Definitions
BGA120 Pin# and Name
Pin # Pin Name
G1
PB3
G2
PB4
G3
IOVDD_2
G11
PE0
G12
PE1
G13
PE3
H1
PB5
H2
PB6
H3
VSS
H11 VDD_DREG
H12
PE2
H13
PC7
J1
PD14
J2
PD15
J3
VSS
J11
IOVDD_3
J12
PC6
J13 DECOUPLE
K1
PC0
K2
PC1
K3
IOVDD_4
K11
VSS
K12
VSS
K13
PD8
L1
PC2
Pin Alternate Functionality / Description
Analog
EBI
Timers
Communication
Other
EBI_A19 #0/1/2
PCNT1_S0IN #1
US2_TX #1
EBI_A20 #0/1/2
PCNT1_S1IN #1
US2_RX #1
Digital IO power supply 2.
EBI_A07 #0/1/2
TIM3_CC0 #1 PCNT0_S0IN #1
U0_TX #1 I2C1_SDA #2
EBI_A08 #0/1/2
TIM3_CC1 #1 PCNT0_S1IN #1
U0_RX #1 I2C1_SCL #2
BU_STAT
EBI_A10 #0
U1_RX #3
ACMP1_O #1
EBI_A21 #0/1/2
US2_CLK #1
EBI_A22 #0/1/2
US2_CS #1
Ground.
Power supply for on-chip voltage regulator.
BU_VOUT
EBI_A09 #0
TIM3_CC2 #1
U1_TX #3
ACMP0_O #1
ACMP0_CH7
EBI_A06 #0/1/2
LEU1_RX #0 I2C0_SCL #2
LES_CH7 #0 ETM_TD0 #2
I2C0_SDA #3
I2C0_SCL #3
Ground.
Digital IO power supply 3.
ACMP0_CH6
EBI_A05 #0/1/2
LEU1_TX #0 I2C0_SDA #2
LES_CH6 #0 ETM_TCLK #2
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin.
ACMP0_CH0 DAC0_OUT0ALT
#0/ OPAMP_OUT0ALT
EBI_A23 #0/1/2
TIM0_CC1 #4 PCNT0_S0IN #2
US0_TX #5 US1_TX #0 I2C0_SDA #4
LES_CH0 #0 PRS_CH2 #0
ACMP0_CH1 DAC0_OUT0ALT
#1/ OPAMP_OUT0ALT
EBI_A24 #0/1/2
TIM0_CC2 #4 PCNT0_S1IN #2
US0_RX #5 US1_RX #0 I2C0_SCL #4
LES_CH1 #0 PRS_CH3 #0
Digital IO power supply 4.
Ground.
Ground.
BU_VIN
CMU_CLK1 #1
ACMP0_CH2 DAC0_OUT0ALT
#2/ OPAMP_OUT0ALT
EBI_A25 #0/1/2
TIM0_CDTI0 #4
US2_TX #0
LES_CH2 #0
silabs.com | Building a more connected world.
Rev. 2.30 | 254
EFM32LG Data Sheet
Pin Definitions
BGA120 Pin# and Name
Pin # Pin Name
L2
PC3
L3
PA7
L4
IOVDD_5
L5
VSS
L6
VSS
L7
IOVDD_6
L8
PB9
L9
PB10
L10
PD0
L11
PD1
L12
PD4
L13
PD7
M1
PB7
M2
PC4
M3
PA8
M4
PA10
M5
PA13
M6
PA14
M7
RESETn
M8
AVSS_1
M9
AVDD_2
M10
AVDD_1
M11
AVSS_0
M12
PD3
Pin Alternate Functionality / Description
Analog
EBI
Timers
Communication
Other
ACMP0_CH3 DAC0_OUT0ALT
#3/ OPAMP_OUT0ALT
EBI_NANDREn #0/1/2
TIM0_CDTI1 #4
US2_RX #0
LES_CH3 #0
EBI_CSTFT #0/1/2
Digital IO power supply 5.
Ground.
Ground.
Digital IO power supply 6.
EBI_A03 #0/1/2
U1_TX #2
EBI_A04 #0/1/2
U1_RX #2
ADC0_CH0 DAC0_OUT0ALT
#4/ OPAMP_OUT0ALT OPAMP_OUT2 #1
PCNT2_S0IN #0
US1_TX #1
ADC0_CH1 DAC0_OUT1ALT
#4/ OPAMP_OUT1ALT
TIM0_CC0 #3 PCNT2_S1IN #0
US1_RX #1
DBG_SWO #2
ADC0_CH4 OPAMP_P2
LEU0_TX #0
ETM_TD2 #0/2
ADC0_CH7 / DAC0_N1 / OPAMP_N1
TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3
US1_TX #2 I2C0_SCL #1
CMU_CLK0 #2 LES_ALTEX1 #0
ACMP1_O #2 ETM_TCLK #0
LFXTAL_P
TIM1_CC0 #3
US0_TX #4 US1_CLK #0
ACMP0_CH4 / DAC0_P0 / OPAMP_P0
EBI_A26 #0/1/2
TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0
US2_CLK #0 I2C1_SDA #0
LES_CH4 #0
EBI_DCLK #0/1/2
TIM2_CC0 #0
EBI_VSNC #0/1/2
TIM2_CC2 #0
EBI_A01 #0/1/2
TIM2_CC1 #1
EBI_A02 #0/1/2
TIM2_CC2 #1
Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released.
Analog ground 1.
Analog power supply 2.
Analog power supply 1.
Analog ground 0.
ADC0_CH3 OPAMP_N2
TIM0_CC2 #3
US1_CS #1
ETM_TD1 #0/2
silabs.com | Building a more connected world.
Rev. 2.30 | 255
EFM32LG Data Sheet
Pin Definitions
BGA120 Pin# and Name
Pin # Pin Name
M13
PD6
N1
PB8
N2
PC5
N3
PA9
N4
PA11
N5
PA12
N6
PB11
N7
PB12
N8
AVSS_2
N9
PB13
N10
PB14
N11
AVDD_0
N12
PD2
N13
PD5
Pin Alternate Functionality / Description
Analog ADC0_CH6 / DAC0_P1 / OPAMP_P1
LFXTAL_N
ACMP0_CH5 / DAC0_N0 / OPAMP_N0
DAC0_OUT0 / OPAMP_OUT0 DAC0_OUT1 / OPAMP_OUT1 Analog ground 2.
HFXTAL_P
EBI
Timers
TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3
TIM1_CC1 #3
EBI_NANDWEn #0/1/2
LETIM0_OUT1 #3 PCNT1_S1IN #0
EBI_DTEN #0/1/2 EBI_HSNC #0/1/2
EBI_A00 #0/1/2
TIM2_CC1 #0
TIM2_CC0 #1 TIM1_CC2 #3 LE-
TIM0_OUT0 #1
LETIM0_OUT1 #1
HFXTAL_N
Analog power supply 0.
ADC0_CH2
EBI_A27 #0/1/2
ADC0_CH5 OPAMP_OUT2 #0
TIM0_CC1 #3
Communication US1_RX #2 I2C0_SDA #1 US0_RX #4 US1_CS #0 US2_CS #0 I2C1_SCL #0
I2C1_SDA #1
I2C1_SCL #1
US0_CLK #4/5 LEU0_TX #1 US0_CS #4/5 LEU0_RX #1
USB_DMPU #0 US1_CLK #1 LEU0_RX #0
Other LES_ALTEX0 #0
ACMP0_O #2 ETM_TD0 #0 LES_CH5 #0
DBG_SWO #3 ETM_TD3 #0/2
silabs.com | Building a more connected world.
Rev. 2.30 | 256
EFM32LG Data Sheet
Pin Definitions
5.11.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0.
Alternate Functionality ACMP0_CH0 ACMP0_CH1 ACMP0_CH2 ACMP0_CH3 ACMP0_CH4 ACMP0_CH5 ACMP0_CH6 ACMP0_CH7 ACMP0_O ACMP1_CH0 ACMP1_CH1 ACMP1_CH2 ACMP1_CH3 ACMP1_CH4 ACMP1_CH5 ACMP1_CH6 ACMP1_CH7 ACMP1_O ADC0_CH0
ADC0_CH1
ADC0_CH2
ADC0_CH3
ADC0_CH4
ADC0_CH5
ADC0_CH6
Table 5.32. Alternate Functionality Overview
LOCATION
0
1
2
3
4
5
6
Description
PC0
Analog comparator ACMP0, channel 0.
PC1
Analog comparator ACMP0, channel 1.
PC2
Analog comparator ACMP0, channel 2.
PC3
Analog comparator ACMP0, channel 3.
PC4
Analog comparator ACMP0, channel 4.
PC5
Analog comparator ACMP0, channel 5.
PC6
Analog comparator ACMP0, channel 6.
PC7
Analog comparator ACMP0, channel 7.
PE13 PE2 PD6
Analog comparator ACMP0, digital output.
PC8
Analog comparator ACMP1, channel 0.
PC9
Analog comparator ACMP1, channel 1.
PC10
Analog comparator ACMP1, channel 2.
PC11
Analog comparator ACMP1, channel 3.
PC12
Analog comparator ACMP1, channel 4.
PC13
Analog comparator ACMP1, channel 5.
PC14
Analog comparator ACMP1, channel 6.
PC15
Analog comparator ACMP1, channel 7.
PF2 PE3 PD7
Analog comparator ACMP1, digital output.
PD0
Analog to digital converter ADC0, input channel number 0.
PD1
Analog to digital converter ADC0, input channel number 1.
PD2
Analog to digital converter ADC0, input channel number 2.
PD3
Analog to digital converter ADC0, input channel number 3.
PD4
Analog to digital converter ADC0, input channel number 4.
PD5
Analog to digital converter ADC0, input channel number 5.
PD6
Analog to digital converter ADC0, input channel number 6.
silabs.com | Building a more connected world.
Rev. 2.30 | 257
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
ADC0_CH7
PD7
Analog to digital converter ADC0, input channel number 7.
BOOT_RX
PE11
Bootloader RX.
BOOT_TX
PE10
Bootloader TX.
BU_STAT
PE3
Backup Power Domain status, whether or not the system is in backup mode
BU_VIN
PD8
Battery input for Backup Power Domain
BU_VOUT
PE2
Power output for Backup Power Domain
CMU_CLK0
PA2 PC12 PD7
Clock Management Unit, clock output number 0.
CMU_CLK1
PA1 PD8 PE12
Clock Management Unit, clock output number 1.
DAC0_OUT0 / OPAMP_OUT0
PB11
Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0.
DAC0_OUT0ALT / OPAMP_OUT0ALT
PC0
PC1
PC2
PC3
PD0
Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0.
DAC0_OUT1 / OPAMP_OUT1
PB12
Digital to Analog Converter DAC0_OUT1 / OPAMP output channel number 1.
DAC0_OUT1ALT / OPAMP_OUT1ALT
PC12
PC13
PC14
PC15
PD1
Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1.
DBG_SWCLK
PF0 PF0 PF0 PF0
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, and has a built-in pull down.
DBG_SWDIO
PF1 PF1 PF1 PF1
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and has a built-in pull up.
DBG_SWO
PF2 PC15 PD1 PD2
Debug-interface Serial Wire viewer Output.
Note that this function is not enabled after reset, and must be enabled by software to be used.
EBI_A00
PA12 PA12 PA12
External Bus Interface (EBI) address output pin 00.
EBI_A01
PA13 PA13 PA13
External Bus Interface (EBI) address output pin 01.
EBI_A02
PA14 PA14 PA14
External Bus Interface (EBI) address output pin 02.
EBI_A03
PB9 PB9 PB9
External Bus Interface (EBI) address output pin 03.
EBI_A04
PB10 PB10 PB10
External Bus Interface (EBI) address output pin 04.
EBI_A05
PC6 PC6 PC6
External Bus Interface (EBI) address output pin 05.
EBI_A06
PC7 PC7 PC7
External Bus Interface (EBI) address output pin 06.
EBI_A07
PE0 PE0 PE0
External Bus Interface (EBI) address output pin 07.
EBI_A08
PE1 PE1 PE1
External Bus Interface (EBI) address output pin 08.
EBI_A09
PE2 PC9 PC9
External Bus Interface (EBI) address output pin 09.
EBI_A10
PE3 PC10 PC10
External Bus Interface (EBI) address output pin 10.
EBI_A11
PE4 PE4 PE4
External Bus Interface (EBI) address output pin 11.
EBI_A12
PE5 PE5 PE5
External Bus Interface (EBI) address output pin 12.
silabs.com | Building a more connected world.
Rev. 2.30 | 258
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
EBI_A13
PE6 PE6 PE6
External Bus Interface (EBI) address output pin 13.
EBI_A14
PE7 PE7 PE7
External Bus Interface (EBI) address output pin 14.
EBI_A15
PC8 PC8 PC8
External Bus Interface (EBI) address output pin 15.
EBI_A16
PB0 PB0 PB0
External Bus Interface (EBI) address output pin 16.
EBI_A17
PB1 PB1 PB1
External Bus Interface (EBI) address output pin 17.
EBI_A18
PB2 PB2 PB2
External Bus Interface (EBI) address output pin 18.
EBI_A19
PB3 PB3 PB3
External Bus Interface (EBI) address output pin 19.
EBI_A20
PB4 PB4 PB4
External Bus Interface (EBI) address output pin 20.
EBI_A21
PB5 PB5 PB5
External Bus Interface (EBI) address output pin 21.
EBI_A22
PB6 PB6 PB6
External Bus Interface (EBI) address output pin 22.
EBI_A23
PC0 PC0 PC0
External Bus Interface (EBI) address output pin 23.
EBI_A24
PC1 PC1 PC1
External Bus Interface (EBI) address output pin 24.
EBI_A25
PC2 PC2 PC2
External Bus Interface (EBI) address output pin 25.
EBI_A26
PC4 PC4 PC4
External Bus Interface (EBI) address output pin 26.
EBI_A27
PD2 PD2 PD2
External Bus Interface (EBI) address output pin 27.
EBI_AD00
PE8 PE8 PE8
External Bus Interface (EBI) address and data input / output pin 00.
EBI_AD01
PE9 PE9 PE9
External Bus Interface (EBI) address and data input / output pin 01.
EBI_AD02
PE10 PE10 PE10
External Bus Interface (EBI) address and data input / output pin 02.
EBI_AD03
PE11 PE11 PE11
External Bus Interface (EBI) address and data input / output pin 03.
EBI_AD04
PE12 PE12 PE12
External Bus Interface (EBI) address and data input / output pin 04.
EBI_AD05
PE13 PE13 PE13
External Bus Interface (EBI) address and data input / output pin 05.
EBI_AD06
PE14 PE14 PE14
External Bus Interface (EBI) address and data input / output pin 06.
EBI_AD07
PE15 PE15 PE15
External Bus Interface (EBI) address and data input / output pin 07.
EBI_AD08
PA15 PA15 PA15
External Bus Interface (EBI) address and data input / output pin 08.
EBI_AD09
PA0 PA0 PA0
External Bus Interface (EBI) address and data input / output pin 09.
EBI_AD10
PA1 PA1 PA1
External Bus Interface (EBI) address and data input / output pin 10.
EBI_AD11
PA2 PA2 PA2
External Bus Interface (EBI) address and data input / output pin 11.
EBI_AD12
PA3 PA3 PA3
External Bus Interface (EBI) address and data input / output pin 12.
silabs.com | Building a more connected world.
Rev. 2.30 | 259
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
EBI_AD13
PA4 PA4 PA4
External Bus Interface (EBI) address and data input / output pin 13.
EBI_AD14
PA5 PA5 PA5
External Bus Interface (EBI) address and data input / output pin 14.
EBI_AD15
PA6 PA6 PA6
External Bus Interface (EBI) address and data input / output pin 15.
EBI_ALE
PF3 PC11 PC11
External Bus Interface (EBI) Address Latch Enable output.
EBI_ARDY
PF2 PF2 PF2
External Bus Interface (EBI) Hardware Ready Control input.
EBI_BL0
PF6 PF6 PF6
External Bus Interface (EBI) Byte Lane/Enable pin 0.
EBI_BL1
PF7 PF7 PF7
External Bus Interface (EBI) Byte Lane/Enable pin 1.
EBI_CS0
PD9 PD9 PD9
External Bus Interface (EBI) Chip Select output 0.
EBI_CS1
PD10 PD10 PD10
External Bus Interface (EBI) Chip Select output 1.
EBI_CS2
PD11 PD11 PD11
External Bus Interface (EBI) Chip Select output 2.
EBI_CS3
PD12 PD12 PD12
External Bus Interface (EBI) Chip Select output 3.
EBI_CSTFT
PA7 PA7 PA7
External Bus Interface (EBI) Chip Select output TFT.
EBI_DCLK
PA8 PA8 PA8
External Bus Interface (EBI) TFT Dot Clock pin.
EBI_DTEN
PA9 PA9 PA9
External Bus Interface (EBI) TFT Data Enable pin.
EBI_HSNC
PA11 PA11 PA11
External Bus Interface (EBI) TFT Horizontal Synchronization pin.
EBI_NANDREn
PC3 PC3 PC3
External Bus Interface (EBI) NAND Read Enable output.
EBI_NANDWEn
PC5 PC5 PC5
External Bus Interface (EBI) NAND Write Enable output.
EBI_REn
PF5 PF9 PF5
External Bus Interface (EBI) Read Enable output.
EBI_VSNC
PA10 PA10 PA10
External Bus Interface (EBI) TFT Vertical Synchronization pin.
EBI_WEn
PF4 PF8 PF4
External Bus Interface (EBI) Write Enable output.
ETM_TCLK
PD7 PF8 PC6 PA6
Embedded Trace Module ETM clock .
ETM_TD0
PD6 PF9 PC7 PA2
Embedded Trace Module ETM data 0.
ETM_TD1
PD3 PD13 PD3 PA3
Embedded Trace Module ETM data 1.
ETM_TD2
PD4 PB15 PD4 PA4
Embedded Trace Module ETM data 2.
ETM_TD3
PD5 PF3 PD5 PA5
Embedded Trace Module ETM data 3.
GPIO_EM4WU0 PA0
Pin can be used to wake the system up from EM4
GPIO_EM4WU1 PA6
Pin can be used to wake the system up from EM4
GPIO_EM4WU2 PC9
Pin can be used to wake the system up from EM4
GPIO_EM4WU3 PF1
Pin can be used to wake the system up from EM4
silabs.com | Building a more connected world.
Rev. 2.30 | 260
Alternate Functionality GPIO_EM4WU4 GPIO_EM4WU5
HFXTAL_N
HFXTAL_P I2C0_SCL I2C0_SDA I2C1_SCL I2C1_SDA LES_ALTEX0 LES_ALTEX1 LES_ALTEX2 LES_ALTEX3 LES_ALTEX4 LES_ALTEX5 LES_ALTEX6 LES_ALTEX7 LES_CH0 LES_CH1 LES_CH2 LES_CH3 LES_CH4 LES_CH5 LES_CH6 LES_CH7 LES_CH8 LES_CH9 LES_CH10 LES_CH11 LES_CH12 LES_CH13 LES_CH14 LES_CH15 LETIM0_OUT0 LETIM0_OUT1 LEU0_RX
EFM32LG Data Sheet
Pin Definitions
LOCATION
0
1
2
3
4
5
6
Description
PF2
Pin can be used to wake the system up from EM4
PE13
Pin can be used to wake the system up from EM4
PB14
High Frequency Crystal negative pin. Also used as external optional clock input pin.
PB13
High Frequency Crystal positive pin.
PA1 PD7 PC7 PD15 PC1 PF1 PE13 I2C0 Serial Clock Line input / output.
PA0 PD6 PC6 PD14 PC0 PF0 PE12 I2C0 Serial Data input / output.
PC5 PB12 PE1
I2C1 Serial Clock Line input / output.
PC4 PB11 PE0
I2C1 Serial Data input / output.
PD6
LESENSE alternate exite output 0.
PD7
LESENSE alternate exite output 1.
PA3
LESENSE alternate exite output 2.
PA4
LESENSE alternate exite output 3.
PA5
LESENSE alternate exite output 4.
PE11
LESENSE alternate exite output 5.
PE12
LESENSE alternate exite output 6.
PE13
LESENSE alternate exite output 7.
PC0
LESENSE channel 0.
PC1
LESENSE channel 1.
PC2
LESENSE channel 2.
PC3
LESENSE channel 3.
PC4
LESENSE channel 4.
PC5
LESENSE channel 5.
PC6
LESENSE channel 6.
PC7
LESENSE channel 7.
PC8
LESENSE channel 8.
PC9
LESENSE channel 9.
PC10
LESENSE channel 10.
PC11
LESENSE channel 11.
PC12
LESENSE channel 12.
PC13
LESENSE channel 13.
PC14
LESENSE channel 14.
PC15
LESENSE channel 15.
PD6 PB11 PF0 PC4
Low Energy Timer LETIM0, output channel 0.
PD7 PB12 PF1 PC5
Low Energy Timer LETIM0, output channel 1.
PD5 PB14 PE15 PF1 PA0
LEUART0 Receive input.
silabs.com | Building a more connected world.
Rev. 2.30 | 261
Alternate Functionality
LOCATION
0
1
2
3
4
5
LEU0_TX
PD4 PB13 PE14 PF0 PF2
LEU1_RX
PC7 PA6
LEU1_TX
PC6 PA5
LFXTAL_N
PB8
LFXTAL_P
OPAMP_N0 / DAC0_N0 OPAMP_N1 / DAC0_N1 OPAMP_N2 OPAMP_OUT2 OPAMP_P0 / DAC0_P0 OPAMP_P1 / DAC0_P1 OPAMP_P2 PCNT0_S0IN PCNT0_S1IN PCNT1_S0IN PCNT1_S1IN PCNT2_S0IN PCNT2_S1IN PRS_CH0 PRS_CH1 PRS_CH2 PRS_CH3 TIM0_CC0 TIM0_CC1 TIM0_CC2
TIM0_CDTI0
TIM0_CDTI1
TIM0_CDTI2
TIM1_CC0
PB7
PC5
PD7 PD3 PD5 PD0 PC4
PD6 PD4 PC13 PE0 PC0 PD6 PC14 PE1 PC1 PD7 PC4 PB3 PC5 PB4 PD0 PE8 PD1 PE9 PA0 PF3 PA1 PF4 PC0 PF5 PC1 PE8 PA0 PA0 PF6 PD1 PA0 PF0 PA1 PA1 PF7 PD2 PC0 PF1 PA2 PA2 PF8 PD3 PC1 PF2 PA3 PC13 PF3 PC13 PC2 PF3
PA4 PC14 PF4 PC14 PC3 PF4
PA5 PC15 PF5 PC15 PC4 PF5 PC13 PE10 PB0 PB7 PD6
silabs.com | Building a more connected world.
EFM32LG Data Sheet
Pin Definitions
6
Description
LEUART0 Transmit output. Also used as receive input in half duplex communication.
LEUART1 Receive input.
LEUART1 Transmit output. Also used as receive input in half duplex communication.
Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin.
Low Frequency Crystal (typically 32.768 kHz) positive pin.
Operational Amplifier 0 external negative input.
Operational Amplifier 1 external negative input. Operational Amplifier 2 external negative input. Operational Amplifier 2 output. Operational Amplifier 0 external positive input.
Operational Amplifier 1 external positive input.
Operational Amplifier 2 external positive input. Pulse Counter PCNT0 input number 0. Pulse Counter PCNT0 input number 1. Pulse Counter PCNT1 input number 0. Pulse Counter PCNT1 input number 1. Pulse Counter PCNT2 input number 0. Pulse Counter PCNT2 input number 1. Peripheral Reflex System PRS, channel 0. Peripheral Reflex System PRS, channel 1. Peripheral Reflex System PRS, channel 2. Peripheral Reflex System PRS, channel 3. Timer 0 Capture Compare input / output channel 0. Timer 0 Capture Compare input / output channel 1. Timer 0 Capture Compare input / output channel 2. Timer 0 Complimentary Deat Time Insertion channel 0. Timer 0 Complimentary Deat Time Insertion channel 1. Timer 0 Complimentary Deat Time Insertion channel 2. Timer 1 Capture Compare input / output channel 0.
Rev. 2.30 | 262
Alternate Functionality TIM1_CC1 TIM1_CC2 TIM2_CC0 TIM2_CC1 TIM2_CC2 TIM3_CC0 TIM3_CC1 TIM3_CC2 U0_RX U0_TX U1_RX U1_TX US0_CLK US0_CS
US0_RX
US0_TX
US1_CLK US1_CS
US1_RX
US1_TX
US2_CLK US2_CS
US2_RX
LOCATION
0
1
2
3
4
5
PC14 PE11 PB1 PB8 PD7
PC15 PE12 PB2 PB11 PC13
PA8 PA12 PC8
PA9 PA13 PC9
PA10 PA14 PC10
PE14 PE0
PE15 PE1
PA15 PE2
PF7 PE1 PA4 PC15
PF6 PE0 PA3 PC14
PC13 PF11 PB10 PE3
PC12 PF10 PB9 PE2
PE12 PE5 PC9 PC15 PB13 PB13 PE13 PE4 PC8 PC14 PB14 PB14
PE11 PE6 PC10 PE12 PB8 PC1
PE10 PE7 PC11 PE13 PB7 PC0
PB7 PD2 PF0 PB8 PD3 PF1 PC1 PD1 PD6
PC0 PD0 PD7
PC4 PB5 PC5 PB6 PC3 PB4
EFM32LG Data Sheet
Pin Definitions
6
Description
Timer 1 Capture Compare input / output channel 1.
Timer 1 Capture Compare input / output channel 2.
Timer 2 Capture Compare input / output channel 0.
Timer 2 Capture Compare input / output channel 1.
Timer 2 Capture Compare input / output channel 2.
Timer 3 Capture Compare input / output channel 0.
Timer 3 Capture Compare input / output channel 1.
Timer 3 Capture Compare input / output channel 2.
UART0 Receive input.
UART0 Transmit output. Also used as receive input in half duplex communication.
UART1 Receive input.
UART1 Transmit output. Also used as receive input in half duplex communication.
USART0 clock input / output.
USART0 chip select input / output.
USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output (MISO).
USART0 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input (MOSI).
USART1 clock input / output.
USART1 chip select input / output.
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output (MISO).
USART1 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input (MOSI).
USART2 clock input / output.
USART2 chip select input / output.
USART2 Asynchronous Receive.
USART2 Synchronous mode Master Input / Slave Output (MISO).
silabs.com | Building a more connected world.
Rev. 2.30 | 263
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
US2_TX
PC2 PB3
USART2 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART2 Synchronous mode Master Output / Slave Input (MOSI).
USB_DM
PF10
USB D- pin.
USB_DMPU
PD2
USB D- Pullup control.
USB_DP
PF11
USB D+ pin.
USB_ID
PF12
USB ID pin. Used in OTG mode.
USB_VBUS
USB_ VBUS
USB 5 V VBUS input.
USB_VBUSEN
PF5
USB 5 V VBUS enable.
USB_VREGI
USB_ VREGI
USB Input to internal 3.3 V regulator
USB_VREGO
USB_ VREGO
USB Decoupling for internal 3.3 V USB regulator and regulator output
5.11.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG395 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.33. GPIO Pinout
Port
Port A Port B Port C Port D Port E Port F
Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 15 14 13 12 11 10 PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 -- -- -- PF12 PF11 PF10 PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0
silabs.com | Building a more connected world.
Rev. 2.30 | 264
5.11.4 Opamp Pinout Overview
The specific opamp terminals available in EFM32LG395 is shown in the following figure.
PC4
+ OUT0ALT
PC5
OPA0 -
OUT0
PD4
+
PD3
OPA2 -
OUT2
PD6
+ OUT1ALT
PD7
OPA1 -
OUT1
PB11 PB12 PC0 PC1 PC2 PC3 PC12 PC13 PC14 PC15 PD0 PD1 PD5
Figure 5.22. Opamp Pinout
EFM32LG Data Sheet
Pin Definitions
silabs.com | Building a more connected world.
Rev. 2.30 | 265
5.12 EFM32LG840 (QFN64)
EFM32LG Data Sheet
Pin Definitions
5.12.1 Pinout
The EFM32LG840 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question.
Figure 5.23. EFM32LG840 Pinout (top view, not to scale) Table 5.34. Device Pinout
QFN64 Pin# and Name
Pin #
Pin Name
0
VSS
Analog Ground.
1
PA0
LCD_SEG13
2
PA1
LCD_SEG14
Pin Alternate Functionality / Description
Timers
Communication
Other
TIM0_CC0 #0/1/4 TIM0_CC1 #0/1
LEU0_RX #4 I2C0_SDA #0
I2C0_SCL #0
PRS_CH0 #0 GPIO_EM4WU0
CMU_CLK1 #0 PRS_CH1 #0
silabs.com | Building a more connected world.
Rev. 2.30 | 266
EFM32LG Data Sheet
Pin Definitions
QFN64 Pin# and Name
Pin #
Pin Name
3
PA2
4
PA3
5
PA4
6
PA5
7
PA6
8
IOVDD_0
9
PB3
10
PB4
11
PB5
12
PB6
13
PC4
14
PC5
15
PB7
16
PB8
17
PA12
18
PA13
19
PA14
20
RESETn
21
PB11
22
PB12
23
AVDD_1
24
PB13
25
PB14
26
IOVDD_3
27
AVDD_0
Pin Alternate Functionality / Description
Analog
Timers
Communication
Other
LCD_SEG15
TIM0_CC2 #0/1
CMU_CLK0 #0 ETM_TD0 #3
LCD_SEG16
TIM0_CDTI0 #0
LES_ALTEX2 #0 ETM_TD1 #3
LCD_SEG17
TIM0_CDTI1 #0
LES_ALTEX3 #0 ETM_TD2 #3
LCD_SEG18
TIM0_CDTI2 #0
LEU1_TX #1
LES_ALTEX4 #0 ETM_TD3 #3
LCD_SEG19
LEU1_RX #1
ETM_TCLK #3 GPIO_EM4WU1
Digital IO power supply 0.
LCD_SEG20/ LCD_COM4
PCNT1_S0IN #1
US2_TX #1
LCD_SEG21/ LCD_COM5
PCNT1_S1IN #1
US2_RX #1
LCD_SEG22/ LCD_COM6
US2_CLK #1
LCD_SEG23/ LCD_COM7
US2_CS #1
ACMP0_CH4 / DAC0_P0 / OPAMP_P0
TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0
US2_CLK #0 I2C1_SDA #0
LES_CH4 #0
ACMP0_CH5 / DAC0_N0 / OPAMP_N0
LETIM0_OUT1 #3 PCNT1_S1IN #0
US2_CS #0 I2C1_SCL #0
LES_CH5 #0
LFXTAL_P
TIM1_CC0 #3
US0_TX #4 US1_CLK #0
LFXTAL_N
TIM1_CC1 #3
US0_RX #4 US1_CS #0
LCD_BCAP_P
TIM2_CC0 #1
LCD_BCAP_N
TIM2_CC1 #1
LCD_BEXT
TIM2_CC2 #1
Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released.
DAC0_OUT0 / OPAMP_OUT0
TIM1_CC2 #3 LETIM0_OUT0 #1
I2C1_SDA #1
DAC0_OUT1 / OPAMP_OUT1
LETIM0_OUT1 #1
I2C1_SCL #1
Analog power supply 1.
HFXTAL_P
US0_CLK #4/5 LEU0_TX #1
HFXTAL_N
US0_CS #4/5 LEU0_RX #1
Digital IO power supply 3.
Analog power supply 0.
silabs.com | Building a more connected world.
Rev. 2.30 | 267
EFM32LG Data Sheet
Pin Definitions
QFN64 Pin# and Name
Pin #
Pin Name
28
PD0
29
PD1
30
PD2
31
PD3
32
PD4
33
PD5
34
PD6
35
PD7
36
PD8
37
PC6
38
PC7
39
VDD_DREG
40
DECOUPLE
41
PE4
42
PE5
43
PE6
44
PE7
45
PC12
46
PC13
47
PC14
48
PC15
49
PF0
Pin Alternate Functionality / Description
Analog
Timers
Communication
Other
ADC0_CH0 DAC0_OUT0ALT #4/ OPAMP_OUT0ALT
OPAMP_OUT2 #1
PCNT2_S0IN #0
US1_TX #1
ADC0_CH1 DAC0_OUT1ALT #4/ OPAMP_OUT1ALT
TIM0_CC0 #3 PCNT2_S1IN #0
US1_RX #1
DBG_SWO #2
ADC0_CH2
TIM0_CC1 #3
US1_CLK #1
DBG_SWO #3
ADC0_CH3 OPAMP_N2
TIM0_CC2 #3
US1_CS #1
ETM_TD1 #0/2
ADC0_CH4 OPAMP_P2
LEU0_TX #0
ETM_TD2 #0/2
ADC0_CH5 OPAMP_OUT2 #0
LEU0_RX #0
ETM_TD3 #0/2
ADC0_CH6 / DAC0_P1 / OPAMP_P1
TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3
US1_RX #2 I2C0_SDA #1
LES_ALTEX0 #0 ACMP0_O #2 ETM_TD0 #0
ADC0_CH7 / DAC0_N1 / OPAMP_N1
TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3
US1_TX #2 I2C0_SCL #1
CMU_CLK0 #2 LES_ALTEX1 #0
ACMP1_O #2 ETM_TCLK #0
BU_VIN
CMU_CLK1 #1
ACMP0_CH6
LEU1_TX #0 I2C0_SDA #2
LES_CH6 #0 ETM_TCLK #2
ACMP0_CH7
LEU1_RX #0 I2C0_SCL LES_CH7 #0 ETM_TD0
#2
#2
Power supply for on-chip voltage regulator.
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin.
LCD_COM0
US0_CS #1
LCD_COM1
US0_CLK #1
LCD_COM2
US0_RX #1
LCD_COM3
US0_TX #1
ACMP1_CH4 DAC0_OUT1ALT #0/ OPAMP_OUT1ALT
CMU_CLK0 #1 LES_CH12 #0
ACMP1_CH5 DAC0_OUT1ALT #1/ OPAMP_OUT1ALT
TIM0_CDTI0 #1/3 TIM1_CC0 #0 TIM1_CC2 #4
PCNT0_S0IN #0
LES_CH13 #0
ACMP1_CH6 DAC0_OUT1ALT #2/ OPAMP_OUT1ALT
TIM0_CDTI1 #1/3 TIM1_CC1 #0
PCNT0_S1IN #0
US0_CS #3
LES_CH14 #0
ACMP1_CH7 DAC0_OUT1ALT #3/ OPAMP_OUT1ALT
TIM0_CDTI2 #1/3 TIM1_CC2 #0
US0_CLK #3
LES_CH15 #0 DBG_SWO #1
TIM0_CC0 #5 LETIM0_OUT0 #2
US1_CLK #2 LEU0_TX #3 I2C0_SDA #5
DBG_SWCLK #0/1/2/3
silabs.com | Building a more connected world.
Rev. 2.30 | 268
EFM32LG Data Sheet
Pin Definitions
QFN64 Pin# and Name
Pin #
Pin Name
50
PF1
51
PF2
52
PF3
53
PF4
54
PF5
55
IOVDD_5
56
PE8
57
PE9
58
PE10
59
PE11
60
PE12
61
PE13
62
PE14
63
PE15
64
PA15
Analog
LCD_SEG0
LCD_SEG1 LCD_SEG2 LCD_SEG3 Digital IO power supply 5. LCD_SEG4 LCD_SEG5 LCD_SEG6 LCD_SEG7 LCD_SEG8
LCD_SEG9 LCD_SEG10 LCD_SEG11 LCD_SEG12
Pin Alternate Functionality / Description
Timers
Communication
Other
TIM0_CC1 #5 LETIM0_OUT1 #2
US1_CS #2 LEU0_RX DBG_SWDIO #0/1/2/3
#3 I2C0_SCL #5
GPIO_EM4WU3
TIM0_CC2 #5
LEU0_TX #4
ACMP1_O #0 DBG_SWO #0 GPIO_EM4WU4
TIM0_CDTI0 #2/5
PRS_CH0 #1 ETM_TD3 #1
TIM0_CDTI1 #2/5
PRS_CH1 #1
TIM0_CDTI2 #2/5
PRS_CH2 #1
PCNT2_S0IN #1 PCNT2_S1IN #1
TIM1_CC0 #1 TIM1_CC1 #1 TIM1_CC2 #1
TIM3_CC0 #0 TIM3_CC1 #0 TIM3_CC2 #0
US0_TX #0
US0_RX #0
US0_RX #3 US0_CLK #0 I2C0_SDA #6
US0_TX #3 US0_CS #0 I2C0_SCL #6
LEU0_TX #2 LEU0_RX #2
PRS_CH3 #1
BOOT_TX LES_ALTEX5 #0
BOOT_RX CMU_CLK1 #2 LES_ALTEX6 #0 LES_ALTEX7 #0 ACMP0_O #0 GPIO_EM4WU5
silabs.com | Building a more connected world.
Rev. 2.30 | 269
EFM32LG Data Sheet
Pin Definitions
5.12.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0.
Table 5.35. Alternate Functionality Overview
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
ACMP0_CH4 PC4
Analog comparator ACMP0, channel 4.
ACMP0_CH5 PC5
Analog comparator ACMP0, channel 5.
ACMP0_CH6 PC6
Analog comparator ACMP0, channel 6.
ACMP0_CH7 PC7
Analog comparator ACMP0, channel 7.
ACMP0_O
PE13
PD6
Analog comparator ACMP0, digital output.
ACMP1_CH4 PC12
Analog comparator ACMP1, channel 4.
ACMP1_CH5 PC13
Analog comparator ACMP1, channel 5.
ACMP1_CH6 PC14
Analog comparator ACMP1, channel 6.
ACMP1_CH7 PC15
Analog comparator ACMP1, channel 7.
ACMP1_O
PF2
PD7
Analog comparator ACMP1, digital output.
ADC0_CH0
PD0
Analog to digital converter ADC0, input channel number 0.
ADC0_CH1
PD1
Analog to digital converter ADC0, input channel number 1.
ADC0_CH2
PD2
Analog to digital converter ADC0, input channel number 2.
ADC0_CH3
PD3
Analog to digital converter ADC0, input channel number 3.
ADC0_CH4
PD4
Analog to digital converter ADC0, input channel number 4.
ADC0_CH5
PD5
Analog to digital converter ADC0, input channel number 5.
ADC0_CH6
PD6
Analog to digital converter ADC0, input channel number 6.
ADC0_CH7
PD7
Analog to digital converter ADC0, input channel number 7.
BOOT_RX
PE11
Bootloader RX.
BOOT_TX
PE10
Bootloader TX.
BU_VIN
PD8
Battery input for Backup Power Domain
CMU_CLK0
PA2 PC12 PD7
Clock Management Unit, clock output number 0.
CMU_CLK1
PA1 PD8 PE12
Clock Management Unit, clock output number 1.
DAC0_OUT0 / OPAMP_OUT0
PB11
Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0.
silabs.com | Building a more connected world.
Rev. 2.30 | 270
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
DAC0_OUT0ALT / OPAMP_OUT0A LT
PD0
Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0.
DAC0_OUT1 / OPAMP_OUT1
PB12
Digital to Analog Converter DAC0_OUT1 / OPAMP output channel number 1.
DAC0_OUT1ALT / OPAMP_OUT1A PC12 PC13 PC14 PC15 PD1 LT
Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1.
DBG_SWCLK PF0 PF0 PF0 PF0
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, and has a built-in pull down.
DBG_SWDIO PF1 PF1 PF1 PF1
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and has a built-in pull up.
DBG_SWO
PF2 PC15 PD1 PD2
Debug-interface Serial Wire viewer Output.
Note that this function is not enabled after reset, and must be enabled by software to be used.
ETM_TCLK
PD7
PC6 PA6
Embedded Trace Module ETM clock .
ETM_TD0
PD6
PC7 PA2
Embedded Trace Module ETM data 0.
ETM_TD1
PD3
PD3 PA3
Embedded Trace Module ETM data 1.
ETM_TD2
PD4
PD4 PA4
Embedded Trace Module ETM data 2.
ETM_TD3
PD5 PF3 PD5 PA5
Embedded Trace Module ETM data 3.
GPIO_EM4WU0 PA0
Pin can be used to wake the system up from EM4
GPIO_EM4WU1 PA6
Pin can be used to wake the system up from EM4
GPIO_EM4WU3 PF1
Pin can be used to wake the system up from EM4
GPIO_EM4WU4 PF2
Pin can be used to wake the system up from EM4
GPIO_EM4WU5 PE13
Pin can be used to wake the system up from EM4
HFXTAL_N
PB14
High Frequency Crystal negative pin. Also used as external optional clock input pin.
HFXTAL_P
PB13
High Frequency Crystal positive pin.
I2C0_SCL
PA1 PD7 PC7
PF1 PE13 I2C0 Serial Clock Line input / output.
I2C0_SDA
PA0 PD6 PC6
PF0 PE12 I2C0 Serial Data input / output.
I2C1_SCL
PC5 PB12
I2C1 Serial Clock Line input / output.
I2C1_SDA
PC4 PB11
I2C1 Serial Data input / output.
LCD_BCAP_N PA13
LCD voltage booster (optional), boost capacitor, negative pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P.
LCD_BCAP_P PA12
LCD voltage booster (optional), boost capacitor, positive pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P.
silabs.com | Building a more connected world.
Rev. 2.30 | 271
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
LCD voltage booster (optional), boost output. If using the LCD voltage booster, connect a 1 uF capacitor between this pin and VSS.
LCD_BEXT
PA14
An external LCD voltage may also be applied to this pin if the booster is not enabled.
If AVDD is used directly as the LCD supply voltage, this pin may be left unconnected or used as a GPIO.
LCD_COM0
PE4
LCD driver common line number 0.
LCD_COM1
PE5
LCD driver common line number 1.
LCD_COM2
PE6
LCD driver common line number 2.
LCD_COM3
PE7
LCD driver common line number 3.
LCD_SEG0
PF2
LCD segment line 0. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
LCD_SEG1
PF3
LCD segment line 1. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
LCD_SEG2
PF4
LCD segment line 2. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
LCD_SEG3
PF5
LCD segment line 3. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
LCD_SEG4
PE8
LCD segment line 4. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
LCD_SEG5
PE9
LCD segment line 5. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
LCD_SEG6
PE10
LCD segment line 6. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
LCD_SEG7
PE11
LCD segment line 7. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
LCD_SEG8
PE12
LCD segment line 8. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG9
PE13
LCD segment line 9. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG10
PE14
LCD segment line 10. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG11
PE15
LCD segment line 11. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG12
PA15
LCD segment line 12. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG13
PA0
LCD segment line 13. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG14
PA1
LCD segment line 14. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG15
PA2
LCD segment line 15. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG16
PA3
LCD segment line 16. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
silabs.com | Building a more connected world.
Rev. 2.30 | 272
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
LCD_SEG17
PA4
LCD segment line 17. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG18
PA5
LCD segment line 18. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG19
PA6
LCD segment line 19. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG20/ LCD_COM4
PB3
LCD segment line 20. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 4
LCD_SEG21/ LCD_COM5
PB4
LCD segment line 21. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 5
LCD_SEG22/ LCD_COM6
PB5
LCD segment line 22. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 6
LCD_SEG23/ LCD_COM7
PB6
LCD segment line 23. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 7
LES_ALTEX0 PD6
LESENSE alternate exite output 0.
LES_ALTEX1 PD7
LESENSE alternate exite output 1.
LES_ALTEX2 PA3
LESENSE alternate exite output 2.
LES_ALTEX3 PA4
LESENSE alternate exite output 3.
LES_ALTEX4 PA5
LESENSE alternate exite output 4.
LES_ALTEX5 PE11
LESENSE alternate exite output 5.
LES_ALTEX6 PE12
LESENSE alternate exite output 6.
LES_ALTEX7 PE13
LESENSE alternate exite output 7.
LES_CH4
PC4
LESENSE channel 4.
LES_CH5
PC5
LESENSE channel 5.
LES_CH6
PC6
LESENSE channel 6.
LES_CH7
PC7
LESENSE channel 7.
LES_CH12
PC12
LESENSE channel 12.
LES_CH13
PC13
LESENSE channel 13.
LES_CH14
PC14
LESENSE channel 14.
LES_CH15
PC15
LESENSE channel 15.
LETIM0_OUT0 PD6 PB11 PF0 PC4
Low Energy Timer LETIM0, output channel 0.
LETIM0_OUT1 PD7 PB12 PF1 PC5
Low Energy Timer LETIM0, output channel 1.
LEU0_RX
PD5 PB14 PE15 PF1 PA0
LEUART0 Receive input.
LEU0_TX
PD4 PB13 PE14 PF0 PF2
LEUART0 Transmit output. Also used as receive input in half duplex communication.
LEU1_RX
PC7 PA6
LEUART1 Receive input.
silabs.com | Building a more connected world.
Rev. 2.30 | 273
Alternate
LOCATION
Functionality
0
1
2
3
4
5
LEU1_TX
PC6 PA5
LFXTAL_N
PB8
LFXTAL_P
PB7
OPAMP_N0 / DAC0_N0
PC5
OPAMP_N1 / DAC0_N1
PD7
OPAMP_N2
PD3
OPAMP_OUT2 PD5 PD0
OPAMP_P0 / DAC0_P0
PC4
OPAMP_P1 / DAC0_P1
PD6
OPAMP_P2
PD4
PCNT0_S0IN PC13
PCNT0_S1IN PC14
PCNT1_S0IN PC4 PB3
PCNT1_S1IN PC5 PB4
PCNT2_S0IN PD0 PE8
PCNT2_S1IN PD1 PE9
PRS_CH0
PA0 PF3
PRS_CH1
PA1 PF4
PRS_CH2
PF5
PRS_CH3
PE8
TIM0_CC0
PA0 PA0
TIM0_CC1
PA1 PA1
TIM0_CC2
PA2 PA2
PD6 PD7
PD1 PA0 PF0
PD2
PF1
PD3
PF2
TIM0_CDTI0
PA3 PC13 PF3 PC13
PF3
TIM0_CDTI1
PA4 PC14 PF4 PC14
PF4
TIM0_CDTI2
PA5 PC15 PF5 PC15 PC4 PF5
TIM1_CC0 TIM1_CC1 TIM1_CC2 TIM2_CC0
PC13 PC14 PC15
PE10 PE11 PE12 PA12
PB7 PB8 PB11
PD6 PD7 PC13
silabs.com | Building a more connected world.
EFM32LG Data Sheet
Pin Definitions
6
Description
LEUART1 Transmit output. Also used as receive input in half duplex communication.
Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin.
Low Frequency Crystal (typically 32.768 kHz) positive pin.
Operational Amplifier 0 external negative input.
Operational Amplifier 1 external negative input. Operational Amplifier 2 external negative input. Operational Amplifier 2 output. Operational Amplifier 0 external positive input.
Operational Amplifier 1 external positive input.
Operational Amplifier 2 external positive input. Pulse Counter PCNT0 input number 0. Pulse Counter PCNT0 input number 1. Pulse Counter PCNT1 input number 0. Pulse Counter PCNT1 input number 1. Pulse Counter PCNT2 input number 0. Pulse Counter PCNT2 input number 1. Peripheral Reflex System PRS, channel 0. Peripheral Reflex System PRS, channel 1. Peripheral Reflex System PRS, channel 2. Peripheral Reflex System PRS, channel 3. Timer 0 Capture Compare input / output channel 0. Timer 0 Capture Compare input / output channel 1. Timer 0 Capture Compare input / output channel 2. Timer 0 Complimentary Deat Time Insertion channel 0. Timer 0 Complimentary Deat Time Insertion channel 1. Timer 0 Complimentary Deat Time Insertion channel 2. Timer 1 Capture Compare input / output channel 0. Timer 1 Capture Compare input / output channel 1. Timer 1 Capture Compare input / output channel 2. Timer 2 Capture Compare input / output channel 0.
Rev. 2.30 | 274
Alternate Functionality TIM2_CC1 TIM2_CC2 TIM3_CC0 TIM3_CC1 TIM3_CC2 US0_CLK US0_CS
0
PE14 PE15 PA15 PE12 PE13
1 PA13 PA14
PE5 PE4
LOCATION
2
3
4
5
PC15 PB13 PB13 PC14 PB14 PB14
US0_RX
PE11 PE6
PE12 PB8
US0_TX
US1_CLK US1_CS US1_RX
PE10 PE7
PE13 PB7
PB7 PD2 PF0 PB8 PD3 PF1
PD1 PD6
US1_TX
US2_CLK US2_CS US2_RX
PD0 PD7
PC4 PB5 PC5 PB6
PB4
US2_TX
PB3
EFM32LG Data Sheet
Pin Definitions
6
Description
Timer 2 Capture Compare input / output channel 1.
Timer 2 Capture Compare input / output channel 2.
Timer 3 Capture Compare input / output channel 0.
Timer 3 Capture Compare input / output channel 1.
Timer 3 Capture Compare input / output channel 2.
USART0 clock input / output.
USART0 chip select input / output.
USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output (MISO).
USART0 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input (MOSI).
USART1 clock input / output.
USART1 chip select input / output.
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output (MISO).
USART1 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input (MOSI).
USART2 clock input / output.
USART2 chip select input / output.
USART2 Asynchronous Receive.
USART2 Synchronous mode Master Input / Slave Output (MISO).
USART2 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART2 Synchronous mode Master Output / Slave Input (MOSI).
silabs.com | Building a more connected world.
Rev. 2.30 | 275
EFM32LG Data Sheet
Pin Definitions
5.12.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG840 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.36. GPIO Pinout
Port
Port A Port B Port C Port D Port E Port F
Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 15 14 13 12 11 10 PA15 PA14 PA13 PA12 -- -- -- -- -- PA6 PA5 PA4 PA3 PA2 PA1 PA0 -- PB14 PB13 PB12 PB11 -- -- PB8 PB7 PB6 PB5 PB4 PB3 -- -- -- PC15 PC14 PC13 PC12 -- -- -- -- PC7 PC6 PC5 PC4 -- -- -- -- -- -- -- -- -- -- -- PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- PF5 PF4 PF3 PF2 PF1 PF0
5.12.4 Opamp Pinout Overview
The specific opamp terminals available in EFM32LG840 is shown in the following figure.
PC4
+ OUT0ALT
OPA0 OUT0
PC5
-
PD4
+
PD3
OPA2 -
OUT2
PD6
+ OUT1ALT
PD7
OPA1 -
OUT1
PB11 PB12
PC12 PC13 PC14 PC15 PD0 PD1 PD5
Figure 5.24. Opamp Pinout
silabs.com | Building a more connected world.
Rev. 2.30 | 276
5.13 EFM32LG842 (TQFP64)
EFM32LG Data Sheet
Pin Definitions
5.13.1 Pinout
The EFM32LG842 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question.
Figure 5.25. EFM32LG842 Pinout (top view, not to scale) Table 5.37. Device Pinout
QFP64 Pin# and Name
Pin #
Pin Name
1
PA0
2
PA1
3
PA2
Analog LCD_SEG13 LCD_SEG14 LCD_SEG15
Pin Alternate Functionality / Description
Timers
Communication
TIM0_CC0 #0/1/4
LEU0_RX #4 I2C0_SDA #0
TIM0_CC1 #0/1
I2C0_SCL #0
TIM0_CC2 #0/1
Other
PRS_CH0 #0 GPIO_EM4WU0
CMU_CLK1 #0 PRS_CH1 #0
CMU_CLK0 #0 ETM_TD0 #3
silabs.com | Building a more connected world.
Rev. 2.30 | 277
EFM32LG Data Sheet
Pin Definitions
QFP64 Pin# and Name
Pin #
Pin Name
4
PA3
5
PA4
6
PA5
7
IOVDD_0
8
VSS
9
PB3
10
PB4
11
PB5
12
PB6
13
PC4
14
PC5
15
PB7
16
PB8
17
PA12
18
PA13
19
PA14
20
RESETn
21
PB11
22
VSS
23
AVDD_1
24
PB13
25
PB14
26
IOVDD_3
27
AVDD_0
28
PD0
Pin Alternate Functionality / Description
Analog
Timers
Communication
Other
LCD_SEG16
TIM0_CDTI0 #0
LES_ALTEX2 #0 ETM_TD1 #3
LCD_SEG17
TIM0_CDTI1 #0
LES_ALTEX3 #0 ETM_TD2 #3
LCD_SEG18
TIM0_CDTI2 #0
LEU1_TX #1
LES_ALTEX4 #0 ETM_TD3 #3
Digital IO power supply 0.
Ground.
LCD_SEG20/ LCD_COM4
PCNT1_S0IN #1
US2_TX #1
LCD_SEG21/ LCD_COM5
PCNT1_S1IN #1
US2_RX #1
LCD_SEG22/ LCD_COM6
US2_CLK #1
LCD_SEG23/ LCD_COM7
US2_CS #1
ACMP0_CH4 / DAC0_P0 / OPAMP_P0
TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0
US2_CLK #0 I2C1_SDA #0
LES_CH4 #0
ACMP0_CH5 / DAC0_N0 / OPAMP_N0
LETIM0_OUT1 #3 PCNT1_S1IN #0
US2_CS #0 I2C1_SCL #0
LES_CH5 #0
LFXTAL_P
TIM1_CC0 #3
US0_TX #4 US1_CLK #0
LFXTAL_N
TIM1_CC1 #3
US0_RX #4 US1_CS #0
LCD_BCAP_P
TIM2_CC0 #1
LCD_BCAP_N
TIM2_CC1 #1
LCD_BEXT
TIM2_CC2 #1
Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released.
DAC0_OUT0 / OPAMP_OUT0
TIM1_CC2 #3 LETIM0_OUT0 #1
I2C1_SDA #1
Ground.
Analog power supply 1.
HFXTAL_P
US0_CLK #4/5 LEU0_TX #1
HFXTAL_N
US0_CS #4/5 LEU0_RX #1
Digital IO power supply 3.
Analog power supply 0.
ADC0_CH0 DAC0_OUT0ALT #4/ OPAMP_OUT0ALT
OPAMP_OUT2 #1
PCNT2_S0IN #0
US1_TX #1
silabs.com | Building a more connected world.
Rev. 2.30 | 278
EFM32LG Data Sheet
Pin Definitions
QFP64 Pin# and Name
Pin #
Pin Name
29
PD1
30
PD2
31
PD3
32
PD4
33
PD5
34
PD6
35
PD7
36
PD8
37
PC6
38
PC7
39
VDD_DREG
40
DECOUPLE
41
PE4
42
PE5
43
PE6
44
PE7
45
PC12
46
PC13
47
PC14
48
PC15
49
PF0
50
PF1
Pin Alternate Functionality / Description
Analog
Timers
Communication
Other
ADC0_CH1 DAC0_OUT1ALT #4/ OPAMP_OUT1ALT
TIM0_CC0 #3 PCNT2_S1IN #0
US1_RX #1
DBG_SWO #2
ADC0_CH2
TIM0_CC1 #3
US1_CLK #1
DBG_SWO #3
ADC0_CH3 OPAMP_N2
TIM0_CC2 #3
US1_CS #1
ETM_TD1 #0/2
ADC0_CH4 OPAMP_P2
LEU0_TX #0
ETM_TD2 #0/2
ADC0_CH5 OPAMP_OUT2 #0
LEU0_RX #0
ETM_TD3 #0/2
ADC0_CH6 / DAC0_P1 / OPAMP_P1
TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3
US1_RX #2 I2C0_SDA #1
LES_ALTEX0 #0 ACMP0_O #2 ETM_TD0 #0
ADC0_CH7 / DAC0_N1 / OPAMP_N1
TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3
US1_TX #2 I2C0_SCL #1
CMU_CLK0 #2 LES_ALTEX1 #0
ACMP1_O #2 ETM_TCLK #0
BU_VIN
CMU_CLK1 #1
ACMP0_CH6
LEU1_TX #0 I2C0_SDA #2
LES_CH6 #0 ETM_TCLK #2
ACMP0_CH7
LEU1_RX #0 I2C0_SCL LES_CH7 #0 ETM_TD0
#2
#2
Power supply for on-chip voltage regulator.
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin.
LCD_COM0
US0_CS #1
LCD_COM1
US0_CLK #1
LCD_COM2
US0_RX #1
LCD_COM3
US0_TX #1
ACMP1_CH4 DAC0_OUT1ALT #0/ OPAMP_OUT1ALT
CMU_CLK0 #1 LES_CH12 #0
ACMP1_CH5 DAC0_OUT1ALT #1/ OPAMP_OUT1ALT
TIM0_CDTI0 #1/3 TIM1_CC0 #0 TIM1_CC2 #4
PCNT0_S0IN #0
LES_CH13 #0
ACMP1_CH6 DAC0_OUT1ALT #2/ OPAMP_OUT1ALT
TIM0_CDTI1 #1/3 TIM1_CC1 #0
PCNT0_S1IN #0
US0_CS #3
LES_CH14 #0
ACMP1_CH7 DAC0_OUT1ALT #3/ OPAMP_OUT1ALT
TIM0_CDTI2 #1/3 TIM1_CC2 #0
US0_CLK #3
LES_CH15 #0 DBG_SWO #1
TIM0_CC0 #5 LETIM0_OUT0 #2
US1_CLK #2 LEU0_TX #3 I2C0_SDA #5
DBG_SWCLK #0/1/2/3
TIM0_CC1 #5 LETIM0_OUT1 #2
US1_CS #2 LEU0_RX DBG_SWDIO #0/1/2/3
#3 I2C0_SCL #5
GPIO_EM4WU3
silabs.com | Building a more connected world.
Rev. 2.30 | 279
EFM32LG Data Sheet
Pin Definitions
QFP64 Pin# and Name
Pin #
Pin Name
51
PF2
52
PF3
53
PF4
54
PF5
55
IOVDD_5
56
VSS
57
PE8
58
PE9
59
PE10
60
PE11
61
PE12
62
PE13
63
PE14
64
PE15
Analog
LCD_SEG0
LCD_SEG1 LCD_SEG2 LCD_SEG3 Digital IO power supply 5. Ground. LCD_SEG4 LCD_SEG5 LCD_SEG6 LCD_SEG7
LCD_SEG8
LCD_SEG9
LCD_SEG10 LCD_SEG11
Pin Alternate Functionality / Description
Timers
Communication
TIM0_CC2 #5
LEU0_TX #4
TIM0_CDTI0 #2/5 TIM0_CDTI1 #2/5 TIM0_CDTI2 #2/5
Other
ACMP1_O #0 DBG_SWO #0 GPIO_EM4WU4
PRS_CH0 #1 ETM_TD3 #1
PRS_CH1 #1
PRS_CH2 #1
PCNT2_S0IN #1 PCNT2_S1IN #1
TIM1_CC0 #1 TIM1_CC1 #1 TIM1_CC2 #1
TIM3_CC0 #0 TIM3_CC1 #0
US0_TX #0
US0_RX #0
US0_RX #3 US0_CLK #0 I2C0_SDA #6
US0_TX #3 US0_CS #0 I2C0_SCL #6
LEU0_TX #2 LEU0_RX #2
PRS_CH3 #1
BOOT_TX LES_ALTEX5 #0
BOOT_RX CMU_CLK1 #2 LES_ALTEX6 #0 LES_ALTEX7 #0 ACMP0_O #0 GPIO_EM4WU5
silabs.com | Building a more connected world.
Rev. 2.30 | 280
EFM32LG Data Sheet
Pin Definitions
5.13.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0.
Table 5.38. Alternate Functionality Overview
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
ACMP0_CH4 PC4
Analog comparator ACMP0, channel 4.
ACMP0_CH5 PC5
Analog comparator ACMP0, channel 5.
ACMP0_CH6 PC6
Analog comparator ACMP0, channel 6.
ACMP0_CH7 PC7
Analog comparator ACMP0, channel 7.
ACMP0_O
PE13
PD6
Analog comparator ACMP0, digital output.
ACMP1_CH4 PC12
Analog comparator ACMP1, channel 4.
ACMP1_CH5 PC13
Analog comparator ACMP1, channel 5.
ACMP1_CH6 PC14
Analog comparator ACMP1, channel 6.
ACMP1_CH7 PC15
Analog comparator ACMP1, channel 7.
ACMP1_O
PF2
PD7
Analog comparator ACMP1, digital output.
ADC0_CH0
PD0
Analog to digital converter ADC0, input channel number 0.
ADC0_CH1
PD1
Analog to digital converter ADC0, input channel number 1.
ADC0_CH2
PD2
Analog to digital converter ADC0, input channel number 2.
ADC0_CH3
PD3
Analog to digital converter ADC0, input channel number 3.
ADC0_CH4
PD4
Analog to digital converter ADC0, input channel number 4.
ADC0_CH5
PD5
Analog to digital converter ADC0, input channel number 5.
ADC0_CH6
PD6
Analog to digital converter ADC0, input channel number 6.
ADC0_CH7
PD7
Analog to digital converter ADC0, input channel number 7.
BOOT_RX
PE11
Bootloader RX.
BOOT_TX
PE10
Bootloader TX.
BU_VIN
PD8
Battery input for Backup Power Domain
CMU_CLK0
PA2 PC12 PD7
Clock Management Unit, clock output number 0.
CMU_CLK1
PA1 PD8 PE12
Clock Management Unit, clock output number 1.
DAC0_OUT0 / OPAMP_OUT0
PB11
Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0.
silabs.com | Building a more connected world.
Rev. 2.30 | 281
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
DAC0_OUT0ALT / OPAMP_OUT0A LT
PD0
Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0.
DAC0_OUT1ALT / OPAMP_OUT1A PC12 PC13 PC14 PC15 PD1 LT
Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1.
DBG_SWCLK PF0 PF0 PF0 PF0
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, and has a built-in pull down.
DBG_SWDIO PF1 PF1 PF1 PF1
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and has a built-in pull up.
DBG_SWO
PF2 PC15 PD1 PD2
Debug-interface Serial Wire viewer Output.
Note that this function is not enabled after reset, and must be enabled by software to be used.
ETM_TCLK
PD7
PC6
Embedded Trace Module ETM clock .
ETM_TD0
PD6
PC7 PA2
Embedded Trace Module ETM data 0.
ETM_TD1
PD3
PD3 PA3
Embedded Trace Module ETM data 1.
ETM_TD2
PD4
PD4 PA4
Embedded Trace Module ETM data 2.
ETM_TD3
PD5 PF3 PD5 PA5
Embedded Trace Module ETM data 3.
GPIO_EM4WU0 PA0
Pin can be used to wake the system up from EM4
GPIO_EM4WU3 PF1
Pin can be used to wake the system up from EM4
GPIO_EM4WU4 PF2
Pin can be used to wake the system up from EM4
GPIO_EM4WU5 PE13
Pin can be used to wake the system up from EM4
HFXTAL_N
PB14
High Frequency Crystal negative pin. Also used as external optional clock input pin.
HFXTAL_P
PB13
High Frequency Crystal positive pin.
I2C0_SCL
PA1 PD7 PC7
PF1 PE13 I2C0 Serial Clock Line input / output.
I2C0_SDA
PA0 PD6 PC6
PF0 PE12 I2C0 Serial Data input / output.
I2C1_SCL
PC5
I2C1 Serial Clock Line input / output.
I2C1_SDA
PC4
I2C1 Serial Data input / output.
LCD_BCAP_N PA13
LCD voltage booster (optional), boost capacitor, negative pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P.
LCD_BCAP_P PA12
LCD voltage booster (optional), boost capacitor, positive pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P.
silabs.com | Building a more connected world.
Rev. 2.30 | 282
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
LCD voltage booster (optional), boost output. If using the LCD voltage booster, connect a 1 uF capacitor between this pin and VSS.
LCD_BEXT
PA14
An external LCD voltage may also be applied to this pin if the booster is not enabled.
If AVDD is used directly as the LCD supply voltage, this pin may be left unconnected or used as a GPIO.
LCD_COM0
PE4
LCD driver common line number 0.
LCD_COM1
PE5
LCD driver common line number 1.
LCD_COM2
PE6
LCD driver common line number 2.
LCD_COM3
PE7
LCD driver common line number 3.
LCD_SEG0
PF2
LCD segment line 0. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
LCD_SEG1
PF3
LCD segment line 1. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
LCD_SEG2
PF4
LCD segment line 2. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
LCD_SEG3
PF5
LCD segment line 3. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
LCD_SEG4
PE8
LCD segment line 4. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
LCD_SEG5
PE9
LCD segment line 5. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
LCD_SEG6
PE10
LCD segment line 6. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
LCD_SEG7
PE11
LCD segment line 7. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
LCD_SEG8
PE12
LCD segment line 8. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG9
PE13
LCD segment line 9. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG10
PE14
LCD segment line 10. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG11
PE15
LCD segment line 11. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG13
PA0
LCD segment line 13. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG14
PA1
LCD segment line 14. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG15
PA2
LCD segment line 15. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG16
PA3
LCD segment line 16. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG17
PA4
LCD segment line 17. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
silabs.com | Building a more connected world.
Rev. 2.30 | 283
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
LCD_SEG18
PA5
LCD segment line 18. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG20/ LCD_COM4
PB3
LCD segment line 20. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 4
LCD_SEG21/ LCD_COM5
PB4
LCD segment line 21. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 5
LCD_SEG22/ LCD_COM6
PB5
LCD segment line 22. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 6
LCD_SEG23/ LCD_COM7
PB6
LCD segment line 23. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 7
LES_ALTEX0 PD6
LESENSE alternate exite output 0.
LES_ALTEX1 PD7
LESENSE alternate exite output 1.
LES_ALTEX2 PA3
LESENSE alternate exite output 2.
LES_ALTEX3 PA4
LESENSE alternate exite output 3.
LES_ALTEX4 PA5
LESENSE alternate exite output 4.
LES_ALTEX5 PE11
LESENSE alternate exite output 5.
LES_ALTEX6 PE12
LESENSE alternate exite output 6.
LES_ALTEX7 PE13
LESENSE alternate exite output 7.
LES_CH4
PC4
LESENSE channel 4.
LES_CH5
PC5
LESENSE channel 5.
LES_CH6
PC6
LESENSE channel 6.
LES_CH7
PC7
LESENSE channel 7.
LES_CH12
PC12
LESENSE channel 12.
LES_CH13
PC13
LESENSE channel 13.
LES_CH14
PC14
LESENSE channel 14.
LES_CH15
PC15
LESENSE channel 15.
LETIM0_OUT0 PD6 PB11 PF0 PC4
Low Energy Timer LETIM0, output channel 0.
LETIM0_OUT1 PD7
PF1 PC5
Low Energy Timer LETIM0, output channel 1.
LEU0_RX
PD5 PB14 PE15 PF1 PA0
LEUART0 Receive input.
LEU0_TX
PD4 PB13 PE14 PF0 PF2
LEUART0 Transmit output. Also used as receive input in half duplex communication.
LEU1_RX
PC7
LEUART1 Receive input.
LEU1_TX
PC6 PA5
LEUART1 Transmit output. Also used as receive input in half duplex communication.
LFXTAL_N
PB8
Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin.
silabs.com | Building a more connected world.
Rev. 2.30 | 284
Alternate
LOCATION
Functionality
0
1
2
3
4
5
LFXTAL_P
PB7
OPAMP_N0 / DAC0_N0
PC5
OPAMP_N1 / DAC0_N1
PD7
OPAMP_N2
PD3
OPAMP_OUT2 PD5 PD0
OPAMP_P0 / DAC0_P0
PC4
OPAMP_P1 / DAC0_P1
PD6
OPAMP_P2
PD4
PCNT0_S0IN PC13
PCNT0_S1IN PC14
PCNT1_S0IN PC4 PB3
PCNT1_S1IN PC5 PB4
PCNT2_S0IN PD0 PE8
PCNT2_S1IN PD1 PE9
PRS_CH0
PA0 PF3
PRS_CH1
PA1 PF4
PRS_CH2
PF5
PRS_CH3
PE8
TIM0_CC0
PA0 PA0
TIM0_CC1
PA1 PA1
TIM0_CC2
PA2 PA2
PD6 PD7
PD1 PA0 PF0
PD2
PF1
PD3
PF2
TIM0_CDTI0
PA3 PC13 PF3 PC13
PF3
TIM0_CDTI1
PA4 PC14 PF4 PC14
PF4
TIM0_CDTI2
TIM1_CC0 TIM1_CC1 TIM1_CC2 TIM2_CC0 TIM2_CC1 TIM2_CC2 TIM3_CC0
PA5 PC15 PF5
PC13 PC14 PC15
PE14
PE10 PE11 PE12 PA12 PA13 PA14
PC15 PC4 PF5
PB7 PB8 PB11
PD6 PD7 PC13
EFM32LG Data Sheet
Pin Definitions
6
Description
Low Frequency Crystal (typically 32.768 kHz) positive pin.
Operational Amplifier 0 external negative input.
Operational Amplifier 1 external negative input. Operational Amplifier 2 external negative input. Operational Amplifier 2 output. Operational Amplifier 0 external positive input.
Operational Amplifier 1 external positive input.
Operational Amplifier 2 external positive input. Pulse Counter PCNT0 input number 0. Pulse Counter PCNT0 input number 1. Pulse Counter PCNT1 input number 0. Pulse Counter PCNT1 input number 1. Pulse Counter PCNT2 input number 0. Pulse Counter PCNT2 input number 1. Peripheral Reflex System PRS, channel 0. Peripheral Reflex System PRS, channel 1. Peripheral Reflex System PRS, channel 2. Peripheral Reflex System PRS, channel 3. Timer 0 Capture Compare input / output channel 0. Timer 0 Capture Compare input / output channel 1. Timer 0 Capture Compare input / output channel 2. Timer 0 Complimentary Deat Time Insertion channel 0. Timer 0 Complimentary Deat Time Insertion channel 1. Timer 0 Complimentary Deat Time Insertion channel 2. Timer 1 Capture Compare input / output channel 0. Timer 1 Capture Compare input / output channel 1. Timer 1 Capture Compare input / output channel 2. Timer 2 Capture Compare input / output channel 0. Timer 2 Capture Compare input / output channel 1. Timer 2 Capture Compare input / output channel 2. Timer 3 Capture Compare input / output channel 0.
silabs.com | Building a more connected world.
Rev. 2.30 | 285
Alternate Functionality TIM3_CC1 US0_CLK US0_CS
0
1
PE15
PE12 PE5
PE13 PE4
US0_RX
PE11 PE6
LOCATION
2
3
4
5
PC15 PB13 PB13 PC14 PB14 PB14
PE12 PB8
US0_TX
US1_CLK US1_CS US1_RX
PE10 PE7
PE13 PB7
PB7 PD2 PF0 PB8 PD3 PF1
PD1 PD6
US1_TX
US2_CLK US2_CS US2_RX
PD0 PD7
PC4 PB5 PC5 PB6
PB4
US2_TX
PB3
EFM32LG Data Sheet
Pin Definitions
6
Description
Timer 3 Capture Compare input / output channel 1.
USART0 clock input / output.
USART0 chip select input / output.
USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output (MISO).
USART0 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input (MOSI).
USART1 clock input / output.
USART1 chip select input / output.
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output (MISO).
USART1 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input (MOSI).
USART2 clock input / output.
USART2 chip select input / output.
USART2 Asynchronous Receive.
USART2 Synchronous mode Master Input / Slave Output (MISO).
USART2 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART2 Synchronous mode Master Output / Slave Input (MOSI).
silabs.com | Building a more connected world.
Rev. 2.30 | 286
EFM32LG Data Sheet
Pin Definitions
5.13.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG842 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.39. GPIO Pinout
Port
Port A Port B Port C Port D Port E Port F
Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 15 14 13 12 11 10 -- PA14 PA13 PA12 -- -- -- -- -- -- PA5 PA4 PA3 PA2 PA1 PA0 -- PB14 PB13 -- PB11 -- -- PB8 PB7 PB6 PB5 PB4 PB3 -- -- -- PC15 PC14 PC13 PC12 -- -- -- -- PC7 PC6 PC5 PC4 -- -- -- -- -- -- -- -- -- -- -- PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- PF5 PF4 PF3 PF2 PF1 PF0
5.13.4 Opamp Pinout Overview
The specific opamp terminals available in EFM32LG842 is shown in the following figure.
PC4
+ OUT0ALT
OPA0 OUT0
PC5
-
PD4
+
PD3
OPA2 -
OUT2
PD6
+ OUT1ALT
PD7
OPA1 -
OUT1
PB11
PC12 PC13 PC14 PC15 PD0 PD1 PD5
Figure 5.26. Opamp Pinout
silabs.com | Building a more connected world.
Rev. 2.30 | 287
5.14 EFM32LG880 (LQFP100)
EFM32LG Data Sheet
Pin Definitions
5.14.1 Pinout
The EFM32LG880 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question.
Figure 5.27. EFM32LG880 Pinout (top view, not to scale)
silabs.com | Building a more connected world.
Rev. 2.30 | 288
EFM32LG Data Sheet
Pin Definitions
Table 5.40. Device Pinout
LQFP100 Pin# and Name
Pin # Pin Name
1
PA0
2
PA1
Analog LCD_SEG13 LCD_SEG14
Pin Alternate Functionality / Description
EBI EBI_AD09 #0/1/2
Timers TIM0_CC0 #0/1/4
Communication
LEU0_RX #4 I2C0_SDA #0
EBI_AD10 #0/1/2 TIM0_CC1 #0/1
I2C0_SCL #0
3
PA2
LCD_SEG15
EBI_AD11 #0/1/2 TIM0_CC2 #0/1
4
PA3
LCD_SEG16
EBI_AD12 #0/1/2 TIM0_CDTI0 #0
U0_TX #2
5
PA4
LCD_SEG17
EBI_AD13 #0/1/2 TIM0_CDTI1 #0
U0_RX #2
6
PA5
LCD_SEG18
EBI_AD14 #0/1/2 TIM0_CDTI2 #0
LEU1_TX #1
7
PA6
LCD_SEG19
EBI_AD15 #0/1/2
LEU1_RX #1
8
IOVDD_0 Digital IO power supply 0.
9
PB0
LCD_SEG32
EBI_A16 #0/1/2
TIM1_CC0 #2
10
PB1
LCD_SEG33
EBI_A17 #0/1/2
TIM1_CC1 #2
11
PB2
LCD_SEG34
EBI_A18 #0/1/2
TIM1_CC2 #2
12
PB3
LCD_SEG20/ LCD_COM4
EBI_A19 #0/1/2
PCNT1_S0IN #1
US2_TX #1
13
PB4
LCD_SEG21/ LCD_COM5
EBI_A20 #0/1/2
PCNT1_S1IN #1
US2_RX #1
14
PB5
LCD_SEG22/ LCD_COM6
EBI_A21 #0/1/2
US2_CLK #1
15
PB6
LCD_SEG23/ LCD_COM7
EBI_A22 #0/1/2
US2_CS #1
16
VSS
Ground.
17
IOVDD_1 Digital IO power supply 1.
18
PC0
ACMP0_CH0 DAC0_OUT0ALT
#0/ OPAMP_OUT0ALT
EBI_A23 #0/1/2
TIM0_CC1 #4 PCNT0_S0IN #2
US0_TX #5 US1_TX #0 I2C0_SDA #4
19
PC1
ACMP0_CH1 DAC0_OUT0ALT
#1/ OPAMP_OUT0ALT
EBI_A24 #0/1/2
TIM0_CC2 #4 PCNT0_S1IN #2
US0_RX #5 US1_RX #0 I2C0_SCL #4
ACMP0_CH2
20
PC2
DAC0_OUT0ALT #2/
EBI_A25 #0/1/2
TIM0_CDTI0 #4
US2_TX #0
OPAMP_OUT0ALT
Other PRS_CH0 #0 GPIO_EM4WU0 CMU_CLK1 #0 PRS_CH1 #0 CMU_CLK0 #0 ETM_TD0 #3 LES_ALTEX2 #0 ETM_TD1 #3 LES_ALTEX3 #0 ETM_TD2 #3 LES_ALTEX4 #0 ETM_TD3 #3 ETM_TCLK #3 GPIO_EM4WU1
LES_CH0 #0 PRS_CH2 #0
LES_CH1 #0 PRS_CH3 #0
LES_CH2 #0
silabs.com | Building a more connected world.
Rev. 2.30 | 289
EFM32LG Data Sheet
Pin Definitions
LQFP100 Pin# and Name
Pin # Pin Name
21
PC3
22
PC4
23
PC5
24
PB7
25
PB8
26
PA7
27
PA8
28
PA9
29
PA10
30
PA11
31
IOVDD_2
32
VSS
33
PA12
34
PA13
35
PA14
36
RESETn
37
PB9
38
PB10
39
PB11
40
PB12
41
AVDD_1
42
PB13
43
PB14
44
IOVDD_3
45
AVDD_0
Pin Alternate Functionality / Description
Analog
EBI
Timers
Communication
Other
ACMP0_CH3 DAC0_OUT0ALT
#3/ OPAMP_OUT0ALT
EBI_NANDREn #0/1/2
TIM0_CDTI1 #4
US2_RX #0
LES_CH3 #0
ACMP0_CH4 / DAC0_P0 / OPAMP_P0
EBI_A26 #0/1/2
TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0
US2_CLK #0 I2C1_SDA #0
LES_CH4 #0
ACMP0_CH5 / DAC0_N0 / OPAMP_N0
EBI_NANDWEn #0/1/2
LETIM0_OUT1 #3 PCNT1_S1IN #0
US2_CS #0 I2C1_SCL #0
LES_CH5 #0
LFXTAL_P
TIM1_CC0 #3
US0_TX #4 US1_CLK #0
LFXTAL_N
TIM1_CC1 #3
US0_RX #4 US1_CS #0
LCD_SEG35
EBI_CSTFT #0/1/2
LCD_SEG36
EBI_DCLK #0/1/2
TIM2_CC0 #0
LCD_SEG37
EBI_DTEN #0/1/2
TIM2_CC1 #0
LCD_SEG38
EBI_VSNC #0/1/2
TIM2_CC2 #0
LCD_SEG39
EBI_HSNC #0/1/2
Digital IO power supply 2.
Ground.
LCD_BCAP_P
EBI_A00 #0/1/2
TIM2_CC0 #1
LCD_BCAP_N
EBI_A01 #0/1/2
TIM2_CC1 #1
LCD_BEXT
EBI_A02 #0/1/2
TIM2_CC2 #1
Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released.
EBI_A03 #0/1/2
U1_TX #2
EBI_A04 #0/1/2
U1_RX #2
DAC0_OUT0 / OPAMP_OUT0
TIM1_CC2 #3 LETIM0_OUT0 #1
I2C1_SDA #1
DAC0_OUT1 / OPAMP_OUT1
LETIM0_OUT1 #1
I2C1_SCL #1
Analog power supply 1.
HFXTAL_P
US0_CLK #4/5 LEU0_TX #1
HFXTAL_N
US0_CS #4/5 LEU0_RX #1
Digital IO power supply 3.
Analog power supply 0.
silabs.com | Building a more connected world.
Rev. 2.30 | 290
EFM32LG Data Sheet
Pin Definitions
LQFP100 Pin# and Name
Pin # Pin Name
46
PD0
47
PD1
48
PD2
49
PD3
50
PD4
51
PD5
52
PD6
53
PD7
54
PD8
55
PC6
56
PC7
57 VDD_DREG
58
VSS
59 DECOUPLE
60
PE0
61
PE1
62
PE2
63
PE3
64
PE4
65
PE5
66
PE6
67
PE7
68
PC8
Pin Alternate Functionality / Description
Analog
EBI
Timers
Communication
Other
ADC0_CH0 DAC0_OUT0ALT
#4/ OPAMP_OUT0ALT OPAMP_OUT2 #1
PCNT2_S0IN #0
US1_TX #1
ADC0_CH1 DAC0_OUT1ALT
#4/ OPAMP_OUT1ALT
TIM0_CC0 #3 PCNT2_S1IN #0
US1_RX #1
DBG_SWO #2
ADC0_CH2
EBI_A27 #0/1/2
TIM0_CC1 #3
US1_CLK #1
DBG_SWO #3
ADC0_CH3 OPAMP_N2
TIM0_CC2 #3
US1_CS #1
ETM_TD1 #0/2
ADC0_CH4 OPAMP_P2
LEU0_TX #0
ETM_TD2 #0/2
ADC0_CH5 OPAMP_OUT2 #0
LEU0_RX #0
ETM_TD3 #0/2
ADC0_CH6 / DAC0_P1 / OPAMP_P1
TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3
US1_RX #2 I2C0_SDA #1
LES_ALTEX0 #0 ACMP0_O #2 ETM_TD0 #0
ADC0_CH7 / DAC0_N1 / OPAMP_N1
TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3
US1_TX #2 I2C0_SCL #1
CMU_CLK0 #2 LES_ALTEX1 #0
ACMP1_O #2 ETM_TCLK #0
BU_VIN
CMU_CLK1 #1
ACMP0_CH6
EBI_A05 #0/1/2
LEU1_TX #0 I2C0_SDA #2
LES_CH6 #0 ETM_TCLK #2
ACMP0_CH7
EBI_A06 #0/1/2
LEU1_RX #0 I2C0_SCL #2
LES_CH7 #0 ETM_TD0 #2
Power supply for on-chip voltage regulator.
Ground.
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin.
EBI_A07 #0/1/2
TIM3_CC0 #1 PCNT0_S0IN #1
U0_TX #1 I2C1_SDA #2
EBI_A08 #0/1/2
TIM3_CC1 #1 PCNT0_S1IN #1
U0_RX #1 I2C1_SCL #2
BU_VOUT
EBI_A09 #0
TIM3_CC2 #1
U1_TX #3
ACMP0_O #1
BU_STAT
EBI_A10 #0
U1_RX #3
ACMP1_O #1
LCD_COM0
EBI_A11 #0/1/2
US0_CS #1
LCD_COM1
EBI_A12 #0/1/2
US0_CLK #1
LCD_COM2
EBI_A13 #0/1/2
US0_RX #1
LCD_COM3
EBI_A14 #0/1/2
US0_TX #1
ACMP1_CH0
EBI_A15 #0/1/2
TIM2_CC0 #2
US0_CS #2
LES_CH8 #0
silabs.com | Building a more connected world.
Rev. 2.30 | 291
EFM32LG Data Sheet
Pin Definitions
LQFP100 Pin# and Name
Pin # Pin Name
69
PC9
70
PC10
71
PC11
72
PC12
73
PC13
74
PC14
75
PC15
76
PF0
77
PF1
78
PF2
79
PF3
80
PF4
81
PF5
82
IOVDD_5
83
VSS
84
PF6
85
PF7
86
PF8
87
PF9
88
PD9
89
PD10
90
PD11
91
PD12
92
PE8
Analog
ACMP1_CH1
ACMP1_CH2
ACMP1_CH3
ACMP1_CH4 DAC0_OUT1ALT
#0/ OPAMP_OUT1ALT
ACMP1_CH5 DAC0_OUT1ALT
#1/ OPAMP_OUT1ALT
ACMP1_CH6 DAC0_OUT1ALT
#2/ OPAMP_OUT1ALT
ACMP1_CH7 DAC0_OUT1ALT
#3/ OPAMP_OUT1ALT
Pin Alternate Functionality / Description
EBI
Timers
Communication
EBI_A09 #1/2
TIM2_CC1 #2
US0_CLK #2
EBI_A10 #1/2 EBI_ALE #1/2
TIM2_CC2 #2
US0_RX #2 US0_TX #2
U1_TX #0
TIM0_CDTI0 #1/3 TIM1_CC0 #0 TIM1_CC2 #4
PCNT0_S0IN #0
U1_RX #0
TIM0_CDTI1 #1/3 TIM1_CC1 #0
PCNT0_S1IN #0
US0_CS #3 U0_TX #3
TIM0_CDTI2 #1/3 TIM1_CC2 #0
US0_CLK #3 U0_RX #3
TIM0_CC0 #5 LETIM0_OUT0 #2
TIM0_CC1 #5 LETIM0_OUT1 #2
US1_CLK #2 LEU0_TX #3 I2C0_SDA #5
US1_CS #2 LEU0_RX #3 I2C0_SCL #5
LCD_SEG0
EBI_ARDY #0/1/2
TIM0_CC2 #5
LEU0_TX #4
LCD_SEG1
EBI_ALE #0
TIM0_CDTI0 #2/5
LCD_SEG2
EBI_WEn #0/2
LCD_SEG3
EBI_REn #0/2
Digital IO power supply 5.
Ground.
LCD_SEG24
EBI_BL0 #0/1/2
LCD_SEG25
EBI_BL1 #0/1/2
LCD_SEG26
EBI_WEn #1
LCD_SEG27
EBI_REn #1
LCD_SEG28
EBI_CS0 #0/1/2
LCD_SEG29
EBI_CS1 #0/1/2
LCD_SEG30
EBI_CS2 #0/1/2
LCD_SEG31
EBI_CS3 #0/1/2
LCD_SEG4
EBI_AD00 #0/1/2
TIM0_CDTI1 #2/5 TIM0_CDTI2 #2/5
TIM0_CC0 #2 TIM0_CC1 #2 TIM0_CC2 #2
PCNT2_S0IN #1
U0_TX #0 U0_RX #0
Other LES_CH9 #0 GPIO_EM4WU2 LES_CH10 #0 LES_CH11 #0 CMU_CLK0 #1 LES_CH12 #0
LES_CH13 #0
LES_CH14 #0
LES_CH15 #0 DBG_SWO #1
DBG_SWCLK #0/1/2/3
DBG_SWDIO #0/1/2/3
GPIO_EM4WU3 ACMP1_O #0 DBG_SWO #0
GPIO_EM4WU4 PRS_CH0 #1 ETM_TD3 #1 PRS_CH1 #1 PRS_CH2 #1
ETM_TCLK #1 ETM_TD0 #1
PRS_CH3 #1
silabs.com | Building a more connected world.
Rev. 2.30 | 292
LQFP100 Pin# and Name
Pin # Pin Name
93
PE9
94
PE10
95
PE11
96
PE12
97
PE13
98
PE14
99
PE15
100
PA15
Analog LCD_SEG5 LCD_SEG6 LCD_SEG7
LCD_SEG8
LCD_SEG9
LCD_SEG10 LCD_SEG11 LCD_SEG12
EFM32LG Data Sheet
Pin Definitions
Pin Alternate Functionality / Description
EBI EBI_AD01 #0/1/2 EBI_AD02 #0/1/2
Timers PCNT2_S1IN #1
TIM1_CC0 #1
Communication US0_TX #0
EBI_AD03 #0/1/2
TIM1_CC1 #1
US0_RX #0
EBI_AD04 #0/1/2
TIM1_CC2 #1
EBI_AD05 #0/1/2
EBI_AD06 #0/1/2 EBI_AD07 #0/1/2 EBI_AD08 #0/1/2
TIM3_CC0 #0 TIM3_CC1 #0 TIM3_CC2 #0
US0_RX #3 US0_CLK #0 I2C0_SDA #6
US0_TX #3 US0_CS #0 I2C0_SCL #6
LEU0_TX #2
LEU0_RX #2
Other
BOOT_TX LES_ALTEX5 #0
BOOT_RX
CMU_CLK1 #2 LES_ALTEX6 #0
LES_ALTEX7 #0 ACMP0_O #0
GPIO_EM4WU5
silabs.com | Building a more connected world.
Rev. 2.30 | 293
EFM32LG Data Sheet
Pin Definitions
5.14.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0.
Table 5.41. Alternate Functionality Overview
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
ACMP0_CH0 PC0
Analog comparator ACMP0, channel 0.
ACMP0_CH1 PC1
Analog comparator ACMP0, channel 1.
ACMP0_CH2 PC2
Analog comparator ACMP0, channel 2.
ACMP0_CH3 PC3
Analog comparator ACMP0, channel 3.
ACMP0_CH4 PC4
Analog comparator ACMP0, channel 4.
ACMP0_CH5 PC5
Analog comparator ACMP0, channel 5.
ACMP0_CH6 PC6
Analog comparator ACMP0, channel 6.
ACMP0_CH7 PC7
Analog comparator ACMP0, channel 7.
ACMP0_O
PE13 PE2 PD6
Analog comparator ACMP0, digital output.
ACMP1_CH0 PC8
Analog comparator ACMP1, channel 0.
ACMP1_CH1 PC9
Analog comparator ACMP1, channel 1.
ACMP1_CH2 PC10
Analog comparator ACMP1, channel 2.
ACMP1_CH3 PC11
Analog comparator ACMP1, channel 3.
ACMP1_CH4 PC12
Analog comparator ACMP1, channel 4.
ACMP1_CH5 PC13
Analog comparator ACMP1, channel 5.
ACMP1_CH6 PC14
Analog comparator ACMP1, channel 6.
ACMP1_CH7 PC15
Analog comparator ACMP1, channel 7.
ACMP1_O
PF2 PE3 PD7
Analog comparator ACMP1, digital output.
ADC0_CH0
PD0
Analog to digital converter ADC0, input channel number 0.
ADC0_CH1
PD1
Analog to digital converter ADC0, input channel number 1.
ADC0_CH2
PD2
Analog to digital converter ADC0, input channel number 2.
ADC0_CH3
PD3
Analog to digital converter ADC0, input channel number 3.
ADC0_CH4
PD4
Analog to digital converter ADC0, input channel number 4.
ADC0_CH5
PD5
Analog to digital converter ADC0, input channel number 5.
ADC0_CH6
PD6
Analog to digital converter ADC0, input channel number 6.
silabs.com | Building a more connected world.
Rev. 2.30 | 294
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
ADC0_CH7
PD7
Analog to digital converter ADC0, input channel number 7.
BOOT_RX
PE11
Bootloader RX.
BOOT_TX
PE10
Bootloader TX.
BU_STAT
PE3
Backup Power Domain status, whether or not the system is in backup mode
BU_VIN
PD8
Battery input for Backup Power Domain
BU_VOUT
PE2
Power output for Backup Power Domain
CMU_CLK0
PA2 PC12 PD7
Clock Management Unit, clock output number 0.
CMU_CLK1
PA1 PD8 PE12
Clock Management Unit, clock output number 1.
DAC0_OUT0 / OPAMP_OUT0
PB11
Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0.
DAC0_OUT0ALT / OPAMP_OUT0A PC0 PC1 PC2 PC3 PD0 LT
Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0.
DAC0_OUT1 / OPAMP_OUT1
PB12
Digital to Analog Converter DAC0_OUT1 /OPAMP output channel number 1.
DAC0_OUT1ALT / OPAMP_OUT1A PC12 PC13 PC14 PC15 PD1 LT
Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1.
DBG_SWCLK PF0 PF0 PF0 PF0
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, and has a built-in pull down.
DBG_SWDIO PF1 PF1 PF1 PF1
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and has a built-in pull up.
DBG_SWO
PF2 PC15 PD1 PD2
Debug-interface Serial Wire viewer Output.
Note that this function is not enabled after reset, and must be enabled by software to be used.
EBI_A00
PA12 PA12 PA12
External Bus Interface (EBI) address output pin 00.
EBI_A01
PA13 PA13 PA13
External Bus Interface (EBI) address output pin 01.
EBI_A02
PA14 PA14 PA14
External Bus Interface (EBI) address output pin 02.
EBI_A03
PB9 PB9 PB9
External Bus Interface (EBI) address output pin 03.
EBI_A04
PB10 PB10 PB10
External Bus Interface (EBI) address output pin 04.
EBI_A05
PC6 PC6 PC6
External Bus Interface (EBI) address output pin 05.
EBI_A06
PC7 PC7 PC7
External Bus Interface (EBI) address output pin 06.
EBI_A07
PE0 PE0 PE0
External Bus Interface (EBI) address output pin 07.
EBI_A08
PE1 PE1 PE1
External Bus Interface (EBI) address output pin 08.
EBI_A09
PE2 PC9 PC9
External Bus Interface (EBI) address output pin 09.
EBI_A10
PE3 PC10 PC10
External Bus Interface (EBI) address output pin 10.
silabs.com | Building a more connected world.
Rev. 2.30 | 295
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
EBI_A11
PE4 PE4 PE4
External Bus Interface (EBI) address output pin 11.
EBI_A12
PE5 PE5 PE5
External Bus Interface (EBI) address output pin 12.
EBI_A13
PE6 PE6 PE6
External Bus Interface (EBI) address output pin 13.
EBI_A14
PE7 PE7 PE7
External Bus Interface (EBI) address output pin 14.
EBI_A15
PC8 PC8 PC8
External Bus Interface (EBI) address output pin 15.
EBI_A16
PB0 PB0 PB0
External Bus Interface (EBI) address output pin 16.
EBI_A17
PB1 PB1 PB1
External Bus Interface (EBI) address output pin 17.
EBI_A18
PB2 PB2 PB2
External Bus Interface (EBI) address output pin 18.
EBI_A19
PB3 PB3 PB3
External Bus Interface (EBI) address output pin 19.
EBI_A20
PB4 PB4 PB4
External Bus Interface (EBI) address output pin 20.
EBI_A21
PB5 PB5 PB5
External Bus Interface (EBI) address output pin 21.
EBI_A22
PB6 PB6 PB6
External Bus Interface (EBI) address output pin 22.
EBI_A23
PC0 PC0 PC0
External Bus Interface (EBI) address output pin 23.
EBI_A24
PC1 PC1 PC1
External Bus Interface (EBI) address output pin 24.
EBI_A25
PC2 PC2 PC2
External Bus Interface (EBI) address output pin 25.
EBI_A26
PC4 PC4 PC4
External Bus Interface (EBI) address output pin 26.
EBI_A27
PD2 PD2 PD2
External Bus Interface (EBI) address output pin 27.
EBI_AD00
PE8 PE8 PE8
External Bus Interface (EBI) address and data input / output pin 00.
EBI_AD01
PE9 PE9 PE9
External Bus Interface (EBI) address and data input / output pin 01.
EBI_AD02
PE10 PE10 PE10
External Bus Interface (EBI) address and data input / output pin 02.
EBI_AD03
PE11 PE11 PE11
External Bus Interface (EBI) address and data input / output pin 03.
EBI_AD04
PE12 PE12 PE12
External Bus Interface (EBI) address and data input / output pin 04.
EBI_AD05
PE13 PE13 PE13
External Bus Interface (EBI) address and data input / output pin 05.
EBI_AD06
PE14 PE14 PE14
External Bus Interface (EBI) address and data input / output pin 06.
EBI_AD07
PE15 PE15 PE15
External Bus Interface (EBI) address and data input / output pin 07.
EBI_AD08
PA15 PA15 PA15
External Bus Interface (EBI) address and data input / output pin 08.
EBI_AD09
PA0 PA0 PA0
External Bus Interface (EBI) address and data input / output pin 09.
EBI_AD10
PA1 PA1 PA1
External Bus Interface (EBI) address and data input / output pin 10.
EBI_AD11
PA2 PA2 PA2
External Bus Interface (EBI) address and data input / output pin 11.
silabs.com | Building a more connected world.
Rev. 2.30 | 296
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
EBI_AD12
PA3 PA3 PA3
External Bus Interface (EBI) address and data input / output pin 12.
EBI_AD13
PA4 PA4 PA4
External Bus Interface (EBI) address and data input / output pin 13.
EBI_AD14
PA5 PA5 PA5
External Bus Interface (EBI) address and data input / output pin 14.
EBI_AD15
PA6 PA6 PA6
External Bus Interface (EBI) address and data input / output pin 15.
EBI_ALE
PF3 PC11 PC11
External Bus Interface (EBI) Address Latch Enable output.
EBI_ARDY
PF2 PF2 PF2
External Bus Interface (EBI) Hardware Ready Control input.
EBI_BL0
PF6 PF6 PF6
External Bus Interface (EBI) Byte Lane/Enable pin 0.
EBI_BL1
PF7 PF7 PF7
External Bus Interface (EBI) Byte Lane/Enable pin 1.
EBI_CS0
PD9 PD9 PD9
External Bus Interface (EBI) Chip Select output 0.
EBI_CS1
PD10 PD10 PD10
External Bus Interface (EBI) Chip Select output 1.
EBI_CS2
PD11 PD11 PD11
External Bus Interface (EBI) Chip Select output 2.
EBI_CS3
PD12 PD12 PD12
External Bus Interface (EBI) Chip Select output 3.
EBI_CSTFT
PA7 PA7 PA7
External Bus Interface (EBI) Chip Select output TFT.
EBI_DCLK
PA8 PA8 PA8
External Bus Interface (EBI) TFT Dot Clock pin.
EBI_DTEN
PA9 PA9 PA9
External Bus Interface (EBI) TFT Data Enable pin.
EBI_HSNC
PA11 PA11 PA11
External Bus Interface (EBI) TFT Horizontal Synchronization pin.
EBI_NANDREn PC3 PC3 PC3
External Bus Interface (EBI) NAND Read Enable output.
EBI_NANDWEn PC5 PC5 PC5
External Bus Interface (EBI) NAND Write Enable output.
EBI_REn
PF5 PF9 PF5
External Bus Interface (EBI) Read Enable output.
EBI_VSNC
PA10 PA10 PA10
External Bus Interface (EBI) TFT Vertical Synchronization pin.
EBI_WEn
PF4 PF8 PF4
External Bus Interface (EBI) Write Enable output.
ETM_TCLK
PD7 PF8 PC6 PA6
Embedded Trace Module ETM clock .
ETM_TD0
PD6 PF9 PC7 PA2
Embedded Trace Module ETM data 0.
ETM_TD1
PD3
PD3 PA3
Embedded Trace Module ETM data 1.
ETM_TD2
PD4
PD4 PA4
Embedded Trace Module ETM data 2.
ETM_TD3
PD5 PF3 PD5 PA5
Embedded Trace Module ETM data 3.
GPIO_EM4WU0 PA0
Pin can be used to wake the system up from EM4
GPIO_EM4WU1 PA6
Pin can be used to wake the system up from EM4
silabs.com | Building a more connected world.
Rev. 2.30 | 297
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
GPIO_EM4WU2 PC9
Pin can be used to wake the system up from EM4
GPIO_EM4WU3 PF1
Pin can be used to wake the system up from EM4
GPIO_EM4WU4 PF2
Pin can be used to wake the system up from EM4
GPIO_EM4WU5 PE13
Pin can be used to wake the system up from EM4
HFXTAL_N
PB14
High Frequency Crystal negative pin. Also used as external optional clock input pin.
HFXTAL_P
PB13
High Frequency Crystal positive pin.
I2C0_SCL
PA1 PD7 PC7
PC1 PF1 PE13 I2C0 Serial Clock Line input / output.
I2C0_SDA
PA0 PD6 PC6
PC0 PF0 PE12 I2C0 Serial Data input / output.
I2C1_SCL
PC5 PB12 PE1
I2C1 Serial Clock Line input / output.
I2C1_SDA
PC4 PB11 PE0
I2C1 Serial Data input / output.
LCD_BCAP_N PA13
LCD voltage booster (optional), boost capacitor, negative pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P.
LCD_BCAP_P PA12
LCD voltage booster (optional), boost capacitor, positive pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P.
LCD voltage booster (optional), boost output. If using the LCD voltage booster, connect a 1 uF capacitor between this pin and VSS.
LCD_BEXT
PA14
An external LCD voltage may also be applied to this pin if the booster is not enabled.
If AVDD is used directly as the LCD supply voltage, this pin may be left unconnected or used as a GPIO.
LCD_COM0
PE4
LCD driver common line number 0.
LCD_COM1
PE5
LCD driver common line number 1.
LCD_COM2
PE6
LCD driver common line number 2.
LCD_COM3
PE7
LCD driver common line number 3.
LCD_SEG0
PF2
LCD segment line 0. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
LCD_SEG1
PF3
LCD segment line 0. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
LCD_SEG2
PF4
LCD segment line 0. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
LCD_SEG3
PF5
LCD segment line 3. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
LCD_SEG4
PE8
LCD segment line 4. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
LCD_SEG5
PE9
LCD segment line 5. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
silabs.com | Building a more connected world.
Rev. 2.30 | 298
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
LCD_SEG6
PE10
LCD segment line 6. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
LCD_SEG7
PE11
LCD segment line 7. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
LCD_SEG8
PE12
LCD segment line 8. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG9
PE13
LCD segment line 9. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG10
PE14
LCD segment line 10. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG11
PE15
LCD segment line 11. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG12
PA15
LCD segment line 12. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG13
PA0
LCD segment line 13. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG14
PA1
LCD segment line 14. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG15
PA2
LCD segment line 15. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG16
PA3
LCD segment line 16. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG17
PA4
LCD segment line 17. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG18
PA5
LCD segment line 18. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG19
PA6
LCD segment line 19. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG20/ LCD_COM4
PB3
LCD segment line 20. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 4
LCD_SEG21/ LCD_COM5
PB4
LCD segment line 21. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 5
LCD_SEG22/ LCD_COM6
PB5
LCD segment line 22. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 6
LCD_SEG23/ LCD_COM7
PB6
LCD segment line 23. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 7
LCD_SEG24
PF6
LCD segment line 24. Segments 24, 25, 26 and 27 are controlled by SEGEN6.
LCD_SEG25
PF7
LCD segment line 25. Segments 24, 25, 26 and 27 are controlled by SEGEN6.
LCD_SEG26
PF8
LCD segment line 26. Segments 24, 25, 26 and 27 are controlled by SEGEN6.
silabs.com | Building a more connected world.
Rev. 2.30 | 299
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
LCD_SEG27
PF9
LCD segment line 27. Segments 24, 25, 26 and 27 are controlled by SEGEN6.
LCD_SEG28
PD9
LCD segment line 28. Segments 28, 29, 30 and 31 are controlled by SEGEN7.
LCD_SEG29
PD10
LCD segment line 29. Segments 28, 29, 30 and 31 are controlled by SEGEN7.
LCD_SEG30
PD11
LCD segment line 30. Segments 28, 29, 30 and 31 are controlled by SEGEN7.
LCD_SEG31
PD12
LCD segment line 31. Segments 28, 29, 30 and 31 are controlled by SEGEN7.
LCD_SEG32
PB0
LCD segment line 32. Segments 32, 33, 34 and 35 are controlled by SEGEN8.
LCD_SEG33
PB1
LCD segment line 33. Segments 32, 33, 34 and 35 are controlled by SEGEN8.
LCD_SEG34
PB2
LCD segment line 34. Segments 32, 33, 34 and 35 are controlled by SEGEN8.
LCD_SEG35
PA7
LCD segment line 35. Segments 32, 33, 34 and 35 are controlled by SEGEN8.
LCD_SEG36
PA8
LCD segment line 36. Segments 36, 37, 38 and 39 are controlled by SEGEN9.
LCD_SEG37
PA9
LCD segment line 37. Segments 36, 37, 38 and 39 are controlled by SEGEN9.
LCD_SEG38
PA10
LCD segment line 38. Segments 36, 37, 38 and 39 are controlled by SEGEN9.
LCD_SEG39
PA11
LCD segment line 39. Segments 36, 37, 38 and 39 are controlled by SEGEN9.
LES_ALTEX0 PD6
LESENSE alternate exite output 0.
LES_ALTEX1 PD7
LESENSE alternate exite output 1.
LES_ALTEX2 PA3
LESENSE alternate exite output 2.
LES_ALTEX3 PA4
LESENSE alternate exite output 3.
LES_ALTEX4 PA5
LESENSE alternate exite output 4.
LES_ALTEX5 PE11
LESENSE alternate exite output 5.
LES_ALTEX6 PE12
LESENSE alternate exite output 6.
LES_ALTEX7 PE13
LESENSE alternate exite output 7.
LES_CH0
PC0
LESENSE channel 0.
LES_CH1
PC1
LESENSE channel 1.
LES_CH2
PC2
LESENSE channel 2.
LES_CH3
PC3
LESENSE channel 3.
LES_CH4
PC4
LESENSE channel 4.
LES_CH5
PC5
LESENSE channel 5.
LES_CH6
PC6
LESENSE channel 6.
silabs.com | Building a more connected world.
Rev. 2.30 | 300
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
LES_CH7
PC7
LESENSE channel 7.
LES_CH8
PC8
LESENSE channel 8.
LES_CH9
PC9
LESENSE channel 9.
LES_CH10
PC10
LESENSE channel 10.
LES_CH11
PC11
LESENSE channel 11.
LES_CH12
PC12
LESENSE channel 12.
LES_CH13
PC13
LESENSE channel 13.
LES_CH14
PC14
LESENSE channel 14.
LES_CH15
PC15
LESENSE channel 15.
LETIM0_OUT0 PD6 PB11 PF0 PC4
Low Energy Timer LETIM0, output channel 0.
LETIM0_OUT1 PD7 PB12 PF1 PC5
Low Energy Timer LETIM0, output channel 1.
LEU0_RX
PD5 PB14 PE15 PF1 PA0
LEUART0 Receive input.
LEU0_TX
PD4 PB13 PE14 PF0 PF2
LEUART0 Transmit output. Also used as receive input in half duplex communication.
LEU1_RX
PC7 PA6
LEUART1 Receive input.
LEU1_TX
PC6 PA5
LEUART1 Transmit output. Also used as receive input in half duplex communication.
LFXTAL_N
PB8
Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin.
LFXTAL_P
PB7
Low Frequency Crystal (typically 32.768 kHz) positive pin.
OPAMP_N0 / DAC0_N0
PC5
Operational Amplifier 0 external negative input.
OPAMP_N1 / DAC0_N1
PD7
Operational Amplifier 1 external negative input.
OPAMP_N2
PD3
Operational Amplifier 2 external negative input.
OPAMP_OUT2 PD5 PD0
Operational Amplifier 2 output.
OPAMP_P0 / DAC0_P0
PC4
Operational Amplifier 0 external positive input.
OPAMP_P1 / DAC0_P1
PD6
Operational Amplifier 1 external positive input.
OPAMP_P2
PD4
Operational Amplifier 2 external positive input.
PCNT0_S0IN PC13 PE0 PC0 PD6
Pulse Counter PCNT0 input number 0.
PCNT0_S1IN PC14 PE1 PC1 PD7
Pulse Counter PCNT0 input number 1.
PCNT1_S0IN PC4 PB3
Pulse Counter PCNT1 input number 0.
PCNT1_S1IN PC5 PB4
Pulse Counter PCNT1 input number 1.
PCNT2_S0IN PD0 PE8
Pulse Counter PCNT2 input number 0.
PCNT2_S1IN PD1 PE9
Pulse Counter PCNT2 input number 1.
PRS_CH0
PA0 PF3
Peripheral Reflex System PRS, channel 0.
silabs.com | Building a more connected world.
Rev. 2.30 | 301
Alternate
LOCATION
Functionality
0
1
2
3
4
5
PRS_CH1
PA1 PF4
PRS_CH2
PC0 PF5
PRS_CH3
PC1 PE8
TIM0_CC0
PA0 PA0 PF6 PD1 PA0 PF0
TIM0_CC1
PA1 PA1 PF7 PD2 PC0 PF1
TIM0_CC2
PA2 PA2 PF8 PD3 PC1 PF2
TIM0_CDTI0
PA3 PC13 PF3 PC13 PC2 PF3
TIM0_CDTI1
PA4 PC14 PF4 PC14 PC3 PF4
TIM0_CDTI2
TIM1_CC0 TIM1_CC1 TIM1_CC2 TIM2_CC0 TIM2_CC1 TIM2_CC2 TIM3_CC0 TIM3_CC1 TIM3_CC2 U0_RX
U0_TX
U1_RX
U1_TX
US0_CLK US0_CS
PA5 PC15 PF5 PC15 PC4 PF5
PC13 PC14 PC15 PA8 PA9 PA10 PE14 PE15 PA15 PF7
PE10 PE11 PE12 PA12 PA13 PA14 PE0 PE1 PE2 PE1
PB0 PB1 PB2 PC8 PC9 PC10
PA4
PB7 PB8 PB11
PC15
PD6 PD7 PC13
PF6 PE0 PA3 PC14
PC13
PB10 PE3
PC12
PB9 PE2
PE12 PE5 PC9 PC15 PB13 PB13 PE13 PE4 PC8 PC14 PB14 PB14
US0_RX
PE11 PE6 PC10 PE12 PB8 PC1
US0_TX
US1_CLK US1_CS
PE10 PE7 PC11 PE13 PB7 PC0
PB7 PD2 PF0 PB8 PD3 PF1
EFM32LG Data Sheet
Pin Definitions
6
Description
Peripheral Reflex System PRS, channel 1.
Peripheral Reflex System PRS, channel 2.
Peripheral Reflex System PRS, channel 3.
Timer 0 Capture Compare input / output channel 0.
Timer 0 Capture Compare input / output channel 1.
Timer 0 Capture Compare input / output channel 2.
Timer 0 Complimentary Deat Time Insertion channel 0.
Timer 0 Complimentary Deat Time Insertion channel 1.
Timer 0 Complimentary Deat Time Insertion channel 2.
Timer 1 Capture Compare input / output channel 0.
Timer 1 Capture Compare input / output channel 1.
Timer 1 Capture Compare input / output channel 2.
Timer 2 Capture Compare input / output channel 0.
Timer 2 Capture Compare input / output channel 1.
Timer 2 Capture Compare input / output channel 2.
Timer 3 Capture Compare input / output channel 0.
Timer 3 Capture Compare input / output channel 1.
Timer 3 Capture Compare input / output channel 2.
UART0 Receive input.
UART0 Transmit output. Also used as receive input in half duplex communication.
UART1 Receive input.
UART1 Transmit output. Also used as receive input in half duplex communication.
USART0 clock input / output.
USART0 chip select input / output.
USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output (MISO).
USART0 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input (MOSI).
USART1 clock input / output.
USART1 chip select input / output.
silabs.com | Building a more connected world.
Rev. 2.30 | 302
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
US1_RX
PC1 PD1 PD6
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output (MISO).
US1_TX
PC0 PD0 PD7
USART1 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input (MOSI).
US2_CLK
PC4 PB5
USART2 clock input / output.
US2_CS
PC5 PB6
USART2 chip select input / output.
US2_RX
PC3 PB4
USART2 Asynchronous Receive.
USART2 Synchronous mode Master Input / Slave Output (MISO).
US2_TX
PC2 PB3
USART2 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART2 Synchronous mode Master Output / Slave Input (MOSI).
5.14.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG880 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.42. GPIO Pinout
Port
Port A Port B Port C Port D Port E Port F
Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 15 14 13 12 11 10 PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 -- PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 -- -- -- PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 -- -- -- -- -- -- PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0
silabs.com | Building a more connected world.
Rev. 2.30 | 303
5.14.4 Opamp Pinout Overview
The specific opamp terminals available in EFM32LG880 is shown in the following figure.
PC4
+ OUT0ALT
PC5
OPA0 -
OUT0
PD4
+
PD3
OPA2 -
OUT2
PD6
+ OUT1ALT
PD7
OPA1 -
OUT1
PB11 PB12 PC0 PC1 PC2 PC3
PD0 PD1 PD5
Figure 5.28. Opamp Pinout
EFM32LG Data Sheet
Pin Definitions
silabs.com | Building a more connected world.
Rev. 2.30 | 304
5.15 EFM32LG890 (BGA112)
EFM32LG Data Sheet
Pin Definitions
5.15.1 Pinout
The EFM32LG890 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question.
Figure 5.29. EFM32LG890 Pinout (top view, not to scale)
silabs.com | Building a more connected world.
Rev. 2.30 | 305
EFM32LG Data Sheet
Pin Definitions
Table 5.43. Device Pinout
BGA112 Pin# and Name
Pin # Pin Name
A1
PE15
A2
PE14
A3
PE12
A4
PE9
A5
PD10
A6
PF7
A7
PF5
A8
PF4
A9
PE4
A10
PC14
A11
PC15
B1
PA15
B2
PE13
B3
PE11
B4
PE8
B5
PD11
B6
PF8
B7
PF6
B8
PF3
B9
PE5
B10
PC12
B11
PC13
Pin Alternate Functionality / Description
Analog LCD_SEG11 LCD_SEG10
EBI EBI_AD07 #0/1/2 EBI_AD06 #0/1/2
LCD_SEG8
EBI_AD04 #0/1/2
LCD_SEG5
LCD_SEG29
LCD_SEG25
LCD_SEG3
LCD_SEG2
LCD_COM0
ACMP1_CH6 DAC0_OUT1ALT
#2/ OPAMP_OUT1ALT
ACMP1_CH7 DAC0_OUT1ALT
#3/ OPAMP_OUT1ALT
LCD_SEG12
EBI_AD01 #0/1/2 EBI_CS1 #0/1/2 EBI_BL1 #0/1/2 EBI_REn #0/2 EBI_WEn #0/2 EBI_A11 #0/1/2
EBI_AD08 #0/1/2
LCD_SEG9
EBI_AD05 #0/1/2
LCD_SEG7
EBI_AD03 #0/1/2
LCD_SEG4 LCD_SEG30 LCD_SEG26 LCD_SEG24
EBI_AD00 #0/1/2 EBI_CS2 #0/1/2
EBI_WEn #1 EBI_BL0 #0/1/2
LCD_SEG1
EBI_ALE #0
LCD_COM1
ACMP1_CH4 DAC0_OUT1ALT
#0/ OPAMP_OUT1ALT
ACMP1_CH5 DAC0_OUT1ALT
#1/ OPAMP_OUT1ALT
EBI_A12 #0/1/2
Timers TIM3_CC1 #0 TIM3_CC0 #0 TIM1_CC2 #1 PCNT2_S1IN #1
TIM0_CC1 #2 TIM0_CDTI2 #2/5 TIM0_CDTI1 #2/5
TIM0_CDTI1 #1/3 TIM1_CC1 #0
PCNT0_S1IN #0
TIM0_CDTI2 #1/3 TIM1_CC2 #0 TIM3_CC2 #0
TIM1_CC1 #1 PCNT2_S0IN #1
TIM0_CC2 #2 TIM0_CC0 #2 TIM0_CDTI0 #2/5
TIM0_CDTI0 #1/3 TIM1_CC0 #0 TIM1_CC2 #4
PCNT0_S0IN #0
Communication
LEU0_RX #2
LEU0_TX #2
US0_RX #3 US0_CLK #0 I2C0_SDA #6
Other
CMU_CLK1 #2 LES_ALTEX6 #0
U0_RX #0 US0_CS #1
PRS_CH2 #1 PRS_CH1 #1
US0_CS #3 U0_TX #3
LES_CH14 #0
US0_CLK #3 U0_RX #3
LES_CH15 #0 DBG_SWO #1
US0_TX #3 US0_CS #0 I2C0_SCL #6
US0_RX #0
LES_ALTEX7 #0 ACMP0_O #0
GPIO_EM4WU5
LES_ALTEX5 #0 BOOT_RX
PRS_CH3 #1
U0_TX #0 US0_CLK #1
ETM_TCLK #1
PRS_CH0 #1 ETM_TD3 #1
U1_TX #0
CMU_CLK0 #1 LES_CH12 #0
U1_RX #0
LES_CH13 #0
silabs.com | Building a more connected world.
Rev. 2.30 | 306
EFM32LG Data Sheet
Pin Definitions
BGA112 Pin# and Name
Pin # Pin Name
C1
PA1
Analog LCD_SEG14
C2
PA0
LCD_SEG13
C3
PE10
LCD_SEG6
C4
PD13
C5
PD12
LCD_SEG31
C6
PF9
LCD_SEG27
C7
VSS
Ground.
Pin Alternate Functionality / Description
EBI
Timers
Communication
EBI_AD10 #0/1/2 TIM0_CC1 #0/1
I2C0_SCL #0
EBI_AD09 #0/1/2 TIM0_CC0 #0/1/4
EBI_AD02 #0/1/2
TIM1_CC0 #1
LEU0_RX #4 I2C0_SDA #0
US0_TX #0
EBI_CS3 #0/1/2 EBI_REn #1
C8
PF2
LCD_SEG0
EBI_ARDY #0/1/2
TIM0_CC2 #5
LEU0_TX #4
C9
PE6
C10
PC10
C11
PC11
D1
PA3
LCD_COM2 ACMP1_CH2 ACMP1_CH3
LCD_SEG16
EBI_A13 #0/1/2 EBI_A10 #1/2 EBI_ALE #1/2
EBI_AD12 #0/1/2
TIM2_CC2 #2 TIM0_CDTI0 #0
US0_RX #1 US0_RX #2 US0_TX #2
U0_TX #2
D2
PA2
LCD_SEG15
EBI_AD11 #0/1/2 TIM0_CC2 #0/1
D3
PB15
D4
VSS
Ground.
D5
IOVDD_6 Digital IO power supply 6.
D6
PD9
LCD_SEG28
EBI_CS0 #0/1/2
D7
IOVDD_5 Digital IO power supply 5.
D8
PF1
TIM0_CC1 #5 LETIM0_OUT1 #2
US1_CS #2 LEU0_RX #3 I2C0_SCL #5
D9
PE7
LCD_COM3
EBI_A14 #0/1/2
US0_TX #1
D10
PC8
ACMP1_CH0
EBI_A15 #0/1/2
TIM2_CC0 #2
US0_CS #2
D11
PC9
ACMP1_CH1
EBI_A09 #1/2
TIM2_CC1 #2
US0_CLK #2
E1
PA6
LCD_SEG19
EBI_AD15 #0/1/2
LEU1_RX #1
E2
PA5
LCD_SEG18
EBI_AD14 #0/1/2 TIM0_CDTI2 #0
LEU1_TX #1
E3
PA4
E4
PB0
E8
PF0
LCD_SEG17 LCD_SEG32
EBI_AD13 #0/1/2 TIM0_CDTI1 #0
EBI_A16 #0/1/2
TIM1_CC0 #2
TIM0_CC0 #5 LETIM0_OUT0 #2
U0_RX #2
US1_CLK #2 LEU0_TX #3 I2C0_SDA #5
Other CMU_CLK1 #0 PRS_CH1 #0 PRS_CH0 #0 GPIO_EM4WU0
BOOT_TX ETM_TD1 #1
ETM_TD0 #1
ACMP1_O #0 DBG_SWO #0 GPIO_EM4WU4
LES_CH10 #0 LES_CH11 #0 LES_ALTEX2 #0 ETM_TD1 #3 CMU_CLK0 #0 ETM_TD0 #3 ETM_TD2 #1
DBG_SWDIO #0/1/2/3
GPIO_EM4WU3
LES_CH8 #0 LES_CH9 #0 GPIO_EM4WU2 ETM_TCLK #3 GPIO_EM4WU1 LES_ALTEX4 #0 ETM_TD3 #3 LES_ALTEX3 #0 ETM_TD2 #3
DBG_SWCLK #0/1/2/3
silabs.com | Building a more connected world.
Rev. 2.30 | 307
EFM32LG Data Sheet
Pin Definitions
BGA112 Pin# and Name
Pin # Pin Name
E9
PE0
E10
PE1
E11
PE3
F1
PB1
F2
PB2
F3
PB3
F4
PB4
F8 VDD_DREG
F9 VSS_DREG
F10
PE2
F11 DECOUPLE
G1
PB5
G2
PB6
G3
VSS
G4
IOVDD_0
G8
IOVDD_4
G9
VSS
G10
PC6
G11
PC7
H1
PC0
H2
PC2
H3
PD14
H4
PA7
H5
PA8
H6
VSS
H7
IOVDD_3
H8
PD8
Pin Alternate Functionality / Description
Analog
EBI
Timers
Communication
Other
EBI_A07 #0/1/2
TIM3_CC0 #1 PCNT0_S0IN #1
U0_TX #1 I2C1_SDA #2
EBI_A08 #0/1/2
TIM3_CC1 #1 PCNT0_S1IN #1
U0_RX #1 I2C1_SCL #2
BU_STAT
EBI_A10 #0
U1_RX #3
ACMP1_O #1
LCD_SEG33
EBI_A17 #0/1/2
TIM1_CC1 #2
LCD_SEG34
EBI_A18 #0/1/2
TIM1_CC2 #2
LCD_SEG20/ LCD_COM4
EBI_A19 #0/1/2
PCNT1_S0IN #1
US2_TX #1
LCD_SEG21/ LCD_COM5
EBI_A20 #0/1/2
PCNT1_S1IN #1
US2_RX #1
Power supply for on-chip voltage regulator.
Ground for on-chip voltage regulator.
BU_VOUT
EBI_A09 #0
TIM3_CC2 #1
U1_TX #3
ACMP0_O #1
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin.
LCD_SEG22/ LCD_COM6
EBI_A21 #0/1/2
US2_CLK #1
LCD_SEG23/ LCD_COM7
EBI_A22 #0/1/2
US2_CS #1
Ground.
Digital IO power supply 0.
Digital IO power supply 4.
Ground.
ACMP0_CH6
EBI_A05 #0/1/2
LEU1_TX #0 I2C0_SDA #2
LES_CH6 #0 ETM_TCLK #2
ACMP0_CH7
EBI_A06 #0/1/2
LEU1_RX #0 I2C0_SCL #2
LES_CH7 #0 ETM_TD0 #2
ACMP0_CH0 DAC0_OUT0ALT
#0/ OPAMP_OUT0ALT
EBI_A23 #0/1/2
TIM0_CC1 #4 PCNT0_S0IN #2
US0_TX #5 US1_TX #0 I2C0_SDA #4
LES_CH0 #0 PRS_CH2 #0
ACMP0_CH2 DAC0_OUT0ALT
#2/ OPAMP_OUT0ALT
EBI_A25 #0/1/2
TIM0_CDTI0 #4
US2_TX #0
LES_CH2 #0
I2C0_SDA #3
LCD_SEG35
EBI_CSTFT #0/1/2
LCD_SEG36
EBI_DCLK #0/1/2
TIM2_CC0 #0
Ground.
Digital IO power supply 3.
BU_VIN
CMU_CLK1 #1
silabs.com | Building a more connected world.
Rev. 2.30 | 308
EFM32LG Data Sheet
Pin Definitions
BGA112 Pin# and Name
Pin # Pin Name
H9
PD5
H10
PD6
H11
PD7
J1
PC1
J2
PC3
J3
PD15
J4
PA12
J5
PA9
J6
PA10
J7
PB9
J8
PB10
J9
PD2
J10
PD3
J11
PD4
K1
PB7
K2
PC4
K3
PA13
K4
VSS
K5
PA11
K6
RESETn
K7
AVSS_1
K8
AVDD_2
K9
AVDD_1
K10
AVSS_0
Pin Alternate Functionality / Description
Analog
EBI
Timers
Communication
Other
ADC0_CH5 OPAMP_OUT2 #0
LEU0_RX #0
ETM_TD3 #0/2
ADC0_CH6 / DAC0_P1 / OPAMP_P1
TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3
US1_RX #2 I2C0_SDA #1
LES_ALTEX0 #0 ACMP0_O #2 ETM_TD0 #0
ADC0_CH7 / DAC0_N1 / OPAMP_N1
TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3
US1_TX #2 I2C0_SCL #1
CMU_CLK0 #2 LES_ALTEX1 #0
ACMP1_O #2 ETM_TCLK #0
ACMP0_CH1 DAC0_OUT0ALT
#1/ OPAMP_OUT0ALT
EBI_A24 #0/1/2
TIM0_CC2 #4 PCNT0_S1IN #2
US0_RX #5 US1_RX #0 I2C0_SCL #4
LES_CH1 #0 PRS_CH3 #0
ACMP0_CH3 DAC0_OUT0ALT
#3/ OPAMP_OUT0ALT
EBI_NANDREn #0/1/2
TIM0_CDTI1 #4
US2_RX #0
LES_CH3 #0
I2C0_SCL #3
LCD_BCAP_P
EBI_A00 #0/1/2
TIM2_CC0 #1
LCD_SEG37
EBI_DTEN #0/1/2
TIM2_CC1 #0
LCD_SEG38
EBI_VSNC #0/1/2
TIM2_CC2 #0
EBI_A03 #0/1/2
U1_TX #2
EBI_A04 #0/1/2
U1_RX #2
ADC0_CH2
EBI_A27 #0/1/2
TIM0_CC1 #3
US1_CLK #1
DBG_SWO #3
ADC0_CH3 OPAMP_N2
TIM0_CC2 #3
US1_CS #1
ETM_TD1 #0/2
ADC0_CH4 OPAMP_P2
LEU0_TX #0
ETM_TD2 #0/2
LFXTAL_P
TIM1_CC0 #3
US0_TX #4 US1_CLK #0
ACMP0_CH4 / DAC0_P0 / OPAMP_P0
EBI_A26 #0/1/2
TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0
US2_CLK #0 I2C1_SDA #0
LES_CH4 #0
LCD_BCAP_N
EBI_A01 #0/1/2
TIM2_CC1 #1
Ground.
LCD_SEG39
EBI_HSNC #0/1/2
Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released.
Analog ground 1.
Analog power supply 2.
Analog power supply 1.
Analog ground 0.
silabs.com | Building a more connected world.
Rev. 2.30 | 309
EFM32LG Data Sheet
Pin Definitions
BGA112 Pin# and Name
Pin # Pin Name
K11
PD1
L1
PB8
L2
PC5
L3
PA14
L4
IOVDD_1
L5
PB11
L6
PB12
L7
AVSS_2
L8
PB13
L9
PB14
L10
AVDD_0
L11
PD0
Pin Alternate Functionality / Description
Analog
EBI
ADC0_CH1 DAC0_OUT1ALT
#4/ OPAMP_OUT1ALT
LFXTAL_N
ACMP0_CH5 / DAC0_N0 / OPAMP_N0
EBI_NANDWEn #0/1/2
LCD_BEXT
EBI_A02 #0/1/2
Digital IO power supply 1.
DAC0_OUT0 / OPAMP_OUT0
DAC0_OUT1 / OPAMP_OUT1
Analog ground 2.
HFXTAL_P
HFXTAL_N
Analog power supply 0.
ADC0_CH0 DAC0_OUT0ALT
#4/ OPAMP_OUT0ALT OPAMP_OUT2 #1
Timers TIM0_CC0 #3 PCNT2_S1IN #0 TIM1_CC1 #3 LETIM0_OUT1 #3 PCNT1_S1IN #0 TIM2_CC2 #1 TIM1_CC2 #3 LETIM0_OUT0 #1 LETIM0_OUT1 #1
PCNT2_S0IN #0
Communication
US1_RX #1
US0_RX #4 US1_CS #0 US2_CS #0 I2C1_SCL #0
I2C1_SDA #1 I2C1_SCL #1
US0_CLK #4/5 LEU0_TX #1 US0_CS #4/5 LEU0_RX #1
US1_TX #1
Other DBG_SWO #2
LES_CH5 #0
silabs.com | Building a more connected world.
Rev. 2.30 | 310
EFM32LG Data Sheet
Pin Definitions
5.15.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0.
Table 5.44. Alternate Functionality Overview
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
ACMP0_CH0 PC0
Analog comparator ACMP0, channel 0.
ACMP0_CH1 PC1
Analog comparator ACMP0, channel 1.
ACMP0_CH2 PC2
Analog comparator ACMP0, channel 2.
ACMP0_CH3 PC3
Analog comparator ACMP0, channel 3.
ACMP0_CH4 PC4
Analog comparator ACMP0, channel 4.
ACMP0_CH5 PC5
Analog comparator ACMP0, channel 5.
ACMP0_CH6 PC6
Analog comparator ACMP0, channel 6.
ACMP0_CH7 PC7
Analog comparator ACMP0, channel 7.
ACMP0_O
PE13 PE2 PD6
Analog comparator ACMP0, digital output.
ACMP1_CH0 PC8
Analog comparator ACMP1, channel 0.
ACMP1_CH1 PC9
Analog comparator ACMP1, channel 1.
ACMP1_CH2 PC10
Analog comparator ACMP1, channel 2.
ACMP1_CH3 PC11
Analog comparator ACMP1, channel 3.
ACMP1_CH4 PC12
Analog comparator ACMP1, channel 4.
ACMP1_CH5 PC13
Analog comparator ACMP1, channel 5.
ACMP1_CH6 PC14
Analog comparator ACMP1, channel 6.
ACMP1_CH7 PC15
Analog comparator ACMP1, channel 7.
ACMP1_O
PF2 PE3 PD7
Analog comparator ACMP1, digital output.
ADC0_CH0
PD0
Analog to digital converter ADC0, input channel number 0.
ADC0_CH1
PD1
Analog to digital converter ADC0, input channel number 1.
ADC0_CH2
PD2
Analog to digital converter ADC0, input channel number 2.
ADC0_CH3
PD3
Analog to digital converter ADC0, input channel number 3.
ADC0_CH4
PD4
Analog to digital converter ADC0, input channel number 4.
ADC0_CH5
PD5
Analog to digital converter ADC0, input channel number 5.
ADC0_CH6
PD6
Analog to digital converter ADC0, input channel number 6.
silabs.com | Building a more connected world.
Rev. 2.30 | 311
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
ADC0_CH7
PD7
Analog to digital converter ADC0, input channel number 7.
BOOT_RX
PE11
Bootloader RX.
BOOT_TX
PE10
Bootloader TX.
BU_STAT
PE3
Backup Power Domain status, whether or not the system is in backup mode
BU_VIN
PD8
Battery input for Backup Power Domain
BU_VOUT
PE2
Power output for Backup Power Domain
CMU_CLK0
PA2 PC12 PD7
Clock Management Unit, clock output number 0.
CMU_CLK1
PA1 PD8 PE12
Clock Management Unit, clock output number 1.
DAC0_OUT0 / OPAMP_OUT0
PB11
Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0.
DAC0_OUT0ALT / OPAMP_OUT0A PC0 PC1 PC2 PC3 PD0 LT
Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0.
DAC0_OUT1 / OPAMP_OUT1
PB12
Digital to Analog Converter DAC0_OUT1 /OPAMP output channel number 1.
DAC0_OUT1ALT / OPAMP_OUT1A PC12 PC13 PC14 PC15 PD1 LT
Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1.
DBG_SWCLK PF0 PF0 PF0 PF0
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, and has a built-in pull down.
DBG_SWDIO PF1 PF1 PF1 PF1
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and has a built-in pull up.
DBG_SWO
PF2 PC15 PD1 PD2
Debug-interface Serial Wire viewer Output.
Note that this function is not enabled after reset, and must be enabled by software to be used.
EBI_A00
PA12 PA12 PA12
External Bus Interface (EBI) address output pin 00.
EBI_A01
PA13 PA13 PA13
External Bus Interface (EBI) address output pin 01.
EBI_A02
PA14 PA14 PA14
External Bus Interface (EBI) address output pin 02.
EBI_A03
PB9 PB9 PB9
External Bus Interface (EBI) address output pin 03.
EBI_A04
PB10 PB10 PB10
External Bus Interface (EBI) address output pin 04.
EBI_A05
PC6 PC6 PC6
External Bus Interface (EBI) address output pin 05.
EBI_A06
PC7 PC7 PC7
External Bus Interface (EBI) address output pin 06.
EBI_A07
PE0 PE0 PE0
External Bus Interface (EBI) address output pin 07.
EBI_A08
PE1 PE1 PE1
External Bus Interface (EBI) address output pin 08.
EBI_A09
PE2 PC9 PC9
External Bus Interface (EBI) address output pin 09.
EBI_A10
PE3 PC10 PC10
External Bus Interface (EBI) address output pin 10.
silabs.com | Building a more connected world.
Rev. 2.30 | 312
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
EBI_A11
PE4 PE4 PE4
External Bus Interface (EBI) address output pin 11.
EBI_A12
PE5 PE5 PE5
External Bus Interface (EBI) address output pin 12.
EBI_A13
PE6 PE6 PE6
External Bus Interface (EBI) address output pin 13.
EBI_A14
PE7 PE7 PE7
External Bus Interface (EBI) address output pin 14.
EBI_A15
PC8 PC8 PC8
External Bus Interface (EBI) address output pin 15.
EBI_A16
PB0 PB0 PB0
External Bus Interface (EBI) address output pin 16.
EBI_A17
PB1 PB1 PB1
External Bus Interface (EBI) address output pin 17.
EBI_A18
PB2 PB2 PB2
External Bus Interface (EBI) address output pin 18.
EBI_A19
PB3 PB3 PB3
External Bus Interface (EBI) address output pin 19.
EBI_A20
PB4 PB4 PB4
External Bus Interface (EBI) address output pin 20.
EBI_A21
PB5 PB5 PB5
External Bus Interface (EBI) address output pin 21.
EBI_A22
PB6 PB6 PB6
External Bus Interface (EBI) address output pin 22.
EBI_A23
PC0 PC0 PC0
External Bus Interface (EBI) address output pin 23.
EBI_A24
PC1 PC1 PC1
External Bus Interface (EBI) address output pin 24.
EBI_A25
PC2 PC2 PC2
External Bus Interface (EBI) address output pin 25.
EBI_A26
PC4 PC4 PC4
External Bus Interface (EBI) address output pin 26.
EBI_A27
PD2 PD2 PD2
External Bus Interface (EBI) address output pin 27.
EBI_AD00
PE8 PE8 PE8
External Bus Interface (EBI) address and data input / output pin 00.
EBI_AD01
PE9 PE9 PE9
External Bus Interface (EBI) address and data input / output pin 01.
EBI_AD02
PE10 PE10 PE10
External Bus Interface (EBI) address and data input / output pin 02.
EBI_AD03
PE11 PE11 PE11
External Bus Interface (EBI) address and data input / output pin 03.
EBI_AD04
PE12 PE12 PE12
External Bus Interface (EBI) address and data input / output pin 04.
EBI_AD05
PE13 PE13 PE13
External Bus Interface (EBI) address and data input / output pin 05.
EBI_AD06
PE14 PE14 PE14
External Bus Interface (EBI) address and data input / output pin 06.
EBI_AD07
PE15 PE15 PE15
External Bus Interface (EBI) address and data input / output pin 07.
EBI_AD08
PA15 PA15 PA15
External Bus Interface (EBI) address and data input / output pin 08.
EBI_AD09
PA0 PA0 PA0
External Bus Interface (EBI) address and data input / output pin 09.
EBI_AD10
PA1 PA1 PA1
External Bus Interface (EBI) address and data input / output pin 10.
EBI_AD11
PA2 PA2 PA2
External Bus Interface (EBI) address and data input / output pin 11.
silabs.com | Building a more connected world.
Rev. 2.30 | 313
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
EBI_AD12
PA3 PA3 PA3
External Bus Interface (EBI) address and data input / output pin 12.
EBI_AD13
PA4 PA4 PA4
External Bus Interface (EBI) address and data input / output pin 13.
EBI_AD14
PA5 PA5 PA5
External Bus Interface (EBI) address and data input / output pin 14.
EBI_AD15
PA6 PA6 PA6
External Bus Interface (EBI) address and data input / output pin 15.
EBI_ALE
PF3 PC11 PC11
External Bus Interface (EBI) Address Latch Enable output.
EBI_ARDY
PF2 PF2 PF2
External Bus Interface (EBI) Hardware Ready Control input.
EBI_BL0
PF6 PF6 PF6
External Bus Interface (EBI) Byte Lane/Enable pin 0.
EBI_BL1
PF7 PF7 PF7
External Bus Interface (EBI) Byte Lane/Enable pin 1.
EBI_CS0
PD9 PD9 PD9
External Bus Interface (EBI) Chip Select output 0.
EBI_CS1
PD10 PD10 PD10
External Bus Interface (EBI) Chip Select output 1.
EBI_CS2
PD11 PD11 PD11
External Bus Interface (EBI) Chip Select output 2.
EBI_CS3
PD12 PD12 PD12
External Bus Interface (EBI) Chip Select output 3.
EBI_CSTFT
PA7 PA7 PA7
External Bus Interface (EBI) Chip Select output TFT.
EBI_DCLK
PA8 PA8 PA8
External Bus Interface (EBI) TFT Dot Clock pin.
EBI_DTEN
PA9 PA9 PA9
External Bus Interface (EBI) TFT Data Enable pin.
EBI_HSNC
PA11 PA11 PA11
External Bus Interface (EBI) TFT Horizontal Synchronization pin.
EBI_NANDREn PC3 PC3 PC3
External Bus Interface (EBI) NAND Read Enable output.
EBI_NANDWEn PC5 PC5 PC5
External Bus Interface (EBI) NAND Write Enable output.
EBI_REn
PF5 PF9 PF5
External Bus Interface (EBI) Read Enable output.
EBI_VSNC
PA10 PA10 PA10
External Bus Interface (EBI) TFT Vertical Synchronization pin.
EBI_WEn
PF4 PF8 PF4
External Bus Interface (EBI) Write Enable output.
ETM_TCLK
PD7 PF8 PC6 PA6
Embedded Trace Module ETM clock .
ETM_TD0
PD6 PF9 PC7 PA2
Embedded Trace Module ETM data 0.
ETM_TD1
PD3 PD13 PD3 PA3
Embedded Trace Module ETM data 1.
ETM_TD2
PD4 PB15 PD4 PA4
Embedded Trace Module ETM data 2.
ETM_TD3
PD5 PF3 PD5 PA5
Embedded Trace Module ETM data 3.
GPIO_EM4WU0 PA0
Pin can be used to wake the system up from EM4
GPIO_EM4WU1 PA6
Pin can be used to wake the system up from EM4
silabs.com | Building a more connected world.
Rev. 2.30 | 314
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
GPIO_EM4WU2 PC9
Pin can be used to wake the system up from EM4
GPIO_EM4WU3 PF1
Pin can be used to wake the system up from EM4
GPIO_EM4WU4 PF2
Pin can be used to wake the system up from EM4
GPIO_EM4WU5 PE13
Pin can be used to wake the system up from EM4
HFXTAL_N
PB14
High Frequency Crystal negative pin. Also used as external optional clock input pin.
HFXTAL_P
PB13
High Frequency Crystal positive pin.
I2C0_SCL
PA1 PD7 PC7 PD15 PC1 PF1 PE13 I2C0 Serial Clock Line input / output.
I2C0_SDA
PA0 PD6 PC6 PD14 PC0 PF0 PE12 I2C0 Serial Data input / output.
I2C1_SCL
PC5 PB12 PE1
I2C1 Serial Clock Line input / output.
I2C1_SDA
PC4 PB11 PE0
I2C1 Serial Data input / output.
LCD_BCAP_N PA13
LCD voltage booster (optional), boost capacitor, negative pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P.
LCD_BCAP_P PA12
LCD voltage booster (optional), boost capacitor, positive pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P.
LCD voltage booster (optional), boost output. If using the LCD voltage booster, connect a 1 uF capacitor between this pin and VSS.
LCD_BEXT
PA14
An external LCD voltage may also be applied to this pin if the booster is not enabled.
If AVDD is used directly as the LCD supply voltage, this pin may be left unconnected or used as a GPIO.
LCD_COM0
PE4
LCD driver common line number 0.
LCD_COM1
PE5
LCD driver common line number 1.
LCD_COM2
PE6
LCD driver common line number 2.
LCD_COM3
PE7
LCD driver common line number 3.
LCD_SEG0
PF2
LCD segment line 0. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
LCD_SEG1
PF3
LCD segment line 1. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
LCD_SEG2
PF4
LCD segment line 2. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
LCD_SEG3
PF5
LCD segment line 3. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
LCD_SEG4
PE8
LCD segment line 4. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
LCD_SEG5
PE9
LCD segment line 5. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
silabs.com | Building a more connected world.
Rev. 2.30 | 315
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
LCD_SEG6
PE10
LCD segment line 6. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
LCD_SEG7
PE11
LCD segment line 7. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
LCD_SEG8
PE12
LCD segment line 8. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG9
PE13
LCD segment line 9. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG10
PE14
LCD segment line 10. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG11
PE15
LCD segment line 11. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG12
PA15
LCD segment line 12. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG13
PA0
LCD segment line 13. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG14
PA1
LCD segment line 14. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG15
PA2
LCD segment line 15. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG16
PA3
LCD segment line 16. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG17
PA4
LCD segment line 17. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG18
PA5
LCD segment line 18. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG19
PA6
LCD segment line 19. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG20/ LCD_COM4
PB3
LCD segment line 20. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 4
LCD_SEG21/ LCD_COM5
PB4
LCD segment line 21. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 5
LCD_SEG22/ LCD_COM6
PB5
LCD segment line 22. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 6
LCD_SEG23/ LCD_COM7
PB6
LCD segment line 23. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 7
LCD_SEG24
PF6
LCD segment line 24. Segments 24, 25, 26 and 27 are controlled by SEGEN6.
LCD_SEG25
PF7
LCD segment line 25. Segments 24, 25, 26 and 27 are controlled by SEGEN6.
LCD_SEG26
PF8
LCD segment line 26. Segments 24, 25, 26 and 27 are controlled by SEGEN6.
silabs.com | Building a more connected world.
Rev. 2.30 | 316
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
LCD_SEG27
PF9
LCD segment line 27. Segments 24, 25, 26 and 27 are controlled by SEGEN6.
LCD_SEG28
PD9
LCD segment line 28. Segments 28, 29, 30 and 31 are controlled by SEGEN7.
LCD_SEG29
PD10
LCD segment line 29. Segments 28, 29, 30 and 31 are controlled by SEGEN7.
LCD_SEG30
PD11
LCD segment line 30. Segments 28, 29, 30 and 31 are controlled by SEGEN7.
LCD_SEG31
PD12
LCD segment line 31. Segments 28, 29, 30 and 31 are controlled by SEGEN7.
LCD_SEG32
PB0
LCD segment line 32. Segments 32, 33, 34 and 35 are controlled by SEGEN8.
LCD_SEG33
PB1
LCD segment line 33. Segments 32, 33, 34 and 35 are controlled by SEGEN8.
LCD_SEG34
PB2
LCD segment line 34. Segments 32, 33, 34 and 35 are controlled by SEGEN8.
LCD_SEG35
PA7
LCD segment line 35. Segments 32, 33, 34 and 35 are controlled by SEGEN8.
LCD_SEG36
PA8
LCD segment line 36. Segments 36, 37, 38 and 39 are controlled by SEGEN9.
LCD_SEG37
PA9
LCD segment line 37. Segments 36, 37, 38 and 39 are controlled by SEGEN9.
LCD_SEG38
PA10
LCD segment line 38. Segments 36, 37, 38 and 39 are controlled by SEGEN9.
LCD_SEG39
PA11
LCD segment line 39. Segments 36, 37, 38 and 39 are controlled by SEGEN9.
LES_ALTEX0 PD6
LESENSE alternate exite output 0.
LES_ALTEX1 PD7
LESENSE alternate exite output 1.
LES_ALTEX2 PA3
LESENSE alternate exite output 2.
LES_ALTEX3 PA4
LESENSE alternate exite output 3.
LES_ALTEX4 PA5
LESENSE alternate exite output 4.
LES_ALTEX5 PE11
LESENSE alternate exite output 5.
LES_ALTEX6 PE12
LESENSE alternate exite output 6.
LES_ALTEX7 PE13
LESENSE alternate exite output 7.
LES_CH0
PC0
LESENSE channel 0.
LES_CH1
PC1
LESENSE channel 1.
LES_CH2
PC2
LESENSE channel 2.
LES_CH3
PC3
LESENSE channel 3.
LES_CH4
PC4
LESENSE channel 4.
LES_CH5
PC5
LESENSE channel 5.
LES_CH6
PC6
LESENSE channel 6.
silabs.com | Building a more connected world.
Rev. 2.30 | 317
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
LES_CH7
PC7
LESENSE channel 7.
LES_CH8
PC8
LESENSE channel 8.
LES_CH9
PC9
LESENSE channel 9.
LES_CH10
PC10
LESENSE channel 10.
LES_CH11
PC11
LESENSE channel 11.
LES_CH12
PC12
LESENSE channel 12.
LES_CH13
PC13
LESENSE channel 13.
LES_CH14
PC14
LESENSE channel 14.
LES_CH15
PC15
LESENSE channel 15.
LETIM0_OUT0 PD6 PB11 PF0 PC4
Low Energy Timer LETIM0, output channel 0.
LETIM0_OUT1 PD7 PB12 PF1 PC5
Low Energy Timer LETIM0, output channel 1.
LEU0_RX
PD5 PB14 PE15 PF1 PA0
LEUART0 Receive input.
LEU0_TX
PD4 PB13 PE14 PF0 PF2
LEUART0 Transmit output. Also used as receive input in half duplex communication.
LEU1_RX
PC7 PA6
LEUART1 Receive input.
LEU1_TX
PC6 PA5
LEUART1 Transmit output. Also used as receive input in half duplex communication.
LFXTAL_N
PB8
Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin.
OPAMP_N0 / DAC0_N0
PC5
Operational Amplifier 0 external negative input.
OPAMP_N1 / DAC0_N1
PD7
Operational Amplifier 1 external negative input.
OPAMP_N2
PD3
Operational Amplifier 2 external negative input.
OPAMP_OUT2 PD5 PD0
Operational Amplifier 2 output.
OPAMP_P0 / DAC0_P0
PC4
Operational Amplifier 0 external positive input.
OPAMP_P1 / DAC0_P1
PD6
Operational Amplifier 1 external positive input.
OPAMP_P2
PD4
Operational Amplifier 2 external positive input.
LFXTAL_P
PB7
Low Frequency Crystal (typically 32.768 kHz) positive pin.
PCNT0_S0IN PC13 PE0 PC0 PD6
Pulse Counter PCNT0 input number 0.
PCNT0_S1IN PC14 PE1 PC1 PD7
Pulse Counter PCNT0 input number 1.
PCNT1_S0IN PC4 PB3
Pulse Counter PCNT1 input number 0.
PCNT1_S1IN PC5 PB4
Pulse Counter PCNT1 input number 1.
PCNT2_S0IN PD0 PE8
Pulse Counter PCNT2 input number 0.
PCNT2_S1IN PD1 PE9
Pulse Counter PCNT2 input number 1.
PRS_CH0
PA0 PF3
Peripheral Reflex System PRS, channel 0.
silabs.com | Building a more connected world.
Rev. 2.30 | 318
Alternate
LOCATION
Functionality
0
1
2
3
4
5
PRS_CH1
PA1 PF4
PRS_CH2
PC0 PF5
PRS_CH3
PC1 PE8
TIM0_CC0
PA0 PA0 PF6 PD1 PA0 PF0
TIM0_CC1
PA1 PA1 PF7 PD2 PC0 PF1
TIM0_CC2
PA2 PA2 PF8 PD3 PC1 PF2
TIM0_CDTI0
PA3 PC13 PF3 PC13 PC2 PF3
TIM0_CDTI1
PA4 PC14 PF4 PC14 PC3 PF4
TIM0_CDTI2
TIM1_CC0 TIM1_CC1 TIM1_CC2 TIM2_CC0 TIM2_CC1 TIM2_CC2 TIM3_CC0 TIM3_CC1 TIM3_CC2 U0_RX
U0_TX
U1_RX
U1_TX
US0_CLK US0_CS
PA5 PC15 PF5 PC15 PC4 PF5
PC13 PC14 PC15 PA8 PA9 PA10 PE14 PE15 PA15 PF7
PE10 PE11 PE12 PA12 PA13 PA14 PE0 PE1 PE2 PE1
PB0 PB1 PB2 PC8 PC9 PC10
PA4
PB7 PB8 PB11
PC15
PD6 PD7 PC13
PF6 PE0 PA3 PC14
PC13
PB10 PE3
PC12
PB9 PE2
PE12 PE5 PC9 PC15 PB13 PB13 PE13 PE4 PC8 PC14 PB14 PB14
US0_RX
PE11 PE6 PC10 PE12 PB8 PC1
US0_TX
US1_CLK US1_CS
PE10 PE7 PC11 PE13 PB7 PC0
PB7 PD2 PF0 PB8 PD3 PF1
EFM32LG Data Sheet
Pin Definitions
6
Description
Peripheral Reflex System PRS, channel 1.
Peripheral Reflex System PRS, channel 2.
Peripheral Reflex System PRS, channel 3.
Timer 0 Capture Compare input / output channel 0.
Timer 0 Capture Compare input / output channel 1.
Timer 0 Capture Compare input / output channel 2.
Timer 0 Complimentary Deat Time Insertion channel 0.
Timer 0 Complimentary Deat Time Insertion channel 1.
Timer 0 Complimentary Deat Time Insertion channel 2.
Timer 1 Capture Compare input / output channel 0.
Timer 1 Capture Compare input / output channel 1.
Timer 1 Capture Compare input / output channel 2.
Timer 2 Capture Compare input / output channel 0.
Timer 2 Capture Compare input / output channel 1.
Timer 2 Capture Compare input / output channel 2.
Timer 3 Capture Compare input / output channel 0.
Timer 3 Capture Compare input / output channel 1.
Timer 3 Capture Compare input / output channel 2.
UART0 Receive input.
UART0 Transmit output. Also used as receive input in half duplex communication.
UART1 Receive input.
UART1 Transmit output. Also used as receive input in half duplex communication.
USART0 clock input / output.
USART0 chip select input / output.
USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output (MISO).
USART0 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input (MOSI).
USART1 clock input / output.
USART1 chip select input / output.
silabs.com | Building a more connected world.
Rev. 2.30 | 319
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
US1_RX
PC1 PD1 PD6
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output (MISO).
US1_TX
PC0 PD0 PD7
USART1 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input (MOSI).
US2_CLK
PC4 PB5
USART2 clock input / output.
US2_CS
PC5 PB6
USART2 chip select input / output.
US2_RX
PC3 PB4
USART2 Asynchronous Receive.
USART2 Synchronous mode Master Input / Slave Output (MISO).
US2_TX
PC2 PB3
USART2 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART2 Synchronous mode Master Output / Slave Input (MOSI).
5.15.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG890 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.45. GPIO Pinout
Port
Port A Port B Port C Port D Port E Port F
Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 15 14 13 12 11 10 PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 -- -- -- -- -- -- PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0
silabs.com | Building a more connected world.
Rev. 2.30 | 320
5.15.4 Opamp Pinout Overview
The specific opamp terminals available in EFM32LG890 is shown in the following figure.
PC4
+ OUT0ALT
PC5
OPA0 -
OUT0
PD4
+
PD3
OPA2 -
OUT2
PD6
+ OUT1ALT
PD7
OPA1 -
OUT1
PB11 PB12 PC0 PC1 PC2 PC3 PC12 PC13 PC14 PC15 PD0 PD1 PD5
Figure 5.30. Opamp Pinout
EFM32LG Data Sheet
Pin Definitions
silabs.com | Building a more connected world.
Rev. 2.30 | 321
5.16 EFM32LG895 (BGA120)
EFM32LG Data Sheet
Pin Definitions
5.16.1 Pinout
The EFM32LG895 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question.
Figure 5.31. EFM32LG895 Pinout (top view, not to scale)
silabs.com | Building a more connected world.
Rev. 2.30 | 322
EFM32LG Data Sheet
Pin Definitions
Table 5.46. Device Pinout
BGA120 Pin# and Name
Pin # Pin Name
A1
PE15
A2
PE14
A3
PE12
A4
PE9
A5
PD11
A6
PD9
A7
PF7
A8
PF5
A9
PF4
Analog LCD_SEG11 LCD_SEG10
LCD_SEG8
LCD_SEG5 LCD_SEG30 LCD_SEG28 LCD_SEG25 LCD_SEG3 LCD_SEG2
Pin Alternate Functionality / Description
EBI EBI_AD07 #0/1/2 EBI_AD06 #0/1/2
EBI_AD04 #0/1/2
EBI_AD01 #0/1/2 EBI_CS2 #0/1/2 EBI_CS0 #0/1/2 EBI_BL1 #0/1/2 EBI_REn #0/2 EBI_WEn #0/2
Timers TIM3_CC1 #0 TIM3_CC0 #0 TIM1_CC2 #1 PCNT2_S1IN #1
TIM0_CC1 #2 TIM0_CDTI2 #2/5 TIM0_CDTI1 #2/5
Communication LEU0_RX #2 LEU0_TX #2 US0_RX #3 US0_CLK #0 I2C0_SDA #6
U0_RX #0
A10
PF2
LCD_SEG0
EBI_ARDY #0/1/2
TIM0_CC2 #5
LEU0_TX #4
A11 USB_VREGI Input to internal 3.3V USB regulator
A12 USB_VREGO Output and decoupling for internal 3.3V USB regulator
A13
PF11
B1
PA15
LCD_SEG12
EBI_AD08 #0/1/2
TIM3_CC2 #0
B2
PE13
LCD_SEG9
EBI_AD05 #0/1/2
B3
PE11
B4
PE8
B5
PD12
B6
PD10
B7
PF8
B8
PF6
B9
PF3
LCD_SEG7
LCD_SEG4 LCD_SEG31 LCD_SEG29 LCD_SEG26 LCD_SEG24
LCD_SEG1
EBI_AD03 #0/1/2
TIM1_CC1 #1
EBI_AD00 #0/1/2 EBI_CS3 #0/1/2 EBI_CS1 #0/1/2
EBI_WEn #1 EBI_BL0 #0/1/2
PCNT2_S0IN #1
TIM0_CC2 #2 TIM0_CC0 #2
EBI_ALE #0
TIM0_CDTI0 #2/5
B10
PF1
TIM0_CC1 #5 LETIM0_OUT1 #2
B11
PF12
B12 USB_VBUS USB 5.0 V VBUS input.
B13
PF10
C1
PA1
LCD_SEG14
EBI_AD10 #0/1/2 TIM0_CC1 #0/1
U1_RX #1 US0_TX #3 US0_CS #0 I2C0_SCL #6 US0_RX #0
U0_TX #0
US1_CS #2 LEU0_RX #3 I2C0_SCL #5
U1_TX #1 I2C0_SCL #0
Other
CMU_CLK1 #2 LES_ALTEX6 #0
PRS_CH2 #1 PRS_CH1 #1 ACMP1_O #0 DBG_SWO #0 GPIO_EM4WU4
LES_ALTEX7 #0 ACMP0_O #0
GPIO_EM4WU5 LES_ALTEX5 #0
BOOT_RX PRS_CH3 #1
ETM_TCLK #1
PRS_CH0 #1 ETM_TD3 #1 DBG_SWDIO
#0/1/2/3 GPIO_EM4WU3
CMU_CLK1 #0 PRS_CH1 #0
silabs.com | Building a more connected world.
Rev. 2.30 | 323
EFM32LG Data Sheet
Pin Definitions
BGA120 Pin# and Name
Pin # Pin Name
C2
PA0
C3
PE10
C4
PD13
C5
VSS
C6
IOVDD_0
C7
PF9
C8
VSS
C9
IOVDD_1
C10
PF0
C11
PE4
C12
PC14
C13
PC15
D1
PA3
D2
PA2
D3
PB15
D11
PE5
D12
PC12
D13
PC13
E1
PA6
E2
PA5
E3
PA4
E11
PE6
E12
PC10
E13
PC11
Analog LCD_SEG13 LCD_SEG6
Pin Alternate Functionality / Description
EBI EBI_AD09 #0/1/2 EBI_AD02 #0/1/2
Timers TIM0_CC0 #0/1/4
TIM1_CC0 #1
Communication
LEU0_RX #4 I2C0_SDA #0
US0_TX #0
Ground.
Digital IO power supply 0.
LCD_SEG27
EBI_REn #1
Ground.
Digital IO power supply 1.
LCD_COM0
ACMP1_CH6 DAC0_OUT1ALT
#2/ OPAMP_OUT1ALT
ACMP1_CH7 DAC0_OUT1ALT
#3/ OPAMP_OUT1ALT
EBI_A11 #0/1/2
TIM0_CC0 #5 LETIM0_OUT0 #2
US1_CLK #2 LEU0_TX #3 I2C0_SDA #5
US0_CS #1
TIM0_CDTI1 #1/3 TIM1_CC1 #0
PCNT0_S1IN #0
US0_CS #3 U0_TX #3
TIM0_CDTI2 #1/3 TIM1_CC2 #0
US0_CLK #3 U0_RX #3
LCD_SEG16
EBI_AD12 #0/1/2 TIM0_CDTI0 #0
U0_TX #2
LCD_SEG15
EBI_AD11 #0/1/2 TIM0_CC2 #0/1
LCD_COM1
ACMP1_CH4 DAC0_OUT1ALT
#0/ OPAMP_OUT1ALT
ACMP1_CH5 DAC0_OUT1ALT
#1/ OPAMP_OUT1ALT
EBI_A12 #0/1/2
TIM0_CDTI0 #1/3 TIM1_CC0 #0 TIM1_CC2 #4
PCNT0_S0IN #0
LCD_SEG19
EBI_AD15 #0/1/2
LCD_SEG18
EBI_AD14 #0/1/2 TIM0_CDTI2 #0
LCD_SEG17
LCD_COM2 ACMP1_CH2 ACMP1_CH3
EBI_AD13 #0/1/2
EBI_A13 #0/1/2 EBI_A10 #1/2 EBI_ALE #1/2
TIM0_CDTI1 #0 TIM2_CC2 #2
US0_CLK #1 U1_TX #0
U1_RX #0
LEU1_RX #1 LEU1_TX #1
U0_RX #2 US0_RX #1 US0_RX #2 US0_TX #2
Other PRS_CH0 #0 GPIO_EM4WU0
BOOT_TX ETM_TD1 #1
ETM_TD0 #1
DBG_SWCLK #0/1/2/3
LES_CH14 #0
LES_CH15 #0 DBG_SWO #1 LES_ALTEX2 #0 ETM_TD1 #3 CMU_CLK0 #0 ETM_TD0 #3 ETM_TD2 #1
CMU_CLK0 #1 LES_CH12 #0
LES_CH13 #0
ETM_TCLK #3 GPIO_EM4WU1 LES_ALTEX4 #0
ETM_TD3 #3 LES_ALTEX3 #0
ETM_TD2 #3
LES_CH10 #0 LES_CH11 #0
silabs.com | Building a more connected world.
Rev. 2.30 | 324
EFM32LG Data Sheet
Pin Definitions
BGA120 Pin# and Name
Pin # Pin Name
F1
PB0
F2
PB1
F3
PB2
F11
PE7
F12
PC8
F13
PC9
G1
PB3
G2
PB4
G3
IOVDD_2
G11
PE0
G12
PE1
G13
PE3
H1
PB5
H2
PB6
H3
VSS
H11 VDD_DREG
H12
PE2
H13
PC7
J1
PD14
J2
PD15
J3
VSS
J11
IOVDD_3
J12
PC6
J13 DECOUPLE
K1
PC0
K2
PC1
Pin Alternate Functionality / Description
Analog
EBI
Timers
Communication
Other
LCD_SEG32
EBI_A16 #0/1/2
TIM1_CC0 #2
LCD_SEG33
EBI_A17 #0/1/2
TIM1_CC1 #2
LCD_SEG34
EBI_A18 #0/1/2
TIM1_CC2 #2
LCD_COM3
EBI_A14 #0/1/2
US0_TX #1
ACMP1_CH0
EBI_A15 #0/1/2
TIM2_CC0 #2
US0_CS #2
LES_CH8 #0
ACMP1_CH1
EBI_A09 #1/2
TIM2_CC1 #2
US0_CLK #2
LES_CH9 #0 GPIO_EM4WU2
LCD_SEG20/ LCD_COM4
EBI_A19 #0/1/2
PCNT1_S0IN #1
US2_TX #1
LCD_SEG21/ LCD_COM5
EBI_A20 #0/1/2
PCNT1_S1IN #1
US2_RX #1
Digital IO power supply 2.
EBI_A07 #0/1/2
TIM3_CC0 #1 PCNT0_S0IN #1
U0_TX #1 I2C1_SDA #2
EBI_A08 #0/1/2
TIM3_CC1 #1 PCNT0_S1IN #1
U0_RX #1 I2C1_SCL #2
BU_STAT
EBI_A10 #0
U1_RX #3
ACMP1_O #1
LCD_SEG22/ LCD_COM6
EBI_A21 #0/1/2
US2_CLK #1
LCD_SEG23/ LCD_COM7
EBI_A22 #0/1/2
US2_CS #1
Ground.
Power supply for on-chip voltage regulator.
BU_VOUT
EBI_A09 #0
TIM3_CC2 #1
U1_TX #3
ACMP0_O #1
ACMP0_CH7
EBI_A06 #0/1/2
LEU1_RX #0 I2C0_SCL #2
LES_CH7 #0 ETM_TD0 #2
I2C0_SDA #3
I2C0_SCL #3
Ground.
Digital IO power supply 3.
ACMP0_CH6
EBI_A05 #0/1/2
LEU1_TX #0 I2C0_SDA #2
LES_CH6 #0 ETM_TCLK #2
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin.
ACMP0_CH0 DAC0_OUT0ALT
#0/ OPAMP_OUT0ALT
EBI_A23 #0/1/2
TIM0_CC1 #4 PCNT0_S0IN #2
US0_TX #5 US1_TX #0 I2C0_SDA #4
LES_CH0 #0 PRS_CH2 #0
ACMP0_CH1 DAC0_OUT0ALT
#1/ OPAMP_OUT0ALT
EBI_A24 #0/1/2
TIM0_CC2 #4 PCNT0_S1IN #2
US0_RX #5 US1_RX #0 I2C0_SCL #4
LES_CH1 #0 PRS_CH3 #0
silabs.com | Building a more connected world.
Rev. 2.30 | 325
EFM32LG Data Sheet
Pin Definitions
BGA120 Pin# and Name
Pin # Pin Name
K3
IOVDD_4
K11
VSS
K12
VSS
K13
PD8
L1
PC2
L2
PC3
L3
PA7
L4
IOVDD_5
L5
VSS
L6
VSS
L7
IOVDD_6
L8
PB9
L9
PB10
L10
PD0
L11
PD1
L12
PD4
Pin Alternate Functionality / Description
Analog
EBI
Digital IO power supply 4.
Ground.
Ground.
BU_VIN
ACMP0_CH2 DAC0_OUT0ALT
#2/ OPAMP_OUT0ALT
EBI_A25 #0/1/2
ACMP0_CH3 DAC0_OUT0ALT
#3/ OPAMP_OUT0ALT
EBI_NANDREn #0/1/2
LCD_SEG35
EBI_CSTFT #0/1/2
Digital IO power supply 5.
Ground.
Ground.
Digital IO power supply 6.
EBI_A03 #0/1/2
EBI_A04 #0/1/2
ADC0_CH0 DAC0_OUT0ALT
#4/ OPAMP_OUT0ALT OPAMP_OUT2 #1
ADC0_CH1 DAC0_OUT1ALT
#4/ OPAMP_OUT1ALT
ADC0_CH4 OPAMP_P2
Timers
TIM0_CDTI0 #4 TIM0_CDTI1 #4
PCNT2_S0IN #0 TIM0_CC0 #3
PCNT2_S1IN #0
Communication
US2_TX #0 US2_RX #0
U1_TX #2 U1_RX #2 US1_TX #1 US1_RX #1 LEU0_TX #0
L13
PD7
ADC0_CH7 / DAC0_N1 / OPAMP_N1
TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3
US1_TX #2 I2C0_SCL #1
M1
PB7
M2
PC4
M3
PA8
M4
PA10
M5
PA13
M6
PA14
LFXTAL_P
ACMP0_CH4 / DAC0_P0 / OPAMP_P0 LCD_SEG36 LCD_SEG38
LCD_BCAP_N LCD_BEXT
TIM1_CC0 #3
EBI_A26 #0/1/2
TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0
EBI_DCLK #0/1/2
TIM2_CC0 #0
EBI_VSNC #0/1/2
TIM2_CC2 #0
EBI_A01 #0/1/2
TIM2_CC1 #1
EBI_A02 #0/1/2
TIM2_CC2 #1
US0_TX #4 US1_CLK #0
US2_CLK #0 I2C1_SDA #0
Other
CMU_CLK1 #1 LES_CH2 #0 LES_CH3 #0
DBG_SWO #2 ETM_TD2 #0/2 CMU_CLK0 #2 LES_ALTEX1 #0 ACMP1_O #2 ETM_TCLK #0 LES_CH4 #0
silabs.com | Building a more connected world.
Rev. 2.30 | 326
EFM32LG Data Sheet
Pin Definitions
BGA120 Pin# and Name
Pin # Pin Name
M7
RESETn
M8
AVSS_1
M9
AVDD_2
M10
AVDD_1
M11
AVSS_0
M12
PD3
M13
PD6
N1
PB8
N2
PC5
N3
PA9
N4
PA11
N5
PA12
N6
PB11
N7
PB12
N8
AVSS_2
N9
PB13
N10
PB14
N11
AVDD_0
N12
PD2
N13
PD5
Pin Alternate Functionality / Description
Analog
EBI
Timers
Communication
Other
Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released.
Analog ground 1.
Analog power supply 2.
Analog power supply 1.
Analog ground 0.
ADC0_CH3 OPAMP_N2
TIM0_CC2 #3
US1_CS #1
ETM_TD1 #0/2
ADC0_CH6 / DAC0_P1 / OPAMP_P1
TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3
US1_RX #2 I2C0_SDA #1
LES_ALTEX0 #0 ACMP0_O #2 ETM_TD0 #0
LFXTAL_N
TIM1_CC1 #3
US0_RX #4 US1_CS #0
ACMP0_CH5 / DAC0_N0 / OPAMP_N0
EBI_NANDWEn #0/1/2
LETIM0_OUT1 #3 PCNT1_S1IN #0
US2_CS #0 I2C1_SCL #0
LES_CH5 #0
LCD_SEG37
EBI_DTEN #0/1/2
TIM2_CC1 #0
LCD_SEG39
EBI_HSNC #0/1/2
LCD_BCAP_P
EBI_A00 #0/1/2
TIM2_CC0 #1
DAC0_OUT0 / OPAMP_OUT0
TIM1_CC2 #3 LETIM0_OUT0 #1
I2C1_SDA #1
DAC0_OUT1 / OPAMP_OUT1
LETIM0_OUT1 #1
I2C1_SCL #1
Analog ground 2.
HFXTAL_P
US0_CLK #4/5 LEU0_TX #1
HFXTAL_N
US0_CS #4/5 LEU0_RX #1
Analog power supply 0.
ADC0_CH2
EBI_A27 #0/1/2
TIM0_CC1 #3
US1_CLK #1
DBG_SWO #3
ADC0_CH5 OPAMP_OUT2 #0
LEU0_RX #0
ETM_TD3 #0/2
silabs.com | Building a more connected world.
Rev. 2.30 | 327
EFM32LG Data Sheet
Pin Definitions
5.16.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0.
Alternate Functionality ACMP0_CH0 ACMP0_CH1 ACMP0_CH2 ACMP0_CH3 ACMP0_CH4 ACMP0_CH5 ACMP0_CH6 ACMP0_CH7 ACMP0_O ACMP1_CH0 ACMP1_CH1 ACMP1_CH2 ACMP1_CH3 ACMP1_CH4 ACMP1_CH5 ACMP1_CH6 ACMP1_CH7 ACMP1_O ADC0_CH0
ADC0_CH1
ADC0_CH2
ADC0_CH3
ADC0_CH4
ADC0_CH5
ADC0_CH6
Table 5.47. Alternate Functionality Overview
LOCATION
0
1
2
3
4
5
6
Description
PC0
Analog comparator ACMP0, channel 0.
PC1
Analog comparator ACMP0, channel 1.
PC2
Analog comparator ACMP0, channel 2.
PC3
Analog comparator ACMP0, channel 3.
PC4
Analog comparator ACMP0, channel 4.
PC5
Analog comparator ACMP0, channel 5.
PC6
Analog comparator ACMP0, channel 6.
PC7
Analog comparator ACMP0, channel 7.
PE13 PE2 PD6
Analog comparator ACMP0, digital output.
PC8
Analog comparator ACMP1, channel 0.
PC9
Analog comparator ACMP1, channel 1.
PC10
Analog comparator ACMP1, channel 2.
PC11
Analog comparator ACMP1, channel 3.
PC12
Analog comparator ACMP1, channel 4.
PC13
Analog comparator ACMP1, channel 5.
PC14
Analog comparator ACMP1, channel 6.
PC15
Analog comparator ACMP1, channel 7.
PF2 PE3 PD7
Analog comparator ACMP1, digital output.
PD0
Analog to digital converter ADC0, input channel number 0.
PD1
Analog to digital converter ADC0, input channel number 1.
PD2
Analog to digital converter ADC0, input channel number 2.
PD3
Analog to digital converter ADC0, input channel number 3.
PD4
Analog to digital converter ADC0, input channel number 4.
PD5
Analog to digital converter ADC0, input channel number 5.
PD6
Analog to digital converter ADC0, input channel number 6.
silabs.com | Building a more connected world.
Rev. 2.30 | 328
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
ADC0_CH7
PD7
Analog to digital converter ADC0, input channel number 7.
BOOT_RX
PE11
Bootloader RX.
BOOT_TX
PE10
Bootloader TX.
BU_STAT
PE3
Backup Power Domain status, whether or not the system is in backup mode
BU_VIN
PD8
Battery input for Backup Power Domain
BU_VOUT
PE2
Power output for Backup Power Domain
CMU_CLK0
PA2 PC12 PD7
Clock Management Unit, clock output number 0.
CMU_CLK1
PA1 PD8 PE12
Clock Management Unit, clock output number 1.
DAC0_OUT0 / OPAMP_OUT0
PB11
Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0.
DAC0_OUT0ALT / OPAMP_OUT0ALT
PC0
PC1
PC2
PC3
PD0
Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0.
DAC0_OUT1 / OPAMP_OUT1
PB12
Digital to Analog Converter DAC0_OUT1 / OPAMP output channel number 1.
DAC0_OUT1ALT / OPAMP_OUT1ALT
PC12
PC13
PC14
PC15
PD1
Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1.
DBG_SWCLK
PF0 PF0 PF0 PF0
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, and has a built-in pull down.
DBG_SWDIO
PF1 PF1 PF1 PF1
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and has a built-in pull up.
DBG_SWO
PF2 PC15 PD1 PD2
Debug-interface Serial Wire viewer Output.
Note that this function is not enabled after reset, and must be enabled by software to be used.
EBI_A00
PA12 PA12 PA12
External Bus Interface (EBI) address output pin 00.
EBI_A01
PA13 PA13 PA13
External Bus Interface (EBI) address output pin 01.
EBI_A02
PA14 PA14 PA14
External Bus Interface (EBI) address output pin 02.
EBI_A03
PB9 PB9 PB9
External Bus Interface (EBI) address output pin 03.
EBI_A04
PB10 PB10 PB10
External Bus Interface (EBI) address output pin 04.
EBI_A05
PC6 PC6 PC6
External Bus Interface (EBI) address output pin 05.
EBI_A06
PC7 PC7 PC7
External Bus Interface (EBI) address output pin 06.
EBI_A07
PE0 PE0 PE0
External Bus Interface (EBI) address output pin 07.
EBI_A08
PE1 PE1 PE1
External Bus Interface (EBI) address output pin 08.
EBI_A09
PE2 PC9 PC9
External Bus Interface (EBI) address output pin 09.
EBI_A10
PE3 PC10 PC10
External Bus Interface (EBI) address output pin 10.
EBI_A11
PE4 PE4 PE4
External Bus Interface (EBI) address output pin 11.
EBI_A12
PE5 PE5 PE5
External Bus Interface (EBI) address output pin 12.
silabs.com | Building a more connected world.
Rev. 2.30 | 329
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
EBI_A13
PE6 PE6 PE6
External Bus Interface (EBI) address output pin 13.
EBI_A14
PE7 PE7 PE7
External Bus Interface (EBI) address output pin 14.
EBI_A15
PC8 PC8 PC8
External Bus Interface (EBI) address output pin 15.
EBI_A16
PB0 PB0 PB0
External Bus Interface (EBI) address output pin 16.
EBI_A17
PB1 PB1 PB1
External Bus Interface (EBI) address output pin 17.
EBI_A18
PB2 PB2 PB2
External Bus Interface (EBI) address output pin 18.
EBI_A19
PB3 PB3 PB3
External Bus Interface (EBI) address output pin 19.
EBI_A20
PB4 PB4 PB4
External Bus Interface (EBI) address output pin 20.
EBI_A21
PB5 PB5 PB5
External Bus Interface (EBI) address output pin 21.
EBI_A22
PB6 PB6 PB6
External Bus Interface (EBI) address output pin 22.
EBI_A23
PC0 PC0 PC0
External Bus Interface (EBI) address output pin 23.
EBI_A24
PC1 PC1 PC1
External Bus Interface (EBI) address output pin 24.
EBI_A25
PC2 PC2 PC2
External Bus Interface (EBI) address output pin 25.
EBI_A26
PC4 PC4 PC4
External Bus Interface (EBI) address output pin 26.
EBI_A27
PD2 PD2 PD2
External Bus Interface (EBI) address output pin 27.
EBI_AD00
PE8 PE8 PE8
External Bus Interface (EBI) address and data input / output pin 00.
EBI_AD01
PE9 PE9 PE9
External Bus Interface (EBI) address and data input / output pin 01.
EBI_AD02
PE10 PE10 PE10
External Bus Interface (EBI) address and data input / output pin 02.
EBI_AD03
PE11 PE11 PE11
External Bus Interface (EBI) address and data input / output pin 03.
EBI_AD04
PE12 PE12 PE12
External Bus Interface (EBI) address and data input / output pin 04.
EBI_AD05
PE13 PE13 PE13
External Bus Interface (EBI) address and data input / output pin 05.
EBI_AD06
PE14 PE14 PE14
External Bus Interface (EBI) address and data input / output pin 06.
EBI_AD07
PE15 PE15 PE15
External Bus Interface (EBI) address and data input / output pin 07.
EBI_AD08
PA15 PA15 PA15
External Bus Interface (EBI) address and data input / output pin 08.
EBI_AD09
PA0 PA0 PA0
External Bus Interface (EBI) address and data input / output pin 09.
EBI_AD10
PA1 PA1 PA1
External Bus Interface (EBI) address and data input / output pin 10.
EBI_AD11
PA2 PA2 PA2
External Bus Interface (EBI) address and data input / output pin 11.
EBI_AD12
PA3 PA3 PA3
External Bus Interface (EBI) address and data input / output pin 12.
silabs.com | Building a more connected world.
Rev. 2.30 | 330
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
EBI_AD13
PA4 PA4 PA4
External Bus Interface (EBI) address and data input / output pin 13.
EBI_AD14
PA5 PA5 PA5
External Bus Interface (EBI) address and data input / output pin 14.
EBI_AD15
PA6 PA6 PA6
External Bus Interface (EBI) address and data input / output pin 15.
EBI_ALE
PF3 PC11 PC11
External Bus Interface (EBI) Address Latch Enable output.
EBI_ARDY
PF2 PF2 PF2
External Bus Interface (EBI) Hardware Ready Control input.
EBI_BL0
PF6 PF6 PF6
External Bus Interface (EBI) Byte Lane/Enable pin 0.
EBI_BL1
PF7 PF7 PF7
External Bus Interface (EBI) Byte Lane/Enable pin 1.
EBI_CS0
PD9 PD9 PD9
External Bus Interface (EBI) Chip Select output 0.
EBI_CS1
PD10 PD10 PD10
External Bus Interface (EBI) Chip Select output 1.
EBI_CS2
PD11 PD11 PD11
External Bus Interface (EBI) Chip Select output 2.
EBI_CS3
PD12 PD12 PD12
External Bus Interface (EBI) Chip Select output 3.
EBI_CSTFT
PA7 PA7 PA7
External Bus Interface (EBI) Chip Select output TFT.
EBI_DCLK
PA8 PA8 PA8
External Bus Interface (EBI) TFT Dot Clock pin.
EBI_DTEN
PA9 PA9 PA9
External Bus Interface (EBI) TFT Data Enable pin.
EBI_HSNC
PA11 PA11 PA11
External Bus Interface (EBI) TFT Horizontal Synchronization pin.
EBI_NANDREn
PC3 PC3 PC3
External Bus Interface (EBI) NAND Read Enable output.
EBI_NANDWEn
PC5 PC5 PC5
External Bus Interface (EBI) NAND Write Enable output.
EBI_REn
PF5 PF9 PF5
External Bus Interface (EBI) Read Enable output.
EBI_VSNC
PA10 PA10 PA10
External Bus Interface (EBI) TFT Vertical Synchronization pin.
EBI_WEn
PF4 PF8 PF4
External Bus Interface (EBI) Write Enable output.
ETM_TCLK
PD7 PF8 PC6 PA6
Embedded Trace Module ETM clock .
ETM_TD0
PD6 PF9 PC7 PA2
Embedded Trace Module ETM data 0.
ETM_TD1
PD3 PD13 PD3 PA3
Embedded Trace Module ETM data 1.
ETM_TD2
PD4 PB15 PD4 PA4
Embedded Trace Module ETM data 2.
ETM_TD3
PD5 PF3 PD5 PA5
Embedded Trace Module ETM data 3.
GPIO_EM4WU0 PA0
Pin can be used to wake the system up from EM4
GPIO_EM4WU1 PA6
Pin can be used to wake the system up from EM4
GPIO_EM4WU2 PC9
Pin can be used to wake the system up from EM4
GPIO_EM4WU3 PF1
Pin can be used to wake the system up from EM4
silabs.com | Building a more connected world.
Rev. 2.30 | 331
Alternate Functionality GPIO_EM4WU4 GPIO_EM4WU5 HFXTAL_N HFXTAL_P I2C0_SCL I2C0_SDA I2C1_SCL I2C1_SDA
LCD_BCAP_N
LCD_BCAP_P
LCD_BEXT
LCD_COM0 LCD_COM1 LCD_COM2 LCD_COM3 LCD_SEG0 LCD_SEG1 LCD_SEG2 LCD_SEG3 LCD_SEG4 LCD_SEG5 LCD_SEG6
EFM32LG Data Sheet
Pin Definitions
LOCATION
0
1
2
3
4
5
6
Description
PF2
Pin can be used to wake the system up from EM4
PE13
Pin can be used to wake the system up from EM4
PB14
High Frequency Crystal negative pin. Also used as external optional clock input pin.
PB13
High Frequency Crystal positive pin.
PA1 PD7 PC7 PD15 PC1 PF1 PE13 I2C0 Serial Clock Line input / output.
PA0 PD6 PC6 PD14 PC0 PF0 PE12 I2C0 Serial Data input / output.
PC5 PB12 PE1
I2C1 Serial Clock Line input / output.
PC4 PB11 PE0
I2C1 Serial Data input / output.
PA13
LCD voltage booster (optional), boost capacitor, negative pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P.
PA12
LCD voltage booster (optional), boost capacitor, positive pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P.
LCD voltage booster (optional), boost output. If using the LCD voltage booster, connect a 1 uF capacitor between this pin and VSS.
PA14
An external LCD voltage may also be applied to this pin if the booster is not enabled.
If AVDD is used directly as the LCD supply voltage, this pin may be left unconnected or used as a GPIO.
PE4
LCD driver common line number 0.
PE5
LCD driver common line number 1.
PE6
LCD driver common line number 2.
PE7
LCD driver common line number 3.
PF2
LCD segment line 0. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
PF3
LCD segment line 1. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
PF4
LCD segment line 2. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
PF5
LCD segment line 3. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
PE8
LCD segment line 4. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
PE9
LCD segment line 5. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
PE10
LCD segment line 6. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
silabs.com | Building a more connected world.
Rev. 2.30 | 332
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
LCD_SEG7
PE11
LCD segment line 7. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
LCD_SEG8
PE12
LCD segment line 8. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG9
PE13
LCD segment line 9. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG10
PE14
LCD segment line 10. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG11
PE15
LCD segment line 11. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG12
PA15
LCD segment line 12. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG13
PA0
LCD segment line 13. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG14
PA1
LCD segment line 14. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG15
PA2
LCD segment line 15. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG16
PA3
LCD segment line 16. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG17
PA4
LCD segment line 17. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG18
PA5
LCD segment line 18. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG19
PA6
LCD segment line 19. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG20/ LCD_COM4
PB3
LCD segment line 20. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 4
LCD_SEG21/ LCD_COM5
PB4
LCD segment line 21. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 5
LCD_SEG22/ LCD_COM6
PB5
LCD segment line 22. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 6
LCD_SEG23/ LCD_COM7
PB6
LCD segment line 23. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 7
LCD_SEG24
PF6
LCD segment line 24. Segments 24, 25, 26 and 27 are controlled by SEGEN6.
LCD_SEG25
PF7
LCD segment line 25. Segments 24, 25, 26 and 27 are controlled by SEGEN6.
LCD_SEG26
PF8
LCD segment line 26. Segments 24, 25, 26 and 27 are controlled by SEGEN6.
LCD_SEG27
PF9
LCD segment line 27. Segments 24, 25, 26 and 27 are controlled by SEGEN6.
silabs.com | Building a more connected world.
Rev. 2.30 | 333
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
LCD_SEG28
PD9
LCD segment line 28. Segments 28, 29, 30 and 31 are controlled by SEGEN7.
LCD_SEG29
PD10
LCD segment line 29. Segments 28, 29, 30 and 31 are controlled by SEGEN7.
LCD_SEG30
PD11
LCD segment line 30. Segments 28, 29, 30 and 31 are controlled by SEGEN7.
LCD_SEG31
PD12
LCD segment line 31. Segments 28, 29, 30 and 31 are controlled by SEGEN7.
LCD_SEG32
PB0
LCD segment line 32. Segments 32, 33, 34 and 35 are controlled by SEGEN8.
LCD_SEG33
PB1
LCD segment line 33. Segments 32, 33, 34 and 35 are controlled by SEGEN8.
LCD_SEG34
PB2
LCD segment line 34. Segments 32, 33, 34 and 35 are controlled by SEGEN8.
LCD_SEG35
PA7
LCD segment line 35. Segments 32, 33, 34 and 35 are controlled by SEGEN8.
LCD_SEG36
PA8
LCD segment line 36. Segments 36, 37, 38 and 39 are controlled by SEGEN9.
LCD_SEG37
PA9
LCD segment line 37. Segments 36, 37, 38 and 39 are controlled by SEGEN9.
LCD_SEG38
PA10
LCD segment line 38. Segments 36, 37, 38 and 39 are controlled by SEGEN9.
LCD_SEG39
PA11
LCD segment line 39. Segments 36, 37, 38 and 39 are controlled by SEGEN9.
LES_ALTEX0
PD6
LESENSE alternate exite output 0.
LES_ALTEX1
PD7
LESENSE alternate exite output 1.
LES_ALTEX2
PA3
LESENSE alternate exite output 2.
LES_ALTEX3
PA4
LESENSE alternate exite output 3.
LES_ALTEX4
PA5
LESENSE alternate exite output 4.
LES_ALTEX5
PE11
LESENSE alternate exite output 5.
LES_ALTEX6
PE12
LESENSE alternate exite output 6.
LES_ALTEX7
PE13
LESENSE alternate exite output 7.
LES_CH0
PC0
LESENSE channel 0.
LES_CH1
PC1
LESENSE channel 1.
LES_CH2
PC2
LESENSE channel 2.
LES_CH3
PC3
LESENSE channel 3.
LES_CH4
PC4
LESENSE channel 4.
LES_CH5
PC5
LESENSE channel 5.
LES_CH6
PC6
LESENSE channel 6.
LES_CH7
PC7
LESENSE channel 7.
LES_CH8
PC8
LESENSE channel 8.
silabs.com | Building a more connected world.
Rev. 2.30 | 334
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
LES_CH9
PC9
LESENSE channel 9.
LES_CH10
PC10
LESENSE channel 10.
LES_CH11
PC11
LESENSE channel 11.
LES_CH12
PC12
LESENSE channel 12.
LES_CH13
PC13
LESENSE channel 13.
LES_CH14
PC14
LESENSE channel 14.
LES_CH15
PC15
LESENSE channel 15.
LETIM0_OUT0
PD6 PB11 PF0 PC4
Low Energy Timer LETIM0, output channel 0.
LETIM0_OUT1
PD7 PB12 PF1 PC5
Low Energy Timer LETIM0, output channel 1.
LEU0_RX
PD5 PB14 PE15 PF1 PA0
LEUART0 Receive input.
LEU0_TX
PD4 PB13 PE14 PF0 PF2
LEUART0 Transmit output. Also used as receive input in half duplex communication.
LEU1_RX
PC7 PA6
LEUART1 Receive input.
LEU1_TX
PC6 PA5
LEUART1 Transmit output. Also used as receive input in half duplex communication.
LFXTAL_N
PB8
Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin.
LFXTAL_P
PB7
Low Frequency Crystal (typically 32.768 kHz) positive pin.
OPAMP_N0 / DAC0_N0
PC5
Operational Amplifier 0 external negative input.
OPAMP_N1 / DAC0_N1
PD7
Operational Amplifier 1 external negative input.
OPAMP_N2
PD3
Operational Amplifier 2 external negative input.
OPAMP_OUT2
PD5 PD0
Operational Amplifier 2 output.
OPAMP_P0 / DAC0_P0
PC4
Operational Amplifier 0 external positive input.
OPAMP_P1 / DAC0_P1
PD6
Operational Amplifier 1 external positive input.
OPAMP_P2
PD4
Operational Amplifier 2 external positive input.
PCNT0_S0IN
PC13 PE0 PC0 PD6
Pulse Counter PCNT0 input number 0.
PCNT0_S1IN
PC14 PE1 PC1 PD7
Pulse Counter PCNT0 input number 1.
PCNT1_S0IN
PC4 PB3
Pulse Counter PCNT1 input number 0.
PCNT1_S1IN
PC5 PB4
Pulse Counter PCNT1 input number 1.
PCNT2_S0IN
PD0 PE8
Pulse Counter PCNT2 input number 0.
PCNT2_S1IN
PD1 PE9
Pulse Counter PCNT2 input number 1.
PRS_CH0
PA0 PF3
Peripheral Reflex System PRS, channel 0.
PRS_CH1
PA1 PF4
Peripheral Reflex System PRS, channel 1.
PRS_CH2
PC0 PF5
Peripheral Reflex System PRS, channel 2.
silabs.com | Building a more connected world.
Rev. 2.30 | 335
Alternate Functionality PRS_CH3 TIM0_CC0 TIM0_CC1 TIM0_CC2 TIM0_CDTI0
TIM0_CDTI1
TIM0_CDTI2 TIM1_CC0 TIM1_CC1 TIM1_CC2 TIM2_CC0 TIM2_CC1 TIM2_CC2 TIM3_CC0 TIM3_CC1 TIM3_CC2 U0_RX U0_TX U1_RX U1_TX US0_CLK US0_CS
US0_RX
US0_TX
US1_CLK US1_CS
US1_RX
LOCATION
0
1
2
3
4
5
PC1 PE8
PA0 PA0 PF6 PD1 PA0 PF0
PA1 PA1 PF7 PD2 PC0 PF1
PA2 PA2 PF8 PD3 PC1 PF2
PA3 PC13 PF3 PC13 PC2 PF3
PA4 PC14 PF4 PC14 PC3 PF4
PA5 PC15 PF5 PC15 PC4 PF5
PC13 PE10 PB0 PB7 PD6 PC14 PE11 PB1 PB8 PD7 PC15 PE12 PB2 PB11 PC13 PA8 PA12 PC8 PA9 PA13 PC9 PA10 PA14 PC10 PE14 PE0 PE15 PE1 PA15 PE2 PF7 PE1 PA4 PC15
PF6 PE0 PA3 PC14
PC13 PF11 PB10 PE3
PC12 PF10 PB9 PE2
PE12 PE5 PC9 PC15 PB13 PB13 PE13 PE4 PC8 PC14 PB14 PB14
PE11 PE6 PC10 PE12 PB8 PC1
PE10 PE7 PC11 PE13 PB7 PC0
PB7 PD2 PF0 PB8 PD3 PF1 PC1 PD1 PD6
EFM32LG Data Sheet
Pin Definitions
6
Description
Peripheral Reflex System PRS, channel 3.
Timer 0 Capture Compare input / output channel 0.
Timer 0 Capture Compare input / output channel 1.
Timer 0 Capture Compare input / output channel 2.
Timer 0 Complimentary Deat Time Insertion channel 0.
Timer 0 Complimentary Deat Time Insertion channel 1.
Timer 0 Complimentary Deat Time Insertion channel 2.
Timer 1 Capture Compare input / output channel 0.
Timer 1 Capture Compare input / output channel 1.
Timer 1 Capture Compare input / output channel 2.
Timer 2 Capture Compare input / output channel 0.
Timer 2 Capture Compare input / output channel 1.
Timer 2 Capture Compare input / output channel 2.
Timer 3 Capture Compare input / output channel 0.
Timer 3 Capture Compare input / output channel 1.
Timer 3 Capture Compare input / output channel 2.
UART0 Receive input.
UART0 Transmit output. Also used as receive input in half duplex communication.
UART1 Receive input.
UART1 Transmit output. Also used as receive input in half duplex communication.
USART0 clock input / output.
USART0 chip select input / output.
USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output (MISO).
USART0 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input (MOSI).
USART1 clock input / output.
USART1 chip select input / output.
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output (MISO).
silabs.com | Building a more connected world.
Rev. 2.30 | 336
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
US1_TX
PC0 PD0 PD7
USART1 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input (MOSI).
US2_CLK
PC4 PB5
USART2 clock input / output.
US2_CS
PC5 PB6
USART2 chip select input / output.
US2_RX
PC3 PB4
USART2 Asynchronous Receive.
USART2 Synchronous mode Master Input / Slave Output (MISO).
US2_TX
PC2 PB3
USART2 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART2 Synchronous mode Master Output / Slave Input (MOSI).
5.16.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG895 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.48. GPIO Pinout
Port
Port A Port B Port C Port D Port E Port F
Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 15 14 13 12 11 10 PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 -- -- -- PF12 PF11 PF10 PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0
5.16.4 Opamp Pinout Overview
The specific opamp terminals available in EFM32LG895 is shown in the following figure.
PC4
+ OUT0ALT
PC5
OPA0 -
OUT0
PD4
+
PD3
OPA2 -
OUT2
PD6
+ OUT1ALT
PD7
OPA1 -
OUT1
PB11 PB12 PC0 PC1 PC2 PC3 PC12 PC13 PC14 PC15 PD0 PD1 PD5
Figure 5.32. Opamp Pinout
silabs.com | Building a more connected world.
Rev. 2.30 | 337
5.17 EFM32LG900 (Wafer)
EFM32LG Data Sheet
Pin Definitions
5.17.1 Padout
The EFM32LG900 padout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pad are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question.
128 PA15 127 PE15 126 PE14 125 PE13 124 PE12 123 iovss_6 122 iovdd_6 121 PE11 120 PE10 119 PE9 118 PE8 117 PB15 116 PD13 115 PD12 114 PD11 113 PD10 112 PD9 111 NC 110 PF9 109 PF8 108 PF7 107 PF6 106 iovdd_5 105 iovss_5 104 PF5 103 PF12 102 PF4 101 usb_vbus 100 PF3
99 PF2 98 PF1 97 PF0 96 iovss_7
PA0 1 PA1 2 PA2 3 PA3 4 PA4 5 PA5 6 PA6 7 iovdd_0 8
iovss_0 9 PD14 10 PD15 11 PB0 12 PB1 13 PB2 14
NC 15
PB3 16 PB4 17
PB5 18 PB6 19 iovss_1 20 iovdd_1 21 PC0 22 PC1 23 PC2 24 PC3 25
PC4 26 PC5 27 PB7 28 PB8 29
95 PF11 94 PC15 93 PF10 92 PC14 91 usb_vrego_1 90 usb_vrego_0 89 usb_vregi_1 88 usb_vregi_0 87 PC13 86 PC12
85 PC11 84 PC10 83 PC9 82 PC8 81 PE7 80 PE6 79 PE5
78 PE4 77 PE3 76 PE2 75 PE1 74 PE0 73 iovss_4 72 NC
71 dec_2 70 dec_1 69 dec_0 68 iovdd_4 67 vdd_dreg 66 vss_dreg 65 PC7 64 PC6 63 PD8 62 PD7 61 PD6 60 PD5
PA7 30 PA8 31 PA9 32 PA10 33 PA11 34 iovdd_2 35 iovss_2 36 PA12 37 PA13 38 PA14 39 reset 40 PB9 41 PB10 42 PB11 43 PB12 44 avss_2 45 avdd_2 46 avdd_1 47 avss_1 48 PB13 49 PB14 50 iovss_3 51 iovdd_3 52 avss_0 53 avdd_0 54 PD0 55 PD1 56 PD2 57 PD3 58 PD4 59
Water Pads
Pad
Pad Name
#
1
PA0
2
PA1
3
PA2
4
PA3
Figure 5.33. EFM32LG900 Padout (top view, not to scale) Table 5.49. Device Padout
Analog LCD_SEG13 LCD_SEG14 LCD_SEG15 LCD_SEG16
Pad Alternative Functionality / Description
EBI
Timers
Communication
Other
EBI_AD09 #0/1/2 TIM0_CC0 #0/1/4 EBI_AD10 #0/1/2 TIM0_CC1 #0/1
LEU0_RX #4 I2C0_SDA #0
I2C0_SCL #0
EBI_AD11 #0/1/2 TIM0_CC2 #0/1
EBI_AD12 #0/1/2 TIM0_CDTI0 #0
U0_TX #2
PRS_CH0 #0 GPIO_EM4WU0
CMU_CLK1 #0 PRS_CH1 #0
CMU_CLK0 #0 ETM_TD0 #3
LES_ALTEX2 #0 ETM_TD1 #3
silabs.com | Building a more connected world.
Rev. 2.30 | 338
Water Pads
Pad
Pad Name
#
5
PA4
6
PA5
7
PA6
8
IOVDD_0
9
IOVSS_0
10
PD14
11
PD15
12
PB0
13
PB1
14
PB2
15
NC
16
PB3
17
PB4
18
PB5
19
PB6
20
IOVSS_1
21
IOVDD_1
22
PC0
23
PC1
24
PC2
25
PC3
26
PC4
Analog
EFM32LG Data Sheet
Pin Definitions
Pad Alternative Functionality / Description
EBI
Timers
Communication
Other
LCD_SEG17
EBI_AD13 #0/1/2 TIM0_CDTI1 #0
U0_RX #2
LCD_SEG18
EBI_AD14 #0/1/2 TIM0_CDTI2 #0
LEU1_TX #1
LCD_SEG19
EBI_AD15 #0/1/2
LEU1_RX #1
Digital IO power supply 0. Digital IO ground 0.
LCD_SEG32
EBI_A16 #0/1/2
LCD_SEG33
EBI_A17 #0/1/2
LCD_SEG34
EBI_A18 #0/1/2
Do not connect.
LCD_SEG20/ LCD_COM4
EBI_A19 #0/1/2
LCD_SEG21/ LCD_COM5
EBI_A20 #0/1/2
LCD_SEG22/ LCD_COM6
EBI_A21 #0/1/2
LCD_SEG23/ LCD_COM7
EBI_A22 #0/1/2
Digital IO ground 1.
Digital IO power supply 1.
ACMP0_CH0 DAC0_OUT0ALT
#0/ OPAMP_OUT0ALT
EBI_A23 #0/1/2
ACMP0_CH1 DAC0_OUT0ALT
#1/ OPAMP_OUT0ALT
EBI_A24 #0/1/2
ACMP0_CH2 DAC0_OUT0ALT
#2/ OPAMP_OUT0ALT
EBI_A25 #0/1/2
ACMP0_CH3 DAC0_OUT0ALT
#3/ OPAMP_OUT0ALT
EBI_NANDREn #0/1/2
ACMP0_CH4 / DAC0_P0 / OPAMP_P0
EBI_A26 #0/1/2
TIM1_CC0 #2 TIM1_CC1 #2 TIM1_CC2 #2 PCNT1_S0IN #1 PCNT1_S1IN #1
TIM0_CC1 #4 PCNT0_S0IN #2
TIM0_CC2 #4 PCNT0_S1IN #2 TIM0_CDTI0 #4
TIM0_CDTI1 #4
TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0
I2C0_SDA #3 I2C0_SCL #3
US2_TX #1 US2_RX #1 US2_CLK #1 US2_CS #1
US0_TX #5 US1_TX #0 I2C0_SDA #4 US0_RX #5 US1_RX #0 I2C0_SCL #4 US2_TX #0
US2_RX #0
US2_CLK #0 I2C1_SDA #0
LES_ALTEX3 #0 ETM_TD2 #3
LES_ALTEX4 #0 ETM_TD3 #3 ETM_TCLK #3
GPIO_EM4WU1
LES_CH0 #0 PRS_CH2 #0 LES_CH1 #0 PRS_CH3 #0 LES_CH2 #0 LES_CH3 #0 LES_CH4 #0
silabs.com | Building a more connected world.
Rev. 2.30 | 339
Water Pads
Pad
Pad Name
#
27
PC5
28
PB7
29
PB8
30
PA7
31
PA8
32
PA9
33
PA10
34
PA11
35
IOVDD_2
36
IOVSS_2
37
PA12
38
PA13
39
PA14
40
RESETn
41
PB9
42
PB10
43
PB11
44
PB12
45
AVSS_2
46
AVDD_2
47
AVDD_1
48
AVSS_1
49
PB13
50
PB14
51
IOVSS_3
52
IOVDD_3
53
AVSS_0
54
AVDD_0
Analog
EFM32LG Data Sheet
Pin Definitions
Pad Alternative Functionality / Description
EBI
Timers
Communication
Other
ACMP0_CH5 / DAC0_N0 / OPAMP_N0
EBI_NANDWEn LETIM0_OUT1 #3
#0/1/2
PCNT1_S1IN #0
US2_CS #0 I2C1_SCL #0
LES_CH5 #0
LFXTAL_P
TIM1_CC0 #3
US0_TX #4 US1_CLK #0
LFXTAL_N
TIM1_CC1 #3
US0_RX #4 US1_CS #0
LCD_SEG35 EBI_CSTFT #0/1/2
LCD_SEG36
EBI_DCLK #0/1/2
TIM2_CC0 #0
LCD_SEG37
EBI_DTEN #0/1/2
TIM2_CC1 #0
LCD_SEG38
EBI_VSNC #0/1/2
TIM2_CC2 #0
LCD_SEG39
EBI_HSNC #0/1/2
Digital IO power supply 2.
Digital IO ground 2.
LCD_BCAP_P
EBI_A00 #0/1/2
TIM2_CC0 #1
LCD_BCAP_N
EBI_A01 #0/1/2
TIM2_CC1 #1
LCD_BEXT
EBI_A02 #0/1/2
TIM2_CC2 #1
Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released.
EBI_A03 #0/1/2
U1_TX #2
EBI_A04 #0/1/2
U1_RX #2
DAC0_OUT0 / OPAMP_OUT0
TIM1_CC2 #3 LETIM0_OUT0 #1
I2C1_SDA #1
DAC0_OUT1 / OPAMP_OUT1
LETIM0_OUT1 #1 I2C1_SCL #1
Analog ground 2.
Analog power supply 2.
Analog power supply 1.
Analog ground 1.
HFXTAL_P
US0_CLK #4/5 LEU0_TX #1
HFXTAL_N
US0_CS #4/5 LEU0_RX #1
Digital IO ground 3.
Digital IO power supply 3.
Analog ground 0.
Analog power supply 0.
silabs.com | Building a more connected world.
Rev. 2.30 | 340
EFM32LG Data Sheet
Pin Definitions
Water Pads
Pad
Pad Name
#
55
PD0
56
PD1
57
PD2
58
PD3
59
PD4
60
PD5
61
PD6
62
PD7
63
PD8
64
PC6
65
PC7
66
VSS_DREG
67
VDD_DREG
68
IOVDD_4
69
DEC_0
70
DEC_1
71
DEC_2
72
NC
73
IOVSS_4
74
PE0
75
PE1
76
PE2
77
PE3
78
PE4
Analog
Pad Alternative Functionality / Description
EBI
Timers
Communication
Other
ADC0_CH0 DAC0_OUT0ALT
#4/ OPAMP_OUT0ALT OPAMP_OUT2 #1
ADC0_CH1 DAC0_OUT1ALT
#4/ OPAMP_OUT1ALT
ADC0_CH2
EBI_A27 #0/1/2
ADC0_CH3 OPAMP_N2
ADC0_CH4 OPAMP_P2
ADC0_CH5 OPAMP_OUT2 #0
ADC0_CH6 / DAC0_P1 / OPAMP_P1
ADC0_CH7 / DAC0_N1 / OPAMP_N1
PCNT2_S0IN #0
TIM0_CC0 #3 PCNT2_S1IN #0
TIM0_CC1 #3 TIM0_CC2 #3
TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3
TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3
US1_TX #1
US1_RX #1
USB_DMPU #0 US1_CLK #1 US1_CS #1 LEU0_TX #0 LEU0_RX #0 US1_RX #2 I2C0_SDA #1 US1_TX #2 I2C0_SCL #1
BU_VIN ACMP0_CH6
EBI_A05 #0/1/2
ACMP0_CH7
EBI_A06 #0/1/2
Ground for on-chip voltage regulator.
Power supply for on-chip voltage regulator.
Digital IO power supply 4.
Decouple output for on-chip voltage regulator.
Decouple output for on-chip voltage regulator.
Decouple output for on-chip voltage regulator.
Do not connect.
Digital IO ground 4.
EBI_A07 #0/1/2
TIM3_CC0 #1 PCNT0_S0IN #1
EBI_A08 #0/1/2
TIM3_CC1 #1 PCNT0_S1IN #1
BU_VOUT
EBI_A09 #0
TIM3_CC2 #1
BU_STAT
EBI_A10 #0
LCD_COM0
EBI_A11 #0/1/2
LEU1_TX #0 I2C0_SDA #2 LEU1_RX #0 I2C0_SCL #2
U0_TX #1 I2C1_SDA #2
U0_RX #1 I2C1_SCL #2
U1_TX #3 U1_RX #3 US0_CS #1
DBG_SWO #2
DBG_SWO #3 ETM_TD1 #0/2 ETM_TD2 #0/2 ETM_TD3 #0/2 LES_ALTEX0 #0 ACMP0_O #2 ETM_TD0 #0 CMU_CLK0 #2 LES_ALTEX1 #0 ACMP1_O #2 ETM_TCLK #0 CMU_CLK1 #1 LES_CH6 #0 ETM_TCLK #2 LES_CH7 #0 ETM_TD0 #2
ACMP0_O #1 ACMP1_O #1
silabs.com | Building a more connected world.
Rev. 2.30 | 341
EFM32LG Data Sheet
Pin Definitions
Water Pads
Pad
Pad Name
#
79
PE5
80
PE6
81
PE7
82
PC8
83
PC9
84
PC10
85
PC11
86
PC12
87
PC13
88 USB_VREGI_0
89 USB_VREGI_1
90 USB_VREGO_0
91 USB_VREGO_1
92
PC14
93
PF10
94
PC15
95
PF11
96
IOVSS_7
97
PF0
98
PF1
99
PF2
100
PF3
101
USB_VBUS
Analog
Pad Alternative Functionality / Description
EBI
Timers
Communication
LCD_COM1 LCD_COM2 LCD_COM3 ACMP1_CH0 ACMP1_CH1
EBI_A12 #0/1/2 EBI_A13 #0/1/2 EBI_A14 #0/1/2 EBI_A15 #0/1/2 EBI_A09 #1/2
TIM2_CC0 #2 TIM2_CC1 #2
US0_CLK #1 US0_RX #1 US0_TX #1 US0_CS #2 US0_CLK #2
ACMP1_CH2
EBI_A10 #1/2
TIM2_CC2 #2
US0_RX #2
ACMP1_CH3
EBI_ALE #1/2
US0_TX #2
ACMP1_CH4 DAC0_OUT1ALT
#0/ OPAMP_OUT1ALT
U1_TX #0
ACMP1_CH5 DAC0_OUT1ALT
#1/ OPAMP_OUT1ALT
TIM0_CDTI0 #1/3 TIM1_CC0 #0 TIM1_CC2 #4
PCNT0_S0IN #0
U1_RX #0
Input to internal 3.3V USB regulator
Input to internal 3.3V USB regulator
Output and decoupling for internal 3.3V USB regulator
Output and decoupling for internal 3.3V USB regulator
ACMP1_CH6 DAC0_OUT1ALT
#2/ OPAMP_OUT1ALT
TIM0_CDTI1 #1/3 US0_CS #3 U0_TX
TIM1_CC1 #0
#3
PCNT0_S1IN #0
U1_TX #1 USB_DM
ACMP1_CH7 DAC0_OUT1ALT
#3/ OPAMP_OUT1ALT
TIM0_CDTI2 #1/3 TIM1_CC2 #0
US0_CLK #3 U0_RX #3
U1_RX #1 USB_DP
Digital IO ground 7.
TIM0_CC0 #5 LETIM0_OUT0 #2
US1_CLK #2 LEU0_TX #3 I2C0_SDA #5
TIM0_CC1 #5 LETIM0_OUT1 #2
US1_CS #2 LEU0_RX #3 I2C0_SCL #5
LCD_SEG0
EBI_ARDY #0/1/2 TIM0_CC2 #5
LEU0_TX #4
LCD_SEG1
EBI_ALE #0
TIM0_CDTI0 #2/5
USB 5.0 V VBUS input.
Other
LES_CH8 #0 LES_CH9 #0 GPIO_EM4WU2 LES_CH10 #0 LES_CH11 #0 CMU_CLK0 #1 LES_CH12 #0
LES_CH13 #0
LES_CH14 #0
LES_CH15 #0 DBG_SWO #1
DBG_SWCLK #0/1/2/3
DBG_SWDIO #0/1/2/3
GPIO_EM4WU3 ACMP1_O #0 DBG_SWO #0
GPIO_EM4WU4 PRS_CH0 #1 ETM_TD3 #1
silabs.com | Building a more connected world.
Rev. 2.30 | 342
Water Pads
Pad
Pad Name
#
102
PF4
103
PF12
104
PF5
105
IOVSS_5
106
IOVDD_5
107
PF6
108
PF7
109
PF8
110
PF9
111
NC
112
PD9
113
PD10
114
PD11
115
PD12
116
PD13
117
PB15
118
PE8
119
PE9
120
PE10
121
PE11
122
IOVDD_6
123
IOVSS_6
124
PE12
125
PE13
126
PE14
127
PE15
128
PA15
Analog
EFM32LG Data Sheet
Pin Definitions
Pad Alternative Functionality / Description
EBI
Timers
Communication
Other
LCD_SEG2
EBI_WEn #0/2
LCD_SEG3
EBI_REn #0/2
Digital IO ground 5.
Digital IO power supply 5.
LCD_SEG24
EBI_BL0 #0/1/2
LCD_SEG25
EBI_BL1 #0/1/2
LCD_SEG26
EBI_WEn #1
LCD_SEG27
EBI_REn #1
LCD_SEG28 LCD_SEG29 LCD_SEG30 LCD_SEG31
EBI_CS0 #0/1/2 EBI_CS1 #0/1/2 EBI_CS2 #0/1/2 EBI_CS3 #0/1/2
LCD_SEG4 LCD_SEG5 LCD_SEG6 LCD_SEG7
EBI_AD00 #0/1/2 EBI_AD01 #0/1/2 EBI_AD02 #0/1/2 EBI_AD03 #0/1/2
Digital IO power supply 6.
Digital IO ground 6.
LCD_SEG8
EBI_AD04 #0/1/2
LCD_SEG9
EBI_AD05 #0/1/2
LCD_SEG10 LCD_SEG11 LCD_SEG12
EBI_AD06 #0/1/2 EBI_AD07 #0/1/2 EBI_AD08 #0/1/2
TIM0_CDTI1 #2/5 TIM0_CDTI2 #2/5
USB_ID USB_VBUSEN #0
TIM0_CC0 #2 TIM0_CC1 #2 TIM0_CC2 #2
Do not connect.
U0_TX #0 U0_RX #0
PCNT2_S0IN #1 PCNT2_S1IN #1
TIM1_CC0 #1 TIM1_CC1 #1
US0_TX #0 US0_RX #0
TIM1_CC2 #1
TIM3_CC0 #0 TIM3_CC1 #0 TIM3_CC2 #0
US0_RX #3 US0_CLK #0 I2C0_SDA #6
US0_TX #3 US0_CS #0 I2C0_SCL #6
LEU0_TX #2
LEU0_RX #2
PRS_CH1 #1 PRS_CH2 #1
ETM_TCLK #1 ETM_TD0 #1
ETM_TD1 #1 ETM_TD2 #1 PRS_CH3 #1
BOOT_TX LES_ALTEX5 #0
BOOT_RX
CMU_CLK1 #2 LES_ALTEX6 #0 LES_ALTEX7 #0
ACMP0_O #0 GPIO_EM4WU5
silabs.com | Building a more connected world.
Rev. 2.30 | 343
EFM32LG Data Sheet
Pin Definitions
5.17.2 Alternate Functionality Padout
A wide selection of alternate functionality is available for multiplexing to various pads. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the padout is shown in the column corresponding to LOCATION 0.
Alternate Functionality ACMP0_CH0 ACMP0_CH1 ACMP0_CH2 ACMP0_CH3 ACMP0_CH4 ACMP0_CH5 ACMP0_CH6 ACMP0_CH7 ACMP0_O ACMP1_CH0 ACMP1_CH1 ACMP1_CH2 ACMP1_CH3 ACMP1_CH4 ACMP1_CH5 ACMP1_CH6 ACMP1_CH7 ACMP1_O ADC0_CH0
ADC0_CH1
ADC0_CH2
ADC0_CH3
ADC0_CH4
ADC0_CH5
ADC0_CH6
Table 5.50. Alternate Functionality Overview
LOCATION
0
1
2
3
4
5
6
Description
PC0
Analog comparator ACMP0, channel 0.
PC1
Analog comparator ACMP0, channel 1.
PC2
Analog comparator ACMP0, channel 2.
PC3
Analog comparator ACMP0, channel 3.
PC4
Analog comparator ACMP0, channel 4.
PC5
Analog comparator ACMP0, channel 5.
PC6
Analog comparator ACMP0, channel 6.
PC7
Analog comparator ACMP0, channel 7.
PE13 PE2 PD6
Analog comparator ACMP0, digital output.
PC8
Analog comparator ACMP1, channel 0.
PC9
Analog comparator ACMP1, channel 1.
PC10
Analog comparator ACMP1, channel 2.
PC11
Analog comparator ACMP1, channel 3.
PC12
Analog comparator ACMP1, channel 4.
PC13
Analog comparator ACMP1, channel 5.
PC14
Analog comparator ACMP1, channel 6.
PC15
Analog comparator ACMP1, channel 7.
PF2 PE3 PD7
Analog comparator ACMP1, digital output.
PD0
Analog to digital converter ADC0, input channel number 0.
PD1
Analog to digital converter ADC0, input channel number 1.
PD2
Analog to digital converter ADC0, input channel number 2.
PD3
Analog to digital converter ADC0, input channel number 3.
PD4
Analog to digital converter ADC0, input channel number 4.
PD5
Analog to digital converter ADC0, input channel number 5.
PD6
Analog to digital converter ADC0, input channel number 6.
silabs.com | Building a more connected world.
Rev. 2.30 | 344
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
ADC0_CH7
PD7
Analog to digital converter ADC0, input channel number 7.
BOOT_RX
PE11
Bootloader RX.
BOOT_TX
PE10
Bootloader TX.
BU_STAT
PE3
Backup Power Domain status, whether or not the system is in backup mode
BU_VIN
PD8
Battery input for Backup Power Domain
BU_VOUT
PE2
Power output for Backup Power Domain
CMU_CLK0
PA2 PC12 PD7
Clock Management Unit, clock output number 0.
CMU_CLK1
PA1 PD8 PE12
Clock Management Unit, clock output number 1.
DAC0_OUT0 / OPAMP_OUT0
PB11
Digital to Analog Converter DAC0_OUT0 / OPAMP output channel number 0.
DAC0_OUT0ALT / OPAMP_OUT0ALT
PC0
PC1
PC2
PC3
PD0
Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0.
DAC0_OUT1 / OPAMP_OUT1
PB12
Digital to Analog Converter DAC0_OUT1 / OPAMP output channel number 1.
DAC0_OUT1ALT / OPAMP_OUT1ALT
PC12
PC13
PC14
PC15
PD1
Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1.
DBG_SWCLK
PF0 PF0 PF0 PF0
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, and has a built-in pull down.
DBG_SWDIO
PF1 PF1 PF1 PF1
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and has a built-in pull up.
DBG_SWO
PF2 PC15 PD1 PD2
Debug-interface Serial Wire viewer Output.
Note that this function is not enabled after reset, and must be enabled by software to be used.
EBI_A00
PA12 PA12 PA12
External Bus Interface (EBI) address output pin 00.
EBI_A01
PA13 PA13 PA13
External Bus Interface (EBI) address output pin 01.
EBI_A02
PA14 PA14 PA14
External Bus Interface (EBI) address output pin 02.
EBI_A03
PB9 PB9 PB9
External Bus Interface (EBI) address output pin 03.
EBI_A04
PB10 PB10 PB10
External Bus Interface (EBI) address output pin 04.
EBI_A05
PC6 PC6 PC6
External Bus Interface (EBI) address output pin 05.
EBI_A06
PC7 PC7 PC7
External Bus Interface (EBI) address output pin 06.
EBI_A07
PE0 PE0 PE0
External Bus Interface (EBI) address output pin 07.
EBI_A08
PE1 PE1 PE1
External Bus Interface (EBI) address output pin 08.
EBI_A09
PE2 PC9 PC9
External Bus Interface (EBI) address output pin 09.
EBI_A10
PE3 PC10 PC10
External Bus Interface (EBI) address output pin 10.
EBI_A11
PE4 PE4 PE4
External Bus Interface (EBI) address output pin 11.
EBI_A12
PE5 PE5 PE5
External Bus Interface (EBI) address output pin 12.
silabs.com | Building a more connected world.
Rev. 2.30 | 345
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
EBI_A13
PE6 PE6 PE6
External Bus Interface (EBI) address output pin 13.
EBI_A14
PE7 PE7 PE7
External Bus Interface (EBI) address output pin 14.
EBI_A15
PC8 PC8 PC8
External Bus Interface (EBI) address output pin 15.
EBI_A16
PB0 PB0 PB0
External Bus Interface (EBI) address output pin 16.
EBI_A17
PB1 PB1 PB1
External Bus Interface (EBI) address output pin 17.
EBI_A18
PB2 PB2 PB2
External Bus Interface (EBI) address output pin 18.
EBI_A19
PB3 PB3 PB3
External Bus Interface (EBI) address output pin 19.
EBI_A20
PB4 PB4 PB4
External Bus Interface (EBI) address output pin 20.
EBI_A21
PB5 PB5 PB5
External Bus Interface (EBI) address output pin 21.
EBI_A22
PB6 PB6 PB6
External Bus Interface (EBI) address output pin 22.
EBI_A23
PC0 PC0 PC0
External Bus Interface (EBI) address output pin 23.
EBI_A24
PC1 PC1 PC1
External Bus Interface (EBI) address output pin 24.
EBI_A25
PC2 PC2 PC2
External Bus Interface (EBI) address output pin 25.
EBI_A26
PC4 PC4 PC4
External Bus Interface (EBI) address output pin 26.
EBI_A27
PD2 PD2 PD2
External Bus Interface (EBI) address output pin 27.
EBI_AD00
PE8 PE8 PE8
External Bus Interface (EBI) address and data input / output pin 00.
EBI_AD01
PE9 PE9 PE9
External Bus Interface (EBI) address and data input / output pin 01.
EBI_AD02
PE10 PE10 PE10
External Bus Interface (EBI) address and data input / output pin 02.
EBI_AD03
PE11 PE11 PE11
External Bus Interface (EBI) address and data input / output pin 03.
EBI_AD04
PE12 PE12 PE12
External Bus Interface (EBI) address and data input / output pin 04.
EBI_AD05
PE13 PE13 PE13
External Bus Interface (EBI) address and data input / output pin 05.
EBI_AD06
PE14 PE14 PE14
External Bus Interface (EBI) address and data input / output pin 06.
EBI_AD07
PE15 PE15 PE15
External Bus Interface (EBI) address and data input / output pin 07.
EBI_AD08
PA15 PA15 PA15
External Bus Interface (EBI) address and data input / output pin 08.
EBI_AD09
PA0 PA0 PA0
External Bus Interface (EBI) address and data input / output pin 09.
EBI_AD10
PA1 PA1 PA1
External Bus Interface (EBI) address and data input / output pin 10.
EBI_AD11
PA2 PA2 PA2
External Bus Interface (EBI) address and data input / output pin 11.
EBI_AD12
PA3 PA3 PA3
External Bus Interface (EBI) address and data input / output pin 12.
silabs.com | Building a more connected world.
Rev. 2.30 | 346
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
EBI_AD13
PA4 PA4 PA4
External Bus Interface (EBI) address and data input / output pin 13.
EBI_AD14
PA5 PA5 PA5
External Bus Interface (EBI) address and data input / output pin 14.
EBI_AD15
PA6 PA6 PA6
External Bus Interface (EBI) address and data input / output pin 15.
EBI_ALE
PF3 PC11 PC11
External Bus Interface (EBI) Address Latch Enable output.
EBI_ARDY
PF2 PF2 PF2
External Bus Interface (EBI) Hardware Ready Control input.
EBI_BL0
PF6 PF6 PF6
External Bus Interface (EBI) Byte Lane/Enable pin 0.
EBI_BL1
PF7 PF7 PF7
External Bus Interface (EBI) Byte Lane/Enable pin 1.
EBI_CS0
PD9 PD9 PD9
External Bus Interface (EBI) Chip Select output 0.
EBI_CS1
PD10 PD10 PD10
External Bus Interface (EBI) Chip Select output 1.
EBI_CS2
PD11 PD11 PD11
External Bus Interface (EBI) Chip Select output 2.
EBI_CS3
PD12 PD12 PD12
External Bus Interface (EBI) Chip Select output 3.
EBI_CSTFT
PA7 PA7 PA7
External Bus Interface (EBI) Chip Select output TFT.
EBI_DCLK
PA8 PA8 PA8
External Bus Interface (EBI) TFT Dot Clock pin.
EBI_DTEN
PA9 PA9 PA9
External Bus Interface (EBI) TFT Data Enable pin.
EBI_HSNC
PA11 PA11 PA11
External Bus Interface (EBI) TFT Horizontal Synchronization pin.
EBI_NANDREn
PC3 PC3 PC3
External Bus Interface (EBI) NAND Read Enable output.
EBI_NANDWEn
PC5 PC5 PC5
External Bus Interface (EBI) NAND Write Enable output.
EBI_REn
PF5 PF9 PF5
External Bus Interface (EBI) Read Enable output.
EBI_VSNC
PA10 PA10 PA10
External Bus Interface (EBI) TFT Vertical Synchronization pin.
EBI_WEn
PF4 PF8 PF4
External Bus Interface (EBI) Write Enable output.
ETM_TCLK
PD7 PF8 PC6 PA6
Embedded Trace Module ETM clock .
ETM_TD0
PD6 PF9 PC7 PA2
Embedded Trace Module ETM data 0.
ETM_TD1
PD3 PD13 PD3 PA3
Embedded Trace Module ETM data 1.
ETM_TD2
PD4 PB15 PD4 PA4
Embedded Trace Module ETM data 2.
ETM_TD3
PD5 PF3 PD5 PA5
Embedded Trace Module ETM data 3.
GPIO_EM4WU0 PA0
Pin can be used to wake the system up from EM4
GPIO_EM4WU1 PA6
Pin can be used to wake the system up from EM4
GPIO_EM4WU2 PC9
Pin can be used to wake the system up from EM4
GPIO_EM4WU3 PF1
Pin can be used to wake the system up from EM4
silabs.com | Building a more connected world.
Rev. 2.30 | 347
Alternate Functionality GPIO_EM4WU4 GPIO_EM4WU5 HFXTAL_N HFXTAL_P I2C0_SCL I2C0_SDA I2C1_SCL I2C1_SDA
LCD_BCAP_N
LCD_BCAP_P
LCD_BEXT
LCD_COM0 LCD_COM1 LCD_COM2 LCD_COM3 LCD_SEG0 LCD_SEG1 LCD_SEG2 LCD_SEG3 LCD_SEG4 LCD_SEG5 LCD_SEG6
EFM32LG Data Sheet
Pin Definitions
LOCATION
0
1
2
3
4
5
6
Description
PF2
Pin can be used to wake the system up from EM4
PE13
Pin can be used to wake the system up from EM4
PB14
High Frequency Crystal negative pin. Also used as external optional clock input pin.
PB13
High Frequency Crystal positive pin.
PA1 PD7 PC7 PD15 PC1 PF1 PE13 I2C0 Serial Clock Line input / output.
PA0 PD6 PC6 PD14 PC0 PF0 PE12 I2C0 Serial Data input / output.
PC5 PB12 PE1
I2C1 Serial Clock Line input / output.
PC4 PB11 PE0
I2C1 Serial Data input / output.
PA13
LCD voltage booster (optional), boost capacitor, negative pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P.
PA12
LCD voltage booster (optional), boost capacitor, positive pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P.
LCD voltage booster (optional), boost output. If using the LCD voltage booster, connect a 1 uF capacitor between this pin and VSS.
PA14
An external LCD voltage may also be applied to this pin if the booster is not enabled.
If AVDD is used directly as the LCD supply voltage, this pin may be left unconnected or used as a GPIO.
PE4
LCD driver common line number 0.
PE5
LCD driver common line number 1.
PE6
LCD driver common line number 2.
PE7
LCD driver common line number 3.
PF2
LCD segment line 0. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
PF3
LCD segment line 1. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
PF4
LCD segment line 2. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
PF5
LCD segment line 3. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
PE8
LCD segment line 4. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
PE9
LCD segment line 5. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
PE10
LCD segment line 6. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
silabs.com | Building a more connected world.
Rev. 2.30 | 348
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
LCD_SEG7
PE11
LCD segment line 7. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
LCD_SEG8
PE12
LCD segment line 8. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG9
PE13
LCD segment line 9. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG10
PE14
LCD segment line 10. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG11
PE15
LCD segment line 11. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG12
PA15
LCD segment line 12. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG13
PA0
LCD segment line 13. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG14
PA1
LCD segment line 14. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG15
PA2
LCD segment line 15. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG16
PA3
LCD segment line 16. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG17
PA4
LCD segment line 17. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG18
PA5
LCD segment line 18. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG19
PA6
LCD segment line 19. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG20/ LCD_COM4
PB3
LCD segment line 20. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 4
LCD_SEG21/ LCD_COM5
PB4
LCD segment line 21. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 5
LCD_SEG22/ LCD_COM6
PB5
LCD segment line 22. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 6
LCD_SEG23/ LCD_COM7
PB6
LCD segment line 23. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 7
LCD_SEG24
PF6
LCD segment line 24. Segments 24, 25, 26 and 27 are controlled by SEGEN6.
LCD_SEG25
PF7
LCD segment line 25. Segments 24, 25, 26 and 27 are controlled by SEGEN6.
LCD_SEG26
PF8
LCD segment line 26. Segments 24, 25, 26 and 27 are controlled by SEGEN6.
LCD_SEG27
PF9
LCD segment line 27. Segments 24, 25, 26 and 27 are controlled by SEGEN6.
silabs.com | Building a more connected world.
Rev. 2.30 | 349
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
LCD_SEG28
PD9
LCD segment line 28. Segments 28, 29, 30 and 31 are controlled by SEGEN7.
LCD_SEG29
PD10
LCD segment line 29. Segments 28, 29, 30 and 31 are controlled by SEGEN7.
LCD_SEG30
PD11
LCD segment line 30. Segments 28, 29, 30 and 31 are controlled by SEGEN7.
LCD_SEG31
PD12
LCD segment line 31. Segments 28, 29, 30 and 31 are controlled by SEGEN7.
LCD_SEG32
PB0
LCD segment line 32. Segments 32, 33, 34 and 35 are controlled by SEGEN8.
LCD_SEG33
PB1
LCD segment line 33. Segments 32, 33, 34 and 35 are controlled by SEGEN8.
LCD_SEG34
PB2
LCD segment line 34. Segments 32, 33, 34 and 35 are controlled by SEGEN8.
LCD_SEG35
PA7
LCD segment line 35. Segments 32, 33, 34 and 35 are controlled by SEGEN8.
LCD_SEG36
PA8
LCD segment line 36. Segments 36, 37, 38 and 39 are controlled by SEGEN9.
LCD_SEG37
PA9
LCD segment line 37. Segments 36, 37, 38 and 39 are controlled by SEGEN9.
LCD_SEG38
PA10
LCD segment line 38. Segments 36, 37, 38 and 39 are controlled by SEGEN9.
LCD_SEG39
PA11
LCD segment line 39. Segments 36, 37, 38 and 39 are controlled by SEGEN9.
LES_ALTEX0
PD6
LESENSE alternate exite output 0.
LES_ALTEX1
PD7
LESENSE alternate exite output 1.
LES_ALTEX2
PA3
LESENSE alternate exite output 2.
LES_ALTEX3
PA4
LESENSE alternate exite output 3.
LES_ALTEX4
PA5
LESENSE alternate exite output 4.
LES_ALTEX5
PE11
LESENSE alternate exite output 5.
LES_ALTEX6
PE12
LESENSE alternate exite output 6.
LES_ALTEX7
PE13
LESENSE alternate exite output 7.
LES_CH0
PC0
LESENSE channel 0.
LES_CH1
PC1
LESENSE channel 1.
LES_CH2
PC2
LESENSE channel 2.
LES_CH3
PC3
LESENSE channel 3.
LES_CH4
PC4
LESENSE channel 4.
LES_CH5
PC5
LESENSE channel 5.
LES_CH6
PC6
LESENSE channel 6.
LES_CH7
PC7
LESENSE channel 7.
LES_CH8
PC8
LESENSE channel 8.
silabs.com | Building a more connected world.
Rev. 2.30 | 350
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
LES_CH9
PC9
LESENSE channel 9.
LES_CH10
PC10
LESENSE channel 10.
LES_CH11
PC11
LESENSE channel 11.
LES_CH12
PC12
LESENSE channel 12.
LES_CH13
PC13
LESENSE channel 13.
LES_CH14
PC14
LESENSE channel 14.
LES_CH15
PC15
LESENSE channel 15.
LETIM0_OUT0
PD6 PB11 PF0 PC4
Low Energy Timer LETIM0, output channel 0.
LETIM0_OUT1
PD7 PB12 PF1 PC5
Low Energy Timer LETIM0, output channel 1.
LEU0_RX
PD5 PB14 PE15 PF1 PA0
LEUART0 Receive input.
LEU0_TX
PD4 PB13 PE14 PF0 PF2
LEUART0 Transmit output. Also used as receive input in half duplex communication.
LEU1_RX
PC7 PA6
LEUART1 Receive input.
LEU1_TX
PC6 PA5
LEUART1 Transmit output. Also used as receive input in half duplex communication.
LFXTAL_N
PB8
Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin.
LFXTAL_P
PB7
Low Frequency Crystal (typically 32.768 kHz) positive pin.
OPAMP_N0 / DAC0_N0
PC5
Operational Amplifier 0 external negative input.
OPAMP_N1 / DAC0_N1
PD7
Operational Amplifier 1 external negative input.
OPAMP_N2
PD3
Operational Amplifier 2 external negative input.
OPAMP_OUT2
PD5 PD0
Operational Amplifier 2 output.
OPAMP_P0 / DAC0_P0
PC4
Operational Amplifier 0 external positive input.
OPAMP_P1 / DAC0_P1
PD6
Operational Amplifier 1 external positive input.
OPAMP_P2
PD4
Operational Amplifier 2 external positive input.
PCNT0_S0IN
PC13 PE0 PC0 PD6
Pulse Counter PCNT0 input number 0.
PCNT0_S1IN
PC14 PE1 PC1 PD7
Pulse Counter PCNT0 input number 1.
PCNT1_S0IN
PC4 PB3
Pulse Counter PCNT1 input number 0.
PCNT1_S1IN
PC5 PB4
Pulse Counter PCNT1 input number 1.
PCNT2_S0IN
PD0 PE8
Pulse Counter PCNT2 input number 0.
PCNT2_S1IN
PD1 PE9
Pulse Counter PCNT2 input number 1.
PRS_CH0
PA0 PF3
Peripheral Reflex System PRS, channel 0.
PRS_CH1
PA1 PF4
Peripheral Reflex System PRS, channel 1.
PRS_CH2
PC0 PF5
Peripheral Reflex System PRS, channel 2.
silabs.com | Building a more connected world.
Rev. 2.30 | 351
Alternate Functionality PRS_CH3 TIM0_CC0 TIM0_CC1 TIM0_CC2 TIM0_CDTI0
TIM0_CDTI1
TIM0_CDTI2 TIM1_CC0 TIM1_CC1 TIM1_CC2 TIM2_CC0 TIM2_CC1 TIM2_CC2 TIM3_CC0 TIM3_CC1 TIM3_CC2 U0_RX U0_TX U1_RX U1_TX US0_CLK US0_CS
US0_RX
US0_TX
US1_CLK US1_CS
US1_RX
LOCATION
0
1
2
3
4
5
PC1 PE8
PA0 PA0 PF6 PD1 PA0 PF0
PA1 PA1 PF7 PD2 PC0 PF1
PA2 PA2 PF8 PD3 PC1 PF2
PA3 PC13 PF3 PC13 PC2 PF3
PA4 PC14 PF4 PC14 PC3 PF4
PA5 PC15 PF5 PC15 PC4 PF5
PC13 PE10 PB0 PB7 PD6 PC14 PE11 PB1 PB8 PD7 PC15 PE12 PB2 PB11 PC13 PA8 PA12 PC8 PA9 PA13 PC9 PA10 PA14 PC10 PE14 PE0 PE15 PE1 PA15 PE2 PF7 PE1 PA4 PC15
PF6 PE0 PA3 PC14
PC13 PF11 PB10 PE3
PC12 PF10 PB9 PE2
PE12 PE5 PC9 PC15 PB13 PB13 PE13 PE4 PC8 PC14 PB14 PB14
PE11 PE6 PC10 PE12 PB8 PC1
PE10 PE7 PC11 PE13 PB7 PC0
PB7 PD2 PF0 PB8 PD3 PF1 PC1 PD1 PD6
EFM32LG Data Sheet
Pin Definitions
6
Description
Peripheral Reflex System PRS, channel 3.
Timer 0 Capture Compare input / output channel 0.
Timer 0 Capture Compare input / output channel 1.
Timer 0 Capture Compare input / output channel 2.
Timer 0 Complimentary Deat Time Insertion channel 0.
Timer 0 Complimentary Deat Time Insertion channel 1.
Timer 0 Complimentary Deat Time Insertion channel 2.
Timer 1 Capture Compare input / output channel 0.
Timer 1 Capture Compare input / output channel 1.
Timer 1 Capture Compare input / output channel 2.
Timer 2 Capture Compare input / output channel 0.
Timer 2 Capture Compare input / output channel 1.
Timer 2 Capture Compare input / output channel 2.
Timer 3 Capture Compare input / output channel 0.
Timer 3 Capture Compare input / output channel 1.
Timer 3 Capture Compare input / output channel 2.
UART0 Receive input.
UART0 Transmit output. Also used as receive input in half duplex communication.
UART1 Receive input.
UART1 Transmit output. Also used as receive input in half duplex communication.
USART0 clock input / output.
USART0 chip select input / output.
USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output (MISO).
USART0 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input (MOSI).
USART1 clock input / output.
USART1 chip select input / output.
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output (MISO).
silabs.com | Building a more connected world.
Rev. 2.30 | 352
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
US1_TX
PC0 PD0 PD7
USART1 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input (MOSI).
US2_CLK
PC4 PB5
USART2 clock input / output.
US2_CS
PC5 PB6
USART2 chip select input / output.
US2_RX
PC3 PB4
USART2 Asynchronous Receive.
USART2 Synchronous mode Master Input / Slave Output (MISO).
US2_TX
PC2 PB3
USART2 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART2 Synchronous mode Master Output / Slave Input (MOSI).
USB_DM
PF10
USB D- pin.
USB_DMPU
PD2
USB D- Pullup control.
USB_DP
PF11
USB D+ pin.
USB_ID
PF12
USB ID pin. Used in OTG mode.
USB_VBUS
USB_ VBUS
USB 5 V VBUS input.
USB_VBUSEN
PF5
USB 5 V VBUS enable.
USB_VREGI
USB_ VREGI
USB Input to internal 3.3 V regulator
USB_VREGO
USB_ VREGO
USB Decoupling for internal 3.3 V USB regulator and regulator output
5.17.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG900 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.51. GPIO Pinout
Port
Port A Port B Port C Port D Port E Port F
Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 15 14 13 12 11 10 PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 -- -- -- PF12 PF11 PF10 PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0
silabs.com | Building a more connected world.
Rev. 2.30 | 353
5.17.4 Opamp Pinout Overview
The specific opamp terminals available in EFM32LG900 is shown in the following figure.
PC4
+ OUT0ALT
PC5
OPA0 -
OUT0
PD4
+
PD3
OPA2 -
OUT2
PD6
+ OUT1ALT
PD7
OPA1 -
OUT1
PB11 PB12 PC0 PC1 PC2 PC3 PC12 PC13 PC14 PC15 PD0 PD1 PD5
Figure 5.34. Opamp Pinout
EFM32LG Data Sheet
Pin Definitions
silabs.com | Building a more connected world.
Rev. 2.30 | 354
5.18 EFM32LG940 (QFN64)
EFM32LG Data Sheet
Pin Definitions
5.18.1 Pinout
The EFM32LG940 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question.
Figure 5.35. EFM32LG940 Pinout (top view, not to scale)
silabs.com | Building a more connected world.
Rev. 2.30 | 355
EFM32LG Data Sheet
Pin Definitions
Table 5.52. Device Pinout
QFN64 Pin# and Name
Pin #
Pin Name
0
VSS
1
PA0
2
PA1
3
PA2
4
PA3
5
PA4
6
PA5
7
PA6
8
IOVDD_0
9
PB3
10
PB4
11
PB5
12
PB6
13
PC4
14
PC5
15
PB7
16
PB8
17
PA12
18
PA13
19
PA14
20
RESETn
21
PB11
22
PB12
Pin Alternate Functionality / Description
Analog
Timers
Communication
Other
Ground.
LCD_SEG13
TIM0_CC0 #0/1/4
LEU0_RX #4 I2C0_SDA #0
PRS_CH0 #0 GPIO_EM4WU0
LCD_SEG14
TIM0_CC1 #0/1
I2C0_SCL #0
CMU_CLK1 #0 PRS_CH1 #0
LCD_SEG15
TIM0_CC2 #0/1
CMU_CLK0 #0 ETM_TD0 #3
LCD_SEG16
TIM0_CDTI0 #0
LES_ALTEX2 #0 ETM_TD1 #3
LCD_SEG17
TIM0_CDTI1 #0
LES_ALTEX3 #0 ETM_TD2 #3
LCD_SEG18
TIM0_CDTI2 #0
LEU1_TX #1
LES_ALTEX4 #0 ETM_TD3 #3
LCD_SEG19
LEU1_RX #1
ETM_TCLK #3 GPIO_EM4WU1
Digital IO power supply 0.
LCD_SEG20/ LCD_COM4
PCNT1_S0IN #1
US2_TX #1
LCD_SEG21/ LCD_COM5
PCNT1_S1IN #1
US2_RX #1
LCD_SEG22/ LCD_COM6
US2_CLK #1
LCD_SEG23/ LCD_COM7
US2_CS #1
ACMP0_CH4 / DAC0_P0 / OPAMP_P0
TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0
US2_CLK #0 I2C1_SDA #0
LES_CH4 #0
ACMP0_CH5 / DAC0_N0 / OPAMP_N0
LETIM0_OUT1 #3 PCNT1_S1IN #0
US2_CS #0 I2C1_SCL #0
LES_CH5 #0
LFXTAL_P
TIM1_CC0 #3
US0_TX #4 US1_CLK #0
LFXTAL_N
TIM1_CC1 #3
US0_RX #4 US1_CS #0
LCD_BCAP_P
TIM2_CC0 #1
LCD_BCAP_N
TIM2_CC1 #1
LCD_BEXT
TIM2_CC2 #1
Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released.
DAC0_OUT0 / OPAMP_OUT0
TIM1_CC2 #3 LETIM0_OUT0 #1
I2C1_SDA #1
DAC0_OUT1 / OPAMP_OUT1
LETIM0_OUT1 #1
I2C1_SCL #1
silabs.com | Building a more connected world.
Rev. 2.30 | 356
EFM32LG Data Sheet
Pin Definitions
QFN64 Pin# and Name
Pin #
Pin Name
23
AVDD_1
24
PB13
25
PB14
26
IOVDD_3
27
AVDD_0
28
PD0
29
PD1
30
PD2
31
PD3
32
PD4
33
PD5
34
PD6
35
PD7
36
PD8
37
PC6
38
PC7
39
VDD_DREG
40
DECOUPLE
41
PE4
42
PE5
43
PE6
44
PE7
45
USB_VREGI
46
USB_VREGO
47
PF10
48
PF11
Pin Alternate Functionality / Description
Analog
Timers
Communication
Other
Analog power supply 1.
HFXTAL_P
US0_CLK #4/5 LEU0_TX #1
HFXTAL_N
US0_CS #4/5 LEU0_RX #1
Digital IO power supply 3.
Analog power supply 0.
ADC0_CH0 DAC0_OUT0ALT #4/ OPAMP_OUT0ALT
OPAMP_OUT2 #1
PCNT2_S0IN #0
US1_TX #1
ADC0_CH1 DAC0_OUT1ALT #4/ OPAMP_OUT1ALT
TIM0_CC0 #3 PCNT2_S1IN #0
US1_RX #1
DBG_SWO #2
ADC0_CH2
TIM0_CC1 #3
USB_DMPU #0 US1_CLK #1
DBG_SWO #3
ADC0_CH3 OPAMP_N2
TIM0_CC2 #3
US1_CS #1
ETM_TD1 #0/2
ADC0_CH4 OPAMP_P2
LEU0_TX #0
ETM_TD2 #0/2
ADC0_CH5 OPAMP_OUT2 #0
LEU0_RX #0
ETM_TD3 #0/2
ADC0_CH6 / DAC0_P1 / OPAMP_P1
TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3
US1_RX #2 I2C0_SDA #1
LES_ALTEX0 #0 ACMP0_O #2 ETM_TD0 #0
ADC0_CH7 / DAC0_N1 / OPAMP_N1
TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3
US1_TX #2 I2C0_SCL #1
CMU_CLK0 #2 LES_ALTEX1 #0
ACMP1_O #2 ETM_TCLK #0
BU_VIN
CMU_CLK1 #1
ACMP0_CH6
LEU1_TX #0 I2C0_SDA #2
LES_CH6 #0 ETM_TCLK #2
ACMP0_CH7
LEU1_RX #0 I2C0_SCL LES_CH7 #0 ETM_TD0
#2
#2
Power supply for on-chip voltage regulator.
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin.
LCD_COM0
US0_CS #1
LCD_COM1
US0_CLK #1
LCD_COM2
US0_RX #1
LCD_COM3
US0_TX #1
Input to internal 3.3V USB regulator
Output and decoupling for internal 3.3V USB regulator
USB_DM
USB_DP
silabs.com | Building a more connected world.
Rev. 2.30 | 357
EFM32LG Data Sheet
Pin Definitions
QFN64 Pin# and Name
Pin #
Pin Name
49
PF0
50
PF1
51
PF2
52
USB_VBUS
53
PF12
54
PF5
55
IOVDD_5
56
PE8
57
PE9
58
PE10
59
PE11
60
PE12
61
PE13
62
PE14
63
PE15
64
PA15
Analog
LCD_SEG0 USB 5.0 V VBUS input.
LCD_SEG3 Digital IO power supply 5.
LCD_SEG4 LCD_SEG5 LCD_SEG6 LCD_SEG7 LCD_SEG8
LCD_SEG9 LCD_SEG10 LCD_SEG11 LCD_SEG12
Pin Alternate Functionality / Description
Timers
Communication
Other
TIM0_CC0 #5 LETIM0_OUT0 #2
US1_CLK #2 LEU0_TX #3 I2C0_SDA #5
DBG_SWCLK #0/1/2/3
TIM0_CC1 #5 LETIM0_OUT1 #2
US1_CS #2 LEU0_RX DBG_SWDIO #0/1/2/3
#3 I2C0_SCL #5
GPIO_EM4WU3
TIM0_CC2 #5
LEU0_TX #4
ACMP1_O #0 DBG_SWO #0 GPIO_EM4WU4
TIM0_CDTI2 #2/5
USB_ID USB_VBUSEN #0
PRS_CH2 #1
PCNT2_S0IN #1 PCNT2_S1IN #1
TIM1_CC0 #1 TIM1_CC1 #1 TIM1_CC2 #1
TIM3_CC0 #0 TIM3_CC1 #0 TIM3_CC2 #0
US0_TX #0
US0_RX #0
US0_RX #3 US0_CLK #0 I2C0_SDA #6
US0_TX #3 US0_CS #0 I2C0_SCL #6
LEU0_TX #2 LEU0_RX #2
PRS_CH3 #1
BOOT_TX LES_ALTEX5 #0
BOOT_RX CMU_CLK1 #2 LES_ALTEX6 #0 LES_ALTEX7 #0 ACMP0_O #0 GPIO_EM4WU5
silabs.com | Building a more connected world.
Rev. 2.30 | 358
EFM32LG Data Sheet
Pin Definitions
5.18.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0.
Table 5.53. Alternate Functionality Overview
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
ACMP0_CH4 PC4
Analog comparator ACMP0, channel 4.
ACMP0_CH5 PC5
Analog comparator ACMP0, channel 5.
ACMP0_CH6 PC6
Analog comparator ACMP0, channel 6.
ACMP0_CH7 PC7
Analog comparator ACMP0, channel 7.
ACMP0_O
PE13
PD6
Analog comparator ACMP0, digital output.
ACMP1_O
PF2
PD7
Analog comparator ACMP1, digital output.
ADC0_CH0
PD0
Analog to digital converter ADC0, input channel number 0.
ADC0_CH1
PD1
Analog to digital converter ADC0, input channel number 1.
ADC0_CH2
PD2
Analog to digital converter ADC0, input channel number 2.
ADC0_CH3
PD3
Analog to digital converter ADC0, input channel number 3.
ADC0_CH4
PD4
Analog to digital converter ADC0, input channel number 4.
ADC0_CH5
PD5
Analog to digital converter ADC0, input channel number 5.
ADC0_CH6
PD6
Analog to digital converter ADC0, input channel number 6.
ADC0_CH7
PD7
Analog to digital converter ADC0, input channel number 7.
BOOT_RX
PE11
Bootloader RX.
BOOT_TX
PE10
Bootloader TX.
BU_VIN
PD8
Battery input for Backup Power Domain
CMU_CLK0
PA2
PD7
Clock Management Unit, clock output number 0.
CMU_CLK1
PA1 PD8 PE12
Clock Management Unit, clock output number 1.
DAC0_OUT0 / OPAMP_OUT0
PB11
Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0.
DAC0_OUT0ALT / OPAMP_OUT0A LT
PD0
Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0.
DAC0_OUT1 / OPAMP_OUT1
PB12
Digital to Analog Converter DAC0_OUT1 / OPAMP output channel number 1.
silabs.com | Building a more connected world.
Rev. 2.30 | 359
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
DAC0_OUT1ALT / OPAMP_OUT1A LT
PD1
Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1.
DBG_SWCLK PF0 PF0 PF0 PF0
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, and has a built-in pull down.
DBG_SWDIO PF1 PF1 PF1 PF1
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and has a built-in pull up.
DBG_SWO
PF2
PD1 PD2
Debug-interface Serial Wire viewer Output.
Note that this function is not enabled after reset, and must be enabled by software to be used.
ETM_TCLK
PD7
PC6 PA6
Embedded Trace Module ETM clock .
ETM_TD0
PD6
PC7 PA2
Embedded Trace Module ETM data 0.
ETM_TD1
PD3
PD3 PA3
Embedded Trace Module ETM data 1.
ETM_TD2
PD4
PD4 PA4
Embedded Trace Module ETM data 2.
ETM_TD3
PD5
PD5 PA5
Embedded Trace Module ETM data 3.
GPIO_EM4WU0 PA0
Pin can be used to wake the system up from EM4
GPIO_EM4WU1 PA6
Pin can be used to wake the system up from EM4
GPIO_EM4WU3 PF1
Pin can be used to wake the system up from EM4
GPIO_EM4WU4 PF2
Pin can be used to wake the system up from EM4
GPIO_EM4WU5 PE13
Pin can be used to wake the system up from EM4
HFXTAL_N
PB14
High Frequency Crystal negative pin. Also used as external optional clock input pin.
HFXTAL_P
PB13
High Frequency Crystal positive pin.
I2C0_SCL
PA1 PD7 PC7
PF1 PE13 I2C0 Serial Clock Line input / output.
I2C0_SDA
PA0 PD6 PC6
PF0 PE12 I2C0 Serial Data input / output.
I2C1_SCL
PC5 PB12
I2C1 Serial Clock Line input / output.
I2C1_SDA
PC4 PB11
I2C1 Serial Data input / output.
LCD_BCAP_N PA13
LCD voltage booster (optional), boost capacitor, negative pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P.
LCD_BCAP_P PA12
LCD voltage booster (optional), boost capacitor, positive pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P.
silabs.com | Building a more connected world.
Rev. 2.30 | 360
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
LCD voltage booster (optional), boost output. If using the LCD voltage booster, connect a 1 uF capacitor between this pin and VSS.
LCD_BEXT
PA14
An external LCD voltage may also be applied to this pin if the booster is not enabled.
If AVDD is used directly as the LCD supply voltage, this pin may be left unconnected or used as a GPIO.
LCD_COM0
PE4
LCD driver common line number 0.
LCD_COM1
PE5
LCD driver common line number 1.
LCD_COM2
PE6
LCD driver common line number 2.
LCD_COM3
PE7
LCD driver common line number 3.
LCD_SEG0
PF2
LCD segment line 0. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
LCD_SEG3
PF5
LCD segment line 3. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
LCD_SEG4
PE8
LCD segment line 4. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
LCD_SEG5
PE9
LCD segment line 5. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
LCD_SEG6
PE10
LCD segment line 6. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
LCD_SEG7
PE11
LCD segment line 7. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
LCD_SEG8
PE12
LCD segment line 8. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG9
PE13
LCD segment line 9. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG10
PE14
LCD segment line 10. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG11
PE15
LCD segment line 11. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG12
PA15
LCD segment line 12. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG13
PA0
LCD segment line 13. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG14
PA1
LCD segment line 14. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG15
PA2
LCD segment line 15. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG16
PA3
LCD segment line 16. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG17
PA4
LCD segment line 17. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG18
PA5
LCD segment line 18. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
silabs.com | Building a more connected world.
Rev. 2.30 | 361
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
LCD_SEG19
PA6
LCD segment line 19. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG20/ LCD_COM4
PB3
LCD segment line 20. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 4
LCD_SEG21/ LCD_COM5
PB4
LCD segment line 21. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 5
LCD_SEG22/ LCD_COM6
PB5
LCD segment line 22. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 6
LCD_SEG23/ LCD_COM7
PB6
LCD segment line 23. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 7
LES_ALTEX0 PD6
LESENSE alternate exite output 0.
LES_ALTEX1 PD7
LESENSE alternate exite output 1.
LES_ALTEX2 PA3
LESENSE alternate exite output 2.
LES_ALTEX3 PA4
LESENSE alternate exite output 3.
LES_ALTEX4 PA5
LESENSE alternate exite output 4.
LES_ALTEX5 PE11
LESENSE alternate exite output 5.
LES_ALTEX6 PE12
LESENSE alternate exite output 6.
LES_ALTEX7 PE13
LESENSE alternate exite output 7.
LES_CH4
PC4
LESENSE channel 4.
LES_CH5
PC5
LESENSE channel 5.
LES_CH6
PC6
LESENSE channel 6.
LES_CH7
PC7
LESENSE channel 7.
LETIM0_OUT0 PD6 PB11 PF0 PC4
Low Energy Timer LETIM0, output channel 0.
LETIM0_OUT1 PD7 PB12 PF1 PC5
Low Energy Timer LETIM0, output channel 1.
LEU0_RX
PD5 PB14 PE15 PF1 PA0
LEUART0 Receive input.
LEU0_TX
PD4 PB13 PE14 PF0 PF2
LEUART0 Transmit output. Also used as receive input in half duplex communication.
LEU1_RX
PC7 PA6
LEUART1 Receive input.
LEU1_TX
PC6 PA5
LEUART1 Transmit output. Also used as receive input in half duplex communication.
LFXTAL_N
PB8
Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin.
LFXTAL_P
PB7
Low Frequency Crystal (typically 32.768 kHz) positive pin.
OPAMP_N0 / DAC0_N0
PC5
Operational Amplifier 0 external negative input.
OPAMP_N1 / DAC0_N1
PD7
Operational Amplifier 1 external negative input.
silabs.com | Building a more connected world.
Rev. 2.30 | 362
Alternate
Functionality
0
1
OPAMP_N2
PD3
OPAMP_OUT2 PD5 PD0
OPAMP_P0 / DAC0_P0
PC4
OPAMP_P1 / DAC0_P1
PD6
OPAMP_P2
PD4
PCNT0_S0IN
PCNT0_S1IN
PCNT1_S0IN PC4 PB3
PCNT1_S1IN PC5 PB4
PCNT2_S0IN PD0 PE8
PCNT2_S1IN PD1 PE9
PRS_CH0
PA0
PRS_CH1
PA1
PRS_CH2
PF5
PRS_CH3
PE8
TIM0_CC0
PA0 PA0
TIM0_CC1
PA1 PA1
TIM0_CC2
PA2 PA2
TIM0_CDTI0
PA3
LOCATION
2
3
4
5
PD6 PD7
PD1 PA0 PF0
PD2
PF1
PD3
PF2
TIM0_CDTI1
PA4
TIM0_CDTI2
TIM1_CC0 TIM1_CC1 TIM1_CC2 TIM2_CC0 TIM2_CC1 TIM2_CC2 TIM3_CC0 TIM3_CC1 TIM3_CC2 US0_CLK US0_CS
PA5
PF5
PE14 PE15 PA15 PE12 PE13
PE10 PE11 PE12 PA12 PA13 PA14
PE5 PE4
PC4 PF5 PB7 PD6 PB8 PD7 PB11
PB13 PB13 PB14 PB14
EFM32LG Data Sheet
Pin Definitions
6
Description
Operational Amplifier 2 external negative input.
Operational Amplifier 2 output.
Operational Amplifier 0 external positive input.
Operational Amplifier 1 external positive input.
Operational Amplifier 2 external positive input. Pulse Counter PCNT0 input number 0. Pulse Counter PCNT0 input number 1. Pulse Counter PCNT1 input number 0. Pulse Counter PCNT1 input number 1. Pulse Counter PCNT2 input number 0. Pulse Counter PCNT2 input number 1. Peripheral Reflex System PRS, channel 0. Peripheral Reflex System PRS, channel 1. Peripheral Reflex System PRS, channel 2. Peripheral Reflex System PRS, channel 3. Timer 0 Capture Compare input / output channel 0. Timer 0 Capture Compare input / output channel 1. Timer 0 Capture Compare input / output channel 2. Timer 0 Complimentary Deat Time Insertion channel 0. Timer 0 Complimentary Deat Time Insertion channel 1. Timer 0 Complimentary Deat Time Insertion channel 2. Timer 1 Capture Compare input / output channel 0. Timer 1 Capture Compare input / output channel 1. Timer 1 Capture Compare input / output channel 2. Timer 2 Capture Compare input / output channel 0. Timer 2 Capture Compare input / output channel 1. Timer 2 Capture Compare input / output channel 2. Timer 3 Capture Compare input / output channel 0. Timer 3 Capture Compare input / output channel 1. Timer 3 Capture Compare input / output channel 2. USART0 clock input / output. USART0 chip select input / output.
silabs.com | Building a more connected world.
Rev. 2.30 | 363
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
US0_RX
PE11 PE6
PE12 PB8
USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output (MISO).
US0_TX
PE10 PE7
PE13 PB7
USART0 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input (MOSI).
US1_CLK
PB7 PD2 PF0
USART1 clock input / output.
US1_CS
PB8 PD3 PF1
USART1 chip select input / output.
US1_RX
PD1 PD6
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output (MISO).
US1_TX
PD0 PD7
USART1 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input (MOSI).
US2_CLK
PC4 PB5
USART2 clock input / output.
US2_CS
PC5 PB6
USART2 chip select input / output.
US2_RX
PB4
USART2 Asynchronous Receive.
USART2 Synchronous mode Master Input / Slave Output (MISO).
US2_TX
PB3
USART2 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART2 Synchronous mode Master Output / Slave Input (MOSI).
USB_DM
PF10
USB D- pin.
USB_DMPU
PD2
USB D- Pullup control.
USB_DP
PF11
USB D+ pin.
USB_ID
PF12
USB ID pin. Used in OTG mode.
USB_VBUS
USB_V BUS
USB 5 V VBUS input.
USB_VBUSEN PF5
USB 5 V VBUS enable.
USB_VREGI
USB_V REGI
USB Input to internal 3.3 V regulator
USB_VREGO
USB_V REGO
USB Decoupling for internal 3.3 V USB regulator and regulator output
silabs.com | Building a more connected world.
Rev. 2.30 | 364
EFM32LG Data Sheet
Pin Definitions
5.18.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG940 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.54. GPIO Pinout
Port
Port A Port B Port C Port D Port E Port F
Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 15 14 13 12 11 10 PA15 PA14 PA13 PA12 -- -- -- -- -- PA6 PA5 PA4 PA3 PA2 PA1 PA0 -- PB14 PB13 PB12 PB11 -- -- PB8 PB7 PB6 PB5 PB4 PB3 -- -- -- -- -- -- -- -- -- -- -- PC7 PC6 PC5 PC4 -- -- -- -- -- -- -- -- -- -- -- PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 -- -- -- -- -- -- -- PF12 PF11 PF10 -- -- -- -- PF5 -- -- PF2 PF1 PF0
5.18.4 Opamp Pinout Overview
The specific opamp terminals available in EFM32LG940 is shown in the following figure.
PC4
+ OUT0ALT
OPA0 OUT0
PC5
-
PD4
+
PD3
OPA2 -
OUT2
PD6
+ OUT1ALT
PD7
OPA1 -
OUT1
PB11 PB12
PC12 PC13 PC14 PC15 PD0 PD1 PD5
Figure 5.36. Opamp Pinout
silabs.com | Building a more connected world.
Rev. 2.30 | 365
5.19 EFM32LG942 (TQFP64)
EFM32LG Data Sheet
Pin Definitions
5.19.1 Pinout
The EFM32LG942 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question.
Figure 5.37. EFM32LG942 Pinout (top view, not to scale) Table 5.55. Device Pinout
QFP64 Pin# and Name
Pin #
Pin Name
1
PA0
2
PA1
3
PA2
Analog LCD_SEG13 LCD_SEG14 LCD_SEG15
Pin Alternate Functionality / Description
Timers
Communication
TIM0_CC0 #0/1/4
LEU0_RX #4 I2C0_SDA #0
TIM0_CC1 #0/1
I2C0_SCL #0
TIM0_CC2 #0/1
Other
PRS_CH0 #0 GPIO_EM4WU0
CMU_CLK1 #0 PRS_CH1 #0
CMU_CLK0 #0 ETM_TD0 #3
silabs.com | Building a more connected world.
Rev. 2.30 | 366
EFM32LG Data Sheet
Pin Definitions
QFP64 Pin# and Name
Pin #
Pin Name
4
PA3
5
PA4
6
PA5
7
IOVDD_0
8
VSS
9
PB3
10
PB4
11
PB5
12
PB6
13
PC4
14
PC5
15
PB7
16
PB8
17
PA12
18
PA13
19
PA14
20
RESETn
21
PB11
22
VSS
23
AVDD_1
24
PB13
25
PB14
26
IOVDD_3
27
AVDD_0
28
PD0
Pin Alternate Functionality / Description
Analog
Timers
Communication
Other
LCD_SEG16
TIM0_CDTI0 #0
LES_ALTEX2 #0 ETM_TD1 #3
LCD_SEG17
TIM0_CDTI1 #0
LES_ALTEX3 #0 ETM_TD2 #3
LCD_SEG18
TIM0_CDTI2 #0
LEU1_TX #1
LES_ALTEX4 #0 ETM_TD3 #3
Digital IO power supply 0.
Ground.
LCD_SEG20/ LCD_COM4
PCNT1_S0IN #1
US2_TX #1
LCD_SEG21/ LCD_COM5
PCNT1_S1IN #1
US2_RX #1
LCD_SEG22/ LCD_COM6
US2_CLK #1
LCD_SEG23/ LCD_COM7
US2_CS #1
ACMP0_CH4 / DAC0_P0 / OPAMP_P0
TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0
US2_CLK #0 I2C1_SDA #0
LES_CH4 #0
ACMP0_CH5 / DAC0_N0 / OPAMP_N0
LETIM0_OUT1 #3 PCNT1_S1IN #0
US2_CS #0 I2C1_SCL #0
LES_CH5 #0
LFXTAL_P
TIM1_CC0 #3
US0_TX #4 US1_CLK #0
LFXTAL_N
TIM1_CC1 #3
US0_RX #4 US1_CS #0
LCD_BCAP_P
TIM2_CC0 #1
LCD_BCAP_N
TIM2_CC1 #1
LCD_BEXT
TIM2_CC2 #1
Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released.
DAC0_OUT0 / OPAMP_OUT0
TIM1_CC2 #3 LETIM0_OUT0 #1
I2C1_SDA #1
Ground.
Analog power supply 1.
HFXTAL_P
US0_CLK #4/5 LEU0_TX #1
HFXTAL_N
US0_CS #4/5 LEU0_RX #1
Digital IO power supply 3.
Analog power supply 0.
ADC0_CH0 DAC0_OUT0ALT #4/ OPAMP_OUT0ALT
OPAMP_OUT2 #1
PCNT2_S0IN #0
US1_TX #1
silabs.com | Building a more connected world.
Rev. 2.30 | 367
EFM32LG Data Sheet
Pin Definitions
QFP64 Pin# and Name
Pin #
Pin Name
29
PD1
30
PD2
31
PD3
32
PD4
33
PD5
34
PD6
35
PD7
36
PD8
37
PC6
38
PC7
39
VDD_DREG
40
DECOUPLE
41
PE4
42
PE5
43
PE6
44
PE7
45
USB_VREGI
46
USB_VREGO
47
PF10
48
PF11
49
PF0
50
PF1
51
PF2
52
USB_VBUS
53
PF12
54
PF5
55
IOVDD_5
Pin Alternate Functionality / Description
Analog
Timers
Communication
Other
ADC0_CH1 DAC0_OUT1ALT #4/ OPAMP_OUT1ALT
TIM0_CC0 #3 PCNT2_S1IN #0
US1_RX #1
DBG_SWO #2
ADC0_CH2
TIM0_CC1 #3
USB_DMPU #0 US1_CLK #1
DBG_SWO #3
ADC0_CH3 OPAMP_N2
TIM0_CC2 #3
US1_CS #1
ETM_TD1 #0/2
ADC0_CH4 OPAMP_P2
LEU0_TX #0
ETM_TD2 #0/2
ADC0_CH5 OPAMP_OUT2 #0
LEU0_RX #0
ETM_TD3 #0/2
ADC0_CH6 / DAC0_P1 / OPAMP_P1
TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3
US1_RX #2 I2C0_SDA #1
LES_ALTEX0 #0 ACMP0_O #2 ETM_TD0 #0
ADC0_CH7 / DAC0_N1 / OPAMP_N1
TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3
US1_TX #2 I2C0_SCL #1
CMU_CLK0 #2 LES_ALTEX1 #0
ACMP1_O #2 ETM_TCLK #0
BU_VIN
CMU_CLK1 #1
ACMP0_CH6
LEU1_TX #0 I2C0_SDA #2
LES_CH6 #0 ETM_TCLK #2
ACMP0_CH7
LEU1_RX #0 I2C0_SCL LES_CH7 #0 ETM_TD0
#2
#2
Power supply for on-chip voltage regulator.
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin.
LCD_COM0
US0_CS #1
LCD_COM1
US0_CLK #1
LCD_COM2
US0_RX #1
LCD_COM3
US0_TX #1
Input to internal 3.3V USB regulator
Output and decoupling for internal 3.3V USB regulator
USB_DM
USB_DP
TIM0_CC0 #5 LETIM0_OUT0 #2
US1_CLK #2 LEU0_TX #3 I2C0_SDA #5
DBG_SWCLK #0/1/2/3
TIM0_CC1 #5 LETIM0_OUT1 #2
US1_CS #2 LEU0_RX DBG_SWDIO #0/1/2/3
#3 I2C0_SCL #5
GPIO_EM4WU3
LCD_SEG0
TIM0_CC2 #5
LEU0_TX #4
ACMP1_O #0 DBG_SWO #0 GPIO_EM4WU4
USB 5.0 V VBUS input.
USB_ID
LCD_SEG3
TIM0_CDTI2 #2/5
USB_VBUSEN #0
PRS_CH2 #1
Digital IO power supply 5.
silabs.com | Building a more connected world.
Rev. 2.30 | 368
QFP64 Pin# and Name
Pin #
Pin Name
56
VSS
57
PE8
58
PE9
59
PE10
Analog Ground.
LCD_SEG4 LCD_SEG5 LCD_SEG6
60
PE11
LCD_SEG7
61
PE12
LCD_SEG8
62
PE13
63
PE14
64
PE15
LCD_SEG9
LCD_SEG10 LCD_SEG11
Pin Alternate Functionality / Description
Timers
Communication
EFM32LG Data Sheet
Pin Definitions
Other
PCNT2_S0IN #1 PCNT2_S1IN #1
TIM1_CC0 #1 TIM1_CC1 #1 TIM1_CC2 #1
TIM3_CC0 #0 TIM3_CC1 #0
US0_TX #0
US0_RX #0
US0_RX #3 US0_CLK #0 I2C0_SDA #6
US0_TX #3 US0_CS #0 I2C0_SCL #6
LEU0_TX #2 LEU0_RX #2
PRS_CH3 #1
BOOT_TX LES_ALTEX5 #0
BOOT_RX CMU_CLK1 #2 LES_ALTEX6 #0 LES_ALTEX7 #0 ACMP0_O #0 GPIO_EM4WU5
silabs.com | Building a more connected world.
Rev. 2.30 | 369
EFM32LG Data Sheet
Pin Definitions
5.19.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0.
Table 5.56. Alternate Functionality Overview
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
ACMP0_CH4 PC4
Analog comparator ACMP0, channel 4.
ACMP0_CH5 PC5
Analog comparator ACMP0, channel 5.
ACMP0_CH6 PC6
Analog comparator ACMP0, channel 6.
ACMP0_CH7 PC7
Analog comparator ACMP0, channel 7.
ACMP0_O
PE13
PD6
Analog comparator ACMP0, digital output.
ACMP1_O
PF2
PD7
Analog comparator ACMP1, digital output.
ADC0_CH0
PD0
Analog to digital converter ADC0, input channel number 0.
ADC0_CH1
PD1
Analog to digital converter ADC0, input channel number 1.
ADC0_CH2
PD2
Analog to digital converter ADC0, input channel number 2.
ADC0_CH3
PD3
Analog to digital converter ADC0, input channel number 3.
ADC0_CH4
PD4
Analog to digital converter ADC0, input channel number 4.
ADC0_CH5
PD5
Analog to digital converter ADC0, input channel number 5.
ADC0_CH6
PD6
Analog to digital converter ADC0, input channel number 6.
ADC0_CH7
PD7
Analog to digital converter ADC0, input channel number 7.
BOOT_RX
PE11
Bootloader RX.
BOOT_TX
PE10
Bootloader TX.
BU_VIN
PD8
Battery input for Backup Power Domain
CMU_CLK0
PA2
PD7
Clock Management Unit, clock output number 0.
CMU_CLK1
PA1 PD8 PE12
Clock Management Unit, clock output number 1.
DAC0_OUT0 / OPAMP_OUT0
PB11
Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0.
DAC0_OUT0ALT / OPAMP_OUT0A LT
PD0
Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0.
DAC0_OUT1ALT / OPAMP_OUT1A LT
PD1
Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1.
silabs.com | Building a more connected world.
Rev. 2.30 | 370
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
DBG_SWCLK PF0 PF0 PF0 PF0
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, and has a built-in pull down.
DBG_SWDIO PF1 PF1 PF1 PF1
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and has a built-in pull up.
DBG_SWO
PF2
PD1 PD2
Debug-interface Serial Wire viewer Output.
Note that this function is not enabled after reset, and must be enabled by software to be used.
ETM_TCLK
PD7
PC6
Embedded Trace Module ETM clock .
ETM_TD0
PD6
PC7 PA2
Embedded Trace Module ETM data 0.
ETM_TD1
PD3
PD3 PA3
Embedded Trace Module ETM data 1.
ETM_TD2
PD4
PD4 PA4
Embedded Trace Module ETM data 2.
ETM_TD3
PD5
PD5 PA5
Embedded Trace Module ETM data 3.
GPIO_EM4WU0 PA0
Pin can be used to wake the system up from EM4
GPIO_EM4WU3 PF1
Pin can be used to wake the system up from EM4
GPIO_EM4WU4 PF2
Pin can be used to wake the system up from EM4
GPIO_EM4WU5 PE13
Pin can be used to wake the system up from EM4
HFXTAL_N
PB14
High Frequency Crystal negative pin. Also used as external optional clock input pin.
HFXTAL_P
PB13
High Frequency Crystal positive pin.
I2C0_SCL
PA1 PD7 PC7
PF1 PE13 I2C0 Serial Clock Line input / output.
I2C0_SDA
PA0 PD6 PC6
PF0 PE12 I2C0 Serial Data input / output.
I2C1_SCL
PC5
I2C1 Serial Clock Line input / output.
I2C1_SDA
PC4
I2C1 Serial Data input / output.
LCD_BCAP_N PA13
LCD voltage booster (optional), boost capacitor, negative pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P.
LCD_BCAP_P PA12
LCD voltage booster (optional), boost capacitor, positive pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P.
LCD voltage booster (optional), boost output. If using the LCD voltage booster, connect a 1 uF capacitor between this pin and VSS.
LCD_BEXT
PA14
An external LCD voltage may also be applied to this pin if the booster is not enabled.
If AVDD is used directly as the LCD supply voltage, this pin may be left unconnected or used as a GPIO.
LCD_COM0
PE4
LCD driver common line number 0.
LCD_COM1
PE5
LCD driver common line number 1.
silabs.com | Building a more connected world.
Rev. 2.30 | 371
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
LCD_COM2
PE6
LCD driver common line number 2.
LCD_COM3
PE7
LCD driver common line number 3.
LCD_SEG0
PF2
LCD segment line 0. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
LCD_SEG3
PF5
LCD segment line 3. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
LCD_SEG4
PE8
LCD segment line 4. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
LCD_SEG5
PE9
LCD segment line 5. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
LCD_SEG6
PE10
LCD segment line 6. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
LCD_SEG7
PE11
LCD segment line 7. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
LCD_SEG8
PE12
LCD segment line 8. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG9
PE13
LCD segment line 9. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG10
PE14
LCD segment line 10. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG11
PE15
LCD segment line 11. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG13
PA0
LCD segment line 13. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG14
PA1
LCD segment line 14. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG15
PA2
LCD segment line 15. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG16
PA3
LCD segment line 16. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG17
PA4
LCD segment line 17. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG18
PA5
LCD segment line 18. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG20/ LCD_COM4
PB3
LCD segment line 20. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 4
LCD_SEG21/ LCD_COM5
PB4
LCD segment line 21. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 5
LCD_SEG22/ LCD_COM6
PB5
LCD segment line 22. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 6
LCD_SEG23/ LCD_COM7
PB6
LCD segment line 23. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 7
silabs.com | Building a more connected world.
Rev. 2.30 | 372
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
LES_ALTEX0 PD6
LESENSE alternate exite output 0.
LES_ALTEX1 PD7
LESENSE alternate exite output 1.
LES_ALTEX2 PA3
LESENSE alternate exite output 2.
LES_ALTEX3 PA4
LESENSE alternate exite output 3.
LES_ALTEX4 PA5
LESENSE alternate exite output 4.
LES_ALTEX5 PE11
LESENSE alternate exite output 5.
LES_ALTEX6 PE12
LESENSE alternate exite output 6.
LES_ALTEX7 PE13
LESENSE alternate exite output 7.
LES_CH4
PC4
LESENSE channel 4.
LES_CH5
PC5
LESENSE channel 5.
LES_CH6
PC6
LESENSE channel 6.
LES_CH7
PC7
LESENSE channel 7.
LETIM0_OUT0 PD6 PB11 PF0 PC4
Low Energy Timer LETIM0, output channel 0.
LETIM0_OUT1 PD7
PF1 PC5
Low Energy Timer LETIM0, output channel 1.
LEU0_RX
PD5 PB14 PE15 PF1 PA0
LEUART0 Receive input.
LEU0_TX
PD4 PB13 PE14 PF0 PF2
LEUART0 Transmit output. Also used as receive input in half duplex communication.
LEU1_RX
PC7
LEUART1 Receive input.
LEU1_TX
PC6 PA5
LEUART1 Transmit output. Also used as receive input in half duplex communication.
LFXTAL_N
PB8
Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin.
OPAMP_N0 / DAC0_N0
PC5
Operational Amplifier 0 external negative input.
OPAMP_N1 / DAC0_N1
PD7
Operational Amplifier 1 external negative input.
OPAMP_N2
PD3
Operational Amplifier 2 external negative input.
OPAMP_OUT2 PD5 PD0
Operational Amplifier 2 output.
OPAMP_P0 / DAC0_P0
PC4
Operational Amplifier 0 external positive input.
OPAMP_P1 / DAC0_P1
PD6
Operational Amplifier 1 external positive input.
OPAMP_P2
PD4
Operational Amplifier 2 external positive input.
LFXTAL_P
PB7
Low Frequency Crystal (typically 32.768 kHz) positive pin.
PCNT0_S0IN
PD6
Pulse Counter PCNT0 input number 0.
PCNT0_S1IN
PD7
Pulse Counter PCNT0 input number 1.
PCNT1_S0IN PC4 PB3
Pulse Counter PCNT1 input number 0.
PCNT1_S1IN PC5 PB4
Pulse Counter PCNT1 input number 1.
silabs.com | Building a more connected world.
Rev. 2.30 | 373
Alternate
Functionality
0
1
PCNT2_S0IN PD0 PE8
PCNT2_S1IN PD1 PE9
PRS_CH0
PA0
PRS_CH1
PA1
PRS_CH2
PF5
PRS_CH3
PE8
TIM0_CC0
PA0 PA0
TIM0_CC1
PA1 PA1
TIM0_CC2
PA2 PA2
TIM0_CDTI0
PA3
LOCATION
2
3
4
5
PD1 PA0 PF0
PD2
PF1
PD3
PF2
TIM0_CDTI1
PA4
TIM0_CDTI2
TIM1_CC0 TIM1_CC1 TIM1_CC2 TIM2_CC0 TIM2_CC1 TIM2_CC2 TIM3_CC0 TIM3_CC1 US0_CLK US0_CS
PA5
PF5
PE14 PE15 PE12 PE13
PE10 PE11 PE12 PA12 PA13 PA14
PE5 PE4
PC4 PF5 PB7 PD6 PB8 PD7 PB11
PB13 PB13 PB14 PB14
US0_RX
PE11 PE6
PE12 PB8
US0_TX
US1_CLK US1_CS US1_RX
PE10 PE7
PE13 PB7
PB7 PD2 PF0 PB8 PD3 PF1
PD1 PD6
EFM32LG Data Sheet
Pin Definitions
6
Description
Pulse Counter PCNT2 input number 0.
Pulse Counter PCNT2 input number 1.
Peripheral Reflex System PRS, channel 0.
Peripheral Reflex System PRS, channel 1.
Peripheral Reflex System PRS, channel 2.
Peripheral Reflex System PRS, channel 3.
Timer 0 Capture Compare input / output channel 0.
Timer 0 Capture Compare input / output channel 1.
Timer 0 Capture Compare input / output channel 2.
Timer 0 Complimentary Deat Time Insertion channel 0.
Timer 0 Complimentary Deat Time Insertion channel 1.
Timer 0 Complimentary Deat Time Insertion channel 2.
Timer 1 Capture Compare input / output channel 0.
Timer 1 Capture Compare input / output channel 1.
Timer 1 Capture Compare input / output channel 2.
Timer 2 Capture Compare input / output channel 0.
Timer 2 Capture Compare input / output channel 1.
Timer 2 Capture Compare input / output channel 2.
Timer 3 Capture Compare input / output channel 0.
Timer 3 Capture Compare input / output channel 1.
USART0 clock input / output.
USART0 chip select input / output.
USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output (MISO).
USART0 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input (MOSI).
USART1 clock input / output.
USART1 chip select input / output.
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output (MISO).
silabs.com | Building a more connected world.
Rev. 2.30 | 374
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
US1_TX
PD0 PD7
USART1 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input (MOSI).
US2_CLK
PC4 PB5
USART2 clock input / output.
US2_CS
PC5 PB6
USART2 chip select input / output.
US2_RX
PB4
USART2 Asynchronous Receive.
USART2 Synchronous mode Master Input / Slave Output (MISO).
US2_TX
PB3
USART2 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART2 Synchronous mode Master Output / Slave Input (MOSI).
USB_DM
PF10
USB D- pin.
USB_DMPU
PD2
USB D- Pullup control.
USB_DP
PF11
USB D+ pin.
USB_ID
PF12
USB ID pin. Used in OTG mode.
USB_VBUS
USB_V BUS
USB 5 V VBUS input.
USB_VBUSEN PF5
USB 5 V VBUS enable.
USB_VREGI
USB_V REGI
USB Input to internal 3.3 V regulator
USB_VREGO
USB_V REGO
USB Decoupling for internal 3.3 V USB regulator and regulator output
5.19.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG942 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.57. GPIO Pinout
Port
Port A Port B Port C Port D Port E Port F
Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 15 14 13 12 11 10 -- PA14 PA13 PA12 -- -- -- -- -- -- PA5 PA4 PA3 PA2 PA1 PA0 -- PB14 PB13 -- PB11 -- -- PB8 PB7 PB6 PB5 PB4 PB3 -- -- -- -- -- -- -- -- -- -- -- PC7 PC6 PC5 PC4 -- -- -- -- -- -- -- -- -- -- -- PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 -- -- -- -- -- -- -- PF12 PF11 PF10 -- -- -- -- PF5 -- -- PF2 PF1 PF0
silabs.com | Building a more connected world.
Rev. 2.30 | 375
5.19.4 Opamp Pinout Overview
The specific opamp terminals available in EFM32LG942 is shown in the following figure.
PC4
+ OUT0ALT
PC5
OPA0 -
OUT0
PD4
+
PD3
OPA2 -
OUT2
PD6
+ OUT1ALT
PD7
OPA1 -
OUT1
PB11
PC12 PC13 PC14 PC15 PD0 PD1 PD5
Figure 5.38. Opamp Pinout
EFM32LG Data Sheet
Pin Definitions
silabs.com | Building a more connected world.
Rev. 2.30 | 376
5.20 EFM32LG980 (LQFP100)
EFM32LG Data Sheet
Pin Definitions
5.20.1 Pinout
The EFM32LG980 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question.
Figure 5.39. EFM32LG980 Pinout (top view, not to scale)
silabs.com | Building a more connected world.
Rev. 2.30 | 377
EFM32LG Data Sheet
Pin Definitions
Table 5.58. Device Pinout
LQFP100 Pin# and Name
Pin # Pin Name
1
PA0
2
PA1
Analog LCD_SEG13 LCD_SEG14
Pin Alternate Functionality / Description
EBI EBI_AD09 #0/1/2
Timers TIM0_CC0 #0/1/4
Communication
LEU0_RX #4 I2C0_SDA #0
EBI_AD10 #0/1/2 TIM0_CC1 #0/1
I2C0_SCL #0
3
PA2
LCD_SEG15
EBI_AD11 #0/1/2 TIM0_CC2 #0/1
4
PA3
LCD_SEG16
EBI_AD12 #0/1/2 TIM0_CDTI0 #0
U0_TX #2
5
PA4
LCD_SEG17
EBI_AD13 #0/1/2 TIM0_CDTI1 #0
U0_RX #2
6
PA5
LCD_SEG18
EBI_AD14 #0/1/2 TIM0_CDTI2 #0
LEU1_TX #1
7
PA6
LCD_SEG19
EBI_AD15 #0/1/2
LEU1_RX #1
8
IOVDD_0 Digital IO power supply 0.
9
PB0
LCD_SEG32
EBI_A16 #0/1/2
TIM1_CC0 #2
10
PB1
LCD_SEG33
EBI_A17 #0/1/2
TIM1_CC1 #2
11
PB2
LCD_SEG34
EBI_A18 #0/1/2
TIM1_CC2 #2
12
PB3
LCD_SEG20/ LCD_COM4
EBI_A19 #0/1/2
PCNT1_S0IN #1
US2_TX #1
13
PB4
LCD_SEG21/ LCD_COM5
EBI_A20 #0/1/2
PCNT1_S1IN #1
US2_RX #1
14
PB5
LCD_SEG22/ LCD_COM6
EBI_A21 #0/1/2
US2_CLK #1
15
PB6
LCD_SEG23/ LCD_COM7
EBI_A22 #0/1/2
US2_CS #1
16
VSS
Ground.
17
IOVDD_1 Digital IO power supply 1.
18
PC0
ACMP0_CH0 DAC0_OUT0ALT
#0/ OPAMP_OUT0ALT
EBI_A23 #0/1/2
TIM0_CC1 #4 PCNT0_S0IN #2
US0_TX #5 US1_TX #0 I2C0_SDA #4
19
PC1
ACMP0_CH1 DAC0_OUT0ALT
#1/ OPAMP_OUT0ALT
EBI_A24 #0/1/2
TIM0_CC2 #4 PCNT0_S1IN #2
US0_RX #5 US1_RX #0 I2C0_SCL #4
ACMP0_CH2
20
PC2
DAC0_OUT0ALT #2/
EBI_A25 #0/1/2
TIM0_CDTI0 #4
US2_TX #0
OPAMP_OUT0ALT
Other PRS_CH0 #0 GPIO_EM4WU0 CMU_CLK1 #0 PRS_CH1 #0 CMU_CLK0 #0 ETM_TD0 #3 LES_ALTEX2 #0 ETM_TD1 #3 LES_ALTEX3 #0 ETM_TD2 #3 LES_ALTEX4 #0 ETM_TD3 #3 ETM_TCLK #3 GPIO_EM4WU1
LES_CH0 #0 PRS_CH2 #0
LES_CH1 #0 PRS_CH3 #0
LES_CH2 #0
silabs.com | Building a more connected world.
Rev. 2.30 | 378
EFM32LG Data Sheet
Pin Definitions
LQFP100 Pin# and Name
Pin # Pin Name
21
PC3
22
PC4
23
PC5
24
PB7
25
PB8
26
PA7
27
PA8
28
PA9
29
PA10
30
PA11
31
IOVDD_2
32
VSS
33
PA12
34
PA13
35
PA14
36
RESETn
37
PB9
38
PB10
39
PB11
40
PB12
41
AVDD_1
42
PB13
43
PB14
44
IOVDD_3
45
AVDD_0
Pin Alternate Functionality / Description
Analog
EBI
Timers
Communication
Other
ACMP0_CH3 DAC0_OUT0ALT
#3/ OPAMP_OUT0ALT
EBI_NANDREn #0/1/2
TIM0_CDTI1 #4
US2_RX #0
LES_CH3 #0
ACMP0_CH4 / DAC0_P0 / OPAMP_P0
EBI_A26 #0/1/2
TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0
US2_CLK #0 I2C1_SDA #0
LES_CH4 #0
ACMP0_CH5 / DAC0_N0 / OPAMP_N0
EBI_NANDWEn #0/1/2
LETIM0_OUT1 #3 PCNT1_S1IN #0
US2_CS #0 I2C1_SCL #0
LES_CH5 #0
LFXTAL_P
TIM1_CC0 #3
US0_TX #4 US1_CLK #0
LFXTAL_N
TIM1_CC1 #3
US0_RX #4 US1_CS #0
LCD_SEG35
EBI_CSTFT #0/1/2
LCD_SEG36
EBI_DCLK #0/1/2
TIM2_CC0 #0
LCD_SEG37
EBI_DTEN #0/1/2
TIM2_CC1 #0
LCD_SEG38
EBI_VSNC #0/1/2
TIM2_CC2 #0
LCD_SEG39
EBI_HSNC #0/1/2
Digital IO power supply 2.
Ground.
LCD_BCAP_P
EBI_A00 #0/1/2
TIM2_CC0 #1
LCD_BCAP_N
EBI_A01 #0/1/2
TIM2_CC1 #1
LCD_BEXT
EBI_A02 #0/1/2
TIM2_CC2 #1
Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released.
EBI_A03 #0/1/2
U1_TX #2
EBI_A04 #0/1/2
U1_RX #2
DAC0_OUT0 / OPAMP_OUT0
TIM1_CC2 #3 LETIM0_OUT0 #1
I2C1_SDA #1
DAC0_OUT1 / OPAMP_OUT1
LETIM0_OUT1 #1
I2C1_SCL #1
Analog power supply 1.
HFXTAL_P
US0_CLK #4/5 LEU0_TX #1
HFXTAL_N
US0_CS #4/5 LEU0_RX #1
Digital IO power supply 3.
Analog power supply 0.
silabs.com | Building a more connected world.
Rev. 2.30 | 379
EFM32LG Data Sheet
Pin Definitions
LQFP100 Pin# and Name
Pin # Pin Name
46
PD0
47
PD1
48
PD2
49
PD3
50
PD4
51
PD5
52
PD6
53
PD7
54
PD8
55
PC6
56
PC7
57 VDD_DREG
58
VSS
59 DECOUPLE
60
PE0
61
PE1
62
PE2
63
PE3
64
PE4
65
PE5
66
PE6
67
PE7
68
PC8
Pin Alternate Functionality / Description
Analog
EBI
Timers
Communication
Other
ADC0_CH0 DAC0_OUT0ALT
#4/ OPAMP_OUT0ALT OPAMP_OUT2 #1
PCNT2_S0IN #0
US1_TX #1
ADC0_CH1 DAC0_OUT1ALT
#4/ OPAMP_OUT1ALT
TIM0_CC0 #3 PCNT2_S1IN #0
US1_RX #1
DBG_SWO #2
ADC0_CH2
EBI_A27 #0/1/2
TIM0_CC1 #3
USB_DMPU #0 US1_CLK #1
DBG_SWO #3
ADC0_CH3 OPAMP_N2
TIM0_CC2 #3
US1_CS #1
ETM_TD1 #0/2
ADC0_CH4 OPAMP_P2
LEU0_TX #0
ETM_TD2 #0/2
ADC0_CH5 OPAMP_OUT2 #0
LEU0_RX #0
ETM_TD3 #0/2
ADC0_CH6 / DAC0_P1 / OPAMP_P1
TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3
US1_RX #2 I2C0_SDA #1
LES_ALTEX0 #0 ACMP0_O #2 ETM_TD0 #0
ADC0_CH7 / DAC0_N1 / OPAMP_N1
TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3
US1_TX #2 I2C0_SCL #1
CMU_CLK0 #2 LES_ALTEX1 #0
ACMP1_O #2 ETM_TCLK #0
BU_VIN
CMU_CLK1 #1
ACMP0_CH6
EBI_A05 #0/1/2
LEU1_TX #0 I2C0_SDA #2
LES_CH6 #0 ETM_TCLK #2
ACMP0_CH7
EBI_A06 #0/1/2
LEU1_RX #0 I2C0_SCL #2
LES_CH7 #0 ETM_TD0 #2
Power supply for on-chip voltage regulator.
Ground.
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin.
EBI_A07 #0/1/2
TIM3_CC0 #1 PCNT0_S0IN #1
U0_TX #1 I2C1_SDA #2
EBI_A08 #0/1/2
TIM3_CC1 #1 PCNT0_S1IN #1
U0_RX #1 I2C1_SCL #2
BU_VOUT
EBI_A09 #0
TIM3_CC2 #1
U1_TX #3
ACMP0_O #1
BU_STAT
EBI_A10 #0
U1_RX #3
ACMP1_O #1
LCD_COM0
EBI_A11 #0/1/2
US0_CS #1
LCD_COM1
EBI_A12 #0/1/2
US0_CLK #1
LCD_COM2
EBI_A13 #0/1/2
US0_RX #1
LCD_COM3
EBI_A14 #0/1/2
US0_TX #1
ACMP1_CH0
EBI_A15 #0/1/2
TIM2_CC0 #2
US0_CS #2
LES_CH8 #0
silabs.com | Building a more connected world.
Rev. 2.30 | 380
EFM32LG Data Sheet
Pin Definitions
LQFP100 Pin# and Name
Pin # Pin Name
Analog
Pin Alternate Functionality / Description
EBI
Timers
Communication
69
PC9
ACMP1_CH1
EBI_A09 #1/2
TIM2_CC1 #2
US0_CLK #2
70
PC10
ACMP1_CH2
EBI_A10 #1/2
TIM2_CC2 #2
US0_RX #2
71
PC11
ACMP1_CH3
EBI_ALE #1/2
US0_TX #2
72 USB_VREGI Input to internal 3.3V USB regulator
73 USB_VREGO Output and decoupling for internal 3.3V USB regulator
74
PF10
U1_TX #1 USB_DM
75
PF11
U1_RX #1 USB_DP
76
PF0
TIM0_CC0 #5 LETIM0_OUT0 #2
US1_CLK #2 LEU0_TX #3 I2C0_SDA #5
77
PF1
TIM0_CC1 #5 LETIM0_OUT1 #2
US1_CS #2 LEU0_RX #3 I2C0_SCL #5
78
PF2
LCD_SEG0
EBI_ARDY #0/1/2
TIM0_CC2 #5
LEU0_TX #4
79 USB_VBUS USB 5.0 V VBUS input.
80
PF12
USB_ID
81
PF5
LCD_SEG3
EBI_REn #0/2
TIM0_CDTI2 #2/5 USB_VBUSEN #0
82
IOVDD_5 Digital IO power supply 5.
83
VSS
Ground.
84
PF6
LCD_SEG24
EBI_BL0 #0/1/2
TIM0_CC0 #2
U0_TX #0
85
PF7
LCD_SEG25
EBI_BL1 #0/1/2
TIM0_CC1 #2
U0_RX #0
86
PF8
LCD_SEG26
EBI_WEn #1
TIM0_CC2 #2
87
PF9
LCD_SEG27
EBI_REn #1
88
PD9
LCD_SEG28
EBI_CS0 #0/1/2
89
PD10
LCD_SEG29
EBI_CS1 #0/1/2
90
PD11
LCD_SEG30
EBI_CS2 #0/1/2
91
PD12
LCD_SEG31
EBI_CS3 #0/1/2
92
PE8
LCD_SEG4
EBI_AD00 #0/1/2 PCNT2_S0IN #1
93
PE9
LCD_SEG5
EBI_AD01 #0/1/2 PCNT2_S1IN #1
94
PE10
LCD_SEG6
EBI_AD02 #0/1/2
TIM1_CC0 #1
US0_TX #0
95
PE11
LCD_SEG7
EBI_AD03 #0/1/2
TIM1_CC1 #1
US0_RX #0
96
PE12
LCD_SEG8
EBI_AD04 #0/1/2
TIM1_CC2 #1
US0_RX #3 US0_CLK #0 I2C0_SDA #6
Other LES_CH9 #0 GPIO_EM4WU2 LES_CH10 #0 LES_CH11 #0
DBG_SWCLK #0/1/2/3
DBG_SWDIO #0/1/2/3
GPIO_EM4WU3 ACMP1_O #0 DBG_SWO #0
GPIO_EM4WU4
PRS_CH2 #1
ETM_TCLK #1 ETM_TD0 #1
PRS_CH3 #1
BOOT_TX LES_ALTEX5 #0
BOOT_RX CMU_CLK1 #2 LES_ALTEX6 #0
silabs.com | Building a more connected world.
Rev. 2.30 | 381
LQFP100 Pin# and Name
Pin # Pin Name
97
PE13
98
PE14
99
PE15
100
PA15
Analog
LCD_SEG9
LCD_SEG10 LCD_SEG11 LCD_SEG12
EFM32LG Data Sheet
Pin Definitions
Pin Alternate Functionality / Description
EBI
EBI_AD05 #0/1/2
EBI_AD06 #0/1/2 EBI_AD07 #0/1/2 EBI_AD08 #0/1/2
Timers
TIM3_CC0 #0 TIM3_CC1 #0 TIM3_CC2 #0
Communication
US0_TX #3 US0_CS #0 I2C0_SCL #6
LEU0_TX #2
LEU0_RX #2
Other
LES_ALTEX7 #0 ACMP0_O #0
GPIO_EM4WU5
silabs.com | Building a more connected world.
Rev. 2.30 | 382
EFM32LG Data Sheet
Pin Definitions
5.20.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0.
Table 5.59. Alternate Functionality Overview
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
ACMP0_CH0 PC0
Analog comparator ACMP0, channel 0.
ACMP0_CH1 PC1
Analog comparator ACMP0, channel 1.
ACMP0_CH2 PC2
Analog comparator ACMP0, channel 2.
ACMP0_CH3 PC3
Analog comparator ACMP0, channel 3.
ACMP0_CH4 PC4
Analog comparator ACMP0, channel 4.
ACMP0_CH5 PC5
Analog comparator ACMP0, channel 5.
ACMP0_CH6 PC6
Analog comparator ACMP0, channel 6.
ACMP0_CH7 PC7
Analog comparator ACMP0, channel 7.
ACMP0_O
PE13 PE2 PD6
Analog comparator ACMP0, digital output.
ACMP1_CH0 PC8
Analog comparator ACMP1, channel 0.
ACMP1_CH1 PC9
Analog comparator ACMP1, channel 1.
ACMP1_CH2 PC10
Analog comparator ACMP1, channel 2.
ACMP1_CH3 PC11
Analog comparator ACMP1, channel 3.
ACMP1_O
PF2 PE3 PD7
Analog comparator ACMP1, digital output.
ADC0_CH0
PD0
Analog to digital converter ADC0, input channel number 0.
ADC0_CH1
PD1
Analog to digital converter ADC0, input channel number 1.
ADC0_CH2
PD2
Analog to digital converter ADC0, input channel number 2.
ADC0_CH3
PD3
Analog to digital converter ADC0, input channel number 3.
ADC0_CH4
PD4
Analog to digital converter ADC0, input channel number 4.
ADC0_CH5
PD5
Analog to digital converter ADC0, input channel number 5.
ADC0_CH6
PD6
Analog to digital converter ADC0, input channel number 6.
ADC0_CH7
PD7
Analog to digital converter ADC0, input channel number 7.
BOOT_RX
PE11
Bootloader RX.
BOOT_TX
PE10
Bootloader TX.
silabs.com | Building a more connected world.
Rev. 2.30 | 383
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
BU_STAT
PE3
Backup Power Domain status, whether or not the system is in backup mode
BU_VIN
PD8
Battery input for Backup Power Domain
BU_VOUT
PE2
Power output for Backup Power Domain
CMU_CLK0
PA2
PD7
Clock Management Unit, clock output number 0.
CMU_CLK1
PA1 PD8 PE12
Clock Management Unit, clock output number 1.
DAC0_OUT0 / OPAMP_OUT0
PB11
Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0.
DAC0_OUT0ALT / OPAMP_OUT0A PC0 PC1 PC2 PC3 PD0 LT
Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0.
DAC0_OUT1 / OPAMP_OUT1
PB12
Digital to Analog Converter DAC0_OUT1 /OPAMP output channel number 1.
DAC0_OUT1ALT / OPAMP_OUT1A LT
PD1
Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1.
DBG_SWCLK PF0 PF0 PF0 PF0
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, and has a built-in pull down.
DBG_SWDIO PF1 PF1 PF1 PF1
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and has a built-in pull up.
DBG_SWO
PF2
PD1 PD2
Debug-interface Serial Wire viewer Output.
Note that this function is not enabled after reset, and must be enabled by software to be used.
EBI_A00
PA12 PA12 PA12
External Bus Interface (EBI) address output pin 00.
EBI_A01
PA13 PA13 PA13
External Bus Interface (EBI) address output pin 01.
EBI_A02
PA14 PA14 PA14
External Bus Interface (EBI) address output pin 02.
EBI_A03
PB9 PB9 PB9
External Bus Interface (EBI) address output pin 03.
EBI_A04
PB10 PB10 PB10
External Bus Interface (EBI) address output pin 04.
EBI_A05
PC6 PC6 PC6
External Bus Interface (EBI) address output pin 05.
EBI_A06
PC7 PC7 PC7
External Bus Interface (EBI) address output pin 06.
EBI_A07
PE0 PE0 PE0
External Bus Interface (EBI) address output pin 07.
EBI_A08
PE1 PE1 PE1
External Bus Interface (EBI) address output pin 08.
EBI_A09
PE2 PC9 PC9
External Bus Interface (EBI) address output pin 09.
EBI_A10
PE3 PC10 PC10
External Bus Interface (EBI) address output pin 10.
EBI_A11
PE4 PE4 PE4
External Bus Interface (EBI) address output pin 11.
EBI_A12
PE5 PE5 PE5
External Bus Interface (EBI) address output pin 12.
EBI_A13
PE6 PE6 PE6
External Bus Interface (EBI) address output pin 13.
EBI_A14
PE7 PE7 PE7
External Bus Interface (EBI) address output pin 14.
silabs.com | Building a more connected world.
Rev. 2.30 | 384
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
EBI_A15
PC8 PC8 PC8
External Bus Interface (EBI) address output pin 15.
EBI_A16
PB0 PB0 PB0
External Bus Interface (EBI) address output pin 16.
EBI_A17
PB1 PB1 PB1
External Bus Interface (EBI) address output pin 17.
EBI_A18
PB2 PB2 PB2
External Bus Interface (EBI) address output pin 18.
EBI_A19
PB3 PB3 PB3
External Bus Interface (EBI) address output pin 19.
EBI_A20
PB4 PB4 PB4
External Bus Interface (EBI) address output pin 20.
EBI_A21
PB5 PB5 PB5
External Bus Interface (EBI) address output pin 21.
EBI_A22
PB6 PB6 PB6
External Bus Interface (EBI) address output pin 22.
EBI_A23
PC0 PC0 PC0
External Bus Interface (EBI) address output pin 23.
EBI_A24
PC1 PC1 PC1
External Bus Interface (EBI) address output pin 24.
EBI_A25
PC2 PC2 PC2
External Bus Interface (EBI) address output pin 25.
EBI_A26
PC4 PC4 PC4
External Bus Interface (EBI) address output pin 26.
EBI_A27
PD2 PD2 PD2
External Bus Interface (EBI) address output pin 27.
EBI_AD00
PE8 PE8 PE8
External Bus Interface (EBI) address and data input / output pin 00.
EBI_AD01
PE9 PE9 PE9
External Bus Interface (EBI) address and data input / output pin 01.
EBI_AD02
PE10 PE10 PE10
External Bus Interface (EBI) address and data input / output pin 02.
EBI_AD03
PE11 PE11 PE11
External Bus Interface (EBI) address and data input / output pin 03.
EBI_AD04
PE12 PE12 PE12
External Bus Interface (EBI) address and data input / output pin 04.
EBI_AD05
PE13 PE13 PE13
External Bus Interface (EBI) address and data input / output pin 05.
EBI_AD06
PE14 PE14 PE14
External Bus Interface (EBI) address and data input / output pin 06.
EBI_AD07
PE15 PE15 PE15
External Bus Interface (EBI) address and data input / output pin 07.
EBI_AD08
PA15 PA15 PA15
External Bus Interface (EBI) address and data input / output pin 08.
EBI_AD09
PA0 PA0 PA0
External Bus Interface (EBI) address and data input / output pin 09.
EBI_AD10
PA1 PA1 PA1
External Bus Interface (EBI) address and data input / output pin 10.
EBI_AD11
PA2 PA2 PA2
External Bus Interface (EBI) address and data input / output pin 11.
EBI_AD12
PA3 PA3 PA3
External Bus Interface (EBI) address and data input / output pin 12.
EBI_AD13
PA4 PA4 PA4
External Bus Interface (EBI) address and data input / output pin 13.
silabs.com | Building a more connected world.
Rev. 2.30 | 385
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
EBI_AD14
PA5 PA5 PA5
External Bus Interface (EBI) address and data input / output pin 14.
EBI_AD15
PA6 PA6 PA6
External Bus Interface (EBI) address and data input / output pin 15.
EBI_ALE
PC11 PC11
External Bus Interface (EBI) Address Latch Enable output.
EBI_ARDY
PF2 PF2 PF2
External Bus Interface (EBI) Hardware Ready Control input.
EBI_BL0
PF6 PF6 PF6
External Bus Interface (EBI) Byte Lane/Enable pin 0.
EBI_BL1
PF7 PF7 PF7
External Bus Interface (EBI) Byte Lane/Enable pin 1.
EBI_CS0
PD9 PD9 PD9
External Bus Interface (EBI) Chip Select output 0.
EBI_CS1
PD10 PD10 PD10
External Bus Interface (EBI) Chip Select output 1.
EBI_CS2
PD11 PD11 PD11
External Bus Interface (EBI) Chip Select output 2.
EBI_CS3
PD12 PD12 PD12
External Bus Interface (EBI) Chip Select output 3.
EBI_CSTFT
PA7 PA7 PA7
External Bus Interface (EBI) Chip Select output TFT.
EBI_DCLK
PA8 PA8 PA8
External Bus Interface (EBI) TFT Dot Clock pin.
EBI_DTEN
PA9 PA9 PA9
External Bus Interface (EBI) TFT Data Enable pin.
EBI_HSNC
PA11 PA11 PA11
External Bus Interface (EBI) TFT Horizontal Synchronization pin.
EBI_NANDREn PC3 PC3 PC3
External Bus Interface (EBI) NAND Read Enable output.
EBI_NANDWEn PC5 PC5 PC5
External Bus Interface (EBI) NAND Write Enable output.
EBI_REn
PF5 PF9 PF5
External Bus Interface (EBI) Read Enable output.
EBI_VSNC
PA10 PA10 PA10
External Bus Interface (EBI) TFT Vertical Synchronization pin.
EBI_WEn
PF8
External Bus Interface (EBI) Write Enable output.
ETM_TCLK
PD7 PF8 PC6 PA6
Embedded Trace Module ETM clock .
ETM_TD0
PD6 PF9 PC7 PA2
Embedded Trace Module ETM data 0.
ETM_TD1
PD3
PD3 PA3
Embedded Trace Module ETM data 1.
ETM_TD2
PD4
PD4 PA4
Embedded Trace Module ETM data 2.
ETM_TD3
PD5
PD5 PA5
Embedded Trace Module ETM data 3.
GPIO_EM4WU0 PA0
Pin can be used to wake the system up from EM4
GPIO_EM4WU1 PA6
Pin can be used to wake the system up from EM4
GPIO_EM4WU2 PC9
Pin can be used to wake the system up from EM4
GPIO_EM4WU3 PF1
Pin can be used to wake the system up from EM4
GPIO_EM4WU4 PF2
Pin can be used to wake the system up from EM4
GPIO_EM4WU5 PE13
Pin can be used to wake the system up from EM4
silabs.com | Building a more connected world.
Rev. 2.30 | 386
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
HFXTAL_N
PB14
High Frequency Crystal negative pin. Also used as external optional clock input pin.
HFXTAL_P
PB13
High Frequency Crystal positive pin.
I2C0_SCL
PA1 PD7 PC7
PC1 PF1 PE13 I2C0 Serial Clock Line input / output.
I2C0_SDA
PA0 PD6 PC6
PC0 PF0 PE12 I2C0 Serial Data input / output.
I2C1_SCL
PC5 PB12 PE1
I2C1 Serial Clock Line input / output.
I2C1_SDA
PC4 PB11 PE0
I2C1 Serial Data input / output.
LCD_BCAP_N PA13
LCD voltage booster (optional), boost capacitor, negative pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P.
LCD_BCAP_P PA12
LCD voltage booster (optional), boost capacitor, positive pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P.
LCD voltage booster (optional), boost output. If using the LCD voltage booster, connect a 1 uF capacitor between this pin and VSS.
LCD_BEXT
PA14
An external LCD voltage may also be applied to this pin if the booster is not enabled.
If AVDD is used directly as the LCD supply voltage, this pin may be left unconnected or used as a GPIO.
LCD_COM0
PE4
LCD driver common line number 0.
LCD_COM1
PE5
LCD driver common line number 1.
LCD_COM2
PE6
LCD driver common line number 2.
LCD_COM3
PE7
LCD driver common line number 3.
LCD_SEG0
PF2
LCD segment line 0. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
LCD_SEG3
PF5
LCD segment line 3. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
LCD_SEG4
PE8
LCD segment line 4. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
LCD_SEG5
PE9
LCD segment line 5. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
LCD_SEG6
PE10
LCD segment line 6. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
LCD_SEG7
PE11
LCD segment line 7. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
LCD_SEG8
PE12
LCD segment line 8. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG9
PE13
LCD segment line 9. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG10
PE14
LCD segment line 10. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
silabs.com | Building a more connected world.
Rev. 2.30 | 387
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
LCD_SEG11
PE15
LCD segment line 11. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG12
PA15
LCD segment line 12. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG13
PA0
LCD segment line 13. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG14
PA1
LCD segment line 14. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG15
PA2
LCD segment line 15. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG16
PA3
LCD segment line 16. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG17
PA4
LCD segment line 17. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG18
PA5
LCD segment line 18. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG19
PA6
LCD segment line 19. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG20/ LCD_COM4
PB3
LCD segment line 20. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 4
LCD_SEG21/ LCD_COM5
PB4
LCD segment line 21. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 5
LCD_SEG22/ LCD_COM6
PB5
LCD segment line 22. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 6
LCD_SEG23/ LCD_COM7
PB6
LCD segment line 23. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 7
LCD_SEG24
PF6
LCD segment line 24. Segments 24, 25, 26 and 27 are controlled by SEGEN6.
LCD_SEG25
PF7
LCD segment line 25. Segments 24, 25, 26 and 27 are controlled by SEGEN6.
LCD_SEG26
PF8
LCD segment line 26. Segments 24, 25, 26 and 27 are controlled by SEGEN6.
LCD_SEG27
PF9
LCD segment line 27. Segments 24, 25, 26 and 27 are controlled by SEGEN6.
LCD_SEG28
PD9
LCD segment line 28. Segments 28, 29, 30 and 31 are controlled by SEGEN7.
LCD_SEG29
PD10
LCD segment line 29. Segments 28, 29, 30 and 31 are controlled by SEGEN7.
LCD_SEG30
PD11
LCD segment line 30. Segments 28, 29, 30 and 31 are controlled by SEGEN7.
LCD_SEG31
PD12
LCD segment line 31. Segments 28, 29, 30 and 31 are controlled by SEGEN7.
silabs.com | Building a more connected world.
Rev. 2.30 | 388
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
LCD_SEG32
PB0
LCD segment line 32. Segments 32, 33, 34 and 35 are controlled by SEGEN8.
LCD_SEG33
PB1
LCD segment line 33. Segments 32, 33, 34 and 35 are controlled by SEGEN8.
LCD_SEG34
PB2
LCD segment line 34. Segments 32, 33, 34 and 35 are controlled by SEGEN8.
LCD_SEG35
PA7
LCD segment line 35. Segments 32, 33, 34 and 35 are controlled by SEGEN8.
LCD_SEG36
PA8
LCD segment line 36. Segments 36, 37, 38 and 39 are controlled by SEGEN9.
LCD_SEG37
PA9
LCD segment line 37. Segments 36, 37, 38 and 39 are controlled by SEGEN9.
LCD_SEG38
PA10
LCD segment line 38. Segments 36, 37, 38 and 39 are controlled by SEGEN9.
LCD_SEG39
PA11
LCD segment line 39. Segments 36, 37, 38 and 39 are controlled by SEGEN9.
LES_ALTEX0 PD6
LESENSE alternate exite output 0.
LES_ALTEX1 PD7
LESENSE alternate exite output 1.
LES_ALTEX2 PA3
LESENSE alternate exite output 2.
LES_ALTEX3 PA4
LESENSE alternate exite output 3.
LES_ALTEX4 PA5
LESENSE alternate exite output 4.
LES_ALTEX5 PE11
LESENSE alternate exite output 5.
LES_ALTEX6 PE12
LESENSE alternate exite output 6.
LES_ALTEX7 PE13
LESENSE alternate exite output 7.
LES_CH0
PC0
LESENSE channel 0.
LES_CH1
PC1
LESENSE channel 1.
LES_CH2
PC2
LESENSE channel 2.
LES_CH3
PC3
LESENSE channel 3.
LES_CH4
PC4
LESENSE channel 4.
LES_CH5
PC5
LESENSE channel 5.
LES_CH6
PC6
LESENSE channel 6.
LES_CH7
PC7
LESENSE channel 7.
LES_CH8
PC8
LESENSE channel 8.
LES_CH9
PC9
LESENSE channel 9.
LES_CH10
PC10
LESENSE channel 10.
LES_CH11
PC11
LESENSE channel 11.
LETIM0_OUT0 PD6 PB11 PF0 PC4
Low Energy Timer LETIM0, output channel 0.
LETIM0_OUT1 PD7 PB12 PF1 PC5
Low Energy Timer LETIM0, output channel 1.
LEU0_RX
PD5 PB14 PE15 PF1 PA0
LEUART0 Receive input.
silabs.com | Building a more connected world.
Rev. 2.30 | 389
Alternate
LOCATION
Functionality
0
1
2
3
4
5
LEU0_TX
PD4 PB13 PE14 PF0 PF2
LEU1_RX
PC7 PA6
LEU1_TX
PC6 PA5
LFXTAL_N
PB8
LFXTAL_P
PB7
OPAMP_N0 / DAC0_N0
PC5
OPAMP_N1 / DAC0_N1
PD7
OPAMP_N2
PD3
OPAMP_OUT2 PD5 PD0
OPAMP_P0 / DAC0_P0
PC4
OPAMP_P1 / DAC0_P1
PD6
OPAMP_P2
PD4
PCNT0_S0IN
PE0 PC0 PD6
PCNT0_S1IN
PE1 PC1 PD7
PCNT1_S0IN PC4 PB3
PCNT1_S1IN PC5 PB4
PCNT2_S0IN PD0 PE8
PCNT2_S1IN PD1 PE9
PRS_CH0
PA0
PRS_CH1
PA1
PRS_CH2
PC0 PF5
PRS_CH3
PC1 PE8
TIM0_CC0
PA0 PA0 PF6 PD1 PA0 PF0
TIM0_CC1
PA1 PA1 PF7 PD2 PC0 PF1
TIM0_CC2
PA2 PA2 PF8 PD3 PC1 PF2
TIM0_CDTI0
PA3
PC2
TIM0_CDTI1
PA4
PC3
TIM0_CDTI2 TIM1_CC0
PA5
PF5
PC4 PF5
PE10 PB0 PB7 PD6
silabs.com | Building a more connected world.
EFM32LG Data Sheet
Pin Definitions
6
Description
LEUART0 Transmit output. Also used as receive input in half duplex communication.
LEUART1 Receive input.
LEUART1 Transmit output. Also used as receive input in half duplex communication.
Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin.
Low Frequency Crystal (typically 32.768 kHz) positive pin.
Operational Amplifier 0 external negative input.
Operational Amplifier 1 external negative input. Operational Amplifier 2 external negative input. Operational Amplifier 2 output. Operational Amplifier 0 external positive input.
Operational Amplifier 1 external positive input.
Operational Amplifier 2 external positive input. Pulse Counter PCNT0 input number 0. Pulse Counter PCNT0 input number 1. Pulse Counter PCNT1 input number 0. Pulse Counter PCNT1 input number 1. Pulse Counter PCNT2 input number 0. Pulse Counter PCNT2 input number 1. Peripheral Reflex System PRS, channel 0. Peripheral Reflex System PRS, channel 1. Peripheral Reflex System PRS, channel 2. Peripheral Reflex System PRS, channel 3. Timer 0 Capture Compare input / output channel 0. Timer 0 Capture Compare input / output channel 1. Timer 0 Capture Compare input / output channel 2. Timer 0 Complimentary Deat Time Insertion channel 0. Timer 0 Complimentary Deat Time Insertion channel 1. Timer 0 Complimentary Deat Time Insertion channel 2. Timer 1 Capture Compare input / output channel 0.
Rev. 2.30 | 390
Alternate Functionality TIM1_CC1 TIM1_CC2 TIM2_CC0 TIM2_CC1 TIM2_CC2 TIM3_CC0 TIM3_CC1 TIM3_CC2 U0_RX
U0_TX
U1_RX
U1_TX
US0_CLK US0_CS
LOCATION
0
1
2
3
4
5
PE11 PB1 PB8 PD7
PE12 PB2 PB11
PA8 PA12 PC8
PA9 PA13 PC9
PA10 PA14 PC10
PE14 PE0
PE15 PE1
PA15 PE2
PF7 PE1 PA4
PF6 PE0 PA3
PF11 PB10 PE3
PF10 PB9 PE2
PE12 PE5 PC9 PE13 PE4 PC8
PB13 PB13 PB14 PB14
US0_RX
PE11 PE6 PC10 PE12 PB8 PC1
US0_TX
US1_CLK US1_CS US1_RX
PE10 PE7 PC11 PE13 PB7 PC0
PB7 PD2 PF0 PB8 PD3 PF1 PC1 PD1 PD6
US1_TX
US2_CLK US2_CS US2_RX
PC0 PD0 PD7
PC4 PB5 PC5 PB6 PC3 PB4
EFM32LG Data Sheet
Pin Definitions
6
Description
Timer 1 Capture Compare input / output channel 1.
Timer 1 Capture Compare input / output channel 2.
Timer 2 Capture Compare input / output channel 0.
Timer 2 Capture Compare input / output channel 1.
Timer 2 Capture Compare input / output channel 2.
Timer 3 Capture Compare input / output channel 0.
Timer 3 Capture Compare input / output channel 1.
Timer 3 Capture Compare input / output channel 2.
UART0 Receive input.
UART0 Transmit output. Also used as receive input in half duplex communication.
UART1 Receive input.
UART1 Transmit output. Also used as receive input in half duplex communication.
USART0 clock input / output.
USART0 chip select input / output.
USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output (MISO).
USART0 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input (MOSI).
USART1 clock input / output.
USART1 chip select input / output.
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output (MISO).
USART1 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input (MOSI).
USART2 clock input / output.
USART2 chip select input / output.
USART2 Asynchronous Receive.
USART2 Synchronous mode Master Input / Slave Output (MISO).
silabs.com | Building a more connected world.
Rev. 2.30 | 391
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
US2_TX
PC2 PB3
USART2 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART2 Synchronous mode Master Output / Slave Input (MOSI).
USB_DM
PF10
USB D- pin.
USB_DMPU
PD2
USB D- Pullup control.
USB_DP
PF11
USB D+ pin.
USB_ID
PF12
USB ID pin. Used in OTG mode.
USB_VBUS
USB_V BUS
USB 5 V VBUS input.
USB_VBUSEN PF5
USB 5 V VBUS enable.
USB_VREGI
USB_V REGI
USB Input to internal 3.3 V regulator
USB_VREGO
USB_V REGO
USB Decoupling for internal 3.3 V USB regulator and regulator output
5.20.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG980 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.60. GPIO Pinout
Port
Port A Port B Port C Port D Port E Port F
Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 15 14 13 12 11 10 PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 -- PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 -- -- -- -- PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 -- -- -- PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 -- -- -- PF12 PF11 PF10 PF9 PF8 PF7 PF6 PF5 -- -- PF2 PF1 PF0
5.20.4 Opamp Pinout Overview
The specific opamp terminals available in EFM32LG980 is shown in the following figure.
PC4
+ OUT0ALT
PC5
OPA0 -
OUT0
PD4
+
PD3
OPA2 -
OUT2
PD6
+ OUT1ALT
PD7
OPA1 -
OUT1
PB11 PB12 PC0 PC1 PC2 PC3
PD0 PD1 PD5
Figure 5.40. Opamp Pinout
silabs.com | Building a more connected world.
Rev. 2.30 | 392
5.21 EFM32LG990 (BGA112)
EFM32LG Data Sheet
Pin Definitions
5.21.1 Pinout
The EFM32LG990 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question.
Figure 5.41. EFM32LG990 Pinout (top view, not to scale) Table 5.61. Device Pinout
BGA112 Pin# and Name
Pin # Pin Name
A1
PE15
A2
PE14
A3
PE12
Analog LCD_SEG11 LCD_SEG10
LCD_SEG8
Pin Alternate Functionality / Description
EBI EBI_AD07 #0/1/2 EBI_AD06 #0/1/2
EBI_AD04 #0/1/2
Timers TIM3_CC1 #0 TIM3_CC0 #0
TIM1_CC2 #1
Communication
LEU0_RX #2
LEU0_TX #2
US0_RX #3 US0_CLK #0 I2C0_SDA #6
Other
CMU_CLK1 #2 LES_ALTEX6 #0
silabs.com | Building a more connected world.
Rev. 2.30 | 393
EFM32LG Data Sheet
Pin Definitions
BGA112 Pin# and Name
Pin # Pin Name
A4
PE9
A5
PD10
A6
PF7
A7
PF5
A8
PF12
A9
PE4
A10
PF10
A11
PF11
B1
PA15
B2
PE13
Analog LCD_SEG5 LCD_SEG29 LCD_SEG25 LCD_SEG3
LCD_COM0
LCD_SEG12 LCD_SEG9
Pin Alternate Functionality / Description
EBI EBI_AD01 #0/1/2 EBI_CS1 #0/1/2 EBI_BL1 #0/1/2
EBI_REn #0/2
EBI_A11 #0/1/2
EBI_AD08 #0/1/2 EBI_AD05 #0/1/2
Timers PCNT2_S1IN #1
Communication
TIM0_CC1 #2
U0_RX #0
TIM0_CDTI2 #2/5 USB_VBUSEN #0
USB_ID
US0_CS #1
U1_TX #1 USB_DM
U1_RX #1 USB_DP
TIM3_CC2 #0
US0_TX #3 US0_CS #0 I2C0_SCL #6
B3
PE11
LCD_SEG7
EBI_AD03 #0/1/2
TIM1_CC1 #1
US0_RX #0
B4
PE8
LCD_SEG4
EBI_AD00 #0/1/2 PCNT2_S0IN #1
B5
PD11
LCD_SEG30
EBI_CS2 #0/1/2
B6
PF8
LCD_SEG26
EBI_WEn #1
TIM0_CC2 #2
B7
PF6
LCD_SEG24
EBI_BL0 #0/1/2
TIM0_CC0 #2
B8 USB_VBUS USB 5.0 V VBUS input.
B9
PE5
LCD_COM1
EBI_A12 #0/1/2
B10 USB_VREGI Input to internal 3.3V USB regulator
B11 USB_VREGO Output and decoupling for internal 3.3V USB regulator
U0_TX #0 US0_CLK #1
C1
PA1
LCD_SEG14
EBI_AD10 #0/1/2 TIM0_CC1 #0/1
I2C0_SCL #0
C2
PA0
LCD_SEG13
EBI_AD09 #0/1/2 TIM0_CC0 #0/1/4
LEU0_RX #4 I2C0_SDA #0
C3
PE10
LCD_SEG6
EBI_AD02 #0/1/2
TIM1_CC0 #1
US0_TX #0
C4
PD13
C5
PD12
LCD_SEG31
EBI_CS3 #0/1/2
C6
PF9
LCD_SEG27
EBI_REn #1
C7
VSS
Ground.
C8
PF2
LCD_SEG0
EBI_ARDY #0/1/2
TIM0_CC2 #5
LEU0_TX #4
C9
PE6
C10
PC10
C11
PC11
D1
PA3
LCD_COM2 ACMP1_CH2 ACMP1_CH3
LCD_SEG16
EBI_A13 #0/1/2 EBI_A10 #1/2 EBI_ALE #1/2
EBI_AD12 #0/1/2
TIM2_CC2 #2 TIM0_CDTI0 #0
US0_RX #1 US0_RX #2 US0_TX #2
U0_TX #2
Other
PRS_CH2 #1
LES_ALTEX7 #0 ACMP0_O #0
GPIO_EM4WU5 LES_ALTEX5 #0
BOOT_RX PRS_CH3 #1
ETM_TCLK #1
CMU_CLK1 #0 PRS_CH1 #0 PRS_CH0 #0 GPIO_EM4WU0
BOOT_TX ETM_TD1 #1
ETM_TD0 #1
ACMP1_O #0 DBG_SWO #0 GPIO_EM4WU4
LES_CH10 #0 LES_CH11 #0 LES_ALTEX2 #0 ETM_TD1 #3
silabs.com | Building a more connected world.
Rev. 2.30 | 394
EFM32LG Data Sheet
Pin Definitions
BGA112 Pin# and Name
Pin # Pin Name
D2
PA2
D3
PB15
D4
VSS
D5
IOVDD_6
D6
PD9
D7
IOVDD_5
D8
PF1
D9
PE7
D10
PC8
D11
PC9
E1
PA6
E2
PA5
E3
PA4
E4
PB0
E8
PF0
E9
PE0
E10
PE1
E11
PE3
F1
PB1
F2
PB2
F3
PB3
F4
PB4
F8 VDD_DREG
F9 VSS_DREG
F10
PE2
F11 DECOUPLE
G1
PB5
Pin Alternate Functionality / Description
Analog
EBI
Timers
Communication
Other
LCD_SEG15
EBI_AD11 #0/1/2 TIM0_CC2 #0/1
CMU_CLK0 #0 ETM_TD0 #3
ETM_TD2 #1
Ground.
Digital IO power supply 6.
LCD_SEG28
EBI_CS0 #0/1/2
Digital IO power supply 5.
TIM0_CC1 #5 LETIM0_OUT1 #2
US1_CS #2 LEU0_RX #3 I2C0_SCL #5
DBG_SWDIO #0/1/2/3
GPIO_EM4WU3
LCD_COM3
EBI_A14 #0/1/2
US0_TX #1
ACMP1_CH0
EBI_A15 #0/1/2
TIM2_CC0 #2
US0_CS #2
LES_CH8 #0
ACMP1_CH1
EBI_A09 #1/2
TIM2_CC1 #2
US0_CLK #2
LES_CH9 #0 GPIO_EM4WU2
LCD_SEG19
EBI_AD15 #0/1/2
LEU1_RX #1
ETM_TCLK #3 GPIO_EM4WU1
LCD_SEG18
EBI_AD14 #0/1/2 TIM0_CDTI2 #0
LEU1_TX #1
LES_ALTEX4 #0 ETM_TD3 #3
LCD_SEG17
EBI_AD13 #0/1/2 TIM0_CDTI1 #0
U0_RX #2
LES_ALTEX3 #0 ETM_TD2 #3
LCD_SEG32
EBI_A16 #0/1/2
TIM1_CC0 #2
TIM0_CC0 #5 LETIM0_OUT0 #2
US1_CLK #2 LEU0_TX #3 I2C0_SDA #5
DBG_SWCLK #0/1/2/3
EBI_A07 #0/1/2
TIM3_CC0 #1 PCNT0_S0IN #1
U0_TX #1 I2C1_SDA #2
EBI_A08 #0/1/2
TIM3_CC1 #1 PCNT0_S1IN #1
U0_RX #1 I2C1_SCL #2
BU_STAT
EBI_A10 #0
U1_RX #3
ACMP1_O #1
LCD_SEG33
EBI_A17 #0/1/2
TIM1_CC1 #2
LCD_SEG34
EBI_A18 #0/1/2
TIM1_CC2 #2
LCD_SEG20/ LCD_COM4
EBI_A19 #0/1/2
PCNT1_S0IN #1
US2_TX #1
LCD_SEG21/ LCD_COM5
EBI_A20 #0/1/2
PCNT1_S1IN #1
US2_RX #1
Power supply for on-chip voltage regulator.
Ground for on-chip voltage regulator.
BU_VOUT
EBI_A09 #0
TIM3_CC2 #1
U1_TX #3
ACMP0_O #1
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin.
LCD_SEG22/ LCD_COM6
EBI_A21 #0/1/2
US2_CLK #1
silabs.com | Building a more connected world.
Rev. 2.30 | 395
EFM32LG Data Sheet
Pin Definitions
BGA112 Pin# and Name
Pin # Pin Name
G2
PB6
G3
VSS
G4
IOVDD_0
G8
IOVDD_4
G9
VSS
G10
PC6
G11
PC7
H1
PC0
H2
PC2
H3
PD14
H4
PA7
H5
PA8
H6
VSS
H7
IOVDD_3
H8
PD8
H9
PD5
H10
PD6
Pin Alternate Functionality / Description
Analog
EBI
LCD_SEG23/ LCD_COM7
EBI_A22 #0/1/2
Ground.
Digital IO power supply 0.
Digital IO power supply 4.
Ground.
ACMP0_CH6
EBI_A05 #0/1/2
Timers
ACMP0_CH7
EBI_A06 #0/1/2
ACMP0_CH0 DAC0_OUT0ALT
#0/ OPAMP_OUT0ALT
ACMP0_CH2 DAC0_OUT0ALT
#2/ OPAMP_OUT0ALT
EBI_A23 #0/1/2 EBI_A25 #0/1/2
TIM0_CC1 #4 PCNT0_S0IN #2
TIM0_CDTI0 #4
LCD_SEG35
EBI_CSTFT #0/1/2
LCD_SEG36
EBI_DCLK #0/1/2
Ground.
Digital IO power supply 3.
BU_VIN
ADC0_CH5 OPAMP_OUT2 #0
ADC0_CH6 / DAC0_P1 / OPAMP_P1
TIM2_CC0 #0
TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3
Communication US2_CS #1
LEU1_TX #0 I2C0_SDA #2 LEU1_RX #0 I2C0_SCL #2 US0_TX #5 US1_TX #0 I2C0_SDA #4
US2_TX #0 I2C0_SDA #3
LEU0_RX #0 US1_RX #2 I2C0_SDA #1
H11
PD7
ADC0_CH7 / DAC0_N1 / OPAMP_N1
TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3
US1_TX #2 I2C0_SCL #1
J1
PC1
ACMP0_CH1 DAC0_OUT0ALT
#1/ OPAMP_OUT0ALT
EBI_A24 #0/1/2
TIM0_CC2 #4 PCNT0_S1IN #2
US0_RX #5 US1_RX #0 I2C0_SCL #4
ACMP0_CH3
J2
PC3
DAC0_OUT0ALT #3/
EBI_NANDREn #0/1/2
TIM0_CDTI1 #4
US2_RX #0
OPAMP_OUT0ALT
J3
PD15
I2C0_SCL #3
J4
PA12
LCD_BCAP_P
EBI_A00 #0/1/2
TIM2_CC0 #1
J5
PA9
LCD_SEG37
EBI_DTEN #0/1/2
TIM2_CC1 #0
Other
LES_CH6 #0 ETM_TCLK #2 LES_CH7 #0 ETM_TD0 #2 LES_CH0 #0 PRS_CH2 #0
LES_CH2 #0
CMU_CLK1 #1 ETM_TD3 #0/2 LES_ALTEX0 #0 ACMP0_O #2 ETM_TD0 #0 CMU_CLK0 #2 LES_ALTEX1 #0 ACMP1_O #2 ETM_TCLK #0 LES_CH1 #0 PRS_CH3 #0
LES_CH3 #0
silabs.com | Building a more connected world.
Rev. 2.30 | 396
EFM32LG Data Sheet
Pin Definitions
BGA112 Pin# and Name
Pin # Pin Name
J6
PA10
J7
PB9
J8
PB10
J9
PD2
J10
PD3
J11
PD4
K1
PB7
K2
PC4
K3
PA13
K4
VSS
K5
PA11
K6
RESETn
K7
AVSS_1
K8
AVDD_2
K9
AVDD_1
K10
AVSS_0
K11
PD1
L1
PB8
L2
PC5
L3
PA14
L4
IOVDD_1
L5
PB11
L6
PB12
L7
AVSS_2
L8
PB13
Pin Alternate Functionality / Description
Analog
EBI
Timers
Communication
Other
LCD_SEG38
EBI_VSNC #0/1/2
TIM2_CC2 #0
EBI_A03 #0/1/2
U1_TX #2
EBI_A04 #0/1/2
U1_RX #2
ADC0_CH2
EBI_A27 #0/1/2
TIM0_CC1 #3
USB_DMPU #0 US1_CLK #1
DBG_SWO #3
ADC0_CH3 OPAMP_N2
TIM0_CC2 #3
US1_CS #1
ETM_TD1 #0/2
ADC0_CH4 OPAMP_P2
LEU0_TX #0
ETM_TD2 #0/2
LFXTAL_P
TIM1_CC0 #3
US0_TX #4 US1_CLK #0
ACMP0_CH4 / DAC0_P0 / OPAMP_P0
EBI_A26 #0/1/2
TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0
US2_CLK #0 I2C1_SDA #0
LES_CH4 #0
LCD_BCAP_N
EBI_A01 #0/1/2
TIM2_CC1 #1
Ground.
LCD_SEG39
EBI_HSNC #0/1/2
Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released.
Analog ground 1.
Analog power supply 2.
Analog power supply 1.
Analog ground 0.
ADC0_CH1 DAC0_OUT1ALT
#4/ OPAMP_OUT1ALT
TIM0_CC0 #3 PCNT2_S1IN #0
US1_RX #1
DBG_SWO #2
LFXTAL_N
TIM1_CC1 #3
US0_RX #4 US1_CS #0
ACMP0_CH5 / DAC0_N0 / OPAMP_N0
EBI_NANDWEn #0/1/2
LETIM0_OUT1 #3 PCNT1_S1IN #0
US2_CS #0 I2C1_SCL #0
LES_CH5 #0
LCD_BEXT
EBI_A02 #0/1/2
TIM2_CC2 #1
Digital IO power supply 1.
DAC0_OUT0 / OPAMP_OUT0
TIM1_CC2 #3 LETIM0_OUT0 #1
I2C1_SDA #1
DAC0_OUT1 / OPAMP_OUT1
LETIM0_OUT1 #1
I2C1_SCL #1
Analog ground 2.
HFXTAL_P
US0_CLK #4/5 LEU0_TX #1
silabs.com | Building a more connected world.
Rev. 2.30 | 397
BGA112 Pin# and Name
Pin # Pin Name
Analog
L9
PB14
HFXTAL_N
L10
AVDD_0 Analog power supply 0.
ADC0_CH0
DAC0_OUT0ALT
L11
PD0
#4/
OPAMP_OUT0ALT
OPAMP_OUT2 #1
EFM32LG Data Sheet
Pin Definitions
Pin Alternate Functionality / Description
EBI
Timers
Communication
US0_CS #4/5 LEU0_RX #1
Other
PCNT2_S0IN #0
US1_TX #1
silabs.com | Building a more connected world.
Rev. 2.30 | 398
EFM32LG Data Sheet
Pin Definitions
5.21.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0.
Table 5.62. Alternate Functionality Overview
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
ACMP0_CH0 PC0
Analog comparator ACMP0, channel 0.
ACMP0_CH1 PC1
Analog comparator ACMP0, channel 1.
ACMP0_CH2 PC2
Analog comparator ACMP0, channel 2.
ACMP0_CH3 PC3
Analog comparator ACMP0, channel 3.
ACMP0_CH4 PC4
Analog comparator ACMP0, channel 4.
ACMP0_CH5 PC5
Analog comparator ACMP0, channel 5.
ACMP0_CH6 PC6
Analog comparator ACMP0, channel 6.
ACMP0_CH7 PC7
Analog comparator ACMP0, channel 7.
ACMP0_O
PE13 PE2 PD6
Analog comparator ACMP0, digital output.
ACMP1_CH0 PC8
Analog comparator ACMP1, channel 0.
ACMP1_CH1 PC9
Analog comparator ACMP1, channel 1.
ACMP1_CH2 PC10
Analog comparator ACMP1, channel 2.
ACMP1_CH3 PC11
Analog comparator ACMP1, channel 3.
ACMP1_O
PF2 PE3 PD7
Analog comparator ACMP1, digital output.
ADC0_CH0
PD0
Analog to digital converter ADC0, input channel number 0.
ADC0_CH1
PD1
Analog to digital converter ADC0, input channel number 1.
ADC0_CH2
PD2
Analog to digital converter ADC0, input channel number 2.
ADC0_CH3
PD3
Analog to digital converter ADC0, input channel number 3.
ADC0_CH4
PD4
Analog to digital converter ADC0, input channel number 4.
ADC0_CH5
PD5
Analog to digital converter ADC0, input channel number 5.
ADC0_CH6
PD6
Analog to digital converter ADC0, input channel number 6.
ADC0_CH7
PD7
Analog to digital converter ADC0, input channel number 7.
BOOT_RX
PE11
Bootloader RX.
BOOT_TX
PE10
Bootloader TX.
silabs.com | Building a more connected world.
Rev. 2.30 | 399
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
BU_STAT
PE3
Backup Power Domain status, whether or not the system is in backup mode
BU_VIN
PD8
Battery input for Backup Power Domain
BU_VOUT
PE2
Power output for Backup Power Domain
CMU_CLK0
PA2
PD7
Clock Management Unit, clock output number 0.
CMU_CLK1
PA1 PD8 PE12
Clock Management Unit, clock output number 1.
DAC0_OUT0 / OPAMP_OUT0
PB11
Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0.
DAC0_OUT0ALT / OPAMP_OUT0A PC0 PC1 PC2 PC3 PD0 LT
Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0.
DAC0_OUT1 / OPAMP_OUT1
PB12
Digital to Analog Converter DAC0_OUT1 /OPAMP output channel number 1.
DAC0_OUT1ALT / OPAMP_OUT1A LT
PD1
Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1.
DBG_SWCLK PF0 PF0 PF0 PF0
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, and has a built-in pull down.
DBG_SWDIO PF1 PF1 PF1 PF1
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and has a built-in pull up.
DBG_SWO
PF2
PD1 PD2
Debug-interface Serial Wire viewer Output.
Note that this function is not enabled after reset, and must be enabled by software to be used.
EBI_A00
PA12 PA12 PA12
External Bus Interface (EBI) address output pin 00.
EBI_A01
PA13 PA13 PA13
External Bus Interface (EBI) address output pin 01.
EBI_A02
PA14 PA14 PA14
External Bus Interface (EBI) address output pin 02.
EBI_A03
PB9 PB9 PB9
External Bus Interface (EBI) address output pin 03.
EBI_A04
PB10 PB10 PB10
External Bus Interface (EBI) address output pin 04.
EBI_A05
PC6 PC6 PC6
External Bus Interface (EBI) address output pin 05.
EBI_A06
PC7 PC7 PC7
External Bus Interface (EBI) address output pin 06.
EBI_A07
PE0 PE0 PE0
External Bus Interface (EBI) address output pin 07.
EBI_A08
PE1 PE1 PE1
External Bus Interface (EBI) address output pin 08.
EBI_A09
PE2 PC9 PC9
External Bus Interface (EBI) address output pin 09.
EBI_A10
PE3 PC10 PC10
External Bus Interface (EBI) address output pin 10.
EBI_A11
PE4 PE4 PE4
External Bus Interface (EBI) address output pin 11.
EBI_A12
PE5 PE5 PE5
External Bus Interface (EBI) address output pin 12.
EBI_A13
PE6 PE6 PE6
External Bus Interface (EBI) address output pin 13.
EBI_A14
PE7 PE7 PE7
External Bus Interface (EBI) address output pin 14.
silabs.com | Building a more connected world.
Rev. 2.30 | 400
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
EBI_A15
PC8 PC8 PC8
External Bus Interface (EBI) address output pin 15.
EBI_A16
PB0 PB0 PB0
External Bus Interface (EBI) address output pin 16.
EBI_A17
PB1 PB1 PB1
External Bus Interface (EBI) address output pin 17.
EBI_A18
PB2 PB2 PB2
External Bus Interface (EBI) address output pin 18.
EBI_A19
PB3 PB3 PB3
External Bus Interface (EBI) address output pin 19.
EBI_A20
PB4 PB4 PB4
External Bus Interface (EBI) address output pin 20.
EBI_A21
PB5 PB5 PB5
External Bus Interface (EBI) address output pin 21.
EBI_A22
PB6 PB6 PB6
External Bus Interface (EBI) address output pin 22.
EBI_A23
PC0 PC0 PC0
External Bus Interface (EBI) address output pin 23.
EBI_A24
PC1 PC1 PC1
External Bus Interface (EBI) address output pin 24.
EBI_A25
PC2 PC2 PC2
External Bus Interface (EBI) address output pin 25.
EBI_A26
PC4 PC4 PC4
External Bus Interface (EBI) address output pin 26.
EBI_A27
PD2 PD2 PD2
External Bus Interface (EBI) address output pin 27.
EBI_AD00
PE8 PE8 PE8
External Bus Interface (EBI) address and data input / output pin 00.
EBI_AD01
PE9 PE9 PE9
External Bus Interface (EBI) address and data input / output pin 01.
EBI_AD02
PE10 PE10 PE10
External Bus Interface (EBI) address and data input / output pin 02.
EBI_AD03
PE11 PE11 PE11
External Bus Interface (EBI) address and data input / output pin 03.
EBI_AD04
PE12 PE12 PE12
External Bus Interface (EBI) address and data input / output pin 04.
EBI_AD05
PE13 PE13 PE13
External Bus Interface (EBI) address and data input / output pin 05.
EBI_AD06
PE14 PE14 PE14
External Bus Interface (EBI) address and data input / output pin 06.
EBI_AD07
PE15 PE15 PE15
External Bus Interface (EBI) address and data input / output pin 07.
EBI_AD08
PA15 PA15 PA15
External Bus Interface (EBI) address and data input / output pin 08.
EBI_AD09
PA0 PA0 PA0
External Bus Interface (EBI) address and data input / output pin 09.
EBI_AD10
PA1 PA1 PA1
External Bus Interface (EBI) address and data input / output pin 10.
EBI_AD11
PA2 PA2 PA2
External Bus Interface (EBI) address and data input / output pin 11.
EBI_AD12
PA3 PA3 PA3
External Bus Interface (EBI) address and data input / output pin 12.
EBI_AD13
PA4 PA4 PA4
External Bus Interface (EBI) address and data input / output pin 13.
silabs.com | Building a more connected world.
Rev. 2.30 | 401
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
EBI_AD14
PA5 PA5 PA5
External Bus Interface (EBI) address and data input / output pin 14.
EBI_AD15
PA6 PA6 PA6
External Bus Interface (EBI) address and data input / output pin 15.
EBI_ALE
PC11 PC11
External Bus Interface (EBI) Address Latch Enable output.
EBI_ARDY
PF2 PF2 PF2
External Bus Interface (EBI) Hardware Ready Control input.
EBI_BL0
PF6 PF6 PF6
External Bus Interface (EBI) Byte Lane/Enable pin 0.
EBI_BL1
PF7 PF7 PF7
External Bus Interface (EBI) Byte Lane/Enable pin 1.
EBI_CS0
PD9 PD9 PD9
External Bus Interface (EBI) Chip Select output 0.
EBI_CS1
PD10 PD10 PD10
External Bus Interface (EBI) Chip Select output 1.
EBI_CS2
PD11 PD11 PD11
External Bus Interface (EBI) Chip Select output 2.
EBI_CS3
PD12 PD12 PD12
External Bus Interface (EBI) Chip Select output 3.
EBI_CSTFT
PA7 PA7 PA7
External Bus Interface (EBI) Chip Select output TFT.
EBI_DCLK
PA8 PA8 PA8
External Bus Interface (EBI) TFT Dot Clock pin.
EBI_DTEN
PA9 PA9 PA9
External Bus Interface (EBI) TFT Data Enable pin.
EBI_HSNC
PA11 PA11 PA11
External Bus Interface (EBI) TFT Horizontal Synchronization pin.
EBI_NANDREn PC3 PC3 PC3
External Bus Interface (EBI) NAND Read Enable output.
EBI_NANDWEn PC5 PC5 PC5
External Bus Interface (EBI) NAND Write Enable output.
EBI_REn
PF5 PF9 PF5
External Bus Interface (EBI) Read Enable output.
EBI_VSNC
PA10 PA10 PA10
External Bus Interface (EBI) TFT Vertical Synchronization pin.
EBI_WEn
PF8
External Bus Interface (EBI) Write Enable output.
ETM_TCLK
PD7 PF8 PC6 PA6
Embedded Trace Module ETM clock .
ETM_TD0
PD6 PF9 PC7 PA2
Embedded Trace Module ETM data 0.
ETM_TD1
PD3 PD13 PD3 PA3
Embedded Trace Module ETM data 1.
ETM_TD2
PD4 PB15 PD4 PA4
Embedded Trace Module ETM data 2.
ETM_TD3
PD5
PD5 PA5
Embedded Trace Module ETM data 3.
GPIO_EM4WU0 PA0
Pin can be used to wake the system up from EM4
GPIO_EM4WU1 PA6
Pin can be used to wake the system up from EM4
GPIO_EM4WU2 PC9
Pin can be used to wake the system up from EM4
GPIO_EM4WU3 PF1
Pin can be used to wake the system up from EM4
GPIO_EM4WU4 PF2
Pin can be used to wake the system up from EM4
GPIO_EM4WU5 PE13
Pin can be used to wake the system up from EM4
silabs.com | Building a more connected world.
Rev. 2.30 | 402
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
HFXTAL_N
PB14
High Frequency Crystal negative pin. Also used as external optional clock input pin.
HFXTAL_P
PB13
High Frequency Crystal positive pin.
I2C0_SCL
PA1 PD7 PC7 PD15 PC1 PF1 PE13 I2C0 Serial Clock Line input / output.
I2C0_SDA
PA0 PD6 PC6 PD14 PC0 PF0 PE12 I2C0 Serial Data input / output.
I2C1_SCL
PC5 PB12 PE1
I2C1 Serial Clock Line input / output.
I2C1_SDA
PC4 PB11 PE0
I2C1 Serial Data input / output.
LCD_BCAP_N PA13
LCD voltage booster (optional), boost capacitor, negative pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P.
LCD_BCAP_P PA12
LCD voltage booster (optional), boost capacitor, positive pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P.
LCD voltage booster (optional), boost output. If using the LCD voltage booster, connect a 1 uF capacitor between this pin and VSS.
LCD_BEXT
PA14
An external LCD voltage may also be applied to this pin if the booster is not enabled.
If AVDD is used directly as the LCD supply voltage, this pin may be left unconnected or used as a GPIO.
LCD_COM0
PE4
LCD driver common line number 0.
LCD_COM1
PE5
LCD driver common line number 1.
LCD_COM2
PE6
LCD driver common line number 2.
LCD_COM3
PE7
LCD driver common line number 3.
LCD_SEG0
PF2
LCD segment line 0. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
LCD_SEG3
PF5
LCD segment line 3. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
LCD_SEG4
PE8
LCD segment line 4. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
LCD_SEG5
PE9
LCD segment line 5. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
LCD_SEG6
PE10
LCD segment line 6. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
LCD_SEG7
PE11
LCD segment line 7. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
LCD_SEG8
PE12
LCD segment line 8. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG9
PE13
LCD segment line 9. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG10
PE14
LCD segment line 10. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
silabs.com | Building a more connected world.
Rev. 2.30 | 403
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
LCD_SEG11
PE15
LCD segment line 11. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG12
PA15
LCD segment line 12. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG13
PA0
LCD segment line 13. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG14
PA1
LCD segment line 14. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG15
PA2
LCD segment line 15. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG16
PA3
LCD segment line 16. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG17
PA4
LCD segment line 17. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG18
PA5
LCD segment line 18. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG19
PA6
LCD segment line 19. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG20/ LCD_COM4
PB3
LCD segment line 20. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 4
LCD_SEG21/ LCD_COM5
PB4
LCD segment line 21. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 5
LCD_SEG22/ LCD_COM6
PB5
LCD segment line 22. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 6
LCD_SEG23/ LCD_COM7
PB6
LCD segment line 23. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 7
LCD_SEG24
PF6
LCD segment line 24. Segments 24, 25, 26 and 27 are controlled by SEGEN6.
LCD_SEG25
PF7
LCD segment line 25. Segments 24, 25, 26 and 27 are controlled by SEGEN6.
LCD_SEG26
PF8
LCD segment line 26. Segments 24, 25, 26 and 27 are controlled by SEGEN6.
LCD_SEG27
PF9
LCD segment line 27. Segments 24, 25, 26 and 27 are controlled by SEGEN6.
LCD_SEG28
PD9
LCD segment line 28. Segments 28, 29, 30 and 31 are controlled by SEGEN7.
LCD_SEG29
PD10
LCD segment line 29. Segments 28, 29, 30 and 31 are controlled by SEGEN7.
LCD_SEG30
PD11
LCD segment line 30. Segments 28, 29, 30 and 31 are controlled by SEGEN7.
LCD_SEG31
PD12
LCD segment line 31. Segments 28, 29, 30 and 31 are controlled by SEGEN7.
silabs.com | Building a more connected world.
Rev. 2.30 | 404
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
LCD_SEG32
PB0
LCD segment line 32. Segments 32, 33, 34 and 35 are controlled by SEGEN8.
LCD_SEG33
PB1
LCD segment line 33. Segments 32, 33, 34 and 35 are controlled by SEGEN8.
LCD_SEG34
PB2
LCD segment line 34. Segments 32, 33, 34 and 35 are controlled by SEGEN8.
LCD_SEG35
PA7
LCD segment line 35. Segments 32, 33, 34 and 35 are controlled by SEGEN8.
LCD_SEG36
PA8
LCD segment line 36. Segments 36, 37, 38 and 39 are controlled by SEGEN9.
LCD_SEG37
PA9
LCD segment line 37. Segments 36, 37, 38 and 39 are controlled by SEGEN9.
LCD_SEG38
PA10
LCD segment line 38. Segments 36, 37, 38 and 39 are controlled by SEGEN9.
LCD_SEG39
PA11
LCD segment line 39. Segments 36, 37, 38 and 39 are controlled by SEGEN9.
LES_ALTEX0 PD6
LESENSE alternate exite output 0.
LES_ALTEX1 PD7
LESENSE alternate exite output 1.
LES_ALTEX2 PA3
LESENSE alternate exite output 2.
LES_ALTEX3 PA4
LESENSE alternate exite output 3.
LES_ALTEX4 PA5
LESENSE alternate exite output 4.
LES_ALTEX5 PE11
LESENSE alternate exite output 5.
LES_ALTEX6 PE12
LESENSE alternate exite output 6.
LES_ALTEX7 PE13
LESENSE alternate exite output 7.
LES_CH0
PC0
LESENSE channel 0.
LES_CH1
PC1
LESENSE channel 1.
LES_CH2
PC2
LESENSE channel 2.
LES_CH3
PC3
LESENSE channel 3.
LES_CH4
PC4
LESENSE channel 4.
LES_CH5
PC5
LESENSE channel 5.
LES_CH6
PC6
LESENSE channel 6.
LES_CH7
PC7
LESENSE channel 7.
LES_CH8
PC8
LESENSE channel 8.
LES_CH9
PC9
LESENSE channel 9.
LES_CH10
PC10
LESENSE channel 10.
LES_CH11
PC11
LESENSE channel 11.
LETIM0_OUT0 PD6 PB11 PF0 PC4
Low Energy Timer LETIM0, output channel 0.
LETIM0_OUT1 PD7 PB12 PF1 PC5
Low Energy Timer LETIM0, output channel 1.
LEU0_RX
PD5 PB14 PE15 PF1 PA0
LEUART0 Receive input.
silabs.com | Building a more connected world.
Rev. 2.30 | 405
Alternate
LOCATION
Functionality
0
1
2
3
4
5
LEU0_TX
PD4 PB13 PE14 PF0 PF2
LEU1_RX
PC7 PA6
LEU1_TX
PC6 PA5
LFXTAL_N
PB8
LFXTAL_P
PB7
OPAMP_N0 / DAC0_N0
PC5
OPAMP_N1 / DAC0_N1
PD7
OPAMP_N2
PD3
OPAMP_OUT2 PD5 PD0
OPAMP_P0 / DAC0_P0
PC4
OPAMP_P1 / DAC0_P1
PD6
OPAMP_P2
PD4
PCNT0_S0IN
PE0 PC0 PD6
PCNT0_S1IN
PE1 PC1 PD7
PCNT1_S0IN PC4 PB3
PCNT1_S1IN PC5 PB4
PCNT2_S0IN PD0 PE8
PCNT2_S1IN PD1 PE9
PRS_CH0
PA0
PRS_CH1
PA1
PRS_CH2
PC0 PF5
PRS_CH3
PC1 PE8
TIM0_CC0
PA0 PA0 PF6 PD1 PA0 PF0
TIM0_CC1
PA1 PA1 PF7 PD2 PC0 PF1
TIM0_CC2
PA2 PA2 PF8 PD3 PC1 PF2
TIM0_CDTI0
PA3
PC2
TIM0_CDTI1
PA4
PC3
TIM0_CDTI2 TIM1_CC0
PA5
PF5
PC4 PF5
PE10 PB0 PB7 PD6
silabs.com | Building a more connected world.
EFM32LG Data Sheet
Pin Definitions
6
Description
LEUART0 Transmit output. Also used as receive input in half duplex communication.
LEUART1 Receive input.
LEUART1 Transmit output. Also used as receive input in half duplex communication.
Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin.
Low Frequency Crystal (typically 32.768 kHz) positive pin.
Operational Amplifier 0 external negative input.
Operational Amplifier 1 external negative input. Operational Amplifier 2 external negative input. Operational Amplifier 2 output. Operational Amplifier 0 external positive input.
Operational Amplifier 1 external positive input.
Operational Amplifier 2 external positive input. Pulse Counter PCNT0 input number 0. Pulse Counter PCNT0 input number 1. Pulse Counter PCNT1 input number 0. Pulse Counter PCNT1 input number 1. Pulse Counter PCNT2 input number 0. Pulse Counter PCNT2 input number 1. Peripheral Reflex System PRS, channel 0. Peripheral Reflex System PRS, channel 1. Peripheral Reflex System PRS, channel 2. Peripheral Reflex System PRS, channel 3. Timer 0 Capture Compare input / output channel 0. Timer 0 Capture Compare input / output channel 1. Timer 0 Capture Compare input / output channel 2. Timer 0 Complimentary Deat Time Insertion channel 0. Timer 0 Complimentary Deat Time Insertion channel 1. Timer 0 Complimentary Deat Time Insertion channel 2. Timer 1 Capture Compare input / output channel 0.
Rev. 2.30 | 406
Alternate Functionality TIM1_CC1 TIM1_CC2 TIM2_CC0 TIM2_CC1 TIM2_CC2 TIM3_CC0 TIM3_CC1 TIM3_CC2 U0_RX
U0_TX
U1_RX
U1_TX
US0_CLK US0_CS
LOCATION
0
1
2
3
4
5
PE11 PB1 PB8 PD7
PE12 PB2 PB11
PA8 PA12 PC8
PA9 PA13 PC9
PA10 PA14 PC10
PE14 PE0
PE15 PE1
PA15 PE2
PF7 PE1 PA4
PF6 PE0 PA3
PF11 PB10 PE3
PF10 PB9 PE2
PE12 PE5 PC9 PE13 PE4 PC8
PB13 PB13 PB14 PB14
US0_RX
PE11 PE6 PC10 PE12 PB8 PC1
US0_TX
US1_CLK US1_CS US1_RX
PE10 PE7 PC11 PE13 PB7 PC0
PB7 PD2 PF0 PB8 PD3 PF1 PC1 PD1 PD6
US1_TX
US2_CLK US2_CS US2_RX
PC0 PD0 PD7
PC4 PB5 PC5 PB6 PC3 PB4
EFM32LG Data Sheet
Pin Definitions
6
Description
Timer 1 Capture Compare input / output channel 1.
Timer 1 Capture Compare input / output channel 2.
Timer 2 Capture Compare input / output channel 0.
Timer 2 Capture Compare input / output channel 1.
Timer 2 Capture Compare input / output channel 2.
Timer 3 Capture Compare input / output channel 0.
Timer 3 Capture Compare input / output channel 1.
Timer 3 Capture Compare input / output channel 2.
UART0 Receive input.
UART0 Transmit output. Also used as receive input in half duplex communication.
UART1 Receive input.
UART1 Transmit output. Also used as receive input in half duplex communication.
USART0 clock input / output.
USART0 chip select input / output.
USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output (MISO).
USART0 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input (MOSI).
USART1 clock input / output.
USART1 chip select input / output.
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output (MISO).
USART1 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input (MOSI).
USART2 clock input / output.
USART2 chip select input / output.
USART2 Asynchronous Receive.
USART2 Synchronous mode Master Input / Slave Output (MISO).
silabs.com | Building a more connected world.
Rev. 2.30 | 407
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
US2_TX
PC2 PB3
USART2 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART2 Synchronous mode Master Output / Slave Input (MOSI).
USB_DM
PF10
USB D- pin.
USB_DMPU
PD2
USB D- Pullup control.
USB_DP
PF11
USB D+ pin.
USB_ID
PF12
USB ID pin. Used in OTG mode.
USB_VBUS
USB_V BUS
USB 5 V VBUS input.
USB_VBUSEN PF5
USB 5 V VBUS enable.
USB_VREGI
USB_V REGI
USB Input to internal 3.3 V regulator
USB_VREGO
USB_V REGO
USB Decoupling for internal 3.3 V USB regulator and regulator output
5.21.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG990 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.63. GPIO Pinout
Port
Port A Port B Port C Port D Port E Port F
Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 15 14 13 12 11 10 PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 -- -- -- -- PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 -- -- -- PF12 PF11 PF10 PF9 PF8 PF7 PF6 PF5 -- -- PF2 PF1 PF0
5.21.4 Opamp Pinout Overview
The specific opamp terminals available in EFM32LG990 is shown in the following figure.
PC4
+ OUT0ALT
PC5
OPA0 -
OUT0
PD4
+
PD3
OPA2 -
OUT2
PD6
+ OUT1ALT
PD7
OPA1 -
OUT1
PB11 PB12 PC0 PC1 PC2 PC3
PD0 PD1 PD5
Figure 5.42. Opamp Pinout
silabs.com | Building a more connected world.
Rev. 2.30 | 408
5.22 EFM32LG995 (BGA120)
EFM32LG Data Sheet
Pin Definitions
5.22.1 Pinout
The EFM32LG995 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module in question.
Figure 5.43. EFM32LG995 Pinout (top view, not to scale) Table 5.64. Device Pinout
BGA120 Pin# and Name
Pin # Pin Name
A1
PE15
A2
PE14
A3
PE12
Analog LCD_SEG11 LCD_SEG10
LCD_SEG8
Pin Alternate Functionality / Description
EBI EBI_AD07 #0/1/2 EBI_AD06 #0/1/2
EBI_AD04 #0/1/2
Timers TIM3_CC1 #0 TIM3_CC0 #0
TIM1_CC2 #1
Communication
LEU0_RX #2
LEU0_TX #2
US0_RX #3 US0_CLK #0 I2C0_SDA #6
Other
CMU_CLK1 #2 LES_ALTEX6 #0
silabs.com | Building a more connected world.
Rev. 2.30 | 409
EFM32LG Data Sheet
Pin Definitions
BGA120 Pin# and Name
Pin # Pin Name
A4
PE9
A5
PD11
A6
PD9
A7
PF7
A8
PF5
A9
PF4
Analog LCD_SEG5 LCD_SEG30 LCD_SEG28 LCD_SEG25 LCD_SEG3 LCD_SEG2
Pin Alternate Functionality / Description
EBI EBI_AD01 #0/1/2 EBI_CS2 #0/1/2 EBI_CS0 #0/1/2 EBI_BL1 #0/1/2
EBI_REn #0/2 EBI_WEn #0/2
Timers PCNT2_S1IN #1
Communication
TIM0_CC1 #2 TIM0_CDTI2 #2/5 TIM0_CDTI1 #2/5
U0_RX #0 USB_VBUSEN #0
A10
PF2
LCD_SEG0
EBI_ARDY #0/1/2
TIM0_CC2 #5
LEU0_TX #4
A11 USB_VREGI Input to internal 3.3V USB regulator
A12 USB_VREGO Output and decoupling for internal 3.3V USB regulator
A13
PF11
B1
PA15
LCD_SEG12
EBI_AD08 #0/1/2
TIM3_CC2 #0
B2
PE13
LCD_SEG9
EBI_AD05 #0/1/2
U1_RX #1 USB_DP
US0_TX #3 US0_CS #0 I2C0_SCL #6
B3
PE11
LCD_SEG7
EBI_AD03 #0/1/2
TIM1_CC1 #1
US0_RX #0
B4
PE8
B5
PD12
B6
PD10
B7
PF8
B8
PF6
LCD_SEG4 LCD_SEG31 LCD_SEG29 LCD_SEG26 LCD_SEG24
EBI_AD00 #0/1/2 EBI_CS3 #0/1/2 EBI_CS1 #0/1/2
EBI_WEn #1 EBI_BL0 #0/1/2
PCNT2_S0IN #1
TIM0_CC2 #2 TIM0_CC0 #2
U0_TX #0
B9
PF3
LCD_SEG1
EBI_ALE #0
TIM0_CDTI0 #2/5
B10
PF1
B11
PF12
B12 USB_VBUS USB 5.0 V VBUS input.
B13
PF10
TIM0_CC1 #5 LETIM0_OUT1 #2
US1_CS #2 LEU0_RX #3 I2C0_SCL #5
USB_ID
U1_TX #1 USB_DM
C1
PA1
LCD_SEG14
EBI_AD10 #0/1/2 TIM0_CC1 #0/1
I2C0_SCL #0
C2
PA0
LCD_SEG13
EBI_AD09 #0/1/2 TIM0_CC0 #0/1/4
LEU0_RX #4 I2C0_SDA #0
C3
PE10
LCD_SEG6
EBI_AD02 #0/1/2
TIM1_CC0 #1
US0_TX #0
C4
PD13
C5
VSS
Ground.
C6
IOVDD_0 Digital IO power supply 0.
C7
PF9
LCD_SEG27
EBI_REn #1
Other
PRS_CH2 #1 PRS_CH1 #1 ACMP1_O #0 DBG_SWO #0 GPIO_EM4WU4
LES_ALTEX7 #0 ACMP0_O #0
GPIO_EM4WU5 LES_ALTEX5 #0
BOOT_RX PRS_CH3 #1
ETM_TCLK #1
PRS_CH0 #1 ETM_TD3 #1 DBG_SWDIO
#0/1/2/3 GPIO_EM4WU3
CMU_CLK1 #0 PRS_CH1 #0 PRS_CH0 #0 GPIO_EM4WU0
BOOT_TX ETM_TD1 #1
ETM_TD0 #1
silabs.com | Building a more connected world.
Rev. 2.30 | 410
EFM32LG Data Sheet
Pin Definitions
BGA120 Pin# and Name
Pin # Pin Name
C8
VSS
C9
IOVDD_1
C10
PF0
C11
PE4
C12
PC14
C13
PC15
D1
PA3
D2
PA2
D3
PB15
D11
PE5
D12
PC12
D13
PC13
E1
PA6
E2
PA5
E3
PA4
E11
PE6
E12
PC10
E13
PC11
F1
PB0
F2
PB1
F3
PB2
F11
PE7
F12
PC8
F13
PC9
Pin Alternate Functionality / Description
Analog
EBI
Ground.
Digital IO power supply 1.
LCD_COM0
ACMP1_CH6 DAC0_OUT1ALT
#2/ OPAMP_OUT1ALT
ACMP1_CH7 DAC0_OUT1ALT
#3/ OPAMP_OUT1ALT
EBI_A11 #0/1/2
Timers
Communication
TIM0_CC0 #5 LETIM0_OUT0 #2
US1_CLK #2 LEU0_TX #3 I2C0_SDA #5
US0_CS #1
TIM0_CDTI1 #1/3 TIM1_CC1 #0
PCNT0_S1IN #0
US0_CS #3 U0_TX #3
TIM0_CDTI2 #1/3 TIM1_CC2 #0
US0_CLK #3 U0_RX #3
LCD_SEG16
EBI_AD12 #0/1/2 TIM0_CDTI0 #0
U0_TX #2
LCD_SEG15
EBI_AD11 #0/1/2 TIM0_CC2 #0/1
LCD_COM1
ACMP1_CH4 DAC0_OUT1ALT
#0/ OPAMP_OUT1ALT
ACMP1_CH5 DAC0_OUT1ALT
#1/ OPAMP_OUT1ALT
EBI_A12 #0/1/2
TIM0_CDTI0 #1/3 TIM1_CC0 #0 TIM1_CC2 #4
PCNT0_S0IN #0
LCD_SEG19
EBI_AD15 #0/1/2
LCD_SEG18
EBI_AD14 #0/1/2 TIM0_CDTI2 #0
LCD_SEG17
LCD_COM2 ACMP1_CH2 ACMP1_CH3 LCD_SEG32 LCD_SEG33 LCD_SEG34 LCD_COM3 ACMP1_CH0
ACMP1_CH1
EBI_AD13 #0/1/2
EBI_A13 #0/1/2 EBI_A10 #1/2 EBI_ALE #1/2 EBI_A16 #0/1/2 EBI_A17 #0/1/2 EBI_A18 #0/1/2 EBI_A14 #0/1/2 EBI_A15 #0/1/2
EBI_A09 #1/2
TIM0_CDTI1 #0
TIM2_CC2 #2
TIM1_CC0 #2 TIM1_CC1 #2 TIM1_CC2 #2
TIM2_CC0 #2 TIM2_CC1 #2
US0_CLK #1 U1_TX #0
U1_RX #0
LEU1_RX #1 LEU1_TX #1
U0_RX #2 US0_RX #1 US0_RX #2 US0_TX #2
US0_TX #1 US0_CS #2 US0_CLK #2
Other
DBG_SWCLK #0/1/2/3
LES_CH14 #0
LES_CH15 #0 DBG_SWO #1 LES_ALTEX2 #0 ETM_TD1 #3 CMU_CLK0 #0 ETM_TD0 #3 ETM_TD2 #1
CMU_CLK0 #1 LES_CH12 #0
LES_CH13 #0
ETM_TCLK #3 GPIO_EM4WU1 LES_ALTEX4 #0
ETM_TD3 #3 LES_ALTEX3 #0
ETM_TD2 #3
LES_CH10 #0 LES_CH11 #0
LES_CH8 #0 LES_CH9 #0 GPIO_EM4WU2
silabs.com | Building a more connected world.
Rev. 2.30 | 411
EFM32LG Data Sheet
Pin Definitions
BGA120 Pin# and Name
Pin # Pin Name
G1
PB3
G2
PB4
G3
IOVDD_2
G11
PE0
G12
PE1
G13
PE3
H1
PB5
H2
PB6
H3
VSS
H11 VDD_DREG
H12
PE2
H13
PC7
J1
PD14
J2
PD15
J3
VSS
J11
IOVDD_3
J12
PC6
J13 DECOUPLE
K1
PC0
K2
PC1
K3
IOVDD_4
K11
VSS
K12
VSS
K13
PD8
L1
PC2
Pin Alternate Functionality / Description
Analog
EBI
Timers
Communication
Other
LCD_SEG20/ LCD_COM4
EBI_A19 #0/1/2
PCNT1_S0IN #1
US2_TX #1
LCD_SEG21/ LCD_COM5
EBI_A20 #0/1/2
PCNT1_S1IN #1
US2_RX #1
Digital IO power supply 2.
EBI_A07 #0/1/2
TIM3_CC0 #1 PCNT0_S0IN #1
U0_TX #1 I2C1_SDA #2
EBI_A08 #0/1/2
TIM3_CC1 #1 PCNT0_S1IN #1
U0_RX #1 I2C1_SCL #2
BU_STAT
EBI_A10 #0
U1_RX #3
ACMP1_O #1
LCD_SEG22/ LCD_COM6
EBI_A21 #0/1/2
US2_CLK #1
LCD_SEG23/ LCD_COM7
EBI_A22 #0/1/2
US2_CS #1
Ground.
Power supply for on-chip voltage regulator.
BU_VOUT
EBI_A09 #0
TIM3_CC2 #1
U1_TX #3
ACMP0_O #1
ACMP0_CH7
EBI_A06 #0/1/2
LEU1_RX #0 I2C0_SCL #2
LES_CH7 #0 ETM_TD0 #2
I2C0_SDA #3
I2C0_SCL #3
Ground.
Digital IO power supply 3.
ACMP0_CH6
EBI_A05 #0/1/2
LEU1_TX #0 I2C0_SDA #2
LES_CH6 #0 ETM_TCLK #2
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin.
ACMP0_CH0 DAC0_OUT0ALT
#0/ OPAMP_OUT0ALT
EBI_A23 #0/1/2
TIM0_CC1 #4 PCNT0_S0IN #2
US0_TX #5 US1_TX #0 I2C0_SDA #4
LES_CH0 #0 PRS_CH2 #0
ACMP0_CH1 DAC0_OUT0ALT
#1/ OPAMP_OUT0ALT
EBI_A24 #0/1/2
TIM0_CC2 #4 PCNT0_S1IN #2
US0_RX #5 US1_RX #0 I2C0_SCL #4
LES_CH1 #0 PRS_CH3 #0
Digital IO power supply 4.
Ground.
Ground.
BU_VIN
CMU_CLK1 #1
ACMP0_CH2 DAC0_OUT0ALT
#2/ OPAMP_OUT0ALT
EBI_A25 #0/1/2
TIM0_CDTI0 #4
US2_TX #0
LES_CH2 #0
silabs.com | Building a more connected world.
Rev. 2.30 | 412
EFM32LG Data Sheet
Pin Definitions
BGA120 Pin# and Name
Pin # Pin Name
L2
PC3
L3
PA7
L4
IOVDD_5
L5
VSS
L6
VSS
L7
IOVDD_6
L8
PB9
L9
PB10
L10
PD0
L11
PD1
L12
PD4
L13
PD7
M1
PB7
M2
PC4
M3
PA8
M4
PA10
M5
PA13
M6
PA14
M7
RESETn
M8
AVSS_1
M9
AVDD_2
M10
AVDD_1
M11
AVSS_0
M12
PD3
Pin Alternate Functionality / Description
Analog
EBI
Timers
Communication
Other
ACMP0_CH3 DAC0_OUT0ALT
#3/ OPAMP_OUT0ALT
EBI_NANDREn #0/1/2
TIM0_CDTI1 #4
US2_RX #0
LES_CH3 #0
LCD_SEG35
EBI_CSTFT #0/1/2
Digital IO power supply 5.
Ground.
Ground.
Digital IO power supply 6.
EBI_A03 #0/1/2
U1_TX #2
EBI_A04 #0/1/2
U1_RX #2
ADC0_CH0 DAC0_OUT0ALT
#4/ OPAMP_OUT0ALT OPAMP_OUT2 #1
PCNT2_S0IN #0
US1_TX #1
ADC0_CH1 DAC0_OUT1ALT
#4/ OPAMP_OUT1ALT
TIM0_CC0 #3 PCNT2_S1IN #0
US1_RX #1
DBG_SWO #2
ADC0_CH4 OPAMP_P2
LEU0_TX #0
ETM_TD2 #0/2
ADC0_CH7 / DAC0_N1 / OPAMP_N1
TIM1_CC1 #4 LETIM0_OUT1 #0 PCNT0_S1IN #3
US1_TX #2 I2C0_SCL #1
CMU_CLK0 #2 LES_ALTEX1 #0
ACMP1_O #2 ETM_TCLK #0
LFXTAL_P
TIM1_CC0 #3
US0_TX #4 US1_CLK #0
ACMP0_CH4 / DAC0_P0 / OPAMP_P0
EBI_A26 #0/1/2
TIM0_CDTI2 #4 LETIM0_OUT0 #3 PCNT1_S0IN #0
US2_CLK #0 I2C1_SDA #0
LES_CH4 #0
LCD_SEG36
EBI_DCLK #0/1/2
TIM2_CC0 #0
LCD_SEG38
EBI_VSNC #0/1/2
TIM2_CC2 #0
LCD_BCAP_N
EBI_A01 #0/1/2
TIM2_CC1 #1
LCD_BEXT
EBI_A02 #0/1/2
TIM2_CC2 #1
Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released.
Analog ground 1.
Analog power supply 2.
Analog power supply 1.
Analog ground 0.
ADC0_CH3 OPAMP_N2
TIM0_CC2 #3
US1_CS #1
ETM_TD1 #0/2
silabs.com | Building a more connected world.
Rev. 2.30 | 413
EFM32LG Data Sheet
Pin Definitions
BGA120 Pin# and Name
Pin # Pin Name
M13
PD6
N1
PB8
N2
PC5
N3
PA9
N4
PA11
N5
PA12
N6
PB11
N7
PB12
N8
AVSS_2
N9
PB13
N10
PB14
N11
AVDD_0
N12
PD2
N13
PD5
Pin Alternate Functionality / Description
Analog ADC0_CH6 / DAC0_P1 / OPAMP_P1
LFXTAL_N
ACMP0_CH5 / DAC0_N0 / OPAMP_N0
LCD_SEG37
LCD_SEG39
LCD_BCAP_P
DAC0_OUT0 / OPAMP_OUT0
DAC0_OUT1 / OPAMP_OUT1
Analog ground 2.
HFXTAL_P
EBI
Timers
TIM1_CC0 #4 LETIM0_OUT0 #0 PCNT0_S0IN #3
TIM1_CC1 #3
EBI_NANDWEn #0/1/2
LETIM0_OUT1 #3 PCNT1_S1IN #0
EBI_DTEN #0/1/2 EBI_HSNC #0/1/2
EBI_A00 #0/1/2
TIM2_CC1 #0
TIM2_CC0 #1 TIM1_CC2 #3 LE-
TIM0_OUT0 #1
LETIM0_OUT1 #1
HFXTAL_N
Analog power supply 0.
ADC0_CH2
EBI_A27 #0/1/2
ADC0_CH5 OPAMP_OUT2 #0
TIM0_CC1 #3
Communication US1_RX #2 I2C0_SDA #1 US0_RX #4 US1_CS #0 US2_CS #0 I2C1_SCL #0
I2C1_SDA #1
I2C1_SCL #1
US0_CLK #4/5 LEU0_TX #1 US0_CS #4/5 LEU0_RX #1
USB_DMPU #0 US1_CLK #1 LEU0_RX #0
Other LES_ALTEX0 #0
ACMP0_O #2 ETM_TD0 #0 LES_CH5 #0
DBG_SWO #3 ETM_TD3 #0/2
silabs.com | Building a more connected world.
Rev. 2.30 | 414
EFM32LG Data Sheet
Pin Definitions
5.22.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0.
Alternate Functionality ACMP0_CH0 ACMP0_CH1 ACMP0_CH2 ACMP0_CH3 ACMP0_CH4 ACMP0_CH5 ACMP0_CH6 ACMP0_CH7 ACMP0_O ACMP1_CH0 ACMP1_CH1 ACMP1_CH2 ACMP1_CH3 ACMP1_CH4 ACMP1_CH5 ACMP1_CH6 ACMP1_CH7 ACMP1_O ADC0_CH0
ADC0_CH1
ADC0_CH2
ADC0_CH3
ADC0_CH4
ADC0_CH5
ADC0_CH6
Table 5.65. Alternate Functionality Overview
LOCATION
0
1
2
3
4
5
6
Description
PC0
Analog comparator ACMP0, channel 0.
PC1
Analog comparator ACMP0, channel 1.
PC2
Analog comparator ACMP0, channel 2.
PC3
Analog comparator ACMP0, channel 3.
PC4
Analog comparator ACMP0, channel 4.
PC5
Analog comparator ACMP0, channel 5.
PC6
Analog comparator ACMP0, channel 6.
PC7
Analog comparator ACMP0, channel 7.
PE13 PE2 PD6
Analog comparator ACMP0, digital output.
PC8
Analog comparator ACMP1, channel 0.
PC9
Analog comparator ACMP1, channel 1.
PC10
Analog comparator ACMP1, channel 2.
PC11
Analog comparator ACMP1, channel 3.
PC12
Analog comparator ACMP1, channel 4.
PC13
Analog comparator ACMP1, channel 5.
PC14
Analog comparator ACMP1, channel 6.
PC15
Analog comparator ACMP1, channel 7.
PF2 PE3 PD7
Analog comparator ACMP1, digital output.
PD0
Analog to digital converter ADC0, input channel number 0.
PD1
Analog to digital converter ADC0, input channel number 1.
PD2
Analog to digital converter ADC0, input channel number 2.
PD3
Analog to digital converter ADC0, input channel number 3.
PD4
Analog to digital converter ADC0, input channel number 4.
PD5
Analog to digital converter ADC0, input channel number 5.
PD6
Analog to digital converter ADC0, input channel number 6.
silabs.com | Building a more connected world.
Rev. 2.30 | 415
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
ADC0_CH7
PD7
Analog to digital converter ADC0, input channel number 7.
BOOT_RX
PE11
Bootloader RX.
BOOT_TX
PE10
Bootloader TX.
BU_STAT
PE3
Backup Power Domain status, whether or not the system is in backup mode
BU_VIN
PD8
Battery input for Backup Power Domain
BU_VOUT
PE2
Power output for Backup Power Domain
CMU_CLK0
PA2 PC12 PD7
Clock Management Unit, clock output number 0.
CMU_CLK1
PA1 PD8 PE12
Clock Management Unit, clock output number 1.
DAC0_OUT0 / OPAMP_OUT0
PB11
Digital to Analog Converter DAC0_OUT0 /OPAMP output channel number 0.
DAC0_OUT0ALT / OPAMP_OUT0ALT
PC0
PC1
PC2
PC3
PD0
Digital to Analog Converter DAC0_OUT0ALT / OPAMP alternative output for channel 0.
DAC0_OUT1 / OPAMP_OUT1
PB12
Digital to Analog Converter DAC0_OUT1 / OPAMP output channel number 1.
DAC0_OUT1ALT / OPAMP_OUT1ALT
PC12
PC13
PC14
PC15
PD1
Digital to Analog Converter DAC0_OUT1ALT / OPAMP alternative output for channel 1.
DBG_SWCLK
PF0 PF0 PF0 PF0
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, and has a built-in pull down.
DBG_SWDIO
PF1 PF1 PF1 PF1
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and has a built-in pull up.
DBG_SWO
PF2 PC15 PD1 PD2
Debug-interface Serial Wire viewer Output.
Note that this function is not enabled after reset, and must be enabled by software to be used.
EBI_A00
PA12 PA12 PA12
External Bus Interface (EBI) address output pin 00.
EBI_A01
PA13 PA13 PA13
External Bus Interface (EBI) address output pin 01.
EBI_A02
PA14 PA14 PA14
External Bus Interface (EBI) address output pin 02.
EBI_A03
PB9 PB9 PB9
External Bus Interface (EBI) address output pin 03.
EBI_A04
PB10 PB10 PB10
External Bus Interface (EBI) address output pin 04.
EBI_A05
PC6 PC6 PC6
External Bus Interface (EBI) address output pin 05.
EBI_A06
PC7 PC7 PC7
External Bus Interface (EBI) address output pin 06.
EBI_A07
PE0 PE0 PE0
External Bus Interface (EBI) address output pin 07.
EBI_A08
PE1 PE1 PE1
External Bus Interface (EBI) address output pin 08.
EBI_A09
PE2 PC9 PC9
External Bus Interface (EBI) address output pin 09.
EBI_A10
PE3 PC10 PC10
External Bus Interface (EBI) address output pin 10.
EBI_A11
PE4 PE4 PE4
External Bus Interface (EBI) address output pin 11.
EBI_A12
PE5 PE5 PE5
External Bus Interface (EBI) address output pin 12.
silabs.com | Building a more connected world.
Rev. 2.30 | 416
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
EBI_A13
PE6 PE6 PE6
External Bus Interface (EBI) address output pin 13.
EBI_A14
PE7 PE7 PE7
External Bus Interface (EBI) address output pin 14.
EBI_A15
PC8 PC8 PC8
External Bus Interface (EBI) address output pin 15.
EBI_A16
PB0 PB0 PB0
External Bus Interface (EBI) address output pin 16.
EBI_A17
PB1 PB1 PB1
External Bus Interface (EBI) address output pin 17.
EBI_A18
PB2 PB2 PB2
External Bus Interface (EBI) address output pin 18.
EBI_A19
PB3 PB3 PB3
External Bus Interface (EBI) address output pin 19.
EBI_A20
PB4 PB4 PB4
External Bus Interface (EBI) address output pin 20.
EBI_A21
PB5 PB5 PB5
External Bus Interface (EBI) address output pin 21.
EBI_A22
PB6 PB6 PB6
External Bus Interface (EBI) address output pin 22.
EBI_A23
PC0 PC0 PC0
External Bus Interface (EBI) address output pin 23.
EBI_A24
PC1 PC1 PC1
External Bus Interface (EBI) address output pin 24.
EBI_A25
PC2 PC2 PC2
External Bus Interface (EBI) address output pin 25.
EBI_A26
PC4 PC4 PC4
External Bus Interface (EBI) address output pin 26.
EBI_A27
PD2 PD2 PD2
External Bus Interface (EBI) address output pin 27.
EBI_AD00
PE8 PE8 PE8
External Bus Interface (EBI) address and data input / output pin 00.
EBI_AD01
PE9 PE9 PE9
External Bus Interface (EBI) address and data input / output pin 01.
EBI_AD02
PE10 PE10 PE10
External Bus Interface (EBI) address and data input / output pin 02.
EBI_AD03
PE11 PE11 PE11
External Bus Interface (EBI) address and data input / output pin 03.
EBI_AD04
PE12 PE12 PE12
External Bus Interface (EBI) address and data input / output pin 04.
EBI_AD05
PE13 PE13 PE13
External Bus Interface (EBI) address and data input / output pin 05.
EBI_AD06
PE14 PE14 PE14
External Bus Interface (EBI) address and data input / output pin 06.
EBI_AD07
PE15 PE15 PE15
External Bus Interface (EBI) address and data input / output pin 07.
EBI_AD08
PA15 PA15 PA15
External Bus Interface (EBI) address and data input / output pin 08.
EBI_AD09
PA0 PA0 PA0
External Bus Interface (EBI) address and data input / output pin 09.
EBI_AD10
PA1 PA1 PA1
External Bus Interface (EBI) address and data input / output pin 10.
EBI_AD11
PA2 PA2 PA2
External Bus Interface (EBI) address and data input / output pin 11.
EBI_AD12
PA3 PA3 PA3
External Bus Interface (EBI) address and data input / output pin 12.
silabs.com | Building a more connected world.
Rev. 2.30 | 417
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
EBI_AD13
PA4 PA4 PA4
External Bus Interface (EBI) address and data input / output pin 13.
EBI_AD14
PA5 PA5 PA5
External Bus Interface (EBI) address and data input / output pin 14.
EBI_AD15
PA6 PA6 PA6
External Bus Interface (EBI) address and data input / output pin 15.
EBI_ALE
PF3 PC11 PC11
External Bus Interface (EBI) Address Latch Enable output.
EBI_ARDY
PF2 PF2 PF2
External Bus Interface (EBI) Hardware Ready Control input.
EBI_BL0
PF6 PF6 PF6
External Bus Interface (EBI) Byte Lane/Enable pin 0.
EBI_BL1
PF7 PF7 PF7
External Bus Interface (EBI) Byte Lane/Enable pin 1.
EBI_CS0
PD9 PD9 PD9
External Bus Interface (EBI) Chip Select output 0.
EBI_CS1
PD10 PD10 PD10
External Bus Interface (EBI) Chip Select output 1.
EBI_CS2
PD11 PD11 PD11
External Bus Interface (EBI) Chip Select output 2.
EBI_CS3
PD12 PD12 PD12
External Bus Interface (EBI) Chip Select output 3.
EBI_CSTFT
PA7 PA7 PA7
External Bus Interface (EBI) Chip Select output TFT.
EBI_DCLK
PA8 PA8 PA8
External Bus Interface (EBI) TFT Dot Clock pin.
EBI_DTEN
PA9 PA9 PA9
External Bus Interface (EBI) TFT Data Enable pin.
EBI_HSNC
PA11 PA11 PA11
External Bus Interface (EBI) TFT Horizontal Synchronization pin.
EBI_NANDREn
PC3 PC3 PC3
External Bus Interface (EBI) NAND Read Enable output.
EBI_NANDWEn
PC5 PC5 PC5
External Bus Interface (EBI) NAND Write Enable output.
EBI_REn
PF5 PF9 PF5
External Bus Interface (EBI) Read Enable output.
EBI_VSNC
PA10 PA10 PA10
External Bus Interface (EBI) TFT Vertical Synchronization pin.
EBI_WEn
PF4 PF8 PF4
External Bus Interface (EBI) Write Enable output.
ETM_TCLK
PD7 PF8 PC6 PA6
Embedded Trace Module ETM clock .
ETM_TD0
PD6 PF9 PC7 PA2
Embedded Trace Module ETM data 0.
ETM_TD1
PD3 PD13 PD3 PA3
Embedded Trace Module ETM data 1.
ETM_TD2
PD4 PB15 PD4 PA4
Embedded Trace Module ETM data 2.
ETM_TD3
PD5 PF3 PD5 PA5
Embedded Trace Module ETM data 3.
GPIO_EM4WU0 PA0
Pin can be used to wake the system up from EM4
GPIO_EM4WU1 PA6
Pin can be used to wake the system up from EM4
GPIO_EM4WU2 PC9
Pin can be used to wake the system up from EM4
GPIO_EM4WU3 PF1
Pin can be used to wake the system up from EM4
silabs.com | Building a more connected world.
Rev. 2.30 | 418
Alternate Functionality GPIO_EM4WU4 GPIO_EM4WU5 HFXTAL_N HFXTAL_P I2C0_SCL I2C0_SDA I2C1_SCL I2C1_SDA
LCD_BCAP_N
LCD_BCAP_P
LCD_BEXT
LCD_COM0 LCD_COM1 LCD_COM2 LCD_COM3 LCD_SEG0 LCD_SEG1 LCD_SEG2 LCD_SEG3 LCD_SEG4 LCD_SEG5 LCD_SEG6
EFM32LG Data Sheet
Pin Definitions
LOCATION
0
1
2
3
4
5
6
Description
PF2
Pin can be used to wake the system up from EM4
PE13
Pin can be used to wake the system up from EM4
PB14
High Frequency Crystal negative pin. Also used as external optional clock input pin.
PB13
High Frequency Crystal positive pin.
PA1 PD7 PC7 PD15 PC1 PF1 PE13 I2C0 Serial Clock Line input / output.
PA0 PD6 PC6 PD14 PC0 PF0 PE12 I2C0 Serial Data input / output.
PC5 PB12 PE1
I2C1 Serial Clock Line input / output.
PC4 PB11 PE0
I2C1 Serial Data input / output.
PA13
LCD voltage booster (optional), boost capacitor, negative pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P.
PA12
LCD voltage booster (optional), boost capacitor, positive pin. If using the LCD voltage booster, connect a 22 nF capacitor between LCD_BCAP_N and LCD_BCAP_P.
LCD voltage booster (optional), boost output. If using the LCD voltage booster, connect a 1 uF capacitor between this pin and VSS.
PA14
An external LCD voltage may also be applied to this pin if the booster is not enabled.
If AVDD is used directly as the LCD supply voltage, this pin may be left unconnected or used as a GPIO.
PE4
LCD driver common line number 0.
PE5
LCD driver common line number 1.
PE6
LCD driver common line number 2.
PE7
LCD driver common line number 3.
PF2
LCD segment line 0. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
PF3
LCD segment line 1. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
PF4
LCD segment line 2. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
PF5
LCD segment line 3. Segments 0, 1, 2 and 3 are controlled by SEGEN0.
PE8
LCD segment line 4. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
PE9
LCD segment line 5. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
PE10
LCD segment line 6. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
silabs.com | Building a more connected world.
Rev. 2.30 | 419
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
LCD_SEG7
PE11
LCD segment line 7. Segments 4, 5, 6 and 7 are controlled by SEGEN1.
LCD_SEG8
PE12
LCD segment line 8. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG9
PE13
LCD segment line 9. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG10
PE14
LCD segment line 10. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG11
PE15
LCD segment line 11. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG12
PA15
LCD segment line 12. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG13
PA0
LCD segment line 13. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG14
PA1
LCD segment line 14. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG15
PA2
LCD segment line 15. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG16
PA3
LCD segment line 16. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG17
PA4
LCD segment line 17. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG18
PA5
LCD segment line 18. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG19
PA6
LCD segment line 19. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG20/ LCD_COM4
PB3
LCD segment line 20. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 4
LCD_SEG21/ LCD_COM5
PB4
LCD segment line 21. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 5
LCD_SEG22/ LCD_COM6
PB5
LCD segment line 22. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 6
LCD_SEG23/ LCD_COM7
PB6
LCD segment line 23. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM line 7
LCD_SEG24
PF6
LCD segment line 24. Segments 24, 25, 26 and 27 are controlled by SEGEN6.
LCD_SEG25
PF7
LCD segment line 25. Segments 24, 25, 26 and 27 are controlled by SEGEN6.
LCD_SEG26
PF8
LCD segment line 26. Segments 24, 25, 26 and 27 are controlled by SEGEN6.
LCD_SEG27
PF9
LCD segment line 27. Segments 24, 25, 26 and 27 are controlled by SEGEN6.
silabs.com | Building a more connected world.
Rev. 2.30 | 420
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
LCD_SEG28
PD9
LCD segment line 28. Segments 28, 29, 30 and 31 are controlled by SEGEN7.
LCD_SEG29
PD10
LCD segment line 29. Segments 28, 29, 30 and 31 are controlled by SEGEN7.
LCD_SEG30
PD11
LCD segment line 30. Segments 28, 29, 30 and 31 are controlled by SEGEN7.
LCD_SEG31
PD12
LCD segment line 31. Segments 28, 29, 30 and 31 are controlled by SEGEN7.
LCD_SEG32
PB0
LCD segment line 32. Segments 32, 33, 34 and 35 are controlled by SEGEN8.
LCD_SEG33
PB1
LCD segment line 33. Segments 32, 33, 34 and 35 are controlled by SEGEN8.
LCD_SEG34
PB2
LCD segment line 34. Segments 32, 33, 34 and 35 are controlled by SEGEN8.
LCD_SEG35
PA7
LCD segment line 35. Segments 32, 33, 34 and 35 are controlled by SEGEN8.
LCD_SEG36
PA8
LCD segment line 36. Segments 36, 37, 38 and 39 are controlled by SEGEN9.
LCD_SEG37
PA9
LCD segment line 37. Segments 36, 37, 38 and 39 are controlled by SEGEN9.
LCD_SEG38
PA10
LCD segment line 38. Segments 36, 37, 38 and 39 are controlled by SEGEN9.
LCD_SEG39
PA11
LCD segment line 39. Segments 36, 37, 38 and 39 are controlled by SEGEN9.
LES_ALTEX0
PD6
LESENSE alternate exite output 0.
LES_ALTEX1
PD7
LESENSE alternate exite output 1.
LES_ALTEX2
PA3
LESENSE alternate exite output 2.
LES_ALTEX3
PA4
LESENSE alternate exite output 3.
LES_ALTEX4
PA5
LESENSE alternate exite output 4.
LES_ALTEX5
PE11
LESENSE alternate exite output 5.
LES_ALTEX6
PE12
LESENSE alternate exite output 6.
LES_ALTEX7
PE13
LESENSE alternate exite output 7.
LES_CH0
PC0
LESENSE channel 0.
LES_CH1
PC1
LESENSE channel 1.
LES_CH2
PC2
LESENSE channel 2.
LES_CH3
PC3
LESENSE channel 3.
LES_CH4
PC4
LESENSE channel 4.
LES_CH5
PC5
LESENSE channel 5.
LES_CH6
PC6
LESENSE channel 6.
LES_CH7
PC7
LESENSE channel 7.
LES_CH8
PC8
LESENSE channel 8.
silabs.com | Building a more connected world.
Rev. 2.30 | 421
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
LES_CH9
PC9
LESENSE channel 9.
LES_CH10
PC10
LESENSE channel 10.
LES_CH11
PC11
LESENSE channel 11.
LES_CH12
PC12
LESENSE channel 12.
LES_CH13
PC13
LESENSE channel 13.
LES_CH14
PC14
LESENSE channel 14.
LES_CH15
PC15
LESENSE channel 15.
LETIM0_OUT0
PD6 PB11 PF0 PC4
Low Energy Timer LETIM0, output channel 0.
LETIM0_OUT1
PD7 PB12 PF1 PC5
Low Energy Timer LETIM0, output channel 1.
LEU0_RX
PD5 PB14 PE15 PF1 PA0
LEUART0 Receive input.
LEU0_TX
PD4 PB13 PE14 PF0 PF2
LEUART0 Transmit output. Also used as receive input in half duplex communication.
LEU1_RX
PC7 PA6
LEUART1 Receive input.
LEU1_TX
PC6 PA5
LEUART1 Transmit output. Also used as receive input in half duplex communication.
LFXTAL_N
PB8
Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an optional external clock input pin.
LFXTAL_P
PB7
Low Frequency Crystal (typically 32.768 kHz) positive pin.
OPAMP_N0 / DAC0_N0
PC5
Operational Amplifier 0 external negative input.
OPAMP_N1 / DAC0_N1
PD7
Operational Amplifier 1 external negative input.
OPAMP_N2
PD3
Operational Amplifier 2 external negative input.
OPAMP_OUT2
PD5 PD0
Operational Amplifier 2 output.
OPAMP_P0 / DAC0_P0
PC4
Operational Amplifier 0 external positive input.
OPAMP_P1 / DAC0_P1
PD6
Operational Amplifier 1 external positive input.
OPAMP_P2
PD4
Operational Amplifier 2 external positive input.
PCNT0_S0IN
PC13 PE0 PC0 PD6
Pulse Counter PCNT0 input number 0.
PCNT0_S1IN
PC14 PE1 PC1 PD7
Pulse Counter PCNT0 input number 1.
PCNT1_S0IN
PC4 PB3
Pulse Counter PCNT1 input number 0.
PCNT1_S1IN
PC5 PB4
Pulse Counter PCNT1 input number 1.
PCNT2_S0IN
PD0 PE8
Pulse Counter PCNT2 input number 0.
PCNT2_S1IN
PD1 PE9
Pulse Counter PCNT2 input number 1.
PRS_CH0
PA0 PF3
Peripheral Reflex System PRS, channel 0.
PRS_CH1
PA1 PF4
Peripheral Reflex System PRS, channel 1.
PRS_CH2
PC0 PF5
Peripheral Reflex System PRS, channel 2.
silabs.com | Building a more connected world.
Rev. 2.30 | 422
Alternate Functionality PRS_CH3 TIM0_CC0 TIM0_CC1 TIM0_CC2 TIM0_CDTI0
TIM0_CDTI1
TIM0_CDTI2 TIM1_CC0 TIM1_CC1 TIM1_CC2 TIM2_CC0 TIM2_CC1 TIM2_CC2 TIM3_CC0 TIM3_CC1 TIM3_CC2 U0_RX U0_TX U1_RX U1_TX US0_CLK US0_CS
US0_RX
US0_TX
US1_CLK US1_CS
US1_RX
LOCATION
0
1
2
3
4
5
PC1 PE8
PA0 PA0 PF6 PD1 PA0 PF0
PA1 PA1 PF7 PD2 PC0 PF1
PA2 PA2 PF8 PD3 PC1 PF2
PA3 PC13 PF3 PC13 PC2 PF3
PA4 PC14 PF4 PC14 PC3 PF4
PA5 PC15 PF5 PC15 PC4 PF5
PC13 PE10 PB0 PB7 PD6 PC14 PE11 PB1 PB8 PD7 PC15 PE12 PB2 PB11 PC13 PA8 PA12 PC8 PA9 PA13 PC9 PA10 PA14 PC10 PE14 PE0 PE15 PE1 PA15 PE2 PF7 PE1 PA4 PC15
PF6 PE0 PA3 PC14
PC13 PF11 PB10 PE3
PC12 PF10 PB9 PE2
PE12 PE5 PC9 PC15 PB13 PB13 PE13 PE4 PC8 PC14 PB14 PB14
PE11 PE6 PC10 PE12 PB8 PC1
PE10 PE7 PC11 PE13 PB7 PC0
PB7 PD2 PF0 PB8 PD3 PF1 PC1 PD1 PD6
EFM32LG Data Sheet
Pin Definitions
6
Description
Peripheral Reflex System PRS, channel 3.
Timer 0 Capture Compare input / output channel 0.
Timer 0 Capture Compare input / output channel 1.
Timer 0 Capture Compare input / output channel 2.
Timer 0 Complimentary Deat Time Insertion channel 0.
Timer 0 Complimentary Deat Time Insertion channel 1.
Timer 0 Complimentary Deat Time Insertion channel 2.
Timer 1 Capture Compare input / output channel 0.
Timer 1 Capture Compare input / output channel 1.
Timer 1 Capture Compare input / output channel 2.
Timer 2 Capture Compare input / output channel 0.
Timer 2 Capture Compare input / output channel 1.
Timer 2 Capture Compare input / output channel 2.
Timer 3 Capture Compare input / output channel 0.
Timer 3 Capture Compare input / output channel 1.
Timer 3 Capture Compare input / output channel 2.
UART0 Receive input.
UART0 Transmit output. Also used as receive input in half duplex communication.
UART1 Receive input.
UART1 Transmit output. Also used as receive input in half duplex communication.
USART0 clock input / output.
USART0 chip select input / output.
USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output (MISO).
USART0 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input (MOSI).
USART1 clock input / output.
USART1 chip select input / output.
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output (MISO).
silabs.com | Building a more connected world.
Rev. 2.30 | 423
EFM32LG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
US1_TX
PC0 PD0 PD7
USART1 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input (MOSI).
US2_CLK
PC4 PB5
USART2 clock input / output.
US2_CS
PC5 PB6
USART2 chip select input / output.
US2_RX
PC3 PB4
USART2 Asynchronous Receive.
USART2 Synchronous mode Master Input / Slave Output (MISO).
US2_TX
PC2 PB3
USART2 Asynchronous Transmit.Also used as receive input in half duplex communication.
USART2 Synchronous mode Master Output / Slave Input (MOSI).
USB_DM
PF10
USB D- pin.
USB_DMPU
PD2
USB D- Pullup control.
USB_DP
PF11
USB D+ pin.
USB_ID
PF12
USB ID pin. Used in OTG mode.
USB_VBUS
USB_ VBUS
USB 5 V VBUS input.
USB_VBUSEN
PF5
USB 5 V VBUS enable.
USB_VREGI
USB_ VREGI
USB Input to internal 3.3 V regulator
USB_VREGO
USB_ VREGO
USB Decoupling for internal 3.3 V USB regulator and regulator output
5.22.3 GPIO Pinout Overview The specific GPIO pins available in EFM32LG995 are shown in the following table. Each GPIO port is organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.66. GPIO Pinout
Port
Port A Port B Port C Port D Port E Port F
Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0 15 14 13 12 11 10 PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 -- -- -- PF12 PF11 PF10 PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0
silabs.com | Building a more connected world.
Rev. 2.30 | 424
5.22.4 Opamp Pinout Overview
The specific opamp terminals available in EFM32LG995 is shown in the following figure.
PC4
+ OUT0ALT
PC5
OPA0 -
OUT0
PD4
+
PD3
OPA2 -
OUT2
PD6
+ OUT1ALT
PD7
OPA1 -
OUT1
PB11 PB12 PC0 PC1 PC2 PC3 PC12 PC13 PC14 PC15 PD0 PD1 PD5
Figure 5.44. Opamp Pinout
EFM32LG Data Sheet
Pin Definitions
silabs.com | Building a more connected world.
Rev. 2.30 | 425
6. BGA112 Package Specifications
6.1 BGA112 Package Dimensions
EFM32LG Data Sheet
BGA112 Package Specifications
Rev: 97SPP01315A_X03_06Jun11
TOP VIEW
BOTTOM VIEW
SIDE VIEW
Figure 6.1. BGA112
Note: 1. The dimensions in parenthesis are reference. 2. Datum 'C' and seating plane are defined by the crown of the solder balls. 3. All dimensions are in millimeters.
silabs.com | Building a more connected world.
Rev. 2.30 | 426
6.2 BGA112 PCB Layout
b
a e
EFM32LG Data Sheet
BGA112 Package Specifications
d Figure 6.2. BGA112 PCB Land Pattern Table 6.1. BGA112 PCB Land Pattern Dimensions (Dimensions in mm)
Symbol a b d e
b
Dim. (mm) 0.35 0.80 8.00 8.00
a e
d Figure 6.3. BGA112 PCB Solder Mask Table 6.2. BGA112 PCB Solder Mask Dimensions (Dimensions in mm)
Symbol a b d e
Dim. (mm) 0.48 0.80 8.00 8.00
silabs.com | Building a more connected world.
Rev. 2.30 | 427
b
a e
EFM32LG Data Sheet
BGA112 Package Specifications
d Figure 6.4. BGA112 PCB Stencil Design Table 6.3. BGA112 PCB Stencil Design Dimensions (Dimensions in mm)
Symbol
a
b
d
e
Note: 1. The drawings are not to scale. 2. All dimensions are in millimeters. 3. All drawings are subject to change without notice. 4. The PCB Land Pattern drawing is in compliance with IPC-7351B. 5. Stencil thickness 0.125 mm. 6. For detailed pin-positioning, see Pin Definitions.
Dim. (mm) 0.33 0.80 8.00 8.00
silabs.com | Building a more connected world.
Rev. 2.30 | 428
6.3 BGA112 Package Marking In the illustration below package fields and position are shown.
EFM32LG Data Sheet
BGA112 Package Specifications
Figure 6.5. Example Chip Marking (Top View)
silabs.com | Building a more connected world.
Rev. 2.30 | 429
7. BGA120 Package Specifications
7.1 BGA120 Package Dimensions
EFM32LG Data Sheet
BGA120 Package Specifications
Rev: 97SPP01321A_XO1_06APR2011
Figure 7.1. BGA120
Note: 1. The dimensions in parenthesis are reference. 2. Datum "C" and seating plane are defined by the crown of the soldier balls. 3. All dimensions are in millimeters.
silabs.com | Building a more connected world.
Rev. 2.30 | 430
7.2 BGA120 PCB Layout
b
a e
EFM32LG Data Sheet
BGA120 Package Specifications
d Figure 7.2. BGA120 PCB Land Pattern Table 7.1. BGA120 PCB Land Pattern Dimensions (Dimensions in mm)
Symbol a b d e
b
Dim. (mm) 0.25 0.50 6.00 6.00
a e
d Figure 7.3. BGA120 PCB Solder Mask Table 7.2. BGA120 PCB Solder Mask Dimensions (Dimensions in mm)
Symbol a b d e
Dim. (mm) 0.35 0.50 6.00 6.00
silabs.com | Building a more connected world.
Rev. 2.30 | 431
b
a e
EFM32LG Data Sheet
BGA120 Package Specifications
d Figure 7.4. BGA120 PCB Stencil Design Table 7.3. BGA120 PCB Stencil Design Dimensions (Dimensions in mm)
Symbol
a
b
d
e
Note: 1. The drawings are not to scale. 2. All dimensions are in millimeters. 3. All drawings are subject to change without notice. 4. The PCB Land Pattern drawing is in compliance with IPC-7351B. 5. Stencil thickness 0.125 mm. 6. For detailed pin-positioning, see Pin Definitions.
Dim. (mm) 0.25 0.50 6.00 6.00
silabs.com | Building a more connected world.
Rev. 2.30 | 432
7.3 BGA120 Package Marking In the illustration below package fields and position are shown.
EFM32LG Data Sheet
BGA120 Package Specifications
Figure 7.5. Example Chip Marking (Top View)
silabs.com | Building a more connected world.
Rev. 2.30 | 433
8. CSP81 Package Specifications
8.1 CSP81 Package Dimensions
EFM32LG Data Sheet
CSP81 Package Specifications
Figure 8.1. CSP81
Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. Primary datum "C" and seating plane are defined by the spherical crowns of the solder balls. 4. Dimension "b" is measured at the maximum solder bump diameter, parallel to primary datum "C". 5. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
silabs.com | Building a more connected world.
Rev. 2.30 | 434
Symbol A A1 A2 b S D E e D1 E1 n
aaa bbb ccc ddd eee
Table 8.1. CSP81 (Dimensions in mm)
Min 0.491 0.17 0.036 0.23 0.3075
Nom 0.55 -- -- -- 0.31 4.355 BSC. 4.275 BSC. 0.40 BSC. 3.20 BSC. 3.20 BSC. 81 0.05 0.10 0.075 0.15 0.05
EFM32LG Data Sheet
CSP81 Package Specifications
Max 0.609 0.23 0.044 0.29 0.3125
silabs.com | Building a more connected world.
Rev. 2.30 | 435
8.2 CSP81 PCB Layout
EFM32LG Data Sheet
CSP81 Package Specifications
Figure 8.2. CSP81 PCB Land Pattern Table 8.2. CSP81 PCB Land Pattern Dimensions (Dimensions in mm)
Symbol X C1 C2 E1 E2
Dim. (mm) 0.20 3.20 3.20 0.40 0.40
silabs.com | Building a more connected world.
Rev. 2.30 | 436
EFM32LG Data Sheet
CSP81 Package Specifications
Figure 8.3. CSP81 PCB Solder Mask Table 8.3. CSP81 PCB Solder Mask Dimensions (Dimensions in mm)
Symbol X C1 C2 E1 E2
Dim. (mm) 0.26 3.20 3.20 0.40 0.40
silabs.com | Building a more connected world.
Rev. 2.30 | 437
EFM32LG Data Sheet
CSP81 Package Specifications
Figure 8.4. CSP81 PCB Stencil Design Table 8.4. CSP81 PCB Stencil Design Dimensions (Dimensions in mm)
Symbol
X
C1
C2
E1
E2
Note: 1. The drawings are not to scale. 2. All dimensions are in millimeters. 3. All drawings are subject to change without notice. 4. The PCB Land Pattern drawing is in compliance with IPC-7351B. 5. Stencil thickness 0.125 mm. 6. For detailed pin-positioning, see Pin Definitions.
Dim. (mm) 0.20 3.20 3.20 0.40 0.40
silabs.com | Building a more connected world.
Rev. 2.30 | 438
8.3 CSP81 Package Marking In the illustration below package fields and position are shown.
EFM32LG Data Sheet
CSP81 Package Specifications
Figure 8.5. Example Chip Marking (Top View)
8.4 CSP81 Environmental WLCSP devices can be handled and soldered using industry standard surface mount assembly techniques. However, because WLCSP devices are essentially a piece of silicon and are not encapsulated in plastic, they are susceptible to mechanical damage and may be sensitive to light. When WLCSPs must be used in an environment exposed to light, it may be necessary to cover the top and sides withan opaque material.
silabs.com | Building a more connected world.
Rev. 2.30 | 439
9. LQFP100 Package Specifications
9.1 LQFP100 Package Dimensions
EFM32LG Data Sheet
LQFP100 Package Specifications
Rev: 98A0100QP043_03MAY2007
Figure 9.1. LQFP100
Note: 1. Datum 'T', 'U' and 'Z' to be determined at datum plane 'H' 2. Datum 'D' and 'E' to be determined at seating plane datum 'Y'. 3. Dimension 'D1' and 'E1' do not include mold protrusions. Allowable protrusion is 0.25 per side. Dimensions 'D1' and 'E1' do include mold mismatch and are determined at datum plane datum 'H'. 4. Dimension 'b' does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum 'b' dimension by more than 0.08 mm. Dambar can not be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm. 5. Exact shape of each corner is optional.
silabs.com | Building a more connected world.
Rev. 2.30 | 440
total thickness stand off
mold thickness lead width (plating)
lead width L/F thickness (plating)
lead thickness x y x
body size y
lead pitch
footprint
package edge tolerance lead edge tolerance coplanarity lead offset mold flatness
EFM32LG Data Sheet
LQFP100 Package Specifications
Table 9.1. LQFP100 (Dimensions in mm)
SYMBOL
MIN
A
--
A1
0.05
A2
1.35
b
0.17
b1
0.17
c
0.09
c1
0.09
D
E
D1
E1
e
L
0.45
L1
0º
1
0º
2
11º
3
11º
R1
0.08
R1
0.08
S
0.2
aaa
bbb
ccc
ddd
eee
NOM -- -- 1.4 0.2 -- -- --
16 BSC 16 BSC 14 BSC 14 BSC 0.5 BSC
0.6 1 REF
3.5º -- 12º 12º -- -- -- 0.2 0.2 0.08 0.08 0.05
MAX 1.6 0.15 1.45 0.27 0.23 0.2 0.16
0.75
7º -- 13º 13º -- 0.2 --
silabs.com | Building a more connected world.
Rev. 2.30 | 441
9.2 LQFP100 PCB Layout
a
p8 p1
b
EFM32LG Data Sheet
LQFP100 Package Specifications
p7 p6
e c
p2
p5
p3
p4
d
Figure 9.2. LQFP100 PCB Land Pattern
Table 9.2. LQFP100 PCB Land Pattern Dimensions (Dimensions in mm)
Symbol a b c d e
Dim. (mm) 1.45 0.30 0.50 15.40 15.40
Symbol P1 P2 P3 P4 P5
a
Pin Number 1 25 26 50 51
Symbol P6 P7 P8
Pin Number 75 76 100
b
e c
d Figure 9.3. LQFP100 PCB Solder Mask Table 9.3. LQFP100 PCB Solder Mask Dimensions (Dimensions in mm)
Symbol a b c d e
silabs.com | Building a more connected world.
Dim. (mm) 1.57 0.42 0.50 15.40 15.40
Rev. 2.30 | 442
a b c
EFM32LG Data Sheet
LQFP100 Package Specifications
e
d Figure 9.4. LQFP100 PCB Stencil Design Table 9.4. LQFP100 PCB Stencil Design Dimensions (Dimensions in mm)
Symbol
a
b
c
d
e
Note: 1. The drawings are not to scale. 2. All dimensions are in millimeters. 3. All drawings are subject to change without notice. 4. The PCB Land Pattern drawing is in compliance with IPC-7351B. 5. Stencil thickness 0.125 mm. 6. For detailed pin-positioning, see Pin Definitions.
Dim. (mm) 1.35 0.20 0.50 15.40 15.40
silabs.com | Building a more connected world.
Rev. 2.30 | 443
9.3 LQFP100 Package Marking In the illustration below package fields and position are shown.
EFM32LG Data Sheet
LQFP100 Package Specifications
Figure 9.5. Example Chip Marking (Top View)
silabs.com | Building a more connected world.
Rev. 2.30 | 444
10. QFN64 Package Specifications
10.1 QFN64 Package Dimensions
EFM32LG Data Sheet
QFN64 Package Specifications
49 48
64 1
33 32
16 17
m m
Rev: 98SPP64048A_XO1_08MAR2011
Figure 10.1. QFN64
Note: 1. Dimensioning & tolerancing confirm to ASME Y14.5M-1994. 2. All dimensions are in millimeters. Angles are in degrees. 3. Dimension 'b' applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from the terminal tip. Dimension L1 represents terminal full back from package edge up to 0.1 mm is acceptable. 4. Coplanarity applies to the exposed heat slug as well as the terminal. 5. Radius on terminal is optional.
silabs.com | Building a more connected world.
Rev. 2.30 | 445
Symbol A A1 A3 b D E D2 E2 e L L1
aaa bbb ccc ddd eee
Table 10.1. QFN64 (Dimensions in mm)
Min
Nom
0.80
0.85
0.00
--
0.203 REF
0.20
0.25
9.00 BSC
9.00 BSC
7.10
7.20
7.10
7.20
0.50 BSC
0.40
0.45
0.00
--
0.10
0.10
0.10
0.05
0.08
EFM32LG Data Sheet
QFN64 Package Specifications
Max 0.90 0.05
0.30
7.30 7.30
0.50 0.10
silabs.com | Building a more connected world.
Rev. 2.30 | 446
10.2 QFN64 PCB Layout a
EFM32LG Data Sheet
QFN64 Package Specifications
Symbol a b c d e f g
p8
b
p1
p7 p6
p9
ge
c
p2 p3
p5 p4
f d
Figure 10.2. QFN64 PCB Land Pattern
Table 10.2. QFN64 PCB Land Pattern Dimensions (Dimensions in mm)
Dim. (mm) 0.85 0.30 0.50 8.90 8.90 7.20 7.20
Symbol P1 P2 P3 P4 P5 P6 P7
a
Pin Number 1 16 17 32 33 48 49
Symbol P8 P9
Pin Number 64 0
b
ge c
f d Figure 10.3. QFN64 PCB Solder Mask
Table 10.3. QFN64 PCB Solder Mask Dimensions (Dimensions in mm)
Symbol a b c
Dim. (mm) 0.97 0.42 0.50
silabs.com | Building a more connected world.
Symbol e f g
Dim. (mm) 8.90 7.32 7.32
Rev. 2.30 | 447
Symbol d
Dim. (mm) 8.90 a
Symbol -
b
x
y
e
c
z
EFM32LG Data Sheet
QFN64 Package Specifications
Dim. (mm) -
d Figure 10.4. QFN64 PCB Stencil Design Table 10.4. QFN64 PCB Stencil Design Dimensions (Dimensions in mm)
Symbol a b c d
Dim. (mm) 0.75 0.22 0.50 8.90
Note: 1. The drawings are not to scale. 2. All dimensions are in millimeters. 3. All drawings are subject to change without notice. 4. The PCB Land Pattern drawing is in compliance with IPC-7351B. 5. Stencil thickness 0.125 mm. 6. For detailed pin-positioning, see Pin Definitions.
Symbol e x y z
Dim. (mm) 8.90 2.70 2.70 0.80
silabs.com | Building a more connected world.
Rev. 2.30 | 448
10.3 QFN64 Package Marking In the illustration below package fields and position are shown.
EFM32LG Data Sheet
QFN64 Package Specifications
Figure 10.5. Example Chip Marking (Top View)
silabs.com | Building a more connected world.
Rev. 2.30 | 449
11. TQFP64 Package Specifications
11.1 TQFP64 Package Dimensions
EFM32LG Data Sheet
TQFP64 Package Specifications
Rev: 98SPP64023A_XO1_17MAR2011
F
CL
Figure 11.1. TQFP64
Note: 1. All dimensions & tolerancing confirm to ASME Y14.5M-1994. 2. The top package body size may be smaller than the bottom package body size. 3. Datum 'A,B', and 'B' to be determined at datum plane 'H'. 4. To be determined at seating place 'C'. 5. Dimension 'D1' and 'E1' do not include mold protrusions. Allowable protrusion is 0.25mm per side. 'D1' and 'E1' are maximum plastic body size dimension including mold mismatch. Dimension 'D1' and 'E1' shall be determined at datum plane 'H'. 6. Detail of Pin 1 indicatifier are option all but must be located within the zone indicated. 7. Dimension 'b' does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum 'b' dimension by more than 0.08 mm. Dambar can not be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm. 8. Exact shape of each corner is optional. 9. These dimension apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
10. All dimensions are in millimeters.
silabs.com | Building a more connected world.
Rev. 2.30 | 450
DIM
MIN
A
--
A1
0.05
A2
0.95
b
0.17
b1
0.17
c
0.09
C1
0.09
D
D1
e
E
E1
L
0.45
Table 11.1. QFP64 (Dimensions in mm)
NOM
MAX
DIM
MIN
1.10
1.20
L1
--
0.15
R1
0.08
1.00
1.05
R2
0.08
0.22
0.27
S
0.20
0.20
0.23
0°
--
0.20
1
0°
--
0.16
2
11°
12.0 BSC
3
11°
10.0 BSC
0.50 BSC
12.0 BSC
10.0 BSC
0.60
0.75
EFM32LG Data Sheet
TQFP64 Package Specifications
NOM -- -- -- -- 3.5° -- 12° 12°
MAX
-- 0.20 -- 7° -- 13° 13°
silabs.com | Building a more connected world.
Rev. 2.30 | 451
11.2 TQFP64 PCB Layout
a
p8 p1
b
EFM32LG Data Sheet
TQFP64 Package Specifications
p7 p6
e c
p2
p5
p3
p4
d
Figure 11.2. TQFP64 PCB Land Pattern
Table 11.2. TQFP64 PCB Land Pattern Dimensions (Dimensions in mm)
Symbol a b c d e
Dim. (mm) 1.60 0.30 0.50 11.50 11.50
Symbol P1 P2 P3 P4 P5
a
Pin Number 1 16 17 32 33
Symbol P6 P7 P8
Pin Number 48 49 64
b
e c
d Figure 11.3. TQFP64 PCB Solder Mask Table 11.3. TQFP64 PCB Solder Mask Dimensions (Dimensions in mm)
Symbol a b c d e
silabs.com | Building a more connected world.
Dim. (mm) 1.72 0.42 0.50 11.50 11.50
Rev. 2.30 | 452
a b c
EFM32LG Data Sheet
TQFP64 Package Specifications
e
d Figure 11.4. TQFP64 PCB Stencil Design Table 11.4. TQFP64 PCB Stencil Design Dimensions (Dimensions in mm)
Symbol
a
b
c
d
e
Note: 1. The drawings are not to scale. 2. All dimensions are in millimeters. 3. All drawings are subject to change without notice. 4. The PCB Land Pattern drawing is in compliance with IPC-7351B. 5. Stencil thickness 0.125 mm. 6. For detailed pin-positioning, see Pin Definitions.
Dim. (mm) 1.50 0.20 0.50 11.50 11.50
silabs.com | Building a more connected world.
Rev. 2.30 | 453
11.3 TQFP64 Package Marking In the illustration below package fields and position are shown.
EFM32LG Data Sheet
TQFP64 Package Specifications
Figure 11.5. Example Chip Marking (Top View)
silabs.com | Building a more connected world.
Rev. 2.30 | 454
12. Wafer Specifications
EFM32LG Data Sheet
Wafer Specifications
12.1 Bonding Instructions
All pads should be bonded out, with the exception of the pads labeled "NC" and listed as "Do not connect" in Padout. Gold bond wires are recommended for these devices.
All three voltage regulator output decouple pads (DEC_0, DEC_1, DEC_2) must be bonded out and electrically connected on the PCB. In the packaged devices, these three pads are all bonded to a single DECOUPLE pin.
If the USB feature of EFM32LG900 will be used, all of the USB pads must be bonded out, and · both USB_VREGO_0 and USB_VREGO_1 must be bonded out and electrically connected on the PCB. In the packaged devices,
these two pads are both bonded to a single USB_VREGO pin. · both USB_VREGI_0 and USB_VREGI_1 must be bonded out and electrically connected on the PCB. In the packaged devices,
these two pads are both bonded to a single USB_VREGI pin.
12.2 Wafer Description
Table 12.1. Wafer and Die Information
Parameter
Value
Device Family
EFM32LG (Leopard Gecko)
Wafer Diameter
8 in
Die Dimensions (Outer edge of seal ring)
Contact sales for information
Wafer Thickness (No backgrind)
725 µm ±15 µm (28.54 mil ±1 mil)
Wafer Identification
Notch
Scribe Street Width
80 µm × 160 µm
Die Per Wafer1
Contact sales for information
Passivation
Standard
Wafer Packaging Detail
Wafer Jar
Bond Pad Dimensions
65 µm (parallel to die edge) × 66 µm
Bond Pad Pitch Minimum
76 µm
Maximum Processing Temperature
250 °C
Electronic Die Map Format
.txt
Note: 1. This is the Expected Known Good Die yielded per wafer and represents the batch order quantity (one wafer).
12.2.1 Environmental
Bare silicon die are susceptible to mechanical damage and may be sensitive to light. When bare die must be used in an environment exposed to light, it may be necessary to cover the top and sides with an opaque material.
Further quality and environmental information, please see: http://www.silabs.com/support/quality/pages/default.aspx.
silabs.com | Building a more connected world.
Rev. 2.30 | 455
EFM32LG Data Sheet
Wafer Specifications
12.3 Wafer Storage Guidelines
It is necessary to conform to appropriate wafer storage practices to avoid product degradation or contamination. · Wafers may be stored for up to 18 months in the original packaging supplied by Silicon Labs. · Wafers must be stored at a temperature of 18 - 24 °C. · Wafers must be stored in a humidity-controlled environment with a relative humidity of <30%. · Wafers should be stored in a clean, dry, inert atmosphere (e.g. nitrogen or clean, dry air).
12.4 Failure Analysis (FA) Guidelines
Certain conditions must be met for Silicon Laboratories to perform Failure Analysis on devices sold in wafer form. · In order to conduct failure analysis on a device in a customer-provided package, Silicon Laboratories must be provided with die as-
sembled in an industry standard package that is pin compatible with existing packages Silicon Laboratories offers for the device. Initial response time for FA requests that meet these requirements will follow the standard FA guidelines for packaged parts. · If retest of the entire wafer is requested, Silicon Laboratories must be provided with the whole wafer. Silicon Laboratories cannot retest any wafers that have been sawed, diced, backgrind or are on tape. Initial response time for FA requests that meet these requirements will be 3 weeks.
silabs.com | Building a more connected world.
Rev. 2.30 | 456
13. Chip Revision, Solder Information, Errata
EFM32LG Data Sheet
Chip Revision, Solder Information, Errata
13.1 Chip Revision The revision of a chip can be determined from the "Revision" field in the package marking.
13.2 Soldering Information The latest IPC/JEDEC J-STD-020 recommendations for Pb-Free reflow soldering should be followed.
13.3 Errata
Please see the errata document for description and resolution of device errata. This document is available in Simplicity Studio and online at: http://www.silabs.com/support/pages/document-library.aspx?p=MCUs--32-bit
silabs.com | Building a more connected world.
Rev. 2.30 | 457
14. Revision History
EFM32LG Data Sheet
Revision History
Revision 2.30
November, 2019 · Updated Ordering Information for the release of revision F devices. · In Flash Electrical Specifications Added word write cycles between erase (WWCFLASH) specification. · In Table 4.15 Analog Digital Converter (ADC) on page 91 Electrical Specifications Updated ADC input ON resistance (RADCIN). · In Alternate Functionality Overview tables, restored DAC0_P0, DAC0_P1, DAC0_N0 and DAC0_N1 alternate functionalities for all
the devices. · Removed PB11 as the 1st alternate location of I2C1_SDA in Alternate Functionality Overview tables for:
· EFM32LG232 · EFM32LG332 · EFM32LG842 · EFM32LG942 · Removed MSL information (Moisture Sensitivity Level). Instead, MSL information can be found in the Qual report that is available on the Silicon Labs website. · Consolidated revision history with new format.
silabs.com | Building a more connected world.
Rev. 2.30 | 458
EFM32LG Data Sheet
Revision History
Revision 2.20
April 2019 · Key Features stop mode current changed to match value specified in 4.5 Current Consumption. · 2. Ordering Information corrected to show that the package for the EFM32LG942 is the TQFP64 and not the BGA120. · Spelling and punctuation errors fixed in 3.1.12 Universal Serial Bus Controller (USB). · Corrected available ACMP0 and ACMP1 channels in the following Configuration Summary sections:
· 3.2.6 EFM32LG330 · 3.2.7 EFM32LG332 · 3.2.9 EFM32LG380 · 3.2.10 EFM32LG390 · 3.2.12 EFM32LG840 · 3.2.13 EFM32LG842 · 3.2.18 EFM32LG940 · 3.2.19 EFM32LG942 · 3.2.20 EFM32LG980 · 3.2.21 EFM32LG990 · GPIO count in Table 3.6 EFM32LG330 Configuration Summary on page 27 increased from 52 to 53. · GPIO count in Table 3.18 EFM32LG940 Configuration Summary on page 51 increased from 52 to 53. · Added TJ parameter to Table 4.1 Absolute Maximum Ratings on page 63. · Added 4.4 Backup Supply Domain specifications to 4. Electrical Characteristics. · Capitalization of figure titles made consistent in 4.5.1 EM1 Current Consumption. · Restored figure title for Figure 4.7 EM1 Current Consumption with all Peripheral Clocks Disabled and HFRCO Running at 1.2 MHz on page 70. · Restored note to 4.5.2 EM2 Current Consumption indicating use of Backup RTC (BURTC). · Updated the following 4.8 Flash specifications and added relevant notes: · Page erase time (tPERASE) · Device erase time (tDERASE) · Added load current (ILOAD_DC) maximum to 4.12 Digital Analog Converter (DAC) specifications. · Updated the load resistance (RLOAD) in 4.13 Operational Amplifier (OPAMP) specifications. · Corrected the following 4.16 EBI parameters: · Minimum tOH_ALEn equation to use ADDRHOLD instead of WRHOLD. · Minimum tH_ARDY equation to include addition of (3 * tHFCORECLK) term. · Title of Figure 4.44 SPI Slave Timing on page 129 corrected to specify slave (not master) timing. · Restored the analog description of USB_VREGI and USB_VREGO as follows: · Pins A11 and A12 in the Table 5.13 Device Pinout on page 179 for EFM32LG295. · Pin s 45 and 46 in the Table 5.13 Device Pinout on page 179 for EFM32LG330. · Pin s 45 and 46 in the Table 5.19 Device Pinout on page 203 for EFM32LG332. · Pins A11 and A12 in the Table 5.64 Device Pinout on page 409 for EFM32LG995. · Pins B1 and C1 in the Table 5.22 Device Pinout on page 213 for EFM32LG360. · Pins 72 and 73 in the Table 5.25 Device Pinout on page 225 for EFM32LG380. · Pins B10 and B11 in the Table 5.28 Device Pinout on page 237 for EFM32LG390. · Pins A11 and A12 in the Table 5.31 Device Pinout on page 251 for EFM32LG395. · Pins A11 and A12 in the Table 5.46 Device Pinout on page 323 for EFM32LG895. · Pins 45 and 46 in the Table 5.52 Device Pinout on page 356 for EFM32LG940. · Pins 45 and 46 in the Table 5.55 Device Pinout on page 366 for EFM32LG942. · Pins 72 and 73 in the Table 5.58 Device Pinout on page 378 for EFM32LG980. · Pins B10 and B11 in the Table 5.61 Device Pinout on page 393 for EFM32LG990. · Pins A11 and A12 in the Table 5.64 Device Pinout on page 409 for EFM32LG995. · Changed pin #8 in Table 5.1 Device Pinout on page 132 from VSS to IOVDD_0 to match Figure 5.1 EFM32LG232 on page 131. · Restored PC1 and PC0 as 4th alternate locations of I2C0_SCL and I2C0_SDA, respectively in 5.2.2 Alternate Functionality Pinout for the EFM32LG232. · Removed USB_DMPU #0 from the Communication column of pin 48 in Table 5.7 Device Pinout on page 152 for the EFM32LG280.
silabs.com | Building a more connected world.
Rev. 2.30 | 459
EFM32LG Data Sheet
Revision History
· Restored PC15 as the 1st alternate location of DBG_SWO in 5.4.2 Alternate Functionality Pinout for the EFM32LG290. · Corrected 5.5.3 GPIO Pinout Overview text to reflect that the information shown is for the EFM32LG295 and not the EFM32LG395. · Restored the signal descriptions of DAC0_OUT1 /OPAMP_OUT1 in 5.6.2 Alternate Functionality Pinout for the EFM32LG330. · Restored the following signals in 5.12.2 Alternate Functionality Pinout for the EFM32LG840:
· GPIO_EM4WU1 · PA6 as 4th location of ETM_CLK · PC13 as the 4th location of TIM1_CC2 · Restored PC13 as the 4th location of TIM1_CC2 in 5.13.2 Alternate Functionality Pinout for the EFM32LG842. · Removed USB_DMPU #0 from the Communication column of pin 48 in Table 5.40 Device Pinout on page 289 for the EFM32LG880. · Restored PF3 as the 0th (primary) location of EBI_ALE in 5.14.2 Alternate Functionality Pinout for the EFM32LG880. · Restored PC15 as the 1st location of DBG_SWO in 5.15.2 Alternate Functionality Pinout for the EFM32LG890. · Restored U1_RX #1 to the Communication column of pin A13 in Table 5.46 Device Pinout on page 323 for the EFM32LG895. · Pad 117 changed from PD15 to PB15 in Table 5.49 Device Padout on page 338 for the EFM32LG900. · Added TIM3_CC2 to 5.19.2 Alternate Functionality Pinout for the EFM32LG940. · Restored moisture sensitivity information to 13.2 Soldering Information. · Corrected symbol b in 10.1 QFN64 Package Dimensions. · Corrected the pin number for symbol P9 in 10.2 QFN64 PCB Layout. · Statements regarding packaging materials have been removed. The most current device quality and environmental information can be found at http://www.silabs.com/support/quality/pages/default.aspx.
Revision 2.10
September 20th, 2017 · In 4.10.5 AUXHFRCO, updated test conditions for oscillation frequency. · In 4.11 Analog Digital Converter (ADC):
· Added footnote for average active current. · Updated conditions for INL and DNL. · Updated parameter description for VREF. · Updated VREF current consumption max for 1.25V and 2.5V reference. · In 4.12 Digital Analog Converter (DAC): · Updated parameter description and test conditions for IDAC. · Updated parameter description for VREF. · Corrected pinout diagram for EFM32LG230 in 5.1.1 Pinout. · Spelling and formatting updates throughout.
silabs.com | Building a more connected world.
Rev. 2.30 | 460
EFM32LG Data Sheet
Revision History
Revision 2.00
April 17th, 2017 · Consolidated all EFM32LG data sheets:
· EFM32LG230 · EFM32LG232 · EFM32LG280 · EFM32LG290 · EFM32LG295 · EFM32LG330 · EFM32LG332 · EFM32LG360 · EFM32LG380 · EFM32LG390 · EFM32LG395 · EFM32LG840 · EFM32LG842 · EFM32LG880 · EFM32LG890 · EFM32LG895 · EFM32LG900 · EFM32LG940 · EFM32LG942 · EFM32LG980 · EFM32LG990 · EFM32LG995 · Added a Feature List section. · 2. Ordering Information Added ordering code decoder. · 3.3 Memory Map Separated the Memory Map into two figures one for core and code space listing and one for peripheral listing. · 4.2 Absolute Maximum Ratings Removed the footnote about storage temperature and added max source/sink current per I/O pin. · Environmental Removed this section. Environmental specifications are available in the qualification report. · 4.5 Current Consumption - Added maximum current specifications for the highest energy mode, IEM0. · 4.9 General Purpose Input Output Reduced maximum input leakage current (IIOLEAK, max). · 4.10.1 LFXO Replaced "energyAware Designer" with "Configurator tool". · 4.10.3 LFRCO Added (min, typ, max) specifications for oscillation frequency over full power supply and full temperature range. Also added typical voltage drift and temperature drift specs. · 4.10.3 LFRCO Updated graphs for calibrated LFRCO Frequency vs. Temperature and Supply Range, and also fixed y-axis unit [kHz]. · 4.10.4 HFRCO Added specifications for oscillation frequency over full power supply and temperature range, added typical voltage drift and temperature drift specs at each frequency band, and removed the duty cycle spec (DCHFRCO). · 4.10.4 HFRCO Updated all HFRCO graphs (various frequency bands). · 4.10.6 ULFRCO Removed the duty cycle spec for AUXHFRCO (DCAUXHFRCO). · 4.11 Analog Digital Converter (ADC) Added the following specs: · Input bias current (IADCBIASIN) added max (source and sink). · Input offset current (IADCOFFSETIN) added max (source and sink). · VREF output voltage (VREF) added min, typ, max. · VREF voltage drift (VREF_VDRIFT) added min, typ, max. · VREF temperature drift (VREF_TDRIFT) added min, typ, max. · VREF current consumption (IVREF) added typ, max, replacing IADCREF. · ADC and DAC VREF matching (VREF_MATCH) added typical.
silabs.com | Building a more connected world.
Rev. 2.30 | 461
EFM32LG Data Sheet
Revision History
· 4.12 Digital Analog Converter (DAC) Updated the footnote for active average current (IDAC), and added the following new VREF specs at each voltage reference: · VREF output voltage (VREF) added min, typ, max. · VREF voltage drift (VREF_VDRIFT) added min, typ, max. · VREF temperature drift (VREF_TDRIFT) added min, typ, max. · VREF current consumption (IVREF) added typ, max. · ADC and DAC VREF matching (VREF_MATCH) added typical.
· 4.13 Operational Amplifier (OPAMP) Removed note specifying that OPAMP specs stem from simulations, and added new specifications for the following: · Active Current (IOPAMP) new specifications at various (new) bias program settings. · Gain Bandwidth Product (GBWOPAMP) new (typ) specifications at new bias program settings and DC bias settings. · Input Offset Voltage (VOFFSET) specified min, typ, max for Op Amps (OPA0-1). · Input Bias Current (IOPAMPBIASIN) new min and max specifications. · Input Offset Current (IOPAMPOFF-SETIN) new min and max specifications. · Slew Rate (SROPAMP) new specifications at new bias program settings. · Updated footnote.
· 4.14 Analog Comparator (ACMP) Added new specifications for the following: · Input Bias Current (IACMPBIASIN) added min and max. · Input Offset Current (IACMPOFFSETIN) added min and max. · Active Current (IACMP) added two new condition settings, and footnote. · Negative Response Time (tRESPONSE_N) added new specifications. · Positive Response Times (tRESPONSE_P) added new specifications. · Offset Voltage (VACMPOFFSET) added specifications at new bias program settings. · ACMP Hysteresis (VACMPHYST) added specifications for negative and positive hysteresis at various bias program settings. · VDD SCALED Input Accuracy (VVDDSCALED) added new specifications (typical).
· 4.15 Voltage Comparator (VCMP) Added the following new specifications: · Negative hysteresis (VVCMPHYST_N), replacing VCMP hysteresis. · Positive hysteresis (VVCMPHYST_P), replacing VCMP hysteresis. · Hysteresis Delta (VVCMPHYST_DELTA). · Negative Response Time (tRESPONSE_N). · Positive Response Time (tRESPONSE_P). · Footnote for active current, IVCMP.
· 4.19 USART SPI Corrected parameter descriptions for tCS_DIS_MI. · 4.20 Digital Peripherals Added (typical) LE Peripheral Interface Clock Current (ILFCLK) specifications with both the LFXO-LFA and
LFXO-LFB clock trees. · Removed MSL information (Moisture Sensitivity Level). Instead, MSL information can be found in the Qual report that is available on
the Silicon Labs website. · New formatting throughout.
silabs.com | Building a more connected world.
Rev. 2.30 | 462
EFM32LG Data Sheet
Revision History
Revision 1.31
December 16th, 2015 · Removed Environmental section from General Operating Conditions. · Added max current consumption numbers for energy modes. · For devices with an ADC, added clarification on conditions for INLADC and DNLADC parameters. · For devices with an EBI, updated EBI ready/wait figure. · Updated memory map. · Removed DCHFRCO and DCAUXHFRCO parameters. · For CSP81 package, updated typical and added min/max values for fHFRCO and fAUXHFRCO. · For devices in CSP81 package with a DAC, updated OPAMP table. · Fixed typos. · Added OPAMP, ADC, and ACMP Input Bias Current and Input Offset Current specifications. · Added lower limit for GPIO Input Leakage Current and updated the upper limit for this specification. · Removed the "by simulation and/or technology characterization" phrase from the Electrical Characteristics Test Conditions section.
Revision 1.30
June 13th, 2014 · This revision applies the following devices:
· EFM32LG230 · EFM32LG232 · EFM32LG280 · EFM32LG290 · EFM32LG295 · EFM32LG330 · EFM32LG332 · EFM32LG380 · EFM32LG390 · EFM32LG395 · EFM32LG840 · EFM32LG842 · EFM32LG880 · EFM32LG890 · EFM32LG895 · EFM32LG940 · EFM32LG942 · EFM32LG980 · EFM32LG990 · EFM32LG995 · Removed "Preliminary" markings. · Updated electrical characteristics and updated/added plots. · Updated orderable part numbers. · Added AUXHFRCO to block diagram and electrical characteristics. · For devices with EBI, added EBI timing chapter.
silabs.com | Building a more connected world.
Rev. 2.30 | 463
Revision 1.21
November 21st, 2013 · This revision applies the following devices:
· EFM32LG230 · EFM32LG232 · EFM32LG280 · EFM32LG290 · EFM32LG295 · EFM32LG330 · EFM32LG332 · EFM32LG380 · EFM32LG390 · EFM32LG395 · EFM32LG840 · EFM32LG842 · EFM32LG880 · EFM32LG890 · EFM32LG895 · EFM32LG940 · EFM32LG942 · EFM32LG980 · EFM32LG990 · EFM32LG995 · Updated figures. · Updated errata-link. · Updated chip marking. · Added link to Environmental and Quality information. · For devices with a DAC, re-added missing DAC-data.
EFM32LG Data Sheet
Revision History
silabs.com | Building a more connected world.
Rev. 2.30 | 464
Revision 1.20
March 16th, 2015 · This revision applies the following devices:
· EFM32LG900 · Corrected pad numbers and the order of the pads in the padout table so that it matches the drawing.
March 16th, 2015 · This revision applies the following devices:
· EFM32LG230 · EFM32LG232 · EFM32LG280 · EFM32LG290 · EFM32LG295 · EFM32LG330 · EFM32LG332 · EFM32LG380 · EFM32LG390 · EFM32LG395 · EFM32LG840 · EFM32LG842 · EFM32LG880 · EFM32LG890 · EFM32LG895 · EFM32LG940 · EFM32LG942 · EFM32LG980 · EFM32LG990 · EFM32LG995 · Added I2C characterization data. · Added SPI characterization data. · Corrected the DAC and OPAMP2 pin sharing information in the Alternate Functionality Pinout section. · Corrected GPIO operating voltage from 1.8 V to 1.85 V. · For devices with USB, added the USB bootloader information. · Corrected the ADC resolution from 12, 10 and 6 bit to 12, 8 and 6 bit. · For QFN64 packages, removed UART mentioned incorrectly in the QFN64 parts. · Updated Environmental information. · Updated trademark, disclaimer and contact information. · Other minor corrections.
EFM32LG Data Sheet
Revision History
silabs.com | Building a more connected world.
Rev. 2.30 | 465
Revision 1.11
November 17th, 2010 · This revision applies the following devices:
· EFM32G200 · EFM32G210 · EFM32G230 · EFM32G280 · EFM32G290 · EFM32G840 · EFM32G880 · EFM32G890 · Corrected maximum DAC clock speed for continuous mode. · Added DAC sample-hold mode voltage drift rate. · Added pulse widths detected by the HFXO glitch detector. · Added power sequencing information to Power Management section.
Revision 1.10
December 12th, 2014 · This revision applies the following devices:
· EFM32LG900 · Added recommendation to use gold bond wire.
June 28th, 2013
· This revision applies the following devices: · EFM32LG230 · EFM32LG232 · EFM32LG280 · EFM32LG290 · EFM32LG295 · EFM32LG330 · EFM32LG332 · EFM32LG380 · EFM32LG390 · EFM32LG395 · EFM32LG840 · EFM32LG842 · EFM32LG880 · EFM32LG890 · EFM32LG895 · EFM32LG940 · EFM32LG942 · EFM32LG980 · EFM32LG990 · EFM32LG995
· Updated power requirements in the Power Management section. · For BGA packages, updated PCB Land Pattern, PCB Solder Mask and PCB Stencil Design figures. · Removed minimum load capacitance figure and table. Added reference to application note. · Other minor corrections.
EFM32LG Data Sheet
Revision History
silabs.com | Building a more connected world.
Rev. 2.30 | 466
EFM32LG Data Sheet
Revision History
Revision 1.00
October 15th, 2014 · This revision applies the following devices:
· EFM32LG360 · EFM32LG900 September 11th, 2012 · This revision applies the following devices: · EFM32LG230 · EFM32LG232 · EFM32LG280 · EFM32LG290 · EFM32LG295 · EFM32LG330 · EFM32LG332 · EFM32LG380 · EFM32LG390 · EFM32LG395 · EFM32LG840 · EFM32LG842 · EFM32LG880 · EFM32LG890 · EFM32LG895 · EFM32LG940 · EFM32LG942 · EFM32LG980 · EFM32LG990 · EFM32LG995
· Updated the HFRCO 1 MHz band typical value to 1.2 MHz. · Updated the HFRCO 7 MHz band typical value to 6.6 MHz. · For BGA112 and BGA120 packages, corrected BGA solder balls material from Sn96.5/Ag3/Cu0.5 to SAC105.
Revision 0.92 May 25th, 2012
· This revision applies the following devices: · EFM32LG290 · EFM32LG295 · EFM32LG390 · EFM32LG395 · EFM32LG890 · EFM32LG895 · EFM32LG990 · EFM32LG995
· Corrected BGA solder balls material description. · Corrected EM3 current consumption in the Electrical Characteristics section.
silabs.com | Building a more connected world.
Rev. 2.30 | 467
Revision 0.90 April 27th, 2012
· This revision applies the following devices: · EFM32LG230 · EFM32LG232 · EFM32LG280 · EFM32LG290 · EFM32LG295 · EFM32LG330 · EFM32LG332 · EFM32LG380 · EFM32LG390 · EFM32LG395 · EFM32LG840 · EFM32LG842 · EFM32LG880 · EFM32LG890 · EFM32LG895 · EFM32LG940 · EFM32LG942 · EFM32LG980 · EFM32LG990 · EFM32LG995
· Initial preliminary release.
EFM32LG Data Sheet
Revision History
silabs.com | Building a more connected world.
Rev. 2.30 | 468
Simplicity Studio
One-click access to MCU and wireless tools, documentation, software, source code libraries & more. Available for Windows, Mac and Linux!
IoT Portfolio www.silabs.com/IoT
SW/HW www.silabs.com/simplicity
Quality www.silabs.com/quality
Support and Community community.silabs.com
Disclaimer Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes without further notice to the product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Without prior notification, Silicon Labs may update product firmware during the manufacturing process for security or reliability reasons. Such changes will not alter the specifications or the performance of the product. Silicon Labs shall have no liability for the consequences of use of the information supplied in this document. This document does not imply or expressly grant any license to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any FDA Class III devices, applications for which FDA premarket approval is required or Life Support Systems without the specific written consent of Silicon Labs. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. Silicon Labs products are not designed or authorized for military applications. Silicon Labs products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons. Silicon Labs disclaims all express and implied warranties and shall not be responsible or liable for any injuries or damages related to use of a Silicon Labs product in such unauthorized applications.
Trademark Information Silicon Laboratories Inc.® , Silicon Laboratories®, Silicon Labs®, SiLabs® and the Silicon Labs logo®, Bluegiga®, Bluegiga Logo®, ClockBuilder®, CMEMS®, DSPLL®, EFM®, EFM32®, EFR, Ember®, Energy Micro, Energy Micro logo and combinations thereof, "the world's most energy friendly microcontrollers", Ember®, EZLink®, EZRadio®, EZRadioPRO®, Gecko®, Gecko OS, Gecko OS Studio, ISOmodem®, Precision32®, ProSLIC®, Simplicity Studio®, SiPHY®, Telegesis, the Telegesis Logo®, USBXpress® , Zentri, the Zentri logo and Zentri DMS, Z-Wave®, and others are trademarks or registered trademarks of Silicon Labs. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. Wi-Fi is a registered trademark of the Wi-Fi Alliance. All other products or brand names mentioned herein are trademarks of their respective holders.
Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 USA
http://www.silabs.com
Antenna House PDF Output Library 6.0.283 (Linux64)